Boot log: asus-cx9400-volteer
- Kernel Errors: 0
- Boot result: FAIL
- Warnings: 0
- Errors: 2
- Kernel Warnings: 0
1 12:40:24.877376 lava-dispatcher, installed at version: 2023.06
2 12:40:24.877623 start: 0 validate
3 12:40:24.877778 Start time: 2023-08-30 12:40:24.877769+00:00 (UTC)
4 12:40:24.877923 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:40:24.878086 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-cros-ec%2F20230623.0%2Famd64%2Frootfs.cpio.gz exists
6 12:40:25.151439 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:40:25.152031 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-4.4.y-st-rc%2Fv4.4-st20-1637-g085b4ca13c9a%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fkernel%2FbzImage exists
8 12:40:25.421363 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:40:25.422058 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-4.4.y-st-rc%2Fv4.4-st20-1637-g085b4ca13c9a%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
10 12:40:29.657083 validate duration: 4.78
12 12:40:29.657427 start: 1 tftp-deploy (timeout 00:10:00) [common]
13 12:40:29.657535 start: 1.1 download-retry (timeout 00:10:00) [common]
14 12:40:29.657632 start: 1.1.1 http-download (timeout 00:10:00) [common]
15 12:40:29.657762 Not decompressing ramdisk as can be used compressed.
16 12:40:29.657859 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-cros-ec/20230623.0/amd64/rootfs.cpio.gz
17 12:40:29.657934 saving as /var/lib/lava/dispatcher/tmp/11383472/tftp-deploy-vcc61456/ramdisk/rootfs.cpio.gz
18 12:40:29.658003 total size: 35760064 (34 MB)
19 12:40:30.182394 progress 0 % (0 MB)
20 12:40:30.199939 progress 5 % (1 MB)
21 12:40:30.218186 progress 10 % (3 MB)
22 12:40:30.231177 progress 15 % (5 MB)
23 12:40:30.241876 progress 20 % (6 MB)
24 12:40:30.252120 progress 25 % (8 MB)
25 12:40:30.262544 progress 30 % (10 MB)
26 12:40:30.272789 progress 35 % (11 MB)
27 12:40:30.283230 progress 40 % (13 MB)
28 12:40:30.293716 progress 45 % (15 MB)
29 12:40:30.303955 progress 50 % (17 MB)
30 12:40:30.314506 progress 55 % (18 MB)
31 12:40:30.324762 progress 60 % (20 MB)
32 12:40:30.335236 progress 65 % (22 MB)
33 12:40:30.345495 progress 70 % (23 MB)
34 12:40:30.356020 progress 75 % (25 MB)
35 12:40:30.366450 progress 80 % (27 MB)
36 12:40:30.376700 progress 85 % (29 MB)
37 12:40:30.387112 progress 90 % (30 MB)
38 12:40:30.397217 progress 95 % (32 MB)
39 12:40:30.407518 progress 100 % (34 MB)
40 12:40:30.407725 34 MB downloaded in 0.75 s (45.49 MB/s)
41 12:40:30.407904 end: 1.1.1 http-download (duration 00:00:01) [common]
43 12:40:30.408184 end: 1.1 download-retry (duration 00:00:01) [common]
44 12:40:30.408283 start: 1.2 download-retry (timeout 00:09:59) [common]
45 12:40:30.408379 start: 1.2.1 http-download (timeout 00:09:59) [common]
46 12:40:30.408518 downloading http://storage.kernelci.org/cip/linux-4.4.y-st-rc/v4.4-st20-1637-g085b4ca13c9a/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/kernel/bzImage
47 12:40:30.408598 saving as /var/lib/lava/dispatcher/tmp/11383472/tftp-deploy-vcc61456/kernel/bzImage
48 12:40:30.408667 total size: 8490896 (8 MB)
49 12:40:30.408737 No compression specified
50 12:40:30.409962 progress 0 % (0 MB)
51 12:40:30.412419 progress 5 % (0 MB)
52 12:40:30.414994 progress 10 % (0 MB)
53 12:40:30.417525 progress 15 % (1 MB)
54 12:40:30.420063 progress 20 % (1 MB)
55 12:40:30.422632 progress 25 % (2 MB)
56 12:40:30.425184 progress 30 % (2 MB)
57 12:40:30.427727 progress 35 % (2 MB)
58 12:40:30.430251 progress 40 % (3 MB)
59 12:40:30.432784 progress 45 % (3 MB)
60 12:40:30.435325 progress 50 % (4 MB)
61 12:40:30.437849 progress 55 % (4 MB)
62 12:40:30.440340 progress 60 % (4 MB)
63 12:40:30.442825 progress 65 % (5 MB)
64 12:40:30.445318 progress 70 % (5 MB)
65 12:40:30.447820 progress 75 % (6 MB)
66 12:40:30.450306 progress 80 % (6 MB)
67 12:40:30.452793 progress 85 % (6 MB)
68 12:40:30.455298 progress 90 % (7 MB)
69 12:40:30.457779 progress 95 % (7 MB)
70 12:40:30.460313 progress 100 % (8 MB)
71 12:40:30.460447 8 MB downloaded in 0.05 s (156.40 MB/s)
72 12:40:30.460609 end: 1.2.1 http-download (duration 00:00:00) [common]
74 12:40:30.460868 end: 1.2 download-retry (duration 00:00:00) [common]
75 12:40:30.460965 start: 1.3 download-retry (timeout 00:09:59) [common]
76 12:40:30.461067 start: 1.3.1 http-download (timeout 00:09:59) [common]
77 12:40:30.461218 downloading http://storage.kernelci.org/cip/linux-4.4.y-st-rc/v4.4-st20-1637-g085b4ca13c9a/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/modules.tar.xz
78 12:40:30.461299 saving as /var/lib/lava/dispatcher/tmp/11383472/tftp-deploy-vcc61456/modules/modules.tar
79 12:40:30.461367 total size: 250888 (0 MB)
80 12:40:30.461435 Using unxz to decompress xz
81 12:40:30.466187 progress 13 % (0 MB)
82 12:40:30.466662 progress 26 % (0 MB)
83 12:40:30.466930 progress 39 % (0 MB)
84 12:40:30.468671 progress 52 % (0 MB)
85 12:40:30.470739 progress 65 % (0 MB)
86 12:40:30.472825 progress 78 % (0 MB)
87 12:40:30.474924 progress 91 % (0 MB)
88 12:40:30.476849 progress 100 % (0 MB)
89 12:40:30.483055 0 MB downloaded in 0.02 s (11.04 MB/s)
90 12:40:30.483314 end: 1.3.1 http-download (duration 00:00:00) [common]
92 12:40:30.483612 end: 1.3 download-retry (duration 00:00:00) [common]
93 12:40:30.483719 start: 1.4 prepare-tftp-overlay (timeout 00:09:59) [common]
94 12:40:30.483829 start: 1.4.1 extract-nfsrootfs (timeout 00:09:59) [common]
95 12:40:30.483923 end: 1.4.1 extract-nfsrootfs (duration 00:00:00) [common]
96 12:40:30.484019 start: 1.4.2 lava-overlay (timeout 00:09:59) [common]
97 12:40:30.484267 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11383472/lava-overlay-lpuxeb6x
98 12:40:30.484420 makedir: /var/lib/lava/dispatcher/tmp/11383472/lava-overlay-lpuxeb6x/lava-11383472/bin
99 12:40:30.484542 makedir: /var/lib/lava/dispatcher/tmp/11383472/lava-overlay-lpuxeb6x/lava-11383472/tests
100 12:40:30.484653 makedir: /var/lib/lava/dispatcher/tmp/11383472/lava-overlay-lpuxeb6x/lava-11383472/results
101 12:40:30.484783 Creating /var/lib/lava/dispatcher/tmp/11383472/lava-overlay-lpuxeb6x/lava-11383472/bin/lava-add-keys
102 12:40:30.484950 Creating /var/lib/lava/dispatcher/tmp/11383472/lava-overlay-lpuxeb6x/lava-11383472/bin/lava-add-sources
103 12:40:30.485101 Creating /var/lib/lava/dispatcher/tmp/11383472/lava-overlay-lpuxeb6x/lava-11383472/bin/lava-background-process-start
104 12:40:30.485250 Creating /var/lib/lava/dispatcher/tmp/11383472/lava-overlay-lpuxeb6x/lava-11383472/bin/lava-background-process-stop
105 12:40:30.485393 Creating /var/lib/lava/dispatcher/tmp/11383472/lava-overlay-lpuxeb6x/lava-11383472/bin/lava-common-functions
106 12:40:30.485539 Creating /var/lib/lava/dispatcher/tmp/11383472/lava-overlay-lpuxeb6x/lava-11383472/bin/lava-echo-ipv4
107 12:40:30.485683 Creating /var/lib/lava/dispatcher/tmp/11383472/lava-overlay-lpuxeb6x/lava-11383472/bin/lava-install-packages
108 12:40:30.485826 Creating /var/lib/lava/dispatcher/tmp/11383472/lava-overlay-lpuxeb6x/lava-11383472/bin/lava-installed-packages
109 12:40:30.485967 Creating /var/lib/lava/dispatcher/tmp/11383472/lava-overlay-lpuxeb6x/lava-11383472/bin/lava-os-build
110 12:40:30.486117 Creating /var/lib/lava/dispatcher/tmp/11383472/lava-overlay-lpuxeb6x/lava-11383472/bin/lava-probe-channel
111 12:40:30.486259 Creating /var/lib/lava/dispatcher/tmp/11383472/lava-overlay-lpuxeb6x/lava-11383472/bin/lava-probe-ip
112 12:40:30.486400 Creating /var/lib/lava/dispatcher/tmp/11383472/lava-overlay-lpuxeb6x/lava-11383472/bin/lava-target-ip
113 12:40:30.486550 Creating /var/lib/lava/dispatcher/tmp/11383472/lava-overlay-lpuxeb6x/lava-11383472/bin/lava-target-mac
114 12:40:30.486692 Creating /var/lib/lava/dispatcher/tmp/11383472/lava-overlay-lpuxeb6x/lava-11383472/bin/lava-target-storage
115 12:40:30.486839 Creating /var/lib/lava/dispatcher/tmp/11383472/lava-overlay-lpuxeb6x/lava-11383472/bin/lava-test-case
116 12:40:30.486980 Creating /var/lib/lava/dispatcher/tmp/11383472/lava-overlay-lpuxeb6x/lava-11383472/bin/lava-test-event
117 12:40:30.487128 Creating /var/lib/lava/dispatcher/tmp/11383472/lava-overlay-lpuxeb6x/lava-11383472/bin/lava-test-feedback
118 12:40:30.487270 Creating /var/lib/lava/dispatcher/tmp/11383472/lava-overlay-lpuxeb6x/lava-11383472/bin/lava-test-raise
119 12:40:30.487415 Creating /var/lib/lava/dispatcher/tmp/11383472/lava-overlay-lpuxeb6x/lava-11383472/bin/lava-test-reference
120 12:40:30.487561 Creating /var/lib/lava/dispatcher/tmp/11383472/lava-overlay-lpuxeb6x/lava-11383472/bin/lava-test-runner
121 12:40:30.487751 Creating /var/lib/lava/dispatcher/tmp/11383472/lava-overlay-lpuxeb6x/lava-11383472/bin/lava-test-set
122 12:40:30.487918 Creating /var/lib/lava/dispatcher/tmp/11383472/lava-overlay-lpuxeb6x/lava-11383472/bin/lava-test-shell
123 12:40:30.488068 Updating /var/lib/lava/dispatcher/tmp/11383472/lava-overlay-lpuxeb6x/lava-11383472/bin/lava-install-packages (oe)
124 12:40:30.488251 Updating /var/lib/lava/dispatcher/tmp/11383472/lava-overlay-lpuxeb6x/lava-11383472/bin/lava-installed-packages (oe)
125 12:40:30.488396 Creating /var/lib/lava/dispatcher/tmp/11383472/lava-overlay-lpuxeb6x/lava-11383472/environment
126 12:40:30.488514 LAVA metadata
127 12:40:30.488598 - LAVA_JOB_ID=11383472
128 12:40:30.488670 - LAVA_DISPATCHER_IP=192.168.201.1
129 12:40:30.488785 start: 1.4.2.1 lava-vland-overlay (timeout 00:09:59) [common]
130 12:40:30.488860 skipped lava-vland-overlay
131 12:40:30.488947 end: 1.4.2.1 lava-vland-overlay (duration 00:00:00) [common]
132 12:40:30.489038 start: 1.4.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
133 12:40:30.489108 skipped lava-multinode-overlay
134 12:40:30.489189 end: 1.4.2.2 lava-multinode-overlay (duration 00:00:00) [common]
135 12:40:30.489278 start: 1.4.2.3 test-definition (timeout 00:09:59) [common]
136 12:40:30.489363 Loading test definitions
137 12:40:30.489470 start: 1.4.2.3.1 inline-repo-action (timeout 00:09:59) [common]
138 12:40:30.489554 Using /lava-11383472 at stage 0
139 12:40:30.489899 uuid=11383472_1.4.2.3.1 testdef=None
140 12:40:30.489998 end: 1.4.2.3.1 inline-repo-action (duration 00:00:00) [common]
141 12:40:30.490098 start: 1.4.2.3.2 test-overlay (timeout 00:09:59) [common]
142 12:40:30.490701 end: 1.4.2.3.2 test-overlay (duration 00:00:00) [common]
144 12:40:30.490949 start: 1.4.2.3.3 test-install-overlay (timeout 00:09:59) [common]
145 12:40:30.491664 end: 1.4.2.3.3 test-install-overlay (duration 00:00:00) [common]
147 12:40:30.491922 start: 1.4.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
148 12:40:30.492608 runner path: /var/lib/lava/dispatcher/tmp/11383472/lava-overlay-lpuxeb6x/lava-11383472/0/tests/0_cros-ec test_uuid 11383472_1.4.2.3.1
149 12:40:30.492785 end: 1.4.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
151 12:40:30.493015 Creating lava-test-runner.conf files
152 12:40:30.493087 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11383472/lava-overlay-lpuxeb6x/lava-11383472/0 for stage 0
153 12:40:30.493188 - 0_cros-ec
154 12:40:30.493298 end: 1.4.2.3 test-definition (duration 00:00:00) [common]
155 12:40:30.493397 start: 1.4.2.4 compress-overlay (timeout 00:09:59) [common]
156 12:40:30.500850 end: 1.4.2.4 compress-overlay (duration 00:00:00) [common]
157 12:40:30.500973 start: 1.4.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
158 12:40:30.501070 end: 1.4.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
159 12:40:30.501166 end: 1.4.2 lava-overlay (duration 00:00:00) [common]
160 12:40:30.501262 start: 1.4.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
161 12:40:31.668616 end: 1.4.3 extract-overlay-ramdisk (duration 00:00:01) [common]
162 12:40:31.669053 start: 1.4.4 extract-modules (timeout 00:09:58) [common]
163 12:40:31.669184 extracting modules file /var/lib/lava/dispatcher/tmp/11383472/tftp-deploy-vcc61456/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11383472/extract-overlay-ramdisk-y1el5n9m/ramdisk
164 12:40:31.685795 end: 1.4.4 extract-modules (duration 00:00:00) [common]
165 12:40:31.685961 start: 1.4.5 apply-overlay-tftp (timeout 00:09:58) [common]
166 12:40:31.686064 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11383472/compress-overlay-6b23pj58/overlay-1.4.2.4.tar.gz to ramdisk
167 12:40:31.686147 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11383472/compress-overlay-6b23pj58/overlay-1.4.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11383472/extract-overlay-ramdisk-y1el5n9m/ramdisk
168 12:40:31.694560 end: 1.4.5 apply-overlay-tftp (duration 00:00:00) [common]
169 12:40:31.694698 start: 1.4.6 configure-preseed-file (timeout 00:09:58) [common]
170 12:40:31.694803 end: 1.4.6 configure-preseed-file (duration 00:00:00) [common]
171 12:40:31.694906 start: 1.4.7 compress-ramdisk (timeout 00:09:58) [common]
172 12:40:31.694994 Building ramdisk /var/lib/lava/dispatcher/tmp/11383472/extract-overlay-ramdisk-y1el5n9m/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11383472/extract-overlay-ramdisk-y1el5n9m/ramdisk
173 12:40:32.246809 >> 184082 blocks
174 12:40:36.218760 rename /var/lib/lava/dispatcher/tmp/11383472/extract-overlay-ramdisk-y1el5n9m/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11383472/tftp-deploy-vcc61456/ramdisk/ramdisk.cpio.gz
175 12:40:36.219259 end: 1.4.7 compress-ramdisk (duration 00:00:05) [common]
176 12:40:36.219404 start: 1.4.8 prepare-kernel (timeout 00:09:53) [common]
177 12:40:36.219518 start: 1.4.8.1 prepare-fit (timeout 00:09:53) [common]
178 12:40:36.219629 No mkimage arch provided, not using FIT.
179 12:40:36.219730 end: 1.4.8.1 prepare-fit (duration 00:00:00) [common]
180 12:40:36.219846 end: 1.4.8 prepare-kernel (duration 00:00:00) [common]
181 12:40:36.219964 end: 1.4 prepare-tftp-overlay (duration 00:00:06) [common]
182 12:40:36.220065 start: 1.5 lxc-create-udev-rule-action (timeout 00:09:53) [common]
183 12:40:36.220154 No LXC device requested
184 12:40:36.220243 end: 1.5 lxc-create-udev-rule-action (duration 00:00:00) [common]
185 12:40:36.220339 start: 1.6 deploy-device-env (timeout 00:09:53) [common]
186 12:40:36.220447 end: 1.6 deploy-device-env (duration 00:00:00) [common]
187 12:40:36.220527 Checking files for TFTP limit of 4294967296 bytes.
188 12:40:36.220975 end: 1 tftp-deploy (duration 00:00:07) [common]
189 12:40:36.221092 start: 2 depthcharge-action (timeout 00:05:00) [common]
190 12:40:36.221194 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
191 12:40:36.221330 substitutions:
192 12:40:36.221405 - {DTB}: None
193 12:40:36.221474 - {INITRD}: 11383472/tftp-deploy-vcc61456/ramdisk/ramdisk.cpio.gz
194 12:40:36.221540 - {KERNEL}: 11383472/tftp-deploy-vcc61456/kernel/bzImage
195 12:40:36.221604 - {LAVA_MAC}: None
196 12:40:36.221666 - {PRESEED_CONFIG}: None
197 12:40:36.221728 - {PRESEED_LOCAL}: None
198 12:40:36.221789 - {RAMDISK}: 11383472/tftp-deploy-vcc61456/ramdisk/ramdisk.cpio.gz
199 12:40:36.221850 - {ROOT_PART}: None
200 12:40:36.221910 - {ROOT}: None
201 12:40:36.221970 - {SERVER_IP}: 192.168.201.1
202 12:40:36.222030 - {TEE}: None
203 12:40:36.222089 Parsed boot commands:
204 12:40:36.222147 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
205 12:40:36.222342 Parsed boot commands: tftpboot 192.168.201.1 11383472/tftp-deploy-vcc61456/kernel/bzImage 11383472/tftp-deploy-vcc61456/kernel/cmdline 11383472/tftp-deploy-vcc61456/ramdisk/ramdisk.cpio.gz
206 12:40:36.222450 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
207 12:40:36.222548 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
208 12:40:36.222652 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
209 12:40:36.222751 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
210 12:40:36.222827 Not connected, no need to disconnect.
211 12:40:36.222913 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
212 12:40:36.223003 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
213 12:40:36.223080 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh asus-cx9400-volteer-cbg-11'
214 12:40:36.227316 Setting prompt string to ['lava-test: # ']
215 12:40:36.227707 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
216 12:40:36.227824 end: 2.2.1 reset-connection (duration 00:00:00) [common]
217 12:40:36.227941 start: 2.2.2 reset-device (timeout 00:05:00) [common]
218 12:40:36.228052 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
219 12:40:36.228271 Calling: 'pduclient' '--daemon=localhost' '--hostname=asus-cx9400-volteer-cbg-11' '--port=1' '--command=reboot'
220 12:40:41.371960 >> Command sent successfully.
221 12:40:41.378293 Returned 0 in 5 seconds
222 12:40:41.479080 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
224 12:40:41.480662 end: 2.2.2 reset-device (duration 00:00:05) [common]
225 12:40:41.481151 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
226 12:40:41.481803 Setting prompt string to 'Starting depthcharge on Voema...'
227 12:40:41.482225 Changing prompt to 'Starting depthcharge on Voema...'
228 12:40:41.482665 depthcharge-start: Wait for prompt Starting depthcharge on Voema... (timeout 00:05:00)
229 12:40:41.483853 [Enter `^Ec?' for help]
230 12:40:43.038049
231 12:40:43.038628
232 12:40:43.048003 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 bootblock starting (log level: 8)...
233 12:40:43.050760 CPU: 11th Gen Intel(R) Core(TM) i7-1160G7 @ 1.20GHz
234 12:40:43.057459 CPU: ID 806c1, Tigerlake B0, ucode: 00000086
235 12:40:43.060809 CPU: AES supported, TXT NOT supported, VT supported
236 12:40:43.068236 MCH: device id 9a12 (rev 01) is Tigerlake-Y-4-2
237 12:40:43.071297 PCH: device id a087 (rev 20) is Tigerlake-Y Premium SKU
238 12:40:43.078339 IGD: device id 9a40 (rev 01) is Tigerlake Y GT2
239 12:40:43.081987 VBOOT: Loading verstage.
240 12:40:43.084941 FMAP: Found "FLASH" version 1.1 at 0x1804000.
241 12:40:43.091415 FMAP: base = 0x0 size = 0x2000000 #areas = 32
242 12:40:43.095086 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
243 12:40:43.104931 CBFS: mcache @0xfef45600 built for 70 files, used 0xfdc of 0x1800 bytes
244 12:40:43.111587 CBFS: Found 'fallback/verstage' @0x165e40 size 0x147ec in mcache @0xfef45984
245 12:40:43.112111
246 12:40:43.112451
247 12:40:43.121698 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 verstage starting (log level: 8)...
248 12:40:43.138611 Probing TPM: . done!
249 12:40:43.141416 TPM ready after 0 ms
250 12:40:43.145250 Connected to device vid:did:rid of 1ae0:0028:00
251 12:40:43.156237 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_A:0.5.171/cr50_v2.94_mp.164-2fb1dd676c
252 12:40:43.163154 Current CR50_BOARD_CFG = 0x80000001, matches desired = 0x00000001
253 12:40:43.166220 Initialized TPM device CR50 revision 0
254 12:40:43.222270 tlcl_send_startup: Startup return code is 0
255 12:40:43.222484 TPM: setup succeeded
256 12:40:43.237882 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
257 12:40:43.251726 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
258 12:40:43.265130 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
259 12:40:43.275411 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
260 12:40:43.278688 Chrome EC: UHEPI supported
261 12:40:43.282203 Phase 1
262 12:40:43.285468 FMAP: area GBB found @ 1805000 (458752 bytes)
263 12:40:43.292430 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
264 12:40:43.301883 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
265 12:40:43.308724 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
266 12:40:43.314998 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
267 12:40:43.318307 Recovery requested (1009000e)
268 12:40:43.322081 TPM: Extending digest for VBOOT: boot mode into PCR 0
269 12:40:43.333444 tlcl_extend: response is 0
270 12:40:43.340071 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
271 12:40:43.349872 tlcl_extend: response is 0
272 12:40:43.356646 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
273 12:40:43.363043 CBFS: Found 'fallback/romstage' @0x80 size 0x1bf24 in mcache @0xfef45638
274 12:40:43.370028 BS: verstage times (exec / console): total (unknown) / 142 ms
275 12:40:43.370496
276 12:40:43.370847
277 12:40:43.382913 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 romstage starting (log level: 8)...
278 12:40:43.390168 VB2:vb2api_ec_sync() In recovery mode, skipping EC sync
279 12:40:43.392971 pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00
280 12:40:43.396074 gpe0_sts[0]: 00200000 gpe0_en[0]: 00000000
281 12:40:43.402804 gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000
282 12:40:43.406118 gpe0_sts[2]: 00001000 gpe0_en[2]: 00000000
283 12:40:43.410174 gpe0_sts[3]: 00000000 gpe0_en[3]: 00092000
284 12:40:43.412991 TCO_STS: 0000 0000
285 12:40:43.416511 GEN_PMCON: d0015038 00002200
286 12:40:43.420048 GBLRST_CAUSE: 00000000 00000000
287 12:40:43.420630 HPR_CAUSE0: 00000000
288 12:40:43.423167 prev_sleep_state 5
289 12:40:43.426050 Boot Count incremented to 20508
290 12:40:43.432904 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
291 12:40:43.439197 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
292 12:40:43.445900 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
293 12:40:43.452718 CBFS: Found 'fspm.bin' @0x78fc0 size 0xa5000 in mcache @0xfef4585c
294 12:40:43.457480 Chrome EC: UHEPI supported
295 12:40:43.463841 FMAP: area RECOVERY_MRC_CACHE found @ f00000 (65536 bytes)
296 12:40:43.477322 Probing TPM: done!
297 12:40:43.483845 Connected to device vid:did:rid of 1ae0:0028:00
298 12:40:43.493832 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_A:0.5.171/cr50_v2.94_mp.164-2fb1dd676c
299 12:40:43.497412 Initialized TPM device CR50 revision 0
300 12:40:43.512450 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x100b return code 0
301 12:40:43.518793 MRC: Hash idx 0x100b comparison successful.
302 12:40:43.521869 MRC cache found, size faa8
303 12:40:43.522406 bootmode is set to: 2
304 12:40:43.525240 SPD index = 2
305 12:40:43.531766 CBFS: Found 'spd.bin' @0x72940 size 0x600 in mcache @0xfef4579c
306 12:40:43.534878 SPD: module type is LPDDR4X
307 12:40:43.538652 SPD: module part number is MT53D1G64D4NW-046
308 12:40:43.544966 SPD: banks 8, ranks 1, rows 17, columns 10, density 16384 Mb
309 12:40:43.547938 SPD: device width 16 bits, bus width 16 bits
310 12:40:43.554932 SPD: module size is 2048 MB (per channel)
311 12:40:43.985231 CBMEM:
312 12:40:43.988444 IMD: root @ 0x76fff000 254 entries.
313 12:40:43.991250 IMD: root @ 0x76ffec00 62 entries.
314 12:40:43.994614 FMAP: area RO_VPD found @ 1800000 (16384 bytes)
315 12:40:44.002301 FMAP: area RW_VPD found @ f35000 (8192 bytes)
316 12:40:44.004501 External stage cache:
317 12:40:44.007769 IMD: root @ 0x7b3ff000 254 entries.
318 12:40:44.011207 IMD: root @ 0x7b3fec00 62 entries.
319 12:40:44.026053 FMAP: area RECOVERY_MRC_CACHE found @ f00000 (65536 bytes)
320 12:40:44.032857 MRC: Checking cached data update for 'RECOVERY_MRC_CACHE'.
321 12:40:44.039572 SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
322 12:40:44.053254 MRC: 'RECOVERY_MRC_CACHE' does not need update.
323 12:40:44.060272 cse_lite: Skip switching to RW in the recovery path
324 12:40:44.060702 8 DIMMs found
325 12:40:44.061044 SMM Memory Map
326 12:40:44.066507 SMRAM : 0x7b000000 0x800000
327 12:40:44.069650 Subregion 0: 0x7b000000 0x200000
328 12:40:44.073191 Subregion 1: 0x7b200000 0x200000
329 12:40:44.076530 Subregion 2: 0x7b400000 0x400000
330 12:40:44.077056 top_of_ram = 0x77000000
331 12:40:44.082853 MTRR Range: Start=76000000 End=77000000 (Size 1000000)
332 12:40:44.089494 MTRR Range: Start=7b000000 End=7b800000 (Size 800000)
333 12:40:44.093195 MTRR Range: Start=f9000000 End=fa000000 (Size 1000000)
334 12:40:44.099700 MTRR Range: Start=ff000000 End=0 (Size 1000000)
335 12:40:44.106379 CBFS: Found 'fallback/postcar' @0x160900 size 0x54f8 in mcache @0xfef4594c
336 12:40:44.113089 Decompressing stage fallback/postcar @ 0x76c0afc0 (38208 bytes)
337 12:40:44.123212 Loading module at 0x76c0b000 with entry 0x76c0b000. filesize: 0x5150 memsize: 0x9500
338 12:40:44.129946 Processing 211 relocs. Offset value of 0x74c0b000
339 12:40:44.136004 BS: romstage times (exec / console): total (unknown) / 277 ms
340 12:40:44.142180
341 12:40:44.142756
342 12:40:44.149834 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 postcar starting (log level: 8)...
343 12:40:44.156578 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
344 12:40:44.162943 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
345 12:40:44.169378 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
346 12:40:44.179718 CBFS: Found 'fallback/ramstage' @0x524c0 size 0x1fbe3 in mcache @0x76c4c0ec
347 12:40:44.186044 Decompressing stage fallback/ramstage @ 0x76b97fc0 (463536 bytes)
348 12:40:44.228437 Loading module at 0x76b98000 with entry 0x76b98000. filesize: 0x4d5d8 memsize: 0x71270
349 12:40:44.235567 Processing 5008 relocs. Offset value of 0x75d98000
350 12:40:44.238411 BS: postcar times (exec / console): total (unknown) / 59 ms
351 12:40:44.239112
352 12:40:44.241858
353 12:40:44.251900 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 ramstage starting (log level: 8)...
354 12:40:44.252329 Normal boot
355 12:40:44.255507 FW_CONFIG value is 0x804c02
356 12:40:44.258751 PCI: 00:07.0 disabled by fw_config
357 12:40:44.262180 PCI: 00:07.1 disabled by fw_config
358 12:40:44.265216 PCI: 00:0d.2 disabled by fw_config
359 12:40:44.268518 PCI: 00:1c.7 disabled by fw_config
360 12:40:44.275310 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
361 12:40:44.282012 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
362 12:40:44.285037 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
363 12:40:44.288348 GENERIC: 0.0 disabled by fw_config
364 12:40:44.294957 GENERIC: 1.0 disabled by fw_config
365 12:40:44.298474 fw_config match found: DB_USB=USB3_ACTIVE
366 12:40:44.301302 fw_config match found: DB_USB=USB3_ACTIVE
367 12:40:44.305023 fw_config match found: DB_USB=USB3_ACTIVE
368 12:40:44.311555 fw_config match found: DB_USB=USB3_ACTIVE
369 12:40:44.314881 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
370 12:40:44.321509 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
371 12:40:44.331223 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
372 12:40:44.337774 CBFS: Found 'cpu_microcode_blob.bin' @0x1c040 size 0x36400 in mcache @0x76c4c09c
373 12:40:44.341161 microcode: sig=0x806c1 pf=0x80 revision=0x86
374 12:40:44.347900 microcode: Update skipped, already up-to-date
375 12:40:44.354208 CBFS: Found 'fsps.bin' @0x11efc0 size 0x418f9 in mcache @0x76c4c30c
376 12:40:44.382476 Detected 4 core, 8 thread CPU.
377 12:40:44.385630 Setting up SMI for CPU
378 12:40:44.388908 IED base = 0x7b400000
379 12:40:44.389431 IED size = 0x00400000
380 12:40:44.392937 Will perform SMM setup.
381 12:40:44.398819 CPU: 11th Gen Intel(R) Core(TM) i7-1160G7 @ 1.20GHz.
382 12:40:44.405703 Loading module at 0x00030000 with entry 0x00030000. filesize: 0x170 memsize: 0x170
383 12:40:44.412140 Processing 16 relocs. Offset value of 0x00030000
384 12:40:44.415304 Attempting to start 7 APs
385 12:40:44.418929 Waiting for 10ms after sending INIT.
386 12:40:44.434187 Waiting for 1st SIPI to complete...done.
387 12:40:44.434766 AP: slot 1 apic_id 1.
388 12:40:44.440828 Waiting for 2nd SIPI to complete...done.
389 12:40:44.441373 AP: slot 2 apic_id 7.
390 12:40:44.443998 AP: slot 5 apic_id 6.
391 12:40:44.447791 AP: slot 7 apic_id 5.
392 12:40:44.448212 AP: slot 4 apic_id 4.
393 12:40:44.450751 AP: slot 6 apic_id 2.
394 12:40:44.453890 AP: slot 3 apic_id 3.
395 12:40:44.460822 Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1b8 memsize: 0x1b8
396 12:40:44.467418 Processing 13 relocs. Offset value of 0x00038000
397 12:40:44.470878 Unable to locate Global NVS
398 12:40:44.477461 SMM Module: stub loaded at 0x00038000. Will call 0x76bb6318(0x00000000)
399 12:40:44.481191 Installing permanent SMM handler to 0x7b000000
400 12:40:44.490194 Loading module at 0x7b010000 with entry 0x7b010c16. filesize: 0xa7c8 memsize: 0xf908
401 12:40:44.493401 Processing 794 relocs. Offset value of 0x7b010000
402 12:40:44.503736 Loading module at 0x7b008000 with entry 0x7b008000. filesize: 0x1b8 memsize: 0x1b8
403 12:40:44.507002 Processing 13 relocs. Offset value of 0x7b008000
404 12:40:44.513669 SMM Module: placing jmp sequence at 0x7b007c00 rel16 0x03fd
405 12:40:44.520275 SMM Module: placing jmp sequence at 0x7b007800 rel16 0x07fd
406 12:40:44.524168 SMM Module: placing jmp sequence at 0x7b007400 rel16 0x0bfd
407 12:40:44.530636 SMM Module: placing jmp sequence at 0x7b007000 rel16 0x0ffd
408 12:40:44.536667 SMM Module: placing jmp sequence at 0x7b006c00 rel16 0x13fd
409 12:40:44.543579 SMM Module: placing jmp sequence at 0x7b006800 rel16 0x17fd
410 12:40:44.550682 SMM Module: placing jmp sequence at 0x7b006400 rel16 0x1bfd
411 12:40:44.551121 Unable to locate Global NVS
412 12:40:44.560067 SMM Module: stub loaded at 0x7b008000. Will call 0x7b010c16(0x00000000)
413 12:40:44.563090 Clearing SMI status registers
414 12:40:44.563528 SMI_STS: PM1
415 12:40:44.566518 PM1_STS: PWRBTN
416 12:40:44.573157 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b000000, cpu = 0
417 12:40:44.576370 In relocation handler: CPU 0
418 12:40:44.580075 New SMBASE=0x7b000000 IEDBASE=0x7b400000
419 12:40:44.586490 Writing SMRR. base = 0x7b000006, mask=0xff800c00
420 12:40:44.587004 Relocation complete.
421 12:40:44.596839 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afffc00, cpu = 1
422 12:40:44.597343 In relocation handler: CPU 1
423 12:40:44.603494 New SMBASE=0x7afffc00 IEDBASE=0x7b400000
424 12:40:44.604019 Relocation complete.
425 12:40:44.613120 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affe400, cpu = 7
426 12:40:44.613649 In relocation handler: CPU 7
427 12:40:44.619763 New SMBASE=0x7affe400 IEDBASE=0x7b400000
428 12:40:44.620287 Relocation complete.
429 12:40:44.626853 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff000, cpu = 4
430 12:40:44.630010 In relocation handler: CPU 4
431 12:40:44.636602 New SMBASE=0x7afff000 IEDBASE=0x7b400000
432 12:40:44.639662 Writing SMRR. base = 0x7b000006, mask=0xff800c00
433 12:40:44.642606 Relocation complete.
434 12:40:44.649248 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff400, cpu = 3
435 12:40:44.652474 In relocation handler: CPU 3
436 12:40:44.656294 New SMBASE=0x7afff400 IEDBASE=0x7b400000
437 12:40:44.659891 Relocation complete.
438 12:40:44.666484 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affe800, cpu = 6
439 12:40:44.669906 In relocation handler: CPU 6
440 12:40:44.673175 New SMBASE=0x7affe800 IEDBASE=0x7b400000
441 12:40:44.676012 Writing SMRR. base = 0x7b000006, mask=0xff800c00
442 12:40:44.679691 Relocation complete.
443 12:40:44.686229 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affec00, cpu = 5
444 12:40:44.689575 In relocation handler: CPU 5
445 12:40:44.692994 New SMBASE=0x7affec00 IEDBASE=0x7b400000
446 12:40:44.699879 Writing SMRR. base = 0x7b000006, mask=0xff800c00
447 12:40:44.702963 Relocation complete.
448 12:40:44.710170 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff800, cpu = 2
449 12:40:44.713284 In relocation handler: CPU 2
450 12:40:44.715954 New SMBASE=0x7afff800 IEDBASE=0x7b400000
451 12:40:44.716389 Relocation complete.
452 12:40:44.719255 Initializing CPU #0
453 12:40:44.722796 CPU: vendor Intel device 806c1
454 12:40:44.725652 CPU: family 06, model 8c, stepping 01
455 12:40:44.729470 Clearing out pending MCEs
456 12:40:44.732432 Setting up local APIC...
457 12:40:44.736219 apic_id: 0x00 done.
458 12:40:44.736318 Turbo is available but hidden
459 12:40:44.738979 Turbo is available and visible
460 12:40:44.746088 microcode: Update skipped, already up-to-date
461 12:40:44.746584 CPU #0 initialized
462 12:40:44.749711 Initializing CPU #5
463 12:40:44.753246 Initializing CPU #2
464 12:40:44.756176 CPU: vendor Intel device 806c1
465 12:40:44.759489 CPU: family 06, model 8c, stepping 01
466 12:40:44.762697 CPU: vendor Intel device 806c1
467 12:40:44.766013 CPU: family 06, model 8c, stepping 01
468 12:40:44.769576 Clearing out pending MCEs
469 12:40:44.770011 Clearing out pending MCEs
470 12:40:44.772870 Setting up local APIC...
471 12:40:44.776194 Initializing CPU #6
472 12:40:44.776631 Initializing CPU #3
473 12:40:44.779178 Initializing CPU #7
474 12:40:44.782990 Initializing CPU #4
475 12:40:44.786043 CPU: vendor Intel device 806c1
476 12:40:44.789087 CPU: family 06, model 8c, stepping 01
477 12:40:44.793097 CPU: vendor Intel device 806c1
478 12:40:44.795785 CPU: family 06, model 8c, stepping 01
479 12:40:44.799494 Clearing out pending MCEs
480 12:40:44.799916 Clearing out pending MCEs
481 12:40:44.802917 Setting up local APIC...
482 12:40:44.805428 CPU: vendor Intel device 806c1
483 12:40:44.809315 CPU: family 06, model 8c, stepping 01
484 12:40:44.813026 Setting up local APIC...
485 12:40:44.816724 Initializing CPU #1
486 12:40:44.817144 Clearing out pending MCEs
487 12:40:44.820127 CPU: vendor Intel device 806c1
488 12:40:44.823408 CPU: family 06, model 8c, stepping 01
489 12:40:44.826691 Setting up local APIC...
490 12:40:44.830340 Setting up local APIC...
491 12:40:44.830895 apic_id: 0x07 done.
492 12:40:44.833966 apic_id: 0x06 done.
493 12:40:44.836744 microcode: Update skipped, already up-to-date
494 12:40:44.840734 apic_id: 0x03 done.
495 12:40:44.843494 Clearing out pending MCEs
496 12:40:44.847019 microcode: Update skipped, already up-to-date
497 12:40:44.850220 Setting up local APIC...
498 12:40:44.853642 CPU #3 initialized
499 12:40:44.854170 apic_id: 0x02 done.
500 12:40:44.860002 microcode: Update skipped, already up-to-date
501 12:40:44.860512 CPU #2 initialized
502 12:40:44.863330 CPU #5 initialized
503 12:40:44.867127 microcode: Update skipped, already up-to-date
504 12:40:44.870303 CPU: vendor Intel device 806c1
505 12:40:44.873485 CPU: family 06, model 8c, stepping 01
506 12:40:44.876656 apic_id: 0x05 done.
507 12:40:44.880306 apic_id: 0x04 done.
508 12:40:44.883182 microcode: Update skipped, already up-to-date
509 12:40:44.887157 microcode: Update skipped, already up-to-date
510 12:40:44.889523 CPU #7 initialized
511 12:40:44.889616 CPU #4 initialized
512 12:40:44.892894 Clearing out pending MCEs
513 12:40:44.896647 CPU #6 initialized
514 12:40:44.899505 Setting up local APIC...
515 12:40:44.899700 apic_id: 0x01 done.
516 12:40:44.906573 microcode: Update skipped, already up-to-date
517 12:40:44.906775 CPU #1 initialized
518 12:40:44.913820 bsp_do_flight_plan done after 468 msecs.
519 12:40:44.916195 CPU: frequency set to 4400 MHz
520 12:40:44.916426 Enabling SMIs.
521 12:40:44.922787 BS: BS_DEV_INIT_CHIPS entry times (exec / console): 347 / 317 ms
522 12:40:44.938821 SATAXPCIE1 indicates PCIe NVMe is present
523 12:40:44.942492 Probing TPM: done!
524 12:40:44.945701 Connected to device vid:did:rid of 1ae0:0028:00
525 12:40:44.956085 Firmware version: B2-C:0 RO_B:0.0.12/9eb618de RW_A:0.5.171/cr50_v2.94_mp.164-2fb1dd676c
526 12:40:44.959374 Initialized TPM device CR50 revision 0
527 12:40:44.962472 Enabling S0i3.4
528 12:40:44.969076 CBFS: Found 'vbt.bin' @0x78a40 size 0x4f0 in mcache @0x76c4c1fc
529 12:40:44.972501 Found a VBT of 8704 bytes after decompression
530 12:40:44.979071 cse_lite: CSE RO boot. HybridStorageMode disabled
531 12:40:44.986214 WEAK: src/soc/intel/tigerlake/fsp_params.c/mainboard_silicon_init_params called
532 12:40:45.061386 FSPS returned 0
533 12:40:45.064894 Executing Phase 1 of FspMultiPhaseSiInit
534 12:40:45.074699 FSP MultiPhaseSiInit src/soc/intel/tigerlake/fsp_params.c/platform_fsp_multi_phase_init_cb called
535 12:40:45.078250 port C0 DISC req: usage 1 usb3 1 usb2 5
536 12:40:45.081385 Raw Buffer output 0 00000511
537 12:40:45.084648 Raw Buffer output 1 00000000
538 12:40:45.088334 pmc_send_ipc_cmd succeeded
539 12:40:45.095009 port C1 DISC req: usage 1 usb3 2 usb2 3
540 12:40:45.095461 Raw Buffer output 0 00000321
541 12:40:45.098328 Raw Buffer output 1 00000000
542 12:40:45.102834 pmc_send_ipc_cmd succeeded
543 12:40:45.107097 Detected 4 core, 8 thread CPU.
544 12:40:45.110579 Detected 4 core, 8 thread CPU.
545 12:40:45.311731 Display FSP Version Info HOB
546 12:40:45.314627 Reference Code - CPU = a.0.4c.31
547 12:40:45.317767 uCode Version = 0.0.0.86
548 12:40:45.321296 TXT ACM version = ff.ff.ff.ffff
549 12:40:45.324782 Reference Code - ME = a.0.4c.31
550 12:40:45.327723 MEBx version = 0.0.0.0
551 12:40:45.331288 ME Firmware Version = Consumer SKU
552 12:40:45.334200 Reference Code - PCH = a.0.4c.31
553 12:40:45.337612 PCH-CRID Status = Disabled
554 12:40:45.340940 PCH-CRID Original Value = ff.ff.ff.ffff
555 12:40:45.344310 PCH-CRID New Value = ff.ff.ff.ffff
556 12:40:45.347424 OPROM - RST - RAID = ff.ff.ff.ffff
557 12:40:45.351340 PCH Hsio Version = 4.0.0.0
558 12:40:45.354192 Reference Code - SA - System Agent = a.0.4c.31
559 12:40:45.357116 Reference Code - MRC = 2.0.0.1
560 12:40:45.360761 SA - PCIe Version = a.0.4c.31
561 12:40:45.363413 SA-CRID Status = Disabled
562 12:40:45.366765 SA-CRID Original Value = 0.0.0.1
563 12:40:45.370127 SA-CRID New Value = 0.0.0.1
564 12:40:45.373694 OPROM - VBIOS = ff.ff.ff.ffff
565 12:40:45.376855 IO Manageability Engine FW Version = 11.1.4.0
566 12:40:45.380692 PHY Build Version = 0.0.0.e0
567 12:40:45.383754 Thunderbolt(TM) FW Version = 0.0.0.0
568 12:40:45.390490 System Agent Manageability Engine FW Version = ff.ff.ff.ffff
569 12:40:45.393934 ITSS IRQ Polarities Before:
570 12:40:45.394157 IPC0: 0xffffffff
571 12:40:45.397842 IPC1: 0xffffffff
572 12:40:45.398072 IPC2: 0xffffffff
573 12:40:45.401520 IPC3: 0xffffffff
574 12:40:45.401786 ITSS IRQ Polarities After:
575 12:40:45.405102 IPC0: 0xffffffff
576 12:40:45.405398 IPC1: 0xffffffff
577 12:40:45.407717 IPC2: 0xffffffff
578 12:40:45.411608 IPC3: 0xffffffff
579 12:40:45.414754 Found PCIe Root Port #9 at PCI: 00:1d.0.
580 12:40:45.425197 pcie_rp_update_dev: Couldn't find PCIe Root Port #1 (originally PCI: 00:1c.0) which was enabled in devicetree, removing.
581 12:40:45.437456 pcie_rp_update_dev: Couldn't find PCIe Root Port #7 (originally PCI: 00:1c.6) which was enabled in devicetree, removing.
582 12:40:45.451406 pcie_rp_update_dev: Couldn't find PCIe Root Port #11 (originally PCI: 00:1d.2) which was enabled in devicetree, removing.
583 12:40:45.457426 BS: BS_DEV_INIT_CHIPS run times (exec / console): 291 / 236 ms
584 12:40:45.457615 Enumerating buses...
585 12:40:45.463977 Show all devs... Before device enumeration.
586 12:40:45.464173 Root Device: enabled 1
587 12:40:45.467731 DOMAIN: 0000: enabled 1
588 12:40:45.471164 CPU_CLUSTER: 0: enabled 1
589 12:40:45.474159 PCI: 00:00.0: enabled 1
590 12:40:45.474386 PCI: 00:02.0: enabled 1
591 12:40:45.477435 PCI: 00:04.0: enabled 1
592 12:40:45.481042 PCI: 00:05.0: enabled 1
593 12:40:45.481321 PCI: 00:06.0: enabled 0
594 12:40:45.484288 PCI: 00:07.0: enabled 0
595 12:40:45.487693 PCI: 00:07.1: enabled 0
596 12:40:45.491068 PCI: 00:07.2: enabled 0
597 12:40:45.491441 PCI: 00:07.3: enabled 0
598 12:40:45.494613 PCI: 00:08.0: enabled 1
599 12:40:45.497857 PCI: 00:09.0: enabled 0
600 12:40:45.501218 PCI: 00:0a.0: enabled 0
601 12:40:45.501742 PCI: 00:0d.0: enabled 1
602 12:40:45.504639 PCI: 00:0d.1: enabled 0
603 12:40:45.507898 PCI: 00:0d.2: enabled 0
604 12:40:45.510734 PCI: 00:0d.3: enabled 0
605 12:40:45.511155 PCI: 00:0e.0: enabled 0
606 12:40:45.514741 PCI: 00:10.2: enabled 1
607 12:40:45.517777 PCI: 00:10.6: enabled 0
608 12:40:45.520384 PCI: 00:10.7: enabled 0
609 12:40:45.520477 PCI: 00:12.0: enabled 0
610 12:40:45.523739 PCI: 00:12.6: enabled 0
611 12:40:45.527761 PCI: 00:13.0: enabled 0
612 12:40:45.528289 PCI: 00:14.0: enabled 1
613 12:40:45.531120 PCI: 00:14.1: enabled 0
614 12:40:45.534324 PCI: 00:14.2: enabled 1
615 12:40:45.537323 PCI: 00:14.3: enabled 1
616 12:40:45.537745 PCI: 00:15.0: enabled 1
617 12:40:45.541126 PCI: 00:15.1: enabled 1
618 12:40:45.544146 PCI: 00:15.2: enabled 1
619 12:40:45.548056 PCI: 00:15.3: enabled 1
620 12:40:45.548571 PCI: 00:16.0: enabled 1
621 12:40:45.550891 PCI: 00:16.1: enabled 0
622 12:40:45.554111 PCI: 00:16.2: enabled 0
623 12:40:45.557346 PCI: 00:16.3: enabled 0
624 12:40:45.557923 PCI: 00:16.4: enabled 0
625 12:40:45.560509 PCI: 00:16.5: enabled 0
626 12:40:45.564098 PCI: 00:17.0: enabled 1
627 12:40:45.564615 PCI: 00:19.0: enabled 0
628 12:40:45.567305 PCI: 00:19.1: enabled 1
629 12:40:45.570975 PCI: 00:19.2: enabled 0
630 12:40:45.574004 PCI: 00:1c.0: enabled 1
631 12:40:45.574581 PCI: 00:1c.1: enabled 0
632 12:40:45.577238 PCI: 00:1c.2: enabled 0
633 12:40:45.580760 PCI: 00:1c.3: enabled 0
634 12:40:45.584086 PCI: 00:1c.4: enabled 0
635 12:40:45.584613 PCI: 00:1c.5: enabled 0
636 12:40:45.587477 PCI: 00:1c.6: enabled 1
637 12:40:45.590699 PCI: 00:1c.7: enabled 0
638 12:40:45.594011 PCI: 00:1d.0: enabled 1
639 12:40:45.594686 PCI: 00:1d.1: enabled 0
640 12:40:45.597110 PCI: 00:1d.2: enabled 1
641 12:40:45.600198 PCI: 00:1d.3: enabled 0
642 12:40:45.604229 PCI: 00:1e.0: enabled 1
643 12:40:45.604649 PCI: 00:1e.1: enabled 0
644 12:40:45.607254 PCI: 00:1e.2: enabled 1
645 12:40:45.610518 PCI: 00:1e.3: enabled 1
646 12:40:45.610951 PCI: 00:1f.0: enabled 1
647 12:40:45.614391 PCI: 00:1f.1: enabled 0
648 12:40:45.617438 PCI: 00:1f.2: enabled 1
649 12:40:45.620645 PCI: 00:1f.3: enabled 1
650 12:40:45.621163 PCI: 00:1f.4: enabled 0
651 12:40:45.624009 PCI: 00:1f.5: enabled 1
652 12:40:45.627088 PCI: 00:1f.6: enabled 0
653 12:40:45.630343 PCI: 00:1f.7: enabled 0
654 12:40:45.630921 APIC: 00: enabled 1
655 12:40:45.633730 GENERIC: 0.0: enabled 1
656 12:40:45.636971 GENERIC: 0.0: enabled 1
657 12:40:45.637576 GENERIC: 1.0: enabled 1
658 12:40:45.640540 GENERIC: 0.0: enabled 1
659 12:40:45.643516 GENERIC: 1.0: enabled 1
660 12:40:45.647141 USB0 port 0: enabled 1
661 12:40:45.647582 GENERIC: 0.0: enabled 1
662 12:40:45.650365 USB0 port 0: enabled 1
663 12:40:45.653708 GENERIC: 0.0: enabled 1
664 12:40:45.654245 I2C: 00:1a: enabled 1
665 12:40:45.656838 I2C: 00:31: enabled 1
666 12:40:45.660409 I2C: 00:32: enabled 1
667 12:40:45.660946 I2C: 00:10: enabled 1
668 12:40:45.663691 I2C: 00:15: enabled 1
669 12:40:45.666849 GENERIC: 0.0: enabled 0
670 12:40:45.670227 GENERIC: 1.0: enabled 0
671 12:40:45.670751 GENERIC: 0.0: enabled 1
672 12:40:45.673734 SPI: 00: enabled 1
673 12:40:45.676642 SPI: 00: enabled 1
674 12:40:45.676837 PNP: 0c09.0: enabled 1
675 12:40:45.679925 GENERIC: 0.0: enabled 1
676 12:40:45.683359 USB3 port 0: enabled 1
677 12:40:45.683531 USB3 port 1: enabled 1
678 12:40:45.687125 USB3 port 2: enabled 0
679 12:40:45.690346 USB3 port 3: enabled 0
680 12:40:45.690567 USB2 port 0: enabled 0
681 12:40:45.693366 USB2 port 1: enabled 1
682 12:40:45.696437 USB2 port 2: enabled 1
683 12:40:45.700492 USB2 port 3: enabled 0
684 12:40:45.700713 USB2 port 4: enabled 1
685 12:40:45.703621 USB2 port 5: enabled 0
686 12:40:45.706632 USB2 port 6: enabled 0
687 12:40:45.706878 USB2 port 7: enabled 0
688 12:40:45.710022 USB2 port 8: enabled 0
689 12:40:45.713319 USB2 port 9: enabled 0
690 12:40:45.716550 USB3 port 0: enabled 0
691 12:40:45.716812 USB3 port 1: enabled 1
692 12:40:45.720651 USB3 port 2: enabled 0
693 12:40:45.723410 USB3 port 3: enabled 0
694 12:40:45.723660 GENERIC: 0.0: enabled 1
695 12:40:45.726884 GENERIC: 1.0: enabled 1
696 12:40:45.730038 APIC: 01: enabled 1
697 12:40:45.730510 APIC: 07: enabled 1
698 12:40:45.733380 APIC: 03: enabled 1
699 12:40:45.737109 APIC: 04: enabled 1
700 12:40:45.737663 APIC: 06: enabled 1
701 12:40:45.740010 APIC: 02: enabled 1
702 12:40:45.740556 APIC: 05: enabled 1
703 12:40:45.743090 Compare with tree...
704 12:40:45.746646 Root Device: enabled 1
705 12:40:45.749961 DOMAIN: 0000: enabled 1
706 12:40:45.750397 PCI: 00:00.0: enabled 1
707 12:40:45.753161 PCI: 00:02.0: enabled 1
708 12:40:45.756251 PCI: 00:04.0: enabled 1
709 12:40:45.759996 GENERIC: 0.0: enabled 1
710 12:40:45.763147 PCI: 00:05.0: enabled 1
711 12:40:45.763587 PCI: 00:06.0: enabled 0
712 12:40:45.766407 PCI: 00:07.0: enabled 0
713 12:40:45.770565 GENERIC: 0.0: enabled 1
714 12:40:45.773608 PCI: 00:07.1: enabled 0
715 12:40:45.776525 GENERIC: 1.0: enabled 1
716 12:40:45.776967 PCI: 00:07.2: enabled 0
717 12:40:45.780348 GENERIC: 0.0: enabled 1
718 12:40:45.783892 PCI: 00:07.3: enabled 0
719 12:40:45.786960 GENERIC: 1.0: enabled 1
720 12:40:45.789578 PCI: 00:08.0: enabled 1
721 12:40:45.790102 PCI: 00:09.0: enabled 0
722 12:40:45.793186 PCI: 00:0a.0: enabled 0
723 12:40:45.796207 PCI: 00:0d.0: enabled 1
724 12:40:45.799515 USB0 port 0: enabled 1
725 12:40:45.803114 USB3 port 0: enabled 1
726 12:40:45.806649 USB3 port 1: enabled 1
727 12:40:45.807116 USB3 port 2: enabled 0
728 12:40:45.809810 USB3 port 3: enabled 0
729 12:40:45.813022 PCI: 00:0d.1: enabled 0
730 12:40:45.816054 PCI: 00:0d.2: enabled 0
731 12:40:45.819703 GENERIC: 0.0: enabled 1
732 12:40:45.820235 PCI: 00:0d.3: enabled 0
733 12:40:45.823019 PCI: 00:0e.0: enabled 0
734 12:40:45.826359 PCI: 00:10.2: enabled 1
735 12:40:45.829707 PCI: 00:10.6: enabled 0
736 12:40:45.832613 PCI: 00:10.7: enabled 0
737 12:40:45.832852 PCI: 00:12.0: enabled 0
738 12:40:45.836122 PCI: 00:12.6: enabled 0
739 12:40:45.839292 PCI: 00:13.0: enabled 0
740 12:40:45.842286 PCI: 00:14.0: enabled 1
741 12:40:45.845879 USB0 port 0: enabled 1
742 12:40:45.845979 USB2 port 0: enabled 0
743 12:40:45.848861 USB2 port 1: enabled 1
744 12:40:45.852475 USB2 port 2: enabled 1
745 12:40:45.856183 USB2 port 3: enabled 0
746 12:40:45.859232 USB2 port 4: enabled 1
747 12:40:45.859434 USB2 port 5: enabled 0
748 12:40:45.862406 USB2 port 6: enabled 0
749 12:40:45.865786 USB2 port 7: enabled 0
750 12:40:45.869024 USB2 port 8: enabled 0
751 12:40:45.872863 USB2 port 9: enabled 0
752 12:40:45.876042 USB3 port 0: enabled 0
753 12:40:45.876332 USB3 port 1: enabled 1
754 12:40:45.879342 USB3 port 2: enabled 0
755 12:40:45.882325 USB3 port 3: enabled 0
756 12:40:45.886357 PCI: 00:14.1: enabled 0
757 12:40:45.889297 PCI: 00:14.2: enabled 1
758 12:40:45.889711 PCI: 00:14.3: enabled 1
759 12:40:45.892704 GENERIC: 0.0: enabled 1
760 12:40:45.896604 PCI: 00:15.0: enabled 1
761 12:40:45.899440 I2C: 00:1a: enabled 1
762 12:40:45.902273 I2C: 00:31: enabled 1
763 12:40:45.902762 I2C: 00:32: enabled 1
764 12:40:45.905831 PCI: 00:15.1: enabled 1
765 12:40:45.908617 I2C: 00:10: enabled 1
766 12:40:45.912193 PCI: 00:15.2: enabled 1
767 12:40:45.912286 PCI: 00:15.3: enabled 1
768 12:40:45.915531 PCI: 00:16.0: enabled 1
769 12:40:45.918860 PCI: 00:16.1: enabled 0
770 12:40:45.921863 PCI: 00:16.2: enabled 0
771 12:40:45.925274 PCI: 00:16.3: enabled 0
772 12:40:45.925383 PCI: 00:16.4: enabled 0
773 12:40:45.928926 PCI: 00:16.5: enabled 0
774 12:40:45.932448 PCI: 00:17.0: enabled 1
775 12:40:45.936156 PCI: 00:19.0: enabled 0
776 12:40:45.938735 PCI: 00:19.1: enabled 1
777 12:40:45.938929 I2C: 00:15: enabled 1
778 12:40:45.942143 PCI: 00:19.2: enabled 0
779 12:40:45.945776 PCI: 00:1d.0: enabled 1
780 12:40:45.949257 GENERIC: 0.0: enabled 1
781 12:40:45.952030 PCI: 00:1e.0: enabled 1
782 12:40:45.952319 PCI: 00:1e.1: enabled 0
783 12:40:45.955892 PCI: 00:1e.2: enabled 1
784 12:40:45.959114 SPI: 00: enabled 1
785 12:40:45.962190 PCI: 00:1e.3: enabled 1
786 12:40:45.962507 SPI: 00: enabled 1
787 12:40:45.966062 PCI: 00:1f.0: enabled 1
788 12:40:45.969417 PNP: 0c09.0: enabled 1
789 12:40:45.972109 PCI: 00:1f.1: enabled 0
790 12:40:45.976251 PCI: 00:1f.2: enabled 1
791 12:40:45.976798 GENERIC: 0.0: enabled 1
792 12:40:45.979039 GENERIC: 0.0: enabled 1
793 12:40:45.982409 GENERIC: 1.0: enabled 1
794 12:40:45.985357 PCI: 00:1f.3: enabled 1
795 12:40:45.988840 PCI: 00:1f.4: enabled 0
796 12:40:45.989265 PCI: 00:1f.5: enabled 1
797 12:40:45.992180 PCI: 00:1f.6: enabled 0
798 12:40:45.995699 PCI: 00:1f.7: enabled 0
799 12:40:45.999051 CPU_CLUSTER: 0: enabled 1
800 12:40:46.050986 APIC: 00: enabled 1
801 12:40:46.051526 APIC: 01: enabled 1
802 12:40:46.051890 APIC: 07: enabled 1
803 12:40:46.052577 APIC: 03: enabled 1
804 12:40:46.052954 APIC: 04: enabled 1
805 12:40:46.053264 APIC: 06: enabled 1
806 12:40:46.053559 APIC: 02: enabled 1
807 12:40:46.053845 APIC: 05: enabled 1
808 12:40:46.054131 Root Device scanning...
809 12:40:46.054412 scan_static_bus for Root Device
810 12:40:46.054750 DOMAIN: 0000 enabled
811 12:40:46.055030 CPU_CLUSTER: 0 enabled
812 12:40:46.055311 DOMAIN: 0000 scanning...
813 12:40:46.055589 PCI: pci_scan_bus for bus 00
814 12:40:46.055936 PCI: 00:00.0 [8086/0000] ops
815 12:40:46.056284 PCI: 00:00.0 [8086/9a12] enabled
816 12:40:46.056576 PCI: 00:02.0 [8086/0000] bus ops
817 12:40:46.056856 PCI: 00:02.0 [8086/9a40] enabled
818 12:40:46.057137 PCI: 00:04.0 [8086/0000] bus ops
819 12:40:46.080299 PCI: 00:04.0 [8086/9a03] enabled
820 12:40:46.080933 PCI: 00:05.0 [8086/9a19] enabled
821 12:40:46.081302 PCI: 00:07.0 [0000/0000] hidden
822 12:40:46.081640 PCI: 00:08.0 [8086/9a11] enabled
823 12:40:46.082288 PCI: 00:0a.0 [8086/9a0d] disabled
824 12:40:46.082660 PCI: 00:0d.0 [8086/0000] bus ops
825 12:40:46.083026 PCI: 00:0d.0 [8086/9a13] enabled
826 12:40:46.083439 PCI: 00:14.0 [8086/0000] bus ops
827 12:40:46.084262 PCI: 00:14.0 [8086/a0ed] enabled
828 12:40:46.084711 PCI: 00:14.2 [8086/a0ef] enabled
829 12:40:46.087280 PCI: 00:14.3 [8086/0000] bus ops
830 12:40:46.091008 PCI: 00:14.3 [8086/a0f0] enabled
831 12:40:46.094374 PCI: 00:15.0 [8086/0000] bus ops
832 12:40:46.097874 PCI: 00:15.0 [8086/a0e8] enabled
833 12:40:46.101031 PCI: 00:15.1 [8086/0000] bus ops
834 12:40:46.104179 PCI: 00:15.1 [8086/a0e9] enabled
835 12:40:46.107366 PCI: 00:15.2 [8086/0000] bus ops
836 12:40:46.111412 PCI: 00:15.2 [8086/a0ea] enabled
837 12:40:46.113814 PCI: 00:15.3 [8086/0000] bus ops
838 12:40:46.117732 PCI: 00:15.3 [8086/a0eb] enabled
839 12:40:46.120688 PCI: 00:16.0 [8086/0000] ops
840 12:40:46.124209 PCI: 00:16.0 [8086/a0e0] enabled
841 12:40:46.127322 PCI: Static device PCI: 00:17.0 not found, disabling it.
842 12:40:46.130679 PCI: 00:19.0 [8086/0000] bus ops
843 12:40:46.133949 PCI: 00:19.0 [8086/a0c5] disabled
844 12:40:46.137444 PCI: 00:19.1 [8086/0000] bus ops
845 12:40:46.140770 PCI: 00:19.1 [8086/a0c6] enabled
846 12:40:46.144102 PCI: 00:1d.0 [8086/0000] bus ops
847 12:40:46.147463 PCI: 00:1d.0 [8086/a0b0] enabled
848 12:40:46.150400 PCI: 00:1e.0 [8086/0000] ops
849 12:40:46.154130 PCI: 00:1e.0 [8086/a0a8] enabled
850 12:40:46.157395 PCI: 00:1e.2 [8086/0000] bus ops
851 12:40:46.160752 PCI: 00:1e.2 [8086/a0aa] enabled
852 12:40:46.164316 PCI: 00:1e.3 [8086/0000] bus ops
853 12:40:46.167289 PCI: 00:1e.3 [8086/a0ab] enabled
854 12:40:46.170966 PCI: 00:1f.0 [8086/0000] bus ops
855 12:40:46.174470 PCI: 00:1f.0 [8086/a087] enabled
856 12:40:46.177489 RTC Init
857 12:40:46.180764 Set power on after power failure.
858 12:40:46.181188 Disabling Deep S3
859 12:40:46.184120 Disabling Deep S3
860 12:40:46.184542 Disabling Deep S4
861 12:40:46.187681 Disabling Deep S4
862 12:40:46.190957 Disabling Deep S5
863 12:40:46.191379 Disabling Deep S5
864 12:40:46.194375 PCI: 00:1f.2 [0000/0000] hidden
865 12:40:46.197458 PCI: 00:1f.3 [8086/0000] bus ops
866 12:40:46.200628 PCI: 00:1f.3 [8086/a0c8] enabled
867 12:40:46.204672 PCI: 00:1f.5 [8086/0000] bus ops
868 12:40:46.207309 PCI: 00:1f.5 [8086/a0a4] enabled
869 12:40:46.211252 PCI: Leftover static devices:
870 12:40:46.211706 PCI: 00:10.2
871 12:40:46.213979 PCI: 00:10.6
872 12:40:46.214402 PCI: 00:10.7
873 12:40:46.217365 PCI: 00:06.0
874 12:40:46.217890 PCI: 00:07.1
875 12:40:46.218232 PCI: 00:07.2
876 12:40:46.220399 PCI: 00:07.3
877 12:40:46.220823 PCI: 00:09.0
878 12:40:46.223933 PCI: 00:0d.1
879 12:40:46.224465 PCI: 00:0d.2
880 12:40:46.226987 PCI: 00:0d.3
881 12:40:46.227079 PCI: 00:0e.0
882 12:40:46.227153 PCI: 00:12.0
883 12:40:46.230232 PCI: 00:12.6
884 12:40:46.230323 PCI: 00:13.0
885 12:40:46.233706 PCI: 00:14.1
886 12:40:46.233798 PCI: 00:16.1
887 12:40:46.233871 PCI: 00:16.2
888 12:40:46.236959 PCI: 00:16.3
889 12:40:46.237058 PCI: 00:16.4
890 12:40:46.240166 PCI: 00:16.5
891 12:40:46.240353 PCI: 00:17.0
892 12:40:46.240454 PCI: 00:19.2
893 12:40:46.243697 PCI: 00:1e.1
894 12:40:46.243902 PCI: 00:1f.1
895 12:40:46.247219 PCI: 00:1f.4
896 12:40:46.247462 PCI: 00:1f.6
897 12:40:46.250126 PCI: 00:1f.7
898 12:40:46.250293 PCI: Check your devicetree.cb.
899 12:40:46.253435 PCI: 00:02.0 scanning...
900 12:40:46.257381 scan_generic_bus for PCI: 00:02.0
901 12:40:46.260626 scan_generic_bus for PCI: 00:02.0 done
902 12:40:46.267188 scan_bus: bus PCI: 00:02.0 finished in 7 msecs
903 12:40:46.270652 PCI: 00:04.0 scanning...
904 12:40:46.274060 scan_generic_bus for PCI: 00:04.0
905 12:40:46.274302 GENERIC: 0.0 enabled
906 12:40:46.280498 bus: PCI: 00:04.0[0]->scan_generic_bus for PCI: 00:04.0 done
907 12:40:46.287398 scan_bus: bus PCI: 00:04.0 finished in 11 msecs
908 12:40:46.287923 PCI: 00:0d.0 scanning...
909 12:40:46.290723 scan_static_bus for PCI: 00:0d.0
910 12:40:46.293842 USB0 port 0 enabled
911 12:40:46.297056 USB0 port 0 scanning...
912 12:40:46.299925 scan_static_bus for USB0 port 0
913 12:40:46.303358 USB3 port 0 enabled
914 12:40:46.303450 USB3 port 1 enabled
915 12:40:46.306484 USB3 port 2 disabled
916 12:40:46.306577 USB3 port 3 disabled
917 12:40:46.309658 USB3 port 0 scanning...
918 12:40:46.313528 scan_static_bus for USB3 port 0
919 12:40:46.316669 scan_static_bus for USB3 port 0 done
920 12:40:46.323163 scan_bus: bus USB3 port 0 finished in 6 msecs
921 12:40:46.323351 USB3 port 1 scanning...
922 12:40:46.326750 scan_static_bus for USB3 port 1
923 12:40:46.333129 scan_static_bus for USB3 port 1 done
924 12:40:46.336805 scan_bus: bus USB3 port 1 finished in 6 msecs
925 12:40:46.340248 scan_static_bus for USB0 port 0 done
926 12:40:46.346744 scan_bus: bus USB0 port 0 finished in 43 msecs
927 12:40:46.350059 scan_static_bus for PCI: 00:0d.0 done
928 12:40:46.353822 scan_bus: bus PCI: 00:0d.0 finished in 60 msecs
929 12:40:46.356875 PCI: 00:14.0 scanning...
930 12:40:46.360292 scan_static_bus for PCI: 00:14.0
931 12:40:46.363700 USB0 port 0 enabled
932 12:40:46.364120 USB0 port 0 scanning...
933 12:40:46.366854 scan_static_bus for USB0 port 0
934 12:40:46.370210 USB2 port 0 disabled
935 12:40:46.373869 USB2 port 1 enabled
936 12:40:46.374395 USB2 port 2 enabled
937 12:40:46.376835 USB2 port 3 disabled
938 12:40:46.377254 USB2 port 4 enabled
939 12:40:46.380028 USB2 port 5 disabled
940 12:40:46.383437 USB2 port 6 disabled
941 12:40:46.383857 USB2 port 7 disabled
942 12:40:46.386584 USB2 port 8 disabled
943 12:40:46.389839 USB2 port 9 disabled
944 12:40:46.390256 USB3 port 0 disabled
945 12:40:46.393356 USB3 port 1 enabled
946 12:40:46.397047 USB3 port 2 disabled
947 12:40:46.397572 USB3 port 3 disabled
948 12:40:46.400048 USB2 port 1 scanning...
949 12:40:46.403315 scan_static_bus for USB2 port 1
950 12:40:46.406599 scan_static_bus for USB2 port 1 done
951 12:40:46.413395 scan_bus: bus USB2 port 1 finished in 6 msecs
952 12:40:46.413917 USB2 port 2 scanning...
953 12:40:46.416585 scan_static_bus for USB2 port 2
954 12:40:46.420412 scan_static_bus for USB2 port 2 done
955 12:40:46.426746 scan_bus: bus USB2 port 2 finished in 6 msecs
956 12:40:46.429625 USB2 port 4 scanning...
957 12:40:46.432749 scan_static_bus for USB2 port 4
958 12:40:46.436582 scan_static_bus for USB2 port 4 done
959 12:40:46.439479 scan_bus: bus USB2 port 4 finished in 6 msecs
960 12:40:46.443083 USB3 port 1 scanning...
961 12:40:46.446667 scan_static_bus for USB3 port 1
962 12:40:46.449513 scan_static_bus for USB3 port 1 done
963 12:40:46.452678 scan_bus: bus USB3 port 1 finished in 6 msecs
964 12:40:46.459851 scan_static_bus for USB0 port 0 done
965 12:40:46.462921 scan_bus: bus USB0 port 0 finished in 93 msecs
966 12:40:46.465829 scan_static_bus for PCI: 00:14.0 done
967 12:40:46.472906 scan_bus: bus PCI: 00:14.0 finished in 109 msecs
968 12:40:46.473331 PCI: 00:14.3 scanning...
969 12:40:46.476049 scan_static_bus for PCI: 00:14.3
970 12:40:46.478953 GENERIC: 0.0 enabled
971 12:40:46.483080 scan_static_bus for PCI: 00:14.3 done
972 12:40:46.489270 scan_bus: bus PCI: 00:14.3 finished in 9 msecs
973 12:40:46.489791 PCI: 00:15.0 scanning...
974 12:40:46.492827 scan_static_bus for PCI: 00:15.0
975 12:40:46.496101 I2C: 00:1a enabled
976 12:40:46.499447 I2C: 00:31 enabled
977 12:40:46.499906 I2C: 00:32 enabled
978 12:40:46.502818 scan_static_bus for PCI: 00:15.0 done
979 12:40:46.509129 scan_bus: bus PCI: 00:15.0 finished in 12 msecs
980 12:40:46.512385 PCI: 00:15.1 scanning...
981 12:40:46.515715 scan_static_bus for PCI: 00:15.1
982 12:40:46.516154 I2C: 00:10 enabled
983 12:40:46.518994 scan_static_bus for PCI: 00:15.1 done
984 12:40:46.526108 scan_bus: bus PCI: 00:15.1 finished in 9 msecs
985 12:40:46.529351 PCI: 00:15.2 scanning...
986 12:40:46.532575 scan_static_bus for PCI: 00:15.2
987 12:40:46.535506 scan_static_bus for PCI: 00:15.2 done
988 12:40:46.539113 scan_bus: bus PCI: 00:15.2 finished in 7 msecs
989 12:40:46.542187 PCI: 00:15.3 scanning...
990 12:40:46.545332 scan_static_bus for PCI: 00:15.3
991 12:40:46.548754 scan_static_bus for PCI: 00:15.3 done
992 12:40:46.555271 scan_bus: bus PCI: 00:15.3 finished in 7 msecs
993 12:40:46.555708 PCI: 00:19.1 scanning...
994 12:40:46.558807 scan_static_bus for PCI: 00:19.1
995 12:40:46.562023 I2C: 00:15 enabled
996 12:40:46.565192 scan_static_bus for PCI: 00:19.1 done
997 12:40:46.571918 scan_bus: bus PCI: 00:19.1 finished in 9 msecs
998 12:40:46.572356 PCI: 00:1d.0 scanning...
999 12:40:46.578573 do_pci_scan_bridge for PCI: 00:1d.0
1000 12:40:46.579012 PCI: pci_scan_bus for bus 01
1001 12:40:46.581995 PCI: 01:00.0 [15b7/5009] enabled
1002 12:40:46.585320 GENERIC: 0.0 enabled
1003 12:40:46.588912 Enabling Common Clock Configuration
1004 12:40:46.595274 L1 Sub-State supported from root port 29
1005 12:40:46.595817 L1 Sub-State Support = 0x5
1006 12:40:46.598850 CommonModeRestoreTime = 0x28
1007 12:40:46.605525 Power On Value = 0x16, Power On Scale = 0x0
1008 12:40:46.606063 ASPM: Enabled L1
1009 12:40:46.608643 PCIe: Max_Payload_Size adjusted to 128
1010 12:40:46.615780 scan_bus: bus PCI: 00:1d.0 finished in 35 msecs
1011 12:40:46.616221 PCI: 00:1e.2 scanning...
1012 12:40:46.622151 scan_generic_bus for PCI: 00:1e.2
1013 12:40:46.622618 SPI: 00 enabled
1014 12:40:46.628806 bus: PCI: 00:1e.2[0]->scan_generic_bus for PCI: 00:1e.2 done
1015 12:40:46.632506 scan_bus: bus PCI: 00:1e.2 finished in 11 msecs
1016 12:40:46.635504 PCI: 00:1e.3 scanning...
1017 12:40:46.638507 scan_generic_bus for PCI: 00:1e.3
1018 12:40:46.642178 SPI: 00 enabled
1019 12:40:46.646513 bus: PCI: 00:1e.3[0]->scan_generic_bus for PCI: 00:1e.3 done
1020 12:40:46.653108 scan_bus: bus PCI: 00:1e.3 finished in 11 msecs
1021 12:40:46.653530 PCI: 00:1f.0 scanning...
1022 12:40:46.656397 scan_static_bus for PCI: 00:1f.0
1023 12:40:46.659542 PNP: 0c09.0 enabled
1024 12:40:46.662691 PNP: 0c09.0 scanning...
1025 12:40:46.665927 scan_static_bus for PNP: 0c09.0
1026 12:40:46.669497 scan_static_bus for PNP: 0c09.0 done
1027 12:40:46.673368 scan_bus: bus PNP: 0c09.0 finished in 6 msecs
1028 12:40:46.679691 scan_static_bus for PCI: 00:1f.0 done
1029 12:40:46.682896 scan_bus: bus PCI: 00:1f.0 finished in 23 msecs
1030 12:40:46.686292 PCI: 00:1f.2 scanning...
1031 12:40:46.689305 scan_static_bus for PCI: 00:1f.2
1032 12:40:46.689827 GENERIC: 0.0 enabled
1033 12:40:46.692478 GENERIC: 0.0 scanning...
1034 12:40:46.695793 scan_static_bus for GENERIC: 0.0
1035 12:40:46.698757 GENERIC: 0.0 enabled
1036 12:40:46.702154 GENERIC: 1.0 enabled
1037 12:40:46.705667 scan_static_bus for GENERIC: 0.0 done
1038 12:40:46.709238 scan_bus: bus GENERIC: 0.0 finished in 11 msecs
1039 12:40:46.712095 scan_static_bus for PCI: 00:1f.2 done
1040 12:40:46.718852 scan_bus: bus PCI: 00:1f.2 finished in 28 msecs
1041 12:40:46.722442 PCI: 00:1f.3 scanning...
1042 12:40:46.725527 scan_static_bus for PCI: 00:1f.3
1043 12:40:46.728642 scan_static_bus for PCI: 00:1f.3 done
1044 12:40:46.732538 scan_bus: bus PCI: 00:1f.3 finished in 7 msecs
1045 12:40:46.735598 PCI: 00:1f.5 scanning...
1046 12:40:46.738775 scan_generic_bus for PCI: 00:1f.5
1047 12:40:46.742445 scan_generic_bus for PCI: 00:1f.5 done
1048 12:40:46.749078 scan_bus: bus PCI: 00:1f.5 finished in 7 msecs
1049 12:40:46.752117 scan_bus: bus DOMAIN: 0000 finished in 716 msecs
1050 12:40:46.755674 scan_static_bus for Root Device done
1051 12:40:46.762318 scan_bus: bus Root Device finished in 735 msecs
1052 12:40:46.762917 done
1053 12:40:46.769065 BS: BS_DEV_ENUMERATE run times (exec / console): 10 / 1295 ms
1054 12:40:46.772444 Chrome EC: UHEPI supported
1055 12:40:46.778673 FMAP: area UNIFIED_MRC_CACHE found @ f00000 (196608 bytes)
1056 12:40:46.785488 SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
1057 12:40:46.789522 SPI flash protection: WPSW=0 SRP0=1
1058 12:40:46.792049 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
1059 12:40:46.798936 BS: BS_DEV_ENUMERATE exit times (exec / console): 2 / 23 ms
1060 12:40:46.802336 found VGA at PCI: 00:02.0
1061 12:40:46.805153 Setting up VGA for PCI: 00:02.0
1062 12:40:46.808824 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
1063 12:40:46.815228 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
1064 12:40:46.818505 Allocating resources...
1065 12:40:46.818781 Reading resources...
1066 12:40:46.821732 Root Device read_resources bus 0 link: 0
1067 12:40:46.828759 DOMAIN: 0000 read_resources bus 0 link: 0
1068 12:40:46.832262 PCI: 00:04.0 read_resources bus 1 link: 0
1069 12:40:46.838705 PCI: 00:04.0 read_resources bus 1 link: 0 done
1070 12:40:46.841950 PCI: 00:0d.0 read_resources bus 0 link: 0
1071 12:40:46.848231 USB0 port 0 read_resources bus 0 link: 0
1072 12:40:46.851931 USB0 port 0 read_resources bus 0 link: 0 done
1073 12:40:46.858483 PCI: 00:0d.0 read_resources bus 0 link: 0 done
1074 12:40:46.861814 PCI: 00:14.0 read_resources bus 0 link: 0
1075 12:40:46.865121 USB0 port 0 read_resources bus 0 link: 0
1076 12:40:46.872587 USB0 port 0 read_resources bus 0 link: 0 done
1077 12:40:46.875838 PCI: 00:14.0 read_resources bus 0 link: 0 done
1078 12:40:46.882605 PCI: 00:14.3 read_resources bus 0 link: 0
1079 12:40:46.886353 PCI: 00:14.3 read_resources bus 0 link: 0 done
1080 12:40:46.892742 PCI: 00:15.0 read_resources bus 0 link: 0
1081 12:40:46.896041 PCI: 00:15.0 read_resources bus 0 link: 0 done
1082 12:40:46.902930 PCI: 00:15.1 read_resources bus 0 link: 0
1083 12:40:46.905891 PCI: 00:15.1 read_resources bus 0 link: 0 done
1084 12:40:46.913271 PCI: 00:19.1 read_resources bus 0 link: 0
1085 12:40:46.916437 PCI: 00:19.1 read_resources bus 0 link: 0 done
1086 12:40:46.923077 PCI: 00:1d.0 read_resources bus 1 link: 0
1087 12:40:46.926378 PCI: 00:1d.0 read_resources bus 1 link: 0 done
1088 12:40:46.932205 PCI: 00:1e.2 read_resources bus 2 link: 0
1089 12:40:46.935567 PCI: 00:1e.2 read_resources bus 2 link: 0 done
1090 12:40:46.942444 PCI: 00:1e.3 read_resources bus 3 link: 0
1091 12:40:46.945792 PCI: 00:1e.3 read_resources bus 3 link: 0 done
1092 12:40:46.952859 PCI: 00:1f.0 read_resources bus 0 link: 0
1093 12:40:46.956320 PCI: 00:1f.0 read_resources bus 0 link: 0 done
1094 12:40:46.959255 PCI: 00:1f.2 read_resources bus 0 link: 0
1095 12:40:46.966410 GENERIC: 0.0 read_resources bus 0 link: 0
1096 12:40:46.969658 GENERIC: 0.0 read_resources bus 0 link: 0 done
1097 12:40:46.976261 PCI: 00:1f.2 read_resources bus 0 link: 0 done
1098 12:40:46.979839 DOMAIN: 0000 read_resources bus 0 link: 0 done
1099 12:40:46.986464 CPU_CLUSTER: 0 read_resources bus 0 link: 0
1100 12:40:46.989824 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
1101 12:40:46.996484 Root Device read_resources bus 0 link: 0 done
1102 12:40:47.000313 Done reading resources.
1103 12:40:47.003281 Show resources in subtree (Root Device)...After reading.
1104 12:40:47.009763 Root Device child on link 0 DOMAIN: 0000
1105 12:40:47.012587 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1106 12:40:47.023313 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1107 12:40:47.033081 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100
1108 12:40:47.033618 PCI: 00:00.0
1109 12:40:47.043466 PCI: 00:00.0 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1110 12:40:47.052970 PCI: 00:00.0 resource base fedc0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1
1111 12:40:47.062724 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1112 12:40:47.072388 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1113 12:40:47.078924 PCI: 00:00.0 resource base fb000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1114 12:40:47.088954 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1115 12:40:47.099070 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 6
1116 12:40:47.108921 PCI: 00:00.0 resource base fed92000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1117 12:40:47.119030 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1118 12:40:47.129044 PCI: 00:00.0 resource base fed85000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9
1119 12:40:47.135311 PCI: 00:00.0 resource base fed86000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
1120 12:40:47.145035 PCI: 00:00.0 resource base fed87000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b
1121 12:40:47.154856 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c
1122 12:40:47.165236 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index d
1123 12:40:47.174775 PCI: 00:00.0 resource base c0000 size 76f40000 align 0 gran 0 limit 0 flags e0004200 index e
1124 12:40:47.184594 PCI: 00:00.0 resource base 77000000 size 8c00000 align 0 gran 0 limit 0 flags f0000200 index f
1125 12:40:47.194363 PCI: 00:00.0 resource base 100000000 size 380400000 align 0 gran 0 limit 0 flags e0004200 index 10
1126 12:40:47.201313 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11
1127 12:40:47.211419 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12
1128 12:40:47.220999 PCI: 00:00.0 resource base f8000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 13
1129 12:40:47.224526 PCI: 00:02.0
1130 12:40:47.234197 PCI: 00:02.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1131 12:40:47.244009 PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
1132 12:40:47.250771 PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
1133 12:40:47.257455 PCI: 00:04.0 child on link 0 GENERIC: 0.0
1134 12:40:47.267250 PCI: 00:04.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 201 index 10
1135 12:40:47.267683 GENERIC: 0.0
1136 12:40:47.270660 PCI: 00:05.0
1137 12:40:47.280539 PCI: 00:05.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1138 12:40:47.283799 PCI: 00:07.0 child on link 0 GENERIC: 0.0
1139 12:40:47.286953 GENERIC: 0.0
1140 12:40:47.287381 PCI: 00:08.0
1141 12:40:47.296946 PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1142 12:40:47.300630 PCI: 00:0a.0
1143 12:40:47.303601 PCI: 00:0d.0 child on link 0 USB0 port 0
1144 12:40:47.313973 PCI: 00:0d.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1145 12:40:47.320389 USB0 port 0 child on link 0 USB3 port 0
1146 12:40:47.320822 USB3 port 0
1147 12:40:47.323388 USB3 port 1
1148 12:40:47.323817 USB3 port 2
1149 12:40:47.327234 USB3 port 3
1150 12:40:47.330362 PCI: 00:14.0 child on link 0 USB0 port 0
1151 12:40:47.340080 PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1152 12:40:47.343628 USB0 port 0 child on link 0 USB2 port 0
1153 12:40:47.346628 USB2 port 0
1154 12:40:47.347057 USB2 port 1
1155 12:40:47.350102 USB2 port 2
1156 12:40:47.353374 USB2 port 3
1157 12:40:47.353834 USB2 port 4
1158 12:40:47.357099 USB2 port 5
1159 12:40:47.357623 USB2 port 6
1160 12:40:47.360298 USB2 port 7
1161 12:40:47.360827 USB2 port 8
1162 12:40:47.363583 USB2 port 9
1163 12:40:47.364105 USB3 port 0
1164 12:40:47.366554 USB3 port 1
1165 12:40:47.366985 USB3 port 2
1166 12:40:47.370104 USB3 port 3
1167 12:40:47.370800 PCI: 00:14.2
1168 12:40:47.379812 PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1169 12:40:47.390396 PCI: 00:14.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
1170 12:40:47.396535 PCI: 00:14.3 child on link 0 GENERIC: 0.0
1171 12:40:47.406716 PCI: 00:14.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1172 12:40:47.407218 GENERIC: 0.0
1173 12:40:47.412875 PCI: 00:15.0 child on link 0 I2C: 00:1a
1174 12:40:47.423155 PCI: 00:15.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1175 12:40:47.423339 I2C: 00:1a
1176 12:40:47.423435 I2C: 00:31
1177 12:40:47.426305 I2C: 00:32
1178 12:40:47.429613 PCI: 00:15.1 child on link 0 I2C: 00:10
1179 12:40:47.439932 PCI: 00:15.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1180 12:40:47.443015 I2C: 00:10
1181 12:40:47.443229 PCI: 00:15.2
1182 12:40:47.452720 PCI: 00:15.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1183 12:40:47.455960 PCI: 00:15.3
1184 12:40:47.466402 PCI: 00:15.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1185 12:40:47.467007 PCI: 00:16.0
1186 12:40:47.476088 PCI: 00:16.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1187 12:40:47.479160 PCI: 00:19.0
1188 12:40:47.483057 PCI: 00:19.1 child on link 0 I2C: 00:15
1189 12:40:47.492581 PCI: 00:19.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1190 12:40:47.496350 I2C: 00:15
1191 12:40:47.499293 PCI: 00:1d.0 child on link 0 GENERIC: 0.0
1192 12:40:47.506612 PCI: 00:1d.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
1193 12:40:47.515939 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
1194 12:40:47.526124 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
1195 12:40:47.529209 GENERIC: 0.0
1196 12:40:47.529626 PCI: 01:00.0
1197 12:40:47.539421 PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1198 12:40:47.549208 PCI: 01:00.0 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 20
1199 12:40:47.552313 PCI: 00:1e.0
1200 12:40:47.562106 PCI: 00:1e.0 resource base fe03e000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1201 12:40:47.565517 PCI: 00:1e.2 child on link 0 SPI: 00
1202 12:40:47.575731 PCI: 00:1e.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1203 12:40:47.578827 SPI: 00
1204 12:40:47.582482 PCI: 00:1e.3 child on link 0 SPI: 00
1205 12:40:47.592371 PCI: 00:1e.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1206 12:40:47.592890 SPI: 00
1207 12:40:47.598770 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1208 12:40:47.605683 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1209 12:40:47.609276 PNP: 0c09.0
1210 12:40:47.615115 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1211 12:40:47.622274 PCI: 00:1f.2 child on link 0 GENERIC: 0.0
1212 12:40:47.632091 PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0
1213 12:40:47.638406 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1
1214 12:40:47.645269 GENERIC: 0.0 child on link 0 GENERIC: 0.0
1215 12:40:47.645709 GENERIC: 0.0
1216 12:40:47.648285 GENERIC: 1.0
1217 12:40:47.648695 PCI: 00:1f.3
1218 12:40:47.658864 PCI: 00:1f.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1219 12:40:47.668482 PCI: 00:1f.3 resource base 0 size 100000 align 20 gran 20 limit ffffffffffffffff flags 201 index 20
1220 12:40:47.671651 PCI: 00:1f.5
1221 12:40:47.682370 PCI: 00:1f.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
1222 12:40:47.685422 CPU_CLUSTER: 0 child on link 0 APIC: 00
1223 12:40:47.685937 APIC: 00
1224 12:40:47.689303 APIC: 01
1225 12:40:47.689846 APIC: 07
1226 12:40:47.690183 APIC: 03
1227 12:40:47.691917 APIC: 04
1228 12:40:47.692366 APIC: 06
1229 12:40:47.694935 APIC: 02
1230 12:40:47.695349 APIC: 05
1231 12:40:47.702042 ==== Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) ===
1232 12:40:47.708899 PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff
1233 12:40:47.715329 PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff done
1234 12:40:47.722118 PCI: 00:1d.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
1235 12:40:47.724981 PCI: 01:00.0 10 * [0x0 - 0x3fff] mem
1236 12:40:47.728628 PCI: 01:00.0 20 * [0x4000 - 0x40ff] mem
1237 12:40:47.735371 PCI: 00:1d.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
1238 12:40:47.745414 PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
1239 12:40:47.751287 PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
1240 12:40:47.758219 === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
1241 12:40:47.764968 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
1242 12:40:47.771325 update_constraints: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
1243 12:40:47.781536 update_constraints: PNP: 0c09.0 00 base 00000800 limit 000009fe io (fixed)
1244 12:40:47.788224 update_constraints: PCI: 00:1f.2 01 base 00001800 limit 000018ff io (fixed)
1245 12:40:47.791742 DOMAIN: 0000: Resource ranges:
1246 12:40:47.794466 * Base: 1000, Size: 800, Tag: 100
1247 12:40:47.797875 * Base: 1900, Size: e700, Tag: 100
1248 12:40:47.804660 PCI: 00:02.0 20 * [0x1000 - 0x103f] limit: 103f io
1249 12:40:47.811091 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
1250 12:40:47.817824 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff
1251 12:40:47.824787 update_constraints: PCI: 00:00.0 00 base c0000000 limit cfffffff mem (fixed)
1252 12:40:47.831156 update_constraints: PCI: 00:00.0 01 base fedc0000 limit feddffff mem (fixed)
1253 12:40:47.841343 update_constraints: PCI: 00:00.0 02 base feda0000 limit feda0fff mem (fixed)
1254 12:40:47.847765 update_constraints: PCI: 00:00.0 03 base feda1000 limit feda1fff mem (fixed)
1255 12:40:47.854532 update_constraints: PCI: 00:00.0 04 base fb000000 limit fb000fff mem (fixed)
1256 12:40:47.864201 update_constraints: PCI: 00:00.0 05 base fed80000 limit fed83fff mem (fixed)
1257 12:40:47.870935 update_constraints: PCI: 00:00.0 06 base fed90000 limit fed90fff mem (fixed)
1258 12:40:47.877278 update_constraints: PCI: 00:00.0 07 base fed92000 limit fed92fff mem (fixed)
1259 12:40:47.884062 update_constraints: PCI: 00:00.0 08 base fed84000 limit fed84fff mem (fixed)
1260 12:40:47.894024 update_constraints: PCI: 00:00.0 09 base fed85000 limit fed85fff mem (fixed)
1261 12:40:47.900488 update_constraints: PCI: 00:00.0 0a base fed86000 limit fed86fff mem (fixed)
1262 12:40:47.910930 update_constraints: PCI: 00:00.0 0b base fed87000 limit fed87fff mem (fixed)
1263 12:40:47.917246 update_constraints: PCI: 00:00.0 0c base fed91000 limit fed91fff mem (fixed)
1264 12:40:47.923832 update_constraints: PCI: 00:00.0 0d base 00000000 limit 0009ffff mem (fixed)
1265 12:40:47.933276 update_constraints: PCI: 00:00.0 0e base 000c0000 limit 76ffffff mem (fixed)
1266 12:40:47.940117 update_constraints: PCI: 00:00.0 0f base 77000000 limit 7fbfffff mem (fixed)
1267 12:40:47.946722 update_constraints: PCI: 00:00.0 10 base 100000000 limit 4803fffff mem (fixed)
1268 12:40:47.956500 update_constraints: PCI: 00:00.0 11 base 000a0000 limit 000bffff mem (fixed)
1269 12:40:47.963310 update_constraints: PCI: 00:00.0 12 base 000c0000 limit 000fffff mem (fixed)
1270 12:40:47.969669 update_constraints: PCI: 00:00.0 13 base f8000000 limit f9ffffff mem (fixed)
1271 12:40:47.980012 update_constraints: PCI: 00:1e.0 10 base fe03e000 limit fe03efff mem (fixed)
1272 12:40:47.986161 update_constraints: PCI: 00:1f.2 00 base fe000000 limit fe00ffff mem (fixed)
1273 12:40:47.989863 DOMAIN: 0000: Resource ranges:
1274 12:40:47.993312 * Base: 7fc00000, Size: 40400000, Tag: 200
1275 12:40:47.999490 * Base: d0000000, Size: 28000000, Tag: 200
1276 12:40:48.002981 * Base: fa000000, Size: 1000000, Tag: 200
1277 12:40:48.006223 * Base: fb001000, Size: 2fff000, Tag: 200
1278 12:40:48.009482 * Base: fe010000, Size: 2e000, Tag: 200
1279 12:40:48.016224 * Base: fe03f000, Size: d41000, Tag: 200
1280 12:40:48.019557 * Base: fed88000, Size: 8000, Tag: 200
1281 12:40:48.023062 * Base: fed93000, Size: d000, Tag: 200
1282 12:40:48.026369 * Base: feda2000, Size: 1e000, Tag: 200
1283 12:40:48.032764 * Base: fede0000, Size: 1220000, Tag: 200
1284 12:40:48.035726 * Base: 480400000, Size: 7b7fc00000, Tag: 100200
1285 12:40:48.042223 PCI: 00:02.0 18 * [0x80000000 - 0x8fffffff] limit: 8fffffff prefmem
1286 12:40:48.049152 PCI: 00:02.0 10 * [0x90000000 - 0x90ffffff] limit: 90ffffff mem
1287 12:40:48.055843 PCI: 00:05.0 10 * [0x91000000 - 0x91ffffff] limit: 91ffffff mem
1288 12:40:48.062228 PCI: 00:1d.0 20 * [0x7fc00000 - 0x7fcfffff] limit: 7fcfffff mem
1289 12:40:48.069007 PCI: 00:1f.3 20 * [0x7fd00000 - 0x7fdfffff] limit: 7fdfffff mem
1290 12:40:48.075730 PCI: 00:04.0 10 * [0x7fe00000 - 0x7fe1ffff] limit: 7fe1ffff mem
1291 12:40:48.082584 PCI: 00:0d.0 10 * [0x7fe20000 - 0x7fe2ffff] limit: 7fe2ffff mem
1292 12:40:48.088663 PCI: 00:14.0 10 * [0x7fe30000 - 0x7fe3ffff] limit: 7fe3ffff mem
1293 12:40:48.095456 PCI: 00:14.2 10 * [0x7fe40000 - 0x7fe43fff] limit: 7fe43fff mem
1294 12:40:48.101860 PCI: 00:14.3 10 * [0x7fe44000 - 0x7fe47fff] limit: 7fe47fff mem
1295 12:40:48.109072 PCI: 00:1f.3 10 * [0x7fe48000 - 0x7fe4bfff] limit: 7fe4bfff mem
1296 12:40:48.115552 PCI: 00:08.0 10 * [0x7fe4c000 - 0x7fe4cfff] limit: 7fe4cfff mem
1297 12:40:48.122292 PCI: 00:14.2 18 * [0x7fe4d000 - 0x7fe4dfff] limit: 7fe4dfff mem
1298 12:40:48.129008 PCI: 00:15.0 10 * [0x7fe4e000 - 0x7fe4efff] limit: 7fe4efff mem
1299 12:40:48.135564 PCI: 00:15.1 10 * [0x7fe4f000 - 0x7fe4ffff] limit: 7fe4ffff mem
1300 12:40:48.142173 PCI: 00:15.2 10 * [0x7fe50000 - 0x7fe50fff] limit: 7fe50fff mem
1301 12:40:48.148449 PCI: 00:15.3 10 * [0x7fe51000 - 0x7fe51fff] limit: 7fe51fff mem
1302 12:40:48.155039 PCI: 00:16.0 10 * [0x7fe52000 - 0x7fe52fff] limit: 7fe52fff mem
1303 12:40:48.161938 PCI: 00:19.1 10 * [0x7fe53000 - 0x7fe53fff] limit: 7fe53fff mem
1304 12:40:48.168624 PCI: 00:1e.2 10 * [0x7fe54000 - 0x7fe54fff] limit: 7fe54fff mem
1305 12:40:48.175215 PCI: 00:1e.3 10 * [0x7fe55000 - 0x7fe55fff] limit: 7fe55fff mem
1306 12:40:48.181790 PCI: 00:1f.5 10 * [0x7fe56000 - 0x7fe56fff] limit: 7fe56fff mem
1307 12:40:48.191846 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff done
1308 12:40:48.197984 PCI: 00:1d.0 mem: base: 7fc00000 size: 100000 align: 20 gran: 20 limit: 7fcfffff
1309 12:40:48.201498 PCI: 00:1d.0: Resource ranges:
1310 12:40:48.205081 * Base: 7fc00000, Size: 100000, Tag: 200
1311 12:40:48.211355 PCI: 01:00.0 10 * [0x7fc00000 - 0x7fc03fff] limit: 7fc03fff mem
1312 12:40:48.218253 PCI: 01:00.0 20 * [0x7fc04000 - 0x7fc040ff] limit: 7fc040ff mem
1313 12:40:48.228604 PCI: 00:1d.0 mem: base: 7fc00000 size: 100000 align: 20 gran: 20 limit: 7fcfffff done
1314 12:40:48.234689 === Resource allocator: DOMAIN: 0000 - resource allocation complete ===
1315 12:40:48.238055 Root Device assign_resources, bus 0 link: 0
1316 12:40:48.244641 DOMAIN: 0000 assign_resources, bus 0 link: 0
1317 12:40:48.251151 PCI: 00:02.0 10 <- [0x0090000000 - 0x0090ffffff] size 0x01000000 gran 0x18 mem64
1318 12:40:48.261663 PCI: 00:02.0 18 <- [0x0080000000 - 0x008fffffff] size 0x10000000 gran 0x1c prefmem64
1319 12:40:48.267959 PCI: 00:02.0 20 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io
1320 12:40:48.277657 PCI: 00:04.0 10 <- [0x007fe00000 - 0x007fe1ffff] size 0x00020000 gran 0x11 mem64
1321 12:40:48.281016 PCI: 00:04.0 assign_resources, bus 1 link: 0
1322 12:40:48.284286 PCI: 00:04.0 assign_resources, bus 1 link: 0
1323 12:40:48.294593 PCI: 00:05.0 10 <- [0x0091000000 - 0x0091ffffff] size 0x01000000 gran 0x18 mem64
1324 12:40:48.301516 PCI: 00:08.0 10 <- [0x007fe4c000 - 0x007fe4cfff] size 0x00001000 gran 0x0c mem64
1325 12:40:48.310930 PCI: 00:0d.0 10 <- [0x007fe20000 - 0x007fe2ffff] size 0x00010000 gran 0x10 mem64
1326 12:40:48.314386 PCI: 00:0d.0 assign_resources, bus 0 link: 0
1327 12:40:48.317849 PCI: 00:0d.0 assign_resources, bus 0 link: 0
1328 12:40:48.327663 PCI: 00:14.0 10 <- [0x007fe30000 - 0x007fe3ffff] size 0x00010000 gran 0x10 mem64
1329 12:40:48.331576 PCI: 00:14.0 assign_resources, bus 0 link: 0
1330 12:40:48.337587 PCI: 00:14.0 assign_resources, bus 0 link: 0
1331 12:40:48.344594 PCI: 00:14.2 10 <- [0x007fe40000 - 0x007fe43fff] size 0x00004000 gran 0x0e mem64
1332 12:40:48.354593 PCI: 00:14.2 18 <- [0x007fe4d000 - 0x007fe4dfff] size 0x00001000 gran 0x0c mem64
1333 12:40:48.361210 PCI: 00:14.3 10 <- [0x007fe44000 - 0x007fe47fff] size 0x00004000 gran 0x0e mem64
1334 12:40:48.364344 PCI: 00:14.3 assign_resources, bus 0 link: 0
1335 12:40:48.371110 PCI: 00:14.3 assign_resources, bus 0 link: 0
1336 12:40:48.377663 PCI: 00:15.0 10 <- [0x007fe4e000 - 0x007fe4efff] size 0x00001000 gran 0x0c mem64
1337 12:40:48.384121 PCI: 00:15.0 assign_resources, bus 0 link: 0
1338 12:40:48.387482 PCI: 00:15.0 assign_resources, bus 0 link: 0
1339 12:40:48.397568 PCI: 00:15.1 10 <- [0x007fe4f000 - 0x007fe4ffff] size 0x00001000 gran 0x0c mem64
1340 12:40:48.400853 PCI: 00:15.1 assign_resources, bus 0 link: 0
1341 12:40:48.404214 PCI: 00:15.1 assign_resources, bus 0 link: 0
1342 12:40:48.414055 PCI: 00:15.2 10 <- [0x007fe50000 - 0x007fe50fff] size 0x00001000 gran 0x0c mem64
1343 12:40:48.420638 PCI: 00:15.3 10 <- [0x007fe51000 - 0x007fe51fff] size 0x00001000 gran 0x0c mem64
1344 12:40:48.430494 PCI: 00:16.0 10 <- [0x007fe52000 - 0x007fe52fff] size 0x00001000 gran 0x0c mem64
1345 12:40:48.437354 PCI: 00:19.1 10 <- [0x007fe53000 - 0x007fe53fff] size 0x00001000 gran 0x0c mem64
1346 12:40:48.444145 PCI: 00:19.1 assign_resources, bus 0 link: 0
1347 12:40:48.447430 PCI: 00:19.1 assign_resources, bus 0 link: 0
1348 12:40:48.457167 PCI: 00:1d.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
1349 12:40:48.467115 PCI: 00:1d.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
1350 12:40:48.473973 PCI: 00:1d.0 20 <- [0x007fc00000 - 0x007fcfffff] size 0x00100000 gran 0x14 bus 01 mem
1351 12:40:48.480734 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1352 12:40:48.486842 PCI: 01:00.0 10 <- [0x007fc00000 - 0x007fc03fff] size 0x00004000 gran 0x0e mem64
1353 12:40:48.497125 PCI: 01:00.0 20 <- [0x007fc04000 - 0x007fc040ff] size 0x00000100 gran 0x08 mem64
1354 12:40:48.500424 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1355 12:40:48.510091 PCI: 00:1e.2 10 <- [0x007fe54000 - 0x007fe54fff] size 0x00001000 gran 0x0c mem64
1356 12:40:48.513479 PCI: 00:1e.2 assign_resources, bus 2 link: 0
1357 12:40:48.516777 PCI: 00:1e.2 assign_resources, bus 2 link: 0
1358 12:40:48.526391 PCI: 00:1e.3 10 <- [0x007fe55000 - 0x007fe55fff] size 0x00001000 gran 0x0c mem64
1359 12:40:48.530032 PCI: 00:1e.3 assign_resources, bus 3 link: 0
1360 12:40:48.536536 PCI: 00:1e.3 assign_resources, bus 3 link: 0
1361 12:40:48.539977 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1362 12:40:48.543146 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1363 12:40:48.550014 LPC: Trying to open IO window from 800 size 1ff
1364 12:40:48.556292 PCI: 00:1f.3 10 <- [0x007fe48000 - 0x007fe4bfff] size 0x00004000 gran 0x0e mem64
1365 12:40:48.566448 PCI: 00:1f.3 20 <- [0x007fd00000 - 0x007fdfffff] size 0x00100000 gran 0x14 mem64
1366 12:40:48.572857 PCI: 00:1f.5 10 <- [0x007fe56000 - 0x007fe56fff] size 0x00001000 gran 0x0c mem
1367 12:40:48.579973 DOMAIN: 0000 assign_resources, bus 0 link: 0
1368 12:40:48.582985 Root Device assign_resources, bus 0 link: 0
1369 12:40:48.586370 Done setting resources.
1370 12:40:48.593135 Show resources in subtree (Root Device)...After assigning values.
1371 12:40:48.596590 Root Device child on link 0 DOMAIN: 0000
1372 12:40:48.599702 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1373 12:40:48.609782 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1374 12:40:48.619604 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100
1375 12:40:48.622892 PCI: 00:00.0
1376 12:40:48.632975 PCI: 00:00.0 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1377 12:40:48.639376 PCI: 00:00.0 resource base fedc0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1
1378 12:40:48.649627 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1379 12:40:48.659318 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1380 12:40:48.669093 PCI: 00:00.0 resource base fb000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1381 12:40:48.678994 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1382 12:40:48.689458 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 6
1383 12:40:48.696236 PCI: 00:00.0 resource base fed92000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1384 12:40:48.705789 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1385 12:40:48.715738 PCI: 00:00.0 resource base fed85000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9
1386 12:40:48.725373 PCI: 00:00.0 resource base fed86000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
1387 12:40:48.735530 PCI: 00:00.0 resource base fed87000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b
1388 12:40:48.745801 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c
1389 12:40:48.751853 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index d
1390 12:40:48.762009 PCI: 00:00.0 resource base c0000 size 76f40000 align 0 gran 0 limit 0 flags e0004200 index e
1391 12:40:48.772465 PCI: 00:00.0 resource base 77000000 size 8c00000 align 0 gran 0 limit 0 flags f0000200 index f
1392 12:40:48.782050 PCI: 00:00.0 resource base 100000000 size 380400000 align 0 gran 0 limit 0 flags e0004200 index 10
1393 12:40:48.791875 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11
1394 12:40:48.801945 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12
1395 12:40:48.811996 PCI: 00:00.0 resource base f8000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 13
1396 12:40:48.812507 PCI: 00:02.0
1397 12:40:48.821285 PCI: 00:02.0 resource base 90000000 size 1000000 align 24 gran 24 limit 90ffffff flags 60000201 index 10
1398 12:40:48.835075 PCI: 00:02.0 resource base 80000000 size 10000000 align 28 gran 28 limit 8fffffff flags 60001201 index 18
1399 12:40:48.841798 PCI: 00:02.0 resource base 1000 size 40 align 6 gran 6 limit 103f flags 60000100 index 20
1400 12:40:48.847904 PCI: 00:04.0 child on link 0 GENERIC: 0.0
1401 12:40:48.858116 PCI: 00:04.0 resource base 7fe00000 size 20000 align 17 gran 17 limit 7fe1ffff flags 60000201 index 10
1402 12:40:48.858753 GENERIC: 0.0
1403 12:40:48.860986 PCI: 00:05.0
1404 12:40:48.870922 PCI: 00:05.0 resource base 91000000 size 1000000 align 24 gran 24 limit 91ffffff flags 60000201 index 10
1405 12:40:48.874163 PCI: 00:07.0 child on link 0 GENERIC: 0.0
1406 12:40:48.878006 GENERIC: 0.0
1407 12:40:48.878612 PCI: 00:08.0
1408 12:40:48.891165 PCI: 00:08.0 resource base 7fe4c000 size 1000 align 12 gran 12 limit 7fe4cfff flags 60000201 index 10
1409 12:40:48.891589 PCI: 00:0a.0
1410 12:40:48.894769 PCI: 00:0d.0 child on link 0 USB0 port 0
1411 12:40:48.907443 PCI: 00:0d.0 resource base 7fe20000 size 10000 align 16 gran 16 limit 7fe2ffff flags 60000201 index 10
1412 12:40:48.911081 USB0 port 0 child on link 0 USB3 port 0
1413 12:40:48.911496 USB3 port 0
1414 12:40:48.914459 USB3 port 1
1415 12:40:48.914877 USB3 port 2
1416 12:40:48.917391 USB3 port 3
1417 12:40:48.920858 PCI: 00:14.0 child on link 0 USB0 port 0
1418 12:40:48.934141 PCI: 00:14.0 resource base 7fe30000 size 10000 align 16 gran 16 limit 7fe3ffff flags 60000201 index 10
1419 12:40:48.937640 USB0 port 0 child on link 0 USB2 port 0
1420 12:40:48.938169 USB2 port 0
1421 12:40:48.940944 USB2 port 1
1422 12:40:48.941359 USB2 port 2
1423 12:40:48.943886 USB2 port 3
1424 12:40:48.947697 USB2 port 4
1425 12:40:48.948221 USB2 port 5
1426 12:40:48.950757 USB2 port 6
1427 12:40:48.951285 USB2 port 7
1428 12:40:48.954397 USB2 port 8
1429 12:40:48.954858 USB2 port 9
1430 12:40:48.957489 USB3 port 0
1431 12:40:48.957905 USB3 port 1
1432 12:40:48.960612 USB3 port 2
1433 12:40:48.961031 USB3 port 3
1434 12:40:48.964188 PCI: 00:14.2
1435 12:40:48.973590 PCI: 00:14.2 resource base 7fe40000 size 4000 align 14 gran 14 limit 7fe43fff flags 60000201 index 10
1436 12:40:48.983849 PCI: 00:14.2 resource base 7fe4d000 size 1000 align 12 gran 12 limit 7fe4dfff flags 60000201 index 18
1437 12:40:48.986923 PCI: 00:14.3 child on link 0 GENERIC: 0.0
1438 12:40:49.000464 PCI: 00:14.3 resource base 7fe44000 size 4000 align 14 gran 14 limit 7fe47fff flags 60000201 index 10
1439 12:40:49.000902 GENERIC: 0.0
1440 12:40:49.004107 PCI: 00:15.0 child on link 0 I2C: 00:1a
1441 12:40:49.013535 PCI: 00:15.0 resource base 7fe4e000 size 1000 align 12 gran 12 limit 7fe4efff flags 60000201 index 10
1442 12:40:49.016804 I2C: 00:1a
1443 12:40:49.017228 I2C: 00:31
1444 12:40:49.020218 I2C: 00:32
1445 12:40:49.023438 PCI: 00:15.1 child on link 0 I2C: 00:10
1446 12:40:49.033208 PCI: 00:15.1 resource base 7fe4f000 size 1000 align 12 gran 12 limit 7fe4ffff flags 60000201 index 10
1447 12:40:49.036322 I2C: 00:10
1448 12:40:49.036413 PCI: 00:15.2
1449 12:40:49.046215 PCI: 00:15.2 resource base 7fe50000 size 1000 align 12 gran 12 limit 7fe50fff flags 60000201 index 10
1450 12:40:49.050296 PCI: 00:15.3
1451 12:40:49.059864 PCI: 00:15.3 resource base 7fe51000 size 1000 align 12 gran 12 limit 7fe51fff flags 60000201 index 10
1452 12:40:49.060055 PCI: 00:16.0
1453 12:40:49.073199 PCI: 00:16.0 resource base 7fe52000 size 1000 align 12 gran 12 limit 7fe52fff flags 60000201 index 10
1454 12:40:49.073475 PCI: 00:19.0
1455 12:40:49.076459 PCI: 00:19.1 child on link 0 I2C: 00:15
1456 12:40:49.089856 PCI: 00:19.1 resource base 7fe53000 size 1000 align 12 gran 12 limit 7fe53fff flags 60000201 index 10
1457 12:40:49.090274 I2C: 00:15
1458 12:40:49.093470 PCI: 00:1d.0 child on link 0 GENERIC: 0.0
1459 12:40:49.103773 PCI: 00:1d.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 20080102 index 1c
1460 12:40:49.116577 PCI: 00:1d.0 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24
1461 12:40:49.126531 PCI: 00:1d.0 resource base 7fc00000 size 100000 align 20 gran 20 limit 7fcfffff flags 60080202 index 20
1462 12:40:49.127043 GENERIC: 0.0
1463 12:40:49.129601 PCI: 01:00.0
1464 12:40:49.139640 PCI: 01:00.0 resource base 7fc00000 size 4000 align 14 gran 14 limit 7fc03fff flags 60000201 index 10
1465 12:40:49.149910 PCI: 01:00.0 resource base 7fc04000 size 100 align 12 gran 8 limit 7fc040ff flags 60000201 index 20
1466 12:40:49.153325 PCI: 00:1e.0
1467 12:40:49.162820 PCI: 00:1e.0 resource base fe03e000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1468 12:40:49.166117 PCI: 00:1e.2 child on link 0 SPI: 00
1469 12:40:49.176441 PCI: 00:1e.2 resource base 7fe54000 size 1000 align 12 gran 12 limit 7fe54fff flags 60000201 index 10
1470 12:40:49.179494 SPI: 00
1471 12:40:49.183037 PCI: 00:1e.3 child on link 0 SPI: 00
1472 12:40:49.192924 PCI: 00:1e.3 resource base 7fe55000 size 1000 align 12 gran 12 limit 7fe55fff flags 60000201 index 10
1473 12:40:49.193397 SPI: 00
1474 12:40:49.199279 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1475 12:40:49.206140 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1476 12:40:49.209107 PNP: 0c09.0
1477 12:40:49.215745 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1478 12:40:49.222846 PCI: 00:1f.2 child on link 0 GENERIC: 0.0
1479 12:40:49.232868 PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0
1480 12:40:49.240000 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1
1481 12:40:49.245904 GENERIC: 0.0 child on link 0 GENERIC: 0.0
1482 12:40:49.246580 GENERIC: 0.0
1483 12:40:49.249211 GENERIC: 1.0
1484 12:40:49.249623 PCI: 00:1f.3
1485 12:40:49.262538 PCI: 00:1f.3 resource base 7fe48000 size 4000 align 14 gran 14 limit 7fe4bfff flags 60000201 index 10
1486 12:40:49.272292 PCI: 00:1f.3 resource base 7fd00000 size 100000 align 20 gran 20 limit 7fdfffff flags 60000201 index 20
1487 12:40:49.272971 PCI: 00:1f.5
1488 12:40:49.282294 PCI: 00:1f.5 resource base 7fe56000 size 1000 align 12 gran 12 limit 7fe56fff flags 60000200 index 10
1489 12:40:49.288974 CPU_CLUSTER: 0 child on link 0 APIC: 00
1490 12:40:49.289394 APIC: 00
1491 12:40:49.289719 APIC: 01
1492 12:40:49.292139 APIC: 07
1493 12:40:49.292555 APIC: 03
1494 12:40:49.295362 APIC: 04
1495 12:40:49.295792 APIC: 06
1496 12:40:49.296120 APIC: 02
1497 12:40:49.299323 APIC: 05
1498 12:40:49.299796 Done allocating resources.
1499 12:40:49.305535 BS: BS_DEV_RESOURCES run times (exec / console): 27 / 2475 ms
1500 12:40:49.311978 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
1501 12:40:49.315523 Configure GPIOs for I2S audio on UP4.
1502 12:40:49.322818 BS: BS_DEV_ENABLE entry times (exec / console): 2 / 9 ms
1503 12:40:49.326332 Enabling resources...
1504 12:40:49.329329 PCI: 00:00.0 subsystem <- 8086/9a12
1505 12:40:49.332761 PCI: 00:00.0 cmd <- 06
1506 12:40:49.336089 PCI: 00:02.0 subsystem <- 8086/9a40
1507 12:40:49.339594 PCI: 00:02.0 cmd <- 03
1508 12:40:49.342794 PCI: 00:04.0 subsystem <- 8086/9a03
1509 12:40:49.343229 PCI: 00:04.0 cmd <- 02
1510 12:40:49.349496 PCI: 00:05.0 subsystem <- 8086/9a19
1511 12:40:49.349978 PCI: 00:05.0 cmd <- 02
1512 12:40:49.352779 PCI: 00:08.0 subsystem <- 8086/9a11
1513 12:40:49.356144 PCI: 00:08.0 cmd <- 06
1514 12:40:49.359784 PCI: 00:0d.0 subsystem <- 8086/9a13
1515 12:40:49.363058 PCI: 00:0d.0 cmd <- 02
1516 12:40:49.366540 PCI: 00:14.0 subsystem <- 8086/a0ed
1517 12:40:49.369594 PCI: 00:14.0 cmd <- 02
1518 12:40:49.372947 PCI: 00:14.2 subsystem <- 8086/a0ef
1519 12:40:49.376108 PCI: 00:14.2 cmd <- 02
1520 12:40:49.379332 PCI: 00:14.3 subsystem <- 8086/a0f0
1521 12:40:49.383246 PCI: 00:14.3 cmd <- 02
1522 12:40:49.386277 PCI: 00:15.0 subsystem <- 8086/a0e8
1523 12:40:49.389526 PCI: 00:15.0 cmd <- 02
1524 12:40:49.392609 PCI: 00:15.1 subsystem <- 8086/a0e9
1525 12:40:49.393025 PCI: 00:15.1 cmd <- 02
1526 12:40:49.399448 PCI: 00:15.2 subsystem <- 8086/a0ea
1527 12:40:49.399928 PCI: 00:15.2 cmd <- 02
1528 12:40:49.402739 PCI: 00:15.3 subsystem <- 8086/a0eb
1529 12:40:49.406091 PCI: 00:15.3 cmd <- 02
1530 12:40:49.409544 PCI: 00:16.0 subsystem <- 8086/a0e0
1531 12:40:49.412743 PCI: 00:16.0 cmd <- 02
1532 12:40:49.415523 PCI: 00:19.1 subsystem <- 8086/a0c6
1533 12:40:49.419423 PCI: 00:19.1 cmd <- 02
1534 12:40:49.422512 PCI: 00:1d.0 bridge ctrl <- 0013
1535 12:40:49.425522 PCI: 00:1d.0 subsystem <- 8086/a0b0
1536 12:40:49.429459 PCI: 00:1d.0 cmd <- 06
1537 12:40:49.432438 PCI: 00:1e.0 subsystem <- 8086/a0a8
1538 12:40:49.435812 PCI: 00:1e.0 cmd <- 06
1539 12:40:49.439388 PCI: 00:1e.2 subsystem <- 8086/a0aa
1540 12:40:49.442312 PCI: 00:1e.2 cmd <- 06
1541 12:40:49.445570 PCI: 00:1e.3 subsystem <- 8086/a0ab
1542 12:40:49.446079 PCI: 00:1e.3 cmd <- 02
1543 12:40:49.452943 PCI: 00:1f.0 subsystem <- 8086/a087
1544 12:40:49.453596 PCI: 00:1f.0 cmd <- 407
1545 12:40:49.455332 PCI: 00:1f.3 subsystem <- 8086/a0c8
1546 12:40:49.458494 PCI: 00:1f.3 cmd <- 02
1547 12:40:49.462286 PCI: 00:1f.5 subsystem <- 8086/a0a4
1548 12:40:49.465231 PCI: 00:1f.5 cmd <- 406
1549 12:40:49.470076 PCI: 01:00.0 cmd <- 02
1550 12:40:49.474341 done.
1551 12:40:49.477996 BS: BS_DEV_ENABLE run times (exec / console): 10 / 140 ms
1552 12:40:49.481147 Initializing devices...
1553 12:40:49.484173 Root Device init
1554 12:40:49.487433 Chrome EC: Set SMI mask to 0x0000000000000000
1555 12:40:49.494126 Chrome EC: clear events_b mask to 0x0000000000000000
1556 12:40:49.501217 Chrome EC: Set S5 LAZY WAKE mask to 0x0000000000000006
1557 12:40:49.507442 Chrome EC: Set S3 LAZY WAKE mask to 0x000000001800101e
1558 12:40:49.514385 Chrome EC: Set S0iX LAZY WAKE mask to 0x000000001800101e
1559 12:40:49.517691 Chrome EC: Set WAKE mask to 0x0000000000000000
1560 12:40:49.525262 fw_config match found: DB_USB=USB3_ACTIVE
1561 12:40:49.528208 Configure Right Type-C port orientation for retimer
1562 12:40:49.531364 Root Device init finished in 45 msecs
1563 12:40:49.535824 PCI: 00:00.0 init
1564 12:40:49.539023 CPU TDP = 9 Watts
1565 12:40:49.539400 CPU PL1 = 9 Watts
1566 12:40:49.542237 CPU PL2 = 40 Watts
1567 12:40:49.545128 CPU PL4 = 83 Watts
1568 12:40:49.548963 PCI: 00:00.0 init finished in 8 msecs
1569 12:40:49.549478 PCI: 00:02.0 init
1570 12:40:49.552893 GMA: Found VBT in CBFS
1571 12:40:49.555369 GMA: Found valid VBT in CBFS
1572 12:40:49.562214 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
1573 12:40:49.569034 x_res x y_res: 1920 x 1080, size: 8294400 at 0x80000000
1574 12:40:49.573048 PCI: 00:02.0 init finished in 18 msecs
1575 12:40:49.575138 PCI: 00:05.0 init
1576 12:40:49.578351 PCI: 00:05.0 init finished in 0 msecs
1577 12:40:49.581869 PCI: 00:08.0 init
1578 12:40:49.584975 PCI: 00:08.0 init finished in 0 msecs
1579 12:40:49.588435 PCI: 00:14.0 init
1580 12:40:49.591482 PCI: 00:14.0 init finished in 0 msecs
1581 12:40:49.594921 PCI: 00:14.2 init
1582 12:40:49.598412 PCI: 00:14.2 init finished in 0 msecs
1583 12:40:49.601928 PCI: 00:15.0 init
1584 12:40:49.602337 I2C bus 0 version 0x3230302a
1585 12:40:49.608561 DW I2C bus 0 at 0x7fe4e000 (400 KHz)
1586 12:40:49.611549 PCI: 00:15.0 init finished in 6 msecs
1587 12:40:49.612091 PCI: 00:15.1 init
1588 12:40:49.614817 I2C bus 1 version 0x3230302a
1589 12:40:49.618089 DW I2C bus 1 at 0x7fe4f000 (400 KHz)
1590 12:40:49.625312 PCI: 00:15.1 init finished in 6 msecs
1591 12:40:49.625720 PCI: 00:15.2 init
1592 12:40:49.628358 I2C bus 2 version 0x3230302a
1593 12:40:49.631413 DW I2C bus 2 at 0x7fe50000 (400 KHz)
1594 12:40:49.635317 PCI: 00:15.2 init finished in 6 msecs
1595 12:40:49.638183 PCI: 00:15.3 init
1596 12:40:49.641437 I2C bus 3 version 0x3230302a
1597 12:40:49.644689 DW I2C bus 3 at 0x7fe51000 (400 KHz)
1598 12:40:49.648709 PCI: 00:15.3 init finished in 6 msecs
1599 12:40:49.651691 PCI: 00:16.0 init
1600 12:40:49.655234 PCI: 00:16.0 init finished in 0 msecs
1601 12:40:49.658077 PCI: 00:19.1 init
1602 12:40:49.661709 I2C bus 5 version 0x3230302a
1603 12:40:49.664940 DW I2C bus 5 at 0x7fe53000 (400 KHz)
1604 12:40:49.668162 PCI: 00:19.1 init finished in 6 msecs
1605 12:40:49.671328 PCI: 00:1d.0 init
1606 12:40:49.671762 Initializing PCH PCIe bridge.
1607 12:40:49.678269 PCI: 00:1d.0 init finished in 3 msecs
1608 12:40:49.681256 PCI: 00:1f.0 init
1609 12:40:49.684846 IOAPIC: Initializing IOAPIC at 0xfec00000
1610 12:40:49.688115 IOAPIC: Bootstrap Processor Local APIC = 0x00
1611 12:40:49.691340 IOAPIC: ID = 0x02
1612 12:40:49.694506 IOAPIC: Dumping registers
1613 12:40:49.694916 reg 0x0000: 0x02000000
1614 12:40:49.698411 reg 0x0001: 0x00770020
1615 12:40:49.701088 reg 0x0002: 0x00000000
1616 12:40:49.704595 PCI: 00:1f.0 init finished in 21 msecs
1617 12:40:49.708108 PCI: 00:1f.2 init
1618 12:40:49.708518 Disabling ACPI via APMC.
1619 12:40:49.713009 APMC done.
1620 12:40:49.715670 PCI: 00:1f.2 init finished in 5 msecs
1621 12:40:49.727079 PCI: 01:00.0 init
1622 12:40:49.730404 PCI: 01:00.0 init finished in 0 msecs
1623 12:40:49.733738 PNP: 0c09.0 init
1624 12:40:49.737007 Google Chrome EC uptime: 8.246 seconds
1625 12:40:49.743760 Google Chrome AP resets since EC boot: 1
1626 12:40:49.746774 Google Chrome most recent AP reset causes:
1627 12:40:49.750304 0.451: 32775 shutdown: entering G3
1628 12:40:49.756818 Google Chrome EC reset flags at last EC boot: reset-pin | sysjump
1629 12:40:49.760266 PNP: 0c09.0 init finished in 22 msecs
1630 12:40:49.765277 Devices initialized
1631 12:40:49.769210 Show all devs... After init.
1632 12:40:49.771864 Root Device: enabled 1
1633 12:40:49.772313 DOMAIN: 0000: enabled 1
1634 12:40:49.775141 CPU_CLUSTER: 0: enabled 1
1635 12:40:49.778569 PCI: 00:00.0: enabled 1
1636 12:40:49.782188 PCI: 00:02.0: enabled 1
1637 12:40:49.782659 PCI: 00:04.0: enabled 1
1638 12:40:49.785257 PCI: 00:05.0: enabled 1
1639 12:40:49.788651 PCI: 00:06.0: enabled 0
1640 12:40:49.791958 PCI: 00:07.0: enabled 0
1641 12:40:49.792376 PCI: 00:07.1: enabled 0
1642 12:40:49.795201 PCI: 00:07.2: enabled 0
1643 12:40:49.798894 PCI: 00:07.3: enabled 0
1644 12:40:49.801651 PCI: 00:08.0: enabled 1
1645 12:40:49.802071 PCI: 00:09.0: enabled 0
1646 12:40:49.805246 PCI: 00:0a.0: enabled 0
1647 12:40:49.808663 PCI: 00:0d.0: enabled 1
1648 12:40:49.811912 PCI: 00:0d.1: enabled 0
1649 12:40:49.812332 PCI: 00:0d.2: enabled 0
1650 12:40:49.815126 PCI: 00:0d.3: enabled 0
1651 12:40:49.818732 PCI: 00:0e.0: enabled 0
1652 12:40:49.819200 PCI: 00:10.2: enabled 1
1653 12:40:49.821688 PCI: 00:10.6: enabled 0
1654 12:40:49.825009 PCI: 00:10.7: enabled 0
1655 12:40:49.828268 PCI: 00:12.0: enabled 0
1656 12:40:49.828685 PCI: 00:12.6: enabled 0
1657 12:40:49.831814 PCI: 00:13.0: enabled 0
1658 12:40:49.835000 PCI: 00:14.0: enabled 1
1659 12:40:49.838200 PCI: 00:14.1: enabled 0
1660 12:40:49.838726 PCI: 00:14.2: enabled 1
1661 12:40:49.841311 PCI: 00:14.3: enabled 1
1662 12:40:49.845034 PCI: 00:15.0: enabled 1
1663 12:40:49.848579 PCI: 00:15.1: enabled 1
1664 12:40:49.848999 PCI: 00:15.2: enabled 1
1665 12:40:49.851419 PCI: 00:15.3: enabled 1
1666 12:40:49.854481 PCI: 00:16.0: enabled 1
1667 12:40:49.858510 PCI: 00:16.1: enabled 0
1668 12:40:49.858993 PCI: 00:16.2: enabled 0
1669 12:40:49.861335 PCI: 00:16.3: enabled 0
1670 12:40:49.864688 PCI: 00:16.4: enabled 0
1671 12:40:49.865155 PCI: 00:16.5: enabled 0
1672 12:40:49.868311 PCI: 00:17.0: enabled 0
1673 12:40:49.871574 PCI: 00:19.0: enabled 0
1674 12:40:49.874877 PCI: 00:19.1: enabled 1
1675 12:40:49.875294 PCI: 00:19.2: enabled 0
1676 12:40:49.878535 PCI: 00:1c.0: enabled 1
1677 12:40:49.881495 PCI: 00:1c.1: enabled 0
1678 12:40:49.884976 PCI: 00:1c.2: enabled 0
1679 12:40:49.885550 PCI: 00:1c.3: enabled 0
1680 12:40:49.887716 PCI: 00:1c.4: enabled 0
1681 12:40:49.891407 PCI: 00:1c.5: enabled 0
1682 12:40:49.894660 PCI: 00:1c.6: enabled 1
1683 12:40:49.895269 PCI: 00:1c.7: enabled 0
1684 12:40:49.897897 PCI: 00:1d.0: enabled 1
1685 12:40:49.901058 PCI: 00:1d.1: enabled 0
1686 12:40:49.904226 PCI: 00:1d.2: enabled 1
1687 12:40:49.904833 PCI: 00:1d.3: enabled 0
1688 12:40:49.907996 PCI: 00:1e.0: enabled 1
1689 12:40:49.911011 PCI: 00:1e.1: enabled 0
1690 12:40:49.914698 PCI: 00:1e.2: enabled 1
1691 12:40:49.915312 PCI: 00:1e.3: enabled 1
1692 12:40:49.917681 PCI: 00:1f.0: enabled 1
1693 12:40:49.920905 PCI: 00:1f.1: enabled 0
1694 12:40:49.921467 PCI: 00:1f.2: enabled 1
1695 12:40:49.924229 PCI: 00:1f.3: enabled 1
1696 12:40:49.927886 PCI: 00:1f.4: enabled 0
1697 12:40:49.931158 PCI: 00:1f.5: enabled 1
1698 12:40:49.931610 PCI: 00:1f.6: enabled 0
1699 12:40:49.934353 PCI: 00:1f.7: enabled 0
1700 12:40:49.937638 APIC: 00: enabled 1
1701 12:40:49.938146 GENERIC: 0.0: enabled 1
1702 12:40:49.940828 GENERIC: 0.0: enabled 1
1703 12:40:49.944080 GENERIC: 1.0: enabled 1
1704 12:40:49.948264 GENERIC: 0.0: enabled 1
1705 12:40:49.948769 GENERIC: 1.0: enabled 1
1706 12:40:49.950799 USB0 port 0: enabled 1
1707 12:40:49.954188 GENERIC: 0.0: enabled 1
1708 12:40:49.957619 USB0 port 0: enabled 1
1709 12:40:49.958066 GENERIC: 0.0: enabled 1
1710 12:40:49.960782 I2C: 00:1a: enabled 1
1711 12:40:49.964415 I2C: 00:31: enabled 1
1712 12:40:49.964826 I2C: 00:32: enabled 1
1713 12:40:49.967426 I2C: 00:10: enabled 1
1714 12:40:49.971005 I2C: 00:15: enabled 1
1715 12:40:49.971412 GENERIC: 0.0: enabled 0
1716 12:40:49.974141 GENERIC: 1.0: enabled 0
1717 12:40:49.977646 GENERIC: 0.0: enabled 1
1718 12:40:49.978158 SPI: 00: enabled 1
1719 12:40:49.980489 SPI: 00: enabled 1
1720 12:40:49.984177 PNP: 0c09.0: enabled 1
1721 12:40:49.987977 GENERIC: 0.0: enabled 1
1722 12:40:49.988490 USB3 port 0: enabled 1
1723 12:40:49.991131 USB3 port 1: enabled 1
1724 12:40:49.994341 USB3 port 2: enabled 0
1725 12:40:49.994820 USB3 port 3: enabled 0
1726 12:40:49.997556 USB2 port 0: enabled 0
1727 12:40:50.000826 USB2 port 1: enabled 1
1728 12:40:50.001345 USB2 port 2: enabled 1
1729 12:40:50.004496 USB2 port 3: enabled 0
1730 12:40:50.007370 USB2 port 4: enabled 1
1731 12:40:50.010160 USB2 port 5: enabled 0
1732 12:40:50.010253 USB2 port 6: enabled 0
1733 12:40:50.013776 USB2 port 7: enabled 0
1734 12:40:50.017067 USB2 port 8: enabled 0
1735 12:40:50.017170 USB2 port 9: enabled 0
1736 12:40:50.020071 USB3 port 0: enabled 0
1737 12:40:50.024024 USB3 port 1: enabled 1
1738 12:40:50.026782 USB3 port 2: enabled 0
1739 12:40:50.026912 USB3 port 3: enabled 0
1740 12:40:50.030499 GENERIC: 0.0: enabled 1
1741 12:40:50.034084 GENERIC: 1.0: enabled 1
1742 12:40:50.034828 APIC: 01: enabled 1
1743 12:40:50.037570 APIC: 07: enabled 1
1744 12:40:50.040313 APIC: 03: enabled 1
1745 12:40:50.040748 APIC: 04: enabled 1
1746 12:40:50.043576 APIC: 06: enabled 1
1747 12:40:50.043997 APIC: 02: enabled 1
1748 12:40:50.047157 APIC: 05: enabled 1
1749 12:40:50.050557 PCI: 01:00.0: enabled 1
1750 12:40:50.053720 BS: BS_DEV_INIT run times (exec / console): 30 / 540 ms
1751 12:40:50.060711 FMAP: area RW_ELOG found @ f30000 (4096 bytes)
1752 12:40:50.063986 ELOG: NV offset 0xf30000 size 0x1000
1753 12:40:50.070493 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
1754 12:40:50.077705 ELOG: Event(17) added with size 13 at 2023-08-30 12:40:46 UTC
1755 12:40:50.083906 ELOG: Event(92) added with size 9 at 2023-08-30 12:40:46 UTC
1756 12:40:50.090597 ELOG: Event(93) added with size 9 at 2023-08-30 12:40:46 UTC
1757 12:40:50.097469 ELOG: Event(9E) added with size 10 at 2023-08-30 12:40:46 UTC
1758 12:40:50.103865 ELOG: Event(9F) added with size 14 at 2023-08-30 12:40:46 UTC
1759 12:40:50.110030 BS: BS_DEV_INIT exit times (exec / console): 3 / 45 ms
1760 12:40:50.113645 ELOG: Event(A1) added with size 10 at 2023-08-30 12:40:46 UTC
1761 12:40:50.123295 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
1762 12:40:50.130316 ELOG: Event(A0) added with size 9 at 2023-08-30 12:40:46 UTC
1763 12:40:50.133962 elog_add_boot_reason: Logged dev mode boot
1764 12:40:50.140352 BS: BS_POST_DEVICE entry times (exec / console): 1 / 24 ms
1765 12:40:50.140955 Finalize devices...
1766 12:40:50.143340 Devices finalized
1767 12:40:50.150250 BS: BS_POST_DEVICE run times (exec / console): 0 / 4 ms
1768 12:40:50.153445 FMAP: area RW_NVRAM found @ f37000 (24576 bytes)
1769 12:40:50.160102 BS: BS_POST_DEVICE exit times (exec / console): 0 / 5 ms
1770 12:40:50.163434 ME: HFSTS1 : 0x80030055
1771 12:40:50.170072 ME: HFSTS2 : 0x30280116
1772 12:40:50.173109 ME: HFSTS3 : 0x00000050
1773 12:40:50.176759 ME: HFSTS4 : 0x00004000
1774 12:40:50.183458 ME: HFSTS5 : 0x00000000
1775 12:40:50.186343 ME: HFSTS6 : 0x40400006
1776 12:40:50.189702 ME: Manufacturing Mode : YES
1777 12:40:50.193445 ME: SPI Protection Mode Enabled : NO
1778 12:40:50.196624 ME: FW Partition Table : OK
1779 12:40:50.203103 ME: Bringup Loader Failure : NO
1780 12:40:50.206272 ME: Firmware Init Complete : NO
1781 12:40:50.209765 ME: Boot Options Present : NO
1782 12:40:50.213319 ME: Update In Progress : NO
1783 12:40:50.216282 ME: D0i3 Support : YES
1784 12:40:50.219658 ME: Low Power State Enabled : NO
1785 12:40:50.223250 ME: CPU Replaced : YES
1786 12:40:50.226545 ME: CPU Replacement Valid : YES
1787 12:40:50.233216 ME: Current Working State : 5
1788 12:40:50.236205 ME: Current Operation State : 1
1789 12:40:50.239469 ME: Current Operation Mode : 3
1790 12:40:50.242988 ME: Error Code : 0
1791 12:40:50.245943 ME: Enhanced Debug Mode : NO
1792 12:40:50.249905 ME: CPU Debug Disabled : YES
1793 12:40:50.253014 ME: TXT Support : NO
1794 12:40:50.260147 BS: BS_OS_RESUME_CHECK exit times (exec / console): 0 / 94 ms
1795 12:40:50.266192 CBFS: Found 'fallback/dsdt.aml' @0x72f80 size 0x5a67 in mcache @0x76c4c1c4
1796 12:40:50.269447 CBFS: 'fallback/slic' not found.
1797 12:40:50.276420 ACPI: Writing ACPI tables at 76b01000.
1798 12:40:50.276933 ACPI: * FACS
1799 12:40:50.279956 ACPI: * DSDT
1800 12:40:50.282936 Ramoops buffer: 0x100000@0x76a00000.
1801 12:40:50.285881 FMAP: area RO_VPD found @ 1800000 (16384 bytes)
1802 12:40:50.292534 FMAP: area RW_VPD found @ f35000 (8192 bytes)
1803 12:40:50.296078 Google Chrome EC: version:
1804 12:40:50.299424 ro: voema_v2.0.10114-a447f03e46
1805 12:40:50.302867 rw: voema_v2.0.10114-a447f03e46
1806 12:40:50.303289 running image: 2
1807 12:40:50.309122 PCI space above 4GB MMIO is at 0x480400000, len = 0x7b7fc00000
1808 12:40:50.314055 ACPI: * FADT
1809 12:40:50.314622 SCI is IRQ9
1810 12:40:50.320392 ACPI: added table 1/32, length now 40
1811 12:40:50.321104 ACPI: * SSDT
1812 12:40:50.323953 Found 1 CPU(s) with 8 core(s) each.
1813 12:40:50.330553 \_SB.PCI0.PMC: Intel Tigerlake at PCI: 00:1f.2
1814 12:40:50.334023 \_SB.DPTF: Intel DPTF at GENERIC: 0.0
1815 12:40:50.337366 \_SB.PCI0.CNVW: WIFI Device GENERIC: 0.0
1816 12:40:50.340272 \_SB.PCI0.I2C0.RT58: Headset Codec at I2C: 00:1a
1817 12:40:50.347319 \_SB.PCI0.I2C0.MAXR: Maxim MAX98373 Codec address 031h
1818 12:40:50.353601 \_SB.PCI0.I2C0.MAXL: Maxim MAX98373 Codec address 032h
1819 12:40:50.356934 \_SB.PCI0.I2C1.H010: ELAN Touchscreen at I2C: 00:10
1820 12:40:50.363737 \_SB.PCI0.I2C5.D015: ELAN Touchpad at I2C: 00:15
1821 12:40:50.370221 \_SB.PCI0.RP09: Enable RTD3 for PCI: 00:1d.0 (Intel PCIe Runtime D3)
1822 12:40:50.373924 \_SB.PCI0.RP09: Added StorageD3Enable property
1823 12:40:50.376721 \_SB.PCI0.SPI0.S001: SPI Device at SPI: 00
1824 12:40:50.383464 \_SB.PCI0.SPI1.CRFP: SPI Device at SPI: 00
1825 12:40:50.390378 PS2K: Physmap: [ EA E7 91 92 93 94 95 A0 AE B0 ]
1826 12:40:50.393523 PS2K: Passing 80 keymaps to kernel
1827 12:40:50.400068 \_SB.PCI0.TXHC.RHUB.SS01: USB3 Type-C Port C0 (MLB) at USB3 port 0
1828 12:40:50.406557 \_SB.PCI0.TXHC.RHUB.SS02: USB3 Type-C Port C1 (DB) at USB3 port 1
1829 12:40:50.413385 \_SB.PCI0.XHCI.RHUB.HS02: USB2 Type-A Port A1 (DB) at USB2 port 1
1830 12:40:50.420216 \_SB.PCI0.XHCI.RHUB.HS03: USB2 Type-C Port C1 (DB) at USB2 port 2
1831 12:40:50.426977 \_SB.PCI0.XHCI.RHUB.HS05: USB2 Type-C Port C0 (MLB) at USB2 port 4
1832 12:40:50.433865 \_SB.PCI0.XHCI.RHUB.SS02: USB3 Type-A Port A1 (DB) at USB3 port 1
1833 12:40:50.440191 \_SB.PCI0.PMC.MUX.CON0: Intel PMC MUX CONN Driver at GENERIC: 0.0
1834 12:40:50.446915 \_SB.PCI0.PMC.MUX.CON1: Intel PMC MUX CONN Driver at GENERIC: 1.0
1835 12:40:50.450274 ACPI: added table 2/32, length now 44
1836 12:40:50.450738 ACPI: * MCFG
1837 12:40:50.456694 ACPI: added table 3/32, length now 48
1838 12:40:50.457110 ACPI: * TPM2
1839 12:40:50.460092 TPM2 log created at 0x769f0000
1840 12:40:50.463294 ACPI: added table 4/32, length now 52
1841 12:40:50.466534 ACPI: * MADT
1842 12:40:50.466950 SCI is IRQ9
1843 12:40:50.469856 ACPI: added table 5/32, length now 56
1844 12:40:50.472968 current = 76b09850
1845 12:40:50.473385 ACPI: * DMAR
1846 12:40:50.476906 ACPI: added table 6/32, length now 60
1847 12:40:50.483271 ACPI: added table 7/32, length now 64
1848 12:40:50.483686 ACPI: * HPET
1849 12:40:50.486613 ACPI: added table 8/32, length now 68
1850 12:40:50.489953 ACPI: done.
1851 12:40:50.490394 ACPI tables: 35216 bytes.
1852 12:40:50.493184 smbios_write_tables: 769ef000
1853 12:40:50.496990 EC returned error result code 3
1854 12:40:50.499705 Couldn't obtain OEM name from CBI
1855 12:40:50.503633 Create SMBIOS type 16
1856 12:40:50.506754 Create SMBIOS type 17
1857 12:40:50.510098 GENERIC: 0.0 (WIFI Device)
1858 12:40:50.510649 SMBIOS tables: 1734 bytes.
1859 12:40:50.517044 Writing table forward entry at 0x00000500
1860 12:40:50.523651 Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 392c
1861 12:40:50.527398 Writing coreboot table at 0x76b25000
1862 12:40:50.533520 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1863 12:40:50.536740 1. 0000000000001000-000000000009ffff: RAM
1864 12:40:50.540044 2. 00000000000a0000-00000000000fffff: RESERVED
1865 12:40:50.546842 3. 0000000000100000-00000000769eefff: RAM
1866 12:40:50.550119 4. 00000000769ef000-0000000076b97fff: CONFIGURATION TABLES
1867 12:40:50.556611 5. 0000000076b98000-0000000076c09fff: RAMSTAGE
1868 12:40:50.563163 6. 0000000076c0a000-0000000076ffffff: CONFIGURATION TABLES
1869 12:40:50.566558 7. 0000000077000000-000000007fbfffff: RESERVED
1870 12:40:50.569813 8. 00000000c0000000-00000000cfffffff: RESERVED
1871 12:40:50.577089 9. 00000000f8000000-00000000f9ffffff: RESERVED
1872 12:40:50.580153 10. 00000000fb000000-00000000fb000fff: RESERVED
1873 12:40:50.586527 11. 00000000fe000000-00000000fe00ffff: RESERVED
1874 12:40:50.589948 12. 00000000fed80000-00000000fed87fff: RESERVED
1875 12:40:50.596411 13. 00000000fed90000-00000000fed92fff: RESERVED
1876 12:40:50.599684 14. 00000000feda0000-00000000feda1fff: RESERVED
1877 12:40:50.606879 15. 00000000fedc0000-00000000feddffff: RESERVED
1878 12:40:50.609989 16. 0000000100000000-00000004803fffff: RAM
1879 12:40:50.612918 Passing 4 GPIOs to payload:
1880 12:40:50.616442 NAME | PORT | POLARITY | VALUE
1881 12:40:50.622832 lid | undefined | high | high
1882 12:40:50.626458 power | undefined | high | low
1883 12:40:50.632913 oprom | undefined | high | low
1884 12:40:50.639773 EC in RW | 0x000000e5 | high | high
1885 12:40:50.646109 Wrote coreboot table at: 0x76b25000, 0x610 bytes, checksum f1ab
1886 12:40:50.646579 coreboot table: 1576 bytes.
1887 12:40:50.652941 IMD ROOT 0. 0x76fff000 0x00001000
1888 12:40:50.656278 IMD SMALL 1. 0x76ffe000 0x00001000
1889 12:40:50.659422 FSP MEMORY 2. 0x76c4e000 0x003b0000
1890 12:40:50.662944 VPD 3. 0x76c4d000 0x00000367
1891 12:40:50.666330 RO MCACHE 4. 0x76c4c000 0x00000fdc
1892 12:40:50.669757 CONSOLE 5. 0x76c2c000 0x00020000
1893 12:40:50.672825 FMAP 6. 0x76c2b000 0x00000578
1894 12:40:50.676675 TIME STAMP 7. 0x76c2a000 0x00000910
1895 12:40:50.679958 VBOOT WORK 8. 0x76c16000 0x00014000
1896 12:40:50.686515 ROMSTG STCK 9. 0x76c15000 0x00001000
1897 12:40:50.689795 AFTER CAR 10. 0x76c0a000 0x0000b000
1898 12:40:50.692861 RAMSTAGE 11. 0x76b97000 0x00073000
1899 12:40:50.696886 REFCODE 12. 0x76b42000 0x00055000
1900 12:40:50.699858 SMM BACKUP 13. 0x76b32000 0x00010000
1901 12:40:50.703140 4f444749 14. 0x76b30000 0x00002000
1902 12:40:50.706662 EXT VBT15. 0x76b2d000 0x0000219f
1903 12:40:50.709301 COREBOOT 16. 0x76b25000 0x00008000
1904 12:40:50.713122 ACPI 17. 0x76b01000 0x00024000
1905 12:40:50.719365 ACPI GNVS 18. 0x76b00000 0x00001000
1906 12:40:50.722908 RAMOOPS 19. 0x76a00000 0x00100000
1907 12:40:50.726567 TPM2 TCGLOG20. 0x769f0000 0x00010000
1908 12:40:50.729921 SMBIOS 21. 0x769ef000 0x00000800
1909 12:40:50.730645 IMD small region:
1910 12:40:50.736179 IMD ROOT 0. 0x76ffec00 0x00000400
1911 12:40:50.739663 FSP RUNTIME 1. 0x76ffebe0 0x00000004
1912 12:40:50.742705 POWER STATE 2. 0x76ffeb80 0x00000044
1913 12:40:50.746397 ROMSTAGE 3. 0x76ffeb60 0x00000004
1914 12:40:50.749553 MEM INFO 4. 0x76ffe980 0x000001e0
1915 12:40:50.756345 BS: BS_WRITE_TABLES run times (exec / console): 7 / 484 ms
1916 12:40:50.760341 MTRR: Physical address space:
1917 12:40:50.766061 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
1918 12:40:50.773258 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
1919 12:40:50.779328 0x00000000000c0000 - 0x0000000077000000 size 0x76f40000 type 6
1920 12:40:50.786029 0x0000000077000000 - 0x0000000080000000 size 0x09000000 type 0
1921 12:40:50.789167 0x0000000080000000 - 0x0000000090000000 size 0x10000000 type 1
1922 12:40:50.795993 0x0000000090000000 - 0x0000000100000000 size 0x70000000 type 0
1923 12:40:50.802700 0x0000000100000000 - 0x0000000480400000 size 0x380400000 type 6
1924 12:40:50.806103 MTRR: Fixed MSR 0x250 0x0606060606060606
1925 12:40:50.812576 MTRR: Fixed MSR 0x258 0x0606060606060606
1926 12:40:50.815542 MTRR: Fixed MSR 0x259 0x0000000000000000
1927 12:40:50.818969 MTRR: Fixed MSR 0x268 0x0606060606060606
1928 12:40:50.822563 MTRR: Fixed MSR 0x269 0x0606060606060606
1929 12:40:50.829597 MTRR: Fixed MSR 0x26a 0x0606060606060606
1930 12:40:50.832441 MTRR: Fixed MSR 0x26b 0x0606060606060606
1931 12:40:50.835901 MTRR: Fixed MSR 0x26c 0x0606060606060606
1932 12:40:50.839166 MTRR: Fixed MSR 0x26d 0x0606060606060606
1933 12:40:50.845728 MTRR: Fixed MSR 0x26e 0x0606060606060606
1934 12:40:50.848825 MTRR: Fixed MSR 0x26f 0x0606060606060606
1935 12:40:50.852546 call enable_fixed_mtrr()
1936 12:40:50.856052 CPU physical address size: 39 bits
1937 12:40:50.862550 MTRR: default type WB/UC MTRR counts: 6/7.
1938 12:40:50.865740 MTRR: WB selected as default type.
1939 12:40:50.872178 MTRR: 0 base 0x0000000077000000 mask 0x0000007fff000000 type 0
1940 12:40:50.876037 MTRR: 1 base 0x0000000078000000 mask 0x0000007ff8000000 type 0
1941 12:40:50.882870 MTRR: 2 base 0x0000000080000000 mask 0x0000007ff0000000 type 1
1942 12:40:50.889353 MTRR: 3 base 0x0000000090000000 mask 0x0000007ff0000000 type 0
1943 12:40:50.895650 MTRR: 4 base 0x00000000a0000000 mask 0x0000007fe0000000 type 0
1944 12:40:50.902347 MTRR: 5 base 0x00000000c0000000 mask 0x0000007fc0000000 type 0
1945 12:40:50.906879
1946 12:40:50.907386 MTRR check
1947 12:40:50.909441 Fixed MTRRs : Enabled
1948 12:40:50.909856 Variable MTRRs: Enabled
1949 12:40:50.910186
1950 12:40:50.916855 MTRR: Fixed MSR 0x250 0x0606060606060606
1951 12:40:50.919516 MTRR: Fixed MSR 0x258 0x0606060606060606
1952 12:40:50.923023 MTRR: Fixed MSR 0x259 0x0000000000000000
1953 12:40:50.926387 MTRR: Fixed MSR 0x268 0x0606060606060606
1954 12:40:50.933032 MTRR: Fixed MSR 0x269 0x0606060606060606
1955 12:40:50.936166 MTRR: Fixed MSR 0x26a 0x0606060606060606
1956 12:40:50.939738 MTRR: Fixed MSR 0x26b 0x0606060606060606
1957 12:40:50.943390 MTRR: Fixed MSR 0x26c 0x0606060606060606
1958 12:40:50.949382 MTRR: Fixed MSR 0x26d 0x0606060606060606
1959 12:40:50.952537 MTRR: Fixed MSR 0x26e 0x0606060606060606
1960 12:40:50.955823 MTRR: Fixed MSR 0x26f 0x0606060606060606
1961 12:40:50.963733 BS: BS_WRITE_TABLES exit times (exec / console): 4 / 150 ms
1962 12:40:50.966946 call enable_fixed_mtrr()
1963 12:40:50.970184 Checking cr50 for pending updates
1964 12:40:50.973675 CPU physical address size: 39 bits
1965 12:40:50.976964 MTRR: Fixed MSR 0x250 0x0606060606060606
1966 12:40:50.980467 MTRR: Fixed MSR 0x250 0x0606060606060606
1967 12:40:50.986521 MTRR: Fixed MSR 0x258 0x0606060606060606
1968 12:40:50.990365 MTRR: Fixed MSR 0x259 0x0000000000000000
1969 12:40:50.993556 MTRR: Fixed MSR 0x268 0x0606060606060606
1970 12:40:50.996675 MTRR: Fixed MSR 0x269 0x0606060606060606
1971 12:40:51.003445 MTRR: Fixed MSR 0x26a 0x0606060606060606
1972 12:40:51.006551 MTRR: Fixed MSR 0x26b 0x0606060606060606
1973 12:40:51.010044 MTRR: Fixed MSR 0x26c 0x0606060606060606
1974 12:40:51.013468 MTRR: Fixed MSR 0x26d 0x0606060606060606
1975 12:40:51.020273 MTRR: Fixed MSR 0x26e 0x0606060606060606
1976 12:40:51.023539 MTRR: Fixed MSR 0x26f 0x0606060606060606
1977 12:40:51.030177 MTRR: Fixed MSR 0x258 0x0606060606060606
1978 12:40:51.030709 call enable_fixed_mtrr()
1979 12:40:51.036720 MTRR: Fixed MSR 0x259 0x0000000000000000
1980 12:40:51.040145 MTRR: Fixed MSR 0x268 0x0606060606060606
1981 12:40:51.043587 MTRR: Fixed MSR 0x269 0x0606060606060606
1982 12:40:51.046832 MTRR: Fixed MSR 0x26a 0x0606060606060606
1983 12:40:51.053378 MTRR: Fixed MSR 0x26b 0x0606060606060606
1984 12:40:51.056512 MTRR: Fixed MSR 0x26c 0x0606060606060606
1985 12:40:51.059780 MTRR: Fixed MSR 0x26d 0x0606060606060606
1986 12:40:51.063278 MTRR: Fixed MSR 0x26e 0x0606060606060606
1987 12:40:51.069883 MTRR: Fixed MSR 0x26f 0x0606060606060606
1988 12:40:51.072940 CPU physical address size: 39 bits
1989 12:40:51.077986 call enable_fixed_mtrr()
1990 12:40:51.081172 MTRR: Fixed MSR 0x250 0x0606060606060606
1991 12:40:51.087905 MTRR: Fixed MSR 0x250 0x0606060606060606
1992 12:40:51.091035 MTRR: Fixed MSR 0x258 0x0606060606060606
1993 12:40:51.094653 MTRR: Fixed MSR 0x259 0x0000000000000000
1994 12:40:51.097826 MTRR: Fixed MSR 0x268 0x0606060606060606
1995 12:40:51.104385 MTRR: Fixed MSR 0x269 0x0606060606060606
1996 12:40:51.107889 MTRR: Fixed MSR 0x26a 0x0606060606060606
1997 12:40:51.111069 MTRR: Fixed MSR 0x26b 0x0606060606060606
1998 12:40:51.114557 MTRR: Fixed MSR 0x26c 0x0606060606060606
1999 12:40:51.121275 MTRR: Fixed MSR 0x26d 0x0606060606060606
2000 12:40:51.124338 MTRR: Fixed MSR 0x26e 0x0606060606060606
2001 12:40:51.127804 MTRR: Fixed MSR 0x26f 0x0606060606060606
2002 12:40:51.135252 MTRR: Fixed MSR 0x258 0x0606060606060606
2003 12:40:51.135743 call enable_fixed_mtrr()
2004 12:40:51.142203 MTRR: Fixed MSR 0x259 0x0000000000000000
2005 12:40:51.145244 MTRR: Fixed MSR 0x268 0x0606060606060606
2006 12:40:51.148811 MTRR: Fixed MSR 0x269 0x0606060606060606
2007 12:40:51.151644 MTRR: Fixed MSR 0x26a 0x0606060606060606
2008 12:40:51.158349 MTRR: Fixed MSR 0x26b 0x0606060606060606
2009 12:40:51.162082 MTRR: Fixed MSR 0x26c 0x0606060606060606
2010 12:40:51.165311 MTRR: Fixed MSR 0x26d 0x0606060606060606
2011 12:40:51.168304 MTRR: Fixed MSR 0x26e 0x0606060606060606
2012 12:40:51.175072 MTRR: Fixed MSR 0x26f 0x0606060606060606
2013 12:40:51.178288 CPU physical address size: 39 bits
2014 12:40:51.183563 call enable_fixed_mtrr()
2015 12:40:51.186535 Reading cr50 TPM mode
2016 12:40:51.189979 CPU physical address size: 39 bits
2017 12:40:51.193778 CPU physical address size: 39 bits
2018 12:40:51.197075 MTRR: Fixed MSR 0x250 0x0606060606060606
2019 12:40:51.200208 MTRR: Fixed MSR 0x250 0x0606060606060606
2020 12:40:51.207377 MTRR: Fixed MSR 0x258 0x0606060606060606
2021 12:40:51.210543 MTRR: Fixed MSR 0x259 0x0000000000000000
2022 12:40:51.213474 MTRR: Fixed MSR 0x268 0x0606060606060606
2023 12:40:51.216742 MTRR: Fixed MSR 0x269 0x0606060606060606
2024 12:40:51.220298 MTRR: Fixed MSR 0x26a 0x0606060606060606
2025 12:40:51.226902 MTRR: Fixed MSR 0x26b 0x0606060606060606
2026 12:40:51.230234 MTRR: Fixed MSR 0x26c 0x0606060606060606
2027 12:40:51.233823 MTRR: Fixed MSR 0x26d 0x0606060606060606
2028 12:40:51.237470 MTRR: Fixed MSR 0x26e 0x0606060606060606
2029 12:40:51.243074 MTRR: Fixed MSR 0x26f 0x0606060606060606
2030 12:40:51.249994 MTRR: Fixed MSR 0x258 0x0606060606060606
2031 12:40:51.253522 MTRR: Fixed MSR 0x259 0x0000000000000000
2032 12:40:51.256323 MTRR: Fixed MSR 0x268 0x0606060606060606
2033 12:40:51.259552 MTRR: Fixed MSR 0x269 0x0606060606060606
2034 12:40:51.266005 MTRR: Fixed MSR 0x26a 0x0606060606060606
2035 12:40:51.269388 MTRR: Fixed MSR 0x26b 0x0606060606060606
2036 12:40:51.272453 MTRR: Fixed MSR 0x26c 0x0606060606060606
2037 12:40:51.276130 MTRR: Fixed MSR 0x26d 0x0606060606060606
2038 12:40:51.282589 MTRR: Fixed MSR 0x26e 0x0606060606060606
2039 12:40:51.286352 MTRR: Fixed MSR 0x26f 0x0606060606060606
2040 12:40:51.289548 call enable_fixed_mtrr()
2041 12:40:51.292738 call enable_fixed_mtrr()
2042 12:40:51.299245 BS: BS_PAYLOAD_LOAD entry times (exec / console): 221 / 6 ms
2043 12:40:51.302661 CPU physical address size: 39 bits
2044 12:40:51.306968 CPU physical address size: 39 bits
2045 12:40:51.316690 CBFS: Found 'fallback/payload' @0x38db00 size 0x4be9c in mcache @0x76c4cf60
2046 12:40:51.319759 Checking segment from ROM address 0xffc02b38
2047 12:40:51.323169 Checking segment from ROM address 0xffc02b54
2048 12:40:51.329429 Loading segment from ROM address 0xffc02b38
2049 12:40:51.332880 code (compression=0)
2050 12:40:51.339956 New segment dstaddr 0x30000000 memsize 0x2662db0 srcaddr 0xffc02b70 filesize 0x4be64
2051 12:40:51.349373 Loading Segment: addr: 0x30000000 memsz: 0x0000000002662db0 filesz: 0x000000000004be64
2052 12:40:51.349795 it's not compressed!
2053 12:40:51.500122 [ 0x30000000, 3004be64, 0x32662db0) <- ffc02b70
2054 12:40:51.506259 Clearing Segment: addr: 0x000000003004be64 memsz: 0x0000000002616f4c
2055 12:40:51.514013 Loading segment from ROM address 0xffc02b54
2056 12:40:51.516968 Entry Point 0x30000000
2057 12:40:51.517484 Loaded segments
2058 12:40:51.523653 BS: BS_PAYLOAD_LOAD run times (exec / console): 155 / 63 ms
2059 12:40:51.569601 Finalizing chipset.
2060 12:40:51.572265 Finalizing SMM.
2061 12:40:51.572789 APMC done.
2062 12:40:51.579132 BS: BS_PAYLOAD_LOAD exit times (exec / console): 44 / 5 ms
2063 12:40:51.582467 mp_park_aps done after 0 msecs.
2064 12:40:51.585605 Jumping to boot code at 0x30000000(0x76b25000)
2065 12:40:51.595310 CPU0: stack: 0x76bee000 - 0x76bef000, lowest used address 0x76beea78, stack used: 1416 bytes
2066 12:40:51.595733
2067 12:40:51.596065
2068 12:40:51.596370
2069 12:40:51.598831 Starting depthcharge on Voema...
2070 12:40:51.599261
2071 12:40:51.600310 end: 2.2.3 depthcharge-start (duration 00:00:10) [common]
2072 12:40:51.600778 start: 2.2.4 bootloader-commands (timeout 00:04:45) [common]
2073 12:40:51.601176 Setting prompt string to ['volteer:']
2074 12:40:51.601541 bootloader-commands: Wait for prompt ['volteer:'] (timeout 00:04:45)
2075 12:40:51.609254 WARNING: can't convert coreboot GPIOs, 'lid' won't be resampled at runtime!
2076 12:40:51.609776
2077 12:40:51.615737 WARNING: can't convert coreboot GPIOs, 'power' won't be resampled at runtime!
2078 12:40:51.616258
2079 12:40:51.622187 Looking for NVMe Controller 0x3005f220 @ 00:1d:00
2080 12:40:51.622740
2081 12:40:51.625636 Failed to find eMMC card reader
2082 12:40:51.626054
2083 12:40:51.626381 Wipe memory regions:
2084 12:40:51.626732
2085 12:40:51.632455 [0x00000000001000, 0x000000000a0000)
2086 12:40:51.632982
2087 12:40:51.635079 [0x00000000100000, 0x00000030000000)
2088 12:40:51.674646
2089 12:40:51.677852 [0x00000032662db0, 0x000000769ef000)
2090 12:40:51.732200
2091 12:40:51.735638 [0x00000100000000, 0x00000480400000)
2092 12:40:52.417277
2093 12:40:52.420404 ec_init: CrosEC protocol v3 supported (256, 256)
2094 12:40:52.851502
2095 12:40:52.851653 R8152: Initializing
2096 12:40:52.851726
2097 12:40:52.854725 Version 6 (ocp_data = 5c30)
2098 12:40:52.854815
2099 12:40:52.858326 R8152: Done initializing
2100 12:40:52.858425
2101 12:40:52.861438 Adding net device
2102 12:40:53.162629
2103 12:40:53.166125 [firmware-volteer-13672.B-collabora] Oct 22 2021 06:32:35
2104 12:40:53.166218
2105 12:40:53.166290
2106 12:40:53.166356
2107 12:40:53.169892 Setting prompt string to ['volteer:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2109 12:40:53.270285 volteer: tftpboot 192.168.201.1 11383472/tftp-deploy-vcc61456/kernel/bzImage 11383472/tftp-deploy-vcc61456/kernel/cmdline 11383472/tftp-deploy-vcc61456/ramdisk/ramdisk.cpio.gz
2110 12:40:53.270440 Setting prompt string to ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2111 12:40:53.270541 bootloader-commands: Wait for prompt ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:43)
2112 12:40:53.274873 tftpboot 192.168.201.1 11383472/tftp-deploy-vcc61456/kernel/bzIploy-vcc61456/kernel/cmdline 11383472/tftp-deploy-vcc61456/ramdisk/ramdisk.cpio.gz
2113 12:40:53.274968
2114 12:40:53.275039 Waiting for link
2115 12:40:53.478741
2116 12:40:53.478887 done.
2117 12:40:53.478962
2118 12:40:53.479029 MAC: 00:24:32:30:77:d1
2119 12:40:53.479096
2120 12:40:53.482085 Sending DHCP discover... done.
2121 12:40:53.482177
2122 12:40:53.485729 Waiting for reply... done.
2123 12:40:53.485829
2124 12:40:53.488512 Sending DHCP request... done.
2125 12:40:53.488602
2126 12:40:53.494906 Waiting for reply... done.
2127 12:40:53.494997
2128 12:40:53.495069 My ip is 192.168.201.13
2129 12:40:53.495136
2130 12:40:53.498413 The DHCP server ip is 192.168.201.1
2131 12:40:53.498517
2132 12:40:53.504943 TFTP server IP predefined by user: 192.168.201.1
2133 12:40:53.505034
2134 12:40:53.511448 Bootfile predefined by user: 11383472/tftp-deploy-vcc61456/kernel/bzImage
2135 12:40:53.511540
2136 12:40:53.515133 Sending tftp read request... done.
2137 12:40:53.515224
2138 12:40:53.518240 Waiting for the transfer...
2139 12:40:53.518334
2140 12:40:54.060944 00000000 ################################################################
2141 12:40:54.061101
2142 12:40:54.602065 00080000 ################################################################
2143 12:40:54.602223
2144 12:40:55.147370 00100000 ################################################################
2145 12:40:55.147529
2146 12:40:55.697406 00180000 ################################################################
2147 12:40:55.697557
2148 12:40:56.234829 00200000 ################################################################
2149 12:40:56.234986
2150 12:40:56.779647 00280000 ################################################################
2151 12:40:56.779808
2152 12:40:57.310891 00300000 ################################################################
2153 12:40:57.311050
2154 12:40:57.842340 00380000 ################################################################
2155 12:40:57.842511
2156 12:40:58.370498 00400000 ################################################################
2157 12:40:58.370651
2158 12:40:58.903423 00480000 ################################################################
2159 12:40:58.903586
2160 12:40:59.430733 00500000 ################################################################
2161 12:40:59.430884
2162 12:40:59.978667 00580000 ################################################################
2163 12:40:59.978824
2164 12:41:00.509196 00600000 ################################################################
2165 12:41:00.509356
2166 12:41:01.049516 00680000 ################################################################
2167 12:41:01.049676
2168 12:41:01.573788 00700000 ################################################################
2169 12:41:01.573947
2170 12:41:02.090955 00780000 ################################################################
2171 12:41:02.091111
2172 12:41:02.191507 00800000 ############# done.
2173 12:41:02.191650
2174 12:41:02.195268 The bootfile was 8490896 bytes long.
2175 12:41:02.195353
2176 12:41:02.198587 Sending tftp read request... done.
2177 12:41:02.198689
2178 12:41:02.201368 Waiting for the transfer...
2179 12:41:02.201456
2180 12:41:02.722564 00000000 ################################################################
2181 12:41:02.722727
2182 12:41:03.240276 00080000 ################################################################
2183 12:41:03.240470
2184 12:41:03.778669 00100000 ################################################################
2185 12:41:03.778826
2186 12:41:04.327773 00180000 ################################################################
2187 12:41:04.327929
2188 12:41:04.875780 00200000 ################################################################
2189 12:41:04.875941
2190 12:41:05.433258 00280000 ################################################################
2191 12:41:05.433419
2192 12:41:05.964251 00300000 ################################################################
2193 12:41:05.964409
2194 12:41:06.501151 00380000 ################################################################
2195 12:41:06.501311
2196 12:41:07.016535 00400000 ################################################################
2197 12:41:07.016695
2198 12:41:07.547832 00480000 ################################################################
2199 12:41:07.547993
2200 12:41:08.062596 00500000 ################################################################
2201 12:41:08.062743
2202 12:41:08.579039 00580000 ################################################################
2203 12:41:08.579180
2204 12:41:09.100451 00600000 ################################################################
2205 12:41:09.100595
2206 12:41:09.617479 00680000 ################################################################
2207 12:41:09.617629
2208 12:41:10.155432 00700000 ################################################################
2209 12:41:10.155578
2210 12:41:10.695515 00780000 ################################################################
2211 12:41:10.695666
2212 12:41:11.234188 00800000 ################################################################
2213 12:41:11.234340
2214 12:41:11.769550 00880000 ################################################################
2215 12:41:11.769702
2216 12:41:12.318246 00900000 ################################################################
2217 12:41:12.318429
2218 12:41:12.859229 00980000 ################################################################
2219 12:41:12.859384
2220 12:41:13.416753 00a00000 ################################################################
2221 12:41:13.416910
2222 12:41:13.956951 00a80000 ################################################################
2223 12:41:13.957106
2224 12:41:14.511505 00b00000 ################################################################
2225 12:41:14.511656
2226 12:41:15.178838 00b80000 ################################################################
2227 12:41:15.179361
2228 12:41:15.886020 00c00000 ################################################################
2229 12:41:15.886606
2230 12:41:16.582884 00c80000 ################################################################
2231 12:41:16.583506
2232 12:41:17.278590 00d00000 ################################################################
2233 12:41:17.279078
2234 12:41:17.975878 00d80000 ################################################################
2235 12:41:17.976403
2236 12:41:18.677510 00e00000 ################################################################
2237 12:41:18.678087
2238 12:41:19.378478 00e80000 ################################################################
2239 12:41:19.379033
2240 12:41:20.095102 00f00000 ################################################################
2241 12:41:20.095614
2242 12:41:20.792773 00f80000 ################################################################
2243 12:41:20.793294
2244 12:41:21.522044 01000000 ################################################################
2245 12:41:21.522620
2246 12:41:22.242307 01080000 ################################################################
2247 12:41:22.242868
2248 12:41:22.963383 01100000 ################################################################
2249 12:41:22.963929
2250 12:41:23.671858 01180000 ################################################################
2251 12:41:23.672378
2252 12:41:24.380813 01200000 ################################################################
2253 12:41:24.381347
2254 12:41:25.092595 01280000 ################################################################
2255 12:41:25.093103
2256 12:41:25.811114 01300000 ################################################################
2257 12:41:25.811685
2258 12:41:26.520591 01380000 ################################################################
2259 12:41:26.521100
2260 12:41:27.219278 01400000 ################################################################
2261 12:41:27.219787
2262 12:41:27.920330 01480000 ################################################################
2263 12:41:27.920833
2264 12:41:28.627859 01500000 ################################################################
2265 12:41:28.628367
2266 12:41:29.323169 01580000 ################################################################
2267 12:41:29.323687
2268 12:41:30.006394 01600000 ################################################################
2269 12:41:30.006954
2270 12:41:30.710652 01680000 ################################################################
2271 12:41:30.710912
2272 12:41:31.365032 01700000 ################################################################
2273 12:41:31.365179
2274 12:41:31.990384 01780000 ################################################################
2275 12:41:31.990927
2276 12:41:32.556709 01800000 ################################################################
2277 12:41:32.556855
2278 12:41:33.101886 01880000 ################################################################
2279 12:41:33.102048
2280 12:41:33.641319 01900000 ################################################################
2281 12:41:33.641479
2282 12:41:34.176254 01980000 ################################################################
2283 12:41:34.176424
2284 12:41:34.729545 01a00000 ################################################################
2285 12:41:34.729731
2286 12:41:35.256027 01a80000 ################################################################
2287 12:41:35.256194
2288 12:41:35.818083 01b00000 ################################################################
2289 12:41:35.818241
2290 12:41:36.421107 01b80000 ################################################################
2291 12:41:36.421338
2292 12:41:37.107749 01c00000 ################################################################
2293 12:41:37.108262
2294 12:41:37.812391 01c80000 ################################################################
2295 12:41:37.812878
2296 12:41:38.523320 01d00000 ################################################################
2297 12:41:38.523814
2298 12:41:39.220938 01d80000 ################################################################
2299 12:41:39.221142
2300 12:41:39.931671 01e00000 ################################################################
2301 12:41:39.932177
2302 12:41:40.618036 01e80000 ################################################################
2303 12:41:40.618252
2304 12:41:41.324904 01f00000 ################################################################
2305 12:41:41.325428
2306 12:41:42.058014 01f80000 ################################################################
2307 12:41:42.058555
2308 12:41:42.771572 02000000 ################################################################
2309 12:41:42.772120
2310 12:41:43.480903 02080000 ################################################################
2311 12:41:43.481416
2312 12:41:44.176531 02100000 ################################################################
2313 12:41:44.177055
2314 12:41:44.881515 02180000 ################################################################
2315 12:41:44.882049
2316 12:41:45.449504 02200000 #################################################### done.
2317 12:41:45.450020
2318 12:41:45.452991 Sending tftp read request... done.
2319 12:41:45.453405
2320 12:41:45.456550 Waiting for the transfer...
2321 12:41:45.456962
2322 12:41:45.457281 00000000 # done.
2323 12:41:45.457590
2324 12:41:45.466637 Command line loaded dynamically from TFTP file: 11383472/tftp-deploy-vcc61456/kernel/cmdline
2325 12:41:45.467052
2326 12:41:45.482969 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
2327 12:41:45.488580
2328 12:41:45.491998 Shutting down all USB controllers.
2329 12:41:45.492412
2330 12:41:45.492737 Removing current net device
2331 12:41:45.493038
2332 12:41:45.495043 Finalizing coreboot
2333 12:41:45.495458
2334 12:41:45.501786 Exiting depthcharge with code 4 at timestamp: 62489754
2335 12:41:45.502203
2336 12:41:45.502562
2337 12:41:45.502873 Starting kernel ...
2338 12:41:45.503195
2339 12:41:45.503491
2340 12:41:45.504797 end: 2.2.4 bootloader-commands (duration 00:00:54) [common]
2341 12:41:45.505297 start: 2.2.5 auto-login-action (timeout 00:03:51) [common]
2342 12:41:45.505678 Setting prompt string to ['Linux version [0-9]']
2343 12:41:45.506016 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2344 12:41:45.506362 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
2346 12:45:36.506175 end: 2.2.5 auto-login-action (duration 00:03:51) [common]
2348 12:45:36.507213 depthcharge-retry failed: 1 of 1 attempts. 'auto-login-action timed out after 231 seconds'
2350 12:45:36.507991 end: 2.2 depthcharge-retry (duration 00:05:00) [common]
2353 12:45:36.509592 end: 2 depthcharge-action (duration 00:05:00) [common]
2355 12:45:36.510843 Cleaning after the job
2356 12:45:36.510993 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11383472/tftp-deploy-vcc61456/ramdisk
2357 12:45:36.516367 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11383472/tftp-deploy-vcc61456/kernel
2358 12:45:36.517831 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11383472/tftp-deploy-vcc61456/modules
2359 12:45:36.518219 start: 4.1 power-off (timeout 00:00:30) [common]
2360 12:45:36.518393 Calling: 'pduclient' '--daemon=localhost' '--hostname=asus-cx9400-volteer-cbg-11' '--port=1' '--command=off'
2361 12:45:36.592202 >> Command sent successfully.
2362 12:45:36.597207 Returned 0 in 0 seconds
2363 12:45:36.698181 end: 4.1 power-off (duration 00:00:00) [common]
2365 12:45:36.699621 start: 4.2 read-feedback (timeout 00:10:00) [common]
2366 12:45:36.700829 Listened to connection for namespace 'common' for up to 1s
2367 12:45:37.701344 Finalising connection for namespace 'common'
2368 12:45:37.701541 Disconnecting from shell: Finalise
2369 12:45:37.701618
2370 12:45:37.802226 end: 4.2 read-feedback (duration 00:00:01) [common]
2371 12:45:37.802818 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11383472
2372 12:45:37.902391 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11383472
2373 12:45:37.902606 JobError: Your job cannot terminate cleanly.