Boot log: acer-cbv514-1h-34uz-brya
- Warnings: 0
- Kernel Warnings: 0
- Kernel Errors: 0
- Errors: 2
- Boot result: FAIL
1 17:46:56.578266 lava-dispatcher, installed at version: 2023.08
2 17:46:56.578432 start: 0 validate
3 17:46:56.578542 Start time: 2023-10-09 17:46:56.578534+00:00 (UTC)
4 17:46:56.578646 Using caching service: 'http://localhost/cache/?uri=%s'
5 17:46:56.578754 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230623.0%2Fx86%2Frootfs.cpio.gz exists
6 17:46:56.841642 Using caching service: 'http://localhost/cache/?uri=%s'
7 17:46:56.842217 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-4.4.y-st-rc%2Fv4.4-st20-1778-gc774a35d86d2%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fkernel%2FbzImage exists
8 17:46:57.111772 Using caching service: 'http://localhost/cache/?uri=%s'
9 17:46:57.112372 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-4.4.y-st-rc%2Fv4.4-st20-1778-gc774a35d86d2%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
10 17:46:57.381223 validate duration: 0.80
12 17:46:57.381503 start: 1 tftp-deploy (timeout 00:10:00) [common]
13 17:46:57.381595 start: 1.1 download-retry (timeout 00:10:00) [common]
14 17:46:57.381668 start: 1.1.1 http-download (timeout 00:10:00) [common]
15 17:46:57.381783 Not decompressing ramdisk as can be used compressed.
16 17:46:57.381861 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230623.0/x86/rootfs.cpio.gz
17 17:46:57.381917 saving as /var/lib/lava/dispatcher/tmp/11712741/tftp-deploy-ljrl3t7v/ramdisk/rootfs.cpio.gz
18 17:46:57.381966 total size: 8418130 (8 MB)
19 17:46:57.382979 progress 0 % (0 MB)
20 17:46:57.384716 progress 5 % (0 MB)
21 17:46:57.386301 progress 10 % (0 MB)
22 17:46:57.387890 progress 15 % (1 MB)
23 17:46:57.389495 progress 20 % (1 MB)
24 17:46:57.391073 progress 25 % (2 MB)
25 17:46:57.392667 progress 30 % (2 MB)
26 17:46:57.394144 progress 35 % (2 MB)
27 17:46:57.395741 progress 40 % (3 MB)
28 17:46:57.397315 progress 45 % (3 MB)
29 17:46:57.398976 progress 50 % (4 MB)
30 17:46:57.400546 progress 55 % (4 MB)
31 17:46:57.402095 progress 60 % (4 MB)
32 17:46:57.403544 progress 65 % (5 MB)
33 17:46:57.405118 progress 70 % (5 MB)
34 17:46:57.406668 progress 75 % (6 MB)
35 17:46:57.408194 progress 80 % (6 MB)
36 17:46:57.409818 progress 85 % (6 MB)
37 17:46:57.411379 progress 90 % (7 MB)
38 17:46:57.412896 progress 95 % (7 MB)
39 17:46:57.414368 progress 100 % (8 MB)
40 17:46:57.414542 8 MB downloaded in 0.03 s (246.46 MB/s)
41 17:46:57.414678 end: 1.1.1 http-download (duration 00:00:00) [common]
43 17:46:57.414874 end: 1.1 download-retry (duration 00:00:00) [common]
44 17:46:57.414940 start: 1.2 download-retry (timeout 00:10:00) [common]
45 17:46:57.415007 start: 1.2.1 http-download (timeout 00:10:00) [common]
46 17:46:57.415121 downloading http://storage.kernelci.org/cip/linux-4.4.y-st-rc/v4.4-st20-1778-gc774a35d86d2/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/kernel/bzImage
47 17:46:57.415187 saving as /var/lib/lava/dispatcher/tmp/11712741/tftp-deploy-ljrl3t7v/kernel/bzImage
48 17:46:57.415236 total size: 8490896 (8 MB)
49 17:46:57.415284 No compression specified
50 17:46:57.416220 progress 0 % (0 MB)
51 17:46:57.417779 progress 5 % (0 MB)
52 17:46:57.419337 progress 10 % (0 MB)
53 17:46:57.420965 progress 15 % (1 MB)
54 17:46:57.422548 progress 20 % (1 MB)
55 17:46:57.424094 progress 25 % (2 MB)
56 17:46:57.425690 progress 30 % (2 MB)
57 17:46:57.427244 progress 35 % (2 MB)
58 17:46:57.428786 progress 40 % (3 MB)
59 17:46:57.430341 progress 45 % (3 MB)
60 17:46:57.431898 progress 50 % (4 MB)
61 17:46:57.433476 progress 55 % (4 MB)
62 17:46:57.434991 progress 60 % (4 MB)
63 17:46:57.436536 progress 65 % (5 MB)
64 17:46:57.438060 progress 70 % (5 MB)
65 17:46:57.439571 progress 75 % (6 MB)
66 17:46:57.441087 progress 80 % (6 MB)
67 17:46:57.442605 progress 85 % (6 MB)
68 17:46:57.444150 progress 90 % (7 MB)
69 17:46:57.445689 progress 95 % (7 MB)
70 17:46:57.447224 progress 100 % (8 MB)
71 17:46:57.447319 8 MB downloaded in 0.03 s (252.43 MB/s)
72 17:46:57.447444 end: 1.2.1 http-download (duration 00:00:00) [common]
74 17:46:57.447654 end: 1.2 download-retry (duration 00:00:00) [common]
75 17:46:57.447720 start: 1.3 download-retry (timeout 00:10:00) [common]
76 17:46:57.447783 start: 1.3.1 http-download (timeout 00:10:00) [common]
77 17:46:57.447897 downloading http://storage.kernelci.org/cip/linux-4.4.y-st-rc/v4.4-st20-1778-gc774a35d86d2/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/modules.tar.xz
78 17:46:57.447957 saving as /var/lib/lava/dispatcher/tmp/11712741/tftp-deploy-ljrl3t7v/modules/modules.tar
79 17:46:57.448003 total size: 250868 (0 MB)
80 17:46:57.448052 Using unxz to decompress xz
81 17:46:57.451095 progress 13 % (0 MB)
82 17:46:57.451394 progress 26 % (0 MB)
83 17:46:57.451602 progress 39 % (0 MB)
84 17:46:57.453175 progress 52 % (0 MB)
85 17:46:57.454864 progress 65 % (0 MB)
86 17:46:57.456492 progress 78 % (0 MB)
87 17:46:57.458181 progress 91 % (0 MB)
88 17:46:57.459660 progress 100 % (0 MB)
89 17:46:57.464576 0 MB downloaded in 0.02 s (14.44 MB/s)
90 17:46:57.464770 end: 1.3.1 http-download (duration 00:00:00) [common]
92 17:46:57.464992 end: 1.3 download-retry (duration 00:00:00) [common]
93 17:46:57.465068 start: 1.4 prepare-tftp-overlay (timeout 00:10:00) [common]
94 17:46:57.465144 start: 1.4.1 extract-nfsrootfs (timeout 00:10:00) [common]
95 17:46:57.465211 end: 1.4.1 extract-nfsrootfs (duration 00:00:00) [common]
96 17:46:57.465279 start: 1.4.2 lava-overlay (timeout 00:10:00) [common]
97 17:46:57.465489 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11712741/lava-overlay-n7ei8poq
98 17:46:57.465613 makedir: /var/lib/lava/dispatcher/tmp/11712741/lava-overlay-n7ei8poq/lava-11712741/bin
99 17:46:57.465695 makedir: /var/lib/lava/dispatcher/tmp/11712741/lava-overlay-n7ei8poq/lava-11712741/tests
100 17:46:57.465769 makedir: /var/lib/lava/dispatcher/tmp/11712741/lava-overlay-n7ei8poq/lava-11712741/results
101 17:46:57.465862 Creating /var/lib/lava/dispatcher/tmp/11712741/lava-overlay-n7ei8poq/lava-11712741/bin/lava-add-keys
102 17:46:57.465973 Creating /var/lib/lava/dispatcher/tmp/11712741/lava-overlay-n7ei8poq/lava-11712741/bin/lava-add-sources
103 17:46:57.466075 Creating /var/lib/lava/dispatcher/tmp/11712741/lava-overlay-n7ei8poq/lava-11712741/bin/lava-background-process-start
104 17:46:57.466188 Creating /var/lib/lava/dispatcher/tmp/11712741/lava-overlay-n7ei8poq/lava-11712741/bin/lava-background-process-stop
105 17:46:57.466280 Creating /var/lib/lava/dispatcher/tmp/11712741/lava-overlay-n7ei8poq/lava-11712741/bin/lava-common-functions
106 17:46:57.466380 Creating /var/lib/lava/dispatcher/tmp/11712741/lava-overlay-n7ei8poq/lava-11712741/bin/lava-echo-ipv4
107 17:46:57.466484 Creating /var/lib/lava/dispatcher/tmp/11712741/lava-overlay-n7ei8poq/lava-11712741/bin/lava-install-packages
108 17:46:57.466578 Creating /var/lib/lava/dispatcher/tmp/11712741/lava-overlay-n7ei8poq/lava-11712741/bin/lava-installed-packages
109 17:46:57.466670 Creating /var/lib/lava/dispatcher/tmp/11712741/lava-overlay-n7ei8poq/lava-11712741/bin/lava-os-build
110 17:46:57.466761 Creating /var/lib/lava/dispatcher/tmp/11712741/lava-overlay-n7ei8poq/lava-11712741/bin/lava-probe-channel
111 17:46:57.466852 Creating /var/lib/lava/dispatcher/tmp/11712741/lava-overlay-n7ei8poq/lava-11712741/bin/lava-probe-ip
112 17:46:57.466944 Creating /var/lib/lava/dispatcher/tmp/11712741/lava-overlay-n7ei8poq/lava-11712741/bin/lava-target-ip
113 17:46:57.467034 Creating /var/lib/lava/dispatcher/tmp/11712741/lava-overlay-n7ei8poq/lava-11712741/bin/lava-target-mac
114 17:46:57.467124 Creating /var/lib/lava/dispatcher/tmp/11712741/lava-overlay-n7ei8poq/lava-11712741/bin/lava-target-storage
115 17:46:57.467220 Creating /var/lib/lava/dispatcher/tmp/11712741/lava-overlay-n7ei8poq/lava-11712741/bin/lava-test-case
116 17:46:57.467313 Creating /var/lib/lava/dispatcher/tmp/11712741/lava-overlay-n7ei8poq/lava-11712741/bin/lava-test-event
117 17:46:57.467403 Creating /var/lib/lava/dispatcher/tmp/11712741/lava-overlay-n7ei8poq/lava-11712741/bin/lava-test-feedback
118 17:46:57.467495 Creating /var/lib/lava/dispatcher/tmp/11712741/lava-overlay-n7ei8poq/lava-11712741/bin/lava-test-raise
119 17:46:57.467589 Creating /var/lib/lava/dispatcher/tmp/11712741/lava-overlay-n7ei8poq/lava-11712741/bin/lava-test-reference
120 17:46:57.467682 Creating /var/lib/lava/dispatcher/tmp/11712741/lava-overlay-n7ei8poq/lava-11712741/bin/lava-test-runner
121 17:46:57.467773 Creating /var/lib/lava/dispatcher/tmp/11712741/lava-overlay-n7ei8poq/lava-11712741/bin/lava-test-set
122 17:46:57.467866 Creating /var/lib/lava/dispatcher/tmp/11712741/lava-overlay-n7ei8poq/lava-11712741/bin/lava-test-shell
123 17:46:57.467959 Updating /var/lib/lava/dispatcher/tmp/11712741/lava-overlay-n7ei8poq/lava-11712741/bin/lava-install-packages (oe)
124 17:46:57.468079 Updating /var/lib/lava/dispatcher/tmp/11712741/lava-overlay-n7ei8poq/lava-11712741/bin/lava-installed-packages (oe)
125 17:46:57.468171 Creating /var/lib/lava/dispatcher/tmp/11712741/lava-overlay-n7ei8poq/lava-11712741/environment
126 17:46:57.468250 LAVA metadata
127 17:46:57.468310 - LAVA_JOB_ID=11712741
128 17:46:57.468361 - LAVA_DISPATCHER_IP=192.168.201.1
129 17:46:57.468441 start: 1.4.2.1 lava-vland-overlay (timeout 00:10:00) [common]
130 17:46:57.468496 skipped lava-vland-overlay
131 17:46:57.468555 end: 1.4.2.1 lava-vland-overlay (duration 00:00:00) [common]
132 17:46:57.468615 start: 1.4.2.2 lava-multinode-overlay (timeout 00:10:00) [common]
133 17:46:57.468665 skipped lava-multinode-overlay
134 17:46:57.468723 end: 1.4.2.2 lava-multinode-overlay (duration 00:00:00) [common]
135 17:46:57.468783 start: 1.4.2.3 test-definition (timeout 00:10:00) [common]
136 17:46:57.468840 Loading test definitions
137 17:46:57.468910 start: 1.4.2.3.1 inline-repo-action (timeout 00:10:00) [common]
138 17:46:57.468974 Using /lava-11712741 at stage 0
139 17:46:57.469217 uuid=11712741_1.4.2.3.1 testdef=None
140 17:46:57.469292 end: 1.4.2.3.1 inline-repo-action (duration 00:00:00) [common]
141 17:46:57.469360 start: 1.4.2.3.2 test-overlay (timeout 00:10:00) [common]
142 17:46:57.469790 end: 1.4.2.3.2 test-overlay (duration 00:00:00) [common]
144 17:46:57.469975 start: 1.4.2.3.3 test-install-overlay (timeout 00:10:00) [common]
145 17:46:57.470507 end: 1.4.2.3.3 test-install-overlay (duration 00:00:00) [common]
147 17:46:57.470683 start: 1.4.2.3.4 test-runscript-overlay (timeout 00:10:00) [common]
148 17:46:57.471180 runner path: /var/lib/lava/dispatcher/tmp/11712741/lava-overlay-n7ei8poq/lava-11712741/0/tests/0_dmesg test_uuid 11712741_1.4.2.3.1
149 17:46:57.471307 end: 1.4.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
151 17:46:57.471502 start: 1.4.2.3.5 inline-repo-action (timeout 00:10:00) [common]
152 17:46:57.471558 Using /lava-11712741 at stage 1
153 17:46:57.471798 uuid=11712741_1.4.2.3.5 testdef=None
154 17:46:57.471869 end: 1.4.2.3.5 inline-repo-action (duration 00:00:00) [common]
155 17:46:57.471933 start: 1.4.2.3.6 test-overlay (timeout 00:10:00) [common]
156 17:46:57.472287 end: 1.4.2.3.6 test-overlay (duration 00:00:00) [common]
158 17:46:57.472454 start: 1.4.2.3.7 test-install-overlay (timeout 00:10:00) [common]
159 17:46:57.472957 end: 1.4.2.3.7 test-install-overlay (duration 00:00:00) [common]
161 17:46:57.473139 start: 1.4.2.3.8 test-runscript-overlay (timeout 00:10:00) [common]
162 17:46:57.473672 runner path: /var/lib/lava/dispatcher/tmp/11712741/lava-overlay-n7ei8poq/lava-11712741/1/tests/1_bootrr test_uuid 11712741_1.4.2.3.5
163 17:46:57.473791 end: 1.4.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
165 17:46:57.473945 Creating lava-test-runner.conf files
166 17:46:57.473989 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11712741/lava-overlay-n7ei8poq/lava-11712741/0 for stage 0
167 17:46:57.474052 - 0_dmesg
168 17:46:57.474113 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11712741/lava-overlay-n7ei8poq/lava-11712741/1 for stage 1
169 17:46:57.474179 - 1_bootrr
170 17:46:57.474251 end: 1.4.2.3 test-definition (duration 00:00:00) [common]
171 17:46:57.474316 start: 1.4.2.4 compress-overlay (timeout 00:10:00) [common]
172 17:46:57.480942 end: 1.4.2.4 compress-overlay (duration 00:00:00) [common]
173 17:46:57.481040 start: 1.4.2.5 persistent-nfs-overlay (timeout 00:10:00) [common]
174 17:46:57.481114 end: 1.4.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
175 17:46:57.481183 end: 1.4.2 lava-overlay (duration 00:00:00) [common]
176 17:46:57.481249 start: 1.4.3 extract-overlay-ramdisk (timeout 00:10:00) [common]
177 17:46:57.648387 end: 1.4.3 extract-overlay-ramdisk (duration 00:00:00) [common]
178 17:46:57.648636 start: 1.4.4 extract-modules (timeout 00:10:00) [common]
179 17:46:57.648735 extracting modules file /var/lib/lava/dispatcher/tmp/11712741/tftp-deploy-ljrl3t7v/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11712741/extract-overlay-ramdisk-0dl_micu/ramdisk
180 17:46:57.657787 end: 1.4.4 extract-modules (duration 00:00:00) [common]
181 17:46:57.657907 start: 1.4.5 apply-overlay-tftp (timeout 00:10:00) [common]
182 17:46:57.657985 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11712741/compress-overlay-m_clxbvy/overlay-1.4.2.4.tar.gz to ramdisk
183 17:46:57.658044 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11712741/compress-overlay-m_clxbvy/overlay-1.4.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11712741/extract-overlay-ramdisk-0dl_micu/ramdisk
184 17:46:57.664621 end: 1.4.5 apply-overlay-tftp (duration 00:00:00) [common]
185 17:46:57.664734 start: 1.4.6 configure-preseed-file (timeout 00:10:00) [common]
186 17:46:57.664821 end: 1.4.6 configure-preseed-file (duration 00:00:00) [common]
187 17:46:57.664893 start: 1.4.7 compress-ramdisk (timeout 00:10:00) [common]
188 17:46:57.664959 Building ramdisk /var/lib/lava/dispatcher/tmp/11712741/extract-overlay-ramdisk-0dl_micu/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11712741/extract-overlay-ramdisk-0dl_micu/ramdisk
189 17:46:57.720933 >> 49788 blocks
190 17:46:58.470129 rename /var/lib/lava/dispatcher/tmp/11712741/extract-overlay-ramdisk-0dl_micu/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11712741/tftp-deploy-ljrl3t7v/ramdisk/ramdisk.cpio.gz
191 17:46:58.470422 end: 1.4.7 compress-ramdisk (duration 00:00:01) [common]
192 17:46:58.470541 start: 1.4.8 prepare-kernel (timeout 00:09:59) [common]
193 17:46:58.470618 start: 1.4.8.1 prepare-fit (timeout 00:09:59) [common]
194 17:46:58.470692 No mkimage arch provided, not using FIT.
195 17:46:58.470789 end: 1.4.8.1 prepare-fit (duration 00:00:00) [common]
196 17:46:58.470852 end: 1.4.8 prepare-kernel (duration 00:00:00) [common]
197 17:46:58.470983 end: 1.4 prepare-tftp-overlay (duration 00:00:01) [common]
198 17:46:58.471055 start: 1.5 lxc-create-udev-rule-action (timeout 00:09:59) [common]
199 17:46:58.471117 No LXC device requested
200 17:46:58.471181 end: 1.5 lxc-create-udev-rule-action (duration 00:00:00) [common]
201 17:46:58.471252 start: 1.6 deploy-device-env (timeout 00:09:59) [common]
202 17:46:58.471319 end: 1.6 deploy-device-env (duration 00:00:00) [common]
203 17:46:58.471380 Checking files for TFTP limit of 4294967296 bytes.
204 17:46:58.471696 end: 1 tftp-deploy (duration 00:00:01) [common]
205 17:46:58.471780 start: 2 depthcharge-action (timeout 00:05:00) [common]
206 17:46:58.471846 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
207 17:46:58.471934 substitutions:
208 17:46:58.471985 - {DTB}: None
209 17:46:58.472032 - {INITRD}: 11712741/tftp-deploy-ljrl3t7v/ramdisk/ramdisk.cpio.gz
210 17:46:58.472077 - {KERNEL}: 11712741/tftp-deploy-ljrl3t7v/kernel/bzImage
211 17:46:58.472121 - {LAVA_MAC}: None
212 17:46:58.472163 - {PRESEED_CONFIG}: None
213 17:46:58.472206 - {PRESEED_LOCAL}: None
214 17:46:58.472248 - {RAMDISK}: 11712741/tftp-deploy-ljrl3t7v/ramdisk/ramdisk.cpio.gz
215 17:46:58.472292 - {ROOT_PART}: None
216 17:46:58.472335 - {ROOT}: None
217 17:46:58.472379 - {SERVER_IP}: 192.168.201.1
218 17:46:58.472431 - {TEE}: None
219 17:46:58.472480 Parsed boot commands:
220 17:46:58.472523 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
221 17:46:58.472681 Parsed boot commands: tftpboot 192.168.201.1 11712741/tftp-deploy-ljrl3t7v/kernel/bzImage 11712741/tftp-deploy-ljrl3t7v/kernel/cmdline 11712741/tftp-deploy-ljrl3t7v/ramdisk/ramdisk.cpio.gz
222 17:46:58.472752 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
223 17:46:58.472822 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
224 17:46:58.472891 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
225 17:46:58.472957 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
226 17:46:58.473011 Not connected, no need to disconnect.
227 17:46:58.473084 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
228 17:46:58.473144 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
229 17:46:58.473199 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh acer-cbv514-1h-34uz-brya-cbg-2'
230 17:46:58.475602 Setting prompt string to ['lava-test: # ']
231 17:46:58.475838 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
232 17:46:58.475915 end: 2.2.1 reset-connection (duration 00:00:00) [common]
233 17:46:58.475987 start: 2.2.2 reset-device (timeout 00:05:00) [common]
234 17:46:58.476056 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
235 17:46:58.476208 Calling: 'pduclient' '--daemon=localhost' '--hostname=acer-cbv514-1h-34uz-brya-cbg-2' '--port=1' '--command=reboot'
236 17:47:03.609792 >> Command sent successfully.
237 17:47:03.617736 Returned 0 in 5 seconds
238 17:47:03.718592 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
240 17:47:03.719431 end: 2.2.2 reset-device (duration 00:00:05) [common]
241 17:47:03.719705 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
242 17:47:03.719945 Setting prompt string to 'Starting depthcharge on Volmar...'
243 17:47:03.720121 Changing prompt to 'Starting depthcharge on Volmar...'
244 17:47:03.720298 depthcharge-start: Wait for prompt Starting depthcharge on Volmar... (timeout 00:05:00)
245 17:47:03.720890 [Enter `^Ec?' for help]
246 17:47:05.088989
247 17:47:05.089434
248 17:47:05.097098 coreboot-c7721883 Tue Feb 7 00:11:29 UTC 2023 bootblock starting (log level: 8)...
249 17:47:05.100801 CPU: 12th Gen Intel(R) Core(TM) i3-1215U
250 17:47:05.105048 CPU: ID 906a4, Alderlake R0 Platform, ucode: 00000423
251 17:47:05.111724 CPU: AES supported, TXT NOT supported, VT supported
252 17:47:05.118161 Cache: Level 3: Associativity = 10 Partitions = 1 Line Size = 64 Sets = 16384
253 17:47:05.121174 Cache size = 10 MiB
254 17:47:05.124481 MCH: device id 4609 (rev 04) is Alderlake-P
255 17:47:05.128103 PCH: device id 5182 (rev 01) is Raptorlake-P SKU
256 17:47:05.134704 IGD: device id 46b3 (rev 0c) is Alderlake P GT2
257 17:47:05.138557 VBOOT: Loading verstage.
258 17:47:05.142063 FMAP: Found "FLASH" version 1.1 at 0x1804000.
259 17:47:05.145047 FMAP: base = 0x0 size = 0x2000000 #areas = 37
260 17:47:05.152455 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
261 17:47:05.159590 CBFS: mcache @0xfef85600 built for 72 files, used 0xfd8 of 0x2000 bytes
262 17:47:05.166025 CBFS: Found 'fallback/verstage' @0x18a540 size 0x16ae8 in mcache @0xfef85954
263 17:47:05.169729
264 17:47:05.169806
265 17:47:05.176241 coreboot-c7721883 Tue Feb 7 00:11:29 UTC 2023 verstage starting (log level: 8)...
266 17:47:05.182922 Probing TPM I2C: I2C bus 1 version 0x3230302a
267 17:47:05.186180 DW I2C bus 1 at 0xfe022000 (400 KHz)
268 17:47:05.189357 I2C TX abort detected (00000001)
269 17:47:05.192781 cr50_i2c_read: Address write failed
270 17:47:05.205605 .done! DID_VID 0x00281ae0
271 17:47:05.209102 TPM ready after 0 ms
272 17:47:05.212740 cr50 TPM 2.0 (i2c 1:0x50 id 0x28)
273 17:47:05.225399 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.111/cr50_v3.9
274 17:47:05.232210 Current CR50_BOARD_CFG = 0x80000001, matches desired = 0x00000001
275 17:47:05.282198 tlcl_send_startup: Startup return code is 0
276 17:47:05.282322 TPM: setup succeeded
277 17:47:05.302115 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
278 17:47:05.322233 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
279 17:47:05.326375 Chrome EC: UHEPI supported
280 17:47:05.329354 Reading cr50 boot mode
281 17:47:05.344012 Cr50 says boot_mode is VERIFIED_RW(0x00).
282 17:47:05.344100 Phase 1
283 17:47:05.351877 FMAP: area GBB found @ 1805000 (458752 bytes)
284 17:47:05.357774 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
285 17:47:05.364531 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
286 17:47:05.370864 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
287 17:47:05.378409 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
288 17:47:05.381042 Recovery requested (1009000e)
289 17:47:05.387781 TPM: Extending digest for `VBOOT: boot mode` into PCR 0
290 17:47:05.403192 tlcl_extend: response is 0
291 17:47:05.409631 TPM: Digest of `VBOOT: boot mode` to PCR 0 measured
292 17:47:05.416144 TPM: Extending digest for `VBOOT: GBB HWID` into PCR 1
293 17:47:05.430761 tlcl_extend: response is 0
294 17:47:05.437502 TPM: Digest of `VBOOT: GBB HWID` to PCR 1 measured
295 17:47:05.441047 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
296 17:47:05.450836 CBFS: Found 'fallback/romstage' @0x80 size 0x1d810 in mcache @0xfef8562c
297 17:47:05.454032 BS: verstage times (exec / console): total (unknown) / 151 ms
298 17:47:05.458443
299 17:47:05.458514
300 17:47:05.465362 coreboot-c7721883 Tue Feb 7 00:11:29 UTC 2023 romstage starting (log level: 8)...
301 17:47:05.471766 VB2:vb2api_ec_sync() In recovery mode, skipping EC sync
302 17:47:05.475262 pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00
303 17:47:05.482226 gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000
304 17:47:05.485688 gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000
305 17:47:05.488920 gpe0_sts[2]: 00040000 gpe0_en[2]: 00000000
306 17:47:05.495513 gpe0_sts[3]: 00000000 gpe0_en[3]: 00082000
307 17:47:05.495889 TCO_STS: 0000 0000
308 17:47:05.498840 GEN_PMCON: d0015038 00002200
309 17:47:05.502568 GBLRST_CAUSE: 00000000 00000000
310 17:47:05.504908 HPR_CAUSE0: 00000000
311 17:47:05.504980 prev_sleep_state 5
312 17:47:05.512310 Abort disabling TXT, as CPU is not TXT capable.
313 17:47:05.519078 cse_lite: Skip switching to RW in the recovery path
314 17:47:05.522400 Boot Count incremented to 1685
315 17:47:05.525762 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
316 17:47:05.535515 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
317 17:47:05.542190 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
318 17:47:05.548990 CBFS: Found 'fspm.bin' @0x7dfc0 size 0xc0000 in mcache @0xfef8589c
319 17:47:05.552274 Chrome EC: UHEPI supported
320 17:47:05.558711 FMAP: area RECOVERY_MRC_CACHE found @ f00000 (65536 bytes)
321 17:47:05.572812 Probing TPM I2C: done! DID_VID 0x00281ae0
322 17:47:05.575981 Locality already claimed
323 17:47:05.579607 cr50 TPM 2.0 (i2c 1:0x50 id 0x28)
324 17:47:05.600214 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x100b return code 0
325 17:47:05.606279 MRC: Hash idx 0x100b comparison successful.
326 17:47:05.609494 MRC cache found, size f6c8
327 17:47:05.609842 bootmode is set to: 2
328 17:47:05.614037 EC returned error result code 3
329 17:47:05.617316 FW_CONFIG value from CBI is 0x131
330 17:47:05.623972 fw_config match found: BOOT_NVME_MASK=BOOT_NVME_ENABLED
331 17:47:05.627323 SPD index = 0
332 17:47:05.634025 CBFS: Found 'spd.bin' @0x78480 size 0x400 in mcache @0xfef857c8
333 17:47:05.637080 SPD: module type is LPDDR4X
334 17:47:05.640711 SPD: module part number is K4U6E3S4AB-MGCL
335 17:47:05.647114 SPD: banks 8, ranks 1, rows 16, columns 10, density 8192 Mb
336 17:47:05.650433 SPD: device width 16 bits, bus width 16 bits
337 17:47:05.653748 SPD: module size is 1024 MB (per channel)
338 17:47:05.748919 CBMEM:
339 17:47:05.752591 IMD: root @ 0x76fff000 254 entries.
340 17:47:05.755613 IMD: root @ 0x76ffec00 62 entries.
341 17:47:05.762847 FMAP: area RO_VPD found @ 1800000 (16384 bytes)
342 17:47:05.766107 RO_VPD is uninitialized or empty.
343 17:47:05.769496 FMAP: area RW_VPD found @ f29000 (8192 bytes)
344 17:47:05.772684 External stage cache:
345 17:47:05.776939 IMD: root @ 0x7bbff000 254 entries.
346 17:47:05.779629 IMD: root @ 0x7bbfec00 62 entries.
347 17:47:05.787143 FMAP: area RECOVERY_MRC_CACHE found @ f00000 (65536 bytes)
348 17:47:05.793899 MRC: Checking cached data update for 'RECOVERY_MRC_CACHE'.
349 17:47:05.800287 SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
350 17:47:05.803891 MRC: 'RECOVERY_MRC_CACHE' does not need update.
351 17:47:05.806967 8 DIMMs found
352 17:47:05.807362 SMM Memory Map
353 17:47:05.810232 SMRAM : 0x7b800000 0x800000
354 17:47:05.813165 Subregion 0: 0x7b800000 0x200000
355 17:47:05.816929 Subregion 1: 0x7ba00000 0x200000
356 17:47:05.820226 Subregion 2: 0x7bc00000 0x400000
357 17:47:05.823311 top_of_ram = 0x77000000
358 17:47:05.830129 MTRR Range: Start=76000000 End=77000000 (Size 1000000)
359 17:47:05.833162 MTRR Range: Start=7b800000 End=7c000000 (Size 800000)
360 17:47:05.839532 MTRR Range: Start=f9000000 End=fa000000 (Size 1000000)
361 17:47:05.846310 MTRR Range: Start=ff000000 End=0 (Size 1000000)
362 17:47:05.846388 Normal boot
363 17:47:05.853441 CBFS: Found 'fallback/postcar' @0x185000 size 0x54dc in mcache @0xfef85910
364 17:47:05.864237 Loading module at 0x76aba000 with entry 0x76aba031. filesize: 0x50e8 memsize: 0xa4a0
365 17:47:05.867460 Processing 237 relocs. Offset value of 0x74aba000
366 17:47:05.877769 BS: romstage times (exec / console): total (unknown) / 280 ms
367 17:47:05.885475
368 17:47:05.885831
369 17:47:05.891720 coreboot-c7721883 Tue Feb 7 00:11:29 UTC 2023 postcar starting (log level: 8)...
370 17:47:05.892078 Normal boot
371 17:47:05.898213 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
372 17:47:05.904895 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
373 17:47:05.911598 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
374 17:47:05.921129 CBFS: Found 'fallback/ramstage' @0x52e00 size 0x24b33 in mcache @0x76add10c
375 17:47:05.968751 Loading module at 0x76a30000 with entry 0x76a30000. filesize: 0x51f70 memsize: 0x880d0
376 17:47:05.975381 Processing 5931 relocs. Offset value of 0x72a30000
377 17:47:05.978672 BS: postcar times (exec / console): total (unknown) / 51 ms
378 17:47:05.982094
379 17:47:05.982506
380 17:47:05.988781 coreboot-c7721883 Tue Feb 7 00:11:29 UTC 2023 ramstage starting (log level: 8)...
381 17:47:05.992398 Reserving BERT start 76a1f000, size 10000
382 17:47:05.995472 Normal boot
383 17:47:05.999066 FMAP: area RO_VPD found @ 1800000 (16384 bytes)
384 17:47:06.005588 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
385 17:47:06.015725 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
386 17:47:06.018927 FMAP: area RW_VPD found @ f29000 (8192 bytes)
387 17:47:06.022137 Google Chrome EC: version:
388 17:47:06.025372 ro: volmar_v2.0.14126-e605144e9c
389 17:47:06.028822 rw: volmar_v2.0.14126-e605144e9c
390 17:47:06.031916 running image: 2
391 17:47:06.035142 ACPI _SWS is PM1 Index 8 GPE Index -1
392 17:47:06.041953 BS: BS_PRE_DEVICE entry times (exec / console): 0 / 4 ms
393 17:47:06.044983 EC returned error result code 3
394 17:47:06.048238 FW_CONFIG value from CBI is 0x131
395 17:47:06.052071 fw_config match found: BOOT_NVME_MASK=BOOT_NVME_ENABLED
396 17:47:06.058695 PCI: 00:1c.2 disabled by fw_config
397 17:47:06.061797 fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S
398 17:47:06.068292 fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S
399 17:47:06.071956 fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S
400 17:47:06.078605 fw_config match found: FPMCU_MASK=FPMCU_ENABLED
401 17:47:06.081411 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
402 17:47:06.091385 CBFS: Found 'cpu_microcode_blob.bin' @0x1d940 size 0x35400 in mcache @0x76add0ac
403 17:47:06.094708 microcode: sig=0x906a4 pf=0x80 revision=0x423
404 17:47:06.098171 microcode: Update skipped, already up-to-date
405 17:47:06.104718 CBFS: Found 'fsps.bin' @0x13e000 size 0x46fb3 in mcache @0x76add2dc
406 17:47:06.137082 Detected 6 core, 8 thread CPU.
407 17:47:06.140117 Setting up SMI for CPU
408 17:47:06.143606 IED base = 0x7bc00000
409 17:47:06.143942 IED size = 0x00400000
410 17:47:06.146515 Will perform SMM setup.
411 17:47:06.149682 CPU: 12th Gen Intel(R) Core(TM) i3-1215U.
412 17:47:06.153027 LAPIC 0x0 in XAPIC mode.
413 17:47:06.163072 Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178
414 17:47:06.166592 Processing 18 relocs. Offset value of 0x00030000
415 17:47:06.170944 Attempting to start 7 APs
416 17:47:06.174224 Waiting for 10ms after sending INIT.
417 17:47:06.187640 Waiting for SIPI to complete...
418 17:47:06.191168 LAPIC 0x1 in XAPIC mode.
419 17:47:06.191640 done.
420 17:47:06.194351 LAPIC 0x10 in XAPIC mode.
421 17:47:06.197348 LAPIC 0x9 in XAPIC mode.
422 17:47:06.200901 LAPIC 0x12 in XAPIC mode.
423 17:47:06.204158 LAPIC 0x16 in XAPIC mode.
424 17:47:06.207842 AP: slot 3 apic_id 12, MCU rev: 0x00000423
425 17:47:06.210984 AP: slot 1 apic_id 16, MCU rev: 0x00000423
426 17:47:06.214401 AP: slot 2 apic_id 10, MCU rev: 0x00000423
427 17:47:06.217351 LAPIC 0x14 in XAPIC mode.
428 17:47:06.220749 AP: slot 5 apic_id 9, MCU rev: 0x00000423
429 17:47:06.227723 AP: slot 4 apic_id 14, MCU rev: 0x00000423
430 17:47:06.230850 AP: slot 6 apic_id 1, MCU rev: 0x00000423
431 17:47:06.234409 Waiting for SIPI to complete...
432 17:47:06.234759 done.
433 17:47:06.237369 LAPIC 0x8 in XAPIC mode.
434 17:47:06.240783 AP: slot 7 apic_id 8, MCU rev: 0x00000423
435 17:47:06.244223 smm_setup_relocation_handler: enter
436 17:47:06.247380 smm_setup_relocation_handler: exit
437 17:47:06.257354 Loading module at 0x00038000 with entry 0x00038000. filesize: 0x208 memsize: 0x208
438 17:47:06.260791 Processing 11 relocs. Offset value of 0x00038000
439 17:47:06.267310 smm_module_setup_stub: stack_top = 0x7b804000
440 17:47:06.270786 smm_module_setup_stub: per cpu stack_size = 0x800
441 17:47:06.277189 smm_module_setup_stub: runtime.start32_offset = 0x4c
442 17:47:06.280570 smm_module_setup_stub: runtime.smm_size = 0x10000
443 17:47:06.287075 SMM Module: stub loaded at 38000. Will call 0x76a53094
444 17:47:06.290273 Installing permanent SMM handler to 0x7b800000
445 17:47:06.297180 smm_load_module: total_smm_space_needed e468, available -> 200000
446 17:47:06.307128 Loading module at 0x7b9f6000 with entry 0x7b9f6d5f. filesize: 0x4348 memsize: 0x9468
447 17:47:06.310480 Processing 255 relocs. Offset value of 0x7b9f6000
448 17:47:06.316874 smm_load_module: smram_start: 0x7b800000
449 17:47:06.320196 smm_load_module: smram_end: 7ba00000
450 17:47:06.323781 smm_load_module: handler start 0x7b9f6d5f
451 17:47:06.327269 smm_load_module: handler_size 98d0
452 17:47:06.330978 smm_load_module: fxsave_area 0x7b9ff000
453 17:47:06.334563 smm_load_module: fxsave_size 1000
454 17:47:06.338107 smm_load_module: CONFIG_MSEG_SIZE 0x0
455 17:47:06.344746 smm_load_module: CONFIG_BIOS_RESOURCE_LIST_SIZE 0x0
456 17:47:06.347800 smm_load_module: handler_mod_params.smbase = 0x7b800000
457 17:47:06.355008 smm_load_module: per_cpu_save_state_size = 0x400
458 17:47:06.358401 smm_load_module: num_cpus = 0x8
459 17:47:06.361559 smm_load_module: cbmemc = 0x76ade000, cbmemc_size = 0x20000
460 17:47:06.368298 smm_load_module: total_save_state_size = 0x2000
461 17:47:06.371475 smm_load_module: cpu0 entry: 7b9e6000
462 17:47:06.374930 smm_create_map: cpus allowed in one segment 30
463 17:47:06.381429 smm_create_map: min # of segments needed 1
464 17:47:06.381857 CPU 0x0
465 17:47:06.385001 smbase 7b9e6000 entry 7b9ee000
466 17:47:06.391450 ss_start 7b9f5c00 code_end 7b9ee208
467 17:47:06.391801 CPU 0x1
468 17:47:06.394777 smbase 7b9e5c00 entry 7b9edc00
469 17:47:06.398357 ss_start 7b9f5800 code_end 7b9ede08
470 17:47:06.401478 CPU 0x2
471 17:47:06.405006 smbase 7b9e5800 entry 7b9ed800
472 17:47:06.408320 ss_start 7b9f5400 code_end 7b9eda08
473 17:47:06.408671 CPU 0x3
474 17:47:06.414611 smbase 7b9e5400 entry 7b9ed400
475 17:47:06.418134 ss_start 7b9f5000 code_end 7b9ed608
476 17:47:06.418486 CPU 0x4
477 17:47:06.421269 smbase 7b9e5000 entry 7b9ed000
478 17:47:06.428602 ss_start 7b9f4c00 code_end 7b9ed208
479 17:47:06.428962 CPU 0x5
480 17:47:06.431305 smbase 7b9e4c00 entry 7b9ecc00
481 17:47:06.437780 ss_start 7b9f4800 code_end 7b9ece08
482 17:47:06.437850 CPU 0x6
483 17:47:06.441650 smbase 7b9e4800 entry 7b9ec800
484 17:47:06.444857 ss_start 7b9f4400 code_end 7b9eca08
485 17:47:06.447848 CPU 0x7
486 17:47:06.451514 smbase 7b9e4400 entry 7b9ec400
487 17:47:06.454818 ss_start 7b9f4000 code_end 7b9ec608
488 17:47:06.464445 Loading module at 0x7b9ee000 with entry 0x7b9ee000. filesize: 0x208 memsize: 0x208
489 17:47:06.468101 Processing 11 relocs. Offset value of 0x7b9ee000
490 17:47:06.474884 smm_place_entry_code: smbase 7b9e4400, stack_top 7b804000
491 17:47:06.481233 SMM Module: placing smm entry code at 7b9edc00, cpu # 0x1
492 17:47:06.487877 smm_place_entry_code: copying from 7b9ee000 to 7b9edc00 0x208 bytes
493 17:47:06.491455 SMM Module: placing smm entry code at 7b9ed800, cpu # 0x2
494 17:47:06.497718 smm_place_entry_code: copying from 7b9ee000 to 7b9ed800 0x208 bytes
495 17:47:06.504333 SMM Module: placing smm entry code at 7b9ed400, cpu # 0x3
496 17:47:06.511150 smm_place_entry_code: copying from 7b9ee000 to 7b9ed400 0x208 bytes
497 17:47:06.517602 SMM Module: placing smm entry code at 7b9ed000, cpu # 0x4
498 17:47:06.524807 smm_place_entry_code: copying from 7b9ee000 to 7b9ed000 0x208 bytes
499 17:47:06.531651 SMM Module: placing smm entry code at 7b9ecc00, cpu # 0x5
500 17:47:06.538027 smm_place_entry_code: copying from 7b9ee000 to 7b9ecc00 0x208 bytes
501 17:47:06.541203 SMM Module: placing smm entry code at 7b9ec800, cpu # 0x6
502 17:47:06.548400 smm_place_entry_code: copying from 7b9ee000 to 7b9ec800 0x208 bytes
503 17:47:06.555085 SMM Module: placing smm entry code at 7b9ec400, cpu # 0x7
504 17:47:06.561510 smm_place_entry_code: copying from 7b9ee000 to 7b9ec400 0x208 bytes
505 17:47:06.564972 smm_module_setup_stub: stack_top = 0x7b804000
506 17:47:06.571892 smm_module_setup_stub: per cpu stack_size = 0x800
507 17:47:06.577978 smm_module_setup_stub: runtime.start32_offset = 0x4c
508 17:47:06.581254 smm_module_setup_stub: runtime.smm_size = 0x200000
509 17:47:06.587941 SMM Module: stub loaded at 7b9ee000. Will call 0x7b9f6d5f
510 17:47:06.591578 Clearing SMI status registers
511 17:47:06.594763 SMI_STS: PM1
512 17:47:06.595109 PM1_STS: PWRBTN
513 17:47:06.604451 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b9e6000, cpu = 0
514 17:47:06.604800 In relocation handler: CPU 0
515 17:47:06.611221 New SMBASE=0x7b9e6000 IEDBASE=0x7bc00000
516 17:47:06.614710 Writing SMRR. base = 0x7b800006, mask=0xff800c00
517 17:47:06.617512 Relocation complete.
518 17:47:06.624234 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b9e4800, cpu = 6
519 17:47:06.627707 In relocation handler: CPU 6
520 17:47:06.630893 New SMBASE=0x7b9e4800 IEDBASE=0x7bc00000
521 17:47:06.634012 Relocation complete.
522 17:47:06.641124 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b9e5000, cpu = 4
523 17:47:06.644290 In relocation handler: CPU 4
524 17:47:06.647510 New SMBASE=0x7b9e5000 IEDBASE=0x7bc00000
525 17:47:06.654263 Writing SMRR. base = 0x7b800006, mask=0xff800c00
526 17:47:06.654334 Relocation complete.
527 17:47:06.660948 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b9e5c00, cpu = 1
528 17:47:06.664011 In relocation handler: CPU 1
529 17:47:06.667601 New SMBASE=0x7b9e5c00 IEDBASE=0x7bc00000
530 17:47:06.674055 Writing SMRR. base = 0x7b800006, mask=0xff800c00
531 17:47:06.677394 Relocation complete.
532 17:47:06.684280 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b9e5800, cpu = 2
533 17:47:06.687521 In relocation handler: CPU 2
534 17:47:06.690694 New SMBASE=0x7b9e5800 IEDBASE=0x7bc00000
535 17:47:06.694284 Writing SMRR. base = 0x7b800006, mask=0xff800c00
536 17:47:06.697515 Relocation complete.
537 17:47:06.704386 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b9e5400, cpu = 3
538 17:47:06.707898 In relocation handler: CPU 3
539 17:47:06.710869 New SMBASE=0x7b9e5400 IEDBASE=0x7bc00000
540 17:47:06.717395 Writing SMRR. base = 0x7b800006, mask=0xff800c00
541 17:47:06.717473 Relocation complete.
542 17:47:06.724574 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b9e4c00, cpu = 5
543 17:47:06.727744 In relocation handler: CPU 5
544 17:47:06.733882 New SMBASE=0x7b9e4c00 IEDBASE=0x7bc00000
545 17:47:06.734188 Relocation complete.
546 17:47:06.740917 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b9e4400, cpu = 7
547 17:47:06.744314 In relocation handler: CPU 7
548 17:47:06.747480 New SMBASE=0x7b9e4400 IEDBASE=0x7bc00000
549 17:47:06.754190 Writing SMRR. base = 0x7b800006, mask=0xff800c00
550 17:47:06.757634 Relocation complete.
551 17:47:06.757994 Initializing CPU #0
552 17:47:06.760699 CPU: vendor Intel device 906a4
553 17:47:06.764138 CPU: family 06, model 9a, stepping 04
554 17:47:06.767264 Clearing out pending MCEs
555 17:47:06.770816 cpu: energy policy set to 7
556 17:47:06.773889 Turbo is available but hidden
557 17:47:06.777673 Turbo is available and visible
558 17:47:06.780841 microcode: Update skipped, already up-to-date
559 17:47:06.783931 CPU #0 initialized
560 17:47:06.784292 Initializing CPU #6
561 17:47:06.787576 Initializing CPU #3
562 17:47:06.790815 Initializing CPU #4
563 17:47:06.791166 Initializing CPU #2
564 17:47:06.794278 Initializing CPU #1
565 17:47:06.797326 CPU: vendor Intel device 906a4
566 17:47:06.800900 CPU: family 06, model 9a, stepping 04
567 17:47:06.804027 CPU: vendor Intel device 906a4
568 17:47:06.807103 CPU: family 06, model 9a, stepping 04
569 17:47:06.810752 Clearing out pending MCEs
570 17:47:06.814058 CPU: vendor Intel device 906a4
571 17:47:06.817350 CPU: family 06, model 9a, stepping 04
572 17:47:06.820343 CPU: vendor Intel device 906a4
573 17:47:06.823808 CPU: family 06, model 9a, stepping 04
574 17:47:06.828057 Clearing out pending MCEs
575 17:47:06.830443 Clearing out pending MCEs
576 17:47:06.830739 cpu: energy policy set to 7
577 17:47:06.833799 cpu: energy policy set to 7
578 17:47:06.836978 Clearing out pending MCEs
579 17:47:06.840603 microcode: Update skipped, already up-to-date
580 17:47:06.843793 CPU #2 initialized
581 17:47:06.847262 cpu: energy policy set to 7
582 17:47:06.850562 cpu: energy policy set to 7
583 17:47:06.854151 microcode: Update skipped, already up-to-date
584 17:47:06.857122 CPU #1 initialized
585 17:47:06.860538 microcode: Update skipped, already up-to-date
586 17:47:06.863713 CPU #3 initialized
587 17:47:06.866909 microcode: Update skipped, already up-to-date
588 17:47:06.870270 CPU #4 initialized
589 17:47:06.873731 CPU: vendor Intel device 906a4
590 17:47:06.877229 CPU: family 06, model 9a, stepping 04
591 17:47:06.877331 Initializing CPU #7
592 17:47:06.880435 Initializing CPU #5
593 17:47:06.883726 CPU: vendor Intel device 906a4
594 17:47:06.887300 CPU: family 06, model 9a, stepping 04
595 17:47:06.890430 CPU: vendor Intel device 906a4
596 17:47:06.893767 CPU: family 06, model 9a, stepping 04
597 17:47:06.897105 Clearing out pending MCEs
598 17:47:06.900546 Clearing out pending MCEs
599 17:47:06.903926 Clearing out pending MCEs
600 17:47:06.904445 cpu: energy policy set to 7
601 17:47:06.907443 cpu: energy policy set to 7
602 17:47:06.910198 cpu: energy policy set to 7
603 17:47:06.917060 microcode: Update skipped, already up-to-date
604 17:47:06.917585 CPU #5 initialized
605 17:47:06.923692 microcode: Update skipped, already up-to-date
606 17:47:06.924197 CPU #7 initialized
607 17:47:06.927032 microcode: Update skipped, already up-to-date
608 17:47:06.930150 CPU #6 initialized
609 17:47:06.933227 bsp_do_flight_plan done after 695 msecs.
610 17:47:06.937173 CPU: frequency set to 4400 MHz
611 17:47:06.940095 Enabling SMIs.
612 17:47:06.947044 BS: BS_DEV_INIT_CHIPS entry times (exec / console): 379 / 520 ms
613 17:47:06.960165 Probing TPM I2C: done! DID_VID 0x00281ae0
614 17:47:06.963246 Locality already claimed
615 17:47:06.966658 cr50 TPM 2.0 (i2c 1:0x50 id 0x28)
616 17:47:06.978032 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.111/cr50_v3.9
617 17:47:06.981260 Enabling GPIO PM b/c CR50 has long IRQ pulse support
618 17:47:06.987940 fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S
619 17:47:06.995532 CBFS: Found 'vbt.bin' @0x7d8c0 size 0x4e9 in mcache @0x76add214
620 17:47:06.998935 Found a VBT of 9216 bytes after decompression
621 17:47:07.002493 PCI 1.0, PIN A, using IRQ #16
622 17:47:07.006154 PCI 2.0, PIN A, using IRQ #17
623 17:47:07.009213 PCI 4.0, PIN A, using IRQ #18
624 17:47:07.012219 PCI 5.0, PIN A, using IRQ #16
625 17:47:07.016152 PCI 6.0, PIN A, using IRQ #16
626 17:47:07.019205 PCI 6.2, PIN C, using IRQ #18
627 17:47:07.019555 PCI 7.0, PIN A, using IRQ #19
628 17:47:07.022610 PCI 7.1, PIN B, using IRQ #20
629 17:47:07.026074 PCI 7.2, PIN C, using IRQ #21
630 17:47:07.029047 PCI 7.3, PIN D, using IRQ #22
631 17:47:07.032378 PCI 8.0, PIN A, using IRQ #23
632 17:47:07.035692 PCI D.0, PIN A, using IRQ #17
633 17:47:07.039319 PCI D.1, PIN B, using IRQ #19
634 17:47:07.042617 PCI 10.0, PIN A, using IRQ #24
635 17:47:07.045975 PCI 10.1, PIN B, using IRQ #25
636 17:47:07.048901 PCI 10.6, PIN C, using IRQ #20
637 17:47:07.052360 PCI 10.7, PIN D, using IRQ #21
638 17:47:07.055552 PCI 11.0, PIN A, using IRQ #26
639 17:47:07.059006 PCI 11.1, PIN B, using IRQ #27
640 17:47:07.062216 PCI 11.2, PIN C, using IRQ #28
641 17:47:07.066043 PCI 11.3, PIN D, using IRQ #29
642 17:47:07.069078 PCI 12.0, PIN A, using IRQ #30
643 17:47:07.069553 PCI 12.6, PIN B, using IRQ #31
644 17:47:07.072502 PCI 12.7, PIN C, using IRQ #22
645 17:47:07.075864 PCI 13.0, PIN A, using IRQ #32
646 17:47:07.079168 PCI 13.1, PIN B, using IRQ #33
647 17:47:07.082412 PCI 13.2, PIN C, using IRQ #34
648 17:47:07.085705 PCI 13.3, PIN D, using IRQ #35
649 17:47:07.089327 PCI 14.0, PIN B, using IRQ #23
650 17:47:07.092530 PCI 14.1, PIN A, using IRQ #36
651 17:47:07.095720 PCI 14.3, PIN C, using IRQ #17
652 17:47:07.098963 PCI 15.0, PIN A, using IRQ #37
653 17:47:07.102478 PCI 15.1, PIN B, using IRQ #38
654 17:47:07.105785 PCI 15.2, PIN C, using IRQ #39
655 17:47:07.109051 PCI 15.3, PIN D, using IRQ #40
656 17:47:07.112361 PCI 16.0, PIN A, using IRQ #18
657 17:47:07.115675 PCI 16.1, PIN B, using IRQ #19
658 17:47:07.119027 PCI 16.2, PIN C, using IRQ #20
659 17:47:07.122490 PCI 16.3, PIN D, using IRQ #21
660 17:47:07.122844 PCI 16.4, PIN A, using IRQ #18
661 17:47:07.125539 PCI 16.5, PIN B, using IRQ #19
662 17:47:07.128892 PCI 17.0, PIN A, using IRQ #22
663 17:47:07.132146 PCI 19.0, PIN A, using IRQ #41
664 17:47:07.135314 PCI 19.1, PIN B, using IRQ #42
665 17:47:07.139120 PCI 19.2, PIN C, using IRQ #43
666 17:47:07.142699 PCI 1C.0, PIN A, using IRQ #16
667 17:47:07.145366 PCI 1C.1, PIN B, using IRQ #17
668 17:47:07.148880 PCI 1C.2, PIN C, using IRQ #18
669 17:47:07.152076 PCI 1C.3, PIN D, using IRQ #19
670 17:47:07.155299 PCI 1C.4, PIN A, using IRQ #16
671 17:47:07.158830 PCI 1C.5, PIN B, using IRQ #17
672 17:47:07.162090 PCI 1C.6, PIN C, using IRQ #18
673 17:47:07.164809 PCI 1C.7, PIN D, using IRQ #19
674 17:47:07.168598 PCI 1D.0, PIN A, using IRQ #16
675 17:47:07.172103 PCI 1D.1, PIN B, using IRQ #17
676 17:47:07.175515 PCI 1D.2, PIN C, using IRQ #18
677 17:47:07.175846 PCI 1D.3, PIN D, using IRQ #19
678 17:47:07.178700 PCI 1E.0, PIN A, using IRQ #23
679 17:47:07.181679 PCI 1E.1, PIN B, using IRQ #20
680 17:47:07.185103 PCI 1E.2, PIN C, using IRQ #44
681 17:47:07.188466 PCI 1E.3, PIN D, using IRQ #45
682 17:47:07.192386 PCI 1F.3, PIN B, using IRQ #22
683 17:47:07.195627 PCI 1F.4, PIN C, using IRQ #23
684 17:47:07.200437 PCI 1F.6, PIN D, using IRQ #20
685 17:47:07.202008 PCI 1F.7, PIN A, using IRQ #21
686 17:47:07.205359 IRQ: Using dynamically assigned PCI IO-APIC IRQs
687 17:47:07.215502 WEAK: src/soc/intel/alderlake/fsp_params.c/mainboard_silicon_init_params called
688 17:47:07.380581 FSPS returned 0
689 17:47:07.383684 Executing Phase 1 of FspMultiPhaseSiInit
690 17:47:07.393546 FSP MultiPhaseSiInit src/soc/intel/alderlake/fsp_params.c/platform_fsp_multi_phase_init_cb called
691 17:47:07.397237 port C0 DISC req: usage 1 usb3 1 usb2 1
692 17:47:07.400383 Raw Buffer output 0 00000111
693 17:47:07.403632 Raw Buffer output 1 00000000
694 17:47:07.407338 pmc_send_ipc_cmd succeeded
695 17:47:07.413769 port C1 DISC req: usage 1 usb3 3 usb2 3
696 17:47:07.413829 Raw Buffer output 0 00000331
697 17:47:07.416988 Raw Buffer output 1 00000000
698 17:47:07.421432 pmc_send_ipc_cmd succeeded
699 17:47:07.425116 Detected 6 core, 8 thread CPU.
700 17:47:07.428276 Detected 6 core, 8 thread CPU.
701 17:47:07.433616 Detected 6 core, 8 thread CPU.
702 17:47:07.437165 Detected 6 core, 8 thread CPU.
703 17:47:07.440441 Detected 6 core, 8 thread CPU.
704 17:47:07.443731 Detected 6 core, 8 thread CPU.
705 17:47:07.446960 Detected 6 core, 8 thread CPU.
706 17:47:07.450580 Detected 6 core, 8 thread CPU.
707 17:47:07.453847 Detected 6 core, 8 thread CPU.
708 17:47:07.457036 Detected 6 core, 8 thread CPU.
709 17:47:07.460336 Detected 6 core, 8 thread CPU.
710 17:47:07.463822 Detected 6 core, 8 thread CPU.
711 17:47:07.467232 Detected 6 core, 8 thread CPU.
712 17:47:07.470323 Detected 6 core, 8 thread CPU.
713 17:47:07.473661 Detected 6 core, 8 thread CPU.
714 17:47:07.477208 Detected 6 core, 8 thread CPU.
715 17:47:07.480432 Detected 6 core, 8 thread CPU.
716 17:47:07.483645 Detected 6 core, 8 thread CPU.
717 17:47:07.487050 Detected 6 core, 8 thread CPU.
718 17:47:07.490528 Detected 6 core, 8 thread CPU.
719 17:47:07.493969 Detected 6 core, 8 thread CPU.
720 17:47:07.494030 Detected 6 core, 8 thread CPU.
721 17:47:07.783672 Detected 6 core, 8 thread CPU.
722 17:47:07.786876 Detected 6 core, 8 thread CPU.
723 17:47:07.790169 Detected 6 core, 8 thread CPU.
724 17:47:07.793570 Detected 6 core, 8 thread CPU.
725 17:47:07.796586 Detected 6 core, 8 thread CPU.
726 17:47:07.799881 Detected 6 core, 8 thread CPU.
727 17:47:07.803463 Detected 6 core, 8 thread CPU.
728 17:47:07.806527 Detected 6 core, 8 thread CPU.
729 17:47:07.810003 Detected 6 core, 8 thread CPU.
730 17:47:07.813160 Detected 6 core, 8 thread CPU.
731 17:47:07.816631 Detected 6 core, 8 thread CPU.
732 17:47:07.819977 Detected 6 core, 8 thread CPU.
733 17:47:07.823441 Detected 6 core, 8 thread CPU.
734 17:47:07.826630 Detected 6 core, 8 thread CPU.
735 17:47:07.829916 Detected 6 core, 8 thread CPU.
736 17:47:07.833097 Detected 6 core, 8 thread CPU.
737 17:47:07.836706 Detected 6 core, 8 thread CPU.
738 17:47:07.840340 Detected 6 core, 8 thread CPU.
739 17:47:07.843099 Detected 6 core, 8 thread CPU.
740 17:47:07.846638 Detected 6 core, 8 thread CPU.
741 17:47:07.846719 Display FSP Version Info HOB
742 17:47:07.849947 Reference Code - CPU = c.0.65.70
743 17:47:07.853506 uCode Version = 0.0.4.23
744 17:47:07.856649 TXT ACM version = ff.ff.ff.ffff
745 17:47:07.859994 Reference Code - ME = c.0.65.70
746 17:47:07.863311 MEBx version = 0.0.0.0
747 17:47:07.866702 ME Firmware Version = Consumer SKU
748 17:47:07.869988 Reference Code - PCH = c.0.65.70
749 17:47:07.873125 PCH-CRID Status = Disabled
750 17:47:07.876769 PCH-CRID Original Value = ff.ff.ff.ffff
751 17:47:07.879948 PCH-CRID New Value = ff.ff.ff.ffff
752 17:47:07.883394 OPROM - RST - RAID = ff.ff.ff.ffff
753 17:47:07.886661 PCH Hsio Version = 4.0.0.0
754 17:47:07.890097 Reference Code - SA - System Agent = c.0.65.70
755 17:47:07.893358 Reference Code - MRC = 0.0.3.80
756 17:47:07.896681 SA - PCIe Version = c.0.65.70
757 17:47:07.900029 SA-CRID Status = Disabled
758 17:47:07.903397 SA-CRID Original Value = 0.0.0.4
759 17:47:07.906822 SA-CRID New Value = 0.0.0.4
760 17:47:07.910190 OPROM - VBIOS = ff.ff.ff.ffff
761 17:47:07.913357 IO Manageability Engine FW Version = 24.0.4.0
762 17:47:07.916650 PHY Build Version = 0.0.0.2016
763 17:47:07.920051 Thunderbolt(TM) FW Version = 0.0.0.0
764 17:47:07.926685 System Agent Manageability Engine FW Version = ff.ff.ff.ffff
765 17:47:07.933514 BS: BS_DEV_INIT_CHIPS run times (exec / console): 473 / 507 ms
766 17:47:07.936712 Enumerating buses...
767 17:47:07.940364 Show all devs... Before device enumeration.
768 17:47:07.943521 Root Device: enabled 1
769 17:47:07.943600 CPU_CLUSTER: 0: enabled 1
770 17:47:07.947095 DOMAIN: 0000: enabled 1
771 17:47:07.950198 GPIO: 0: enabled 1
772 17:47:07.953315 PCI: 00:00.0: enabled 1
773 17:47:07.953666 PCI: 00:01.0: enabled 0
774 17:47:07.956595 PCI: 00:01.1: enabled 0
775 17:47:07.960191 PCI: 00:02.0: enabled 1
776 17:47:07.960505 PCI: 00:04.0: enabled 1
777 17:47:07.963103 PCI: 00:05.0: enabled 0
778 17:47:07.966636 PCI: 00:06.0: enabled 1
779 17:47:07.969732 PCI: 00:06.2: enabled 0
780 17:47:07.969813 PCI: 00:07.0: enabled 0
781 17:47:07.973262 PCI: 00:07.1: enabled 0
782 17:47:07.976615 PCI: 00:07.2: enabled 0
783 17:47:07.979834 PCI: 00:07.3: enabled 0
784 17:47:07.979908 PCI: 00:08.0: enabled 0
785 17:47:07.982994 PCI: 00:09.0: enabled 0
786 17:47:07.986611 PCI: 00:0a.0: enabled 1
787 17:47:07.989848 PCI: 00:0d.0: enabled 1
788 17:47:07.989954 PCI: 00:0d.1: enabled 0
789 17:47:07.993248 PCI: 00:0d.2: enabled 0
790 17:47:07.996334 PCI: 00:0d.3: enabled 0
791 17:47:07.996409 PCI: 00:0e.0: enabled 0
792 17:47:07.999961 PCI: 00:10.0: enabled 0
793 17:47:08.003242 PCI: 00:10.1: enabled 0
794 17:47:08.006510 PCI: 00:10.6: enabled 0
795 17:47:08.006589 PCI: 00:10.7: enabled 0
796 17:47:08.009681 PCI: 00:12.0: enabled 0
797 17:47:08.059556 PCI: 00:12.6: enabled 0
798 17:47:08.059681 PCI: 00:12.7: enabled 0
799 17:47:08.059738 PCI: 00:13.0: enabled 0
800 17:47:08.059976 PCI: 00:14.0: enabled 1
801 17:47:08.060028 PCI: 00:14.1: enabled 0
802 17:47:08.060073 PCI: 00:14.2: enabled 1
803 17:47:08.060115 PCI: 00:14.3: enabled 1
804 17:47:08.060174 PCI: 00:15.0: enabled 1
805 17:47:08.060232 PCI: 00:15.1: enabled 1
806 17:47:08.060278 PCI: 00:15.2: enabled 0
807 17:47:08.060629 PCI: 00:15.3: enabled 1
808 17:47:08.060705 PCI: 00:16.0: enabled 1
809 17:47:08.060754 PCI: 00:16.1: enabled 0
810 17:47:08.061115 PCI: 00:16.2: enabled 0
811 17:47:08.061167 PCI: 00:16.3: enabled 0
812 17:47:08.061524 PCI: 00:16.4: enabled 0
813 17:47:08.061588 PCI: 00:16.5: enabled 0
814 17:47:08.061631 PCI: 00:17.0: enabled 1
815 17:47:08.061845 PCI: 00:19.0: enabled 0
816 17:47:08.061893 PCI: 00:19.1: enabled 1
817 17:47:08.064835 PCI: 00:19.2: enabled 0
818 17:47:08.064893 PCI: 00:1a.0: enabled 0
819 17:47:08.067988 PCI: 00:1c.0: enabled 0
820 17:47:08.068048 PCI: 00:1c.1: enabled 0
821 17:47:08.071218 PCI: 00:1c.2: enabled 0
822 17:47:08.074752 PCI: 00:1c.3: enabled 0
823 17:47:08.074809 PCI: 00:1c.4: enabled 0
824 17:47:08.077910 PCI: 00:1c.5: enabled 0
825 17:47:08.081283 PCI: 00:1c.6: enabled 0
826 17:47:08.084473 PCI: 00:1c.7: enabled 0
827 17:47:08.084530 PCI: 00:1d.0: enabled 0
828 17:47:08.087720 PCI: 00:1d.1: enabled 0
829 17:47:08.091454 PCI: 00:1d.2: enabled 0
830 17:47:08.094630 PCI: 00:1d.3: enabled 0
831 17:47:08.094697 PCI: 00:1e.0: enabled 1
832 17:47:08.097811 PCI: 00:1e.1: enabled 0
833 17:47:08.101201 PCI: 00:1e.2: enabled 0
834 17:47:08.104806 PCI: 00:1e.3: enabled 1
835 17:47:08.104862 PCI: 00:1f.0: enabled 1
836 17:47:08.108115 PCI: 00:1f.1: enabled 0
837 17:47:08.111248 PCI: 00:1f.2: enabled 1
838 17:47:08.111315 PCI: 00:1f.3: enabled 1
839 17:47:08.114532 PCI: 00:1f.4: enabled 0
840 17:47:08.118248 PCI: 00:1f.5: enabled 1
841 17:47:08.121376 PCI: 00:1f.6: enabled 0
842 17:47:08.121468 PCI: 00:1f.7: enabled 0
843 17:47:08.124805 GENERIC: 0.0: enabled 1
844 17:47:08.127872 GENERIC: 0.0: enabled 1
845 17:47:08.131435 GENERIC: 1.0: enabled 1
846 17:47:08.131500 GENERIC: 0.0: enabled 1
847 17:47:08.134593 GENERIC: 1.0: enabled 1
848 17:47:08.138115 USB0 port 0: enabled 1
849 17:47:08.138191 USB0 port 0: enabled 1
850 17:47:08.141278 GENERIC: 0.0: enabled 1
851 17:47:08.144299 I2C: 00:1a: enabled 1
852 17:47:08.147810 I2C: 00:31: enabled 1
853 17:47:08.147892 I2C: 00:32: enabled 1
854 17:47:08.151063 I2C: 00:50: enabled 1
855 17:47:08.154401 I2C: 00:10: enabled 1
856 17:47:08.154476 I2C: 00:15: enabled 1
857 17:47:08.157848 I2C: 00:2c: enabled 1
858 17:47:08.161637 GENERIC: 0.0: enabled 1
859 17:47:08.161728 SPI: 00: enabled 1
860 17:47:08.164636 PNP: 0c09.0: enabled 1
861 17:47:08.168128 GENERIC: 0.0: enabled 1
862 17:47:08.168441 USB3 port 0: enabled 1
863 17:47:08.171343 USB3 port 1: enabled 0
864 17:47:08.174596 USB3 port 2: enabled 1
865 17:47:08.177833 USB3 port 3: enabled 0
866 17:47:08.177908 USB2 port 0: enabled 1
867 17:47:08.180965 USB2 port 1: enabled 0
868 17:47:08.184484 USB2 port 2: enabled 1
869 17:47:08.184554 USB2 port 3: enabled 0
870 17:47:08.187752 USB2 port 4: enabled 0
871 17:47:08.190833 USB2 port 5: enabled 1
872 17:47:08.194307 USB2 port 6: enabled 0
873 17:47:08.194628 USB2 port 7: enabled 0
874 17:47:08.197735 USB2 port 8: enabled 1
875 17:47:08.200954 USB2 port 9: enabled 1
876 17:47:08.201223 USB3 port 0: enabled 1
877 17:47:08.204497 USB3 port 1: enabled 0
878 17:47:08.207551 USB3 port 2: enabled 0
879 17:47:08.207863 USB3 port 3: enabled 0
880 17:47:08.210881 GENERIC: 0.0: enabled 1
881 17:47:08.214323 GENERIC: 1.0: enabled 1
882 17:47:08.217501 APIC: 00: enabled 1
883 17:47:08.217576 APIC: 16: enabled 1
884 17:47:08.220984 APIC: 10: enabled 1
885 17:47:08.221053 APIC: 12: enabled 1
886 17:47:08.223916 APIC: 14: enabled 1
887 17:47:08.227679 APIC: 09: enabled 1
888 17:47:08.227754 APIC: 01: enabled 1
889 17:47:08.230672 APIC: 08: enabled 1
890 17:47:08.234355 Compare with tree...
891 17:47:08.234431 Root Device: enabled 1
892 17:47:08.238162 CPU_CLUSTER: 0: enabled 1
893 17:47:08.242205 APIC: 00: enabled 1
894 17:47:08.242285 APIC: 16: enabled 1
895 17:47:08.245744 APIC: 10: enabled 1
896 17:47:08.246123 APIC: 12: enabled 1
897 17:47:08.248852 APIC: 14: enabled 1
898 17:47:08.252286 APIC: 09: enabled 1
899 17:47:08.252363 APIC: 01: enabled 1
900 17:47:08.255892 APIC: 08: enabled 1
901 17:47:08.258896 DOMAIN: 0000: enabled 1
902 17:47:08.258970 GPIO: 0: enabled 1
903 17:47:08.262393 PCI: 00:00.0: enabled 1
904 17:47:08.265630 PCI: 00:01.0: enabled 0
905 17:47:08.268858 PCI: 00:01.1: enabled 0
906 17:47:08.272109 PCI: 00:02.0: enabled 1
907 17:47:08.272184 PCI: 00:04.0: enabled 1
908 17:47:08.275378 GENERIC: 0.0: enabled 1
909 17:47:08.278612 PCI: 00:05.0: enabled 0
910 17:47:08.281876 PCI: 00:06.0: enabled 1
911 17:47:08.285737 PCI: 00:06.2: enabled 0
912 17:47:08.285831 PCI: 00:08.0: enabled 0
913 17:47:08.288839 PCI: 00:09.0: enabled 0
914 17:47:08.292424 PCI: 00:0a.0: enabled 1
915 17:47:08.295483 PCI: 00:0d.0: enabled 1
916 17:47:08.299047 USB0 port 0: enabled 1
917 17:47:08.299121 USB3 port 0: enabled 1
918 17:47:08.302172 USB3 port 1: enabled 0
919 17:47:08.305300 USB3 port 2: enabled 1
920 17:47:08.308807 USB3 port 3: enabled 0
921 17:47:08.311961 PCI: 00:0d.1: enabled 0
922 17:47:08.312036 PCI: 00:0d.2: enabled 0
923 17:47:08.315262 PCI: 00:0d.3: enabled 0
924 17:47:08.319102 PCI: 00:0e.0: enabled 0
925 17:47:08.322176 PCI: 00:10.0: enabled 0
926 17:47:08.325334 PCI: 00:10.1: enabled 0
927 17:47:08.325414 PCI: 00:10.6: enabled 0
928 17:47:08.328598 PCI: 00:10.7: enabled 0
929 17:47:08.332174 PCI: 00:12.0: enabled 0
930 17:47:08.335274 PCI: 00:12.6: enabled 0
931 17:47:08.338891 PCI: 00:12.7: enabled 0
932 17:47:08.338970 PCI: 00:13.0: enabled 0
933 17:47:08.342243 PCI: 00:14.0: enabled 1
934 17:47:08.345520 USB0 port 0: enabled 1
935 17:47:08.348649 USB2 port 0: enabled 1
936 17:47:08.352187 USB2 port 1: enabled 0
937 17:47:08.352611 USB2 port 2: enabled 1
938 17:47:08.355858 USB2 port 3: enabled 0
939 17:47:08.359357 USB2 port 4: enabled 0
940 17:47:08.362512 USB2 port 5: enabled 1
941 17:47:08.365670 USB2 port 6: enabled 0
942 17:47:08.366036 USB2 port 7: enabled 0
943 17:47:08.368885 USB2 port 8: enabled 1
944 17:47:08.372369 USB2 port 9: enabled 1
945 17:47:08.375690 USB3 port 0: enabled 1
946 17:47:08.379150 USB3 port 1: enabled 0
947 17:47:08.382361 USB3 port 2: enabled 0
948 17:47:08.382708 USB3 port 3: enabled 0
949 17:47:08.385698 PCI: 00:14.1: enabled 0
950 17:47:08.388728 PCI: 00:14.2: enabled 1
951 17:47:08.392221 PCI: 00:14.3: enabled 1
952 17:47:08.395494 GENERIC: 0.0: enabled 1
953 17:47:08.395837 PCI: 00:15.0: enabled 1
954 17:47:08.398648 I2C: 00:1a: enabled 1
955 17:47:08.401912 I2C: 00:31: enabled 1
956 17:47:08.405135 I2C: 00:32: enabled 1
957 17:47:08.408239 PCI: 00:15.1: enabled 1
958 17:47:08.408314 I2C: 00:50: enabled 1
959 17:47:08.411595 PCI: 00:15.2: enabled 0
960 17:47:08.415333 PCI: 00:15.3: enabled 1
961 17:47:08.418613 I2C: 00:10: enabled 1
962 17:47:08.418689 PCI: 00:16.0: enabled 1
963 17:47:08.421822 PCI: 00:16.1: enabled 0
964 17:47:08.425124 PCI: 00:16.2: enabled 0
965 17:47:08.428093 PCI: 00:16.3: enabled 0
966 17:47:08.431865 PCI: 00:16.4: enabled 0
967 17:47:08.431940 PCI: 00:16.5: enabled 0
968 17:47:08.434715 PCI: 00:17.0: enabled 1
969 17:47:08.438114 PCI: 00:19.0: enabled 0
970 17:47:08.441689 PCI: 00:19.1: enabled 1
971 17:47:08.444943 I2C: 00:15: enabled 1
972 17:47:08.445012 I2C: 00:2c: enabled 1
973 17:47:08.448146 PCI: 00:19.2: enabled 0
974 17:47:08.451699 PCI: 00:1a.0: enabled 0
975 17:47:08.454667 PCI: 00:1e.0: enabled 1
976 17:47:08.458003 PCI: 00:1e.1: enabled 0
977 17:47:08.458077 PCI: 00:1e.2: enabled 0
978 17:47:08.461624 PCI: 00:1e.3: enabled 1
979 17:47:08.464612 SPI: 00: enabled 1
980 17:47:08.468240 PCI: 00:1f.0: enabled 1
981 17:47:08.468314 PNP: 0c09.0: enabled 1
982 17:47:08.471517 PCI: 00:1f.1: enabled 0
983 17:47:08.474649 PCI: 00:1f.2: enabled 1
984 17:47:08.478017 GENERIC: 0.0: enabled 1
985 17:47:08.481760 GENERIC: 0.0: enabled 1
986 17:47:08.484733 GENERIC: 1.0: enabled 1
987 17:47:08.485067 PCI: 00:1f.3: enabled 1
988 17:47:08.487923 PCI: 00:1f.4: enabled 0
989 17:47:08.491534 PCI: 00:1f.5: enabled 1
990 17:47:08.494507 PCI: 00:1f.6: enabled 0
991 17:47:08.497939 PCI: 00:1f.7: enabled 0
992 17:47:08.498026 Root Device scanning...
993 17:47:08.501232 scan_static_bus for Root Device
994 17:47:08.504393 CPU_CLUSTER: 0 enabled
995 17:47:08.508228 DOMAIN: 0000 enabled
996 17:47:08.508302 DOMAIN: 0000 scanning...
997 17:47:08.511302 PCI: pci_scan_bus for bus 00
998 17:47:08.514477 PCI: 00:00.0 [8086/0000] ops
999 17:47:08.517866 PCI: 00:00.0 [8086/4609] enabled
1000 17:47:08.521426 PCI: 00:02.0 [8086/0000] bus ops
1001 17:47:08.524877 PCI: 00:02.0 [8086/46b3] enabled
1002 17:47:08.528151 PCI: 00:04.0 [8086/0000] bus ops
1003 17:47:08.531164 PCI: 00:04.0 [8086/461d] enabled
1004 17:47:08.534428 PCI: 00:06.0 [8086/0000] bus ops
1005 17:47:08.537751 PCI: 00:06.0 [8086/464d] enabled
1006 17:47:08.541108 PCI: 00:08.0 [8086/464f] disabled
1007 17:47:08.544398 PCI: 00:0a.0 [8086/467d] enabled
1008 17:47:08.547933 PCI: 00:0d.0 [8086/0000] bus ops
1009 17:47:08.551006 PCI: 00:0d.0 [8086/461e] enabled
1010 17:47:08.554441 PCI: 00:14.0 [8086/0000] bus ops
1011 17:47:08.557934 PCI: 00:14.0 [8086/51ed] enabled
1012 17:47:08.561268 PCI: 00:14.2 [8086/51ef] enabled
1013 17:47:08.564422 PCI: 00:14.3 [8086/0000] bus ops
1014 17:47:08.567953 PCI: 00:14.3 [8086/51f0] enabled
1015 17:47:08.571258 PCI: 00:15.0 [8086/0000] bus ops
1016 17:47:08.574422 PCI: 00:15.0 [8086/51e8] enabled
1017 17:47:08.578004 PCI: 00:15.1 [8086/0000] bus ops
1018 17:47:08.581126 PCI: 00:15.1 [8086/51e9] enabled
1019 17:47:08.584331 PCI: 00:15.2 [8086/0000] bus ops
1020 17:47:08.591323 PCI: 00:15.2 [8086/51ea] disabled
1021 17:47:08.594482 PCI: 00:15.3 [8086/0000] bus ops
1022 17:47:08.598127 PCI: 00:15.3 [8086/51eb] enabled
1023 17:47:08.598489 PCI: 00:16.0 [8086/0000] ops
1024 17:47:08.601182 PCI: 00:16.0 [8086/51e0] enabled
1025 17:47:08.608025 PCI: Static device PCI: 00:17.0 not found, disabling it.
1026 17:47:08.611482 PCI: 00:19.0 [8086/0000] bus ops
1027 17:47:08.614621 PCI: 00:19.0 [8086/51c5] disabled
1028 17:47:08.617978 PCI: 00:19.1 [8086/0000] bus ops
1029 17:47:08.621237 PCI: 00:19.1 [8086/51c6] enabled
1030 17:47:08.624444 PCI: 00:1e.0 [8086/0000] ops
1031 17:47:08.627923 PCI: 00:1e.0 [8086/51a8] enabled
1032 17:47:08.631376 PCI: 00:1e.3 [8086/0000] bus ops
1033 17:47:08.634599 PCI: 00:1e.3 [8086/51ab] enabled
1034 17:47:08.637951 PCI: 00:1f.0 [8086/0000] bus ops
1035 17:47:08.641081 PCI: 00:1f.0 [8086/5182] enabled
1036 17:47:08.644676 RTC Init
1037 17:47:08.647906 Set power on after power failure.
1038 17:47:08.651454 Disabling Deep S3
1039 17:47:08.651953 Disabling Deep S3
1040 17:47:08.654679 Disabling Deep S4
1041 17:47:08.655134 Disabling Deep S4
1042 17:47:08.657895 Disabling Deep S5
1043 17:47:08.658361 Disabling Deep S5
1044 17:47:08.660911 PCI: 00:1f.2 [0000/0000] hidden
1045 17:47:08.664381 PCI: 00:1f.3 [8086/0000] bus ops
1046 17:47:08.668085 PCI: 00:1f.3 [8086/51c8] enabled
1047 17:47:08.671218 PCI: 00:1f.5 [8086/0000] bus ops
1048 17:47:08.674553 PCI: 00:1f.5 [8086/51a4] enabled
1049 17:47:08.678074 GPIO: 0 enabled
1050 17:47:08.681175 PCI: Leftover static devices:
1051 17:47:08.681626 PCI: 00:01.0
1052 17:47:08.681885 PCI: 00:01.1
1053 17:47:08.684567 PCI: 00:05.0
1054 17:47:08.685035 PCI: 00:06.2
1055 17:47:08.687785 PCI: 00:09.0
1056 17:47:08.688256 PCI: 00:0d.1
1057 17:47:08.691785 PCI: 00:0d.2
1058 17:47:08.692324 PCI: 00:0d.3
1059 17:47:08.692591 PCI: 00:0e.0
1060 17:47:08.694681 PCI: 00:10.0
1061 17:47:08.695135 PCI: 00:10.1
1062 17:47:08.698175 PCI: 00:10.6
1063 17:47:08.698551 PCI: 00:10.7
1064 17:47:08.698835 PCI: 00:12.0
1065 17:47:08.701275 PCI: 00:12.6
1066 17:47:08.701674 PCI: 00:12.7
1067 17:47:08.704943 PCI: 00:13.0
1068 17:47:08.705368 PCI: 00:14.1
1069 17:47:08.705759 PCI: 00:16.1
1070 17:47:08.707768 PCI: 00:16.2
1071 17:47:08.707864 PCI: 00:16.3
1072 17:47:08.710990 PCI: 00:16.4
1073 17:47:08.711096 PCI: 00:16.5
1074 17:47:08.714455 PCI: 00:17.0
1075 17:47:08.714536 PCI: 00:19.2
1076 17:47:08.714587 PCI: 00:1a.0
1077 17:47:08.717660 PCI: 00:1e.1
1078 17:47:08.717752 PCI: 00:1e.2
1079 17:47:08.721155 PCI: 00:1f.1
1080 17:47:08.721257 PCI: 00:1f.4
1081 17:47:08.721315 PCI: 00:1f.6
1082 17:47:08.724677 PCI: 00:1f.7
1083 17:47:08.727917 PCI: Check your devicetree.cb.
1084 17:47:08.727985 PCI: 00:02.0 scanning...
1085 17:47:08.734716 scan_generic_bus for PCI: 00:02.0
1086 17:47:08.738005 scan_generic_bus for PCI: 00:02.0 done
1087 17:47:08.741031 scan_bus: bus PCI: 00:02.0 finished in 7 msecs
1088 17:47:08.744336 PCI: 00:04.0 scanning...
1089 17:47:08.747695 scan_generic_bus for PCI: 00:04.0
1090 17:47:08.751245 GENERIC: 0.0 enabled
1091 17:47:08.754307 bus: PCI: 00:04.0[0]->scan_generic_bus for PCI: 00:04.0 done
1092 17:47:08.761019 scan_bus: bus PCI: 00:04.0 finished in 11 msecs
1093 17:47:08.764448 PCI: 00:06.0 scanning...
1094 17:47:08.767553 do_pci_scan_bridge for PCI: 00:06.0
1095 17:47:08.770925 PCI: pci_scan_bus for bus 01
1096 17:47:08.774408 PCI: 01:00.0 [15b7/5009] enabled
1097 17:47:08.777695 Enabling Common Clock Configuration
1098 17:47:08.780924 L1 Sub-State supported from root port 6
1099 17:47:08.784509 L1 Sub-State Support = 0x5
1100 17:47:08.787569 CommonModeRestoreTime = 0x6e
1101 17:47:08.791208 Power On Value = 0x5, Power On Scale = 0x2
1102 17:47:08.791310 ASPM: Enabled L1
1103 17:47:08.798031 PCIe: Max_Payload_Size adjusted to 256
1104 17:47:08.798453 PCI: 01:00.0: Enabled LTR
1105 17:47:08.804587 PCI: 01:00.0: Programmed LTR max latencies
1106 17:47:08.808114 scan_bus: bus PCI: 00:06.0 finished in 40 msecs
1107 17:47:08.811549 PCI: 00:0d.0 scanning...
1108 17:47:08.815299 scan_static_bus for PCI: 00:0d.0
1109 17:47:08.815769 USB0 port 0 enabled
1110 17:47:08.818686 USB0 port 0 scanning...
1111 17:47:08.821905 scan_static_bus for USB0 port 0
1112 17:47:08.824990 USB3 port 0 enabled
1113 17:47:08.825059 USB3 port 1 disabled
1114 17:47:08.828629 USB3 port 2 enabled
1115 17:47:08.828702 USB3 port 3 disabled
1116 17:47:08.831810 USB3 port 0 scanning...
1117 17:47:08.835275 scan_static_bus for USB3 port 0
1118 17:47:08.839105 scan_static_bus for USB3 port 0 done
1119 17:47:08.845431 scan_bus: bus USB3 port 0 finished in 6 msecs
1120 17:47:08.845506 USB3 port 2 scanning...
1121 17:47:08.848702 scan_static_bus for USB3 port 2
1122 17:47:08.852318 scan_static_bus for USB3 port 2 done
1123 17:47:08.858976 scan_bus: bus USB3 port 2 finished in 6 msecs
1124 17:47:08.861810 scan_static_bus for USB0 port 0 done
1125 17:47:08.865327 scan_bus: bus USB0 port 0 finished in 43 msecs
1126 17:47:08.868806 scan_static_bus for PCI: 00:0d.0 done
1127 17:47:08.875306 scan_bus: bus PCI: 00:0d.0 finished in 59 msecs
1128 17:47:08.878592 PCI: 00:14.0 scanning...
1129 17:47:08.882125 scan_static_bus for PCI: 00:14.0
1130 17:47:08.882231 USB0 port 0 enabled
1131 17:47:08.885001 USB0 port 0 scanning...
1132 17:47:08.888661 scan_static_bus for USB0 port 0
1133 17:47:08.891694 USB2 port 0 enabled
1134 17:47:08.891768 USB2 port 1 disabled
1135 17:47:08.894977 USB2 port 2 enabled
1136 17:47:08.898602 USB2 port 3 disabled
1137 17:47:08.898660 USB2 port 4 disabled
1138 17:47:08.901817 USB2 port 5 enabled
1139 17:47:08.901872 USB2 port 6 disabled
1140 17:47:08.904960 USB2 port 7 disabled
1141 17:47:08.908260 USB2 port 8 enabled
1142 17:47:08.908317 USB2 port 9 enabled
1143 17:47:08.912112 USB3 port 0 enabled
1144 17:47:08.915123 USB3 port 1 disabled
1145 17:47:08.915185 USB3 port 2 disabled
1146 17:47:08.918126 USB3 port 3 disabled
1147 17:47:08.921513 USB2 port 0 scanning...
1148 17:47:08.924802 scan_static_bus for USB2 port 0
1149 17:47:08.928284 scan_static_bus for USB2 port 0 done
1150 17:47:08.931706 scan_bus: bus USB2 port 0 finished in 6 msecs
1151 17:47:08.934816 USB2 port 2 scanning...
1152 17:47:08.938340 scan_static_bus for USB2 port 2
1153 17:47:08.941902 scan_static_bus for USB2 port 2 done
1154 17:47:08.944982 scan_bus: bus USB2 port 2 finished in 6 msecs
1155 17:47:08.948062 USB2 port 5 scanning...
1156 17:47:08.951366 scan_static_bus for USB2 port 5
1157 17:47:08.954989 scan_static_bus for USB2 port 5 done
1158 17:47:08.958046 scan_bus: bus USB2 port 5 finished in 6 msecs
1159 17:47:08.961578 USB2 port 8 scanning...
1160 17:47:08.964784 scan_static_bus for USB2 port 8
1161 17:47:08.968324 scan_static_bus for USB2 port 8 done
1162 17:47:08.974917 scan_bus: bus USB2 port 8 finished in 6 msecs
1163 17:47:08.974985 USB2 port 9 scanning...
1164 17:47:08.978161 scan_static_bus for USB2 port 9
1165 17:47:08.982034 scan_static_bus for USB2 port 9 done
1166 17:47:08.988029 scan_bus: bus USB2 port 9 finished in 6 msecs
1167 17:47:08.991681 USB3 port 0 scanning...
1168 17:47:08.994883 scan_static_bus for USB3 port 0
1169 17:47:08.998087 scan_static_bus for USB3 port 0 done
1170 17:47:09.001349 scan_bus: bus USB3 port 0 finished in 6 msecs
1171 17:47:09.005129 scan_static_bus for USB0 port 0 done
1172 17:47:09.011700 scan_bus: bus USB0 port 0 finished in 120 msecs
1173 17:47:09.014795 scan_static_bus for PCI: 00:14.0 done
1174 17:47:09.018162 scan_bus: bus PCI: 00:14.0 finished in 136 msecs
1175 17:47:09.021570 PCI: 00:14.3 scanning...
1176 17:47:09.024703 scan_static_bus for PCI: 00:14.3
1177 17:47:09.028250 GENERIC: 0.0 enabled
1178 17:47:09.031616 scan_static_bus for PCI: 00:14.3 done
1179 17:47:09.034683 scan_bus: bus PCI: 00:14.3 finished in 9 msecs
1180 17:47:09.038415 PCI: 00:15.0 scanning...
1181 17:47:09.041568 scan_static_bus for PCI: 00:15.0
1182 17:47:09.044727 I2C: 00:1a enabled
1183 17:47:09.044800 I2C: 00:31 enabled
1184 17:47:09.047955 I2C: 00:32 enabled
1185 17:47:09.051310 scan_static_bus for PCI: 00:15.0 done
1186 17:47:09.054566 scan_bus: bus PCI: 00:15.0 finished in 12 msecs
1187 17:47:09.058255 PCI: 00:15.1 scanning...
1188 17:47:09.061355 scan_static_bus for PCI: 00:15.1
1189 17:47:09.064522 I2C: 00:50 enabled
1190 17:47:09.068114 scan_static_bus for PCI: 00:15.1 done
1191 17:47:09.071198 scan_bus: bus PCI: 00:15.1 finished in 9 msecs
1192 17:47:09.074777 PCI: 00:15.3 scanning...
1193 17:47:09.078025 scan_static_bus for PCI: 00:15.3
1194 17:47:09.081051 I2C: 00:10 enabled
1195 17:47:09.084543 scan_static_bus for PCI: 00:15.3 done
1196 17:47:09.087741 scan_bus: bus PCI: 00:15.3 finished in 9 msecs
1197 17:47:09.091409 PCI: 00:19.1 scanning...
1198 17:47:09.094649 scan_static_bus for PCI: 00:19.1
1199 17:47:09.094711 I2C: 00:15 enabled
1200 17:47:09.098302 I2C: 00:2c enabled
1201 17:47:09.101293 scan_static_bus for PCI: 00:19.1 done
1202 17:47:09.108341 scan_bus: bus PCI: 00:19.1 finished in 11 msecs
1203 17:47:09.108468 PCI: 00:1e.3 scanning...
1204 17:47:09.111433 scan_generic_bus for PCI: 00:1e.3
1205 17:47:09.114607 SPI: 00 enabled
1206 17:47:09.121316 bus: PCI: 00:1e.3[0]->scan_generic_bus for PCI: 00:1e.3 done
1207 17:47:09.125029 scan_bus: bus PCI: 00:1e.3 finished in 11 msecs
1208 17:47:09.128089 PCI: 00:1f.0 scanning...
1209 17:47:09.131122 scan_static_bus for PCI: 00:1f.0
1210 17:47:09.134338 PNP: 0c09.0 enabled
1211 17:47:09.134410 PNP: 0c09.0 scanning...
1212 17:47:09.137958 scan_static_bus for PNP: 0c09.0
1213 17:47:09.141269 scan_static_bus for PNP: 0c09.0 done
1214 17:47:09.148096 scan_bus: bus PNP: 0c09.0 finished in 6 msecs
1215 17:47:09.151171 scan_static_bus for PCI: 00:1f.0 done
1216 17:47:09.154543 scan_bus: bus PCI: 00:1f.0 finished in 23 msecs
1217 17:47:09.158096 PCI: 00:1f.2 scanning...
1218 17:47:09.161133 scan_static_bus for PCI: 00:1f.2
1219 17:47:09.164279 GENERIC: 0.0 enabled
1220 17:47:09.168135 GENERIC: 0.0 scanning...
1221 17:47:09.171366 scan_static_bus for GENERIC: 0.0
1222 17:47:09.171672 GENERIC: 0.0 enabled
1223 17:47:09.174385 GENERIC: 1.0 enabled
1224 17:47:09.177778 scan_static_bus for GENERIC: 0.0 done
1225 17:47:09.181010 scan_bus: bus GENERIC: 0.0 finished in 11 msecs
1226 17:47:09.187639 scan_static_bus for PCI: 00:1f.2 done
1227 17:47:09.191047 scan_bus: bus PCI: 00:1f.2 finished in 28 msecs
1228 17:47:09.194317 PCI: 00:1f.3 scanning...
1229 17:47:09.197703 scan_static_bus for PCI: 00:1f.3
1230 17:47:09.201197 scan_static_bus for PCI: 00:1f.3 done
1231 17:47:09.204462 scan_bus: bus PCI: 00:1f.3 finished in 7 msecs
1232 17:47:09.207665 PCI: 00:1f.5 scanning...
1233 17:47:09.211325 scan_generic_bus for PCI: 00:1f.5
1234 17:47:09.214626 scan_generic_bus for PCI: 00:1f.5 done
1235 17:47:09.221197 scan_bus: bus PCI: 00:1f.5 finished in 7 msecs
1236 17:47:09.224543 scan_bus: bus DOMAIN: 0000 finished in 710 msecs
1237 17:47:09.227720 scan_static_bus for Root Device done
1238 17:47:09.234509 scan_bus: bus Root Device finished in 729 msecs
1239 17:47:09.234815 done
1240 17:47:09.241055 BS: BS_DEV_ENUMERATE run times (exec / console): 3 / 1297 ms
1241 17:47:09.244440 Chrome EC: UHEPI supported
1242 17:47:09.250903 FMAP: area UNIFIED_MRC_CACHE found @ f00000 (131072 bytes)
1243 17:47:09.258065 SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
1244 17:47:09.261140 SPI flash protection: WPSW=0 SRP0=0
1245 17:47:09.264971 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
1246 17:47:09.271312 BS: BS_DEV_ENUMERATE exit times (exec / console): 2 / 23 ms
1247 17:47:09.274230 found VGA at PCI: 00:02.0
1248 17:47:09.277921 Setting up VGA for PCI: 00:02.0
1249 17:47:09.281136 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
1250 17:47:09.287925 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
1251 17:47:09.291454 Allocating resources...
1252 17:47:09.291896 Reading resources...
1253 17:47:09.294527 Root Device read_resources bus 0 link: 0
1254 17:47:09.300986 CPU_CLUSTER: 0 read_resources bus 0 link: 0
1255 17:47:09.304368 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
1256 17:47:09.307788 DOMAIN: 0000 read_resources bus 0 link: 0
1257 17:47:09.314158 SA MMIO resource: MCHBAR -> base = 0xfedc0000, size = 0x20000
1258 17:47:09.321004 SA MMIO resource: DMIBAR -> base = 0xfeda0000, size = 0x1000
1259 17:47:09.327627 SA MMIO resource: EPBAR -> base = 0xfeda1000, size = 0x1000
1260 17:47:09.334070 SA MMIO resource: REGBAR -> base = 0xfb000000, size = 0x1000
1261 17:47:09.340489 SA MMIO resource: EDRAMBAR -> base = 0xfed80000, size = 0x4000
1262 17:47:09.347441 SA MMIO resource: CRAB_ABORT -> base = 0xfeb00000, size = 0x80000
1263 17:47:09.353745 SA MMIO resource: TPM -> base = 0xfed40000, size = 0x10000
1264 17:47:09.360514 SA MMIO resource: LT_SECURITY -> base = 0xfed50000, size = 0x20000
1265 17:47:09.363698 SA MMIO resource: APIC -> base = 0xfec00000, size = 0x100000
1266 17:47:09.373918 SA MMIO resource: PCH_RESERVED -> base = 0xfc800000, size = 0x2000000
1267 17:47:09.380155 SA MMIO resource: GFXVTBAR -> base = 0xfed90000, size = 0x1000
1268 17:47:09.383594 SA MMIO resource: IPUVTBAR -> base = 0xfed92000, size = 0x1000
1269 17:47:09.390382 SA MMIO resource: TBT0BAR -> base = 0xfed84000, size = 0x1000
1270 17:47:09.396902 SA MMIO resource: TBT1BAR -> base = 0xfed85000, size = 0x1000
1271 17:47:09.403687 SA MMIO resource: TBT2BAR -> base = 0xfed86000, size = 0x1000
1272 17:47:09.410354 SA MMIO resource: TBT3BAR -> base = 0xfed87000, size = 0x1000
1273 17:47:09.416761 SA MMIO resource: VTVC0BAR -> base = 0xfed91000, size = 0x1000
1274 17:47:09.423507 SA MMIO resource: MMCONF -> base = 0xc0000000, size = 0x10000000
1275 17:47:09.429902 SA MMIO resource: DSM -> base = 0x7c800000, size = 0x3c00000
1276 17:47:09.436289 SA MMIO resource: TSEG -> base = 0x7b800000, size = 0x800000
1277 17:47:09.439895 SA MMIO resource: GSM -> base = 0x7c000000, size = 0x800000
1278 17:47:09.446248 PCI: 00:04.0 read_resources bus 1 link: 0
1279 17:47:09.449901 PCI: 00:04.0 read_resources bus 1 link: 0 done
1280 17:47:09.452944 PCI: 00:06.0 read_resources bus 1 link: 0
1281 17:47:09.459474 PCI: 00:06.0 read_resources bus 1 link: 0 done
1282 17:47:09.463185 PCI: 00:0d.0 read_resources bus 0 link: 0
1283 17:47:09.466501 USB0 port 0 read_resources bus 0 link: 0
1284 17:47:09.473139 USB0 port 0 read_resources bus 0 link: 0 done
1285 17:47:09.476278 PCI: 00:0d.0 read_resources bus 0 link: 0 done
1286 17:47:09.479838 PCI: 00:14.0 read_resources bus 0 link: 0
1287 17:47:09.486483 USB0 port 0 read_resources bus 0 link: 0
1288 17:47:09.489773 USB0 port 0 read_resources bus 0 link: 0 done
1289 17:47:09.492898 PCI: 00:14.0 read_resources bus 0 link: 0 done
1290 17:47:09.499905 PCI: 00:14.3 read_resources bus 0 link: 0
1291 17:47:09.503291 PCI: 00:14.3 read_resources bus 0 link: 0 done
1292 17:47:09.506822 PCI: 00:15.0 read_resources bus 0 link: 0
1293 17:47:09.513008 PCI: 00:15.0 read_resources bus 0 link: 0 done
1294 17:47:09.516464 PCI: 00:15.1 read_resources bus 0 link: 0
1295 17:47:09.522966 PCI: 00:15.1 read_resources bus 0 link: 0 done
1296 17:47:09.526913 PCI: 00:15.3 read_resources bus 0 link: 0
1297 17:47:09.529729 PCI: 00:15.3 read_resources bus 0 link: 0 done
1298 17:47:09.536186 PCI: 00:19.1 read_resources bus 0 link: 0
1299 17:47:09.539517 PCI: 00:19.1 read_resources bus 0 link: 0 done
1300 17:47:09.543149 PCI: 00:1e.3 read_resources bus 2 link: 0
1301 17:47:09.549829 PCI: 00:1e.3 read_resources bus 2 link: 0 done
1302 17:47:09.553038 PCI: 00:1f.0 read_resources bus 0 link: 0
1303 17:47:09.556553 PCI: 00:1f.0 read_resources bus 0 link: 0 done
1304 17:47:09.563022 PCI: 00:1f.2 read_resources bus 0 link: 0
1305 17:47:09.566023 GENERIC: 0.0 read_resources bus 0 link: 0
1306 17:47:09.569639 GENERIC: 0.0 read_resources bus 0 link: 0 done
1307 17:47:09.576151 PCI: 00:1f.2 read_resources bus 0 link: 0 done
1308 17:47:09.579634 DOMAIN: 0000 read_resources bus 0 link: 0 done
1309 17:47:09.586319 Root Device read_resources bus 0 link: 0 done
1310 17:47:09.589304 Done reading resources.
1311 17:47:09.592833 Show resources in subtree (Root Device)...After reading.
1312 17:47:09.599415 Root Device child on link 0 CPU_CLUSTER: 0
1313 17:47:09.602589 CPU_CLUSTER: 0 child on link 0 APIC: 00
1314 17:47:09.602931 APIC: 00
1315 17:47:09.606336 APIC: 16
1316 17:47:09.606678 APIC: 10
1317 17:47:09.606919 APIC: 12
1318 17:47:09.609420 APIC: 14
1319 17:47:09.609603 APIC: 09
1320 17:47:09.609711 APIC: 01
1321 17:47:09.612728 APIC: 08
1322 17:47:09.616125 DOMAIN: 0000 child on link 0 GPIO: 0
1323 17:47:09.626228 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1324 17:47:09.636064 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100
1325 17:47:09.636418 GPIO: 0
1326 17:47:09.639816 PCI: 00:00.0
1327 17:47:09.646023 PCI: 00:00.0 resource base fedc0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 0
1328 17:47:09.656012 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 1
1329 17:47:09.666598 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1330 17:47:09.676269 PCI: 00:00.0 resource base fb000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1331 17:47:09.685987 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 4
1332 17:47:09.696195 PCI: 00:00.0 resource base feb00000 size 80000 align 0 gran 0 limit 0 flags f0000200 index 5
1333 17:47:09.702491 PCI: 00:00.0 resource base fed40000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 6
1334 17:47:09.712535 PCI: 00:00.0 resource base fed50000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 7
1335 17:47:09.722616 PCI: 00:00.0 resource base fec00000 size 100000 align 0 gran 0 limit 0 flags f0000200 index 8
1336 17:47:09.732690 PCI: 00:00.0 resource base fc800000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 9
1337 17:47:09.742269 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
1338 17:47:09.752411 PCI: 00:00.0 resource base fed92000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b
1339 17:47:09.762412 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c
1340 17:47:09.769090 PCI: 00:00.0 resource base fed85000 size 1000 align 0 gran 0 limit 0 flags f0000200 index d
1341 17:47:09.779103 PCI: 00:00.0 resource base fed86000 size 1000 align 0 gran 0 limit 0 flags f0000200 index e
1342 17:47:09.789356 PCI: 00:00.0 resource base fed87000 size 1000 align 0 gran 0 limit 0 flags f0000200 index f
1343 17:47:09.799306 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 10
1344 17:47:09.809085 PCI: 00:00.0 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 11
1345 17:47:09.818718 PCI: 00:00.0 resource base 7c800000 size 3c00000 align 0 gran 0 limit 0 flags f0000200 index 12
1346 17:47:09.828649 PCI: 00:00.0 resource base 7b800000 size 800000 align 0 gran 0 limit 0 flags f0000200 index 13
1347 17:47:09.838575 PCI: 00:00.0 resource base 7c000000 size 800000 align 0 gran 0 limit 0 flags f0000200 index 14
1348 17:47:09.845072 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 15
1349 17:47:09.856013 PCI: 00:00.0 resource base c0000 size 76f40000 align 0 gran 0 limit 0 flags e0004200 index 16
1350 17:47:09.865727 PCI: 00:00.0 resource base 77000000 size 9400000 align 0 gran 0 limit 0 flags f0000200 index 17
1351 17:47:09.875173 PCI: 00:00.0 resource base 100000000 size 17fc00000 align 0 gran 0 limit 0 flags e0004200 index 18
1352 17:47:09.885259 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 19
1353 17:47:09.894960 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 1a
1354 17:47:09.905027 PCI: 00:00.0 resource base f8000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 1b
1355 17:47:09.905458 PCI: 00:02.0
1356 17:47:09.915030 PCI: 00:02.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1357 17:47:09.925429 PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
1358 17:47:09.934811 PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
1359 17:47:09.938167 PCI: 00:04.0 child on link 0 GENERIC: 0.0
1360 17:47:09.948382 PCI: 00:04.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 201 index 10
1361 17:47:09.951511 GENERIC: 0.0
1362 17:47:09.954897 PCI: 00:06.0 child on link 0 PCI: 01:00.0
1363 17:47:09.964961 PCI: 00:06.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
1364 17:47:09.974944 PCI: 00:06.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
1365 17:47:09.981770 PCI: 00:06.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
1366 17:47:09.985114 PCI: 01:00.0
1367 17:47:09.994467 PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1368 17:47:10.004897 PCI: 01:00.0 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 20
1369 17:47:10.004980 PCI: 00:08.0
1370 17:47:10.007703 PCI: 00:0a.0
1371 17:47:10.018404 PCI: 00:0a.0 resource base 0 size 8000 align 15 gran 15 limit ffffffffffffffff flags 201 index 10
1372 17:47:10.021618 PCI: 00:0d.0 child on link 0 USB0 port 0
1373 17:47:10.031557 PCI: 00:0d.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1374 17:47:10.038000 USB0 port 0 child on link 0 USB3 port 0
1375 17:47:10.038301 USB3 port 0
1376 17:47:10.041278 USB3 port 1
1377 17:47:10.041655 USB3 port 2
1378 17:47:10.044989 USB3 port 3
1379 17:47:10.048053 PCI: 00:14.0 child on link 0 USB0 port 0
1380 17:47:10.058254 PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1381 17:47:10.061360 USB0 port 0 child on link 0 USB2 port 0
1382 17:47:10.064706 USB2 port 0
1383 17:47:10.065133 USB2 port 1
1384 17:47:10.067908 USB2 port 2
1385 17:47:10.071704 USB2 port 3
1386 17:47:10.072068 USB2 port 4
1387 17:47:10.074924 USB2 port 5
1388 17:47:10.075268 USB2 port 6
1389 17:47:10.078046 USB2 port 7
1390 17:47:10.078389 USB2 port 8
1391 17:47:10.081670 USB2 port 9
1392 17:47:10.082157 USB3 port 0
1393 17:47:10.084691 USB3 port 1
1394 17:47:10.084956 USB3 port 2
1395 17:47:10.088185 USB3 port 3
1396 17:47:10.088523 PCI: 00:14.2
1397 17:47:10.097856 PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1398 17:47:10.108046 PCI: 00:14.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
1399 17:47:10.114631 PCI: 00:14.3 child on link 0 GENERIC: 0.0
1400 17:47:10.124501 PCI: 00:14.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1401 17:47:10.124578 GENERIC: 0.0
1402 17:47:10.127797 PCI: 00:15.0 child on link 0 I2C: 00:1a
1403 17:47:10.137494 PCI: 00:15.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1404 17:47:10.140933 I2C: 00:1a
1405 17:47:10.141009 I2C: 00:31
1406 17:47:10.144198 I2C: 00:32
1407 17:47:10.147729 PCI: 00:15.1 child on link 0 I2C: 00:50
1408 17:47:10.157666 PCI: 00:15.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1409 17:47:10.161414 I2C: 00:50
1410 17:47:10.161760 PCI: 00:15.2
1411 17:47:10.164793 PCI: 00:15.3 child on link 0 I2C: 00:10
1412 17:47:10.174390 PCI: 00:15.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1413 17:47:10.177712 I2C: 00:10
1414 17:47:10.178020 PCI: 00:16.0
1415 17:47:10.187923 PCI: 00:16.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1416 17:47:10.191127 PCI: 00:19.0
1417 17:47:10.194349 PCI: 00:19.1 child on link 0 I2C: 00:15
1418 17:47:10.204155 PCI: 00:19.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1419 17:47:10.207547 I2C: 00:15
1420 17:47:10.207619 I2C: 00:2c
1421 17:47:10.210656 PCI: 00:1e.0
1422 17:47:10.220754 PCI: 00:1e.0 resource base fe03e000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1423 17:47:10.223923 PCI: 00:1e.3 child on link 0 SPI: 00
1424 17:47:10.234305 PCI: 00:1e.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1425 17:47:10.237032 SPI: 00
1426 17:47:10.240708 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1427 17:47:10.250563 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1428 17:47:10.250639 PNP: 0c09.0
1429 17:47:10.260739 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1430 17:47:10.264496 PCI: 00:1f.2 child on link 0 GENERIC: 0.0
1431 17:47:10.274430 PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0
1432 17:47:10.283844 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1
1433 17:47:10.287779 GENERIC: 0.0 child on link 0 GENERIC: 0.0
1434 17:47:10.290653 GENERIC: 0.0
1435 17:47:10.291004 GENERIC: 1.0
1436 17:47:10.294038 PCI: 00:1f.3
1437 17:47:10.303963 PCI: 00:1f.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1438 17:47:10.313853 PCI: 00:1f.3 resource base 0 size 100000 align 20 gran 20 limit ffffffffffffffff flags 201 index 20
1439 17:47:10.314196 PCI: 00:1f.5
1440 17:47:10.324094 PCI: 00:1f.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
1441 17:47:10.330639 === Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) ===
1442 17:47:10.337137 PCI: 00:06.0 io: size: 0 align: 12 gran: 12 limit: ffff
1443 17:47:10.343740 PCI: 00:06.0 io: size: 0 align: 12 gran: 12 limit: ffff done
1444 17:47:10.350236 PCI: 00:06.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
1445 17:47:10.353643 PCI: 01:00.0 10 * [0x0 - 0x3fff] mem
1446 17:47:10.356882 PCI: 01:00.0 20 * [0x4000 - 0x40ff] mem
1447 17:47:10.363697 PCI: 00:06.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
1448 17:47:10.370352 PCI: 00:06.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
1449 17:47:10.380165 PCI: 00:06.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
1450 17:47:10.387073 === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
1451 17:47:10.393720 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
1452 17:47:10.400252 update_constraints: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
1453 17:47:10.407293 update_constraints: PNP: 0c09.0 00 base 00000800 limit 000009fe io (fixed)
1454 17:47:10.417283 update_constraints: PCI: 00:1f.2 01 base 00001800 limit 000018ff io (fixed)
1455 17:47:10.420100 DOMAIN: 0000: Resource ranges:
1456 17:47:10.423496 * Base: 1000, Size: 800, Tag: 100
1457 17:47:10.426769 * Base: 1900, Size: e700, Tag: 100
1458 17:47:10.429910 PCI: 00:02.0 20 * [0x1000 - 0x103f] limit: 103f io
1459 17:47:10.437011 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
1460 17:47:10.443592 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff
1461 17:47:10.453358 update_constraints: PCI: 00:00.0 00 base fedc0000 limit feddffff mem (fixed)
1462 17:47:10.460107 update_constraints: PCI: 00:00.0 01 base feda0000 limit feda0fff mem (fixed)
1463 17:47:10.466711 update_constraints: PCI: 00:00.0 02 base feda1000 limit feda1fff mem (fixed)
1464 17:47:10.476780 update_constraints: PCI: 00:00.0 03 base fb000000 limit fb000fff mem (fixed)
1465 17:47:10.483721 update_constraints: PCI: 00:00.0 04 base fed80000 limit fed83fff mem (fixed)
1466 17:47:10.489903 update_constraints: PCI: 00:00.0 05 base feb00000 limit feb7ffff mem (fixed)
1467 17:47:10.499866 update_constraints: PCI: 00:00.0 06 base fed40000 limit fed4ffff mem (fixed)
1468 17:47:10.506706 update_constraints: PCI: 00:00.0 07 base fed50000 limit fed6ffff mem (fixed)
1469 17:47:10.513365 update_constraints: PCI: 00:00.0 08 base fec00000 limit fecfffff mem (fixed)
1470 17:47:10.523724 update_constraints: PCI: 00:00.0 09 base fc800000 limit fe7fffff mem (fixed)
1471 17:47:10.530296 update_constraints: PCI: 00:00.0 0a base fed90000 limit fed90fff mem (fixed)
1472 17:47:10.536890 update_constraints: PCI: 00:00.0 0b base fed92000 limit fed92fff mem (fixed)
1473 17:47:10.547164 update_constraints: PCI: 00:00.0 0c base fed84000 limit fed84fff mem (fixed)
1474 17:47:10.553459 update_constraints: PCI: 00:00.0 0d base fed85000 limit fed85fff mem (fixed)
1475 17:47:10.559821 update_constraints: PCI: 00:00.0 0e base fed86000 limit fed86fff mem (fixed)
1476 17:47:10.569936 update_constraints: PCI: 00:00.0 0f base fed87000 limit fed87fff mem (fixed)
1477 17:47:10.576431 update_constraints: PCI: 00:00.0 10 base fed91000 limit fed91fff mem (fixed)
1478 17:47:10.583245 update_constraints: PCI: 00:00.0 11 base c0000000 limit cfffffff mem (fixed)
1479 17:47:10.592930 update_constraints: PCI: 00:00.0 12 base 7c800000 limit 803fffff mem (fixed)
1480 17:47:10.600005 update_constraints: PCI: 00:00.0 13 base 7b800000 limit 7bffffff mem (fixed)
1481 17:47:10.606376 update_constraints: PCI: 00:00.0 14 base 7c000000 limit 7c7fffff mem (fixed)
1482 17:47:10.612639 update_constraints: PCI: 00:00.0 15 base 00000000 limit 0009ffff mem (fixed)
1483 17:47:10.623241 update_constraints: PCI: 00:00.0 16 base 000c0000 limit 76ffffff mem (fixed)
1484 17:47:10.629615 update_constraints: PCI: 00:00.0 17 base 77000000 limit 803fffff mem (fixed)
1485 17:47:10.639267 update_constraints: PCI: 00:00.0 18 base 100000000 limit 27fbfffff mem (fixed)
1486 17:47:10.646275 update_constraints: PCI: 00:00.0 19 base 000a0000 limit 000bffff mem (fixed)
1487 17:47:10.652800 update_constraints: PCI: 00:00.0 1a base 000c0000 limit 000fffff mem (fixed)
1488 17:47:10.659414 update_constraints: PCI: 00:00.0 1b base f8000000 limit f9ffffff mem (fixed)
1489 17:47:10.669309 update_constraints: PCI: 00:1e.0 10 base fe03e000 limit fe03efff mem (fixed)
1490 17:47:10.676024 update_constraints: PCI: 00:1f.2 00 base fe000000 limit fe00ffff mem (fixed)
1491 17:47:10.679432 DOMAIN: 0000: Resource ranges:
1492 17:47:10.682658 * Base: 80400000, Size: 3fc00000, Tag: 200
1493 17:47:10.689463 * Base: d0000000, Size: 28000000, Tag: 200
1494 17:47:10.692770 * Base: fa000000, Size: 1000000, Tag: 200
1495 17:47:10.695811 * Base: fb001000, Size: 17ff000, Tag: 200
1496 17:47:10.702701 * Base: fe800000, Size: 300000, Tag: 200
1497 17:47:10.705960 * Base: feb80000, Size: 80000, Tag: 200
1498 17:47:10.709163 * Base: fed00000, Size: 40000, Tag: 200
1499 17:47:10.712500 * Base: fed70000, Size: 10000, Tag: 200
1500 17:47:10.715624 * Base: fed88000, Size: 8000, Tag: 200
1501 17:47:10.722384 * Base: fed93000, Size: d000, Tag: 200
1502 17:47:10.725588 * Base: feda2000, Size: 1e000, Tag: 200
1503 17:47:10.728761 * Base: fede0000, Size: 1220000, Tag: 200
1504 17:47:10.735797 * Base: 27fc00000, Size: 7d80400000, Tag: 100200
1505 17:47:10.742649 PCI: 00:02.0 18 * [0x90000000 - 0x9fffffff] limit: 9fffffff prefmem
1506 17:47:10.749038 PCI: 00:02.0 10 * [0x81000000 - 0x81ffffff] limit: 81ffffff mem
1507 17:47:10.755738 PCI: 00:06.0 20 * [0x80400000 - 0x804fffff] limit: 804fffff mem
1508 17:47:10.762158 PCI: 00:1f.3 20 * [0x80500000 - 0x805fffff] limit: 805fffff mem
1509 17:47:10.768822 PCI: 00:04.0 10 * [0x80600000 - 0x8061ffff] limit: 8061ffff mem
1510 17:47:10.776045 PCI: 00:0d.0 10 * [0x80620000 - 0x8062ffff] limit: 8062ffff mem
1511 17:47:10.782178 PCI: 00:14.0 10 * [0x80630000 - 0x8063ffff] limit: 8063ffff mem
1512 17:47:10.789011 PCI: 00:0a.0 10 * [0x80640000 - 0x80647fff] limit: 80647fff mem
1513 17:47:10.795819 PCI: 00:14.2 10 * [0x80648000 - 0x8064bfff] limit: 8064bfff mem
1514 17:47:10.802400 PCI: 00:14.3 10 * [0x8064c000 - 0x8064ffff] limit: 8064ffff mem
1515 17:47:10.808901 PCI: 00:1f.3 10 * [0x80650000 - 0x80653fff] limit: 80653fff mem
1516 17:47:10.815465 PCI: 00:14.2 18 * [0x80654000 - 0x80654fff] limit: 80654fff mem
1517 17:47:10.822540 PCI: 00:15.0 10 * [0x80655000 - 0x80655fff] limit: 80655fff mem
1518 17:47:10.829215 PCI: 00:15.1 10 * [0x80656000 - 0x80656fff] limit: 80656fff mem
1519 17:47:10.835472 PCI: 00:15.3 10 * [0x80657000 - 0x80657fff] limit: 80657fff mem
1520 17:47:10.841842 PCI: 00:16.0 10 * [0x80658000 - 0x80658fff] limit: 80658fff mem
1521 17:47:10.848858 PCI: 00:19.1 10 * [0x80659000 - 0x80659fff] limit: 80659fff mem
1522 17:47:10.855470 PCI: 00:1e.3 10 * [0x8065a000 - 0x8065afff] limit: 8065afff mem
1523 17:47:10.861697 PCI: 00:1f.5 10 * [0x8065b000 - 0x8065bfff] limit: 8065bfff mem
1524 17:47:10.868446 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff done
1525 17:47:10.875078 PCI: 00:06.0 mem: base: 80400000 size: 100000 align: 20 gran: 20 limit: 804fffff
1526 17:47:10.878495 PCI: 00:06.0: Resource ranges:
1527 17:47:10.884925 * Base: 80400000, Size: 100000, Tag: 200
1528 17:47:10.891462 PCI: 01:00.0 10 * [0x80400000 - 0x80403fff] limit: 80403fff mem
1529 17:47:10.898151 PCI: 01:00.0 20 * [0x80404000 - 0x804040ff] limit: 804040ff mem
1530 17:47:10.904854 PCI: 00:06.0 mem: base: 80400000 size: 100000 align: 20 gran: 20 limit: 804fffff done
1531 17:47:10.911948 === Resource allocator: DOMAIN: 0000 - resource allocation complete ===
1532 17:47:10.918126 Root Device assign_resources, bus 0 link: 0
1533 17:47:10.921696 DOMAIN: 0000 assign_resources, bus 0 link: 0
1534 17:47:10.928285 PCI: 00:02.0 10 <- [0x0081000000 - 0x0081ffffff] size 0x01000000 gran 0x18 mem64
1535 17:47:10.938355 PCI: 00:02.0 18 <- [0x0090000000 - 0x009fffffff] size 0x10000000 gran 0x1c prefmem64
1536 17:47:10.945020 PCI: 00:02.0 20 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io
1537 17:47:10.954640 PCI: 00:04.0 10 <- [0x0080600000 - 0x008061ffff] size 0x00020000 gran 0x11 mem64
1538 17:47:10.958443 PCI: 00:04.0 assign_resources, bus 1 link: 0
1539 17:47:10.961831 PCI: 00:04.0 assign_resources, bus 1 link: 0 done
1540 17:47:10.971617 PCI: 00:06.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
1541 17:47:10.981262 PCI: 00:06.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
1542 17:47:10.991279 PCI: 00:06.0 20 <- [0x0080400000 - 0x00804fffff] size 0x00100000 gran 0x14 bus 01 mem
1543 17:47:10.994826 PCI: 00:06.0 assign_resources, bus 1 link: 0
1544 17:47:11.001370 PCI: 01:00.0 10 <- [0x0080400000 - 0x0080403fff] size 0x00004000 gran 0x0e mem64
1545 17:47:11.011542 PCI: 01:00.0 20 <- [0x0080404000 - 0x00804040ff] size 0x00000100 gran 0x08 mem64
1546 17:47:11.014701 PCI: 00:06.0 assign_resources, bus 1 link: 0 done
1547 17:47:11.024541 PCI: 00:0a.0 10 <- [0x0080640000 - 0x0080647fff] size 0x00008000 gran 0x0f mem64
1548 17:47:11.031191 PCI: 00:0d.0 10 <- [0x0080620000 - 0x008062ffff] size 0x00010000 gran 0x10 mem64
1549 17:47:11.034596 PCI: 00:0d.0 assign_resources, bus 0 link: 0
1550 17:47:11.041246 PCI: 00:0d.0 assign_resources, bus 0 link: 0 done
1551 17:47:11.048102 PCI: 00:14.0 10 <- [0x0080630000 - 0x008063ffff] size 0x00010000 gran 0x10 mem64
1552 17:47:11.054510 PCI: 00:14.0 assign_resources, bus 0 link: 0
1553 17:47:11.057826 PCI: 00:14.0 assign_resources, bus 0 link: 0 done
1554 17:47:11.067787 PCI: 00:14.2 10 <- [0x0080648000 - 0x008064bfff] size 0x00004000 gran 0x0e mem64
1555 17:47:11.074683 PCI: 00:14.2 18 <- [0x0080654000 - 0x0080654fff] size 0x00001000 gran 0x0c mem64
1556 17:47:11.081024 PCI: 00:14.3 10 <- [0x008064c000 - 0x008064ffff] size 0x00004000 gran 0x0e mem64
1557 17:47:11.087967 PCI: 00:14.3 assign_resources, bus 0 link: 0
1558 17:47:11.091090 PCI: 00:14.3 assign_resources, bus 0 link: 0 done
1559 17:47:11.101253 PCI: 00:15.0 10 <- [0x0080655000 - 0x0080655fff] size 0x00001000 gran 0x0c mem64
1560 17:47:11.104738 PCI: 00:15.0 assign_resources, bus 0 link: 0
1561 17:47:11.111471 PCI: 00:15.0 assign_resources, bus 0 link: 0 done
1562 17:47:11.117905 PCI: 00:15.1 10 <- [0x0080656000 - 0x0080656fff] size 0x00001000 gran 0x0c mem64
1563 17:47:11.121123 PCI: 00:15.1 assign_resources, bus 0 link: 0
1564 17:47:11.127850 PCI: 00:15.1 assign_resources, bus 0 link: 0 done
1565 17:47:11.134522 PCI: 00:15.3 10 <- [0x0080657000 - 0x0080657fff] size 0x00001000 gran 0x0c mem64
1566 17:47:11.141094 PCI: 00:15.3 assign_resources, bus 0 link: 0
1567 17:47:11.144460 PCI: 00:15.3 assign_resources, bus 0 link: 0 done
1568 17:47:11.151400 PCI: 00:16.0 10 <- [0x0080658000 - 0x0080658fff] size 0x00001000 gran 0x0c mem64
1569 17:47:11.161238 PCI: 00:19.1 10 <- [0x0080659000 - 0x0080659fff] size 0x00001000 gran 0x0c mem64
1570 17:47:11.164395 PCI: 00:19.1 assign_resources, bus 0 link: 0
1571 17:47:11.170786 PCI: 00:19.1 assign_resources, bus 0 link: 0 done
1572 17:47:11.177547 PCI: 00:1e.3 10 <- [0x008065a000 - 0x008065afff] size 0x00001000 gran 0x0c mem64
1573 17:47:11.180879 PCI: 00:1e.3 assign_resources, bus 2 link: 0
1574 17:47:11.187805 PCI: 00:1e.3 assign_resources, bus 2 link: 0 done
1575 17:47:11.191107 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1576 17:47:11.197445 PCI: 00:1f.0 assign_resources, bus 0 link: 0 done
1577 17:47:11.200675 LPC: Trying to open IO window from 800 size 1ff
1578 17:47:11.210986 PCI: 00:1f.3 10 <- [0x0080650000 - 0x0080653fff] size 0x00004000 gran 0x0e mem64
1579 17:47:11.217438 PCI: 00:1f.3 20 <- [0x0080500000 - 0x00805fffff] size 0x00100000 gran 0x14 mem64
1580 17:47:11.224359 PCI: 00:1f.5 10 <- [0x008065b000 - 0x008065bfff] size 0x00001000 gran 0x0c mem
1581 17:47:11.231119 DOMAIN: 0000 assign_resources, bus 0 link: 0 done
1582 17:47:11.234169 Root Device assign_resources, bus 0 link: 0 done
1583 17:47:11.237746 Done setting resources.
1584 17:47:11.244238 Show resources in subtree (Root Device)...After assigning values.
1585 17:47:11.247454 Root Device child on link 0 CPU_CLUSTER: 0
1586 17:47:11.254278 CPU_CLUSTER: 0 child on link 0 APIC: 00
1587 17:47:11.254692 APIC: 00
1588 17:47:11.255047 APIC: 16
1589 17:47:11.257404 APIC: 10
1590 17:47:11.257817 APIC: 12
1591 17:47:11.260978 APIC: 14
1592 17:47:11.261516 APIC: 09
1593 17:47:11.261901 APIC: 01
1594 17:47:11.263990 APIC: 08
1595 17:47:11.267350 DOMAIN: 0000 child on link 0 GPIO: 0
1596 17:47:11.277486 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1597 17:47:11.287809 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100
1598 17:47:11.288259 GPIO: 0
1599 17:47:11.290910 PCI: 00:00.0
1600 17:47:11.297493 PCI: 00:00.0 resource base fedc0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 0
1601 17:47:11.307624 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 1
1602 17:47:11.317195 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1603 17:47:11.327777 PCI: 00:00.0 resource base fb000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1604 17:47:11.337260 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 4
1605 17:47:11.347213 PCI: 00:00.0 resource base feb00000 size 80000 align 0 gran 0 limit 0 flags f0000200 index 5
1606 17:47:11.354030 PCI: 00:00.0 resource base fed40000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 6
1607 17:47:11.363955 PCI: 00:00.0 resource base fed50000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 7
1608 17:47:11.374131 PCI: 00:00.0 resource base fec00000 size 100000 align 0 gran 0 limit 0 flags f0000200 index 8
1609 17:47:11.383591 PCI: 00:00.0 resource base fc800000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 9
1610 17:47:11.393203 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
1611 17:47:11.403671 PCI: 00:00.0 resource base fed92000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b
1612 17:47:11.413314 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c
1613 17:47:11.420026 PCI: 00:00.0 resource base fed85000 size 1000 align 0 gran 0 limit 0 flags f0000200 index d
1614 17:47:11.429899 PCI: 00:00.0 resource base fed86000 size 1000 align 0 gran 0 limit 0 flags f0000200 index e
1615 17:47:11.439891 PCI: 00:00.0 resource base fed87000 size 1000 align 0 gran 0 limit 0 flags f0000200 index f
1616 17:47:11.449914 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 10
1617 17:47:11.459509 PCI: 00:00.0 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 11
1618 17:47:11.469419 PCI: 00:00.0 resource base 7c800000 size 3c00000 align 0 gran 0 limit 0 flags f0000200 index 12
1619 17:47:11.480042 PCI: 00:00.0 resource base 7b800000 size 800000 align 0 gran 0 limit 0 flags f0000200 index 13
1620 17:47:11.489534 PCI: 00:00.0 resource base 7c000000 size 800000 align 0 gran 0 limit 0 flags f0000200 index 14
1621 17:47:11.496039 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 15
1622 17:47:11.506529 PCI: 00:00.0 resource base c0000 size 76f40000 align 0 gran 0 limit 0 flags e0004200 index 16
1623 17:47:11.516245 PCI: 00:00.0 resource base 77000000 size 9400000 align 0 gran 0 limit 0 flags f0000200 index 17
1624 17:47:11.525896 PCI: 00:00.0 resource base 100000000 size 17fc00000 align 0 gran 0 limit 0 flags e0004200 index 18
1625 17:47:11.535943 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 19
1626 17:47:11.545860 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 1a
1627 17:47:11.555793 PCI: 00:00.0 resource base f8000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 1b
1628 17:47:11.555865 PCI: 00:02.0
1629 17:47:11.565648 PCI: 00:02.0 resource base 81000000 size 1000000 align 24 gran 24 limit 81ffffff flags 60000201 index 10
1630 17:47:11.579173 PCI: 00:02.0 resource base 90000000 size 10000000 align 28 gran 28 limit 9fffffff flags 60001201 index 18
1631 17:47:11.585700 PCI: 00:02.0 resource base 1000 size 40 align 6 gran 6 limit 103f flags 60000100 index 20
1632 17:47:11.592364 PCI: 00:04.0 child on link 0 GENERIC: 0.0
1633 17:47:11.602789 PCI: 00:04.0 resource base 80600000 size 20000 align 17 gran 17 limit 8061ffff flags 60000201 index 10
1634 17:47:11.603195 GENERIC: 0.0
1635 17:47:11.609302 PCI: 00:06.0 child on link 0 PCI: 01:00.0
1636 17:47:11.615739 PCI: 00:06.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 20080102 index 1c
1637 17:47:11.629042 PCI: 00:06.0 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24
1638 17:47:11.638650 PCI: 00:06.0 resource base 80400000 size 100000 align 20 gran 20 limit 804fffff flags 60080202 index 20
1639 17:47:11.641948 PCI: 01:00.0
1640 17:47:11.652014 PCI: 01:00.0 resource base 80400000 size 4000 align 14 gran 14 limit 80403fff flags 60000201 index 10
1641 17:47:11.661919 PCI: 01:00.0 resource base 80404000 size 100 align 12 gran 8 limit 804040ff flags 60000201 index 20
1642 17:47:11.661978 PCI: 00:08.0
1643 17:47:11.665423 PCI: 00:0a.0
1644 17:47:11.675574 PCI: 00:0a.0 resource base 80640000 size 8000 align 15 gran 15 limit 80647fff flags 60000201 index 10
1645 17:47:11.679013 PCI: 00:0d.0 child on link 0 USB0 port 0
1646 17:47:11.689295 PCI: 00:0d.0 resource base 80620000 size 10000 align 16 gran 16 limit 8062ffff flags 60000201 index 10
1647 17:47:11.696554 USB0 port 0 child on link 0 USB3 port 0
1648 17:47:11.696960 USB3 port 0
1649 17:47:11.699523 USB3 port 1
1650 17:47:11.699867 USB3 port 2
1651 17:47:11.702408 USB3 port 3
1652 17:47:11.705949 PCI: 00:14.0 child on link 0 USB0 port 0
1653 17:47:11.715767 PCI: 00:14.0 resource base 80630000 size 10000 align 16 gran 16 limit 8063ffff flags 60000201 index 10
1654 17:47:11.722870 USB0 port 0 child on link 0 USB2 port 0
1655 17:47:11.723228 USB2 port 0
1656 17:47:11.725496 USB2 port 1
1657 17:47:11.725766 USB2 port 2
1658 17:47:11.729102 USB2 port 3
1659 17:47:11.729425 USB2 port 4
1660 17:47:11.732273 USB2 port 5
1661 17:47:11.732620 USB2 port 6
1662 17:47:11.735644 USB2 port 7
1663 17:47:11.735989 USB2 port 8
1664 17:47:11.738658 USB2 port 9
1665 17:47:11.738732 USB3 port 0
1666 17:47:11.742488 USB3 port 1
1667 17:47:11.745724 USB3 port 2
1668 17:47:11.746050 USB3 port 3
1669 17:47:11.749030 PCI: 00:14.2
1670 17:47:11.758728 PCI: 00:14.2 resource base 80648000 size 4000 align 14 gran 14 limit 8064bfff flags 60000201 index 10
1671 17:47:11.769084 PCI: 00:14.2 resource base 80654000 size 1000 align 12 gran 12 limit 80654fff flags 60000201 index 18
1672 17:47:11.772254 PCI: 00:14.3 child on link 0 GENERIC: 0.0
1673 17:47:11.782473 PCI: 00:14.3 resource base 8064c000 size 4000 align 14 gran 14 limit 8064ffff flags 60000201 index 10
1674 17:47:11.785250 GENERIC: 0.0
1675 17:47:11.788967 PCI: 00:15.0 child on link 0 I2C: 00:1a
1676 17:47:11.798907 PCI: 00:15.0 resource base 80655000 size 1000 align 12 gran 12 limit 80655fff flags 60000201 index 10
1677 17:47:11.801921 I2C: 00:1a
1678 17:47:11.802230 I2C: 00:31
1679 17:47:11.805640 I2C: 00:32
1680 17:47:11.808553 PCI: 00:15.1 child on link 0 I2C: 00:50
1681 17:47:11.818678 PCI: 00:15.1 resource base 80656000 size 1000 align 12 gran 12 limit 80656fff flags 60000201 index 10
1682 17:47:11.822273 I2C: 00:50
1683 17:47:11.822689 PCI: 00:15.2
1684 17:47:11.825255 PCI: 00:15.3 child on link 0 I2C: 00:10
1685 17:47:11.835431 PCI: 00:15.3 resource base 80657000 size 1000 align 12 gran 12 limit 80657fff flags 60000201 index 10
1686 17:47:11.838481 I2C: 00:10
1687 17:47:11.838840 PCI: 00:16.0
1688 17:47:11.851840 PCI: 00:16.0 resource base 80658000 size 1000 align 12 gran 12 limit 80658fff flags 60000201 index 10
1689 17:47:11.851916 PCI: 00:19.0
1690 17:47:11.855477 PCI: 00:19.1 child on link 0 I2C: 00:15
1691 17:47:11.865180 PCI: 00:19.1 resource base 80659000 size 1000 align 12 gran 12 limit 80659fff flags 60000201 index 10
1692 17:47:11.868594 I2C: 00:15
1693 17:47:11.869016 I2C: 00:2c
1694 17:47:11.871608 PCI: 00:1e.0
1695 17:47:11.881681 PCI: 00:1e.0 resource base fe03e000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1696 17:47:11.884874 PCI: 00:1e.3 child on link 0 SPI: 00
1697 17:47:11.898595 PCI: 00:1e.3 resource base 8065a000 size 1000 align 12 gran 12 limit 8065afff flags 60000201 index 10
1698 17:47:11.899027 SPI: 00
1699 17:47:11.901366 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1700 17:47:11.911768 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1701 17:47:11.912201 PNP: 0c09.0
1702 17:47:11.922615 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1703 17:47:11.925227 PCI: 00:1f.2 child on link 0 GENERIC: 0.0
1704 17:47:11.935231 PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0
1705 17:47:11.944807 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1
1706 17:47:11.948328 GENERIC: 0.0 child on link 0 GENERIC: 0.0
1707 17:47:11.951429 GENERIC: 0.0
1708 17:47:11.951775 GENERIC: 1.0
1709 17:47:11.954856 PCI: 00:1f.3
1710 17:47:11.964875 PCI: 00:1f.3 resource base 80650000 size 4000 align 14 gran 14 limit 80653fff flags 60000201 index 10
1711 17:47:11.974883 PCI: 00:1f.3 resource base 80500000 size 100000 align 20 gran 20 limit 805fffff flags 60000201 index 20
1712 17:47:11.978229 PCI: 00:1f.5
1713 17:47:11.987920 PCI: 00:1f.5 resource base 8065b000 size 1000 align 12 gran 12 limit 8065bfff flags 60000200 index 10
1714 17:47:11.991454 Done allocating resources.
1715 17:47:11.998035 BS: BS_DEV_RESOURCES run times (exec / console): 2 / 2717 ms
1716 17:47:12.001245 fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S
1717 17:47:12.008164 Configure audio over I2S with MAX98373 NAU88L25B.
1718 17:47:12.011383 Enabling BT offload
1719 17:47:12.018680 BS: BS_DEV_ENABLE entry times (exec / console): 5 / 12 ms
1720 17:47:12.021868 Enabling resources...
1721 17:47:12.025217 PCI: 00:00.0 subsystem <- 8086/4609
1722 17:47:12.028978 PCI: 00:00.0 cmd <- 06
1723 17:47:12.032291 PCI: 00:02.0 subsystem <- 8086/46b3
1724 17:47:12.035262 PCI: 00:02.0 cmd <- 03
1725 17:47:12.038864 PCI: 00:04.0 subsystem <- 8086/461d
1726 17:47:12.039239 PCI: 00:04.0 cmd <- 02
1727 17:47:12.041922 PCI: 00:06.0 bridge ctrl <- 0013
1728 17:47:12.045105 PCI: 00:06.0 subsystem <- 8086/464d
1729 17:47:12.048332 PCI: 00:06.0 cmd <- 106
1730 17:47:12.051664 PCI: 00:0a.0 subsystem <- 8086/467d
1731 17:47:12.055627 PCI: 00:0a.0 cmd <- 02
1732 17:47:12.058646 PCI: 00:0d.0 subsystem <- 8086/461e
1733 17:47:12.061890 PCI: 00:0d.0 cmd <- 02
1734 17:47:12.065271 PCI: 00:14.0 subsystem <- 8086/51ed
1735 17:47:12.068441 PCI: 00:14.0 cmd <- 02
1736 17:47:12.071896 PCI: 00:14.2 subsystem <- 8086/51ef
1737 17:47:12.072245 PCI: 00:14.2 cmd <- 02
1738 17:47:12.075208 PCI: 00:14.3 subsystem <- 8086/51f0
1739 17:47:12.078774 PCI: 00:14.3 cmd <- 02
1740 17:47:12.082256 PCI: 00:15.0 subsystem <- 8086/51e8
1741 17:47:12.085106 PCI: 00:15.0 cmd <- 02
1742 17:47:12.088632 PCI: 00:15.1 subsystem <- 8086/51e9
1743 17:47:12.091950 PCI: 00:15.1 cmd <- 06
1744 17:47:12.095479 PCI: 00:15.3 subsystem <- 8086/51eb
1745 17:47:12.098730 PCI: 00:15.3 cmd <- 02
1746 17:47:12.101718 PCI: 00:16.0 subsystem <- 8086/51e0
1747 17:47:12.102066 PCI: 00:16.0 cmd <- 02
1748 17:47:12.105090 PCI: 00:19.1 subsystem <- 8086/51c6
1749 17:47:12.108189 PCI: 00:19.1 cmd <- 02
1750 17:47:12.112083 PCI: 00:1e.0 subsystem <- 8086/51a8
1751 17:47:12.115419 PCI: 00:1e.0 cmd <- 06
1752 17:47:12.118602 PCI: 00:1e.3 subsystem <- 8086/51ab
1753 17:47:12.121813 PCI: 00:1e.3 cmd <- 02
1754 17:47:12.124827 PCI: 00:1f.0 subsystem <- 8086/5182
1755 17:47:12.128442 PCI: 00:1f.0 cmd <- 407
1756 17:47:12.131466 PCI: 00:1f.3 subsystem <- 8086/51c8
1757 17:47:12.131528 PCI: 00:1f.3 cmd <- 02
1758 17:47:12.135219 PCI: 00:1f.5 subsystem <- 8086/51a4
1759 17:47:12.138630 PCI: 00:1f.5 cmd <- 406
1760 17:47:12.141457 PCI: 01:00.0 cmd <- 02
1761 17:47:12.141535 done.
1762 17:47:12.148485 BS: BS_DEV_ENABLE run times (exec / console): 1 / 122 ms
1763 17:47:12.152120 ME: Version: Unavailable
1764 17:47:12.155303 BS: BS_DEV_ENABLE exit times (exec / console): 0 / 3 ms
1765 17:47:12.158807 Initializing devices...
1766 17:47:12.159150 Root Device init
1767 17:47:12.161901 mainboard: EC init
1768 17:47:12.165127 Chrome EC: Set SMI mask to 0x0000000000000000
1769 17:47:12.172462 Chrome EC: clear events_b mask to 0x0000000000000000
1770 17:47:12.179173 Chrome EC: Set S5 LAZY WAKE mask to 0x0000000000000006
1771 17:47:12.185513 Chrome EC: Set S3 LAZY WAKE mask to 0x000000001000101e
1772 17:47:12.188868 Chrome EC: Set S0iX LAZY WAKE mask to 0x000000001808101e
1773 17:47:12.195939 Chrome EC: Set WAKE mask to 0x0000000000000000
1774 17:47:12.199037 Root Device init finished in 35 msecs
1775 17:47:12.201839 PCI: 00:00.0 init
1776 17:47:12.205467 CPU TDP = 15 Watts
1777 17:47:12.205601 CPU PL1 = 15 Watts
1778 17:47:12.209035 CPU PL2 = 55 Watts
1779 17:47:12.209377 CPU PL4 = 123 Watts
1780 17:47:12.215506 PCI: 00:00.0 init finished in 8 msecs
1781 17:47:12.215581 PCI: 00:02.0 init
1782 17:47:12.218514 GMA: Found VBT in CBFS
1783 17:47:12.222154 GMA: Found valid VBT in CBFS
1784 17:47:12.225240 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
1785 17:47:12.235369 x_res x y_res: 1920 x 1080, size: 8294400 at 0x90000000
1786 17:47:12.238948 PCI: 00:02.0 init finished in 18 msecs
1787 17:47:12.239319 PCI: 00:06.0 init
1788 17:47:12.241805 Initializing PCH PCIe bridge.
1789 17:47:12.248721 PCI: 00:06.0 init finished in 3 msecs
1790 17:47:12.249296 PCI: 00:0a.0 init
1791 17:47:12.252138 PCI: 00:0a.0 init finished in 0 msecs
1792 17:47:12.255503 PCI: 00:14.0 init
1793 17:47:12.258901 PCI: 00:14.0 init finished in 0 msecs
1794 17:47:12.259247 PCI: 00:14.2 init
1795 17:47:12.265354 PCI: 00:14.2 init finished in 0 msecs
1796 17:47:12.265732 PCI: 00:15.0 init
1797 17:47:12.268630 I2C bus 0 version 0x3230302a
1798 17:47:12.271861 DW I2C bus 0 at 0x80655000 (400 KHz)
1799 17:47:12.275550 PCI: 00:15.0 init finished in 6 msecs
1800 17:47:12.278853 PCI: 00:15.1 init
1801 17:47:12.281792 I2C bus 1 version 0x3230302a
1802 17:47:12.285412 DW I2C bus 1 at 0x80656000 (400 KHz)
1803 17:47:12.288711 PCI: 00:15.1 init finished in 6 msecs
1804 17:47:12.292183 PCI: 00:15.3 init
1805 17:47:12.292643 I2C bus 3 version 0x3230302a
1806 17:47:12.298681 DW I2C bus 3 at 0x80657000 (400 KHz)
1807 17:47:12.302319 PCI: 00:15.3 init finished in 6 msecs
1808 17:47:12.302724 PCI: 00:16.0 init
1809 17:47:12.305270 PCI: 00:16.0 init finished in 0 msecs
1810 17:47:12.308628 PCI: 00:19.1 init
1811 17:47:12.312132 I2C bus 5 version 0x3230302a
1812 17:47:12.315283 DW I2C bus 5 at 0x80659000 (400 KHz)
1813 17:47:12.318461 PCI: 00:19.1 init finished in 6 msecs
1814 17:47:12.322345 PCI: 00:1f.0 init
1815 17:47:12.325220 IOAPIC: Initializing IOAPIC at 0xfec00000
1816 17:47:12.328932 IOAPIC: ID = 0x02
1817 17:47:12.329368 IOAPIC: Dumping registers
1818 17:47:12.331845 reg 0x0000: 0x02000000
1819 17:47:12.335159 reg 0x0001: 0x00770020
1820 17:47:12.338386 reg 0x0002: 0x00000000
1821 17:47:12.338512 IOAPIC: 120 interrupts
1822 17:47:12.344871 IOAPIC: Clearing IOAPIC at 0xfec00000
1823 17:47:12.348455 IOAPIC: vector 0x00 value 0x00000000 0x00010000
1824 17:47:12.351472 IOAPIC: vector 0x01 value 0x00000000 0x00010000
1825 17:47:12.358119 IOAPIC: vector 0x02 value 0x00000000 0x00010000
1826 17:47:12.361696 IOAPIC: vector 0x03 value 0x00000000 0x00010000
1827 17:47:12.368064 IOAPIC: vector 0x04 value 0x00000000 0x00010000
1828 17:47:12.371548 IOAPIC: vector 0x05 value 0x00000000 0x00010000
1829 17:47:12.378085 IOAPIC: vector 0x06 value 0x00000000 0x00010000
1830 17:47:12.381967 IOAPIC: vector 0x07 value 0x00000000 0x00010000
1831 17:47:12.388154 IOAPIC: vector 0x08 value 0x00000000 0x00010000
1832 17:47:12.391443 IOAPIC: vector 0x09 value 0x00000000 0x00010000
1833 17:47:12.394982 IOAPIC: vector 0x0a value 0x00000000 0x00010000
1834 17:47:12.401550 IOAPIC: vector 0x0b value 0x00000000 0x00010000
1835 17:47:12.404811 IOAPIC: vector 0x0c value 0x00000000 0x00010000
1836 17:47:12.411555 IOAPIC: vector 0x0d value 0x00000000 0x00010000
1837 17:47:12.414987 IOAPIC: vector 0x0e value 0x00000000 0x00010000
1838 17:47:12.421496 IOAPIC: vector 0x0f value 0x00000000 0x00010000
1839 17:47:12.424532 IOAPIC: vector 0x10 value 0x00000000 0x00010000
1840 17:47:12.428069 IOAPIC: vector 0x11 value 0x00000000 0x00010000
1841 17:47:12.434685 IOAPIC: vector 0x12 value 0x00000000 0x00010000
1842 17:47:12.437867 IOAPIC: vector 0x13 value 0x00000000 0x00010000
1843 17:47:12.444692 IOAPIC: vector 0x14 value 0x00000000 0x00010000
1844 17:47:12.447915 IOAPIC: vector 0x15 value 0x00000000 0x00010000
1845 17:47:12.454595 IOAPIC: vector 0x16 value 0x00000000 0x00010000
1846 17:47:12.457977 IOAPIC: vector 0x17 value 0x00000000 0x00010000
1847 17:47:12.464706 IOAPIC: vector 0x18 value 0x00000000 0x00010000
1848 17:47:12.467828 IOAPIC: vector 0x19 value 0x00000000 0x00010000
1849 17:47:12.471474 IOAPIC: vector 0x1a value 0x00000000 0x00010000
1850 17:47:12.477845 IOAPIC: vector 0x1b value 0x00000000 0x00010000
1851 17:47:12.481450 IOAPIC: vector 0x1c value 0x00000000 0x00010000
1852 17:47:12.487866 IOAPIC: vector 0x1d value 0x00000000 0x00010000
1853 17:47:12.491402 IOAPIC: vector 0x1e value 0x00000000 0x00010000
1854 17:47:12.497817 IOAPIC: vector 0x1f value 0x00000000 0x00010000
1855 17:47:12.501315 IOAPIC: vector 0x20 value 0x00000000 0x00010000
1856 17:47:12.507949 IOAPIC: vector 0x21 value 0x00000000 0x00010000
1857 17:47:12.511095 IOAPIC: vector 0x22 value 0x00000000 0x00010000
1858 17:47:12.514669 IOAPIC: vector 0x23 value 0x00000000 0x00010000
1859 17:47:12.521236 IOAPIC: vector 0x24 value 0x00000000 0x00010000
1860 17:47:12.524536 IOAPIC: vector 0x25 value 0x00000000 0x00010000
1861 17:47:12.530981 IOAPIC: vector 0x26 value 0x00000000 0x00010000
1862 17:47:12.534607 IOAPIC: vector 0x27 value 0x00000000 0x00010000
1863 17:47:12.541073 IOAPIC: vector 0x28 value 0x00000000 0x00010000
1864 17:47:12.544333 IOAPIC: vector 0x29 value 0x00000000 0x00010000
1865 17:47:12.547573 IOAPIC: vector 0x2a value 0x00000000 0x00010000
1866 17:47:12.554324 IOAPIC: vector 0x2b value 0x00000000 0x00010000
1867 17:47:12.557700 IOAPIC: vector 0x2c value 0x00000000 0x00010000
1868 17:47:12.564600 IOAPIC: vector 0x2d value 0x00000000 0x00010000
1869 17:47:12.567935 IOAPIC: vector 0x2e value 0x00000000 0x00010000
1870 17:47:12.574598 IOAPIC: vector 0x2f value 0x00000000 0x00010000
1871 17:47:12.577725 IOAPIC: vector 0x30 value 0x00000000 0x00010000
1872 17:47:12.584158 IOAPIC: vector 0x31 value 0x00000000 0x00010000
1873 17:47:12.587607 IOAPIC: vector 0x32 value 0x00000000 0x00010000
1874 17:47:12.590863 IOAPIC: vector 0x33 value 0x00000000 0x00010000
1875 17:47:12.597726 IOAPIC: vector 0x34 value 0x00000000 0x00010000
1876 17:47:12.600779 IOAPIC: vector 0x35 value 0x00000000 0x00010000
1877 17:47:12.607608 IOAPIC: vector 0x36 value 0x00000000 0x00010000
1878 17:47:12.610849 IOAPIC: vector 0x37 value 0x00000000 0x00010000
1879 17:47:12.617539 IOAPIC: vector 0x38 value 0x00000000 0x00010000
1880 17:47:12.620969 IOAPIC: vector 0x39 value 0x00000000 0x00010000
1881 17:47:12.627610 IOAPIC: vector 0x3a value 0x00000000 0x00010000
1882 17:47:12.630963 IOAPIC: vector 0x3b value 0x00000000 0x00010000
1883 17:47:12.634115 IOAPIC: vector 0x3c value 0x00000000 0x00010000
1884 17:47:12.640850 IOAPIC: vector 0x3d value 0x00000000 0x00010000
1885 17:47:12.644245 IOAPIC: vector 0x3e value 0x00000000 0x00010000
1886 17:47:12.650799 IOAPIC: vector 0x3f value 0x00000000 0x00010000
1887 17:47:12.654358 IOAPIC: vector 0x40 value 0x00000000 0x00010000
1888 17:47:12.660702 IOAPIC: vector 0x41 value 0x00000000 0x00010000
1889 17:47:12.664118 IOAPIC: vector 0x42 value 0x00000000 0x00010000
1890 17:47:12.670886 IOAPIC: vector 0x43 value 0x00000000 0x00010000
1891 17:47:12.674272 IOAPIC: vector 0x44 value 0x00000000 0x00010000
1892 17:47:12.677416 IOAPIC: vector 0x45 value 0x00000000 0x00010000
1893 17:47:12.684070 IOAPIC: vector 0x46 value 0x00000000 0x00010000
1894 17:47:12.687146 IOAPIC: vector 0x47 value 0x00000000 0x00010000
1895 17:47:12.693960 IOAPIC: vector 0x48 value 0x00000000 0x00010000
1896 17:47:12.697155 IOAPIC: vector 0x49 value 0x00000000 0x00010000
1897 17:47:12.703780 IOAPIC: vector 0x4a value 0x00000000 0x00010000
1898 17:47:12.707591 IOAPIC: vector 0x4b value 0x00000000 0x00010000
1899 17:47:12.714373 IOAPIC: vector 0x4c value 0x00000000 0x00010000
1900 17:47:12.717528 IOAPIC: vector 0x4d value 0x00000000 0x00010000
1901 17:47:12.720586 IOAPIC: vector 0x4e value 0x00000000 0x00010000
1902 17:47:12.727042 IOAPIC: vector 0x4f value 0x00000000 0x00010000
1903 17:47:12.730417 IOAPIC: vector 0x50 value 0x00000000 0x00010000
1904 17:47:12.737079 IOAPIC: vector 0x51 value 0x00000000 0x00010000
1905 17:47:12.740311 IOAPIC: vector 0x52 value 0x00000000 0x00010000
1906 17:47:12.746937 IOAPIC: vector 0x53 value 0x00000000 0x00010000
1907 17:47:12.750512 IOAPIC: vector 0x54 value 0x00000000 0x00010000
1908 17:47:12.756991 IOAPIC: vector 0x55 value 0x00000000 0x00010000
1909 17:47:12.760628 IOAPIC: vector 0x56 value 0x00000000 0x00010000
1910 17:47:12.763855 IOAPIC: vector 0x57 value 0x00000000 0x00010000
1911 17:47:12.770570 IOAPIC: vector 0x58 value 0x00000000 0x00010000
1912 17:47:12.773602 IOAPIC: vector 0x59 value 0x00000000 0x00010000
1913 17:47:12.780761 IOAPIC: vector 0x5a value 0x00000000 0x00010000
1914 17:47:12.783554 IOAPIC: vector 0x5b value 0x00000000 0x00010000
1915 17:47:12.790397 IOAPIC: vector 0x5c value 0x00000000 0x00010000
1916 17:47:12.793635 IOAPIC: vector 0x5d value 0x00000000 0x00010000
1917 17:47:12.796815 IOAPIC: vector 0x5e value 0x00000000 0x00010000
1918 17:47:12.803431 IOAPIC: vector 0x5f value 0x00000000 0x00010000
1919 17:47:12.806864 IOAPIC: vector 0x60 value 0x00000000 0x00010000
1920 17:47:12.813397 IOAPIC: vector 0x61 value 0x00000000 0x00010000
1921 17:47:12.816883 IOAPIC: vector 0x62 value 0x00000000 0x00010000
1922 17:47:12.823469 IOAPIC: vector 0x63 value 0x00000000 0x00010000
1923 17:47:12.826994 IOAPIC: vector 0x64 value 0x00000000 0x00010000
1924 17:47:12.833591 IOAPIC: vector 0x65 value 0x00000000 0x00010000
1925 17:47:12.836817 IOAPIC: vector 0x66 value 0x00000000 0x00010000
1926 17:47:12.840483 IOAPIC: vector 0x67 value 0x00000000 0x00010000
1927 17:47:12.847082 IOAPIC: vector 0x68 value 0x00000000 0x00010000
1928 17:47:12.850281 IOAPIC: vector 0x69 value 0x00000000 0x00010000
1929 17:47:12.857065 IOAPIC: vector 0x6a value 0x00000000 0x00010000
1930 17:47:12.860326 IOAPIC: vector 0x6b value 0x00000000 0x00010000
1931 17:47:12.867091 IOAPIC: vector 0x6c value 0x00000000 0x00010000
1932 17:47:12.870691 IOAPIC: vector 0x6d value 0x00000000 0x00010000
1933 17:47:12.873616 IOAPIC: vector 0x6e value 0x00000000 0x00010000
1934 17:47:12.880252 IOAPIC: vector 0x6f value 0x00000000 0x00010000
1935 17:47:12.883489 IOAPIC: vector 0x70 value 0x00000000 0x00010000
1936 17:47:12.890152 IOAPIC: vector 0x71 value 0x00000000 0x00010000
1937 17:47:12.893811 IOAPIC: vector 0x72 value 0x00000000 0x00010000
1938 17:47:12.900232 IOAPIC: vector 0x73 value 0x00000000 0x00010000
1939 17:47:12.903567 IOAPIC: vector 0x74 value 0x00000000 0x00010000
1940 17:47:12.910360 IOAPIC: vector 0x75 value 0x00000000 0x00010000
1941 17:47:12.913619 IOAPIC: vector 0x76 value 0x00000000 0x00010000
1942 17:47:12.916685 IOAPIC: vector 0x77 value 0x00000000 0x00010000
1943 17:47:12.923311 IOAPIC: Bootstrap Processor Local APIC = 0x00
1944 17:47:12.926783 IOAPIC: vector 0x00 value 0x00000000 0x00000700
1945 17:47:12.933667 PCI: 00:1f.0 init finished in 607 msecs
1946 17:47:12.933742 PCI: 00:1f.2 init
1947 17:47:12.936735 apm_control: Disabling ACPI.
1948 17:47:12.940591 APMC done.
1949 17:47:12.944026 PCI: 00:1f.2 init finished in 6 msecs
1950 17:47:12.947316 PCI: 00:1f.3 init
1951 17:47:12.950784 PCI: 00:1f.3 init finished in 0 msecs
1952 17:47:12.950856 PCI: 01:00.0 init
1953 17:47:12.953978 PCI: 01:00.0 init finished in 0 msecs
1954 17:47:12.957187 PNP: 0c09.0 init
1955 17:47:12.960784 Google Chrome EC uptime: 9.313 seconds
1956 17:47:12.967167 Google Chrome AP resets since EC boot: 1
1957 17:47:12.970825 Google Chrome most recent AP reset causes:
1958 17:47:12.973777 0.342: 32775 shutdown: entering G3
1959 17:47:12.980384 Google Chrome EC reset flags at last EC boot: reset-pin | sysjump
1960 17:47:12.983752 PNP: 0c09.0 init finished in 23 msecs
1961 17:47:12.987330 GENERIC: 0.0 init
1962 17:47:12.990762 GENERIC: 0.0 init finished in 0 msecs
1963 17:47:12.990850 GENERIC: 1.0 init
1964 17:47:12.994040 GENERIC: 1.0 init finished in 0 msecs
1965 17:47:12.997537 Devices initialized
1966 17:47:13.000665 Show all devs... After init.
1967 17:47:13.004233 Root Device: enabled 1
1968 17:47:13.004306 CPU_CLUSTER: 0: enabled 1
1969 17:47:13.007523 DOMAIN: 0000: enabled 1
1970 17:47:13.010632 GPIO: 0: enabled 1
1971 17:47:13.010705 PCI: 00:00.0: enabled 1
1972 17:47:13.014107 PCI: 00:01.0: enabled 0
1973 17:47:13.017051 PCI: 00:01.1: enabled 0
1974 17:47:13.020751 PCI: 00:02.0: enabled 1
1975 17:47:13.020824 PCI: 00:04.0: enabled 1
1976 17:47:13.023892 PCI: 00:05.0: enabled 0
1977 17:47:13.027395 PCI: 00:06.0: enabled 1
1978 17:47:13.030505 PCI: 00:06.2: enabled 0
1979 17:47:13.030581 PCI: 00:07.0: enabled 0
1980 17:47:13.033797 PCI: 00:07.1: enabled 0
1981 17:47:13.037042 PCI: 00:07.2: enabled 0
1982 17:47:13.040684 PCI: 00:07.3: enabled 0
1983 17:47:13.040763 PCI: 00:08.0: enabled 0
1984 17:47:13.044217 PCI: 00:09.0: enabled 0
1985 17:47:13.047186 PCI: 00:0a.0: enabled 1
1986 17:47:13.050759 PCI: 00:0d.0: enabled 1
1987 17:47:13.050836 PCI: 00:0d.1: enabled 0
1988 17:47:13.054003 PCI: 00:0d.2: enabled 0
1989 17:47:13.057129 PCI: 00:0d.3: enabled 0
1990 17:47:13.057204 PCI: 00:0e.0: enabled 0
1991 17:47:13.060700 PCI: 00:10.0: enabled 0
1992 17:47:13.063898 PCI: 00:10.1: enabled 0
1993 17:47:13.067016 PCI: 00:10.6: enabled 0
1994 17:47:13.067088 PCI: 00:10.7: enabled 0
1995 17:47:13.070411 PCI: 00:12.0: enabled 0
1996 17:47:13.073947 PCI: 00:12.6: enabled 0
1997 17:47:13.076814 PCI: 00:12.7: enabled 0
1998 17:47:13.076887 PCI: 00:13.0: enabled 0
1999 17:47:13.080457 PCI: 00:14.0: enabled 1
2000 17:47:13.083509 PCI: 00:14.1: enabled 0
2001 17:47:13.087010 PCI: 00:14.2: enabled 1
2002 17:47:13.087083 PCI: 00:14.3: enabled 1
2003 17:47:13.090460 PCI: 00:15.0: enabled 1
2004 17:47:13.093565 PCI: 00:15.1: enabled 1
2005 17:47:13.093639 PCI: 00:15.2: enabled 0
2006 17:47:13.097099 PCI: 00:15.3: enabled 1
2007 17:47:13.100161 PCI: 00:16.0: enabled 1
2008 17:47:13.103482 PCI: 00:16.1: enabled 0
2009 17:47:13.103578 PCI: 00:16.2: enabled 0
2010 17:47:13.106780 PCI: 00:16.3: enabled 0
2011 17:47:13.110259 PCI: 00:16.4: enabled 0
2012 17:47:13.113389 PCI: 00:16.5: enabled 0
2013 17:47:13.113463 PCI: 00:17.0: enabled 0
2014 17:47:13.117006 PCI: 00:19.0: enabled 0
2015 17:47:13.120260 PCI: 00:19.1: enabled 1
2016 17:47:13.123386 PCI: 00:19.2: enabled 0
2017 17:47:13.123459 PCI: 00:1a.0: enabled 0
2018 17:47:13.127118 PCI: 00:1c.0: enabled 0
2019 17:47:13.130234 PCI: 00:1c.1: enabled 0
2020 17:47:13.133634 PCI: 00:1c.2: enabled 0
2021 17:47:13.133707 PCI: 00:1c.3: enabled 0
2022 17:47:13.136866 PCI: 00:1c.4: enabled 0
2023 17:47:13.140101 PCI: 00:1c.5: enabled 0
2024 17:47:13.140173 PCI: 00:1c.6: enabled 0
2025 17:47:13.143281 PCI: 00:1c.7: enabled 0
2026 17:47:13.146982 PCI: 00:1d.0: enabled 0
2027 17:47:13.150288 PCI: 00:1d.1: enabled 0
2028 17:47:13.150359 PCI: 00:1d.2: enabled 0
2029 17:47:13.153561 PCI: 00:1d.3: enabled 0
2030 17:47:13.156600 PCI: 00:1e.0: enabled 1
2031 17:47:13.160064 PCI: 00:1e.1: enabled 0
2032 17:47:13.160137 PCI: 00:1e.2: enabled 0
2033 17:47:13.163670 PCI: 00:1e.3: enabled 1
2034 17:47:13.166817 PCI: 00:1f.0: enabled 1
2035 17:47:13.169974 PCI: 00:1f.1: enabled 0
2036 17:47:13.170049 PCI: 00:1f.2: enabled 1
2037 17:47:13.173436 PCI: 00:1f.3: enabled 1
2038 17:47:13.176647 PCI: 00:1f.4: enabled 0
2039 17:47:13.176733 PCI: 00:1f.5: enabled 1
2040 17:47:13.179908 PCI: 00:1f.6: enabled 0
2041 17:47:13.183583 PCI: 00:1f.7: enabled 0
2042 17:47:13.186869 GENERIC: 0.0: enabled 1
2043 17:47:13.186946 GENERIC: 0.0: enabled 1
2044 17:47:13.189903 GENERIC: 1.0: enabled 1
2045 17:47:13.193235 GENERIC: 0.0: enabled 1
2046 17:47:13.196879 GENERIC: 1.0: enabled 1
2047 17:47:13.196952 USB0 port 0: enabled 1
2048 17:47:13.200284 USB0 port 0: enabled 1
2049 17:47:13.203492 GENERIC: 0.0: enabled 1
2050 17:47:13.203562 I2C: 00:1a: enabled 1
2051 17:47:13.207289 I2C: 00:31: enabled 1
2052 17:47:13.209897 I2C: 00:32: enabled 1
2053 17:47:13.209969 I2C: 00:50: enabled 1
2054 17:47:13.213411 I2C: 00:10: enabled 1
2055 17:47:13.216532 I2C: 00:15: enabled 1
2056 17:47:13.216604 I2C: 00:2c: enabled 1
2057 17:47:13.220211 GENERIC: 0.0: enabled 1
2058 17:47:13.223354 SPI: 00: enabled 1
2059 17:47:13.226677 PNP: 0c09.0: enabled 1
2060 17:47:13.226749 GENERIC: 0.0: enabled 1
2061 17:47:13.230145 USB3 port 0: enabled 1
2062 17:47:13.233310 USB3 port 1: enabled 0
2063 17:47:13.233388 USB3 port 2: enabled 1
2064 17:47:13.236901 USB3 port 3: enabled 0
2065 17:47:13.239983 USB2 port 0: enabled 1
2066 17:47:13.240056 USB2 port 1: enabled 0
2067 17:47:13.243586 USB2 port 2: enabled 1
2068 17:47:13.246751 USB2 port 3: enabled 0
2069 17:47:13.250039 USB2 port 4: enabled 0
2070 17:47:13.250111 USB2 port 5: enabled 1
2071 17:47:13.253174 USB2 port 6: enabled 0
2072 17:47:13.256565 USB2 port 7: enabled 0
2073 17:47:13.256681 USB2 port 8: enabled 1
2074 17:47:13.260082 USB2 port 9: enabled 1
2075 17:47:13.263326 USB3 port 0: enabled 1
2076 17:47:13.266550 USB3 port 1: enabled 0
2077 17:47:13.266661 USB3 port 2: enabled 0
2078 17:47:13.269859 USB3 port 3: enabled 0
2079 17:47:13.273776 GENERIC: 0.0: enabled 1
2080 17:47:13.273854 GENERIC: 1.0: enabled 1
2081 17:47:13.276524 APIC: 00: enabled 1
2082 17:47:13.279943 APIC: 16: enabled 1
2083 17:47:13.280017 APIC: 10: enabled 1
2084 17:47:13.283212 APIC: 12: enabled 1
2085 17:47:13.286527 APIC: 14: enabled 1
2086 17:47:13.286600 APIC: 09: enabled 1
2087 17:47:13.289743 APIC: 01: enabled 1
2088 17:47:13.289817 APIC: 08: enabled 1
2089 17:47:13.292996 PCI: 01:00.0: enabled 1
2090 17:47:13.299922 BS: BS_DEV_INIT run times (exec / console): 8 / 1130 ms
2091 17:47:13.303140 FMAP: area RW_ELOG found @ f20000 (16384 bytes)
2092 17:47:13.306370 ELOG: NV offset 0xf20000 size 0x4000
2093 17:47:13.314472 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
2094 17:47:13.321436 ELOG: Event(17) added with size 13 at 2023-10-09 17:47:13 UTC
2095 17:47:13.327772 ELOG: Event(92) added with size 9 at 2023-10-09 17:47:13 UTC
2096 17:47:13.334858 ELOG: Event(93) added with size 9 at 2023-10-09 17:47:13 UTC
2097 17:47:13.341317 ELOG: Event(9E) added with size 10 at 2023-10-09 17:47:13 UTC
2098 17:47:13.348134 ELOG: Event(9F) added with size 14 at 2023-10-09 17:47:13 UTC
2099 17:47:13.354567 BS: BS_DEV_INIT exit times (exec / console): 4 / 45 ms
2100 17:47:13.361192 ELOG: Event(A1) added with size 10 at 2023-10-09 17:47:13 UTC
2101 17:47:13.367994 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
2102 17:47:13.374598 ELOG: Event(A0) added with size 9 at 2023-10-09 17:47:13 UTC
2103 17:47:13.377698 elog_add_boot_reason: Logged dev mode boot
2104 17:47:13.384587 BS: BS_POST_DEVICE entry times (exec / console): 1 / 24 ms
2105 17:47:13.387674 Finalize devices...
2106 17:47:13.387749 PCI: 00:16.0 final
2107 17:47:13.391360 PCI: 00:1f.2 final
2108 17:47:13.391434 GENERIC: 0.0 final
2109 17:47:13.398168 added type-c port0 info to cbmem: usb2:1 usb3:1 sbu:0 data:0
2110 17:47:13.401367 GENERIC: 1.0 final
2111 17:47:13.404586 added type-c port1 info to cbmem: usb2:3 usb3:3 sbu:0 data:0
2112 17:47:13.408060 Devices finalized
2113 17:47:13.414904 BS: BS_POST_DEVICE run times (exec / console): 0 / 24 ms
2114 17:47:13.417984 FMAP: area RW_NVRAM found @ f2b000 (24576 bytes)
2115 17:47:13.425020 BS: BS_POST_DEVICE exit times (exec / console): 0 / 5 ms
2116 17:47:13.427881 ME: HFSTS1 : 0x80030045
2117 17:47:13.434647 ME: HFSTS2 : 0x30280116
2118 17:47:13.437945 ME: HFSTS3 : 0x00000050
2119 17:47:13.441120 ME: HFSTS4 : 0x00004000
2120 17:47:13.447889 ME: HFSTS5 : 0x00000000
2121 17:47:13.451408 ME: HFSTS6 : 0x00400006
2122 17:47:13.454491 ME: Manufacturing Mode : YES
2123 17:47:13.457847 ME: SPI Protection Mode Enabled : YES
2124 17:47:13.464633 ME: FPFs Committed : NO
2125 17:47:13.467940 ME: Manufacturing Vars Locked : NO
2126 17:47:13.471053 ME: FW Partition Table : OK
2127 17:47:13.474574 ME: Bringup Loader Failure : NO
2128 17:47:13.478016 ME: Firmware Init Complete : NO
2129 17:47:13.481008 ME: Boot Options Present : NO
2130 17:47:13.484716 ME: Update In Progress : NO
2131 17:47:13.487874 ME: D0i3 Support : YES
2132 17:47:13.494332 ME: Low Power State Enabled : NO
2133 17:47:13.497837 ME: CPU Replaced : YES
2134 17:47:13.501027 ME: CPU Replacement Valid : YES
2135 17:47:13.504317 ME: Current Working State : 5
2136 17:47:13.507545 ME: Current Operation State : 1
2137 17:47:13.510906 ME: Current Operation Mode : 3
2138 17:47:13.514439 ME: Error Code : 0
2139 17:47:13.517443 ME: Enhanced Debug Mode : NO
2140 17:47:13.521079 ME: CPU Debug Disabled : YES
2141 17:47:13.527856 ME: TXT Support : NO
2142 17:47:13.530943 ME: WP for RO is enabled : YES
2143 17:47:13.537437 ME: RO write protection scope - Start=0x1000, End=0x15AFFF
2144 17:47:13.540692 BS: BS_OS_RESUME_CHECK exit times (exec / console): 0 / 111 ms
2145 17:47:13.547435 Ramoops buffer: 0x100000@0x7689a000.
2146 17:47:13.550681 BS: BS_WRITE_TABLES entry times (exec / console): 0 / 4 ms
2147 17:47:13.560998 CBFS: Found 'fallback/dsdt.aml' @0x788c0 size 0x4fd1 in mcache @0x76add1e8
2148 17:47:13.564202 CBFS: 'fallback/slic' not found.
2149 17:47:13.567280 ACPI: Writing ACPI tables at 7686e000.
2150 17:47:13.567354 ACPI: * FACS
2151 17:47:13.570589 ACPI: * DSDT
2152 17:47:13.577358 PCI space above 4GB MMIO is at 0x27fc00000, len = 0x7d80400000
2153 17:47:13.580535 ACPI: * FADT
2154 17:47:13.580609 SCI is IRQ9
2155 17:47:13.584083 ACPI: added table 1/32, length now 40
2156 17:47:13.587370 ACPI: * SSDT
2157 17:47:13.590521 Found 1 CPU(s) with 6/8 physical/logical core(s) each.
2158 17:47:13.598119 \_SB.PCI0.PEPD: Intel Power Engine Plug-in
2159 17:47:13.601302 \_SB.PCI0.PMC: Intel Alderlake at PCI: 00:1f.2
2160 17:47:13.604890 \_SB.DPTF: Intel DPTF at GENERIC: 0.0
2161 17:47:13.611111 CBFS: Found 'wifi_sar_0.hex' @0x3b1c40 size 0xe6 in mcache @0x76addf40
2162 17:47:13.618228 \_SB.PCI0.CNVW: WIFI Device GENERIC: 0.0
2163 17:47:13.624542 \_SB.PCI0.I2C0.NAU8: Nuvoton NAU8825 Codec address 01ah irq 0
2164 17:47:13.628085 \_SB.PCI0.I2C0.MAXR: Maxim MAX98373 Codec address 031h
2165 17:47:13.634824 \_SB.PCI0.I2C0.MAXL: Maxim MAX98373 Codec address 032h
2166 17:47:13.637887 \_SB.PCI0.I2C1.TPMI: I2C TPM at I2C: 00:50
2167 17:47:13.644846 \_SB.PCI0.I2C3.H010: ELAN Touchscreen at I2C: 00:10
2168 17:47:13.647970 \_SB.PCI0.I2C5.D015: ELAN Touchpad at I2C: 00:15
2169 17:47:13.654668 \_SB.PCI0.I2C5.H02C: Synaptics Touchpad at I2C: 00:2c
2170 17:47:13.657839 \_SB.PCI0.SPI1.CRFP: SPI Device at SPI: 00
2171 17:47:13.665340 PS2K: Physmap: [ EA E7 91 92 93 94 95 A0 AE B0 ]
2172 17:47:13.668854 PS2K: Passing 80 keymaps to kernel
2173 17:47:13.675314 \_SB.PCI0.TXHC.RHUB.SS01: USB3 Type-C Port C0 (MLB) at USB3 port 0
2174 17:47:13.681804 \_SB.PCI0.TXHC.RHUB.SS03: USB3 Type-C Port C1 (DB) at USB3 port 2
2175 17:47:13.688634 \_SB.PCI0.XHCI.RHUB.HS01: USB2 Type-C Port C0 (MLB) at USB2 port 0
2176 17:47:13.695412 \_SB.PCI0.XHCI.RHUB.HS03: USB2 Type-C Port C1 (DB) at USB2 port 2
2177 17:47:13.701838 \_SB.PCI0.XHCI.RHUB.HS06: USB2 Camera at USB2 port 5
2178 17:47:13.708497 \_SB.PCI0.XHCI.RHUB.HS09: USB2 Type-A Port A0 (DB) at USB2 port 8
2179 17:47:13.712000 \_SB.PCI0.XHCI.RHUB.HS10: USB2 Bluetooth at USB2 port 9
2180 17:47:13.718525 \_SB.PCI0.XHCI.RHUB.SS01: USB3 Type-A Port A0 (DB) at USB3 port 0
2181 17:47:13.725218 \_SB.PCI0.PMC.MUX.CON0: Intel PMC MUX CONN Driver at GENERIC: 0.0
2182 17:47:13.731830 \_SB.PCI0.PMC.MUX.CON1: Intel PMC MUX CONN Driver at GENERIC: 1.0
2183 17:47:13.735118 ACPI: added table 2/32, length now 44
2184 17:47:13.738521 ACPI: * MCFG
2185 17:47:13.741567 ACPI: added table 3/32, length now 48
2186 17:47:13.741641 ACPI: * TPM2
2187 17:47:13.744906 TPM2 log created at 0x7685e000
2188 17:47:13.751826 ACPI: added table 4/32, length now 52
2189 17:47:13.751900 ACPI: * LPIT
2190 17:47:13.754992 ACPI: added table 5/32, length now 56
2191 17:47:13.758158 ACPI: * MADT
2192 17:47:13.758238 SCI is IRQ9
2193 17:47:13.761481 ACPI: added table 6/32, length now 60
2194 17:47:13.764890 cmd_reg from pmc_make_ipc_cmd 1052838
2195 17:47:13.771762 CL PMC desc table: numb of regions is 0x2 at addr 0xfe0121bc
2196 17:47:13.778243 CL PMC desc table: region 0x0 has size 0x280 at offset 0x2200
2197 17:47:13.785017 CL PMC desc table: region 0x1 has size 0x80 at offset 0x3e00
2198 17:47:13.788167 PMC CrashLog size in discovery mode: 0xC00
2199 17:47:13.791466 cpu crashlog bar addr: 0x80640000
2200 17:47:13.794667 cpu discovery table offset: 0x6030
2201 17:47:13.801462 cpu_crashlog_discovery_table buffer count: 0x3
2202 17:47:13.808023 cpu_crashlog_discovery_table buffer: 0x0 size: 0x700 offset: 0x0
2203 17:47:13.814841 cpu_crashlog_discovery_table buffer: 0x1 size: 0x2b0 offset: 0x4000
2204 17:47:13.821377 cpu_crashlog_discovery_table buffer: 0x2 size: 0x370 offset: 0x5000
2205 17:47:13.824659 PMC crashLog size in discovery mode : 0xC00
2206 17:47:13.831471 Invalid data 0x0 at offset 0x2200 from addr 0xfe010000 of PMC SRAM.
2207 17:47:13.837867 discover mode PMC crashlog size adjusted to: 0x200
2208 17:47:13.844785 Invalid data 0x0 at offset 0x3e00 from addr 0xfe010000 of PMC SRAM.
2209 17:47:13.847926 discover mode PMC crashlog size adjusted to: 0x0
2210 17:47:13.851299 m_cpu_crashLog_size : 0x3480 bytes
2211 17:47:13.854527 CPU crashLog present.
2212 17:47:13.857819 CPU crash data size: 0x3480 bytes in 0x3 region(s).
2213 17:47:13.867867 Invalid data 0x0 at offset 0x0 from addr 0x80640000 of telemetry SRAM.
2214 17:47:13.867941 current = 76877550
2215 17:47:13.871300 ACPI: * DMAR
2216 17:47:13.874443 ACPI: added table 7/32, length now 64
2217 17:47:13.877809 ACPI: added table 8/32, length now 68
2218 17:47:13.877883 ACPI: * HPET
2219 17:47:13.884584 ACPI: added table 9/32, length now 72
2220 17:47:13.884657 ACPI: done.
2221 17:47:13.887947 ACPI tables: 38528 bytes.
2222 17:47:13.891495 smbios_write_tables: 76858000
2223 17:47:13.895192 EC returned error result code 3
2224 17:47:13.898355 Couldn't obtain OEM name from CBI
2225 17:47:13.901477 Create SMBIOS type 16
2226 17:47:13.904783 Create SMBIOS type 17
2227 17:47:13.904857 Create SMBIOS type 20
2228 17:47:13.907921 GENERIC: 0.0 (WIFI Device)
2229 17:47:13.911482 SMBIOS tables: 2156 bytes.
2230 17:47:13.914862 Writing table forward entry at 0x00000500
2231 17:47:13.921110 Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 6955
2232 17:47:13.924556 Writing coreboot table at 0x76892000
2233 17:47:13.931165 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
2234 17:47:13.934677 1. 0000000000001000-000000000009ffff: RAM
2235 17:47:13.941166 2. 00000000000a0000-00000000000fffff: RESERVED
2236 17:47:13.944431 3. 0000000000100000-0000000076857fff: RAM
2237 17:47:13.951189 4. 0000000076858000-0000000076a2ffff: CONFIGURATION TABLES
2238 17:47:13.954389 5. 0000000076a30000-0000000076ab8fff: RAMSTAGE
2239 17:47:13.961227 6. 0000000076ab9000-0000000076ffffff: CONFIGURATION TABLES
2240 17:47:13.967699 7. 0000000077000000-00000000803fffff: RESERVED
2241 17:47:13.970799 8. 00000000c0000000-00000000cfffffff: RESERVED
2242 17:47:13.974316 9. 00000000f8000000-00000000f9ffffff: RESERVED
2243 17:47:13.981135 10. 00000000fb000000-00000000fb000fff: RESERVED
2244 17:47:13.984488 11. 00000000fc800000-00000000fe7fffff: RESERVED
2245 17:47:13.991045 12. 00000000feb00000-00000000feb7ffff: RESERVED
2246 17:47:13.994128 13. 00000000fec00000-00000000fecfffff: RESERVED
2247 17:47:14.000827 14. 00000000fed40000-00000000fed6ffff: RESERVED
2248 17:47:14.003950 15. 00000000fed80000-00000000fed87fff: RESERVED
2249 17:47:14.010757 16. 00000000fed90000-00000000fed92fff: RESERVED
2250 17:47:14.014041 17. 00000000feda0000-00000000feda1fff: RESERVED
2251 17:47:14.017297 18. 00000000fedc0000-00000000feddffff: RESERVED
2252 17:47:14.023668 19. 0000000100000000-000000027fbfffff: RAM
2253 17:47:14.027269 Passing 4 GPIOs to payload:
2254 17:47:14.030775 NAME | PORT | POLARITY | VALUE
2255 17:47:14.037017 lid | undefined | high | high
2256 17:47:14.040754 power | undefined | high | low
2257 17:47:14.047330 oprom | undefined | high | low
2258 17:47:14.053824 EC in RW | 0x00000151 | high | high
2259 17:47:14.053905 Board ID: 3
2260 17:47:14.057130 FW config: 0x131
2261 17:47:14.060390 Wrote coreboot table at: 0x76892000, 0x6cc bytes, checksum d651
2262 17:47:14.063726 coreboot table: 1764 bytes.
2263 17:47:14.067031 IMD ROOT 0. 0x76fff000 0x00001000
2264 17:47:14.073817 IMD SMALL 1. 0x76ffe000 0x00001000
2265 17:47:14.077179 FSP MEMORY 2. 0x76afe000 0x00500000
2266 17:47:14.080424 CONSOLE 3. 0x76ade000 0x00020000
2267 17:47:14.083670 RO MCACHE 4. 0x76add000 0x00000fd8
2268 17:47:14.086942 FMAP 5. 0x76adc000 0x0000064a
2269 17:47:14.090495 TIME STAMP 6. 0x76adb000 0x00000910
2270 17:47:14.093421 VBOOT WORK 7. 0x76ac7000 0x00014000
2271 17:47:14.097158 MEM INFO 8. 0x76ac6000 0x000003b8
2272 17:47:14.103333 ROMSTG STCK 9. 0x76ac5000 0x00001000
2273 17:47:14.106820 AFTER CAR 10. 0x76ab9000 0x0000c000
2274 17:47:14.109992 RAMSTAGE 11. 0x76a2f000 0x0008a000
2275 17:47:14.113610 ACPI BERT 12. 0x76a1f000 0x00010000
2276 17:47:14.116787 CHROMEOS NVS13. 0x76a1e000 0x00000f00
2277 17:47:14.119898 REFCODE 14. 0x769af000 0x0006f000
2278 17:47:14.123420 SMM BACKUP 15. 0x7699f000 0x00010000
2279 17:47:14.126815 IGD OPREGION16. 0x7699a000 0x00004203
2280 17:47:14.133378 RAMOOPS 17. 0x7689a000 0x00100000
2281 17:47:14.136503 COREBOOT 18. 0x76892000 0x00008000
2282 17:47:14.140105 ACPI 19. 0x7686e000 0x00024000
2283 17:47:14.143246 TPM2 TCGLOG20. 0x7685e000 0x00010000
2284 17:47:14.146794 PMC CRASHLOG21. 0x7685d000 0x00000c00
2285 17:47:14.149861 CPU CRASHLOG22. 0x76859000 0x00003480
2286 17:47:14.153398 SMBIOS 23. 0x76858000 0x00001000
2287 17:47:14.156583 IMD small region:
2288 17:47:14.159845 IMD ROOT 0. 0x76ffec00 0x00000400
2289 17:47:14.163328 FSP RUNTIME 1. 0x76ffebe0 0x00000004
2290 17:47:14.166749 VPD 2. 0x76ffeb80 0x0000004c
2291 17:47:14.173368 POWER STATE 3. 0x76ffeb20 0x00000044
2292 17:47:14.176741 ROMSTAGE 4. 0x76ffeb00 0x00000004
2293 17:47:14.179604 ACPI GNVS 5. 0x76ffeaa0 0x00000048
2294 17:47:14.183104 TYPE_C INFO 6. 0x76ffea80 0x0000000c
2295 17:47:14.189753 BS: BS_WRITE_TABLES run times (exec / console): 8 / 624 ms
2296 17:47:14.193302 MTRR: Physical address space:
2297 17:47:14.199727 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
2298 17:47:14.206509 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
2299 17:47:14.212800 0x00000000000c0000 - 0x0000000077000000 size 0x76f40000 type 6
2300 17:47:14.216341 0x0000000077000000 - 0x0000000090000000 size 0x19000000 type 0
2301 17:47:14.222822 0x0000000090000000 - 0x00000000a0000000 size 0x10000000 type 1
2302 17:47:14.229716 0x00000000a0000000 - 0x0000000100000000 size 0x60000000 type 0
2303 17:47:14.236197 0x0000000100000000 - 0x000000027fc00000 size 0x17fc00000 type 6
2304 17:47:14.239569 MTRR: Fixed MSR 0x250 0x0606060606060606
2305 17:47:14.246299 MTRR: Fixed MSR 0x258 0x0606060606060606
2306 17:47:14.249489 MTRR: Fixed MSR 0x259 0x0000000000000000
2307 17:47:14.252795 MTRR: Fixed MSR 0x268 0x0606060606060606
2308 17:47:14.256013 MTRR: Fixed MSR 0x269 0x0606060606060606
2309 17:47:14.262665 MTRR: Fixed MSR 0x26a 0x0606060606060606
2310 17:47:14.265907 MTRR: Fixed MSR 0x26b 0x0606060606060606
2311 17:47:14.269329 MTRR: Fixed MSR 0x26c 0x0606060606060606
2312 17:47:14.272875 MTRR: Fixed MSR 0x26d 0x0606060606060606
2313 17:47:14.276038 MTRR: Fixed MSR 0x26e 0x0606060606060606
2314 17:47:14.282831 MTRR: Fixed MSR 0x26f 0x0606060606060606
2315 17:47:14.286115 call enable_fixed_mtrr()
2316 17:47:14.289202 CPU physical address size: 39 bits
2317 17:47:14.292827 MTRR: default type WB/UC MTRR counts: 6/6.
2318 17:47:14.296215 MTRR: UC selected as default type.
2319 17:47:14.302460 MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
2320 17:47:14.309209 MTRR: 1 base 0x0000000077000000 mask 0x0000007fff000000 type 0
2321 17:47:14.315825 MTRR: 2 base 0x0000000078000000 mask 0x0000007ff8000000 type 0
2322 17:47:14.322479 MTRR: 3 base 0x0000000090000000 mask 0x0000007ff0000000 type 1
2323 17:47:14.328904 MTRR: 4 base 0x0000000100000000 mask 0x0000007f00000000 type 6
2324 17:47:14.335861 MTRR: 5 base 0x0000000200000000 mask 0x0000007f80000000 type 6
2325 17:47:14.339010 MTRR: Fixed MSR 0x250 0x0606060606060606
2326 17:47:14.345804 MTRR: Fixed MSR 0x258 0x0606060606060606
2327 17:47:14.348897 MTRR: Fixed MSR 0x259 0x0000000000000000
2328 17:47:14.352548 MTRR: Fixed MSR 0x268 0x0606060606060606
2329 17:47:14.355705 MTRR: Fixed MSR 0x269 0x0606060606060606
2330 17:47:14.358942 MTRR: Fixed MSR 0x26a 0x0606060606060606
2331 17:47:14.365884 MTRR: Fixed MSR 0x26b 0x0606060606060606
2332 17:47:14.368979 MTRR: Fixed MSR 0x26c 0x0606060606060606
2333 17:47:14.372487 MTRR: Fixed MSR 0x26d 0x0606060606060606
2334 17:47:14.375575 MTRR: Fixed MSR 0x26e 0x0606060606060606
2335 17:47:14.382367 MTRR: Fixed MSR 0x26f 0x0606060606060606
2336 17:47:14.386019 MTRR: Fixed MSR 0x250 0x0606060606060606
2337 17:47:14.388689 MTRR: Fixed MSR 0x250 0x0606060606060606
2338 17:47:14.391912 MTRR: Fixed MSR 0x250 0x0606060606060606
2339 17:47:14.398821 MTRR: Fixed MSR 0x250 0x0606060606060606
2340 17:47:14.402050 MTRR: Fixed MSR 0x258 0x0606060606060606
2341 17:47:14.405188 MTRR: Fixed MSR 0x259 0x0000000000000000
2342 17:47:14.408528 MTRR: Fixed MSR 0x268 0x0606060606060606
2343 17:47:14.415371 MTRR: Fixed MSR 0x269 0x0606060606060606
2344 17:47:14.418823 MTRR: Fixed MSR 0x26a 0x0606060606060606
2345 17:47:14.421783 MTRR: Fixed MSR 0x26b 0x0606060606060606
2346 17:47:14.425494 MTRR: Fixed MSR 0x26c 0x0606060606060606
2347 17:47:14.428571 MTRR: Fixed MSR 0x26d 0x0606060606060606
2348 17:47:14.435364 MTRR: Fixed MSR 0x26e 0x0606060606060606
2349 17:47:14.438689 MTRR: Fixed MSR 0x26f 0x0606060606060606
2350 17:47:14.441787 call enable_fixed_mtrr()
2351 17:47:14.444943 MTRR: Fixed MSR 0x258 0x0606060606060606
2352 17:47:14.448306 MTRR: Fixed MSR 0x258 0x0606060606060606
2353 17:47:14.451927 MTRR: Fixed MSR 0x258 0x0606060606060606
2354 17:47:14.458284 MTRR: Fixed MSR 0x250 0x0606060606060606
2355 17:47:14.461836 MTRR: Fixed MSR 0x250 0x0606060606060606
2356 17:47:14.464824 MTRR: Fixed MSR 0x258 0x0606060606060606
2357 17:47:14.468555 MTRR: Fixed MSR 0x259 0x0000000000000000
2358 17:47:14.475114 MTRR: Fixed MSR 0x268 0x0606060606060606
2359 17:47:14.478153 MTRR: Fixed MSR 0x269 0x0606060606060606
2360 17:47:14.481871 MTRR: Fixed MSR 0x259 0x0000000000000000
2361 17:47:14.485081 MTRR: Fixed MSR 0x268 0x0606060606060606
2362 17:47:14.491401 MTRR: Fixed MSR 0x269 0x0606060606060606
2363 17:47:14.495115 MTRR: Fixed MSR 0x26a 0x0606060606060606
2364 17:47:14.498158 MTRR: Fixed MSR 0x26b 0x0606060606060606
2365 17:47:14.501342 MTRR: Fixed MSR 0x26c 0x0606060606060606
2366 17:47:14.504786 MTRR: Fixed MSR 0x26d 0x0606060606060606
2367 17:47:14.511614 MTRR: Fixed MSR 0x26e 0x0606060606060606
2368 17:47:14.514896 MTRR: Fixed MSR 0x26f 0x0606060606060606
2369 17:47:14.518124 MTRR: Fixed MSR 0x259 0x0000000000000000
2370 17:47:14.521293 call enable_fixed_mtrr()
2371 17:47:14.524757 MTRR: Fixed MSR 0x268 0x0606060606060606
2372 17:47:14.527952 MTRR: Fixed MSR 0x269 0x0606060606060606
2373 17:47:14.531545 CPU physical address size: 39 bits
2374 17:47:14.534806 call enable_fixed_mtrr()
2375 17:47:14.538059 MTRR: Fixed MSR 0x259 0x0000000000000000
2376 17:47:14.544760 CPU physical address size: 39 bits
2377 17:47:14.547978 CPU physical address size: 39 bits
2378 17:47:14.551444 MTRR: Fixed MSR 0x268 0x0606060606060606
2379 17:47:14.554644 MTRR: Fixed MSR 0x26a 0x0606060606060606
2380 17:47:14.557832 MTRR: Fixed MSR 0x26b 0x0606060606060606
2381 17:47:14.564418 MTRR: Fixed MSR 0x26c 0x0606060606060606
2382 17:47:14.567807 MTRR: Fixed MSR 0x26d 0x0606060606060606
2383 17:47:14.571003 MTRR: Fixed MSR 0x26e 0x0606060606060606
2384 17:47:14.574537 MTRR: Fixed MSR 0x26f 0x0606060606060606
2385 17:47:14.577752 MTRR: Fixed MSR 0x269 0x0606060606060606
2386 17:47:14.581213 call enable_fixed_mtrr()
2387 17:47:14.584410 MTRR: Fixed MSR 0x26a 0x0606060606060606
2388 17:47:14.591270 MTRR: Fixed MSR 0x26b 0x0606060606060606
2389 17:47:14.594487 MTRR: Fixed MSR 0x26c 0x0606060606060606
2390 17:47:14.597721 MTRR: Fixed MSR 0x26d 0x0606060606060606
2391 17:47:14.600925 MTRR: Fixed MSR 0x26e 0x0606060606060606
2392 17:47:14.607520 MTRR: Fixed MSR 0x26f 0x0606060606060606
2393 17:47:14.611185 CPU physical address size: 39 bits
2394 17:47:14.611259 call enable_fixed_mtrr()
2395 17:47:14.617779 MTRR: Fixed MSR 0x258 0x0606060606060606
2396 17:47:14.621025 CPU physical address size: 39 bits
2397 17:47:14.624306 MTRR: Fixed MSR 0x259 0x0000000000000000
2398 17:47:14.627692 MTRR: Fixed MSR 0x26a 0x0606060606060606
2399 17:47:14.630814 MTRR: Fixed MSR 0x268 0x0606060606060606
2400 17:47:14.637516 MTRR: Fixed MSR 0x269 0x0606060606060606
2401 17:47:14.640848 MTRR: Fixed MSR 0x26b 0x0606060606060606
2402 17:47:14.644043 MTRR: Fixed MSR 0x26c 0x0606060606060606
2403 17:47:14.647310 MTRR: Fixed MSR 0x26d 0x0606060606060606
2404 17:47:14.654047 MTRR: Fixed MSR 0x26e 0x0606060606060606
2405 17:47:14.657452 MTRR: Fixed MSR 0x26f 0x0606060606060606
2406 17:47:14.660744 MTRR: Fixed MSR 0x26a 0x0606060606060606
2407 17:47:14.664040 call enable_fixed_mtrr()
2408 17:47:14.667440 MTRR: Fixed MSR 0x26b 0x0606060606060606
2409 17:47:14.673958 MTRR: Fixed MSR 0x26c 0x0606060606060606
2410 17:47:14.677185 MTRR: Fixed MSR 0x26d 0x0606060606060606
2411 17:47:14.680604 MTRR: Fixed MSR 0x26e 0x0606060606060606
2412 17:47:14.684112 MTRR: Fixed MSR 0x26f 0x0606060606060606
2413 17:47:14.690634 CPU physical address size: 39 bits
2414 17:47:14.690709 call enable_fixed_mtrr()
2415 17:47:14.697198 CPU physical address size: 39 bits
2416 17:47:14.697272
2417 17:47:14.697325 MTRR check
2418 17:47:14.700469 Fixed MTRRs : Enabled
2419 17:47:14.703882 Variable MTRRs: Enabled
2420 17:47:14.703956
2421 17:47:14.710195 BS: BS_WRITE_TABLES exit times (exec / console): 253 / 150 ms
2422 17:47:14.713636 Checking cr50 for pending updates
2423 17:47:14.724569 Reading cr50 TPM mode
2424 17:47:14.739854 BS: BS_PAYLOAD_LOAD entry times (exec / console): 17 / 6 ms
2425 17:47:14.749820 CBFS: Found 'fallback/payload' @0x3b1d80 size 0x25902 in mcache @0x76addf68
2426 17:47:14.752936 Checking segment from ROM address 0xffc26dac
2427 17:47:14.756216 Checking segment from ROM address 0xffc26dc8
2428 17:47:14.763166 Loading segment from ROM address 0xffc26dac
2429 17:47:14.763249 code (compression=1)
2430 17:47:14.772984 New segment dstaddr 0x30000000 memsize 0x2668e60 srcaddr 0xffc26de4 filesize 0x258ca
2431 17:47:14.779625 Loading Segment: addr: 0x30000000 memsz: 0x0000000002668e60 filesz: 0x00000000000258ca
2432 17:47:14.782934 using LZMA
2433 17:47:14.870598 [ 0x30000000, 30051214, 0x32668e60) <- ffc26de4
2434 17:47:14.876938 Clearing Segment: addr: 0x0000000030051214 memsz: 0x0000000002617c4c
2435 17:47:14.885076 Loading segment from ROM address 0xffc26dc8
2436 17:47:14.888212 Entry Point 0x30000000
2437 17:47:14.888293 Loaded segments
2438 17:47:14.894961 BS: BS_PAYLOAD_LOAD run times (exec / console): 86 / 62 ms
2439 17:47:14.901707 BS: BS_PAYLOAD_LOAD exit times (exec / console): 1 / 0 ms
2440 17:47:14.905108 Finalizing chipset.
2441 17:47:14.905182 apm_control: Finalizing SMM.
2442 17:47:14.908444 APMC done.
2443 17:47:14.911739 HECI: CSE device 16.0 is hidden
2444 17:47:14.915352 HECI: CSE device 16.1 is disabled
2445 17:47:14.918420 HECI: CSE device 16.2 is disabled
2446 17:47:14.921774 HECI: CSE device 16.3 is disabled
2447 17:47:14.925253 HECI: CSE device 16.4 is disabled
2448 17:47:14.928229 HECI: CSE device 16.5 is disabled
2449 17:47:14.931723 HECI: CSE device 16.0 is hidden
2450 17:47:14.938429 CSE is disabled, cannot send End-of-Post (EOP) message
2451 17:47:14.941584 BS: BS_PAYLOAD_BOOT entry times (exec / console): 0 / 35 ms
2452 17:47:14.945145 mp_park_aps done after 0 msecs.
2453 17:47:14.951870 Jumping to boot code at 0x30000000(0x76892000)
2454 17:47:14.958420 CPU0: stack: 0x76a9a000 - 0x76a9b000, lowest used address 0x76a9a3dc, stack used: 3108 bytes
2455 17:47:14.964895
2456 17:47:14.964968
2457 17:47:14.965021
2458 17:47:14.968261 Starting depthcharge on Volmar...
2459 17:47:14.968336
2460 17:47:14.968658 end: 2.2.3 depthcharge-start (duration 00:00:11) [common]
2461 17:47:14.968740 start: 2.2.4 bootloader-commands (timeout 00:04:44) [common]
2462 17:47:14.968806 Setting prompt string to ['brya:']
2463 17:47:14.968867 bootloader-commands: Wait for prompt ['brya:'] (timeout 00:04:44)
2464 17:47:14.974857 WARNING: can't convert coreboot GPIOs, 'lid' won't be resampled at runtime!
2465 17:47:14.974934
2466 17:47:14.981743 WARNING: can't convert coreboot GPIOs, 'power' won't be resampled at runtime!
2467 17:47:14.981817
2468 17:47:14.987950 Looking for NVMe Controller 0x300653c0 @ 00:06:00
2469 17:47:14.988049
2470 17:47:14.991498 configure_storage: Failed to remap 1C:2
2471 17:47:14.991571
2472 17:47:14.994820 Wipe memory regions:
2473 17:47:14.994893
2474 17:47:14.998078 [0x00000000001000, 0x000000000a0000)
2475 17:47:14.998151
2476 17:47:15.001189 [0x00000000100000, 0x00000030000000)
2477 17:47:15.103664
2478 17:47:15.106836 [0x00000032668e60, 0x00000076858000)
2479 17:47:15.251312
2480 17:47:15.254564 [0x00000100000000, 0x0000027fc00000)
2481 17:47:16.064517
2482 17:47:16.067719 ec_init: CrosEC protocol v3 supported (256, 256)
2483 17:47:16.675873
2484 17:47:16.676000 R8152: Initializing
2485 17:47:16.676071
2486 17:47:16.679485 Version 9 (ocp_data = 6010)
2487 17:47:16.679562
2488 17:47:16.682613 R8152: Done initializing
2489 17:47:16.682687
2490 17:47:16.685741 Adding net device
2491 17:47:16.986966
2492 17:47:16.990012 [firmware-brya-14505.B-collabora] Feb 7 2023 16:06:26
2493 17:47:16.990100
2494 17:47:16.990154
2495 17:47:16.990209
2496 17:47:16.990481 Setting prompt string to ['brya:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2498 17:47:17.090845 brya: tftpboot 192.168.201.1 11712741/tftp-deploy-ljrl3t7v/kernel/bzImage 11712741/tftp-deploy-ljrl3t7v/kernel/cmdline 11712741/tftp-deploy-ljrl3t7v/ramdisk/ramdisk.cpio.gz
2499 17:47:17.091023 Setting prompt string to ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2500 17:47:17.091103 bootloader-commands: Wait for prompt ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:41)
2501 17:47:17.095666 tftpboot 192.168.201.1 11712741/tftp-deploy-ljrl3t7v/kernel/bzImaploy-ljrl3t7v/kernel/cmdline 11712741/tftp-deploy-ljrl3t7v/ramdisk/ramdisk.cpio.gz
2502 17:47:17.095745
2503 17:47:17.095805 Waiting for link
2504 17:47:17.298085
2505 17:47:17.298210 done.
2506 17:47:17.298281
2507 17:47:17.298329 MAC: 00:e0:4c:68:02:a7
2508 17:47:17.298377
2509 17:47:17.301549 Sending DHCP discover... done.
2510 17:47:17.301635
2511 17:47:17.304841 Waiting for reply... done.
2512 17:47:17.304963
2513 17:47:17.307923 Sending DHCP request... done.
2514 17:47:17.308038
2515 17:47:17.311226 Waiting for reply... done.
2516 17:47:17.314769
2517 17:47:17.314842 My ip is 192.168.201.15
2518 17:47:17.314895
2519 17:47:17.317903 The DHCP server ip is 192.168.201.1
2520 17:47:17.317978
2521 17:47:17.324307 TFTP server IP predefined by user: 192.168.201.1
2522 17:47:17.324382
2523 17:47:17.331116 Bootfile predefined by user: 11712741/tftp-deploy-ljrl3t7v/kernel/bzImage
2524 17:47:17.331193
2525 17:47:17.334281 Sending tftp read request... done.
2526 17:47:17.334353
2527 17:47:17.337718 Waiting for the transfer...
2528 17:47:17.337793
2529 17:47:17.564600 00000000 ################################################################
2530 17:47:17.564725
2531 17:47:17.788894 00080000 ################################################################
2532 17:47:17.789019
2533 17:47:18.013539 00100000 ################################################################
2534 17:47:18.013653
2535 17:47:18.238431 00180000 ################################################################
2536 17:47:18.238570
2537 17:47:18.464588 00200000 ################################################################
2538 17:47:18.464722
2539 17:47:18.689891 00280000 ################################################################
2540 17:47:18.690013
2541 17:47:18.915811 00300000 ################################################################
2542 17:47:18.915951
2543 17:47:19.141305 00380000 ################################################################
2544 17:47:19.141446
2545 17:47:19.366512 00400000 ################################################################
2546 17:47:19.366634
2547 17:47:19.592048 00480000 ################################################################
2548 17:47:19.592172
2549 17:47:19.820687 00500000 ################################################################
2550 17:47:19.820807
2551 17:47:20.048934 00580000 ################################################################
2552 17:47:20.049078
2553 17:47:20.276130 00600000 ################################################################
2554 17:47:20.276251
2555 17:47:20.503302 00680000 ################################################################
2556 17:47:20.503417
2557 17:47:20.731693 00700000 ################################################################
2558 17:47:20.731829
2559 17:47:20.956711 00780000 ################################################################
2560 17:47:20.956833
2561 17:47:21.000173 00800000 ############# done.
2562 17:47:21.000271
2563 17:47:21.003302 The bootfile was 8490896 bytes long.
2564 17:47:21.003377
2565 17:47:21.006786 Sending tftp read request... done.
2566 17:47:21.006894
2567 17:47:21.010297 Waiting for the transfer...
2568 17:47:21.010384
2569 17:47:21.238952 00000000 ################################################################
2570 17:47:21.239076
2571 17:47:21.464744 00080000 ################################################################
2572 17:47:21.464866
2573 17:47:21.690905 00100000 ################################################################
2574 17:47:21.691050
2575 17:47:21.917442 00180000 ################################################################
2576 17:47:21.917565
2577 17:47:22.145669 00200000 ################################################################
2578 17:47:22.145789
2579 17:47:22.368656 00280000 ################################################################
2580 17:47:22.368794
2581 17:47:22.595227 00300000 ################################################################
2582 17:47:22.595366
2583 17:47:22.821316 00380000 ################################################################
2584 17:47:22.821447
2585 17:47:23.047593 00400000 ################################################################
2586 17:47:23.047723
2587 17:47:23.276459 00480000 ################################################################
2588 17:47:23.276586
2589 17:47:23.504398 00500000 ################################################################
2590 17:47:23.504525
2591 17:47:23.731237 00580000 ################################################################
2592 17:47:23.731367
2593 17:47:23.959299 00600000 ################################################################
2594 17:47:23.959429
2595 17:47:24.187817 00680000 ################################################################
2596 17:47:24.187934
2597 17:47:24.415330 00700000 ################################################################
2598 17:47:24.415465
2599 17:47:24.642749 00780000 ################################################################
2600 17:47:24.642875
2601 17:47:24.826817 00800000 ##################################################### done.
2602 17:47:24.826937
2603 17:47:24.830187 Sending tftp read request... done.
2604 17:47:24.830268
2605 17:47:24.833549 Waiting for the transfer...
2606 17:47:24.833624
2607 17:47:24.833694 00000000 # done.
2608 17:47:24.833774
2609 17:47:24.843620 Command line loaded dynamically from TFTP file: 11712741/tftp-deploy-ljrl3t7v/kernel/cmdline
2610 17:47:24.843698
2611 17:47:24.860158 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
2612 17:47:24.864662
2613 17:47:24.867968 Shutting down all USB controllers.
2614 17:47:24.868049
2615 17:47:24.868102 Removing current net device
2616 17:47:24.868148
2617 17:47:24.871392 Finalizing coreboot
2618 17:47:24.871466
2619 17:47:24.877702 Exiting depthcharge with code 4 at timestamp: 19799757
2620 17:47:24.877776
2621 17:47:24.877828
2622 17:47:24.877890 Starting kernel ...
2623 17:47:24.877936
2624 17:47:24.878009
2625 17:47:24.878341 end: 2.2.4 bootloader-commands (duration 00:00:10) [common]
2626 17:47:24.878418 start: 2.2.5 auto-login-action (timeout 00:04:34) [common]
2627 17:47:24.878477 Setting prompt string to ['Linux version [0-9]']
2628 17:47:24.878554 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2629 17:47:24.878619 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
2631 17:51:58.878687 end: 2.2.5 auto-login-action (duration 00:04:34) [common]
2633 17:51:58.878877 depthcharge-retry failed: 1 of 1 attempts. 'auto-login-action timed out after 274 seconds'
2635 17:51:58.879006 end: 2.2 depthcharge-retry (duration 00:05:00) [common]
2638 17:51:58.879215 end: 2 depthcharge-action (duration 00:05:00) [common]
2640 17:51:58.879389 Cleaning after the job
2641 17:51:58.879471 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11712741/tftp-deploy-ljrl3t7v/ramdisk
2642 17:51:58.880333 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11712741/tftp-deploy-ljrl3t7v/kernel
2643 17:51:58.881448 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11712741/tftp-deploy-ljrl3t7v/modules
2644 17:51:58.881708 start: 5.1 power-off (timeout 00:00:30) [common]
2645 17:51:58.881842 Calling: 'pduclient' '--daemon=localhost' '--hostname=acer-cbv514-1h-34uz-brya-cbg-2' '--port=1' '--command=off'
2646 17:51:58.953150 >> Command sent successfully.
2647 17:51:58.956101 Returned 0 in 0 seconds
2648 17:51:59.056573 end: 5.1 power-off (duration 00:00:00) [common]
2650 17:51:59.056869 start: 5.2 read-feedback (timeout 00:10:00) [common]
2651 17:51:59.057062 Listened to connection for namespace 'common' for up to 1s
2653 17:51:59.057404 Listened to connection for namespace 'common' for up to 1s
2654 17:52:00.057642 Finalising connection for namespace 'common'
2655 17:52:00.058236 Disconnecting from shell: Finalise
2656 17:52:00.058545
2657 17:52:00.159357 end: 5.2 read-feedback (duration 00:00:01) [common]
2658 17:52:00.159847 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11712741
2659 17:52:00.172975 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11712741
2660 17:52:00.173098 JobError: Your job cannot terminate cleanly.