Boot log: asus-C436FA-Flip-hatch
- Warnings: 0
- Kernel Warnings: 0
- Kernel Errors: 0
- Errors: 2
- Boot result: FAIL
1 17:49:14.399602 lava-dispatcher, installed at version: 2023.08
2 17:49:14.399823 start: 0 validate
3 17:49:14.399959 Start time: 2023-10-09 17:49:14.399950+00:00 (UTC)
4 17:49:14.400086 Using caching service: 'http://localhost/cache/?uri=%s'
5 17:49:14.400220 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230623.0%2Fx86%2Frootfs.cpio.gz exists
6 17:49:14.668838 Using caching service: 'http://localhost/cache/?uri=%s'
7 17:49:14.669065 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-4.4.y-st-rc%2Fv4.4-st20-1778-gc774a35d86d2%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fkernel%2FbzImage exists
8 17:49:14.938122 Using caching service: 'http://localhost/cache/?uri=%s'
9 17:49:14.938341 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-4.4.y-st-rc%2Fv4.4-st20-1778-gc774a35d86d2%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
10 17:49:17.331272 validate duration: 2.93
12 17:49:17.331570 start: 1 tftp-deploy (timeout 00:10:00) [common]
13 17:49:17.331677 start: 1.1 download-retry (timeout 00:10:00) [common]
14 17:49:17.331780 start: 1.1.1 http-download (timeout 00:10:00) [common]
15 17:49:17.331911 Not decompressing ramdisk as can be used compressed.
16 17:49:17.331997 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230623.0/x86/rootfs.cpio.gz
17 17:49:17.332068 saving as /var/lib/lava/dispatcher/tmp/11712709/tftp-deploy-uer_z78u/ramdisk/rootfs.cpio.gz
18 17:49:17.332138 total size: 8418130 (8 MB)
19 17:49:17.843996 progress 0 % (0 MB)
20 17:49:17.846424 progress 5 % (0 MB)
21 17:49:17.848786 progress 10 % (0 MB)
22 17:49:17.851173 progress 15 % (1 MB)
23 17:49:17.853627 progress 20 % (1 MB)
24 17:49:17.856263 progress 25 % (2 MB)
25 17:49:17.858871 progress 30 % (2 MB)
26 17:49:17.861158 progress 35 % (2 MB)
27 17:49:17.863687 progress 40 % (3 MB)
28 17:49:17.866153 progress 45 % (3 MB)
29 17:49:17.868760 progress 50 % (4 MB)
30 17:49:17.871418 progress 55 % (4 MB)
31 17:49:17.873854 progress 60 % (4 MB)
32 17:49:17.876180 progress 65 % (5 MB)
33 17:49:17.878606 progress 70 % (5 MB)
34 17:49:17.881083 progress 75 % (6 MB)
35 17:49:17.883688 progress 80 % (6 MB)
36 17:49:17.886155 progress 85 % (6 MB)
37 17:49:17.888630 progress 90 % (7 MB)
38 17:49:17.891157 progress 95 % (7 MB)
39 17:49:17.893409 progress 100 % (8 MB)
40 17:49:17.893659 8 MB downloaded in 0.56 s (14.30 MB/s)
41 17:49:17.893817 end: 1.1.1 http-download (duration 00:00:01) [common]
43 17:49:17.894084 end: 1.1 download-retry (duration 00:00:01) [common]
44 17:49:17.894170 start: 1.2 download-retry (timeout 00:09:59) [common]
45 17:49:17.894253 start: 1.2.1 http-download (timeout 00:09:59) [common]
46 17:49:17.894397 downloading http://storage.kernelci.org/cip/linux-4.4.y-st-rc/v4.4-st20-1778-gc774a35d86d2/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/kernel/bzImage
47 17:49:17.894472 saving as /var/lib/lava/dispatcher/tmp/11712709/tftp-deploy-uer_z78u/kernel/bzImage
48 17:49:17.894567 total size: 8490896 (8 MB)
49 17:49:17.894628 No compression specified
50 17:49:17.895991 progress 0 % (0 MB)
51 17:49:17.898444 progress 5 % (0 MB)
52 17:49:17.901049 progress 10 % (0 MB)
53 17:49:17.903491 progress 15 % (1 MB)
54 17:49:17.905788 progress 20 % (1 MB)
55 17:49:17.908088 progress 25 % (2 MB)
56 17:49:17.910423 progress 30 % (2 MB)
57 17:49:17.912795 progress 35 % (2 MB)
58 17:49:17.915107 progress 40 % (3 MB)
59 17:49:17.917411 progress 45 % (3 MB)
60 17:49:17.919733 progress 50 % (4 MB)
61 17:49:17.922026 progress 55 % (4 MB)
62 17:49:17.924384 progress 60 % (4 MB)
63 17:49:17.926649 progress 65 % (5 MB)
64 17:49:17.928894 progress 70 % (5 MB)
65 17:49:17.931185 progress 75 % (6 MB)
66 17:49:17.933439 progress 80 % (6 MB)
67 17:49:17.935687 progress 85 % (6 MB)
68 17:49:17.937959 progress 90 % (7 MB)
69 17:49:17.940205 progress 95 % (7 MB)
70 17:49:17.942493 progress 100 % (8 MB)
71 17:49:17.942620 8 MB downloaded in 0.05 s (168.53 MB/s)
72 17:49:17.942767 end: 1.2.1 http-download (duration 00:00:00) [common]
74 17:49:17.942995 end: 1.2 download-retry (duration 00:00:00) [common]
75 17:49:17.943087 start: 1.3 download-retry (timeout 00:09:59) [common]
76 17:49:17.943172 start: 1.3.1 http-download (timeout 00:09:59) [common]
77 17:49:17.943308 downloading http://storage.kernelci.org/cip/linux-4.4.y-st-rc/v4.4-st20-1778-gc774a35d86d2/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/modules.tar.xz
78 17:49:17.943385 saving as /var/lib/lava/dispatcher/tmp/11712709/tftp-deploy-uer_z78u/modules/modules.tar
79 17:49:17.943445 total size: 250868 (0 MB)
80 17:49:17.943507 Using unxz to decompress xz
81 17:49:17.947772 progress 13 % (0 MB)
82 17:49:17.948199 progress 26 % (0 MB)
83 17:49:17.948454 progress 39 % (0 MB)
84 17:49:17.950057 progress 52 % (0 MB)
85 17:49:17.952176 progress 65 % (0 MB)
86 17:49:17.954396 progress 78 % (0 MB)
87 17:49:17.956532 progress 91 % (0 MB)
88 17:49:17.958543 progress 100 % (0 MB)
89 17:49:17.964837 0 MB downloaded in 0.02 s (11.19 MB/s)
90 17:49:17.965086 end: 1.3.1 http-download (duration 00:00:00) [common]
92 17:49:17.965351 end: 1.3 download-retry (duration 00:00:00) [common]
93 17:49:17.965445 start: 1.4 prepare-tftp-overlay (timeout 00:09:59) [common]
94 17:49:17.965542 start: 1.4.1 extract-nfsrootfs (timeout 00:09:59) [common]
95 17:49:17.965622 end: 1.4.1 extract-nfsrootfs (duration 00:00:00) [common]
96 17:49:17.965716 start: 1.4.2 lava-overlay (timeout 00:09:59) [common]
97 17:49:17.965948 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11712709/lava-overlay-aew9wdiv
98 17:49:17.966094 makedir: /var/lib/lava/dispatcher/tmp/11712709/lava-overlay-aew9wdiv/lava-11712709/bin
99 17:49:17.966205 makedir: /var/lib/lava/dispatcher/tmp/11712709/lava-overlay-aew9wdiv/lava-11712709/tests
100 17:49:17.966310 makedir: /var/lib/lava/dispatcher/tmp/11712709/lava-overlay-aew9wdiv/lava-11712709/results
101 17:49:17.966429 Creating /var/lib/lava/dispatcher/tmp/11712709/lava-overlay-aew9wdiv/lava-11712709/bin/lava-add-keys
102 17:49:17.966593 Creating /var/lib/lava/dispatcher/tmp/11712709/lava-overlay-aew9wdiv/lava-11712709/bin/lava-add-sources
103 17:49:17.966729 Creating /var/lib/lava/dispatcher/tmp/11712709/lava-overlay-aew9wdiv/lava-11712709/bin/lava-background-process-start
104 17:49:17.966865 Creating /var/lib/lava/dispatcher/tmp/11712709/lava-overlay-aew9wdiv/lava-11712709/bin/lava-background-process-stop
105 17:49:17.966995 Creating /var/lib/lava/dispatcher/tmp/11712709/lava-overlay-aew9wdiv/lava-11712709/bin/lava-common-functions
106 17:49:17.967125 Creating /var/lib/lava/dispatcher/tmp/11712709/lava-overlay-aew9wdiv/lava-11712709/bin/lava-echo-ipv4
107 17:49:17.967254 Creating /var/lib/lava/dispatcher/tmp/11712709/lava-overlay-aew9wdiv/lava-11712709/bin/lava-install-packages
108 17:49:17.967383 Creating /var/lib/lava/dispatcher/tmp/11712709/lava-overlay-aew9wdiv/lava-11712709/bin/lava-installed-packages
109 17:49:17.967512 Creating /var/lib/lava/dispatcher/tmp/11712709/lava-overlay-aew9wdiv/lava-11712709/bin/lava-os-build
110 17:49:17.967641 Creating /var/lib/lava/dispatcher/tmp/11712709/lava-overlay-aew9wdiv/lava-11712709/bin/lava-probe-channel
111 17:49:17.967768 Creating /var/lib/lava/dispatcher/tmp/11712709/lava-overlay-aew9wdiv/lava-11712709/bin/lava-probe-ip
112 17:49:17.967902 Creating /var/lib/lava/dispatcher/tmp/11712709/lava-overlay-aew9wdiv/lava-11712709/bin/lava-target-ip
113 17:49:17.968031 Creating /var/lib/lava/dispatcher/tmp/11712709/lava-overlay-aew9wdiv/lava-11712709/bin/lava-target-mac
114 17:49:17.968158 Creating /var/lib/lava/dispatcher/tmp/11712709/lava-overlay-aew9wdiv/lava-11712709/bin/lava-target-storage
115 17:49:17.968311 Creating /var/lib/lava/dispatcher/tmp/11712709/lava-overlay-aew9wdiv/lava-11712709/bin/lava-test-case
116 17:49:17.968441 Creating /var/lib/lava/dispatcher/tmp/11712709/lava-overlay-aew9wdiv/lava-11712709/bin/lava-test-event
117 17:49:17.968567 Creating /var/lib/lava/dispatcher/tmp/11712709/lava-overlay-aew9wdiv/lava-11712709/bin/lava-test-feedback
118 17:49:17.968694 Creating /var/lib/lava/dispatcher/tmp/11712709/lava-overlay-aew9wdiv/lava-11712709/bin/lava-test-raise
119 17:49:17.968826 Creating /var/lib/lava/dispatcher/tmp/11712709/lava-overlay-aew9wdiv/lava-11712709/bin/lava-test-reference
120 17:49:17.968956 Creating /var/lib/lava/dispatcher/tmp/11712709/lava-overlay-aew9wdiv/lava-11712709/bin/lava-test-runner
121 17:49:17.969085 Creating /var/lib/lava/dispatcher/tmp/11712709/lava-overlay-aew9wdiv/lava-11712709/bin/lava-test-set
122 17:49:17.969214 Creating /var/lib/lava/dispatcher/tmp/11712709/lava-overlay-aew9wdiv/lava-11712709/bin/lava-test-shell
123 17:49:17.969345 Updating /var/lib/lava/dispatcher/tmp/11712709/lava-overlay-aew9wdiv/lava-11712709/bin/lava-install-packages (oe)
124 17:49:17.969504 Updating /var/lib/lava/dispatcher/tmp/11712709/lava-overlay-aew9wdiv/lava-11712709/bin/lava-installed-packages (oe)
125 17:49:17.969630 Creating /var/lib/lava/dispatcher/tmp/11712709/lava-overlay-aew9wdiv/lava-11712709/environment
126 17:49:17.969739 LAVA metadata
127 17:49:17.969814 - LAVA_JOB_ID=11712709
128 17:49:17.969879 - LAVA_DISPATCHER_IP=192.168.201.1
129 17:49:17.969983 start: 1.4.2.1 lava-vland-overlay (timeout 00:09:59) [common]
130 17:49:17.970052 skipped lava-vland-overlay
131 17:49:17.970133 end: 1.4.2.1 lava-vland-overlay (duration 00:00:00) [common]
132 17:49:17.970214 start: 1.4.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
133 17:49:17.970278 skipped lava-multinode-overlay
134 17:49:17.970355 end: 1.4.2.2 lava-multinode-overlay (duration 00:00:00) [common]
135 17:49:17.970436 start: 1.4.2.3 test-definition (timeout 00:09:59) [common]
136 17:49:17.970513 Loading test definitions
137 17:49:17.970623 start: 1.4.2.3.1 inline-repo-action (timeout 00:09:59) [common]
138 17:49:17.970705 Using /lava-11712709 at stage 0
139 17:49:17.971044 uuid=11712709_1.4.2.3.1 testdef=None
140 17:49:17.971134 end: 1.4.2.3.1 inline-repo-action (duration 00:00:00) [common]
141 17:49:17.971225 start: 1.4.2.3.2 test-overlay (timeout 00:09:59) [common]
142 17:49:17.971766 end: 1.4.2.3.2 test-overlay (duration 00:00:00) [common]
144 17:49:17.971988 start: 1.4.2.3.3 test-install-overlay (timeout 00:09:59) [common]
145 17:49:17.972644 end: 1.4.2.3.3 test-install-overlay (duration 00:00:00) [common]
147 17:49:17.972874 start: 1.4.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
148 17:49:17.973501 runner path: /var/lib/lava/dispatcher/tmp/11712709/lava-overlay-aew9wdiv/lava-11712709/0/tests/0_dmesg test_uuid 11712709_1.4.2.3.1
149 17:49:17.973661 end: 1.4.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
151 17:49:17.973895 start: 1.4.2.3.5 inline-repo-action (timeout 00:09:59) [common]
152 17:49:17.973967 Using /lava-11712709 at stage 1
153 17:49:17.974277 uuid=11712709_1.4.2.3.5 testdef=None
154 17:49:17.974364 end: 1.4.2.3.5 inline-repo-action (duration 00:00:00) [common]
155 17:49:17.974447 start: 1.4.2.3.6 test-overlay (timeout 00:09:59) [common]
156 17:49:17.974935 end: 1.4.2.3.6 test-overlay (duration 00:00:00) [common]
158 17:49:17.975150 start: 1.4.2.3.7 test-install-overlay (timeout 00:09:59) [common]
159 17:49:17.975808 end: 1.4.2.3.7 test-install-overlay (duration 00:00:00) [common]
161 17:49:17.976037 start: 1.4.2.3.8 test-runscript-overlay (timeout 00:09:59) [common]
162 17:49:17.976686 runner path: /var/lib/lava/dispatcher/tmp/11712709/lava-overlay-aew9wdiv/lava-11712709/1/tests/1_bootrr test_uuid 11712709_1.4.2.3.5
163 17:49:17.976840 end: 1.4.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
165 17:49:17.977046 Creating lava-test-runner.conf files
166 17:49:17.977108 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11712709/lava-overlay-aew9wdiv/lava-11712709/0 for stage 0
167 17:49:17.977199 - 0_dmesg
168 17:49:17.977280 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11712709/lava-overlay-aew9wdiv/lava-11712709/1 for stage 1
169 17:49:17.977377 - 1_bootrr
170 17:49:17.977472 end: 1.4.2.3 test-definition (duration 00:00:00) [common]
171 17:49:17.977558 start: 1.4.2.4 compress-overlay (timeout 00:09:59) [common]
172 17:49:17.986249 end: 1.4.2.4 compress-overlay (duration 00:00:00) [common]
173 17:49:17.986360 start: 1.4.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
174 17:49:17.986447 end: 1.4.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
175 17:49:17.986539 end: 1.4.2 lava-overlay (duration 00:00:00) [common]
176 17:49:17.986624 start: 1.4.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
177 17:49:18.248728 end: 1.4.3 extract-overlay-ramdisk (duration 00:00:00) [common]
178 17:49:18.249158 start: 1.4.4 extract-modules (timeout 00:09:59) [common]
179 17:49:18.249315 extracting modules file /var/lib/lava/dispatcher/tmp/11712709/tftp-deploy-uer_z78u/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11712709/extract-overlay-ramdisk-ufisy0fg/ramdisk
180 17:49:18.269424 end: 1.4.4 extract-modules (duration 00:00:00) [common]
181 17:49:18.269588 start: 1.4.5 apply-overlay-tftp (timeout 00:09:59) [common]
182 17:49:18.269717 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11712709/compress-overlay-eslu1n87/overlay-1.4.2.4.tar.gz to ramdisk
183 17:49:18.269795 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11712709/compress-overlay-eslu1n87/overlay-1.4.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11712709/extract-overlay-ramdisk-ufisy0fg/ramdisk
184 17:49:18.283435 end: 1.4.5 apply-overlay-tftp (duration 00:00:00) [common]
185 17:49:18.283593 start: 1.4.6 configure-preseed-file (timeout 00:09:59) [common]
186 17:49:18.283726 end: 1.4.6 configure-preseed-file (duration 00:00:00) [common]
187 17:49:18.283855 start: 1.4.7 compress-ramdisk (timeout 00:09:59) [common]
188 17:49:18.283972 Building ramdisk /var/lib/lava/dispatcher/tmp/11712709/extract-overlay-ramdisk-ufisy0fg/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11712709/extract-overlay-ramdisk-ufisy0fg/ramdisk
189 17:49:18.418049 >> 49788 blocks
190 17:49:19.293978 rename /var/lib/lava/dispatcher/tmp/11712709/extract-overlay-ramdisk-ufisy0fg/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11712709/tftp-deploy-uer_z78u/ramdisk/ramdisk.cpio.gz
191 17:49:19.294443 end: 1.4.7 compress-ramdisk (duration 00:00:01) [common]
192 17:49:19.294638 start: 1.4.8 prepare-kernel (timeout 00:09:58) [common]
193 17:49:19.294738 start: 1.4.8.1 prepare-fit (timeout 00:09:58) [common]
194 17:49:19.294841 No mkimage arch provided, not using FIT.
195 17:49:19.294931 end: 1.4.8.1 prepare-fit (duration 00:00:00) [common]
196 17:49:19.295019 end: 1.4.8 prepare-kernel (duration 00:00:00) [common]
197 17:49:19.295123 end: 1.4 prepare-tftp-overlay (duration 00:00:01) [common]
198 17:49:19.295236 start: 1.5 lxc-create-udev-rule-action (timeout 00:09:58) [common]
199 17:49:19.295320 No LXC device requested
200 17:49:19.295403 end: 1.5 lxc-create-udev-rule-action (duration 00:00:00) [common]
201 17:49:19.295492 start: 1.6 deploy-device-env (timeout 00:09:58) [common]
202 17:49:19.295580 end: 1.6 deploy-device-env (duration 00:00:00) [common]
203 17:49:19.295651 Checking files for TFTP limit of 4294967296 bytes.
204 17:49:19.296071 end: 1 tftp-deploy (duration 00:00:02) [common]
205 17:49:19.296185 start: 2 depthcharge-action (timeout 00:05:00) [common]
206 17:49:19.296275 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
207 17:49:19.296392 substitutions:
208 17:49:19.296497 - {DTB}: None
209 17:49:19.296588 - {INITRD}: 11712709/tftp-deploy-uer_z78u/ramdisk/ramdisk.cpio.gz
210 17:49:19.296678 - {KERNEL}: 11712709/tftp-deploy-uer_z78u/kernel/bzImage
211 17:49:19.296764 - {LAVA_MAC}: None
212 17:49:19.296848 - {PRESEED_CONFIG}: None
213 17:49:19.296946 - {PRESEED_LOCAL}: None
214 17:49:19.297031 - {RAMDISK}: 11712709/tftp-deploy-uer_z78u/ramdisk/ramdisk.cpio.gz
215 17:49:19.297119 - {ROOT_PART}: None
216 17:49:19.297203 - {ROOT}: None
217 17:49:19.297290 - {SERVER_IP}: 192.168.201.1
218 17:49:19.297383 - {TEE}: None
219 17:49:19.297467 Parsed boot commands:
220 17:49:19.297548 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
221 17:49:19.297735 Parsed boot commands: tftpboot 192.168.201.1 11712709/tftp-deploy-uer_z78u/kernel/bzImage 11712709/tftp-deploy-uer_z78u/kernel/cmdline 11712709/tftp-deploy-uer_z78u/ramdisk/ramdisk.cpio.gz
222 17:49:19.297824 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
223 17:49:19.297909 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
224 17:49:19.298026 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
225 17:49:19.298139 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
226 17:49:19.298236 Not connected, no need to disconnect.
227 17:49:19.298343 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
228 17:49:19.298455 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
229 17:49:19.298597 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh asus-C436FA-Flip-hatch-cbg-0'
230 17:49:19.302470 Setting prompt string to ['lava-test: # ']
231 17:49:19.302880 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
232 17:49:19.303001 end: 2.2.1 reset-connection (duration 00:00:00) [common]
233 17:49:19.303140 start: 2.2.2 reset-device (timeout 00:05:00) [common]
234 17:49:19.303264 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
235 17:49:19.303698 Calling: 'pduclient' '--daemon=localhost' '--hostname=asus-C436FA-Flip-hatch-cbg-0' '--port=1' '--command=reboot'
236 17:49:24.445143 >> Command sent successfully.
237 17:49:24.447860 Returned 0 in 5 seconds
238 17:49:24.548211 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
240 17:49:24.548570 end: 2.2.2 reset-device (duration 00:00:05) [common]
241 17:49:24.548714 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
242 17:49:24.548839 Setting prompt string to 'Starting depthcharge on Helios...'
243 17:49:24.548938 Changing prompt to 'Starting depthcharge on Helios...'
244 17:49:24.549034 depthcharge-start: Wait for prompt Starting depthcharge on Helios... (timeout 00:05:00)
245 17:49:24.549406 [Enter `^Ec?' for help]
246 17:49:25.169706 test fbcdrrs-1p-offscren-pri-shr
247 17:49:25.169903
248 17:49:25.179564 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 bootblock starting (log level: 8)...
249 17:49:25.183261 CPU: Intel(R) Core(TM) i5-10210U CPU @ 1.60GHz
250 17:49:25.189622 CPU: ID 806ec, Whiskeylake V0, ucode: 000000c9
251 17:49:25.193046 CPU: AES supported, TXT NOT supported, VT supported
252 17:49:25.199586 MCH: device id 9b61 (rev 0c) is CometLake-U (4+2)
253 17:49:25.203495 PCH: device id 0284 (rev 00) is Cometlake-U Premium
254 17:49:25.210033 IGD: device id 9b41 (rev 02) is CometLake ULT GT2
255 17:49:25.213136 VBOOT: Loading verstage.
256 17:49:25.216470 FMAP: Found "FLASH" version 1.1 at 0xc04000.
257 17:49:25.223151 FMAP: base = 0xff000000 size = 0x1000000 #areas = 31
258 17:49:25.226299 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
259 17:49:25.229528 CBFS @ c08000 size 3f8000
260 17:49:25.236037 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
261 17:49:25.239822 CBFS: Locating 'fallback/verstage'
262 17:49:25.242934 CBFS: Found @ offset 10fb80 size 1072c
263 17:49:25.243008
264 17:49:25.246115
265 17:49:25.256099 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 verstage starting (log level: 8)...
266 17:49:25.270156 Probing TPM: . done!
267 17:49:25.273319 TPM ready after 0 ms
268 17:49:25.276595 Connected to device vid:did:rid of 1ae0:0028:00
269 17:49:25.286904 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.5.7/cr50_v1.9308_87_mp.514-29d5b602
270 17:49:25.290414 Initialized TPM device CR50 revision 0
271 17:49:25.338775 tlcl_send_startup: Startup return code is 0
272 17:49:25.338895 TPM: setup succeeded
273 17:49:25.351240 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0
274 17:49:25.354907 Chrome EC: UHEPI supported
275 17:49:25.358694 Phase 1
276 17:49:25.361693 FMAP: area GBB found @ c05000 (12288 bytes)
277 17:49:25.368445 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0
278 17:49:25.371831 Phase 2
279 17:49:25.371906 Phase 3
280 17:49:25.375245 FMAP: area GBB found @ c05000 (12288 bytes)
281 17:49:25.381763 VB2:vb2_report_dev_firmware() This is developer signed firmware
282 17:49:25.388582 FMAP: area VBLOCK_B found @ 768000 (65536 bytes)
283 17:49:25.391819 FMAP: area VBLOCK_B found @ 768000 (65536 bytes)
284 17:49:25.398030 VB2:vb2_verify_keyblock() Checking keyblock signature...
285 17:49:25.414075 FMAP: area VBLOCK_B found @ 768000 (65536 bytes)
286 17:49:25.417051 FMAP: area VBLOCK_B found @ 768000 (65536 bytes)
287 17:49:25.424020 VB2:vb2_verify_fw_preamble() Verifying preamble.
288 17:49:25.427959 Phase 4
289 17:49:25.431789 FMAP: area FW_MAIN_B found @ 778000 (3506112 bytes)
290 17:49:25.438125 VB2:vb2api_init_hash() HW crypto for hash_alg 2 not supported, using SW
291 17:49:25.617959 VB2:vb2_rsa_verify_digest() Digest check failed!
292 17:49:25.621059 VB2:vb2api_fail() Need recovery, reason: 0x1b / 0x7
293 17:49:25.624125 Saving nvdata
294 17:49:25.627272 Reboot requested (10020007)
295 17:49:25.630951 board_reset() called!
296 17:49:25.631066 full_reset() called!
297 17:49:30.136634
298 17:49:30.136827
299 17:49:30.146370 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 bootblock starting (log level: 8)...
300 17:49:30.149422 CPU: Intel(R) Core(TM) i5-10210U CPU @ 1.60GHz
301 17:49:30.156285 CPU: ID 806ec, Whiskeylake V0, ucode: 000000c9
302 17:49:30.159385 CPU: AES supported, TXT NOT supported, VT supported
303 17:49:30.166323 MCH: device id 9b61 (rev 0c) is CometLake-U (4+2)
304 17:49:30.169427 PCH: device id 0284 (rev 00) is Cometlake-U Premium
305 17:49:30.176308 IGD: device id 9b41 (rev 02) is CometLake ULT GT2
306 17:49:30.179267 VBOOT: Loading verstage.
307 17:49:30.182795 FMAP: Found "FLASH" version 1.1 at 0xc04000.
308 17:49:30.189460 FMAP: base = 0xff000000 size = 0x1000000 #areas = 31
309 17:49:30.192676 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
310 17:49:30.195817 CBFS @ c08000 size 3f8000
311 17:49:30.202810 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
312 17:49:30.205718 CBFS: Locating 'fallback/verstage'
313 17:49:30.209141 CBFS: Found @ offset 10fb80 size 1072c
314 17:49:30.213468
315 17:49:30.213573
316 17:49:30.222787 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 verstage starting (log level: 8)...
317 17:49:30.237156 Probing TPM: . done!
318 17:49:30.240770 TPM ready after 0 ms
319 17:49:30.243769 Connected to device vid:did:rid of 1ae0:0028:00
320 17:49:30.254013 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.5.7/cr50_v1.9308_87_mp.514-29d5b602
321 17:49:30.257714 Initialized TPM device CR50 revision 0
322 17:49:30.305706 tlcl_send_startup: Startup return code is 0
323 17:49:30.305845 TPM: setup succeeded
324 17:49:30.318735 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0
325 17:49:30.322063 Chrome EC: UHEPI supported
326 17:49:30.325723 Phase 1
327 17:49:30.328699 FMAP: area GBB found @ c05000 (12288 bytes)
328 17:49:30.335781 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
329 17:49:30.341833 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x0
330 17:49:30.345701 Recovery requested (1009000e)
331 17:49:30.351118 Saving nvdata
332 17:49:30.357605 tlcl_extend: response is 0
333 17:49:30.366242 tlcl_extend: response is 0
334 17:49:30.373303 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
335 17:49:30.376402 CBFS @ c08000 size 3f8000
336 17:49:30.382773 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
337 17:49:30.386020 CBFS: Locating 'fallback/romstage'
338 17:49:30.389767 CBFS: Found @ offset 80 size 145fc
339 17:49:30.392750 Accumulated console time in verstage 98 ms
340 17:49:30.392856
341 17:49:30.392949
342 17:49:30.406010 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 romstage starting (log level: 8)...
343 17:49:30.412890 VB2:vb2api_ec_sync() In recovery mode, skipping EC sync
344 17:49:30.416103 pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00
345 17:49:30.419256 gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000
346 17:49:30.425779 gpe0_sts[1]: 00200000 gpe0_en[1]: 00000000
347 17:49:30.429278 gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000
348 17:49:30.432895 gpe0_sts[3]: 00000000 gpe0_en[3]: 00010000
349 17:49:30.436010 TCO_STS: 0000 0000
350 17:49:30.439094 GEN_PMCON: e0015238 00000200
351 17:49:30.442285 GBLRST_CAUSE: 00000000 00000000
352 17:49:30.442417 prev_sleep_state 5
353 17:49:30.446109 Boot Count incremented to 71418
354 17:49:30.452792 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
355 17:49:30.456488 CBFS @ c08000 size 3f8000
356 17:49:30.462315 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
357 17:49:30.462429 CBFS: Locating 'fspm.bin'
358 17:49:30.468899 CBFS: Found @ offset 5ffc0 size 71000
359 17:49:30.472343 Chrome EC: UHEPI supported
360 17:49:30.479174 FMAP: area RECOVERY_MRC_CACHE found @ ad0000 (65536 bytes)
361 17:49:30.482913 Probing TPM: done!
362 17:49:30.489257 Connected to device vid:did:rid of 1ae0:0028:00
363 17:49:30.499386 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.5.7/cr50_v1.9308_87_mp.514-29d5b602
364 17:49:30.505612 Initialized TPM device CR50 revision 0
365 17:49:30.514191 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x100b return code 0
366 17:49:30.520669 MRC: Hash comparison successful. Using data from RECOVERY_MRC_CACHE
367 17:49:30.524358 MRC cache found, size 1948
368 17:49:30.527554 bootmode is set to: 2
369 17:49:30.530742 PRMRR disabled by config.
370 17:49:30.534286 SPD INDEX = 1
371 17:49:30.537449 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
372 17:49:30.540775 CBFS @ c08000 size 3f8000
373 17:49:30.547693 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
374 17:49:30.547781 CBFS: Locating 'spd.bin'
375 17:49:30.550862 CBFS: Found @ offset 5fb80 size 400
376 17:49:30.554079 SPD: module type is LPDDR3
377 17:49:30.557117 SPD: module part is
378 17:49:30.564150 SPD: banks 16, ranks 2, rows 15, columns 11, density 8192 Mb
379 17:49:30.567156 SPD: device width 4 bits, bus width 8 bits
380 17:49:30.570678 SPD: module size is 4096 MB (per channel)
381 17:49:30.573761 memory slot: 0 configuration done.
382 17:49:30.577383 memory slot: 2 configuration done.
383 17:49:30.628651 CBMEM:
384 17:49:30.631793 IMD: root @ 99fff000 254 entries.
385 17:49:30.635451 IMD: root @ 99ffec00 62 entries.
386 17:49:30.638375 External stage cache:
387 17:49:30.641679 IMD: root @ 9abff000 254 entries.
388 17:49:30.645361 IMD: root @ 9abfec00 62 entries.
389 17:49:30.648359 Chrome EC: clear events_b mask to 0x0000000020004000
390 17:49:30.669361 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x100b return code 0
391 17:49:30.677820 tlcl_write: response is 0
392 17:49:30.686676 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x100b return code 0
393 17:49:30.693549 MRC: TPM MRC hash updated successfully.
394 17:49:30.693658 2 DIMMs found
395 17:49:30.696789 SMM Memory Map
396 17:49:30.700382 SMRAM : 0x9a000000 0x1000000
397 17:49:30.703433 Subregion 0: 0x9a000000 0xa00000
398 17:49:30.706658 Subregion 1: 0x9aa00000 0x200000
399 17:49:30.710358 Subregion 2: 0x9ac00000 0x400000
400 17:49:30.713530 top_of_ram = 0x9a000000
401 17:49:30.716697 MTRR Range: Start=99000000 End=9a000000 (Size 1000000)
402 17:49:30.723587 MTRR Range: Start=9a000000 End=9b000000 (Size 1000000)
403 17:49:30.726815 MTRR Range: Start=ff000000 End=0 (Size 1000000)
404 17:49:30.733323 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
405 17:49:30.736898 CBFS @ c08000 size 3f8000
406 17:49:30.740038 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
407 17:49:30.743057 CBFS: Locating 'fallback/postcar'
408 17:49:30.749938 CBFS: Found @ offset 107000 size 4b44
409 17:49:30.753154 Decompressing stage fallback/postcar @ 0x99c0bfc0 (35640 bytes)
410 17:49:30.765696 Loading module at 99c0c000 with entry 99c0c000. filesize: 0x4818 memsize: 0x8af8
411 17:49:30.768798 Processing 180 relocs. Offset value of 0x97c0c000
412 17:49:30.777613 Accumulated console time in romstage 286 ms
413 17:49:30.777702
414 17:49:30.777777
415 17:49:30.787714 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 postcar starting (log level: 8)...
416 17:49:30.794092 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
417 17:49:30.797735 CBFS @ c08000 size 3f8000
418 17:49:30.800856 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
419 17:49:30.807076 CBFS: Locating 'fallback/ramstage'
420 17:49:30.810812 CBFS: Found @ offset 43380 size 1b9e8
421 17:49:30.817027 Decompressing stage fallback/ramstage @ 0x99baffc0 (372088 bytes)
422 17:49:30.849428 Loading module at 99bb0000 with entry 99bb0000. filesize: 0x40940 memsize: 0x5ad38
423 17:49:30.852572 Processing 3976 relocs. Offset value of 0x98db0000
424 17:49:30.859445 Accumulated console time in postcar 52 ms
425 17:49:30.859529
426 17:49:30.859595
427 17:49:30.869152 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 ramstage starting (log level: 8)...
428 17:49:30.875984 FMAP: area RO_VPD found @ c00000 (16384 bytes)
429 17:49:30.879091 WARNING: RO_VPD is uninitialized or empty.
430 17:49:30.882272 FMAP: area RW_VPD found @ af8000 (8192 bytes)
431 17:49:30.889165 FMAP: area RW_VPD found @ af8000 (8192 bytes)
432 17:49:30.889277 Normal boot.
433 17:49:30.895572 BS: BS_PRE_DEVICE times (ms): entry 0 run 0 exit 0
434 17:49:30.898965 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
435 17:49:30.902616 CBFS @ c08000 size 3f8000
436 17:49:30.909211 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
437 17:49:30.912234 CBFS: Locating 'cpu_microcode_blob.bin'
438 17:49:30.915834 CBFS: Found @ offset 14700 size 2ec00
439 17:49:30.918877 microcode: sig=0x806ec pf=0x4 revision=0xc9
440 17:49:30.922150 Skip microcode update
441 17:49:30.928597 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
442 17:49:30.928705 CBFS @ c08000 size 3f8000
443 17:49:30.935429 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
444 17:49:30.939133 CBFS: Locating 'fsps.bin'
445 17:49:30.942284 CBFS: Found @ offset d1fc0 size 35000
446 17:49:30.967505 Detected 4 core, 8 thread CPU.
447 17:49:30.970741 Setting up SMI for CPU
448 17:49:30.974516 IED base = 0x9ac00000
449 17:49:30.974680 IED size = 0x00400000
450 17:49:30.977497 Will perform SMM setup.
451 17:49:30.984334 CPU: Intel(R) Core(TM) i5-10210U CPU @ 1.60GHz.
452 17:49:30.990550 Loading module at 00030000 with entry 00030000. filesize: 0x170 memsize: 0x170
453 17:49:30.994330 Processing 16 relocs. Offset value of 0x00030000
454 17:49:30.997592 Attempting to start 7 APs
455 17:49:31.001230 Waiting for 10ms after sending INIT.
456 17:49:31.017163 Waiting for 1st SIPI to complete...done.
457 17:49:31.017262 AP: slot 3 apic_id 1.
458 17:49:31.023891 Waiting for 2nd SIPI to complete...done.
459 17:49:31.023972 AP: slot 6 apic_id 2.
460 17:49:31.027748 AP: slot 7 apic_id 3.
461 17:49:31.031007 AP: slot 2 apic_id 6.
462 17:49:31.031093 AP: slot 5 apic_id 7.
463 17:49:31.033973 AP: slot 1 apic_id 4.
464 17:49:31.037098 AP: slot 4 apic_id 5.
465 17:49:31.044078 Loading module at 00038000 with entry 00038000. filesize: 0x1a8 memsize: 0x1a8
466 17:49:31.050452 Processing 13 relocs. Offset value of 0x00038000
467 17:49:31.057306 SMM Module: stub loaded at 00038000. Will call 99bcb71d(00000000)
468 17:49:31.060424 Installing SMM handler to 0x9a000000
469 17:49:31.067240 Loading module at 9a010000 with entry 9a010a52. filesize: 0x7e88 memsize: 0xcf58
470 17:49:31.073719 Processing 658 relocs. Offset value of 0x9a010000
471 17:49:31.080569 Loading module at 9a008000 with entry 9a008000. filesize: 0x1a8 memsize: 0x1a8
472 17:49:31.083632 Processing 13 relocs. Offset value of 0x9a008000
473 17:49:31.090327 SMM Module: placing jmp sequence at 9a007c00 rel16 0x03fd
474 17:49:31.097312 SMM Module: placing jmp sequence at 9a007800 rel16 0x07fd
475 17:49:31.103536 SMM Module: placing jmp sequence at 9a007400 rel16 0x0bfd
476 17:49:31.107315 SMM Module: placing jmp sequence at 9a007000 rel16 0x0ffd
477 17:49:31.113913 SMM Module: placing jmp sequence at 9a006c00 rel16 0x13fd
478 17:49:31.120196 SMM Module: placing jmp sequence at 9a006800 rel16 0x17fd
479 17:49:31.123748 SMM Module: placing jmp sequence at 9a006400 rel16 0x1bfd
480 17:49:31.130558 SMM Module: stub loaded at 9a008000. Will call 9a010a52(00000000)
481 17:49:31.133484 Clearing SMI status registers
482 17:49:31.137250 SMI_STS: PM1
483 17:49:31.137355 PM1_STS: PWRBTN
484 17:49:31.140521 TCO_STS: SECOND_TO
485 17:49:31.143673 New SMBASE 0x9a000000
486 17:49:31.146796 In relocation handler: CPU 0
487 17:49:31.150715 New SMBASE=0x9a000000 IEDBASE=0x9ac00000
488 17:49:31.153923 Writing SMRR. base = 0x9a000006, mask=0xff000800
489 17:49:31.157000 Relocation complete.
490 17:49:31.160104 New SMBASE 0x99fff400
491 17:49:31.163782 In relocation handler: CPU 3
492 17:49:31.166776 New SMBASE=0x99fff400 IEDBASE=0x9ac00000
493 17:49:31.170278 Writing SMRR. base = 0x9a000006, mask=0xff000800
494 17:49:31.173798 Relocation complete.
495 17:49:31.176793 New SMBASE 0x99ffec00
496 17:49:31.176898 In relocation handler: CPU 5
497 17:49:31.183223 New SMBASE=0x99ffec00 IEDBASE=0x9ac00000
498 17:49:31.186951 Writing SMRR. base = 0x9a000006, mask=0xff000800
499 17:49:31.190022 Relocation complete.
500 17:49:31.193065 New SMBASE 0x99fff800
501 17:49:31.193171 In relocation handler: CPU 2
502 17:49:31.199922 New SMBASE=0x99fff800 IEDBASE=0x9ac00000
503 17:49:31.203025 Writing SMRR. base = 0x9a000006, mask=0xff000800
504 17:49:31.206876 Relocation complete.
505 17:49:31.206962 New SMBASE 0x99fff000
506 17:49:31.210023 In relocation handler: CPU 4
507 17:49:31.216964 New SMBASE=0x99fff000 IEDBASE=0x9ac00000
508 17:49:31.220209 Writing SMRR. base = 0x9a000006, mask=0xff000800
509 17:49:31.223253 Relocation complete.
510 17:49:31.223352 New SMBASE 0x99fffc00
511 17:49:31.226686 In relocation handler: CPU 1
512 17:49:31.230126 New SMBASE=0x99fffc00 IEDBASE=0x9ac00000
513 17:49:31.236748 Writing SMRR. base = 0x9a000006, mask=0xff000800
514 17:49:31.239729 Relocation complete.
515 17:49:31.239818 New SMBASE 0x99ffe800
516 17:49:31.243105 In relocation handler: CPU 6
517 17:49:31.246793 New SMBASE=0x99ffe800 IEDBASE=0x9ac00000
518 17:49:31.253118 Writing SMRR. base = 0x9a000006, mask=0xff000800
519 17:49:31.256202 Relocation complete.
520 17:49:31.256331 New SMBASE 0x99ffe400
521 17:49:31.259786 In relocation handler: CPU 7
522 17:49:31.262937 New SMBASE=0x99ffe400 IEDBASE=0x9ac00000
523 17:49:31.269600 Writing SMRR. base = 0x9a000006, mask=0xff000800
524 17:49:31.269683 Relocation complete.
525 17:49:31.272886 Initializing CPU #0
526 17:49:31.276529 CPU: vendor Intel device 806ec
527 17:49:31.279525 CPU: family 06, model 8e, stepping 0c
528 17:49:31.282998 Clearing out pending MCEs
529 17:49:31.286598 Setting up local APIC...
530 17:49:31.286687 apic_id: 0x00 done.
531 17:49:31.289771 Turbo is available but hidden
532 17:49:31.292918 Turbo is available and visible
533 17:49:31.295925 VMX status: enabled
534 17:49:31.299615 IA32_FEATURE_CONTROL status: locked
535 17:49:31.302687 Skip microcode update
536 17:49:31.302776 CPU #0 initialized
537 17:49:31.306235 Initializing CPU #7
538 17:49:31.309406 Initializing CPU #1
539 17:49:31.309486 Initializing CPU #4
540 17:49:31.312564 CPU: vendor Intel device 806ec
541 17:49:31.316441 CPU: family 06, model 8e, stepping 0c
542 17:49:31.319457 CPU: vendor Intel device 806ec
543 17:49:31.322786 CPU: family 06, model 8e, stepping 0c
544 17:49:31.325778 Clearing out pending MCEs
545 17:49:31.329604 Clearing out pending MCEs
546 17:49:31.332466 Setting up local APIC...
547 17:49:31.332658 Initializing CPU #2
548 17:49:31.335923 Initializing CPU #5
549 17:49:31.339587 CPU: vendor Intel device 806ec
550 17:49:31.342583 CPU: family 06, model 8e, stepping 0c
551 17:49:31.346079 CPU: vendor Intel device 806ec
552 17:49:31.349063 CPU: family 06, model 8e, stepping 0c
553 17:49:31.352816 Clearing out pending MCEs
554 17:49:31.355859 Clearing out pending MCEs
555 17:49:31.355963 Setting up local APIC...
556 17:49:31.359026 Initializing CPU #6
557 17:49:31.362867 CPU: vendor Intel device 806ec
558 17:49:31.366015 CPU: family 06, model 8e, stepping 0c
559 17:49:31.369088 CPU: vendor Intel device 806ec
560 17:49:31.372696 CPU: family 06, model 8e, stepping 0c
561 17:49:31.375954 Clearing out pending MCEs
562 17:49:31.379075 Clearing out pending MCEs
563 17:49:31.382212 Setting up local APIC...
564 17:49:31.382330 apic_id: 0x05 done.
565 17:49:31.386101 Setting up local APIC...
566 17:49:31.389195 apic_id: 0x06 done.
567 17:49:31.389299 Setting up local APIC...
568 17:49:31.392626 apic_id: 0x04 done.
569 17:49:31.395962 VMX status: enabled
570 17:49:31.396069 VMX status: enabled
571 17:49:31.399031 IA32_FEATURE_CONTROL status: locked
572 17:49:31.402334 IA32_FEATURE_CONTROL status: locked
573 17:49:31.405883 Skip microcode update
574 17:49:31.408931 Skip microcode update
575 17:49:31.409045 CPU #4 initialized
576 17:49:31.412518 CPU #1 initialized
577 17:49:31.415583 Setting up local APIC...
578 17:49:31.415688 apic_id: 0x07 done.
579 17:49:31.418958 VMX status: enabled
580 17:49:31.422436 VMX status: enabled
581 17:49:31.425402 IA32_FEATURE_CONTROL status: locked
582 17:49:31.428710 IA32_FEATURE_CONTROL status: locked
583 17:49:31.432378 Skip microcode update
584 17:49:31.432490 Skip microcode update
585 17:49:31.435368 CPU #2 initialized
586 17:49:31.435501 CPU #5 initialized
587 17:49:31.439009 apic_id: 0x02 done.
588 17:49:31.441965 apic_id: 0x03 done.
589 17:49:31.442071 VMX status: enabled
590 17:49:31.445462 VMX status: enabled
591 17:49:31.449112 IA32_FEATURE_CONTROL status: locked
592 17:49:31.452073 IA32_FEATURE_CONTROL status: locked
593 17:49:31.455698 Skip microcode update
594 17:49:31.455812 Skip microcode update
595 17:49:31.458670 CPU #6 initialized
596 17:49:31.461782 CPU #7 initialized
597 17:49:31.461901 Initializing CPU #3
598 17:49:31.465623 CPU: vendor Intel device 806ec
599 17:49:31.468797 CPU: family 06, model 8e, stepping 0c
600 17:49:31.471969 Clearing out pending MCEs
601 17:49:31.475524 Setting up local APIC...
602 17:49:31.478536 apic_id: 0x01 done.
603 17:49:31.478643 VMX status: enabled
604 17:49:31.481770 IA32_FEATURE_CONTROL status: locked
605 17:49:31.485652 Skip microcode update
606 17:49:31.488520 CPU #3 initialized
607 17:49:31.491703 bsp_do_flight_plan done after 466 msecs.
608 17:49:31.495367 CPU: frequency set to 4200 MHz
609 17:49:31.495474 Enabling SMIs.
610 17:49:31.498405 Locking SMM.
611 17:49:31.512030 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
612 17:49:31.515643 CBFS @ c08000 size 3f8000
613 17:49:31.522258 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
614 17:49:31.522365 CBFS: Locating 'vbt.bin'
615 17:49:31.525424 CBFS: Found @ offset 5f5c0 size 499
616 17:49:31.532306 Found a VBT of 4608 bytes after decompression
617 17:49:31.716779 Display FSP Version Info HOB
618 17:49:31.720241 Reference Code - CPU = 9.0.1e.30
619 17:49:31.723284 uCode Version = 0.0.0.ca
620 17:49:31.727135 TXT ACM version = ff.ff.ff.ffff
621 17:49:31.730128 Display FSP Version Info HOB
622 17:49:31.733911 Reference Code - ME = 9.0.1e.30
623 17:49:31.736597 MEBx version = 0.0.0.0
624 17:49:31.740133 ME Firmware Version = Consumer SKU
625 17:49:31.743435 Display FSP Version Info HOB
626 17:49:31.746312 Reference Code - CML PCH = 9.0.1e.30
627 17:49:31.749606 PCH-CRID Status = Disabled
628 17:49:31.753274 PCH-CRID Original Value = ff.ff.ff.ffff
629 17:49:31.756361 PCH-CRID New Value = ff.ff.ff.ffff
630 17:49:31.759951 OPROM - RST - RAID = ff.ff.ff.ffff
631 17:49:31.763050 ChipsetInit Base Version = ff.ff.ff.ffff
632 17:49:31.766736 ChipsetInit Oem Version = ff.ff.ff.ffff
633 17:49:31.769599 Display FSP Version Info HOB
634 17:49:31.775904 Reference Code - SA - System Agent = 9.0.1e.30
635 17:49:31.779420 Reference Code - MRC = 0.7.1.6c
636 17:49:31.779540 SA - PCIe Version = 9.0.1e.30
637 17:49:31.783143 SA-CRID Status = Disabled
638 17:49:31.786273 SA-CRID Original Value = 0.0.0.c
639 17:49:31.789379 SA-CRID New Value = 0.0.0.c
640 17:49:31.792498 OPROM - VBIOS = ff.ff.ff.ffff
641 17:49:31.795749 RTC Init
642 17:49:31.799488 Set power on after power failure.
643 17:49:31.799571 Disabling Deep S3
644 17:49:31.802614 Disabling Deep S3
645 17:49:31.802724 Disabling Deep S4
646 17:49:31.805651 Disabling Deep S4
647 17:49:31.809415 Disabling Deep S5
648 17:49:31.809499 Disabling Deep S5
649 17:49:31.815694 BS: BS_DEV_INIT_CHIPS times (ms): entry 37 run 195 exit 1
650 17:49:31.815780 Enumerating buses...
651 17:49:31.822619 Show all devs... Before device enumeration.
652 17:49:31.822703 Root Device: enabled 1
653 17:49:31.825890 CPU_CLUSTER: 0: enabled 1
654 17:49:31.828972 DOMAIN: 0000: enabled 1
655 17:49:31.832947 APIC: 00: enabled 1
656 17:49:31.833031 PCI: 00:00.0: enabled 1
657 17:49:31.836023 PCI: 00:02.0: enabled 1
658 17:49:31.839312 PCI: 00:04.0: enabled 0
659 17:49:31.842344 PCI: 00:05.0: enabled 0
660 17:49:31.842457 PCI: 00:12.0: enabled 1
661 17:49:31.845351 PCI: 00:12.5: enabled 0
662 17:49:31.848742 PCI: 00:12.6: enabled 0
663 17:49:31.852668 PCI: 00:14.0: enabled 1
664 17:49:31.853186 PCI: 00:14.1: enabled 0
665 17:49:31.855754 PCI: 00:14.3: enabled 1
666 17:49:31.859391 PCI: 00:14.5: enabled 0
667 17:49:31.859816 PCI: 00:15.0: enabled 1
668 17:49:31.862455 PCI: 00:15.1: enabled 1
669 17:49:31.865679 PCI: 00:15.2: enabled 0
670 17:49:31.869393 PCI: 00:15.3: enabled 0
671 17:49:31.869816 PCI: 00:16.0: enabled 1
672 17:49:31.872433 PCI: 00:16.1: enabled 0
673 17:49:31.875499 PCI: 00:16.2: enabled 0
674 17:49:31.879165 PCI: 00:16.3: enabled 0
675 17:49:31.879663 PCI: 00:16.4: enabled 0
676 17:49:31.882156 PCI: 00:16.5: enabled 0
677 17:49:31.885714 PCI: 00:17.0: enabled 1
678 17:49:31.889343 PCI: 00:19.0: enabled 1
679 17:49:31.889766 PCI: 00:19.1: enabled 0
680 17:49:31.892477 PCI: 00:19.2: enabled 0
681 17:49:31.895607 PCI: 00:1a.0: enabled 0
682 17:49:31.896031 PCI: 00:1c.0: enabled 0
683 17:49:31.898725 PCI: 00:1c.1: enabled 0
684 17:49:31.902615 PCI: 00:1c.2: enabled 0
685 17:49:31.905769 PCI: 00:1c.3: enabled 0
686 17:49:31.906326 PCI: 00:1c.4: enabled 0
687 17:49:31.908819 PCI: 00:1c.5: enabled 0
688 17:49:31.912027 PCI: 00:1c.6: enabled 0
689 17:49:31.915836 PCI: 00:1c.7: enabled 0
690 17:49:31.916255 PCI: 00:1d.0: enabled 1
691 17:49:31.918882 PCI: 00:1d.1: enabled 0
692 17:49:31.922031 PCI: 00:1d.2: enabled 0
693 17:49:31.925191 PCI: 00:1d.3: enabled 0
694 17:49:31.925614 PCI: 00:1d.4: enabled 0
695 17:49:31.928743 PCI: 00:1d.5: enabled 1
696 17:49:31.932079 PCI: 00:1e.0: enabled 1
697 17:49:31.932501 PCI: 00:1e.1: enabled 0
698 17:49:31.935561 PCI: 00:1e.2: enabled 1
699 17:49:31.938681 PCI: 00:1e.3: enabled 1
700 17:49:31.941850 PCI: 00:1f.0: enabled 1
701 17:49:31.942271 PCI: 00:1f.1: enabled 1
702 17:49:31.945741 PCI: 00:1f.2: enabled 1
703 17:49:31.949038 PCI: 00:1f.3: enabled 1
704 17:49:31.952210 PCI: 00:1f.4: enabled 1
705 17:49:31.952628 PCI: 00:1f.5: enabled 1
706 17:49:31.955063 PCI: 00:1f.6: enabled 0
707 17:49:31.958630 USB0 port 0: enabled 1
708 17:49:31.959092 I2C: 00:15: enabled 1
709 17:49:31.961590 I2C: 00:5d: enabled 1
710 17:49:31.964994 GENERIC: 0.0: enabled 1
711 17:49:31.968683 I2C: 00:1a: enabled 1
712 17:49:31.969122 I2C: 00:38: enabled 1
713 17:49:31.971852 I2C: 00:39: enabled 1
714 17:49:31.975693 I2C: 00:3a: enabled 1
715 17:49:31.976130 I2C: 00:3b: enabled 1
716 17:49:31.978872 PCI: 00:00.0: enabled 1
717 17:49:31.982054 SPI: 00: enabled 1
718 17:49:31.982475 SPI: 01: enabled 1
719 17:49:31.984981 PNP: 0c09.0: enabled 1
720 17:49:31.988124 USB2 port 0: enabled 1
721 17:49:31.988699 USB2 port 1: enabled 1
722 17:49:31.991714 USB2 port 2: enabled 0
723 17:49:31.995135 USB2 port 3: enabled 0
724 17:49:31.995637 USB2 port 5: enabled 0
725 17:49:31.998433 USB2 port 6: enabled 1
726 17:49:32.001434 USB2 port 9: enabled 1
727 17:49:32.005201 USB3 port 0: enabled 1
728 17:49:32.005760 USB3 port 1: enabled 1
729 17:49:32.008526 USB3 port 2: enabled 1
730 17:49:32.011384 USB3 port 3: enabled 1
731 17:49:32.011953 USB3 port 4: enabled 0
732 17:49:32.015231 APIC: 04: enabled 1
733 17:49:32.018422 APIC: 06: enabled 1
734 17:49:32.018921 APIC: 01: enabled 1
735 17:49:32.021568 APIC: 05: enabled 1
736 17:49:32.022035 APIC: 07: enabled 1
737 17:49:32.024955 APIC: 02: enabled 1
738 17:49:32.027976 APIC: 03: enabled 1
739 17:49:32.028417 Compare with tree...
740 17:49:32.031315 Root Device: enabled 1
741 17:49:32.035021 CPU_CLUSTER: 0: enabled 1
742 17:49:32.037993 APIC: 00: enabled 1
743 17:49:32.038620 APIC: 04: enabled 1
744 17:49:32.041138 APIC: 06: enabled 1
745 17:49:32.044538 APIC: 01: enabled 1
746 17:49:32.044962 APIC: 05: enabled 1
747 17:49:32.047678 APIC: 07: enabled 1
748 17:49:32.051432 APIC: 02: enabled 1
749 17:49:32.051905 APIC: 03: enabled 1
750 17:49:32.054645 DOMAIN: 0000: enabled 1
751 17:49:32.057727 PCI: 00:00.0: enabled 1
752 17:49:32.061274 PCI: 00:02.0: enabled 1
753 17:49:32.061837 PCI: 00:04.0: enabled 0
754 17:49:32.064320 PCI: 00:05.0: enabled 0
755 17:49:32.067448 PCI: 00:12.0: enabled 1
756 17:49:32.071228 PCI: 00:12.5: enabled 0
757 17:49:32.074062 PCI: 00:12.6: enabled 0
758 17:49:32.074446 PCI: 00:14.0: enabled 1
759 17:49:32.077563 USB0 port 0: enabled 1
760 17:49:32.081019 USB2 port 0: enabled 1
761 17:49:32.084049 USB2 port 1: enabled 1
762 17:49:32.087355 USB2 port 2: enabled 0
763 17:49:32.087887 USB2 port 3: enabled 0
764 17:49:32.090864 USB2 port 5: enabled 0
765 17:49:32.094393 USB2 port 6: enabled 1
766 17:49:32.097489 USB2 port 9: enabled 1
767 17:49:32.101119 USB3 port 0: enabled 1
768 17:49:32.104139 USB3 port 1: enabled 1
769 17:49:32.104563 USB3 port 2: enabled 1
770 17:49:32.107535 USB3 port 3: enabled 1
771 17:49:32.111111 USB3 port 4: enabled 0
772 17:49:32.114151 PCI: 00:14.1: enabled 0
773 17:49:32.117232 PCI: 00:14.3: enabled 1
774 17:49:32.117659 PCI: 00:14.5: enabled 0
775 17:49:32.120461 PCI: 00:15.0: enabled 1
776 17:49:32.124241 I2C: 00:15: enabled 1
777 17:49:32.127489 PCI: 00:15.1: enabled 1
778 17:49:32.130460 I2C: 00:5d: enabled 1
779 17:49:32.130933 GENERIC: 0.0: enabled 1
780 17:49:32.134311 PCI: 00:15.2: enabled 0
781 17:49:32.137340 PCI: 00:15.3: enabled 0
782 17:49:32.140499 PCI: 00:16.0: enabled 1
783 17:49:32.143875 PCI: 00:16.1: enabled 0
784 17:49:32.144300 PCI: 00:16.2: enabled 0
785 17:49:32.147348 PCI: 00:16.3: enabled 0
786 17:49:32.150342 PCI: 00:16.4: enabled 0
787 17:49:32.153912 PCI: 00:16.5: enabled 0
788 17:49:32.156934 PCI: 00:17.0: enabled 1
789 17:49:32.157236 PCI: 00:19.0: enabled 1
790 17:49:32.160163 I2C: 00:1a: enabled 1
791 17:49:32.163798 I2C: 00:38: enabled 1
792 17:49:32.166652 I2C: 00:39: enabled 1
793 17:49:32.166957 I2C: 00:3a: enabled 1
794 17:49:32.170310 I2C: 00:3b: enabled 1
795 17:49:32.173500 PCI: 00:19.1: enabled 0
796 17:49:32.176610 PCI: 00:19.2: enabled 0
797 17:49:32.179853 PCI: 00:1a.0: enabled 0
798 17:49:32.180153 PCI: 00:1c.0: enabled 0
799 17:49:32.183320 PCI: 00:1c.1: enabled 0
800 17:49:32.186628 PCI: 00:1c.2: enabled 0
801 17:49:32.190232 PCI: 00:1c.3: enabled 0
802 17:49:32.190666 PCI: 00:1c.4: enabled 0
803 17:49:32.193239 PCI: 00:1c.5: enabled 0
804 17:49:32.197052 PCI: 00:1c.6: enabled 0
805 17:49:32.199979 PCI: 00:1c.7: enabled 0
806 17:49:32.203100 PCI: 00:1d.0: enabled 1
807 17:49:32.203554 PCI: 00:1d.1: enabled 0
808 17:49:32.206915 PCI: 00:1d.2: enabled 0
809 17:49:32.209993 PCI: 00:1d.3: enabled 0
810 17:49:32.213001 PCI: 00:1d.4: enabled 0
811 17:49:32.216497 PCI: 00:1d.5: enabled 1
812 17:49:32.216835 PCI: 00:00.0: enabled 1
813 17:49:32.219927 PCI: 00:1e.0: enabled 1
814 17:49:32.223181 PCI: 00:1e.1: enabled 0
815 17:49:32.226253 PCI: 00:1e.2: enabled 1
816 17:49:32.230075 SPI: 00: enabled 1
817 17:49:32.230381 PCI: 00:1e.3: enabled 1
818 17:49:32.233189 SPI: 01: enabled 1
819 17:49:32.236284 PCI: 00:1f.0: enabled 1
820 17:49:32.239385 PNP: 0c09.0: enabled 1
821 17:49:32.239689 PCI: 00:1f.1: enabled 1
822 17:49:32.243379 PCI: 00:1f.2: enabled 1
823 17:49:32.246565 PCI: 00:1f.3: enabled 1
824 17:49:32.249723 PCI: 00:1f.4: enabled 1
825 17:49:32.252983 PCI: 00:1f.5: enabled 1
826 17:49:32.253287 PCI: 00:1f.6: enabled 0
827 17:49:32.256058 Root Device scanning...
828 17:49:32.259487 scan_static_bus for Root Device
829 17:49:32.262475 CPU_CLUSTER: 0 enabled
830 17:49:32.266328 DOMAIN: 0000 enabled
831 17:49:32.266663 DOMAIN: 0000 scanning...
832 17:49:32.269369 PCI: pci_scan_bus for bus 00
833 17:49:32.272343 PCI: 00:00.0 [8086/0000] ops
834 17:49:32.276277 PCI: 00:00.0 [8086/9b61] enabled
835 17:49:32.279612 PCI: 00:02.0 [8086/0000] bus ops
836 17:49:32.282747 PCI: 00:02.0 [8086/9b41] enabled
837 17:49:32.285651 PCI: 00:04.0 [8086/1903] disabled
838 17:49:32.289297 PCI: 00:08.0 [8086/1911] enabled
839 17:49:32.292908 PCI: 00:12.0 [8086/02f9] enabled
840 17:49:32.295707 PCI: 00:14.0 [8086/0000] bus ops
841 17:49:32.299212 PCI: 00:14.0 [8086/02ed] enabled
842 17:49:32.302786 PCI: 00:14.2 [8086/02ef] enabled
843 17:49:32.305656 PCI: 00:14.3 [8086/02f0] enabled
844 17:49:32.309377 PCI: 00:15.0 [8086/0000] bus ops
845 17:49:32.312706 PCI: 00:15.0 [8086/02e8] enabled
846 17:49:32.315972 PCI: 00:15.1 [8086/0000] bus ops
847 17:49:32.318988 PCI: 00:15.1 [8086/02e9] enabled
848 17:49:32.322688 PCI: 00:16.0 [8086/0000] ops
849 17:49:32.325777 PCI: 00:16.0 [8086/02e0] enabled
850 17:49:32.329064 PCI: 00:17.0 [8086/0000] ops
851 17:49:32.331994 PCI: 00:17.0 [8086/02d3] enabled
852 17:49:32.335617 PCI: 00:19.0 [8086/0000] bus ops
853 17:49:32.338805 PCI: 00:19.0 [8086/02c5] enabled
854 17:49:32.341962 PCI: 00:1d.0 [8086/0000] bus ops
855 17:49:32.345476 PCI: 00:1d.0 [8086/02b0] enabled
856 17:49:32.351957 PCI: Static device PCI: 00:1d.5 not found, disabling it.
857 17:49:32.355005 PCI: 00:1e.0 [8086/0000] ops
858 17:49:32.358848 PCI: 00:1e.0 [8086/02a8] enabled
859 17:49:32.361941 PCI: 00:1e.2 [8086/0000] bus ops
860 17:49:32.364993 PCI: 00:1e.2 [8086/02aa] enabled
861 17:49:32.368452 PCI: 00:1e.3 [8086/0000] bus ops
862 17:49:32.371637 PCI: 00:1e.3 [8086/02ab] enabled
863 17:49:32.375215 PCI: 00:1f.0 [8086/0000] bus ops
864 17:49:32.378201 PCI: 00:1f.0 [8086/0284] enabled
865 17:49:32.382152 PCI: Static device PCI: 00:1f.1 not found, disabling it.
866 17:49:32.388385 PCI: Static device PCI: 00:1f.2 not found, disabling it.
867 17:49:32.391543 PCI: 00:1f.3 [8086/0000] bus ops
868 17:49:32.395109 PCI: 00:1f.3 [8086/02c8] enabled
869 17:49:32.398170 PCI: 00:1f.4 [8086/0000] bus ops
870 17:49:32.402000 PCI: 00:1f.4 [8086/02a3] enabled
871 17:49:32.405029 PCI: 00:1f.5 [8086/0000] bus ops
872 17:49:32.408459 PCI: 00:1f.5 [8086/02a4] enabled
873 17:49:32.411630 PCI: Leftover static devices:
874 17:49:32.412098 PCI: 00:05.0
875 17:49:32.414724 PCI: 00:12.5
876 17:49:32.415168 PCI: 00:12.6
877 17:49:32.418353 PCI: 00:14.1
878 17:49:32.418832 PCI: 00:14.5
879 17:49:32.421460 PCI: 00:15.2
880 17:49:32.421899 PCI: 00:15.3
881 17:49:32.422315 PCI: 00:16.1
882 17:49:32.424673 PCI: 00:16.2
883 17:49:32.425103 PCI: 00:16.3
884 17:49:32.427814 PCI: 00:16.4
885 17:49:32.428341 PCI: 00:16.5
886 17:49:32.428778 PCI: 00:19.1
887 17:49:32.431498 PCI: 00:19.2
888 17:49:32.431913 PCI: 00:1a.0
889 17:49:32.434592 PCI: 00:1c.0
890 17:49:32.434893 PCI: 00:1c.1
891 17:49:32.438159 PCI: 00:1c.2
892 17:49:32.438612 PCI: 00:1c.3
893 17:49:32.438934 PCI: 00:1c.4
894 17:49:32.441192 PCI: 00:1c.5
895 17:49:32.441495 PCI: 00:1c.6
896 17:49:32.444825 PCI: 00:1c.7
897 17:49:32.445130 PCI: 00:1d.1
898 17:49:32.445373 PCI: 00:1d.2
899 17:49:32.448042 PCI: 00:1d.3
900 17:49:32.448346 PCI: 00:1d.4
901 17:49:32.451293 PCI: 00:1d.5
902 17:49:32.451597 PCI: 00:1e.1
903 17:49:32.451839 PCI: 00:1f.1
904 17:49:32.454478 PCI: 00:1f.2
905 17:49:32.454812 PCI: 00:1f.6
906 17:49:32.457635 PCI: Check your devicetree.cb.
907 17:49:32.461411 PCI: 00:02.0 scanning...
908 17:49:32.464717 scan_generic_bus for PCI: 00:02.0
909 17:49:32.467831 scan_generic_bus for PCI: 00:02.0 done
910 17:49:32.474738 scan_bus: scanning of bus PCI: 00:02.0 took 10174 usecs
911 17:49:32.477970 PCI: 00:14.0 scanning...
912 17:49:32.480743 scan_static_bus for PCI: 00:14.0
913 17:49:32.481046 USB0 port 0 enabled
914 17:49:32.484489 USB0 port 0 scanning...
915 17:49:32.487527 scan_static_bus for USB0 port 0
916 17:49:32.490742 USB2 port 0 enabled
917 17:49:32.491089 USB2 port 1 enabled
918 17:49:32.494496 USB2 port 2 disabled
919 17:49:32.497592 USB2 port 3 disabled
920 17:49:32.497991 USB2 port 5 disabled
921 17:49:32.500720 USB2 port 6 enabled
922 17:49:32.503915 USB2 port 9 enabled
923 17:49:32.504309 USB3 port 0 enabled
924 17:49:32.507639 USB3 port 1 enabled
925 17:49:32.508082 USB3 port 2 enabled
926 17:49:32.510828 USB3 port 3 enabled
927 17:49:32.513825 USB3 port 4 disabled
928 17:49:32.517351 USB2 port 0 scanning...
929 17:49:32.520163 scan_static_bus for USB2 port 0
930 17:49:32.524043 scan_static_bus for USB2 port 0 done
931 17:49:32.526890 scan_bus: scanning of bus USB2 port 0 took 9692 usecs
932 17:49:32.530631 USB2 port 1 scanning...
933 17:49:32.533718 scan_static_bus for USB2 port 1
934 17:49:32.537080 scan_static_bus for USB2 port 1 done
935 17:49:32.543564 scan_bus: scanning of bus USB2 port 1 took 9702 usecs
936 17:49:32.547207 USB2 port 6 scanning...
937 17:49:32.550145 scan_static_bus for USB2 port 6
938 17:49:32.553854 scan_static_bus for USB2 port 6 done
939 17:49:32.556993 scan_bus: scanning of bus USB2 port 6 took 9704 usecs
940 17:49:32.560204 USB2 port 9 scanning...
941 17:49:32.563381 scan_static_bus for USB2 port 9
942 17:49:32.567052 scan_static_bus for USB2 port 9 done
943 17:49:32.573123 scan_bus: scanning of bus USB2 port 9 took 9705 usecs
944 17:49:32.576867 USB3 port 0 scanning...
945 17:49:32.580142 scan_static_bus for USB3 port 0
946 17:49:32.583045 scan_static_bus for USB3 port 0 done
947 17:49:32.586701 scan_bus: scanning of bus USB3 port 0 took 9704 usecs
948 17:49:32.589956 USB3 port 1 scanning...
949 17:49:32.593462 scan_static_bus for USB3 port 1
950 17:49:32.596509 scan_static_bus for USB3 port 1 done
951 17:49:32.603385 scan_bus: scanning of bus USB3 port 1 took 9695 usecs
952 17:49:32.606355 USB3 port 2 scanning...
953 17:49:32.610166 scan_static_bus for USB3 port 2
954 17:49:32.612780 scan_static_bus for USB3 port 2 done
955 17:49:32.619575 scan_bus: scanning of bus USB3 port 2 took 9695 usecs
956 17:49:32.619880 USB3 port 3 scanning...
957 17:49:32.622794 scan_static_bus for USB3 port 3
958 17:49:32.629534 scan_static_bus for USB3 port 3 done
959 17:49:32.633006 scan_bus: scanning of bus USB3 port 3 took 9702 usecs
960 17:49:32.635858 scan_static_bus for USB0 port 0 done
961 17:49:32.642636 scan_bus: scanning of bus USB0 port 0 took 155310 usecs
962 17:49:32.646175 scan_static_bus for PCI: 00:14.0 done
963 17:49:32.652501 scan_bus: scanning of bus PCI: 00:14.0 took 172919 usecs
964 17:49:32.656200 PCI: 00:15.0 scanning...
965 17:49:32.659166 scan_generic_bus for PCI: 00:15.0
966 17:49:32.662427 bus: PCI: 00:15.0[0]->I2C: 01:15 enabled
967 17:49:32.665702 scan_generic_bus for PCI: 00:15.0 done
968 17:49:32.672626 scan_bus: scanning of bus PCI: 00:15.0 took 14287 usecs
969 17:49:32.675846 PCI: 00:15.1 scanning...
970 17:49:32.679158 scan_generic_bus for PCI: 00:15.1
971 17:49:32.682175 bus: PCI: 00:15.1[0]->I2C: 02:5d enabled
972 17:49:32.685987 bus: PCI: 00:15.1[0]->GENERIC: 0.0 enabled
973 17:49:32.688975 scan_generic_bus for PCI: 00:15.1 done
974 17:49:32.695846 scan_bus: scanning of bus PCI: 00:15.1 took 18604 usecs
975 17:49:32.698873 PCI: 00:19.0 scanning...
976 17:49:32.702346 scan_generic_bus for PCI: 00:19.0
977 17:49:32.705672 bus: PCI: 00:19.0[0]->I2C: 03:1a enabled
978 17:49:32.708645 bus: PCI: 00:19.0[0]->I2C: 03:38 enabled
979 17:49:32.715686 bus: PCI: 00:19.0[0]->I2C: 03:39 enabled
980 17:49:32.718934 bus: PCI: 00:19.0[0]->I2C: 03:3a enabled
981 17:49:32.722082 bus: PCI: 00:19.0[0]->I2C: 03:3b enabled
982 17:49:32.725268 scan_generic_bus for PCI: 00:19.0 done
983 17:49:32.732127 scan_bus: scanning of bus PCI: 00:19.0 took 30723 usecs
984 17:49:32.735266 PCI: 00:1d.0 scanning...
985 17:49:32.738931 do_pci_scan_bridge for PCI: 00:1d.0
986 17:49:32.742079 PCI: pci_scan_bus for bus 01
987 17:49:32.745190 PCI: 01:00.0 [1c5c/1327] enabled
988 17:49:32.748869 Enabling Common Clock Configuration
989 17:49:32.752091 L1 Sub-State supported from root port 29
990 17:49:32.755408 L1 Sub-State Support = 0xf
991 17:49:32.758974 CommonModeRestoreTime = 0x28
992 17:49:32.761658 Power On Value = 0x16, Power On Scale = 0x0
993 17:49:32.765059 ASPM: Enabled L1
994 17:49:32.768535 scan_bus: scanning of bus PCI: 00:1d.0 took 32775 usecs
995 17:49:32.771813 PCI: 00:1e.2 scanning...
996 17:49:32.775672 scan_generic_bus for PCI: 00:1e.2
997 17:49:32.778748 bus: PCI: 00:1e.2[0]->SPI: 00 enabled
998 17:49:32.784978 scan_generic_bus for PCI: 00:1e.2 done
999 17:49:32.788179 scan_bus: scanning of bus PCI: 00:1e.2 took 14010 usecs
1000 17:49:32.792022 PCI: 00:1e.3 scanning...
1001 17:49:32.795276 scan_generic_bus for PCI: 00:1e.3
1002 17:49:32.798352 bus: PCI: 00:1e.3[0]->SPI: 01 enabled
1003 17:49:32.801646 scan_generic_bus for PCI: 00:1e.3 done
1004 17:49:32.808296 scan_bus: scanning of bus PCI: 00:1e.3 took 14002 usecs
1005 17:49:32.811794 PCI: 00:1f.0 scanning...
1006 17:49:32.814764 scan_static_bus for PCI: 00:1f.0
1007 17:49:32.818286 PNP: 0c09.0 enabled
1008 17:49:32.821282 scan_static_bus for PCI: 00:1f.0 done
1009 17:49:32.825035 scan_bus: scanning of bus PCI: 00:1f.0 took 12045 usecs
1010 17:49:32.828141 PCI: 00:1f.3 scanning...
1011 17:49:32.835337 scan_bus: scanning of bus PCI: 00:1f.3 took 2858 usecs
1012 17:49:32.838346 PCI: 00:1f.4 scanning...
1013 17:49:32.841283 scan_generic_bus for PCI: 00:1f.4
1014 17:49:32.844929 scan_generic_bus for PCI: 00:1f.4 done
1015 17:49:32.851221 scan_bus: scanning of bus PCI: 00:1f.4 took 10182 usecs
1016 17:49:32.851647 PCI: 00:1f.5 scanning...
1017 17:49:32.858222 scan_generic_bus for PCI: 00:1f.5
1018 17:49:32.861592 scan_generic_bus for PCI: 00:1f.5 done
1019 17:49:32.864840 scan_bus: scanning of bus PCI: 00:1f.5 took 10175 usecs
1020 17:49:32.871390 scan_bus: scanning of bus DOMAIN: 0000 took 604845 usecs
1021 17:49:32.874675 scan_static_bus for Root Device done
1022 17:49:32.881259 scan_bus: scanning of bus Root Device took 624702 usecs
1023 17:49:32.881748 done
1024 17:49:32.884417 Chrome EC: UHEPI supported
1025 17:49:32.891398 FMAP: area RECOVERY_MRC_CACHE found @ ad0000 (65536 bytes)
1026 17:49:32.898351 MRC: Checking cached data update for 'RECOVERY_MRC_CACHE'.
1027 17:49:32.901437 SF: Detected 00 0000 with sector size 0x1000, total 0x1000000
1028 17:49:32.909507 FMAP: area UNIFIED_MRC_CACHE found @ ad0000 (131072 bytes)
1029 17:49:32.912586 SPI flash protection: WPSW=0 SRP0=0
1030 17:49:32.919598 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
1031 17:49:32.922804 BS: BS_DEV_ENUMERATE times (ms): entry 0 run 9 exit 2
1032 17:49:32.925860 found VGA at PCI: 00:02.0
1033 17:49:32.929383 Setting up VGA for PCI: 00:02.0
1034 17:49:32.935737 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
1035 17:49:32.939391 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
1036 17:49:32.942513 Allocating resources...
1037 17:49:32.945672 Reading resources...
1038 17:49:32.949082 Root Device read_resources bus 0 link: 0
1039 17:49:32.952141 CPU_CLUSTER: 0 read_resources bus 0 link: 0
1040 17:49:32.959092 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
1041 17:49:32.962073 DOMAIN: 0000 read_resources bus 0 link: 0
1042 17:49:32.969679 PCI: 00:14.0 read_resources bus 0 link: 0
1043 17:49:32.972831 USB0 port 0 read_resources bus 0 link: 0
1044 17:49:32.980804 USB0 port 0 read_resources bus 0 link: 0 done
1045 17:49:32.984276 PCI: 00:14.0 read_resources bus 0 link: 0 done
1046 17:49:32.991735 PCI: 00:15.0 read_resources bus 1 link: 0
1047 17:49:32.994931 PCI: 00:15.0 read_resources bus 1 link: 0 done
1048 17:49:33.001532 PCI: 00:15.1 read_resources bus 2 link: 0
1049 17:49:33.004551 PCI: 00:15.1 read_resources bus 2 link: 0 done
1050 17:49:33.012165 PCI: 00:19.0 read_resources bus 3 link: 0
1051 17:49:33.019078 PCI: 00:19.0 read_resources bus 3 link: 0 done
1052 17:49:33.021997 PCI: 00:1d.0 read_resources bus 1 link: 0
1053 17:49:33.028719 PCI: 00:1d.0 read_resources bus 1 link: 0 done
1054 17:49:33.032268 PCI: 00:1e.2 read_resources bus 4 link: 0
1055 17:49:33.038894 PCI: 00:1e.2 read_resources bus 4 link: 0 done
1056 17:49:33.041936 PCI: 00:1e.3 read_resources bus 5 link: 0
1057 17:49:33.048857 PCI: 00:1e.3 read_resources bus 5 link: 0 done
1058 17:49:33.051857 PCI: 00:1f.0 read_resources bus 0 link: 0
1059 17:49:33.058400 PCI: 00:1f.0 read_resources bus 0 link: 0 done
1060 17:49:33.065361 DOMAIN: 0000 read_resources bus 0 link: 0 done
1061 17:49:33.068290 Root Device read_resources bus 0 link: 0 done
1062 17:49:33.072066 Done reading resources.
1063 17:49:33.078330 Show resources in subtree (Root Device)...After reading.
1064 17:49:33.081521 Root Device child on link 0 CPU_CLUSTER: 0
1065 17:49:33.084754 CPU_CLUSTER: 0 child on link 0 APIC: 00
1066 17:49:33.084838 APIC: 00
1067 17:49:33.088418 APIC: 04
1068 17:49:33.088517 APIC: 06
1069 17:49:33.091588 APIC: 01
1070 17:49:33.091685 APIC: 05
1071 17:49:33.091772 APIC: 07
1072 17:49:33.094711 APIC: 02
1073 17:49:33.094819 APIC: 03
1074 17:49:33.098308 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1075 17:49:33.151230 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1076 17:49:33.152137 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
1077 17:49:33.152272 PCI: 00:00.0
1078 17:49:33.152405 PCI: 00:00.0 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1079 17:49:33.152498 PCI: 00:00.0 resource base fed10000 size 8000 align 0 gran 0 limit 0 flags f0000200 index 1
1080 17:49:33.153134 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1081 17:49:33.200972 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1082 17:49:33.201744 PCI: 00:00.0 resource base fc000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1083 17:49:33.201869 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1084 17:49:33.202187 PCI: 00:00.0 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 6
1085 17:49:33.202300 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1086 17:49:33.209200 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1087 17:49:33.212422 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 9
1088 17:49:33.222296 PCI: 00:00.0 resource base c0000 size 99f40000 align 0 gran 0 limit 0 flags e0004200 index a
1089 17:49:33.232389 PCI: 00:00.0 resource base 9a000000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index b
1090 17:49:33.242118 PCI: 00:00.0 resource base 9b000000 size 4800000 align 0 gran 0 limit 0 flags f0000200 index c
1091 17:49:33.252496 PCI: 00:00.0 resource base 100000000 size 35e800000 align 0 gran 0 limit 0 flags e0004200 index d
1092 17:49:33.262248 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index e
1093 17:49:33.268677 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index f
1094 17:49:33.271787 PCI: 00:02.0
1095 17:49:33.281870 PCI: 00:02.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1096 17:49:33.292056 PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
1097 17:49:33.302292 PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
1098 17:49:33.302401 PCI: 00:04.0
1099 17:49:33.305377 PCI: 00:08.0
1100 17:49:33.315364 PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1101 17:49:33.315450 PCI: 00:12.0
1102 17:49:33.324883 PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1103 17:49:33.331599 PCI: 00:14.0 child on link 0 USB0 port 0
1104 17:49:33.341297 PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1105 17:49:33.344749 USB0 port 0 child on link 0 USB2 port 0
1106 17:49:33.344862 USB2 port 0
1107 17:49:33.348135 USB2 port 1
1108 17:49:33.348218 USB2 port 2
1109 17:49:33.351562 USB2 port 3
1110 17:49:33.355096 USB2 port 5
1111 17:49:33.355183 USB2 port 6
1112 17:49:33.358183 USB2 port 9
1113 17:49:33.358291 USB3 port 0
1114 17:49:33.361806 USB3 port 1
1115 17:49:33.361889 USB3 port 2
1116 17:49:33.364806 USB3 port 3
1117 17:49:33.364888 USB3 port 4
1118 17:49:33.368461 PCI: 00:14.2
1119 17:49:33.378538 PCI: 00:14.2 resource base 0 size 2000 align 13 gran 13 limit ffffffffffffffff flags 201 index 10
1120 17:49:33.387819 PCI: 00:14.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
1121 17:49:33.387906 PCI: 00:14.3
1122 17:49:33.398005 PCI: 00:14.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1123 17:49:33.404320 PCI: 00:15.0 child on link 0 I2C: 01:15
1124 17:49:33.411093 PCI: 00:15.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1125 17:49:33.414313 I2C: 01:15
1126 17:49:33.418049 PCI: 00:15.1 child on link 0 I2C: 02:5d
1127 17:49:33.427972 PCI: 00:15.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1128 17:49:33.431273 I2C: 02:5d
1129 17:49:33.431379 GENERIC: 0.0
1130 17:49:33.434433 PCI: 00:16.0
1131 17:49:33.444166 PCI: 00:16.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1132 17:49:33.444325 PCI: 00:17.0
1133 17:49:33.454356 PCI: 00:17.0 resource base 0 size 2000 align 13 gran 13 limit ffffffff flags 200 index 10
1134 17:49:33.464239 PCI: 00:17.0 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 14
1135 17:49:33.470752 PCI: 00:17.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
1136 17:49:33.480858 PCI: 00:17.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
1137 17:49:33.487530 PCI: 00:17.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
1138 17:49:33.497337 PCI: 00:17.0 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 24
1139 17:49:33.500466 PCI: 00:19.0 child on link 0 I2C: 03:1a
1140 17:49:33.510592 PCI: 00:19.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1141 17:49:33.513720 I2C: 03:1a
1142 17:49:33.513828 I2C: 03:38
1143 17:49:33.516924 I2C: 03:39
1144 17:49:33.517031 I2C: 03:3a
1145 17:49:33.520142 I2C: 03:3b
1146 17:49:33.524028 PCI: 00:1d.0 child on link 0 PCI: 01:00.0
1147 17:49:33.533470 PCI: 00:1d.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
1148 17:49:33.543569 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
1149 17:49:33.550039 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
1150 17:49:33.553673 PCI: 01:00.0
1151 17:49:33.563747 PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1152 17:49:33.563859 PCI: 00:1e.0
1153 17:49:33.576564 PCI: 00:1e.0 resource base fe032000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1154 17:49:33.586886 PCI: 00:1e.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
1155 17:49:33.589567 PCI: 00:1e.2 child on link 0 SPI: 00
1156 17:49:33.600075 PCI: 00:1e.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1157 17:49:33.600266 SPI: 00
1158 17:49:33.606203 PCI: 00:1e.3 child on link 0 SPI: 01
1159 17:49:33.616476 PCI: 00:1e.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1160 17:49:33.616817 SPI: 01
1161 17:49:33.619606 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1162 17:49:33.629880 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1163 17:49:33.639945 PCI: 00:1f.0 resource base 1800 size 100 align 0 gran 0 limit 0 flags c0000100 index 20
1164 17:49:33.640403 PNP: 0c09.0
1165 17:49:33.650107 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1166 17:49:33.650672 PCI: 00:1f.3
1167 17:49:33.659632 PCI: 00:1f.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1168 17:49:33.669647 PCI: 00:1f.3 resource base 0 size 100000 align 20 gran 20 limit ffffffffffffffff flags 201 index 20
1169 17:49:33.672507 PCI: 00:1f.4
1170 17:49:33.682606 PCI: 00:1f.4 resource base efa0 size 20 align 0 gran 0 limit efbf flags f0000100 index 20
1171 17:49:33.689455 PCI: 00:1f.4 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 10
1172 17:49:33.692349 PCI: 00:1f.5
1173 17:49:33.702698 PCI: 00:1f.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
1174 17:49:33.709421 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
1175 17:49:33.715552 PCI: 00:1d.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
1176 17:49:33.722378 PCI: 00:1d.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
1177 17:49:33.726064 PCI: 00:02.0 20 * [0x0 - 0x3f] io
1178 17:49:33.729257 PCI: 00:17.0 20 * [0x40 - 0x5f] io
1179 17:49:33.732357 PCI: 00:17.0 18 * [0x60 - 0x67] io
1180 17:49:33.735998 PCI: 00:17.0 1c * [0x68 - 0x6b] io
1181 17:49:33.742495 DOMAIN: 0000 io: base: 6c size: 6c align: 6 gran: 0 limit: ffff done
1182 17:49:33.748813 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
1183 17:49:33.755641 PCI: 00:1d.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
1184 17:49:33.765187 PCI: 00:1d.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
1185 17:49:33.772206 PCI: 00:1d.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
1186 17:49:33.775431 PCI: 01:00.0 10 * [0x0 - 0x3fff] mem
1187 17:49:33.785488 PCI: 00:1d.0 mem: base: 4000 size: 100000 align: 20 gran: 20 limit: ffffffff done
1188 17:49:33.788482 PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem
1189 17:49:33.791801 PCI: 00:02.0 10 * [0x10000000 - 0x10ffffff] mem
1190 17:49:33.798430 PCI: 00:1d.0 20 * [0x11000000 - 0x110fffff] mem
1191 17:49:33.801638 PCI: 00:1f.3 20 * [0x11100000 - 0x111fffff] mem
1192 17:49:33.808471 PCI: 00:14.0 10 * [0x11200000 - 0x1120ffff] mem
1193 17:49:33.811545 PCI: 00:14.3 10 * [0x11210000 - 0x11213fff] mem
1194 17:49:33.818183 PCI: 00:1f.3 10 * [0x11214000 - 0x11217fff] mem
1195 17:49:33.821194 PCI: 00:14.2 10 * [0x11218000 - 0x11219fff] mem
1196 17:49:33.828140 PCI: 00:17.0 10 * [0x1121a000 - 0x1121bfff] mem
1197 17:49:33.831459 PCI: 00:08.0 10 * [0x1121c000 - 0x1121cfff] mem
1198 17:49:33.838353 PCI: 00:12.0 10 * [0x1121d000 - 0x1121dfff] mem
1199 17:49:33.841473 PCI: 00:14.2 18 * [0x1121e000 - 0x1121efff] mem
1200 17:49:33.847777 PCI: 00:15.0 10 * [0x1121f000 - 0x1121ffff] mem
1201 17:49:33.851555 PCI: 00:15.1 10 * [0x11220000 - 0x11220fff] mem
1202 17:49:33.857837 PCI: 00:16.0 10 * [0x11221000 - 0x11221fff] mem
1203 17:49:33.861525 PCI: 00:19.0 10 * [0x11222000 - 0x11222fff] mem
1204 17:49:33.864476 PCI: 00:1e.0 18 * [0x11223000 - 0x11223fff] mem
1205 17:49:33.870822 PCI: 00:1e.2 10 * [0x11224000 - 0x11224fff] mem
1206 17:49:33.874374 PCI: 00:1e.3 10 * [0x11225000 - 0x11225fff] mem
1207 17:49:33.880897 PCI: 00:1f.5 10 * [0x11226000 - 0x11226fff] mem
1208 17:49:33.884618 PCI: 00:17.0 24 * [0x11227000 - 0x112277ff] mem
1209 17:49:33.890985 PCI: 00:17.0 14 * [0x11228000 - 0x112280ff] mem
1210 17:49:33.894088 PCI: 00:1f.4 10 * [0x11229000 - 0x112290ff] mem
1211 17:49:33.904170 DOMAIN: 0000 mem: base: 11229100 size: 11229100 align: 28 gran: 0 limit: ffffffff done
1212 17:49:33.907881 avoid_fixed_resources: DOMAIN: 0000
1213 17:49:33.914051 avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
1214 17:49:33.920753 avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
1215 17:49:33.927618 constrain_resources: PCI: 00:00.0 00 base e0000000 limit efffffff mem (fixed)
1216 17:49:33.934314 constrain_resources: PCI: 00:00.0 09 base 00000000 limit 0009ffff mem (fixed)
1217 17:49:33.940779 constrain_resources: PCI: 00:00.0 0a base 000c0000 limit 99ffffff mem (fixed)
1218 17:49:33.950755 constrain_resources: PCI: 00:00.0 0b base 9a000000 limit 9affffff mem (fixed)
1219 17:49:33.957181 constrain_resources: PCI: 00:00.0 0c base 9b000000 limit 9f7fffff mem (fixed)
1220 17:49:33.963555 constrain_resources: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
1221 17:49:33.974080 constrain_resources: PCI: 00:1f.0 20 base 00001800 limit 000018ff io (fixed)
1222 17:49:33.980249 constrain_resources: PCI: 00:1f.4 20 base 0000efa0 limit 0000efbf io (fixed)
1223 17:49:33.986652 avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001900 limit 0000ef9f
1224 17:49:33.993489 avoid_fixed_resources:@DOMAIN: 0000 10000100 base c0000000 limit dfffffff
1225 17:49:33.996923 Setting resources...
1226 17:49:34.003599 DOMAIN: 0000 io: base:1900 size:6c align:6 gran:0 limit:ef9f
1227 17:49:34.006596 PCI: 00:02.0 20 * [0x1c00 - 0x1c3f] io
1228 17:49:34.010196 PCI: 00:17.0 20 * [0x1c40 - 0x1c5f] io
1229 17:49:34.016554 PCI: 00:17.0 18 * [0x1c60 - 0x1c67] io
1230 17:49:34.020075 PCI: 00:17.0 1c * [0x1c68 - 0x1c6b] io
1231 17:49:34.026420 DOMAIN: 0000 io: next_base: 1c6c size: 6c align: 6 gran: 0 done
1232 17:49:34.033323 PCI: 00:1d.0 io: base:ef9f size:0 align:12 gran:12 limit:ef9f
1233 17:49:34.036898 PCI: 00:1d.0 io: next_base: ef9f size: 0 align: 12 gran: 12 done
1234 17:49:34.046490 DOMAIN: 0000 mem: base:c0000000 size:11229100 align:28 gran:0 limit:dfffffff
1235 17:49:34.050129 PCI: 00:02.0 18 * [0xc0000000 - 0xcfffffff] prefmem
1236 17:49:34.056396 PCI: 00:02.0 10 * [0xd0000000 - 0xd0ffffff] mem
1237 17:49:34.059728 PCI: 00:1d.0 20 * [0xd1000000 - 0xd10fffff] mem
1238 17:49:34.066554 PCI: 00:1f.3 20 * [0xd1100000 - 0xd11fffff] mem
1239 17:49:34.069590 PCI: 00:14.0 10 * [0xd1200000 - 0xd120ffff] mem
1240 17:49:34.076753 PCI: 00:14.3 10 * [0xd1210000 - 0xd1213fff] mem
1241 17:49:34.079901 PCI: 00:1f.3 10 * [0xd1214000 - 0xd1217fff] mem
1242 17:49:34.086258 PCI: 00:14.2 10 * [0xd1218000 - 0xd1219fff] mem
1243 17:49:34.089913 PCI: 00:17.0 10 * [0xd121a000 - 0xd121bfff] mem
1244 17:49:34.096444 PCI: 00:08.0 10 * [0xd121c000 - 0xd121cfff] mem
1245 17:49:34.099674 PCI: 00:12.0 10 * [0xd121d000 - 0xd121dfff] mem
1246 17:49:34.103270 PCI: 00:14.2 18 * [0xd121e000 - 0xd121efff] mem
1247 17:49:34.109822 PCI: 00:15.0 10 * [0xd121f000 - 0xd121ffff] mem
1248 17:49:34.112825 PCI: 00:15.1 10 * [0xd1220000 - 0xd1220fff] mem
1249 17:49:34.119656 PCI: 00:16.0 10 * [0xd1221000 - 0xd1221fff] mem
1250 17:49:34.122830 PCI: 00:19.0 10 * [0xd1222000 - 0xd1222fff] mem
1251 17:49:34.129433 PCI: 00:1e.0 18 * [0xd1223000 - 0xd1223fff] mem
1252 17:49:34.133309 PCI: 00:1e.2 10 * [0xd1224000 - 0xd1224fff] mem
1253 17:49:34.139344 PCI: 00:1e.3 10 * [0xd1225000 - 0xd1225fff] mem
1254 17:49:34.142946 PCI: 00:1f.5 10 * [0xd1226000 - 0xd1226fff] mem
1255 17:49:34.149578 PCI: 00:17.0 24 * [0xd1227000 - 0xd12277ff] mem
1256 17:49:34.153046 PCI: 00:17.0 14 * [0xd1228000 - 0xd12280ff] mem
1257 17:49:34.159148 PCI: 00:1f.4 10 * [0xd1229000 - 0xd12290ff] mem
1258 17:49:34.166147 DOMAIN: 0000 mem: next_base: d1229100 size: 11229100 align: 28 gran: 0 done
1259 17:49:34.172973 PCI: 00:1d.0 prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff
1260 17:49:34.179173 PCI: 00:1d.0 prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done
1261 17:49:34.189282 PCI: 00:1d.0 mem: base:d1000000 size:100000 align:20 gran:20 limit:d10fffff
1262 17:49:34.192475 PCI: 01:00.0 10 * [0xd1000000 - 0xd1003fff] mem
1263 17:49:34.199215 PCI: 00:1d.0 mem: next_base: d1004000 size: 100000 align: 20 gran: 20 done
1264 17:49:34.205800 Root Device assign_resources, bus 0 link: 0
1265 17:49:34.209100 DOMAIN: 0000 assign_resources, bus 0 link: 0
1266 17:49:34.218677 PCI: 00:02.0 10 <- [0x00d0000000 - 0x00d0ffffff] size 0x01000000 gran 0x18 mem64
1267 17:49:34.225279 PCI: 00:02.0 18 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x1c prefmem64
1268 17:49:34.232128 PCI: 00:02.0 20 <- [0x0000001c00 - 0x0000001c3f] size 0x00000040 gran 0x06 io
1269 17:49:34.242181 PCI: 00:08.0 10 <- [0x00d121c000 - 0x00d121cfff] size 0x00001000 gran 0x0c mem64
1270 17:49:34.249102 PCI: 00:12.0 10 <- [0x00d121d000 - 0x00d121dfff] size 0x00001000 gran 0x0c mem64
1271 17:49:34.258731 PCI: 00:14.0 10 <- [0x00d1200000 - 0x00d120ffff] size 0x00010000 gran 0x10 mem64
1272 17:49:34.262299 PCI: 00:14.0 assign_resources, bus 0 link: 0
1273 17:49:34.268799 PCI: 00:14.0 assign_resources, bus 0 link: 0
1274 17:49:34.275194 PCI: 00:14.2 10 <- [0x00d1218000 - 0x00d1219fff] size 0x00002000 gran 0x0d mem64
1275 17:49:34.285196 PCI: 00:14.2 18 <- [0x00d121e000 - 0x00d121efff] size 0x00001000 gran 0x0c mem64
1276 17:49:34.292103 PCI: 00:14.3 10 <- [0x00d1210000 - 0x00d1213fff] size 0x00004000 gran 0x0e mem64
1277 17:49:34.301566 PCI: 00:15.0 10 <- [0x00d121f000 - 0x00d121ffff] size 0x00001000 gran 0x0c mem64
1278 17:49:34.305272 PCI: 00:15.0 assign_resources, bus 1 link: 0
1279 17:49:34.308268 PCI: 00:15.0 assign_resources, bus 1 link: 0
1280 17:49:34.318441 PCI: 00:15.1 10 <- [0x00d1220000 - 0x00d1220fff] size 0x00001000 gran 0x0c mem64
1281 17:49:34.322117 PCI: 00:15.1 assign_resources, bus 2 link: 0
1282 17:49:34.328694 PCI: 00:15.1 assign_resources, bus 2 link: 0
1283 17:49:34.335086 PCI: 00:16.0 10 <- [0x00d1221000 - 0x00d1221fff] size 0x00001000 gran 0x0c mem64
1284 17:49:34.345080 PCI: 00:17.0 10 <- [0x00d121a000 - 0x00d121bfff] size 0x00002000 gran 0x0d mem
1285 17:49:34.351863 PCI: 00:17.0 14 <- [0x00d1228000 - 0x00d12280ff] size 0x00000100 gran 0x08 mem
1286 17:49:34.358008 PCI: 00:17.0 18 <- [0x0000001c60 - 0x0000001c67] size 0x00000008 gran 0x03 io
1287 17:49:34.368272 PCI: 00:17.0 1c <- [0x0000001c68 - 0x0000001c6b] size 0x00000004 gran 0x02 io
1288 17:49:34.374923 PCI: 00:17.0 20 <- [0x0000001c40 - 0x0000001c5f] size 0x00000020 gran 0x05 io
1289 17:49:34.380942 PCI: 00:17.0 24 <- [0x00d1227000 - 0x00d12277ff] size 0x00000800 gran 0x0b mem
1290 17:49:34.391072 PCI: 00:19.0 10 <- [0x00d1222000 - 0x00d1222fff] size 0x00001000 gran 0x0c mem64
1291 17:49:34.394139 PCI: 00:19.0 assign_resources, bus 3 link: 0
1292 17:49:34.401158 PCI: 00:19.0 assign_resources, bus 3 link: 0
1293 17:49:34.407375 PCI: 00:1d.0 1c <- [0x000000ef9f - 0x000000ef9e] size 0x00000000 gran 0x0c bus 01 io
1294 17:49:34.417667 PCI: 00:1d.0 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
1295 17:49:34.427420 PCI: 00:1d.0 20 <- [0x00d1000000 - 0x00d10fffff] size 0x00100000 gran 0x14 bus 01 mem
1296 17:49:34.430647 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1297 17:49:34.437422 PCI: 01:00.0 10 <- [0x00d1000000 - 0x00d1003fff] size 0x00004000 gran 0x0e mem64
1298 17:49:34.443865 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1299 17:49:34.450505 PCI: 00:1e.0 18 <- [0x00d1223000 - 0x00d1223fff] size 0x00001000 gran 0x0c mem64
1300 17:49:34.460910 PCI: 00:1e.2 10 <- [0x00d1224000 - 0x00d1224fff] size 0x00001000 gran 0x0c mem64
1301 17:49:34.463907 PCI: 00:1e.2 assign_resources, bus 4 link: 0
1302 17:49:34.470485 PCI: 00:1e.2 assign_resources, bus 4 link: 0
1303 17:49:34.476987 PCI: 00:1e.3 10 <- [0x00d1225000 - 0x00d1225fff] size 0x00001000 gran 0x0c mem64
1304 17:49:34.480658 PCI: 00:1e.3 assign_resources, bus 5 link: 0
1305 17:49:34.487640 PCI: 00:1e.3 assign_resources, bus 5 link: 0
1306 17:49:34.490796 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1307 17:49:34.497167 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1308 17:49:34.500267 LPC: Trying to open IO window from 800 size 1ff
1309 17:49:34.510496 PCI: 00:1f.3 10 <- [0x00d1214000 - 0x00d1217fff] size 0x00004000 gran 0x0e mem64
1310 17:49:34.516871 PCI: 00:1f.3 20 <- [0x00d1100000 - 0x00d11fffff] size 0x00100000 gran 0x14 mem64
1311 17:49:34.526783 PCI: 00:1f.4 10 <- [0x00d1229000 - 0x00d12290ff] size 0x00000100 gran 0x08 mem64
1312 17:49:34.533756 PCI: 00:1f.5 10 <- [0x00d1226000 - 0x00d1226fff] size 0x00001000 gran 0x0c mem
1313 17:49:34.539778 DOMAIN: 0000 assign_resources, bus 0 link: 0
1314 17:49:34.543643 Root Device assign_resources, bus 0 link: 0
1315 17:49:34.546765 Done setting resources.
1316 17:49:34.553192 Show resources in subtree (Root Device)...After assigning values.
1317 17:49:34.556632 Root Device child on link 0 CPU_CLUSTER: 0
1318 17:49:34.559619 CPU_CLUSTER: 0 child on link 0 APIC: 00
1319 17:49:34.563181 APIC: 00
1320 17:49:34.563284 APIC: 04
1321 17:49:34.566212 APIC: 06
1322 17:49:34.566311 APIC: 01
1323 17:49:34.566413 APIC: 05
1324 17:49:34.569919 APIC: 07
1325 17:49:34.569993 APIC: 02
1326 17:49:34.570054 APIC: 03
1327 17:49:34.576296 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1328 17:49:34.586349 DOMAIN: 0000 resource base 1900 size 6c align 6 gran 0 limit ef9f flags 40040100 index 10000000
1329 17:49:34.596303 DOMAIN: 0000 resource base c0000000 size 11229100 align 28 gran 0 limit dfffffff flags 40040200 index 10000100
1330 17:49:34.599584 PCI: 00:00.0
1331 17:49:34.606062 PCI: 00:00.0 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1332 17:49:34.616034 PCI: 00:00.0 resource base fed10000 size 8000 align 0 gran 0 limit 0 flags f0000200 index 1
1333 17:49:34.626164 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1334 17:49:34.636010 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1335 17:49:34.646076 PCI: 00:00.0 resource base fc000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1336 17:49:34.655549 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1337 17:49:34.662241 PCI: 00:00.0 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 6
1338 17:49:34.672079 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1339 17:49:34.682012 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1340 17:49:34.691949 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 9
1341 17:49:34.701942 PCI: 00:00.0 resource base c0000 size 99f40000 align 0 gran 0 limit 0 flags e0004200 index a
1342 17:49:34.712100 PCI: 00:00.0 resource base 9a000000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index b
1343 17:49:34.718350 PCI: 00:00.0 resource base 9b000000 size 4800000 align 0 gran 0 limit 0 flags f0000200 index c
1344 17:49:34.728414 PCI: 00:00.0 resource base 100000000 size 35e800000 align 0 gran 0 limit 0 flags e0004200 index d
1345 17:49:34.738359 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index e
1346 17:49:34.748291 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index f
1347 17:49:34.751253 PCI: 00:02.0
1348 17:49:34.761028 PCI: 00:02.0 resource base d0000000 size 1000000 align 24 gran 24 limit d0ffffff flags 60000201 index 10
1349 17:49:34.771504 PCI: 00:02.0 resource base c0000000 size 10000000 align 28 gran 28 limit cfffffff flags 60001201 index 18
1350 17:49:34.780944 PCI: 00:02.0 resource base 1c00 size 40 align 6 gran 6 limit 1c3f flags 60000100 index 20
1351 17:49:34.781032 PCI: 00:04.0
1352 17:49:34.784468 PCI: 00:08.0
1353 17:49:34.794241 PCI: 00:08.0 resource base d121c000 size 1000 align 12 gran 12 limit d121cfff flags 60000201 index 10
1354 17:49:34.794353 PCI: 00:12.0
1355 17:49:34.803991 PCI: 00:12.0 resource base d121d000 size 1000 align 12 gran 12 limit d121dfff flags 60000201 index 10
1356 17:49:34.810844 PCI: 00:14.0 child on link 0 USB0 port 0
1357 17:49:34.820958 PCI: 00:14.0 resource base d1200000 size 10000 align 16 gran 16 limit d120ffff flags 60000201 index 10
1358 17:49:34.824161 USB0 port 0 child on link 0 USB2 port 0
1359 17:49:34.827289 USB2 port 0
1360 17:49:34.827363 USB2 port 1
1361 17:49:34.830448 USB2 port 2
1362 17:49:34.830590 USB2 port 3
1363 17:49:34.834212 USB2 port 5
1364 17:49:34.834315 USB2 port 6
1365 17:49:34.837329 USB2 port 9
1366 17:49:34.840485 USB3 port 0
1367 17:49:34.840560 USB3 port 1
1368 17:49:34.843633 USB3 port 2
1369 17:49:34.843720 USB3 port 3
1370 17:49:34.847530 USB3 port 4
1371 17:49:34.847612 PCI: 00:14.2
1372 17:49:34.857362 PCI: 00:14.2 resource base d1218000 size 2000 align 13 gran 13 limit d1219fff flags 60000201 index 10
1373 17:49:34.866918 PCI: 00:14.2 resource base d121e000 size 1000 align 12 gran 12 limit d121efff flags 60000201 index 18
1374 17:49:34.870139 PCI: 00:14.3
1375 17:49:34.880588 PCI: 00:14.3 resource base d1210000 size 4000 align 14 gran 14 limit d1213fff flags 60000201 index 10
1376 17:49:34.883516 PCI: 00:15.0 child on link 0 I2C: 01:15
1377 17:49:34.893527 PCI: 00:15.0 resource base d121f000 size 1000 align 12 gran 12 limit d121ffff flags 60000201 index 10
1378 17:49:34.896572 I2C: 01:15
1379 17:49:34.900215 PCI: 00:15.1 child on link 0 I2C: 02:5d
1380 17:49:34.910140 PCI: 00:15.1 resource base d1220000 size 1000 align 12 gran 12 limit d1220fff flags 60000201 index 10
1381 17:49:34.913304 I2C: 02:5d
1382 17:49:34.913384 GENERIC: 0.0
1383 17:49:34.916389 PCI: 00:16.0
1384 17:49:34.926385 PCI: 00:16.0 resource base d1221000 size 1000 align 12 gran 12 limit d1221fff flags 60000201 index 10
1385 17:49:34.926492 PCI: 00:17.0
1386 17:49:34.939547 PCI: 00:17.0 resource base d121a000 size 2000 align 13 gran 13 limit d121bfff flags 60000200 index 10
1387 17:49:34.949479 PCI: 00:17.0 resource base d1228000 size 100 align 12 gran 8 limit d12280ff flags 60000200 index 14
1388 17:49:34.956358 PCI: 00:17.0 resource base 1c60 size 8 align 3 gran 3 limit 1c67 flags 60000100 index 18
1389 17:49:34.966418 PCI: 00:17.0 resource base 1c68 size 4 align 2 gran 2 limit 1c6b flags 60000100 index 1c
1390 17:49:34.976236 PCI: 00:17.0 resource base 1c40 size 20 align 5 gran 5 limit 1c5f flags 60000100 index 20
1391 17:49:34.986138 PCI: 00:17.0 resource base d1227000 size 800 align 12 gran 11 limit d12277ff flags 60000200 index 24
1392 17:49:34.989186 PCI: 00:19.0 child on link 0 I2C: 03:1a
1393 17:49:34.999305 PCI: 00:19.0 resource base d1222000 size 1000 align 12 gran 12 limit d1222fff flags 60000201 index 10
1394 17:49:35.002705 I2C: 03:1a
1395 17:49:35.002803 I2C: 03:38
1396 17:49:35.006062 I2C: 03:39
1397 17:49:35.006160 I2C: 03:3a
1398 17:49:35.009175 I2C: 03:3b
1399 17:49:35.012758 PCI: 00:1d.0 child on link 0 PCI: 01:00.0
1400 17:49:35.022319 PCI: 00:1d.0 resource base ef9f size 0 align 12 gran 12 limit ef9f flags 60080102 index 1c
1401 17:49:35.032255 PCI: 00:1d.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081202 index 24
1402 17:49:35.042293 PCI: 00:1d.0 resource base d1000000 size 100000 align 20 gran 20 limit d10fffff flags 60080202 index 20
1403 17:49:35.045754 PCI: 01:00.0
1404 17:49:35.055791 PCI: 01:00.0 resource base d1000000 size 4000 align 14 gran 14 limit d1003fff flags 60000201 index 10
1405 17:49:35.055898 PCI: 00:1e.0
1406 17:49:35.068530 PCI: 00:1e.0 resource base fe032000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1407 17:49:35.078390 PCI: 00:1e.0 resource base d1223000 size 1000 align 12 gran 12 limit d1223fff flags 60000201 index 18
1408 17:49:35.081748 PCI: 00:1e.2 child on link 0 SPI: 00
1409 17:49:35.091823 PCI: 00:1e.2 resource base d1224000 size 1000 align 12 gran 12 limit d1224fff flags 60000201 index 10
1410 17:49:35.091907 SPI: 00
1411 17:49:35.098641 PCI: 00:1e.3 child on link 0 SPI: 01
1412 17:49:35.108028 PCI: 00:1e.3 resource base d1225000 size 1000 align 12 gran 12 limit d1225fff flags 60000201 index 10
1413 17:49:35.108177 SPI: 01
1414 17:49:35.111618 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1415 17:49:35.121314 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1416 17:49:35.131235 PCI: 00:1f.0 resource base 1800 size 100 align 0 gran 0 limit 0 flags c0000100 index 20
1417 17:49:35.131322 PNP: 0c09.0
1418 17:49:35.141317 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1419 17:49:35.141422 PCI: 00:1f.3
1420 17:49:35.154420 PCI: 00:1f.3 resource base d1214000 size 4000 align 14 gran 14 limit d1217fff flags 60000201 index 10
1421 17:49:35.164476 PCI: 00:1f.3 resource base d1100000 size 100000 align 20 gran 20 limit d11fffff flags 60000201 index 20
1422 17:49:35.164562 PCI: 00:1f.4
1423 17:49:35.174550 PCI: 00:1f.4 resource base efa0 size 20 align 0 gran 0 limit efbf flags f0000100 index 20
1424 17:49:35.184311 PCI: 00:1f.4 resource base d1229000 size 100 align 12 gran 8 limit d12290ff flags 60000201 index 10
1425 17:49:35.187429 PCI: 00:1f.5
1426 17:49:35.197529 PCI: 00:1f.5 resource base d1226000 size 1000 align 12 gran 12 limit d1226fff flags 60000200 index 10
1427 17:49:35.197634 Done allocating resources.
1428 17:49:35.204380 BS: BS_DEV_RESOURCES times (ms): entry 0 run 30 exit 0
1429 17:49:35.207331 Enabling resources...
1430 17:49:35.210980 PCI: 00:00.0 subsystem <- 8086/9b61
1431 17:49:35.213956 PCI: 00:00.0 cmd <- 06
1432 17:49:35.217586 PCI: 00:02.0 subsystem <- 8086/9b41
1433 17:49:35.220496 PCI: 00:02.0 cmd <- 03
1434 17:49:35.223974 PCI: 00:08.0 cmd <- 06
1435 17:49:35.227610 PCI: 00:12.0 subsystem <- 8086/02f9
1436 17:49:35.230578 PCI: 00:12.0 cmd <- 02
1437 17:49:35.234219 PCI: 00:14.0 subsystem <- 8086/02ed
1438 17:49:35.237365 PCI: 00:14.0 cmd <- 02
1439 17:49:35.237442 PCI: 00:14.2 cmd <- 02
1440 17:49:35.243649 PCI: 00:14.3 subsystem <- 8086/02f0
1441 17:49:35.243725 PCI: 00:14.3 cmd <- 02
1442 17:49:35.247315 PCI: 00:15.0 subsystem <- 8086/02e8
1443 17:49:35.250569 PCI: 00:15.0 cmd <- 02
1444 17:49:35.253710 PCI: 00:15.1 subsystem <- 8086/02e9
1445 17:49:35.256808 PCI: 00:15.1 cmd <- 02
1446 17:49:35.260587 PCI: 00:16.0 subsystem <- 8086/02e0
1447 17:49:35.263716 PCI: 00:16.0 cmd <- 02
1448 17:49:35.266810 PCI: 00:17.0 subsystem <- 8086/02d3
1449 17:49:35.270010 PCI: 00:17.0 cmd <- 03
1450 17:49:35.273716 PCI: 00:19.0 subsystem <- 8086/02c5
1451 17:49:35.276931 PCI: 00:19.0 cmd <- 02
1452 17:49:35.279990 PCI: 00:1d.0 bridge ctrl <- 0013
1453 17:49:35.283615 PCI: 00:1d.0 subsystem <- 8086/02b0
1454 17:49:35.286738 PCI: 00:1d.0 cmd <- 06
1455 17:49:35.290018 PCI: 00:1e.0 subsystem <- 8086/02a8
1456 17:49:35.293035 PCI: 00:1e.0 cmd <- 06
1457 17:49:35.296943 PCI: 00:1e.2 subsystem <- 8086/02aa
1458 17:49:35.297041 PCI: 00:1e.2 cmd <- 06
1459 17:49:35.303686 PCI: 00:1e.3 subsystem <- 8086/02ab
1460 17:49:35.303798 PCI: 00:1e.3 cmd <- 02
1461 17:49:35.306607 PCI: 00:1f.0 subsystem <- 8086/0284
1462 17:49:35.309584 PCI: 00:1f.0 cmd <- 407
1463 17:49:35.313012 PCI: 00:1f.3 subsystem <- 8086/02c8
1464 17:49:35.316502 PCI: 00:1f.3 cmd <- 02
1465 17:49:35.319985 PCI: 00:1f.4 subsystem <- 8086/02a3
1466 17:49:35.322993 PCI: 00:1f.4 cmd <- 03
1467 17:49:35.326715 PCI: 00:1f.5 subsystem <- 8086/02a4
1468 17:49:35.329443 PCI: 00:1f.5 cmd <- 406
1469 17:49:35.338202 PCI: 01:00.0 cmd <- 02
1470 17:49:35.343783 done.
1471 17:49:35.355713 ME: Version: 14.0.39.1367
1472 17:49:35.362079 BS: BS_DEV_ENABLE times (ms): entry 0 run 17 exit 11
1473 17:49:35.365194 Initializing devices...
1474 17:49:35.365291 Root Device init ...
1475 17:49:35.372130 Chrome EC: Set SMI mask to 0x0000000000000000
1476 17:49:35.375197 Chrome EC: clear events_b mask to 0x0000000000000000
1477 17:49:35.382007 Chrome EC: Set S5 LAZY WAKE mask to 0x0000000000000006
1478 17:49:35.388868 Chrome EC: Set S3 LAZY WAKE mask to 0x0000000014001006
1479 17:49:35.394925 Chrome EC: Set S0iX LAZY WAKE mask to 0x0000000014081006
1480 17:49:35.398725 Chrome EC: Set WAKE mask to 0x0000000000000000
1481 17:49:35.404952 Root Device init finished in 35350 usecs
1482 17:49:35.405028 CPU_CLUSTER: 0 init ...
1483 17:49:35.411680 CPU_CLUSTER: 0 init finished in 2449 usecs
1484 17:49:35.416282 PCI: 00:00.0 init ...
1485 17:49:35.419516 CPU TDP: 15 Watts
1486 17:49:35.423058 CPU PL2 = 64 Watts
1487 17:49:35.425951 PCI: 00:00.0 init finished in 7082 usecs
1488 17:49:35.429443 PCI: 00:02.0 init ...
1489 17:49:35.432573 PCI: 00:02.0 init finished in 2255 usecs
1490 17:49:35.436172 PCI: 00:08.0 init ...
1491 17:49:35.439044 PCI: 00:08.0 init finished in 2254 usecs
1492 17:49:35.442409 PCI: 00:12.0 init ...
1493 17:49:35.446048 PCI: 00:12.0 init finished in 2254 usecs
1494 17:49:35.449458 PCI: 00:14.0 init ...
1495 17:49:35.452633 PCI: 00:14.0 init finished in 2254 usecs
1496 17:49:35.455788 PCI: 00:14.2 init ...
1497 17:49:35.458901 PCI: 00:14.2 init finished in 2253 usecs
1498 17:49:35.462777 PCI: 00:14.3 init ...
1499 17:49:35.465922 PCI: 00:14.3 init finished in 2270 usecs
1500 17:49:35.469233 PCI: 00:15.0 init ...
1501 17:49:35.472355 DW I2C bus 0 at 0xd121f000 (400 KHz)
1502 17:49:35.475513 PCI: 00:15.0 init finished in 5981 usecs
1503 17:49:35.479188 PCI: 00:15.1 init ...
1504 17:49:35.482344 DW I2C bus 1 at 0xd1220000 (400 KHz)
1505 17:49:35.489334 PCI: 00:15.1 init finished in 5972 usecs
1506 17:49:35.489412 PCI: 00:16.0 init ...
1507 17:49:35.496093 PCI: 00:16.0 init finished in 2254 usecs
1508 17:49:35.499490 PCI: 00:19.0 init ...
1509 17:49:35.502479 DW I2C bus 4 at 0xd1222000 (400 KHz)
1510 17:49:35.505547 PCI: 00:19.0 init finished in 5981 usecs
1511 17:49:35.508734 PCI: 00:1d.0 init ...
1512 17:49:35.512075 Initializing PCH PCIe bridge.
1513 17:49:35.515906 PCI: 00:1d.0 init finished in 5290 usecs
1514 17:49:35.518933 PCI: 00:1f.0 init ...
1515 17:49:35.522538 IOAPIC: Initializing IOAPIC at 0xfec00000
1516 17:49:35.528665 IOAPIC: Bootstrap Processor Local APIC = 0x00
1517 17:49:35.528750 IOAPIC: ID = 0x02
1518 17:49:35.531690 IOAPIC: Dumping registers
1519 17:49:35.535285 reg 0x0000: 0x02000000
1520 17:49:35.538685 reg 0x0001: 0x00770020
1521 17:49:35.538783 reg 0x0002: 0x00000000
1522 17:49:35.544977 PCI: 00:1f.0 init finished in 23554 usecs
1523 17:49:35.548457 PCI: 00:1f.4 init ...
1524 17:49:35.551335 PCI: 00:1f.4 init finished in 2263 usecs
1525 17:49:35.562890 PCI: 01:00.0 init ...
1526 17:49:35.566157 PCI: 01:00.0 init finished in 2253 usecs
1527 17:49:35.569951 PNP: 0c09.0 init ...
1528 17:49:35.573703 Google Chrome EC uptime: 11.087 seconds
1529 17:49:35.580077 Google Chrome AP resets since EC boot: 0
1530 17:49:35.583245 Google Chrome most recent AP reset causes:
1531 17:49:35.589810 Google Chrome EC reset flags at last EC boot: reset-pin
1532 17:49:35.593417 PNP: 0c09.0 init finished in 20584 usecs
1533 17:49:35.596525 Devices initialized
1534 17:49:35.600087 Show all devs... After init.
1535 17:49:35.600185 Root Device: enabled 1
1536 17:49:35.603246 CPU_CLUSTER: 0: enabled 1
1537 17:49:35.606308 DOMAIN: 0000: enabled 1
1538 17:49:35.606407 APIC: 00: enabled 1
1539 17:49:35.610129 PCI: 00:00.0: enabled 1
1540 17:49:35.613085 PCI: 00:02.0: enabled 1
1541 17:49:35.616794 PCI: 00:04.0: enabled 0
1542 17:49:35.616947 PCI: 00:05.0: enabled 0
1543 17:49:35.619867 PCI: 00:12.0: enabled 1
1544 17:49:35.623044 PCI: 00:12.5: enabled 0
1545 17:49:35.626121 PCI: 00:12.6: enabled 0
1546 17:49:35.626209 PCI: 00:14.0: enabled 1
1547 17:49:35.629562 PCI: 00:14.1: enabled 0
1548 17:49:35.633091 PCI: 00:14.3: enabled 1
1549 17:49:35.633189 PCI: 00:14.5: enabled 0
1550 17:49:35.636238 PCI: 00:15.0: enabled 1
1551 17:49:35.639418 PCI: 00:15.1: enabled 1
1552 17:49:35.642917 PCI: 00:15.2: enabled 0
1553 17:49:35.643012 PCI: 00:15.3: enabled 0
1554 17:49:35.645893 PCI: 00:16.0: enabled 1
1555 17:49:35.649448 PCI: 00:16.1: enabled 0
1556 17:49:35.652893 PCI: 00:16.2: enabled 0
1557 17:49:35.652995 PCI: 00:16.3: enabled 0
1558 17:49:35.655913 PCI: 00:16.4: enabled 0
1559 17:49:35.659512 PCI: 00:16.5: enabled 0
1560 17:49:35.662483 PCI: 00:17.0: enabled 1
1561 17:49:35.662591 PCI: 00:19.0: enabled 1
1562 17:49:35.665971 PCI: 00:19.1: enabled 0
1563 17:49:35.669453 PCI: 00:19.2: enabled 0
1564 17:49:35.672761 PCI: 00:1a.0: enabled 0
1565 17:49:35.672901 PCI: 00:1c.0: enabled 0
1566 17:49:35.675914 PCI: 00:1c.1: enabled 0
1567 17:49:35.679031 PCI: 00:1c.2: enabled 0
1568 17:49:35.679107 PCI: 00:1c.3: enabled 0
1569 17:49:35.682883 PCI: 00:1c.4: enabled 0
1570 17:49:35.685942 PCI: 00:1c.5: enabled 0
1571 17:49:35.689084 PCI: 00:1c.6: enabled 0
1572 17:49:35.689162 PCI: 00:1c.7: enabled 0
1573 17:49:35.692185 PCI: 00:1d.0: enabled 1
1574 17:49:35.695960 PCI: 00:1d.1: enabled 0
1575 17:49:35.699133 PCI: 00:1d.2: enabled 0
1576 17:49:35.699209 PCI: 00:1d.3: enabled 0
1577 17:49:35.702156 PCI: 00:1d.4: enabled 0
1578 17:49:35.705909 PCI: 00:1d.5: enabled 0
1579 17:49:35.708992 PCI: 00:1e.0: enabled 1
1580 17:49:35.709104 PCI: 00:1e.1: enabled 0
1581 17:49:35.712029 PCI: 00:1e.2: enabled 1
1582 17:49:35.715800 PCI: 00:1e.3: enabled 1
1583 17:49:35.718932 PCI: 00:1f.0: enabled 1
1584 17:49:35.719010 PCI: 00:1f.1: enabled 0
1585 17:49:35.722056 PCI: 00:1f.2: enabled 0
1586 17:49:35.725239 PCI: 00:1f.3: enabled 1
1587 17:49:35.725321 PCI: 00:1f.4: enabled 1
1588 17:49:35.728476 PCI: 00:1f.5: enabled 1
1589 17:49:35.732157 PCI: 00:1f.6: enabled 0
1590 17:49:35.735223 USB0 port 0: enabled 1
1591 17:49:35.735300 I2C: 01:15: enabled 1
1592 17:49:35.738798 I2C: 02:5d: enabled 1
1593 17:49:35.741825 GENERIC: 0.0: enabled 1
1594 17:49:35.741912 I2C: 03:1a: enabled 1
1595 17:49:35.745022 I2C: 03:38: enabled 1
1596 17:49:35.748689 I2C: 03:39: enabled 1
1597 17:49:35.748801 I2C: 03:3a: enabled 1
1598 17:49:35.752041 I2C: 03:3b: enabled 1
1599 17:49:35.755052 PCI: 00:00.0: enabled 1
1600 17:49:35.755140 SPI: 00: enabled 1
1601 17:49:35.758689 SPI: 01: enabled 1
1602 17:49:35.761563 PNP: 0c09.0: enabled 1
1603 17:49:35.761668 USB2 port 0: enabled 1
1604 17:49:35.765222 USB2 port 1: enabled 1
1605 17:49:35.768272 USB2 port 2: enabled 0
1606 17:49:35.771870 USB2 port 3: enabled 0
1607 17:49:35.771988 USB2 port 5: enabled 0
1608 17:49:35.774750 USB2 port 6: enabled 1
1609 17:49:35.778277 USB2 port 9: enabled 1
1610 17:49:35.778386 USB3 port 0: enabled 1
1611 17:49:35.781487 USB3 port 1: enabled 1
1612 17:49:35.784689 USB3 port 2: enabled 1
1613 17:49:35.788386 USB3 port 3: enabled 1
1614 17:49:35.788463 USB3 port 4: enabled 0
1615 17:49:35.791745 APIC: 04: enabled 1
1616 17:49:35.791829 APIC: 06: enabled 1
1617 17:49:35.794806 APIC: 01: enabled 1
1618 17:49:35.797950 APIC: 05: enabled 1
1619 17:49:35.798052 APIC: 07: enabled 1
1620 17:49:35.801647 APIC: 02: enabled 1
1621 17:49:35.804731 APIC: 03: enabled 1
1622 17:49:35.804850 PCI: 00:08.0: enabled 1
1623 17:49:35.807728 PCI: 00:14.2: enabled 1
1624 17:49:35.811492 PCI: 01:00.0: enabled 1
1625 17:49:35.814674 Disabling ACPI via APMC:
1626 17:49:35.817772 done.
1627 17:49:35.821524 FMAP: area RW_ELOG found @ af0000 (16384 bytes)
1628 17:49:35.824578 ELOG: NV offset 0xaf0000 size 0x4000
1629 17:49:35.831502 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
1630 17:49:35.838717 ELOG: Event(17) added with size 13 at 2023-10-09 17:49:35 UTC
1631 17:49:35.845275 ELOG: Event(92) added with size 9 at 2023-10-09 17:49:35 UTC
1632 17:49:35.852164 ELOG: Event(93) added with size 9 at 2023-10-09 17:49:35 UTC
1633 17:49:35.858115 ELOG: Event(9A) added with size 9 at 2023-10-09 17:49:35 UTC
1634 17:49:35.864882 ELOG: Event(9E) added with size 10 at 2023-10-09 17:49:35 UTC
1635 17:49:35.871847 ELOG: Event(9F) added with size 14 at 2023-10-09 17:49:35 UTC
1636 17:49:35.874822 BS: BS_DEV_INIT times (ms): entry 0 run 28 exit 6
1637 17:49:35.882312 ELOG: Event(A1) added with size 10 at 2023-10-09 17:49:35 UTC
1638 17:49:35.891944 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
1639 17:49:35.898203 ELOG: Event(A0) added with size 9 at 2023-10-09 17:49:35 UTC
1640 17:49:35.902075 elog_add_boot_reason: Logged dev mode boot
1641 17:49:35.905269 Finalize devices...
1642 17:49:35.905413 PCI: 00:17.0 final
1643 17:49:35.908446 Devices finalized
1644 17:49:35.911492 FMAP: area RW_NVRAM found @ afa000 (24576 bytes)
1645 17:49:35.918198 BS: BS_POST_DEVICE times (ms): entry 1 run 0 exit 0
1646 17:49:35.921856 ME: HFSTS1 : 0x90000245
1647 17:49:35.925047 ME: HFSTS2 : 0x3B850126
1648 17:49:35.931481 ME: HFSTS3 : 0x00000020
1649 17:49:35.934622 ME: HFSTS4 : 0x00004800
1650 17:49:35.938382 ME: HFSTS5 : 0x00000000
1651 17:49:35.941667 ME: HFSTS6 : 0x40400006
1652 17:49:35.944882 ME: Manufacturing Mode : NO
1653 17:49:35.948025 ME: FW Partition Table : OK
1654 17:49:35.951140 ME: Bringup Loader Failure : NO
1655 17:49:35.954564 ME: Firmware Init Complete : YES
1656 17:49:35.958207 ME: Boot Options Present : NO
1657 17:49:35.961252 ME: Update In Progress : NO
1658 17:49:35.964470 ME: D0i3 Support : YES
1659 17:49:35.967589 ME: Low Power State Enabled : NO
1660 17:49:35.971256 ME: CPU Replaced : NO
1661 17:49:35.974283 ME: CPU Replacement Valid : YES
1662 17:49:35.977783 ME: Current Working State : 5
1663 17:49:35.981275 ME: Current Operation State : 1
1664 17:49:35.984176 ME: Current Operation Mode : 0
1665 17:49:35.987773 ME: Error Code : 0
1666 17:49:35.991158 ME: CPU Debug Disabled : YES
1667 17:49:35.994066 ME: TXT Support : NO
1668 17:49:36.001123 BS: BS_OS_RESUME_CHECK times (ms): entry 0 run 0 exit 0
1669 17:49:36.007514 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1670 17:49:36.007611 CBFS @ c08000 size 3f8000
1671 17:49:36.014345 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1672 17:49:36.017487 CBFS: Locating 'fallback/dsdt.aml'
1673 17:49:36.023862 CBFS: Found @ offset 10bb80 size 3fa5
1674 17:49:36.027548 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1675 17:49:36.030829 CBFS @ c08000 size 3f8000
1676 17:49:36.037076 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1677 17:49:36.040683 CBFS: Locating 'fallback/slic'
1678 17:49:36.043915 CBFS: 'fallback/slic' not found.
1679 17:49:36.047075 ACPI: Writing ACPI tables at 99b3e000.
1680 17:49:36.050233 ACPI: * FACS
1681 17:49:36.050315 ACPI: * DSDT
1682 17:49:36.053969 Ramoops buffer: 0x100000@0x99a3d000.
1683 17:49:36.060729 FMAP: area RO_VPD found @ c00000 (16384 bytes)
1684 17:49:36.063619 FMAP: area RW_VPD found @ af8000 (8192 bytes)
1685 17:49:36.067112 Google Chrome EC: version:
1686 17:49:36.070188 ro: helios_v2.0.2659-56403530b
1687 17:49:36.073447 rw: helios_v2.0.2849-c41de27e7d
1688 17:49:36.077213 running image: 1
1689 17:49:36.080396 ACPI: * FADT
1690 17:49:36.080486 SCI is IRQ9
1691 17:49:36.083416 ACPI: added table 1/32, length now 40
1692 17:49:36.086981 ACPI: * SSDT
1693 17:49:36.090041 Found 1 CPU(s) with 8 core(s) each.
1694 17:49:36.093727 Error: Could not locate 'wifi_sar' in VPD.
1695 17:49:36.096634 Checking CBFS for default SAR values
1696 17:49:36.103731 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1697 17:49:36.106753 CBFS @ c08000 size 3f8000
1698 17:49:36.113722 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1699 17:49:36.116792 CBFS: Locating 'wifi_sar_defaults.hex'
1700 17:49:36.120029 CBFS: Found @ offset 5fac0 size 77
1701 17:49:36.123802 \_SB.PCI0.WFA3: Intel WiFi PCI: 00:14.3
1702 17:49:36.126850 \_SB.PCI0.I2C0.D015: ELAN Touchpad at I2C: 01:15
1703 17:49:36.133152 \_SB.PCI0.I2C1.H05D: Goodix Touchscreen at I2C: 02:5d
1704 17:49:36.139998 \_SB.PCI0.I2C4.RT58: Realtek RT5682 at I2C: 03:1a
1705 17:49:36.143173 failed to find key in VPD: dsm_calib_r0_0
1706 17:49:36.153363 Failed to get dsm_calib parameters from VPD with key dsm_calib_r0_0 and dsm_calib_temp_0
1707 17:49:36.156605 \_SB.PCI0.I2C4.RTWL: Realtek RT1011 Codec address 038h
1708 17:49:36.159705 failed to find key in VPD: dsm_calib_r0_1
1709 17:49:36.169604 Failed to get dsm_calib parameters from VPD with key dsm_calib_r0_1 and dsm_calib_temp_0
1710 17:49:36.176551 \_SB.PCI0.I2C4.RTWR: Realtek RT1011 Codec address 039h
1711 17:49:36.179545 failed to find key in VPD: dsm_calib_r0_2
1712 17:49:36.189635 Failed to get dsm_calib parameters from VPD with key dsm_calib_r0_2 and dsm_calib_temp_0
1713 17:49:36.192589 \_SB.PCI0.I2C4.RTTL: Realtek RT1011 Codec address 03ah
1714 17:49:36.199141 failed to find key in VPD: dsm_calib_r0_3
1715 17:49:36.206348 Failed to get dsm_calib parameters from VPD with key dsm_calib_r0_3 and dsm_calib_temp_0
1716 17:49:36.212364 \_SB.PCI0.I2C4.RTTR: Realtek RT1011 Codec address 03bh
1717 17:49:36.216070 \_SB.PCI0.SPI0.S001: SPI Device at SPI: 00
1718 17:49:36.219464 \_SB.PCI0.SPI1.CRFP: SPI Device at SPI: 01
1719 17:49:36.223340 EC returned error result code 1
1720 17:49:36.226913 EC returned error result code 1
1721 17:49:36.230665 EC returned error result code 1
1722 17:49:36.237442 PS2K: Bad resp from EC. Vivaldi disabled!
1723 17:49:36.240549 \_SB.PCI0.XHCI.RHUB.HS01: Left Type-C Port at USB2 port 0
1724 17:49:36.247572 \_SB.PCI0.XHCI.RHUB.HS02: Right Type-C Port 1 at USB2 port 1
1725 17:49:36.253790 \_SB.PCI0.XHCI.RHUB.HS07: Camera at USB2 port 6
1726 17:49:36.257101 \_SB.PCI0.XHCI.RHUB.HS10: Bluetooth at USB2 port 9
1727 17:49:36.263796 \_SB.PCI0.XHCI.RHUB.SS01: Left Type-C Port at USB3 port 0
1728 17:49:36.270242 \_SB.PCI0.XHCI.RHUB.SS02: Right Type-C Port 1 at USB3 port 1
1729 17:49:36.277330 \_SB.PCI0.XHCI.RHUB.SS03: Left Type-A Port at USB3 port 2
1730 17:49:36.280465 \_SB.PCI0.XHCI.RHUB.SS04: Right Type-A Port 1 at USB3 port 3
1731 17:49:36.283869 ACPI: added table 2/32, length now 44
1732 17:49:36.286808 ACPI: * MCFG
1733 17:49:36.290597 ACPI: added table 3/32, length now 48
1734 17:49:36.293690 ACPI: * TPM2
1735 17:49:36.296843 TPM2 log created at 99a2d000
1736 17:49:36.299996 ACPI: added table 4/32, length now 52
1737 17:49:36.300077 ACPI: * MADT
1738 17:49:36.303576 SCI is IRQ9
1739 17:49:36.306730 ACPI: added table 5/32, length now 56
1740 17:49:36.306810 current = 99b43ac0
1741 17:49:36.310160 ACPI: * DMAR
1742 17:49:36.313803 ACPI: added table 6/32, length now 60
1743 17:49:36.316752 ACPI: * IGD OpRegion
1744 17:49:36.316833 GMA: Found VBT in CBFS
1745 17:49:36.319830 GMA: Found valid VBT in CBFS
1746 17:49:36.323428 ACPI: added table 7/32, length now 64
1747 17:49:36.326409 ACPI: * HPET
1748 17:49:36.329763 ACPI: added table 8/32, length now 68
1749 17:49:36.329844 ACPI: done.
1750 17:49:36.333618 ACPI tables: 31744 bytes.
1751 17:49:36.336787 smbios_write_tables: 99a2c000
1752 17:49:36.340358 EC returned error result code 3
1753 17:49:36.343542 Couldn't obtain OEM name from CBI
1754 17:49:36.346723 Create SMBIOS type 17
1755 17:49:36.350075 PCI: 00:00.0 (Intel Cannonlake)
1756 17:49:36.353715 PCI: 00:14.3 (Intel WiFi)
1757 17:49:36.356792 SMBIOS tables: 939 bytes.
1758 17:49:36.360055 Writing table forward entry at 0x00000500
1759 17:49:36.366944 Wrote coreboot table at: 00000500, 0x10 bytes, checksum 4628
1760 17:49:36.370064 Writing coreboot table at 0x99b62000
1761 17:49:36.376420 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1762 17:49:36.379603 1. 0000000000001000-000000000009ffff: RAM
1763 17:49:36.383404 2. 00000000000a0000-00000000000fffff: RESERVED
1764 17:49:36.389590 3. 0000000000100000-0000000099a2bfff: RAM
1765 17:49:36.393251 4. 0000000099a2c000-0000000099baffff: CONFIGURATION TABLES
1766 17:49:36.399429 5. 0000000099bb0000-0000000099c0afff: RAMSTAGE
1767 17:49:36.406296 6. 0000000099c0b000-0000000099ffffff: CONFIGURATION TABLES
1768 17:49:36.409384 7. 000000009a000000-000000009f7fffff: RESERVED
1769 17:49:36.416129 8. 00000000e0000000-00000000efffffff: RESERVED
1770 17:49:36.419570 9. 00000000fc000000-00000000fc000fff: RESERVED
1771 17:49:36.423149 10. 00000000fe000000-00000000fe00ffff: RESERVED
1772 17:49:36.429560 11. 00000000fed10000-00000000fed17fff: RESERVED
1773 17:49:36.433012 12. 00000000fed80000-00000000fed83fff: RESERVED
1774 17:49:36.439441 13. 00000000fed90000-00000000fed91fff: RESERVED
1775 17:49:36.442377 14. 00000000feda0000-00000000feda1fff: RESERVED
1776 17:49:36.449145 15. 0000000100000000-000000045e7fffff: RAM
1777 17:49:36.452397 Graphics framebuffer located at 0xc0000000
1778 17:49:36.456246 Passing 5 GPIOs to payload:
1779 17:49:36.459470 NAME | PORT | POLARITY | VALUE
1780 17:49:36.465710 write protect | undefined | high | low
1781 17:49:36.469344 lid | undefined | high | high
1782 17:49:36.475841 power | undefined | high | low
1783 17:49:36.482322 oprom | undefined | high | low
1784 17:49:36.485924 EC in RW | 0x000000cb | high | low
1785 17:49:36.488969 Board ID: 4
1786 17:49:36.492533 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1787 17:49:36.495872 CBFS @ c08000 size 3f8000
1788 17:49:36.502189 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1789 17:49:36.508974 Wrote coreboot table at: 99b62000, 0x5bc bytes, checksum 6baa
1790 17:49:36.509093 coreboot table: 1492 bytes.
1791 17:49:36.512497 IMD ROOT 0. 99fff000 00001000
1792 17:49:36.515645 IMD SMALL 1. 99ffe000 00001000
1793 17:49:36.518795 FSP MEMORY 2. 99c4e000 003b0000
1794 17:49:36.521915 CONSOLE 3. 99c2e000 00020000
1795 17:49:36.525530 FMAP 4. 99c2d000 0000054e
1796 17:49:36.528995 TIME STAMP 5. 99c2c000 00000910
1797 17:49:36.531860 VBOOT WORK 6. 99c18000 00014000
1798 17:49:36.535632 MRC DATA 7. 99c16000 00001958
1799 17:49:36.538339 ROMSTG STCK 8. 99c15000 00001000
1800 17:49:36.541823 AFTER CAR 9. 99c0b000 0000a000
1801 17:49:36.545265 RAMSTAGE 10. 99baf000 0005c000
1802 17:49:36.551635 REFCODE 11. 99b7a000 00035000
1803 17:49:36.555317 SMM BACKUP 12. 99b6a000 00010000
1804 17:49:36.558453 COREBOOT 13. 99b62000 00008000
1805 17:49:36.561631 ACPI 14. 99b3e000 00024000
1806 17:49:36.564841 ACPI GNVS 15. 99b3d000 00001000
1807 17:49:36.568088 RAMOOPS 16. 99a3d000 00100000
1808 17:49:36.571332 TPM2 TCGLOG17. 99a2d000 00010000
1809 17:49:36.575128 SMBIOS 18. 99a2c000 00000800
1810 17:49:36.575219 IMD small region:
1811 17:49:36.578386 IMD ROOT 0. 99ffec00 00000400
1812 17:49:36.581574 FSP RUNTIME 1. 99ffebe0 00000004
1813 17:49:36.584665 EC HOSTEVENT 2. 99ffebc0 00000008
1814 17:49:36.588287 POWER STATE 3. 99ffeb80 00000040
1815 17:49:36.591540 ROMSTAGE 4. 99ffeb60 00000004
1816 17:49:36.598257 MEM INFO 5. 99ffe9a0 000001b9
1817 17:49:36.601443 VPD 6. 99ffe920 0000006c
1818 17:49:36.601523 MTRR: Physical address space:
1819 17:49:36.608177 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
1820 17:49:36.614701 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
1821 17:49:36.621593 0x00000000000c0000 - 0x000000009b000000 size 0x9af40000 type 6
1822 17:49:36.627934 0x000000009b000000 - 0x00000000c0000000 size 0x25000000 type 0
1823 17:49:36.634356 0x00000000c0000000 - 0x00000000d0000000 size 0x10000000 type 1
1824 17:49:36.641260 0x00000000d0000000 - 0x0000000100000000 size 0x30000000 type 0
1825 17:49:36.647889 0x0000000100000000 - 0x000000045e800000 size 0x35e800000 type 6
1826 17:49:36.650752 MTRR: Fixed MSR 0x250 0x0606060606060606
1827 17:49:36.654296 MTRR: Fixed MSR 0x258 0x0606060606060606
1828 17:49:36.657733 MTRR: Fixed MSR 0x259 0x0000000000000000
1829 17:49:36.664110 MTRR: Fixed MSR 0x268 0x0606060606060606
1830 17:49:36.667277 MTRR: Fixed MSR 0x269 0x0606060606060606
1831 17:49:36.670989 MTRR: Fixed MSR 0x26a 0x0606060606060606
1832 17:49:36.674245 MTRR: Fixed MSR 0x26b 0x0606060606060606
1833 17:49:36.681188 MTRR: Fixed MSR 0x26c 0x0606060606060606
1834 17:49:36.684393 MTRR: Fixed MSR 0x26d 0x0606060606060606
1835 17:49:36.687711 MTRR: Fixed MSR 0x26e 0x0606060606060606
1836 17:49:36.690840 MTRR: Fixed MSR 0x26f 0x0606060606060606
1837 17:49:36.694661 call enable_fixed_mtrr()
1838 17:49:36.697809 CPU physical address size: 39 bits
1839 17:49:36.704441 MTRR: default type WB/UC MTRR counts: 6/8.
1840 17:49:36.707631 MTRR: WB selected as default type.
1841 17:49:36.714411 MTRR: 0 base 0x000000009b000000 mask 0x0000007fff000000 type 0
1842 17:49:36.717483 MTRR: 1 base 0x000000009c000000 mask 0x0000007ffc000000 type 0
1843 17:49:36.723976 MTRR: 2 base 0x00000000a0000000 mask 0x0000007fe0000000 type 0
1844 17:49:36.730701 MTRR: 3 base 0x00000000c0000000 mask 0x0000007ff0000000 type 1
1845 17:49:36.737559 MTRR: 4 base 0x00000000d0000000 mask 0x0000007ff0000000 type 0
1846 17:49:36.744356 MTRR: 5 base 0x00000000e0000000 mask 0x0000007fe0000000 type 0
1847 17:49:36.747537 MTRR: Fixed MSR 0x250 0x0606060606060606
1848 17:49:36.754261 MTRR: Fixed MSR 0x258 0x0606060606060606
1849 17:49:36.757405 MTRR: Fixed MSR 0x259 0x0000000000000000
1850 17:49:36.760937 MTRR: Fixed MSR 0x268 0x0606060606060606
1851 17:49:36.763981 MTRR: Fixed MSR 0x269 0x0606060606060606
1852 17:49:36.770941 MTRR: Fixed MSR 0x26a 0x0606060606060606
1853 17:49:36.774056 MTRR: Fixed MSR 0x26b 0x0606060606060606
1854 17:49:36.777182 MTRR: Fixed MSR 0x26c 0x0606060606060606
1855 17:49:36.780468 MTRR: Fixed MSR 0x26d 0x0606060606060606
1856 17:49:36.787561 MTRR: Fixed MSR 0x26e 0x0606060606060606
1857 17:49:36.790718 MTRR: Fixed MSR 0x26f 0x0606060606060606
1858 17:49:36.791139
1859 17:49:36.791531 MTRR check
1860 17:49:36.793891 Fixed MTRRs : Enabled
1861 17:49:36.797069 Variable MTRRs: Enabled
1862 17:49:36.797703
1863 17:49:36.800741 call enable_fixed_mtrr()
1864 17:49:36.803839 BS: BS_WRITE_TABLES times (ms): entry 0 run 9 exit 2
1865 17:49:36.806903 CPU physical address size: 39 bits
1866 17:49:36.814368 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1867 17:49:36.817462 MTRR: Fixed MSR 0x250 0x0606060606060606
1868 17:49:36.820685 MTRR: Fixed MSR 0x258 0x0606060606060606
1869 17:49:36.827499 MTRR: Fixed MSR 0x259 0x0000000000000000
1870 17:49:36.830490 MTRR: Fixed MSR 0x268 0x0606060606060606
1871 17:49:36.834054 MTRR: Fixed MSR 0x269 0x0606060606060606
1872 17:49:36.836935 MTRR: Fixed MSR 0x26a 0x0606060606060606
1873 17:49:36.843732 MTRR: Fixed MSR 0x26b 0x0606060606060606
1874 17:49:36.847387 MTRR: Fixed MSR 0x26c 0x0606060606060606
1875 17:49:36.850484 MTRR: Fixed MSR 0x26d 0x0606060606060606
1876 17:49:36.853637 MTRR: Fixed MSR 0x26e 0x0606060606060606
1877 17:49:36.857368 MTRR: Fixed MSR 0x26f 0x0606060606060606
1878 17:49:36.863284 MTRR: Fixed MSR 0x250 0x0606060606060606
1879 17:49:36.866896 call enable_fixed_mtrr()
1880 17:49:36.870021 MTRR: Fixed MSR 0x258 0x0606060606060606
1881 17:49:36.873666 MTRR: Fixed MSR 0x259 0x0000000000000000
1882 17:49:36.876608 MTRR: Fixed MSR 0x268 0x0606060606060606
1883 17:49:36.883320 MTRR: Fixed MSR 0x269 0x0606060606060606
1884 17:49:36.886513 MTRR: Fixed MSR 0x26a 0x0606060606060606
1885 17:49:36.890485 MTRR: Fixed MSR 0x26b 0x0606060606060606
1886 17:49:36.893526 MTRR: Fixed MSR 0x26c 0x0606060606060606
1887 17:49:36.899961 MTRR: Fixed MSR 0x26d 0x0606060606060606
1888 17:49:36.903053 MTRR: Fixed MSR 0x26e 0x0606060606060606
1889 17:49:36.906750 MTRR: Fixed MSR 0x26f 0x0606060606060606
1890 17:49:36.909857 CPU physical address size: 39 bits
1891 17:49:36.912911 call enable_fixed_mtrr()
1892 17:49:36.916653 MTRR: Fixed MSR 0x250 0x0606060606060606
1893 17:49:36.919742 MTRR: Fixed MSR 0x258 0x0606060606060606
1894 17:49:36.926299 MTRR: Fixed MSR 0x259 0x0000000000000000
1895 17:49:36.929676 MTRR: Fixed MSR 0x268 0x0606060606060606
1896 17:49:36.932702 MTRR: Fixed MSR 0x269 0x0606060606060606
1897 17:49:36.936509 MTRR: Fixed MSR 0x26a 0x0606060606060606
1898 17:49:36.943298 MTRR: Fixed MSR 0x26b 0x0606060606060606
1899 17:49:36.946018 MTRR: Fixed MSR 0x26c 0x0606060606060606
1900 17:49:36.949670 MTRR: Fixed MSR 0x26d 0x0606060606060606
1901 17:49:36.952586 MTRR: Fixed MSR 0x26e 0x0606060606060606
1902 17:49:36.959486 MTRR: Fixed MSR 0x26f 0x0606060606060606
1903 17:49:36.962618 MTRR: Fixed MSR 0x250 0x0606060606060606
1904 17:49:36.966257 MTRR: Fixed MSR 0x258 0x0606060606060606
1905 17:49:36.969617 MTRR: Fixed MSR 0x259 0x0000000000000000
1906 17:49:36.976416 MTRR: Fixed MSR 0x268 0x0606060606060606
1907 17:49:36.979538 MTRR: Fixed MSR 0x269 0x0606060606060606
1908 17:49:36.982414 MTRR: Fixed MSR 0x26a 0x0606060606060606
1909 17:49:36.985936 MTRR: Fixed MSR 0x26b 0x0606060606060606
1910 17:49:36.992812 MTRR: Fixed MSR 0x26c 0x0606060606060606
1911 17:49:36.995690 MTRR: Fixed MSR 0x26d 0x0606060606060606
1912 17:49:36.999550 MTRR: Fixed MSR 0x26e 0x0606060606060606
1913 17:49:37.002594 MTRR: Fixed MSR 0x26f 0x0606060606060606
1914 17:49:37.006358 call enable_fixed_mtrr()
1915 17:49:37.009555 call enable_fixed_mtrr()
1916 17:49:37.012621 CPU physical address size: 39 bits
1917 17:49:37.015919 CPU physical address size: 39 bits
1918 17:49:37.019445 MTRR: Fixed MSR 0x250 0x0606060606060606
1919 17:49:37.025767 MTRR: Fixed MSR 0x250 0x0606060606060606
1920 17:49:37.029350 MTRR: Fixed MSR 0x258 0x0606060606060606
1921 17:49:37.032472 MTRR: Fixed MSR 0x259 0x0000000000000000
1922 17:49:37.035594 MTRR: Fixed MSR 0x268 0x0606060606060606
1923 17:49:37.039390 MTRR: Fixed MSR 0x269 0x0606060606060606
1924 17:49:37.045549 MTRR: Fixed MSR 0x26a 0x0606060606060606
1925 17:49:37.049441 MTRR: Fixed MSR 0x26b 0x0606060606060606
1926 17:49:37.052156 MTRR: Fixed MSR 0x26c 0x0606060606060606
1927 17:49:37.055732 MTRR: Fixed MSR 0x26d 0x0606060606060606
1928 17:49:37.062281 MTRR: Fixed MSR 0x26e 0x0606060606060606
1929 17:49:37.065453 MTRR: Fixed MSR 0x26f 0x0606060606060606
1930 17:49:37.069287 MTRR: Fixed MSR 0x258 0x0606060606060606
1931 17:49:37.072273 MTRR: Fixed MSR 0x259 0x0000000000000000
1932 17:49:37.079072 MTRR: Fixed MSR 0x268 0x0606060606060606
1933 17:49:37.082094 MTRR: Fixed MSR 0x269 0x0606060606060606
1934 17:49:37.085875 MTRR: Fixed MSR 0x26a 0x0606060606060606
1935 17:49:37.088889 MTRR: Fixed MSR 0x26b 0x0606060606060606
1936 17:49:37.095284 MTRR: Fixed MSR 0x26c 0x0606060606060606
1937 17:49:37.099064 MTRR: Fixed MSR 0x26d 0x0606060606060606
1938 17:49:37.102105 MTRR: Fixed MSR 0x26e 0x0606060606060606
1939 17:49:37.105361 MTRR: Fixed MSR 0x26f 0x0606060606060606
1940 17:49:37.108525 call enable_fixed_mtrr()
1941 17:49:37.111729 call enable_fixed_mtrr()
1942 17:49:37.115293 CPU physical address size: 39 bits
1943 17:49:37.118329 CPU physical address size: 39 bits
1944 17:49:37.122128 CPU physical address size: 39 bits
1945 17:49:37.125304 CBFS @ c08000 size 3f8000
1946 17:49:37.131666 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1947 17:49:37.135420 CBFS: Locating 'fallback/payload'
1948 17:49:37.138415 CBFS: Found @ offset 1c96c0 size 3f798
1949 17:49:37.144667 Checking segment from ROM address 0xffdd16f8
1950 17:49:37.148384 Checking segment from ROM address 0xffdd1714
1951 17:49:37.151583 Loading segment from ROM address 0xffdd16f8
1952 17:49:37.154704 code (compression=0)
1953 17:49:37.165032 New segment dstaddr 0x30000000 memsize 0x657430 srcaddr 0xffdd1730 filesize 0x3f760
1954 17:49:37.171558 Loading Segment: addr: 0x30000000 memsz: 0x0000000000657430 filesz: 0x000000000003f760
1955 17:49:37.174426 it's not compressed!
1956 17:49:37.266348 [ 0x30000000, 3003f760, 0x30657430) <- ffdd1730
1957 17:49:37.273195 Clearing Segment: addr: 0x000000003003f760 memsz: 0x0000000000617cd0
1958 17:49:37.276393 Loading segment from ROM address 0xffdd1714
1959 17:49:37.279573 Entry Point 0x30000000
1960 17:49:37.283060 Loaded segments
1961 17:49:37.288426 Finalizing chipset.
1962 17:49:37.291558 Finalizing SMM.
1963 17:49:37.295291 BS: BS_PAYLOAD_LOAD times (ms): entry 0 run 89 exit 5
1964 17:49:37.298252 mp_park_aps done after 0 msecs.
1965 17:49:37.304978 Jumping to boot code at 30000000(99b62000)
1966 17:49:37.311375 CPU0: stack: 99bf9000 - 99bfa000, lowest used address 99bf99d8, stack used: 1576 bytes
1967 17:49:37.311806
1968 17:49:37.312139
1969 17:49:37.312449
1970 17:49:37.314709 Starting depthcharge on Helios...
1971 17:49:37.315127
1972 17:49:37.316260 end: 2.2.3 depthcharge-start (duration 00:00:13) [common]
1973 17:49:37.316763 start: 2.2.4 bootloader-commands (timeout 00:04:42) [common]
1974 17:49:37.317252 Setting prompt string to ['hatch:']
1975 17:49:37.317737 bootloader-commands: Wait for prompt ['hatch:'] (timeout 00:04:42)
1976 17:49:37.324741 WARNING: can't convert coreboot GPIOs, 'lid' won't be resampled at runtime!
1977 17:49:37.325163
1978 17:49:37.331396 WARNING: can't convert coreboot GPIOs, 'power' won't be resampled at runtime!
1979 17:49:37.332049
1980 17:49:37.337742 board_setup: Info: eMMC controller not present; skipping
1981 17:49:37.338241
1982 17:49:37.340998 New NVMe Controller 0x30053ac0 @ 00:1d:00
1983 17:49:37.341564
1984 17:49:37.347618 board_setup: Info: SDHCI controller not present; skipping
1985 17:49:37.348175
1986 17:49:37.354116 vboot_create_vbsd: creating legacy VbSharedDataHeader structure
1987 17:49:37.354757
1988 17:49:37.355184 Wipe memory regions:
1989 17:49:37.355599
1990 17:49:37.357457 [0x00000000001000, 0x000000000a0000)
1991 17:49:37.361095
1992 17:49:37.364290 [0x00000000100000, 0x00000030000000)
1993 17:49:37.426979
1994 17:49:37.430495 [0x00000030657430, 0x00000099a2c000)
1995 17:49:37.567142
1996 17:49:37.570336 [0x00000100000000, 0x0000045e800000)
1997 17:49:38.953446
1998 17:49:38.954066 R8152: Initializing
1999 17:49:38.954456
2000 17:49:38.956932 Version 9 (ocp_data = 6010)
2001 17:49:38.961515
2002 17:49:38.961984 R8152: Done initializing
2003 17:49:38.962359
2004 17:49:38.964498 Adding net device
2005 17:49:39.574244
2006 17:49:39.574850 R8152: Initializing
2007 17:49:39.575246
2008 17:49:39.577453 Version 6 (ocp_data = 5c30)
2009 17:49:39.577927
2010 17:49:39.581004 R8152: Done initializing
2011 17:49:39.581568
2012 17:49:39.584057 net_add_device: Attemp to include the same device
2013 17:49:39.587184
2014 17:49:39.594445 [firmware-hatch-12672.B-collabora] Jul 21 2021 08:27:58
2015 17:49:39.595095
2016 17:49:39.595577
2017 17:49:39.596078
2018 17:49:39.597248 Setting prompt string to ['hatch:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2020 17:49:39.698778 hatch: tftpboot 192.168.201.1 11712709/tftp-deploy-uer_z78u/kernel/bzImage 11712709/tftp-deploy-uer_z78u/kernel/cmdline 11712709/tftp-deploy-uer_z78u/ramdisk/ramdisk.cpio.gz
2021 17:49:39.699409 Setting prompt string to ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2022 17:49:39.699829 bootloader-commands: Wait for prompt ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:40)
2023 17:49:39.704210 tftpboot 192.168.201.1 11712709/tftp-deploy-uer_z78u/kernel/bzImloy-uer_z78u/kernel/cmdline 11712709/tftp-deploy-uer_z78u/ramdisk/ramdisk.cpio.gz
2024 17:49:39.704650
2025 17:49:39.704979 Waiting for link
2026 17:49:39.905462
2027 17:49:39.905961 done.
2028 17:49:39.906615
2029 17:49:39.907007 MAC: 00:24:32:50:1a:5f
2030 17:49:39.907571
2031 17:49:39.908637 Sending DHCP discover... done.
2032 17:49:39.909294
2033 17:49:39.911712 Waiting for reply... done.
2034 17:49:39.912524
2035 17:49:39.914766 Sending DHCP request... done.
2036 17:49:39.915449
2037 17:49:39.941007 Waiting for reply... done.
2038 17:49:39.941440
2039 17:49:39.941833 My ip is 192.168.201.21
2040 17:49:39.942154
2041 17:49:39.944423 The DHCP server ip is 192.168.201.1
2042 17:49:39.947415
2043 17:49:39.951087 TFTP server IP predefined by user: 192.168.201.1
2044 17:49:39.951511
2045 17:49:39.957465 Bootfile predefined by user: 11712709/tftp-deploy-uer_z78u/kernel/bzImage
2046 17:49:39.958064
2047 17:49:39.960529 Sending tftp read request... done.
2048 17:49:39.961001
2049 17:49:39.970046 Waiting for the transfer...
2050 17:49:39.970468
2051 17:49:40.611214 00000000 ################################################################
2052 17:49:40.611846
2053 17:49:41.205173 00080000 ################################################################
2054 17:49:41.205685
2055 17:49:41.795691 00100000 ################################################################
2056 17:49:41.796201
2057 17:49:42.373769 00180000 ################################################################
2058 17:49:42.374018
2059 17:49:42.905505 00200000 ################################################################
2060 17:49:42.905653
2061 17:49:43.438011 00280000 ################################################################
2062 17:49:43.438183
2063 17:49:43.957274 00300000 ################################################################
2064 17:49:43.957424
2065 17:49:44.478787 00380000 ################################################################
2066 17:49:44.478920
2067 17:49:45.047403 00400000 ################################################################
2068 17:49:45.047541
2069 17:49:45.657102 00480000 ################################################################
2070 17:49:45.657620
2071 17:49:46.226942 00500000 ################################################################
2072 17:49:46.227459
2073 17:49:46.811898 00580000 ################################################################
2074 17:49:46.812063
2075 17:49:47.407162 00600000 ################################################################
2076 17:49:47.407311
2077 17:49:48.028057 00680000 ################################################################
2078 17:49:48.028571
2079 17:49:48.591166 00700000 ################################################################
2080 17:49:48.591312
2081 17:49:49.194743 00780000 ################################################################
2082 17:49:49.194903
2083 17:49:49.303085 00800000 ############# done.
2084 17:49:49.303228
2085 17:49:49.306026 The bootfile was 8490896 bytes long.
2086 17:49:49.306128
2087 17:49:49.309642 Sending tftp read request... done.
2088 17:49:49.309786
2089 17:49:49.312686 Waiting for the transfer...
2090 17:49:49.312794
2091 17:49:49.893487 00000000 ################################################################
2092 17:49:49.893655
2093 17:49:50.515036 00080000 ################################################################
2094 17:49:50.515653
2095 17:49:51.129104 00100000 ################################################################
2096 17:49:51.129280
2097 17:49:51.768077 00180000 ################################################################
2098 17:49:51.768226
2099 17:49:52.321019 00200000 ################################################################
2100 17:49:52.321772
2101 17:49:52.893779 00280000 ################################################################
2102 17:49:52.893920
2103 17:49:53.446310 00300000 ################################################################
2104 17:49:53.446455
2105 17:49:54.008863 00380000 ################################################################
2106 17:49:54.009037
2107 17:49:54.564879 00400000 ################################################################
2108 17:49:54.565045
2109 17:49:55.112574 00480000 ################################################################
2110 17:49:55.112722
2111 17:49:55.680349 00500000 ################################################################
2112 17:49:55.680492
2113 17:49:56.213620 00580000 ################################################################
2114 17:49:56.213765
2115 17:49:56.745931 00600000 ################################################################
2116 17:49:56.746091
2117 17:49:57.294186 00680000 ################################################################
2118 17:49:57.294333
2119 17:49:57.885634 00700000 ################################################################
2120 17:49:57.885779
2121 17:49:58.437700 00780000 ################################################################
2122 17:49:58.437860
2123 17:49:58.955967 00800000 ##################################################### done.
2124 17:49:58.956478
2125 17:49:58.959893 Sending tftp read request... done.
2126 17:49:58.960366
2127 17:49:58.962922 Waiting for the transfer...
2128 17:49:58.963374
2129 17:49:58.966097 00000000 # done.
2130 17:49:58.966550
2131 17:49:58.973125 Command line loaded dynamically from TFTP file: 11712709/tftp-deploy-uer_z78u/kernel/cmdline
2132 17:49:58.973542
2133 17:49:58.992609 The command line is: earlyprintk=uart8250,mmio32,0xfedc6000,115200n8 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
2134 17:49:58.993047
2135 17:49:58.998999 ec_init(0): CrosEC protocol v3 supported (256, 256)
2136 17:49:59.003898
2137 17:49:59.007588 Shutting down all USB controllers.
2138 17:49:59.007999
2139 17:49:59.008326 Removing current net device
2140 17:49:59.014978
2141 17:49:59.015402 Finalizing coreboot
2142 17:49:59.015726
2143 17:49:59.021451 Exiting depthcharge with code 4 at timestamp: 29063544
2144 17:49:59.021865
2145 17:49:59.022190
2146 17:49:59.022491 Starting kernel ...
2147 17:49:59.022871
2148 17:49:59.023162
2149 17:49:59.024383 end: 2.2.4 bootloader-commands (duration 00:00:22) [common]
2150 17:49:59.025038 start: 2.2.5 auto-login-action (timeout 00:04:20) [common]
2151 17:49:59.025426 Setting prompt string to ['Linux version [0-9]']
2152 17:49:59.025768 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2153 17:49:59.026110 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
2155 17:54:19.025329 end: 2.2.5 auto-login-action (duration 00:04:20) [common]
2157 17:54:19.025544 depthcharge-retry failed: 1 of 1 attempts. 'auto-login-action timed out after 260 seconds'
2159 17:54:19.025702 end: 2.2 depthcharge-retry (duration 00:05:00) [common]
2162 17:54:19.025952 end: 2 depthcharge-action (duration 00:05:00) [common]
2164 17:54:19.026171 Cleaning after the job
2165 17:54:19.026264 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11712709/tftp-deploy-uer_z78u/ramdisk
2166 17:54:19.027750 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11712709/tftp-deploy-uer_z78u/kernel
2167 17:54:19.029090 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11712709/tftp-deploy-uer_z78u/modules
2168 17:54:19.029597 start: 5.1 power-off (timeout 00:00:30) [common]
2169 17:54:19.029758 Calling: 'pduclient' '--daemon=localhost' '--hostname=asus-C436FA-Flip-hatch-cbg-0' '--port=1' '--command=off'
2170 17:54:19.106798 >> Command sent successfully.
2171 17:54:19.109258 Returned 0 in 0 seconds
2172 17:54:19.209661 end: 5.1 power-off (duration 00:00:00) [common]
2174 17:54:19.209999 start: 5.2 read-feedback (timeout 00:10:00) [common]
2175 17:54:19.210270 Listened to connection for namespace 'common' for up to 1s
2177 17:54:19.210643 Listened to connection for namespace 'common' for up to 1s
2178 17:54:20.210626 Finalising connection for namespace 'common'
2179 17:54:20.210811 Disconnecting from shell: Finalise
2180 17:54:20.210892
2181 17:54:20.311213 end: 5.2 read-feedback (duration 00:00:01) [common]
2182 17:54:20.311371 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11712709
2183 17:54:20.329797 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11712709
2184 17:54:20.329990 JobError: Your job cannot terminate cleanly.