[Enter `^Ec?' for help] coreboot-v1.9308_26_0.0.22-18292-gb7f2ee574a Tue Apr 26 08:50:11 UTC 2022 bootblock starting (log level: 8)... CPU: Intel(R) Celeron(R) N4500 @ 1.10GHz CPU: ID 906c0, Jasperlake A0, ucode: 2400001f CPU: AES supported, TXT NOT supported, VT supported MCH: device id 4e22 (rev 00) is Jasperlake SKU4-1 PCH: device id 4d87 (rev 01) is Jasperlake Super IGD: device id 4e55 (rev 01) is Jasperlake GT4 VBOOT: Loading verstage. FMAP: Found "FLASH" version 1.1 at 0xc04000. FMAP: base = 0xff000000 size = 0x1000000 #areas = 32 FMAP: area COREBOOT found @ c08000 (4161536 bytes) CBFS: Found 'fallback/verstage' @0xfa740 size 0x155ec coreboot-v1.9308_26_0.0.22-18292-gb7f2ee574a Tue Apr 26 08:50:11 UTC 2022 verstage starting (log level: 8)... Probing TPM: . done! TPM ready after 0 ms Connected to device vid:did:rid of 1ae0:0028:00 Firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_A:0.5.171/cr50_v2.94_mp.164-2fb1dd676c Current CR50_BOARD_CFG = 0x80000001, matches desired = 0x00000001 Initialized TPM device CR50 revision 0 tlcl_send_startup: Startup return code is 0 TPM: setup succeeded src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes) src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0 Chrome EC: UHEPI supported Phase 1 FMAP: area GBB found @ c05000 (12288 bytes) VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7 Recovery requested (1009000e) TPM: Extending digest for VBOOT: boot mode into PCR 0 tlcl_extend: response is 0 TPM: Extending digest for VBOOT: GBB HWID into PCR 1 tlcl_extend: response is 0 FMAP: area COREBOOT found @ c08000 (4161536 bytes) CBFS: Found 'fallback/romstage' @0x80 size 0x1bde4 BS: verstage times (exec / console): total (unknown) / 124 ms coreboot-v1.9308_26_0.0.22-18292-gb7f2ee574a Tue Apr 26 08:50:11 UTC 2022 romstage starting (log level: 8)... VB2:vb2api_ec_sync() In recovery mode, skipping EC sync pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00 gpe0_sts[0]: 00000010 gpe0_en[0]: 00000000 gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000 gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000 gpe0_sts[3]: 00080000 gpe0_en[3]: 00010000 TCO_STS: 0000 0001 GEN_PMCON: d0015038 00002200 GBLRST_CAUSE: 00000000 00000000 prev_sleep_state 5 Boot Count incremented to 7274 FMAP: area COREBOOT found @ c08000 (4161536 bytes) CBFS: Found 'fspm.bin' @0x44fc0 size 0x79000 Chrome EC: UHEPI supported FMAP: area RECOVERY_MRC_CACHE found @ bca000 (65536 bytes) Probing TPM: done! Connected to device vid:did:rid of 1ae0:0028:00 Firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_A:0.5.171/cr50_v2.94_mp.164-2fb1dd676c Initialized TPM device CR50 revision 0 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x100b return code 0 MRC: Hash idx 0x100b comparison successful. MRC cache found, size 5458 bootmode is set to: 2 SPD INDEX = 0 CBFS: Found 'spd.bin' @0x40c40 size 0x600 SPD: module type is LPDDR4X SPD: module part number is MT53E512M32D2NP-046 WT:E SPD: banks 8, ranks 1, rows 16, columns 10, density 16384 Mb SPD: device width 16 bits, bus width 32 bits SPD: module size is 4096 MB (per channel) meminit_channels: DRAM half-populated CBMEM: IMD: root @ 0x76fff000 254 entries. IMD: root @ 0x76ffec00 62 entries. FMAP: area RO_VPD found @ c00000 (16384 bytes) WARNING: RO_VPD is uninitialized or empty. FMAP: area RW_VPD found @ bfc000 (8192 bytes) External stage cache: IMD: root @ 0x7b3ff000 254 entries. IMD: root @ 0x7b3fec00 62 entries. FMAP: area RECOVERY_MRC_CACHE found @ bca000 (65536 bytes) MRC: Checking cached data update for 'RECOVERY_MRC_CACHE'. SF: Detected 00 0000 with sector size 0x1000, total 0x1000000 MRC: 'RECOVERY_MRC_CACHE' does not need update. cse_lite: Skip switching to RW in the recovery path 1 DIMMs found SMM Memory Map SMRAM : 0x7b000000 0x800000 Subregion 0: 0x7b000000 0x200000 Subregion 1: 0x7b200000 0x200000 Subregion 2: 0x7b400000 0x400000 top_of_ram = 0x77000000 MTRR Range: Start=76000000 End=77000000 (Size 1000000) MTRR Range: Start=7b000000 End=7b800000 (Size 800000) MTRR Range: Start=ff000000 End=0 (Size 1000000) CBFS: Found 'fallback/postcar' @0xf5940 size 0x4d9c Decompressing stage fallback/postcar @ 0x76c0dfc0 (36304 bytes) Loading module at 0x76c0e000 with entry 0x76c0e000. filesize: 0x4a50 memsize: 0x8d90 Processing 188 relocs. Offset value of 0x74c0e000 BS: romstage times (exec / console): total (unknown) / 255 ms coreboot-v1.9308_26_0.0.22-18292-gb7f2ee574a Tue Apr 26 08:50:11 UTC 2022 postcar starting (log level: 8)... FMAP: area COREBOOT found @ c08000 (4161536 bytes) CBFS: Found 'fallback/ramstage' @0x20f80 size 0x1f488 Decompressing stage fallback/ramstage @ 0x76ba7fc0 (413104 bytes) Loading module at 0x76ba8000 with entry 0x76ba8000. filesize: 0x4ec20 memsize: 0x64d70 Processing 4805 relocs. Offset value of 0x75da8000 BS: postcar times (exec / console): total (unknown) / 42 ms coreboot-v1.9308_26_0.0.22-18292-gb7f2ee574a Tue Apr 26 08:50:11 UTC 2022 ramstage starting (log level: 8)... Normal boot EC returned error result code 3 FW_CONFIG value is 0x204 GENERIC: 0.0 disabled by fw_config fw_config match found: TS_SOURCE=TS_UNPROVISIONED I2C: 00:10 disabled by fw_config I2C: 00:10 disabled by fw_config fw_config match found: TS_SOURCE=TS_UNPROVISIONED fw_config match found: TS_SOURCE=TS_UNPROVISIONED fw_config match found: TS_SOURCE=TS_UNPROVISIONED fw_config match found: TS_SOURCE=TS_UNPROVISIONED fw_config match found: CAMERA_WFC=CAMERA_UNPROVISIONED I2C: 00:10 disabled by fw_config fw_config match found: CAMERA_VCM=CAMERA_VCM_UNPROVISIONED fw_config match found: AUDIO_CODEC_SOURCE=AUDIO_CODEC_UNPROVISIONED I2C: 00:1a disabled by fw_config I2C: 00:1a disabled by fw_config fw_config match found: AUDIO_AMP=UNPROVISIONED fw_config match found: AUDIO_AMP=UNPROVISIONED GENERIC: 0.0 disabled by fw_config FMAP: area COREBOOT found @ c08000 (4161536 bytes) CBFS: Found 'cpu_microcode_blob.bin' @0x1bf00 size 0x5000 microcode: sig=0x906c0 pf=0x1 revision=0x2400001f microcode: Update skipped, already up-to-date CBFS: Found 'fsps.bin' @0xbefc0 size 0x36906 Detected 2 core, 2 thread CPU. Setting up SMI for CPU IED base = 0x7b400000 IED size = 0x00400000 Will perform SMM setup. CPU: Intel(R) Celeron(R) N4500 @ 1.10GHz. Loading module at 0x00030000 with entry 0x00030000. filesize: 0x170 memsize: 0x170 Processing 16 relocs. Offset value of 0x00030000 Attempting to start 1 APs Waiting for 10ms after sending INIT. Waiting for 1st SIPI to complete...done. AP: slot 1 apic_id 2. Waiting for 2nd SIPI to complete...done. Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1b8 memsize: 0x1b8 Processing 13 relocs. Offset value of 0x00038000 Unable to locate Global NVS SMM Module: stub loaded at 0x00038000. Will call 0x76bc5fe2(0x00000000) Installing permanent SMM handler to 0x7b000000 Loading module at 0x7b010000 with entry 0x7b010a91. filesize: 0xba48 memsize: 0x10b10 Processing 704 relocs. Offset value of 0x7b010000 Loading module at 0x7b008000 with entry 0x7b008000. filesize: 0x1b8 memsize: 0x1b8 Processing 13 relocs. Offset value of 0x7b008000 SMM Module: placing jmp sequence at 0x7b007c00 rel16 0x03fd Unable to locate Global NVS SMM Module: stub loaded at 0x7b008000. Will call 0x7b010a91(0x00000000) Clearing SMI status registers SMI_STS: PM1 PM1_STS: PWRBTN TCO_STS: INTRD_DET GPE0 STD STS: smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b000000, cpu = 0 In relocation handler: CPU 0 New SMBASE=0x7b000000 IEDBASE=0x7b400000 Writing SMRR. base = 0x7b000006, mask=0xff800800 Relocation complete. smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afffc00, cpu = 1 In relocation handler: CPU 1 New SMBASE=0x7afffc00 IEDBASE=0x7b400000 Writing SMRR. base = 0x7b000006, mask=0xff800800 Relocation complete. Initializing CPU #0 CPU: vendor Intel device 906c0 CPU: family 06, model 9c, stepping 00 Clearing out pending MCEs Setting up local APIC... apic_id: 0x00 done. Turbo is available but hidden Turbo is available and visible microcode: Update skipped, already up-to-date CPU #0 initialized Initializing CPU #1 CPU: vendor Intel device 906c0 CPU: family 06, model 9c, stepping 00 Clearing out pending MCEs Setting up local APIC... apic_id: 0x02 done. microcode: Update skipped, already up-to-date CPU #1 initialized bsp_do_flight_plan done after 175 msecs. CPU: frequency set to 2800 MHz Enabling SMIs. BS: BS_DEV_INIT_CHIPS entry times (exec / console): 86 / 288 ms Probing TPM: done! Connected to device vid:did:rid of 1ae0:0028:00 Firmware version: B2-C:0 RO_A:0.0.12/bf248b9d RW_A:0.5.171/cr50_v2.94_mp.164-2fb1dd676c Initialized TPM device CR50 revision 0 CBFS: Found 'vbt.bin' @0x445c0 size 0x4bc Found a VBT of 7680 bytes after decompression WEAK: src/soc/intel/jasperlake/fsp_params.c/mainboard_silicon_init_params called Detected 2 core, 2 thread CPU. Detected 2 core, 2 thread CPU. Display FSP Version Info HOB Reference Code - CPU = 8.7.22.30 uCode Version = 24.0.0.1f TXT ACM version = ff.ff.ff.ffff Reference Code - ME = 8.7.22.30 MEBx version = 0.0.0.0 ME Firmware Version = Consumer SKU Reference Code - PCH = 8.7.22.30 PCH-CRID Status = Disabled PCH-CRID Original Value = ff.ff.ff.ffff PCH-CRID New Value = ff.ff.ff.ffff OPROM - RST - RAID = ff.ff.ff.ffff PCH Hsio Version = 4.0.0.0 Reference Code - SA - System Agent = 8.7.22.30 Reference Code - MRC = 0.0.4.68 SA - PCIe Version = 8.7.22.30 SA-CRID Status = Disabled SA-CRID Original Value = 0.0.0.0 SA-CRID New Value = 0.0.0.0 OPROM - VBIOS = ff.ff.ff.ffff IO Manageability Engine FW Version = ff.ff.ff.ffff PHY Build Version = ff.ff.ff.ffff Thunderbolt(TM) FW Version = ff.ff.ff.ffff System Agent Manageability Engine FW Version = ff.ff.ff.ffff ITSS IRQ Polarities Before: IPC0: 0xffffffff IPC1: 0xffffffff IPC2: 0xffffffff IPC3: 0xffffffff ITSS IRQ Polarities After: IPC0: 0xffffffff IPC1: 0xffffffff IPC2: 0xffffffff IPC3: 0xffffffff pcie_rp_update_dev: Couldn't find PCIe Root Port #8 (originally PCI: 00:1c.7) which was enabled in devicetree, removing. BS: BS_DEV_INIT_CHIPS run times (exec / console): 405 / 156 ms Enumerating buses... Show all devs... Before device enumeration. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:04.0: enabled 1 PCI: 00:05.0: enabled 1 PCI: 00:09.0: enabled 0 PCI: 00:12.6: enabled 0 PCI: 00:14.0: enabled 1 PCI: 00:14.1: enabled 0 PCI: 00:14.2: enabled 0 PCI: 00:14.3: enabled 1 PCI: 00:14.5: enabled 1 PCI: 00:15.0: enabled 1 PCI: 00:15.1: enabled 1 PCI: 00:15.2: enabled 1 PCI: 00:15.3: enabled 1 PCI: 00:16.0: enabled 1 PCI: 00:16.1: enabled 0 PCI: 00:16.4: enabled 0 PCI: 00:16.5: enabled 0 PCI: 00:17.0: enabled 0 PCI: 00:19.0: enabled 1 PCI: 00:19.1: enabled 0 PCI: 00:19.2: enabled 1 PCI: 00:1a.0: enabled 1 PCI: 00:1c.0: enabled 0 PCI: 00:1c.1: enabled 0 PCI: 00:1c.2: enabled 0 PCI: 00:1c.3: enabled 0 PCI: 00:1c.4: enabled 0 PCI: 00:1c.5: enabled 0 PCI: 00:1c.6: enabled 0 PCI: 00:1c.7: enabled 1 PCI: 00:1e.0: enabled 0 PCI: 00:1e.1: enabled 0 PCI: 00:1e.2: enabled 1 PCI: 00:1e.3: enabled 0 PCI: 00:1f.0: enabled 1 PCI: 00:1f.1: enabled 1 PCI: 00:1f.2: enabled 1 PCI: 00:1f.3: enabled 1 PCI: 00:1f.4: enabled 0 PCI: 00:1f.5: enabled 1 PCI: 00:1f.7: enabled 0 GENERIC: 0.0: enabled 1 GENERIC: 0.0: enabled 1 USB0 port 0: enabled 1 GENERIC: 0.0: enabled 1 I2C: 00:2c: enabled 1 I2C: 00:15: enabled 1 GENERIC: 0.0: enabled 0 I2C: 00:15: enabled 1 I2C: 00:10: enabled 0 I2C: 00:10: enabled 0 I2C: 00:2c: enabled 1 I2C: 00:40: enabled 1 I2C: 00:10: enabled 1 I2C: 00:39: enabled 1 I2C: 00:36: enabled 1 I2C: 00:10: enabled 0 I2C: 00:0c: enabled 1 I2C: 00:50: enabled 1 I2C: 00:1a: enabled 1 I2C: 00:1a: enabled 0 I2C: 00:1a: enabled 0 I2C: 00:28: enabled 1 I2C: 00:29: enabled 1 PCI: 00:00.0: enabled 1 SPI: 00: enabled 1 PNP: 0c09.0: enabled 1 GENERIC: 0.0: enabled 0 USB2 port 0: enabled 1 USB2 port 1: enabled 1 USB2 port 2: enabled 1 USB2 port 3: enabled 1 USB2 port 4: enabled 0 USB2 port 5: enabled 1 USB2 port 6: enabled 0 USB2 port 7: enabled 1 USB3 port 0: enabled 1 USB3 port 1: enabled 1 USB3 port 2: enabled 1 USB3 port 3: enabled 1 APIC: 00: enabled 1 APIC: 02: enabled 1 Compare with tree... Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 APIC: 02: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:04.0: enabled 1 GENERIC: 0.0: enabled 1 PCI: 00:05.0: enabled 1 GENERIC: 0.0: enabled 1 PCI: 00:09.0: enabled 0 PCI: 00:12.6: enabled 0 PCI: 00:14.0: enabled 1 USB0 port 0: enabled 1 USB2 port 0: enabled 1 USB2 port 1: enabled 1 USB2 port 2: enabled 1 USB2 port 3: enabled 1 USB2 port 4: enabled 0 USB2 port 5: enabled 1 USB2 port 6: enabled 0 USB2 port 7: enabled 1 USB3 port 0: enabled 1 USB3 port 1: enabled 1 USB3 port 2: enabled 1 USB3 port 3: enabled 1 PCI: 00:14.1: enabled 0 PCI: 00:14.2: enabled 0 PCI: 00:14.3: enabled 1 GENERIC: 0.0: enabled 1 PCI: 00:14.5: enabled 1 PCI: 00:15.0: enabled 1 I2C: 00:2c: enabled 1 I2C: 00:15: enabled 1 PCI: 00:15.1: enabled 1 PCI: 00:15.2: enabled 1 GENERIC: 0.0: enabled 0 I2C: 00:15: enabled 1 I2C: 00:10: enabled 0 I2C: 00:10: enabled 0 I2C: 00:2c: enabled 1 I2C: 00:40: enabled 1 I2C: 00:10: enabled 1 I2C: 00:39: enabled 1 PCI: 00:15.3: enabled 1 I2C: 00:36: enabled 1 I2C: 00:10: enabled 0 I2C: 00:0c: enabled 1 I2C: 00:50: enabled 1 PCI: 00:16.0: enabled 1 PCI: 00:16.1: enabled 0 PCI: 00:16.4: enabled 0 PCI: 00:16.5: enabled 0 PCI: 00:17.0: enabled 0 PCI: 00:19.0: enabled 1 I2C: 00:1a: enabled 1 I2C: 00:1a: enabled 0 I2C: 00:1a: enabled 0 I2C: 00:28: enabled 1 I2C: 00:29: enabled 1 PCI: 00:19.1: enabled 0 PCI: 00:19.2: enabled 1 PCI: 00:1a.0: enabled 1 PCI: 00:1e.0: enabled 0 PCI: 00:1e.1: enabled 0 PCI: 00:1e.2: enabled 1 SPI: 00: enabled 1 PCI: 00:1e.3: enabled 0 PCI: 00:1f.0: enabled 1 PNP: 0c09.0: enabled 1 PCI: 00:1f.1: enabled 1 PCI: 00:1f.2: enabled 1 PCI: 00:1f.3: enabled 1 GENERIC: 0.0: enabled 0 PCI: 00:1f.4: enabled 0 PCI: 00:1f.5: enabled 1 PCI: 00:1f.7: enabled 0 Root Device scanning... scan_static_bus for Root Device CPU_CLUSTER: 0 enabled DOMAIN: 0000 enabled DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [8086/0000] ops PCI: 00:00.0 [8086/4e22] enabled PCI: 00:02.0 [8086/0000] bus ops PCI: 00:02.0 [8086/4e55] enabled PCI: 00:04.0 [8086/0000] bus ops PCI: 00:04.0 [8086/4e03] enabled PCI: 00:05.0 [8086/0000] bus ops PCI: 00:05.0 [8086/4e19] enabled PCI: 00:08.0 [8086/4e11] enabled PCI: 00:14.0 [8086/0000] bus ops PCI: 00:14.0 [8086/4ded] enabled PCI: 00:14.2 [8086/4def] disabled PCI: 00:14.3 [8086/0000] bus ops PCI: 00:14.3 [8086/4df0] enabled PCI: 00:14.5 [8086/0000] ops PCI: 00:14.5 [8086/4df8] enabled PCI: 00:15.0 [8086/0000] bus ops PCI: 00:15.0 [8086/4de8] enabled PCI: 00:15.1 [8086/0000] bus ops PCI: 00:15.1 [8086/4de9] enabled PCI: 00:15.2 [8086/0000] bus ops PCI: 00:15.2 [8086/4dea] enabled PCI: 00:15.3 [8086/0000] bus ops PCI: 00:15.3 [8086/4deb] enabled PCI: 00:16.0 [8086/0000] ops PCI: 00:16.0 [8086/4de0] enabled PCI: 00:19.0 [8086/0000] bus ops PCI: 00:19.0 [8086/4dc5] enabled PCI: 00:19.2 [8086/0000] ops PCI: 00:19.2 [8086/4dc7] enabled PCI: 00:1a.0 [8086/0000] ops PCI: 00:1a.0 [8086/4dc4] enabled PCI: 00:1e.0 [8086/0000] ops PCI: 00:1e.0 [8086/4da8] disabled PCI: 00:1e.2 [8086/0000] bus ops PCI: 00:1e.2 [8086/4daa] enabled PCI: 00:1f.0 [8086/0000] bus ops PCI: 00:1f.0 [8086/4d87] enabled PCI: Static device PCI: 00:1f.1 not found, disabling it. RTC Init Set power on after power failure. Disabling Deep S3 Disabling Deep S3 Disabling Deep S4 Disabling Deep S4 Disabling Deep S5 Disabling Deep S5 PCI: 00:1f.2 [0000/0000] hidden PCI: 00:1f.3 [8086/0000] bus ops PCI: 00:1f.3 [8086/4dc8] enabled PCI: 00:1f.5 [8086/0000] bus ops PCI: 00:1f.5 [8086/4da4] enabled PCI: Leftover static devices: PCI: 00:12.6 PCI: 00:09.0 PCI: 00:14.1 PCI: 00:16.1 PCI: 00:16.4 PCI: 00:16.5 PCI: 00:17.0 PCI: 00:19.1 PCI: 00:1e.1 PCI: 00:1e.3 PCI: 00:1f.1 PCI: 00:1f.4 PCI: 00:1f.7 PCI: Check your devicetree.cb. PCI: 00:02.0 scanning... scan_generic_bus for PCI: 00:02.0 scan_generic_bus for PCI: 00:02.0 done scan_bus: bus PCI: 00:02.0 finished in 7 msecs PCI: 00:04.0 scanning... scan_generic_bus for PCI: 00:04.0 GENERIC: 0.0 enabled bus: PCI: 00:04.0[0]->scan_generic_bus for PCI: 00:04.0 done scan_bus: bus PCI: 00:04.0 finished in 11 msecs PCI: 00:05.0 scanning... scan_generic_bus for PCI: 00:05.0 GENERIC: 0.0 enabled bus: PCI: 00:05.0[0]->scan_generic_bus for PCI: 00:05.0 done scan_bus: bus PCI: 00:05.0 finished in 11 msecs PCI: 00:14.0 scanning... scan_static_bus for PCI: 00:14.0 USB0 port 0 enabled USB0 port 0 scanning... scan_static_bus for USB0 port 0 USB2 port 0 enabled USB2 port 1 enabled USB2 port 2 enabled USB2 port 3 enabled USB2 port 4 disabled USB2 port 5 enabled USB2 port 6 disabled USB2 port 7 enabled USB3 port 0 enabled USB3 port 1 enabled USB3 port 2 enabled USB3 port 3 enabled USB2 port 0 scanning... scan_static_bus for USB2 port 0 scan_static_bus for USB2 port 0 done scan_bus: bus USB2 port 0 finished in 6 msecs USB2 port 1 scanning... scan_static_bus for USB2 port 1 scan_static_bus for USB2 port 1 done scan_bus: bus USB2 port 1 finished in 6 msecs USB2 port 2 scanning... scan_static_bus for USB2 port 2 scan_static_bus for USB2 port 2 done scan_bus: bus USB2 port 2 finished in 6 msecs USB2 port 3 scanning... scan_static_bus for USB2 port 3 scan_static_bus for USB2 port 3 done scan_bus: bus USB2 port 3 finished in 6 msecs USB2 port 5 scanning... scan_static_bus for USB2 port 5 scan_static_bus for USB2 port 5 done scan_bus: bus USB2 port 5 finished in 6 msecs USB2 port 7 scanning... scan_static_bus for USB2 port 7 scan_static_bus for USB2 port 7 done scan_bus: bus USB2 port 7 finished in 6 msecs USB3 port 0 scanning... scan_static_bus for USB3 port 0 scan_static_bus for USB3 port 0 done scan_bus: bus USB3 port 0 finished in 6 msecs USB3 port 1 scanning... scan_static_bus for USB3 port 1 scan_static_bus for USB3 port 1 done scan_bus: bus USB3 port 1 finished in 6 msecs USB3 port 2 scanning... scan_static_bus for USB3 port 2 scan_static_bus for USB3 port 2 done scan_bus: bus USB3 port 2 finished in 6 msecs USB3 port 3 scanning... scan_static_bus for USB3 port 3 scan_static_bus for USB3 port 3 done scan_bus: bus USB3 port 3 finished in 6 msecs scan_static_bus for USB0 port 0 done scan_bus: bus USB0 port 0 finished in 172 msecs scan_static_bus for PCI: 00:14.0 done scan_bus: bus PCI: 00:14.0 finished in 188 msecs PCI: 00:14.3 scanning... scan_static_bus for PCI: 00:14.3 GENERIC: 0.0 enabled scan_static_bus for PCI: 00:14.3 done scan_bus: bus PCI: 00:14.3 finished in 9 msecs PCI: 00:15.0 scanning... scan_static_bus for PCI: 00:15.0 I2C: 00:2c enabled I2C: 00:15 enabled scan_static_bus for PCI: 00:15.0 done scan_bus: bus PCI: 00:15.0 finished in 10 msecs PCI: 00:15.1 scanning... scan_static_bus for PCI: 00:15.1 scan_static_bus for PCI: 00:15.1 done scan_bus: bus PCI: 00:15.1 finished in 7 msecs PCI: 00:15.2 scanning... scan_static_bus for PCI: 00:15.2 GENERIC: 0.0 disabled I2C: 00:15 enabled I2C: 00:10 disabled I2C: 00:10 disabled I2C: 00:2c enabled I2C: 00:40 enabled I2C: 00:10 enabled I2C: 00:39 enabled scan_static_bus for PCI: 00:15.2 done scan_bus: bus PCI: 00:15.2 finished in 23 msecs PCI: 00:15.3 scanning... scan_static_bus for PCI: 00:15.3 I2C: 00:36 enabled I2C: 00:10 disabled I2C: 00:0c enabled I2C: 00:50 enabled scan_static_bus for PCI: 00:15.3 done scan_bus: bus PCI: 00:15.3 finished in 14 msecs PCI: 00:19.0 scanning... scan_static_bus for PCI: 00:19.0 I2C: 00:1a enabled I2C: 00:1a disabled I2C: 00:1a disabled I2C: 00:28 enabled I2C: 00:29 enabled scan_static_bus for PCI: 00:19.0 done scan_bus: bus PCI: 00:19.0 finished in 17 msecs PCI: 00:1e.2 scanning... scan_generic_bus for PCI: 00:1e.2 SPI: 00 enabled bus: PCI: 00:1e.2[0]->scan_generic_bus for PCI: 00:1e.2 done scan_bus: bus PCI: 00:1e.2 finished in 11 msecs PCI: 00:1f.0 scanning... scan_static_bus for PCI: 00:1f.0 PNP: 0c09.0 enabled PNP: 0c09.0 scanning... scan_static_bus for PNP: 0c09.0 scan_static_bus for PNP: 0c09.0 done scan_bus: bus PNP: 0c09.0 finished in 6 msecs scan_static_bus for PCI: 00:1f.0 done scan_bus: bus PCI: 00:1f.0 finished in 23 msecs PCI: 00:1f.3 scanning... scan_static_bus for PCI: 00:1f.3 GENERIC: 0.0 disabled scan_static_bus for PCI: 00:1f.3 done scan_bus: bus PCI: 00:1f.3 finished in 9 msecs PCI: 00:1f.5 scanning... scan_generic_bus for PCI: 00:1f.5 scan_generic_bus for PCI: 00:1f.5 done scan_bus: bus PCI: 00:1f.5 finished in 7 msecs scan_bus: bus DOMAIN: 0000 finished in 645 msecs scan_static_bus for Root Device done scan_bus: bus Root Device finished in 664 msecs done BS: BS_DEV_ENUMERATE run times (exec / console): 6 / 1084 ms Chrome EC: UHEPI supported FMAP: area UNIFIED_MRC_CACHE found @ bca000 (196608 bytes) SF: Detected 00 0000 with sector size 0x1000, total 0x1000000 SPI flash protection: WPSW=0 SRP0=0 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'. BS: BS_DEV_ENUMERATE exit times (exec / console): 1 / 23 ms found VGA at PCI: 00:02.0 Setting up VGA for PCI: 00:02.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done DOMAIN: 0000 read_resources bus 0 link: 0 PCI: 00:04.0 read_resources bus 1 link: 0 PCI: 00:04.0 read_resources bus 1 link: 0 done PCI: 00:05.0 read_resources bus 2 link: 0 PCI: 00:05.0 read_resources bus 2 link: 0 done PCI: 00:14.0 read_resources bus 0 link: 0 USB0 port 0 read_resources bus 0 link: 0 USB0 port 0 read_resources bus 0 link: 0 done PCI: 00:14.0 read_resources bus 0 link: 0 done PCI: 00:14.3 read_resources bus 0 link: 0 PCI: 00:14.3 read_resources bus 0 link: 0 done PCI: 00:15.0 read_resources bus 0 link: 0 PCI: 00:15.0 read_resources bus 0 link: 0 done PCI: 00:15.2 read_resources bus 0 link: 0 PCI: 00:15.2 read_resources bus 0 link: 0 done PCI: 00:15.3 read_resources bus 0 link: 0 PCI: 00:15.3 read_resources bus 0 link: 0 done PCI: 00:19.0 read_resources bus 0 link: 0 PCI: 00:19.0 read_resources bus 0 link: 0 done PCI: 00:1e.2 read_resources bus 3 link: 0 PCI: 00:1e.2 read_resources bus 3 link: 0 done PCI: 00:1f.0 read_resources bus 0 link: 0 PCI: 00:1f.0 read_resources bus 0 link: 0 done PCI: 00:1f.3 read_resources bus 0 link: 0 PCI: 00:1f.3 read_resources bus 0 link: 0 done DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 APIC: 02 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100 PCI: 00:00.0 PCI: 00:00.0 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0 PCI: 00:00.0 resource base fea80000 size 8000 align 0 gran 0 limit 0 flags f0000200 index 1 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3 PCI: 00:00.0 resource base fb000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 6 PCI: 00:00.0 resource base fed92000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8 PCI: 00:00.0 resource base fed85000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9 PCI: 00:00.0 resource base fed86000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a PCI: 00:00.0 resource base fed87000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index d PCI: 00:00.0 resource base c0000 size 76f40000 align 0 gran 0 limit 0 flags e0004200 index e PCI: 00:00.0 resource base 77000000 size 8c00000 align 0 gran 0 limit 0 flags f0000200 index f PCI: 00:00.0 resource base 100000000 size 80400000 align 0 gran 0 limit 0 flags e0004200 index 10 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12 PCI: 00:02.0 PCI: 00:02.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10 PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18 PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20 PCI: 00:04.0 child on link 0 GENERIC: 0.0 PCI: 00:04.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10 GENERIC: 0.0 PCI: 00:05.0 child on link 0 GENERIC: 0.0 PCI: 00:05.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10 GENERIC: 0.0 PCI: 00:08.0 PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10 PCI: 00:14.0 child on link 0 USB0 port 0 PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10 USB0 port 0 child on link 0 USB2 port 0 USB2 port 0 USB2 port 1 USB2 port 2 USB2 port 3 USB2 port 4 USB2 port 5 USB2 port 6 USB2 port 7 USB3 port 0 USB3 port 1 USB3 port 2 USB3 port 3 PCI: 00:14.2 PCI: 00:14.3 child on link 0 GENERIC: 0.0 PCI: 00:14.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 GENERIC: 0.0 PCI: 00:14.5 PCI: 00:14.5 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10 PCI: 00:15.0 child on link 0 I2C: 00:2c PCI: 00:15.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10 I2C: 00:2c I2C: 00:15 PCI: 00:15.1 PCI: 00:15.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10 PCI: 00:15.2 child on link 0 GENERIC: 0.0 PCI: 00:15.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10 GENERIC: 0.0 I2C: 00:15 I2C: 00:10 I2C: 00:10 I2C: 00:2c I2C: 00:40 I2C: 00:10 I2C: 00:39 PCI: 00:15.3 child on link 0 I2C: 00:36 PCI: 00:15.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10 I2C: 00:36 I2C: 00:10 I2C: 00:0c I2C: 00:50 PCI: 00:16.0 PCI: 00:16.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10 PCI: 00:19.0 child on link 0 I2C: 00:1a PCI: 00:19.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10 I2C: 00:1a I2C: 00:1a I2C: 00:1a I2C: 00:28 I2C: 00:29 PCI: 00:19.2 PCI: 00:19.2 resource base fe032000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10 PCI: 00:19.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18 PCI: 00:1a.0 PCI: 00:1a.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10 PCI: 00:1e.0 PCI: 00:1e.2 child on link 0 SPI: 00 PCI: 00:1e.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10 SPI: 00 PCI: 00:1f.0 child on link 0 PNP: 0c09.0 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0 PNP: 0c09.0 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0 PCI: 00:1f.2 PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 1901 flags c0000100 index 1 PCI: 00:1f.3 child on link 0 GENERIC: 0.0 PCI: 00:1f.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 PCI: 00:1f.3 resource base 0 size 100000 align 20 gran 20 limit ffffffffffffffff flags 201 index 20 GENERIC: 0.0 PCI: 00:1f.5 PCI: 00:1f.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 ==== Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) === === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) === DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff update_constraints: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed) update_constraints: PNP: 0c09.0 00 base 00000800 limit 000009fe io (fixed) update_constraints: PCI: 00:1f.2 01 base 00001800 limit 000018ff io (fixed) DOMAIN: 0000: Resource ranges: * Base: 1000, Size: 800, Tag: 100 * Base: 1900, Size: e700, Tag: 100 PCI: 00:02.0 20 * [0x1000 - 0x103f] limit: 103f io DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff update_constraints: PCI: 00:00.0 00 base c0000000 limit cfffffff mem (fixed) update_constraints: PCI: 00:00.0 01 base fea80000 limit fea87fff mem (fixed) update_constraints: PCI: 00:00.0 02 base feda0000 limit feda0fff mem (fixed) update_constraints: PCI: 00:00.0 03 base feda1000 limit feda1fff mem (fixed) update_constraints: PCI: 00:00.0 04 base fb000000 limit fb000fff mem (fixed) update_constraints: PCI: 00:00.0 05 base fed80000 limit fed83fff mem (fixed) update_constraints: PCI: 00:00.0 06 base fed90000 limit fed90fff mem (fixed) update_constraints: PCI: 00:00.0 07 base fed92000 limit fed92fff mem (fixed) update_constraints: PCI: 00:00.0 08 base fed84000 limit fed84fff mem (fixed) update_constraints: PCI: 00:00.0 09 base fed85000 limit fed85fff mem (fixed) update_constraints: PCI: 00:00.0 0a base fed86000 limit fed86fff mem (fixed) update_constraints: PCI: 00:00.0 0b base fed87000 limit fed87fff mem (fixed) update_constraints: PCI: 00:00.0 0c base fed91000 limit fed91fff mem (fixed) update_constraints: PCI: 00:00.0 0d base 00000000 limit 0009ffff mem (fixed) update_constraints: PCI: 00:00.0 0e base 000c0000 limit 76ffffff mem (fixed) update_constraints: PCI: 00:00.0 0f base 77000000 limit 7fbfffff mem (fixed) update_constraints: PCI: 00:00.0 10 base 100000000 limit 1803fffff mem (fixed) update_constraints: PCI: 00:00.0 11 base 000a0000 limit 000bffff mem (fixed) update_constraints: PCI: 00:00.0 12 base 000c0000 limit 000fffff mem (fixed) update_constraints: PCI: 00:19.2 10 base fe032000 limit fe032fff mem (fixed) update_constraints: PCI: 00:1f.2 00 base fe000000 limit fe00ffff mem (fixed) DOMAIN: 0000: Resource ranges: * Base: 7fc00000, Size: 40400000, Tag: 200 * Base: d0000000, Size: 2b000000, Tag: 200 * Base: fb001000, Size: 2fff000, Tag: 200 * Base: fe010000, Size: 22000, Tag: 200 * Base: fe033000, Size: a4d000, Tag: 200 * Base: fea88000, Size: 2f8000, Tag: 200 * Base: fed88000, Size: 8000, Tag: 200 * Base: fed93000, Size: d000, Tag: 200 * Base: feda2000, Size: 125e000, Tag: 200 * Base: 180400000, Size: 7e7fc00000, Tag: 100200 PCI: 00:02.0 18 * [0x80000000 - 0x8fffffff] limit: 8fffffff prefmem PCI: 00:02.0 10 * [0x90000000 - 0x90ffffff] limit: 90ffffff mem PCI: 00:05.0 10 * [0x91000000 - 0x91ffffff] limit: 91ffffff mem PCI: 00:1f.3 20 * [0x7fc00000 - 0x7fcfffff] limit: 7fcfffff mem PCI: 00:04.0 10 * [0x7fd00000 - 0x7fd0ffff] limit: 7fd0ffff mem PCI: 00:14.0 10 * [0x7fd10000 - 0x7fd1ffff] limit: 7fd1ffff mem PCI: 00:14.3 10 * [0x7fd20000 - 0x7fd23fff] limit: 7fd23fff mem PCI: 00:1f.3 10 * [0x7fd24000 - 0x7fd27fff] limit: 7fd27fff mem PCI: 00:08.0 10 * [0x7fd28000 - 0x7fd28fff] limit: 7fd28fff mem PCI: 00:14.5 10 * [0x7fd29000 - 0x7fd29fff] limit: 7fd29fff mem PCI: 00:15.0 10 * [0x7fd2a000 - 0x7fd2afff] limit: 7fd2afff mem PCI: 00:15.1 10 * [0x7fd2b000 - 0x7fd2bfff] limit: 7fd2bfff mem PCI: 00:15.2 10 * [0x7fd2c000 - 0x7fd2cfff] limit: 7fd2cfff mem PCI: 00:15.3 10 * [0x7fd2d000 - 0x7fd2dfff] limit: 7fd2dfff mem PCI: 00:16.0 10 * [0x7fd2e000 - 0x7fd2efff] limit: 7fd2efff mem PCI: 00:19.0 10 * [0x7fd2f000 - 0x7fd2ffff] limit: 7fd2ffff mem PCI: 00:19.2 18 * [0x7fd30000 - 0x7fd30fff] limit: 7fd30fff mem PCI: 00:1a.0 10 * [0x7fd31000 - 0x7fd31fff] limit: 7fd31fff mem PCI: 00:1e.2 10 * [0x7fd32000 - 0x7fd32fff] limit: 7fd32fff mem PCI: 00:1f.5 10 * [0x7fd33000 - 0x7fd33fff] limit: 7fd33fff mem DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff done === Resource allocator: DOMAIN: 0000 - resource allocation complete === Root Device assign_resources, bus 0 link: 0 DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:02.0 10 <- [0x0090000000 - 0x0090ffffff] size 0x01000000 gran 0x18 mem64 PCI: 00:02.0 18 <- [0x0080000000 - 0x008fffffff] size 0x10000000 gran 0x1c prefmem64 PCI: 00:02.0 20 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io PCI: 00:04.0 10 <- [0x007fd00000 - 0x007fd0ffff] size 0x00010000 gran 0x10 mem64 PCI: 00:04.0 assign_resources, bus 1 link: 0 PCI: 00:04.0 assign_resources, bus 1 link: 0 PCI: 00:05.0 10 <- [0x0091000000 - 0x0091ffffff] size 0x01000000 gran 0x18 mem64 PCI: 00:05.0 assign_resources, bus 2 link: 0 PCI: 00:05.0 assign_resources, bus 2 link: 0 PCI: 00:08.0 10 <- [0x007fd28000 - 0x007fd28fff] size 0x00001000 gran 0x0c mem64 PCI: 00:14.0 10 <- [0x007fd10000 - 0x007fd1ffff] size 0x00010000 gran 0x10 mem64 PCI: 00:14.0 assign_resources, bus 0 link: 0 PCI: 00:14.0 assign_resources, bus 0 link: 0 PCI: 00:14.3 10 <- [0x007fd20000 - 0x007fd23fff] size 0x00004000 gran 0x0e mem64 PCI: 00:14.3 assign_resources, bus 0 link: 0 PCI: 00:14.3 assign_resources, bus 0 link: 0 PCI: 00:14.5 10 <- [0x007fd29000 - 0x007fd29fff] size 0x00001000 gran 0x0c mem64 PCI: 00:15.0 10 <- [0x007fd2a000 - 0x007fd2afff] size 0x00001000 gran 0x0c mem64 PCI: 00:15.0 assign_resources, bus 0 link: 0 PCI: 00:15.0 assign_resources, bus 0 link: 0 PCI: 00:15.1 10 <- [0x007fd2b000 - 0x007fd2bfff] size 0x00001000 gran 0x0c mem64 PCI: 00:15.2 10 <- [0x007fd2c000 - 0x007fd2cfff] size 0x00001000 gran 0x0c mem64 PCI: 00:15.2 assign_resources, bus 0 link: 0 PCI: 00:15.2 assign_resources, bus 0 link: 0 PCI: 00:15.3 10 <- [0x007fd2d000 - 0x007fd2dfff] size 0x00001000 gran 0x0c mem64 PCI: 00:15.3 assign_resources, bus 0 link: 0 PCI: 00:15.3 assign_resources, bus 0 link: 0 PCI: 00:16.0 10 <- [0x007fd2e000 - 0x007fd2efff] size 0x00001000 gran 0x0c mem64 PCI: 00:19.0 10 <- [0x007fd2f000 - 0x007fd2ffff] size 0x00001000 gran 0x0c mem64 PCI: 00:19.0 assign_resources, bus 0 link: 0 PCI: 00:19.0 assign_resources, bus 0 link: 0 PCI: 00:19.2 18 <- [0x007fd30000 - 0x007fd30fff] size 0x00001000 gran 0x0c mem64 PCI: 00:1a.0 10 <- [0x007fd31000 - 0x007fd31fff] size 0x00001000 gran 0x0c mem64 PCI: 00:1e.2 10 <- [0x007fd32000 - 0x007fd32fff] size 0x00001000 gran 0x0c mem64 PCI: 00:1e.2 assign_resources, bus 3 link: 0 PCI: 00:1e.2 assign_resources, bus 3 link: 0 PCI: 00:1f.0 assign_resources, bus 0 link: 0 PCI: 00:1f.0 assign_resources, bus 0 link: 0 LPC: Trying to open IO window from 800 size 1ff PCI: 00:1f.3 10 <- [0x007fd24000 - 0x007fd27fff] size 0x00004000 gran 0x0e mem64 PCI: 00:1f.3 20 <- [0x007fc00000 - 0x007fcfffff] size 0x00100000 gran 0x14 mem64 PCI: 00:1f.3 assign_resources, bus 0 link: 0 PCI: 00:1f.3 assign_resources, bus 0 link: 0 PCI: 00:1f.5 10 <- [0x007fd33000 - 0x007fd33fff] size 0x00001000 gran 0x0c mem DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 APIC: 02 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100 PCI: 00:00.0 PCI: 00:00.0 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0 PCI: 00:00.0 resource base fea80000 size 8000 align 0 gran 0 limit 0 flags f0000200 index 1 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3 PCI: 00:00.0 resource base fb000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 6 PCI: 00:00.0 resource base fed92000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8 PCI: 00:00.0 resource base fed85000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9 PCI: 00:00.0 resource base fed86000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a PCI: 00:00.0 resource base fed87000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index d PCI: 00:00.0 resource base c0000 size 76f40000 align 0 gran 0 limit 0 flags e0004200 index e PCI: 00:00.0 resource base 77000000 size 8c00000 align 0 gran 0 limit 0 flags f0000200 index f PCI: 00:00.0 resource base 100000000 size 80400000 align 0 gran 0 limit 0 flags e0004200 index 10 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12 PCI: 00:02.0 PCI: 00:02.0 resource base 90000000 size 1000000 align 24 gran 24 limit 90ffffff flags 60000201 index 10 PCI: 00:02.0 resource base 80000000 size 10000000 align 28 gran 28 limit 8fffffff flags 60001201 index 18 PCI: 00:02.0 resource base 1000 size 40 align 6 gran 6 limit 103f flags 60000100 index 20 PCI: 00:04.0 child on link 0 GENERIC: 0.0 PCI: 00:04.0 resource base 7fd00000 size 10000 align 16 gran 16 limit 7fd0ffff flags 60000201 index 10 GENERIC: 0.0 PCI: 00:05.0 child on link 0 GENERIC: 0.0 PCI: 00:05.0 resource base 91000000 size 1000000 align 24 gran 24 limit 91ffffff flags 60000201 index 10 GENERIC: 0.0 PCI: 00:08.0 PCI: 00:08.0 resource base 7fd28000 size 1000 align 12 gran 12 limit 7fd28fff flags 60000201 index 10 PCI: 00:14.0 child on link 0 USB0 port 0 PCI: 00:14.0 resource base 7fd10000 size 10000 align 16 gran 16 limit 7fd1ffff flags 60000201 index 10 USB0 port 0 child on link 0 USB2 port 0 USB2 port 0 USB2 port 1 USB2 port 2 USB2 port 3 USB2 port 4 USB2 port 5 USB2 port 6 USB2 port 7 USB3 port 0 USB3 port 1 USB3 port 2 USB3 port 3 PCI: 00:14.2 PCI: 00:14.3 child on link 0 GENERIC: 0.0 PCI: 00:14.3 resource base 7fd20000 size 4000 align 14 gran 14 limit 7fd23fff flags 60000201 index 10 GENERIC: 0.0 PCI: 00:14.5 PCI: 00:14.5 resource base 7fd29000 size 1000 align 12 gran 12 limit 7fd29fff flags 60000201 index 10 PCI: 00:15.0 child on link 0 I2C: 00:2c PCI: 00:15.0 resource base 7fd2a000 size 1000 align 12 gran 12 limit 7fd2afff flags 60000201 index 10 I2C: 00:2c I2C: 00:15 PCI: 00:15.1 PCI: 00:15.1 resource base 7fd2b000 size 1000 align 12 gran 12 limit 7fd2bfff flags 60000201 index 10 PCI: 00:15.2 child on link 0 GENERIC: 0.0 PCI: 00:15.2 resource base 7fd2c000 size 1000 align 12 gran 12 limit 7fd2cfff flags 60000201 index 10 GENERIC: 0.0 I2C: 00:15 I2C: 00:10 I2C: 00:10 I2C: 00:2c I2C: 00:40 I2C: 00:10 I2C: 00:39 PCI: 00:15.3 child on link 0 I2C: 00:36 PCI: 00:15.3 resource base 7fd2d000 size 1000 align 12 gran 12 limit 7fd2dfff flags 60000201 index 10 I2C: 00:36 I2C: 00:10 I2C: 00:0c I2C: 00:50 PCI: 00:16.0 PCI: 00:16.0 resource base 7fd2e000 size 1000 align 12 gran 12 limit 7fd2efff flags 60000201 index 10 PCI: 00:19.0 child on link 0 I2C: 00:1a PCI: 00:19.0 resource base 7fd2f000 size 1000 align 12 gran 12 limit 7fd2ffff flags 60000201 index 10 I2C: 00:1a I2C: 00:1a I2C: 00:1a I2C: 00:28 I2C: 00:29 PCI: 00:19.2 PCI: 00:19.2 resource base fe032000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10 PCI: 00:19.2 resource base 7fd30000 size 1000 align 12 gran 12 limit 7fd30fff flags 60000201 index 18 PCI: 00:1a.0 PCI: 00:1a.0 resource base 7fd31000 size 1000 align 12 gran 12 limit 7fd31fff flags 60000201 index 10 PCI: 00:1e.0 PCI: 00:1e.2 child on link 0 SPI: 00 PCI: 00:1e.2 resource base 7fd32000 size 1000 align 12 gran 12 limit 7fd32fff flags 60000201 index 10 SPI: 00 PCI: 00:1f.0 child on link 0 PNP: 0c09.0 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0 PNP: 0c09.0 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0 PCI: 00:1f.2 PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 1901 flags c0000100 index 1 PCI: 00:1f.3 child on link 0 GENERIC: 0.0 PCI: 00:1f.3 resource base 7fd24000 size 4000 align 14 gran 14 limit 7fd27fff flags 60000201 index 10 PCI: 00:1f.3 resource base 7fc00000 size 100000 align 20 gran 20 limit 7fcfffff flags 60000201 index 20 GENERIC: 0.0 PCI: 00:1f.5 PCI: 00:1f.5 resource base 7fd33000 size 1000 align 12 gran 12 limit 7fd33fff flags 60000200 index 10 Done allocating resources. BS: BS_DEV_RESOURCES run times (exec / console): 21 / 2094 ms Enabling resources... PCI: 00:00.0 subsystem <- 8086/4e22 PCI: 00:00.0 cmd <- 06 PCI: 00:02.0 subsystem <- 8086/4e55 PCI: 00:02.0 cmd <- 03 PCI: 00:04.0 subsystem <- 8086/4e03 PCI: 00:04.0 cmd <- 02 PCI: 00:05.0 bridge ctrl <- 0003 PCI: 00:05.0 subsystem <- 8086/4e19 PCI: 00:05.0 cmd <- 02 PCI: 00:08.0 cmd <- 06 PCI: 00:14.0 subsystem <- 8086/4ded PCI: 00:14.0 cmd <- 02 PCI: 00:14.3 subsystem <- 8086/4df0 PCI: 00:14.3 cmd <- 02 PCI: 00:14.5 subsystem <- 8086/4df8 PCI: 00:14.5 cmd <- 06 PCI: 00:15.0 subsystem <- 8086/4de8 PCI: 00:15.0 cmd <- 02 PCI: 00:15.1 subsystem <- 8086/4de9 PCI: 00:15.1 cmd <- 02 PCI: 00:15.2 subsystem <- 8086/4dea PCI: 00:15.2 cmd <- 02 PCI: 00:15.3 subsystem <- 8086/4deb PCI: 00:15.3 cmd <- 02 PCI: 00:16.0 subsystem <- 8086/4de0 PCI: 00:16.0 cmd <- 02 PCI: 00:19.0 subsystem <- 8086/4dc5 PCI: 00:19.0 cmd <- 02 PCI: 00:19.2 subsystem <- 8086/4dc7 PCI: 00:19.2 cmd <- 06 PCI: 00:1a.0 subsystem <- 8086/4dc4 PCI: 00:1a.0 cmd <- 06 PCI: 00:1e.2 subsystem <- 8086/4daa PCI: 00:1e.2 cmd <- 06 PCI: 00:1f.0 subsystem <- 8086/4d87 PCI: 00:1f.0 cmd <- 407 PCI: 00:1f.3 subsystem <- 8086/4dc8 PCI: 00:1f.3 cmd <- 02 PCI: 00:1f.5 subsystem <- 8086/4da4 PCI: 00:1f.5 cmd <- 406 done. BS: BS_DEV_ENABLE run times (exec / console): 7 / 121 ms Initializing devices... Root Device init mainboard: EC init Chrome EC: Set SMI mask to 0x0000000000000000 Chrome EC: clear events_b mask to 0x0000000000000000 Chrome EC: Set S5 LAZY WAKE mask to 0x0000000000000006 Chrome EC: Set S3 LAZY WAKE mask to 0x000000001000101e Chrome EC: Set S0iX LAZY WAKE mask to 0x000000001000101e Chrome EC: Set WAKE mask to 0x0000000000000000 Root Device init finished in 36 msecs PCI: 00:00.0 init CPU TDP = 6 Watts CPU PL1 = 7 Watts CPU PL2 = 12 Watts PCI: 00:00.0 init finished in 6 msecs PCI: 00:02.0 init GMA: Found VBT in CBFS GMA: Found valid VBT in CBFS framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32 x_res x y_res: 1920 x 1080, size: 8294400 at 0x80000000 PCI: 00:02.0 init finished in 18 msecs PCI: 00:08.0 init PCI: 00:08.0 init finished in 0 msecs PCI: 00:14.0 init XHCI: Updated LFPS sampling OFF time to 9 ms PCI: 00:14.0 init finished in 4 msecs PCI: 00:15.0 init I2C bus 0 version 0x3230302a DW I2C bus 0 at 0x7fd2a000 (400 KHz) PCI: 00:15.0 init finished in 6 msecs PCI: 00:15.1 init I2C bus 1 version 0x3230302a DW I2C bus 1 at 0x7fd2b000 (400 KHz) PCI: 00:15.1 init finished in 6 msecs PCI: 00:15.2 init I2C bus 2 version 0x3230302a DW I2C bus 2 at 0x7fd2c000 (400 KHz) PCI: 00:15.2 init finished in 6 msecs PCI: 00:15.3 init I2C bus 3 version 0x3230302a DW I2C bus 3 at 0x7fd2d000 (400 KHz) PCI: 00:15.3 init finished in 6 msecs PCI: 00:16.0 init PCI: 00:16.0 init finished in 0 msecs PCI: 00:19.0 init I2C bus 4 version 0x3230302a DW I2C bus 4 at 0x7fd2f000 (400 KHz) PCI: 00:19.0 init finished in 6 msecs PCI: 00:1a.0 init PCI: 00:1a.0 init finished in 0 msecs PCI: 00:1f.0 init IOAPIC: Initializing IOAPIC at 0xfec00000 IOAPIC: Bootstrap Processor Local APIC = 0x00 IOAPIC: ID = 0x02 IOAPIC: Dumping registers reg 0x0000: 0x02000000 reg 0x0001: 0x00770020 reg 0x0002: 0x00000000 PCI: 00:1f.0 init finished in 21 msecs PCI: 00:1f.2 init Disabling ACPI via APMC. APMC done. PCI: 00:1f.2 init finished in 6 msecs PNP: 0c09.0 init Google Chrome EC uptime: 6.516 seconds Google Chrome AP resets since EC boot: 0 Google Chrome most recent AP reset causes: Google Chrome EC reset flags at last EC boot: reset-pin PNP: 0c09.0 init finished in 19 msecs Devices initialized Show all devs... After init. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:04.0: enabled 1 PCI: 00:05.0: enabled 1 PCI: 00:09.0: enabled 0 PCI: 00:12.6: enabled 0 PCI: 00:14.0: enabled 1 PCI: 00:14.1: enabled 0 PCI: 00:14.2: enabled 0 PCI: 00:14.3: enabled 1 PCI: 00:14.5: enabled 1 PCI: 00:15.0: enabled 1 PCI: 00:15.1: enabled 1 PCI: 00:15.2: enabled 1 PCI: 00:15.3: enabled 1 PCI: 00:16.0: enabled 1 PCI: 00:16.1: enabled 0 PCI: 00:16.4: enabled 0 PCI: 00:16.5: enabled 0 PCI: 00:17.0: enabled 0 PCI: 00:19.0: enabled 1 PCI: 00:19.1: enabled 0 PCI: 00:19.2: enabled 1 PCI: 00:1a.0: enabled 1 PCI: 00:1c.0: enabled 0 PCI: 00:1c.1: enabled 0 PCI: 00:1c.2: enabled 0 PCI: 00:1c.3: enabled 0 PCI: 00:1c.4: enabled 0 PCI: 00:1c.5: enabled 0 PCI: 00:1c.6: enabled 0 PCI: 00:1c.7: enabled 1 PCI: 00:1e.0: enabled 0 PCI: 00:1e.1: enabled 0 PCI: 00:1e.2: enabled 1 PCI: 00:1e.3: enabled 0 PCI: 00:1f.0: enabled 1 PCI: 00:1f.1: enabled 0 PCI: 00:1f.2: enabled 1 PCI: 00:1f.3: enabled 1 PCI: 00:1f.4: enabled 0 PCI: 00:1f.5: enabled 1 PCI: 00:1f.7: enabled 0 GENERIC: 0.0: enabled 1 GENERIC: 0.0: enabled 1 USB0 port 0: enabled 1 GENERIC: 0.0: enabled 1 I2C: 00:2c: enabled 1 I2C: 00:15: enabled 1 GENERIC: 0.0: enabled 0 I2C: 00:15: enabled 1 I2C: 00:10: enabled 0 I2C: 00:10: enabled 0 I2C: 00:2c: enabled 1 I2C: 00:40: enabled 1 I2C: 00:10: enabled 1 I2C: 00:39: enabled 1 I2C: 00:36: enabled 1 I2C: 00:10: enabled 0 I2C: 00:0c: enabled 1 I2C: 00:50: enabled 1 I2C: 00:1a: enabled 1 I2C: 00:1a: enabled 0 I2C: 00:1a: enabled 0 I2C: 00:28: enabled 1 I2C: 00:29: enabled 1 PCI: 00:00.0: enabled 1 SPI: 00: enabled 1 PNP: 0c09.0: enabled 1 GENERIC: 0.0: enabled 0 USB2 port 0: enabled 1 USB2 port 1: enabled 1 USB2 port 2: enabled 1 USB2 port 3: enabled 1 USB2 port 4: enabled 0 USB2 port 5: enabled 1 USB2 port 6: enabled 0 USB2 port 7: enabled 1 USB3 port 0: enabled 1 USB3 port 1: enabled 1 USB3 port 2: enabled 1 USB3 port 3: enabled 1 APIC: 00: enabled 1 APIC: 02: enabled 1 PCI: 00:08.0: enabled 1 BS: BS_DEV_INIT run times (exec / console): 25 / 437 ms FMAP: area RW_ELOG found @ bfa000 (4096 bytes) ELOG: NV offset 0xbfa000 size 0x1000 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024 ELOG: Event(17) added with size 13 at 2023-12-07 06:42:33 UTC ELOG: Event(92) added with size 9 at 2023-12-07 06:42:34 UTC ELOG: Event(93) added with size 9 at 2023-12-07 06:42:34 UTC ELOG: Event(9E) added with size 10 at 2023-12-07 06:42:34 UTC ELOG: Event(9F) added with size 14 at 2023-12-07 06:42:34 UTC BS: BS_DEV_INIT exit times (exec / console): 3 / 45 ms ELOG: Event(A1) added with size 10 at 2023-12-07 06:42:34 UTC elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b ELOG: Event(A0) added with size 9 at 2023-12-07 06:42:34 UTC elog_add_boot_reason: Logged dev mode boot BS: BS_POST_DEVICE entry times (exec / console): 0 / 24 ms Finalize devices... Devices finalized BS: BS_POST_DEVICE run times (exec / console): 0 / 4 ms FMAP: area RW_NVRAM found @ bfe000 (8192 bytes) BS: BS_POST_DEVICE exit times (exec / console): 0 / 5 ms ME: HFSTS1 : 0x80030045 ME: HFSTS2 : 0x30280136 ME: HFSTS3 : 0x00000050 ME: HFSTS4 : 0x00004000 ME: HFSTS5 : 0x00000000 ME: HFSTS6 : 0x40400006 ME: Manufacturing Mode : NO ME: FW Partition Table : OK ME: Bringup Loader Failure : NO ME: Firmware Init Complete : NO ME: Boot Options Present : NO ME: Update In Progress : NO ME: D0i3 Support : YES ME: Low Power State Enabled : NO ME: CPU Replaced : YES ME: CPU Replacement Valid : YES ME: Current Working State : 5 ME: Current Operation State : 1 ME: Current Operation Mode : 3 ME: Error Code : 0 ME: CPU Debug Disabled : YES ME: TXT Support : NO BS: BS_OS_RESUME_CHECK exit times (exec / console): 0 / 77 ms CBFS: Found 'fallback/dsdt.aml' @0x41280 size 0x32d2 ACPI: Writing ACPI tables at 76b27000. ACPI: * FACS ACPI: * DSDT Ramoops buffer: 0x100000@0x76a26000. FMAP: area RO_VPD found @ c00000 (16384 bytes) FMAP: area RW_VPD found @ bfc000 (8192 bytes) Google Chrome EC: version: ro: magolor_1.1.9999-103b6f9 rw: magolor_1.1.9999-103b6f9 running image: 1 PCI space above 4GB MMIO is at 0x180400000, len = 0x7e7fc00000 ACPI: * FADT SCI is IRQ9 ACPI: added table 1/32, length now 40 ACPI: * SSDT Found 1 CPU(s) with 2 core(s) each. \_SB.DPTF: Intel DPTF at GENERIC: 0.0 \_SB.PCI0.IPU0.IPU0: Intel MIPI Camera Device I2C address 00h Could not locate 'wifi_sar' in VPD. Checking CBFS for default SAR values wifi_sar_defaults.hex has bad len in CBFS failed from getting SAR limits! \_SB.PCI0.CNVW: WIFI Device GENERIC: 0.0 \_SB.PCI0.I2C0.H02C: Synaptics Touchpad at I2C: 00:2c \_SB.PCI0.I2C0.D015: ELAN Touchpad at I2C: 00:15 \_SB.PCI0.I2C2.H015: ELAN Touchscreen at I2C: 00:15 \_SB.PCI0.I2C2.H02C: WDT Touchscreen at I2C: 00:2c \_SB.PCI0.I2C2.H040: G2 Touchscreen at I2C: 00:40 \_SB.PCI0.I2C2.D010: ELAN Touchscreen at I2C: 00:10 \_SB.PCI0.I2C2.D039: Raydium Touchscreen at I2C: 00:39 \_SB.PCI0.I2C3.CAM0: Intel MIPI Camera Device I2C address 036h \_SB.PCI0.I2C3.VCM0: Intel MIPI Camera Device I2C address 0ch \_SB.PCI0.I2C3.NVM0: Intel MIPI Camera Device I2C address 050h \_SB.PCI0.I2C4.RT58: Realtek RT5682 at I2C: 00:1a \_SB.PCI0.I2C4.D028: Realtek SPK AMP L at I2C: 00:28 \_SB.PCI0.I2C4.D029: Realtek SPK AMP R at I2C: 00:29 \_SB.PCI0.SPI0.S001: SPI Device at SPI: 00 PS2K: Physmap: [ EA E9 E7 91 92 94 95 A0 AE B0 ] PS2K: Passing 101 keymaps to kernel \_SB.PCI0.XHCI.RHUB.HS01: Left Type-C Port at USB2 port 0 \_SB.PCI0.XHCI.RHUB.HS02: Right Type-C Port at USB2 port 1 \_SB.PCI0.XHCI.RHUB.HS03: Left Type-A Port at USB2 port 2 \_SB.PCI0.XHCI.RHUB.HS04: Right Type-A Port at USB2 port 3 \_SB.PCI0.XHCI.RHUB.HS06: Camera at USB2 port 5 \_SB.PCI0.XHCI.RHUB.HS08: Bluetooth at USB2 port 7 \_SB.PCI0.XHCI.RHUB.SS01: Left Type-C Port at USB3 port 0 \_SB.PCI0.XHCI.RHUB.SS02: Right Type-C Port at USB3 port 1 \_SB.PCI0.XHCI.RHUB.SS03: Left Type-A Port at USB3 port 2 \_SB.PCI0.XHCI.RHUB.SS04: Right Type-A Port at USB3 port 3 ACPI: added table 2/32, length now 44 ACPI: * MCFG ACPI: added table 3/32, length now 48 ACPI: * TPM2 TPM2 log created at 0x76a16000 ACPI: added table 4/32, length now 52 ACPI: * MADT SCI is IRQ9 ACPI: added table 5/32, length now 56 current = 76b2d580 ACPI: * DMAR ACPI: added table 6/32, length now 60 ACPI: added table 7/32, length now 64 ACPI: * HPET ACPI: added table 8/32, length now 68 ACPI: done. ACPI tables: 26304 bytes. smbios_write_tables: 76a15000 EC returned error result code 3 Couldn't obtain OEM name from CBI Create SMBIOS type 16 Create SMBIOS type 17 GENERIC: 0.0 (WIFI Device) SMBIOS tables: 913 bytes. Writing table forward entry at 0x00000500 Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum d929 Writing coreboot table at 0x76b4b000 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000a0000-00000000000fffff: RESERVED 3. 0000000000100000-0000000076a14fff: RAM 4. 0000000076a15000-0000000076ba7fff: CONFIGURATION TABLES 5. 0000000076ba8000-0000000076c0cfff: RAMSTAGE 6. 0000000076c0d000-0000000076ffffff: CONFIGURATION TABLES 7. 0000000077000000-000000007fbfffff: RESERVED 8. 00000000c0000000-00000000cfffffff: RESERVED 9. 00000000fb000000-00000000fb000fff: RESERVED 10. 00000000fe000000-00000000fe00ffff: RESERVED 11. 00000000fea80000-00000000fea87fff: RESERVED 12. 00000000fed80000-00000000fed87fff: RESERVED 13. 00000000fed90000-00000000fed92fff: RESERVED 14. 00000000feda0000-00000000feda1fff: RESERVED 15. 0000000100000000-00000001803fffff: RAM Passing 4 GPIOs to payload: NAME | PORT | POLARITY | VALUE lid | undefined | high | high power | undefined | high | low oprom | undefined | high | low EC in RW | 0x000000b9 | high | low Wrote coreboot table at: 0x76b4b000, 0x5c8 bytes, checksum a608 coreboot table: 1504 bytes. IMD ROOT 0. 0x76fff000 0x00001000 IMD SMALL 1. 0x76ffe000 0x00001000 FSP MEMORY 2. 0x76c4e000 0x003b0000 CONSOLE 3. 0x76c2e000 0x00020000 FMAP 4. 0x76c2d000 0x00000578 TIME STAMP 5. 0x76c2c000 0x00000910 VBOOT WORK 6. 0x76c18000 0x00014000 ROMSTG STCK 7. 0x76c17000 0x00001000 AFTER CAR 8. 0x76c0d000 0x0000a000 RAMSTAGE 9. 0x76ba7000 0x00066000 REFCODE 10. 0x76b67000 0x00040000 SMM BACKUP 11. 0x76b57000 0x00010000 4f444749 12. 0x76b55000 0x00002000 EXT VBT13. 0x76b53000 0x00001c43 COREBOOT 14. 0x76b4b000 0x00008000 ACPI 15. 0x76b27000 0x00024000 ACPI GNVS 16. 0x76b26000 0x00001000 RAMOOPS 17. 0x76a26000 0x00100000 TPM2 TCGLOG18. 0x76a16000 0x00010000 SMBIOS 19. 0x76a15000 0x00000800 IMD small region: IMD ROOT 0. 0x76ffec00 0x00000400 FSP RUNTIME 1. 0x76ffebe0 0x00000004 VPD 2. 0x76ffeb80 0x00000058 POWER STATE 3. 0x76ffeb40 0x00000040 ROMSTAGE 4. 0x76ffeb20 0x00000004 MEM INFO 5. 0x76ffe940 0x000001e0 BS: BS_WRITE_TABLES run times (exec / console): 7 / 516 ms MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x0000000077000000 size 0x76f40000 type 6 0x0000000077000000 - 0x0000000080000000 size 0x09000000 type 0 0x0000000080000000 - 0x0000000090000000 size 0x10000000 type 1 0x0000000090000000 - 0x0000000100000000 size 0x70000000 type 0 0x0000000100000000 - 0x0000000180400000 size 0x80400000 type 6 MTRR: Fixed MSR 0x250 0x0606060606060606 MTRR: Fixed MSR 0x258 0x0606060606060606 MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x0606060606060606 MTRR: Fixed MSR 0x269 0x0606060606060606 MTRR: Fixed MSR 0x26a 0x0606060606060606 MTRR: Fixed MSR 0x26b 0x0606060606060606 MTRR: Fixed MSR 0x26c 0x0606060606060606 MTRR: Fixed MSR 0x26d 0x0606060606060606 MTRR: Fixed MSR 0x26e 0x0606060606060606 MTRR: Fixed MSR 0x26f 0x0606060606060606 call enable_fixed_mtrr() CPU physical address size: 39 bits MTRR: default type WB/UC MTRR counts: 6/5. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6 MTRR: 1 base 0x0000000077000000 mask 0x0000007fff000000 type 0 MTRR: 2 base 0x0000000078000000 mask 0x0000007ff8000000 type 0 MTRR: 3 base 0x0000000080000000 mask 0x0000007ff0000000 type 1 MTRR: 4 base 0x0000000100000000 mask 0x0000007f00000000 type 6 MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled MTRR: Fixed MSR 0x250 0x0606060606060606 MTRR: Fixed MSR 0x258 0x0606060606060606 MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x0606060606060606 MTRR: Fixed MSR 0x269 0x0606060606060606 MTRR: Fixed MSR 0x26a 0x0606060606060606 MTRR: Fixed MSR 0x26b 0x0606060606060606 MTRR: Fixed MSR 0x26c 0x0606060606060606 MTRR: Fixed MSR 0x26d 0x0606060606060606 MTRR: Fixed MSR 0x26e 0x0606060606060606 MTRR: Fixed MSR 0x26f 0x0606060606060606 BS: BS_WRITE_TABLES exit times (exec / console): 1 / 143 ms call enable_fixed_mtrr() Checking cr50 for pending updates CPU physical address size: 39 bits Reading cr50 TPM mode BS: BS_PAYLOAD_LOAD entry times (exec / console): 11 / 6 ms CBFS: Found 'fallback/payload' @0x395580 size 0x4ae38 Checking segment from ROM address 0xfff9d5b8 Checking segment from ROM address 0xfff9d5d4 Loading segment from ROM address 0xfff9d5b8 code (compression=0) New segment dstaddr 0x30000000 memsize 0x1062170 srcaddr 0xfff9d5f0 filesize 0x4ae00 Loading Segment: addr: 0x30000000 memsz: 0x0000000001062170 filesz: 0x000000000004ae00 it's not compressed! [ 0x30000000, 3004ae00, 0x31062170) <- fff9d5f0 Clearing Segment: addr: 0x000000003004ae00 memsz: 0x0000000001017370 Loading segment from ROM address 0xfff9d5d4 Entry Point 0x30000000 Loaded segments BS: BS_PAYLOAD_LOAD run times (exec / console): 126 / 60 ms Finalizing chipset. Finalizing SMM. APMC done. BS: BS_PAYLOAD_LOAD exit times (exec / console): 15 / 5 ms mp_park_aps done after 0 msecs. Jumping to boot code at 0x30000000(0x76b4b000) CPU0: stack: 0x76bfb000 - 0x76bfc000, lowest used address 0x76bfb918, stack used: 1768 bytes Starting depthcharge on Magolor... WARNING: can't convert coreboot GPIOs, 'lid' won't be resampled at runtime! WARNING: can't convert coreboot GPIOs, 'power' won't be resampled at runtime! fw_config match found: AUDIO_AMP=UNPROVISIONED Wipe memory regions: [0x00000000001000, 0x000000000a0000) [0x00000000100000, 0x00000030000000) [0x00000031062170, 0x00000076a15000) [0x00000100000000, 0x00000180400000) R8152: Initializing Version 9 (ocp_data = 6010) R8152: Done initializing Adding net device [firmware-dedede-13606.B-collabora] Apr 28 2022 09:20:48 dedede: tftpboot 192.168.201.1 12205520/tftp-deploy-ry50sqyo/kernel/bzImage 12205520/tftp-deploy-ry50sqyo/kernel/cmdline 12205520/tftp-deploy-ry50sqyo/ramdisk/ramdisk.cpio.gz tftpboot 192.168.201.1 12205520/tftp-deploy-ry50sqyo/kernel/bzIploy-ry50sqyo/kernel/cmdline 12205520/tftp-deploy-ry50sqyo/ramdisk/ramdisk.cpio.gz Waiting for link done. MAC: 00:e0:4c:72:3d:b7 Sending DHCP discover... done. Waiting for reply... done. Sending DHCP request... done. Waiting for reply... done. My ip is 192.168.201.22 The DHCP server ip is 192.168.201.1 TFTP server IP predefined by user: 192.168.201.1 Bootfile predefined by user: 12205520/tftp-deploy-ry50sqyo/kernel/bzImage Sending tftp read request... done. Waiting for the transfer... 00000000 ################################################################ 00080000 ################################################################ 00100000 ################################################################ 00180000 ################################################################ 00200000 ################################################################ 00280000 ################################################################ 00300000 ################################################################ 00380000 ################################################################ 00400000 ################################################################ 00480000 ################################################################ 00500000 ################################################################ 00580000 ################################################################ 00600000 ################################################################ 00680000 ################################################################ 00700000 ################################################################ 00780000 ################################################################ 00800000 ####################### done. The bootfile was 8576912 bytes long. Sending tftp read request... done. Waiting for the transfer... 00000000 ################################################################ 00080000 ################################################################ 00100000 ################################################################ 00180000 ################################################################ 00200000 ################################################################ 00280000 ################################################################ 00300000 ################################################################ 00380000 ################################################################ 00400000 ################################################################ 00480000 ################################################################ 00500000 ################################################################ 00580000 ################################################################ 00600000 ################################################################ 00680000 ################################################################ 00700000 ################################################################ 00780000 ################################################################ 00800000 ##################################################### done. Sending tftp read request... done. Waiting for the transfer... 00000000 # done. Command line loaded dynamically from TFTP file: 12205520/tftp-deploy-ry50sqyo/kernel/cmdline The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1 ec_init: CrosEC protocol v3 supported (256, 256) Shutting down all USB controllers. Removing current net device Finalizing coreboot Exiting depthcharge with code 4 at timestamp: 17608146 Starting kernel ...