Boot log: asus-cx9400-volteer
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Kernel Errors: 0
- Boot result: FAIL
1 12:43:51.536249 lava-dispatcher, installed at version: 2024.01
2 12:43:51.536462 start: 0 validate
3 12:43:51.536603 Start time: 2024-03-05 12:43:51.536589+00:00 (UTC)
4 12:43:51.536719 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:43:51.536849 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230623.0%2Fx86%2Frootfs.cpio.gz exists
6 12:43:51.797765 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:43:51.798442 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-4.4.y-st-rc%2Fv4.4-st20-2247-g140bf69dc64d%2Fx86_64%2Fx86_64_defconfig%2Bx86-board%2Fgcc-10%2Fkernel%2FbzImage exists
8 12:43:52.060505 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:43:52.061410 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-4.4.y-st-rc%2Fv4.4-st20-2247-g140bf69dc64d%2Fx86_64%2Fx86_64_defconfig%2Bx86-board%2Fgcc-10%2Fmodules.tar.xz exists
10 12:43:52.329375 validate duration: 0.79
12 12:43:52.329690 start: 1 tftp-deploy (timeout 00:10:00) [common]
13 12:43:52.329817 start: 1.1 download-retry (timeout 00:10:00) [common]
14 12:43:52.329932 start: 1.1.1 http-download (timeout 00:10:00) [common]
15 12:43:52.330080 Not decompressing ramdisk as can be used compressed.
16 12:43:52.330177 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230623.0/x86/rootfs.cpio.gz
17 12:43:52.330249 saving as /var/lib/lava/dispatcher/tmp/12948307/tftp-deploy-d3sr_p9r/ramdisk/rootfs.cpio.gz
18 12:43:52.330351 total size: 8418130 (8 MB)
19 12:43:52.331858 progress 0 % (0 MB)
20 12:43:52.334344 progress 5 % (0 MB)
21 12:43:52.336631 progress 10 % (0 MB)
22 12:43:52.338849 progress 15 % (1 MB)
23 12:43:52.341132 progress 20 % (1 MB)
24 12:43:52.343365 progress 25 % (2 MB)
25 12:43:52.345635 progress 30 % (2 MB)
26 12:43:52.347692 progress 35 % (2 MB)
27 12:43:52.349952 progress 40 % (3 MB)
28 12:43:52.352292 progress 45 % (3 MB)
29 12:43:52.354513 progress 50 % (4 MB)
30 12:43:52.356795 progress 55 % (4 MB)
31 12:43:52.359058 progress 60 % (4 MB)
32 12:43:52.361129 progress 65 % (5 MB)
33 12:43:52.363300 progress 70 % (5 MB)
34 12:43:52.365512 progress 75 % (6 MB)
35 12:43:52.367728 progress 80 % (6 MB)
36 12:43:52.369917 progress 85 % (6 MB)
37 12:43:52.372150 progress 90 % (7 MB)
38 12:43:52.374370 progress 95 % (7 MB)
39 12:43:52.376452 progress 100 % (8 MB)
40 12:43:52.376689 8 MB downloaded in 0.05 s (173.25 MB/s)
41 12:43:52.376869 end: 1.1.1 http-download (duration 00:00:00) [common]
43 12:43:52.377135 end: 1.1 download-retry (duration 00:00:00) [common]
44 12:43:52.377242 start: 1.2 download-retry (timeout 00:10:00) [common]
45 12:43:52.377342 start: 1.2.1 http-download (timeout 00:10:00) [common]
46 12:43:52.377494 downloading http://storage.kernelci.org/cip/linux-4.4.y-st-rc/v4.4-st20-2247-g140bf69dc64d/x86_64/x86_64_defconfig+x86-board/gcc-10/kernel/bzImage
47 12:43:52.377573 saving as /var/lib/lava/dispatcher/tmp/12948307/tftp-deploy-d3sr_p9r/kernel/bzImage
48 12:43:52.377673 total size: 9367440 (8 MB)
49 12:43:52.377773 No compression specified
50 12:43:52.379387 progress 0 % (0 MB)
51 12:43:52.382044 progress 5 % (0 MB)
52 12:43:52.384553 progress 10 % (0 MB)
53 12:43:52.387009 progress 15 % (1 MB)
54 12:43:52.389708 progress 20 % (1 MB)
55 12:43:52.392185 progress 25 % (2 MB)
56 12:43:52.394662 progress 30 % (2 MB)
57 12:43:52.397310 progress 35 % (3 MB)
58 12:43:52.399760 progress 40 % (3 MB)
59 12:43:52.402242 progress 45 % (4 MB)
60 12:43:52.404727 progress 50 % (4 MB)
61 12:43:52.407302 progress 55 % (4 MB)
62 12:43:52.409733 progress 60 % (5 MB)
63 12:43:52.412161 progress 65 % (5 MB)
64 12:43:52.414716 progress 70 % (6 MB)
65 12:43:52.417148 progress 75 % (6 MB)
66 12:43:52.419524 progress 80 % (7 MB)
67 12:43:52.421917 progress 85 % (7 MB)
68 12:43:52.424507 progress 90 % (8 MB)
69 12:43:52.426903 progress 95 % (8 MB)
70 12:43:52.429313 progress 100 % (8 MB)
71 12:43:52.429543 8 MB downloaded in 0.05 s (172.24 MB/s)
72 12:43:52.429706 end: 1.2.1 http-download (duration 00:00:00) [common]
74 12:43:52.429962 end: 1.2 download-retry (duration 00:00:00) [common]
75 12:43:52.430070 start: 1.3 download-retry (timeout 00:10:00) [common]
76 12:43:52.430171 start: 1.3.1 http-download (timeout 00:10:00) [common]
77 12:43:52.430327 downloading http://storage.kernelci.org/cip/linux-4.4.y-st-rc/v4.4-st20-2247-g140bf69dc64d/x86_64/x86_64_defconfig+x86-board/gcc-10/modules.tar.xz
78 12:43:52.430400 saving as /var/lib/lava/dispatcher/tmp/12948307/tftp-deploy-d3sr_p9r/modules/modules.tar
79 12:43:52.430498 total size: 251176 (0 MB)
80 12:43:52.430599 Using unxz to decompress xz
81 12:43:52.435357 progress 13 % (0 MB)
82 12:43:52.435801 progress 26 % (0 MB)
83 12:43:52.436086 progress 39 % (0 MB)
84 12:43:52.437631 progress 52 % (0 MB)
85 12:43:52.439533 progress 65 % (0 MB)
86 12:43:52.441331 progress 78 % (0 MB)
87 12:43:52.443276 progress 91 % (0 MB)
88 12:43:52.445159 progress 100 % (0 MB)
89 12:43:52.450567 0 MB downloaded in 0.02 s (11.94 MB/s)
90 12:43:52.450813 end: 1.3.1 http-download (duration 00:00:00) [common]
92 12:43:52.451112 end: 1.3 download-retry (duration 00:00:00) [common]
93 12:43:52.451224 start: 1.4 prepare-tftp-overlay (timeout 00:10:00) [common]
94 12:43:52.451338 start: 1.4.1 extract-nfsrootfs (timeout 00:10:00) [common]
95 12:43:52.451438 end: 1.4.1 extract-nfsrootfs (duration 00:00:00) [common]
96 12:43:52.451551 start: 1.4.2 lava-overlay (timeout 00:10:00) [common]
97 12:43:52.451808 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/12948307/lava-overlay-mmhivv_d
98 12:43:52.451989 makedir: /var/lib/lava/dispatcher/tmp/12948307/lava-overlay-mmhivv_d/lava-12948307/bin
99 12:43:52.452181 makedir: /var/lib/lava/dispatcher/tmp/12948307/lava-overlay-mmhivv_d/lava-12948307/tests
100 12:43:52.452324 makedir: /var/lib/lava/dispatcher/tmp/12948307/lava-overlay-mmhivv_d/lava-12948307/results
101 12:43:52.452456 Creating /var/lib/lava/dispatcher/tmp/12948307/lava-overlay-mmhivv_d/lava-12948307/bin/lava-add-keys
102 12:43:52.452618 Creating /var/lib/lava/dispatcher/tmp/12948307/lava-overlay-mmhivv_d/lava-12948307/bin/lava-add-sources
103 12:43:52.452767 Creating /var/lib/lava/dispatcher/tmp/12948307/lava-overlay-mmhivv_d/lava-12948307/bin/lava-background-process-start
104 12:43:52.452915 Creating /var/lib/lava/dispatcher/tmp/12948307/lava-overlay-mmhivv_d/lava-12948307/bin/lava-background-process-stop
105 12:43:52.453064 Creating /var/lib/lava/dispatcher/tmp/12948307/lava-overlay-mmhivv_d/lava-12948307/bin/lava-common-functions
106 12:43:52.453235 Creating /var/lib/lava/dispatcher/tmp/12948307/lava-overlay-mmhivv_d/lava-12948307/bin/lava-echo-ipv4
107 12:43:52.453406 Creating /var/lib/lava/dispatcher/tmp/12948307/lava-overlay-mmhivv_d/lava-12948307/bin/lava-install-packages
108 12:43:52.453574 Creating /var/lib/lava/dispatcher/tmp/12948307/lava-overlay-mmhivv_d/lava-12948307/bin/lava-installed-packages
109 12:43:52.453717 Creating /var/lib/lava/dispatcher/tmp/12948307/lava-overlay-mmhivv_d/lava-12948307/bin/lava-os-build
110 12:43:52.453866 Creating /var/lib/lava/dispatcher/tmp/12948307/lava-overlay-mmhivv_d/lava-12948307/bin/lava-probe-channel
111 12:43:52.454013 Creating /var/lib/lava/dispatcher/tmp/12948307/lava-overlay-mmhivv_d/lava-12948307/bin/lava-probe-ip
112 12:43:52.454158 Creating /var/lib/lava/dispatcher/tmp/12948307/lava-overlay-mmhivv_d/lava-12948307/bin/lava-target-ip
113 12:43:52.454302 Creating /var/lib/lava/dispatcher/tmp/12948307/lava-overlay-mmhivv_d/lava-12948307/bin/lava-target-mac
114 12:43:52.454449 Creating /var/lib/lava/dispatcher/tmp/12948307/lava-overlay-mmhivv_d/lava-12948307/bin/lava-target-storage
115 12:43:52.454628 Creating /var/lib/lava/dispatcher/tmp/12948307/lava-overlay-mmhivv_d/lava-12948307/bin/lava-test-case
116 12:43:52.454801 Creating /var/lib/lava/dispatcher/tmp/12948307/lava-overlay-mmhivv_d/lava-12948307/bin/lava-test-event
117 12:43:52.454974 Creating /var/lib/lava/dispatcher/tmp/12948307/lava-overlay-mmhivv_d/lava-12948307/bin/lava-test-feedback
118 12:43:52.455147 Creating /var/lib/lava/dispatcher/tmp/12948307/lava-overlay-mmhivv_d/lava-12948307/bin/lava-test-raise
119 12:43:52.455321 Creating /var/lib/lava/dispatcher/tmp/12948307/lava-overlay-mmhivv_d/lava-12948307/bin/lava-test-reference
120 12:43:52.455498 Creating /var/lib/lava/dispatcher/tmp/12948307/lava-overlay-mmhivv_d/lava-12948307/bin/lava-test-runner
121 12:43:52.455671 Creating /var/lib/lava/dispatcher/tmp/12948307/lava-overlay-mmhivv_d/lava-12948307/bin/lava-test-set
122 12:43:52.455845 Creating /var/lib/lava/dispatcher/tmp/12948307/lava-overlay-mmhivv_d/lava-12948307/bin/lava-test-shell
123 12:43:52.456020 Updating /var/lib/lava/dispatcher/tmp/12948307/lava-overlay-mmhivv_d/lava-12948307/bin/lava-install-packages (oe)
124 12:43:52.456264 Updating /var/lib/lava/dispatcher/tmp/12948307/lava-overlay-mmhivv_d/lava-12948307/bin/lava-installed-packages (oe)
125 12:43:52.456431 Creating /var/lib/lava/dispatcher/tmp/12948307/lava-overlay-mmhivv_d/lava-12948307/environment
126 12:43:52.456571 LAVA metadata
127 12:43:52.456682 - LAVA_JOB_ID=12948307
128 12:43:52.456786 - LAVA_DISPATCHER_IP=192.168.201.1
129 12:43:52.456944 start: 1.4.2.1 lava-vland-overlay (timeout 00:10:00) [common]
130 12:43:52.457045 skipped lava-vland-overlay
131 12:43:52.457176 end: 1.4.2.1 lava-vland-overlay (duration 00:00:00) [common]
132 12:43:52.457298 start: 1.4.2.2 lava-multinode-overlay (timeout 00:10:00) [common]
133 12:43:52.457403 skipped lava-multinode-overlay
134 12:43:52.457529 end: 1.4.2.2 lava-multinode-overlay (duration 00:00:00) [common]
135 12:43:52.457654 start: 1.4.2.3 test-definition (timeout 00:10:00) [common]
136 12:43:52.457771 Loading test definitions
137 12:43:52.457913 start: 1.4.2.3.1 inline-repo-action (timeout 00:10:00) [common]
138 12:43:52.458030 Using /lava-12948307 at stage 0
139 12:43:52.458475 uuid=12948307_1.4.2.3.1 testdef=None
140 12:43:52.458597 end: 1.4.2.3.1 inline-repo-action (duration 00:00:00) [common]
141 12:43:52.458732 start: 1.4.2.3.2 test-overlay (timeout 00:10:00) [common]
142 12:43:52.459387 end: 1.4.2.3.2 test-overlay (duration 00:00:00) [common]
144 12:43:52.459640 start: 1.4.2.3.3 test-install-overlay (timeout 00:10:00) [common]
145 12:43:52.460485 end: 1.4.2.3.3 test-install-overlay (duration 00:00:00) [common]
147 12:43:52.460741 start: 1.4.2.3.4 test-runscript-overlay (timeout 00:10:00) [common]
148 12:43:52.461380 runner path: /var/lib/lava/dispatcher/tmp/12948307/lava-overlay-mmhivv_d/lava-12948307/0/tests/0_dmesg test_uuid 12948307_1.4.2.3.1
149 12:43:52.461555 end: 1.4.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
151 12:43:52.461808 start: 1.4.2.3.5 inline-repo-action (timeout 00:10:00) [common]
152 12:43:52.461891 Using /lava-12948307 at stage 1
153 12:43:52.462324 uuid=12948307_1.4.2.3.5 testdef=None
154 12:43:52.462446 end: 1.4.2.3.5 inline-repo-action (duration 00:00:00) [common]
155 12:43:52.462570 start: 1.4.2.3.6 test-overlay (timeout 00:10:00) [common]
156 12:43:52.463273 end: 1.4.2.3.6 test-overlay (duration 00:00:00) [common]
158 12:43:52.463640 start: 1.4.2.3.7 test-install-overlay (timeout 00:10:00) [common]
159 12:43:52.464493 end: 1.4.2.3.7 test-install-overlay (duration 00:00:00) [common]
161 12:43:52.464748 start: 1.4.2.3.8 test-runscript-overlay (timeout 00:10:00) [common]
162 12:43:52.465398 runner path: /var/lib/lava/dispatcher/tmp/12948307/lava-overlay-mmhivv_d/lava-12948307/1/tests/1_bootrr test_uuid 12948307_1.4.2.3.5
163 12:43:52.465564 end: 1.4.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
165 12:43:52.465791 Creating lava-test-runner.conf files
166 12:43:52.465873 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12948307/lava-overlay-mmhivv_d/lava-12948307/0 for stage 0
167 12:43:52.465990 - 0_dmesg
168 12:43:52.466104 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/12948307/lava-overlay-mmhivv_d/lava-12948307/1 for stage 1
169 12:43:52.466239 - 1_bootrr
170 12:43:52.466374 end: 1.4.2.3 test-definition (duration 00:00:00) [common]
171 12:43:52.466501 start: 1.4.2.4 compress-overlay (timeout 00:10:00) [common]
172 12:43:52.474587 end: 1.4.2.4 compress-overlay (duration 00:00:00) [common]
173 12:43:52.474699 start: 1.4.2.5 persistent-nfs-overlay (timeout 00:10:00) [common]
174 12:43:52.474797 end: 1.4.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
175 12:43:52.474897 end: 1.4.2 lava-overlay (duration 00:00:00) [common]
176 12:43:52.474996 start: 1.4.3 extract-overlay-ramdisk (timeout 00:10:00) [common]
177 12:43:52.729015 end: 1.4.3 extract-overlay-ramdisk (duration 00:00:00) [common]
178 12:43:52.729434 start: 1.4.4 extract-modules (timeout 00:10:00) [common]
179 12:43:52.729576 extracting modules file /var/lib/lava/dispatcher/tmp/12948307/tftp-deploy-d3sr_p9r/modules/modules.tar to /var/lib/lava/dispatcher/tmp/12948307/extract-overlay-ramdisk-r8_db7fr/ramdisk
180 12:43:52.743037 end: 1.4.4 extract-modules (duration 00:00:00) [common]
181 12:43:52.743161 start: 1.4.5 apply-overlay-tftp (timeout 00:10:00) [common]
182 12:43:52.743261 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12948307/compress-overlay-9dtg0ugz/overlay-1.4.2.4.tar.gz to ramdisk
183 12:43:52.743344 [common] Applying overlay /var/lib/lava/dispatcher/tmp/12948307/compress-overlay-9dtg0ugz/overlay-1.4.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/12948307/extract-overlay-ramdisk-r8_db7fr/ramdisk
184 12:43:52.751579 end: 1.4.5 apply-overlay-tftp (duration 00:00:00) [common]
185 12:43:52.751696 start: 1.4.6 configure-preseed-file (timeout 00:10:00) [common]
186 12:43:52.751804 end: 1.4.6 configure-preseed-file (duration 00:00:00) [common]
187 12:43:52.751906 start: 1.4.7 compress-ramdisk (timeout 00:10:00) [common]
188 12:43:52.752015 Building ramdisk /var/lib/lava/dispatcher/tmp/12948307/extract-overlay-ramdisk-r8_db7fr/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/12948307/extract-overlay-ramdisk-r8_db7fr/ramdisk
189 12:43:52.898091 >> 49788 blocks
190 12:43:53.737882 rename /var/lib/lava/dispatcher/tmp/12948307/extract-overlay-ramdisk-r8_db7fr/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/12948307/tftp-deploy-d3sr_p9r/ramdisk/ramdisk.cpio.gz
191 12:43:53.738355 end: 1.4.7 compress-ramdisk (duration 00:00:01) [common]
192 12:43:53.738498 start: 1.4.8 prepare-kernel (timeout 00:09:59) [common]
193 12:43:53.738620 start: 1.4.8.1 prepare-fit (timeout 00:09:59) [common]
194 12:43:53.738730 No mkimage arch provided, not using FIT.
195 12:43:53.738829 end: 1.4.8.1 prepare-fit (duration 00:00:00) [common]
196 12:43:53.738954 end: 1.4.8 prepare-kernel (duration 00:00:00) [common]
197 12:43:53.739099 end: 1.4 prepare-tftp-overlay (duration 00:00:01) [common]
198 12:43:53.739205 start: 1.5 lxc-create-udev-rule-action (timeout 00:09:59) [common]
199 12:43:53.739321 No LXC device requested
200 12:43:53.739443 end: 1.5 lxc-create-udev-rule-action (duration 00:00:00) [common]
201 12:43:53.739572 start: 1.6 deploy-device-env (timeout 00:09:59) [common]
202 12:43:53.739693 end: 1.6 deploy-device-env (duration 00:00:00) [common]
203 12:43:53.739807 Checking files for TFTP limit of 4294967296 bytes.
204 12:43:53.740436 end: 1 tftp-deploy (duration 00:00:01) [common]
205 12:43:53.740557 start: 2 depthcharge-action (timeout 00:05:00) [common]
206 12:43:53.740675 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
207 12:43:53.740880 substitutions:
208 12:43:53.740980 - {DTB}: None
209 12:43:53.741080 - {INITRD}: 12948307/tftp-deploy-d3sr_p9r/ramdisk/ramdisk.cpio.gz
210 12:43:53.741177 - {KERNEL}: 12948307/tftp-deploy-d3sr_p9r/kernel/bzImage
211 12:43:53.741274 - {LAVA_MAC}: None
212 12:43:53.741369 - {PRESEED_CONFIG}: None
213 12:43:53.741462 - {PRESEED_LOCAL}: None
214 12:43:53.741537 - {RAMDISK}: 12948307/tftp-deploy-d3sr_p9r/ramdisk/ramdisk.cpio.gz
215 12:43:53.741630 - {ROOT_PART}: None
216 12:43:53.741722 - {ROOT}: None
217 12:43:53.741813 - {SERVER_IP}: 192.168.201.1
218 12:43:53.741904 - {TEE}: None
219 12:43:53.741995 Parsed boot commands:
220 12:43:53.742087 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
221 12:43:53.742317 Parsed boot commands: tftpboot 192.168.201.1 12948307/tftp-deploy-d3sr_p9r/kernel/bzImage 12948307/tftp-deploy-d3sr_p9r/kernel/cmdline 12948307/tftp-deploy-d3sr_p9r/ramdisk/ramdisk.cpio.gz
222 12:43:53.742441 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
223 12:43:53.742569 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
224 12:43:53.742702 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
225 12:43:53.742828 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
226 12:43:53.742934 Not connected, no need to disconnect.
227 12:43:53.743051 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
228 12:43:53.743303 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
229 12:43:53.743413 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh asus-cx9400-volteer-cbg-10'
230 12:43:53.747661 Setting prompt string to ['lava-test: # ']
231 12:43:53.748063 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
232 12:43:53.748236 end: 2.2.1 reset-connection (duration 00:00:00) [common]
233 12:43:53.748346 start: 2.2.2 reset-device (timeout 00:05:00) [common]
234 12:43:53.748482 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
235 12:43:53.748731 Calling: 'pduclient' '--daemon=localhost' '--hostname=asus-cx9400-volteer-cbg-10' '--port=1' '--command=reboot'
236 12:43:58.898997 >> Command sent successfully.
237 12:43:58.909629 Returned 0 in 5 seconds
238 12:43:59.010884 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
240 12:43:59.012501 end: 2.2.2 reset-device (duration 00:00:05) [common]
241 12:43:59.013078 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
242 12:43:59.013609 Setting prompt string to 'Starting depthcharge on Voema...'
243 12:43:59.014023 Changing prompt to 'Starting depthcharge on Voema...'
244 12:43:59.014484 depthcharge-start: Wait for prompt Starting depthcharge on Voema... (timeout 00:05:00)
245 12:43:59.016033 [Enter `^Ec?' for help]
246 12:44:00.564593
247 12:44:00.565178
248 12:44:00.573910 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 bootblock starting (log level: 8)...
249 12:44:00.580535 CPU: 11th Gen Intel(R) Core(TM) i7-1160G7 @ 1.20GHz
250 12:44:00.584025 CPU: ID 806c1, Tigerlake B0, ucode: 00000086
251 12:44:00.587513 CPU: AES supported, TXT NOT supported, VT supported
252 12:44:00.594348 MCH: device id 9a12 (rev 01) is Tigerlake-Y-4-2
253 12:44:00.598052 PCH: device id a087 (rev 20) is Tigerlake-Y Premium SKU
254 12:44:00.604546 IGD: device id 9a40 (rev 01) is Tigerlake Y GT2
255 12:44:00.607748 VBOOT: Loading verstage.
256 12:44:00.611090 FMAP: Found "FLASH" version 1.1 at 0x1804000.
257 12:44:00.617581 FMAP: base = 0x0 size = 0x2000000 #areas = 32
258 12:44:00.620960 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
259 12:44:00.630540 CBFS: mcache @0xfef45600 built for 70 files, used 0xfdc of 0x1800 bytes
260 12:44:00.637171 CBFS: Found 'fallback/verstage' @0x165e40 size 0x147ec in mcache @0xfef45984
261 12:44:00.637742
262 12:44:00.638226
263 12:44:00.651072 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 verstage starting (log level: 8)...
264 12:44:00.665475 Probing TPM: . done!
265 12:44:00.667727 TPM ready after 0 ms
266 12:44:00.671727 Connected to device vid:did:rid of 1ae0:0028:00
267 12:44:00.682659 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.5.30/cr50_v1.9311_mp.7-535187521e
268 12:44:00.689285 Current CR50_BOARD_CFG = 0x80000001, matches desired = 0x00000001
269 12:44:00.693040 Initialized TPM device CR50 revision 0
270 12:44:00.748812 tlcl_send_startup: Startup return code is 0
271 12:44:00.749323 TPM: setup succeeded
272 12:44:00.764683 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
273 12:44:00.778738 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
274 12:44:00.791890 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
275 12:44:00.801505 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
276 12:44:00.805544 Chrome EC: UHEPI supported
277 12:44:00.808242 Phase 1
278 12:44:00.811226 FMAP: area GBB found @ 1805000 (458752 bytes)
279 12:44:00.821416 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
280 12:44:00.828088 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
281 12:44:00.835052 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
282 12:44:00.841269 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
283 12:44:00.844384 Recovery requested (1009000e)
284 12:44:00.853381 TPM: Extending digest for VBOOT: boot mode into PCR 0
285 12:44:00.859530 tlcl_extend: response is 0
286 12:44:00.866302 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
287 12:44:00.876172 tlcl_extend: response is 0
288 12:44:00.883274 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
289 12:44:00.889667 CBFS: Found 'fallback/romstage' @0x80 size 0x1bf24 in mcache @0xfef45638
290 12:44:00.896118 BS: verstage times (exec / console): total (unknown) / 142 ms
291 12:44:00.896645
292 12:44:00.896981
293 12:44:00.908797 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 romstage starting (log level: 8)...
294 12:44:00.915659 VB2:vb2api_ec_sync() In recovery mode, skipping EC sync
295 12:44:00.919397 pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00
296 12:44:00.925877 gpe0_sts[0]: 00200000 gpe0_en[0]: 00000000
297 12:44:00.928882 gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000
298 12:44:00.931781 gpe0_sts[2]: 00001000 gpe0_en[2]: 00000000
299 12:44:00.935556 gpe0_sts[3]: 00000000 gpe0_en[3]: 00092000
300 12:44:00.938762 TCO_STS: 0000 0000
301 12:44:00.942250 GEN_PMCON: d0015038 00002200
302 12:44:00.945244 GBLRST_CAUSE: 00000000 00000000
303 12:44:00.948458 HPR_CAUSE0: 00000000
304 12:44:00.948922 prev_sleep_state 5
305 12:44:00.952137 Boot Count incremented to 25335
306 12:44:00.958702 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
307 12:44:00.965662 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
308 12:44:00.975047 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
309 12:44:00.981858 CBFS: Found 'fspm.bin' @0x78fc0 size 0xa5000 in mcache @0xfef4585c
310 12:44:00.984852 Chrome EC: UHEPI supported
311 12:44:00.991604 FMAP: area RECOVERY_MRC_CACHE found @ f00000 (65536 bytes)
312 12:44:01.002816 Probing TPM: done!
313 12:44:01.009227 Connected to device vid:did:rid of 1ae0:0028:00
314 12:44:01.019105 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.5.30/cr50_v1.9311_mp.7-535187521e
315 12:44:01.022735 Initialized TPM device CR50 revision 0
316 12:44:01.038161 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x100b return code 0
317 12:44:01.044106 MRC: Hash idx 0x100b comparison successful.
318 12:44:01.047481 MRC cache found, size faa8
319 12:44:01.048142 bootmode is set to: 2
320 12:44:01.051219 SPD index = 2
321 12:44:01.058261 CBFS: Found 'spd.bin' @0x72940 size 0x600 in mcache @0xfef4579c
322 12:44:01.060661 SPD: module type is LPDDR4X
323 12:44:01.064143 SPD: module part number is MT53D1G64D4NW-046
324 12:44:01.070821 SPD: banks 8, ranks 1, rows 17, columns 10, density 16384 Mb
325 12:44:01.074292 SPD: device width 16 bits, bus width 16 bits
326 12:44:01.080576 SPD: module size is 2048 MB (per channel)
327 12:44:01.509375 CBMEM:
328 12:44:01.512595 IMD: root @ 0x76fff000 254 entries.
329 12:44:01.516156 IMD: root @ 0x76ffec00 62 entries.
330 12:44:01.519629 FMAP: area RO_VPD found @ 1800000 (16384 bytes)
331 12:44:01.525695 FMAP: area RW_VPD found @ f35000 (8192 bytes)
332 12:44:01.528836 External stage cache:
333 12:44:01.532002 IMD: root @ 0x7b3ff000 254 entries.
334 12:44:01.535582 IMD: root @ 0x7b3fec00 62 entries.
335 12:44:01.550539 FMAP: area RECOVERY_MRC_CACHE found @ f00000 (65536 bytes)
336 12:44:01.557199 MRC: Checking cached data update for 'RECOVERY_MRC_CACHE'.
337 12:44:01.563646 SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
338 12:44:01.577678 MRC: 'RECOVERY_MRC_CACHE' does not need update.
339 12:44:01.584143 cse_lite: Skip switching to RW in the recovery path
340 12:44:01.584671 8 DIMMs found
341 12:44:01.587018 SMM Memory Map
342 12:44:01.590920 SMRAM : 0x7b000000 0x800000
343 12:44:01.594154 Subregion 0: 0x7b000000 0x200000
344 12:44:01.597362 Subregion 1: 0x7b200000 0x200000
345 12:44:01.600377 Subregion 2: 0x7b400000 0x400000
346 12:44:01.600806 top_of_ram = 0x77000000
347 12:44:01.607152 MTRR Range: Start=76000000 End=77000000 (Size 1000000)
348 12:44:01.614080 MTRR Range: Start=7b000000 End=7b800000 (Size 800000)
349 12:44:01.617147 MTRR Range: Start=f9000000 End=fa000000 (Size 1000000)
350 12:44:01.623565 MTRR Range: Start=ff000000 End=0 (Size 1000000)
351 12:44:01.630391 CBFS: Found 'fallback/postcar' @0x160900 size 0x54f8 in mcache @0xfef4594c
352 12:44:01.636503 Decompressing stage fallback/postcar @ 0x76c0afc0 (38208 bytes)
353 12:44:01.647611 Loading module at 0x76c0b000 with entry 0x76c0b000. filesize: 0x5150 memsize: 0x9500
354 12:44:01.654389 Processing 211 relocs. Offset value of 0x74c0b000
355 12:44:01.660340 BS: romstage times (exec / console): total (unknown) / 277 ms
356 12:44:01.666757
357 12:44:01.667337
358 12:44:01.676816 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 postcar starting (log level: 8)...
359 12:44:01.679997 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
360 12:44:01.687115 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
361 12:44:01.696458 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
362 12:44:01.703458 CBFS: Found 'fallback/ramstage' @0x524c0 size 0x1fbe3 in mcache @0x76c4c0ec
363 12:44:01.709737 Decompressing stage fallback/ramstage @ 0x76b97fc0 (463536 bytes)
364 12:44:01.752990 Loading module at 0x76b98000 with entry 0x76b98000. filesize: 0x4d5d8 memsize: 0x71270
365 12:44:01.759730 Processing 5008 relocs. Offset value of 0x75d98000
366 12:44:01.763003 BS: postcar times (exec / console): total (unknown) / 59 ms
367 12:44:01.766004
368 12:44:01.766428
369 12:44:01.776190 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 ramstage starting (log level: 8)...
370 12:44:01.776727 Normal boot
371 12:44:01.779309 FW_CONFIG value is 0x804c02
372 12:44:01.782842 PCI: 00:07.0 disabled by fw_config
373 12:44:01.785745 PCI: 00:07.1 disabled by fw_config
374 12:44:01.792222 PCI: 00:0d.2 disabled by fw_config
375 12:44:01.796121 PCI: 00:1c.7 disabled by fw_config
376 12:44:01.798986 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
377 12:44:01.805230 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
378 12:44:01.811978 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
379 12:44:01.815214 GENERIC: 0.0 disabled by fw_config
380 12:44:01.819092 GENERIC: 1.0 disabled by fw_config
381 12:44:01.821916 fw_config match found: DB_USB=USB3_ACTIVE
382 12:44:01.825565 fw_config match found: DB_USB=USB3_ACTIVE
383 12:44:01.831776 fw_config match found: DB_USB=USB3_ACTIVE
384 12:44:01.835402 fw_config match found: DB_USB=USB3_ACTIVE
385 12:44:01.838674 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
386 12:44:01.848582 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
387 12:44:01.855100 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
388 12:44:01.861622 CBFS: Found 'cpu_microcode_blob.bin' @0x1c040 size 0x36400 in mcache @0x76c4c09c
389 12:44:01.867818 microcode: sig=0x806c1 pf=0x80 revision=0x86
390 12:44:01.871324 microcode: Update skipped, already up-to-date
391 12:44:01.877565 CBFS: Found 'fsps.bin' @0x11efc0 size 0x418f9 in mcache @0x76c4c30c
392 12:44:01.906666 Detected 4 core, 8 thread CPU.
393 12:44:01.909855 Setting up SMI for CPU
394 12:44:01.913492 IED base = 0x7b400000
395 12:44:01.915866 IED size = 0x00400000
396 12:44:01.916400 Will perform SMM setup.
397 12:44:01.922851 CPU: 11th Gen Intel(R) Core(TM) i7-1160G7 @ 1.20GHz.
398 12:44:01.929833 Loading module at 0x00030000 with entry 0x00030000. filesize: 0x170 memsize: 0x170
399 12:44:01.935821 Processing 16 relocs. Offset value of 0x00030000
400 12:44:01.939594 Attempting to start 7 APs
401 12:44:01.942445 Waiting for 10ms after sending INIT.
402 12:44:01.958561 Waiting for 1st SIPI to complete...AP: slot 1 apic_id 1.
403 12:44:01.961493 AP: slot 7 apic_id 5.
404 12:44:01.964805 AP: slot 4 apic_id 4.
405 12:44:01.965355 done.
406 12:44:01.965700 AP: slot 2 apic_id 7.
407 12:44:01.968185 AP: slot 5 apic_id 6.
408 12:44:01.971427 AP: slot 3 apic_id 3.
409 12:44:01.974987 AP: slot 6 apic_id 2.
410 12:44:01.977924 Waiting for 2nd SIPI to complete...done.
411 12:44:01.984307 Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1b8 memsize: 0x1b8
412 12:44:01.991177 Processing 13 relocs. Offset value of 0x00038000
413 12:44:01.994644 Unable to locate Global NVS
414 12:44:02.000869 SMM Module: stub loaded at 0x00038000. Will call 0x76bb6318(0x00000000)
415 12:44:02.004426 Installing permanent SMM handler to 0x7b000000
416 12:44:02.014221 Loading module at 0x7b010000 with entry 0x7b010c16. filesize: 0xa7c8 memsize: 0xf908
417 12:44:02.017020 Processing 794 relocs. Offset value of 0x7b010000
418 12:44:02.027405 Loading module at 0x7b008000 with entry 0x7b008000. filesize: 0x1b8 memsize: 0x1b8
419 12:44:02.030226 Processing 13 relocs. Offset value of 0x7b008000
420 12:44:02.036615 SMM Module: placing jmp sequence at 0x7b007c00 rel16 0x03fd
421 12:44:02.043774 SMM Module: placing jmp sequence at 0x7b007800 rel16 0x07fd
422 12:44:02.050010 SMM Module: placing jmp sequence at 0x7b007400 rel16 0x0bfd
423 12:44:02.056404 SMM Module: placing jmp sequence at 0x7b007000 rel16 0x0ffd
424 12:44:02.059774 SMM Module: placing jmp sequence at 0x7b006c00 rel16 0x13fd
425 12:44:02.066248 SMM Module: placing jmp sequence at 0x7b006800 rel16 0x17fd
426 12:44:02.073135 SMM Module: placing jmp sequence at 0x7b006400 rel16 0x1bfd
427 12:44:02.075918 Unable to locate Global NVS
428 12:44:02.082446 SMM Module: stub loaded at 0x7b008000. Will call 0x7b010c16(0x00000000)
429 12:44:02.086106 Clearing SMI status registers
430 12:44:02.089011 SMI_STS: PM1
431 12:44:02.089436 PM1_STS: PWRBTN
432 12:44:02.099316 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b000000, cpu = 0
433 12:44:02.102406 In relocation handler: CPU 0
434 12:44:02.105581 New SMBASE=0x7b000000 IEDBASE=0x7b400000
435 12:44:02.108798 Writing SMRR. base = 0x7b000006, mask=0xff800c00
436 12:44:02.111982 Relocation complete.
437 12:44:02.118913 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afffc00, cpu = 1
438 12:44:02.122036 In relocation handler: CPU 1
439 12:44:02.125428 New SMBASE=0x7afffc00 IEDBASE=0x7b400000
440 12:44:02.128411 Relocation complete.
441 12:44:02.134968 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff400, cpu = 3
442 12:44:02.138389 In relocation handler: CPU 3
443 12:44:02.141690 New SMBASE=0x7afff400 IEDBASE=0x7b400000
444 12:44:02.144837 Relocation complete.
445 12:44:02.152212 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affe800, cpu = 6
446 12:44:02.154949 In relocation handler: CPU 6
447 12:44:02.158262 New SMBASE=0x7affe800 IEDBASE=0x7b400000
448 12:44:02.164897 Writing SMRR. base = 0x7b000006, mask=0xff800c00
449 12:44:02.165438 Relocation complete.
450 12:44:02.174832 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affec00, cpu = 5
451 12:44:02.177907 In relocation handler: CPU 5
452 12:44:02.180847 New SMBASE=0x7affec00 IEDBASE=0x7b400000
453 12:44:02.184311 Writing SMRR. base = 0x7b000006, mask=0xff800c00
454 12:44:02.187823 Relocation complete.
455 12:44:02.194445 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff800, cpu = 2
456 12:44:02.197525 In relocation handler: CPU 2
457 12:44:02.200845 New SMBASE=0x7afff800 IEDBASE=0x7b400000
458 12:44:02.204271 Relocation complete.
459 12:44:02.210311 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affe400, cpu = 7
460 12:44:02.213601 In relocation handler: CPU 7
461 12:44:02.216952 New SMBASE=0x7affe400 IEDBASE=0x7b400000
462 12:44:02.220690 Relocation complete.
463 12:44:02.226904 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff000, cpu = 4
464 12:44:02.230392 In relocation handler: CPU 4
465 12:44:02.233530 New SMBASE=0x7afff000 IEDBASE=0x7b400000
466 12:44:02.240009 Writing SMRR. base = 0x7b000006, mask=0xff800c00
467 12:44:02.243208 Relocation complete.
468 12:44:02.243628 Initializing CPU #0
469 12:44:02.246701 CPU: vendor Intel device 806c1
470 12:44:02.250080 CPU: family 06, model 8c, stepping 01
471 12:44:02.252919 Clearing out pending MCEs
472 12:44:02.256486 Setting up local APIC...
473 12:44:02.260122 apic_id: 0x00 done.
474 12:44:02.263428 Turbo is available but hidden
475 12:44:02.266249 Turbo is available and visible
476 12:44:02.269474 microcode: Update skipped, already up-to-date
477 12:44:02.272537 CPU #0 initialized
478 12:44:02.272960 Initializing CPU #1
479 12:44:02.275866 Initializing CPU #7
480 12:44:02.276338 Initializing CPU #4
481 12:44:02.279038 CPU: vendor Intel device 806c1
482 12:44:02.286174 CPU: family 06, model 8c, stepping 01
483 12:44:02.288825 CPU: vendor Intel device 806c1
484 12:44:02.292524 CPU: family 06, model 8c, stepping 01
485 12:44:02.295989 Clearing out pending MCEs
486 12:44:02.296562 Clearing out pending MCEs
487 12:44:02.299243 Setting up local APIC...
488 12:44:02.302271 Initializing CPU #6
489 12:44:02.302693 Initializing CPU #3
490 12:44:02.305889 Initializing CPU #5
491 12:44:02.309213 Initializing CPU #2
492 12:44:02.312566 CPU: vendor Intel device 806c1
493 12:44:02.316239 CPU: family 06, model 8c, stepping 01
494 12:44:02.316774 apic_id: 0x04 done.
495 12:44:02.319467 Setting up local APIC...
496 12:44:02.322442 Clearing out pending MCEs
497 12:44:02.325585 CPU: vendor Intel device 806c1
498 12:44:02.329130 CPU: family 06, model 8c, stepping 01
499 12:44:02.332719 Setting up local APIC...
500 12:44:02.333146 CPU: vendor Intel device 806c1
501 12:44:02.339372 CPU: family 06, model 8c, stepping 01
502 12:44:02.342984 CPU: vendor Intel device 806c1
503 12:44:02.346267 CPU: family 06, model 8c, stepping 01
504 12:44:02.346693 Clearing out pending MCEs
505 12:44:02.349628 apic_id: 0x06 done.
506 12:44:02.352907 Setting up local APIC...
507 12:44:02.356299 microcode: Update skipped, already up-to-date
508 12:44:02.359300 apic_id: 0x07 done.
509 12:44:02.362953 CPU #5 initialized
510 12:44:02.366067 microcode: Update skipped, already up-to-date
511 12:44:02.369496 Clearing out pending MCEs
512 12:44:02.372641 CPU: vendor Intel device 806c1
513 12:44:02.375811 CPU: family 06, model 8c, stepping 01
514 12:44:02.378976 Setting up local APIC...
515 12:44:02.379410 apic_id: 0x05 done.
516 12:44:02.385484 microcode: Update skipped, already up-to-date
517 12:44:02.389162 microcode: Update skipped, already up-to-date
518 12:44:02.392704 CPU #4 initialized
519 12:44:02.393227 CPU #7 initialized
520 12:44:02.396235 Clearing out pending MCEs
521 12:44:02.399170 apic_id: 0x03 done.
522 12:44:02.399600 Clearing out pending MCEs
523 12:44:02.402355 CPU #2 initialized
524 12:44:02.405465 microcode: Update skipped, already up-to-date
525 12:44:02.409194 Setting up local APIC...
526 12:44:02.412379 Setting up local APIC...
527 12:44:02.415587 apic_id: 0x02 done.
528 12:44:02.416010 apic_id: 0x01 done.
529 12:44:02.422165 microcode: Update skipped, already up-to-date
530 12:44:02.422690 CPU #3 initialized
531 12:44:02.425118 CPU #6 initialized
532 12:44:02.428208 microcode: Update skipped, already up-to-date
533 12:44:02.432159 CPU #1 initialized
534 12:44:02.434696 bsp_do_flight_plan done after 454 msecs.
535 12:44:02.438129 CPU: frequency set to 4400 MHz
536 12:44:02.441723 Enabling SMIs.
537 12:44:02.448122 BS: BS_DEV_INIT_CHIPS entry times (exec / console): 347 / 317 ms
538 12:44:02.462530 SATAXPCIE1 indicates PCIe NVMe is present
539 12:44:02.466342 Probing TPM: done!
540 12:44:02.469460 Connected to device vid:did:rid of 1ae0:0028:00
541 12:44:02.480277 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.5.30/cr50_v1.9311_mp.7-535187521e
542 12:44:02.483504 Initialized TPM device CR50 revision 0
543 12:44:02.486709 Enabling S0i3.4
544 12:44:02.493732 CBFS: Found 'vbt.bin' @0x78a40 size 0x4f0 in mcache @0x76c4c1fc
545 12:44:02.496771 Found a VBT of 8704 bytes after decompression
546 12:44:02.503075 cse_lite: CSE RO boot. HybridStorageMode disabled
547 12:44:02.510117 WEAK: src/soc/intel/tigerlake/fsp_params.c/mainboard_silicon_init_params called
548 12:44:02.585322 FSPS returned 0
549 12:44:02.588887 Executing Phase 1 of FspMultiPhaseSiInit
550 12:44:02.598051 FSP MultiPhaseSiInit src/soc/intel/tigerlake/fsp_params.c/platform_fsp_multi_phase_init_cb called
551 12:44:02.601289 port C0 DISC req: usage 1 usb3 1 usb2 5
552 12:44:02.604518 Raw Buffer output 0 00000511
553 12:44:02.607903 Raw Buffer output 1 00000000
554 12:44:02.612010 pmc_send_ipc_cmd succeeded
555 12:44:02.618614 port C1 DISC req: usage 1 usb3 2 usb2 3
556 12:44:02.619138 Raw Buffer output 0 00000321
557 12:44:02.622078 Raw Buffer output 1 00000000
558 12:44:02.626791 pmc_send_ipc_cmd succeeded
559 12:44:02.631487 Detected 4 core, 8 thread CPU.
560 12:44:02.634842 Detected 4 core, 8 thread CPU.
561 12:44:02.834881 Display FSP Version Info HOB
562 12:44:02.837871 Reference Code - CPU = a.0.4c.31
563 12:44:02.841351 uCode Version = 0.0.0.86
564 12:44:02.844279 TXT ACM version = ff.ff.ff.ffff
565 12:44:02.847430 Reference Code - ME = a.0.4c.31
566 12:44:02.850715 MEBx version = 0.0.0.0
567 12:44:02.854263 ME Firmware Version = Consumer SKU
568 12:44:02.857638 Reference Code - PCH = a.0.4c.31
569 12:44:02.860590 PCH-CRID Status = Disabled
570 12:44:02.864160 PCH-CRID Original Value = ff.ff.ff.ffff
571 12:44:02.867213 PCH-CRID New Value = ff.ff.ff.ffff
572 12:44:02.870784 OPROM - RST - RAID = ff.ff.ff.ffff
573 12:44:02.873748 PCH Hsio Version = 4.0.0.0
574 12:44:02.877323 Reference Code - SA - System Agent = a.0.4c.31
575 12:44:02.880933 Reference Code - MRC = 2.0.0.1
576 12:44:02.883457 SA - PCIe Version = a.0.4c.31
577 12:44:02.886744 SA-CRID Status = Disabled
578 12:44:02.890152 SA-CRID Original Value = 0.0.0.1
579 12:44:02.893899 SA-CRID New Value = 0.0.0.1
580 12:44:02.896899 OPROM - VBIOS = ff.ff.ff.ffff
581 12:44:02.900610 IO Manageability Engine FW Version = 11.1.4.0
582 12:44:02.903930 PHY Build Version = 0.0.0.e0
583 12:44:02.907986 Thunderbolt(TM) FW Version = 0.0.0.0
584 12:44:02.914871 System Agent Manageability Engine FW Version = ff.ff.ff.ffff
585 12:44:02.915383 ITSS IRQ Polarities Before:
586 12:44:02.918260 IPC0: 0xffffffff
587 12:44:02.922017 IPC1: 0xffffffff
588 12:44:02.922546 IPC2: 0xffffffff
589 12:44:02.925243 IPC3: 0xffffffff
590 12:44:02.925764 ITSS IRQ Polarities After:
591 12:44:02.928270 IPC0: 0xffffffff
592 12:44:02.932220 IPC1: 0xffffffff
593 12:44:02.932742 IPC2: 0xffffffff
594 12:44:02.934884 IPC3: 0xffffffff
595 12:44:02.937873 Found PCIe Root Port #9 at PCI: 00:1d.0.
596 12:44:02.948127 pcie_rp_update_dev: Couldn't find PCIe Root Port #1 (originally PCI: 00:1c.0) which was enabled in devicetree, removing.
597 12:44:02.961226 pcie_rp_update_dev: Couldn't find PCIe Root Port #7 (originally PCI: 00:1c.6) which was enabled in devicetree, removing.
598 12:44:02.974465 pcie_rp_update_dev: Couldn't find PCIe Root Port #11 (originally PCI: 00:1d.2) which was enabled in devicetree, removing.
599 12:44:02.980960 BS: BS_DEV_INIT_CHIPS run times (exec / console): 290 / 236 ms
600 12:44:02.981386 Enumerating buses...
601 12:44:02.987546 Show all devs... Before device enumeration.
602 12:44:02.988124 Root Device: enabled 1
603 12:44:02.991178 DOMAIN: 0000: enabled 1
604 12:44:02.994720 CPU_CLUSTER: 0: enabled 1
605 12:44:02.997991 PCI: 00:00.0: enabled 1
606 12:44:02.998513 PCI: 00:02.0: enabled 1
607 12:44:03.000710 PCI: 00:04.0: enabled 1
608 12:44:03.003920 PCI: 00:05.0: enabled 1
609 12:44:03.007010 PCI: 00:06.0: enabled 0
610 12:44:03.007624 PCI: 00:07.0: enabled 0
611 12:44:03.010750 PCI: 00:07.1: enabled 0
612 12:44:03.013530 PCI: 00:07.2: enabled 0
613 12:44:03.016862 PCI: 00:07.3: enabled 0
614 12:44:03.017289 PCI: 00:08.0: enabled 1
615 12:44:03.019960 PCI: 00:09.0: enabled 0
616 12:44:03.023346 PCI: 00:0a.0: enabled 0
617 12:44:03.026904 PCI: 00:0d.0: enabled 1
618 12:44:03.027613 PCI: 00:0d.1: enabled 0
619 12:44:03.030326 PCI: 00:0d.2: enabled 0
620 12:44:03.033308 PCI: 00:0d.3: enabled 0
621 12:44:03.036265 PCI: 00:0e.0: enabled 0
622 12:44:03.036568 PCI: 00:10.2: enabled 1
623 12:44:03.039723 PCI: 00:10.6: enabled 0
624 12:44:03.043072 PCI: 00:10.7: enabled 0
625 12:44:03.046919 PCI: 00:12.0: enabled 0
626 12:44:03.047313 PCI: 00:12.6: enabled 0
627 12:44:03.050026 PCI: 00:13.0: enabled 0
628 12:44:03.053006 PCI: 00:14.0: enabled 1
629 12:44:03.056566 PCI: 00:14.1: enabled 0
630 12:44:03.056867 PCI: 00:14.2: enabled 1
631 12:44:03.060016 PCI: 00:14.3: enabled 1
632 12:44:03.063205 PCI: 00:15.0: enabled 1
633 12:44:03.066647 PCI: 00:15.1: enabled 1
634 12:44:03.067041 PCI: 00:15.2: enabled 1
635 12:44:03.069019 PCI: 00:15.3: enabled 1
636 12:44:03.072582 PCI: 00:16.0: enabled 1
637 12:44:03.075811 PCI: 00:16.1: enabled 0
638 12:44:03.076148 PCI: 00:16.2: enabled 0
639 12:44:03.079869 PCI: 00:16.3: enabled 0
640 12:44:03.082498 PCI: 00:16.4: enabled 0
641 12:44:03.082893 PCI: 00:16.5: enabled 0
642 12:44:03.086320 PCI: 00:17.0: enabled 1
643 12:44:03.089424 PCI: 00:19.0: enabled 0
644 12:44:03.092580 PCI: 00:19.1: enabled 1
645 12:44:03.092971 PCI: 00:19.2: enabled 0
646 12:44:03.096146 PCI: 00:1c.0: enabled 1
647 12:44:03.099355 PCI: 00:1c.1: enabled 0
648 12:44:03.102836 PCI: 00:1c.2: enabled 0
649 12:44:03.103324 PCI: 00:1c.3: enabled 0
650 12:44:03.105737 PCI: 00:1c.4: enabled 0
651 12:44:03.109332 PCI: 00:1c.5: enabled 0
652 12:44:03.112725 PCI: 00:1c.6: enabled 1
653 12:44:03.113225 PCI: 00:1c.7: enabled 0
654 12:44:03.115416 PCI: 00:1d.0: enabled 1
655 12:44:03.118663 PCI: 00:1d.1: enabled 0
656 12:44:03.121769 PCI: 00:1d.2: enabled 1
657 12:44:03.122158 PCI: 00:1d.3: enabled 0
658 12:44:03.125500 PCI: 00:1e.0: enabled 1
659 12:44:03.128621 PCI: 00:1e.1: enabled 0
660 12:44:03.131944 PCI: 00:1e.2: enabled 1
661 12:44:03.132485 PCI: 00:1e.3: enabled 1
662 12:44:03.135669 PCI: 00:1f.0: enabled 1
663 12:44:03.138573 PCI: 00:1f.1: enabled 0
664 12:44:03.141784 PCI: 00:1f.2: enabled 1
665 12:44:03.142286 PCI: 00:1f.3: enabled 1
666 12:44:03.145151 PCI: 00:1f.4: enabled 0
667 12:44:03.148457 PCI: 00:1f.5: enabled 1
668 12:44:03.152142 PCI: 00:1f.6: enabled 0
669 12:44:03.152632 PCI: 00:1f.7: enabled 0
670 12:44:03.155352 APIC: 00: enabled 1
671 12:44:03.158392 GENERIC: 0.0: enabled 1
672 12:44:03.158884 GENERIC: 0.0: enabled 1
673 12:44:03.161521 GENERIC: 1.0: enabled 1
674 12:44:03.164665 GENERIC: 0.0: enabled 1
675 12:44:03.168116 GENERIC: 1.0: enabled 1
676 12:44:03.168590 USB0 port 0: enabled 1
677 12:44:03.171807 GENERIC: 0.0: enabled 1
678 12:44:03.175033 USB0 port 0: enabled 1
679 12:44:03.178564 GENERIC: 0.0: enabled 1
680 12:44:03.179055 I2C: 00:1a: enabled 1
681 12:44:03.181348 I2C: 00:31: enabled 1
682 12:44:03.184705 I2C: 00:32: enabled 1
683 12:44:03.185246 I2C: 00:10: enabled 1
684 12:44:03.188029 I2C: 00:15: enabled 1
685 12:44:03.191192 GENERIC: 0.0: enabled 0
686 12:44:03.191584 GENERIC: 1.0: enabled 0
687 12:44:03.194856 GENERIC: 0.0: enabled 1
688 12:44:03.197893 SPI: 00: enabled 1
689 12:44:03.198383 SPI: 00: enabled 1
690 12:44:03.200762 PNP: 0c09.0: enabled 1
691 12:44:03.204377 GENERIC: 0.0: enabled 1
692 12:44:03.204768 USB3 port 0: enabled 1
693 12:44:03.208351 USB3 port 1: enabled 1
694 12:44:03.211327 USB3 port 2: enabled 0
695 12:44:03.214255 USB3 port 3: enabled 0
696 12:44:03.214648 USB2 port 0: enabled 0
697 12:44:03.217831 USB2 port 1: enabled 1
698 12:44:03.220874 USB2 port 2: enabled 1
699 12:44:03.221379 USB2 port 3: enabled 0
700 12:44:03.224313 USB2 port 4: enabled 1
701 12:44:03.228003 USB2 port 5: enabled 0
702 12:44:03.231202 USB2 port 6: enabled 0
703 12:44:03.231692 USB2 port 7: enabled 0
704 12:44:03.234503 USB2 port 8: enabled 0
705 12:44:03.237231 USB2 port 9: enabled 0
706 12:44:03.237628 USB3 port 0: enabled 0
707 12:44:03.240273 USB3 port 1: enabled 1
708 12:44:03.243857 USB3 port 2: enabled 0
709 12:44:03.246980 USB3 port 3: enabled 0
710 12:44:03.247473 GENERIC: 0.0: enabled 1
711 12:44:03.250504 GENERIC: 1.0: enabled 1
712 12:44:03.253566 APIC: 01: enabled 1
713 12:44:03.253958 APIC: 07: enabled 1
714 12:44:03.256832 APIC: 03: enabled 1
715 12:44:03.260498 APIC: 04: enabled 1
716 12:44:03.260985 APIC: 06: enabled 1
717 12:44:03.263560 APIC: 02: enabled 1
718 12:44:03.267031 APIC: 05: enabled 1
719 12:44:03.267525 Compare with tree...
720 12:44:03.270169 Root Device: enabled 1
721 12:44:03.273646 DOMAIN: 0000: enabled 1
722 12:44:03.274137 PCI: 00:00.0: enabled 1
723 12:44:03.276250 PCI: 00:02.0: enabled 1
724 12:44:03.279583 PCI: 00:04.0: enabled 1
725 12:44:03.283553 GENERIC: 0.0: enabled 1
726 12:44:03.286888 PCI: 00:05.0: enabled 1
727 12:44:03.287382 PCI: 00:06.0: enabled 0
728 12:44:03.289832 PCI: 00:07.0: enabled 0
729 12:44:03.292857 GENERIC: 0.0: enabled 1
730 12:44:03.296656 PCI: 00:07.1: enabled 0
731 12:44:03.299901 GENERIC: 1.0: enabled 1
732 12:44:03.303018 PCI: 00:07.2: enabled 0
733 12:44:03.303507 GENERIC: 0.0: enabled 1
734 12:44:03.306401 PCI: 00:07.3: enabled 0
735 12:44:03.309601 GENERIC: 1.0: enabled 1
736 12:44:03.312952 PCI: 00:08.0: enabled 1
737 12:44:03.315976 PCI: 00:09.0: enabled 0
738 12:44:03.316389 PCI: 00:0a.0: enabled 0
739 12:44:03.319364 PCI: 00:0d.0: enabled 1
740 12:44:03.322924 USB0 port 0: enabled 1
741 12:44:03.326053 USB3 port 0: enabled 1
742 12:44:03.329456 USB3 port 1: enabled 1
743 12:44:03.329951 USB3 port 2: enabled 0
744 12:44:03.332774 USB3 port 3: enabled 0
745 12:44:03.336050 PCI: 00:0d.1: enabled 0
746 12:44:03.339471 PCI: 00:0d.2: enabled 0
747 12:44:03.342711 GENERIC: 0.0: enabled 1
748 12:44:03.346463 PCI: 00:0d.3: enabled 0
749 12:44:03.346966 PCI: 00:0e.0: enabled 0
750 12:44:03.349299 PCI: 00:10.2: enabled 1
751 12:44:03.352570 PCI: 00:10.6: enabled 0
752 12:44:03.356119 PCI: 00:10.7: enabled 0
753 12:44:03.359305 PCI: 00:12.0: enabled 0
754 12:44:03.359793 PCI: 00:12.6: enabled 0
755 12:44:03.362206 PCI: 00:13.0: enabled 0
756 12:44:03.365694 PCI: 00:14.0: enabled 1
757 12:44:03.368738 USB0 port 0: enabled 1
758 12:44:03.372313 USB2 port 0: enabled 0
759 12:44:03.372806 USB2 port 1: enabled 1
760 12:44:03.375802 USB2 port 2: enabled 1
761 12:44:03.378909 USB2 port 3: enabled 0
762 12:44:03.381923 USB2 port 4: enabled 1
763 12:44:03.385684 USB2 port 5: enabled 0
764 12:44:03.388648 USB2 port 6: enabled 0
765 12:44:03.389141 USB2 port 7: enabled 0
766 12:44:03.392081 USB2 port 8: enabled 0
767 12:44:03.395367 USB2 port 9: enabled 0
768 12:44:03.398466 USB3 port 0: enabled 0
769 12:44:03.401771 USB3 port 1: enabled 1
770 12:44:03.404654 USB3 port 2: enabled 0
771 12:44:03.405044 USB3 port 3: enabled 0
772 12:44:03.408569 PCI: 00:14.1: enabled 0
773 12:44:03.411664 PCI: 00:14.2: enabled 1
774 12:44:03.414534 PCI: 00:14.3: enabled 1
775 12:44:03.418003 GENERIC: 0.0: enabled 1
776 12:44:03.418490 PCI: 00:15.0: enabled 1
777 12:44:03.421803 I2C: 00:1a: enabled 1
778 12:44:03.424861 I2C: 00:31: enabled 1
779 12:44:03.428008 I2C: 00:32: enabled 1
780 12:44:03.431641 PCI: 00:15.1: enabled 1
781 12:44:03.432174 I2C: 00:10: enabled 1
782 12:44:03.435066 PCI: 00:15.2: enabled 1
783 12:44:03.437806 PCI: 00:15.3: enabled 1
784 12:44:03.441290 PCI: 00:16.0: enabled 1
785 12:44:03.441679 PCI: 00:16.1: enabled 0
786 12:44:03.444147 PCI: 00:16.2: enabled 0
787 12:44:03.447479 PCI: 00:16.3: enabled 0
788 12:44:03.450908 PCI: 00:16.4: enabled 0
789 12:44:03.454143 PCI: 00:16.5: enabled 0
790 12:44:03.457337 PCI: 00:17.0: enabled 1
791 12:44:03.457728 PCI: 00:19.0: enabled 0
792 12:44:03.460944 PCI: 00:19.1: enabled 1
793 12:44:03.463978 I2C: 00:15: enabled 1
794 12:44:03.467308 PCI: 00:19.2: enabled 0
795 12:44:03.467710 PCI: 00:1d.0: enabled 1
796 12:44:03.471110 GENERIC: 0.0: enabled 1
797 12:44:03.474315 PCI: 00:1e.0: enabled 1
798 12:44:03.478154 PCI: 00:1e.1: enabled 0
799 12:44:03.480316 PCI: 00:1e.2: enabled 1
800 12:44:03.480751 SPI: 00: enabled 1
801 12:44:03.484268 PCI: 00:1e.3: enabled 1
802 12:44:03.487957 SPI: 00: enabled 1
803 12:44:03.490786 PCI: 00:1f.0: enabled 1
804 12:44:03.491425 PNP: 0c09.0: enabled 1
805 12:44:03.493976 PCI: 00:1f.1: enabled 0
806 12:44:03.497436 PCI: 00:1f.2: enabled 1
807 12:44:03.500275 GENERIC: 0.0: enabled 1
808 12:44:03.538822 GENERIC: 0.0: enabled 1
809 12:44:03.539375 GENERIC: 1.0: enabled 1
810 12:44:03.539723 PCI: 00:1f.3: enabled 1
811 12:44:03.540037 PCI: 00:1f.4: enabled 0
812 12:44:03.540602 PCI: 00:1f.5: enabled 1
813 12:44:03.541363 PCI: 00:1f.6: enabled 0
814 12:44:03.541702 PCI: 00:1f.7: enabled 0
815 12:44:03.542009 CPU_CLUSTER: 0: enabled 1
816 12:44:03.542305 APIC: 00: enabled 1
817 12:44:03.542596 APIC: 01: enabled 1
818 12:44:03.542879 APIC: 07: enabled 1
819 12:44:03.543159 APIC: 03: enabled 1
820 12:44:03.543472 APIC: 04: enabled 1
821 12:44:03.543760 APIC: 06: enabled 1
822 12:44:03.544041 APIC: 02: enabled 1
823 12:44:03.544383 APIC: 05: enabled 1
824 12:44:03.545196 Root Device scanning...
825 12:44:03.548291 scan_static_bus for Root Device
826 12:44:03.548714 DOMAIN: 0000 enabled
827 12:44:03.552102 CPU_CLUSTER: 0 enabled
828 12:44:03.555268 DOMAIN: 0000 scanning...
829 12:44:03.558081 PCI: pci_scan_bus for bus 00
830 12:44:03.561793 PCI: 00:00.0 [8086/0000] ops
831 12:44:03.565038 PCI: 00:00.0 [8086/9a12] enabled
832 12:44:03.568225 PCI: 00:02.0 [8086/0000] bus ops
833 12:44:03.571938 PCI: 00:02.0 [8086/9a40] enabled
834 12:44:03.575877 PCI: 00:04.0 [8086/0000] bus ops
835 12:44:03.576447 PCI: 00:04.0 [8086/9a03] enabled
836 12:44:03.579553 PCI: 00:05.0 [8086/9a19] enabled
837 12:44:03.582416 PCI: 00:07.0 [0000/0000] hidden
838 12:44:03.585899 PCI: 00:08.0 [8086/9a11] enabled
839 12:44:03.589421 PCI: 00:0a.0 [8086/9a0d] disabled
840 12:44:03.592764 PCI: 00:0d.0 [8086/0000] bus ops
841 12:44:03.596115 PCI: 00:0d.0 [8086/9a13] enabled
842 12:44:03.599524 PCI: 00:14.0 [8086/0000] bus ops
843 12:44:03.602429 PCI: 00:14.0 [8086/a0ed] enabled
844 12:44:03.605005 PCI: 00:14.2 [8086/a0ef] enabled
845 12:44:03.608426 PCI: 00:14.3 [8086/0000] bus ops
846 12:44:03.611669 PCI: 00:14.3 [8086/a0f0] enabled
847 12:44:03.614832 PCI: 00:15.0 [8086/0000] bus ops
848 12:44:03.618440 PCI: 00:15.0 [8086/a0e8] enabled
849 12:44:03.622189 PCI: 00:15.1 [8086/0000] bus ops
850 12:44:03.625160 PCI: 00:15.1 [8086/a0e9] enabled
851 12:44:03.628010 PCI: 00:15.2 [8086/0000] bus ops
852 12:44:03.631705 PCI: 00:15.2 [8086/a0ea] enabled
853 12:44:03.638307 PCI: 00:15.3 [8086/0000] bus ops
854 12:44:03.641335 PCI: 00:15.3 [8086/a0eb] enabled
855 12:44:03.641530 PCI: 00:16.0 [8086/0000] ops
856 12:44:03.644385 PCI: 00:16.0 [8086/a0e0] enabled
857 12:44:03.651794 PCI: Static device PCI: 00:17.0 not found, disabling it.
858 12:44:03.654995 PCI: 00:19.0 [8086/0000] bus ops
859 12:44:03.658286 PCI: 00:19.0 [8086/a0c5] disabled
860 12:44:03.661416 PCI: 00:19.1 [8086/0000] bus ops
861 12:44:03.664543 PCI: 00:19.1 [8086/a0c6] enabled
862 12:44:03.667861 PCI: 00:1d.0 [8086/0000] bus ops
863 12:44:03.671008 PCI: 00:1d.0 [8086/a0b0] enabled
864 12:44:03.674591 PCI: 00:1e.0 [8086/0000] ops
865 12:44:03.677772 PCI: 00:1e.0 [8086/a0a8] enabled
866 12:44:03.681545 PCI: 00:1e.2 [8086/0000] bus ops
867 12:44:03.684259 PCI: 00:1e.2 [8086/a0aa] enabled
868 12:44:03.688200 PCI: 00:1e.3 [8086/0000] bus ops
869 12:44:03.691347 PCI: 00:1e.3 [8086/a0ab] enabled
870 12:44:03.694206 PCI: 00:1f.0 [8086/0000] bus ops
871 12:44:03.697934 PCI: 00:1f.0 [8086/a087] enabled
872 12:44:03.701018 RTC Init
873 12:44:03.704695 Set power on after power failure.
874 12:44:03.705233 Disabling Deep S3
875 12:44:03.707620 Disabling Deep S3
876 12:44:03.708188 Disabling Deep S4
877 12:44:03.710739 Disabling Deep S4
878 12:44:03.713673 Disabling Deep S5
879 12:44:03.714095 Disabling Deep S5
880 12:44:03.717010 PCI: 00:1f.2 [0000/0000] hidden
881 12:44:03.720337 PCI: 00:1f.3 [8086/0000] bus ops
882 12:44:03.723562 PCI: 00:1f.3 [8086/a0c8] enabled
883 12:44:03.727223 PCI: 00:1f.5 [8086/0000] bus ops
884 12:44:03.730307 PCI: 00:1f.5 [8086/a0a4] enabled
885 12:44:03.733296 PCI: Leftover static devices:
886 12:44:03.737496 PCI: 00:10.2
887 12:44:03.738029 PCI: 00:10.6
888 12:44:03.738364 PCI: 00:10.7
889 12:44:03.740347 PCI: 00:06.0
890 12:44:03.740771 PCI: 00:07.1
891 12:44:03.743769 PCI: 00:07.2
892 12:44:03.744393 PCI: 00:07.3
893 12:44:03.744741 PCI: 00:09.0
894 12:44:03.746943 PCI: 00:0d.1
895 12:44:03.747372 PCI: 00:0d.2
896 12:44:03.749894 PCI: 00:0d.3
897 12:44:03.750323 PCI: 00:0e.0
898 12:44:03.753032 PCI: 00:12.0
899 12:44:03.753461 PCI: 00:12.6
900 12:44:03.753796 PCI: 00:13.0
901 12:44:03.756641 PCI: 00:14.1
902 12:44:03.757191 PCI: 00:16.1
903 12:44:03.759857 PCI: 00:16.2
904 12:44:03.760340 PCI: 00:16.3
905 12:44:03.760680 PCI: 00:16.4
906 12:44:03.763099 PCI: 00:16.5
907 12:44:03.763523 PCI: 00:17.0
908 12:44:03.766195 PCI: 00:19.2
909 12:44:03.766619 PCI: 00:1e.1
910 12:44:03.769941 PCI: 00:1f.1
911 12:44:03.770366 PCI: 00:1f.4
912 12:44:03.770706 PCI: 00:1f.6
913 12:44:03.772993 PCI: 00:1f.7
914 12:44:03.776427 PCI: Check your devicetree.cb.
915 12:44:03.779745 PCI: 00:02.0 scanning...
916 12:44:03.783008 scan_generic_bus for PCI: 00:02.0
917 12:44:03.786827 scan_generic_bus for PCI: 00:02.0 done
918 12:44:03.790014 scan_bus: bus PCI: 00:02.0 finished in 7 msecs
919 12:44:03.792715 PCI: 00:04.0 scanning...
920 12:44:03.796433 scan_generic_bus for PCI: 00:04.0
921 12:44:03.799579 GENERIC: 0.0 enabled
922 12:44:03.805804 bus: PCI: 00:04.0[0]->scan_generic_bus for PCI: 00:04.0 done
923 12:44:03.809474 scan_bus: bus PCI: 00:04.0 finished in 11 msecs
924 12:44:03.812648 PCI: 00:0d.0 scanning...
925 12:44:03.815510 scan_static_bus for PCI: 00:0d.0
926 12:44:03.819477 USB0 port 0 enabled
927 12:44:03.819998 USB0 port 0 scanning...
928 12:44:03.822882 scan_static_bus for USB0 port 0
929 12:44:03.826092 USB3 port 0 enabled
930 12:44:03.829227 USB3 port 1 enabled
931 12:44:03.829746 USB3 port 2 disabled
932 12:44:03.832843 USB3 port 3 disabled
933 12:44:03.835822 USB3 port 0 scanning...
934 12:44:03.838755 scan_static_bus for USB3 port 0
935 12:44:03.842160 scan_static_bus for USB3 port 0 done
936 12:44:03.845593 scan_bus: bus USB3 port 0 finished in 6 msecs
937 12:44:03.848515 USB3 port 1 scanning...
938 12:44:03.852143 scan_static_bus for USB3 port 1
939 12:44:03.855531 scan_static_bus for USB3 port 1 done
940 12:44:03.861618 scan_bus: bus USB3 port 1 finished in 6 msecs
941 12:44:03.864816 scan_static_bus for USB0 port 0 done
942 12:44:03.867997 scan_bus: bus USB0 port 0 finished in 43 msecs
943 12:44:03.871773 scan_static_bus for PCI: 00:0d.0 done
944 12:44:03.878110 scan_bus: bus PCI: 00:0d.0 finished in 60 msecs
945 12:44:03.881767 PCI: 00:14.0 scanning...
946 12:44:03.884316 scan_static_bus for PCI: 00:14.0
947 12:44:03.884745 USB0 port 0 enabled
948 12:44:03.887532 USB0 port 0 scanning...
949 12:44:03.891057 scan_static_bus for USB0 port 0
950 12:44:03.894246 USB2 port 0 disabled
951 12:44:03.894670 USB2 port 1 enabled
952 12:44:03.897969 USB2 port 2 enabled
953 12:44:03.900641 USB2 port 3 disabled
954 12:44:03.901064 USB2 port 4 enabled
955 12:44:03.904280 USB2 port 5 disabled
956 12:44:03.907546 USB2 port 6 disabled
957 12:44:03.908111 USB2 port 7 disabled
958 12:44:03.911025 USB2 port 8 disabled
959 12:44:03.914410 USB2 port 9 disabled
960 12:44:03.914930 USB3 port 0 disabled
961 12:44:03.916826 USB3 port 1 enabled
962 12:44:03.920593 USB3 port 2 disabled
963 12:44:03.921111 USB3 port 3 disabled
964 12:44:03.923709 USB2 port 1 scanning...
965 12:44:03.927104 scan_static_bus for USB2 port 1
966 12:44:03.930954 scan_static_bus for USB2 port 1 done
967 12:44:03.936657 scan_bus: bus USB2 port 1 finished in 6 msecs
968 12:44:03.937175 USB2 port 2 scanning...
969 12:44:03.940171 scan_static_bus for USB2 port 2
970 12:44:03.942951 scan_static_bus for USB2 port 2 done
971 12:44:03.950120 scan_bus: bus USB2 port 2 finished in 6 msecs
972 12:44:03.953239 USB2 port 4 scanning...
973 12:44:03.956678 scan_static_bus for USB2 port 4
974 12:44:03.960167 scan_static_bus for USB2 port 4 done
975 12:44:03.962959 scan_bus: bus USB2 port 4 finished in 6 msecs
976 12:44:03.966613 USB3 port 1 scanning...
977 12:44:03.969465 scan_static_bus for USB3 port 1
978 12:44:03.972778 scan_static_bus for USB3 port 1 done
979 12:44:03.979669 scan_bus: bus USB3 port 1 finished in 6 msecs
980 12:44:03.982500 scan_static_bus for USB0 port 0 done
981 12:44:03.986048 scan_bus: bus USB0 port 0 finished in 93 msecs
982 12:44:03.989025 scan_static_bus for PCI: 00:14.0 done
983 12:44:03.995865 scan_bus: bus PCI: 00:14.0 finished in 109 msecs
984 12:44:03.998981 PCI: 00:14.3 scanning...
985 12:44:04.002286 scan_static_bus for PCI: 00:14.3
986 12:44:04.002711 GENERIC: 0.0 enabled
987 12:44:04.005140 scan_static_bus for PCI: 00:14.3 done
988 12:44:04.011996 scan_bus: bus PCI: 00:14.3 finished in 9 msecs
989 12:44:04.015721 PCI: 00:15.0 scanning...
990 12:44:04.019013 scan_static_bus for PCI: 00:15.0
991 12:44:04.019549 I2C: 00:1a enabled
992 12:44:04.022360 I2C: 00:31 enabled
993 12:44:04.025639 I2C: 00:32 enabled
994 12:44:04.028660 scan_static_bus for PCI: 00:15.0 done
995 12:44:04.031894 scan_bus: bus PCI: 00:15.0 finished in 12 msecs
996 12:44:04.035177 PCI: 00:15.1 scanning...
997 12:44:04.038577 scan_static_bus for PCI: 00:15.1
998 12:44:04.041908 I2C: 00:10 enabled
999 12:44:04.044836 scan_static_bus for PCI: 00:15.1 done
1000 12:44:04.048269 scan_bus: bus PCI: 00:15.1 finished in 9 msecs
1001 12:44:04.051005 PCI: 00:15.2 scanning...
1002 12:44:04.054477 scan_static_bus for PCI: 00:15.2
1003 12:44:04.057778 scan_static_bus for PCI: 00:15.2 done
1004 12:44:04.064731 scan_bus: bus PCI: 00:15.2 finished in 7 msecs
1005 12:44:04.065260 PCI: 00:15.3 scanning...
1006 12:44:04.067885 scan_static_bus for PCI: 00:15.3
1007 12:44:04.074656 scan_static_bus for PCI: 00:15.3 done
1008 12:44:04.077447 scan_bus: bus PCI: 00:15.3 finished in 7 msecs
1009 12:44:04.080950 PCI: 00:19.1 scanning...
1010 12:44:04.084006 scan_static_bus for PCI: 00:19.1
1011 12:44:04.087754 I2C: 00:15 enabled
1012 12:44:04.091416 scan_static_bus for PCI: 00:19.1 done
1013 12:44:04.094148 scan_bus: bus PCI: 00:19.1 finished in 9 msecs
1014 12:44:04.096917 PCI: 00:1d.0 scanning...
1015 12:44:04.101010 do_pci_scan_bridge for PCI: 00:1d.0
1016 12:44:04.104257 PCI: pci_scan_bus for bus 01
1017 12:44:04.107186 PCI: 01:00.0 [15b7/5009] enabled
1018 12:44:04.110955 GENERIC: 0.0 enabled
1019 12:44:04.113557 Enabling Common Clock Configuration
1020 12:44:04.117423 L1 Sub-State supported from root port 29
1021 12:44:04.120461 L1 Sub-State Support = 0x5
1022 12:44:04.123958 CommonModeRestoreTime = 0x28
1023 12:44:04.127138 Power On Value = 0x16, Power On Scale = 0x0
1024 12:44:04.130153 ASPM: Enabled L1
1025 12:44:04.133684 PCIe: Max_Payload_Size adjusted to 128
1026 12:44:04.136984 scan_bus: bus PCI: 00:1d.0 finished in 35 msecs
1027 12:44:04.140169 PCI: 00:1e.2 scanning...
1028 12:44:04.143037 scan_generic_bus for PCI: 00:1e.2
1029 12:44:04.146931 SPI: 00 enabled
1030 12:44:04.153869 bus: PCI: 00:1e.2[0]->scan_generic_bus for PCI: 00:1e.2 done
1031 12:44:04.156754 scan_bus: bus PCI: 00:1e.2 finished in 11 msecs
1032 12:44:04.159936 PCI: 00:1e.3 scanning...
1033 12:44:04.163728 scan_generic_bus for PCI: 00:1e.3
1034 12:44:04.164288 SPI: 00 enabled
1035 12:44:04.170215 bus: PCI: 00:1e.3[0]->scan_generic_bus for PCI: 00:1e.3 done
1036 12:44:04.176687 scan_bus: bus PCI: 00:1e.3 finished in 11 msecs
1037 12:44:04.177203 PCI: 00:1f.0 scanning...
1038 12:44:04.180105 scan_static_bus for PCI: 00:1f.0
1039 12:44:04.183415 PNP: 0c09.0 enabled
1040 12:44:04.186896 PNP: 0c09.0 scanning...
1041 12:44:04.190256 scan_static_bus for PNP: 0c09.0
1042 12:44:04.192935 scan_static_bus for PNP: 0c09.0 done
1043 12:44:04.195970 scan_bus: bus PNP: 0c09.0 finished in 6 msecs
1044 12:44:04.203293 scan_static_bus for PCI: 00:1f.0 done
1045 12:44:04.206304 scan_bus: bus PCI: 00:1f.0 finished in 23 msecs
1046 12:44:04.209728 PCI: 00:1f.2 scanning...
1047 12:44:04.212686 scan_static_bus for PCI: 00:1f.2
1048 12:44:04.213206 GENERIC: 0.0 enabled
1049 12:44:04.216029 GENERIC: 0.0 scanning...
1050 12:44:04.219588 scan_static_bus for GENERIC: 0.0
1051 12:44:04.222728 GENERIC: 0.0 enabled
1052 12:44:04.225966 GENERIC: 1.0 enabled
1053 12:44:04.229593 scan_static_bus for GENERIC: 0.0 done
1054 12:44:04.232747 scan_bus: bus GENERIC: 0.0 finished in 11 msecs
1055 12:44:04.235701 scan_static_bus for PCI: 00:1f.2 done
1056 12:44:04.242690 scan_bus: bus PCI: 00:1f.2 finished in 28 msecs
1057 12:44:04.245573 PCI: 00:1f.3 scanning...
1058 12:44:04.248802 scan_static_bus for PCI: 00:1f.3
1059 12:44:04.252170 scan_static_bus for PCI: 00:1f.3 done
1060 12:44:04.255746 scan_bus: bus PCI: 00:1f.3 finished in 7 msecs
1061 12:44:04.259077 PCI: 00:1f.5 scanning...
1062 12:44:04.262175 scan_generic_bus for PCI: 00:1f.5
1063 12:44:04.265580 scan_generic_bus for PCI: 00:1f.5 done
1064 12:44:04.272306 scan_bus: bus PCI: 00:1f.5 finished in 7 msecs
1065 12:44:04.275158 scan_bus: bus DOMAIN: 0000 finished in 716 msecs
1066 12:44:04.278887 scan_static_bus for Root Device done
1067 12:44:04.285104 scan_bus: bus Root Device finished in 736 msecs
1068 12:44:04.285612 done
1069 12:44:04.291795 BS: BS_DEV_ENUMERATE run times (exec / console): 10 / 1295 ms
1070 12:44:04.294972 Chrome EC: UHEPI supported
1071 12:44:04.301390 FMAP: area UNIFIED_MRC_CACHE found @ f00000 (196608 bytes)
1072 12:44:04.307854 SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
1073 12:44:04.311498 SPI flash protection: WPSW=0 SRP0=0
1074 12:44:04.314909 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
1075 12:44:04.321013 BS: BS_DEV_ENUMERATE exit times (exec / console): 2 / 23 ms
1076 12:44:04.324728 found VGA at PCI: 00:02.0
1077 12:44:04.328301 Setting up VGA for PCI: 00:02.0
1078 12:44:04.334191 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
1079 12:44:04.337459 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
1080 12:44:04.340980 Allocating resources...
1081 12:44:04.344148 Reading resources...
1082 12:44:04.347845 Root Device read_resources bus 0 link: 0
1083 12:44:04.350873 DOMAIN: 0000 read_resources bus 0 link: 0
1084 12:44:04.356996 PCI: 00:04.0 read_resources bus 1 link: 0
1085 12:44:04.360236 PCI: 00:04.0 read_resources bus 1 link: 0 done
1086 12:44:04.367456 PCI: 00:0d.0 read_resources bus 0 link: 0
1087 12:44:04.370566 USB0 port 0 read_resources bus 0 link: 0
1088 12:44:04.377283 USB0 port 0 read_resources bus 0 link: 0 done
1089 12:44:04.380344 PCI: 00:0d.0 read_resources bus 0 link: 0 done
1090 12:44:04.386560 PCI: 00:14.0 read_resources bus 0 link: 0
1091 12:44:04.389963 USB0 port 0 read_resources bus 0 link: 0
1092 12:44:04.396592 USB0 port 0 read_resources bus 0 link: 0 done
1093 12:44:04.400237 PCI: 00:14.0 read_resources bus 0 link: 0 done
1094 12:44:04.406356 PCI: 00:14.3 read_resources bus 0 link: 0
1095 12:44:04.410007 PCI: 00:14.3 read_resources bus 0 link: 0 done
1096 12:44:04.416690 PCI: 00:15.0 read_resources bus 0 link: 0
1097 12:44:04.420231 PCI: 00:15.0 read_resources bus 0 link: 0 done
1098 12:44:04.426692 PCI: 00:15.1 read_resources bus 0 link: 0
1099 12:44:04.429791 PCI: 00:15.1 read_resources bus 0 link: 0 done
1100 12:44:04.436556 PCI: 00:19.1 read_resources bus 0 link: 0
1101 12:44:04.439649 PCI: 00:19.1 read_resources bus 0 link: 0 done
1102 12:44:04.445992 PCI: 00:1d.0 read_resources bus 1 link: 0
1103 12:44:04.449649 PCI: 00:1d.0 read_resources bus 1 link: 0 done
1104 12:44:04.456463 PCI: 00:1e.2 read_resources bus 2 link: 0
1105 12:44:04.459353 PCI: 00:1e.2 read_resources bus 2 link: 0 done
1106 12:44:04.466278 PCI: 00:1e.3 read_resources bus 3 link: 0
1107 12:44:04.469609 PCI: 00:1e.3 read_resources bus 3 link: 0 done
1108 12:44:04.476644 PCI: 00:1f.0 read_resources bus 0 link: 0
1109 12:44:04.479171 PCI: 00:1f.0 read_resources bus 0 link: 0 done
1110 12:44:04.485936 PCI: 00:1f.2 read_resources bus 0 link: 0
1111 12:44:04.488993 GENERIC: 0.0 read_resources bus 0 link: 0
1112 12:44:04.495455 GENERIC: 0.0 read_resources bus 0 link: 0 done
1113 12:44:04.498877 PCI: 00:1f.2 read_resources bus 0 link: 0 done
1114 12:44:04.505494 DOMAIN: 0000 read_resources bus 0 link: 0 done
1115 12:44:04.508769 CPU_CLUSTER: 0 read_resources bus 0 link: 0
1116 12:44:04.515218 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
1117 12:44:04.519091 Root Device read_resources bus 0 link: 0 done
1118 12:44:04.522386 Done reading resources.
1119 12:44:04.528461 Show resources in subtree (Root Device)...After reading.
1120 12:44:04.532216 Root Device child on link 0 DOMAIN: 0000
1121 12:44:04.535035 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1122 12:44:04.544692 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1123 12:44:04.554923 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100
1124 12:44:04.558441 PCI: 00:00.0
1125 12:44:04.567594 PCI: 00:00.0 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1126 12:44:04.574866 PCI: 00:00.0 resource base fedc0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1
1127 12:44:04.583950 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1128 12:44:04.593890 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1129 12:44:04.603684 PCI: 00:00.0 resource base fb000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1130 12:44:04.613729 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1131 12:44:04.623421 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 6
1132 12:44:04.633511 PCI: 00:00.0 resource base fed92000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1133 12:44:04.639975 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1134 12:44:04.649946 PCI: 00:00.0 resource base fed85000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9
1135 12:44:04.659812 PCI: 00:00.0 resource base fed86000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
1136 12:44:04.669954 PCI: 00:00.0 resource base fed87000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b
1137 12:44:04.679698 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c
1138 12:44:04.687007 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index d
1139 12:44:04.695987 PCI: 00:00.0 resource base c0000 size 76f40000 align 0 gran 0 limit 0 flags e0004200 index e
1140 12:44:04.706354 PCI: 00:00.0 resource base 77000000 size 8c00000 align 0 gran 0 limit 0 flags f0000200 index f
1141 12:44:04.716018 PCI: 00:00.0 resource base 100000000 size 380400000 align 0 gran 0 limit 0 flags e0004200 index 10
1142 12:44:04.725614 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11
1143 12:44:04.736157 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12
1144 12:44:04.745579 PCI: 00:00.0 resource base f8000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 13
1145 12:44:04.746097 PCI: 00:02.0
1146 12:44:04.758345 PCI: 00:02.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1147 12:44:04.768706 PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
1148 12:44:04.775350 PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
1149 12:44:04.782206 PCI: 00:04.0 child on link 0 GENERIC: 0.0
1150 12:44:04.791845 PCI: 00:04.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 201 index 10
1151 12:44:04.792416 GENERIC: 0.0
1152 12:44:04.795162 PCI: 00:05.0
1153 12:44:04.805131 PCI: 00:05.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1154 12:44:04.807632 PCI: 00:07.0 child on link 0 GENERIC: 0.0
1155 12:44:04.811422 GENERIC: 0.0
1156 12:44:04.811936 PCI: 00:08.0
1157 12:44:04.821388 PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1158 12:44:04.824644 PCI: 00:0a.0
1159 12:44:04.828244 PCI: 00:0d.0 child on link 0 USB0 port 0
1160 12:44:04.837820 PCI: 00:0d.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1161 12:44:04.841038 USB0 port 0 child on link 0 USB3 port 0
1162 12:44:04.844453 USB3 port 0
1163 12:44:04.847288 USB3 port 1
1164 12:44:04.847717 USB3 port 2
1165 12:44:04.850647 USB3 port 3
1166 12:44:04.854104 PCI: 00:14.0 child on link 0 USB0 port 0
1167 12:44:04.863928 PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1168 12:44:04.867347 USB0 port 0 child on link 0 USB2 port 0
1169 12:44:04.870730 USB2 port 0
1170 12:44:04.871294 USB2 port 1
1171 12:44:04.873984 USB2 port 2
1172 12:44:04.877243 USB2 port 3
1173 12:44:04.877767 USB2 port 4
1174 12:44:04.880757 USB2 port 5
1175 12:44:04.881277 USB2 port 6
1176 12:44:04.883979 USB2 port 7
1177 12:44:04.884577 USB2 port 8
1178 12:44:04.887311 USB2 port 9
1179 12:44:04.887864 USB3 port 0
1180 12:44:04.890709 USB3 port 1
1181 12:44:04.891228 USB3 port 2
1182 12:44:04.893530 USB3 port 3
1183 12:44:04.894046 PCI: 00:14.2
1184 12:44:04.903582 PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1185 12:44:04.913246 PCI: 00:14.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
1186 12:44:04.920519 PCI: 00:14.3 child on link 0 GENERIC: 0.0
1187 12:44:04.930335 PCI: 00:14.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1188 12:44:04.930858 GENERIC: 0.0
1189 12:44:04.936400 PCI: 00:15.0 child on link 0 I2C: 00:1a
1190 12:44:04.945841 PCI: 00:15.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1191 12:44:04.946379 I2C: 00:1a
1192 12:44:04.949079 I2C: 00:31
1193 12:44:04.949498 I2C: 00:32
1194 12:44:04.952482 PCI: 00:15.1 child on link 0 I2C: 00:10
1195 12:44:04.962462 PCI: 00:15.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1196 12:44:04.965508 I2C: 00:10
1197 12:44:04.965927 PCI: 00:15.2
1198 12:44:04.975836 PCI: 00:15.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1199 12:44:04.979121 PCI: 00:15.3
1200 12:44:04.989141 PCI: 00:15.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1201 12:44:04.992465 PCI: 00:16.0
1202 12:44:05.001993 PCI: 00:16.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1203 12:44:05.002515 PCI: 00:19.0
1204 12:44:05.005398 PCI: 00:19.1 child on link 0 I2C: 00:15
1205 12:44:05.015168 PCI: 00:19.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1206 12:44:05.018130 I2C: 00:15
1207 12:44:05.022074 PCI: 00:1d.0 child on link 0 GENERIC: 0.0
1208 12:44:05.031812 PCI: 00:1d.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
1209 12:44:05.041332 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
1210 12:44:05.051333 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
1211 12:44:05.051845 GENERIC: 0.0
1212 12:44:05.054523 PCI: 01:00.0
1213 12:44:05.064600 PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1214 12:44:05.074366 PCI: 01:00.0 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 20
1215 12:44:05.074891 PCI: 00:1e.0
1216 12:44:05.087353 PCI: 00:1e.0 resource base fe03e000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1217 12:44:05.090841 PCI: 00:1e.2 child on link 0 SPI: 00
1218 12:44:05.100707 PCI: 00:1e.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1219 12:44:05.101224 SPI: 00
1220 12:44:05.104011 PCI: 00:1e.3 child on link 0 SPI: 00
1221 12:44:05.114127 PCI: 00:1e.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1222 12:44:05.117042 SPI: 00
1223 12:44:05.120508 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1224 12:44:05.130812 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1225 12:44:05.131330 PNP: 0c09.0
1226 12:44:05.140437 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1227 12:44:05.143613 PCI: 00:1f.2 child on link 0 GENERIC: 0.0
1228 12:44:05.153503 PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0
1229 12:44:05.163202 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1
1230 12:44:05.166613 GENERIC: 0.0 child on link 0 GENERIC: 0.0
1231 12:44:05.169692 GENERIC: 0.0
1232 12:44:05.172834 GENERIC: 1.0
1233 12:44:05.173353 PCI: 00:1f.3
1234 12:44:05.183124 PCI: 00:1f.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1235 12:44:05.193108 PCI: 00:1f.3 resource base 0 size 100000 align 20 gran 20 limit ffffffffffffffff flags 201 index 20
1236 12:44:05.196223 PCI: 00:1f.5
1237 12:44:05.202796 PCI: 00:1f.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
1238 12:44:05.209473 CPU_CLUSTER: 0 child on link 0 APIC: 00
1239 12:44:05.209983 APIC: 00
1240 12:44:05.213008 APIC: 01
1241 12:44:05.213515 APIC: 07
1242 12:44:05.213852 APIC: 03
1243 12:44:05.216192 APIC: 04
1244 12:44:05.216707 APIC: 06
1245 12:44:05.217046 APIC: 02
1246 12:44:05.218938 APIC: 05
1247 12:44:05.225636 ==== Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) ===
1248 12:44:05.231993 PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff
1249 12:44:05.238751 PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff done
1250 12:44:05.245538 PCI: 00:1d.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
1251 12:44:05.248871 PCI: 01:00.0 10 * [0x0 - 0x3fff] mem
1252 12:44:05.251951 PCI: 01:00.0 20 * [0x4000 - 0x40ff] mem
1253 12:44:05.258678 PCI: 00:1d.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
1254 12:44:05.268600 PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
1255 12:44:05.274991 PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
1256 12:44:05.281629 === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
1257 12:44:05.287777 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
1258 12:44:05.295055 update_constraints: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
1259 12:44:05.304754 update_constraints: PNP: 0c09.0 00 base 00000800 limit 000009fe io (fixed)
1260 12:44:05.311548 update_constraints: PCI: 00:1f.2 01 base 00001800 limit 000018ff io (fixed)
1261 12:44:05.314795 DOMAIN: 0000: Resource ranges:
1262 12:44:05.318016 * Base: 1000, Size: 800, Tag: 100
1263 12:44:05.320848 * Base: 1900, Size: e700, Tag: 100
1264 12:44:05.327693 PCI: 00:02.0 20 * [0x1000 - 0x103f] limit: 103f io
1265 12:44:05.334499 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
1266 12:44:05.340621 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff
1267 12:44:05.347344 update_constraints: PCI: 00:00.0 00 base c0000000 limit cfffffff mem (fixed)
1268 12:44:05.353616 update_constraints: PCI: 00:00.0 01 base fedc0000 limit feddffff mem (fixed)
1269 12:44:05.363700 update_constraints: PCI: 00:00.0 02 base feda0000 limit feda0fff mem (fixed)
1270 12:44:05.369933 update_constraints: PCI: 00:00.0 03 base feda1000 limit feda1fff mem (fixed)
1271 12:44:05.380024 update_constraints: PCI: 00:00.0 04 base fb000000 limit fb000fff mem (fixed)
1272 12:44:05.386494 update_constraints: PCI: 00:00.0 05 base fed80000 limit fed83fff mem (fixed)
1273 12:44:05.393584 update_constraints: PCI: 00:00.0 06 base fed90000 limit fed90fff mem (fixed)
1274 12:44:05.403895 update_constraints: PCI: 00:00.0 07 base fed92000 limit fed92fff mem (fixed)
1275 12:44:05.409177 update_constraints: PCI: 00:00.0 08 base fed84000 limit fed84fff mem (fixed)
1276 12:44:05.416153 update_constraints: PCI: 00:00.0 09 base fed85000 limit fed85fff mem (fixed)
1277 12:44:05.426231 update_constraints: PCI: 00:00.0 0a base fed86000 limit fed86fff mem (fixed)
1278 12:44:05.432815 update_constraints: PCI: 00:00.0 0b base fed87000 limit fed87fff mem (fixed)
1279 12:44:05.439036 update_constraints: PCI: 00:00.0 0c base fed91000 limit fed91fff mem (fixed)
1280 12:44:05.449123 update_constraints: PCI: 00:00.0 0d base 00000000 limit 0009ffff mem (fixed)
1281 12:44:05.455614 update_constraints: PCI: 00:00.0 0e base 000c0000 limit 76ffffff mem (fixed)
1282 12:44:05.461930 update_constraints: PCI: 00:00.0 0f base 77000000 limit 7fbfffff mem (fixed)
1283 12:44:05.472329 update_constraints: PCI: 00:00.0 10 base 100000000 limit 4803fffff mem (fixed)
1284 12:44:05.478806 update_constraints: PCI: 00:00.0 11 base 000a0000 limit 000bffff mem (fixed)
1285 12:44:05.485061 update_constraints: PCI: 00:00.0 12 base 000c0000 limit 000fffff mem (fixed)
1286 12:44:05.495320 update_constraints: PCI: 00:00.0 13 base f8000000 limit f9ffffff mem (fixed)
1287 12:44:05.501779 update_constraints: PCI: 00:1e.0 10 base fe03e000 limit fe03efff mem (fixed)
1288 12:44:05.508382 update_constraints: PCI: 00:1f.2 00 base fe000000 limit fe00ffff mem (fixed)
1289 12:44:05.511506 DOMAIN: 0000: Resource ranges:
1290 12:44:05.518242 * Base: 7fc00000, Size: 40400000, Tag: 200
1291 12:44:05.521485 * Base: d0000000, Size: 28000000, Tag: 200
1292 12:44:05.524482 * Base: fa000000, Size: 1000000, Tag: 200
1293 12:44:05.531428 * Base: fb001000, Size: 2fff000, Tag: 200
1294 12:44:05.534819 * Base: fe010000, Size: 2e000, Tag: 200
1295 12:44:05.538095 * Base: fe03f000, Size: d41000, Tag: 200
1296 12:44:05.541028 * Base: fed88000, Size: 8000, Tag: 200
1297 12:44:05.547803 * Base: fed93000, Size: d000, Tag: 200
1298 12:44:05.551125 * Base: feda2000, Size: 1e000, Tag: 200
1299 12:44:05.554137 * Base: fede0000, Size: 1220000, Tag: 200
1300 12:44:05.560740 * Base: 480400000, Size: 7b7fc00000, Tag: 100200
1301 12:44:05.567552 PCI: 00:02.0 18 * [0x80000000 - 0x8fffffff] limit: 8fffffff prefmem
1302 12:44:05.574424 PCI: 00:02.0 10 * [0x90000000 - 0x90ffffff] limit: 90ffffff mem
1303 12:44:05.580779 PCI: 00:05.0 10 * [0x91000000 - 0x91ffffff] limit: 91ffffff mem
1304 12:44:05.586630 PCI: 00:1d.0 20 * [0x7fc00000 - 0x7fcfffff] limit: 7fcfffff mem
1305 12:44:05.594223 PCI: 00:1f.3 20 * [0x7fd00000 - 0x7fdfffff] limit: 7fdfffff mem
1306 12:44:05.600676 PCI: 00:04.0 10 * [0x7fe00000 - 0x7fe1ffff] limit: 7fe1ffff mem
1307 12:44:05.606779 PCI: 00:0d.0 10 * [0x7fe20000 - 0x7fe2ffff] limit: 7fe2ffff mem
1308 12:44:05.613208 PCI: 00:14.0 10 * [0x7fe30000 - 0x7fe3ffff] limit: 7fe3ffff mem
1309 12:44:05.620107 PCI: 00:14.2 10 * [0x7fe40000 - 0x7fe43fff] limit: 7fe43fff mem
1310 12:44:05.626316 PCI: 00:14.3 10 * [0x7fe44000 - 0x7fe47fff] limit: 7fe47fff mem
1311 12:44:05.632938 PCI: 00:1f.3 10 * [0x7fe48000 - 0x7fe4bfff] limit: 7fe4bfff mem
1312 12:44:05.639247 PCI: 00:08.0 10 * [0x7fe4c000 - 0x7fe4cfff] limit: 7fe4cfff mem
1313 12:44:05.646369 PCI: 00:14.2 18 * [0x7fe4d000 - 0x7fe4dfff] limit: 7fe4dfff mem
1314 12:44:05.652865 PCI: 00:15.0 10 * [0x7fe4e000 - 0x7fe4efff] limit: 7fe4efff mem
1315 12:44:05.659272 PCI: 00:15.1 10 * [0x7fe4f000 - 0x7fe4ffff] limit: 7fe4ffff mem
1316 12:44:05.665948 PCI: 00:15.2 10 * [0x7fe50000 - 0x7fe50fff] limit: 7fe50fff mem
1317 12:44:05.672339 PCI: 00:15.3 10 * [0x7fe51000 - 0x7fe51fff] limit: 7fe51fff mem
1318 12:44:05.679204 PCI: 00:16.0 10 * [0x7fe52000 - 0x7fe52fff] limit: 7fe52fff mem
1319 12:44:05.685641 PCI: 00:19.1 10 * [0x7fe53000 - 0x7fe53fff] limit: 7fe53fff mem
1320 12:44:05.692435 PCI: 00:1e.2 10 * [0x7fe54000 - 0x7fe54fff] limit: 7fe54fff mem
1321 12:44:05.698759 PCI: 00:1e.3 10 * [0x7fe55000 - 0x7fe55fff] limit: 7fe55fff mem
1322 12:44:05.705339 PCI: 00:1f.5 10 * [0x7fe56000 - 0x7fe56fff] limit: 7fe56fff mem
1323 12:44:05.711965 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff done
1324 12:44:05.721751 PCI: 00:1d.0 mem: base: 7fc00000 size: 100000 align: 20 gran: 20 limit: 7fcfffff
1325 12:44:05.724898 PCI: 00:1d.0: Resource ranges:
1326 12:44:05.728624 * Base: 7fc00000, Size: 100000, Tag: 200
1327 12:44:05.734964 PCI: 01:00.0 10 * [0x7fc00000 - 0x7fc03fff] limit: 7fc03fff mem
1328 12:44:05.741935 PCI: 01:00.0 20 * [0x7fc04000 - 0x7fc040ff] limit: 7fc040ff mem
1329 12:44:05.751404 PCI: 00:1d.0 mem: base: 7fc00000 size: 100000 align: 20 gran: 20 limit: 7fcfffff done
1330 12:44:05.758343 === Resource allocator: DOMAIN: 0000 - resource allocation complete ===
1331 12:44:05.761439 Root Device assign_resources, bus 0 link: 0
1332 12:44:05.768094 DOMAIN: 0000 assign_resources, bus 0 link: 0
1333 12:44:05.774477 PCI: 00:02.0 10 <- [0x0090000000 - 0x0090ffffff] size 0x01000000 gran 0x18 mem64
1334 12:44:05.784698 PCI: 00:02.0 18 <- [0x0080000000 - 0x008fffffff] size 0x10000000 gran 0x1c prefmem64
1335 12:44:05.791194 PCI: 00:02.0 20 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io
1336 12:44:05.801226 PCI: 00:04.0 10 <- [0x007fe00000 - 0x007fe1ffff] size 0x00020000 gran 0x11 mem64
1337 12:44:05.804671 PCI: 00:04.0 assign_resources, bus 1 link: 0
1338 12:44:05.807241 PCI: 00:04.0 assign_resources, bus 1 link: 0
1339 12:44:05.817643 PCI: 00:05.0 10 <- [0x0091000000 - 0x0091ffffff] size 0x01000000 gran 0x18 mem64
1340 12:44:05.823989 PCI: 00:08.0 10 <- [0x007fe4c000 - 0x007fe4cfff] size 0x00001000 gran 0x0c mem64
1341 12:44:05.833950 PCI: 00:0d.0 10 <- [0x007fe20000 - 0x007fe2ffff] size 0x00010000 gran 0x10 mem64
1342 12:44:05.837011 PCI: 00:0d.0 assign_resources, bus 0 link: 0
1343 12:44:05.843443 PCI: 00:0d.0 assign_resources, bus 0 link: 0
1344 12:44:05.850266 PCI: 00:14.0 10 <- [0x007fe30000 - 0x007fe3ffff] size 0x00010000 gran 0x10 mem64
1345 12:44:05.856776 PCI: 00:14.0 assign_resources, bus 0 link: 0
1346 12:44:05.859776 PCI: 00:14.0 assign_resources, bus 0 link: 0
1347 12:44:05.869576 PCI: 00:14.2 10 <- [0x007fe40000 - 0x007fe43fff] size 0x00004000 gran 0x0e mem64
1348 12:44:05.876412 PCI: 00:14.2 18 <- [0x007fe4d000 - 0x007fe4dfff] size 0x00001000 gran 0x0c mem64
1349 12:44:05.883372 PCI: 00:14.3 10 <- [0x007fe44000 - 0x007fe47fff] size 0x00004000 gran 0x0e mem64
1350 12:44:05.890123 PCI: 00:14.3 assign_resources, bus 0 link: 0
1351 12:44:05.893132 PCI: 00:14.3 assign_resources, bus 0 link: 0
1352 12:44:05.902614 PCI: 00:15.0 10 <- [0x007fe4e000 - 0x007fe4efff] size 0x00001000 gran 0x0c mem64
1353 12:44:05.905952 PCI: 00:15.0 assign_resources, bus 0 link: 0
1354 12:44:05.912233 PCI: 00:15.0 assign_resources, bus 0 link: 0
1355 12:44:05.919419 PCI: 00:15.1 10 <- [0x007fe4f000 - 0x007fe4ffff] size 0x00001000 gran 0x0c mem64
1356 12:44:05.922708 PCI: 00:15.1 assign_resources, bus 0 link: 0
1357 12:44:05.928773 PCI: 00:15.1 assign_resources, bus 0 link: 0
1358 12:44:05.935371 PCI: 00:15.2 10 <- [0x007fe50000 - 0x007fe50fff] size 0x00001000 gran 0x0c mem64
1359 12:44:05.945709 PCI: 00:15.3 10 <- [0x007fe51000 - 0x007fe51fff] size 0x00001000 gran 0x0c mem64
1360 12:44:05.951840 PCI: 00:16.0 10 <- [0x007fe52000 - 0x007fe52fff] size 0x00001000 gran 0x0c mem64
1361 12:44:05.961640 PCI: 00:19.1 10 <- [0x007fe53000 - 0x007fe53fff] size 0x00001000 gran 0x0c mem64
1362 12:44:05.965132 PCI: 00:19.1 assign_resources, bus 0 link: 0
1363 12:44:05.971668 PCI: 00:19.1 assign_resources, bus 0 link: 0
1364 12:44:05.978387 PCI: 00:1d.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
1365 12:44:05.988020 PCI: 00:1d.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
1366 12:44:05.998456 PCI: 00:1d.0 20 <- [0x007fc00000 - 0x007fcfffff] size 0x00100000 gran 0x14 bus 01 mem
1367 12:44:06.000811 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1368 12:44:06.010918 PCI: 01:00.0 10 <- [0x007fc00000 - 0x007fc03fff] size 0x00004000 gran 0x0e mem64
1369 12:44:06.017743 PCI: 01:00.0 20 <- [0x007fc04000 - 0x007fc040ff] size 0x00000100 gran 0x08 mem64
1370 12:44:06.023886 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1371 12:44:06.030883 PCI: 00:1e.2 10 <- [0x007fe54000 - 0x007fe54fff] size 0x00001000 gran 0x0c mem64
1372 12:44:06.037504 PCI: 00:1e.2 assign_resources, bus 2 link: 0
1373 12:44:06.040385 PCI: 00:1e.2 assign_resources, bus 2 link: 0
1374 12:44:06.050193 PCI: 00:1e.3 10 <- [0x007fe55000 - 0x007fe55fff] size 0x00001000 gran 0x0c mem64
1375 12:44:06.053117 PCI: 00:1e.3 assign_resources, bus 3 link: 0
1376 12:44:06.060267 PCI: 00:1e.3 assign_resources, bus 3 link: 0
1377 12:44:06.063435 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1378 12:44:06.066652 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1379 12:44:06.072774 LPC: Trying to open IO window from 800 size 1ff
1380 12:44:06.083215 PCI: 00:1f.3 10 <- [0x007fe48000 - 0x007fe4bfff] size 0x00004000 gran 0x0e mem64
1381 12:44:06.090056 PCI: 00:1f.3 20 <- [0x007fd00000 - 0x007fdfffff] size 0x00100000 gran 0x14 mem64
1382 12:44:06.096586 PCI: 00:1f.5 10 <- [0x007fe56000 - 0x007fe56fff] size 0x00001000 gran 0x0c mem
1383 12:44:06.102899 DOMAIN: 0000 assign_resources, bus 0 link: 0
1384 12:44:06.106057 Root Device assign_resources, bus 0 link: 0
1385 12:44:06.109285 Done setting resources.
1386 12:44:06.116185 Show resources in subtree (Root Device)...After assigning values.
1387 12:44:06.119025 Root Device child on link 0 DOMAIN: 0000
1388 12:44:06.126162 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1389 12:44:06.132297 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1390 12:44:06.141702 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100
1391 12:44:06.145344 PCI: 00:00.0
1392 12:44:06.154745 PCI: 00:00.0 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1393 12:44:06.164779 PCI: 00:00.0 resource base fedc0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1
1394 12:44:06.174910 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1395 12:44:06.184779 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1396 12:44:06.191130 PCI: 00:00.0 resource base fb000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1397 12:44:06.201258 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1398 12:44:06.210950 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 6
1399 12:44:06.220775 PCI: 00:00.0 resource base fed92000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1400 12:44:06.230597 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1401 12:44:06.240507 PCI: 00:00.0 resource base fed85000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9
1402 12:44:06.250027 PCI: 00:00.0 resource base fed86000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
1403 12:44:06.256572 PCI: 00:00.0 resource base fed87000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b
1404 12:44:06.266927 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c
1405 12:44:06.276509 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index d
1406 12:44:06.286799 PCI: 00:00.0 resource base c0000 size 76f40000 align 0 gran 0 limit 0 flags e0004200 index e
1407 12:44:06.296366 PCI: 00:00.0 resource base 77000000 size 8c00000 align 0 gran 0 limit 0 flags f0000200 index f
1408 12:44:06.306169 PCI: 00:00.0 resource base 100000000 size 380400000 align 0 gran 0 limit 0 flags e0004200 index 10
1409 12:44:06.316200 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11
1410 12:44:06.322793 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12
1411 12:44:06.332836 PCI: 00:00.0 resource base f8000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 13
1412 12:44:06.336157 PCI: 00:02.0
1413 12:44:06.345989 PCI: 00:02.0 resource base 90000000 size 1000000 align 24 gran 24 limit 90ffffff flags 60000201 index 10
1414 12:44:06.355157 PCI: 00:02.0 resource base 80000000 size 10000000 align 28 gran 28 limit 8fffffff flags 60001201 index 18
1415 12:44:06.365472 PCI: 00:02.0 resource base 1000 size 40 align 6 gran 6 limit 103f flags 60000100 index 20
1416 12:44:06.368672 PCI: 00:04.0 child on link 0 GENERIC: 0.0
1417 12:44:06.381775 PCI: 00:04.0 resource base 7fe00000 size 20000 align 17 gran 17 limit 7fe1ffff flags 60000201 index 10
1418 12:44:06.382296 GENERIC: 0.0
1419 12:44:06.384901 PCI: 00:05.0
1420 12:44:06.395186 PCI: 00:05.0 resource base 91000000 size 1000000 align 24 gran 24 limit 91ffffff flags 60000201 index 10
1421 12:44:06.398264 PCI: 00:07.0 child on link 0 GENERIC: 0.0
1422 12:44:06.401666 GENERIC: 0.0
1423 12:44:06.402183 PCI: 00:08.0
1424 12:44:06.414622 PCI: 00:08.0 resource base 7fe4c000 size 1000 align 12 gran 12 limit 7fe4cfff flags 60000201 index 10
1425 12:44:06.415146 PCI: 00:0a.0
1426 12:44:06.417529 PCI: 00:0d.0 child on link 0 USB0 port 0
1427 12:44:06.430839 PCI: 00:0d.0 resource base 7fe20000 size 10000 align 16 gran 16 limit 7fe2ffff flags 60000201 index 10
1428 12:44:06.434180 USB0 port 0 child on link 0 USB3 port 0
1429 12:44:06.434694 USB3 port 0
1430 12:44:06.437748 USB3 port 1
1431 12:44:06.440961 USB3 port 2
1432 12:44:06.441478 USB3 port 3
1433 12:44:06.444216 PCI: 00:14.0 child on link 0 USB0 port 0
1434 12:44:06.457246 PCI: 00:14.0 resource base 7fe30000 size 10000 align 16 gran 16 limit 7fe3ffff flags 60000201 index 10
1435 12:44:06.460046 USB0 port 0 child on link 0 USB2 port 0
1436 12:44:06.460596 USB2 port 0
1437 12:44:06.463496 USB2 port 1
1438 12:44:06.466991 USB2 port 2
1439 12:44:06.467542 USB2 port 3
1440 12:44:06.470028 USB2 port 4
1441 12:44:06.470448 USB2 port 5
1442 12:44:06.473570 USB2 port 6
1443 12:44:06.474042 USB2 port 7
1444 12:44:06.476645 USB2 port 8
1445 12:44:06.477168 USB2 port 9
1446 12:44:06.480439 USB3 port 0
1447 12:44:06.480955 USB3 port 1
1448 12:44:06.483516 USB3 port 2
1449 12:44:06.484039 USB3 port 3
1450 12:44:06.486388 PCI: 00:14.2
1451 12:44:06.496443 PCI: 00:14.2 resource base 7fe40000 size 4000 align 14 gran 14 limit 7fe43fff flags 60000201 index 10
1452 12:44:06.506087 PCI: 00:14.2 resource base 7fe4d000 size 1000 align 12 gran 12 limit 7fe4dfff flags 60000201 index 18
1453 12:44:06.512690 PCI: 00:14.3 child on link 0 GENERIC: 0.0
1454 12:44:06.523367 PCI: 00:14.3 resource base 7fe44000 size 4000 align 14 gran 14 limit 7fe47fff flags 60000201 index 10
1455 12:44:06.523887 GENERIC: 0.0
1456 12:44:06.529388 PCI: 00:15.0 child on link 0 I2C: 00:1a
1457 12:44:06.539149 PCI: 00:15.0 resource base 7fe4e000 size 1000 align 12 gran 12 limit 7fe4efff flags 60000201 index 10
1458 12:44:06.539667 I2C: 00:1a
1459 12:44:06.542214 I2C: 00:31
1460 12:44:06.542630 I2C: 00:32
1461 12:44:06.548843 PCI: 00:15.1 child on link 0 I2C: 00:10
1462 12:44:06.559077 PCI: 00:15.1 resource base 7fe4f000 size 1000 align 12 gran 12 limit 7fe4ffff flags 60000201 index 10
1463 12:44:06.559602 I2C: 00:10
1464 12:44:06.562054 PCI: 00:15.2
1465 12:44:06.572021 PCI: 00:15.2 resource base 7fe50000 size 1000 align 12 gran 12 limit 7fe50fff flags 60000201 index 10
1466 12:44:06.572592 PCI: 00:15.3
1467 12:44:06.582181 PCI: 00:15.3 resource base 7fe51000 size 1000 align 12 gran 12 limit 7fe51fff flags 60000201 index 10
1468 12:44:06.585071 PCI: 00:16.0
1469 12:44:06.594873 PCI: 00:16.0 resource base 7fe52000 size 1000 align 12 gran 12 limit 7fe52fff flags 60000201 index 10
1470 12:44:06.598181 PCI: 00:19.0
1471 12:44:06.601760 PCI: 00:19.1 child on link 0 I2C: 00:15
1472 12:44:06.611030 PCI: 00:19.1 resource base 7fe53000 size 1000 align 12 gran 12 limit 7fe53fff flags 60000201 index 10
1473 12:44:06.614374 I2C: 00:15
1474 12:44:06.617707 PCI: 00:1d.0 child on link 0 GENERIC: 0.0
1475 12:44:06.627633 PCI: 00:1d.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 20080102 index 1c
1476 12:44:06.637294 PCI: 00:1d.0 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24
1477 12:44:06.650711 PCI: 00:1d.0 resource base 7fc00000 size 100000 align 20 gran 20 limit 7fcfffff flags 60080202 index 20
1478 12:44:06.651228 GENERIC: 0.0
1479 12:44:06.653783 PCI: 01:00.0
1480 12:44:06.663727 PCI: 01:00.0 resource base 7fc00000 size 4000 align 14 gran 14 limit 7fc03fff flags 60000201 index 10
1481 12:44:06.673943 PCI: 01:00.0 resource base 7fc04000 size 100 align 12 gran 8 limit 7fc040ff flags 60000201 index 20
1482 12:44:06.674480 PCI: 00:1e.0
1483 12:44:06.686954 PCI: 00:1e.0 resource base fe03e000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1484 12:44:06.689523 PCI: 00:1e.2 child on link 0 SPI: 00
1485 12:44:06.699558 PCI: 00:1e.2 resource base 7fe54000 size 1000 align 12 gran 12 limit 7fe54fff flags 60000201 index 10
1486 12:44:06.703030 SPI: 00
1487 12:44:06.706275 PCI: 00:1e.3 child on link 0 SPI: 00
1488 12:44:06.716227 PCI: 00:1e.3 resource base 7fe55000 size 1000 align 12 gran 12 limit 7fe55fff flags 60000201 index 10
1489 12:44:06.716666 SPI: 00
1490 12:44:06.722569 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1491 12:44:06.729396 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1492 12:44:06.732734 PNP: 0c09.0
1493 12:44:06.739513 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1494 12:44:06.745515 PCI: 00:1f.2 child on link 0 GENERIC: 0.0
1495 12:44:06.755752 PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0
1496 12:44:06.762781 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1
1497 12:44:06.768608 GENERIC: 0.0 child on link 0 GENERIC: 0.0
1498 12:44:06.769130 GENERIC: 0.0
1499 12:44:06.771745 GENERIC: 1.0
1500 12:44:06.775309 PCI: 00:1f.3
1501 12:44:06.785057 PCI: 00:1f.3 resource base 7fe48000 size 4000 align 14 gran 14 limit 7fe4bfff flags 60000201 index 10
1502 12:44:06.794913 PCI: 00:1f.3 resource base 7fd00000 size 100000 align 20 gran 20 limit 7fdfffff flags 60000201 index 20
1503 12:44:06.795552 PCI: 00:1f.5
1504 12:44:06.807887 PCI: 00:1f.5 resource base 7fe56000 size 1000 align 12 gran 12 limit 7fe56fff flags 60000200 index 10
1505 12:44:06.811686 CPU_CLUSTER: 0 child on link 0 APIC: 00
1506 12:44:06.812149 APIC: 00
1507 12:44:06.815348 APIC: 01
1508 12:44:06.816201 APIC: 07
1509 12:44:06.816685 APIC: 03
1510 12:44:06.817882 APIC: 04
1511 12:44:06.818266 APIC: 06
1512 12:44:06.821018 APIC: 02
1513 12:44:06.821440 APIC: 05
1514 12:44:06.824625 Done allocating resources.
1515 12:44:06.831326 BS: BS_DEV_RESOURCES run times (exec / console): 26 / 2475 ms
1516 12:44:06.834283 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
1517 12:44:06.841308 Configure GPIOs for I2S audio on UP4.
1518 12:44:06.847788 BS: BS_DEV_ENABLE entry times (exec / console): 2 / 9 ms
1519 12:44:06.848398 Enabling resources...
1520 12:44:06.854302 PCI: 00:00.0 subsystem <- 8086/9a12
1521 12:44:06.854812 PCI: 00:00.0 cmd <- 06
1522 12:44:06.857255 PCI: 00:02.0 subsystem <- 8086/9a40
1523 12:44:06.860619 PCI: 00:02.0 cmd <- 03
1524 12:44:06.864224 PCI: 00:04.0 subsystem <- 8086/9a03
1525 12:44:06.867540 PCI: 00:04.0 cmd <- 02
1526 12:44:06.870945 PCI: 00:05.0 subsystem <- 8086/9a19
1527 12:44:06.874089 PCI: 00:05.0 cmd <- 02
1528 12:44:06.877146 PCI: 00:08.0 subsystem <- 8086/9a11
1529 12:44:06.880603 PCI: 00:08.0 cmd <- 06
1530 12:44:06.884212 PCI: 00:0d.0 subsystem <- 8086/9a13
1531 12:44:06.887357 PCI: 00:0d.0 cmd <- 02
1532 12:44:06.890446 PCI: 00:14.0 subsystem <- 8086/a0ed
1533 12:44:06.894085 PCI: 00:14.0 cmd <- 02
1534 12:44:06.897292 PCI: 00:14.2 subsystem <- 8086/a0ef
1535 12:44:06.897810 PCI: 00:14.2 cmd <- 02
1536 12:44:06.904261 PCI: 00:14.3 subsystem <- 8086/a0f0
1537 12:44:06.904782 PCI: 00:14.3 cmd <- 02
1538 12:44:06.907336 PCI: 00:15.0 subsystem <- 8086/a0e8
1539 12:44:06.910251 PCI: 00:15.0 cmd <- 02
1540 12:44:06.914330 PCI: 00:15.1 subsystem <- 8086/a0e9
1541 12:44:06.917337 PCI: 00:15.1 cmd <- 02
1542 12:44:06.920697 PCI: 00:15.2 subsystem <- 8086/a0ea
1543 12:44:06.923760 PCI: 00:15.2 cmd <- 02
1544 12:44:06.926948 PCI: 00:15.3 subsystem <- 8086/a0eb
1545 12:44:06.930530 PCI: 00:15.3 cmd <- 02
1546 12:44:06.933672 PCI: 00:16.0 subsystem <- 8086/a0e0
1547 12:44:06.937322 PCI: 00:16.0 cmd <- 02
1548 12:44:06.940287 PCI: 00:19.1 subsystem <- 8086/a0c6
1549 12:44:06.942994 PCI: 00:19.1 cmd <- 02
1550 12:44:06.947305 PCI: 00:1d.0 bridge ctrl <- 0013
1551 12:44:06.949727 PCI: 00:1d.0 subsystem <- 8086/a0b0
1552 12:44:06.952910 PCI: 00:1d.0 cmd <- 06
1553 12:44:06.956427 PCI: 00:1e.0 subsystem <- 8086/a0a8
1554 12:44:06.956847 PCI: 00:1e.0 cmd <- 06
1555 12:44:06.963198 PCI: 00:1e.2 subsystem <- 8086/a0aa
1556 12:44:06.963716 PCI: 00:1e.2 cmd <- 06
1557 12:44:06.966206 PCI: 00:1e.3 subsystem <- 8086/a0ab
1558 12:44:06.969789 PCI: 00:1e.3 cmd <- 02
1559 12:44:06.973079 PCI: 00:1f.0 subsystem <- 8086/a087
1560 12:44:06.975895 PCI: 00:1f.0 cmd <- 407
1561 12:44:06.979547 PCI: 00:1f.3 subsystem <- 8086/a0c8
1562 12:44:06.982880 PCI: 00:1f.3 cmd <- 02
1563 12:44:06.985854 PCI: 00:1f.5 subsystem <- 8086/a0a4
1564 12:44:06.989066 PCI: 00:1f.5 cmd <- 406
1565 12:44:06.992963 PCI: 01:00.0 cmd <- 02
1566 12:44:06.997936 done.
1567 12:44:07.000697 BS: BS_DEV_ENABLE run times (exec / console): 10 / 140 ms
1568 12:44:07.004211 Initializing devices...
1569 12:44:07.007518 Root Device init
1570 12:44:07.010716 Chrome EC: Set SMI mask to 0x0000000000000000
1571 12:44:07.017033 Chrome EC: clear events_b mask to 0x0000000000000000
1572 12:44:07.024174 Chrome EC: Set S5 LAZY WAKE mask to 0x0000000000000006
1573 12:44:07.027387 Chrome EC: Set S3 LAZY WAKE mask to 0x000000001800101e
1574 12:44:07.034001 Chrome EC: Set S0iX LAZY WAKE mask to 0x000000001800101e
1575 12:44:07.040935 Chrome EC: Set WAKE mask to 0x0000000000000000
1576 12:44:07.043971 fw_config match found: DB_USB=USB3_ACTIVE
1577 12:44:07.050107 Configure Right Type-C port orientation for retimer
1578 12:44:07.053994 Root Device init finished in 43 msecs
1579 12:44:07.056624 PCI: 00:00.0 init
1580 12:44:07.059939 CPU TDP = 9 Watts
1581 12:44:07.060410 CPU PL1 = 9 Watts
1582 12:44:07.063522 CPU PL2 = 40 Watts
1583 12:44:07.063954 CPU PL4 = 83 Watts
1584 12:44:07.070402 PCI: 00:00.0 init finished in 8 msecs
1585 12:44:07.070934 PCI: 00:02.0 init
1586 12:44:07.073504 GMA: Found VBT in CBFS
1587 12:44:07.076923 GMA: Found valid VBT in CBFS
1588 12:44:07.083658 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
1589 12:44:07.089428 x_res x y_res: 1920 x 1080, size: 8294400 at 0x80000000
1590 12:44:07.093027 PCI: 00:02.0 init finished in 18 msecs
1591 12:44:07.096594 PCI: 00:05.0 init
1592 12:44:07.099903 PCI: 00:05.0 init finished in 0 msecs
1593 12:44:07.103173 PCI: 00:08.0 init
1594 12:44:07.106245 PCI: 00:08.0 init finished in 0 msecs
1595 12:44:07.109351 PCI: 00:14.0 init
1596 12:44:07.112516 PCI: 00:14.0 init finished in 0 msecs
1597 12:44:07.116227 PCI: 00:14.2 init
1598 12:44:07.119418 PCI: 00:14.2 init finished in 0 msecs
1599 12:44:07.119961 PCI: 00:15.0 init
1600 12:44:07.122714 I2C bus 0 version 0x3230302a
1601 12:44:07.129175 DW I2C bus 0 at 0x7fe4e000 (400 KHz)
1602 12:44:07.132375 PCI: 00:15.0 init finished in 6 msecs
1603 12:44:07.132809 PCI: 00:15.1 init
1604 12:44:07.136477 I2C bus 1 version 0x3230302a
1605 12:44:07.139689 DW I2C bus 1 at 0x7fe4f000 (400 KHz)
1606 12:44:07.145834 PCI: 00:15.1 init finished in 6 msecs
1607 12:44:07.146477 PCI: 00:15.2 init
1608 12:44:07.148617 I2C bus 2 version 0x3230302a
1609 12:44:07.152659 DW I2C bus 2 at 0x7fe50000 (400 KHz)
1610 12:44:07.155554 PCI: 00:15.2 init finished in 6 msecs
1611 12:44:07.158986 PCI: 00:15.3 init
1612 12:44:07.161936 I2C bus 3 version 0x3230302a
1613 12:44:07.164944 DW I2C bus 3 at 0x7fe51000 (400 KHz)
1614 12:44:07.168570 PCI: 00:15.3 init finished in 6 msecs
1615 12:44:07.171820 PCI: 00:16.0 init
1616 12:44:07.175033 PCI: 00:16.0 init finished in 0 msecs
1617 12:44:07.178735 PCI: 00:19.1 init
1618 12:44:07.182047 I2C bus 5 version 0x3230302a
1619 12:44:07.185114 DW I2C bus 5 at 0x7fe53000 (400 KHz)
1620 12:44:07.188614 PCI: 00:19.1 init finished in 6 msecs
1621 12:44:07.191714 PCI: 00:1d.0 init
1622 12:44:07.195047 Initializing PCH PCIe bridge.
1623 12:44:07.198603 PCI: 00:1d.0 init finished in 3 msecs
1624 12:44:07.201801 PCI: 00:1f.0 init
1625 12:44:07.204938 IOAPIC: Initializing IOAPIC at 0xfec00000
1626 12:44:07.208416 IOAPIC: Bootstrap Processor Local APIC = 0x00
1627 12:44:07.211268 IOAPIC: ID = 0x02
1628 12:44:07.214477 IOAPIC: Dumping registers
1629 12:44:07.214898 reg 0x0000: 0x02000000
1630 12:44:07.218066 reg 0x0001: 0x00770020
1631 12:44:07.221270 reg 0x0002: 0x00000000
1632 12:44:07.224578 PCI: 00:1f.0 init finished in 21 msecs
1633 12:44:07.227750 PCI: 00:1f.2 init
1634 12:44:07.231195 Disabling ACPI via APMC.
1635 12:44:07.234839 APMC done.
1636 12:44:07.238340 PCI: 00:1f.2 init finished in 6 msecs
1637 12:44:07.250369 PCI: 01:00.0 init
1638 12:44:07.253392 PCI: 01:00.0 init finished in 0 msecs
1639 12:44:07.256585 PNP: 0c09.0 init
1640 12:44:07.262798 Google Chrome EC uptime: 8.281 seconds
1641 12:44:07.266350 Google Chrome AP resets since EC boot: 1
1642 12:44:07.269489 Google Chrome most recent AP reset causes:
1643 12:44:07.273225 0.454: 32775 shutdown: entering G3
1644 12:44:07.279403 Google Chrome EC reset flags at last EC boot: reset-pin | sysjump
1645 12:44:07.285687 PNP: 0c09.0 init finished in 24 msecs
1646 12:44:07.289873 Devices initialized
1647 12:44:07.293125 Show all devs... After init.
1648 12:44:07.296207 Root Device: enabled 1
1649 12:44:07.296719 DOMAIN: 0000: enabled 1
1650 12:44:07.299602 CPU_CLUSTER: 0: enabled 1
1651 12:44:07.302993 PCI: 00:00.0: enabled 1
1652 12:44:07.306171 PCI: 00:02.0: enabled 1
1653 12:44:07.306684 PCI: 00:04.0: enabled 1
1654 12:44:07.309825 PCI: 00:05.0: enabled 1
1655 12:44:07.312478 PCI: 00:06.0: enabled 0
1656 12:44:07.315912 PCI: 00:07.0: enabled 0
1657 12:44:07.316386 PCI: 00:07.1: enabled 0
1658 12:44:07.319285 PCI: 00:07.2: enabled 0
1659 12:44:07.322519 PCI: 00:07.3: enabled 0
1660 12:44:07.326345 PCI: 00:08.0: enabled 1
1661 12:44:07.326858 PCI: 00:09.0: enabled 0
1662 12:44:07.329210 PCI: 00:0a.0: enabled 0
1663 12:44:07.332794 PCI: 00:0d.0: enabled 1
1664 12:44:07.335757 PCI: 00:0d.1: enabled 0
1665 12:44:07.336314 PCI: 00:0d.2: enabled 0
1666 12:44:07.339175 PCI: 00:0d.3: enabled 0
1667 12:44:07.342367 PCI: 00:0e.0: enabled 0
1668 12:44:07.345205 PCI: 00:10.2: enabled 1
1669 12:44:07.345629 PCI: 00:10.6: enabled 0
1670 12:44:07.348789 PCI: 00:10.7: enabled 0
1671 12:44:07.352214 PCI: 00:12.0: enabled 0
1672 12:44:07.355674 PCI: 00:12.6: enabled 0
1673 12:44:07.356237 PCI: 00:13.0: enabled 0
1674 12:44:07.358515 PCI: 00:14.0: enabled 1
1675 12:44:07.361453 PCI: 00:14.1: enabled 0
1676 12:44:07.365065 PCI: 00:14.2: enabled 1
1677 12:44:07.365484 PCI: 00:14.3: enabled 1
1678 12:44:07.368281 PCI: 00:15.0: enabled 1
1679 12:44:07.371407 PCI: 00:15.1: enabled 1
1680 12:44:07.375215 PCI: 00:15.2: enabled 1
1681 12:44:07.375740 PCI: 00:15.3: enabled 1
1682 12:44:07.377983 PCI: 00:16.0: enabled 1
1683 12:44:07.381233 PCI: 00:16.1: enabled 0
1684 12:44:07.384777 PCI: 00:16.2: enabled 0
1685 12:44:07.385198 PCI: 00:16.3: enabled 0
1686 12:44:07.388270 PCI: 00:16.4: enabled 0
1687 12:44:07.391044 PCI: 00:16.5: enabled 0
1688 12:44:07.394340 PCI: 00:17.0: enabled 0
1689 12:44:07.394801 PCI: 00:19.0: enabled 0
1690 12:44:07.398084 PCI: 00:19.1: enabled 1
1691 12:44:07.400982 PCI: 00:19.2: enabled 0
1692 12:44:07.404184 PCI: 00:1c.0: enabled 1
1693 12:44:07.404707 PCI: 00:1c.1: enabled 0
1694 12:44:07.407762 PCI: 00:1c.2: enabled 0
1695 12:44:07.411130 PCI: 00:1c.3: enabled 0
1696 12:44:07.414402 PCI: 00:1c.4: enabled 0
1697 12:44:07.414912 PCI: 00:1c.5: enabled 0
1698 12:44:07.417532 PCI: 00:1c.6: enabled 1
1699 12:44:07.420415 PCI: 00:1c.7: enabled 0
1700 12:44:07.423658 PCI: 00:1d.0: enabled 1
1701 12:44:07.424102 PCI: 00:1d.1: enabled 0
1702 12:44:07.427290 PCI: 00:1d.2: enabled 1
1703 12:44:07.430815 PCI: 00:1d.3: enabled 0
1704 12:44:07.431329 PCI: 00:1e.0: enabled 1
1705 12:44:07.433786 PCI: 00:1e.1: enabled 0
1706 12:44:07.437437 PCI: 00:1e.2: enabled 1
1707 12:44:07.440569 PCI: 00:1e.3: enabled 1
1708 12:44:07.441081 PCI: 00:1f.0: enabled 1
1709 12:44:07.443839 PCI: 00:1f.1: enabled 0
1710 12:44:07.447016 PCI: 00:1f.2: enabled 1
1711 12:44:07.450280 PCI: 00:1f.3: enabled 1
1712 12:44:07.450796 PCI: 00:1f.4: enabled 0
1713 12:44:07.453343 PCI: 00:1f.5: enabled 1
1714 12:44:07.456705 PCI: 00:1f.6: enabled 0
1715 12:44:07.460043 PCI: 00:1f.7: enabled 0
1716 12:44:07.460606 APIC: 00: enabled 1
1717 12:44:07.463134 GENERIC: 0.0: enabled 1
1718 12:44:07.466358 GENERIC: 0.0: enabled 1
1719 12:44:07.469696 GENERIC: 1.0: enabled 1
1720 12:44:07.470211 GENERIC: 0.0: enabled 1
1721 12:44:07.472932 GENERIC: 1.0: enabled 1
1722 12:44:07.476509 USB0 port 0: enabled 1
1723 12:44:07.479412 GENERIC: 0.0: enabled 1
1724 12:44:07.479828 USB0 port 0: enabled 1
1725 12:44:07.483236 GENERIC: 0.0: enabled 1
1726 12:44:07.486613 I2C: 00:1a: enabled 1
1727 12:44:07.487128 I2C: 00:31: enabled 1
1728 12:44:07.489281 I2C: 00:32: enabled 1
1729 12:44:07.492573 I2C: 00:10: enabled 1
1730 12:44:07.492991 I2C: 00:15: enabled 1
1731 12:44:07.496286 GENERIC: 0.0: enabled 0
1732 12:44:07.499467 GENERIC: 1.0: enabled 0
1733 12:44:07.502376 GENERIC: 0.0: enabled 1
1734 12:44:07.502793 SPI: 00: enabled 1
1735 12:44:07.506359 SPI: 00: enabled 1
1736 12:44:07.506779 PNP: 0c09.0: enabled 1
1737 12:44:07.509485 GENERIC: 0.0: enabled 1
1738 12:44:07.512378 USB3 port 0: enabled 1
1739 12:44:07.515642 USB3 port 1: enabled 1
1740 12:44:07.516171 USB3 port 2: enabled 0
1741 12:44:07.518946 USB3 port 3: enabled 0
1742 12:44:07.522167 USB2 port 0: enabled 0
1743 12:44:07.522638 USB2 port 1: enabled 1
1744 12:44:07.525692 USB2 port 2: enabled 1
1745 12:44:07.528898 USB2 port 3: enabled 0
1746 12:44:07.532293 USB2 port 4: enabled 1
1747 12:44:07.532778 USB2 port 5: enabled 0
1748 12:44:07.535724 USB2 port 6: enabled 0
1749 12:44:07.538694 USB2 port 7: enabled 0
1750 12:44:07.539109 USB2 port 8: enabled 0
1751 12:44:07.542297 USB2 port 9: enabled 0
1752 12:44:07.545806 USB3 port 0: enabled 0
1753 12:44:07.548932 USB3 port 1: enabled 1
1754 12:44:07.549423 USB3 port 2: enabled 0
1755 12:44:07.552394 USB3 port 3: enabled 0
1756 12:44:07.555149 GENERIC: 0.0: enabled 1
1757 12:44:07.558813 GENERIC: 1.0: enabled 1
1758 12:44:07.559235 APIC: 01: enabled 1
1759 12:44:07.561526 APIC: 07: enabled 1
1760 12:44:07.562059 APIC: 03: enabled 1
1761 12:44:07.565635 APIC: 04: enabled 1
1762 12:44:07.568563 APIC: 06: enabled 1
1763 12:44:07.568983 APIC: 02: enabled 1
1764 12:44:07.571893 APIC: 05: enabled 1
1765 12:44:07.575267 PCI: 01:00.0: enabled 1
1766 12:44:07.578237 BS: BS_DEV_INIT run times (exec / console): 31 / 540 ms
1767 12:44:07.585218 FMAP: area RW_ELOG found @ f30000 (4096 bytes)
1768 12:44:07.588184 ELOG: NV offset 0xf30000 size 0x1000
1769 12:44:07.594516 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
1770 12:44:07.601192 ELOG: Event(17) added with size 13 at 2024-03-05 12:44:07 UTC
1771 12:44:07.607833 ELOG: Event(92) added with size 9 at 2024-03-05 12:44:07 UTC
1772 12:44:07.614253 ELOG: Event(93) added with size 9 at 2024-03-05 12:44:07 UTC
1773 12:44:07.621159 ELOG: Event(9E) added with size 10 at 2024-03-05 12:44:07 UTC
1774 12:44:07.627429 ELOG: Event(9F) added with size 14 at 2024-03-05 12:44:07 UTC
1775 12:44:07.634391 BS: BS_DEV_INIT exit times (exec / console): 3 / 45 ms
1776 12:44:07.640933 ELOG: Event(A1) added with size 10 at 2024-03-05 12:44:07 UTC
1777 12:44:07.647243 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
1778 12:44:07.654343 ELOG: Event(A0) added with size 9 at 2024-03-05 12:44:08 UTC
1779 12:44:07.657065 elog_add_boot_reason: Logged dev mode boot
1780 12:44:07.663501 BS: BS_POST_DEVICE entry times (exec / console): 1 / 24 ms
1781 12:44:07.666874 Finalize devices...
1782 12:44:07.667230 Devices finalized
1783 12:44:07.673454 BS: BS_POST_DEVICE run times (exec / console): 0 / 4 ms
1784 12:44:07.676813 FMAP: area RW_NVRAM found @ f37000 (24576 bytes)
1785 12:44:07.683515 BS: BS_POST_DEVICE exit times (exec / console): 0 / 5 ms
1786 12:44:07.686367 ME: HFSTS1 : 0x80030055
1787 12:44:07.693511 ME: HFSTS2 : 0x30280116
1788 12:44:07.696484 ME: HFSTS3 : 0x00000050
1789 12:44:07.703118 ME: HFSTS4 : 0x00004000
1790 12:44:07.706360 ME: HFSTS5 : 0x00000000
1791 12:44:07.709842 ME: HFSTS6 : 0x40400006
1792 12:44:07.713022 ME: Manufacturing Mode : YES
1793 12:44:07.719550 ME: SPI Protection Mode Enabled : NO
1794 12:44:07.722568 ME: FW Partition Table : OK
1795 12:44:07.726101 ME: Bringup Loader Failure : NO
1796 12:44:07.729457 ME: Firmware Init Complete : NO
1797 12:44:07.732400 ME: Boot Options Present : NO
1798 12:44:07.735727 ME: Update In Progress : NO
1799 12:44:07.739141 ME: D0i3 Support : YES
1800 12:44:07.742489 ME: Low Power State Enabled : NO
1801 12:44:07.749118 ME: CPU Replaced : YES
1802 12:44:07.752150 ME: CPU Replacement Valid : YES
1803 12:44:07.755811 ME: Current Working State : 5
1804 12:44:07.759026 ME: Current Operation State : 1
1805 12:44:07.762317 ME: Current Operation Mode : 3
1806 12:44:07.765770 ME: Error Code : 0
1807 12:44:07.768991 ME: Enhanced Debug Mode : NO
1808 12:44:07.771972 ME: CPU Debug Disabled : YES
1809 12:44:07.778776 ME: TXT Support : NO
1810 12:44:07.782522 BS: BS_OS_RESUME_CHECK exit times (exec / console): 0 / 94 ms
1811 12:44:07.792427 CBFS: Found 'fallback/dsdt.aml' @0x72f80 size 0x5a67 in mcache @0x76c4c1c4
1812 12:44:07.795242 CBFS: 'fallback/slic' not found.
1813 12:44:07.798645 ACPI: Writing ACPI tables at 76b01000.
1814 12:44:07.798778 ACPI: * FACS
1815 12:44:07.801828 ACPI: * DSDT
1816 12:44:07.805705 Ramoops buffer: 0x100000@0x76a00000.
1817 12:44:07.811747 FMAP: area RO_VPD found @ 1800000 (16384 bytes)
1818 12:44:07.815177 FMAP: area RW_VPD found @ f35000 (8192 bytes)
1819 12:44:07.818493 Google Chrome EC: version:
1820 12:44:07.821735 ro: voema_v2.0.10114-a447f03e46
1821 12:44:07.825601 rw: voema_v2.0.10114-a447f03e46
1822 12:44:07.828553 running image: 2
1823 12:44:07.835209 PCI space above 4GB MMIO is at 0x480400000, len = 0x7b7fc00000
1824 12:44:07.838282 ACPI: * FADT
1825 12:44:07.838708 SCI is IRQ9
1826 12:44:07.841606 ACPI: added table 1/32, length now 40
1827 12:44:07.845366 ACPI: * SSDT
1828 12:44:07.848011 Found 1 CPU(s) with 8 core(s) each.
1829 12:44:07.851756 \_SB.PCI0.PMC: Intel Tigerlake at PCI: 00:1f.2
1830 12:44:07.857947 \_SB.DPTF: Intel DPTF at GENERIC: 0.0
1831 12:44:07.861090 \_SB.PCI0.CNVW: WIFI Device GENERIC: 0.0
1832 12:44:07.864645 \_SB.PCI0.I2C0.RT58: Headset Codec at I2C: 00:1a
1833 12:44:07.871053 \_SB.PCI0.I2C0.MAXR: Maxim MAX98373 Codec address 031h
1834 12:44:07.877772 \_SB.PCI0.I2C0.MAXL: Maxim MAX98373 Codec address 032h
1835 12:44:07.881160 \_SB.PCI0.I2C1.H010: ELAN Touchscreen at I2C: 00:10
1836 12:44:07.887526 \_SB.PCI0.I2C5.D015: ELAN Touchpad at I2C: 00:15
1837 12:44:07.894811 \_SB.PCI0.RP09: Enable RTD3 for PCI: 00:1d.0 (Intel PCIe Runtime D3)
1838 12:44:07.898194 \_SB.PCI0.RP09: Added StorageD3Enable property
1839 12:44:07.900910 \_SB.PCI0.SPI0.S001: SPI Device at SPI: 00
1840 12:44:07.907917 \_SB.PCI0.SPI1.CRFP: SPI Device at SPI: 00
1841 12:44:07.913950 PS2K: Physmap: [ EA E7 91 92 93 94 95 A0 AE B0 ]
1842 12:44:07.917602 PS2K: Passing 80 keymaps to kernel
1843 12:44:07.923921 \_SB.PCI0.TXHC.RHUB.SS01: USB3 Type-C Port C0 (MLB) at USB3 port 0
1844 12:44:07.930286 \_SB.PCI0.TXHC.RHUB.SS02: USB3 Type-C Port C1 (DB) at USB3 port 1
1845 12:44:07.936816 \_SB.PCI0.XHCI.RHUB.HS02: USB2 Type-A Port A1 (DB) at USB2 port 1
1846 12:44:07.943522 \_SB.PCI0.XHCI.RHUB.HS03: USB2 Type-C Port C1 (DB) at USB2 port 2
1847 12:44:07.949972 \_SB.PCI0.XHCI.RHUB.HS05: USB2 Type-C Port C0 (MLB) at USB2 port 4
1848 12:44:07.956713 \_SB.PCI0.XHCI.RHUB.SS02: USB3 Type-A Port A1 (DB) at USB3 port 1
1849 12:44:07.963206 \_SB.PCI0.PMC.MUX.CON0: Intel PMC MUX CONN Driver at GENERIC: 0.0
1850 12:44:07.969734 \_SB.PCI0.PMC.MUX.CON1: Intel PMC MUX CONN Driver at GENERIC: 1.0
1851 12:44:07.973391 ACPI: added table 2/32, length now 44
1852 12:44:07.973819 ACPI: * MCFG
1853 12:44:07.976462 ACPI: added table 3/32, length now 48
1854 12:44:07.979911 ACPI: * TPM2
1855 12:44:07.982965 TPM2 log created at 0x769f0000
1856 12:44:07.986152 ACPI: added table 4/32, length now 52
1857 12:44:07.989734 ACPI: * MADT
1858 12:44:07.990207 SCI is IRQ9
1859 12:44:07.992772 ACPI: added table 5/32, length now 56
1860 12:44:07.996212 current = 76b09850
1861 12:44:07.996627 ACPI: * DMAR
1862 12:44:07.999537 ACPI: added table 6/32, length now 60
1863 12:44:08.005802 ACPI: added table 7/32, length now 64
1864 12:44:08.006218 ACPI: * HPET
1865 12:44:08.009302 ACPI: added table 8/32, length now 68
1866 12:44:08.012658 ACPI: done.
1867 12:44:08.013088 ACPI tables: 35216 bytes.
1868 12:44:08.016356 smbios_write_tables: 769ef000
1869 12:44:08.019311 EC returned error result code 3
1870 12:44:08.022496 Couldn't obtain OEM name from CBI
1871 12:44:08.026214 Create SMBIOS type 16
1872 12:44:08.029473 Create SMBIOS type 17
1873 12:44:08.032634 GENERIC: 0.0 (WIFI Device)
1874 12:44:08.035886 SMBIOS tables: 1734 bytes.
1875 12:44:08.039138 Writing table forward entry at 0x00000500
1876 12:44:08.045804 Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 392c
1877 12:44:08.048901 Writing coreboot table at 0x76b25000
1878 12:44:08.055698 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1879 12:44:08.059059 1. 0000000000001000-000000000009ffff: RAM
1880 12:44:08.062829 2. 00000000000a0000-00000000000fffff: RESERVED
1881 12:44:08.068625 3. 0000000000100000-00000000769eefff: RAM
1882 12:44:08.075758 4. 00000000769ef000-0000000076b97fff: CONFIGURATION TABLES
1883 12:44:08.078713 5. 0000000076b98000-0000000076c09fff: RAMSTAGE
1884 12:44:08.085194 6. 0000000076c0a000-0000000076ffffff: CONFIGURATION TABLES
1885 12:44:08.088615 7. 0000000077000000-000000007fbfffff: RESERVED
1886 12:44:08.095465 8. 00000000c0000000-00000000cfffffff: RESERVED
1887 12:44:08.098152 9. 00000000f8000000-00000000f9ffffff: RESERVED
1888 12:44:08.104820 10. 00000000fb000000-00000000fb000fff: RESERVED
1889 12:44:08.108138 11. 00000000fe000000-00000000fe00ffff: RESERVED
1890 12:44:08.114748 12. 00000000fed80000-00000000fed87fff: RESERVED
1891 12:44:08.118059 13. 00000000fed90000-00000000fed92fff: RESERVED
1892 12:44:08.121374 14. 00000000feda0000-00000000feda1fff: RESERVED
1893 12:44:08.127589 15. 00000000fedc0000-00000000feddffff: RESERVED
1894 12:44:08.131495 16. 0000000100000000-00000004803fffff: RAM
1895 12:44:08.134039 Passing 4 GPIOs to payload:
1896 12:44:08.141097 NAME | PORT | POLARITY | VALUE
1897 12:44:08.144573 lid | undefined | high | high
1898 12:44:08.150809 power | undefined | high | low
1899 12:44:08.153950 oprom | undefined | high | low
1900 12:44:08.160507 EC in RW | 0x000000e5 | high | high
1901 12:44:08.166916 Wrote coreboot table at: 0x76b25000, 0x610 bytes, checksum f865
1902 12:44:08.170893 coreboot table: 1576 bytes.
1903 12:44:08.173845 IMD ROOT 0. 0x76fff000 0x00001000
1904 12:44:08.176908 IMD SMALL 1. 0x76ffe000 0x00001000
1905 12:44:08.180366 FSP MEMORY 2. 0x76c4e000 0x003b0000
1906 12:44:08.183739 VPD 3. 0x76c4d000 0x00000367
1907 12:44:08.190087 RO MCACHE 4. 0x76c4c000 0x00000fdc
1908 12:44:08.193613 CONSOLE 5. 0x76c2c000 0x00020000
1909 12:44:08.196882 FMAP 6. 0x76c2b000 0x00000578
1910 12:44:08.199812 TIME STAMP 7. 0x76c2a000 0x00000910
1911 12:44:08.203422 VBOOT WORK 8. 0x76c16000 0x00014000
1912 12:44:08.206695 ROMSTG STCK 9. 0x76c15000 0x00001000
1913 12:44:08.209943 AFTER CAR 10. 0x76c0a000 0x0000b000
1914 12:44:08.213409 RAMSTAGE 11. 0x76b97000 0x00073000
1915 12:44:08.219739 REFCODE 12. 0x76b42000 0x00055000
1916 12:44:08.223013 SMM BACKUP 13. 0x76b32000 0x00010000
1917 12:44:08.226366 4f444749 14. 0x76b30000 0x00002000
1918 12:44:08.229721 EXT VBT15. 0x76b2d000 0x0000219f
1919 12:44:08.233221 COREBOOT 16. 0x76b25000 0x00008000
1920 12:44:08.236402 ACPI 17. 0x76b01000 0x00024000
1921 12:44:08.239625 ACPI GNVS 18. 0x76b00000 0x00001000
1922 12:44:08.242891 RAMOOPS 19. 0x76a00000 0x00100000
1923 12:44:08.249640 TPM2 TCGLOG20. 0x769f0000 0x00010000
1924 12:44:08.252637 SMBIOS 21. 0x769ef000 0x00000800
1925 12:44:08.253059 IMD small region:
1926 12:44:08.255966 IMD ROOT 0. 0x76ffec00 0x00000400
1927 12:44:08.262788 FSP RUNTIME 1. 0x76ffebe0 0x00000004
1928 12:44:08.265884 POWER STATE 2. 0x76ffeb80 0x00000044
1929 12:44:08.269218 ROMSTAGE 3. 0x76ffeb60 0x00000004
1930 12:44:08.272421 MEM INFO 4. 0x76ffe980 0x000001e0
1931 12:44:08.278823 BS: BS_WRITE_TABLES run times (exec / console): 5 / 484 ms
1932 12:44:08.282161 MTRR: Physical address space:
1933 12:44:08.288694 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
1934 12:44:08.295866 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
1935 12:44:08.302020 0x00000000000c0000 - 0x0000000077000000 size 0x76f40000 type 6
1936 12:44:08.308475 0x0000000077000000 - 0x0000000080000000 size 0x09000000 type 0
1937 12:44:08.312236 0x0000000080000000 - 0x0000000090000000 size 0x10000000 type 1
1938 12:44:08.318732 0x0000000090000000 - 0x0000000100000000 size 0x70000000 type 0
1939 12:44:08.325171 0x0000000100000000 - 0x0000000480400000 size 0x380400000 type 6
1940 12:44:08.331876 MTRR: Fixed MSR 0x250 0x0606060606060606
1941 12:44:08.334920 MTRR: Fixed MSR 0x258 0x0606060606060606
1942 12:44:08.338466 MTRR: Fixed MSR 0x259 0x0000000000000000
1943 12:44:08.341495 MTRR: Fixed MSR 0x268 0x0606060606060606
1944 12:44:08.348221 MTRR: Fixed MSR 0x269 0x0606060606060606
1945 12:44:08.351366 MTRR: Fixed MSR 0x26a 0x0606060606060606
1946 12:44:08.354567 MTRR: Fixed MSR 0x26b 0x0606060606060606
1947 12:44:08.357919 MTRR: Fixed MSR 0x26c 0x0606060606060606
1948 12:44:08.364449 MTRR: Fixed MSR 0x26d 0x0606060606060606
1949 12:44:08.367877 MTRR: Fixed MSR 0x26e 0x0606060606060606
1950 12:44:08.371221 MTRR: Fixed MSR 0x26f 0x0606060606060606
1951 12:44:08.374826 call enable_fixed_mtrr()
1952 12:44:08.378062 CPU physical address size: 39 bits
1953 12:44:08.384972 MTRR: default type WB/UC MTRR counts: 6/7.
1954 12:44:08.388126 MTRR: WB selected as default type.
1955 12:44:08.394840 MTRR: 0 base 0x0000000077000000 mask 0x0000007fff000000 type 0
1956 12:44:08.401398 MTRR: 1 base 0x0000000078000000 mask 0x0000007ff8000000 type 0
1957 12:44:08.404505 MTRR: 2 base 0x0000000080000000 mask 0x0000007ff0000000 type 1
1958 12:44:08.411292 MTRR: 3 base 0x0000000090000000 mask 0x0000007ff0000000 type 0
1959 12:44:08.417717 MTRR: 4 base 0x00000000a0000000 mask 0x0000007fe0000000 type 0
1960 12:44:08.424147 MTRR: 5 base 0x00000000c0000000 mask 0x0000007fc0000000 type 0
1961 12:44:08.428557
1962 12:44:08.428968 MTRR check
1963 12:44:08.431525 Fixed MTRRs : Enabled
1964 12:44:08.432030 Variable MTRRs: Enabled
1965 12:44:08.432515
1966 12:44:08.438301 MTRR: Fixed MSR 0x250 0x0606060606060606
1967 12:44:08.441556 MTRR: Fixed MSR 0x258 0x0606060606060606
1968 12:44:08.444772 MTRR: Fixed MSR 0x259 0x0000000000000000
1969 12:44:08.448226 MTRR: Fixed MSR 0x268 0x0606060606060606
1970 12:44:08.454527 MTRR: Fixed MSR 0x269 0x0606060606060606
1971 12:44:08.458000 MTRR: Fixed MSR 0x26a 0x0606060606060606
1972 12:44:08.460840 MTRR: Fixed MSR 0x26b 0x0606060606060606
1973 12:44:08.464581 MTRR: Fixed MSR 0x26c 0x0606060606060606
1974 12:44:08.470802 MTRR: Fixed MSR 0x26d 0x0606060606060606
1975 12:44:08.474259 MTRR: Fixed MSR 0x26e 0x0606060606060606
1976 12:44:08.477447 MTRR: Fixed MSR 0x26f 0x0606060606060606
1977 12:44:08.485275 BS: BS_WRITE_TABLES exit times (exec / console): 4 / 150 ms
1978 12:44:08.488538 call enable_fixed_mtrr()
1979 12:44:08.492420 Checking cr50 for pending updates
1980 12:44:08.496499 MTRR: Fixed MSR 0x250 0x0606060606060606
1981 12:44:08.499860 MTRR: Fixed MSR 0x250 0x0606060606060606
1982 12:44:08.506258 MTRR: Fixed MSR 0x258 0x0606060606060606
1983 12:44:08.509138 MTRR: Fixed MSR 0x259 0x0000000000000000
1984 12:44:08.512467 MTRR: Fixed MSR 0x268 0x0606060606060606
1985 12:44:08.515733 MTRR: Fixed MSR 0x269 0x0606060606060606
1986 12:44:08.522755 MTRR: Fixed MSR 0x26a 0x0606060606060606
1987 12:44:08.525669 MTRR: Fixed MSR 0x26b 0x0606060606060606
1988 12:44:08.529333 MTRR: Fixed MSR 0x26c 0x0606060606060606
1989 12:44:08.532384 MTRR: Fixed MSR 0x26d 0x0606060606060606
1990 12:44:08.538527 MTRR: Fixed MSR 0x26e 0x0606060606060606
1991 12:44:08.542322 MTRR: Fixed MSR 0x26f 0x0606060606060606
1992 12:44:08.548596 MTRR: Fixed MSR 0x258 0x0606060606060606
1993 12:44:08.549097 call enable_fixed_mtrr()
1994 12:44:08.555253 MTRR: Fixed MSR 0x259 0x0000000000000000
1995 12:44:08.558369 MTRR: Fixed MSR 0x268 0x0606060606060606
1996 12:44:08.561896 MTRR: Fixed MSR 0x269 0x0606060606060606
1997 12:44:08.565582 MTRR: Fixed MSR 0x26a 0x0606060606060606
1998 12:44:08.571798 MTRR: Fixed MSR 0x26b 0x0606060606060606
1999 12:44:08.574963 MTRR: Fixed MSR 0x26c 0x0606060606060606
2000 12:44:08.578189 MTRR: Fixed MSR 0x26d 0x0606060606060606
2001 12:44:08.581462 MTRR: Fixed MSR 0x26e 0x0606060606060606
2002 12:44:08.587666 MTRR: Fixed MSR 0x26f 0x0606060606060606
2003 12:44:08.590974 CPU physical address size: 39 bits
2004 12:44:08.595641 call enable_fixed_mtrr()
2005 12:44:08.599149 MTRR: Fixed MSR 0x250 0x0606060606060606
2006 12:44:08.602628 Reading cr50 TPM mode
2007 12:44:08.605756 CPU physical address size: 39 bits
2008 12:44:08.609692 MTRR: Fixed MSR 0x250 0x0606060606060606
2009 12:44:08.612851 MTRR: Fixed MSR 0x258 0x0606060606060606
2010 12:44:08.619328 MTRR: Fixed MSR 0x258 0x0606060606060606
2011 12:44:08.622787 MTRR: Fixed MSR 0x259 0x0000000000000000
2012 12:44:08.626208 MTRR: Fixed MSR 0x268 0x0606060606060606
2013 12:44:08.629324 MTRR: Fixed MSR 0x269 0x0606060606060606
2014 12:44:08.635815 MTRR: Fixed MSR 0x26a 0x0606060606060606
2015 12:44:08.639335 MTRR: Fixed MSR 0x26b 0x0606060606060606
2016 12:44:08.642545 MTRR: Fixed MSR 0x26c 0x0606060606060606
2017 12:44:08.646068 MTRR: Fixed MSR 0x26d 0x0606060606060606
2018 12:44:08.652368 MTRR: Fixed MSR 0x26e 0x0606060606060606
2019 12:44:08.655400 MTRR: Fixed MSR 0x26f 0x0606060606060606
2020 12:44:08.662100 MTRR: Fixed MSR 0x259 0x0000000000000000
2021 12:44:08.662591 call enable_fixed_mtrr()
2022 12:44:08.668759 MTRR: Fixed MSR 0x268 0x0606060606060606
2023 12:44:08.672194 MTRR: Fixed MSR 0x269 0x0606060606060606
2024 12:44:08.675450 MTRR: Fixed MSR 0x26a 0x0606060606060606
2025 12:44:08.679191 MTRR: Fixed MSR 0x26b 0x0606060606060606
2026 12:44:08.685327 MTRR: Fixed MSR 0x26c 0x0606060606060606
2027 12:44:08.689293 MTRR: Fixed MSR 0x26d 0x0606060606060606
2028 12:44:08.692101 MTRR: Fixed MSR 0x26e 0x0606060606060606
2029 12:44:08.695223 MTRR: Fixed MSR 0x26f 0x0606060606060606
2030 12:44:08.700474 CPU physical address size: 39 bits
2031 12:44:08.706921 call enable_fixed_mtrr()
2032 12:44:08.713671 BS: BS_PAYLOAD_LOAD entry times (exec / console): 115 / 6 ms
2033 12:44:08.716738 CPU physical address size: 39 bits
2034 12:44:08.727090 CBFS: Found 'fallback/payload' @0x38db00 size 0x4be9c in mcache @0x76c4cf60
2035 12:44:08.730257 MTRR: Fixed MSR 0x250 0x0606060606060606
2036 12:44:08.733563 MTRR: Fixed MSR 0x250 0x0606060606060606
2037 12:44:08.736587 MTRR: Fixed MSR 0x258 0x0606060606060606
2038 12:44:08.743179 MTRR: Fixed MSR 0x259 0x0000000000000000
2039 12:44:08.746483 MTRR: Fixed MSR 0x268 0x0606060606060606
2040 12:44:08.749817 MTRR: Fixed MSR 0x269 0x0606060606060606
2041 12:44:08.752812 MTRR: Fixed MSR 0x26a 0x0606060606060606
2042 12:44:08.759496 MTRR: Fixed MSR 0x26b 0x0606060606060606
2043 12:44:08.763162 MTRR: Fixed MSR 0x26c 0x0606060606060606
2044 12:44:08.766524 MTRR: Fixed MSR 0x26d 0x0606060606060606
2045 12:44:08.769753 MTRR: Fixed MSR 0x26e 0x0606060606060606
2046 12:44:08.775957 MTRR: Fixed MSR 0x26f 0x0606060606060606
2047 12:44:08.782499 MTRR: Fixed MSR 0x258 0x0606060606060606
2048 12:44:08.785823 MTRR: Fixed MSR 0x259 0x0000000000000000
2049 12:44:08.789143 MTRR: Fixed MSR 0x268 0x0606060606060606
2050 12:44:08.792715 MTRR: Fixed MSR 0x269 0x0606060606060606
2051 12:44:08.796111 MTRR: Fixed MSR 0x26a 0x0606060606060606
2052 12:44:08.802824 MTRR: Fixed MSR 0x26b 0x0606060606060606
2053 12:44:08.805858 MTRR: Fixed MSR 0x26c 0x0606060606060606
2054 12:44:08.808992 MTRR: Fixed MSR 0x26d 0x0606060606060606
2055 12:44:08.812607 MTRR: Fixed MSR 0x26e 0x0606060606060606
2056 12:44:08.819194 MTRR: Fixed MSR 0x26f 0x0606060606060606
2057 12:44:08.822888 call enable_fixed_mtrr()
2058 12:44:08.825283 call enable_fixed_mtrr()
2059 12:44:08.828634 CPU physical address size: 39 bits
2060 12:44:08.832201 CPU physical address size: 39 bits
2061 12:44:08.839075 CPU physical address size: 39 bits
2062 12:44:08.842373 Checking segment from ROM address 0xffc02b38
2063 12:44:08.845463 Checking segment from ROM address 0xffc02b54
2064 12:44:08.852550 Loading segment from ROM address 0xffc02b38
2065 12:44:08.852991 code (compression=0)
2066 12:44:08.862077 New segment dstaddr 0x30000000 memsize 0x2662db0 srcaddr 0xffc02b70 filesize 0x4be64
2067 12:44:08.871941 Loading Segment: addr: 0x30000000 memsz: 0x0000000002662db0 filesz: 0x000000000004be64
2068 12:44:08.872461 it's not compressed!
2069 12:44:09.016417 [ 0x30000000, 3004be64, 0x32662db0) <- ffc02b70
2070 12:44:09.023305 Clearing Segment: addr: 0x000000003004be64 memsz: 0x0000000002616f4c
2071 12:44:09.029926 Loading segment from ROM address 0xffc02b54
2072 12:44:09.033557 Entry Point 0x30000000
2073 12:44:09.033975 Loaded segments
2074 12:44:09.039919 BS: BS_PAYLOAD_LOAD run times (exec / console): 256 / 65 ms
2075 12:44:09.085192 Finalizing chipset.
2076 12:44:09.088317 Finalizing SMM.
2077 12:44:09.088546 APMC done.
2078 12:44:09.095077 BS: BS_PAYLOAD_LOAD exit times (exec / console): 44 / 5 ms
2079 12:44:09.098657 mp_park_aps done after 0 msecs.
2080 12:44:09.101873 Jumping to boot code at 0x30000000(0x76b25000)
2081 12:44:09.111218 CPU0: stack: 0x76bee000 - 0x76bef000, lowest used address 0x76beea78, stack used: 1416 bytes
2082 12:44:09.111322
2083 12:44:09.114408
2084 12:44:09.114512
2085 12:44:09.118244 Starting depthcharge on Voema...
2086 12:44:09.118336
2087 12:44:09.118705 end: 2.2.3 depthcharge-start (duration 00:00:10) [common]
2088 12:44:09.118815 start: 2.2.4 bootloader-commands (timeout 00:04:45) [common]
2089 12:44:09.118903 Setting prompt string to ['volteer:']
2090 12:44:09.118991 bootloader-commands: Wait for prompt ['volteer:'] (timeout 00:04:45)
2091 12:44:09.124389 WARNING: can't convert coreboot GPIOs, 'lid' won't be resampled at runtime!
2092 12:44:09.124502
2093 12:44:09.131581 WARNING: can't convert coreboot GPIOs, 'power' won't be resampled at runtime!
2094 12:44:09.131664
2095 12:44:09.137610 Looking for NVMe Controller 0x3005f220 @ 00:1d:00
2096 12:44:09.137693
2097 12:44:09.141137 Failed to find eMMC card reader
2098 12:44:09.141219
2099 12:44:09.144149 Wipe memory regions:
2100 12:44:09.144229
2101 12:44:09.147826 [0x00000000001000, 0x000000000a0000)
2102 12:44:09.147913
2103 12:44:09.150680 [0x00000000100000, 0x00000030000000)
2104 12:44:09.186845
2105 12:44:09.189871 [0x00000032662db0, 0x000000769ef000)
2106 12:44:09.240014
2107 12:44:09.243007 [0x00000100000000, 0x00000480400000)
2108 12:44:09.899223
2109 12:44:09.903027 ec_init: CrosEC protocol v3 supported (256, 256)
2110 12:44:10.334599
2111 12:44:10.335115 R8152: Initializing
2112 12:44:10.335453
2113 12:44:10.337797 Version 6 (ocp_data = 5c30)
2114 12:44:10.338310
2115 12:44:10.341364 R8152: Done initializing
2116 12:44:10.341904
2117 12:44:10.344264 Adding net device
2118 12:44:10.645975
2119 12:44:10.649010 [firmware-volteer-13672.B-collabora] Oct 22 2021 06:32:35
2120 12:44:10.649526
2121 12:44:10.649863
2122 12:44:10.650176
2123 12:44:10.652784 Setting prompt string to ['volteer:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2125 12:44:10.754292 volteer: tftpboot 192.168.201.1 12948307/tftp-deploy-d3sr_p9r/kernel/bzImage 12948307/tftp-deploy-d3sr_p9r/kernel/cmdline 12948307/tftp-deploy-d3sr_p9r/ramdisk/ramdisk.cpio.gz
2126 12:44:10.754912 Setting prompt string to ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2127 12:44:10.755359 bootloader-commands: Wait for prompt ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:43)
2128 12:44:10.759740 tftpboot 192.168.201.1 12948307/tftp-deploy-d3sr_p9r/kernel/bzIploy-d3sr_p9r/kernel/cmdline 12948307/tftp-deploy-d3sr_p9r/ramdisk/ramdisk.cpio.gz
2129 12:44:10.760424
2130 12:44:10.760975 Waiting for link
2131 12:44:10.963303
2132 12:44:10.963970 done.
2133 12:44:10.964559
2134 12:44:10.964999 MAC: 00:24:32:30:7a:04
2135 12:44:10.965341
2136 12:44:10.966181 Sending DHCP discover... done.
2137 12:44:10.966566
2138 12:44:10.970006 Waiting for reply... done.
2139 12:44:10.970577
2140 12:44:10.974355 Sending DHCP request... done.
2141 12:44:10.974776
2142 12:44:10.985446 Waiting for reply... done.
2143 12:44:10.985610
2144 12:44:10.985687 My ip is 192.168.201.22
2145 12:44:10.985761
2146 12:44:10.991841 The DHCP server ip is 192.168.201.1
2147 12:44:10.992019
2148 12:44:10.994948 TFTP server IP predefined by user: 192.168.201.1
2149 12:44:10.995124
2150 12:44:11.002140 Bootfile predefined by user: 12948307/tftp-deploy-d3sr_p9r/kernel/bzImage
2151 12:44:11.002337
2152 12:44:11.004495 Sending tftp read request... done.
2153 12:44:11.004663
2154 12:44:11.012005 Waiting for the transfer...
2155 12:44:11.012267
2156 12:44:11.740448 00000000 ################################################################
2157 12:44:11.740977
2158 12:44:12.477193 00080000 ################################################################
2159 12:44:12.477747
2160 12:44:13.213822 00100000 ################################################################
2161 12:44:13.214357
2162 12:44:13.948844 00180000 ################################################################
2163 12:44:13.949412
2164 12:44:14.685350 00200000 ################################################################
2165 12:44:14.686000
2166 12:44:15.435926 00280000 ################################################################
2167 12:44:15.436526
2168 12:44:16.183413 00300000 ################################################################
2169 12:44:16.183942
2170 12:44:16.915609 00380000 ################################################################
2171 12:44:16.916183
2172 12:44:17.648649 00400000 ################################################################
2173 12:44:17.649165
2174 12:44:18.378403 00480000 ################################################################
2175 12:44:18.378972
2176 12:44:19.122381 00500000 ################################################################
2177 12:44:19.122916
2178 12:44:19.859140 00580000 ################################################################
2179 12:44:19.859687
2180 12:44:20.589695 00600000 ################################################################
2181 12:44:20.590260
2182 12:44:21.302630 00680000 ################################################################
2183 12:44:21.303230
2184 12:44:22.053303 00700000 ################################################################
2185 12:44:22.053840
2186 12:44:22.797270 00780000 ################################################################
2187 12:44:22.797795
2188 12:44:23.528121 00800000 ################################################################
2189 12:44:23.528658
2190 12:44:24.172180 00880000 ######################################################## done.
2191 12:44:24.172709
2192 12:44:24.175542 The bootfile was 9367440 bytes long.
2193 12:44:24.176134
2194 12:44:24.178392 Sending tftp read request... done.
2195 12:44:24.178812
2196 12:44:24.181546 Waiting for the transfer...
2197 12:44:24.181969
2198 12:44:24.919723 00000000 ################################################################
2199 12:44:24.920317
2200 12:44:25.667907 00080000 ################################################################
2201 12:44:25.668507
2202 12:44:26.406944 00100000 ################################################################
2203 12:44:26.407484
2204 12:44:27.137777 00180000 ################################################################
2205 12:44:27.138489
2206 12:44:27.867430 00200000 ################################################################
2207 12:44:27.867972
2208 12:44:28.579082 00280000 ################################################################
2209 12:44:28.579613
2210 12:44:29.307184 00300000 ################################################################
2211 12:44:29.307670
2212 12:44:30.061028 00380000 ################################################################
2213 12:44:30.061568
2214 12:44:30.774065 00400000 ################################################################
2215 12:44:30.774594
2216 12:44:31.478785 00480000 ################################################################
2217 12:44:31.479012
2218 12:44:32.137751 00500000 ################################################################
2219 12:44:32.138315
2220 12:44:32.806593 00580000 ################################################################
2221 12:44:32.806747
2222 12:44:33.369836 00600000 ################################################################
2223 12:44:33.370010
2224 12:44:33.941742 00680000 ################################################################
2225 12:44:33.941887
2226 12:44:34.509632 00700000 ################################################################
2227 12:44:34.509780
2228 12:44:35.070397 00780000 ################################################################
2229 12:44:35.070549
2230 12:44:35.540020 00800000 #################################################### done.
2231 12:44:35.540231
2232 12:44:35.543029 Sending tftp read request... done.
2233 12:44:35.543106
2234 12:44:35.546370 Waiting for the transfer...
2235 12:44:35.546450
2236 12:44:35.546514 00000000 # done.
2237 12:44:35.546577
2238 12:44:35.555863 Command line loaded dynamically from TFTP file: 12948307/tftp-deploy-d3sr_p9r/kernel/cmdline
2239 12:44:35.555977
2240 12:44:35.572531 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
2241 12:44:35.576542
2242 12:44:35.579651 Shutting down all USB controllers.
2243 12:44:35.579727
2244 12:44:35.579820 Removing current net device
2245 12:44:35.579908
2246 12:44:35.582541 Finalizing coreboot
2247 12:44:35.582623
2248 12:44:35.588958 Exiting depthcharge with code 4 at timestamp: 35052293
2249 12:44:35.589045
2250 12:44:35.589109
2251 12:44:35.589170 Starting kernel ...
2252 12:44:35.589228
2253 12:44:35.589599 end: 2.2.4 bootloader-commands (duration 00:00:26) [common]
2254 12:44:35.589693 start: 2.2.5 auto-login-action (timeout 00:04:18) [common]
2255 12:44:35.589768 Setting prompt string to ['Linux version [0-9]']
2256 12:44:35.589835 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2257 12:44:35.589901 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
2258 12:44:35.592358
2260 12:48:53.590744 end: 2.2.5 auto-login-action (duration 00:04:18) [common]
2262 12:48:53.591893 depthcharge-retry failed: 1 of 1 attempts. 'auto-login-action timed out after 258 seconds'
2264 12:48:53.592771 end: 2.2 depthcharge-retry (duration 00:05:00) [common]
2267 12:48:53.594036 end: 2 depthcharge-action (duration 00:05:00) [common]
2269 12:48:53.595105 Cleaning after the job
2270 12:48:53.595386 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12948307/tftp-deploy-d3sr_p9r/ramdisk
2271 12:48:53.596682 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12948307/tftp-deploy-d3sr_p9r/kernel
2272 12:48:53.598173 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/12948307/tftp-deploy-d3sr_p9r/modules
2273 12:48:53.598508 start: 5.1 power-off (timeout 00:00:30) [common]
2274 12:48:53.598664 Calling: 'pduclient' '--daemon=localhost' '--hostname=asus-cx9400-volteer-cbg-10' '--port=1' '--command=off'
2275 12:48:53.679064 >> Command sent successfully.
2276 12:48:53.685438 Returned 0 in 0 seconds
2277 12:48:53.786535 end: 5.1 power-off (duration 00:00:00) [common]
2279 12:48:53.788136 start: 5.2 read-feedback (timeout 00:10:00) [common]
2280 12:48:53.789355 Listened to connection for namespace 'common' for up to 1s
2281 12:48:54.789974 Finalising connection for namespace 'common'
2282 12:48:54.790592 Disconnecting from shell: Finalise
2283 12:48:54.790977
2284 12:48:54.892087 end: 5.2 read-feedback (duration 00:00:01) [common]
2285 12:48:54.892744 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/12948307
2286 12:48:54.944854 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/12948307
2287 12:48:54.945084 JobError: Your job cannot terminate cleanly.