[Enter `^Ec?' for help] � coreboot-v1.9308_26_0.0.22-15031-g42970b8c8b Tue Mar 29 17:32:50 UTC 2022 bootblock starting (log level: 8)... CPU: Intel(R) Celeron(R) CPU 5205U @ 1.90GHz CPU: ID a0660, Cometlake-U A0 (6+2), ucode: 000000c9 CPU: AES supported, TXT NOT supported, VT supported MCH: device id 9b71 (rev 00) is CometLake-U (2+2) PCH: device id 0285 (rev 00) is Cometlake-U Base IGD: device id 9baa (rev 04) is CometLake ULT GT2 VBOOT: Loading verstage. FMAP: Found "FLASH" version 1.1 at 0xc04000. FMAP: base = 0xff000000 size = 0x1000000 #areas = 32 FMAP: area COREBOOT found @ c08000 (4161536 bytes) CBFS: Locating 'fallback/verstage' CBFS: Found @ offset 10c240 size 1152c coreboot-v1.9308_26_0.0.22-15031-g42970b8c8b Tue Mar 29 17:32:50 UTC 2022 verstage starting (log level: 8)... Probing TPM: . done! TPM ready after 0 ms Connected to device vid:did:rid of 1ae0:0028:00 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_B:0.5.130/cr50_v2.94_mp.110-683b81dc66 Initialized TPM device CR50 revision 0 tlcl_send_startup: Startup return code is 0 TPM: setup succeeded src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes) src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0 Chrome EC: UHEPI supported Phase 1 FMAP: area GBB found @ c05000 (12288 bytes) VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7 Recovery requested (1009000e) TPM: Extending digest for VBOOT: boot mode into PCR 0 tlcl_extend: response is 0 TPM: Extending digest for VBOOT: GBB HWID into PCR 1 tlcl_extend: response is 0 FMAP: area COREBOOT found @ c08000 (4161536 bytes) CBFS: Locating 'fallback/romstage' CBFS: Found @ offset 80 size 1607c BS: verstage times (exec / console): total (unknown) / 119 ms coreboot-v1.9308_26_0.0.22-15031-g42970b8c8b Tue Mar 29 17:32:50 UTC 2022 romstage starting (log level: 8)... VB2:vb2api_ec_sync() In recovery mode, skipping EC sync pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00 gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000 gpe0_sts[1]: 00200000 gpe0_en[1]: 00000000 gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000 gpe0_sts[3]: 00000000 gpe0_en[3]: 00000000 TCO_STS: 0000 0000 GEN_PMCON: e0015038 00000200 GBLRST_CAUSE: 00000000 00000000 prev_sleep_state 5 Boot Count incremented to 25467 FMAP: area COREBOOT found @ c08000 (4161536 bytes) CBFS: Locating 'fspm.bin' CBFS: Found @ offset 66fc0 size 71000 Chrome EC: UHEPI supported FMAP: area RECOVERY_MRC_CACHE found @ ad0000 (65536 bytes) Probing TPM: done! Connected to device vid:did:rid of 1ae0:0028:00 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_B:0.5.130/cr50_v2.94_mp.110-683b81dc66 Initialized TPM device CR50 revision 0 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x100b return code 0 MRC: Hash comparison successful. Using data from RECOVERY_MRC_CACHE MRC cache found, size 1948 bootmode is set to: 2 PRMRR disabled by config. FMAP: area RW_SPD_CACHE found @ aff000 (4096 bytes) SPD_CACHE: cache found, size 0x1000 No memory dimm at address 50 SPD_CACHE: DIMM0 is not present SPD_CACHE: DIMM1 is the same SPD @ 0x52 SPD: module type is DDR4 SPD: module part number is HMA851S6CJR6N-VK SPD: banks 8, ranks 1, rows 16, columns 10, density 8192 Mb SPD: device width 16 bits, bus width 64 bits SPD: module size is 4096 MB (per channel) memory slot: 2 configuration done. CBMEM: IMD: root @ 0x99fff000 254 entries. IMD: root @ 0x99ffec00 62 entries. FMAP: area RO_VPD found @ c00000 (16384 bytes) WARNING: RO_VPD is uninitialized or empty. FMAP: area RW_VPD found @ af8000 (8192 bytes) External stage cache: IMD: root @ 0x9abff000 254 entries. IMD: root @ 0x9abfec00 62 entries. src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x100b return code 0 tlcl_write: response is 0 MRC: TPM MRC hash updated successfully. 1 DIMMs found SMM Memory Map SMRAM : 0x9a000000 0x1000000 Subregion 0: 0x9a000000 0xa00000 Subregion 1: 0x9aa00000 0x200000 Subregion 2: 0x9ac00000 0x400000 top_of_ram = 0x9a000000 MTRR Range: Start=99000000 End=9a000000 (Size 1000000) MTRR Range: Start=9a000000 End=9b000000 (Size 1000000) MTRR Range: Start=ff000000 End=0 (Size 1000000) FMAP: area COREBOOT found @ c08000 (4161536 bytes) CBFS: Locating 'fallback/postcar' CBFS: Found @ offset 1076c0 size 4b28 Decompressing stage fallback/postcar @ 0x99c0bfc0 (35640 bytes) Loading module at 0x99c0c000 with entry 0x99c0c000. filesize: 0x4818 memsize: 0x8af8 Processing 173 relocs. Offset value of 0x97c0c000 BS: romstage times (exec / console): total (unknown) / 267 ms coreboot-v1.9308_26_0.0.22-15031-g42970b8c8b Tue Mar 29 17:32:50 UTC 2022 postcar starting (log level: 8)... FMAP: area COREBOOT found @ c08000 (4161536 bytes) CBFS: Locating 'fallback/ramstage' CBFS: Found @ offset 44e00 size 1e0ef Decompressing stage fallback/ramstage @ 0x99ba4fc0 (415200 bytes) Loading module at 0x99ba5000 with entry 0x99ba5000. filesize: 0x46598 memsize: 0x655a0 Processing 4604 relocs. Offset value of 0x98da5000 BS: postcar times (exec / console): total (unknown) / 43 ms coreboot-v1.9308_26_0.0.22-15031-g42970b8c8b Tue Mar 29 17:32:50 UTC 2022 ramstage starting (log level: 8)... Normal boot cse_lite: Skip switching to RW in the recovery path BS: BS_PRE_DEVICE entry times (exec / console): 0 / 5 ms FMAP: area COREBOOT found @ c08000 (4161536 bytes) CBFS: Locating 'cpu_microcode_blob.bin' CBFS: Found @ offset 16180 size 2ec00 microcode: sig=0xa0660 pf=0x80 revision=0xc9 Skip microcode update FMAP: area COREBOOT found @ c08000 (4161536 bytes) CBFS: Locating 'fsps.bin' CBFS: Found @ offset d8fc0 size 2e69d Detected 2 core, 2 thread CPU. Setting up SMI for CPU IED base = 0x9ac00000 IED size = 0x00400000 Will perform SMM setup. CPU: Intel(R) Celeron(R) CPU 5205U @ 1.90GHz. Loading module at 0x00030000 with entry 0x00030000. filesize: 0x170 memsize: 0x170 Processing 16 relocs. Offset value of 0x00030000 Attempting to start 1 APs Waiting for 10ms after sending INIT. Waiting for 1st SIPI to complete...done. AP: slot 1 apic_id 2. Waiting for 2nd SIPI to complete...done. Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1b8 memsize: 0x1b8 Processing 13 relocs. Offset value of 0x00038000 SMM Module: stub loaded at 0x00038000. Will call 0x99bc2760(0x00000000) Installing SMM handler to 0x9a000000 Loading module at 0x9a010000 with entry 0x9a010a30. filesize: 0x7bc8 memsize: 0xcc90 Processing 617 relocs. Offset value of 0x9a010000 Loading module at 0x9a008000 with entry 0x9a008000. filesize: 0x1b8 memsize: 0x1b8 Processing 13 relocs. Offset value of 0x9a008000 SMM Module: placing jmp sequence at 0x9a007c00 rel16 0x03fd SMM Module: stub loaded at 0x9a008000. Will call 0x9a010a30(0x00000000) Clearing SMI status registers SMI_STS: PM1 PM1_STS: PWRBTN New SMBASE 0x9a000000 In relocation handler: CPU 0 New SMBASE=0x9a000000 IEDBASE=0x9ac00000 Writing SMRR. base = 0x9a000006, mask=0xff000800 Relocation complete. New SMBASE 0x99fffc00 In relocation handler: CPU 1 New SMBASE=0x99fffc00 IEDBASE=0x9ac00000 Writing SMRR. base = 0x9a000006, mask=0xff000800 Relocation complete. Initializing CPU #0 CPU: vendor Intel device a0660 CPU: family 06, model a6, stepping 00 Clearing out pending MCEs Setting up local APIC... apic_id: 0x00 done. Turbo is available but hidden Turbo is unavailable VMX status: enabled IA32_FEATURE_CONTROL status: locked Skip microcode update CPU #0 initialized Initializing CPU #1 CPU: vendor Intel device a0660 CPU: family 06, model a6, stepping 00 Clearing out pending MCEs Setting up local APIC... apic_id: 0x02 done. VMX status: enabled IA32_FEATURE_CONTROL status: locked Skip microcode update CPU #1 initialized bsp_do_flight_plan done after 160 msecs. Enabling SMIs. Locking SMM. BS: BS_DEV_INIT_CHIPS entry times (exec / console): 89 / 199 ms Waiting for DisplayPort DisplayPort not ready after 3000ms. Abort. FMAP: area COREBOOT found @ c08000 (4161536 bytes) CBFS: Locating 'vbt.bin' CBFS: Found @ offset 66a80 size 49e Found a VBT of 4608 bytes after decompression psys_pmax = 182W Display FSP Version Info HOB Reference Code - CPU = 9.0.1e.30 uCode Version = 0.0.0.ca TXT ACM version = ff.ff.ff.ffff Reference Code - ME = 9.0.1e.30 MEBx version = 0.0.0.0 ME Firmware Version = Consumer SKU Reference Code - CML PCH = 9.0.1e.30 PCH-CRID Status = Disabled PCH-CRID Original Value = ff.ff.ff.ffff PCH-CRID New Value = ff.ff.ff.ffff OPROM - RST - RAID = ff.ff.ff.ffff ChipsetInit Base Version = ff.ff.ff.ffff ChipsetInit Oem Version = ff.ff.ff.ffff Reference Code - SA - System Agent = 9.0.1e.30 Reference Code - MRC = 0.0.0.2d SA - PCIe Version = 9.0.1e.30 SA-CRID Status = Disabled SA-CRID Original Value = 0.0.0.0 SA-CRID New Value = 0.0.0.0 OPROM - VBIOS = ff.ff.ff.ffff Found PCIe Root Port #7 at PCI: 00:1c.0. Remapping PCIe Root Port #7 from PCI: 00:1c.6 to new function number 0. pcie_rp_update_dev: Couldn't find PCIe Root Port #9 (originally PCI: 00:1d.0) which was enabled in devicetree, removing. pcie_rp_update_dev: Couldn't find PCIe Root Port #11 (originally PCI: 00:1d.2) which was enabled in devicetree, removing. pcie_rp_update_dev: Couldn't find PCIe Root Port #14 (originally PCI: 00:1d.5) which was enabled in devicetree, removing. BS: BS_DEV_INIT_CHIPS run times (exec / console): 3064 / 140 ms RTC Init Set power on after power failure. Disabling Deep S3 Disabling Deep S3 Disabling Deep S4 Disabling Deep S4 Disabling Deep S5 Disabling Deep S5 BS: BS_DEV_INIT_CHIPS exit times (exec / console): 1 / 15 ms Enumerating buses... Show all devs... Before device enumeration. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 DOMAIN: 0000: enabled 1 APIC: 00: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:04.0: enabled 1 PCI: 00:05.0: enabled 0 PCI: 00:12.0: enabled 1 PCI: 00:12.5: enabled 0 PCI: 00:12.6: enabled 0 PCI: 00:14.0: enabled 1 PCI: 00:14.1: enabled 0 PCI: 00:14.3: enabled 1 PCI: 00:14.5: enabled 1 PCI: 00:15.0: enabled 0 PCI: 00:15.1: enabled 0 PCI: 00:15.2: enabled 1 PCI: 00:15.3: enabled 1 PCI: 00:16.0: enabled 1 PCI: 00:16.1: enabled 0 PCI: 00:16.2: enabled 0 PCI: 00:16.3: enabled 0 PCI: 00:16.4: enabled 0 PCI: 00:16.5: enabled 0 PCI: 00:17.0: enabled 1 PCI: 00:19.0: enabled 1 PCI: 00:19.1: enabled 0 PCI: 00:19.2: enabled 0 PCI: 00:1a.0: enabled 1 PCI: 00:1c.0: enabled 0 PCI: 00:1c.1: enabled 0 PCI: 00:1c.2: enabled 0 PCI: 00:1c.3: enabled 0 PCI: 00:1c.4: enabled 0 PCI: 00:1c.5: enabled 0 PCI: 00:1c.0: enabled 1 PCI: 00:1c.7: enabled 0 PCI: 00:1d.0: enabled 1 PCI: 00:1d.1: enabled 0 PCI: 00:1d.2: enabled 1 PCI: 00:1d.3: enabled 0 PCI: 00:1d.4: enabled 0 PCI: 00:1d.5: enabled 1 PCI: 00:1e.0: enabled 1 PCI: 00:1e.1: enabled 0 PCI: 00:1e.2: enabled 1 PCI: 00:1e.3: enabled 0 PCI: 00:1f.0: enabled 1 PCI: 00:1f.1: enabled 1 PCI: 00:1f.2: enabled 1 PCI: 00:1f.3: enabled 1 PCI: 00:1f.4: enabled 1 PCI: 00:1f.5: enabled 1 PCI: 00:1f.6: enabled 0 GENERIC: 0.0: enabled 1 USB0 port 0: enabled 1 I2C: 00:4a: enabled 1 I2C: 00:4a: enabled 1 I2C: 00:1a: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.0: enabled 1 SPI: 00: enabled 1 PNP: 0c09.0: enabled 1 USB2 port 0: enabled 1 USB2 port 1: enabled 1 USB2 port 2: enabled 1 USB2 port 3: enabled 1 USB2 port 5: enabled 1 USB2 port 6: enabled 0 USB2 port 9: enabled 1 USB3 port 0: enabled 1 USB3 port 1: enabled 1 USB3 port 2: enabled 1 USB3 port 3: enabled 1 USB3 port 4: enabled 1 USB2 port 4: enabled 1 USB3 port 5: enabled 1 APIC: 02: enabled 1 Compare with tree... Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 00: enabled 1 APIC: 02: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:04.0: enabled 1 GENERIC: 0.0: enabled 1 PCI: 00:05.0: enabled 0 PCI: 00:12.0: enabled 1 PCI: 00:12.5: enabled 0 PCI: 00:12.6: enabled 0 PCI: 00:14.0: enabled 1 USB0 port 0: enabled 1 USB2 port 0: enabled 1 USB2 port 1: enabled 1 USB2 port 2: enabled 1 USB2 port 3: enabled 1 USB2 port 5: enabled 1 USB2 port 6: enabled 0 USB2 port 9: enabled 1 USB3 port 0: enabled 1 USB3 port 1: enabled 1 USB3 port 2: enabled 1 USB3 port 3: enabled 1 USB3 port 4: enabled 1 USB2 port 4: enabled 1 USB3 port 5: enabled 1 PCI: 00:14.1: enabled 0 PCI: 00:14.3: enabled 1 PCI: 00:14.5: enabled 1 PCI: 00:15.0: enabled 0 PCI: 00:15.1: enabled 0 PCI: 00:15.2: enabled 1 I2C: 00:4a: enabled 1 PCI: 00:15.3: enabled 1 I2C: 00:4a: enabled 1 PCI: 00:16.0: enabled 1 PCI: 00:16.1: enabled 0 PCI: 00:16.2: enabled 0 PCI: 00:16.3: enabled 0 PCI: 00:16.4: enabled 0 PCI: 00:16.5: enabled 0 PCI: 00:17.0: enabled 1 PCI: 00:19.0: enabled 1 I2C: 00:1a: enabled 1 PCI: 00:19.1: enabled 0 PCI: 00:19.2: enabled 0 PCI: 00:1a.0: enabled 1 PCI: 00:1c.0: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:1e.0: enabled 1 PCI: 00:1e.1: enabled 0 PCI: 00:1e.2: enabled 1 SPI: 00: enabled 1 PCI: 00:1e.3: enabled 0 PCI: 00:1f.0: enabled 1 PNP: 0c09.0: enabled 1 PCI: 00:1f.1: enabled 1 PCI: 00:1f.2: enabled 1 PCI: 00:1f.3: enabled 1 PCI: 00:1f.4: enabled 1 PCI: 00:1f.5: enabled 1 PCI: 00:1f.6: enabled 0 Root Device scanning... scan_static_bus for Root Device CPU_CLUSTER: 0 enabled DOMAIN: 0000 enabled DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [8086/0000] ops PCI: 00:00.0 [8086/9b71] enabled PCI: 00:02.0 [8086/0000] bus ops PCI: 00:02.0 [8086/9baa] enabled PCI: 00:04.0 [8086/0000] bus ops PCI: 00:04.0 [8086/1903] enabled PCI: 00:08.0 [8086/1911] enabled PCI: 00:12.0 [8086/02f9] enabled PCI: 00:14.0 [8086/0000] bus ops PCI: 00:14.0 [8086/02ed] enabled PCI: 00:14.2 [8086/02ef] enabled PCI: 00:14.3 [8086/02f0] enabled PCI: 00:14.5 [8086/0000] ops PCI: 00:14.5 [8086/02f5] enabled PCI: 00:15.0 [8086/0000] bus ops PCI: 00:15.0 [8086/02e8] disabled PCI: 00:15.2 [8086/0000] bus ops PCI: 00:15.2 [8086/02ea] enabled PCI: 00:15.3 [8086/0000] bus ops PCI: 00:15.3 [8086/02eb] enabled PCI: 00:16.0 [8086/0000] ops PCI: 00:16.0 [8086/02e0] enabled PCI: Static device PCI: 00:17.0 not found, disabling it. PCI: 00:19.0 [8086/0000] bus ops PCI: 00:19.0 [8086/02c5] enabled PCI: 00:1a.0 [8086/0000] ops PCI: 00:1a.0 [8086/02c4] enabled PCI: 00:1c.0 [8086/0000] bus ops PCI: 00:1c.0 [8086/02be] enabled PCI: 00:1e.0 [8086/0000] ops PCI: 00:1e.0 [8086/02a8] enabled PCI: 00:1e.2 [8086/0000] bus ops PCI: 00:1e.2 [8086/02aa] enabled PCI: 00:1f.0 [8086/0000] bus ops PCI: 00:1f.0 [8086/0285] enabled PCI: Static device PCI: 00:1f.1 not found, disabling it. PCI: Static device PCI: 00:1f.2 not found, disabling it. PCI: 00:1f.3 [8086/0000] bus ops PCI: 00:1f.3 [8086/02c8] enabled PCI: 00:1f.4 [8086/0000] bus ops PCI: 00:1f.4 [8086/02a3] enabled PCI: 00:1f.5 [8086/0000] bus ops PCI: 00:1f.5 [8086/02a4] enabled PCI: Leftover static devices: PCI: 00:05.0 PCI: 00:12.5 PCI: 00:12.6 PCI: 00:14.1 PCI: 00:15.1 PCI: 00:16.1 PCI: 00:16.2 PCI: 00:16.3 PCI: 00:16.4 PCI: 00:16.5 PCI: 00:17.0 PCI: 00:19.1 PCI: 00:19.2 PCI: 00:1e.1 PCI: 00:1e.3 PCI: 00:1f.1 PCI: 00:1f.2 PCI: 00:1f.6 PCI: Check your devicetree.cb. PCI: 00:02.0 scanning... scan_generic_bus for PCI: 00:02.0 scan_generic_bus for PCI: 00:02.0 done scan_bus: bus PCI: 00:02.0 finished in 7 msecs PCI: 00:04.0 scanning... scan_generic_bus for PCI: 00:04.0 bus: PCI: 00:04.0[0]->GENERIC: 0.0 enabled scan_generic_bus for PCI: 00:04.0 done scan_bus: bus PCI: 00:04.0 finished in 11 msecs PCI: 00:14.0 scanning... scan_static_bus for PCI: 00:14.0 USB0 port 0 enabled USB0 port 0 scanning... scan_static_bus for USB0 port 0 USB2 port 0 enabled USB2 port 1 enabled USB2 port 2 enabled USB2 port 3 enabled USB2 port 5 enabled USB2 port 6 disabled USB2 port 9 enabled USB3 port 0 enabled USB3 port 1 enabled USB3 port 2 enabled USB3 port 3 enabled USB3 port 4 enabled USB2 port 4 enabled USB3 port 5 enabled USB2 port 0 scanning... scan_static_bus for USB2 port 0 scan_static_bus for USB2 port 0 done scan_bus: bus USB2 port 0 finished in 6 msecs USB2 port 1 scanning... scan_static_bus for USB2 port 1 scan_static_bus for USB2 port 1 done scan_bus: bus USB2 port 1 finished in 6 msecs USB2 port 2 scanning... scan_static_bus for USB2 port 2 scan_static_bus for USB2 port 2 done scan_bus: bus USB2 port 2 finished in 6 msecs USB2 port 3 scanning... scan_static_bus for USB2 port 3 scan_static_bus for USB2 port 3 done scan_bus: bus USB2 port 3 finished in 6 msecs USB2 port 5 scanning... scan_static_bus for USB2 port 5 scan_static_bus for USB2 port 5 done scan_bus: bus USB2 port 5 finished in 6 msecs USB2 port 9 scanning... scan_static_bus for USB2 port 9 scan_static_bus for USB2 port 9 done scan_bus: bus USB2 port 9 finished in 6 msecs USB3 port 0 scanning... scan_static_bus for USB3 port 0 scan_static_bus for USB3 port 0 done scan_bus: bus USB3 port 0 finished in 6 msecs USB3 port 1 scanning... scan_static_bus for USB3 port 1 scan_static_bus for USB3 port 1 done scan_bus: bus USB3 port 1 finished in 6 msecs USB3 port 2 scanning... scan_static_bus for USB3 port 2 scan_static_bus for USB3 port 2 done scan_bus: bus USB3 port 2 finished in 6 msecs USB3 port 3 scanning... scan_static_bus for USB3 port 3 scan_static_bus for USB3 port 3 done scan_bus: bus USB3 port 3 finished in 6 msecs USB3 port 4 scanning... scan_static_bus for USB3 port 4 scan_static_bus for USB3 port 4 done scan_bus: bus USB3 port 4 finished in 6 msecs USB2 port 4 scanning... scan_static_bus for USB2 port 4 scan_static_bus for USB2 port 4 done scan_bus: bus USB2 port 4 finished in 6 msecs USB3 port 5 scanning... scan_static_bus for USB3 port 5 scan_static_bus for USB3 port 5 done scan_bus: bus USB3 port 5 finished in 6 msecs scan_static_bus for USB0 port 0 done scan_bus: bus USB0 port 0 finished in 219 msecs scan_static_bus for PCI: 00:14.0 done scan_bus: bus PCI: 00:14.0 finished in 236 msecs PCI: 00:15.2 scanning... scan_generic_bus for PCI: 00:15.2 bus: PCI: 00:15.2[0]->I2C: 02:4a enabled scan_generic_bus for PCI: 00:15.2 done scan_bus: bus PCI: 00:15.2 finished in 11 msecs PCI: 00:15.3 scanning... scan_generic_bus for PCI: 00:15.3 bus: PCI: 00:15.3[0]->I2C: 03:4a enabled scan_generic_bus for PCI: 00:15.3 done scan_bus: bus PCI: 00:15.3 finished in 11 msecs PCI: 00:19.0 scanning... scan_generic_bus for PCI: 00:19.0 bus: PCI: 00:19.0[0]->I2C: 04:1a enabled scan_generic_bus for PCI: 00:19.0 done scan_bus: bus PCI: 00:19.0 finished in 11 msecs PCI: 00:1c.0 scanning... do_pci_scan_bridge for PCI: 00:1c.0 PCI: pci_scan_bus for bus 01 PCI: 01:00.0 [10ec/8168] ops PCI: 01:00.0 [10ec/8168] enabled Enabling Common Clock Configuration L1 Sub-State supported from root port 28 L1 Sub-State Support = 0xf CommonModeRestoreTime = 0x96 Power On Value = 0xf, Power On Scale = 0x1 ASPM: Enabled L1 PCIe: Max_Payload_Size adjusted to 128 scan_bus: bus PCI: 00:1c.0 finished in 36 msecs PCI: 00:1e.2 scanning... scan_generic_bus for PCI: 00:1e.2 bus: PCI: 00:1e.2[0]->SPI: 00 enabled scan_generic_bus for PCI: 00:1e.2 done scan_bus: bus PCI: 00:1e.2 finished in 11 msecs PCI: 00:1f.0 scanning... scan_static_bus for PCI: 00:1f.0 PNP: 0c09.0 enabled PNP: 0c09.0 scanning... scan_static_bus for PNP: 0c09.0 scan_static_bus for PNP: 0c09.0 done scan_bus: bus PNP: 0c09.0 finished in 6 msecs scan_static_bus for PCI: 00:1f.0 done scan_bus: bus PCI: 00:1f.0 finished in 23 msecs PCI: 00:1f.3 scanning... scan_static_bus for PCI: 00:1f.3 scan_static_bus for PCI: 00:1f.3 done scan_bus: bus PCI: 00:1f.3 finished in 7 msecs PCI: 00:1f.4 scanning... scan_generic_bus for PCI: 00:1f.4 scan_generic_bus for PCI: 00:1f.4 done scan_bus: bus PCI: 00:1f.4 finished in 7 msecs PCI: 00:1f.5 scanning... scan_generic_bus for PCI: 00:1f.5 scan_generic_bus for PCI: 00:1f.5 done scan_bus: bus PCI: 00:1f.5 finished in 7 msecs scan_bus: bus DOMAIN: 0000 finished in 653 msecs scan_static_bus for Root Device done scan_bus: bus Root Device finished in 672 msecs done BS: BS_DEV_ENUMERATE run times (exec / console): 11 / 1037 ms FMAP: area RECOVERY_MRC_CACHE found @ ad0000 (65536 bytes) MRC: Checking cached data update for 'RECOVERY_MRC_CACHE'. SF: Detected 00 0000 with sector size 0x1000, total 0x1000000 MRC: 'RECOVERY_MRC_CACHE' does not need update. Chrome EC: UHEPI supported FMAP: area UNIFIED_MRC_CACHE found @ ad0000 (131072 bytes) SPI flash protection: WPSW=0 SRP0=0 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'. BS: BS_DEV_ENUMERATE exit times (exec / console): 2 / 39 ms found VGA at PCI: 00:02.0 Setting up VGA for PCI: 00:02.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done DOMAIN: 0000 read_resources bus 0 link: 0 PCI: 00:04.0 read_resources bus 1 link: 0 PCI: 00:04.0 read_resources bus 1 link: 0 done PCI: 00:14.0 read_resources bus 0 link: 0 USB0 port 0 read_resources bus 0 link: 0 USB0 port 0 read_resources bus 0 link: 0 done PCI: 00:14.0 read_resources bus 0 link: 0 done PCI: 00:15.2 read_resources bus 2 link: 0 PCI: 00:15.2 read_resources bus 2 link: 0 done PCI: 00:15.3 read_resources bus 3 link: 0 PCI: 00:15.3 read_resources bus 3 link: 0 done PCI: 00:19.0 read_resources bus 4 link: 0 PCI: 00:19.0 read_resources bus 4 link: 0 done PCI: 00:1c.0 read_resources bus 1 link: 0 PCI: 00:1c.0 read_resources bus 1 link: 0 done PCI: 00:1e.2 read_resources bus 5 link: 0 PCI: 00:1e.2 read_resources bus 5 link: 0 done PCI: 00:1f.0 read_resources bus 0 link: 0 PCI: 00:1f.0 read_resources bus 0 link: 0 done DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 APIC: 02 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100 PCI: 00:00.0 PCI: 00:00.0 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0 PCI: 00:00.0 resource base fed10000 size 8000 align 0 gran 0 limit 0 flags f0000200 index 1 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3 PCI: 00:00.0 resource base fc000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5 PCI: 00:00.0 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 6 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 9 PCI: 00:00.0 resource base c0000 size 99f40000 align 0 gran 0 limit 0 flags e0004200 index a PCI: 00:00.0 resource base 9a000000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index b PCI: 00:00.0 resource base 9b000000 size 4800000 align 0 gran 0 limit 0 flags f0000200 index c PCI: 00:00.0 resource base 100000000 size 5e800000 align 0 gran 0 limit 0 flags e0004200 index d PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index e PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index f PCI: 00:02.0 PCI: 00:02.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10 PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18 PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20 PCI: 00:04.0 child on link 0 GENERIC: 0.0 PCI: 00:04.0 resource base 0 size 8000 align 15 gran 15 limit ffffffffffffffff flags 201 index 10 GENERIC: 0.0 PCI: 00:08.0 PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10 PCI: 00:12.0 PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10 PCI: 00:14.0 child on link 0 USB0 port 0 PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10 USB0 port 0 child on link 0 USB2 port 0 USB2 port 0 USB2 port 1 USB2 port 2 USB2 port 3 USB2 port 5 USB2 port 6 USB2 port 9 USB3 port 0 USB3 port 1 USB3 port 2 USB3 port 3 USB3 port 4 USB2 port 4 USB3 port 5 PCI: 00:14.2 PCI: 00:14.2 resource base 0 size 2000 align 13 gran 13 limit ffffffffffffffff flags 201 index 10 PCI: 00:14.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18 PCI: 00:14.3 PCI: 00:14.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 PCI: 00:14.5 PCI: 00:14.5 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10 PCI: 00:15.0 PCI: 00:15.2 child on link 0 I2C: 02:4a PCI: 00:15.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10 I2C: 02:4a PCI: 00:15.3 child on link 0 I2C: 03:4a PCI: 00:15.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10 I2C: 03:4a PCI: 00:16.0 PCI: 00:16.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10 PCI: 00:19.0 child on link 0 I2C: 04:1a PCI: 00:19.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10 I2C: 04:1a PCI: 00:1a.0 PCI: 00:1a.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10 PCI: 00:1c.0 child on link 0 PCI: 01:00.0 PCI: 00:1c.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:1c.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 01:00.0 PCI: 01:00.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 10 PCI: 01:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18 PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 20 PCI: 00:1e.0 PCI: 00:1e.0 resource base fe032000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10 PCI: 00:1e.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18 PCI: 00:1e.2 child on link 0 SPI: 00 PCI: 00:1e.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10 SPI: 00 PCI: 00:1f.0 child on link 0 PNP: 0c09.0 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0 PCI: 00:1f.0 resource base 1800 size 100 align 0 gran 0 limit 0 flags c0000100 index 20 PNP: 0c09.0 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0 PCI: 00:1f.3 PCI: 00:1f.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 PCI: 00:1f.3 resource base 0 size 100000 align 20 gran 20 limit ffffffffffffffff flags 201 index 20 PCI: 00:1f.4 PCI: 00:1f.4 resource base efa0 size 20 align 0 gran 0 limit efbf flags f0000100 index 20 PCI: 00:1f.4 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 10 PCI: 00:1f.5 PCI: 00:1f.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 ==== Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) === PCI: 00:1c.0 io: size: 0 align: 12 gran: 12 limit: ffff PCI: 01:00.0 10 * [0x0 - 0xff] io PCI: 00:1c.0 io: size: 1000 align: 12 gran: 12 limit: ffff done PCI: 00:1c.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff PCI: 01:00.0 20 * [0x0 - 0x3fff] mem PCI: 01:00.0 18 * [0x4000 - 0x4fff] mem PCI: 00:1c.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:1c.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) === DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff update_constraints: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed) update_constraints: PCI: 00:1f.0 20 base 00001800 limit 000018ff io (fixed) update_constraints: PNP: 0c09.0 00 base 00000800 limit 000009fe io (fixed) update_constraints: PCI: 00:1f.4 20 base 0000efa0 limit 0000efbf io (fixed) DOMAIN: 0000: Resource ranges: * Base: 1000, Size: 800, Tag: 100 * Base: 1900, Size: d6a0, Tag: 100 * Base: efc0, Size: 1040, Tag: 100 PCI: 00:1c.0 1c * [0x2000 - 0x2fff] limit: 2fff io PCI: 00:02.0 20 * [0x1000 - 0x103f] limit: 103f io DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff update_constraints: PCI: 00:00.0 00 base e0000000 limit efffffff mem (fixed) update_constraints: PCI: 00:00.0 01 base fed10000 limit fed17fff mem (fixed) update_constraints: PCI: 00:00.0 02 base feda0000 limit feda0fff mem (fixed) update_constraints: PCI: 00:00.0 03 base feda1000 limit feda1fff mem (fixed) update_constraints: PCI: 00:00.0 04 base fc000000 limit fc000fff mem (fixed) update_constraints: PCI: 00:00.0 05 base fed80000 limit fed83fff mem (fixed) update_constraints: PCI: 00:00.0 06 base fe000000 limit fe00ffff mem (fixed) update_constraints: PCI: 00:00.0 07 base fed90000 limit fed90fff mem (fixed) update_constraints: PCI: 00:00.0 08 base fed91000 limit fed91fff mem (fixed) update_constraints: PCI: 00:00.0 09 base 00000000 limit 0009ffff mem (fixed) update_constraints: PCI: 00:00.0 0a base 000c0000 limit 99ffffff mem (fixed) update_constraints: PCI: 00:00.0 0b base 9a000000 limit 9affffff mem (fixed) update_constraints: PCI: 00:00.0 0c base 9b000000 limit 9f7fffff mem (fixed) update_constraints: PCI: 00:00.0 0d base 100000000 limit 15e7fffff mem (fixed) update_constraints: PCI: 00:00.0 0e base 000a0000 limit 000bffff mem (fixed) update_constraints: PCI: 00:00.0 0f base 000c0000 limit 000fffff mem (fixed) update_constraints: PCI: 00:1e.0 10 base fe032000 limit fe032fff mem (fixed) DOMAIN: 0000: Resource ranges: * Base: 9f800000, Size: 40800000, Tag: 200 * Base: f0000000, Size: c000000, Tag: 200 * Base: fc001000, Size: 1fff000, Tag: 200 * Base: fe010000, Size: 22000, Tag: 200 * Base: fe033000, Size: cdd000, Tag: 200 * Base: fed18000, Size: 68000, Tag: 200 * Base: fed84000, Size: c000, Tag: 200 * Base: fed92000, Size: e000, Tag: 200 * Base: feda2000, Size: 125e000, Tag: 200 * Base: 15e800000, Size: 7ea1800000, Tag: 100200 PCI: 00:02.0 18 * [0xa0000000 - 0xafffffff] limit: afffffff prefmem PCI: 00:02.0 10 * [0xb0000000 - 0xb0ffffff] limit: b0ffffff mem PCI: 00:1c.0 20 * [0x9f800000 - 0x9f8fffff] limit: 9f8fffff mem PCI: 00:1f.3 20 * [0x9f900000 - 0x9f9fffff] limit: 9f9fffff mem PCI: 00:14.0 10 * [0x9fa00000 - 0x9fa0ffff] limit: 9fa0ffff mem PCI: 00:04.0 10 * [0x9fa10000 - 0x9fa17fff] limit: 9fa17fff mem PCI: 00:14.3 10 * [0x9fa18000 - 0x9fa1bfff] limit: 9fa1bfff mem PCI: 00:1f.3 10 * [0x9fa1c000 - 0x9fa1ffff] limit: 9fa1ffff mem PCI: 00:14.2 10 * [0x9fa20000 - 0x9fa21fff] limit: 9fa21fff mem PCI: 00:08.0 10 * [0x9fa22000 - 0x9fa22fff] limit: 9fa22fff mem PCI: 00:12.0 10 * [0x9fa23000 - 0x9fa23fff] limit: 9fa23fff mem PCI: 00:14.2 18 * [0x9fa24000 - 0x9fa24fff] limit: 9fa24fff mem PCI: 00:14.5 10 * [0x9fa25000 - 0x9fa25fff] limit: 9fa25fff mem PCI: 00:15.2 10 * [0x9fa26000 - 0x9fa26fff] limit: 9fa26fff mem PCI: 00:15.3 10 * [0x9fa27000 - 0x9fa27fff] limit: 9fa27fff mem PCI: 00:16.0 10 * [0x9fa28000 - 0x9fa28fff] limit: 9fa28fff mem PCI: 00:19.0 10 * [0x9fa29000 - 0x9fa29fff] limit: 9fa29fff mem PCI: 00:1a.0 10 * [0x9fa2a000 - 0x9fa2afff] limit: 9fa2afff mem PCI: 00:1e.0 18 * [0x9fa2b000 - 0x9fa2bfff] limit: 9fa2bfff mem PCI: 00:1e.2 10 * [0x9fa2c000 - 0x9fa2cfff] limit: 9fa2cfff mem PCI: 00:1f.5 10 * [0x9fa2d000 - 0x9fa2dfff] limit: 9fa2dfff mem PCI: 00:1f.4 10 * [0x9fa2e000 - 0x9fa2e0ff] limit: 9fa2e0ff mem DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff done PCI: 00:1c.0 io: base: 2000 size: 1000 align: 12 gran: 12 limit: 2fff PCI: 00:1c.0: Resource ranges: * Base: 2000, Size: 1000, Tag: 100 PCI: 01:00.0 10 * [0x2000 - 0x20ff] limit: 20ff io PCI: 00:1c.0 io: base: 2000 size: 1000 align: 12 gran: 12 limit: 2fff done PCI: 00:1c.0 mem: base: 9f800000 size: 100000 align: 20 gran: 20 limit: 9f8fffff PCI: 00:1c.0: Resource ranges: * Base: 9f800000, Size: 100000, Tag: 200 PCI: 01:00.0 20 * [0x9f800000 - 0x9f803fff] limit: 9f803fff mem PCI: 01:00.0 18 * [0x9f804000 - 0x9f804fff] limit: 9f804fff mem PCI: 00:1c.0 mem: base: 9f800000 size: 100000 align: 20 gran: 20 limit: 9f8fffff done === Resource allocator: DOMAIN: 0000 - resource allocation complete === Root Device assign_resources, bus 0 link: 0 DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:02.0 10 <- [0x00b0000000 - 0x00b0ffffff] size 0x01000000 gran 0x18 mem64 PCI: 00:02.0 18 <- [0x00a0000000 - 0x00afffffff] size 0x10000000 gran 0x1c prefmem64 PCI: 00:02.0 20 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io PCI: 00:04.0 10 <- [0x009fa10000 - 0x009fa17fff] size 0x00008000 gran 0x0f mem64 PCI: 00:04.0 assign_resources, bus 1 link: 0 PCI: 00:04.0 assign_resources, bus 1 link: 0 PCI: 00:08.0 10 <- [0x009fa22000 - 0x009fa22fff] size 0x00001000 gran 0x0c mem64 PCI: 00:12.0 10 <- [0x009fa23000 - 0x009fa23fff] size 0x00001000 gran 0x0c mem64 PCI: 00:14.0 10 <- [0x009fa00000 - 0x009fa0ffff] size 0x00010000 gran 0x10 mem64 PCI: 00:14.0 assign_resources, bus 0 link: 0 PCI: 00:14.0 assign_resources, bus 0 link: 0 PCI: 00:14.2 10 <- [0x009fa20000 - 0x009fa21fff] size 0x00002000 gran 0x0d mem64 PCI: 00:14.2 18 <- [0x009fa24000 - 0x009fa24fff] size 0x00001000 gran 0x0c mem64 PCI: 00:14.3 10 <- [0x009fa18000 - 0x009fa1bfff] size 0x00004000 gran 0x0e mem64 PCI: 00:14.5 10 <- [0x009fa25000 - 0x009fa25fff] size 0x00001000 gran 0x0c mem64 PCI: 00:15.2 10 <- [0x009fa26000 - 0x009fa26fff] size 0x00001000 gran 0x0c mem64 PCI: 00:15.2 assign_resources, bus 2 link: 0 PCI: 00:15.2 assign_resources, bus 2 link: 0 PCI: 00:15.3 10 <- [0x009fa27000 - 0x009fa27fff] size 0x00001000 gran 0x0c mem64 PCI: 00:15.3 assign_resources, bus 3 link: 0 PCI: 00:15.3 assign_resources, bus 3 link: 0 PCI: 00:16.0 10 <- [0x009fa28000 - 0x009fa28fff] size 0x00001000 gran 0x0c mem64 PCI: 00:19.0 10 <- [0x009fa29000 - 0x009fa29fff] size 0x00001000 gran 0x0c mem64 PCI: 00:19.0 assign_resources, bus 4 link: 0 PCI: 00:19.0 assign_resources, bus 4 link: 0 PCI: 00:1a.0 10 <- [0x009fa2a000 - 0x009fa2afff] size 0x00001000 gran 0x0c mem64 PCI: 00:1c.0 1c <- [0x0000002000 - 0x0000002fff] size 0x00001000 gran 0x0c bus 01 io PCI: 00:1c.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem PCI: 00:1c.0 20 <- [0x009f800000 - 0x009f8fffff] size 0x00100000 gran 0x14 bus 01 mem PCI: 00:1c.0 assign_resources, bus 1 link: 0 PCI: 01:00.0 10 <- [0x0000002000 - 0x00000020ff] size 0x00000100 gran 0x08 io PCI: 01:00.0 18 <- [0x009f804000 - 0x009f804fff] size 0x00001000 gran 0x0c mem64 PCI: 01:00.0 20 <- [0x009f800000 - 0x009f803fff] size 0x00004000 gran 0x0e mem64 PCI: 00:1c.0 assign_resources, bus 1 link: 0 PCI: 00:1e.0 18 <- [0x009fa2b000 - 0x009fa2bfff] size 0x00001000 gran 0x0c mem64 PCI: 00:1e.2 10 <- [0x009fa2c000 - 0x009fa2cfff] size 0x00001000 gran 0x0c mem64 PCI: 00:1e.2 assign_resources, bus 5 link: 0 PCI: 00:1e.2 assign_resources, bus 5 link: 0 PCI: 00:1f.0 assign_resources, bus 0 link: 0 PCI: 00:1f.0 assign_resources, bus 0 link: 0 LPC: Trying to open IO window from 800 size 1ff PCI: 00:1f.3 10 <- [0x009fa1c000 - 0x009fa1ffff] size 0x00004000 gran 0x0e mem64 PCI: 00:1f.3 20 <- [0x009f900000 - 0x009f9fffff] size 0x00100000 gran 0x14 mem64 PCI: 00:1f.4 10 <- [0x009fa2e000 - 0x009fa2e0ff] size 0x00000100 gran 0x08 mem64 PCI: 00:1f.5 10 <- [0x009fa2d000 - 0x009fa2dfff] size 0x00001000 gran 0x0c mem DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 00 APIC: 00 APIC: 02 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100 PCI: 00:00.0 PCI: 00:00.0 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0 PCI: 00:00.0 resource base fed10000 size 8000 align 0 gran 0 limit 0 flags f0000200 index 1 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3 PCI: 00:00.0 resource base fc000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5 PCI: 00:00.0 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 6 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 9 PCI: 00:00.0 resource base c0000 size 99f40000 align 0 gran 0 limit 0 flags e0004200 index a PCI: 00:00.0 resource base 9a000000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index b PCI: 00:00.0 resource base 9b000000 size 4800000 align 0 gran 0 limit 0 flags f0000200 index c PCI: 00:00.0 resource base 100000000 size 5e800000 align 0 gran 0 limit 0 flags e0004200 index d PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index e PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index f PCI: 00:02.0 PCI: 00:02.0 resource base b0000000 size 1000000 align 24 gran 24 limit b0ffffff flags 60000201 index 10 PCI: 00:02.0 resource base a0000000 size 10000000 align 28 gran 28 limit afffffff flags 60001201 index 18 PCI: 00:02.0 resource base 1000 size 40 align 6 gran 6 limit 103f flags 60000100 index 20 PCI: 00:04.0 child on link 0 GENERIC: 0.0 PCI: 00:04.0 resource base 9fa10000 size 8000 align 15 gran 15 limit 9fa17fff flags 60000201 index 10 GENERIC: 0.0 PCI: 00:08.0 PCI: 00:08.0 resource base 9fa22000 size 1000 align 12 gran 12 limit 9fa22fff flags 60000201 index 10 PCI: 00:12.0 PCI: 00:12.0 resource base 9fa23000 size 1000 align 12 gran 12 limit 9fa23fff flags 60000201 index 10 PCI: 00:14.0 child on link 0 USB0 port 0 PCI: 00:14.0 resource base 9fa00000 size 10000 align 16 gran 16 limit 9fa0ffff flags 60000201 index 10 USB0 port 0 child on link 0 USB2 port 0 USB2 port 0 USB2 port 1 USB2 port 2 USB2 port 3 USB2 port 5 USB2 port 6 USB2 port 9 USB3 port 0 USB3 port 1 USB3 port 2 USB3 port 3 USB3 port 4 USB2 port 4 USB3 port 5 PCI: 00:14.2 PCI: 00:14.2 resource base 9fa20000 size 2000 align 13 gran 13 limit 9fa21fff flags 60000201 index 10 PCI: 00:14.2 resource base 9fa24000 size 1000 align 12 gran 12 limit 9fa24fff flags 60000201 index 18 PCI: 00:14.3 PCI: 00:14.3 resource base 9fa18000 size 4000 align 14 gran 14 limit 9fa1bfff flags 60000201 index 10 PCI: 00:14.5 PCI: 00:14.5 resource base 9fa25000 size 1000 align 12 gran 12 limit 9fa25fff flags 60000201 index 10 PCI: 00:15.0 PCI: 00:15.2 child on link 0 I2C: 02:4a PCI: 00:15.2 resource base 9fa26000 size 1000 align 12 gran 12 limit 9fa26fff flags 60000201 index 10 I2C: 02:4a PCI: 00:15.3 child on link 0 I2C: 03:4a PCI: 00:15.3 resource base 9fa27000 size 1000 align 12 gran 12 limit 9fa27fff flags 60000201 index 10 I2C: 03:4a PCI: 00:16.0 PCI: 00:16.0 resource base 9fa28000 size 1000 align 12 gran 12 limit 9fa28fff flags 60000201 index 10 PCI: 00:19.0 child on link 0 I2C: 04:1a PCI: 00:19.0 resource base 9fa29000 size 1000 align 12 gran 12 limit 9fa29fff flags 60000201 index 10 I2C: 04:1a PCI: 00:1a.0 PCI: 00:1a.0 resource base 9fa2a000 size 1000 align 12 gran 12 limit 9fa2afff flags 60000201 index 10 PCI: 00:1c.0 child on link 0 PCI: 01:00.0 PCI: 00:1c.0 resource base 2000 size 1000 align 12 gran 12 limit 2fff flags 60080102 index 1c PCI: 00:1c.0 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24 PCI: 00:1c.0 resource base 9f800000 size 100000 align 20 gran 20 limit 9f8fffff flags 60080202 index 20 PCI: 01:00.0 PCI: 01:00.0 resource base 2000 size 100 align 8 gran 8 limit 20ff flags 60000100 index 10 PCI: 01:00.0 resource base 9f804000 size 1000 align 12 gran 12 limit 9f804fff flags 60000201 index 18 PCI: 01:00.0 resource base 9f800000 size 4000 align 14 gran 14 limit 9f803fff flags 60000201 index 20 PCI: 00:1e.0 PCI: 00:1e.0 resource base fe032000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10 PCI: 00:1e.0 resource base 9fa2b000 size 1000 align 12 gran 12 limit 9fa2bfff flags 60000201 index 18 PCI: 00:1e.2 child on link 0 SPI: 00 PCI: 00:1e.2 resource base 9fa2c000 size 1000 align 12 gran 12 limit 9fa2cfff flags 60000201 index 10 SPI: 00 PCI: 00:1f.0 child on link 0 PNP: 0c09.0 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0 PCI: 00:1f.0 resource base 1800 size 100 align 0 gran 0 limit 0 flags c0000100 index 20 PNP: 0c09.0 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0 PCI: 00:1f.3 PCI: 00:1f.3 resource base 9fa1c000 size 4000 align 14 gran 14 limit 9fa1ffff flags 60000201 index 10 PCI: 00:1f.3 resource base 9f900000 size 100000 align 20 gran 20 limit 9f9fffff flags 60000201 index 20 PCI: 00:1f.4 PCI: 00:1f.4 resource base efa0 size 20 align 0 gran 0 limit efbf flags f0000100 index 20 PCI: 00:1f.4 resource base 9fa2e000 size 100 align 12 gran 8 limit 9fa2e0ff flags 60000201 index 10 PCI: 00:1f.5 PCI: 00:1f.5 resource base 9fa2d000 size 1000 align 12 gran 12 limit 9fa2dfff flags 60000200 index 10 Done allocating resources. BS: BS_DEV_RESOURCES run times (exec / console): 30 / 2220 ms Enabling resources... PCI: 00:00.0 subsystem <- 8086/9b71 PCI: 00:00.0 cmd <- 06 PCI: 00:02.0 subsystem <- 8086/9baa PCI: 00:02.0 cmd <- 03 PCI: 00:04.0 subsystem <- 8086/1903 PCI: 00:04.0 cmd <- 02 PCI: 00:08.0 cmd <- 06 PCI: 00:12.0 subsystem <- 8086/02f9 PCI: 00:12.0 cmd <- 02 PCI: 00:14.0 subsystem <- 8086/02ed PCI: 00:14.0 cmd <- 02 PCI: 00:14.2 cmd <- 02 PCI: 00:14.3 subsystem <- 8086/02f0 PCI: 00:14.3 cmd <- 02 PCI: 00:14.5 subsystem <- 8086/02f5 PCI: 00:14.5 cmd <- 06 PCI: 00:15.2 subsystem <- 8086/02ea PCI: 00:15.2 cmd <- 02 PCI: 00:15.3 subsystem <- 8086/02eb PCI: 00:15.3 cmd <- 02 PCI: 00:16.0 subsystem <- 8086/02e0 PCI: 00:16.0 cmd <- 02 PCI: 00:19.0 subsystem <- 8086/02c5 PCI: 00:19.0 cmd <- 02 PCI: 00:1a.0 subsystem <- 8086/02c4 PCI: 00:1a.0 cmd <- 06 PCI: 00:1c.0 bridge ctrl <- 0013 PCI: 00:1c.0 subsystem <- 8086/02be PCI: 00:1c.0 cmd <- 07 PCI: 00:1e.0 subsystem <- 8086/02a8 PCI: 00:1e.0 cmd <- 06 PCI: 00:1e.2 subsystem <- 8086/02aa PCI: 00:1e.2 cmd <- 06 PCI: 00:1f.0 subsystem <- 8086/0285 PCI: 00:1f.0 cmd <- 407 PCI: 00:1f.3 subsystem <- 8086/02c8 PCI: 00:1f.3 cmd <- 02 PCI: 00:1f.4 subsystem <- 8086/02a3 PCI: 00:1f.4 cmd <- 03 PCI: 00:1f.5 subsystem <- 8086/02a4 PCI: 00:1f.5 cmd <- 406 PCI: 01:00.0 cmd <- 03 done. BS: BS_DEV_ENABLE run times (exec / console): 11 / 126 ms Initializing devices... Root Device init Chrome EC: Set SMI mask to 0x0000000000000000 FMAP: area RW_ELOG found @ af0000 (16384 bytes) ELOG: NV offset 0xaf0000 size 0x4000 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024 ELOG: Event(17) added with size 13 at 2024-05-03 11:44:59 UTC ELOG: Event(91) added with size 10 at 2024-05-03 11:44:59 UTC Chrome EC: clear events_b mask to 0x0000000000000004 Chrome EC: Set S5 LAZY WAKE mask to 0x0000000000000004 Chrome EC: Set S3 LAZY WAKE mask to 0x0000000000000004 Chrome EC: Set S0iX LAZY WAKE mask to 0x0000000000080004 Chrome EC: Set WAKE mask to 0x0000000000000000 Root Device init finished in 63 msecs PCI: 00:00.0 init CPU TDP = 15 Watts CPU PL1 = 15 Watts CPU PL2 = 35 Watts CPU PsysPL2 = 65 Watts PCI: 00:00.0 init finished in 9 msecs PCI: 00:02.0 init GMA: Found VBT in CBFS GMA: Found valid VBT in CBFS PCI: 00:02.0 init finished in 5 msecs PCI: 00:08.0 init PCI: 00:08.0 init finished in 0 msecs PCI: 00:12.0 init PCI: 00:12.0 init finished in 0 msecs PCI: 00:14.0 init PCI: 00:14.0 init finished in 0 msecs PCI: 00:14.2 init PCI: 00:14.2 init finished in 0 msecs PCI: 00:14.3 init PCI: 00:14.3 init finished in 0 msecs PCI: 00:15.2 init I2C bus 2 version 0x3132322a DW I2C bus 2 at 0x9fa26000 (400 KHz) PCI: 00:15.2 init finished in 6 msecs PCI: 00:15.3 init I2C bus 3 version 0x3132322a DW I2C bus 3 at 0x9fa27000 (400 KHz) PCI: 00:15.3 init finished in 6 msecs PCI: 00:16.0 init PCI: 00:16.0 init finished in 0 msecs PCI: 00:19.0 init I2C bus 4 version 0x3132322a DW I2C bus 4 at 0x9fa29000 (400 KHz) PCI: 00:19.0 init finished in 6 msecs PCI: 00:1a.0 init PCI: 00:1a.0 init finished in 0 msecs PCI: 00:1c.0 init Initializing PCH PCIe bridge. PCI: 00:1c.0 init finished in 3 msecs PCI: 00:1f.0 init IOAPIC: Initializing IOAPIC at 0xfec00000 IOAPIC: Bootstrap Processor Local APIC = 0x00 IOAPIC: ID = 0x02 IOAPIC: Dumping registers reg 0x0000: 0x02000000 reg 0x0001: 0x00770020 reg 0x0002: 0x00000000 PCI: 00:1f.0 init finished in 21 msecs PCI: 00:1f.4 init PCI: 00:1f.4 init finished in 0 msecs PCI: 01:00.0 init FMAP: area RO_VPD found @ c00000 (16384 bytes) Error: Could not locate 'ethernet_mac0' in VPD r8168: mac address not found in VPD, using default 00:e0:4c:00:c0:b0 r8168: ignore invalid MAC address in cbfs r8168: Resetting NIC...done r8168: Programming MAC Address...done r8168: Customized LED 0x5af r8168: read back LED setting as 0x5af PCI: 01:00.0 init finished in 35 msecs PNP: 0c09.0 init Google Chrome EC uptime: 1572123.311 seconds Google Chrome AP resets since EC boot: 3677 Google Chrome most recent AP reset causes: 1568026.335: 32775 shutdown: entering G3 1568245.658: 32775 shutdown: entering G3 1568255.037: 32774 shutdown: by console command 1572108.128: 32774 shutdown: by console command Google Chrome EC reset flags at last EC boot: reset-pin PNP: 0c09.0 init finished in 37 msecs Devices initialized Show all devs... After init. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 DOMAIN: 0000: enabled 1 APIC: 00: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:04.0: enabled 1 PCI: 00:05.0: enabled 0 PCI: 00:12.0: enabled 1 PCI: 00:12.5: enabled 0 PCI: 00:12.6: enabled 0 PCI: 00:14.0: enabled 1 PCI: 00:14.1: enabled 0 PCI: 00:14.3: enabled 1 PCI: 00:14.5: enabled 1 PCI: 00:15.0: enabled 0 PCI: 00:15.1: enabled 0 PCI: 00:15.2: enabled 1 PCI: 00:15.3: enabled 1 PCI: 00:16.0: enabled 1 PCI: 00:16.1: enabled 0 PCI: 00:16.2: enabled 0 PCI: 00:16.3: enabled 0 PCI: 00:16.4: enabled 0 PCI: 00:16.5: enabled 0 PCI: 00:17.0: enabled 0 PCI: 00:19.0: enabled 1 PCI: 00:19.1: enabled 0 PCI: 00:19.2: enabled 0 PCI: 00:1a.0: enabled 1 PCI: 00:1c.0: enabled 0 PCI: 00:1c.1: enabled 0 PCI: 00:1c.2: enabled 0 PCI: 00:1c.3: enabled 0 PCI: 00:1c.4: enabled 0 PCI: 00:1c.5: enabled 0 PCI: 00:1c.0: enabled 1 PCI: 00:1c.7: enabled 0 PCI: 00:1d.0: enabled 1 PCI: 00:1d.1: enabled 0 PCI: 00:1d.2: enabled 1 PCI: 00:1d.3: enabled 0 PCI: 00:1d.4: enabled 0 PCI: 00:1d.5: enabled 1 PCI: 00:1e.0: enabled 1 PCI: 00:1e.1: enabled 0 PCI: 00:1e.2: enabled 1 PCI: 00:1e.3: enabled 0 PCI: 00:1f.0: enabled 1 PCI: 00:1f.1: enabled 0 PCI: 00:1f.2: enabled 0 PCI: 00:1f.3: enabled 1 PCI: 00:1f.4: enabled 1 PCI: 00:1f.5: enabled 1 PCI: 00:1f.6: enabled 0 GENERIC: 0.0: enabled 1 USB0 port 0: enabled 1 I2C: 02:4a: enabled 1 I2C: 03:4a: enabled 1 I2C: 04:1a: enabled 1 PCI: 01:00.0: enabled 1 PCI: 00:00.0: enabled 1 SPI: 00: enabled 1 PNP: 0c09.0: enabled 1 USB2 port 0: enabled 1 USB2 port 1: enabled 1 USB2 port 2: enabled 1 USB2 port 3: enabled 1 USB2 port 5: enabled 1 USB2 port 6: enabled 0 USB2 port 9: enabled 1 USB3 port 0: enabled 1 USB3 port 1: enabled 1 USB3 port 2: enabled 1 USB3 port 3: enabled 1 USB3 port 4: enabled 1 USB2 port 4: enabled 1 USB3 port 5: enabled 1 APIC: 02: enabled 1 PCI: 00:08.0: enabled 1 PCI: 00:14.2: enabled 1 BS: BS_DEV_INIT run times (exec / console): 29 / 487 ms Disabling ACPI via APMC. APMC done. ELOG: Event(92) added with size 9 at 2024-05-03 11:44:59 UTC ELOG: Event(93) added with size 9 at 2024-05-03 11:44:59 UTC ELOG: Event(9E) added with size 10 at 2024-05-03 11:44:59 UTC ELOG: Event(9F) added with size 14 at 2024-05-03 11:44:59 UTC BS: BS_DEV_INIT exit times (exec / console): 5 / 28 ms ELOG: Event(A1) added with size 10 at 2024-05-03 11:44:59 UTC elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b ELOG: Event(A0) added with size 9 at 2024-05-03 11:44:59 UTC elog_add_boot_reason: Logged dev mode boot BS: BS_POST_DEVICE entry times (exec / console): 1 / 24 ms Finalize devices... Devices finalized BS: BS_POST_DEVICE run times (exec / console): 0 / 4 ms FMAP: area RW_NVRAM found @ afa000 (20480 bytes) BS: BS_POST_DEVICE exit times (exec / console): 0 / 5 ms ME: HFSTS1 : 0x80030045 ME: HFSTS2 : 0x30280136 ME: HFSTS3 : 0x00000050 ME: HFSTS4 : 0x00004800 ME: HFSTS5 : 0x00000000 ME: HFSTS6 : 0x40400006 ME: Manufacturing Mode : NO ME: FW Partition Table : OK ME: Bringup Loader Failure : NO ME: Firmware Init Complete : NO ME: Boot Options Present : NO ME: Update In Progress : NO ME: D0i3 Support : YES ME: Low Power State Enabled : NO ME: CPU Replaced : YES ME: CPU Replacement Valid : YES ME: Current Working State : 5 ME: Current Operation State : 1 ME: Current Operation Mode : 3 ME: Error Code : 0 ME: CPU Debug Disabled : YES ME: TXT Support : NO BS: BS_OS_RESUME_CHECK exit times (exec / console): 0 / 77 ms FMAP: area COREBOOT found @ c08000 (4161536 bytes) CBFS: Locating 'fallback/dsdt.aml' CBFS: Found @ offset 636c0 size 32e0 FMAP: area COREBOOT found @ c08000 (4161536 bytes) CBFS: Locating 'fallback/slic' CBFS: 'fallback/slic' not found. ACPI: Writing ACPI tables at 99b31000. ACPI: * FACS ACPI: * DSDT Ramoops buffer: 0x100000@0x99a30000. FMAP: area RO_VPD found @ c00000 (16384 bytes) FMAP: area RW_VPD found @ af8000 (8192 bytes) Google Chrome EC: version: ro: puff_v2.0.4638-67e4d7990 rw: puff_v2.0.4638-67e4d7990 running image: 1 PCI space above 4GB MMIO is at 0x15e800000, len = 0x7ea1800000 ACPI: * FADT SCI is IRQ9 ACPI: added table 1/32, length now 40 ACPI: * SSDT Found 1 CPU(s) with 2 core(s) each. \_SB.PCI0.WFA3.WFA3: Intel WiFi PCI: 00:14.3 \_SB.DPTF: Intel DPTF at GENERIC: 0.0 \_SB.PCI0.I2C2.PS17: Parade PS175 at I2C: 02:4a \_SB.PCI0.I2C3.RTD2: Realtek RTD2142 at I2C: 03:4a \_SB.PCI0.I2C4.RT58: Realtek RT5682 at I2C: 04:1a \_SB.PCI0.RP01.RLTK.RLTK: Realtek r8168 PCI: 01:00.0 \_SB.PCI0.SPI0.S001: SPI Device at SPI: 00 EC returned error result code 3 EC returned error result code 1 PS2K: Bad resp from EC. Vivaldi disabled! \_SB.PCI0.XHCI.RHUB.HS01: USB2 Type-A Front Left at USB2 port 0 \_SB.PCI0.XHCI.RHUB.HS02: USB2 Type-C Port Rear at USB2 port 1 \_SB.PCI0.XHCI.RHUB.HS03: USB2 Type-A Front Right at USB2 port 2 \_SB.PCI0.XHCI.RHUB.HS04: USB2 Type-A Rear Right at USB2 port 3 \_SB.PCI0.XHCI.RHUB.HS06: USB2 Type-A Rear Left at USB2 port 5 \_SB.PCI0.XHCI.RHUB.HS10: Bluetooth at USB2 port 9 \_SB.PCI0.XHCI.RHUB.SS01: USB3 Type-A Front Left at USB3 port 0 \_SB.PCI0.XHCI.RHUB.SS02: USB3 Type-A Front Right at USB3 port 1 \_SB.PCI0.XHCI.RHUB.SS03: USB3 Type-A Rear Right at USB3 port 2 \_SB.PCI0.XHCI.RHUB.SS04: USB3 Type-C Rear at USB3 port 3 \_SB.PCI0.XHCI.RHUB.SS05: USB3 Type-A Rear Left at USB3 port 4 \_SB.PCI0.XHCI.RHUB.HS05: USB2 Type-A Rear Middle at USB2 port 4 \_SB.PCI0.XHCI.RHUB.SS06: USB3 Type-A Rear Middle at USB3 port 5 ACPI: added table 2/32, length now 44 ACPI: * MCFG ACPI: added table 3/32, length now 48 ACPI: * TPM2 TPM2 log created at 0x99a20000 ACPI: added table 4/32, length now 52 ACPI: * MADT SCI is IRQ9 ACPI: added table 5/32, length now 56 current = 99b36070 ACPI: * DMAR ACPI: added table 6/32, length now 60 ACPI: added table 7/32, length now 64 ACPI: * HPET ACPI: added table 8/32, length now 68 ACPI: done. ACPI tables: 20912 bytes. smbios_write_tables: 99a1f000 EC returned error result code 3 Couldn't obtain OEM name from CBI Create SMBIOS type 17 PCI: 00:00.0 (Intel Cannonlake) PCI: 00:14.3 (Intel WiFi) SMBIOS tables: 841 bytes. Writing table forward entry at 0x00000500 Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 1629 Writing coreboot table at 0x99b55000 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000a0000-00000000000fffff: RESERVED 3. 0000000000100000-0000000099a1efff: RAM 4. 0000000099a1f000-0000000099ba4fff: CONFIGURATION TABLES 5. 0000000099ba5000-0000000099c0afff: RAMSTAGE 6. 0000000099c0b000-0000000099ffffff: CONFIGURATION TABLES 7. 000000009a000000-000000009f7fffff: RESERVED 8. 00000000e0000000-00000000efffffff: RESERVED 9. 00000000fc000000-00000000fc000fff: RESERVED 10. 00000000fe000000-00000000fe00ffff: RESERVED 11. 00000000fed10000-00000000fed17fff: RESERVED 12. 00000000fed80000-00000000fed83fff: RESERVED 13. 00000000fed90000-00000000fed91fff: RESERVED 14. 00000000feda0000-00000000feda1fff: RESERVED 15. 0000000100000000-000000015e7fffff: RAM Graphics hand-off block not found FSP did not return a valid framebuffer Passing 4 GPIOs to payload: NAME | PORT | POLARITY | VALUE lid | undefined | high | high power | undefined | high | low oprom | undefined | high | low EC in RW | 0x000000cb | high | low Board ID: 4 FMAP: area COREBOOT found @ c08000 (4161536 bytes) Wrote coreboot table at: 0x99b55000, 0x578 bytes, checksum 4cd4 coreboot table: 1424 bytes. IMD ROOT 0. 0x99fff000 0x00001000 IMD SMALL 1. 0x99ffe000 0x00001000 FSP MEMORY 2. 0x99c4e000 0x003b0000 CONSOLE 3. 0x99c2e000 0x00020000 FMAP 4. 0x99c2d000 0x00000578 TIME STAMP 5. 0x99c2c000 0x00000910 VBOOT WORK 6. 0x99c18000 0x00014000 MRC DATA 7. 0x99c16000 0x00001958 ROMSTG STCK 8. 0x99c15000 0x00001000 AFTER CAR 9. 0x99c0b000 0x0000a000 RAMSTAGE 10. 0x99ba4000 0x00067000 REFCODE 11. 0x99b6f000 0x00035000 SMM BACKUP 12. 0x99b5f000 0x00010000 4f444749 13. 0x99b5d000 0x00002000 COREBOOT 14. 0x99b55000 0x00008000 ACPI 15. 0x99b31000 0x00024000 ACPI GNVS 16. 0x99b30000 0x00001000 RAMOOPS 17. 0x99a30000 0x00100000 TPM2 TCGLOG18. 0x99a20000 0x00010000 SMBIOS 19. 0x99a1f000 0x00000800 IMD small region: IMD ROOT 0. 0x99ffec00 0x00000400 FSP RUNTIME 1. 0x99ffebe0 0x00000004 VPD 2. 0x99ffeb80 0x00000058 POWER STATE 3. 0x99ffeb40 0x00000040 ROMSTAGE 4. 0x99ffeb20 0x00000004 MEM INFO 5. 0x99ffe960 0x000001b9 BS: BS_WRITE_TABLES run times (exec / console): 9 / 504 ms MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x000000009b000000 size 0x9af40000 type 6 0x000000009b000000 - 0x00000000a0000000 size 0x05000000 type 0 0x00000000a0000000 - 0x00000000b0000000 size 0x10000000 type 1 0x00000000b0000000 - 0x0000000100000000 size 0x50000000 type 0 0x0000000100000000 - 0x000000015e800000 size 0x5e800000 type 6 MTRR: Fixed MSR 0x250 0x0606060606060606 MTRR: Fixed MSR 0x258 0x0606060606060606 MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x0606060606060606 MTRR: Fixed MSR 0x269 0x0606060606060606 MTRR: Fixed MSR 0x26a 0x0606060606060606 MTRR: Fixed MSR 0x26b 0x0606060606060606 MTRR: Fixed MSR 0x26c 0x0606060606060606 MTRR: Fixed MSR 0x26d 0x0606060606060606 MTRR: Fixed MSR 0x26e 0x0606060606060606 MTRR: Fixed MSR 0x26f 0x0606060606060606 call enable_fixed_mtrr() CPU physical address size: 39 bits MTRR: default type WB/UC MTRR counts: 5/6. MTRR: WB selected as default type. MTRR: 0 base 0x000000009b000000 mask 0x0000007fff000000 type 0 MTRR: 1 base 0x000000009c000000 mask 0x0000007ffc000000 type 0 MTRR: 2 base 0x00000000a0000000 mask 0x0000007ff0000000 type 1 MTRR: 3 base 0x00000000b0000000 mask 0x0000007ff0000000 type 0 MTRR: 4 base 0x00000000c0000000 mask 0x0000007fc0000000 type 0 MTRR: Fixed MSR 0x250 0x0606060606060606 MTRR: Fixed MSR 0x258 0x0606060606060606 MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x0606060606060606 MTRR: Fixed MSR 0x269 0x0606060606060606 MTRR: Fixed MSR 0x26a 0x0606060606060606 MTRR: Fixed MSR 0x26b 0x0606060606060606 MTRR: Fixed MSR 0x26c 0x0606060606060606 MTRR: Fixed MSR 0x26d 0x0606060606060606 MTRR: Fixed MSR 0x26e 0x0606060606060606 MTRR: Fixed MSR 0x26f 0x0606060606060606 MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled call enable_fixed_mtrr() BS: BS_WRITE_TABLES exit times (exec / console): 46 / 142 ms CPU physical address size: 39 bits Probing TPM: done! Connected to device vid:did:rid of 1ae0:0028:00 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_B:0.5.130/cr50_v2.94_mp.110-683b81dc66 Initialized TPM device CR50 revision 0 Checking cr50 for pending updates Reading cr50 TPM mode BS: BS_PAYLOAD_LOAD entry times (exec / console): 12 / 25 ms FMAP: area COREBOOT found @ c08000 (4161536 bytes) CBFS: Locating 'fallback/payload' CBFS: Found @ offset 3a0c00 size 48db0 Checking segment from ROM address 0xfffa8c38 Checking segment from ROM address 0xfffa8c54 Loading segment from ROM address 0xfffa8c38 code (compression=0) New segment dstaddr 0x30000000 memsize 0x2660100 srcaddr 0xfffa8c70 filesize 0x48d78 Loading Segment: addr: 0x30000000 memsz: 0x0000000002660100 filesz: 0x0000000000048d78 it's not compressed! [ 0x30000000, 30048d78, 0x32660100) <- fffa8c70 Clearing Segment: addr: 0x0000000030048d78 memsz: 0x0000000002617388 Loading segment from ROM address 0xfffa8c54 Entry Point 0x30000000 Loaded segments BS: BS_PAYLOAD_LOAD run times (exec / console): 103 / 67 ms Finalizing chipset. Finalizing SMM. APMC done. BS: BS_PAYLOAD_LOAD exit times (exec / console): 2 / 5 ms mp_park_aps done after 0 msecs. Jumping to boot code at 0x30000000(0x99b55000) CPU0: stack: 0x99bf8000 - 0x99bf9000, lowest used address 0x99bf8a88, stack used: 1400 bytes Starting depthcharge on Kaisa... WARNING: can't convert coreboot GPIOs, 'lid' won't be resampled at runtime! WARNING: can't convert coreboot GPIOs, 'power' won't be resampled at runtime! BIOS MMAP details: IFD Base Offset : 0x300000 IFD End Offset : 0x1000000 MMAP Size : 0xd00000 MMAP Start : 0xff300000 Looking for NVMe Controller 0x3105c848 @ 00:1d:00 Wipe memory regions: [0x00000000001000, 0x000000000a0000) [0x00000000100000, 0x00000030000000) [0x00000032660100, 0x00000099a1f000) [0x00000100000000, 0x0000015e800000) R8152: Initializing Version 9 (ocp_data = 6010) R8152: Done initializing Adding net device [firmware-puff-13324.B-collabora] Feb 14 2023 12:06:39 puff: tftpboot 192.168.201.1 13627357/tftp-deploy-47tuaejj/kernel/bzImage 13627357/tftp-deploy-47tuaejj/kernel/cmdline 13627357/tftp-deploy-47tuaejj/ramdisk/ramdisk.cpio.gz tftpboot 192.168.201.1 13627357/tftp-deploy-47tuaejj/kernel/bzImage 13627357/tftp-deploy-47tuaejj/kernel/cmdline 13627357/tftp-deploy-47tuaejj/ramdisk/ramdisk.cpio.gz Waiting for link done. MAC: 00:e0:4c:68:00:ff Sending DHCP discover... done. Waiting for reply... done. Sending DHCP request... done. Waiting for reply... done. My ip is 192.168.201.13 The DHCP server ip is 192.168.201.1 TFTP server IP predefined by user: 192.168.201.1 Bootfile predefined by user: 13627357/tftp-deploy-47tuaejj/kernel/bzImage Sending tftp read request... done. Waiting for the transfer... 00000000 ################################################################ 00080000 ################################################################ 00100000 ################################################################ 00180000 ################################################################ 00200000 ################################################################ 00280000 ################################################################ 00300000 ################################################################ 00380000 ################################################################ 00400000 ################################################################ 00480000 ################################################################ 00500000 ################################################################ 00580000 ################################################################ 00600000 ################################################################ 00680000 ################################################################ 00700000 ################################################################ 00780000 ################################################################ 00800000 ################################################################ 00880000 ################################################################ 00900000 ################################################################ 00980000 ################################################################ 00a00000 ################################################################ 00a80000 ################################################################ 00b00000 ################################################################ 00b80000 ################################################################ 00c00000 ################################################################ 00c80000 ################################################################ 00d00000 ######################################################## done. The bootfile was 14090128 bytes long. Sending tftp read request... done. Waiting for the transfer... 00000000 ################################################################ 00080000 ################################################################ 00100000 ################################################################ 00180000 ################################################################ 00200000 ################################################################ 00280000 ################################################################ 00300000 ################################################################ 00380000 ################################################################ 00400000 ################################################################ 00480000 ################################################################ 00500000 ################################################################ 00580000 ################################################################ 00600000 ########################################################### done. Sending tftp read request... done. Waiting for the transfer... 00000000 # done. Command line loaded dynamically from TFTP file: 13627357/tftp-deploy-47tuaejj/kernel/cmdline The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/13627357/extract-nfsrootfs-686x2i8u,tcp,hard ip=dhcp tftpserverip=192.168.201.1 ec_init: CrosEC protocol v3 supported (256, 256) Shutting down all USB controllers. Removing current net device Finalizing coreboot Exiting depthcharge with code 4 at timestamp: 20684262 Starting kernel ...