Boot log: asus-cx9400-volteer
- Kernel Warnings: 0
- Warnings: 0
- Boot result: FAIL
- Kernel Errors: 0
- Errors: 2
1 13:48:34.058727 lava-dispatcher, installed at version: 2023.06
2 13:48:34.058954 start: 0 validate
3 13:48:34.059095 Start time: 2023-08-16 13:48:34.059087+00:00 (UTC)
4 13:48:34.059228 Using caching service: 'http://localhost/cache/?uri=%s'
5 13:48:34.059386 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230623.0%2Fx86%2Frootfs.cpio.gz exists
6 13:48:34.318996 Using caching service: 'http://localhost/cache/?uri=%s'
7 13:48:34.319286 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-4.4.y-st-rt%2Fv4.4-st20-2312-g74888f4b13f0%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fkernel%2FbzImage exists
8 13:48:34.570152 Using caching service: 'http://localhost/cache/?uri=%s'
9 13:48:34.570330 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-4.4.y-st-rt%2Fv4.4-st20-2312-g74888f4b13f0%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
10 13:48:34.820965 validate duration: 0.76
12 13:48:34.821245 start: 1 tftp-deploy (timeout 00:10:00) [common]
13 13:48:34.821342 start: 1.1 download-retry (timeout 00:10:00) [common]
14 13:48:34.821426 start: 1.1.1 http-download (timeout 00:10:00) [common]
15 13:48:34.821549 Not decompressing ramdisk as can be used compressed.
16 13:48:34.821639 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230623.0/x86/rootfs.cpio.gz
17 13:48:34.821708 saving as /var/lib/lava/dispatcher/tmp/11299541/tftp-deploy-iowl9d7g/ramdisk/rootfs.cpio.gz
18 13:48:34.821771 total size: 8418130 (8 MB)
19 13:48:34.822912 progress 0 % (0 MB)
20 13:48:34.825212 progress 5 % (0 MB)
21 13:48:34.827574 progress 10 % (0 MB)
22 13:48:34.829874 progress 15 % (1 MB)
23 13:48:34.832300 progress 20 % (1 MB)
24 13:48:34.834681 progress 25 % (2 MB)
25 13:48:34.836963 progress 30 % (2 MB)
26 13:48:34.839183 progress 35 % (2 MB)
27 13:48:34.841694 progress 40 % (3 MB)
28 13:48:34.844271 progress 45 % (3 MB)
29 13:48:34.847097 progress 50 % (4 MB)
30 13:48:34.849451 progress 55 % (4 MB)
31 13:48:34.851785 progress 60 % (4 MB)
32 13:48:34.853840 progress 65 % (5 MB)
33 13:48:34.856079 progress 70 % (5 MB)
34 13:48:34.858253 progress 75 % (6 MB)
35 13:48:34.860476 progress 80 % (6 MB)
36 13:48:34.862696 progress 85 % (6 MB)
37 13:48:34.864868 progress 90 % (7 MB)
38 13:48:34.867080 progress 95 % (7 MB)
39 13:48:34.869149 progress 100 % (8 MB)
40 13:48:34.869377 8 MB downloaded in 0.05 s (168.64 MB/s)
41 13:48:34.869538 end: 1.1.1 http-download (duration 00:00:00) [common]
43 13:48:34.869776 end: 1.1 download-retry (duration 00:00:00) [common]
44 13:48:34.869863 start: 1.2 download-retry (timeout 00:10:00) [common]
45 13:48:34.869945 start: 1.2.1 http-download (timeout 00:10:00) [common]
46 13:48:34.870068 downloading http://storage.kernelci.org/cip/linux-4.4.y-st-rt/v4.4-st20-2312-g74888f4b13f0/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/kernel/bzImage
47 13:48:34.870145 saving as /var/lib/lava/dispatcher/tmp/11299541/tftp-deploy-iowl9d7g/kernel/bzImage
48 13:48:34.870204 total size: 8499088 (8 MB)
49 13:48:34.870263 No compression specified
50 13:48:34.871474 progress 0 % (0 MB)
51 13:48:34.873595 progress 5 % (0 MB)
52 13:48:34.875971 progress 10 % (0 MB)
53 13:48:34.878185 progress 15 % (1 MB)
54 13:48:34.880631 progress 20 % (1 MB)
55 13:48:34.882896 progress 25 % (2 MB)
56 13:48:34.885113 progress 30 % (2 MB)
57 13:48:34.887464 progress 35 % (2 MB)
58 13:48:34.889718 progress 40 % (3 MB)
59 13:48:34.891978 progress 45 % (3 MB)
60 13:48:34.894211 progress 50 % (4 MB)
61 13:48:34.896562 progress 55 % (4 MB)
62 13:48:34.898903 progress 60 % (4 MB)
63 13:48:34.901174 progress 65 % (5 MB)
64 13:48:34.903412 progress 70 % (5 MB)
65 13:48:34.905587 progress 75 % (6 MB)
66 13:48:34.907759 progress 80 % (6 MB)
67 13:48:34.909924 progress 85 % (6 MB)
68 13:48:34.912142 progress 90 % (7 MB)
69 13:48:34.914305 progress 95 % (7 MB)
70 13:48:34.916519 progress 100 % (8 MB)
71 13:48:34.916669 8 MB downloaded in 0.05 s (174.46 MB/s)
72 13:48:34.916813 end: 1.2.1 http-download (duration 00:00:00) [common]
74 13:48:34.917036 end: 1.2 download-retry (duration 00:00:00) [common]
75 13:48:34.917119 start: 1.3 download-retry (timeout 00:10:00) [common]
76 13:48:34.917201 start: 1.3.1 http-download (timeout 00:10:00) [common]
77 13:48:34.917323 downloading http://storage.kernelci.org/cip/linux-4.4.y-st-rt/v4.4-st20-2312-g74888f4b13f0/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/modules.tar.xz
78 13:48:34.917393 saving as /var/lib/lava/dispatcher/tmp/11299541/tftp-deploy-iowl9d7g/modules/modules.tar
79 13:48:34.917452 total size: 253616 (0 MB)
80 13:48:34.917512 Using unxz to decompress xz
81 13:48:34.921784 progress 12 % (0 MB)
82 13:48:34.922177 progress 25 % (0 MB)
83 13:48:34.922453 progress 38 % (0 MB)
84 13:48:34.924057 progress 51 % (0 MB)
85 13:48:34.925954 progress 64 % (0 MB)
86 13:48:34.927802 progress 77 % (0 MB)
87 13:48:34.929642 progress 90 % (0 MB)
88 13:48:34.931421 progress 100 % (0 MB)
89 13:48:34.937230 0 MB downloaded in 0.02 s (12.23 MB/s)
90 13:48:34.937481 end: 1.3.1 http-download (duration 00:00:00) [common]
92 13:48:34.937740 end: 1.3 download-retry (duration 00:00:00) [common]
93 13:48:34.937832 start: 1.4 prepare-tftp-overlay (timeout 00:10:00) [common]
94 13:48:34.937924 start: 1.4.1 extract-nfsrootfs (timeout 00:10:00) [common]
95 13:48:34.938004 end: 1.4.1 extract-nfsrootfs (duration 00:00:00) [common]
96 13:48:34.938084 start: 1.4.2 lava-overlay (timeout 00:10:00) [common]
97 13:48:34.938290 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11299541/lava-overlay-ap2_y7d4
98 13:48:34.938452 makedir: /var/lib/lava/dispatcher/tmp/11299541/lava-overlay-ap2_y7d4/lava-11299541/bin
99 13:48:34.938562 makedir: /var/lib/lava/dispatcher/tmp/11299541/lava-overlay-ap2_y7d4/lava-11299541/tests
100 13:48:34.938707 makedir: /var/lib/lava/dispatcher/tmp/11299541/lava-overlay-ap2_y7d4/lava-11299541/results
101 13:48:34.938825 Creating /var/lib/lava/dispatcher/tmp/11299541/lava-overlay-ap2_y7d4/lava-11299541/bin/lava-add-keys
102 13:48:34.938968 Creating /var/lib/lava/dispatcher/tmp/11299541/lava-overlay-ap2_y7d4/lava-11299541/bin/lava-add-sources
103 13:48:34.939096 Creating /var/lib/lava/dispatcher/tmp/11299541/lava-overlay-ap2_y7d4/lava-11299541/bin/lava-background-process-start
104 13:48:34.939225 Creating /var/lib/lava/dispatcher/tmp/11299541/lava-overlay-ap2_y7d4/lava-11299541/bin/lava-background-process-stop
105 13:48:34.939351 Creating /var/lib/lava/dispatcher/tmp/11299541/lava-overlay-ap2_y7d4/lava-11299541/bin/lava-common-functions
106 13:48:34.939473 Creating /var/lib/lava/dispatcher/tmp/11299541/lava-overlay-ap2_y7d4/lava-11299541/bin/lava-echo-ipv4
107 13:48:34.939597 Creating /var/lib/lava/dispatcher/tmp/11299541/lava-overlay-ap2_y7d4/lava-11299541/bin/lava-install-packages
108 13:48:34.939719 Creating /var/lib/lava/dispatcher/tmp/11299541/lava-overlay-ap2_y7d4/lava-11299541/bin/lava-installed-packages
109 13:48:34.939841 Creating /var/lib/lava/dispatcher/tmp/11299541/lava-overlay-ap2_y7d4/lava-11299541/bin/lava-os-build
110 13:48:34.939964 Creating /var/lib/lava/dispatcher/tmp/11299541/lava-overlay-ap2_y7d4/lava-11299541/bin/lava-probe-channel
111 13:48:34.940086 Creating /var/lib/lava/dispatcher/tmp/11299541/lava-overlay-ap2_y7d4/lava-11299541/bin/lava-probe-ip
112 13:48:34.940208 Creating /var/lib/lava/dispatcher/tmp/11299541/lava-overlay-ap2_y7d4/lava-11299541/bin/lava-target-ip
113 13:48:34.940354 Creating /var/lib/lava/dispatcher/tmp/11299541/lava-overlay-ap2_y7d4/lava-11299541/bin/lava-target-mac
114 13:48:34.940489 Creating /var/lib/lava/dispatcher/tmp/11299541/lava-overlay-ap2_y7d4/lava-11299541/bin/lava-target-storage
115 13:48:34.940619 Creating /var/lib/lava/dispatcher/tmp/11299541/lava-overlay-ap2_y7d4/lava-11299541/bin/lava-test-case
116 13:48:34.940744 Creating /var/lib/lava/dispatcher/tmp/11299541/lava-overlay-ap2_y7d4/lava-11299541/bin/lava-test-event
117 13:48:34.940868 Creating /var/lib/lava/dispatcher/tmp/11299541/lava-overlay-ap2_y7d4/lava-11299541/bin/lava-test-feedback
118 13:48:34.940992 Creating /var/lib/lava/dispatcher/tmp/11299541/lava-overlay-ap2_y7d4/lava-11299541/bin/lava-test-raise
119 13:48:34.941119 Creating /var/lib/lava/dispatcher/tmp/11299541/lava-overlay-ap2_y7d4/lava-11299541/bin/lava-test-reference
120 13:48:34.941248 Creating /var/lib/lava/dispatcher/tmp/11299541/lava-overlay-ap2_y7d4/lava-11299541/bin/lava-test-runner
121 13:48:34.941372 Creating /var/lib/lava/dispatcher/tmp/11299541/lava-overlay-ap2_y7d4/lava-11299541/bin/lava-test-set
122 13:48:34.941501 Creating /var/lib/lava/dispatcher/tmp/11299541/lava-overlay-ap2_y7d4/lava-11299541/bin/lava-test-shell
123 13:48:34.941704 Updating /var/lib/lava/dispatcher/tmp/11299541/lava-overlay-ap2_y7d4/lava-11299541/bin/lava-install-packages (oe)
124 13:48:34.941862 Updating /var/lib/lava/dispatcher/tmp/11299541/lava-overlay-ap2_y7d4/lava-11299541/bin/lava-installed-packages (oe)
125 13:48:34.941990 Creating /var/lib/lava/dispatcher/tmp/11299541/lava-overlay-ap2_y7d4/lava-11299541/environment
126 13:48:34.942090 LAVA metadata
127 13:48:34.942165 - LAVA_JOB_ID=11299541
128 13:48:34.942228 - LAVA_DISPATCHER_IP=192.168.201.1
129 13:48:34.942334 start: 1.4.2.1 lava-vland-overlay (timeout 00:10:00) [common]
130 13:48:34.942400 skipped lava-vland-overlay
131 13:48:34.942475 end: 1.4.2.1 lava-vland-overlay (duration 00:00:00) [common]
132 13:48:34.942554 start: 1.4.2.2 lava-multinode-overlay (timeout 00:10:00) [common]
133 13:48:34.942644 skipped lava-multinode-overlay
134 13:48:34.942733 end: 1.4.2.2 lava-multinode-overlay (duration 00:00:00) [common]
135 13:48:34.942812 start: 1.4.2.3 test-definition (timeout 00:10:00) [common]
136 13:48:34.942884 Loading test definitions
137 13:48:34.942975 start: 1.4.2.3.1 inline-repo-action (timeout 00:10:00) [common]
138 13:48:34.943060 Using /lava-11299541 at stage 0
139 13:48:34.943377 uuid=11299541_1.4.2.3.1 testdef=None
140 13:48:34.943464 end: 1.4.2.3.1 inline-repo-action (duration 00:00:00) [common]
141 13:48:34.943551 start: 1.4.2.3.2 test-overlay (timeout 00:10:00) [common]
142 13:48:34.944089 end: 1.4.2.3.2 test-overlay (duration 00:00:00) [common]
144 13:48:34.944435 start: 1.4.2.3.3 test-install-overlay (timeout 00:10:00) [common]
145 13:48:34.945134 end: 1.4.2.3.3 test-install-overlay (duration 00:00:00) [common]
147 13:48:34.945364 start: 1.4.2.3.4 test-runscript-overlay (timeout 00:10:00) [common]
148 13:48:34.945985 runner path: /var/lib/lava/dispatcher/tmp/11299541/lava-overlay-ap2_y7d4/lava-11299541/0/tests/0_dmesg test_uuid 11299541_1.4.2.3.1
149 13:48:34.946140 end: 1.4.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
151 13:48:34.946364 start: 1.4.2.3.5 inline-repo-action (timeout 00:10:00) [common]
152 13:48:34.946434 Using /lava-11299541 at stage 1
153 13:48:34.946777 uuid=11299541_1.4.2.3.5 testdef=None
154 13:48:34.946864 end: 1.4.2.3.5 inline-repo-action (duration 00:00:00) [common]
155 13:48:34.946946 start: 1.4.2.3.6 test-overlay (timeout 00:10:00) [common]
156 13:48:34.947417 end: 1.4.2.3.6 test-overlay (duration 00:00:00) [common]
158 13:48:34.947633 start: 1.4.2.3.7 test-install-overlay (timeout 00:10:00) [common]
159 13:48:34.948276 end: 1.4.2.3.7 test-install-overlay (duration 00:00:00) [common]
161 13:48:34.948499 start: 1.4.2.3.8 test-runscript-overlay (timeout 00:10:00) [common]
162 13:48:34.949128 runner path: /var/lib/lava/dispatcher/tmp/11299541/lava-overlay-ap2_y7d4/lava-11299541/1/tests/1_bootrr test_uuid 11299541_1.4.2.3.5
163 13:48:34.949280 end: 1.4.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
165 13:48:34.949485 Creating lava-test-runner.conf files
166 13:48:34.949548 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11299541/lava-overlay-ap2_y7d4/lava-11299541/0 for stage 0
167 13:48:34.949638 - 0_dmesg
168 13:48:34.949716 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11299541/lava-overlay-ap2_y7d4/lava-11299541/1 for stage 1
169 13:48:34.949807 - 1_bootrr
170 13:48:34.949900 end: 1.4.2.3 test-definition (duration 00:00:00) [common]
171 13:48:34.949982 start: 1.4.2.4 compress-overlay (timeout 00:10:00) [common]
172 13:48:34.958407 end: 1.4.2.4 compress-overlay (duration 00:00:00) [common]
173 13:48:34.958536 start: 1.4.2.5 persistent-nfs-overlay (timeout 00:10:00) [common]
174 13:48:34.958668 end: 1.4.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
175 13:48:34.958760 end: 1.4.2 lava-overlay (duration 00:00:00) [common]
176 13:48:34.958847 start: 1.4.3 extract-overlay-ramdisk (timeout 00:10:00) [common]
177 13:48:35.214915 end: 1.4.3 extract-overlay-ramdisk (duration 00:00:00) [common]
178 13:48:35.215318 start: 1.4.4 extract-modules (timeout 00:10:00) [common]
179 13:48:35.215434 extracting modules file /var/lib/lava/dispatcher/tmp/11299541/tftp-deploy-iowl9d7g/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11299541/extract-overlay-ramdisk-tmn0v9r7/ramdisk
180 13:48:35.229323 end: 1.4.4 extract-modules (duration 00:00:00) [common]
181 13:48:35.229495 start: 1.4.5 apply-overlay-tftp (timeout 00:10:00) [common]
182 13:48:35.229594 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11299541/compress-overlay-4i3kt7_n/overlay-1.4.2.4.tar.gz to ramdisk
183 13:48:35.229668 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11299541/compress-overlay-4i3kt7_n/overlay-1.4.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11299541/extract-overlay-ramdisk-tmn0v9r7/ramdisk
184 13:48:35.239071 end: 1.4.5 apply-overlay-tftp (duration 00:00:00) [common]
185 13:48:35.239226 start: 1.4.6 configure-preseed-file (timeout 00:10:00) [common]
186 13:48:35.239322 end: 1.4.6 configure-preseed-file (duration 00:00:00) [common]
187 13:48:35.239413 start: 1.4.7 compress-ramdisk (timeout 00:10:00) [common]
188 13:48:35.239492 Building ramdisk /var/lib/lava/dispatcher/tmp/11299541/extract-overlay-ramdisk-tmn0v9r7/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11299541/extract-overlay-ramdisk-tmn0v9r7/ramdisk
189 13:48:35.372735 >> 49825 blocks
190 13:48:36.204108 rename /var/lib/lava/dispatcher/tmp/11299541/extract-overlay-ramdisk-tmn0v9r7/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11299541/tftp-deploy-iowl9d7g/ramdisk/ramdisk.cpio.gz
191 13:48:36.204705 end: 1.4.7 compress-ramdisk (duration 00:00:01) [common]
192 13:48:36.204840 start: 1.4.8 prepare-kernel (timeout 00:09:59) [common]
193 13:48:36.204982 start: 1.4.8.1 prepare-fit (timeout 00:09:59) [common]
194 13:48:36.205100 No mkimage arch provided, not using FIT.
195 13:48:36.205219 end: 1.4.8.1 prepare-fit (duration 00:00:00) [common]
196 13:48:36.205336 end: 1.4.8 prepare-kernel (duration 00:00:00) [common]
197 13:48:36.205472 end: 1.4 prepare-tftp-overlay (duration 00:00:01) [common]
198 13:48:36.205575 start: 1.5 lxc-create-udev-rule-action (timeout 00:09:59) [common]
199 13:48:36.205659 No LXC device requested
200 13:48:36.205737 end: 1.5 lxc-create-udev-rule-action (duration 00:00:00) [common]
201 13:48:36.205823 start: 1.6 deploy-device-env (timeout 00:09:59) [common]
202 13:48:36.205901 end: 1.6 deploy-device-env (duration 00:00:00) [common]
203 13:48:36.205970 Checking files for TFTP limit of 4294967296 bytes.
204 13:48:36.206372 end: 1 tftp-deploy (duration 00:00:01) [common]
205 13:48:36.206475 start: 2 depthcharge-action (timeout 00:05:00) [common]
206 13:48:36.206566 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
207 13:48:36.206729 substitutions:
208 13:48:36.206798 - {DTB}: None
209 13:48:36.206860 - {INITRD}: 11299541/tftp-deploy-iowl9d7g/ramdisk/ramdisk.cpio.gz
210 13:48:36.206920 - {KERNEL}: 11299541/tftp-deploy-iowl9d7g/kernel/bzImage
211 13:48:36.206977 - {LAVA_MAC}: None
212 13:48:36.207032 - {PRESEED_CONFIG}: None
213 13:48:36.207085 - {PRESEED_LOCAL}: None
214 13:48:36.207139 - {RAMDISK}: 11299541/tftp-deploy-iowl9d7g/ramdisk/ramdisk.cpio.gz
215 13:48:36.207193 - {ROOT_PART}: None
216 13:48:36.207245 - {ROOT}: None
217 13:48:36.207298 - {SERVER_IP}: 192.168.201.1
218 13:48:36.207350 - {TEE}: None
219 13:48:36.207402 Parsed boot commands:
220 13:48:36.207455 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
221 13:48:36.207631 Parsed boot commands: tftpboot 192.168.201.1 11299541/tftp-deploy-iowl9d7g/kernel/bzImage 11299541/tftp-deploy-iowl9d7g/kernel/cmdline 11299541/tftp-deploy-iowl9d7g/ramdisk/ramdisk.cpio.gz
222 13:48:36.207719 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
223 13:48:36.207800 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
224 13:48:36.207888 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
225 13:48:36.207975 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
226 13:48:36.208044 Not connected, no need to disconnect.
227 13:48:36.208115 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
228 13:48:36.208309 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
229 13:48:36.208418 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh asus-cx9400-volteer-cbg-8'
230 13:48:36.212483 Setting prompt string to ['lava-test: # ']
231 13:48:36.212852 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
232 13:48:36.212964 end: 2.2.1 reset-connection (duration 00:00:00) [common]
233 13:48:36.213085 start: 2.2.2 reset-device (timeout 00:05:00) [common]
234 13:48:36.213213 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
235 13:48:36.213469 Calling: 'pduclient' '--daemon=localhost' '--hostname=asus-cx9400-volteer-cbg-8' '--port=1' '--command=reboot'
236 13:48:41.366073 >> Command sent successfully.
237 13:48:41.377836 Returned 0 in 5 seconds
238 13:48:41.479150 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
240 13:48:41.480548 end: 2.2.2 reset-device (duration 00:00:05) [common]
241 13:48:41.481151 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
242 13:48:41.481691 Setting prompt string to 'Starting depthcharge on Voema...'
243 13:48:41.482081 Changing prompt to 'Starting depthcharge on Voema...'
244 13:48:41.482473 depthcharge-start: Wait for prompt Starting depthcharge on Voema... (timeout 00:05:00)
245 13:48:41.483831 [Enter `^Ec?' for help]
246 13:48:43.071912
247 13:48:43.072833
248 13:48:43.080223 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 bootblock starting (log level: 8)...
249 13:48:43.083412 CPU: 11th Gen Intel(R) Core(TM) i5-1130G7 @ 1.10GHz
250 13:48:43.090360 CPU: ID 806c1, Tigerlake B0, ucode: 00000086
251 13:48:43.093643 CPU: AES supported, TXT NOT supported, VT supported
252 13:48:43.101270 MCH: device id 9a12 (rev 01) is Tigerlake-Y-4-2
253 13:48:43.106946 PCH: device id a087 (rev 20) is Tigerlake-Y Premium SKU
254 13:48:43.110817 IGD: device id 9a40 (rev 01) is Tigerlake Y GT2
255 13:48:43.113915 VBOOT: Loading verstage.
256 13:48:43.117047 FMAP: Found "FLASH" version 1.1 at 0x1804000.
257 13:48:43.123566 FMAP: base = 0x0 size = 0x2000000 #areas = 32
258 13:48:43.127090 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
259 13:48:43.137240 CBFS: mcache @0xfef45600 built for 70 files, used 0xfdc of 0x1800 bytes
260 13:48:43.144410 CBFS: Found 'fallback/verstage' @0x165e40 size 0x147ec in mcache @0xfef45984
261 13:48:43.145012
262 13:48:43.145350
263 13:48:43.157298 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 verstage starting (log level: 8)...
264 13:48:43.170665 Probing TPM: . done!
265 13:48:43.174497 TPM ready after 0 ms
266 13:48:43.177550 Connected to device vid:did:rid of 1ae0:0028:00
267 13:48:43.188947 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.6.20/cr50_v1.9308_B.947-551594aae6
268 13:48:43.195344 Current CR50_BOARD_CFG = 0x80000001, matches desired = 0x00000001
269 13:48:43.198667 Initialized TPM device CR50 revision 0
270 13:48:43.251733 tlcl_send_startup: Startup return code is 0
271 13:48:43.252323 TPM: setup succeeded
272 13:48:43.265990 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
273 13:48:43.280331 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
274 13:48:43.292749 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
275 13:48:43.302621 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
276 13:48:43.306672 Chrome EC: UHEPI supported
277 13:48:43.309979 Phase 1
278 13:48:43.312897 FMAP: area GBB found @ 1805000 (458752 bytes)
279 13:48:43.323015 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
280 13:48:43.329244 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
281 13:48:43.336356 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
282 13:48:43.342915 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
283 13:48:43.345860 Recovery requested (1009000e)
284 13:48:43.349453 TPM: Extending digest for VBOOT: boot mode into PCR 0
285 13:48:43.360942 tlcl_extend: response is 0
286 13:48:43.367978 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
287 13:48:43.378015 tlcl_extend: response is 0
288 13:48:43.384526 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
289 13:48:43.390892 CBFS: Found 'fallback/romstage' @0x80 size 0x1bf24 in mcache @0xfef45638
290 13:48:43.397861 BS: verstage times (exec / console): total (unknown) / 142 ms
291 13:48:43.398292
292 13:48:43.398658
293 13:48:43.410581 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 romstage starting (log level: 8)...
294 13:48:43.417277 VB2:vb2api_ec_sync() In recovery mode, skipping EC sync
295 13:48:43.420675 pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00
296 13:48:43.427192 gpe0_sts[0]: 00200000 gpe0_en[0]: 00000000
297 13:48:43.430153 gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000
298 13:48:43.433417 gpe0_sts[2]: 00001000 gpe0_en[2]: 00000000
299 13:48:43.437408 gpe0_sts[3]: 00000000 gpe0_en[3]: 00092000
300 13:48:43.440551 TCO_STS: 0000 0000
301 13:48:43.443548 GEN_PMCON: d0015038 00002200
302 13:48:43.446662 GBLRST_CAUSE: 00000000 00000000
303 13:48:43.450051 HPR_CAUSE0: 00000000
304 13:48:43.450472 prev_sleep_state 5
305 13:48:43.453573 Boot Count incremented to 21911
306 13:48:43.460126 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
307 13:48:43.466907 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
308 13:48:43.477031 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
309 13:48:43.483326 CBFS: Found 'fspm.bin' @0x78fc0 size 0xa5000 in mcache @0xfef4585c
310 13:48:43.486823 Chrome EC: UHEPI supported
311 13:48:43.493133 FMAP: area RECOVERY_MRC_CACHE found @ f00000 (65536 bytes)
312 13:48:43.505066 Probing TPM: done!
313 13:48:43.512360 Connected to device vid:did:rid of 1ae0:0028:00
314 13:48:43.523064 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.6.20/cr50_v1.9308_B.947-551594aae6
315 13:48:43.529863 Initialized TPM device CR50 revision 0
316 13:48:43.539843 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x100b return code 0
317 13:48:43.546399 MRC: Hash idx 0x100b comparison successful.
318 13:48:43.549522 MRC cache found, size faa8
319 13:48:43.550084 bootmode is set to: 2
320 13:48:43.552698 SPD index = 0
321 13:48:43.559761 CBFS: Found 'spd.bin' @0x72940 size 0x600 in mcache @0xfef4579c
322 13:48:43.562763 SPD: module type is LPDDR4X
323 13:48:43.566419 SPD: module part number is MT53E512M64D4NW-046
324 13:48:43.572609 SPD: banks 8, ranks 1, rows 16, columns 10, density 8192 Mb
325 13:48:43.579258 SPD: device width 16 bits, bus width 16 bits
326 13:48:43.582448 SPD: module size is 1024 MB (per channel)
327 13:48:44.013213 CBMEM:
328 13:48:44.016920 IMD: root @ 0x76fff000 254 entries.
329 13:48:44.020103 IMD: root @ 0x76ffec00 62 entries.
330 13:48:44.023119 FMAP: area RO_VPD found @ 1800000 (16384 bytes)
331 13:48:44.029671 FMAP: area RW_VPD found @ f35000 (8192 bytes)
332 13:48:44.033058 External stage cache:
333 13:48:44.036827 IMD: root @ 0x7b3ff000 254 entries.
334 13:48:44.039794 IMD: root @ 0x7b3fec00 62 entries.
335 13:48:44.055780 FMAP: area RECOVERY_MRC_CACHE found @ f00000 (65536 bytes)
336 13:48:44.061686 MRC: Checking cached data update for 'RECOVERY_MRC_CACHE'.
337 13:48:44.068545 SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
338 13:48:44.082479 MRC: 'RECOVERY_MRC_CACHE' does not need update.
339 13:48:44.088855 cse_lite: Skip switching to RW in the recovery path
340 13:48:44.089286 8 DIMMs found
341 13:48:44.089670 SMM Memory Map
342 13:48:44.093367 SMRAM : 0x7b000000 0x800000
343 13:48:44.096467 Subregion 0: 0x7b000000 0x200000
344 13:48:44.099862 Subregion 1: 0x7b200000 0x200000
345 13:48:44.103256 Subregion 2: 0x7b400000 0x400000
346 13:48:44.106631 top_of_ram = 0x77000000
347 13:48:44.112742 MTRR Range: Start=76000000 End=77000000 (Size 1000000)
348 13:48:44.116350 MTRR Range: Start=7b000000 End=7b800000 (Size 800000)
349 13:48:44.122962 MTRR Range: Start=f9000000 End=fa000000 (Size 1000000)
350 13:48:44.126221 MTRR Range: Start=ff000000 End=0 (Size 1000000)
351 13:48:44.136079 CBFS: Found 'fallback/postcar' @0x160900 size 0x54f8 in mcache @0xfef4594c
352 13:48:44.142681 Decompressing stage fallback/postcar @ 0x76c0afc0 (38208 bytes)
353 13:48:44.152721 Loading module at 0x76c0b000 with entry 0x76c0b000. filesize: 0x5150 memsize: 0x9500
354 13:48:44.156020 Processing 211 relocs. Offset value of 0x74c0b000
355 13:48:44.165168 BS: romstage times (exec / console): total (unknown) / 277 ms
356 13:48:44.171796
357 13:48:44.172640
358 13:48:44.180989 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 postcar starting (log level: 8)...
359 13:48:44.184008 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
360 13:48:44.194056 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
361 13:48:44.200969 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
362 13:48:44.207343 CBFS: Found 'fallback/ramstage' @0x524c0 size 0x1fbe3 in mcache @0x76c4c0ec
363 13:48:44.214050 Decompressing stage fallback/ramstage @ 0x76b97fc0 (463536 bytes)
364 13:48:44.261261 Loading module at 0x76b98000 with entry 0x76b98000. filesize: 0x4d5d8 memsize: 0x71270
365 13:48:44.267632 Processing 5008 relocs. Offset value of 0x75d98000
366 13:48:44.270993 BS: postcar times (exec / console): total (unknown) / 59 ms
367 13:48:44.274808
368 13:48:44.275324
369 13:48:44.284486 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 ramstage starting (log level: 8)...
370 13:48:44.284928 Normal boot
371 13:48:44.287946 FW_CONFIG value is 0x804c02
372 13:48:44.291369 PCI: 00:07.0 disabled by fw_config
373 13:48:44.294175 PCI: 00:07.1 disabled by fw_config
374 13:48:44.297578 PCI: 00:0d.2 disabled by fw_config
375 13:48:44.304775 PCI: 00:1c.7 disabled by fw_config
376 13:48:44.307670 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
377 13:48:44.314487 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
378 13:48:44.317738 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
379 13:48:44.324163 GENERIC: 0.0 disabled by fw_config
380 13:48:44.327197 GENERIC: 1.0 disabled by fw_config
381 13:48:44.330530 fw_config match found: DB_USB=USB3_ACTIVE
382 13:48:44.333840 fw_config match found: DB_USB=USB3_ACTIVE
383 13:48:44.337669 fw_config match found: DB_USB=USB3_ACTIVE
384 13:48:44.343697 fw_config match found: DB_USB=USB3_ACTIVE
385 13:48:44.347236 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
386 13:48:44.357312 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
387 13:48:44.363449 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
388 13:48:44.370101 CBFS: Found 'cpu_microcode_blob.bin' @0x1c040 size 0x36400 in mcache @0x76c4c09c
389 13:48:44.376949 microcode: sig=0x806c1 pf=0x80 revision=0x86
390 13:48:44.380398 microcode: Update skipped, already up-to-date
391 13:48:44.386581 CBFS: Found 'fsps.bin' @0x11efc0 size 0x418f9 in mcache @0x76c4c30c
392 13:48:44.414455 Detected 4 core, 8 thread CPU.
393 13:48:44.417599 Setting up SMI for CPU
394 13:48:44.421037 IED base = 0x7b400000
395 13:48:44.424376 IED size = 0x00400000
396 13:48:44.424516 Will perform SMM setup.
397 13:48:44.430908 CPU: 11th Gen Intel(R) Core(TM) i5-1130G7 @ 1.10GHz.
398 13:48:44.437484 Loading module at 0x00030000 with entry 0x00030000. filesize: 0x170 memsize: 0x170
399 13:48:44.443951 Processing 16 relocs. Offset value of 0x00030000
400 13:48:44.447552 Attempting to start 7 APs
401 13:48:44.450634 Waiting for 10ms after sending INIT.
402 13:48:44.466466 Waiting for 1st SIPI to complete...AP: slot 1 apic_id 1.
403 13:48:44.469776 AP: slot 3 apic_id 2.
404 13:48:44.473003 AP: slot 6 apic_id 3.
405 13:48:44.473088 AP: slot 5 apic_id 6.
406 13:48:44.476287 AP: slot 2 apic_id 7.
407 13:48:44.476373 done.
408 13:48:44.479815 AP: slot 7 apic_id 5.
409 13:48:44.479901 AP: slot 4 apic_id 4.
410 13:48:44.486412 Waiting for 2nd SIPI to complete...done.
411 13:48:44.493005 Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1b8 memsize: 0x1b8
412 13:48:44.499995 Processing 13 relocs. Offset value of 0x00038000
413 13:48:44.500331 Unable to locate Global NVS
414 13:48:44.509851 SMM Module: stub loaded at 0x00038000. Will call 0x76bb6318(0x00000000)
415 13:48:44.513043 Installing permanent SMM handler to 0x7b000000
416 13:48:44.522844 Loading module at 0x7b010000 with entry 0x7b010c16. filesize: 0xa7c8 memsize: 0xf908
417 13:48:44.526211 Processing 794 relocs. Offset value of 0x7b010000
418 13:48:44.536518 Loading module at 0x7b008000 with entry 0x7b008000. filesize: 0x1b8 memsize: 0x1b8
419 13:48:44.539899 Processing 13 relocs. Offset value of 0x7b008000
420 13:48:44.546297 SMM Module: placing jmp sequence at 0x7b007c00 rel16 0x03fd
421 13:48:44.552638 SMM Module: placing jmp sequence at 0x7b007800 rel16 0x07fd
422 13:48:44.556215 SMM Module: placing jmp sequence at 0x7b007400 rel16 0x0bfd
423 13:48:44.562654 SMM Module: placing jmp sequence at 0x7b007000 rel16 0x0ffd
424 13:48:44.569297 SMM Module: placing jmp sequence at 0x7b006c00 rel16 0x13fd
425 13:48:44.575740 SMM Module: placing jmp sequence at 0x7b006800 rel16 0x17fd
426 13:48:44.582718 SMM Module: placing jmp sequence at 0x7b006400 rel16 0x1bfd
427 13:48:44.582819 Unable to locate Global NVS
428 13:48:44.592561 SMM Module: stub loaded at 0x7b008000. Will call 0x7b010c16(0x00000000)
429 13:48:44.596110 Clearing SMI status registers
430 13:48:44.596196 SMI_STS: PM1
431 13:48:44.598916 PM1_STS: PWRBTN
432 13:48:44.605615 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b000000, cpu = 0
433 13:48:44.608860 In relocation handler: CPU 0
434 13:48:44.612266 New SMBASE=0x7b000000 IEDBASE=0x7b400000
435 13:48:44.618694 Writing SMRR. base = 0x7b000006, mask=0xff800c00
436 13:48:44.618781 Relocation complete.
437 13:48:44.629163 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afffc00, cpu = 1
438 13:48:44.632207 In relocation handler: CPU 1
439 13:48:44.635744 New SMBASE=0x7afffc00 IEDBASE=0x7b400000
440 13:48:44.635829 Relocation complete.
441 13:48:44.645741 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affec00, cpu = 5
442 13:48:44.648461 In relocation handler: CPU 5
443 13:48:44.651828 New SMBASE=0x7affec00 IEDBASE=0x7b400000
444 13:48:44.655131 Writing SMRR. base = 0x7b000006, mask=0xff800c00
445 13:48:44.658837 Relocation complete.
446 13:48:44.664970 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff800, cpu = 2
447 13:48:44.668927 In relocation handler: CPU 2
448 13:48:44.671864 New SMBASE=0x7afff800 IEDBASE=0x7b400000
449 13:48:44.675189 Relocation complete.
450 13:48:44.681732 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff400, cpu = 3
451 13:48:44.685141 In relocation handler: CPU 3
452 13:48:44.688341 New SMBASE=0x7afff400 IEDBASE=0x7b400000
453 13:48:44.694788 Writing SMRR. base = 0x7b000006, mask=0xff800c00
454 13:48:44.694875 Relocation complete.
455 13:48:44.704806 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affe800, cpu = 6
456 13:48:44.704903 In relocation handler: CPU 6
457 13:48:44.711585 New SMBASE=0x7affe800 IEDBASE=0x7b400000
458 13:48:44.711673 Relocation complete.
459 13:48:44.718260 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affe400, cpu = 7
460 13:48:44.721954 In relocation handler: CPU 7
461 13:48:44.728222 New SMBASE=0x7affe400 IEDBASE=0x7b400000
462 13:48:44.728308 Relocation complete.
463 13:48:44.734683 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff000, cpu = 4
464 13:48:44.737914 In relocation handler: CPU 4
465 13:48:44.744652 New SMBASE=0x7afff000 IEDBASE=0x7b400000
466 13:48:44.747924 Writing SMRR. base = 0x7b000006, mask=0xff800c00
467 13:48:44.751187 Relocation complete.
468 13:48:44.751273 Initializing CPU #0
469 13:48:44.754834 CPU: vendor Intel device 806c1
470 13:48:44.759160 CPU: family 06, model 8c, stepping 01
471 13:48:44.762303 Clearing out pending MCEs
472 13:48:44.765507 Setting up local APIC...
473 13:48:44.765640 apic_id: 0x00 done.
474 13:48:44.768768 Turbo is available but hidden
475 13:48:44.772105 Turbo is available and visible
476 13:48:44.778914 microcode: Update skipped, already up-to-date
477 13:48:44.779026 CPU #0 initialized
478 13:48:44.781990 Initializing CPU #2
479 13:48:44.785257 Initializing CPU #5
480 13:48:44.788832 CPU: vendor Intel device 806c1
481 13:48:44.791967 CPU: family 06, model 8c, stepping 01
482 13:48:44.792051 Initializing CPU #3
483 13:48:44.795404 Initializing CPU #6
484 13:48:44.798824 CPU: vendor Intel device 806c1
485 13:48:44.801778 CPU: family 06, model 8c, stepping 01
486 13:48:44.805197 Initializing CPU #1
487 13:48:44.805279 Clearing out pending MCEs
488 13:48:44.808758 Clearing out pending MCEs
489 13:48:44.811880 Setting up local APIC...
490 13:48:44.815288 Setting up local APIC...
491 13:48:44.815415 Initializing CPU #4
492 13:48:44.818357 Initializing CPU #7
493 13:48:44.821803 CPU: vendor Intel device 806c1
494 13:48:44.824967 CPU: family 06, model 8c, stepping 01
495 13:48:44.828742 CPU: vendor Intel device 806c1
496 13:48:44.831914 CPU: family 06, model 8c, stepping 01
497 13:48:44.835463 Clearing out pending MCEs
498 13:48:44.838891 Clearing out pending MCEs
499 13:48:44.841777 Setting up local APIC...
500 13:48:44.844917 CPU: vendor Intel device 806c1
501 13:48:44.848542 CPU: family 06, model 8c, stepping 01
502 13:48:44.851544 CPU: vendor Intel device 806c1
503 13:48:44.854884 CPU: family 06, model 8c, stepping 01
504 13:48:44.858310 Clearing out pending MCEs
505 13:48:44.858393 Clearing out pending MCEs
506 13:48:44.861545 Setting up local APIC...
507 13:48:44.864751 CPU: vendor Intel device 806c1
508 13:48:44.868307 CPU: family 06, model 8c, stepping 01
509 13:48:44.871486 apic_id: 0x04 done.
510 13:48:44.875049 Setting up local APIC...
511 13:48:44.875132 apic_id: 0x06 done.
512 13:48:44.878002 apic_id: 0x07 done.
513 13:48:44.881431 microcode: Update skipped, already up-to-date
514 13:48:44.887990 microcode: Update skipped, already up-to-date
515 13:48:44.891284 microcode: Update skipped, already up-to-date
516 13:48:44.894618 apic_id: 0x05 done.
517 13:48:44.894702 CPU #4 initialized
518 13:48:44.900966 microcode: Update skipped, already up-to-date
519 13:48:44.901050 CPU #2 initialized
520 13:48:44.904439 CPU #5 initialized
521 13:48:44.907809 CPU #7 initialized
522 13:48:44.907892 apic_id: 0x02 done.
523 13:48:44.911430 Setting up local APIC...
524 13:48:44.914402 Clearing out pending MCEs
525 13:48:44.917610 microcode: Update skipped, already up-to-date
526 13:48:44.921225 apic_id: 0x03 done.
527 13:48:44.921309 CPU #3 initialized
528 13:48:44.927644 microcode: Update skipped, already up-to-date
529 13:48:44.931272 Setting up local APIC...
530 13:48:44.931360 CPU #6 initialized
531 13:48:44.934202 apic_id: 0x01 done.
532 13:48:44.937403 microcode: Update skipped, already up-to-date
533 13:48:44.940694 CPU #1 initialized
534 13:48:44.943986 bsp_do_flight_plan done after 455 msecs.
535 13:48:44.947294 CPU: frequency set to 4000 MHz
536 13:48:44.947378 Enabling SMIs.
537 13:48:44.954027 BS: BS_DEV_INIT_CHIPS entry times (exec / console): 347 / 317 ms
538 13:48:44.971593 SATAXPCIE1 indicates PCIe NVMe is present
539 13:48:44.975072 Probing TPM: done!
540 13:48:44.978280 Connected to device vid:did:rid of 1ae0:0028:00
541 13:48:44.989015 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.6.20/cr50_v1.9308_B.947-551594aae6
542 13:48:44.992053 Initialized TPM device CR50 revision 0
543 13:48:44.995384 Enabling S0i3.4
544 13:48:45.002079 CBFS: Found 'vbt.bin' @0x78a40 size 0x4f0 in mcache @0x76c4c1fc
545 13:48:45.005314 Found a VBT of 8704 bytes after decompression
546 13:48:45.011755 cse_lite: CSE RO boot. HybridStorageMode disabled
547 13:48:45.018304 WEAK: src/soc/intel/tigerlake/fsp_params.c/mainboard_silicon_init_params called
548 13:48:45.093343 FSPS returned 0
549 13:48:45.096677 Executing Phase 1 of FspMultiPhaseSiInit
550 13:48:45.106538 FSP MultiPhaseSiInit src/soc/intel/tigerlake/fsp_params.c/platform_fsp_multi_phase_init_cb called
551 13:48:45.109915 port C0 DISC req: usage 1 usb3 1 usb2 5
552 13:48:45.113122 Raw Buffer output 0 00000511
553 13:48:45.116270 Raw Buffer output 1 00000000
554 13:48:45.119956 pmc_send_ipc_cmd succeeded
555 13:48:45.126716 port C1 DISC req: usage 1 usb3 2 usb2 3
556 13:48:45.126799 Raw Buffer output 0 00000321
557 13:48:45.130035 Raw Buffer output 1 00000000
558 13:48:45.134352 pmc_send_ipc_cmd succeeded
559 13:48:45.139540 Detected 4 core, 8 thread CPU.
560 13:48:45.142952 Detected 4 core, 8 thread CPU.
561 13:48:45.377508 Display FSP Version Info HOB
562 13:48:45.380187 Reference Code - CPU = a.0.4c.31
563 13:48:45.383901 uCode Version = 0.0.0.86
564 13:48:45.386813 TXT ACM version = ff.ff.ff.ffff
565 13:48:45.390521 Reference Code - ME = a.0.4c.31
566 13:48:45.393630 MEBx version = 0.0.0.0
567 13:48:45.396680 ME Firmware Version = Consumer SKU
568 13:48:45.400110 Reference Code - PCH = a.0.4c.31
569 13:48:45.403427 PCH-CRID Status = Disabled
570 13:48:45.406761 PCH-CRID Original Value = ff.ff.ff.ffff
571 13:48:45.410128 PCH-CRID New Value = ff.ff.ff.ffff
572 13:48:45.413743 OPROM - RST - RAID = ff.ff.ff.ffff
573 13:48:45.416398 PCH Hsio Version = 4.0.0.0
574 13:48:45.420062 Reference Code - SA - System Agent = a.0.4c.31
575 13:48:45.423240 Reference Code - MRC = 2.0.0.1
576 13:48:45.426377 SA - PCIe Version = a.0.4c.31
577 13:48:45.429804 SA-CRID Status = Disabled
578 13:48:45.433008 SA-CRID Original Value = 0.0.0.1
579 13:48:45.436333 SA-CRID New Value = 0.0.0.1
580 13:48:45.439747 OPROM - VBIOS = ff.ff.ff.ffff
581 13:48:45.443218 IO Manageability Engine FW Version = 11.1.4.0
582 13:48:45.446191 PHY Build Version = 0.0.0.e0
583 13:48:45.449788 Thunderbolt(TM) FW Version = 0.0.0.0
584 13:48:45.456433 System Agent Manageability Engine FW Version = ff.ff.ff.ffff
585 13:48:45.459372 ITSS IRQ Polarities Before:
586 13:48:45.459454 IPC0: 0xffffffff
587 13:48:45.463161 IPC1: 0xffffffff
588 13:48:45.463243 IPC2: 0xffffffff
589 13:48:45.465942 IPC3: 0xffffffff
590 13:48:45.469278 ITSS IRQ Polarities After:
591 13:48:45.469360 IPC0: 0xffffffff
592 13:48:45.472847 IPC1: 0xffffffff
593 13:48:45.472930 IPC2: 0xffffffff
594 13:48:45.475876 IPC3: 0xffffffff
595 13:48:45.479252 Found PCIe Root Port #9 at PCI: 00:1d.0.
596 13:48:45.492304 pcie_rp_update_dev: Couldn't find PCIe Root Port #1 (originally PCI: 00:1c.0) which was enabled in devicetree, removing.
597 13:48:45.502471 pcie_rp_update_dev: Couldn't find PCIe Root Port #7 (originally PCI: 00:1c.6) which was enabled in devicetree, removing.
598 13:48:45.515446 pcie_rp_update_dev: Couldn't find PCIe Root Port #11 (originally PCI: 00:1d.2) which was enabled in devicetree, removing.
599 13:48:45.522334 BS: BS_DEV_INIT_CHIPS run times (exec / console): 325 / 236 ms
600 13:48:45.525593 Enumerating buses...
601 13:48:45.528844 Show all devs... Before device enumeration.
602 13:48:45.532652 Root Device: enabled 1
603 13:48:45.532734 DOMAIN: 0000: enabled 1
604 13:48:45.535449 CPU_CLUSTER: 0: enabled 1
605 13:48:45.538802 PCI: 00:00.0: enabled 1
606 13:48:45.542253 PCI: 00:02.0: enabled 1
607 13:48:45.542334 PCI: 00:04.0: enabled 1
608 13:48:45.545483 PCI: 00:05.0: enabled 1
609 13:48:45.548946 PCI: 00:06.0: enabled 0
610 13:48:45.552036 PCI: 00:07.0: enabled 0
611 13:48:45.552117 PCI: 00:07.1: enabled 0
612 13:48:45.555662 PCI: 00:07.2: enabled 0
613 13:48:45.558603 PCI: 00:07.3: enabled 0
614 13:48:45.561886 PCI: 00:08.0: enabled 1
615 13:48:45.561967 PCI: 00:09.0: enabled 0
616 13:48:45.565469 PCI: 00:0a.0: enabled 0
617 13:48:45.568831 PCI: 00:0d.0: enabled 1
618 13:48:45.572023 PCI: 00:0d.1: enabled 0
619 13:48:45.572104 PCI: 00:0d.2: enabled 0
620 13:48:45.575177 PCI: 00:0d.3: enabled 0
621 13:48:45.578417 PCI: 00:0e.0: enabled 0
622 13:48:45.582118 PCI: 00:10.2: enabled 1
623 13:48:45.582215 PCI: 00:10.6: enabled 0
624 13:48:45.585168 PCI: 00:10.7: enabled 0
625 13:48:45.588432 PCI: 00:12.0: enabled 0
626 13:48:45.588514 PCI: 00:12.6: enabled 0
627 13:48:45.591672 PCI: 00:13.0: enabled 0
628 13:48:45.595085 PCI: 00:14.0: enabled 1
629 13:48:45.598496 PCI: 00:14.1: enabled 0
630 13:48:45.598579 PCI: 00:14.2: enabled 1
631 13:48:45.601829 PCI: 00:14.3: enabled 1
632 13:48:45.605297 PCI: 00:15.0: enabled 1
633 13:48:45.608667 PCI: 00:15.1: enabled 1
634 13:48:45.608749 PCI: 00:15.2: enabled 1
635 13:48:45.611766 PCI: 00:15.3: enabled 1
636 13:48:45.615255 PCI: 00:16.0: enabled 1
637 13:48:45.618530 PCI: 00:16.1: enabled 0
638 13:48:45.618631 PCI: 00:16.2: enabled 0
639 13:48:45.621651 PCI: 00:16.3: enabled 0
640 13:48:45.625090 PCI: 00:16.4: enabled 0
641 13:48:45.628246 PCI: 00:16.5: enabled 0
642 13:48:45.628327 PCI: 00:17.0: enabled 1
643 13:48:45.631666 PCI: 00:19.0: enabled 0
644 13:48:45.634961 PCI: 00:19.1: enabled 1
645 13:48:45.635043 PCI: 00:19.2: enabled 0
646 13:48:45.638476 PCI: 00:1c.0: enabled 1
647 13:48:45.641346 PCI: 00:1c.1: enabled 0
648 13:48:45.644958 PCI: 00:1c.2: enabled 0
649 13:48:45.645039 PCI: 00:1c.3: enabled 0
650 13:48:45.647781 PCI: 00:1c.4: enabled 0
651 13:48:45.651485 PCI: 00:1c.5: enabled 0
652 13:48:45.654430 PCI: 00:1c.6: enabled 1
653 13:48:45.654511 PCI: 00:1c.7: enabled 0
654 13:48:45.658338 PCI: 00:1d.0: enabled 1
655 13:48:45.661279 PCI: 00:1d.1: enabled 0
656 13:48:45.664749 PCI: 00:1d.2: enabled 1
657 13:48:45.664831 PCI: 00:1d.3: enabled 0
658 13:48:45.667683 PCI: 00:1e.0: enabled 1
659 13:48:45.671272 PCI: 00:1e.1: enabled 0
660 13:48:45.674862 PCI: 00:1e.2: enabled 1
661 13:48:45.674944 PCI: 00:1e.3: enabled 1
662 13:48:45.677854 PCI: 00:1f.0: enabled 1
663 13:48:45.681167 PCI: 00:1f.1: enabled 0
664 13:48:45.685232 PCI: 00:1f.2: enabled 1
665 13:48:45.685315 PCI: 00:1f.3: enabled 1
666 13:48:45.687711 PCI: 00:1f.4: enabled 0
667 13:48:45.691166 PCI: 00:1f.5: enabled 1
668 13:48:45.694193 PCI: 00:1f.6: enabled 0
669 13:48:45.694273 PCI: 00:1f.7: enabled 0
670 13:48:45.697553 APIC: 00: enabled 1
671 13:48:45.700740 GENERIC: 0.0: enabled 1
672 13:48:45.700821 GENERIC: 0.0: enabled 1
673 13:48:45.704144 GENERIC: 1.0: enabled 1
674 13:48:45.707614 GENERIC: 0.0: enabled 1
675 13:48:45.710950 GENERIC: 1.0: enabled 1
676 13:48:45.711031 USB0 port 0: enabled 1
677 13:48:45.714456 GENERIC: 0.0: enabled 1
678 13:48:45.717356 USB0 port 0: enabled 1
679 13:48:45.717437 GENERIC: 0.0: enabled 1
680 13:48:45.720736 I2C: 00:1a: enabled 1
681 13:48:45.724119 I2C: 00:31: enabled 1
682 13:48:45.727075 I2C: 00:32: enabled 1
683 13:48:45.727156 I2C: 00:10: enabled 1
684 13:48:45.730558 I2C: 00:15: enabled 1
685 13:48:45.733796 GENERIC: 0.0: enabled 0
686 13:48:45.733877 GENERIC: 1.0: enabled 0
687 13:48:45.737343 GENERIC: 0.0: enabled 1
688 13:48:45.740828 SPI: 00: enabled 1
689 13:48:45.740909 SPI: 00: enabled 1
690 13:48:45.743816 PNP: 0c09.0: enabled 1
691 13:48:45.747367 GENERIC: 0.0: enabled 1
692 13:48:45.747447 USB3 port 0: enabled 1
693 13:48:45.750238 USB3 port 1: enabled 1
694 13:48:45.753570 USB3 port 2: enabled 0
695 13:48:45.756941 USB3 port 3: enabled 0
696 13:48:45.757022 USB2 port 0: enabled 0
697 13:48:45.760377 USB2 port 1: enabled 1
698 13:48:45.763579 USB2 port 2: enabled 1
699 13:48:45.763661 USB2 port 3: enabled 0
700 13:48:45.766736 USB2 port 4: enabled 1
701 13:48:45.770373 USB2 port 5: enabled 0
702 13:48:45.773506 USB2 port 6: enabled 0
703 13:48:45.773588 USB2 port 7: enabled 0
704 13:48:45.776732 USB2 port 8: enabled 0
705 13:48:45.780188 USB2 port 9: enabled 0
706 13:48:45.780269 USB3 port 0: enabled 0
707 13:48:45.783668 USB3 port 1: enabled 1
708 13:48:45.786971 USB3 port 2: enabled 0
709 13:48:45.790176 USB3 port 3: enabled 0
710 13:48:45.790257 GENERIC: 0.0: enabled 1
711 13:48:45.793398 GENERIC: 1.0: enabled 1
712 13:48:45.796566 APIC: 01: enabled 1
713 13:48:45.796646 APIC: 07: enabled 1
714 13:48:45.799909 APIC: 02: enabled 1
715 13:48:45.799991 APIC: 04: enabled 1
716 13:48:45.803136 APIC: 06: enabled 1
717 13:48:45.806490 APIC: 03: enabled 1
718 13:48:45.806624 APIC: 05: enabled 1
719 13:48:45.809988 Compare with tree...
720 13:48:45.813290 Root Device: enabled 1
721 13:48:45.816368 DOMAIN: 0000: enabled 1
722 13:48:45.816449 PCI: 00:00.0: enabled 1
723 13:48:45.819594 PCI: 00:02.0: enabled 1
724 13:48:45.823076 PCI: 00:04.0: enabled 1
725 13:48:45.826709 GENERIC: 0.0: enabled 1
726 13:48:45.829537 PCI: 00:05.0: enabled 1
727 13:48:45.829618 PCI: 00:06.0: enabled 0
728 13:48:45.832910 PCI: 00:07.0: enabled 0
729 13:48:45.836239 GENERIC: 0.0: enabled 1
730 13:48:45.839477 PCI: 00:07.1: enabled 0
731 13:48:45.842866 GENERIC: 1.0: enabled 1
732 13:48:45.842947 PCI: 00:07.2: enabled 0
733 13:48:45.846023 GENERIC: 0.0: enabled 1
734 13:48:45.849644 PCI: 00:07.3: enabled 0
735 13:48:45.853070 GENERIC: 1.0: enabled 1
736 13:48:45.856274 PCI: 00:08.0: enabled 1
737 13:48:45.856356 PCI: 00:09.0: enabled 0
738 13:48:45.859464 PCI: 00:0a.0: enabled 0
739 13:48:45.862737 PCI: 00:0d.0: enabled 1
740 13:48:45.865900 USB0 port 0: enabled 1
741 13:48:45.869478 USB3 port 0: enabled 1
742 13:48:45.869559 USB3 port 1: enabled 1
743 13:48:45.872598 USB3 port 2: enabled 0
744 13:48:45.876057 USB3 port 3: enabled 0
745 13:48:45.879330 PCI: 00:0d.1: enabled 0
746 13:48:45.882737 PCI: 00:0d.2: enabled 0
747 13:48:45.886088 GENERIC: 0.0: enabled 1
748 13:48:45.886169 PCI: 00:0d.3: enabled 0
749 13:48:45.889157 PCI: 00:0e.0: enabled 0
750 13:48:45.892403 PCI: 00:10.2: enabled 1
751 13:48:45.895744 PCI: 00:10.6: enabled 0
752 13:48:45.898955 PCI: 00:10.7: enabled 0
753 13:48:45.899036 PCI: 00:12.0: enabled 0
754 13:48:45.902475 PCI: 00:12.6: enabled 0
755 13:48:45.905659 PCI: 00:13.0: enabled 0
756 13:48:45.908855 PCI: 00:14.0: enabled 1
757 13:48:45.912527 USB0 port 0: enabled 1
758 13:48:45.912607 USB2 port 0: enabled 0
759 13:48:45.915470 USB2 port 1: enabled 1
760 13:48:45.918928 USB2 port 2: enabled 1
761 13:48:45.922951 USB2 port 3: enabled 0
762 13:48:45.925474 USB2 port 4: enabled 1
763 13:48:45.925606 USB2 port 5: enabled 0
764 13:48:45.928946 USB2 port 6: enabled 0
765 13:48:45.932077 USB2 port 7: enabled 0
766 13:48:45.935454 USB2 port 8: enabled 0
767 13:48:45.938895 USB2 port 9: enabled 0
768 13:48:45.942133 USB3 port 0: enabled 0
769 13:48:45.942216 USB3 port 1: enabled 1
770 13:48:45.945273 USB3 port 2: enabled 0
771 13:48:45.948580 USB3 port 3: enabled 0
772 13:48:45.951685 PCI: 00:14.1: enabled 0
773 13:48:45.955375 PCI: 00:14.2: enabled 1
774 13:48:45.958438 PCI: 00:14.3: enabled 1
775 13:48:45.958521 GENERIC: 0.0: enabled 1
776 13:48:45.961872 PCI: 00:15.0: enabled 1
777 13:48:45.965130 I2C: 00:1a: enabled 1
778 13:48:45.968398 I2C: 00:31: enabled 1
779 13:48:45.968485 I2C: 00:32: enabled 1
780 13:48:45.971728 PCI: 00:15.1: enabled 1
781 13:48:45.974794 I2C: 00:10: enabled 1
782 13:48:45.978111 PCI: 00:15.2: enabled 1
783 13:48:45.981634 PCI: 00:15.3: enabled 1
784 13:48:45.981717 PCI: 00:16.0: enabled 1
785 13:48:45.984943 PCI: 00:16.1: enabled 0
786 13:48:45.988172 PCI: 00:16.2: enabled 0
787 13:48:45.991617 PCI: 00:16.3: enabled 0
788 13:48:45.994824 PCI: 00:16.4: enabled 0
789 13:48:45.994908 PCI: 00:16.5: enabled 0
790 13:48:45.999218 PCI: 00:17.0: enabled 1
791 13:48:46.002492 PCI: 00:19.0: enabled 0
792 13:48:46.002575 PCI: 00:19.1: enabled 1
793 13:48:46.005925 I2C: 00:15: enabled 1
794 13:48:46.009402 PCI: 00:19.2: enabled 0
795 13:48:46.012537 PCI: 00:1d.0: enabled 1
796 13:48:46.016262 GENERIC: 0.0: enabled 1
797 13:48:46.016345 PCI: 00:1e.0: enabled 1
798 13:48:46.065515 PCI: 00:1e.1: enabled 0
799 13:48:46.065637 PCI: 00:1e.2: enabled 1
800 13:48:46.065924 SPI: 00: enabled 1
801 13:48:46.065992 PCI: 00:1e.3: enabled 1
802 13:48:46.066053 SPI: 00: enabled 1
803 13:48:46.066121 PCI: 00:1f.0: enabled 1
804 13:48:46.066242 PNP: 0c09.0: enabled 1
805 13:48:46.066346 PCI: 00:1f.1: enabled 0
806 13:48:46.066470 PCI: 00:1f.2: enabled 1
807 13:48:46.066585 GENERIC: 0.0: enabled 1
808 13:48:46.066703 GENERIC: 0.0: enabled 1
809 13:48:46.066760 GENERIC: 1.0: enabled 1
810 13:48:46.067045 PCI: 00:1f.3: enabled 1
811 13:48:46.067137 PCI: 00:1f.4: enabled 0
812 13:48:46.067451 PCI: 00:1f.5: enabled 1
813 13:48:46.067542 PCI: 00:1f.6: enabled 0
814 13:48:46.067703 PCI: 00:1f.7: enabled 0
815 13:48:46.067820 CPU_CLUSTER: 0: enabled 1
816 13:48:46.067918 APIC: 00: enabled 1
817 13:48:46.070491 APIC: 01: enabled 1
818 13:48:46.070587 APIC: 07: enabled 1
819 13:48:46.073874 APIC: 02: enabled 1
820 13:48:46.077142 APIC: 04: enabled 1
821 13:48:46.077223 APIC: 06: enabled 1
822 13:48:46.080581 APIC: 03: enabled 1
823 13:48:46.083778 APIC: 05: enabled 1
824 13:48:46.087251 Root Device scanning...
825 13:48:46.090286 scan_static_bus for Root Device
826 13:48:46.090367 DOMAIN: 0000 enabled
827 13:48:46.093713 CPU_CLUSTER: 0 enabled
828 13:48:46.096946 DOMAIN: 0000 scanning...
829 13:48:46.100108 PCI: pci_scan_bus for bus 00
830 13:48:46.103489 PCI: 00:00.0 [8086/0000] ops
831 13:48:46.107086 PCI: 00:00.0 [8086/9a12] enabled
832 13:48:46.110167 PCI: 00:02.0 [8086/0000] bus ops
833 13:48:46.113295 PCI: 00:02.0 [8086/9a40] enabled
834 13:48:46.116990 PCI: 00:04.0 [8086/0000] bus ops
835 13:48:46.119861 PCI: 00:04.0 [8086/9a03] enabled
836 13:48:46.123511 PCI: 00:05.0 [8086/9a19] enabled
837 13:48:46.126689 PCI: 00:07.0 [0000/0000] hidden
838 13:48:46.129806 PCI: 00:08.0 [8086/9a11] enabled
839 13:48:46.133402 PCI: 00:0a.0 [8086/9a0d] disabled
840 13:48:46.136651 PCI: 00:0d.0 [8086/0000] bus ops
841 13:48:46.139719 PCI: 00:0d.0 [8086/9a13] enabled
842 13:48:46.143221 PCI: 00:14.0 [8086/0000] bus ops
843 13:48:46.146513 PCI: 00:14.0 [8086/a0ed] enabled
844 13:48:46.149729 PCI: 00:14.2 [8086/a0ef] enabled
845 13:48:46.153151 PCI: 00:14.3 [8086/0000] bus ops
846 13:48:46.156344 PCI: 00:14.3 [8086/a0f0] enabled
847 13:48:46.159739 PCI: 00:15.0 [8086/0000] bus ops
848 13:48:46.162898 PCI: 00:15.0 [8086/a0e8] enabled
849 13:48:46.166142 PCI: 00:15.1 [8086/0000] bus ops
850 13:48:46.169535 PCI: 00:15.1 [8086/a0e9] enabled
851 13:48:46.173020 PCI: 00:15.2 [8086/0000] bus ops
852 13:48:46.176201 PCI: 00:15.2 [8086/a0ea] enabled
853 13:48:46.179271 PCI: 00:15.3 [8086/0000] bus ops
854 13:48:46.182498 PCI: 00:15.3 [8086/a0eb] enabled
855 13:48:46.186061 PCI: 00:16.0 [8086/0000] ops
856 13:48:46.189500 PCI: 00:16.0 [8086/a0e0] enabled
857 13:48:46.195780 PCI: Static device PCI: 00:17.0 not found, disabling it.
858 13:48:46.199123 PCI: 00:19.0 [8086/0000] bus ops
859 13:48:46.202788 PCI: 00:19.0 [8086/a0c5] disabled
860 13:48:46.205783 PCI: 00:19.1 [8086/0000] bus ops
861 13:48:46.209221 PCI: 00:19.1 [8086/a0c6] enabled
862 13:48:46.212472 PCI: 00:1d.0 [8086/0000] bus ops
863 13:48:46.216219 PCI: 00:1d.0 [8086/a0b0] enabled
864 13:48:46.218963 PCI: 00:1e.0 [8086/0000] ops
865 13:48:46.222394 PCI: 00:1e.0 [8086/a0a8] enabled
866 13:48:46.226001 PCI: 00:1e.2 [8086/0000] bus ops
867 13:48:46.228841 PCI: 00:1e.2 [8086/a0aa] enabled
868 13:48:46.232094 PCI: 00:1e.3 [8086/0000] bus ops
869 13:48:46.235479 PCI: 00:1e.3 [8086/a0ab] enabled
870 13:48:46.238938 PCI: 00:1f.0 [8086/0000] bus ops
871 13:48:46.241917 PCI: 00:1f.0 [8086/a087] enabled
872 13:48:46.241999 RTC Init
873 13:48:46.245450 Set power on after power failure.
874 13:48:46.248800 Disabling Deep S3
875 13:48:46.248883 Disabling Deep S3
876 13:48:46.252025 Disabling Deep S4
877 13:48:46.255322 Disabling Deep S4
878 13:48:46.255405 Disabling Deep S5
879 13:48:46.258929 Disabling Deep S5
880 13:48:46.261840 PCI: 00:1f.2 [0000/0000] hidden
881 13:48:46.265079 PCI: 00:1f.3 [8086/0000] bus ops
882 13:48:46.268466 PCI: 00:1f.3 [8086/a0c8] enabled
883 13:48:46.271767 PCI: 00:1f.5 [8086/0000] bus ops
884 13:48:46.275032 PCI: 00:1f.5 [8086/a0a4] enabled
885 13:48:46.278270 PCI: Leftover static devices:
886 13:48:46.278352 PCI: 00:10.2
887 13:48:46.278417 PCI: 00:10.6
888 13:48:46.281743 PCI: 00:10.7
889 13:48:46.281825 PCI: 00:06.0
890 13:48:46.285110 PCI: 00:07.1
891 13:48:46.285193 PCI: 00:07.2
892 13:48:46.285258 PCI: 00:07.3
893 13:48:46.288206 PCI: 00:09.0
894 13:48:46.288289 PCI: 00:0d.1
895 13:48:46.292064 PCI: 00:0d.2
896 13:48:46.292146 PCI: 00:0d.3
897 13:48:46.294903 PCI: 00:0e.0
898 13:48:46.294985 PCI: 00:12.0
899 13:48:46.295051 PCI: 00:12.6
900 13:48:46.298345 PCI: 00:13.0
901 13:48:46.298428 PCI: 00:14.1
902 13:48:46.301577 PCI: 00:16.1
903 13:48:46.301660 PCI: 00:16.2
904 13:48:46.305000 PCI: 00:16.3
905 13:48:46.305083 PCI: 00:16.4
906 13:48:46.305148 PCI: 00:16.5
907 13:48:46.308159 PCI: 00:17.0
908 13:48:46.308242 PCI: 00:19.2
909 13:48:46.311266 PCI: 00:1e.1
910 13:48:46.311348 PCI: 00:1f.1
911 13:48:46.311415 PCI: 00:1f.4
912 13:48:46.314551 PCI: 00:1f.6
913 13:48:46.314643 PCI: 00:1f.7
914 13:48:46.318192 PCI: Check your devicetree.cb.
915 13:48:46.321143 PCI: 00:02.0 scanning...
916 13:48:46.324554 scan_generic_bus for PCI: 00:02.0
917 13:48:46.327878 scan_generic_bus for PCI: 00:02.0 done
918 13:48:46.334309 scan_bus: bus PCI: 00:02.0 finished in 7 msecs
919 13:48:46.334392 PCI: 00:04.0 scanning...
920 13:48:46.341258 scan_generic_bus for PCI: 00:04.0
921 13:48:46.341341 GENERIC: 0.0 enabled
922 13:48:46.347950 bus: PCI: 00:04.0[0]->scan_generic_bus for PCI: 00:04.0 done
923 13:48:46.351136 scan_bus: bus PCI: 00:04.0 finished in 11 msecs
924 13:48:46.354571 PCI: 00:0d.0 scanning...
925 13:48:46.357849 scan_static_bus for PCI: 00:0d.0
926 13:48:46.360910 USB0 port 0 enabled
927 13:48:46.364239 USB0 port 0 scanning...
928 13:48:46.367479 scan_static_bus for USB0 port 0
929 13:48:46.367589 USB3 port 0 enabled
930 13:48:46.370987 USB3 port 1 enabled
931 13:48:46.374177 USB3 port 2 disabled
932 13:48:46.374260 USB3 port 3 disabled
933 13:48:46.377624 USB3 port 0 scanning...
934 13:48:46.380812 scan_static_bus for USB3 port 0
935 13:48:46.384278 scan_static_bus for USB3 port 0 done
936 13:48:46.390528 scan_bus: bus USB3 port 0 finished in 6 msecs
937 13:48:46.390672 USB3 port 1 scanning...
938 13:48:46.393896 scan_static_bus for USB3 port 1
939 13:48:46.397447 scan_static_bus for USB3 port 1 done
940 13:48:46.404094 scan_bus: bus USB3 port 1 finished in 6 msecs
941 13:48:46.407337 scan_static_bus for USB0 port 0 done
942 13:48:46.410522 scan_bus: bus USB0 port 0 finished in 43 msecs
943 13:48:46.417708 scan_static_bus for PCI: 00:0d.0 done
944 13:48:46.420443 scan_bus: bus PCI: 00:0d.0 finished in 60 msecs
945 13:48:46.423803 PCI: 00:14.0 scanning...
946 13:48:46.427172 scan_static_bus for PCI: 00:14.0
947 13:48:46.427255 USB0 port 0 enabled
948 13:48:46.430277 USB0 port 0 scanning...
949 13:48:46.433605 scan_static_bus for USB0 port 0
950 13:48:46.437259 USB2 port 0 disabled
951 13:48:46.440553 USB2 port 1 enabled
952 13:48:46.440636 USB2 port 2 enabled
953 13:48:46.443758 USB2 port 3 disabled
954 13:48:46.443841 USB2 port 4 enabled
955 13:48:46.446788 USB2 port 5 disabled
956 13:48:46.450318 USB2 port 6 disabled
957 13:48:46.450401 USB2 port 7 disabled
958 13:48:46.453684 USB2 port 8 disabled
959 13:48:46.457226 USB2 port 9 disabled
960 13:48:46.457309 USB3 port 0 disabled
961 13:48:46.460207 USB3 port 1 enabled
962 13:48:46.463644 USB3 port 2 disabled
963 13:48:46.463727 USB3 port 3 disabled
964 13:48:46.466531 USB2 port 1 scanning...
965 13:48:46.470155 scan_static_bus for USB2 port 1
966 13:48:46.473495 scan_static_bus for USB2 port 1 done
967 13:48:46.479882 scan_bus: bus USB2 port 1 finished in 6 msecs
968 13:48:46.479964 USB2 port 2 scanning...
969 13:48:46.483135 scan_static_bus for USB2 port 2
970 13:48:46.486623 scan_static_bus for USB2 port 2 done
971 13:48:46.493199 scan_bus: bus USB2 port 2 finished in 6 msecs
972 13:48:46.496532 USB2 port 4 scanning...
973 13:48:46.499866 scan_static_bus for USB2 port 4
974 13:48:46.503132 scan_static_bus for USB2 port 4 done
975 13:48:46.506742 scan_bus: bus USB2 port 4 finished in 6 msecs
976 13:48:46.510146 USB3 port 1 scanning...
977 13:48:46.512941 scan_static_bus for USB3 port 1
978 13:48:46.516345 scan_static_bus for USB3 port 1 done
979 13:48:46.519825 scan_bus: bus USB3 port 1 finished in 6 msecs
980 13:48:46.526368 scan_static_bus for USB0 port 0 done
981 13:48:46.529764 scan_bus: bus USB0 port 0 finished in 93 msecs
982 13:48:46.533039 scan_static_bus for PCI: 00:14.0 done
983 13:48:46.539532 scan_bus: bus PCI: 00:14.0 finished in 110 msecs
984 13:48:46.539615 PCI: 00:14.3 scanning...
985 13:48:46.542999 scan_static_bus for PCI: 00:14.3
986 13:48:46.546546 GENERIC: 0.0 enabled
987 13:48:46.549529 scan_static_bus for PCI: 00:14.3 done
988 13:48:46.556126 scan_bus: bus PCI: 00:14.3 finished in 9 msecs
989 13:48:46.556210 PCI: 00:15.0 scanning...
990 13:48:46.559462 scan_static_bus for PCI: 00:15.0
991 13:48:46.562534 I2C: 00:1a enabled
992 13:48:46.566061 I2C: 00:31 enabled
993 13:48:46.566144 I2C: 00:32 enabled
994 13:48:46.569396 scan_static_bus for PCI: 00:15.0 done
995 13:48:46.576958 scan_bus: bus PCI: 00:15.0 finished in 12 msecs
996 13:48:46.577056 PCI: 00:15.1 scanning...
997 13:48:46.579989 scan_static_bus for PCI: 00:15.1
998 13:48:46.583499 I2C: 00:10 enabled
999 13:48:46.586540 scan_static_bus for PCI: 00:15.1 done
1000 13:48:46.593037 scan_bus: bus PCI: 00:15.1 finished in 9 msecs
1001 13:48:46.593162 PCI: 00:15.2 scanning...
1002 13:48:46.596365 scan_static_bus for PCI: 00:15.2
1003 13:48:46.603483 scan_static_bus for PCI: 00:15.2 done
1004 13:48:46.606572 scan_bus: bus PCI: 00:15.2 finished in 7 msecs
1005 13:48:46.610743 PCI: 00:15.3 scanning...
1006 13:48:46.613023 scan_static_bus for PCI: 00:15.3
1007 13:48:46.616724 scan_static_bus for PCI: 00:15.3 done
1008 13:48:46.620068 scan_bus: bus PCI: 00:15.3 finished in 7 msecs
1009 13:48:46.622691 PCI: 00:19.1 scanning...
1010 13:48:46.626120 scan_static_bus for PCI: 00:19.1
1011 13:48:46.629723 I2C: 00:15 enabled
1012 13:48:46.632674 scan_static_bus for PCI: 00:19.1 done
1013 13:48:46.636420 scan_bus: bus PCI: 00:19.1 finished in 9 msecs
1014 13:48:46.639845 PCI: 00:1d.0 scanning...
1015 13:48:46.642848 do_pci_scan_bridge for PCI: 00:1d.0
1016 13:48:46.646164 PCI: pci_scan_bus for bus 01
1017 13:48:46.649431 PCI: 01:00.0 [1c5c/174a] enabled
1018 13:48:46.652926 GENERIC: 0.0 enabled
1019 13:48:46.656248 Enabling Common Clock Configuration
1020 13:48:46.659230 L1 Sub-State supported from root port 29
1021 13:48:46.662492 L1 Sub-State Support = 0xf
1022 13:48:46.665717 CommonModeRestoreTime = 0x28
1023 13:48:46.669059 Power On Value = 0x16, Power On Scale = 0x0
1024 13:48:46.672584 ASPM: Enabled L1
1025 13:48:46.676119 PCIe: Max_Payload_Size adjusted to 128
1026 13:48:46.682312 scan_bus: bus PCI: 00:1d.0 finished in 35 msecs
1027 13:48:46.682394 PCI: 00:1e.2 scanning...
1028 13:48:46.688899 scan_generic_bus for PCI: 00:1e.2
1029 13:48:46.688982 SPI: 00 enabled
1030 13:48:46.695469 bus: PCI: 00:1e.2[0]->scan_generic_bus for PCI: 00:1e.2 done
1031 13:48:46.699024 scan_bus: bus PCI: 00:1e.2 finished in 11 msecs
1032 13:48:46.702049 PCI: 00:1e.3 scanning...
1033 13:48:46.705564 scan_generic_bus for PCI: 00:1e.3
1034 13:48:46.708623 SPI: 00 enabled
1035 13:48:46.715337 bus: PCI: 00:1e.3[0]->scan_generic_bus for PCI: 00:1e.3 done
1036 13:48:46.718822 scan_bus: bus PCI: 00:1e.3 finished in 11 msecs
1037 13:48:46.721996 PCI: 00:1f.0 scanning...
1038 13:48:46.725176 scan_static_bus for PCI: 00:1f.0
1039 13:48:46.725258 PNP: 0c09.0 enabled
1040 13:48:46.728539 PNP: 0c09.0 scanning...
1041 13:48:46.731916 scan_static_bus for PNP: 0c09.0
1042 13:48:46.735180 scan_static_bus for PNP: 0c09.0 done
1043 13:48:46.741816 scan_bus: bus PNP: 0c09.0 finished in 6 msecs
1044 13:48:46.745021 scan_static_bus for PCI: 00:1f.0 done
1045 13:48:46.748542 scan_bus: bus PCI: 00:1f.0 finished in 23 msecs
1046 13:48:46.751898 PCI: 00:1f.2 scanning...
1047 13:48:46.755440 scan_static_bus for PCI: 00:1f.2
1048 13:48:46.758219 GENERIC: 0.0 enabled
1049 13:48:46.761757 GENERIC: 0.0 scanning...
1050 13:48:46.765059 scan_static_bus for GENERIC: 0.0
1051 13:48:46.765142 GENERIC: 0.0 enabled
1052 13:48:46.768072 GENERIC: 1.0 enabled
1053 13:48:46.771401 scan_static_bus for GENERIC: 0.0 done
1054 13:48:46.778079 scan_bus: bus GENERIC: 0.0 finished in 11 msecs
1055 13:48:46.781413 scan_static_bus for PCI: 00:1f.2 done
1056 13:48:46.784878 scan_bus: bus PCI: 00:1f.2 finished in 28 msecs
1057 13:48:46.787996 PCI: 00:1f.3 scanning...
1058 13:48:46.791334 scan_static_bus for PCI: 00:1f.3
1059 13:48:46.794441 scan_static_bus for PCI: 00:1f.3 done
1060 13:48:46.801360 scan_bus: bus PCI: 00:1f.3 finished in 7 msecs
1061 13:48:46.801443 PCI: 00:1f.5 scanning...
1062 13:48:46.804859 scan_generic_bus for PCI: 00:1f.5
1063 13:48:46.811345 scan_generic_bus for PCI: 00:1f.5 done
1064 13:48:46.814410 scan_bus: bus PCI: 00:1f.5 finished in 7 msecs
1065 13:48:46.821355 scan_bus: bus DOMAIN: 0000 finished in 717 msecs
1066 13:48:46.824395 scan_static_bus for Root Device done
1067 13:48:46.827969 scan_bus: bus Root Device finished in 736 msecs
1068 13:48:46.828052 done
1069 13:48:46.834698 BS: BS_DEV_ENUMERATE run times (exec / console): 11 / 1296 ms
1070 13:48:46.837541 Chrome EC: UHEPI supported
1071 13:48:46.844150 FMAP: area UNIFIED_MRC_CACHE found @ f00000 (196608 bytes)
1072 13:48:46.850810 SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
1073 13:48:46.854154 SPI flash protection: WPSW=1 SRP0=0
1074 13:48:46.857249 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
1075 13:48:46.863966 BS: BS_DEV_ENUMERATE exit times (exec / console): 1 / 23 ms
1076 13:48:46.867435 found VGA at PCI: 00:02.0
1077 13:48:46.870547 Setting up VGA for PCI: 00:02.0
1078 13:48:46.877510 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
1079 13:48:46.880638 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
1080 13:48:46.883905 Allocating resources...
1081 13:48:46.883986 Reading resources...
1082 13:48:46.891182 Root Device read_resources bus 0 link: 0
1083 13:48:46.893930 DOMAIN: 0000 read_resources bus 0 link: 0
1084 13:48:46.900543 PCI: 00:04.0 read_resources bus 1 link: 0
1085 13:48:46.903808 PCI: 00:04.0 read_resources bus 1 link: 0 done
1086 13:48:46.910143 PCI: 00:0d.0 read_resources bus 0 link: 0
1087 13:48:46.913469 USB0 port 0 read_resources bus 0 link: 0
1088 13:48:46.919815 USB0 port 0 read_resources bus 0 link: 0 done
1089 13:48:46.923284 PCI: 00:0d.0 read_resources bus 0 link: 0 done
1090 13:48:46.929965 PCI: 00:14.0 read_resources bus 0 link: 0
1091 13:48:46.933072 USB0 port 0 read_resources bus 0 link: 0
1092 13:48:46.939816 USB0 port 0 read_resources bus 0 link: 0 done
1093 13:48:46.943300 PCI: 00:14.0 read_resources bus 0 link: 0 done
1094 13:48:46.949999 PCI: 00:14.3 read_resources bus 0 link: 0
1095 13:48:46.952882 PCI: 00:14.3 read_resources bus 0 link: 0 done
1096 13:48:46.959338 PCI: 00:15.0 read_resources bus 0 link: 0
1097 13:48:46.962626 PCI: 00:15.0 read_resources bus 0 link: 0 done
1098 13:48:46.969306 PCI: 00:15.1 read_resources bus 0 link: 0
1099 13:48:46.972734 PCI: 00:15.1 read_resources bus 0 link: 0 done
1100 13:48:46.979573 PCI: 00:19.1 read_resources bus 0 link: 0
1101 13:48:46.982812 PCI: 00:19.1 read_resources bus 0 link: 0 done
1102 13:48:46.989254 PCI: 00:1d.0 read_resources bus 1 link: 0
1103 13:48:46.992831 PCI: 00:1d.0 read_resources bus 1 link: 0 done
1104 13:48:46.999429 PCI: 00:1e.2 read_resources bus 2 link: 0
1105 13:48:47.003021 PCI: 00:1e.2 read_resources bus 2 link: 0 done
1106 13:48:47.009301 PCI: 00:1e.3 read_resources bus 3 link: 0
1107 13:48:47.012783 PCI: 00:1e.3 read_resources bus 3 link: 0 done
1108 13:48:47.019240 PCI: 00:1f.0 read_resources bus 0 link: 0
1109 13:48:47.023097 PCI: 00:1f.0 read_resources bus 0 link: 0 done
1110 13:48:47.029375 PCI: 00:1f.2 read_resources bus 0 link: 0
1111 13:48:47.032668 GENERIC: 0.0 read_resources bus 0 link: 0
1112 13:48:47.038887 GENERIC: 0.0 read_resources bus 0 link: 0 done
1113 13:48:47.042520 PCI: 00:1f.2 read_resources bus 0 link: 0 done
1114 13:48:47.048931 DOMAIN: 0000 read_resources bus 0 link: 0 done
1115 13:48:47.052146 CPU_CLUSTER: 0 read_resources bus 0 link: 0
1116 13:48:47.058975 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
1117 13:48:47.062166 Root Device read_resources bus 0 link: 0 done
1118 13:48:47.065252 Done reading resources.
1119 13:48:47.071849 Show resources in subtree (Root Device)...After reading.
1120 13:48:47.075494 Root Device child on link 0 DOMAIN: 0000
1121 13:48:47.078357 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1122 13:48:47.088171 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1123 13:48:47.098289 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100
1124 13:48:47.101460 PCI: 00:00.0
1125 13:48:47.108071 PCI: 00:00.0 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1126 13:48:47.118121 PCI: 00:00.0 resource base fedc0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1
1127 13:48:47.127977 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1128 13:48:47.137808 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1129 13:48:47.147555 PCI: 00:00.0 resource base fb000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1130 13:48:47.157744 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1131 13:48:47.167392 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 6
1132 13:48:47.174112 PCI: 00:00.0 resource base fed92000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1133 13:48:47.184591 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1134 13:48:47.194127 PCI: 00:00.0 resource base fed85000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9
1135 13:48:47.203947 PCI: 00:00.0 resource base fed86000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
1136 13:48:47.213823 PCI: 00:00.0 resource base fed87000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b
1137 13:48:47.223788 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c
1138 13:48:47.230452 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index d
1139 13:48:47.240145 PCI: 00:00.0 resource base c0000 size 76f40000 align 0 gran 0 limit 0 flags e0004200 index e
1140 13:48:47.250173 PCI: 00:00.0 resource base 77000000 size 8c00000 align 0 gran 0 limit 0 flags f0000200 index f
1141 13:48:47.259912 PCI: 00:00.0 resource base 100000000 size 180400000 align 0 gran 0 limit 0 flags e0004200 index 10
1142 13:48:47.269916 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11
1143 13:48:47.279934 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12
1144 13:48:47.289758 PCI: 00:00.0 resource base f8000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 13
1145 13:48:47.289850 PCI: 00:02.0
1146 13:48:47.299407 PCI: 00:02.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1147 13:48:47.309592 PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
1148 13:48:47.319349 PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
1149 13:48:47.322686 PCI: 00:04.0 child on link 0 GENERIC: 0.0
1150 13:48:47.333313 PCI: 00:04.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 201 index 10
1151 13:48:47.335878 GENERIC: 0.0
1152 13:48:47.335959 PCI: 00:05.0
1153 13:48:47.345926 PCI: 00:05.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1154 13:48:47.352527 PCI: 00:07.0 child on link 0 GENERIC: 0.0
1155 13:48:47.352609 GENERIC: 0.0
1156 13:48:47.355857 PCI: 00:08.0
1157 13:48:47.365689 PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1158 13:48:47.365773 PCI: 00:0a.0
1159 13:48:47.372442 PCI: 00:0d.0 child on link 0 USB0 port 0
1160 13:48:47.382984 PCI: 00:0d.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1161 13:48:47.385493 USB0 port 0 child on link 0 USB3 port 0
1162 13:48:47.388993 USB3 port 0
1163 13:48:47.389075 USB3 port 1
1164 13:48:47.392211 USB3 port 2
1165 13:48:47.392293 USB3 port 3
1166 13:48:47.398630 PCI: 00:14.0 child on link 0 USB0 port 0
1167 13:48:47.408579 PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1168 13:48:47.411825 USB0 port 0 child on link 0 USB2 port 0
1169 13:48:47.411907 USB2 port 0
1170 13:48:47.415264 USB2 port 1
1171 13:48:47.415346 USB2 port 2
1172 13:48:47.418550 USB2 port 3
1173 13:48:47.422231 USB2 port 4
1174 13:48:47.422313 USB2 port 5
1175 13:48:47.425159 USB2 port 6
1176 13:48:47.425242 USB2 port 7
1177 13:48:47.428302 USB2 port 8
1178 13:48:47.428384 USB2 port 9
1179 13:48:47.431930 USB3 port 0
1180 13:48:47.432012 USB3 port 1
1181 13:48:47.435240 USB3 port 2
1182 13:48:47.435322 USB3 port 3
1183 13:48:47.438376 PCI: 00:14.2
1184 13:48:47.448175 PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1185 13:48:47.458087 PCI: 00:14.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
1186 13:48:47.461598 PCI: 00:14.3 child on link 0 GENERIC: 0.0
1187 13:48:47.471336 PCI: 00:14.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1188 13:48:47.475177 GENERIC: 0.0
1189 13:48:47.477991 PCI: 00:15.0 child on link 0 I2C: 00:1a
1190 13:48:47.487832 PCI: 00:15.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1191 13:48:47.491100 I2C: 00:1a
1192 13:48:47.491181 I2C: 00:31
1193 13:48:47.494736 I2C: 00:32
1194 13:48:47.497754 PCI: 00:15.1 child on link 0 I2C: 00:10
1195 13:48:47.508128 PCI: 00:15.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1196 13:48:47.508210 I2C: 00:10
1197 13:48:47.511294 PCI: 00:15.2
1198 13:48:47.520748 PCI: 00:15.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1199 13:48:47.520829 PCI: 00:15.3
1200 13:48:47.530812 PCI: 00:15.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1201 13:48:47.534567 PCI: 00:16.0
1202 13:48:47.543984 PCI: 00:16.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1203 13:48:47.544066 PCI: 00:19.0
1204 13:48:47.550852 PCI: 00:19.1 child on link 0 I2C: 00:15
1205 13:48:47.560614 PCI: 00:19.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1206 13:48:47.560695 I2C: 00:15
1207 13:48:47.564359 PCI: 00:1d.0 child on link 0 GENERIC: 0.0
1208 13:48:47.574020 PCI: 00:1d.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
1209 13:48:47.583699 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
1210 13:48:47.593980 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
1211 13:48:47.594066 GENERIC: 0.0
1212 13:48:47.597065 PCI: 01:00.0
1213 13:48:47.606930 PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1214 13:48:47.616960 PCI: 01:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 18
1215 13:48:47.626743 PCI: 01:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 1c
1216 13:48:47.626827 PCI: 00:1e.0
1217 13:48:47.637116 PCI: 00:1e.0 resource base fe03e000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1218 13:48:47.643355 PCI: 00:1e.2 child on link 0 SPI: 00
1219 13:48:47.653128 PCI: 00:1e.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1220 13:48:47.653212 SPI: 00
1221 13:48:47.656786 PCI: 00:1e.3 child on link 0 SPI: 00
1222 13:48:47.666532 PCI: 00:1e.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1223 13:48:47.669879 SPI: 00
1224 13:48:47.673104 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1225 13:48:47.683089 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1226 13:48:47.683170 PNP: 0c09.0
1227 13:48:47.693070 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1228 13:48:47.696127 PCI: 00:1f.2 child on link 0 GENERIC: 0.0
1229 13:48:47.705958 PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0
1230 13:48:47.716048 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1
1231 13:48:47.719311 GENERIC: 0.0 child on link 0 GENERIC: 0.0
1232 13:48:47.722434 GENERIC: 0.0
1233 13:48:47.722516 GENERIC: 1.0
1234 13:48:47.726139 PCI: 00:1f.3
1235 13:48:47.735857 PCI: 00:1f.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1236 13:48:47.745849 PCI: 00:1f.3 resource base 0 size 100000 align 20 gran 20 limit ffffffffffffffff flags 201 index 20
1237 13:48:47.745933 PCI: 00:1f.5
1238 13:48:47.755858 PCI: 00:1f.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
1239 13:48:47.758992 CPU_CLUSTER: 0 child on link 0 APIC: 00
1240 13:48:47.762055 APIC: 00
1241 13:48:47.762138 APIC: 01
1242 13:48:47.765292 APIC: 07
1243 13:48:47.765375 APIC: 02
1244 13:48:47.765461 APIC: 04
1245 13:48:47.768770 APIC: 06
1246 13:48:47.768868 APIC: 03
1247 13:48:47.771840 APIC: 05
1248 13:48:47.778828 ==== Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) ===
1249 13:48:47.785169 PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff
1250 13:48:47.788610 PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff done
1251 13:48:47.795152 PCI: 00:1d.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
1252 13:48:47.801627 PCI: 01:00.0 10 * [0x0 - 0x3fff] mem
1253 13:48:47.805057 PCI: 01:00.0 18 * [0x4000 - 0x4fff] mem
1254 13:48:47.808408 PCI: 01:00.0 1c * [0x5000 - 0x5fff] mem
1255 13:48:47.815103 PCI: 00:1d.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
1256 13:48:47.821756 PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
1257 13:48:47.831574 PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
1258 13:48:47.838204 === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
1259 13:48:47.844729 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
1260 13:48:47.851296 update_constraints: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
1261 13:48:47.858211 update_constraints: PNP: 0c09.0 00 base 00000800 limit 000009fe io (fixed)
1262 13:48:47.868036 update_constraints: PCI: 00:1f.2 01 base 00001800 limit 000018ff io (fixed)
1263 13:48:47.871206 DOMAIN: 0000: Resource ranges:
1264 13:48:47.875090 * Base: 1000, Size: 800, Tag: 100
1265 13:48:47.877787 * Base: 1900, Size: e700, Tag: 100
1266 13:48:47.884468 PCI: 00:02.0 20 * [0x1000 - 0x103f] limit: 103f io
1267 13:48:47.891379 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
1268 13:48:47.897906 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff
1269 13:48:47.904414 update_constraints: PCI: 00:00.0 00 base c0000000 limit cfffffff mem (fixed)
1270 13:48:47.910838 update_constraints: PCI: 00:00.0 01 base fedc0000 limit feddffff mem (fixed)
1271 13:48:47.921079 update_constraints: PCI: 00:00.0 02 base feda0000 limit feda0fff mem (fixed)
1272 13:48:47.927586 update_constraints: PCI: 00:00.0 03 base feda1000 limit feda1fff mem (fixed)
1273 13:48:47.934056 update_constraints: PCI: 00:00.0 04 base fb000000 limit fb000fff mem (fixed)
1274 13:48:47.944196 update_constraints: PCI: 00:00.0 05 base fed80000 limit fed83fff mem (fixed)
1275 13:48:47.950491 update_constraints: PCI: 00:00.0 06 base fed90000 limit fed90fff mem (fixed)
1276 13:48:47.957139 update_constraints: PCI: 00:00.0 07 base fed92000 limit fed92fff mem (fixed)
1277 13:48:47.967183 update_constraints: PCI: 00:00.0 08 base fed84000 limit fed84fff mem (fixed)
1278 13:48:47.973902 update_constraints: PCI: 00:00.0 09 base fed85000 limit fed85fff mem (fixed)
1279 13:48:47.980244 update_constraints: PCI: 00:00.0 0a base fed86000 limit fed86fff mem (fixed)
1280 13:48:47.990455 update_constraints: PCI: 00:00.0 0b base fed87000 limit fed87fff mem (fixed)
1281 13:48:47.997186 update_constraints: PCI: 00:00.0 0c base fed91000 limit fed91fff mem (fixed)
1282 13:48:48.003348 update_constraints: PCI: 00:00.0 0d base 00000000 limit 0009ffff mem (fixed)
1283 13:48:48.013532 update_constraints: PCI: 00:00.0 0e base 000c0000 limit 76ffffff mem (fixed)
1284 13:48:48.020111 update_constraints: PCI: 00:00.0 0f base 77000000 limit 7fbfffff mem (fixed)
1285 13:48:48.026793 update_constraints: PCI: 00:00.0 10 base 100000000 limit 2803fffff mem (fixed)
1286 13:48:48.037017 update_constraints: PCI: 00:00.0 11 base 000a0000 limit 000bffff mem (fixed)
1287 13:48:48.043196 update_constraints: PCI: 00:00.0 12 base 000c0000 limit 000fffff mem (fixed)
1288 13:48:48.049850 update_constraints: PCI: 00:00.0 13 base f8000000 limit f9ffffff mem (fixed)
1289 13:48:48.059764 update_constraints: PCI: 00:1e.0 10 base fe03e000 limit fe03efff mem (fixed)
1290 13:48:48.066749 update_constraints: PCI: 00:1f.2 00 base fe000000 limit fe00ffff mem (fixed)
1291 13:48:48.069646 DOMAIN: 0000: Resource ranges:
1292 13:48:48.072712 * Base: 7fc00000, Size: 40400000, Tag: 200
1293 13:48:48.079486 * Base: d0000000, Size: 28000000, Tag: 200
1294 13:48:48.082706 * Base: fa000000, Size: 1000000, Tag: 200
1295 13:48:48.085878 * Base: fb001000, Size: 2fff000, Tag: 200
1296 13:48:48.089526 * Base: fe010000, Size: 2e000, Tag: 200
1297 13:48:48.096001 * Base: fe03f000, Size: d41000, Tag: 200
1298 13:48:48.099046 * Base: fed88000, Size: 8000, Tag: 200
1299 13:48:48.102548 * Base: fed93000, Size: d000, Tag: 200
1300 13:48:48.105757 * Base: feda2000, Size: 1e000, Tag: 200
1301 13:48:48.112374 * Base: fede0000, Size: 1220000, Tag: 200
1302 13:48:48.115646 * Base: 280400000, Size: 7d7fc00000, Tag: 100200
1303 13:48:48.122808 PCI: 00:02.0 18 * [0x80000000 - 0x8fffffff] limit: 8fffffff prefmem
1304 13:48:48.128769 PCI: 00:02.0 10 * [0x90000000 - 0x90ffffff] limit: 90ffffff mem
1305 13:48:48.135557 PCI: 00:05.0 10 * [0x91000000 - 0x91ffffff] limit: 91ffffff mem
1306 13:48:48.142338 PCI: 00:1d.0 20 * [0x7fc00000 - 0x7fcfffff] limit: 7fcfffff mem
1307 13:48:48.148603 PCI: 00:1f.3 20 * [0x7fd00000 - 0x7fdfffff] limit: 7fdfffff mem
1308 13:48:48.155159 PCI: 00:04.0 10 * [0x7fe00000 - 0x7fe1ffff] limit: 7fe1ffff mem
1309 13:48:48.162266 PCI: 00:0d.0 10 * [0x7fe20000 - 0x7fe2ffff] limit: 7fe2ffff mem
1310 13:48:48.168517 PCI: 00:14.0 10 * [0x7fe30000 - 0x7fe3ffff] limit: 7fe3ffff mem
1311 13:48:48.175204 PCI: 00:14.2 10 * [0x7fe40000 - 0x7fe43fff] limit: 7fe43fff mem
1312 13:48:48.181722 PCI: 00:14.3 10 * [0x7fe44000 - 0x7fe47fff] limit: 7fe47fff mem
1313 13:48:48.188351 PCI: 00:1f.3 10 * [0x7fe48000 - 0x7fe4bfff] limit: 7fe4bfff mem
1314 13:48:48.195074 PCI: 00:08.0 10 * [0x7fe4c000 - 0x7fe4cfff] limit: 7fe4cfff mem
1315 13:48:48.201678 PCI: 00:14.2 18 * [0x7fe4d000 - 0x7fe4dfff] limit: 7fe4dfff mem
1316 13:48:48.208159 PCI: 00:15.0 10 * [0x7fe4e000 - 0x7fe4efff] limit: 7fe4efff mem
1317 13:48:48.215150 PCI: 00:15.1 10 * [0x7fe4f000 - 0x7fe4ffff] limit: 7fe4ffff mem
1318 13:48:48.221849 PCI: 00:15.2 10 * [0x7fe50000 - 0x7fe50fff] limit: 7fe50fff mem
1319 13:48:48.228111 PCI: 00:15.3 10 * [0x7fe51000 - 0x7fe51fff] limit: 7fe51fff mem
1320 13:48:48.234635 PCI: 00:16.0 10 * [0x7fe52000 - 0x7fe52fff] limit: 7fe52fff mem
1321 13:48:48.241715 PCI: 00:19.1 10 * [0x7fe53000 - 0x7fe53fff] limit: 7fe53fff mem
1322 13:48:48.247699 PCI: 00:1e.2 10 * [0x7fe54000 - 0x7fe54fff] limit: 7fe54fff mem
1323 13:48:48.254546 PCI: 00:1e.3 10 * [0x7fe55000 - 0x7fe55fff] limit: 7fe55fff mem
1324 13:48:48.261020 PCI: 00:1f.5 10 * [0x7fe56000 - 0x7fe56fff] limit: 7fe56fff mem
1325 13:48:48.270833 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff done
1326 13:48:48.277567 PCI: 00:1d.0 mem: base: 7fc00000 size: 100000 align: 20 gran: 20 limit: 7fcfffff
1327 13:48:48.280967 PCI: 00:1d.0: Resource ranges:
1328 13:48:48.284238 * Base: 7fc00000, Size: 100000, Tag: 200
1329 13:48:48.290972 PCI: 01:00.0 10 * [0x7fc00000 - 0x7fc03fff] limit: 7fc03fff mem
1330 13:48:48.297861 PCI: 01:00.0 18 * [0x7fc04000 - 0x7fc04fff] limit: 7fc04fff mem
1331 13:48:48.304194 PCI: 01:00.0 1c * [0x7fc05000 - 0x7fc05fff] limit: 7fc05fff mem
1332 13:48:48.314089 PCI: 00:1d.0 mem: base: 7fc00000 size: 100000 align: 20 gran: 20 limit: 7fcfffff done
1333 13:48:48.320582 === Resource allocator: DOMAIN: 0000 - resource allocation complete ===
1334 13:48:48.323835 Root Device assign_resources, bus 0 link: 0
1335 13:48:48.330791 DOMAIN: 0000 assign_resources, bus 0 link: 0
1336 13:48:48.336879 PCI: 00:02.0 10 <- [0x0090000000 - 0x0090ffffff] size 0x01000000 gran 0x18 mem64
1337 13:48:48.346953 PCI: 00:02.0 18 <- [0x0080000000 - 0x008fffffff] size 0x10000000 gran 0x1c prefmem64
1338 13:48:48.353463 PCI: 00:02.0 20 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io
1339 13:48:48.363466 PCI: 00:04.0 10 <- [0x007fe00000 - 0x007fe1ffff] size 0x00020000 gran 0x11 mem64
1340 13:48:48.366748 PCI: 00:04.0 assign_resources, bus 1 link: 0
1341 13:48:48.373568 PCI: 00:04.0 assign_resources, bus 1 link: 0
1342 13:48:48.380064 PCI: 00:05.0 10 <- [0x0091000000 - 0x0091ffffff] size 0x01000000 gran 0x18 mem64
1343 13:48:48.389877 PCI: 00:08.0 10 <- [0x007fe4c000 - 0x007fe4cfff] size 0x00001000 gran 0x0c mem64
1344 13:48:48.397232 PCI: 00:0d.0 10 <- [0x007fe20000 - 0x007fe2ffff] size 0x00010000 gran 0x10 mem64
1345 13:48:48.399489 PCI: 00:0d.0 assign_resources, bus 0 link: 0
1346 13:48:48.406554 PCI: 00:0d.0 assign_resources, bus 0 link: 0
1347 13:48:48.412930 PCI: 00:14.0 10 <- [0x007fe30000 - 0x007fe3ffff] size 0x00010000 gran 0x10 mem64
1348 13:48:48.420266 PCI: 00:14.0 assign_resources, bus 0 link: 0
1349 13:48:48.422801 PCI: 00:14.0 assign_resources, bus 0 link: 0
1350 13:48:48.432553 PCI: 00:14.2 10 <- [0x007fe40000 - 0x007fe43fff] size 0x00004000 gran 0x0e mem64
1351 13:48:48.439660 PCI: 00:14.2 18 <- [0x007fe4d000 - 0x007fe4dfff] size 0x00001000 gran 0x0c mem64
1352 13:48:48.449211 PCI: 00:14.3 10 <- [0x007fe44000 - 0x007fe47fff] size 0x00004000 gran 0x0e mem64
1353 13:48:48.452877 PCI: 00:14.3 assign_resources, bus 0 link: 0
1354 13:48:48.456108 PCI: 00:14.3 assign_resources, bus 0 link: 0
1355 13:48:48.465898 PCI: 00:15.0 10 <- [0x007fe4e000 - 0x007fe4efff] size 0x00001000 gran 0x0c mem64
1356 13:48:48.469113 PCI: 00:15.0 assign_resources, bus 0 link: 0
1357 13:48:48.476016 PCI: 00:15.0 assign_resources, bus 0 link: 0
1358 13:48:48.482294 PCI: 00:15.1 10 <- [0x007fe4f000 - 0x007fe4ffff] size 0x00001000 gran 0x0c mem64
1359 13:48:48.488773 PCI: 00:15.1 assign_resources, bus 0 link: 0
1360 13:48:48.492273 PCI: 00:15.1 assign_resources, bus 0 link: 0
1361 13:48:48.498854 PCI: 00:15.2 10 <- [0x007fe50000 - 0x007fe50fff] size 0x00001000 gran 0x0c mem64
1362 13:48:48.509060 PCI: 00:15.3 10 <- [0x007fe51000 - 0x007fe51fff] size 0x00001000 gran 0x0c mem64
1363 13:48:48.515224 PCI: 00:16.0 10 <- [0x007fe52000 - 0x007fe52fff] size 0x00001000 gran 0x0c mem64
1364 13:48:48.525273 PCI: 00:19.1 10 <- [0x007fe53000 - 0x007fe53fff] size 0x00001000 gran 0x0c mem64
1365 13:48:48.528720 PCI: 00:19.1 assign_resources, bus 0 link: 0
1366 13:48:48.535490 PCI: 00:19.1 assign_resources, bus 0 link: 0
1367 13:48:48.541869 PCI: 00:1d.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
1368 13:48:48.551631 PCI: 00:1d.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
1369 13:48:48.561949 PCI: 00:1d.0 20 <- [0x007fc00000 - 0x007fcfffff] size 0x00100000 gran 0x14 bus 01 mem
1370 13:48:48.564867 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1371 13:48:48.574813 PCI: 01:00.0 10 <- [0x007fc00000 - 0x007fc03fff] size 0x00004000 gran 0x0e mem64
1372 13:48:48.581296 PCI: 01:00.0 18 <- [0x007fc04000 - 0x007fc04fff] size 0x00001000 gran 0x0c mem
1373 13:48:48.591274 PCI: 01:00.0 1c <- [0x007fc05000 - 0x007fc05fff] size 0x00001000 gran 0x0c mem
1374 13:48:48.595096 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1375 13:48:48.604791 PCI: 00:1e.2 10 <- [0x007fe54000 - 0x007fe54fff] size 0x00001000 gran 0x0c mem64
1376 13:48:48.607949 PCI: 00:1e.2 assign_resources, bus 2 link: 0
1377 13:48:48.610806 PCI: 00:1e.2 assign_resources, bus 2 link: 0
1378 13:48:48.620784 PCI: 00:1e.3 10 <- [0x007fe55000 - 0x007fe55fff] size 0x00001000 gran 0x0c mem64
1379 13:48:48.624191 PCI: 00:1e.3 assign_resources, bus 3 link: 0
1380 13:48:48.630958 PCI: 00:1e.3 assign_resources, bus 3 link: 0
1381 13:48:48.634039 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1382 13:48:48.640694 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1383 13:48:48.643766 LPC: Trying to open IO window from 800 size 1ff
1384 13:48:48.653970 PCI: 00:1f.3 10 <- [0x007fe48000 - 0x007fe4bfff] size 0x00004000 gran 0x0e mem64
1385 13:48:48.660285 PCI: 00:1f.3 20 <- [0x007fd00000 - 0x007fdfffff] size 0x00100000 gran 0x14 mem64
1386 13:48:48.666945 PCI: 00:1f.5 10 <- [0x007fe56000 - 0x007fe56fff] size 0x00001000 gran 0x0c mem
1387 13:48:48.673704 DOMAIN: 0000 assign_resources, bus 0 link: 0
1388 13:48:48.677078 Root Device assign_resources, bus 0 link: 0
1389 13:48:48.680687 Done setting resources.
1390 13:48:48.687096 Show resources in subtree (Root Device)...After assigning values.
1391 13:48:48.690484 Root Device child on link 0 DOMAIN: 0000
1392 13:48:48.697154 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1393 13:48:48.703403 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1394 13:48:48.713547 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100
1395 13:48:48.716894 PCI: 00:00.0
1396 13:48:48.726717 PCI: 00:00.0 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1397 13:48:48.736493 PCI: 00:00.0 resource base fedc0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1
1398 13:48:48.746899 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1399 13:48:48.753143 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1400 13:48:48.763144 PCI: 00:00.0 resource base fb000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1401 13:48:48.773065 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1402 13:48:48.783122 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 6
1403 13:48:48.792952 PCI: 00:00.0 resource base fed92000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1404 13:48:48.799484 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1405 13:48:48.809972 PCI: 00:00.0 resource base fed85000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9
1406 13:48:48.819455 PCI: 00:00.0 resource base fed86000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
1407 13:48:48.829295 PCI: 00:00.0 resource base fed87000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b
1408 13:48:48.839483 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c
1409 13:48:48.845856 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index d
1410 13:48:48.856229 PCI: 00:00.0 resource base c0000 size 76f40000 align 0 gran 0 limit 0 flags e0004200 index e
1411 13:48:48.865720 PCI: 00:00.0 resource base 77000000 size 8c00000 align 0 gran 0 limit 0 flags f0000200 index f
1412 13:48:48.875665 PCI: 00:00.0 resource base 100000000 size 180400000 align 0 gran 0 limit 0 flags e0004200 index 10
1413 13:48:48.885526 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11
1414 13:48:48.895738 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12
1415 13:48:48.905549 PCI: 00:00.0 resource base f8000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 13
1416 13:48:48.905632 PCI: 00:02.0
1417 13:48:48.915596 PCI: 00:02.0 resource base 90000000 size 1000000 align 24 gran 24 limit 90ffffff flags 60000201 index 10
1418 13:48:48.928907 PCI: 00:02.0 resource base 80000000 size 10000000 align 28 gran 28 limit 8fffffff flags 60001201 index 18
1419 13:48:48.935246 PCI: 00:02.0 resource base 1000 size 40 align 6 gran 6 limit 103f flags 60000100 index 20
1420 13:48:48.942063 PCI: 00:04.0 child on link 0 GENERIC: 0.0
1421 13:48:48.951873 PCI: 00:04.0 resource base 7fe00000 size 20000 align 17 gran 17 limit 7fe1ffff flags 60000201 index 10
1422 13:48:48.955221 GENERIC: 0.0
1423 13:48:48.955302 PCI: 00:05.0
1424 13:48:48.965051 PCI: 00:05.0 resource base 91000000 size 1000000 align 24 gran 24 limit 91ffffff flags 60000201 index 10
1425 13:48:48.971988 PCI: 00:07.0 child on link 0 GENERIC: 0.0
1426 13:48:48.972070 GENERIC: 0.0
1427 13:48:48.974869 PCI: 00:08.0
1428 13:48:48.985016 PCI: 00:08.0 resource base 7fe4c000 size 1000 align 12 gran 12 limit 7fe4cfff flags 60000201 index 10
1429 13:48:48.985097 PCI: 00:0a.0
1430 13:48:48.991632 PCI: 00:0d.0 child on link 0 USB0 port 0
1431 13:48:49.001828 PCI: 00:0d.0 resource base 7fe20000 size 10000 align 16 gran 16 limit 7fe2ffff flags 60000201 index 10
1432 13:48:49.005432 USB0 port 0 child on link 0 USB3 port 0
1433 13:48:49.008227 USB3 port 0
1434 13:48:49.008308 USB3 port 1
1435 13:48:49.011503 USB3 port 2
1436 13:48:49.011584 USB3 port 3
1437 13:48:49.018010 PCI: 00:14.0 child on link 0 USB0 port 0
1438 13:48:49.028119 PCI: 00:14.0 resource base 7fe30000 size 10000 align 16 gran 16 limit 7fe3ffff flags 60000201 index 10
1439 13:48:49.031075 USB0 port 0 child on link 0 USB2 port 0
1440 13:48:49.034423 USB2 port 0
1441 13:48:49.034504 USB2 port 1
1442 13:48:49.038139 USB2 port 2
1443 13:48:49.038221 USB2 port 3
1444 13:48:49.041394 USB2 port 4
1445 13:48:49.041476 USB2 port 5
1446 13:48:49.044730 USB2 port 6
1447 13:48:49.044811 USB2 port 7
1448 13:48:49.047714 USB2 port 8
1449 13:48:49.047794 USB2 port 9
1450 13:48:49.051002 USB3 port 0
1451 13:48:49.051084 USB3 port 1
1452 13:48:49.054513 USB3 port 2
1453 13:48:49.057595 USB3 port 3
1454 13:48:49.057676 PCI: 00:14.2
1455 13:48:49.067597 PCI: 00:14.2 resource base 7fe40000 size 4000 align 14 gran 14 limit 7fe43fff flags 60000201 index 10
1456 13:48:49.077688 PCI: 00:14.2 resource base 7fe4d000 size 1000 align 12 gran 12 limit 7fe4dfff flags 60000201 index 18
1457 13:48:49.084273 PCI: 00:14.3 child on link 0 GENERIC: 0.0
1458 13:48:49.094073 PCI: 00:14.3 resource base 7fe44000 size 4000 align 14 gran 14 limit 7fe47fff flags 60000201 index 10
1459 13:48:49.094156 GENERIC: 0.0
1460 13:48:49.100489 PCI: 00:15.0 child on link 0 I2C: 00:1a
1461 13:48:49.110810 PCI: 00:15.0 resource base 7fe4e000 size 1000 align 12 gran 12 limit 7fe4efff flags 60000201 index 10
1462 13:48:49.110893 I2C: 00:1a
1463 13:48:49.114094 I2C: 00:31
1464 13:48:49.114174 I2C: 00:32
1465 13:48:49.117842 PCI: 00:15.1 child on link 0 I2C: 00:10
1466 13:48:49.130504 PCI: 00:15.1 resource base 7fe4f000 size 1000 align 12 gran 12 limit 7fe4ffff flags 60000201 index 10
1467 13:48:49.130586 I2C: 00:10
1468 13:48:49.133830 PCI: 00:15.2
1469 13:48:49.143534 PCI: 00:15.2 resource base 7fe50000 size 1000 align 12 gran 12 limit 7fe50fff flags 60000201 index 10
1470 13:48:49.143616 PCI: 00:15.3
1471 13:48:49.153496 PCI: 00:15.3 resource base 7fe51000 size 1000 align 12 gran 12 limit 7fe51fff flags 60000201 index 10
1472 13:48:49.156984 PCI: 00:16.0
1473 13:48:49.167041 PCI: 00:16.0 resource base 7fe52000 size 1000 align 12 gran 12 limit 7fe52fff flags 60000201 index 10
1474 13:48:49.167123 PCI: 00:19.0
1475 13:48:49.173728 PCI: 00:19.1 child on link 0 I2C: 00:15
1476 13:48:49.183693 PCI: 00:19.1 resource base 7fe53000 size 1000 align 12 gran 12 limit 7fe53fff flags 60000201 index 10
1477 13:48:49.183775 I2C: 00:15
1478 13:48:49.189992 PCI: 00:1d.0 child on link 0 GENERIC: 0.0
1479 13:48:49.196696 PCI: 00:1d.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 20080102 index 1c
1480 13:48:49.210210 PCI: 00:1d.0 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24
1481 13:48:49.219967 PCI: 00:1d.0 resource base 7fc00000 size 100000 align 20 gran 20 limit 7fcfffff flags 60080202 index 20
1482 13:48:49.223170 GENERIC: 0.0
1483 13:48:49.223254 PCI: 01:00.0
1484 13:48:49.232914 PCI: 01:00.0 resource base 7fc00000 size 4000 align 14 gran 14 limit 7fc03fff flags 60000201 index 10
1485 13:48:49.246192 PCI: 01:00.0 resource base 7fc04000 size 1000 align 12 gran 12 limit 7fc04fff flags 60000200 index 18
1486 13:48:49.256383 PCI: 01:00.0 resource base 7fc05000 size 1000 align 12 gran 12 limit 7fc05fff flags 60000200 index 1c
1487 13:48:49.256468 PCI: 00:1e.0
1488 13:48:49.269287 PCI: 00:1e.0 resource base fe03e000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1489 13:48:49.272687 PCI: 00:1e.2 child on link 0 SPI: 00
1490 13:48:49.282855 PCI: 00:1e.2 resource base 7fe54000 size 1000 align 12 gran 12 limit 7fe54fff flags 60000201 index 10
1491 13:48:49.282939 SPI: 00
1492 13:48:49.289216 PCI: 00:1e.3 child on link 0 SPI: 00
1493 13:48:49.299013 PCI: 00:1e.3 resource base 7fe55000 size 1000 align 12 gran 12 limit 7fe55fff flags 60000201 index 10
1494 13:48:49.299097 SPI: 00
1495 13:48:49.302654 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1496 13:48:49.312304 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1497 13:48:49.315892 PNP: 0c09.0
1498 13:48:49.322390 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1499 13:48:49.328740 PCI: 00:1f.2 child on link 0 GENERIC: 0.0
1500 13:48:49.335413 PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0
1501 13:48:49.345282 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1
1502 13:48:49.352043 GENERIC: 0.0 child on link 0 GENERIC: 0.0
1503 13:48:49.352126 GENERIC: 0.0
1504 13:48:49.355178 GENERIC: 1.0
1505 13:48:49.355260 PCI: 00:1f.3
1506 13:48:49.365270 PCI: 00:1f.3 resource base 7fe48000 size 4000 align 14 gran 14 limit 7fe4bfff flags 60000201 index 10
1507 13:48:49.378466 PCI: 00:1f.3 resource base 7fd00000 size 100000 align 20 gran 20 limit 7fdfffff flags 60000201 index 20
1508 13:48:49.378551 PCI: 00:1f.5
1509 13:48:49.388281 PCI: 00:1f.5 resource base 7fe56000 size 1000 align 12 gran 12 limit 7fe56fff flags 60000200 index 10
1510 13:48:49.391703 CPU_CLUSTER: 0 child on link 0 APIC: 00
1511 13:48:49.394767 APIC: 00
1512 13:48:49.394848 APIC: 01
1513 13:48:49.398185 APIC: 07
1514 13:48:49.398266 APIC: 02
1515 13:48:49.398330 APIC: 04
1516 13:48:49.401366 APIC: 06
1517 13:48:49.401447 APIC: 03
1518 13:48:49.405358 APIC: 05
1519 13:48:49.405439 Done allocating resources.
1520 13:48:49.411231 BS: BS_DEV_RESOURCES run times (exec / console): 28 / 2514 ms
1521 13:48:49.417904 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
1522 13:48:49.421315 Configure GPIOs for I2S audio on UP4.
1523 13:48:49.428252 BS: BS_DEV_ENABLE entry times (exec / console): 2 / 9 ms
1524 13:48:49.431430 Enabling resources...
1525 13:48:49.434727 PCI: 00:00.0 subsystem <- 8086/9a12
1526 13:48:49.438066 PCI: 00:00.0 cmd <- 06
1527 13:48:49.441682 PCI: 00:02.0 subsystem <- 8086/9a40
1528 13:48:49.444853 PCI: 00:02.0 cmd <- 03
1529 13:48:49.448279 PCI: 00:04.0 subsystem <- 8086/9a03
1530 13:48:49.451249 PCI: 00:04.0 cmd <- 02
1531 13:48:49.454498 PCI: 00:05.0 subsystem <- 8086/9a19
1532 13:48:49.457918 PCI: 00:05.0 cmd <- 02
1533 13:48:49.460943 PCI: 00:08.0 subsystem <- 8086/9a11
1534 13:48:49.461024 PCI: 00:08.0 cmd <- 06
1535 13:48:49.467442 PCI: 00:0d.0 subsystem <- 8086/9a13
1536 13:48:49.467523 PCI: 00:0d.0 cmd <- 02
1537 13:48:49.473925 PCI: 00:14.0 subsystem <- 8086/a0ed
1538 13:48:49.474005 PCI: 00:14.0 cmd <- 02
1539 13:48:49.477459 PCI: 00:14.2 subsystem <- 8086/a0ef
1540 13:48:49.481232 PCI: 00:14.2 cmd <- 02
1541 13:48:49.483878 PCI: 00:14.3 subsystem <- 8086/a0f0
1542 13:48:49.487086 PCI: 00:14.3 cmd <- 02
1543 13:48:49.490895 PCI: 00:15.0 subsystem <- 8086/a0e8
1544 13:48:49.493897 PCI: 00:15.0 cmd <- 02
1545 13:48:49.497152 PCI: 00:15.1 subsystem <- 8086/a0e9
1546 13:48:49.500143 PCI: 00:15.1 cmd <- 02
1547 13:48:49.503532 PCI: 00:15.2 subsystem <- 8086/a0ea
1548 13:48:49.507441 PCI: 00:15.2 cmd <- 02
1549 13:48:49.510196 PCI: 00:15.3 subsystem <- 8086/a0eb
1550 13:48:49.513529 PCI: 00:15.3 cmd <- 02
1551 13:48:49.516510 PCI: 00:16.0 subsystem <- 8086/a0e0
1552 13:48:49.516589 PCI: 00:16.0 cmd <- 02
1553 13:48:49.523498 PCI: 00:19.1 subsystem <- 8086/a0c6
1554 13:48:49.523578 PCI: 00:19.1 cmd <- 02
1555 13:48:49.526700 PCI: 00:1d.0 bridge ctrl <- 0013
1556 13:48:49.530057 PCI: 00:1d.0 subsystem <- 8086/a0b0
1557 13:48:49.533428 PCI: 00:1d.0 cmd <- 06
1558 13:48:49.536685 PCI: 00:1e.0 subsystem <- 8086/a0a8
1559 13:48:49.539869 PCI: 00:1e.0 cmd <- 06
1560 13:48:49.543509 PCI: 00:1e.2 subsystem <- 8086/a0aa
1561 13:48:49.546468 PCI: 00:1e.2 cmd <- 06
1562 13:48:49.550045 PCI: 00:1e.3 subsystem <- 8086/a0ab
1563 13:48:49.553117 PCI: 00:1e.3 cmd <- 02
1564 13:48:49.556834 PCI: 00:1f.0 subsystem <- 8086/a087
1565 13:48:49.559654 PCI: 00:1f.0 cmd <- 407
1566 13:48:49.562931 PCI: 00:1f.3 subsystem <- 8086/a0c8
1567 13:48:49.566306 PCI: 00:1f.3 cmd <- 02
1568 13:48:49.569986 PCI: 00:1f.5 subsystem <- 8086/a0a4
1569 13:48:49.572974 PCI: 00:1f.5 cmd <- 406
1570 13:48:49.576288 PCI: 01:00.0 cmd <- 02
1571 13:48:49.580223 done.
1572 13:48:49.583640 BS: BS_DEV_ENABLE run times (exec / console): 10 / 140 ms
1573 13:48:49.586800 Initializing devices...
1574 13:48:49.590363 Root Device init
1575 13:48:49.593697 Chrome EC: Set SMI mask to 0x0000000000000000
1576 13:48:49.600060 Chrome EC: clear events_b mask to 0x0000000000000000
1577 13:48:49.606396 Chrome EC: Set S5 LAZY WAKE mask to 0x0000000000000006
1578 13:48:49.612907 Chrome EC: Set S3 LAZY WAKE mask to 0x000000001800101e
1579 13:48:49.616115 Chrome EC: Set S0iX LAZY WAKE mask to 0x000000001800101e
1580 13:48:49.622957 Chrome EC: Set WAKE mask to 0x0000000000000000
1581 13:48:49.626089 fw_config match found: DB_USB=USB3_ACTIVE
1582 13:48:49.632658 Configure Right Type-C port orientation for retimer
1583 13:48:49.636162 Root Device init finished in 42 msecs
1584 13:48:49.639254 PCI: 00:00.0 init
1585 13:48:49.642458 CPU TDP = 9 Watts
1586 13:48:49.642563 CPU PL1 = 9 Watts
1587 13:48:49.645903 CPU PL2 = 40 Watts
1588 13:48:49.645983 CPU PL4 = 83 Watts
1589 13:48:49.652784 PCI: 00:00.0 init finished in 8 msecs
1590 13:48:49.652883 PCI: 00:02.0 init
1591 13:48:49.655788 GMA: Found VBT in CBFS
1592 13:48:49.659415 GMA: Found valid VBT in CBFS
1593 13:48:49.665649 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
1594 13:48:49.672256 x_res x y_res: 1920 x 1080, size: 8294400 at 0x80000000
1595 13:48:49.675476 PCI: 00:02.0 init finished in 18 msecs
1596 13:48:49.678792 PCI: 00:05.0 init
1597 13:48:49.681838 PCI: 00:05.0 init finished in 0 msecs
1598 13:48:49.685528 PCI: 00:08.0 init
1599 13:48:49.688641 PCI: 00:08.0 init finished in 0 msecs
1600 13:48:49.691878 PCI: 00:14.0 init
1601 13:48:49.695426 PCI: 00:14.0 init finished in 0 msecs
1602 13:48:49.698545 PCI: 00:14.2 init
1603 13:48:49.701888 PCI: 00:14.2 init finished in 0 msecs
1604 13:48:49.701968 PCI: 00:15.0 init
1605 13:48:49.704877 I2C bus 0 version 0x3230302a
1606 13:48:49.711552 DW I2C bus 0 at 0x7fe4e000 (400 KHz)
1607 13:48:49.714972 PCI: 00:15.0 init finished in 6 msecs
1608 13:48:49.715052 PCI: 00:15.1 init
1609 13:48:49.718094 I2C bus 1 version 0x3230302a
1610 13:48:49.721540 DW I2C bus 1 at 0x7fe4f000 (400 KHz)
1611 13:48:49.725142 PCI: 00:15.1 init finished in 6 msecs
1612 13:48:49.728326 PCI: 00:15.2 init
1613 13:48:49.731599 I2C bus 2 version 0x3230302a
1614 13:48:49.735082 DW I2C bus 2 at 0x7fe50000 (400 KHz)
1615 13:48:49.738304 PCI: 00:15.2 init finished in 6 msecs
1616 13:48:49.741613 PCI: 00:15.3 init
1617 13:48:49.745136 I2C bus 3 version 0x3230302a
1618 13:48:49.748525 DW I2C bus 3 at 0x7fe51000 (400 KHz)
1619 13:48:49.751556 PCI: 00:15.3 init finished in 6 msecs
1620 13:48:49.755174 PCI: 00:16.0 init
1621 13:48:49.758213 PCI: 00:16.0 init finished in 0 msecs
1622 13:48:49.761754 PCI: 00:19.1 init
1623 13:48:49.764595 I2C bus 5 version 0x3230302a
1624 13:48:49.768100 DW I2C bus 5 at 0x7fe53000 (400 KHz)
1625 13:48:49.771221 PCI: 00:19.1 init finished in 6 msecs
1626 13:48:49.771301 PCI: 00:1d.0 init
1627 13:48:49.774523 Initializing PCH PCIe bridge.
1628 13:48:49.781131 PCI: 00:1d.0 init finished in 3 msecs
1629 13:48:49.784570 PCI: 00:1f.0 init
1630 13:48:49.787930 IOAPIC: Initializing IOAPIC at 0xfec00000
1631 13:48:49.791443 IOAPIC: Bootstrap Processor Local APIC = 0x00
1632 13:48:49.794187 IOAPIC: ID = 0x02
1633 13:48:49.797754 IOAPIC: Dumping registers
1634 13:48:49.797834 reg 0x0000: 0x02000000
1635 13:48:49.800705 reg 0x0001: 0x00770020
1636 13:48:49.804057 reg 0x0002: 0x00000000
1637 13:48:49.807306 PCI: 00:1f.0 init finished in 21 msecs
1638 13:48:49.810936 PCI: 00:1f.2 init
1639 13:48:49.814096 Disabling ACPI via APMC.
1640 13:48:49.817588 APMC done.
1641 13:48:49.820777 PCI: 00:1f.2 init finished in 6 msecs
1642 13:48:49.832096 PCI: 01:00.0 init
1643 13:48:49.835574 PCI: 01:00.0 init finished in 0 msecs
1644 13:48:49.838727 PNP: 0c09.0 init
1645 13:48:49.845553 Google Chrome EC uptime: 8.409 seconds
1646 13:48:49.848751 Google Chrome AP resets since EC boot: 1
1647 13:48:49.851934 Google Chrome most recent AP reset causes:
1648 13:48:49.855550 0.350: 32775 shutdown: entering G3
1649 13:48:49.861980 Google Chrome EC reset flags at last EC boot: reset-pin | sysjump
1650 13:48:49.865290 PNP: 0c09.0 init finished in 23 msecs
1651 13:48:49.871810 Devices initialized
1652 13:48:49.875087 Show all devs... After init.
1653 13:48:49.878452 Root Device: enabled 1
1654 13:48:49.878531 DOMAIN: 0000: enabled 1
1655 13:48:49.881463 CPU_CLUSTER: 0: enabled 1
1656 13:48:49.884870 PCI: 00:00.0: enabled 1
1657 13:48:49.888373 PCI: 00:02.0: enabled 1
1658 13:48:49.888471 PCI: 00:04.0: enabled 1
1659 13:48:49.891637 PCI: 00:05.0: enabled 1
1660 13:48:49.894966 PCI: 00:06.0: enabled 0
1661 13:48:49.898255 PCI: 00:07.0: enabled 0
1662 13:48:49.898334 PCI: 00:07.1: enabled 0
1663 13:48:49.902237 PCI: 00:07.2: enabled 0
1664 13:48:49.904872 PCI: 00:07.3: enabled 0
1665 13:48:49.908078 PCI: 00:08.0: enabled 1
1666 13:48:49.908157 PCI: 00:09.0: enabled 0
1667 13:48:49.911537 PCI: 00:0a.0: enabled 0
1668 13:48:49.915069 PCI: 00:0d.0: enabled 1
1669 13:48:49.918129 PCI: 00:0d.1: enabled 0
1670 13:48:49.918208 PCI: 00:0d.2: enabled 0
1671 13:48:49.921763 PCI: 00:0d.3: enabled 0
1672 13:48:49.924734 PCI: 00:0e.0: enabled 0
1673 13:48:49.924813 PCI: 00:10.2: enabled 1
1674 13:48:49.928375 PCI: 00:10.6: enabled 0
1675 13:48:49.931694 PCI: 00:10.7: enabled 0
1676 13:48:49.934862 PCI: 00:12.0: enabled 0
1677 13:48:49.934942 PCI: 00:12.6: enabled 0
1678 13:48:49.938089 PCI: 00:13.0: enabled 0
1679 13:48:49.941409 PCI: 00:14.0: enabled 1
1680 13:48:49.944751 PCI: 00:14.1: enabled 0
1681 13:48:49.944830 PCI: 00:14.2: enabled 1
1682 13:48:49.947938 PCI: 00:14.3: enabled 1
1683 13:48:49.951348 PCI: 00:15.0: enabled 1
1684 13:48:49.954581 PCI: 00:15.1: enabled 1
1685 13:48:49.954698 PCI: 00:15.2: enabled 1
1686 13:48:49.958099 PCI: 00:15.3: enabled 1
1687 13:48:49.961207 PCI: 00:16.0: enabled 1
1688 13:48:49.964352 PCI: 00:16.1: enabled 0
1689 13:48:49.964431 PCI: 00:16.2: enabled 0
1690 13:48:49.967844 PCI: 00:16.3: enabled 0
1691 13:48:49.970917 PCI: 00:16.4: enabled 0
1692 13:48:49.970996 PCI: 00:16.5: enabled 0
1693 13:48:49.974304 PCI: 00:17.0: enabled 0
1694 13:48:49.977659 PCI: 00:19.0: enabled 0
1695 13:48:49.980866 PCI: 00:19.1: enabled 1
1696 13:48:49.980945 PCI: 00:19.2: enabled 0
1697 13:48:49.984155 PCI: 00:1c.0: enabled 1
1698 13:48:49.987464 PCI: 00:1c.1: enabled 0
1699 13:48:49.991131 PCI: 00:1c.2: enabled 0
1700 13:48:49.991240 PCI: 00:1c.3: enabled 0
1701 13:48:49.994493 PCI: 00:1c.4: enabled 0
1702 13:48:49.997441 PCI: 00:1c.5: enabled 0
1703 13:48:50.001503 PCI: 00:1c.6: enabled 1
1704 13:48:50.001582 PCI: 00:1c.7: enabled 0
1705 13:48:50.004049 PCI: 00:1d.0: enabled 1
1706 13:48:50.007382 PCI: 00:1d.1: enabled 0
1707 13:48:50.010693 PCI: 00:1d.2: enabled 1
1708 13:48:50.010773 PCI: 00:1d.3: enabled 0
1709 13:48:50.013958 PCI: 00:1e.0: enabled 1
1710 13:48:50.017612 PCI: 00:1e.1: enabled 0
1711 13:48:50.021088 PCI: 00:1e.2: enabled 1
1712 13:48:50.021168 PCI: 00:1e.3: enabled 1
1713 13:48:50.024050 PCI: 00:1f.0: enabled 1
1714 13:48:50.027243 PCI: 00:1f.1: enabled 0
1715 13:48:50.027323 PCI: 00:1f.2: enabled 1
1716 13:48:50.030473 PCI: 00:1f.3: enabled 1
1717 13:48:50.034247 PCI: 00:1f.4: enabled 0
1718 13:48:50.037444 PCI: 00:1f.5: enabled 1
1719 13:48:50.037523 PCI: 00:1f.6: enabled 0
1720 13:48:50.040574 PCI: 00:1f.7: enabled 0
1721 13:48:50.044018 APIC: 00: enabled 1
1722 13:48:50.044098 GENERIC: 0.0: enabled 1
1723 13:48:50.047469 GENERIC: 0.0: enabled 1
1724 13:48:50.050393 GENERIC: 1.0: enabled 1
1725 13:48:50.053700 GENERIC: 0.0: enabled 1
1726 13:48:50.053832 GENERIC: 1.0: enabled 1
1727 13:48:50.056873 USB0 port 0: enabled 1
1728 13:48:50.060161 GENERIC: 0.0: enabled 1
1729 13:48:50.063625 USB0 port 0: enabled 1
1730 13:48:50.063704 GENERIC: 0.0: enabled 1
1731 13:48:50.066913 I2C: 00:1a: enabled 1
1732 13:48:50.070435 I2C: 00:31: enabled 1
1733 13:48:50.070516 I2C: 00:32: enabled 1
1734 13:48:50.073626 I2C: 00:10: enabled 1
1735 13:48:50.076945 I2C: 00:15: enabled 1
1736 13:48:50.077024 GENERIC: 0.0: enabled 0
1737 13:48:50.080187 GENERIC: 1.0: enabled 0
1738 13:48:50.083691 GENERIC: 0.0: enabled 1
1739 13:48:50.087222 SPI: 00: enabled 1
1740 13:48:50.087301 SPI: 00: enabled 1
1741 13:48:50.090076 PNP: 0c09.0: enabled 1
1742 13:48:50.093724 GENERIC: 0.0: enabled 1
1743 13:48:50.093808 USB3 port 0: enabled 1
1744 13:48:50.096774 USB3 port 1: enabled 1
1745 13:48:50.100383 USB3 port 2: enabled 0
1746 13:48:50.100465 USB3 port 3: enabled 0
1747 13:48:50.103360 USB2 port 0: enabled 0
1748 13:48:50.106571 USB2 port 1: enabled 1
1749 13:48:50.109939 USB2 port 2: enabled 1
1750 13:48:50.110022 USB2 port 3: enabled 0
1751 13:48:50.113339 USB2 port 4: enabled 1
1752 13:48:50.117058 USB2 port 5: enabled 0
1753 13:48:50.117141 USB2 port 6: enabled 0
1754 13:48:50.120009 USB2 port 7: enabled 0
1755 13:48:50.123309 USB2 port 8: enabled 0
1756 13:48:50.126489 USB2 port 9: enabled 0
1757 13:48:50.126572 USB3 port 0: enabled 0
1758 13:48:50.129757 USB3 port 1: enabled 1
1759 13:48:50.133406 USB3 port 2: enabled 0
1760 13:48:50.133489 USB3 port 3: enabled 0
1761 13:48:50.136626 GENERIC: 0.0: enabled 1
1762 13:48:50.140098 GENERIC: 1.0: enabled 1
1763 13:48:50.140181 APIC: 01: enabled 1
1764 13:48:50.143152 APIC: 07: enabled 1
1765 13:48:50.146378 APIC: 02: enabled 1
1766 13:48:50.146463 APIC: 04: enabled 1
1767 13:48:50.149866 APIC: 06: enabled 1
1768 13:48:50.153090 APIC: 03: enabled 1
1769 13:48:50.153176 APIC: 05: enabled 1
1770 13:48:50.156258 PCI: 01:00.0: enabled 1
1771 13:48:50.163073 BS: BS_DEV_INIT run times (exec / console): 31 / 540 ms
1772 13:48:50.166128 FMAP: area RW_ELOG found @ f30000 (4096 bytes)
1773 13:48:50.169663 ELOG: NV offset 0xf30000 size 0x1000
1774 13:48:50.176796 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
1775 13:48:50.183369 ELOG: Event(17) added with size 13 at 2023-08-16 13:48:50 UTC
1776 13:48:50.189868 ELOG: Event(92) added with size 9 at 2023-08-16 13:48:50 UTC
1777 13:48:50.196678 ELOG: Event(93) added with size 9 at 2023-08-16 13:48:50 UTC
1778 13:48:50.203079 ELOG: Event(9E) added with size 10 at 2023-08-16 13:48:50 UTC
1779 13:48:50.209810 ELOG: Event(9F) added with size 14 at 2023-08-16 13:48:50 UTC
1780 13:48:50.216245 BS: BS_DEV_INIT exit times (exec / console): 3 / 45 ms
1781 13:48:50.222740 ELOG: Event(A1) added with size 10 at 2023-08-16 13:48:50 UTC
1782 13:48:50.226238 elog_add_boot_reason: Logged recovery mode boot, reason: 0x1b
1783 13:48:50.232614 BS: BS_POST_DEVICE entry times (exec / console): 0 / 12 ms
1784 13:48:50.235874 Finalize devices...
1785 13:48:50.235956 Devices finalized
1786 13:48:50.242455 BS: BS_POST_DEVICE run times (exec / console): 0 / 4 ms
1787 13:48:50.249303 FMAP: area RW_NVRAM found @ f37000 (24576 bytes)
1788 13:48:50.252741 BS: BS_POST_DEVICE exit times (exec / console): 0 / 5 ms
1789 13:48:50.258990 ME: HFSTS1 : 0x80030055
1790 13:48:50.262226 ME: HFSTS2 : 0x30280116
1791 13:48:50.269194 ME: HFSTS3 : 0x00000050
1792 13:48:50.272129 ME: HFSTS4 : 0x00004000
1793 13:48:50.275643 ME: HFSTS5 : 0x00000000
1794 13:48:50.282431 ME: HFSTS6 : 0x00400006
1795 13:48:50.285500 ME: Manufacturing Mode : YES
1796 13:48:50.288989 ME: SPI Protection Mode Enabled : NO
1797 13:48:50.292478 ME: FW Partition Table : OK
1798 13:48:50.295783 ME: Bringup Loader Failure : NO
1799 13:48:50.298801 ME: Firmware Init Complete : NO
1800 13:48:50.302268 ME: Boot Options Present : NO
1801 13:48:50.308803 ME: Update In Progress : NO
1802 13:48:50.312084 ME: D0i3 Support : YES
1803 13:48:50.315442 ME: Low Power State Enabled : NO
1804 13:48:50.318674 ME: CPU Replaced : YES
1805 13:48:50.321890 ME: CPU Replacement Valid : YES
1806 13:48:50.325321 ME: Current Working State : 5
1807 13:48:50.328808 ME: Current Operation State : 1
1808 13:48:50.331929 ME: Current Operation Mode : 3
1809 13:48:50.335196 ME: Error Code : 0
1810 13:48:50.341885 ME: Enhanced Debug Mode : NO
1811 13:48:50.345263 ME: CPU Debug Disabled : YES
1812 13:48:50.348432 ME: TXT Support : NO
1813 13:48:50.355162 BS: BS_OS_RESUME_CHECK exit times (exec / console): 0 / 94 ms
1814 13:48:50.361838 CBFS: Found 'fallback/dsdt.aml' @0x72f80 size 0x5a67 in mcache @0x76c4c1c4
1815 13:48:50.365052 CBFS: 'fallback/slic' not found.
1816 13:48:50.368179 ACPI: Writing ACPI tables at 76b01000.
1817 13:48:50.371897 ACPI: * FACS
1818 13:48:50.371977 ACPI: * DSDT
1819 13:48:50.374792 Ramoops buffer: 0x100000@0x76a00000.
1820 13:48:50.381349 FMAP: area RO_VPD found @ 1800000 (16384 bytes)
1821 13:48:50.385140 FMAP: area RW_VPD found @ f35000 (8192 bytes)
1822 13:48:50.388524 Google Chrome EC: version:
1823 13:48:50.391379 ro: voema_v2.0.7540-147f8d37d1
1824 13:48:50.394707 rw: voema_v2.0.7540-147f8d37d1
1825 13:48:50.397978 running image: 2
1826 13:48:50.404569 PCI space above 4GB MMIO is at 0x280400000, len = 0x7d7fc00000
1827 13:48:50.407970 ACPI: * FADT
1828 13:48:50.408050 SCI is IRQ9
1829 13:48:50.411420 ACPI: added table 1/32, length now 40
1830 13:48:50.414856 ACPI: * SSDT
1831 13:48:50.417956 Found 1 CPU(s) with 8 core(s) each.
1832 13:48:50.421428 \_SB.PCI0.PMC: Intel Tigerlake at PCI: 00:1f.2
1833 13:48:50.427737 \_SB.DPTF: Intel DPTF at GENERIC: 0.0
1834 13:48:50.431005 \_SB.PCI0.CNVW: WIFI Device GENERIC: 0.0
1835 13:48:50.434685 \_SB.PCI0.I2C0.RT58: Headset Codec at I2C: 00:1a
1836 13:48:50.441183 \_SB.PCI0.I2C0.MAXR: Maxim MAX98373 Codec address 031h
1837 13:48:50.447571 \_SB.PCI0.I2C0.MAXL: Maxim MAX98373 Codec address 032h
1838 13:48:50.450897 \_SB.PCI0.I2C1.H010: ELAN Touchscreen at I2C: 00:10
1839 13:48:50.457275 \_SB.PCI0.I2C5.D015: ELAN Touchpad at I2C: 00:15
1840 13:48:50.463920 \_SB.PCI0.RP09: Enable RTD3 for PCI: 00:1d.0 (Intel PCIe Runtime D3)
1841 13:48:50.467354 \_SB.PCI0.RP09: Added StorageD3Enable property
1842 13:48:50.470531 \_SB.PCI0.SPI0.S001: SPI Device at SPI: 00
1843 13:48:50.477573 \_SB.PCI0.SPI1.CRFP: SPI Device at SPI: 00
1844 13:48:50.483814 PS2K: Physmap: [ EA E7 91 92 93 94 95 A0 AE B0 ]
1845 13:48:50.487029 PS2K: Passing 80 keymaps to kernel
1846 13:48:50.493854 \_SB.PCI0.TXHC.RHUB.SS01: USB3 Type-C Port C0 (MLB) at USB3 port 0
1847 13:48:50.500234 \_SB.PCI0.TXHC.RHUB.SS02: USB3 Type-C Port C1 (DB) at USB3 port 1
1848 13:48:50.506835 \_SB.PCI0.XHCI.RHUB.HS02: USB2 Type-A Port A1 (DB) at USB2 port 1
1849 13:48:50.513613 \_SB.PCI0.XHCI.RHUB.HS03: USB2 Type-C Port C1 (DB) at USB2 port 2
1850 13:48:50.520442 \_SB.PCI0.XHCI.RHUB.HS05: USB2 Type-C Port C0 (MLB) at USB2 port 4
1851 13:48:50.526795 \_SB.PCI0.XHCI.RHUB.SS02: USB3 Type-A Port A1 (DB) at USB3 port 1
1852 13:48:50.533941 \_SB.PCI0.PMC.MUX.CON0: Intel PMC MUX CONN Driver at GENERIC: 0.0
1853 13:48:50.540689 \_SB.PCI0.PMC.MUX.CON1: Intel PMC MUX CONN Driver at GENERIC: 1.0
1854 13:48:50.543328 ACPI: added table 2/32, length now 44
1855 13:48:50.543409 ACPI: * MCFG
1856 13:48:50.547081 ACPI: added table 3/32, length now 48
1857 13:48:50.550125 ACPI: * TPM2
1858 13:48:50.553540 TPM2 log created at 0x769f0000
1859 13:48:50.556640 ACPI: added table 4/32, length now 52
1860 13:48:50.556720 ACPI: * MADT
1861 13:48:50.560352 SCI is IRQ9
1862 13:48:50.563273 ACPI: added table 5/32, length now 56
1863 13:48:50.566586 current = 76b09850
1864 13:48:50.566703 ACPI: * DMAR
1865 13:48:50.570164 ACPI: added table 6/32, length now 60
1866 13:48:50.573322 ACPI: added table 7/32, length now 64
1867 13:48:50.576704 ACPI: * HPET
1868 13:48:50.579950 ACPI: added table 8/32, length now 68
1869 13:48:50.580030 ACPI: done.
1870 13:48:50.583303 ACPI tables: 35216 bytes.
1871 13:48:50.586246 smbios_write_tables: 769ef000
1872 13:48:50.589730 EC returned error result code 3
1873 13:48:50.592839 Couldn't obtain OEM name from CBI
1874 13:48:50.596415 Create SMBIOS type 16
1875 13:48:50.599716 Create SMBIOS type 17
1876 13:48:50.603193 GENERIC: 0.0 (WIFI Device)
1877 13:48:50.606373 SMBIOS tables: 1750 bytes.
1878 13:48:50.609923 Writing table forward entry at 0x00000500
1879 13:48:50.616449 Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 392c
1880 13:48:50.619529 Writing coreboot table at 0x76b25000
1881 13:48:50.626460 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1882 13:48:50.629483 1. 0000000000001000-000000000009ffff: RAM
1883 13:48:50.633223 2. 00000000000a0000-00000000000fffff: RESERVED
1884 13:48:50.639501 3. 0000000000100000-00000000769eefff: RAM
1885 13:48:50.642614 4. 00000000769ef000-0000000076b97fff: CONFIGURATION TABLES
1886 13:48:50.649646 5. 0000000076b98000-0000000076c09fff: RAMSTAGE
1887 13:48:50.655961 6. 0000000076c0a000-0000000076ffffff: CONFIGURATION TABLES
1888 13:48:50.659426 7. 0000000077000000-000000007fbfffff: RESERVED
1889 13:48:50.666532 8. 00000000c0000000-00000000cfffffff: RESERVED
1890 13:48:50.669504 9. 00000000f8000000-00000000f9ffffff: RESERVED
1891 13:48:50.673110 10. 00000000fb000000-00000000fb000fff: RESERVED
1892 13:48:50.679442 11. 00000000fe000000-00000000fe00ffff: RESERVED
1893 13:48:50.682584 12. 00000000fed80000-00000000fed87fff: RESERVED
1894 13:48:50.689211 13. 00000000fed90000-00000000fed92fff: RESERVED
1895 13:48:50.692695 14. 00000000feda0000-00000000feda1fff: RESERVED
1896 13:48:50.699220 15. 00000000fedc0000-00000000feddffff: RESERVED
1897 13:48:50.703107 16. 0000000100000000-00000002803fffff: RAM
1898 13:48:50.705848 Passing 4 GPIOs to payload:
1899 13:48:50.709498 NAME | PORT | POLARITY | VALUE
1900 13:48:50.715656 lid | undefined | high | high
1901 13:48:50.722086 power | undefined | high | low
1902 13:48:50.725512 oprom | undefined | high | low
1903 13:48:50.732370 EC in RW | 0x000000e5 | high | high
1904 13:48:50.738796 Wrote coreboot table at: 0x76b25000, 0x610 bytes, checksum cda7
1905 13:48:50.742398 coreboot table: 1576 bytes.
1906 13:48:50.745302 IMD ROOT 0. 0x76fff000 0x00001000
1907 13:48:50.748746 IMD SMALL 1. 0x76ffe000 0x00001000
1908 13:48:50.752161 FSP MEMORY 2. 0x76c4e000 0x003b0000
1909 13:48:50.755567 VPD 3. 0x76c4d000 0x00000367
1910 13:48:50.758940 RO MCACHE 4. 0x76c4c000 0x00000fdc
1911 13:48:50.761842 CONSOLE 5. 0x76c2c000 0x00020000
1912 13:48:50.765475 FMAP 6. 0x76c2b000 0x00000578
1913 13:48:50.771640 TIME STAMP 7. 0x76c2a000 0x00000910
1914 13:48:50.774903 VBOOT WORK 8. 0x76c16000 0x00014000
1915 13:48:50.778587 ROMSTG STCK 9. 0x76c15000 0x00001000
1916 13:48:50.781742 AFTER CAR 10. 0x76c0a000 0x0000b000
1917 13:48:50.785212 RAMSTAGE 11. 0x76b97000 0x00073000
1918 13:48:50.788254 REFCODE 12. 0x76b42000 0x00055000
1919 13:48:50.792138 SMM BACKUP 13. 0x76b32000 0x00010000
1920 13:48:50.794793 4f444749 14. 0x76b30000 0x00002000
1921 13:48:50.801707 EXT VBT15. 0x76b2d000 0x0000219f
1922 13:48:50.804909 COREBOOT 16. 0x76b25000 0x00008000
1923 13:48:50.808291 ACPI 17. 0x76b01000 0x00024000
1924 13:48:50.811371 ACPI GNVS 18. 0x76b00000 0x00001000
1925 13:48:50.814597 RAMOOPS 19. 0x76a00000 0x00100000
1926 13:48:50.817884 TPM2 TCGLOG20. 0x769f0000 0x00010000
1927 13:48:50.821326 SMBIOS 21. 0x769ef000 0x00000800
1928 13:48:50.824757 IMD small region:
1929 13:48:50.827952 IMD ROOT 0. 0x76ffec00 0x00000400
1930 13:48:50.831584 FSP RUNTIME 1. 0x76ffebe0 0x00000004
1931 13:48:50.834482 POWER STATE 2. 0x76ffeb80 0x00000044
1932 13:48:50.841078 ROMSTAGE 3. 0x76ffeb60 0x00000004
1933 13:48:50.844758 MEM INFO 4. 0x76ffe980 0x000001e0
1934 13:48:50.851138 BS: BS_WRITE_TABLES run times (exec / console): 6 / 484 ms
1935 13:48:50.851225 MTRR: Physical address space:
1936 13:48:50.857632 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
1937 13:48:50.864542 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
1938 13:48:50.870978 0x00000000000c0000 - 0x0000000077000000 size 0x76f40000 type 6
1939 13:48:50.877508 0x0000000077000000 - 0x0000000080000000 size 0x09000000 type 0
1940 13:48:50.884302 0x0000000080000000 - 0x0000000090000000 size 0x10000000 type 1
1941 13:48:50.891056 0x0000000090000000 - 0x0000000100000000 size 0x70000000 type 0
1942 13:48:50.897588 0x0000000100000000 - 0x0000000280400000 size 0x180400000 type 6
1943 13:48:50.900817 MTRR: Fixed MSR 0x250 0x0606060606060606
1944 13:48:50.904155 MTRR: Fixed MSR 0x258 0x0606060606060606
1945 13:48:50.907473 MTRR: Fixed MSR 0x259 0x0000000000000000
1946 13:48:50.914413 MTRR: Fixed MSR 0x268 0x0606060606060606
1947 13:48:50.917435 MTRR: Fixed MSR 0x269 0x0606060606060606
1948 13:48:50.920745 MTRR: Fixed MSR 0x26a 0x0606060606060606
1949 13:48:50.924208 MTRR: Fixed MSR 0x26b 0x0606060606060606
1950 13:48:50.930514 MTRR: Fixed MSR 0x26c 0x0606060606060606
1951 13:48:50.933773 MTRR: Fixed MSR 0x26d 0x0606060606060606
1952 13:48:50.937525 MTRR: Fixed MSR 0x26e 0x0606060606060606
1953 13:48:50.940518 MTRR: Fixed MSR 0x26f 0x0606060606060606
1954 13:48:50.944249 call enable_fixed_mtrr()
1955 13:48:50.947600 CPU physical address size: 39 bits
1956 13:48:50.954465 MTRR: default type WB/UC MTRR counts: 6/6.
1957 13:48:50.957453 MTRR: UC selected as default type.
1958 13:48:50.964171 MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
1959 13:48:50.967466 MTRR: 1 base 0x0000000077000000 mask 0x0000007fff000000 type 0
1960 13:48:50.974245 MTRR: 2 base 0x0000000078000000 mask 0x0000007ff8000000 type 0
1961 13:48:50.981052 MTRR: 3 base 0x0000000080000000 mask 0x0000007ff0000000 type 1
1962 13:48:50.987437 MTRR: 4 base 0x0000000100000000 mask 0x0000007f00000000 type 6
1963 13:48:50.994043 MTRR: 5 base 0x0000000200000000 mask 0x0000007f00000000 type 6
1964 13:48:50.997110
1965 13:48:50.997251 MTRR check
1966 13:48:51.000264 Fixed MTRRs : Enabled
1967 13:48:51.000344 Variable MTRRs: Enabled
1968 13:48:51.000407
1969 13:48:51.007009 MTRR: Fixed MSR 0x250 0x0606060606060606
1970 13:48:51.010396 MTRR: Fixed MSR 0x258 0x0606060606060606
1971 13:48:51.013374 MTRR: Fixed MSR 0x259 0x0000000000000000
1972 13:48:51.016840 MTRR: Fixed MSR 0x268 0x0606060606060606
1973 13:48:51.023541 MTRR: Fixed MSR 0x269 0x0606060606060606
1974 13:48:51.026732 MTRR: Fixed MSR 0x26a 0x0606060606060606
1975 13:48:51.030281 MTRR: Fixed MSR 0x26b 0x0606060606060606
1976 13:48:51.033272 MTRR: Fixed MSR 0x26c 0x0606060606060606
1977 13:48:51.040125 MTRR: Fixed MSR 0x26d 0x0606060606060606
1978 13:48:51.043088 MTRR: Fixed MSR 0x26e 0x0606060606060606
1979 13:48:51.046483 MTRR: Fixed MSR 0x26f 0x0606060606060606
1980 13:48:51.053006 BS: BS_WRITE_TABLES exit times (exec / console): 2 / 150 ms
1981 13:48:51.056298 call enable_fixed_mtrr()
1982 13:48:51.060162 Checking cr50 for pending updates
1983 13:48:51.063947 CPU physical address size: 39 bits
1984 13:48:51.067331 MTRR: Fixed MSR 0x250 0x0606060606060606
1985 13:48:51.070442 MTRR: Fixed MSR 0x250 0x0606060606060606
1986 13:48:51.077003 MTRR: Fixed MSR 0x258 0x0606060606060606
1987 13:48:51.080241 MTRR: Fixed MSR 0x259 0x0000000000000000
1988 13:48:51.083456 MTRR: Fixed MSR 0x268 0x0606060606060606
1989 13:48:51.087109 MTRR: Fixed MSR 0x269 0x0606060606060606
1990 13:48:51.093619 MTRR: Fixed MSR 0x26a 0x0606060606060606
1991 13:48:51.096952 MTRR: Fixed MSR 0x26b 0x0606060606060606
1992 13:48:51.100478 MTRR: Fixed MSR 0x26c 0x0606060606060606
1993 13:48:51.103780 MTRR: Fixed MSR 0x26d 0x0606060606060606
1994 13:48:51.106604 MTRR: Fixed MSR 0x26e 0x0606060606060606
1995 13:48:51.113178 MTRR: Fixed MSR 0x26f 0x0606060606060606
1996 13:48:51.116842 MTRR: Fixed MSR 0x258 0x0606060606060606
1997 13:48:51.120304 call enable_fixed_mtrr()
1998 13:48:51.124050 MTRR: Fixed MSR 0x259 0x0000000000000000
1999 13:48:51.126568 MTRR: Fixed MSR 0x268 0x0606060606060606
2000 13:48:51.133385 MTRR: Fixed MSR 0x269 0x0606060606060606
2001 13:48:51.136782 MTRR: Fixed MSR 0x26a 0x0606060606060606
2002 13:48:51.140204 MTRR: Fixed MSR 0x26b 0x0606060606060606
2003 13:48:51.143382 MTRR: Fixed MSR 0x26c 0x0606060606060606
2004 13:48:51.150176 MTRR: Fixed MSR 0x26d 0x0606060606060606
2005 13:48:51.153241 MTRR: Fixed MSR 0x26e 0x0606060606060606
2006 13:48:51.156335 MTRR: Fixed MSR 0x26f 0x0606060606060606
2007 13:48:51.160085 CPU physical address size: 39 bits
2008 13:48:51.166510 call enable_fixed_mtrr()
2009 13:48:51.169814 MTRR: Fixed MSR 0x250 0x0606060606060606
2010 13:48:51.173358 MTRR: Fixed MSR 0x250 0x0606060606060606
2011 13:48:51.176545 MTRR: Fixed MSR 0x258 0x0606060606060606
2012 13:48:51.183181 MTRR: Fixed MSR 0x259 0x0000000000000000
2013 13:48:51.186261 MTRR: Fixed MSR 0x268 0x0606060606060606
2014 13:48:51.189630 MTRR: Fixed MSR 0x269 0x0606060606060606
2015 13:48:51.193031 MTRR: Fixed MSR 0x26a 0x0606060606060606
2016 13:48:51.196346 MTRR: Fixed MSR 0x26b 0x0606060606060606
2017 13:48:51.203073 MTRR: Fixed MSR 0x26c 0x0606060606060606
2018 13:48:51.206503 MTRR: Fixed MSR 0x26d 0x0606060606060606
2019 13:48:51.210208 MTRR: Fixed MSR 0x26e 0x0606060606060606
2020 13:48:51.212849 MTRR: Fixed MSR 0x26f 0x0606060606060606
2021 13:48:51.220517 MTRR: Fixed MSR 0x258 0x0606060606060606
2022 13:48:51.220597 call enable_fixed_mtrr()
2023 13:48:51.227248 MTRR: Fixed MSR 0x259 0x0000000000000000
2024 13:48:51.230337 MTRR: Fixed MSR 0x268 0x0606060606060606
2025 13:48:51.234055 MTRR: Fixed MSR 0x269 0x0606060606060606
2026 13:48:51.237139 MTRR: Fixed MSR 0x26a 0x0606060606060606
2027 13:48:51.243675 MTRR: Fixed MSR 0x26b 0x0606060606060606
2028 13:48:51.247064 MTRR: Fixed MSR 0x26c 0x0606060606060606
2029 13:48:51.250404 MTRR: Fixed MSR 0x26d 0x0606060606060606
2030 13:48:51.253623 MTRR: Fixed MSR 0x26e 0x0606060606060606
2031 13:48:51.260294 MTRR: Fixed MSR 0x26f 0x0606060606060606
2032 13:48:51.264121 CPU physical address size: 39 bits
2033 13:48:51.266805 call enable_fixed_mtrr()
2034 13:48:51.270002 MTRR: Fixed MSR 0x250 0x0606060606060606
2035 13:48:51.276551 MTRR: Fixed MSR 0x250 0x0606060606060606
2036 13:48:51.280468 MTRR: Fixed MSR 0x258 0x0606060606060606
2037 13:48:51.283301 MTRR: Fixed MSR 0x259 0x0000000000000000
2038 13:48:51.286732 MTRR: Fixed MSR 0x268 0x0606060606060606
2039 13:48:51.290510 MTRR: Fixed MSR 0x269 0x0606060606060606
2040 13:48:51.296288 MTRR: Fixed MSR 0x26a 0x0606060606060606
2041 13:48:51.299779 MTRR: Fixed MSR 0x26b 0x0606060606060606
2042 13:48:51.303364 MTRR: Fixed MSR 0x26c 0x0606060606060606
2043 13:48:51.306374 MTRR: Fixed MSR 0x26d 0x0606060606060606
2044 13:48:51.313028 MTRR: Fixed MSR 0x26e 0x0606060606060606
2045 13:48:51.316310 MTRR: Fixed MSR 0x26f 0x0606060606060606
2046 13:48:51.322951 MTRR: Fixed MSR 0x258 0x0606060606060606
2047 13:48:51.323031 call enable_fixed_mtrr()
2048 13:48:51.329435 MTRR: Fixed MSR 0x259 0x0000000000000000
2049 13:48:51.333062 MTRR: Fixed MSR 0x268 0x0606060606060606
2050 13:48:51.336162 MTRR: Fixed MSR 0x269 0x0606060606060606
2051 13:48:51.339391 MTRR: Fixed MSR 0x26a 0x0606060606060606
2052 13:48:51.342656 MTRR: Fixed MSR 0x26b 0x0606060606060606
2053 13:48:51.349291 MTRR: Fixed MSR 0x26c 0x0606060606060606
2054 13:48:51.352820 MTRR: Fixed MSR 0x26d 0x0606060606060606
2055 13:48:51.356209 MTRR: Fixed MSR 0x26e 0x0606060606060606
2056 13:48:51.359232 MTRR: Fixed MSR 0x26f 0x0606060606060606
2057 13:48:51.365593 CPU physical address size: 39 bits
2058 13:48:51.368920 call enable_fixed_mtrr()
2059 13:48:51.372186 CPU physical address size: 39 bits
2060 13:48:51.375629 CPU physical address size: 39 bits
2061 13:48:51.378917 CPU physical address size: 39 bits
2062 13:48:51.382366 Reading cr50 TPM mode
2063 13:48:51.392242 BS: BS_PAYLOAD_LOAD entry times (exec / console): 326 / 6 ms
2064 13:48:51.401374 CBFS: Found 'fallback/payload' @0x38db00 size 0x4be9c in mcache @0x76c4cf60
2065 13:48:51.404873 Checking segment from ROM address 0xffc02b38
2066 13:48:51.408017 Checking segment from ROM address 0xffc02b54
2067 13:48:51.414754 Loading segment from ROM address 0xffc02b38
2068 13:48:51.414835 code (compression=0)
2069 13:48:51.424564 New segment dstaddr 0x30000000 memsize 0x2662db0 srcaddr 0xffc02b70 filesize 0x4be64
2070 13:48:51.434278 Loading Segment: addr: 0x30000000 memsz: 0x0000000002662db0 filesz: 0x000000000004be64
2071 13:48:51.434359 it's not compressed!
2072 13:48:51.574339 [ 0x30000000, 3004be64, 0x32662db0) <- ffc02b70
2073 13:48:51.581485 Clearing Segment: addr: 0x000000003004be64 memsz: 0x0000000002616f4c
2074 13:48:51.587325 Loading segment from ROM address 0xffc02b54
2075 13:48:51.590526 Entry Point 0x30000000
2076 13:48:51.590627 Loaded segments
2077 13:48:51.597075 BS: BS_PAYLOAD_LOAD run times (exec / console): 135 / 63 ms
2078 13:48:51.640560 Finalizing chipset.
2079 13:48:51.643655 Finalizing SMM.
2080 13:48:51.643735 APMC done.
2081 13:48:51.650551 BS: BS_PAYLOAD_LOAD exit times (exec / console): 42 / 5 ms
2082 13:48:51.653662 mp_park_aps done after 0 msecs.
2083 13:48:51.656914 Jumping to boot code at 0x30000000(0x76b25000)
2084 13:48:51.666828 CPU0: stack: 0x76bee000 - 0x76bef000, lowest used address 0x76beea78, stack used: 1416 bytes
2085 13:48:51.666910
2086 13:48:51.666972
2087 13:48:51.670308
2088 13:48:51.670387 Starting depthcharge on Voema...
2089 13:48:51.670764 end: 2.2.3 depthcharge-start (duration 00:00:10) [common]
2090 13:48:51.670861 start: 2.2.4 bootloader-commands (timeout 00:04:45) [common]
2091 13:48:51.670941 Setting prompt string to ['volteer:']
2092 13:48:51.671018 bootloader-commands: Wait for prompt ['volteer:'] (timeout 00:04:45)
2093 13:48:51.673858
2094 13:48:51.680533 WARNING: can't convert coreboot GPIOs, 'lid' won't be resampled at runtime!
2095 13:48:51.680613
2096 13:48:51.686840 WARNING: can't convert coreboot GPIOs, 'power' won't be resampled at runtime!
2097 13:48:51.686921
2098 13:48:51.693385 Looking for NVMe Controller 0x3005f220 @ 00:1d:00
2099 13:48:51.693465
2100 13:48:51.696706 Failed to find eMMC card reader
2101 13:48:51.696818
2102 13:48:51.696885 Wipe memory regions:
2103 13:48:51.699841
2104 13:48:51.703431 [0x00000000001000, 0x000000000a0000)
2105 13:48:51.703512
2106 13:48:51.706355 [0x00000000100000, 0x00000030000000)
2107 13:48:51.731757
2108 13:48:51.735397 [0x00000032662db0, 0x000000769ef000)
2109 13:48:51.770292
2110 13:48:51.773404 [0x00000100000000, 0x00000280400000)
2111 13:48:51.973392
2112 13:48:51.976595 ec_init: CrosEC protocol v3 supported (256, 256)
2113 13:48:51.976697
2114 13:48:51.983623 update_port_state: port C0 state: usb enable 1 mux conn 0
2115 13:48:51.983704
2116 13:48:51.989842 update_port_state: port C0 req: usage 0 usb3 1 usb2 9 ufp 1 ori_hsl 0 ori_sbu 0 dbg_acc 1
2117 13:48:51.993117
2118 13:48:51.996451 pmc_check_ipc_sts: STS_BUSY done after 1611 us
2119 13:48:51.996532
2120 13:48:52.002958 send_conn_disc_msg: pmc_send_cmd succeeded
2121 13:48:52.433899
2122 13:48:52.434043 R8152: Initializing
2123 13:48:52.434113
2124 13:48:52.437151 Version 6 (ocp_data = 5c30)
2125 13:48:52.437234
2126 13:48:52.440182 R8152: Done initializing
2127 13:48:52.440266
2128 13:48:52.443568 Adding net device
2129 13:48:52.744975
2130 13:48:52.748468 [firmware-volteer-13672.B-collabora] Oct 22 2021 06:32:35
2131 13:48:52.748555
2132 13:48:52.748619
2133 13:48:52.748678
2134 13:48:52.751745 Setting prompt string to ['volteer:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2136 13:48:52.852114 volteer: tftpboot 192.168.201.1 11299541/tftp-deploy-iowl9d7g/kernel/bzImage 11299541/tftp-deploy-iowl9d7g/kernel/cmdline 11299541/tftp-deploy-iowl9d7g/ramdisk/ramdisk.cpio.gz
2137 13:48:52.852256 Setting prompt string to ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2138 13:48:52.852399 bootloader-commands: Wait for prompt ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:43)
2139 13:48:52.856718 tftpboot 192.168.201.1 11299541/tftp-deploy-iowl9d7g/kernel/bzIploy-iowl9d7g/kernel/cmdline 11299541/tftp-deploy-iowl9d7g/ramdisk/ramdisk.cpio.gz
2140 13:48:52.856804
2141 13:48:52.856867 Waiting for link
2142 13:48:53.059404
2143 13:48:53.059546 done.
2144 13:48:53.059612
2145 13:48:53.059671 MAC: 00:24:32:30:79:42
2146 13:48:53.059727
2147 13:48:53.062577 Sending DHCP discover... done.
2148 13:48:53.062709
2149 13:48:53.066197 Waiting for reply... done.
2150 13:48:53.066278
2151 13:48:53.070574 Sending DHCP request... done.
2152 13:48:53.070727
2153 13:48:53.075694 Waiting for reply... done.
2154 13:48:53.075776
2155 13:48:53.075840 My ip is 192.168.201.13
2156 13:48:53.075900
2157 13:48:53.082713 The DHCP server ip is 192.168.201.1
2158 13:48:53.082799
2159 13:48:53.085635 TFTP server IP predefined by user: 192.168.201.1
2160 13:48:53.085717
2161 13:48:53.092005 Bootfile predefined by user: 11299541/tftp-deploy-iowl9d7g/kernel/bzImage
2162 13:48:53.092088
2163 13:48:53.095548 Sending tftp read request... done.
2164 13:48:53.095652
2165 13:48:53.102209 Waiting for the transfer...
2166 13:48:53.102295
2167 13:48:53.668856 00000000 ################################################################
2168 13:48:53.668998
2169 13:48:54.245359 00080000 ################################################################
2170 13:48:54.245509
2171 13:48:54.921459 00100000 ################################################################
2172 13:48:54.921941
2173 13:48:55.648993 00180000 ################################################################
2174 13:48:55.649524
2175 13:48:56.378401 00200000 ################################################################
2176 13:48:56.378963
2177 13:48:57.096506 00280000 ################################################################
2178 13:48:57.097045
2179 13:48:57.830565 00300000 ################################################################
2180 13:48:57.831169
2181 13:48:58.539151 00380000 ################################################################
2182 13:48:58.539678
2183 13:48:59.242861 00400000 ################################################################
2184 13:48:59.243381
2185 13:48:59.963798 00480000 ################################################################
2186 13:48:59.964319
2187 13:49:00.675577 00500000 ################################################################
2188 13:49:00.676360
2189 13:49:01.386908 00580000 ################################################################
2190 13:49:01.387421
2191 13:49:02.094349 00600000 ################################################################
2192 13:49:02.094915
2193 13:49:02.813089 00680000 ################################################################
2194 13:49:02.813673
2195 13:49:03.538001 00700000 ################################################################
2196 13:49:03.538571
2197 13:49:04.267635 00780000 ################################################################
2198 13:49:04.268167
2199 13:49:04.419733 00800000 ############## done.
2200 13:49:04.420313
2201 13:49:04.422901 The bootfile was 8499088 bytes long.
2202 13:49:04.423662
2203 13:49:04.426073 Sending tftp read request... done.
2204 13:49:04.426649
2205 13:49:04.429222 Waiting for the transfer...
2206 13:49:04.429798
2207 13:49:05.013695 00000000 ################################################################
2208 13:49:05.013842
2209 13:49:05.599836 00080000 ################################################################
2210 13:49:05.599970
2211 13:49:06.186472 00100000 ################################################################
2212 13:49:06.186654
2213 13:49:06.780147 00180000 ################################################################
2214 13:49:06.780284
2215 13:49:07.325383 00200000 ################################################################
2216 13:49:07.325522
2217 13:49:07.881274 00280000 ################################################################
2218 13:49:07.881510
2219 13:49:08.546398 00300000 ################################################################
2220 13:49:08.546925
2221 13:49:09.130379 00380000 ################################################################
2222 13:49:09.130541
2223 13:49:09.691967 00400000 ################################################################
2224 13:49:09.692108
2225 13:49:10.246420 00480000 ################################################################
2226 13:49:10.246576
2227 13:49:10.789189 00500000 ################################################################
2228 13:49:10.789326
2229 13:49:11.368503 00580000 ################################################################
2230 13:49:11.368997
2231 13:49:12.037124 00600000 ################################################################
2232 13:49:12.037642
2233 13:49:12.607951 00680000 ################################################################
2234 13:49:12.608099
2235 13:49:13.153897 00700000 ################################################################
2236 13:49:13.154043
2237 13:49:13.677106 00780000 ################################################################
2238 13:49:13.677276
2239 13:49:14.120880 00800000 ####################################################### done.
2240 13:49:14.121050
2241 13:49:14.124476 Sending tftp read request... done.
2242 13:49:14.124582
2243 13:49:14.127851 Waiting for the transfer...
2244 13:49:14.127933
2245 13:49:14.127998 00000000 # done.
2246 13:49:14.128061
2247 13:49:14.137501 Command line loaded dynamically from TFTP file: 11299541/tftp-deploy-iowl9d7g/kernel/cmdline
2248 13:49:14.137583
2249 13:49:14.153973 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
2250 13:49:14.157663
2251 13:49:14.160531 Shutting down all USB controllers.
2252 13:49:14.160611
2253 13:49:14.160675 Removing current net device
2254 13:49:14.160734
2255 13:49:14.164064 Finalizing coreboot
2256 13:49:14.164145
2257 13:49:14.170355 Exiting depthcharge with code 4 at timestamp: 31140932
2258 13:49:14.170437
2259 13:49:14.170501
2260 13:49:14.170560 Starting kernel ...
2261 13:49:14.170663
2262 13:49:14.170721
2263 13:49:14.171084 end: 2.2.4 bootloader-commands (duration 00:00:23) [common]
2264 13:49:14.171176 start: 2.2.5 auto-login-action (timeout 00:04:22) [common]
2265 13:49:14.171250 Setting prompt string to ['Linux version [0-9]']
2266 13:49:14.171315 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2267 13:49:14.171380 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
2269 13:53:36.172153 end: 2.2.5 auto-login-action (duration 00:04:22) [common]
2271 13:53:36.173240 depthcharge-retry failed: 1 of 1 attempts. 'auto-login-action timed out after 262 seconds'
2273 13:53:36.174156 end: 2.2 depthcharge-retry (duration 00:05:00) [common]
2276 13:53:36.175737 end: 2 depthcharge-action (duration 00:05:00) [common]
2278 13:53:36.177169 Cleaning after the job
2279 13:53:36.177261 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11299541/tftp-deploy-iowl9d7g/ramdisk
2280 13:53:36.178704 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11299541/tftp-deploy-iowl9d7g/kernel
2281 13:53:36.179975 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11299541/tftp-deploy-iowl9d7g/modules
2282 13:53:36.180318 start: 5.1 power-off (timeout 00:00:30) [common]
2283 13:53:36.180475 Calling: 'pduclient' '--daemon=localhost' '--hostname=asus-cx9400-volteer-cbg-8' '--port=1' '--command=off'
2284 13:53:36.259373 >> Command sent successfully.
2285 13:53:36.264850 Returned 0 in 0 seconds
2286 13:53:36.365850 end: 5.1 power-off (duration 00:00:00) [common]
2288 13:53:36.367486 start: 5.2 read-feedback (timeout 00:10:00) [common]
2289 13:53:36.368816 Listened to connection for namespace 'common' for up to 1s
2290 13:53:37.369703 Finalising connection for namespace 'common'
2291 13:53:37.370393 Disconnecting from shell: Finalise
2292 13:53:37.370870
2293 13:53:37.472131 end: 5.2 read-feedback (duration 00:00:01) [common]
2294 13:53:37.472967 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11299541
2295 13:53:37.492808 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11299541
2296 13:53:37.492950 JobError: Your job cannot terminate cleanly.