Boot log: acer-cbv514-1h-34uz-brya
- Warnings: 0
- Kernel Warnings: 0
- Kernel Errors: 0
- Errors: 2
- Boot result: FAIL
1 17:45:30.928026 lava-dispatcher, installed at version: 2023.08
2 17:45:30.928227 start: 0 validate
3 17:45:30.928366 Start time: 2023-10-09 17:45:30.928359+00:00 (UTC)
4 17:45:30.928522 Using caching service: 'http://localhost/cache/?uri=%s'
5 17:45:30.928657 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230623.0%2Fx86%2Frootfs.cpio.gz exists
6 17:45:31.199977 Using caching service: 'http://localhost/cache/?uri=%s'
7 17:45:31.200676 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-4.4.y-st%2Fv4.4-st20-1778-g3b01feff09495%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fkernel%2FbzImage exists
8 17:45:31.472537 Using caching service: 'http://localhost/cache/?uri=%s'
9 17:45:31.473279 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-4.4.y-st%2Fv4.4-st20-1778-g3b01feff09495%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
10 17:45:34.791405 validate duration: 3.86
12 17:45:34.791690 start: 1 tftp-deploy (timeout 00:10:00) [common]
13 17:45:34.791801 start: 1.1 download-retry (timeout 00:10:00) [common]
14 17:45:34.791897 start: 1.1.1 http-download (timeout 00:10:00) [common]
15 17:45:34.792022 Not decompressing ramdisk as can be used compressed.
16 17:45:34.792108 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230623.0/x86/rootfs.cpio.gz
17 17:45:34.792172 saving as /var/lib/lava/dispatcher/tmp/11712549/tftp-deploy-mtnn8qlx/ramdisk/rootfs.cpio.gz
18 17:45:34.792237 total size: 8418130 (8 MB)
19 17:45:35.301790 progress 0 % (0 MB)
20 17:45:35.314023 progress 5 % (0 MB)
21 17:45:35.325610 progress 10 % (0 MB)
22 17:45:35.336641 progress 15 % (1 MB)
23 17:45:35.343711 progress 20 % (1 MB)
24 17:45:35.349014 progress 25 % (2 MB)
25 17:45:35.353375 progress 30 % (2 MB)
26 17:45:35.356932 progress 35 % (2 MB)
27 17:45:35.360461 progress 40 % (3 MB)
28 17:45:35.363619 progress 45 % (3 MB)
29 17:45:35.366575 progress 50 % (4 MB)
30 17:45:35.369361 progress 55 % (4 MB)
31 17:45:35.371929 progress 60 % (4 MB)
32 17:45:35.374216 progress 65 % (5 MB)
33 17:45:35.376554 progress 70 % (5 MB)
34 17:45:35.378886 progress 75 % (6 MB)
35 17:45:35.381105 progress 80 % (6 MB)
36 17:45:35.383338 progress 85 % (6 MB)
37 17:45:35.385525 progress 90 % (7 MB)
38 17:45:35.387750 progress 95 % (7 MB)
39 17:45:35.389818 progress 100 % (8 MB)
40 17:45:35.390048 8 MB downloaded in 0.60 s (13.43 MB/s)
41 17:45:35.390203 end: 1.1.1 http-download (duration 00:00:01) [common]
43 17:45:35.390439 end: 1.1 download-retry (duration 00:00:01) [common]
44 17:45:35.390527 start: 1.2 download-retry (timeout 00:09:59) [common]
45 17:45:35.390645 start: 1.2.1 http-download (timeout 00:09:59) [common]
46 17:45:35.390810 downloading http://storage.kernelci.org/cip/linux-4.4.y-st/v4.4-st20-1778-g3b01feff09495/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/kernel/bzImage
47 17:45:35.390886 saving as /var/lib/lava/dispatcher/tmp/11712549/tftp-deploy-mtnn8qlx/kernel/bzImage
48 17:45:35.390949 total size: 8490896 (8 MB)
49 17:45:35.391010 No compression specified
50 17:45:35.392336 progress 0 % (0 MB)
51 17:45:35.394443 progress 5 % (0 MB)
52 17:45:35.396714 progress 10 % (0 MB)
53 17:45:35.398987 progress 15 % (1 MB)
54 17:45:35.401209 progress 20 % (1 MB)
55 17:45:35.403478 progress 25 % (2 MB)
56 17:45:35.405786 progress 30 % (2 MB)
57 17:45:35.408112 progress 35 % (2 MB)
58 17:45:35.410362 progress 40 % (3 MB)
59 17:45:35.412663 progress 45 % (3 MB)
60 17:45:35.415047 progress 50 % (4 MB)
61 17:45:35.417246 progress 55 % (4 MB)
62 17:45:35.419557 progress 60 % (4 MB)
63 17:45:35.421751 progress 65 % (5 MB)
64 17:45:35.423956 progress 70 % (5 MB)
65 17:45:35.426133 progress 75 % (6 MB)
66 17:45:35.428348 progress 80 % (6 MB)
67 17:45:35.430509 progress 85 % (6 MB)
68 17:45:35.432717 progress 90 % (7 MB)
69 17:45:35.434936 progress 95 % (7 MB)
70 17:45:35.437112 progress 100 % (8 MB)
71 17:45:35.437227 8 MB downloaded in 0.05 s (174.99 MB/s)
72 17:45:35.437368 end: 1.2.1 http-download (duration 00:00:00) [common]
74 17:45:35.437591 end: 1.2 download-retry (duration 00:00:00) [common]
75 17:45:35.437677 start: 1.3 download-retry (timeout 00:09:59) [common]
76 17:45:35.437761 start: 1.3.1 http-download (timeout 00:09:59) [common]
77 17:45:35.437899 downloading http://storage.kernelci.org/cip/linux-4.4.y-st/v4.4-st20-1778-g3b01feff09495/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/modules.tar.xz
78 17:45:35.437971 saving as /var/lib/lava/dispatcher/tmp/11712549/tftp-deploy-mtnn8qlx/modules/modules.tar
79 17:45:35.438033 total size: 250928 (0 MB)
80 17:45:35.438095 Using unxz to decompress xz
81 17:45:35.442459 progress 13 % (0 MB)
82 17:45:35.442899 progress 26 % (0 MB)
83 17:45:35.443133 progress 39 % (0 MB)
84 17:45:35.444712 progress 52 % (0 MB)
85 17:45:35.446562 progress 65 % (0 MB)
86 17:45:35.448414 progress 78 % (0 MB)
87 17:45:35.450224 progress 91 % (0 MB)
88 17:45:35.451938 progress 100 % (0 MB)
89 17:45:35.457449 0 MB downloaded in 0.02 s (12.33 MB/s)
90 17:45:35.457673 end: 1.3.1 http-download (duration 00:00:00) [common]
92 17:45:35.457941 end: 1.3 download-retry (duration 00:00:00) [common]
93 17:45:35.458042 start: 1.4 prepare-tftp-overlay (timeout 00:09:59) [common]
94 17:45:35.458142 start: 1.4.1 extract-nfsrootfs (timeout 00:09:59) [common]
95 17:45:35.458227 end: 1.4.1 extract-nfsrootfs (duration 00:00:00) [common]
96 17:45:35.458314 start: 1.4.2 lava-overlay (timeout 00:09:59) [common]
97 17:45:35.458526 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11712549/lava-overlay-o50xxk__
98 17:45:35.458705 makedir: /var/lib/lava/dispatcher/tmp/11712549/lava-overlay-o50xxk__/lava-11712549/bin
99 17:45:35.458816 makedir: /var/lib/lava/dispatcher/tmp/11712549/lava-overlay-o50xxk__/lava-11712549/tests
100 17:45:35.458922 makedir: /var/lib/lava/dispatcher/tmp/11712549/lava-overlay-o50xxk__/lava-11712549/results
101 17:45:35.459035 Creating /var/lib/lava/dispatcher/tmp/11712549/lava-overlay-o50xxk__/lava-11712549/bin/lava-add-keys
102 17:45:35.459182 Creating /var/lib/lava/dispatcher/tmp/11712549/lava-overlay-o50xxk__/lava-11712549/bin/lava-add-sources
103 17:45:35.459313 Creating /var/lib/lava/dispatcher/tmp/11712549/lava-overlay-o50xxk__/lava-11712549/bin/lava-background-process-start
104 17:45:35.459443 Creating /var/lib/lava/dispatcher/tmp/11712549/lava-overlay-o50xxk__/lava-11712549/bin/lava-background-process-stop
105 17:45:35.459570 Creating /var/lib/lava/dispatcher/tmp/11712549/lava-overlay-o50xxk__/lava-11712549/bin/lava-common-functions
106 17:45:35.459702 Creating /var/lib/lava/dispatcher/tmp/11712549/lava-overlay-o50xxk__/lava-11712549/bin/lava-echo-ipv4
107 17:45:35.459829 Creating /var/lib/lava/dispatcher/tmp/11712549/lava-overlay-o50xxk__/lava-11712549/bin/lava-install-packages
108 17:45:35.459955 Creating /var/lib/lava/dispatcher/tmp/11712549/lava-overlay-o50xxk__/lava-11712549/bin/lava-installed-packages
109 17:45:35.460079 Creating /var/lib/lava/dispatcher/tmp/11712549/lava-overlay-o50xxk__/lava-11712549/bin/lava-os-build
110 17:45:35.460204 Creating /var/lib/lava/dispatcher/tmp/11712549/lava-overlay-o50xxk__/lava-11712549/bin/lava-probe-channel
111 17:45:35.460329 Creating /var/lib/lava/dispatcher/tmp/11712549/lava-overlay-o50xxk__/lava-11712549/bin/lava-probe-ip
112 17:45:35.460454 Creating /var/lib/lava/dispatcher/tmp/11712549/lava-overlay-o50xxk__/lava-11712549/bin/lava-target-ip
113 17:45:35.460578 Creating /var/lib/lava/dispatcher/tmp/11712549/lava-overlay-o50xxk__/lava-11712549/bin/lava-target-mac
114 17:45:35.460703 Creating /var/lib/lava/dispatcher/tmp/11712549/lava-overlay-o50xxk__/lava-11712549/bin/lava-target-storage
115 17:45:35.460832 Creating /var/lib/lava/dispatcher/tmp/11712549/lava-overlay-o50xxk__/lava-11712549/bin/lava-test-case
116 17:45:35.460957 Creating /var/lib/lava/dispatcher/tmp/11712549/lava-overlay-o50xxk__/lava-11712549/bin/lava-test-event
117 17:45:35.461109 Creating /var/lib/lava/dispatcher/tmp/11712549/lava-overlay-o50xxk__/lava-11712549/bin/lava-test-feedback
118 17:45:35.461233 Creating /var/lib/lava/dispatcher/tmp/11712549/lava-overlay-o50xxk__/lava-11712549/bin/lava-test-raise
119 17:45:35.461375 Creating /var/lib/lava/dispatcher/tmp/11712549/lava-overlay-o50xxk__/lava-11712549/bin/lava-test-reference
120 17:45:35.461517 Creating /var/lib/lava/dispatcher/tmp/11712549/lava-overlay-o50xxk__/lava-11712549/bin/lava-test-runner
121 17:45:35.461644 Creating /var/lib/lava/dispatcher/tmp/11712549/lava-overlay-o50xxk__/lava-11712549/bin/lava-test-set
122 17:45:35.461772 Creating /var/lib/lava/dispatcher/tmp/11712549/lava-overlay-o50xxk__/lava-11712549/bin/lava-test-shell
123 17:45:35.461903 Updating /var/lib/lava/dispatcher/tmp/11712549/lava-overlay-o50xxk__/lava-11712549/bin/lava-install-packages (oe)
124 17:45:35.462056 Updating /var/lib/lava/dispatcher/tmp/11712549/lava-overlay-o50xxk__/lava-11712549/bin/lava-installed-packages (oe)
125 17:45:35.462179 Creating /var/lib/lava/dispatcher/tmp/11712549/lava-overlay-o50xxk__/lava-11712549/environment
126 17:45:35.462280 LAVA metadata
127 17:45:35.462355 - LAVA_JOB_ID=11712549
128 17:45:35.462421 - LAVA_DISPATCHER_IP=192.168.201.1
129 17:45:35.462524 start: 1.4.2.1 lava-vland-overlay (timeout 00:09:59) [common]
130 17:45:35.462615 skipped lava-vland-overlay
131 17:45:35.462718 end: 1.4.2.1 lava-vland-overlay (duration 00:00:00) [common]
132 17:45:35.462801 start: 1.4.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
133 17:45:35.462877 skipped lava-multinode-overlay
134 17:45:35.462966 end: 1.4.2.2 lava-multinode-overlay (duration 00:00:00) [common]
135 17:45:35.463045 start: 1.4.2.3 test-definition (timeout 00:09:59) [common]
136 17:45:35.463119 Loading test definitions
137 17:45:35.463212 start: 1.4.2.3.1 inline-repo-action (timeout 00:09:59) [common]
138 17:45:35.463289 Using /lava-11712549 at stage 0
139 17:45:35.463678 uuid=11712549_1.4.2.3.1 testdef=None
140 17:45:35.463766 end: 1.4.2.3.1 inline-repo-action (duration 00:00:00) [common]
141 17:45:35.463850 start: 1.4.2.3.2 test-overlay (timeout 00:09:59) [common]
142 17:45:35.464464 end: 1.4.2.3.2 test-overlay (duration 00:00:00) [common]
144 17:45:35.464707 start: 1.4.2.3.3 test-install-overlay (timeout 00:09:59) [common]
145 17:45:35.465346 end: 1.4.2.3.3 test-install-overlay (duration 00:00:00) [common]
147 17:45:35.465739 start: 1.4.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
148 17:45:35.466352 runner path: /var/lib/lava/dispatcher/tmp/11712549/lava-overlay-o50xxk__/lava-11712549/0/tests/0_dmesg test_uuid 11712549_1.4.2.3.1
149 17:45:35.466510 end: 1.4.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
151 17:45:35.466800 start: 1.4.2.3.5 inline-repo-action (timeout 00:09:59) [common]
152 17:45:35.466871 Using /lava-11712549 at stage 1
153 17:45:35.467177 uuid=11712549_1.4.2.3.5 testdef=None
154 17:45:35.467265 end: 1.4.2.3.5 inline-repo-action (duration 00:00:00) [common]
155 17:45:35.467349 start: 1.4.2.3.6 test-overlay (timeout 00:09:59) [common]
156 17:45:35.467853 end: 1.4.2.3.6 test-overlay (duration 00:00:00) [common]
158 17:45:35.468065 start: 1.4.2.3.7 test-install-overlay (timeout 00:09:59) [common]
159 17:45:35.468734 end: 1.4.2.3.7 test-install-overlay (duration 00:00:00) [common]
161 17:45:35.468965 start: 1.4.2.3.8 test-runscript-overlay (timeout 00:09:59) [common]
162 17:45:35.469713 runner path: /var/lib/lava/dispatcher/tmp/11712549/lava-overlay-o50xxk__/lava-11712549/1/tests/1_bootrr test_uuid 11712549_1.4.2.3.5
163 17:45:35.469897 end: 1.4.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
165 17:45:35.470129 Creating lava-test-runner.conf files
166 17:45:35.470191 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11712549/lava-overlay-o50xxk__/lava-11712549/0 for stage 0
167 17:45:35.470280 - 0_dmesg
168 17:45:35.470359 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11712549/lava-overlay-o50xxk__/lava-11712549/1 for stage 1
169 17:45:35.470451 - 1_bootrr
170 17:45:35.470545 end: 1.4.2.3 test-definition (duration 00:00:00) [common]
171 17:45:35.470689 start: 1.4.2.4 compress-overlay (timeout 00:09:59) [common]
172 17:45:35.479607 end: 1.4.2.4 compress-overlay (duration 00:00:00) [common]
173 17:45:35.479735 start: 1.4.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
174 17:45:35.479859 end: 1.4.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
175 17:45:35.479961 end: 1.4.2 lava-overlay (duration 00:00:00) [common]
176 17:45:35.480046 start: 1.4.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
177 17:45:35.729719 end: 1.4.3 extract-overlay-ramdisk (duration 00:00:00) [common]
178 17:45:35.730143 start: 1.4.4 extract-modules (timeout 00:09:59) [common]
179 17:45:35.730262 extracting modules file /var/lib/lava/dispatcher/tmp/11712549/tftp-deploy-mtnn8qlx/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11712549/extract-overlay-ramdisk-1rb1wmjn/ramdisk
180 17:45:35.748163 end: 1.4.4 extract-modules (duration 00:00:00) [common]
181 17:45:35.748284 start: 1.4.5 apply-overlay-tftp (timeout 00:09:59) [common]
182 17:45:35.748378 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11712549/compress-overlay-igztn2qu/overlay-1.4.2.4.tar.gz to ramdisk
183 17:45:35.748450 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11712549/compress-overlay-igztn2qu/overlay-1.4.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11712549/extract-overlay-ramdisk-1rb1wmjn/ramdisk
184 17:45:35.757284 end: 1.4.5 apply-overlay-tftp (duration 00:00:00) [common]
185 17:45:35.757394 start: 1.4.6 configure-preseed-file (timeout 00:09:59) [common]
186 17:45:35.757487 end: 1.4.6 configure-preseed-file (duration 00:00:00) [common]
187 17:45:35.757578 start: 1.4.7 compress-ramdisk (timeout 00:09:59) [common]
188 17:45:35.757657 Building ramdisk /var/lib/lava/dispatcher/tmp/11712549/extract-overlay-ramdisk-1rb1wmjn/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11712549/extract-overlay-ramdisk-1rb1wmjn/ramdisk
189 17:45:35.885419 >> 49788 blocks
190 17:45:36.711911 rename /var/lib/lava/dispatcher/tmp/11712549/extract-overlay-ramdisk-1rb1wmjn/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11712549/tftp-deploy-mtnn8qlx/ramdisk/ramdisk.cpio.gz
191 17:45:36.712334 end: 1.4.7 compress-ramdisk (duration 00:00:01) [common]
192 17:45:36.712459 start: 1.4.8 prepare-kernel (timeout 00:09:58) [common]
193 17:45:36.712557 start: 1.4.8.1 prepare-fit (timeout 00:09:58) [common]
194 17:45:36.712654 No mkimage arch provided, not using FIT.
195 17:45:36.712744 end: 1.4.8.1 prepare-fit (duration 00:00:00) [common]
196 17:45:36.712824 end: 1.4.8 prepare-kernel (duration 00:00:00) [common]
197 17:45:36.712930 end: 1.4 prepare-tftp-overlay (duration 00:00:01) [common]
198 17:45:36.713023 start: 1.5 lxc-create-udev-rule-action (timeout 00:09:58) [common]
199 17:45:36.713099 No LXC device requested
200 17:45:36.713176 end: 1.5 lxc-create-udev-rule-action (duration 00:00:00) [common]
201 17:45:36.713261 start: 1.6 deploy-device-env (timeout 00:09:58) [common]
202 17:45:36.713346 end: 1.6 deploy-device-env (duration 00:00:00) [common]
203 17:45:36.713439 Checking files for TFTP limit of 4294967296 bytes.
204 17:45:36.713891 end: 1 tftp-deploy (duration 00:00:02) [common]
205 17:45:36.713996 start: 2 depthcharge-action (timeout 00:05:00) [common]
206 17:45:36.714087 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
207 17:45:36.714204 substitutions:
208 17:45:36.714270 - {DTB}: None
209 17:45:36.714332 - {INITRD}: 11712549/tftp-deploy-mtnn8qlx/ramdisk/ramdisk.cpio.gz
210 17:45:36.714392 - {KERNEL}: 11712549/tftp-deploy-mtnn8qlx/kernel/bzImage
211 17:45:36.714449 - {LAVA_MAC}: None
212 17:45:36.714505 - {PRESEED_CONFIG}: None
213 17:45:36.714559 - {PRESEED_LOCAL}: None
214 17:45:36.714660 - {RAMDISK}: 11712549/tftp-deploy-mtnn8qlx/ramdisk/ramdisk.cpio.gz
215 17:45:36.714729 - {ROOT_PART}: None
216 17:45:36.714799 - {ROOT}: None
217 17:45:36.714867 - {SERVER_IP}: 192.168.201.1
218 17:45:36.714921 - {TEE}: None
219 17:45:36.714975 Parsed boot commands:
220 17:45:36.715028 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
221 17:45:36.715200 Parsed boot commands: tftpboot 192.168.201.1 11712549/tftp-deploy-mtnn8qlx/kernel/bzImage 11712549/tftp-deploy-mtnn8qlx/kernel/cmdline 11712549/tftp-deploy-mtnn8qlx/ramdisk/ramdisk.cpio.gz
222 17:45:36.715288 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
223 17:45:36.715374 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
224 17:45:36.715463 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
225 17:45:36.715593 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
226 17:45:36.715663 Not connected, no need to disconnect.
227 17:45:36.715737 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
228 17:45:36.715818 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
229 17:45:36.715887 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh acer-cbv514-1h-34uz-brya-cbg-8'
230 17:45:36.719799 Setting prompt string to ['lava-test: # ']
231 17:45:36.720147 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
232 17:45:36.720250 end: 2.2.1 reset-connection (duration 00:00:00) [common]
233 17:45:36.720346 start: 2.2.2 reset-device (timeout 00:05:00) [common]
234 17:45:36.720440 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
235 17:45:36.720664 Calling: 'pduclient' '--daemon=localhost' '--hostname=acer-cbv514-1h-34uz-brya-cbg-8' '--port=1' '--command=reboot'
236 17:45:41.873703 >> Command sent successfully.
237 17:45:41.884105 Returned 0 in 5 seconds
238 17:45:41.985315 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
240 17:45:41.986849 end: 2.2.2 reset-device (duration 00:00:05) [common]
241 17:45:41.987351 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
242 17:45:41.987801 Setting prompt string to 'Starting depthcharge on Volmar...'
243 17:45:41.988132 Changing prompt to 'Starting depthcharge on Volmar...'
244 17:45:41.988461 depthcharge-start: Wait for prompt Starting depthcharge on Volmar... (timeout 00:05:00)
245 17:45:41.989625 [Enter `^Ec?' for help]
246 17:45:43.775915
247 17:45:43.776463
248 17:45:43.782532 coreboot-c7721883 Tue Feb 7 00:11:29 UTC 2023 bootblock starting (log level: 8)...
249 17:45:43.785283 CPU: 12th Gen Intel(R) Core(TM) i3-1215U
250 17:45:43.792215 CPU: ID 906a4, Alderlake R0 Platform, ucode: 00000423
251 17:45:43.798749 CPU: AES supported, TXT NOT supported, VT supported
252 17:45:43.805422 Cache: Level 3: Associativity = 10 Partitions = 1 Line Size = 64 Sets = 16384
253 17:45:43.805955 Cache size = 10 MiB
254 17:45:43.811947 MCH: device id 4609 (rev 04) is Alderlake-P
255 17:45:43.815967 PCH: device id 5182 (rev 01) is Raptorlake-P SKU
256 17:45:43.822045 IGD: device id 46b3 (rev 0c) is Alderlake P GT2
257 17:45:43.825498 VBOOT: Loading verstage.
258 17:45:43.828847 FMAP: Found "FLASH" version 1.1 at 0x1804000.
259 17:45:43.832137 FMAP: base = 0x0 size = 0x2000000 #areas = 37
260 17:45:43.838700 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
261 17:45:43.845676 CBFS: mcache @0xfef85600 built for 72 files, used 0xfd8 of 0x2000 bytes
262 17:45:43.855531 CBFS: Found 'fallback/verstage' @0x18a540 size 0x16ae8 in mcache @0xfef85954
263 17:45:43.856104
264 17:45:43.856449
265 17:45:43.864947 coreboot-c7721883 Tue Feb 7 00:11:29 UTC 2023 verstage starting (log level: 8)...
266 17:45:43.868649 Probing TPM I2C: I2C bus 1 version 0x3230302a
267 17:45:43.872036 DW I2C bus 1 at 0xfe022000 (400 KHz)
268 17:45:43.875902 done! DID_VID 0x00281ae0
269 17:45:43.879321 TPM ready after 0 ms
270 17:45:43.882701 cr50 TPM 2.0 (i2c 1:0x50 id 0x28)
271 17:45:43.896009 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.111/cr50_v3.9
272 17:45:43.901640 Current CR50_BOARD_CFG = 0x80000001, matches desired = 0x00000001
273 17:45:43.949206 tlcl_send_startup: Startup return code is 0
274 17:45:43.949724 TPM: setup succeeded
275 17:45:43.968833 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
276 17:45:43.989165 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
277 17:45:43.993665 Chrome EC: UHEPI supported
278 17:45:43.996939 Reading cr50 boot mode
279 17:45:44.011456 Cr50 says boot_mode is VERIFIED_RW(0x00).
280 17:45:44.011987 Phase 1
281 17:45:44.015235 FMAP: area GBB found @ 1805000 (458752 bytes)
282 17:45:44.025926 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
283 17:45:44.032122 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
284 17:45:44.039064 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0
285 17:45:44.039597 Phase 2
286 17:45:44.039941 Phase 3
287 17:45:44.045735 FMAP: area GBB found @ 1805000 (458752 bytes)
288 17:45:44.048872 FMAP: area VBLOCK_A found @ 500000 (65536 bytes)
289 17:45:44.055700 FMAP: area VBLOCK_A found @ 500000 (65536 bytes)
290 17:45:44.062386 VB2:vb2_verify_keyblock() Checking keyblock signature...
291 17:45:44.069152 VB2:vb2_verify_data() HW crypto for hash_alg 3 not supported, using SW
292 17:45:44.075624 VB2:vb2_verify_digest() HW RSA for sig_alg 5 not supported, using SW
293 17:45:44.082302 VB2:vb2_rsa_verify_digest() HW modexp for sig_alg 5 not supported, using SW
294 17:45:44.096327 FMAP: area VBLOCK_A found @ 500000 (65536 bytes)
295 17:45:44.099512 FMAP: area VBLOCK_A found @ 500000 (65536 bytes)
296 17:45:44.106184 VB2:vb2_verify_fw_preamble() Verifying preamble.
297 17:45:44.112856 VB2:vb2_verify_data() Using HW crypto engine for hash_alg 2
298 17:45:44.119303 VB2:vb2_verify_digest() HW RSA for sig_alg 4 not supported, using SW
299 17:45:44.126074 VB2:vb2_rsa_verify_digest() HW modexp for sig_alg 4 not supported, using SW
300 17:45:44.130382 Phase 4
301 17:45:44.133656 FMAP: area FW_MAIN_A found @ 510000 (5242816 bytes)
302 17:45:44.140016 VB2:vb2api_init_hash() Using HW crypto engine for hash_alg 2
303 17:45:44.352973 VB2:vb2_verify_digest() HW RSA for sig_alg 4 not supported, using SW
304 17:45:44.359593 VB2:vb2_rsa_verify_digest() HW modexp for sig_alg 4 not supported, using SW
305 17:45:44.362726 Saving vboot hash.
306 17:45:44.370399 TPM: Extending digest for `VBOOT: boot mode` into PCR 0
307 17:45:44.387267 tlcl_extend: response is 0
308 17:45:44.394150 TPM: Digest of `VBOOT: boot mode` to PCR 0 measured
309 17:45:44.400444 TPM: Extending digest for `VBOOT: GBB HWID` into PCR 1
310 17:45:44.414854 tlcl_extend: response is 0
311 17:45:44.422348 TPM: Digest of `VBOOT: GBB HWID` to PCR 1 measured
312 17:45:44.441306 tlcl_lock_nv_write: response is 0
313 17:45:44.460279 tlcl_lock_nv_write: response is 0
314 17:45:44.460819 Slot A is selected
315 17:45:44.466853 FMAP: area FW_MAIN_A found @ 510000 (5242816 bytes)
316 17:45:44.473678 CBFS: mcache @0xfef87600 built for 22 files, used 0x43c of 0x2000 bytes
317 17:45:44.479904 CBFS: Found 'fallback/romstage' @0x0 size 0x1d810 in mcache @0xfef87600
318 17:45:44.487237 BS: verstage times (exec / console): total (unknown) / 256 ms
319 17:45:44.487787
320 17:45:44.488133
321 17:45:44.492956 coreboot-c7721883 Tue Feb 7 00:11:29 UTC 2023 romstage starting (log level: 8)...
322 17:45:44.497583 Google Chrome EC: version:
323 17:45:44.500588 ro: volmar_v2.0.14126-e605144e9c
324 17:45:44.504190 rw: volmar_v0.0.55-22d1557
325 17:45:44.507166 running image: 2
326 17:45:44.511145 FMAP: area FW_MAIN_A found @ 510000 (5242816 bytes)
327 17:45:44.520471 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
328 17:45:44.527490 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
329 17:45:44.533850 CBFS: Found 'ecrw.hash' @0x7de00 size 0x20 in mcache @0xfef8785c
330 17:45:44.543761 VB2:check_ec_hash() Hexp RW(active): 27af2e81512cb95ff50318b5669d2c9bac939e1af81a41d7fa10c014b19b12fa
331 17:45:44.553924 VB2:check_ec_hash() Hmir: 27af2e81512cb95ff50318b5669d2c9bac939e1af81a41d7fa10c014b19b12fa
332 17:45:44.557439 EC took 941us to calculate image hash
333 17:45:44.567286 VB2:check_ec_hash() Heff RW(active): 27af2e81512cb95ff50318b5669d2c9bac939e1af81a41d7fa10c014b19b12fa
334 17:45:44.570105 VB2:sync_ec() select_rw=RW(active)
335 17:45:44.583284 Waited 270us to clear limit power flag.
336 17:45:44.586932 pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00
337 17:45:44.590163 gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000
338 17:45:44.593816 gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000
339 17:45:44.597441 gpe0_sts[2]: 00040000 gpe0_en[2]: 00000000
340 17:45:44.604219 gpe0_sts[3]: 00000000 gpe0_en[3]: 00082000
341 17:45:44.604740 TCO_STS: 0000 0000
342 17:45:44.608148 GEN_PMCON: d0015038 00002200
343 17:45:44.611443 GBLRST_CAUSE: 00000000 00000000
344 17:45:44.614401 HPR_CAUSE0: 00000000
345 17:45:44.614964 prev_sleep_state 5
346 17:45:44.621488 Abort disabling TXT, as CPU is not TXT capable.
347 17:45:44.628037 cse_lite: Number of partitions = 3
348 17:45:44.631258 cse_lite: Current partition = RO
349 17:45:44.631694 cse_lite: Next partition = RO
350 17:45:44.634969 cse_lite: Flags = 0x7
351 17:45:44.641726 cse_lite: RO version = 16.1.25.2049 (Status=0x0, Start=0x2000, End=0x14ffff)
352 17:45:44.651507 cse_lite: RW version = 16.1.25.2049 (Status=0x0, Start=0x1b9000, End=0x3a1fff)
353 17:45:44.654673 FMAP: area SI_ME found @ 1000 (5238784 bytes)
354 17:45:44.661139 SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
355 17:45:44.668005 cse_lite: CSE RW partition: offset = 0x1b9000, size = 0x1e9000
356 17:45:44.674870 CBFS: Found 'me_rw.version' @0x7dd00 size 0xd in mcache @0xfef877e8
357 17:45:44.677775 cse_lite: CSE CBFS RW version : 16.1.25.2049
358 17:45:44.684652 cse_lite: Set Boot Partition Info Command (RW)
359 17:45:44.688100 HECI: Global Reset(Type:1) Command
360 17:45:46.099387
361 17:45:46.100006
362 17:45:46.106977 coreboot-c7721883 Tue Feb 7 00:11:29 UTC 2023 bootblock starting (log level: 8)...
363 17:45:46.110340 CPU: 12th Gen Intel(R) Core(TM) i3-1215U
364 17:45:46.117312 CPU: ID 906a4, Alderlake R0 Platform, ucode: 00000423
365 17:45:46.120514 CPU: AES supported, TXT NOT supported, VT supported
366 17:45:46.129940 Cache: Level 3: Associativity = 10 Partitions = 1 Line Size = 64 Sets = 16384
367 17:45:46.130377 Cache size = 10 MiB
368 17:45:46.136864 MCH: device id 4609 (rev 04) is Alderlake-P
369 17:45:46.140218 PCH: device id 5182 (rev 01) is Raptorlake-P SKU
370 17:45:46.146858 IGD: device id 46b3 (rev 0c) is Alderlake P GT2
371 17:45:46.147297 VBOOT: Loading verstage.
372 17:45:46.154401 FMAP: Found "FLASH" version 1.1 at 0x1804000.
373 17:45:46.157829 FMAP: base = 0x0 size = 0x2000000 #areas = 37
374 17:45:46.161344 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
375 17:45:46.168760 CBFS: mcache @0xfef85600 built for 72 files, used 0xfd8 of 0x2000 bytes
376 17:45:46.178901 CBFS: Found 'fallback/verstage' @0x18a540 size 0x16ae8 in mcache @0xfef85954
377 17:45:46.179433
378 17:45:46.179770
379 17:45:46.189157 coreboot-c7721883 Tue Feb 7 00:11:29 UTC 2023 verstage starting (log level: 8)...
380 17:45:46.195749 Probing TPM I2C: I2C bus 1 version 0x3230302a
381 17:45:46.198781 DW I2C bus 1 at 0xfe022000 (400 KHz)
382 17:45:46.202141 done! DID_VID 0x00281ae0
383 17:45:46.202730 TPM ready after 0 ms
384 17:45:46.206721 cr50 TPM 2.0 (i2c 1:0x50 id 0x28)
385 17:45:46.220684 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.111/cr50_v3.9
386 17:45:46.223813 Current CR50_BOARD_CFG = 0x80000001, matches desired = 0x00000001
387 17:45:46.275170 tlcl_send_startup: Startup return code is 0
388 17:45:46.275702 TPM: setup succeeded
389 17:45:46.295980 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
390 17:45:46.316305 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
391 17:45:46.320528 Chrome EC: UHEPI supported
392 17:45:46.323781 Reading cr50 boot mode
393 17:45:46.338551 Cr50 says boot_mode is VERIFIED_RW(0x00).
394 17:45:46.339104 Phase 1
395 17:45:46.345337 FMAP: area GBB found @ 1805000 (458752 bytes)
396 17:45:46.351697 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
397 17:45:46.358615 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
398 17:45:46.365189 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0
399 17:45:46.365707 Phase 2
400 17:45:46.368449 Phase 3
401 17:45:46.371870 FMAP: area GBB found @ 1805000 (458752 bytes)
402 17:45:46.378657 FMAP: area VBLOCK_A found @ 500000 (65536 bytes)
403 17:45:46.382004 FMAP: area VBLOCK_A found @ 500000 (65536 bytes)
404 17:45:46.388832 VB2:vb2_verify_keyblock() Checking keyblock signature...
405 17:45:46.395412 VB2:vb2_verify_data() HW crypto for hash_alg 3 not supported, using SW
406 17:45:46.402017 VB2:vb2_verify_digest() HW RSA for sig_alg 5 not supported, using SW
407 17:45:46.411209 VB2:vb2_rsa_verify_digest() HW modexp for sig_alg 5 not supported, using SW
408 17:45:46.423723 FMAP: area VBLOCK_A found @ 500000 (65536 bytes)
409 17:45:46.426934 FMAP: area VBLOCK_A found @ 500000 (65536 bytes)
410 17:45:46.433898 VB2:vb2_verify_fw_preamble() Verifying preamble.
411 17:45:46.440747 VB2:vb2_verify_data() Using HW crypto engine for hash_alg 2
412 17:45:46.447384 VB2:vb2_verify_digest() HW RSA for sig_alg 4 not supported, using SW
413 17:45:46.454066 VB2:vb2_rsa_verify_digest() HW modexp for sig_alg 4 not supported, using SW
414 17:45:46.457682 Phase 4
415 17:45:46.461294 FMAP: area FW_MAIN_A found @ 510000 (5242816 bytes)
416 17:45:46.467489 VB2:vb2api_init_hash() Using HW crypto engine for hash_alg 2
417 17:45:46.679707 VB2:vb2_verify_digest() HW RSA for sig_alg 4 not supported, using SW
418 17:45:46.686378 VB2:vb2_rsa_verify_digest() HW modexp for sig_alg 4 not supported, using SW
419 17:45:46.689893 Saving vboot hash.
420 17:45:46.696351 TPM: Extending digest for `VBOOT: boot mode` into PCR 0
421 17:45:46.712440 tlcl_extend: response is 0
422 17:45:46.719318 TPM: Digest of `VBOOT: boot mode` to PCR 0 measured
423 17:45:46.725419 TPM: Extending digest for `VBOOT: GBB HWID` into PCR 1
424 17:45:46.740165 tlcl_extend: response is 0
425 17:45:46.746936 TPM: Digest of `VBOOT: GBB HWID` to PCR 1 measured
426 17:45:46.766835 tlcl_lock_nv_write: response is 0
427 17:45:46.786313 tlcl_lock_nv_write: response is 0
428 17:45:46.786886 Slot A is selected
429 17:45:46.792545 FMAP: area FW_MAIN_A found @ 510000 (5242816 bytes)
430 17:45:46.799513 CBFS: mcache @0xfef87600 built for 22 files, used 0x43c of 0x2000 bytes
431 17:45:46.806237 CBFS: Found 'fallback/romstage' @0x0 size 0x1d810 in mcache @0xfef87600
432 17:45:46.812378 BS: verstage times (exec / console): total (unknown) / 256 ms
433 17:45:46.812915
434 17:45:46.813257
435 17:45:46.819172 coreboot-c7721883 Tue Feb 7 00:11:29 UTC 2023 romstage starting (log level: 8)...
436 17:45:46.822877 Google Chrome EC: version:
437 17:45:46.826451 ro: volmar_v2.0.14126-e605144e9c
438 17:45:46.829435 rw: volmar_v0.0.55-22d1557
439 17:45:46.832838 running image: 2
440 17:45:46.835958 FMAP: area FW_MAIN_A found @ 510000 (5242816 bytes)
441 17:45:46.846476 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
442 17:45:46.852988 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
443 17:45:46.859487 CBFS: Found 'ecrw.hash' @0x7de00 size 0x20 in mcache @0xfef8785c
444 17:45:46.869200 VB2:check_ec_hash() Hexp RW(active): 27af2e81512cb95ff50318b5669d2c9bac939e1af81a41d7fa10c014b19b12fa
445 17:45:46.879391 VB2:check_ec_hash() Hmir: 27af2e81512cb95ff50318b5669d2c9bac939e1af81a41d7fa10c014b19b12fa
446 17:45:46.886649 EC took 2113us to calculate image hash
447 17:45:46.896633 VB2:check_ec_hash() Heff RW(active): 27af2e81512cb95ff50318b5669d2c9bac939e1af81a41d7fa10c014b19b12fa
448 17:45:46.899770 VB2:sync_ec() select_rw=RW(active)
449 17:45:46.910055 Waited 300us to clear limit power flag.
450 17:45:46.913544 pm1_sts: 8100 pm1_en: 0000 pm1_cnt: 00001c00
451 17:45:46.917136 gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000
452 17:45:46.920404 gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000
453 17:45:46.926688 gpe0_sts[2]: 00040000 gpe0_en[2]: 00000000
454 17:45:46.929873 gpe0_sts[3]: 00000000 gpe0_en[3]: 00082000
455 17:45:46.933458 TCO_STS: 0000 0000
456 17:45:46.936515 GEN_PMCON: d1001038 00002200
457 17:45:46.939784 GBLRST_CAUSE: 00000040 00000000
458 17:45:46.940217 HPR_CAUSE0: 00000000
459 17:45:46.943099 prev_sleep_state 5
460 17:45:46.946531 Abort disabling TXT, as CPU is not TXT capable.
461 17:45:46.955063 cse_lite: Number of partitions = 3
462 17:45:46.958469 cse_lite: Current partition = RW
463 17:45:46.959038 cse_lite: Next partition = RW
464 17:45:46.961731 cse_lite: Flags = 0x7
465 17:45:46.968513 cse_lite: RO version = 16.1.25.2049 (Status=0x0, Start=0x2000, End=0x14ffff)
466 17:45:46.978641 cse_lite: RW version = 16.1.25.2049 (Status=0x0, Start=0x1b9000, End=0x3a1fff)
467 17:45:46.981697 FMAP: area SI_ME found @ 1000 (5238784 bytes)
468 17:45:46.988466 SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
469 17:45:46.995028 cse_lite: CSE RW partition: offset = 0x1b9000, size = 0x1e9000
470 17:45:47.001694 CBFS: Found 'me_rw.version' @0x7dd00 size 0xd in mcache @0xfef877e8
471 17:45:47.004990 cse_lite: CSE CBFS RW version : 16.1.25.2049
472 17:45:47.007957 Boot Count incremented to 14766
473 17:45:47.014711 CBFS: Found 'fspm.bin' @0x7dfc0 size 0xc0000 in mcache @0xfef878d4
474 17:45:47.021951 FMAP: area RW_MRC_CACHE found @ f10000 (65536 bytes)
475 17:45:47.034936 Probing TPM I2C: done! DID_VID 0x00281ae0
476 17:45:47.037776 Locality already claimed
477 17:45:47.040796 cr50 TPM 2.0 (i2c 1:0x50 id 0x28)
478 17:45:47.060887 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x100d return code 0
479 17:45:47.067079 MRC: Hash idx 0x100d comparison successful.
480 17:45:47.070322 MRC cache found, size f6c8
481 17:45:47.070792 bootmode is set to: 2
482 17:45:47.074184 EC returned error result code 3
483 17:45:47.077326 FW_CONFIG value from CBI is 0x131
484 17:45:47.084690 fw_config match found: BOOT_NVME_MASK=BOOT_NVME_ENABLED
485 17:45:47.088188 SPD index = 0
486 17:45:47.091555 CBFS: Found 'spd.bin' @0x78380 size 0x400 in mcache @0xfef8776c
487 17:45:47.095008 SPD: module type is LPDDR4X
488 17:45:47.101452 SPD: module part number is K4U6E3S4AB-MGCL
489 17:45:47.104607 SPD: banks 8, ranks 1, rows 16, columns 10, density 8192 Mb
490 17:45:47.111377 SPD: device width 16 bits, bus width 16 bits
491 17:45:47.114887 SPD: module size is 1024 MB (per channel)
492 17:45:47.182613 CBMEM:
493 17:45:47.185992 IMD: root @ 0x76fff000 254 entries.
494 17:45:47.189121 IMD: root @ 0x76ffec00 62 entries.
495 17:45:47.197500 FMAP: area RO_VPD found @ 1800000 (16384 bytes)
496 17:45:47.200683 RO_VPD is uninitialized or empty.
497 17:45:47.203809 FMAP: area RW_VPD found @ f29000 (8192 bytes)
498 17:45:47.210599 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
499 17:45:47.214529 External stage cache:
500 17:45:47.216988 IMD: root @ 0x7bbff000 254 entries.
501 17:45:47.220613 IMD: root @ 0x7bbfec00 62 entries.
502 17:45:47.227453 FMAP: area RW_MRC_CACHE found @ f10000 (65536 bytes)
503 17:45:47.233749 MRC: Checking cached data update for 'RW_MRC_CACHE'.
504 17:45:47.237392 MRC: 'RW_MRC_CACHE' does not need update.
505 17:45:47.237824 8 DIMMs found
506 17:45:47.240767 SMM Memory Map
507 17:45:47.244039 SMRAM : 0x7b800000 0x800000
508 17:45:47.247309 Subregion 0: 0x7b800000 0x200000
509 17:45:47.250689 Subregion 1: 0x7ba00000 0x200000
510 17:45:47.253847 Subregion 2: 0x7bc00000 0x400000
511 17:45:47.257134 top_of_ram = 0x77000000
512 17:45:47.260475 MTRR Range: Start=76000000 End=77000000 (Size 1000000)
513 17:45:47.267127 MTRR Range: Start=7b800000 End=7c000000 (Size 800000)
514 17:45:47.273899 MTRR Range: Start=f9000000 End=fa000000 (Size 1000000)
515 17:45:47.277323 MTRR Range: Start=ff000000 End=0 (Size 1000000)
516 17:45:47.277871 Normal boot
517 17:45:47.287278 CBFS: Found 'fallback/postcar' @0x185000 size 0x54dc in mcache @0xfef87948
518 17:45:47.293616 Loading module at 0x76ab9000 with entry 0x76ab9031. filesize: 0x50e8 memsize: 0xa4a0
519 17:45:47.300743 Processing 237 relocs. Offset value of 0x74ab9000
520 17:45:47.308835 BS: romstage times (exec / console): total (unknown) / 377 ms
521 17:45:47.316117
522 17:45:47.316641
523 17:45:47.322939 coreboot-c7721883 Tue Feb 7 00:11:29 UTC 2023 postcar starting (log level: 8)...
524 17:45:47.323474 Normal boot
525 17:45:47.329366 FMAP: area FW_MAIN_A found @ 510000 (5242816 bytes)
526 17:45:47.335855 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
527 17:45:47.342305 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
528 17:45:47.352276 CBFS: Found 'fallback/ramstage' @0x52d00 size 0x24b33 in mcache @0x76add0b0
529 17:45:47.400418 Loading module at 0x76a2f000 with entry 0x76a2f000. filesize: 0x51f70 memsize: 0x880d0
530 17:45:47.406772 Processing 5931 relocs. Offset value of 0x72a2f000
531 17:45:47.410253 BS: postcar times (exec / console): total (unknown) / 51 ms
532 17:45:47.413447
533 17:45:47.413971
534 17:45:47.420485 coreboot-c7721883 Tue Feb 7 00:11:29 UTC 2023 ramstage starting (log level: 8)...
535 17:45:47.423346 Reserving BERT start 76a1e000, size 10000
536 17:45:47.426990 Normal boot
537 17:45:47.430328 FMAP: area RO_VPD found @ 1800000 (16384 bytes)
538 17:45:47.437089 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
539 17:45:47.446918 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
540 17:45:47.450079 FMAP: area RW_VPD found @ f29000 (8192 bytes)
541 17:45:47.453443 Google Chrome EC: version:
542 17:45:47.457027 ro: volmar_v2.0.14126-e605144e9c
543 17:45:47.460125 rw: volmar_v0.0.55-22d1557
544 17:45:47.463318 running image: 2
545 17:45:47.466579 ACPI _SWS is PM1 Index 8 GPE Index -1
546 17:45:47.469762 BS: BS_PRE_DEVICE entry times (exec / console): 0 / 4 ms
547 17:45:47.475139 EC returned error result code 3
548 17:45:47.478781 FW_CONFIG value from CBI is 0x131
549 17:45:47.485554 fw_config match found: BOOT_NVME_MASK=BOOT_NVME_ENABLED
550 17:45:47.488999 PCI: 00:1c.2 disabled by fw_config
551 17:45:47.495287 fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S
552 17:45:47.498718 fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S
553 17:45:47.505349 fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S
554 17:45:47.508541 fw_config match found: FPMCU_MASK=FPMCU_ENABLED
555 17:45:47.515492 FMAP: area FW_MAIN_A found @ 510000 (5242816 bytes)
556 17:45:47.522126 CBFS: Found 'cpu_microcode_blob.bin' @0x1d8c0 size 0x35400 in mcache @0x76add080
557 17:45:47.528313 microcode: sig=0x906a4 pf=0x80 revision=0x423
558 17:45:47.532041 microcode: Update skipped, already up-to-date
559 17:45:47.538171 CBFS: Found 'fsps.bin' @0x13e000 size 0x46fb3 in mcache @0x76add314
560 17:45:47.571453 Detected 6 core, 8 thread CPU.
561 17:45:47.574553 Setting up SMI for CPU
562 17:45:47.577359 IED base = 0x7bc00000
563 17:45:47.577833 IED size = 0x00400000
564 17:45:47.580671 Will perform SMM setup.
565 17:45:47.584626 CPU: 12th Gen Intel(R) Core(TM) i3-1215U.
566 17:45:47.587527 LAPIC 0x0 in XAPIC mode.
567 17:45:47.597949 Loading module at 0x00030000 with entry 0x00030000. filesize: 0x178 memsize: 0x178
568 17:45:47.600943 Processing 18 relocs. Offset value of 0x00030000
569 17:45:47.605769 Attempting to start 7 APs
570 17:45:47.608646 Waiting for 10ms after sending INIT.
571 17:45:47.622468 Waiting for SIPI to complete...
572 17:45:47.625262 done.
573 17:45:47.625786 LAPIC 0x16 in XAPIC mode.
574 17:45:47.628270 LAPIC 0x9 in XAPIC mode.
575 17:45:47.631750 LAPIC 0x12 in XAPIC mode.
576 17:45:47.635217 LAPIC 0x10 in XAPIC mode.
577 17:45:47.638509 AP: slot 5 apic_id 9, MCU rev: 0x00000423
578 17:45:47.641926 AP: slot 2 apic_id 10, MCU rev: 0x00000423
579 17:45:47.648715 AP: slot 1 apic_id 16, MCU rev: 0x00000423
580 17:45:47.649233 LAPIC 0x8 in XAPIC mode.
581 17:45:47.655145 AP: slot 3 apic_id 12, MCU rev: 0x00000423
582 17:45:47.655584 LAPIC 0x14 in XAPIC mode.
583 17:45:47.658393 LAPIC 0x1 in XAPIC mode.
584 17:45:47.664937 AP: slot 4 apic_id 14, MCU rev: 0x00000423
585 17:45:47.668684 Waiting for SIPI to complete...
586 17:45:47.669214 done.
587 17:45:47.671832 AP: slot 7 apic_id 1, MCU rev: 0x00000423
588 17:45:47.675312 AP: slot 6 apic_id 8, MCU rev: 0x00000423
589 17:45:47.678360 smm_setup_relocation_handler: enter
590 17:45:47.681772 smm_setup_relocation_handler: exit
591 17:45:47.691222 Loading module at 0x00038000 with entry 0x00038000. filesize: 0x208 memsize: 0x208
592 17:45:47.694645 Processing 11 relocs. Offset value of 0x00038000
593 17:45:47.701666 smm_module_setup_stub: stack_top = 0x7b804000
594 17:45:47.704836 smm_module_setup_stub: per cpu stack_size = 0x800
595 17:45:47.711193 smm_module_setup_stub: runtime.start32_offset = 0x4c
596 17:45:47.714748 smm_module_setup_stub: runtime.smm_size = 0x10000
597 17:45:47.721581 SMM Module: stub loaded at 38000. Will call 0x76a52094
598 17:45:47.724473 Installing permanent SMM handler to 0x7b800000
599 17:45:47.731377 smm_load_module: total_smm_space_needed e468, available -> 200000
600 17:45:47.740975 Loading module at 0x7b9f6000 with entry 0x7b9f6d5f. filesize: 0x4348 memsize: 0x9468
601 17:45:47.744377 Processing 255 relocs. Offset value of 0x7b9f6000
602 17:45:47.750925 smm_load_module: smram_start: 0x7b800000
603 17:45:47.754235 smm_load_module: smram_end: 7ba00000
604 17:45:47.757820 smm_load_module: handler start 0x7b9f6d5f
605 17:45:47.761202 smm_load_module: handler_size 98d0
606 17:45:47.764902 smm_load_module: fxsave_area 0x7b9ff000
607 17:45:47.767969 smm_load_module: fxsave_size 1000
608 17:45:47.771131 smm_load_module: CONFIG_MSEG_SIZE 0x0
609 17:45:47.777638 smm_load_module: CONFIG_BIOS_RESOURCE_LIST_SIZE 0x0
610 17:45:47.784486 smm_load_module: handler_mod_params.smbase = 0x7b800000
611 17:45:47.787781 smm_load_module: per_cpu_save_state_size = 0x400
612 17:45:47.791034 smm_load_module: num_cpus = 0x8
613 17:45:47.797727 smm_load_module: cbmemc = 0x76ade000, cbmemc_size = 0x20000
614 17:45:47.801249 smm_load_module: total_save_state_size = 0x2000
615 17:45:47.807948 smm_load_module: cpu0 entry: 7b9e6000
616 17:45:47.810963 smm_create_map: cpus allowed in one segment 30
617 17:45:47.814251 smm_create_map: min # of segments needed 1
618 17:45:47.817626 CPU 0x0
619 17:45:47.820787 smbase 7b9e6000 entry 7b9ee000
620 17:45:47.823957 ss_start 7b9f5c00 code_end 7b9ee208
621 17:45:47.824484 CPU 0x1
622 17:45:47.827429 smbase 7b9e5c00 entry 7b9edc00
623 17:45:47.834116 ss_start 7b9f5800 code_end 7b9ede08
624 17:45:47.834701 CPU 0x2
625 17:45:47.837302 smbase 7b9e5800 entry 7b9ed800
626 17:45:47.844134 ss_start 7b9f5400 code_end 7b9eda08
627 17:45:47.844563 CPU 0x3
628 17:45:47.847156 smbase 7b9e5400 entry 7b9ed400
629 17:45:47.850352 ss_start 7b9f5000 code_end 7b9ed608
630 17:45:47.853999 CPU 0x4
631 17:45:47.857168 smbase 7b9e5000 entry 7b9ed000
632 17:45:47.860951 ss_start 7b9f4c00 code_end 7b9ed208
633 17:45:47.863738 CPU 0x5
634 17:45:47.866944 smbase 7b9e4c00 entry 7b9ecc00
635 17:45:47.870226 ss_start 7b9f4800 code_end 7b9ece08
636 17:45:47.870701 CPU 0x6
637 17:45:47.874208 smbase 7b9e4800 entry 7b9ec800
638 17:45:47.880550 ss_start 7b9f4400 code_end 7b9eca08
639 17:45:47.880999 CPU 0x7
640 17:45:47.884213 smbase 7b9e4400 entry 7b9ec400
641 17:45:47.890326 ss_start 7b9f4000 code_end 7b9ec608
642 17:45:47.896971 Loading module at 0x7b9ee000 with entry 0x7b9ee000. filesize: 0x208 memsize: 0x208
643 17:45:47.903255 Processing 11 relocs. Offset value of 0x7b9ee000
644 17:45:47.906842 smm_place_entry_code: smbase 7b9e4400, stack_top 7b804000
645 17:45:47.913388 SMM Module: placing smm entry code at 7b9edc00, cpu # 0x1
646 17:45:47.920154 smm_place_entry_code: copying from 7b9ee000 to 7b9edc00 0x208 bytes
647 17:45:47.926875 SMM Module: placing smm entry code at 7b9ed800, cpu # 0x2
648 17:45:47.933410 smm_place_entry_code: copying from 7b9ee000 to 7b9ed800 0x208 bytes
649 17:45:47.940077 SMM Module: placing smm entry code at 7b9ed400, cpu # 0x3
650 17:45:47.946451 smm_place_entry_code: copying from 7b9ee000 to 7b9ed400 0x208 bytes
651 17:45:47.950264 SMM Module: placing smm entry code at 7b9ed000, cpu # 0x4
652 17:45:47.959718 smm_place_entry_code: copying from 7b9ee000 to 7b9ed000 0x208 bytes
653 17:45:47.962965 SMM Module: placing smm entry code at 7b9ecc00, cpu # 0x5
654 17:45:47.969485 smm_place_entry_code: copying from 7b9ee000 to 7b9ecc00 0x208 bytes
655 17:45:47.976492 SMM Module: placing smm entry code at 7b9ec800, cpu # 0x6
656 17:45:47.982897 smm_place_entry_code: copying from 7b9ee000 to 7b9ec800 0x208 bytes
657 17:45:47.990154 SMM Module: placing smm entry code at 7b9ec400, cpu # 0x7
658 17:45:47.996343 smm_place_entry_code: copying from 7b9ee000 to 7b9ec400 0x208 bytes
659 17:45:47.999625 smm_module_setup_stub: stack_top = 0x7b804000
660 17:45:48.006653 smm_module_setup_stub: per cpu stack_size = 0x800
661 17:45:48.009330 smm_module_setup_stub: runtime.start32_offset = 0x4c
662 17:45:48.016366 smm_module_setup_stub: runtime.smm_size = 0x200000
663 17:45:48.023163 SMM Module: stub loaded at 7b9ee000. Will call 0x7b9f6d5f
664 17:45:48.026336 Clearing SMI status registers
665 17:45:48.029305 SMI_STS: PM1
666 17:45:48.029736 PM1_STS: WAK PWRBTN
667 17:45:48.039252 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b9e6000, cpu = 0
668 17:45:48.039858 In relocation handler: CPU 0
669 17:45:48.046155 New SMBASE=0x7b9e6000 IEDBASE=0x7bc00000
670 17:45:48.049349 Writing SMRR. base = 0x7b800006, mask=0xff800c00
671 17:45:48.052558 Relocation complete.
672 17:45:48.059525 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b9e4400, cpu = 7
673 17:45:48.062545 In relocation handler: CPU 7
674 17:45:48.065702 New SMBASE=0x7b9e4400 IEDBASE=0x7bc00000
675 17:45:48.068840 Relocation complete.
676 17:45:48.076197 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b9e5400, cpu = 3
677 17:45:48.079170 In relocation handler: CPU 3
678 17:45:48.082785 New SMBASE=0x7b9e5400 IEDBASE=0x7bc00000
679 17:45:48.088820 Writing SMRR. base = 0x7b800006, mask=0xff800c00
680 17:45:48.089350 Relocation complete.
681 17:45:48.095501 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b9e5000, cpu = 4
682 17:45:48.098947 In relocation handler: CPU 4
683 17:45:48.102734 New SMBASE=0x7b9e5000 IEDBASE=0x7bc00000
684 17:45:48.108977 Writing SMRR. base = 0x7b800006, mask=0xff800c00
685 17:45:48.112142 Relocation complete.
686 17:45:48.118488 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b9e5800, cpu = 2
687 17:45:48.122435 In relocation handler: CPU 2
688 17:45:48.125441 New SMBASE=0x7b9e5800 IEDBASE=0x7bc00000
689 17:45:48.128759 Writing SMRR. base = 0x7b800006, mask=0xff800c00
690 17:45:48.132068 Relocation complete.
691 17:45:48.138463 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b9e5c00, cpu = 1
692 17:45:48.141958 In relocation handler: CPU 1
693 17:45:48.145483 New SMBASE=0x7b9e5c00 IEDBASE=0x7bc00000
694 17:45:48.152099 Writing SMRR. base = 0x7b800006, mask=0xff800c00
695 17:45:48.152641 Relocation complete.
696 17:45:48.158957 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b9e4800, cpu = 6
697 17:45:48.162145 In relocation handler: CPU 6
698 17:45:48.168290 New SMBASE=0x7b9e4800 IEDBASE=0x7bc00000
699 17:45:48.172264 Writing SMRR. base = 0x7b800006, mask=0xff800c00
700 17:45:48.175265 Relocation complete.
701 17:45:48.182127 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b9e4c00, cpu = 5
702 17:45:48.185513 In relocation handler: CPU 5
703 17:45:48.188373 New SMBASE=0x7b9e4c00 IEDBASE=0x7bc00000
704 17:45:48.191974 Relocation complete.
705 17:45:48.192506 Initializing CPU #0
706 17:45:48.195499 CPU: vendor Intel device 906a4
707 17:45:48.198466 CPU: family 06, model 9a, stepping 04
708 17:45:48.202087 Clearing out pending MCEs
709 17:45:48.205304 cpu: energy policy set to 7
710 17:45:48.208694 Turbo is available but hidden
711 17:45:48.212049 Turbo is available and visible
712 17:45:48.215308 microcode: Update skipped, already up-to-date
713 17:45:48.218164 CPU #0 initialized
714 17:45:48.218613 Initializing CPU #7
715 17:45:48.221997 Initializing CPU #4
716 17:45:48.225265 Initializing CPU #1
717 17:45:48.225790 Initializing CPU #3
718 17:45:48.228565 Initializing CPU #6
719 17:45:48.231710 Initializing CPU #2
720 17:45:48.232241 CPU: vendor Intel device 906a4
721 17:45:48.238201 CPU: family 06, model 9a, stepping 04
722 17:45:48.238754 Initializing CPU #5
723 17:45:48.241341 CPU: vendor Intel device 906a4
724 17:45:48.244758 CPU: family 06, model 9a, stepping 04
725 17:45:48.248626 CPU: vendor Intel device 906a4
726 17:45:48.252060 CPU: family 06, model 9a, stepping 04
727 17:45:48.255328 CPU: vendor Intel device 906a4
728 17:45:48.261732 CPU: family 06, model 9a, stepping 04
729 17:45:48.262267 CPU: vendor Intel device 906a4
730 17:45:48.267985 CPU: family 06, model 9a, stepping 04
731 17:45:48.268560 Clearing out pending MCEs
732 17:45:48.271275 Clearing out pending MCEs
733 17:45:48.274998 Clearing out pending MCEs
734 17:45:48.278240 Clearing out pending MCEs
735 17:45:48.281824 CPU: vendor Intel device 906a4
736 17:45:48.284969 CPU: family 06, model 9a, stepping 04
737 17:45:48.288304 cpu: energy policy set to 7
738 17:45:48.291590 cpu: energy policy set to 7
739 17:45:48.294688 microcode: Update skipped, already up-to-date
740 17:45:48.297863 CPU #1 initialized
741 17:45:48.301562 microcode: Update skipped, already up-to-date
742 17:45:48.302013 CPU #3 initialized
743 17:45:48.304986 cpu: energy policy set to 7
744 17:45:48.308620 cpu: energy policy set to 7
745 17:45:48.311322 CPU: vendor Intel device 906a4
746 17:45:48.314932 CPU: family 06, model 9a, stepping 04
747 17:45:48.321584 microcode: Update skipped, already up-to-date
748 17:45:48.322123 CPU #2 initialized
749 17:45:48.328026 microcode: Update skipped, already up-to-date
750 17:45:48.328550 CPU #4 initialized
751 17:45:48.331471 Clearing out pending MCEs
752 17:45:48.335214 Clearing out pending MCEs
753 17:45:48.338305 cpu: energy policy set to 7
754 17:45:48.338780 cpu: energy policy set to 7
755 17:45:48.345053 microcode: Update skipped, already up-to-date
756 17:45:48.345579 CPU #6 initialized
757 17:45:48.351384 microcode: Update skipped, already up-to-date
758 17:45:48.351809 CPU #5 initialized
759 17:45:48.354685 Clearing out pending MCEs
760 17:45:48.358322 cpu: energy policy set to 7
761 17:45:48.361533 microcode: Update skipped, already up-to-date
762 17:45:48.364831 CPU #7 initialized
763 17:45:48.367947 bsp_do_flight_plan done after 697 msecs.
764 17:45:48.371498 CPU: frequency set to 4400 MHz
765 17:45:48.374449 Enabling SMIs.
766 17:45:48.381243 BS: BS_DEV_INIT_CHIPS entry times (exec / console): 381 / 521 ms
767 17:45:48.396020 Probing TPM I2C: done! DID_VID 0x00281ae0
768 17:45:48.399223 Locality already claimed
769 17:45:48.403009 cr50 TPM 2.0 (i2c 1:0x50 id 0x28)
770 17:45:48.414299 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.111/cr50_v3.9
771 17:45:48.417593 Enabling GPIO PM b/c CR50 has long IRQ pulse support
772 17:45:48.424340 fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S
773 17:45:48.430685 CBFS: Found 'vbt.bin' @0x7d7c0 size 0x4e9 in mcache @0x76add1b8
774 17:45:48.434055 Found a VBT of 9216 bytes after decompression
775 17:45:48.437065 PCI 1.0, PIN A, using IRQ #16
776 17:45:48.440736 PCI 2.0, PIN A, using IRQ #17
777 17:45:48.443788 PCI 4.0, PIN A, using IRQ #18
778 17:45:48.447195 PCI 5.0, PIN A, using IRQ #16
779 17:45:48.450541 PCI 6.0, PIN A, using IRQ #16
780 17:45:48.454121 PCI 6.2, PIN C, using IRQ #18
781 17:45:48.457375 PCI 7.0, PIN A, using IRQ #19
782 17:45:48.460771 PCI 7.1, PIN B, using IRQ #20
783 17:45:48.463911 PCI 7.2, PIN C, using IRQ #21
784 17:45:48.467083 PCI 7.3, PIN D, using IRQ #22
785 17:45:48.470616 PCI 8.0, PIN A, using IRQ #23
786 17:45:48.474075 PCI D.0, PIN A, using IRQ #17
787 17:45:48.477182 PCI D.1, PIN B, using IRQ #19
788 17:45:48.477718 PCI 10.0, PIN A, using IRQ #24
789 17:45:48.480741 PCI 10.1, PIN B, using IRQ #25
790 17:45:48.483906 PCI 10.6, PIN C, using IRQ #20
791 17:45:48.487032 PCI 10.7, PIN D, using IRQ #21
792 17:45:48.490721 PCI 11.0, PIN A, using IRQ #26
793 17:45:48.493800 PCI 11.1, PIN B, using IRQ #27
794 17:45:48.497516 PCI 11.2, PIN C, using IRQ #28
795 17:45:48.500526 PCI 11.3, PIN D, using IRQ #29
796 17:45:48.503925 PCI 12.0, PIN A, using IRQ #30
797 17:45:48.507211 PCI 12.6, PIN B, using IRQ #31
798 17:45:48.510575 PCI 12.7, PIN C, using IRQ #22
799 17:45:48.513885 PCI 13.0, PIN A, using IRQ #32
800 17:45:48.517232 PCI 13.1, PIN B, using IRQ #33
801 17:45:48.520238 PCI 13.2, PIN C, using IRQ #34
802 17:45:48.523348 PCI 13.3, PIN D, using IRQ #35
803 17:45:48.527550 PCI 14.0, PIN B, using IRQ #23
804 17:45:48.530686 PCI 14.1, PIN A, using IRQ #36
805 17:45:48.531233 PCI 14.3, PIN C, using IRQ #17
806 17:45:48.533859 PCI 15.0, PIN A, using IRQ #37
807 17:45:48.537155 PCI 15.1, PIN B, using IRQ #38
808 17:45:48.540315 PCI 15.2, PIN C, using IRQ #39
809 17:45:48.543728 PCI 15.3, PIN D, using IRQ #40
810 17:45:48.547023 PCI 16.0, PIN A, using IRQ #18
811 17:45:48.550273 PCI 16.1, PIN B, using IRQ #19
812 17:45:48.553784 PCI 16.2, PIN C, using IRQ #20
813 17:45:48.556826 PCI 16.3, PIN D, using IRQ #21
814 17:45:48.560023 PCI 16.4, PIN A, using IRQ #18
815 17:45:48.563729 PCI 16.5, PIN B, using IRQ #19
816 17:45:48.566674 PCI 17.0, PIN A, using IRQ #22
817 17:45:48.570218 PCI 19.0, PIN A, using IRQ #41
818 17:45:48.573520 PCI 19.1, PIN B, using IRQ #42
819 17:45:48.576925 PCI 19.2, PIN C, using IRQ #43
820 17:45:48.580293 PCI 1C.0, PIN A, using IRQ #16
821 17:45:48.583670 PCI 1C.1, PIN B, using IRQ #17
822 17:45:48.584096 PCI 1C.2, PIN C, using IRQ #18
823 17:45:48.586563 PCI 1C.3, PIN D, using IRQ #19
824 17:45:48.589910 PCI 1C.4, PIN A, using IRQ #16
825 17:45:48.593568 PCI 1C.5, PIN B, using IRQ #17
826 17:45:48.596924 PCI 1C.6, PIN C, using IRQ #18
827 17:45:48.600102 PCI 1C.7, PIN D, using IRQ #19
828 17:45:48.603145 PCI 1D.0, PIN A, using IRQ #16
829 17:45:48.606701 PCI 1D.1, PIN B, using IRQ #17
830 17:45:48.610458 PCI 1D.2, PIN C, using IRQ #18
831 17:45:48.613444 PCI 1D.3, PIN D, using IRQ #19
832 17:45:48.616909 PCI 1E.0, PIN A, using IRQ #23
833 17:45:48.619990 PCI 1E.1, PIN B, using IRQ #20
834 17:45:48.623276 PCI 1E.2, PIN C, using IRQ #44
835 17:45:48.626449 PCI 1E.3, PIN D, using IRQ #45
836 17:45:48.629913 PCI 1F.3, PIN B, using IRQ #22
837 17:45:48.633315 PCI 1F.4, PIN C, using IRQ #23
838 17:45:48.636587 PCI 1F.6, PIN D, using IRQ #20
839 17:45:48.637120 PCI 1F.7, PIN A, using IRQ #21
840 17:45:48.643255 IRQ: Using dynamically assigned PCI IO-APIC IRQs
841 17:45:48.649736 WEAK: src/soc/intel/alderlake/fsp_params.c/mainboard_silicon_init_params called
842 17:45:48.828887 FSPS returned 0
843 17:45:48.831815 Executing Phase 1 of FspMultiPhaseSiInit
844 17:45:48.841893 FSP MultiPhaseSiInit src/soc/intel/alderlake/fsp_params.c/platform_fsp_multi_phase_init_cb called
845 17:45:48.845384 port C0 DISC req: usage 1 usb3 1 usb2 1
846 17:45:48.848587 Raw Buffer output 0 00000111
847 17:45:48.852065 Raw Buffer output 1 00000000
848 17:45:48.855750 pmc_send_ipc_cmd succeeded
849 17:45:48.862228 port C1 DISC req: usage 1 usb3 3 usb2 3
850 17:45:48.862811 Raw Buffer output 0 00000331
851 17:45:48.865419 Raw Buffer output 1 00000000
852 17:45:48.869897 pmc_send_ipc_cmd succeeded
853 17:45:48.873416 Detected 6 core, 8 thread CPU.
854 17:45:48.876931 Detected 6 core, 8 thread CPU.
855 17:45:48.882741 Detected 6 core, 8 thread CPU.
856 17:45:48.885437 Detected 6 core, 8 thread CPU.
857 17:45:48.888971 Detected 6 core, 8 thread CPU.
858 17:45:48.891798 Detected 6 core, 8 thread CPU.
859 17:45:48.895178 Detected 6 core, 8 thread CPU.
860 17:45:48.898768 Detected 6 core, 8 thread CPU.
861 17:45:48.902298 Detected 6 core, 8 thread CPU.
862 17:45:48.905755 Detected 6 core, 8 thread CPU.
863 17:45:48.908899 Detected 6 core, 8 thread CPU.
864 17:45:48.912061 Detected 6 core, 8 thread CPU.
865 17:45:48.915557 Detected 6 core, 8 thread CPU.
866 17:45:48.918961 Detected 6 core, 8 thread CPU.
867 17:45:48.922311 Detected 6 core, 8 thread CPU.
868 17:45:48.925512 Detected 6 core, 8 thread CPU.
869 17:45:48.929229 Detected 6 core, 8 thread CPU.
870 17:45:48.932217 Detected 6 core, 8 thread CPU.
871 17:45:48.935486 Detected 6 core, 8 thread CPU.
872 17:45:48.939027 Detected 6 core, 8 thread CPU.
873 17:45:48.942190 Detected 6 core, 8 thread CPU.
874 17:45:48.945394 Detected 6 core, 8 thread CPU.
875 17:45:49.225325 Detected 6 core, 8 thread CPU.
876 17:45:49.229281 Detected 6 core, 8 thread CPU.
877 17:45:49.231922 Detected 6 core, 8 thread CPU.
878 17:45:49.235618 Detected 6 core, 8 thread CPU.
879 17:45:49.238875 Detected 6 core, 8 thread CPU.
880 17:45:49.242043 Detected 6 core, 8 thread CPU.
881 17:45:49.245687 Detected 6 core, 8 thread CPU.
882 17:45:49.249028 Detected 6 core, 8 thread CPU.
883 17:45:49.251814 Detected 6 core, 8 thread CPU.
884 17:45:49.255250 Detected 6 core, 8 thread CPU.
885 17:45:49.258825 Detected 6 core, 8 thread CPU.
886 17:45:49.261953 Detected 6 core, 8 thread CPU.
887 17:45:49.265467 Detected 6 core, 8 thread CPU.
888 17:45:49.268425 Detected 6 core, 8 thread CPU.
889 17:45:49.272224 Detected 6 core, 8 thread CPU.
890 17:45:49.275549 Detected 6 core, 8 thread CPU.
891 17:45:49.278828 Detected 6 core, 8 thread CPU.
892 17:45:49.282393 Detected 6 core, 8 thread CPU.
893 17:45:49.285474 Detected 6 core, 8 thread CPU.
894 17:45:49.288803 Detected 6 core, 8 thread CPU.
895 17:45:49.289333 Display FSP Version Info HOB
896 17:45:49.292113 Reference Code - CPU = c.0.65.70
897 17:45:49.295282 uCode Version = 0.0.4.23
898 17:45:49.298294 TXT ACM version = ff.ff.ff.ffff
899 17:45:49.301976 Reference Code - ME = c.0.65.70
900 17:45:49.305622 MEBx version = 0.0.0.0
901 17:45:49.308641 ME Firmware Version = Lite SKU
902 17:45:49.311926 Reference Code - PCH = c.0.65.70
903 17:45:49.315233 PCH-CRID Status = Disabled
904 17:45:49.318504 PCH-CRID Original Value = ff.ff.ff.ffff
905 17:45:49.322037 PCH-CRID New Value = ff.ff.ff.ffff
906 17:45:49.325590 OPROM - RST - RAID = ff.ff.ff.ffff
907 17:45:49.328712 PCH Hsio Version = 4.0.0.0
908 17:45:49.332209 Reference Code - SA - System Agent = c.0.65.70
909 17:45:49.335254 Reference Code - MRC = 0.0.3.80
910 17:45:49.338687 SA - PCIe Version = c.0.65.70
911 17:45:49.341909 SA-CRID Status = Disabled
912 17:45:49.345189 SA-CRID Original Value = 0.0.0.4
913 17:45:49.348603 SA-CRID New Value = 0.0.0.4
914 17:45:49.351862 OPROM - VBIOS = ff.ff.ff.ffff
915 17:45:49.355163 IO Manageability Engine FW Version = 24.0.4.0
916 17:45:49.358805 PHY Build Version = 0.0.0.2016
917 17:45:49.362066 Thunderbolt(TM) FW Version = 0.0.0.0
918 17:45:49.368707 System Agent Manageability Engine FW Version = ff.ff.ff.ffff
919 17:45:49.375428 BS: BS_DEV_INIT_CHIPS run times (exec / console): 480 / 507 ms
920 17:45:49.378740 Enumerating buses...
921 17:45:49.381929 Show all devs... Before device enumeration.
922 17:45:49.385093 Root Device: enabled 1
923 17:45:49.385519 CPU_CLUSTER: 0: enabled 1
924 17:45:49.388584 DOMAIN: 0000: enabled 1
925 17:45:49.391928 GPIO: 0: enabled 1
926 17:45:49.392457 PCI: 00:00.0: enabled 1
927 17:45:49.395348 PCI: 00:01.0: enabled 0
928 17:45:49.398795 PCI: 00:01.1: enabled 0
929 17:45:49.401950 PCI: 00:02.0: enabled 1
930 17:45:49.402484 PCI: 00:04.0: enabled 1
931 17:45:49.405174 PCI: 00:05.0: enabled 0
932 17:45:49.408376 PCI: 00:06.0: enabled 1
933 17:45:49.412023 PCI: 00:06.2: enabled 0
934 17:45:49.412560 PCI: 00:07.0: enabled 0
935 17:45:49.415169 PCI: 00:07.1: enabled 0
936 17:45:49.418305 PCI: 00:07.2: enabled 0
937 17:45:49.421676 PCI: 00:07.3: enabled 0
938 17:45:49.422211 PCI: 00:08.0: enabled 0
939 17:45:49.425190 PCI: 00:09.0: enabled 0
940 17:45:49.428400 PCI: 00:0a.0: enabled 1
941 17:45:49.428934 PCI: 00:0d.0: enabled 1
942 17:45:49.431811 PCI: 00:0d.1: enabled 0
943 17:45:49.435159 PCI: 00:0d.2: enabled 0
944 17:45:49.438545 PCI: 00:0d.3: enabled 0
945 17:45:49.439145 PCI: 00:0e.0: enabled 0
946 17:45:49.441780 PCI: 00:10.0: enabled 0
947 17:45:49.444990 PCI: 00:10.1: enabled 0
948 17:45:49.448066 PCI: 00:10.6: enabled 0
949 17:45:49.448522 PCI: 00:10.7: enabled 0
950 17:45:49.451537 PCI: 00:12.0: enabled 0
951 17:45:49.455067 PCI: 00:12.6: enabled 0
952 17:45:49.458800 PCI: 00:12.7: enabled 0
953 17:45:49.459349 PCI: 00:13.0: enabled 0
954 17:45:49.461850 PCI: 00:14.0: enabled 1
955 17:45:49.465201 PCI: 00:14.1: enabled 0
956 17:45:49.465741 PCI: 00:14.2: enabled 1
957 17:45:49.468381 PCI: 00:14.3: enabled 1
958 17:45:49.471328 PCI: 00:15.0: enabled 1
959 17:45:49.475070 PCI: 00:15.1: enabled 1
960 17:45:49.475597 PCI: 00:15.2: enabled 0
961 17:45:49.478306 PCI: 00:15.3: enabled 1
962 17:45:49.481238 PCI: 00:16.0: enabled 1
963 17:45:49.485018 PCI: 00:16.1: enabled 0
964 17:45:49.485441 PCI: 00:16.2: enabled 0
965 17:45:49.488410 PCI: 00:16.3: enabled 0
966 17:45:49.491404 PCI: 00:16.4: enabled 0
967 17:45:49.495076 PCI: 00:16.5: enabled 0
968 17:45:49.495604 PCI: 00:17.0: enabled 1
969 17:45:49.498321 PCI: 00:19.0: enabled 0
970 17:45:49.501709 PCI: 00:19.1: enabled 1
971 17:45:49.505026 PCI: 00:19.2: enabled 0
972 17:45:49.505553 PCI: 00:1a.0: enabled 0
973 17:45:49.507870 PCI: 00:1c.0: enabled 0
974 17:45:49.511506 PCI: 00:1c.1: enabled 0
975 17:45:49.512034 PCI: 00:1c.2: enabled 0
976 17:45:49.514888 PCI: 00:1c.3: enabled 0
977 17:45:49.518564 PCI: 00:1c.4: enabled 0
978 17:45:49.521882 PCI: 00:1c.5: enabled 0
979 17:45:49.522410 PCI: 00:1c.6: enabled 0
980 17:45:49.525103 PCI: 00:1c.7: enabled 0
981 17:45:49.528086 PCI: 00:1d.0: enabled 0
982 17:45:49.531084 PCI: 00:1d.1: enabled 0
983 17:45:49.531511 PCI: 00:1d.2: enabled 0
984 17:45:49.534419 PCI: 00:1d.3: enabled 0
985 17:45:49.538512 PCI: 00:1e.0: enabled 1
986 17:45:49.541646 PCI: 00:1e.1: enabled 0
987 17:45:49.542172 PCI: 00:1e.2: enabled 0
988 17:45:49.544460 PCI: 00:1e.3: enabled 1
989 17:45:49.547731 PCI: 00:1f.0: enabled 1
990 17:45:49.548157 PCI: 00:1f.1: enabled 0
991 17:45:49.551376 PCI: 00:1f.2: enabled 1
992 17:45:49.554516 PCI: 00:1f.3: enabled 1
993 17:45:49.557996 PCI: 00:1f.4: enabled 0
994 17:45:49.558520 PCI: 00:1f.5: enabled 1
995 17:45:49.561624 PCI: 00:1f.6: enabled 0
996 17:45:49.564729 PCI: 00:1f.7: enabled 0
997 17:45:49.568010 GENERIC: 0.0: enabled 1
998 17:45:49.568539 GENERIC: 0.0: enabled 1
999 17:45:49.571389 GENERIC: 1.0: enabled 1
1000 17:45:49.574667 GENERIC: 0.0: enabled 1
1001 17:45:49.577959 GENERIC: 1.0: enabled 1
1002 17:45:49.578486 USB0 port 0: enabled 1
1003 17:45:49.581209 USB0 port 0: enabled 1
1004 17:45:49.584411 GENERIC: 0.0: enabled 1
1005 17:45:49.584838 I2C: 00:1a: enabled 1
1006 17:45:49.587922 I2C: 00:31: enabled 1
1007 17:45:49.591198 I2C: 00:32: enabled 1
1008 17:45:49.591627 I2C: 00:50: enabled 1
1009 17:45:49.594329 I2C: 00:10: enabled 1
1010 17:45:49.597806 I2C: 00:15: enabled 1
1011 17:45:49.598339 I2C: 00:2c: enabled 1
1012 17:45:49.601325 GENERIC: 0.0: enabled 1
1013 17:45:49.604515 SPI: 00: enabled 1
1014 17:45:49.605049 PNP: 0c09.0: enabled 1
1015 17:45:49.607677 GENERIC: 0.0: enabled 1
1016 17:45:49.611241 USB3 port 0: enabled 1
1017 17:45:49.614635 USB3 port 1: enabled 0
1018 17:45:49.615169 USB3 port 2: enabled 1
1019 17:45:49.618048 USB3 port 3: enabled 0
1020 17:45:49.621298 USB2 port 0: enabled 1
1021 17:45:49.621832 USB2 port 1: enabled 0
1022 17:45:49.624538 USB2 port 2: enabled 1
1023 17:45:49.627933 USB2 port 3: enabled 0
1024 17:45:49.630927 USB2 port 4: enabled 0
1025 17:45:49.631483 USB2 port 5: enabled 1
1026 17:45:49.634625 USB2 port 6: enabled 0
1027 17:45:49.637876 USB2 port 7: enabled 0
1028 17:45:49.638403 USB2 port 8: enabled 1
1029 17:45:49.641085 USB2 port 9: enabled 1
1030 17:45:49.644276 USB3 port 0: enabled 1
1031 17:45:49.644700 USB3 port 1: enabled 0
1032 17:45:49.647601 USB3 port 2: enabled 0
1033 17:45:49.651130 USB3 port 3: enabled 0
1034 17:45:49.654487 GENERIC: 0.0: enabled 1
1035 17:45:49.654943 GENERIC: 1.0: enabled 1
1036 17:45:49.658075 APIC: 00: enabled 1
1037 17:45:49.661307 APIC: 16: enabled 1
1038 17:45:49.661831 APIC: 10: enabled 1
1039 17:45:49.664384 APIC: 12: enabled 1
1040 17:45:49.664915 APIC: 14: enabled 1
1041 17:45:49.667548 APIC: 09: enabled 1
1042 17:45:49.670753 APIC: 08: enabled 1
1043 17:45:49.671176 APIC: 01: enabled 1
1044 17:45:49.674424 Compare with tree...
1045 17:45:49.677959 Root Device: enabled 1
1046 17:45:49.680497 CPU_CLUSTER: 0: enabled 1
1047 17:45:49.680950 APIC: 00: enabled 1
1048 17:45:49.684171 APIC: 16: enabled 1
1049 17:45:49.687437 APIC: 10: enabled 1
1050 17:45:49.687965 APIC: 12: enabled 1
1051 17:45:49.690991 APIC: 14: enabled 1
1052 17:45:49.694056 APIC: 09: enabled 1
1053 17:45:49.694616 APIC: 08: enabled 1
1054 17:45:49.697069 APIC: 01: enabled 1
1055 17:45:49.700745 DOMAIN: 0000: enabled 1
1056 17:45:49.701320 GPIO: 0: enabled 1
1057 17:45:49.703724 PCI: 00:00.0: enabled 1
1058 17:45:49.707544 PCI: 00:01.0: enabled 0
1059 17:45:49.710440 PCI: 00:01.1: enabled 0
1060 17:45:49.713897 PCI: 00:02.0: enabled 1
1061 17:45:49.714429 PCI: 00:04.0: enabled 1
1062 17:45:49.717169 GENERIC: 0.0: enabled 1
1063 17:45:49.720534 PCI: 00:05.0: enabled 0
1064 17:45:49.723736 PCI: 00:06.0: enabled 1
1065 17:45:49.727175 PCI: 00:06.2: enabled 0
1066 17:45:49.727706 PCI: 00:08.0: enabled 0
1067 17:45:49.730355 PCI: 00:09.0: enabled 0
1068 17:45:49.733399 PCI: 00:0a.0: enabled 1
1069 17:45:49.737459 PCI: 00:0d.0: enabled 1
1070 17:45:49.740377 USB0 port 0: enabled 1
1071 17:45:49.740810 USB3 port 0: enabled 1
1072 17:45:49.743872 USB3 port 1: enabled 0
1073 17:45:49.746814 USB3 port 2: enabled 1
1074 17:45:49.749943 USB3 port 3: enabled 0
1075 17:45:49.753554 PCI: 00:0d.1: enabled 0
1076 17:45:49.757101 PCI: 00:0d.2: enabled 0
1077 17:45:49.757636 PCI: 00:0d.3: enabled 0
1078 17:45:49.760293 PCI: 00:0e.0: enabled 0
1079 17:45:49.763290 PCI: 00:10.0: enabled 0
1080 17:45:49.767099 PCI: 00:10.1: enabled 0
1081 17:45:49.767635 PCI: 00:10.6: enabled 0
1082 17:45:49.769943 PCI: 00:10.7: enabled 0
1083 17:45:49.773383 PCI: 00:12.0: enabled 0
1084 17:45:49.776938 PCI: 00:12.6: enabled 0
1085 17:45:49.780220 PCI: 00:12.7: enabled 0
1086 17:45:49.780752 PCI: 00:13.0: enabled 0
1087 17:45:49.783175 PCI: 00:14.0: enabled 1
1088 17:45:49.787018 USB0 port 0: enabled 1
1089 17:45:49.790069 USB2 port 0: enabled 1
1090 17:45:49.793475 USB2 port 1: enabled 0
1091 17:45:49.796740 USB2 port 2: enabled 1
1092 17:45:49.797275 USB2 port 3: enabled 0
1093 17:45:49.799731 USB2 port 4: enabled 0
1094 17:45:49.803166 USB2 port 5: enabled 1
1095 17:45:49.806811 USB2 port 6: enabled 0
1096 17:45:49.810041 USB2 port 7: enabled 0
1097 17:45:49.810575 USB2 port 8: enabled 1
1098 17:45:49.813302 USB2 port 9: enabled 1
1099 17:45:49.816491 USB3 port 0: enabled 1
1100 17:45:49.819417 USB3 port 1: enabled 0
1101 17:45:49.822722 USB3 port 2: enabled 0
1102 17:45:49.826401 USB3 port 3: enabled 0
1103 17:45:49.826976 PCI: 00:14.1: enabled 0
1104 17:45:49.829722 PCI: 00:14.2: enabled 1
1105 17:45:49.832694 PCI: 00:14.3: enabled 1
1106 17:45:49.836048 GENERIC: 0.0: enabled 1
1107 17:45:49.839737 PCI: 00:15.0: enabled 1
1108 17:45:49.840167 I2C: 00:1a: enabled 1
1109 17:45:49.842785 I2C: 00:31: enabled 1
1110 17:45:49.846395 I2C: 00:32: enabled 1
1111 17:45:49.849251 PCI: 00:15.1: enabled 1
1112 17:45:49.852830 I2C: 00:50: enabled 1
1113 17:45:49.853258 PCI: 00:15.2: enabled 0
1114 17:45:49.855801 PCI: 00:15.3: enabled 1
1115 17:45:49.859382 I2C: 00:10: enabled 1
1116 17:45:49.862652 PCI: 00:16.0: enabled 1
1117 17:45:49.863086 PCI: 00:16.1: enabled 0
1118 17:45:49.865926 PCI: 00:16.2: enabled 0
1119 17:45:49.869459 PCI: 00:16.3: enabled 0
1120 17:45:49.872512 PCI: 00:16.4: enabled 0
1121 17:45:49.876086 PCI: 00:16.5: enabled 0
1122 17:45:49.876615 PCI: 00:17.0: enabled 1
1123 17:45:49.879301 PCI: 00:19.0: enabled 0
1124 17:45:49.882391 PCI: 00:19.1: enabled 1
1125 17:45:49.886057 I2C: 00:15: enabled 1
1126 17:45:49.889445 I2C: 00:2c: enabled 1
1127 17:45:49.889973 PCI: 00:19.2: enabled 0
1128 17:45:49.892172 PCI: 00:1a.0: enabled 0
1129 17:45:49.895618 PCI: 00:1e.0: enabled 1
1130 17:45:49.899099 PCI: 00:1e.1: enabled 0
1131 17:45:49.902128 PCI: 00:1e.2: enabled 0
1132 17:45:49.902560 PCI: 00:1e.3: enabled 1
1133 17:45:49.906201 SPI: 00: enabled 1
1134 17:45:49.909891 PCI: 00:1f.0: enabled 1
1135 17:45:49.912659 PNP: 0c09.0: enabled 1
1136 17:45:49.913188 PCI: 00:1f.1: enabled 0
1137 17:45:49.915937 PCI: 00:1f.2: enabled 1
1138 17:45:49.918922 GENERIC: 0.0: enabled 1
1139 17:45:49.921975 GENERIC: 0.0: enabled 1
1140 17:45:49.925854 GENERIC: 1.0: enabled 1
1141 17:45:49.929144 PCI: 00:1f.3: enabled 1
1142 17:45:49.929678 PCI: 00:1f.4: enabled 0
1143 17:45:49.932122 PCI: 00:1f.5: enabled 1
1144 17:45:49.935246 PCI: 00:1f.6: enabled 0
1145 17:45:49.939144 PCI: 00:1f.7: enabled 0
1146 17:45:49.939709 Root Device scanning...
1147 17:45:49.942109 scan_static_bus for Root Device
1148 17:45:49.945391 CPU_CLUSTER: 0 enabled
1149 17:45:49.948519 DOMAIN: 0000 enabled
1150 17:45:49.951589 DOMAIN: 0000 scanning...
1151 17:45:49.952019 PCI: pci_scan_bus for bus 00
1152 17:45:49.955516 PCI: 00:00.0 [8086/0000] ops
1153 17:45:49.958634 PCI: 00:00.0 [8086/4609] enabled
1154 17:45:49.962167 PCI: 00:02.0 [8086/0000] bus ops
1155 17:45:49.965535 PCI: 00:02.0 [8086/46b3] enabled
1156 17:45:49.968892 PCI: 00:04.0 [8086/0000] bus ops
1157 17:45:49.972154 PCI: 00:04.0 [8086/461d] enabled
1158 17:45:49.975523 PCI: 00:06.0 [8086/0000] bus ops
1159 17:45:49.978837 PCI: 00:06.0 [8086/464d] enabled
1160 17:45:49.985373 PCI: 00:08.0 [8086/464f] disabled
1161 17:45:49.988298 PCI: 00:0a.0 [8086/467d] enabled
1162 17:45:49.991664 PCI: 00:0d.0 [8086/0000] bus ops
1163 17:45:49.995152 PCI: 00:0d.0 [8086/461e] enabled
1164 17:45:49.998385 PCI: 00:14.0 [8086/0000] bus ops
1165 17:45:50.001940 PCI: 00:14.0 [8086/51ed] enabled
1166 17:45:50.005101 PCI: 00:14.2 [8086/51ef] enabled
1167 17:45:50.008260 PCI: 00:14.3 [8086/0000] bus ops
1168 17:45:50.011972 PCI: 00:14.3 [8086/51f0] enabled
1169 17:45:50.014650 PCI: 00:15.0 [8086/0000] bus ops
1170 17:45:50.018421 PCI: 00:15.0 [8086/51e8] enabled
1171 17:45:50.021221 PCI: 00:15.1 [8086/0000] bus ops
1172 17:45:50.025016 PCI: 00:15.1 [8086/51e9] enabled
1173 17:45:50.028118 PCI: 00:15.2 [8086/0000] bus ops
1174 17:45:50.031531 PCI: 00:15.2 [8086/51ea] disabled
1175 17:45:50.034681 PCI: 00:15.3 [8086/0000] bus ops
1176 17:45:50.038409 PCI: 00:15.3 [8086/51eb] enabled
1177 17:45:50.041327 PCI: 00:16.0 [8086/0000] ops
1178 17:45:50.044482 PCI: 00:16.0 [8086/51e0] enabled
1179 17:45:50.051466 PCI: Static device PCI: 00:17.0 not found, disabling it.
1180 17:45:50.055006 PCI: 00:19.0 [8086/0000] bus ops
1181 17:45:50.058186 PCI: 00:19.0 [8086/51c5] disabled
1182 17:45:50.061563 PCI: 00:19.1 [8086/0000] bus ops
1183 17:45:50.064710 PCI: 00:19.1 [8086/51c6] enabled
1184 17:45:50.068365 PCI: 00:1e.0 [8086/0000] ops
1185 17:45:50.071259 PCI: 00:1e.0 [8086/51a8] enabled
1186 17:45:50.074607 PCI: 00:1e.3 [8086/0000] bus ops
1187 17:45:50.078256 PCI: 00:1e.3 [8086/51ab] enabled
1188 17:45:50.081416 PCI: 00:1f.0 [8086/0000] bus ops
1189 17:45:50.084854 PCI: 00:1f.0 [8086/5182] enabled
1190 17:45:50.085381 RTC Init
1191 17:45:50.087790 Set power on after power failure.
1192 17:45:50.091279 Disabling Deep S3
1193 17:45:50.091800 Disabling Deep S3
1194 17:45:50.094719 Disabling Deep S4
1195 17:45:50.097578 Disabling Deep S4
1196 17:45:50.098092 Disabling Deep S5
1197 17:45:50.101259 Disabling Deep S5
1198 17:45:50.104314 PCI: 00:1f.2 [0000/0000] hidden
1199 17:45:50.107703 PCI: 00:1f.3 [8086/0000] bus ops
1200 17:45:50.111265 PCI: 00:1f.3 [8086/51c8] enabled
1201 17:45:50.114802 PCI: 00:1f.5 [8086/0000] bus ops
1202 17:45:50.117704 PCI: 00:1f.5 [8086/51a4] enabled
1203 17:45:50.118136 GPIO: 0 enabled
1204 17:45:50.121341 PCI: Leftover static devices:
1205 17:45:50.121868 PCI: 00:01.0
1206 17:45:50.124804 PCI: 00:01.1
1207 17:45:50.125326 PCI: 00:05.0
1208 17:45:50.127860 PCI: 00:06.2
1209 17:45:50.128379 PCI: 00:09.0
1210 17:45:50.131192 PCI: 00:0d.1
1211 17:45:50.131619 PCI: 00:0d.2
1212 17:45:50.131955 PCI: 00:0d.3
1213 17:45:50.134497 PCI: 00:0e.0
1214 17:45:50.135119 PCI: 00:10.0
1215 17:45:50.137927 PCI: 00:10.1
1216 17:45:50.138447 PCI: 00:10.6
1217 17:45:50.138847 PCI: 00:10.7
1218 17:45:50.140917 PCI: 00:12.0
1219 17:45:50.141343 PCI: 00:12.6
1220 17:45:50.144169 PCI: 00:12.7
1221 17:45:50.144644 PCI: 00:13.0
1222 17:45:50.144986 PCI: 00:14.1
1223 17:45:50.147690 PCI: 00:16.1
1224 17:45:50.148117 PCI: 00:16.2
1225 17:45:50.151017 PCI: 00:16.3
1226 17:45:50.151442 PCI: 00:16.4
1227 17:45:50.154216 PCI: 00:16.5
1228 17:45:50.154721 PCI: 00:17.0
1229 17:45:50.155058 PCI: 00:19.2
1230 17:45:50.157633 PCI: 00:1a.0
1231 17:45:50.158048 PCI: 00:1e.1
1232 17:45:50.161313 PCI: 00:1e.2
1233 17:45:50.161887 PCI: 00:1f.1
1234 17:45:50.162233 PCI: 00:1f.4
1235 17:45:50.164311 PCI: 00:1f.6
1236 17:45:50.164728 PCI: 00:1f.7
1237 17:45:50.167366 PCI: Check your devicetree.cb.
1238 17:45:50.171192 PCI: 00:02.0 scanning...
1239 17:45:50.174035 scan_generic_bus for PCI: 00:02.0
1240 17:45:50.177976 scan_generic_bus for PCI: 00:02.0 done
1241 17:45:50.184269 scan_bus: bus PCI: 00:02.0 finished in 7 msecs
1242 17:45:50.184807 PCI: 00:04.0 scanning...
1243 17:45:50.187977 scan_generic_bus for PCI: 00:04.0
1244 17:45:50.191446 GENERIC: 0.0 enabled
1245 17:45:50.197656 bus: PCI: 00:04.0[0]->scan_generic_bus for PCI: 00:04.0 done
1246 17:45:50.200981 scan_bus: bus PCI: 00:04.0 finished in 11 msecs
1247 17:45:50.204106 PCI: 00:06.0 scanning...
1248 17:45:50.207394 do_pci_scan_bridge for PCI: 00:06.0
1249 17:45:50.210880 PCI: pci_scan_bus for bus 01
1250 17:45:50.214728 PCI: 01:00.0 [15b7/5009] enabled
1251 17:45:50.217968 Enabling Common Clock Configuration
1252 17:45:50.220901 L1 Sub-State supported from root port 6
1253 17:45:50.224414 L1 Sub-State Support = 0x5
1254 17:45:50.227515 CommonModeRestoreTime = 0x6e
1255 17:45:50.230802 Power On Value = 0x5, Power On Scale = 0x2
1256 17:45:50.234171 ASPM: Enabled L1
1257 17:45:50.237575 PCIe: Max_Payload_Size adjusted to 256
1258 17:45:50.240622 PCI: 01:00.0: Enabled LTR
1259 17:45:50.243837 PCI: 01:00.0: Programmed LTR max latencies
1260 17:45:50.250921 scan_bus: bus PCI: 00:06.0 finished in 40 msecs
1261 17:45:50.251353 PCI: 00:0d.0 scanning...
1262 17:45:50.254216 scan_static_bus for PCI: 00:0d.0
1263 17:45:50.257164 USB0 port 0 enabled
1264 17:45:50.260627 USB0 port 0 scanning...
1265 17:45:50.264296 scan_static_bus for USB0 port 0
1266 17:45:50.264823 USB3 port 0 enabled
1267 17:45:50.267424 USB3 port 1 disabled
1268 17:45:50.270740 USB3 port 2 enabled
1269 17:45:50.271170 USB3 port 3 disabled
1270 17:45:50.273773 USB3 port 0 scanning...
1271 17:45:50.277167 scan_static_bus for USB3 port 0
1272 17:45:50.280802 scan_static_bus for USB3 port 0 done
1273 17:45:50.283760 scan_bus: bus USB3 port 0 finished in 6 msecs
1274 17:45:50.287242 USB3 port 2 scanning...
1275 17:45:50.290554 scan_static_bus for USB3 port 2
1276 17:45:50.293795 scan_static_bus for USB3 port 2 done
1277 17:45:50.301101 scan_bus: bus USB3 port 2 finished in 6 msecs
1278 17:45:50.303683 scan_static_bus for USB0 port 0 done
1279 17:45:50.307464 scan_bus: bus USB0 port 0 finished in 43 msecs
1280 17:45:50.310276 scan_static_bus for PCI: 00:0d.0 done
1281 17:45:50.317326 scan_bus: bus PCI: 00:0d.0 finished in 59 msecs
1282 17:45:50.320668 PCI: 00:14.0 scanning...
1283 17:45:50.324233 scan_static_bus for PCI: 00:14.0
1284 17:45:50.324754 USB0 port 0 enabled
1285 17:45:50.327500 USB0 port 0 scanning...
1286 17:45:50.330787 scan_static_bus for USB0 port 0
1287 17:45:50.331309 USB2 port 0 enabled
1288 17:45:50.334313 USB2 port 1 disabled
1289 17:45:50.337318 USB2 port 2 enabled
1290 17:45:50.337837 USB2 port 3 disabled
1291 17:45:50.341057 USB2 port 4 disabled
1292 17:45:50.343437 USB2 port 5 enabled
1293 17:45:50.343869 USB2 port 6 disabled
1294 17:45:50.347101 USB2 port 7 disabled
1295 17:45:50.350334 USB2 port 8 enabled
1296 17:45:50.350798 USB2 port 9 enabled
1297 17:45:50.353494 USB3 port 0 enabled
1298 17:45:50.353865 USB3 port 1 disabled
1299 17:45:50.356811 USB3 port 2 disabled
1300 17:45:50.360524 USB3 port 3 disabled
1301 17:45:50.360948 USB2 port 0 scanning...
1302 17:45:50.364142 scan_static_bus for USB2 port 0
1303 17:45:50.370646 scan_static_bus for USB2 port 0 done
1304 17:45:50.374154 scan_bus: bus USB2 port 0 finished in 6 msecs
1305 17:45:50.377218 USB2 port 2 scanning...
1306 17:45:50.380117 scan_static_bus for USB2 port 2
1307 17:45:50.383460 scan_static_bus for USB2 port 2 done
1308 17:45:50.387091 scan_bus: bus USB2 port 2 finished in 6 msecs
1309 17:45:50.390723 USB2 port 5 scanning...
1310 17:45:50.393596 scan_static_bus for USB2 port 5
1311 17:45:50.397000 scan_static_bus for USB2 port 5 done
1312 17:45:50.400102 scan_bus: bus USB2 port 5 finished in 6 msecs
1313 17:45:50.403622 USB2 port 8 scanning...
1314 17:45:50.406560 scan_static_bus for USB2 port 8
1315 17:45:50.410468 scan_static_bus for USB2 port 8 done
1316 17:45:50.416956 scan_bus: bus USB2 port 8 finished in 6 msecs
1317 17:45:50.417482 USB2 port 9 scanning...
1318 17:45:50.420020 scan_static_bus for USB2 port 9
1319 17:45:50.423725 scan_static_bus for USB2 port 9 done
1320 17:45:50.430311 scan_bus: bus USB2 port 9 finished in 6 msecs
1321 17:45:50.430885 USB3 port 0 scanning...
1322 17:45:50.433343 scan_static_bus for USB3 port 0
1323 17:45:50.440330 scan_static_bus for USB3 port 0 done
1324 17:45:50.443399 scan_bus: bus USB3 port 0 finished in 6 msecs
1325 17:45:50.446661 scan_static_bus for USB0 port 0 done
1326 17:45:50.453639 scan_bus: bus USB0 port 0 finished in 120 msecs
1327 17:45:50.456622 scan_static_bus for PCI: 00:14.0 done
1328 17:45:50.459680 scan_bus: bus PCI: 00:14.0 finished in 136 msecs
1329 17:45:50.463122 PCI: 00:14.3 scanning...
1330 17:45:50.466718 scan_static_bus for PCI: 00:14.3
1331 17:45:50.470218 GENERIC: 0.0 enabled
1332 17:45:50.473102 scan_static_bus for PCI: 00:14.3 done
1333 17:45:50.476529 scan_bus: bus PCI: 00:14.3 finished in 9 msecs
1334 17:45:50.479866 PCI: 00:15.0 scanning...
1335 17:45:50.483064 scan_static_bus for PCI: 00:15.0
1336 17:45:50.483507 I2C: 00:1a enabled
1337 17:45:50.486447 I2C: 00:31 enabled
1338 17:45:50.489602 I2C: 00:32 enabled
1339 17:45:50.493173 scan_static_bus for PCI: 00:15.0 done
1340 17:45:50.496358 scan_bus: bus PCI: 00:15.0 finished in 13 msecs
1341 17:45:50.499588 PCI: 00:15.1 scanning...
1342 17:45:50.503080 scan_static_bus for PCI: 00:15.1
1343 17:45:50.506722 I2C: 00:50 enabled
1344 17:45:50.509754 scan_static_bus for PCI: 00:15.1 done
1345 17:45:50.513180 scan_bus: bus PCI: 00:15.1 finished in 9 msecs
1346 17:45:50.516369 PCI: 00:15.3 scanning...
1347 17:45:50.519773 scan_static_bus for PCI: 00:15.3
1348 17:45:50.522843 I2C: 00:10 enabled
1349 17:45:50.526670 scan_static_bus for PCI: 00:15.3 done
1350 17:45:50.529653 scan_bus: bus PCI: 00:15.3 finished in 9 msecs
1351 17:45:50.533160 PCI: 00:19.1 scanning...
1352 17:45:50.536043 scan_static_bus for PCI: 00:19.1
1353 17:45:50.536474 I2C: 00:15 enabled
1354 17:45:50.539778 I2C: 00:2c enabled
1355 17:45:50.543204 scan_static_bus for PCI: 00:19.1 done
1356 17:45:50.549871 scan_bus: bus PCI: 00:19.1 finished in 11 msecs
1357 17:45:50.550397 PCI: 00:1e.3 scanning...
1358 17:45:50.553236 scan_generic_bus for PCI: 00:1e.3
1359 17:45:50.556275 SPI: 00 enabled
1360 17:45:50.562992 bus: PCI: 00:1e.3[0]->scan_generic_bus for PCI: 00:1e.3 done
1361 17:45:50.566072 scan_bus: bus PCI: 00:1e.3 finished in 11 msecs
1362 17:45:50.569675 PCI: 00:1f.0 scanning...
1363 17:45:50.572821 scan_static_bus for PCI: 00:1f.0
1364 17:45:50.576419 PNP: 0c09.0 enabled
1365 17:45:50.576946 PNP: 0c09.0 scanning...
1366 17:45:50.579408 scan_static_bus for PNP: 0c09.0
1367 17:45:50.582836 scan_static_bus for PNP: 0c09.0 done
1368 17:45:50.589667 scan_bus: bus PNP: 0c09.0 finished in 6 msecs
1369 17:45:50.592839 scan_static_bus for PCI: 00:1f.0 done
1370 17:45:50.595990 scan_bus: bus PCI: 00:1f.0 finished in 23 msecs
1371 17:45:50.599357 PCI: 00:1f.2 scanning...
1372 17:45:50.602874 scan_static_bus for PCI: 00:1f.2
1373 17:45:50.606054 GENERIC: 0.0 enabled
1374 17:45:50.609255 GENERIC: 0.0 scanning...
1375 17:45:50.612954 scan_static_bus for GENERIC: 0.0
1376 17:45:50.613484 GENERIC: 0.0 enabled
1377 17:45:50.616008 GENERIC: 1.0 enabled
1378 17:45:50.619094 scan_static_bus for GENERIC: 0.0 done
1379 17:45:50.622615 scan_bus: bus GENERIC: 0.0 finished in 11 msecs
1380 17:45:50.629238 scan_static_bus for PCI: 00:1f.2 done
1381 17:45:50.632755 scan_bus: bus PCI: 00:1f.2 finished in 27 msecs
1382 17:45:50.636110 PCI: 00:1f.3 scanning...
1383 17:45:50.639211 scan_static_bus for PCI: 00:1f.3
1384 17:45:50.642483 scan_static_bus for PCI: 00:1f.3 done
1385 17:45:50.645670 scan_bus: bus PCI: 00:1f.3 finished in 7 msecs
1386 17:45:50.648919 PCI: 00:1f.5 scanning...
1387 17:45:50.652749 scan_generic_bus for PCI: 00:1f.5
1388 17:45:50.655694 scan_generic_bus for PCI: 00:1f.5 done
1389 17:45:50.662706 scan_bus: bus PCI: 00:1f.5 finished in 7 msecs
1390 17:45:50.665807 scan_bus: bus DOMAIN: 0000 finished in 710 msecs
1391 17:45:50.669238 scan_static_bus for Root Device done
1392 17:45:50.675603 scan_bus: bus Root Device finished in 729 msecs
1393 17:45:50.676033 done
1394 17:45:50.682713 BS: BS_DEV_ENUMERATE run times (exec / console): 3 / 1297 ms
1395 17:45:50.685980 FMAP: area UNIFIED_MRC_CACHE found @ f00000 (131072 bytes)
1396 17:45:50.692504 SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
1397 17:45:50.695918 SPI flash protection: WPSW=0 SRP0=0
1398 17:45:50.702568 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
1399 17:45:50.708826 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 20 ms
1400 17:45:50.709337 found VGA at PCI: 00:02.0
1401 17:45:50.712266 Setting up VGA for PCI: 00:02.0
1402 17:45:50.719103 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
1403 17:45:50.722219 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
1404 17:45:50.726023 Allocating resources...
1405 17:45:50.729318 Reading resources...
1406 17:45:50.732652 Root Device read_resources bus 0 link: 0
1407 17:45:50.735662 CPU_CLUSTER: 0 read_resources bus 0 link: 0
1408 17:45:50.742663 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
1409 17:45:50.745427 DOMAIN: 0000 read_resources bus 0 link: 0
1410 17:45:50.752782 SA MMIO resource: MCHBAR -> base = 0xfedc0000, size = 0x20000
1411 17:45:50.758739 SA MMIO resource: DMIBAR -> base = 0xfeda0000, size = 0x1000
1412 17:45:50.765591 SA MMIO resource: EPBAR -> base = 0xfeda1000, size = 0x1000
1413 17:45:50.772052 SA MMIO resource: REGBAR -> base = 0xfb000000, size = 0x1000
1414 17:45:50.775296 SA MMIO resource: EDRAMBAR -> base = 0xfed80000, size = 0x4000
1415 17:45:50.782334 SA MMIO resource: CRAB_ABORT -> base = 0xfeb00000, size = 0x80000
1416 17:45:50.788952 SA MMIO resource: TPM -> base = 0xfed40000, size = 0x10000
1417 17:45:50.795279 SA MMIO resource: LT_SECURITY -> base = 0xfed50000, size = 0x20000
1418 17:45:50.802374 SA MMIO resource: APIC -> base = 0xfec00000, size = 0x100000
1419 17:45:50.808500 SA MMIO resource: PCH_RESERVED -> base = 0xfc800000, size = 0x2000000
1420 17:45:50.815266 SA MMIO resource: GFXVTBAR -> base = 0xfed90000, size = 0x1000
1421 17:45:50.822092 SA MMIO resource: IPUVTBAR -> base = 0xfed92000, size = 0x1000
1422 17:45:50.828725 SA MMIO resource: TBT0BAR -> base = 0xfed84000, size = 0x1000
1423 17:45:50.835543 SA MMIO resource: TBT1BAR -> base = 0xfed85000, size = 0x1000
1424 17:45:50.842285 SA MMIO resource: TBT2BAR -> base = 0xfed86000, size = 0x1000
1425 17:45:50.848449 SA MMIO resource: TBT3BAR -> base = 0xfed87000, size = 0x1000
1426 17:45:50.854790 SA MMIO resource: VTVC0BAR -> base = 0xfed91000, size = 0x1000
1427 17:45:50.857957 SA MMIO resource: MMCONF -> base = 0xc0000000, size = 0x10000000
1428 17:45:50.865415 SA MMIO resource: DSM -> base = 0x7c800000, size = 0x3c00000
1429 17:45:50.871460 SA MMIO resource: TSEG -> base = 0x7b800000, size = 0x800000
1430 17:45:50.878453 SA MMIO resource: GSM -> base = 0x7c000000, size = 0x800000
1431 17:45:50.881548 PCI: 00:04.0 read_resources bus 1 link: 0
1432 17:45:50.888059 PCI: 00:04.0 read_resources bus 1 link: 0 done
1433 17:45:50.891550 PCI: 00:06.0 read_resources bus 1 link: 0
1434 17:45:50.895029 PCI: 00:06.0 read_resources bus 1 link: 0 done
1435 17:45:50.901875 PCI: 00:0d.0 read_resources bus 0 link: 0
1436 17:45:50.904721 USB0 port 0 read_resources bus 0 link: 0
1437 17:45:50.907619 USB0 port 0 read_resources bus 0 link: 0 done
1438 17:45:50.914502 PCI: 00:0d.0 read_resources bus 0 link: 0 done
1439 17:45:50.917482 PCI: 00:14.0 read_resources bus 0 link: 0
1440 17:45:50.921133 USB0 port 0 read_resources bus 0 link: 0
1441 17:45:50.927653 USB0 port 0 read_resources bus 0 link: 0 done
1442 17:45:50.931136 PCI: 00:14.0 read_resources bus 0 link: 0 done
1443 17:45:50.934053 PCI: 00:14.3 read_resources bus 0 link: 0
1444 17:45:50.940999 PCI: 00:14.3 read_resources bus 0 link: 0 done
1445 17:45:50.944347 PCI: 00:15.0 read_resources bus 0 link: 0
1446 17:45:50.950899 PCI: 00:15.0 read_resources bus 0 link: 0 done
1447 17:45:50.953918 PCI: 00:15.1 read_resources bus 0 link: 0
1448 17:45:50.957471 PCI: 00:15.1 read_resources bus 0 link: 0 done
1449 17:45:50.963987 PCI: 00:15.3 read_resources bus 0 link: 0
1450 17:45:50.967195 PCI: 00:15.3 read_resources bus 0 link: 0 done
1451 17:45:50.970541 PCI: 00:19.1 read_resources bus 0 link: 0
1452 17:45:50.977755 PCI: 00:19.1 read_resources bus 0 link: 0 done
1453 17:45:50.980780 PCI: 00:1e.3 read_resources bus 2 link: 0
1454 17:45:50.987051 PCI: 00:1e.3 read_resources bus 2 link: 0 done
1455 17:45:50.990338 PCI: 00:1f.0 read_resources bus 0 link: 0
1456 17:45:50.993975 PCI: 00:1f.0 read_resources bus 0 link: 0 done
1457 17:45:50.997369 PCI: 00:1f.2 read_resources bus 0 link: 0
1458 17:45:51.004346 GENERIC: 0.0 read_resources bus 0 link: 0
1459 17:45:51.007430 GENERIC: 0.0 read_resources bus 0 link: 0 done
1460 17:45:51.014102 PCI: 00:1f.2 read_resources bus 0 link: 0 done
1461 17:45:51.017547 DOMAIN: 0000 read_resources bus 0 link: 0 done
1462 17:45:51.023922 Root Device read_resources bus 0 link: 0 done
1463 17:45:51.024427 Done reading resources.
1464 17:45:51.030515 Show resources in subtree (Root Device)...After reading.
1465 17:45:51.033628 Root Device child on link 0 CPU_CLUSTER: 0
1466 17:45:51.040746 CPU_CLUSTER: 0 child on link 0 APIC: 00
1467 17:45:51.041265 APIC: 00
1468 17:45:51.041605 APIC: 16
1469 17:45:51.043976 APIC: 10
1470 17:45:51.044402 APIC: 12
1471 17:45:51.044737 APIC: 14
1472 17:45:51.046938 APIC: 09
1473 17:45:51.047481 APIC: 08
1474 17:45:51.050076 APIC: 01
1475 17:45:51.053481 DOMAIN: 0000 child on link 0 GPIO: 0
1476 17:45:51.063634 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1477 17:45:51.073574 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100
1478 17:45:51.074002 GPIO: 0
1479 17:45:51.074342 PCI: 00:00.0
1480 17:45:51.083537 PCI: 00:00.0 resource base fedc0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 0
1481 17:45:51.094014 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 1
1482 17:45:51.103731 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1483 17:45:51.113652 PCI: 00:00.0 resource base fb000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1484 17:45:51.123215 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 4
1485 17:45:51.129978 PCI: 00:00.0 resource base feb00000 size 80000 align 0 gran 0 limit 0 flags f0000200 index 5
1486 17:45:51.139693 PCI: 00:00.0 resource base fed40000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 6
1487 17:45:51.149789 PCI: 00:00.0 resource base fed50000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 7
1488 17:45:51.159785 PCI: 00:00.0 resource base fec00000 size 100000 align 0 gran 0 limit 0 flags f0000200 index 8
1489 17:45:51.169876 PCI: 00:00.0 resource base fc800000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 9
1490 17:45:51.179619 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
1491 17:45:51.189724 PCI: 00:00.0 resource base fed92000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b
1492 17:45:51.196097 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c
1493 17:45:51.206055 PCI: 00:00.0 resource base fed85000 size 1000 align 0 gran 0 limit 0 flags f0000200 index d
1494 17:45:51.216097 PCI: 00:00.0 resource base fed86000 size 1000 align 0 gran 0 limit 0 flags f0000200 index e
1495 17:45:51.226133 PCI: 00:00.0 resource base fed87000 size 1000 align 0 gran 0 limit 0 flags f0000200 index f
1496 17:45:51.236052 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 10
1497 17:45:51.245743 PCI: 00:00.0 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 11
1498 17:45:51.255638 PCI: 00:00.0 resource base 7c800000 size 3c00000 align 0 gran 0 limit 0 flags f0000200 index 12
1499 17:45:51.265722 PCI: 00:00.0 resource base 7b800000 size 800000 align 0 gran 0 limit 0 flags f0000200 index 13
1500 17:45:51.275404 PCI: 00:00.0 resource base 7c000000 size 800000 align 0 gran 0 limit 0 flags f0000200 index 14
1501 17:45:51.282250 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 15
1502 17:45:51.292603 PCI: 00:00.0 resource base c0000 size 76f40000 align 0 gran 0 limit 0 flags e0004200 index 16
1503 17:45:51.302241 PCI: 00:00.0 resource base 77000000 size 9400000 align 0 gran 0 limit 0 flags f0000200 index 17
1504 17:45:51.312042 PCI: 00:00.0 resource base 100000000 size 17fc00000 align 0 gran 0 limit 0 flags e0004200 index 18
1505 17:45:51.322068 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 19
1506 17:45:51.332047 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 1a
1507 17:45:51.342318 PCI: 00:00.0 resource base f8000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 1b
1508 17:45:51.342922 PCI: 00:02.0
1509 17:45:51.351935 PCI: 00:02.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1510 17:45:51.361830 PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
1511 17:45:51.371855 PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
1512 17:45:51.375040 PCI: 00:04.0 child on link 0 GENERIC: 0.0
1513 17:45:51.385305 PCI: 00:04.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 201 index 10
1514 17:45:51.388496 GENERIC: 0.0
1515 17:45:51.392439 PCI: 00:06.0 child on link 0 PCI: 01:00.0
1516 17:45:51.401770 PCI: 00:06.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
1517 17:45:51.411411 PCI: 00:06.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
1518 17:45:51.418387 PCI: 00:06.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
1519 17:45:51.421805 PCI: 01:00.0
1520 17:45:51.431316 PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1521 17:45:51.441542 PCI: 01:00.0 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 20
1522 17:45:51.442058 PCI: 00:08.0
1523 17:45:51.444969 PCI: 00:0a.0
1524 17:45:51.454876 PCI: 00:0a.0 resource base 0 size 8000 align 15 gran 15 limit ffffffffffffffff flags 201 index 10
1525 17:45:51.458018 PCI: 00:0d.0 child on link 0 USB0 port 0
1526 17:45:51.468153 PCI: 00:0d.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1527 17:45:51.474894 USB0 port 0 child on link 0 USB3 port 0
1528 17:45:51.475442 USB3 port 0
1529 17:45:51.478445 USB3 port 1
1530 17:45:51.479018 USB3 port 2
1531 17:45:51.481600 USB3 port 3
1532 17:45:51.485043 PCI: 00:14.0 child on link 0 USB0 port 0
1533 17:45:51.495224 PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1534 17:45:51.498521 USB0 port 0 child on link 0 USB2 port 0
1535 17:45:51.501576 USB2 port 0
1536 17:45:51.502108 USB2 port 1
1537 17:45:51.504321 USB2 port 2
1538 17:45:51.508472 USB2 port 3
1539 17:45:51.509005 USB2 port 4
1540 17:45:51.511452 USB2 port 5
1541 17:45:51.511988 USB2 port 6
1542 17:45:51.514704 USB2 port 7
1543 17:45:51.515132 USB2 port 8
1544 17:45:51.518305 USB2 port 9
1545 17:45:51.518879 USB3 port 0
1546 17:45:51.521680 USB3 port 1
1547 17:45:51.522212 USB3 port 2
1548 17:45:51.524918 USB3 port 3
1549 17:45:51.525449 PCI: 00:14.2
1550 17:45:51.534945 PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1551 17:45:51.544349 PCI: 00:14.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
1552 17:45:51.551491 PCI: 00:14.3 child on link 0 GENERIC: 0.0
1553 17:45:51.561266 PCI: 00:14.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1554 17:45:51.561807 GENERIC: 0.0
1555 17:45:51.567970 PCI: 00:15.0 child on link 0 I2C: 00:1a
1556 17:45:51.577927 PCI: 00:15.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1557 17:45:51.578363 I2C: 00:1a
1558 17:45:51.578841 I2C: 00:31
1559 17:45:51.581311 I2C: 00:32
1560 17:45:51.584765 PCI: 00:15.1 child on link 0 I2C: 00:50
1561 17:45:51.594268 PCI: 00:15.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1562 17:45:51.597413 I2C: 00:50
1563 17:45:51.597841 PCI: 00:15.2
1564 17:45:51.601141 PCI: 00:15.3 child on link 0 I2C: 00:10
1565 17:45:51.610949 PCI: 00:15.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1566 17:45:51.614687 I2C: 00:10
1567 17:45:51.615220 PCI: 00:16.0
1568 17:45:51.624605 PCI: 00:16.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1569 17:45:51.627630 PCI: 00:19.0
1570 17:45:51.631058 PCI: 00:19.1 child on link 0 I2C: 00:15
1571 17:45:51.640907 PCI: 00:19.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1572 17:45:51.644436 I2C: 00:15
1573 17:45:51.644974 I2C: 00:2c
1574 17:45:51.647139 PCI: 00:1e.0
1575 17:45:51.657730 PCI: 00:1e.0 resource base fe03e000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1576 17:45:51.660907 PCI: 00:1e.3 child on link 0 SPI: 00
1577 17:45:51.671193 PCI: 00:1e.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1578 17:45:51.674612 SPI: 00
1579 17:45:51.677808 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1580 17:45:51.687373 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1581 17:45:51.687896 PNP: 0c09.0
1582 17:45:51.697674 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1583 17:45:51.700599 PCI: 00:1f.2 child on link 0 GENERIC: 0.0
1584 17:45:51.710288 PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0
1585 17:45:51.720759 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1
1586 17:45:51.724088 GENERIC: 0.0 child on link 0 GENERIC: 0.0
1587 17:45:51.727020 GENERIC: 0.0
1588 17:45:51.727456 GENERIC: 1.0
1589 17:45:51.730765 PCI: 00:1f.3
1590 17:45:51.740496 PCI: 00:1f.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1591 17:45:51.750847 PCI: 00:1f.3 resource base 0 size 100000 align 20 gran 20 limit ffffffffffffffff flags 201 index 20
1592 17:45:51.751387 PCI: 00:1f.5
1593 17:45:51.760244 PCI: 00:1f.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
1594 17:45:51.766930 === Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) ===
1595 17:45:51.774043 PCI: 00:06.0 io: size: 0 align: 12 gran: 12 limit: ffff
1596 17:45:51.780826 PCI: 00:06.0 io: size: 0 align: 12 gran: 12 limit: ffff done
1597 17:45:51.787359 PCI: 00:06.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
1598 17:45:51.790802 PCI: 01:00.0 10 * [0x0 - 0x3fff] mem
1599 17:45:51.793795 PCI: 01:00.0 20 * [0x4000 - 0x40ff] mem
1600 17:45:51.800226 PCI: 00:06.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
1601 17:45:51.810127 PCI: 00:06.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
1602 17:45:51.816665 PCI: 00:06.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
1603 17:45:51.823553 === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
1604 17:45:51.830053 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
1605 17:45:51.837118 update_constraints: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
1606 17:45:51.843532 update_constraints: PNP: 0c09.0 00 base 00000800 limit 000009fe io (fixed)
1607 17:45:51.853388 update_constraints: PCI: 00:1f.2 01 base 00001800 limit 000018ff io (fixed)
1608 17:45:51.856398 DOMAIN: 0000: Resource ranges:
1609 17:45:51.860389 * Base: 1000, Size: 800, Tag: 100
1610 17:45:51.863716 * Base: 1900, Size: e700, Tag: 100
1611 17:45:51.866266 PCI: 00:02.0 20 * [0x1000 - 0x103f] limit: 103f io
1612 17:45:51.873449 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
1613 17:45:51.883253 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff
1614 17:45:51.889856 update_constraints: PCI: 00:00.0 00 base fedc0000 limit feddffff mem (fixed)
1615 17:45:51.896532 update_constraints: PCI: 00:00.0 01 base feda0000 limit feda0fff mem (fixed)
1616 17:45:51.906342 update_constraints: PCI: 00:00.0 02 base feda1000 limit feda1fff mem (fixed)
1617 17:45:51.913069 update_constraints: PCI: 00:00.0 03 base fb000000 limit fb000fff mem (fixed)
1618 17:45:51.919411 update_constraints: PCI: 00:00.0 04 base fed80000 limit fed83fff mem (fixed)
1619 17:45:51.926049 update_constraints: PCI: 00:00.0 05 base feb00000 limit feb7ffff mem (fixed)
1620 17:45:51.936203 update_constraints: PCI: 00:00.0 06 base fed40000 limit fed4ffff mem (fixed)
1621 17:45:51.943241 update_constraints: PCI: 00:00.0 07 base fed50000 limit fed6ffff mem (fixed)
1622 17:45:51.949439 update_constraints: PCI: 00:00.0 08 base fec00000 limit fecfffff mem (fixed)
1623 17:45:51.959067 update_constraints: PCI: 00:00.0 09 base fc800000 limit fe7fffff mem (fixed)
1624 17:45:51.966128 update_constraints: PCI: 00:00.0 0a base fed90000 limit fed90fff mem (fixed)
1625 17:45:51.972767 update_constraints: PCI: 00:00.0 0b base fed92000 limit fed92fff mem (fixed)
1626 17:45:51.983071 update_constraints: PCI: 00:00.0 0c base fed84000 limit fed84fff mem (fixed)
1627 17:45:51.989263 update_constraints: PCI: 00:00.0 0d base fed85000 limit fed85fff mem (fixed)
1628 17:45:51.995547 update_constraints: PCI: 00:00.0 0e base fed86000 limit fed86fff mem (fixed)
1629 17:45:52.006189 update_constraints: PCI: 00:00.0 0f base fed87000 limit fed87fff mem (fixed)
1630 17:45:52.012653 update_constraints: PCI: 00:00.0 10 base fed91000 limit fed91fff mem (fixed)
1631 17:45:52.019288 update_constraints: PCI: 00:00.0 11 base c0000000 limit cfffffff mem (fixed)
1632 17:45:52.029111 update_constraints: PCI: 00:00.0 12 base 7c800000 limit 803fffff mem (fixed)
1633 17:45:52.035807 update_constraints: PCI: 00:00.0 13 base 7b800000 limit 7bffffff mem (fixed)
1634 17:45:52.042313 update_constraints: PCI: 00:00.0 14 base 7c000000 limit 7c7fffff mem (fixed)
1635 17:45:52.052215 update_constraints: PCI: 00:00.0 15 base 00000000 limit 0009ffff mem (fixed)
1636 17:45:52.059004 update_constraints: PCI: 00:00.0 16 base 000c0000 limit 76ffffff mem (fixed)
1637 17:45:52.065688 update_constraints: PCI: 00:00.0 17 base 77000000 limit 803fffff mem (fixed)
1638 17:45:52.075252 update_constraints: PCI: 00:00.0 18 base 100000000 limit 27fbfffff mem (fixed)
1639 17:45:52.081840 update_constraints: PCI: 00:00.0 19 base 000a0000 limit 000bffff mem (fixed)
1640 17:45:52.088808 update_constraints: PCI: 00:00.0 1a base 000c0000 limit 000fffff mem (fixed)
1641 17:45:52.098525 update_constraints: PCI: 00:00.0 1b base f8000000 limit f9ffffff mem (fixed)
1642 17:45:52.105309 update_constraints: PCI: 00:1e.0 10 base fe03e000 limit fe03efff mem (fixed)
1643 17:45:52.111985 update_constraints: PCI: 00:1f.2 00 base fe000000 limit fe00ffff mem (fixed)
1644 17:45:52.115192 DOMAIN: 0000: Resource ranges:
1645 17:45:52.121893 * Base: 80400000, Size: 3fc00000, Tag: 200
1646 17:45:52.125375 * Base: d0000000, Size: 28000000, Tag: 200
1647 17:45:52.128678 * Base: fa000000, Size: 1000000, Tag: 200
1648 17:45:52.135189 * Base: fb001000, Size: 17ff000, Tag: 200
1649 17:45:52.138062 * Base: fe800000, Size: 300000, Tag: 200
1650 17:45:52.141699 * Base: feb80000, Size: 80000, Tag: 200
1651 17:45:52.144812 * Base: fed00000, Size: 40000, Tag: 200
1652 17:45:52.151255 * Base: fed70000, Size: 10000, Tag: 200
1653 17:45:52.154476 * Base: fed88000, Size: 8000, Tag: 200
1654 17:45:52.158689 * Base: fed93000, Size: d000, Tag: 200
1655 17:45:52.161465 * Base: feda2000, Size: 1e000, Tag: 200
1656 17:45:52.164552 * Base: fede0000, Size: 1220000, Tag: 200
1657 17:45:52.171588 * Base: 27fc00000, Size: 7d80400000, Tag: 100200
1658 17:45:52.177801 PCI: 00:02.0 18 * [0x90000000 - 0x9fffffff] limit: 9fffffff prefmem
1659 17:45:52.184812 PCI: 00:02.0 10 * [0x81000000 - 0x81ffffff] limit: 81ffffff mem
1660 17:45:52.191136 PCI: 00:06.0 20 * [0x80400000 - 0x804fffff] limit: 804fffff mem
1661 17:45:52.197856 PCI: 00:1f.3 20 * [0x80500000 - 0x805fffff] limit: 805fffff mem
1662 17:45:52.204450 PCI: 00:04.0 10 * [0x80600000 - 0x8061ffff] limit: 8061ffff mem
1663 17:45:52.211238 PCI: 00:0d.0 10 * [0x80620000 - 0x8062ffff] limit: 8062ffff mem
1664 17:45:52.217834 PCI: 00:14.0 10 * [0x80630000 - 0x8063ffff] limit: 8063ffff mem
1665 17:45:52.224561 PCI: 00:0a.0 10 * [0x80640000 - 0x80647fff] limit: 80647fff mem
1666 17:45:52.231070 PCI: 00:14.2 10 * [0x80648000 - 0x8064bfff] limit: 8064bfff mem
1667 17:45:52.238121 PCI: 00:14.3 10 * [0x8064c000 - 0x8064ffff] limit: 8064ffff mem
1668 17:45:52.244563 PCI: 00:1f.3 10 * [0x80650000 - 0x80653fff] limit: 80653fff mem
1669 17:45:52.251180 PCI: 00:14.2 18 * [0x80654000 - 0x80654fff] limit: 80654fff mem
1670 17:45:52.258094 PCI: 00:15.0 10 * [0x80655000 - 0x80655fff] limit: 80655fff mem
1671 17:45:52.264073 PCI: 00:15.1 10 * [0x80656000 - 0x80656fff] limit: 80656fff mem
1672 17:45:52.270635 PCI: 00:15.3 10 * [0x80657000 - 0x80657fff] limit: 80657fff mem
1673 17:45:52.277625 PCI: 00:16.0 10 * [0x80658000 - 0x80658fff] limit: 80658fff mem
1674 17:45:52.284102 PCI: 00:19.1 10 * [0x80659000 - 0x80659fff] limit: 80659fff mem
1675 17:45:52.291118 PCI: 00:1e.3 10 * [0x8065a000 - 0x8065afff] limit: 8065afff mem
1676 17:45:52.297669 PCI: 00:1f.5 10 * [0x8065b000 - 0x8065bfff] limit: 8065bfff mem
1677 17:45:52.304089 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff done
1678 17:45:52.314019 PCI: 00:06.0 mem: base: 80400000 size: 100000 align: 20 gran: 20 limit: 804fffff
1679 17:45:52.317307 PCI: 00:06.0: Resource ranges:
1680 17:45:52.320688 * Base: 80400000, Size: 100000, Tag: 200
1681 17:45:52.327371 PCI: 01:00.0 10 * [0x80400000 - 0x80403fff] limit: 80403fff mem
1682 17:45:52.334107 PCI: 01:00.0 20 * [0x80404000 - 0x804040ff] limit: 804040ff mem
1683 17:45:52.343876 PCI: 00:06.0 mem: base: 80400000 size: 100000 align: 20 gran: 20 limit: 804fffff done
1684 17:45:52.350335 === Resource allocator: DOMAIN: 0000 - resource allocation complete ===
1685 17:45:52.353356 Root Device assign_resources, bus 0 link: 0
1686 17:45:52.356946 DOMAIN: 0000 assign_resources, bus 0 link: 0
1687 17:45:52.366631 PCI: 00:02.0 10 <- [0x0081000000 - 0x0081ffffff] size 0x01000000 gran 0x18 mem64
1688 17:45:52.373745 PCI: 00:02.0 18 <- [0x0090000000 - 0x009fffffff] size 0x10000000 gran 0x1c prefmem64
1689 17:45:52.383538 PCI: 00:02.0 20 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io
1690 17:45:52.390698 PCI: 00:04.0 10 <- [0x0080600000 - 0x008061ffff] size 0x00020000 gran 0x11 mem64
1691 17:45:52.393925 PCI: 00:04.0 assign_resources, bus 1 link: 0
1692 17:45:52.400158 PCI: 00:04.0 assign_resources, bus 1 link: 0 done
1693 17:45:52.406921 PCI: 00:06.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
1694 17:45:52.420233 PCI: 00:06.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
1695 17:45:52.426783 PCI: 00:06.0 20 <- [0x0080400000 - 0x00804fffff] size 0x00100000 gran 0x14 bus 01 mem
1696 17:45:52.430057 PCI: 00:06.0 assign_resources, bus 1 link: 0
1697 17:45:52.440156 PCI: 01:00.0 10 <- [0x0080400000 - 0x0080403fff] size 0x00004000 gran 0x0e mem64
1698 17:45:52.446866 PCI: 01:00.0 20 <- [0x0080404000 - 0x00804040ff] size 0x00000100 gran 0x08 mem64
1699 17:45:52.453059 PCI: 00:06.0 assign_resources, bus 1 link: 0 done
1700 17:45:52.459973 PCI: 00:0a.0 10 <- [0x0080640000 - 0x0080647fff] size 0x00008000 gran 0x0f mem64
1701 17:45:52.469827 PCI: 00:0d.0 10 <- [0x0080620000 - 0x008062ffff] size 0x00010000 gran 0x10 mem64
1702 17:45:52.473028 PCI: 00:0d.0 assign_resources, bus 0 link: 0
1703 17:45:52.476589 PCI: 00:0d.0 assign_resources, bus 0 link: 0 done
1704 17:45:52.486213 PCI: 00:14.0 10 <- [0x0080630000 - 0x008063ffff] size 0x00010000 gran 0x10 mem64
1705 17:45:52.489719 PCI: 00:14.0 assign_resources, bus 0 link: 0
1706 17:45:52.496268 PCI: 00:14.0 assign_resources, bus 0 link: 0 done
1707 17:45:52.502741 PCI: 00:14.2 10 <- [0x0080648000 - 0x008064bfff] size 0x00004000 gran 0x0e mem64
1708 17:45:52.512844 PCI: 00:14.2 18 <- [0x0080654000 - 0x0080654fff] size 0x00001000 gran 0x0c mem64
1709 17:45:52.519465 PCI: 00:14.3 10 <- [0x008064c000 - 0x008064ffff] size 0x00004000 gran 0x0e mem64
1710 17:45:52.522960 PCI: 00:14.3 assign_resources, bus 0 link: 0
1711 17:45:52.529027 PCI: 00:14.3 assign_resources, bus 0 link: 0 done
1712 17:45:52.535699 PCI: 00:15.0 10 <- [0x0080655000 - 0x0080655fff] size 0x00001000 gran 0x0c mem64
1713 17:45:52.542508 PCI: 00:15.0 assign_resources, bus 0 link: 0
1714 17:45:52.545893 PCI: 00:15.0 assign_resources, bus 0 link: 0 done
1715 17:45:52.555492 PCI: 00:15.1 10 <- [0x0080656000 - 0x0080656fff] size 0x00001000 gran 0x0c mem64
1716 17:45:52.558817 PCI: 00:15.1 assign_resources, bus 0 link: 0
1717 17:45:52.562217 PCI: 00:15.1 assign_resources, bus 0 link: 0 done
1718 17:45:52.572064 PCI: 00:15.3 10 <- [0x0080657000 - 0x0080657fff] size 0x00001000 gran 0x0c mem64
1719 17:45:52.575757 PCI: 00:15.3 assign_resources, bus 0 link: 0
1720 17:45:52.582214 PCI: 00:15.3 assign_resources, bus 0 link: 0 done
1721 17:45:52.589005 PCI: 00:16.0 10 <- [0x0080658000 - 0x0080658fff] size 0x00001000 gran 0x0c mem64
1722 17:45:52.599123 PCI: 00:19.1 10 <- [0x0080659000 - 0x0080659fff] size 0x00001000 gran 0x0c mem64
1723 17:45:52.602459 PCI: 00:19.1 assign_resources, bus 0 link: 0
1724 17:45:52.605263 PCI: 00:19.1 assign_resources, bus 0 link: 0 done
1725 17:45:52.615261 PCI: 00:1e.3 10 <- [0x008065a000 - 0x008065afff] size 0x00001000 gran 0x0c mem64
1726 17:45:52.618654 PCI: 00:1e.3 assign_resources, bus 2 link: 0
1727 17:45:52.625188 PCI: 00:1e.3 assign_resources, bus 2 link: 0 done
1728 17:45:52.628740 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1729 17:45:52.635194 PCI: 00:1f.0 assign_resources, bus 0 link: 0 done
1730 17:45:52.638308 LPC: Trying to open IO window from 800 size 1ff
1731 17:45:52.645104 PCI: 00:1f.3 10 <- [0x0080650000 - 0x0080653fff] size 0x00004000 gran 0x0e mem64
1732 17:45:52.654836 PCI: 00:1f.3 20 <- [0x0080500000 - 0x00805fffff] size 0x00100000 gran 0x14 mem64
1733 17:45:52.661424 PCI: 00:1f.5 10 <- [0x008065b000 - 0x008065bfff] size 0x00001000 gran 0x0c mem
1734 17:45:52.668026 DOMAIN: 0000 assign_resources, bus 0 link: 0 done
1735 17:45:52.671294 Root Device assign_resources, bus 0 link: 0 done
1736 17:45:52.674855 Done setting resources.
1737 17:45:52.681692 Show resources in subtree (Root Device)...After assigning values.
1738 17:45:52.684735 Root Device child on link 0 CPU_CLUSTER: 0
1739 17:45:52.691102 CPU_CLUSTER: 0 child on link 0 APIC: 00
1740 17:45:52.691619 APIC: 00
1741 17:45:52.691966 APIC: 16
1742 17:45:52.694626 APIC: 10
1743 17:45:52.695161 APIC: 12
1744 17:45:52.697849 APIC: 14
1745 17:45:52.698382 APIC: 09
1746 17:45:52.698768 APIC: 08
1747 17:45:52.701271 APIC: 01
1748 17:45:52.704554 DOMAIN: 0000 child on link 0 GPIO: 0
1749 17:45:52.713971 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1750 17:45:52.724761 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100
1751 17:45:52.725303 GPIO: 0
1752 17:45:52.725653 PCI: 00:00.0
1753 17:45:52.733958 PCI: 00:00.0 resource base fedc0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 0
1754 17:45:52.744029 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 1
1755 17:45:52.754054 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1756 17:45:52.764134 PCI: 00:00.0 resource base fb000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1757 17:45:52.774511 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 4
1758 17:45:52.780852 PCI: 00:00.0 resource base feb00000 size 80000 align 0 gran 0 limit 0 flags f0000200 index 5
1759 17:45:52.790632 PCI: 00:00.0 resource base fed40000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 6
1760 17:45:52.800275 PCI: 00:00.0 resource base fed50000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 7
1761 17:45:52.810556 PCI: 00:00.0 resource base fec00000 size 100000 align 0 gran 0 limit 0 flags f0000200 index 8
1762 17:45:52.820497 PCI: 00:00.0 resource base fc800000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 9
1763 17:45:52.830393 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
1764 17:45:52.840419 PCI: 00:00.0 resource base fed92000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b
1765 17:45:52.850255 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c
1766 17:45:52.856963 PCI: 00:00.0 resource base fed85000 size 1000 align 0 gran 0 limit 0 flags f0000200 index d
1767 17:45:52.867034 PCI: 00:00.0 resource base fed86000 size 1000 align 0 gran 0 limit 0 flags f0000200 index e
1768 17:45:52.876529 PCI: 00:00.0 resource base fed87000 size 1000 align 0 gran 0 limit 0 flags f0000200 index f
1769 17:45:52.886823 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 10
1770 17:45:52.896671 PCI: 00:00.0 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 11
1771 17:45:52.906440 PCI: 00:00.0 resource base 7c800000 size 3c00000 align 0 gran 0 limit 0 flags f0000200 index 12
1772 17:45:52.916440 PCI: 00:00.0 resource base 7b800000 size 800000 align 0 gran 0 limit 0 flags f0000200 index 13
1773 17:45:52.926069 PCI: 00:00.0 resource base 7c000000 size 800000 align 0 gran 0 limit 0 flags f0000200 index 14
1774 17:45:52.932943 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 15
1775 17:45:52.942815 PCI: 00:00.0 resource base c0000 size 76f40000 align 0 gran 0 limit 0 flags e0004200 index 16
1776 17:45:52.952787 PCI: 00:00.0 resource base 77000000 size 9400000 align 0 gran 0 limit 0 flags f0000200 index 17
1777 17:45:52.962811 PCI: 00:00.0 resource base 100000000 size 17fc00000 align 0 gran 0 limit 0 flags e0004200 index 18
1778 17:45:52.972377 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 19
1779 17:45:52.982178 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 1a
1780 17:45:52.992129 PCI: 00:00.0 resource base f8000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 1b
1781 17:45:52.992666 PCI: 00:02.0
1782 17:45:53.001981 PCI: 00:02.0 resource base 81000000 size 1000000 align 24 gran 24 limit 81ffffff flags 60000201 index 10
1783 17:45:53.015258 PCI: 00:02.0 resource base 90000000 size 10000000 align 28 gran 28 limit 9fffffff flags 60001201 index 18
1784 17:45:53.021980 PCI: 00:02.0 resource base 1000 size 40 align 6 gran 6 limit 103f flags 60000100 index 20
1785 17:45:53.028691 PCI: 00:04.0 child on link 0 GENERIC: 0.0
1786 17:45:53.038697 PCI: 00:04.0 resource base 80600000 size 20000 align 17 gran 17 limit 8061ffff flags 60000201 index 10
1787 17:45:53.039200 GENERIC: 0.0
1788 17:45:53.045336 PCI: 00:06.0 child on link 0 PCI: 01:00.0
1789 17:45:53.055002 PCI: 00:06.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 20080102 index 1c
1790 17:45:53.065420 PCI: 00:06.0 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24
1791 17:45:53.075528 PCI: 00:06.0 resource base 80400000 size 100000 align 20 gran 20 limit 804fffff flags 60080202 index 20
1792 17:45:53.078670 PCI: 01:00.0
1793 17:45:53.088366 PCI: 01:00.0 resource base 80400000 size 4000 align 14 gran 14 limit 80403fff flags 60000201 index 10
1794 17:45:53.097701 PCI: 01:00.0 resource base 80404000 size 100 align 12 gran 8 limit 804040ff flags 60000201 index 20
1795 17:45:53.101209 PCI: 00:08.0
1796 17:45:53.101743 PCI: 00:0a.0
1797 17:45:53.111246 PCI: 00:0a.0 resource base 80640000 size 8000 align 15 gran 15 limit 80647fff flags 60000201 index 10
1798 17:45:53.118431 PCI: 00:0d.0 child on link 0 USB0 port 0
1799 17:45:53.128056 PCI: 00:0d.0 resource base 80620000 size 10000 align 16 gran 16 limit 8062ffff flags 60000201 index 10
1800 17:45:53.131275 USB0 port 0 child on link 0 USB3 port 0
1801 17:45:53.134396 USB3 port 0
1802 17:45:53.134943 USB3 port 1
1803 17:45:53.138168 USB3 port 2
1804 17:45:53.138790 USB3 port 3
1805 17:45:53.144697 PCI: 00:14.0 child on link 0 USB0 port 0
1806 17:45:53.154674 PCI: 00:14.0 resource base 80630000 size 10000 align 16 gran 16 limit 8063ffff flags 60000201 index 10
1807 17:45:53.157795 USB0 port 0 child on link 0 USB2 port 0
1808 17:45:53.161314 USB2 port 0
1809 17:45:53.161847 USB2 port 1
1810 17:45:53.164521 USB2 port 2
1811 17:45:53.165054 USB2 port 3
1812 17:45:53.167407 USB2 port 4
1813 17:45:53.167832 USB2 port 5
1814 17:45:53.170698 USB2 port 6
1815 17:45:53.171128 USB2 port 7
1816 17:45:53.174440 USB2 port 8
1817 17:45:53.174936 USB2 port 9
1818 17:45:53.177749 USB3 port 0
1819 17:45:53.178252 USB3 port 1
1820 17:45:53.181286 USB3 port 2
1821 17:45:53.181821 USB3 port 3
1822 17:45:53.184558 PCI: 00:14.2
1823 17:45:53.194285 PCI: 00:14.2 resource base 80648000 size 4000 align 14 gran 14 limit 8064bfff flags 60000201 index 10
1824 17:45:53.204517 PCI: 00:14.2 resource base 80654000 size 1000 align 12 gran 12 limit 80654fff flags 60000201 index 18
1825 17:45:53.210688 PCI: 00:14.3 child on link 0 GENERIC: 0.0
1826 17:45:53.220980 PCI: 00:14.3 resource base 8064c000 size 4000 align 14 gran 14 limit 8064ffff flags 60000201 index 10
1827 17:45:53.221516 GENERIC: 0.0
1828 17:45:53.227522 PCI: 00:15.0 child on link 0 I2C: 00:1a
1829 17:45:53.237709 PCI: 00:15.0 resource base 80655000 size 1000 align 12 gran 12 limit 80655fff flags 60000201 index 10
1830 17:45:53.238248 I2C: 00:1a
1831 17:45:53.240924 I2C: 00:31
1832 17:45:53.241459 I2C: 00:32
1833 17:45:53.244085 PCI: 00:15.1 child on link 0 I2C: 00:50
1834 17:45:53.253859 PCI: 00:15.1 resource base 80656000 size 1000 align 12 gran 12 limit 80656fff flags 60000201 index 10
1835 17:45:53.257800 I2C: 00:50
1836 17:45:53.258332 PCI: 00:15.2
1837 17:45:53.263771 PCI: 00:15.3 child on link 0 I2C: 00:10
1838 17:45:53.274352 PCI: 00:15.3 resource base 80657000 size 1000 align 12 gran 12 limit 80657fff flags 60000201 index 10
1839 17:45:53.274937 I2C: 00:10
1840 17:45:53.277302 PCI: 00:16.0
1841 17:45:53.287146 PCI: 00:16.0 resource base 80658000 size 1000 align 12 gran 12 limit 80658fff flags 60000201 index 10
1842 17:45:53.287571 PCI: 00:19.0
1843 17:45:53.294083 PCI: 00:19.1 child on link 0 I2C: 00:15
1844 17:45:53.303830 PCI: 00:19.1 resource base 80659000 size 1000 align 12 gran 12 limit 80659fff flags 60000201 index 10
1845 17:45:53.304347 I2C: 00:15
1846 17:45:53.307084 I2C: 00:2c
1847 17:45:53.307505 PCI: 00:1e.0
1848 17:45:53.320338 PCI: 00:1e.0 resource base fe03e000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1849 17:45:53.324451 PCI: 00:1e.3 child on link 0 SPI: 00
1850 17:45:53.333877 PCI: 00:1e.3 resource base 8065a000 size 1000 align 12 gran 12 limit 8065afff flags 60000201 index 10
1851 17:45:53.334396 SPI: 00
1852 17:45:53.340549 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1853 17:45:53.346993 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1854 17:45:53.350411 PNP: 0c09.0
1855 17:45:53.356700 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1856 17:45:53.363287 PCI: 00:1f.2 child on link 0 GENERIC: 0.0
1857 17:45:53.373505 PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0
1858 17:45:53.380020 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1
1859 17:45:53.386851 GENERIC: 0.0 child on link 0 GENERIC: 0.0
1860 17:45:53.387385 GENERIC: 0.0
1861 17:45:53.390253 GENERIC: 1.0
1862 17:45:53.390835 PCI: 00:1f.3
1863 17:45:53.403664 PCI: 00:1f.3 resource base 80650000 size 4000 align 14 gran 14 limit 80653fff flags 60000201 index 10
1864 17:45:53.418204 PCI: 00:1f.3 resource base 80500000 size 100000 align 20 gran 20 limit 805fffff flags 60000201 index 20
1865 17:45:53.418393 PCI: 00:1f.5
1866 17:45:53.422931 PCI: 00:1f.5 resource base 8065b000 size 1000 align 12 gran 12 limit 8065bfff flags 60000200 index 10
1867 17:45:53.425914 Done allocating resources.
1868 17:45:53.432918 BS: BS_DEV_RESOURCES run times (exec / console): 2 / 2717 ms
1869 17:45:53.439222 fw_config match found: AUDIO=MAX98373_NAU88L25B_I2S
1870 17:45:53.443173 Configure audio over I2S with MAX98373 NAU88L25B.
1871 17:45:53.447892 Enabling BT offload
1872 17:45:53.455293 BS: BS_DEV_ENABLE entry times (exec / console): 5 / 12 ms
1873 17:45:53.458963 Enabling resources...
1874 17:45:53.462041 PCI: 00:00.0 subsystem <- 8086/4609
1875 17:45:53.465167 PCI: 00:00.0 cmd <- 06
1876 17:45:53.468836 PCI: 00:02.0 subsystem <- 8086/46b3
1877 17:45:53.471823 PCI: 00:02.0 cmd <- 03
1878 17:45:53.475017 PCI: 00:04.0 subsystem <- 8086/461d
1879 17:45:53.475563 PCI: 00:04.0 cmd <- 02
1880 17:45:53.478437 PCI: 00:06.0 bridge ctrl <- 0013
1881 17:45:53.482097 PCI: 00:06.0 subsystem <- 8086/464d
1882 17:45:53.485494 PCI: 00:06.0 cmd <- 106
1883 17:45:53.488570 PCI: 00:0a.0 subsystem <- 8086/467d
1884 17:45:53.492010 PCI: 00:0a.0 cmd <- 02
1885 17:45:53.494965 PCI: 00:0d.0 subsystem <- 8086/461e
1886 17:45:53.498529 PCI: 00:0d.0 cmd <- 02
1887 17:45:53.502198 PCI: 00:14.0 subsystem <- 8086/51ed
1888 17:45:53.505205 PCI: 00:14.0 cmd <- 02
1889 17:45:53.508861 PCI: 00:14.2 subsystem <- 8086/51ef
1890 17:45:53.509395 PCI: 00:14.2 cmd <- 02
1891 17:45:53.511940 PCI: 00:14.3 subsystem <- 8086/51f0
1892 17:45:53.515547 PCI: 00:14.3 cmd <- 02
1893 17:45:53.518251 PCI: 00:15.0 subsystem <- 8086/51e8
1894 17:45:53.521507 PCI: 00:15.0 cmd <- 02
1895 17:45:53.525105 PCI: 00:15.1 subsystem <- 8086/51e9
1896 17:45:53.528077 PCI: 00:15.1 cmd <- 06
1897 17:45:53.531715 PCI: 00:15.3 subsystem <- 8086/51eb
1898 17:45:53.534842 PCI: 00:15.3 cmd <- 02
1899 17:45:53.538458 PCI: 00:16.0 subsystem <- 8086/51e0
1900 17:45:53.538915 PCI: 00:16.0 cmd <- 02
1901 17:45:53.544683 PCI: 00:19.1 subsystem <- 8086/51c6
1902 17:45:53.545202 PCI: 00:19.1 cmd <- 02
1903 17:45:53.548449 PCI: 00:1e.0 subsystem <- 8086/51a8
1904 17:45:53.551391 PCI: 00:1e.0 cmd <- 06
1905 17:45:53.554738 PCI: 00:1e.3 subsystem <- 8086/51ab
1906 17:45:53.558377 PCI: 00:1e.3 cmd <- 02
1907 17:45:53.561541 PCI: 00:1f.0 subsystem <- 8086/5182
1908 17:45:53.564713 PCI: 00:1f.0 cmd <- 407
1909 17:45:53.568256 PCI: 00:1f.3 subsystem <- 8086/51c8
1910 17:45:53.568688 PCI: 00:1f.3 cmd <- 02
1911 17:45:53.574708 PCI: 00:1f.5 subsystem <- 8086/51a4
1912 17:45:53.575244 PCI: 00:1f.5 cmd <- 406
1913 17:45:53.578299 PCI: 01:00.0 cmd <- 02
1914 17:45:53.578839 done.
1915 17:45:53.584696 BS: BS_DEV_ENABLE run times (exec / console): 1 / 122 ms
1916 17:45:53.588263 ME: Version: Unavailable
1917 17:45:53.591565 BS: BS_DEV_ENABLE exit times (exec / console): 0 / 3 ms
1918 17:45:53.594734 Initializing devices...
1919 17:45:53.598332 Root Device init
1920 17:45:53.598800 mainboard: EC init
1921 17:45:53.604474 Chrome EC: Set SMI mask to 0x0000000000000000
1922 17:45:53.608334 Chrome EC: UHEPI supported
1923 17:45:53.614833 Chrome EC: clear events_b mask to 0x0000000000000000
1924 17:45:53.621410 Chrome EC: Set S5 LAZY WAKE mask to 0x0000000000000006
1925 17:45:53.624760 Chrome EC: Set S3 LAZY WAKE mask to 0x000000001000101e
1926 17:45:53.630955 Chrome EC: Set S0iX LAZY WAKE mask to 0x000000001808101e
1927 17:45:53.637744 Chrome EC: Set WAKE mask to 0x0000000000000000
1928 17:45:53.640885 Root Device init finished in 40 msecs
1929 17:45:53.644142 PCI: 00:00.0 init
1930 17:45:53.644574 CPU TDP = 15 Watts
1931 17:45:53.647365 CPU PL1 = 15 Watts
1932 17:45:53.651195 CPU PL2 = 55 Watts
1933 17:45:53.651698 CPU PL4 = 123 Watts
1934 17:45:53.654421 PCI: 00:00.0 init finished in 8 msecs
1935 17:45:53.657772 PCI: 00:02.0 init
1936 17:45:53.660865 GMA: Found VBT in CBFS
1937 17:45:53.664122 GMA: Found valid VBT in CBFS
1938 17:45:53.667428 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
1939 17:45:53.677558 x_res x y_res: 1920 x 1080, size: 8294400 at 0x90000000
1940 17:45:53.680770 PCI: 00:02.0 init finished in 18 msecs
1941 17:45:53.681206 PCI: 00:06.0 init
1942 17:45:53.684075 Initializing PCH PCIe bridge.
1943 17:45:53.687300 PCI: 00:06.0 init finished in 3 msecs
1944 17:45:53.690815 PCI: 00:0a.0 init
1945 17:45:53.693828 PCI: 00:0a.0 init finished in 0 msecs
1946 17:45:53.697563 PCI: 00:14.0 init
1947 17:45:53.700565 PCI: 00:14.0 init finished in 0 msecs
1948 17:45:53.700998 PCI: 00:14.2 init
1949 17:45:53.707693 PCI: 00:14.2 init finished in 0 msecs
1950 17:45:53.708122 PCI: 00:15.0 init
1951 17:45:53.710787 I2C bus 0 version 0x3230302a
1952 17:45:53.713987 DW I2C bus 0 at 0x80655000 (400 KHz)
1953 17:45:53.717254 PCI: 00:15.0 init finished in 6 msecs
1954 17:45:53.720656 PCI: 00:15.1 init
1955 17:45:53.723916 I2C bus 1 version 0x3230302a
1956 17:45:53.727292 DW I2C bus 1 at 0x80656000 (400 KHz)
1957 17:45:53.730467 PCI: 00:15.1 init finished in 6 msecs
1958 17:45:53.730943 PCI: 00:15.3 init
1959 17:45:53.734197 I2C bus 3 version 0x3230302a
1960 17:45:53.737488 DW I2C bus 3 at 0x80657000 (400 KHz)
1961 17:45:53.743960 PCI: 00:15.3 init finished in 6 msecs
1962 17:45:53.744389 PCI: 00:16.0 init
1963 17:45:53.747326 PCI: 00:16.0 init finished in 0 msecs
1964 17:45:53.750645 PCI: 00:19.1 init
1965 17:45:53.753913 I2C bus 5 version 0x3230302a
1966 17:45:53.757243 DW I2C bus 5 at 0x80659000 (400 KHz)
1967 17:45:53.760696 PCI: 00:19.1 init finished in 6 msecs
1968 17:45:53.763767 PCI: 00:1f.0 init
1969 17:45:53.767216 IOAPIC: Initializing IOAPIC at 0xfec00000
1970 17:45:53.767645 IOAPIC: ID = 0x02
1971 17:45:53.770436 IOAPIC: Dumping registers
1972 17:45:53.774247 reg 0x0000: 0x02000000
1973 17:45:53.777046 reg 0x0001: 0x00770020
1974 17:45:53.780816 reg 0x0002: 0x00000000
1975 17:45:53.781247 IOAPIC: 120 interrupts
1976 17:45:53.783998 IOAPIC: Clearing IOAPIC at 0xfec00000
1977 17:45:53.790395 IOAPIC: vector 0x00 value 0x00000000 0x00010000
1978 17:45:53.793872 IOAPIC: vector 0x01 value 0x00000000 0x00010000
1979 17:45:53.800504 IOAPIC: vector 0x02 value 0x00000000 0x00010000
1980 17:45:53.803804 IOAPIC: vector 0x03 value 0x00000000 0x00010000
1981 17:45:53.810699 IOAPIC: vector 0x04 value 0x00000000 0x00010000
1982 17:45:53.813604 IOAPIC: vector 0x05 value 0x00000000 0x00010000
1983 17:45:53.820544 IOAPIC: vector 0x06 value 0x00000000 0x00010000
1984 17:45:53.823889 IOAPIC: vector 0x07 value 0x00000000 0x00010000
1985 17:45:53.827112 IOAPIC: vector 0x08 value 0x00000000 0x00010000
1986 17:45:53.833505 IOAPIC: vector 0x09 value 0x00000000 0x00010000
1987 17:45:53.836907 IOAPIC: vector 0x0a value 0x00000000 0x00010000
1988 17:45:53.843525 IOAPIC: vector 0x0b value 0x00000000 0x00010000
1989 17:45:53.847218 IOAPIC: vector 0x0c value 0x00000000 0x00010000
1990 17:45:53.853388 IOAPIC: vector 0x0d value 0x00000000 0x00010000
1991 17:45:53.857416 IOAPIC: vector 0x0e value 0x00000000 0x00010000
1992 17:45:53.860801 IOAPIC: vector 0x0f value 0x00000000 0x00010000
1993 17:45:53.867343 IOAPIC: vector 0x10 value 0x00000000 0x00010000
1994 17:45:53.870713 IOAPIC: vector 0x11 value 0x00000000 0x00010000
1995 17:45:53.877020 IOAPIC: vector 0x12 value 0x00000000 0x00010000
1996 17:45:53.880263 IOAPIC: vector 0x13 value 0x00000000 0x00010000
1997 17:45:53.887078 IOAPIC: vector 0x14 value 0x00000000 0x00010000
1998 17:45:53.890286 IOAPIC: vector 0x15 value 0x00000000 0x00010000
1999 17:45:53.897108 IOAPIC: vector 0x16 value 0x00000000 0x00010000
2000 17:45:53.900662 IOAPIC: vector 0x17 value 0x00000000 0x00010000
2001 17:45:53.904080 IOAPIC: vector 0x18 value 0x00000000 0x00010000
2002 17:45:53.910232 IOAPIC: vector 0x19 value 0x00000000 0x00010000
2003 17:45:53.913390 IOAPIC: vector 0x1a value 0x00000000 0x00010000
2004 17:45:53.920504 IOAPIC: vector 0x1b value 0x00000000 0x00010000
2005 17:45:53.923398 IOAPIC: vector 0x1c value 0x00000000 0x00010000
2006 17:45:53.930346 IOAPIC: vector 0x1d value 0x00000000 0x00010000
2007 17:45:53.933240 IOAPIC: vector 0x1e value 0x00000000 0x00010000
2008 17:45:53.940108 IOAPIC: vector 0x1f value 0x00000000 0x00010000
2009 17:45:53.943111 IOAPIC: vector 0x20 value 0x00000000 0x00010000
2010 17:45:53.946848 IOAPIC: vector 0x21 value 0x00000000 0x00010000
2011 17:45:53.953314 IOAPIC: vector 0x22 value 0x00000000 0x00010000
2012 17:45:53.956883 IOAPIC: vector 0x23 value 0x00000000 0x00010000
2013 17:45:53.963551 IOAPIC: vector 0x24 value 0x00000000 0x00010000
2014 17:45:53.967004 IOAPIC: vector 0x25 value 0x00000000 0x00010000
2015 17:45:53.973399 IOAPIC: vector 0x26 value 0x00000000 0x00010000
2016 17:45:53.976719 IOAPIC: vector 0x27 value 0x00000000 0x00010000
2017 17:45:53.983355 IOAPIC: vector 0x28 value 0x00000000 0x00010000
2018 17:45:53.986910 IOAPIC: vector 0x29 value 0x00000000 0x00010000
2019 17:45:53.990241 IOAPIC: vector 0x2a value 0x00000000 0x00010000
2020 17:45:53.996773 IOAPIC: vector 0x2b value 0x00000000 0x00010000
2021 17:45:53.999974 IOAPIC: vector 0x2c value 0x00000000 0x00010000
2022 17:45:54.006741 IOAPIC: vector 0x2d value 0x00000000 0x00010000
2023 17:45:54.010099 IOAPIC: vector 0x2e value 0x00000000 0x00010000
2024 17:45:54.016544 IOAPIC: vector 0x2f value 0x00000000 0x00010000
2025 17:45:54.019985 IOAPIC: vector 0x30 value 0x00000000 0x00010000
2026 17:45:54.026633 IOAPIC: vector 0x31 value 0x00000000 0x00010000
2027 17:45:54.029815 IOAPIC: vector 0x32 value 0x00000000 0x00010000
2028 17:45:54.033303 IOAPIC: vector 0x33 value 0x00000000 0x00010000
2029 17:45:54.040211 IOAPIC: vector 0x34 value 0x00000000 0x00010000
2030 17:45:54.043412 IOAPIC: vector 0x35 value 0x00000000 0x00010000
2031 17:45:54.050158 IOAPIC: vector 0x36 value 0x00000000 0x00010000
2032 17:45:54.053066 IOAPIC: vector 0x37 value 0x00000000 0x00010000
2033 17:45:54.059797 IOAPIC: vector 0x38 value 0x00000000 0x00010000
2034 17:45:54.062998 IOAPIC: vector 0x39 value 0x00000000 0x00010000
2035 17:45:54.069540 IOAPIC: vector 0x3a value 0x00000000 0x00010000
2036 17:45:54.072885 IOAPIC: vector 0x3b value 0x00000000 0x00010000
2037 17:45:54.076152 IOAPIC: vector 0x3c value 0x00000000 0x00010000
2038 17:45:54.082852 IOAPIC: vector 0x3d value 0x00000000 0x00010000
2039 17:45:54.086548 IOAPIC: vector 0x3e value 0x00000000 0x00010000
2040 17:45:54.092910 IOAPIC: vector 0x3f value 0x00000000 0x00010000
2041 17:45:54.096229 IOAPIC: vector 0x40 value 0x00000000 0x00010000
2042 17:45:54.102795 IOAPIC: vector 0x41 value 0x00000000 0x00010000
2043 17:45:54.105989 IOAPIC: vector 0x42 value 0x00000000 0x00010000
2044 17:45:54.112756 IOAPIC: vector 0x43 value 0x00000000 0x00010000
2045 17:45:54.115975 IOAPIC: vector 0x44 value 0x00000000 0x00010000
2046 17:45:54.119229 IOAPIC: vector 0x45 value 0x00000000 0x00010000
2047 17:45:54.126003 IOAPIC: vector 0x46 value 0x00000000 0x00010000
2048 17:45:54.129355 IOAPIC: vector 0x47 value 0x00000000 0x00010000
2049 17:45:54.136344 IOAPIC: vector 0x48 value 0x00000000 0x00010000
2050 17:45:54.139510 IOAPIC: vector 0x49 value 0x00000000 0x00010000
2051 17:45:54.145728 IOAPIC: vector 0x4a value 0x00000000 0x00010000
2052 17:45:54.149441 IOAPIC: vector 0x4b value 0x00000000 0x00010000
2053 17:45:54.152738 IOAPIC: vector 0x4c value 0x00000000 0x00010000
2054 17:45:54.159289 IOAPIC: vector 0x4d value 0x00000000 0x00010000
2055 17:45:54.162883 IOAPIC: vector 0x4e value 0x00000000 0x00010000
2056 17:45:54.169226 IOAPIC: vector 0x4f value 0x00000000 0x00010000
2057 17:45:54.172795 IOAPIC: vector 0x50 value 0x00000000 0x00010000
2058 17:45:54.179249 IOAPIC: vector 0x51 value 0x00000000 0x00010000
2059 17:45:54.182534 IOAPIC: vector 0x52 value 0x00000000 0x00010000
2060 17:45:54.189134 IOAPIC: vector 0x53 value 0x00000000 0x00010000
2061 17:45:54.193210 IOAPIC: vector 0x54 value 0x00000000 0x00010000
2062 17:45:54.196157 IOAPIC: vector 0x55 value 0x00000000 0x00010000
2063 17:45:54.202399 IOAPIC: vector 0x56 value 0x00000000 0x00010000
2064 17:45:54.205732 IOAPIC: vector 0x57 value 0x00000000 0x00010000
2065 17:45:54.212649 IOAPIC: vector 0x58 value 0x00000000 0x00010000
2066 17:45:54.216047 IOAPIC: vector 0x59 value 0x00000000 0x00010000
2067 17:45:54.222649 IOAPIC: vector 0x5a value 0x00000000 0x00010000
2068 17:45:54.225837 IOAPIC: vector 0x5b value 0x00000000 0x00010000
2069 17:45:54.232664 IOAPIC: vector 0x5c value 0x00000000 0x00010000
2070 17:45:54.235717 IOAPIC: vector 0x5d value 0x00000000 0x00010000
2071 17:45:54.239368 IOAPIC: vector 0x5e value 0x00000000 0x00010000
2072 17:45:54.245805 IOAPIC: vector 0x5f value 0x00000000 0x00010000
2073 17:45:54.249353 IOAPIC: vector 0x60 value 0x00000000 0x00010000
2074 17:45:54.255434 IOAPIC: vector 0x61 value 0x00000000 0x00010000
2075 17:45:54.258800 IOAPIC: vector 0x62 value 0x00000000 0x00010000
2076 17:45:54.265645 IOAPIC: vector 0x63 value 0x00000000 0x00010000
2077 17:45:54.269022 IOAPIC: vector 0x64 value 0x00000000 0x00010000
2078 17:45:54.275395 IOAPIC: vector 0x65 value 0x00000000 0x00010000
2079 17:45:54.278749 IOAPIC: vector 0x66 value 0x00000000 0x00010000
2080 17:45:54.282084 IOAPIC: vector 0x67 value 0x00000000 0x00010000
2081 17:45:54.289118 IOAPIC: vector 0x68 value 0x00000000 0x00010000
2082 17:45:54.292454 IOAPIC: vector 0x69 value 0x00000000 0x00010000
2083 17:45:54.299053 IOAPIC: vector 0x6a value 0x00000000 0x00010000
2084 17:45:54.302263 IOAPIC: vector 0x6b value 0x00000000 0x00010000
2085 17:45:54.308806 IOAPIC: vector 0x6c value 0x00000000 0x00010000
2086 17:45:54.312525 IOAPIC: vector 0x6d value 0x00000000 0x00010000
2087 17:45:54.318710 IOAPIC: vector 0x6e value 0x00000000 0x00010000
2088 17:45:54.322223 IOAPIC: vector 0x6f value 0x00000000 0x00010000
2089 17:45:54.325636 IOAPIC: vector 0x70 value 0x00000000 0x00010000
2090 17:45:54.332141 IOAPIC: vector 0x71 value 0x00000000 0x00010000
2091 17:45:54.335285 IOAPIC: vector 0x72 value 0x00000000 0x00010000
2092 17:45:54.342170 IOAPIC: vector 0x73 value 0x00000000 0x00010000
2093 17:45:54.345013 IOAPIC: vector 0x74 value 0x00000000 0x00010000
2094 17:45:54.351566 IOAPIC: vector 0x75 value 0x00000000 0x00010000
2095 17:45:54.355036 IOAPIC: vector 0x76 value 0x00000000 0x00010000
2096 17:45:54.361628 IOAPIC: vector 0x77 value 0x00000000 0x00010000
2097 17:45:54.364725 IOAPIC: Bootstrap Processor Local APIC = 0x00
2098 17:45:54.368159 IOAPIC: vector 0x00 value 0x00000000 0x00000700
2099 17:45:54.375280 PCI: 00:1f.0 init finished in 607 msecs
2100 17:45:54.375743 PCI: 00:1f.2 init
2101 17:45:54.378355 apm_control: Disabling ACPI.
2102 17:45:54.383255 APMC done.
2103 17:45:54.386391 PCI: 00:1f.2 init finished in 6 msecs
2104 17:45:54.389607 PCI: 00:1f.3 init
2105 17:45:54.392959 PCI: 00:1f.3 init finished in 0 msecs
2106 17:45:54.393382 PCI: 01:00.0 init
2107 17:45:54.396174 PCI: 01:00.0 init finished in 0 msecs
2108 17:45:54.400063 PNP: 0c09.0 init
2109 17:45:54.403367 Google Chrome EC uptime: 12.478 seconds
2110 17:45:54.409543 Google Chrome AP resets since EC boot: 1
2111 17:45:54.412940 Google Chrome most recent AP reset causes:
2112 17:45:54.416198 0.343: 32775 shutdown: entering G3
2113 17:45:54.423119 Google Chrome EC reset flags at last EC boot: reset-pin | sysjump
2114 17:45:54.426410 PNP: 0c09.0 init finished in 23 msecs
2115 17:45:54.429587 GENERIC: 0.0 init
2116 17:45:54.433247 GENERIC: 0.0 init finished in 0 msecs
2117 17:45:54.433674 GENERIC: 1.0 init
2118 17:45:54.439390 GENERIC: 1.0 init finished in 0 msecs
2119 17:45:54.439836 Devices initialized
2120 17:45:54.442663 Show all devs... After init.
2121 17:45:54.446353 Root Device: enabled 1
2122 17:45:54.449595 CPU_CLUSTER: 0: enabled 1
2123 17:45:54.450022 DOMAIN: 0000: enabled 1
2124 17:45:54.452732 GPIO: 0: enabled 1
2125 17:45:54.455986 PCI: 00:00.0: enabled 1
2126 17:45:54.456412 PCI: 00:01.0: enabled 0
2127 17:45:54.459813 PCI: 00:01.1: enabled 0
2128 17:45:54.462560 PCI: 00:02.0: enabled 1
2129 17:45:54.466302 PCI: 00:04.0: enabled 1
2130 17:45:54.466768 PCI: 00:05.0: enabled 0
2131 17:45:54.469680 PCI: 00:06.0: enabled 1
2132 17:45:54.472841 PCI: 00:06.2: enabled 0
2133 17:45:54.473268 PCI: 00:07.0: enabled 0
2134 17:45:54.475951 PCI: 00:07.1: enabled 0
2135 17:45:54.479553 PCI: 00:07.2: enabled 0
2136 17:45:54.483056 PCI: 00:07.3: enabled 0
2137 17:45:54.483483 PCI: 00:08.0: enabled 0
2138 17:45:54.486180 PCI: 00:09.0: enabled 0
2139 17:45:54.489751 PCI: 00:0a.0: enabled 1
2140 17:45:54.493284 PCI: 00:0d.0: enabled 1
2141 17:45:54.493820 PCI: 00:0d.1: enabled 0
2142 17:45:54.496200 PCI: 00:0d.2: enabled 0
2143 17:45:54.499294 PCI: 00:0d.3: enabled 0
2144 17:45:54.502894 PCI: 00:0e.0: enabled 0
2145 17:45:54.503444 PCI: 00:10.0: enabled 0
2146 17:45:54.505797 PCI: 00:10.1: enabled 0
2147 17:45:54.509671 PCI: 00:10.6: enabled 0
2148 17:45:54.512879 PCI: 00:10.7: enabled 0
2149 17:45:54.513469 PCI: 00:12.0: enabled 0
2150 17:45:54.516544 PCI: 00:12.6: enabled 0
2151 17:45:54.519493 PCI: 00:12.7: enabled 0
2152 17:45:54.520024 PCI: 00:13.0: enabled 0
2153 17:45:54.523229 PCI: 00:14.0: enabled 1
2154 17:45:54.526159 PCI: 00:14.1: enabled 0
2155 17:45:54.529507 PCI: 00:14.2: enabled 1
2156 17:45:54.530040 PCI: 00:14.3: enabled 1
2157 17:45:54.532382 PCI: 00:15.0: enabled 1
2158 17:45:54.536517 PCI: 00:15.1: enabled 1
2159 17:45:54.539162 PCI: 00:15.2: enabled 0
2160 17:45:54.539590 PCI: 00:15.3: enabled 1
2161 17:45:54.542717 PCI: 00:16.0: enabled 1
2162 17:45:54.545629 PCI: 00:16.1: enabled 0
2163 17:45:54.549600 PCI: 00:16.2: enabled 0
2164 17:45:54.550130 PCI: 00:16.3: enabled 0
2165 17:45:54.552679 PCI: 00:16.4: enabled 0
2166 17:45:54.555692 PCI: 00:16.5: enabled 0
2167 17:45:54.556216 PCI: 00:17.0: enabled 0
2168 17:45:54.559260 PCI: 00:19.0: enabled 0
2169 17:45:54.562475 PCI: 00:19.1: enabled 1
2170 17:45:54.565903 PCI: 00:19.2: enabled 0
2171 17:45:54.566334 PCI: 00:1a.0: enabled 0
2172 17:45:54.569353 PCI: 00:1c.0: enabled 0
2173 17:45:54.572657 PCI: 00:1c.1: enabled 0
2174 17:45:54.575657 PCI: 00:1c.2: enabled 0
2175 17:45:54.576084 PCI: 00:1c.3: enabled 0
2176 17:45:54.579235 PCI: 00:1c.4: enabled 0
2177 17:45:54.582346 PCI: 00:1c.5: enabled 0
2178 17:45:54.585680 PCI: 00:1c.6: enabled 0
2179 17:45:54.586105 PCI: 00:1c.7: enabled 0
2180 17:45:54.589412 PCI: 00:1d.0: enabled 0
2181 17:45:54.592906 PCI: 00:1d.1: enabled 0
2182 17:45:54.595563 PCI: 00:1d.2: enabled 0
2183 17:45:54.595988 PCI: 00:1d.3: enabled 0
2184 17:45:54.598810 PCI: 00:1e.0: enabled 1
2185 17:45:54.602497 PCI: 00:1e.1: enabled 0
2186 17:45:54.603074 PCI: 00:1e.2: enabled 0
2187 17:45:54.605809 PCI: 00:1e.3: enabled 1
2188 17:45:54.609121 PCI: 00:1f.0: enabled 1
2189 17:45:54.612781 PCI: 00:1f.1: enabled 0
2190 17:45:54.613316 PCI: 00:1f.2: enabled 1
2191 17:45:54.616045 PCI: 00:1f.3: enabled 1
2192 17:45:54.618923 PCI: 00:1f.4: enabled 0
2193 17:45:54.622638 PCI: 00:1f.5: enabled 1
2194 17:45:54.623183 PCI: 00:1f.6: enabled 0
2195 17:45:54.625500 PCI: 00:1f.7: enabled 0
2196 17:45:54.629055 GENERIC: 0.0: enabled 1
2197 17:45:54.632304 GENERIC: 0.0: enabled 1
2198 17:45:54.632839 GENERIC: 1.0: enabled 1
2199 17:45:54.636000 GENERIC: 0.0: enabled 1
2200 17:45:54.639273 GENERIC: 1.0: enabled 1
2201 17:45:54.639805 USB0 port 0: enabled 1
2202 17:45:54.642397 USB0 port 0: enabled 1
2203 17:45:54.645864 GENERIC: 0.0: enabled 1
2204 17:45:54.648997 I2C: 00:1a: enabled 1
2205 17:45:54.649530 I2C: 00:31: enabled 1
2206 17:45:54.651949 I2C: 00:32: enabled 1
2207 17:45:54.655475 I2C: 00:50: enabled 1
2208 17:45:54.655960 I2C: 00:10: enabled 1
2209 17:45:54.658947 I2C: 00:15: enabled 1
2210 17:45:54.662052 I2C: 00:2c: enabled 1
2211 17:45:54.662486 GENERIC: 0.0: enabled 1
2212 17:45:54.665252 SPI: 00: enabled 1
2213 17:45:54.668705 PNP: 0c09.0: enabled 1
2214 17:45:54.669148 GENERIC: 0.0: enabled 1
2215 17:45:54.671923 USB3 port 0: enabled 1
2216 17:45:54.675377 USB3 port 1: enabled 0
2217 17:45:54.678650 USB3 port 2: enabled 1
2218 17:45:54.679078 USB3 port 3: enabled 0
2219 17:45:54.681762 USB2 port 0: enabled 1
2220 17:45:54.685446 USB2 port 1: enabled 0
2221 17:45:54.685892 USB2 port 2: enabled 1
2222 17:45:54.688652 USB2 port 3: enabled 0
2223 17:45:54.691922 USB2 port 4: enabled 0
2224 17:45:54.692344 USB2 port 5: enabled 1
2225 17:45:54.695256 USB2 port 6: enabled 0
2226 17:45:54.699218 USB2 port 7: enabled 0
2227 17:45:54.702402 USB2 port 8: enabled 1
2228 17:45:54.702978 USB2 port 9: enabled 1
2229 17:45:54.705689 USB3 port 0: enabled 1
2230 17:45:54.708919 USB3 port 1: enabled 0
2231 17:45:54.709464 USB3 port 2: enabled 0
2232 17:45:54.712195 USB3 port 3: enabled 0
2233 17:45:54.715132 GENERIC: 0.0: enabled 1
2234 17:45:54.718804 GENERIC: 1.0: enabled 1
2235 17:45:54.719352 APIC: 00: enabled 1
2236 17:45:54.722011 APIC: 16: enabled 1
2237 17:45:54.722541 APIC: 10: enabled 1
2238 17:45:54.725716 APIC: 12: enabled 1
2239 17:45:54.728935 APIC: 14: enabled 1
2240 17:45:54.729474 APIC: 09: enabled 1
2241 17:45:54.732059 APIC: 08: enabled 1
2242 17:45:54.735518 APIC: 01: enabled 1
2243 17:45:54.736049 PCI: 01:00.0: enabled 1
2244 17:45:54.742342 BS: BS_DEV_INIT run times (exec / console): 10 / 1133 ms
2245 17:45:54.745696 FMAP: area RW_ELOG found @ f20000 (16384 bytes)
2246 17:45:54.751878 ELOG: NV offset 0xf20000 size 0x4000
2247 17:45:54.758707 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
2248 17:45:54.765073 ELOG: Event(17) added with size 13 at 2023-10-09 17:45:54 UTC
2249 17:45:54.772133 ELOG: Event(9E) added with size 10 at 2023-10-09 17:45:54 UTC
2250 17:45:54.777954 ELOG: Event(9F) added with size 14 at 2023-10-09 17:45:54 UTC
2251 17:45:54.784674 BS: BS_DEV_INIT exit times (exec / console): 3 / 33 ms
2252 17:45:54.791459 ELOG: Event(A0) added with size 9 at 2023-10-09 17:45:54 UTC
2253 17:45:54.794918 elog_add_boot_reason: Logged dev mode boot
2254 17:45:54.801902 BS: BS_POST_DEVICE entry times (exec / console): 1 / 10 ms
2255 17:45:54.802438 Finalize devices...
2256 17:45:54.804891 PCI: 00:16.0 final
2257 17:45:54.805317 PCI: 00:1f.2 final
2258 17:45:54.808324 GENERIC: 0.0 final
2259 17:45:54.814494 added type-c port0 info to cbmem: usb2:1 usb3:1 sbu:0 data:0
2260 17:45:54.815079 GENERIC: 1.0 final
2261 17:45:54.821345 added type-c port1 info to cbmem: usb2:3 usb3:3 sbu:0 data:0
2262 17:45:54.824540 Devices finalized
2263 17:45:54.831394 BS: BS_POST_DEVICE run times (exec / console): 0 / 24 ms
2264 17:45:54.834533 FMAP: area RW_NVRAM found @ f2b000 (24576 bytes)
2265 17:45:54.841026 BS: BS_POST_DEVICE exit times (exec / console): 0 / 5 ms
2266 17:45:54.844476 ME: HFSTS1 : 0x90000245
2267 17:45:54.851410 ME: HFSTS2 : 0x82100116
2268 17:45:54.854119 ME: HFSTS3 : 0x00000050
2269 17:45:54.857782 ME: HFSTS4 : 0x00004000
2270 17:45:54.864448 ME: HFSTS5 : 0x00000000
2271 17:45:54.867780 ME: HFSTS6 : 0x40600006
2272 17:45:54.871232 ME: Manufacturing Mode : NO
2273 17:45:54.874291 ME: SPI Protection Mode Enabled : YES
2274 17:45:54.877692 ME: FPFs Committed : YES
2275 17:45:54.884032 ME: Manufacturing Vars Locked : YES
2276 17:45:54.887306 ME: FW Partition Table : OK
2277 17:45:54.890900 ME: Bringup Loader Failure : NO
2278 17:45:54.894352 ME: Firmware Init Complete : YES
2279 17:45:54.897728 ME: Boot Options Present : NO
2280 17:45:54.900940 ME: Update In Progress : NO
2281 17:45:54.904423 ME: D0i3 Support : YES
2282 17:45:54.907634 ME: Low Power State Enabled : NO
2283 17:45:54.914223 ME: CPU Replaced : YES
2284 17:45:54.917375 ME: CPU Replacement Valid : YES
2285 17:45:54.920557 ME: Current Working State : 5
2286 17:45:54.924105 ME: Current Operation State : 1
2287 17:45:54.927884 ME: Current Operation Mode : 0
2288 17:45:54.930610 ME: Error Code : 0
2289 17:45:54.934089 ME: Enhanced Debug Mode : NO
2290 17:45:54.936879 ME: CPU Debug Disabled : YES
2291 17:45:54.944111 ME: TXT Support : NO
2292 17:45:54.947277 ME: WP for RO is enabled : YES
2293 17:45:54.950012 ME: RO write protection scope - Start=0x1000, End=0x15AFFF
2294 17:45:54.957213 BS: BS_OS_RESUME_CHECK exit times (exec / console): 0 / 111 ms
2295 17:45:54.960045 Ramoops buffer: 0x100000@0x76899000.
2296 17:45:54.967445 BS: BS_WRITE_TABLES entry times (exec / console): 0 / 4 ms
2297 17:45:54.973914 CBFS: Found 'fallback/dsdt.aml' @0x787c0 size 0x4fd1 in mcache @0x76add18c
2298 17:45:54.977314 CBFS: 'fallback/slic' not found.
2299 17:45:54.983441 ACPI: Writing ACPI tables at 7686d000.
2300 17:45:54.983875 ACPI: * FACS
2301 17:45:54.987016 ACPI: * DSDT
2302 17:45:54.993784 PCI space above 4GB MMIO is at 0x27fc00000, len = 0x7d80400000
2303 17:45:54.997011 ACPI: * FADT
2304 17:45:54.997435 SCI is IRQ9
2305 17:45:55.000340 ACPI: added table 1/32, length now 40
2306 17:45:55.003388 ACPI: * SSDT
2307 17:45:55.006620 Found 1 CPU(s) with 6/8 physical/logical core(s) each.
2308 17:45:55.014476 \_SB.PCI0.PEPD: Intel Power Engine Plug-in
2309 17:45:55.017797 \_SB.PCI0.PMC: Intel Alderlake at PCI: 00:1f.2
2310 17:45:55.020717 \_SB.DPTF: Intel DPTF at GENERIC: 0.0
2311 17:45:55.027429 CBFS: Found 'wifi_sar_0.hex' @0x1bbd00 size 0xe6 in mcache @0x76add3e4
2312 17:45:55.034218 \_SB.PCI0.CNVW: WIFI Device GENERIC: 0.0
2313 17:45:55.040976 \_SB.PCI0.I2C0.NAU8: Nuvoton NAU8825 Codec address 01ah irq 0
2314 17:45:55.044433 \_SB.PCI0.I2C0.MAXR: Maxim MAX98373 Codec address 031h
2315 17:45:55.051170 \_SB.PCI0.I2C0.MAXL: Maxim MAX98373 Codec address 032h
2316 17:45:55.053947 \_SB.PCI0.I2C1.TPMI: I2C TPM at I2C: 00:50
2317 17:45:55.060900 \_SB.PCI0.I2C3.H010: ELAN Touchscreen at I2C: 00:10
2318 17:45:55.064411 \_SB.PCI0.I2C5.D015: ELAN Touchpad at I2C: 00:15
2319 17:45:55.070955 \_SB.PCI0.I2C5.H02C: Synaptics Touchpad at I2C: 00:2c
2320 17:45:55.074101 \_SB.PCI0.SPI1.CRFP: SPI Device at SPI: 00
2321 17:45:55.081556 PS2K: Physmap: [ EA E7 91 92 93 94 95 A0 AE B0 ]
2322 17:45:55.085108 PS2K: Passing 80 keymaps to kernel
2323 17:45:55.092141 \_SB.PCI0.TXHC.RHUB.SS01: USB3 Type-C Port C0 (MLB) at USB3 port 0
2324 17:45:55.098846 \_SB.PCI0.TXHC.RHUB.SS03: USB3 Type-C Port C1 (DB) at USB3 port 2
2325 17:45:55.104970 \_SB.PCI0.XHCI.RHUB.HS01: USB2 Type-C Port C0 (MLB) at USB2 port 0
2326 17:45:55.112121 \_SB.PCI0.XHCI.RHUB.HS03: USB2 Type-C Port C1 (DB) at USB2 port 2
2327 17:45:55.118420 \_SB.PCI0.XHCI.RHUB.HS06: USB2 Camera at USB2 port 5
2328 17:45:55.125334 \_SB.PCI0.XHCI.RHUB.HS09: USB2 Type-A Port A0 (DB) at USB2 port 8
2329 17:45:55.128618 \_SB.PCI0.XHCI.RHUB.HS10: USB2 Bluetooth at USB2 port 9
2330 17:45:55.135129 \_SB.PCI0.XHCI.RHUB.SS01: USB3 Type-A Port A0 (DB) at USB3 port 0
2331 17:45:55.142243 \_SB.PCI0.PMC.MUX.CON0: Intel PMC MUX CONN Driver at GENERIC: 0.0
2332 17:45:55.148288 \_SB.PCI0.PMC.MUX.CON1: Intel PMC MUX CONN Driver at GENERIC: 1.0
2333 17:45:55.151916 ACPI: added table 2/32, length now 44
2334 17:45:55.154520 ACPI: * MCFG
2335 17:45:55.158168 ACPI: added table 3/32, length now 48
2336 17:45:55.158741 ACPI: * TPM2
2337 17:45:55.161499 TPM2 log created at 0x7685d000
2338 17:45:55.168419 ACPI: added table 4/32, length now 52
2339 17:45:55.168946 ACPI: * LPIT
2340 17:45:55.171779 ACPI: added table 5/32, length now 56
2341 17:45:55.175244 ACPI: * MADT
2342 17:45:55.175770 SCI is IRQ9
2343 17:45:55.178391 ACPI: added table 6/32, length now 60
2344 17:45:55.181291 cmd_reg from pmc_make_ipc_cmd 1052838
2345 17:45:55.188437 CL PMC desc table: numb of regions is 0x2 at addr 0xfe0121bc
2346 17:45:55.194996 CL PMC desc table: region 0x0 has size 0x280 at offset 0x2200
2347 17:45:55.201836 CL PMC desc table: region 0x1 has size 0x80 at offset 0x3e00
2348 17:45:55.205091 PMC CrashLog size in discovery mode: 0xC00
2349 17:45:55.208472 cpu crashlog bar addr: 0x80640000
2350 17:45:55.211764 cpu discovery table offset: 0x6030
2351 17:45:55.217982 cpu_crashlog_discovery_table buffer count: 0x3
2352 17:45:55.224888 cpu_crashlog_discovery_table buffer: 0x0 size: 0x700 offset: 0x0
2353 17:45:55.231151 cpu_crashlog_discovery_table buffer: 0x1 size: 0x2b0 offset: 0x4000
2354 17:45:55.238005 cpu_crashlog_discovery_table buffer: 0x2 size: 0x370 offset: 0x5000
2355 17:45:55.241429 PMC crashLog size in discovery mode : 0xC00
2356 17:45:55.247864 Invalid data 0x0 at offset 0x2200 from addr 0xfe010000 of PMC SRAM.
2357 17:45:55.254757 discover mode PMC crashlog size adjusted to: 0x200
2358 17:45:55.260882 Invalid data 0x0 at offset 0x3e00 from addr 0xfe010000 of PMC SRAM.
2359 17:45:55.264821 discover mode PMC crashlog size adjusted to: 0x0
2360 17:45:55.267490 m_cpu_crashLog_size : 0x3480 bytes
2361 17:45:55.271203 CPU crashLog present.
2362 17:45:55.274461 CPU crash data size: 0x3480 bytes in 0x3 region(s).
2363 17:45:55.284306 Invalid data 0x0 at offset 0x0 from addr 0x80640000 of telemetry SRAM.
2364 17:45:55.284859 current = 76876550
2365 17:45:55.287406 ACPI: * DMAR
2366 17:45:55.291092 ACPI: added table 7/32, length now 64
2367 17:45:55.294507 ACPI: added table 8/32, length now 68
2368 17:45:55.294986 ACPI: * HPET
2369 17:45:55.300742 ACPI: added table 9/32, length now 72
2370 17:45:55.301245 ACPI: done.
2371 17:45:55.304102 ACPI tables: 38528 bytes.
2372 17:45:55.307451 smbios_write_tables: 76857000
2373 17:45:55.310976 EC returned error result code 3
2374 17:45:55.314177 Couldn't obtain OEM name from CBI
2375 17:45:55.317368 Create SMBIOS type 16
2376 17:45:55.317795 Create SMBIOS type 17
2377 17:45:55.320750 Create SMBIOS type 20
2378 17:45:55.324312 GENERIC: 0.0 (WIFI Device)
2379 17:45:55.327392 SMBIOS tables: 2156 bytes.
2380 17:45:55.330688 Writing table forward entry at 0x00000500
2381 17:45:55.337382 Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 7955
2382 17:45:55.340751 Writing coreboot table at 0x76891000
2383 17:45:55.347532 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
2384 17:45:55.350966 1. 0000000000001000-000000000009ffff: RAM
2385 17:45:55.357682 2. 00000000000a0000-00000000000fffff: RESERVED
2386 17:45:55.360493 3. 0000000000100000-0000000076856fff: RAM
2387 17:45:55.367541 4. 0000000076857000-0000000076a2efff: CONFIGURATION TABLES
2388 17:45:55.370462 5. 0000000076a2f000-0000000076ab7fff: RAMSTAGE
2389 17:45:55.377723 6. 0000000076ab8000-0000000076ffffff: CONFIGURATION TABLES
2390 17:45:55.380456 7. 0000000077000000-00000000803fffff: RESERVED
2391 17:45:55.387039 8. 00000000c0000000-00000000cfffffff: RESERVED
2392 17:45:55.390350 9. 00000000f8000000-00000000f9ffffff: RESERVED
2393 17:45:55.396950 10. 00000000fb000000-00000000fb000fff: RESERVED
2394 17:45:55.400545 11. 00000000fc800000-00000000fe7fffff: RESERVED
2395 17:45:55.407175 12. 00000000feb00000-00000000feb7ffff: RESERVED
2396 17:45:55.410306 13. 00000000fec00000-00000000fecfffff: RESERVED
2397 17:45:55.413823 14. 00000000fed40000-00000000fed6ffff: RESERVED
2398 17:45:55.420083 15. 00000000fed80000-00000000fed87fff: RESERVED
2399 17:45:55.423259 16. 00000000fed90000-00000000fed92fff: RESERVED
2400 17:45:55.430024 17. 00000000feda0000-00000000feda1fff: RESERVED
2401 17:45:55.433575 18. 00000000fedc0000-00000000feddffff: RESERVED
2402 17:45:55.439530 19. 0000000100000000-000000027fbfffff: RAM
2403 17:45:55.439967 Passing 4 GPIOs to payload:
2404 17:45:55.446311 NAME | PORT | POLARITY | VALUE
2405 17:45:55.452840 lid | undefined | high | high
2406 17:45:55.456060 power | undefined | high | low
2407 17:45:55.462515 oprom | undefined | high | low
2408 17:45:55.466063 EC in RW | 0x00000151 | high | high
2409 17:45:55.469616 Board ID: 3
2410 17:45:55.469887 FW config: 0x131
2411 17:45:55.476650 Wrote coreboot table at: 0x76891000, 0x6e4 bytes, checksum e946
2412 17:45:55.479810 coreboot table: 1788 bytes.
2413 17:45:55.482795 IMD ROOT 0. 0x76fff000 0x00001000
2414 17:45:55.486141 IMD SMALL 1. 0x76ffe000 0x00001000
2415 17:45:55.489924 FSP MEMORY 2. 0x76afe000 0x00500000
2416 17:45:55.495967 CONSOLE 3. 0x76ade000 0x00020000
2417 17:45:55.499864 RW MCACHE 4. 0x76add000 0x0000043c
2418 17:45:55.503108 RO MCACHE 5. 0x76adc000 0x00000fd8
2419 17:45:55.506158 FMAP 6. 0x76adb000 0x0000064a
2420 17:45:55.509739 TIME STAMP 7. 0x76ada000 0x00000910
2421 17:45:55.513061 VBOOT WORK 8. 0x76ac6000 0x00014000
2422 17:45:55.516598 MEM INFO 9. 0x76ac5000 0x000003b8
2423 17:45:55.519774 ROMSTG STCK10. 0x76ac4000 0x00001000
2424 17:45:55.526491 AFTER CAR 11. 0x76ab8000 0x0000c000
2425 17:45:55.529722 RAMSTAGE 12. 0x76a2e000 0x0008a000
2426 17:45:55.532821 ACPI BERT 13. 0x76a1e000 0x00010000
2427 17:45:55.536272 CHROMEOS NVS14. 0x76a1d000 0x00000f00
2428 17:45:55.539785 REFCODE 15. 0x769ae000 0x0006f000
2429 17:45:55.542986 SMM BACKUP 16. 0x7699e000 0x00010000
2430 17:45:55.546361 IGD OPREGION17. 0x76999000 0x00004203
2431 17:45:55.549563 RAMOOPS 18. 0x76899000 0x00100000
2432 17:45:55.556100 COREBOOT 19. 0x76891000 0x00008000
2433 17:45:55.559782 ACPI 20. 0x7686d000 0x00024000
2434 17:45:55.562995 TPM2 TCGLOG21. 0x7685d000 0x00010000
2435 17:45:55.566123 PMC CRASHLOG22. 0x7685c000 0x00000c00
2436 17:45:55.569723 CPU CRASHLOG23. 0x76858000 0x00003480
2437 17:45:55.572875 SMBIOS 24. 0x76857000 0x00001000
2438 17:45:55.576126 IMD small region:
2439 17:45:55.579954 IMD ROOT 0. 0x76ffec00 0x00000400
2440 17:45:55.582863 FSP RUNTIME 1. 0x76ffebe0 0x00000004
2441 17:45:55.586443 VPD 2. 0x76ffeb60 0x0000006c
2442 17:45:55.589623 POWER STATE 3. 0x76ffeb00 0x00000044
2443 17:45:55.596444 ROMSTAGE 4. 0x76ffeae0 0x00000004
2444 17:45:55.600004 ACPI GNVS 5. 0x76ffea80 0x00000048
2445 17:45:55.603252 TYPE_C INFO 6. 0x76ffea60 0x0000000c
2446 17:45:55.609772 BS: BS_WRITE_TABLES run times (exec / console): 7 / 628 ms
2447 17:45:55.613116 MTRR: Physical address space:
2448 17:45:55.619419 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
2449 17:45:55.622898 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
2450 17:45:55.629225 0x00000000000c0000 - 0x0000000077000000 size 0x76f40000 type 6
2451 17:45:55.636590 0x0000000077000000 - 0x0000000090000000 size 0x19000000 type 0
2452 17:45:55.642810 0x0000000090000000 - 0x00000000a0000000 size 0x10000000 type 1
2453 17:45:55.649466 0x00000000a0000000 - 0x0000000100000000 size 0x60000000 type 0
2454 17:45:55.655758 0x0000000100000000 - 0x000000027fc00000 size 0x17fc00000 type 6
2455 17:45:55.659262 MTRR: Fixed MSR 0x250 0x0606060606060606
2456 17:45:55.662520 MTRR: Fixed MSR 0x258 0x0606060606060606
2457 17:45:55.669117 MTRR: Fixed MSR 0x259 0x0000000000000000
2458 17:45:55.672586 MTRR: Fixed MSR 0x268 0x0606060606060606
2459 17:45:55.675792 MTRR: Fixed MSR 0x269 0x0606060606060606
2460 17:45:55.678835 MTRR: Fixed MSR 0x26a 0x0606060606060606
2461 17:45:55.685375 MTRR: Fixed MSR 0x26b 0x0606060606060606
2462 17:45:55.688650 MTRR: Fixed MSR 0x26c 0x0606060606060606
2463 17:45:55.692316 MTRR: Fixed MSR 0x26d 0x0606060606060606
2464 17:45:55.695266 MTRR: Fixed MSR 0x26e 0x0606060606060606
2465 17:45:55.698520 MTRR: Fixed MSR 0x26f 0x0606060606060606
2466 17:45:55.703553 call enable_fixed_mtrr()
2467 17:45:55.706760 CPU physical address size: 39 bits
2468 17:45:55.713561 MTRR: default type WB/UC MTRR counts: 6/6.
2469 17:45:55.716818 MTRR: UC selected as default type.
2470 17:45:55.723340 MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
2471 17:45:55.726620 MTRR: 1 base 0x0000000077000000 mask 0x0000007fff000000 type 0
2472 17:45:55.733137 MTRR: 2 base 0x0000000078000000 mask 0x0000007ff8000000 type 0
2473 17:45:55.739790 MTRR: 3 base 0x0000000090000000 mask 0x0000007ff0000000 type 1
2474 17:45:55.746734 MTRR: 4 base 0x0000000100000000 mask 0x0000007f00000000 type 6
2475 17:45:55.753302 MTRR: 5 base 0x0000000200000000 mask 0x0000007f80000000 type 6
2476 17:45:55.759669 MTRR: Fixed MSR 0x250 0x0606060606060606
2477 17:45:55.762943 MTRR: Fixed MSR 0x258 0x0606060606060606
2478 17:45:55.766378 MTRR: Fixed MSR 0x259 0x0000000000000000
2479 17:45:55.769603 MTRR: Fixed MSR 0x268 0x0606060606060606
2480 17:45:55.776326 MTRR: Fixed MSR 0x269 0x0606060606060606
2481 17:45:55.779538 MTRR: Fixed MSR 0x26a 0x0606060606060606
2482 17:45:55.782775 MTRR: Fixed MSR 0x26b 0x0606060606060606
2483 17:45:55.786466 MTRR: Fixed MSR 0x26c 0x0606060606060606
2484 17:45:55.792972 MTRR: Fixed MSR 0x26d 0x0606060606060606
2485 17:45:55.796358 MTRR: Fixed MSR 0x26e 0x0606060606060606
2486 17:45:55.799801 MTRR: Fixed MSR 0x26f 0x0606060606060606
2487 17:45:55.802819 MTRR: Fixed MSR 0x250 0x0606060606060606
2488 17:45:55.806447 MTRR: Fixed MSR 0x250 0x0606060606060606
2489 17:45:55.812826 MTRR: Fixed MSR 0x258 0x0606060606060606
2490 17:45:55.816628 MTRR: Fixed MSR 0x259 0x0000000000000000
2491 17:45:55.819779 MTRR: Fixed MSR 0x268 0x0606060606060606
2492 17:45:55.822949 MTRR: Fixed MSR 0x269 0x0606060606060606
2493 17:45:55.829586 MTRR: Fixed MSR 0x250 0x0606060606060606
2494 17:45:55.832715 MTRR: Fixed MSR 0x250 0x0606060606060606
2495 17:45:55.836211 MTRR: Fixed MSR 0x250 0x0606060606060606
2496 17:45:55.839503 MTRR: Fixed MSR 0x258 0x0606060606060606
2497 17:45:55.846195 MTRR: Fixed MSR 0x259 0x0000000000000000
2498 17:45:55.849419 MTRR: Fixed MSR 0x268 0x0606060606060606
2499 17:45:55.852902 MTRR: Fixed MSR 0x269 0x0606060606060606
2500 17:45:55.856182 MTRR: Fixed MSR 0x258 0x0606060606060606
2501 17:45:55.859474 MTRR: Fixed MSR 0x259 0x0000000000000000
2502 17:45:55.865789 MTRR: Fixed MSR 0x268 0x0606060606060606
2503 17:45:55.869102 MTRR: Fixed MSR 0x269 0x0606060606060606
2504 17:45:55.872461 MTRR: Fixed MSR 0x26a 0x0606060606060606
2505 17:45:55.875771 MTRR: Fixed MSR 0x26b 0x0606060606060606
2506 17:45:55.882211 MTRR: Fixed MSR 0x26c 0x0606060606060606
2507 17:45:55.885682 MTRR: Fixed MSR 0x26d 0x0606060606060606
2508 17:45:55.889356 MTRR: Fixed MSR 0x26e 0x0606060606060606
2509 17:45:55.892536 MTRR: Fixed MSR 0x26f 0x0606060606060606
2510 17:45:55.898999 MTRR: Fixed MSR 0x258 0x0606060606060606
2511 17:45:55.899082 call enable_fixed_mtrr()
2512 17:45:55.902159 call enable_fixed_mtrr()
2513 17:45:55.906139 MTRR: Fixed MSR 0x258 0x0606060606060606
2514 17:45:55.908994 CPU physical address size: 39 bits
2515 17:45:55.915730 MTRR: Fixed MSR 0x259 0x0000000000000000
2516 17:45:55.918854 MTRR: Fixed MSR 0x26a 0x0606060606060606
2517 17:45:55.922166 MTRR: Fixed MSR 0x250 0x0606060606060606
2518 17:45:55.925572 CPU physical address size: 39 bits
2519 17:45:55.928882 MTRR: Fixed MSR 0x259 0x0000000000000000
2520 17:45:55.935790 MTRR: Fixed MSR 0x26a 0x0606060606060606
2521 17:45:55.938656 MTRR: Fixed MSR 0x26b 0x0606060606060606
2522 17:45:55.942395 MTRR: Fixed MSR 0x258 0x0606060606060606
2523 17:45:55.945452 MTRR: Fixed MSR 0x259 0x0000000000000000
2524 17:45:55.951981 MTRR: Fixed MSR 0x268 0x0606060606060606
2525 17:45:55.955946 MTRR: Fixed MSR 0x269 0x0606060606060606
2526 17:45:55.959047 MTRR: Fixed MSR 0x26a 0x0606060606060606
2527 17:45:55.962496 MTRR: Fixed MSR 0x26b 0x0606060606060606
2528 17:45:55.969225 MTRR: Fixed MSR 0x26c 0x0606060606060606
2529 17:45:55.972319 MTRR: Fixed MSR 0x26d 0x0606060606060606
2530 17:45:55.975353 MTRR: Fixed MSR 0x26e 0x0606060606060606
2531 17:45:55.978654 MTRR: Fixed MSR 0x26f 0x0606060606060606
2532 17:45:55.985933 MTRR: Fixed MSR 0x268 0x0606060606060606
2533 17:45:55.986362 call enable_fixed_mtrr()
2534 17:45:55.992320 MTRR: Fixed MSR 0x26b 0x0606060606060606
2535 17:45:55.995656 MTRR: Fixed MSR 0x269 0x0606060606060606
2536 17:45:55.998874 MTRR: Fixed MSR 0x26c 0x0606060606060606
2537 17:45:56.002347 MTRR: Fixed MSR 0x26d 0x0606060606060606
2538 17:45:56.008753 MTRR: Fixed MSR 0x26e 0x0606060606060606
2539 17:45:56.012278 MTRR: Fixed MSR 0x26f 0x0606060606060606
2540 17:45:56.015379 CPU physical address size: 39 bits
2541 17:45:56.018561 call enable_fixed_mtrr()
2542 17:45:56.021892 MTRR: Fixed MSR 0x26a 0x0606060606060606
2543 17:45:56.025195 CPU physical address size: 39 bits
2544 17:45:56.028774 MTRR: Fixed MSR 0x26b 0x0606060606060606
2545 17:45:56.031959 MTRR: Fixed MSR 0x268 0x0606060606060606
2546 17:45:56.038108 MTRR: Fixed MSR 0x269 0x0606060606060606
2547 17:45:56.041769 MTRR: Fixed MSR 0x26a 0x0606060606060606
2548 17:45:56.045051 MTRR: Fixed MSR 0x26b 0x0606060606060606
2549 17:45:56.048594 MTRR: Fixed MSR 0x26c 0x0606060606060606
2550 17:45:56.055264 MTRR: Fixed MSR 0x26d 0x0606060606060606
2551 17:45:56.058292 MTRR: Fixed MSR 0x26e 0x0606060606060606
2552 17:45:56.061694 MTRR: Fixed MSR 0x26f 0x0606060606060606
2553 17:45:56.064608 MTRR: Fixed MSR 0x26c 0x0606060606060606
2554 17:45:56.068216 call enable_fixed_mtrr()
2555 17:45:56.071157 MTRR: Fixed MSR 0x26d 0x0606060606060606
2556 17:45:56.078386 MTRR: Fixed MSR 0x26e 0x0606060606060606
2557 17:45:56.081558 MTRR: Fixed MSR 0x26f 0x0606060606060606
2558 17:45:56.085187 MTRR: Fixed MSR 0x26c 0x0606060606060606
2559 17:45:56.088088 call enable_fixed_mtrr()
2560 17:45:56.091254 CPU physical address size: 39 bits
2561 17:45:56.094751 CPU physical address size: 39 bits
2562 17:45:56.098006 MTRR: Fixed MSR 0x26d 0x0606060606060606
2563 17:45:56.101291 MTRR: Fixed MSR 0x26e 0x0606060606060606
2564 17:45:56.107667 MTRR: Fixed MSR 0x26f 0x0606060606060606
2565 17:45:56.111089 call enable_fixed_mtrr()
2566 17:45:56.114751 CPU physical address size: 39 bits
2567 17:45:56.115285
2568 17:45:56.117938 MTRR check
2569 17:45:56.121410 Fixed MTRRs : Enabled
2570 17:45:56.121943 Variable MTRRs: Enabled
2571 17:45:56.122290
2572 17:45:56.127825 BS: BS_WRITE_TABLES exit times (exec / console): 253 / 150 ms
2573 17:45:56.131129 Checking cr50 for pending updates
2574 17:45:56.143080 Reading cr50 TPM mode
2575 17:45:56.158321 BS: BS_PAYLOAD_LOAD entry times (exec / console): 17 / 6 ms
2576 17:45:56.168356 CBFS: Found 'fallback/payload' @0x1bbe40 size 0x25902 in mcache @0x76add40c
2577 17:45:56.171670 Checking segment from ROM address 0xf96cbe6c
2578 17:45:56.175109 Checking segment from ROM address 0xf96cbe88
2579 17:45:56.181844 Loading segment from ROM address 0xf96cbe6c
2580 17:45:56.182377 code (compression=1)
2581 17:45:56.191737 New segment dstaddr 0x30000000 memsize 0x2668e60 srcaddr 0xf96cbea4 filesize 0x258ca
2582 17:45:56.198221 Loading Segment: addr: 0x30000000 memsz: 0x0000000002668e60 filesz: 0x00000000000258ca
2583 17:45:56.201581 using LZMA
2584 17:45:56.223427 [ 0x30000000, 30051214, 0x32668e60) <- f96cbea4
2585 17:45:56.229821 Clearing Segment: addr: 0x0000000030051214 memsz: 0x0000000002617c4c
2586 17:45:56.237853 Loading segment from ROM address 0xf96cbe88
2587 17:45:56.241213 Entry Point 0x30000000
2588 17:45:56.241672 Loaded segments
2589 17:45:56.247983 BS: BS_PAYLOAD_LOAD run times (exec / console): 20 / 62 ms
2590 17:45:56.254745 BS: BS_PAYLOAD_LOAD exit times (exec / console): 1 / 0 ms
2591 17:45:56.257753 Finalizing chipset.
2592 17:45:56.261121 apm_control: Finalizing SMM.
2593 17:45:56.261549 APMC done.
2594 17:45:56.264583 HECI: CSE device 16.1 is disabled
2595 17:45:56.268040 HECI: CSE device 16.2 is disabled
2596 17:45:56.270857 HECI: CSE device 16.3 is disabled
2597 17:45:56.274102 HECI: CSE device 16.4 is disabled
2598 17:45:56.277481 HECI: CSE device 16.5 is disabled
2599 17:45:56.280966 HECI: Sending End-of-Post
2600 17:45:56.289299 CSE: EOP requested action: continue boot
2601 17:45:56.293063 CSE EOP successful, continuing boot
2602 17:45:56.299211 BS: BS_PAYLOAD_BOOT entry times (exec / console): 4 / 34 ms
2603 17:45:56.302841 mp_park_aps done after 0 msecs.
2604 17:45:56.306140 Jumping to boot code at 0x30000000(0x76891000)
2605 17:45:56.316090 CPU0: stack: 0x76a99000 - 0x76a9a000, lowest used address 0x76a993dc, stack used: 3108 bytes
2606 17:45:56.320819
2607 17:45:56.321361
2608 17:45:56.321712
2609 17:45:56.323370 Starting depthcharge on Volmar...
2610 17:45:56.323796
2611 17:45:56.324974 end: 2.2.3 depthcharge-start (duration 00:00:14) [common]
2612 17:45:56.325476 start: 2.2.4 bootloader-commands (timeout 00:04:40) [common]
2613 17:45:56.325886 Setting prompt string to ['brya:']
2614 17:45:56.326284 bootloader-commands: Wait for prompt ['brya:'] (timeout 00:04:40)
2615 17:45:56.330686 WARNING: can't convert coreboot GPIOs, 'lid' won't be resampled at runtime!
2616 17:45:56.331224
2617 17:45:56.337128 WARNING: can't convert coreboot GPIOs, 'power' won't be resampled at runtime!
2618 17:45:56.337674
2619 17:45:56.343426 Looking for NVMe Controller 0x300653d8 @ 00:06:00
2620 17:45:56.343947
2621 17:45:56.346644 configure_storage: Failed to remap 1C:2
2622 17:45:56.347074
2623 17:45:56.350141 Wipe memory regions:
2624 17:45:56.350569
2625 17:45:56.353363 [0x00000000001000, 0x000000000a0000)
2626 17:45:56.353795
2627 17:45:56.356777 [0x00000000100000, 0x00000030000000)
2628 17:45:56.459114
2629 17:45:56.462344 [0x00000032668e60, 0x00000076857000)
2630 17:45:56.606357
2631 17:45:56.609706 [0x00000100000000, 0x0000027fc00000)
2632 17:45:57.419945
2633 17:45:57.423363 ec_init: CrosEC protocol v3 supported (256, 256)
2634 17:45:58.031389
2635 17:45:58.031916 R8152: Initializing
2636 17:45:58.032259
2637 17:45:58.034282 Version 9 (ocp_data = 6010)
2638 17:45:58.034753
2639 17:45:58.038267 R8152: Done initializing
2640 17:45:58.038839
2641 17:45:58.041564 Adding net device
2642 17:45:58.343281
2643 17:45:58.346553 [firmware-brya-14505.B-collabora] Feb 7 2023 16:06:26
2644 17:45:58.347116
2645 17:45:58.347458
2646 17:45:58.347774
2647 17:45:58.348519 Setting prompt string to ['brya:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2649 17:45:58.449744 brya: tftpboot 192.168.201.1 11712549/tftp-deploy-mtnn8qlx/kernel/bzImage 11712549/tftp-deploy-mtnn8qlx/kernel/cmdline 11712549/tftp-deploy-mtnn8qlx/ramdisk/ramdisk.cpio.gz
2650 17:45:58.450347 Setting prompt string to ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2651 17:45:58.450891 bootloader-commands: Wait for prompt ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:38)
2652 17:45:58.455702 tftpboot 192.168.201.1 11712549/tftp-deploy-mtnn8qlx/kernel/bzIploy-mtnn8qlx/kernel/cmdline 11712549/tftp-deploy-mtnn8qlx/ramdisk/ramdisk.cpio.gz
2653 17:45:58.456248
2654 17:45:58.456593 Waiting for link
2655 17:45:58.658650
2656 17:45:58.659183 done.
2657 17:45:58.659525
2658 17:45:58.659844 MAC: 00:e0:4c:68:01:74
2659 17:45:58.660155
2660 17:45:58.662097 Sending DHCP discover... done.
2661 17:45:58.662526
2662 17:45:58.665864 Waiting for reply... done.
2663 17:45:58.666415
2664 17:45:58.668652 Sending DHCP request... done.
2665 17:45:58.669080
2666 17:45:58.675813 Waiting for reply... done.
2667 17:45:58.676338
2668 17:45:58.676683 My ip is 192.168.201.16
2669 17:45:58.677003
2670 17:45:58.678669 The DHCP server ip is 192.168.201.1
2671 17:45:58.682416
2672 17:45:58.685857 TFTP server IP predefined by user: 192.168.201.1
2673 17:45:58.686406
2674 17:45:58.692182 Bootfile predefined by user: 11712549/tftp-deploy-mtnn8qlx/kernel/bzImage
2675 17:45:58.692736
2676 17:45:58.695605 Sending tftp read request... done.
2677 17:45:58.696141
2678 17:45:58.704019 Waiting for the transfer...
2679 17:45:58.704448
2680 17:45:58.975370 00000000 ################################################################
2681 17:45:58.975511
2682 17:45:59.269860 00080000 ################################################################
2683 17:45:59.269996
2684 17:45:59.581705 00100000 ################################################################
2685 17:45:59.581859
2686 17:45:59.858772 00180000 ################################################################
2687 17:45:59.858919
2688 17:46:00.113519 00200000 ################################################################
2689 17:46:00.113651
2690 17:46:00.379553 00280000 ################################################################
2691 17:46:00.379691
2692 17:46:00.632241 00300000 ################################################################
2693 17:46:00.632386
2694 17:46:00.883202 00380000 ################################################################
2695 17:46:00.883346
2696 17:46:01.148030 00400000 ################################################################
2697 17:46:01.148168
2698 17:46:01.402688 00480000 ################################################################
2699 17:46:01.402825
2700 17:46:01.650173 00500000 ################################################################
2701 17:46:01.650316
2702 17:46:01.933428 00580000 ################################################################
2703 17:46:01.933567
2704 17:46:02.205978 00600000 ################################################################
2705 17:46:02.206104
2706 17:46:02.454820 00680000 ################################################################
2707 17:46:02.454943
2708 17:46:02.710766 00700000 ################################################################
2709 17:46:02.710907
2710 17:46:02.958407 00780000 ################################################################
2711 17:46:02.958538
2712 17:46:03.013379 00800000 ############# done.
2713 17:46:03.013474
2714 17:46:03.016710 The bootfile was 8490896 bytes long.
2715 17:46:03.016796
2716 17:46:03.019955 Sending tftp read request... done.
2717 17:46:03.022881
2718 17:46:03.022978 Waiting for the transfer...
2719 17:46:03.023056
2720 17:46:03.312533 00000000 ################################################################
2721 17:46:03.312668
2722 17:46:03.596841 00080000 ################################################################
2723 17:46:03.596987
2724 17:46:03.881127 00100000 ################################################################
2725 17:46:03.881268
2726 17:46:04.161998 00180000 ################################################################
2727 17:46:04.162129
2728 17:46:04.443576 00200000 ################################################################
2729 17:46:04.443712
2730 17:46:04.729271 00280000 ################################################################
2731 17:46:04.729405
2732 17:46:05.007088 00300000 ################################################################
2733 17:46:05.007231
2734 17:46:05.290493 00380000 ################################################################
2735 17:46:05.290660
2736 17:46:05.585873 00400000 ################################################################
2737 17:46:05.586012
2738 17:46:05.856296 00480000 ################################################################
2739 17:46:05.856444
2740 17:46:06.141800 00500000 ################################################################
2741 17:46:06.141949
2742 17:46:06.425352 00580000 ################################################################
2743 17:46:06.425489
2744 17:46:06.718468 00600000 ################################################################
2745 17:46:06.718642
2746 17:46:07.004062 00680000 ################################################################
2747 17:46:07.004208
2748 17:46:07.296985 00700000 ################################################################
2749 17:46:07.297126
2750 17:46:07.583197 00780000 ################################################################
2751 17:46:07.583335
2752 17:46:07.820004 00800000 ####################################################### done.
2753 17:46:07.820135
2754 17:46:07.823535 Sending tftp read request... done.
2755 17:46:07.823705
2756 17:46:07.826724 Waiting for the transfer...
2757 17:46:07.826838
2758 17:46:07.830087 00000000 # done.
2759 17:46:07.830265
2760 17:46:07.836616 Command line loaded dynamically from TFTP file: 11712549/tftp-deploy-mtnn8qlx/kernel/cmdline
2761 17:46:07.836802
2762 17:46:07.852989 The command line is: console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
2763 17:46:07.858889
2764 17:46:07.861773 Shutting down all USB controllers.
2765 17:46:07.861974
2766 17:46:07.862115 Removing current net device
2767 17:46:07.862247
2768 17:46:07.865136 Finalizing coreboot
2769 17:46:07.865341
2770 17:46:07.872174 Exiting depthcharge with code 4 at timestamp: 21782663
2771 17:46:07.872517
2772 17:46:07.872739
2773 17:46:07.872960 Starting kernel ...
2774 17:46:07.873180
2775 17:46:07.873397
2776 17:46:07.874328 end: 2.2.4 bootloader-commands (duration 00:00:12) [common]
2777 17:46:07.874705 start: 2.2.5 auto-login-action (timeout 00:04:29) [common]
2778 17:46:07.874982 Setting prompt string to ['Linux version [0-9]']
2779 17:46:07.875234 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2780 17:46:07.875487 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
2782 17:50:36.875032 end: 2.2.5 auto-login-action (duration 00:04:29) [common]
2784 17:50:36.875256 depthcharge-retry failed: 1 of 1 attempts. 'auto-login-action timed out after 269 seconds'
2786 17:50:36.875425 end: 2.2 depthcharge-retry (duration 00:05:00) [common]
2789 17:50:36.875680 end: 2 depthcharge-action (duration 00:05:00) [common]
2791 17:50:36.875916 Cleaning after the job
2792 17:50:36.876011 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11712549/tftp-deploy-mtnn8qlx/ramdisk
2793 17:50:36.877551 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11712549/tftp-deploy-mtnn8qlx/kernel
2794 17:50:36.878933 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11712549/tftp-deploy-mtnn8qlx/modules
2795 17:50:36.879366 start: 5.1 power-off (timeout 00:00:30) [common]
2796 17:50:36.879531 Calling: 'pduclient' '--daemon=localhost' '--hostname=acer-cbv514-1h-34uz-brya-cbg-8' '--port=1' '--command=off'
2797 17:50:36.955746 >> Command sent successfully.
2798 17:50:36.958359 Returned 0 in 0 seconds
2799 17:50:37.058706 end: 5.1 power-off (duration 00:00:00) [common]
2801 17:50:37.059094 start: 5.2 read-feedback (timeout 00:10:00) [common]
2802 17:50:37.059376 Listened to connection for namespace 'common' for up to 1s
2804 17:50:37.059772 Listened to connection for namespace 'common' for up to 1s
2805 17:50:38.060321 Finalising connection for namespace 'common'
2806 17:50:38.060501 Disconnecting from shell: Finalise
2807 17:50:38.060581
2808 17:50:38.160917 end: 5.2 read-feedback (duration 00:00:01) [common]
2809 17:50:38.161063 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11712549
2810 17:50:38.178662 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11712549
2811 17:50:38.178821 JobError: Your job cannot terminate cleanly.