Boot log: asus-C436FA-Flip-hatch
- Warnings: 0
- Kernel Warnings: 0
- Kernel Errors: 0
- Errors: 2
- Boot result: FAIL
1 17:49:57.595916 lava-dispatcher, installed at version: 2023.08
2 17:49:57.596124 start: 0 validate
3 17:49:57.596253 Start time: 2023-10-09 17:49:57.596245+00:00 (UTC)
4 17:49:57.596374 Using caching service: 'http://localhost/cache/?uri=%s'
5 17:49:57.596510 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230623.0%2Fx86%2Frootfs.cpio.gz exists
6 17:49:57.855264 Using caching service: 'http://localhost/cache/?uri=%s'
7 17:49:57.855430 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-4.4.y-st%2Fv4.4-st20-1778-g3b01feff09495%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fkernel%2FbzImage exists
8 17:49:58.111873 Using caching service: 'http://localhost/cache/?uri=%s'
9 17:49:58.112050 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-4.4.y-st%2Fv4.4-st20-1778-g3b01feff09495%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
10 17:49:58.369749 validate duration: 0.77
12 17:49:58.370065 start: 1 tftp-deploy (timeout 00:10:00) [common]
13 17:49:58.370177 start: 1.1 download-retry (timeout 00:10:00) [common]
14 17:49:58.370271 start: 1.1.1 http-download (timeout 00:10:00) [common]
15 17:49:58.370400 Not decompressing ramdisk as can be used compressed.
16 17:49:58.370486 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230623.0/x86/rootfs.cpio.gz
17 17:49:58.370549 saving as /var/lib/lava/dispatcher/tmp/11712576/tftp-deploy-uhc0u1w3/ramdisk/rootfs.cpio.gz
18 17:49:58.370618 total size: 8418130 (8 MB)
19 17:49:58.371770 progress 0 % (0 MB)
20 17:49:58.374235 progress 5 % (0 MB)
21 17:49:58.376662 progress 10 % (0 MB)
22 17:49:58.379112 progress 15 % (1 MB)
23 17:49:58.381500 progress 20 % (1 MB)
24 17:49:58.383908 progress 25 % (2 MB)
25 17:49:58.386342 progress 30 % (2 MB)
26 17:49:58.388554 progress 35 % (2 MB)
27 17:49:58.390811 progress 40 % (3 MB)
28 17:49:58.393136 progress 45 % (3 MB)
29 17:49:58.395456 progress 50 % (4 MB)
30 17:49:58.397795 progress 55 % (4 MB)
31 17:49:58.400180 progress 60 % (4 MB)
32 17:49:58.402301 progress 65 % (5 MB)
33 17:49:58.404728 progress 70 % (5 MB)
34 17:49:58.407043 progress 75 % (6 MB)
35 17:49:58.409310 progress 80 % (6 MB)
36 17:49:58.411784 progress 85 % (6 MB)
37 17:49:58.414165 progress 90 % (7 MB)
38 17:49:58.416462 progress 95 % (7 MB)
39 17:49:58.418660 progress 100 % (8 MB)
40 17:49:58.418919 8 MB downloaded in 0.05 s (166.21 MB/s)
41 17:49:58.419077 end: 1.1.1 http-download (duration 00:00:00) [common]
43 17:49:58.419314 end: 1.1 download-retry (duration 00:00:00) [common]
44 17:49:58.419400 start: 1.2 download-retry (timeout 00:10:00) [common]
45 17:49:58.419486 start: 1.2.1 http-download (timeout 00:10:00) [common]
46 17:49:58.419648 downloading http://storage.kernelci.org/cip/linux-4.4.y-st/v4.4-st20-1778-g3b01feff09495/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/kernel/bzImage
47 17:49:58.419734 saving as /var/lib/lava/dispatcher/tmp/11712576/tftp-deploy-uhc0u1w3/kernel/bzImage
48 17:49:58.419794 total size: 8490896 (8 MB)
49 17:49:58.419853 No compression specified
50 17:49:58.420943 progress 0 % (0 MB)
51 17:49:58.423132 progress 5 % (0 MB)
52 17:49:58.425618 progress 10 % (0 MB)
53 17:49:58.427977 progress 15 % (1 MB)
54 17:49:58.430290 progress 20 % (1 MB)
55 17:49:58.432672 progress 25 % (2 MB)
56 17:49:58.435061 progress 30 % (2 MB)
57 17:49:58.437427 progress 35 % (2 MB)
58 17:49:58.439827 progress 40 % (3 MB)
59 17:49:58.442192 progress 45 % (3 MB)
60 17:49:58.444564 progress 50 % (4 MB)
61 17:49:58.446876 progress 55 % (4 MB)
62 17:49:58.449264 progress 60 % (4 MB)
63 17:49:58.451642 progress 65 % (5 MB)
64 17:49:58.454169 progress 70 % (5 MB)
65 17:49:58.456535 progress 75 % (6 MB)
66 17:49:58.458870 progress 80 % (6 MB)
67 17:49:58.461163 progress 85 % (6 MB)
68 17:49:58.463497 progress 90 % (7 MB)
69 17:49:58.465893 progress 95 % (7 MB)
70 17:49:58.468264 progress 100 % (8 MB)
71 17:49:58.468380 8 MB downloaded in 0.05 s (166.67 MB/s)
72 17:49:58.468525 end: 1.2.1 http-download (duration 00:00:00) [common]
74 17:49:58.468750 end: 1.2 download-retry (duration 00:00:00) [common]
75 17:49:58.468835 start: 1.3 download-retry (timeout 00:10:00) [common]
76 17:49:58.468917 start: 1.3.1 http-download (timeout 00:10:00) [common]
77 17:49:58.469060 downloading http://storage.kernelci.org/cip/linux-4.4.y-st/v4.4-st20-1778-g3b01feff09495/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/modules.tar.xz
78 17:49:58.469131 saving as /var/lib/lava/dispatcher/tmp/11712576/tftp-deploy-uhc0u1w3/modules/modules.tar
79 17:49:58.469190 total size: 250928 (0 MB)
80 17:49:58.469250 Using unxz to decompress xz
81 17:49:58.473303 progress 13 % (0 MB)
82 17:49:58.473726 progress 26 % (0 MB)
83 17:49:58.473969 progress 39 % (0 MB)
84 17:49:58.475599 progress 52 % (0 MB)
85 17:49:58.477469 progress 65 % (0 MB)
86 17:49:58.479328 progress 78 % (0 MB)
87 17:49:58.481229 progress 91 % (0 MB)
88 17:49:58.483006 progress 100 % (0 MB)
89 17:49:58.488781 0 MB downloaded in 0.02 s (12.22 MB/s)
90 17:49:58.489022 end: 1.3.1 http-download (duration 00:00:00) [common]
92 17:49:58.489290 end: 1.3 download-retry (duration 00:00:00) [common]
93 17:49:58.489386 start: 1.4 prepare-tftp-overlay (timeout 00:10:00) [common]
94 17:49:58.489484 start: 1.4.1 extract-nfsrootfs (timeout 00:10:00) [common]
95 17:49:58.489568 end: 1.4.1 extract-nfsrootfs (duration 00:00:00) [common]
96 17:49:58.489674 start: 1.4.2 lava-overlay (timeout 00:10:00) [common]
97 17:49:58.489903 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/11712576/lava-overlay-t_a5475f
98 17:49:58.490051 makedir: /var/lib/lava/dispatcher/tmp/11712576/lava-overlay-t_a5475f/lava-11712576/bin
99 17:49:58.490190 makedir: /var/lib/lava/dispatcher/tmp/11712576/lava-overlay-t_a5475f/lava-11712576/tests
100 17:49:58.490328 makedir: /var/lib/lava/dispatcher/tmp/11712576/lava-overlay-t_a5475f/lava-11712576/results
101 17:49:58.490472 Creating /var/lib/lava/dispatcher/tmp/11712576/lava-overlay-t_a5475f/lava-11712576/bin/lava-add-keys
102 17:49:58.490648 Creating /var/lib/lava/dispatcher/tmp/11712576/lava-overlay-t_a5475f/lava-11712576/bin/lava-add-sources
103 17:49:58.490810 Creating /var/lib/lava/dispatcher/tmp/11712576/lava-overlay-t_a5475f/lava-11712576/bin/lava-background-process-start
104 17:49:58.490970 Creating /var/lib/lava/dispatcher/tmp/11712576/lava-overlay-t_a5475f/lava-11712576/bin/lava-background-process-stop
105 17:49:58.491103 Creating /var/lib/lava/dispatcher/tmp/11712576/lava-overlay-t_a5475f/lava-11712576/bin/lava-common-functions
106 17:49:58.491235 Creating /var/lib/lava/dispatcher/tmp/11712576/lava-overlay-t_a5475f/lava-11712576/bin/lava-echo-ipv4
107 17:49:58.491391 Creating /var/lib/lava/dispatcher/tmp/11712576/lava-overlay-t_a5475f/lava-11712576/bin/lava-install-packages
108 17:49:58.491553 Creating /var/lib/lava/dispatcher/tmp/11712576/lava-overlay-t_a5475f/lava-11712576/bin/lava-installed-packages
109 17:49:58.491749 Creating /var/lib/lava/dispatcher/tmp/11712576/lava-overlay-t_a5475f/lava-11712576/bin/lava-os-build
110 17:49:58.491877 Creating /var/lib/lava/dispatcher/tmp/11712576/lava-overlay-t_a5475f/lava-11712576/bin/lava-probe-channel
111 17:49:58.492000 Creating /var/lib/lava/dispatcher/tmp/11712576/lava-overlay-t_a5475f/lava-11712576/bin/lava-probe-ip
112 17:49:58.492122 Creating /var/lib/lava/dispatcher/tmp/11712576/lava-overlay-t_a5475f/lava-11712576/bin/lava-target-ip
113 17:49:58.492246 Creating /var/lib/lava/dispatcher/tmp/11712576/lava-overlay-t_a5475f/lava-11712576/bin/lava-target-mac
114 17:49:58.492374 Creating /var/lib/lava/dispatcher/tmp/11712576/lava-overlay-t_a5475f/lava-11712576/bin/lava-target-storage
115 17:49:58.492502 Creating /var/lib/lava/dispatcher/tmp/11712576/lava-overlay-t_a5475f/lava-11712576/bin/lava-test-case
116 17:49:58.492662 Creating /var/lib/lava/dispatcher/tmp/11712576/lava-overlay-t_a5475f/lava-11712576/bin/lava-test-event
117 17:49:58.492785 Creating /var/lib/lava/dispatcher/tmp/11712576/lava-overlay-t_a5475f/lava-11712576/bin/lava-test-feedback
118 17:49:58.492909 Creating /var/lib/lava/dispatcher/tmp/11712576/lava-overlay-t_a5475f/lava-11712576/bin/lava-test-raise
119 17:49:58.493034 Creating /var/lib/lava/dispatcher/tmp/11712576/lava-overlay-t_a5475f/lava-11712576/bin/lava-test-reference
120 17:49:58.493164 Creating /var/lib/lava/dispatcher/tmp/11712576/lava-overlay-t_a5475f/lava-11712576/bin/lava-test-runner
121 17:49:58.493288 Creating /var/lib/lava/dispatcher/tmp/11712576/lava-overlay-t_a5475f/lava-11712576/bin/lava-test-set
122 17:49:58.493412 Creating /var/lib/lava/dispatcher/tmp/11712576/lava-overlay-t_a5475f/lava-11712576/bin/lava-test-shell
123 17:49:58.493542 Updating /var/lib/lava/dispatcher/tmp/11712576/lava-overlay-t_a5475f/lava-11712576/bin/lava-install-packages (oe)
124 17:49:58.493768 Updating /var/lib/lava/dispatcher/tmp/11712576/lava-overlay-t_a5475f/lava-11712576/bin/lava-installed-packages (oe)
125 17:49:58.493942 Creating /var/lib/lava/dispatcher/tmp/11712576/lava-overlay-t_a5475f/lava-11712576/environment
126 17:49:58.494072 LAVA metadata
127 17:49:58.494171 - LAVA_JOB_ID=11712576
128 17:49:58.494269 - LAVA_DISPATCHER_IP=192.168.201.1
129 17:49:58.494407 start: 1.4.2.1 lava-vland-overlay (timeout 00:10:00) [common]
130 17:49:58.494498 skipped lava-vland-overlay
131 17:49:58.494604 end: 1.4.2.1 lava-vland-overlay (duration 00:00:00) [common]
132 17:49:58.494711 start: 1.4.2.2 lava-multinode-overlay (timeout 00:10:00) [common]
133 17:49:58.494790 skipped lava-multinode-overlay
134 17:49:58.494867 end: 1.4.2.2 lava-multinode-overlay (duration 00:00:00) [common]
135 17:49:58.494946 start: 1.4.2.3 test-definition (timeout 00:10:00) [common]
136 17:49:58.495018 Loading test definitions
137 17:49:58.495112 start: 1.4.2.3.1 inline-repo-action (timeout 00:10:00) [common]
138 17:49:58.495189 Using /lava-11712576 at stage 0
139 17:49:58.495687 uuid=11712576_1.4.2.3.1 testdef=None
140 17:49:58.495806 end: 1.4.2.3.1 inline-repo-action (duration 00:00:00) [common]
141 17:49:58.495896 start: 1.4.2.3.2 test-overlay (timeout 00:10:00) [common]
142 17:49:58.496430 end: 1.4.2.3.2 test-overlay (duration 00:00:00) [common]
144 17:49:58.496645 start: 1.4.2.3.3 test-install-overlay (timeout 00:10:00) [common]
145 17:49:58.497315 end: 1.4.2.3.3 test-install-overlay (duration 00:00:00) [common]
147 17:49:58.497540 start: 1.4.2.3.4 test-runscript-overlay (timeout 00:10:00) [common]
148 17:49:58.498191 runner path: /var/lib/lava/dispatcher/tmp/11712576/lava-overlay-t_a5475f/lava-11712576/0/tests/0_dmesg test_uuid 11712576_1.4.2.3.1
149 17:49:58.498380 end: 1.4.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
151 17:49:58.498600 start: 1.4.2.3.5 inline-repo-action (timeout 00:10:00) [common]
152 17:49:58.498670 Using /lava-11712576 at stage 1
153 17:49:58.498965 uuid=11712576_1.4.2.3.5 testdef=None
154 17:49:58.499056 end: 1.4.2.3.5 inline-repo-action (duration 00:00:00) [common]
155 17:49:58.499154 start: 1.4.2.3.6 test-overlay (timeout 00:10:00) [common]
156 17:49:58.499711 end: 1.4.2.3.6 test-overlay (duration 00:00:00) [common]
158 17:49:58.499929 start: 1.4.2.3.7 test-install-overlay (timeout 00:10:00) [common]
159 17:49:58.500575 end: 1.4.2.3.7 test-install-overlay (duration 00:00:00) [common]
161 17:49:58.500799 start: 1.4.2.3.8 test-runscript-overlay (timeout 00:10:00) [common]
162 17:49:58.501422 runner path: /var/lib/lava/dispatcher/tmp/11712576/lava-overlay-t_a5475f/lava-11712576/1/tests/1_bootrr test_uuid 11712576_1.4.2.3.5
163 17:49:58.501581 end: 1.4.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
165 17:49:58.501788 Creating lava-test-runner.conf files
166 17:49:58.501849 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11712576/lava-overlay-t_a5475f/lava-11712576/0 for stage 0
167 17:49:58.501937 - 0_dmesg
168 17:49:58.502017 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/11712576/lava-overlay-t_a5475f/lava-11712576/1 for stage 1
169 17:49:58.502142 - 1_bootrr
170 17:49:58.502233 end: 1.4.2.3 test-definition (duration 00:00:00) [common]
171 17:49:58.502315 start: 1.4.2.4 compress-overlay (timeout 00:10:00) [common]
172 17:49:58.511972 end: 1.4.2.4 compress-overlay (duration 00:00:00) [common]
173 17:49:58.512098 start: 1.4.2.5 persistent-nfs-overlay (timeout 00:10:00) [common]
174 17:49:58.512187 end: 1.4.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
175 17:49:58.512271 end: 1.4.2 lava-overlay (duration 00:00:00) [common]
176 17:49:58.512353 start: 1.4.3 extract-overlay-ramdisk (timeout 00:10:00) [common]
177 17:49:58.768186 end: 1.4.3 extract-overlay-ramdisk (duration 00:00:00) [common]
178 17:49:58.768557 start: 1.4.4 extract-modules (timeout 00:10:00) [common]
179 17:49:58.768673 extracting modules file /var/lib/lava/dispatcher/tmp/11712576/tftp-deploy-uhc0u1w3/modules/modules.tar to /var/lib/lava/dispatcher/tmp/11712576/extract-overlay-ramdisk-1_mwq187/ramdisk
180 17:49:58.782972 end: 1.4.4 extract-modules (duration 00:00:00) [common]
181 17:49:58.783085 start: 1.4.5 apply-overlay-tftp (timeout 00:10:00) [common]
182 17:49:58.783173 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11712576/compress-overlay-3lph1b6j/overlay-1.4.2.4.tar.gz to ramdisk
183 17:49:58.783242 [common] Applying overlay /var/lib/lava/dispatcher/tmp/11712576/compress-overlay-3lph1b6j/overlay-1.4.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/11712576/extract-overlay-ramdisk-1_mwq187/ramdisk
184 17:49:58.794615 end: 1.4.5 apply-overlay-tftp (duration 00:00:00) [common]
185 17:49:58.794759 start: 1.4.6 configure-preseed-file (timeout 00:10:00) [common]
186 17:49:58.794880 end: 1.4.6 configure-preseed-file (duration 00:00:00) [common]
187 17:49:58.794981 start: 1.4.7 compress-ramdisk (timeout 00:10:00) [common]
188 17:49:58.795060 Building ramdisk /var/lib/lava/dispatcher/tmp/11712576/extract-overlay-ramdisk-1_mwq187/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/11712576/extract-overlay-ramdisk-1_mwq187/ramdisk
189 17:49:58.924103 >> 49788 blocks
190 17:49:59.759858 rename /var/lib/lava/dispatcher/tmp/11712576/extract-overlay-ramdisk-1_mwq187/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/11712576/tftp-deploy-uhc0u1w3/ramdisk/ramdisk.cpio.gz
191 17:49:59.760291 end: 1.4.7 compress-ramdisk (duration 00:00:01) [common]
192 17:49:59.760414 start: 1.4.8 prepare-kernel (timeout 00:09:59) [common]
193 17:49:59.760515 start: 1.4.8.1 prepare-fit (timeout 00:09:59) [common]
194 17:49:59.760613 No mkimage arch provided, not using FIT.
195 17:49:59.760699 end: 1.4.8.1 prepare-fit (duration 00:00:00) [common]
196 17:49:59.760780 end: 1.4.8 prepare-kernel (duration 00:00:00) [common]
197 17:49:59.760881 end: 1.4 prepare-tftp-overlay (duration 00:00:01) [common]
198 17:49:59.760966 start: 1.5 lxc-create-udev-rule-action (timeout 00:09:59) [common]
199 17:49:59.761046 No LXC device requested
200 17:49:59.761124 end: 1.5 lxc-create-udev-rule-action (duration 00:00:00) [common]
201 17:49:59.761207 start: 1.6 deploy-device-env (timeout 00:09:59) [common]
202 17:49:59.761289 end: 1.6 deploy-device-env (duration 00:00:00) [common]
203 17:49:59.761361 Checking files for TFTP limit of 4294967296 bytes.
204 17:49:59.761783 end: 1 tftp-deploy (duration 00:00:01) [common]
205 17:49:59.761893 start: 2 depthcharge-action (timeout 00:05:00) [common]
206 17:49:59.761981 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
207 17:49:59.762099 substitutions:
208 17:49:59.762163 - {DTB}: None
209 17:49:59.762226 - {INITRD}: 11712576/tftp-deploy-uhc0u1w3/ramdisk/ramdisk.cpio.gz
210 17:49:59.762283 - {KERNEL}: 11712576/tftp-deploy-uhc0u1w3/kernel/bzImage
211 17:49:59.762338 - {LAVA_MAC}: None
212 17:49:59.762391 - {PRESEED_CONFIG}: None
213 17:49:59.762444 - {PRESEED_LOCAL}: None
214 17:49:59.762495 - {RAMDISK}: 11712576/tftp-deploy-uhc0u1w3/ramdisk/ramdisk.cpio.gz
215 17:49:59.762548 - {ROOT_PART}: None
216 17:49:59.762600 - {ROOT}: None
217 17:49:59.762652 - {SERVER_IP}: 192.168.201.1
218 17:49:59.762703 - {TEE}: None
219 17:49:59.762756 Parsed boot commands:
220 17:49:59.762810 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
221 17:49:59.762976 Parsed boot commands: tftpboot 192.168.201.1 11712576/tftp-deploy-uhc0u1w3/kernel/bzImage 11712576/tftp-deploy-uhc0u1w3/kernel/cmdline 11712576/tftp-deploy-uhc0u1w3/ramdisk/ramdisk.cpio.gz
222 17:49:59.763060 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
223 17:49:59.763143 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
224 17:49:59.763229 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
225 17:49:59.763315 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
226 17:49:59.763388 Not connected, no need to disconnect.
227 17:49:59.763489 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
228 17:49:59.763601 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
229 17:49:59.763724 [common] connect-device Connecting to device using '/usr/local/bin/chromebook-console.sh asus-C436FA-Flip-hatch-cbg-3'
230 17:49:59.767414 Setting prompt string to ['lava-test: # ']
231 17:49:59.767864 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
232 17:49:59.768002 end: 2.2.1 reset-connection (duration 00:00:00) [common]
233 17:49:59.768127 start: 2.2.2 reset-device (timeout 00:05:00) [common]
234 17:49:59.768251 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
235 17:49:59.768460 Calling: 'pduclient' '--daemon=localhost' '--hostname=asus-C436FA-Flip-hatch-cbg-3' '--port=1' '--command=reboot'
236 17:50:04.906931 >> Command sent successfully.
237 17:50:04.909361 Returned 0 in 5 seconds
238 17:50:05.009738 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
240 17:50:05.010065 end: 2.2.2 reset-device (duration 00:00:05) [common]
241 17:50:05.010166 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
242 17:50:05.010254 Setting prompt string to 'Starting depthcharge on Helios...'
243 17:50:05.010321 Changing prompt to 'Starting depthcharge on Helios...'
244 17:50:05.010390 depthcharge-start: Wait for prompt Starting depthcharge on Helios... (timeout 00:05:00)
245 17:50:05.010681 [Enter `^Ec?' for help]
246 17:50:05.630699
247 17:50:05.630869
248 17:50:05.640107 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 bootblock starting (log level: 8)...
249 17:50:05.643513 CPU: Intel(R) Core(TM) i5-10210U CPU @ 1.60GHz
250 17:50:05.650389 CPU: ID 806ec, Whiskeylake V0, ucode: 000000c9
251 17:50:05.653614 CPU: AES supported, TXT NOT supported, VT supported
252 17:50:05.660171 MCH: device id 9b61 (rev 0c) is CometLake-U (4+2)
253 17:50:05.663573 PCH: device id 0284 (rev 00) is Cometlake-U Premium
254 17:50:05.670358 IGD: device id 9b41 (rev 02) is CometLake ULT GT2
255 17:50:05.673670 VBOOT: Loading verstage.
256 17:50:05.677199 FMAP: Found "FLASH" version 1.1 at 0xc04000.
257 17:50:05.683968 FMAP: base = 0xff000000 size = 0x1000000 #areas = 31
258 17:50:05.687253 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
259 17:50:05.690380 CBFS @ c08000 size 3f8000
260 17:50:05.697303 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
261 17:50:05.700729 CBFS: Locating 'fallback/verstage'
262 17:50:05.703422 CBFS: Found @ offset 10fb80 size 1072c
263 17:50:05.707318
264 17:50:05.707399
265 17:50:05.716972 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 verstage starting (log level: 8)...
266 17:50:05.731483 Probing TPM: . done!
267 17:50:05.734769 TPM ready after 0 ms
268 17:50:05.738282 Connected to device vid:did:rid of 1ae0:0028:00
269 17:50:05.748111 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.5.153/cr50_v2.94_mp.151-b967c9caf7
270 17:50:05.751571 Initialized TPM device CR50 revision 0
271 17:50:05.796330 tlcl_send_startup: Startup return code is 0
272 17:50:05.796422 TPM: setup succeeded
273 17:50:05.809056 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0
274 17:50:05.813010 Chrome EC: UHEPI supported
275 17:50:05.816104 Phase 1
276 17:50:05.819110 FMAP: area GBB found @ c05000 (12288 bytes)
277 17:50:05.826028 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0
278 17:50:05.829321 Phase 2
279 17:50:05.829407 Phase 3
280 17:50:05.832416 FMAP: area GBB found @ c05000 (12288 bytes)
281 17:50:05.839496 VB2:vb2_report_dev_firmware() This is developer signed firmware
282 17:50:05.845656 FMAP: area VBLOCK_B found @ 768000 (65536 bytes)
283 17:50:05.848963 FMAP: area VBLOCK_B found @ 768000 (65536 bytes)
284 17:50:05.855781 VB2:vb2_verify_keyblock() Checking keyblock signature...
285 17:50:05.871412 FMAP: area VBLOCK_B found @ 768000 (65536 bytes)
286 17:50:05.874838 FMAP: area VBLOCK_B found @ 768000 (65536 bytes)
287 17:50:05.881677 VB2:vb2_verify_fw_preamble() Verifying preamble.
288 17:50:05.885596 Phase 4
289 17:50:05.888789 FMAP: area FW_MAIN_B found @ 778000 (3506112 bytes)
290 17:50:05.895510 VB2:vb2api_init_hash() HW crypto for hash_alg 2 not supported, using SW
291 17:50:06.075196 VB2:vb2_rsa_verify_digest() Digest check failed!
292 17:50:06.081923 VB2:vb2api_fail() Need recovery, reason: 0x1b / 0x7
293 17:50:06.082008 Saving nvdata
294 17:50:06.085256 Reboot requested (10020007)
295 17:50:06.088594 board_reset() called!
296 17:50:06.088671 full_reset() called!
297 17:50:10.597813
298 17:50:10.597961
299 17:50:10.608171 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 bootblock starting (log level: 8)...
300 17:50:10.611477 CPU: Intel(R) Core(TM) i5-10210U CPU @ 1.60GHz
301 17:50:10.617801 CPU: ID 806ec, Whiskeylake V0, ucode: 000000c9
302 17:50:10.621092 CPU: AES supported, TXT NOT supported, VT supported
303 17:50:10.628078 MCH: device id 9b61 (rev 0c) is CometLake-U (4+2)
304 17:50:10.631496 PCH: device id 0284 (rev 00) is Cometlake-U Premium
305 17:50:10.637625 IGD: device id 9b41 (rev 02) is CometLake ULT GT2
306 17:50:10.640875 VBOOT: Loading verstage.
307 17:50:10.644245 FMAP: Found "FLASH" version 1.1 at 0xc04000.
308 17:50:10.651097 FMAP: base = 0xff000000 size = 0x1000000 #areas = 31
309 17:50:10.654598 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
310 17:50:10.657943 CBFS @ c08000 size 3f8000
311 17:50:10.664681 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
312 17:50:10.667456 CBFS: Locating 'fallback/verstage'
313 17:50:10.671073 CBFS: Found @ offset 10fb80 size 1072c
314 17:50:10.674520
315 17:50:10.674599
316 17:50:10.684498 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 verstage starting (log level: 8)...
317 17:50:10.699100 Probing TPM: . done!
318 17:50:10.702299 TPM ready after 0 ms
319 17:50:10.705475 Connected to device vid:did:rid of 1ae0:0028:00
320 17:50:10.715945 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.5.153/cr50_v2.94_mp.151-b967c9caf7
321 17:50:10.719375 Initialized TPM device CR50 revision 0
322 17:50:10.763570 tlcl_send_startup: Startup return code is 0
323 17:50:10.763720 TPM: setup succeeded
324 17:50:10.776363 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x1007 return code 0
325 17:50:10.780439 Chrome EC: UHEPI supported
326 17:50:10.783283 Phase 1
327 17:50:10.786706 FMAP: area GBB found @ c05000 (12288 bytes)
328 17:50:10.793569 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
329 17:50:10.800322 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x0
330 17:50:10.803861 Recovery requested (1009000e)
331 17:50:10.808946 Saving nvdata
332 17:50:10.815484 tlcl_extend: response is 0
333 17:50:10.824312 tlcl_extend: response is 0
334 17:50:10.831211 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
335 17:50:10.834629 CBFS @ c08000 size 3f8000
336 17:50:10.841460 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
337 17:50:10.844746 CBFS: Locating 'fallback/romstage'
338 17:50:10.847464 CBFS: Found @ offset 80 size 145fc
339 17:50:10.851355 Accumulated console time in verstage 98 ms
340 17:50:10.851461
341 17:50:10.851553
342 17:50:10.864083 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 romstage starting (log level: 8)...
343 17:50:10.870978 VB2:vb2api_ec_sync() In recovery mode, skipping EC sync
344 17:50:10.874183 pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00
345 17:50:10.877707 gpe0_sts[0]: 00000000 gpe0_en[0]: 00000000
346 17:50:10.884078 gpe0_sts[1]: 00200000 gpe0_en[1]: 00000000
347 17:50:10.887600 gpe0_sts[2]: 00000000 gpe0_en[2]: 00000000
348 17:50:10.890443 gpe0_sts[3]: 00000000 gpe0_en[3]: 00010000
349 17:50:10.893836 TCO_STS: 0000 0000
350 17:50:10.897055 GEN_PMCON: e0015238 00000200
351 17:50:10.900270 GBLRST_CAUSE: 00000000 00000000
352 17:50:10.900351 prev_sleep_state 5
353 17:50:10.904344 Boot Count incremented to 66018
354 17:50:10.910995 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
355 17:50:10.914452 CBFS @ c08000 size 3f8000
356 17:50:10.920623 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
357 17:50:10.920706 CBFS: Locating 'fspm.bin'
358 17:50:10.927542 CBFS: Found @ offset 5ffc0 size 71000
359 17:50:10.931014 Chrome EC: UHEPI supported
360 17:50:10.937156 FMAP: area RECOVERY_MRC_CACHE found @ ad0000 (65536 bytes)
361 17:50:10.940543 Probing TPM: done!
362 17:50:10.947460 Connected to device vid:did:rid of 1ae0:0028:00
363 17:50:10.957375 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.5.153/cr50_v2.94_mp.151-b967c9caf7
364 17:50:10.963134 Initialized TPM device CR50 revision 0
365 17:50:10.972369 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x100b return code 0
366 17:50:10.979086 MRC: Hash comparison successful. Using data from RECOVERY_MRC_CACHE
367 17:50:10.982507 MRC cache found, size 1948
368 17:50:10.985352 bootmode is set to: 2
369 17:50:10.988610 PRMRR disabled by config.
370 17:50:10.992115 SPD INDEX = 1
371 17:50:10.995761 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
372 17:50:10.999002 CBFS @ c08000 size 3f8000
373 17:50:11.005697 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
374 17:50:11.005780 CBFS: Locating 'spd.bin'
375 17:50:11.009203 CBFS: Found @ offset 5fb80 size 400
376 17:50:11.012526 SPD: module type is LPDDR3
377 17:50:11.015243 SPD: module part is
378 17:50:11.021824 SPD: banks 16, ranks 2, rows 15, columns 11, density 8192 Mb
379 17:50:11.025303 SPD: device width 4 bits, bus width 8 bits
380 17:50:11.028577 SPD: module size is 4096 MB (per channel)
381 17:50:11.032110 memory slot: 0 configuration done.
382 17:50:11.035976 memory slot: 2 configuration done.
383 17:50:11.086787 CBMEM:
384 17:50:11.090312 IMD: root @ 99fff000 254 entries.
385 17:50:11.093322 IMD: root @ 99ffec00 62 entries.
386 17:50:11.096846 External stage cache:
387 17:50:11.100105 IMD: root @ 9abff000 254 entries.
388 17:50:11.103512 IMD: root @ 9abfec00 62 entries.
389 17:50:11.106928 Chrome EC: clear events_b mask to 0x0000000020004000
390 17:50:11.122614 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x100b return code 0
391 17:50:11.136021 tlcl_write: response is 0
392 17:50:11.145229 src/security/tpm/tss/tcg-2.0/tss.c:223 index 0x100b return code 0
393 17:50:11.151708 MRC: TPM MRC hash updated successfully.
394 17:50:11.152297 2 DIMMs found
395 17:50:11.155280 SMM Memory Map
396 17:50:11.158086 SMRAM : 0x9a000000 0x1000000
397 17:50:11.161402 Subregion 0: 0x9a000000 0xa00000
398 17:50:11.164779 Subregion 1: 0x9aa00000 0x200000
399 17:50:11.168320 Subregion 2: 0x9ac00000 0x400000
400 17:50:11.171763 top_of_ram = 0x9a000000
401 17:50:11.175061 MTRR Range: Start=99000000 End=9a000000 (Size 1000000)
402 17:50:11.181272 MTRR Range: Start=9a000000 End=9b000000 (Size 1000000)
403 17:50:11.184971 MTRR Range: Start=ff000000 End=0 (Size 1000000)
404 17:50:11.191178 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
405 17:50:11.194545 CBFS @ c08000 size 3f8000
406 17:50:11.198322 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
407 17:50:11.201514 CBFS: Locating 'fallback/postcar'
408 17:50:11.208239 CBFS: Found @ offset 107000 size 4b44
409 17:50:11.211183 Decompressing stage fallback/postcar @ 0x99c0bfc0 (35640 bytes)
410 17:50:11.224441 Loading module at 99c0c000 with entry 99c0c000. filesize: 0x4818 memsize: 0x8af8
411 17:50:11.227767 Processing 180 relocs. Offset value of 0x97c0c000
412 17:50:11.236122 Accumulated console time in romstage 286 ms
413 17:50:11.236732
414 17:50:11.237199
415 17:50:11.246186 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 postcar starting (log level: 8)...
416 17:50:11.252577 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
417 17:50:11.256055 CBFS @ c08000 size 3f8000
418 17:50:11.258726 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
419 17:50:11.265633 CBFS: Locating 'fallback/ramstage'
420 17:50:11.269026 CBFS: Found @ offset 43380 size 1b9e8
421 17:50:11.275719 Decompressing stage fallback/ramstage @ 0x99baffc0 (372088 bytes)
422 17:50:11.307475 Loading module at 99bb0000 with entry 99bb0000. filesize: 0x40940 memsize: 0x5ad38
423 17:50:11.310787 Processing 3976 relocs. Offset value of 0x98db0000
424 17:50:11.317406 Accumulated console time in postcar 52 ms
425 17:50:11.318111
426 17:50:11.318696
427 17:50:11.327729 coreboot-v1.9308_26_0.0.22-11197-gc9b4b7136b Thu Mar 18 05:35:38 UTC 2021 ramstage starting (log level: 8)...
428 17:50:11.334307 FMAP: area RO_VPD found @ c00000 (16384 bytes)
429 17:50:11.337345 WARNING: RO_VPD is uninitialized or empty.
430 17:50:11.340816 FMAP: area RW_VPD found @ af8000 (8192 bytes)
431 17:50:11.347325 FMAP: area RW_VPD found @ af8000 (8192 bytes)
432 17:50:11.347787 Normal boot.
433 17:50:11.354464 BS: BS_PRE_DEVICE times (ms): entry 0 run 0 exit 0
434 17:50:11.357390 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
435 17:50:11.360683 CBFS @ c08000 size 3f8000
436 17:50:11.367602 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
437 17:50:11.370878 CBFS: Locating 'cpu_microcode_blob.bin'
438 17:50:11.374226 CBFS: Found @ offset 14700 size 2ec00
439 17:50:11.377092 microcode: sig=0x806ec pf=0x4 revision=0xc9
440 17:50:11.380511 Skip microcode update
441 17:50:11.387293 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
442 17:50:11.388005 CBFS @ c08000 size 3f8000
443 17:50:11.394192 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
444 17:50:11.396858 CBFS: Locating 'fsps.bin'
445 17:50:11.400210 CBFS: Found @ offset d1fc0 size 35000
446 17:50:11.425593 Detected 4 core, 8 thread CPU.
447 17:50:11.428803 Setting up SMI for CPU
448 17:50:11.432233 IED base = 0x9ac00000
449 17:50:11.432667 IED size = 0x00400000
450 17:50:11.435403 Will perform SMM setup.
451 17:50:11.442437 CPU: Intel(R) Core(TM) i5-10210U CPU @ 1.60GHz.
452 17:50:11.449365 Loading module at 00030000 with entry 00030000. filesize: 0x170 memsize: 0x170
453 17:50:11.452506 Processing 16 relocs. Offset value of 0x00030000
454 17:50:11.456310 Attempting to start 7 APs
455 17:50:11.459172 Waiting for 10ms after sending INIT.
456 17:50:11.475858 Waiting for 1st SIPI to complete...AP: slot 3 apic_id 1.
457 17:50:11.476290 done.
458 17:50:11.479265 AP: slot 1 apic_id 3.
459 17:50:11.481974 AP: slot 4 apic_id 2.
460 17:50:11.485417 Waiting for 2nd SIPI to complete...done.
461 17:50:11.488896 AP: slot 5 apic_id 7.
462 17:50:11.489327 AP: slot 2 apic_id 6.
463 17:50:11.492258 AP: slot 7 apic_id 5.
464 17:50:11.495538 AP: slot 6 apic_id 4.
465 17:50:11.501826 Loading module at 00038000 with entry 00038000. filesize: 0x1a8 memsize: 0x1a8
466 17:50:11.508705 Processing 13 relocs. Offset value of 0x00038000
467 17:50:11.511842 SMM Module: stub loaded at 00038000. Will call 99bcb71d(00000000)
468 17:50:11.518473 Installing SMM handler to 0x9a000000
469 17:50:11.525186 Loading module at 9a010000 with entry 9a010a52. filesize: 0x7e88 memsize: 0xcf58
470 17:50:11.532002 Processing 658 relocs. Offset value of 0x9a010000
471 17:50:11.538936 Loading module at 9a008000 with entry 9a008000. filesize: 0x1a8 memsize: 0x1a8
472 17:50:11.542001 Processing 13 relocs. Offset value of 0x9a008000
473 17:50:11.548900 SMM Module: placing jmp sequence at 9a007c00 rel16 0x03fd
474 17:50:11.555051 SMM Module: placing jmp sequence at 9a007800 rel16 0x07fd
475 17:50:11.561664 SMM Module: placing jmp sequence at 9a007400 rel16 0x0bfd
476 17:50:11.564969 SMM Module: placing jmp sequence at 9a007000 rel16 0x0ffd
477 17:50:11.571574 SMM Module: placing jmp sequence at 9a006c00 rel16 0x13fd
478 17:50:11.577954 SMM Module: placing jmp sequence at 9a006800 rel16 0x17fd
479 17:50:11.581454 SMM Module: placing jmp sequence at 9a006400 rel16 0x1bfd
480 17:50:11.588520 SMM Module: stub loaded at 9a008000. Will call 9a010a52(00000000)
481 17:50:11.591741 Clearing SMI status registers
482 17:50:11.595256 SMI_STS: PM1
483 17:50:11.595877 PM1_STS: PWRBTN
484 17:50:11.598417 TCO_STS: SECOND_TO
485 17:50:11.601899 New SMBASE 0x9a000000
486 17:50:11.605458 In relocation handler: CPU 0
487 17:50:11.608203 New SMBASE=0x9a000000 IEDBASE=0x9ac00000
488 17:50:11.611375 Writing SMRR. base = 0x9a000006, mask=0xff000800
489 17:50:11.614782 Relocation complete.
490 17:50:11.618092 New SMBASE 0x99fff400
491 17:50:11.618515 In relocation handler: CPU 3
492 17:50:11.625373 New SMBASE=0x99fff400 IEDBASE=0x9ac00000
493 17:50:11.628838 Writing SMRR. base = 0x9a000006, mask=0xff000800
494 17:50:11.632004 Relocation complete.
495 17:50:11.635247 New SMBASE 0x99ffec00
496 17:50:11.635819 In relocation handler: CPU 5
497 17:50:11.641754 New SMBASE=0x99ffec00 IEDBASE=0x9ac00000
498 17:50:11.645449 Writing SMRR. base = 0x9a000006, mask=0xff000800
499 17:50:11.648605 Relocation complete.
500 17:50:11.649042 New SMBASE 0x99ffe800
501 17:50:11.651402 In relocation handler: CPU 6
502 17:50:11.658332 New SMBASE=0x99ffe800 IEDBASE=0x9ac00000
503 17:50:11.661500 Writing SMRR. base = 0x9a000006, mask=0xff000800
504 17:50:11.664637 Relocation complete.
505 17:50:11.665058 New SMBASE 0x99ffe400
506 17:50:11.668035 In relocation handler: CPU 7
507 17:50:11.675131 New SMBASE=0x99ffe400 IEDBASE=0x9ac00000
508 17:50:11.677902 Writing SMRR. base = 0x9a000006, mask=0xff000800
509 17:50:11.681313 Relocation complete.
510 17:50:11.681747 New SMBASE 0x99fff800
511 17:50:11.684602 In relocation handler: CPU 2
512 17:50:11.687912 New SMBASE=0x99fff800 IEDBASE=0x9ac00000
513 17:50:11.694481 Writing SMRR. base = 0x9a000006, mask=0xff000800
514 17:50:11.698028 Relocation complete.
515 17:50:11.698610 New SMBASE 0x99fff000
516 17:50:11.701175 In relocation handler: CPU 4
517 17:50:11.704609 New SMBASE=0x99fff000 IEDBASE=0x9ac00000
518 17:50:11.711550 Writing SMRR. base = 0x9a000006, mask=0xff000800
519 17:50:11.712076 Relocation complete.
520 17:50:11.714434 New SMBASE 0x99fffc00
521 17:50:11.718347 In relocation handler: CPU 1
522 17:50:11.721586 New SMBASE=0x99fffc00 IEDBASE=0x9ac00000
523 17:50:11.727899 Writing SMRR. base = 0x9a000006, mask=0xff000800
524 17:50:11.727982 Relocation complete.
525 17:50:11.731277 Initializing CPU #0
526 17:50:11.734718 CPU: vendor Intel device 806ec
527 17:50:11.737538 CPU: family 06, model 8e, stepping 0c
528 17:50:11.741007 Clearing out pending MCEs
529 17:50:11.744283 Setting up local APIC...
530 17:50:11.744365 apic_id: 0x00 done.
531 17:50:11.747599 Turbo is available but hidden
532 17:50:11.750927 Turbo is available and visible
533 17:50:11.754082 VMX status: enabled
534 17:50:11.757830 IA32_FEATURE_CONTROL status: locked
535 17:50:11.761479 Skip microcode update
536 17:50:11.761560 CPU #0 initialized
537 17:50:11.764239 Initializing CPU #3
538 17:50:11.764320 Initializing CPU #4
539 17:50:11.767357 Initializing CPU #1
540 17:50:11.771329 CPU: vendor Intel device 806ec
541 17:50:11.774580 CPU: family 06, model 8e, stepping 0c
542 17:50:11.777883 CPU: vendor Intel device 806ec
543 17:50:11.781088 CPU: family 06, model 8e, stepping 0c
544 17:50:11.784283 Clearing out pending MCEs
545 17:50:11.787587 Clearing out pending MCEs
546 17:50:11.790967 Setting up local APIC...
547 17:50:11.794520 CPU: vendor Intel device 806ec
548 17:50:11.798049 CPU: family 06, model 8e, stepping 0c
549 17:50:11.798472 Clearing out pending MCEs
550 17:50:11.801252 apic_id: 0x03 done.
551 17:50:11.804516 Setting up local APIC...
552 17:50:11.804935 Initializing CPU #5
553 17:50:11.807756 Initializing CPU #2
554 17:50:11.811065 CPU: vendor Intel device 806ec
555 17:50:11.814341 CPU: family 06, model 8e, stepping 0c
556 17:50:11.817906 Setting up local APIC...
557 17:50:11.820802 Initializing CPU #7
558 17:50:11.821290 Initializing CPU #6
559 17:50:11.823972 CPU: vendor Intel device 806ec
560 17:50:11.827254 CPU: family 06, model 8e, stepping 0c
561 17:50:11.830688 CPU: vendor Intel device 806ec
562 17:50:11.834194 CPU: family 06, model 8e, stepping 0c
563 17:50:11.837014 Clearing out pending MCEs
564 17:50:11.840440 Clearing out pending MCEs
565 17:50:11.843750 Setting up local APIC...
566 17:50:11.843873 VMX status: enabled
567 17:50:11.847237 apic_id: 0x02 done.
568 17:50:11.850669 IA32_FEATURE_CONTROL status: locked
569 17:50:11.854266 VMX status: enabled
570 17:50:11.854427 Skip microcode update
571 17:50:11.856911 IA32_FEATURE_CONTROL status: locked
572 17:50:11.860364 CPU #1 initialized
573 17:50:11.863674 Skip microcode update
574 17:50:11.867429 CPU: vendor Intel device 806ec
575 17:50:11.870312 CPU: family 06, model 8e, stepping 0c
576 17:50:11.874090 Clearing out pending MCEs
577 17:50:11.874330 Clearing out pending MCEs
578 17:50:11.876754 Setting up local APIC...
579 17:50:11.880147 CPU #4 initialized
580 17:50:11.880359 apic_id: 0x05 done.
581 17:50:11.883490 Setting up local APIC...
582 17:50:11.886960 apic_id: 0x06 done.
583 17:50:11.890428 Setting up local APIC...
584 17:50:11.890786 VMX status: enabled
585 17:50:11.893717 apic_id: 0x04 done.
586 17:50:11.897059 IA32_FEATURE_CONTROL status: locked
587 17:50:11.900561 VMX status: enabled
588 17:50:11.901110 Skip microcode update
589 17:50:11.903974 IA32_FEATURE_CONTROL status: locked
590 17:50:11.906673 CPU #7 initialized
591 17:50:11.910231 Skip microcode update
592 17:50:11.910857 apic_id: 0x07 done.
593 17:50:11.913715 VMX status: enabled
594 17:50:11.917091 apic_id: 0x01 done.
595 17:50:11.920695 IA32_FEATURE_CONTROL status: locked
596 17:50:11.921264 VMX status: enabled
597 17:50:11.923765 CPU #6 initialized
598 17:50:11.927002 IA32_FEATURE_CONTROL status: locked
599 17:50:11.930064 Skip microcode update
600 17:50:11.930428 Skip microcode update
601 17:50:11.933183 CPU #2 initialized
602 17:50:11.933480 VMX status: enabled
603 17:50:11.936311 CPU #3 initialized
604 17:50:11.939758 IA32_FEATURE_CONTROL status: locked
605 17:50:11.943212 Skip microcode update
606 17:50:11.943454 CPU #5 initialized
607 17:50:11.949871 bsp_do_flight_plan done after 461 msecs.
608 17:50:11.953072 CPU: frequency set to 4200 MHz
609 17:50:11.953207 Enabling SMIs.
610 17:50:11.956380 Locking SMM.
611 17:50:11.969339 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
612 17:50:11.973273 CBFS @ c08000 size 3f8000
613 17:50:11.979742 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
614 17:50:11.979827 CBFS: Locating 'vbt.bin'
615 17:50:11.983028 CBFS: Found @ offset 5f5c0 size 499
616 17:50:11.989844 Found a VBT of 4608 bytes after decompression
617 17:50:12.174496 Display FSP Version Info HOB
618 17:50:12.177987 Reference Code - CPU = 9.0.1e.30
619 17:50:12.181102 uCode Version = 0.0.0.ca
620 17:50:12.184522 TXT ACM version = ff.ff.ff.ffff
621 17:50:12.187825 Display FSP Version Info HOB
622 17:50:12.190721 Reference Code - ME = 9.0.1e.30
623 17:50:12.194357 MEBx version = 0.0.0.0
624 17:50:12.197558 ME Firmware Version = Consumer SKU
625 17:50:12.201256 Display FSP Version Info HOB
626 17:50:12.204487 Reference Code - CML PCH = 9.0.1e.30
627 17:50:12.207797 PCH-CRID Status = Disabled
628 17:50:12.210723 PCH-CRID Original Value = ff.ff.ff.ffff
629 17:50:12.214760 PCH-CRID New Value = ff.ff.ff.ffff
630 17:50:12.218060 OPROM - RST - RAID = ff.ff.ff.ffff
631 17:50:12.221195 ChipsetInit Base Version = ff.ff.ff.ffff
632 17:50:12.224661 ChipsetInit Oem Version = ff.ff.ff.ffff
633 17:50:12.227484 Display FSP Version Info HOB
634 17:50:12.234212 Reference Code - SA - System Agent = 9.0.1e.30
635 17:50:12.237614 Reference Code - MRC = 0.7.1.6c
636 17:50:12.238033 SA - PCIe Version = 9.0.1e.30
637 17:50:12.241109 SA-CRID Status = Disabled
638 17:50:12.244393 SA-CRID Original Value = 0.0.0.c
639 17:50:12.247631 SA-CRID New Value = 0.0.0.c
640 17:50:12.250971 OPROM - VBIOS = ff.ff.ff.ffff
641 17:50:12.254424 RTC Init
642 17:50:12.257732 Set power on after power failure.
643 17:50:12.258152 Disabling Deep S3
644 17:50:12.260611 Disabling Deep S3
645 17:50:12.261030 Disabling Deep S4
646 17:50:12.264007 Disabling Deep S4
647 17:50:12.264424 Disabling Deep S5
648 17:50:12.267480 Disabling Deep S5
649 17:50:12.274367 BS: BS_DEV_INIT_CHIPS times (ms): entry 37 run 195 exit 1
650 17:50:12.274790 Enumerating buses...
651 17:50:12.280453 Show all devs... Before device enumeration.
652 17:50:12.280873 Root Device: enabled 1
653 17:50:12.283819 CPU_CLUSTER: 0: enabled 1
654 17:50:12.287289 DOMAIN: 0000: enabled 1
655 17:50:12.290676 APIC: 00: enabled 1
656 17:50:12.291097 PCI: 00:00.0: enabled 1
657 17:50:12.294156 PCI: 00:02.0: enabled 1
658 17:50:12.297657 PCI: 00:04.0: enabled 0
659 17:50:12.300692 PCI: 00:05.0: enabled 0
660 17:50:12.301116 PCI: 00:12.0: enabled 1
661 17:50:12.303673 PCI: 00:12.5: enabled 0
662 17:50:12.307007 PCI: 00:12.6: enabled 0
663 17:50:12.310391 PCI: 00:14.0: enabled 1
664 17:50:12.310809 PCI: 00:14.1: enabled 0
665 17:50:12.313559 PCI: 00:14.3: enabled 1
666 17:50:12.317048 PCI: 00:14.5: enabled 0
667 17:50:12.317497 PCI: 00:15.0: enabled 1
668 17:50:12.320458 PCI: 00:15.1: enabled 1
669 17:50:12.323329 PCI: 00:15.2: enabled 0
670 17:50:12.327003 PCI: 00:15.3: enabled 0
671 17:50:12.327427 PCI: 00:16.0: enabled 1
672 17:50:12.330043 PCI: 00:16.1: enabled 0
673 17:50:12.333392 PCI: 00:16.2: enabled 0
674 17:50:12.336741 PCI: 00:16.3: enabled 0
675 17:50:12.337163 PCI: 00:16.4: enabled 0
676 17:50:12.339914 PCI: 00:16.5: enabled 0
677 17:50:12.343479 PCI: 00:17.0: enabled 1
678 17:50:12.346814 PCI: 00:19.0: enabled 1
679 17:50:12.347256 PCI: 00:19.1: enabled 0
680 17:50:12.350254 PCI: 00:19.2: enabled 0
681 17:50:12.353199 PCI: 00:1a.0: enabled 0
682 17:50:12.353687 PCI: 00:1c.0: enabled 0
683 17:50:12.356551 PCI: 00:1c.1: enabled 0
684 17:50:12.359756 PCI: 00:1c.2: enabled 0
685 17:50:12.363207 PCI: 00:1c.3: enabled 0
686 17:50:12.363782 PCI: 00:1c.4: enabled 0
687 17:50:12.366592 PCI: 00:1c.5: enabled 0
688 17:50:12.370303 PCI: 00:1c.6: enabled 0
689 17:50:12.372994 PCI: 00:1c.7: enabled 0
690 17:50:12.373450 PCI: 00:1d.0: enabled 1
691 17:50:12.376512 PCI: 00:1d.1: enabled 0
692 17:50:12.379824 PCI: 00:1d.2: enabled 0
693 17:50:12.383302 PCI: 00:1d.3: enabled 0
694 17:50:12.383863 PCI: 00:1d.4: enabled 0
695 17:50:12.386609 PCI: 00:1d.5: enabled 1
696 17:50:12.389954 PCI: 00:1e.0: enabled 1
697 17:50:12.390537 PCI: 00:1e.1: enabled 0
698 17:50:12.393298 PCI: 00:1e.2: enabled 1
699 17:50:12.396800 PCI: 00:1e.3: enabled 1
700 17:50:12.400181 PCI: 00:1f.0: enabled 1
701 17:50:12.400600 PCI: 00:1f.1: enabled 1
702 17:50:12.403497 PCI: 00:1f.2: enabled 1
703 17:50:12.406998 PCI: 00:1f.3: enabled 1
704 17:50:12.409497 PCI: 00:1f.4: enabled 1
705 17:50:12.409918 PCI: 00:1f.5: enabled 1
706 17:50:12.413075 PCI: 00:1f.6: enabled 0
707 17:50:12.416347 USB0 port 0: enabled 1
708 17:50:12.416765 I2C: 00:15: enabled 1
709 17:50:12.419664 I2C: 00:5d: enabled 1
710 17:50:12.422938 GENERIC: 0.0: enabled 1
711 17:50:12.426609 I2C: 00:1a: enabled 1
712 17:50:12.427030 I2C: 00:38: enabled 1
713 17:50:12.429800 I2C: 00:39: enabled 1
714 17:50:12.432876 I2C: 00:3a: enabled 1
715 17:50:12.433296 I2C: 00:3b: enabled 1
716 17:50:12.436369 PCI: 00:00.0: enabled 1
717 17:50:12.439771 SPI: 00: enabled 1
718 17:50:12.440204 SPI: 01: enabled 1
719 17:50:12.443164 PNP: 0c09.0: enabled 1
720 17:50:12.446385 USB2 port 0: enabled 1
721 17:50:12.446815 USB2 port 1: enabled 1
722 17:50:12.449855 USB2 port 2: enabled 0
723 17:50:12.452828 USB2 port 3: enabled 0
724 17:50:12.453249 USB2 port 5: enabled 0
725 17:50:12.456471 USB2 port 6: enabled 1
726 17:50:12.459286 USB2 port 9: enabled 1
727 17:50:12.459746 USB3 port 0: enabled 1
728 17:50:12.462937 USB3 port 1: enabled 1
729 17:50:12.466080 USB3 port 2: enabled 1
730 17:50:12.469773 USB3 port 3: enabled 1
731 17:50:12.470198 USB3 port 4: enabled 0
732 17:50:12.472987 APIC: 03: enabled 1
733 17:50:12.476547 APIC: 06: enabled 1
734 17:50:12.476971 APIC: 01: enabled 1
735 17:50:12.479130 APIC: 02: enabled 1
736 17:50:12.479682 APIC: 07: enabled 1
737 17:50:12.482520 APIC: 04: enabled 1
738 17:50:12.486039 APIC: 05: enabled 1
739 17:50:12.486464 Compare with tree...
740 17:50:12.489462 Root Device: enabled 1
741 17:50:12.492782 CPU_CLUSTER: 0: enabled 1
742 17:50:12.493206 APIC: 00: enabled 1
743 17:50:12.495607 APIC: 03: enabled 1
744 17:50:12.499035 APIC: 06: enabled 1
745 17:50:12.502603 APIC: 01: enabled 1
746 17:50:12.503038 APIC: 02: enabled 1
747 17:50:12.506152 APIC: 07: enabled 1
748 17:50:12.508857 APIC: 04: enabled 1
749 17:50:12.509279 APIC: 05: enabled 1
750 17:50:12.512344 DOMAIN: 0000: enabled 1
751 17:50:12.515742 PCI: 00:00.0: enabled 1
752 17:50:12.519569 PCI: 00:02.0: enabled 1
753 17:50:12.520153 PCI: 00:04.0: enabled 0
754 17:50:12.522798 PCI: 00:05.0: enabled 0
755 17:50:12.526252 PCI: 00:12.0: enabled 1
756 17:50:12.529017 PCI: 00:12.5: enabled 0
757 17:50:12.532596 PCI: 00:12.6: enabled 0
758 17:50:12.533188 PCI: 00:14.0: enabled 1
759 17:50:12.535800 USB0 port 0: enabled 1
760 17:50:12.539103 USB2 port 0: enabled 1
761 17:50:12.542455 USB2 port 1: enabled 1
762 17:50:12.545705 USB2 port 2: enabled 0
763 17:50:12.546131 USB2 port 3: enabled 0
764 17:50:12.549220 USB2 port 5: enabled 0
765 17:50:12.552000 USB2 port 6: enabled 1
766 17:50:12.555422 USB2 port 9: enabled 1
767 17:50:12.558670 USB3 port 0: enabled 1
768 17:50:12.561913 USB3 port 1: enabled 1
769 17:50:12.562366 USB3 port 2: enabled 1
770 17:50:12.565546 USB3 port 3: enabled 1
771 17:50:12.568581 USB3 port 4: enabled 0
772 17:50:12.572093 PCI: 00:14.1: enabled 0
773 17:50:12.575596 PCI: 00:14.3: enabled 1
774 17:50:12.576098 PCI: 00:14.5: enabled 0
775 17:50:12.578682 PCI: 00:15.0: enabled 1
776 17:50:12.582008 I2C: 00:15: enabled 1
777 17:50:12.585685 PCI: 00:15.1: enabled 1
778 17:50:12.586109 I2C: 00:5d: enabled 1
779 17:50:12.588941 GENERIC: 0.0: enabled 1
780 17:50:12.592198 PCI: 00:15.2: enabled 0
781 17:50:12.595436 PCI: 00:15.3: enabled 0
782 17:50:12.598417 PCI: 00:16.0: enabled 1
783 17:50:12.598981 PCI: 00:16.1: enabled 0
784 17:50:12.601666 PCI: 00:16.2: enabled 0
785 17:50:12.605360 PCI: 00:16.3: enabled 0
786 17:50:12.608247 PCI: 00:16.4: enabled 0
787 17:50:12.611893 PCI: 00:16.5: enabled 0
788 17:50:12.612341 PCI: 00:17.0: enabled 1
789 17:50:12.615399 PCI: 00:19.0: enabled 1
790 17:50:12.618129 I2C: 00:1a: enabled 1
791 17:50:12.621746 I2C: 00:38: enabled 1
792 17:50:12.625251 I2C: 00:39: enabled 1
793 17:50:12.625779 I2C: 00:3a: enabled 1
794 17:50:12.628678 I2C: 00:3b: enabled 1
795 17:50:12.631922 PCI: 00:19.1: enabled 0
796 17:50:12.634770 PCI: 00:19.2: enabled 0
797 17:50:12.635195 PCI: 00:1a.0: enabled 0
798 17:50:12.638051 PCI: 00:1c.0: enabled 0
799 17:50:12.641511 PCI: 00:1c.1: enabled 0
800 17:50:12.645275 PCI: 00:1c.2: enabled 0
801 17:50:12.648382 PCI: 00:1c.3: enabled 0
802 17:50:12.648913 PCI: 00:1c.4: enabled 0
803 17:50:12.651766 PCI: 00:1c.5: enabled 0
804 17:50:12.654623 PCI: 00:1c.6: enabled 0
805 17:50:12.658072 PCI: 00:1c.7: enabled 0
806 17:50:12.661585 PCI: 00:1d.0: enabled 1
807 17:50:12.662009 PCI: 00:1d.1: enabled 0
808 17:50:12.664945 PCI: 00:1d.2: enabled 0
809 17:50:12.667809 PCI: 00:1d.3: enabled 0
810 17:50:12.671447 PCI: 00:1d.4: enabled 0
811 17:50:12.674515 PCI: 00:1d.5: enabled 1
812 17:50:12.674939 PCI: 00:00.0: enabled 1
813 17:50:12.677958 PCI: 00:1e.0: enabled 1
814 17:50:12.681257 PCI: 00:1e.1: enabled 0
815 17:50:12.684630 PCI: 00:1e.2: enabled 1
816 17:50:12.685055 SPI: 00: enabled 1
817 17:50:12.687958 PCI: 00:1e.3: enabled 1
818 17:50:12.691104 SPI: 01: enabled 1
819 17:50:12.694281 PCI: 00:1f.0: enabled 1
820 17:50:12.697535 PNP: 0c09.0: enabled 1
821 17:50:12.697973 PCI: 00:1f.1: enabled 1
822 17:50:12.700708 PCI: 00:1f.2: enabled 1
823 17:50:12.703886 PCI: 00:1f.3: enabled 1
824 17:50:12.707669 PCI: 00:1f.4: enabled 1
825 17:50:12.710764 PCI: 00:1f.5: enabled 1
826 17:50:12.711377 PCI: 00:1f.6: enabled 0
827 17:50:12.714301 Root Device scanning...
828 17:50:12.717696 scan_static_bus for Root Device
829 17:50:12.720535 CPU_CLUSTER: 0 enabled
830 17:50:12.720956 DOMAIN: 0000 enabled
831 17:50:12.723914 DOMAIN: 0000 scanning...
832 17:50:12.727268 PCI: pci_scan_bus for bus 00
833 17:50:12.730977 PCI: 00:00.0 [8086/0000] ops
834 17:50:12.733535 PCI: 00:00.0 [8086/9b61] enabled
835 17:50:12.737451 PCI: 00:02.0 [8086/0000] bus ops
836 17:50:12.740888 PCI: 00:02.0 [8086/9b41] enabled
837 17:50:12.743755 PCI: 00:04.0 [8086/1903] disabled
838 17:50:12.747209 PCI: 00:08.0 [8086/1911] enabled
839 17:50:12.750526 PCI: 00:12.0 [8086/02f9] enabled
840 17:50:12.754028 PCI: 00:14.0 [8086/0000] bus ops
841 17:50:12.757409 PCI: 00:14.0 [8086/02ed] enabled
842 17:50:12.760875 PCI: 00:14.2 [8086/02ef] enabled
843 17:50:12.763611 PCI: 00:14.3 [8086/02f0] enabled
844 17:50:12.766834 PCI: 00:15.0 [8086/0000] bus ops
845 17:50:12.770495 PCI: 00:15.0 [8086/02e8] enabled
846 17:50:12.773993 PCI: 00:15.1 [8086/0000] bus ops
847 17:50:12.777287 PCI: 00:15.1 [8086/02e9] enabled
848 17:50:12.780397 PCI: 00:16.0 [8086/0000] ops
849 17:50:12.783949 PCI: 00:16.0 [8086/02e0] enabled
850 17:50:12.787316 PCI: 00:17.0 [8086/0000] ops
851 17:50:12.790419 PCI: 00:17.0 [8086/02d3] enabled
852 17:50:12.793449 PCI: 00:19.0 [8086/0000] bus ops
853 17:50:12.797201 PCI: 00:19.0 [8086/02c5] enabled
854 17:50:12.800307 PCI: 00:1d.0 [8086/0000] bus ops
855 17:50:12.803521 PCI: 00:1d.0 [8086/02b0] enabled
856 17:50:12.810294 PCI: Static device PCI: 00:1d.5 not found, disabling it.
857 17:50:12.813936 PCI: 00:1e.0 [8086/0000] ops
858 17:50:12.816646 PCI: 00:1e.0 [8086/02a8] enabled
859 17:50:12.819916 PCI: 00:1e.2 [8086/0000] bus ops
860 17:50:12.823347 PCI: 00:1e.2 [8086/02aa] enabled
861 17:50:12.826724 PCI: 00:1e.3 [8086/0000] bus ops
862 17:50:12.830108 PCI: 00:1e.3 [8086/02ab] enabled
863 17:50:12.833317 PCI: 00:1f.0 [8086/0000] bus ops
864 17:50:12.836609 PCI: 00:1f.0 [8086/0284] enabled
865 17:50:12.840082 PCI: Static device PCI: 00:1f.1 not found, disabling it.
866 17:50:12.846603 PCI: Static device PCI: 00:1f.2 not found, disabling it.
867 17:50:12.849610 PCI: 00:1f.3 [8086/0000] bus ops
868 17:50:12.853247 PCI: 00:1f.3 [8086/02c8] enabled
869 17:50:12.856790 PCI: 00:1f.4 [8086/0000] bus ops
870 17:50:12.859431 PCI: 00:1f.4 [8086/02a3] enabled
871 17:50:12.863105 PCI: 00:1f.5 [8086/0000] bus ops
872 17:50:12.866391 PCI: 00:1f.5 [8086/02a4] enabled
873 17:50:12.869782 PCI: Leftover static devices:
874 17:50:12.870201 PCI: 00:05.0
875 17:50:12.873160 PCI: 00:12.5
876 17:50:12.873578 PCI: 00:12.6
877 17:50:12.876449 PCI: 00:14.1
878 17:50:12.876868 PCI: 00:14.5
879 17:50:12.877201 PCI: 00:15.2
880 17:50:12.879884 PCI: 00:15.3
881 17:50:12.880302 PCI: 00:16.1
882 17:50:12.883036 PCI: 00:16.2
883 17:50:12.883548 PCI: 00:16.3
884 17:50:12.883953 PCI: 00:16.4
885 17:50:12.886486 PCI: 00:16.5
886 17:50:12.887006 PCI: 00:19.1
887 17:50:12.889665 PCI: 00:19.2
888 17:50:12.890082 PCI: 00:1a.0
889 17:50:12.892986 PCI: 00:1c.0
890 17:50:12.893403 PCI: 00:1c.1
891 17:50:12.893736 PCI: 00:1c.2
892 17:50:12.896207 PCI: 00:1c.3
893 17:50:12.896672 PCI: 00:1c.4
894 17:50:12.899470 PCI: 00:1c.5
895 17:50:12.899948 PCI: 00:1c.6
896 17:50:12.900285 PCI: 00:1c.7
897 17:50:12.902970 PCI: 00:1d.1
898 17:50:12.903389 PCI: 00:1d.2
899 17:50:12.906254 PCI: 00:1d.3
900 17:50:12.906721 PCI: 00:1d.4
901 17:50:12.907091 PCI: 00:1d.5
902 17:50:12.909204 PCI: 00:1e.1
903 17:50:12.909624 PCI: 00:1f.1
904 17:50:12.912783 PCI: 00:1f.2
905 17:50:12.913199 PCI: 00:1f.6
906 17:50:12.916155 PCI: Check your devicetree.cb.
907 17:50:12.919524 PCI: 00:02.0 scanning...
908 17:50:12.922788 scan_generic_bus for PCI: 00:02.0
909 17:50:12.926168 scan_generic_bus for PCI: 00:02.0 done
910 17:50:12.932398 scan_bus: scanning of bus PCI: 00:02.0 took 10189 usecs
911 17:50:12.935872 PCI: 00:14.0 scanning...
912 17:50:12.939176 scan_static_bus for PCI: 00:14.0
913 17:50:12.939604 USB0 port 0 enabled
914 17:50:12.942632 USB0 port 0 scanning...
915 17:50:12.945867 scan_static_bus for USB0 port 0
916 17:50:12.949173 USB2 port 0 enabled
917 17:50:12.949512 USB2 port 1 enabled
918 17:50:12.952316 USB2 port 2 disabled
919 17:50:12.955689 USB2 port 3 disabled
920 17:50:12.955880 USB2 port 5 disabled
921 17:50:12.959068 USB2 port 6 enabled
922 17:50:12.959253 USB2 port 9 enabled
923 17:50:12.962386 USB3 port 0 enabled
924 17:50:12.965573 USB3 port 1 enabled
925 17:50:12.965727 USB3 port 2 enabled
926 17:50:12.968910 USB3 port 3 enabled
927 17:50:12.972042 USB3 port 4 disabled
928 17:50:12.972203 USB2 port 0 scanning...
929 17:50:12.975397 scan_static_bus for USB2 port 0
930 17:50:12.982115 scan_static_bus for USB2 port 0 done
931 17:50:12.985011 scan_bus: scanning of bus USB2 port 0 took 9695 usecs
932 17:50:12.988903 USB2 port 1 scanning...
933 17:50:12.991555 scan_static_bus for USB2 port 1
934 17:50:12.995026 scan_static_bus for USB2 port 1 done
935 17:50:13.001683 scan_bus: scanning of bus USB2 port 1 took 9704 usecs
936 17:50:13.001775 USB2 port 6 scanning...
937 17:50:13.005107 scan_static_bus for USB2 port 6
938 17:50:13.011925 scan_static_bus for USB2 port 6 done
939 17:50:13.015217 scan_bus: scanning of bus USB2 port 6 took 9703 usecs
940 17:50:13.018690 USB2 port 9 scanning...
941 17:50:13.021557 scan_static_bus for USB2 port 9
942 17:50:13.025152 scan_static_bus for USB2 port 9 done
943 17:50:13.031665 scan_bus: scanning of bus USB2 port 9 took 9702 usecs
944 17:50:13.031889 USB3 port 0 scanning...
945 17:50:13.034988 scan_static_bus for USB3 port 0
946 17:50:13.041943 scan_static_bus for USB3 port 0 done
947 17:50:13.045680 scan_bus: scanning of bus USB3 port 0 took 9692 usecs
948 17:50:13.048523 USB3 port 1 scanning...
949 17:50:13.051881 scan_static_bus for USB3 port 1
950 17:50:13.055613 scan_static_bus for USB3 port 1 done
951 17:50:13.062194 scan_bus: scanning of bus USB3 port 1 took 9687 usecs
952 17:50:13.062647 USB3 port 2 scanning...
953 17:50:13.065434 scan_static_bus for USB3 port 2
954 17:50:13.072273 scan_static_bus for USB3 port 2 done
955 17:50:13.075537 scan_bus: scanning of bus USB3 port 2 took 9693 usecs
956 17:50:13.078933 USB3 port 3 scanning...
957 17:50:13.082015 scan_static_bus for USB3 port 3
958 17:50:13.085465 scan_static_bus for USB3 port 3 done
959 17:50:13.092059 scan_bus: scanning of bus USB3 port 3 took 9701 usecs
960 17:50:13.095276 scan_static_bus for USB0 port 0 done
961 17:50:13.098235 scan_bus: scanning of bus USB0 port 0 took 155263 usecs
962 17:50:13.104887 scan_static_bus for PCI: 00:14.0 done
963 17:50:13.108614 scan_bus: scanning of bus PCI: 00:14.0 took 172879 usecs
964 17:50:13.112152 PCI: 00:15.0 scanning...
965 17:50:13.115420 scan_generic_bus for PCI: 00:15.0
966 17:50:13.118696 bus: PCI: 00:15.0[0]->I2C: 01:15 enabled
967 17:50:13.124810 scan_generic_bus for PCI: 00:15.0 done
968 17:50:13.128730 scan_bus: scanning of bus PCI: 00:15.0 took 14295 usecs
969 17:50:13.131524 PCI: 00:15.1 scanning...
970 17:50:13.134789 scan_generic_bus for PCI: 00:15.1
971 17:50:13.138287 bus: PCI: 00:15.1[0]->I2C: 02:5d enabled
972 17:50:13.145179 bus: PCI: 00:15.1[0]->GENERIC: 0.0 enabled
973 17:50:13.148504 scan_generic_bus for PCI: 00:15.1 done
974 17:50:13.154730 scan_bus: scanning of bus PCI: 00:15.1 took 18594 usecs
975 17:50:13.155206 PCI: 00:19.0 scanning...
976 17:50:13.158391 scan_generic_bus for PCI: 00:19.0
977 17:50:13.164831 bus: PCI: 00:19.0[0]->I2C: 03:1a enabled
978 17:50:13.168349 bus: PCI: 00:19.0[0]->I2C: 03:38 enabled
979 17:50:13.171582 bus: PCI: 00:19.0[0]->I2C: 03:39 enabled
980 17:50:13.175010 bus: PCI: 00:19.0[0]->I2C: 03:3a enabled
981 17:50:13.181925 bus: PCI: 00:19.0[0]->I2C: 03:3b enabled
982 17:50:13.184672 scan_generic_bus for PCI: 00:19.0 done
983 17:50:13.187878 scan_bus: scanning of bus PCI: 00:19.0 took 30715 usecs
984 17:50:13.191411 PCI: 00:1d.0 scanning...
985 17:50:13.194707 do_pci_scan_bridge for PCI: 00:1d.0
986 17:50:13.198107 PCI: pci_scan_bus for bus 01
987 17:50:13.201422 PCI: 01:00.0 [1c5c/1327] enabled
988 17:50:13.204819 Enabling Common Clock Configuration
989 17:50:13.211473 L1 Sub-State supported from root port 29
990 17:50:13.212120 L1 Sub-State Support = 0xf
991 17:50:13.215039 CommonModeRestoreTime = 0x28
992 17:50:13.221402 Power On Value = 0x16, Power On Scale = 0x0
993 17:50:13.221983 ASPM: Enabled L1
994 17:50:13.227920 scan_bus: scanning of bus PCI: 00:1d.0 took 32777 usecs
995 17:50:13.231187 PCI: 00:1e.2 scanning...
996 17:50:13.234190 scan_generic_bus for PCI: 00:1e.2
997 17:50:13.237754 bus: PCI: 00:1e.2[0]->SPI: 00 enabled
998 17:50:13.241388 scan_generic_bus for PCI: 00:1e.2 done
999 17:50:13.247481 scan_bus: scanning of bus PCI: 00:1e.2 took 13996 usecs
1000 17:50:13.251091 PCI: 00:1e.3 scanning...
1001 17:50:13.254552 scan_generic_bus for PCI: 00:1e.3
1002 17:50:13.257364 bus: PCI: 00:1e.3[0]->SPI: 01 enabled
1003 17:50:13.260757 scan_generic_bus for PCI: 00:1e.3 done
1004 17:50:13.267430 scan_bus: scanning of bus PCI: 00:1e.3 took 14000 usecs
1005 17:50:13.267956 PCI: 00:1f.0 scanning...
1006 17:50:13.271388 scan_static_bus for PCI: 00:1f.0
1007 17:50:13.274536 PNP: 0c09.0 enabled
1008 17:50:13.277902 scan_static_bus for PCI: 00:1f.0 done
1009 17:50:13.284155 scan_bus: scanning of bus PCI: 00:1f.0 took 12053 usecs
1010 17:50:13.287858 PCI: 00:1f.3 scanning...
1011 17:50:13.290814 scan_bus: scanning of bus PCI: 00:1f.3 took 2850 usecs
1012 17:50:13.294022 PCI: 00:1f.4 scanning...
1013 17:50:13.297453 scan_generic_bus for PCI: 00:1f.4
1014 17:50:13.300742 scan_generic_bus for PCI: 00:1f.4 done
1015 17:50:13.307881 scan_bus: scanning of bus PCI: 00:1f.4 took 10181 usecs
1016 17:50:13.311231 PCI: 00:1f.5 scanning...
1017 17:50:13.314563 scan_generic_bus for PCI: 00:1f.5
1018 17:50:13.317709 scan_generic_bus for PCI: 00:1f.5 done
1019 17:50:13.324524 scan_bus: scanning of bus PCI: 00:1f.5 took 10189 usecs
1020 17:50:13.330802 scan_bus: scanning of bus DOMAIN: 0000 took 604721 usecs
1021 17:50:13.334163 scan_static_bus for Root Device done
1022 17:50:13.337377 scan_bus: scanning of bus Root Device took 624583 usecs
1023 17:50:13.340682 done
1024 17:50:13.341265 Chrome EC: UHEPI supported
1025 17:50:13.347519 FMAP: area RECOVERY_MRC_CACHE found @ ad0000 (65536 bytes)
1026 17:50:13.354208 MRC: Checking cached data update for 'RECOVERY_MRC_CACHE'.
1027 17:50:13.360781 SF: Detected 00 0000 with sector size 0x1000, total 0x1000000
1028 17:50:13.367346 FMAP: area UNIFIED_MRC_CACHE found @ ad0000 (131072 bytes)
1029 17:50:13.370587 SPI flash protection: WPSW=0 SRP0=0
1030 17:50:13.377351 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
1031 17:50:13.380483 BS: BS_DEV_ENUMERATE times (ms): entry 0 run 9 exit 2
1032 17:50:13.383969 found VGA at PCI: 00:02.0
1033 17:50:13.387404 Setting up VGA for PCI: 00:02.0
1034 17:50:13.390808 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
1035 17:50:13.397466 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
1036 17:50:13.400895 Allocating resources...
1037 17:50:13.401401 Reading resources...
1038 17:50:13.407349 Root Device read_resources bus 0 link: 0
1039 17:50:13.410782 CPU_CLUSTER: 0 read_resources bus 0 link: 0
1040 17:50:13.416957 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
1041 17:50:13.420397 DOMAIN: 0000 read_resources bus 0 link: 0
1042 17:50:13.427233 PCI: 00:14.0 read_resources bus 0 link: 0
1043 17:50:13.430689 USB0 port 0 read_resources bus 0 link: 0
1044 17:50:13.438367 USB0 port 0 read_resources bus 0 link: 0 done
1045 17:50:13.441799 PCI: 00:14.0 read_resources bus 0 link: 0 done
1046 17:50:13.449371 PCI: 00:15.0 read_resources bus 1 link: 0
1047 17:50:13.452616 PCI: 00:15.0 read_resources bus 1 link: 0 done
1048 17:50:13.459491 PCI: 00:15.1 read_resources bus 2 link: 0
1049 17:50:13.462611 PCI: 00:15.1 read_resources bus 2 link: 0 done
1050 17:50:13.469644 PCI: 00:19.0 read_resources bus 3 link: 0
1051 17:50:13.476744 PCI: 00:19.0 read_resources bus 3 link: 0 done
1052 17:50:13.479708 PCI: 00:1d.0 read_resources bus 1 link: 0
1053 17:50:13.486172 PCI: 00:1d.0 read_resources bus 1 link: 0 done
1054 17:50:13.489888 PCI: 00:1e.2 read_resources bus 4 link: 0
1055 17:50:13.496322 PCI: 00:1e.2 read_resources bus 4 link: 0 done
1056 17:50:13.499609 PCI: 00:1e.3 read_resources bus 5 link: 0
1057 17:50:13.506374 PCI: 00:1e.3 read_resources bus 5 link: 0 done
1058 17:50:13.509683 PCI: 00:1f.0 read_resources bus 0 link: 0
1059 17:50:13.516020 PCI: 00:1f.0 read_resources bus 0 link: 0 done
1060 17:50:13.522634 DOMAIN: 0000 read_resources bus 0 link: 0 done
1061 17:50:13.526208 Root Device read_resources bus 0 link: 0 done
1062 17:50:13.529569 Done reading resources.
1063 17:50:13.535749 Show resources in subtree (Root Device)...After reading.
1064 17:50:13.539297 Root Device child on link 0 CPU_CLUSTER: 0
1065 17:50:13.542697 CPU_CLUSTER: 0 child on link 0 APIC: 00
1066 17:50:13.543114 APIC: 00
1067 17:50:13.545588 APIC: 03
1068 17:50:13.546002 APIC: 06
1069 17:50:13.549177 APIC: 01
1070 17:50:13.549589 APIC: 02
1071 17:50:13.549915 APIC: 07
1072 17:50:13.552524 APIC: 04
1073 17:50:13.553132 APIC: 05
1074 17:50:13.555856 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1075 17:50:13.612312 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1076 17:50:13.613369 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100
1077 17:50:13.613758 PCI: 00:00.0
1078 17:50:13.614087 PCI: 00:00.0 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1079 17:50:13.614400 PCI: 00:00.0 resource base fed10000 size 8000 align 0 gran 0 limit 0 flags f0000200 index 1
1080 17:50:13.614769 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1081 17:50:13.662091 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1082 17:50:13.662895 PCI: 00:00.0 resource base fc000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1083 17:50:13.663256 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1084 17:50:13.663577 PCI: 00:00.0 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 6
1085 17:50:13.663978 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1086 17:50:13.664289 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1087 17:50:13.669578 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 9
1088 17:50:13.679907 PCI: 00:00.0 resource base c0000 size 99f40000 align 0 gran 0 limit 0 flags e0004200 index a
1089 17:50:13.689329 PCI: 00:00.0 resource base 9a000000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index b
1090 17:50:13.699058 PCI: 00:00.0 resource base 9b000000 size 4800000 align 0 gran 0 limit 0 flags f0000200 index c
1091 17:50:13.708858 PCI: 00:00.0 resource base 100000000 size 35e800000 align 0 gran 0 limit 0 flags e0004200 index d
1092 17:50:13.718860 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index e
1093 17:50:13.728597 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index f
1094 17:50:13.728688 PCI: 00:02.0
1095 17:50:13.738526 PCI: 00:02.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1096 17:50:13.748633 PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
1097 17:50:13.758839 PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
1098 17:50:13.758936 PCI: 00:04.0
1099 17:50:13.761678 PCI: 00:08.0
1100 17:50:13.771989 PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1101 17:50:13.772073 PCI: 00:12.0
1102 17:50:13.781450 PCI: 00:12.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1103 17:50:13.788259 PCI: 00:14.0 child on link 0 USB0 port 0
1104 17:50:13.798349 PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1105 17:50:13.801788 USB0 port 0 child on link 0 USB2 port 0
1106 17:50:13.805195 USB2 port 0
1107 17:50:13.805275 USB2 port 1
1108 17:50:13.808434 USB2 port 2
1109 17:50:13.808514 USB2 port 3
1110 17:50:13.811555 USB2 port 5
1111 17:50:13.811660 USB2 port 6
1112 17:50:13.814804 USB2 port 9
1113 17:50:13.814919 USB3 port 0
1114 17:50:13.817883 USB3 port 1
1115 17:50:13.817999 USB3 port 2
1116 17:50:13.821322 USB3 port 3
1117 17:50:13.821405 USB3 port 4
1118 17:50:13.824773 PCI: 00:14.2
1119 17:50:13.835216 PCI: 00:14.2 resource base 0 size 2000 align 13 gran 13 limit ffffffffffffffff flags 201 index 10
1120 17:50:13.844707 PCI: 00:14.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
1121 17:50:13.844818 PCI: 00:14.3
1122 17:50:13.854879 PCI: 00:14.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1123 17:50:13.861522 PCI: 00:15.0 child on link 0 I2C: 01:15
1124 17:50:13.871482 PCI: 00:15.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1125 17:50:13.871571 I2C: 01:15
1126 17:50:13.874404 PCI: 00:15.1 child on link 0 I2C: 02:5d
1127 17:50:13.884646 PCI: 00:15.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1128 17:50:13.888159 I2C: 02:5d
1129 17:50:13.888265 GENERIC: 0.0
1130 17:50:13.891554 PCI: 00:16.0
1131 17:50:13.901163 PCI: 00:16.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1132 17:50:13.901335 PCI: 00:17.0
1133 17:50:13.910699 PCI: 00:17.0 resource base 0 size 2000 align 13 gran 13 limit ffffffff flags 200 index 10
1134 17:50:13.920777 PCI: 00:17.0 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 14
1135 17:50:13.927555 PCI: 00:17.0 resource base 0 size 8 align 3 gran 3 limit ffff flags 100 index 18
1136 17:50:13.937694 PCI: 00:17.0 resource base 0 size 4 align 2 gran 2 limit ffff flags 100 index 1c
1137 17:50:13.944174 PCI: 00:17.0 resource base 0 size 20 align 5 gran 5 limit ffff flags 100 index 20
1138 17:50:13.954251 PCI: 00:17.0 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 24
1139 17:50:13.957725 PCI: 00:19.0 child on link 0 I2C: 03:1a
1140 17:50:13.967117 PCI: 00:19.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1141 17:50:13.970265 I2C: 03:1a
1142 17:50:13.970541 I2C: 03:38
1143 17:50:13.973667 I2C: 03:39
1144 17:50:13.973819 I2C: 03:3a
1145 17:50:13.977013 I2C: 03:3b
1146 17:50:13.980744 PCI: 00:1d.0 child on link 0 PCI: 01:00.0
1147 17:50:13.990528 PCI: 00:1d.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
1148 17:50:14.000304 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
1149 17:50:14.006935 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
1150 17:50:14.010289 PCI: 01:00.0
1151 17:50:14.019952 PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1152 17:50:14.023229 PCI: 00:1e.0
1153 17:50:14.033401 PCI: 00:1e.0 resource base fe032000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1154 17:50:14.043146 PCI: 00:1e.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
1155 17:50:14.046572 PCI: 00:1e.2 child on link 0 SPI: 00
1156 17:50:14.056364 PCI: 00:1e.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1157 17:50:14.056457 SPI: 00
1158 17:50:14.063097 PCI: 00:1e.3 child on link 0 SPI: 01
1159 17:50:14.072794 PCI: 00:1e.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1160 17:50:14.072884 SPI: 01
1161 17:50:14.075985 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1162 17:50:14.085748 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1163 17:50:14.096207 PCI: 00:1f.0 resource base 1800 size 100 align 0 gran 0 limit 0 flags c0000100 index 20
1164 17:50:14.096301 PNP: 0c09.0
1165 17:50:14.106341 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1166 17:50:14.106440 PCI: 00:1f.3
1167 17:50:14.115441 PCI: 00:1f.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1168 17:50:14.125309 PCI: 00:1f.3 resource base 0 size 100000 align 20 gran 20 limit ffffffffffffffff flags 201 index 20
1169 17:50:14.128703 PCI: 00:1f.4
1170 17:50:14.139102 PCI: 00:1f.4 resource base efa0 size 20 align 0 gran 0 limit efbf flags f0000100 index 20
1171 17:50:14.149134 PCI: 00:1f.4 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 10
1172 17:50:14.149217 PCI: 00:1f.5
1173 17:50:14.158179 PCI: 00:1f.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
1174 17:50:14.164805 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
1175 17:50:14.171615 PCI: 00:1d.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff
1176 17:50:14.178640 PCI: 00:1d.0 io: base: 0 size: 0 align: 12 gran: 12 limit: ffff done
1177 17:50:14.181913 PCI: 00:02.0 20 * [0x0 - 0x3f] io
1178 17:50:14.185318 PCI: 00:17.0 20 * [0x40 - 0x5f] io
1179 17:50:14.188040 PCI: 00:17.0 18 * [0x60 - 0x67] io
1180 17:50:14.191571 PCI: 00:17.0 1c * [0x68 - 0x6b] io
1181 17:50:14.198270 DOMAIN: 0000 io: base: 6c size: 6c align: 6 gran: 0 limit: ffff done
1182 17:50:14.205008 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff
1183 17:50:14.214628 PCI: 00:1d.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff
1184 17:50:14.221409 PCI: 00:1d.0 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
1185 17:50:14.227493 PCI: 00:1d.0 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff
1186 17:50:14.231299 PCI: 01:00.0 10 * [0x0 - 0x3fff] mem
1187 17:50:14.241214 PCI: 00:1d.0 mem: base: 4000 size: 100000 align: 20 gran: 20 limit: ffffffff done
1188 17:50:14.244384 PCI: 00:02.0 18 * [0x0 - 0xfffffff] prefmem
1189 17:50:14.250918 PCI: 00:02.0 10 * [0x10000000 - 0x10ffffff] mem
1190 17:50:14.254126 PCI: 00:1d.0 20 * [0x11000000 - 0x110fffff] mem
1191 17:50:14.260681 PCI: 00:1f.3 20 * [0x11100000 - 0x111fffff] mem
1192 17:50:14.263955 PCI: 00:14.0 10 * [0x11200000 - 0x1120ffff] mem
1193 17:50:14.271033 PCI: 00:14.3 10 * [0x11210000 - 0x11213fff] mem
1194 17:50:14.273845 PCI: 00:1f.3 10 * [0x11214000 - 0x11217fff] mem
1195 17:50:14.280679 PCI: 00:14.2 10 * [0x11218000 - 0x11219fff] mem
1196 17:50:14.284048 PCI: 00:17.0 10 * [0x1121a000 - 0x1121bfff] mem
1197 17:50:14.290492 PCI: 00:08.0 10 * [0x1121c000 - 0x1121cfff] mem
1198 17:50:14.293874 PCI: 00:12.0 10 * [0x1121d000 - 0x1121dfff] mem
1199 17:50:14.297491 PCI: 00:14.2 18 * [0x1121e000 - 0x1121efff] mem
1200 17:50:14.304042 PCI: 00:15.0 10 * [0x1121f000 - 0x1121ffff] mem
1201 17:50:14.307190 PCI: 00:15.1 10 * [0x11220000 - 0x11220fff] mem
1202 17:50:14.313442 PCI: 00:16.0 10 * [0x11221000 - 0x11221fff] mem
1203 17:50:14.316693 PCI: 00:19.0 10 * [0x11222000 - 0x11222fff] mem
1204 17:50:14.323563 PCI: 00:1e.0 18 * [0x11223000 - 0x11223fff] mem
1205 17:50:14.326918 PCI: 00:1e.2 10 * [0x11224000 - 0x11224fff] mem
1206 17:50:14.333078 PCI: 00:1e.3 10 * [0x11225000 - 0x11225fff] mem
1207 17:50:14.336315 PCI: 00:1f.5 10 * [0x11226000 - 0x11226fff] mem
1208 17:50:14.343530 PCI: 00:17.0 24 * [0x11227000 - 0x112277ff] mem
1209 17:50:14.346684 PCI: 00:17.0 14 * [0x11228000 - 0x112280ff] mem
1210 17:50:14.353422 PCI: 00:1f.4 10 * [0x11229000 - 0x112290ff] mem
1211 17:50:14.359542 DOMAIN: 0000 mem: base: 11229100 size: 11229100 align: 28 gran: 0 limit: ffffffff done
1212 17:50:14.362970 avoid_fixed_resources: DOMAIN: 0000
1213 17:50:14.369385 avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff
1214 17:50:14.376374 avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff
1215 17:50:14.383025 constrain_resources: PCI: 00:00.0 00 base e0000000 limit efffffff mem (fixed)
1216 17:50:14.392539 constrain_resources: PCI: 00:00.0 09 base 00000000 limit 0009ffff mem (fixed)
1217 17:50:14.399212 constrain_resources: PCI: 00:00.0 0a base 000c0000 limit 99ffffff mem (fixed)
1218 17:50:14.406118 constrain_resources: PCI: 00:00.0 0b base 9a000000 limit 9affffff mem (fixed)
1219 17:50:14.415481 constrain_resources: PCI: 00:00.0 0c base 9b000000 limit 9f7fffff mem (fixed)
1220 17:50:14.422453 constrain_resources: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
1221 17:50:14.428769 constrain_resources: PCI: 00:1f.0 20 base 00001800 limit 000018ff io (fixed)
1222 17:50:14.438891 constrain_resources: PCI: 00:1f.4 20 base 0000efa0 limit 0000efbf io (fixed)
1223 17:50:14.445547 avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001900 limit 0000ef9f
1224 17:50:14.451930 avoid_fixed_resources:@DOMAIN: 0000 10000100 base c0000000 limit dfffffff
1225 17:50:14.455229 Setting resources...
1226 17:50:14.458610 DOMAIN: 0000 io: base:1900 size:6c align:6 gran:0 limit:ef9f
1227 17:50:14.465318 PCI: 00:02.0 20 * [0x1c00 - 0x1c3f] io
1228 17:50:14.468281 PCI: 00:17.0 20 * [0x1c40 - 0x1c5f] io
1229 17:50:14.472224 PCI: 00:17.0 18 * [0x1c60 - 0x1c67] io
1230 17:50:14.475318 PCI: 00:17.0 1c * [0x1c68 - 0x1c6b] io
1231 17:50:14.481854 DOMAIN: 0000 io: next_base: 1c6c size: 6c align: 6 gran: 0 done
1232 17:50:14.488561 PCI: 00:1d.0 io: base:ef9f size:0 align:12 gran:12 limit:ef9f
1233 17:50:14.494988 PCI: 00:1d.0 io: next_base: ef9f size: 0 align: 12 gran: 12 done
1234 17:50:14.501479 DOMAIN: 0000 mem: base:c0000000 size:11229100 align:28 gran:0 limit:dfffffff
1235 17:50:14.508252 PCI: 00:02.0 18 * [0xc0000000 - 0xcfffffff] prefmem
1236 17:50:14.511734 PCI: 00:02.0 10 * [0xd0000000 - 0xd0ffffff] mem
1237 17:50:14.518178 PCI: 00:1d.0 20 * [0xd1000000 - 0xd10fffff] mem
1238 17:50:14.521416 PCI: 00:1f.3 20 * [0xd1100000 - 0xd11fffff] mem
1239 17:50:14.528196 PCI: 00:14.0 10 * [0xd1200000 - 0xd120ffff] mem
1240 17:50:14.531577 PCI: 00:14.3 10 * [0xd1210000 - 0xd1213fff] mem
1241 17:50:14.537701 PCI: 00:1f.3 10 * [0xd1214000 - 0xd1217fff] mem
1242 17:50:14.541147 PCI: 00:14.2 10 * [0xd1218000 - 0xd1219fff] mem
1243 17:50:14.547979 PCI: 00:17.0 10 * [0xd121a000 - 0xd121bfff] mem
1244 17:50:14.551375 PCI: 00:08.0 10 * [0xd121c000 - 0xd121cfff] mem
1245 17:50:14.558008 PCI: 00:12.0 10 * [0xd121d000 - 0xd121dfff] mem
1246 17:50:14.561103 PCI: 00:14.2 18 * [0xd121e000 - 0xd121efff] mem
1247 17:50:14.567774 PCI: 00:15.0 10 * [0xd121f000 - 0xd121ffff] mem
1248 17:50:14.571331 PCI: 00:15.1 10 * [0xd1220000 - 0xd1220fff] mem
1249 17:50:14.574008 PCI: 00:16.0 10 * [0xd1221000 - 0xd1221fff] mem
1250 17:50:14.580733 PCI: 00:19.0 10 * [0xd1222000 - 0xd1222fff] mem
1251 17:50:14.584414 PCI: 00:1e.0 18 * [0xd1223000 - 0xd1223fff] mem
1252 17:50:14.591080 PCI: 00:1e.2 10 * [0xd1224000 - 0xd1224fff] mem
1253 17:50:14.594310 PCI: 00:1e.3 10 * [0xd1225000 - 0xd1225fff] mem
1254 17:50:14.600679 PCI: 00:1f.5 10 * [0xd1226000 - 0xd1226fff] mem
1255 17:50:14.604278 PCI: 00:17.0 24 * [0xd1227000 - 0xd12277ff] mem
1256 17:50:14.610626 PCI: 00:17.0 14 * [0xd1228000 - 0xd12280ff] mem
1257 17:50:14.613832 PCI: 00:1f.4 10 * [0xd1229000 - 0xd12290ff] mem
1258 17:50:14.620670 DOMAIN: 0000 mem: next_base: d1229100 size: 11229100 align: 28 gran: 0 done
1259 17:50:14.630541 PCI: 00:1d.0 prefmem: base:dfffffff size:0 align:20 gran:20 limit:dfffffff
1260 17:50:14.637478 PCI: 00:1d.0 prefmem: next_base: dfffffff size: 0 align: 20 gran: 20 done
1261 17:50:14.643606 PCI: 00:1d.0 mem: base:d1000000 size:100000 align:20 gran:20 limit:d10fffff
1262 17:50:14.650308 PCI: 01:00.0 10 * [0xd1000000 - 0xd1003fff] mem
1263 17:50:14.657023 PCI: 00:1d.0 mem: next_base: d1004000 size: 100000 align: 20 gran: 20 done
1264 17:50:14.660528 Root Device assign_resources, bus 0 link: 0
1265 17:50:14.666691 DOMAIN: 0000 assign_resources, bus 0 link: 0
1266 17:50:14.673198 PCI: 00:02.0 10 <- [0x00d0000000 - 0x00d0ffffff] size 0x01000000 gran 0x18 mem64
1267 17:50:14.683526 PCI: 00:02.0 18 <- [0x00c0000000 - 0x00cfffffff] size 0x10000000 gran 0x1c prefmem64
1268 17:50:14.690138 PCI: 00:02.0 20 <- [0x0000001c00 - 0x0000001c3f] size 0x00000040 gran 0x06 io
1269 17:50:14.699933 PCI: 00:08.0 10 <- [0x00d121c000 - 0x00d121cfff] size 0x00001000 gran 0x0c mem64
1270 17:50:14.706186 PCI: 00:12.0 10 <- [0x00d121d000 - 0x00d121dfff] size 0x00001000 gran 0x0c mem64
1271 17:50:14.716111 PCI: 00:14.0 10 <- [0x00d1200000 - 0x00d120ffff] size 0x00010000 gran 0x10 mem64
1272 17:50:14.719740 PCI: 00:14.0 assign_resources, bus 0 link: 0
1273 17:50:14.722797 PCI: 00:14.0 assign_resources, bus 0 link: 0
1274 17:50:14.732903 PCI: 00:14.2 10 <- [0x00d1218000 - 0x00d1219fff] size 0x00002000 gran 0x0d mem64
1275 17:50:14.740195 PCI: 00:14.2 18 <- [0x00d121e000 - 0x00d121efff] size 0x00001000 gran 0x0c mem64
1276 17:50:14.749618 PCI: 00:14.3 10 <- [0x00d1210000 - 0x00d1213fff] size 0x00004000 gran 0x0e mem64
1277 17:50:14.756382 PCI: 00:15.0 10 <- [0x00d121f000 - 0x00d121ffff] size 0x00001000 gran 0x0c mem64
1278 17:50:14.763181 PCI: 00:15.0 assign_resources, bus 1 link: 0
1279 17:50:14.766646 PCI: 00:15.0 assign_resources, bus 1 link: 0
1280 17:50:14.776229 PCI: 00:15.1 10 <- [0x00d1220000 - 0x00d1220fff] size 0x00001000 gran 0x0c mem64
1281 17:50:14.779474 PCI: 00:15.1 assign_resources, bus 2 link: 0
1282 17:50:14.782720 PCI: 00:15.1 assign_resources, bus 2 link: 0
1283 17:50:14.792554 PCI: 00:16.0 10 <- [0x00d1221000 - 0x00d1221fff] size 0x00001000 gran 0x0c mem64
1284 17:50:14.799167 PCI: 00:17.0 10 <- [0x00d121a000 - 0x00d121bfff] size 0x00002000 gran 0x0d mem
1285 17:50:14.809581 PCI: 00:17.0 14 <- [0x00d1228000 - 0x00d12280ff] size 0x00000100 gran 0x08 mem
1286 17:50:14.815612 PCI: 00:17.0 18 <- [0x0000001c60 - 0x0000001c67] size 0x00000008 gran 0x03 io
1287 17:50:14.822286 PCI: 00:17.0 1c <- [0x0000001c68 - 0x0000001c6b] size 0x00000004 gran 0x02 io
1288 17:50:14.832206 PCI: 00:17.0 20 <- [0x0000001c40 - 0x0000001c5f] size 0x00000020 gran 0x05 io
1289 17:50:14.839240 PCI: 00:17.0 24 <- [0x00d1227000 - 0x00d12277ff] size 0x00000800 gran 0x0b mem
1290 17:50:14.848818 PCI: 00:19.0 10 <- [0x00d1222000 - 0x00d1222fff] size 0x00001000 gran 0x0c mem64
1291 17:50:14.852286 PCI: 00:19.0 assign_resources, bus 3 link: 0
1292 17:50:14.855540 PCI: 00:19.0 assign_resources, bus 3 link: 0
1293 17:50:14.865334 PCI: 00:1d.0 1c <- [0x000000ef9f - 0x000000ef9e] size 0x00000000 gran 0x0c bus 01 io
1294 17:50:14.875451 PCI: 00:1d.0 24 <- [0x00dfffffff - 0x00dffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
1295 17:50:14.882063 PCI: 00:1d.0 20 <- [0x00d1000000 - 0x00d10fffff] size 0x00100000 gran 0x14 bus 01 mem
1296 17:50:14.889101 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1297 17:50:14.895402 PCI: 01:00.0 10 <- [0x00d1000000 - 0x00d1003fff] size 0x00004000 gran 0x0e mem64
1298 17:50:14.898706 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1299 17:50:14.908637 PCI: 00:1e.0 18 <- [0x00d1223000 - 0x00d1223fff] size 0x00001000 gran 0x0c mem64
1300 17:50:14.915302 PCI: 00:1e.2 10 <- [0x00d1224000 - 0x00d1224fff] size 0x00001000 gran 0x0c mem64
1301 17:50:14.921693 PCI: 00:1e.2 assign_resources, bus 4 link: 0
1302 17:50:14.925150 PCI: 00:1e.2 assign_resources, bus 4 link: 0
1303 17:50:14.935255 PCI: 00:1e.3 10 <- [0x00d1225000 - 0x00d1225fff] size 0x00001000 gran 0x0c mem64
1304 17:50:14.938300 PCI: 00:1e.3 assign_resources, bus 5 link: 0
1305 17:50:14.941595 PCI: 00:1e.3 assign_resources, bus 5 link: 0
1306 17:50:14.949028 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1307 17:50:14.952177 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1308 17:50:14.958818 LPC: Trying to open IO window from 800 size 1ff
1309 17:50:14.965206 PCI: 00:1f.3 10 <- [0x00d1214000 - 0x00d1217fff] size 0x00004000 gran 0x0e mem64
1310 17:50:14.974959 PCI: 00:1f.3 20 <- [0x00d1100000 - 0x00d11fffff] size 0x00100000 gran 0x14 mem64
1311 17:50:14.981890 PCI: 00:1f.4 10 <- [0x00d1229000 - 0x00d12290ff] size 0x00000100 gran 0x08 mem64
1312 17:50:14.992216 PCI: 00:1f.5 10 <- [0x00d1226000 - 0x00d1226fff] size 0x00001000 gran 0x0c mem
1313 17:50:14.994807 DOMAIN: 0000 assign_resources, bus 0 link: 0
1314 17:50:15.001553 Root Device assign_resources, bus 0 link: 0
1315 17:50:15.001674 Done setting resources.
1316 17:50:15.008307 Show resources in subtree (Root Device)...After assigning values.
1317 17:50:15.014787 Root Device child on link 0 CPU_CLUSTER: 0
1318 17:50:15.018383 CPU_CLUSTER: 0 child on link 0 APIC: 00
1319 17:50:15.018556 APIC: 00
1320 17:50:15.021539 APIC: 03
1321 17:50:15.021680 APIC: 06
1322 17:50:15.021775 APIC: 01
1323 17:50:15.025032 APIC: 02
1324 17:50:15.025113 APIC: 07
1325 17:50:15.028166 APIC: 04
1326 17:50:15.028292 APIC: 05
1327 17:50:15.031590 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1328 17:50:15.041441 DOMAIN: 0000 resource base 1900 size 6c align 6 gran 0 limit ef9f flags 40040100 index 10000000
1329 17:50:15.055036 DOMAIN: 0000 resource base c0000000 size 11229100 align 28 gran 0 limit dfffffff flags 40040200 index 10000100
1330 17:50:15.055579 PCI: 00:00.0
1331 17:50:15.064824 PCI: 00:00.0 resource base e0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1332 17:50:15.074751 PCI: 00:00.0 resource base fed10000 size 8000 align 0 gran 0 limit 0 flags f0000200 index 1
1333 17:50:15.084264 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1334 17:50:15.091435 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1335 17:50:15.100959 PCI: 00:00.0 resource base fc000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1336 17:50:15.111358 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1337 17:50:15.121221 PCI: 00:00.0 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 6
1338 17:50:15.131208 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1339 17:50:15.140933 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1340 17:50:15.147151 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 9
1341 17:50:15.157121 PCI: 00:00.0 resource base c0000 size 99f40000 align 0 gran 0 limit 0 flags e0004200 index a
1342 17:50:15.167244 PCI: 00:00.0 resource base 9a000000 size 1000000 align 0 gran 0 limit 0 flags f0004200 index b
1343 17:50:15.176821 PCI: 00:00.0 resource base 9b000000 size 4800000 align 0 gran 0 limit 0 flags f0000200 index c
1344 17:50:15.187021 PCI: 00:00.0 resource base 100000000 size 35e800000 align 0 gran 0 limit 0 flags e0004200 index d
1345 17:50:15.197228 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index e
1346 17:50:15.203589 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index f
1347 17:50:15.206878 PCI: 00:02.0
1348 17:50:15.216716 PCI: 00:02.0 resource base d0000000 size 1000000 align 24 gran 24 limit d0ffffff flags 60000201 index 10
1349 17:50:15.226360 PCI: 00:02.0 resource base c0000000 size 10000000 align 28 gran 28 limit cfffffff flags 60001201 index 18
1350 17:50:15.236622 PCI: 00:02.0 resource base 1c00 size 40 align 6 gran 6 limit 1c3f flags 60000100 index 20
1351 17:50:15.239685 PCI: 00:04.0
1352 17:50:15.240313 PCI: 00:08.0
1353 17:50:15.249976 PCI: 00:08.0 resource base d121c000 size 1000 align 12 gran 12 limit d121cfff flags 60000201 index 10
1354 17:50:15.252788 PCI: 00:12.0
1355 17:50:15.263179 PCI: 00:12.0 resource base d121d000 size 1000 align 12 gran 12 limit d121dfff flags 60000201 index 10
1356 17:50:15.266271 PCI: 00:14.0 child on link 0 USB0 port 0
1357 17:50:15.276114 PCI: 00:14.0 resource base d1200000 size 10000 align 16 gran 16 limit d120ffff flags 60000201 index 10
1358 17:50:15.282935 USB0 port 0 child on link 0 USB2 port 0
1359 17:50:15.283426 USB2 port 0
1360 17:50:15.286309 USB2 port 1
1361 17:50:15.286670 USB2 port 2
1362 17:50:15.289078 USB2 port 3
1363 17:50:15.289413 USB2 port 5
1364 17:50:15.292798 USB2 port 6
1365 17:50:15.293198 USB2 port 9
1366 17:50:15.295851 USB3 port 0
1367 17:50:15.296202 USB3 port 1
1368 17:50:15.299034 USB3 port 2
1369 17:50:15.302704 USB3 port 3
1370 17:50:15.303073 USB3 port 4
1371 17:50:15.305876 PCI: 00:14.2
1372 17:50:15.315532 PCI: 00:14.2 resource base d1218000 size 2000 align 13 gran 13 limit d1219fff flags 60000201 index 10
1373 17:50:15.326010 PCI: 00:14.2 resource base d121e000 size 1000 align 12 gran 12 limit d121efff flags 60000201 index 18
1374 17:50:15.326500 PCI: 00:14.3
1375 17:50:15.335529 PCI: 00:14.3 resource base d1210000 size 4000 align 14 gran 14 limit d1213fff flags 60000201 index 10
1376 17:50:15.342260 PCI: 00:15.0 child on link 0 I2C: 01:15
1377 17:50:15.351986 PCI: 00:15.0 resource base d121f000 size 1000 align 12 gran 12 limit d121ffff flags 60000201 index 10
1378 17:50:15.352393 I2C: 01:15
1379 17:50:15.358867 PCI: 00:15.1 child on link 0 I2C: 02:5d
1380 17:50:15.368790 PCI: 00:15.1 resource base d1220000 size 1000 align 12 gran 12 limit d1220fff flags 60000201 index 10
1381 17:50:15.369202 I2C: 02:5d
1382 17:50:15.372147 GENERIC: 0.0
1383 17:50:15.372715 PCI: 00:16.0
1384 17:50:15.382328 PCI: 00:16.0 resource base d1221000 size 1000 align 12 gran 12 limit d1221fff flags 60000201 index 10
1385 17:50:15.384995 PCI: 00:17.0
1386 17:50:15.395394 PCI: 00:17.0 resource base d121a000 size 2000 align 13 gran 13 limit d121bfff flags 60000200 index 10
1387 17:50:15.405097 PCI: 00:17.0 resource base d1228000 size 100 align 12 gran 8 limit d12280ff flags 60000200 index 14
1388 17:50:15.415014 PCI: 00:17.0 resource base 1c60 size 8 align 3 gran 3 limit 1c67 flags 60000100 index 18
1389 17:50:15.421906 PCI: 00:17.0 resource base 1c68 size 4 align 2 gran 2 limit 1c6b flags 60000100 index 1c
1390 17:50:15.431568 PCI: 00:17.0 resource base 1c40 size 20 align 5 gran 5 limit 1c5f flags 60000100 index 20
1391 17:50:15.441244 PCI: 00:17.0 resource base d1227000 size 800 align 12 gran 11 limit d12277ff flags 60000200 index 24
1392 17:50:15.448594 PCI: 00:19.0 child on link 0 I2C: 03:1a
1393 17:50:15.457997 PCI: 00:19.0 resource base d1222000 size 1000 align 12 gran 12 limit d1222fff flags 60000201 index 10
1394 17:50:15.458563 I2C: 03:1a
1395 17:50:15.461479 I2C: 03:38
1396 17:50:15.462070 I2C: 03:39
1397 17:50:15.464650 I2C: 03:3a
1398 17:50:15.465208 I2C: 03:3b
1399 17:50:15.467767 PCI: 00:1d.0 child on link 0 PCI: 01:00.0
1400 17:50:15.477689 PCI: 00:1d.0 resource base ef9f size 0 align 12 gran 12 limit ef9f flags 60080102 index 1c
1401 17:50:15.487569 PCI: 00:1d.0 resource base dfffffff size 0 align 20 gran 20 limit dfffffff flags 60081202 index 24
1402 17:50:15.497410 PCI: 00:1d.0 resource base d1000000 size 100000 align 20 gran 20 limit d10fffff flags 60080202 index 20
1403 17:50:15.501250 PCI: 01:00.0
1404 17:50:15.510713 PCI: 01:00.0 resource base d1000000 size 4000 align 14 gran 14 limit d1003fff flags 60000201 index 10
1405 17:50:15.514140 PCI: 00:1e.0
1406 17:50:15.524365 PCI: 00:1e.0 resource base fe032000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1407 17:50:15.533734 PCI: 00:1e.0 resource base d1223000 size 1000 align 12 gran 12 limit d1223fff flags 60000201 index 18
1408 17:50:15.537229 PCI: 00:1e.2 child on link 0 SPI: 00
1409 17:50:15.546880 PCI: 00:1e.2 resource base d1224000 size 1000 align 12 gran 12 limit d1224fff flags 60000201 index 10
1410 17:50:15.550393 SPI: 00
1411 17:50:15.553817 PCI: 00:1e.3 child on link 0 SPI: 01
1412 17:50:15.563366 PCI: 00:1e.3 resource base d1225000 size 1000 align 12 gran 12 limit d1225fff flags 60000201 index 10
1413 17:50:15.566610 SPI: 01
1414 17:50:15.570611 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1415 17:50:15.580067 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1416 17:50:15.586720 PCI: 00:1f.0 resource base 1800 size 100 align 0 gran 0 limit 0 flags c0000100 index 20
1417 17:50:15.590118 PNP: 0c09.0
1418 17:50:15.596933 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1419 17:50:15.599564 PCI: 00:1f.3
1420 17:50:15.609796 PCI: 00:1f.3 resource base d1214000 size 4000 align 14 gran 14 limit d1217fff flags 60000201 index 10
1421 17:50:15.619940 PCI: 00:1f.3 resource base d1100000 size 100000 align 20 gran 20 limit d11fffff flags 60000201 index 20
1422 17:50:15.623192 PCI: 00:1f.4
1423 17:50:15.629580 PCI: 00:1f.4 resource base efa0 size 20 align 0 gran 0 limit efbf flags f0000100 index 20
1424 17:50:15.642507 PCI: 00:1f.4 resource base d1229000 size 100 align 12 gran 8 limit d12290ff flags 60000201 index 10
1425 17:50:15.643130 PCI: 00:1f.5
1426 17:50:15.652574 PCI: 00:1f.5 resource base d1226000 size 1000 align 12 gran 12 limit d1226fff flags 60000200 index 10
1427 17:50:15.655622 Done allocating resources.
1428 17:50:15.662497 BS: BS_DEV_RESOURCES times (ms): entry 0 run 30 exit 0
1429 17:50:15.663077 Enabling resources...
1430 17:50:15.670007 PCI: 00:00.0 subsystem <- 8086/9b61
1431 17:50:15.670425 PCI: 00:00.0 cmd <- 06
1432 17:50:15.673490 PCI: 00:02.0 subsystem <- 8086/9b41
1433 17:50:15.676715 PCI: 00:02.0 cmd <- 03
1434 17:50:15.679906 PCI: 00:08.0 cmd <- 06
1435 17:50:15.683369 PCI: 00:12.0 subsystem <- 8086/02f9
1436 17:50:15.686598 PCI: 00:12.0 cmd <- 02
1437 17:50:15.689786 PCI: 00:14.0 subsystem <- 8086/02ed
1438 17:50:15.693266 PCI: 00:14.0 cmd <- 02
1439 17:50:15.696468 PCI: 00:14.2 cmd <- 02
1440 17:50:15.700005 PCI: 00:14.3 subsystem <- 8086/02f0
1441 17:50:15.700419 PCI: 00:14.3 cmd <- 02
1442 17:50:15.706783 PCI: 00:15.0 subsystem <- 8086/02e8
1443 17:50:15.707197 PCI: 00:15.0 cmd <- 02
1444 17:50:15.710239 PCI: 00:15.1 subsystem <- 8086/02e9
1445 17:50:15.713667 PCI: 00:15.1 cmd <- 02
1446 17:50:15.716757 PCI: 00:16.0 subsystem <- 8086/02e0
1447 17:50:15.720281 PCI: 00:16.0 cmd <- 02
1448 17:50:15.722906 PCI: 00:17.0 subsystem <- 8086/02d3
1449 17:50:15.726437 PCI: 00:17.0 cmd <- 03
1450 17:50:15.729840 PCI: 00:19.0 subsystem <- 8086/02c5
1451 17:50:15.732998 PCI: 00:19.0 cmd <- 02
1452 17:50:15.736794 PCI: 00:1d.0 bridge ctrl <- 0013
1453 17:50:15.739716 PCI: 00:1d.0 subsystem <- 8086/02b0
1454 17:50:15.742840 PCI: 00:1d.0 cmd <- 06
1455 17:50:15.746494 PCI: 00:1e.0 subsystem <- 8086/02a8
1456 17:50:15.749729 PCI: 00:1e.0 cmd <- 06
1457 17:50:15.752962 PCI: 00:1e.2 subsystem <- 8086/02aa
1458 17:50:15.756415 PCI: 00:1e.2 cmd <- 06
1459 17:50:15.759445 PCI: 00:1e.3 subsystem <- 8086/02ab
1460 17:50:15.759943 PCI: 00:1e.3 cmd <- 02
1461 17:50:15.766468 PCI: 00:1f.0 subsystem <- 8086/0284
1462 17:50:15.766876 PCI: 00:1f.0 cmd <- 407
1463 17:50:15.769356 PCI: 00:1f.3 subsystem <- 8086/02c8
1464 17:50:15.772640 PCI: 00:1f.3 cmd <- 02
1465 17:50:15.776033 PCI: 00:1f.4 subsystem <- 8086/02a3
1466 17:50:15.779338 PCI: 00:1f.4 cmd <- 03
1467 17:50:15.782598 PCI: 00:1f.5 subsystem <- 8086/02a4
1468 17:50:15.785907 PCI: 00:1f.5 cmd <- 406
1469 17:50:15.795338 PCI: 01:00.0 cmd <- 02
1470 17:50:15.800475 done.
1471 17:50:15.809803 ME: Version: 14.0.39.1367
1472 17:50:15.816071 BS: BS_DEV_ENABLE times (ms): entry 0 run 17 exit 9
1473 17:50:15.819324 Initializing devices...
1474 17:50:15.819768 Root Device init ...
1475 17:50:15.826016 Chrome EC: Set SMI mask to 0x0000000000000000
1476 17:50:15.829399 Chrome EC: clear events_b mask to 0x0000000000000000
1477 17:50:15.836221 Chrome EC: Set S5 LAZY WAKE mask to 0x0000000000000006
1478 17:50:15.842248 Chrome EC: Set S3 LAZY WAKE mask to 0x0000000014001006
1479 17:50:15.849390 Chrome EC: Set S0iX LAZY WAKE mask to 0x0000000014081006
1480 17:50:15.852671 Chrome EC: Set WAKE mask to 0x0000000000000000
1481 17:50:15.855526 Root Device init finished in 35207 usecs
1482 17:50:15.859674 CPU_CLUSTER: 0 init ...
1483 17:50:15.865779 CPU_CLUSTER: 0 init finished in 2446 usecs
1484 17:50:15.870613 PCI: 00:00.0 init ...
1485 17:50:15.874135 CPU TDP: 15 Watts
1486 17:50:15.877323 CPU PL2 = 64 Watts
1487 17:50:15.880347 PCI: 00:00.0 init finished in 7082 usecs
1488 17:50:15.883463 PCI: 00:02.0 init ...
1489 17:50:15.886893 PCI: 00:02.0 init finished in 2252 usecs
1490 17:50:15.890217 PCI: 00:08.0 init ...
1491 17:50:15.893451 PCI: 00:08.0 init finished in 2252 usecs
1492 17:50:15.896695 PCI: 00:12.0 init ...
1493 17:50:15.900059 PCI: 00:12.0 init finished in 2252 usecs
1494 17:50:15.903699 PCI: 00:14.0 init ...
1495 17:50:15.906801 PCI: 00:14.0 init finished in 2253 usecs
1496 17:50:15.910203 PCI: 00:14.2 init ...
1497 17:50:15.913044 PCI: 00:14.2 init finished in 2254 usecs
1498 17:50:15.916487 PCI: 00:14.3 init ...
1499 17:50:15.919752 PCI: 00:14.3 init finished in 2271 usecs
1500 17:50:15.923188 PCI: 00:15.0 init ...
1501 17:50:15.926563 DW I2C bus 0 at 0xd121f000 (400 KHz)
1502 17:50:15.929786 PCI: 00:15.0 init finished in 5979 usecs
1503 17:50:15.933315 PCI: 00:15.1 init ...
1504 17:50:15.936619 DW I2C bus 1 at 0xd1220000 (400 KHz)
1505 17:50:15.943431 PCI: 00:15.1 init finished in 5977 usecs
1506 17:50:15.943897 PCI: 00:16.0 init ...
1507 17:50:15.949679 PCI: 00:16.0 init finished in 2244 usecs
1508 17:50:15.950097 PCI: 00:19.0 init ...
1509 17:50:15.956317 DW I2C bus 4 at 0xd1222000 (400 KHz)
1510 17:50:15.959572 PCI: 00:19.0 init finished in 5979 usecs
1511 17:50:15.962752 PCI: 00:1d.0 init ...
1512 17:50:15.966493 Initializing PCH PCIe bridge.
1513 17:50:15.969614 PCI: 00:1d.0 init finished in 5285 usecs
1514 17:50:15.972656 PCI: 00:1f.0 init ...
1515 17:50:15.976400 IOAPIC: Initializing IOAPIC at 0xfec00000
1516 17:50:15.982506 IOAPIC: Bootstrap Processor Local APIC = 0x00
1517 17:50:15.982924 IOAPIC: ID = 0x02
1518 17:50:15.986324 IOAPIC: Dumping registers
1519 17:50:15.989173 reg 0x0000: 0x02000000
1520 17:50:15.992945 reg 0x0001: 0x00770020
1521 17:50:15.993358 reg 0x0002: 0x00000000
1522 17:50:15.999354 PCI: 00:1f.0 init finished in 23536 usecs
1523 17:50:16.002929 PCI: 00:1f.4 init ...
1524 17:50:16.005870 PCI: 00:1f.4 init finished in 2262 usecs
1525 17:50:16.016245 PCI: 01:00.0 init ...
1526 17:50:16.019980 PCI: 01:00.0 init finished in 2254 usecs
1527 17:50:16.024142 PNP: 0c09.0 init ...
1528 17:50:16.027546 Google Chrome EC uptime: 11.085 seconds
1529 17:50:16.034290 Google Chrome AP resets since EC boot: 0
1530 17:50:16.037625 Google Chrome most recent AP reset causes:
1531 17:50:16.043940 Google Chrome EC reset flags at last EC boot: reset-pin
1532 17:50:16.047344 PNP: 0c09.0 init finished in 20612 usecs
1533 17:50:16.050133 Devices initialized
1534 17:50:16.053573 Show all devs... After init.
1535 17:50:16.053983 Root Device: enabled 1
1536 17:50:16.057012 CPU_CLUSTER: 0: enabled 1
1537 17:50:16.060500 DOMAIN: 0000: enabled 1
1538 17:50:16.061074 APIC: 00: enabled 1
1539 17:50:16.063561 PCI: 00:00.0: enabled 1
1540 17:50:16.067113 PCI: 00:02.0: enabled 1
1541 17:50:16.070550 PCI: 00:04.0: enabled 0
1542 17:50:16.070978 PCI: 00:05.0: enabled 0
1543 17:50:16.073346 PCI: 00:12.0: enabled 1
1544 17:50:16.076640 PCI: 00:12.5: enabled 0
1545 17:50:16.080193 PCI: 00:12.6: enabled 0
1546 17:50:16.080606 PCI: 00:14.0: enabled 1
1547 17:50:16.083634 PCI: 00:14.1: enabled 0
1548 17:50:16.086848 PCI: 00:14.3: enabled 1
1549 17:50:16.087262 PCI: 00:14.5: enabled 0
1550 17:50:16.090004 PCI: 00:15.0: enabled 1
1551 17:50:16.093531 PCI: 00:15.1: enabled 1
1552 17:50:16.097091 PCI: 00:15.2: enabled 0
1553 17:50:16.097508 PCI: 00:15.3: enabled 0
1554 17:50:16.099748 PCI: 00:16.0: enabled 1
1555 17:50:16.103094 PCI: 00:16.1: enabled 0
1556 17:50:16.106384 PCI: 00:16.2: enabled 0
1557 17:50:16.106795 PCI: 00:16.3: enabled 0
1558 17:50:16.109726 PCI: 00:16.4: enabled 0
1559 17:50:16.113061 PCI: 00:16.5: enabled 0
1560 17:50:16.116501 PCI: 00:17.0: enabled 1
1561 17:50:16.116938 PCI: 00:19.0: enabled 1
1562 17:50:16.119728 PCI: 00:19.1: enabled 0
1563 17:50:16.123545 PCI: 00:19.2: enabled 0
1564 17:50:16.126683 PCI: 00:1a.0: enabled 0
1565 17:50:16.127088 PCI: 00:1c.0: enabled 0
1566 17:50:16.129738 PCI: 00:1c.1: enabled 0
1567 17:50:16.133134 PCI: 00:1c.2: enabled 0
1568 17:50:16.133636 PCI: 00:1c.3: enabled 0
1569 17:50:16.136409 PCI: 00:1c.4: enabled 0
1570 17:50:16.139721 PCI: 00:1c.5: enabled 0
1571 17:50:16.142990 PCI: 00:1c.6: enabled 0
1572 17:50:16.143394 PCI: 00:1c.7: enabled 0
1573 17:50:16.146510 PCI: 00:1d.0: enabled 1
1574 17:50:16.149823 PCI: 00:1d.1: enabled 0
1575 17:50:16.152630 PCI: 00:1d.2: enabled 0
1576 17:50:16.153059 PCI: 00:1d.3: enabled 0
1577 17:50:16.156272 PCI: 00:1d.4: enabled 0
1578 17:50:16.159553 PCI: 00:1d.5: enabled 0
1579 17:50:16.162892 PCI: 00:1e.0: enabled 1
1580 17:50:16.163406 PCI: 00:1e.1: enabled 0
1581 17:50:16.166212 PCI: 00:1e.2: enabled 1
1582 17:50:16.169507 PCI: 00:1e.3: enabled 1
1583 17:50:16.169917 PCI: 00:1f.0: enabled 1
1584 17:50:16.173029 PCI: 00:1f.1: enabled 0
1585 17:50:16.175758 PCI: 00:1f.2: enabled 0
1586 17:50:16.179157 PCI: 00:1f.3: enabled 1
1587 17:50:16.179565 PCI: 00:1f.4: enabled 1
1588 17:50:16.182553 PCI: 00:1f.5: enabled 1
1589 17:50:16.185846 PCI: 00:1f.6: enabled 0
1590 17:50:16.189220 USB0 port 0: enabled 1
1591 17:50:16.189729 I2C: 01:15: enabled 1
1592 17:50:16.192842 I2C: 02:5d: enabled 1
1593 17:50:16.195826 GENERIC: 0.0: enabled 1
1594 17:50:16.196407 I2C: 03:1a: enabled 1
1595 17:50:16.199429 I2C: 03:38: enabled 1
1596 17:50:16.202485 I2C: 03:39: enabled 1
1597 17:50:16.202895 I2C: 03:3a: enabled 1
1598 17:50:16.206142 I2C: 03:3b: enabled 1
1599 17:50:16.209502 PCI: 00:00.0: enabled 1
1600 17:50:16.209929 SPI: 00: enabled 1
1601 17:50:16.212180 SPI: 01: enabled 1
1602 17:50:16.215497 PNP: 0c09.0: enabled 1
1603 17:50:16.216020 USB2 port 0: enabled 1
1604 17:50:16.219374 USB2 port 1: enabled 1
1605 17:50:16.222067 USB2 port 2: enabled 0
1606 17:50:16.225638 USB2 port 3: enabled 0
1607 17:50:16.226182 USB2 port 5: enabled 0
1608 17:50:16.228888 USB2 port 6: enabled 1
1609 17:50:16.232272 USB2 port 9: enabled 1
1610 17:50:16.232680 USB3 port 0: enabled 1
1611 17:50:16.235576 USB3 port 1: enabled 1
1612 17:50:16.239196 USB3 port 2: enabled 1
1613 17:50:16.239772 USB3 port 3: enabled 1
1614 17:50:16.242178 USB3 port 4: enabled 0
1615 17:50:16.245853 APIC: 03: enabled 1
1616 17:50:16.246256 APIC: 06: enabled 1
1617 17:50:16.248892 APIC: 01: enabled 1
1618 17:50:16.252545 APIC: 02: enabled 1
1619 17:50:16.252953 APIC: 07: enabled 1
1620 17:50:16.255777 APIC: 04: enabled 1
1621 17:50:16.256195 APIC: 05: enabled 1
1622 17:50:16.259185 PCI: 00:08.0: enabled 1
1623 17:50:16.261906 PCI: 00:14.2: enabled 1
1624 17:50:16.265151 PCI: 01:00.0: enabled 1
1625 17:50:16.269261 Disabling ACPI via APMC:
1626 17:50:16.269675 done.
1627 17:50:16.275974 FMAP: area RW_ELOG found @ af0000 (16384 bytes)
1628 17:50:16.279364 ELOG: NV offset 0xaf0000 size 0x4000
1629 17:50:16.285715 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
1630 17:50:16.292706 ELOG: Event(17) added with size 13 at 2023-10-09 17:48:44 UTC
1631 17:50:16.299553 POST: Unexpected post code in previous boot: 0x73
1632 17:50:16.305735 ELOG: Event(A3) added with size 11 at 2023-10-09 17:48:44 UTC
1633 17:50:16.312178 ELOG: Event(A6) added with size 13 at 2023-10-09 17:48:44 UTC
1634 17:50:16.319083 ELOG: Event(92) added with size 9 at 2023-10-09 17:48:44 UTC
1635 17:50:16.322301 ELOG: Event(93) added with size 9 at 2023-10-09 17:48:44 UTC
1636 17:50:16.329040 ELOG: Event(9A) added with size 9 at 2023-10-09 17:48:44 UTC
1637 17:50:16.335576 ELOG: Event(9E) added with size 10 at 2023-10-09 17:48:44 UTC
1638 17:50:16.341799 ELOG: Event(9F) added with size 14 at 2023-10-09 17:48:44 UTC
1639 17:50:16.348554 BS: BS_DEV_INIT times (ms): entry 0 run 28 exit 6
1640 17:50:16.355038 ELOG: Event(A1) added with size 10 at 2023-10-09 17:48:44 UTC
1641 17:50:16.361977 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
1642 17:50:16.368615 ELOG: Event(A0) added with size 9 at 2023-10-09 17:48:44 UTC
1643 17:50:16.371513 elog_add_boot_reason: Logged dev mode boot
1644 17:50:16.374941 Finalize devices...
1645 17:50:16.378142 PCI: 00:17.0 final
1646 17:50:16.378552 Devices finalized
1647 17:50:16.385167 FMAP: area RW_NVRAM found @ afa000 (24576 bytes)
1648 17:50:16.387766 BS: BS_POST_DEVICE times (ms): entry 1 run 0 exit 0
1649 17:50:16.394621 ME: HFSTS1 : 0x90000245
1650 17:50:16.398165 ME: HFSTS2 : 0x3B850126
1651 17:50:16.400867 ME: HFSTS3 : 0x00000020
1652 17:50:16.404456 ME: HFSTS4 : 0x00004800
1653 17:50:16.411039 ME: HFSTS5 : 0x00000000
1654 17:50:16.414203 ME: HFSTS6 : 0x40400006
1655 17:50:16.418113 ME: Manufacturing Mode : NO
1656 17:50:16.421273 ME: FW Partition Table : OK
1657 17:50:16.424209 ME: Bringup Loader Failure : NO
1658 17:50:16.427966 ME: Firmware Init Complete : YES
1659 17:50:16.430949 ME: Boot Options Present : NO
1660 17:50:16.434079 ME: Update In Progress : NO
1661 17:50:16.437567 ME: D0i3 Support : YES
1662 17:50:16.441013 ME: Low Power State Enabled : NO
1663 17:50:16.444389 ME: CPU Replaced : NO
1664 17:50:16.447118 ME: CPU Replacement Valid : YES
1665 17:50:16.450619 ME: Current Working State : 5
1666 17:50:16.453723 ME: Current Operation State : 1
1667 17:50:16.457202 ME: Current Operation Mode : 0
1668 17:50:16.460457 ME: Error Code : 0
1669 17:50:16.463794 ME: CPU Debug Disabled : YES
1670 17:50:16.467328 ME: TXT Support : NO
1671 17:50:16.473857 BS: BS_OS_RESUME_CHECK times (ms): entry 0 run 0 exit 0
1672 17:50:16.476969 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1673 17:50:16.480666 CBFS @ c08000 size 3f8000
1674 17:50:16.486804 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1675 17:50:16.489946 CBFS: Locating 'fallback/dsdt.aml'
1676 17:50:16.493768 CBFS: Found @ offset 10bb80 size 3fa5
1677 17:50:16.500412 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1678 17:50:16.500853 CBFS @ c08000 size 3f8000
1679 17:50:16.506545 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1680 17:50:16.509817 CBFS: Locating 'fallback/slic'
1681 17:50:16.513892 CBFS: 'fallback/slic' not found.
1682 17:50:16.520670 ACPI: Writing ACPI tables at 99b3e000.
1683 17:50:16.521086 ACPI: * FACS
1684 17:50:16.524041 ACPI: * DSDT
1685 17:50:16.527270 Ramoops buffer: 0x100000@0x99a3d000.
1686 17:50:16.530587 FMAP: area RO_VPD found @ c00000 (16384 bytes)
1687 17:50:16.537511 FMAP: area RW_VPD found @ af8000 (8192 bytes)
1688 17:50:16.540648 Google Chrome EC: version:
1689 17:50:16.543838 ro: helios_v2.0.2659-56403530b
1690 17:50:16.547013 rw: helios_v2.0.2849-c41de27e7d
1691 17:50:16.547574 running image: 1
1692 17:50:16.551319 ACPI: * FADT
1693 17:50:16.551787 SCI is IRQ9
1694 17:50:16.558232 ACPI: added table 1/32, length now 40
1695 17:50:16.558644 ACPI: * SSDT
1696 17:50:16.561394 Found 1 CPU(s) with 8 core(s) each.
1697 17:50:16.564685 Error: Could not locate 'wifi_sar' in VPD.
1698 17:50:16.571426 Checking CBFS for default SAR values
1699 17:50:16.574299 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1700 17:50:16.577613 CBFS @ c08000 size 3f8000
1701 17:50:16.584735 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1702 17:50:16.587969 CBFS: Locating 'wifi_sar_defaults.hex'
1703 17:50:16.590721 CBFS: Found @ offset 5fac0 size 77
1704 17:50:16.593986 \_SB.PCI0.WFA3: Intel WiFi PCI: 00:14.3
1705 17:50:16.601168 \_SB.PCI0.I2C0.D015: ELAN Touchpad at I2C: 01:15
1706 17:50:16.604408 \_SB.PCI0.I2C1.H05D: Goodix Touchscreen at I2C: 02:5d
1707 17:50:16.610796 \_SB.PCI0.I2C4.RT58: Realtek RT5682 at I2C: 03:1a
1708 17:50:16.614281 failed to find key in VPD: dsm_calib_r0_0
1709 17:50:16.624026 Failed to get dsm_calib parameters from VPD with key dsm_calib_r0_0 and dsm_calib_temp_0
1710 17:50:16.627461 \_SB.PCI0.I2C4.RTWL: Realtek RT1011 Codec address 038h
1711 17:50:16.630856 failed to find key in VPD: dsm_calib_r0_1
1712 17:50:16.640748 Failed to get dsm_calib parameters from VPD with key dsm_calib_r0_1 and dsm_calib_temp_0
1713 17:50:16.647186 \_SB.PCI0.I2C4.RTWR: Realtek RT1011 Codec address 039h
1714 17:50:16.650442 failed to find key in VPD: dsm_calib_r0_2
1715 17:50:16.660370 Failed to get dsm_calib parameters from VPD with key dsm_calib_r0_2 and dsm_calib_temp_0
1716 17:50:16.663952 \_SB.PCI0.I2C4.RTTL: Realtek RT1011 Codec address 03ah
1717 17:50:16.670454 failed to find key in VPD: dsm_calib_r0_3
1718 17:50:16.677400 Failed to get dsm_calib parameters from VPD with key dsm_calib_r0_3 and dsm_calib_temp_0
1719 17:50:16.683355 \_SB.PCI0.I2C4.RTTR: Realtek RT1011 Codec address 03bh
1720 17:50:16.686660 \_SB.PCI0.SPI0.S001: SPI Device at SPI: 00
1721 17:50:16.690059 \_SB.PCI0.SPI1.CRFP: SPI Device at SPI: 01
1722 17:50:16.694582 EC returned error result code 1
1723 17:50:16.698228 EC returned error result code 1
1724 17:50:16.701722 EC returned error result code 1
1725 17:50:16.708436 PS2K: Bad resp from EC. Vivaldi disabled!
1726 17:50:16.711762 \_SB.PCI0.XHCI.RHUB.HS01: Left Type-C Port at USB2 port 0
1727 17:50:16.718073 \_SB.PCI0.XHCI.RHUB.HS02: Right Type-C Port 1 at USB2 port 1
1728 17:50:16.724548 \_SB.PCI0.XHCI.RHUB.HS07: Camera at USB2 port 6
1729 17:50:16.728071 \_SB.PCI0.XHCI.RHUB.HS10: Bluetooth at USB2 port 9
1730 17:50:16.734985 \_SB.PCI0.XHCI.RHUB.SS01: Left Type-C Port at USB3 port 0
1731 17:50:16.740970 \_SB.PCI0.XHCI.RHUB.SS02: Right Type-C Port 1 at USB3 port 1
1732 17:50:16.747635 \_SB.PCI0.XHCI.RHUB.SS03: Left Type-A Port at USB3 port 2
1733 17:50:16.750849 \_SB.PCI0.XHCI.RHUB.SS04: Right Type-A Port 1 at USB3 port 3
1734 17:50:16.758038 ACPI: added table 2/32, length now 44
1735 17:50:16.758307 ACPI: * MCFG
1736 17:50:16.760639 ACPI: added table 3/32, length now 48
1737 17:50:16.764133 ACPI: * TPM2
1738 17:50:16.767580 TPM2 log created at 99a2d000
1739 17:50:16.770953 ACPI: added table 4/32, length now 52
1740 17:50:16.771224 ACPI: * MADT
1741 17:50:16.774293 SCI is IRQ9
1742 17:50:16.777273 ACPI: added table 5/32, length now 56
1743 17:50:16.777684 current = 99b43ac0
1744 17:50:16.780961 ACPI: * DMAR
1745 17:50:16.784187 ACPI: added table 6/32, length now 60
1746 17:50:16.787557 ACPI: * IGD OpRegion
1747 17:50:16.788132 GMA: Found VBT in CBFS
1748 17:50:16.790906 GMA: Found valid VBT in CBFS
1749 17:50:16.794405 ACPI: added table 7/32, length now 64
1750 17:50:16.797754 ACPI: * HPET
1751 17:50:16.801099 ACPI: added table 8/32, length now 68
1752 17:50:16.804105 ACPI: done.
1753 17:50:16.804519 ACPI tables: 31744 bytes.
1754 17:50:16.808011 smbios_write_tables: 99a2c000
1755 17:50:16.811353 EC returned error result code 3
1756 17:50:16.814089 Couldn't obtain OEM name from CBI
1757 17:50:16.817650 Create SMBIOS type 17
1758 17:50:16.820781 PCI: 00:00.0 (Intel Cannonlake)
1759 17:50:16.824403 PCI: 00:14.3 (Intel WiFi)
1760 17:50:16.827603 SMBIOS tables: 939 bytes.
1761 17:50:16.831131 Writing table forward entry at 0x00000500
1762 17:50:16.837813 Wrote coreboot table at: 00000500, 0x10 bytes, checksum 4628
1763 17:50:16.840583 Writing coreboot table at 0x99b62000
1764 17:50:16.847291 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1765 17:50:16.850613 1. 0000000000001000-000000000009ffff: RAM
1766 17:50:16.854205 2. 00000000000a0000-00000000000fffff: RESERVED
1767 17:50:16.860444 3. 0000000000100000-0000000099a2bfff: RAM
1768 17:50:16.866903 4. 0000000099a2c000-0000000099baffff: CONFIGURATION TABLES
1769 17:50:16.870440 5. 0000000099bb0000-0000000099c0afff: RAMSTAGE
1770 17:50:16.877118 6. 0000000099c0b000-0000000099ffffff: CONFIGURATION TABLES
1771 17:50:16.880712 7. 000000009a000000-000000009f7fffff: RESERVED
1772 17:50:16.887332 8. 00000000e0000000-00000000efffffff: RESERVED
1773 17:50:16.890609 9. 00000000fc000000-00000000fc000fff: RESERVED
1774 17:50:16.896952 10. 00000000fe000000-00000000fe00ffff: RESERVED
1775 17:50:16.900565 11. 00000000fed10000-00000000fed17fff: RESERVED
1776 17:50:16.903595 12. 00000000fed80000-00000000fed83fff: RESERVED
1777 17:50:16.910430 13. 00000000fed90000-00000000fed91fff: RESERVED
1778 17:50:16.913899 14. 00000000feda0000-00000000feda1fff: RESERVED
1779 17:50:16.920075 15. 0000000100000000-000000045e7fffff: RAM
1780 17:50:16.923593 Graphics framebuffer located at 0xc0000000
1781 17:50:16.927029 Passing 5 GPIOs to payload:
1782 17:50:16.930518 NAME | PORT | POLARITY | VALUE
1783 17:50:16.936624 write protect | undefined | high | low
1784 17:50:16.943726 lid | undefined | high | high
1785 17:50:16.946806 power | undefined | high | low
1786 17:50:16.953597 oprom | undefined | high | low
1787 17:50:16.957123 EC in RW | 0x000000cb | high | low
1788 17:50:16.960095 Board ID: 4
1789 17:50:16.963449 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1790 17:50:16.966773 CBFS @ c08000 size 3f8000
1791 17:50:16.973401 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1792 17:50:16.980003 Wrote coreboot table at: 99b62000, 0x5bc bytes, checksum 4d87
1793 17:50:16.980424 coreboot table: 1492 bytes.
1794 17:50:16.983491 IMD ROOT 0. 99fff000 00001000
1795 17:50:16.986343 IMD SMALL 1. 99ffe000 00001000
1796 17:50:16.989721 FSP MEMORY 2. 99c4e000 003b0000
1797 17:50:16.993108 CONSOLE 3. 99c2e000 00020000
1798 17:50:16.996395 FMAP 4. 99c2d000 0000054e
1799 17:50:16.999734 TIME STAMP 5. 99c2c000 00000910
1800 17:50:17.003229 VBOOT WORK 6. 99c18000 00014000
1801 17:50:17.006659 MRC DATA 7. 99c16000 00001958
1802 17:50:17.010097 ROMSTG STCK 8. 99c15000 00001000
1803 17:50:17.013307 AFTER CAR 9. 99c0b000 0000a000
1804 17:50:17.016378 RAMSTAGE 10. 99baf000 0005c000
1805 17:50:17.019312 REFCODE 11. 99b7a000 00035000
1806 17:50:17.023001 SMM BACKUP 12. 99b6a000 00010000
1807 17:50:17.026149 COREBOOT 13. 99b62000 00008000
1808 17:50:17.029626 ACPI 14. 99b3e000 00024000
1809 17:50:17.032620 ACPI GNVS 15. 99b3d000 00001000
1810 17:50:17.036137 RAMOOPS 16. 99a3d000 00100000
1811 17:50:17.039715 TPM2 TCGLOG17. 99a2d000 00010000
1812 17:50:17.042994 SMBIOS 18. 99a2c000 00000800
1813 17:50:17.046338 IMD small region:
1814 17:50:17.049616 IMD ROOT 0. 99ffec00 00000400
1815 17:50:17.053049 FSP RUNTIME 1. 99ffebe0 00000004
1816 17:50:17.056117 EC HOSTEVENT 2. 99ffebc0 00000008
1817 17:50:17.059175 POWER STATE 3. 99ffeb80 00000040
1818 17:50:17.062557 ROMSTAGE 4. 99ffeb60 00000004
1819 17:50:17.065772 MEM INFO 5. 99ffe9a0 000001b9
1820 17:50:17.072250 VPD 6. 99ffe920 0000006c
1821 17:50:17.072480 MTRR: Physical address space:
1822 17:50:17.078995 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
1823 17:50:17.085432 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
1824 17:50:17.092382 0x00000000000c0000 - 0x000000009b000000 size 0x9af40000 type 6
1825 17:50:17.098624 0x000000009b000000 - 0x00000000c0000000 size 0x25000000 type 0
1826 17:50:17.105229 0x00000000c0000000 - 0x00000000d0000000 size 0x10000000 type 1
1827 17:50:17.112209 0x00000000d0000000 - 0x0000000100000000 size 0x30000000 type 0
1828 17:50:17.118609 0x0000000100000000 - 0x000000045e800000 size 0x35e800000 type 6
1829 17:50:17.122259 MTRR: Fixed MSR 0x250 0x0606060606060606
1830 17:50:17.125667 MTRR: Fixed MSR 0x258 0x0606060606060606
1831 17:50:17.128959 MTRR: Fixed MSR 0x259 0x0000000000000000
1832 17:50:17.134919 MTRR: Fixed MSR 0x268 0x0606060606060606
1833 17:50:17.138092 MTRR: Fixed MSR 0x269 0x0606060606060606
1834 17:50:17.141814 MTRR: Fixed MSR 0x26a 0x0606060606060606
1835 17:50:17.145313 MTRR: Fixed MSR 0x26b 0x0606060606060606
1836 17:50:17.151632 MTRR: Fixed MSR 0x26c 0x0606060606060606
1837 17:50:17.155312 MTRR: Fixed MSR 0x26d 0x0606060606060606
1838 17:50:17.158801 MTRR: Fixed MSR 0x26e 0x0606060606060606
1839 17:50:17.162107 MTRR: Fixed MSR 0x26f 0x0606060606060606
1840 17:50:17.165534 call enable_fixed_mtrr()
1841 17:50:17.168465 CPU physical address size: 39 bits
1842 17:50:17.175250 MTRR: default type WB/UC MTRR counts: 6/8.
1843 17:50:17.178354 MTRR: WB selected as default type.
1844 17:50:17.185024 MTRR: 0 base 0x000000009b000000 mask 0x0000007fff000000 type 0
1845 17:50:17.188437 MTRR: 1 base 0x000000009c000000 mask 0x0000007ffc000000 type 0
1846 17:50:17.195018 MTRR: 2 base 0x00000000a0000000 mask 0x0000007fe0000000 type 0
1847 17:50:17.201898 MTRR: 3 base 0x00000000c0000000 mask 0x0000007ff0000000 type 1
1848 17:50:17.208543 MTRR: 4 base 0x00000000d0000000 mask 0x0000007ff0000000 type 0
1849 17:50:17.215143 MTRR: 5 base 0x00000000e0000000 mask 0x0000007fe0000000 type 0
1850 17:50:17.217961 MTRR: Fixed MSR 0x250 0x0606060606060606
1851 17:50:17.224949 MTRR: Fixed MSR 0x258 0x0606060606060606
1852 17:50:17.228043 MTRR: Fixed MSR 0x259 0x0000000000000000
1853 17:50:17.231358 MTRR: Fixed MSR 0x268 0x0606060606060606
1854 17:50:17.234657 MTRR: Fixed MSR 0x269 0x0606060606060606
1855 17:50:17.241488 MTRR: Fixed MSR 0x26a 0x0606060606060606
1856 17:50:17.244949 MTRR: Fixed MSR 0x26b 0x0606060606060606
1857 17:50:17.248329 MTRR: Fixed MSR 0x26c 0x0606060606060606
1858 17:50:17.251632 MTRR: Fixed MSR 0x26d 0x0606060606060606
1859 17:50:17.258022 MTRR: Fixed MSR 0x26e 0x0606060606060606
1860 17:50:17.261370 MTRR: Fixed MSR 0x26f 0x0606060606060606
1861 17:50:17.261781
1862 17:50:17.262128 MTRR check
1863 17:50:17.264528 Fixed MTRRs : Enabled
1864 17:50:17.267888 Variable MTRRs: Enabled
1865 17:50:17.268296
1866 17:50:17.271437 call enable_fixed_mtrr()
1867 17:50:17.274731 BS: BS_WRITE_TABLES times (ms): entry 0 run 9 exit 2
1868 17:50:17.277624 CPU physical address size: 39 bits
1869 17:50:17.284601 FMAP: area COREBOOT found @ c08000 (4161536 bytes)
1870 17:50:17.287996 CBFS @ c08000 size 3f8000
1871 17:50:17.291624 CBFS: 'COREBOOT Locator' located CBFS at [c08000:1000000)
1872 17:50:17.294497 CBFS: Locating 'fallback/payload'
1873 17:50:17.301821 MTRR: Fixed MSR 0x250 0x0606060606060606
1874 17:50:17.304994 MTRR: Fixed MSR 0x250 0x0606060606060606
1875 17:50:17.307762 MTRR: Fixed MSR 0x258 0x0606060606060606
1876 17:50:17.311238 MTRR: Fixed MSR 0x259 0x0000000000000000
1877 17:50:17.317780 MTRR: Fixed MSR 0x268 0x0606060606060606
1878 17:50:17.321558 MTRR: Fixed MSR 0x269 0x0606060606060606
1879 17:50:17.324431 MTRR: Fixed MSR 0x26a 0x0606060606060606
1880 17:50:17.327705 MTRR: Fixed MSR 0x26b 0x0606060606060606
1881 17:50:17.334617 MTRR: Fixed MSR 0x26c 0x0606060606060606
1882 17:50:17.338101 MTRR: Fixed MSR 0x26d 0x0606060606060606
1883 17:50:17.341412 MTRR: Fixed MSR 0x26e 0x0606060606060606
1884 17:50:17.344133 MTRR: Fixed MSR 0x26f 0x0606060606060606
1885 17:50:17.351171 MTRR: Fixed MSR 0x258 0x0606060606060606
1886 17:50:17.351743 call enable_fixed_mtrr()
1887 17:50:17.358037 MTRR: Fixed MSR 0x259 0x0000000000000000
1888 17:50:17.360763 MTRR: Fixed MSR 0x268 0x0606060606060606
1889 17:50:17.364200 MTRR: Fixed MSR 0x269 0x0606060606060606
1890 17:50:17.367481 MTRR: Fixed MSR 0x26a 0x0606060606060606
1891 17:50:17.373969 MTRR: Fixed MSR 0x26b 0x0606060606060606
1892 17:50:17.377575 MTRR: Fixed MSR 0x26c 0x0606060606060606
1893 17:50:17.381020 MTRR: Fixed MSR 0x26d 0x0606060606060606
1894 17:50:17.383785 MTRR: Fixed MSR 0x26e 0x0606060606060606
1895 17:50:17.390317 MTRR: Fixed MSR 0x26f 0x0606060606060606
1896 17:50:17.394138 CPU physical address size: 39 bits
1897 17:50:17.397189 call enable_fixed_mtrr()
1898 17:50:17.400317 CBFS: Found @ offset 1c96c0 size 3f798
1899 17:50:17.404054 MTRR: Fixed MSR 0x250 0x0606060606060606
1900 17:50:17.406964 MTRR: Fixed MSR 0x250 0x0606060606060606
1901 17:50:17.410463 MTRR: Fixed MSR 0x258 0x0606060606060606
1902 17:50:17.417258 MTRR: Fixed MSR 0x259 0x0000000000000000
1903 17:50:17.420425 MTRR: Fixed MSR 0x268 0x0606060606060606
1904 17:50:17.423582 MTRR: Fixed MSR 0x269 0x0606060606060606
1905 17:50:17.427055 MTRR: Fixed MSR 0x26a 0x0606060606060606
1906 17:50:17.433758 MTRR: Fixed MSR 0x26b 0x0606060606060606
1907 17:50:17.437177 MTRR: Fixed MSR 0x26c 0x0606060606060606
1908 17:50:17.439798 MTRR: Fixed MSR 0x26d 0x0606060606060606
1909 17:50:17.443231 MTRR: Fixed MSR 0x26e 0x0606060606060606
1910 17:50:17.450157 MTRR: Fixed MSR 0x26f 0x0606060606060606
1911 17:50:17.453731 MTRR: Fixed MSR 0x258 0x0606060606060606
1912 17:50:17.457001 call enable_fixed_mtrr()
1913 17:50:17.459751 MTRR: Fixed MSR 0x259 0x0000000000000000
1914 17:50:17.463213 MTRR: Fixed MSR 0x268 0x0606060606060606
1915 17:50:17.466501 MTRR: Fixed MSR 0x269 0x0606060606060606
1916 17:50:17.473677 MTRR: Fixed MSR 0x26a 0x0606060606060606
1917 17:50:17.476653 MTRR: Fixed MSR 0x26b 0x0606060606060606
1918 17:50:17.479971 MTRR: Fixed MSR 0x26c 0x0606060606060606
1919 17:50:17.483323 MTRR: Fixed MSR 0x26d 0x0606060606060606
1920 17:50:17.489565 MTRR: Fixed MSR 0x26e 0x0606060606060606
1921 17:50:17.493066 MTRR: Fixed MSR 0x26f 0x0606060606060606
1922 17:50:17.496573 CPU physical address size: 39 bits
1923 17:50:17.499634 call enable_fixed_mtrr()
1924 17:50:17.502862 CPU physical address size: 39 bits
1925 17:50:17.506378 CPU physical address size: 39 bits
1926 17:50:17.509776 Checking segment from ROM address 0xffdd16f8
1927 17:50:17.516541 MTRR: Fixed MSR 0x250 0x0606060606060606
1928 17:50:17.519767 MTRR: Fixed MSR 0x250 0x0606060606060606
1929 17:50:17.522409 MTRR: Fixed MSR 0x258 0x0606060606060606
1930 17:50:17.526098 MTRR: Fixed MSR 0x259 0x0000000000000000
1931 17:50:17.532616 MTRR: Fixed MSR 0x268 0x0606060606060606
1932 17:50:17.536047 MTRR: Fixed MSR 0x269 0x0606060606060606
1933 17:50:17.539369 MTRR: Fixed MSR 0x26a 0x0606060606060606
1934 17:50:17.542667 MTRR: Fixed MSR 0x26b 0x0606060606060606
1935 17:50:17.546044 MTRR: Fixed MSR 0x26c 0x0606060606060606
1936 17:50:17.552226 MTRR: Fixed MSR 0x26d 0x0606060606060606
1937 17:50:17.555743 MTRR: Fixed MSR 0x26e 0x0606060606060606
1938 17:50:17.559052 MTRR: Fixed MSR 0x26f 0x0606060606060606
1939 17:50:17.566059 MTRR: Fixed MSR 0x258 0x0606060606060606
1940 17:50:17.568656 MTRR: Fixed MSR 0x259 0x0000000000000000
1941 17:50:17.572189 MTRR: Fixed MSR 0x268 0x0606060606060606
1942 17:50:17.575567 MTRR: Fixed MSR 0x269 0x0606060606060606
1943 17:50:17.582419 MTRR: Fixed MSR 0x26a 0x0606060606060606
1944 17:50:17.586004 MTRR: Fixed MSR 0x26b 0x0606060606060606
1945 17:50:17.588566 MTRR: Fixed MSR 0x26c 0x0606060606060606
1946 17:50:17.591862 MTRR: Fixed MSR 0x26d 0x0606060606060606
1947 17:50:17.595420 MTRR: Fixed MSR 0x26e 0x0606060606060606
1948 17:50:17.602173 MTRR: Fixed MSR 0x26f 0x0606060606060606
1949 17:50:17.605451 call enable_fixed_mtrr()
1950 17:50:17.605861 call enable_fixed_mtrr()
1951 17:50:17.608749 CPU physical address size: 39 bits
1952 17:50:17.614824 CPU physical address size: 39 bits
1953 17:50:17.618692 Checking segment from ROM address 0xffdd1714
1954 17:50:17.621906 Loading segment from ROM address 0xffdd16f8
1955 17:50:17.625335 code (compression=0)
1956 17:50:17.635158 New segment dstaddr 0x30000000 memsize 0x657430 srcaddr 0xffdd1730 filesize 0x3f760
1957 17:50:17.641292 Loading Segment: addr: 0x30000000 memsz: 0x0000000000657430 filesz: 0x000000000003f760
1958 17:50:17.644599 it's not compressed!
1959 17:50:17.736523 [ 0x30000000, 3003f760, 0x30657430) <- ffdd1730
1960 17:50:17.742615 Clearing Segment: addr: 0x000000003003f760 memsz: 0x0000000000617cd0
1961 17:50:17.745975 Loading segment from ROM address 0xffdd1714
1962 17:50:17.749473 Entry Point 0x30000000
1963 17:50:17.752837 Loaded segments
1964 17:50:17.758227 Finalizing chipset.
1965 17:50:17.761330 Finalizing SMM.
1966 17:50:17.765416 BS: BS_PAYLOAD_LOAD times (ms): entry 0 run 88 exit 5
1967 17:50:17.768621 mp_park_aps done after 0 msecs.
1968 17:50:17.775096 Jumping to boot code at 30000000(99b62000)
1969 17:50:17.781516 CPU0: stack: 99bf9000 - 99bfa000, lowest used address 99bf99d8, stack used: 1576 bytes
1970 17:50:17.781928
1971 17:50:17.782255
1972 17:50:17.782596
1973 17:50:17.784954 Starting depthcharge on Helios...
1974 17:50:17.785363
1975 17:50:17.786364 end: 2.2.3 depthcharge-start (duration 00:00:13) [common]
1976 17:50:17.786864 start: 2.2.4 bootloader-commands (timeout 00:04:42) [common]
1977 17:50:17.787266 Setting prompt string to ['hatch:']
1978 17:50:17.787776 bootloader-commands: Wait for prompt ['hatch:'] (timeout 00:04:42)
1979 17:50:17.794792 WARNING: can't convert coreboot GPIOs, 'lid' won't be resampled at runtime!
1980 17:50:17.795317
1981 17:50:17.801225 WARNING: can't convert coreboot GPIOs, 'power' won't be resampled at runtime!
1982 17:50:17.801640
1983 17:50:17.808049 board_setup: Info: eMMC controller not present; skipping
1984 17:50:17.808460
1985 17:50:17.811565 New NVMe Controller 0x30053ac0 @ 00:1d:00
1986 17:50:17.812029
1987 17:50:17.817771 board_setup: Info: SDHCI controller not present; skipping
1988 17:50:17.818206
1989 17:50:17.824284 vboot_create_vbsd: creating legacy VbSharedDataHeader structure
1990 17:50:17.824711
1991 17:50:17.825106 Wipe memory regions:
1992 17:50:17.825437
1993 17:50:17.827603 [0x00000000001000, 0x000000000a0000)
1994 17:50:17.828056
1995 17:50:17.831493 [0x00000000100000, 0x00000030000000)
1996 17:50:17.897156
1997 17:50:17.900392 [0x00000030657430, 0x00000099a2c000)
1998 17:50:18.038373
1999 17:50:18.041694 [0x00000100000000, 0x0000045e800000)
2000 17:50:19.424013
2001 17:50:19.424517 R8152: Initializing
2002 17:50:19.424852
2003 17:50:19.427339 Version 9 (ocp_data = 6010)
2004 17:50:19.431411
2005 17:50:19.431850 R8152: Done initializing
2006 17:50:19.432180
2007 17:50:19.434648 Adding net device
2008 17:50:19.917864
2009 17:50:19.918394 R8152: Initializing
2010 17:50:19.918817
2011 17:50:19.921291 Version 6 (ocp_data = 5c30)
2012 17:50:19.921716
2013 17:50:19.924310 R8152: Done initializing
2014 17:50:19.924718
2015 17:50:19.927516 net_add_device: Attemp to include the same device
2016 17:50:19.931312
2017 17:50:19.938421 [firmware-hatch-12672.B-collabora] Jul 21 2021 08:27:58
2018 17:50:19.938973
2019 17:50:19.939436
2020 17:50:19.940025
2021 17:50:19.940943 Setting prompt string to ['hatch:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2023 17:50:20.042154 hatch: tftpboot 192.168.201.1 11712576/tftp-deploy-uhc0u1w3/kernel/bzImage 11712576/tftp-deploy-uhc0u1w3/kernel/cmdline 11712576/tftp-deploy-uhc0u1w3/ramdisk/ramdisk.cpio.gz
2024 17:50:20.042755 Setting prompt string to ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2025 17:50:20.043349 bootloader-commands: Wait for prompt ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:40)
2026 17:50:20.048095 tftpboot 192.168.201.1 11712576/tftp-deploy-uhc0u1w3/kernel/bzImploy-uhc0u1w3/kernel/cmdline 11712576/tftp-deploy-uhc0u1w3/ramdisk/ramdisk.cpio.gz
2027 17:50:20.048531
2028 17:50:20.048883 Waiting for link
2029 17:50:20.248925
2030 17:50:20.249459 done.
2031 17:50:20.249807
2032 17:50:20.250117 MAC: 00:24:32:50:19:be
2033 17:50:20.250418
2034 17:50:20.252310 Sending DHCP discover... done.
2035 17:50:20.252761
2036 17:50:20.281490 Waiting for reply... done.
2037 17:50:20.282287
2038 17:50:20.286058 Sending DHCP request... done.
2039 17:50:20.286608
2040 17:50:20.301018 Waiting for reply... done.
2041 17:50:20.301703
2042 17:50:20.302261 My ip is 192.168.201.15
2043 17:50:20.302827
2044 17:50:20.304128 The DHCP server ip is 192.168.201.1
2045 17:50:20.307528
2046 17:50:20.310870 TFTP server IP predefined by user: 192.168.201.1
2047 17:50:20.311446
2048 17:50:20.317473 Bootfile predefined by user: 11712576/tftp-deploy-uhc0u1w3/kernel/bzImage
2049 17:50:20.318074
2050 17:50:20.320735 Sending tftp read request... done.
2051 17:50:20.321298
2052 17:50:20.330272 Waiting for the transfer...
2053 17:50:20.330692
2054 17:50:20.937976 00000000 ################################################################
2055 17:50:20.938146
2056 17:50:21.580657 00080000 ################################################################
2057 17:50:21.580793
2058 17:50:22.163287 00100000 ################################################################
2059 17:50:22.163434
2060 17:50:22.727994 00180000 ################################################################
2061 17:50:22.728141
2062 17:50:23.289834 00200000 ################################################################
2063 17:50:23.289975
2064 17:50:23.878614 00280000 ################################################################
2065 17:50:23.879116
2066 17:50:24.508795 00300000 ################################################################
2067 17:50:24.508929
2068 17:50:25.148489 00380000 ################################################################
2069 17:50:25.148636
2070 17:50:25.718329 00400000 ################################################################
2071 17:50:25.718492
2072 17:50:26.277164 00480000 ################################################################
2073 17:50:26.277316
2074 17:50:26.844400 00500000 ################################################################
2075 17:50:26.844540
2076 17:50:27.395864 00580000 ################################################################
2077 17:50:27.396076
2078 17:50:27.963910 00600000 ################################################################
2079 17:50:27.964060
2080 17:50:28.505742 00680000 ################################################################
2081 17:50:28.505906
2082 17:50:29.045904 00700000 ################################################################
2083 17:50:29.046052
2084 17:50:29.572132 00780000 ################################################################
2085 17:50:29.572281
2086 17:50:29.676687 00800000 ############# done.
2087 17:50:29.676831
2088 17:50:29.680133 The bootfile was 8490896 bytes long.
2089 17:50:29.680213
2090 17:50:29.683385 Sending tftp read request... done.
2091 17:50:29.683496
2092 17:50:29.686120 Waiting for the transfer...
2093 17:50:29.686193
2094 17:50:30.261006 00000000 ################################################################
2095 17:50:30.261152
2096 17:50:30.802017 00080000 ################################################################
2097 17:50:30.802161
2098 17:50:31.351137 00100000 ################################################################
2099 17:50:31.351307
2100 17:50:31.900836 00180000 ################################################################
2101 17:50:31.900989
2102 17:50:32.447819 00200000 ################################################################
2103 17:50:32.447969
2104 17:50:33.002337 00280000 ################################################################
2105 17:50:33.002486
2106 17:50:33.551572 00300000 ################################################################
2107 17:50:33.551758
2108 17:50:34.110605 00380000 ################################################################
2109 17:50:34.110752
2110 17:50:34.665303 00400000 ################################################################
2111 17:50:34.665449
2112 17:50:35.217115 00480000 ################################################################
2113 17:50:35.217257
2114 17:50:35.813586 00500000 ################################################################
2115 17:50:35.813741
2116 17:50:36.383210 00580000 ################################################################
2117 17:50:36.383363
2118 17:50:36.948308 00600000 ################################################################
2119 17:50:36.948457
2120 17:50:37.487754 00680000 ################################################################
2121 17:50:37.487895
2122 17:50:38.072593 00700000 ################################################################
2123 17:50:38.073126
2124 17:50:38.630376 00780000 ################################################################
2125 17:50:38.630522
2126 17:50:39.115530 00800000 ####################################################### done.
2127 17:50:39.115748
2128 17:50:39.118996 Sending tftp read request... done.
2129 17:50:39.119079
2130 17:50:39.122329 Waiting for the transfer...
2131 17:50:39.122413
2132 17:50:39.125717 00000000 # done.
2133 17:50:39.125800
2134 17:50:39.132089 Command line loaded dynamically from TFTP file: 11712576/tftp-deploy-uhc0u1w3/kernel/cmdline
2135 17:50:39.135175
2136 17:50:39.151437 The command line is: earlyprintk=uart8250,mmio32,0xfedc6000,115200n8 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
2137 17:50:39.154720
2138 17:50:39.158366 ec_init(0): CrosEC protocol v3 supported (256, 256)
2139 17:50:39.163644
2140 17:50:39.166986 Shutting down all USB controllers.
2141 17:50:39.167063
2142 17:50:39.167126 Removing current net device
2143 17:50:39.171293
2144 17:50:39.171370 Finalizing coreboot
2145 17:50:39.171434
2146 17:50:39.177420 Exiting depthcharge with code 4 at timestamp: 28756314
2147 17:50:39.177501
2148 17:50:39.177565
2149 17:50:39.177625 Starting kernel ...
2150 17:50:39.177683
2151 17:50:39.177740
2152 17:50:39.178107 end: 2.2.4 bootloader-commands (duration 00:00:21) [common]
2153 17:50:39.178220 start: 2.2.5 auto-login-action (timeout 00:04:21) [common]
2154 17:50:39.178297 Setting prompt string to ['Linux version [0-9]']
2155 17:50:39.178365 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2156 17:50:39.178433 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
2158 17:55:00.178493 end: 2.2.5 auto-login-action (duration 00:04:21) [common]
2160 17:55:00.178699 depthcharge-retry failed: 1 of 1 attempts. 'auto-login-action timed out after 261 seconds'
2162 17:55:00.178860 end: 2.2 depthcharge-retry (duration 00:05:00) [common]
2165 17:55:00.179113 end: 2 depthcharge-action (duration 00:05:00) [common]
2167 17:55:00.179362 Cleaning after the job
2168 17:55:00.179450 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11712576/tftp-deploy-uhc0u1w3/ramdisk
2169 17:55:00.180706 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11712576/tftp-deploy-uhc0u1w3/kernel
2170 17:55:00.181932 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/11712576/tftp-deploy-uhc0u1w3/modules
2171 17:55:00.182318 start: 5.1 power-off (timeout 00:00:30) [common]
2172 17:55:00.182481 Calling: 'pduclient' '--daemon=localhost' '--hostname=asus-C436FA-Flip-hatch-cbg-3' '--port=1' '--command=off'
2173 17:55:00.260461 >> Command sent successfully.
2174 17:55:00.262841 Returned 0 in 0 seconds
2175 17:55:00.363248 end: 5.1 power-off (duration 00:00:00) [common]
2177 17:55:00.363579 start: 5.2 read-feedback (timeout 00:10:00) [common]
2178 17:55:00.363883 Listened to connection for namespace 'common' for up to 1s
2180 17:55:00.364259 Listened to connection for namespace 'common' for up to 1s
2181 17:55:01.364804 Finalising connection for namespace 'common'
2182 17:55:01.364972 Disconnecting from shell: Finalise
2183 17:55:01.365049
2184 17:55:01.465383 end: 5.2 read-feedback (duration 00:00:01) [common]
2185 17:55:01.465550 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/11712576
2186 17:55:01.482268 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/11712576
2187 17:55:01.482417 JobError: Your job cannot terminate cleanly.