Boot log: asus-cx9400-volteer
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Kernel Errors: 0
- Boot result: FAIL
1 12:48:09.265398 lava-dispatcher, installed at version: 2023.01
2 12:48:09.265603 start: 0 validate
3 12:48:09.265736 Start time: 2023-03-13 12:48:09.265729+00:00 (UTC)
4 12:48:09.265892 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:48:09.266031 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230303.0%2Fx86%2Frootfs.cpio.gz exists
6 12:48:09.558021 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:48:09.558203 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-4.4.y-st%2Fv4.4-st20-939-g5ff13a6decb9%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fkernel%2FbzImage exists
8 12:48:09.850490 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:48:09.850656 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-4.4.y-st%2Fv4.4-st20-939-g5ff13a6decb9%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
10 12:48:13.052585 validate duration: 3.79
12 12:48:13.052889 start: 1 tftp-deploy (timeout 00:10:00) [common]
13 12:48:13.053064 start: 1.1 download-retry (timeout 00:10:00) [common]
14 12:48:13.053182 start: 1.1.1 http-download (timeout 00:10:00) [common]
15 12:48:13.053293 Not decompressing ramdisk as can be used compressed.
16 12:48:13.053383 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230303.0/x86/rootfs.cpio.gz
17 12:48:13.053458 saving as /var/lib/lava/dispatcher/tmp/9584839/tftp-deploy-0bzs7r4m/ramdisk/rootfs.cpio.gz
18 12:48:13.053525 total size: 8423697 (8MB)
19 12:48:13.633231 progress 0% (0MB)
20 12:48:13.635668 progress 5% (0MB)
21 12:48:13.638008 progress 10% (0MB)
22 12:48:13.640227 progress 15% (1MB)
23 12:48:13.642503 progress 20% (1MB)
24 12:48:13.644734 progress 25% (2MB)
25 12:48:13.646958 progress 30% (2MB)
26 12:48:13.648958 progress 35% (2MB)
27 12:48:13.651147 progress 40% (3MB)
28 12:48:13.653261 progress 45% (3MB)
29 12:48:13.655442 progress 50% (4MB)
30 12:48:13.657576 progress 55% (4MB)
31 12:48:13.659769 progress 60% (4MB)
32 12:48:13.661967 progress 65% (5MB)
33 12:48:13.663926 progress 70% (5MB)
34 12:48:13.666081 progress 75% (6MB)
35 12:48:13.668176 progress 80% (6MB)
36 12:48:13.670337 progress 85% (6MB)
37 12:48:13.672596 progress 90% (7MB)
38 12:48:13.674811 progress 95% (7MB)
39 12:48:13.677251 progress 100% (8MB)
40 12:48:13.677370 8MB downloaded in 0.62s (12.88MB/s)
41 12:48:13.677562 end: 1.1.1 http-download (duration 00:00:01) [common]
43 12:48:13.677880 end: 1.1 download-retry (duration 00:00:01) [common]
44 12:48:13.677991 start: 1.2 download-retry (timeout 00:09:59) [common]
45 12:48:13.678083 start: 1.2.1 http-download (timeout 00:09:59) [common]
46 12:48:13.678227 downloading http://storage.kernelci.org/cip/linux-4.4.y-st/v4.4-st20-939-g5ff13a6decb9/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/kernel/bzImage
47 12:48:13.678299 saving as /var/lib/lava/dispatcher/tmp/9584839/tftp-deploy-0bzs7r4m/kernel/bzImage
48 12:48:13.678364 total size: 7638928 (7MB)
49 12:48:13.678458 No compression specified
50 12:48:13.679360 progress 0% (0MB)
51 12:48:13.681591 progress 5% (0MB)
52 12:48:13.683861 progress 10% (0MB)
53 12:48:13.686039 progress 15% (1MB)
54 12:48:13.688266 progress 20% (1MB)
55 12:48:13.690609 progress 25% (1MB)
56 12:48:13.692718 progress 30% (2MB)
57 12:48:13.694928 progress 35% (2MB)
58 12:48:13.697146 progress 40% (2MB)
59 12:48:13.698995 progress 45% (3MB)
60 12:48:13.700998 progress 50% (3MB)
61 12:48:13.703046 progress 55% (4MB)
62 12:48:13.704853 progress 60% (4MB)
63 12:48:13.706821 progress 65% (4MB)
64 12:48:13.708766 progress 70% (5MB)
65 12:48:13.710576 progress 75% (5MB)
66 12:48:13.712527 progress 80% (5MB)
67 12:48:13.714481 progress 85% (6MB)
68 12:48:13.716279 progress 90% (6MB)
69 12:48:13.718239 progress 95% (6MB)
70 12:48:13.720206 progress 100% (7MB)
71 12:48:13.720335 7MB downloaded in 0.04s (173.60MB/s)
72 12:48:13.720495 end: 1.2.1 http-download (duration 00:00:00) [common]
74 12:48:13.720749 end: 1.2 download-retry (duration 00:00:00) [common]
75 12:48:13.720842 start: 1.3 download-retry (timeout 00:09:59) [common]
76 12:48:13.720938 start: 1.3.1 http-download (timeout 00:09:59) [common]
77 12:48:13.721058 downloading http://storage.kernelci.org/cip/linux-4.4.y-st/v4.4-st20-939-g5ff13a6decb9/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/modules.tar.xz
78 12:48:13.721130 saving as /var/lib/lava/dispatcher/tmp/9584839/tftp-deploy-0bzs7r4m/modules/modules.tar
79 12:48:13.721194 total size: 250760 (0MB)
80 12:48:13.721261 Using unxz to decompress xz
81 12:48:13.724220 progress 13% (0MB)
82 12:48:13.724612 progress 26% (0MB)
83 12:48:13.724856 progress 39% (0MB)
84 12:48:13.726177 progress 52% (0MB)
85 12:48:13.728118 progress 65% (0MB)
86 12:48:13.730060 progress 78% (0MB)
87 12:48:13.732018 progress 91% (0MB)
88 12:48:13.733854 progress 100% (0MB)
89 12:48:13.739375 0MB downloaded in 0.02s (13.16MB/s)
90 12:48:13.739666 end: 1.3.1 http-download (duration 00:00:00) [common]
92 12:48:13.739959 end: 1.3 download-retry (duration 00:00:00) [common]
93 12:48:13.740064 start: 1.4 prepare-tftp-overlay (timeout 00:09:59) [common]
94 12:48:13.740178 start: 1.4.1 extract-nfsrootfs (timeout 00:09:59) [common]
95 12:48:13.740268 end: 1.4.1 extract-nfsrootfs (duration 00:00:00) [common]
96 12:48:13.740373 start: 1.4.2 lava-overlay (timeout 00:09:59) [common]
97 12:48:13.740565 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/9584839/lava-overlay-3z5jbpws
98 12:48:13.740681 makedir: /var/lib/lava/dispatcher/tmp/9584839/lava-overlay-3z5jbpws/lava-9584839/bin
99 12:48:13.740770 makedir: /var/lib/lava/dispatcher/tmp/9584839/lava-overlay-3z5jbpws/lava-9584839/tests
100 12:48:13.740869 makedir: /var/lib/lava/dispatcher/tmp/9584839/lava-overlay-3z5jbpws/lava-9584839/results
101 12:48:13.740990 Creating /var/lib/lava/dispatcher/tmp/9584839/lava-overlay-3z5jbpws/lava-9584839/bin/lava-add-keys
102 12:48:13.741142 Creating /var/lib/lava/dispatcher/tmp/9584839/lava-overlay-3z5jbpws/lava-9584839/bin/lava-add-sources
103 12:48:13.741265 Creating /var/lib/lava/dispatcher/tmp/9584839/lava-overlay-3z5jbpws/lava-9584839/bin/lava-background-process-start
104 12:48:13.741399 Creating /var/lib/lava/dispatcher/tmp/9584839/lava-overlay-3z5jbpws/lava-9584839/bin/lava-background-process-stop
105 12:48:13.741516 Creating /var/lib/lava/dispatcher/tmp/9584839/lava-overlay-3z5jbpws/lava-9584839/bin/lava-common-functions
106 12:48:13.741645 Creating /var/lib/lava/dispatcher/tmp/9584839/lava-overlay-3z5jbpws/lava-9584839/bin/lava-echo-ipv4
107 12:48:13.741775 Creating /var/lib/lava/dispatcher/tmp/9584839/lava-overlay-3z5jbpws/lava-9584839/bin/lava-install-packages
108 12:48:13.741909 Creating /var/lib/lava/dispatcher/tmp/9584839/lava-overlay-3z5jbpws/lava-9584839/bin/lava-installed-packages
109 12:48:13.742023 Creating /var/lib/lava/dispatcher/tmp/9584839/lava-overlay-3z5jbpws/lava-9584839/bin/lava-os-build
110 12:48:13.742154 Creating /var/lib/lava/dispatcher/tmp/9584839/lava-overlay-3z5jbpws/lava-9584839/bin/lava-probe-channel
111 12:48:13.742269 Creating /var/lib/lava/dispatcher/tmp/9584839/lava-overlay-3z5jbpws/lava-9584839/bin/lava-probe-ip
112 12:48:13.742398 Creating /var/lib/lava/dispatcher/tmp/9584839/lava-overlay-3z5jbpws/lava-9584839/bin/lava-target-ip
113 12:48:13.742512 Creating /var/lib/lava/dispatcher/tmp/9584839/lava-overlay-3z5jbpws/lava-9584839/bin/lava-target-mac
114 12:48:13.742638 Creating /var/lib/lava/dispatcher/tmp/9584839/lava-overlay-3z5jbpws/lava-9584839/bin/lava-target-storage
115 12:48:13.742758 Creating /var/lib/lava/dispatcher/tmp/9584839/lava-overlay-3z5jbpws/lava-9584839/bin/lava-test-case
116 12:48:13.742870 Creating /var/lib/lava/dispatcher/tmp/9584839/lava-overlay-3z5jbpws/lava-9584839/bin/lava-test-event
117 12:48:13.742997 Creating /var/lib/lava/dispatcher/tmp/9584839/lava-overlay-3z5jbpws/lava-9584839/bin/lava-test-feedback
118 12:48:13.743114 Creating /var/lib/lava/dispatcher/tmp/9584839/lava-overlay-3z5jbpws/lava-9584839/bin/lava-test-raise
119 12:48:13.743262 Creating /var/lib/lava/dispatcher/tmp/9584839/lava-overlay-3z5jbpws/lava-9584839/bin/lava-test-reference
120 12:48:13.743377 Creating /var/lib/lava/dispatcher/tmp/9584839/lava-overlay-3z5jbpws/lava-9584839/bin/lava-test-runner
121 12:48:13.743504 Creating /var/lib/lava/dispatcher/tmp/9584839/lava-overlay-3z5jbpws/lava-9584839/bin/lava-test-set
122 12:48:13.743619 Creating /var/lib/lava/dispatcher/tmp/9584839/lava-overlay-3z5jbpws/lava-9584839/bin/lava-test-shell
123 12:48:13.743746 Updating /var/lib/lava/dispatcher/tmp/9584839/lava-overlay-3z5jbpws/lava-9584839/bin/lava-install-packages (oe)
124 12:48:13.743866 Updating /var/lib/lava/dispatcher/tmp/9584839/lava-overlay-3z5jbpws/lava-9584839/bin/lava-installed-packages (oe)
125 12:48:13.743980 Creating /var/lib/lava/dispatcher/tmp/9584839/lava-overlay-3z5jbpws/lava-9584839/environment
126 12:48:13.744082 LAVA metadata
127 12:48:13.744158 - LAVA_JOB_ID=9584839
128 12:48:13.744243 - LAVA_DISPATCHER_IP=192.168.201.1
129 12:48:13.744352 start: 1.4.2.1 lava-vland-overlay (timeout 00:09:59) [common]
130 12:48:13.744422 skipped lava-vland-overlay
131 12:48:13.744519 end: 1.4.2.1 lava-vland-overlay (duration 00:00:00) [common]
132 12:48:13.744608 start: 1.4.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
133 12:48:13.744675 skipped lava-multinode-overlay
134 12:48:13.744753 end: 1.4.2.2 lava-multinode-overlay (duration 00:00:00) [common]
135 12:48:13.744864 start: 1.4.2.3 test-definition (timeout 00:09:59) [common]
136 12:48:13.744943 Loading test definitions
137 12:48:13.745067 start: 1.4.2.3.1 inline-repo-action (timeout 00:09:59) [common]
138 12:48:13.745156 Using /lava-9584839 at stage 0
139 12:48:13.745447 uuid=9584839_1.4.2.3.1 testdef=None
140 12:48:13.745544 end: 1.4.2.3.1 inline-repo-action (duration 00:00:00) [common]
141 12:48:13.745652 start: 1.4.2.3.2 test-overlay (timeout 00:09:59) [common]
142 12:48:13.746205 end: 1.4.2.3.2 test-overlay (duration 00:00:00) [common]
144 12:48:13.746462 start: 1.4.2.3.3 test-install-overlay (timeout 00:09:59) [common]
145 12:48:13.747084 end: 1.4.2.3.3 test-install-overlay (duration 00:00:00) [common]
147 12:48:13.747335 start: 1.4.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
148 12:48:13.747914 runner path: /var/lib/lava/dispatcher/tmp/9584839/lava-overlay-3z5jbpws/lava-9584839/0/tests/0_dmesg test_uuid 9584839_1.4.2.3.1
149 12:48:13.748078 end: 1.4.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
151 12:48:13.748338 start: 1.4.2.3.5 inline-repo-action (timeout 00:09:59) [common]
152 12:48:13.748420 Using /lava-9584839 at stage 1
153 12:48:13.748696 uuid=9584839_1.4.2.3.5 testdef=None
154 12:48:13.748803 end: 1.4.2.3.5 inline-repo-action (duration 00:00:00) [common]
155 12:48:13.748894 start: 1.4.2.3.6 test-overlay (timeout 00:09:59) [common]
156 12:48:13.749463 end: 1.4.2.3.6 test-overlay (duration 00:00:00) [common]
158 12:48:13.749706 start: 1.4.2.3.7 test-install-overlay (timeout 00:09:59) [common]
159 12:48:13.750343 end: 1.4.2.3.7 test-install-overlay (duration 00:00:00) [common]
161 12:48:13.750599 start: 1.4.2.3.8 test-runscript-overlay (timeout 00:09:59) [common]
162 12:48:13.751187 runner path: /var/lib/lava/dispatcher/tmp/9584839/lava-overlay-3z5jbpws/lava-9584839/1/tests/1_bootrr test_uuid 9584839_1.4.2.3.5
163 12:48:13.751337 end: 1.4.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
165 12:48:13.751566 Creating lava-test-runner.conf files
166 12:48:13.751633 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/9584839/lava-overlay-3z5jbpws/lava-9584839/0 for stage 0
167 12:48:13.751731 - 0_dmesg
168 12:48:13.751812 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/9584839/lava-overlay-3z5jbpws/lava-9584839/1 for stage 1
169 12:48:13.751902 - 1_bootrr
170 12:48:13.752026 end: 1.4.2.3 test-definition (duration 00:00:00) [common]
171 12:48:13.752116 start: 1.4.2.4 compress-overlay (timeout 00:09:59) [common]
172 12:48:13.759032 end: 1.4.2.4 compress-overlay (duration 00:00:00) [common]
173 12:48:13.759156 start: 1.4.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
174 12:48:13.759265 end: 1.4.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
175 12:48:13.759358 end: 1.4.2 lava-overlay (duration 00:00:00) [common]
176 12:48:13.759462 start: 1.4.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
177 12:48:13.948134 end: 1.4.3 extract-overlay-ramdisk (duration 00:00:00) [common]
178 12:48:13.948510 start: 1.4.4 extract-modules (timeout 00:09:59) [common]
179 12:48:13.948623 extracting modules file /var/lib/lava/dispatcher/tmp/9584839/tftp-deploy-0bzs7r4m/modules/modules.tar to /var/lib/lava/dispatcher/tmp/9584839/extract-overlay-ramdisk-vp6p_e0i/ramdisk
180 12:48:13.956555 end: 1.4.4 extract-modules (duration 00:00:00) [common]
181 12:48:13.956699 start: 1.4.5 apply-overlay-tftp (timeout 00:09:59) [common]
182 12:48:13.956794 [common] Applying overlay /var/lib/lava/dispatcher/tmp/9584839/compress-overlay-tz4xn0xl/overlay-1.4.2.4.tar.gz to ramdisk
183 12:48:13.956872 [common] Applying overlay /var/lib/lava/dispatcher/tmp/9584839/compress-overlay-tz4xn0xl/overlay-1.4.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/9584839/extract-overlay-ramdisk-vp6p_e0i/ramdisk
184 12:48:13.961189 end: 1.4.5 apply-overlay-tftp (duration 00:00:00) [common]
185 12:48:13.961309 start: 1.4.6 configure-preseed-file (timeout 00:09:59) [common]
186 12:48:13.961409 end: 1.4.6 configure-preseed-file (duration 00:00:00) [common]
187 12:48:13.961513 start: 1.4.7 compress-ramdisk (timeout 00:09:59) [common]
188 12:48:13.961594 Building ramdisk /var/lib/lava/dispatcher/tmp/9584839/extract-overlay-ramdisk-vp6p_e0i/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/9584839/extract-overlay-ramdisk-vp6p_e0i/ramdisk
189 12:48:14.029659 >> 49731 blocks
190 12:48:14.862472 rename /var/lib/lava/dispatcher/tmp/9584839/extract-overlay-ramdisk-vp6p_e0i/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/9584839/tftp-deploy-0bzs7r4m/ramdisk/ramdisk.cpio.gz
191 12:48:14.862884 end: 1.4.7 compress-ramdisk (duration 00:00:01) [common]
192 12:48:14.863010 start: 1.4.8 prepare-kernel (timeout 00:09:58) [common]
193 12:48:14.863116 start: 1.4.8.1 prepare-fit (timeout 00:09:58) [common]
194 12:48:14.863222 No mkimage arch provided, not using FIT.
195 12:48:14.863349 end: 1.4.8.1 prepare-fit (duration 00:00:00) [common]
196 12:48:14.863637 end: 1.4.8 prepare-kernel (duration 00:00:00) [common]
197 12:48:14.863744 end: 1.4 prepare-tftp-overlay (duration 00:00:01) [common]
198 12:48:14.863845 start: 1.5 lxc-create-udev-rule-action (timeout 00:09:58) [common]
199 12:48:14.863924 No LXC device requested
200 12:48:14.864009 end: 1.5 lxc-create-udev-rule-action (duration 00:00:00) [common]
201 12:48:14.864110 start: 1.6 deploy-device-env (timeout 00:09:58) [common]
202 12:48:14.864203 end: 1.6 deploy-device-env (duration 00:00:00) [common]
203 12:48:14.864276 Checking files for TFTP limit of 4294967296 bytes.
204 12:48:14.864680 end: 1 tftp-deploy (duration 00:00:02) [common]
205 12:48:14.864782 start: 2 depthcharge-action (timeout 00:05:00) [common]
206 12:48:14.864888 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
207 12:48:14.865014 substitutions:
208 12:48:14.865081 - {DTB}: None
209 12:48:14.865146 - {INITRD}: 9584839/tftp-deploy-0bzs7r4m/ramdisk/ramdisk.cpio.gz
210 12:48:14.865224 - {KERNEL}: 9584839/tftp-deploy-0bzs7r4m/kernel/bzImage
211 12:48:14.865284 - {LAVA_MAC}: None
212 12:48:14.865342 - {PRESEED_CONFIG}: None
213 12:48:14.865400 - {PRESEED_LOCAL}: None
214 12:48:14.865466 - {RAMDISK}: 9584839/tftp-deploy-0bzs7r4m/ramdisk/ramdisk.cpio.gz
215 12:48:14.865523 - {ROOT_PART}: None
216 12:48:14.865579 - {ROOT}: None
217 12:48:14.865635 - {SERVER_IP}: 192.168.201.1
218 12:48:14.865717 - {TEE}: None
219 12:48:14.865777 Parsed boot commands:
220 12:48:14.865833 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
221 12:48:14.866000 Parsed boot commands: tftpboot 192.168.201.1 9584839/tftp-deploy-0bzs7r4m/kernel/bzImage 9584839/tftp-deploy-0bzs7r4m/kernel/cmdline 9584839/tftp-deploy-0bzs7r4m/ramdisk/ramdisk.cpio.gz
222 12:48:14.866096 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
223 12:48:14.866197 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
224 12:48:14.866297 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
225 12:48:14.866384 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
226 12:48:14.866464 Not connected, no need to disconnect.
227 12:48:14.866545 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
228 12:48:14.866628 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
229 12:48:14.866704 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost asus-cx9400-volteer-cbg-3'
230 12:48:14.869625 Setting prompt string to ['lava-test: # ']
231 12:48:14.869964 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
232 12:48:14.870071 end: 2.2.1 reset-connection (duration 00:00:00) [common]
233 12:48:14.870172 start: 2.2.2 reset-device (timeout 00:05:00) [common]
234 12:48:14.870272 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
235 12:48:14.870462 Calling: 'nice' 'pduclient' '--daemon=localhost' '--hostname=asus-cx9400-volteer-cbg-3' '--port=1' '--command=reboot'
236 12:48:20.000348 >> Command sent successfully.
237 12:48:20.002471 Returned 0 in 5 seconds
238 12:48:20.103227 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
240 12:48:20.103588 end: 2.2.2 reset-device (duration 00:00:05) [common]
241 12:48:20.103694 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
242 12:48:20.103782 Setting prompt string to 'Starting depthcharge on Voema...'
243 12:48:20.103861 Changing prompt to 'Starting depthcharge on Voema...'
244 12:48:20.103935 depthcharge-start: Wait for prompt Starting depthcharge on Voema... (timeout 00:05:00)
245 12:48:20.104211 [Enter `^Ec?' for help]
246 12:48:21.705188
247 12:48:21.705358
248 12:48:21.715058 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 bootblock starting (log level: 8)...
249 12:48:21.721816 CPU: 11th Gen Intel(R) Core(TM) i5-1130G7 @ 1.10GHz
250 12:48:21.724654 CPU: ID 806c1, Tigerlake B0, ucode: 00000086
251 12:48:21.728169 CPU: AES supported, TXT NOT supported, VT supported
252 12:48:21.735027 MCH: device id 9a12 (rev 01) is Tigerlake-Y-4-2
253 12:48:21.741335 PCH: device id a087 (rev 20) is Tigerlake-Y Premium SKU
254 12:48:21.744692 IGD: device id 9a40 (rev 01) is Tigerlake Y GT2
255 12:48:21.748147 VBOOT: Loading verstage.
256 12:48:21.754672 FMAP: Found "FLASH" version 1.1 at 0x1804000.
257 12:48:21.758294 FMAP: base = 0x0 size = 0x2000000 #areas = 32
258 12:48:21.761537 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
259 12:48:21.772078 CBFS: mcache @0xfef45600 built for 70 files, used 0xfdc of 0x1800 bytes
260 12:48:21.778922 CBFS: Found 'fallback/verstage' @0x165e40 size 0x147ec in mcache @0xfef45984
261 12:48:21.779047
262 12:48:21.779136
263 12:48:21.791910 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 verstage starting (log level: 8)...
264 12:48:21.805804 Probing TPM: . done!
265 12:48:21.809220 TPM ready after 0 ms
266 12:48:21.812211 Connected to device vid:did:rid of 1ae0:0028:00
267 12:48:21.823768 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.6.20/cr50_v1.9308_B.947-551594aae6
268 12:48:21.830301 Current CR50_BOARD_CFG = 0x80000001, matches desired = 0x00000001
269 12:48:21.833454 Initialized TPM device CR50 revision 0
270 12:48:21.885278 tlcl_send_startup: Startup return code is 0
271 12:48:21.885412 TPM: setup succeeded
272 12:48:21.900700 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
273 12:48:21.914914 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
274 12:48:21.927601 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
275 12:48:21.937349 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
276 12:48:21.941893 Chrome EC: UHEPI supported
277 12:48:21.945145 Phase 1
278 12:48:21.948320 FMAP: area GBB found @ 1805000 (458752 bytes)
279 12:48:21.958591 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
280 12:48:21.964950 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
281 12:48:21.971680 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
282 12:48:21.978384 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
283 12:48:21.981794 Recovery requested (1009000e)
284 12:48:21.984941 TPM: Extending digest for VBOOT: boot mode into PCR 0
285 12:48:21.996648 tlcl_extend: response is 0
286 12:48:22.003041 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
287 12:48:22.012989 tlcl_extend: response is 0
288 12:48:22.019835 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
289 12:48:22.026499 CBFS: Found 'fallback/romstage' @0x80 size 0x1bf24 in mcache @0xfef45638
290 12:48:22.033125 BS: verstage times (exec / console): total (unknown) / 142 ms
291 12:48:22.033215
292 12:48:22.033289
293 12:48:22.046277 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 romstage starting (log level: 8)...
294 12:48:22.052938 VB2:vb2api_ec_sync() In recovery mode, skipping EC sync
295 12:48:22.056504 pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00
296 12:48:22.059719 gpe0_sts[0]: 00200000 gpe0_en[0]: 00000000
297 12:48:22.066425 gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000
298 12:48:22.069718 gpe0_sts[2]: 00001000 gpe0_en[2]: 00000000
299 12:48:22.073076 gpe0_sts[3]: 00000000 gpe0_en[3]: 00092000
300 12:48:22.076116 TCO_STS: 0000 0000
301 12:48:22.079468 GEN_PMCON: d0015038 00002200
302 12:48:22.083087 GBLRST_CAUSE: 00000000 00000000
303 12:48:22.083169 HPR_CAUSE0: 00000000
304 12:48:22.086357 prev_sleep_state 5
305 12:48:22.089556 Boot Count incremented to 17342
306 12:48:22.096197 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
307 12:48:22.102705 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
308 12:48:22.109447 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
309 12:48:22.116156 CBFS: Found 'fspm.bin' @0x78fc0 size 0xa5000 in mcache @0xfef4585c
310 12:48:22.120831 Chrome EC: UHEPI supported
311 12:48:22.127038 FMAP: area RECOVERY_MRC_CACHE found @ f00000 (65536 bytes)
312 12:48:22.140181 Probing TPM: done!
313 12:48:22.147048 Connected to device vid:did:rid of 1ae0:0028:00
314 12:48:22.157402 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.6.20/cr50_v1.9308_B.947-551594aae6
315 12:48:22.160608 Initialized TPM device CR50 revision 0
316 12:48:22.175331 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x100b return code 0
317 12:48:22.181832 MRC: Hash idx 0x100b comparison successful.
318 12:48:22.185212 MRC cache found, size faa8
319 12:48:22.185302 bootmode is set to: 2
320 12:48:22.188557 SPD index = 0
321 12:48:22.195277 CBFS: Found 'spd.bin' @0x72940 size 0x600 in mcache @0xfef4579c
322 12:48:22.198437 SPD: module type is LPDDR4X
323 12:48:22.204877 SPD: module part number is MT53E512M64D4NW-046
324 12:48:22.208271 SPD: banks 8, ranks 1, rows 16, columns 10, density 8192 Mb
325 12:48:22.215111 SPD: device width 16 bits, bus width 16 bits
326 12:48:22.218312 SPD: module size is 1024 MB (per channel)
327 12:48:22.649745 CBMEM:
328 12:48:22.653121 IMD: root @ 0x76fff000 254 entries.
329 12:48:22.656547 IMD: root @ 0x76ffec00 62 entries.
330 12:48:22.659985 FMAP: area RO_VPD found @ 1800000 (16384 bytes)
331 12:48:22.666364 FMAP: area RW_VPD found @ f35000 (8192 bytes)
332 12:48:22.669844 External stage cache:
333 12:48:22.673223 IMD: root @ 0x7b3ff000 254 entries.
334 12:48:22.676254 IMD: root @ 0x7b3fec00 62 entries.
335 12:48:22.691814 FMAP: area RECOVERY_MRC_CACHE found @ f00000 (65536 bytes)
336 12:48:22.698380 MRC: Checking cached data update for 'RECOVERY_MRC_CACHE'.
337 12:48:22.704619 SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
338 12:48:22.718921 MRC: 'RECOVERY_MRC_CACHE' does not need update.
339 12:48:22.722295 cse_lite: Skip switching to RW in the recovery path
340 12:48:22.726005 8 DIMMs found
341 12:48:22.726107 SMM Memory Map
342 12:48:22.730059 SMRAM : 0x7b000000 0x800000
343 12:48:22.733126 Subregion 0: 0x7b000000 0x200000
344 12:48:22.736519 Subregion 1: 0x7b200000 0x200000
345 12:48:22.739880 Subregion 2: 0x7b400000 0x400000
346 12:48:22.743193 top_of_ram = 0x77000000
347 12:48:22.750042 MTRR Range: Start=76000000 End=77000000 (Size 1000000)
348 12:48:22.753283 MTRR Range: Start=7b000000 End=7b800000 (Size 800000)
349 12:48:22.759740 MTRR Range: Start=f9000000 End=fa000000 (Size 1000000)
350 12:48:22.763299 MTRR Range: Start=ff000000 End=0 (Size 1000000)
351 12:48:22.772873 CBFS: Found 'fallback/postcar' @0x160900 size 0x54f8 in mcache @0xfef4594c
352 12:48:22.779664 Decompressing stage fallback/postcar @ 0x76c0afc0 (38208 bytes)
353 12:48:22.789476 Loading module at 0x76c0b000 with entry 0x76c0b000. filesize: 0x5150 memsize: 0x9500
354 12:48:22.793014 Processing 211 relocs. Offset value of 0x74c0b000
355 12:48:22.801952 BS: romstage times (exec / console): total (unknown) / 277 ms
356 12:48:22.807790
357 12:48:22.807868
358 12:48:22.817688 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 postcar starting (log level: 8)...
359 12:48:22.820948 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
360 12:48:22.831100 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
361 12:48:22.837550 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
362 12:48:22.843925 CBFS: Found 'fallback/ramstage' @0x524c0 size 0x1fbe3 in mcache @0x76c4c0ec
363 12:48:22.850511 Decompressing stage fallback/ramstage @ 0x76b97fc0 (463536 bytes)
364 12:48:22.897782 Loading module at 0x76b98000 with entry 0x76b98000. filesize: 0x4d5d8 memsize: 0x71270
365 12:48:22.904312 Processing 5008 relocs. Offset value of 0x75d98000
366 12:48:22.907835 BS: postcar times (exec / console): total (unknown) / 59 ms
367 12:48:22.911163
368 12:48:22.911248
369 12:48:22.921539 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 ramstage starting (log level: 8)...
370 12:48:22.921626 Normal boot
371 12:48:22.924783 FW_CONFIG value is 0x804c02
372 12:48:22.928250 PCI: 00:07.0 disabled by fw_config
373 12:48:22.931483 PCI: 00:07.1 disabled by fw_config
374 12:48:22.934946 PCI: 00:0d.2 disabled by fw_config
375 12:48:22.938073 PCI: 00:1c.7 disabled by fw_config
376 12:48:22.944775 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
377 12:48:22.951406 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
378 12:48:22.954833 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
379 12:48:22.957853 GENERIC: 0.0 disabled by fw_config
380 12:48:22.961115 GENERIC: 1.0 disabled by fw_config
381 12:48:22.967827 fw_config match found: DB_USB=USB3_ACTIVE
382 12:48:22.971235 fw_config match found: DB_USB=USB3_ACTIVE
383 12:48:22.974555 fw_config match found: DB_USB=USB3_ACTIVE
384 12:48:22.978062 fw_config match found: DB_USB=USB3_ACTIVE
385 12:48:22.984320 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
386 12:48:22.991261 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
387 12:48:23.000994 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
388 12:48:23.007730 CBFS: Found 'cpu_microcode_blob.bin' @0x1c040 size 0x36400 in mcache @0x76c4c09c
389 12:48:23.011104 microcode: sig=0x806c1 pf=0x80 revision=0x86
390 12:48:23.017451 microcode: Update skipped, already up-to-date
391 12:48:23.024302 CBFS: Found 'fsps.bin' @0x11efc0 size 0x418f9 in mcache @0x76c4c30c
392 12:48:23.051365 Detected 4 core, 8 thread CPU.
393 12:48:23.054711 Setting up SMI for CPU
394 12:48:23.058012 IED base = 0x7b400000
395 12:48:23.058099 IED size = 0x00400000
396 12:48:23.061398 Will perform SMM setup.
397 12:48:23.067979 CPU: 11th Gen Intel(R) Core(TM) i5-1130G7 @ 1.10GHz.
398 12:48:23.074881 Loading module at 0x00030000 with entry 0x00030000. filesize: 0x170 memsize: 0x170
399 12:48:23.081334 Processing 16 relocs. Offset value of 0x00030000
400 12:48:23.084628 Attempting to start 7 APs
401 12:48:23.088087 Waiting for 10ms after sending INIT.
402 12:48:23.103533 Waiting for 1st SIPI to complete...AP: slot 1 apic_id 1.
403 12:48:23.103624 done.
404 12:48:23.106907 AP: slot 2 apic_id 5.
405 12:48:23.110153 AP: slot 6 apic_id 4.
406 12:48:23.110240 AP: slot 5 apic_id 3.
407 12:48:23.113674 AP: slot 3 apic_id 6.
408 12:48:23.116611 AP: slot 7 apic_id 7.
409 12:48:23.116705 AP: slot 4 apic_id 2.
410 12:48:23.123513 Waiting for 2nd SIPI to complete...done.
411 12:48:23.130133 Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1b8 memsize: 0x1b8
412 12:48:23.136500 Processing 13 relocs. Offset value of 0x00038000
413 12:48:23.136580 Unable to locate Global NVS
414 12:48:23.146526 SMM Module: stub loaded at 0x00038000. Will call 0x76bb6318(0x00000000)
415 12:48:23.149998 Installing permanent SMM handler to 0x7b000000
416 12:48:23.160051 Loading module at 0x7b010000 with entry 0x7b010c16. filesize: 0xa7c8 memsize: 0xf908
417 12:48:23.163221 Processing 794 relocs. Offset value of 0x7b010000
418 12:48:23.173036 Loading module at 0x7b008000 with entry 0x7b008000. filesize: 0x1b8 memsize: 0x1b8
419 12:48:23.176364 Processing 13 relocs. Offset value of 0x7b008000
420 12:48:23.183093 SMM Module: placing jmp sequence at 0x7b007c00 rel16 0x03fd
421 12:48:23.189589 SMM Module: placing jmp sequence at 0x7b007800 rel16 0x07fd
422 12:48:23.192960 SMM Module: placing jmp sequence at 0x7b007400 rel16 0x0bfd
423 12:48:23.199697 SMM Module: placing jmp sequence at 0x7b007000 rel16 0x0ffd
424 12:48:23.206390 SMM Module: placing jmp sequence at 0x7b006c00 rel16 0x13fd
425 12:48:23.213147 SMM Module: placing jmp sequence at 0x7b006800 rel16 0x17fd
426 12:48:23.219446 SMM Module: placing jmp sequence at 0x7b006400 rel16 0x1bfd
427 12:48:23.219557 Unable to locate Global NVS
428 12:48:23.229558 SMM Module: stub loaded at 0x7b008000. Will call 0x7b010c16(0x00000000)
429 12:48:23.232688 Clearing SMI status registers
430 12:48:23.232782 SMI_STS: PM1
431 12:48:23.236099 PM1_STS: PWRBTN
432 12:48:23.242844 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b000000, cpu = 0
433 12:48:23.246116 In relocation handler: CPU 0
434 12:48:23.249433 New SMBASE=0x7b000000 IEDBASE=0x7b400000
435 12:48:23.255866 Writing SMRR. base = 0x7b000006, mask=0xff800c00
436 12:48:23.255963 Relocation complete.
437 12:48:23.265764 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afffc00, cpu = 1
438 12:48:23.265851 In relocation handler: CPU 1
439 12:48:23.272622 New SMBASE=0x7afffc00 IEDBASE=0x7b400000
440 12:48:23.272719 Relocation complete.
441 12:48:23.282694 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affe400, cpu = 7
442 12:48:23.282780 In relocation handler: CPU 7
443 12:48:23.289104 New SMBASE=0x7affe400 IEDBASE=0x7b400000
444 12:48:23.289193 Relocation complete.
445 12:48:23.298987 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff400, cpu = 3
446 12:48:23.299073 In relocation handler: CPU 3
447 12:48:23.305550 New SMBASE=0x7afff400 IEDBASE=0x7b400000
448 12:48:23.308887 Writing SMRR. base = 0x7b000006, mask=0xff800c00
449 12:48:23.312366 Relocation complete.
450 12:48:23.319135 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affec00, cpu = 5
451 12:48:23.322512 In relocation handler: CPU 5
452 12:48:23.325557 New SMBASE=0x7affec00 IEDBASE=0x7b400000
453 12:48:23.328931 Relocation complete.
454 12:48:23.335433 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff000, cpu = 4
455 12:48:23.338812 In relocation handler: CPU 4
456 12:48:23.342191 New SMBASE=0x7afff000 IEDBASE=0x7b400000
457 12:48:23.348908 Writing SMRR. base = 0x7b000006, mask=0xff800c00
458 12:48:23.349002 Relocation complete.
459 12:48:23.355423 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff800, cpu = 2
460 12:48:23.358995 In relocation handler: CPU 2
461 12:48:23.365405 New SMBASE=0x7afff800 IEDBASE=0x7b400000
462 12:48:23.365499 Relocation complete.
463 12:48:23.371958 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affe800, cpu = 6
464 12:48:23.375145 In relocation handler: CPU 6
465 12:48:23.378445 New SMBASE=0x7affe800 IEDBASE=0x7b400000
466 12:48:23.385129 Writing SMRR. base = 0x7b000006, mask=0xff800c00
467 12:48:23.389058 Relocation complete.
468 12:48:23.389166 Initializing CPU #0
469 12:48:23.392935 CPU: vendor Intel device 806c1
470 12:48:23.396360 CPU: family 06, model 8c, stepping 01
471 12:48:23.399677 Clearing out pending MCEs
472 12:48:23.402841 Setting up local APIC...
473 12:48:23.402921 apic_id: 0x00 done.
474 12:48:23.406253 Turbo is available but hidden
475 12:48:23.409334 Turbo is available and visible
476 12:48:23.416126 microcode: Update skipped, already up-to-date
477 12:48:23.416204 CPU #0 initialized
478 12:48:23.419457 Initializing CPU #4
479 12:48:23.422824 Initializing CPU #5
480 12:48:23.422901 CPU: vendor Intel device 806c1
481 12:48:23.429151 CPU: family 06, model 8c, stepping 01
482 12:48:23.432910 CPU: vendor Intel device 806c1
483 12:48:23.435878 CPU: family 06, model 8c, stepping 01
484 12:48:23.435953 Clearing out pending MCEs
485 12:48:23.439348 Clearing out pending MCEs
486 12:48:23.442813 Setting up local APIC...
487 12:48:23.446199 Initializing CPU #2
488 12:48:23.446281 Initializing CPU #6
489 12:48:23.449084 CPU: vendor Intel device 806c1
490 12:48:23.452871 CPU: family 06, model 8c, stepping 01
491 12:48:23.455900 CPU: vendor Intel device 806c1
492 12:48:23.459181 CPU: family 06, model 8c, stepping 01
493 12:48:23.462496 Clearing out pending MCEs
494 12:48:23.465989 Clearing out pending MCEs
495 12:48:23.469152 Setting up local APIC...
496 12:48:23.469239 Initializing CPU #1
497 12:48:23.472283 apic_id: 0x02 done.
498 12:48:23.475925 Setting up local APIC...
499 12:48:23.479186 Setting up local APIC...
500 12:48:23.479274 Initializing CPU #3
501 12:48:23.482377 Initializing CPU #7
502 12:48:23.485752 CPU: vendor Intel device 806c1
503 12:48:23.489038 CPU: family 06, model 8c, stepping 01
504 12:48:23.492440 CPU: vendor Intel device 806c1
505 12:48:23.495776 CPU: family 06, model 8c, stepping 01
506 12:48:23.499068 Clearing out pending MCEs
507 12:48:23.502411 Clearing out pending MCEs
508 12:48:23.502499 Setting up local APIC...
509 12:48:23.508941 microcode: Update skipped, already up-to-date
510 12:48:23.509030 apic_id: 0x03 done.
511 12:48:23.512386 CPU #4 initialized
512 12:48:23.515825 microcode: Update skipped, already up-to-date
513 12:48:23.519075 apic_id: 0x06 done.
514 12:48:23.522262 Setting up local APIC...
515 12:48:23.525515 CPU: vendor Intel device 806c1
516 12:48:23.528893 CPU: family 06, model 8c, stepping 01
517 12:48:23.528981 CPU #5 initialized
518 12:48:23.532269 apic_id: 0x04 done.
519 12:48:23.535632 apic_id: 0x05 done.
520 12:48:23.538997 microcode: Update skipped, already up-to-date
521 12:48:23.545693 microcode: Update skipped, already up-to-date
522 12:48:23.545789 CPU #6 initialized
523 12:48:23.548702 CPU #2 initialized
524 12:48:23.548790 Clearing out pending MCEs
525 12:48:23.555501 microcode: Update skipped, already up-to-date
526 12:48:23.558774 apic_id: 0x07 done.
527 12:48:23.558864 CPU #3 initialized
528 12:48:23.562238 microcode: Update skipped, already up-to-date
529 12:48:23.565548 Setting up local APIC...
530 12:48:23.569012 CPU #7 initialized
531 12:48:23.569100 apic_id: 0x01 done.
532 12:48:23.575435 microcode: Update skipped, already up-to-date
533 12:48:23.578503 CPU #1 initialized
534 12:48:23.582128 bsp_do_flight_plan done after 455 msecs.
535 12:48:23.585391 CPU: frequency set to 4000 MHz
536 12:48:23.585479 Enabling SMIs.
537 12:48:23.592006 BS: BS_DEV_INIT_CHIPS entry times (exec / console): 347 / 317 ms
538 12:48:23.608215 SATAXPCIE1 indicates PCIe NVMe is present
539 12:48:23.612053 Probing TPM: done!
540 12:48:23.615261 Connected to device vid:did:rid of 1ae0:0028:00
541 12:48:23.625530 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_A:0.6.20/cr50_v1.9308_B.947-551594aae6
542 12:48:23.629186 Initialized TPM device CR50 revision 0
543 12:48:23.632390 Enabling S0i3.4
544 12:48:23.639135 CBFS: Found 'vbt.bin' @0x78a40 size 0x4f0 in mcache @0x76c4c1fc
545 12:48:23.642268 Found a VBT of 8704 bytes after decompression
546 12:48:23.649092 cse_lite: CSE RO boot. HybridStorageMode disabled
547 12:48:23.655545 WEAK: src/soc/intel/tigerlake/fsp_params.c/mainboard_silicon_init_params called
548 12:48:23.731391 FSPS returned 0
549 12:48:23.734766 Executing Phase 1 of FspMultiPhaseSiInit
550 12:48:23.744690 FSP MultiPhaseSiInit src/soc/intel/tigerlake/fsp_params.c/platform_fsp_multi_phase_init_cb called
551 12:48:23.748195 port C0 DISC req: usage 1 usb3 1 usb2 5
552 12:48:23.751189 Raw Buffer output 0 00000511
553 12:48:23.754670 Raw Buffer output 1 00000000
554 12:48:23.758110 pmc_send_ipc_cmd succeeded
555 12:48:23.764969 port C1 DISC req: usage 1 usb3 2 usb2 3
556 12:48:23.765065 Raw Buffer output 0 00000321
557 12:48:23.768217 Raw Buffer output 1 00000000
558 12:48:23.772445 pmc_send_ipc_cmd succeeded
559 12:48:23.777502 Detected 4 core, 8 thread CPU.
560 12:48:23.781024 Detected 4 core, 8 thread CPU.
561 12:48:24.014971 Display FSP Version Info HOB
562 12:48:24.018128 Reference Code - CPU = a.0.4c.31
563 12:48:24.021431 uCode Version = 0.0.0.86
564 12:48:24.025003 TXT ACM version = ff.ff.ff.ffff
565 12:48:24.028278 Reference Code - ME = a.0.4c.31
566 12:48:24.031532 MEBx version = 0.0.0.0
567 12:48:24.034695 ME Firmware Version = Consumer SKU
568 12:48:24.038316 Reference Code - PCH = a.0.4c.31
569 12:48:24.041345 PCH-CRID Status = Disabled
570 12:48:24.044864 PCH-CRID Original Value = ff.ff.ff.ffff
571 12:48:24.048141 PCH-CRID New Value = ff.ff.ff.ffff
572 12:48:24.051777 OPROM - RST - RAID = ff.ff.ff.ffff
573 12:48:24.055057 PCH Hsio Version = 4.0.0.0
574 12:48:24.058044 Reference Code - SA - System Agent = a.0.4c.31
575 12:48:24.061509 Reference Code - MRC = 2.0.0.1
576 12:48:24.064945 SA - PCIe Version = a.0.4c.31
577 12:48:24.068009 SA-CRID Status = Disabled
578 12:48:24.071322 SA-CRID Original Value = 0.0.0.1
579 12:48:24.074761 SA-CRID New Value = 0.0.0.1
580 12:48:24.078095 OPROM - VBIOS = ff.ff.ff.ffff
581 12:48:24.081393 IO Manageability Engine FW Version = 11.1.4.0
582 12:48:24.084924 PHY Build Version = 0.0.0.e0
583 12:48:24.088002 Thunderbolt(TM) FW Version = 0.0.0.0
584 12:48:24.094698 System Agent Manageability Engine FW Version = ff.ff.ff.ffff
585 12:48:24.098034 ITSS IRQ Polarities Before:
586 12:48:24.098120 IPC0: 0xffffffff
587 12:48:24.101233 IPC1: 0xffffffff
588 12:48:24.101322 IPC2: 0xffffffff
589 12:48:24.104611 IPC3: 0xffffffff
590 12:48:24.108082 ITSS IRQ Polarities After:
591 12:48:24.108166 IPC0: 0xffffffff
592 12:48:24.111381 IPC1: 0xffffffff
593 12:48:24.111465 IPC2: 0xffffffff
594 12:48:24.114775 IPC3: 0xffffffff
595 12:48:24.117980 Found PCIe Root Port #9 at PCI: 00:1d.0.
596 12:48:24.131248 pcie_rp_update_dev: Couldn't find PCIe Root Port #1 (originally PCI: 00:1c.0) which was enabled in devicetree, removing.
597 12:48:24.141079 pcie_rp_update_dev: Couldn't find PCIe Root Port #7 (originally PCI: 00:1c.6) which was enabled in devicetree, removing.
598 12:48:24.154386 pcie_rp_update_dev: Couldn't find PCIe Root Port #11 (originally PCI: 00:1d.2) which was enabled in devicetree, removing.
599 12:48:24.160928 BS: BS_DEV_INIT_CHIPS run times (exec / console): 326 / 236 ms
600 12:48:24.164419 Enumerating buses...
601 12:48:24.167697 Show all devs... Before device enumeration.
602 12:48:24.171059 Root Device: enabled 1
603 12:48:24.171151 DOMAIN: 0000: enabled 1
604 12:48:24.174370 CPU_CLUSTER: 0: enabled 1
605 12:48:24.177741 PCI: 00:00.0: enabled 1
606 12:48:24.180736 PCI: 00:02.0: enabled 1
607 12:48:24.180817 PCI: 00:04.0: enabled 1
608 12:48:24.184219 PCI: 00:05.0: enabled 1
609 12:48:24.187580 PCI: 00:06.0: enabled 0
610 12:48:24.187667 PCI: 00:07.0: enabled 0
611 12:48:24.190945 PCI: 00:07.1: enabled 0
612 12:48:24.194033 PCI: 00:07.2: enabled 0
613 12:48:24.197400 PCI: 00:07.3: enabled 0
614 12:48:24.197479 PCI: 00:08.0: enabled 1
615 12:48:24.200891 PCI: 00:09.0: enabled 0
616 12:48:24.204214 PCI: 00:0a.0: enabled 0
617 12:48:24.207272 PCI: 00:0d.0: enabled 1
618 12:48:24.207355 PCI: 00:0d.1: enabled 0
619 12:48:24.210586 PCI: 00:0d.2: enabled 0
620 12:48:24.214071 PCI: 00:0d.3: enabled 0
621 12:48:24.217519 PCI: 00:0e.0: enabled 0
622 12:48:24.217598 PCI: 00:10.2: enabled 1
623 12:48:24.220885 PCI: 00:10.6: enabled 0
624 12:48:24.224179 PCI: 00:10.7: enabled 0
625 12:48:24.227646 PCI: 00:12.0: enabled 0
626 12:48:24.227730 PCI: 00:12.6: enabled 0
627 12:48:24.230555 PCI: 00:13.0: enabled 0
628 12:48:24.233979 PCI: 00:14.0: enabled 1
629 12:48:24.234066 PCI: 00:14.1: enabled 0
630 12:48:24.237578 PCI: 00:14.2: enabled 1
631 12:48:24.240697 PCI: 00:14.3: enabled 1
632 12:48:24.244035 PCI: 00:15.0: enabled 1
633 12:48:24.244125 PCI: 00:15.1: enabled 1
634 12:48:24.247146 PCI: 00:15.2: enabled 1
635 12:48:24.250845 PCI: 00:15.3: enabled 1
636 12:48:24.254046 PCI: 00:16.0: enabled 1
637 12:48:24.254135 PCI: 00:16.1: enabled 0
638 12:48:24.257153 PCI: 00:16.2: enabled 0
639 12:48:24.260422 PCI: 00:16.3: enabled 0
640 12:48:24.263651 PCI: 00:16.4: enabled 0
641 12:48:24.263734 PCI: 00:16.5: enabled 0
642 12:48:24.267101 PCI: 00:17.0: enabled 1
643 12:48:24.270480 PCI: 00:19.0: enabled 0
644 12:48:24.273940 PCI: 00:19.1: enabled 1
645 12:48:24.274024 PCI: 00:19.2: enabled 0
646 12:48:24.276941 PCI: 00:1c.0: enabled 1
647 12:48:24.280376 PCI: 00:1c.1: enabled 0
648 12:48:24.280459 PCI: 00:1c.2: enabled 0
649 12:48:24.283798 PCI: 00:1c.3: enabled 0
650 12:48:24.287261 PCI: 00:1c.4: enabled 0
651 12:48:24.290452 PCI: 00:1c.5: enabled 0
652 12:48:24.290539 PCI: 00:1c.6: enabled 1
653 12:48:24.293869 PCI: 00:1c.7: enabled 0
654 12:48:24.296893 PCI: 00:1d.0: enabled 1
655 12:48:24.300296 PCI: 00:1d.1: enabled 0
656 12:48:24.300387 PCI: 00:1d.2: enabled 1
657 12:48:24.303743 PCI: 00:1d.3: enabled 0
658 12:48:24.307216 PCI: 00:1e.0: enabled 1
659 12:48:24.310473 PCI: 00:1e.1: enabled 0
660 12:48:24.310559 PCI: 00:1e.2: enabled 1
661 12:48:24.313624 PCI: 00:1e.3: enabled 1
662 12:48:24.317070 PCI: 00:1f.0: enabled 1
663 12:48:24.317160 PCI: 00:1f.1: enabled 0
664 12:48:24.320474 PCI: 00:1f.2: enabled 1
665 12:48:24.323721 PCI: 00:1f.3: enabled 1
666 12:48:24.327073 PCI: 00:1f.4: enabled 0
667 12:48:24.327159 PCI: 00:1f.5: enabled 1
668 12:48:24.330071 PCI: 00:1f.6: enabled 0
669 12:48:24.333518 PCI: 00:1f.7: enabled 0
670 12:48:24.336988 APIC: 00: enabled 1
671 12:48:24.337075 GENERIC: 0.0: enabled 1
672 12:48:24.340318 GENERIC: 0.0: enabled 1
673 12:48:24.343556 GENERIC: 1.0: enabled 1
674 12:48:24.343639 GENERIC: 0.0: enabled 1
675 12:48:24.346701 GENERIC: 1.0: enabled 1
676 12:48:24.350245 USB0 port 0: enabled 1
677 12:48:24.353575 GENERIC: 0.0: enabled 1
678 12:48:24.353667 USB0 port 0: enabled 1
679 12:48:24.356992 GENERIC: 0.0: enabled 1
680 12:48:24.360167 I2C: 00:1a: enabled 1
681 12:48:24.360251 I2C: 00:31: enabled 1
682 12:48:24.363329 I2C: 00:32: enabled 1
683 12:48:24.366659 I2C: 00:10: enabled 1
684 12:48:24.366749 I2C: 00:15: enabled 1
685 12:48:24.370065 GENERIC: 0.0: enabled 0
686 12:48:24.373594 GENERIC: 1.0: enabled 0
687 12:48:24.376943 GENERIC: 0.0: enabled 1
688 12:48:24.377048 SPI: 00: enabled 1
689 12:48:24.379920 SPI: 00: enabled 1
690 12:48:24.383550 PNP: 0c09.0: enabled 1
691 12:48:24.383648 GENERIC: 0.0: enabled 1
692 12:48:24.386575 USB3 port 0: enabled 1
693 12:48:24.389972 USB3 port 1: enabled 1
694 12:48:24.390060 USB3 port 2: enabled 0
695 12:48:24.393540 USB3 port 3: enabled 0
696 12:48:24.396922 USB2 port 0: enabled 0
697 12:48:24.399957 USB2 port 1: enabled 1
698 12:48:24.400036 USB2 port 2: enabled 1
699 12:48:24.403187 USB2 port 3: enabled 0
700 12:48:24.406525 USB2 port 4: enabled 1
701 12:48:24.406608 USB2 port 5: enabled 0
702 12:48:24.410073 USB2 port 6: enabled 0
703 12:48:24.413428 USB2 port 7: enabled 0
704 12:48:24.413507 USB2 port 8: enabled 0
705 12:48:24.417071 USB2 port 9: enabled 0
706 12:48:24.419918 USB3 port 0: enabled 0
707 12:48:24.423325 USB3 port 1: enabled 1
708 12:48:24.423408 USB3 port 2: enabled 0
709 12:48:24.426701 USB3 port 3: enabled 0
710 12:48:24.430096 GENERIC: 0.0: enabled 1
711 12:48:24.430180 GENERIC: 1.0: enabled 1
712 12:48:24.433054 APIC: 01: enabled 1
713 12:48:24.436865 APIC: 05: enabled 1
714 12:48:24.436944 APIC: 06: enabled 1
715 12:48:24.439853 APIC: 02: enabled 1
716 12:48:24.443227 APIC: 03: enabled 1
717 12:48:24.443304 APIC: 04: enabled 1
718 12:48:24.446648 APIC: 07: enabled 1
719 12:48:24.446724 Compare with tree...
720 12:48:24.449976 Root Device: enabled 1
721 12:48:24.453243 DOMAIN: 0000: enabled 1
722 12:48:24.456372 PCI: 00:00.0: enabled 1
723 12:48:24.459995 PCI: 00:02.0: enabled 1
724 12:48:24.460088 PCI: 00:04.0: enabled 1
725 12:48:24.463132 GENERIC: 0.0: enabled 1
726 12:48:24.466469 PCI: 00:05.0: enabled 1
727 12:48:24.469872 PCI: 00:06.0: enabled 0
728 12:48:24.473017 PCI: 00:07.0: enabled 0
729 12:48:24.473106 GENERIC: 0.0: enabled 1
730 12:48:24.476453 PCI: 00:07.1: enabled 0
731 12:48:24.479830 GENERIC: 1.0: enabled 1
732 12:48:24.483029 PCI: 00:07.2: enabled 0
733 12:48:24.486260 GENERIC: 0.0: enabled 1
734 12:48:24.486352 PCI: 00:07.3: enabled 0
735 12:48:24.489599 GENERIC: 1.0: enabled 1
736 12:48:24.492691 PCI: 00:08.0: enabled 1
737 12:48:24.496168 PCI: 00:09.0: enabled 0
738 12:48:24.499502 PCI: 00:0a.0: enabled 0
739 12:48:24.499586 PCI: 00:0d.0: enabled 1
740 12:48:24.502969 USB0 port 0: enabled 1
741 12:48:24.506097 USB3 port 0: enabled 1
742 12:48:24.509392 USB3 port 1: enabled 1
743 12:48:24.512899 USB3 port 2: enabled 0
744 12:48:24.512981 USB3 port 3: enabled 0
745 12:48:24.516320 PCI: 00:0d.1: enabled 0
746 12:48:24.519291 PCI: 00:0d.2: enabled 0
747 12:48:24.522979 GENERIC: 0.0: enabled 1
748 12:48:24.525956 PCI: 00:0d.3: enabled 0
749 12:48:24.526046 PCI: 00:0e.0: enabled 0
750 12:48:24.529418 PCI: 00:10.2: enabled 1
751 12:48:24.532760 PCI: 00:10.6: enabled 0
752 12:48:24.536091 PCI: 00:10.7: enabled 0
753 12:48:24.539409 PCI: 00:12.0: enabled 0
754 12:48:24.539491 PCI: 00:12.6: enabled 0
755 12:48:24.542955 PCI: 00:13.0: enabled 0
756 12:48:24.546344 PCI: 00:14.0: enabled 1
757 12:48:24.549218 USB0 port 0: enabled 1
758 12:48:24.552756 USB2 port 0: enabled 0
759 12:48:24.552847 USB2 port 1: enabled 1
760 12:48:24.556128 USB2 port 2: enabled 1
761 12:48:24.559284 USB2 port 3: enabled 0
762 12:48:24.562866 USB2 port 4: enabled 1
763 12:48:24.566138 USB2 port 5: enabled 0
764 12:48:24.569193 USB2 port 6: enabled 0
765 12:48:24.569282 USB2 port 7: enabled 0
766 12:48:24.572709 USB2 port 8: enabled 0
767 12:48:24.575869 USB2 port 9: enabled 0
768 12:48:24.579107 USB3 port 0: enabled 0
769 12:48:24.582722 USB3 port 1: enabled 1
770 12:48:24.586156 USB3 port 2: enabled 0
771 12:48:24.586240 USB3 port 3: enabled 0
772 12:48:24.589125 PCI: 00:14.1: enabled 0
773 12:48:24.592584 PCI: 00:14.2: enabled 1
774 12:48:24.595685 PCI: 00:14.3: enabled 1
775 12:48:24.599172 GENERIC: 0.0: enabled 1
776 12:48:24.599254 PCI: 00:15.0: enabled 1
777 12:48:24.602433 I2C: 00:1a: enabled 1
778 12:48:24.605676 I2C: 00:31: enabled 1
779 12:48:24.609095 I2C: 00:32: enabled 1
780 12:48:24.609180 PCI: 00:15.1: enabled 1
781 12:48:24.612517 I2C: 00:10: enabled 1
782 12:48:24.616105 PCI: 00:15.2: enabled 1
783 12:48:24.619073 PCI: 00:15.3: enabled 1
784 12:48:24.622427 PCI: 00:16.0: enabled 1
785 12:48:24.622507 PCI: 00:16.1: enabled 0
786 12:48:24.625586 PCI: 00:16.2: enabled 0
787 12:48:24.629062 PCI: 00:16.3: enabled 0
788 12:48:24.632865 PCI: 00:16.4: enabled 0
789 12:48:24.632947 PCI: 00:16.5: enabled 0
790 12:48:24.636643 PCI: 00:17.0: enabled 1
791 12:48:24.640408 PCI: 00:19.0: enabled 0
792 12:48:24.643379 PCI: 00:19.1: enabled 1
793 12:48:24.643462 I2C: 00:15: enabled 1
794 12:48:24.646840 PCI: 00:19.2: enabled 0
795 12:48:24.650364 PCI: 00:1d.0: enabled 1
796 12:48:24.653729 GENERIC: 0.0: enabled 1
797 12:48:24.656725 PCI: 00:1e.0: enabled 1
798 12:48:24.656814 PCI: 00:1e.1: enabled 0
799 12:48:24.660164 PCI: 00:1e.2: enabled 1
800 12:48:24.663588 SPI: 00: enabled 1
801 12:48:24.667051 PCI: 00:1e.3: enabled 1
802 12:48:24.667132 SPI: 00: enabled 1
803 12:48:24.716713 PCI: 00:1f.0: enabled 1
804 12:48:24.716857 PNP: 0c09.0: enabled 1
805 12:48:24.717134 PCI: 00:1f.1: enabled 0
806 12:48:24.717218 PCI: 00:1f.2: enabled 1
807 12:48:24.717287 GENERIC: 0.0: enabled 1
808 12:48:24.717353 GENERIC: 0.0: enabled 1
809 12:48:24.717424 GENERIC: 1.0: enabled 1
810 12:48:24.717487 PCI: 00:1f.3: enabled 1
811 12:48:24.717548 PCI: 00:1f.4: enabled 0
812 12:48:24.717617 PCI: 00:1f.5: enabled 1
813 12:48:24.717678 PCI: 00:1f.6: enabled 0
814 12:48:24.717749 PCI: 00:1f.7: enabled 0
815 12:48:24.717825 CPU_CLUSTER: 0: enabled 1
816 12:48:24.717885 APIC: 00: enabled 1
817 12:48:24.718129 APIC: 01: enabled 1
818 12:48:24.718206 APIC: 05: enabled 1
819 12:48:24.718267 APIC: 06: enabled 1
820 12:48:24.718327 APIC: 02: enabled 1
821 12:48:24.718393 APIC: 03: enabled 1
822 12:48:24.718454 APIC: 04: enabled 1
823 12:48:24.732060 APIC: 07: enabled 1
824 12:48:24.732150 Root Device scanning...
825 12:48:24.732421 scan_static_bus for Root Device
826 12:48:24.732494 DOMAIN: 0000 enabled
827 12:48:24.732561 CPU_CLUSTER: 0 enabled
828 12:48:24.735416 DOMAIN: 0000 scanning...
829 12:48:24.738425 PCI: pci_scan_bus for bus 00
830 12:48:24.741714 PCI: 00:00.0 [8086/0000] ops
831 12:48:24.745465 PCI: 00:00.0 [8086/9a12] enabled
832 12:48:24.748416 PCI: 00:02.0 [8086/0000] bus ops
833 12:48:24.751971 PCI: 00:02.0 [8086/9a40] enabled
834 12:48:24.755368 PCI: 00:04.0 [8086/0000] bus ops
835 12:48:24.758390 PCI: 00:04.0 [8086/9a03] enabled
836 12:48:24.761759 PCI: 00:05.0 [8086/9a19] enabled
837 12:48:24.765129 PCI: 00:07.0 [0000/0000] hidden
838 12:48:24.768482 PCI: 00:08.0 [8086/9a11] enabled
839 12:48:24.771562 PCI: 00:0a.0 [8086/9a0d] disabled
840 12:48:24.774992 PCI: 00:0d.0 [8086/0000] bus ops
841 12:48:24.778366 PCI: 00:0d.0 [8086/9a13] enabled
842 12:48:24.781844 PCI: 00:14.0 [8086/0000] bus ops
843 12:48:24.784895 PCI: 00:14.0 [8086/a0ed] enabled
844 12:48:24.788303 PCI: 00:14.2 [8086/a0ef] enabled
845 12:48:24.791553 PCI: 00:14.3 [8086/0000] bus ops
846 12:48:24.794967 PCI: 00:14.3 [8086/a0f0] enabled
847 12:48:24.798465 PCI: 00:15.0 [8086/0000] bus ops
848 12:48:24.801663 PCI: 00:15.0 [8086/a0e8] enabled
849 12:48:24.804922 PCI: 00:15.1 [8086/0000] bus ops
850 12:48:24.808195 PCI: 00:15.1 [8086/a0e9] enabled
851 12:48:24.811491 PCI: 00:15.2 [8086/0000] bus ops
852 12:48:24.814800 PCI: 00:15.2 [8086/a0ea] enabled
853 12:48:24.818120 PCI: 00:15.3 [8086/0000] bus ops
854 12:48:24.821583 PCI: 00:15.3 [8086/a0eb] enabled
855 12:48:24.824592 PCI: 00:16.0 [8086/0000] ops
856 12:48:24.828036 PCI: 00:16.0 [8086/a0e0] enabled
857 12:48:24.831280 PCI: Static device PCI: 00:17.0 not found, disabling it.
858 12:48:24.834613 PCI: 00:19.0 [8086/0000] bus ops
859 12:48:24.841249 PCI: 00:19.0 [8086/a0c5] disabled
860 12:48:24.844695 PCI: 00:19.1 [8086/0000] bus ops
861 12:48:24.848071 PCI: 00:19.1 [8086/a0c6] enabled
862 12:48:24.851318 PCI: 00:1d.0 [8086/0000] bus ops
863 12:48:24.854802 PCI: 00:1d.0 [8086/a0b0] enabled
864 12:48:24.854894 PCI: 00:1e.0 [8086/0000] ops
865 12:48:24.858118 PCI: 00:1e.0 [8086/a0a8] enabled
866 12:48:24.861089 PCI: 00:1e.2 [8086/0000] bus ops
867 12:48:24.864582 PCI: 00:1e.2 [8086/a0aa] enabled
868 12:48:24.867968 PCI: 00:1e.3 [8086/0000] bus ops
869 12:48:24.871452 PCI: 00:1e.3 [8086/a0ab] enabled
870 12:48:24.874522 PCI: 00:1f.0 [8086/0000] bus ops
871 12:48:24.877974 PCI: 00:1f.0 [8086/a087] enabled
872 12:48:24.881467 RTC Init
873 12:48:24.884474 Set power on after power failure.
874 12:48:24.884553 Disabling Deep S3
875 12:48:24.887712 Disabling Deep S3
876 12:48:24.891338 Disabling Deep S4
877 12:48:24.891418 Disabling Deep S4
878 12:48:24.894685 Disabling Deep S5
879 12:48:24.894764 Disabling Deep S5
880 12:48:24.897662 PCI: 00:1f.2 [0000/0000] hidden
881 12:48:24.901048 PCI: 00:1f.3 [8086/0000] bus ops
882 12:48:24.904656 PCI: 00:1f.3 [8086/a0c8] enabled
883 12:48:24.907991 PCI: 00:1f.5 [8086/0000] bus ops
884 12:48:24.911297 PCI: 00:1f.5 [8086/a0a4] enabled
885 12:48:24.914599 PCI: Leftover static devices:
886 12:48:24.917682 PCI: 00:10.2
887 12:48:24.917777 PCI: 00:10.6
888 12:48:24.917848 PCI: 00:10.7
889 12:48:24.921285 PCI: 00:06.0
890 12:48:24.921366 PCI: 00:07.1
891 12:48:24.924502 PCI: 00:07.2
892 12:48:24.924590 PCI: 00:07.3
893 12:48:24.924658 PCI: 00:09.0
894 12:48:24.928078 PCI: 00:0d.1
895 12:48:24.928159 PCI: 00:0d.2
896 12:48:24.931019 PCI: 00:0d.3
897 12:48:24.931104 PCI: 00:0e.0
898 12:48:24.934477 PCI: 00:12.0
899 12:48:24.934564 PCI: 00:12.6
900 12:48:24.934631 PCI: 00:13.0
901 12:48:24.937834 PCI: 00:14.1
902 12:48:24.937912 PCI: 00:16.1
903 12:48:24.940999 PCI: 00:16.2
904 12:48:24.941077 PCI: 00:16.3
905 12:48:24.941144 PCI: 00:16.4
906 12:48:24.944404 PCI: 00:16.5
907 12:48:24.944488 PCI: 00:17.0
908 12:48:24.947835 PCI: 00:19.2
909 12:48:24.947919 PCI: 00:1e.1
910 12:48:24.947986 PCI: 00:1f.1
911 12:48:24.951029 PCI: 00:1f.4
912 12:48:24.951112 PCI: 00:1f.6
913 12:48:24.954422 PCI: 00:1f.7
914 12:48:24.957871 PCI: Check your devicetree.cb.
915 12:48:24.957952 PCI: 00:02.0 scanning...
916 12:48:24.964273 scan_generic_bus for PCI: 00:02.0
917 12:48:24.967674 scan_generic_bus for PCI: 00:02.0 done
918 12:48:24.971040 scan_bus: bus PCI: 00:02.0 finished in 7 msecs
919 12:48:24.974187 PCI: 00:04.0 scanning...
920 12:48:24.977622 scan_generic_bus for PCI: 00:04.0
921 12:48:24.980955 GENERIC: 0.0 enabled
922 12:48:24.984286 bus: PCI: 00:04.0[0]->scan_generic_bus for PCI: 00:04.0 done
923 12:48:24.991017 scan_bus: bus PCI: 00:04.0 finished in 11 msecs
924 12:48:24.994349 PCI: 00:0d.0 scanning...
925 12:48:24.997451 scan_static_bus for PCI: 00:0d.0
926 12:48:24.997540 USB0 port 0 enabled
927 12:48:25.000740 USB0 port 0 scanning...
928 12:48:25.004111 scan_static_bus for USB0 port 0
929 12:48:25.007462 USB3 port 0 enabled
930 12:48:25.007556 USB3 port 1 enabled
931 12:48:25.010693 USB3 port 2 disabled
932 12:48:25.014441 USB3 port 3 disabled
933 12:48:25.014530 USB3 port 0 scanning...
934 12:48:25.017345 scan_static_bus for USB3 port 0
935 12:48:25.024273 scan_static_bus for USB3 port 0 done
936 12:48:25.027270 scan_bus: bus USB3 port 0 finished in 6 msecs
937 12:48:25.030579 USB3 port 1 scanning...
938 12:48:25.033981 scan_static_bus for USB3 port 1
939 12:48:25.037367 scan_static_bus for USB3 port 1 done
940 12:48:25.040921 scan_bus: bus USB3 port 1 finished in 6 msecs
941 12:48:25.044132 scan_static_bus for USB0 port 0 done
942 12:48:25.050429 scan_bus: bus USB0 port 0 finished in 43 msecs
943 12:48:25.053974 scan_static_bus for PCI: 00:0d.0 done
944 12:48:25.057307 scan_bus: bus PCI: 00:0d.0 finished in 60 msecs
945 12:48:25.060712 PCI: 00:14.0 scanning...
946 12:48:25.063671 scan_static_bus for PCI: 00:14.0
947 12:48:25.067079 USB0 port 0 enabled
948 12:48:25.070429 USB0 port 0 scanning...
949 12:48:25.073954 scan_static_bus for USB0 port 0
950 12:48:25.074037 USB2 port 0 disabled
951 12:48:25.076910 USB2 port 1 enabled
952 12:48:25.080383 USB2 port 2 enabled
953 12:48:25.080498 USB2 port 3 disabled
954 12:48:25.083952 USB2 port 4 enabled
955 12:48:25.084046 USB2 port 5 disabled
956 12:48:25.086860 USB2 port 6 disabled
957 12:48:25.090189 USB2 port 7 disabled
958 12:48:25.090277 USB2 port 8 disabled
959 12:48:25.093476 USB2 port 9 disabled
960 12:48:25.096871 USB3 port 0 disabled
961 12:48:25.096954 USB3 port 1 enabled
962 12:48:25.100203 USB3 port 2 disabled
963 12:48:25.103539 USB3 port 3 disabled
964 12:48:25.103618 USB2 port 1 scanning...
965 12:48:25.106883 scan_static_bus for USB2 port 1
966 12:48:25.110238 scan_static_bus for USB2 port 1 done
967 12:48:25.116894 scan_bus: bus USB2 port 1 finished in 6 msecs
968 12:48:25.120330 USB2 port 2 scanning...
969 12:48:25.123596 scan_static_bus for USB2 port 2
970 12:48:25.126879 scan_static_bus for USB2 port 2 done
971 12:48:25.130291 scan_bus: bus USB2 port 2 finished in 6 msecs
972 12:48:25.133329 USB2 port 4 scanning...
973 12:48:25.136717 scan_static_bus for USB2 port 4
974 12:48:25.140059 scan_static_bus for USB2 port 4 done
975 12:48:25.143125 scan_bus: bus USB2 port 4 finished in 6 msecs
976 12:48:25.146496 USB3 port 1 scanning...
977 12:48:25.150126 scan_static_bus for USB3 port 1
978 12:48:25.153092 scan_static_bus for USB3 port 1 done
979 12:48:25.159918 scan_bus: bus USB3 port 1 finished in 6 msecs
980 12:48:25.163293 scan_static_bus for USB0 port 0 done
981 12:48:25.166653 scan_bus: bus USB0 port 0 finished in 93 msecs
982 12:48:25.170122 scan_static_bus for PCI: 00:14.0 done
983 12:48:25.176449 scan_bus: bus PCI: 00:14.0 finished in 110 msecs
984 12:48:25.179988 PCI: 00:14.3 scanning...
985 12:48:25.183036 scan_static_bus for PCI: 00:14.3
986 12:48:25.183122 GENERIC: 0.0 enabled
987 12:48:25.189964 scan_static_bus for PCI: 00:14.3 done
988 12:48:25.192976 scan_bus: bus PCI: 00:14.3 finished in 9 msecs
989 12:48:25.196435 PCI: 00:15.0 scanning...
990 12:48:25.199690 scan_static_bus for PCI: 00:15.0
991 12:48:25.199775 I2C: 00:1a enabled
992 12:48:25.203119 I2C: 00:31 enabled
993 12:48:25.206173 I2C: 00:32 enabled
994 12:48:25.210122 scan_static_bus for PCI: 00:15.0 done
995 12:48:25.213835 scan_bus: bus PCI: 00:15.0 finished in 12 msecs
996 12:48:25.217190 PCI: 00:15.1 scanning...
997 12:48:25.220437 scan_static_bus for PCI: 00:15.1
998 12:48:25.220518 I2C: 00:10 enabled
999 12:48:25.223759 scan_static_bus for PCI: 00:15.1 done
1000 12:48:25.230065 scan_bus: bus PCI: 00:15.1 finished in 9 msecs
1001 12:48:25.233310 PCI: 00:15.2 scanning...
1002 12:48:25.236942 scan_static_bus for PCI: 00:15.2
1003 12:48:25.240155 scan_static_bus for PCI: 00:15.2 done
1004 12:48:25.243467 scan_bus: bus PCI: 00:15.2 finished in 7 msecs
1005 12:48:25.246866 PCI: 00:15.3 scanning...
1006 12:48:25.250075 scan_static_bus for PCI: 00:15.3
1007 12:48:25.253573 scan_static_bus for PCI: 00:15.3 done
1008 12:48:25.260052 scan_bus: bus PCI: 00:15.3 finished in 7 msecs
1009 12:48:25.260142 PCI: 00:19.1 scanning...
1010 12:48:25.263421 scan_static_bus for PCI: 00:19.1
1011 12:48:25.267125 I2C: 00:15 enabled
1012 12:48:25.270356 scan_static_bus for PCI: 00:19.1 done
1013 12:48:25.276835 scan_bus: bus PCI: 00:19.1 finished in 9 msecs
1014 12:48:25.276929 PCI: 00:1d.0 scanning...
1015 12:48:25.283582 do_pci_scan_bridge for PCI: 00:1d.0
1016 12:48:25.283662 PCI: pci_scan_bus for bus 01
1017 12:48:25.286967 PCI: 01:00.0 [1c5c/174a] enabled
1018 12:48:25.290398 GENERIC: 0.0 enabled
1019 12:48:25.293463 Enabling Common Clock Configuration
1020 12:48:25.300358 L1 Sub-State supported from root port 29
1021 12:48:25.300440 L1 Sub-State Support = 0xf
1022 12:48:25.303686 CommonModeRestoreTime = 0x28
1023 12:48:25.310087 Power On Value = 0x16, Power On Scale = 0x0
1024 12:48:25.310169 ASPM: Enabled L1
1025 12:48:25.313431 PCIe: Max_Payload_Size adjusted to 128
1026 12:48:25.320237 scan_bus: bus PCI: 00:1d.0 finished in 35 msecs
1027 12:48:25.323205 PCI: 00:1e.2 scanning...
1028 12:48:25.326621 scan_generic_bus for PCI: 00:1e.2
1029 12:48:25.326702 SPI: 00 enabled
1030 12:48:25.333422 bus: PCI: 00:1e.2[0]->scan_generic_bus for PCI: 00:1e.2 done
1031 12:48:25.336709 scan_bus: bus PCI: 00:1e.2 finished in 11 msecs
1032 12:48:25.340004 PCI: 00:1e.3 scanning...
1033 12:48:25.343374 scan_generic_bus for PCI: 00:1e.3
1034 12:48:25.346554 SPI: 00 enabled
1035 12:48:25.353052 bus: PCI: 00:1e.3[0]->scan_generic_bus for PCI: 00:1e.3 done
1036 12:48:25.356423 scan_bus: bus PCI: 00:1e.3 finished in 11 msecs
1037 12:48:25.359620 PCI: 00:1f.0 scanning...
1038 12:48:25.362928 scan_static_bus for PCI: 00:1f.0
1039 12:48:25.366187 PNP: 0c09.0 enabled
1040 12:48:25.366271 PNP: 0c09.0 scanning...
1041 12:48:25.369527 scan_static_bus for PNP: 0c09.0
1042 12:48:25.372959 scan_static_bus for PNP: 0c09.0 done
1043 12:48:25.379798 scan_bus: bus PNP: 0c09.0 finished in 6 msecs
1044 12:48:25.383150 scan_static_bus for PCI: 00:1f.0 done
1045 12:48:25.386178 scan_bus: bus PCI: 00:1f.0 finished in 23 msecs
1046 12:48:25.389609 PCI: 00:1f.2 scanning...
1047 12:48:25.393060 scan_static_bus for PCI: 00:1f.2
1048 12:48:25.396000 GENERIC: 0.0 enabled
1049 12:48:25.399371 GENERIC: 0.0 scanning...
1050 12:48:25.402851 scan_static_bus for GENERIC: 0.0
1051 12:48:25.402939 GENERIC: 0.0 enabled
1052 12:48:25.406200 GENERIC: 1.0 enabled
1053 12:48:25.409514 scan_static_bus for GENERIC: 0.0 done
1054 12:48:25.415962 scan_bus: bus GENERIC: 0.0 finished in 11 msecs
1055 12:48:25.419372 scan_static_bus for PCI: 00:1f.2 done
1056 12:48:25.422829 scan_bus: bus PCI: 00:1f.2 finished in 28 msecs
1057 12:48:25.425849 PCI: 00:1f.3 scanning...
1058 12:48:25.429263 scan_static_bus for PCI: 00:1f.3
1059 12:48:25.432639 scan_static_bus for PCI: 00:1f.3 done
1060 12:48:25.439071 scan_bus: bus PCI: 00:1f.3 finished in 7 msecs
1061 12:48:25.439167 PCI: 00:1f.5 scanning...
1062 12:48:25.445771 scan_generic_bus for PCI: 00:1f.5
1063 12:48:25.449072 scan_generic_bus for PCI: 00:1f.5 done
1064 12:48:25.452275 scan_bus: bus PCI: 00:1f.5 finished in 7 msecs
1065 12:48:25.458882 scan_bus: bus DOMAIN: 0000 finished in 717 msecs
1066 12:48:25.462565 scan_static_bus for Root Device done
1067 12:48:25.465708 scan_bus: bus Root Device finished in 736 msecs
1068 12:48:25.465791 done
1069 12:48:25.472391 BS: BS_DEV_ENUMERATE run times (exec / console): 11 / 1296 ms
1070 12:48:25.475603 Chrome EC: UHEPI supported
1071 12:48:25.482476 FMAP: area UNIFIED_MRC_CACHE found @ f00000 (196608 bytes)
1072 12:48:25.488942 SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
1073 12:48:25.492408 SPI flash protection: WPSW=0 SRP0=0
1074 12:48:25.495298 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
1075 12:48:25.502224 BS: BS_DEV_ENUMERATE exit times (exec / console): 1 / 23 ms
1076 12:48:25.505540 found VGA at PCI: 00:02.0
1077 12:48:25.508501 Setting up VGA for PCI: 00:02.0
1078 12:48:25.515458 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
1079 12:48:25.518891 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
1080 12:48:25.521933 Allocating resources...
1081 12:48:25.522025 Reading resources...
1082 12:48:25.528662 Root Device read_resources bus 0 link: 0
1083 12:48:25.532066 DOMAIN: 0000 read_resources bus 0 link: 0
1084 12:48:25.538391 PCI: 00:04.0 read_resources bus 1 link: 0
1085 12:48:25.542022 PCI: 00:04.0 read_resources bus 1 link: 0 done
1086 12:48:25.548556 PCI: 00:0d.0 read_resources bus 0 link: 0
1087 12:48:25.551814 USB0 port 0 read_resources bus 0 link: 0
1088 12:48:25.558269 USB0 port 0 read_resources bus 0 link: 0 done
1089 12:48:25.561483 PCI: 00:0d.0 read_resources bus 0 link: 0 done
1090 12:48:25.564892 PCI: 00:14.0 read_resources bus 0 link: 0
1091 12:48:25.571734 USB0 port 0 read_resources bus 0 link: 0
1092 12:48:25.574936 USB0 port 0 read_resources bus 0 link: 0 done
1093 12:48:25.581644 PCI: 00:14.0 read_resources bus 0 link: 0 done
1094 12:48:25.584907 PCI: 00:14.3 read_resources bus 0 link: 0
1095 12:48:25.591664 PCI: 00:14.3 read_resources bus 0 link: 0 done
1096 12:48:25.594858 PCI: 00:15.0 read_resources bus 0 link: 0
1097 12:48:25.601620 PCI: 00:15.0 read_resources bus 0 link: 0 done
1098 12:48:25.604921 PCI: 00:15.1 read_resources bus 0 link: 0
1099 12:48:25.611782 PCI: 00:15.1 read_resources bus 0 link: 0 done
1100 12:48:25.615114 PCI: 00:19.1 read_resources bus 0 link: 0
1101 12:48:25.622058 PCI: 00:19.1 read_resources bus 0 link: 0 done
1102 12:48:25.625478 PCI: 00:1d.0 read_resources bus 1 link: 0
1103 12:48:25.631966 PCI: 00:1d.0 read_resources bus 1 link: 0 done
1104 12:48:25.635251 PCI: 00:1e.2 read_resources bus 2 link: 0
1105 12:48:25.642135 PCI: 00:1e.2 read_resources bus 2 link: 0 done
1106 12:48:25.645279 PCI: 00:1e.3 read_resources bus 3 link: 0
1107 12:48:25.651999 PCI: 00:1e.3 read_resources bus 3 link: 0 done
1108 12:48:25.655423 PCI: 00:1f.0 read_resources bus 0 link: 0
1109 12:48:25.662002 PCI: 00:1f.0 read_resources bus 0 link: 0 done
1110 12:48:25.665240 PCI: 00:1f.2 read_resources bus 0 link: 0
1111 12:48:25.668494 GENERIC: 0.0 read_resources bus 0 link: 0
1112 12:48:25.675663 GENERIC: 0.0 read_resources bus 0 link: 0 done
1113 12:48:25.679059 PCI: 00:1f.2 read_resources bus 0 link: 0 done
1114 12:48:25.686183 DOMAIN: 0000 read_resources bus 0 link: 0 done
1115 12:48:25.689646 CPU_CLUSTER: 0 read_resources bus 0 link: 0
1116 12:48:25.696111 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
1117 12:48:25.699458 Root Device read_resources bus 0 link: 0 done
1118 12:48:25.702869 Done reading resources.
1119 12:48:25.709375 Show resources in subtree (Root Device)...After reading.
1120 12:48:25.712744 Root Device child on link 0 DOMAIN: 0000
1121 12:48:25.716328 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1122 12:48:25.726047 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1123 12:48:25.736138 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100
1124 12:48:25.739182 PCI: 00:00.0
1125 12:48:25.749333 PCI: 00:00.0 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1126 12:48:25.755823 PCI: 00:00.0 resource base fedc0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1
1127 12:48:25.765828 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1128 12:48:25.775603 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1129 12:48:25.785673 PCI: 00:00.0 resource base fb000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1130 12:48:25.795657 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1131 12:48:25.805534 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 6
1132 12:48:25.812360 PCI: 00:00.0 resource base fed92000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1133 12:48:25.822311 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1134 12:48:25.832203 PCI: 00:00.0 resource base fed85000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9
1135 12:48:25.842083 PCI: 00:00.0 resource base fed86000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
1136 12:48:25.851876 PCI: 00:00.0 resource base fed87000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b
1137 12:48:25.858686 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c
1138 12:48:25.868519 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index d
1139 12:48:25.878612 PCI: 00:00.0 resource base c0000 size 76f40000 align 0 gran 0 limit 0 flags e0004200 index e
1140 12:48:25.888468 PCI: 00:00.0 resource base 77000000 size 8c00000 align 0 gran 0 limit 0 flags f0000200 index f
1141 12:48:25.898289 PCI: 00:00.0 resource base 100000000 size 180400000 align 0 gran 0 limit 0 flags e0004200 index 10
1142 12:48:25.908439 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11
1143 12:48:25.914945 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12
1144 12:48:25.925120 PCI: 00:00.0 resource base f8000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 13
1145 12:48:25.928084 PCI: 00:02.0
1146 12:48:25.938160 PCI: 00:02.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1147 12:48:25.947999 PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
1148 12:48:25.957976 PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
1149 12:48:25.961381 PCI: 00:04.0 child on link 0 GENERIC: 0.0
1150 12:48:25.971324 PCI: 00:04.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 201 index 10
1151 12:48:25.974844 GENERIC: 0.0
1152 12:48:25.974927 PCI: 00:05.0
1153 12:48:25.984517 PCI: 00:05.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1154 12:48:25.991428 PCI: 00:07.0 child on link 0 GENERIC: 0.0
1155 12:48:25.991527 GENERIC: 0.0
1156 12:48:25.994667 PCI: 00:08.0
1157 12:48:26.004560 PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1158 12:48:26.004649 PCI: 00:0a.0
1159 12:48:26.008020 PCI: 00:0d.0 child on link 0 USB0 port 0
1160 12:48:26.017822 PCI: 00:0d.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1161 12:48:26.024525 USB0 port 0 child on link 0 USB3 port 0
1162 12:48:26.024620 USB3 port 0
1163 12:48:26.027827 USB3 port 1
1164 12:48:26.027908 USB3 port 2
1165 12:48:26.031168 USB3 port 3
1166 12:48:26.034543 PCI: 00:14.0 child on link 0 USB0 port 0
1167 12:48:26.044357 PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1168 12:48:26.050974 USB0 port 0 child on link 0 USB2 port 0
1169 12:48:26.051082 USB2 port 0
1170 12:48:26.054257 USB2 port 1
1171 12:48:26.054348 USB2 port 2
1172 12:48:26.057662 USB2 port 3
1173 12:48:26.057758 USB2 port 4
1174 12:48:26.061074 USB2 port 5
1175 12:48:26.061174 USB2 port 6
1176 12:48:26.064409 USB2 port 7
1177 12:48:26.064503 USB2 port 8
1178 12:48:26.067458 USB2 port 9
1179 12:48:26.067553 USB3 port 0
1180 12:48:26.070912 USB3 port 1
1181 12:48:26.074344 USB3 port 2
1182 12:48:26.074437 USB3 port 3
1183 12:48:26.077361 PCI: 00:14.2
1184 12:48:26.087263 PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1185 12:48:26.097441 PCI: 00:14.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
1186 12:48:26.100572 PCI: 00:14.3 child on link 0 GENERIC: 0.0
1187 12:48:26.110840 PCI: 00:14.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1188 12:48:26.110950 GENERIC: 0.0
1189 12:48:26.117551 PCI: 00:15.0 child on link 0 I2C: 00:1a
1190 12:48:26.127380 PCI: 00:15.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1191 12:48:26.127482 I2C: 00:1a
1192 12:48:26.130871 I2C: 00:31
1193 12:48:26.130979 I2C: 00:32
1194 12:48:26.133855 PCI: 00:15.1 child on link 0 I2C: 00:10
1195 12:48:26.143823 PCI: 00:15.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1196 12:48:26.147247 I2C: 00:10
1197 12:48:26.147350 PCI: 00:15.2
1198 12:48:26.157143 PCI: 00:15.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1199 12:48:26.160598 PCI: 00:15.3
1200 12:48:26.170602 PCI: 00:15.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1201 12:48:26.170712 PCI: 00:16.0
1202 12:48:26.180264 PCI: 00:16.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1203 12:48:26.183691 PCI: 00:19.0
1204 12:48:26.187124 PCI: 00:19.1 child on link 0 I2C: 00:15
1205 12:48:26.197027 PCI: 00:19.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1206 12:48:26.200278 I2C: 00:15
1207 12:48:26.203626 PCI: 00:1d.0 child on link 0 GENERIC: 0.0
1208 12:48:26.213627 PCI: 00:1d.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
1209 12:48:26.223443 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
1210 12:48:26.230020 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
1211 12:48:26.233228 GENERIC: 0.0
1212 12:48:26.233307 PCI: 01:00.0
1213 12:48:26.243189 PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1214 12:48:26.253376 PCI: 01:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 18
1215 12:48:26.263402 PCI: 01:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 1c
1216 12:48:26.266406 PCI: 00:1e.0
1217 12:48:26.276606 PCI: 00:1e.0 resource base fe03e000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1218 12:48:26.279684 PCI: 00:1e.2 child on link 0 SPI: 00
1219 12:48:26.289970 PCI: 00:1e.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1220 12:48:26.292985 SPI: 00
1221 12:48:26.296315 PCI: 00:1e.3 child on link 0 SPI: 00
1222 12:48:26.306487 PCI: 00:1e.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1223 12:48:26.306582 SPI: 00
1224 12:48:26.309914 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1225 12:48:26.319512 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1226 12:48:26.322838 PNP: 0c09.0
1227 12:48:26.329456 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1228 12:48:26.336154 PCI: 00:1f.2 child on link 0 GENERIC: 0.0
1229 12:48:26.342725 PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0
1230 12:48:26.352848 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1
1231 12:48:26.359639 GENERIC: 0.0 child on link 0 GENERIC: 0.0
1232 12:48:26.359749 GENERIC: 0.0
1233 12:48:26.362635 GENERIC: 1.0
1234 12:48:26.362731 PCI: 00:1f.3
1235 12:48:26.372882 PCI: 00:1f.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1236 12:48:26.382655 PCI: 00:1f.3 resource base 0 size 100000 align 20 gran 20 limit ffffffffffffffff flags 201 index 20
1237 12:48:26.386135 PCI: 00:1f.5
1238 12:48:26.392513 PCI: 00:1f.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
1239 12:48:26.399116 CPU_CLUSTER: 0 child on link 0 APIC: 00
1240 12:48:26.399217 APIC: 00
1241 12:48:26.402446 APIC: 01
1242 12:48:26.402540 APIC: 05
1243 12:48:26.402614 APIC: 06
1244 12:48:26.405854 APIC: 02
1245 12:48:26.405943 APIC: 03
1246 12:48:26.406019 APIC: 04
1247 12:48:26.409380 APIC: 07
1248 12:48:26.415693 ==== Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) ===
1249 12:48:26.422359 PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff
1250 12:48:26.428968 PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff done
1251 12:48:26.435560 PCI: 00:1d.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
1252 12:48:26.438844 PCI: 01:00.0 10 * [0x0 - 0x3fff] mem
1253 12:48:26.442182 PCI: 01:00.0 18 * [0x4000 - 0x4fff] mem
1254 12:48:26.445595 PCI: 01:00.0 1c * [0x5000 - 0x5fff] mem
1255 12:48:26.455466 PCI: 00:1d.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
1256 12:48:26.462221 PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
1257 12:48:26.468724 PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
1258 12:48:26.475569 === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
1259 12:48:26.482332 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
1260 12:48:26.488676 update_constraints: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
1261 12:48:26.498684 update_constraints: PNP: 0c09.0 00 base 00000800 limit 000009fe io (fixed)
1262 12:48:26.505465 update_constraints: PCI: 00:1f.2 01 base 00001800 limit 000018ff io (fixed)
1263 12:48:26.508742 DOMAIN: 0000: Resource ranges:
1264 12:48:26.512140 * Base: 1000, Size: 800, Tag: 100
1265 12:48:26.515506 * Base: 1900, Size: e700, Tag: 100
1266 12:48:26.521805 PCI: 00:02.0 20 * [0x1000 - 0x103f] limit: 103f io
1267 12:48:26.528780 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
1268 12:48:26.535391 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff
1269 12:48:26.542025 update_constraints: PCI: 00:00.0 00 base c0000000 limit cfffffff mem (fixed)
1270 12:48:26.548751 update_constraints: PCI: 00:00.0 01 base fedc0000 limit feddffff mem (fixed)
1271 12:48:26.558451 update_constraints: PCI: 00:00.0 02 base feda0000 limit feda0fff mem (fixed)
1272 12:48:26.565138 update_constraints: PCI: 00:00.0 03 base feda1000 limit feda1fff mem (fixed)
1273 12:48:26.571626 update_constraints: PCI: 00:00.0 04 base fb000000 limit fb000fff mem (fixed)
1274 12:48:26.581783 update_constraints: PCI: 00:00.0 05 base fed80000 limit fed83fff mem (fixed)
1275 12:48:26.588356 update_constraints: PCI: 00:00.0 06 base fed90000 limit fed90fff mem (fixed)
1276 12:48:26.594821 update_constraints: PCI: 00:00.0 07 base fed92000 limit fed92fff mem (fixed)
1277 12:48:26.605091 update_constraints: PCI: 00:00.0 08 base fed84000 limit fed84fff mem (fixed)
1278 12:48:26.611398 update_constraints: PCI: 00:00.0 09 base fed85000 limit fed85fff mem (fixed)
1279 12:48:26.618019 update_constraints: PCI: 00:00.0 0a base fed86000 limit fed86fff mem (fixed)
1280 12:48:26.627908 update_constraints: PCI: 00:00.0 0b base fed87000 limit fed87fff mem (fixed)
1281 12:48:26.634702 update_constraints: PCI: 00:00.0 0c base fed91000 limit fed91fff mem (fixed)
1282 12:48:26.641265 update_constraints: PCI: 00:00.0 0d base 00000000 limit 0009ffff mem (fixed)
1283 12:48:26.651369 update_constraints: PCI: 00:00.0 0e base 000c0000 limit 76ffffff mem (fixed)
1284 12:48:26.657951 update_constraints: PCI: 00:00.0 0f base 77000000 limit 7fbfffff mem (fixed)
1285 12:48:26.664473 update_constraints: PCI: 00:00.0 10 base 100000000 limit 2803fffff mem (fixed)
1286 12:48:26.674724 update_constraints: PCI: 00:00.0 11 base 000a0000 limit 000bffff mem (fixed)
1287 12:48:26.681169 update_constraints: PCI: 00:00.0 12 base 000c0000 limit 000fffff mem (fixed)
1288 12:48:26.688005 update_constraints: PCI: 00:00.0 13 base f8000000 limit f9ffffff mem (fixed)
1289 12:48:26.697771 update_constraints: PCI: 00:1e.0 10 base fe03e000 limit fe03efff mem (fixed)
1290 12:48:26.704515 update_constraints: PCI: 00:1f.2 00 base fe000000 limit fe00ffff mem (fixed)
1291 12:48:26.707561 DOMAIN: 0000: Resource ranges:
1292 12:48:26.710992 * Base: 7fc00000, Size: 40400000, Tag: 200
1293 12:48:26.717868 * Base: d0000000, Size: 28000000, Tag: 200
1294 12:48:26.721135 * Base: fa000000, Size: 1000000, Tag: 200
1295 12:48:26.724147 * Base: fb001000, Size: 2fff000, Tag: 200
1296 12:48:26.727586 * Base: fe010000, Size: 2e000, Tag: 200
1297 12:48:26.734094 * Base: fe03f000, Size: d41000, Tag: 200
1298 12:48:26.737464 * Base: fed88000, Size: 8000, Tag: 200
1299 12:48:26.740883 * Base: fed93000, Size: d000, Tag: 200
1300 12:48:26.744266 * Base: feda2000, Size: 1e000, Tag: 200
1301 12:48:26.750933 * Base: fede0000, Size: 1220000, Tag: 200
1302 12:48:26.754071 * Base: 280400000, Size: 7d7fc00000, Tag: 100200
1303 12:48:26.760805 PCI: 00:02.0 18 * [0x80000000 - 0x8fffffff] limit: 8fffffff prefmem
1304 12:48:26.767391 PCI: 00:02.0 10 * [0x90000000 - 0x90ffffff] limit: 90ffffff mem
1305 12:48:26.773837 PCI: 00:05.0 10 * [0x91000000 - 0x91ffffff] limit: 91ffffff mem
1306 12:48:26.780485 PCI: 00:1d.0 20 * [0x7fc00000 - 0x7fcfffff] limit: 7fcfffff mem
1307 12:48:26.787334 PCI: 00:1f.3 20 * [0x7fd00000 - 0x7fdfffff] limit: 7fdfffff mem
1308 12:48:26.793890 PCI: 00:04.0 10 * [0x7fe00000 - 0x7fe1ffff] limit: 7fe1ffff mem
1309 12:48:26.800648 PCI: 00:0d.0 10 * [0x7fe20000 - 0x7fe2ffff] limit: 7fe2ffff mem
1310 12:48:26.807147 PCI: 00:14.0 10 * [0x7fe30000 - 0x7fe3ffff] limit: 7fe3ffff mem
1311 12:48:26.813936 PCI: 00:14.2 10 * [0x7fe40000 - 0x7fe43fff] limit: 7fe43fff mem
1312 12:48:26.820632 PCI: 00:14.3 10 * [0x7fe44000 - 0x7fe47fff] limit: 7fe47fff mem
1313 12:48:26.826933 PCI: 00:1f.3 10 * [0x7fe48000 - 0x7fe4bfff] limit: 7fe4bfff mem
1314 12:48:26.833647 PCI: 00:08.0 10 * [0x7fe4c000 - 0x7fe4cfff] limit: 7fe4cfff mem
1315 12:48:26.840429 PCI: 00:14.2 18 * [0x7fe4d000 - 0x7fe4dfff] limit: 7fe4dfff mem
1316 12:48:26.846792 PCI: 00:15.0 10 * [0x7fe4e000 - 0x7fe4efff] limit: 7fe4efff mem
1317 12:48:26.853521 PCI: 00:15.1 10 * [0x7fe4f000 - 0x7fe4ffff] limit: 7fe4ffff mem
1318 12:48:26.860218 PCI: 00:15.2 10 * [0x7fe50000 - 0x7fe50fff] limit: 7fe50fff mem
1319 12:48:26.867002 PCI: 00:15.3 10 * [0x7fe51000 - 0x7fe51fff] limit: 7fe51fff mem
1320 12:48:26.873690 PCI: 00:16.0 10 * [0x7fe52000 - 0x7fe52fff] limit: 7fe52fff mem
1321 12:48:26.880276 PCI: 00:19.1 10 * [0x7fe53000 - 0x7fe53fff] limit: 7fe53fff mem
1322 12:48:26.887107 PCI: 00:1e.2 10 * [0x7fe54000 - 0x7fe54fff] limit: 7fe54fff mem
1323 12:48:26.893372 PCI: 00:1e.3 10 * [0x7fe55000 - 0x7fe55fff] limit: 7fe55fff mem
1324 12:48:26.899937 PCI: 00:1f.5 10 * [0x7fe56000 - 0x7fe56fff] limit: 7fe56fff mem
1325 12:48:26.906808 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff done
1326 12:48:26.916712 PCI: 00:1d.0 mem: base: 7fc00000 size: 100000 align: 20 gran: 20 limit: 7fcfffff
1327 12:48:26.920082 PCI: 00:1d.0: Resource ranges:
1328 12:48:26.923448 * Base: 7fc00000, Size: 100000, Tag: 200
1329 12:48:26.929764 PCI: 01:00.0 10 * [0x7fc00000 - 0x7fc03fff] limit: 7fc03fff mem
1330 12:48:26.936670 PCI: 01:00.0 18 * [0x7fc04000 - 0x7fc04fff] limit: 7fc04fff mem
1331 12:48:26.943158 PCI: 01:00.0 1c * [0x7fc05000 - 0x7fc05fff] limit: 7fc05fff mem
1332 12:48:26.952901 PCI: 00:1d.0 mem: base: 7fc00000 size: 100000 align: 20 gran: 20 limit: 7fcfffff done
1333 12:48:26.959715 === Resource allocator: DOMAIN: 0000 - resource allocation complete ===
1334 12:48:26.963009 Root Device assign_resources, bus 0 link: 0
1335 12:48:26.969714 DOMAIN: 0000 assign_resources, bus 0 link: 0
1336 12:48:26.976192 PCI: 00:02.0 10 <- [0x0090000000 - 0x0090ffffff] size 0x01000000 gran 0x18 mem64
1337 12:48:26.985987 PCI: 00:02.0 18 <- [0x0080000000 - 0x008fffffff] size 0x10000000 gran 0x1c prefmem64
1338 12:48:26.992701 PCI: 00:02.0 20 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io
1339 12:48:26.999311 PCI: 00:04.0 10 <- [0x007fe00000 - 0x007fe1ffff] size 0x00020000 gran 0x11 mem64
1340 12:48:27.005961 PCI: 00:04.0 assign_resources, bus 1 link: 0
1341 12:48:27.009062 PCI: 00:04.0 assign_resources, bus 1 link: 0
1342 12:48:27.019339 PCI: 00:05.0 10 <- [0x0091000000 - 0x0091ffffff] size 0x01000000 gran 0x18 mem64
1343 12:48:27.025636 PCI: 00:08.0 10 <- [0x007fe4c000 - 0x007fe4cfff] size 0x00001000 gran 0x0c mem64
1344 12:48:27.035903 PCI: 00:0d.0 10 <- [0x007fe20000 - 0x007fe2ffff] size 0x00010000 gran 0x10 mem64
1345 12:48:27.038958 PCI: 00:0d.0 assign_resources, bus 0 link: 0
1346 12:48:27.045326 PCI: 00:0d.0 assign_resources, bus 0 link: 0
1347 12:48:27.052111 PCI: 00:14.0 10 <- [0x007fe30000 - 0x007fe3ffff] size 0x00010000 gran 0x10 mem64
1348 12:48:27.055562 PCI: 00:14.0 assign_resources, bus 0 link: 0
1349 12:48:27.062376 PCI: 00:14.0 assign_resources, bus 0 link: 0
1350 12:48:27.068692 PCI: 00:14.2 10 <- [0x007fe40000 - 0x007fe43fff] size 0x00004000 gran 0x0e mem64
1351 12:48:27.078531 PCI: 00:14.2 18 <- [0x007fe4d000 - 0x007fe4dfff] size 0x00001000 gran 0x0c mem64
1352 12:48:27.085449 PCI: 00:14.3 10 <- [0x007fe44000 - 0x007fe47fff] size 0x00004000 gran 0x0e mem64
1353 12:48:27.091982 PCI: 00:14.3 assign_resources, bus 0 link: 0
1354 12:48:27.095143 PCI: 00:14.3 assign_resources, bus 0 link: 0
1355 12:48:27.105124 PCI: 00:15.0 10 <- [0x007fe4e000 - 0x007fe4efff] size 0x00001000 gran 0x0c mem64
1356 12:48:27.108498 PCI: 00:15.0 assign_resources, bus 0 link: 0
1357 12:48:27.111728 PCI: 00:15.0 assign_resources, bus 0 link: 0
1358 12:48:27.121434 PCI: 00:15.1 10 <- [0x007fe4f000 - 0x007fe4ffff] size 0x00001000 gran 0x0c mem64
1359 12:48:27.124930 PCI: 00:15.1 assign_resources, bus 0 link: 0
1360 12:48:27.131455 PCI: 00:15.1 assign_resources, bus 0 link: 0
1361 12:48:27.138280 PCI: 00:15.2 10 <- [0x007fe50000 - 0x007fe50fff] size 0x00001000 gran 0x0c mem64
1362 12:48:27.148046 PCI: 00:15.3 10 <- [0x007fe51000 - 0x007fe51fff] size 0x00001000 gran 0x0c mem64
1363 12:48:27.154835 PCI: 00:16.0 10 <- [0x007fe52000 - 0x007fe52fff] size 0x00001000 gran 0x0c mem64
1364 12:48:27.164382 PCI: 00:19.1 10 <- [0x007fe53000 - 0x007fe53fff] size 0x00001000 gran 0x0c mem64
1365 12:48:27.167835 PCI: 00:19.1 assign_resources, bus 0 link: 0
1366 12:48:27.171058 PCI: 00:19.1 assign_resources, bus 0 link: 0
1367 12:48:27.181013 PCI: 00:1d.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
1368 12:48:27.190931 PCI: 00:1d.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
1369 12:48:27.201024 PCI: 00:1d.0 20 <- [0x007fc00000 - 0x007fcfffff] size 0x00100000 gran 0x14 bus 01 mem
1370 12:48:27.204129 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1371 12:48:27.210922 PCI: 01:00.0 10 <- [0x007fc00000 - 0x007fc03fff] size 0x00004000 gran 0x0e mem64
1372 12:48:27.220602 PCI: 01:00.0 18 <- [0x007fc04000 - 0x007fc04fff] size 0x00001000 gran 0x0c mem
1373 12:48:27.227328 PCI: 01:00.0 1c <- [0x007fc05000 - 0x007fc05fff] size 0x00001000 gran 0x0c mem
1374 12:48:27.233828 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1375 12:48:27.240585 PCI: 00:1e.2 10 <- [0x007fe54000 - 0x007fe54fff] size 0x00001000 gran 0x0c mem64
1376 12:48:27.247083 PCI: 00:1e.2 assign_resources, bus 2 link: 0
1377 12:48:27.250409 PCI: 00:1e.2 assign_resources, bus 2 link: 0
1378 12:48:27.257011 PCI: 00:1e.3 10 <- [0x007fe55000 - 0x007fe55fff] size 0x00001000 gran 0x0c mem64
1379 12:48:27.263586 PCI: 00:1e.3 assign_resources, bus 3 link: 0
1380 12:48:27.267052 PCI: 00:1e.3 assign_resources, bus 3 link: 0
1381 12:48:27.273456 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1382 12:48:27.276810 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1383 12:48:27.283612 LPC: Trying to open IO window from 800 size 1ff
1384 12:48:27.290137 PCI: 00:1f.3 10 <- [0x007fe48000 - 0x007fe4bfff] size 0x00004000 gran 0x0e mem64
1385 12:48:27.300112 PCI: 00:1f.3 20 <- [0x007fd00000 - 0x007fdfffff] size 0x00100000 gran 0x14 mem64
1386 12:48:27.306901 PCI: 00:1f.5 10 <- [0x007fe56000 - 0x007fe56fff] size 0x00001000 gran 0x0c mem
1387 12:48:27.310000 DOMAIN: 0000 assign_resources, bus 0 link: 0
1388 12:48:27.316755 Root Device assign_resources, bus 0 link: 0
1389 12:48:27.320300 Done setting resources.
1390 12:48:27.327005 Show resources in subtree (Root Device)...After assigning values.
1391 12:48:27.330298 Root Device child on link 0 DOMAIN: 0000
1392 12:48:27.333508 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1393 12:48:27.343255 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1394 12:48:27.353238 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100
1395 12:48:27.353335 PCI: 00:00.0
1396 12:48:27.363489 PCI: 00:00.0 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1397 12:48:27.373120 PCI: 00:00.0 resource base fedc0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1
1398 12:48:27.383299 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1399 12:48:27.393215 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1400 12:48:27.403265 PCI: 00:00.0 resource base fb000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1401 12:48:27.409670 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1402 12:48:27.419643 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 6
1403 12:48:27.429517 PCI: 00:00.0 resource base fed92000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1404 12:48:27.439539 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1405 12:48:27.449533 PCI: 00:00.0 resource base fed85000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9
1406 12:48:27.459482 PCI: 00:00.0 resource base fed86000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
1407 12:48:27.465946 PCI: 00:00.0 resource base fed87000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b
1408 12:48:27.475988 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c
1409 12:48:27.486194 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index d
1410 12:48:27.495979 PCI: 00:00.0 resource base c0000 size 76f40000 align 0 gran 0 limit 0 flags e0004200 index e
1411 12:48:27.505849 PCI: 00:00.0 resource base 77000000 size 8c00000 align 0 gran 0 limit 0 flags f0000200 index f
1412 12:48:27.515931 PCI: 00:00.0 resource base 100000000 size 180400000 align 0 gran 0 limit 0 flags e0004200 index 10
1413 12:48:27.522531 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11
1414 12:48:27.532364 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12
1415 12:48:27.542380 PCI: 00:00.0 resource base f8000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 13
1416 12:48:27.545745 PCI: 00:02.0
1417 12:48:27.555664 PCI: 00:02.0 resource base 90000000 size 1000000 align 24 gran 24 limit 90ffffff flags 60000201 index 10
1418 12:48:27.565684 PCI: 00:02.0 resource base 80000000 size 10000000 align 28 gran 28 limit 8fffffff flags 60001201 index 18
1419 12:48:27.575324 PCI: 00:02.0 resource base 1000 size 40 align 6 gran 6 limit 103f flags 60000100 index 20
1420 12:48:27.578669 PCI: 00:04.0 child on link 0 GENERIC: 0.0
1421 12:48:27.588649 PCI: 00:04.0 resource base 7fe00000 size 20000 align 17 gran 17 limit 7fe1ffff flags 60000201 index 10
1422 12:48:27.591971 GENERIC: 0.0
1423 12:48:27.592060 PCI: 00:05.0
1424 12:48:27.605243 PCI: 00:05.0 resource base 91000000 size 1000000 align 24 gran 24 limit 91ffffff flags 60000201 index 10
1425 12:48:27.608828 PCI: 00:07.0 child on link 0 GENERIC: 0.0
1426 12:48:27.611835 GENERIC: 0.0
1427 12:48:27.611916 PCI: 00:08.0
1428 12:48:27.621720 PCI: 00:08.0 resource base 7fe4c000 size 1000 align 12 gran 12 limit 7fe4cfff flags 60000201 index 10
1429 12:48:27.625259 PCI: 00:0a.0
1430 12:48:27.628388 PCI: 00:0d.0 child on link 0 USB0 port 0
1431 12:48:27.638497 PCI: 00:0d.0 resource base 7fe20000 size 10000 align 16 gran 16 limit 7fe2ffff flags 60000201 index 10
1432 12:48:27.642003 USB0 port 0 child on link 0 USB3 port 0
1433 12:48:27.645174 USB3 port 0
1434 12:48:27.648651 USB3 port 1
1435 12:48:27.648736 USB3 port 2
1436 12:48:27.651813 USB3 port 3
1437 12:48:27.655123 PCI: 00:14.0 child on link 0 USB0 port 0
1438 12:48:27.665207 PCI: 00:14.0 resource base 7fe30000 size 10000 align 16 gran 16 limit 7fe3ffff flags 60000201 index 10
1439 12:48:27.668234 USB0 port 0 child on link 0 USB2 port 0
1440 12:48:27.671706 USB2 port 0
1441 12:48:27.671796 USB2 port 1
1442 12:48:27.675104 USB2 port 2
1443 12:48:27.675201 USB2 port 3
1444 12:48:27.678482 USB2 port 4
1445 12:48:27.681645 USB2 port 5
1446 12:48:27.681733 USB2 port 6
1447 12:48:27.685039 USB2 port 7
1448 12:48:27.685117 USB2 port 8
1449 12:48:27.688497 USB2 port 9
1450 12:48:27.688572 USB3 port 0
1451 12:48:27.691818 USB3 port 1
1452 12:48:27.691903 USB3 port 2
1453 12:48:27.695066 USB3 port 3
1454 12:48:27.695143 PCI: 00:14.2
1455 12:48:27.704991 PCI: 00:14.2 resource base 7fe40000 size 4000 align 14 gran 14 limit 7fe43fff flags 60000201 index 10
1456 12:48:27.718271 PCI: 00:14.2 resource base 7fe4d000 size 1000 align 12 gran 12 limit 7fe4dfff flags 60000201 index 18
1457 12:48:27.721594 PCI: 00:14.3 child on link 0 GENERIC: 0.0
1458 12:48:27.731600 PCI: 00:14.3 resource base 7fe44000 size 4000 align 14 gran 14 limit 7fe47fff flags 60000201 index 10
1459 12:48:27.734582 GENERIC: 0.0
1460 12:48:27.738184 PCI: 00:15.0 child on link 0 I2C: 00:1a
1461 12:48:27.747887 PCI: 00:15.0 resource base 7fe4e000 size 1000 align 12 gran 12 limit 7fe4efff flags 60000201 index 10
1462 12:48:27.747980 I2C: 00:1a
1463 12:48:27.751404 I2C: 00:31
1464 12:48:27.751493 I2C: 00:32
1465 12:48:27.757752 PCI: 00:15.1 child on link 0 I2C: 00:10
1466 12:48:27.768005 PCI: 00:15.1 resource base 7fe4f000 size 1000 align 12 gran 12 limit 7fe4ffff flags 60000201 index 10
1467 12:48:27.768109 I2C: 00:10
1468 12:48:27.771257 PCI: 00:15.2
1469 12:48:27.781019 PCI: 00:15.2 resource base 7fe50000 size 1000 align 12 gran 12 limit 7fe50fff flags 60000201 index 10
1470 12:48:27.781115 PCI: 00:15.3
1471 12:48:27.794360 PCI: 00:15.3 resource base 7fe51000 size 1000 align 12 gran 12 limit 7fe51fff flags 60000201 index 10
1472 12:48:27.794454 PCI: 00:16.0
1473 12:48:27.804627 PCI: 00:16.0 resource base 7fe52000 size 1000 align 12 gran 12 limit 7fe52fff flags 60000201 index 10
1474 12:48:27.807593 PCI: 00:19.0
1475 12:48:27.811072 PCI: 00:19.1 child on link 0 I2C: 00:15
1476 12:48:27.821068 PCI: 00:19.1 resource base 7fe53000 size 1000 align 12 gran 12 limit 7fe53fff flags 60000201 index 10
1477 12:48:27.824356 I2C: 00:15
1478 12:48:27.827664 PCI: 00:1d.0 child on link 0 GENERIC: 0.0
1479 12:48:27.837600 PCI: 00:1d.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 20080102 index 1c
1480 12:48:27.847782 PCI: 00:1d.0 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24
1481 12:48:27.857534 PCI: 00:1d.0 resource base 7fc00000 size 100000 align 20 gran 20 limit 7fcfffff flags 60080202 index 20
1482 12:48:27.860766 GENERIC: 0.0
1483 12:48:27.860850 PCI: 01:00.0
1484 12:48:27.874217 PCI: 01:00.0 resource base 7fc00000 size 4000 align 14 gran 14 limit 7fc03fff flags 60000201 index 10
1485 12:48:27.884323 PCI: 01:00.0 resource base 7fc04000 size 1000 align 12 gran 12 limit 7fc04fff flags 60000200 index 18
1486 12:48:27.894001 PCI: 01:00.0 resource base 7fc05000 size 1000 align 12 gran 12 limit 7fc05fff flags 60000200 index 1c
1487 12:48:27.894097 PCI: 00:1e.0
1488 12:48:27.907105 PCI: 00:1e.0 resource base fe03e000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1489 12:48:27.910531 PCI: 00:1e.2 child on link 0 SPI: 00
1490 12:48:27.920599 PCI: 00:1e.2 resource base 7fe54000 size 1000 align 12 gran 12 limit 7fe54fff flags 60000201 index 10
1491 12:48:27.920690 SPI: 00
1492 12:48:27.927135 PCI: 00:1e.3 child on link 0 SPI: 00
1493 12:48:27.937056 PCI: 00:1e.3 resource base 7fe55000 size 1000 align 12 gran 12 limit 7fe55fff flags 60000201 index 10
1494 12:48:27.937163 SPI: 00
1495 12:48:27.940549 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1496 12:48:27.950342 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1497 12:48:27.953667 PNP: 0c09.0
1498 12:48:27.960147 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1499 12:48:27.966871 PCI: 00:1f.2 child on link 0 GENERIC: 0.0
1500 12:48:27.973715 PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0
1501 12:48:27.983663 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1
1502 12:48:27.990352 GENERIC: 0.0 child on link 0 GENERIC: 0.0
1503 12:48:27.990452 GENERIC: 0.0
1504 12:48:27.993324 GENERIC: 1.0
1505 12:48:27.993405 PCI: 00:1f.3
1506 12:48:28.003480 PCI: 00:1f.3 resource base 7fe48000 size 4000 align 14 gran 14 limit 7fe4bfff flags 60000201 index 10
1507 12:48:28.013198 PCI: 00:1f.3 resource base 7fd00000 size 100000 align 20 gran 20 limit 7fdfffff flags 60000201 index 20
1508 12:48:28.016581 PCI: 00:1f.5
1509 12:48:28.026608 PCI: 00:1f.5 resource base 7fe56000 size 1000 align 12 gran 12 limit 7fe56fff flags 60000200 index 10
1510 12:48:28.030050 CPU_CLUSTER: 0 child on link 0 APIC: 00
1511 12:48:28.033380 APIC: 00
1512 12:48:28.033464 APIC: 01
1513 12:48:28.036601 APIC: 05
1514 12:48:28.036692 APIC: 06
1515 12:48:28.036761 APIC: 02
1516 12:48:28.040075 APIC: 03
1517 12:48:28.040168 APIC: 04
1518 12:48:28.040238 APIC: 07
1519 12:48:28.043441 Done allocating resources.
1520 12:48:28.049819 BS: BS_DEV_RESOURCES run times (exec / console): 28 / 2514 ms
1521 12:48:28.056417 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
1522 12:48:28.059855 Configure GPIOs for I2S audio on UP4.
1523 12:48:28.066301 BS: BS_DEV_ENABLE entry times (exec / console): 2 / 9 ms
1524 12:48:28.069638 Enabling resources...
1525 12:48:28.073057 PCI: 00:00.0 subsystem <- 8086/9a12
1526 12:48:28.076467 PCI: 00:00.0 cmd <- 06
1527 12:48:28.079781 PCI: 00:02.0 subsystem <- 8086/9a40
1528 12:48:28.082967 PCI: 00:02.0 cmd <- 03
1529 12:48:28.086507 PCI: 00:04.0 subsystem <- 8086/9a03
1530 12:48:28.089478 PCI: 00:04.0 cmd <- 02
1531 12:48:28.093133 PCI: 00:05.0 subsystem <- 8086/9a19
1532 12:48:28.093222 PCI: 00:05.0 cmd <- 02
1533 12:48:28.099325 PCI: 00:08.0 subsystem <- 8086/9a11
1534 12:48:28.099416 PCI: 00:08.0 cmd <- 06
1535 12:48:28.102886 PCI: 00:0d.0 subsystem <- 8086/9a13
1536 12:48:28.106252 PCI: 00:0d.0 cmd <- 02
1537 12:48:28.109373 PCI: 00:14.0 subsystem <- 8086/a0ed
1538 12:48:28.112914 PCI: 00:14.0 cmd <- 02
1539 12:48:28.115986 PCI: 00:14.2 subsystem <- 8086/a0ef
1540 12:48:28.119445 PCI: 00:14.2 cmd <- 02
1541 12:48:28.122727 PCI: 00:14.3 subsystem <- 8086/a0f0
1542 12:48:28.126098 PCI: 00:14.3 cmd <- 02
1543 12:48:28.129214 PCI: 00:15.0 subsystem <- 8086/a0e8
1544 12:48:28.132576 PCI: 00:15.0 cmd <- 02
1545 12:48:28.136113 PCI: 00:15.1 subsystem <- 8086/a0e9
1546 12:48:28.139355 PCI: 00:15.1 cmd <- 02
1547 12:48:28.142578 PCI: 00:15.2 subsystem <- 8086/a0ea
1548 12:48:28.142662 PCI: 00:15.2 cmd <- 02
1549 12:48:28.149001 PCI: 00:15.3 subsystem <- 8086/a0eb
1550 12:48:28.149085 PCI: 00:15.3 cmd <- 02
1551 12:48:28.152495 PCI: 00:16.0 subsystem <- 8086/a0e0
1552 12:48:28.155882 PCI: 00:16.0 cmd <- 02
1553 12:48:28.159128 PCI: 00:19.1 subsystem <- 8086/a0c6
1554 12:48:28.162539 PCI: 00:19.1 cmd <- 02
1555 12:48:28.166029 PCI: 00:1d.0 bridge ctrl <- 0013
1556 12:48:28.168999 PCI: 00:1d.0 subsystem <- 8086/a0b0
1557 12:48:28.172314 PCI: 00:1d.0 cmd <- 06
1558 12:48:28.175820 PCI: 00:1e.0 subsystem <- 8086/a0a8
1559 12:48:28.179013 PCI: 00:1e.0 cmd <- 06
1560 12:48:28.182558 PCI: 00:1e.2 subsystem <- 8086/a0aa
1561 12:48:28.185815 PCI: 00:1e.2 cmd <- 06
1562 12:48:28.188957 PCI: 00:1e.3 subsystem <- 8086/a0ab
1563 12:48:28.192108 PCI: 00:1e.3 cmd <- 02
1564 12:48:28.195361 PCI: 00:1f.0 subsystem <- 8086/a087
1565 12:48:28.195448 PCI: 00:1f.0 cmd <- 407
1566 12:48:28.202225 PCI: 00:1f.3 subsystem <- 8086/a0c8
1567 12:48:28.202312 PCI: 00:1f.3 cmd <- 02
1568 12:48:28.205431 PCI: 00:1f.5 subsystem <- 8086/a0a4
1569 12:48:28.209011 PCI: 00:1f.5 cmd <- 406
1570 12:48:28.214079 PCI: 01:00.0 cmd <- 02
1571 12:48:28.218260 done.
1572 12:48:28.221637 BS: BS_DEV_ENABLE run times (exec / console): 10 / 140 ms
1573 12:48:28.225005 Initializing devices...
1574 12:48:28.228419 Root Device init
1575 12:48:28.231378 Chrome EC: Set SMI mask to 0x0000000000000000
1576 12:48:28.238096 Chrome EC: clear events_b mask to 0x0000000000000000
1577 12:48:28.244710 Chrome EC: Set S5 LAZY WAKE mask to 0x0000000000000006
1578 12:48:28.248085 Chrome EC: Set S3 LAZY WAKE mask to 0x000000001800101e
1579 12:48:28.254534 Chrome EC: Set S0iX LAZY WAKE mask to 0x000000001800101e
1580 12:48:28.261272 Chrome EC: Set WAKE mask to 0x0000000000000000
1581 12:48:28.264600 fw_config match found: DB_USB=USB3_ACTIVE
1582 12:48:28.271453 Configure Right Type-C port orientation for retimer
1583 12:48:28.274497 Root Device init finished in 42 msecs
1584 12:48:28.278011 PCI: 00:00.0 init
1585 12:48:28.281298 CPU TDP = 9 Watts
1586 12:48:28.281381 CPU PL1 = 9 Watts
1587 12:48:28.284609 CPU PL2 = 40 Watts
1588 12:48:28.284692 CPU PL4 = 83 Watts
1589 12:48:28.287835 PCI: 00:00.0 init finished in 8 msecs
1590 12:48:28.291413 PCI: 00:02.0 init
1591 12:48:28.294721 GMA: Found VBT in CBFS
1592 12:48:28.297928 GMA: Found valid VBT in CBFS
1593 12:48:28.301178 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
1594 12:48:28.311132 x_res x y_res: 1920 x 1080, size: 8294400 at 0x80000000
1595 12:48:28.314863 PCI: 00:02.0 init finished in 18 msecs
1596 12:48:28.317753 PCI: 00:05.0 init
1597 12:48:28.321415 PCI: 00:05.0 init finished in 0 msecs
1598 12:48:28.321504 PCI: 00:08.0 init
1599 12:48:28.327873 PCI: 00:08.0 init finished in 0 msecs
1600 12:48:28.327963 PCI: 00:14.0 init
1601 12:48:28.334385 PCI: 00:14.0 init finished in 0 msecs
1602 12:48:28.334475 PCI: 00:14.2 init
1603 12:48:28.337882 PCI: 00:14.2 init finished in 0 msecs
1604 12:48:28.341662 PCI: 00:15.0 init
1605 12:48:28.344661 I2C bus 0 version 0x3230302a
1606 12:48:28.348278 DW I2C bus 0 at 0x7fe4e000 (400 KHz)
1607 12:48:28.351643 PCI: 00:15.0 init finished in 6 msecs
1608 12:48:28.354626 PCI: 00:15.1 init
1609 12:48:28.358048 I2C bus 1 version 0x3230302a
1610 12:48:28.361477 DW I2C bus 1 at 0x7fe4f000 (400 KHz)
1611 12:48:28.364559 PCI: 00:15.1 init finished in 6 msecs
1612 12:48:28.367918 PCI: 00:15.2 init
1613 12:48:28.371282 I2C bus 2 version 0x3230302a
1614 12:48:28.374368 DW I2C bus 2 at 0x7fe50000 (400 KHz)
1615 12:48:28.377771 PCI: 00:15.2 init finished in 6 msecs
1616 12:48:28.381248 PCI: 00:15.3 init
1617 12:48:28.381338 I2C bus 3 version 0x3230302a
1618 12:48:28.387574 DW I2C bus 3 at 0x7fe51000 (400 KHz)
1619 12:48:28.390908 PCI: 00:15.3 init finished in 6 msecs
1620 12:48:28.390998 PCI: 00:16.0 init
1621 12:48:28.394316 PCI: 00:16.0 init finished in 0 msecs
1622 12:48:28.398086 PCI: 00:19.1 init
1623 12:48:28.401504 I2C bus 5 version 0x3230302a
1624 12:48:28.404774 DW I2C bus 5 at 0x7fe53000 (400 KHz)
1625 12:48:28.408158 PCI: 00:19.1 init finished in 6 msecs
1626 12:48:28.411717 PCI: 00:1d.0 init
1627 12:48:28.415060 Initializing PCH PCIe bridge.
1628 12:48:28.418383 PCI: 00:1d.0 init finished in 3 msecs
1629 12:48:28.421596 PCI: 00:1f.0 init
1630 12:48:28.425088 IOAPIC: Initializing IOAPIC at 0xfec00000
1631 12:48:28.431417 IOAPIC: Bootstrap Processor Local APIC = 0x00
1632 12:48:28.431506 IOAPIC: ID = 0x02
1633 12:48:28.434884 IOAPIC: Dumping registers
1634 12:48:28.438174 reg 0x0000: 0x02000000
1635 12:48:28.438262 reg 0x0001: 0x00770020
1636 12:48:28.441550 reg 0x0002: 0x00000000
1637 12:48:28.444608 PCI: 00:1f.0 init finished in 21 msecs
1638 12:48:28.448015 PCI: 00:1f.2 init
1639 12:48:28.451645 Disabling ACPI via APMC.
1640 12:48:28.455193 APMC done.
1641 12:48:28.458175 PCI: 00:1f.2 init finished in 5 msecs
1642 12:48:28.469191 PCI: 01:00.0 init
1643 12:48:28.472596 PCI: 01:00.0 init finished in 0 msecs
1644 12:48:28.475670 PNP: 0c09.0 init
1645 12:48:28.479061 Google Chrome EC uptime: 8.409 seconds
1646 12:48:28.485581 Google Chrome AP resets since EC boot: 1
1647 12:48:28.488985 Google Chrome most recent AP reset causes:
1648 12:48:28.492295 0.347: 32775 shutdown: entering G3
1649 12:48:28.499006 Google Chrome EC reset flags at last EC boot: reset-pin | sysjump
1650 12:48:28.502359 PNP: 0c09.0 init finished in 22 msecs
1651 12:48:28.508072 Devices initialized
1652 12:48:28.511132 Show all devs... After init.
1653 12:48:28.514451 Root Device: enabled 1
1654 12:48:28.514548 DOMAIN: 0000: enabled 1
1655 12:48:28.518015 CPU_CLUSTER: 0: enabled 1
1656 12:48:28.521308 PCI: 00:00.0: enabled 1
1657 12:48:28.524572 PCI: 00:02.0: enabled 1
1658 12:48:28.524650 PCI: 00:04.0: enabled 1
1659 12:48:28.527792 PCI: 00:05.0: enabled 1
1660 12:48:28.531236 PCI: 00:06.0: enabled 0
1661 12:48:28.534527 PCI: 00:07.0: enabled 0
1662 12:48:28.534606 PCI: 00:07.1: enabled 0
1663 12:48:28.537834 PCI: 00:07.2: enabled 0
1664 12:48:28.541054 PCI: 00:07.3: enabled 0
1665 12:48:28.544454 PCI: 00:08.0: enabled 1
1666 12:48:28.544538 PCI: 00:09.0: enabled 0
1667 12:48:28.547997 PCI: 00:0a.0: enabled 0
1668 12:48:28.550991 PCI: 00:0d.0: enabled 1
1669 12:48:28.554400 PCI: 00:0d.1: enabled 0
1670 12:48:28.554531 PCI: 00:0d.2: enabled 0
1671 12:48:28.557952 PCI: 00:0d.3: enabled 0
1672 12:48:28.561132 PCI: 00:0e.0: enabled 0
1673 12:48:28.561217 PCI: 00:10.2: enabled 1
1674 12:48:28.564443 PCI: 00:10.6: enabled 0
1675 12:48:28.567808 PCI: 00:10.7: enabled 0
1676 12:48:28.571211 PCI: 00:12.0: enabled 0
1677 12:48:28.571320 PCI: 00:12.6: enabled 0
1678 12:48:28.574535 PCI: 00:13.0: enabled 0
1679 12:48:28.577601 PCI: 00:14.0: enabled 1
1680 12:48:28.581025 PCI: 00:14.1: enabled 0
1681 12:48:28.581140 PCI: 00:14.2: enabled 1
1682 12:48:28.584575 PCI: 00:14.3: enabled 1
1683 12:48:28.587548 PCI: 00:15.0: enabled 1
1684 12:48:28.591039 PCI: 00:15.1: enabled 1
1685 12:48:28.591118 PCI: 00:15.2: enabled 1
1686 12:48:28.594316 PCI: 00:15.3: enabled 1
1687 12:48:28.597718 PCI: 00:16.0: enabled 1
1688 12:48:28.597814 PCI: 00:16.1: enabled 0
1689 12:48:28.601083 PCI: 00:16.2: enabled 0
1690 12:48:28.604052 PCI: 00:16.3: enabled 0
1691 12:48:28.607397 PCI: 00:16.4: enabled 0
1692 12:48:28.607478 PCI: 00:16.5: enabled 0
1693 12:48:28.610876 PCI: 00:17.0: enabled 0
1694 12:48:28.614347 PCI: 00:19.0: enabled 0
1695 12:48:28.617603 PCI: 00:19.1: enabled 1
1696 12:48:28.617683 PCI: 00:19.2: enabled 0
1697 12:48:28.620900 PCI: 00:1c.0: enabled 1
1698 12:48:28.623986 PCI: 00:1c.1: enabled 0
1699 12:48:28.627282 PCI: 00:1c.2: enabled 0
1700 12:48:28.627362 PCI: 00:1c.3: enabled 0
1701 12:48:28.630633 PCI: 00:1c.4: enabled 0
1702 12:48:28.634030 PCI: 00:1c.5: enabled 0
1703 12:48:28.637457 PCI: 00:1c.6: enabled 1
1704 12:48:28.637537 PCI: 00:1c.7: enabled 0
1705 12:48:28.640804 PCI: 00:1d.0: enabled 1
1706 12:48:28.644075 PCI: 00:1d.1: enabled 0
1707 12:48:28.644155 PCI: 00:1d.2: enabled 1
1708 12:48:28.647313 PCI: 00:1d.3: enabled 0
1709 12:48:28.650762 PCI: 00:1e.0: enabled 1
1710 12:48:28.654142 PCI: 00:1e.1: enabled 0
1711 12:48:28.654232 PCI: 00:1e.2: enabled 1
1712 12:48:28.657204 PCI: 00:1e.3: enabled 1
1713 12:48:28.660711 PCI: 00:1f.0: enabled 1
1714 12:48:28.663947 PCI: 00:1f.1: enabled 0
1715 12:48:28.664031 PCI: 00:1f.2: enabled 1
1716 12:48:28.667544 PCI: 00:1f.3: enabled 1
1717 12:48:28.670863 PCI: 00:1f.4: enabled 0
1718 12:48:28.673967 PCI: 00:1f.5: enabled 1
1719 12:48:28.674046 PCI: 00:1f.6: enabled 0
1720 12:48:28.677302 PCI: 00:1f.7: enabled 0
1721 12:48:28.680596 APIC: 00: enabled 1
1722 12:48:28.680681 GENERIC: 0.0: enabled 1
1723 12:48:28.683974 GENERIC: 0.0: enabled 1
1724 12:48:28.687381 GENERIC: 1.0: enabled 1
1725 12:48:28.690822 GENERIC: 0.0: enabled 1
1726 12:48:28.690899 GENERIC: 1.0: enabled 1
1727 12:48:28.693927 USB0 port 0: enabled 1
1728 12:48:28.697348 GENERIC: 0.0: enabled 1
1729 12:48:28.697423 USB0 port 0: enabled 1
1730 12:48:28.700461 GENERIC: 0.0: enabled 1
1731 12:48:28.703829 I2C: 00:1a: enabled 1
1732 12:48:28.707278 I2C: 00:31: enabled 1
1733 12:48:28.707354 I2C: 00:32: enabled 1
1734 12:48:28.710318 I2C: 00:10: enabled 1
1735 12:48:28.713736 I2C: 00:15: enabled 1
1736 12:48:28.713822 GENERIC: 0.0: enabled 0
1737 12:48:28.717160 GENERIC: 1.0: enabled 0
1738 12:48:28.720407 GENERIC: 0.0: enabled 1
1739 12:48:28.720491 SPI: 00: enabled 1
1740 12:48:28.723659 SPI: 00: enabled 1
1741 12:48:28.727007 PNP: 0c09.0: enabled 1
1742 12:48:28.727095 GENERIC: 0.0: enabled 1
1743 12:48:28.730265 USB3 port 0: enabled 1
1744 12:48:28.734030 USB3 port 1: enabled 1
1745 12:48:28.737107 USB3 port 2: enabled 0
1746 12:48:28.737190 USB3 port 3: enabled 0
1747 12:48:28.740399 USB2 port 0: enabled 0
1748 12:48:28.743919 USB2 port 1: enabled 1
1749 12:48:28.744008 USB2 port 2: enabled 1
1750 12:48:28.747065 USB2 port 3: enabled 0
1751 12:48:28.750046 USB2 port 4: enabled 1
1752 12:48:28.750128 USB2 port 5: enabled 0
1753 12:48:28.753696 USB2 port 6: enabled 0
1754 12:48:28.756683 USB2 port 7: enabled 0
1755 12:48:28.760199 USB2 port 8: enabled 0
1756 12:48:28.760286 USB2 port 9: enabled 0
1757 12:48:28.763554 USB3 port 0: enabled 0
1758 12:48:28.766968 USB3 port 1: enabled 1
1759 12:48:28.767056 USB3 port 2: enabled 0
1760 12:48:28.770256 USB3 port 3: enabled 0
1761 12:48:28.773406 GENERIC: 0.0: enabled 1
1762 12:48:28.776695 GENERIC: 1.0: enabled 1
1763 12:48:28.776781 APIC: 01: enabled 1
1764 12:48:28.780103 APIC: 05: enabled 1
1765 12:48:28.780183 APIC: 06: enabled 1
1766 12:48:28.783455 APIC: 02: enabled 1
1767 12:48:28.786903 APIC: 03: enabled 1
1768 12:48:28.786991 APIC: 04: enabled 1
1769 12:48:28.789889 APIC: 07: enabled 1
1770 12:48:28.793517 PCI: 01:00.0: enabled 1
1771 12:48:28.796523 BS: BS_DEV_INIT run times (exec / console): 29 / 540 ms
1772 12:48:28.803371 FMAP: area RW_ELOG found @ f30000 (4096 bytes)
1773 12:48:28.806675 ELOG: NV offset 0xf30000 size 0x1000
1774 12:48:28.813172 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
1775 12:48:28.819718 ELOG: Event(17) added with size 13 at 2023-03-13 12:48:28 UTC
1776 12:48:28.826380 ELOG: Event(92) added with size 9 at 2023-03-13 12:48:28 UTC
1777 12:48:28.832822 ELOG: Event(93) added with size 9 at 2023-03-13 12:48:28 UTC
1778 12:48:28.839484 ELOG: Event(9E) added with size 10 at 2023-03-13 12:48:28 UTC
1779 12:48:28.846022 ELOG: Event(9F) added with size 14 at 2023-03-13 12:48:28 UTC
1780 12:48:28.852597 BS: BS_DEV_INIT exit times (exec / console): 3 / 45 ms
1781 12:48:28.859278 ELOG: Event(A1) added with size 10 at 2023-03-13 12:48:28 UTC
1782 12:48:28.862662 elog_add_boot_reason: Logged recovery mode boot, reason: 0x1b
1783 12:48:28.869404 BS: BS_POST_DEVICE entry times (exec / console): 0 / 12 ms
1784 12:48:28.872414 Finalize devices...
1785 12:48:28.872495 Devices finalized
1786 12:48:28.879147 BS: BS_POST_DEVICE run times (exec / console): 0 / 4 ms
1787 12:48:28.885821 FMAP: area RW_NVRAM found @ f37000 (24576 bytes)
1788 12:48:28.889144 BS: BS_POST_DEVICE exit times (exec / console): 0 / 5 ms
1789 12:48:28.895995 ME: HFSTS1 : 0x80030055
1790 12:48:28.899060 ME: HFSTS2 : 0x30280116
1791 12:48:28.902446 ME: HFSTS3 : 0x00000050
1792 12:48:28.909240 ME: HFSTS4 : 0x00004000
1793 12:48:28.912573 ME: HFSTS5 : 0x00000000
1794 12:48:28.915960 ME: HFSTS6 : 0x00400006
1795 12:48:28.922284 ME: Manufacturing Mode : YES
1796 12:48:28.925682 ME: SPI Protection Mode Enabled : NO
1797 12:48:28.929123 ME: FW Partition Table : OK
1798 12:48:28.932126 ME: Bringup Loader Failure : NO
1799 12:48:28.935542 ME: Firmware Init Complete : NO
1800 12:48:28.938941 ME: Boot Options Present : NO
1801 12:48:28.942127 ME: Update In Progress : NO
1802 12:48:28.945451 ME: D0i3 Support : YES
1803 12:48:28.952141 ME: Low Power State Enabled : NO
1804 12:48:28.955610 ME: CPU Replaced : YES
1805 12:48:28.958941 ME: CPU Replacement Valid : YES
1806 12:48:28.962351 ME: Current Working State : 5
1807 12:48:28.965287 ME: Current Operation State : 1
1808 12:48:28.968657 ME: Current Operation Mode : 3
1809 12:48:28.972007 ME: Error Code : 0
1810 12:48:28.975482 ME: Enhanced Debug Mode : NO
1811 12:48:28.982115 ME: CPU Debug Disabled : YES
1812 12:48:28.985473 ME: TXT Support : NO
1813 12:48:28.988934 BS: BS_OS_RESUME_CHECK exit times (exec / console): 0 / 94 ms
1814 12:48:28.998740 CBFS: Found 'fallback/dsdt.aml' @0x72f80 size 0x5a67 in mcache @0x76c4c1c4
1815 12:48:29.002226 CBFS: 'fallback/slic' not found.
1816 12:48:29.005305 ACPI: Writing ACPI tables at 76b01000.
1817 12:48:29.005394 ACPI: * FACS
1818 12:48:29.008677 ACPI: * DSDT
1819 12:48:29.012007 Ramoops buffer: 0x100000@0x76a00000.
1820 12:48:29.018645 FMAP: area RO_VPD found @ 1800000 (16384 bytes)
1821 12:48:29.022090 FMAP: area RW_VPD found @ f35000 (8192 bytes)
1822 12:48:29.025481 Google Chrome EC: version:
1823 12:48:29.028524 ro: voema_v2.0.7540-147f8d37d1
1824 12:48:29.032085 rw: voema_v2.0.7540-147f8d37d1
1825 12:48:29.035406 running image: 2
1826 12:48:29.038413 PCI space above 4GB MMIO is at 0x280400000, len = 0x7d7fc00000
1827 12:48:29.043942 ACPI: * FADT
1828 12:48:29.044032 SCI is IRQ9
1829 12:48:29.050355 ACPI: added table 1/32, length now 40
1830 12:48:29.050446 ACPI: * SSDT
1831 12:48:29.053633 Found 1 CPU(s) with 8 core(s) each.
1832 12:48:29.060420 \_SB.PCI0.PMC: Intel Tigerlake at PCI: 00:1f.2
1833 12:48:29.063611 \_SB.DPTF: Intel DPTF at GENERIC: 0.0
1834 12:48:29.067021 \_SB.PCI0.CNVW: WIFI Device GENERIC: 0.0
1835 12:48:29.070351 \_SB.PCI0.I2C0.RT58: Headset Codec at I2C: 00:1a
1836 12:48:29.076805 \_SB.PCI0.I2C0.MAXR: Maxim MAX98373 Codec address 031h
1837 12:48:29.083623 \_SB.PCI0.I2C0.MAXL: Maxim MAX98373 Codec address 032h
1838 12:48:29.086937 \_SB.PCI0.I2C1.H010: ELAN Touchscreen at I2C: 00:10
1839 12:48:29.093693 \_SB.PCI0.I2C5.D015: ELAN Touchpad at I2C: 00:15
1840 12:48:29.100178 \_SB.PCI0.RP09: Enable RTD3 for PCI: 00:1d.0 (Intel PCIe Runtime D3)
1841 12:48:29.103649 \_SB.PCI0.RP09: Added StorageD3Enable property
1842 12:48:29.107025 \_SB.PCI0.SPI0.S001: SPI Device at SPI: 00
1843 12:48:29.113444 \_SB.PCI0.SPI1.CRFP: SPI Device at SPI: 00
1844 12:48:29.120215 PS2K: Physmap: [ EA E7 91 92 93 94 95 A0 AE B0 ]
1845 12:48:29.123526 PS2K: Passing 80 keymaps to kernel
1846 12:48:29.129991 \_SB.PCI0.TXHC.RHUB.SS01: USB3 Type-C Port C0 (MLB) at USB3 port 0
1847 12:48:29.136892 \_SB.PCI0.TXHC.RHUB.SS02: USB3 Type-C Port C1 (DB) at USB3 port 1
1848 12:48:29.143328 \_SB.PCI0.XHCI.RHUB.HS02: USB2 Type-A Port A1 (DB) at USB2 port 1
1849 12:48:29.149819 \_SB.PCI0.XHCI.RHUB.HS03: USB2 Type-C Port C1 (DB) at USB2 port 2
1850 12:48:29.156561 \_SB.PCI0.XHCI.RHUB.HS05: USB2 Type-C Port C0 (MLB) at USB2 port 4
1851 12:48:29.163316 \_SB.PCI0.XHCI.RHUB.SS02: USB3 Type-A Port A1 (DB) at USB3 port 1
1852 12:48:29.169970 \_SB.PCI0.PMC.MUX.CON0: Intel PMC MUX CONN Driver at GENERIC: 0.0
1853 12:48:29.173185 \_SB.PCI0.PMC.MUX.CON1: Intel PMC MUX CONN Driver at GENERIC: 1.0
1854 12:48:29.179705 ACPI: added table 2/32, length now 44
1855 12:48:29.179794 ACPI: * MCFG
1856 12:48:29.183193 ACPI: added table 3/32, length now 48
1857 12:48:29.186497 ACPI: * TPM2
1858 12:48:29.189901 TPM2 log created at 0x769f0000
1859 12:48:29.193123 ACPI: added table 4/32, length now 52
1860 12:48:29.193201 ACPI: * MADT
1861 12:48:29.196440 SCI is IRQ9
1862 12:48:29.199576 ACPI: added table 5/32, length now 56
1863 12:48:29.199657 current = 76b09850
1864 12:48:29.202927 ACPI: * DMAR
1865 12:48:29.206287 ACPI: added table 6/32, length now 60
1866 12:48:29.209721 ACPI: added table 7/32, length now 64
1867 12:48:29.213148 ACPI: * HPET
1868 12:48:29.216581 ACPI: added table 8/32, length now 68
1869 12:48:29.216659 ACPI: done.
1870 12:48:29.219886 ACPI tables: 35216 bytes.
1871 12:48:29.222904 smbios_write_tables: 769ef000
1872 12:48:29.226123 EC returned error result code 3
1873 12:48:29.229516 Couldn't obtain OEM name from CBI
1874 12:48:29.233005 Create SMBIOS type 16
1875 12:48:29.236108 Create SMBIOS type 17
1876 12:48:29.236185 GENERIC: 0.0 (WIFI Device)
1877 12:48:29.239654 SMBIOS tables: 1750 bytes.
1878 12:48:29.246069 Writing table forward entry at 0x00000500
1879 12:48:29.249502 Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 392c
1880 12:48:29.256323 Writing coreboot table at 0x76b25000
1881 12:48:29.259651 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1882 12:48:29.266224 1. 0000000000001000-000000000009ffff: RAM
1883 12:48:29.269521 2. 00000000000a0000-00000000000fffff: RESERVED
1884 12:48:29.272880 3. 0000000000100000-00000000769eefff: RAM
1885 12:48:29.279366 4. 00000000769ef000-0000000076b97fff: CONFIGURATION TABLES
1886 12:48:29.285803 5. 0000000076b98000-0000000076c09fff: RAMSTAGE
1887 12:48:29.289089 6. 0000000076c0a000-0000000076ffffff: CONFIGURATION TABLES
1888 12:48:29.295867 7. 0000000077000000-000000007fbfffff: RESERVED
1889 12:48:29.299257 8. 00000000c0000000-00000000cfffffff: RESERVED
1890 12:48:29.306008 9. 00000000f8000000-00000000f9ffffff: RESERVED
1891 12:48:29.309015 10. 00000000fb000000-00000000fb000fff: RESERVED
1892 12:48:29.315848 11. 00000000fe000000-00000000fe00ffff: RESERVED
1893 12:48:29.319222 12. 00000000fed80000-00000000fed87fff: RESERVED
1894 12:48:29.322505 13. 00000000fed90000-00000000fed92fff: RESERVED
1895 12:48:29.328963 14. 00000000feda0000-00000000feda1fff: RESERVED
1896 12:48:29.332377 15. 00000000fedc0000-00000000feddffff: RESERVED
1897 12:48:29.339098 16. 0000000100000000-00000002803fffff: RAM
1898 12:48:29.342120 Passing 4 GPIOs to payload:
1899 12:48:29.345569 NAME | PORT | POLARITY | VALUE
1900 12:48:29.352267 lid | undefined | high | high
1901 12:48:29.355669 power | undefined | high | low
1902 12:48:29.362163 oprom | undefined | high | low
1903 12:48:29.365541 EC in RW | 0x000000e5 | high | high
1904 12:48:29.372323 Wrote coreboot table at: 0x76b25000, 0x610 bytes, checksum f590
1905 12:48:29.375555 coreboot table: 1576 bytes.
1906 12:48:29.378700 IMD ROOT 0. 0x76fff000 0x00001000
1907 12:48:29.385574 IMD SMALL 1. 0x76ffe000 0x00001000
1908 12:48:29.388827 FSP MEMORY 2. 0x76c4e000 0x003b0000
1909 12:48:29.392091 VPD 3. 0x76c4d000 0x00000367
1910 12:48:29.395358 RO MCACHE 4. 0x76c4c000 0x00000fdc
1911 12:48:29.398934 CONSOLE 5. 0x76c2c000 0x00020000
1912 12:48:29.402045 FMAP 6. 0x76c2b000 0x00000578
1913 12:48:29.405476 TIME STAMP 7. 0x76c2a000 0x00000910
1914 12:48:29.408932 VBOOT WORK 8. 0x76c16000 0x00014000
1915 12:48:29.412126 ROMSTG STCK 9. 0x76c15000 0x00001000
1916 12:48:29.418545 AFTER CAR 10. 0x76c0a000 0x0000b000
1917 12:48:29.421878 RAMSTAGE 11. 0x76b97000 0x00073000
1918 12:48:29.425285 REFCODE 12. 0x76b42000 0x00055000
1919 12:48:29.428648 SMM BACKUP 13. 0x76b32000 0x00010000
1920 12:48:29.432038 4f444749 14. 0x76b30000 0x00002000
1921 12:48:29.435331 EXT VBT15. 0x76b2d000 0x0000219f
1922 12:48:29.438371 COREBOOT 16. 0x76b25000 0x00008000
1923 12:48:29.441981 ACPI 17. 0x76b01000 0x00024000
1924 12:48:29.445067 ACPI GNVS 18. 0x76b00000 0x00001000
1925 12:48:29.451936 RAMOOPS 19. 0x76a00000 0x00100000
1926 12:48:29.455379 TPM2 TCGLOG20. 0x769f0000 0x00010000
1927 12:48:29.458442 SMBIOS 21. 0x769ef000 0x00000800
1928 12:48:29.458515 IMD small region:
1929 12:48:29.465353 IMD ROOT 0. 0x76ffec00 0x00000400
1930 12:48:29.468804 FSP RUNTIME 1. 0x76ffebe0 0x00000004
1931 12:48:29.471722 POWER STATE 2. 0x76ffeb80 0x00000044
1932 12:48:29.475087 ROMSTAGE 3. 0x76ffeb60 0x00000004
1933 12:48:29.478646 MEM INFO 4. 0x76ffe980 0x000001e0
1934 12:48:29.484962 BS: BS_WRITE_TABLES run times (exec / console): 5 / 484 ms
1935 12:48:29.488525 MTRR: Physical address space:
1936 12:48:29.495197 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
1937 12:48:29.501644 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
1938 12:48:29.508246 0x00000000000c0000 - 0x0000000077000000 size 0x76f40000 type 6
1939 12:48:29.511889 0x0000000077000000 - 0x0000000080000000 size 0x09000000 type 0
1940 12:48:29.518144 0x0000000080000000 - 0x0000000090000000 size 0x10000000 type 1
1941 12:48:29.524929 0x0000000090000000 - 0x0000000100000000 size 0x70000000 type 0
1942 12:48:29.531347 0x0000000100000000 - 0x0000000280400000 size 0x180400000 type 6
1943 12:48:29.534826 MTRR: Fixed MSR 0x250 0x0606060606060606
1944 12:48:29.541442 MTRR: Fixed MSR 0x258 0x0606060606060606
1945 12:48:29.544971 MTRR: Fixed MSR 0x259 0x0000000000000000
1946 12:48:29.548032 MTRR: Fixed MSR 0x268 0x0606060606060606
1947 12:48:29.551426 MTRR: Fixed MSR 0x269 0x0606060606060606
1948 12:48:29.558204 MTRR: Fixed MSR 0x26a 0x0606060606060606
1949 12:48:29.561585 MTRR: Fixed MSR 0x26b 0x0606060606060606
1950 12:48:29.564941 MTRR: Fixed MSR 0x26c 0x0606060606060606
1951 12:48:29.567949 MTRR: Fixed MSR 0x26d 0x0606060606060606
1952 12:48:29.574793 MTRR: Fixed MSR 0x26e 0x0606060606060606
1953 12:48:29.578071 MTRR: Fixed MSR 0x26f 0x0606060606060606
1954 12:48:29.581400 call enable_fixed_mtrr()
1955 12:48:29.584639 CPU physical address size: 39 bits
1956 12:48:29.587815 MTRR: default type WB/UC MTRR counts: 6/6.
1957 12:48:29.591071 MTRR: UC selected as default type.
1958 12:48:29.597660 MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
1959 12:48:29.604566 MTRR: 1 base 0x0000000077000000 mask 0x0000007fff000000 type 0
1960 12:48:29.611048 MTRR: 2 base 0x0000000078000000 mask 0x0000007ff8000000 type 0
1961 12:48:29.617838 MTRR: 3 base 0x0000000080000000 mask 0x0000007ff0000000 type 1
1962 12:48:29.624435 MTRR: 4 base 0x0000000100000000 mask 0x0000007f00000000 type 6
1963 12:48:29.630815 MTRR: 5 base 0x0000000200000000 mask 0x0000007f00000000 type 6
1964 12:48:29.630894
1965 12:48:29.630961 MTRR check
1966 12:48:29.634119 Fixed MTRRs : Enabled
1967 12:48:29.637533 Variable MTRRs: Enabled
1968 12:48:29.637613
1969 12:48:29.640889 MTRR: Fixed MSR 0x250 0x0606060606060606
1970 12:48:29.644120 MTRR: Fixed MSR 0x258 0x0606060606060606
1971 12:48:29.651150 MTRR: Fixed MSR 0x259 0x0000000000000000
1972 12:48:29.654092 MTRR: Fixed MSR 0x268 0x0606060606060606
1973 12:48:29.657482 MTRR: Fixed MSR 0x269 0x0606060606060606
1974 12:48:29.660942 MTRR: Fixed MSR 0x26a 0x0606060606060606
1975 12:48:29.667318 MTRR: Fixed MSR 0x26b 0x0606060606060606
1976 12:48:29.670749 MTRR: Fixed MSR 0x26c 0x0606060606060606
1977 12:48:29.674123 MTRR: Fixed MSR 0x26d 0x0606060606060606
1978 12:48:29.677420 MTRR: Fixed MSR 0x26e 0x0606060606060606
1979 12:48:29.684268 MTRR: Fixed MSR 0x26f 0x0606060606060606
1980 12:48:29.690838 BS: BS_WRITE_TABLES exit times (exec / console): 2 / 150 ms
1981 12:48:29.690923 call enable_fixed_mtrr()
1982 12:48:29.694156 Checking cr50 for pending updates
1983 12:48:29.697670 CPU physical address size: 39 bits
1984 12:48:29.704093 MTRR: Fixed MSR 0x250 0x0606060606060606
1985 12:48:29.707617 MTRR: Fixed MSR 0x250 0x0606060606060606
1986 12:48:29.710931 MTRR: Fixed MSR 0x258 0x0606060606060606
1987 12:48:29.714238 MTRR: Fixed MSR 0x259 0x0000000000000000
1988 12:48:29.720631 MTRR: Fixed MSR 0x268 0x0606060606060606
1989 12:48:29.724375 MTRR: Fixed MSR 0x269 0x0606060606060606
1990 12:48:29.727239 MTRR: Fixed MSR 0x26a 0x0606060606060606
1991 12:48:29.730687 MTRR: Fixed MSR 0x26b 0x0606060606060606
1992 12:48:29.737401 MTRR: Fixed MSR 0x26c 0x0606060606060606
1993 12:48:29.740850 MTRR: Fixed MSR 0x26d 0x0606060606060606
1994 12:48:29.744141 MTRR: Fixed MSR 0x26e 0x0606060606060606
1995 12:48:29.747086 MTRR: Fixed MSR 0x26f 0x0606060606060606
1996 12:48:29.754334 MTRR: Fixed MSR 0x258 0x0606060606060606
1997 12:48:29.754419 call enable_fixed_mtrr()
1998 12:48:29.761198 MTRR: Fixed MSR 0x259 0x0000000000000000
1999 12:48:29.764585 MTRR: Fixed MSR 0x268 0x0606060606060606
2000 12:48:29.768082 MTRR: Fixed MSR 0x269 0x0606060606060606
2001 12:48:29.770961 MTRR: Fixed MSR 0x26a 0x0606060606060606
2002 12:48:29.777872 MTRR: Fixed MSR 0x26b 0x0606060606060606
2003 12:48:29.780967 MTRR: Fixed MSR 0x26c 0x0606060606060606
2004 12:48:29.784358 MTRR: Fixed MSR 0x26d 0x0606060606060606
2005 12:48:29.787623 MTRR: Fixed MSR 0x26e 0x0606060606060606
2006 12:48:29.794294 MTRR: Fixed MSR 0x26f 0x0606060606060606
2007 12:48:29.797412 CPU physical address size: 39 bits
2008 12:48:29.800840 call enable_fixed_mtrr()
2009 12:48:29.804472 MTRR: Fixed MSR 0x250 0x0606060606060606
2010 12:48:29.807475 MTRR: Fixed MSR 0x250 0x0606060606060606
2011 12:48:29.814311 MTRR: Fixed MSR 0x258 0x0606060606060606
2012 12:48:29.817619 MTRR: Fixed MSR 0x259 0x0000000000000000
2013 12:48:29.820964 MTRR: Fixed MSR 0x268 0x0606060606060606
2014 12:48:29.824158 MTRR: Fixed MSR 0x269 0x0606060606060606
2015 12:48:29.830804 MTRR: Fixed MSR 0x26a 0x0606060606060606
2016 12:48:29.833947 MTRR: Fixed MSR 0x26b 0x0606060606060606
2017 12:48:29.837244 MTRR: Fixed MSR 0x26c 0x0606060606060606
2018 12:48:29.840846 MTRR: Fixed MSR 0x26d 0x0606060606060606
2019 12:48:29.847479 MTRR: Fixed MSR 0x26e 0x0606060606060606
2020 12:48:29.850540 MTRR: Fixed MSR 0x26f 0x0606060606060606
2021 12:48:29.853867 MTRR: Fixed MSR 0x258 0x0606060606060606
2022 12:48:29.857250 call enable_fixed_mtrr()
2023 12:48:29.860526 MTRR: Fixed MSR 0x259 0x0000000000000000
2024 12:48:29.867017 MTRR: Fixed MSR 0x268 0x0606060606060606
2025 12:48:29.870461 MTRR: Fixed MSR 0x269 0x0606060606060606
2026 12:48:29.873845 MTRR: Fixed MSR 0x26a 0x0606060606060606
2027 12:48:29.877124 MTRR: Fixed MSR 0x26b 0x0606060606060606
2028 12:48:29.884041 MTRR: Fixed MSR 0x26c 0x0606060606060606
2029 12:48:29.887082 MTRR: Fixed MSR 0x26d 0x0606060606060606
2030 12:48:29.890361 MTRR: Fixed MSR 0x26e 0x0606060606060606
2031 12:48:29.893633 MTRR: Fixed MSR 0x26f 0x0606060606060606
2032 12:48:29.897744 CPU physical address size: 39 bits
2033 12:48:29.904447 call enable_fixed_mtrr()
2034 12:48:29.907441 MTRR: Fixed MSR 0x250 0x0606060606060606
2035 12:48:29.910896 MTRR: Fixed MSR 0x250 0x0606060606060606
2036 12:48:29.914331 MTRR: Fixed MSR 0x258 0x0606060606060606
2037 12:48:29.920846 MTRR: Fixed MSR 0x259 0x0000000000000000
2038 12:48:29.924254 MTRR: Fixed MSR 0x268 0x0606060606060606
2039 12:48:29.927382 MTRR: Fixed MSR 0x269 0x0606060606060606
2040 12:48:29.930612 MTRR: Fixed MSR 0x26a 0x0606060606060606
2041 12:48:29.933918 MTRR: Fixed MSR 0x26b 0x0606060606060606
2042 12:48:29.940906 MTRR: Fixed MSR 0x26c 0x0606060606060606
2043 12:48:29.944198 MTRR: Fixed MSR 0x26d 0x0606060606060606
2044 12:48:29.947532 MTRR: Fixed MSR 0x26e 0x0606060606060606
2045 12:48:29.950695 MTRR: Fixed MSR 0x26f 0x0606060606060606
2046 12:48:29.958308 MTRR: Fixed MSR 0x258 0x0606060606060606
2047 12:48:29.961747 MTRR: Fixed MSR 0x259 0x0000000000000000
2048 12:48:29.965046 MTRR: Fixed MSR 0x268 0x0606060606060606
2049 12:48:29.968058 MTRR: Fixed MSR 0x269 0x0606060606060606
2050 12:48:29.974908 MTRR: Fixed MSR 0x26a 0x0606060606060606
2051 12:48:29.978287 MTRR: Fixed MSR 0x26b 0x0606060606060606
2052 12:48:29.981620 MTRR: Fixed MSR 0x26c 0x0606060606060606
2053 12:48:29.985049 MTRR: Fixed MSR 0x26d 0x0606060606060606
2054 12:48:29.991446 MTRR: Fixed MSR 0x26e 0x0606060606060606
2055 12:48:29.994936 MTRR: Fixed MSR 0x26f 0x0606060606060606
2056 12:48:29.998008 call enable_fixed_mtrr()
2057 12:48:30.001363 call enable_fixed_mtrr()
2058 12:48:30.004736 CPU physical address size: 39 bits
2059 12:48:30.008046 CPU physical address size: 39 bits
2060 12:48:30.011452 CPU physical address size: 39 bits
2061 12:48:30.014918 CPU physical address size: 39 bits
2062 12:48:30.017883 Reading cr50 TPM mode
2063 12:48:30.027577 BS: BS_PAYLOAD_LOAD entry times (exec / console): 326 / 6 ms
2064 12:48:30.037388 CBFS: Found 'fallback/payload' @0x38db00 size 0x4be9c in mcache @0x76c4cf60
2065 12:48:30.040576 Checking segment from ROM address 0xffc02b38
2066 12:48:30.044111 Checking segment from ROM address 0xffc02b54
2067 12:48:30.050503 Loading segment from ROM address 0xffc02b38
2068 12:48:30.050587 code (compression=0)
2069 12:48:30.060552 New segment dstaddr 0x30000000 memsize 0x2662db0 srcaddr 0xffc02b70 filesize 0x4be64
2070 12:48:30.070530 Loading Segment: addr: 0x30000000 memsz: 0x0000000002662db0 filesz: 0x000000000004be64
2071 12:48:30.070624 it's not compressed!
2072 12:48:30.210042 [ 0x30000000, 3004be64, 0x32662db0) <- ffc02b70
2073 12:48:30.216683 Clearing Segment: addr: 0x000000003004be64 memsz: 0x0000000002616f4c
2074 12:48:30.223488 Loading segment from ROM address 0xffc02b54
2075 12:48:30.223577 Entry Point 0x30000000
2076 12:48:30.226898 Loaded segments
2077 12:48:30.233273 BS: BS_PAYLOAD_LOAD run times (exec / console): 135 / 63 ms
2078 12:48:30.276421 Finalizing chipset.
2079 12:48:30.279636 Finalizing SMM.
2080 12:48:30.279729 APMC done.
2081 12:48:30.286258 BS: BS_PAYLOAD_LOAD exit times (exec / console): 42 / 5 ms
2082 12:48:30.289559 mp_park_aps done after 0 msecs.
2083 12:48:30.293029 Jumping to boot code at 0x30000000(0x76b25000)
2084 12:48:30.302806 CPU0: stack: 0x76bee000 - 0x76bef000, lowest used address 0x76beea78, stack used: 1416 bytes
2085 12:48:30.302902
2086 12:48:30.302979
2087 12:48:30.303046
2088 12:48:30.306096 Starting depthcharge on Voema...
2089 12:48:30.306183
2090 12:48:30.306544 end: 2.2.3 depthcharge-start (duration 00:00:10) [common]
2091 12:48:30.306648 start: 2.2.4 bootloader-commands (timeout 00:04:45) [common]
2092 12:48:30.306736 Setting prompt string to ['volteer:']
2093 12:48:30.306819 bootloader-commands: Wait for prompt ['volteer:'] (timeout 00:04:45)
2094 12:48:30.316267 WARNING: can't convert coreboot GPIOs, 'lid' won't be resampled at runtime!
2095 12:48:30.316355
2096 12:48:30.322642 WARNING: can't convert coreboot GPIOs, 'power' won't be resampled at runtime!
2097 12:48:30.322730
2098 12:48:30.329287 Looking for NVMe Controller 0x3005f220 @ 00:1d:00
2099 12:48:30.329375
2100 12:48:30.332609 Failed to find eMMC card reader
2101 12:48:30.332697
2102 12:48:30.332766 Wipe memory regions:
2103 12:48:30.332830
2104 12:48:30.339307 [0x00000000001000, 0x000000000a0000)
2105 12:48:30.339395
2106 12:48:30.342368 [0x00000000100000, 0x00000030000000)
2107 12:48:30.368224
2108 12:48:30.371405 [0x00000032662db0, 0x000000769ef000)
2109 12:48:30.406940
2110 12:48:30.410370 [0x00000100000000, 0x00000280400000)
2111 12:48:30.611550
2112 12:48:30.614515 ec_init: CrosEC protocol v3 supported (256, 256)
2113 12:48:30.614607
2114 12:48:30.621132 update_port_state: port C0 state: usb enable 1 mux conn 0
2115 12:48:30.621224
2116 12:48:30.627894 update_port_state: port C0 req: usage 0 usb3 1 usb2 9 ufp 1 ori_hsl 0 ori_sbu 0 dbg_acc 1
2117 12:48:30.632418
2118 12:48:30.635747 pmc_check_ipc_sts: STS_BUSY done after 1563 us
2119 12:48:30.635855
2120 12:48:30.639188 send_conn_disc_msg: pmc_send_cmd succeeded
2121 12:48:31.073326
2122 12:48:31.073471 R8152: Initializing
2123 12:48:31.073545
2124 12:48:31.076733 Version 6 (ocp_data = 5c30)
2125 12:48:31.076816
2126 12:48:31.080214 R8152: Done initializing
2127 12:48:31.080295
2128 12:48:31.083035 Adding net device
2129 12:48:31.385983
2130 12:48:31.389280 [firmware-volteer-13672.B-collabora] Oct 22 2021 06:32:35
2131 12:48:31.389371
2132 12:48:31.389440
2133 12:48:31.389504
2134 12:48:31.392592 Setting prompt string to ['volteer:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2136 12:48:31.493389 volteer: tftpboot 192.168.201.1 9584839/tftp-deploy-0bzs7r4m/kernel/bzImage 9584839/tftp-deploy-0bzs7r4m/kernel/cmdline 9584839/tftp-deploy-0bzs7r4m/ramdisk/ramdisk.cpio.gz
2137 12:48:31.493543 Setting prompt string to ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2138 12:48:31.493652 bootloader-commands: Wait for prompt ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:43)
2139 12:48:31.498202 tftpboot 192.168.201.1 9584839/tftp-deploy-0bzs7r4m/kernel/bzImoy-0bzs7r4m/kernel/cmdline 9584839/tftp-deploy-0bzs7r4m/ramdisk/ramdisk.cpio.gz
2140 12:48:31.498292
2141 12:48:31.498362 Waiting for link
2142 12:48:31.701559
2143 12:48:31.701733 done.
2144 12:48:31.701821
2145 12:48:31.701887 MAC: 00:24:32:30:7c:e4
2146 12:48:31.701951
2147 12:48:31.704524 Sending DHCP discover... done.
2148 12:48:31.704615
2149 12:48:31.707749 Waiting for reply... done.
2150 12:48:31.707837
2151 12:48:31.711163 Sending DHCP request... done.
2152 12:48:31.711254
2153 12:48:31.714406 Waiting for reply... done.
2154 12:48:31.714494
2155 12:48:31.717664 My ip is 192.168.201.23
2156 12:48:31.717775
2157 12:48:31.721084 The DHCP server ip is 192.168.201.1
2158 12:48:31.721172
2159 12:48:31.727772 TFTP server IP predefined by user: 192.168.201.1
2160 12:48:31.727860
2161 12:48:31.734479 Bootfile predefined by user: 9584839/tftp-deploy-0bzs7r4m/kernel/bzImage
2162 12:48:31.734567
2163 12:48:31.737919 Sending tftp read request... done.
2164 12:48:31.738006
2165 12:48:31.740857 Waiting for the transfer...
2166 12:48:31.740944
2167 12:48:32.262925 00000000 ################################################################
2168 12:48:32.263082
2169 12:48:32.787615 00080000 ################################################################
2170 12:48:32.787758
2171 12:48:33.320168 00100000 ################################################################
2172 12:48:33.320316
2173 12:48:33.849280 00180000 ################################################################
2174 12:48:33.849423
2175 12:48:34.375219 00200000 ################################################################
2176 12:48:34.375378
2177 12:48:34.893902 00280000 ################################################################
2178 12:48:34.894066
2179 12:48:35.414536 00300000 ################################################################
2180 12:48:35.414699
2181 12:48:35.934355 00380000 ################################################################
2182 12:48:35.934511
2183 12:48:36.464445 00400000 ################################################################
2184 12:48:36.464605
2185 12:48:36.994005 00480000 ################################################################
2186 12:48:36.994161
2187 12:48:37.520773 00500000 ################################################################
2188 12:48:37.520913
2189 12:48:38.055487 00580000 ################################################################
2190 12:48:38.055632
2191 12:48:38.585284 00600000 ################################################################
2192 12:48:38.585428
2193 12:48:39.116263 00680000 ################################################################
2194 12:48:39.116407
2195 12:48:39.414251 00700000 ##################################### done.
2196 12:48:39.414397
2197 12:48:39.417660 The bootfile was 7638928 bytes long.
2198 12:48:39.417753
2199 12:48:39.421104 Sending tftp read request... done.
2200 12:48:39.421189
2201 12:48:39.424089 Waiting for the transfer...
2202 12:48:39.424164
2203 12:48:39.955043 00000000 ################################################################
2204 12:48:39.955182
2205 12:48:40.490399 00080000 ################################################################
2206 12:48:40.490544
2207 12:48:41.032985 00100000 ################################################################
2208 12:48:41.033125
2209 12:48:41.580981 00180000 ################################################################
2210 12:48:41.581124
2211 12:48:42.114793 00200000 ################################################################
2212 12:48:42.114933
2213 12:48:42.666572 00280000 ################################################################
2214 12:48:42.666714
2215 12:48:43.218915 00300000 ################################################################
2216 12:48:43.219270
2217 12:48:43.916832 00380000 ################################################################
2218 12:48:43.917425
2219 12:48:44.534679 00400000 ################################################################
2220 12:48:44.535224
2221 12:48:45.194137 00480000 ################################################################
2222 12:48:45.194730
2223 12:48:45.830670 00500000 ################################################################
2224 12:48:45.830816
2225 12:48:46.453206 00580000 ################################################################
2226 12:48:46.453345
2227 12:48:47.004534 00600000 ################################################################
2228 12:48:47.004682
2229 12:48:47.557295 00680000 ################################################################
2230 12:48:47.557497
2231 12:48:48.088706 00700000 ################################################################
2232 12:48:48.088851
2233 12:48:48.709593 00780000 ################################################################
2234 12:48:48.709761
2235 12:48:49.171913 00800000 ##################################################### done.
2236 12:48:49.172054
2237 12:48:49.174956 Sending tftp read request... done.
2238 12:48:49.175044
2239 12:48:49.175114 Waiting for the transfer...
2240 12:48:49.178316
2241 12:48:49.178405 00000000 # done.
2242 12:48:49.178477
2243 12:48:49.188396 Command line loaded dynamically from TFTP file: 9584839/tftp-deploy-0bzs7r4m/kernel/cmdline
2244 12:48:49.188486
2245 12:48:49.201546 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
2246 12:48:49.205051
2247 12:48:49.208140 Shutting down all USB controllers.
2248 12:48:49.208219
2249 12:48:49.208286 Removing current net device
2250 12:48:49.208367
2251 12:48:49.211497 Finalizing coreboot
2252 12:48:49.211575
2253 12:48:49.218323 Exiting depthcharge with code 4 at timestamp: 27551554
2254 12:48:49.218405
2255 12:48:49.218472
2256 12:48:49.218533 Starting kernel ...
2257 12:48:49.218594
2258 12:48:49.218652
2259 12:48:49.219019 end: 2.2.4 bootloader-commands (duration 00:00:19) [common]
2260 12:48:49.219122 start: 2.2.5 auto-login-action (timeout 00:04:26) [common]
2261 12:48:49.219202 Setting prompt string to ['Linux version [0-9]']
2262 12:48:49.219277 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2263 12:48:49.219349 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
2265 12:53:15.219996 end: 2.2.5 auto-login-action (duration 00:04:26) [common]
2267 12:53:15.221250 depthcharge-retry failed: 1 of 1 attempts. 'auto-login-action timed out after 266 seconds'
2269 12:53:15.222396 end: 2.2 depthcharge-retry (duration 00:05:00) [common]
2272 12:53:15.224349 end: 2 depthcharge-action (duration 00:05:00) [common]
2274 12:53:15.225942 Cleaning after the job
2275 12:53:15.226536 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/9584839/tftp-deploy-0bzs7r4m/ramdisk
2276 12:53:15.229392 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/9584839/tftp-deploy-0bzs7r4m/kernel
2277 12:53:15.231496 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/9584839/tftp-deploy-0bzs7r4m/modules
2278 12:53:15.232333 start: 5.1 power-off (timeout 00:00:30) [common]
2279 12:53:15.232769 Calling: 'nice' 'pduclient' '--daemon=localhost' '--hostname=asus-cx9400-volteer-cbg-3' '--port=1' '--command=off'
2280 12:53:15.330034 >> Command sent successfully.
2281 12:53:15.338937 Returned 0 in 0 seconds
2282 12:53:15.440435 end: 5.1 power-off (duration 00:00:00) [common]
2284 12:53:15.441460 start: 5.2 read-feedback (timeout 00:10:00) [common]
2285 12:53:15.442269 Listened to connection for namespace 'common' for up to 1s
2286 12:53:16.446945 Finalising connection for namespace 'common'
2287 12:53:16.447123 Disconnecting from shell: Finalise
2288 12:53:16.447207
2289 12:53:16.547928 end: 5.2 read-feedback (duration 00:00:01) [common]
2290 12:53:16.548094 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/9584839
2291 12:53:16.553333 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/9584839
2292 12:53:16.553459 JobError: Your job cannot terminate cleanly.