Boot log: asus-cx9400-volteer
- Warnings: 0
- Kernel Warnings: 0
- Errors: 2
- Kernel Errors: 0
- Boot result: FAIL
1 12:48:10.107342 lava-dispatcher, installed at version: 2023.01
2 12:48:10.107545 start: 0 validate
3 12:48:10.107667 Start time: 2023-03-13 12:48:10.107661+00:00 (UTC)
4 12:48:10.107791 Using caching service: 'http://localhost/cache/?uri=%s'
5 12:48:10.107920 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-ltp%2F20230303.0%2Famd64%2Finitrd.cpio.gz exists
6 12:48:10.402302 Using caching service: 'http://localhost/cache/?uri=%s'
7 12:48:10.402706 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-4.4.y-st%2Fv4.4-st20-939-g5ff13a6decb9%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fkernel%2FbzImage exists
8 12:48:10.693543 Using caching service: 'http://localhost/cache/?uri=%s'
9 12:48:10.694363 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-ltp%2F20230303.0%2Famd64%2Ffull.rootfs.tar.xz exists
10 12:48:13.762221 Using caching service: 'http://localhost/cache/?uri=%s'
11 12:48:13.762923 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-4.4.y-st%2Fv4.4-st20-939-g5ff13a6decb9%2Fx86_64%2Fx86_64_defconfig%2Bx86-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 12:48:14.063090 validate duration: 3.96
14 12:48:14.064753 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 12:48:14.065389 start: 1.1 download-retry (timeout 00:10:00) [common]
16 12:48:14.065917 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 12:48:14.066466 Not decompressing ramdisk as can be used compressed.
18 12:48:14.066928 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-ltp/20230303.0/amd64/initrd.cpio.gz
19 12:48:14.067320 saving as /var/lib/lava/dispatcher/tmp/9584814/tftp-deploy-ti558n_g/ramdisk/initrd.cpio.gz
20 12:48:14.067673 total size: 5432112 (5MB)
21 12:48:14.636866 progress 0% (0MB)
22 12:48:14.645380 progress 5% (0MB)
23 12:48:14.653174 progress 10% (0MB)
24 12:48:14.660942 progress 15% (0MB)
25 12:48:14.668857 progress 20% (1MB)
26 12:48:14.673552 progress 25% (1MB)
27 12:48:14.677197 progress 30% (1MB)
28 12:48:14.680635 progress 35% (1MB)
29 12:48:14.683444 progress 40% (2MB)
30 12:48:14.685879 progress 45% (2MB)
31 12:48:14.688217 progress 50% (2MB)
32 12:48:14.690544 progress 55% (2MB)
33 12:48:14.692572 progress 60% (3MB)
34 12:48:14.694490 progress 65% (3MB)
35 12:48:14.696486 progress 70% (3MB)
36 12:48:14.698252 progress 75% (3MB)
37 12:48:14.699877 progress 80% (4MB)
38 12:48:14.701466 progress 85% (4MB)
39 12:48:14.703228 progress 90% (4MB)
40 12:48:14.704708 progress 95% (4MB)
41 12:48:14.706155 progress 100% (5MB)
42 12:48:14.706377 5MB downloaded in 0.64s (8.11MB/s)
43 12:48:14.706543 end: 1.1.1 http-download (duration 00:00:01) [common]
45 12:48:14.706816 end: 1.1 download-retry (duration 00:00:01) [common]
46 12:48:14.706915 start: 1.2 download-retry (timeout 00:09:59) [common]
47 12:48:14.707011 start: 1.2.1 http-download (timeout 00:09:59) [common]
48 12:48:14.707130 downloading http://storage.kernelci.org/cip/linux-4.4.y-st/v4.4-st20-939-g5ff13a6decb9/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/kernel/bzImage
49 12:48:14.707206 saving as /var/lib/lava/dispatcher/tmp/9584814/tftp-deploy-ti558n_g/kernel/bzImage
50 12:48:14.707276 total size: 7638928 (7MB)
51 12:48:14.707344 No compression specified
52 12:48:14.708335 progress 0% (0MB)
53 12:48:14.710249 progress 5% (0MB)
54 12:48:14.712295 progress 10% (0MB)
55 12:48:14.714172 progress 15% (1MB)
56 12:48:14.716145 progress 20% (1MB)
57 12:48:14.718171 progress 25% (1MB)
58 12:48:14.719957 progress 30% (2MB)
59 12:48:14.721896 progress 35% (2MB)
60 12:48:14.723797 progress 40% (2MB)
61 12:48:14.725604 progress 45% (3MB)
62 12:48:14.727558 progress 50% (3MB)
63 12:48:14.729508 progress 55% (4MB)
64 12:48:14.731243 progress 60% (4MB)
65 12:48:14.733158 progress 65% (4MB)
66 12:48:14.735050 progress 70% (5MB)
67 12:48:14.736834 progress 75% (5MB)
68 12:48:14.738802 progress 80% (5MB)
69 12:48:14.740794 progress 85% (6MB)
70 12:48:14.742579 progress 90% (6MB)
71 12:48:14.744499 progress 95% (6MB)
72 12:48:14.746403 progress 100% (7MB)
73 12:48:14.746516 7MB downloaded in 0.04s (185.68MB/s)
74 12:48:14.746662 end: 1.2.1 http-download (duration 00:00:00) [common]
76 12:48:14.746898 end: 1.2 download-retry (duration 00:00:00) [common]
77 12:48:14.746986 start: 1.3 download-retry (timeout 00:09:59) [common]
78 12:48:14.747072 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 12:48:14.747173 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-ltp/20230303.0/amd64/full.rootfs.tar.xz
80 12:48:14.747243 saving as /var/lib/lava/dispatcher/tmp/9584814/tftp-deploy-ti558n_g/nfsrootfs/full.rootfs.tar
81 12:48:14.747304 total size: 124197008 (118MB)
82 12:48:14.747365 Using unxz to decompress xz
83 12:48:14.750462 progress 0% (0MB)
84 12:48:15.193745 progress 5% (5MB)
85 12:48:15.645590 progress 10% (11MB)
86 12:48:16.096634 progress 15% (17MB)
87 12:48:16.553994 progress 20% (23MB)
88 12:48:16.888530 progress 25% (29MB)
89 12:48:17.226392 progress 30% (35MB)
90 12:48:17.494109 progress 35% (41MB)
91 12:48:17.647221 progress 40% (47MB)
92 12:48:18.012392 progress 45% (53MB)
93 12:48:18.372371 progress 50% (59MB)
94 12:48:18.705988 progress 55% (65MB)
95 12:48:19.058176 progress 60% (71MB)
96 12:48:19.389168 progress 65% (77MB)
97 12:48:19.762418 progress 70% (82MB)
98 12:48:20.165147 progress 75% (88MB)
99 12:48:20.570093 progress 80% (94MB)
100 12:48:20.699635 progress 85% (100MB)
101 12:48:20.855470 progress 90% (106MB)
102 12:48:21.178869 progress 95% (112MB)
103 12:48:21.542610 progress 100% (118MB)
104 12:48:21.547598 118MB downloaded in 6.80s (17.42MB/s)
105 12:48:21.547889 end: 1.3.1 http-download (duration 00:00:07) [common]
107 12:48:21.548155 end: 1.3 download-retry (duration 00:00:07) [common]
108 12:48:21.548250 start: 1.4 download-retry (timeout 00:09:53) [common]
109 12:48:21.548382 start: 1.4.1 http-download (timeout 00:09:53) [common]
110 12:48:21.548499 downloading http://storage.kernelci.org/cip/linux-4.4.y-st/v4.4-st20-939-g5ff13a6decb9/x86_64/x86_64_defconfig+x86-chromebook/gcc-10/modules.tar.xz
111 12:48:21.548575 saving as /var/lib/lava/dispatcher/tmp/9584814/tftp-deploy-ti558n_g/modules/modules.tar
112 12:48:21.548640 total size: 250760 (0MB)
113 12:48:21.548704 Using unxz to decompress xz
114 12:48:21.551648 progress 13% (0MB)
115 12:48:21.552012 progress 26% (0MB)
116 12:48:21.552245 progress 39% (0MB)
117 12:48:21.553597 progress 52% (0MB)
118 12:48:21.555464 progress 65% (0MB)
119 12:48:21.557371 progress 78% (0MB)
120 12:48:21.559173 progress 91% (0MB)
121 12:48:21.560987 progress 100% (0MB)
122 12:48:21.566409 0MB downloaded in 0.02s (13.46MB/s)
123 12:48:21.566649 end: 1.4.1 http-download (duration 00:00:00) [common]
125 12:48:21.566914 end: 1.4 download-retry (duration 00:00:00) [common]
126 12:48:21.567014 start: 1.5 prepare-tftp-overlay (timeout 00:09:52) [common]
127 12:48:21.567115 start: 1.5.1 extract-nfsrootfs (timeout 00:09:52) [common]
128 12:48:23.227989 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/9584814/extract-nfsrootfs-ywgv904d
129 12:48:23.228203 end: 1.5.1 extract-nfsrootfs (duration 00:00:02) [common]
130 12:48:23.228594 start: 1.5.2 lava-overlay (timeout 00:09:51) [common]
131 12:48:23.228744 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/9584814/lava-overlay-0mtn_p8d
132 12:48:23.228856 makedir: /var/lib/lava/dispatcher/tmp/9584814/lava-overlay-0mtn_p8d/lava-9584814/bin
133 12:48:23.228945 makedir: /var/lib/lava/dispatcher/tmp/9584814/lava-overlay-0mtn_p8d/lava-9584814/tests
134 12:48:23.229031 makedir: /var/lib/lava/dispatcher/tmp/9584814/lava-overlay-0mtn_p8d/lava-9584814/results
135 12:48:23.229135 Creating /var/lib/lava/dispatcher/tmp/9584814/lava-overlay-0mtn_p8d/lava-9584814/bin/lava-add-keys
136 12:48:23.229273 Creating /var/lib/lava/dispatcher/tmp/9584814/lava-overlay-0mtn_p8d/lava-9584814/bin/lava-add-sources
137 12:48:23.229395 Creating /var/lib/lava/dispatcher/tmp/9584814/lava-overlay-0mtn_p8d/lava-9584814/bin/lava-background-process-start
138 12:48:23.229510 Creating /var/lib/lava/dispatcher/tmp/9584814/lava-overlay-0mtn_p8d/lava-9584814/bin/lava-background-process-stop
139 12:48:23.229625 Creating /var/lib/lava/dispatcher/tmp/9584814/lava-overlay-0mtn_p8d/lava-9584814/bin/lava-common-functions
140 12:48:23.229741 Creating /var/lib/lava/dispatcher/tmp/9584814/lava-overlay-0mtn_p8d/lava-9584814/bin/lava-echo-ipv4
141 12:48:23.229866 Creating /var/lib/lava/dispatcher/tmp/9584814/lava-overlay-0mtn_p8d/lava-9584814/bin/lava-install-packages
142 12:48:23.229982 Creating /var/lib/lava/dispatcher/tmp/9584814/lava-overlay-0mtn_p8d/lava-9584814/bin/lava-installed-packages
143 12:48:23.230091 Creating /var/lib/lava/dispatcher/tmp/9584814/lava-overlay-0mtn_p8d/lava-9584814/bin/lava-os-build
144 12:48:23.230203 Creating /var/lib/lava/dispatcher/tmp/9584814/lava-overlay-0mtn_p8d/lava-9584814/bin/lava-probe-channel
145 12:48:23.230313 Creating /var/lib/lava/dispatcher/tmp/9584814/lava-overlay-0mtn_p8d/lava-9584814/bin/lava-probe-ip
146 12:48:23.230426 Creating /var/lib/lava/dispatcher/tmp/9584814/lava-overlay-0mtn_p8d/lava-9584814/bin/lava-target-ip
147 12:48:23.230538 Creating /var/lib/lava/dispatcher/tmp/9584814/lava-overlay-0mtn_p8d/lava-9584814/bin/lava-target-mac
148 12:48:23.230656 Creating /var/lib/lava/dispatcher/tmp/9584814/lava-overlay-0mtn_p8d/lava-9584814/bin/lava-target-storage
149 12:48:23.230773 Creating /var/lib/lava/dispatcher/tmp/9584814/lava-overlay-0mtn_p8d/lava-9584814/bin/lava-test-case
150 12:48:23.230887 Creating /var/lib/lava/dispatcher/tmp/9584814/lava-overlay-0mtn_p8d/lava-9584814/bin/lava-test-event
151 12:48:23.231000 Creating /var/lib/lava/dispatcher/tmp/9584814/lava-overlay-0mtn_p8d/lava-9584814/bin/lava-test-feedback
152 12:48:23.231113 Creating /var/lib/lava/dispatcher/tmp/9584814/lava-overlay-0mtn_p8d/lava-9584814/bin/lava-test-raise
153 12:48:23.231222 Creating /var/lib/lava/dispatcher/tmp/9584814/lava-overlay-0mtn_p8d/lava-9584814/bin/lava-test-reference
154 12:48:23.231340 Creating /var/lib/lava/dispatcher/tmp/9584814/lava-overlay-0mtn_p8d/lava-9584814/bin/lava-test-runner
155 12:48:23.231455 Creating /var/lib/lava/dispatcher/tmp/9584814/lava-overlay-0mtn_p8d/lava-9584814/bin/lava-test-set
156 12:48:23.231565 Creating /var/lib/lava/dispatcher/tmp/9584814/lava-overlay-0mtn_p8d/lava-9584814/bin/lava-test-shell
157 12:48:23.231675 Updating /var/lib/lava/dispatcher/tmp/9584814/lava-overlay-0mtn_p8d/lava-9584814/bin/lava-install-packages (oe)
158 12:48:23.231790 Updating /var/lib/lava/dispatcher/tmp/9584814/lava-overlay-0mtn_p8d/lava-9584814/bin/lava-installed-packages (oe)
159 12:48:23.231890 Creating /var/lib/lava/dispatcher/tmp/9584814/lava-overlay-0mtn_p8d/lava-9584814/environment
160 12:48:23.231977 LAVA metadata
161 12:48:23.232046 - LAVA_JOB_ID=9584814
162 12:48:23.232112 - LAVA_DISPATCHER_IP=192.168.201.1
163 12:48:23.232215 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:51) [common]
164 12:48:23.232283 skipped lava-vland-overlay
165 12:48:23.232413 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
166 12:48:23.232496 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:51) [common]
167 12:48:23.232566 skipped lava-multinode-overlay
168 12:48:23.232644 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
169 12:48:23.232724 start: 1.5.2.3 test-definition (timeout 00:09:51) [common]
170 12:48:23.232799 Loading test definitions
171 12:48:23.232894 start: 1.5.2.3.1 git-repo-action (timeout 00:09:51) [common]
172 12:48:23.232964 Using /lava-9584814 at stage 0
173 12:48:23.233064 Fetching tests from https://github.com/kernelci/test-definitions
174 12:48:23.233143 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions /var/lib/lava/dispatcher/tmp/9584814/lava-overlay-0mtn_p8d/lava-9584814/0/tests/0_ltp-ipc'
175 12:48:31.805839 Running '/usr/bin/git checkout kernelci.org
176 12:48:31.941729 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/9584814/lava-overlay-0mtn_p8d/lava-9584814/0/tests/0_ltp-ipc/automated/linux/ltp/ltp.yaml
177 12:48:31.942482 uuid=9584814_1.5.2.3.1 testdef=None
178 12:48:31.942645 end: 1.5.2.3.1 git-repo-action (duration 00:00:09) [common]
180 12:48:31.942905 start: 1.5.2.3.2 test-overlay (timeout 00:09:42) [common]
181 12:48:31.943691 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
183 12:48:31.943935 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:42) [common]
184 12:48:31.944983 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
186 12:48:31.945232 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:42) [common]
187 12:48:31.946191 runner path: /var/lib/lava/dispatcher/tmp/9584814/lava-overlay-0mtn_p8d/lava-9584814/0/tests/0_ltp-ipc test_uuid 9584814_1.5.2.3.1
188 12:48:31.946283 SKIPFILE='skipfile-lkft.yaml'
189 12:48:31.946349 SKIP_INSTALL='true'
190 12:48:31.946411 TST_CMDFILES='ipc'
191 12:48:31.946546 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
193 12:48:31.946766 Creating lava-test-runner.conf files
194 12:48:31.946832 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/9584814/lava-overlay-0mtn_p8d/lava-9584814/0 for stage 0
195 12:48:31.946919 - 0_ltp-ipc
196 12:48:31.947018 end: 1.5.2.3 test-definition (duration 00:00:09) [common]
197 12:48:31.947109 start: 1.5.2.4 compress-overlay (timeout 00:09:42) [common]
198 12:48:39.654365 end: 1.5.2.4 compress-overlay (duration 00:00:08) [common]
199 12:48:39.654540 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:34) [common]
200 12:48:39.654655 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
201 12:48:39.654776 end: 1.5.2 lava-overlay (duration 00:00:16) [common]
202 12:48:39.654885 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:34) [common]
203 12:48:39.757481 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
204 12:48:39.757844 start: 1.5.4 extract-modules (timeout 00:09:34) [common]
205 12:48:39.757967 extracting modules file /var/lib/lava/dispatcher/tmp/9584814/tftp-deploy-ti558n_g/modules/modules.tar to /var/lib/lava/dispatcher/tmp/9584814/extract-nfsrootfs-ywgv904d
206 12:48:39.765724 extracting modules file /var/lib/lava/dispatcher/tmp/9584814/tftp-deploy-ti558n_g/modules/modules.tar to /var/lib/lava/dispatcher/tmp/9584814/extract-overlay-ramdisk-8kvwjs01/ramdisk
207 12:48:39.773167 end: 1.5.4 extract-modules (duration 00:00:00) [common]
208 12:48:39.773286 start: 1.5.5 apply-overlay-tftp (timeout 00:09:34) [common]
209 12:48:39.773385 [common] Applying overlay to NFS
210 12:48:39.773464 [common] Applying overlay /var/lib/lava/dispatcher/tmp/9584814/compress-overlay-z4ximjo3/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/9584814/extract-nfsrootfs-ywgv904d
211 12:48:40.570494 end: 1.5.5 apply-overlay-tftp (duration 00:00:01) [common]
212 12:48:40.570655 start: 1.5.6 configure-preseed-file (timeout 00:09:33) [common]
213 12:48:40.570756 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
214 12:48:40.570846 start: 1.5.7 compress-ramdisk (timeout 00:09:33) [common]
215 12:48:40.570939 Building ramdisk /var/lib/lava/dispatcher/tmp/9584814/extract-overlay-ramdisk-8kvwjs01/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/9584814/extract-overlay-ramdisk-8kvwjs01/ramdisk
216 12:48:40.606780 >> 26158 blocks
217 12:48:41.103593 rename /var/lib/lava/dispatcher/tmp/9584814/extract-overlay-ramdisk-8kvwjs01/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/9584814/tftp-deploy-ti558n_g/ramdisk/ramdisk.cpio.gz
218 12:48:41.104004 end: 1.5.7 compress-ramdisk (duration 00:00:01) [common]
219 12:48:41.104127 start: 1.5.8 prepare-kernel (timeout 00:09:33) [common]
220 12:48:41.104247 start: 1.5.8.1 prepare-fit (timeout 00:09:33) [common]
221 12:48:41.104386 No mkimage arch provided, not using FIT.
222 12:48:41.104585 end: 1.5.8.1 prepare-fit (duration 00:00:00) [common]
223 12:48:41.104754 end: 1.5.8 prepare-kernel (duration 00:00:00) [common]
224 12:48:41.104862 end: 1.5 prepare-tftp-overlay (duration 00:00:20) [common]
225 12:48:41.104957 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:33) [common]
226 12:48:41.105034 No LXC device requested
227 12:48:41.105117 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
228 12:48:41.105217 start: 1.7 deploy-device-env (timeout 00:09:33) [common]
229 12:48:41.105308 end: 1.7 deploy-device-env (duration 00:00:00) [common]
230 12:48:41.105384 Checking files for TFTP limit of 4294967296 bytes.
231 12:48:41.105764 end: 1 tftp-deploy (duration 00:00:27) [common]
232 12:48:41.105917 start: 2 depthcharge-action (timeout 00:05:00) [common]
233 12:48:41.106014 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
234 12:48:41.106143 substitutions:
235 12:48:41.106214 - {DTB}: None
236 12:48:41.106279 - {INITRD}: 9584814/tftp-deploy-ti558n_g/ramdisk/ramdisk.cpio.gz
237 12:48:41.106341 - {KERNEL}: 9584814/tftp-deploy-ti558n_g/kernel/bzImage
238 12:48:41.106408 - {LAVA_MAC}: None
239 12:48:41.106469 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/9584814/extract-nfsrootfs-ywgv904d
240 12:48:41.106530 - {NFS_SERVER_IP}: 192.168.201.1
241 12:48:41.106588 - {PRESEED_CONFIG}: None
242 12:48:41.106646 - {PRESEED_LOCAL}: None
243 12:48:41.106702 - {RAMDISK}: 9584814/tftp-deploy-ti558n_g/ramdisk/ramdisk.cpio.gz
244 12:48:41.106760 - {ROOT_PART}: None
245 12:48:41.106816 - {ROOT}: None
246 12:48:41.106872 - {SERVER_IP}: 192.168.201.1
247 12:48:41.106935 - {TEE}: None
248 12:48:41.106992 Parsed boot commands:
249 12:48:41.107051 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
250 12:48:41.107210 Parsed boot commands: tftpboot 192.168.201.1 9584814/tftp-deploy-ti558n_g/kernel/bzImage 9584814/tftp-deploy-ti558n_g/kernel/cmdline 9584814/tftp-deploy-ti558n_g/ramdisk/ramdisk.cpio.gz
251 12:48:41.107305 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
252 12:48:41.107394 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
253 12:48:41.107497 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
254 12:48:41.107591 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
255 12:48:41.107670 Not connected, no need to disconnect.
256 12:48:41.107752 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
257 12:48:41.107842 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
258 12:48:41.107912 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost asus-cx9400-volteer-cbg-7'
259 12:48:41.110830 Setting prompt string to ['lava-test: # ']
260 12:48:41.111136 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
261 12:48:41.111244 end: 2.2.1 reset-connection (duration 00:00:00) [common]
262 12:48:41.111344 start: 2.2.2 reset-device (timeout 00:05:00) [common]
263 12:48:41.111449 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
264 12:48:41.111621 Calling: 'nice' 'pduclient' '--daemon=localhost' '--hostname=asus-cx9400-volteer-cbg-7' '--port=1' '--command=reboot'
265 12:48:46.242477 >> Command sent successfully.
266 12:48:46.244587 Returned 0 in 5 seconds
267 12:48:46.345386 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
269 12:48:46.345699 end: 2.2.2 reset-device (duration 00:00:05) [common]
270 12:48:46.345800 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
271 12:48:46.345903 Setting prompt string to 'Starting depthcharge on Voema...'
272 12:48:46.345975 Changing prompt to 'Starting depthcharge on Voema...'
273 12:48:46.346047 depthcharge-start: Wait for prompt Starting depthcharge on Voema... (timeout 00:05:00)
274 12:48:46.346310 [Enter `^Ec?' for help]
275 12:48:47.947114
276 12:48:47.947288
277 12:48:47.957463 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 bootblock starting (log level: 8)...
278 12:48:47.960507 CPU: 11th Gen Intel(R) Core(TM) i5-1130G7 @ 1.10GHz
279 12:48:47.967400 CPU: ID 806c1, Tigerlake B0, ucode: 00000086
280 12:48:47.970635 CPU: AES supported, TXT NOT supported, VT supported
281 12:48:47.976975 MCH: device id 9a12 (rev 01) is Tigerlake-Y-4-2
282 12:48:47.983663 PCH: device id a087 (rev 20) is Tigerlake-Y Premium SKU
283 12:48:47.987256 IGD: device id 9a40 (rev 01) is Tigerlake Y GT2
284 12:48:47.990611 VBOOT: Loading verstage.
285 12:48:47.993663 FMAP: Found "FLASH" version 1.1 at 0x1804000.
286 12:48:48.000689 FMAP: base = 0x0 size = 0x2000000 #areas = 32
287 12:48:48.003711 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
288 12:48:48.014177 CBFS: mcache @0xfef45600 built for 70 files, used 0xfdc of 0x1800 bytes
289 12:48:48.021022 CBFS: Found 'fallback/verstage' @0x165e40 size 0x147ec in mcache @0xfef45984
290 12:48:48.021113
291 12:48:48.021180
292 12:48:48.034272 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 verstage starting (log level: 8)...
293 12:48:48.047963 Probing TPM: . done!
294 12:48:48.051578 TPM ready after 0 ms
295 12:48:48.054428 Connected to device vid:did:rid of 1ae0:0028:00
296 12:48:48.065770 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_B:0.6.20/cr50_v1.9308_B.947-551594aae6
297 12:48:48.072623 Current CR50_BOARD_CFG = 0x80000001, matches desired = 0x00000001
298 12:48:48.076172 Initialized TPM device CR50 revision 0
299 12:48:48.144430 tlcl_send_startup: Startup return code is 0
300 12:48:48.145049 TPM: setup succeeded
301 12:48:48.159788 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
302 12:48:48.173801 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
303 12:48:48.186396 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
304 12:48:48.196153 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
305 12:48:48.200068 Chrome EC: UHEPI supported
306 12:48:48.203233 Phase 1
307 12:48:48.206895 FMAP: area GBB found @ 1805000 (458752 bytes)
308 12:48:48.216785 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
309 12:48:48.223399 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
310 12:48:48.230044 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
311 12:48:48.237055 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
312 12:48:48.240091 Recovery requested (1009000e)
313 12:48:48.243491 TPM: Extending digest for VBOOT: boot mode into PCR 0
314 12:48:48.254853 tlcl_extend: response is 0
315 12:48:48.261736 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
316 12:48:48.271324 tlcl_extend: response is 0
317 12:48:48.277675 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
318 12:48:48.284430 CBFS: Found 'fallback/romstage' @0x80 size 0x1bf24 in mcache @0xfef45638
319 12:48:48.290692 BS: verstage times (exec / console): total (unknown) / 142 ms
320 12:48:48.290773
321 12:48:48.290841
322 12:48:48.304162 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 romstage starting (log level: 8)...
323 12:48:48.310788 VB2:vb2api_ec_sync() In recovery mode, skipping EC sync
324 12:48:48.313967 pm1_sts: 0100 pm1_en: 0000 pm1_cnt: 00001c00
325 12:48:48.317220 gpe0_sts[0]: 00200000 gpe0_en[0]: 00000000
326 12:48:48.324180 gpe0_sts[1]: 00000000 gpe0_en[1]: 00000000
327 12:48:48.327276 gpe0_sts[2]: 00001000 gpe0_en[2]: 00000000
328 12:48:48.330587 gpe0_sts[3]: 00000000 gpe0_en[3]: 00010000
329 12:48:48.334279 TCO_STS: 0000 0000
330 12:48:48.337103 GEN_PMCON: d0015038 00002200
331 12:48:48.340716 GBLRST_CAUSE: 00000000 00000000
332 12:48:48.340791 HPR_CAUSE0: 00000000
333 12:48:48.343943 prev_sleep_state 5
334 12:48:48.347189 Boot Count incremented to 17287
335 12:48:48.353990 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
336 12:48:48.360681 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
337 12:48:48.367084 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
338 12:48:48.373747 CBFS: Found 'fspm.bin' @0x78fc0 size 0xa5000 in mcache @0xfef4585c
339 12:48:48.378098 Chrome EC: UHEPI supported
340 12:48:48.385575 FMAP: area RECOVERY_MRC_CACHE found @ f00000 (65536 bytes)
341 12:48:48.398271 Probing TPM: done!
342 12:48:48.405147 Connected to device vid:did:rid of 1ae0:0028:00
343 12:48:48.415054 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_B:0.6.20/cr50_v1.9308_B.947-551594aae6
344 12:48:48.418981 Initialized TPM device CR50 revision 0
345 12:48:48.433583 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x100b return code 0
346 12:48:48.440244 MRC: Hash idx 0x100b comparison successful.
347 12:48:48.443411 MRC cache found, size faa8
348 12:48:48.443500 bootmode is set to: 2
349 12:48:48.446688 SPD index = 0
350 12:48:48.453430 CBFS: Found 'spd.bin' @0x72940 size 0x600 in mcache @0xfef4579c
351 12:48:48.456499 SPD: module type is LPDDR4X
352 12:48:48.460056 SPD: module part number is MT53E512M64D4NW-046
353 12:48:48.466668 SPD: banks 8, ranks 1, rows 16, columns 10, density 8192 Mb
354 12:48:48.469996 SPD: device width 16 bits, bus width 16 bits
355 12:48:48.476266 SPD: module size is 1024 MB (per channel)
356 12:48:48.910247 CBMEM:
357 12:48:48.913786 IMD: root @ 0x76fff000 254 entries.
358 12:48:48.916729 IMD: root @ 0x76ffec00 62 entries.
359 12:48:48.920305 FMAP: area RO_VPD found @ 1800000 (16384 bytes)
360 12:48:48.926824 FMAP: area RW_VPD found @ f35000 (8192 bytes)
361 12:48:48.929779 External stage cache:
362 12:48:48.932993 IMD: root @ 0x7b3ff000 254 entries.
363 12:48:48.936817 IMD: root @ 0x7b3fec00 62 entries.
364 12:48:48.952004 FMAP: area RECOVERY_MRC_CACHE found @ f00000 (65536 bytes)
365 12:48:48.958997 MRC: Checking cached data update for 'RECOVERY_MRC_CACHE'.
366 12:48:48.965289 SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
367 12:48:48.979083 MRC: 'RECOVERY_MRC_CACHE' does not need update.
368 12:48:48.985724 cse_lite: Skip switching to RW in the recovery path
369 12:48:48.985819 8 DIMMs found
370 12:48:48.985893 SMM Memory Map
371 12:48:48.989606 SMRAM : 0x7b000000 0x800000
372 12:48:48.995628 Subregion 0: 0x7b000000 0x200000
373 12:48:48.999180 Subregion 1: 0x7b200000 0x200000
374 12:48:49.002446 Subregion 2: 0x7b400000 0x400000
375 12:48:49.002523 top_of_ram = 0x77000000
376 12:48:49.009119 MTRR Range: Start=76000000 End=77000000 (Size 1000000)
377 12:48:49.015880 MTRR Range: Start=7b000000 End=7b800000 (Size 800000)
378 12:48:49.018946 MTRR Range: Start=f9000000 End=fa000000 (Size 1000000)
379 12:48:49.025534 MTRR Range: Start=ff000000 End=0 (Size 1000000)
380 12:48:49.032620 CBFS: Found 'fallback/postcar' @0x160900 size 0x54f8 in mcache @0xfef4594c
381 12:48:49.038885 Decompressing stage fallback/postcar @ 0x76c0afc0 (38208 bytes)
382 12:48:49.048940 Loading module at 0x76c0b000 with entry 0x76c0b000. filesize: 0x5150 memsize: 0x9500
383 12:48:49.052478 Processing 211 relocs. Offset value of 0x74c0b000
384 12:48:49.062680 BS: romstage times (exec / console): total (unknown) / 277 ms
385 12:48:49.068260
386 12:48:49.068808
387 12:48:49.078381 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 postcar starting (log level: 8)...
388 12:48:49.081571 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
389 12:48:49.091498 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
390 12:48:49.098484 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
391 12:48:49.105162 CBFS: Found 'fallback/ramstage' @0x524c0 size 0x1fbe3 in mcache @0x76c4c0ec
392 12:48:49.111256 Decompressing stage fallback/ramstage @ 0x76b97fc0 (463536 bytes)
393 12:48:49.158572 Loading module at 0x76b98000 with entry 0x76b98000. filesize: 0x4d5d8 memsize: 0x71270
394 12:48:49.162164 Processing 5008 relocs. Offset value of 0x75d98000
395 12:48:49.169013 BS: postcar times (exec / console): total (unknown) / 59 ms
396 12:48:49.169493
397 12:48:49.169851
398 12:48:49.182320 coreboot-v1.9308_26_0.0.22-18730-gcb819b1082 Tue May 4 00:08:52 UTC 2021 ramstage starting (log level: 8)...
399 12:48:49.182778 Normal boot
400 12:48:49.185437 FW_CONFIG value is 0x804c02
401 12:48:49.188542 PCI: 00:07.0 disabled by fw_config
402 12:48:49.192010 PCI: 00:07.1 disabled by fw_config
403 12:48:49.198888 PCI: 00:0d.2 disabled by fw_config
404 12:48:49.201923 PCI: 00:1c.7 disabled by fw_config
405 12:48:49.205514 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
406 12:48:49.211855 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
407 12:48:49.218818 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
408 12:48:49.221941 GENERIC: 0.0 disabled by fw_config
409 12:48:49.225411 GENERIC: 1.0 disabled by fw_config
410 12:48:49.228868 fw_config match found: DB_USB=USB3_ACTIVE
411 12:48:49.232416 fw_config match found: DB_USB=USB3_ACTIVE
412 12:48:49.235237 fw_config match found: DB_USB=USB3_ACTIVE
413 12:48:49.242200 fw_config match found: DB_USB=USB3_ACTIVE
414 12:48:49.245198 FMAP: area COREBOOT found @ 1875000 (7909376 bytes)
415 12:48:49.252094 MMAP window: SPI flash base=0x1000000, Host base=0xff000000, Size=0x1000000
416 12:48:49.261800 MMAP window: SPI flash base=0x500000, Host base=0xf9500000, Size=0xb00000
417 12:48:49.269067 CBFS: Found 'cpu_microcode_blob.bin' @0x1c040 size 0x36400 in mcache @0x76c4c09c
418 12:48:49.272129 microcode: sig=0x806c1 pf=0x80 revision=0x86
419 12:48:49.278315 microcode: Update skipped, already up-to-date
420 12:48:49.285241 CBFS: Found 'fsps.bin' @0x11efc0 size 0x418f9 in mcache @0x76c4c30c
421 12:48:49.312997 Detected 4 core, 8 thread CPU.
422 12:48:49.316196 Setting up SMI for CPU
423 12:48:49.319288 IED base = 0x7b400000
424 12:48:49.319744 IED size = 0x00400000
425 12:48:49.322966 Will perform SMM setup.
426 12:48:49.329543 CPU: 11th Gen Intel(R) Core(TM) i5-1130G7 @ 1.10GHz.
427 12:48:49.336084 Loading module at 0x00030000 with entry 0x00030000. filesize: 0x170 memsize: 0x170
428 12:48:49.342932 Processing 16 relocs. Offset value of 0x00030000
429 12:48:49.346033 Attempting to start 7 APs
430 12:48:49.349308 Waiting for 10ms after sending INIT.
431 12:48:49.364448 Waiting for 1st SIPI to complete...done.
432 12:48:49.364552 AP: slot 1 apic_id 1.
433 12:48:49.371108 Waiting for 2nd SIPI to complete...done.
434 12:48:49.371210 AP: slot 7 apic_id 7.
435 12:48:49.374412 AP: slot 3 apic_id 6.
436 12:48:49.378180 AP: slot 2 apic_id 3.
437 12:48:49.378264 AP: slot 6 apic_id 2.
438 12:48:49.381394 AP: slot 4 apic_id 5.
439 12:48:49.384598 AP: slot 5 apic_id 4.
440 12:48:49.391427 Loading module at 0x00038000 with entry 0x00038000. filesize: 0x1b8 memsize: 0x1b8
441 12:48:49.397832 Processing 13 relocs. Offset value of 0x00038000
442 12:48:49.397920 Unable to locate Global NVS
443 12:48:49.407678 SMM Module: stub loaded at 0x00038000. Will call 0x76bb6318(0x00000000)
444 12:48:49.411312 Installing permanent SMM handler to 0x7b000000
445 12:48:49.421318 Loading module at 0x7b010000 with entry 0x7b010c16. filesize: 0xa7c8 memsize: 0xf908
446 12:48:49.424578 Processing 794 relocs. Offset value of 0x7b010000
447 12:48:49.431485 Loading module at 0x7b008000 with entry 0x7b008000. filesize: 0x1b8 memsize: 0x1b8
448 12:48:49.438047 Processing 13 relocs. Offset value of 0x7b008000
449 12:48:49.444486 SMM Module: placing jmp sequence at 0x7b007c00 rel16 0x03fd
450 12:48:49.451198 SMM Module: placing jmp sequence at 0x7b007800 rel16 0x07fd
451 12:48:49.454306 SMM Module: placing jmp sequence at 0x7b007400 rel16 0x0bfd
452 12:48:49.461288 SMM Module: placing jmp sequence at 0x7b007000 rel16 0x0ffd
453 12:48:49.467603 SMM Module: placing jmp sequence at 0x7b006c00 rel16 0x13fd
454 12:48:49.474271 SMM Module: placing jmp sequence at 0x7b006800 rel16 0x17fd
455 12:48:49.480705 SMM Module: placing jmp sequence at 0x7b006400 rel16 0x1bfd
456 12:48:49.480796 Unable to locate Global NVS
457 12:48:49.487679 SMM Module: stub loaded at 0x7b008000. Will call 0x7b010c16(0x00000000)
458 12:48:49.492548 Clearing SMI status registers
459 12:48:49.495571 SMI_STS: PM1
460 12:48:49.495662 PM1_STS: PWRBTN
461 12:48:49.505498 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7b000000, cpu = 0
462 12:48:49.505606 In relocation handler: CPU 0
463 12:48:49.512421 New SMBASE=0x7b000000 IEDBASE=0x7b400000
464 12:48:49.515476 Writing SMRR. base = 0x7b000006, mask=0xff800c00
465 12:48:49.518940 Relocation complete.
466 12:48:49.525455 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afffc00, cpu = 1
467 12:48:49.529140 In relocation handler: CPU 1
468 12:48:49.532407 New SMBASE=0x7afffc00 IEDBASE=0x7b400000
469 12:48:49.535827 Relocation complete.
470 12:48:49.542421 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affe400, cpu = 7
471 12:48:49.545812 In relocation handler: CPU 7
472 12:48:49.548998 New SMBASE=0x7affe400 IEDBASE=0x7b400000
473 12:48:49.552507 Relocation complete.
474 12:48:49.559101 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff400, cpu = 3
475 12:48:49.562140 In relocation handler: CPU 3
476 12:48:49.565606 New SMBASE=0x7afff400 IEDBASE=0x7b400000
477 12:48:49.571975 Writing SMRR. base = 0x7b000006, mask=0xff800c00
478 12:48:49.572082 Relocation complete.
479 12:48:49.579104 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affe800, cpu = 6
480 12:48:49.582386 In relocation handler: CPU 6
481 12:48:49.585586 New SMBASE=0x7affe800 IEDBASE=0x7b400000
482 12:48:49.591933 Writing SMRR. base = 0x7b000006, mask=0xff800c00
483 12:48:49.595467 Relocation complete.
484 12:48:49.602235 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff800, cpu = 2
485 12:48:49.605457 In relocation handler: CPU 2
486 12:48:49.608894 New SMBASE=0x7afff800 IEDBASE=0x7b400000
487 12:48:49.611961 Relocation complete.
488 12:48:49.618749 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7affec00, cpu = 5
489 12:48:49.622433 In relocation handler: CPU 5
490 12:48:49.625616 New SMBASE=0x7affec00 IEDBASE=0x7b400000
491 12:48:49.629338 Writing SMRR. base = 0x7b000006, mask=0xff800c00
492 12:48:49.633544 Relocation complete.
493 12:48:49.640406 smm_do_relocation : curr_smbase 0x30000 perm_smbase 0x7afff000, cpu = 4
494 12:48:49.643411 In relocation handler: CPU 4
495 12:48:49.646835 New SMBASE=0x7afff000 IEDBASE=0x7b400000
496 12:48:49.646925 Relocation complete.
497 12:48:49.650353 Initializing CPU #0
498 12:48:49.653349 CPU: vendor Intel device 806c1
499 12:48:49.656923 CPU: family 06, model 8c, stepping 01
500 12:48:49.660305 Clearing out pending MCEs
501 12:48:49.663347 Setting up local APIC...
502 12:48:49.667096 apic_id: 0x00 done.
503 12:48:49.667186 Turbo is available but hidden
504 12:48:49.670370 Turbo is available and visible
505 12:48:49.676661 microcode: Update skipped, already up-to-date
506 12:48:49.676750 CPU #0 initialized
507 12:48:49.680388 Initializing CPU #5
508 12:48:49.683485 Initializing CPU #4
509 12:48:49.686526 CPU: vendor Intel device 806c1
510 12:48:49.690285 CPU: family 06, model 8c, stepping 01
511 12:48:49.693377 CPU: vendor Intel device 806c1
512 12:48:49.696588 CPU: family 06, model 8c, stepping 01
513 12:48:49.699884 Clearing out pending MCEs
514 12:48:49.699971 Clearing out pending MCEs
515 12:48:49.703627 Setting up local APIC...
516 12:48:49.706622 Initializing CPU #2
517 12:48:49.706709 Initializing CPU #6
518 12:48:49.709889 CPU: vendor Intel device 806c1
519 12:48:49.716922 CPU: family 06, model 8c, stepping 01
520 12:48:49.717010 Initializing CPU #1
521 12:48:49.720105 CPU: vendor Intel device 806c1
522 12:48:49.723099 CPU: family 06, model 8c, stepping 01
523 12:48:49.726632 Clearing out pending MCEs
524 12:48:49.729720 Clearing out pending MCEs
525 12:48:49.732997 Setting up local APIC...
526 12:48:49.736528 CPU: vendor Intel device 806c1
527 12:48:49.740016 CPU: family 06, model 8c, stepping 01
528 12:48:49.740103 Setting up local APIC...
529 12:48:49.743074 Initializing CPU #3
530 12:48:49.746330 apic_id: 0x04 done.
531 12:48:49.746418 apic_id: 0x05 done.
532 12:48:49.752953 microcode: Update skipped, already up-to-date
533 12:48:49.756706 microcode: Update skipped, already up-to-date
534 12:48:49.759636 CPU #5 initialized
535 12:48:49.759723 CPU #4 initialized
536 12:48:49.762833 CPU: vendor Intel device 806c1
537 12:48:49.766251 CPU: family 06, model 8c, stepping 01
538 12:48:49.769902 Initializing CPU #7
539 12:48:49.773251 Clearing out pending MCEs
540 12:48:49.776486 Clearing out pending MCEs
541 12:48:49.776574 Setting up local APIC...
542 12:48:49.779917 CPU: vendor Intel device 806c1
543 12:48:49.782996 CPU: family 06, model 8c, stepping 01
544 12:48:49.786580 Setting up local APIC...
545 12:48:49.789690 apic_id: 0x02 done.
546 12:48:49.789777 apic_id: 0x03 done.
547 12:48:49.796110 microcode: Update skipped, already up-to-date
548 12:48:49.799457 microcode: Update skipped, already up-to-date
549 12:48:49.802931 CPU #6 initialized
550 12:48:49.803018 CPU #2 initialized
551 12:48:49.806208 apic_id: 0x06 done.
552 12:48:49.809842 Clearing out pending MCEs
553 12:48:49.812993 microcode: Update skipped, already up-to-date
554 12:48:49.816521 Setting up local APIC...
555 12:48:49.819406 Setting up local APIC...
556 12:48:49.819492 apic_id: 0x07 done.
557 12:48:49.823189 CPU #3 initialized
558 12:48:49.826364 microcode: Update skipped, already up-to-date
559 12:48:49.829328 apic_id: 0x01 done.
560 12:48:49.832904 CPU #7 initialized
561 12:48:49.836054 microcode: Update skipped, already up-to-date
562 12:48:49.839875 CPU #1 initialized
563 12:48:49.842873 bsp_do_flight_plan done after 468 msecs.
564 12:48:49.845846 CPU: frequency set to 4000 MHz
565 12:48:49.845934 Enabling SMIs.
566 12:48:49.852610 BS: BS_DEV_INIT_CHIPS entry times (exec / console): 348 / 317 ms
567 12:48:49.869407 SATAXPCIE1 indicates PCIe NVMe is present
568 12:48:49.872843 Probing TPM: done!
569 12:48:49.876301 Connected to device vid:did:rid of 1ae0:0028:00
570 12:48:49.887311 Firmware version: B2-C:0 RO_B:0.0.11/4d655eab RW_B:0.6.20/cr50_v1.9308_B.947-551594aae6
571 12:48:49.890429 Initialized TPM device CR50 revision 0
572 12:48:49.893535 Enabling S0i3.4
573 12:48:49.900887 CBFS: Found 'vbt.bin' @0x78a40 size 0x4f0 in mcache @0x76c4c1fc
574 12:48:49.903926 Found a VBT of 8704 bytes after decompression
575 12:48:49.910303 cse_lite: CSE RO boot. HybridStorageMode disabled
576 12:48:49.916975 WEAK: src/soc/intel/tigerlake/fsp_params.c/mainboard_silicon_init_params called
577 12:48:49.993050 FSPS returned 0
578 12:48:49.996265 Executing Phase 1 of FspMultiPhaseSiInit
579 12:48:50.005963 FSP MultiPhaseSiInit src/soc/intel/tigerlake/fsp_params.c/platform_fsp_multi_phase_init_cb called
580 12:48:50.008982 port C0 DISC req: usage 1 usb3 1 usb2 5
581 12:48:50.012738 Raw Buffer output 0 00000511
582 12:48:50.015869 Raw Buffer output 1 00000000
583 12:48:50.019782 pmc_send_ipc_cmd succeeded
584 12:48:50.026431 port C1 DISC req: usage 1 usb3 2 usb2 3
585 12:48:50.026519 Raw Buffer output 0 00000321
586 12:48:50.029425 Raw Buffer output 1 00000000
587 12:48:50.033596 pmc_send_ipc_cmd succeeded
588 12:48:50.039107 Detected 4 core, 8 thread CPU.
589 12:48:50.041869 Detected 4 core, 8 thread CPU.
590 12:48:50.276114 Display FSP Version Info HOB
591 12:48:50.279428 Reference Code - CPU = a.0.4c.31
592 12:48:50.282505 uCode Version = 0.0.0.86
593 12:48:50.285703 TXT ACM version = ff.ff.ff.ffff
594 12:48:50.289401 Reference Code - ME = a.0.4c.31
595 12:48:50.292566 MEBx version = 0.0.0.0
596 12:48:50.295702 ME Firmware Version = Consumer SKU
597 12:48:50.298810 Reference Code - PCH = a.0.4c.31
598 12:48:50.302555 PCH-CRID Status = Disabled
599 12:48:50.305889 PCH-CRID Original Value = ff.ff.ff.ffff
600 12:48:50.308928 PCH-CRID New Value = ff.ff.ff.ffff
601 12:48:50.312301 OPROM - RST - RAID = ff.ff.ff.ffff
602 12:48:50.315677 PCH Hsio Version = 4.0.0.0
603 12:48:50.319103 Reference Code - SA - System Agent = a.0.4c.31
604 12:48:50.322412 Reference Code - MRC = 2.0.0.1
605 12:48:50.325891 SA - PCIe Version = a.0.4c.31
606 12:48:50.329027 SA-CRID Status = Disabled
607 12:48:50.332034 SA-CRID Original Value = 0.0.0.1
608 12:48:50.335779 SA-CRID New Value = 0.0.0.1
609 12:48:50.338762 OPROM - VBIOS = ff.ff.ff.ffff
610 12:48:50.342505 IO Manageability Engine FW Version = 11.1.4.0
611 12:48:50.345757 PHY Build Version = 0.0.0.e0
612 12:48:50.348898 Thunderbolt(TM) FW Version = 0.0.0.0
613 12:48:50.355480 System Agent Manageability Engine FW Version = ff.ff.ff.ffff
614 12:48:50.359295 ITSS IRQ Polarities Before:
615 12:48:50.359369 IPC0: 0xffffffff
616 12:48:50.362356 IPC1: 0xffffffff
617 12:48:50.362429 IPC2: 0xffffffff
618 12:48:50.365786 IPC3: 0xffffffff
619 12:48:50.369076 ITSS IRQ Polarities After:
620 12:48:50.369164 IPC0: 0xffffffff
621 12:48:50.372386 IPC1: 0xffffffff
622 12:48:50.372491 IPC2: 0xffffffff
623 12:48:50.375377 IPC3: 0xffffffff
624 12:48:50.379248 Found PCIe Root Port #9 at PCI: 00:1d.0.
625 12:48:50.392254 pcie_rp_update_dev: Couldn't find PCIe Root Port #1 (originally PCI: 00:1c.0) which was enabled in devicetree, removing.
626 12:48:50.402222 pcie_rp_update_dev: Couldn't find PCIe Root Port #7 (originally PCI: 00:1c.6) which was enabled in devicetree, removing.
627 12:48:50.415236 pcie_rp_update_dev: Couldn't find PCIe Root Port #11 (originally PCI: 00:1d.2) which was enabled in devicetree, removing.
628 12:48:50.421941 BS: BS_DEV_INIT_CHIPS run times (exec / console): 325 / 236 ms
629 12:48:50.422030 Enumerating buses...
630 12:48:50.428966 Show all devs... Before device enumeration.
631 12:48:50.429085 Root Device: enabled 1
632 12:48:50.431870 DOMAIN: 0000: enabled 1
633 12:48:50.435240 CPU_CLUSTER: 0: enabled 1
634 12:48:50.438357 PCI: 00:00.0: enabled 1
635 12:48:50.438440 PCI: 00:02.0: enabled 1
636 12:48:50.441824 PCI: 00:04.0: enabled 1
637 12:48:50.445597 PCI: 00:05.0: enabled 1
638 12:48:50.448732 PCI: 00:06.0: enabled 0
639 12:48:50.448811 PCI: 00:07.0: enabled 0
640 12:48:50.452077 PCI: 00:07.1: enabled 0
641 12:48:50.455363 PCI: 00:07.2: enabled 0
642 12:48:50.458465 PCI: 00:07.3: enabled 0
643 12:48:50.458542 PCI: 00:08.0: enabled 1
644 12:48:50.462053 PCI: 00:09.0: enabled 0
645 12:48:50.465116 PCI: 00:0a.0: enabled 0
646 12:48:50.468448 PCI: 00:0d.0: enabled 1
647 12:48:50.468531 PCI: 00:0d.1: enabled 0
648 12:48:50.471589 PCI: 00:0d.2: enabled 0
649 12:48:50.475257 PCI: 00:0d.3: enabled 0
650 12:48:50.475335 PCI: 00:0e.0: enabled 0
651 12:48:50.478392 PCI: 00:10.2: enabled 1
652 12:48:50.481490 PCI: 00:10.6: enabled 0
653 12:48:50.485305 PCI: 00:10.7: enabled 0
654 12:48:50.485394 PCI: 00:12.0: enabled 0
655 12:48:50.488561 PCI: 00:12.6: enabled 0
656 12:48:50.491784 PCI: 00:13.0: enabled 0
657 12:48:50.494942 PCI: 00:14.0: enabled 1
658 12:48:50.495035 PCI: 00:14.1: enabled 0
659 12:48:50.498598 PCI: 00:14.2: enabled 1
660 12:48:50.501798 PCI: 00:14.3: enabled 1
661 12:48:50.504933 PCI: 00:15.0: enabled 1
662 12:48:50.505022 PCI: 00:15.1: enabled 1
663 12:48:50.508670 PCI: 00:15.2: enabled 1
664 12:48:50.511822 PCI: 00:15.3: enabled 1
665 12:48:50.515180 PCI: 00:16.0: enabled 1
666 12:48:50.515268 PCI: 00:16.1: enabled 0
667 12:48:50.518166 PCI: 00:16.2: enabled 0
668 12:48:50.521764 PCI: 00:16.3: enabled 0
669 12:48:50.521862 PCI: 00:16.4: enabled 0
670 12:48:50.525094 PCI: 00:16.5: enabled 0
671 12:48:50.528217 PCI: 00:17.0: enabled 1
672 12:48:50.531674 PCI: 00:19.0: enabled 0
673 12:48:50.531763 PCI: 00:19.1: enabled 1
674 12:48:50.534787 PCI: 00:19.2: enabled 0
675 12:48:50.538335 PCI: 00:1c.0: enabled 1
676 12:48:50.541708 PCI: 00:1c.1: enabled 0
677 12:48:50.541797 PCI: 00:1c.2: enabled 0
678 12:48:50.544824 PCI: 00:1c.3: enabled 0
679 12:48:50.548561 PCI: 00:1c.4: enabled 0
680 12:48:50.551652 PCI: 00:1c.5: enabled 0
681 12:48:50.551729 PCI: 00:1c.6: enabled 1
682 12:48:50.555317 PCI: 00:1c.7: enabled 0
683 12:48:50.558387 PCI: 00:1d.0: enabled 1
684 12:48:50.558473 PCI: 00:1d.1: enabled 0
685 12:48:50.561813 PCI: 00:1d.2: enabled 1
686 12:48:50.565068 PCI: 00:1d.3: enabled 0
687 12:48:50.568556 PCI: 00:1e.0: enabled 1
688 12:48:50.568647 PCI: 00:1e.1: enabled 0
689 12:48:50.571644 PCI: 00:1e.2: enabled 1
690 12:48:50.574809 PCI: 00:1e.3: enabled 1
691 12:48:50.578630 PCI: 00:1f.0: enabled 1
692 12:48:50.578711 PCI: 00:1f.1: enabled 0
693 12:48:50.581809 PCI: 00:1f.2: enabled 1
694 12:48:50.584828 PCI: 00:1f.3: enabled 1
695 12:48:50.588292 PCI: 00:1f.4: enabled 0
696 12:48:50.588410 PCI: 00:1f.5: enabled 1
697 12:48:50.591620 PCI: 00:1f.6: enabled 0
698 12:48:50.594588 PCI: 00:1f.7: enabled 0
699 12:48:50.594685 APIC: 00: enabled 1
700 12:48:50.598293 GENERIC: 0.0: enabled 1
701 12:48:50.601475 GENERIC: 0.0: enabled 1
702 12:48:50.605157 GENERIC: 1.0: enabled 1
703 12:48:50.605233 GENERIC: 0.0: enabled 1
704 12:48:50.608432 GENERIC: 1.0: enabled 1
705 12:48:50.611542 USB0 port 0: enabled 1
706 12:48:50.611615 GENERIC: 0.0: enabled 1
707 12:48:50.614575 USB0 port 0: enabled 1
708 12:48:50.618174 GENERIC: 0.0: enabled 1
709 12:48:50.621736 I2C: 00:1a: enabled 1
710 12:48:50.621823 I2C: 00:31: enabled 1
711 12:48:50.625104 I2C: 00:32: enabled 1
712 12:48:50.628275 I2C: 00:10: enabled 1
713 12:48:50.628397 I2C: 00:15: enabled 1
714 12:48:50.631368 GENERIC: 0.0: enabled 0
715 12:48:50.635006 GENERIC: 1.0: enabled 0
716 12:48:50.635093 GENERIC: 0.0: enabled 1
717 12:48:50.638352 SPI: 00: enabled 1
718 12:48:50.641374 SPI: 00: enabled 1
719 12:48:50.641461 PNP: 0c09.0: enabled 1
720 12:48:50.644817 GENERIC: 0.0: enabled 1
721 12:48:50.648352 USB3 port 0: enabled 1
722 12:48:50.651319 USB3 port 1: enabled 1
723 12:48:50.651406 USB3 port 2: enabled 0
724 12:48:50.655098 USB3 port 3: enabled 0
725 12:48:50.658339 USB2 port 0: enabled 0
726 12:48:50.658426 USB2 port 1: enabled 1
727 12:48:50.661411 USB2 port 2: enabled 1
728 12:48:50.664890 USB2 port 3: enabled 0
729 12:48:50.664973 USB2 port 4: enabled 1
730 12:48:50.667886 USB2 port 5: enabled 0
731 12:48:50.671561 USB2 port 6: enabled 0
732 12:48:50.674680 USB2 port 7: enabled 0
733 12:48:50.674759 USB2 port 8: enabled 0
734 12:48:50.678233 USB2 port 9: enabled 0
735 12:48:50.681551 USB3 port 0: enabled 0
736 12:48:50.681628 USB3 port 1: enabled 1
737 12:48:50.684786 USB3 port 2: enabled 0
738 12:48:50.687986 USB3 port 3: enabled 0
739 12:48:50.691623 GENERIC: 0.0: enabled 1
740 12:48:50.691699 GENERIC: 1.0: enabled 1
741 12:48:50.694929 APIC: 01: enabled 1
742 12:48:50.697975 APIC: 03: enabled 1
743 12:48:50.698052 APIC: 06: enabled 1
744 12:48:50.701186 APIC: 05: enabled 1
745 12:48:50.701264 APIC: 04: enabled 1
746 12:48:50.704815 APIC: 02: enabled 1
747 12:48:50.707795 APIC: 07: enabled 1
748 12:48:50.707903 Compare with tree...
749 12:48:50.711544 Root Device: enabled 1
750 12:48:50.714646 DOMAIN: 0000: enabled 1
751 12:48:50.717889 PCI: 00:00.0: enabled 1
752 12:48:50.718019 PCI: 00:02.0: enabled 1
753 12:48:50.721498 PCI: 00:04.0: enabled 1
754 12:48:50.724702 GENERIC: 0.0: enabled 1
755 12:48:50.728106 PCI: 00:05.0: enabled 1
756 12:48:50.728273 PCI: 00:06.0: enabled 0
757 12:48:50.731257 PCI: 00:07.0: enabled 0
758 12:48:50.734692 GENERIC: 0.0: enabled 1
759 12:48:50.738179 PCI: 00:07.1: enabled 0
760 12:48:50.741615 GENERIC: 1.0: enabled 1
761 12:48:50.744804 PCI: 00:07.2: enabled 0
762 12:48:50.745071 GENERIC: 0.0: enabled 1
763 12:48:50.748004 PCI: 00:07.3: enabled 0
764 12:48:50.751424 GENERIC: 1.0: enabled 1
765 12:48:50.754716 PCI: 00:08.0: enabled 1
766 12:48:50.758430 PCI: 00:09.0: enabled 0
767 12:48:50.758890 PCI: 00:0a.0: enabled 0
768 12:48:50.761328 PCI: 00:0d.0: enabled 1
769 12:48:50.765080 USB0 port 0: enabled 1
770 12:48:50.768137 USB3 port 0: enabled 1
771 12:48:50.771541 USB3 port 1: enabled 1
772 12:48:50.772007 USB3 port 2: enabled 0
773 12:48:50.774864 USB3 port 3: enabled 0
774 12:48:50.778107 PCI: 00:0d.1: enabled 0
775 12:48:50.781895 PCI: 00:0d.2: enabled 0
776 12:48:50.785016 GENERIC: 0.0: enabled 1
777 12:48:50.785480 PCI: 00:0d.3: enabled 0
778 12:48:50.788137 PCI: 00:0e.0: enabled 0
779 12:48:50.791408 PCI: 00:10.2: enabled 1
780 12:48:50.795313 PCI: 00:10.6: enabled 0
781 12:48:50.798312 PCI: 00:10.7: enabled 0
782 12:48:50.798765 PCI: 00:12.0: enabled 0
783 12:48:50.801368 PCI: 00:12.6: enabled 0
784 12:48:50.804564 PCI: 00:13.0: enabled 0
785 12:48:50.808113 PCI: 00:14.0: enabled 1
786 12:48:50.811263 USB0 port 0: enabled 1
787 12:48:50.811716 USB2 port 0: enabled 0
788 12:48:50.814536 USB2 port 1: enabled 1
789 12:48:50.818023 USB2 port 2: enabled 1
790 12:48:50.821435 USB2 port 3: enabled 0
791 12:48:50.824590 USB2 port 4: enabled 1
792 12:48:50.825046 USB2 port 5: enabled 0
793 12:48:50.828436 USB2 port 6: enabled 0
794 12:48:50.831396 USB2 port 7: enabled 0
795 12:48:50.835013 USB2 port 8: enabled 0
796 12:48:50.837969 USB2 port 9: enabled 0
797 12:48:50.841587 USB3 port 0: enabled 0
798 12:48:50.842042 USB3 port 1: enabled 1
799 12:48:50.844897 USB3 port 2: enabled 0
800 12:48:50.847848 USB3 port 3: enabled 0
801 12:48:50.851386 PCI: 00:14.1: enabled 0
802 12:48:50.855062 PCI: 00:14.2: enabled 1
803 12:48:50.855522 PCI: 00:14.3: enabled 1
804 12:48:50.857961 GENERIC: 0.0: enabled 1
805 12:48:50.861487 PCI: 00:15.0: enabled 1
806 12:48:50.864538 I2C: 00:1a: enabled 1
807 12:48:50.867985 I2C: 00:31: enabled 1
808 12:48:50.868498 I2C: 00:32: enabled 1
809 12:48:50.871616 PCI: 00:15.1: enabled 1
810 12:48:50.875242 I2C: 00:10: enabled 1
811 12:48:50.878486 PCI: 00:15.2: enabled 1
812 12:48:50.879006 PCI: 00:15.3: enabled 1
813 12:48:50.882373 PCI: 00:16.0: enabled 1
814 12:48:50.885439 PCI: 00:16.1: enabled 0
815 12:48:50.888518 PCI: 00:16.2: enabled 0
816 12:48:50.889038 PCI: 00:16.3: enabled 0
817 12:48:50.892004 PCI: 00:16.4: enabled 0
818 12:48:50.895603 PCI: 00:16.5: enabled 0
819 12:48:50.898733 PCI: 00:17.0: enabled 1
820 12:48:50.902078 PCI: 00:19.0: enabled 0
821 12:48:50.902528 PCI: 00:19.1: enabled 1
822 12:48:50.905193 I2C: 00:15: enabled 1
823 12:48:50.908814 PCI: 00:19.2: enabled 0
824 12:48:50.911835 PCI: 00:1d.0: enabled 1
825 12:48:50.915488 GENERIC: 0.0: enabled 1
826 12:48:50.915939 PCI: 00:1e.0: enabled 1
827 12:48:50.964987 PCI: 00:1e.1: enabled 0
828 12:48:50.965094 PCI: 00:1e.2: enabled 1
829 12:48:50.965367 SPI: 00: enabled 1
830 12:48:50.965449 PCI: 00:1e.3: enabled 1
831 12:48:50.965556 SPI: 00: enabled 1
832 12:48:50.965620 PCI: 00:1f.0: enabled 1
833 12:48:50.965681 PNP: 0c09.0: enabled 1
834 12:48:50.965740 PCI: 00:1f.1: enabled 0
835 12:48:50.965799 PCI: 00:1f.2: enabled 1
836 12:48:50.965857 GENERIC: 0.0: enabled 1
837 12:48:50.965915 GENERIC: 0.0: enabled 1
838 12:48:50.965972 GENERIC: 1.0: enabled 1
839 12:48:50.966218 PCI: 00:1f.3: enabled 1
840 12:48:50.966316 PCI: 00:1f.4: enabled 0
841 12:48:50.966407 PCI: 00:1f.5: enabled 1
842 12:48:50.966481 PCI: 00:1f.6: enabled 0
843 12:48:50.966552 PCI: 00:1f.7: enabled 0
844 12:48:50.966609 CPU_CLUSTER: 0: enabled 1
845 12:48:50.966666 APIC: 00: enabled 1
846 12:48:51.016705 APIC: 01: enabled 1
847 12:48:51.016805 APIC: 03: enabled 1
848 12:48:51.016887 APIC: 06: enabled 1
849 12:48:51.017174 APIC: 05: enabled 1
850 12:48:51.017247 APIC: 04: enabled 1
851 12:48:51.017594 APIC: 02: enabled 1
852 12:48:51.017666 APIC: 07: enabled 1
853 12:48:51.017728 Root Device scanning...
854 12:48:51.017789 scan_static_bus for Root Device
855 12:48:51.017849 DOMAIN: 0000 enabled
856 12:48:51.018090 CPU_CLUSTER: 0 enabled
857 12:48:51.018154 DOMAIN: 0000 scanning...
858 12:48:51.018214 PCI: pci_scan_bus for bus 00
859 12:48:51.018272 PCI: 00:00.0 [8086/0000] ops
860 12:48:51.018329 PCI: 00:00.0 [8086/9a12] enabled
861 12:48:51.018386 PCI: 00:02.0 [8086/0000] bus ops
862 12:48:51.018443 PCI: 00:02.0 [8086/9a40] enabled
863 12:48:51.018681 PCI: 00:04.0 [8086/0000] bus ops
864 12:48:51.023549 PCI: 00:04.0 [8086/9a03] enabled
865 12:48:51.023629 PCI: 00:05.0 [8086/9a19] enabled
866 12:48:51.027362 PCI: 00:07.0 [0000/0000] hidden
867 12:48:51.027448 PCI: 00:08.0 [8086/9a11] enabled
868 12:48:51.033685 PCI: 00:0a.0 [8086/9a0d] disabled
869 12:48:51.036937 PCI: 00:0d.0 [8086/0000] bus ops
870 12:48:51.040639 PCI: 00:0d.0 [8086/9a13] enabled
871 12:48:51.043679 PCI: 00:14.0 [8086/0000] bus ops
872 12:48:51.047024 PCI: 00:14.0 [8086/a0ed] enabled
873 12:48:51.050533 PCI: 00:14.2 [8086/a0ef] enabled
874 12:48:51.053708 PCI: 00:14.3 [8086/0000] bus ops
875 12:48:51.056706 PCI: 00:14.3 [8086/a0f0] enabled
876 12:48:51.060291 PCI: 00:15.0 [8086/0000] bus ops
877 12:48:51.063721 PCI: 00:15.0 [8086/a0e8] enabled
878 12:48:51.067004 PCI: 00:15.1 [8086/0000] bus ops
879 12:48:51.070009 PCI: 00:15.1 [8086/a0e9] enabled
880 12:48:51.073390 PCI: 00:15.2 [8086/0000] bus ops
881 12:48:51.076830 PCI: 00:15.2 [8086/a0ea] enabled
882 12:48:51.080237 PCI: 00:15.3 [8086/0000] bus ops
883 12:48:51.083652 PCI: 00:15.3 [8086/a0eb] enabled
884 12:48:51.083741 PCI: 00:16.0 [8086/0000] ops
885 12:48:51.086761 PCI: 00:16.0 [8086/a0e0] enabled
886 12:48:51.093450 PCI: Static device PCI: 00:17.0 not found, disabling it.
887 12:48:51.096610 PCI: 00:19.0 [8086/0000] bus ops
888 12:48:51.100370 PCI: 00:19.0 [8086/a0c5] disabled
889 12:48:51.103627 PCI: 00:19.1 [8086/0000] bus ops
890 12:48:51.106726 PCI: 00:19.1 [8086/a0c6] enabled
891 12:48:51.109863 PCI: 00:1d.0 [8086/0000] bus ops
892 12:48:51.113681 PCI: 00:1d.0 [8086/a0b0] enabled
893 12:48:51.116821 PCI: 00:1e.0 [8086/0000] ops
894 12:48:51.119970 PCI: 00:1e.0 [8086/a0a8] enabled
895 12:48:51.123464 PCI: 00:1e.2 [8086/0000] bus ops
896 12:48:51.126551 PCI: 00:1e.2 [8086/a0aa] enabled
897 12:48:51.129847 PCI: 00:1e.3 [8086/0000] bus ops
898 12:48:51.133447 PCI: 00:1e.3 [8086/a0ab] enabled
899 12:48:51.136593 PCI: 00:1f.0 [8086/0000] bus ops
900 12:48:51.140248 PCI: 00:1f.0 [8086/a087] enabled
901 12:48:51.140371 RTC Init
902 12:48:51.146689 Set power on after power failure.
903 12:48:51.146775 Disabling Deep S3
904 12:48:51.149965 Disabling Deep S3
905 12:48:51.150051 Disabling Deep S4
906 12:48:51.153464 Disabling Deep S4
907 12:48:51.153557 Disabling Deep S5
908 12:48:51.156494 Disabling Deep S5
909 12:48:51.159830 PCI: 00:1f.2 [0000/0000] hidden
910 12:48:51.163203 PCI: 00:1f.3 [8086/0000] bus ops
911 12:48:51.166817 PCI: 00:1f.3 [8086/a0c8] enabled
912 12:48:51.170003 PCI: 00:1f.5 [8086/0000] bus ops
913 12:48:51.173610 PCI: 00:1f.5 [8086/a0a4] enabled
914 12:48:51.176436 PCI: Leftover static devices:
915 12:48:51.176523 PCI: 00:10.2
916 12:48:51.179908 PCI: 00:10.6
917 12:48:51.179993 PCI: 00:10.7
918 12:48:51.180060 PCI: 00:06.0
919 12:48:51.183243 PCI: 00:07.1
920 12:48:51.183329 PCI: 00:07.2
921 12:48:51.186552 PCI: 00:07.3
922 12:48:51.186638 PCI: 00:09.0
923 12:48:51.190005 PCI: 00:0d.1
924 12:48:51.190091 PCI: 00:0d.2
925 12:48:51.190157 PCI: 00:0d.3
926 12:48:51.192983 PCI: 00:0e.0
927 12:48:51.193100 PCI: 00:12.0
928 12:48:51.196686 PCI: 00:12.6
929 12:48:51.196772 PCI: 00:13.0
930 12:48:51.196839 PCI: 00:14.1
931 12:48:51.199733 PCI: 00:16.1
932 12:48:51.199819 PCI: 00:16.2
933 12:48:51.203528 PCI: 00:16.3
934 12:48:51.203614 PCI: 00:16.4
935 12:48:51.203681 PCI: 00:16.5
936 12:48:51.206789 PCI: 00:17.0
937 12:48:51.206874 PCI: 00:19.2
938 12:48:51.209797 PCI: 00:1e.1
939 12:48:51.209883 PCI: 00:1f.1
940 12:48:51.213482 PCI: 00:1f.4
941 12:48:51.213567 PCI: 00:1f.6
942 12:48:51.213634 PCI: 00:1f.7
943 12:48:51.216601 PCI: Check your devicetree.cb.
944 12:48:51.219743 PCI: 00:02.0 scanning...
945 12:48:51.223400 scan_generic_bus for PCI: 00:02.0
946 12:48:51.226756 scan_generic_bus for PCI: 00:02.0 done
947 12:48:51.233271 scan_bus: bus PCI: 00:02.0 finished in 7 msecs
948 12:48:51.236640 PCI: 00:04.0 scanning...
949 12:48:51.239832 scan_generic_bus for PCI: 00:04.0
950 12:48:51.239917 GENERIC: 0.0 enabled
951 12:48:51.246274 bus: PCI: 00:04.0[0]->scan_generic_bus for PCI: 00:04.0 done
952 12:48:51.252960 scan_bus: bus PCI: 00:04.0 finished in 11 msecs
953 12:48:51.253046 PCI: 00:0d.0 scanning...
954 12:48:51.256063 scan_static_bus for PCI: 00:0d.0
955 12:48:51.259870 USB0 port 0 enabled
956 12:48:51.262831 USB0 port 0 scanning...
957 12:48:51.266426 scan_static_bus for USB0 port 0
958 12:48:51.266516 USB3 port 0 enabled
959 12:48:51.269270 USB3 port 1 enabled
960 12:48:51.272869 USB3 port 2 disabled
961 12:48:51.272973 USB3 port 3 disabled
962 12:48:51.276268 USB3 port 0 scanning...
963 12:48:51.279319 scan_static_bus for USB3 port 0
964 12:48:51.282700 scan_static_bus for USB3 port 0 done
965 12:48:51.289236 scan_bus: bus USB3 port 0 finished in 6 msecs
966 12:48:51.289328 USB3 port 1 scanning...
967 12:48:51.292588 scan_static_bus for USB3 port 1
968 12:48:51.299466 scan_static_bus for USB3 port 1 done
969 12:48:51.303062 scan_bus: bus USB3 port 1 finished in 6 msecs
970 12:48:51.306042 scan_static_bus for USB0 port 0 done
971 12:48:51.309301 scan_bus: bus USB0 port 0 finished in 43 msecs
972 12:48:51.316147 scan_static_bus for PCI: 00:0d.0 done
973 12:48:51.319484 scan_bus: bus PCI: 00:0d.0 finished in 60 msecs
974 12:48:51.322618 PCI: 00:14.0 scanning...
975 12:48:51.325892 scan_static_bus for PCI: 00:14.0
976 12:48:51.325982 USB0 port 0 enabled
977 12:48:51.329455 USB0 port 0 scanning...
978 12:48:51.332531 scan_static_bus for USB0 port 0
979 12:48:51.335759 USB2 port 0 disabled
980 12:48:51.339405 USB2 port 1 enabled
981 12:48:51.339494 USB2 port 2 enabled
982 12:48:51.342382 USB2 port 3 disabled
983 12:48:51.342471 USB2 port 4 enabled
984 12:48:51.346225 USB2 port 5 disabled
985 12:48:51.349314 USB2 port 6 disabled
986 12:48:51.349402 USB2 port 7 disabled
987 12:48:51.352417 USB2 port 8 disabled
988 12:48:51.356178 USB2 port 9 disabled
989 12:48:51.356267 USB3 port 0 disabled
990 12:48:51.359407 USB3 port 1 enabled
991 12:48:51.362404 USB3 port 2 disabled
992 12:48:51.362493 USB3 port 3 disabled
993 12:48:51.366246 USB2 port 1 scanning...
994 12:48:51.369181 scan_static_bus for USB2 port 1
995 12:48:51.372365 scan_static_bus for USB2 port 1 done
996 12:48:51.375862 scan_bus: bus USB2 port 1 finished in 6 msecs
997 12:48:51.379472 USB2 port 2 scanning...
998 12:48:51.382465 scan_static_bus for USB2 port 2
999 12:48:51.385554 scan_static_bus for USB2 port 2 done
1000 12:48:51.392231 scan_bus: bus USB2 port 2 finished in 6 msecs
1001 12:48:51.392329 USB2 port 4 scanning...
1002 12:48:51.395841 scan_static_bus for USB2 port 4
1003 12:48:51.402612 scan_static_bus for USB2 port 4 done
1004 12:48:51.405879 scan_bus: bus USB2 port 4 finished in 6 msecs
1005 12:48:51.409585 USB3 port 1 scanning...
1006 12:48:51.412662 scan_static_bus for USB3 port 1
1007 12:48:51.415918 scan_static_bus for USB3 port 1 done
1008 12:48:51.419088 scan_bus: bus USB3 port 1 finished in 6 msecs
1009 12:48:51.422353 scan_static_bus for USB0 port 0 done
1010 12:48:51.429169 scan_bus: bus USB0 port 0 finished in 93 msecs
1011 12:48:51.433002 scan_static_bus for PCI: 00:14.0 done
1012 12:48:51.435727 scan_bus: bus PCI: 00:14.0 finished in 110 msecs
1013 12:48:51.439115 PCI: 00:14.3 scanning...
1014 12:48:51.442601 scan_static_bus for PCI: 00:14.3
1015 12:48:51.445890 GENERIC: 0.0 enabled
1016 12:48:51.449895 scan_static_bus for PCI: 00:14.3 done
1017 12:48:51.453449 scan_bus: bus PCI: 00:14.3 finished in 9 msecs
1018 12:48:51.456668 PCI: 00:15.0 scanning...
1019 12:48:51.459667 scan_static_bus for PCI: 00:15.0
1020 12:48:51.462814 I2C: 00:1a enabled
1021 12:48:51.462903 I2C: 00:31 enabled
1022 12:48:51.466748 I2C: 00:32 enabled
1023 12:48:51.469810 scan_static_bus for PCI: 00:15.0 done
1024 12:48:51.473023 scan_bus: bus PCI: 00:15.0 finished in 12 msecs
1025 12:48:51.476240 PCI: 00:15.1 scanning...
1026 12:48:51.479455 scan_static_bus for PCI: 00:15.1
1027 12:48:51.482775 I2C: 00:10 enabled
1028 12:48:51.486557 scan_static_bus for PCI: 00:15.1 done
1029 12:48:51.489507 scan_bus: bus PCI: 00:15.1 finished in 9 msecs
1030 12:48:51.492902 PCI: 00:15.2 scanning...
1031 12:48:51.496006 scan_static_bus for PCI: 00:15.2
1032 12:48:51.499299 scan_static_bus for PCI: 00:15.2 done
1033 12:48:51.506056 scan_bus: bus PCI: 00:15.2 finished in 7 msecs
1034 12:48:51.509470 PCI: 00:15.3 scanning...
1035 12:48:51.512812 scan_static_bus for PCI: 00:15.3
1036 12:48:51.515988 scan_static_bus for PCI: 00:15.3 done
1037 12:48:51.519165 scan_bus: bus PCI: 00:15.3 finished in 7 msecs
1038 12:48:51.522705 PCI: 00:19.1 scanning...
1039 12:48:51.525845 scan_static_bus for PCI: 00:19.1
1040 12:48:51.529448 I2C: 00:15 enabled
1041 12:48:51.532620 scan_static_bus for PCI: 00:19.1 done
1042 12:48:51.535842 scan_bus: bus PCI: 00:19.1 finished in 9 msecs
1043 12:48:51.539363 PCI: 00:1d.0 scanning...
1044 12:48:51.542446 do_pci_scan_bridge for PCI: 00:1d.0
1045 12:48:51.546179 PCI: pci_scan_bus for bus 01
1046 12:48:51.549432 PCI: 01:00.0 [1c5c/174a] enabled
1047 12:48:51.552572 GENERIC: 0.0 enabled
1048 12:48:51.556121 Enabling Common Clock Configuration
1049 12:48:51.559399 L1 Sub-State supported from root port 29
1050 12:48:51.562433 L1 Sub-State Support = 0xf
1051 12:48:51.566082 CommonModeRestoreTime = 0x28
1052 12:48:51.569247 Power On Value = 0x16, Power On Scale = 0x0
1053 12:48:51.572264 ASPM: Enabled L1
1054 12:48:51.575990 PCIe: Max_Payload_Size adjusted to 128
1055 12:48:51.579069 scan_bus: bus PCI: 00:1d.0 finished in 35 msecs
1056 12:48:51.582314 PCI: 00:1e.2 scanning...
1057 12:48:51.585719 scan_generic_bus for PCI: 00:1e.2
1058 12:48:51.588905 SPI: 00 enabled
1059 12:48:51.595732 bus: PCI: 00:1e.2[0]->scan_generic_bus for PCI: 00:1e.2 done
1060 12:48:51.598694 scan_bus: bus PCI: 00:1e.2 finished in 11 msecs
1061 12:48:51.602292 PCI: 00:1e.3 scanning...
1062 12:48:51.605186 scan_generic_bus for PCI: 00:1e.3
1063 12:48:51.605276 SPI: 00 enabled
1064 12:48:51.612206 bus: PCI: 00:1e.3[0]->scan_generic_bus for PCI: 00:1e.3 done
1065 12:48:51.618378 scan_bus: bus PCI: 00:1e.3 finished in 11 msecs
1066 12:48:51.618472 PCI: 00:1f.0 scanning...
1067 12:48:51.625254 scan_static_bus for PCI: 00:1f.0
1068 12:48:51.625350 PNP: 0c09.0 enabled
1069 12:48:51.628550 PNP: 0c09.0 scanning...
1070 12:48:51.631761 scan_static_bus for PNP: 0c09.0
1071 12:48:51.634847 scan_static_bus for PNP: 0c09.0 done
1072 12:48:51.638534 scan_bus: bus PNP: 0c09.0 finished in 6 msecs
1073 12:48:51.645437 scan_static_bus for PCI: 00:1f.0 done
1074 12:48:51.648510 scan_bus: bus PCI: 00:1f.0 finished in 23 msecs
1075 12:48:51.651652 PCI: 00:1f.2 scanning...
1076 12:48:51.654985 scan_static_bus for PCI: 00:1f.2
1077 12:48:51.658773 GENERIC: 0.0 enabled
1078 12:48:51.658862 GENERIC: 0.0 scanning...
1079 12:48:51.661806 scan_static_bus for GENERIC: 0.0
1080 12:48:51.665183 GENERIC: 0.0 enabled
1081 12:48:51.668331 GENERIC: 1.0 enabled
1082 12:48:51.671653 scan_static_bus for GENERIC: 0.0 done
1083 12:48:51.675226 scan_bus: bus GENERIC: 0.0 finished in 11 msecs
1084 12:48:51.678457 scan_static_bus for PCI: 00:1f.2 done
1085 12:48:51.684748 scan_bus: bus PCI: 00:1f.2 finished in 28 msecs
1086 12:48:51.688202 PCI: 00:1f.3 scanning...
1087 12:48:51.691428 scan_static_bus for PCI: 00:1f.3
1088 12:48:51.694621 scan_static_bus for PCI: 00:1f.3 done
1089 12:48:51.698188 scan_bus: bus PCI: 00:1f.3 finished in 7 msecs
1090 12:48:51.701720 PCI: 00:1f.5 scanning...
1091 12:48:51.705039 scan_generic_bus for PCI: 00:1f.5
1092 12:48:51.708032 scan_generic_bus for PCI: 00:1f.5 done
1093 12:48:51.714968 scan_bus: bus PCI: 00:1f.5 finished in 7 msecs
1094 12:48:51.718252 scan_bus: bus DOMAIN: 0000 finished in 717 msecs
1095 12:48:51.721198 scan_static_bus for Root Device done
1096 12:48:51.728221 scan_bus: bus Root Device finished in 736 msecs
1097 12:48:51.728329 done
1098 12:48:51.734820 BS: BS_DEV_ENUMERATE run times (exec / console): 11 / 1296 ms
1099 12:48:51.737991 Chrome EC: UHEPI supported
1100 12:48:51.744827 FMAP: area UNIFIED_MRC_CACHE found @ f00000 (196608 bytes)
1101 12:48:51.751561 SF: Detected 00 0000 with sector size 0x1000, total 0x2000000
1102 12:48:51.754680 SPI flash protection: WPSW=0 SRP0=0
1103 12:48:51.757982 MRC: NOT enabling PRR for 'UNIFIED_MRC_CACHE'.
1104 12:48:51.764660 BS: BS_DEV_ENUMERATE exit times (exec / console): 1 / 23 ms
1105 12:48:51.768170 found VGA at PCI: 00:02.0
1106 12:48:51.771894 Setting up VGA for PCI: 00:02.0
1107 12:48:51.774943 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000
1108 12:48:51.781688 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device
1109 12:48:51.782192 Allocating resources...
1110 12:48:51.785038 Reading resources...
1111 12:48:51.788063 Root Device read_resources bus 0 link: 0
1112 12:48:51.795025 DOMAIN: 0000 read_resources bus 0 link: 0
1113 12:48:51.798361 PCI: 00:04.0 read_resources bus 1 link: 0
1114 12:48:51.804890 PCI: 00:04.0 read_resources bus 1 link: 0 done
1115 12:48:51.807886 PCI: 00:0d.0 read_resources bus 0 link: 0
1116 12:48:51.814531 USB0 port 0 read_resources bus 0 link: 0
1117 12:48:51.818148 USB0 port 0 read_resources bus 0 link: 0 done
1118 12:48:51.824932 PCI: 00:0d.0 read_resources bus 0 link: 0 done
1119 12:48:51.827899 PCI: 00:14.0 read_resources bus 0 link: 0
1120 12:48:51.831327 USB0 port 0 read_resources bus 0 link: 0
1121 12:48:51.838678 USB0 port 0 read_resources bus 0 link: 0 done
1122 12:48:51.842376 PCI: 00:14.0 read_resources bus 0 link: 0 done
1123 12:48:51.848944 PCI: 00:14.3 read_resources bus 0 link: 0
1124 12:48:51.852377 PCI: 00:14.3 read_resources bus 0 link: 0 done
1125 12:48:51.858613 PCI: 00:15.0 read_resources bus 0 link: 0
1126 12:48:51.862300 PCI: 00:15.0 read_resources bus 0 link: 0 done
1127 12:48:51.868657 PCI: 00:15.1 read_resources bus 0 link: 0
1128 12:48:51.872303 PCI: 00:15.1 read_resources bus 0 link: 0 done
1129 12:48:51.879066 PCI: 00:19.1 read_resources bus 0 link: 0
1130 12:48:51.882743 PCI: 00:19.1 read_resources bus 0 link: 0 done
1131 12:48:51.888975 PCI: 00:1d.0 read_resources bus 1 link: 0
1132 12:48:51.892864 PCI: 00:1d.0 read_resources bus 1 link: 0 done
1133 12:48:51.899197 PCI: 00:1e.2 read_resources bus 2 link: 0
1134 12:48:51.902546 PCI: 00:1e.2 read_resources bus 2 link: 0 done
1135 12:48:51.909245 PCI: 00:1e.3 read_resources bus 3 link: 0
1136 12:48:51.912963 PCI: 00:1e.3 read_resources bus 3 link: 0 done
1137 12:48:51.919125 PCI: 00:1f.0 read_resources bus 0 link: 0
1138 12:48:51.922379 PCI: 00:1f.0 read_resources bus 0 link: 0 done
1139 12:48:51.925663 PCI: 00:1f.2 read_resources bus 0 link: 0
1140 12:48:51.932669 GENERIC: 0.0 read_resources bus 0 link: 0
1141 12:48:51.935754 GENERIC: 0.0 read_resources bus 0 link: 0 done
1142 12:48:51.942556 PCI: 00:1f.2 read_resources bus 0 link: 0 done
1143 12:48:51.949135 DOMAIN: 0000 read_resources bus 0 link: 0 done
1144 12:48:51.952911 CPU_CLUSTER: 0 read_resources bus 0 link: 0
1145 12:48:51.955930 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
1146 12:48:51.962714 Root Device read_resources bus 0 link: 0 done
1147 12:48:51.966323 Done reading resources.
1148 12:48:51.969553 Show resources in subtree (Root Device)...After reading.
1149 12:48:51.976247 Root Device child on link 0 DOMAIN: 0000
1150 12:48:51.979524 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1151 12:48:51.989549 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1152 12:48:51.999612 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100
1153 12:48:52.000096 PCI: 00:00.0
1154 12:48:52.009342 PCI: 00:00.0 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1155 12:48:52.019352 PCI: 00:00.0 resource base fedc0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1
1156 12:48:52.029128 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1157 12:48:52.039071 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1158 12:48:52.045919 PCI: 00:00.0 resource base fb000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1159 12:48:52.055429 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1160 12:48:52.065881 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 6
1161 12:48:52.075613 PCI: 00:00.0 resource base fed92000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1162 12:48:52.085720 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1163 12:48:52.095861 PCI: 00:00.0 resource base fed85000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9
1164 12:48:52.102223 PCI: 00:00.0 resource base fed86000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
1165 12:48:52.112426 PCI: 00:00.0 resource base fed87000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b
1166 12:48:52.122288 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c
1167 12:48:52.132114 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index d
1168 12:48:52.138875 PCI: 00:00.0 resource base c0000 size 76f40000 align 0 gran 0 limit 0 flags e0004200 index e
1169 12:48:52.148678 PCI: 00:00.0 resource base 77000000 size 8c00000 align 0 gran 0 limit 0 flags f0000200 index f
1170 12:48:52.158672 PCI: 00:00.0 resource base 100000000 size 180400000 align 0 gran 0 limit 0 flags e0004200 index 10
1171 12:48:52.168269 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11
1172 12:48:52.178807 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12
1173 12:48:52.188456 PCI: 00:00.0 resource base f8000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 13
1174 12:48:52.188913 PCI: 00:02.0
1175 12:48:52.201787 PCI: 00:02.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1176 12:48:52.211888 PCI: 00:02.0 resource base 0 size 10000000 align 28 gran 28 limit ffffffffffffffff flags 1201 index 18
1177 12:48:52.218169 PCI: 00:02.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 20
1178 12:48:52.224843 PCI: 00:04.0 child on link 0 GENERIC: 0.0
1179 12:48:52.235116 PCI: 00:04.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 201 index 10
1180 12:48:52.235328 GENERIC: 0.0
1181 12:48:52.237977 PCI: 00:05.0
1182 12:48:52.247878 PCI: 00:05.0 resource base 0 size 1000000 align 24 gran 24 limit ffffffffffffffff flags 201 index 10
1183 12:48:52.251459 PCI: 00:07.0 child on link 0 GENERIC: 0.0
1184 12:48:52.254389 GENERIC: 0.0
1185 12:48:52.254476 PCI: 00:08.0
1186 12:48:52.264491 PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1187 12:48:52.267875 PCI: 00:0a.0
1188 12:48:52.270909 PCI: 00:0d.0 child on link 0 USB0 port 0
1189 12:48:52.281238 PCI: 00:0d.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1190 12:48:52.284494 USB0 port 0 child on link 0 USB3 port 0
1191 12:48:52.287562 USB3 port 0
1192 12:48:52.287649 USB3 port 1
1193 12:48:52.291336 USB3 port 2
1194 12:48:52.291423 USB3 port 3
1195 12:48:52.297637 PCI: 00:14.0 child on link 0 USB0 port 0
1196 12:48:52.307762 PCI: 00:14.0 resource base 0 size 10000 align 16 gran 16 limit ffffffffffffffff flags 201 index 10
1197 12:48:52.310930 USB0 port 0 child on link 0 USB2 port 0
1198 12:48:52.314471 USB2 port 0
1199 12:48:52.314565 USB2 port 1
1200 12:48:52.317477 USB2 port 2
1201 12:48:52.317567 USB2 port 3
1202 12:48:52.321224 USB2 port 4
1203 12:48:52.321315 USB2 port 5
1204 12:48:52.324524 USB2 port 6
1205 12:48:52.324611 USB2 port 7
1206 12:48:52.327530 USB2 port 8
1207 12:48:52.327618 USB2 port 9
1208 12:48:52.330855 USB3 port 0
1209 12:48:52.330942 USB3 port 1
1210 12:48:52.334612 USB3 port 2
1211 12:48:52.334699 USB3 port 3
1212 12:48:52.337579 PCI: 00:14.2
1213 12:48:52.347645 PCI: 00:14.2 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1214 12:48:52.357493 PCI: 00:14.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 18
1215 12:48:52.360925 PCI: 00:14.3 child on link 0 GENERIC: 0.0
1216 12:48:52.370863 PCI: 00:14.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1217 12:48:52.374226 GENERIC: 0.0
1218 12:48:52.378006 PCI: 00:15.0 child on link 0 I2C: 00:1a
1219 12:48:52.387723 PCI: 00:15.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1220 12:48:52.391076 I2C: 00:1a
1221 12:48:52.391165 I2C: 00:31
1222 12:48:52.394171 I2C: 00:32
1223 12:48:52.397496 PCI: 00:15.1 child on link 0 I2C: 00:10
1224 12:48:52.407252 PCI: 00:15.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1225 12:48:52.407342 I2C: 00:10
1226 12:48:52.410865 PCI: 00:15.2
1227 12:48:52.420800 PCI: 00:15.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1228 12:48:52.420890 PCI: 00:15.3
1229 12:48:52.430938 PCI: 00:15.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1230 12:48:52.434019 PCI: 00:16.0
1231 12:48:52.444167 PCI: 00:16.0 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1232 12:48:52.444261 PCI: 00:19.0
1233 12:48:52.450931 PCI: 00:19.1 child on link 0 I2C: 00:15
1234 12:48:52.460652 PCI: 00:19.1 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1235 12:48:52.460737 I2C: 00:15
1236 12:48:52.464029 PCI: 00:1d.0 child on link 0 GENERIC: 0.0
1237 12:48:52.473746 PCI: 00:1d.0 resource base 0 size 0 align 12 gran 12 limit ffff flags 80102 index 1c
1238 12:48:52.483783 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24
1239 12:48:52.493836 PCI: 00:1d.0 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20
1240 12:48:52.493932 GENERIC: 0.0
1241 12:48:52.497333 PCI: 01:00.0
1242 12:48:52.507119 PCI: 01:00.0 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1243 12:48:52.517219 PCI: 01:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 18
1244 12:48:52.523706 PCI: 01:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 1c
1245 12:48:52.526871 PCI: 00:1e.0
1246 12:48:52.536908 PCI: 00:1e.0 resource base fe03e000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1247 12:48:52.543236 PCI: 00:1e.2 child on link 0 SPI: 00
1248 12:48:52.553671 PCI: 00:1e.2 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1249 12:48:52.553754 SPI: 00
1250 12:48:52.556905 PCI: 00:1e.3 child on link 0 SPI: 00
1251 12:48:52.566943 PCI: 00:1e.3 resource base 0 size 1000 align 12 gran 12 limit ffffffffffffffff flags 201 index 10
1252 12:48:52.567427 SPI: 00
1253 12:48:52.573807 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1254 12:48:52.580196 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1255 12:48:52.583557 PNP: 0c09.0
1256 12:48:52.593860 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1257 12:48:52.597305 PCI: 00:1f.2 child on link 0 GENERIC: 0.0
1258 12:48:52.606919 PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0
1259 12:48:52.616869 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1
1260 12:48:52.620020 GENERIC: 0.0 child on link 0 GENERIC: 0.0
1261 12:48:52.620571 GENERIC: 0.0
1262 12:48:52.623775 GENERIC: 1.0
1263 12:48:52.627019 PCI: 00:1f.3
1264 12:48:52.637022 PCI: 00:1f.3 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10
1265 12:48:52.646826 PCI: 00:1f.3 resource base 0 size 100000 align 20 gran 20 limit ffffffffffffffff flags 201 index 20
1266 12:48:52.647281 PCI: 00:1f.5
1267 12:48:52.656890 PCI: 00:1f.5 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10
1268 12:48:52.659985 CPU_CLUSTER: 0 child on link 0 APIC: 00
1269 12:48:52.660577 APIC: 00
1270 12:48:52.662997 APIC: 01
1271 12:48:52.663451 APIC: 03
1272 12:48:52.666801 APIC: 06
1273 12:48:52.667272 APIC: 05
1274 12:48:52.667700 APIC: 04
1275 12:48:52.670053 APIC: 02
1276 12:48:52.670578 APIC: 07
1277 12:48:52.679776 ==== Resource allocator: DOMAIN: 0000 - Pass 1 (gathering requirements) ===
1278 12:48:52.683053 PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff
1279 12:48:52.689699 PCI: 00:1d.0 io: size: 0 align: 12 gran: 12 limit: ffff done
1280 12:48:52.696213 PCI: 00:1d.0 mem: size: 0 align: 20 gran: 20 limit: ffffffff
1281 12:48:52.699964 PCI: 01:00.0 10 * [0x0 - 0x3fff] mem
1282 12:48:52.703300 PCI: 01:00.0 18 * [0x4000 - 0x4fff] mem
1283 12:48:52.709607 PCI: 01:00.0 1c * [0x5000 - 0x5fff] mem
1284 12:48:52.716743 PCI: 00:1d.0 mem: size: 100000 align: 20 gran: 20 limit: ffffffff done
1285 12:48:52.722904 PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff
1286 12:48:52.729985 PCI: 00:1d.0 prefmem: size: 0 align: 20 gran: 20 limit: ffffffffffffffff done
1287 12:48:52.739165 === Resource allocator: DOMAIN: 0000 - Pass 2 (allocating resources) ===
1288 12:48:52.742528 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff
1289 12:48:52.752597 update_constraints: PCI: 00:1f.0 00 base 00000000 limit 00000fff io (fixed)
1290 12:48:52.759641 update_constraints: PNP: 0c09.0 00 base 00000800 limit 000009fe io (fixed)
1291 12:48:52.766163 update_constraints: PCI: 00:1f.2 01 base 00001800 limit 000018ff io (fixed)
1292 12:48:52.769185 DOMAIN: 0000: Resource ranges:
1293 12:48:52.772672 * Base: 1000, Size: 800, Tag: 100
1294 12:48:52.775824 * Base: 1900, Size: e700, Tag: 100
1295 12:48:52.782519 PCI: 00:02.0 20 * [0x1000 - 0x103f] limit: 103f io
1296 12:48:52.788852 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff done
1297 12:48:52.795656 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff
1298 12:48:52.802220 update_constraints: PCI: 00:00.0 00 base c0000000 limit cfffffff mem (fixed)
1299 12:48:52.812036 update_constraints: PCI: 00:00.0 01 base fedc0000 limit feddffff mem (fixed)
1300 12:48:52.818738 update_constraints: PCI: 00:00.0 02 base feda0000 limit feda0fff mem (fixed)
1301 12:48:52.825647 update_constraints: PCI: 00:00.0 03 base feda1000 limit feda1fff mem (fixed)
1302 12:48:52.835547 update_constraints: PCI: 00:00.0 04 base fb000000 limit fb000fff mem (fixed)
1303 12:48:52.842420 update_constraints: PCI: 00:00.0 05 base fed80000 limit fed83fff mem (fixed)
1304 12:48:52.848803 update_constraints: PCI: 00:00.0 06 base fed90000 limit fed90fff mem (fixed)
1305 12:48:52.858928 update_constraints: PCI: 00:00.0 07 base fed92000 limit fed92fff mem (fixed)
1306 12:48:52.865277 update_constraints: PCI: 00:00.0 08 base fed84000 limit fed84fff mem (fixed)
1307 12:48:52.872111 update_constraints: PCI: 00:00.0 09 base fed85000 limit fed85fff mem (fixed)
1308 12:48:52.882051 update_constraints: PCI: 00:00.0 0a base fed86000 limit fed86fff mem (fixed)
1309 12:48:52.888404 update_constraints: PCI: 00:00.0 0b base fed87000 limit fed87fff mem (fixed)
1310 12:48:52.895182 update_constraints: PCI: 00:00.0 0c base fed91000 limit fed91fff mem (fixed)
1311 12:48:52.905342 update_constraints: PCI: 00:00.0 0d base 00000000 limit 0009ffff mem (fixed)
1312 12:48:52.911692 update_constraints: PCI: 00:00.0 0e base 000c0000 limit 76ffffff mem (fixed)
1313 12:48:52.918684 update_constraints: PCI: 00:00.0 0f base 77000000 limit 7fbfffff mem (fixed)
1314 12:48:52.928370 update_constraints: PCI: 00:00.0 10 base 100000000 limit 2803fffff mem (fixed)
1315 12:48:52.935258 update_constraints: PCI: 00:00.0 11 base 000a0000 limit 000bffff mem (fixed)
1316 12:48:52.942116 update_constraints: PCI: 00:00.0 12 base 000c0000 limit 000fffff mem (fixed)
1317 12:48:52.951770 update_constraints: PCI: 00:00.0 13 base f8000000 limit f9ffffff mem (fixed)
1318 12:48:52.958580 update_constraints: PCI: 00:1e.0 10 base fe03e000 limit fe03efff mem (fixed)
1319 12:48:52.965050 update_constraints: PCI: 00:1f.2 00 base fe000000 limit fe00ffff mem (fixed)
1320 12:48:52.968346 DOMAIN: 0000: Resource ranges:
1321 12:48:52.975127 * Base: 7fc00000, Size: 40400000, Tag: 200
1322 12:48:52.978420 * Base: d0000000, Size: 28000000, Tag: 200
1323 12:48:52.982103 * Base: fa000000, Size: 1000000, Tag: 200
1324 12:48:52.985239 * Base: fb001000, Size: 2fff000, Tag: 200
1325 12:48:52.992250 * Base: fe010000, Size: 2e000, Tag: 200
1326 12:48:52.995415 * Base: fe03f000, Size: d41000, Tag: 200
1327 12:48:52.998416 * Base: fed88000, Size: 8000, Tag: 200
1328 12:48:53.001970 * Base: fed93000, Size: d000, Tag: 200
1329 12:48:53.008352 * Base: feda2000, Size: 1e000, Tag: 200
1330 12:48:53.011851 * Base: fede0000, Size: 1220000, Tag: 200
1331 12:48:53.015361 * Base: 280400000, Size: 7d7fc00000, Tag: 100200
1332 12:48:53.021540 PCI: 00:02.0 18 * [0x80000000 - 0x8fffffff] limit: 8fffffff prefmem
1333 12:48:53.028256 PCI: 00:02.0 10 * [0x90000000 - 0x90ffffff] limit: 90ffffff mem
1334 12:48:53.034828 PCI: 00:05.0 10 * [0x91000000 - 0x91ffffff] limit: 91ffffff mem
1335 12:48:53.041278 PCI: 00:1d.0 20 * [0x7fc00000 - 0x7fcfffff] limit: 7fcfffff mem
1336 12:48:53.047867 PCI: 00:1f.3 20 * [0x7fd00000 - 0x7fdfffff] limit: 7fdfffff mem
1337 12:48:53.054636 PCI: 00:04.0 10 * [0x7fe00000 - 0x7fe1ffff] limit: 7fe1ffff mem
1338 12:48:53.061362 PCI: 00:0d.0 10 * [0x7fe20000 - 0x7fe2ffff] limit: 7fe2ffff mem
1339 12:48:53.067914 PCI: 00:14.0 10 * [0x7fe30000 - 0x7fe3ffff] limit: 7fe3ffff mem
1340 12:48:53.074707 PCI: 00:14.2 10 * [0x7fe40000 - 0x7fe43fff] limit: 7fe43fff mem
1341 12:48:53.081299 PCI: 00:14.3 10 * [0x7fe44000 - 0x7fe47fff] limit: 7fe47fff mem
1342 12:48:53.088174 PCI: 00:1f.3 10 * [0x7fe48000 - 0x7fe4bfff] limit: 7fe4bfff mem
1343 12:48:53.094636 PCI: 00:08.0 10 * [0x7fe4c000 - 0x7fe4cfff] limit: 7fe4cfff mem
1344 12:48:53.101100 PCI: 00:14.2 18 * [0x7fe4d000 - 0x7fe4dfff] limit: 7fe4dfff mem
1345 12:48:53.108163 PCI: 00:15.0 10 * [0x7fe4e000 - 0x7fe4efff] limit: 7fe4efff mem
1346 12:48:53.114928 PCI: 00:15.1 10 * [0x7fe4f000 - 0x7fe4ffff] limit: 7fe4ffff mem
1347 12:48:53.121016 PCI: 00:15.2 10 * [0x7fe50000 - 0x7fe50fff] limit: 7fe50fff mem
1348 12:48:53.128149 PCI: 00:15.3 10 * [0x7fe51000 - 0x7fe51fff] limit: 7fe51fff mem
1349 12:48:53.134442 PCI: 00:16.0 10 * [0x7fe52000 - 0x7fe52fff] limit: 7fe52fff mem
1350 12:48:53.140854 PCI: 00:19.1 10 * [0x7fe53000 - 0x7fe53fff] limit: 7fe53fff mem
1351 12:48:53.147652 PCI: 00:1e.2 10 * [0x7fe54000 - 0x7fe54fff] limit: 7fe54fff mem
1352 12:48:53.154153 PCI: 00:1e.3 10 * [0x7fe55000 - 0x7fe55fff] limit: 7fe55fff mem
1353 12:48:53.160463 PCI: 00:1f.5 10 * [0x7fe56000 - 0x7fe56fff] limit: 7fe56fff mem
1354 12:48:53.171148 DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: 7fffffffff done
1355 12:48:53.177391 PCI: 00:1d.0 mem: base: 7fc00000 size: 100000 align: 20 gran: 20 limit: 7fcfffff
1356 12:48:53.181065 PCI: 00:1d.0: Resource ranges:
1357 12:48:53.184055 * Base: 7fc00000, Size: 100000, Tag: 200
1358 12:48:53.190951 PCI: 01:00.0 10 * [0x7fc00000 - 0x7fc03fff] limit: 7fc03fff mem
1359 12:48:53.197446 PCI: 01:00.0 18 * [0x7fc04000 - 0x7fc04fff] limit: 7fc04fff mem
1360 12:48:53.204352 PCI: 01:00.0 1c * [0x7fc05000 - 0x7fc05fff] limit: 7fc05fff mem
1361 12:48:53.214198 PCI: 00:1d.0 mem: base: 7fc00000 size: 100000 align: 20 gran: 20 limit: 7fcfffff done
1362 12:48:53.220409 === Resource allocator: DOMAIN: 0000 - resource allocation complete ===
1363 12:48:53.223938 Root Device assign_resources, bus 0 link: 0
1364 12:48:53.230546 DOMAIN: 0000 assign_resources, bus 0 link: 0
1365 12:48:53.237348 PCI: 00:02.0 10 <- [0x0090000000 - 0x0090ffffff] size 0x01000000 gran 0x18 mem64
1366 12:48:53.247486 PCI: 00:02.0 18 <- [0x0080000000 - 0x008fffffff] size 0x10000000 gran 0x1c prefmem64
1367 12:48:53.253849 PCI: 00:02.0 20 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io
1368 12:48:53.263772 PCI: 00:04.0 10 <- [0x007fe00000 - 0x007fe1ffff] size 0x00020000 gran 0x11 mem64
1369 12:48:53.266870 PCI: 00:04.0 assign_resources, bus 1 link: 0
1370 12:48:53.270688 PCI: 00:04.0 assign_resources, bus 1 link: 0
1371 12:48:53.280582 PCI: 00:05.0 10 <- [0x0091000000 - 0x0091ffffff] size 0x01000000 gran 0x18 mem64
1372 12:48:53.287315 PCI: 00:08.0 10 <- [0x007fe4c000 - 0x007fe4cfff] size 0x00001000 gran 0x0c mem64
1373 12:48:53.297032 PCI: 00:0d.0 10 <- [0x007fe20000 - 0x007fe2ffff] size 0x00010000 gran 0x10 mem64
1374 12:48:53.300762 PCI: 00:0d.0 assign_resources, bus 0 link: 0
1375 12:48:53.307126 PCI: 00:0d.0 assign_resources, bus 0 link: 0
1376 12:48:53.313708 PCI: 00:14.0 10 <- [0x007fe30000 - 0x007fe3ffff] size 0x00010000 gran 0x10 mem64
1377 12:48:53.316756 PCI: 00:14.0 assign_resources, bus 0 link: 0
1378 12:48:53.324053 PCI: 00:14.0 assign_resources, bus 0 link: 0
1379 12:48:53.330734 PCI: 00:14.2 10 <- [0x007fe40000 - 0x007fe43fff] size 0x00004000 gran 0x0e mem64
1380 12:48:53.340647 PCI: 00:14.2 18 <- [0x007fe4d000 - 0x007fe4dfff] size 0x00001000 gran 0x0c mem64
1381 12:48:53.347075 PCI: 00:14.3 10 <- [0x007fe44000 - 0x007fe47fff] size 0x00004000 gran 0x0e mem64
1382 12:48:53.353734 PCI: 00:14.3 assign_resources, bus 0 link: 0
1383 12:48:53.357317 PCI: 00:14.3 assign_resources, bus 0 link: 0
1384 12:48:53.367334 PCI: 00:15.0 10 <- [0x007fe4e000 - 0x007fe4efff] size 0x00001000 gran 0x0c mem64
1385 12:48:53.370485 PCI: 00:15.0 assign_resources, bus 0 link: 0
1386 12:48:53.373537 PCI: 00:15.0 assign_resources, bus 0 link: 0
1387 12:48:53.383725 PCI: 00:15.1 10 <- [0x007fe4f000 - 0x007fe4ffff] size 0x00001000 gran 0x0c mem64
1388 12:48:53.386998 PCI: 00:15.1 assign_resources, bus 0 link: 0
1389 12:48:53.393418 PCI: 00:15.1 assign_resources, bus 0 link: 0
1390 12:48:53.400411 PCI: 00:15.2 10 <- [0x007fe50000 - 0x007fe50fff] size 0x00001000 gran 0x0c mem64
1391 12:48:53.410181 PCI: 00:15.3 10 <- [0x007fe51000 - 0x007fe51fff] size 0x00001000 gran 0x0c mem64
1392 12:48:53.416987 PCI: 00:16.0 10 <- [0x007fe52000 - 0x007fe52fff] size 0x00001000 gran 0x0c mem64
1393 12:48:53.426433 PCI: 00:19.1 10 <- [0x007fe53000 - 0x007fe53fff] size 0x00001000 gran 0x0c mem64
1394 12:48:53.429989 PCI: 00:19.1 assign_resources, bus 0 link: 0
1395 12:48:53.433269 PCI: 00:19.1 assign_resources, bus 0 link: 0
1396 12:48:53.443171 PCI: 00:1d.0 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io
1397 12:48:53.453156 PCI: 00:1d.0 24 <- [0xffffffffffffffff - 0xfffffffffffffffe] size 0x00000000 gran 0x14 bus 01 prefmem
1398 12:48:53.460023 PCI: 00:1d.0 20 <- [0x007fc00000 - 0x007fcfffff] size 0x00100000 gran 0x14 bus 01 mem
1399 12:48:53.466371 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1400 12:48:53.473068 PCI: 01:00.0 10 <- [0x007fc00000 - 0x007fc03fff] size 0x00004000 gran 0x0e mem64
1401 12:48:53.483009 PCI: 01:00.0 18 <- [0x007fc04000 - 0x007fc04fff] size 0x00001000 gran 0x0c mem
1402 12:48:53.489707 PCI: 01:00.0 1c <- [0x007fc05000 - 0x007fc05fff] size 0x00001000 gran 0x0c mem
1403 12:48:53.493059 PCI: 00:1d.0 assign_resources, bus 1 link: 0
1404 12:48:53.503358 PCI: 00:1e.2 10 <- [0x007fe54000 - 0x007fe54fff] size 0x00001000 gran 0x0c mem64
1405 12:48:53.506531 PCI: 00:1e.2 assign_resources, bus 2 link: 0
1406 12:48:53.513529 PCI: 00:1e.2 assign_resources, bus 2 link: 0
1407 12:48:53.519706 PCI: 00:1e.3 10 <- [0x007fe55000 - 0x007fe55fff] size 0x00001000 gran 0x0c mem64
1408 12:48:53.523239 PCI: 00:1e.3 assign_resources, bus 3 link: 0
1409 12:48:53.529688 PCI: 00:1e.3 assign_resources, bus 3 link: 0
1410 12:48:53.533017 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1411 12:48:53.539675 PCI: 00:1f.0 assign_resources, bus 0 link: 0
1412 12:48:53.543012 LPC: Trying to open IO window from 800 size 1ff
1413 12:48:53.553324 PCI: 00:1f.3 10 <- [0x007fe48000 - 0x007fe4bfff] size 0x00004000 gran 0x0e mem64
1414 12:48:53.559913 PCI: 00:1f.3 20 <- [0x007fd00000 - 0x007fdfffff] size 0x00100000 gran 0x14 mem64
1415 12:48:53.569896 PCI: 00:1f.5 10 <- [0x007fe56000 - 0x007fe56fff] size 0x00001000 gran 0x0c mem
1416 12:48:53.573413 DOMAIN: 0000 assign_resources, bus 0 link: 0
1417 12:48:53.576431 Root Device assign_resources, bus 0 link: 0
1418 12:48:53.580001 Done setting resources.
1419 12:48:53.586908 Show resources in subtree (Root Device)...After assigning values.
1420 12:48:53.590029 Root Device child on link 0 DOMAIN: 0000
1421 12:48:53.596283 DOMAIN: 0000 child on link 0 PCI: 00:00.0
1422 12:48:53.606313 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000
1423 12:48:53.613122 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit 7fffffffff flags 40040200 index 10000100
1424 12:48:53.616241 PCI: 00:00.0
1425 12:48:53.626263 PCI: 00:00.0 resource base c0000000 size 10000000 align 0 gran 0 limit 0 flags f0000200 index 0
1426 12:48:53.636212 PCI: 00:00.0 resource base fedc0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 1
1427 12:48:53.645893 PCI: 00:00.0 resource base feda0000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 2
1428 12:48:53.652279 PCI: 00:00.0 resource base feda1000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 3
1429 12:48:53.662403 PCI: 00:00.0 resource base fb000000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 4
1430 12:48:53.672586 PCI: 00:00.0 resource base fed80000 size 4000 align 0 gran 0 limit 0 flags f0000200 index 5
1431 12:48:53.682362 PCI: 00:00.0 resource base fed90000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 6
1432 12:48:53.692709 PCI: 00:00.0 resource base fed92000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 7
1433 12:48:53.702727 PCI: 00:00.0 resource base fed84000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 8
1434 12:48:53.708988 PCI: 00:00.0 resource base fed85000 size 1000 align 0 gran 0 limit 0 flags f0000200 index 9
1435 12:48:53.718971 PCI: 00:00.0 resource base fed86000 size 1000 align 0 gran 0 limit 0 flags f0000200 index a
1436 12:48:53.729003 PCI: 00:00.0 resource base fed87000 size 1000 align 0 gran 0 limit 0 flags f0000200 index b
1437 12:48:53.738891 PCI: 00:00.0 resource base fed91000 size 1000 align 0 gran 0 limit 0 flags f0000200 index c
1438 12:48:53.745582 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index d
1439 12:48:53.755366 PCI: 00:00.0 resource base c0000 size 76f40000 align 0 gran 0 limit 0 flags e0004200 index e
1440 12:48:53.765219 PCI: 00:00.0 resource base 77000000 size 8c00000 align 0 gran 0 limit 0 flags f0000200 index f
1441 12:48:53.775671 PCI: 00:00.0 resource base 100000000 size 180400000 align 0 gran 0 limit 0 flags e0004200 index 10
1442 12:48:53.785344 PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11
1443 12:48:53.795358 PCI: 00:00.0 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12
1444 12:48:53.805232 PCI: 00:00.0 resource base f8000000 size 2000000 align 0 gran 0 limit 0 flags f0000200 index 13
1445 12:48:53.805324 PCI: 00:02.0
1446 12:48:53.815061 PCI: 00:02.0 resource base 90000000 size 1000000 align 24 gran 24 limit 90ffffff flags 60000201 index 10
1447 12:48:53.828763 PCI: 00:02.0 resource base 80000000 size 10000000 align 28 gran 28 limit 8fffffff flags 60001201 index 18
1448 12:48:53.835373 PCI: 00:02.0 resource base 1000 size 40 align 6 gran 6 limit 103f flags 60000100 index 20
1449 12:48:53.841716 PCI: 00:04.0 child on link 0 GENERIC: 0.0
1450 12:48:53.851799 PCI: 00:04.0 resource base 7fe00000 size 20000 align 17 gran 17 limit 7fe1ffff flags 60000201 index 10
1451 12:48:53.851885 GENERIC: 0.0
1452 12:48:53.855385 PCI: 00:05.0
1453 12:48:53.865441 PCI: 00:05.0 resource base 91000000 size 1000000 align 24 gran 24 limit 91ffffff flags 60000201 index 10
1454 12:48:53.868416 PCI: 00:07.0 child on link 0 GENERIC: 0.0
1455 12:48:53.872255 GENERIC: 0.0
1456 12:48:53.872379 PCI: 00:08.0
1457 12:48:53.885084 PCI: 00:08.0 resource base 7fe4c000 size 1000 align 12 gran 12 limit 7fe4cfff flags 60000201 index 10
1458 12:48:53.885180 PCI: 00:0a.0
1459 12:48:53.888483 PCI: 00:0d.0 child on link 0 USB0 port 0
1460 12:48:53.901840 PCI: 00:0d.0 resource base 7fe20000 size 10000 align 16 gran 16 limit 7fe2ffff flags 60000201 index 10
1461 12:48:53.904983 USB0 port 0 child on link 0 USB3 port 0
1462 12:48:53.905075 USB3 port 0
1463 12:48:53.908772 USB3 port 1
1464 12:48:53.908868 USB3 port 2
1465 12:48:53.911904 USB3 port 3
1466 12:48:53.914883 PCI: 00:14.0 child on link 0 USB0 port 0
1467 12:48:53.924993 PCI: 00:14.0 resource base 7fe30000 size 10000 align 16 gran 16 limit 7fe3ffff flags 60000201 index 10
1468 12:48:53.931946 USB0 port 0 child on link 0 USB2 port 0
1469 12:48:53.932035 USB2 port 0
1470 12:48:53.935109 USB2 port 1
1471 12:48:53.935201 USB2 port 2
1472 12:48:53.938381 USB2 port 3
1473 12:48:53.938469 USB2 port 4
1474 12:48:53.941901 USB2 port 5
1475 12:48:53.944983 USB2 port 6
1476 12:48:53.945080 USB2 port 7
1477 12:48:53.948679 USB2 port 8
1478 12:48:53.948758 USB2 port 9
1479 12:48:53.951842 USB3 port 0
1480 12:48:53.951923 USB3 port 1
1481 12:48:53.955031 USB3 port 2
1482 12:48:53.955107 USB3 port 3
1483 12:48:53.958527 PCI: 00:14.2
1484 12:48:53.968252 PCI: 00:14.2 resource base 7fe40000 size 4000 align 14 gran 14 limit 7fe43fff flags 60000201 index 10
1485 12:48:53.978630 PCI: 00:14.2 resource base 7fe4d000 size 1000 align 12 gran 12 limit 7fe4dfff flags 60000201 index 18
1486 12:48:53.981882 PCI: 00:14.3 child on link 0 GENERIC: 0.0
1487 12:48:53.991591 PCI: 00:14.3 resource base 7fe44000 size 4000 align 14 gran 14 limit 7fe47fff flags 60000201 index 10
1488 12:48:53.995044 GENERIC: 0.0
1489 12:48:53.998343 PCI: 00:15.0 child on link 0 I2C: 00:1a
1490 12:48:54.008341 PCI: 00:15.0 resource base 7fe4e000 size 1000 align 12 gran 12 limit 7fe4efff flags 60000201 index 10
1491 12:48:54.011576 I2C: 00:1a
1492 12:48:54.011769 I2C: 00:31
1493 12:48:54.015126 I2C: 00:32
1494 12:48:54.018277 PCI: 00:15.1 child on link 0 I2C: 00:10
1495 12:48:54.028499 PCI: 00:15.1 resource base 7fe4f000 size 1000 align 12 gran 12 limit 7fe4ffff flags 60000201 index 10
1496 12:48:54.031639 I2C: 00:10
1497 12:48:54.032095 PCI: 00:15.2
1498 12:48:54.041617 PCI: 00:15.2 resource base 7fe50000 size 1000 align 12 gran 12 limit 7fe50fff flags 60000201 index 10
1499 12:48:54.045256 PCI: 00:15.3
1500 12:48:54.055197 PCI: 00:15.3 resource base 7fe51000 size 1000 align 12 gran 12 limit 7fe51fff flags 60000201 index 10
1501 12:48:54.055656 PCI: 00:16.0
1502 12:48:54.065385 PCI: 00:16.0 resource base 7fe52000 size 1000 align 12 gran 12 limit 7fe52fff flags 60000201 index 10
1503 12:48:54.068432 PCI: 00:19.0
1504 12:48:54.071489 PCI: 00:19.1 child on link 0 I2C: 00:15
1505 12:48:54.081692 PCI: 00:19.1 resource base 7fe53000 size 1000 align 12 gran 12 limit 7fe53fff flags 60000201 index 10
1506 12:48:54.084845 I2C: 00:15
1507 12:48:54.088167 PCI: 00:1d.0 child on link 0 GENERIC: 0.0
1508 12:48:54.097785 PCI: 00:1d.0 resource base ffff size 0 align 12 gran 12 limit ffff flags 20080102 index 1c
1509 12:48:54.107992 PCI: 00:1d.0 resource base ffffffffffffffff size 0 align 20 gran 20 limit ffffffffffffffff flags 20081202 index 24
1510 12:48:54.121503 PCI: 00:1d.0 resource base 7fc00000 size 100000 align 20 gran 20 limit 7fcfffff flags 60080202 index 20
1511 12:48:54.121622 GENERIC: 0.0
1512 12:48:54.124579 PCI: 01:00.0
1513 12:48:54.134549 PCI: 01:00.0 resource base 7fc00000 size 4000 align 14 gran 14 limit 7fc03fff flags 60000201 index 10
1514 12:48:54.144587 PCI: 01:00.0 resource base 7fc04000 size 1000 align 12 gran 12 limit 7fc04fff flags 60000200 index 18
1515 12:48:54.154522 PCI: 01:00.0 resource base 7fc05000 size 1000 align 12 gran 12 limit 7fc05fff flags 60000200 index 1c
1516 12:48:54.157739 PCI: 00:1e.0
1517 12:48:54.167673 PCI: 00:1e.0 resource base fe03e000 size 1000 align 12 gran 12 limit ffffffffffffffff flags c0000200 index 10
1518 12:48:54.171237 PCI: 00:1e.2 child on link 0 SPI: 00
1519 12:48:54.181246 PCI: 00:1e.2 resource base 7fe54000 size 1000 align 12 gran 12 limit 7fe54fff flags 60000201 index 10
1520 12:48:54.184204 SPI: 00
1521 12:48:54.187923 PCI: 00:1e.3 child on link 0 SPI: 00
1522 12:48:54.197556 PCI: 00:1e.3 resource base 7fe55000 size 1000 align 12 gran 12 limit 7fe55fff flags 60000201 index 10
1523 12:48:54.197647 SPI: 00
1524 12:48:54.204141 PCI: 00:1f.0 child on link 0 PNP: 0c09.0
1525 12:48:54.210778 PCI: 00:1f.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0000100 index 0
1526 12:48:54.214588 PNP: 0c09.0
1527 12:48:54.220851 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0
1528 12:48:54.227402 PCI: 00:1f.2 child on link 0 GENERIC: 0.0
1529 12:48:54.237370 PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran 0 limit 0 flags f0000200 index 0
1530 12:48:54.244229 PCI: 00:1f.2 resource base 1800 size 100 align 0 gran 0 limit 18ff flags c0000100 index 1
1531 12:48:54.250540 GENERIC: 0.0 child on link 0 GENERIC: 0.0
1532 12:48:54.250630 GENERIC: 0.0
1533 12:48:54.254269 GENERIC: 1.0
1534 12:48:54.254361 PCI: 00:1f.3
1535 12:48:54.267327 PCI: 00:1f.3 resource base 7fe48000 size 4000 align 14 gran 14 limit 7fe4bfff flags 60000201 index 10
1536 12:48:54.277410 PCI: 00:1f.3 resource base 7fd00000 size 100000 align 20 gran 20 limit 7fdfffff flags 60000201 index 20
1537 12:48:54.277509 PCI: 00:1f.5
1538 12:48:54.287476 PCI: 00:1f.5 resource base 7fe56000 size 1000 align 12 gran 12 limit 7fe56fff flags 60000200 index 10
1539 12:48:54.293708 CPU_CLUSTER: 0 child on link 0 APIC: 00
1540 12:48:54.293797 APIC: 00
1541 12:48:54.293876 APIC: 01
1542 12:48:54.297318 APIC: 03
1543 12:48:54.297399 APIC: 06
1544 12:48:54.300763 APIC: 05
1545 12:48:54.300842 APIC: 04
1546 12:48:54.300909 APIC: 02
1547 12:48:54.303829 APIC: 07
1548 12:48:54.303918 Done allocating resources.
1549 12:48:54.310621 BS: BS_DEV_RESOURCES run times (exec / console): 28 / 2514 ms
1550 12:48:54.316902 fw_config match found: AUDIO=MAX98373_ALC5682I_I2S_UP4
1551 12:48:54.320291 Configure GPIOs for I2S audio on UP4.
1552 12:48:54.328147 BS: BS_DEV_ENABLE entry times (exec / console): 2 / 9 ms
1553 12:48:54.331651 Enabling resources...
1554 12:48:54.334784 PCI: 00:00.0 subsystem <- 8086/9a12
1555 12:48:54.338025 PCI: 00:00.0 cmd <- 06
1556 12:48:54.341256 PCI: 00:02.0 subsystem <- 8086/9a40
1557 12:48:54.345118 PCI: 00:02.0 cmd <- 03
1558 12:48:54.348254 PCI: 00:04.0 subsystem <- 8086/9a03
1559 12:48:54.348375 PCI: 00:04.0 cmd <- 02
1560 12:48:54.355009 PCI: 00:05.0 subsystem <- 8086/9a19
1561 12:48:54.355130 PCI: 00:05.0 cmd <- 02
1562 12:48:54.358553 PCI: 00:08.0 subsystem <- 8086/9a11
1563 12:48:54.361757 PCI: 00:08.0 cmd <- 06
1564 12:48:54.365063 PCI: 00:0d.0 subsystem <- 8086/9a13
1565 12:48:54.368227 PCI: 00:0d.0 cmd <- 02
1566 12:48:54.371439 PCI: 00:14.0 subsystem <- 8086/a0ed
1567 12:48:54.374731 PCI: 00:14.0 cmd <- 02
1568 12:48:54.378483 PCI: 00:14.2 subsystem <- 8086/a0ef
1569 12:48:54.381642 PCI: 00:14.2 cmd <- 02
1570 12:48:54.384727 PCI: 00:14.3 subsystem <- 8086/a0f0
1571 12:48:54.388014 PCI: 00:14.3 cmd <- 02
1572 12:48:54.391668 PCI: 00:15.0 subsystem <- 8086/a0e8
1573 12:48:54.394971 PCI: 00:15.0 cmd <- 02
1574 12:48:54.398142 PCI: 00:15.1 subsystem <- 8086/a0e9
1575 12:48:54.398601 PCI: 00:15.1 cmd <- 02
1576 12:48:54.404679 PCI: 00:15.2 subsystem <- 8086/a0ea
1577 12:48:54.405139 PCI: 00:15.2 cmd <- 02
1578 12:48:54.408189 PCI: 00:15.3 subsystem <- 8086/a0eb
1579 12:48:54.411399 PCI: 00:15.3 cmd <- 02
1580 12:48:54.414874 PCI: 00:16.0 subsystem <- 8086/a0e0
1581 12:48:54.418320 PCI: 00:16.0 cmd <- 02
1582 12:48:54.421751 PCI: 00:19.1 subsystem <- 8086/a0c6
1583 12:48:54.424732 PCI: 00:19.1 cmd <- 02
1584 12:48:54.428081 PCI: 00:1d.0 bridge ctrl <- 0013
1585 12:48:54.431617 PCI: 00:1d.0 subsystem <- 8086/a0b0
1586 12:48:54.434707 PCI: 00:1d.0 cmd <- 06
1587 12:48:54.438226 PCI: 00:1e.0 subsystem <- 8086/a0a8
1588 12:48:54.441432 PCI: 00:1e.0 cmd <- 06
1589 12:48:54.444816 PCI: 00:1e.2 subsystem <- 8086/a0aa
1590 12:48:54.447857 PCI: 00:1e.2 cmd <- 06
1591 12:48:54.451336 PCI: 00:1e.3 subsystem <- 8086/a0ab
1592 12:48:54.451795 PCI: 00:1e.3 cmd <- 02
1593 12:48:54.457834 PCI: 00:1f.0 subsystem <- 8086/a087
1594 12:48:54.458317 PCI: 00:1f.0 cmd <- 407
1595 12:48:54.461552 PCI: 00:1f.3 subsystem <- 8086/a0c8
1596 12:48:54.464570 PCI: 00:1f.3 cmd <- 02
1597 12:48:54.467781 PCI: 00:1f.5 subsystem <- 8086/a0a4
1598 12:48:54.470888 PCI: 00:1f.5 cmd <- 406
1599 12:48:54.475593 PCI: 01:00.0 cmd <- 02
1600 12:48:54.480401 done.
1601 12:48:54.483535 BS: BS_DEV_ENABLE run times (exec / console): 10 / 140 ms
1602 12:48:54.486784 Initializing devices...
1603 12:48:54.490039 Root Device init
1604 12:48:54.493739 Chrome EC: Set SMI mask to 0x0000000000000000
1605 12:48:54.500064 Chrome EC: clear events_b mask to 0x0000000000000000
1606 12:48:54.506645 Chrome EC: Set S5 LAZY WAKE mask to 0x0000000000000006
1607 12:48:54.510098 Chrome EC: Set S3 LAZY WAKE mask to 0x000000001800101e
1608 12:48:54.517324 Chrome EC: Set S0iX LAZY WAKE mask to 0x000000001800101e
1609 12:48:54.524046 Chrome EC: Set WAKE mask to 0x0000000000000000
1610 12:48:54.527364 fw_config match found: DB_USB=USB3_ACTIVE
1611 12:48:54.533664 Configure Right Type-C port orientation for retimer
1612 12:48:54.537109 Root Device init finished in 44 msecs
1613 12:48:54.539855 PCI: 00:00.0 init
1614 12:48:54.543321 CPU TDP = 9 Watts
1615 12:48:54.546462 CPU PL1 = 9 Watts
1616 12:48:54.546550 CPU PL2 = 40 Watts
1617 12:48:54.550158 CPU PL4 = 83 Watts
1618 12:48:54.553199 PCI: 00:00.0 init finished in 8 msecs
1619 12:48:54.553288 PCI: 00:02.0 init
1620 12:48:54.556443 GMA: Found VBT in CBFS
1621 12:48:54.559682 GMA: Found valid VBT in CBFS
1622 12:48:54.566719 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
1623 12:48:54.573413 x_res x y_res: 1920 x 1080, size: 8294400 at 0x80000000
1624 12:48:54.576112 PCI: 00:02.0 init finished in 18 msecs
1625 12:48:54.579661 PCI: 00:05.0 init
1626 12:48:54.582815 PCI: 00:05.0 init finished in 0 msecs
1627 12:48:54.586490 PCI: 00:08.0 init
1628 12:48:54.589710 PCI: 00:08.0 init finished in 0 msecs
1629 12:48:54.593061 PCI: 00:14.0 init
1630 12:48:54.596117 PCI: 00:14.0 init finished in 0 msecs
1631 12:48:54.599269 PCI: 00:14.2 init
1632 12:48:54.603105 PCI: 00:14.2 init finished in 0 msecs
1633 12:48:54.605920 PCI: 00:15.0 init
1634 12:48:54.609099 I2C bus 0 version 0x3230302a
1635 12:48:54.612795 DW I2C bus 0 at 0x7fe4e000 (400 KHz)
1636 12:48:54.616124 PCI: 00:15.0 init finished in 6 msecs
1637 12:48:54.616205 PCI: 00:15.1 init
1638 12:48:54.619302 I2C bus 1 version 0x3230302a
1639 12:48:54.622852 DW I2C bus 1 at 0x7fe4f000 (400 KHz)
1640 12:48:54.629385 PCI: 00:15.1 init finished in 6 msecs
1641 12:48:54.629472 PCI: 00:15.2 init
1642 12:48:54.632654 I2C bus 2 version 0x3230302a
1643 12:48:54.636045 DW I2C bus 2 at 0x7fe50000 (400 KHz)
1644 12:48:54.639155 PCI: 00:15.2 init finished in 6 msecs
1645 12:48:54.642572 PCI: 00:15.3 init
1646 12:48:54.645789 I2C bus 3 version 0x3230302a
1647 12:48:54.649442 DW I2C bus 3 at 0x7fe51000 (400 KHz)
1648 12:48:54.652512 PCI: 00:15.3 init finished in 6 msecs
1649 12:48:54.655882 PCI: 00:16.0 init
1650 12:48:54.659641 PCI: 00:16.0 init finished in 0 msecs
1651 12:48:54.662499 PCI: 00:19.1 init
1652 12:48:54.665560 I2C bus 5 version 0x3230302a
1653 12:48:54.669215 DW I2C bus 5 at 0x7fe53000 (400 KHz)
1654 12:48:54.672459 PCI: 00:19.1 init finished in 6 msecs
1655 12:48:54.675646 PCI: 00:1d.0 init
1656 12:48:54.678761 Initializing PCH PCIe bridge.
1657 12:48:54.682393 PCI: 00:1d.0 init finished in 3 msecs
1658 12:48:54.685501 PCI: 00:1f.0 init
1659 12:48:54.689221 IOAPIC: Initializing IOAPIC at 0xfec00000
1660 12:48:54.692257 IOAPIC: Bootstrap Processor Local APIC = 0x00
1661 12:48:54.695394 IOAPIC: ID = 0x02
1662 12:48:54.699288 IOAPIC: Dumping registers
1663 12:48:54.699377 reg 0x0000: 0x02000000
1664 12:48:54.702474 reg 0x0001: 0x00770020
1665 12:48:54.705641 reg 0x0002: 0x00000000
1666 12:48:54.708700 PCI: 00:1f.0 init finished in 21 msecs
1667 12:48:54.712212 PCI: 00:1f.2 init
1668 12:48:54.716007 Disabling ACPI via APMC.
1669 12:48:54.716095 APMC done.
1670 12:48:54.719143 PCI: 00:1f.2 init finished in 5 msecs
1671 12:48:54.732822 PCI: 01:00.0 init
1672 12:48:54.735998 PCI: 01:00.0 init finished in 0 msecs
1673 12:48:54.739222 PNP: 0c09.0 init
1674 12:48:54.742752 Google Chrome EC uptime: 8.438 seconds
1675 12:48:54.749116 Google Chrome AP resets since EC boot: 1
1676 12:48:54.752230 Google Chrome most recent AP reset causes:
1677 12:48:54.755660 0.349: 32775 shutdown: entering G3
1678 12:48:54.762541 Google Chrome EC reset flags at last EC boot: reset-pin | sysjump
1679 12:48:54.765653 PNP: 0c09.0 init finished in 22 msecs
1680 12:48:54.771926 Devices initialized
1681 12:48:54.775269 Show all devs... After init.
1682 12:48:54.778294 Root Device: enabled 1
1683 12:48:54.778837 DOMAIN: 0000: enabled 1
1684 12:48:54.781925 CPU_CLUSTER: 0: enabled 1
1685 12:48:54.785172 PCI: 00:00.0: enabled 1
1686 12:48:54.788374 PCI: 00:02.0: enabled 1
1687 12:48:54.788881 PCI: 00:04.0: enabled 1
1688 12:48:54.791578 PCI: 00:05.0: enabled 1
1689 12:48:54.794870 PCI: 00:06.0: enabled 0
1690 12:48:54.798386 PCI: 00:07.0: enabled 0
1691 12:48:54.798475 PCI: 00:07.1: enabled 0
1692 12:48:54.801441 PCI: 00:07.2: enabled 0
1693 12:48:54.804707 PCI: 00:07.3: enabled 0
1694 12:48:54.807967 PCI: 00:08.0: enabled 1
1695 12:48:54.808056 PCI: 00:09.0: enabled 0
1696 12:48:54.811624 PCI: 00:0a.0: enabled 0
1697 12:48:54.814619 PCI: 00:0d.0: enabled 1
1698 12:48:54.818151 PCI: 00:0d.1: enabled 0
1699 12:48:54.818240 PCI: 00:0d.2: enabled 0
1700 12:48:54.821223 PCI: 00:0d.3: enabled 0
1701 12:48:54.824528 PCI: 00:0e.0: enabled 0
1702 12:48:54.824617 PCI: 00:10.2: enabled 1
1703 12:48:54.827921 PCI: 00:10.6: enabled 0
1704 12:48:54.831330 PCI: 00:10.7: enabled 0
1705 12:48:54.834511 PCI: 00:12.0: enabled 0
1706 12:48:54.834599 PCI: 00:12.6: enabled 0
1707 12:48:54.838124 PCI: 00:13.0: enabled 0
1708 12:48:54.841143 PCI: 00:14.0: enabled 1
1709 12:48:54.844318 PCI: 00:14.1: enabled 0
1710 12:48:54.844421 PCI: 00:14.2: enabled 1
1711 12:48:54.847760 PCI: 00:14.3: enabled 1
1712 12:48:54.850888 PCI: 00:15.0: enabled 1
1713 12:48:54.854420 PCI: 00:15.1: enabled 1
1714 12:48:54.854509 PCI: 00:15.2: enabled 1
1715 12:48:54.857785 PCI: 00:15.3: enabled 1
1716 12:48:54.860997 PCI: 00:16.0: enabled 1
1717 12:48:54.861086 PCI: 00:16.1: enabled 0
1718 12:48:54.864592 PCI: 00:16.2: enabled 0
1719 12:48:54.867703 PCI: 00:16.3: enabled 0
1720 12:48:54.870884 PCI: 00:16.4: enabled 0
1721 12:48:54.870973 PCI: 00:16.5: enabled 0
1722 12:48:54.874580 PCI: 00:17.0: enabled 0
1723 12:48:54.877731 PCI: 00:19.0: enabled 0
1724 12:48:54.881008 PCI: 00:19.1: enabled 1
1725 12:48:54.881099 PCI: 00:19.2: enabled 0
1726 12:48:54.884065 PCI: 00:1c.0: enabled 1
1727 12:48:54.887725 PCI: 00:1c.1: enabled 0
1728 12:48:54.891011 PCI: 00:1c.2: enabled 0
1729 12:48:54.891092 PCI: 00:1c.3: enabled 0
1730 12:48:54.894143 PCI: 00:1c.4: enabled 0
1731 12:48:54.897382 PCI: 00:1c.5: enabled 0
1732 12:48:54.901159 PCI: 00:1c.6: enabled 1
1733 12:48:54.901251 PCI: 00:1c.7: enabled 0
1734 12:48:54.904212 PCI: 00:1d.0: enabled 1
1735 12:48:54.907482 PCI: 00:1d.1: enabled 0
1736 12:48:54.907561 PCI: 00:1d.2: enabled 1
1737 12:48:54.911088 PCI: 00:1d.3: enabled 0
1738 12:48:54.914297 PCI: 00:1e.0: enabled 1
1739 12:48:54.917319 PCI: 00:1e.1: enabled 0
1740 12:48:54.917417 PCI: 00:1e.2: enabled 1
1741 12:48:54.920914 PCI: 00:1e.3: enabled 1
1742 12:48:54.924523 PCI: 00:1f.0: enabled 1
1743 12:48:54.927723 PCI: 00:1f.1: enabled 0
1744 12:48:54.927808 PCI: 00:1f.2: enabled 1
1745 12:48:54.930917 PCI: 00:1f.3: enabled 1
1746 12:48:54.933951 PCI: 00:1f.4: enabled 0
1747 12:48:54.937359 PCI: 00:1f.5: enabled 1
1748 12:48:54.937455 PCI: 00:1f.6: enabled 0
1749 12:48:54.941003 PCI: 00:1f.7: enabled 0
1750 12:48:54.944055 APIC: 00: enabled 1
1751 12:48:54.944160 GENERIC: 0.0: enabled 1
1752 12:48:54.947806 GENERIC: 0.0: enabled 1
1753 12:48:54.950780 GENERIC: 1.0: enabled 1
1754 12:48:54.954099 GENERIC: 0.0: enabled 1
1755 12:48:54.954188 GENERIC: 1.0: enabled 1
1756 12:48:54.957461 USB0 port 0: enabled 1
1757 12:48:54.961043 GENERIC: 0.0: enabled 1
1758 12:48:54.961149 USB0 port 0: enabled 1
1759 12:48:54.964225 GENERIC: 0.0: enabled 1
1760 12:48:54.967250 I2C: 00:1a: enabled 1
1761 12:48:54.970484 I2C: 00:31: enabled 1
1762 12:48:54.970588 I2C: 00:32: enabled 1
1763 12:48:54.973748 I2C: 00:10: enabled 1
1764 12:48:54.977363 I2C: 00:15: enabled 1
1765 12:48:54.977467 GENERIC: 0.0: enabled 0
1766 12:48:54.980472 GENERIC: 1.0: enabled 0
1767 12:48:54.984040 GENERIC: 0.0: enabled 1
1768 12:48:54.984127 SPI: 00: enabled 1
1769 12:48:54.987349 SPI: 00: enabled 1
1770 12:48:54.990488 PNP: 0c09.0: enabled 1
1771 12:48:54.990576 GENERIC: 0.0: enabled 1
1772 12:48:54.994014 USB3 port 0: enabled 1
1773 12:48:54.997175 USB3 port 1: enabled 1
1774 12:48:54.997263 USB3 port 2: enabled 0
1775 12:48:55.000299 USB3 port 3: enabled 0
1776 12:48:55.004051 USB2 port 0: enabled 0
1777 12:48:55.007329 USB2 port 1: enabled 1
1778 12:48:55.007417 USB2 port 2: enabled 1
1779 12:48:55.010419 USB2 port 3: enabled 0
1780 12:48:55.013494 USB2 port 4: enabled 1
1781 12:48:55.013582 USB2 port 5: enabled 0
1782 12:48:55.017384 USB2 port 6: enabled 0
1783 12:48:55.020377 USB2 port 7: enabled 0
1784 12:48:55.023750 USB2 port 8: enabled 0
1785 12:48:55.023844 USB2 port 9: enabled 0
1786 12:48:55.026953 USB3 port 0: enabled 0
1787 12:48:55.030755 USB3 port 1: enabled 1
1788 12:48:55.030856 USB3 port 2: enabled 0
1789 12:48:55.033907 USB3 port 3: enabled 0
1790 12:48:55.036843 GENERIC: 0.0: enabled 1
1791 12:48:55.040373 GENERIC: 1.0: enabled 1
1792 12:48:55.040492 APIC: 01: enabled 1
1793 12:48:55.043913 APIC: 03: enabled 1
1794 12:48:55.044045 APIC: 06: enabled 1
1795 12:48:55.047078 APIC: 05: enabled 1
1796 12:48:55.050445 APIC: 04: enabled 1
1797 12:48:55.050591 APIC: 02: enabled 1
1798 12:48:55.053746 APIC: 07: enabled 1
1799 12:48:55.056801 PCI: 01:00.0: enabled 1
1800 12:48:55.060053 BS: BS_DEV_INIT run times (exec / console): 31 / 540 ms
1801 12:48:55.066761 FMAP: area RW_ELOG found @ f30000 (4096 bytes)
1802 12:48:55.070306 ELOG: NV offset 0xf30000 size 0x1000
1803 12:48:55.076860 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
1804 12:48:55.083619 ELOG: Event(17) added with size 13 at 2023-03-13 12:48:55 UTC
1805 12:48:55.090065 ELOG: Event(92) added with size 9 at 2023-03-13 12:48:55 UTC
1806 12:48:55.096467 ELOG: Event(93) added with size 9 at 2023-03-13 12:48:55 UTC
1807 12:48:55.103459 ELOG: Event(9E) added with size 10 at 2023-03-13 12:48:55 UTC
1808 12:48:55.110150 ELOG: Event(9F) added with size 14 at 2023-03-13 12:48:55 UTC
1809 12:48:55.116597 BS: BS_DEV_INIT exit times (exec / console): 3 / 45 ms
1810 12:48:55.119819 ELOG: Event(A1) added with size 10 at 2023-03-13 12:48:55 UTC
1811 12:48:55.129540 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
1812 12:48:55.136422 ELOG: Event(A0) added with size 9 at 2023-03-13 12:48:55 UTC
1813 12:48:55.139825 elog_add_boot_reason: Logged dev mode boot
1814 12:48:55.146203 BS: BS_POST_DEVICE entry times (exec / console): 0 / 24 ms
1815 12:48:55.146289 Finalize devices...
1816 12:48:55.149582 Devices finalized
1817 12:48:55.156129 BS: BS_POST_DEVICE run times (exec / console): 0 / 4 ms
1818 12:48:55.159570 FMAP: area RW_NVRAM found @ f37000 (24576 bytes)
1819 12:48:55.166556 BS: BS_POST_DEVICE exit times (exec / console): 0 / 5 ms
1820 12:48:55.169343 ME: HFSTS1 : 0x80030055
1821 12:48:55.176212 ME: HFSTS2 : 0x30280116
1822 12:48:55.179237 ME: HFSTS3 : 0x00000050
1823 12:48:55.182801 ME: HFSTS4 : 0x00004000
1824 12:48:55.189687 ME: HFSTS5 : 0x00000000
1825 12:48:55.192816 ME: HFSTS6 : 0x00400006
1826 12:48:55.196359 ME: Manufacturing Mode : YES
1827 12:48:55.199528 ME: SPI Protection Mode Enabled : NO
1828 12:48:55.202825 ME: FW Partition Table : OK
1829 12:48:55.209713 ME: Bringup Loader Failure : NO
1830 12:48:55.212832 ME: Firmware Init Complete : NO
1831 12:48:55.215862 ME: Boot Options Present : NO
1832 12:48:55.219715 ME: Update In Progress : NO
1833 12:48:55.222888 ME: D0i3 Support : YES
1834 12:48:55.225990 ME: Low Power State Enabled : NO
1835 12:48:55.229520 ME: CPU Replaced : YES
1836 12:48:55.232675 ME: CPU Replacement Valid : YES
1837 12:48:55.239518 ME: Current Working State : 5
1838 12:48:55.242622 ME: Current Operation State : 1
1839 12:48:55.245844 ME: Current Operation Mode : 3
1840 12:48:55.249490 ME: Error Code : 0
1841 12:48:55.252517 ME: Enhanced Debug Mode : NO
1842 12:48:55.255671 ME: CPU Debug Disabled : YES
1843 12:48:55.259308 ME: TXT Support : NO
1844 12:48:55.265871 BS: BS_OS_RESUME_CHECK exit times (exec / console): 0 / 94 ms
1845 12:48:55.272565 CBFS: Found 'fallback/dsdt.aml' @0x72f80 size 0x5a67 in mcache @0x76c4c1c4
1846 12:48:55.275950 CBFS: 'fallback/slic' not found.
1847 12:48:55.279021 ACPI: Writing ACPI tables at 76b01000.
1848 12:48:55.282572 ACPI: * FACS
1849 12:48:55.282649 ACPI: * DSDT
1850 12:48:55.288921 Ramoops buffer: 0x100000@0x76a00000.
1851 12:48:55.292470 FMAP: area RO_VPD found @ 1800000 (16384 bytes)
1852 12:48:55.295658 FMAP: area RW_VPD found @ f35000 (8192 bytes)
1853 12:48:55.300335 Google Chrome EC: version:
1854 12:48:55.303771 ro: voema_v2.0.7540-147f8d37d1
1855 12:48:55.306773 rw: voema_v2.0.7540-147f8d37d1
1856 12:48:55.309949 running image: 2
1857 12:48:55.316452 PCI space above 4GB MMIO is at 0x280400000, len = 0x7d7fc00000
1858 12:48:55.319755 ACPI: * FADT
1859 12:48:55.319833 SCI is IRQ9
1860 12:48:55.323020 ACPI: added table 1/32, length now 40
1861 12:48:55.326672 ACPI: * SSDT
1862 12:48:55.330254 Found 1 CPU(s) with 8 core(s) each.
1863 12:48:55.333613 \_SB.PCI0.PMC: Intel Tigerlake at PCI: 00:1f.2
1864 12:48:55.340268 \_SB.DPTF: Intel DPTF at GENERIC: 0.0
1865 12:48:55.343505 \_SB.PCI0.CNVW: WIFI Device GENERIC: 0.0
1866 12:48:55.346647 \_SB.PCI0.I2C0.RT58: Headset Codec at I2C: 00:1a
1867 12:48:55.353339 \_SB.PCI0.I2C0.MAXR: Maxim MAX98373 Codec address 031h
1868 12:48:55.360192 \_SB.PCI0.I2C0.MAXL: Maxim MAX98373 Codec address 032h
1869 12:48:55.363539 \_SB.PCI0.I2C1.H010: ELAN Touchscreen at I2C: 00:10
1870 12:48:55.369873 \_SB.PCI0.I2C5.D015: ELAN Touchpad at I2C: 00:15
1871 12:48:55.376548 \_SB.PCI0.RP09: Enable RTD3 for PCI: 00:1d.0 (Intel PCIe Runtime D3)
1872 12:48:55.379781 \_SB.PCI0.RP09: Added StorageD3Enable property
1873 12:48:55.383193 \_SB.PCI0.SPI0.S001: SPI Device at SPI: 00
1874 12:48:55.389632 \_SB.PCI0.SPI1.CRFP: SPI Device at SPI: 00
1875 12:48:55.392931 PS2K: Physmap: [ EA E7 91 92 93 94 95 A0 AE B0 ]
1876 12:48:55.399790 PS2K: Passing 80 keymaps to kernel
1877 12:48:55.406634 \_SB.PCI0.TXHC.RHUB.SS01: USB3 Type-C Port C0 (MLB) at USB3 port 0
1878 12:48:55.409803 \_SB.PCI0.TXHC.RHUB.SS02: USB3 Type-C Port C1 (DB) at USB3 port 1
1879 12:48:55.416707 \_SB.PCI0.XHCI.RHUB.HS02: USB2 Type-A Port A1 (DB) at USB2 port 1
1880 12:48:55.422857 \_SB.PCI0.XHCI.RHUB.HS03: USB2 Type-C Port C1 (DB) at USB2 port 2
1881 12:48:55.429760 \_SB.PCI0.XHCI.RHUB.HS05: USB2 Type-C Port C0 (MLB) at USB2 port 4
1882 12:48:55.436021 \_SB.PCI0.XHCI.RHUB.SS02: USB3 Type-A Port A1 (DB) at USB3 port 1
1883 12:48:55.443180 \_SB.PCI0.PMC.MUX.CON0: Intel PMC MUX CONN Driver at GENERIC: 0.0
1884 12:48:55.449452 \_SB.PCI0.PMC.MUX.CON1: Intel PMC MUX CONN Driver at GENERIC: 1.0
1885 12:48:55.452854 ACPI: added table 2/32, length now 44
1886 12:48:55.456280 ACPI: * MCFG
1887 12:48:55.459420 ACPI: added table 3/32, length now 48
1888 12:48:55.463246 ACPI: * TPM2
1889 12:48:55.466328 TPM2 log created at 0x769f0000
1890 12:48:55.469935 ACPI: added table 4/32, length now 52
1891 12:48:55.470018 ACPI: * MADT
1892 12:48:55.472796 SCI is IRQ9
1893 12:48:55.476258 ACPI: added table 5/32, length now 56
1894 12:48:55.476368 current = 76b09850
1895 12:48:55.479441 ACPI: * DMAR
1896 12:48:55.482713 ACPI: added table 6/32, length now 60
1897 12:48:55.486353 ACPI: added table 7/32, length now 64
1898 12:48:55.489417 ACPI: * HPET
1899 12:48:55.492796 ACPI: added table 8/32, length now 68
1900 12:48:55.492954 ACPI: done.
1901 12:48:55.496137 ACPI tables: 35216 bytes.
1902 12:48:55.499449 smbios_write_tables: 769ef000
1903 12:48:55.503060 EC returned error result code 3
1904 12:48:55.505996 Couldn't obtain OEM name from CBI
1905 12:48:55.509214 Create SMBIOS type 16
1906 12:48:55.513125 Create SMBIOS type 17
1907 12:48:55.513232 GENERIC: 0.0 (WIFI Device)
1908 12:48:55.516153 SMBIOS tables: 1750 bytes.
1909 12:48:55.519238 Writing table forward entry at 0x00000500
1910 12:48:55.525936 Wrote coreboot table at: 0x00000500, 0x10 bytes, checksum 392c
1911 12:48:55.529254 Writing coreboot table at 0x76b25000
1912 12:48:55.536192 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1913 12:48:55.542368 1. 0000000000001000-000000000009ffff: RAM
1914 12:48:55.545634 2. 00000000000a0000-00000000000fffff: RESERVED
1915 12:48:55.549058 3. 0000000000100000-00000000769eefff: RAM
1916 12:48:55.555957 4. 00000000769ef000-0000000076b97fff: CONFIGURATION TABLES
1917 12:48:55.562401 5. 0000000076b98000-0000000076c09fff: RAMSTAGE
1918 12:48:55.565990 6. 0000000076c0a000-0000000076ffffff: CONFIGURATION TABLES
1919 12:48:55.572276 7. 0000000077000000-000000007fbfffff: RESERVED
1920 12:48:55.575456 8. 00000000c0000000-00000000cfffffff: RESERVED
1921 12:48:55.582380 9. 00000000f8000000-00000000f9ffffff: RESERVED
1922 12:48:55.585507 10. 00000000fb000000-00000000fb000fff: RESERVED
1923 12:48:55.591947 11. 00000000fe000000-00000000fe00ffff: RESERVED
1924 12:48:55.595320 12. 00000000fed80000-00000000fed87fff: RESERVED
1925 12:48:55.598699 13. 00000000fed90000-00000000fed92fff: RESERVED
1926 12:48:55.605662 14. 00000000feda0000-00000000feda1fff: RESERVED
1927 12:48:55.608721 15. 00000000fedc0000-00000000feddffff: RESERVED
1928 12:48:55.615684 16. 0000000100000000-00000002803fffff: RAM
1929 12:48:55.615772 Passing 4 GPIOs to payload:
1930 12:48:55.622015 NAME | PORT | POLARITY | VALUE
1931 12:48:55.628645 lid | undefined | high | high
1932 12:48:55.632277 power | undefined | high | low
1933 12:48:55.638608 oprom | undefined | high | low
1934 12:48:55.642290 EC in RW | 0x000000e5 | high | high
1935 12:48:55.648684 Wrote coreboot table at: 0x76b25000, 0x610 bytes, checksum 1796
1936 12:48:55.652502 coreboot table: 1576 bytes.
1937 12:48:55.655650 IMD ROOT 0. 0x76fff000 0x00001000
1938 12:48:55.658847 IMD SMALL 1. 0x76ffe000 0x00001000
1939 12:48:55.662813 FSP MEMORY 2. 0x76c4e000 0x003b0000
1940 12:48:55.669121 VPD 3. 0x76c4d000 0x00000367
1941 12:48:55.672462 RO MCACHE 4. 0x76c4c000 0x00000fdc
1942 12:48:55.675984 CONSOLE 5. 0x76c2c000 0x00020000
1943 12:48:55.678990 FMAP 6. 0x76c2b000 0x00000578
1944 12:48:55.682746 TIME STAMP 7. 0x76c2a000 0x00000910
1945 12:48:55.686124 VBOOT WORK 8. 0x76c16000 0x00014000
1946 12:48:55.689064 ROMSTG STCK 9. 0x76c15000 0x00001000
1947 12:48:55.692420 AFTER CAR 10. 0x76c0a000 0x0000b000
1948 12:48:55.699442 RAMSTAGE 11. 0x76b97000 0x00073000
1949 12:48:55.702345 REFCODE 12. 0x76b42000 0x00055000
1950 12:48:55.705776 SMM BACKUP 13. 0x76b32000 0x00010000
1951 12:48:55.709254 4f444749 14. 0x76b30000 0x00002000
1952 12:48:55.712750 EXT VBT15. 0x76b2d000 0x0000219f
1953 12:48:55.715838 COREBOOT 16. 0x76b25000 0x00008000
1954 12:48:55.719009 ACPI 17. 0x76b01000 0x00024000
1955 12:48:55.722311 ACPI GNVS 18. 0x76b00000 0x00001000
1956 12:48:55.725979 RAMOOPS 19. 0x76a00000 0x00100000
1957 12:48:55.729388 TPM2 TCGLOG20. 0x769f0000 0x00010000
1958 12:48:55.735989 SMBIOS 21. 0x769ef000 0x00000800
1959 12:48:55.736479 IMD small region:
1960 12:48:55.738986 IMD ROOT 0. 0x76ffec00 0x00000400
1961 12:48:55.742266 FSP RUNTIME 1. 0x76ffebe0 0x00000004
1962 12:48:55.749167 POWER STATE 2. 0x76ffeb80 0x00000044
1963 12:48:55.752840 ROMSTAGE 3. 0x76ffeb60 0x00000004
1964 12:48:55.755832 MEM INFO 4. 0x76ffe980 0x000001e0
1965 12:48:55.762026 BS: BS_WRITE_TABLES run times (exec / console): 6 / 484 ms
1966 12:48:55.765785 MTRR: Physical address space:
1967 12:48:55.772574 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6
1968 12:48:55.775651 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0
1969 12:48:55.782220 0x00000000000c0000 - 0x0000000077000000 size 0x76f40000 type 6
1970 12:48:55.789204 0x0000000077000000 - 0x0000000080000000 size 0x09000000 type 0
1971 12:48:55.795650 0x0000000080000000 - 0x0000000090000000 size 0x10000000 type 1
1972 12:48:55.801905 0x0000000090000000 - 0x0000000100000000 size 0x70000000 type 0
1973 12:48:55.808656 0x0000000100000000 - 0x0000000280400000 size 0x180400000 type 6
1974 12:48:55.812100 MTRR: Fixed MSR 0x250 0x0606060606060606
1975 12:48:55.815230 MTRR: Fixed MSR 0x258 0x0606060606060606
1976 12:48:55.822080 MTRR: Fixed MSR 0x259 0x0000000000000000
1977 12:48:55.825448 MTRR: Fixed MSR 0x268 0x0606060606060606
1978 12:48:55.828393 MTRR: Fixed MSR 0x269 0x0606060606060606
1979 12:48:55.832324 MTRR: Fixed MSR 0x26a 0x0606060606060606
1980 12:48:55.835509 MTRR: Fixed MSR 0x26b 0x0606060606060606
1981 12:48:55.842025 MTRR: Fixed MSR 0x26c 0x0606060606060606
1982 12:48:55.845546 MTRR: Fixed MSR 0x26d 0x0606060606060606
1983 12:48:55.848764 MTRR: Fixed MSR 0x26e 0x0606060606060606
1984 12:48:55.851781 MTRR: Fixed MSR 0x26f 0x0606060606060606
1985 12:48:55.856425 call enable_fixed_mtrr()
1986 12:48:55.859576 CPU physical address size: 39 bits
1987 12:48:55.866180 MTRR: default type WB/UC MTRR counts: 6/6.
1988 12:48:55.869901 MTRR: UC selected as default type.
1989 12:48:55.876142 MTRR: 0 base 0x0000000000000000 mask 0x0000007f80000000 type 6
1990 12:48:55.879980 MTRR: 1 base 0x0000000077000000 mask 0x0000007fff000000 type 0
1991 12:48:55.886047 MTRR: 2 base 0x0000000078000000 mask 0x0000007ff8000000 type 0
1992 12:48:55.893057 MTRR: 3 base 0x0000000080000000 mask 0x0000007ff0000000 type 1
1993 12:48:55.899375 MTRR: 4 base 0x0000000100000000 mask 0x0000007f00000000 type 6
1994 12:48:55.906112 MTRR: 5 base 0x0000000200000000 mask 0x0000007f00000000 type 6
1995 12:48:55.912705 MTRR: Fixed MSR 0x250 0x0606060606060606
1996 12:48:55.916238 MTRR: Fixed MSR 0x258 0x0606060606060606
1997 12:48:55.919373 MTRR: Fixed MSR 0x259 0x0000000000000000
1998 12:48:55.922824 MTRR: Fixed MSR 0x268 0x0606060606060606
1999 12:48:55.926202 MTRR: Fixed MSR 0x269 0x0606060606060606
2000 12:48:55.932687 MTRR: Fixed MSR 0x26a 0x0606060606060606
2001 12:48:55.936090 MTRR: Fixed MSR 0x26b 0x0606060606060606
2002 12:48:55.939649 MTRR: Fixed MSR 0x26c 0x0606060606060606
2003 12:48:55.942882 MTRR: Fixed MSR 0x26d 0x0606060606060606
2004 12:48:55.949674 MTRR: Fixed MSR 0x26e 0x0606060606060606
2005 12:48:55.952661 MTRR: Fixed MSR 0x26f 0x0606060606060606
2006 12:48:55.952749
2007 12:48:55.956020 MTRR check
2008 12:48:55.956109 call enable_fixed_mtrr()
2009 12:48:55.959633 Fixed MTRRs : Enabled
2010 12:48:55.962532 Variable MTRRs: Enabled
2011 12:48:55.962621
2012 12:48:55.966193 CPU physical address size: 39 bits
2013 12:48:55.972525 BS: BS_WRITE_TABLES exit times (exec / console): 50 / 151 ms
2014 12:48:55.976141 MTRR: Fixed MSR 0x250 0x0606060606060606
2015 12:48:55.982412 MTRR: Fixed MSR 0x250 0x0606060606060606
2016 12:48:55.986116 MTRR: Fixed MSR 0x258 0x0606060606060606
2017 12:48:55.989157 MTRR: Fixed MSR 0x259 0x0000000000000000
2018 12:48:55.992729 MTRR: Fixed MSR 0x268 0x0606060606060606
2019 12:48:55.999002 MTRR: Fixed MSR 0x269 0x0606060606060606
2020 12:48:56.002709 MTRR: Fixed MSR 0x26a 0x0606060606060606
2021 12:48:56.005718 MTRR: Fixed MSR 0x26b 0x0606060606060606
2022 12:48:56.009229 MTRR: Fixed MSR 0x26c 0x0606060606060606
2023 12:48:56.012657 MTRR: Fixed MSR 0x26d 0x0606060606060606
2024 12:48:56.019304 MTRR: Fixed MSR 0x26e 0x0606060606060606
2025 12:48:56.022351 MTRR: Fixed MSR 0x26f 0x0606060606060606
2026 12:48:56.025816 MTRR: Fixed MSR 0x258 0x0606060606060606
2027 12:48:56.032215 MTRR: Fixed MSR 0x259 0x0000000000000000
2028 12:48:56.035946 MTRR: Fixed MSR 0x268 0x0606060606060606
2029 12:48:56.039314 MTRR: Fixed MSR 0x269 0x0606060606060606
2030 12:48:56.042588 MTRR: Fixed MSR 0x26a 0x0606060606060606
2031 12:48:56.048845 MTRR: Fixed MSR 0x26b 0x0606060606060606
2032 12:48:56.052492 MTRR: Fixed MSR 0x26c 0x0606060606060606
2033 12:48:56.055761 MTRR: Fixed MSR 0x26d 0x0606060606060606
2034 12:48:56.058861 MTRR: Fixed MSR 0x26e 0x0606060606060606
2035 12:48:56.065647 MTRR: Fixed MSR 0x26f 0x0606060606060606
2036 12:48:56.068693 call enable_fixed_mtrr()
2037 12:48:56.068782 call enable_fixed_mtrr()
2038 12:48:56.075670 MTRR: Fixed MSR 0x250 0x0606060606060606
2039 12:48:56.078752 MTRR: Fixed MSR 0x250 0x0606060606060606
2040 12:48:56.082521 MTRR: Fixed MSR 0x258 0x0606060606060606
2041 12:48:56.085565 MTRR: Fixed MSR 0x259 0x0000000000000000
2042 12:48:56.091940 MTRR: Fixed MSR 0x268 0x0606060606060606
2043 12:48:56.095512 MTRR: Fixed MSR 0x269 0x0606060606060606
2044 12:48:56.098456 MTRR: Fixed MSR 0x26a 0x0606060606060606
2045 12:48:56.102277 MTRR: Fixed MSR 0x26b 0x0606060606060606
2046 12:48:56.108945 MTRR: Fixed MSR 0x26c 0x0606060606060606
2047 12:48:56.112043 MTRR: Fixed MSR 0x26d 0x0606060606060606
2048 12:48:56.115121 MTRR: Fixed MSR 0x26e 0x0606060606060606
2049 12:48:56.118467 MTRR: Fixed MSR 0x26f 0x0606060606060606
2050 12:48:56.125617 MTRR: Fixed MSR 0x258 0x0606060606060606
2051 12:48:56.125707 call enable_fixed_mtrr()
2052 12:48:56.132329 MTRR: Fixed MSR 0x259 0x0000000000000000
2053 12:48:56.135652 MTRR: Fixed MSR 0x268 0x0606060606060606
2054 12:48:56.139129 MTRR: Fixed MSR 0x269 0x0606060606060606
2055 12:48:56.142014 MTRR: Fixed MSR 0x26a 0x0606060606060606
2056 12:48:56.149072 MTRR: Fixed MSR 0x26b 0x0606060606060606
2057 12:48:56.152155 MTRR: Fixed MSR 0x26c 0x0606060606060606
2058 12:48:56.155459 MTRR: Fixed MSR 0x26d 0x0606060606060606
2059 12:48:56.158557 MTRR: Fixed MSR 0x26e 0x0606060606060606
2060 12:48:56.165531 MTRR: Fixed MSR 0x26f 0x0606060606060606
2061 12:48:56.168709 CPU physical address size: 39 bits
2062 12:48:56.172226 call enable_fixed_mtrr()
2063 12:48:56.175471 CPU physical address size: 39 bits
2064 12:48:56.179219 CPU physical address size: 39 bits
2065 12:48:56.185523 CPU physical address size: 39 bits
2066 12:48:56.188855 MTRR: Fixed MSR 0x250 0x0606060606060606
2067 12:48:56.192290 MTRR: Fixed MSR 0x250 0x0606060606060606
2068 12:48:56.195477 MTRR: Fixed MSR 0x258 0x0606060606060606
2069 12:48:56.199054 MTRR: Fixed MSR 0x259 0x0000000000000000
2070 12:48:56.205260 MTRR: Fixed MSR 0x268 0x0606060606060606
2071 12:48:56.209002 MTRR: Fixed MSR 0x269 0x0606060606060606
2072 12:48:56.211947 MTRR: Fixed MSR 0x26a 0x0606060606060606
2073 12:48:56.215214 MTRR: Fixed MSR 0x26b 0x0606060606060606
2074 12:48:56.222285 MTRR: Fixed MSR 0x26c 0x0606060606060606
2075 12:48:56.225250 MTRR: Fixed MSR 0x26d 0x0606060606060606
2076 12:48:56.228775 MTRR: Fixed MSR 0x26e 0x0606060606060606
2077 12:48:56.231864 MTRR: Fixed MSR 0x26f 0x0606060606060606
2078 12:48:56.239909 MTRR: Fixed MSR 0x258 0x0606060606060606
2079 12:48:56.240418 call enable_fixed_mtrr()
2080 12:48:56.246363 MTRR: Fixed MSR 0x259 0x0000000000000000
2081 12:48:56.249734 MTRR: Fixed MSR 0x268 0x0606060606060606
2082 12:48:56.252673 MTRR: Fixed MSR 0x269 0x0606060606060606
2083 12:48:56.256307 MTRR: Fixed MSR 0x26a 0x0606060606060606
2084 12:48:56.262856 MTRR: Fixed MSR 0x26b 0x0606060606060606
2085 12:48:56.266158 MTRR: Fixed MSR 0x26c 0x0606060606060606
2086 12:48:56.269858 MTRR: Fixed MSR 0x26d 0x0606060606060606
2087 12:48:56.272915 MTRR: Fixed MSR 0x26e 0x0606060606060606
2088 12:48:56.279046 MTRR: Fixed MSR 0x26f 0x0606060606060606
2089 12:48:56.282862 CPU physical address size: 39 bits
2090 12:48:56.286108 call enable_fixed_mtrr()
2091 12:48:56.289693 Checking cr50 for pending updates
2092 12:48:56.292979 CPU physical address size: 39 bits
2093 12:48:56.296765 Reading cr50 TPM mode
2094 12:48:56.306918 BS: BS_PAYLOAD_LOAD entry times (exec / console): 322 / 6 ms
2095 12:48:56.316614 CBFS: Found 'fallback/payload' @0x38db00 size 0x4be9c in mcache @0x76c4cf60
2096 12:48:56.320381 Checking segment from ROM address 0xffc02b38
2097 12:48:56.323623 Checking segment from ROM address 0xffc02b54
2098 12:48:56.330028 Loading segment from ROM address 0xffc02b38
2099 12:48:56.330592 code (compression=0)
2100 12:48:56.340229 New segment dstaddr 0x30000000 memsize 0x2662db0 srcaddr 0xffc02b70 filesize 0x4be64
2101 12:48:56.350246 Loading Segment: addr: 0x30000000 memsz: 0x0000000002662db0 filesz: 0x000000000004be64
2102 12:48:56.350753 it's not compressed!
2103 12:48:56.489561 [ 0x30000000, 3004be64, 0x32662db0) <- ffc02b70
2104 12:48:56.495896 Clearing Segment: addr: 0x000000003004be64 memsz: 0x0000000002616f4c
2105 12:48:56.502935 Loading segment from ROM address 0xffc02b54
2106 12:48:56.503390 Entry Point 0x30000000
2107 12:48:56.506506 Loaded segments
2108 12:48:56.512813 BS: BS_PAYLOAD_LOAD run times (exec / console): 135 / 63 ms
2109 12:48:56.555696 Finalizing chipset.
2110 12:48:56.558741 Finalizing SMM.
2111 12:48:56.559196 APMC done.
2112 12:48:56.565752 BS: BS_PAYLOAD_LOAD exit times (exec / console): 42 / 5 ms
2113 12:48:56.568806 mp_park_aps done after 0 msecs.
2114 12:48:56.572284 Jumping to boot code at 0x30000000(0x76b25000)
2115 12:48:56.582506 CPU0: stack: 0x76bee000 - 0x76bef000, lowest used address 0x76beea78, stack used: 1416 bytes
2116 12:48:56.583039
2117 12:48:56.583423
2118 12:48:56.583763
2119 12:48:56.585537 Starting depthcharge on Voema...
2120 12:48:56.586167
2121 12:48:56.587370 end: 2.2.3 depthcharge-start (duration 00:00:10) [common]
2122 12:48:56.588118 start: 2.2.4 bootloader-commands (timeout 00:04:45) [common]
2123 12:48:56.588683 Setting prompt string to ['volteer:']
2124 12:48:56.589184 bootloader-commands: Wait for prompt ['volteer:'] (timeout 00:04:45)
2125 12:48:56.595796 WARNING: can't convert coreboot GPIOs, 'lid' won't be resampled at runtime!
2126 12:48:56.596276
2127 12:48:56.602045 WARNING: can't convert coreboot GPIOs, 'power' won't be resampled at runtime!
2128 12:48:56.602566
2129 12:48:56.605249 Looking for NVMe Controller 0x3005f220 @ 00:1d:00
2130 12:48:56.608539
2131 12:48:56.612188 Failed to find eMMC card reader
2132 12:48:56.612764
2133 12:48:56.613154 Wipe memory regions:
2134 12:48:56.613495
2135 12:48:56.618413 [0x00000000001000, 0x000000000a0000)
2136 12:48:56.618888
2137 12:48:56.622008 [0x00000000100000, 0x00000030000000)
2138 12:48:56.646959
2139 12:48:56.650640 [0x00000032662db0, 0x000000769ef000)
2140 12:48:56.685720
2141 12:48:56.689372 [0x00000100000000, 0x00000280400000)
2142 12:48:56.892127
2143 12:48:56.895060 ec_init: CrosEC protocol v3 supported (256, 256)
2144 12:48:56.895539
2145 12:48:56.901897 update_port_state: port C0 state: usb enable 1 mux conn 0
2146 12:48:56.902384
2147 12:48:56.912067 update_port_state: port C0 req: usage 0 usb3 1 usb2 9 ufp 1 ori_hsl 0 ori_sbu 0 dbg_acc 1
2148 12:48:56.912610
2149 12:48:56.918458 pmc_check_ipc_sts: STS_BUSY done after 1612 us
2150 12:48:56.919057
2151 12:48:56.921571 send_conn_disc_msg: pmc_send_cmd succeeded
2152 12:48:57.354645
2153 12:48:57.354821 R8152: Initializing
2154 12:48:57.354920
2155 12:48:57.357746 Version 9 (ocp_data = 6010)
2156 12:48:57.357827
2157 12:48:57.360843 R8152: Done initializing
2158 12:48:57.360924
2159 12:48:57.364418 Adding net device
2160 12:48:57.666401
2161 12:48:57.669434 [firmware-volteer-13672.B-collabora] Oct 22 2021 06:32:35
2162 12:48:57.669534
2163 12:48:57.669622
2164 12:48:57.669704
2165 12:48:57.672606 Setting prompt string to ['volteer:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2167 12:48:57.773338 volteer: tftpboot 192.168.201.1 9584814/tftp-deploy-ti558n_g/kernel/bzImage 9584814/tftp-deploy-ti558n_g/kernel/cmdline 9584814/tftp-deploy-ti558n_g/ramdisk/ramdisk.cpio.gz
2168 12:48:57.773477 Setting prompt string to ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2169 12:48:57.773565 bootloader-commands: Wait for prompt ['Starting kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:43)
2170 12:48:57.778295 tftpboot 192.168.201.1 9584814/tftp-deploy-ti558n_g/kernel/bzImaoy-ti558n_g/kernel/cmdline 9584814/tftp-deploy-ti558n_g/ramdisk/ramdisk.cpio.gz
2171 12:48:57.778383
2172 12:48:57.778454 Waiting for link
2173 12:48:57.981334
2174 12:48:57.981515 done.
2175 12:48:57.981605
2176 12:48:57.981686 MAC: 00:e0:4c:71:a6:42
2177 12:48:57.981765
2178 12:48:57.984763 Sending DHCP discover... done.
2179 12:48:57.984883
2180 12:48:57.988331 Waiting for reply... done.
2181 12:48:57.988462
2182 12:48:57.991403 Sending DHCP request... done.
2183 12:48:57.991536
2184 12:48:57.994904 Waiting for reply... done.
2185 12:48:57.995050
2186 12:48:57.998067 My ip is 192.168.201.18
2187 12:48:57.998147
2188 12:48:58.001277 The DHCP server ip is 192.168.201.1
2189 12:48:58.001354
2190 12:48:58.007952 TFTP server IP predefined by user: 192.168.201.1
2191 12:48:58.008034
2192 12:48:58.014710 Bootfile predefined by user: 9584814/tftp-deploy-ti558n_g/kernel/bzImage
2193 12:48:58.014799
2194 12:48:58.017880 Sending tftp read request... done.
2195 12:48:58.017974
2196 12:48:58.020939 Waiting for the transfer...
2197 12:48:58.021019
2198 12:48:58.274842 00000000 ################################################################
2199 12:48:58.275001
2200 12:48:58.523984 00080000 ################################################################
2201 12:48:58.524138
2202 12:48:58.764227 00100000 ################################################################
2203 12:48:58.764390
2204 12:48:59.010271 00180000 ################################################################
2205 12:48:59.010418
2206 12:48:59.253765 00200000 ################################################################
2207 12:48:59.253926
2208 12:48:59.499559 00280000 ################################################################
2209 12:48:59.499716
2210 12:48:59.746057 00300000 ################################################################
2211 12:48:59.746213
2212 12:48:59.995015 00380000 ################################################################
2213 12:48:59.995159
2214 12:49:00.245330 00400000 ################################################################
2215 12:49:00.245481
2216 12:49:00.492517 00480000 ################################################################
2217 12:49:00.492666
2218 12:49:00.748519 00500000 ################################################################
2219 12:49:00.748674
2220 12:49:01.033704 00580000 ################################################################
2221 12:49:01.033860
2222 12:49:01.287816 00600000 ################################################################
2223 12:49:01.287981
2224 12:49:01.534004 00680000 ################################################################
2225 12:49:01.534155
2226 12:49:01.670305 00700000 ##################################### done.
2227 12:49:01.670445
2228 12:49:01.673524 The bootfile was 7638928 bytes long.
2229 12:49:01.673609
2230 12:49:01.676505 Sending tftp read request... done.
2231 12:49:01.676586
2232 12:49:01.680189 Waiting for the transfer...
2233 12:49:01.680268
2234 12:49:01.958959 00000000 ################################################################
2235 12:49:01.959110
2236 12:49:02.235498 00080000 ################################################################
2237 12:49:02.235636
2238 12:49:02.487909 00100000 ################################################################
2239 12:49:02.488049
2240 12:49:02.727665 00180000 ################################################################
2241 12:49:02.727823
2242 12:49:02.970426 00200000 ################################################################
2243 12:49:02.970593
2244 12:49:03.212517 00280000 ################################################################
2245 12:49:03.212677
2246 12:49:03.456955 00300000 ################################################################
2247 12:49:03.457110
2248 12:49:03.698016 00380000 ################################################################
2249 12:49:03.698161
2250 12:49:03.943532 00400000 ################################################################
2251 12:49:03.943686
2252 12:49:04.187147 00480000 ################################################################
2253 12:49:04.187289
2254 12:49:04.419491 00500000 ############################################################### done.
2255 12:49:04.419647
2256 12:49:04.422922 Sending tftp read request... done.
2257 12:49:04.426425
2258 12:49:04.426517 Waiting for the transfer...
2259 12:49:04.426588
2260 12:49:04.429760 00000000 # done.
2261 12:49:04.429851
2262 12:49:04.439668 Command line loaded dynamically from TFTP file: 9584814/tftp-deploy-ti558n_g/kernel/cmdline
2263 12:49:04.439758
2264 12:49:04.455846 The command line is: console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/9584814/extract-nfsrootfs-ywgv904d,tcp,hard ip=dhcp tftpserverip=192.168.201.1
2265 12:49:04.461931
2266 12:49:04.465136 Shutting down all USB controllers.
2267 12:49:04.465227
2268 12:49:04.465297 Removing current net device
2269 12:49:04.465362
2270 12:49:04.468845 Finalizing coreboot
2271 12:49:04.468933
2272 12:49:04.475281 Exiting depthcharge with code 4 at timestamp: 16561886
2273 12:49:04.475369
2274 12:49:04.475438
2275 12:49:04.475503 Starting kernel ...
2276 12:49:04.475566
2277 12:49:04.475626
2278 12:49:04.475987 end: 2.2.4 bootloader-commands (duration 00:00:08) [common]
2279 12:49:04.476092 start: 2.2.5 auto-login-action (timeout 00:04:37) [common]
2280 12:49:04.476170 Setting prompt string to ['Linux version [0-9]']
2281 12:49:04.476242 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
2282 12:49:04.476319 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
2284 12:53:41.477165 end: 2.2.5 auto-login-action (duration 00:04:37) [common]
2286 12:53:41.478326 depthcharge-retry failed: 1 of 1 attempts. 'auto-login-action timed out after 277 seconds'
2288 12:53:41.479228 end: 2.2 depthcharge-retry (duration 00:05:00) [common]
2291 12:53:41.480784 end: 2 depthcharge-action (duration 00:05:00) [common]
2293 12:53:41.482045 Cleaning after the job
2294 12:53:41.482521 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/9584814/tftp-deploy-ti558n_g/ramdisk
2295 12:53:41.485081 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/9584814/tftp-deploy-ti558n_g/kernel
2296 12:53:41.488192 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/9584814/tftp-deploy-ti558n_g/nfsrootfs
2297 12:53:41.565768 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/9584814/tftp-deploy-ti558n_g/modules
2298 12:53:41.566118 start: 4.1 power-off (timeout 00:00:30) [common]
2299 12:53:41.566285 Calling: 'nice' 'pduclient' '--daemon=localhost' '--hostname=asus-cx9400-volteer-cbg-7' '--port=1' '--command=off'
2300 12:53:41.641860 >> Command sent successfully.
2301 12:53:41.645617 Returned 0 in 0 seconds
2302 12:53:41.746524 end: 4.1 power-off (duration 00:00:00) [common]
2304 12:53:41.746861 start: 4.2 read-feedback (timeout 00:10:00) [common]
2305 12:53:41.747102 Listened to connection for namespace 'common' for up to 1s
2306 12:53:42.752265 Finalising connection for namespace 'common'
2307 12:53:42.753006 Disconnecting from shell: Finalise
2308 12:53:42.753444
2309 12:53:42.855710 end: 4.2 read-feedback (duration 00:00:01) [common]
2310 12:53:42.856396 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/9584814
2311 12:53:43.008437 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/9584814
2312 12:53:43.008643 JobError: Your job cannot terminate cleanly.