[Enter `^Ec?' for help] coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 bootblock starting... Family_Model: 00670f00 PMxC0 STATUS: 0x80800 DoReset BIT11 DW I2C bus 1 at 0xfedc3000 (400 KHz) VBOOT: Loading verstage. CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'fallback/verstage' CBFS: Found @ offset aa8c0 size d5a4 coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 verstage starting... Probing TPM I2C: done! DID_VID 0x00281ae0 TPM ready after 0 ms cr50 TPM 2.0 (i2c 1:0x50 id 0x28) TPM: setup succeeded src/security/tpm/tss/tcg-2.0/tss.c:177 index 0x1007 return code 0 Chrome EC: UHEPI supported Phase 1 FMAP: Found "FLASH" version 1.1 at d7f000. FMAP: base = ff000000 size = 1000000 #areas = 30 FMAP: area GBB found @ d80000 (458752 bytes) VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0 Phase 2 Phase 3 FMAP: area GBB found @ d80000 (458752 bytes) VB2:vb2_report_dev_firmware() This is developer signed firmware FMAP: area VBLOCK_A found @ 21000 (65536 bytes) FMAP: area VBLOCK_A found @ 21000 (65536 bytes) VB2:vb2_verify_keyblock() Checking key block signature... FMAP: area VBLOCK_A found @ 21000 (65536 bytes) FMAP: area VBLOCK_A found @ 21000 (65536 bytes) VB2:vb2_verify_fw_preamble() Verifying preamble. Phase 4 FMAP: area FW_MAIN_A found @ 31000 (2154432 bytes) VB2:vb2api_init_hash() HW crypto for hash_alg 2 not supported, using SW VB2:vb2_rsa_verify_digest() Digest check failed! VB2:vb2_fail() Need recovery, reason: 0x1b / 0x7 Saving nvdata Reboot requested (10020007) board_reset() called! coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 bootblock starting... Family_Model: 00670f00 PMxC0 STATUS: 0x80800 DoReset BIT11 DW I2C bus 1 at 0xfedc3000 (400 KHz) VBOOT: Loading verstage. CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'fallback/verstage' CBFS: Found @ offset aa8c0 size d5a4 coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 verstage starting... Probing TPM I2C: done! DID_VID 0x00281ae0 TPM ready after 0 ms cr50 TPM 2.0 (i2c 1:0x50 id 0x28) TPM: setup succeeded src/security/tpm/tss/tcg-2.0/tss.c:177 index 0x1007 return code 0 Chrome EC: UHEPI supported Phase 1 FMAP: Found "FLASH" version 1.1 at d7f000. FMAP: base = ff000000 size = 1000000 #areas = 30 FMAP: area GBB found @ d80000 (458752 bytes) VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x0 Recovery requested (1009000e) Saving nvdata tlcl_extend: response is 0 tlcl_extend: response is 0 CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'fallback/romstage' CBFS: Found @ offset 80 size d2e4 coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 romstage starting... CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'smu_fw' CBFS: Found @ offset 7bc00 size 12262 PSP: Load blob type 19 from @ffe6bc38... OK Google Chrome set keyboard backlight: 4 status (0) POST: 0x37 agesawrapper_amdinitreset() entry CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'AGESA_PRE_MEM' CBFS: Found @ offset df80 size 53bcc agesawrapper_amdinitreset() returned AGESA_SUCCESS POST: 0x38 agesawrapper_amdinitearly() entry Warning - AGESA callout: platform_PcieSlotResetControl not supported Warning - AGESA callout: platform_PcieSlotResetControl not supported agesawrapper_amdinitearly() returned AGESA_SUCCESS POST: 0x40 agesawrapper_amdinitpost() entry DRAM clear on reset: Keep variant_mainboard_read_spd SPD index 9 CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'spd.bin' CBFS: Found @ offset 79bc0 size 2000 AGESA set: umamode UMA_SPECIFIED : syslimit 0x12effffff, bottomio 0x00d00000 : uma size 16MB, uma start 0xcf000000 agesawrapper_amdinitpost() returned AGESA_SUCCESS POST: 0x41 Boot Count incremented to 69453 POST: 0x42 PSP: Notify that DRAM is available... OK POST: 0x43 CBMEM: IMD: root @ cdfff000 254 entries. IMD: root @ cdffec00 62 entries. External stage cache: IMD: root @ cefff000 254 entries. IMD: root @ ceffec00 62 entries. creating vboot_handoff structure Chrome EC: UHEPI supported Chrome EC: clear events_b mask to 0x0000000021004000 POST: 0x44 MTRR Range: Start=cd000000 End=ce000000 (Size 1000000) MTRR Range: Start=ff000000 End=0 (Size 1000000) MTRR Range: Start=ce800000 End=cf000000 (Size 800000) POST: 0x45 CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'fallback/postcar' CBFS: Found @ offset a2a80 size 41f4 Decompressing stage fallback/postcar @ 0xcdfa1fc0 (33488 bytes) Loading module at cdfa2000 with entry cdfa2000. filesize: 0x3fd0 memsize: 0x8290 Processing 114 relocs. Offset value of 0xcbfa2000 coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 postcar starting... CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'fallback/ramstage' CBFS: Found @ offset 61bc0 size 17f95 Decompressing stage fallback/ramstage @ 0xcde9efc0 (1055256 bytes) Loading module at cde9f000 with entry cde9f000. filesize: 0x37198 memsize: 0x1019d8 Processing 3480 relocs. Offset value of 0xcdd9f000 coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 ramstage starting... POST: 0x39 FMAP: Found "FLASH" version 1.1 at d7f000. FMAP: base = ff000000 size = 1000000 #areas = 30 FMAP: area RO_VPD found @ c00000 (16384 bytes) WARNING: RO_VPD is uninitialized or empty. FMAP: area RW_VPD found @ 465000 (8192 bytes) FMAP: area RW_VPD found @ 465000 (8192 bytes) POST: 0x80 Normal boot. POST: 0x46 CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'smu_fw2' CBFS: Found @ offset 8dec0 size 4cf2 PSP: Load blob type 1a from @ffe7def8... OK POST: 0x47 agesawrapper_amdinitenv() entry CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'AGESA_POST_MEM' CBFS: Found @ offset b7f00 size 135b2 Decompressing stage AGESA_POST_MEM @ 0xcde6cfc0 (198492 bytes) Loading module at cde6d000 with entry cde6d000. filesize: 0x2f340 memsize: 0x2f480 Processing 1271 relocs. Offset value of 0xce06d000 AGESA: Saving stage to cache Fch OEM config in INIT ENV Done agesawrapper_amdinitenv() returned AGESA_SUCCESS POST: 0x70 BS: BS_PRE_DEVICE times (us): entry 124125 run 1061 exit 0 POST: 0x71 Board ID: 6 mainboard: EC init Chrome EC: Set SMI mask to 0x0000000000000000 Chrome EC: UHEPI supported Chrome EC: Set S5 LAZY WAKE mask to 0x0000000000000006 Chrome EC: Set S3 LAZY WAKE mask to 0x0000000010001006 Chrome EC: Set WAKE mask to 0x0000000000000000 DW I2C bus 0 at 0xfedc2000 (400 KHz) DW I2C bus 2 at 0xfedc4000 (400 KHz) DW I2C bus 3 at 0xfedc5000 (400 KHz) FMAP: area RW_ELOG found @ 45d000 (16384 bytes) Manufacturer: ef SF: Detected W25Q128FW with sector size 0x1000, total 0x1000000 ELOG: NV offset 0x45d000 size 0x4000 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024 ELOG: Event(17) added with size 13 at 2023-08-09 04:53:10 UTC POST: Unexpected post code in previous boot: 0x90 ELOG: Event(A3) added with size 11 at 2023-08-09 04:53:10 UTC ELOG: Event(9F) added with size 14 at 2023-08-09 04:53:10 UTC PM1_STS: PWRBTN BMSTATUS setup_bsp_ramtop, TOP MEM: msr.lo = 0xd0000000, msr.hi = 0x00000000 setup_bsp_ramtop, TOP MEM2: msr.lo = 0x2f000000, msr.hi = 0x00000001 BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 96210 exit 0 POST: 0x72 Enumerating buses... Show all devs... Before device enumeration. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 DOMAIN: 0000: enabled 1 MMIO: fedc2000: enabled 1 MMIO: fedc3000: enabled 1 MMIO: fedc4000: enabled 1 MMIO: fedc5000: enabled 1 APIC: 10: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.2: enabled 0 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 1 PCI: 00:02.2: enabled 1 PCI: 00:02.3: enabled 1 PCI: 00:02.4: enabled 1 PCI: 00:02.5: enabled 1 PCI: 00:08.0: enabled 1 PCI: 00:09.0: enabled 1 PCI: 00:09.2: enabled 1 PCI: 00:10.0: enabled 1 PCI: 00:11.0: enabled 0 PCI: 00:12.0: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:14.3: enabled 1 PCI: 00:14.7: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 GENERIC: 0.0: enabled 1 I2C: 00:1a: enabled 1 GENERIC: 0.1: enabled 1 I2C: 00:50: enabled 1 I2C: 00:15: enabled 1 I2C: 00:39: enabled 1 I2C: 00:10: enabled 1 PCI: 00:00.0: enabled 1 PNP: 0c09.0: enabled 1 Compare with tree... Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 10: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.2: enabled 0 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 1 PCI: 00:02.2: enabled 1 PCI: 00:02.3: enabled 1 PCI: 00:02.4: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:02.5: enabled 1 PCI: 00:08.0: enabled 1 PCI: 00:09.0: enabled 1 PCI: 00:09.2: enabled 1 PCI: 00:10.0: enabled 1 PCI: 00:11.0: enabled 0 PCI: 00:12.0: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:14.3: enabled 1 PNP: 0c09.0: enabled 1 PCI: 00:14.7: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 MMIO: fedc2000: enabled 1 GENERIC: 0.0: enabled 1 I2C: 00:1a: enabled 1 GENERIC: 0.1: enabled 1 MMIO: fedc3000: enabled 1 I2C: 00:50: enabled 1 MMIO: fedc4000: enabled 1 I2C: 00:15: enabled 1 MMIO: fedc5000: enabled 1 I2C: 00:39: enabled 1 I2C: 00:10: enabled 1 Mainboard Grunt Enable. Root Device scanning... root_dev_scan_bus for Root Device CPU_CLUSTER: 0 enabled DOMAIN: 0000 enabled MMIO: fedc2000 enabled MMIO: fedc3000 enabled MMIO: fedc4000 enabled MMIO: fedc5000 enabled DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 POST: 0x24 sb_enable PCI: 00:00.0 [1022/1576] enabled sb_enable sb_enable PCI: 00:01.0 [1002/98e4] enabled sb_enable PCI: 00:01.1 [1002/15b3] enabled sb_enable PCI: 00:02.0 [1022/157b] enabled sb_enable PCI: Static device PCI: 00:02.1 not found, disabling it. sb_enable Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xc0 Capability: type 0x08 @ 0xc8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 PCI: 00:02.2 subordinate bus PCI Express PCI: 00:02.2 [1022/157c] enabled sb_enable PCI: Static device PCI: 00:02.3 not found, disabling it. sb_enable Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xc0 Capability: type 0x08 @ 0xc8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 PCI: 00:02.4 subordinate bus PCI Express PCI: 00:02.4 [1022/157c] enabled sb_enable PCI: Static device PCI: 00:02.5 not found, disabling it. PCI: 00:03.0 [1022/157b] enabled sb_enable PCI: 00:08.0 [1022/1578] enabled sb_enable PCI: 00:09.0 [1022/157d] enabled sb_enable PCI: Static device PCI: 00:09.2 not found, disabling it. sb_enable PCI: 00:10.0 [1022/0000] bus ops PCI: 00:10.0 [1022/7914] enabled sb_enable sb_enable PCI: 00:12.0 [1022/0000] bus ops PCI: 00:12.0 [1022/7908] enabled sb_enable PCI: 00:14.0 [1022/790b] bus ops PCI: 00:14.0 [1022/790b] enabled sb_enable PCI: 00:14.3 [1022/0000] bus ops PCI: 00:14.3 [1022/790e] enabled sb_enable PCI: 00:14.7 [1022/7906] enabled sb_enable PCI: 00:18.0 [1022/15b0] ops PCI: 00:18.0 [1022/15b0] enabled sb_enable PCI: 00:18.1 [1022/15b1] enabled sb_enable PCI: 00:18.2 [1022/15b2] enabled sb_enable PCI: 00:18.3 [1022/15b3] enabled sb_enable PCI: 00:18.4 [1022/15b4] enabled sb_enable PCI: 00:18.5 [1022/15b5] enabled POST: 0x25 PCI: 00:02.2 scanning... do_pci_scan_bridge for PCI: 00:02.2 PCI: pci_scan_bus for bus 01 POST: 0x24 PCI: 01:00.0 [168c/003e] enabled POST: 0x25 POST: 0x55 Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x50 Capability: type 0x10 @ 0x70 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Enabling Common Clock Configuration ASPM: Enabled L0s and L1 Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x50 Capability: type 0x10 @ 0x70 scan_bus: scanning of bus PCI: 00:02.2 took 40758 usecs PCI: 00:02.4 scanning... do_pci_scan_bridge for PCI: 00:02.4 PCI: pci_scan_bus for bus 02 POST: 0x24 PCI: 02:00.0 [1217/0000] ops PCI: 02:00.0 [1217/8620] enabled POST: 0x25 POST: 0x55 Capability: type 0x01 @ 0x6c Capability: type 0x05 @ 0x48 Capability: type 0x10 @ 0x80 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 ASPM: Enabled L0s and L1 Capability: type 0x01 @ 0x6c Capability: type 0x05 @ 0x48 Capability: type 0x10 @ 0x80 scan_bus: scanning of bus PCI: 00:02.4 took 40311 usecs PCI: 00:10.0 scanning... scan_usb_bus for PCI: 00:10.0 scan_usb_bus for PCI: 00:10.0 done scan_bus: scanning of bus PCI: 00:10.0 took 8111 usecs PCI: 00:12.0 scanning... scan_usb_bus for PCI: 00:12.0 scan_usb_bus for PCI: 00:12.0 done scan_bus: scanning of bus PCI: 00:12.0 took 8110 usecs PCI: 00:14.0 scanning... scan_generic_bus for PCI: 00:14.0 scan_generic_bus for PCI: 00:14.0 done scan_bus: scanning of bus PCI: 00:14.0 took 8802 usecs PCI: 00:14.3 scanning... scan_lpc_bus for PCI: 00:14.3 PNP: 0c09.0 enabled scan_lpc_bus for PCI: 00:14.3 done scan_bus: scanning of bus PCI: 00:14.3 took 9949 usecs POST: 0x55 scan_bus: scanning of bus DOMAIN: 0000 took 315144 usecs MMIO: fedc2000 scanning... scan_generic_bus for MMIO: fedc2000 bus: MMIO: fedc2000[0]->GENERIC: 0.0 enabled bus: MMIO: fedc2000[0]->I2C: 01:1a enabled bus: MMIO: fedc2000[0]->GENERIC: 0.1 enabled scan_generic_bus for MMIO: fedc2000 done scan_bus: scanning of bus MMIO: fedc2000 took 21200 usecs MMIO: fedc3000 scanning... scan_generic_bus for MMIO: fedc3000 bus: MMIO: fedc3000[0]->I2C: 02:50 enabled scan_generic_bus for MMIO: fedc3000 done scan_bus: scanning of bus MMIO: fedc3000 took 13163 usecs MMIO: fedc4000 scanning... scan_generic_bus for MMIO: fedc4000 bus: MMIO: fedc4000[0]->I2C: 03:15 enabled scan_generic_bus for MMIO: fedc4000 done scan_bus: scanning of bus MMIO: fedc4000 took 13155 usecs MMIO: fedc5000 scanning... scan_generic_bus for MMIO: fedc5000 bus: MMIO: fedc5000[0]->I2C: 04:39 enabled bus: MMIO: fedc5000[0]->I2C: 04:10 enabled scan_generic_bus for MMIO: fedc5000 done scan_bus: scanning of bus MMIO: fedc5000 took 16987 usecs root_dev_scan_bus for Root Device done scan_bus: scanning of bus Root Device took 426234 usecs done BS: BS_DEV_ENUMERATE times (us): entry 0 run 631180 exit 0 POST: 0x73 found VGA at PCI: 00:01.0 Setting up VGA for PCI: 00:01.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done DOMAIN: 0000 read_resources bus 0 link: 0 PCI: 00:02.2 read_resources bus 1 link: 0 PCI: 00:02.2 read_resources bus 1 link: 0 done PCI: 00:02.4 read_resources bus 2 link: 0 PCI: 00:02.4 read_resources bus 2 link: 0 done PCI: 00:14.3 read_resources bus 0 link: 0 PCI: 00:14.3 read_resources bus 0 link: 0 done Adding PCIe enhanced config space BAR 0xf8000000-0xfc000000. DOMAIN: 0000 read_resources bus 0 link: 0 done MMIO: fedc2000 read_resources bus 1 link: 0 MMIO: fedc2000 read_resources bus 1 link: 0 done MMIO: fedc3000 read_resources bus 2 link: 0 MMIO: fedc3000 read_resources bus 2 link: 0 done MMIO: fedc4000 read_resources bus 3 link: 0 MMIO: fedc4000 read_resources bus 3 link: 0 done MMIO: fedc5000 read_resources bus 4 link: 0 MMIO: fedc5000 read_resources bus 4 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 10 APIC: 10 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI: 00:00.0 PCI: 00:00.2 PCI: 00:01.0 PCI: 00:01.0 resource base 0 size 4000000 align 26 gran 26 limit ffffffffffffffff flags 1201 index 10 PCI: 00:01.0 resource base 0 size 800000 align 23 gran 23 limit ffffffffffffffff flags 1201 index 18 PCI: 00:01.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 20 PCI: 00:01.0 resource base 0 size 40000 align 18 gran 18 limit ffffffff flags 200 index 24 PCI: 00:01.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 2200 index 30 PCI: 00:01.1 PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 PCI: 00:02.0 PCI: 00:02.1 PCI: 00:02.2 child on link 0 PCI: 01:00.0 PCI: 00:02.2 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:02.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:02.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 01:00.0 PCI: 01:00.0 resource base 0 size 200000 align 21 gran 21 limit ffffffffffffffff flags 201 index 10 PCI: 00:02.3 PCI: 00:02.4 child on link 0 PCI: 02:00.0 PCI: 00:02.4 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:02.4 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:02.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 02:00.0 PCI: 02:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 02:00.0 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 14 PCI: 00:02.5 PCI: 00:03.0 PCI: 00:08.0 PCI: 00:08.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 1201 index 10 PCI: 00:08.0 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 200 index 18 PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 1c PCI: 00:08.0 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 200 index 20 PCI: 00:08.0 resource base 0 size 2000 align 13 gran 13 limit ffffffff flags 200 index 24 PCI: 00:09.0 PCI: 00:09.2 PCI: 00:10.0 PCI: 00:10.0 resource base 0 size 2000 align 13 gran 13 limit ffffffffffffffff flags 201 index 10 PCI: 00:11.0 PCI: 00:12.0 PCI: 00:12.0 resource base 0 size 100 align 12 gran 8 limit ffffffff flags 200 index 10 PCI: 00:14.0 PCI: 00:14.3 child on link 0 PNP: 0c09.0 PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:14.3 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100 PCI: 00:14.3 resource base fec10000 size 400 align 0 gran 0 limit 0 flags e0040200 index 2 PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PCI: 00:14.3 resource base fedc2000 size 4000 align 0 gran 0 limit 0 flags c0000200 index 4 PNP: 0c09.0 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0 PCI: 00:14.7 PCI: 00:14.7 resource base 0 size 100 align 12 gran 8 limit ffffffffffffffff flags 201 index 10 PCI: 00:18.0 PCI: 00:18.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI: 00:18.0 resource base fec20000 size 1000 align 0 gran 0 limit 0 flags c0000200 index fec20000 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.4 PCI: 00:18.5 MMIO: fedc2000 child on link 0 GENERIC: 0.0 GENERIC: 0.0 I2C: 01:1a GENERIC: 0.1 MMIO: fedc3000 child on link 0 I2C: 02:50 I2C: 02:50 MMIO: fedc4000 child on link 0 I2C: 03:15 I2C: 03:15 MMIO: fedc5000 child on link 0 I2C: 04:39 I2C: 04:39 I2C: 04:10 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:02.2 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:02.2 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:02.4 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:02.4 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:01.0 20 * [0x0 - 0xff] io DOMAIN: 0000 io: base: 100 size: 100 align: 8 gran: 0 limit: ffff done DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:02.2 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:02.2 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:02.2 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 01:00.0 10 * [0x0 - 0x1fffff] mem PCI: 00:02.2 mem: base: 200000 size: 200000 align: 21 gran: 20 limit: ffffffff done PCI: 00:02.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:02.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:02.4 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 02:00.0 10 * [0x0 - 0xfff] mem PCI: 02:00.0 14 * [0x1000 - 0x17ff] mem PCI: 00:02.4 mem: base: 1800 size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:01.0 10 * [0x0 - 0x3ffffff] prefmem PCI: 00:01.0 18 * [0x4000000 - 0x47fffff] prefmem PCI: 00:02.2 20 * [0x4800000 - 0x49fffff] mem PCI: 00:02.4 20 * [0x4a00000 - 0x4afffff] mem PCI: 00:08.0 18 * [0x4b00000 - 0x4bfffff] mem PCI: 00:08.0 20 * [0x4c00000 - 0x4cfffff] mem PCI: 00:01.0 24 * [0x4d00000 - 0x4d3ffff] mem PCI: 00:01.0 30 * [0x4d40000 - 0x4d5ffff] mem PCI: 00:08.0 10 * [0x4d60000 - 0x4d7ffff] prefmem PCI: 00:01.1 10 * [0x4d80000 - 0x4d83fff] mem PCI: 00:08.0 24 * [0x4d84000 - 0x4d85fff] mem PCI: 00:10.0 10 * [0x4d86000 - 0x4d87fff] mem PCI: 00:08.0 1c * [0x4d88000 - 0x4d88fff] mem PCI: 00:12.0 10 * [0x4d89000 - 0x4d890ff] mem PCI: 00:14.7 10 * [0x4d8a000 - 0x4d8a0ff] mem DOMAIN: 0000 mem: base: 4d8a100 size: 4d8a100 align: 26 gran: 0 limit: ffffffff done avoid_fixed_resources: DOMAIN: 0000 avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI: 00:14.3 10000000 base 00000000 limit 00000fff io (fixed) constrain_resources: PCI: 00:14.3 10000100 base ff000000 limit ffffffff mem (fixed) constrain_resources: PCI: 00:14.3 02 base fec10000 limit fec103ff mem (fixed) constrain_resources: PCI: 00:14.3 03 base fec00000 limit fec00fff mem (fixed) constrain_resources: PCI: 00:18.0 c0010058 base f8000000 limit fbffffff mem (fixed) avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001000 limit 0000ffff avoid_fixed_resources:@DOMAIN: 0000 10000100 base f0000000 limit f7ffffff Setting resources... DOMAIN: 0000 io: base:1000 size:100 align:8 gran:0 limit:ffff PCI: 00:01.0 20 * [0x1000 - 0x10ff] io DOMAIN: 0000 io: next_base: 1100 size: 100 align: 8 gran: 0 done PCI: 00:02.2 io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:02.2 io: next_base: ffff size: 0 align: 12 gran: 12 done PCI: 00:02.4 io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:02.4 io: next_base: ffff size: 0 align: 12 gran: 12 done DOMAIN: 0000 mem: base:f0000000 size:4d8a100 align:26 gran:0 limit:f7ffffff PCI: 00:01.0 10 * [0xf0000000 - 0xf3ffffff] prefmem PCI: 00:01.0 18 * [0xf4000000 - 0xf47fffff] prefmem PCI: 00:02.2 20 * [0xf4800000 - 0xf49fffff] mem PCI: 00:02.4 20 * [0xf4a00000 - 0xf4afffff] mem PCI: 00:08.0 18 * [0xf4b00000 - 0xf4bfffff] mem PCI: 00:08.0 20 * [0xf4c00000 - 0xf4cfffff] mem PCI: 00:01.0 24 * [0xf4d00000 - 0xf4d3ffff] mem PCI: 00:01.0 30 * [0xf4d40000 - 0xf4d5ffff] mem PCI: 00:08.0 10 * [0xf4d60000 - 0xf4d7ffff] prefmem PCI: 00:01.1 10 * [0xf4d80000 - 0xf4d83fff] mem PCI: 00:08.0 24 * [0xf4d84000 - 0xf4d85fff] mem PCI: 00:10.0 10 * [0xf4d86000 - 0xf4d87fff] mem PCI: 00:08.0 1c * [0xf4d88000 - 0xf4d88fff] mem PCI: 00:12.0 10 * [0xf4d89000 - 0xf4d890ff] mem PCI: 00:14.7 10 * [0xf4d8a000 - 0xf4d8a0ff] mem DOMAIN: 0000 mem: next_base: f4d8a100 size: 4d8a100 align: 26 gran: 0 done PCI: 00:02.2 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff PCI: 00:02.2 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done PCI: 00:02.2 mem: base:f4800000 size:200000 align:21 gran:20 limit:f49fffff PCI: 01:00.0 10 * [0xf4800000 - 0xf49fffff] mem PCI: 00:02.2 mem: next_base: f4a00000 size: 200000 align: 21 gran: 20 done PCI: 00:02.4 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff PCI: 00:02.4 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done PCI: 00:02.4 mem: base:f4a00000 size:100000 align:20 gran:20 limit:f4afffff PCI: 02:00.0 10 * [0xf4a00000 - 0xf4a00fff] mem PCI: 02:00.0 14 * [0xf4a01000 - 0xf4a017ff] mem PCI: 00:02.4 mem: next_base: f4a01800 size: 100000 align: 20 gran: 20 done Root Device assign_resources, bus 0 link: 0 DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:01.0 10 <- [0x00f0000000 - 0x00f3ffffff] size 0x04000000 gran 0x1a prefmem64 PCI: 00:01.0 18 <- [0x00f4000000 - 0x00f47fffff] size 0x00800000 gran 0x17 prefmem64 PCI: 00:01.0 20 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io PCI: 00:01.0 24 <- [0x00f4d00000 - 0x00f4d3ffff] size 0x00040000 gran 0x12 mem PCI: 00:01.0 30 <- [0x00f4d40000 - 0x00f4d5ffff] size 0x00020000 gran 0x11 romem PCI: 00:01.1 10 <- [0x00f4d80000 - 0x00f4d83fff] size 0x00004000 gran 0x0e mem64 PCI: 00:02.2 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io PCI: 00:02.2 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 01 prefmem PCI: 00:02.2 20 <- [0x00f4800000 - 0x00f49fffff] size 0x00200000 gran 0x14 bus 01 mem PCI: 00:02.2 assign_resources, bus 1 link: 0 PCI: 01:00.0 10 <- [0x00f4800000 - 0x00f49fffff] size 0x00200000 gran 0x15 mem64 PCI: 00:02.2 assign_resources, bus 1 link: 0 PCI: 00:02.4 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io PCI: 00:02.4 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 02 prefmem PCI: 00:02.4 20 <- [0x00f4a00000 - 0x00f4afffff] size 0x00100000 gran 0x14 bus 02 mem PCI: 00:02.4 assign_resources, bus 2 link: 0 PCI: 02:00.0 10 <- [0x00f4a00000 - 0x00f4a00fff] size 0x00001000 gran 0x0c mem PCI: 02:00.0 14 <- [0x00f4a01000 - 0x00f4a017ff] size 0x00000800 gran 0x0b mem PCI: 00:02.4 assign_resources, bus 2 link: 0 PCI: 00:08.0 10 <- [0x00f4d60000 - 0x00f4d7ffff] size 0x00020000 gran 0x11 prefmem64 PCI: 00:08.0 18 <- [0x00f4b00000 - 0x00f4bfffff] size 0x00100000 gran 0x14 mem PCI: 00:08.0 1c <- [0x00f4d88000 - 0x00f4d88fff] size 0x00001000 gran 0x0c mem PCI: 00:08.0 20 <- [0x00f4c00000 - 0x00f4cfffff] size 0x00100000 gran 0x14 mem PCI: 00:08.0 24 <- [0x00f4d84000 - 0x00f4d85fff] size 0x00002000 gran 0x0d mem PCI: 00:10.0 10 <- [0x00f4d86000 - 0x00f4d87fff] size 0x00002000 gran 0x0d mem64 PCI: 00:12.0 10 <- [0x00f4d89000 - 0x00f4d890ff] size 0x00000100 gran 0x08 mem PCI: 00:14.3 assign_resources, bus 0 link: 0 PCI: 00:14.3 assign_resources, bus 0 link: 0 PCI: 00:14.7 10 <- [0x00f4d8a000 - 0x00f4d8a0ff] size 0x00000100 gran 0x08 mem64 DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 10 APIC: 10 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 1000 size 100 align 8 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base f0000000 size 4d8a100 align 26 gran 0 limit f7ffffff flags 40040200 index 10000100 DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10 DOMAIN: 0000 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11 DOMAIN: 0000 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12 DOMAIN: 0000 resource base 100000 size cdf00000 align 0 gran 0 limit 0 flags e0004200 index 13 DOMAIN: 0000 resource base ce000000 size 2000000 align 0 gran 0 limit 0 flags f0004200 index 14 DOMAIN: 0000 resource base 100000000 size 2f000000 align 0 gran 0 limit 0 flags e0004200 index 15 PCI: 00:00.0 PCI: 00:00.2 PCI: 00:01.0 PCI: 00:01.0 resource base f0000000 size 4000000 align 26 gran 26 limit f3ffffff flags 60001201 index 10 PCI: 00:01.0 resource base f4000000 size 800000 align 23 gran 23 limit f47fffff flags 60001201 index 18 PCI: 00:01.0 resource base 1000 size 100 align 8 gran 8 limit 10ff flags 60000100 index 20 PCI: 00:01.0 resource base f4d00000 size 40000 align 18 gran 18 limit f4d3ffff flags 60000200 index 24 PCI: 00:01.0 resource base f4d40000 size 20000 align 17 gran 17 limit f4d5ffff flags 60002200 index 30 PCI: 00:01.1 PCI: 00:01.1 resource base f4d80000 size 4000 align 14 gran 14 limit f4d83fff flags 60000201 index 10 PCI: 00:02.0 PCI: 00:02.1 PCI: 00:02.2 child on link 0 PCI: 01:00.0 PCI: 00:02.2 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:02.2 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24 PCI: 00:02.2 resource base f4800000 size 200000 align 21 gran 20 limit f49fffff flags 60080202 index 20 PCI: 01:00.0 PCI: 01:00.0 resource base f4800000 size 200000 align 21 gran 21 limit f49fffff flags 60000201 index 10 PCI: 00:02.3 PCI: 00:02.4 child on link 0 PCI: 02:00.0 PCI: 00:02.4 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:02.4 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24 PCI: 00:02.4 resource base f4a00000 size 100000 align 20 gran 20 limit f4afffff flags 60080202 index 20 PCI: 02:00.0 PCI: 02:00.0 resource base f4a00000 size 1000 align 12 gran 12 limit f4a00fff flags 60000200 index 10 PCI: 02:00.0 resource base f4a01000 size 800 align 12 gran 11 limit f4a017ff flags 60000200 index 14 PCI: 00:02.5 PCI: 00:03.0 PCI: 00:08.0 PCI: 00:08.0 resource base f4d60000 size 20000 align 17 gran 17 limit f4d7ffff flags 60001201 index 10 PCI: 00:08.0 resource base f4b00000 size 100000 align 20 gran 20 limit f4bfffff flags 60000200 index 18 PCI: 00:08.0 resource base f4d88000 size 1000 align 12 gran 12 limit f4d88fff flags 60000200 index 1c PCI: 00:08.0 resource base f4c00000 size 100000 align 20 gran 20 limit f4cfffff flags 60000200 index 20 PCI: 00:08.0 resource base f4d84000 size 2000 align 13 gran 13 limit f4d85fff flags 60000200 index 24 PCI: 00:09.0 PCI: 00:09.2 PCI: 00:10.0 PCI: 00:10.0 resource base f4d86000 size 2000 align 13 gran 13 limit f4d87fff flags 60000201 index 10 PCI: 00:11.0 PCI: 00:12.0 PCI: 00:12.0 resource base f4d89000 size 100 align 12 gran 8 limit f4d890ff flags 60000200 index 10 PCI: 00:14.0 PCI: 00:14.3 child on link 0 PNP: 0c09.0 PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:14.3 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100 PCI: 00:14.3 resource base fec10000 size 400 align 0 gran 0 limit 0 flags e0040200 index 2 PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PCI: 00:14.3 resource base fedc2000 size 4000 align 0 gran 0 limit 0 flags c0000200 index 4 PNP: 0c09.0 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0 PCI: 00:14.7 PCI: 00:14.7 resource base f4d8a000 size 100 align 12 gran 8 limit f4d8a0ff flags 60000201 index 10 PCI: 00:18.0 PCI: 00:18.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI: 00:18.0 resource base fec20000 size 1000 align 0 gran 0 limit 0 flags c0000200 index fec20000 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.4 PCI: 00:18.5 MMIO: fedc2000 child on link 0 GENERIC: 0.0 GENERIC: 0.0 I2C: 01:1a GENERIC: 0.1 MMIO: fedc3000 child on link 0 I2C: 02:50 I2C: 02:50 MMIO: fedc4000 child on link 0 I2C: 03:15 I2C: 03:15 MMIO: fedc5000 child on link 0 I2C: 04:39 I2C: 04:39 I2C: 04:10 Done allocating resources. BS: BS_DEV_RESOURCES times (us): entry 0 run 1563930 exit 0 PCI_INTR tables: Writing registers C00/C01 for PCI IRQ routing: PCI_INTR_INDEX name PIC mode APIC mode 0x00 INTA# 0x03 0x10 0x01 INTB# 0x04 0x11 0x02 INTC# 0x05 0x12 0x03 INTD# 0x07 0x13 0x04 INTE# 0x0B 0x14 0x05 INTF# 0x1F 0x1F 0x06 INTG# 0x1F 0x16 0x07 INTH# 0x1F 0x17 0x08 Misc 0xFA 0x00 0x09 Misc0 0xF1 0x00 0x0A Misc1 0x00 0x00 0x0B Misc2 0x00 0x00 0x0C Ser IRQ INTA 0x1F 0x1F 0x0D Ser IRQ INTB 0x1F 0x1F 0x0E Ser IRQ INTC 0x1F 0x1F 0x0F Ser IRQ INTD 0x1F 0x1F 0x10 SCI 0x09 0x09 0x11 SMBUS 0x1F 0x1F 0x12 ASF 0x1F 0x1F 0x13 HDA 0x03 0x10 0x14 FC 0x1F 0x1F 0x16 PerMon 0x1F 0x1F 0x17 SD 0x03 0x10 0x1A SDIOt 0x00 0x1F 0x30 EHCI 0x05 0x12 0x34 XHCI 0x04 0x12 0x41 SATA 0x07 0x13 0x62 GPIO 0x07 0x07 0x70 I2C0 0x03 0x03 0x71 I2C1 0x0F 0x0F 0x72 I2C2 0x06 0x06 0x73 I2C3 0x0E 0x0E 0x74 UART0 0x0A 0x0A 0x75 UART1 0x0B 0x0B PCI_CFG IRQ: Write PCI config space IRQ assignments PCI IRQ: Found device 0:01.00 using PIN A PCI Devfn (0x8) not found in pirq_data table PCI IRQ: Found device 0:01.01 using PIN B Found this device in pirq_data table entry 5 Orig INT_PIN : 2 (PIN B) PCI_INTR idx : 0x13 (HDA) INT_LINE : 0x3 (IRQ 3) PCI IRQ: Found device 0:02.02 using PIN A Found this device in pirq_data table entry 1 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x01 (INTB#) INT_LINE : 0x4 (IRQ 4) PCI IRQ: Found device 0:02.04 using PIN A Found this device in pirq_data table entry 3 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x03 (INTD#) INT_LINE : 0x7 (IRQ 7) PCI IRQ: Found device 0:08.00 using PIN A PCI Devfn (0x40) not found in pirq_data table PCI IRQ: Found device 0:10.00 using PIN A Found this device in pirq_data table entry 10 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x34 (XHCI) INT_LINE : 0x4 (IRQ 4) PCI IRQ: Found device 0:12.00 using PIN A Found this device in pirq_data table entry 9 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x30 (EHCI) INT_LINE : 0x5 (IRQ 5) PCI IRQ: Found device 0:14.07 using PIN A Found this device in pirq_data table entry 6 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x17 (SD) INT_LINE : 0x3 (IRQ 3) PCI IRQ: Found device 2:00.00 using PIN A With INT_PIN swizzled to PIN A Attached to bridge device 0:02h.04h Found this device in pirq_data table entry 3 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x03 (INTD#) INT_LINE : 0x7 (IRQ 7) PCI IRQ: Found device 1:00.00 using PIN A With INT_PIN swizzled to PIN A Attached to bridge device 0:02h.02h Found this device in pirq_data table entry 1 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x01 (INTB#) INT_LINE : 0x4 (IRQ 4) PCI_CFG IRQ: Finished writing PCI config space IRQ assignments POST: 0x74 Enabling resources... agesawrapper_amdinitmid() entry agesawrapper_amdinitmid() returned AGESA_SUCCESS PCI: 00:00.0 subsystem <- 1022/1576 PCI: 00:00.0 cmd <- 04 PCI: 00:01.0 subsystem <- 1002/98e4 PCI: 00:01.0 cmd <- 07 PCI: 00:01.1 subsystem <- 1002/15b3 PCI: 00:01.1 cmd <- 02 PCI: 00:02.0 subsystem <- 1022/157b PCI: 00:02.0 cmd <- 00 PCI: 00:02.2 bridge ctrl <- 0003 PCI: 00:02.2 cmd <- 06 PCI: 00:02.4 bridge ctrl <- 0003 PCI: 00:02.4 cmd <- 06 PCI: 00:03.0 cmd <- 00 PCI: 00:08.0 subsystem <- 1022/1578 PCI: 00:08.0 cmd <- 06 PCI: 00:09.0 subsystem <- 1022/157d PCI: 00:09.0 cmd <- 00 PCI: 00:10.0 subsystem <- 1022/7914 PCI: 00:10.0 cmd <- 02 PCI: 00:12.0 subsystem <- 1022/7908 PCI: 00:12.0 cmd <- 02 PCI: 00:14.0 subsystem <- 1022/790b PCI: 00:14.0 cmd <- 403 PCI: 00:14.3 subsystem <- 1022/790e PCI: 00:14.3 cmd <- 0f Southbridge LPC decode:PNP: 0c09.0, base=0x00000800, end=0x000009fe Covered by wideIO 0 PCI: 00:14.7 subsystem <- 1022/7906 PCI: 00:14.7 cmd <- 06 PCI: 00:18.0 cmd <- 00 PCI: 00:18.1 subsystem <- 1022/15b1 PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 subsystem <- 1022/15b2 PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 subsystem <- 1022/15b3 PCI: 00:18.3 cmd <- 00 PCI: 00:18.4 subsystem <- 1022/15b4 PCI: 00:18.4 cmd <- 00 PCI: 00:18.5 subsystem <- 1022/15b5 PCI: 00:18.5 cmd <- 00 PCI: 01:00.0 cmd <- 02 PCI: 02:00.0 subsystem <- 1217/8620 PCI: 02:00.0 cmd <- 06 done. BS: BS_DEV_ENABLE times (us): entry 279609 run 130735 exit 0 POST: 0x75 Initializing devices... Root Device init ... Root Device init finished in 1950 usecs POST: 0x75 CPU_CLUSTER: 0 init ... MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x00000000d0000000 size 0xcff40000 type 6 0x00000000d0000000 - 0x00000000f0000000 size 0x20000000 type 0 0x00000000f0000000 - 0x00000000f4800000 size 0x04800000 type 1 0x00000000f4800000 - 0x0000000100000000 size 0x0b800000 type 0 0x0000000100000000 - 0x000000012f000000 size 0x2f000000 type 6 MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e call enable_fixed_mtrr() CPU physical address size: 48 bits MTRR: default type WB/UC MTRR counts: 8/6. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000ffff80000000 type 6 MTRR: 1 base 0x0000000080000000 mask 0x0000ffffc0000000 type 6 MTRR: 2 base 0x00000000c0000000 mask 0x0000fffff0000000 type 6 MTRR: 3 base 0x00000000f0000000 mask 0x0000fffffc000000 type 1 MTRR: 4 base 0x00000000f4000000 mask 0x0000ffffff800000 type 1 MTRR: 5 base 0x0000000100000000 mask 0x0000ffffc0000000 type 6 MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Will perform SMM setup. CPU: AMD A4-9120C RADEON R4, 5 COMPUTE CORES 2C+3G . Loading module at 00030000 with entry 00030000. filesize: 0x170 memsize: 0x170 Processing 16 relocs. Offset value of 0x00030000 Attempting to start 1 APs Waiting for 10ms after sending INIT. Waiting for 1st SIPI to complete...AP: slot 1 apic_id 11. done. Waiting for 2nd SIPI to complete...done. Loading module at 00038000 with entry 00038000. filesize: 0x1a8 memsize: 0x1a8 Processing 13 relocs. Offset value of 0x00038000 SMM Module: stub loaded at 00038000. Will call cdeb995b(00000000) Installing SMM handler to 0xce800000 Loading module at ce810000 with entry ce81142b. filesize: 0x6c98 memsize: 0xad18 Processing 481 relocs. Offset value of 0xce810000 Loading module at ce808000 with entry ce808000. filesize: 0x1a8 memsize: 0x1a8 Processing 13 relocs. Offset value of 0xce808000 SMM Module: placing jmp sequence at ce807e00 rel16 0x01fd SMM Module: stub loaded at ce808000. Will call ce81142b(00000000) New SMBASE 0xce800000 Relocation complete. New SMBASE 0xce7ffe00 Relocation complete. Initializing CPU #0 CPU: vendor AMD device 670f00 CPU: family 15, model 70, stepping 00 Setting up local APIC... apic_id: 0x10 done. CPU #0 initialized Initializing CPU #1 CPU: vendor AMD device 670f00 CPU: family 15, model 70, stepping 00 Setting up local APIC... apic_id: 0x11 done. CPU #1 initialized bsp_do_flight_plan done after 91 msecs. MTRR: TEMPORARY Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x00000000d0000000 size 0xcff40000 type 6 0x00000000d0000000 - 0x00000000ff000000 size 0x2f000000 type 0 0x00000000ff000000 - 0x0000000100000000 size 0x01000000 type 5 0x0000000100000000 - 0x000000012f000000 size 0x2f000000 type 6 MTRR: default type WB/UC MTRR counts: 7/5. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000ffff80000000 type 6 MTRR: 1 base 0x0000000080000000 mask 0x0000ffffc0000000 type 6 MTRR: 2 base 0x00000000c0000000 mask 0x0000fffff0000000 type 6 MTRR: 3 base 0x00000000ff000000 mask 0x0000ffffff000000 type 5 MTRR: 4 base 0x0000000100000000 mask 0x0000ffffc0000000 type 6 CPU_CLUSTER: 0 init finished in 346114 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 PCI: 00:00.0 init ... PCI: 00:00.0 init finished in 2003 usecs POST: 0x75 POST: 0x75 PCI: 00:01.0 init ... CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'pci1002,98e4.rom' CBFS: Found @ offset 92c00 size fe00 Mapping PCI device 100298e4 to 100298e0 In CBFS, ROM address for PCI: 00:01.0 = ffe82c48 PCI expansion ROM, signature 0xaa55, INIT size 0xfe00, data ptr 0x01c0 PCI ROM image, vendor ID 1002, device ID 98e0, PCI ROM image, Class Code 030000, Code Type 00 Copying VGA ROM Image from ffe82c48 to 0xc0000, 0xfe00 bytes Real mode stub @00000600: 867 bytes Calling Option ROM... ... Option ROM returned. VBE: Getting information about VESA mode 41d2 VBE: resolution: 1366x768@16 VBE: framebuffer: f0000000 VBE: Setting VESA mode 41d2 VGA Option ROM was run PCI: 00:01.0 init finished in 112291 usecs POST: 0x75 PCI: 00:01.1 init ... PCI: 00:01.1 init finished in 2002 usecs POST: 0x75 PCI: 00:02.0 init ... PCI: 00:02.0 init finished in 2002 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 PCI: 00:03.0 init ... PCI: 00:03.0 init finished in 2002 usecs POST: 0x75 PCI: 00:08.0 init ... PCI: 00:08.0 init finished in 2002 usecs POST: 0x75 PCI: 00:09.0 init ... PCI: 00:09.0 init finished in 2002 usecs POST: 0x75 POST: 0x75 PCI: 00:10.0 init ... PCI: 00:10.0 init finished in 2002 usecs POST: 0x75 POST: 0x75 PCI: 00:12.0 init ... PCI: 00:12.0 init finished in 2002 usecs POST: 0x75 PCI: 00:14.0 init ... IOAPIC: Initializing IOAPIC at 0xfec00000 IOAPIC: Bootstrap Processor Local APIC = 0x10 IOAPIC: ID = 0x04 IOAPIC: Dumping registers reg 0x0000: 0x04000000 reg 0x0001: 0x00178021 reg 0x0002: 0x04000000 IOAPIC: 24 interrupts IOAPIC: Enabling interrupts on FSB IOAPIC: reg 0x00000000 value 0x10000000 0x00000700 IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 IOAPIC: reg 0x00000017 value 0x00000000 0x00010000 PCI: 00:14.0 init finished in 133953 usecs POST: 0x75 PCI: 00:14.3 init ... RTC Init PCI: 00:14.3 init finished in 2962 usecs POST: 0x75 PCI: 00:14.7 init ... PCI: 00:14.7 init finished in 2002 usecs POST: 0x75 PCI: 00:18.0 init ... IOAPIC: Initializing IOAPIC at 0xfec20000 IOAPIC: Bootstrap Processor Local APIC = 0x10 IOAPIC: ID = 0x05 IOAPIC: Dumping registers reg 0x0000: 0x05000000 reg 0x0001: 0x001f8021 reg 0x0002: 0x00000000 IOAPIC: 32 interrupts IOAPIC: Enabling interrupts on FSB IOAPIC: reg 0x00000000 value 0x10000000 0x00000700 IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 IOAPIC: reg 0x00000017 value 0x00000000 0x00010000 IOAPIC: reg 0x00000018 value 0x00000000 0x00010000 IOAPIC: reg 0x00000019 value 0x00000000 0x00010000 IOAPIC: reg 0x0000001a value 0x00000000 0x00010000 IOAPIC: reg 0x0000001b value 0x00000000 0x00010000 IOAPIC: reg 0x0000001c value 0x00000000 0x00010000 IOAPIC: reg 0x0000001d value 0x00000000 0x00010000 IOAPIC: reg 0x0000001e value 0x00000000 0x00010000 IOAPIC: reg 0x0000001f value 0x00000000 0x00010000 PCI: 00:18.0 init finished in 170055 usecs POST: 0x75 PCI: 00:18.1 init ... PCI: 00:18.1 init finished in 2002 usecs POST: 0x75 PCI: 00:18.2 init ... PCI: 00:18.2 init finished in 2002 usecs POST: 0x75 PCI: 00:18.3 init ... PCI: 00:18.3 init finished in 2002 usecs POST: 0x75 PCI: 00:18.4 init ... PCI: 00:18.4 init finished in 2002 usecs POST: 0x75 PCI: 00:18.5 init ... PCI: 00:18.5 init finished in 2002 usecs POST: 0x75 PCI: 01:00.0 init ... PCI: 01:00.0 init finished in 2002 usecs POST: 0x75 PCI: 02:00.0 init ... BayHub BH720: Power-saving enabled (link_ctrl=0x110103) PCI: 02:00.0 init finished in 7128 usecs POST: 0x75 PNP: 0c09.0 init ... Google Chrome EC: Hello got back 11223344 status (0) Google Chrome EC: version: ro: careena_v2.0.11488-7215d6e0e4 rw: careena_v2.0.11488-7215d6e0e4 running image: 1 Google Chrome EC uptime: 5.573 seconds Google Chrome AP resets since EC boot: 0 Google Chrome most recent AP reset causes: Google Chrome EC reset flags at last EC boot: reset-pin PNP: 0c09.0 init finished in 34471 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 Devices initialized Show all devs... After init. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 DOMAIN: 0000: enabled 1 MMIO: fedc2000: enabled 1 MMIO: fedc3000: enabled 1 MMIO: fedc4000: enabled 1 MMIO: fedc5000: enabled 1 APIC: 10: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.2: enabled 0 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 0 PCI: 00:02.2: enabled 1 PCI: 00:02.3: enabled 0 PCI: 00:02.4: enabled 1 PCI: 00:02.5: enabled 0 PCI: 00:08.0: enabled 1 PCI: 00:09.0: enabled 1 PCI: 00:09.2: enabled 0 PCI: 00:10.0: enabled 1 PCI: 00:11.0: enabled 0 PCI: 00:12.0: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:14.3: enabled 1 PCI: 00:14.7: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 GENERIC: 0.0: enabled 1 I2C: 01:1a: enabled 1 GENERIC: 0.1: enabled 1 I2C: 02:50: enabled 1 I2C: 03:15: enabled 1 I2C: 04:39: enabled 1 I2C: 04:10: enabled 1 PCI: 02:00.0: enabled 1 PNP: 0c09.0: enabled 1 PCI: 00:03.0: enabled 1 PCI: 01:00.0: enabled 1 APIC: 11: enabled 1 BS: BS_DEV_INIT times (us): entry 0 run 1076516 exit 151 ELOG: Event(A1) added with size 10 at 2023-08-09 04:53:14 UTC elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b ELOG: Event(A0) added with size 9 at 2023-08-09 04:53:14 UTC elog_add_boot_reason: Logged dev mode boot POST: 0x76 Finalize devices... Devices finalized FMAP: area RW_NVRAM found @ 467000 (20480 bytes) agesawrapper_amdinitlate() entry DmiTable:cdfbd4a3, AcpiPstatein: cdfbc2b9, AcpiSrat:00000000,AcpiSlit:00000000, Mce:cdfbd327, Cmc:cdfbd3e9,Alib:cdfbe586, AcpiIvrs:00000000 in agesawrapper_amdinitlate agesawrapper_amdinitlate() returned AGESA_SUCCESS agesawrapper_amdinitrtb() entry agesawrapper_amdinitrtb() returned AGESA_SUCCESS BS: BS_POST_DEVICE times (us): entry 22178 run 4546 exit 37850 FMAP: area RW_MRC_CACHE found @ 0 (65536 bytes) MRC: Checking cached data update for 'RW_MRC_CACHE'. MRC: cache data 'RW_MRC_CACHE' needs update. ELOG: Event(AA) added with size 11 at 2023-08-09 04:53:14 UTC POST: 0x77 BS: BS_OS_RESUME_CHECK times (us): entry 29669 run 1061 exit 0 POST: 0x79 POST: 0x9c CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'fallback/dsdt.aml' CBFS: Found @ offset a6cc0 size 3b94 CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'fallback/slic' CBFS: 'fallback/slic' not found. ACPI: Writing ACPI tables at cde2e000. ACPI: * FACS ACPI: * DSDT Ramoops buffer: 0x100000@0xcdd2e000. ACPI: * FADT pm_base: 0x0400 ACPI: added table 1/32, length now 40 ACPI: * SSDT ACPI \_PR report 2 core(s) dw_i2c: bad counts. hcnt = -1 lcnt = 9 dw_i2c: bad counts. hcnt = -1 lcnt = 13 dw_i2c: bad counts. hcnt = -13 lcnt = 11 dw_i2c: bad counts. hcnt = -7 lcnt = 16 CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'pci1002,98e4.rom' CBFS: Found @ offset 92c00 size fe00 Mapping PCI device 100298e4 to 100298e0 In CBFS, ROM address for PCI: 00:01.0 = ffe82c48 PCI expansion ROM, signature 0xaa55, INIT size 0xfe00, data ptr 0x01c0 PCI ROM image, vendor ID 1002, device ID 98e0, PCI ROM image, Class Code 030000, Code Type 00 \_SB.I2CA.ADAU: Analog Digital DMIC \_SB.I2CA.DLG7: Dialog Semiconductor DA7219 Audio Codec address 01ah irq 0 \_SB.I2CA.MAXM: Maxim Integrated 98357A Amplifier \_SB.I2CB.TPMI: I2C TPM at I2C: 02:50 \_SB.I2CC.D015: ELAN Touchpad at I2C: 03:15 \_SB.I2CD.D039: Raydium Touchscreen at I2C: 04:39 \_SB.I2CD.D010: ELAN Touchscreen at I2C: 04:10 ACPI: added table 2/32, length now 44 ACPI: * MCFG ACPI: added table 3/32, length now 48 ACPI: * TCPA TCPA log created at cdd0e000 ACPI: added table 4/32, length now 52 ACPI: * MADT ACPI: added table 5/32, length now 56 current = cde32e10 CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'pci1002,98e4.rom' CBFS: Found @ offset 92c00 size fe00 Mapping PCI device 100298e4 to 100298e0 In CBFS, ROM address for PCI: 00:01.0 = ffe82c48 PCI expansion ROM, signature 0xaa55, INIT size 0xfe00, data ptr 0x01c0 PCI ROM image, vendor ID 1002, device ID 98e0, PCI ROM image, Class Code 030000, Code Type 00 ACPI: * VFCT at cde32e10 Copying initialized VBIOS image from 000c0000 ACPI: added table 6/32, length now 60 ACPI: * HPET ACPI: added table 7/32, length now 64 ACPI: added table 8/32, length now 68 ACPI: * IVRS at cde42e90 AGESA IVRS table NULL. Skipping. ACPI: * SRAT at cde42e90 AGESA SRAT table NULL. Skipping. ACPI: * SLIT at cde42e90 AGESA SLIT table NULL. Skipping. ACPI: * AGESA ALIB SSDT at cde42e90 ACPI: added table 9/32, length now 72 ACPI: * SSDT at cde479f0 ACPI: added table 10/32, length now 76 ACPI: * SSDT for PState at cde47e2c ACPI: done. ACPI tables: 106032 bytes. smbios_write_tables: cdd0d000 Create SMBIOS type 17 SMBIOS tables: 539 bytes. Writing table forward entry at 0x00000500 Wrote coreboot table at: 00000500, 0x10 bytes, checksum 11f9 Writing coreboot table at 0xcde52000 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000a0000-00000000000fffff: RESERVED 3. 0000000000100000-00000000cdd0cfff: RAM 4. 00000000cdd0d000-00000000cde9efff: CONFIGURATION TABLES 5. 00000000cde9f000-00000000cdfa0fff: RAMSTAGE 6. 00000000cdfa1000-00000000cdffffff: CONFIGURATION TABLES 7. 00000000ce000000-00000000cfffffff: RESERVED 8. 00000000f8000000-00000000fbffffff: RESERVED 9. 0000000100000000-000000012effffff: RAM Passing 5 GPIOs to payload: NAME | PORT | POLARITY | VALUE write protect | undefined | high | high recovery | undefined | high | low lid | undefined | high | high power | undefined | high | low EC in RW | 0x0000000f | high | low Board ID: 6 SKU ID: 33 CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) Wrote coreboot table at: cde52000, 0x538 bytes, checksum 6ac3 coreboot table: 1360 bytes. IMD ROOT 0. cdfff000 00001000 IMD SMALL 1. cdffe000 00001000 CONSOLE 2. cdfde000 00020000 TIME STAMP 3. cdfdd000 00000910 VBOOT 4. cdfdc000 00000c0c ACPISCRATCH 5. cdfac000 00030000 ROMSTG STCK 6. cdfab000 00000400 AFTER CAR 7. cdfa1000 0000a000 RAMSTAGE 8. cde9e000 00103000 REFCODE 9. cde6c000 00032000 ACPI GNVS 10. cde6b000 00001000 SMM BACKUP 11. cde5b000 00010000 MRC DATA 12. cde5a000 00000e75 COREBOOT 13. cde52000 00008000 ACPI 14. cde2e000 00024000 RAMOOPS 15. cdd2e000 00100000 VGA ROM #0 16. cdd1e000 0000fe00 TCPA TCGLOG17. cdd0e000 00010000 SMBIOS 18. cdd0d000 00000800 IMD small region: IMD ROOT 0. cdffec00 00000400 VBOOT SEL 1. cdffebe0 00000008 EC HOSTEVENT 2. cdffebc0 00000008 ROMSTAGE 3. cdffeba0 00000004 VPD 4. cdffeb20 0000006c POWER STATE 5. cdffeb00 00000010 MEM INFO 6. cdffe9a0 00000149 COREBOOTFWD 7. cdffe960 00000028 BS: BS_WRITE_TABLES times (us): entry 2 run 438404 exit 1 POST: 0x7a CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'fallback/payload' CBFS: Found @ offset 1ae180 size 39f90 Loading segment from ROM address 0xfff9e1b8 code (compression=0) New segment dstaddr 0x30104020 memsize 0x254890 srcaddr 0xfff9e1f0 filesize 0x39f58 Loading segment from ROM address 0xfff9e1d4 Entry Point 0x30104020 Loading Segment: addr: 0x0000000030104020 memsz: 0x0000000000254890 filesz: 0x0000000000039f58 lb: [0x00000000cde9f000, 0x00000000cdfa09d8) Post relocation: addr: 0x0000000030104020 memsz: 0x0000000000254890 filesz: 0x0000000000039f58 it's not compressed! [ 0x30104020, 3013df78, 0x303588b0) <- fff9e1f0 Clearing Segment: addr: 0x000000003013df78 memsz: 0x000000000021a938 dest 30104020, end 303588b0, bouncebuffer ffffffff Loaded segments Lock SMM configuration POST: 0xfe BS: BS_PAYLOAD_LOAD times (us): entry 230 run 92765 exit 3307 PSP: Notify that POST is finishing... OK POST: 0x7b mp_park_aps done after 0 msecs. Jumping to boot code at 30104020(cde52000) POST: 0xf8 CPU0: stack: cdeda000 - cdedb000, lowest used address cdeda558, stack used: 2728 bytes Starting depthcharge on grunt... WARNING: can't convert coreboot GPIOs, 'lid' won't be resampled at runtime! WARNING: can't convert coreboot GPIOs, 'power' won't be resampled at runtime! The GBB signature is at 0x30004020 and is: 24 47 42 42 [firmware-grunt-11031.B-collabora] Dec 11 2020 09:59:28 grunt: tftpboot 192.168.201.1 11241467/tftp-deploy-40pygwua/kernel/bzImage 11241467/tftp-deploy-40pygwua/kernel/cmdline 11241467/tftp-deploy-40pygwua/ramdisk/ramdisk.cpio.gz tftpboot 192.168.201.1 11241467/tftp-deploy-40pygwua/kernel/bzImagewua/kernel/cmdline 11241467/tftp-deploy-40pygwua/ramdisk/ramdisk.cpio.gz Waiting for link R8152: Initializing Version 9 (ocp_data = 6010) R8152: Done initializing Adding net device R8152: Initializing Version 9 (ocp_data = 6010) R8152: Done initializing net_add_device: Attemp to include the same device done. MAC: 00:e0:4c:78:7f:44 Sending DHCP discover... done. Waiting for reply... done. Sending DHCP request... done. Waiting for reply... done. My ip is 192.168.201.12 The DHCP server ip is 192.168.201.1 TFTP server IP predefined by user: 192.168.201.1 Bootfile predefined by user: 11241467/tftp-deploy-40pygwua/kernel/bzImage Sending tftp read request... done. Waiting for the transfer... 00000000 ################################################################ 00080000 ################################################################ 00100000 ################################################################ 00180000 ################################################################ 00200000 ################################################################ 00280000 ################################################################ 00300000 ################################################################ 00380000 ################################################################ 00400000 ################################################################ 00480000 ################################################################ 00500000 ################################################################ 00580000 ################################################################ 00600000 ################################################################ 00680000 ################################################################ 00700000 ################################################################ 00780000 ################################################################ 00800000 ################################################################ 00880000 ################################################################ 00900000 ################################################################ 00980000 ################################################################ 00a00000 ################################################################ 00a80000 ################################################################ 00b00000 ################################################################ 00b80000 ################################################################ 00c00000 ################################################################ 00c80000 ##################################### done. The bootfile was 13407008 bytes long. Sending tftp read request... done. Waiting for the transfer... 00000000 ################################################################ 00080000 ################################################################ 00100000 ################################################################ 00180000 ################################################################ 00200000 ################################################################ 00280000 ################################################################ 00300000 ################################################################ 00380000 ################################################################ 00400000 ################################################################ 00480000 ################################################################ 00500000 ################################################################ 00580000 ################################################################ 00600000 ################################################################ 00680000 ################################################################ 00700000 ################################################################ 00780000 ################################################################ 00800000 ################################################################ 00880000 ################################################################ 00900000 ################################################################ 00980000 ################################################################ 00a00000 ################################################################ 00a80000 ################################################################ 00b00000 ################################################################ 00b80000 ################################################################ 00c00000 ################################################################ 00c80000 ################################################################ 00d00000 ################################################################ 00d80000 ################################################################ 00e00000 ################################################################ 00e80000 ################################################################ 00f00000 ################################################################ 00f80000 ################################################################ 01000000 ################################################################ 01080000 ################################################################ 01100000 ################################################################ 01180000 ################################################################ 01200000 ################################################################ 01280000 ################################################################ 01300000 ################################################################ 01380000 ################################################################ 01400000 ################################################################ 01480000 ################################################################ 01500000 ################################################################ 01580000 ################################################################ 01600000 ################################################################ 01680000 ################################################################ 01700000 ################################################################ 01780000 ################################################################ 01800000 ################################################################ 01880000 ################################################################ 01900000 ################################################################ 01980000 ################################################################ 01a00000 ################################################################ 01a80000 ################################################################ 01b00000 ################################################################ 01b80000 ################################################################ 01c00000 ################################################################ 01c80000 ################################################################ 01d00000 ################################################################ 01d80000 ################################################################ 01e00000 ################################################################ 01e80000 ################################################################ 01f00000 ################################################################ 01f80000 ################################################################ 02000000 ################################################################ 02080000 ################################################################ 02100000 ################################################################ 02180000 ################################################################ 02200000 ################################################################ 02280000 ################################################################ 02300000 ################################################################ 02380000 ################################################################ 02400000 ################################################################ 02480000 ################################################################ 02500000 ################################################################ 02580000 ################################################################ 02600000 ################################################################ 02680000 ################################################################ 02700000 ################################################################ 02780000 ################################################################ 02800000 ################################################################ 02880000 ################################################################ 02900000 ################################################################ 02980000 ################################################################ 02a00000 ################################################################ 02a80000 ################################################################ 02b00000 ################################################################ 02b80000 ################################################################ 02c00000 ################################################################ 02c80000 ################################################################ 02d00000 ################################################################ 02d80000 ################################################################ 02e00000 ################################################################ 02e80000 ################################################################ 02f00000 ################################################################ 02f80000 ################################################################ 03000000 ################################################################ 03080000 ################################################################ 03100000 ################################################################ 03180000 ################################################################ 03200000 ################################################################ 03280000 ################################################################ 03300000 ################################################################ 03380000 ################################################################ 03400000 ################################################################ 03480000 ################################################################ 03500000 ################################################################ 03580000 ################################################################ 03600000 ################################################################ 03680000 ################################################################ 03700000 ################################################################ 03780000 ################################################################ 03800000 ################################################################ 03880000 ################################################################ 03900000 ################################################################ 03980000 ################################################################ 03a00000 ################################################################ 03a80000 ################################################################ 03b00000 ################################################################ 03b80000 ################################################################ 03c00000 ################################################################ 03c80000 ################################################################ 03d00000 ################################################################ 03d80000 ################################################################ 03e00000 ################################################################ 03e80000 ################################################################ 03f00000 ################################################################ 03f80000 ################################################################ 04000000 ################################################################ 04080000 ################################################################ 04100000 ################################################################ 04180000 ################################################################ 04200000 ################################################################ 04280000 ################################################################ 04300000 ################################################################ 04380000 ################################################################ 04400000 ################################################################ 04480000 ################################################################ 04500000 ################################################################ 04580000 ################################################################ 04600000 ################################################################ 04680000 ################################################################ 04700000 ################################################################ 04780000 ################################################################ 04800000 ################################################################ 04880000 ################################################################ 04900000 ################################################################ 04980000 ################################################################ 04a00000 ################################################################ 04a80000 ################################################################ 04b00000 ################################################################ 04b80000 ################################################################ 04c00000 ################################################################ 04c80000 ################################################################ 04d00000 ################################################################ 04d80000 ################################################################ 04e00000 ################################################################ 04e80000 ################################################################ 04f00000 ################################################################ 04f80000 ################################################################ 05000000 ################################################################ 05080000 ################################################################ 05100000 ################################################################ 05180000 ################################################################ 05200000 ################################################################ 05280000 ################################################################ 05300000 ################################################################ 05380000 ################################################################ 05400000 ################################################################ 05480000 ################################################################ 05500000 ################################################################ 05580000 ################################################################ 05600000 ################################################################ 05680000 ################################################################ 05700000 ################################################################ 05780000 ################################################################ 05800000 ################## done. Sending tftp read request... done. Waiting for the transfer... 00000000 # done. Command line loaded dynamically from TFTP file: 11241467/tftp-deploy-40pygwua/kernel/cmdline The command line is: earlyprintk=uart8250,mmio32,0xfedc6000,115200n8 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1 Shutting down all USB controllers. Removing current net device Finalizing coreboot coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 smm starting... SMI# #0 Exiting depthcharge with code 4 at timestamp: 62159278 Starting kernel ... coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 smm starting... SMI# #0 Chrome EC: Set SMI mask to 0x0000000000000000 Chrome EC: UHEPI supported Clearing pending EC events. Error code 1 is expected. EC returned error result code 9 Chrome EC: Set SCI mask to 0x00000000142609fb <5>[ 0.000000] Linux version 5.10.186-cip37 (KernelCI@build-j7192-x86-64-gcc-10-x86-64-defconfig-x86-chromebook-nmfv8) (gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP Wed Aug 9 04:27:38 UTC 2023 <6>[ 0.000000] Command line: earlyprintk=uart8250,mmio32,0xfedc6000,115200n8 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1 <6>[ 0.000000] x86/fpu: Supporting XSAVE feature 0x001: 'x87 floating point registers' <6>[ 0.000000] x86/fpu: Supporting XSAVE feature 0x002: 'SSE registers' <6>[ 0.000000] x86/fpu: Supporting XSAVE feature 0x004: 'AVX registers' <6>[ 0.000000] x86/fpu: xstate_offset[2]: 576, xstate_sizes[2]: 256 <6>[ 0.000000] x86/fpu: Enabled xstate features 0x7, context size is 832 bytes, using 'standard' format. <6>[ 0.000000] BIOS-provided physical RAM map: <6>[ 0.000000] BIOS-e820: [mem 0x0000000000000000-0x0000000000000fff] type 16 <6>[ 0.000000] BIOS-e820: [mem 0x0000000000001000-0x000000000009ffff] usable <6>[ 0.000000] BIOS-e820: [mem 0x00000000000a0000-0x00000000000fffff] reserved <6>[ 0.000000] BIOS-e820: [mem 0x0000000000100000-0x00000000cdd0cfff] usable <6>[ 0.000000] BIOS-e820: [mem 0x00000000cdd0d000-0x00000000cdffffff] type 16 <6>[ 0.000000] BIOS-e820: [mem 0x00000000ce000000-0x00000000cfffffff] reserved <6>[ 0.000000] BIOS-e820: [mem 0x00000000f8000000-0x00000000fbffffff] reserved <6>[ 0.000000] BIOS-e820: [mem 0x0000000100000000-0x000000012effffff] usable <6>[ 0.000000] NX (Execute Disable) protection: active <6>[ 0.000000] SMBIOS 2.7 present. <6>[ 0.000000] DMI: Google Grunt/Grunt, BIOS 09/05/2019 <6>[ 0.000000] tsc: Fast TSC calibration using PIT <6>[ 0.000000] tsc: Detected 1596.961 MHz processor <6>[ 0.000890] last_pfn = 0x12f000 max_arch_pfn = 0x400000000 <6>[ 0.001186] x86/PAT: Configuration [0-7]: WB WC UC- UC WB WP UC- WT <6>[ 0.001451] last_pfn = 0xcdd0d max_arch_pfn = 0x400000000 <6>[ 0.007494] check: Scanning 1 areas for low memory corruption <6>[ 0.007502] Using GB pages for direct mapping <6>[ 0.007677] RAMDISK: [mem 0x327dc000-0x37ffffff] <6>[ 0.007682] ACPI: Early table checksum verification disabled <6>[ 0.007687] ACPI: RSDP 0x00000000000F0000 000024 (v02 COREv4) <6>[ 0.007693] ACPI: XSDT 0x00000000CDE2E0E0 000074 (v01 COREv4 COREBOOT 00000000 CORE 00000000) <6>[ 0.007701] ACPI: FACP 0x00000000CDE31E60 0000F4 (v04 COREv4 COREBOOT 00000000 CORE 00000000) <6>[ 0.007708] ACPI: DSDT 0x00000000CDE2E280 003BE0 (v02 COREv4 COREBOOT 00010001 INTL 20180531) <6>[ 0.007713] ACPI: FACS 0x00000000CDE2E240 000040 <6>[ 0.007717] ACPI: SSDT 0x00000000CDE31F60 000DB5 (v02 COREv4 COREBOOT 0000002A CORE 0000002A) <6>[ 0.007722] ACPI: MCFG 0x00000000CDE32D20 00003C (v01 COREv4 COREBOOT 00000000 CORE 00000000) <6>[ 0.007726] ACPI: TCPA 0x00000000CDE32D60 000032 (v02 COREv4 COREBOOT 00000000 CORE 00000000) <6>[ 0.007730] ACPI: APIC 0x00000000CDE32DA0 00006E (v02 COREv4 COREBOOT 00000000 CORE 00000000) <6>[ 0.007734] ACPI: VFCT 0x00000000CDE32E10 00FE69 (v01 COREv4 COREBOOT 00000000 CORE 00000000) <6>[ 0.007738] ACPI: HPET 0x00000000CDE42C80 000038 (v01 COREv4 COREBOOT 00000000 CORE 00000000) <6>[ 0.007742] ACPI: HEST 0x00000000CDE42CC0 0001D0 (v01 COREv4 COREBOOT 00000000 CORE 00000000) <6>[ 0.007746] ACPI: SSDT 0x00000000CDE42E90 004B5B (v02 AMD AGESA 00000002 MSFT 04000000) <6>[ 0.007750] ACPI: SSDT 0x00000000CDE479F0 00043C (v01 AMD AGESA 00000001 AMD 00000001) <6>[ 0.007754] ACPI: Reserving FACP table memory at [mem 0xcde31e60-0xcde31f53] <6>[ 0.007756] ACPI: Reserving DSDT table memory at [mem 0xcde2e280-0xcde31e5f] <6>[ 0.007758] ACPI: Reserving FACS table memory at [mem 0xcde2e240-0xcde2e27f] <6>[ 0.007760] ACPI: Reserving SSDT table memory at [mem 0xcde31f60-0xcde32d14] <6>[ 0.007761] ACPI: Reserving MCFG table memory at [mem 0xcde32d20-0xcde32d5b] <6>[ 0.007763] ACPI: Reserving TCPA table memory at [mem 0xcde32d60-0xcde32d91] <6>[ 0.007764] ACPI: Reserving APIC table memory at [mem 0xcde32da0-0xcde32e0d] <6>[ 0.007766] ACPI: Reserving VFCT table memory at [mem 0xcde32e10-0xcde42c78] <6>[ 0.007768] ACPI: Reserving HPET table memory at [mem 0xcde42c80-0xcde42cb7] <6>[ 0.007769] ACPI: Reserving HEST table memory at [mem 0xcde42cc0-0xcde42e8f] <6>[ 0.007771] ACPI: Reserving SSDT table memory at [mem 0xcde42e90-0xcde479ea] <6>[ 0.007772] ACPI: Reserving SSDT table memory at [mem 0xcde479f0-0xcde47e2b] <6>[ 0.007833] No NUMA configuration found <6>[ 0.007835] Faking a node at [mem 0x0000000000000000-0x000000012effffff] <6>[ 0.007841] NODE_DATA(0) allocated [mem 0x12effa000-0x12effdfff] <6>[ 0.007866] Zone ranges: <6>[ 0.007868] DMA [mem 0x0000000000001000-0x0000000000ffffff] <6>[ 0.007870] DMA32 [mem 0x0000000001000000-0x00000000ffffffff] <6>[ 0.007872] Normal [mem 0x0000000100000000-0x000000012effffff] <6>[ 0.007874] Movable zone start for each node <6>[ 0.007876] Early memory node ranges <6>[ 0.007877] node 0: [mem 0x0000000000001000-0x000000000009ffff] <6>[ 0.007879] node 0: [mem 0x0000000000100000-0x00000000cdd0cfff] <6>[ 0.007881] node 0: [mem 0x0000000100000000-0x000000012effffff] <6>[ 0.007884] Initmem setup node 0 [mem 0x0000000000001000-0x000000012effffff] <6>[ 0.007898] On node 0, zone DMA: 1 pages in unavailable ranges <6>[ 0.007932] On node 0, zone DMA: 96 pages in unavailable ranges <6>[ 0.023861] On node 0, zone Normal: 8947 pages in unavailable ranges <6>[ 0.023931] On node 0, zone Normal: 4096 pages in unavailable ranges <6>[ 0.023994] ACPI: PM-Timer IO Port: 0x418 <6>[ 0.024004] ACPI: LAPIC_NMI (acpi_id[0xff] high edge lint[0x1]) <6>[ 0.024013] IOAPIC[0]: apic_id 4, version 33, address 0xfec00000, GSI 0-23 <6>[ 0.024017] IOAPIC[1]: apic_id 5, version 33, address 0xfec20000, GSI 24-55 <6>[ 0.024020] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl) <6>[ 0.024022] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 low level) <6>[ 0.024028] Using ACPI (MADT) for SMP configuration information <6>[ 0.024030] ACPI: HPET id: 0x10228201 base: 0xfed00000 <6>[ 0.024035] smpboot: Allowing 2 CPUs, 0 hotplug CPUs <6>[ 0.024049] PM: hibernation: Registered nosave memory: [mem 0x00000000-0x00000fff] <6>[ 0.024052] PM: hibernation: Registered nosave memory: [mem 0x000a0000-0x000fffff] <6>[ 0.024055] PM: hibernation: Registered nosave memory: [mem 0xcdd0d000-0xcdffffff] <6>[ 0.024056] PM: hibernation: Registered nosave memory: [mem 0xce000000-0xcfffffff] <6>[ 0.024058] PM: hibernation: Registered nosave memory: [mem 0xd0000000-0xf7ffffff] <6>[ 0.024059] PM: hibernation: Registered nosave memory: [mem 0xf8000000-0xfbffffff] <6>[ 0.024060] PM: hibernation: Registered nosave memory: [mem 0xfc000000-0xffffffff] <6>[ 0.024063] [mem 0xd0000000-0xf7ffffff] available for PCI devices <6>[ 0.024067] clocksource: refined-jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 1910969940391419 ns <6>[ 0.031401] setup_percpu: NR_CPUS:64 nr_cpumask_bits:64 nr_cpu_ids:2 nr_node_ids:1 <6>[ 0.031931] percpu: Embedded 56 pages/cpu s189848 r8192 d31336 u1048576 <6>[ 0.031964] Built 1 zonelists, mobility grouping on. Total pages: 1019233 <6>[ 0.031967] Policy zone: Normal <5>[ 0.031970] Kernel command line: earlyprintk=uart8250,mmio32,0xfedc6000,115200n8 console_msg_format=syslog earlycon deferred_probe_timeout=60 console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1 <6>[ 0.033037] Dentry cache hash table entries: 524288 (order: 10, 4194304 bytes, linear) <6>[ 0.033517] Inode-cache hash table entries: 262144 (order: 9, 2097152 bytes, linear) <6>[ 0.033544] mem auto-init: stack:off, heap alloc:off, heap free:off <6>[ 0.067091] Memory: 3872008K/4141744K available (18446K kernel code, 2735K rwdata, 8136K rodata, 1592K init, 2172K bss, 269476K reserved, 0K cma-reserved) <6>[ 0.067145] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1 <6>[ 0.067263] rcu: Hierarchical RCU implementation. <6>[ 0.067266] rcu: RCU event tracing is enabled. <6>[ 0.067268] rcu: RCU restricting CPUs from NR_CPUS=64 to nr_cpu_ids=2. <6>[ 0.067271] rcu: RCU calculated value of scheduler-enlistment delay is 100 jiffies. <6>[ 0.067273] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2 <6>[ 0.068295] NR_IRQS: 4352, nr_irqs: 512, preallocated irqs: 16 <5>[ 0.068525] random: crng init done <6>[ 0.068565] Console: colour dummy device 80x25 <6>[ 0.094152] printk: console [ttyS0] enabled <6>[ 0.094318] ACPI: Core revision 20200925 <6>[ 0.094588] clocksource: hpet: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 133484873504 ns <6>[ 0.094917] APIC: Switch to symmetric I/O mode setup <6>[ 0.095430] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=0 pin2=0 <6>[ 0.099918] clocksource: tsc-early: mask: 0xffffffffffffffff max_cycles: 0x1704ee2e775, max_idle_ns: 440795247995 ns <6>[ 0.100281] Calibrating delay loop (skipped), value calculated using timer frequency.. 3193.92 BogoMIPS (lpj=1596961) <6>[ 0.100645] pid_max: default: 32768 minimum: 301 <6>[ 0.100832] LSM: Security Framework initializing <6>[ 0.101287] SELinux: Initializing. <6>[ 0.101456] Mount-cache hash table entries: 8192 (order: 4, 65536 bytes, linear) <6>[ 0.101729] Mountpoint-cache hash table entries: 8192 (order: 4, 65536 bytes, linear) <6>[ 0.102322] BIOS may not properly restore RDRAND after suspend, hiding RDRAND via CPUID. Use rdrand=force to reenable. <6>[ 0.102742] LVT offset 1 assigned for vector 0xf9 <6>[ 0.102919] Last level iTLB entries: 4KB 512, 2MB 1024, 4MB 512 <6>[ 0.103127] Last level dTLB entries: 4KB 1024, 2MB 1024, 4MB 512, 1GB 0 <6>[ 0.103282] Spectre V1 : Mitigation: usercopy/swapgs barriers and __user pointer sanitization <6>[ 0.103577] Spectre V2 : Mitigation: Retpolines <6>[ 0.103739] Spectre V2 : Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch <6>[ 0.104023] Spectre V2 : Spectre v2 / SpectreRSB : Filling RSB on VMEXIT <6>[ 0.104278] Spectre V2 : Enabling Speculation Barrier for firmware calls <6>[ 0.104511] RETBleed: Mitigation: untrained return thunk <6>[ 0.104701] Spectre V2 : mitigation: Enabling conditional Indirect Branch Prediction Barrier <6>[ 0.104992] Speculative Store Bypass: Mitigation: Speculative Store Bypass disabled via prctl and seccomp <6>[ 0.115678] Freeing SMP alternatives memory: 44K <6>[ 0.117348] smpboot: CPU 0 Converting physical 2 to logical die 0 <6>[ 0.219575] smpboot: CPU0: AMD A4-9120C RADEON R4, 5 COMPUTE CORES 2C+3G (family: 0x15, model: 0x70, stepping: 0x0) <6>[ 0.220064] Performance Events: Fam15h core perfctr, AMD PMU driver. <6>[ 0.220276] ... version: 0 <6>[ 0.220276] ... bit width: 48 <6>[ 0.220278] ... generic registers: 6 <6>[ 0.220424] ... value mask: 0000ffffffffffff <6>[ 0.220612] ... max period: 00007fffffffffff <6>[ 0.220800] ... fixed-purpose events: 0 <6>[ 0.220946] ... event mask: 000000000000003f <6>[ 0.221234] rcu: Hierarchical SRCU implementation. <6>[ 0.221570] smp: Bringing up secondary CPUs ... <6>[ 0.221842] x86: Booting SMP configuration: <6>[ 0.221994] .... node #0, CPUs: #1 <6>[ 0.223307] smp: Brought up 1 node, 2 CPUs <6>[ 0.223599] smpboot: Max logical packages: 1 <6>[ 0.223753] smpboot: Total of 2 processors activated (6387.84 BogoMIPS) <6>[ 0.224640] devtmpfs: initialized <6>[ 0.224640] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 1911260446275000 ns <6>[ 0.225285] futex hash table entries: 512 (order: 3, 32768 bytes, linear) <6>[ 0.225552] pinctrl core: initialized pinctrl subsystem <6>[ 0.225865] PM: RTC time: 04:54:12, date: 2023-08-09 <6>[ 0.226386] NET: Registered protocol family 16 <6>[ 0.226663] audit: initializing netlink subsys (disabled) <5>[ 0.226865] audit: type=2000 audit(1691556852.131:1): state=initialized audit_enabled=0 res=1 <6>[ 0.226865] thermal_sys: Registered thermal governor 'step_wise' <6>[ 0.226865] thermal_sys: Registered thermal governor 'user_space' <6>[ 0.227295] cpuidle: using governor menu <6>[ 0.227718] ACPI: bus type PCI registered <6>[ 0.227718] PCI: MMCONFIG for domain 0000 [bus 00-40] at [mem 0xf8000000-0xfc0fffff] (base 0xf8000000) <6>[ 0.228282] PCI: MMCONFIG at [mem 0xf8000000-0xfc0fffff] reserved in E820 <6>[ 0.228520] PCI: MMCONFIG for 0000 [bus00-1f] at [mem 0xf8000000-0xf9ffffff] (base 0xf8000000) (size reduced!) <6>[ 0.228876] PCI: Using configuration type 1 for base access <6>[ 0.234151] Kprobes globally optimized <6>[ 0.234308] HugeTLB registered 2.00 MiB page size, pre-allocated 0 pages <6>[ 0.234539] cryptomgr_test (26) used greatest stack depth: 15672 bytes left <6>[ 0.234544] cryptomgr_test (27) used greatest stack depth: 15512 bytes left <6>[ 0.235349] ACPI: Added _OSI(Module Device) <6>[ 0.235502] ACPI: Added _OSI(Processor Device) <6>[ 0.235662] ACPI: Added _OSI(3.0 _SCP Extensions) <6>[ 0.236303] ACPI: Added _OSI(Processor Aggregator Device) <6>[ 0.236525] ACPI: Added _OSI(Linux-Dell-Video) <6>[ 0.236685] ACPI: Added _OSI(Linux-Lenovo-NV-HDMI-Audio) <6>[ 0.236874] ACPI: Added _OSI(Linux-HPI-Hybrid-Graphics) <6>[ 0.242204] ACPI: 4 ACPI AML tables successfully acquired and loaded <6>[ 0.244902] ACPI: EC: EC started <6>[ 0.245023] ACPI: EC: interrupt blocked <6>[ 0.245248] ACPI: EC: EC_CMD/EC_SC=0x66, EC_DATA=0x62 <6>[ 0.245280] ACPI: \_SB_.PCI0.LPCB.EC0_: Boot DSDT EC used to handle transactions <6>[ 0.245537] ACPI: Interpreter enabled <6>[ 0.245690] ACPI: (supports S0 S1 S3 S4 S5) <6>[ 0.245843] ACPI: Using IOAPIC for interrupt routing <6>[ 0.246034] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug <6>[ 0.246463] ACPI: Enabled 3 GPEs in block 00 to 1F <6>[ 0.247421] ACPI: Power Resource [P0U2] (off) <6>[ 0.247610] ACPI: Power Resource [P3U2] (off) <6>[ 0.248102] ACPI: Power Resource [P0U3] (off) <6>[ 0.248294] ACPI: Power Resource [P3U3] (off) <6>[ 0.250709] ACPI: Power Resource [PRIC] (on) <6>[ 0.275541] ACPI: Power Resource [PRIC] (on) <6>[ 0.302648] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff]) <6>[ 0.302874] acpi PNP0A08:00: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI HPX-Type3] <6>[ 0.303226] acpi PNP0A08:00: _OSC: OS now controls [PME PCIeCapability LTR] <6>[ 0.303289] acpi PNP0A08:00: [Firmware Info]: MMCONFIG for domain 0000 [bus 00-1f] only partially covers this bridge <6>[ 0.303684] acpi PNP0A08:00: host bridge window expanded to [io 0x0000-0x0cf7 window]; [io 0x03b0-0x03df window] ignored <6>[ 0.304285] PCI host bridge to bus 0000:00 <6>[ 0.304436] pci_bus 0000:00: root bus resource [io 0x0000-0x0cf7 window] <6>[ 0.304673] pci_bus 0000:00: root bus resource [io 0x0d00-0xffff window] <6>[ 0.304910] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff] <6>[ 0.305149] pci_bus 0000:00: root bus resource [mem 0x000c0000-0x000dffff] <6>[ 0.305279] pci_bus 0000:00: root bus resource [mem 0xd0000000-0xffffffff] <6>[ 0.305519] pci_bus 0000:00: root bus resource [bus 00-ff] <6>[ 0.305726] pci 0000:00:00.0: [1022:1576] type 00 class 0x060000 <6>[ 0.306060] pci 0000:00:01.0: [1002:98e4] type 00 class 0x030000 <6>[ 0.306291] pci 0000:00:01.0: reg 0x10: [mem 0xf0000000-0xf3ffffff 64bit pref] <6>[ 0.306549] pci 0000:00:01.0: reg 0x18: [mem 0xf4000000-0xf47fffff 64bit pref] <6>[ 0.306804] pci 0000:00:01.0: reg 0x20: [io 0x1000-0x10ff] <6>[ 0.307006] pci 0000:00:01.0: reg 0x24: [mem 0xf4d00000-0xf4d3ffff] <6>[ 0.307283] pci 0000:00:01.0: reg 0x30: [mem 0xf4d40000-0xf4d5ffff pref] <6>[ 0.307522] pci 0000:00:01.0: enabling Extended Tags <6>[ 0.307740] pci 0000:00:01.0: supports D1 D2 <6>[ 0.307895] pci 0000:00:01.0: PME# supported from D1 D2 D3hot <6>[ 0.308196] pci 0000:00:01.1: [1002:15b3] type 00 class 0x040300 <6>[ 0.308289] pci 0000:00:01.1: reg 0x10: [mem 0xf4d80000-0xf4d83fff 64bit] <6>[ 0.308551] pci 0000:00:01.1: enabling Extended Tags <6>[ 0.308759] pci 0000:00:01.1: supports D1 D2 <6>[ 0.308984] pci 0000:00:02.0: [1022:157b] type 00 class 0x060000 <6>[ 0.309361] pci 0000:00:02.2: [1022:157c] type 01 class 0x060400 <6>[ 0.309607] pci 0000:00:02.2: enabling Extended Tags <6>[ 0.309830] pci 0000:00:02.2: PME# supported from D0 D3hot D3cold <6>[ 0.310145] pci 0000:00:02.4: [1022:157c] type 01 class 0x060400 <6>[ 0.310313] pci 0000:00:02.4: enabling Extended Tags <6>[ 0.310534] pci 0000:00:02.4: PME# supported from D0 D3hot D3cold <6>[ 0.310845] pci 0000:00:03.0: [1022:157b] type 00 class 0x060000 <6>[ 0.311332] pci 0000:00:08.0: [1022:1578] type 00 class 0x108000 <6>[ 0.311553] pci 0000:00:08.0: reg 0x10: [mem 0xf4d60000-0xf4d7ffff 64bit pref] <6>[ 0.311808] pci 0000:00:08.0: reg 0x18: [mem 0xf4b00000-0xf4bfffff] <6>[ 0.312031] pci 0000:00:08.0: reg 0x1c: [mem 0xf4d88000-0xf4d88fff] <6>[ 0.312255] pci 0000:00:08.0: reg 0x20: [mem 0xf4c00000-0xf4cfffff] <6>[ 0.312282] pci 0000:00:08.0: reg 0x24: [mem 0xf4d84000-0xf4d85fff] <6>[ 0.312583] pci 0000:00:09.0: [1022:157d] type 00 class 0x060000 <6>[ 0.312894] pci 0000:00:10.0: [1022:7914] type 00 class 0x0c0330 <6>[ 0.313300] pci 0000:00:10.0: reg 0x10: [mem 0xf4d86000-0xf4d87fff 64bit] <6>[ 0.313646] pci 0000:00:10.0: PME# supported from D0 D3hot D3cold <6>[ 0.313968] pci 0000:00:12.0: [1022:7908] type 00 class 0x0c0320 <6>[ 0.314193] pci 0000:00:12.0: reg 0x10: [mem 0xf4d89000-0xf4d890ff] <6>[ 0.314352] pci 0000:00:12.0: supports D1 D2 <6>[ 0.314507] pci 0000:00:12.0: PME# supported from D0 D1 D2 D3hot D3cold <6>[ 0.314821] pci 0000:00:14.0: [1022:790b] type 00 class 0x0c0500 <6>[ 0.315331] pci 0000:00:14.3: [1022:790e] type 00 class 0x060100 <6>[ 0.315687] pci 0000:00:14.7: [1022:7906] type 00 class 0x080501 <6>[ 0.315916] pci 0000:00:14.7: reg 0x10: [mem 0xf4d8a000-0xf4d8a0ff 64bit] <6>[ 0.316221] pci 0000:00:14.7: PME# supported from D3cold <6>[ 0.316361] pci 0000:00:18.0: [1022:15b0] type 00 class 0x060000 <6>[ 0.316639] pci 0000:00:18.1: [1022:15b1] type 00 class 0x060000 <6>[ 0.316915] pci 0000:00:18.2: [1022:15b2] type 00 class 0x060000 <6>[ 0.317334] pci 0000:00:18.3: [1022:15b3] type 00 class 0x060000 <6>[ 0.317613] pci 0000:00:18.4: [1022:15b4] type 00 class 0x060000 <6>[ 0.317888] pci 0000:00:18.5: [1022:15b5] type 00 class 0x060000 <6>[ 0.318290] pci 0000:01:00.0: [168c:003e] type 00 class 0x028000 <6>[ 0.318582] pci 0000:01:00.0: reg 0x10: [mem 0xf4800000-0xf49fffff 64bit] <6>[ 0.319004] pci 0000:01:00.0: PME# supported from D0 D3hot D3cold <6>[ 0.319432] pci 0000:00:02.2: PCI bridge to [bus 01] <6>[ 0.319615] pci 0000:00:02.2: bridge window [mem 0xf4800000-0xf49fffff] <6>[ 0.320000] pci 0000:02:00.0: [1217:8620] type 00 class 0x080501 <6>[ 0.320295] pci 0000:02:00.0: reg 0x10: [mem 0xf4a00000-0xf4a00fff] <6>[ 0.320607] pci 0000:02:00.0: reg 0x14: [mem 0xf4a01000-0xf4a017ff] <6>[ 0.321029] pci 0000:02:00.0: PME# supported from D3hot D3cold <6>[ 0.324483] pci 0000:00:02.4: PCI bridge to [bus 02] <6>[ 0.324673] pci 0000:00:02.4: bridge window [mem 0xf4a00000-0xf4afffff] <6>[ 0.325651] ACPI: PCI Interrupt Link [INTA] (IRQs *3 4 5 7 10 11 12 15) <6>[ 0.325928] ACPI: PCI Interrupt Link [INTB] (IRQs 3 *4 5 7 10 11 12 15) <6>[ 0.326202] ACPI: PCI Interrupt Link [INTC] (IRQs 3 4 *5 7 10 11 12 15) <6>[ 0.326318] ACPI: PCI Interrupt Link [INTD] (IRQs 3 4 5 *7 10 11 12 15) <6>[ 0.326591] ACPI: PCI Interrupt Link [INTE] (IRQs 3 4 5 7 10 *11 12 15) <6>[ 0.326864] ACPI: PCI Interrupt Link [INTF] (IRQs 9) *0 <6>[ 0.327088] ACPI: PCI Interrupt Link [INTG] (IRQs 3 4 5 7 10 11 12 15) *0 <6>[ 0.327316] ACPI: PCI Interrupt Link [INTH] (IRQs 3 4 5 7 10 11 12 15) *0 <6>[ 0.329766] ACPI: EC: interrupt unblocked <6>[ 0.329912] ACPI: EC: event unblocked <6>[ 0.330051] ACPI: EC: EC_CMD/EC_SC=0x66, EC_DATA=0x62 <6>[ 0.330231] ACPI: EC: GPE=0x3 <6>[ 0.330280] ACPI: \_SB_.PCI0.LPCB.EC0_: Boot DSDT EC initialization complete <6>[ 0.330526] ACPI: \_SB_.PCI0.LPCB.EC0_: EC: Used to handle transactions and events <6>[ 0.330874] iommu: Default domain type: Translated <6>[ 0.330874] pci 0000:00:01.0: vgaarb: setting as boot VGA device <6>[ 0.330874] pci 0000:00:01.0: vgaarb: VGA device added: decodes=io+mem,owns=io+mem,locks=none <6>[ 0.331285] pci 0000:00:01.0: vgaarb: bridge control possible <6>[ 0.331487] vgaarb: loaded <5>[ 0.331673] SCSI subsystem initialized <6>[ 0.332334] ACPI: bus type USB registered <6>[ 0.332498] usbcore: registered new interface driver usbfs <6>[ 0.332701] usbcore: registered new interface driver hub <6>[ 0.332896] usbcore: registered new device driver usb <6>[ 0.344373] mc: Linux media interface: v0.10 <6>[ 0.344548] videodev: Linux video capture interface: v2.00 <6>[ 0.344752] pps_core: LinuxPPS API ver. 1 registered <6>[ 0.345283] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <6>[ 0.345599] PTP clock support registered <6>[ 0.345770] Advanced Linux Sound Architecture Driver Initialized. <6>[ 0.345770] NetLabel: Initializing <6>[ 0.345831] NetLabel: domain hash size = 128 <6>[ 0.346278] NetLabel: protocols = UNLABELED CIPSOv4 CALIPSO <6>[ 0.346495] NetLabel: unlabeled traffic allowed by default <6>[ 0.346709] PCI: Using ACPI for IRQ routing <6>[ 0.348174] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0 <6>[ 0.348279] hpet0: 3 comparators, 32-bit 14.318180 MHz counter <6>[ 0.351301] clocksource: Switched to clocksource tsc-early <5>[ 0.573780] VFS: Disk quotas dquot_6.6.0 <6>[ 0.573946] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes) <6>[ 0.574263] pnp: PnP ACPI init <6>[ 0.574558] system 00:00: [mem 0xfec1000a-0xfec11009] has been reserved <6>[ 0.574919] system 00:03: [io 0x0900-0x09fe] has been reserved <6>[ 0.575181] system 00:04: [io 0x0200] has been reserved <6>[ 0.575370] system 00:04: [io 0x0204] has been reserved <6>[ 0.575559] system 00:04: [io 0x0800-0x087f] has been reserved <6>[ 0.575768] system 00:04: [io 0x0880-0x08ff] has been reserved <6>[ 0.576947] pnp: PnP ACPI: found 6 devices <6>[ 0.583402] clocksource: acpi_pm: mask: 0xffffff max_cycles: 0xffffff, max_idle_ns: 2085701024 ns <6>[ 0.583741] NET: Registered protocol family 2 <6>[ 0.584040] IP idents hash table entries: 65536 (order: 7, 524288 bytes, linear) <6>[ 0.584941] tcp_listen_portaddr_hash hash table entries: 2048 (order: 3, 32768 bytes, linear) <6>[ 0.585265] TCP established hash table entries: 32768 (order: 6, 262144 bytes, linear) <6>[ 0.585622] TCP bind hash table entries: 32768 (order: 7, 524288 bytes, linear) <6>[ 0.586012] TCP: Hash tables configured (established 32768 bind 32768) <6>[ 0.586303] UDP hash table entries: 2048 (order: 4, 65536 bytes, linear) <6>[ 0.586556] UDP-Lite hash table entries: 2048 (order: 4, 65536 bytes, linear) <6>[ 0.586876] NET: Registered protocol family 1 <6>[ 0.587207] RPC: Registered named UNIX socket transport module. <6>[ 0.587417] RPC: Registered udp transport module. <6>[ 0.587586] RPC: Registered tcp transport module. <6>[ 0.587754] RPC: Registered tcp NFSv4.1 backchannel transport module. <6>[ 0.588220] pci 0000:00:02.2: PCI bridge to [bus 01] <6>[ 0.588404] pci 0000:00:02.2: bridge window [mem 0xf4800000-0xf49fffff] <6>[ 0.588646] pci 0000:00:02.4: PCI bridge to [bus 02] <6>[ 0.588825] pci 0000:00:02.4: bridge window [mem 0xf4a00000-0xf4afffff] <6>[ 0.589073] pci_bus 0000:00: resource 4 [io 0x0000-0x0cf7 window] <6>[ 0.589291] pci_bus 0000:00: resource 5 [io 0x0d00-0xffff window] <6>[ 0.589508] pci_bus 0000:00: resource 6 [mem 0x000a0000-0x000bffff] <6>[ 0.589728] pci_bus 0000:00: resource 7 [mem 0x000c0000-0x000dffff] <6>[ 0.589950] pci_bus 0000:00: resource 8 [mem 0xd0000000-0xffffffff] <6>[ 0.590170] pci_bus 0000:01: resource 1 [mem 0xf4800000-0xf49fffff] <6>[ 0.590391] pci_bus 0000:02: resource 1 [mem 0xf4a00000-0xf4afffff] <6>[ 0.590655] pci 0000:00:01.0: disabling ATS <6>[ 0.590811] pci 0000:00:01.0: Video device with shadowed ROM at [mem 0x000c0000-0x000dffff] <6>[ 0.591126] pci 0000:00:01.1: D0 power state depends on 0000:00:01.0 <6>[ 0.591577] pci 0000:00:10.0: PME# does not work under D0, disabling it <6>[ 0.592080] PCI: CLS 64 bytes, default 64 <6>[ 0.592284] Unpacking initramfs... <6>[ 2.385653] Freeing initrd memory: 90256K <6>[ 2.385816] PCI-DMA: Using software bounce buffering for IO (SWIOTLB) <6>[ 2.386044] software IO TLB: mapped [mem 0x00000000c9d0d000-0x00000000cdd0d000] (64MB) <6>[ 2.386387] LVT offset 0 assigned for vector 0x400 <6>[ 2.386591] perf: AMD IBS detected (0x000007ff) <6>[ 2.387046] check: Scanning for low memory corruption every 60 seconds <5>[ 2.387627] Initialise system trusted keyrings <6>[ 2.387876] workingset: timestamp_bits=56 max_order=20 bucket_order=0 <5>[ 2.390094] NFS: Registering the id_resolver key type <5>[ 2.390281] Key type id_resolver registered <5>[ 2.390433] Key type id_legacy registered <5>[ 2.405399] Key type asymmetric registered <5>[ 2.405550] Asymmetric key parser 'x509' registered <6>[ 2.405736] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 248) <6>[ 2.405997] io scheduler mq-deadline registered <6>[ 2.406161] io scheduler kyber registered <6>[ 2.407117] pcieport 0000:00:02.2: PME: Signaling with IRQ 25 <6>[ 2.407479] pcieport 0000:00:02.4: PME: Signaling with IRQ 26 <6>[ 2.407935] ACPI: AC Adapter [AC] (on-line) <6>[ 2.408153] input: Lid Switch as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/device:17/PNP0C09:00/PNP0C0D:00/input/input0 <6>[ 2.408570] ACPI: Lid Switch [LID0] <6>[ 2.408744] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input1 <6>[ 2.409034] ACPI: Power Button [PWRF] <6>[ 2.409220] ACPI: Video Device [IGFX] (multi-head: no rom: yes post: no) <6>[ 2.409542] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input2 <6>[ 2.409899] ACPI: \_PR_.P000: Found 2 idle states <6>[ 2.410160] ACPI: \_PR_.P001: Found 2 idle states <6>[ 2.410910] thermal LNXTHERM:00: registered as thermal_zone0 <6>[ 2.411111] ACPI: Thermal Zone [THRM] (45 C) <6>[ 2.411417] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled <6>[ 2.411970] battery: ACPI: Battery Slot [BAT0] (battery present) <6>[ 2.412186] printk: console [ttyS0] disabled <6>[ 2.412357] AMD0020:00: ttyS0 at MMIO 0xfedc6000 (irq = 10, base_baud = 3000000) is a 16550A <6>[ 3.393708] tsc: Refined TSC clocksource calibration: 1597.002 MHz <6>[ 3.393713] clocksource: tsc: mask: 0xffffffffffffffff max_cycles: 0x170514dcf86, max_idle_ns: 440795282824 ns <6>[ 3.393726] clocksource: Switched to clocksource tsc <6>[ 4.828580] printk: console [ttyS0] enabled <6>[ 4.833207] AMD0020:01: ttyS1 at MMIO 0xfedc8000 (irq = 11, base_baud = 3000000) is a 16550A <6>[ 4.842069] Non-volatile memory driver v1.3 <6>[ 4.846537] Linux agpgart interface v0.103 <6>[ 4.850978] [drm] amdgpu kernel modesetting enabled. <6>[ 4.856210] amdgpu 0000:00:01.0: vgaarb: deactivate vga console <6>[ 4.862520] [drm] initializing kernel modesetting (STONEY 0x1002:0x98E4 0x1002:0x1EB0 0xEB). <4>[ 4.871208] amdgpu 0000:00:01.0: amdgpu: Trusted Memory Zone (TMZ) feature not supported <6>[ 4.879582] [drm] register mmio base: 0xF4D00000 <6>[ 4.884454] [drm] register mmio size: 262144 <6>[ 4.888985] [drm] add ip block number 0 <6>[ 4.894116] [drm] add ip block number 1 <6>[ 4.899158] [drm] add ip block number 2 <6>[ 4.903943] [drm] add ip block number 3 <6>[ 4.908986] [drm] add ip block number 4 <6>[ 4.914117] [drm] add ip block number 5 <6>[ 4.919248] [drm] add ip block number 6 <6>[ 4.923772] [drm] add ip block number 7 <6>[ 4.928819] [drm] add ip block number 8 <6>[ 4.933862] [drm] add ip block number 9 <6>[ 4.938760] amdgpu 0000:00:01.0: amdgpu: Fetched VBIOS from VFCT <6>[ 4.945019] amdgpu: ATOM BIOS: 113-C91400-010 <6>[ 4.949646] [drm] UVD is enabled in physical mode <6>[ 4.954605] [drm] VCE enabled in VM mode <6>[ 4.958811] [drm] vm size is 64 GB, 2 levels, block size is 10-bit, fragment size is 9-bit <6>[ 4.967325] amdgpu 0000:00:01.0: amdgpu: VRAM: 16M 0x000000F400000000 - 0x000000F400FFFFFF (16M used) <6>[ 4.976791] amdgpu 0000:00:01.0: amdgpu: GART: 1024M 0x000000FF00000000 - 0x000000FF3FFFFFFF <6>[ 4.985479] [drm] Detected VRAM RAM=16M, BAR=16M <6>[ 4.990349] [drm] RAM width 64bits UNKNOWN <6>[ 4.994773] [TTM] Zone kernel: Available graphics memory: 1981284 KiB <6>[ 5.001557] [TTM] Initializing pool allocator <6>[ 5.006181] [TTM] Initializing DMA pool allocator <6>[ 5.011175] [drm] amdgpu: 16M of VRAM memory ready <6>[ 5.016221] [drm] amdgpu: 2902M of GTT memory ready. <6>[ 5.021441] [drm] GART: num cpu pages 262144, num gpu pages 262144 <6>[ 5.027905] [drm] PCIE GART of 1024M enabled (table at 0x000000F400401000). <6>[ 5.036185] amdgpu: hwmgr_sw_init smu backed is smu8_smu <6>[ 5.041766] [drm] Found UVD firmware Version: 1.43 Family ID: 15 <6>[ 5.048026] [drm] UVD ENC is disabled <6>[ 5.052241] [drm] Found VCE firmware Version: 52.0 Binary ID: 3 <6>[ 5.059300] amdgpu: smu version 33.09.00 <6>[ 5.071091] [drm] DM_PPLIB: values for Engine clock <6>[ 5.076227] [drm] DM_PPLIB: 200000 <6>[ 5.079971] [drm] DM_PPLIB: 300000 <6>[ 5.083714] [drm] DM_PPLIB: 400000 <6>[ 5.087457] [drm] DM_PPLIB: 450000 <6>[ 5.091201] [drm] DM_PPLIB: 496560 <6>[ 5.094944] [drm] DM_PPLIB: 533340 <6>[ 5.098689] [drm] DM_PPLIB: 576000 <6>[ 5.102432] [drm] DM_PPLIB: 600000 <6>[ 5.106178] [drm] DM_PPLIB: Validation clocks: <6>[ 5.110876] [drm] DM_PPLIB: engine_max_clock: 60000 <6>[ 5.116267] [drm] DM_PPLIB: memory_max_clock: 93300 <6>[ 5.121656] [drm] DM_PPLIB: level : 8 <6>[ 5.126700] [drm] DM_PPLIB: values for Display clock <6>[ 5.131918] [drm] DM_PPLIB: 300000 <6>[ 5.135660] [drm] DM_PPLIB: 400000 <6>[ 5.139404] [drm] DM_PPLIB: 496560 <6>[ 5.143148] [drm] DM_PPLIB: 626090 <6>[ 5.146892] [drm] DM_PPLIB: 685720 <6>[ 5.150635] [drm] DM_PPLIB: 757900 <6>[ 5.154377] [drm] DM_PPLIB: 800000 <6>[ 5.158121] [drm] DM_PPLIB: 847060 <6>[ 5.161863] [drm] DM_PPLIB: Validation clocks: <6>[ 5.166560] [drm] DM_PPLIB: engine_max_clock: 60000 <6>[ 5.171951] [drm] DM_PPLIB: memory_max_clock: 93300 <6>[ 5.177342] [drm] DM_PPLIB: level : 8 <6>[ 5.182385] [drm] DM_PPLIB: values for Memory clock <6>[ 5.187515] [drm] DM_PPLIB: 667000 <6>[ 5.191258] [drm] DM_PPLIB: 933000 <6>[ 5.195001] [drm] DM_PPLIB: Validation clocks: <6>[ 5.199698] [drm] DM_PPLIB: engine_max_clock: 60000 <6>[ 5.205089] [drm] DM_PPLIB: memory_max_clock: 93300 <6>[ 5.210480] [drm] DM_PPLIB: level : 8 <6>[ 5.215619] [drm] Display Core initialized with v3.2.104! <6>[ 5.324322] [drm] UVD initialized successfully. <6>[ 5.430437] [drm] VCE initialized successfully. <6>[ 5.435350] amdgpu 0000:00:01.0: amdgpu: SE 1, SH per SE 1, CU per SH 3, active_cu_number 3 <6>[ 5.444369] [drm] fb mappable at 0xCF86F000 <6>[ 5.448811] [drm] vram apper at 0xCF000000 <6>[ 5.453161] [drm] size 1179648 <6>[ 5.456472] [drm] fb depth is 8 <6>[ 5.459869] [drm] pitch is 1536 <6>[ 5.463592] fbcon: amdgpudrmfb (fb0) is primary device <6>[ 5.464855] Console: switching to colour frame buffer device 170x48 <6>[ 5.478024] amdgpu 0000:00:01.0: [drm] fb0: amdgpudrmfb frame buffer device <6>[ 5.487184] [drm] Initialized amdgpu 3.40.0 20150101 for 0000:00:01.0 on minor 0 <6>[ 5.497181] loop: module loaded <6>[ 5.501060] e100: Intel(R) PRO/100 Network Driver <6>[ 5.506020] e100: Copyright(c) 1999-2006 Intel Corporation <6>[ 5.511772] e1000: Intel(R) PRO/1000 Network Driver <6>[ 5.516902] e1000: Copyright (c) 1999-2006 Intel Corporation. <6>[ 5.522915] e1000e: Intel(R) PRO/1000 Network Driver <6>[ 5.528132] e1000e: Copyright(c) 1999 - 2015 Intel Corporation. <6>[ 5.534320] sky2: driver version 1.30 <6>[ 5.538295] usbcore: registered new interface driver r8152 <6>[ 5.544107] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver <6>[ 5.550885] ehci-pci: EHCI PCI platform driver <6>[ 5.555740] ehci-pci 0000:00:12.0: EHCI Host Controller <6>[ 5.561270] ehci-pci 0000:00:12.0: new USB bus registered, assigned bus number 1 <6>[ 5.568930] ehci-pci 0000:00:12.0: debug port 2 <6>[ 5.573755] ehci-pci 0000:00:12.0: irq 18, io mem 0xf4d89000 <6>[ 5.585985] ehci-pci 0000:00:12.0: USB 2.0 started, EHCI 1.00 <6>[ 5.592051] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 5.10 <6>[ 5.600566] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1 <6>[ 5.608044] usb usb1: Product: EHCI Host Controller <6>[ 5.613177] usb usb1: Manufacturer: Linux 5.10.186-cip37 ehci_hcd <6>[ 5.619519] usb usb1: SerialNumber: 0000:00:12.0 <6>[ 5.624560] hub 1-0:1.0: USB hub found <6>[ 5.628571] hub 1-0:1.0: 2 ports detected <6>[ 5.633005] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver <6>[ 5.639442] ohci-pci: OHCI PCI platform driver <6>[ 5.644156] uhci_hcd: USB Universal Host Controller Interface driver <6>[ 5.650886] xhci_hcd 0000:00:10.0: xHCI Host Controller <6>[ 5.656436] xhci_hcd 0000:00:10.0: new USB bus registered, assigned bus number 2 <6>[ 5.664263] xhci_hcd 0000:00:10.0: hcc params 0x014040c3 hci version 0x100 quirks 0x0000000000000410 <6>[ 5.673915] xhci_hcd 0000:00:10.0: xHCI Host Controller <6>[ 5.679438] xhci_hcd 0000:00:10.0: new USB bus registered, assigned bus number 3 <6>[ 5.687086] xhci_hcd 0000:00:10.0: Host supports USB 3.0 SuperSpeed <6>[ 5.693638] usb usb2: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 5.10 <6>[ 5.702150] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1 <6>[ 5.709622] usb usb2: Product: xHCI Host Controller <6>[ 5.714756] usb usb2: Manufacturer: Linux 5.10.186-cip37 xhci-hcd <6>[ 5.721100] usb usb2: SerialNumber: 0000:00:10.0 <6>[ 5.726077] hub 2-0:1.0: USB hub found <6>[ 5.730093] hub 2-0:1.0: 4 ports detected <6>[ 5.734495] usb usb3: We don't know the algorithms for LPM for this host, disabling LPM. <6>[ 5.742854] usb usb3: New USB device found, idVendor=1d6b, idProduct=0003, bcdDevice= 5.10 <6>[ 5.751365] usb usb3: New USB device strings: Mfr=3, Product=2, SerialNumber=1 <6>[ 5.758837] usb usb3: Product: xHCI Host Controller <6>[ 5.763971] usb usb3: Manufacturer: Linux 5.10.186-cip37 xhci-hcd <6>[ 5.770316] usb usb3: SerialNumber: 0000:00:10.0 <6>[ 5.775307] hub 3-0:1.0: USB hub found <6>[ 5.779327] hub 3-0:1.0: 4 ports detected <6>[ 5.783763] usbcore: registered new interface driver usblp <6>[ 5.789522] usbcore: registered new interface driver usb-storage <6>[ 5.795808] udc-core: couldn't find an available UDC - added [g_ether] to list of pending drivers <6>[ 5.804964] i8042: PNP: PS/2 Controller [PNP0303:PS2K] at 0x60,0x64 irq 1 <4>[ 5.812003] i8042: PNP: PS/2 appears to have AUX port disabled, if this is incorrect please boot with i8042.nopnp <4>[ 5.823607] i8042: Warning: Keylock active <6>[ 5.828097] serio: i8042 KBD port at 0x60,0x64 irq 1 <6>[ 5.833511] rtc_cmos 00:01: RTC can wake from S4 <6>[ 5.838601] rtc_cmos 00:01: registered as rtc0 <6>[ 5.843342] rtc_cmos 00:01: alarms up to one day, 114 bytes nvram, hpet irqs <6>[ 5.850781] device-mapper: ioctl: 4.43.0-ioctl (2020-10-01) initialised: dm-devel@redhat.com <6>[ 5.859500] sdhci: Secure Digital Host Controller Interface driver <6>[ 5.865935] sdhci: Copyright(c) Pierre Ossman <6>[ 5.870573] sdhci-pci 0000:00:14.7: SDHCI controller found [1022:7906] (rev 1) <6>[ 5.870599] input: AT Translated Set 2 keyboard as /devices/platform/i8042/serio0/input/input3 <6>[ 5.888976] usb 1-1: new high-speed USB device number 2 using ehci-pci <6>[ 5.988755] mmc0: SDHCI controller on PCI [0000:00:14.7] using ADMA 64-bit <6>[ 5.995960] sdhci-pci 0000:02:00.0: SDHCI controller found [1217:8620] (rev 1) <6>[ 6.003706] mmc1: emmc 1.8v flag is set, force 1.8v signaling voltage <6>[ 6.003798] usb 2-1: new high-speed USB device number 2 using xhci_hcd <6>[ 6.011764] mmc1: SDHCI controller on PCI [0000:02:00.0] using ADMA <6>[ 6.024019] hid: raw HID events driver (C) Jiri Kosina <6>[ 6.029593] usbcore: registered new interface driver usbhid <6>[ 6.032375] usb 1-1: New USB device found, idVendor=0438, idProduct=7900, bcdDevice= 0.18 <6>[ 6.035421] usbhid: USB HID core driver <6>[ 6.043844] usb 1-1: New USB device strings: Mfr=0, Product=0, SerialNumber=0 <6>[ 6.044154] hub 1-1:1.0: USB hub found <6>[ 6.051146] cros_ec_lpcs GOOG0004:00: Chrome EC device registered <6>[ 6.055868] hub 1-1:1.0: 4 ports detected <6>[ 6.061302] snd_hda_intel 0000:00:01.1: Force to non-snoop mode <6>[ 6.076692] Initializing XFRM netlink socket <6>[ 6.081630] NET: Registered protocol family 10 <6>[ 6.086704] Segment Routing with IPv6 <3>[ 6.090756] snd_hda_intel 0000:00:01.1: Cannot probe codecs, giving up <6>[ 6.097629] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver <6>[ 6.104128] NET: Registered protocol family 17 <5>[ 6.108854] Key type dns_resolver registered <6>[ 6.113380] x86/pm: family 0x15 cpu detected, MSR saving is needed during suspending. <6>[ 6.121653] microcode: CPU0: patch_level=0x06006705 <6>[ 6.126799] microcode: CPU1: patch_level=0x06006705 <6>[ 6.131931] microcode: Microcode Update Driver: v2.2. <6>[ 6.131937] IPI shorthand broadcast: enabled <6>[ 6.141866] sched_clock: Marking stable (6115063712, 26780576)->(6168206260, -26361972) <6>[ 6.150220] registered taskstats version 1 <5>[ 6.154573] Loading compiled-in X.509 certificates <6>[ 6.159946] PM: Magic number: 3:2:919 <6>[ 6.164124] printk: console [netcon0] enabled <6>[ 6.168737] netconsole: network logging started <6>[ 6.173655] acpi_cpufreq: overriding BIOS provided _PSD data <6>[ 6.181530] usb 2-1: New USB device found, idVendor=04b4, idProduct=6502, bcdDevice=50.10 <6>[ 6.189968] usb 2-1: New USB device strings: Mfr=0, Product=0, SerialNumber=0 <6>[ 6.199576] hub 2-1:1.0: USB hub found <6>[ 6.203874] hub 2-1:1.0: 4 ports detected <6>[ 6.325795] usb 2-4: new high-speed USB device number 3 using xhci_hcd <6>[ 6.363789] usb 1-1.1: new high-speed USB device number 3 using ehci-pci <6>[ 6.465750] usb 2-4: New USB device found, idVendor=0bda, idProduct=8153, bcdDevice=31.00 <6>[ 6.474179] usb 2-4: New USB device strings: Mfr=1, Product=2, SerialNumber=6 <6>[ 6.481565] usb 2-4: Product: USB 10/100/1000 LAN <6>[ 6.486531] usb 2-4: Manufacturer: Realtek <6>[ 6.490883] usb 2-4: SerialNumber: 001000001 <6>[ 6.501933] usb 1-1.1: New USB device found, idVendor=05c8, idProduct=03d1, bcdDevice= 1.03 <6>[ 6.510533] usb 1-1.1: New USB device strings: Mfr=3, Product=1, SerialNumber=2 <6>[ 6.518095] usb 1-1.1: Product: HP TrueVision HD Camera <6>[ 6.523581] usb 1-1.1: Manufacturer: Foxlink <6>[ 6.528109] usb 1-1.1: SerialNumber: 0x0001 <6>[ 6.548787] usb 2-1.1: new high-speed USB device number 4 using xhci_hcd <6>[ 6.610788] usb 1-1.2: new full-speed USB device number 4 using ehci-pci <6>[ 6.638751] usb 2-1.1: New USB device found, idVendor=0bda, idProduct=8153, bcdDevice=31.00 <6>[ 6.647352] usb 2-1.1: New USB device strings: Mfr=1, Product=2, SerialNumber=6 <6>[ 6.654916] usb 2-1.1: Product: USB 10/100/1000 LAN <6>[ 6.660058] usb 2-1.1: Manufacturer: Realtek <6>[ 6.664584] usb 2-1.1: SerialNumber: 001000001 <6>[ 6.739532] usb 1-1.2: New USB device found, idVendor=0cf3, idProduct=e300, bcdDevice= 0.01 <6>[ 6.748133] usb 1-1.2: New USB device strings: Mfr=0, Product=0, SerialNumber=0 <6>[ 6.756441] usb 2-4: reset high-speed USB device number 3 using xhci_hcd <6>[ 6.956790] usb 2-1.4: new full-speed USB device number 5 using xhci_hcd <6>[ 6.991628] r8152 2-4:1.0: load rtl8153b-2 v2 04/27/23 successfully <6>[ 7.046775] usb 2-1.4: New USB device found, idVendor=03eb, idProduct=2042, bcdDevice= 0.01 <6>[ 7.055388] usb 2-1.4: New USB device strings: Mfr=1, Product=2, SerialNumber=0 <6>[ 7.062951] usb 2-1.4: Product: LUFA Keyboard Emulator <6>[ 7.068345] usb 2-1.4: Manufacturer: Google Servo <6>[ 7.076189] r8152 2-4:1.0 eth0: v1.11.11 <6>[ 7.090811] input: Google Servo LUFA Keyboard Emulator as /devices/pci0000:00/0000:00:10.0/usb2/2-1/2-1.4/2-1.4:1.0/0003:03EB:2042.0001/input/input4 <6>[ 7.126624] usb 2-1.1: reset high-speed USB device number 4 using xhci_hcd <6>[ 7.156070] hid-generic 0003:03EB:2042.0001: input,hidraw0: USB HID v1.11 Keyboard [Google Servo LUFA Keyboard Emulator] on usb-0000:00:10.0-1.4/input0 <6>[ 7.291207] mmc1: new HS200 MMC card at address 0001 <6>[ 7.296708] mmcblk1: mmc1:0001 DF4016 14.7 GiB <6>[ 7.301614] mmcblk1boot0: mmc1:0001 DF4016 partition 1 4.00 MiB <6>[ 7.307920] mmcblk1boot1: mmc1:0001 DF4016 partition 2 4.00 MiB <6>[ 7.314189] mmcblk1rpmb: mmc1:0001 DF4016 partition 3 4.00 MiB, chardev (245:0) <6>[ 7.329453] mmcblk1: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 <6>[ 7.335880] r8152 2-1.1:1.0: load rtl8153b-2 v2 04/27/23 successfully <6>[ 7.407665] r8152 2-1.1:1.0 eth1: v1.11.11 <6>[ 8.670997] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready <6>[ 8.671386] r8152 2-4:1.0 eth0: carrier on <5>[ 8.682934] Sending DHCP requests .., OK <6>[ 11.209172] IP-Config: Got DHCP answer from 192.168.201.1, my address is 192.168.201.12 <6>[ 11.217426] IP-Config: Complete: <6>[ 11.220914] device=eth0, hwaddr=00:e0:4c:78:7f:44, ipaddr=192.168.201.12, mask=255.255.255.0, gw=192.168.201.1 <6>[ 11.231592] host=hp-11a-g6-ee-grunt-cbg-7, domain=lava-rack, nis-domain=(none) <6>[ 11.239496] bootserver=192.168.201.1, rootserver=192.168.201.1, rootpath= <6>[ 11.239497] nameserver0=192.168.201.1 <5>[ 11.291082] cfg80211: Loading compiled-in X.509 certificates for regulatory database <6>[ 11.301280] modprobe (92) used greatest stack depth: 14736 bytes left <6>[ 11.307984] modprobe (93) used greatest stack depth: 14408 bytes left <5>[ 11.308414] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7' <4>[ 11.321509] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2 <6>[ 11.330379] ALSA device list: <6>[ 11.333621] No soundcards found. <6>[ 11.337302] cfg80211: failed to load regulatory.db <4>[ 11.342422] dw-apb-uart AMD0020:00: forbid DMA for kernel console <6>[ 11.349352] Freeing unused kernel image (initmem) memory: 1592K <6>[ 11.358964] Write protecting the kernel read-only data: 28672k <6>[ 11.365807] Freeing unused kernel image (text/rodata gap) memory: 2032K <6>[ 11.372718] Freeing unused kernel image (rodata/data gap) memory: 56K <6>[ 11.379440] Run /init as init process SELinux: Could not open policy file <= /etc/selinux/targeted/policy/policy.33: No such file or directory <30>[ 11.409056] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified) <30>[ 11.444141] systemd[1]: Detected architecture x86-64. Welcome to Debian GNU/Linux 11 (bullseye)! <30>[ 11.456160] systemd[1]: Set hostname to . <6>[ 11.484114] (sd-executor) (96) used greatest stack depth: 14376 bytes left <30>[ 11.530888] systemd[1]: Queued start job for default target Graphical Interface. <28>[ 11.538913] systemd[1]: system-getty.slice: unit configures an IP firewall, but the local system does not support BPF/cgroup firewalling. <28>[ 11.551632] systemd[1]: (This warning is only shown for the first unit using IP firewalling.) <30>[ 11.560767] systemd[1]: Created slice system-getty.slice. [ OK ] Created slice system-getty.slice. <30>[ 11.575394] systemd[1]: Created slice system-modprobe.slice. [ OK ] Created slice system-modprobe.slice. <30>[ 11.590387] systemd[1]: Created slice system-serial\x2dgetty.slice. [ OK ] Created slice system-serial\x2dgetty.slice. <30>[ 11.606342] systemd[1]: Created slice User and Session Slice. [ OK ] Created slice User and Session Slice. <30>[ 11.621252] systemd[1]: Started Dispatch Password Requests to Console Directory Watch. [ OK ] Started Dispatch Password …ts to Console Directory Watch. <30>[ 11.640236] systemd[1]: Started Forward Password Requests to Wall Directory Watch. [ OK ] Started Forward Password R…uests to Wall Directory Watch. <30>[ 11.659396] systemd[1]: Set up automount Arbitrary Executable File Formats File System Automount Point. [ OK ] Set up automount Arbitrary…s File System Automount Point. <30>[ 11.680179] systemd[1]: Reached target Local Encrypted Volumes. [ OK ] Reached target Local Encrypted Volumes. <30>[ 11.696154] systemd[1]: Reached target Paths. [ OK ] Reached target Paths. <30>[ 11.708121] systemd[1]: Reached target Remote File Systems. [ OK ] Reached target Remote File Systems. <30>[ 11.723127] systemd[1]: Reached target Slices. [ OK ] Reached target Slices. <30>[ 11.736093] systemd[1]: Reached target Swap. [ OK ] Reached target Swap. <30>[ 11.748318] systemd[1]: Listening on initctl Compatibility Named Pipe. [ OK ] Listening on initctl Compatibility Named Pipe. <30>[ 11.765429] systemd[1]: Listening on Journal Audit Socket. [ OK ] Listening on Journal Audit Socket. <30>[ 11.780376] systemd[1]: Listening on Journal Socket (/dev/log). [ OK ] Listening on Journal Socket (/dev/log). <30>[ 11.796383] systemd[1]: Listening on Journal Socket. [ OK ] Listening on Journal Socket. <30>[ 11.810402] systemd[1]: Listening on udev Control Socket. [ OK ] Listening on udev Control Socket. <30>[ 11.825329] systemd[1]: Listening on udev Kernel Socket. [ OK ] Listening on udev Kernel Socket. <30>[ 11.840037] systemd[1]: Mounting Huge Pages File System... Mounting Huge Pages File System... <30>[ 11.854877] systemd[1]: Mounting POSIX Message Queue File System... Mounting POSIX Message Queue File System... <30>[ 11.870869] systemd[1]: Mounting Kernel Debug File System... Mounting Kernel Debug File System... <30>[ 11.885881] systemd[1]: Mounting Kernel Trace File System... Mounting Kernel Trace File System... <30>[ 11.900110] systemd[1]: Condition check resulted in Create list of static device nodes for the current kernel being skipped. <30>[ 11.912589] systemd[1]: Starting Load Kernel Module configfs... Starting Load Kernel Module configfs... <30>[ 11.927930] systemd[1]: Starting Load Kernel Module drm... Starting Load Kernel Module drm... <30>[ 11.942232] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped. <30>[ 11.952495] systemd[1]: Starting Journal Service... Starting Journal Service... <30>[ 11.965988] systemd[1]: Starting Load Kernel Modules... Starting Load Kernel Modules... <30>[ 11.979663] systemd[1]: Starting Remount Root and Kernel File Systems... Starting Remount Root and Kernel File Systems... <30>[ 11.996726] systemd[1]: Starting Coldplug All udev Devices... Starting Coldplug All udev Devices... <30>[ 12.013355] systemd[1]: Mounted Huge Pages File System. [ OK ] Mounted Huge Pages File System. <30>[ 12.029134] systemd[1]: Mounted POSIX Message Queue File System. [ OK ] Mounted POSIX Message Queue File System. <30>[ 12.045300] systemd[1]: Mounted Kernel Debug File System. [ OK ] Mounted Kernel Debug File System. <30>[ 12.060044] systemd[1]: Mounted Kernel Trace File System. [ OK ] Mounted Kernel Trace File System. <30>[ 12.075726] systemd[1]: modprobe@configfs.service: Succeeded. <30>[ 12.082736] systemd[1]: Finished Load Kernel Module configfs. [ OK ] Finished Load Kernel Module configfs. <30>[ 12.098650] systemd[1]: modprobe@drm.service: Succeeded. <30>[ 12.104746] systemd[1]: Finished Load Kernel Module drm. [ OK ] Finished Load Kernel Module drm. <30>[ 12.119382] systemd[1]: Finished Load Kernel Modules. [ OK ] Finished Load Kernel Modules. <30>[ 12.135114] systemd[1]: Mounting Kernel Configuration File System... Mounting Kernel Configuration File System... <30>[ 12.153625] systemd[1]: Starting Apply Kernel Variables... Starting Apply Kernel Variables... <30>[ 12.167482] systemd[1]: Started Journal Service. [ OK ] Started Journal Service. [FAILED] Failed to start Remount Root and Kernel File Systems. See 'systemctl status systemd-remount-fs.service' for details. [ OK ] Mounted Kernel Configuration File System. [ OK ] Finished Apply Kernel Variables.<6>[ 12.210336] udevadm (115) used greatest stack depth: 14280 bytes left [ OK ] Finished Coldplug All udev Devices. Starting Flush Journal to Persistent Storage... <46>[ 12.239911] systemd-journald[108]: Received client request to flush runtime journal. Starting Load/Save Random Seed... Starting Create System Users... [ OK ] Finished Flush Journal to Persistent Storage. [ OK ] Finished Load/Save Random Seed. [ OK ] Finished Create System Users. Starting Create Static Device Nodes in /dev... [ OK ] Finished Create Static Device Nodes in /dev. [ OK ] Reached target Local File Systems (Pre). [ OK ] Reached target Local File Systems. Starting Create Volatile Files and Directories... Starting Rule-based Manage…for Device Events and Files... [ OK ] Finished Create Volatile Files and Directories. Starting Network Time Synchronization... Starting Update UTMP about System Boot/Shutdown... [ OK ] Started Rule-based Manager for Device Events and Files. [ OK ] Finished Update UTMP about System Boot/Shutdown. [ OK ] Started Network Time Synchronization. [ OK ] Reached target System Initialization. [ OK ] Started Daily Cleanup of Temporary Directories. [ OK ] Reached target System Time Set.<4>[ 12.528070] da7219 i2c-DLGS7219:00: Using default DAI clk names: da7219-dai-wclk, da7219-dai-bclk [ OK ] Reached target System Time Synchronized. [ OK ] Started Discard unused blocks once a week. <6>[ 12.557555] cz-da7219-max98357a AMD7219:00: ASoC: CPU DAI designware-i2s.1.auto not registered <3>[ 12.566708] cz-da7219-max98357a AMD7219:00: devm_snd_soc_register_card(acpd7219m98357) failed: -517 [ OK ] Reached target Timers.<6>[ 12.578697] cz-da7219-max98357a AMD7219:00: ASoC: CPU DAI designware-i2s.1.auto not registered [ OK ] Listening on D-Bus System Message Bus Socket.<3>[ 12.595878] cz-da7219-max98357a AMD7219:00: devm_snd_soc_register_card(acpd7219m98357) failed: -517 <6>[ 12.600988] chromeos ramoops using acpi device. [ OK ] Reached target Sockets.<4>[ 12.618296] cros-usbpd-notify-acpi GOOG0003:00: Couldn't get Chrome EC device pointer. <6>[ 12.629453] cz-da7219-max98357a AMD7219:00: ASoC: CPU DAI designware-i2s.1.auto not registered <3>[ 12.640120] cz-da7219-max98357a AMD7219:00: devm_snd_soc_register_card(acpd7219m98357) failed: -517 [ OK ] Reached target Basic System.<3>[ 12.657854] designware-i2s designware-i2s.1.auto: IRQ index 0 not found <6>[ 12.680241] cz-da7219-max98357a AMD7219:00: ASoC: CPU DAI designware-i2s.2.auto not registered <3>[ 12.687901] designware-i2s designware-i2s.2.auto: IRQ index 0 not found <3>[ 12.692004] cz-da7219-max98357a AMD7219:00: devm_snd_soc_register_card(acpd7219m98357) failed: -517 [ OK ] Started D-Bus System Message Bus.<6>[ 12.706582] cz-da7219-max98357a AMD7219:00: ASoC: CPU DAI designware-i2s.2.auto not registered <3>[ 12.721808] cz-da7219-max98357a AMD7219:00: devm_snd_soc_register_card(acpd7219m98357) failed: -517 Starting User Login Management... Starting Permit User Sessions... <3>[ 12.825285] designware-i2s designware-i2s.3.auto: IRQ index 0 not found <6>[ 12.832541] r8152 2-1.1:1.0 enx88541f0f6c0a: renamed from eth1 <6>[ 12.833476] cz-da7219-max98357a AMD7219:00: ASoC: CPU DAI designware-i2s.3.auto not registered <3>[ 12.851210] cz-da7219-max98357a AMD7219:00: devm_snd_soc_register_card(acpd7219m98357) failed: -517 <6>[ 12.897157] cz-da7219-max98357a AMD7219:00: ASoC: CPU DAI designware-i2s.3.auto not registered <3>[ 12.955667] cz-da7219-max98357a AMD7219:00: devm_snd_soc_register_card(acpd7219m98357) failed: -517 coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 smm starting... SMI# #0 GSMI Unknown: 0xff coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 smm starting... SMI# #0 GSMI Handshake [ OK ] Finished Permit User Sessions. <6>[ 13.028967] uvcvideo: Found UVC 1.00 device HP TrueVision HD Camera (05c8:03d1) <6>[ 13.060877] Registered efivars operations <6>[ 13.076466] input: HP TrueVision HD Camera: HP Tru as /devices/pci0000:00/0000:00:12.0/usb1/1-1/1-1.1/1-1.1:1.0/input/input5 <6>[ 13.091499] gsmi version 1.0 loaded <6>[ 13.100266] amd-da7219-play: codec dai name = da7219-hifi <6>[ 13.112243] input: acpd7219m98357 Headset Jack as /devices/platform/AMD7219:00/sound/card0/input6 <6>[ 13.130594] usbcore: registered new interface driver uvcvideo <6>[ 13.136611] USB Video Class driver (1.1.1) [ OK ] Found device /dev/ttyS0. [ OK ] Started User Login Management. [ OK ] Created slice system-systemd\x2dbacklight.slice. [ OK ] Reached target Sound Card. [ OK ] Listening on Load/Save RF …itch Status /dev/rfkill Watch. [ OK ] Started Getty on tty1. [ OK ] Started Serial Getty on ttyS0. [ OK ] Reached target Login Prompts. [ OK ] Reached target Multi-User System. [ OK ] Reached target Graphical Interface. Starting Load/Save Screen …ess of backlight:amdgpu_bl0... Starting Update UTMP about System Runlevel Changes... [FAILED] Failed to start Load/Save …tness of backlight:amdgpu_bl0. See 'systemctl status systemd-backlight…klight:amdgpu_bl0.service' for details. [ OK ] Finished Update UTMP about System Runlevel Changes. Debian GNU/Linux 11 debian-bullseye-amd64 ttyS0 debian-bullseye-amd64 login: root (automatic login) Linux debian-bullseye-amd64 5.10.186-cip37 #1 SMP Wed Aug 9 04:27:38 UTC 2023 x86_64 The programs included with the Debian GNU/Linux system are free software; the exact distribution terms for each program are described in the individual files in /usr/share/doc/*/copyright. Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent permitted by applicable law. / # / # # # / # export SHELL=/bin/sh export SHELL=/bin/sh / # . /lava-11241467/environment . /lava-11241467/environment / # /lava-11241467/bin/lava-test-runner /lava-11241467/0 /lava-11241467/bin/lava-test-runner /lava-11241467/0 + export TESTRUN_ID=0_sleep + cd /lava-11241467/0/tests/0_sleep + cat uuid + UUID=11241467_1.4.2.3.1 + set +x + ./config/lava/sleep/sleep.sh mem freeze rtcwake: assuming RTC uses UTC ... rtcwake: wakeup from "mem" using rtc0 at Wed Aug 9 04:54:32 2023 <6>[ 14.008794] PM: suspend entry (deep) <6>[ 14.022416] Filesystems sync: 0.000 seconds <6>[ 14.027016] Freezing user space processes ... (elapsed 0.001 seconds) done. <6>[ 14.035737] OOM killer disabled. <6>[ 14.039223] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done. <6>[ 14.048190] printk: Suspending console(s) (use no_console_suspend to debug) coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 smm starting... SMI# #0 SMI#: SLP = 0x0c01 Chrome EC: Set SMI mask to 0x0000000000000000 Chrome EC: Set SCI mask to 0x0000000000000000 Clearing pending EC events. Error code 1 is expected. EC returned error result code 9 SMI#: Entering S3 (Suspend-To-RAM) FMAP: Found "FLASH" version 1.1 at d7f000. FMAP: base = ff000000 size = 1000000 #areas = 30 FMAP: area RW_ELOG found @ 45d000 (16384 bytes) Manufacturer: ef SF: Detected W25Q128FW with sector size 0x1000, total 0x1000000 ELOG: NV offset 0x45d000 size 0x4000 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024 ELOG: Event(9D) added with size 10 at 2023-08-09 04:54:26 UTC coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 bootblock starting... Family_Model: 00670f00 PMxC0 STATUS: 0x40200800 BIT30 SleepReset BIT11 DW I2C bus 1 at 0xfedc3000 (400 KHz) VBOOT: Loading verstage. CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'fallback/verstage' CBFS: Found @ offset aa8c0 size d5a4 coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 verstage starting... Probing TPM I2C: done! DID_VID 0x00281ae0 TPM ready after 0 ms cr50 TPM 2.0 (i2c 1:0x50 id 0x28) tlcl_send_startup: Startup return code is 84 src/security/tpm/tss/tcg-2.0/tss.c:177 index 0x1007 return code 100 read_space_firmware():99: Antirollback: 0000500a returned by tlcl_read(FIRMWARE_NV_INDEX, ctx->secdata, VB2_SECDATA_SIZE) antirollback_read_space_firmware():474: TPM: Firmware space in a bad state; giving up. Chrome EC: UHEPI supported Phase 1 VB2:vb2_fail() Need recovery, reason: 0x2b / 0x2 FMAP: Found "FLASH" version 1.1 at d7f000. FMAP: base = ff000000 size = 1000000 #areas = 30 FMAP: area GBB found @ d80000 (458752 bytes) VB2:vb2_check_recovery() Recovery reason from previous boot: 0x2b / 0x2 VB2:vb2_check_recovery() We have a recovery request: 0x2b / 0x0 Clearing TPM owner TPM: Clear and re-enable tlcl_force_clear: response is 100 TPM: Can't initiate a force clear. Recovery requested (1009000e) Saving nvdata tlcl_extend: response is 100 CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'fallback/romstage' CBFS: Found @ offset 80 size d2e4 coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 romstage starting... CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'smu_fw' CBFS: Found @ offset 7bc00 size 12262 PSP: Load blob type 19 from @ffe6bc38... OK POST: 0x37 agesawrapper_amdinitreset() entry CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'AGESA_PRE_MEM' CBFS: Found @ offset df80 size 53bcc agesawrapper_amdinitreset() returned AGESA_SUCCESS POST: 0x38 agesawrapper_amdinitearly() entry Warning - AGESA callout: platform_PcieSlotResetControl not supported Warning - AGESA callout: platform_PcieSlotResetControl not supported agesawrapper_amdinitearly() returned AGESA_SUCCESS S3 detected POST: 0x60 agesawrapper_amdinitresume() entry Chrome EC: UHEPI supported FMAP: Found "FLASH" version 1.1 at d7f000. FMAP: base = ff000000 size = 1000000 #areas = 30 FMAP: area RW_MRC_CACHE found @ 0 (65536 bytes) S3 NV data @0xff0048c0, 0xe65 bytes agesawrapper_amdinitresume() returned AGESA_SUCCESS POST: 0x61 POST: 0x42 PSP: Notify that DRAM is available... OK POST: 0x43 creating vboot_handoff structure Chrome EC: clear events_b mask to 0x0000000021004000 POST: 0x44 MTRR Range: Start=cd000000 End=ce000000 (Size 1000000) MTRR Range: Start=ff000000 End=0 (Size 1000000) MTRR Range: Start=ce800000 End=cf000000 (Size 800000) POST: 0x45 coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 postcar starting... Jumping to image. coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 ramstage starting... POST: 0x39 FMAP: Found "FLASH" version 1.1 at d7f000. FMAP: base = ff000000 size = 1000000 #areas = 30 FMAP: area RO_VPD found @ c00000 (16384 bytes) WARNING: RO_VPD is uninitialized or empty. FMAP: area RW_VPD found @ 465000 (8192 bytes) FMAP: area RW_VPD found @ 465000 (8192 bytes) POST: 0x80 S3 Resume. POST: 0x46 agesawrapper_amds3laterestore() entry AGESA: Loading stage from cache S3 volatile data @0xceebe000 0x4160 total bytes agesawrapper_amds3laterestore() returned AGESA_SUCCESS POST: 0x70 BS: BS_PRE_DEVICE times (us): entry 20047 run 1061 exit 0 POST: 0x71 Board ID: 6 mainboard: EC init Chrome EC: Set SMI mask to 0x0000000000000000 Chrome EC: UHEPI supported Chrome EC: Set SCI mask to 0x00000000142609fb Chrome EC: Set WAKE mask to 0x0000000000000000 DW I2C bus 0 at 0xfedc2000 (400 KHz) DW I2C bus 2 at 0xfedc4000 (400 KHz) DW I2C bus 3 at 0xfedc5000 (400 KHz) FMAP: area RW_ELOG found @ 45d000 (16384 bytes) Manufacturer: ef SF: Detected W25Q128FW with sector size 0x1000, total 0x1000000 ELOG: NV offset 0x45d000 size 0x4000 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024 ELOG: Event(9E) added with size 10 at 2023-08-09 04:54:32 UTC ELOG: Event(9F) added with size 14 at 2023-08-09 04:54:32 UTC PM1_STS: WAK RTC BMSTATUS setup_bsp_ramtop, TOP MEM: msr.lo = 0xd0000000, msr.hi = 0x00000000 setup_bsp_ramtop, TOP MEM2: msr.lo = 0x2f000000, msr.hi = 0x00000001 BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 79958 exit 0 POST: 0x72 Enumerating buses... Show all devs... Before device enumeration. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 DOMAIN: 0000: enabled 1 MMIO: fedc2000: enabled 1 MMIO: fedc3000: enabled 1 MMIO: fedc4000: enabled 1 MMIO: fedc5000: enabled 1 APIC: 10: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.2: enabled 0 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 1 PCI: 00:02.2: enabled 1 PCI: 00:02.3: enabled 1 PCI: 00:02.4: enabled 1 PCI: 00:02.5: enabled 1 PCI: 00:08.0: enabled 1 PCI: 00:09.0: enabled 1 PCI: 00:09.2: enabled 1 PCI: 00:10.0: enabled 1 PCI: 00:11.0: enabled 0 PCI: 00:12.0: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:14.3: enabled 1 PCI: 00:14.7: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 GENERIC: 0.0: enabled 1 I2C: 00:1a: enabled 1 GENERIC: 0.1: enabled 1 I2C: 00:50: enabled 1 I2C: 00:15: enabled 1 I2C: 00:39: enabled 1 I2C: 00:10: enabled 1 PCI: 00:00.0: enabled 1 PNP: 0c09.0: enabled 1 Compare with tree... Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 10: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.2: enabled 0 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 1 PCI: 00:02.2: enabled 1 PCI: 00:02.3: enabled 1 PCI: 00:02.4: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:02.5: enabled 1 PCI: 00:08.0: enabled 1 PCI: 00:09.0: enabled 1 PCI: 00:09.2: enabled 1 PCI: 00:10.0: enabled 1 PCI: 00:11.0: enabled 0 PCI: 00:12.0: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:14.3: enabled 1 PNP: 0c09.0: enabled 1 PCI: 00:14.7: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 MMIO: fedc2000: enabled 1 GENERIC: 0.0: enabled 1 I2C: 00:1a: enabled 1 GENERIC: 0.1: enabled 1 MMIO: fedc3000: enabled 1 I2C: 00:50: enabled 1 MMIO: fedc4000: enabled 1 I2C: 00:15: enabled 1 MMIO: fedc5000: enabled 1 I2C: 00:39: enabled 1 I2C: 00:10: enabled 1 Mainboard Grunt Enable. Root Device scanning... root_dev_scan_bus for Root Device CPU_CLUSTER: 0 enabled DOMAIN: 0000 enabled MMIO: fedc2000 enabled MMIO: fedc3000 enabled MMIO: fedc4000 enabled MMIO: fedc5000 enabled DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 POST: 0x24 sb_enable PCI: 00:00.0 [1022/1576] enabled sb_enable sb_enable PCI: 00:01.0 [1002/98e4] enabled sb_enable PCI: 00:01.1 [1002/15b3] enabled sb_enable PCI: 00:02.0 [1022/157b] enabled sb_enable PCI: Static device PCI: 00:02.1 not found, disabling it. sb_enable Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xc0 Capability: type 0x08 @ 0xc8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 PCI: 00:02.2 subordinate bus PCI Express PCI: 00:02.2 [1022/157c] enabled sb_enable PCI: Static device PCI: 00:02.3 not found, disabling it. sb_enable Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xc0 Capability: type 0x08 @ 0xc8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 PCI: 00:02.4 subordinate bus PCI Express PCI: 00:02.4 [1022/157c] enabled sb_enable PCI: Static device PCI: 00:02.5 not found, disabling it. PCI: 00:03.0 [1022/157b] enabled sb_enable PCI: 00:08.0 [1022/1578] enabled sb_enable PCI: 00:09.0 [1022/157d] enabled sb_enable PCI: Static device PCI: 00:09.2 not found, disabling it. sb_enable PCI: Static device PCI: 00:10.0 not found, disabling it. sb_enable sb_enable PCI: Static device PCI: 00:12.0 not found, disabling it. sb_enable PCI: 00:14.0 [1022/790b] bus ops PCI: 00:14.0 [1022/790b] enabled sb_enable PCI: 00:14.3 [1022/0000] bus ops PCI: 00:14.3 [1022/790e] enabled sb_enable PCI: Static device PCI: 00:14.7 not found, disabling it. sb_enable PCI: 00:18.0 [1022/15b0] ops PCI: 00:18.0 [1022/15b0] enabled sb_enable PCI: 00:18.1 [1022/15b1] enabled sb_enable PCI: 00:18.2 [1022/15b2] enabled sb_enable PCI: 00:18.3 [1022/15b3] enabled sb_enable PCI: 00:18.4 [1022/15b4] enabled sb_enable PCI: 00:18.5 [1022/15b5] enabled POST: 0x25 PCI: 00:02.2 scanning... do_pci_scan_bridge for PCI: 00:02.2 PCI: pci_scan_bus for bus 01 POST: 0x24 PCI: 01:00.0 [168c/003e] enabled POST: 0x25 POST: 0x55 Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x50 Capability: type 0x10 @ 0x70 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Enabling Common Clock Configuration ASPM: Enabled L0s and L1 Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x50 Capability: type 0x10 @ 0x70 scan_bus: scanning of bus PCI: 00:02.2 took 40766 usecs PCI: 00:02.4 scanning... do_pci_scan_bridge for PCI: 00:02.4 PCI: pci_scan_bus for bus 02 POST: 0x24 PCI: 02:00.0 [1217/0000] ops PCI: 02:00.0 [1217/8620] enabled POST: 0x25 POST: 0x55 Capability: type 0x01 @ 0x6c Capability: type 0x05 @ 0x48 Capability: type 0x10 @ 0x80 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 ASPM: Enabled L0s and L1 Capability: type 0x01 @ 0x6c Capability: type 0x05 @ 0x48 Capability: type 0x10 @ 0x80 scan_bus: scanning of bus PCI: 00:02.4 took 40398 usecs PCI: 00:14.0 scanning... scan_generic_bus for PCI: 00:14.0 scan_generic_bus for PCI: 00:14.0 done scan_bus: scanning of bus PCI: 00:14.0 took 8804 usecs PCI: 00:14.3 scanning... scan_lpc_bus for PCI: 00:14.3 PNP: 0c09.0 enabled scan_lpc_bus for PCI: 00:14.3 done scan_bus: scanning of bus PCI: 00:14.3 took 9940 usecs POST: 0x55 scan_bus: scanning of bus DOMAIN: 0000 took 289522 usecs MMIO: fedc2000 scanning... scan_generic_bus for MMIO: fedc2000 bus: MMIO: fedc2000[0]->GENERIC: 0.0 enabled bus: MMIO: fedc2000[0]->I2C: 01:1a enabled bus: MMIO: fedc2000[0]->GENERIC: 0.1 enabled scan_generic_bus for MMIO: fedc2000 done scan_bus: scanning of bus MMIO: fedc2000 took 21233 usecs MMIO: fedc3000 scanning... scan_generic_bus for MMIO: fedc3000 bus: MMIO: fedc3000[0]->I2C: 02:50 enabled scan_generic_bus for MMIO: fedc3000 done scan_bus: scanning of bus MMIO: fedc3000 took 13203 usecs MMIO: fedc4000 scanning... scan_generic_bus for MMIO: fedc4000 bus: MMIO: fedc4000[0]->I2C: 03:15 enabled scan_generic_bus for MMIO: fedc4000 done scan_bus: scanning of bus MMIO: fedc4000 took 13152 usecs MMIO: fedc5000 scanning... scan_generic_bus for MMIO: fedc5000 bus: MMIO: fedc5000[0]->I2C: 04:39 enabled bus: MMIO: fedc5000[0]->I2C: 04:10 enabled scan_generic_bus for MMIO: fedc5000 done scan_bus: scanning of bus MMIO: fedc5000 took 16983 usecs root_dev_scan_bus for Root Device done scan_bus: scanning of bus Root Device took 400708 usecs done BS: BS_DEV_ENUMERATE times (us): entry 0 run 605670 exit 0 POST: 0x73 found VGA at PCI: 00:01.0 Setting up VGA for PCI: 00:01.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done DOMAIN: 0000 read_resources bus 0 link: 0 PCI: 00:02.2 read_resources bus 1 link: 0 PCI: 00:02.2 read_resources bus 1 link: 0 done PCI: 00:02.4 read_resources bus 2 link: 0 PCI: 00:02.4 read_resources bus 2 link: 0 done PCI: 00:14.3 read_resources bus 0 link: 0 PCI: 00:14.3 read_resources bus 0 link: 0 done Adding PCIe enhanced config space BAR 0xf8000000-0xfc000000. DOMAIN: 0000 read_resources bus 0 link: 0 done MMIO: fedc2000 read_resources bus 1 link: 0 MMIO: fedc2000 read_resources bus 1 link: 0 done MMIO: fedc3000 read_resources bus 2 link: 0 MMIO: fedc3000 read_resources bus 2 link: 0 done MMIO: fedc4000 read_resources bus 3 link: 0 MMIO: fedc4000 read_resources bus 3 link: 0 done MMIO: fedc5000 read_resources bus 4 link: 0 MMIO: fedc5000 read_resources bus 4 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 10 APIC: 10 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI: 00:00.0 PCI: 00:00.2 PCI: 00:01.0 PCI: 00:01.0 resource base 0 size 4000000 align 26 gran 26 limit ffffffffffffffff flags 1201 index 10 PCI: 00:01.0 resource base 0 size 800000 align 23 gran 23 limit ffffffffffffffff flags 1201 index 18 PCI: 00:01.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 20 PCI: 00:01.0 resource base 0 size 40000 align 18 gran 18 limit ffffffff flags 200 index 24 PCI: 00:01.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 2200 index 30 PCI: 00:01.1 PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 PCI: 00:02.0 PCI: 00:02.1 PCI: 00:02.2 child on link 0 PCI: 01:00.0 PCI: 00:02.2 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:02.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:02.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 01:00.0 PCI: 01:00.0 resource base 0 size 200000 align 21 gran 21 limit ffffffffffffffff flags 201 index 10 PCI: 00:02.3 PCI: 00:02.4 child on link 0 PCI: 02:00.0 PCI: 00:02.4 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:02.4 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:02.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 02:00.0 PCI: 02:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 02:00.0 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 14 PCI: 00:02.5 PCI: 00:03.0 PCI: 00:08.0 PCI: 00:08.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 1201 index 10 PCI: 00:08.0 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 200 index 18 PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 1c PCI: 00:08.0 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 200 index 20 PCI: 00:08.0 resource base 0 size 2000 align 13 gran 13 limit ffffffff flags 200 index 24 PCI: 00:09.0 PCI: 00:09.2 PCI: 00:10.0 PCI: 00:11.0 PCI: 00:12.0 PCI: 00:14.0 PCI: 00:14.3 child on link 0 PNP: 0c09.0 PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:14.3 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100 PCI: 00:14.3 resource base fec10000 size 400 align 0 gran 0 limit 0 flags e0040200 index 2 PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PCI: 00:14.3 resource base fedc2000 size 4000 align 0 gran 0 limit 0 flags c0000200 index 4 PNP: 0c09.0 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0 PCI: 00:14.7 PCI: 00:18.0 PCI: 00:18.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI: 00:18.0 resource base fec20000 size 1000 align 0 gran 0 limit 0 flags c0000200 index fec20000 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.4 PCI: 00:18.5 MMIO: fedc2000 child on link 0 GENERIC: 0.0 GENERIC: 0.0 I2C: 01:1a GENERIC: 0.1 MMIO: fedc3000 child on link 0 I2C: 02:50 I2C: 02:50 MMIO: fedc4000 child on link 0 I2C: 03:15 I2C: 03:15 MMIO: fedc5000 child on link 0 I2C: 04:39 I2C: 04:39 I2C: 04:10 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:02.2 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:02.2 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:02.4 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:02.4 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:01.0 20 * [0x0 - 0xff] io DOMAIN: 0000 io: base: 100 size: 100 align: 8 gran: 0 limit: ffff done DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:02.2 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:02.2 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:02.2 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 01:00.0 10 * [0x0 - 0x1fffff] mem PCI: 00:02.2 mem: base: 200000 size: 200000 align: 21 gran: 20 limit: ffffffff done PCI: 00:02.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:02.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:02.4 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 02:00.0 10 * [0x0 - 0xfff] mem PCI: 02:00.0 14 * [0x1000 - 0x17ff] mem PCI: 00:02.4 mem: base: 1800 size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:01.0 10 * [0x0 - 0x3ffffff] prefmem PCI: 00:01.0 18 * [0x4000000 - 0x47fffff] prefmem PCI: 00:02.2 20 * [0x4800000 - 0x49fffff] mem PCI: 00:02.4 20 * [0x4a00000 - 0x4afffff] mem PCI: 00:08.0 18 * [0x4b00000 - 0x4bfffff] mem PCI: 00:08.0 20 * [0x4c00000 - 0x4cfffff] mem PCI: 00:01.0 24 * [0x4d00000 - 0x4d3ffff] mem PCI: 00:01.0 30 * [0x4d40000 - 0x4d5ffff] mem PCI: 00:08.0 10 * [0x4d60000 - 0x4d7ffff] prefmem PCI: 00:01.1 10 * [0x4d80000 - 0x4d83fff] mem PCI: 00:08.0 24 * [0x4d84000 - 0x4d85fff] mem PCI: 00:08.0 1c * [0x4d86000 - 0x4d86fff] mem DOMAIN: 0000 mem: base: 4d87000 size: 4d87000 align: 26 gran: 0 limit: ffffffff done avoid_fixed_resources: DOMAIN: 0000 avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI: 00:14.3 10000000 base 00000000 limit 00000fff io (fixed) constrain_resources: PCI: 00:14.3 10000100 base ff000000 limit ffffffff mem (fixed) constrain_resources: PCI: 00:14.3 02 base fec10000 limit fec103ff mem (fixed) constrain_resources: PCI: 00:14.3 03 base fec00000 limit fec00fff mem (fixed) constrain_resources: PCI: 00:18.0 c0010058 base f8000000 limit fbffffff mem (fixed) avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001000 limit 0000ffff avoid_fixed_resources:@DOMAIN: 0000 10000100 base f0000000 limit f7ffffff Setting resources... DOMAIN: 0000 io: base:1000 size:100 align:8 gran:0 limit:ffff PCI: 00:01.0 20 * [0x1000 - 0x10ff] io DOMAIN: 0000 io: next_base: 1100 size: 100 align: 8 gran: 0 done PCI: 00:02.2 io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:02.2 io: next_base: ffff size: 0 align: 12 gran: 12 done PCI: 00:02.4 io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:02.4 io: next_base: ffff size: 0 align: 12 gran: 12 done DOMAIN: 0000 mem: base:f0000000 size:4d87000 align:26 gran:0 limit:f7ffffff PCI: 00:01.0 10 * [0xf0000000 - 0xf3ffffff] prefmem PCI: 00:01.0 18 * [0xf4000000 - 0xf47fffff] prefmem PCI: 00:02.2 20 * [0xf4800000 - 0xf49fffff] mem PCI: 00:02.4 20 * [0xf4a00000 - 0xf4afffff] mem PCI: 00:08.0 18 * [0xf4b00000 - 0xf4bfffff] mem PCI: 00:08.0 20 * [0xf4c00000 - 0xf4cfffff] mem PCI: 00:01.0 24 * [0xf4d00000 - 0xf4d3ffff] mem PCI: 00:01.0 30 * [0xf4d40000 - 0xf4d5ffff] mem PCI: 00:08.0 10 * [0xf4d60000 - 0xf4d7ffff] prefmem PCI: 00:01.1 10 * [0xf4d80000 - 0xf4d83fff] mem PCI: 00:08.0 24 * [0xf4d84000 - 0xf4d85fff] mem PCI: 00:08.0 1c * [0xf4d86000 - 0xf4d86fff] mem DOMAIN: 0000 mem: next_base: f4d87000 size: 4d87000 align: 26 gran: 0 done PCI: 00:02.2 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff PCI: 00:02.2 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done PCI: 00:02.2 mem: base:f4800000 size:200000 align:21 gran:20 limit:f49fffff PCI: 01:00.0 10 * [0xf4800000 - 0xf49fffff] mem PCI: 00:02.2 mem: next_base: f4a00000 size: 200000 align: 21 gran: 20 done PCI: 00:02.4 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff PCI: 00:02.4 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done PCI: 00:02.4 mem: base:f4a00000 size:100000 align:20 gran:20 limit:f4afffff PCI: 02:00.0 10 * [0xf4a00000 - 0xf4a00fff] mem PCI: 02:00.0 14 * [0xf4a01000 - 0xf4a017ff] mem PCI: 00:02.4 mem: next_base: f4a01800 size: 100000 align: 20 gran: 20 done Root Device assign_resources, bus 0 link: 0 DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:01.0 10 <- [0x00f0000000 - 0x00f3ffffff] size 0x04000000 gran 0x1a prefmem64 PCI: 00:01.0 18 <- [0x00f4000000 - 0x00f47fffff] size 0x00800000 gran 0x17 prefmem64 PCI: 00:01.0 20 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io PCI: 00:01.0 24 <- [0x00f4d00000 - 0x00f4d3ffff] size 0x00040000 gran 0x12 mem PCI: 00:01.0 30 <- [0x00f4d40000 - 0x00f4d5ffff] size 0x00020000 gran 0x11 romem PCI: 00:01.1 10 <- [0x00f4d80000 - 0x00f4d83fff] size 0x00004000 gran 0x0e mem64 PCI: 00:02.2 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io PCI: 00:02.2 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 01 prefmem PCI: 00:02.2 20 <- [0x00f4800000 - 0x00f49fffff] size 0x00200000 gran 0x14 bus 01 mem PCI: 00:02.2 assign_resources, bus 1 link: 0 PCI: 01:00.0 10 <- [0x00f4800000 - 0x00f49fffff] size 0x00200000 gran 0x15 mem64 PCI: 00:02.2 assign_resources, bus 1 link: 0 PCI: 00:02.4 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io PCI: 00:02.4 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 02 prefmem PCI: 00:02.4 20 <- [0x00f4a00000 - 0x00f4afffff] size 0x00100000 gran 0x14 bus 02 mem PCI: 00:02.4 assign_resources, bus 2 link: 0 PCI: 02:00.0 10 <- [0x00f4a00000 - 0x00f4a00fff] size 0x00001000 gran 0x0c mem PCI: 02:00.0 14 <- [0x00f4a01000 - 0x00f4a017ff] size 0x00000800 gran 0x0b mem PCI: 00:02.4 assign_resources, bus 2 link: 0 PCI: 00:08.0 10 <- [0x00f4d60000 - 0x00f4d7ffff] size 0x00020000 gran 0x11 prefmem64 PCI: 00:08.0 18 <- [0x00f4b00000 - 0x00f4bfffff] size 0x00100000 gran 0x14 mem PCI: 00:08.0 1c <- [0x00f4d86000 - 0x00f4d86fff] size 0x00001000 gran 0x0c mem PCI: 00:08.0 20 <- [0x00f4c00000 - 0x00f4cfffff] size 0x00100000 gran 0x14 mem PCI: 00:08.0 24 <- [0x00f4d84000 - 0x00f4d85fff] size 0x00002000 gran 0x0d mem PCI: 00:14.3 assign_resources, bus 0 link: 0 PCI: 00:14.3 assign_resources, bus 0 link: 0 DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 10 APIC: 10 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 1000 size 100 align 8 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base f0000000 size 4d87000 align 26 gran 0 limit f7ffffff flags 40040200 index 10000100 DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10 DOMAIN: 0000 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11 DOMAIN: 0000 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12 DOMAIN: 0000 resource base 100000 size cdf00000 align 0 gran 0 limit 0 flags e0004200 index 13 DOMAIN: 0000 resource base ce000000 size 2000000 align 0 gran 0 limit 0 flags f0004200 index 14 DOMAIN: 0000 resource base 100000000 size 2f000000 align 0 gran 0 limit 0 flags e0004200 index 15 PCI: 00:00.0 PCI: 00:00.2 PCI: 00:01.0 PCI: 00:01.0 resource base f0000000 size 4000000 align 26 gran 26 limit f3ffffff flags 60001201 index 10 PCI: 00:01.0 resource base f4000000 size 800000 align 23 gran 23 limit f47fffff flags 60001201 index 18 PCI: 00:01.0 resource base 1000 size 100 align 8 gran 8 limit 10ff flags 60000100 index 20 PCI: 00:01.0 resource base f4d00000 size 40000 align 18 gran 18 limit f4d3ffff flags 60000200 index 24 PCI: 00:01.0 resource base f4d40000 size 20000 align 17 gran 17 limit f4d5ffff flags 60002200 index 30 PCI: 00:01.1 PCI: 00:01.1 resource base f4d80000 size 4000 align 14 gran 14 limit f4d83fff flags 60000201 index 10 PCI: 00:02.0 PCI: 00:02.1 PCI: 00:02.2 child on link 0 PCI: 01:00.0 PCI: 00:02.2 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:02.2 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24 PCI: 00:02.2 resource base f4800000 size 200000 align 21 gran 20 limit f49fffff flags 60080202 index 20 PCI: 01:00.0 PCI: 01:00.0 resource base f4800000 size 200000 align 21 gran 21 limit f49fffff flags 60000201 index 10 PCI: 00:02.3 PCI: 00:02.4 child on link 0 PCI: 02:00.0 PCI: 00:02.4 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:02.4 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24 PCI: 00:02.4 resource base f4a00000 size 100000 align 20 gran 20 limit f4afffff flags 60080202 index 20 PCI: 02:00.0 PCI: 02:00.0 resource base f4a00000 size 1000 align 12 gran 12 limit f4a00fff flags 60000200 index 10 PCI: 02:00.0 resource base f4a01000 size 800 align 12 gran 11 limit f4a017ff flags 60000200 index 14 PCI: 00:02.5 PCI: 00:03.0 PCI: 00:08.0 PCI: 00:08.0 resource base f4d60000 size 20000 align 17 gran 17 limit f4d7ffff flags 60001201 index 10 PCI: 00:08.0 resource base f4b00000 size 100000 align 20 gran 20 limit f4bfffff flags 60000200 index 18 PCI: 00:08.0 resource base f4d86000 size 1000 align 12 gran 12 limit f4d86fff flags 60000200 index 1c PCI: 00:08.0 resource base f4c00000 size 100000 align 20 gran 20 limit f4cfffff flags 60000200 index 20 PCI: 00:08.0 resource base f4d84000 size 2000 align 13 gran 13 limit f4d85fff flags 60000200 index 24 PCI: 00:09.0 PCI: 00:09.2 PCI: 00:10.0 PCI: 00:11.0 PCI: 00:12.0 PCI: 00:14.0 PCI: 00:14.3 child on link 0 PNP: 0c09.0 PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:14.3 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100 PCI: 00:14.3 resource base fec10000 size 400 align 0 gran 0 limit 0 flags e0040200 index 2 PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PCI: 00:14.3 resource base fedc2000 size 4000 align 0 gran 0 limit 0 flags c0000200 index 4 PNP: 0c09.0 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0 PCI: 00:14.7 PCI: 00:18.0 PCI: 00:18.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI: 00:18.0 resource base fec20000 size 1000 align 0 gran 0 limit 0 flags c0000200 index fec20000 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.4 PCI: 00:18.5 MMIO: fedc2000 child on link 0 GENERIC: 0.0 GENERIC: 0.0 I2C: 01:1a GENERIC: 0.1 MMIO: fedc3000 child on link 0 I2C: 02:50 I2C: 02:50 MMIO: fedc4000 child on link 0 I2C: 03:15 I2C: 03:15 MMIO: fedc5000 child on link 0 I2C: 04:39 I2C: 04:39 I2C: 04:10 Done allocating resources. BS: BS_DEV_RESOURCES times (us): entry 0 run 1463937 exit 0 PCI_INTR tables: Writing registers C00/C01 for PCI IRQ routing: PCI_INTR_INDEX name PIC mode APIC mode 0x00 INTA# 0x03 0x10 0x01 INTB# 0x04 0x11 0x02 INTC# 0x05 0x12 0x03 INTD# 0x07 0x13 0x04 INTE# 0x0B 0x14 0x05 INTF# 0x1F 0x1F 0x06 INTG# 0x1F 0x16 0x07 INTH# 0x1F 0x17 0x08 Misc 0xFA 0x00 0x09 Misc0 0xF1 0x00 0x0A Misc1 0x00 0x00 0x0B Misc2 0x00 0x00 0x0C Ser IRQ INTA 0x1F 0x1F 0x0D Ser IRQ INTB 0x1F 0x1F 0x0E Ser IRQ INTC 0x1F 0x1F 0x0F Ser IRQ INTD 0x1F 0x1F 0x10 SCI 0x09 0x09 0x11 SMBUS 0x1F 0x1F 0x12 ASF 0x1F 0x1F 0x13 HDA 0x03 0x10 0x14 FC 0x1F 0x1F 0x16 PerMon 0x1F 0x1F 0x17 SD 0x03 0x10 0x1A SDIOt 0x00 0x1F 0x30 EHCI 0x05 0x12 0x34 XHCI 0x04 0x12 0x41 SATA 0x07 0x13 0x62 GPIO 0x07 0x07 0x70 I2C0 0x03 0x03 0x71 I2C1 0x0F 0x0F 0x72 I2C2 0x06 0x06 0x73 I2C3 0x0E 0x0E 0x74 UART0 0x0A 0x0A 0x75 UART1 0x0B 0x0B PCI_CFG IRQ: Write PCI config space IRQ assignments PCI IRQ: Found device 0:01.00 using PIN A PCI Devfn (0x8) not found in pirq_data table PCI IRQ: Found device 0:01.01 using PIN B Found this device in pirq_data table entry 5 Orig INT_PIN : 2 (PIN B) PCI_INTR idx : 0x13 (HDA) INT_LINE : 0x3 (IRQ 3) PCI IRQ: Found device 0:02.02 using PIN A Found this device in pirq_data table entry 1 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x01 (INTB#) INT_LINE : 0x4 (IRQ 4) PCI IRQ: Found device 0:02.04 using PIN A Found this device in pirq_data table entry 3 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x03 (INTD#) INT_LINE : 0x7 (IRQ 7) PCI IRQ: Found device 0:08.00 using PIN A PCI Devfn (0x40) not found in pirq_data table PCI IRQ: Found device 2:00.00 using PIN A With INT_PIN swizzled to PIN A Attached to bridge device 0:02h.04h Found this device in pirq_data table entry 3 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x03 (INTD#) INT_LINE : 0x7 (IRQ 7) PCI IRQ: Found device 1:00.00 using PIN A With INT_PIN swizzled to PIN A Attached to bridge device 0:02h.02h Found this device in pirq_data table entry 1 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x01 (INTB#) INT_LINE : 0x4 (IRQ 4) PCI_CFG IRQ: Finished writing PCI config space IRQ assignments POST: 0x74 Enabling resources... PCI: 00:00.0 subsystem <- 1022/1576 PCI: 00:00.0 cmd <- 04 PCI: 00:01.0 subsystem <- 1002/98e4 PCI: 00:01.0 cmd <- 07 PCI: 00:01.1 subsystem <- 1002/15b3 PCI: 00:01.1 cmd <- 02 PCI: 00:02.0 subsystem <- 1022/157b PCI: 00:02.0 cmd <- 00 PCI: 00:02.2 bridge ctrl <- 0003 PCI: 00:02.2 cmd <- 06 PCI: 00:02.4 bridge ctrl <- 0003 PCI: 00:02.4 cmd <- 06 PCI: 00:03.0 cmd <- 00 PCI: 00:08.0 subsystem <- 1022/1578 PCI: 00:08.0 cmd <- 06 PCI: 00:09.0 subsystem <- 1022/157d PCI: 00:09.0 cmd <- 00 PCI: 00:14.0 subsystem <- 1022/790b PCI: 00:14.0 cmd <- 403 PCI: 00:14.3 subsystem <- 1022/790e PCI: 00:14.3 cmd <- 0f Southbridge LPC decode:PNP: 0c09.0, base=0x00000800, end=0x000009fe Covered by wideIO 0 PCI: 00:18.0 cmd <- 00 PCI: 00:18.1 subsystem <- 1022/15b1 PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 subsystem <- 1022/15b2 PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 subsystem <- 1022/15b3 PCI: 00:18.3 cmd <- 00 PCI: 00:18.4 subsystem <- 1022/15b4 PCI: 00:18.4 cmd <- 00 PCI: 00:18.5 subsystem <- 1022/15b5 PCI: 00:18.5 cmd <- 00 PCI: 01:00.0 cmd <- 02 PCI: 02:00.0 subsystem <- 1217/8620 PCI: 02:00.0 cmd <- 06 done. BS: BS_DEV_ENABLE times (us): entry 235056 run 103718 exit 0 POST: 0x75 Initializing devices... Root Device init ... Root Device init finished in 1947 usecs POST: 0x75 CPU_CLUSTER: 0 init ... MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x00000000d0000000 size 0xcff40000 type 6 0x00000000d0000000 - 0x00000000f0000000 size 0x20000000 type 0 0x00000000f0000000 - 0x00000000f4800000 size 0x04800000 type 1 0x00000000f4800000 - 0x0000000100000000 size 0x0b800000 type 0 0x0000000100000000 - 0x000000012f000000 size 0x2f000000 type 6 MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e call enable_fixed_mtrr() CPU physical address size: 48 bits MTRR: default type WB/UC MTRR counts: 8/6. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000ffff80000000 type 6 MTRR: 1 base 0x0000000080000000 mask 0x0000ffffc0000000 type 6 MTRR: 2 base 0x00000000c0000000 mask 0x0000fffff0000000 type 6 MTRR: 3 base 0x00000000f0000000 mask 0x0000fffffc000000 type 1 MTRR: 4 base 0x00000000f4000000 mask 0x0000ffffff800000 type 1 MTRR: 5 base 0x0000000100000000 mask 0x0000ffffc0000000 type 6 MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Will perform SMM setup. CPU: AMD A4-9120C RADEON R4, 5 COMPUTE CORES 2C+3G . Loading module at 00030000 with entry 00030000. filesize: 0x170 memsize: 0x170 Processing 16 relocs. Offset value of 0x00030000 Attempting to start 1 APs Waiting for 10ms after sending INIT. Waiting for 1st SIPI to complete...AP: slot 1 apic_id 11. done. Waiting for 2nd SIPI to complete...done. Loading module at 00038000 with entry 00038000. filesize: 0x1a8 memsize: 0x1a8 Processing 13 relocs. Offset value of 0x00038000 SMM Module: stub loaded at 00038000. Will call cdeb995b(00000000) Installing SMM handler to 0xce800000 Loading module at ce810000 with entry ce81142b. filesize: 0x6c98 memsize: 0xad18 Processing 481 relocs. Offset value of 0xce810000 Loading module at ce808000 with entry ce808000. filesize: 0x1a8 memsize: 0x1a8 Processing 13 relocs. Offset value of 0xce808000 SMM Module: placing jmp sequence at ce807e00 rel16 0x01fd SMM Module: stub loaded at ce808000. Will call ce81142b(00000000) New SMBASE 0xce800000 Relocation complete. New SMBASE 0xce7ffe00 Relocation complete. Initializing CPU #0 CPU: vendor AMD device 670f00 CPU: family 15, model 70, stepping 00 Setting up local APIC... apic_id: 0x10 done. CPU #0 initialized Initializing CPU #1 CPU: vendor AMD device 670f00 CPU: family 15, model 70, stepping 00 Setting up local APIC... apic_id: 0x11 done. CPU #1 initialized bsp_do_flight_plan done after 91 msecs. MTRR: TEMPORARY Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x00000000d0000000 size 0xcff40000 type 6 0x00000000d0000000 - 0x00000000ff000000 size 0x2f000000 type 0 0x00000000ff000000 - 0x0000000100000000 size 0x01000000 type 5 0x0000000100000000 - 0x000000012f000000 size 0x2f000000 type 6 MTRR: default type WB/UC MTRR counts: 7/5. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000ffff80000000 type 6 MTRR: 1 base 0x0000000080000000 mask 0x0000ffffc0000000 type 6 MTRR: 2 base 0x00000000c0000000 mask 0x0000fffff0000000 type 6 MTRR: 3 base 0x00000000ff000000 mask 0x0000ffffff000000 type 5 MTRR: 4 base 0x0000000100000000 mask 0x0000ffffc0000000 type 6 CPU_CLUSTER: 0 init finished in 345967 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 PCI: 00:00.0 init ... PCI: 00:00.0 init finished in 2002 usecs POST: 0x75 POST: 0x75 PCI: 00:01.0 init ... PCI: 00:01.0 init finished in 2002 usecs POST: 0x75 PCI: 00:01.1 init ... PCI: 00:01.1 init finished in 2002 usecs POST: 0x75 PCI: 00:02.0 init ... PCI: 00:02.0 init finished in 2002 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 PCI: 00:03.0 init ... PCI: 00:03.0 init finished in 2002 usecs POST: 0x75 PCI: 00:08.0 init ... PCI: 00:08.0 init finished in 2002 usecs POST: 0x75 PCI: 00:09.0 init ... PCI: 00:09.0 init finished in 2002 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 PCI: 00:14.0 init ... IOAPIC: Initializing IOAPIC at 0xfec00000 IOAPIC: Bootstrap Processor Local APIC = 0x10 IOAPIC: ID = 0x04 IOAPIC: Dumping registers reg 0x0000: 0x04000000 reg 0x0001: 0x00178021 reg 0x0002: 0x04000000 IOAPIC: 24 interrupts IOAPIC: Enabling interrupts on FSB IOAPIC: reg 0x00000000 value 0x10000000 0x00000700 IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 IOAPIC: reg 0x00000017 value 0x00000000 0x00010000 PCI: 00:14.0 init finished in 133959 usecs POST: 0x75 PCI: 00:14.3 init ... PCI: 00:14.3 init finished in 2061 usecs POST: 0x75 POST: 0x75 PCI: 00:18.0 init ... IOAPIC: Initializing IOAPIC at 0xfec20000 IOAPIC: Bootstrap Processor Local APIC = 0x10 IOAPIC: ID = 0x05 IOAPIC: Dumping registers reg 0x0000: 0x05000000 reg 0x0001: 0x001f8021 reg 0x0002: 0x00000000 IOAPIC: 32 interrupts IOAPIC: Enabling interrupts on FSB IOAPIC: reg 0x00000000 value 0x10000000 0x00000700 IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 IOAPIC: reg 0x00000017 value 0x00000000 0x00010000 IOAPIC: reg 0x00000018 value 0x00000000 0x00010000 IOAPIC: reg 0x00000019 value 0x00000000 0x00010000 IOAPIC: reg 0x0000001a value 0x00000000 0x00010000 IOAPIC: reg 0x0000001b value 0x00000000 0x00010000 IOAPIC: reg 0x0000001c value 0x00000000 0x00010000 IOAPIC: reg 0x0000001d value 0x00000000 0x00010000 IOAPIC: reg 0x0000001e value 0x00000000 0x00010000 IOAPIC: reg 0x0000001f value 0x00000000 0x00010000 PCI: 00:18.0 init finished in 170043 usecs POST: 0x75 PCI: 00:18.1 init ... PCI: 00:18.1 init finished in 2002 usecs POST: 0x75 PCI: 00:18.2 init ... PCI: 00:18.2 init finished in 2002 usecs POST: 0x75 PCI: 00:18.3 init ... PCI: 00:18.3 init finished in 2002 usecs POST: 0x75 PCI: 00:18.4 init ... PCI: 00:18.4 init finished in 2002 usecs POST: 0x75 PCI: 00:18.5 init ... PCI: 00:18.5 init finished in 2002 usecs POST: 0x75 PCI: 01:00.0 init ... PCI: 01:00.0 init finished in 2002 usecs POST: 0x75 PCI: 02:00.0 init ... BayHub BH720: Power-saving enabled (link_ctrl=0x110103) PCI: 02:00.0 init finished in 7127 usecs POST: 0x75 PNP: 0c09.0 init ... Google Chrome EC: Hello got back 11223344 status (0) Google Chrome EC: version: ro: careena_v2.0.11488-7215d6e0e4 rw: careena_v2.0.11488-7215d6e0e4 running image: 1 Google Chrome EC uptime: 87.091 seconds Google Chrome AP resets since EC boot: 0 Google Chrome most recent AP reset causes: Google Chrome EC reset flags at last EC boot: reset-pin PNP: 0c09.0 init finished in 34541 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 Devices initialized Show all devs... After init. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 DOMAIN: 0000: enabled 1 MMIO: fedc2000: enabled 1 MMIO: fedc3000: enabled 1 MMIO: fedc4000: enabled 1 MMIO: fedc5000: enabled 1 APIC: 10: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.2: enabled 0 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 0 PCI: 00:02.2: enabled 1 PCI: 00:02.3: enabled 0 PCI: 00:02.4: enabled 1 PCI: 00:02.5: enabled 0 PCI: 00:08.0: enabled 1 PCI: 00:09.0: enabled 1 PCI: 00:09.2: enabled 0 PCI: 00:10.0: enabled 0 PCI: 00:11.0: enabled 0 PCI: 00:12.0: enabled 0 PCI: 00:14.0: enabled 1 PCI: 00:14.3: enabled 1 PCI: 00:14.7: enabled 0 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 GENERIC: 0.0: enabled 1 I2C: 01:1a: enabled 1 GENERIC: 0.1: enabled 1 I2C: 02:50: enabled 1 I2C: 03:15: enabled 1 I2C: 04:39: enabled 1 I2C: 04:10: enabled 1 PCI: 02:00.0: enabled 1 PNP: 0c09.0: enabled 1 PCI: 00:03.0: enabled 1 PCI: 01:00.0: enabled 1 APIC: 11: enabled 1 BS: BS_DEV_INIT times (us): entry 0 run 947931 exit 141 ELOG: Event(A1) added with size 10 at 2023-08-09 04:54:36 UTC elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x2b POST: 0x76 Finalize devices... Devices finalized FMAP: area RW_NVRAM found @ 467000 (20480 bytes) BS: BS_POST_DEVICE times (us): entry 12947 run 4545 exit 4671 FMAP: area RW_MRC_CACHE found @ 0 (65536 bytes) MRC: Checking cached data update for 'RW_MRC_CACHE'. POST: 0x77 Trying to find the wakeup vector... Looking on 000f0000 for valid checksum Checksum 1 passed Checksum 2 passed all OK RSDP found at 000f0000 RSDT found at cde2e030 ends at cde2e07c FADT found at cde31e60 FACS found at cde2e240 OS waking vector is 0009a1d0 BS: BS_OS_RESUME_CHECK times (us): entry 9597 run 24105 exit 0 agesawrapper_amds3finalrestore() entry S3 volatile data @0xceebe000 0x4160 total bytes agesawrapper_amds3finalrestore() returned AGESA_SUCCESS Lock SMM configuration POST: 0xfe Probing TPM I2C: done! DID_VID 0x00281ae0 Locality already claimed cr50 TPM 2.0 (i2c 1:0x50 id 0x28) Platform hierarchy disablement failed: 5001 POST: 0x78 mp_park_aps done after 0 msecs. Restore GNVS pointer to cde6b000 smm_setup_structures STUB!!! POST: 0xfd <6>[ 14.126908] ACPI: EC: interrupt blocked <6>[ 14.151674] ACPI: Preparing to enter system sleep state S3 <6>[ 14.152484] ACPI: EC: event blocked <6>[ 14.152485] ACPI: EC: EC stopped <6>[ 14.152486] PM: Saving platform NVS memory <6>[ 14.152487] Disabling non-boot CPUs ... <6>[ 14.153887] smpboot: CPU 1 is now offline <6>[ 14.154377] ACPI: Low-level resume complete <6>[ 14.154394] ACPI: EC: EC started <6>[ 14.154395] PM: Restoring platform NVS memory <6>[ 14.154412] LVT offset 0 assigned for vector 0x400 <6>[ 14.154673] Enabling non-boot CPUs ... <6>[ 14.154709] x86: Booting SMP configuration: <6>[ 14.154710] smpboot: Booting Node 0 Processor 1 APIC 0x11 <6>[ 14.154865] microcode: CPU1: patch_level=0x06006705 <6>[ 14.157184] ACPI: \_PR_.P001: Found 2 idle states <6>[ 14.157403] CPU1 is up <6>[ 14.157698] ACPI: Waking up from system sleep state S3 <6>[ 14.184919] ACPI: EC: interrupt unblocked <6>[ 14.210766] ACPI: EC: event unblocked <6>[ 14.211468] [drm] PCIE GART of 1024M enabled (table at 0x000000F400000000). <6>[ 14.211491] amdgpu: smu version 33.09.00 <6>[ 14.479990] usb 1-1.1: reset high-speed USB device number 3 using ehci-pci <6>[ 14.502027] r8152 2-4:1.0 eth0: carrier on <6>[ 14.891602] [drm] UVD initialized successfully. <6>[ 14.993228] [drm] VCE initialized successfully. <6>[ 15.117471] OOM killer enabled. <6>[ 15.120869] Restarting tasks ... done. <6>[ 15.127135] PM: suspend exit <6>[ 15.130524] rtcwake (205) used greatest stack depth: 14144 bytes left rtcwake: assuming RTC uses UTC ... rtcwake: wakeup from "mem" using rtc0 at Wed Aug 9 04:54:43 2023 <6>[ 15.158969] PM: suspend entry (deep) <6>[ 15.162834] Filesystems sync: 0.000 seconds <6>[ 15.167536] Freezing user space processes ... (elapsed 0.001 seconds) done. <6>[ 15.176470] OOM killer disabled. <6>[ 15.179956] Freezing remaining freezable tasks ... (elapsed 1.093 seconds) done. <6>[ 16.297951] printk: Suspending console(s) (use no_console_suspend to debug) coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 smm starting... SMI# #0 SMI#: SLP = 0x0c01 Chrome EC: UHEPI supported Chrome EC: Set SMI mask to 0x0000000000000000 Chrome EC: Set SCI mask to 0x0000000000000000 Clearing pending EC events. Error code 1 is expected. EC returned error result code 9 SMI#: Entering S3 (Suspend-To-RAM) FMAP: Found "FLASH" version 1.1 at d7f000. FMAP: base = ff000000 size = 1000000 #areas = 30 FMAP: area RW_ELOG found @ 45d000 (16384 bytes) Manufacturer: ef SF: Detected W25Q128FW with sector size 0x1000, total 0x1000000 ELOG: NV offset 0x45d000 size 0x4000 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024 ELOG: Event(9D) added with size 10 at 2023-08-09 04:54:38 UTC coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 bootblock starting... Family_Model: 00670f00 PMxC0 STATUS: 0x40200800 BIT30 SleepReset BIT11 DW I2C bus 1 at 0xfedc3000 (400 KHz) VBOOT: Loading verstage. CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'fallback/verstage' CBFS: Found @ offset aa8c0 size d5a4 coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 verstage starting... Probing TPM I2C: done! DID_VID 0x00281ae0 TPM ready after 0 ms cr50 TPM 2.0 (i2c 1:0x50 id 0x28) tlcl_send_startup: Startup return code is 84 src/security/tpm/tss/tcg-2.0/tss.c:177 index 0x1007 return code 100 read_space_firmware():99: Antirollback: 0000500a returned by tlcl_read(FIRMWARE_NV_INDEX, ctx->secdata, VB2_SECDATA_SIZE) antirollback_read_space_firmware():474: TPM: Firmware space in a bad state; giving up. Chrome EC: UHEPI supported Phase 1 VB2:vb2_fail() Need recovery, reason: 0x2b / 0x2 FMAP: Found "FLASH" version 1.1 at d7f000. FMAP: base = ff000000 size = 1000000 #areas = 30 FMAP: area GBB found @ d80000 (458752 bytes) VB2:vb2_check_recovery() Recovery reason from previous boot: 0x2b / 0x2 VB2:vb2_check_recovery() We have a recovery request: 0x2b / 0x0 Clearing TPM owner TPM: Clear and re-enable tlcl_force_clear: response is 100 TPM: Can't initiate a force clear. Recovery requested (1009000e) Saving nvdata tlcl_extend: response is 100 CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'fallback/romstage' CBFS: Found @ offset 80 size d2e4 coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 romstage starting... CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'smu_fw' CBFS: Found @ offset 7bc00 size 12262 PSP: Load blob type 19 from @ffe6bc38... OK POST: 0x37 agesawrapper_amdinitreset() entry CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'AGESA_PRE_MEM' CBFS: Found @ offset df80 size 53bcc agesawrapper_amdinitreset() returned AGESA_SUCCESS POST: 0x38 agesawrapper_amdinitearly() entry Warning - AGESA callout: platform_PcieSlotResetControl not supported Warning - AGESA callout: platform_PcieSlotResetControl not supported agesawrapper_amdinitearly() returned AGESA_SUCCESS S3 detected POST: 0x60 agesawrapper_amdinitresume() entry Chrome EC: UHEPI supported FMAP: Found "FLASH" version 1.1 at d7f000. FMAP: base = ff000000 size = 1000000 #areas = 30 FMAP: area RW_MRC_CACHE found @ 0 (65536 bytes) S3 NV data @0xff0048c0, 0xe65 bytes agesawrapper_amdinitresume() returned AGESA_SUCCESS POST: 0x61 POST: 0x42 PSP: Notify that DRAM is available... OK POST: 0x43 creating vboot_handoff structure Chrome EC: clear events_b mask to 0x0000000021004000 POST: 0x44 MTRR Range: Start=cd000000 End=ce000000 (Size 1000000) MTRR Range: Start=ff000000 End=0 (Size 1000000) MTRR Range: Start=ce800000 End=cf000000 (Size 800000) POST: 0x45 coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 postcar starting... Jumping to image. coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 ramstage starting... POST: 0x39 FMAP: Found "FLASH" version 1.1 at d7f000. FMAP: base = ff000000 size = 1000000 #areas = 30 FMAP: area RO_VPD found @ c00000 (16384 bytes) WARNING: RO_VPD is uninitialized or empty. FMAP: area RW_VPD found @ 465000 (8192 bytes) FMAP: area RW_VPD found @ 465000 (8192 bytes) POST: 0x80 S3 Resume. POST: 0x46 agesawrapper_amds3laterestore() entry AGESA: Loading stage from cache S3 volatile data @0xceebe000 0x4160 total bytes agesawrapper_amds3laterestore() returned AGESA_SUCCESS POST: 0x70 BS: BS_PRE_DEVICE times (us): entry 20385 run 1060 exit 1 POST: 0x71 Board ID: 6 mainboard: EC init Chrome EC: Set SMI mask to 0x0000000000000000 Chrome EC: UHEPI supported Chrome EC: Set SCI mask to 0x00000000142609fb Chrome EC: Set WAKE mask to 0x0000000000000000 DW I2C bus 0 at 0xfedc2000 (400 KHz) DW I2C bus 2 at 0xfedc4000 (400 KHz) DW I2C bus 3 at 0xfedc5000 (400 KHz) FMAP: area RW_ELOG found @ 45d000 (16384 bytes) Manufacturer: ef SF: Detected W25Q128FW with sector size 0x1000, total 0x1000000 ELOG: NV offset 0x45d000 size 0x4000 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024 ELOG: Event(9E) added with size 10 at 2023-08-09 04:54:43 UTC ELOG: Event(9F) added with size 14 at 2023-08-09 04:54:43 UTC PM1_STS: WAK RTC BMSTATUS setup_bsp_ramtop, TOP MEM: msr.lo = 0xd0000000, msr.hi = 0x00000000 setup_bsp_ramtop, TOP MEM2: msr.lo = 0x2f000000, msr.hi = 0x00000001 BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 79971 exit 1 POST: 0x72 Enumerating buses... Show all devs... Before device enumeration. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 DOMAIN: 0000: enabled 1 MMIO: fedc2000: enabled 1 MMIO: fedc3000: enabled 1 MMIO: fedc4000: enabled 1 MMIO: fedc5000: enabled 1 APIC: 10: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.2: enabled 0 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 1 PCI: 00:02.2: enabled 1 PCI: 00:02.3: enabled 1 PCI: 00:02.4: enabled 1 PCI: 00:02.5: enabled 1 PCI: 00:08.0: enabled 1 PCI: 00:09.0: enabled 1 PCI: 00:09.2: enabled 1 PCI: 00:10.0: enabled 1 PCI: 00:11.0: enabled 0 PCI: 00:12.0: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:14.3: enabled 1 PCI: 00:14.7: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 GENERIC: 0.0: enabled 1 I2C: 00:1a: enabled 1 GENERIC: 0.1: enabled 1 I2C: 00:50: enabled 1 I2C: 00:15: enabled 1 I2C: 00:39: enabled 1 I2C: 00:10: enabled 1 PCI: 00:00.0: enabled 1 PNP: 0c09.0: enabled 1 Compare with tree... Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 10: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.2: enabled 0 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 1 PCI: 00:02.2: enabled 1 PCI: 00:02.3: enabled 1 PCI: 00:02.4: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:02.5: enabled 1 PCI: 00:08.0: enabled 1 PCI: 00:09.0: enabled 1 PCI: 00:09.2: enabled 1 PCI: 00:10.0: enabled 1 PCI: 00:11.0: enabled 0 PCI: 00:12.0: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:14.3: enabled 1 PNP: 0c09.0: enabled 1 PCI: 00:14.7: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 MMIO: fedc2000: enabled 1 GENERIC: 0.0: enabled 1 I2C: 00:1a: enabled 1 GENERIC: 0.1: enabled 1 MMIO: fedc3000: enabled 1 I2C: 00:50: enabled 1 MMIO: fedc4000: enabled 1 I2C: 00:15: enabled 1 MMIO: fedc5000: enabled 1 I2C: 00:39: enabled 1 I2C: 00:10: enabled 1 Mainboard Grunt Enable. Root Device scanning... root_dev_scan_bus for Root Device CPU_CLUSTER: 0 enabled DOMAIN: 0000 enabled MMIO: fedc2000 enabled MMIO: fedc3000 enabled MMIO: fedc4000 enabled MMIO: fedc5000 enabled DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 POST: 0x24 sb_enable PCI: 00:00.0 [1022/1576] enabled sb_enable sb_enable PCI: 00:01.0 [1002/98e4] enabled sb_enable PCI: 00:01.1 [1002/15b3] enabled sb_enable PCI: 00:02.0 [1022/157b] enabled sb_enable PCI: Static device PCI: 00:02.1 not found, disabling it. sb_enable Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xc0 Capability: type 0x08 @ 0xc8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 PCI: 00:02.2 subordinate bus PCI Express PCI: 00:02.2 [1022/157c] enabled sb_enable PCI: Static device PCI: 00:02.3 not found, disabling it. sb_enable Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xc0 Capability: type 0x08 @ 0xc8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 PCI: 00:02.4 subordinate bus PCI Express PCI: 00:02.4 [1022/157c] enabled sb_enable PCI: Static device PCI: 00:02.5 not found, disabling it. PCI: 00:03.0 [1022/157b] enabled sb_enable PCI: 00:08.0 [1022/1578] enabled sb_enable PCI: 00:09.0 [1022/157d] enabled sb_enable PCI: Static device PCI: 00:09.2 not found, disabling it. sb_enable PCI: Static device PCI: 00:10.0 not found, disabling it. sb_enable sb_enable PCI: Static device PCI: 00:12.0 not found, disabling it. sb_enable PCI: 00:14.0 [1022/790b] bus ops PCI: 00:14.0 [1022/790b] enabled sb_enable PCI: 00:14.3 [1022/0000] bus ops PCI: 00:14.3 [1022/790e] enabled sb_enable PCI: Static device PCI: 00:14.7 not found, disabling it. sb_enable PCI: 00:18.0 [1022/15b0] ops PCI: 00:18.0 [1022/15b0] enabled sb_enable PCI: 00:18.1 [1022/15b1] enabled sb_enable PCI: 00:18.2 [1022/15b2] enabled sb_enable PCI: 00:18.3 [1022/15b3] enabled sb_enable PCI: 00:18.4 [1022/15b4] enabled sb_enable PCI: 00:18.5 [1022/15b5] enabled POST: 0x25 PCI: 00:02.2 scanning... do_pci_scan_bridge for PCI: 00:02.2 PCI: pci_scan_bus for bus 01 POST: 0x24 PCI: 01:00.0 [168c/003e] enabled POST: 0x25 POST: 0x55 Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x50 Capability: type 0x10 @ 0x70 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Enabling Common Clock Configuration ASPM: Enabled L0s and L1 Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x50 Capability: type 0x10 @ 0x70 scan_bus: scanning of bus PCI: 00:02.2 took 40771 usecs PCI: 00:02.4 scanning... do_pci_scan_bridge for PCI: 00:02.4 PCI: pci_scan_bus for bus 02 POST: 0x24 PCI: 02:00.0 [1217/0000] ops PCI: 02:00.0 [1217/8620] enabled POST: 0x25 POST: 0x55 Capability: type 0x01 @ 0x6c Capability: type 0x05 @ 0x48 Capability: type 0x10 @ 0x80 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 ASPM: Enabled L0s and L1 Capability: type 0x01 @ 0x6c Capability: type 0x05 @ 0x48 Capability: type 0x10 @ 0x80 scan_bus: scanning of bus PCI: 00:02.4 took 40400 usecs PCI: 00:14.0 scanning... scan_generic_bus for PCI: 00:14.0 scan_generic_bus for PCI: 00:14.0 done scan_bus: scanning of bus PCI: 00:14.0 took 8801 usecs PCI: 00:14.3 scanning... scan_lpc_bus for PCI: 00:14.3 PNP: 0c09.0 enabled scan_lpc_bus for PCI: 00:14.3 done scan_bus: scanning of bus PCI: 00:14.3 took 9948 usecs POST: 0x55 scan_bus: scanning of bus DOMAIN: 0000 took 289489 usecs MMIO: fedc2000 scanning... scan_generic_bus for MMIO: fedc2000 bus: MMIO: fedc2000[0]->GENERIC: 0.0 enabled bus: MMIO: fedc2000[0]->I2C: 01:1a enabled bus: MMIO: fedc2000[0]->GENERIC: 0.1 enabled scan_generic_bus for MMIO: fedc2000 done scan_bus: scanning of bus MMIO: fedc2000 took 21203 usecs MMIO: fedc3000 scanning... scan_generic_bus for MMIO: fedc3000 bus: MMIO: fedc3000[0]->I2C: 02:50 enabled scan_generic_bus for MMIO: fedc3000 done scan_bus: scanning of bus MMIO: fedc3000 took 13170 usecs MMIO: fedc4000 scanning... scan_generic_bus for MMIO: fedc4000 bus: MMIO: fedc4000[0]->I2C: 03:15 enabled scan_generic_bus for MMIO: fedc4000 done scan_bus: scanning of bus MMIO: fedc4000 took 13152 usecs MMIO: fedc5000 scanning... scan_generic_bus for MMIO: fedc5000 bus: MMIO: fedc5000[0]->I2C: 04:39 enabled bus: MMIO: fedc5000[0]->I2C: 04:10 enabled scan_generic_bus for MMIO: fedc5000 done scan_bus: scanning of bus MMIO: fedc5000 took 16983 usecs root_dev_scan_bus for Root Device done scan_bus: scanning of bus Root Device took 400609 usecs done BS: BS_DEV_ENUMERATE times (us): entry 0 run 605566 exit 0 POST: 0x73 found VGA at PCI: 00:01.0 Setting up VGA for PCI: 00:01.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done DOMAIN: 0000 read_resources bus 0 link: 0 PCI: 00:02.2 read_resources bus 1 link: 0 PCI: 00:02.2 read_resources bus 1 link: 0 done PCI: 00:02.4 read_resources bus 2 link: 0 PCI: 00:02.4 read_resources bus 2 link: 0 done PCI: 00:14.3 read_resources bus 0 link: 0 PCI: 00:14.3 read_resources bus 0 link: 0 done Adding PCIe enhanced config space BAR 0xf8000000-0xfc000000. DOMAIN: 0000 read_resources bus 0 link: 0 done MMIO: fedc2000 read_resources bus 1 link: 0 MMIO: fedc2000 read_resources bus 1 link: 0 done MMIO: fedc3000 read_resources bus 2 link: 0 MMIO: fedc3000 read_resources bus 2 link: 0 done MMIO: fedc4000 read_resources bus 3 link: 0 MMIO: fedc4000 read_resources bus 3 link: 0 done MMIO: fedc5000 read_resources bus 4 link: 0 MMIO: fedc5000 read_resources bus 4 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 10 APIC: 10 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI: 00:00.0 PCI: 00:00.2 PCI: 00:01.0 PCI: 00:01.0 resource base 0 size 4000000 align 26 gran 26 limit ffffffffffffffff flags 1201 index 10 PCI: 00:01.0 resource base 0 size 800000 align 23 gran 23 limit ffffffffffffffff flags 1201 index 18 PCI: 00:01.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 20 PCI: 00:01.0 resource base 0 size 40000 align 18 gran 18 limit ffffffff flags 200 index 24 PCI: 00:01.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 2200 index 30 PCI: 00:01.1 PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 PCI: 00:02.0 PCI: 00:02.1 PCI: 00:02.2 child on link 0 PCI: 01:00.0 PCI: 00:02.2 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:02.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:02.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 01:00.0 PCI: 01:00.0 resource base 0 size 200000 align 21 gran 21 limit ffffffffffffffff flags 201 index 10 PCI: 00:02.3 PCI: 00:02.4 child on link 0 PCI: 02:00.0 PCI: 00:02.4 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:02.4 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:02.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 02:00.0 PCI: 02:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 02:00.0 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 14 PCI: 00:02.5 PCI: 00:03.0 PCI: 00:08.0 PCI: 00:08.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 1201 index 10 PCI: 00:08.0 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 200 index 18 PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 1c PCI: 00:08.0 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 200 index 20 PCI: 00:08.0 resource base 0 size 2000 align 13 gran 13 limit ffffffff flags 200 index 24 PCI: 00:09.0 PCI: 00:09.2 PCI: 00:10.0 PCI: 00:11.0 PCI: 00:12.0 PCI: 00:14.0 PCI: 00:14.3 child on link 0 PNP: 0c09.0 PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:14.3 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100 PCI: 00:14.3 resource base fec10000 size 400 align 0 gran 0 limit 0 flags e0040200 index 2 PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PCI: 00:14.3 resource base fedc2000 size 4000 align 0 gran 0 limit 0 flags c0000200 index 4 PNP: 0c09.0 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0 PCI: 00:14.7 PCI: 00:18.0 PCI: 00:18.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI: 00:18.0 resource base fec20000 size 1000 align 0 gran 0 limit 0 flags c0000200 index fec20000 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.4 PCI: 00:18.5 MMIO: fedc2000 child on link 0 GENERIC: 0.0 GENERIC: 0.0 I2C: 01:1a GENERIC: 0.1 MMIO: fedc3000 child on link 0 I2C: 02:50 I2C: 02:50 MMIO: fedc4000 child on link 0 I2C: 03:15 I2C: 03:15 MMIO: fedc5000 child on link 0 I2C: 04:39 I2C: 04:39 I2C: 04:10 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:02.2 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:02.2 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:02.4 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:02.4 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:01.0 20 * [0x0 - 0xff] io DOMAIN: 0000 io: base: 100 size: 100 align: 8 gran: 0 limit: ffff done DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:02.2 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:02.2 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:02.2 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 01:00.0 10 * [0x0 - 0x1fffff] mem PCI: 00:02.2 mem: base: 200000 size: 200000 align: 21 gran: 20 limit: ffffffff done PCI: 00:02.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:02.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:02.4 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 02:00.0 10 * [0x0 - 0xfff] mem PCI: 02:00.0 14 * [0x1000 - 0x17ff] mem PCI: 00:02.4 mem: base: 1800 size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:01.0 10 * [0x0 - 0x3ffffff] prefmem PCI: 00:01.0 18 * [0x4000000 - 0x47fffff] prefmem PCI: 00:02.2 20 * [0x4800000 - 0x49fffff] mem PCI: 00:02.4 20 * [0x4a00000 - 0x4afffff] mem PCI: 00:08.0 18 * [0x4b00000 - 0x4bfffff] mem PCI: 00:08.0 20 * [0x4c00000 - 0x4cfffff] mem PCI: 00:01.0 24 * [0x4d00000 - 0x4d3ffff] mem PCI: 00:01.0 30 * [0x4d40000 - 0x4d5ffff] mem PCI: 00:08.0 10 * [0x4d60000 - 0x4d7ffff] prefmem PCI: 00:01.1 10 * [0x4d80000 - 0x4d83fff] mem PCI: 00:08.0 24 * [0x4d84000 - 0x4d85fff] mem PCI: 00:08.0 1c * [0x4d86000 - 0x4d86fff] mem DOMAIN: 0000 mem: base: 4d87000 size: 4d87000 align: 26 gran: 0 limit: ffffffff done avoid_fixed_resources: DOMAIN: 0000 avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI: 00:14.3 10000000 base 00000000 limit 00000fff io (fixed) constrain_resources: PCI: 00:14.3 10000100 base ff000000 limit ffffffff mem (fixed) constrain_resources: PCI: 00:14.3 02 base fec10000 limit fec103ff mem (fixed) constrain_resources: PCI: 00:14.3 03 base fec00000 limit fec00fff mem (fixed) constrain_resources: PCI: 00:18.0 c0010058 base f8000000 limit fbffffff mem (fixed) avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001000 limit 0000ffff avoid_fixed_resources:@DOMAIN: 0000 10000100 base f0000000 limit f7ffffff Setting resources... DOMAIN: 0000 io: base:1000 size:100 align:8 gran:0 limit:ffff PCI: 00:01.0 20 * [0x1000 - 0x10ff] io DOMAIN: 0000 io: next_base: 1100 size: 100 align: 8 gran: 0 done PCI: 00:02.2 io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:02.2 io: next_base: ffff size: 0 align: 12 gran: 12 done PCI: 00:02.4 io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:02.4 io: next_base: ffff size: 0 align: 12 gran: 12 done DOMAIN: 0000 mem: base:f0000000 size:4d87000 align:26 gran:0 limit:f7ffffff PCI: 00:01.0 10 * [0xf0000000 - 0xf3ffffff] prefmem PCI: 00:01.0 18 * [0xf4000000 - 0xf47fffff] prefmem PCI: 00:02.2 20 * [0xf4800000 - 0xf49fffff] mem PCI: 00:02.4 20 * [0xf4a00000 - 0xf4afffff] mem PCI: 00:08.0 18 * [0xf4b00000 - 0xf4bfffff] mem PCI: 00:08.0 20 * [0xf4c00000 - 0xf4cfffff] mem PCI: 00:01.0 24 * [0xf4d00000 - 0xf4d3ffff] mem PCI: 00:01.0 30 * [0xf4d40000 - 0xf4d5ffff] mem PCI: 00:08.0 10 * [0xf4d60000 - 0xf4d7ffff] prefmem PCI: 00:01.1 10 * [0xf4d80000 - 0xf4d83fff] mem PCI: 00:08.0 24 * [0xf4d84000 - 0xf4d85fff] mem PCI: 00:08.0 1c * [0xf4d86000 - 0xf4d86fff] mem DOMAIN: 0000 mem: next_base: f4d87000 size: 4d87000 align: 26 gran: 0 done PCI: 00:02.2 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff PCI: 00:02.2 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done PCI: 00:02.2 mem: base:f4800000 size:200000 align:21 gran:20 limit:f49fffff PCI: 01:00.0 10 * [0xf4800000 - 0xf49fffff] mem PCI: 00:02.2 mem: next_base: f4a00000 size: 200000 align: 21 gran: 20 done PCI: 00:02.4 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff PCI: 00:02.4 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done PCI: 00:02.4 mem: base:f4a00000 size:100000 align:20 gran:20 limit:f4afffff PCI: 02:00.0 10 * [0xf4a00000 - 0xf4a00fff] mem PCI: 02:00.0 14 * [0xf4a01000 - 0xf4a017ff] mem PCI: 00:02.4 mem: next_base: f4a01800 size: 100000 align: 20 gran: 20 done Root Device assign_resources, bus 0 link: 0 DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:01.0 10 <- [0x00f0000000 - 0x00f3ffffff] size 0x04000000 gran 0x1a prefmem64 PCI: 00:01.0 18 <- [0x00f4000000 - 0x00f47fffff] size 0x00800000 gran 0x17 prefmem64 PCI: 00:01.0 20 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io PCI: 00:01.0 24 <- [0x00f4d00000 - 0x00f4d3ffff] size 0x00040000 gran 0x12 mem PCI: 00:01.0 30 <- [0x00f4d40000 - 0x00f4d5ffff] size 0x00020000 gran 0x11 romem PCI: 00:01.1 10 <- [0x00f4d80000 - 0x00f4d83fff] size 0x00004000 gran 0x0e mem64 PCI: 00:02.2 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io PCI: 00:02.2 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 01 prefmem PCI: 00:02.2 20 <- [0x00f4800000 - 0x00f49fffff] size 0x00200000 gran 0x14 bus 01 mem PCI: 00:02.2 assign_resources, bus 1 link: 0 PCI: 01:00.0 10 <- [0x00f4800000 - 0x00f49fffff] size 0x00200000 gran 0x15 mem64 PCI: 00:02.2 assign_resources, bus 1 link: 0 PCI: 00:02.4 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io PCI: 00:02.4 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 02 prefmem PCI: 00:02.4 20 <- [0x00f4a00000 - 0x00f4afffff] size 0x00100000 gran 0x14 bus 02 mem PCI: 00:02.4 assign_resources, bus 2 link: 0 PCI: 02:00.0 10 <- [0x00f4a00000 - 0x00f4a00fff] size 0x00001000 gran 0x0c mem PCI: 02:00.0 14 <- [0x00f4a01000 - 0x00f4a017ff] size 0x00000800 gran 0x0b mem PCI: 00:02.4 assign_resources, bus 2 link: 0 PCI: 00:08.0 10 <- [0x00f4d60000 - 0x00f4d7ffff] size 0x00020000 gran 0x11 prefmem64 PCI: 00:08.0 18 <- [0x00f4b00000 - 0x00f4bfffff] size 0x00100000 gran 0x14 mem PCI: 00:08.0 1c <- [0x00f4d86000 - 0x00f4d86fff] size 0x00001000 gran 0x0c mem PCI: 00:08.0 20 <- [0x00f4c00000 - 0x00f4cfffff] size 0x00100000 gran 0x14 mem PCI: 00:08.0 24 <- [0x00f4d84000 - 0x00f4d85fff] size 0x00002000 gran 0x0d mem PCI: 00:14.3 assign_resources, bus 0 link: 0 PCI: 00:14.3 assign_resources, bus 0 link: 0 DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 10 APIC: 10 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 1000 size 100 align 8 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base f0000000 size 4d87000 align 26 gran 0 limit f7ffffff flags 40040200 index 10000100 DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10 DOMAIN: 0000 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11 DOMAIN: 0000 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12 DOMAIN: 0000 resource base 100000 size cdf00000 align 0 gran 0 limit 0 flags e0004200 index 13 DOMAIN: 0000 resource base ce000000 size 2000000 align 0 gran 0 limit 0 flags f0004200 index 14 DOMAIN: 0000 resource base 100000000 size 2f000000 align 0 gran 0 limit 0 flags e0004200 index 15 PCI: 00:00.0 PCI: 00:00.2 PCI: 00:01.0 PCI: 00:01.0 resource base f0000000 size 4000000 align 26 gran 26 limit f3ffffff flags 60001201 index 10 PCI: 00:01.0 resource base f4000000 size 800000 align 23 gran 23 limit f47fffff flags 60001201 index 18 PCI: 00:01.0 resource base 1000 size 100 align 8 gran 8 limit 10ff flags 60000100 index 20 PCI: 00:01.0 resource base f4d00000 size 40000 align 18 gran 18 limit f4d3ffff flags 60000200 index 24 PCI: 00:01.0 resource base f4d40000 size 20000 align 17 gran 17 limit f4d5ffff flags 60002200 index 30 PCI: 00:01.1 PCI: 00:01.1 resource base f4d80000 size 4000 align 14 gran 14 limit f4d83fff flags 60000201 index 10 PCI: 00:02.0 PCI: 00:02.1 PCI: 00:02.2 child on link 0 PCI: 01:00.0 PCI: 00:02.2 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:02.2 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24 PCI: 00:02.2 resource base f4800000 size 200000 align 21 gran 20 limit f49fffff flags 60080202 index 20 PCI: 01:00.0 PCI: 01:00.0 resource base f4800000 size 200000 align 21 gran 21 limit f49fffff flags 60000201 index 10 PCI: 00:02.3 PCI: 00:02.4 child on link 0 PCI: 02:00.0 PCI: 00:02.4 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:02.4 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24 PCI: 00:02.4 resource base f4a00000 size 100000 align 20 gran 20 limit f4afffff flags 60080202 index 20 PCI: 02:00.0 PCI: 02:00.0 resource base f4a00000 size 1000 align 12 gran 12 limit f4a00fff flags 60000200 index 10 PCI: 02:00.0 resource base f4a01000 size 800 align 12 gran 11 limit f4a017ff flags 60000200 index 14 PCI: 00:02.5 PCI: 00:03.0 PCI: 00:08.0 PCI: 00:08.0 resource base f4d60000 size 20000 align 17 gran 17 limit f4d7ffff flags 60001201 index 10 PCI: 00:08.0 resource base f4b00000 size 100000 align 20 gran 20 limit f4bfffff flags 60000200 index 18 PCI: 00:08.0 resource base f4d86000 size 1000 align 12 gran 12 limit f4d86fff flags 60000200 index 1c PCI: 00:08.0 resource base f4c00000 size 100000 align 20 gran 20 limit f4cfffff flags 60000200 index 20 PCI: 00:08.0 resource base f4d84000 size 2000 align 13 gran 13 limit f4d85fff flags 60000200 index 24 PCI: 00:09.0 PCI: 00:09.2 PCI: 00:10.0 PCI: 00:11.0 PCI: 00:12.0 PCI: 00:14.0 PCI: 00:14.3 child on link 0 PNP: 0c09.0 PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:14.3 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100 PCI: 00:14.3 resource base fec10000 size 400 align 0 gran 0 limit 0 flags e0040200 index 2 PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PCI: 00:14.3 resource base fedc2000 size 4000 align 0 gran 0 limit 0 flags c0000200 index 4 PNP: 0c09.0 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0 PCI: 00:14.7 PCI: 00:18.0 PCI: 00:18.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI: 00:18.0 resource base fec20000 size 1000 align 0 gran 0 limit 0 flags c0000200 index fec20000 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.4 PCI: 00:18.5 MMIO: fedc2000 child on link 0 GENERIC: 0.0 GENERIC: 0.0 I2C: 01:1a GENERIC: 0.1 MMIO: fedc3000 child on link 0 I2C: 02:50 I2C: 02:50 MMIO: fedc4000 child on link 0 I2C: 03:15 I2C: 03:15 MMIO: fedc5000 child on link 0 I2C: 04:39 I2C: 04:39 I2C: 04:10 Done allocating resources. BS: BS_DEV_RESOURCES times (us): entry 0 run 1463969 exit 0 PCI_INTR tables: Writing registers C00/C01 for PCI IRQ routing: PCI_INTR_INDEX name PIC mode APIC mode 0x00 INTA# 0x03 0x10 0x01 INTB# 0x04 0x11 0x02 INTC# 0x05 0x12 0x03 INTD# 0x07 0x13 0x04 INTE# 0x0B 0x14 0x05 INTF# 0x1F 0x1F 0x06 INTG# 0x1F 0x16 0x07 INTH# 0x1F 0x17 0x08 Misc 0xFA 0x00 0x09 Misc0 0xF1 0x00 0x0A Misc1 0x00 0x00 0x0B Misc2 0x00 0x00 0x0C Ser IRQ INTA 0x1F 0x1F 0x0D Ser IRQ INTB 0x1F 0x1F 0x0E Ser IRQ INTC 0x1F 0x1F 0x0F Ser IRQ INTD 0x1F 0x1F 0x10 SCI 0x09 0x09 0x11 SMBUS 0x1F 0x1F 0x12 ASF 0x1F 0x1F 0x13 HDA 0x03 0x10 0x14 FC 0x1F 0x1F 0x16 PerMon 0x1F 0x1F 0x17 SD 0x03 0x10 0x1A SDIOt 0x00 0x1F 0x30 EHCI 0x05 0x12 0x34 XHCI 0x04 0x12 0x41 SATA 0x07 0x13 0x62 GPIO 0x07 0x07 0x70 I2C0 0x03 0x03 0x71 I2C1 0x0F 0x0F 0x72 I2C2 0x06 0x06 0x73 I2C3 0x0E 0x0E 0x74 UART0 0x0A 0x0A 0x75 UART1 0x0B 0x0B PCI_CFG IRQ: Write PCI config space IRQ assignments PCI IRQ: Found device 0:01.00 using PIN A PCI Devfn (0x8) not found in pirq_data table PCI IRQ: Found device 0:01.01 using PIN B Found this device in pirq_data table entry 5 Orig INT_PIN : 2 (PIN B) PCI_INTR idx : 0x13 (HDA) INT_LINE : 0x3 (IRQ 3) PCI IRQ: Found device 0:02.02 using PIN A Found this device in pirq_data table entry 1 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x01 (INTB#) INT_LINE : 0x4 (IRQ 4) PCI IRQ: Found device 0:02.04 using PIN A Found this device in pirq_data table entry 3 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x03 (INTD#) INT_LINE : 0x7 (IRQ 7) PCI IRQ: Found device 0:08.00 using PIN A PCI Devfn (0x40) not found in pirq_data table PCI IRQ: Found device 2:00.00 using PIN A With INT_PIN swizzled to PIN A Attached to bridge device 0:02h.04h Found this device in pirq_data table entry 3 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x03 (INTD#) INT_LINE : 0x7 (IRQ 7) PCI IRQ: Found device 1:00.00 using PIN A With INT_PIN swizzled to PIN A Attached to bridge device 0:02h.02h Found this device in pirq_data table entry 1 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x01 (INTB#) INT_LINE : 0x4 (IRQ 4) PCI_CFG IRQ: Finished writing PCI config space IRQ assignments POST: 0x74 Enabling resources... PCI: 00:00.0 subsystem <- 1022/1576 PCI: 00:00.0 cmd <- 04 PCI: 00:01.0 subsystem <- 1002/98e4 PCI: 00:01.0 cmd <- 07 PCI: 00:01.1 subsystem <- 1002/15b3 PCI: 00:01.1 cmd <- 02 PCI: 00:02.0 subsystem <- 1022/157b PCI: 00:02.0 cmd <- 00 PCI: 00:02.2 bridge ctrl <- 0003 PCI: 00:02.2 cmd <- 06 PCI: 00:02.4 bridge ctrl <- 0003 PCI: 00:02.4 cmd <- 06 PCI: 00:03.0 cmd <- 00 PCI: 00:08.0 subsystem <- 1022/1578 PCI: 00:08.0 cmd <- 06 PCI: 00:09.0 subsystem <- 1022/157d PCI: 00:09.0 cmd <- 00 PCI: 00:14.0 subsystem <- 1022/790b PCI: 00:14.0 cmd <- 403 PCI: 00:14.3 subsystem <- 1022/790e PCI: 00:14.3 cmd <- 0f Southbridge LPC decode:PNP: 0c09.0, base=0x00000800, end=0x000009fe Covered by wideIO 0 PCI: 00:18.0 cmd <- 00 PCI: 00:18.1 subsystem <- 1022/15b1 PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 subsystem <- 1022/15b2 PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 subsystem <- 1022/15b3 PCI: 00:18.3 cmd <- 00 PCI: 00:18.4 subsystem <- 1022/15b4 PCI: 00:18.4 cmd <- 00 PCI: 00:18.5 subsystem <- 1022/15b5 PCI: 00:18.5 cmd <- 00 PCI: 01:00.0 cmd <- 02 PCI: 02:00.0 subsystem <- 1217/8620 PCI: 02:00.0 cmd <- 06 done. BS: BS_DEV_ENABLE times (us): entry 235070 run 103680 exit 0 POST: 0x75 Initializing devices... Root Device init ... Root Device init finished in 1947 usecs POST: 0x75 CPU_CLUSTER: 0 init ... MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x00000000d0000000 size 0xcff40000 type 6 0x00000000d0000000 - 0x00000000f0000000 size 0x20000000 type 0 0x00000000f0000000 - 0x00000000f4800000 size 0x04800000 type 1 0x00000000f4800000 - 0x0000000100000000 size 0x0b800000 type 0 0x0000000100000000 - 0x000000012f000000 size 0x2f000000 type 6 MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e call enable_fixed_mtrr() CPU physical address size: 48 bits MTRR: default type WB/UC MTRR counts: 8/6. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000ffff80000000 type 6 MTRR: 1 base 0x0000000080000000 mask 0x0000ffffc0000000 type 6 MTRR: 2 base 0x00000000c0000000 mask 0x0000fffff0000000 type 6 MTRR: 3 base 0x00000000f0000000 mask 0x0000fffffc000000 type 1 MTRR: 4 base 0x00000000f4000000 mask 0x0000ffffff800000 type 1 MTRR: 5 base 0x0000000100000000 mask 0x0000ffffc0000000 type 6 MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Will perform SMM setup. CPU: AMD A4-9120C RADEON R4, 5 COMPUTE CORES 2C+3G . Loading module at 00030000 with entry 00030000. filesize: 0x170 memsize: 0x170 Processing 16 relocs. Offset value of 0x00030000 Attempting to start 1 APs Waiting for 10ms after sending INIT. Waiting for 1st SIPI to complete...AP: slot 1 apic_id 11. done. Waiting for 2nd SIPI to complete...done. Loading module at 00038000 with entry 00038000. filesize: 0x1a8 memsize: 0x1a8 Processing 13 relocs. Offset value of 0x00038000 SMM Module: stub loaded at 00038000. Will call cdeb995b(00000000) Installing SMM handler to 0xce800000 Loading module at ce810000 with entry ce81142b. filesize: 0x6c98 memsize: 0xad18 Processing 481 relocs. Offset value of 0xce810000 Loading module at ce808000 with entry ce808000. filesize: 0x1a8 memsize: 0x1a8 Processing 13 relocs. Offset value of 0xce808000 SMM Module: placing jmp sequence at ce807e00 rel16 0x01fd SMM Module: stub loaded at ce808000. Will call ce81142b(00000000) New SMBASE 0xce800000 Relocation complete. New SMBASE 0xce7ffe00 Relocation complete. Initializing CPU #0 CPU: vendor AMD device 670f00 CPU: family 15, model 70, stepping 00 Setting up local APIC... apic_id: 0x10 done. CPU #0 initialized Initializing CPU #1 CPU: vendor AMD device 670f00 CPU: family 15, model 70, stepping 00 Setting up local APIC... apic_id: 0x11 done. CPU #1 initialized bsp_do_flight_plan done after 91 msecs. MTRR: TEMPORARY Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x00000000d0000000 size 0xcff40000 type 6 0x00000000d0000000 - 0x00000000ff000000 size 0x2f000000 type 0 0x00000000ff000000 - 0x0000000100000000 size 0x01000000 type 5 0x0000000100000000 - 0x000000012f000000 size 0x2f000000 type 6 MTRR: default type WB/UC MTRR counts: 7/5. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000ffff80000000 type 6 MTRR: 1 base 0x0000000080000000 mask 0x0000ffffc0000000 type 6 MTRR: 2 base 0x00000000c0000000 mask 0x0000fffff0000000 type 6 MTRR: 3 base 0x00000000ff000000 mask 0x0000ffffff000000 type 5 MTRR: 4 base 0x0000000100000000 mask 0x0000ffffc0000000 type 6 CPU_CLUSTER: 0 init finished in 345972 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 PCI: 00:00.0 init ... PCI: 00:00.0 init finished in 2002 usecs POST: 0x75 POST: 0x75 PCI: 00:01.0 init ... PCI: 00:01.0 init finished in 2002 usecs POST: 0x75 PCI: 00:01.1 init ... PCI: 00:01.1 init finished in 2001 usecs POST: 0x75 PCI: 00:02.0 init ... PCI: 00:02.0 init finished in 2001 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 PCI: 00:03.0 init ... PCI: 00:03.0 init finished in 2002 usecs POST: 0x75 PCI: 00:08.0 init ... PCI: 00:08.0 init finished in 2002 usecs POST: 0x75 PCI: 00:09.0 init ... PCI: 00:09.0 init finished in 2001 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 PCI: 00:14.0 init ... IOAPIC: Initializing IOAPIC at 0xfec00000 IOAPIC: Bootstrap Processor Local APIC = 0x10 IOAPIC: ID = 0x04 IOAPIC: Dumping registers reg 0x0000: 0x04000000 reg 0x0001: 0x00178021 reg 0x0002: 0x04000000 IOAPIC: 24 interrupts IOAPIC: Enabling interrupts on FSB IOAPIC: reg 0x00000000 value 0x10000000 0x00000700 IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 IOAPIC: reg 0x00000017 value 0x00000000 0x00010000 PCI: 00:14.0 init finished in 133968 usecs POST: 0x75 PCI: 00:14.3 init ... PCI: 00:14.3 init finished in 2060 usecs POST: 0x75 POST: 0x75 PCI: 00:18.0 init ... IOAPIC: Initializing IOAPIC at 0xfec20000 IOAPIC: Bootstrap Processor Local APIC = 0x10 IOAPIC: ID = 0x05 IOAPIC: Dumping registers reg 0x0000: 0x05000000 reg 0x0001: 0x001f8021 reg 0x0002: 0x00000000 IOAPIC: 32 interrupts IOAPIC: Enabling interrupts on FSB IOAPIC: reg 0x00000000 value 0x10000000 0x00000700 IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 IOAPIC: reg 0x00000017 value 0x00000000 0x00010000 IOAPIC: reg 0x00000018 value 0x00000000 0x00010000 IOAPIC: reg 0x00000019 value 0x00000000 0x00010000 IOAPIC: reg 0x0000001a value 0x00000000 0x00010000 IOAPIC: reg 0x0000001b value 0x00000000 0x00010000 IOAPIC: reg 0x0000001c value 0x00000000 0x00010000 IOAPIC: reg 0x0000001d value 0x00000000 0x00010000 IOAPIC: reg 0x0000001e value 0x00000000 0x00010000 IOAPIC: reg 0x0000001f value 0x00000000 0x00010000 PCI: 00:18.0 init finished in 170046 usecs POST: 0x75 PCI: 00:18.1 init ... PCI: 00:18.1 init finished in 2001 usecs POST: 0x75 PCI: 00:18.2 init ... PCI: 00:18.2 init finished in 2002 usecs POST: 0x75 PCI: 00:18.3 init ... PCI: 00:18.3 init finished in 2001 usecs POST: 0x75 PCI: 00:18.4 init ... PCI: 00:18.4 init finished in 2001 usecs POST: 0x75 PCI: 00:18.5 init ... PCI: 00:18.5 init finished in 2001 usecs POST: 0x75 PCI: 01:00.0 init ... PCI: 01:00.0 init finished in 2002 usecs POST: 0x75 PCI: 02:00.0 init ... BayHub BH720: Power-saving enabled (link_ctrl=0x110103) PCI: 02:00.0 init finished in 7127 usecs POST: 0x75 PNP: 0c09.0 init ... Google Chrome EC: Hello got back 11223344 status (0) Google Chrome EC: version: ro: careena_v2.0.11488-7215d6e0e4 rw: careena_v2.0.11488-7215d6e0e4 running image: 1 Google Chrome EC uptime: 98.074 seconds Google Chrome AP resets since EC boot: 0 Google Chrome most recent AP reset causes: Google Chrome EC reset flags at last EC boot: reset-pin PNP: 0c09.0 init finished in 34552 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 Devices initialized Show all devs... After init. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 DOMAIN: 0000: enabled 1 MMIO: fedc2000: enabled 1 MMIO: fedc3000: enabled 1 MMIO: fedc4000: enabled 1 MMIO: fedc5000: enabled 1 APIC: 10: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.2: enabled 0 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 0 PCI: 00:02.2: enabled 1 PCI: 00:02.3: enabled 0 PCI: 00:02.4: enabled 1 PCI: 00:02.5: enabled 0 PCI: 00:08.0: enabled 1 PCI: 00:09.0: enabled 1 PCI: 00:09.2: enabled 0 PCI: 00:10.0: enabled 0 PCI: 00:11.0: enabled 0 PCI: 00:12.0: enabled 0 PCI: 00:14.0: enabled 1 PCI: 00:14.3: enabled 1 PCI: 00:14.7: enabled 0 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 GENERIC: 0.0: enabled 1 I2C: 01:1a: enabled 1 GENERIC: 0.1: enabled 1 I2C: 02:50: enabled 1 I2C: 03:15: enabled 1 I2C: 04:39: enabled 1 I2C: 04:10: enabled 1 PCI: 02:00.0: enabled 1 PNP: 0c09.0: enabled 1 PCI: 00:03.0: enabled 1 PCI: 01:00.0: enabled 1 APIC: 11: enabled 1 BS: BS_DEV_INIT times (us): entry 0 run 947950 exit 141 ELOG: Event(A1) added with size 10 at 2023-08-09 04:54:47 UTC elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x2b POST: 0x76 Finalize devices... Devices finalized FMAP: area RW_NVRAM found @ 467000 (20480 bytes) BS: BS_POST_DEVICE times (us): entry 12973 run 4542 exit 4671 FMAP: area RW_MRC_CACHE found @ 0 (65536 bytes) MRC: Checking cached data update for 'RW_MRC_CACHE'. POST: 0x77 Trying to find the wakeup vector... Looking on 000f0000 for valid checksum Checksum 1 passed Checksum 2 passed all OK RSDP found at 000f0000 RSDT found at cde2e030 ends at cde2e07c FADT found at cde31e60 FACS found at cde2e240 OS waking vector is 0009a1d0 BS: BS_OS_RESUME_CHECK times (us): entry 9569 run 24097 exit 0 agesawrapper_amds3finalrestore() entry S3 volatile data @0xceebe000 0x4160 total bytes agesawrapper_amds3finalrestore() returned AGESA_SUCCESS Lock SMM configuration POST: 0xfe Probing TPM I2C: done! DID_VID 0x00281ae0 Locality already claimed cr50 TPM 2.0 (i2c 1:0x50 id 0x28) Platform hierarchy disablement failed: 5001 POST: 0x78 mp_park_aps done after 0 msecs. Restore GNVS pointer to cde6b000 smm_setup_structures STUB!!! POST: 0xfd <6>[ 16.382879] ACPI: EC: interrupt blocked <6>[ 16.406957] ACPI: Preparing to enter system sleep state S3 <6>[ 16.407746] ACPI: EC: event blocked <6>[ 16.407747] ACPI: EC: EC stopped <6>[ 16.407748] PM: Saving platform NVS memory <6>[ 16.407749] Disabling non-boot CPUs ... <6>[ 16.409171] smpboot: CPU 1 is now offline <6>[ 16.409617] ACPI: Low-level resume complete <6>[ 16.409634] ACPI: EC: EC started <6>[ 16.409634] PM: Restoring platform NVS memory <6>[ 16.409651] LVT offset 0 assigned for vector 0x400 <6>[ 16.409908] Enabling non-boot CPUs ... <6>[ 16.409943] x86: Booting SMP configuration: <6>[ 16.409944] smpboot: Booting Node 0 Processor 1 APIC 0x11 <6>[ 16.410098] microcode: CPU1: patch_level=0x06006705 <6>[ 16.412437] ACPI: \_PR_.P001: Found 2 idle states <6>[ 16.412647] CPU1 is up <6>[ 16.412946] ACPI: Waking up from system sleep state S3 <6>[ 16.440122] ACPI: EC: interrupt unblocked <6>[ 16.466388] ACPI: EC: event unblocked <6>[ 16.467075] [drm] PCIE GART of 1024M enabled (table at 0x000000F400000000). <6>[ 16.467090] amdgpu: smu version 33.09.00 <6>[ 16.734933] usb 1-1.1: reset high-speed USB device number 3 using ehci-pci <6>[ 16.773210] r8152 2-4:1.0 eth0: carrier on <6>[ 17.155614] [drm] UVD initialized successfully. <6>[ 17.256661] [drm] VCE initialized successfully. <6>[ 17.380287] OOM killer enabled. <6>[ 17.383676] Restarting tasks ... done. <6>[ 17.393586] PM: suspend exit <6>[ 17.396968] rtcwake (253) used greatest stack depth: 13728 bytes left rtcwake: assuming RTC uses UTC ... rtcwake: wakeup from "mem" using rtc0 at Wed Aug 9 04:54:54 2023 <6>[ 17.425281] PM: suspend entry (deep) <6>[ 17.429164] Filesystems sync: 0.000 seconds <6>[ 17.433765] Freezing user space processes ... (elapsed 0.001 seconds) done. <6>[ 17.442912] OOM killer disabled. <6>[ 17.446395] Freezing remaining freezable tasks ... (elapsed 1.101 seconds) done. <6>[ 18.571516] printk: Suspending console(s) (use no_console_suspend to debug) coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 smm starting... SMI# #0 SMI#: SLP = 0x0c01 Chrome EC: UHEPI supported Chrome EC: Set SMI mask to 0x0000000000000000 Chrome EC: Set SCI mask to 0x0000000000000000 Clearing pending EC events. Error code 1 is expected. EC returned error result code 9 SMI#: Entering S3 (Suspend-To-RAM) FMAP: Found "FLASH" version 1.1 at d7f000. FMAP: base = ff000000 size = 1000000 #areas = 30 FMAP: area RW_ELOG found @ 45d000 (16384 bytes) Manufacturer: ef SF: Detected W25Q128FW with sector size 0x1000, total 0x1000000 ELOG: NV offset 0x45d000 size 0x4000 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024 ELOG: Event(9D) added with size 10 at 2023-08-09 04:54:49 UTC coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 bootblock starting... Family_Model: 00670f00 PMxC0 STATUS: 0x40200800 BIT30 SleepReset BIT11 DW I2C bus 1 at 0xfedc3000 (400 KHz) VBOOT: Loading verstage. CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'fallback/verstage' CBFS: Found @ offset aa8c0 size d5a4 coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 verstage starting... Probing TPM I2C: done! DID_VID 0x00281ae0 TPM ready after 0 ms cr50 TPM 2.0 (i2c 1:0x50 id 0x28) tlcl_send_startup: Startup return code is 84 src/security/tpm/tss/tcg-2.0/tss.c:177 index 0x1007 return code 100 read_space_firmware():99: Antirollback: 0000500a returned by tlcl_read(FIRMWARE_NV_INDEX, ctx->secdata, VB2_SECDATA_SIZE) antirollback_read_space_firmware():474: TPM: Firmware space in a bad state; giving up. Chrome EC: UHEPI supported Phase 1 VB2:vb2_fail() Need recovery, reason: 0x2b / 0x2 FMAP: Found "FLASH" version 1.1 at d7f000. FMAP: base = ff000000 size = 1000000 #areas = 30 FMAP: area GBB found @ d80000 (458752 bytes) VB2:vb2_check_recovery() Recovery reason from previous boot: 0x2b / 0x2 VB2:vb2_check_recovery() We have a recovery request: 0x2b / 0x0 Clearing TPM owner TPM: Clear and re-enable tlcl_force_clear: response is 100 TPM: Can't initiate a force clear. Recovery requested (1009000e) Saving nvdata tlcl_extend: response is 100 CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'fallback/romstage' CBFS: Found @ offset 80 size d2e4 coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 romstage starting... CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'smu_fw' CBFS: Found @ offset 7bc00 size 12262 PSP: Load blob type 19 from @ffe6bc38... OK POST: 0x37 agesawrapper_amdinitreset() entry CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'AGESA_PRE_MEM' CBFS: Found @ offset df80 size 53bcc agesawrapper_amdinitreset() returned AGESA_SUCCESS POST: 0x38 agesawrapper_amdinitearly() entry Warning - AGESA callout: platform_PcieSlotResetControl not supported Warning - AGESA callout: platform_PcieSlotResetControl not supported agesawrapper_amdinitearly() returned AGESA_SUCCESS S3 detected POST: 0x60 agesawrapper_amdinitresume() entry Chrome EC: UHEPI supported FMAP: Found "FLASH" version 1.1 at d7f000. FMAP: base = ff000000 size = 1000000 #areas = 30 FMAP: area RW_MRC_CACHE found @ 0 (65536 bytes) S3 NV data @0xff0048c0, 0xe65 bytes agesawrapper_amdinitresume() returned AGESA_SUCCESS POST: 0x61 POST: 0x42 PSP: Notify that DRAM is available... OK POST: 0x43 creating vboot_handoff structure Chrome EC: clear events_b mask to 0x0000000021004000 POST: 0x44 MTRR Range: Start=cd000000 End=ce000000 (Size 1000000) MTRR Range: Start=ff000000 End=0 (Size 1000000) MTRR Range: Start=ce800000 End=cf000000 (Size 800000) POST: 0x45 coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 postcar starting... Jumping to image. coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 ramstage starting... POST: 0x39 FMAP: Found "FLASH" version 1.1 at d7f000. FMAP: base = ff000000 size = 1000000 #areas = 30 FMAP: area RO_VPD found @ c00000 (16384 bytes) WARNING: RO_VPD is uninitialized or empty. FMAP: area RW_VPD found @ 465000 (8192 bytes) FMAP: area RW_VPD found @ 465000 (8192 bytes) POST: 0x80 S3 Resume. POST: 0x46 agesawrapper_amds3laterestore() entry AGESA: Loading stage from cache S3 volatile data @0xceebe000 0x4160 total bytes agesawrapper_amds3laterestore() returned AGESA_SUCCESS POST: 0x70 BS: BS_PRE_DEVICE times (us): entry 20039 run 1061 exit 0 POST: 0x71 Board ID: 6 mainboard: EC init Chrome EC: Set SMI mask to 0x0000000000000000 Chrome EC: UHEPI supported Chrome EC: Set SCI mask to 0x00000000142609fb Chrome EC: Set WAKE mask to 0x0000000000000000 DW I2C bus 0 at 0xfedc2000 (400 KHz) DW I2C bus 2 at 0xfedc4000 (400 KHz) DW I2C bus 3 at 0xfedc5000 (400 KHz) FMAP: area RW_ELOG found @ 45d000 (16384 bytes) Manufacturer: ef SF: Detected W25Q128FW with sector size 0x1000, total 0x1000000 ELOG: NV offset 0x45d000 size 0x4000 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024 ELOG: Event(9E) added with size 10 at 2023-08-09 04:54:54 UTC ELOG: Event(9F) added with size 14 at 2023-08-09 04:54:54 UTC PM1_STS: WAK RTC BMSTATUS setup_bsp_ramtop, TOP MEM: msr.lo = 0xd0000000, msr.hi = 0x00000000 setup_bsp_ramtop, TOP MEM2: msr.lo = 0x2f000000, msr.hi = 0x00000001 BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 80317 exit 1 POST: 0x72 Enumerating buses... Show all devs... Before device enumeration. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 DOMAIN: 0000: enabled 1 MMIO: fedc2000: enabled 1 MMIO: fedc3000: enabled 1 MMIO: fedc4000: enabled 1 MMIO: fedc5000: enabled 1 APIC: 10: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.2: enabled 0 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 1 PCI: 00:02.2: enabled 1 PCI: 00:02.3: enabled 1 PCI: 00:02.4: enabled 1 PCI: 00:02.5: enabled 1 PCI: 00:08.0: enabled 1 PCI: 00:09.0: enabled 1 PCI: 00:09.2: enabled 1 PCI: 00:10.0: enabled 1 PCI: 00:11.0: enabled 0 PCI: 00:12.0: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:14.3: enabled 1 PCI: 00:14.7: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 GENERIC: 0.0: enabled 1 I2C: 00:1a: enabled 1 GENERIC: 0.1: enabled 1 I2C: 00:50: enabled 1 I2C: 00:15: enabled 1 I2C: 00:39: enabled 1 I2C: 00:10: enabled 1 PCI: 00:00.0: enabled 1 PNP: 0c09.0: enabled 1 Compare with tree... Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 10: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.2: enabled 0 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 1 PCI: 00:02.2: enabled 1 PCI: 00:02.3: enabled 1 PCI: 00:02.4: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:02.5: enabled 1 PCI: 00:08.0: enabled 1 PCI: 00:09.0: enabled 1 PCI: 00:09.2: enabled 1 PCI: 00:10.0: enabled 1 PCI: 00:11.0: enabled 0 PCI: 00:12.0: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:14.3: enabled 1 PNP: 0c09.0: enabled 1 PCI: 00:14.7: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 MMIO: fedc2000: enabled 1 GENERIC: 0.0: enabled 1 I2C: 00:1a: enabled 1 GENERIC: 0.1: enabled 1 MMIO: fedc3000: enabled 1 I2C: 00:50: enabled 1 MMIO: fedc4000: enabled 1 I2C: 00:15: enabled 1 MMIO: fedc5000: enabled 1 I2C: 00:39: enabled 1 I2C: 00:10: enabled 1 Mainboard Grunt Enable. Root Device scanning... root_dev_scan_bus for Root Device CPU_CLUSTER: 0 enabled DOMAIN: 0000 enabled MMIO: fedc2000 enabled MMIO: fedc3000 enabled MMIO: fedc4000 enabled MMIO: fedc5000 enabled DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 POST: 0x24 sb_enable PCI: 00:00.0 [1022/1576] enabled sb_enable sb_enable PCI: 00:01.0 [1002/98e4] enabled sb_enable PCI: 00:01.1 [1002/15b3] enabled sb_enable PCI: 00:02.0 [1022/157b] enabled sb_enable PCI: Static device PCI: 00:02.1 not found, disabling it. sb_enable Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xc0 Capability: type 0x08 @ 0xc8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 PCI: 00:02.2 subordinate bus PCI Express PCI: 00:02.2 [1022/157c] enabled sb_enable PCI: Static device PCI: 00:02.3 not found, disabling it. sb_enable Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xc0 Capability: type 0x08 @ 0xc8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 PCI: 00:02.4 subordinate bus PCI Express PCI: 00:02.4 [1022/157c] enabled sb_enable PCI: Static device PCI: 00:02.5 not found, disabling it. PCI: 00:03.0 [1022/157b] enabled sb_enable PCI: 00:08.0 [1022/1578] enabled sb_enable PCI: 00:09.0 [1022/157d] enabled sb_enable PCI: Static device PCI: 00:09.2 not found, disabling it. sb_enable PCI: Static device PCI: 00:10.0 not found, disabling it. sb_enable sb_enable PCI: Static device PCI: 00:12.0 not found, disabling it. sb_enable PCI: 00:14.0 [1022/790b] bus ops PCI: 00:14.0 [1022/790b] enabled sb_enable PCI: 00:14.3 [1022/0000] bus ops PCI: 00:14.3 [1022/790e] enabled sb_enable PCI: Static device PCI: 00:14.7 not found, disabling it. sb_enable PCI: 00:18.0 [1022/15b0] ops PCI: 00:18.0 [1022/15b0] enabled sb_enable PCI: 00:18.1 [1022/15b1] enabled sb_enable PCI: 00:18.2 [1022/15b2] enabled sb_enable PCI: 00:18.3 [1022/15b3] enabled sb_enable PCI: 00:18.4 [1022/15b4] enabled sb_enable PCI: 00:18.5 [1022/15b5] enabled POST: 0x25 PCI: 00:02.2 scanning... do_pci_scan_bridge for PCI: 00:02.2 PCI: pci_scan_bus for bus 01 POST: 0x24 PCI: 01:00.0 [168c/003e] enabled POST: 0x25 POST: 0x55 Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x50 Capability: type 0x10 @ 0x70 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Enabling Common Clock Configuration ASPM: Enabled L0s and L1 Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x50 Capability: type 0x10 @ 0x70 scan_bus: scanning of bus PCI: 00:02.2 took 40759 usecs PCI: 00:02.4 scanning... do_pci_scan_bridge for PCI: 00:02.4 PCI: pci_scan_bus for bus 02 POST: 0x24 PCI: 02:00.0 [1217/0000] ops PCI: 02:00.0 [1217/8620] enabled POST: 0x25 POST: 0x55 Capability: type 0x01 @ 0x6c Capability: type 0x05 @ 0x48 Capability: type 0x10 @ 0x80 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 ASPM: Enabled L0s and L1 Capability: type 0x01 @ 0x6c Capability: type 0x05 @ 0x48 Capability: type 0x10 @ 0x80 scan_bus: scanning of bus PCI: 00:02.4 took 40399 usecs PCI: 00:14.0 scanning... scan_generic_bus for PCI: 00:14.0 scan_generic_bus for PCI: 00:14.0 done scan_bus: scanning of bus PCI: 00:14.0 took 8812 usecs PCI: 00:14.3 scanning... scan_lpc_bus for PCI: 00:14.3 PNP: 0c09.0 enabled scan_lpc_bus for PCI: 00:14.3 done scan_bus: scanning of bus PCI: 00:14.3 took 9945 usecs POST: 0x55 scan_bus: scanning of bus DOMAIN: 0000 took 289536 usecs MMIO: fedc2000 scanning... scan_generic_bus for MMIO: fedc2000 bus: MMIO: fedc2000[0]->GENERIC: 0.0 enabled bus: MMIO: fedc2000[0]->I2C: 01:1a enabled bus: MMIO: fedc2000[0]->GENERIC: 0.1 enabled scan_generic_bus for MMIO: fedc2000 done scan_bus: scanning of bus MMIO: fedc2000 took 21235 usecs MMIO: fedc3000 scanning... scan_generic_bus for MMIO: fedc3000 bus: MMIO: fedc3000[0]->I2C: 02:50 enabled scan_generic_bus for MMIO: fedc3000 done scan_bus: scanning of bus MMIO: fedc3000 took 13198 usecs MMIO: fedc4000 scanning... scan_generic_bus for MMIO: fedc4000 bus: MMIO: fedc4000[0]->I2C: 03:15 enabled scan_generic_bus for MMIO: fedc4000 done scan_bus: scanning of bus MMIO: fedc4000 took 13152 usecs MMIO: fedc5000 scanning... scan_generic_bus for MMIO: fedc5000 bus: MMIO: fedc5000[0]->I2C: 04:39 enabled bus: MMIO: fedc5000[0]->I2C: 04:10 enabled scan_generic_bus for MMIO: fedc5000 done scan_bus: scanning of bus MMIO: fedc5000 took 16986 usecs root_dev_scan_bus for Root Device done scan_bus: scanning of bus Root Device took 400740 usecs done BS: BS_DEV_ENUMERATE times (us): entry 0 run 605727 exit 0 POST: 0x73 found VGA at PCI: 00:01.0 Setting up VGA for PCI: 00:01.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done DOMAIN: 0000 read_resources bus 0 link: 0 PCI: 00:02.2 read_resources bus 1 link: 0 PCI: 00:02.2 read_resources bus 1 link: 0 done PCI: 00:02.4 read_resources bus 2 link: 0 PCI: 00:02.4 read_resources bus 2 link: 0 done PCI: 00:14.3 read_resources bus 0 link: 0 PCI: 00:14.3 read_resources bus 0 link: 0 done Adding PCIe enhanced config space BAR 0xf8000000-0xfc000000. DOMAIN: 0000 read_resources bus 0 link: 0 done MMIO: fedc2000 read_resources bus 1 link: 0 MMIO: fedc2000 read_resources bus 1 link: 0 done MMIO: fedc3000 read_resources bus 2 link: 0 MMIO: fedc3000 read_resources bus 2 link: 0 done MMIO: fedc4000 read_resources bus 3 link: 0 MMIO: fedc4000 read_resources bus 3 link: 0 done MMIO: fedc5000 read_resources bus 4 link: 0 MMIO: fedc5000 read_resources bus 4 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 10 APIC: 10 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI: 00:00.0 PCI: 00:00.2 PCI: 00:01.0 PCI: 00:01.0 resource base 0 size 4000000 align 26 gran 26 limit ffffffffffffffff flags 1201 index 10 PCI: 00:01.0 resource base 0 size 800000 align 23 gran 23 limit ffffffffffffffff flags 1201 index 18 PCI: 00:01.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 20 PCI: 00:01.0 resource base 0 size 40000 align 18 gran 18 limit ffffffff flags 200 index 24 PCI: 00:01.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 2200 index 30 PCI: 00:01.1 PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 PCI: 00:02.0 PCI: 00:02.1 PCI: 00:02.2 child on link 0 PCI: 01:00.0 PCI: 00:02.2 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:02.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:02.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 01:00.0 PCI: 01:00.0 resource base 0 size 200000 align 21 gran 21 limit ffffffffffffffff flags 201 index 10 PCI: 00:02.3 PCI: 00:02.4 child on link 0 PCI: 02:00.0 PCI: 00:02.4 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:02.4 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:02.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 02:00.0 PCI: 02:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 02:00.0 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 14 PCI: 00:02.5 PCI: 00:03.0 PCI: 00:08.0 PCI: 00:08.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 1201 index 10 PCI: 00:08.0 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 200 index 18 PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 1c PCI: 00:08.0 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 200 index 20 PCI: 00:08.0 resource base 0 size 2000 align 13 gran 13 limit ffffffff flags 200 index 24 PCI: 00:09.0 PCI: 00:09.2 PCI: 00:10.0 PCI: 00:11.0 PCI: 00:12.0 PCI: 00:14.0 PCI: 00:14.3 child on link 0 PNP: 0c09.0 PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:14.3 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100 PCI: 00:14.3 resource base fec10000 size 400 align 0 gran 0 limit 0 flags e0040200 index 2 PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PCI: 00:14.3 resource base fedc2000 size 4000 align 0 gran 0 limit 0 flags c0000200 index 4 PNP: 0c09.0 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0 PCI: 00:14.7 PCI: 00:18.0 PCI: 00:18.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI: 00:18.0 resource base fec20000 size 1000 align 0 gran 0 limit 0 flags c0000200 index fec20000 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.4 PCI: 00:18.5 MMIO: fedc2000 child on link 0 GENERIC: 0.0 GENERIC: 0.0 I2C: 01:1a GENERIC: 0.1 MMIO: fedc3000 child on link 0 I2C: 02:50 I2C: 02:50 MMIO: fedc4000 child on link 0 I2C: 03:15 I2C: 03:15 MMIO: fedc5000 child on link 0 I2C: 04:39 I2C: 04:39 I2C: 04:10 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:02.2 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:02.2 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:02.4 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:02.4 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:01.0 20 * [0x0 - 0xff] io DOMAIN: 0000 io: base: 100 size: 100 align: 8 gran: 0 limit: ffff done DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:02.2 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:02.2 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:02.2 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 01:00.0 10 * [0x0 - 0x1fffff] mem PCI: 00:02.2 mem: base: 200000 size: 200000 align: 21 gran: 20 limit: ffffffff done PCI: 00:02.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:02.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:02.4 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 02:00.0 10 * [0x0 - 0xfff] mem PCI: 02:00.0 14 * [0x1000 - 0x17ff] mem PCI: 00:02.4 mem: base: 1800 size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:01.0 10 * [0x0 - 0x3ffffff] prefmem PCI: 00:01.0 18 * [0x4000000 - 0x47fffff] prefmem PCI: 00:02.2 20 * [0x4800000 - 0x49fffff] mem PCI: 00:02.4 20 * [0x4a00000 - 0x4afffff] mem PCI: 00:08.0 18 * [0x4b00000 - 0x4bfffff] mem PCI: 00:08.0 20 * [0x4c00000 - 0x4cfffff] mem PCI: 00:01.0 24 * [0x4d00000 - 0x4d3ffff] mem PCI: 00:01.0 30 * [0x4d40000 - 0x4d5ffff] mem PCI: 00:08.0 10 * [0x4d60000 - 0x4d7ffff] prefmem PCI: 00:01.1 10 * [0x4d80000 - 0x4d83fff] mem PCI: 00:08.0 24 * [0x4d84000 - 0x4d85fff] mem PCI: 00:08.0 1c * [0x4d86000 - 0x4d86fff] mem DOMAIN: 0000 mem: base: 4d87000 size: 4d87000 align: 26 gran: 0 limit: ffffffff done avoid_fixed_resources: DOMAIN: 0000 avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI: 00:14.3 10000000 base 00000000 limit 00000fff io (fixed) constrain_resources: PCI: 00:14.3 10000100 base ff000000 limit ffffffff mem (fixed) constrain_resources: PCI: 00:14.3 02 base fec10000 limit fec103ff mem (fixed) constrain_resources: PCI: 00:14.3 03 base fec00000 limit fec00fff mem (fixed) constrain_resources: PCI: 00:18.0 c0010058 base f8000000 limit fbffffff mem (fixed) avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001000 limit 0000ffff avoid_fixed_resources:@DOMAIN: 0000 10000100 base f0000000 limit f7ffffff Setting resources... DOMAIN: 0000 io: base:1000 size:100 align:8 gran:0 limit:ffff PCI: 00:01.0 20 * [0x1000 - 0x10ff] io DOMAIN: 0000 io: next_base: 1100 size: 100 align: 8 gran: 0 done PCI: 00:02.2 io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:02.2 io: next_base: ffff size: 0 align: 12 gran: 12 done PCI: 00:02.4 io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:02.4 io: next_base: ffff size: 0 align: 12 gran: 12 done DOMAIN: 0000 mem: base:f0000000 size:4d87000 align:26 gran:0 limit:f7ffffff PCI: 00:01.0 10 * [0xf0000000 - 0xf3ffffff] prefmem PCI: 00:01.0 18 * [0xf4000000 - 0xf47fffff] prefmem PCI: 00:02.2 20 * [0xf4800000 - 0xf49fffff] mem PCI: 00:02.4 20 * [0xf4a00000 - 0xf4afffff] mem PCI: 00:08.0 18 * [0xf4b00000 - 0xf4bfffff] mem PCI: 00:08.0 20 * [0xf4c00000 - 0xf4cfffff] mem PCI: 00:01.0 24 * [0xf4d00000 - 0xf4d3ffff] mem PCI: 00:01.0 30 * [0xf4d40000 - 0xf4d5ffff] mem PCI: 00:08.0 10 * [0xf4d60000 - 0xf4d7ffff] prefmem PCI: 00:01.1 10 * [0xf4d80000 - 0xf4d83fff] mem PCI: 00:08.0 24 * [0xf4d84000 - 0xf4d85fff] mem PCI: 00:08.0 1c * [0xf4d86000 - 0xf4d86fff] mem DOMAIN: 0000 mem: next_base: f4d87000 size: 4d87000 align: 26 gran: 0 done PCI: 00:02.2 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff PCI: 00:02.2 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done PCI: 00:02.2 mem: base:f4800000 size:200000 align:21 gran:20 limit:f49fffff PCI: 01:00.0 10 * [0xf4800000 - 0xf49fffff] mem PCI: 00:02.2 mem: next_base: f4a00000 size: 200000 align: 21 gran: 20 done PCI: 00:02.4 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff PCI: 00:02.4 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done PCI: 00:02.4 mem: base:f4a00000 size:100000 align:20 gran:20 limit:f4afffff PCI: 02:00.0 10 * [0xf4a00000 - 0xf4a00fff] mem PCI: 02:00.0 14 * [0xf4a01000 - 0xf4a017ff] mem PCI: 00:02.4 mem: next_base: f4a01800 size: 100000 align: 20 gran: 20 done Root Device assign_resources, bus 0 link: 0 DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:01.0 10 <- [0x00f0000000 - 0x00f3ffffff] size 0x04000000 gran 0x1a prefmem64 PCI: 00:01.0 18 <- [0x00f4000000 - 0x00f47fffff] size 0x00800000 gran 0x17 prefmem64 PCI: 00:01.0 20 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io PCI: 00:01.0 24 <- [0x00f4d00000 - 0x00f4d3ffff] size 0x00040000 gran 0x12 mem PCI: 00:01.0 30 <- [0x00f4d40000 - 0x00f4d5ffff] size 0x00020000 gran 0x11 romem PCI: 00:01.1 10 <- [0x00f4d80000 - 0x00f4d83fff] size 0x00004000 gran 0x0e mem64 PCI: 00:02.2 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io PCI: 00:02.2 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 01 prefmem PCI: 00:02.2 20 <- [0x00f4800000 - 0x00f49fffff] size 0x00200000 gran 0x14 bus 01 mem PCI: 00:02.2 assign_resources, bus 1 link: 0 PCI: 01:00.0 10 <- [0x00f4800000 - 0x00f49fffff] size 0x00200000 gran 0x15 mem64 PCI: 00:02.2 assign_resources, bus 1 link: 0 PCI: 00:02.4 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io PCI: 00:02.4 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 02 prefmem PCI: 00:02.4 20 <- [0x00f4a00000 - 0x00f4afffff] size 0x00100000 gran 0x14 bus 02 mem PCI: 00:02.4 assign_resources, bus 2 link: 0 PCI: 02:00.0 10 <- [0x00f4a00000 - 0x00f4a00fff] size 0x00001000 gran 0x0c mem PCI: 02:00.0 14 <- [0x00f4a01000 - 0x00f4a017ff] size 0x00000800 gran 0x0b mem PCI: 00:02.4 assign_resources, bus 2 link: 0 PCI: 00:08.0 10 <- [0x00f4d60000 - 0x00f4d7ffff] size 0x00020000 gran 0x11 prefmem64 PCI: 00:08.0 18 <- [0x00f4b00000 - 0x00f4bfffff] size 0x00100000 gran 0x14 mem PCI: 00:08.0 1c <- [0x00f4d86000 - 0x00f4d86fff] size 0x00001000 gran 0x0c mem PCI: 00:08.0 20 <- [0x00f4c00000 - 0x00f4cfffff] size 0x00100000 gran 0x14 mem PCI: 00:08.0 24 <- [0x00f4d84000 - 0x00f4d85fff] size 0x00002000 gran 0x0d mem PCI: 00:14.3 assign_resources, bus 0 link: 0 PCI: 00:14.3 assign_resources, bus 0 link: 0 DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 10 APIC: 10 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 1000 size 100 align 8 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base f0000000 size 4d87000 align 26 gran 0 limit f7ffffff flags 40040200 index 10000100 DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10 DOMAIN: 0000 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11 DOMAIN: 0000 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12 DOMAIN: 0000 resource base 100000 size cdf00000 align 0 gran 0 limit 0 flags e0004200 index 13 DOMAIN: 0000 resource base ce000000 size 2000000 align 0 gran 0 limit 0 flags f0004200 index 14 DOMAIN: 0000 resource base 100000000 size 2f000000 align 0 gran 0 limit 0 flags e0004200 index 15 PCI: 00:00.0 PCI: 00:00.2 PCI: 00:01.0 PCI: 00:01.0 resource base f0000000 size 4000000 align 26 gran 26 limit f3ffffff flags 60001201 index 10 PCI: 00:01.0 resource base f4000000 size 800000 align 23 gran 23 limit f47fffff flags 60001201 index 18 PCI: 00:01.0 resource base 1000 size 100 align 8 gran 8 limit 10ff flags 60000100 index 20 PCI: 00:01.0 resource base f4d00000 size 40000 align 18 gran 18 limit f4d3ffff flags 60000200 index 24 PCI: 00:01.0 resource base f4d40000 size 20000 align 17 gran 17 limit f4d5ffff flags 60002200 index 30 PCI: 00:01.1 PCI: 00:01.1 resource base f4d80000 size 4000 align 14 gran 14 limit f4d83fff flags 60000201 index 10 PCI: 00:02.0 PCI: 00:02.1 PCI: 00:02.2 child on link 0 PCI: 01:00.0 PCI: 00:02.2 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:02.2 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24 PCI: 00:02.2 resource base f4800000 size 200000 align 21 gran 20 limit f49fffff flags 60080202 index 20 PCI: 01:00.0 PCI: 01:00.0 resource base f4800000 size 200000 align 21 gran 21 limit f49fffff flags 60000201 index 10 PCI: 00:02.3 PCI: 00:02.4 child on link 0 PCI: 02:00.0 PCI: 00:02.4 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:02.4 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24 PCI: 00:02.4 resource base f4a00000 size 100000 align 20 gran 20 limit f4afffff flags 60080202 index 20 PCI: 02:00.0 PCI: 02:00.0 resource base f4a00000 size 1000 align 12 gran 12 limit f4a00fff flags 60000200 index 10 PCI: 02:00.0 resource base f4a01000 size 800 align 12 gran 11 limit f4a017ff flags 60000200 index 14 PCI: 00:02.5 PCI: 00:03.0 PCI: 00:08.0 PCI: 00:08.0 resource base f4d60000 size 20000 align 17 gran 17 limit f4d7ffff flags 60001201 index 10 PCI: 00:08.0 resource base f4b00000 size 100000 align 20 gran 20 limit f4bfffff flags 60000200 index 18 PCI: 00:08.0 resource base f4d86000 size 1000 align 12 gran 12 limit f4d86fff flags 60000200 index 1c PCI: 00:08.0 resource base f4c00000 size 100000 align 20 gran 20 limit f4cfffff flags 60000200 index 20 PCI: 00:08.0 resource base f4d84000 size 2000 align 13 gran 13 limit f4d85fff flags 60000200 index 24 PCI: 00:09.0 PCI: 00:09.2 PCI: 00:10.0 PCI: 00:11.0 PCI: 00:12.0 PCI: 00:14.0 PCI: 00:14.3 child on link 0 PNP: 0c09.0 PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:14.3 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100 PCI: 00:14.3 resource base fec10000 size 400 align 0 gran 0 limit 0 flags e0040200 index 2 PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PCI: 00:14.3 resource base fedc2000 size 4000 align 0 gran 0 limit 0 flags c0000200 index 4 PNP: 0c09.0 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0 PCI: 00:14.7 PCI: 00:18.0 PCI: 00:18.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI: 00:18.0 resource base fec20000 size 1000 align 0 gran 0 limit 0 flags c0000200 index fec20000 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.4 PCI: 00:18.5 MMIO: fedc2000 child on link 0 GENERIC: 0.0 GENERIC: 0.0 I2C: 01:1a GENERIC: 0.1 MMIO: fedc3000 child on link 0 I2C: 02:50 I2C: 02:50 MMIO: fedc4000 child on link 0 I2C: 03:15 I2C: 03:15 MMIO: fedc5000 child on link 0 I2C: 04:39 I2C: 04:39 I2C: 04:10 Done allocating resources. BS: BS_DEV_RESOURCES times (us): entry 0 run 1463930 exit 0 PCI_INTR tables: Writing registers C00/C01 for PCI IRQ routing: PCI_INTR_INDEX name PIC mode APIC mode 0x00 INTA# 0x03 0x10 0x01 INTB# 0x04 0x11 0x02 INTC# 0x05 0x12 0x03 INTD# 0x07 0x13 0x04 INTE# 0x0B 0x14 0x05 INTF# 0x1F 0x1F 0x06 INTG# 0x1F 0x16 0x07 INTH# 0x1F 0x17 0x08 Misc 0xFA 0x00 0x09 Misc0 0xF1 0x00 0x0A Misc1 0x00 0x00 0x0B Misc2 0x00 0x00 0x0C Ser IRQ INTA 0x1F 0x1F 0x0D Ser IRQ INTB 0x1F 0x1F 0x0E Ser IRQ INTC 0x1F 0x1F 0x0F Ser IRQ INTD 0x1F 0x1F 0x10 SCI 0x09 0x09 0x11 SMBUS 0x1F 0x1F 0x12 ASF 0x1F 0x1F 0x13 HDA 0x03 0x10 0x14 FC 0x1F 0x1F 0x16 PerMon 0x1F 0x1F 0x17 SD 0x03 0x10 0x1A SDIOt 0x00 0x1F 0x30 EHCI 0x05 0x12 0x34 XHCI 0x04 0x12 0x41 SATA 0x07 0x13 0x62 GPIO 0x07 0x07 0x70 I2C0 0x03 0x03 0x71 I2C1 0x0F 0x0F 0x72 I2C2 0x06 0x06 0x73 I2C3 0x0E 0x0E 0x74 UART0 0x0A 0x0A 0x75 UART1 0x0B 0x0B PCI_CFG IRQ: Write PCI config space IRQ assignments PCI IRQ: Found device 0:01.00 using PIN A PCI Devfn (0x8) not found in pirq_data table PCI IRQ: Found device 0:01.01 using PIN B Found this device in pirq_data table entry 5 Orig INT_PIN : 2 (PIN B) PCI_INTR idx : 0x13 (HDA) INT_LINE : 0x3 (IRQ 3) PCI IRQ: Found device 0:02.02 using PIN A Found this device in pirq_data table entry 1 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x01 (INTB#) INT_LINE : 0x4 (IRQ 4) PCI IRQ: Found device 0:02.04 using PIN A Found this device in pirq_data table entry 3 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x03 (INTD#) INT_LINE : 0x7 (IRQ 7) PCI IRQ: Found device 0:08.00 using PIN A PCI Devfn (0x40) not found in pirq_data table PCI IRQ: Found device 2:00.00 using PIN A With INT_PIN swizzled to PIN A Attached to bridge device 0:02h.04h Found this device in pirq_data table entry 3 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x03 (INTD#) INT_LINE : 0x7 (IRQ 7) PCI IRQ: Found device 1:00.00 using PIN A With INT_PIN swizzled to PIN A Attached to bridge device 0:02h.02h Found this device in pirq_data table entry 1 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x01 (INTB#) INT_LINE : 0x4 (IRQ 4) PCI_CFG IRQ: Finished writing PCI config space IRQ assignments POST: 0x74 Enabling resources... PCI: 00:00.0 subsystem <- 1022/1576 PCI: 00:00.0 cmd <- 04 PCI: 00:01.0 subsystem <- 1002/98e4 PCI: 00:01.0 cmd <- 07 PCI: 00:01.1 subsystem <- 1002/15b3 PCI: 00:01.1 cmd <- 02 PCI: 00:02.0 subsystem <- 1022/157b PCI: 00:02.0 cmd <- 00 PCI: 00:02.2 bridge ctrl <- 0003 PCI: 00:02.2 cmd <- 06 PCI: 00:02.4 bridge ctrl <- 0003 PCI: 00:02.4 cmd <- 06 PCI: 00:03.0 cmd <- 00 PCI: 00:08.0 subsystem <- 1022/1578 PCI: 00:08.0 cmd <- 06 PCI: 00:09.0 subsystem <- 1022/157d PCI: 00:09.0 cmd <- 00 PCI: 00:14.0 subsystem <- 1022/790b PCI: 00:14.0 cmd <- 403 PCI: 00:14.3 subsystem <- 1022/790e PCI: 00:14.3 cmd <- 0f Southbridge LPC decode:PNP: 0c09.0, base=0x00000800, end=0x000009fe Covered by wideIO 0 PCI: 00:18.0 cmd <- 00 PCI: 00:18.1 subsystem <- 1022/15b1 PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 subsystem <- 1022/15b2 PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 subsystem <- 1022/15b3 PCI: 00:18.3 cmd <- 00 PCI: 00:18.4 subsystem <- 1022/15b4 PCI: 00:18.4 cmd <- 00 PCI: 00:18.5 subsystem <- 1022/15b5 PCI: 00:18.5 cmd <- 00 PCI: 01:00.0 cmd <- 02 PCI: 02:00.0 subsystem <- 1217/8620 PCI: 02:00.0 cmd <- 06 done. BS: BS_DEV_ENABLE times (us): entry 235075 run 103751 exit 0 POST: 0x75 Initializing devices... Root Device init ... Root Device init finished in 1949 usecs POST: 0x75 CPU_CLUSTER: 0 init ... MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x00000000d0000000 size 0xcff40000 type 6 0x00000000d0000000 - 0x00000000f0000000 size 0x20000000 type 0 0x00000000f0000000 - 0x00000000f4800000 size 0x04800000 type 1 0x00000000f4800000 - 0x0000000100000000 size 0x0b800000 type 0 0x0000000100000000 - 0x000000012f000000 size 0x2f000000 type 6 MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e call enable_fixed_mtrr() CPU physical address size: 48 bits MTRR: default type WB/UC MTRR counts: 8/6. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000ffff80000000 type 6 MTRR: 1 base 0x0000000080000000 mask 0x0000ffffc0000000 type 6 MTRR: 2 base 0x00000000c0000000 mask 0x0000fffff0000000 type 6 MTRR: 3 base 0x00000000f0000000 mask 0x0000fffffc000000 type 1 MTRR: 4 base 0x00000000f4000000 mask 0x0000ffffff800000 type 1 MTRR: 5 base 0x0000000100000000 mask 0x0000ffffc0000000 type 6 MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Will perform SMM setup. CPU: AMD A4-9120C RADEON R4, 5 COMPUTE CORES 2C+3G . Loading module at 00030000 with entry 00030000. filesize: 0x170 memsize: 0x170 Processing 16 relocs. Offset value of 0x00030000 Attempting to start 1 APs Waiting for 10ms after sending INIT. Waiting for 1st SIPI to complete...AP: slot 1 apic_id 11. done. Waiting for 2nd SIPI to complete...done. Loading module at 00038000 with entry 00038000. filesize: 0x1a8 memsize: 0x1a8 Processing 13 relocs. Offset value of 0x00038000 SMM Module: stub loaded at 00038000. Will call cdeb995b(00000000) Installing SMM handler to 0xce800000 Loading module at ce810000 with entry ce81142b. filesize: 0x6c98 memsize: 0xad18 Processing 481 relocs. Offset value of 0xce810000 Loading module at ce808000 with entry ce808000. filesize: 0x1a8 memsize: 0x1a8 Processing 13 relocs. Offset value of 0xce808000 SMM Module: placing jmp sequence at ce807e00 rel16 0x01fd SMM Module: stub loaded at ce808000. Will call ce81142b(00000000) New SMBASE 0xce800000 Relocation complete. New SMBASE 0xce7ffe00 Relocation complete. Initializing CPU #0 CPU: vendor AMD device 670f00 CPU: family 15, model 70, stepping 00 Setting up local APIC... apic_id: 0x10 done. CPU #0 initialized Initializing CPU #1 CPU: vendor AMD device 670f00 CPU: family 15, model 70, stepping 00 Setting up local APIC... apic_id: 0x11 done. CPU #1 initialized bsp_do_flight_plan done after 91 msecs. MTRR: TEMPORARY Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x00000000d0000000 size 0xcff40000 type 6 0x00000000d0000000 - 0x00000000ff000000 size 0x2f000000 type 0 0x00000000ff000000 - 0x0000000100000000 size 0x01000000 type 5 0x0000000100000000 - 0x000000012f000000 size 0x2f000000 type 6 MTRR: default type WB/UC MTRR counts: 7/5. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000ffff80000000 type 6 MTRR: 1 base 0x0000000080000000 mask 0x0000ffffc0000000 type 6 MTRR: 2 base 0x00000000c0000000 mask 0x0000fffff0000000 type 6 MTRR: 3 base 0x00000000ff000000 mask 0x0000ffffff000000 type 5 MTRR: 4 base 0x0000000100000000 mask 0x0000ffffc0000000 type 6 CPU_CLUSTER: 0 init finished in 345966 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 PCI: 00:00.0 init ... PCI: 00:00.0 init finished in 2002 usecs POST: 0x75 POST: 0x75 PCI: 00:01.0 init ... PCI: 00:01.0 init finished in 2002 usecs POST: 0x75 PCI: 00:01.1 init ... PCI: 00:01.1 init finished in 2002 usecs POST: 0x75 PCI: 00:02.0 init ... PCI: 00:02.0 init finished in 2002 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 PCI: 00:03.0 init ... PCI: 00:03.0 init finished in 2002 usecs POST: 0x75 PCI: 00:08.0 init ... PCI: 00:08.0 init finished in 2002 usecs POST: 0x75 PCI: 00:09.0 init ... PCI: 00:09.0 init finished in 2002 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 PCI: 00:14.0 init ... IOAPIC: Initializing IOAPIC at 0xfec00000 IOAPIC: Bootstrap Processor Local APIC = 0x10 IOAPIC: ID = 0x04 IOAPIC: Dumping registers reg 0x0000: 0x04000000 reg 0x0001: 0x00178021 reg 0x0002: 0x04000000 IOAPIC: 24 interrupts IOAPIC: Enabling interrupts on FSB IOAPIC: reg 0x00000000 value 0x10000000 0x00000700 IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 IOAPIC: reg 0x00000017 value 0x00000000 0x00010000 PCI: 00:14.0 init finished in 133954 usecs POST: 0x75 PCI: 00:14.3 init ... PCI: 00:14.3 init finished in 2061 usecs POST: 0x75 POST: 0x75 PCI: 00:18.0 init ... IOAPIC: Initializing IOAPIC at 0xfec20000 IOAPIC: Bootstrap Processor Local APIC = 0x10 IOAPIC: ID = 0x05 IOAPIC: Dumping registers reg 0x0000: 0x05000000 reg 0x0001: 0x001f8021 reg 0x0002: 0x00000000 IOAPIC: 32 interrupts IOAPIC: Enabling interrupts on FSB IOAPIC: reg 0x00000000 value 0x10000000 0x00000700 IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 IOAPIC: reg 0x00000017 value 0x00000000 0x00010000 IOAPIC: reg 0x00000018 value 0x00000000 0x00010000 IOAPIC: reg 0x00000019 value 0x00000000 0x00010000 IOAPIC: reg 0x0000001a value 0x00000000 0x00010000 IOAPIC: reg 0x0000001b value 0x00000000 0x00010000 IOAPIC: reg 0x0000001c value 0x00000000 0x00010000 IOAPIC: reg 0x0000001d value 0x00000000 0x00010000 IOAPIC: reg 0x0000001e value 0x00000000 0x00010000 IOAPIC: reg 0x0000001f value 0x00000000 0x00010000 PCI: 00:18.0 init finished in 170043 usecs POST: 0x75 PCI: 00:18.1 init ... PCI: 00:18.1 init finished in 2002 usecs POST: 0x75 PCI: 00:18.2 init ... PCI: 00:18.2 init finished in 2002 usecs POST: 0x75 PCI: 00:18.3 init ... PCI: 00:18.3 init finished in 2002 usecs POST: 0x75 PCI: 00:18.4 init ... PCI: 00:18.4 init finished in 2002 usecs POST: 0x75 PCI: 00:18.5 init ... PCI: 00:18.5 init finished in 2002 usecs POST: 0x75 PCI: 01:00.0 init ... PCI: 01:00.0 init finished in 2002 usecs POST: 0x75 PCI: 02:00.0 init ... BayHub BH720: Power-saving enabled (link_ctrl=0x110103) PCI: 02:00.0 init finished in 7127 usecs POST: 0x75 PNP: 0c09.0 init ... Google Chrome EC: Hello got back 11223344 status (0) Google Chrome EC: version: ro: careena_v2.0.11488-7215d6e0e4 rw: careena_v2.0.11488-7215d6e0e4 running image: 1 Google Chrome EC uptime: 109.040 seconds Google Chrome AP resets since EC boot: 0 Google Chrome most recent AP reset causes: Google Chrome EC reset flags at last EC boot: reset-pin PNP: 0c09.0 init finished in 34632 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 Devices initialized Show all devs... After init. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 DOMAIN: 0000: enabled 1 MMIO: fedc2000: enabled 1 MMIO: fedc3000: enabled 1 MMIO: fedc4000: enabled 1 MMIO: fedc5000: enabled 1 APIC: 10: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.2: enabled 0 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 0 PCI: 00:02.2: enabled 1 PCI: 00:02.3: enabled 0 PCI: 00:02.4: enabled 1 PCI: 00:02.5: enabled 0 PCI: 00:08.0: enabled 1 PCI: 00:09.0: enabled 1 PCI: 00:09.2: enabled 0 PCI: 00:10.0: enabled 0 PCI: 00:11.0: enabled 0 PCI: 00:12.0: enabled 0 PCI: 00:14.0: enabled 1 PCI: 00:14.3: enabled 1 PCI: 00:14.7: enabled 0 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 GENERIC: 0.0: enabled 1 I2C: 01:1a: enabled 1 GENERIC: 0.1: enabled 1 I2C: 02:50: enabled 1 I2C: 03:15: enabled 1 I2C: 04:39: enabled 1 I2C: 04:10: enabled 1 PCI: 02:00.0: enabled 1 PNP: 0c09.0: enabled 1 PCI: 00:03.0: enabled 1 PCI: 01:00.0: enabled 1 APIC: 11: enabled 1 BS: BS_DEV_INIT times (us): entry 0 run 948012 exit 141 ELOG: Event(A1) added with size 10 at 2023-08-09 04:54:58 UTC elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x2b POST: 0x76 Finalize devices... Devices finalized FMAP: area RW_NVRAM found @ 467000 (20480 bytes) BS: BS_POST_DEVICE times (us): entry 12905 run 4545 exit 4695 FMAP: area RW_MRC_CACHE found @ 0 (65536 bytes) MRC: Checking cached data update for 'RW_MRC_CACHE'. POST: 0x77 Trying to find the wakeup vector... Looking on 000f0000 for valid checksum Checksum 1 passed Checksum 2 passed all OK RSDP found at 000f0000 RSDT found at cde2e030 ends at cde2e07c FADT found at cde31e60 FACS found at cde2e240 OS waking vector is 0009a1d0 BS: BS_OS_RESUME_CHECK times (us): entry 9571 run 24119 exit 0 agesawrapper_amds3finalrestore() entry S3 volatile data @0xceebe000 0x4160 total bytes agesawrapper_amds3finalrestore() returned AGESA_SUCCESS Lock SMM configuration POST: 0xfe Probing TPM I2C: done! DID_VID 0x00281ae0 Locality already claimed cr50 TPM 2.0 (i2c 1:0x50 id 0x28) Platform hierarchy disablement failed: 5001 POST: 0x78 mp_park_aps done after 0 msecs. Restore GNVS pointer to cde6b000 smm_setup_structures STUB!!! POST: 0xfd <6>[ 18.655815] ACPI: EC: interrupt blocked <6>[ 18.680058] ACPI: Preparing to enter system sleep state S3 <6>[ 18.680845] ACPI: EC: event blocked <6>[ 18.680846] ACPI: EC: EC stopped <6>[ 18.680847] PM: Saving platform NVS memory <6>[ 18.680849] Disabling non-boot CPUs ... <6>[ 18.682269] smpboot: CPU 1 is now offline <6>[ 18.682702] ACPI: Low-level resume complete <6>[ 18.682719] ACPI: EC: EC started <6>[ 18.682719] PM: Restoring platform NVS memory <6>[ 18.682736] LVT offset 0 assigned for vector 0x400 <6>[ 18.682994] Enabling non-boot CPUs ... <6>[ 18.683029] x86: Booting SMP configuration: <6>[ 18.683030] smpboot: Booting Node 0 Processor 1 APIC 0x11 <6>[ 18.683184] microcode: CPU1: patch_level=0x06006705 <6>[ 18.685513] ACPI: \_PR_.P001: Found 2 idle states <6>[ 18.685741] CPU1 is up <6>[ 18.686042] ACPI: Waking up from system sleep state S3 <6>[ 18.713686] ACPI: EC: interrupt unblocked <6>[ 18.739653] ACPI: EC: event unblocked <6>[ 18.740349] [drm] PCIE GART of 1024M enabled (table at 0x000000F400000000). <6>[ 18.740364] amdgpu: smu version 33.09.00 <6>[ 19.006786] usb 1-1.1: reset high-speed USB device number 3 using ehci-pci <6>[ 19.013925] r8152 2-4:1.0 eth0: carrier on <6>[ 19.427177] [drm] UVD initialized successfully. <6>[ 19.528332] [drm] VCE initialized successfully. <6>[ 19.652499] OOM killer enabled. <6>[ 19.655897] Restarting tasks ... done. <6>[ 19.669441] PM: suspend exit rtcwake: assuming RTC uses UTC ... rtcwake: wakeup from "mem" using rtc0 at Wed Aug 9 04:55:05 2023 <6>[ 19.696312] PM: suspend entry (deep) <6>[ 19.700187] Filesystems sync: 0.000 seconds <6>[ 19.704785] Freezing user space processes ... (elapsed 0.001 seconds) done. <6>[ 19.713954] OOM killer disabled. <6>[ 19.717439] Freezing remaining freezable tasks ... (elapsed 1.092 seconds) done. <6>[ 20.835234] printk: Suspending console(s) (use no_console_suspend to debug) coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 smm starting... SMI# #0 SMI#: SLP = 0x0c01 Chrome EC: UHEPI supported Chrome EC: Set SMI mask to 0x0000000000000000 Chrome EC: Set SCI mask to 0x0000000000000000 Clearing pending EC events. Error code 1 is expected. EC returned error result code 9 SMI#: Entering S3 (Suspend-To-RAM) FMAP: Found "FLASH" version 1.1 at d7f000. FMAP: base = ff000000 size = 1000000 #areas = 30 FMAP: area RW_ELOG found @ 45d000 (16384 bytes) Manufacturer: ef SF: Detected W25Q128FW with sector size 0x1000, total 0x1000000 ELOG: NV offset 0x45d000 size 0x4000 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024 ELOG: Event(9D) added with size 10 at 2023-08-09 04:55:00 UTC coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 bootblock starting... Family_Model: 00670f00 PMxC0 STATUS: 0x40200800 BIT30 SleepReset BIT11 DW I2C bus 1 at 0xfedc3000 (400 KHz) VBOOT: Loading verstage. CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'fallback/verstage' CBFS: Found @ offset aa8c0 size d5a4 coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 verstage starting... Probing TPM I2C: done! DID_VID 0x00281ae0 TPM ready after 0 ms cr50 TPM 2.0 (i2c 1:0x50 id 0x28) tlcl_send_startup: Startup return code is 84 src/security/tpm/tss/tcg-2.0/tss.c:177 index 0x1007 return code 100 read_space_firmware():99: Antirollback: 0000500a returned by tlcl_read(FIRMWARE_NV_INDEX, ctx->secdata, VB2_SECDATA_SIZE) antirollback_read_space_firmware():474: TPM: Firmware space in a bad state; giving up. Chrome EC: UHEPI supported Phase 1 VB2:vb2_fail() Need recovery, reason: 0x2b / 0x2 FMAP: Found "FLASH" version 1.1 at d7f000. FMAP: base = ff000000 size = 1000000 #areas = 30 FMAP: area GBB found @ d80000 (458752 bytes) VB2:vb2_check_recovery() Recovery reason from previous boot: 0x2b / 0x2 VB2:vb2_check_recovery() We have a recovery request: 0x2b / 0x0 Clearing TPM owner TPM: Clear and re-enable tlcl_force_clear: response is 100 TPM: Can't initiate a force clear. Recovery requested (1009000e) Saving nvdata tlcl_extend: response is 100 CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'fallback/romstage' CBFS: Found @ offset 80 size d2e4 coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 romstage starting... CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'smu_fw' CBFS: Found @ offset 7bc00 size 12262 PSP: Load blob type 19 from @ffe6bc38... OK POST: 0x37 agesawrapper_amdinitreset() entry CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'AGESA_PRE_MEM' CBFS: Found @ offset df80 size 53bcc agesawrapper_amdinitreset() returned AGESA_SUCCESS POST: 0x38 agesawrapper_amdinitearly() entry Warning - AGESA callout: platform_PcieSlotResetControl not supported Warning - AGESA callout: platform_PcieSlotResetControl not supported agesawrapper_amdinitearly() returned AGESA_SUCCESS S3 detected POST: 0x60 agesawrapper_amdinitresume() entry Chrome EC: UHEPI supported FMAP: Found "FLASH" version 1.1 at d7f000. FMAP: base = ff000000 size = 1000000 #areas = 30 FMAP: area RW_MRC_CACHE found @ 0 (65536 bytes) S3 NV data @0xff0048c0, 0xe65 bytes agesawrapper_amdinitresume() returned AGESA_SUCCESS POST: 0x61 POST: 0x42 PSP: Notify that DRAM is available... OK POST: 0x43 creating vboot_handoff structure Chrome EC: clear events_b mask to 0x0000000021004000 POST: 0x44 MTRR Range: Start=cd000000 End=ce000000 (Size 1000000) MTRR Range: Start=ff000000 End=0 (Size 1000000) MTRR Range: Start=ce800000 End=cf000000 (Size 800000) POST: 0x45 coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 postcar starting... Jumping to image. coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 ramstage starting... POST: 0x39 FMAP: Found "FLASH" version 1.1 at d7f000. FMAP: base = ff000000 size = 1000000 #areas = 30 FMAP: area RO_VPD found @ c00000 (16384 bytes) WARNING: RO_VPD is uninitialized or empty. FMAP: area RW_VPD found @ 465000 (8192 bytes) FMAP: area RW_VPD found @ 465000 (8192 bytes) POST: 0x80 S3 Resume. POST: 0x46 agesawrapper_amds3laterestore() entry AGESA: Loading stage from cache S3 volatile data @0xceebe000 0x4160 total bytes agesawrapper_amds3laterestore() returned AGESA_SUCCESS POST: 0x70 BS: BS_PRE_DEVICE times (us): entry 20056 run 1061 exit 0 POST: 0x71 Board ID: 6 mainboard: EC init Chrome EC: Set SMI mask to 0x0000000000000000 Chrome EC: UHEPI supported Chrome EC: Set SCI mask to 0x00000000142609fb Chrome EC: Set WAKE mask to 0x0000000000000000 DW I2C bus 0 at 0xfedc2000 (400 KHz) DW I2C bus 2 at 0xfedc4000 (400 KHz) DW I2C bus 3 at 0xfedc5000 (400 KHz) FMAP: area RW_ELOG found @ 45d000 (16384 bytes) Manufacturer: ef SF: Detected W25Q128FW with sector size 0x1000, total 0x1000000 ELOG: NV offset 0x45d000 size 0x4000 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024 ELOG: Event(9E) added with size 10 at 2023-08-09 04:55:05 UTC ELOG: Event(9F) added with size 14 at 2023-08-09 04:55:05 UTC PM1_STS: WAK RTC BMSTATUS setup_bsp_ramtop, TOP MEM: msr.lo = 0xd0000000, msr.hi = 0x00000000 setup_bsp_ramtop, TOP MEM2: msr.lo = 0x2f000000, msr.hi = 0x00000001 BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 80251 exit 0 POST: 0x72 Enumerating buses... Show all devs... Before device enumeration. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 DOMAIN: 0000: enabled 1 MMIO: fedc2000: enabled 1 MMIO: fedc3000: enabled 1 MMIO: fedc4000: enabled 1 MMIO: fedc5000: enabled 1 APIC: 10: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.2: enabled 0 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 1 PCI: 00:02.2: enabled 1 PCI: 00:02.3: enabled 1 PCI: 00:02.4: enabled 1 PCI: 00:02.5: enabled 1 PCI: 00:08.0: enabled 1 PCI: 00:09.0: enabled 1 PCI: 00:09.2: enabled 1 PCI: 00:10.0: enabled 1 PCI: 00:11.0: enabled 0 PCI: 00:12.0: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:14.3: enabled 1 PCI: 00:14.7: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 GENERIC: 0.0: enabled 1 I2C: 00:1a: enabled 1 GENERIC: 0.1: enabled 1 I2C: 00:50: enabled 1 I2C: 00:15: enabled 1 I2C: 00:39: enabled 1 I2C: 00:10: enabled 1 PCI: 00:00.0: enabled 1 PNP: 0c09.0: enabled 1 Compare with tree... Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 10: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.2: enabled 0 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 1 PCI: 00:02.2: enabled 1 PCI: 00:02.3: enabled 1 PCI: 00:02.4: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:02.5: enabled 1 PCI: 00:08.0: enabled 1 PCI: 00:09.0: enabled 1 PCI: 00:09.2: enabled 1 PCI: 00:10.0: enabled 1 PCI: 00:11.0: enabled 0 PCI: 00:12.0: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:14.3: enabled 1 PNP: 0c09.0: enabled 1 PCI: 00:14.7: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 MMIO: fedc2000: enabled 1 GENERIC: 0.0: enabled 1 I2C: 00:1a: enabled 1 GENERIC: 0.1: enabled 1 MMIO: fedc3000: enabled 1 I2C: 00:50: enabled 1 MMIO: fedc4000: enabled 1 I2C: 00:15: enabled 1 MMIO: fedc5000: enabled 1 I2C: 00:39: enabled 1 I2C: 00:10: enabled 1 Mainboard Grunt Enable. Root Device scanning... root_dev_scan_bus for Root Device CPU_CLUSTER: 0 enabled DOMAIN: 0000 enabled MMIO: fedc2000 enabled MMIO: fedc3000 enabled MMIO: fedc4000 enabled MMIO: fedc5000 enabled DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 POST: 0x24 sb_enable PCI: 00:00.0 [1022/1576] enabled sb_enable sb_enable PCI: 00:01.0 [1002/98e4] enabled sb_enable PCI: 00:01.1 [1002/15b3] enabled sb_enable PCI: 00:02.0 [1022/157b] enabled sb_enable PCI: Static device PCI: 00:02.1 not found, disabling it. sb_enable Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xc0 Capability: type 0x08 @ 0xc8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 PCI: 00:02.2 subordinate bus PCI Express PCI: 00:02.2 [1022/157c] enabled sb_enable PCI: Static device PCI: 00:02.3 not found, disabling it. sb_enable Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xc0 Capability: type 0x08 @ 0xc8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 PCI: 00:02.4 subordinate bus PCI Express PCI: 00:02.4 [1022/157c] enabled sb_enable PCI: Static device PCI: 00:02.5 not found, disabling it. PCI: 00:03.0 [1022/157b] enabled sb_enable PCI: 00:08.0 [1022/1578] enabled sb_enable PCI: 00:09.0 [1022/157d] enabled sb_enable PCI: Static device PCI: 00:09.2 not found, disabling it. sb_enable PCI: Static device PCI: 00:10.0 not found, disabling it. sb_enable sb_enable PCI: Static device PCI: 00:12.0 not found, disabling it. sb_enable PCI: 00:14.0 [1022/790b] bus ops PCI: 00:14.0 [1022/790b] enabled sb_enable PCI: 00:14.3 [1022/0000] bus ops PCI: 00:14.3 [1022/790e] enabled sb_enable PCI: Static device PCI: 00:14.7 not found, disabling it. sb_enable PCI: 00:18.0 [1022/15b0] ops PCI: 00:18.0 [1022/15b0] enabled sb_enable PCI: 00:18.1 [1022/15b1] enabled sb_enable PCI: 00:18.2 [1022/15b2] enabled sb_enable PCI: 00:18.3 [1022/15b3] enabled sb_enable PCI: 00:18.4 [1022/15b4] enabled sb_enable PCI: 00:18.5 [1022/15b5] enabled POST: 0x25 PCI: 00:02.2 scanning... do_pci_scan_bridge for PCI: 00:02.2 PCI: pci_scan_bus for bus 01 POST: 0x24 PCI: 01:00.0 [168c/003e] enabled POST: 0x25 POST: 0x55 Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x50 Capability: type 0x10 @ 0x70 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Enabling Common Clock Configuration ASPM: Enabled L0s and L1 Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x50 Capability: type 0x10 @ 0x70 scan_bus: scanning of bus PCI: 00:02.2 took 40758 usecs PCI: 00:02.4 scanning... do_pci_scan_bridge for PCI: 00:02.4 PCI: pci_scan_bus for bus 02 POST: 0x24 PCI: 02:00.0 [1217/0000] ops PCI: 02:00.0 [1217/8620] enabled POST: 0x25 POST: 0x55 Capability: type 0x01 @ 0x6c Capability: type 0x05 @ 0x48 Capability: type 0x10 @ 0x80 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 ASPM: Enabled L0s and L1 Capability: type 0x01 @ 0x6c Capability: type 0x05 @ 0x48 Capability: type 0x10 @ 0x80 scan_bus: scanning of bus PCI: 00:02.4 took 40398 usecs PCI: 00:14.0 scanning... scan_generic_bus for PCI: 00:14.0 scan_generic_bus for PCI: 00:14.0 done scan_bus: scanning of bus PCI: 00:14.0 took 8804 usecs PCI: 00:14.3 scanning... scan_lpc_bus for PCI: 00:14.3 PNP: 0c09.0 enabled scan_lpc_bus for PCI: 00:14.3 done scan_bus: scanning of bus PCI: 00:14.3 took 9940 usecs POST: 0x55 scan_bus: scanning of bus DOMAIN: 0000 took 289508 usecs MMIO: fedc2000 scanning... scan_generic_bus for MMIO: fedc2000 bus: MMIO: fedc2000[0]->GENERIC: 0.0 enabled bus: MMIO: fedc2000[0]->I2C: 01:1a enabled bus: MMIO: fedc2000[0]->GENERIC: 0.1 enabled scan_generic_bus for MMIO: fedc2000 done scan_bus: scanning of bus MMIO: fedc2000 took 21205 usecs MMIO: fedc3000 scanning... scan_generic_bus for MMIO: fedc3000 bus: MMIO: fedc3000[0]->I2C: 02:50 enabled scan_generic_bus for MMIO: fedc3000 done scan_bus: scanning of bus MMIO: fedc3000 took 13162 usecs MMIO: fedc4000 scanning... scan_generic_bus for MMIO: fedc4000 bus: MMIO: fedc4000[0]->I2C: 03:15 enabled scan_generic_bus for MMIO: fedc4000 done scan_bus: scanning of bus MMIO: fedc4000 took 13159 usecs MMIO: fedc5000 scanning... scan_generic_bus for MMIO: fedc5000 bus: MMIO: fedc5000[0]->I2C: 04:39 enabled bus: MMIO: fedc5000[0]->I2C: 04:10 enabled scan_generic_bus for MMIO: fedc5000 done scan_bus: scanning of bus MMIO: fedc5000 took 16986 usecs root_dev_scan_bus for Root Device done scan_bus: scanning of bus Root Device took 400633 usecs done BS: BS_DEV_ENUMERATE times (us): entry 0 run 605645 exit 0 POST: 0x73 found VGA at PCI: 00:01.0 Setting up VGA for PCI: 00:01.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done DOMAIN: 0000 read_resources bus 0 link: 0 PCI: 00:02.2 read_resources bus 1 link: 0 PCI: 00:02.2 read_resources bus 1 link: 0 done PCI: 00:02.4 read_resources bus 2 link: 0 PCI: 00:02.4 read_resources bus 2 link: 0 done PCI: 00:14.3 read_resources bus 0 link: 0 PCI: 00:14.3 read_resources bus 0 link: 0 done Adding PCIe enhanced config space BAR 0xf8000000-0xfc000000. DOMAIN: 0000 read_resources bus 0 link: 0 done MMIO: fedc2000 read_resources bus 1 link: 0 MMIO: fedc2000 read_resources bus 1 link: 0 done MMIO: fedc3000 read_resources bus 2 link: 0 MMIO: fedc3000 read_resources bus 2 link: 0 done MMIO: fedc4000 read_resources bus 3 link: 0 MMIO: fedc4000 read_resources bus 3 link: 0 done MMIO: fedc5000 read_resources bus 4 link: 0 MMIO: fedc5000 read_resources bus 4 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 10 APIC: 10 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI: 00:00.0 PCI: 00:00.2 PCI: 00:01.0 PCI: 00:01.0 resource base 0 size 4000000 align 26 gran 26 limit ffffffffffffffff flags 1201 index 10 PCI: 00:01.0 resource base 0 size 800000 align 23 gran 23 limit ffffffffffffffff flags 1201 index 18 PCI: 00:01.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 20 PCI: 00:01.0 resource base 0 size 40000 align 18 gran 18 limit ffffffff flags 200 index 24 PCI: 00:01.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 2200 index 30 PCI: 00:01.1 PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 PCI: 00:02.0 PCI: 00:02.1 PCI: 00:02.2 child on link 0 PCI: 01:00.0 PCI: 00:02.2 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:02.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:02.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 01:00.0 PCI: 01:00.0 resource base 0 size 200000 align 21 gran 21 limit ffffffffffffffff flags 201 index 10 PCI: 00:02.3 PCI: 00:02.4 child on link 0 PCI: 02:00.0 PCI: 00:02.4 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:02.4 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:02.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 02:00.0 PCI: 02:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 02:00.0 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 14 PCI: 00:02.5 PCI: 00:03.0 PCI: 00:08.0 PCI: 00:08.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 1201 index 10 PCI: 00:08.0 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 200 index 18 PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 1c PCI: 00:08.0 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 200 index 20 PCI: 00:08.0 resource base 0 size 2000 align 13 gran 13 limit ffffffff flags 200 index 24 PCI: 00:09.0 PCI: 00:09.2 PCI: 00:10.0 PCI: 00:11.0 PCI: 00:12.0 PCI: 00:14.0 PCI: 00:14.3 child on link 0 PNP: 0c09.0 PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:14.3 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100 PCI: 00:14.3 resource base fec10000 size 400 align 0 gran 0 limit 0 flags e0040200 index 2 PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PCI: 00:14.3 resource base fedc2000 size 4000 align 0 gran 0 limit 0 flags c0000200 index 4 PNP: 0c09.0 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0 PCI: 00:14.7 PCI: 00:18.0 PCI: 00:18.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI: 00:18.0 resource base fec20000 size 1000 align 0 gran 0 limit 0 flags c0000200 index fec20000 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.4 PCI: 00:18.5 MMIO: fedc2000 child on link 0 GENERIC: 0.0 GENERIC: 0.0 I2C: 01:1a GENERIC: 0.1 MMIO: fedc3000 child on link 0 I2C: 02:50 I2C: 02:50 MMIO: fedc4000 child on link 0 I2C: 03:15 I2C: 03:15 MMIO: fedc5000 child on link 0 I2C: 04:39 I2C: 04:39 I2C: 04:10 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:02.2 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:02.2 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:02.4 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:02.4 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:01.0 20 * [0x0 - 0xff] io DOMAIN: 0000 io: base: 100 size: 100 align: 8 gran: 0 limit: ffff done DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:02.2 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:02.2 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:02.2 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 01:00.0 10 * [0x0 - 0x1fffff] mem PCI: 00:02.2 mem: base: 200000 size: 200000 align: 21 gran: 20 limit: ffffffff done PCI: 00:02.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:02.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:02.4 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 02:00.0 10 * [0x0 - 0xfff] mem PCI: 02:00.0 14 * [0x1000 - 0x17ff] mem PCI: 00:02.4 mem: base: 1800 size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:01.0 10 * [0x0 - 0x3ffffff] prefmem PCI: 00:01.0 18 * [0x4000000 - 0x47fffff] prefmem PCI: 00:02.2 20 * [0x4800000 - 0x49fffff] mem PCI: 00:02.4 20 * [0x4a00000 - 0x4afffff] mem PCI: 00:08.0 18 * [0x4b00000 - 0x4bfffff] mem PCI: 00:08.0 20 * [0x4c00000 - 0x4cfffff] mem PCI: 00:01.0 24 * [0x4d00000 - 0x4d3ffff] mem PCI: 00:01.0 30 * [0x4d40000 - 0x4d5ffff] mem PCI: 00:08.0 10 * [0x4d60000 - 0x4d7ffff] prefmem PCI: 00:01.1 10 * [0x4d80000 - 0x4d83fff] mem PCI: 00:08.0 24 * [0x4d84000 - 0x4d85fff] mem PCI: 00:08.0 1c * [0x4d86000 - 0x4d86fff] mem DOMAIN: 0000 mem: base: 4d87000 size: 4d87000 align: 26 gran: 0 limit: ffffffff done avoid_fixed_resources: DOMAIN: 0000 avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI: 00:14.3 10000000 base 00000000 limit 00000fff io (fixed) constrain_resources: PCI: 00:14.3 10000100 base ff000000 limit ffffffff mem (fixed) constrain_resources: PCI: 00:14.3 02 base fec10000 limit fec103ff mem (fixed) constrain_resources: PCI: 00:14.3 03 base fec00000 limit fec00fff mem (fixed) constrain_resources: PCI: 00:18.0 c0010058 base f8000000 limit fbffffff mem (fixed) avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001000 limit 0000ffff avoid_fixed_resources:@DOMAIN: 0000 10000100 base f0000000 limit f7ffffff Setting resources... DOMAIN: 0000 io: base:1000 size:100 align:8 gran:0 limit:ffff PCI: 00:01.0 20 * [0x1000 - 0x10ff] io DOMAIN: 0000 io: next_base: 1100 size: 100 align: 8 gran: 0 done PCI: 00:02.2 io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:02.2 io: next_base: ffff size: 0 align: 12 gran: 12 done PCI: 00:02.4 io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:02.4 io: next_base: ffff size: 0 align: 12 gran: 12 done DOMAIN: 0000 mem: base:f0000000 size:4d87000 align:26 gran:0 limit:f7ffffff PCI: 00:01.0 10 * [0xf0000000 - 0xf3ffffff] prefmem PCI: 00:01.0 18 * [0xf4000000 - 0xf47fffff] prefmem PCI: 00:02.2 20 * [0xf4800000 - 0xf49fffff] mem PCI: 00:02.4 20 * [0xf4a00000 - 0xf4afffff] mem PCI: 00:08.0 18 * [0xf4b00000 - 0xf4bfffff] mem PCI: 00:08.0 20 * [0xf4c00000 - 0xf4cfffff] mem PCI: 00:01.0 24 * [0xf4d00000 - 0xf4d3ffff] mem PCI: 00:01.0 30 * [0xf4d40000 - 0xf4d5ffff] mem PCI: 00:08.0 10 * [0xf4d60000 - 0xf4d7ffff] prefmem PCI: 00:01.1 10 * [0xf4d80000 - 0xf4d83fff] mem PCI: 00:08.0 24 * [0xf4d84000 - 0xf4d85fff] mem PCI: 00:08.0 1c * [0xf4d86000 - 0xf4d86fff] mem DOMAIN: 0000 mem: next_base: f4d87000 size: 4d87000 align: 26 gran: 0 done PCI: 00:02.2 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff PCI: 00:02.2 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done PCI: 00:02.2 mem: base:f4800000 size:200000 align:21 gran:20 limit:f49fffff PCI: 01:00.0 10 * [0xf4800000 - 0xf49fffff] mem PCI: 00:02.2 mem: next_base: f4a00000 size: 200000 align: 21 gran: 20 done PCI: 00:02.4 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff PCI: 00:02.4 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done PCI: 00:02.4 mem: base:f4a00000 size:100000 align:20 gran:20 limit:f4afffff PCI: 02:00.0 10 * [0xf4a00000 - 0xf4a00fff] mem PCI: 02:00.0 14 * [0xf4a01000 - 0xf4a017ff] mem PCI: 00:02.4 mem: next_base: f4a01800 size: 100000 align: 20 gran: 20 done Root Device assign_resources, bus 0 link: 0 DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:01.0 10 <- [0x00f0000000 - 0x00f3ffffff] size 0x04000000 gran 0x1a prefmem64 PCI: 00:01.0 18 <- [0x00f4000000 - 0x00f47fffff] size 0x00800000 gran 0x17 prefmem64 PCI: 00:01.0 20 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io PCI: 00:01.0 24 <- [0x00f4d00000 - 0x00f4d3ffff] size 0x00040000 gran 0x12 mem PCI: 00:01.0 30 <- [0x00f4d40000 - 0x00f4d5ffff] size 0x00020000 gran 0x11 romem PCI: 00:01.1 10 <- [0x00f4d80000 - 0x00f4d83fff] size 0x00004000 gran 0x0e mem64 PCI: 00:02.2 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io PCI: 00:02.2 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 01 prefmem PCI: 00:02.2 20 <- [0x00f4800000 - 0x00f49fffff] size 0x00200000 gran 0x14 bus 01 mem PCI: 00:02.2 assign_resources, bus 1 link: 0 PCI: 01:00.0 10 <- [0x00f4800000 - 0x00f49fffff] size 0x00200000 gran 0x15 mem64 PCI: 00:02.2 assign_resources, bus 1 link: 0 PCI: 00:02.4 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io PCI: 00:02.4 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 02 prefmem PCI: 00:02.4 20 <- [0x00f4a00000 - 0x00f4afffff] size 0x00100000 gran 0x14 bus 02 mem PCI: 00:02.4 assign_resources, bus 2 link: 0 PCI: 02:00.0 10 <- [0x00f4a00000 - 0x00f4a00fff] size 0x00001000 gran 0x0c mem PCI: 02:00.0 14 <- [0x00f4a01000 - 0x00f4a017ff] size 0x00000800 gran 0x0b mem PCI: 00:02.4 assign_resources, bus 2 link: 0 PCI: 00:08.0 10 <- [0x00f4d60000 - 0x00f4d7ffff] size 0x00020000 gran 0x11 prefmem64 PCI: 00:08.0 18 <- [0x00f4b00000 - 0x00f4bfffff] size 0x00100000 gran 0x14 mem PCI: 00:08.0 1c <- [0x00f4d86000 - 0x00f4d86fff] size 0x00001000 gran 0x0c mem PCI: 00:08.0 20 <- [0x00f4c00000 - 0x00f4cfffff] size 0x00100000 gran 0x14 mem PCI: 00:08.0 24 <- [0x00f4d84000 - 0x00f4d85fff] size 0x00002000 gran 0x0d mem PCI: 00:14.3 assign_resources, bus 0 link: 0 PCI: 00:14.3 assign_resources, bus 0 link: 0 DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 10 APIC: 10 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 1000 size 100 align 8 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base f0000000 size 4d87000 align 26 gran 0 limit f7ffffff flags 40040200 index 10000100 DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10 DOMAIN: 0000 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11 DOMAIN: 0000 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12 DOMAIN: 0000 resource base 100000 size cdf00000 align 0 gran 0 limit 0 flags e0004200 index 13 DOMAIN: 0000 resource base ce000000 size 2000000 align 0 gran 0 limit 0 flags f0004200 index 14 DOMAIN: 0000 resource base 100000000 size 2f000000 align 0 gran 0 limit 0 flags e0004200 index 15 PCI: 00:00.0 PCI: 00:00.2 PCI: 00:01.0 PCI: 00:01.0 resource base f0000000 size 4000000 align 26 gran 26 limit f3ffffff flags 60001201 index 10 PCI: 00:01.0 resource base f4000000 size 800000 align 23 gran 23 limit f47fffff flags 60001201 index 18 PCI: 00:01.0 resource base 1000 size 100 align 8 gran 8 limit 10ff flags 60000100 index 20 PCI: 00:01.0 resource base f4d00000 size 40000 align 18 gran 18 limit f4d3ffff flags 60000200 index 24 PCI: 00:01.0 resource base f4d40000 size 20000 align 17 gran 17 limit f4d5ffff flags 60002200 index 30 PCI: 00:01.1 PCI: 00:01.1 resource base f4d80000 size 4000 align 14 gran 14 limit f4d83fff flags 60000201 index 10 PCI: 00:02.0 PCI: 00:02.1 PCI: 00:02.2 child on link 0 PCI: 01:00.0 PCI: 00:02.2 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:02.2 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24 PCI: 00:02.2 resource base f4800000 size 200000 align 21 gran 20 limit f49fffff flags 60080202 index 20 PCI: 01:00.0 PCI: 01:00.0 resource base f4800000 size 200000 align 21 gran 21 limit f49fffff flags 60000201 index 10 PCI: 00:02.3 PCI: 00:02.4 child on link 0 PCI: 02:00.0 PCI: 00:02.4 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:02.4 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24 PCI: 00:02.4 resource base f4a00000 size 100000 align 20 gran 20 limit f4afffff flags 60080202 index 20 PCI: 02:00.0 PCI: 02:00.0 resource base f4a00000 size 1000 align 12 gran 12 limit f4a00fff flags 60000200 index 10 PCI: 02:00.0 resource base f4a01000 size 800 align 12 gran 11 limit f4a017ff flags 60000200 index 14 PCI: 00:02.5 PCI: 00:03.0 PCI: 00:08.0 PCI: 00:08.0 resource base f4d60000 size 20000 align 17 gran 17 limit f4d7ffff flags 60001201 index 10 PCI: 00:08.0 resource base f4b00000 size 100000 align 20 gran 20 limit f4bfffff flags 60000200 index 18 PCI: 00:08.0 resource base f4d86000 size 1000 align 12 gran 12 limit f4d86fff flags 60000200 index 1c PCI: 00:08.0 resource base f4c00000 size 100000 align 20 gran 20 limit f4cfffff flags 60000200 index 20 PCI: 00:08.0 resource base f4d84000 size 2000 align 13 gran 13 limit f4d85fff flags 60000200 index 24 PCI: 00:09.0 PCI: 00:09.2 PCI: 00:10.0 PCI: 00:11.0 PCI: 00:12.0 PCI: 00:14.0 PCI: 00:14.3 child on link 0 PNP: 0c09.0 PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:14.3 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100 PCI: 00:14.3 resource base fec10000 size 400 align 0 gran 0 limit 0 flags e0040200 index 2 PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PCI: 00:14.3 resource base fedc2000 size 4000 align 0 gran 0 limit 0 flags c0000200 index 4 PNP: 0c09.0 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0 PCI: 00:14.7 PCI: 00:18.0 PCI: 00:18.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI: 00:18.0 resource base fec20000 size 1000 align 0 gran 0 limit 0 flags c0000200 index fec20000 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.4 PCI: 00:18.5 MMIO: fedc2000 child on link 0 GENERIC: 0.0 GENERIC: 0.0 I2C: 01:1a GENERIC: 0.1 MMIO: fedc3000 child on link 0 I2C: 02:50 I2C: 02:50 MMIO: fedc4000 child on link 0 I2C: 03:15 I2C: 03:15 MMIO: fedc5000 child on link 0 I2C: 04:39 I2C: 04:39 I2C: 04:10 Done allocating resources. BS: BS_DEV_RESOURCES times (us): entry 0 run 1463876 exit 0 PCI_INTR tables: Writing registers C00/C01 for PCI IRQ routing: PCI_INTR_INDEX name PIC mode APIC mode 0x00 INTA# 0x03 0x10 0x01 INTB# 0x04 0x11 0x02 INTC# 0x05 0x12 0x03 INTD# 0x07 0x13 0x04 INTE# 0x0B 0x14 0x05 INTF# 0x1F 0x1F 0x06 INTG# 0x1F 0x16 0x07 INTH# 0x1F 0x17 0x08 Misc 0xFA 0x00 0x09 Misc0 0xF1 0x00 0x0A Misc1 0x00 0x00 0x0B Misc2 0x00 0x00 0x0C Ser IRQ INTA 0x1F 0x1F 0x0D Ser IRQ INTB 0x1F 0x1F 0x0E Ser IRQ INTC 0x1F 0x1F 0x0F Ser IRQ INTD 0x1F 0x1F 0x10 SCI 0x09 0x09 0x11 SMBUS 0x1F 0x1F 0x12 ASF 0x1F 0x1F 0x13 HDA 0x03 0x10 0x14 FC 0x1F 0x1F 0x16 PerMon 0x1F 0x1F 0x17 SD 0x03 0x10 0x1A SDIOt 0x00 0x1F 0x30 EHCI 0x05 0x12 0x34 XHCI 0x04 0x12 0x41 SATA 0x07 0x13 0x62 GPIO 0x07 0x07 0x70 I2C0 0x03 0x03 0x71 I2C1 0x0F 0x0F 0x72 I2C2 0x06 0x06 0x73 I2C3 0x0E 0x0E 0x74 UART0 0x0A 0x0A 0x75 UART1 0x0B 0x0B PCI_CFG IRQ: Write PCI config space IRQ assignments PCI IRQ: Found device 0:01.00 using PIN A PCI Devfn (0x8) not found in pirq_data table PCI IRQ: Found device 0:01.01 using PIN B Found this device in pirq_data table entry 5 Orig INT_PIN : 2 (PIN B) PCI_INTR idx : 0x13 (HDA) INT_LINE : 0x3 (IRQ 3) PCI IRQ: Found device 0:02.02 using PIN A Found this device in pirq_data table entry 1 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x01 (INTB#) INT_LINE : 0x4 (IRQ 4) PCI IRQ: Found device 0:02.04 using PIN A Found this device in pirq_data table entry 3 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x03 (INTD#) INT_LINE : 0x7 (IRQ 7) PCI IRQ: Found device 0:08.00 using PIN A PCI Devfn (0x40) not found in pirq_data table PCI IRQ: Found device 2:00.00 using PIN A With INT_PIN swizzled to PIN A Attached to bridge device 0:02h.04h Found this device in pirq_data table entry 3 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x03 (INTD#) INT_LINE : 0x7 (IRQ 7) PCI IRQ: Found device 1:00.00 using PIN A With INT_PIN swizzled to PIN A Attached to bridge device 0:02h.02h Found this device in pirq_data table entry 1 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x01 (INTB#) INT_LINE : 0x4 (IRQ 4) PCI_CFG IRQ: Finished writing PCI config space IRQ assignments POST: 0x74 Enabling resources... PCI: 00:00.0 subsystem <- 1022/1576 PCI: 00:00.0 cmd <- 04 PCI: 00:01.0 subsystem <- 1002/98e4 PCI: 00:01.0 cmd <- 07 PCI: 00:01.1 subsystem <- 1002/15b3 PCI: 00:01.1 cmd <- 02 PCI: 00:02.0 subsystem <- 1022/157b PCI: 00:02.0 cmd <- 00 PCI: 00:02.2 bridge ctrl <- 0003 PCI: 00:02.2 cmd <- 06 PCI: 00:02.4 bridge ctrl <- 0003 PCI: 00:02.4 cmd <- 06 PCI: 00:03.0 cmd <- 00 PCI: 00:08.0 subsystem <- 1022/1578 PCI: 00:08.0 cmd <- 06 PCI: 00:09.0 subsystem <- 1022/157d PCI: 00:09.0 cmd <- 00 PCI: 00:14.0 subsystem <- 1022/790b PCI: 00:14.0 cmd <- 403 PCI: 00:14.3 subsystem <- 1022/790e PCI: 00:14.3 cmd <- 0f Southbridge LPC decode:PNP: 0c09.0, base=0x00000800, end=0x000009fe Covered by wideIO 0 PCI: 00:18.0 cmd <- 00 PCI: 00:18.1 subsystem <- 1022/15b1 PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 subsystem <- 1022/15b2 PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 subsystem <- 1022/15b3 PCI: 00:18.3 cmd <- 00 PCI: 00:18.4 subsystem <- 1022/15b4 PCI: 00:18.4 cmd <- 00 PCI: 00:18.5 subsystem <- 1022/15b5 PCI: 00:18.5 cmd <- 00 PCI: 01:00.0 cmd <- 02 PCI: 02:00.0 subsystem <- 1217/8620 PCI: 02:00.0 cmd <- 06 done. BS: BS_DEV_ENABLE times (us): entry 235061 run 103699 exit 0 POST: 0x75 Initializing devices... Root Device init ... Root Device init finished in 1947 usecs POST: 0x75 CPU_CLUSTER: 0 init ... MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x00000000d0000000 size 0xcff40000 type 6 0x00000000d0000000 - 0x00000000f0000000 size 0x20000000 type 0 0x00000000f0000000 - 0x00000000f4800000 size 0x04800000 type 1 0x00000000f4800000 - 0x0000000100000000 size 0x0b800000 type 0 0x0000000100000000 - 0x000000012f000000 size 0x2f000000 type 6 MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e call enable_fixed_mtrr() CPU physical address size: 48 bits MTRR: default type WB/UC MTRR counts: 8/6. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000ffff80000000 type 6 MTRR: 1 base 0x0000000080000000 mask 0x0000ffffc0000000 type 6 MTRR: 2 base 0x00000000c0000000 mask 0x0000fffff0000000 type 6 MTRR: 3 base 0x00000000f0000000 mask 0x0000fffffc000000 type 1 MTRR: 4 base 0x00000000f4000000 mask 0x0000ffffff800000 type 1 MTRR: 5 base 0x0000000100000000 mask 0x0000ffffc0000000 type 6 MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Will perform SMM setup. CPU: AMD A4-9120C RADEON R4, 5 COMPUTE CORES 2C+3G . Loading module at 00030000 with entry 00030000. filesize: 0x170 memsize: 0x170 Processing 16 relocs. Offset value of 0x00030000 Attempting to start 1 APs Waiting for 10ms after sending INIT. Waiting for 1st SIPI to complete...AP: slot 1 apic_id 11. done. Waiting for 2nd SIPI to complete...done. Loading module at 00038000 with entry 00038000. filesize: 0x1a8 memsize: 0x1a8 Processing 13 relocs. Offset value of 0x00038000 SMM Module: stub loaded at 00038000. Will call cdeb995b(00000000) Installing SMM handler to 0xce800000 Loading module at ce810000 with entry ce81142b. filesize: 0x6c98 memsize: 0xad18 Processing 481 relocs. Offset value of 0xce810000 Loading module at ce808000 with entry ce808000. filesize: 0x1a8 memsize: 0x1a8 Processing 13 relocs. Offset value of 0xce808000 SMM Module: placing jmp sequence at ce807e00 rel16 0x01fd SMM Module: stub loaded at ce808000. Will call ce81142b(00000000) New SMBASE 0xce800000 Relocation complete. New SMBASE 0xce7ffe00 Relocation complete. Initializing CPU #0 CPU: vendor AMD device 670f00 CPU: family 15, model 70, stepping 00 Setting up local APIC... apic_id: 0x10 done. CPU #0 initialized Initializing CPU #1 CPU: vendor AMD device 670f00 CPU: family 15, model 70, stepping 00 Setting up local APIC... apic_id: 0x11 done. CPU #1 initialized bsp_do_flight_plan done after 91 msecs. MTRR: TEMPORARY Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x00000000d0000000 size 0xcff40000 type 6 0x00000000d0000000 - 0x00000000ff000000 size 0x2f000000 type 0 0x00000000ff000000 - 0x0000000100000000 size 0x01000000 type 5 0x0000000100000000 - 0x000000012f000000 size 0x2f000000 type 6 MTRR: default type WB/UC MTRR counts: 7/5. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000ffff80000000 type 6 MTRR: 1 base 0x0000000080000000 mask 0x0000ffffc0000000 type 6 MTRR: 2 base 0x00000000c0000000 mask 0x0000fffff0000000 type 6 MTRR: 3 base 0x00000000ff000000 mask 0x0000ffffff000000 type 5 MTRR: 4 base 0x0000000100000000 mask 0x0000ffffc0000000 type 6 CPU_CLUSTER: 0 init finished in 345980 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 PCI: 00:00.0 init ... PCI: 00:00.0 init finished in 2002 usecs POST: 0x75 POST: 0x75 PCI: 00:01.0 init ... PCI: 00:01.0 init finished in 2002 usecs POST: 0x75 PCI: 00:01.1 init ... PCI: 00:01.1 init finished in 2002 usecs POST: 0x75 PCI: 00:02.0 init ... PCI: 00:02.0 init finished in 2002 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 PCI: 00:03.0 init ... PCI: 00:03.0 init finished in 2002 usecs POST: 0x75 PCI: 00:08.0 init ... PCI: 00:08.0 init finished in 2002 usecs POST: 0x75 PCI: 00:09.0 init ... PCI: 00:09.0 init finished in 2002 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 PCI: 00:14.0 init ... IOAPIC: Initializing IOAPIC at 0xfec00000 IOAPIC: Bootstrap Processor Local APIC = 0x10 IOAPIC: ID = 0x04 IOAPIC: Dumping registers reg 0x0000: 0x04000000 reg 0x0001: 0x00178021 reg 0x0002: 0x04000000 IOAPIC: 24 interrupts IOAPIC: Enabling interrupts on FSB IOAPIC: reg 0x00000000 value 0x10000000 0x00000700 IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 IOAPIC: reg 0x00000017 value 0x00000000 0x00010000 PCI: 00:14.0 init finished in 133955 usecs POST: 0x75 PCI: 00:14.3 init ... PCI: 00:14.3 init finished in 2060 usecs POST: 0x75 POST: 0x75 PCI: 00:18.0 init ... IOAPIC: Initializing IOAPIC at 0xfec20000 IOAPIC: Bootstrap Processor Local APIC = 0x10 IOAPIC: ID = 0x05 IOAPIC: Dumping registers reg 0x0000: 0x05000000 reg 0x0001: 0x001f8021 reg 0x0002: 0x00000000 IOAPIC: 32 interrupts IOAPIC: Enabling interrupts on FSB IOAPIC: reg 0x00000000 value 0x10000000 0x00000700 IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 IOAPIC: reg 0x00000017 value 0x00000000 0x00010000 IOAPIC: reg 0x00000018 value 0x00000000 0x00010000 IOAPIC: reg 0x00000019 value 0x00000000 0x00010000 IOAPIC: reg 0x0000001a value 0x00000000 0x00010000 IOAPIC: reg 0x0000001b value 0x00000000 0x00010000 IOAPIC: reg 0x0000001c value 0x00000000 0x00010000 IOAPIC: reg 0x0000001d value 0x00000000 0x00010000 IOAPIC: reg 0x0000001e value 0x00000000 0x00010000 IOAPIC: reg 0x0000001f value 0x00000000 0x00010000 PCI: 00:18.0 init finished in 170040 usecs POST: 0x75 PCI: 00:18.1 init ... PCI: 00:18.1 init finished in 2002 usecs POST: 0x75 PCI: 00:18.2 init ... PCI: 00:18.2 init finished in 2002 usecs POST: 0x75 PCI: 00:18.3 init ... PCI: 00:18.3 init finished in 2001 usecs POST: 0x75 PCI: 00:18.4 init ... PCI: 00:18.4 init finished in 2001 usecs POST: 0x75 PCI: 00:18.5 init ... PCI: 00:18.5 init finished in 2002 usecs POST: 0x75 PCI: 01:00.0 init ... PCI: 01:00.0 init finished in 2002 usecs POST: 0x75 PCI: 02:00.0 init ... BayHub BH720: Power-saving enabled (link_ctrl=0x110103) PCI: 02:00.0 init finished in 7127 usecs POST: 0x75 PNP: 0c09.0 init ... Google Chrome EC: Hello got back 11223344 status (0) Google Chrome EC: version: ro: careena_v2.0.11488-7215d6e0e4 rw: careena_v2.0.11488-7215d6e0e4 running image: 1 Google Chrome EC uptime: 120.022 seconds Google Chrome AP resets since EC boot: 0 Google Chrome most recent AP reset causes: Google Chrome EC reset flags at last EC boot: reset-pin PNP: 0c09.0 init finished in 34626 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 Devices initialized Show all devs... After init. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 DOMAIN: 0000: enabled 1 MMIO: fedc2000: enabled 1 MMIO: fedc3000: enabled 1 MMIO: fedc4000: enabled 1 MMIO: fedc5000: enabled 1 APIC: 10: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.2: enabled 0 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 0 PCI: 00:02.2: enabled 1 PCI: 00:02.3: enabled 0 PCI: 00:02.4: enabled 1 PCI: 00:02.5: enabled 0 PCI: 00:08.0: enabled 1 PCI: 00:09.0: enabled 1 PCI: 00:09.2: enabled 0 PCI: 00:10.0: enabled 0 PCI: 00:11.0: enabled 0 PCI: 00:12.0: enabled 0 PCI: 00:14.0: enabled 1 PCI: 00:14.3: enabled 1 PCI: 00:14.7: enabled 0 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 GENERIC: 0.0: enabled 1 I2C: 01:1a: enabled 1 GENERIC: 0.1: enabled 1 I2C: 02:50: enabled 1 I2C: 03:15: enabled 1 I2C: 04:39: enabled 1 I2C: 04:10: enabled 1 PCI: 02:00.0: enabled 1 PNP: 0c09.0: enabled 1 PCI: 00:03.0: enabled 1 PCI: 01:00.0: enabled 1 APIC: 11: enabled 1 BS: BS_DEV_INIT times (us): entry 0 run 948013 exit 141 ELOG: Event(A1) added with size 10 at 2023-08-09 04:55:09 UTC elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x2b POST: 0x76 Finalize devices... Devices finalized FMAP: area RW_NVRAM found @ 467000 (20480 bytes) BS: BS_POST_DEVICE times (us): entry 12912 run 4542 exit 4671 FMAP: area RW_MRC_CACHE found @ 0 (65536 bytes) MRC: Checking cached data update for 'RW_MRC_CACHE'. POST: 0x77 Trying to find the wakeup vector... Looking on 000f0000 for valid checksum Checksum 1 passed Checksum 2 passed all OK RSDP found at 000f0000 RSDT found at cde2e030 ends at cde2e07c FADT found at cde31e60 FACS found at cde2e240 OS waking vector is 0009a1d0 BS: BS_OS_RESUME_CHECK times (us): entry 9566 run 24100 exit 0 agesawrapper_amds3finalrestore() entry S3 volatile data @0xceebe000 0x4160 total bytes agesawrapper_amds3finalrestore() returned AGESA_SUCCESS Lock SMM configuration POST: 0xfe Probing TPM I2C: done! DID_VID 0x00281ae0 Locality already claimed cr50 TPM 2.0 (i2c 1:0x50 id 0x28) Platform hierarchy disablement failed: 5001 POST: 0x78 mp_park_aps done after 0 msecs. Restore GNVS pointer to cde6b000 smm_setup_structures STUB!!! POST: 0xfd <6>[ 20.920969] ACPI: EC: interrupt blocked <6>[ 20.945018] ACPI: Preparing to enter system sleep state S3 <6>[ 20.945768] ACPI: EC: event blocked <6>[ 20.945769] ACPI: EC: EC stopped <6>[ 20.945769] PM: Saving platform NVS memory <6>[ 20.945771] Disabling non-boot CPUs ... <6>[ 20.947167] smpboot: CPU 1 is now offline <6>[ 20.947585] ACPI: Low-level resume complete <6>[ 20.947602] ACPI: EC: EC started <6>[ 20.947603] PM: Restoring platform NVS memory <6>[ 20.947619] LVT offset 0 assigned for vector 0x400 <6>[ 20.947877] Enabling non-boot CPUs ... <6>[ 20.947911] x86: Booting SMP configuration: <6>[ 20.947913] smpboot: Booting Node 0 Processor 1 APIC 0x11 <6>[ 20.948066] microcode: CPU1: patch_level=0x06006705 <6>[ 20.950404] ACPI: \_PR_.P001: Found 2 idle states <6>[ 20.950628] CPU1 is up <6>[ 20.950929] ACPI: Waking up from system sleep state S3 <6>[ 20.978426] ACPI: EC: interrupt unblocked <6>[ 21.004490] ACPI: EC: event unblocked <6>[ 21.005188] [drm] PCIE GART of 1024M enabled (table at 0x000000F400000000). <6>[ 21.005202] amdgpu: smu version 33.09.00 <6>[ 21.271110] usb 1-1.1: reset high-speed USB device number 3 using ehci-pci <6>[ 21.279231] r8152 2-4:1.0 eth0: carrier on <6>[ 21.693167] [drm] UVD initialized successfully. <6>[ 21.794259] [drm] VCE initialized successfully. <6>[ 21.920481] OOM killer enabled. <6>[ 21.923880] Restarting tasks ... done. <6>[ 21.930038] PM: suspend exit rtcwake: assuming RTC uses UTC ... rtcwake: wakeup from "mem" using rtc0 at Wed Aug 9 04:55:16 2023 <6>[ 21.957223] PM: suspend entry (deep) <6>[ 21.961090] Filesystems sync: 0.000 seconds <6>[ 21.965693] Freezing user space processes ... (elapsed 0.001 seconds) done. <6>[ 21.974146] OOM killer disabled. <6>[ 21.977629] Freezing remaining freezable tasks ... (elapsed 1.112 seconds) done. <6>[ 23.114748] printk: Suspending console(s) (use no_console_suspend to debug) coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 smm starting... SMI# #0 SMI#: SLP = 0x0c01 Chrome EC: UHEPI supported Chrome EC: Set SMI mask to 0x0000000000000000 Chrome EC: Set SCI mask to 0x0000000000000000 Clearing pending EC events. Error code 1 is expected. EC returned error result code 9 SMI#: Entering S3 (Suspend-To-RAM) FMAP: Found "FLASH" version 1.1 at d7f000. FMAP: base = ff000000 size = 1000000 #areas = 30 FMAP: area RW_ELOG found @ 45d000 (16384 bytes) Manufacturer: ef SF: Detected W25Q128FW with sector size 0x1000, total 0x1000000 ELOG: NV offset 0x45d000 size 0x4000 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024 ELOG: Event(9D) added with size 10 at 2023-08-09 04:55:11 UTC coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 bootblock starting... Family_Model: 00670f00 PMxC0 STATUS: 0x40200800 BIT30 SleepReset BIT11 DW I2C bus 1 at 0xfedc3000 (400 KHz) VBOOT: Loading verstage. CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'fallback/verstage' CBFS: Found @ offset aa8c0 size d5a4 coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 verstage starting... Probing TPM I2C: done! DID_VID 0x00281ae0 TPM ready after 0 ms cr50 TPM 2.0 (i2c 1:0x50 id 0x28) tlcl_send_startup: Startup return code is 84 src/security/tpm/tss/tcg-2.0/tss.c:177 index 0x1007 return code 100 read_space_firmware():99: Antirollback: 0000500a returned by tlcl_read(FIRMWARE_NV_INDEX, ctx->secdata, VB2_SECDATA_SIZE) antirollback_read_space_firmware():474: TPM: Firmware space in a bad state; giving up. Chrome EC: UHEPI supported Phase 1 VB2:vb2_fail() Need recovery, reason: 0x2b / 0x2 FMAP: Found "FLASH" version 1.1 at d7f000. FMAP: base = ff000000 size = 1000000 #areas = 30 FMAP: area GBB found @ d80000 (458752 bytes) VB2:vb2_check_recovery() Recovery reason from previous boot: 0x2b / 0x2 VB2:vb2_check_recovery() We have a recovery request: 0x2b / 0x0 Clearing TPM owner TPM: Clear and re-enable tlcl_force_clear: response is 100 TPM: Can't initiate a force clear. Recovery requested (1009000e) Saving nvdata tlcl_extend: response is 100 CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'fallback/romstage' CBFS: Found @ offset 80 size d2e4 coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 romstage starting... CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'smu_fw' CBFS: Found @ offset 7bc00 size 12262 PSP: Load blob type 19 from @ffe6bc38... OK POST: 0x37 agesawrapper_amdinitreset() entry CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'AGESA_PRE_MEM' CBFS: Found @ offset df80 size 53bcc agesawrapper_amdinitreset() returned AGESA_SUCCESS POST: 0x38 agesawrapper_amdinitearly() entry Warning - AGESA callout: platform_PcieSlotResetControl not supported Warning - AGESA callout: platform_PcieSlotResetControl not supported agesawrapper_amdinitearly() returned AGESA_SUCCESS S3 detected POST: 0x60 agesawrapper_amdinitresume() entry Chrome EC: UHEPI supported FMAP: Found "FLASH" version 1.1 at d7f000. FMAP: base = ff000000 size = 1000000 #areas = 30 FMAP: area RW_MRC_CACHE found @ 0 (65536 bytes) S3 NV data @0xff0048c0, 0xe65 bytes agesawrapper_amdinitresume() returned AGESA_SUCCESS POST: 0x61 POST: 0x42 PSP: Notify that DRAM is available... OK POST: 0x43 creating vboot_handoff structure Chrome EC: clear events_b mask to 0x0000000021004000 POST: 0x44 MTRR Range: Start=cd000000 End=ce000000 (Size 1000000) MTRR Range: Start=ff000000 End=0 (Size 1000000) MTRR Range: Start=ce800000 End=cf000000 (Size 800000) POST: 0x45 coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 postcar starting... Jumping to image. coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 ramstage starting... POST: 0x39 FMAP: Found "FLASH" version 1.1 at d7f000. FMAP: base = ff000000 size = 1000000 #areas = 30 FMAP: area RO_VPD found @ c00000 (16384 bytes) WARNING: RO_VPD is uninitialized or empty. FMAP: area RW_VPD found @ 465000 (8192 bytes) FMAP: area RW_VPD found @ 465000 (8192 bytes) POST: 0x80 S3 Resume. POST: 0x46 agesawrapper_amds3laterestore() entry AGESA: Loading stage from cache S3 volatile data @0xceebe000 0x4160 total bytes agesawrapper_amds3laterestore() returned AGESA_SUCCESS POST: 0x70 BS: BS_PRE_DEVICE times (us): entry 20065 run 1061 exit 0 POST: 0x71 Board ID: 6 mainboard: EC init Chrome EC: Set SMI mask to 0x0000000000000000 Chrome EC: UHEPI supported Chrome EC: Set SCI mask to 0x00000000142609fb Chrome EC: Set WAKE mask to 0x0000000000000000 DW I2C bus 0 at 0xfedc2000 (400 KHz) DW I2C bus 2 at 0xfedc4000 (400 KHz) DW I2C bus 3 at 0xfedc5000 (400 KHz) FMAP: area RW_ELOG found @ 45d000 (16384 bytes) Manufacturer: ef SF: Detected W25Q128FW with sector size 0x1000, total 0x1000000 ELOG: NV offset 0x45d000 size 0x4000 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024 ELOG: Event(9E) added with size 10 at 2023-08-09 04:55:16 UTC ELOG: Event(16) added with size 11 at 2023-08-09 04:55:16 UTC SF: Successfully erased 4096 bytes @ 0x45d000 ELOG: Event(9F) added with size 14 at 2023-08-09 04:55:16 UTC PM1_STS: WAK RTC BMSTATUS setup_bsp_ramtop, TOP MEM: msr.lo = 0xd0000000, msr.hi = 0x00000000 setup_bsp_ramtop, TOP MEM2: msr.lo = 0x2f000000, msr.hi = 0x00000001 BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 159201 exit 0 POST: 0x72 Enumerating buses... Show all devs... Before device enumeration. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 DOMAIN: 0000: enabled 1 MMIO: fedc2000: enabled 1 MMIO: fedc3000: enabled 1 MMIO: fedc4000: enabled 1 MMIO: fedc5000: enabled 1 APIC: 10: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.2: enabled 0 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 1 PCI: 00:02.2: enabled 1 PCI: 00:02.3: enabled 1 PCI: 00:02.4: enabled 1 PCI: 00:02.5: enabled 1 PCI: 00:08.0: enabled 1 PCI: 00:09.0: enabled 1 PCI: 00:09.2: enabled 1 PCI: 00:10.0: enabled 1 PCI: 00:11.0: enabled 0 PCI: 00:12.0: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:14.3: enabled 1 PCI: 00:14.7: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 GENERIC: 0.0: enabled 1 I2C: 00:1a: enabled 1 GENERIC: 0.1: enabled 1 I2C: 00:50: enabled 1 I2C: 00:15: enabled 1 I2C: 00:39: enabled 1 I2C: 00:10: enabled 1 PCI: 00:00.0: enabled 1 PNP: 0c09.0: enabled 1 Compare with tree... Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 10: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.2: enabled 0 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 1 PCI: 00:02.2: enabled 1 PCI: 00:02.3: enabled 1 PCI: 00:02.4: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:02.5: enabled 1 PCI: 00:08.0: enabled 1 PCI: 00:09.0: enabled 1 PCI: 00:09.2: enabled 1 PCI: 00:10.0: enabled 1 PCI: 00:11.0: enabled 0 PCI: 00:12.0: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:14.3: enabled 1 PNP: 0c09.0: enabled 1 PCI: 00:14.7: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 MMIO: fedc2000: enabled 1 GENERIC: 0.0: enabled 1 I2C: 00:1a: enabled 1 GENERIC: 0.1: enabled 1 MMIO: fedc3000: enabled 1 I2C: 00:50: enabled 1 MMIO: fedc4000: enabled 1 I2C: 00:15: enabled 1 MMIO: fedc5000: enabled 1 I2C: 00:39: enabled 1 I2C: 00:10: enabled 1 Mainboard Grunt Enable. Root Device scanning... root_dev_scan_bus for Root Device CPU_CLUSTER: 0 enabled DOMAIN: 0000 enabled MMIO: fedc2000 enabled MMIO: fedc3000 enabled MMIO: fedc4000 enabled MMIO: fedc5000 enabled DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 POST: 0x24 sb_enable PCI: 00:00.0 [1022/1576] enabled sb_enable sb_enable PCI: 00:01.0 [1002/98e4] enabled sb_enable PCI: 00:01.1 [1002/15b3] enabled sb_enable PCI: 00:02.0 [1022/157b] enabled sb_enable PCI: Static device PCI: 00:02.1 not found, disabling it. sb_enable Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xc0 Capability: type 0x08 @ 0xc8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 PCI: 00:02.2 subordinate bus PCI Express PCI: 00:02.2 [1022/157c] enabled sb_enable PCI: Static device PCI: 00:02.3 not found, disabling it. sb_enable Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xc0 Capability: type 0x08 @ 0xc8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 PCI: 00:02.4 subordinate bus PCI Express PCI: 00:02.4 [1022/157c] enabled sb_enable PCI: Static device PCI: 00:02.5 not found, disabling it. PCI: 00:03.0 [1022/157b] enabled sb_enable PCI: 00:08.0 [1022/1578] enabled sb_enable PCI: 00:09.0 [1022/157d] enabled sb_enable PCI: Static device PCI: 00:09.2 not found, disabling it. sb_enable PCI: Static device PCI: 00:10.0 not found, disabling it. sb_enable sb_enable PCI: Static device PCI: 00:12.0 not found, disabling it. sb_enable PCI: 00:14.0 [1022/790b] bus ops PCI: 00:14.0 [1022/790b] enabled sb_enable PCI: 00:14.3 [1022/0000] bus ops PCI: 00:14.3 [1022/790e] enabled sb_enable PCI: Static device PCI: 00:14.7 not found, disabling it. sb_enable PCI: 00:18.0 [1022/15b0] ops PCI: 00:18.0 [1022/15b0] enabled sb_enable PCI: 00:18.1 [1022/15b1] enabled sb_enable PCI: 00:18.2 [1022/15b2] enabled sb_enable PCI: 00:18.3 [1022/15b3] enabled sb_enable PCI: 00:18.4 [1022/15b4] enabled sb_enable PCI: 00:18.5 [1022/15b5] enabled POST: 0x25 PCI: 00:02.2 scanning... do_pci_scan_bridge for PCI: 00:02.2 PCI: pci_scan_bus for bus 01 POST: 0x24 PCI: 01:00.0 [168c/003e] enabled POST: 0x25 POST: 0x55 Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x50 Capability: type 0x10 @ 0x70 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Enabling Common Clock Configuration ASPM: Enabled L0s and L1 Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x50 Capability: type 0x10 @ 0x70 scan_bus: scanning of bus PCI: 00:02.2 took 40760 usecs PCI: 00:02.4 scanning... do_pci_scan_bridge for PCI: 00:02.4 PCI: pci_scan_bus for bus 02 POST: 0x24 PCI: 02:00.0 [1217/0000] ops PCI: 02:00.0 [1217/8620] enabled POST: 0x25 POST: 0x55 Capability: type 0x01 @ 0x6c Capability: type 0x05 @ 0x48 Capability: type 0x10 @ 0x80 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 ASPM: Enabled L0s and L1 Capability: type 0x01 @ 0x6c Capability: type 0x05 @ 0x48 Capability: type 0x10 @ 0x80 scan_bus: scanning of bus PCI: 00:02.4 took 40397 usecs PCI: 00:14.0 scanning... scan_generic_bus for PCI: 00:14.0 scan_generic_bus for PCI: 00:14.0 done scan_bus: scanning of bus PCI: 00:14.0 took 8803 usecs PCI: 00:14.3 scanning... scan_lpc_bus for PCI: 00:14.3 PNP: 0c09.0 enabled scan_lpc_bus for PCI: 00:14.3 done scan_bus: scanning of bus PCI: 00:14.3 took 9951 usecs POST: 0x55 scan_bus: scanning of bus DOMAIN: 0000 took 289474 usecs MMIO: fedc2000 scanning... scan_generic_bus for MMIO: fedc2000 bus: MMIO: fedc2000[0]->GENERIC: 0.0 enabled bus: MMIO: fedc2000[0]->I2C: 01:1a enabled bus: MMIO: fedc2000[0]->GENERIC: 0.1 enabled scan_generic_bus for MMIO: fedc2000 done scan_bus: scanning of bus MMIO: fedc2000 took 21226 usecs MMIO: fedc3000 scanning... scan_generic_bus for MMIO: fedc3000 bus: MMIO: fedc3000[0]->I2C: 02:50 enabled scan_generic_bus for MMIO: fedc3000 done scan_bus: scanning of bus MMIO: fedc3000 took 13195 usecs MMIO: fedc4000 scanning... scan_generic_bus for MMIO: fedc4000 bus: MMIO: fedc4000[0]->I2C: 03:15 enabled scan_generic_bus for MMIO: fedc4000 done scan_bus: scanning of bus MMIO: fedc4000 took 13171 usecs MMIO: fedc5000 scanning... scan_generic_bus for MMIO: fedc5000 bus: MMIO: fedc5000[0]->I2C: 04:39 enabled bus: MMIO: fedc5000[0]->I2C: 04:10 enabled scan_generic_bus for MMIO: fedc5000 done scan_bus: scanning of bus MMIO: fedc5000 took 16983 usecs root_dev_scan_bus for Root Device done scan_bus: scanning of bus Root Device took 400650 usecs done BS: BS_DEV_ENUMERATE times (us): entry 0 run 605608 exit 0 POST: 0x73 found VGA at PCI: 00:01.0 Setting up VGA for PCI: 00:01.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done DOMAIN: 0000 read_resources bus 0 link: 0 PCI: 00:02.2 read_resources bus 1 link: 0 PCI: 00:02.2 read_resources bus 1 link: 0 done PCI: 00:02.4 read_resources bus 2 link: 0 PCI: 00:02.4 read_resources bus 2 link: 0 done PCI: 00:14.3 read_resources bus 0 link: 0 PCI: 00:14.3 read_resources bus 0 link: 0 done Adding PCIe enhanced config space BAR 0xf8000000-0xfc000000. DOMAIN: 0000 read_resources bus 0 link: 0 done MMIO: fedc2000 read_resources bus 1 link: 0 MMIO: fedc2000 read_resources bus 1 link: 0 done MMIO: fedc3000 read_resources bus 2 link: 0 MMIO: fedc3000 read_resources bus 2 link: 0 done MMIO: fedc4000 read_resources bus 3 link: 0 MMIO: fedc4000 read_resources bus 3 link: 0 done MMIO: fedc5000 read_resources bus 4 link: 0 MMIO: fedc5000 read_resources bus 4 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 10 APIC: 10 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI: 00:00.0 PCI: 00:00.2 PCI: 00:01.0 PCI: 00:01.0 resource base 0 size 4000000 align 26 gran 26 limit ffffffffffffffff flags 1201 index 10 PCI: 00:01.0 resource base 0 size 800000 align 23 gran 23 limit ffffffffffffffff flags 1201 index 18 PCI: 00:01.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 20 PCI: 00:01.0 resource base 0 size 40000 align 18 gran 18 limit ffffffff flags 200 index 24 PCI: 00:01.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 2200 index 30 PCI: 00:01.1 PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 PCI: 00:02.0 PCI: 00:02.1 PCI: 00:02.2 child on link 0 PCI: 01:00.0 PCI: 00:02.2 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:02.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:02.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 01:00.0 PCI: 01:00.0 resource base 0 size 200000 align 21 gran 21 limit ffffffffffffffff flags 201 index 10 PCI: 00:02.3 PCI: 00:02.4 child on link 0 PCI: 02:00.0 PCI: 00:02.4 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:02.4 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:02.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 02:00.0 PCI: 02:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 02:00.0 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 14 PCI: 00:02.5 PCI: 00:03.0 PCI: 00:08.0 PCI: 00:08.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 1201 index 10 PCI: 00:08.0 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 200 index 18 PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 1c PCI: 00:08.0 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 200 index 20 PCI: 00:08.0 resource base 0 size 2000 align 13 gran 13 limit ffffffff flags 200 index 24 PCI: 00:09.0 PCI: 00:09.2 PCI: 00:10.0 PCI: 00:11.0 PCI: 00:12.0 PCI: 00:14.0 PCI: 00:14.3 child on link 0 PNP: 0c09.0 PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:14.3 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100 PCI: 00:14.3 resource base fec10000 size 400 align 0 gran 0 limit 0 flags e0040200 index 2 PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PCI: 00:14.3 resource base fedc2000 size 4000 align 0 gran 0 limit 0 flags c0000200 index 4 PNP: 0c09.0 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0 PCI: 00:14.7 PCI: 00:18.0 PCI: 00:18.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI: 00:18.0 resource base fec20000 size 1000 align 0 gran 0 limit 0 flags c0000200 index fec20000 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.4 PCI: 00:18.5 MMIO: fedc2000 child on link 0 GENERIC: 0.0 GENERIC: 0.0 I2C: 01:1a GENERIC: 0.1 MMIO: fedc3000 child on link 0 I2C: 02:50 I2C: 02:50 MMIO: fedc4000 child on link 0 I2C: 03:15 I2C: 03:15 MMIO: fedc5000 child on link 0 I2C: 04:39 I2C: 04:39 I2C: 04:10 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:02.2 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:02.2 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:02.4 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:02.4 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:01.0 20 * [0x0 - 0xff] io DOMAIN: 0000 io: base: 100 size: 100 align: 8 gran: 0 limit: ffff done DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:02.2 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:02.2 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:02.2 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 01:00.0 10 * [0x0 - 0x1fffff] mem PCI: 00:02.2 mem: base: 200000 size: 200000 align: 21 gran: 20 limit: ffffffff done PCI: 00:02.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:02.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:02.4 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 02:00.0 10 * [0x0 - 0xfff] mem PCI: 02:00.0 14 * [0x1000 - 0x17ff] mem PCI: 00:02.4 mem: base: 1800 size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:01.0 10 * [0x0 - 0x3ffffff] prefmem PCI: 00:01.0 18 * [0x4000000 - 0x47fffff] prefmem PCI: 00:02.2 20 * [0x4800000 - 0x49fffff] mem PCI: 00:02.4 20 * [0x4a00000 - 0x4afffff] mem PCI: 00:08.0 18 * [0x4b00000 - 0x4bfffff] mem PCI: 00:08.0 20 * [0x4c00000 - 0x4cfffff] mem PCI: 00:01.0 24 * [0x4d00000 - 0x4d3ffff] mem PCI: 00:01.0 30 * [0x4d40000 - 0x4d5ffff] mem PCI: 00:08.0 10 * [0x4d60000 - 0x4d7ffff] prefmem PCI: 00:01.1 10 * [0x4d80000 - 0x4d83fff] mem PCI: 00:08.0 24 * [0x4d84000 - 0x4d85fff] mem PCI: 00:08.0 1c * [0x4d86000 - 0x4d86fff] mem DOMAIN: 0000 mem: base: 4d87000 size: 4d87000 align: 26 gran: 0 limit: ffffffff done avoid_fixed_resources: DOMAIN: 0000 avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI: 00:14.3 10000000 base 00000000 limit 00000fff io (fixed) constrain_resources: PCI: 00:14.3 10000100 base ff000000 limit ffffffff mem (fixed) constrain_resources: PCI: 00:14.3 02 base fec10000 limit fec103ff mem (fixed) constrain_resources: PCI: 00:14.3 03 base fec00000 limit fec00fff mem (fixed) constrain_resources: PCI: 00:18.0 c0010058 base f8000000 limit fbffffff mem (fixed) avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001000 limit 0000ffff avoid_fixed_resources:@DOMAIN: 0000 10000100 base f0000000 limit f7ffffff Setting resources... DOMAIN: 0000 io: base:1000 size:100 align:8 gran:0 limit:ffff PCI: 00:01.0 20 * [0x1000 - 0x10ff] io DOMAIN: 0000 io: next_base: 1100 size: 100 align: 8 gran: 0 done PCI: 00:02.2 io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:02.2 io: next_base: ffff size: 0 align: 12 gran: 12 done PCI: 00:02.4 io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:02.4 io: next_base: ffff size: 0 align: 12 gran: 12 done DOMAIN: 0000 mem: base:f0000000 size:4d87000 align:26 gran:0 limit:f7ffffff PCI: 00:01.0 10 * [0xf0000000 - 0xf3ffffff] prefmem PCI: 00:01.0 18 * [0xf4000000 - 0xf47fffff] prefmem PCI: 00:02.2 20 * [0xf4800000 - 0xf49fffff] mem PCI: 00:02.4 20 * [0xf4a00000 - 0xf4afffff] mem PCI: 00:08.0 18 * [0xf4b00000 - 0xf4bfffff] mem PCI: 00:08.0 20 * [0xf4c00000 - 0xf4cfffff] mem PCI: 00:01.0 24 * [0xf4d00000 - 0xf4d3ffff] mem PCI: 00:01.0 30 * [0xf4d40000 - 0xf4d5ffff] mem PCI: 00:08.0 10 * [0xf4d60000 - 0xf4d7ffff] prefmem PCI: 00:01.1 10 * [0xf4d80000 - 0xf4d83fff] mem PCI: 00:08.0 24 * [0xf4d84000 - 0xf4d85fff] mem PCI: 00:08.0 1c * [0xf4d86000 - 0xf4d86fff] mem DOMAIN: 0000 mem: next_base: f4d87000 size: 4d87000 align: 26 gran: 0 done PCI: 00:02.2 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff PCI: 00:02.2 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done PCI: 00:02.2 mem: base:f4800000 size:200000 align:21 gran:20 limit:f49fffff PCI: 01:00.0 10 * [0xf4800000 - 0xf49fffff] mem PCI: 00:02.2 mem: next_base: f4a00000 size: 200000 align: 21 gran: 20 done PCI: 00:02.4 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff PCI: 00:02.4 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done PCI: 00:02.4 mem: base:f4a00000 size:100000 align:20 gran:20 limit:f4afffff PCI: 02:00.0 10 * [0xf4a00000 - 0xf4a00fff] mem PCI: 02:00.0 14 * [0xf4a01000 - 0xf4a017ff] mem PCI: 00:02.4 mem: next_base: f4a01800 size: 100000 align: 20 gran: 20 done Root Device assign_resources, bus 0 link: 0 DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:01.0 10 <- [0x00f0000000 - 0x00f3ffffff] size 0x04000000 gran 0x1a prefmem64 PCI: 00:01.0 18 <- [0x00f4000000 - 0x00f47fffff] size 0x00800000 gran 0x17 prefmem64 PCI: 00:01.0 20 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io PCI: 00:01.0 24 <- [0x00f4d00000 - 0x00f4d3ffff] size 0x00040000 gran 0x12 mem PCI: 00:01.0 30 <- [0x00f4d40000 - 0x00f4d5ffff] size 0x00020000 gran 0x11 romem PCI: 00:01.1 10 <- [0x00f4d80000 - 0x00f4d83fff] size 0x00004000 gran 0x0e mem64 PCI: 00:02.2 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io PCI: 00:02.2 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 01 prefmem PCI: 00:02.2 20 <- [0x00f4800000 - 0x00f49fffff] size 0x00200000 gran 0x14 bus 01 mem PCI: 00:02.2 assign_resources, bus 1 link: 0 PCI: 01:00.0 10 <- [0x00f4800000 - 0x00f49fffff] size 0x00200000 gran 0x15 mem64 PCI: 00:02.2 assign_resources, bus 1 link: 0 PCI: 00:02.4 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io PCI: 00:02.4 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 02 prefmem PCI: 00:02.4 20 <- [0x00f4a00000 - 0x00f4afffff] size 0x00100000 gran 0x14 bus 02 mem PCI: 00:02.4 assign_resources, bus 2 link: 0 PCI: 02:00.0 10 <- [0x00f4a00000 - 0x00f4a00fff] size 0x00001000 gran 0x0c mem PCI: 02:00.0 14 <- [0x00f4a01000 - 0x00f4a017ff] size 0x00000800 gran 0x0b mem PCI: 00:02.4 assign_resources, bus 2 link: 0 PCI: 00:08.0 10 <- [0x00f4d60000 - 0x00f4d7ffff] size 0x00020000 gran 0x11 prefmem64 PCI: 00:08.0 18 <- [0x00f4b00000 - 0x00f4bfffff] size 0x00100000 gran 0x14 mem PCI: 00:08.0 1c <- [0x00f4d86000 - 0x00f4d86fff] size 0x00001000 gran 0x0c mem PCI: 00:08.0 20 <- [0x00f4c00000 - 0x00f4cfffff] size 0x00100000 gran 0x14 mem PCI: 00:08.0 24 <- [0x00f4d84000 - 0x00f4d85fff] size 0x00002000 gran 0x0d mem PCI: 00:14.3 assign_resources, bus 0 link: 0 PCI: 00:14.3 assign_resources, bus 0 link: 0 DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 10 APIC: 10 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 1000 size 100 align 8 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base f0000000 size 4d87000 align 26 gran 0 limit f7ffffff flags 40040200 index 10000100 DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10 DOMAIN: 0000 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11 DOMAIN: 0000 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12 DOMAIN: 0000 resource base 100000 size cdf00000 align 0 gran 0 limit 0 flags e0004200 index 13 DOMAIN: 0000 resource base ce000000 size 2000000 align 0 gran 0 limit 0 flags f0004200 index 14 DOMAIN: 0000 resource base 100000000 size 2f000000 align 0 gran 0 limit 0 flags e0004200 index 15 PCI: 00:00.0 PCI: 00:00.2 PCI: 00:01.0 PCI: 00:01.0 resource base f0000000 size 4000000 align 26 gran 26 limit f3ffffff flags 60001201 index 10 PCI: 00:01.0 resource base f4000000 size 800000 align 23 gran 23 limit f47fffff flags 60001201 index 18 PCI: 00:01.0 resource base 1000 size 100 align 8 gran 8 limit 10ff flags 60000100 index 20 PCI: 00:01.0 resource base f4d00000 size 40000 align 18 gran 18 limit f4d3ffff flags 60000200 index 24 PCI: 00:01.0 resource base f4d40000 size 20000 align 17 gran 17 limit f4d5ffff flags 60002200 index 30 PCI: 00:01.1 PCI: 00:01.1 resource base f4d80000 size 4000 align 14 gran 14 limit f4d83fff flags 60000201 index 10 PCI: 00:02.0 PCI: 00:02.1 PCI: 00:02.2 child on link 0 PCI: 01:00.0 PCI: 00:02.2 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:02.2 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24 PCI: 00:02.2 resource base f4800000 size 200000 align 21 gran 20 limit f49fffff flags 60080202 index 20 PCI: 01:00.0 PCI: 01:00.0 resource base f4800000 size 200000 align 21 gran 21 limit f49fffff flags 60000201 index 10 PCI: 00:02.3 PCI: 00:02.4 child on link 0 PCI: 02:00.0 PCI: 00:02.4 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:02.4 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24 PCI: 00:02.4 resource base f4a00000 size 100000 align 20 gran 20 limit f4afffff flags 60080202 index 20 PCI: 02:00.0 PCI: 02:00.0 resource base f4a00000 size 1000 align 12 gran 12 limit f4a00fff flags 60000200 index 10 PCI: 02:00.0 resource base f4a01000 size 800 align 12 gran 11 limit f4a017ff flags 60000200 index 14 PCI: 00:02.5 PCI: 00:03.0 PCI: 00:08.0 PCI: 00:08.0 resource base f4d60000 size 20000 align 17 gran 17 limit f4d7ffff flags 60001201 index 10 PCI: 00:08.0 resource base f4b00000 size 100000 align 20 gran 20 limit f4bfffff flags 60000200 index 18 PCI: 00:08.0 resource base f4d86000 size 1000 align 12 gran 12 limit f4d86fff flags 60000200 index 1c PCI: 00:08.0 resource base f4c00000 size 100000 align 20 gran 20 limit f4cfffff flags 60000200 index 20 PCI: 00:08.0 resource base f4d84000 size 2000 align 13 gran 13 limit f4d85fff flags 60000200 index 24 PCI: 00:09.0 PCI: 00:09.2 PCI: 00:10.0 PCI: 00:11.0 PCI: 00:12.0 PCI: 00:14.0 PCI: 00:14.3 child on link 0 PNP: 0c09.0 PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:14.3 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100 PCI: 00:14.3 resource base fec10000 size 400 align 0 gran 0 limit 0 flags e0040200 index 2 PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PCI: 00:14.3 resource base fedc2000 size 4000 align 0 gran 0 limit 0 flags c0000200 index 4 PNP: 0c09.0 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0 PCI: 00:14.7 PCI: 00:18.0 PCI: 00:18.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI: 00:18.0 resource base fec20000 size 1000 align 0 gran 0 limit 0 flags c0000200 index fec20000 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.4 PCI: 00:18.5 MMIO: fedc2000 child on link 0 GENERIC: 0.0 GENERIC: 0.0 I2C: 01:1a GENERIC: 0.1 MMIO: fedc3000 child on link 0 I2C: 02:50 I2C: 02:50 MMIO: fedc4000 child on link 0 I2C: 03:15 I2C: 03:15 MMIO: fedc5000 child on link 0 I2C: 04:39 I2C: 04:39 I2C: 04:10 Done allocating resources. BS: BS_DEV_RESOURCES times (us): entry 0 run 1463910 exit 0 PCI_INTR tables: Writing registers C00/C01 for PCI IRQ routing: PCI_INTR_INDEX name PIC mode APIC mode 0x00 INTA# 0x03 0x10 0x01 INTB# 0x04 0x11 0x02 INTC# 0x05 0x12 0x03 INTD# 0x07 0x13 0x04 INTE# 0x0B 0x14 0x05 INTF# 0x1F 0x1F 0x06 INTG# 0x1F 0x16 0x07 INTH# 0x1F 0x17 0x08 Misc 0xFA 0x00 0x09 Misc0 0xF1 0x00 0x0A Misc1 0x00 0x00 0x0B Misc2 0x00 0x00 0x0C Ser IRQ INTA 0x1F 0x1F 0x0D Ser IRQ INTB 0x1F 0x1F 0x0E Ser IRQ INTC 0x1F 0x1F 0x0F Ser IRQ INTD 0x1F 0x1F 0x10 SCI 0x09 0x09 0x11 SMBUS 0x1F 0x1F 0x12 ASF 0x1F 0x1F 0x13 HDA 0x03 0x10 0x14 FC 0x1F 0x1F 0x16 PerMon 0x1F 0x1F 0x17 SD 0x03 0x10 0x1A SDIOt 0x00 0x1F 0x30 EHCI 0x05 0x12 0x34 XHCI 0x04 0x12 0x41 SATA 0x07 0x13 0x62 GPIO 0x07 0x07 0x70 I2C0 0x03 0x03 0x71 I2C1 0x0F 0x0F 0x72 I2C2 0x06 0x06 0x73 I2C3 0x0E 0x0E 0x74 UART0 0x0A 0x0A 0x75 UART1 0x0B 0x0B PCI_CFG IRQ: Write PCI config space IRQ assignments PCI IRQ: Found device 0:01.00 using PIN A PCI Devfn (0x8) not found in pirq_data table PCI IRQ: Found device 0:01.01 using PIN B Found this device in pirq_data table entry 5 Orig INT_PIN : 2 (PIN B) PCI_INTR idx : 0x13 (HDA) INT_LINE : 0x3 (IRQ 3) PCI IRQ: Found device 0:02.02 using PIN A Found this device in pirq_data table entry 1 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x01 (INTB#) INT_LINE : 0x4 (IRQ 4) PCI IRQ: Found device 0:02.04 using PIN A Found this device in pirq_data table entry 3 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x03 (INTD#) INT_LINE : 0x7 (IRQ 7) PCI IRQ: Found device 0:08.00 using PIN A PCI Devfn (0x40) not found in pirq_data table PCI IRQ: Found device 2:00.00 using PIN A With INT_PIN swizzled to PIN A Attached to bridge device 0:02h.04h Found this device in pirq_data table entry 3 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x03 (INTD#) INT_LINE : 0x7 (IRQ 7) PCI IRQ: Found device 1:00.00 using PIN A With INT_PIN swizzled to PIN A Attached to bridge device 0:02h.02h Found this device in pirq_data table entry 1 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x01 (INTB#) INT_LINE : 0x4 (IRQ 4) PCI_CFG IRQ: Finished writing PCI config space IRQ assignments POST: 0x74 Enabling resources... PCI: 00:00.0 subsystem <- 1022/1576 PCI: 00:00.0 cmd <- 04 PCI: 00:01.0 subsystem <- 1002/98e4 PCI: 00:01.0 cmd <- 07 PCI: 00:01.1 subsystem <- 1002/15b3 PCI: 00:01.1 cmd <- 02 PCI: 00:02.0 subsystem <- 1022/157b PCI: 00:02.0 cmd <- 00 PCI: 00:02.2 bridge ctrl <- 0003 PCI: 00:02.2 cmd <- 06 PCI: 00:02.4 bridge ctrl <- 0003 PCI: 00:02.4 cmd <- 06 PCI: 00:03.0 cmd <- 00 PCI: 00:08.0 subsystem <- 1022/1578 PCI: 00:08.0 cmd <- 06 PCI: 00:09.0 subsystem <- 1022/157d PCI: 00:09.0 cmd <- 00 PCI: 00:14.0 subsystem <- 1022/790b PCI: 00:14.0 cmd <- 403 PCI: 00:14.3 subsystem <- 1022/790e PCI: 00:14.3 cmd <- 0f Southbridge LPC decode:PNP: 0c09.0, base=0x00000800, end=0x000009fe Covered by wideIO 0 PCI: 00:18.0 cmd <- 00 PCI: 00:18.1 subsystem <- 1022/15b1 PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 subsystem <- 1022/15b2 PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 subsystem <- 1022/15b3 PCI: 00:18.3 cmd <- 00 PCI: 00:18.4 subsystem <- 1022/15b4 PCI: 00:18.4 cmd <- 00 PCI: 00:18.5 subsystem <- 1022/15b5 PCI: 00:18.5 cmd <- 00 PCI: 01:00.0 cmd <- 02 PCI: 02:00.0 subsystem <- 1217/8620 PCI: 02:00.0 cmd <- 06 done. BS: BS_DEV_ENABLE times (us): entry 235049 run 103700 exit 0 POST: 0x75 Initializing devices... Root Device init ... Root Device init finished in 1947 usecs POST: 0x75 CPU_CLUSTER: 0 init ... MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x00000000d0000000 size 0xcff40000 type 6 0x00000000d0000000 - 0x00000000f0000000 size 0x20000000 type 0 0x00000000f0000000 - 0x00000000f4800000 size 0x04800000 type 1 0x00000000f4800000 - 0x0000000100000000 size 0x0b800000 type 0 0x0000000100000000 - 0x000000012f000000 size 0x2f000000 type 6 MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e call enable_fixed_mtrr() CPU physical address size: 48 bits MTRR: default type WB/UC MTRR counts: 8/6. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000ffff80000000 type 6 MTRR: 1 base 0x0000000080000000 mask 0x0000ffffc0000000 type 6 MTRR: 2 base 0x00000000c0000000 mask 0x0000fffff0000000 type 6 MTRR: 3 base 0x00000000f0000000 mask 0x0000fffffc000000 type 1 MTRR: 4 base 0x00000000f4000000 mask 0x0000ffffff800000 type 1 MTRR: 5 base 0x0000000100000000 mask 0x0000ffffc0000000 type 6 MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Will perform SMM setup. CPU: AMD A4-9120C RADEON R4, 5 COMPUTE CORES 2C+3G . Loading module at 00030000 with entry 00030000. filesize: 0x170 memsize: 0x170 Processing 16 relocs. Offset value of 0x00030000 Attempting to start 1 APs Waiting for 10ms after sending INIT. Waiting for 1st SIPI to complete...AP: slot 1 apic_id 11. done. Waiting for 2nd SIPI to complete...done. Loading module at 00038000 with entry 00038000. filesize: 0x1a8 memsize: 0x1a8 Processing 13 relocs. Offset value of 0x00038000 SMM Module: stub loaded at 00038000. Will call cdeb995b(00000000) Installing SMM handler to 0xce800000 Loading module at ce810000 with entry ce81142b. filesize: 0x6c98 memsize: 0xad18 Processing 481 relocs. Offset value of 0xce810000 Loading module at ce808000 with entry ce808000. filesize: 0x1a8 memsize: 0x1a8 Processing 13 relocs. Offset value of 0xce808000 SMM Module: placing jmp sequence at ce807e00 rel16 0x01fd SMM Module: stub loaded at ce808000. Will call ce81142b(00000000) New SMBASE 0xce800000 Relocation complete. New SMBASE 0xce7ffe00 Relocation complete. Initializing CPU #0 CPU: vendor AMD device 670f00 CPU: family 15, model 70, stepping 00 Setting up local APIC... apic_id: 0x10 done. CPU #0 initialized Initializing CPU #1 CPU: vendor AMD device 670f00 CPU: family 15, model 70, stepping 00 Setting up local APIC... apic_id: 0x11 done. CPU #1 initialized bsp_do_flight_plan done after 91 msecs. MTRR: TEMPORARY Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x00000000d0000000 size 0xcff40000 type 6 0x00000000d0000000 - 0x00000000ff000000 size 0x2f000000 type 0 0x00000000ff000000 - 0x0000000100000000 size 0x01000000 type 5 0x0000000100000000 - 0x000000012f000000 size 0x2f000000 type 6 MTRR: default type WB/UC MTRR counts: 7/5. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000ffff80000000 type 6 MTRR: 1 base 0x0000000080000000 mask 0x0000ffffc0000000 type 6 MTRR: 2 base 0x00000000c0000000 mask 0x0000fffff0000000 type 6 MTRR: 3 base 0x00000000ff000000 mask 0x0000ffffff000000 type 5 MTRR: 4 base 0x0000000100000000 mask 0x0000ffffc0000000 type 6 CPU_CLUSTER: 0 init finished in 345963 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 PCI: 00:00.0 init ... PCI: 00:00.0 init finished in 2002 usecs POST: 0x75 POST: 0x75 PCI: 00:01.0 init ... PCI: 00:01.0 init finished in 2002 usecs POST: 0x75 PCI: 00:01.1 init ... PCI: 00:01.1 init finished in 2001 usecs POST: 0x75 PCI: 00:02.0 init ... PCI: 00:02.0 init finished in 2001 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 PCI: 00:03.0 init ... PCI: 00:03.0 init finished in 2002 usecs POST: 0x75 PCI: 00:08.0 init ... PCI: 00:08.0 init finished in 2001 usecs POST: 0x75 PCI: 00:09.0 init ... PCI: 00:09.0 init finished in 2001 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 PCI: 00:14.0 init ... IOAPIC: Initializing IOAPIC at 0xfec00000 IOAPIC: Bootstrap Processor Local APIC = 0x10 IOAPIC: ID = 0x04 IOAPIC: Dumping registers reg 0x0000: 0x04000000 reg 0x0001: 0x00178021 reg 0x0002: 0x04000000 IOAPIC: 24 interrupts IOAPIC: Enabling interrupts on FSB IOAPIC: reg 0x00000000 value 0x10000000 0x00000700 IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 IOAPIC: reg 0x00000017 value 0x00000000 0x00010000 PCI: 00:14.0 init finished in 133959 usecs POST: 0x75 PCI: 00:14.3 init ... PCI: 00:14.3 init finished in 2060 usecs POST: 0x75 POST: 0x75 PCI: 00:18.0 init ... IOAPIC: Initializing IOAPIC at 0xfec20000 IOAPIC: Bootstrap Processor Local APIC = 0x10 IOAPIC: ID = 0x05 IOAPIC: Dumping registers reg 0x0000: 0x05000000 reg 0x0001: 0x001f8021 reg 0x0002: 0x00000000 IOAPIC: 32 interrupts IOAPIC: Enabling interrupts on FSB IOAPIC: reg 0x00000000 value 0x10000000 0x00000700 IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 IOAPIC: reg 0x00000017 value 0x00000000 0x00010000 IOAPIC: reg 0x00000018 value 0x00000000 0x00010000 IOAPIC: reg 0x00000019 value 0x00000000 0x00010000 IOAPIC: reg 0x0000001a value 0x00000000 0x00010000 IOAPIC: reg 0x0000001b value 0x00000000 0x00010000 IOAPIC: reg 0x0000001c value 0x00000000 0x00010000 IOAPIC: reg 0x0000001d value 0x00000000 0x00010000 IOAPIC: reg 0x0000001e value 0x00000000 0x00010000 IOAPIC: reg 0x0000001f value 0x00000000 0x00010000 PCI: 00:18.0 init finished in 170027 usecs POST: 0x75 PCI: 00:18.1 init ... PCI: 00:18.1 init finished in 2001 usecs POST: 0x75 PCI: 00:18.2 init ... PCI: 00:18.2 init finished in 2001 usecs POST: 0x75 PCI: 00:18.3 init ... PCI: 00:18.3 init finished in 2001 usecs POST: 0x75 PCI: 00:18.4 init ... PCI: 00:18.4 init finished in 2001 usecs POST: 0x75 PCI: 00:18.5 init ... PCI: 00:18.5 init finished in 2001 usecs POST: 0x75 PCI: 01:00.0 init ... PCI: 01:00.0 init finished in 2002 usecs POST: 0x75 PCI: 02:00.0 init ... BayHub BH720: Power-saving enabled (link_ctrl=0x110103) PCI: 02:00.0 init finished in 7127 usecs POST: 0x75 PNP: 0c09.0 init ... Google Chrome EC: Hello got back 11223344 status (0) Google Chrome EC: version: ro: careena_v2.0.11488-7215d6e0e4 rw: careena_v2.0.11488-7215d6e0e4 running image: 1 Google Chrome EC uptime: 131.075 seconds Google Chrome AP resets since EC boot: 0 Google Chrome most recent AP reset causes: Google Chrome EC reset flags at last EC boot: reset-pin PNP: 0c09.0 init finished in 34630 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 Devices initialized Show all devs... After init. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 DOMAIN: 0000: enabled 1 MMIO: fedc2000: enabled 1 MMIO: fedc3000: enabled 1 MMIO: fedc4000: enabled 1 MMIO: fedc5000: enabled 1 APIC: 10: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.2: enabled 0 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 0 PCI: 00:02.2: enabled 1 PCI: 00:02.3: enabled 0 PCI: 00:02.4: enabled 1 PCI: 00:02.5: enabled 0 PCI: 00:08.0: enabled 1 PCI: 00:09.0: enabled 1 PCI: 00:09.2: enabled 0 PCI: 00:10.0: enabled 0 PCI: 00:11.0: enabled 0 PCI: 00:12.0: enabled 0 PCI: 00:14.0: enabled 1 PCI: 00:14.3: enabled 1 PCI: 00:14.7: enabled 0 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 GENERIC: 0.0: enabled 1 I2C: 01:1a: enabled 1 GENERIC: 0.1: enabled 1 I2C: 02:50: enabled 1 I2C: 03:15: enabled 1 I2C: 04:39: enabled 1 I2C: 04:10: enabled 1 PCI: 02:00.0: enabled 1 PNP: 0c09.0: enabled 1 PCI: 00:03.0: enabled 1 PCI: 01:00.0: enabled 1 APIC: 11: enabled 1 BS: BS_DEV_INIT times (us): entry 0 run 947964 exit 140 ELOG: Event(A1) added with size 10 at 2023-08-09 04:55:20 UTC elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x2b POST: 0x76 Finalize devices... Devices finalized FMAP: area RW_NVRAM found @ 467000 (20480 bytes) BS: BS_POST_DEVICE times (us): entry 12889 run 4545 exit 4671 FMAP: area RW_MRC_CACHE found @ 0 (65536 bytes) MRC: Checking cached data update for 'RW_MRC_CACHE'. POST: 0x77 Trying to find the wakeup vector... Looking on 000f0000 for valid checksum Checksum 1 passed Checksum 2 passed all OK RSDP found at 000f0000 RSDT found at cde2e030 ends at cde2e07c FADT found at cde31e60 FACS found at cde2e240 OS waking vector is 0009a1d0 BS: BS_OS_RESUME_CHECK times (us): entry 9570 run 24102 exit 0 agesawrapper_amds3finalrestore() entry S3 volatile data @0xceebe000 0x4160 total bytes agesawrapper_amds3finalrestore() returned AGESA_SUCCESS Lock SMM configuration POST: 0xfe Probing TPM I2C: done! DID_VID 0x00281ae0 Locality already claimed cr50 TPM 2.0 (i2c 1:0x50 id 0x28) Platform hierarchy disablement failed: 5001 POST: 0x78 mp_park_aps done after 0 msecs. Restore GNVS pointer to cde6b000 smm_setup_structures STUB!!! POST: 0xfd <6>[ 23.198937] ACPI: EC: interrupt blocked <6>[ 23.223219] ACPI: Preparing to enter system sleep state S3 <6>[ 23.223967] ACPI: EC: event blocked <6>[ 23.223968] ACPI: EC: EC stopped <6>[ 23.223969] PM: Saving platform NVS memory <6>[ 23.223970] Disabling non-boot CPUs ... <6>[ 23.225360] smpboot: CPU 1 is now offline <6>[ 23.225786] ACPI: Low-level resume complete <6>[ 23.225803] ACPI: EC: EC started <6>[ 23.225804] PM: Restoring platform NVS memory <6>[ 23.225820] LVT offset 0 assigned for vector 0x400 <6>[ 23.226082] Enabling non-boot CPUs ... <6>[ 23.226117] x86: Booting SMP configuration: <6>[ 23.226118] smpboot: Booting Node 0 Processor 1 APIC 0x11 <6>[ 23.226273] microcode: CPU1: patch_level=0x06006705 <6>[ 23.228603] ACPI: \_PR_.P001: Found 2 idle states <6>[ 23.228832] CPU1 is up <6>[ 23.229134] ACPI: Waking up from system sleep state S3 <6>[ 23.256302] ACPI: EC: interrupt unblocked <6>[ 23.282610] ACPI: EC: event unblocked <6>[ 23.283294] [drm] PCIE GART of 1024M enabled (table at 0x000000F400000000). <6>[ 23.283309] amdgpu: smu version 33.09.00 <6>[ 23.553017] usb 1-1.1: reset high-speed USB device number 3 using ehci-pci <6>[ 23.589192] r8152 2-4:1.0 eth0: carrier on <6>[ 23.965598] [drm] UVD initialized successfully. <6>[ 24.066704] [drm] VCE initialized successfully. <6>[ 24.190752] OOM killer enabled. <6>[ 24.194150] Restarting tasks ... done. <6>[ 24.200190] PM: suspend exit rtcwake: assuming RTC uses UTC ... rtcwake: wakeup from "mem" using rtc0 at Wed Aug 9 04:55:27 2023 <6>[ 24.227652] PM: suspend entry (deep) <6>[ 24.231518] Filesystems sync: 0.000 seconds <6>[ 24.236183] Freezing user space processes ... (elapsed 0.001 seconds) done. <6>[ 24.245370] OOM killer disabled. <6>[ 24.248856] Freezing remaining freezable tasks ... (elapsed 1.110 seconds) done. <6>[ 25.372813] printk: Suspending console(s) (use no_console_suspend to debug) coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 smm starting... SMI# #0 SMI#: SLP = 0x0c01 Chrome EC: UHEPI supported Chrome EC: Set SMI mask to 0x0000000000000000 Chrome EC: Set SCI mask to 0x0000000000000000 Clearing pending EC events. Error code 1 is expected. EC returned error result code 9 SMI#: Entering S3 (Suspend-To-RAM) FMAP: Found "FLASH" version 1.1 at d7f000. FMAP: base = ff000000 size = 1000000 #areas = 30 FMAP: area RW_ELOG found @ 45d000 (16384 bytes) Manufacturer: ef SF: Detected W25Q128FW with sector size 0x1000, total 0x1000000 ELOG: NV offset 0x45d000 size 0x4000 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024 ELOG: Event(9D) added with size 10 at 2023-08-09 04:55:22 UTC coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 bootblock starting... Family_Model: 00670f00 PMxC0 STATUS: 0x40200800 BIT30 SleepReset BIT11 DW I2C bus 1 at 0xfedc3000 (400 KHz) VBOOT: Loading verstage. CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'fallback/verstage' CBFS: Found @ offset aa8c0 size d5a4 coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 verstage starting... Probing TPM I2C: done! DID_VID 0x00281ae0 TPM ready after 0 ms cr50 TPM 2.0 (i2c 1:0x50 id 0x28) tlcl_send_startup: Startup return code is 84 src/security/tpm/tss/tcg-2.0/tss.c:177 index 0x1007 return code 100 read_space_firmware():99: Antirollback: 0000500a returned by tlcl_read(FIRMWARE_NV_INDEX, ctx->secdata, VB2_SECDATA_SIZE) antirollback_read_space_firmware():474: TPM: Firmware space in a bad state; giving up. Chrome EC: UHEPI supported Phase 1 VB2:vb2_fail() Need recovery, reason: 0x2b / 0x2 FMAP: Found "FLASH" version 1.1 at d7f000. FMAP: base = ff000000 size = 1000000 #areas = 30 FMAP: area GBB found @ d80000 (458752 bytes) VB2:vb2_check_recovery() Recovery reason from previous boot: 0x2b / 0x2 VB2:vb2_check_recovery() We have a recovery request: 0x2b / 0x0 Clearing TPM owner TPM: Clear and re-enable tlcl_force_clear: response is 100 TPM: Can't initiate a force clear. Recovery requested (1009000e) Saving nvdata tlcl_extend: response is 100 CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'fallback/romstage' CBFS: Found @ offset 80 size d2e4 coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 romstage starting... CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'smu_fw' CBFS: Found @ offset 7bc00 size 12262 PSP: Load blob type 19 from @ffe6bc38... OK POST: 0x37 agesawrapper_amdinitreset() entry CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'AGESA_PRE_MEM' CBFS: Found @ offset df80 size 53bcc agesawrapper_amdinitreset() returned AGESA_SUCCESS POST: 0x38 agesawrapper_amdinitearly() entry Warning - AGESA callout: platform_PcieSlotResetControl not supported Warning - AGESA callout: platform_PcieSlotResetControl not supported agesawrapper_amdinitearly() returned AGESA_SUCCESS S3 detected POST: 0x60 agesawrapper_amdinitresume() entry Chrome EC: UHEPI supported FMAP: Found "FLASH" version 1.1 at d7f000. FMAP: base = ff000000 size = 1000000 #areas = 30 FMAP: area RW_MRC_CACHE found @ 0 (65536 bytes) S3 NV data @0xff0048c0, 0xe65 bytes agesawrapper_amdinitresume() returned AGESA_SUCCESS POST: 0x61 POST: 0x42 PSP: Notify that DRAM is available... OK POST: 0x43 creating vboot_handoff structure Chrome EC: clear events_b mask to 0x0000000021004000 POST: 0x44 MTRR Range: Start=cd000000 End=ce000000 (Size 1000000) MTRR Range: Start=ff000000 End=0 (Size 1000000) MTRR Range: Start=ce800000 End=cf000000 (Size 800000) POST: 0x45 coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 postcar starting... Jumping to image. coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 ramstage starting... POST: 0x39 FMAP: Found "FLASH" version 1.1 at d7f000. FMAP: base = ff000000 size = 1000000 #areas = 30 FMAP: area RO_VPD found @ c00000 (16384 bytes) WARNING: RO_VPD is uninitialized or empty. FMAP: area RW_VPD found @ 465000 (8192 bytes) FMAP: area RW_VPD found @ 465000 (8192 bytes) POST: 0x80 S3 Resume. POST: 0x46 agesawrapper_amds3laterestore() entry AGESA: Loading stage from cache S3 volatile data @0xceebe000 0x4160 total bytes agesawrapper_amds3laterestore() returned AGESA_SUCCESS POST: 0x70 BS: BS_PRE_DEVICE times (us): entry 20400 run 1058 exit 0 POST: 0x71 Board ID: 6 mainboard: EC init Chrome EC: Set SMI mask to 0x0000000000000000 Chrome EC: UHEPI supported Chrome EC: Set SCI mask to 0x00000000142609fb Chrome EC: Set WAKE mask to 0x0000000000000000 DW I2C bus 0 at 0xfedc2000 (400 KHz) DW I2C bus 2 at 0xfedc4000 (400 KHz) DW I2C bus 3 at 0xfedc5000 (400 KHz) FMAP: area RW_ELOG found @ 45d000 (16384 bytes) Manufacturer: ef SF: Detected W25Q128FW with sector size 0x1000, total 0x1000000 ELOG: NV offset 0x45d000 size 0x4000 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024 ELOG: Event(9E) added with size 10 at 2023-08-09 04:55:27 UTC ELOG: Event(9F) added with size 14 at 2023-08-09 04:55:27 UTC PM1_STS: WAK RTC BMSTATUS setup_bsp_ramtop, TOP MEM: msr.lo = 0xd0000000, msr.hi = 0x00000000 setup_bsp_ramtop, TOP MEM2: msr.lo = 0x2f000000, msr.hi = 0x00000001 BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 79986 exit 0 POST: 0x72 Enumerating buses... Show all devs... Before device enumeration. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 DOMAIN: 0000: enabled 1 MMIO: fedc2000: enabled 1 MMIO: fedc3000: enabled 1 MMIO: fedc4000: enabled 1 MMIO: fedc5000: enabled 1 APIC: 10: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.2: enabled 0 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 1 PCI: 00:02.2: enabled 1 PCI: 00:02.3: enabled 1 PCI: 00:02.4: enabled 1 PCI: 00:02.5: enabled 1 PCI: 00:08.0: enabled 1 PCI: 00:09.0: enabled 1 PCI: 00:09.2: enabled 1 PCI: 00:10.0: enabled 1 PCI: 00:11.0: enabled 0 PCI: 00:12.0: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:14.3: enabled 1 PCI: 00:14.7: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 GENERIC: 0.0: enabled 1 I2C: 00:1a: enabled 1 GENERIC: 0.1: enabled 1 I2C: 00:50: enabled 1 I2C: 00:15: enabled 1 I2C: 00:39: enabled 1 I2C: 00:10: enabled 1 PCI: 00:00.0: enabled 1 PNP: 0c09.0: enabled 1 Compare with tree... Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 10: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.2: enabled 0 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 1 PCI: 00:02.2: enabled 1 PCI: 00:02.3: enabled 1 PCI: 00:02.4: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:02.5: enabled 1 PCI: 00:08.0: enabled 1 PCI: 00:09.0: enabled 1 PCI: 00:09.2: enabled 1 PCI: 00:10.0: enabled 1 PCI: 00:11.0: enabled 0 PCI: 00:12.0: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:14.3: enabled 1 PNP: 0c09.0: enabled 1 PCI: 00:14.7: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 MMIO: fedc2000: enabled 1 GENERIC: 0.0: enabled 1 I2C: 00:1a: enabled 1 GENERIC: 0.1: enabled 1 MMIO: fedc3000: enabled 1 I2C: 00:50: enabled 1 MMIO: fedc4000: enabled 1 I2C: 00:15: enabled 1 MMIO: fedc5000: enabled 1 I2C: 00:39: enabled 1 I2C: 00:10: enabled 1 Mainboard Grunt Enable. Root Device scanning... root_dev_scan_bus for Root Device CPU_CLUSTER: 0 enabled DOMAIN: 0000 enabled MMIO: fedc2000 enabled MMIO: fedc3000 enabled MMIO: fedc4000 enabled MMIO: fedc5000 enabled DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 POST: 0x24 sb_enable PCI: 00:00.0 [1022/1576] enabled sb_enable sb_enable PCI: 00:01.0 [1002/98e4] enabled sb_enable PCI: 00:01.1 [1002/15b3] enabled sb_enable PCI: 00:02.0 [1022/157b] enabled sb_enable PCI: Static device PCI: 00:02.1 not found, disabling it. sb_enable Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xc0 Capability: type 0x08 @ 0xc8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 PCI: 00:02.2 subordinate bus PCI Express PCI: 00:02.2 [1022/157c] enabled sb_enable PCI: Static device PCI: 00:02.3 not found, disabling it. sb_enable Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xc0 Capability: type 0x08 @ 0xc8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 PCI: 00:02.4 subordinate bus PCI Express PCI: 00:02.4 [1022/157c] enabled sb_enable PCI: Static device PCI: 00:02.5 not found, disabling it. PCI: 00:03.0 [1022/157b] enabled sb_enable PCI: 00:08.0 [1022/1578] enabled sb_enable PCI: 00:09.0 [1022/157d] enabled sb_enable PCI: Static device PCI: 00:09.2 not found, disabling it. sb_enable PCI: Static device PCI: 00:10.0 not found, disabling it. sb_enable sb_enable PCI: Static device PCI: 00:12.0 not found, disabling it. sb_enable PCI: 00:14.0 [1022/790b] bus ops PCI: 00:14.0 [1022/790b] enabled sb_enable PCI: 00:14.3 [1022/0000] bus ops PCI: 00:14.3 [1022/790e] enabled sb_enable PCI: Static device PCI: 00:14.7 not found, disabling it. sb_enable PCI: 00:18.0 [1022/15b0] ops PCI: 00:18.0 [1022/15b0] enabled sb_enable PCI: 00:18.1 [1022/15b1] enabled sb_enable PCI: 00:18.2 [1022/15b2] enabled sb_enable PCI: 00:18.3 [1022/15b3] enabled sb_enable PCI: 00:18.4 [1022/15b4] enabled sb_enable PCI: 00:18.5 [1022/15b5] enabled POST: 0x25 PCI: 00:02.2 scanning... do_pci_scan_bridge for PCI: 00:02.2 PCI: pci_scan_bus for bus 01 POST: 0x24 PCI: 01:00.0 [168c/003e] enabled POST: 0x25 POST: 0x55 Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x50 Capability: type 0x10 @ 0x70 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Enabling Common Clock Configuration ASPM: Enabled L0s and L1 Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x50 Capability: type 0x10 @ 0x70 scan_bus: scanning of bus PCI: 00:02.2 took 40763 usecs PCI: 00:02.4 scanning... do_pci_scan_bridge for PCI: 00:02.4 PCI: pci_scan_bus for bus 02 POST: 0x24 PCI: 02:00.0 [1217/0000] ops PCI: 02:00.0 [1217/8620] enabled POST: 0x25 POST: 0x55 Capability: type 0x01 @ 0x6c Capability: type 0x05 @ 0x48 Capability: type 0x10 @ 0x80 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 ASPM: Enabled L0s and L1 Capability: type 0x01 @ 0x6c Capability: type 0x05 @ 0x48 Capability: type 0x10 @ 0x80 scan_bus: scanning of bus PCI: 00:02.4 took 40423 usecs PCI: 00:14.0 scanning... scan_generic_bus for PCI: 00:14.0 scan_generic_bus for PCI: 00:14.0 done scan_bus: scanning of bus PCI: 00:14.0 took 8801 usecs PCI: 00:14.3 scanning... scan_lpc_bus for PCI: 00:14.3 PNP: 0c09.0 enabled scan_lpc_bus for PCI: 00:14.3 done scan_bus: scanning of bus PCI: 00:14.3 took 9940 usecs POST: 0x55 scan_bus: scanning of bus DOMAIN: 0000 took 289515 usecs MMIO: fedc2000 scanning... scan_generic_bus for MMIO: fedc2000 bus: MMIO: fedc2000[0]->GENERIC: 0.0 enabled bus: MMIO: fedc2000[0]->I2C: 01:1a enabled bus: MMIO: fedc2000[0]->GENERIC: 0.1 enabled scan_generic_bus for MMIO: fedc2000 done scan_bus: scanning of bus MMIO: fedc2000 took 21216 usecs MMIO: fedc3000 scanning... scan_generic_bus for MMIO: fedc3000 bus: MMIO: fedc3000[0]->I2C: 02:50 enabled scan_generic_bus for MMIO: fedc3000 done scan_bus: scanning of bus MMIO: fedc3000 took 13176 usecs MMIO: fedc4000 scanning... scan_generic_bus for MMIO: fedc4000 bus: MMIO: fedc4000[0]->I2C: 03:15 enabled scan_generic_bus for MMIO: fedc4000 done scan_bus: scanning of bus MMIO: fedc4000 took 13168 usecs MMIO: fedc5000 scanning... scan_generic_bus for MMIO: fedc5000 bus: MMIO: fedc5000[0]->I2C: 04:39 enabled bus: MMIO: fedc5000[0]->I2C: 04:10 enabled scan_generic_bus for MMIO: fedc5000 done scan_bus: scanning of bus MMIO: fedc5000 took 16986 usecs root_dev_scan_bus for Root Device done scan_bus: scanning of bus Root Device took 400658 usecs done BS: BS_DEV_ENUMERATE times (us): entry 0 run 605640 exit 0 POST: 0x73 found VGA at PCI: 00:01.0 Setting up VGA for PCI: 00:01.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done DOMAIN: 0000 read_resources bus 0 link: 0 PCI: 00:02.2 read_resources bus 1 link: 0 PCI: 00:02.2 read_resources bus 1 link: 0 done PCI: 00:02.4 read_resources bus 2 link: 0 PCI: 00:02.4 read_resources bus 2 link: 0 done PCI: 00:14.3 read_resources bus 0 link: 0 PCI: 00:14.3 read_resources bus 0 link: 0 done Adding PCIe enhanced config space BAR 0xf8000000-0xfc000000. DOMAIN: 0000 read_resources bus 0 link: 0 done MMIO: fedc2000 read_resources bus 1 link: 0 MMIO: fedc2000 read_resources bus 1 link: 0 done MMIO: fedc3000 read_resources bus 2 link: 0 MMIO: fedc3000 read_resources bus 2 link: 0 done MMIO: fedc4000 read_resources bus 3 link: 0 MMIO: fedc4000 read_resources bus 3 link: 0 done MMIO: fedc5000 read_resources bus 4 link: 0 MMIO: fedc5000 read_resources bus 4 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 10 APIC: 10 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI: 00:00.0 PCI: 00:00.2 PCI: 00:01.0 PCI: 00:01.0 resource base 0 size 4000000 align 26 gran 26 limit ffffffffffffffff flags 1201 index 10 PCI: 00:01.0 resource base 0 size 800000 align 23 gran 23 limit ffffffffffffffff flags 1201 index 18 PCI: 00:01.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 20 PCI: 00:01.0 resource base 0 size 40000 align 18 gran 18 limit ffffffff flags 200 index 24 PCI: 00:01.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 2200 index 30 PCI: 00:01.1 PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 PCI: 00:02.0 PCI: 00:02.1 PCI: 00:02.2 child on link 0 PCI: 01:00.0 PCI: 00:02.2 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:02.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:02.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 01:00.0 PCI: 01:00.0 resource base 0 size 200000 align 21 gran 21 limit ffffffffffffffff flags 201 index 10 PCI: 00:02.3 PCI: 00:02.4 child on link 0 PCI: 02:00.0 PCI: 00:02.4 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:02.4 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:02.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 02:00.0 PCI: 02:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 02:00.0 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 14 PCI: 00:02.5 PCI: 00:03.0 PCI: 00:08.0 PCI: 00:08.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 1201 index 10 PCI: 00:08.0 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 200 index 18 PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 1c PCI: 00:08.0 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 200 index 20 PCI: 00:08.0 resource base 0 size 2000 align 13 gran 13 limit ffffffff flags 200 index 24 PCI: 00:09.0 PCI: 00:09.2 PCI: 00:10.0 PCI: 00:11.0 PCI: 00:12.0 PCI: 00:14.0 PCI: 00:14.3 child on link 0 PNP: 0c09.0 PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:14.3 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100 PCI: 00:14.3 resource base fec10000 size 400 align 0 gran 0 limit 0 flags e0040200 index 2 PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PCI: 00:14.3 resource base fedc2000 size 4000 align 0 gran 0 limit 0 flags c0000200 index 4 PNP: 0c09.0 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0 PCI: 00:14.7 PCI: 00:18.0 PCI: 00:18.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI: 00:18.0 resource base fec20000 size 1000 align 0 gran 0 limit 0 flags c0000200 index fec20000 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.4 PCI: 00:18.5 MMIO: fedc2000 child on link 0 GENERIC: 0.0 GENERIC: 0.0 I2C: 01:1a GENERIC: 0.1 MMIO: fedc3000 child on link 0 I2C: 02:50 I2C: 02:50 MMIO: fedc4000 child on link 0 I2C: 03:15 I2C: 03:15 MMIO: fedc5000 child on link 0 I2C: 04:39 I2C: 04:39 I2C: 04:10 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:02.2 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:02.2 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:02.4 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:02.4 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:01.0 20 * [0x0 - 0xff] io DOMAIN: 0000 io: base: 100 size: 100 align: 8 gran: 0 limit: ffff done DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:02.2 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:02.2 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:02.2 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 01:00.0 10 * [0x0 - 0x1fffff] mem PCI: 00:02.2 mem: base: 200000 size: 200000 align: 21 gran: 20 limit: ffffffff done PCI: 00:02.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:02.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:02.4 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 02:00.0 10 * [0x0 - 0xfff] mem PCI: 02:00.0 14 * [0x1000 - 0x17ff] mem PCI: 00:02.4 mem: base: 1800 size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:01.0 10 * [0x0 - 0x3ffffff] prefmem PCI: 00:01.0 18 * [0x4000000 - 0x47fffff] prefmem PCI: 00:02.2 20 * [0x4800000 - 0x49fffff] mem PCI: 00:02.4 20 * [0x4a00000 - 0x4afffff] mem PCI: 00:08.0 18 * [0x4b00000 - 0x4bfffff] mem PCI: 00:08.0 20 * [0x4c00000 - 0x4cfffff] mem PCI: 00:01.0 24 * [0x4d00000 - 0x4d3ffff] mem PCI: 00:01.0 30 * [0x4d40000 - 0x4d5ffff] mem PCI: 00:08.0 10 * [0x4d60000 - 0x4d7ffff] prefmem PCI: 00:01.1 10 * [0x4d80000 - 0x4d83fff] mem PCI: 00:08.0 24 * [0x4d84000 - 0x4d85fff] mem PCI: 00:08.0 1c * [0x4d86000 - 0x4d86fff] mem DOMAIN: 0000 mem: base: 4d87000 size: 4d87000 align: 26 gran: 0 limit: ffffffff done avoid_fixed_resources: DOMAIN: 0000 avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI: 00:14.3 10000000 base 00000000 limit 00000fff io (fixed) constrain_resources: PCI: 00:14.3 10000100 base ff000000 limit ffffffff mem (fixed) constrain_resources: PCI: 00:14.3 02 base fec10000 limit fec103ff mem (fixed) constrain_resources: PCI: 00:14.3 03 base fec00000 limit fec00fff mem (fixed) constrain_resources: PCI: 00:18.0 c0010058 base f8000000 limit fbffffff mem (fixed) avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001000 limit 0000ffff avoid_fixed_resources:@DOMAIN: 0000 10000100 base f0000000 limit f7ffffff Setting resources... DOMAIN: 0000 io: base:1000 size:100 align:8 gran:0 limit:ffff PCI: 00:01.0 20 * [0x1000 - 0x10ff] io DOMAIN: 0000 io: next_base: 1100 size: 100 align: 8 gran: 0 done PCI: 00:02.2 io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:02.2 io: next_base: ffff size: 0 align: 12 gran: 12 done PCI: 00:02.4 io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:02.4 io: next_base: ffff size: 0 align: 12 gran: 12 done DOMAIN: 0000 mem: base:f0000000 size:4d87000 align:26 gran:0 limit:f7ffffff PCI: 00:01.0 10 * [0xf0000000 - 0xf3ffffff] prefmem PCI: 00:01.0 18 * [0xf4000000 - 0xf47fffff] prefmem PCI: 00:02.2 20 * [0xf4800000 - 0xf49fffff] mem PCI: 00:02.4 20 * [0xf4a00000 - 0xf4afffff] mem PCI: 00:08.0 18 * [0xf4b00000 - 0xf4bfffff] mem PCI: 00:08.0 20 * [0xf4c00000 - 0xf4cfffff] mem PCI: 00:01.0 24 * [0xf4d00000 - 0xf4d3ffff] mem PCI: 00:01.0 30 * [0xf4d40000 - 0xf4d5ffff] mem PCI: 00:08.0 10 * [0xf4d60000 - 0xf4d7ffff] prefmem PCI: 00:01.1 10 * [0xf4d80000 - 0xf4d83fff] mem PCI: 00:08.0 24 * [0xf4d84000 - 0xf4d85fff] mem PCI: 00:08.0 1c * [0xf4d86000 - 0xf4d86fff] mem DOMAIN: 0000 mem: next_base: f4d87000 size: 4d87000 align: 26 gran: 0 done PCI: 00:02.2 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff PCI: 00:02.2 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done PCI: 00:02.2 mem: base:f4800000 size:200000 align:21 gran:20 limit:f49fffff PCI: 01:00.0 10 * [0xf4800000 - 0xf49fffff] mem PCI: 00:02.2 mem: next_base: f4a00000 size: 200000 align: 21 gran: 20 done PCI: 00:02.4 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff PCI: 00:02.4 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done PCI: 00:02.4 mem: base:f4a00000 size:100000 align:20 gran:20 limit:f4afffff PCI: 02:00.0 10 * [0xf4a00000 - 0xf4a00fff] mem PCI: 02:00.0 14 * [0xf4a01000 - 0xf4a017ff] mem PCI: 00:02.4 mem: next_base: f4a01800 size: 100000 align: 20 gran: 20 done Root Device assign_resources, bus 0 link: 0 DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:01.0 10 <- [0x00f0000000 - 0x00f3ffffff] size 0x04000000 gran 0x1a prefmem64 PCI: 00:01.0 18 <- [0x00f4000000 - 0x00f47fffff] size 0x00800000 gran 0x17 prefmem64 PCI: 00:01.0 20 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io PCI: 00:01.0 24 <- [0x00f4d00000 - 0x00f4d3ffff] size 0x00040000 gran 0x12 mem PCI: 00:01.0 30 <- [0x00f4d40000 - 0x00f4d5ffff] size 0x00020000 gran 0x11 romem PCI: 00:01.1 10 <- [0x00f4d80000 - 0x00f4d83fff] size 0x00004000 gran 0x0e mem64 PCI: 00:02.2 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io PCI: 00:02.2 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 01 prefmem PCI: 00:02.2 20 <- [0x00f4800000 - 0x00f49fffff] size 0x00200000 gran 0x14 bus 01 mem PCI: 00:02.2 assign_resources, bus 1 link: 0 PCI: 01:00.0 10 <- [0x00f4800000 - 0x00f49fffff] size 0x00200000 gran 0x15 mem64 PCI: 00:02.2 assign_resources, bus 1 link: 0 PCI: 00:02.4 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io PCI: 00:02.4 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 02 prefmem PCI: 00:02.4 20 <- [0x00f4a00000 - 0x00f4afffff] size 0x00100000 gran 0x14 bus 02 mem PCI: 00:02.4 assign_resources, bus 2 link: 0 PCI: 02:00.0 10 <- [0x00f4a00000 - 0x00f4a00fff] size 0x00001000 gran 0x0c mem PCI: 02:00.0 14 <- [0x00f4a01000 - 0x00f4a017ff] size 0x00000800 gran 0x0b mem PCI: 00:02.4 assign_resources, bus 2 link: 0 PCI: 00:08.0 10 <- [0x00f4d60000 - 0x00f4d7ffff] size 0x00020000 gran 0x11 prefmem64 PCI: 00:08.0 18 <- [0x00f4b00000 - 0x00f4bfffff] size 0x00100000 gran 0x14 mem PCI: 00:08.0 1c <- [0x00f4d86000 - 0x00f4d86fff] size 0x00001000 gran 0x0c mem PCI: 00:08.0 20 <- [0x00f4c00000 - 0x00f4cfffff] size 0x00100000 gran 0x14 mem PCI: 00:08.0 24 <- [0x00f4d84000 - 0x00f4d85fff] size 0x00002000 gran 0x0d mem PCI: 00:14.3 assign_resources, bus 0 link: 0 PCI: 00:14.3 assign_resources, bus 0 link: 0 DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 10 APIC: 10 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 1000 size 100 align 8 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base f0000000 size 4d87000 align 26 gran 0 limit f7ffffff flags 40040200 index 10000100 DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10 DOMAIN: 0000 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11 DOMAIN: 0000 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12 DOMAIN: 0000 resource base 100000 size cdf00000 align 0 gran 0 limit 0 flags e0004200 index 13 DOMAIN: 0000 resource base ce000000 size 2000000 align 0 gran 0 limit 0 flags f0004200 index 14 DOMAIN: 0000 resource base 100000000 size 2f000000 align 0 gran 0 limit 0 flags e0004200 index 15 PCI: 00:00.0 PCI: 00:00.2 PCI: 00:01.0 PCI: 00:01.0 resource base f0000000 size 4000000 align 26 gran 26 limit f3ffffff flags 60001201 index 10 PCI: 00:01.0 resource base f4000000 size 800000 align 23 gran 23 limit f47fffff flags 60001201 index 18 PCI: 00:01.0 resource base 1000 size 100 align 8 gran 8 limit 10ff flags 60000100 index 20 PCI: 00:01.0 resource base f4d00000 size 40000 align 18 gran 18 limit f4d3ffff flags 60000200 index 24 PCI: 00:01.0 resource base f4d40000 size 20000 align 17 gran 17 limit f4d5ffff flags 60002200 index 30 PCI: 00:01.1 PCI: 00:01.1 resource base f4d80000 size 4000 align 14 gran 14 limit f4d83fff flags 60000201 index 10 PCI: 00:02.0 PCI: 00:02.1 PCI: 00:02.2 child on link 0 PCI: 01:00.0 PCI: 00:02.2 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:02.2 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24 PCI: 00:02.2 resource base f4800000 size 200000 align 21 gran 20 limit f49fffff flags 60080202 index 20 PCI: 01:00.0 PCI: 01:00.0 resource base f4800000 size 200000 align 21 gran 21 limit f49fffff flags 60000201 index 10 PCI: 00:02.3 PCI: 00:02.4 child on link 0 PCI: 02:00.0 PCI: 00:02.4 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:02.4 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24 PCI: 00:02.4 resource base f4a00000 size 100000 align 20 gran 20 limit f4afffff flags 60080202 index 20 PCI: 02:00.0 PCI: 02:00.0 resource base f4a00000 size 1000 align 12 gran 12 limit f4a00fff flags 60000200 index 10 PCI: 02:00.0 resource base f4a01000 size 800 align 12 gran 11 limit f4a017ff flags 60000200 index 14 PCI: 00:02.5 PCI: 00:03.0 PCI: 00:08.0 PCI: 00:08.0 resource base f4d60000 size 20000 align 17 gran 17 limit f4d7ffff flags 60001201 index 10 PCI: 00:08.0 resource base f4b00000 size 100000 align 20 gran 20 limit f4bfffff flags 60000200 index 18 PCI: 00:08.0 resource base f4d86000 size 1000 align 12 gran 12 limit f4d86fff flags 60000200 index 1c PCI: 00:08.0 resource base f4c00000 size 100000 align 20 gran 20 limit f4cfffff flags 60000200 index 20 PCI: 00:08.0 resource base f4d84000 size 2000 align 13 gran 13 limit f4d85fff flags 60000200 index 24 PCI: 00:09.0 PCI: 00:09.2 PCI: 00:10.0 PCI: 00:11.0 PCI: 00:12.0 PCI: 00:14.0 PCI: 00:14.3 child on link 0 PNP: 0c09.0 PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:14.3 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100 PCI: 00:14.3 resource base fec10000 size 400 align 0 gran 0 limit 0 flags e0040200 index 2 PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PCI: 00:14.3 resource base fedc2000 size 4000 align 0 gran 0 limit 0 flags c0000200 index 4 PNP: 0c09.0 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0 PCI: 00:14.7 PCI: 00:18.0 PCI: 00:18.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI: 00:18.0 resource base fec20000 size 1000 align 0 gran 0 limit 0 flags c0000200 index fec20000 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.4 PCI: 00:18.5 MMIO: fedc2000 child on link 0 GENERIC: 0.0 GENERIC: 0.0 I2C: 01:1a GENERIC: 0.1 MMIO: fedc3000 child on link 0 I2C: 02:50 I2C: 02:50 MMIO: fedc4000 child on link 0 I2C: 03:15 I2C: 03:15 MMIO: fedc5000 child on link 0 I2C: 04:39 I2C: 04:39 I2C: 04:10 Done allocating resources. BS: BS_DEV_RESOURCES times (us): entry 0 run 1463971 exit 0 PCI_INTR tables: Writing registers C00/C01 for PCI IRQ routing: PCI_INTR_INDEX name PIC mode APIC mode 0x00 INTA# 0x03 0x10 0x01 INTB# 0x04 0x11 0x02 INTC# 0x05 0x12 0x03 INTD# 0x07 0x13 0x04 INTE# 0x0B 0x14 0x05 INTF# 0x1F 0x1F 0x06 INTG# 0x1F 0x16 0x07 INTH# 0x1F 0x17 0x08 Misc 0xFA 0x00 0x09 Misc0 0xF1 0x00 0x0A Misc1 0x00 0x00 0x0B Misc2 0x00 0x00 0x0C Ser IRQ INTA 0x1F 0x1F 0x0D Ser IRQ INTB 0x1F 0x1F 0x0E Ser IRQ INTC 0x1F 0x1F 0x0F Ser IRQ INTD 0x1F 0x1F 0x10 SCI 0x09 0x09 0x11 SMBUS 0x1F 0x1F 0x12 ASF 0x1F 0x1F 0x13 HDA 0x03 0x10 0x14 FC 0x1F 0x1F 0x16 PerMon 0x1F 0x1F 0x17 SD 0x03 0x10 0x1A SDIOt 0x00 0x1F 0x30 EHCI 0x05 0x12 0x34 XHCI 0x04 0x12 0x41 SATA 0x07 0x13 0x62 GPIO 0x07 0x07 0x70 I2C0 0x03 0x03 0x71 I2C1 0x0F 0x0F 0x72 I2C2 0x06 0x06 0x73 I2C3 0x0E 0x0E 0x74 UART0 0x0A 0x0A 0x75 UART1 0x0B 0x0B PCI_CFG IRQ: Write PCI config space IRQ assignments PCI IRQ: Found device 0:01.00 using PIN A PCI Devfn (0x8) not found in pirq_data table PCI IRQ: Found device 0:01.01 using PIN B Found this device in pirq_data table entry 5 Orig INT_PIN : 2 (PIN B) PCI_INTR idx : 0x13 (HDA) INT_LINE : 0x3 (IRQ 3) PCI IRQ: Found device 0:02.02 using PIN A Found this device in pirq_data table entry 1 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x01 (INTB#) INT_LINE : 0x4 (IRQ 4) PCI IRQ: Found device 0:02.04 using PIN A Found this device in pirq_data table entry 3 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x03 (INTD#) INT_LINE : 0x7 (IRQ 7) PCI IRQ: Found device 0:08.00 using PIN A PCI Devfn (0x40) not found in pirq_data table PCI IRQ: Found device 2:00.00 using PIN A With INT_PIN swizzled to PIN A Attached to bridge device 0:02h.04h Found this device in pirq_data table entry 3 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x03 (INTD#) INT_LINE : 0x7 (IRQ 7) PCI IRQ: Found device 1:00.00 using PIN A With INT_PIN swizzled to PIN A Attached to bridge device 0:02h.02h Found this device in pirq_data table entry 1 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x01 (INTB#) INT_LINE : 0x4 (IRQ 4) PCI_CFG IRQ: Finished writing PCI config space IRQ assignments POST: 0x74 Enabling resources... PCI: 00:00.0 subsystem <- 1022/1576 PCI: 00:00.0 cmd <- 04 PCI: 00:01.0 subsystem <- 1002/98e4 PCI: 00:01.0 cmd <- 07 PCI: 00:01.1 subsystem <- 1002/15b3 PCI: 00:01.1 cmd <- 02 PCI: 00:02.0 subsystem <- 1022/157b PCI: 00:02.0 cmd <- 00 PCI: 00:02.2 bridge ctrl <- 0003 PCI: 00:02.2 cmd <- 06 PCI: 00:02.4 bridge ctrl <- 0003 PCI: 00:02.4 cmd <- 06 PCI: 00:03.0 cmd <- 00 PCI: 00:08.0 subsystem <- 1022/1578 PCI: 00:08.0 cmd <- 06 PCI: 00:09.0 subsystem <- 1022/157d PCI: 00:09.0 cmd <- 00 PCI: 00:14.0 subsystem <- 1022/790b PCI: 00:14.0 cmd <- 403 PCI: 00:14.3 subsystem <- 1022/790e PCI: 00:14.3 cmd <- 0f Southbridge LPC decode:PNP: 0c09.0, base=0x00000800, end=0x000009fe Covered by wideIO 0 PCI: 00:18.0 cmd <- 00 PCI: 00:18.1 subsystem <- 1022/15b1 PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 subsystem <- 1022/15b2 PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 subsystem <- 1022/15b3 PCI: 00:18.3 cmd <- 00 PCI: 00:18.4 subsystem <- 1022/15b4 PCI: 00:18.4 cmd <- 00 PCI: 00:18.5 subsystem <- 1022/15b5 PCI: 00:18.5 cmd <- 00 PCI: 01:00.0 cmd <- 02 PCI: 02:00.0 subsystem <- 1217/8620 PCI: 02:00.0 cmd <- 06 done. BS: BS_DEV_ENABLE times (us): entry 235046 run 103704 exit 0 POST: 0x75 Initializing devices... Root Device init ... Root Device init finished in 1947 usecs POST: 0x75 CPU_CLUSTER: 0 init ... MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x00000000d0000000 size 0xcff40000 type 6 0x00000000d0000000 - 0x00000000f0000000 size 0x20000000 type 0 0x00000000f0000000 - 0x00000000f4800000 size 0x04800000 type 1 0x00000000f4800000 - 0x0000000100000000 size 0x0b800000 type 0 0x0000000100000000 - 0x000000012f000000 size 0x2f000000 type 6 MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e call enable_fixed_mtrr() CPU physical address size: 48 bits MTRR: default type WB/UC MTRR counts: 8/6. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000ffff80000000 type 6 MTRR: 1 base 0x0000000080000000 mask 0x0000ffffc0000000 type 6 MTRR: 2 base 0x00000000c0000000 mask 0x0000fffff0000000 type 6 MTRR: 3 base 0x00000000f0000000 mask 0x0000fffffc000000 type 1 MTRR: 4 base 0x00000000f4000000 mask 0x0000ffffff800000 type 1 MTRR: 5 base 0x0000000100000000 mask 0x0000ffffc0000000 type 6 MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Will perform SMM setup. CPU: AMD A4-9120C RADEON R4, 5 COMPUTE CORES 2C+3G . Loading module at 00030000 with entry 00030000. filesize: 0x170 memsize: 0x170 Processing 16 relocs. Offset value of 0x00030000 Attempting to start 1 APs Waiting for 10ms after sending INIT. Waiting for 1st SIPI to complete...AP: slot 1 apic_id 11. done. Waiting for 2nd SIPI to complete...done. Loading module at 00038000 with entry 00038000. filesize: 0x1a8 memsize: 0x1a8 Processing 13 relocs. Offset value of 0x00038000 SMM Module: stub loaded at 00038000. Will call cdeb995b(00000000) Installing SMM handler to 0xce800000 Loading module at ce810000 with entry ce81142b. filesize: 0x6c98 memsize: 0xad18 Processing 481 relocs. Offset value of 0xce810000 Loading module at ce808000 with entry ce808000. filesize: 0x1a8 memsize: 0x1a8 Processing 13 relocs. Offset value of 0xce808000 SMM Module: placing jmp sequence at ce807e00 rel16 0x01fd SMM Module: stub loaded at ce808000. Will call ce81142b(00000000) New SMBASE 0xce800000 Relocation complete. New SMBASE 0xce7ffe00 Relocation complete. Initializing CPU #0 CPU: vendor AMD device 670f00 CPU: family 15, model 70, stepping 00 Setting up local APIC... apic_id: 0x10 done. CPU #0 initialized Initializing CPU #1 CPU: vendor AMD device 670f00 CPU: family 15, model 70, stepping 00 Setting up local APIC... apic_id: 0x11 done. CPU #1 initialized bsp_do_flight_plan done after 91 msecs. MTRR: TEMPORARY Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x00000000d0000000 size 0xcff40000 type 6 0x00000000d0000000 - 0x00000000ff000000 size 0x2f000000 type 0 0x00000000ff000000 - 0x0000000100000000 size 0x01000000 type 5 0x0000000100000000 - 0x000000012f000000 size 0x2f000000 type 6 MTRR: default type WB/UC MTRR counts: 7/5. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000ffff80000000 type 6 MTRR: 1 base 0x0000000080000000 mask 0x0000ffffc0000000 type 6 MTRR: 2 base 0x00000000c0000000 mask 0x0000fffff0000000 type 6 MTRR: 3 base 0x00000000ff000000 mask 0x0000ffffff000000 type 5 MTRR: 4 base 0x0000000100000000 mask 0x0000ffffc0000000 type 6 CPU_CLUSTER: 0 init finished in 345967 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 PCI: 00:00.0 init ... PCI: 00:00.0 init finished in 2002 usecs POST: 0x75 POST: 0x75 PCI: 00:01.0 init ... PCI: 00:01.0 init finished in 2002 usecs POST: 0x75 PCI: 00:01.1 init ... PCI: 00:01.1 init finished in 2002 usecs POST: 0x75 PCI: 00:02.0 init ... PCI: 00:02.0 init finished in 2002 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 PCI: 00:03.0 init ... PCI: 00:03.0 init finished in 2002 usecs POST: 0x75 PCI: 00:08.0 init ... PCI: 00:08.0 init finished in 2002 usecs POST: 0x75 PCI: 00:09.0 init ... PCI: 00:09.0 init finished in 2002 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 PCI: 00:14.0 init ... IOAPIC: Initializing IOAPIC at 0xfec00000 IOAPIC: Bootstrap Processor Local APIC = 0x10 IOAPIC: ID = 0x04 IOAPIC: Dumping registers reg 0x0000: 0x04000000 reg 0x0001: 0x00178021 reg 0x0002: 0x04000000 IOAPIC: 24 interrupts IOAPIC: Enabling interrupts on FSB IOAPIC: reg 0x00000000 value 0x10000000 0x00000700 IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 IOAPIC: reg 0x00000017 value 0x00000000 0x00010000 PCI: 00:14.0 init finished in 133950 usecs POST: 0x75 PCI: 00:14.3 init ... PCI: 00:14.3 init finished in 2061 usecs POST: 0x75 POST: 0x75 PCI: 00:18.0 init ... IOAPIC: Initializing IOAPIC at 0xfec20000 IOAPIC: Bootstrap Processor Local APIC = 0x10 IOAPIC: ID = 0x05 IOAPIC: Dumping registers reg 0x0000: 0x05000000 reg 0x0001: 0x001f8021 reg 0x0002: 0x00000000 IOAPIC: 32 interrupts IOAPIC: Enabling interrupts on FSB IOAPIC: reg 0x00000000 value 0x10000000 0x00000700 IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 IOAPIC: reg 0x00000017 value 0x00000000 0x00010000 IOAPIC: reg 0x00000018 value 0x00000000 0x00010000 IOAPIC: reg 0x00000019 value 0x00000000 0x00010000 IOAPIC: reg 0x0000001a value 0x00000000 0x00010000 IOAPIC: reg 0x0000001b value 0x00000000 0x00010000 IOAPIC: reg 0x0000001c value 0x00000000 0x00010000 IOAPIC: reg 0x0000001d value 0x00000000 0x00010000 IOAPIC: reg 0x0000001e value 0x00000000 0x00010000 IOAPIC: reg 0x0000001f value 0x00000000 0x00010000 PCI: 00:18.0 init finished in 170043 usecs POST: 0x75 PCI: 00:18.1 init ... PCI: 00:18.1 init finished in 2002 usecs POST: 0x75 PCI: 00:18.2 init ... PCI: 00:18.2 init finished in 2002 usecs POST: 0x75 PCI: 00:18.3 init ... PCI: 00:18.3 init finished in 2002 usecs POST: 0x75 PCI: 00:18.4 init ... PCI: 00:18.4 init finished in 2002 usecs POST: 0x75 PCI: 00:18.5 init ... PCI: 00:18.5 init finished in 2002 usecs POST: 0x75 PCI: 01:00.0 init ... PCI: 01:00.0 init finished in 2002 usecs POST: 0x75 PCI: 02:00.0 init ... BayHub BH720: Power-saving enabled (link_ctrl=0x110103) PCI: 02:00.0 init finished in 7127 usecs POST: 0x75 PNP: 0c09.0 init ... Google Chrome EC: Hello got back 11223344 status (0) Google Chrome EC: version: ro: careena_v2.0.11488-7215d6e0e4 rw: careena_v2.0.11488-7215d6e0e4 running image: 1 Google Chrome EC uptime: 141.967 seconds Google Chrome AP resets since EC boot: 0 Google Chrome most recent AP reset causes: Google Chrome EC reset flags at last EC boot: reset-pin PNP: 0c09.0 init finished in 34640 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 Devices initialized Show all devs... After init. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 DOMAIN: 0000: enabled 1 MMIO: fedc2000: enabled 1 MMIO: fedc3000: enabled 1 MMIO: fedc4000: enabled 1 MMIO: fedc5000: enabled 1 APIC: 10: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.2: enabled 0 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 0 PCI: 00:02.2: enabled 1 PCI: 00:02.3: enabled 0 PCI: 00:02.4: enabled 1 PCI: 00:02.5: enabled 0 PCI: 00:08.0: enabled 1 PCI: 00:09.0: enabled 1 PCI: 00:09.2: enabled 0 PCI: 00:10.0: enabled 0 PCI: 00:11.0: enabled 0 PCI: 00:12.0: enabled 0 PCI: 00:14.0: enabled 1 PCI: 00:14.3: enabled 1 PCI: 00:14.7: enabled 0 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 GENERIC: 0.0: enabled 1 I2C: 01:1a: enabled 1 GENERIC: 0.1: enabled 1 I2C: 02:50: enabled 1 I2C: 03:15: enabled 1 I2C: 04:39: enabled 1 I2C: 04:10: enabled 1 PCI: 02:00.0: enabled 1 PNP: 0c09.0: enabled 1 PCI: 00:03.0: enabled 1 PCI: 01:00.0: enabled 1 APIC: 11: enabled 1 BS: BS_DEV_INIT times (us): entry 0 run 948036 exit 141 ELOG: Event(A1) added with size 10 at 2023-08-09 04:55:31 UTC elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x2b POST: 0x76 Finalize devices... Devices finalized FMAP: area RW_NVRAM found @ 467000 (20480 bytes) BS: BS_POST_DEVICE times (us): entry 12901 run 4545 exit 4677 FMAP: area RW_MRC_CACHE found @ 0 (65536 bytes) MRC: Checking cached data update for 'RW_MRC_CACHE'. POST: 0x77 Trying to find the wakeup vector... Looking on 000f0000 for valid checksum Checksum 1 passed Checksum 2 passed all OK RSDP found at 000f0000 RSDT found at cde2e030 ends at cde2e07c FADT found at cde31e60 FACS found at cde2e240 OS waking vector is 0009a1d0 BS: BS_OS_RESUME_CHECK times (us): entry 9602 run 24100 exit 0 agesawrapper_amds3finalrestore() entry S3 volatile data @0xceebe000 0x4160 total bytes agesawrapper_amds3finalrestore() returned AGESA_SUCCESS Lock SMM configuration POST: 0xfe Probing TPM I2C: done! DID_VID 0x00281ae0 Locality already claimed cr50 TPM 2.0 (i2c 1:0x50 id 0x28) Platform hierarchy disablement failed: 5001 POST: 0x78 mp_park_aps done after 0 msecs. Restore GNVS pointer to cde6b000 smm_setup_structures STUB!!! POST: 0xfd <6>[ 25.456704] ACPI: EC: interrupt blocked <6>[ 25.480553] ACPI: Preparing to enter system sleep state S3 <6>[ 25.481305] ACPI: EC: event blocked <6>[ 25.481306] ACPI: EC: EC stopped <6>[ 25.481307] PM: Saving platform NVS memory <6>[ 25.481308] Disabling non-boot CPUs ... <6>[ 25.482711] smpboot: CPU 1 is now offline <6>[ 25.483122] ACPI: Low-level resume complete <6>[ 25.483139] ACPI: EC: EC started <6>[ 25.483140] PM: Restoring platform NVS memory <6>[ 25.483157] LVT offset 0 assigned for vector 0x400 <6>[ 25.483418] Enabling non-boot CPUs ... <6>[ 25.483453] x86: Booting SMP configuration: <6>[ 25.483454] smpboot: Booting Node 0 Processor 1 APIC 0x11 <6>[ 25.483610] microcode: CPU1: patch_level=0x06006705 <6>[ 25.485946] ACPI: \_PR_.P001: Found 2 idle states <6>[ 25.486167] CPU1 is up <6>[ 25.486470] ACPI: Waking up from system sleep state S3 <6>[ 25.513629] ACPI: EC: interrupt unblocked <6>[ 25.539419] ACPI: EC: event unblocked <6>[ 25.540117] [drm] PCIE GART of 1024M enabled (table at 0x000000F400000000). <6>[ 25.540147] amdgpu: smu version 33.09.00 <6>[ 25.802515] usb 1-1.1: reset high-speed USB device number 3 using ehci-pci <6>[ 25.813687] r8152 2-4:1.0 eth0: carrier on <6>[ 26.219362] [drm] UVD initialized successfully. <6>[ 26.320038] [drm] VCE initialized successfully. <6>[ 26.445813] OOM killer enabled. <6>[ 26.449211] Restarting tasks ... done. <6>[ 26.454340] PM: suspend exit rtcwake: assuming RTC uses UTC ... rtcwake: wakeup from "mem" using rtc0 at Wed Aug 9 04:55:38 2023 <6>[ 26.481582] PM: suspend entry (deep) <6>[ 26.485440] Filesystems sync: 0.000 seconds <6>[ 26.490035] Freezing user space processes ... (elapsed 0.001 seconds) done. <6>[ 26.498887] OOM killer disabled. <6>[ 26.502372] Freezing remaining freezable tasks ... (elapsed 1.112 seconds) done. <6>[ 27.641116] printk: Suspending console(s) (use no_console_suspend to debug) coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 smm starting... SMI# #0 SMI#: SLP = 0x0c01 Chrome EC: UHEPI supported Chrome EC: Set SMI mask to 0x0000000000000000 Chrome EC: Set SCI mask to 0x0000000000000000 Clearing pending EC events. Error code 1 is expected. EC returned error result code 9 SMI#: Entering S3 (Suspend-To-RAM) FMAP: Found "FLASH" version 1.1 at d7f000. FMAP: base = ff000000 size = 1000000 #areas = 30 FMAP: area RW_ELOG found @ 45d000 (16384 bytes) Manufacturer: ef SF: Detected W25Q128FW with sector size 0x1000, total 0x1000000 ELOG: NV offset 0x45d000 size 0x4000 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024 ELOG: Event(9D) added with size 10 at 2023-08-09 04:55:33 UTC coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 bootblock starting... Family_Model: 00670f00 PMxC0 STATUS: 0x40200800 BIT30 SleepReset BIT11 DW I2C bus 1 at 0xfedc3000 (400 KHz) VBOOT: Loading verstage. CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'fallback/verstage' CBFS: Found @ offset aa8c0 size d5a4 coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 verstage starting... Probing TPM I2C: done! DID_VID 0x00281ae0 TPM ready after 0 ms cr50 TPM 2.0 (i2c 1:0x50 id 0x28) tlcl_send_startup: Startup return code is 84 src/security/tpm/tss/tcg-2.0/tss.c:177 index 0x1007 return code 100 read_space_firmware():99: Antirollback: 0000500a returned by tlcl_read(FIRMWARE_NV_INDEX, ctx->secdata, VB2_SECDATA_SIZE) antirollback_read_space_firmware():474: TPM: Firmware space in a bad state; giving up. Chrome EC: UHEPI supported Phase 1 VB2:vb2_fail() Need recovery, reason: 0x2b / 0x2 FMAP: Found "FLASH" version 1.1 at d7f000. FMAP: base = ff000000 size = 1000000 #areas = 30 FMAP: area GBB found @ d80000 (458752 bytes) VB2:vb2_check_recovery() Recovery reason from previous boot: 0x2b / 0x2 VB2:vb2_check_recovery() We have a recovery request: 0x2b / 0x0 Clearing TPM owner TPM: Clear and re-enable tlcl_force_clear: response is 100 TPM: Can't initiate a force clear. Recovery requested (1009000e) Saving nvdata tlcl_extend: response is 100 CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'fallback/romstage' CBFS: Found @ offset 80 size d2e4 coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 romstage starting... CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'smu_fw' CBFS: Found @ offset 7bc00 size 12262 PSP: Load blob type 19 from @ffe6bc38... OK POST: 0x37 agesawrapper_amdinitreset() entry CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'AGESA_PRE_MEM' CBFS: Found @ offset df80 size 53bcc agesawrapper_amdinitreset() returned AGESA_SUCCESS POST: 0x38 agesawrapper_amdinitearly() entry Warning - AGESA callout: platform_PcieSlotResetControl not supported Warning - AGESA callout: platform_PcieSlotResetControl not supported agesawrapper_amdinitearly() returned AGESA_SUCCESS S3 detected POST: 0x60 agesawrapper_amdinitresume() entry Chrome EC: UHEPI supported FMAP: Found "FLASH" version 1.1 at d7f000. FMAP: base = ff000000 size = 1000000 #areas = 30 FMAP: area RW_MRC_CACHE found @ 0 (65536 bytes) S3 NV data @0xff0048c0, 0xe65 bytes agesawrapper_amdinitresume() returned AGESA_SUCCESS POST: 0x61 POST: 0x42 PSP: Notify that DRAM is available... OK POST: 0x43 creating vboot_handoff structure Chrome EC: clear events_b mask to 0x0000000021004000 POST: 0x44 MTRR Range: Start=cd000000 End=ce000000 (Size 1000000) MTRR Range: Start=ff000000 End=0 (Size 1000000) MTRR Range: Start=ce800000 End=cf000000 (Size 800000) POST: 0x45 coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 postcar starting... Jumping to image. coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 ramstage starting... POST: 0x39 FMAP: Found "FLASH" version 1.1 at d7f000. FMAP: base = ff000000 size = 1000000 #areas = 30 FMAP: area RO_VPD found @ c00000 (16384 bytes) WARNING: RO_VPD is uninitialized or empty. FMAP: area RW_VPD found @ 465000 (8192 bytes) FMAP: area RW_VPD found @ 465000 (8192 bytes) POST: 0x80 S3 Resume. POST: 0x46 agesawrapper_amds3laterestore() entry AGESA: Loading stage from cache S3 volatile data @0xceebe000 0x4160 total bytes agesawrapper_amds3laterestore() returned AGESA_SUCCESS POST: 0x70 BS: BS_PRE_DEVICE times (us): entry 20388 run 1061 exit 0 POST: 0x71 Board ID: 6 mainboard: EC init Chrome EC: Set SMI mask to 0x0000000000000000 Chrome EC: UHEPI supported Chrome EC: Set SCI mask to 0x00000000142609fb Chrome EC: Set WAKE mask to 0x0000000000000000 DW I2C bus 0 at 0xfedc2000 (400 KHz) DW I2C bus 2 at 0xfedc4000 (400 KHz) DW I2C bus 3 at 0xfedc5000 (400 KHz) FMAP: area RW_ELOG found @ 45d000 (16384 bytes) Manufacturer: ef SF: Detected W25Q128FW with sector size 0x1000, total 0x1000000 ELOG: NV offset 0x45d000 size 0x4000 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024 ELOG: Event(9E) added with size 10 at 2023-08-09 04:55:38 UTC ELOG: Event(9F) added with size 14 at 2023-08-09 04:55:38 UTC PM1_STS: WAK RTC BMSTATUS setup_bsp_ramtop, TOP MEM: msr.lo = 0xd0000000, msr.hi = 0x00000000 setup_bsp_ramtop, TOP MEM2: msr.lo = 0x2f000000, msr.hi = 0x00000001 BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 79920 exit 1 POST: 0x72 Enumerating buses... Show all devs... Before device enumeration. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 DOMAIN: 0000: enabled 1 MMIO: fedc2000: enabled 1 MMIO: fedc3000: enabled 1 MMIO: fedc4000: enabled 1 MMIO: fedc5000: enabled 1 APIC: 10: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.2: enabled 0 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 1 PCI: 00:02.2: enabled 1 PCI: 00:02.3: enabled 1 PCI: 00:02.4: enabled 1 PCI: 00:02.5: enabled 1 PCI: 00:08.0: enabled 1 PCI: 00:09.0: enabled 1 PCI: 00:09.2: enabled 1 PCI: 00:10.0: enabled 1 PCI: 00:11.0: enabled 0 PCI: 00:12.0: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:14.3: enabled 1 PCI: 00:14.7: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 GENERIC: 0.0: enabled 1 I2C: 00:1a: enabled 1 GENERIC: 0.1: enabled 1 I2C: 00:50: enabled 1 I2C: 00:15: enabled 1 I2C: 00:39: enabled 1 I2C: 00:10: enabled 1 PCI: 00:00.0: enabled 1 PNP: 0c09.0: enabled 1 Compare with tree... Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 10: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.2: enabled 0 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 1 PCI: 00:02.2: enabled 1 PCI: 00:02.3: enabled 1 PCI: 00:02.4: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:02.5: enabled 1 PCI: 00:08.0: enabled 1 PCI: 00:09.0: enabled 1 PCI: 00:09.2: enabled 1 PCI: 00:10.0: enabled 1 PCI: 00:11.0: enabled 0 PCI: 00:12.0: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:14.3: enabled 1 PNP: 0c09.0: enabled 1 PCI: 00:14.7: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 MMIO: fedc2000: enabled 1 GENERIC: 0.0: enabled 1 I2C: 00:1a: enabled 1 GENERIC: 0.1: enabled 1 MMIO: fedc3000: enabled 1 I2C: 00:50: enabled 1 MMIO: fedc4000: enabled 1 I2C: 00:15: enabled 1 MMIO: fedc5000: enabled 1 I2C: 00:39: enabled 1 I2C: 00:10: enabled 1 Mainboard Grunt Enable. Root Device scanning... root_dev_scan_bus for Root Device CPU_CLUSTER: 0 enabled DOMAIN: 0000 enabled MMIO: fedc2000 enabled MMIO: fedc3000 enabled MMIO: fedc4000 enabled MMIO: fedc5000 enabled DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 POST: 0x24 sb_enable PCI: 00:00.0 [1022/1576] enabled sb_enable sb_enable PCI: 00:01.0 [1002/98e4] enabled sb_enable PCI: 00:01.1 [1002/15b3] enabled sb_enable PCI: 00:02.0 [1022/157b] enabled sb_enable PCI: Static device PCI: 00:02.1 not found, disabling it. sb_enable Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xc0 Capability: type 0x08 @ 0xc8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 PCI: 00:02.2 subordinate bus PCI Express PCI: 00:02.2 [1022/157c] enabled sb_enable PCI: Static device PCI: 00:02.3 not found, disabling it. sb_enable Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xc0 Capability: type 0x08 @ 0xc8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 PCI: 00:02.4 subordinate bus PCI Express PCI: 00:02.4 [1022/157c] enabled sb_enable PCI: Static device PCI: 00:02.5 not found, disabling it. PCI: 00:03.0 [1022/157b] enabled sb_enable PCI: 00:08.0 [1022/1578] enabled sb_enable PCI: 00:09.0 [1022/157d] enabled sb_enable PCI: Static device PCI: 00:09.2 not found, disabling it. sb_enable PCI: Static device PCI: 00:10.0 not found, disabling it. sb_enable sb_enable PCI: Static device PCI: 00:12.0 not found, disabling it. sb_enable PCI: 00:14.0 [1022/790b] bus ops PCI: 00:14.0 [1022/790b] enabled sb_enable PCI: 00:14.3 [1022/0000] bus ops PCI: 00:14.3 [1022/790e] enabled sb_enable PCI: Static device PCI: 00:14.7 not found, disabling it. sb_enable PCI: 00:18.0 [1022/15b0] ops PCI: 00:18.0 [1022/15b0] enabled sb_enable PCI: 00:18.1 [1022/15b1] enabled sb_enable PCI: 00:18.2 [1022/15b2] enabled sb_enable PCI: 00:18.3 [1022/15b3] enabled sb_enable PCI: 00:18.4 [1022/15b4] enabled sb_enable PCI: 00:18.5 [1022/15b5] enabled POST: 0x25 PCI: 00:02.2 scanning... do_pci_scan_bridge for PCI: 00:02.2 PCI: pci_scan_bus for bus 01 POST: 0x24 PCI: 01:00.0 [168c/003e] enabled POST: 0x25 POST: 0x55 Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x50 Capability: type 0x10 @ 0x70 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Enabling Common Clock Configuration ASPM: Enabled L0s and L1 Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x50 Capability: type 0x10 @ 0x70 scan_bus: scanning of bus PCI: 00:02.2 took 40760 usecs PCI: 00:02.4 scanning... do_pci_scan_bridge for PCI: 00:02.4 PCI: pci_scan_bus for bus 02 POST: 0x24 PCI: 02:00.0 [1217/0000] ops PCI: 02:00.0 [1217/8620] enabled POST: 0x25 POST: 0x55 Capability: type 0x01 @ 0x6c Capability: type 0x05 @ 0x48 Capability: type 0x10 @ 0x80 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 ASPM: Enabled L0s and L1 Capability: type 0x01 @ 0x6c Capability: type 0x05 @ 0x48 Capability: type 0x10 @ 0x80 scan_bus: scanning of bus PCI: 00:02.4 took 40400 usecs PCI: 00:14.0 scanning... scan_generic_bus for PCI: 00:14.0 scan_generic_bus for PCI: 00:14.0 done scan_bus: scanning of bus PCI: 00:14.0 took 8804 usecs PCI: 00:14.3 scanning... scan_lpc_bus for PCI: 00:14.3 PNP: 0c09.0 enabled scan_lpc_bus for PCI: 00:14.3 done scan_bus: scanning of bus PCI: 00:14.3 took 9945 usecs POST: 0x55 scan_bus: scanning of bus DOMAIN: 0000 took 289505 usecs MMIO: fedc2000 scanning... scan_generic_bus for MMIO: fedc2000 bus: MMIO: fedc2000[0]->GENERIC: 0.0 enabled bus: MMIO: fedc2000[0]->I2C: 01:1a enabled bus: MMIO: fedc2000[0]->GENERIC: 0.1 enabled scan_generic_bus for MMIO: fedc2000 done scan_bus: scanning of bus MMIO: fedc2000 took 21211 usecs MMIO: fedc3000 scanning... scan_generic_bus for MMIO: fedc3000 bus: MMIO: fedc3000[0]->I2C: 02:50 enabled scan_generic_bus for MMIO: fedc3000 done scan_bus: scanning of bus MMIO: fedc3000 took 13192 usecs MMIO: fedc4000 scanning... scan_generic_bus for MMIO: fedc4000 bus: MMIO: fedc4000[0]->I2C: 03:15 enabled scan_generic_bus for MMIO: fedc4000 done scan_bus: scanning of bus MMIO: fedc4000 took 13151 usecs MMIO: fedc5000 scanning... scan_generic_bus for MMIO: fedc5000 bus: MMIO: fedc5000[0]->I2C: 04:39 enabled bus: MMIO: fedc5000[0]->I2C: 04:10 enabled scan_generic_bus for MMIO: fedc5000 done scan_bus: scanning of bus MMIO: fedc5000 took 16983 usecs root_dev_scan_bus for Root Device done scan_bus: scanning of bus Root Device took 400673 usecs done BS: BS_DEV_ENUMERATE times (us): entry 0 run 605665 exit 0 POST: 0x73 found VGA at PCI: 00:01.0 Setting up VGA for PCI: 00:01.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done DOMAIN: 0000 read_resources bus 0 link: 0 PCI: 00:02.2 read_resources bus 1 link: 0 PCI: 00:02.2 read_resources bus 1 link: 0 done PCI: 00:02.4 read_resources bus 2 link: 0 PCI: 00:02.4 read_resources bus 2 link: 0 done PCI: 00:14.3 read_resources bus 0 link: 0 PCI: 00:14.3 read_resources bus 0 link: 0 done Adding PCIe enhanced config space BAR 0xf8000000-0xfc000000. DOMAIN: 0000 read_resources bus 0 link: 0 done MMIO: fedc2000 read_resources bus 1 link: 0 MMIO: fedc2000 read_resources bus 1 link: 0 done MMIO: fedc3000 read_resources bus 2 link: 0 MMIO: fedc3000 read_resources bus 2 link: 0 done MMIO: fedc4000 read_resources bus 3 link: 0 MMIO: fedc4000 read_resources bus 3 link: 0 done MMIO: fedc5000 read_resources bus 4 link: 0 MMIO: fedc5000 read_resources bus 4 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 10 APIC: 10 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI: 00:00.0 PCI: 00:00.2 PCI: 00:01.0 PCI: 00:01.0 resource base 0 size 4000000 align 26 gran 26 limit ffffffffffffffff flags 1201 index 10 PCI: 00:01.0 resource base 0 size 800000 align 23 gran 23 limit ffffffffffffffff flags 1201 index 18 PCI: 00:01.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 20 PCI: 00:01.0 resource base 0 size 40000 align 18 gran 18 limit ffffffff flags 200 index 24 PCI: 00:01.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 2200 index 30 PCI: 00:01.1 PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 PCI: 00:02.0 PCI: 00:02.1 PCI: 00:02.2 child on link 0 PCI: 01:00.0 PCI: 00:02.2 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:02.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:02.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 01:00.0 PCI: 01:00.0 resource base 0 size 200000 align 21 gran 21 limit ffffffffffffffff flags 201 index 10 PCI: 00:02.3 PCI: 00:02.4 child on link 0 PCI: 02:00.0 PCI: 00:02.4 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:02.4 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:02.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 02:00.0 PCI: 02:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 02:00.0 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 14 PCI: 00:02.5 PCI: 00:03.0 PCI: 00:08.0 PCI: 00:08.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 1201 index 10 PCI: 00:08.0 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 200 index 18 PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 1c PCI: 00:08.0 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 200 index 20 PCI: 00:08.0 resource base 0 size 2000 align 13 gran 13 limit ffffffff flags 200 index 24 PCI: 00:09.0 PCI: 00:09.2 PCI: 00:10.0 PCI: 00:11.0 PCI: 00:12.0 PCI: 00:14.0 PCI: 00:14.3 child on link 0 PNP: 0c09.0 PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:14.3 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100 PCI: 00:14.3 resource base fec10000 size 400 align 0 gran 0 limit 0 flags e0040200 index 2 PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PCI: 00:14.3 resource base fedc2000 size 4000 align 0 gran 0 limit 0 flags c0000200 index 4 PNP: 0c09.0 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0 PCI: 00:14.7 PCI: 00:18.0 PCI: 00:18.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI: 00:18.0 resource base fec20000 size 1000 align 0 gran 0 limit 0 flags c0000200 index fec20000 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.4 PCI: 00:18.5 MMIO: fedc2000 child on link 0 GENERIC: 0.0 GENERIC: 0.0 I2C: 01:1a GENERIC: 0.1 MMIO: fedc3000 child on link 0 I2C: 02:50 I2C: 02:50 MMIO: fedc4000 child on link 0 I2C: 03:15 I2C: 03:15 MMIO: fedc5000 child on link 0 I2C: 04:39 I2C: 04:39 I2C: 04:10 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:02.2 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:02.2 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:02.4 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:02.4 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:01.0 20 * [0x0 - 0xff] io DOMAIN: 0000 io: base: 100 size: 100 align: 8 gran: 0 limit: ffff done DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:02.2 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:02.2 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:02.2 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 01:00.0 10 * [0x0 - 0x1fffff] mem PCI: 00:02.2 mem: base: 200000 size: 200000 align: 21 gran: 20 limit: ffffffff done PCI: 00:02.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:02.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:02.4 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 02:00.0 10 * [0x0 - 0xfff] mem PCI: 02:00.0 14 * [0x1000 - 0x17ff] mem PCI: 00:02.4 mem: base: 1800 size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:01.0 10 * [0x0 - 0x3ffffff] prefmem PCI: 00:01.0 18 * [0x4000000 - 0x47fffff] prefmem PCI: 00:02.2 20 * [0x4800000 - 0x49fffff] mem PCI: 00:02.4 20 * [0x4a00000 - 0x4afffff] mem PCI: 00:08.0 18 * [0x4b00000 - 0x4bfffff] mem PCI: 00:08.0 20 * [0x4c00000 - 0x4cfffff] mem PCI: 00:01.0 24 * [0x4d00000 - 0x4d3ffff] mem PCI: 00:01.0 30 * [0x4d40000 - 0x4d5ffff] mem PCI: 00:08.0 10 * [0x4d60000 - 0x4d7ffff] prefmem PCI: 00:01.1 10 * [0x4d80000 - 0x4d83fff] mem PCI: 00:08.0 24 * [0x4d84000 - 0x4d85fff] mem PCI: 00:08.0 1c * [0x4d86000 - 0x4d86fff] mem DOMAIN: 0000 mem: base: 4d87000 size: 4d87000 align: 26 gran: 0 limit: ffffffff done avoid_fixed_resources: DOMAIN: 0000 avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI: 00:14.3 10000000 base 00000000 limit 00000fff io (fixed) constrain_resources: PCI: 00:14.3 10000100 base ff000000 limit ffffffff mem (fixed) constrain_resources: PCI: 00:14.3 02 base fec10000 limit fec103ff mem (fixed) constrain_resources: PCI: 00:14.3 03 base fec00000 limit fec00fff mem (fixed) constrain_resources: PCI: 00:18.0 c0010058 base f8000000 limit fbffffff mem (fixed) avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001000 limit 0000ffff avoid_fixed_resources:@DOMAIN: 0000 10000100 base f0000000 limit f7ffffff Setting resources... DOMAIN: 0000 io: base:1000 size:100 align:8 gran:0 limit:ffff PCI: 00:01.0 20 * [0x1000 - 0x10ff] io DOMAIN: 0000 io: next_base: 1100 size: 100 align: 8 gran: 0 done PCI: 00:02.2 io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:02.2 io: next_base: ffff size: 0 align: 12 gran: 12 done PCI: 00:02.4 io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:02.4 io: next_base: ffff size: 0 align: 12 gran: 12 done DOMAIN: 0000 mem: base:f0000000 size:4d87000 align:26 gran:0 limit:f7ffffff PCI: 00:01.0 10 * [0xf0000000 - 0xf3ffffff] prefmem PCI: 00:01.0 18 * [0xf4000000 - 0xf47fffff] prefmem PCI: 00:02.2 20 * [0xf4800000 - 0xf49fffff] mem PCI: 00:02.4 20 * [0xf4a00000 - 0xf4afffff] mem PCI: 00:08.0 18 * [0xf4b00000 - 0xf4bfffff] mem PCI: 00:08.0 20 * [0xf4c00000 - 0xf4cfffff] mem PCI: 00:01.0 24 * [0xf4d00000 - 0xf4d3ffff] mem PCI: 00:01.0 30 * [0xf4d40000 - 0xf4d5ffff] mem PCI: 00:08.0 10 * [0xf4d60000 - 0xf4d7ffff] prefmem PCI: 00:01.1 10 * [0xf4d80000 - 0xf4d83fff] mem PCI: 00:08.0 24 * [0xf4d84000 - 0xf4d85fff] mem PCI: 00:08.0 1c * [0xf4d86000 - 0xf4d86fff] mem DOMAIN: 0000 mem: next_base: f4d87000 size: 4d87000 align: 26 gran: 0 done PCI: 00:02.2 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff PCI: 00:02.2 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done PCI: 00:02.2 mem: base:f4800000 size:200000 align:21 gran:20 limit:f49fffff PCI: 01:00.0 10 * [0xf4800000 - 0xf49fffff] mem PCI: 00:02.2 mem: next_base: f4a00000 size: 200000 align: 21 gran: 20 done PCI: 00:02.4 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff PCI: 00:02.4 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done PCI: 00:02.4 mem: base:f4a00000 size:100000 align:20 gran:20 limit:f4afffff PCI: 02:00.0 10 * [0xf4a00000 - 0xf4a00fff] mem PCI: 02:00.0 14 * [0xf4a01000 - 0xf4a017ff] mem PCI: 00:02.4 mem: next_base: f4a01800 size: 100000 align: 20 gran: 20 done Root Device assign_resources, bus 0 link: 0 DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:01.0 10 <- [0x00f0000000 - 0x00f3ffffff] size 0x04000000 gran 0x1a prefmem64 PCI: 00:01.0 18 <- [0x00f4000000 - 0x00f47fffff] size 0x00800000 gran 0x17 prefmem64 PCI: 00:01.0 20 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io PCI: 00:01.0 24 <- [0x00f4d00000 - 0x00f4d3ffff] size 0x00040000 gran 0x12 mem PCI: 00:01.0 30 <- [0x00f4d40000 - 0x00f4d5ffff] size 0x00020000 gran 0x11 romem PCI: 00:01.1 10 <- [0x00f4d80000 - 0x00f4d83fff] size 0x00004000 gran 0x0e mem64 PCI: 00:02.2 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io PCI: 00:02.2 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 01 prefmem PCI: 00:02.2 20 <- [0x00f4800000 - 0x00f49fffff] size 0x00200000 gran 0x14 bus 01 mem PCI: 00:02.2 assign_resources, bus 1 link: 0 PCI: 01:00.0 10 <- [0x00f4800000 - 0x00f49fffff] size 0x00200000 gran 0x15 mem64 PCI: 00:02.2 assign_resources, bus 1 link: 0 PCI: 00:02.4 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io PCI: 00:02.4 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 02 prefmem PCI: 00:02.4 20 <- [0x00f4a00000 - 0x00f4afffff] size 0x00100000 gran 0x14 bus 02 mem PCI: 00:02.4 assign_resources, bus 2 link: 0 PCI: 02:00.0 10 <- [0x00f4a00000 - 0x00f4a00fff] size 0x00001000 gran 0x0c mem PCI: 02:00.0 14 <- [0x00f4a01000 - 0x00f4a017ff] size 0x00000800 gran 0x0b mem PCI: 00:02.4 assign_resources, bus 2 link: 0 PCI: 00:08.0 10 <- [0x00f4d60000 - 0x00f4d7ffff] size 0x00020000 gran 0x11 prefmem64 PCI: 00:08.0 18 <- [0x00f4b00000 - 0x00f4bfffff] size 0x00100000 gran 0x14 mem PCI: 00:08.0 1c <- [0x00f4d86000 - 0x00f4d86fff] size 0x00001000 gran 0x0c mem PCI: 00:08.0 20 <- [0x00f4c00000 - 0x00f4cfffff] size 0x00100000 gran 0x14 mem PCI: 00:08.0 24 <- [0x00f4d84000 - 0x00f4d85fff] size 0x00002000 gran 0x0d mem PCI: 00:14.3 assign_resources, bus 0 link: 0 PCI: 00:14.3 assign_resources, bus 0 link: 0 DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 10 APIC: 10 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 1000 size 100 align 8 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base f0000000 size 4d87000 align 26 gran 0 limit f7ffffff flags 40040200 index 10000100 DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10 DOMAIN: 0000 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11 DOMAIN: 0000 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12 DOMAIN: 0000 resource base 100000 size cdf00000 align 0 gran 0 limit 0 flags e0004200 index 13 DOMAIN: 0000 resource base ce000000 size 2000000 align 0 gran 0 limit 0 flags f0004200 index 14 DOMAIN: 0000 resource base 100000000 size 2f000000 align 0 gran 0 limit 0 flags e0004200 index 15 PCI: 00:00.0 PCI: 00:00.2 PCI: 00:01.0 PCI: 00:01.0 resource base f0000000 size 4000000 align 26 gran 26 limit f3ffffff flags 60001201 index 10 PCI: 00:01.0 resource base f4000000 size 800000 align 23 gran 23 limit f47fffff flags 60001201 index 18 PCI: 00:01.0 resource base 1000 size 100 align 8 gran 8 limit 10ff flags 60000100 index 20 PCI: 00:01.0 resource base f4d00000 size 40000 align 18 gran 18 limit f4d3ffff flags 60000200 index 24 PCI: 00:01.0 resource base f4d40000 size 20000 align 17 gran 17 limit f4d5ffff flags 60002200 index 30 PCI: 00:01.1 PCI: 00:01.1 resource base f4d80000 size 4000 align 14 gran 14 limit f4d83fff flags 60000201 index 10 PCI: 00:02.0 PCI: 00:02.1 PCI: 00:02.2 child on link 0 PCI: 01:00.0 PCI: 00:02.2 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:02.2 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24 PCI: 00:02.2 resource base f4800000 size 200000 align 21 gran 20 limit f49fffff flags 60080202 index 20 PCI: 01:00.0 PCI: 01:00.0 resource base f4800000 size 200000 align 21 gran 21 limit f49fffff flags 60000201 index 10 PCI: 00:02.3 PCI: 00:02.4 child on link 0 PCI: 02:00.0 PCI: 00:02.4 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:02.4 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24 PCI: 00:02.4 resource base f4a00000 size 100000 align 20 gran 20 limit f4afffff flags 60080202 index 20 PCI: 02:00.0 PCI: 02:00.0 resource base f4a00000 size 1000 align 12 gran 12 limit f4a00fff flags 60000200 index 10 PCI: 02:00.0 resource base f4a01000 size 800 align 12 gran 11 limit f4a017ff flags 60000200 index 14 PCI: 00:02.5 PCI: 00:03.0 PCI: 00:08.0 PCI: 00:08.0 resource base f4d60000 size 20000 align 17 gran 17 limit f4d7ffff flags 60001201 index 10 PCI: 00:08.0 resource base f4b00000 size 100000 align 20 gran 20 limit f4bfffff flags 60000200 index 18 PCI: 00:08.0 resource base f4d86000 size 1000 align 12 gran 12 limit f4d86fff flags 60000200 index 1c PCI: 00:08.0 resource base f4c00000 size 100000 align 20 gran 20 limit f4cfffff flags 60000200 index 20 PCI: 00:08.0 resource base f4d84000 size 2000 align 13 gran 13 limit f4d85fff flags 60000200 index 24 PCI: 00:09.0 PCI: 00:09.2 PCI: 00:10.0 PCI: 00:11.0 PCI: 00:12.0 PCI: 00:14.0 PCI: 00:14.3 child on link 0 PNP: 0c09.0 PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:14.3 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100 PCI: 00:14.3 resource base fec10000 size 400 align 0 gran 0 limit 0 flags e0040200 index 2 PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PCI: 00:14.3 resource base fedc2000 size 4000 align 0 gran 0 limit 0 flags c0000200 index 4 PNP: 0c09.0 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0 PCI: 00:14.7 PCI: 00:18.0 PCI: 00:18.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI: 00:18.0 resource base fec20000 size 1000 align 0 gran 0 limit 0 flags c0000200 index fec20000 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.4 PCI: 00:18.5 MMIO: fedc2000 child on link 0 GENERIC: 0.0 GENERIC: 0.0 I2C: 01:1a GENERIC: 0.1 MMIO: fedc3000 child on link 0 I2C: 02:50 I2C: 02:50 MMIO: fedc4000 child on link 0 I2C: 03:15 I2C: 03:15 MMIO: fedc5000 child on link 0 I2C: 04:39 I2C: 04:39 I2C: 04:10 Done allocating resources. BS: BS_DEV_RESOURCES times (us): entry 0 run 1463951 exit 0 PCI_INTR tables: Writing registers C00/C01 for PCI IRQ routing: PCI_INTR_INDEX name PIC mode APIC mode 0x00 INTA# 0x03 0x10 0x01 INTB# 0x04 0x11 0x02 INTC# 0x05 0x12 0x03 INTD# 0x07 0x13 0x04 INTE# 0x0B 0x14 0x05 INTF# 0x1F 0x1F 0x06 INTG# 0x1F 0x16 0x07 INTH# 0x1F 0x17 0x08 Misc 0xFA 0x00 0x09 Misc0 0xF1 0x00 0x0A Misc1 0x00 0x00 0x0B Misc2 0x00 0x00 0x0C Ser IRQ INTA 0x1F 0x1F 0x0D Ser IRQ INTB 0x1F 0x1F 0x0E Ser IRQ INTC 0x1F 0x1F 0x0F Ser IRQ INTD 0x1F 0x1F 0x10 SCI 0x09 0x09 0x11 SMBUS 0x1F 0x1F 0x12 ASF 0x1F 0x1F 0x13 HDA 0x03 0x10 0x14 FC 0x1F 0x1F 0x16 PerMon 0x1F 0x1F 0x17 SD 0x03 0x10 0x1A SDIOt 0x00 0x1F 0x30 EHCI 0x05 0x12 0x34 XHCI 0x04 0x12 0x41 SATA 0x07 0x13 0x62 GPIO 0x07 0x07 0x70 I2C0 0x03 0x03 0x71 I2C1 0x0F 0x0F 0x72 I2C2 0x06 0x06 0x73 I2C3 0x0E 0x0E 0x74 UART0 0x0A 0x0A 0x75 UART1 0x0B 0x0B PCI_CFG IRQ: Write PCI config space IRQ assignments PCI IRQ: Found device 0:01.00 using PIN A PCI Devfn (0x8) not found in pirq_data table PCI IRQ: Found device 0:01.01 using PIN B Found this device in pirq_data table entry 5 Orig INT_PIN : 2 (PIN B) PCI_INTR idx : 0x13 (HDA) INT_LINE : 0x3 (IRQ 3) PCI IRQ: Found device 0:02.02 using PIN A Found this device in pirq_data table entry 1 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x01 (INTB#) INT_LINE : 0x4 (IRQ 4) PCI IRQ: Found device 0:02.04 using PIN A Found this device in pirq_data table entry 3 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x03 (INTD#) INT_LINE : 0x7 (IRQ 7) PCI IRQ: Found device 0:08.00 using PIN A PCI Devfn (0x40) not found in pirq_data table PCI IRQ: Found device 2:00.00 using PIN A With INT_PIN swizzled to PIN A Attached to bridge device 0:02h.04h Found this device in pirq_data table entry 3 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x03 (INTD#) INT_LINE : 0x7 (IRQ 7) PCI IRQ: Found device 1:00.00 using PIN A With INT_PIN swizzled to PIN A Attached to bridge device 0:02h.02h Found this device in pirq_data table entry 1 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x01 (INTB#) INT_LINE : 0x4 (IRQ 4) PCI_CFG IRQ: Finished writing PCI config space IRQ assignments POST: 0x74 Enabling resources... PCI: 00:00.0 subsystem <- 1022/1576 PCI: 00:00.0 cmd <- 04 PCI: 00:01.0 subsystem <- 1002/98e4 PCI: 00:01.0 cmd <- 07 PCI: 00:01.1 subsystem <- 1002/15b3 PCI: 00:01.1 cmd <- 02 PCI: 00:02.0 subsystem <- 1022/157b PCI: 00:02.0 cmd <- 00 PCI: 00:02.2 bridge ctrl <- 0003 PCI: 00:02.2 cmd <- 06 PCI: 00:02.4 bridge ctrl <- 0003 PCI: 00:02.4 cmd <- 06 PCI: 00:03.0 cmd <- 00 PCI: 00:08.0 subsystem <- 1022/1578 PCI: 00:08.0 cmd <- 06 PCI: 00:09.0 subsystem <- 1022/157d PCI: 00:09.0 cmd <- 00 PCI: 00:14.0 subsystem <- 1022/790b PCI: 00:14.0 cmd <- 403 PCI: 00:14.3 subsystem <- 1022/790e PCI: 00:14.3 cmd <- 0f Southbridge LPC decode:PNP: 0c09.0, base=0x00000800, end=0x000009fe Covered by wideIO 0 PCI: 00:18.0 cmd <- 00 PCI: 00:18.1 subsystem <- 1022/15b1 PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 subsystem <- 1022/15b2 PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 subsystem <- 1022/15b3 PCI: 00:18.3 cmd <- 00 PCI: 00:18.4 subsystem <- 1022/15b4 PCI: 00:18.4 cmd <- 00 PCI: 00:18.5 subsystem <- 1022/15b5 PCI: 00:18.5 cmd <- 00 PCI: 01:00.0 cmd <- 02 PCI: 02:00.0 subsystem <- 1217/8620 PCI: 02:00.0 cmd <- 06 done. BS: BS_DEV_ENABLE times (us): entry 235071 run 103722 exit 0 POST: 0x75 Initializing devices... Root Device init ... Root Device init finished in 1949 usecs POST: 0x75 CPU_CLUSTER: 0 init ... MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x00000000d0000000 size 0xcff40000 type 6 0x00000000d0000000 - 0x00000000f0000000 size 0x20000000 type 0 0x00000000f0000000 - 0x00000000f4800000 size 0x04800000 type 1 0x00000000f4800000 - 0x0000000100000000 size 0x0b800000 type 0 0x0000000100000000 - 0x000000012f000000 size 0x2f000000 type 6 MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e call enable_fixed_mtrr() CPU physical address size: 48 bits MTRR: default type WB/UC MTRR counts: 8/6. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000ffff80000000 type 6 MTRR: 1 base 0x0000000080000000 mask 0x0000ffffc0000000 type 6 MTRR: 2 base 0x00000000c0000000 mask 0x0000fffff0000000 type 6 MTRR: 3 base 0x00000000f0000000 mask 0x0000fffffc000000 type 1 MTRR: 4 base 0x00000000f4000000 mask 0x0000ffffff800000 type 1 MTRR: 5 base 0x0000000100000000 mask 0x0000ffffc0000000 type 6 MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Will perform SMM setup. CPU: AMD A4-9120C RADEON R4, 5 COMPUTE CORES 2C+3G . Loading module at 00030000 with entry 00030000. filesize: 0x170 memsize: 0x170 Processing 16 relocs. Offset value of 0x00030000 Attempting to start 1 APs Waiting for 10ms after sending INIT. Waiting for 1st SIPI to complete...AP: slot 1 apic_id 11. done. Waiting for 2nd SIPI to complete...done. Loading module at 00038000 with entry 00038000. filesize: 0x1a8 memsize: 0x1a8 Processing 13 relocs. Offset value of 0x00038000 SMM Module: stub loaded at 00038000. Will call cdeb995b(00000000) Installing SMM handler to 0xce800000 Loading module at ce810000 with entry ce81142b. filesize: 0x6c98 memsize: 0xad18 Processing 481 relocs. Offset value of 0xce810000 Loading module at ce808000 with entry ce808000. filesize: 0x1a8 memsize: 0x1a8 Processing 13 relocs. Offset value of 0xce808000 SMM Module: placing jmp sequence at ce807e00 rel16 0x01fd SMM Module: stub loaded at ce808000. Will call ce81142b(00000000) New SMBASE 0xce800000 Relocation complete. New SMBASE 0xce7ffe00 Relocation complete. Initializing CPU #0 CPU: vendor AMD device 670f00 CPU: family 15, model 70, stepping 00 Setting up local APIC... apic_id: 0x10 done. CPU #0 initialized Initializing CPU #1 CPU: vendor AMD device 670f00 CPU: family 15, model 70, stepping 00 Setting up local APIC... apic_id: 0x11 done. CPU #1 initialized bsp_do_flight_plan done after 91 msecs. MTRR: TEMPORARY Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x00000000d0000000 size 0xcff40000 type 6 0x00000000d0000000 - 0x00000000ff000000 size 0x2f000000 type 0 0x00000000ff000000 - 0x0000000100000000 size 0x01000000 type 5 0x0000000100000000 - 0x000000012f000000 size 0x2f000000 type 6 MTRR: default type WB/UC MTRR counts: 7/5. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000ffff80000000 type 6 MTRR: 1 base 0x0000000080000000 mask 0x0000ffffc0000000 type 6 MTRR: 2 base 0x00000000c0000000 mask 0x0000fffff0000000 type 6 MTRR: 3 base 0x00000000ff000000 mask 0x0000ffffff000000 type 5 MTRR: 4 base 0x0000000100000000 mask 0x0000ffffc0000000 type 6 CPU_CLUSTER: 0 init finished in 345946 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 PCI: 00:00.0 init ... PCI: 00:00.0 init finished in 2002 usecs POST: 0x75 POST: 0x75 PCI: 00:01.0 init ... PCI: 00:01.0 init finished in 2002 usecs POST: 0x75 PCI: 00:01.1 init ... PCI: 00:01.1 init finished in 2002 usecs POST: 0x75 PCI: 00:02.0 init ... PCI: 00:02.0 init finished in 2001 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 PCI: 00:03.0 init ... PCI: 00:03.0 init finished in 2002 usecs POST: 0x75 PCI: 00:08.0 init ... PCI: 00:08.0 init finished in 2001 usecs POST: 0x75 PCI: 00:09.0 init ... PCI: 00:09.0 init finished in 2001 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 PCI: 00:14.0 init ... IOAPIC: Initializing IOAPIC at 0xfec00000 IOAPIC: Bootstrap Processor Local APIC = 0x10 IOAPIC: ID = 0x04 IOAPIC: Dumping registers reg 0x0000: 0x04000000 reg 0x0001: 0x00178021 reg 0x0002: 0x04000000 IOAPIC: 24 interrupts IOAPIC: Enabling interrupts on FSB IOAPIC: reg 0x00000000 value 0x10000000 0x00000700 IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 IOAPIC: reg 0x00000017 value 0x00000000 0x00010000 PCI: 00:14.0 init finished in 133956 usecs POST: 0x75 PCI: 00:14.3 init ... PCI: 00:14.3 init finished in 2060 usecs POST: 0x75 POST: 0x75 PCI: 00:18.0 init ... IOAPIC: Initializing IOAPIC at 0xfec20000 IOAPIC: Bootstrap Processor Local APIC = 0x10 IOAPIC: ID = 0x05 IOAPIC: Dumping registers reg 0x0000: 0x05000000 reg 0x0001: 0x001f8021 reg 0x0002: 0x00000000 IOAPIC: 32 interrupts IOAPIC: Enabling interrupts on FSB IOAPIC: reg 0x00000000 value 0x10000000 0x00000700 IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 IOAPIC: reg 0x00000017 value 0x00000000 0x00010000 IOAPIC: reg 0x00000018 value 0x00000000 0x00010000 IOAPIC: reg 0x00000019 value 0x00000000 0x00010000 IOAPIC: reg 0x0000001a value 0x00000000 0x00010000 IOAPIC: reg 0x0000001b value 0x00000000 0x00010000 IOAPIC: reg 0x0000001c value 0x00000000 0x00010000 IOAPIC: reg 0x0000001d value 0x00000000 0x00010000 IOAPIC: reg 0x0000001e value 0x00000000 0x00010000 IOAPIC: reg 0x0000001f value 0x00000000 0x00010000 PCI: 00:18.0 init finished in 170040 usecs POST: 0x75 PCI: 00:18.1 init ... PCI: 00:18.1 init finished in 2002 usecs POST: 0x75 PCI: 00:18.2 init ... PCI: 00:18.2 init finished in 2002 usecs POST: 0x75 PCI: 00:18.3 init ... PCI: 00:18.3 init finished in 2001 usecs POST: 0x75 PCI: 00:18.4 init ... PCI: 00:18.4 init finished in 2001 usecs POST: 0x75 PCI: 00:18.5 init ... PCI: 00:18.5 init finished in 2001 usecs POST: 0x75 PCI: 01:00.0 init ... PCI: 01:00.0 init finished in 2002 usecs POST: 0x75 PCI: 02:00.0 init ... BayHub BH720: Power-saving enabled (link_ctrl=0x110103) PCI: 02:00.0 init finished in 7127 usecs POST: 0x75 PNP: 0c09.0 init ... Google Chrome EC: Hello got back 11223344 status (0) Google Chrome EC: version: ro: careena_v2.0.11488-7215d6e0e4 rw: careena_v2.0.11488-7215d6e0e4 running image: 1 Google Chrome EC uptime: 152.951 seconds Google Chrome AP resets since EC boot: 0 Google Chrome most recent AP reset causes: Google Chrome EC reset flags at last EC boot: reset-pin PNP: 0c09.0 init finished in 34631 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 Devices initialized Show all devs... After init. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 DOMAIN: 0000: enabled 1 MMIO: fedc2000: enabled 1 MMIO: fedc3000: enabled 1 MMIO: fedc4000: enabled 1 MMIO: fedc5000: enabled 1 APIC: 10: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.2: enabled 0 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 0 PCI: 00:02.2: enabled 1 PCI: 00:02.3: enabled 0 PCI: 00:02.4: enabled 1 PCI: 00:02.5: enabled 0 PCI: 00:08.0: enabled 1 PCI: 00:09.0: enabled 1 PCI: 00:09.2: enabled 0 PCI: 00:10.0: enabled 0 PCI: 00:11.0: enabled 0 PCI: 00:12.0: enabled 0 PCI: 00:14.0: enabled 1 PCI: 00:14.3: enabled 1 PCI: 00:14.7: enabled 0 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 GENERIC: 0.0: enabled 1 I2C: 01:1a: enabled 1 GENERIC: 0.1: enabled 1 I2C: 02:50: enabled 1 I2C: 03:15: enabled 1 I2C: 04:39: enabled 1 I2C: 04:10: enabled 1 PCI: 02:00.0: enabled 1 PNP: 0c09.0: enabled 1 PCI: 00:03.0: enabled 1 PCI: 01:00.0: enabled 1 APIC: 11: enabled 1 BS: BS_DEV_INIT times (us): entry 0 run 948007 exit 140 ELOG: Event(A1) added with size 10 at 2023-08-09 04:55:42 UTC elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x2b POST: 0x76 Finalize devices... Devices finalized FMAP: area RW_NVRAM found @ 467000 (20480 bytes) BS: BS_POST_DEVICE times (us): entry 12921 run 4542 exit 4671 FMAP: area RW_MRC_CACHE found @ 0 (65536 bytes) MRC: Checking cached data update for 'RW_MRC_CACHE'. POST: 0x77 Trying to find the wakeup vector... Looking on 000f0000 for valid checksum Checksum 1 passed Checksum 2 passed all OK RSDP found at 000f0000 RSDT found at cde2e030 ends at cde2e07c FADT found at cde31e60 FACS found at cde2e240 OS waking vector is 0009a1d0 BS: BS_OS_RESUME_CHECK times (us): entry 9565 run 24101 exit 0 agesawrapper_amds3finalrestore() entry S3 volatile data @0xceebe000 0x4160 total bytes agesawrapper_amds3finalrestore() returned AGESA_SUCCESS Lock SMM configuration POST: 0xfe Probing TPM I2C: done! DID_VID 0x00281ae0 Locality already claimed cr50 TPM 2.0 (i2c 1:0x50 id 0x28) Platform hierarchy disablement failed: 5001 POST: 0x78 mp_park_aps done after 0 msecs. Restore GNVS pointer to cde6b000 smm_setup_structures STUB!!! POST: 0xfd <6>[ 27.724713] ACPI: EC: interrupt blocked <6>[ 27.748689] ACPI: Preparing to enter system sleep state S3 <6>[ 27.749479] ACPI: EC: event blocked <6>[ 27.749480] ACPI: EC: EC stopped <6>[ 27.749481] PM: Saving platform NVS memory <6>[ 27.749482] Disabling non-boot CPUs ... <6>[ 27.750903] smpboot: CPU 1 is now offline <6>[ 27.751335] ACPI: Low-level resume complete <6>[ 27.751351] ACPI: EC: EC started <6>[ 27.751352] PM: Restoring platform NVS memory <6>[ 27.751369] LVT offset 0 assigned for vector 0x400 <6>[ 27.751614] Enabling non-boot CPUs ... <6>[ 27.751649] x86: Booting SMP configuration: <6>[ 27.751650] smpboot: Booting Node 0 Processor 1 APIC 0x11 <6>[ 27.751803] microcode: CPU1: patch_level=0x06006705 <6>[ 27.754126] ACPI: \_PR_.P001: Found 2 idle states <6>[ 27.754350] CPU1 is up <6>[ 27.754653] ACPI: Waking up from system sleep state S3 <6>[ 27.781824] ACPI: EC: interrupt unblocked <6>[ 27.808400] ACPI: EC: event unblocked <6>[ 27.809118] [drm] PCIE GART of 1024M enabled (table at 0x000000F400000000). <6>[ 27.809133] amdgpu: smu version 33.09.00 <6>[ 28.078891] usb 1-1.1: reset high-speed USB device number 3 using ehci-pci <6>[ 28.115111] r8152 2-4:1.0 eth0: carrier on <6>[ 28.491962] [drm] UVD initialized successfully. <6>[ 28.593147] [drm] VCE initialized successfully. <6>[ 28.718812] OOM killer enabled. <6>[ 28.722210] Restarting tasks ... done. <6>[ 28.728254] PM: suspend exit rtcwake: assuming RTC uses UTC ... rtcwake: wakeup from "mem" using rtc0 at Wed Aug 9 04:55:49 2023 <6>[ 28.756503] PM: suspend entry (deep) <6>[ 28.760370] Filesystems sync: 0.000 seconds <6>[ 28.764951] Freezing user space processes ... (elapsed 0.001 seconds) done. <6>[ 28.774045] OOM killer disabled. <6>[ 28.777528] Freezing remaining freezable tasks ... (elapsed 1.097 seconds) done. <6>[ 29.897410] printk: Suspending console(s) (use no_console_suspend to debug) coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 smm starting... SMI# #0 SMI#: SLP = 0x0c01 Chrome EC: UHEPI supported Chrome EC: Set SMI mask to 0x0000000000000000 Chrome EC: Set SCI mask to 0x0000000000000000 Clearing pending EC events. Error code 1 is expected. EC returned error result code 9 SMI#: Entering S3 (Suspend-To-RAM) FMAP: Found "FLASH" version 1.1 at d7f000. FMAP: base = ff000000 size = 1000000 #areas = 30 FMAP: area RW_ELOG found @ 45d000 (16384 bytes) Manufacturer: ef SF: Detected W25Q128FW with sector size 0x1000, total 0x1000000 ELOG: NV offset 0x45d000 size 0x4000 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024 ELOG: Event(9D) added with size 10 at 2023-08-09 04:55:44 UTC coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 bootblock starting... Family_Model: 00670f00 PMxC0 STATUS: 0x40200800 BIT30 SleepReset BIT11 DW I2C bus 1 at 0xfedc3000 (400 KHz) VBOOT: Loading verstage. CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'fallback/verstage' CBFS: Found @ offset aa8c0 size d5a4 coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 verstage starting... Probing TPM I2C: done! DID_VID 0x00281ae0 TPM ready after 0 ms cr50 TPM 2.0 (i2c 1:0x50 id 0x28) tlcl_send_startup: Startup return code is 84 src/security/tpm/tss/tcg-2.0/tss.c:177 index 0x1007 return code 100 read_space_firmware():99: Antirollback: 0000500a returned by tlcl_read(FIRMWARE_NV_INDEX, ctx->secdata, VB2_SECDATA_SIZE) antirollback_read_space_firmware():474: TPM: Firmware space in a bad state; giving up. Chrome EC: UHEPI supported Phase 1 VB2:vb2_fail() Need recovery, reason: 0x2b / 0x2 FMAP: Found "FLASH" version 1.1 at d7f000. FMAP: base = ff000000 size = 1000000 #areas = 30 FMAP: area GBB found @ d80000 (458752 bytes) VB2:vb2_check_recovery() Recovery reason from previous boot: 0x2b / 0x2 VB2:vb2_check_recovery() We have a recovery request: 0x2b / 0x0 Clearing TPM owner TPM: Clear and re-enable tlcl_force_clear: response is 100 TPM: Can't initiate a force clear. Recovery requested (1009000e) Saving nvdata tlcl_extend: response is 100 CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'fallback/romstage' CBFS: Found @ offset 80 size d2e4 coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 romstage starting... CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'smu_fw' CBFS: Found @ offset 7bc00 size 12262 PSP: Load blob type 19 from @ffe6bc38... OK POST: 0x37 agesawrapper_amdinitreset() entry CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'AGESA_PRE_MEM' CBFS: Found @ offset df80 size 53bcc agesawrapper_amdinitreset() returned AGESA_SUCCESS POST: 0x38 agesawrapper_amdinitearly() entry Warning - AGESA callout: platform_PcieSlotResetControl not supported Warning - AGESA callout: platform_PcieSlotResetControl not supported agesawrapper_amdinitearly() returned AGESA_SUCCESS S3 detected POST: 0x60 agesawrapper_amdinitresume() entry Chrome EC: UHEPI supported FMAP: Found "FLASH" version 1.1 at d7f000. FMAP: base = ff000000 size = 1000000 #areas = 30 FMAP: area RW_MRC_CACHE found @ 0 (65536 bytes) S3 NV data @0xff0048c0, 0xe65 bytes agesawrapper_amdinitresume() returned AGESA_SUCCESS POST: 0x61 POST: 0x42 PSP: Notify that DRAM is available... OK POST: 0x43 creating vboot_handoff structure Chrome EC: clear events_b mask to 0x0000000021004000 POST: 0x44 MTRR Range: Start=cd000000 End=ce000000 (Size 1000000) MTRR Range: Start=ff000000 End=0 (Size 1000000) MTRR Range: Start=ce800000 End=cf000000 (Size 800000) POST: 0x45 coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 postcar starting... Jumping to image. coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 ramstage starting... POST: 0x39 FMAP: Found "FLASH" version 1.1 at d7f000. FMAP: base = ff000000 size = 1000000 #areas = 30 FMAP: area RO_VPD found @ c00000 (16384 bytes) WARNING: RO_VPD is uninitialized or empty. FMAP: area RW_VPD found @ 465000 (8192 bytes) FMAP: area RW_VPD found @ 465000 (8192 bytes) POST: 0x80 S3 Resume. POST: 0x46 agesawrapper_amds3laterestore() entry AGESA: Loading stage from cache S3 volatile data @0xceebe000 0x4160 total bytes agesawrapper_amds3laterestore() returned AGESA_SUCCESS POST: 0x70 BS: BS_PRE_DEVICE times (us): entry 20017 run 1058 exit 0 POST: 0x71 Board ID: 6 mainboard: EC init Chrome EC: Set SMI mask to 0x0000000000000000 Chrome EC: UHEPI supported Chrome EC: Set SCI mask to 0x00000000142609fb Chrome EC: Set WAKE mask to 0x0000000000000000 DW I2C bus 0 at 0xfedc2000 (400 KHz) DW I2C bus 2 at 0xfedc4000 (400 KHz) DW I2C bus 3 at 0xfedc5000 (400 KHz) FMAP: area RW_ELOG found @ 45d000 (16384 bytes) Manufacturer: ef SF: Detected W25Q128FW with sector size 0x1000, total 0x1000000 ELOG: NV offset 0x45d000 size 0x4000 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024 ELOG: Event(9E) added with size 10 at 2023-08-09 04:55:49 UTC ELOG: Event(9F) added with size 14 at 2023-08-09 04:55:49 UTC PM1_STS: WAK RTC BMSTATUS setup_bsp_ramtop, TOP MEM: msr.lo = 0xd0000000, msr.hi = 0x00000000 setup_bsp_ramtop, TOP MEM2: msr.lo = 0x2f000000, msr.hi = 0x00000001 BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 79963 exit 1 POST: 0x72 Enumerating buses... Show all devs... Before device enumeration. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 DOMAIN: 0000: enabled 1 MMIO: fedc2000: enabled 1 MMIO: fedc3000: enabled 1 MMIO: fedc4000: enabled 1 MMIO: fedc5000: enabled 1 APIC: 10: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.2: enabled 0 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 1 PCI: 00:02.2: enabled 1 PCI: 00:02.3: enabled 1 PCI: 00:02.4: enabled 1 PCI: 00:02.5: enabled 1 PCI: 00:08.0: enabled 1 PCI: 00:09.0: enabled 1 PCI: 00:09.2: enabled 1 PCI: 00:10.0: enabled 1 PCI: 00:11.0: enabled 0 PCI: 00:12.0: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:14.3: enabled 1 PCI: 00:14.7: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 GENERIC: 0.0: enabled 1 I2C: 00:1a: enabled 1 GENERIC: 0.1: enabled 1 I2C: 00:50: enabled 1 I2C: 00:15: enabled 1 I2C: 00:39: enabled 1 I2C: 00:10: enabled 1 PCI: 00:00.0: enabled 1 PNP: 0c09.0: enabled 1 Compare with tree... Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 10: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.2: enabled 0 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 1 PCI: 00:02.2: enabled 1 PCI: 00:02.3: enabled 1 PCI: 00:02.4: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:02.5: enabled 1 PCI: 00:08.0: enabled 1 PCI: 00:09.0: enabled 1 PCI: 00:09.2: enabled 1 PCI: 00:10.0: enabled 1 PCI: 00:11.0: enabled 0 PCI: 00:12.0: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:14.3: enabled 1 PNP: 0c09.0: enabled 1 PCI: 00:14.7: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 MMIO: fedc2000: enabled 1 GENERIC: 0.0: enabled 1 I2C: 00:1a: enabled 1 GENERIC: 0.1: enabled 1 MMIO: fedc3000: enabled 1 I2C: 00:50: enabled 1 MMIO: fedc4000: enabled 1 I2C: 00:15: enabled 1 MMIO: fedc5000: enabled 1 I2C: 00:39: enabled 1 I2C: 00:10: enabled 1 Mainboard Grunt Enable. Root Device scanning... root_dev_scan_bus for Root Device CPU_CLUSTER: 0 enabled DOMAIN: 0000 enabled MMIO: fedc2000 enabled MMIO: fedc3000 enabled MMIO: fedc4000 enabled MMIO: fedc5000 enabled DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 POST: 0x24 sb_enable PCI: 00:00.0 [1022/1576] enabled sb_enable sb_enable PCI: 00:01.0 [1002/98e4] enabled sb_enable PCI: 00:01.1 [1002/15b3] enabled sb_enable PCI: 00:02.0 [1022/157b] enabled sb_enable PCI: Static device PCI: 00:02.1 not found, disabling it. sb_enable Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xc0 Capability: type 0x08 @ 0xc8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 PCI: 00:02.2 subordinate bus PCI Express PCI: 00:02.2 [1022/157c] enabled sb_enable PCI: Static device PCI: 00:02.3 not found, disabling it. sb_enable Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xc0 Capability: type 0x08 @ 0xc8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 PCI: 00:02.4 subordinate bus PCI Express PCI: 00:02.4 [1022/157c] enabled sb_enable PCI: Static device PCI: 00:02.5 not found, disabling it. PCI: 00:03.0 [1022/157b] enabled sb_enable PCI: 00:08.0 [1022/1578] enabled sb_enable PCI: 00:09.0 [1022/157d] enabled sb_enable PCI: Static device PCI: 00:09.2 not found, disabling it. sb_enable PCI: Static device PCI: 00:10.0 not found, disabling it. sb_enable sb_enable PCI: Static device PCI: 00:12.0 not found, disabling it. sb_enable PCI: 00:14.0 [1022/790b] bus ops PCI: 00:14.0 [1022/790b] enabled sb_enable PCI: 00:14.3 [1022/0000] bus ops PCI: 00:14.3 [1022/790e] enabled sb_enable PCI: Static device PCI: 00:14.7 not found, disabling it. sb_enable PCI: 00:18.0 [1022/15b0] ops PCI: 00:18.0 [1022/15b0] enabled sb_enable PCI: 00:18.1 [1022/15b1] enabled sb_enable PCI: 00:18.2 [1022/15b2] enabled sb_enable PCI: 00:18.3 [1022/15b3] enabled sb_enable PCI: 00:18.4 [1022/15b4] enabled sb_enable PCI: 00:18.5 [1022/15b5] enabled POST: 0x25 PCI: 00:02.2 scanning... do_pci_scan_bridge for PCI: 00:02.2 PCI: pci_scan_bus for bus 01 POST: 0x24 PCI: 01:00.0 [168c/003e] enabled POST: 0x25 POST: 0x55 Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x50 Capability: type 0x10 @ 0x70 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Enabling Common Clock Configuration ASPM: Enabled L0s and L1 Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x50 Capability: type 0x10 @ 0x70 scan_bus: scanning of bus PCI: 00:02.2 took 40766 usecs PCI: 00:02.4 scanning... do_pci_scan_bridge for PCI: 00:02.4 PCI: pci_scan_bus for bus 02 POST: 0x24 PCI: 02:00.0 [1217/0000] ops PCI: 02:00.0 [1217/8620] enabled POST: 0x25 POST: 0x55 Capability: type 0x01 @ 0x6c Capability: type 0x05 @ 0x48 Capability: type 0x10 @ 0x80 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 ASPM: Enabled L0s and L1 Capability: type 0x01 @ 0x6c Capability: type 0x05 @ 0x48 Capability: type 0x10 @ 0x80 scan_bus: scanning of bus PCI: 00:02.4 took 40411 usecs PCI: 00:14.0 scanning... scan_generic_bus for PCI: 00:14.0 scan_generic_bus for PCI: 00:14.0 done scan_bus: scanning of bus PCI: 00:14.0 took 8801 usecs PCI: 00:14.3 scanning... scan_lpc_bus for PCI: 00:14.3 PNP: 0c09.0 enabled scan_lpc_bus for PCI: 00:14.3 done scan_bus: scanning of bus PCI: 00:14.3 took 9951 usecs POST: 0x55 scan_bus: scanning of bus DOMAIN: 0000 took 289513 usecs MMIO: fedc2000 scanning... scan_generic_bus for MMIO: fedc2000 bus: MMIO: fedc2000[0]->GENERIC: 0.0 enabled bus: MMIO: fedc2000[0]->I2C: 01:1a enabled bus: MMIO: fedc2000[0]->GENERIC: 0.1 enabled scan_generic_bus for MMIO: fedc2000 done scan_bus: scanning of bus MMIO: fedc2000 took 21219 usecs MMIO: fedc3000 scanning... scan_generic_bus for MMIO: fedc3000 bus: MMIO: fedc3000[0]->I2C: 02:50 enabled scan_generic_bus for MMIO: fedc3000 done scan_bus: scanning of bus MMIO: fedc3000 took 13184 usecs MMIO: fedc4000 scanning... scan_generic_bus for MMIO: fedc4000 bus: MMIO: fedc4000[0]->I2C: 03:15 enabled scan_generic_bus for MMIO: fedc4000 done scan_bus: scanning of bus MMIO: fedc4000 took 13165 usecs MMIO: fedc5000 scanning... scan_generic_bus for MMIO: fedc5000 bus: MMIO: fedc5000[0]->I2C: 04:39 enabled bus: MMIO: fedc5000[0]->I2C: 04:10 enabled scan_generic_bus for MMIO: fedc5000 done scan_bus: scanning of bus MMIO: fedc5000 took 16986 usecs root_dev_scan_bus for Root Device done scan_bus: scanning of bus Root Device took 400668 usecs done BS: BS_DEV_ENUMERATE times (us): entry 0 run 605693 exit 0 POST: 0x73 found VGA at PCI: 00:01.0 Setting up VGA for PCI: 00:01.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done DOMAIN: 0000 read_resources bus 0 link: 0 PCI: 00:02.2 read_resources bus 1 link: 0 PCI: 00:02.2 read_resources bus 1 link: 0 done PCI: 00:02.4 read_resources bus 2 link: 0 PCI: 00:02.4 read_resources bus 2 link: 0 done PCI: 00:14.3 read_resources bus 0 link: 0 PCI: 00:14.3 read_resources bus 0 link: 0 done Adding PCIe enhanced config space BAR 0xf8000000-0xfc000000. DOMAIN: 0000 read_resources bus 0 link: 0 done MMIO: fedc2000 read_resources bus 1 link: 0 MMIO: fedc2000 read_resources bus 1 link: 0 done MMIO: fedc3000 read_resources bus 2 link: 0 MMIO: fedc3000 read_resources bus 2 link: 0 done MMIO: fedc4000 read_resources bus 3 link: 0 MMIO: fedc4000 read_resources bus 3 link: 0 done MMIO: fedc5000 read_resources bus 4 link: 0 MMIO: fedc5000 read_resources bus 4 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 10 APIC: 10 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI: 00:00.0 PCI: 00:00.2 PCI: 00:01.0 PCI: 00:01.0 resource base 0 size 4000000 align 26 gran 26 limit ffffffffffffffff flags 1201 index 10 PCI: 00:01.0 resource base 0 size 800000 align 23 gran 23 limit ffffffffffffffff flags 1201 index 18 PCI: 00:01.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 20 PCI: 00:01.0 resource base 0 size 40000 align 18 gran 18 limit ffffffff flags 200 index 24 PCI: 00:01.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 2200 index 30 PCI: 00:01.1 PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 PCI: 00:02.0 PCI: 00:02.1 PCI: 00:02.2 child on link 0 PCI: 01:00.0 PCI: 00:02.2 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:02.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:02.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 01:00.0 PCI: 01:00.0 resource base 0 size 200000 align 21 gran 21 limit ffffffffffffffff flags 201 index 10 PCI: 00:02.3 PCI: 00:02.4 child on link 0 PCI: 02:00.0 PCI: 00:02.4 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:02.4 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:02.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 02:00.0 PCI: 02:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 02:00.0 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 14 PCI: 00:02.5 PCI: 00:03.0 PCI: 00:08.0 PCI: 00:08.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 1201 index 10 PCI: 00:08.0 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 200 index 18 PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 1c PCI: 00:08.0 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 200 index 20 PCI: 00:08.0 resource base 0 size 2000 align 13 gran 13 limit ffffffff flags 200 index 24 PCI: 00:09.0 PCI: 00:09.2 PCI: 00:10.0 PCI: 00:11.0 PCI: 00:12.0 PCI: 00:14.0 PCI: 00:14.3 child on link 0 PNP: 0c09.0 PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:14.3 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100 PCI: 00:14.3 resource base fec10000 size 400 align 0 gran 0 limit 0 flags e0040200 index 2 PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PCI: 00:14.3 resource base fedc2000 size 4000 align 0 gran 0 limit 0 flags c0000200 index 4 PNP: 0c09.0 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0 PCI: 00:14.7 PCI: 00:18.0 PCI: 00:18.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI: 00:18.0 resource base fec20000 size 1000 align 0 gran 0 limit 0 flags c0000200 index fec20000 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.4 PCI: 00:18.5 MMIO: fedc2000 child on link 0 GENERIC: 0.0 GENERIC: 0.0 I2C: 01:1a GENERIC: 0.1 MMIO: fedc3000 child on link 0 I2C: 02:50 I2C: 02:50 MMIO: fedc4000 child on link 0 I2C: 03:15 I2C: 03:15 MMIO: fedc5000 child on link 0 I2C: 04:39 I2C: 04:39 I2C: 04:10 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:02.2 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:02.2 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:02.4 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:02.4 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:01.0 20 * [0x0 - 0xff] io DOMAIN: 0000 io: base: 100 size: 100 align: 8 gran: 0 limit: ffff done DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:02.2 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:02.2 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:02.2 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 01:00.0 10 * [0x0 - 0x1fffff] mem PCI: 00:02.2 mem: base: 200000 size: 200000 align: 21 gran: 20 limit: ffffffff done PCI: 00:02.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:02.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:02.4 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 02:00.0 10 * [0x0 - 0xfff] mem PCI: 02:00.0 14 * [0x1000 - 0x17ff] mem PCI: 00:02.4 mem: base: 1800 size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:01.0 10 * [0x0 - 0x3ffffff] prefmem PCI: 00:01.0 18 * [0x4000000 - 0x47fffff] prefmem PCI: 00:02.2 20 * [0x4800000 - 0x49fffff] mem PCI: 00:02.4 20 * [0x4a00000 - 0x4afffff] mem PCI: 00:08.0 18 * [0x4b00000 - 0x4bfffff] mem PCI: 00:08.0 20 * [0x4c00000 - 0x4cfffff] mem PCI: 00:01.0 24 * [0x4d00000 - 0x4d3ffff] mem PCI: 00:01.0 30 * [0x4d40000 - 0x4d5ffff] mem PCI: 00:08.0 10 * [0x4d60000 - 0x4d7ffff] prefmem PCI: 00:01.1 10 * [0x4d80000 - 0x4d83fff] mem PCI: 00:08.0 24 * [0x4d84000 - 0x4d85fff] mem PCI: 00:08.0 1c * [0x4d86000 - 0x4d86fff] mem DOMAIN: 0000 mem: base: 4d87000 size: 4d87000 align: 26 gran: 0 limit: ffffffff done avoid_fixed_resources: DOMAIN: 0000 avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI: 00:14.3 10000000 base 00000000 limit 00000fff io (fixed) constrain_resources: PCI: 00:14.3 10000100 base ff000000 limit ffffffff mem (fixed) constrain_resources: PCI: 00:14.3 02 base fec10000 limit fec103ff mem (fixed) constrain_resources: PCI: 00:14.3 03 base fec00000 limit fec00fff mem (fixed) constrain_resources: PCI: 00:18.0 c0010058 base f8000000 limit fbffffff mem (fixed) avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001000 limit 0000ffff avoid_fixed_resources:@DOMAIN: 0000 10000100 base f0000000 limit f7ffffff Setting resources... DOMAIN: 0000 io: base:1000 size:100 align:8 gran:0 limit:ffff PCI: 00:01.0 20 * [0x1000 - 0x10ff] io DOMAIN: 0000 io: next_base: 1100 size: 100 align: 8 gran: 0 done PCI: 00:02.2 io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:02.2 io: next_base: ffff size: 0 align: 12 gran: 12 done PCI: 00:02.4 io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:02.4 io: next_base: ffff size: 0 align: 12 gran: 12 done DOMAIN: 0000 mem: base:f0000000 size:4d87000 align:26 gran:0 limit:f7ffffff PCI: 00:01.0 10 * [0xf0000000 - 0xf3ffffff] prefmem PCI: 00:01.0 18 * [0xf4000000 - 0xf47fffff] prefmem PCI: 00:02.2 20 * [0xf4800000 - 0xf49fffff] mem PCI: 00:02.4 20 * [0xf4a00000 - 0xf4afffff] mem PCI: 00:08.0 18 * [0xf4b00000 - 0xf4bfffff] mem PCI: 00:08.0 20 * [0xf4c00000 - 0xf4cfffff] mem PCI: 00:01.0 24 * [0xf4d00000 - 0xf4d3ffff] mem PCI: 00:01.0 30 * [0xf4d40000 - 0xf4d5ffff] mem PCI: 00:08.0 10 * [0xf4d60000 - 0xf4d7ffff] prefmem PCI: 00:01.1 10 * [0xf4d80000 - 0xf4d83fff] mem PCI: 00:08.0 24 * [0xf4d84000 - 0xf4d85fff] mem PCI: 00:08.0 1c * [0xf4d86000 - 0xf4d86fff] mem DOMAIN: 0000 mem: next_base: f4d87000 size: 4d87000 align: 26 gran: 0 done PCI: 00:02.2 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff PCI: 00:02.2 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done PCI: 00:02.2 mem: base:f4800000 size:200000 align:21 gran:20 limit:f49fffff PCI: 01:00.0 10 * [0xf4800000 - 0xf49fffff] mem PCI: 00:02.2 mem: next_base: f4a00000 size: 200000 align: 21 gran: 20 done PCI: 00:02.4 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff PCI: 00:02.4 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done PCI: 00:02.4 mem: base:f4a00000 size:100000 align:20 gran:20 limit:f4afffff PCI: 02:00.0 10 * [0xf4a00000 - 0xf4a00fff] mem PCI: 02:00.0 14 * [0xf4a01000 - 0xf4a017ff] mem PCI: 00:02.4 mem: next_base: f4a01800 size: 100000 align: 20 gran: 20 done Root Device assign_resources, bus 0 link: 0 DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:01.0 10 <- [0x00f0000000 - 0x00f3ffffff] size 0x04000000 gran 0x1a prefmem64 PCI: 00:01.0 18 <- [0x00f4000000 - 0x00f47fffff] size 0x00800000 gran 0x17 prefmem64 PCI: 00:01.0 20 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io PCI: 00:01.0 24 <- [0x00f4d00000 - 0x00f4d3ffff] size 0x00040000 gran 0x12 mem PCI: 00:01.0 30 <- [0x00f4d40000 - 0x00f4d5ffff] size 0x00020000 gran 0x11 romem PCI: 00:01.1 10 <- [0x00f4d80000 - 0x00f4d83fff] size 0x00004000 gran 0x0e mem64 PCI: 00:02.2 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io PCI: 00:02.2 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 01 prefmem PCI: 00:02.2 20 <- [0x00f4800000 - 0x00f49fffff] size 0x00200000 gran 0x14 bus 01 mem PCI: 00:02.2 assign_resources, bus 1 link: 0 PCI: 01:00.0 10 <- [0x00f4800000 - 0x00f49fffff] size 0x00200000 gran 0x15 mem64 PCI: 00:02.2 assign_resources, bus 1 link: 0 PCI: 00:02.4 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io PCI: 00:02.4 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 02 prefmem PCI: 00:02.4 20 <- [0x00f4a00000 - 0x00f4afffff] size 0x00100000 gran 0x14 bus 02 mem PCI: 00:02.4 assign_resources, bus 2 link: 0 PCI: 02:00.0 10 <- [0x00f4a00000 - 0x00f4a00fff] size 0x00001000 gran 0x0c mem PCI: 02:00.0 14 <- [0x00f4a01000 - 0x00f4a017ff] size 0x00000800 gran 0x0b mem PCI: 00:02.4 assign_resources, bus 2 link: 0 PCI: 00:08.0 10 <- [0x00f4d60000 - 0x00f4d7ffff] size 0x00020000 gran 0x11 prefmem64 PCI: 00:08.0 18 <- [0x00f4b00000 - 0x00f4bfffff] size 0x00100000 gran 0x14 mem PCI: 00:08.0 1c <- [0x00f4d86000 - 0x00f4d86fff] size 0x00001000 gran 0x0c mem PCI: 00:08.0 20 <- [0x00f4c00000 - 0x00f4cfffff] size 0x00100000 gran 0x14 mem PCI: 00:08.0 24 <- [0x00f4d84000 - 0x00f4d85fff] size 0x00002000 gran 0x0d mem PCI: 00:14.3 assign_resources, bus 0 link: 0 PCI: 00:14.3 assign_resources, bus 0 link: 0 DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 10 APIC: 10 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 1000 size 100 align 8 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base f0000000 size 4d87000 align 26 gran 0 limit f7ffffff flags 40040200 index 10000100 DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10 DOMAIN: 0000 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11 DOMAIN: 0000 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12 DOMAIN: 0000 resource base 100000 size cdf00000 align 0 gran 0 limit 0 flags e0004200 index 13 DOMAIN: 0000 resource base ce000000 size 2000000 align 0 gran 0 limit 0 flags f0004200 index 14 DOMAIN: 0000 resource base 100000000 size 2f000000 align 0 gran 0 limit 0 flags e0004200 index 15 PCI: 00:00.0 PCI: 00:00.2 PCI: 00:01.0 PCI: 00:01.0 resource base f0000000 size 4000000 align 26 gran 26 limit f3ffffff flags 60001201 index 10 PCI: 00:01.0 resource base f4000000 size 800000 align 23 gran 23 limit f47fffff flags 60001201 index 18 PCI: 00:01.0 resource base 1000 size 100 align 8 gran 8 limit 10ff flags 60000100 index 20 PCI: 00:01.0 resource base f4d00000 size 40000 align 18 gran 18 limit f4d3ffff flags 60000200 index 24 PCI: 00:01.0 resource base f4d40000 size 20000 align 17 gran 17 limit f4d5ffff flags 60002200 index 30 PCI: 00:01.1 PCI: 00:01.1 resource base f4d80000 size 4000 align 14 gran 14 limit f4d83fff flags 60000201 index 10 PCI: 00:02.0 PCI: 00:02.1 PCI: 00:02.2 child on link 0 PCI: 01:00.0 PCI: 00:02.2 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:02.2 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24 PCI: 00:02.2 resource base f4800000 size 200000 align 21 gran 20 limit f49fffff flags 60080202 index 20 PCI: 01:00.0 PCI: 01:00.0 resource base f4800000 size 200000 align 21 gran 21 limit f49fffff flags 60000201 index 10 PCI: 00:02.3 PCI: 00:02.4 child on link 0 PCI: 02:00.0 PCI: 00:02.4 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:02.4 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24 PCI: 00:02.4 resource base f4a00000 size 100000 align 20 gran 20 limit f4afffff flags 60080202 index 20 PCI: 02:00.0 PCI: 02:00.0 resource base f4a00000 size 1000 align 12 gran 12 limit f4a00fff flags 60000200 index 10 PCI: 02:00.0 resource base f4a01000 size 800 align 12 gran 11 limit f4a017ff flags 60000200 index 14 PCI: 00:02.5 PCI: 00:03.0 PCI: 00:08.0 PCI: 00:08.0 resource base f4d60000 size 20000 align 17 gran 17 limit f4d7ffff flags 60001201 index 10 PCI: 00:08.0 resource base f4b00000 size 100000 align 20 gran 20 limit f4bfffff flags 60000200 index 18 PCI: 00:08.0 resource base f4d86000 size 1000 align 12 gran 12 limit f4d86fff flags 60000200 index 1c PCI: 00:08.0 resource base f4c00000 size 100000 align 20 gran 20 limit f4cfffff flags 60000200 index 20 PCI: 00:08.0 resource base f4d84000 size 2000 align 13 gran 13 limit f4d85fff flags 60000200 index 24 PCI: 00:09.0 PCI: 00:09.2 PCI: 00:10.0 PCI: 00:11.0 PCI: 00:12.0 PCI: 00:14.0 PCI: 00:14.3 child on link 0 PNP: 0c09.0 PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:14.3 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100 PCI: 00:14.3 resource base fec10000 size 400 align 0 gran 0 limit 0 flags e0040200 index 2 PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PCI: 00:14.3 resource base fedc2000 size 4000 align 0 gran 0 limit 0 flags c0000200 index 4 PNP: 0c09.0 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0 PCI: 00:14.7 PCI: 00:18.0 PCI: 00:18.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI: 00:18.0 resource base fec20000 size 1000 align 0 gran 0 limit 0 flags c0000200 index fec20000 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.4 PCI: 00:18.5 MMIO: fedc2000 child on link 0 GENERIC: 0.0 GENERIC: 0.0 I2C: 01:1a GENERIC: 0.1 MMIO: fedc3000 child on link 0 I2C: 02:50 I2C: 02:50 MMIO: fedc4000 child on link 0 I2C: 03:15 I2C: 03:15 MMIO: fedc5000 child on link 0 I2C: 04:39 I2C: 04:39 I2C: 04:10 Done allocating resources. BS: BS_DEV_RESOURCES times (us): entry 0 run 1463909 exit 0 PCI_INTR tables: Writing registers C00/C01 for PCI IRQ routing: PCI_INTR_INDEX name PIC mode APIC mode 0x00 INTA# 0x03 0x10 0x01 INTB# 0x04 0x11 0x02 INTC# 0x05 0x12 0x03 INTD# 0x07 0x13 0x04 INTE# 0x0B 0x14 0x05 INTF# 0x1F 0x1F 0x06 INTG# 0x1F 0x16 0x07 INTH# 0x1F 0x17 0x08 Misc 0xFA 0x00 0x09 Misc0 0xF1 0x00 0x0A Misc1 0x00 0x00 0x0B Misc2 0x00 0x00 0x0C Ser IRQ INTA 0x1F 0x1F 0x0D Ser IRQ INTB 0x1F 0x1F 0x0E Ser IRQ INTC 0x1F 0x1F 0x0F Ser IRQ INTD 0x1F 0x1F 0x10 SCI 0x09 0x09 0x11 SMBUS 0x1F 0x1F 0x12 ASF 0x1F 0x1F 0x13 HDA 0x03 0x10 0x14 FC 0x1F 0x1F 0x16 PerMon 0x1F 0x1F 0x17 SD 0x03 0x10 0x1A SDIOt 0x00 0x1F 0x30 EHCI 0x05 0x12 0x34 XHCI 0x04 0x12 0x41 SATA 0x07 0x13 0x62 GPIO 0x07 0x07 0x70 I2C0 0x03 0x03 0x71 I2C1 0x0F 0x0F 0x72 I2C2 0x06 0x06 0x73 I2C3 0x0E 0x0E 0x74 UART0 0x0A 0x0A 0x75 UART1 0x0B 0x0B PCI_CFG IRQ: Write PCI config space IRQ assignments PCI IRQ: Found device 0:01.00 using PIN A PCI Devfn (0x8) not found in pirq_data table PCI IRQ: Found device 0:01.01 using PIN B Found this device in pirq_data table entry 5 Orig INT_PIN : 2 (PIN B) PCI_INTR idx : 0x13 (HDA) INT_LINE : 0x3 (IRQ 3) PCI IRQ: Found device 0:02.02 using PIN A Found this device in pirq_data table entry 1 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x01 (INTB#) INT_LINE : 0x4 (IRQ 4) PCI IRQ: Found device 0:02.04 using PIN A Found this device in pirq_data table entry 3 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x03 (INTD#) INT_LINE : 0x7 (IRQ 7) PCI IRQ: Found device 0:08.00 using PIN A PCI Devfn (0x40) not found in pirq_data table PCI IRQ: Found device 2:00.00 using PIN A With INT_PIN swizzled to PIN A Attached to bridge device 0:02h.04h Found this device in pirq_data table entry 3 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x03 (INTD#) INT_LINE : 0x7 (IRQ 7) PCI IRQ: Found device 1:00.00 using PIN A With INT_PIN swizzled to PIN A Attached to bridge device 0:02h.02h Found this device in pirq_data table entry 1 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x01 (INTB#) INT_LINE : 0x4 (IRQ 4) PCI_CFG IRQ: Finished writing PCI config space IRQ assignments POST: 0x74 Enabling resources... PCI: 00:00.0 subsystem <- 1022/1576 PCI: 00:00.0 cmd <- 04 PCI: 00:01.0 subsystem <- 1002/98e4 PCI: 00:01.0 cmd <- 07 PCI: 00:01.1 subsystem <- 1002/15b3 PCI: 00:01.1 cmd <- 02 PCI: 00:02.0 subsystem <- 1022/157b PCI: 00:02.0 cmd <- 00 PCI: 00:02.2 bridge ctrl <- 0003 PCI: 00:02.2 cmd <- 06 PCI: 00:02.4 bridge ctrl <- 0003 PCI: 00:02.4 cmd <- 06 PCI: 00:03.0 cmd <- 00 PCI: 00:08.0 subsystem <- 1022/1578 PCI: 00:08.0 cmd <- 06 PCI: 00:09.0 subsystem <- 1022/157d PCI: 00:09.0 cmd <- 00 PCI: 00:14.0 subsystem <- 1022/790b PCI: 00:14.0 cmd <- 403 PCI: 00:14.3 subsystem <- 1022/790e PCI: 00:14.3 cmd <- 0f Southbridge LPC decode:PNP: 0c09.0, base=0x00000800, end=0x000009fe Covered by wideIO 0 PCI: 00:18.0 cmd <- 00 PCI: 00:18.1 subsystem <- 1022/15b1 PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 subsystem <- 1022/15b2 PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 subsystem <- 1022/15b3 PCI: 00:18.3 cmd <- 00 PCI: 00:18.4 subsystem <- 1022/15b4 PCI: 00:18.4 cmd <- 00 PCI: 00:18.5 subsystem <- 1022/15b5 PCI: 00:18.5 cmd <- 00 PCI: 01:00.0 cmd <- 02 PCI: 02:00.0 subsystem <- 1217/8620 PCI: 02:00.0 cmd <- 06 done. BS: BS_DEV_ENABLE times (us): entry 235048 run 103681 exit 0 POST: 0x75 Initializing devices... Root Device init ... Root Device init finished in 1947 usecs POST: 0x75 CPU_CLUSTER: 0 init ... MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x00000000d0000000 size 0xcff40000 type 6 0x00000000d0000000 - 0x00000000f0000000 size 0x20000000 type 0 0x00000000f0000000 - 0x00000000f4800000 size 0x04800000 type 1 0x00000000f4800000 - 0x0000000100000000 size 0x0b800000 type 0 0x0000000100000000 - 0x000000012f000000 size 0x2f000000 type 6 MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e call enable_fixed_mtrr() CPU physical address size: 48 bits MTRR: default type WB/UC MTRR counts: 8/6. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000ffff80000000 type 6 MTRR: 1 base 0x0000000080000000 mask 0x0000ffffc0000000 type 6 MTRR: 2 base 0x00000000c0000000 mask 0x0000fffff0000000 type 6 MTRR: 3 base 0x00000000f0000000 mask 0x0000fffffc000000 type 1 MTRR: 4 base 0x00000000f4000000 mask 0x0000ffffff800000 type 1 MTRR: 5 base 0x0000000100000000 mask 0x0000ffffc0000000 type 6 MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Will perform SMM setup. CPU: AMD A4-9120C RADEON R4, 5 COMPUTE CORES 2C+3G . Loading module at 00030000 with entry 00030000. filesize: 0x170 memsize: 0x170 Processing 16 relocs. Offset value of 0x00030000 Attempting to start 1 APs Waiting for 10ms after sending INIT. Waiting for 1st SIPI to complete...AP: slot 1 apic_id 11. done. Waiting for 2nd SIPI to complete...done. Loading module at 00038000 with entry 00038000. filesize: 0x1a8 memsize: 0x1a8 Processing 13 relocs. Offset value of 0x00038000 SMM Module: stub loaded at 00038000. Will call cdeb995b(00000000) Installing SMM handler to 0xce800000 Loading module at ce810000 with entry ce81142b. filesize: 0x6c98 memsize: 0xad18 Processing 481 relocs. Offset value of 0xce810000 Loading module at ce808000 with entry ce808000. filesize: 0x1a8 memsize: 0x1a8 Processing 13 relocs. Offset value of 0xce808000 SMM Module: placing jmp sequence at ce807e00 rel16 0x01fd SMM Module: stub loaded at ce808000. Will call ce81142b(00000000) New SMBASE 0xce800000 Relocation complete. New SMBASE 0xce7ffe00 Relocation complete. Initializing CPU #0 CPU: vendor AMD device 670f00 CPU: family 15, model 70, stepping 00 Setting up local APIC... apic_id: 0x10 done. CPU #0 initialized Initializing CPU #1 CPU: vendor AMD device 670f00 CPU: family 15, model 70, stepping 00 Setting up local APIC... apic_id: 0x11 done. CPU #1 initialized bsp_do_flight_plan done after 91 msecs. MTRR: TEMPORARY Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x00000000d0000000 size 0xcff40000 type 6 0x00000000d0000000 - 0x00000000ff000000 size 0x2f000000 type 0 0x00000000ff000000 - 0x0000000100000000 size 0x01000000 type 5 0x0000000100000000 - 0x000000012f000000 size 0x2f000000 type 6 MTRR: default type WB/UC MTRR counts: 7/5. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000ffff80000000 type 6 MTRR: 1 base 0x0000000080000000 mask 0x0000ffffc0000000 type 6 MTRR: 2 base 0x00000000c0000000 mask 0x0000fffff0000000 type 6 MTRR: 3 base 0x00000000ff000000 mask 0x0000ffffff000000 type 5 MTRR: 4 base 0x0000000100000000 mask 0x0000ffffc0000000 type 6 CPU_CLUSTER: 0 init finished in 345967 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 PCI: 00:00.0 init ... PCI: 00:00.0 init finished in 2002 usecs POST: 0x75 POST: 0x75 PCI: 00:01.0 init ... PCI: 00:01.0 init finished in 2002 usecs POST: 0x75 PCI: 00:01.1 init ... PCI: 00:01.1 init finished in 2002 usecs POST: 0x75 PCI: 00:02.0 init ... PCI: 00:02.0 init finished in 2002 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 PCI: 00:03.0 init ... PCI: 00:03.0 init finished in 2002 usecs POST: 0x75 PCI: 00:08.0 init ... PCI: 00:08.0 init finished in 2002 usecs POST: 0x75 PCI: 00:09.0 init ... PCI: 00:09.0 init finished in 2001 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 PCI: 00:14.0 init ... IOAPIC: Initializing IOAPIC at 0xfec00000 IOAPIC: Bootstrap Processor Local APIC = 0x10 IOAPIC: ID = 0x04 IOAPIC: Dumping registers reg 0x0000: 0x04000000 reg 0x0001: 0x00178021 reg 0x0002: 0x04000000 IOAPIC: 24 interrupts IOAPIC: Enabling interrupts on FSB IOAPIC: reg 0x00000000 value 0x10000000 0x00000700 IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 IOAPIC: reg 0x00000017 value 0x00000000 0x00010000 PCI: 00:14.0 init finished in 133961 usecs POST: 0x75 PCI: 00:14.3 init ... PCI: 00:14.3 init finished in 2061 usecs POST: 0x75 POST: 0x75 PCI: 00:18.0 init ... IOAPIC: Initializing IOAPIC at 0xfec20000 IOAPIC: Bootstrap Processor Local APIC = 0x10 IOAPIC: ID = 0x05 IOAPIC: Dumping registers reg 0x0000: 0x05000000 reg 0x0001: 0x001f8021 reg 0x0002: 0x00000000 IOAPIC: 32 interrupts IOAPIC: Enabling interrupts on FSB IOAPIC: reg 0x00000000 value 0x10000000 0x00000700 IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 IOAPIC: reg 0x00000017 value 0x00000000 0x00010000 IOAPIC: reg 0x00000018 value 0x00000000 0x00010000 IOAPIC: reg 0x00000019 value 0x00000000 0x00010000 IOAPIC: reg 0x0000001a value 0x00000000 0x00010000 IOAPIC: reg 0x0000001b value 0x00000000 0x00010000 IOAPIC: reg 0x0000001c value 0x00000000 0x00010000 IOAPIC: reg 0x0000001d value 0x00000000 0x00010000 IOAPIC: reg 0x0000001e value 0x00000000 0x00010000 IOAPIC: reg 0x0000001f value 0x00000000 0x00010000 PCI: 00:18.0 init finished in 170049 usecs POST: 0x75 PCI: 00:18.1 init ... PCI: 00:18.1 init finished in 2002 usecs POST: 0x75 PCI: 00:18.2 init ... PCI: 00:18.2 init finished in 2002 usecs POST: 0x75 PCI: 00:18.3 init ... PCI: 00:18.3 init finished in 2001 usecs POST: 0x75 PCI: 00:18.4 init ... PCI: 00:18.4 init finished in 2002 usecs POST: 0x75 PCI: 00:18.5 init ... PCI: 00:18.5 init finished in 2002 usecs POST: 0x75 PCI: 01:00.0 init ... PCI: 01:00.0 init finished in 2002 usecs POST: 0x75 PCI: 02:00.0 init ... BayHub BH720: Power-saving enabled (link_ctrl=0x110103) PCI: 02:00.0 init finished in 7127 usecs POST: 0x75 PNP: 0c09.0 init ... Google Chrome EC: Hello got back 11223344 status (0) Google Chrome EC: version: ro: careena_v2.0.11488-7215d6e0e4 rw: careena_v2.0.11488-7215d6e0e4 running image: 1 Google Chrome EC uptime: 163.908 seconds Google Chrome AP resets since EC boot: 0 Google Chrome most recent AP reset causes: Google Chrome EC reset flags at last EC boot: reset-pin PNP: 0c09.0 init finished in 34639 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 Devices initialized Show all devs... After init. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 DOMAIN: 0000: enabled 1 MMIO: fedc2000: enabled 1 MMIO: fedc3000: enabled 1 MMIO: fedc4000: enabled 1 MMIO: fedc5000: enabled 1 APIC: 10: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.2: enabled 0 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 0 PCI: 00:02.2: enabled 1 PCI: 00:02.3: enabled 0 PCI: 00:02.4: enabled 1 PCI: 00:02.5: enabled 0 PCI: 00:08.0: enabled 1 PCI: 00:09.0: enabled 1 PCI: 00:09.2: enabled 0 PCI: 00:10.0: enabled 0 PCI: 00:11.0: enabled 0 PCI: 00:12.0: enabled 0 PCI: 00:14.0: enabled 1 PCI: 00:14.3: enabled 1 PCI: 00:14.7: enabled 0 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 GENERIC: 0.0: enabled 1 I2C: 01:1a: enabled 1 GENERIC: 0.1: enabled 1 I2C: 02:50: enabled 1 I2C: 03:15: enabled 1 I2C: 04:39: enabled 1 I2C: 04:10: enabled 1 PCI: 02:00.0: enabled 1 PNP: 0c09.0: enabled 1 PCI: 00:03.0: enabled 1 PCI: 01:00.0: enabled 1 APIC: 11: enabled 1 BS: BS_DEV_INIT times (us): entry 0 run 948025 exit 141 ELOG: Event(A1) added with size 10 at 2023-08-09 04:55:53 UTC elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x2b POST: 0x76 Finalize devices... Devices finalized FMAP: area RW_NVRAM found @ 467000 (20480 bytes) BS: BS_POST_DEVICE times (us): entry 12946 run 4545 exit 4700 FMAP: area RW_MRC_CACHE found @ 0 (65536 bytes) MRC: Checking cached data update for 'RW_MRC_CACHE'. POST: 0x77 Trying to find the wakeup vector... Looking on 000f0000 for valid checksum Checksum 1 passed Checksum 2 passed all OK RSDP found at 000f0000 RSDT found at cde2e030 ends at cde2e07c FADT found at cde31e60 FACS found at cde2e240 OS waking vector is 0009a1d0 BS: BS_OS_RESUME_CHECK times (us): entry 9566 run 24107 exit 0 agesawrapper_amds3finalrestore() entry S3 volatile data @0xceebe000 0x4160 total bytes agesawrapper_amds3finalrestore() returned AGESA_SUCCESS Lock SMM configuration POST: 0xfe Probing TPM I2C: done! DID_VID 0x00281ae0 Locality already claimed cr50 TPM 2.0 (i2c 1:0x50 id 0x28) Platform hierarchy disablement failed: 5001 POST: 0x78 mp_park_aps done after 0 msecs. Restore GNVS pointer to cde6b000 smm_setup_structures STUB!!! POST: 0xfd <6>[ 29.978760] ACPI: EC: interrupt blocked <6>[ 30.002940] ACPI: Preparing to enter system sleep state S3 <6>[ 30.003690] ACPI: EC: event blocked <6>[ 30.003690] ACPI: EC: EC stopped <6>[ 30.003691] PM: Saving platform NVS memory <6>[ 30.003693] Disabling non-boot CPUs ... <6>[ 30.005088] smpboot: CPU 1 is now offline <6>[ 30.005503] ACPI: Low-level resume complete <6>[ 30.005520] ACPI: EC: EC started <6>[ 30.005521] PM: Restoring platform NVS memory <6>[ 30.005538] LVT offset 0 assigned for vector 0x400 <6>[ 30.005782] Enabling non-boot CPUs ... <6>[ 30.005818] x86: Booting SMP configuration: <6>[ 30.005819] smpboot: Booting Node 0 Processor 1 APIC 0x11 <6>[ 30.005971] microcode: CPU1: patch_level=0x06006705 <6>[ 30.008312] ACPI: \_PR_.P001: Found 2 idle states <6>[ 30.008524] CPU1 is up <6>[ 30.008829] ACPI: Waking up from system sleep state S3 <6>[ 30.035991] ACPI: EC: interrupt unblocked <6>[ 30.062130] ACPI: EC: event unblocked <6>[ 30.062831] [drm] PCIE GART of 1024M enabled (table at 0x000000F400000000). <6>[ 30.062846] amdgpu: smu version 33.09.00 <6>[ 30.323130] usb 1-1.1: reset high-speed USB device number 3 using ehci-pci <6>[ 30.369330] r8152 2-4:1.0 eth0: carrier on <6>[ 30.744922] [drm] UVD initialized successfully. <6>[ 30.845557] [drm] VCE initialized successfully. <6>[ 30.971483] OOM killer enabled. <6>[ 30.974881] Restarting tasks ... done. <6>[ 30.983672] PM: suspend exit rtcwake: assuming RTC uses UTC ... rtcwake: wakeup from "mem" using rtc0 at Wed Aug 9 04:56:00 2023 <6>[ 31.011232] PM: suspend entry (deep) <6>[ 31.015099] Filesystems sync: 0.000 seconds <6>[ 31.019685] Freezing user space processes ... (elapsed 0.001 seconds) done. <6>[ 31.028690] OOM killer disabled. <6>[ 31.032176] Freezing remaining freezable tasks ... (elapsed 1.106 seconds) done. <6>[ 32.163368] printk: Suspending console(s) (use no_console_suspend to debug) coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 smm starting... SMI# #0 SMI#: SLP = 0x0c01 Chrome EC: UHEPI supported Chrome EC: Set SMI mask to 0x0000000000000000 Chrome EC: Set SCI mask to 0x0000000000000000 Clearing pending EC events. Error code 1 is expected. EC returned error result code 9 SMI#: Entering S3 (Suspend-To-RAM) FMAP: Found "FLASH" version 1.1 at d7f000. FMAP: base = ff000000 size = 1000000 #areas = 30 FMAP: area RW_ELOG found @ 45d000 (16384 bytes) Manufacturer: ef SF: Detected W25Q128FW with sector size 0x1000, total 0x1000000 ELOG: NV offset 0x45d000 size 0x4000 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024 ELOG: Event(9D) added with size 10 at 2023-08-09 04:55:55 UTC coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 bootblock starting... Family_Model: 00670f00 PMxC0 STATUS: 0x40200800 BIT30 SleepReset BIT11 DW I2C bus 1 at 0xfedc3000 (400 KHz) VBOOT: Loading verstage. CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'fallback/verstage' CBFS: Found @ offset aa8c0 size d5a4 coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 verstage starting... Probing TPM I2C: done! DID_VID 0x00281ae0 TPM ready after 0 ms cr50 TPM 2.0 (i2c 1:0x50 id 0x28) tlcl_send_startup: Startup return code is 84 src/security/tpm/tss/tcg-2.0/tss.c:177 index 0x1007 return code 100 read_space_firmware():99: Antirollback: 0000500a returned by tlcl_read(FIRMWARE_NV_INDEX, ctx->secdata, VB2_SECDATA_SIZE) antirollback_read_space_firmware():474: TPM: Firmware space in a bad state; giving up. Chrome EC: UHEPI supported Phase 1 VB2:vb2_fail() Need recovery, reason: 0x2b / 0x2 FMAP: Found "FLASH" version 1.1 at d7f000. FMAP: base = ff000000 size = 1000000 #areas = 30 FMAP: area GBB found @ d80000 (458752 bytes) VB2:vb2_check_recovery() Recovery reason from previous boot: 0x2b / 0x2 VB2:vb2_check_recovery() We have a recovery request: 0x2b / 0x0 Clearing TPM owner TPM: Clear and re-enable tlcl_force_clear: response is 100 TPM: Can't initiate a force clear. Recovery requested (1009000e) Saving nvdata tlcl_extend: response is 100 CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'fallback/romstage' CBFS: Found @ offset 80 size d2e4 coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 romstage starting... CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'smu_fw' CBFS: Found @ offset 7bc00 size 12262 PSP: Load blob type 19 from @ffe6bc38... OK POST: 0x37 agesawrapper_amdinitreset() entry CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'AGESA_PRE_MEM' CBFS: Found @ offset df80 size 53bcc agesawrapper_amdinitreset() returned AGESA_SUCCESS POST: 0x38 agesawrapper_amdinitearly() entry Warning - AGESA callout: platform_PcieSlotResetControl not supported Warning - AGESA callout: platform_PcieSlotResetControl not supported agesawrapper_amdinitearly() returned AGESA_SUCCESS S3 detected POST: 0x60 agesawrapper_amdinitresume() entry Chrome EC: UHEPI supported FMAP: Found "FLASH" version 1.1 at d7f000. FMAP: base = ff000000 size = 1000000 #areas = 30 FMAP: area RW_MRC_CACHE found @ 0 (65536 bytes) S3 NV data @0xff0048c0, 0xe65 bytes agesawrapper_amdinitresume() returned AGESA_SUCCESS POST: 0x61 POST: 0x42 PSP: Notify that DRAM is available... OK POST: 0x43 creating vboot_handoff structure Chrome EC: clear events_b mask to 0x0000000021004000 POST: 0x44 MTRR Range: Start=cd000000 End=ce000000 (Size 1000000) MTRR Range: Start=ff000000 End=0 (Size 1000000) MTRR Range: Start=ce800000 End=cf000000 (Size 800000) POST: 0x45 coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 postcar starting... Jumping to image. coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 ramstage starting... POST: 0x39 FMAP: Found "FLASH" version 1.1 at d7f000. FMAP: base = ff000000 size = 1000000 #areas = 30 FMAP: area RO_VPD found @ c00000 (16384 bytes) WARNING: RO_VPD is uninitialized or empty. FMAP: area RW_VPD found @ 465000 (8192 bytes) FMAP: area RW_VPD found @ 465000 (8192 bytes) POST: 0x80 S3 Resume. POST: 0x46 agesawrapper_amds3laterestore() entry AGESA: Loading stage from cache S3 volatile data @0xceebe000 0x4160 total bytes agesawrapper_amds3laterestore() returned AGESA_SUCCESS POST: 0x70 BS: BS_PRE_DEVICE times (us): entry 20045 run 1061 exit 0 POST: 0x71 Board ID: 6 mainboard: EC init Chrome EC: Set SMI mask to 0x0000000000000000 Chrome EC: UHEPI supported Chrome EC: Set SCI mask to 0x00000000142609fb Chrome EC: Set WAKE mask to 0x0000000000000000 DW I2C bus 0 at 0xfedc2000 (400 KHz) DW I2C bus 2 at 0xfedc4000 (400 KHz) DW I2C bus 3 at 0xfedc5000 (400 KHz) FMAP: area RW_ELOG found @ 45d000 (16384 bytes) Manufacturer: ef SF: Detected W25Q128FW with sector size 0x1000, total 0x1000000 ELOG: NV offset 0x45d000 size 0x4000 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024 ELOG: Event(9E) added with size 10 at 2023-08-09 04:56:00 UTC ELOG: Event(9F) added with size 14 at 2023-08-09 04:56:00 UTC PM1_STS: WAK RTC BMSTATUS setup_bsp_ramtop, TOP MEM: msr.lo = 0xd0000000, msr.hi = 0x00000000 setup_bsp_ramtop, TOP MEM2: msr.lo = 0x2f000000, msr.hi = 0x00000001 BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 79918 exit 1 POST: 0x72 Enumerating buses... Show all devs... Before device enumeration. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 DOMAIN: 0000: enabled 1 MMIO: fedc2000: enabled 1 MMIO: fedc3000: enabled 1 MMIO: fedc4000: enabled 1 MMIO: fedc5000: enabled 1 APIC: 10: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.2: enabled 0 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 1 PCI: 00:02.2: enabled 1 PCI: 00:02.3: enabled 1 PCI: 00:02.4: enabled 1 PCI: 00:02.5: enabled 1 PCI: 00:08.0: enabled 1 PCI: 00:09.0: enabled 1 PCI: 00:09.2: enabled 1 PCI: 00:10.0: enabled 1 PCI: 00:11.0: enabled 0 PCI: 00:12.0: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:14.3: enabled 1 PCI: 00:14.7: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 GENERIC: 0.0: enabled 1 I2C: 00:1a: enabled 1 GENERIC: 0.1: enabled 1 I2C: 00:50: enabled 1 I2C: 00:15: enabled 1 I2C: 00:39: enabled 1 I2C: 00:10: enabled 1 PCI: 00:00.0: enabled 1 PNP: 0c09.0: enabled 1 Compare with tree... Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 10: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.2: enabled 0 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 1 PCI: 00:02.2: enabled 1 PCI: 00:02.3: enabled 1 PCI: 00:02.4: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:02.5: enabled 1 PCI: 00:08.0: enabled 1 PCI: 00:09.0: enabled 1 PCI: 00:09.2: enabled 1 PCI: 00:10.0: enabled 1 PCI: 00:11.0: enabled 0 PCI: 00:12.0: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:14.3: enabled 1 PNP: 0c09.0: enabled 1 PCI: 00:14.7: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 MMIO: fedc2000: enabled 1 GENERIC: 0.0: enabled 1 I2C: 00:1a: enabled 1 GENERIC: 0.1: enabled 1 MMIO: fedc3000: enabled 1 I2C: 00:50: enabled 1 MMIO: fedc4000: enabled 1 I2C: 00:15: enabled 1 MMIO: fedc5000: enabled 1 I2C: 00:39: enabled 1 I2C: 00:10: enabled 1 Mainboard Grunt Enable. Root Device scanning... root_dev_scan_bus for Root Device CPU_CLUSTER: 0 enabled DOMAIN: 0000 enabled MMIO: fedc2000 enabled MMIO: fedc3000 enabled MMIO: fedc4000 enabled MMIO: fedc5000 enabled DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 POST: 0x24 sb_enable PCI: 00:00.0 [1022/1576] enabled sb_enable sb_enable PCI: 00:01.0 [1002/98e4] enabled sb_enable PCI: 00:01.1 [1002/15b3] enabled sb_enable PCI: 00:02.0 [1022/157b] enabled sb_enable PCI: Static device PCI: 00:02.1 not found, disabling it. sb_enable Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xc0 Capability: type 0x08 @ 0xc8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 PCI: 00:02.2 subordinate bus PCI Express PCI: 00:02.2 [1022/157c] enabled sb_enable PCI: Static device PCI: 00:02.3 not found, disabling it. sb_enable Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xc0 Capability: type 0x08 @ 0xc8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 PCI: 00:02.4 subordinate bus PCI Express PCI: 00:02.4 [1022/157c] enabled sb_enable PCI: Static device PCI: 00:02.5 not found, disabling it. PCI: 00:03.0 [1022/157b] enabled sb_enable PCI: 00:08.0 [1022/1578] enabled sb_enable PCI: 00:09.0 [1022/157d] enabled sb_enable PCI: Static device PCI: 00:09.2 not found, disabling it. sb_enable PCI: Static device PCI: 00:10.0 not found, disabling it. sb_enable sb_enable PCI: Static device PCI: 00:12.0 not found, disabling it. sb_enable PCI: 00:14.0 [1022/790b] bus ops PCI: 00:14.0 [1022/790b] enabled sb_enable PCI: 00:14.3 [1022/0000] bus ops PCI: 00:14.3 [1022/790e] enabled sb_enable PCI: Static device PCI: 00:14.7 not found, disabling it. sb_enable PCI: 00:18.0 [1022/15b0] ops PCI: 00:18.0 [1022/15b0] enabled sb_enable PCI: 00:18.1 [1022/15b1] enabled sb_enable PCI: 00:18.2 [1022/15b2] enabled sb_enable PCI: 00:18.3 [1022/15b3] enabled sb_enable PCI: 00:18.4 [1022/15b4] enabled sb_enable PCI: 00:18.5 [1022/15b5] enabled POST: 0x25 PCI: 00:02.2 scanning... do_pci_scan_bridge for PCI: 00:02.2 PCI: pci_scan_bus for bus 01 POST: 0x24 PCI: 01:00.0 [168c/003e] enabled POST: 0x25 POST: 0x55 Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x50 Capability: type 0x10 @ 0x70 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Enabling Common Clock Configuration ASPM: Enabled L0s and L1 Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x50 Capability: type 0x10 @ 0x70 scan_bus: scanning of bus PCI: 00:02.2 took 40772 usecs PCI: 00:02.4 scanning... do_pci_scan_bridge for PCI: 00:02.4 PCI: pci_scan_bus for bus 02 POST: 0x24 PCI: 02:00.0 [1217/0000] ops PCI: 02:00.0 [1217/8620] enabled POST: 0x25 POST: 0x55 Capability: type 0x01 @ 0x6c Capability: type 0x05 @ 0x48 Capability: type 0x10 @ 0x80 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 ASPM: Enabled L0s and L1 Capability: type 0x01 @ 0x6c Capability: type 0x05 @ 0x48 Capability: type 0x10 @ 0x80 scan_bus: scanning of bus PCI: 00:02.4 took 40406 usecs PCI: 00:14.0 scanning... scan_generic_bus for PCI: 00:14.0 scan_generic_bus for PCI: 00:14.0 done scan_bus: scanning of bus PCI: 00:14.0 took 8806 usecs PCI: 00:14.3 scanning... scan_lpc_bus for PCI: 00:14.3 PNP: 0c09.0 enabled scan_lpc_bus for PCI: 00:14.3 done scan_bus: scanning of bus PCI: 00:14.3 took 9948 usecs POST: 0x55 scan_bus: scanning of bus DOMAIN: 0000 took 289509 usecs MMIO: fedc2000 scanning... scan_generic_bus for MMIO: fedc2000 bus: MMIO: fedc2000[0]->GENERIC: 0.0 enabled bus: MMIO: fedc2000[0]->I2C: 01:1a enabled bus: MMIO: fedc2000[0]->GENERIC: 0.1 enabled scan_generic_bus for MMIO: fedc2000 done scan_bus: scanning of bus MMIO: fedc2000 took 21203 usecs MMIO: fedc3000 scanning... scan_generic_bus for MMIO: fedc3000 bus: MMIO: fedc3000[0]->I2C: 02:50 enabled scan_generic_bus for MMIO: fedc3000 done scan_bus: scanning of bus MMIO: fedc3000 took 13203 usecs MMIO: fedc4000 scanning... scan_generic_bus for MMIO: fedc4000 bus: MMIO: fedc4000[0]->I2C: 03:15 enabled scan_generic_bus for MMIO: fedc4000 done scan_bus: scanning of bus MMIO: fedc4000 took 13154 usecs MMIO: fedc5000 scanning... scan_generic_bus for MMIO: fedc5000 bus: MMIO: fedc5000[0]->I2C: 04:39 enabled bus: MMIO: fedc5000[0]->I2C: 04:10 enabled scan_generic_bus for MMIO: fedc5000 done scan_bus: scanning of bus MMIO: fedc5000 took 16980 usecs root_dev_scan_bus for Root Device done scan_bus: scanning of bus Root Device took 400686 usecs done BS: BS_DEV_ENUMERATE times (us): entry 0 run 605657 exit 0 POST: 0x73 found VGA at PCI: 00:01.0 Setting up VGA for PCI: 00:01.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done DOMAIN: 0000 read_resources bus 0 link: 0 PCI: 00:02.2 read_resources bus 1 link: 0 PCI: 00:02.2 read_resources bus 1 link: 0 done PCI: 00:02.4 read_resources bus 2 link: 0 PCI: 00:02.4 read_resources bus 2 link: 0 done PCI: 00:14.3 read_resources bus 0 link: 0 PCI: 00:14.3 read_resources bus 0 link: 0 done Adding PCIe enhanced config space BAR 0xf8000000-0xfc000000. DOMAIN: 0000 read_resources bus 0 link: 0 done MMIO: fedc2000 read_resources bus 1 link: 0 MMIO: fedc2000 read_resources bus 1 link: 0 done MMIO: fedc3000 read_resources bus 2 link: 0 MMIO: fedc3000 read_resources bus 2 link: 0 done MMIO: fedc4000 read_resources bus 3 link: 0 MMIO: fedc4000 read_resources bus 3 link: 0 done MMIO: fedc5000 read_resources bus 4 link: 0 MMIO: fedc5000 read_resources bus 4 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 10 APIC: 10 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI: 00:00.0 PCI: 00:00.2 PCI: 00:01.0 PCI: 00:01.0 resource base 0 size 4000000 align 26 gran 26 limit ffffffffffffffff flags 1201 index 10 PCI: 00:01.0 resource base 0 size 800000 align 23 gran 23 limit ffffffffffffffff flags 1201 index 18 PCI: 00:01.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 20 PCI: 00:01.0 resource base 0 size 40000 align 18 gran 18 limit ffffffff flags 200 index 24 PCI: 00:01.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 2200 index 30 PCI: 00:01.1 PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 PCI: 00:02.0 PCI: 00:02.1 PCI: 00:02.2 child on link 0 PCI: 01:00.0 PCI: 00:02.2 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:02.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:02.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 01:00.0 PCI: 01:00.0 resource base 0 size 200000 align 21 gran 21 limit ffffffffffffffff flags 201 index 10 PCI: 00:02.3 PCI: 00:02.4 child on link 0 PCI: 02:00.0 PCI: 00:02.4 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:02.4 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:02.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 02:00.0 PCI: 02:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 02:00.0 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 14 PCI: 00:02.5 PCI: 00:03.0 PCI: 00:08.0 PCI: 00:08.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 1201 index 10 PCI: 00:08.0 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 200 index 18 PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 1c PCI: 00:08.0 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 200 index 20 PCI: 00:08.0 resource base 0 size 2000 align 13 gran 13 limit ffffffff flags 200 index 24 PCI: 00:09.0 PCI: 00:09.2 PCI: 00:10.0 PCI: 00:11.0 PCI: 00:12.0 PCI: 00:14.0 PCI: 00:14.3 child on link 0 PNP: 0c09.0 PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:14.3 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100 PCI: 00:14.3 resource base fec10000 size 400 align 0 gran 0 limit 0 flags e0040200 index 2 PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PCI: 00:14.3 resource base fedc2000 size 4000 align 0 gran 0 limit 0 flags c0000200 index 4 PNP: 0c09.0 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0 PCI: 00:14.7 PCI: 00:18.0 PCI: 00:18.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI: 00:18.0 resource base fec20000 size 1000 align 0 gran 0 limit 0 flags c0000200 index fec20000 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.4 PCI: 00:18.5 MMIO: fedc2000 child on link 0 GENERIC: 0.0 GENERIC: 0.0 I2C: 01:1a GENERIC: 0.1 MMIO: fedc3000 child on link 0 I2C: 02:50 I2C: 02:50 MMIO: fedc4000 child on link 0 I2C: 03:15 I2C: 03:15 MMIO: fedc5000 child on link 0 I2C: 04:39 I2C: 04:39 I2C: 04:10 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:02.2 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:02.2 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:02.4 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:02.4 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:01.0 20 * [0x0 - 0xff] io DOMAIN: 0000 io: base: 100 size: 100 align: 8 gran: 0 limit: ffff done DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:02.2 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:02.2 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:02.2 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 01:00.0 10 * [0x0 - 0x1fffff] mem PCI: 00:02.2 mem: base: 200000 size: 200000 align: 21 gran: 20 limit: ffffffff done PCI: 00:02.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:02.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:02.4 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 02:00.0 10 * [0x0 - 0xfff] mem PCI: 02:00.0 14 * [0x1000 - 0x17ff] mem PCI: 00:02.4 mem: base: 1800 size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:01.0 10 * [0x0 - 0x3ffffff] prefmem PCI: 00:01.0 18 * [0x4000000 - 0x47fffff] prefmem PCI: 00:02.2 20 * [0x4800000 - 0x49fffff] mem PCI: 00:02.4 20 * [0x4a00000 - 0x4afffff] mem PCI: 00:08.0 18 * [0x4b00000 - 0x4bfffff] mem PCI: 00:08.0 20 * [0x4c00000 - 0x4cfffff] mem PCI: 00:01.0 24 * [0x4d00000 - 0x4d3ffff] mem PCI: 00:01.0 30 * [0x4d40000 - 0x4d5ffff] mem PCI: 00:08.0 10 * [0x4d60000 - 0x4d7ffff] prefmem PCI: 00:01.1 10 * [0x4d80000 - 0x4d83fff] mem PCI: 00:08.0 24 * [0x4d84000 - 0x4d85fff] mem PCI: 00:08.0 1c * [0x4d86000 - 0x4d86fff] mem DOMAIN: 0000 mem: base: 4d87000 size: 4d87000 align: 26 gran: 0 limit: ffffffff done avoid_fixed_resources: DOMAIN: 0000 avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI: 00:14.3 10000000 base 00000000 limit 00000fff io (fixed) constrain_resources: PCI: 00:14.3 10000100 base ff000000 limit ffffffff mem (fixed) constrain_resources: PCI: 00:14.3 02 base fec10000 limit fec103ff mem (fixed) constrain_resources: PCI: 00:14.3 03 base fec00000 limit fec00fff mem (fixed) constrain_resources: PCI: 00:18.0 c0010058 base f8000000 limit fbffffff mem (fixed) avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001000 limit 0000ffff avoid_fixed_resources:@DOMAIN: 0000 10000100 base f0000000 limit f7ffffff Setting resources... DOMAIN: 0000 io: base:1000 size:100 align:8 gran:0 limit:ffff PCI: 00:01.0 20 * [0x1000 - 0x10ff] io DOMAIN: 0000 io: next_base: 1100 size: 100 align: 8 gran: 0 done PCI: 00:02.2 io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:02.2 io: next_base: ffff size: 0 align: 12 gran: 12 done PCI: 00:02.4 io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:02.4 io: next_base: ffff size: 0 align: 12 gran: 12 done DOMAIN: 0000 mem: base:f0000000 size:4d87000 align:26 gran:0 limit:f7ffffff PCI: 00:01.0 10 * [0xf0000000 - 0xf3ffffff] prefmem PCI: 00:01.0 18 * [0xf4000000 - 0xf47fffff] prefmem PCI: 00:02.2 20 * [0xf4800000 - 0xf49fffff] mem PCI: 00:02.4 20 * [0xf4a00000 - 0xf4afffff] mem PCI: 00:08.0 18 * [0xf4b00000 - 0xf4bfffff] mem PCI: 00:08.0 20 * [0xf4c00000 - 0xf4cfffff] mem PCI: 00:01.0 24 * [0xf4d00000 - 0xf4d3ffff] mem PCI: 00:01.0 30 * [0xf4d40000 - 0xf4d5ffff] mem PCI: 00:08.0 10 * [0xf4d60000 - 0xf4d7ffff] prefmem PCI: 00:01.1 10 * [0xf4d80000 - 0xf4d83fff] mem PCI: 00:08.0 24 * [0xf4d84000 - 0xf4d85fff] mem PCI: 00:08.0 1c * [0xf4d86000 - 0xf4d86fff] mem DOMAIN: 0000 mem: next_base: f4d87000 size: 4d87000 align: 26 gran: 0 done PCI: 00:02.2 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff PCI: 00:02.2 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done PCI: 00:02.2 mem: base:f4800000 size:200000 align:21 gran:20 limit:f49fffff PCI: 01:00.0 10 * [0xf4800000 - 0xf49fffff] mem PCI: 00:02.2 mem: next_base: f4a00000 size: 200000 align: 21 gran: 20 done PCI: 00:02.4 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff PCI: 00:02.4 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done PCI: 00:02.4 mem: base:f4a00000 size:100000 align:20 gran:20 limit:f4afffff PCI: 02:00.0 10 * [0xf4a00000 - 0xf4a00fff] mem PCI: 02:00.0 14 * [0xf4a01000 - 0xf4a017ff] mem PCI: 00:02.4 mem: next_base: f4a01800 size: 100000 align: 20 gran: 20 done Root Device assign_resources, bus 0 link: 0 DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:01.0 10 <- [0x00f0000000 - 0x00f3ffffff] size 0x04000000 gran 0x1a prefmem64 PCI: 00:01.0 18 <- [0x00f4000000 - 0x00f47fffff] size 0x00800000 gran 0x17 prefmem64 PCI: 00:01.0 20 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io PCI: 00:01.0 24 <- [0x00f4d00000 - 0x00f4d3ffff] size 0x00040000 gran 0x12 mem PCI: 00:01.0 30 <- [0x00f4d40000 - 0x00f4d5ffff] size 0x00020000 gran 0x11 romem PCI: 00:01.1 10 <- [0x00f4d80000 - 0x00f4d83fff] size 0x00004000 gran 0x0e mem64 PCI: 00:02.2 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io PCI: 00:02.2 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 01 prefmem PCI: 00:02.2 20 <- [0x00f4800000 - 0x00f49fffff] size 0x00200000 gran 0x14 bus 01 mem PCI: 00:02.2 assign_resources, bus 1 link: 0 PCI: 01:00.0 10 <- [0x00f4800000 - 0x00f49fffff] size 0x00200000 gran 0x15 mem64 PCI: 00:02.2 assign_resources, bus 1 link: 0 PCI: 00:02.4 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io PCI: 00:02.4 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 02 prefmem PCI: 00:02.4 20 <- [0x00f4a00000 - 0x00f4afffff] size 0x00100000 gran 0x14 bus 02 mem PCI: 00:02.4 assign_resources, bus 2 link: 0 PCI: 02:00.0 10 <- [0x00f4a00000 - 0x00f4a00fff] size 0x00001000 gran 0x0c mem PCI: 02:00.0 14 <- [0x00f4a01000 - 0x00f4a017ff] size 0x00000800 gran 0x0b mem PCI: 00:02.4 assign_resources, bus 2 link: 0 PCI: 00:08.0 10 <- [0x00f4d60000 - 0x00f4d7ffff] size 0x00020000 gran 0x11 prefmem64 PCI: 00:08.0 18 <- [0x00f4b00000 - 0x00f4bfffff] size 0x00100000 gran 0x14 mem PCI: 00:08.0 1c <- [0x00f4d86000 - 0x00f4d86fff] size 0x00001000 gran 0x0c mem PCI: 00:08.0 20 <- [0x00f4c00000 - 0x00f4cfffff] size 0x00100000 gran 0x14 mem PCI: 00:08.0 24 <- [0x00f4d84000 - 0x00f4d85fff] size 0x00002000 gran 0x0d mem PCI: 00:14.3 assign_resources, bus 0 link: 0 PCI: 00:14.3 assign_resources, bus 0 link: 0 DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 10 APIC: 10 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 1000 size 100 align 8 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base f0000000 size 4d87000 align 26 gran 0 limit f7ffffff flags 40040200 index 10000100 DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10 DOMAIN: 0000 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11 DOMAIN: 0000 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12 DOMAIN: 0000 resource base 100000 size cdf00000 align 0 gran 0 limit 0 flags e0004200 index 13 DOMAIN: 0000 resource base ce000000 size 2000000 align 0 gran 0 limit 0 flags f0004200 index 14 DOMAIN: 0000 resource base 100000000 size 2f000000 align 0 gran 0 limit 0 flags e0004200 index 15 PCI: 00:00.0 PCI: 00:00.2 PCI: 00:01.0 PCI: 00:01.0 resource base f0000000 size 4000000 align 26 gran 26 limit f3ffffff flags 60001201 index 10 PCI: 00:01.0 resource base f4000000 size 800000 align 23 gran 23 limit f47fffff flags 60001201 index 18 PCI: 00:01.0 resource base 1000 size 100 align 8 gran 8 limit 10ff flags 60000100 index 20 PCI: 00:01.0 resource base f4d00000 size 40000 align 18 gran 18 limit f4d3ffff flags 60000200 index 24 PCI: 00:01.0 resource base f4d40000 size 20000 align 17 gran 17 limit f4d5ffff flags 60002200 index 30 PCI: 00:01.1 PCI: 00:01.1 resource base f4d80000 size 4000 align 14 gran 14 limit f4d83fff flags 60000201 index 10 PCI: 00:02.0 PCI: 00:02.1 PCI: 00:02.2 child on link 0 PCI: 01:00.0 PCI: 00:02.2 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:02.2 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24 PCI: 00:02.2 resource base f4800000 size 200000 align 21 gran 20 limit f49fffff flags 60080202 index 20 PCI: 01:00.0 PCI: 01:00.0 resource base f4800000 size 200000 align 21 gran 21 limit f49fffff flags 60000201 index 10 PCI: 00:02.3 PCI: 00:02.4 child on link 0 PCI: 02:00.0 PCI: 00:02.4 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:02.4 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24 PCI: 00:02.4 resource base f4a00000 size 100000 align 20 gran 20 limit f4afffff flags 60080202 index 20 PCI: 02:00.0 PCI: 02:00.0 resource base f4a00000 size 1000 align 12 gran 12 limit f4a00fff flags 60000200 index 10 PCI: 02:00.0 resource base f4a01000 size 800 align 12 gran 11 limit f4a017ff flags 60000200 index 14 PCI: 00:02.5 PCI: 00:03.0 PCI: 00:08.0 PCI: 00:08.0 resource base f4d60000 size 20000 align 17 gran 17 limit f4d7ffff flags 60001201 index 10 PCI: 00:08.0 resource base f4b00000 size 100000 align 20 gran 20 limit f4bfffff flags 60000200 index 18 PCI: 00:08.0 resource base f4d86000 size 1000 align 12 gran 12 limit f4d86fff flags 60000200 index 1c PCI: 00:08.0 resource base f4c00000 size 100000 align 20 gran 20 limit f4cfffff flags 60000200 index 20 PCI: 00:08.0 resource base f4d84000 size 2000 align 13 gran 13 limit f4d85fff flags 60000200 index 24 PCI: 00:09.0 PCI: 00:09.2 PCI: 00:10.0 PCI: 00:11.0 PCI: 00:12.0 PCI: 00:14.0 PCI: 00:14.3 child on link 0 PNP: 0c09.0 PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:14.3 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100 PCI: 00:14.3 resource base fec10000 size 400 align 0 gran 0 limit 0 flags e0040200 index 2 PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PCI: 00:14.3 resource base fedc2000 size 4000 align 0 gran 0 limit 0 flags c0000200 index 4 PNP: 0c09.0 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0 PCI: 00:14.7 PCI: 00:18.0 PCI: 00:18.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI: 00:18.0 resource base fec20000 size 1000 align 0 gran 0 limit 0 flags c0000200 index fec20000 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.4 PCI: 00:18.5 MMIO: fedc2000 child on link 0 GENERIC: 0.0 GENERIC: 0.0 I2C: 01:1a GENERIC: 0.1 MMIO: fedc3000 child on link 0 I2C: 02:50 I2C: 02:50 MMIO: fedc4000 child on link 0 I2C: 03:15 I2C: 03:15 MMIO: fedc5000 child on link 0 I2C: 04:39 I2C: 04:39 I2C: 04:10 Done allocating resources. BS: BS_DEV_RESOURCES times (us): entry 0 run 1463978 exit 0 PCI_INTR tables: Writing registers C00/C01 for PCI IRQ routing: PCI_INTR_INDEX name PIC mode APIC mode 0x00 INTA# 0x03 0x10 0x01 INTB# 0x04 0x11 0x02 INTC# 0x05 0x12 0x03 INTD# 0x07 0x13 0x04 INTE# 0x0B 0x14 0x05 INTF# 0x1F 0x1F 0x06 INTG# 0x1F 0x16 0x07 INTH# 0x1F 0x17 0x08 Misc 0xFA 0x00 0x09 Misc0 0xF1 0x00 0x0A Misc1 0x00 0x00 0x0B Misc2 0x00 0x00 0x0C Ser IRQ INTA 0x1F 0x1F 0x0D Ser IRQ INTB 0x1F 0x1F 0x0E Ser IRQ INTC 0x1F 0x1F 0x0F Ser IRQ INTD 0x1F 0x1F 0x10 SCI 0x09 0x09 0x11 SMBUS 0x1F 0x1F 0x12 ASF 0x1F 0x1F 0x13 HDA 0x03 0x10 0x14 FC 0x1F 0x1F 0x16 PerMon 0x1F 0x1F 0x17 SD 0x03 0x10 0x1A SDIOt 0x00 0x1F 0x30 EHCI 0x05 0x12 0x34 XHCI 0x04 0x12 0x41 SATA 0x07 0x13 0x62 GPIO 0x07 0x07 0x70 I2C0 0x03 0x03 0x71 I2C1 0x0F 0x0F 0x72 I2C2 0x06 0x06 0x73 I2C3 0x0E 0x0E 0x74 UART0 0x0A 0x0A 0x75 UART1 0x0B 0x0B PCI_CFG IRQ: Write PCI config space IRQ assignments PCI IRQ: Found device 0:01.00 using PIN A PCI Devfn (0x8) not found in pirq_data table PCI IRQ: Found device 0:01.01 using PIN B Found this device in pirq_data table entry 5 Orig INT_PIN : 2 (PIN B) PCI_INTR idx : 0x13 (HDA) INT_LINE : 0x3 (IRQ 3) PCI IRQ: Found device 0:02.02 using PIN A Found this device in pirq_data table entry 1 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x01 (INTB#) INT_LINE : 0x4 (IRQ 4) PCI IRQ: Found device 0:02.04 using PIN A Found this device in pirq_data table entry 3 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x03 (INTD#) INT_LINE : 0x7 (IRQ 7) PCI IRQ: Found device 0:08.00 using PIN A PCI Devfn (0x40) not found in pirq_data table PCI IRQ: Found device 2:00.00 using PIN A With INT_PIN swizzled to PIN A Attached to bridge device 0:02h.04h Found this device in pirq_data table entry 3 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x03 (INTD#) INT_LINE : 0x7 (IRQ 7) PCI IRQ: Found device 1:00.00 using PIN A With INT_PIN swizzled to PIN A Attached to bridge device 0:02h.02h Found this device in pirq_data table entry 1 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x01 (INTB#) INT_LINE : 0x4 (IRQ 4) PCI_CFG IRQ: Finished writing PCI config space IRQ assignments POST: 0x74 Enabling resources... PCI: 00:00.0 subsystem <- 1022/1576 PCI: 00:00.0 cmd <- 04 PCI: 00:01.0 subsystem <- 1002/98e4 PCI: 00:01.0 cmd <- 07 PCI: 00:01.1 subsystem <- 1002/15b3 PCI: 00:01.1 cmd <- 02 PCI: 00:02.0 subsystem <- 1022/157b PCI: 00:02.0 cmd <- 00 PCI: 00:02.2 bridge ctrl <- 0003 PCI: 00:02.2 cmd <- 06 PCI: 00:02.4 bridge ctrl <- 0003 PCI: 00:02.4 cmd <- 06 PCI: 00:03.0 cmd <- 00 PCI: 00:08.0 subsystem <- 1022/1578 PCI: 00:08.0 cmd <- 06 PCI: 00:09.0 subsystem <- 1022/157d PCI: 00:09.0 cmd <- 00 PCI: 00:14.0 subsystem <- 1022/790b PCI: 00:14.0 cmd <- 403 PCI: 00:14.3 subsystem <- 1022/790e PCI: 00:14.3 cmd <- 0f Southbridge LPC decode:PNP: 0c09.0, base=0x00000800, end=0x000009fe Covered by wideIO 0 PCI: 00:18.0 cmd <- 00 PCI: 00:18.1 subsystem <- 1022/15b1 PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 subsystem <- 1022/15b2 PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 subsystem <- 1022/15b3 PCI: 00:18.3 cmd <- 00 PCI: 00:18.4 subsystem <- 1022/15b4 PCI: 00:18.4 cmd <- 00 PCI: 00:18.5 subsystem <- 1022/15b5 PCI: 00:18.5 cmd <- 00 PCI: 01:00.0 cmd <- 02 PCI: 02:00.0 subsystem <- 1217/8620 PCI: 02:00.0 cmd <- 06 done. BS: BS_DEV_ENABLE times (us): entry 235051 run 103694 exit 0 POST: 0x75 Initializing devices... Root Device init ... Root Device init finished in 1947 usecs POST: 0x75 CPU_CLUSTER: 0 init ... MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x00000000d0000000 size 0xcff40000 type 6 0x00000000d0000000 - 0x00000000f0000000 size 0x20000000 type 0 0x00000000f0000000 - 0x00000000f4800000 size 0x04800000 type 1 0x00000000f4800000 - 0x0000000100000000 size 0x0b800000 type 0 0x0000000100000000 - 0x000000012f000000 size 0x2f000000 type 6 MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e call enable_fixed_mtrr() CPU physical address size: 48 bits MTRR: default type WB/UC MTRR counts: 8/6. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000ffff80000000 type 6 MTRR: 1 base 0x0000000080000000 mask 0x0000ffffc0000000 type 6 MTRR: 2 base 0x00000000c0000000 mask 0x0000fffff0000000 type 6 MTRR: 3 base 0x00000000f0000000 mask 0x0000fffffc000000 type 1 MTRR: 4 base 0x00000000f4000000 mask 0x0000ffffff800000 type 1 MTRR: 5 base 0x0000000100000000 mask 0x0000ffffc0000000 type 6 MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Will perform SMM setup. CPU: AMD A4-9120C RADEON R4, 5 COMPUTE CORES 2C+3G . Loading module at 00030000 with entry 00030000. filesize: 0x170 memsize: 0x170 Processing 16 relocs. Offset value of 0x00030000 Attempting to start 1 APs Waiting for 10ms after sending INIT. Waiting for 1st SIPI to complete...AP: slot 1 apic_id 11. done. Waiting for 2nd SIPI to complete...done. Loading module at 00038000 with entry 00038000. filesize: 0x1a8 memsize: 0x1a8 Processing 13 relocs. Offset value of 0x00038000 SMM Module: stub loaded at 00038000. Will call cdeb995b(00000000) Installing SMM handler to 0xce800000 Loading module at ce810000 with entry ce81142b. filesize: 0x6c98 memsize: 0xad18 Processing 481 relocs. Offset value of 0xce810000 Loading module at ce808000 with entry ce808000. filesize: 0x1a8 memsize: 0x1a8 Processing 13 relocs. Offset value of 0xce808000 SMM Module: placing jmp sequence at ce807e00 rel16 0x01fd SMM Module: stub loaded at ce808000. Will call ce81142b(00000000) New SMBASE 0xce800000 Relocation complete. New SMBASE 0xce7ffe00 Relocation complete. Initializing CPU #0 CPU: vendor AMD device 670f00 CPU: family 15, model 70, stepping 00 Setting up local APIC... apic_id: 0x10 done. CPU #0 initialized Initializing CPU #1 CPU: vendor AMD device 670f00 CPU: family 15, model 70, stepping 00 Setting up local APIC... apic_id: 0x11 done. CPU #1 initialized bsp_do_flight_plan done after 91 msecs. MTRR: TEMPORARY Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x00000000d0000000 size 0xcff40000 type 6 0x00000000d0000000 - 0x00000000ff000000 size 0x2f000000 type 0 0x00000000ff000000 - 0x0000000100000000 size 0x01000000 type 5 0x0000000100000000 - 0x000000012f000000 size 0x2f000000 type 6 MTRR: default type WB/UC MTRR counts: 7/5. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000ffff80000000 type 6 MTRR: 1 base 0x0000000080000000 mask 0x0000ffffc0000000 type 6 MTRR: 2 base 0x00000000c0000000 mask 0x0000fffff0000000 type 6 MTRR: 3 base 0x00000000ff000000 mask 0x0000ffffff000000 type 5 MTRR: 4 base 0x0000000100000000 mask 0x0000ffffc0000000 type 6 CPU_CLUSTER: 0 init finished in 345967 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 PCI: 00:00.0 init ... PCI: 00:00.0 init finished in 2002 usecs POST: 0x75 POST: 0x75 PCI: 00:01.0 init ... PCI: 00:01.0 init finished in 2001 usecs POST: 0x75 PCI: 00:01.1 init ... PCI: 00:01.1 init finished in 2002 usecs POST: 0x75 PCI: 00:02.0 init ... PCI: 00:02.0 init finished in 2001 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 PCI: 00:03.0 init ... PCI: 00:03.0 init finished in 2002 usecs POST: 0x75 PCI: 00:08.0 init ... PCI: 00:08.0 init finished in 2002 usecs POST: 0x75 PCI: 00:09.0 init ... PCI: 00:09.0 init finished in 2001 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 PCI: 00:14.0 init ... IOAPIC: Initializing IOAPIC at 0xfec00000 IOAPIC: Bootstrap Processor Local APIC = 0x10 IOAPIC: ID = 0x04 IOAPIC: Dumping registers reg 0x0000: 0x04000000 reg 0x0001: 0x00178021 reg 0x0002: 0x04000000 IOAPIC: 24 interrupts IOAPIC: Enabling interrupts on FSB IOAPIC: reg 0x00000000 value 0x10000000 0x00000700 IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 IOAPIC: reg 0x00000017 value 0x00000000 0x00010000 PCI: 00:14.0 init finished in 133972 usecs POST: 0x75 PCI: 00:14.3 init ... PCI: 00:14.3 init finished in 2060 usecs POST: 0x75 POST: 0x75 PCI: 00:18.0 init ... IOAPIC: Initializing IOAPIC at 0xfec20000 IOAPIC: Bootstrap Processor Local APIC = 0x10 IOAPIC: ID = 0x05 IOAPIC: Dumping registers reg 0x0000: 0x05000000 reg 0x0001: 0x001f8021 reg 0x0002: 0x00000000 IOAPIC: 32 interrupts IOAPIC: Enabling interrupts on FSB IOAPIC: reg 0x00000000 value 0x10000000 0x00000700 IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 IOAPIC: reg 0x00000017 value 0x00000000 0x00010000 IOAPIC: reg 0x00000018 value 0x00000000 0x00010000 IOAPIC: reg 0x00000019 value 0x00000000 0x00010000 IOAPIC: reg 0x0000001a value 0x00000000 0x00010000 IOAPIC: reg 0x0000001b value 0x00000000 0x00010000 IOAPIC: reg 0x0000001c value 0x00000000 0x00010000 IOAPIC: reg 0x0000001d value 0x00000000 0x00010000 IOAPIC: reg 0x0000001e value 0x00000000 0x00010000 IOAPIC: reg 0x0000001f value 0x00000000 0x00010000 PCI: 00:18.0 init finished in 170034 usecs POST: 0x75 PCI: 00:18.1 init ... PCI: 00:18.1 init finished in 2001 usecs POST: 0x75 PCI: 00:18.2 init ... PCI: 00:18.2 init finished in 2002 usecs POST: 0x75 PCI: 00:18.3 init ... PCI: 00:18.3 init finished in 2001 usecs POST: 0x75 PCI: 00:18.4 init ... PCI: 00:18.4 init finished in 2002 usecs POST: 0x75 PCI: 00:18.5 init ... PCI: 00:18.5 init finished in 2001 usecs POST: 0x75 PCI: 01:00.0 init ... PCI: 01:00.0 init finished in 2002 usecs POST: 0x75 PCI: 02:00.0 init ... BayHub BH720: Power-saving enabled (link_ctrl=0x110103) PCI: 02:00.0 init finished in 7127 usecs POST: 0x75 PNP: 0c09.0 init ... Google Chrome EC: Hello got back 11223344 status (0) Google Chrome EC: version: ro: careena_v2.0.11488-7215d6e0e4 rw: careena_v2.0.11488-7215d6e0e4 running image: 1 Google Chrome EC uptime: 174.880 seconds Google Chrome AP resets since EC boot: 0 Google Chrome most recent AP reset causes: Google Chrome EC reset flags at last EC boot: reset-pin PNP: 0c09.0 init finished in 34636 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 Devices initialized Show all devs... After init. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 DOMAIN: 0000: enabled 1 MMIO: fedc2000: enabled 1 MMIO: fedc3000: enabled 1 MMIO: fedc4000: enabled 1 MMIO: fedc5000: enabled 1 APIC: 10: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.2: enabled 0 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 0 PCI: 00:02.2: enabled 1 PCI: 00:02.3: enabled 0 PCI: 00:02.4: enabled 1 PCI: 00:02.5: enabled 0 PCI: 00:08.0: enabled 1 PCI: 00:09.0: enabled 1 PCI: 00:09.2: enabled 0 PCI: 00:10.0: enabled 0 PCI: 00:11.0: enabled 0 PCI: 00:12.0: enabled 0 PCI: 00:14.0: enabled 1 PCI: 00:14.3: enabled 1 PCI: 00:14.7: enabled 0 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 GENERIC: 0.0: enabled 1 I2C: 01:1a: enabled 1 GENERIC: 0.1: enabled 1 I2C: 02:50: enabled 1 I2C: 03:15: enabled 1 I2C: 04:39: enabled 1 I2C: 04:10: enabled 1 PCI: 02:00.0: enabled 1 PNP: 0c09.0: enabled 1 PCI: 00:03.0: enabled 1 PCI: 01:00.0: enabled 1 APIC: 11: enabled 1 BS: BS_DEV_INIT times (us): entry 0 run 948021 exit 141 ELOG: Event(A1) added with size 10 at 2023-08-09 04:56:04 UTC elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x2b POST: 0x76 Finalize devices... Devices finalized FMAP: area RW_NVRAM found @ 467000 (20480 bytes) BS: BS_POST_DEVICE times (us): entry 12936 run 4545 exit 4697 FMAP: area RW_MRC_CACHE found @ 0 (65536 bytes) MRC: Checking cached data update for 'RW_MRC_CACHE'. POST: 0x77 Trying to find the wakeup vector... Looking on 000f0000 for valid checksum Checksum 1 passed Checksum 2 passed all OK RSDP found at 000f0000 RSDT found at cde2e030 ends at cde2e07c FADT found at cde31e60 FACS found at cde2e240 OS waking vector is 0009a1d0 BS: BS_OS_RESUME_CHECK times (us): entry 9571 run 24102 exit 0 agesawrapper_amds3finalrestore() entry S3 volatile data @0xceebe000 0x4160 total bytes agesawrapper_amds3finalrestore() returned AGESA_SUCCESS Lock SMM configuration POST: 0xfe Probing TPM I2C: done! DID_VID 0x00281ae0 Locality already claimed cr50 TPM 2.0 (i2c 1:0x50 id 0x28) Platform hierarchy disablement failed: 5001 POST: 0x78 mp_park_aps done after 0 msecs. Restore GNVS pointer to cde6b000 smm_setup_structures STUB!!! POST: 0xfd <6>[ 32.243551] ACPI: EC: interrupt blocked <6>[ 32.268061] ACPI: Preparing to enter system sleep state S3 <6>[ 32.268856] ACPI: EC: event blocked <6>[ 32.268856] ACPI: EC: EC stopped <6>[ 32.268857] PM: Saving platform NVS memory <6>[ 32.268874] Disabling non-boot CPUs ... <6>[ 32.270278] smpboot: CPU 1 is now offline <6>[ 32.270716] ACPI: Low-level resume complete <6>[ 32.270733] ACPI: EC: EC started <6>[ 32.270734] PM: Restoring platform NVS memory <6>[ 32.270750] LVT offset 0 assigned for vector 0x400 <6>[ 32.271012] Enabling non-boot CPUs ... <6>[ 32.271047] x86: Booting SMP configuration: <6>[ 32.271048] smpboot: Booting Node 0 Processor 1 APIC 0x11 <6>[ 32.271203] microcode: CPU1: patch_level=0x06006705 <6>[ 32.273534] ACPI: \_PR_.P001: Found 2 idle states <6>[ 32.273755] CPU1 is up <6>[ 32.274019] ACPI: Waking up from system sleep state S3 <6>[ 32.301183] ACPI: EC: interrupt unblocked <6>[ 32.328162] [drm] PCIE GART of 1024M enabled (table at 0x000000F400000000). <6>[ 32.328178] amdgpu: smu version 33.09.00 <6>[ 32.328343] ACPI: EC: event unblocked <6>[ 32.596836] usb 1-1.1: reset high-speed USB device number 3 using ehci-pci <6>[ 32.617314] r8152 2-4:1.0 eth0: carrier on <6>[ 33.009571] [drm] UVD initialized successfully. <6>[ 33.110597] [drm] VCE initialized successfully. <6>[ 33.235076] OOM killer enabled. <6>[ 33.238473] Restarting tasks ... done. <6>[ 33.248327] PM: suspend exit rtcwake: assuming RTC uses UTC ... rtcwake: wakeup from "mem" using rtc0 at Wed Aug 9 04:56:11 2023 <6>[ 33.275266] PM: suspend entry (deep) <6>[ 33.279131] Filesystems sync: 0.000 seconds <6>[ 33.283738] Freezing user space processes ... (elapsed 0.001 seconds) done. <6>[ 33.292299] OOM killer disabled. <6>[ 33.295783] Freezing remaining freezable tasks ... (elapsed 1.107 seconds) done. <6>[ 34.426724] printk: Suspending console(s) (use no_console_suspend to debug) coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 smm starting... SMI# #0 SMI#: SLP = 0x0c01 Chrome EC: UHEPI supported Chrome EC: Set SMI mask to 0x0000000000000000 Chrome EC: Set SCI mask to 0x0000000000000000 Clearing pending EC events. Error code 1 is expected. EC returned error result code 9 SMI#: Entering S3 (Suspend-To-RAM) FMAP: Found "FLASH" version 1.1 at d7f000. FMAP: base = ff000000 size = 1000000 #areas = 30 FMAP: area RW_ELOG found @ 45d000 (16384 bytes) Manufacturer: ef SF: Detected W25Q128FW with sector size 0x1000, total 0x1000000 ELOG: NV offset 0x45d000 size 0x4000 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024 ELOG: Event(9D) added with size 10 at 2023-08-09 04:56:06 UTC coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 bootblock starting... Family_Model: 00670f00 PMxC0 STATUS: 0x40200800 BIT30 SleepReset BIT11 DW I2C bus 1 at 0xfedc3000 (400 KHz) VBOOT: Loading verstage. CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'fallback/verstage' CBFS: Found @ offset aa8c0 size d5a4 coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 verstage starting... Probing TPM I2C: done! DID_VID 0x00281ae0 TPM ready after 0 ms cr50 TPM 2.0 (i2c 1:0x50 id 0x28) tlcl_send_startup: Startup return code is 84 src/security/tpm/tss/tcg-2.0/tss.c:177 index 0x1007 return code 100 read_space_firmware():99: Antirollback: 0000500a returned by tlcl_read(FIRMWARE_NV_INDEX, ctx->secdata, VB2_SECDATA_SIZE) antirollback_read_space_firmware():474: TPM: Firmware space in a bad state; giving up. Chrome EC: UHEPI supported Phase 1 VB2:vb2_fail() Need recovery, reason: 0x2b / 0x2 FMAP: Found "FLASH" version 1.1 at d7f000. FMAP: base = ff000000 size = 1000000 #areas = 30 FMAP: area GBB found @ d80000 (458752 bytes) VB2:vb2_check_recovery() Recovery reason from previous boot: 0x2b / 0x2 VB2:vb2_check_recovery() We have a recovery request: 0x2b / 0x0 Clearing TPM owner TPM: Clear and re-enable tlcl_force_clear: response is 100 TPM: Can't initiate a force clear. Recovery requested (1009000e) Saving nvdata tlcl_extend: response is 100 CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'fallback/romstage' CBFS: Found @ offset 80 size d2e4 coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 romstage starting... CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'smu_fw' CBFS: Found @ offset 7bc00 size 12262 PSP: Load blob type 19 from @ffe6bc38... OK POST: 0x37 agesawrapper_amdinitreset() entry CBFS: 'Master Header Locator' located CBFS at [df0000:ffffc0) CBFS: Locating 'AGESA_PRE_MEM' CBFS: Found @ offset df80 size 53bcc agesawrapper_amdinitreset() returned AGESA_SUCCESS POST: 0x38 agesawrapper_amdinitearly() entry Warning - AGESA callout: platform_PcieSlotResetControl not supported Warning - AGESA callout: platform_PcieSlotResetControl not supported agesawrapper_amdinitearly() returned AGESA_SUCCESS S3 detected POST: 0x60 agesawrapper_amdinitresume() entry Chrome EC: UHEPI supported FMAP: Found "FLASH" version 1.1 at d7f000. FMAP: base = ff000000 size = 1000000 #areas = 30 FMAP: area RW_MRC_CACHE found @ 0 (65536 bytes) S3 NV data @0xff0048c0, 0xe65 bytes agesawrapper_amdinitresume() returned AGESA_SUCCESS POST: 0x61 POST: 0x42 PSP: Notify that DRAM is available... OK POST: 0x43 creating vboot_handoff structure Chrome EC: clear events_b mask to 0x0000000021004000 POST: 0x44 MTRR Range: Start=cd000000 End=ce000000 (Size 1000000) MTRR Range: Start=ff000000 End=0 (Size 1000000) MTRR Range: Start=ce800000 End=cf000000 (Size 800000) POST: 0x45 coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 postcar starting... Jumping to image. coreboot-56f9d1cd49 Thu Sep 5 21:57:06 UTC 2019 ramstage starting... POST: 0x39 FMAP: Found "FLASH" version 1.1 at d7f000. FMAP: base = ff000000 size = 1000000 #areas = 30 FMAP: area RO_VPD found @ c00000 (16384 bytes) WARNING: RO_VPD is uninitialized or empty. FMAP: area RW_VPD found @ 465000 (8192 bytes) FMAP: area RW_VPD found @ 465000 (8192 bytes) POST: 0x80 S3 Resume. POST: 0x46 agesawrapper_amds3laterestore() entry AGESA: Loading stage from cache S3 volatile data @0xceebe000 0x4160 total bytes agesawrapper_amds3laterestore() returned AGESA_SUCCESS POST: 0x70 BS: BS_PRE_DEVICE times (us): entry 20024 run 1058 exit 0 POST: 0x71 Board ID: 6 mainboard: EC init Chrome EC: Set SMI mask to 0x0000000000000000 Chrome EC: UHEPI supported Chrome EC: Set SCI mask to 0x00000000142609fb Chrome EC: Set WAKE mask to 0x0000000000000000 DW I2C bus 0 at 0xfedc2000 (400 KHz) DW I2C bus 2 at 0xfedc4000 (400 KHz) DW I2C bus 3 at 0xfedc5000 (400 KHz) FMAP: area RW_ELOG found @ 45d000 (16384 bytes) Manufacturer: ef SF: Detected W25Q128FW with sector size 0x1000, total 0x1000000 ELOG: NV offset 0x45d000 size 0x4000 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024 ELOG: Event(9E) added with size 10 at 2023-08-09 04:56:11 UTC ELOG: Event(9F) added with size 14 at 2023-08-09 04:56:11 UTC PM1_STS: WAK RTC BMSTATUS setup_bsp_ramtop, TOP MEM: msr.lo = 0xd0000000, msr.hi = 0x00000000 setup_bsp_ramtop, TOP MEM2: msr.lo = 0x2f000000, msr.hi = 0x00000001 BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 79914 exit 0 POST: 0x72 Enumerating buses... Show all devs... Before device enumeration. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 DOMAIN: 0000: enabled 1 MMIO: fedc2000: enabled 1 MMIO: fedc3000: enabled 1 MMIO: fedc4000: enabled 1 MMIO: fedc5000: enabled 1 APIC: 10: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.2: enabled 0 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 1 PCI: 00:02.2: enabled 1 PCI: 00:02.3: enabled 1 PCI: 00:02.4: enabled 1 PCI: 00:02.5: enabled 1 PCI: 00:08.0: enabled 1 PCI: 00:09.0: enabled 1 PCI: 00:09.2: enabled 1 PCI: 00:10.0: enabled 1 PCI: 00:11.0: enabled 0 PCI: 00:12.0: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:14.3: enabled 1 PCI: 00:14.7: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 GENERIC: 0.0: enabled 1 I2C: 00:1a: enabled 1 GENERIC: 0.1: enabled 1 I2C: 00:50: enabled 1 I2C: 00:15: enabled 1 I2C: 00:39: enabled 1 I2C: 00:10: enabled 1 PCI: 00:00.0: enabled 1 PNP: 0c09.0: enabled 1 Compare with tree... Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 APIC: 10: enabled 1 DOMAIN: 0000: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.2: enabled 0 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 1 PCI: 00:02.2: enabled 1 PCI: 00:02.3: enabled 1 PCI: 00:02.4: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:02.5: enabled 1 PCI: 00:08.0: enabled 1 PCI: 00:09.0: enabled 1 PCI: 00:09.2: enabled 1 PCI: 00:10.0: enabled 1 PCI: 00:11.0: enabled 0 PCI: 00:12.0: enabled 1 PCI: 00:14.0: enabled 1 PCI: 00:14.3: enabled 1 PNP: 0c09.0: enabled 1 PCI: 00:14.7: enabled 1 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 MMIO: fedc2000: enabled 1 GENERIC: 0.0: enabled 1 I2C: 00:1a: enabled 1 GENERIC: 0.1: enabled 1 MMIO: fedc3000: enabled 1 I2C: 00:50: enabled 1 MMIO: fedc4000: enabled 1 I2C: 00:15: enabled 1 MMIO: fedc5000: enabled 1 I2C: 00:39: enabled 1 I2C: 00:10: enabled 1 Mainboard Grunt Enable. Root Device scanning... root_dev_scan_bus for Root Device CPU_CLUSTER: 0 enabled DOMAIN: 0000 enabled MMIO: fedc2000 enabled MMIO: fedc3000 enabled MMIO: fedc4000 enabled MMIO: fedc5000 enabled DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 POST: 0x24 sb_enable PCI: 00:00.0 [1022/1576] enabled sb_enable sb_enable PCI: 00:01.0 [1002/98e4] enabled sb_enable PCI: 00:01.1 [1002/15b3] enabled sb_enable PCI: 00:02.0 [1022/157b] enabled sb_enable PCI: Static device PCI: 00:02.1 not found, disabling it. sb_enable Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xc0 Capability: type 0x08 @ 0xc8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 PCI: 00:02.2 subordinate bus PCI Express PCI: 00:02.2 [1022/157c] enabled sb_enable PCI: Static device PCI: 00:02.3 not found, disabling it. sb_enable Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Capability: type 0x05 @ 0xa0 Capability: type 0x0d @ 0xc0 Capability: type 0x08 @ 0xc8 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 PCI: 00:02.4 subordinate bus PCI Express PCI: 00:02.4 [1022/157c] enabled sb_enable PCI: Static device PCI: 00:02.5 not found, disabling it. PCI: 00:03.0 [1022/157b] enabled sb_enable PCI: 00:08.0 [1022/1578] enabled sb_enable PCI: 00:09.0 [1022/157d] enabled sb_enable PCI: Static device PCI: 00:09.2 not found, disabling it. sb_enable PCI: Static device PCI: 00:10.0 not found, disabling it. sb_enable sb_enable PCI: Static device PCI: 00:12.0 not found, disabling it. sb_enable PCI: 00:14.0 [1022/790b] bus ops PCI: 00:14.0 [1022/790b] enabled sb_enable PCI: 00:14.3 [1022/0000] bus ops PCI: 00:14.3 [1022/790e] enabled sb_enable PCI: Static device PCI: 00:14.7 not found, disabling it. sb_enable PCI: 00:18.0 [1022/15b0] ops PCI: 00:18.0 [1022/15b0] enabled sb_enable PCI: 00:18.1 [1022/15b1] enabled sb_enable PCI: 00:18.2 [1022/15b2] enabled sb_enable PCI: 00:18.3 [1022/15b3] enabled sb_enable PCI: 00:18.4 [1022/15b4] enabled sb_enable PCI: 00:18.5 [1022/15b5] enabled POST: 0x25 PCI: 00:02.2 scanning... do_pci_scan_bridge for PCI: 00:02.2 PCI: pci_scan_bus for bus 01 POST: 0x24 PCI: 01:00.0 [168c/003e] enabled POST: 0x25 POST: 0x55 Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x50 Capability: type 0x10 @ 0x70 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 Enabling Common Clock Configuration ASPM: Enabled L0s and L1 Capability: type 0x01 @ 0x40 Capability: type 0x05 @ 0x50 Capability: type 0x10 @ 0x70 scan_bus: scanning of bus PCI: 00:02.2 took 40766 usecs PCI: 00:02.4 scanning... do_pci_scan_bridge for PCI: 00:02.4 PCI: pci_scan_bus for bus 02 POST: 0x24 PCI: 02:00.0 [1217/0000] ops PCI: 02:00.0 [1217/8620] enabled POST: 0x25 POST: 0x55 Capability: type 0x01 @ 0x6c Capability: type 0x05 @ 0x48 Capability: type 0x10 @ 0x80 Capability: type 0x01 @ 0x50 Capability: type 0x10 @ 0x58 ASPM: Enabled L0s and L1 Capability: type 0x01 @ 0x6c Capability: type 0x05 @ 0x48 Capability: type 0x10 @ 0x80 scan_bus: scanning of bus PCI: 00:02.4 took 40422 usecs PCI: 00:14.0 scanning... scan_generic_bus for PCI: 00:14.0 scan_generic_bus for PCI: 00:14.0 done scan_bus: scanning of bus PCI: 00:14.0 took 8803 usecs PCI: 00:14.3 scanning... scan_lpc_bus for PCI: 00:14.3 PNP: 0c09.0 enabled scan_lpc_bus for PCI: 00:14.3 done scan_bus: scanning of bus PCI: 00:14.3 took 9940 usecs POST: 0x55 scan_bus: scanning of bus DOMAIN: 0000 took 289514 usecs MMIO: fedc2000 scanning... scan_generic_bus for MMIO: fedc2000 bus: MMIO: fedc2000[0]->GENERIC: 0.0 enabled bus: MMIO: fedc2000[0]->I2C: 01:1a enabled bus: MMIO: fedc2000[0]->GENERIC: 0.1 enabled scan_generic_bus for MMIO: fedc2000 done scan_bus: scanning of bus MMIO: fedc2000 took 21220 usecs MMIO: fedc3000 scanning... scan_generic_bus for MMIO: fedc3000 bus: MMIO: fedc3000[0]->I2C: 02:50 enabled scan_generic_bus for MMIO: fedc3000 done scan_bus: scanning of bus MMIO: fedc3000 took 13187 usecs MMIO: fedc4000 scanning... scan_generic_bus for MMIO: fedc4000 bus: MMIO: fedc4000[0]->I2C: 03:15 enabled scan_generic_bus for MMIO: fedc4000 done scan_bus: scanning of bus MMIO: fedc4000 took 13154 usecs MMIO: fedc5000 scanning... scan_generic_bus for MMIO: fedc5000 bus: MMIO: fedc5000[0]->I2C: 04:39 enabled bus: MMIO: fedc5000[0]->I2C: 04:10 enabled scan_generic_bus for MMIO: fedc5000 done scan_bus: scanning of bus MMIO: fedc5000 took 16986 usecs root_dev_scan_bus for Root Device done scan_bus: scanning of bus Root Device took 400714 usecs done BS: BS_DEV_ENUMERATE times (us): entry 0 run 605700 exit 0 POST: 0x73 found VGA at PCI: 00:01.0 Setting up VGA for PCI: 00:01.0 Setting PCI_BRIDGE_CTL_VGA for bridge DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done DOMAIN: 0000 read_resources bus 0 link: 0 PCI: 00:02.2 read_resources bus 1 link: 0 PCI: 00:02.2 read_resources bus 1 link: 0 done PCI: 00:02.4 read_resources bus 2 link: 0 PCI: 00:02.4 read_resources bus 2 link: 0 done PCI: 00:14.3 read_resources bus 0 link: 0 PCI: 00:14.3 read_resources bus 0 link: 0 done Adding PCIe enhanced config space BAR 0xf8000000-0xfc000000. DOMAIN: 0000 read_resources bus 0 link: 0 done MMIO: fedc2000 read_resources bus 1 link: 0 MMIO: fedc2000 read_resources bus 1 link: 0 done MMIO: fedc3000 read_resources bus 2 link: 0 MMIO: fedc3000 read_resources bus 2 link: 0 done MMIO: fedc4000 read_resources bus 3 link: 0 MMIO: fedc4000 read_resources bus 3 link: 0 done MMIO: fedc5000 read_resources bus 4 link: 0 MMIO: fedc5000 read_resources bus 4 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 10 APIC: 10 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI: 00:00.0 PCI: 00:00.2 PCI: 00:01.0 PCI: 00:01.0 resource base 0 size 4000000 align 26 gran 26 limit ffffffffffffffff flags 1201 index 10 PCI: 00:01.0 resource base 0 size 800000 align 23 gran 23 limit ffffffffffffffff flags 1201 index 18 PCI: 00:01.0 resource base 0 size 100 align 8 gran 8 limit ffff flags 100 index 20 PCI: 00:01.0 resource base 0 size 40000 align 18 gran 18 limit ffffffff flags 200 index 24 PCI: 00:01.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 2200 index 30 PCI: 00:01.1 PCI: 00:01.1 resource base 0 size 4000 align 14 gran 14 limit ffffffffffffffff flags 201 index 10 PCI: 00:02.0 PCI: 00:02.1 PCI: 00:02.2 child on link 0 PCI: 01:00.0 PCI: 00:02.2 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:02.2 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:02.2 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 01:00.0 PCI: 01:00.0 resource base 0 size 200000 align 21 gran 21 limit ffffffffffffffff flags 201 index 10 PCI: 00:02.3 PCI: 00:02.4 child on link 0 PCI: 02:00.0 PCI: 00:02.4 resource base 0 size 0 align 12 gran 12 limit ffffffff flags 80102 index 1c PCI: 00:02.4 resource base 0 size 0 align 20 gran 20 limit ffffffffffffffff flags 81202 index 24 PCI: 00:02.4 resource base 0 size 0 align 20 gran 20 limit ffffffff flags 80202 index 20 PCI: 02:00.0 PCI: 02:00.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 10 PCI: 02:00.0 resource base 0 size 800 align 12 gran 11 limit ffffffff flags 200 index 14 PCI: 00:02.5 PCI: 00:03.0 PCI: 00:08.0 PCI: 00:08.0 resource base 0 size 20000 align 17 gran 17 limit ffffffffffffffff flags 1201 index 10 PCI: 00:08.0 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 200 index 18 PCI: 00:08.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 1c PCI: 00:08.0 resource base 0 size 100000 align 20 gran 20 limit ffffffff flags 200 index 20 PCI: 00:08.0 resource base 0 size 2000 align 13 gran 13 limit ffffffff flags 200 index 24 PCI: 00:09.0 PCI: 00:09.2 PCI: 00:10.0 PCI: 00:11.0 PCI: 00:12.0 PCI: 00:14.0 PCI: 00:14.3 child on link 0 PNP: 0c09.0 PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:14.3 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100 PCI: 00:14.3 resource base fec10000 size 400 align 0 gran 0 limit 0 flags e0040200 index 2 PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PCI: 00:14.3 resource base fedc2000 size 4000 align 0 gran 0 limit 0 flags c0000200 index 4 PNP: 0c09.0 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0 PCI: 00:14.7 PCI: 00:18.0 PCI: 00:18.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI: 00:18.0 resource base fec20000 size 1000 align 0 gran 0 limit 0 flags c0000200 index fec20000 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.4 PCI: 00:18.5 MMIO: fedc2000 child on link 0 GENERIC: 0.0 GENERIC: 0.0 I2C: 01:1a GENERIC: 0.1 MMIO: fedc3000 child on link 0 I2C: 02:50 I2C: 02:50 MMIO: fedc4000 child on link 0 I2C: 03:15 I2C: 03:15 MMIO: fedc5000 child on link 0 I2C: 04:39 I2C: 04:39 I2C: 04:10 DOMAIN: 0000 io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:02.2 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:02.2 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:02.4 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff PCI: 00:02.4 io: base: 0 size: 0 align: 12 gran: 12 limit: ffffffff done PCI: 00:01.0 20 * [0x0 - 0xff] io DOMAIN: 0000 io: base: 100 size: 100 align: 8 gran: 0 limit: ffff done DOMAIN: 0000 mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:02.2 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:02.2 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:02.2 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 01:00.0 10 * [0x0 - 0x1fffff] mem PCI: 00:02.2 mem: base: 200000 size: 200000 align: 21 gran: 20 limit: ffffffff done PCI: 00:02.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff PCI: 00:02.4 prefmem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffffffffffff done PCI: 00:02.4 mem: base: 0 size: 0 align: 20 gran: 20 limit: ffffffff PCI: 02:00.0 10 * [0x0 - 0xfff] mem PCI: 02:00.0 14 * [0x1000 - 0x17ff] mem PCI: 00:02.4 mem: base: 1800 size: 100000 align: 20 gran: 20 limit: ffffffff done PCI: 00:01.0 10 * [0x0 - 0x3ffffff] prefmem PCI: 00:01.0 18 * [0x4000000 - 0x47fffff] prefmem PCI: 00:02.2 20 * [0x4800000 - 0x49fffff] mem PCI: 00:02.4 20 * [0x4a00000 - 0x4afffff] mem PCI: 00:08.0 18 * [0x4b00000 - 0x4bfffff] mem PCI: 00:08.0 20 * [0x4c00000 - 0x4cfffff] mem PCI: 00:01.0 24 * [0x4d00000 - 0x4d3ffff] mem PCI: 00:01.0 30 * [0x4d40000 - 0x4d5ffff] mem PCI: 00:08.0 10 * [0x4d60000 - 0x4d7ffff] prefmem PCI: 00:01.1 10 * [0x4d80000 - 0x4d83fff] mem PCI: 00:08.0 24 * [0x4d84000 - 0x4d85fff] mem PCI: 00:08.0 1c * [0x4d86000 - 0x4d86fff] mem DOMAIN: 0000 mem: base: 4d87000 size: 4d87000 align: 26 gran: 0 limit: ffffffff done avoid_fixed_resources: DOMAIN: 0000 avoid_fixed_resources:@DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI: 00:14.3 10000000 base 00000000 limit 00000fff io (fixed) constrain_resources: PCI: 00:14.3 10000100 base ff000000 limit ffffffff mem (fixed) constrain_resources: PCI: 00:14.3 02 base fec10000 limit fec103ff mem (fixed) constrain_resources: PCI: 00:14.3 03 base fec00000 limit fec00fff mem (fixed) constrain_resources: PCI: 00:18.0 c0010058 base f8000000 limit fbffffff mem (fixed) avoid_fixed_resources:@DOMAIN: 0000 10000000 base 00001000 limit 0000ffff avoid_fixed_resources:@DOMAIN: 0000 10000100 base f0000000 limit f7ffffff Setting resources... DOMAIN: 0000 io: base:1000 size:100 align:8 gran:0 limit:ffff PCI: 00:01.0 20 * [0x1000 - 0x10ff] io DOMAIN: 0000 io: next_base: 1100 size: 100 align: 8 gran: 0 done PCI: 00:02.2 io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:02.2 io: next_base: ffff size: 0 align: 12 gran: 12 done PCI: 00:02.4 io: base:ffff size:0 align:12 gran:12 limit:ffff PCI: 00:02.4 io: next_base: ffff size: 0 align: 12 gran: 12 done DOMAIN: 0000 mem: base:f0000000 size:4d87000 align:26 gran:0 limit:f7ffffff PCI: 00:01.0 10 * [0xf0000000 - 0xf3ffffff] prefmem PCI: 00:01.0 18 * [0xf4000000 - 0xf47fffff] prefmem PCI: 00:02.2 20 * [0xf4800000 - 0xf49fffff] mem PCI: 00:02.4 20 * [0xf4a00000 - 0xf4afffff] mem PCI: 00:08.0 18 * [0xf4b00000 - 0xf4bfffff] mem PCI: 00:08.0 20 * [0xf4c00000 - 0xf4cfffff] mem PCI: 00:01.0 24 * [0xf4d00000 - 0xf4d3ffff] mem PCI: 00:01.0 30 * [0xf4d40000 - 0xf4d5ffff] mem PCI: 00:08.0 10 * [0xf4d60000 - 0xf4d7ffff] prefmem PCI: 00:01.1 10 * [0xf4d80000 - 0xf4d83fff] mem PCI: 00:08.0 24 * [0xf4d84000 - 0xf4d85fff] mem PCI: 00:08.0 1c * [0xf4d86000 - 0xf4d86fff] mem DOMAIN: 0000 mem: next_base: f4d87000 size: 4d87000 align: 26 gran: 0 done PCI: 00:02.2 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff PCI: 00:02.2 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done PCI: 00:02.2 mem: base:f4800000 size:200000 align:21 gran:20 limit:f49fffff PCI: 01:00.0 10 * [0xf4800000 - 0xf49fffff] mem PCI: 00:02.2 mem: next_base: f4a00000 size: 200000 align: 21 gran: 20 done PCI: 00:02.4 prefmem: base:f7ffffff size:0 align:20 gran:20 limit:f7ffffff PCI: 00:02.4 prefmem: next_base: f7ffffff size: 0 align: 20 gran: 20 done PCI: 00:02.4 mem: base:f4a00000 size:100000 align:20 gran:20 limit:f4afffff PCI: 02:00.0 10 * [0xf4a00000 - 0xf4a00fff] mem PCI: 02:00.0 14 * [0xf4a01000 - 0xf4a017ff] mem PCI: 00:02.4 mem: next_base: f4a01800 size: 100000 align: 20 gran: 20 done Root Device assign_resources, bus 0 link: 0 DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:01.0 10 <- [0x00f0000000 - 0x00f3ffffff] size 0x04000000 gran 0x1a prefmem64 PCI: 00:01.0 18 <- [0x00f4000000 - 0x00f47fffff] size 0x00800000 gran 0x17 prefmem64 PCI: 00:01.0 20 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x08 io PCI: 00:01.0 24 <- [0x00f4d00000 - 0x00f4d3ffff] size 0x00040000 gran 0x12 mem PCI: 00:01.0 30 <- [0x00f4d40000 - 0x00f4d5ffff] size 0x00020000 gran 0x11 romem PCI: 00:01.1 10 <- [0x00f4d80000 - 0x00f4d83fff] size 0x00004000 gran 0x0e mem64 PCI: 00:02.2 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 01 io PCI: 00:02.2 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 01 prefmem PCI: 00:02.2 20 <- [0x00f4800000 - 0x00f49fffff] size 0x00200000 gran 0x14 bus 01 mem PCI: 00:02.2 assign_resources, bus 1 link: 0 PCI: 01:00.0 10 <- [0x00f4800000 - 0x00f49fffff] size 0x00200000 gran 0x15 mem64 PCI: 00:02.2 assign_resources, bus 1 link: 0 PCI: 00:02.4 1c <- [0x000000ffff - 0x000000fffe] size 0x00000000 gran 0x0c bus 02 io PCI: 00:02.4 24 <- [0x00f7ffffff - 0x00f7fffffe] size 0x00000000 gran 0x14 bus 02 prefmem PCI: 00:02.4 20 <- [0x00f4a00000 - 0x00f4afffff] size 0x00100000 gran 0x14 bus 02 mem PCI: 00:02.4 assign_resources, bus 2 link: 0 PCI: 02:00.0 10 <- [0x00f4a00000 - 0x00f4a00fff] size 0x00001000 gran 0x0c mem PCI: 02:00.0 14 <- [0x00f4a01000 - 0x00f4a017ff] size 0x00000800 gran 0x0b mem PCI: 00:02.4 assign_resources, bus 2 link: 0 PCI: 00:08.0 10 <- [0x00f4d60000 - 0x00f4d7ffff] size 0x00020000 gran 0x11 prefmem64 PCI: 00:08.0 18 <- [0x00f4b00000 - 0x00f4bfffff] size 0x00100000 gran 0x14 mem PCI: 00:08.0 1c <- [0x00f4d86000 - 0x00f4d86fff] size 0x00001000 gran 0x0c mem PCI: 00:08.0 20 <- [0x00f4c00000 - 0x00f4cfffff] size 0x00100000 gran 0x14 mem PCI: 00:08.0 24 <- [0x00f4d84000 - 0x00f4d85fff] size 0x00002000 gran 0x0d mem PCI: 00:14.3 assign_resources, bus 0 link: 0 PCI: 00:14.3 assign_resources, bus 0 link: 0 DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device child on link 0 CPU_CLUSTER: 0 CPU_CLUSTER: 0 child on link 0 APIC: 10 APIC: 10 DOMAIN: 0000 child on link 0 PCI: 00:00.0 DOMAIN: 0000 resource base 1000 size 100 align 8 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base f0000000 size 4d87000 align 26 gran 0 limit f7ffffff flags 40040200 index 10000100 DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index 10 DOMAIN: 0000 resource base a0000 size 20000 align 0 gran 0 limit 0 flags f0000200 index 11 DOMAIN: 0000 resource base c0000 size 40000 align 0 gran 0 limit 0 flags f0004200 index 12 DOMAIN: 0000 resource base 100000 size cdf00000 align 0 gran 0 limit 0 flags e0004200 index 13 DOMAIN: 0000 resource base ce000000 size 2000000 align 0 gran 0 limit 0 flags f0004200 index 14 DOMAIN: 0000 resource base 100000000 size 2f000000 align 0 gran 0 limit 0 flags e0004200 index 15 PCI: 00:00.0 PCI: 00:00.2 PCI: 00:01.0 PCI: 00:01.0 resource base f0000000 size 4000000 align 26 gran 26 limit f3ffffff flags 60001201 index 10 PCI: 00:01.0 resource base f4000000 size 800000 align 23 gran 23 limit f47fffff flags 60001201 index 18 PCI: 00:01.0 resource base 1000 size 100 align 8 gran 8 limit 10ff flags 60000100 index 20 PCI: 00:01.0 resource base f4d00000 size 40000 align 18 gran 18 limit f4d3ffff flags 60000200 index 24 PCI: 00:01.0 resource base f4d40000 size 20000 align 17 gran 17 limit f4d5ffff flags 60002200 index 30 PCI: 00:01.1 PCI: 00:01.1 resource base f4d80000 size 4000 align 14 gran 14 limit f4d83fff flags 60000201 index 10 PCI: 00:02.0 PCI: 00:02.1 PCI: 00:02.2 child on link 0 PCI: 01:00.0 PCI: 00:02.2 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:02.2 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24 PCI: 00:02.2 resource base f4800000 size 200000 align 21 gran 20 limit f49fffff flags 60080202 index 20 PCI: 01:00.0 PCI: 01:00.0 resource base f4800000 size 200000 align 21 gran 21 limit f49fffff flags 60000201 index 10 PCI: 00:02.3 PCI: 00:02.4 child on link 0 PCI: 02:00.0 PCI: 00:02.4 resource base ffff size 0 align 12 gran 12 limit ffff flags 60080102 index 1c PCI: 00:02.4 resource base f7ffffff size 0 align 20 gran 20 limit f7ffffff flags 60081202 index 24 PCI: 00:02.4 resource base f4a00000 size 100000 align 20 gran 20 limit f4afffff flags 60080202 index 20 PCI: 02:00.0 PCI: 02:00.0 resource base f4a00000 size 1000 align 12 gran 12 limit f4a00fff flags 60000200 index 10 PCI: 02:00.0 resource base f4a01000 size 800 align 12 gran 11 limit f4a017ff flags 60000200 index 14 PCI: 00:02.5 PCI: 00:03.0 PCI: 00:08.0 PCI: 00:08.0 resource base f4d60000 size 20000 align 17 gran 17 limit f4d7ffff flags 60001201 index 10 PCI: 00:08.0 resource base f4b00000 size 100000 align 20 gran 20 limit f4bfffff flags 60000200 index 18 PCI: 00:08.0 resource base f4d86000 size 1000 align 12 gran 12 limit f4d86fff flags 60000200 index 1c PCI: 00:08.0 resource base f4c00000 size 100000 align 20 gran 20 limit f4cfffff flags 60000200 index 20 PCI: 00:08.0 resource base f4d84000 size 2000 align 13 gran 13 limit f4d85fff flags 60000200 index 24 PCI: 00:09.0 PCI: 00:09.2 PCI: 00:10.0 PCI: 00:11.0 PCI: 00:12.0 PCI: 00:14.0 PCI: 00:14.3 child on link 0 PNP: 0c09.0 PCI: 00:14.3 resource base 0 size 1000 align 0 gran 0 limit 0 flags c0040100 index 10000000 PCI: 00:14.3 resource base ff000000 size 1000000 align 0 gran 0 limit 0 flags c0040200 index 10000100 PCI: 00:14.3 resource base fec10000 size 400 align 0 gran 0 limit 0 flags e0040200 index 2 PCI: 00:14.3 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PCI: 00:14.3 resource base fedc2000 size 4000 align 0 gran 0 limit 0 flags c0000200 index 4 PNP: 0c09.0 PNP: 0c09.0 resource base 800 size 1ff align 0 gran 0 limit 0 flags c0000100 index 0 PCI: 00:14.7 PCI: 00:18.0 PCI: 00:18.0 resource base f8000000 size 4000000 align 0 gran 0 limit 0 flags f0000200 index c0010058 PCI: 00:18.0 resource base fec20000 size 1000 align 0 gran 0 limit 0 flags c0000200 index fec20000 PCI: 00:18.1 PCI: 00:18.2 PCI: 00:18.3 PCI: 00:18.4 PCI: 00:18.5 MMIO: fedc2000 child on link 0 GENERIC: 0.0 GENERIC: 0.0 I2C: 01:1a GENERIC: 0.1 MMIO: fedc3000 child on link 0 I2C: 02:50 I2C: 02:50 MMIO: fedc4000 child on link 0 I2C: 03:15 I2C: 03:15 MMIO: fedc5000 child on link 0 I2C: 04:39 I2C: 04:39 I2C: 04:10 Done allocating resources. BS: BS_DEV_RESOURCES times (us): entry 0 run 1463948 exit 0 PCI_INTR tables: Writing registers C00/C01 for PCI IRQ routing: PCI_INTR_INDEX name PIC mode APIC mode 0x00 INTA# 0x03 0x10 0x01 INTB# 0x04 0x11 0x02 INTC# 0x05 0x12 0x03 INTD# 0x07 0x13 0x04 INTE# 0x0B 0x14 0x05 INTF# 0x1F 0x1F 0x06 INTG# 0x1F 0x16 0x07 INTH# 0x1F 0x17 0x08 Misc 0xFA 0x00 0x09 Misc0 0xF1 0x00 0x0A Misc1 0x00 0x00 0x0B Misc2 0x00 0x00 0x0C Ser IRQ INTA 0x1F 0x1F 0x0D Ser IRQ INTB 0x1F 0x1F 0x0E Ser IRQ INTC 0x1F 0x1F 0x0F Ser IRQ INTD 0x1F 0x1F 0x10 SCI 0x09 0x09 0x11 SMBUS 0x1F 0x1F 0x12 ASF 0x1F 0x1F 0x13 HDA 0x03 0x10 0x14 FC 0x1F 0x1F 0x16 PerMon 0x1F 0x1F 0x17 SD 0x03 0x10 0x1A SDIOt 0x00 0x1F 0x30 EHCI 0x05 0x12 0x34 XHCI 0x04 0x12 0x41 SATA 0x07 0x13 0x62 GPIO 0x07 0x07 0x70 I2C0 0x03 0x03 0x71 I2C1 0x0F 0x0F 0x72 I2C2 0x06 0x06 0x73 I2C3 0x0E 0x0E 0x74 UART0 0x0A 0x0A 0x75 UART1 0x0B 0x0B PCI_CFG IRQ: Write PCI config space IRQ assignments PCI IRQ: Found device 0:01.00 using PIN A PCI Devfn (0x8) not found in pirq_data table PCI IRQ: Found device 0:01.01 using PIN B Found this device in pirq_data table entry 5 Orig INT_PIN : 2 (PIN B) PCI_INTR idx : 0x13 (HDA) INT_LINE : 0x3 (IRQ 3) PCI IRQ: Found device 0:02.02 using PIN A Found this device in pirq_data table entry 1 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x01 (INTB#) INT_LINE : 0x4 (IRQ 4) PCI IRQ: Found device 0:02.04 using PIN A Found this device in pirq_data table entry 3 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x03 (INTD#) INT_LINE : 0x7 (IRQ 7) PCI IRQ: Found device 0:08.00 using PIN A PCI Devfn (0x40) not found in pirq_data table PCI IRQ: Found device 2:00.00 using PIN A With INT_PIN swizzled to PIN A Attached to bridge device 0:02h.04h Found this device in pirq_data table entry 3 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x03 (INTD#) INT_LINE : 0x7 (IRQ 7) PCI IRQ: Found device 1:00.00 using PIN A With INT_PIN swizzled to PIN A Attached to bridge device 0:02h.02h Found this device in pirq_data table entry 1 Orig INT_PIN : 1 (PIN A) PCI_INTR idx : 0x01 (INTB#) INT_LINE : 0x4 (IRQ 4) PCI_CFG IRQ: Finished writing PCI config space IRQ assignments POST: 0x74 Enabling resources... PCI: 00:00.0 subsystem <- 1022/1576 PCI: 00:00.0 cmd <- 04 PCI: 00:01.0 subsystem <- 1002/98e4 PCI: 00:01.0 cmd <- 07 PCI: 00:01.1 subsystem <- 1002/15b3 PCI: 00:01.1 cmd <- 02 PCI: 00:02.0 subsystem <- 1022/157b PCI: 00:02.0 cmd <- 00 PCI: 00:02.2 bridge ctrl <- 0003 PCI: 00:02.2 cmd <- 06 PCI: 00:02.4 bridge ctrl <- 0003 PCI: 00:02.4 cmd <- 06 PCI: 00:03.0 cmd <- 00 PCI: 00:08.0 subsystem <- 1022/1578 PCI: 00:08.0 cmd <- 06 PCI: 00:09.0 subsystem <- 1022/157d PCI: 00:09.0 cmd <- 00 PCI: 00:14.0 subsystem <- 1022/790b PCI: 00:14.0 cmd <- 403 PCI: 00:14.3 subsystem <- 1022/790e PCI: 00:14.3 cmd <- 0f Southbridge LPC decode:PNP: 0c09.0, base=0x00000800, end=0x000009fe Covered by wideIO 0 PCI: 00:18.0 cmd <- 00 PCI: 00:18.1 subsystem <- 1022/15b1 PCI: 00:18.1 cmd <- 00 PCI: 00:18.2 subsystem <- 1022/15b2 PCI: 00:18.2 cmd <- 00 PCI: 00:18.3 subsystem <- 1022/15b3 PCI: 00:18.3 cmd <- 00 PCI: 00:18.4 subsystem <- 1022/15b4 PCI: 00:18.4 cmd <- 00 PCI: 00:18.5 subsystem <- 1022/15b5 PCI: 00:18.5 cmd <- 00 PCI: 01:00.0 cmd <- 02 PCI: 02:00.0 subsystem <- 1217/8620 PCI: 02:00.0 cmd <- 06 done. BS: BS_DEV_ENABLE times (us): entry 235064 run 103738 exit 0 POST: 0x75 Initializing devices... Root Device init ... Root Device init finished in 1947 usecs POST: 0x75 CPU_CLUSTER: 0 init ... MTRR: Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x00000000d0000000 size 0xcff40000 type 6 0x00000000d0000000 - 0x00000000f0000000 size 0x20000000 type 0 0x00000000f0000000 - 0x00000000f4800000 size 0x04800000 type 1 0x00000000f4800000 - 0x0000000100000000 size 0x0b800000 type 0 0x0000000100000000 - 0x000000012f000000 size 0x2f000000 type 6 MTRR: Fixed MSR 0x250 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x258 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x259 0x0000000000000000 MTRR: Fixed MSR 0x268 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x269 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26a 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26b 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26c 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26d 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26e 0x1e1e1e1e1e1e1e1e MTRR: Fixed MSR 0x26f 0x1e1e1e1e1e1e1e1e call enable_fixed_mtrr() CPU physical address size: 48 bits MTRR: default type WB/UC MTRR counts: 8/6. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000ffff80000000 type 6 MTRR: 1 base 0x0000000080000000 mask 0x0000ffffc0000000 type 6 MTRR: 2 base 0x00000000c0000000 mask 0x0000fffff0000000 type 6 MTRR: 3 base 0x00000000f0000000 mask 0x0000fffffc000000 type 1 MTRR: 4 base 0x00000000f4000000 mask 0x0000ffffff800000 type 1 MTRR: 5 base 0x0000000100000000 mask 0x0000ffffc0000000 type 6 MTRR check Fixed MTRRs : Enabled Variable MTRRs: Enabled POST: 0x93 Will perform SMM setup. CPU: AMD A4-9120C RADEON R4, 5 COMPUTE CORES 2C+3G . Loading module at 00030000 with entry 00030000. filesize: 0x170 memsize: 0x170 Processing 16 relocs. Offset value of 0x00030000 Attempting to start 1 APs Waiting for 10ms after sending INIT. Waiting for 1st SIPI to complete...AP: slot 1 apic_id 11. done. Waiting for 2nd SIPI to complete...done. Loading module at 00038000 with entry 00038000. filesize: 0x1a8 memsize: 0x1a8 Processing 13 relocs. Offset value of 0x00038000 SMM Module: stub loaded at 00038000. Will call cdeb995b(00000000) Installing SMM handler to 0xce800000 Loading module at ce810000 with entry ce81142b. filesize: 0x6c98 memsize: 0xad18 Processing 481 relocs. Offset value of 0xce810000 Loading module at ce808000 with entry ce808000. filesize: 0x1a8 memsize: 0x1a8 Processing 13 relocs. Offset value of 0xce808000 SMM Module: placing jmp sequence at ce807e00 rel16 0x01fd SMM Module: stub loaded at ce808000. Will call ce81142b(00000000) New SMBASE 0xce800000 Relocation complete. New SMBASE 0xce7ffe00 Relocation complete. Initializing CPU #0 CPU: vendor AMD device 670f00 CPU: family 15, model 70, stepping 00 Setting up local APIC... apic_id: 0x10 done. CPU #0 initialized Initializing CPU #1 CPU: vendor AMD device 670f00 CPU: family 15, model 70, stepping 00 Setting up local APIC... apic_id: 0x11 done. CPU #1 initialized bsp_do_flight_plan done after 91 msecs. MTRR: TEMPORARY Physical address space: 0x0000000000000000 - 0x00000000000a0000 size 0x000a0000 type 6 0x00000000000a0000 - 0x00000000000c0000 size 0x00020000 type 0 0x00000000000c0000 - 0x00000000d0000000 size 0xcff40000 type 6 0x00000000d0000000 - 0x00000000ff000000 size 0x2f000000 type 0 0x00000000ff000000 - 0x0000000100000000 size 0x01000000 type 5 0x0000000100000000 - 0x000000012f000000 size 0x2f000000 type 6 MTRR: default type WB/UC MTRR counts: 7/5. MTRR: UC selected as default type. MTRR: 0 base 0x0000000000000000 mask 0x0000ffff80000000 type 6 MTRR: 1 base 0x0000000080000000 mask 0x0000ffffc0000000 type 6 MTRR: 2 base 0x00000000c0000000 mask 0x0000fffff0000000 type 6 MTRR: 3 base 0x00000000ff000000 mask 0x0000ffffff000000 type 5 MTRR: 4 base 0x0000000100000000 mask 0x0000ffffc0000000 type 6 CPU_CLUSTER: 0 init finished in 345969 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 PCI: 00:00.0 init ... PCI: 00:00.0 init finished in 2002 usecs POST: 0x75 POST: 0x75 PCI: 00:01.0 init ... PCI: 00:01.0 init finished in 2002 usecs POST: 0x75 PCI: 00:01.1 init ... PCI: 00:01.1 init finished in 2002 usecs POST: 0x75 PCI: 00:02.0 init ... PCI: 00:02.0 init finished in 2002 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 PCI: 00:03.0 init ... PCI: 00:03.0 init finished in 2002 usecs POST: 0x75 PCI: 00:08.0 init ... PCI: 00:08.0 init finished in 2002 usecs POST: 0x75 PCI: 00:09.0 init ... PCI: 00:09.0 init finished in 2002 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 PCI: 00:14.0 init ... IOAPIC: Initializing IOAPIC at 0xfec00000 IOAPIC: Bootstrap Processor Local APIC = 0x10 IOAPIC: ID = 0x04 IOAPIC: Dumping registers reg 0x0000: 0x04000000 reg 0x0001: 0x00178021 reg 0x0002: 0x04000000 IOAPIC: 24 interrupts IOAPIC: Enabling interrupts on FSB IOAPIC: reg 0x00000000 value 0x10000000 0x00000700 IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 IOAPIC: reg 0x00000017 value 0x00000000 0x00010000 PCI: 00:14.0 init finished in 133956 usecs POST: 0x75 PCI: 00:14.3 init ... PCI: 00:14.3 init finished in 2061 usecs POST: 0x75 POST: 0x75 PCI: 00:18.0 init ... IOAPIC: Initializing IOAPIC at 0xfec20000 IOAPIC: Bootstrap Processor Local APIC = 0x10 IOAPIC: ID = 0x05 IOAPIC: Dumping registers reg 0x0000: 0x05000000 reg 0x0001: 0x001f8021 reg 0x0002: 0x00000000 IOAPIC: 32 interrupts IOAPIC: Enabling interrupts on FSB IOAPIC: reg 0x00000000 value 0x10000000 0x00000700 IOAPIC: reg 0x00000001 value 0x00000000 0x00010000 IOAPIC: reg 0x00000002 value 0x00000000 0x00010000 IOAPIC: reg 0x00000003 value 0x00000000 0x00010000 IOAPIC: reg 0x00000004 value 0x00000000 0x00010000 IOAPIC: reg 0x00000005 value 0x00000000 0x00010000 IOAPIC: reg 0x00000006 value 0x00000000 0x00010000 IOAPIC: reg 0x00000007 value 0x00000000 0x00010000 IOAPIC: reg 0x00000008 value 0x00000000 0x00010000 IOAPIC: reg 0x00000009 value 0x00000000 0x00010000 IOAPIC: reg 0x0000000a value 0x00000000 0x00010000 IOAPIC: reg 0x0000000b value 0x00000000 0x00010000 IOAPIC: reg 0x0000000c value 0x00000000 0x00010000 IOAPIC: reg 0x0000000d value 0x00000000 0x00010000 IOAPIC: reg 0x0000000e value 0x00000000 0x00010000 IOAPIC: reg 0x0000000f value 0x00000000 0x00010000 IOAPIC: reg 0x00000010 value 0x00000000 0x00010000 IOAPIC: reg 0x00000011 value 0x00000000 0x00010000 IOAPIC: reg 0x00000012 value 0x00000000 0x00010000 IOAPIC: reg 0x00000013 value 0x00000000 0x00010000 IOAPIC: reg 0x00000014 value 0x00000000 0x00010000 IOAPIC: reg 0x00000015 value 0x00000000 0x00010000 IOAPIC: reg 0x00000016 value 0x00000000 0x00010000 IOAPIC: reg 0x00000017 value 0x00000000 0x00010000 IOAPIC: reg 0x00000018 value 0x00000000 0x00010000 IOAPIC: reg 0x00000019 value 0x00000000 0x00010000 IOAPIC: reg 0x0000001a value 0x00000000 0x00010000 IOAPIC: reg 0x0000001b value 0x00000000 0x00010000 IOAPIC: reg 0x0000001c value 0x00000000 0x00010000 IOAPIC: reg 0x0000001d value 0x00000000 0x00010000 IOAPIC: reg 0x0000001e value 0x00000000 0x00010000 IOAPIC: reg 0x0000001f value 0x00000000 0x00010000 PCI: 00:18.0 init finished in 170028 usecs POST: 0x75 PCI: 00:18.1 init ... PCI: 00:18.1 init finished in 2002 usecs POST: 0x75 PCI: 00:18.2 init ... PCI: 00:18.2 init finished in 2002 usecs POST: 0x75 PCI: 00:18.3 init ... PCI: 00:18.3 init finished in 2002 usecs POST: 0x75 PCI: 00:18.4 init ... PCI: 00:18.4 init finished in 2002 usecs POST: 0x75 PCI: 00:18.5 init ... PCI: 00:18.5 init finished in 2001 usecs POST: 0x75 PCI: 01:00.0 init ... PCI: 01:00.0 init finished in 2002 usecs POST: 0x75 PCI: 02:00.0 init ... BayHub BH720: Power-saving enabled (link_ctrl=0x110103) PCI: 02:00.0 init finished in 7127 usecs POST: 0x75 PNP: 0c09.0 init ... Google Chrome EC: Hello got back 11223344 status (0) Google Chrome EC: version: ro: careena_v2.0.11488-7215d6e0e4 rw: careena_v2.0.11488-7215d6e0e4 running image: 1 Google Chrome EC uptime: 185.830 seconds Google Chrome AP resets since EC boot: 0 Google Chrome most recent AP reset causes: Google Chrome EC reset flags at last EC boot: reset-pin PNP: 0c09.0 init finished in 34634 usecs POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 POST: 0x75 Devices initialized Show all devs... After init. Root Device: enabled 1 CPU_CLUSTER: 0: enabled 1 DOMAIN: 0000: enabled 1 MMIO: fedc2000: enabled 1 MMIO: fedc3000: enabled 1 MMIO: fedc4000: enabled 1 MMIO: fedc5000: enabled 1 APIC: 10: enabled 1 PCI: 00:00.0: enabled 1 PCI: 00:00.2: enabled 0 PCI: 00:01.0: enabled 1 PCI: 00:01.1: enabled 1 PCI: 00:02.0: enabled 1 PCI: 00:02.1: enabled 0 PCI: 00:02.2: enabled 1 PCI: 00:02.3: enabled 0 PCI: 00:02.4: enabled 1 PCI: 00:02.5: enabled 0 PCI: 00:08.0: enabled 1 PCI: 00:09.0: enabled 1 PCI: 00:09.2: enabled 0 PCI: 00:10.0: enabled 0 PCI: 00:11.0: enabled 0 PCI: 00:12.0: enabled 0 PCI: 00:14.0: enabled 1 PCI: 00:14.3: enabled 1 PCI: 00:14.7: enabled 0 PCI: 00:18.0: enabled 1 PCI: 00:18.1: enabled 1 PCI: 00:18.2: enabled 1 PCI: 00:18.3: enabled 1 PCI: 00:18.4: enabled 1 PCI: 00:18.5: enabled 1 GENERIC: 0.0: enabled 1 I2C: 01:1a: enabled 1 GENERIC: 0.1: enabled 1 I2C: 02:50: enabled 1 I2C: 03:15: enabled 1 I2C: 04:39: enabled 1 I2C: 04:10: enabled 1 PCI: 02:00.0: enabled 1 PNP: 0c09.0: enabled 1 PCI: 00:03.0: enabled 1 PCI: 01:00.0: enabled 1 APIC: 11: enabled 1 BS: BS_DEV_INIT times (us): entry 0 run 948018 exit 141 ELOG: Event(A1) added with size 10 at 2023-08-09 04:56:15 UTC elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x2b POST: 0x76 Finalize devices... Devices finalized FMAP: area RW_NVRAM found @ 467000 (20480 bytes) BS: BS_POST_DEVICE times (us): entry 12957 run 4545 exit 4693 FMAP: area RW_MRC_CACHE found @ 0 (65536 bytes) MRC: Checking cached data update for 'RW_MRC_CACHE'. POST: 0x77 Trying to find the wakeup vector... Looking on 000f0000 for valid checksum Checksum 1 passed Checksum 2 passed all OK RSDP found at 000f0000 RSDT found at cde2e030 ends at cde2e07c FADT found at cde31e60 FACS found at cde2e240 OS waking vector is 0009a1d0 BS: BS_OS_RESUME_CHECK times (us): entry 9558 run 24101 exit 0 agesawrapper_amds3finalrestore() entry S3 volatile data @0xceebe000 0x4160 total bytes agesawrapper_amds3finalrestore() returned AGESA_SUCCESS Lock SMM configuration POST: 0xfe Probing TPM I2C: done! DID_VID 0x00281ae0 Locality already claimed cr50 TPM 2.0 (i2c 1:0x50 id 0x28) Platform hierarchy disablement failed: 5001 POST: 0x78 mp_park_aps done after 0 msecs. Restore GNVS pointer to cde6b000 smm_setup_structures STUB!!! POST: 0xfd <6>[ 34.503273] ACPI: EC: interrupt blocked <6>[ 34.527001] ACPI: Preparing to enter system sleep state S3 <6>[ 34.527787] ACPI: EC: event blocked <6>[ 34.527788] ACPI: EC: EC stopped <6>[ 34.527789] PM: Saving platform NVS memory <6>[ 34.527790] Disabling non-boot CPUs ... <6>[ 34.529212] smpboot: CPU 1 is now offline <6>[ 34.529644] ACPI: Low-level resume complete <6>[ 34.529661] ACPI: EC: EC started <6>[ 34.529662] PM: Restoring platform NVS memory <6>[ 34.529679] LVT offset 0 assigned for vector 0x400 <6>[ 34.529941] Enabling non-boot CPUs ... <6>[ 34.529975] x86: Booting SMP configuration: <6>[ 34.529977] smpboot: Booting Node 0 Processor 1 APIC 0x11 <6>[ 34.530130] microcode: CPU1: patch_level=0x06006705 <6>[ 34.532470] ACPI: \_PR_.P001: Found 2 idle states <6>[ 34.532687] CPU1 is up <6>[ 34.532996] ACPI: Waking up from system sleep state S3 <6>[ 34.560155] ACPI: EC: interrupt unblocked <6>[ 34.586395] ACPI: EC: event unblocked <6>[ 34.587091] [drm] PCIE GART of 1024M enabled (table at 0x000000F400000000). <6>[ 34.587120] amdgpu: smu version 33.09.00 <6>[ 34.850523] usb 1-1.1: reset high-speed USB device number 3 using ehci-pci <6>[ 34.876939] r8152 2-4:1.0 eth0: carrier on <6>[ 35.271614] [drm] UVD initialized successfully. <6>[ 35.372721] [drm] VCE initialized successfully. <6>[ 35.498272] OOM killer enabled. <6>[ 35.501668] Restarting tasks ... done. <6>[ 35.508958] PM: suspend exit rtcwake: assuming RTC uses UTC ... rtcwake: wakeup from "freeze" using rtc0 at Wed Aug 9 04:56:22 2023 <6>[ 35.537172] PM: suspend entry (s2idle) <6>[ 35.541212] Filesystems sync: 0.000 seconds <6>[ 35.545912] Freezing user space processes ... (elapsed 0.001 seconds) done. <6>[ 35.554935] OOM killer disabled. <6>[ 35.558421] Freezing remaining freezable tasks ... (elapsed 1.099 seconds) done. <6>[ 36.682994] printk: Suspending console(s) (use no_console_suspend to debug) <6>[ 36.763533] ACPI: EC: interrupt blocked <6>[ 41.348644] ACPI: EC: interrupt unblocked <6>[ 41.375622] [drm] PCIE GART of 1024M enabled (table at 0x000000F400000000). <6>[ 41.375641] amdgpu: smu version 33.09.00 <6>[ 41.510625] [drm] UVD initialized successfully. <6>[ 41.611454] [drm] VCE initialized successfully. <6>[ 41.649455] r8152 2-4:1.0 eth0: carrier on <3>[ 42.647477] amdgpu 0000:00:01.0: [drm:amdgpu_ib_ring_tests] *ERROR* IB test failed on gfx (-110). <3>[ 42.647483] [drm:process_one_work] *ERROR* ib ring test failed (-110). <6>[ 42.698696] OOM killer enabled. <6>[ 42.702098] Restarting tasks ... done. <6>[ 42.709529] PM: suspend exit rtcwake: assuming RTC uses UTC ... rtcwake: wakeup from "freeze" using rtc0 at Wed Aug 9 04:56:29 2023 <6>[ 42.736766] PM: suspend entry (s2idle) <6>[ 42.740806] Filesystems sync: 0.000 seconds <6>[ 42.745405] Freezing user space processes ... (elapsed 0.001 seconds) done. <6>[ 42.754109] OOM killer disabled. <6>[ 42.757593] Freezing remaining freezable tasks ... (elapsed 1.045 seconds) done. <6>[ 43.835969] printk: Suspending console(s) (use no_console_suspend to debug)