Boot log: mt8192-asurada-spherion-r0
- Errors: 2
- Kernel Errors: 27
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 23
1 22:11:48.414982 lava-dispatcher, installed at version: 2023.03
2 22:11:48.415277 start: 0 validate
3 22:11:48.415404 Start time: 2023-06-04 22:11:48.415397+00:00 (UTC)
4 22:11:48.415526 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:11:48.415652 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 22:11:48.704189 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:11:48.704976 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1281-g84d5372e0f314%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:11:49.000253 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:11:49.001341 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1281-g84d5372e0f314%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:12:11.547040 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:12:11.547949 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1281-g84d5372e0f314%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 22:12:12.129881 validate duration: 23.71
14 22:12:12.131140 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 22:12:12.131698 start: 1.1 download-retry (timeout 00:10:00) [common]
16 22:12:12.132188 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 22:12:12.132775 Not decompressing ramdisk as can be used compressed.
18 22:12:12.133250 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230527.0/arm64/rootfs.cpio.gz
19 22:12:12.133607 saving as /var/lib/lava/dispatcher/tmp/10583893/tftp-deploy-arhndd4y/ramdisk/rootfs.cpio.gz
20 22:12:12.133945 total size: 8186575 (7MB)
21 22:12:15.274026 progress 0% (0MB)
22 22:12:15.286776 progress 5% (0MB)
23 22:12:15.297865 progress 10% (0MB)
24 22:12:15.305427 progress 15% (1MB)
25 22:12:15.307506 progress 20% (1MB)
26 22:12:15.309691 progress 25% (1MB)
27 22:12:15.311798 progress 30% (2MB)
28 22:12:15.314013 progress 35% (2MB)
29 22:12:15.316191 progress 40% (3MB)
30 22:12:15.318404 progress 45% (3MB)
31 22:12:15.320547 progress 50% (3MB)
32 22:12:15.322767 progress 55% (4MB)
33 22:12:15.324936 progress 60% (4MB)
34 22:12:15.327122 progress 65% (5MB)
35 22:12:15.329318 progress 70% (5MB)
36 22:12:15.331584 progress 75% (5MB)
37 22:12:15.333587 progress 80% (6MB)
38 22:12:15.335821 progress 85% (6MB)
39 22:12:15.337778 progress 90% (7MB)
40 22:12:15.339967 progress 95% (7MB)
41 22:12:15.342016 progress 100% (7MB)
42 22:12:15.342231 7MB downloaded in 3.21s (2.43MB/s)
43 22:12:15.342376 end: 1.1.1 http-download (duration 00:00:03) [common]
45 22:12:15.342608 end: 1.1 download-retry (duration 00:00:03) [common]
46 22:12:15.342692 start: 1.2 download-retry (timeout 00:09:57) [common]
47 22:12:15.342776 start: 1.2.1 http-download (timeout 00:09:57) [common]
48 22:12:15.342908 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1281-g84d5372e0f314/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 22:12:15.342977 saving as /var/lib/lava/dispatcher/tmp/10583893/tftp-deploy-arhndd4y/kernel/Image
50 22:12:15.343036 total size: 45746688 (43MB)
51 22:12:15.343094 No compression specified
52 22:12:15.344212 progress 0% (0MB)
53 22:12:15.355631 progress 5% (2MB)
54 22:12:15.366940 progress 10% (4MB)
55 22:12:15.378155 progress 15% (6MB)
56 22:12:15.389588 progress 20% (8MB)
57 22:12:15.400956 progress 25% (10MB)
58 22:12:15.412056 progress 30% (13MB)
59 22:12:15.423332 progress 35% (15MB)
60 22:12:15.434738 progress 40% (17MB)
61 22:12:15.446092 progress 45% (19MB)
62 22:12:15.457515 progress 50% (21MB)
63 22:12:15.468785 progress 55% (24MB)
64 22:12:15.480306 progress 60% (26MB)
65 22:12:15.491472 progress 65% (28MB)
66 22:12:15.502576 progress 70% (30MB)
67 22:12:15.513710 progress 75% (32MB)
68 22:12:15.524716 progress 80% (34MB)
69 22:12:15.535973 progress 85% (37MB)
70 22:12:15.547129 progress 90% (39MB)
71 22:12:15.558225 progress 95% (41MB)
72 22:12:15.569455 progress 100% (43MB)
73 22:12:15.569575 43MB downloaded in 0.23s (192.59MB/s)
74 22:12:15.569720 end: 1.2.1 http-download (duration 00:00:00) [common]
76 22:12:15.569955 end: 1.2 download-retry (duration 00:00:00) [common]
77 22:12:15.570038 start: 1.3 download-retry (timeout 00:09:57) [common]
78 22:12:15.570120 start: 1.3.1 http-download (timeout 00:09:57) [common]
79 22:12:15.570251 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1281-g84d5372e0f314/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 22:12:15.570319 saving as /var/lib/lava/dispatcher/tmp/10583893/tftp-deploy-arhndd4y/dtb/mt8192-asurada-spherion-r0.dtb
81 22:12:15.570378 total size: 46924 (0MB)
82 22:12:15.570436 No compression specified
83 22:12:15.571559 progress 69% (0MB)
84 22:12:15.571851 progress 100% (0MB)
85 22:12:15.572013 0MB downloaded in 0.00s (27.43MB/s)
86 22:12:15.572128 end: 1.3.1 http-download (duration 00:00:00) [common]
88 22:12:15.572342 end: 1.3 download-retry (duration 00:00:00) [common]
89 22:12:15.572422 start: 1.4 download-retry (timeout 00:09:57) [common]
90 22:12:15.572501 start: 1.4.1 http-download (timeout 00:09:57) [common]
91 22:12:15.572604 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1281-g84d5372e0f314/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 22:12:15.572670 saving as /var/lib/lava/dispatcher/tmp/10583893/tftp-deploy-arhndd4y/modules/modules.tar
93 22:12:15.572730 total size: 8541948 (8MB)
94 22:12:15.572787 Using unxz to decompress xz
95 22:12:15.576340 progress 0% (0MB)
96 22:12:15.597472 progress 5% (0MB)
97 22:12:15.621935 progress 10% (0MB)
98 22:12:15.646807 progress 15% (1MB)
99 22:12:15.671547 progress 20% (1MB)
100 22:12:15.694556 progress 25% (2MB)
101 22:12:15.720490 progress 30% (2MB)
102 22:12:15.744612 progress 35% (2MB)
103 22:12:15.768461 progress 40% (3MB)
104 22:12:15.792397 progress 45% (3MB)
105 22:12:15.816714 progress 50% (4MB)
106 22:12:15.839667 progress 55% (4MB)
107 22:12:15.863758 progress 60% (4MB)
108 22:12:15.888981 progress 65% (5MB)
109 22:12:15.913414 progress 70% (5MB)
110 22:12:15.936509 progress 75% (6MB)
111 22:12:15.960194 progress 80% (6MB)
112 22:12:15.985029 progress 85% (6MB)
113 22:12:16.013816 progress 90% (7MB)
114 22:12:16.038707 progress 95% (7MB)
115 22:12:16.063297 progress 100% (8MB)
116 22:12:16.069043 8MB downloaded in 0.50s (16.41MB/s)
117 22:12:16.069338 end: 1.4.1 http-download (duration 00:00:00) [common]
119 22:12:16.069600 end: 1.4 download-retry (duration 00:00:00) [common]
120 22:12:16.069692 start: 1.5 prepare-tftp-overlay (timeout 00:09:56) [common]
121 22:12:16.069787 start: 1.5.1 extract-nfsrootfs (timeout 00:09:56) [common]
122 22:12:16.069868 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 22:12:16.069955 start: 1.5.2 lava-overlay (timeout 00:09:56) [common]
124 22:12:16.070172 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10583893/lava-overlay-7ivqnwq6
125 22:12:16.070299 makedir: /var/lib/lava/dispatcher/tmp/10583893/lava-overlay-7ivqnwq6/lava-10583893/bin
126 22:12:16.070400 makedir: /var/lib/lava/dispatcher/tmp/10583893/lava-overlay-7ivqnwq6/lava-10583893/tests
127 22:12:16.070493 makedir: /var/lib/lava/dispatcher/tmp/10583893/lava-overlay-7ivqnwq6/lava-10583893/results
128 22:12:16.070606 Creating /var/lib/lava/dispatcher/tmp/10583893/lava-overlay-7ivqnwq6/lava-10583893/bin/lava-add-keys
129 22:12:16.070758 Creating /var/lib/lava/dispatcher/tmp/10583893/lava-overlay-7ivqnwq6/lava-10583893/bin/lava-add-sources
130 22:12:16.070885 Creating /var/lib/lava/dispatcher/tmp/10583893/lava-overlay-7ivqnwq6/lava-10583893/bin/lava-background-process-start
131 22:12:16.071008 Creating /var/lib/lava/dispatcher/tmp/10583893/lava-overlay-7ivqnwq6/lava-10583893/bin/lava-background-process-stop
132 22:12:16.071127 Creating /var/lib/lava/dispatcher/tmp/10583893/lava-overlay-7ivqnwq6/lava-10583893/bin/lava-common-functions
133 22:12:16.071284 Creating /var/lib/lava/dispatcher/tmp/10583893/lava-overlay-7ivqnwq6/lava-10583893/bin/lava-echo-ipv4
134 22:12:16.071405 Creating /var/lib/lava/dispatcher/tmp/10583893/lava-overlay-7ivqnwq6/lava-10583893/bin/lava-install-packages
135 22:12:16.071524 Creating /var/lib/lava/dispatcher/tmp/10583893/lava-overlay-7ivqnwq6/lava-10583893/bin/lava-installed-packages
136 22:12:16.071641 Creating /var/lib/lava/dispatcher/tmp/10583893/lava-overlay-7ivqnwq6/lava-10583893/bin/lava-os-build
137 22:12:16.071759 Creating /var/lib/lava/dispatcher/tmp/10583893/lava-overlay-7ivqnwq6/lava-10583893/bin/lava-probe-channel
138 22:12:16.071879 Creating /var/lib/lava/dispatcher/tmp/10583893/lava-overlay-7ivqnwq6/lava-10583893/bin/lava-probe-ip
139 22:12:16.071997 Creating /var/lib/lava/dispatcher/tmp/10583893/lava-overlay-7ivqnwq6/lava-10583893/bin/lava-target-ip
140 22:12:16.072115 Creating /var/lib/lava/dispatcher/tmp/10583893/lava-overlay-7ivqnwq6/lava-10583893/bin/lava-target-mac
141 22:12:16.072233 Creating /var/lib/lava/dispatcher/tmp/10583893/lava-overlay-7ivqnwq6/lava-10583893/bin/lava-target-storage
142 22:12:16.072354 Creating /var/lib/lava/dispatcher/tmp/10583893/lava-overlay-7ivqnwq6/lava-10583893/bin/lava-test-case
143 22:12:16.072473 Creating /var/lib/lava/dispatcher/tmp/10583893/lava-overlay-7ivqnwq6/lava-10583893/bin/lava-test-event
144 22:12:16.072590 Creating /var/lib/lava/dispatcher/tmp/10583893/lava-overlay-7ivqnwq6/lava-10583893/bin/lava-test-feedback
145 22:12:16.072710 Creating /var/lib/lava/dispatcher/tmp/10583893/lava-overlay-7ivqnwq6/lava-10583893/bin/lava-test-raise
146 22:12:16.072831 Creating /var/lib/lava/dispatcher/tmp/10583893/lava-overlay-7ivqnwq6/lava-10583893/bin/lava-test-reference
147 22:12:16.072947 Creating /var/lib/lava/dispatcher/tmp/10583893/lava-overlay-7ivqnwq6/lava-10583893/bin/lava-test-runner
148 22:12:16.073064 Creating /var/lib/lava/dispatcher/tmp/10583893/lava-overlay-7ivqnwq6/lava-10583893/bin/lava-test-set
149 22:12:16.073183 Creating /var/lib/lava/dispatcher/tmp/10583893/lava-overlay-7ivqnwq6/lava-10583893/bin/lava-test-shell
150 22:12:16.073306 Updating /var/lib/lava/dispatcher/tmp/10583893/lava-overlay-7ivqnwq6/lava-10583893/bin/lava-install-packages (oe)
151 22:12:16.073455 Updating /var/lib/lava/dispatcher/tmp/10583893/lava-overlay-7ivqnwq6/lava-10583893/bin/lava-installed-packages (oe)
152 22:12:16.073571 Creating /var/lib/lava/dispatcher/tmp/10583893/lava-overlay-7ivqnwq6/lava-10583893/environment
153 22:12:16.073666 LAVA metadata
154 22:12:16.073741 - LAVA_JOB_ID=10583893
155 22:12:16.073804 - LAVA_DISPATCHER_IP=192.168.201.1
156 22:12:16.073907 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:56) [common]
157 22:12:16.073973 skipped lava-vland-overlay
158 22:12:16.074045 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 22:12:16.074122 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:56) [common]
160 22:12:16.074184 skipped lava-multinode-overlay
161 22:12:16.074254 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 22:12:16.074335 start: 1.5.2.3 test-definition (timeout 00:09:56) [common]
163 22:12:16.074406 Loading test definitions
164 22:12:16.074494 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:56) [common]
165 22:12:16.074566 Using /lava-10583893 at stage 0
166 22:12:16.074910 uuid=10583893_1.5.2.3.1 testdef=None
167 22:12:16.075000 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 22:12:16.075086 start: 1.5.2.3.2 test-overlay (timeout 00:09:56) [common]
169 22:12:16.075656 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 22:12:16.075873 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:56) [common]
172 22:12:16.076535 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 22:12:16.076764 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:56) [common]
175 22:12:16.077365 runner path: /var/lib/lava/dispatcher/tmp/10583893/lava-overlay-7ivqnwq6/lava-10583893/0/tests/0_dmesg test_uuid 10583893_1.5.2.3.1
176 22:12:16.077514 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 22:12:16.077735 start: 1.5.2.3.5 inline-repo-action (timeout 00:09:56) [common]
179 22:12:16.077806 Using /lava-10583893 at stage 1
180 22:12:16.078091 uuid=10583893_1.5.2.3.5 testdef=None
181 22:12:16.078178 end: 1.5.2.3.5 inline-repo-action (duration 00:00:00) [common]
182 22:12:16.078260 start: 1.5.2.3.6 test-overlay (timeout 00:09:56) [common]
183 22:12:16.078713 end: 1.5.2.3.6 test-overlay (duration 00:00:00) [common]
185 22:12:16.078929 start: 1.5.2.3.7 test-install-overlay (timeout 00:09:56) [common]
186 22:12:16.080074 end: 1.5.2.3.7 test-install-overlay (duration 00:00:00) [common]
188 22:12:16.080362 start: 1.5.2.3.8 test-runscript-overlay (timeout 00:09:56) [common]
189 22:12:16.080981 runner path: /var/lib/lava/dispatcher/tmp/10583893/lava-overlay-7ivqnwq6/lava-10583893/1/tests/1_bootrr test_uuid 10583893_1.5.2.3.5
190 22:12:16.081132 end: 1.5.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
192 22:12:16.081338 Creating lava-test-runner.conf files
193 22:12:16.081401 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10583893/lava-overlay-7ivqnwq6/lava-10583893/0 for stage 0
194 22:12:16.081488 - 0_dmesg
195 22:12:16.081567 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10583893/lava-overlay-7ivqnwq6/lava-10583893/1 for stage 1
196 22:12:16.081656 - 1_bootrr
197 22:12:16.081748 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
198 22:12:16.081829 start: 1.5.2.4 compress-overlay (timeout 00:09:56) [common]
199 22:12:16.089617 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
200 22:12:16.089728 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:56) [common]
201 22:12:16.089813 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
202 22:12:16.089895 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
203 22:12:16.089977 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:56) [common]
204 22:12:16.324556 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
205 22:12:16.324918 start: 1.5.4 extract-modules (timeout 00:09:56) [common]
206 22:12:16.325030 extracting modules file /var/lib/lava/dispatcher/tmp/10583893/tftp-deploy-arhndd4y/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10583893/extract-overlay-ramdisk-07q5s12p/ramdisk
207 22:12:16.521371 end: 1.5.4 extract-modules (duration 00:00:00) [common]
208 22:12:16.521535 start: 1.5.5 apply-overlay-tftp (timeout 00:09:56) [common]
209 22:12:16.521634 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10583893/compress-overlay-386r8it6/overlay-1.5.2.4.tar.gz to ramdisk
210 22:12:16.521708 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10583893/compress-overlay-386r8it6/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10583893/extract-overlay-ramdisk-07q5s12p/ramdisk
211 22:12:16.529680 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
212 22:12:16.529797 start: 1.5.6 configure-preseed-file (timeout 00:09:56) [common]
213 22:12:16.529892 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
214 22:12:16.529982 start: 1.5.7 compress-ramdisk (timeout 00:09:56) [common]
215 22:12:16.530061 Building ramdisk /var/lib/lava/dispatcher/tmp/10583893/extract-overlay-ramdisk-07q5s12p/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10583893/extract-overlay-ramdisk-07q5s12p/ramdisk
216 22:12:16.902461 >> 143711 blocks
217 22:12:19.154664 rename /var/lib/lava/dispatcher/tmp/10583893/extract-overlay-ramdisk-07q5s12p/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10583893/tftp-deploy-arhndd4y/ramdisk/ramdisk.cpio.gz
218 22:12:19.155098 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
219 22:12:19.155228 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
220 22:12:19.155328 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
221 22:12:19.155430 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10583893/tftp-deploy-arhndd4y/kernel/Image'
222 22:12:30.872321 Returned 0 in 11 seconds
223 22:12:30.972937 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10583893/tftp-deploy-arhndd4y/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10583893/tftp-deploy-arhndd4y/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10583893/tftp-deploy-arhndd4y/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10583893/tftp-deploy-arhndd4y/kernel/image.itb
224 22:12:31.347357 output: FIT description: Kernel Image image with one or more FDT blobs
225 22:12:31.347714 output: Created: Sun Jun 4 23:12:31 2023
226 22:12:31.347791 output: Image 0 (kernel-1)
227 22:12:31.347856 output: Description:
228 22:12:31.347921 output: Created: Sun Jun 4 23:12:31 2023
229 22:12:31.347984 output: Type: Kernel Image
230 22:12:31.348044 output: Compression: lzma compressed
231 22:12:31.348104 output: Data Size: 10081729 Bytes = 9845.44 KiB = 9.61 MiB
232 22:12:31.348163 output: Architecture: AArch64
233 22:12:31.348222 output: OS: Linux
234 22:12:31.348279 output: Load Address: 0x00000000
235 22:12:31.348334 output: Entry Point: 0x00000000
236 22:12:31.348391 output: Hash algo: crc32
237 22:12:31.348447 output: Hash value: 3b3111d8
238 22:12:31.348500 output: Image 1 (fdt-1)
239 22:12:31.348553 output: Description: mt8192-asurada-spherion-r0
240 22:12:31.348606 output: Created: Sun Jun 4 23:12:31 2023
241 22:12:31.348659 output: Type: Flat Device Tree
242 22:12:31.348712 output: Compression: uncompressed
243 22:12:31.348765 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
244 22:12:31.348818 output: Architecture: AArch64
245 22:12:31.348871 output: Hash algo: crc32
246 22:12:31.348923 output: Hash value: 1df858fa
247 22:12:31.348976 output: Image 2 (ramdisk-1)
248 22:12:31.349028 output: Description: unavailable
249 22:12:31.349080 output: Created: Sun Jun 4 23:12:31 2023
250 22:12:31.349132 output: Type: RAMDisk Image
251 22:12:31.349185 output: Compression: Unknown Compression
252 22:12:31.349237 output: Data Size: 21230232 Bytes = 20732.65 KiB = 20.25 MiB
253 22:12:31.349289 output: Architecture: AArch64
254 22:12:31.349341 output: OS: Linux
255 22:12:31.349393 output: Load Address: unavailable
256 22:12:31.349446 output: Entry Point: unavailable
257 22:12:31.349498 output: Hash algo: crc32
258 22:12:31.349550 output: Hash value: 0625d937
259 22:12:31.349602 output: Default Configuration: 'conf-1'
260 22:12:31.349654 output: Configuration 0 (conf-1)
261 22:12:31.349706 output: Description: mt8192-asurada-spherion-r0
262 22:12:31.349758 output: Kernel: kernel-1
263 22:12:31.349811 output: Init Ramdisk: ramdisk-1
264 22:12:31.349863 output: FDT: fdt-1
265 22:12:31.349915 output: Loadables: kernel-1
266 22:12:31.349967 output:
267 22:12:31.350152 end: 1.5.8.1 prepare-fit (duration 00:00:12) [common]
268 22:12:31.350253 end: 1.5.8 prepare-kernel (duration 00:00:12) [common]
269 22:12:31.350359 end: 1.5 prepare-tftp-overlay (duration 00:00:15) [common]
270 22:12:31.350448 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:41) [common]
271 22:12:31.350525 No LXC device requested
272 22:12:31.350603 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
273 22:12:31.350689 start: 1.7 deploy-device-env (timeout 00:09:41) [common]
274 22:12:31.350763 end: 1.7 deploy-device-env (duration 00:00:00) [common]
275 22:12:31.350833 Checking files for TFTP limit of 4294967296 bytes.
276 22:12:31.351330 end: 1 tftp-deploy (duration 00:00:19) [common]
277 22:12:31.351436 start: 2 depthcharge-action (timeout 00:05:00) [common]
278 22:12:31.351525 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
279 22:12:31.351647 substitutions:
280 22:12:31.351714 - {DTB}: 10583893/tftp-deploy-arhndd4y/dtb/mt8192-asurada-spherion-r0.dtb
281 22:12:31.351776 - {INITRD}: 10583893/tftp-deploy-arhndd4y/ramdisk/ramdisk.cpio.gz
282 22:12:31.351834 - {KERNEL}: 10583893/tftp-deploy-arhndd4y/kernel/Image
283 22:12:31.351902 - {LAVA_MAC}: None
284 22:12:31.351960 - {PRESEED_CONFIG}: None
285 22:12:31.352016 - {PRESEED_LOCAL}: None
286 22:12:31.352071 - {RAMDISK}: 10583893/tftp-deploy-arhndd4y/ramdisk/ramdisk.cpio.gz
287 22:12:31.352127 - {ROOT_PART}: None
288 22:12:31.352182 - {ROOT}: None
289 22:12:31.352237 - {SERVER_IP}: 192.168.201.1
290 22:12:31.352291 - {TEE}: None
291 22:12:31.352345 Parsed boot commands:
292 22:12:31.352399 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
293 22:12:31.352571 Parsed boot commands: tftpboot 192.168.201.1 10583893/tftp-deploy-arhndd4y/kernel/image.itb 10583893/tftp-deploy-arhndd4y/kernel/cmdline
294 22:12:31.352660 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
295 22:12:31.352752 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
296 22:12:31.352843 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
297 22:12:31.352925 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
298 22:12:31.352995 Not connected, no need to disconnect.
299 22:12:31.353070 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
300 22:12:31.353150 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
301 22:12:31.353216 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-2'
302 22:12:31.357096 Setting prompt string to ['lava-test: # ']
303 22:12:31.357646 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
304 22:12:31.357754 end: 2.2.1 reset-connection (duration 00:00:00) [common]
305 22:12:31.357850 start: 2.2.2 reset-device (timeout 00:05:00) [common]
306 22:12:31.357976 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
307 22:12:31.358162 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
308 22:12:36.502735 >> Command sent successfully.
309 22:12:36.513092 Returned 0 in 5 seconds
310 22:12:36.614308 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
312 22:12:36.616010 end: 2.2.2 reset-device (duration 00:00:05) [common]
313 22:12:36.616520 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
314 22:12:36.616973 Setting prompt string to 'Starting depthcharge on Spherion...'
315 22:12:36.617340 Changing prompt to 'Starting depthcharge on Spherion...'
316 22:12:36.617696 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
317 22:12:36.619297 [Enter `^Ec?' for help]
318 22:12:36.782059
319 22:12:36.782615
320 22:12:36.782961 F0: 102B 0000
321 22:12:36.783318
322 22:12:36.783630 F3: 1001 0000 [0200]
323 22:12:36.783936
324 22:12:36.785393 F3: 1001 0000
325 22:12:36.785824
326 22:12:36.786162 F7: 102D 0000
327 22:12:36.786479
328 22:12:36.788631 F1: 0000 0000
329 22:12:36.789175
330 22:12:36.789523 V0: 0000 0000 [0001]
331 22:12:36.789847
332 22:12:36.792148 00: 0007 8000
333 22:12:36.792605
334 22:12:36.792950 01: 0000 0000
335 22:12:36.793274
336 22:12:36.794774 BP: 0C00 0209 [0000]
337 22:12:36.795297
338 22:12:36.795652 G0: 1182 0000
339 22:12:36.796018
340 22:12:36.796335 EC: 0000 0021 [4000]
341 22:12:36.798672
342 22:12:36.799096 S7: 0000 0000 [0000]
343 22:12:36.799495
344 22:12:36.801532 CC: 0000 0000 [0001]
345 22:12:36.801962
346 22:12:36.802305 T0: 0000 0040 [010F]
347 22:12:36.802626
348 22:12:36.802932 Jump to BL
349 22:12:36.803280
350 22:12:36.828661
351 22:12:36.829177
352 22:12:36.829517
353 22:12:36.835686 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
354 22:12:36.838745 ARM64: Exception handlers installed.
355 22:12:36.842809 ARM64: Testing exception
356 22:12:36.845602 ARM64: Done test exception
357 22:12:36.852304 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
358 22:12:36.862807 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
359 22:12:36.869956 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
360 22:12:36.879613 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
361 22:12:36.886185 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
362 22:12:36.896011 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
363 22:12:36.906871 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
364 22:12:36.913183 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
365 22:12:36.931086 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
366 22:12:36.934483 WDT: Last reset was cold boot
367 22:12:36.937531 SPI1(PAD0) initialized at 2873684 Hz
368 22:12:36.941095 SPI5(PAD0) initialized at 992727 Hz
369 22:12:36.944470 VBOOT: Loading verstage.
370 22:12:36.951700 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
371 22:12:36.954570 FMAP: Found "FLASH" version 1.1 at 0x20000.
372 22:12:36.958036 FMAP: base = 0x0 size = 0x800000 #areas = 25
373 22:12:36.960988 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
374 22:12:36.968708 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
375 22:12:36.975510 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
376 22:12:36.986172 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
377 22:12:36.986701
378 22:12:36.987038
379 22:12:36.996213 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
380 22:12:36.999375 ARM64: Exception handlers installed.
381 22:12:37.003322 ARM64: Testing exception
382 22:12:37.003863 ARM64: Done test exception
383 22:12:37.010066 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
384 22:12:37.013337 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
385 22:12:37.027651 Probing TPM: . done!
386 22:12:37.028208 TPM ready after 0 ms
387 22:12:37.034537 Connected to device vid:did:rid of 1ae0:0028:00
388 22:12:37.041514 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
389 22:12:37.099845 Initialized TPM device CR50 revision 0
390 22:12:37.111355 tlcl_send_startup: Startup return code is 0
391 22:12:37.111903 TPM: setup succeeded
392 22:12:37.122997 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
393 22:12:37.132095 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
394 22:12:37.143977 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
395 22:12:37.153463 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
396 22:12:37.157297 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
397 22:12:37.161724 in-header: 03 07 00 00 08 00 00 00
398 22:12:37.165496 in-data: aa e4 47 04 13 02 00 00
399 22:12:37.169273 Chrome EC: UHEPI supported
400 22:12:37.176360 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
401 22:12:37.180272 in-header: 03 95 00 00 08 00 00 00
402 22:12:37.180799 in-data: 18 20 20 08 00 00 00 00
403 22:12:37.183774 Phase 1
404 22:12:37.187913 FMAP: area GBB found @ 3f5000 (12032 bytes)
405 22:12:37.191734 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
406 22:12:37.199524 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
407 22:12:37.202989 Recovery requested (1009000e)
408 22:12:37.210425 TPM: Extending digest for VBOOT: boot mode into PCR 0
409 22:12:37.215683 tlcl_extend: response is 0
410 22:12:37.225498 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
411 22:12:37.230908 tlcl_extend: response is 0
412 22:12:37.237639 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
413 22:12:37.257619 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
414 22:12:37.264567 BS: bootblock times (exec / console): total (unknown) / 148 ms
415 22:12:37.265234
416 22:12:37.265594
417 22:12:37.274691 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
418 22:12:37.278017 ARM64: Exception handlers installed.
419 22:12:37.281185 ARM64: Testing exception
420 22:12:37.281614 ARM64: Done test exception
421 22:12:37.303341 pmic_efuse_setting: Set efuses in 11 msecs
422 22:12:37.306200 pmwrap_interface_init: Select PMIF_VLD_RDY
423 22:12:37.313175 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
424 22:12:37.316458 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
425 22:12:37.323866 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
426 22:12:37.327129 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
427 22:12:37.331026 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
428 22:12:37.338309 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
429 22:12:37.342754 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
430 22:12:37.345989 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
431 22:12:37.349324 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
432 22:12:37.356189 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
433 22:12:37.361001 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
434 22:12:37.363717 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
435 22:12:37.367323 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
436 22:12:37.375313 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
437 22:12:37.382045 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
438 22:12:37.386095 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
439 22:12:37.392700 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
440 22:12:37.396706 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
441 22:12:37.403743 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
442 22:12:37.411272 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
443 22:12:37.414831 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
444 22:12:37.422006 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
445 22:12:37.426082 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
446 22:12:37.433131 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
447 22:12:37.436697 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
448 22:12:37.443843 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
449 22:12:37.447961 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
450 22:12:37.451577 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
451 22:12:37.458185 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
452 22:12:37.462100 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
453 22:12:37.465145 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
454 22:12:37.473230 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
455 22:12:37.476199 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
456 22:12:37.483636 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
457 22:12:37.487223 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
458 22:12:37.491014 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
459 22:12:37.498323 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
460 22:12:37.502000 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
461 22:12:37.505195 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
462 22:12:37.509499 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
463 22:12:37.516347 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
464 22:12:37.519703 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
465 22:12:37.523233 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
466 22:12:37.527904 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
467 22:12:37.531664 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
468 22:12:37.539235 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
469 22:12:37.542498 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
470 22:12:37.546032 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
471 22:12:37.549869 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
472 22:12:37.553848 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
473 22:12:37.557356 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
474 22:12:37.564593 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
475 22:12:37.575546 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
476 22:12:37.579797 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
477 22:12:37.586860 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
478 22:12:37.594132 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
479 22:12:37.601966 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
480 22:12:37.605253 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
481 22:12:37.608645 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
482 22:12:37.616051 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x0
483 22:12:37.619817 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
484 22:12:37.628693 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
485 22:12:37.631400 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
486 22:12:37.640531 [RTC]rtc_get_frequency_meter,154: input=15, output=853
487 22:12:37.650588 [RTC]rtc_get_frequency_meter,154: input=7, output=724
488 22:12:37.659338 [RTC]rtc_get_frequency_meter,154: input=11, output=789
489 22:12:37.668740 [RTC]rtc_get_frequency_meter,154: input=13, output=820
490 22:12:37.678287 [RTC]rtc_get_frequency_meter,154: input=12, output=805
491 22:12:37.688461 [RTC]rtc_get_frequency_meter,154: input=11, output=789
492 22:12:37.698376 [RTC]rtc_get_frequency_meter,154: input=12, output=804
493 22:12:37.701693 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
494 22:12:37.705661 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
495 22:12:37.713208 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
496 22:12:37.716647 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
497 22:12:37.720311 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
498 22:12:37.724442 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
499 22:12:37.728493 ADC[4]: Raw value=904064 ID=7
500 22:12:37.728920 ADC[3]: Raw value=213546 ID=1
501 22:12:37.731604 RAM Code: 0x71
502 22:12:37.735050 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
503 22:12:37.738832 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
504 22:12:37.750712 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
505 22:12:37.757251 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
506 22:12:37.757771 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
507 22:12:37.761179 in-header: 03 07 00 00 08 00 00 00
508 22:12:37.765019 in-data: aa e4 47 04 13 02 00 00
509 22:12:37.768998 Chrome EC: UHEPI supported
510 22:12:37.775921 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
511 22:12:37.779425 in-header: 03 95 00 00 08 00 00 00
512 22:12:37.779952 in-data: 18 20 20 08 00 00 00 00
513 22:12:37.783276 MRC: failed to locate region type 0.
514 22:12:37.790179 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
515 22:12:37.793997 DRAM-K: Running full calibration
516 22:12:37.801187 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
517 22:12:37.801617 header.status = 0x0
518 22:12:37.805250 header.version = 0x6 (expected: 0x6)
519 22:12:37.808727 header.size = 0xd00 (expected: 0xd00)
520 22:12:37.809161 header.flags = 0x0
521 22:12:37.815873 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
522 22:12:37.834982 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
523 22:12:37.842020 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
524 22:12:37.846158 dram_init: ddr_geometry: 2
525 22:12:37.846587 [EMI] MDL number = 2
526 22:12:37.849970 [EMI] Get MDL freq = 0
527 22:12:37.850498 dram_init: ddr_type: 0
528 22:12:37.854203 is_discrete_lpddr4: 1
529 22:12:37.856614 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
530 22:12:37.857048
531 22:12:37.857388
532 22:12:37.857705 [Bian_co] ETT version 0.0.0.1
533 22:12:37.864781 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
534 22:12:37.865304
535 22:12:37.867750 dramc_set_vcore_voltage set vcore to 650000
536 22:12:37.868259 Read voltage for 800, 4
537 22:12:37.871760 Vio18 = 0
538 22:12:37.872298 Vcore = 650000
539 22:12:37.872659 Vdram = 0
540 22:12:37.872981 Vddq = 0
541 22:12:37.876119 Vmddr = 0
542 22:12:37.876741 dram_init: config_dvfs: 1
543 22:12:37.883088 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
544 22:12:37.887002 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
545 22:12:37.889723 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
546 22:12:37.892837 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
547 22:12:37.899878 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
548 22:12:37.903570 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
549 22:12:37.904091 MEM_TYPE=3, freq_sel=18
550 22:12:37.907392 sv_algorithm_assistance_LP4_1600
551 22:12:37.911086 ============ PULL DRAM RESETB DOWN ============
552 22:12:37.914754 ========== PULL DRAM RESETB DOWN end =========
553 22:12:37.921824 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
554 22:12:37.925275 ===================================
555 22:12:37.925702 LPDDR4 DRAM CONFIGURATION
556 22:12:37.928388 ===================================
557 22:12:37.931659 EX_ROW_EN[0] = 0x0
558 22:12:37.932085 EX_ROW_EN[1] = 0x0
559 22:12:37.935075 LP4Y_EN = 0x0
560 22:12:37.935570 WORK_FSP = 0x0
561 22:12:37.938663 WL = 0x2
562 22:12:37.939251 RL = 0x2
563 22:12:37.941536 BL = 0x2
564 22:12:37.945504 RPST = 0x0
565 22:12:37.946029 RD_PRE = 0x0
566 22:12:37.949145 WR_PRE = 0x1
567 22:12:37.949664 WR_PST = 0x0
568 22:12:37.952022 DBI_WR = 0x0
569 22:12:37.952543 DBI_RD = 0x0
570 22:12:37.955060 OTF = 0x1
571 22:12:37.958633 ===================================
572 22:12:37.961557 ===================================
573 22:12:37.962084 ANA top config
574 22:12:37.964963 ===================================
575 22:12:37.968685 DLL_ASYNC_EN = 0
576 22:12:37.971534 ALL_SLAVE_EN = 1
577 22:12:37.972054 NEW_RANK_MODE = 1
578 22:12:37.974895 DLL_IDLE_MODE = 1
579 22:12:37.978353 LP45_APHY_COMB_EN = 1
580 22:12:37.981744 TX_ODT_DIS = 1
581 22:12:37.982265 NEW_8X_MODE = 1
582 22:12:37.984860 ===================================
583 22:12:37.988378 ===================================
584 22:12:37.991968 data_rate = 1600
585 22:12:37.994984 CKR = 1
586 22:12:37.997813 DQ_P2S_RATIO = 8
587 22:12:38.001923 ===================================
588 22:12:38.004681 CA_P2S_RATIO = 8
589 22:12:38.008397 DQ_CA_OPEN = 0
590 22:12:38.008822 DQ_SEMI_OPEN = 0
591 22:12:38.012328 CA_SEMI_OPEN = 0
592 22:12:38.015358 CA_FULL_RATE = 0
593 22:12:38.018585 DQ_CKDIV4_EN = 1
594 22:12:38.022306 CA_CKDIV4_EN = 1
595 22:12:38.022729 CA_PREDIV_EN = 0
596 22:12:38.025288 PH8_DLY = 0
597 22:12:38.029053 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
598 22:12:38.031844 DQ_AAMCK_DIV = 4
599 22:12:38.035541 CA_AAMCK_DIV = 4
600 22:12:38.038817 CA_ADMCK_DIV = 4
601 22:12:38.039397 DQ_TRACK_CA_EN = 0
602 22:12:38.041791 CA_PICK = 800
603 22:12:38.045621 CA_MCKIO = 800
604 22:12:38.049273 MCKIO_SEMI = 0
605 22:12:38.052600 PLL_FREQ = 3068
606 22:12:38.055986 DQ_UI_PI_RATIO = 32
607 22:12:38.056561 CA_UI_PI_RATIO = 0
608 22:12:38.060299 ===================================
609 22:12:38.063768 ===================================
610 22:12:38.067472 memory_type:LPDDR4
611 22:12:38.067995 GP_NUM : 10
612 22:12:38.071067 SRAM_EN : 1
613 22:12:38.071628 MD32_EN : 0
614 22:12:38.075070 ===================================
615 22:12:38.078730 [ANA_INIT] >>>>>>>>>>>>>>
616 22:12:38.082408 <<<<<< [CONFIGURE PHASE]: ANA_TX
617 22:12:38.086158 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
618 22:12:38.089245 ===================================
619 22:12:38.089768 data_rate = 1600,PCW = 0X7600
620 22:12:38.092127 ===================================
621 22:12:38.095714 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
622 22:12:38.102226 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
623 22:12:38.109405 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
624 22:12:38.112352 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
625 22:12:38.115669 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
626 22:12:38.119595 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
627 22:12:38.122559 [ANA_INIT] flow start
628 22:12:38.123213 [ANA_INIT] PLL >>>>>>>>
629 22:12:38.125522 [ANA_INIT] PLL <<<<<<<<
630 22:12:38.129150 [ANA_INIT] MIDPI >>>>>>>>
631 22:12:38.132367 [ANA_INIT] MIDPI <<<<<<<<
632 22:12:38.132892 [ANA_INIT] DLL >>>>>>>>
633 22:12:38.135740 [ANA_INIT] flow end
634 22:12:38.139393 ============ LP4 DIFF to SE enter ============
635 22:12:38.142368 ============ LP4 DIFF to SE exit ============
636 22:12:38.146062 [ANA_INIT] <<<<<<<<<<<<<
637 22:12:38.149455 [Flow] Enable top DCM control >>>>>
638 22:12:38.152495 [Flow] Enable top DCM control <<<<<
639 22:12:38.155615 Enable DLL master slave shuffle
640 22:12:38.163148 ==============================================================
641 22:12:38.163720 Gating Mode config
642 22:12:38.169023 ==============================================================
643 22:12:38.169543 Config description:
644 22:12:38.179151 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
645 22:12:38.185818 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
646 22:12:38.192180 SELPH_MODE 0: By rank 1: By Phase
647 22:12:38.196182 ==============================================================
648 22:12:38.198756 GAT_TRACK_EN = 1
649 22:12:38.202235 RX_GATING_MODE = 2
650 22:12:38.205827 RX_GATING_TRACK_MODE = 2
651 22:12:38.208697 SELPH_MODE = 1
652 22:12:38.212030 PICG_EARLY_EN = 1
653 22:12:38.215576 VALID_LAT_VALUE = 1
654 22:12:38.218927 ==============================================================
655 22:12:38.222094 Enter into Gating configuration >>>>
656 22:12:38.225017 Exit from Gating configuration <<<<
657 22:12:38.228391 Enter into DVFS_PRE_config >>>>>
658 22:12:38.242374 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
659 22:12:38.245267 Exit from DVFS_PRE_config <<<<<
660 22:12:38.248782 Enter into PICG configuration >>>>
661 22:12:38.251714 Exit from PICG configuration <<<<
662 22:12:38.252186 [RX_INPUT] configuration >>>>>
663 22:12:38.255076 [RX_INPUT] configuration <<<<<
664 22:12:38.261874 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
665 22:12:38.265620 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
666 22:12:38.272193 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
667 22:12:38.278818 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
668 22:12:38.285605 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
669 22:12:38.291796 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
670 22:12:38.296173 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
671 22:12:38.298377 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
672 22:12:38.302246 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
673 22:12:38.309058 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
674 22:12:38.312316 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
675 22:12:38.315601 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
676 22:12:38.318482 ===================================
677 22:12:38.321725 LPDDR4 DRAM CONFIGURATION
678 22:12:38.325974 ===================================
679 22:12:38.328679 EX_ROW_EN[0] = 0x0
680 22:12:38.329128 EX_ROW_EN[1] = 0x0
681 22:12:38.331792 LP4Y_EN = 0x0
682 22:12:38.332261 WORK_FSP = 0x0
683 22:12:38.334757 WL = 0x2
684 22:12:38.335224 RL = 0x2
685 22:12:38.338561 BL = 0x2
686 22:12:38.339064 RPST = 0x0
687 22:12:38.341717 RD_PRE = 0x0
688 22:12:38.342144 WR_PRE = 0x1
689 22:12:38.345205 WR_PST = 0x0
690 22:12:38.345630 DBI_WR = 0x0
691 22:12:38.348187 DBI_RD = 0x0
692 22:12:38.348612 OTF = 0x1
693 22:12:38.352212 ===================================
694 22:12:38.358076 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
695 22:12:38.361363 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
696 22:12:38.365286 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 22:12:38.368015 ===================================
698 22:12:38.371666 LPDDR4 DRAM CONFIGURATION
699 22:12:38.375338 ===================================
700 22:12:38.375856 EX_ROW_EN[0] = 0x10
701 22:12:38.378395 EX_ROW_EN[1] = 0x0
702 22:12:38.381942 LP4Y_EN = 0x0
703 22:12:38.382469 WORK_FSP = 0x0
704 22:12:38.384857 WL = 0x2
705 22:12:38.385282 RL = 0x2
706 22:12:38.388507 BL = 0x2
707 22:12:38.389031 RPST = 0x0
708 22:12:38.391448 RD_PRE = 0x0
709 22:12:38.391985 WR_PRE = 0x1
710 22:12:38.395167 WR_PST = 0x0
711 22:12:38.395729 DBI_WR = 0x0
712 22:12:38.398407 DBI_RD = 0x0
713 22:12:38.398832 OTF = 0x1
714 22:12:38.401641 ===================================
715 22:12:38.408176 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
716 22:12:38.412718 nWR fixed to 40
717 22:12:38.415930 [ModeRegInit_LP4] CH0 RK0
718 22:12:38.416453 [ModeRegInit_LP4] CH0 RK1
719 22:12:38.419033 [ModeRegInit_LP4] CH1 RK0
720 22:12:38.422621 [ModeRegInit_LP4] CH1 RK1
721 22:12:38.423140 match AC timing 13
722 22:12:38.429202 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
723 22:12:38.432833 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
724 22:12:38.435982 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
725 22:12:38.442301 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
726 22:12:38.446202 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
727 22:12:38.446727 [EMI DOE] emi_dcm 0
728 22:12:38.452652 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
729 22:12:38.453076 ==
730 22:12:38.456144 Dram Type= 6, Freq= 0, CH_0, rank 0
731 22:12:38.458966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
732 22:12:38.459517 ==
733 22:12:38.466363 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
734 22:12:38.472516 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
735 22:12:38.480139 [CA 0] Center 37 (7~68) winsize 62
736 22:12:38.483575 [CA 1] Center 37 (7~68) winsize 62
737 22:12:38.486818 [CA 2] Center 35 (5~65) winsize 61
738 22:12:38.490066 [CA 3] Center 35 (4~66) winsize 63
739 22:12:38.493179 [CA 4] Center 33 (3~64) winsize 62
740 22:12:38.496672 [CA 5] Center 33 (3~64) winsize 62
741 22:12:38.497236
742 22:12:38.499798 [CmdBusTrainingLP45] Vref(ca) range 1: 34
743 22:12:38.500269
744 22:12:38.503000 [CATrainingPosCal] consider 1 rank data
745 22:12:38.506753 u2DelayCellTimex100 = 270/100 ps
746 22:12:38.510336 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
747 22:12:38.513294 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
748 22:12:38.519802 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
749 22:12:38.523435 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
750 22:12:38.526874 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
751 22:12:38.529625 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
752 22:12:38.530095
753 22:12:38.532902 CA PerBit enable=1, Macro0, CA PI delay=33
754 22:12:38.533339
755 22:12:38.536428 [CBTSetCACLKResult] CA Dly = 33
756 22:12:38.536854 CS Dly: 6 (0~37)
757 22:12:38.539753 ==
758 22:12:38.542865 Dram Type= 6, Freq= 0, CH_0, rank 1
759 22:12:38.546348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
760 22:12:38.546867 ==
761 22:12:38.549888 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
762 22:12:38.556141 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
763 22:12:38.566360 [CA 0] Center 38 (7~69) winsize 63
764 22:12:38.570042 [CA 1] Center 37 (7~68) winsize 62
765 22:12:38.573300 [CA 2] Center 35 (4~66) winsize 63
766 22:12:38.576552 [CA 3] Center 34 (4~65) winsize 62
767 22:12:38.579896 [CA 4] Center 34 (3~65) winsize 63
768 22:12:38.583167 [CA 5] Center 33 (3~64) winsize 62
769 22:12:38.583750
770 22:12:38.586283 [CmdBusTrainingLP45] Vref(ca) range 1: 34
771 22:12:38.586848
772 22:12:38.590168 [CATrainingPosCal] consider 2 rank data
773 22:12:38.593171 u2DelayCellTimex100 = 270/100 ps
774 22:12:38.596299 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
775 22:12:38.603719 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
776 22:12:38.606432 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
777 22:12:38.609464 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
778 22:12:38.612794 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
779 22:12:38.616175 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
780 22:12:38.616805
781 22:12:38.619247 CA PerBit enable=1, Macro0, CA PI delay=33
782 22:12:38.619733
783 22:12:38.622872 [CBTSetCACLKResult] CA Dly = 33
784 22:12:38.626671 CS Dly: 6 (0~38)
785 22:12:38.627288
786 22:12:38.629635 ----->DramcWriteLeveling(PI) begin...
787 22:12:38.630207 ==
788 22:12:38.633144 Dram Type= 6, Freq= 0, CH_0, rank 0
789 22:12:38.636386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
790 22:12:38.636857 ==
791 22:12:38.640432 Write leveling (Byte 0): 32 => 32
792 22:12:38.640855 Write leveling (Byte 1): 27 => 27
793 22:12:38.643933 DramcWriteLeveling(PI) end<-----
794 22:12:38.644352
795 22:12:38.644686 ==
796 22:12:38.647976 Dram Type= 6, Freq= 0, CH_0, rank 0
797 22:12:38.654664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
798 22:12:38.655235 ==
799 22:12:38.655596 [Gating] SW mode calibration
800 22:12:38.661454 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
801 22:12:38.668255 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
802 22:12:38.671677 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
803 22:12:38.678601 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
804 22:12:38.681810 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
805 22:12:38.684850 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 22:12:38.687985 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 22:12:38.694642 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 22:12:38.698383 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 22:12:38.701527 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 22:12:38.708411 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 22:12:38.711701 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 22:12:38.715009 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 22:12:38.721589 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 22:12:38.725138 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 22:12:38.727753 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 22:12:38.734752 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 22:12:38.738448 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 22:12:38.741702 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 22:12:38.748178 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
820 22:12:38.751854 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
821 22:12:38.755287 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 22:12:38.761342 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 22:12:38.764466 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 22:12:38.767818 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 22:12:38.774675 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 22:12:38.777659 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 22:12:38.781062 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 22:12:38.787618 0 9 8 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
829 22:12:38.790831 0 9 12 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
830 22:12:38.794647 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
831 22:12:38.801529 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
832 22:12:38.804299 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
833 22:12:38.808201 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
834 22:12:38.814392 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
835 22:12:38.817880 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
836 22:12:38.820869 0 10 8 | B1->B0 | 3434 2a2a | 0 1 | (0 0) (1 0)
837 22:12:38.827394 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
838 22:12:38.830690 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 22:12:38.834191 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 22:12:38.840963 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 22:12:38.843981 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 22:12:38.847570 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 22:12:38.853904 0 11 4 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
844 22:12:38.857163 0 11 8 | B1->B0 | 2424 4343 | 0 0 | (0 0) (0 0)
845 22:12:38.860550 0 11 12 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
846 22:12:38.867169 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
847 22:12:38.870645 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
848 22:12:38.874153 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
849 22:12:38.877712 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 22:12:38.883870 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
851 22:12:38.887151 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
852 22:12:38.890771 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
853 22:12:38.897170 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 22:12:38.900789 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 22:12:38.903674 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 22:12:38.910477 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 22:12:38.913685 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 22:12:38.917335 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
859 22:12:38.924025 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
860 22:12:38.927492 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
861 22:12:38.930534 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
862 22:12:38.937545 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
863 22:12:38.940557 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
864 22:12:38.943824 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
865 22:12:38.950485 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
866 22:12:38.953446 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
867 22:12:38.957696 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
868 22:12:38.963903 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
869 22:12:38.966803 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
870 22:12:38.970232 Total UI for P1: 0, mck2ui 16
871 22:12:38.973471 best dqsien dly found for B0: ( 0, 14, 6)
872 22:12:38.976754 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
873 22:12:38.980157 Total UI for P1: 0, mck2ui 16
874 22:12:38.983269 best dqsien dly found for B1: ( 0, 14, 10)
875 22:12:38.986636 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
876 22:12:38.990411 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
877 22:12:38.990965
878 22:12:38.993356 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
879 22:12:38.999811 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
880 22:12:39.000249 [Gating] SW calibration Done
881 22:12:39.003395 ==
882 22:12:39.003824 Dram Type= 6, Freq= 0, CH_0, rank 0
883 22:12:39.007296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
884 22:12:39.010547 ==
885 22:12:39.011125 RX Vref Scan: 0
886 22:12:39.011520
887 22:12:39.014540 RX Vref 0 -> 0, step: 1
888 22:12:39.015080
889 22:12:39.017209 RX Delay -130 -> 252, step: 16
890 22:12:39.020434 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
891 22:12:39.023701 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
892 22:12:39.027779 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
893 22:12:39.030818 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
894 22:12:39.037556 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
895 22:12:39.041086 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
896 22:12:39.043566 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
897 22:12:39.047136 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
898 22:12:39.050735 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
899 22:12:39.057325 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
900 22:12:39.060484 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
901 22:12:39.063752 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
902 22:12:39.067306 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
903 22:12:39.074367 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
904 22:12:39.076910 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
905 22:12:39.080275 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
906 22:12:39.080855 ==
907 22:12:39.083745 Dram Type= 6, Freq= 0, CH_0, rank 0
908 22:12:39.087298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
909 22:12:39.087776 ==
910 22:12:39.090464 DQS Delay:
911 22:12:39.091043 DQS0 = 0, DQS1 = 0
912 22:12:39.091491 DQM Delay:
913 22:12:39.094111 DQM0 = 87, DQM1 = 75
914 22:12:39.094537 DQ Delay:
915 22:12:39.097291 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
916 22:12:39.100411 DQ4 =93, DQ5 =69, DQ6 =101, DQ7 =93
917 22:12:39.104080 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
918 22:12:39.107279 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
919 22:12:39.107835
920 22:12:39.108184
921 22:12:39.108501 ==
922 22:12:39.110209 Dram Type= 6, Freq= 0, CH_0, rank 0
923 22:12:39.117216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
924 22:12:39.117779 ==
925 22:12:39.118129
926 22:12:39.118447
927 22:12:39.118753 TX Vref Scan disable
928 22:12:39.120992 == TX Byte 0 ==
929 22:12:39.124639 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
930 22:12:39.130600 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
931 22:12:39.131030 == TX Byte 1 ==
932 22:12:39.134612 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
933 22:12:39.141030 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
934 22:12:39.141565 ==
935 22:12:39.144505 Dram Type= 6, Freq= 0, CH_0, rank 0
936 22:12:39.147586 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
937 22:12:39.148124 ==
938 22:12:39.160368 TX Vref=22, minBit 1, minWin=27, winSum=440
939 22:12:39.163918 TX Vref=24, minBit 1, minWin=27, winSum=444
940 22:12:39.167167 TX Vref=26, minBit 1, minWin=27, winSum=445
941 22:12:39.170533 TX Vref=28, minBit 1, minWin=27, winSum=447
942 22:12:39.174545 TX Vref=30, minBit 1, minWin=27, winSum=448
943 22:12:39.177112 TX Vref=32, minBit 1, minWin=27, winSum=447
944 22:12:39.184909 [TxChooseVref] Worse bit 1, Min win 27, Win sum 448, Final Vref 30
945 22:12:39.185481
946 22:12:39.187294 Final TX Range 1 Vref 30
947 22:12:39.187760
948 22:12:39.188133 ==
949 22:12:39.190952 Dram Type= 6, Freq= 0, CH_0, rank 0
950 22:12:39.194721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
951 22:12:39.195342 ==
952 22:12:39.195727
953 22:12:39.196076
954 22:12:39.197364 TX Vref Scan disable
955 22:12:39.200598 == TX Byte 0 ==
956 22:12:39.203523 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
957 22:12:39.207521 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
958 22:12:39.210368 == TX Byte 1 ==
959 22:12:39.214110 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
960 22:12:39.217272 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
961 22:12:39.220222
962 22:12:39.220688 [DATLAT]
963 22:12:39.221059 Freq=800, CH0 RK0
964 22:12:39.221409
965 22:12:39.223872 DATLAT Default: 0xa
966 22:12:39.224299 0, 0xFFFF, sum = 0
967 22:12:39.227245 1, 0xFFFF, sum = 0
968 22:12:39.227725 2, 0xFFFF, sum = 0
969 22:12:39.230173 3, 0xFFFF, sum = 0
970 22:12:39.234160 4, 0xFFFF, sum = 0
971 22:12:39.234693 5, 0xFFFF, sum = 0
972 22:12:39.237510 6, 0xFFFF, sum = 0
973 22:12:39.238063 7, 0xFFFF, sum = 0
974 22:12:39.240077 8, 0xFFFF, sum = 0
975 22:12:39.240548 9, 0x0, sum = 1
976 22:12:39.243899 10, 0x0, sum = 2
977 22:12:39.244332 11, 0x0, sum = 3
978 22:12:39.244680 12, 0x0, sum = 4
979 22:12:39.247468 best_step = 10
980 22:12:39.247893
981 22:12:39.248230 ==
982 22:12:39.250383 Dram Type= 6, Freq= 0, CH_0, rank 0
983 22:12:39.253855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
984 22:12:39.254381 ==
985 22:12:39.257065 RX Vref Scan: 1
986 22:12:39.257586
987 22:12:39.260416 Set Vref Range= 32 -> 127
988 22:12:39.260959
989 22:12:39.261305 RX Vref 32 -> 127, step: 1
990 22:12:39.261623
991 22:12:39.263563 RX Delay -111 -> 252, step: 8
992 22:12:39.264081
993 22:12:39.267503 Set Vref, RX VrefLevel [Byte0]: 32
994 22:12:39.270583 [Byte1]: 32
995 22:12:39.271104
996 22:12:39.273428 Set Vref, RX VrefLevel [Byte0]: 33
997 22:12:39.276769 [Byte1]: 33
998 22:12:39.281551
999 22:12:39.282075 Set Vref, RX VrefLevel [Byte0]: 34
1000 22:12:39.284295 [Byte1]: 34
1001 22:12:39.288291
1002 22:12:39.288720 Set Vref, RX VrefLevel [Byte0]: 35
1003 22:12:39.291837 [Byte1]: 35
1004 22:12:39.296633
1005 22:12:39.297169 Set Vref, RX VrefLevel [Byte0]: 36
1006 22:12:39.299832 [Byte1]: 36
1007 22:12:39.303889
1008 22:12:39.304319 Set Vref, RX VrefLevel [Byte0]: 37
1009 22:12:39.307555 [Byte1]: 37
1010 22:12:39.311902
1011 22:12:39.312329 Set Vref, RX VrefLevel [Byte0]: 38
1012 22:12:39.315113 [Byte1]: 38
1013 22:12:39.319418
1014 22:12:39.319938 Set Vref, RX VrefLevel [Byte0]: 39
1015 22:12:39.323122 [Byte1]: 39
1016 22:12:39.326792
1017 22:12:39.327244 Set Vref, RX VrefLevel [Byte0]: 40
1018 22:12:39.330190 [Byte1]: 40
1019 22:12:39.334663
1020 22:12:39.335088 Set Vref, RX VrefLevel [Byte0]: 41
1021 22:12:39.337694 [Byte1]: 41
1022 22:12:39.342501
1023 22:12:39.343015 Set Vref, RX VrefLevel [Byte0]: 42
1024 22:12:39.345322 [Byte1]: 42
1025 22:12:39.349323
1026 22:12:39.350157 Set Vref, RX VrefLevel [Byte0]: 43
1027 22:12:39.352988 [Byte1]: 43
1028 22:12:39.357222
1029 22:12:39.357642 Set Vref, RX VrefLevel [Byte0]: 44
1030 22:12:39.360428 [Byte1]: 44
1031 22:12:39.365295
1032 22:12:39.365810 Set Vref, RX VrefLevel [Byte0]: 45
1033 22:12:39.368939 [Byte1]: 45
1034 22:12:39.372980
1035 22:12:39.373493 Set Vref, RX VrefLevel [Byte0]: 46
1036 22:12:39.375737 [Byte1]: 46
1037 22:12:39.380121
1038 22:12:39.380635 Set Vref, RX VrefLevel [Byte0]: 47
1039 22:12:39.383779 [Byte1]: 47
1040 22:12:39.388248
1041 22:12:39.388764 Set Vref, RX VrefLevel [Byte0]: 48
1042 22:12:39.391356 [Byte1]: 48
1043 22:12:39.395530
1044 22:12:39.396042 Set Vref, RX VrefLevel [Byte0]: 49
1045 22:12:39.398769 [Byte1]: 49
1046 22:12:39.403300
1047 22:12:39.403813 Set Vref, RX VrefLevel [Byte0]: 50
1048 22:12:39.406514 [Byte1]: 50
1049 22:12:39.411246
1050 22:12:39.411758 Set Vref, RX VrefLevel [Byte0]: 51
1051 22:12:39.414376 [Byte1]: 51
1052 22:12:39.418620
1053 22:12:39.419060 Set Vref, RX VrefLevel [Byte0]: 52
1054 22:12:39.422060 [Byte1]: 52
1055 22:12:39.426058
1056 22:12:39.426586 Set Vref, RX VrefLevel [Byte0]: 53
1057 22:12:39.429575 [Byte1]: 53
1058 22:12:39.433720
1059 22:12:39.434194 Set Vref, RX VrefLevel [Byte0]: 54
1060 22:12:39.437295 [Byte1]: 54
1061 22:12:39.441757
1062 22:12:39.442314 Set Vref, RX VrefLevel [Byte0]: 55
1063 22:12:39.444908 [Byte1]: 55
1064 22:12:39.449485
1065 22:12:39.450040 Set Vref, RX VrefLevel [Byte0]: 56
1066 22:12:39.452259 [Byte1]: 56
1067 22:12:39.456818
1068 22:12:39.457384 Set Vref, RX VrefLevel [Byte0]: 57
1069 22:12:39.460229 [Byte1]: 57
1070 22:12:39.464280
1071 22:12:39.464836 Set Vref, RX VrefLevel [Byte0]: 58
1072 22:12:39.467872 [Byte1]: 58
1073 22:12:39.472034
1074 22:12:39.472590 Set Vref, RX VrefLevel [Byte0]: 59
1075 22:12:39.475672 [Byte1]: 59
1076 22:12:39.479752
1077 22:12:39.480313 Set Vref, RX VrefLevel [Byte0]: 60
1078 22:12:39.483258 [Byte1]: 60
1079 22:12:39.487220
1080 22:12:39.487778 Set Vref, RX VrefLevel [Byte0]: 61
1081 22:12:39.490850 [Byte1]: 61
1082 22:12:39.494924
1083 22:12:39.495601 Set Vref, RX VrefLevel [Byte0]: 62
1084 22:12:39.498071 [Byte1]: 62
1085 22:12:39.503113
1086 22:12:39.503779 Set Vref, RX VrefLevel [Byte0]: 63
1087 22:12:39.506294 [Byte1]: 63
1088 22:12:39.510404
1089 22:12:39.510969 Set Vref, RX VrefLevel [Byte0]: 64
1090 22:12:39.513889 [Byte1]: 64
1091 22:12:39.518033
1092 22:12:39.518594 Set Vref, RX VrefLevel [Byte0]: 65
1093 22:12:39.521080 [Byte1]: 65
1094 22:12:39.525137
1095 22:12:39.525598 Set Vref, RX VrefLevel [Byte0]: 66
1096 22:12:39.528816 [Byte1]: 66
1097 22:12:39.533035
1098 22:12:39.533596 Set Vref, RX VrefLevel [Byte0]: 67
1099 22:12:39.536515 [Byte1]: 67
1100 22:12:39.540710
1101 22:12:39.541174 Set Vref, RX VrefLevel [Byte0]: 68
1102 22:12:39.544727 [Byte1]: 68
1103 22:12:39.549055
1104 22:12:39.549617 Set Vref, RX VrefLevel [Byte0]: 69
1105 22:12:39.551885 [Byte1]: 69
1106 22:12:39.556096
1107 22:12:39.556616 Set Vref, RX VrefLevel [Byte0]: 70
1108 22:12:39.559412 [Byte1]: 70
1109 22:12:39.563631
1110 22:12:39.564148 Set Vref, RX VrefLevel [Byte0]: 71
1111 22:12:39.567048 [Byte1]: 71
1112 22:12:39.571542
1113 22:12:39.572066 Set Vref, RX VrefLevel [Byte0]: 72
1114 22:12:39.574970 [Byte1]: 72
1115 22:12:39.579654
1116 22:12:39.580207 Set Vref, RX VrefLevel [Byte0]: 73
1117 22:12:39.582384 [Byte1]: 73
1118 22:12:39.586642
1119 22:12:39.587243 Set Vref, RX VrefLevel [Byte0]: 74
1120 22:12:39.590013 [Byte1]: 74
1121 22:12:39.594811
1122 22:12:39.595394 Final RX Vref Byte 0 = 54 to rank0
1123 22:12:39.597553 Final RX Vref Byte 1 = 59 to rank0
1124 22:12:39.601022 Final RX Vref Byte 0 = 54 to rank1
1125 22:12:39.604254 Final RX Vref Byte 1 = 59 to rank1==
1126 22:12:39.607558 Dram Type= 6, Freq= 0, CH_0, rank 0
1127 22:12:39.613821 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1128 22:12:39.614494 ==
1129 22:12:39.614944 DQS Delay:
1130 22:12:39.615344 DQS0 = 0, DQS1 = 0
1131 22:12:39.617516 DQM Delay:
1132 22:12:39.617976 DQM0 = 88, DQM1 = 76
1133 22:12:39.620452 DQ Delay:
1134 22:12:39.624193 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =88
1135 22:12:39.627220 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1136 22:12:39.630717 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =76
1137 22:12:39.633821 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =84
1138 22:12:39.634342
1139 22:12:39.634679
1140 22:12:39.641224 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f28, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
1141 22:12:39.644376 CH0 RK0: MR19=606, MR18=2F28
1142 22:12:39.650806 CH0_RK0: MR19=0x606, MR18=0x2F28, DQSOSC=397, MR23=63, INC=93, DEC=62
1143 22:12:39.651376
1144 22:12:39.653726 ----->DramcWriteLeveling(PI) begin...
1145 22:12:39.654252 ==
1146 22:12:39.657346 Dram Type= 6, Freq= 0, CH_0, rank 1
1147 22:12:39.660500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1148 22:12:39.660923 ==
1149 22:12:39.663614 Write leveling (Byte 0): 33 => 33
1150 22:12:39.667424 Write leveling (Byte 1): 26 => 26
1151 22:12:39.670690 DramcWriteLeveling(PI) end<-----
1152 22:12:39.671241
1153 22:12:39.671583 ==
1154 22:12:39.674077 Dram Type= 6, Freq= 0, CH_0, rank 1
1155 22:12:39.677319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1156 22:12:39.677839 ==
1157 22:12:39.680677 [Gating] SW mode calibration
1158 22:12:39.687426 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1159 22:12:39.694248 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1160 22:12:39.738275 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1161 22:12:39.739420 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1162 22:12:39.739874 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1163 22:12:39.740322 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 22:12:39.740762 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 22:12:39.741105 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 22:12:39.741510 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 22:12:39.742059 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 22:12:39.742418 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 22:12:39.742744 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 22:12:39.782360 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 22:12:39.783371 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 22:12:39.783899 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 22:12:39.784344 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 22:12:39.784701 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 22:12:39.785104 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 22:12:39.785540 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 22:12:39.785877 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1178 22:12:39.786196 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1179 22:12:39.786576 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 22:12:39.803068 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 22:12:39.803728 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 22:12:39.804108 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 22:12:39.804775 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 22:12:39.806636 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 22:12:39.810215 0 9 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
1186 22:12:39.813177 0 9 8 | B1->B0 | 2424 3434 | 1 0 | (1 1) (0 0)
1187 22:12:39.816900 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1188 22:12:39.820210 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1189 22:12:39.826781 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1190 22:12:39.829655 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1191 22:12:39.833409 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1192 22:12:39.840640 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1193 22:12:39.843518 0 10 4 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 0)
1194 22:12:39.846637 0 10 8 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (1 0)
1195 22:12:39.850268 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1196 22:12:39.856338 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1197 22:12:39.860105 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 22:12:39.862923 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 22:12:39.869786 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 22:12:39.873078 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 22:12:39.876799 0 11 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
1202 22:12:39.883770 0 11 8 | B1->B0 | 3535 4646 | 0 0 | (1 1) (0 0)
1203 22:12:39.887390 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1204 22:12:39.891495 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1205 22:12:39.894963 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1206 22:12:39.901212 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1207 22:12:39.905374 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1208 22:12:39.908590 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1209 22:12:39.911706 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1210 22:12:39.918472 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 22:12:39.921128 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 22:12:39.925390 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 22:12:39.931212 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 22:12:39.934927 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 22:12:39.937983 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 22:12:39.944871 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 22:12:39.947865 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 22:12:39.951099 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 22:12:39.958400 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 22:12:39.961356 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 22:12:39.964810 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 22:12:39.971750 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 22:12:39.974416 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 22:12:39.978384 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 22:12:39.985446 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1226 22:12:39.988037 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1227 22:12:39.991465 Total UI for P1: 0, mck2ui 16
1228 22:12:39.994723 best dqsien dly found for B0: ( 0, 14, 4)
1229 22:12:39.998215 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1230 22:12:40.001400 Total UI for P1: 0, mck2ui 16
1231 22:12:40.004501 best dqsien dly found for B1: ( 0, 14, 8)
1232 22:12:40.007972 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1233 22:12:40.011397 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1234 22:12:40.011963
1235 22:12:40.014837 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1236 22:12:40.021848 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1237 22:12:40.022416 [Gating] SW calibration Done
1238 22:12:40.022790 ==
1239 22:12:40.024856 Dram Type= 6, Freq= 0, CH_0, rank 1
1240 22:12:40.031457 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1241 22:12:40.032022 ==
1242 22:12:40.032394 RX Vref Scan: 0
1243 22:12:40.032786
1244 22:12:40.034303 RX Vref 0 -> 0, step: 1
1245 22:12:40.034789
1246 22:12:40.037710 RX Delay -130 -> 252, step: 16
1247 22:12:40.041130 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1248 22:12:40.044579 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1249 22:12:40.047781 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1250 22:12:40.054888 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1251 22:12:40.058195 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1252 22:12:40.060993 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
1253 22:12:40.064486 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1254 22:12:40.067414 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1255 22:12:40.071075 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1256 22:12:40.077784 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1257 22:12:40.080837 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1258 22:12:40.084635 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1259 22:12:40.088147 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1260 22:12:40.094986 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1261 22:12:40.098022 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1262 22:12:40.100787 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1263 22:12:40.101252 ==
1264 22:12:40.104315 Dram Type= 6, Freq= 0, CH_0, rank 1
1265 22:12:40.107822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1266 22:12:40.108392 ==
1267 22:12:40.111054 DQS Delay:
1268 22:12:40.111662 DQS0 = 0, DQS1 = 0
1269 22:12:40.114406 DQM Delay:
1270 22:12:40.114969 DQM0 = 85, DQM1 = 76
1271 22:12:40.115378 DQ Delay:
1272 22:12:40.117918 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1273 22:12:40.120827 DQ4 =93, DQ5 =69, DQ6 =93, DQ7 =93
1274 22:12:40.123901 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
1275 22:12:40.127644 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1276 22:12:40.128208
1277 22:12:40.128571
1278 22:12:40.130887 ==
1279 22:12:40.131508 Dram Type= 6, Freq= 0, CH_0, rank 1
1280 22:12:40.137778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1281 22:12:40.138344 ==
1282 22:12:40.138715
1283 22:12:40.139055
1284 22:12:40.140912 TX Vref Scan disable
1285 22:12:40.141478 == TX Byte 0 ==
1286 22:12:40.143659 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1287 22:12:40.150281 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1288 22:12:40.150846 == TX Byte 1 ==
1289 22:12:40.154052 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1290 22:12:40.160386 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1291 22:12:40.160941 ==
1292 22:12:40.163310 Dram Type= 6, Freq= 0, CH_0, rank 1
1293 22:12:40.166723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1294 22:12:40.167143 ==
1295 22:12:40.181188 TX Vref=22, minBit 1, minWin=27, winSum=444
1296 22:12:40.184514 TX Vref=24, minBit 1, minWin=27, winSum=445
1297 22:12:40.187807 TX Vref=26, minBit 5, minWin=27, winSum=446
1298 22:12:40.191395 TX Vref=28, minBit 1, minWin=27, winSum=450
1299 22:12:40.195098 TX Vref=30, minBit 4, minWin=27, winSum=450
1300 22:12:40.200982 TX Vref=32, minBit 4, minWin=27, winSum=450
1301 22:12:40.204835 [TxChooseVref] Worse bit 1, Min win 27, Win sum 450, Final Vref 28
1302 22:12:40.205408
1303 22:12:40.208948 Final TX Range 1 Vref 28
1304 22:12:40.209519
1305 22:12:40.209888 ==
1306 22:12:40.211154 Dram Type= 6, Freq= 0, CH_0, rank 1
1307 22:12:40.215251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1308 22:12:40.215820 ==
1309 22:12:40.218033
1310 22:12:40.218480
1311 22:12:40.218833 TX Vref Scan disable
1312 22:12:40.221408 == TX Byte 0 ==
1313 22:12:40.225075 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1314 22:12:40.231262 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1315 22:12:40.231675 == TX Byte 1 ==
1316 22:12:40.234473 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1317 22:12:40.241397 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1318 22:12:40.241810
1319 22:12:40.242129 [DATLAT]
1320 22:12:40.242428 Freq=800, CH0 RK1
1321 22:12:40.242718
1322 22:12:40.244609 DATLAT Default: 0xa
1323 22:12:40.245120 0, 0xFFFF, sum = 0
1324 22:12:40.247623 1, 0xFFFF, sum = 0
1325 22:12:40.248040 2, 0xFFFF, sum = 0
1326 22:12:40.251031 3, 0xFFFF, sum = 0
1327 22:12:40.254211 4, 0xFFFF, sum = 0
1328 22:12:40.254654 5, 0xFFFF, sum = 0
1329 22:12:40.257559 6, 0xFFFF, sum = 0
1330 22:12:40.257974 7, 0xFFFF, sum = 0
1331 22:12:40.260912 8, 0xFFFF, sum = 0
1332 22:12:40.261328 9, 0x0, sum = 1
1333 22:12:40.264287 10, 0x0, sum = 2
1334 22:12:40.264704 11, 0x0, sum = 3
1335 22:12:40.265033 12, 0x0, sum = 4
1336 22:12:40.267774 best_step = 10
1337 22:12:40.268182
1338 22:12:40.268505 ==
1339 22:12:40.271161 Dram Type= 6, Freq= 0, CH_0, rank 1
1340 22:12:40.274192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1341 22:12:40.274649 ==
1342 22:12:40.277794 RX Vref Scan: 0
1343 22:12:40.278201
1344 22:12:40.278567 RX Vref 0 -> 0, step: 1
1345 22:12:40.280787
1346 22:12:40.281204 RX Delay -95 -> 252, step: 8
1347 22:12:40.287951 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1348 22:12:40.291201 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1349 22:12:40.294661 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1350 22:12:40.297757 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1351 22:12:40.301467 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1352 22:12:40.307827 iDelay=209, Bit 5, Center 80 (-31 ~ 192) 224
1353 22:12:40.311307 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1354 22:12:40.315130 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1355 22:12:40.318045 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1356 22:12:40.320864 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1357 22:12:40.328070 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1358 22:12:40.331729 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1359 22:12:40.334169 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1360 22:12:40.338535 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1361 22:12:40.341809 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1362 22:12:40.347608 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1363 22:12:40.348112 ==
1364 22:12:40.351793 Dram Type= 6, Freq= 0, CH_0, rank 1
1365 22:12:40.355006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1366 22:12:40.355619 ==
1367 22:12:40.356098 DQS Delay:
1368 22:12:40.358047 DQS0 = 0, DQS1 = 0
1369 22:12:40.358457 DQM Delay:
1370 22:12:40.361094 DQM0 = 87, DQM1 = 77
1371 22:12:40.361505 DQ Delay:
1372 22:12:40.364220 DQ0 =84, DQ1 =92, DQ2 =80, DQ3 =80
1373 22:12:40.367727 DQ4 =88, DQ5 =80, DQ6 =100, DQ7 =96
1374 22:12:40.370994 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =72
1375 22:12:40.374560 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =84
1376 22:12:40.374969
1377 22:12:40.375331
1378 22:12:40.384766 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e2a, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 398 ps
1379 22:12:40.385287 CH0 RK1: MR19=606, MR18=2E2A
1380 22:12:40.391074 CH0_RK1: MR19=0x606, MR18=0x2E2A, DQSOSC=398, MR23=63, INC=93, DEC=62
1381 22:12:40.393957 [RxdqsGatingPostProcess] freq 800
1382 22:12:40.400668 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1383 22:12:40.404417 Pre-setting of DQS Precalculation
1384 22:12:40.407571 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1385 22:12:40.407996 ==
1386 22:12:40.411421 Dram Type= 6, Freq= 0, CH_1, rank 0
1387 22:12:40.414590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1388 22:12:40.417733 ==
1389 22:12:40.420769 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1390 22:12:40.427334 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1391 22:12:40.436718 [CA 0] Center 36 (6~67) winsize 62
1392 22:12:40.439788 [CA 1] Center 37 (6~68) winsize 63
1393 22:12:40.443119 [CA 2] Center 34 (4~65) winsize 62
1394 22:12:40.446509 [CA 3] Center 34 (4~65) winsize 62
1395 22:12:40.450688 [CA 4] Center 34 (4~65) winsize 62
1396 22:12:40.452863 [CA 5] Center 33 (3~64) winsize 62
1397 22:12:40.453386
1398 22:12:40.456431 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1399 22:12:40.456959
1400 22:12:40.460380 [CATrainingPosCal] consider 1 rank data
1401 22:12:40.463003 u2DelayCellTimex100 = 270/100 ps
1402 22:12:40.466315 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1403 22:12:40.472771 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1404 22:12:40.476006 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1405 22:12:40.479476 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1406 22:12:40.483263 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1407 22:12:40.485929 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1408 22:12:40.486352
1409 22:12:40.489928 CA PerBit enable=1, Macro0, CA PI delay=33
1410 22:12:40.490459
1411 22:12:40.492788 [CBTSetCACLKResult] CA Dly = 33
1412 22:12:40.493322 CS Dly: 4 (0~35)
1413 22:12:40.495951 ==
1414 22:12:40.499555 Dram Type= 6, Freq= 0, CH_1, rank 1
1415 22:12:40.502785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1416 22:12:40.503230 ==
1417 22:12:40.506268 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1418 22:12:40.513042 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1419 22:12:40.522619 [CA 0] Center 36 (6~67) winsize 62
1420 22:12:40.526829 [CA 1] Center 36 (6~67) winsize 62
1421 22:12:40.529220 [CA 2] Center 34 (4~65) winsize 62
1422 22:12:40.532689 [CA 3] Center 33 (3~64) winsize 62
1423 22:12:40.535791 [CA 4] Center 34 (3~65) winsize 63
1424 22:12:40.539162 [CA 5] Center 33 (3~64) winsize 62
1425 22:12:40.539726
1426 22:12:40.542279 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1427 22:12:40.542807
1428 22:12:40.546386 [CATrainingPosCal] consider 2 rank data
1429 22:12:40.549693 u2DelayCellTimex100 = 270/100 ps
1430 22:12:40.552994 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1431 22:12:40.557103 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1432 22:12:40.560784 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1433 22:12:40.564390 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1434 22:12:40.568166 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1435 22:12:40.571734 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1436 22:12:40.572196
1437 22:12:40.575242 CA PerBit enable=1, Macro0, CA PI delay=33
1438 22:12:40.575705
1439 22:12:40.579431 [CBTSetCACLKResult] CA Dly = 33
1440 22:12:40.579948 CS Dly: 5 (0~38)
1441 22:12:40.580321
1442 22:12:40.582591 ----->DramcWriteLeveling(PI) begin...
1443 22:12:40.586062 ==
1444 22:12:40.586580 Dram Type= 6, Freq= 0, CH_1, rank 0
1445 22:12:40.592550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1446 22:12:40.593105 ==
1447 22:12:40.595901 Write leveling (Byte 0): 24 => 24
1448 22:12:40.598992 Write leveling (Byte 1): 29 => 29
1449 22:12:40.602673 DramcWriteLeveling(PI) end<-----
1450 22:12:40.603133
1451 22:12:40.603530 ==
1452 22:12:40.605969 Dram Type= 6, Freq= 0, CH_1, rank 0
1453 22:12:40.609297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1454 22:12:40.609866 ==
1455 22:12:40.612111 [Gating] SW mode calibration
1456 22:12:40.619259 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1457 22:12:40.626334 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1458 22:12:40.628851 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1459 22:12:40.631985 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1460 22:12:40.638672 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 22:12:40.642374 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 22:12:40.645432 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 22:12:40.648995 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 22:12:40.655879 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 22:12:40.658727 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 22:12:40.661710 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 22:12:40.669008 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 22:12:40.671815 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 22:12:40.674862 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 22:12:40.681931 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 22:12:40.685109 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 22:12:40.688945 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 22:12:40.694974 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 22:12:40.698150 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1475 22:12:40.701337 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1476 22:12:40.707900 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 22:12:40.711356 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 22:12:40.715086 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 22:12:40.721864 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 22:12:40.724750 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 22:12:40.728921 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 22:12:40.735134 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 22:12:40.738372 0 9 4 | B1->B0 | 2323 2626 | 1 1 | (1 1) (1 1)
1484 22:12:40.741080 0 9 8 | B1->B0 | 2e2d 3333 | 1 1 | (0 0) (1 1)
1485 22:12:40.747923 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1486 22:12:40.751666 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1487 22:12:40.755041 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1488 22:12:40.762038 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1489 22:12:40.764324 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1490 22:12:40.768473 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1491 22:12:40.774627 0 10 4 | B1->B0 | 3030 3131 | 1 1 | (1 0) (1 0)
1492 22:12:40.777391 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (1 1) (0 0)
1493 22:12:40.782267 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 22:12:40.787838 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 22:12:40.790986 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 22:12:40.794681 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 22:12:40.801221 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 22:12:40.804153 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 22:12:40.807351 0 11 4 | B1->B0 | 2727 2b2b | 0 0 | (0 0) (0 0)
1500 22:12:40.814614 0 11 8 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
1501 22:12:40.817546 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1502 22:12:40.820773 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1503 22:12:40.827169 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1504 22:12:40.830608 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1505 22:12:40.834123 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1506 22:12:40.840281 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1507 22:12:40.843914 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1508 22:12:40.847396 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 22:12:40.851142 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 22:12:40.857467 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 22:12:40.860653 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 22:12:40.864025 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 22:12:40.870815 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 22:12:40.874158 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 22:12:40.877714 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 22:12:40.884013 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 22:12:40.887455 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 22:12:40.890798 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 22:12:40.897713 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 22:12:40.900299 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 22:12:40.903644 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 22:12:40.910531 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 22:12:40.913635 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1524 22:12:40.916977 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1525 22:12:40.920440 Total UI for P1: 0, mck2ui 16
1526 22:12:40.923719 best dqsien dly found for B0: ( 0, 14, 4)
1527 22:12:40.926745 Total UI for P1: 0, mck2ui 16
1528 22:12:40.930012 best dqsien dly found for B1: ( 0, 14, 6)
1529 22:12:40.933754 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1530 22:12:40.937165 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1531 22:12:40.937598
1532 22:12:40.943675 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1533 22:12:40.946551 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1534 22:12:40.946987 [Gating] SW calibration Done
1535 22:12:40.950002 ==
1536 22:12:40.953065 Dram Type= 6, Freq= 0, CH_1, rank 0
1537 22:12:40.956370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1538 22:12:40.956961 ==
1539 22:12:40.957467 RX Vref Scan: 0
1540 22:12:40.957793
1541 22:12:40.960095 RX Vref 0 -> 0, step: 1
1542 22:12:40.960516
1543 22:12:40.963300 RX Delay -130 -> 252, step: 16
1544 22:12:40.966670 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1545 22:12:40.970167 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1546 22:12:40.976439 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1547 22:12:40.979714 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1548 22:12:40.983525 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1549 22:12:40.987074 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1550 22:12:40.990168 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1551 22:12:40.996794 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1552 22:12:40.999432 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1553 22:12:41.002801 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1554 22:12:41.006272 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1555 22:12:41.009778 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1556 22:12:41.016752 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1557 22:12:41.020203 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1558 22:12:41.023211 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1559 22:12:41.026335 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1560 22:12:41.026756 ==
1561 22:12:41.030037 Dram Type= 6, Freq= 0, CH_1, rank 0
1562 22:12:41.035911 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1563 22:12:41.036336 ==
1564 22:12:41.036664 DQS Delay:
1565 22:12:41.039990 DQS0 = 0, DQS1 = 0
1566 22:12:41.040409 DQM Delay:
1567 22:12:41.040741 DQM0 = 88, DQM1 = 84
1568 22:12:41.043140 DQ Delay:
1569 22:12:41.046776 DQ0 =93, DQ1 =85, DQ2 =69, DQ3 =85
1570 22:12:41.049408 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1571 22:12:41.053169 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1572 22:12:41.055868 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1573 22:12:41.056292
1574 22:12:41.056623
1575 22:12:41.056930 ==
1576 22:12:41.059265 Dram Type= 6, Freq= 0, CH_1, rank 0
1577 22:12:41.063034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1578 22:12:41.063509 ==
1579 22:12:41.063979
1580 22:12:41.064495
1581 22:12:41.066332 TX Vref Scan disable
1582 22:12:41.069072 == TX Byte 0 ==
1583 22:12:41.072866 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1584 22:12:41.075859 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1585 22:12:41.079325 == TX Byte 1 ==
1586 22:12:41.082469 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1587 22:12:41.086217 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1588 22:12:41.086733 ==
1589 22:12:41.089296 Dram Type= 6, Freq= 0, CH_1, rank 0
1590 22:12:41.092651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1591 22:12:41.096109 ==
1592 22:12:41.107552 TX Vref=22, minBit 2, minWin=26, winSum=438
1593 22:12:41.111137 TX Vref=24, minBit 2, minWin=27, winSum=448
1594 22:12:41.114688 TX Vref=26, minBit 0, minWin=27, winSum=447
1595 22:12:41.117577 TX Vref=28, minBit 5, minWin=27, winSum=455
1596 22:12:41.120924 TX Vref=30, minBit 0, minWin=27, winSum=451
1597 22:12:41.124342 TX Vref=32, minBit 0, minWin=27, winSum=447
1598 22:12:41.131266 [TxChooseVref] Worse bit 5, Min win 27, Win sum 455, Final Vref 28
1599 22:12:41.131714
1600 22:12:41.134649 Final TX Range 1 Vref 28
1601 22:12:41.135114
1602 22:12:41.135534 ==
1603 22:12:41.138229 Dram Type= 6, Freq= 0, CH_1, rank 0
1604 22:12:41.141293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1605 22:12:41.141735 ==
1606 22:12:41.142072
1607 22:12:41.142381
1608 22:12:41.145563 TX Vref Scan disable
1609 22:12:41.148031 == TX Byte 0 ==
1610 22:12:41.151383 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1611 22:12:41.154832 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1612 22:12:41.158012 == TX Byte 1 ==
1613 22:12:41.161446 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1614 22:12:41.164574 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1615 22:12:41.165089
1616 22:12:41.167671 [DATLAT]
1617 22:12:41.168089 Freq=800, CH1 RK0
1618 22:12:41.168422
1619 22:12:41.171577 DATLAT Default: 0xa
1620 22:12:41.172091 0, 0xFFFF, sum = 0
1621 22:12:41.174576 1, 0xFFFF, sum = 0
1622 22:12:41.175094 2, 0xFFFF, sum = 0
1623 22:12:41.177737 3, 0xFFFF, sum = 0
1624 22:12:41.178272 4, 0xFFFF, sum = 0
1625 22:12:41.180994 5, 0xFFFF, sum = 0
1626 22:12:41.181515 6, 0xFFFF, sum = 0
1627 22:12:41.184895 7, 0xFFFF, sum = 0
1628 22:12:41.185415 8, 0xFFFF, sum = 0
1629 22:12:41.188278 9, 0x0, sum = 1
1630 22:12:41.188795 10, 0x0, sum = 2
1631 22:12:41.191083 11, 0x0, sum = 3
1632 22:12:41.191632 12, 0x0, sum = 4
1633 22:12:41.194537 best_step = 10
1634 22:12:41.195049
1635 22:12:41.195419 ==
1636 22:12:41.197598 Dram Type= 6, Freq= 0, CH_1, rank 0
1637 22:12:41.201411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1638 22:12:41.201941 ==
1639 22:12:41.204283 RX Vref Scan: 1
1640 22:12:41.204703
1641 22:12:41.205035 Set Vref Range= 32 -> 127
1642 22:12:41.205347
1643 22:12:41.207950 RX Vref 32 -> 127, step: 1
1644 22:12:41.208469
1645 22:12:41.211033 RX Delay -95 -> 252, step: 8
1646 22:12:41.211585
1647 22:12:41.214082 Set Vref, RX VrefLevel [Byte0]: 32
1648 22:12:41.217316 [Byte1]: 32
1649 22:12:41.217832
1650 22:12:41.221506 Set Vref, RX VrefLevel [Byte0]: 33
1651 22:12:41.224024 [Byte1]: 33
1652 22:12:41.227468
1653 22:12:41.227885 Set Vref, RX VrefLevel [Byte0]: 34
1654 22:12:41.231425 [Byte1]: 34
1655 22:12:41.235293
1656 22:12:41.235714 Set Vref, RX VrefLevel [Byte0]: 35
1657 22:12:41.238658 [Byte1]: 35
1658 22:12:41.243052
1659 22:12:41.243653 Set Vref, RX VrefLevel [Byte0]: 36
1660 22:12:41.246146 [Byte1]: 36
1661 22:12:41.250689
1662 22:12:41.251238 Set Vref, RX VrefLevel [Byte0]: 37
1663 22:12:41.254070 [Byte1]: 37
1664 22:12:41.258435
1665 22:12:41.258981 Set Vref, RX VrefLevel [Byte0]: 38
1666 22:12:41.261575 [Byte1]: 38
1667 22:12:41.265503
1668 22:12:41.265925 Set Vref, RX VrefLevel [Byte0]: 39
1669 22:12:41.269353 [Byte1]: 39
1670 22:12:41.273447
1671 22:12:41.273957 Set Vref, RX VrefLevel [Byte0]: 40
1672 22:12:41.276647 [Byte1]: 40
1673 22:12:41.281332
1674 22:12:41.281890 Set Vref, RX VrefLevel [Byte0]: 41
1675 22:12:41.284122 [Byte1]: 41
1676 22:12:41.289233
1677 22:12:41.289786 Set Vref, RX VrefLevel [Byte0]: 42
1678 22:12:41.293013 [Byte1]: 42
1679 22:12:41.296700
1680 22:12:41.297252 Set Vref, RX VrefLevel [Byte0]: 43
1681 22:12:41.299476 [Byte1]: 43
1682 22:12:41.303902
1683 22:12:41.304363 Set Vref, RX VrefLevel [Byte0]: 44
1684 22:12:41.306931 [Byte1]: 44
1685 22:12:41.311699
1686 22:12:41.312252 Set Vref, RX VrefLevel [Byte0]: 45
1687 22:12:41.315024 [Byte1]: 45
1688 22:12:41.319034
1689 22:12:41.319636 Set Vref, RX VrefLevel [Byte0]: 46
1690 22:12:41.322073 [Byte1]: 46
1691 22:12:41.326501
1692 22:12:41.326961 Set Vref, RX VrefLevel [Byte0]: 47
1693 22:12:41.330021 [Byte1]: 47
1694 22:12:41.334058
1695 22:12:41.334476 Set Vref, RX VrefLevel [Byte0]: 48
1696 22:12:41.337373 [Byte1]: 48
1697 22:12:41.341527
1698 22:12:41.341955 Set Vref, RX VrefLevel [Byte0]: 49
1699 22:12:41.345221 [Byte1]: 49
1700 22:12:41.349376
1701 22:12:41.349822 Set Vref, RX VrefLevel [Byte0]: 50
1702 22:12:41.352899 [Byte1]: 50
1703 22:12:41.357325
1704 22:12:41.357843 Set Vref, RX VrefLevel [Byte0]: 51
1705 22:12:41.360300 [Byte1]: 51
1706 22:12:41.365191
1707 22:12:41.365625 Set Vref, RX VrefLevel [Byte0]: 52
1708 22:12:41.368049 [Byte1]: 52
1709 22:12:41.372616
1710 22:12:41.373219 Set Vref, RX VrefLevel [Byte0]: 53
1711 22:12:41.375126 [Byte1]: 53
1712 22:12:41.379760
1713 22:12:41.380181 Set Vref, RX VrefLevel [Byte0]: 54
1714 22:12:41.382907 [Byte1]: 54
1715 22:12:41.387540
1716 22:12:41.388050 Set Vref, RX VrefLevel [Byte0]: 55
1717 22:12:41.390397 [Byte1]: 55
1718 22:12:41.395169
1719 22:12:41.395718 Set Vref, RX VrefLevel [Byte0]: 56
1720 22:12:41.398534 [Byte1]: 56
1721 22:12:41.402710
1722 22:12:41.403216 Set Vref, RX VrefLevel [Byte0]: 57
1723 22:12:41.405808 [Byte1]: 57
1724 22:12:41.411062
1725 22:12:41.411616 Set Vref, RX VrefLevel [Byte0]: 58
1726 22:12:41.413360 [Byte1]: 58
1727 22:12:41.417728
1728 22:12:41.418146 Set Vref, RX VrefLevel [Byte0]: 59
1729 22:12:41.420630 [Byte1]: 59
1730 22:12:41.425090
1731 22:12:41.425574 Set Vref, RX VrefLevel [Byte0]: 60
1732 22:12:41.428268 [Byte1]: 60
1733 22:12:41.433094
1734 22:12:41.433795 Set Vref, RX VrefLevel [Byte0]: 61
1735 22:12:41.436219 [Byte1]: 61
1736 22:12:41.440463
1737 22:12:41.440882 Set Vref, RX VrefLevel [Byte0]: 62
1738 22:12:41.444111 [Byte1]: 62
1739 22:12:41.449274
1740 22:12:41.449702 Set Vref, RX VrefLevel [Byte0]: 63
1741 22:12:41.451146 [Byte1]: 63
1742 22:12:41.455905
1743 22:12:41.456318 Set Vref, RX VrefLevel [Byte0]: 64
1744 22:12:41.459078 [Byte1]: 64
1745 22:12:41.463957
1746 22:12:41.464474 Set Vref, RX VrefLevel [Byte0]: 65
1747 22:12:41.466403 [Byte1]: 65
1748 22:12:41.470702
1749 22:12:41.471230 Set Vref, RX VrefLevel [Byte0]: 66
1750 22:12:41.474412 [Byte1]: 66
1751 22:12:41.478579
1752 22:12:41.479046 Set Vref, RX VrefLevel [Byte0]: 67
1753 22:12:41.481784 [Byte1]: 67
1754 22:12:41.486377
1755 22:12:41.486892 Set Vref, RX VrefLevel [Byte0]: 68
1756 22:12:41.489852 [Byte1]: 68
1757 22:12:41.493646
1758 22:12:41.494134 Set Vref, RX VrefLevel [Byte0]: 69
1759 22:12:41.497074 [Byte1]: 69
1760 22:12:41.502097
1761 22:12:41.502513 Set Vref, RX VrefLevel [Byte0]: 70
1762 22:12:41.504515 [Byte1]: 70
1763 22:12:41.508755
1764 22:12:41.509263 Set Vref, RX VrefLevel [Byte0]: 71
1765 22:12:41.512174 [Byte1]: 71
1766 22:12:41.516613
1767 22:12:41.517095 Set Vref, RX VrefLevel [Byte0]: 72
1768 22:12:41.520479 [Byte1]: 72
1769 22:12:41.524450
1770 22:12:41.524947 Set Vref, RX VrefLevel [Byte0]: 73
1771 22:12:41.527572 [Byte1]: 73
1772 22:12:41.532130
1773 22:12:41.532784 Set Vref, RX VrefLevel [Byte0]: 74
1774 22:12:41.538332 [Byte1]: 74
1775 22:12:41.539432
1776 22:12:41.539826 Final RX Vref Byte 0 = 53 to rank0
1777 22:12:41.542138 Final RX Vref Byte 1 = 58 to rank0
1778 22:12:41.545851 Final RX Vref Byte 0 = 53 to rank1
1779 22:12:41.548934 Final RX Vref Byte 1 = 58 to rank1==
1780 22:12:41.552545 Dram Type= 6, Freq= 0, CH_1, rank 0
1781 22:12:41.559104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1782 22:12:41.559652 ==
1783 22:12:41.559991 DQS Delay:
1784 22:12:41.562644 DQS0 = 0, DQS1 = 0
1785 22:12:41.563074 DQM Delay:
1786 22:12:41.563467 DQM0 = 84, DQM1 = 81
1787 22:12:41.565795 DQ Delay:
1788 22:12:41.569004 DQ0 =92, DQ1 =80, DQ2 =72, DQ3 =84
1789 22:12:41.572540 DQ4 =80, DQ5 =96, DQ6 =96, DQ7 =76
1790 22:12:41.575554 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =72
1791 22:12:41.578813 DQ12 =88, DQ13 =92, DQ14 =88, DQ15 =88
1792 22:12:41.579321
1793 22:12:41.579696
1794 22:12:41.585512 [DQSOSCAuto] RK0, (LSB)MR18= 0x1629, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 404 ps
1795 22:12:41.589165 CH1 RK0: MR19=606, MR18=1629
1796 22:12:41.595267 CH1_RK0: MR19=0x606, MR18=0x1629, DQSOSC=399, MR23=63, INC=92, DEC=61
1797 22:12:41.595765
1798 22:12:41.599126 ----->DramcWriteLeveling(PI) begin...
1799 22:12:41.599699 ==
1800 22:12:41.602258 Dram Type= 6, Freq= 0, CH_1, rank 1
1801 22:12:41.605387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1802 22:12:41.605806 ==
1803 22:12:41.608568 Write leveling (Byte 0): 28 => 28
1804 22:12:41.611929 Write leveling (Byte 1): 28 => 28
1805 22:12:41.615300 DramcWriteLeveling(PI) end<-----
1806 22:12:41.615779
1807 22:12:41.616109 ==
1808 22:12:41.618380 Dram Type= 6, Freq= 0, CH_1, rank 1
1809 22:12:41.622121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1810 22:12:41.622611 ==
1811 22:12:41.625542 [Gating] SW mode calibration
1812 22:12:41.632070 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1813 22:12:41.638839 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1814 22:12:41.641909 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1815 22:12:41.648346 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1816 22:12:41.651614 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1817 22:12:41.654825 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 22:12:41.661834 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 22:12:41.664983 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 22:12:41.668508 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 22:12:41.675683 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 22:12:41.678274 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 22:12:41.682104 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 22:12:41.688360 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 22:12:41.691748 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 22:12:41.694916 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 22:12:41.698964 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 22:12:41.705453 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 22:12:41.708228 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 22:12:41.711403 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1831 22:12:41.718231 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1832 22:12:41.721426 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 22:12:41.725503 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 22:12:41.731722 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 22:12:41.735044 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 22:12:41.738396 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 22:12:41.744493 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 22:12:41.747853 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 22:12:41.751109 0 9 4 | B1->B0 | 2323 2727 | 0 1 | (0 0) (1 1)
1840 22:12:41.758604 0 9 8 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
1841 22:12:41.761465 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 22:12:41.764758 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 22:12:41.771482 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1844 22:12:41.774606 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1845 22:12:41.777980 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1846 22:12:41.784605 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1847 22:12:41.788035 0 10 4 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (0 0)
1848 22:12:41.791115 0 10 8 | B1->B0 | 2e2e 2323 | 0 0 | (1 1) (0 0)
1849 22:12:41.798066 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 22:12:41.801039 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 22:12:41.804616 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 22:12:41.808385 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 22:12:41.814753 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1854 22:12:41.818048 0 11 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 1)
1855 22:12:41.821236 0 11 4 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
1856 22:12:41.828289 0 11 8 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
1857 22:12:41.831751 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 22:12:41.834494 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 22:12:41.841276 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1860 22:12:41.844414 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1861 22:12:41.847682 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1862 22:12:41.854929 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1863 22:12:41.857808 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1864 22:12:41.861161 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1865 22:12:41.867699 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 22:12:41.870724 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 22:12:41.874068 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 22:12:41.880961 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 22:12:41.884486 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 22:12:41.887735 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 22:12:41.894486 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 22:12:41.897459 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 22:12:41.900974 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 22:12:41.907974 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 22:12:41.910790 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 22:12:41.914383 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 22:12:41.921225 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1878 22:12:41.924113 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1879 22:12:41.927628 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1880 22:12:41.930785 Total UI for P1: 0, mck2ui 16
1881 22:12:41.934288 best dqsien dly found for B0: ( 0, 13, 30)
1882 22:12:41.940368 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1883 22:12:41.941076 Total UI for P1: 0, mck2ui 16
1884 22:12:41.946940 best dqsien dly found for B1: ( 0, 14, 4)
1885 22:12:41.950276 best DQS0 dly(MCK, UI, PI) = (0, 13, 30)
1886 22:12:41.954227 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1887 22:12:41.954783
1888 22:12:41.957522 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 30)
1889 22:12:41.960375 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1890 22:12:41.963907 [Gating] SW calibration Done
1891 22:12:41.964448 ==
1892 22:12:41.967110 Dram Type= 6, Freq= 0, CH_1, rank 1
1893 22:12:41.970825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1894 22:12:41.971456 ==
1895 22:12:41.974222 RX Vref Scan: 0
1896 22:12:41.974794
1897 22:12:41.975166 RX Vref 0 -> 0, step: 1
1898 22:12:41.975575
1899 22:12:41.977615 RX Delay -130 -> 252, step: 16
1900 22:12:41.980704 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1901 22:12:41.987163 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1902 22:12:41.990706 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1903 22:12:41.993818 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1904 22:12:41.997481 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1905 22:12:42.000386 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1906 22:12:42.007220 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1907 22:12:42.010438 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1908 22:12:42.013587 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1909 22:12:42.017113 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1910 22:12:42.020642 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1911 22:12:42.027095 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1912 22:12:42.030426 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1913 22:12:42.034033 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1914 22:12:42.036577 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1915 22:12:42.039938 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1916 22:12:42.043213 ==
1917 22:12:42.047236 Dram Type= 6, Freq= 0, CH_1, rank 1
1918 22:12:42.049991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1919 22:12:42.050416 ==
1920 22:12:42.050748 DQS Delay:
1921 22:12:42.054020 DQS0 = 0, DQS1 = 0
1922 22:12:42.054530 DQM Delay:
1923 22:12:42.057200 DQM0 = 84, DQM1 = 81
1924 22:12:42.057719 DQ Delay:
1925 22:12:42.060315 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1926 22:12:42.063081 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =85
1927 22:12:42.066595 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1928 22:12:42.069966 DQ12 =93, DQ13 =93, DQ14 =85, DQ15 =85
1929 22:12:42.070531
1930 22:12:42.070902
1931 22:12:42.071282 ==
1932 22:12:42.073503 Dram Type= 6, Freq= 0, CH_1, rank 1
1933 22:12:42.076604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1934 22:12:42.077073 ==
1935 22:12:42.077432
1936 22:12:42.077765
1937 22:12:42.079690 TX Vref Scan disable
1938 22:12:42.083430 == TX Byte 0 ==
1939 22:12:42.086718 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1940 22:12:42.089780 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1941 22:12:42.093141 == TX Byte 1 ==
1942 22:12:42.096847 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1943 22:12:42.099562 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1944 22:12:42.100022 ==
1945 22:12:42.103088 Dram Type= 6, Freq= 0, CH_1, rank 1
1946 22:12:42.109985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1947 22:12:42.110534 ==
1948 22:12:42.121124 TX Vref=22, minBit 1, minWin=27, winSum=450
1949 22:12:42.125070 TX Vref=24, minBit 0, minWin=28, winSum=454
1950 22:12:42.128023 TX Vref=26, minBit 3, minWin=27, winSum=454
1951 22:12:42.131599 TX Vref=28, minBit 6, minWin=27, winSum=453
1952 22:12:42.135027 TX Vref=30, minBit 0, minWin=27, winSum=453
1953 22:12:42.140932 TX Vref=32, minBit 1, minWin=27, winSum=454
1954 22:12:42.143808 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 24
1955 22:12:42.144268
1956 22:12:42.147163 Final TX Range 1 Vref 24
1957 22:12:42.147668
1958 22:12:42.148028 ==
1959 22:12:42.151279 Dram Type= 6, Freq= 0, CH_1, rank 1
1960 22:12:42.154719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1961 22:12:42.157442 ==
1962 22:12:42.157942
1963 22:12:42.158306
1964 22:12:42.158692 TX Vref Scan disable
1965 22:12:42.161469 == TX Byte 0 ==
1966 22:12:42.164663 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1967 22:12:42.171287 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1968 22:12:42.171881 == TX Byte 1 ==
1969 22:12:42.173877 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1970 22:12:42.180686 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1971 22:12:42.181212
1972 22:12:42.181576 [DATLAT]
1973 22:12:42.181914 Freq=800, CH1 RK1
1974 22:12:42.182243
1975 22:12:42.183864 DATLAT Default: 0xa
1976 22:12:42.184325 0, 0xFFFF, sum = 0
1977 22:12:42.187547 1, 0xFFFF, sum = 0
1978 22:12:42.190509 2, 0xFFFF, sum = 0
1979 22:12:42.191081 3, 0xFFFF, sum = 0
1980 22:12:42.194185 4, 0xFFFF, sum = 0
1981 22:12:42.194653 5, 0xFFFF, sum = 0
1982 22:12:42.197356 6, 0xFFFF, sum = 0
1983 22:12:42.198008 7, 0xFFFF, sum = 0
1984 22:12:42.200476 8, 0xFFFF, sum = 0
1985 22:12:42.201053 9, 0x0, sum = 1
1986 22:12:42.203692 10, 0x0, sum = 2
1987 22:12:42.204163 11, 0x0, sum = 3
1988 22:12:42.207100 12, 0x0, sum = 4
1989 22:12:42.207715 best_step = 10
1990 22:12:42.208089
1991 22:12:42.208434 ==
1992 22:12:42.210364 Dram Type= 6, Freq= 0, CH_1, rank 1
1993 22:12:42.213473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1994 22:12:42.213941 ==
1995 22:12:42.217059 RX Vref Scan: 0
1996 22:12:42.217526
1997 22:12:42.220447 RX Vref 0 -> 0, step: 1
1998 22:12:42.220914
1999 22:12:42.221281 RX Delay -95 -> 252, step: 8
2000 22:12:42.227630 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
2001 22:12:42.230649 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
2002 22:12:42.234672 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2003 22:12:42.237348 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
2004 22:12:42.240923 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2005 22:12:42.247157 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2006 22:12:42.250708 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
2007 22:12:42.254067 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2008 22:12:42.257173 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
2009 22:12:42.260520 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2010 22:12:42.267857 iDelay=209, Bit 10, Center 84 (-31 ~ 200) 232
2011 22:12:42.270438 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2012 22:12:42.273517 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2013 22:12:42.277557 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2014 22:12:42.283751 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2015 22:12:42.287240 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2016 22:12:42.287657 ==
2017 22:12:42.290735 Dram Type= 6, Freq= 0, CH_1, rank 1
2018 22:12:42.293414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2019 22:12:42.293833 ==
2020 22:12:42.297266 DQS Delay:
2021 22:12:42.297800 DQS0 = 0, DQS1 = 0
2022 22:12:42.298145 DQM Delay:
2023 22:12:42.300321 DQM0 = 86, DQM1 = 83
2024 22:12:42.300764 DQ Delay:
2025 22:12:42.303419 DQ0 =88, DQ1 =84, DQ2 =76, DQ3 =84
2026 22:12:42.307165 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
2027 22:12:42.310097 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =80
2028 22:12:42.313754 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
2029 22:12:42.314174
2030 22:12:42.314503
2031 22:12:42.323472 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d38, (MSB)MR19= 0x606, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
2032 22:12:42.323900 CH1 RK1: MR19=606, MR18=1D38
2033 22:12:42.330172 CH1_RK1: MR19=0x606, MR18=0x1D38, DQSOSC=395, MR23=63, INC=94, DEC=63
2034 22:12:42.333841 [RxdqsGatingPostProcess] freq 800
2035 22:12:42.340095 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2036 22:12:42.343534 Pre-setting of DQS Precalculation
2037 22:12:42.346737 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2038 22:12:42.353738 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2039 22:12:42.363520 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2040 22:12:42.364003
2041 22:12:42.364330
2042 22:12:42.366614 [Calibration Summary] 1600 Mbps
2043 22:12:42.367142 CH 0, Rank 0
2044 22:12:42.369646 SW Impedance : PASS
2045 22:12:42.370059 DUTY Scan : NO K
2046 22:12:42.373626 ZQ Calibration : PASS
2047 22:12:42.376356 Jitter Meter : NO K
2048 22:12:42.376770 CBT Training : PASS
2049 22:12:42.381023 Write leveling : PASS
2050 22:12:42.383559 RX DQS gating : PASS
2051 22:12:42.384075 RX DQ/DQS(RDDQC) : PASS
2052 22:12:42.386814 TX DQ/DQS : PASS
2053 22:12:42.387322 RX DATLAT : PASS
2054 22:12:42.389852 RX DQ/DQS(Engine): PASS
2055 22:12:42.393126 TX OE : NO K
2056 22:12:42.393540 All Pass.
2057 22:12:42.393866
2058 22:12:42.394170 CH 0, Rank 1
2059 22:12:42.396698 SW Impedance : PASS
2060 22:12:42.399600 DUTY Scan : NO K
2061 22:12:42.400012 ZQ Calibration : PASS
2062 22:12:42.403464 Jitter Meter : NO K
2063 22:12:42.406677 CBT Training : PASS
2064 22:12:42.407089 Write leveling : PASS
2065 22:12:42.409825 RX DQS gating : PASS
2066 22:12:42.413263 RX DQ/DQS(RDDQC) : PASS
2067 22:12:42.413676 TX DQ/DQS : PASS
2068 22:12:42.416481 RX DATLAT : PASS
2069 22:12:42.419323 RX DQ/DQS(Engine): PASS
2070 22:12:42.419890 TX OE : NO K
2071 22:12:42.423432 All Pass.
2072 22:12:42.423941
2073 22:12:42.424270 CH 1, Rank 0
2074 22:12:42.426582 SW Impedance : PASS
2075 22:12:42.427005 DUTY Scan : NO K
2076 22:12:42.430147 ZQ Calibration : PASS
2077 22:12:42.433180 Jitter Meter : NO K
2078 22:12:42.433725 CBT Training : PASS
2079 22:12:42.436229 Write leveling : PASS
2080 22:12:42.436701 RX DQS gating : PASS
2081 22:12:42.439480 RX DQ/DQS(RDDQC) : PASS
2082 22:12:42.442829 TX DQ/DQS : PASS
2083 22:12:42.443296 RX DATLAT : PASS
2084 22:12:42.446322 RX DQ/DQS(Engine): PASS
2085 22:12:42.449376 TX OE : NO K
2086 22:12:42.449811 All Pass.
2087 22:12:42.450143
2088 22:12:42.450450 CH 1, Rank 1
2089 22:12:42.453007 SW Impedance : PASS
2090 22:12:42.456487 DUTY Scan : NO K
2091 22:12:42.456909 ZQ Calibration : PASS
2092 22:12:42.459380 Jitter Meter : NO K
2093 22:12:42.462692 CBT Training : PASS
2094 22:12:42.463114 Write leveling : PASS
2095 22:12:42.466270 RX DQS gating : PASS
2096 22:12:42.469678 RX DQ/DQS(RDDQC) : PASS
2097 22:12:42.470308 TX DQ/DQS : PASS
2098 22:12:42.473049 RX DATLAT : PASS
2099 22:12:42.476025 RX DQ/DQS(Engine): PASS
2100 22:12:42.476448 TX OE : NO K
2101 22:12:42.479577 All Pass.
2102 22:12:42.479996
2103 22:12:42.480328 DramC Write-DBI off
2104 22:12:42.482957 PER_BANK_REFRESH: Hybrid Mode
2105 22:12:42.483493 TX_TRACKING: ON
2106 22:12:42.485912 [GetDramInforAfterCalByMRR] Vendor 6.
2107 22:12:42.493038 [GetDramInforAfterCalByMRR] Revision 606.
2108 22:12:42.495870 [GetDramInforAfterCalByMRR] Revision 2 0.
2109 22:12:42.496295 MR0 0x3b3b
2110 22:12:42.496630 MR8 0x5151
2111 22:12:42.498937 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2112 22:12:42.499396
2113 22:12:42.502431 MR0 0x3b3b
2114 22:12:42.502975 MR8 0x5151
2115 22:12:42.505941 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2116 22:12:42.506365
2117 22:12:42.515768 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2118 22:12:42.518986 [FAST_K] Save calibration result to emmc
2119 22:12:42.522238 [FAST_K] Save calibration result to emmc
2120 22:12:42.526613 dram_init: config_dvfs: 1
2121 22:12:42.529017 dramc_set_vcore_voltage set vcore to 662500
2122 22:12:42.532456 Read voltage for 1200, 2
2123 22:12:42.532876 Vio18 = 0
2124 22:12:42.533206 Vcore = 662500
2125 22:12:42.535998 Vdram = 0
2126 22:12:42.536414 Vddq = 0
2127 22:12:42.536741 Vmddr = 0
2128 22:12:42.542080 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2129 22:12:42.545362 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2130 22:12:42.548648 MEM_TYPE=3, freq_sel=15
2131 22:12:42.552292 sv_algorithm_assistance_LP4_1600
2132 22:12:42.555345 ============ PULL DRAM RESETB DOWN ============
2133 22:12:42.558874 ========== PULL DRAM RESETB DOWN end =========
2134 22:12:42.565510 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2135 22:12:42.568496 ===================================
2136 22:12:42.572126 LPDDR4 DRAM CONFIGURATION
2137 22:12:42.572576 ===================================
2138 22:12:42.575290 EX_ROW_EN[0] = 0x0
2139 22:12:42.578601 EX_ROW_EN[1] = 0x0
2140 22:12:42.579158 LP4Y_EN = 0x0
2141 22:12:42.582274 WORK_FSP = 0x0
2142 22:12:42.582785 WL = 0x4
2143 22:12:42.586329 RL = 0x4
2144 22:12:42.586868 BL = 0x2
2145 22:12:42.588671 RPST = 0x0
2146 22:12:42.589173 RD_PRE = 0x0
2147 22:12:42.592029 WR_PRE = 0x1
2148 22:12:42.592441 WR_PST = 0x0
2149 22:12:42.595716 DBI_WR = 0x0
2150 22:12:42.596219 DBI_RD = 0x0
2151 22:12:42.598785 OTF = 0x1
2152 22:12:42.601867 ===================================
2153 22:12:42.605694 ===================================
2154 22:12:42.606140 ANA top config
2155 22:12:42.608395 ===================================
2156 22:12:42.611522 DLL_ASYNC_EN = 0
2157 22:12:42.615728 ALL_SLAVE_EN = 0
2158 22:12:42.618715 NEW_RANK_MODE = 1
2159 22:12:42.619282 DLL_IDLE_MODE = 1
2160 22:12:42.622141 LP45_APHY_COMB_EN = 1
2161 22:12:42.625105 TX_ODT_DIS = 1
2162 22:12:42.628975 NEW_8X_MODE = 1
2163 22:12:42.631689 ===================================
2164 22:12:42.634900 ===================================
2165 22:12:42.638441 data_rate = 2400
2166 22:12:42.638858 CKR = 1
2167 22:12:42.642009 DQ_P2S_RATIO = 8
2168 22:12:42.645185 ===================================
2169 22:12:42.648133 CA_P2S_RATIO = 8
2170 22:12:42.651508 DQ_CA_OPEN = 0
2171 22:12:42.654597 DQ_SEMI_OPEN = 0
2172 22:12:42.658353 CA_SEMI_OPEN = 0
2173 22:12:42.658789 CA_FULL_RATE = 0
2174 22:12:42.661521 DQ_CKDIV4_EN = 0
2175 22:12:42.664508 CA_CKDIV4_EN = 0
2176 22:12:42.668095 CA_PREDIV_EN = 0
2177 22:12:42.671580 PH8_DLY = 17
2178 22:12:42.674829 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2179 22:12:42.677866 DQ_AAMCK_DIV = 4
2180 22:12:42.678393 CA_AAMCK_DIV = 4
2181 22:12:42.681741 CA_ADMCK_DIV = 4
2182 22:12:42.684860 DQ_TRACK_CA_EN = 0
2183 22:12:42.687949 CA_PICK = 1200
2184 22:12:42.691276 CA_MCKIO = 1200
2185 22:12:42.694669 MCKIO_SEMI = 0
2186 22:12:42.697827 PLL_FREQ = 2366
2187 22:12:42.698284 DQ_UI_PI_RATIO = 32
2188 22:12:42.701202 CA_UI_PI_RATIO = 0
2189 22:12:42.704793 ===================================
2190 22:12:42.707577 ===================================
2191 22:12:42.710929 memory_type:LPDDR4
2192 22:12:42.715246 GP_NUM : 10
2193 22:12:42.715766 SRAM_EN : 1
2194 22:12:42.718315 MD32_EN : 0
2195 22:12:42.721652 ===================================
2196 22:12:42.724803 [ANA_INIT] >>>>>>>>>>>>>>
2197 22:12:42.725331 <<<<<< [CONFIGURE PHASE]: ANA_TX
2198 22:12:42.727778 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2199 22:12:42.731219 ===================================
2200 22:12:42.734501 data_rate = 2400,PCW = 0X5b00
2201 22:12:42.737622 ===================================
2202 22:12:42.740903 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2203 22:12:42.747289 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2204 22:12:42.754190 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2205 22:12:42.757401 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2206 22:12:42.761489 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2207 22:12:42.764500 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2208 22:12:42.767432 [ANA_INIT] flow start
2209 22:12:42.767914 [ANA_INIT] PLL >>>>>>>>
2210 22:12:42.770690 [ANA_INIT] PLL <<<<<<<<
2211 22:12:42.774260 [ANA_INIT] MIDPI >>>>>>>>
2212 22:12:42.774807 [ANA_INIT] MIDPI <<<<<<<<
2213 22:12:42.777620 [ANA_INIT] DLL >>>>>>>>
2214 22:12:42.780896 [ANA_INIT] DLL <<<<<<<<
2215 22:12:42.781361 [ANA_INIT] flow end
2216 22:12:42.787086 ============ LP4 DIFF to SE enter ============
2217 22:12:42.790838 ============ LP4 DIFF to SE exit ============
2218 22:12:42.794356 [ANA_INIT] <<<<<<<<<<<<<
2219 22:12:42.797580 [Flow] Enable top DCM control >>>>>
2220 22:12:42.800655 [Flow] Enable top DCM control <<<<<
2221 22:12:42.801169 Enable DLL master slave shuffle
2222 22:12:42.807167 ==============================================================
2223 22:12:42.810715 Gating Mode config
2224 22:12:42.813797 ==============================================================
2225 22:12:42.817364 Config description:
2226 22:12:42.827336 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2227 22:12:42.834115 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2228 22:12:42.837338 SELPH_MODE 0: By rank 1: By Phase
2229 22:12:42.843853 ==============================================================
2230 22:12:42.847500 GAT_TRACK_EN = 1
2231 22:12:42.850362 RX_GATING_MODE = 2
2232 22:12:42.854088 RX_GATING_TRACK_MODE = 2
2233 22:12:42.856727 SELPH_MODE = 1
2234 22:12:42.860139 PICG_EARLY_EN = 1
2235 22:12:42.860596 VALID_LAT_VALUE = 1
2236 22:12:42.866860 ==============================================================
2237 22:12:42.870116 Enter into Gating configuration >>>>
2238 22:12:42.873599 Exit from Gating configuration <<<<
2239 22:12:42.876882 Enter into DVFS_PRE_config >>>>>
2240 22:12:42.886710 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2241 22:12:42.890321 Exit from DVFS_PRE_config <<<<<
2242 22:12:42.893313 Enter into PICG configuration >>>>
2243 22:12:42.896987 Exit from PICG configuration <<<<
2244 22:12:42.900225 [RX_INPUT] configuration >>>>>
2245 22:12:42.903746 [RX_INPUT] configuration <<<<<
2246 22:12:42.906754 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2247 22:12:42.913331 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2248 22:12:42.920040 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2249 22:12:42.926758 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2250 22:12:42.933269 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2251 22:12:42.940334 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2252 22:12:42.943368 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2253 22:12:42.946245 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2254 22:12:42.949672 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2255 22:12:42.952959 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2256 22:12:42.959706 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2257 22:12:42.963116 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2258 22:12:42.966369 ===================================
2259 22:12:42.969758 LPDDR4 DRAM CONFIGURATION
2260 22:12:42.973199 ===================================
2261 22:12:42.973667 EX_ROW_EN[0] = 0x0
2262 22:12:42.976727 EX_ROW_EN[1] = 0x0
2263 22:12:42.977191 LP4Y_EN = 0x0
2264 22:12:42.979517 WORK_FSP = 0x0
2265 22:12:42.979938 WL = 0x4
2266 22:12:42.982922 RL = 0x4
2267 22:12:42.983378 BL = 0x2
2268 22:12:42.986745 RPST = 0x0
2269 22:12:42.989918 RD_PRE = 0x0
2270 22:12:42.990344 WR_PRE = 0x1
2271 22:12:42.992870 WR_PST = 0x0
2272 22:12:42.993286 DBI_WR = 0x0
2273 22:12:42.996231 DBI_RD = 0x0
2274 22:12:42.996730 OTF = 0x1
2275 22:12:42.999376 ===================================
2276 22:12:43.003166 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2277 22:12:43.006645 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2278 22:12:43.013025 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2279 22:12:43.016443 ===================================
2280 22:12:43.019666 LPDDR4 DRAM CONFIGURATION
2281 22:12:43.022991 ===================================
2282 22:12:43.023494 EX_ROW_EN[0] = 0x10
2283 22:12:43.026604 EX_ROW_EN[1] = 0x0
2284 22:12:43.027110 LP4Y_EN = 0x0
2285 22:12:43.029536 WORK_FSP = 0x0
2286 22:12:43.029963 WL = 0x4
2287 22:12:43.032635 RL = 0x4
2288 22:12:43.033052 BL = 0x2
2289 22:12:43.035975 RPST = 0x0
2290 22:12:43.036391 RD_PRE = 0x0
2291 22:12:43.039591 WR_PRE = 0x1
2292 22:12:43.040005 WR_PST = 0x0
2293 22:12:43.042879 DBI_WR = 0x0
2294 22:12:43.045913 DBI_RD = 0x0
2295 22:12:43.046323 OTF = 0x1
2296 22:12:43.049437 ===================================
2297 22:12:43.055974 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2298 22:12:43.056392 ==
2299 22:12:43.059555 Dram Type= 6, Freq= 0, CH_0, rank 0
2300 22:12:43.063110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2301 22:12:43.063654 ==
2302 22:12:43.066416 [Duty_Offset_Calibration]
2303 22:12:43.066925 B0:2 B1:0 CA:4
2304 22:12:43.067296
2305 22:12:43.069970 [DutyScan_Calibration_Flow] k_type=0
2306 22:12:43.079555
2307 22:12:43.080239 ==CLK 0==
2308 22:12:43.082700 Final CLK duty delay cell = -4
2309 22:12:43.085921 [-4] MAX Duty = 5031%(X100), DQS PI = 14
2310 22:12:43.089094 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2311 22:12:43.092696 [-4] AVG Duty = 4937%(X100)
2312 22:12:43.093113
2313 22:12:43.095681 CH0 CLK Duty spec in!! Max-Min= 187%
2314 22:12:43.100205 [DutyScan_Calibration_Flow] ====Done====
2315 22:12:43.100608
2316 22:12:43.102462 [DutyScan_Calibration_Flow] k_type=1
2317 22:12:43.118585
2318 22:12:43.119082 ==DQS 0 ==
2319 22:12:43.121381 Final DQS duty delay cell = -4
2320 22:12:43.124988 [-4] MAX Duty = 4969%(X100), DQS PI = 14
2321 22:12:43.128182 [-4] MIN Duty = 4876%(X100), DQS PI = 0
2322 22:12:43.131523 [-4] AVG Duty = 4922%(X100)
2323 22:12:43.131971
2324 22:12:43.132319 ==DQS 1 ==
2325 22:12:43.135516 Final DQS duty delay cell = 0
2326 22:12:43.138481 [0] MAX Duty = 5125%(X100), DQS PI = 4
2327 22:12:43.141922 [0] MIN Duty = 5000%(X100), DQS PI = 0
2328 22:12:43.145105 [0] AVG Duty = 5062%(X100)
2329 22:12:43.145514
2330 22:12:43.148008 CH0 DQS 0 Duty spec in!! Max-Min= 93%
2331 22:12:43.148417
2332 22:12:43.151388 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2333 22:12:43.155278 [DutyScan_Calibration_Flow] ====Done====
2334 22:12:43.155826
2335 22:12:43.158074 [DutyScan_Calibration_Flow] k_type=3
2336 22:12:43.174867
2337 22:12:43.175456 ==DQM 0 ==
2338 22:12:43.178250 Final DQM duty delay cell = 0
2339 22:12:43.181572 [0] MAX Duty = 5125%(X100), DQS PI = 20
2340 22:12:43.185259 [0] MIN Duty = 4844%(X100), DQS PI = 54
2341 22:12:43.188631 [0] AVG Duty = 4984%(X100)
2342 22:12:43.189218
2343 22:12:43.189577 ==DQM 1 ==
2344 22:12:43.191442 Final DQM duty delay cell = 0
2345 22:12:43.194808 [0] MAX Duty = 4969%(X100), DQS PI = 2
2346 22:12:43.198283 [0] MIN Duty = 4907%(X100), DQS PI = 0
2347 22:12:43.201604 [0] AVG Duty = 4938%(X100)
2348 22:12:43.202163
2349 22:12:43.204609 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2350 22:12:43.205180
2351 22:12:43.208281 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2352 22:12:43.211252 [DutyScan_Calibration_Flow] ====Done====
2353 22:12:43.211791
2354 22:12:43.215058 [DutyScan_Calibration_Flow] k_type=2
2355 22:12:43.231623
2356 22:12:43.232164 ==DQ 0 ==
2357 22:12:43.234774 Final DQ duty delay cell = 0
2358 22:12:43.238310 [0] MAX Duty = 5125%(X100), DQS PI = 18
2359 22:12:43.241506 [0] MIN Duty = 5000%(X100), DQS PI = 10
2360 22:12:43.241959 [0] AVG Duty = 5062%(X100)
2361 22:12:43.244647
2362 22:12:43.245186 ==DQ 1 ==
2363 22:12:43.247576 Final DQ duty delay cell = 0
2364 22:12:43.250932 [0] MAX Duty = 5125%(X100), DQS PI = 4
2365 22:12:43.254713 [0] MIN Duty = 4938%(X100), DQS PI = 16
2366 22:12:43.255163 [0] AVG Duty = 5031%(X100)
2367 22:12:43.255578
2368 22:12:43.258084 CH0 DQ 0 Duty spec in!! Max-Min= 125%
2369 22:12:43.261142
2370 22:12:43.264393 CH0 DQ 1 Duty spec in!! Max-Min= 187%
2371 22:12:43.267968 [DutyScan_Calibration_Flow] ====Done====
2372 22:12:43.268418 ==
2373 22:12:43.270649 Dram Type= 6, Freq= 0, CH_1, rank 0
2374 22:12:43.274769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2375 22:12:43.275363 ==
2376 22:12:43.278308 [Duty_Offset_Calibration]
2377 22:12:43.278844 B0:0 B1:-1 CA:3
2378 22:12:43.279238
2379 22:12:43.280582 [DutyScan_Calibration_Flow] k_type=0
2380 22:12:43.290451
2381 22:12:43.290997 ==CLK 0==
2382 22:12:43.294014 Final CLK duty delay cell = -4
2383 22:12:43.296911 [-4] MAX Duty = 5031%(X100), DQS PI = 12
2384 22:12:43.300252 [-4] MIN Duty = 4844%(X100), DQS PI = 4
2385 22:12:43.303557 [-4] AVG Duty = 4937%(X100)
2386 22:12:43.304005
2387 22:12:43.307141 CH1 CLK Duty spec in!! Max-Min= 187%
2388 22:12:43.310306 [DutyScan_Calibration_Flow] ====Done====
2389 22:12:43.310895
2390 22:12:43.313621 [DutyScan_Calibration_Flow] k_type=1
2391 22:12:43.329970
2392 22:12:43.330504 ==DQS 0 ==
2393 22:12:43.333045 Final DQS duty delay cell = 0
2394 22:12:43.337097 [0] MAX Duty = 5187%(X100), DQS PI = 60
2395 22:12:43.340015 [0] MIN Duty = 4907%(X100), DQS PI = 6
2396 22:12:43.340480 [0] AVG Duty = 5047%(X100)
2397 22:12:43.342848
2398 22:12:43.343407 ==DQS 1 ==
2399 22:12:43.346584 Final DQS duty delay cell = 0
2400 22:12:43.349912 [0] MAX Duty = 5156%(X100), DQS PI = 0
2401 22:12:43.352949 [0] MIN Duty = 5031%(X100), DQS PI = 52
2402 22:12:43.353414 [0] AVG Duty = 5093%(X100)
2403 22:12:43.356445
2404 22:12:43.359857 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2405 22:12:43.360522
2406 22:12:43.363160 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2407 22:12:43.366506 [DutyScan_Calibration_Flow] ====Done====
2408 22:12:43.367270
2409 22:12:43.369424 [DutyScan_Calibration_Flow] k_type=3
2410 22:12:43.386778
2411 22:12:43.387352 ==DQM 0 ==
2412 22:12:43.389868 Final DQM duty delay cell = 0
2413 22:12:43.392950 [0] MAX Duty = 5031%(X100), DQS PI = 12
2414 22:12:43.396195 [0] MIN Duty = 4782%(X100), DQS PI = 6
2415 22:12:43.396672 [0] AVG Duty = 4906%(X100)
2416 22:12:43.399631
2417 22:12:43.400100 ==DQM 1 ==
2418 22:12:43.403271 Final DQM duty delay cell = 0
2419 22:12:43.406080 [0] MAX Duty = 5000%(X100), DQS PI = 4
2420 22:12:43.409388 [0] MIN Duty = 4844%(X100), DQS PI = 30
2421 22:12:43.409863 [0] AVG Duty = 4922%(X100)
2422 22:12:43.413002
2423 22:12:43.416306 CH1 DQM 0 Duty spec in!! Max-Min= 249%
2424 22:12:43.416776
2425 22:12:43.419237 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2426 22:12:43.422624 [DutyScan_Calibration_Flow] ====Done====
2427 22:12:43.423047
2428 22:12:43.425833 [DutyScan_Calibration_Flow] k_type=2
2429 22:12:43.441926
2430 22:12:43.442484 ==DQ 0 ==
2431 22:12:43.444906 Final DQ duty delay cell = -4
2432 22:12:43.448460 [-4] MAX Duty = 5031%(X100), DQS PI = 30
2433 22:12:43.451838 [-4] MIN Duty = 4844%(X100), DQS PI = 4
2434 22:12:43.455506 [-4] AVG Duty = 4937%(X100)
2435 22:12:43.455931
2436 22:12:43.456267 ==DQ 1 ==
2437 22:12:43.458617 Final DQ duty delay cell = 0
2438 22:12:43.462136 [0] MAX Duty = 5031%(X100), DQS PI = 2
2439 22:12:43.465053 [0] MIN Duty = 4876%(X100), DQS PI = 24
2440 22:12:43.468255 [0] AVG Duty = 4953%(X100)
2441 22:12:43.468771
2442 22:12:43.471708 CH1 DQ 0 Duty spec in!! Max-Min= 187%
2443 22:12:43.472126
2444 22:12:43.475348 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2445 22:12:43.478830 [DutyScan_Calibration_Flow] ====Done====
2446 22:12:43.481819 nWR fixed to 30
2447 22:12:43.482315 [ModeRegInit_LP4] CH0 RK0
2448 22:12:43.485497 [ModeRegInit_LP4] CH0 RK1
2449 22:12:43.488760 [ModeRegInit_LP4] CH1 RK0
2450 22:12:43.491843 [ModeRegInit_LP4] CH1 RK1
2451 22:12:43.492429 match AC timing 7
2452 22:12:43.498199 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2453 22:12:43.502137 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2454 22:12:43.505250 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2455 22:12:43.511914 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2456 22:12:43.514943 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2457 22:12:43.515496 ==
2458 22:12:43.518038 Dram Type= 6, Freq= 0, CH_0, rank 0
2459 22:12:43.521498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2460 22:12:43.522071 ==
2461 22:12:43.528173 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2462 22:12:43.534560 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2463 22:12:43.541814 [CA 0] Center 39 (9~70) winsize 62
2464 22:12:43.545490 [CA 1] Center 39 (9~69) winsize 61
2465 22:12:43.548344 [CA 2] Center 35 (5~66) winsize 62
2466 22:12:43.552117 [CA 3] Center 35 (5~66) winsize 62
2467 22:12:43.555384 [CA 4] Center 33 (3~64) winsize 62
2468 22:12:43.558785 [CA 5] Center 33 (3~64) winsize 62
2469 22:12:43.559399
2470 22:12:43.562777 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2471 22:12:43.563469
2472 22:12:43.565384 [CATrainingPosCal] consider 1 rank data
2473 22:12:43.569167 u2DelayCellTimex100 = 270/100 ps
2474 22:12:43.572338 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2475 22:12:43.575845 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2476 22:12:43.581729 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2477 22:12:43.585831 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2478 22:12:43.588542 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2479 22:12:43.591675 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2480 22:12:43.592144
2481 22:12:43.595797 CA PerBit enable=1, Macro0, CA PI delay=33
2482 22:12:43.596360
2483 22:12:43.598414 [CBTSetCACLKResult] CA Dly = 33
2484 22:12:43.598876 CS Dly: 7 (0~38)
2485 22:12:43.602260 ==
2486 22:12:43.604969 Dram Type= 6, Freq= 0, CH_0, rank 1
2487 22:12:43.608625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2488 22:12:43.609114 ==
2489 22:12:43.611619 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2490 22:12:43.618140 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2491 22:12:43.627807 [CA 0] Center 39 (9~70) winsize 62
2492 22:12:43.631512 [CA 1] Center 39 (9~70) winsize 62
2493 22:12:43.635155 [CA 2] Center 35 (5~66) winsize 62
2494 22:12:43.637718 [CA 3] Center 35 (5~66) winsize 62
2495 22:12:43.641110 [CA 4] Center 34 (4~65) winsize 62
2496 22:12:43.644115 [CA 5] Center 33 (3~64) winsize 62
2497 22:12:43.644578
2498 22:12:43.647549 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2499 22:12:43.647980
2500 22:12:43.650836 [CATrainingPosCal] consider 2 rank data
2501 22:12:43.654025 u2DelayCellTimex100 = 270/100 ps
2502 22:12:43.657408 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2503 22:12:43.664176 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2504 22:12:43.667538 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2505 22:12:43.671088 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2506 22:12:43.674505 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2507 22:12:43.677510 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2508 22:12:43.677941
2509 22:12:43.680655 CA PerBit enable=1, Macro0, CA PI delay=33
2510 22:12:43.681078
2511 22:12:43.684400 [CBTSetCACLKResult] CA Dly = 33
2512 22:12:43.684919 CS Dly: 8 (0~41)
2513 22:12:43.687568
2514 22:12:43.690939 ----->DramcWriteLeveling(PI) begin...
2515 22:12:43.691484 ==
2516 22:12:43.693792 Dram Type= 6, Freq= 0, CH_0, rank 0
2517 22:12:43.697205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2518 22:12:43.697633 ==
2519 22:12:43.701081 Write leveling (Byte 0): 33 => 33
2520 22:12:43.703857 Write leveling (Byte 1): 27 => 27
2521 22:12:43.706955 DramcWriteLeveling(PI) end<-----
2522 22:12:43.707565
2523 22:12:43.707914 ==
2524 22:12:43.710799 Dram Type= 6, Freq= 0, CH_0, rank 0
2525 22:12:43.713792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2526 22:12:43.714216 ==
2527 22:12:43.717471 [Gating] SW mode calibration
2528 22:12:43.723880 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2529 22:12:43.730563 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2530 22:12:43.733813 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2531 22:12:43.737274 0 15 4 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
2532 22:12:43.743847 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2533 22:12:43.747377 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2534 22:12:43.750239 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2535 22:12:43.756940 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2536 22:12:43.761042 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
2537 22:12:43.763627 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
2538 22:12:43.770106 1 0 0 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
2539 22:12:43.773374 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 22:12:43.776818 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 22:12:43.783734 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 22:12:43.787468 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2543 22:12:43.790008 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2544 22:12:43.797106 1 0 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
2545 22:12:43.799819 1 0 28 | B1->B0 | 2323 4646 | 1 0 | (0 0) (0 0)
2546 22:12:43.803209 1 1 0 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
2547 22:12:43.806836 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 22:12:43.813562 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 22:12:43.816646 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 22:12:43.820112 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 22:12:43.826550 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2552 22:12:43.829827 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2553 22:12:43.833612 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2554 22:12:43.841101 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2555 22:12:43.843803 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 22:12:43.846840 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 22:12:43.853425 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 22:12:43.856267 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 22:12:43.859700 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 22:12:43.866568 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 22:12:43.869792 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 22:12:43.873048 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 22:12:43.879469 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 22:12:43.882939 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 22:12:43.886239 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 22:12:43.893161 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 22:12:43.896724 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 22:12:43.899483 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 22:12:43.906471 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2570 22:12:43.909634 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2571 22:12:43.912784 Total UI for P1: 0, mck2ui 16
2572 22:12:43.915749 best dqsien dly found for B0: ( 1, 3, 28)
2573 22:12:43.919260 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2574 22:12:43.925958 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2575 22:12:43.926531 Total UI for P1: 0, mck2ui 16
2576 22:12:43.932888 best dqsien dly found for B1: ( 1, 4, 2)
2577 22:12:43.935876 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2578 22:12:43.939074 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2579 22:12:43.939585
2580 22:12:43.942459 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2581 22:12:43.945834 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2582 22:12:43.948621 [Gating] SW calibration Done
2583 22:12:43.949082 ==
2584 22:12:43.952275 Dram Type= 6, Freq= 0, CH_0, rank 0
2585 22:12:43.955525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2586 22:12:43.956115 ==
2587 22:12:43.958821 RX Vref Scan: 0
2588 22:12:43.959404
2589 22:12:43.959777 RX Vref 0 -> 0, step: 1
2590 22:12:43.960114
2591 22:12:43.961873 RX Delay -40 -> 252, step: 8
2592 22:12:43.965656 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2593 22:12:43.971986 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2594 22:12:43.975714 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2595 22:12:43.978523 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2596 22:12:43.981920 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2597 22:12:43.985252 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2598 22:12:43.991700 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2599 22:12:43.995295 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2600 22:12:43.998990 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2601 22:12:44.001978 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2602 22:12:44.005336 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2603 22:12:44.011694 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2604 22:12:44.015285 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2605 22:12:44.018497 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2606 22:12:44.021908 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2607 22:12:44.028391 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2608 22:12:44.028921 ==
2609 22:12:44.031708 Dram Type= 6, Freq= 0, CH_0, rank 0
2610 22:12:44.034883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2611 22:12:44.035367 ==
2612 22:12:44.035736 DQS Delay:
2613 22:12:44.038168 DQS0 = 0, DQS1 = 0
2614 22:12:44.038584 DQM Delay:
2615 22:12:44.041574 DQM0 = 117, DQM1 = 108
2616 22:12:44.042096 DQ Delay:
2617 22:12:44.044890 DQ0 =115, DQ1 =119, DQ2 =119, DQ3 =111
2618 22:12:44.047974 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
2619 22:12:44.051600 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2620 22:12:44.054340 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =115
2621 22:12:44.054780
2622 22:12:44.055117
2623 22:12:44.058218 ==
2624 22:12:44.058640 Dram Type= 6, Freq= 0, CH_0, rank 0
2625 22:12:44.064519 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2626 22:12:44.065054 ==
2627 22:12:44.065429
2628 22:12:44.065772
2629 22:12:44.067715 TX Vref Scan disable
2630 22:12:44.068258 == TX Byte 0 ==
2631 22:12:44.071532 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2632 22:12:44.077731 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2633 22:12:44.078290 == TX Byte 1 ==
2634 22:12:44.081276 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2635 22:12:44.088018 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2636 22:12:44.088442 ==
2637 22:12:44.091213 Dram Type= 6, Freq= 0, CH_0, rank 0
2638 22:12:44.094731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2639 22:12:44.095311 ==
2640 22:12:44.107499 TX Vref=22, minBit 1, minWin=25, winSum=409
2641 22:12:44.110226 TX Vref=24, minBit 8, minWin=25, winSum=419
2642 22:12:44.113885 TX Vref=26, minBit 1, minWin=26, winSum=421
2643 22:12:44.117592 TX Vref=28, minBit 10, minWin=25, winSum=426
2644 22:12:44.120111 TX Vref=30, minBit 1, minWin=26, winSum=431
2645 22:12:44.127295 TX Vref=32, minBit 10, minWin=26, winSum=431
2646 22:12:44.130032 [TxChooseVref] Worse bit 1, Min win 26, Win sum 431, Final Vref 30
2647 22:12:44.130518
2648 22:12:44.133438 Final TX Range 1 Vref 30
2649 22:12:44.133897
2650 22:12:44.134256 ==
2651 22:12:44.137075 Dram Type= 6, Freq= 0, CH_0, rank 0
2652 22:12:44.139928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2653 22:12:44.143341 ==
2654 22:12:44.143897
2655 22:12:44.144258
2656 22:12:44.144593 TX Vref Scan disable
2657 22:12:44.147331 == TX Byte 0 ==
2658 22:12:44.150118 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2659 22:12:44.156912 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2660 22:12:44.157371 == TX Byte 1 ==
2661 22:12:44.160511 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2662 22:12:44.167270 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2663 22:12:44.167818
2664 22:12:44.168177 [DATLAT]
2665 22:12:44.168512 Freq=1200, CH0 RK0
2666 22:12:44.168835
2667 22:12:44.169942 DATLAT Default: 0xd
2668 22:12:44.170411 0, 0xFFFF, sum = 0
2669 22:12:44.173597 1, 0xFFFF, sum = 0
2670 22:12:44.176844 2, 0xFFFF, sum = 0
2671 22:12:44.177308 3, 0xFFFF, sum = 0
2672 22:12:44.180322 4, 0xFFFF, sum = 0
2673 22:12:44.180789 5, 0xFFFF, sum = 0
2674 22:12:44.183420 6, 0xFFFF, sum = 0
2675 22:12:44.183884 7, 0xFFFF, sum = 0
2676 22:12:44.187216 8, 0xFFFF, sum = 0
2677 22:12:44.187631 9, 0xFFFF, sum = 0
2678 22:12:44.189833 10, 0xFFFF, sum = 0
2679 22:12:44.190252 11, 0xFFFF, sum = 0
2680 22:12:44.193466 12, 0x0, sum = 1
2681 22:12:44.193887 13, 0x0, sum = 2
2682 22:12:44.196882 14, 0x0, sum = 3
2683 22:12:44.197301 15, 0x0, sum = 4
2684 22:12:44.197634 best_step = 13
2685 22:12:44.200111
2686 22:12:44.200555 ==
2687 22:12:44.203313 Dram Type= 6, Freq= 0, CH_0, rank 0
2688 22:12:44.207007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2689 22:12:44.207656 ==
2690 22:12:44.207994 RX Vref Scan: 1
2691 22:12:44.208318
2692 22:12:44.209797 Set Vref Range= 32 -> 127
2693 22:12:44.210207
2694 22:12:44.213350 RX Vref 32 -> 127, step: 1
2695 22:12:44.213762
2696 22:12:44.216837 RX Delay -21 -> 252, step: 4
2697 22:12:44.217474
2698 22:12:44.219987 Set Vref, RX VrefLevel [Byte0]: 32
2699 22:12:44.223486 [Byte1]: 32
2700 22:12:44.224001
2701 22:12:44.227320 Set Vref, RX VrefLevel [Byte0]: 33
2702 22:12:44.230314 [Byte1]: 33
2703 22:12:44.233449
2704 22:12:44.233955 Set Vref, RX VrefLevel [Byte0]: 34
2705 22:12:44.236588 [Byte1]: 34
2706 22:12:44.241453
2707 22:12:44.241865 Set Vref, RX VrefLevel [Byte0]: 35
2708 22:12:44.244952 [Byte1]: 35
2709 22:12:44.249188
2710 22:12:44.249597 Set Vref, RX VrefLevel [Byte0]: 36
2711 22:12:44.253615 [Byte1]: 36
2712 22:12:44.257577
2713 22:12:44.258006 Set Vref, RX VrefLevel [Byte0]: 37
2714 22:12:44.261286 [Byte1]: 37
2715 22:12:44.264982
2716 22:12:44.265487 Set Vref, RX VrefLevel [Byte0]: 38
2717 22:12:44.268448 [Byte1]: 38
2718 22:12:44.273369
2719 22:12:44.273879 Set Vref, RX VrefLevel [Byte0]: 39
2720 22:12:44.276516 [Byte1]: 39
2721 22:12:44.280823
2722 22:12:44.281278 Set Vref, RX VrefLevel [Byte0]: 40
2723 22:12:44.284572 [Byte1]: 40
2724 22:12:44.289043
2725 22:12:44.289482 Set Vref, RX VrefLevel [Byte0]: 41
2726 22:12:44.292468 [Byte1]: 41
2727 22:12:44.296934
2728 22:12:44.297346 Set Vref, RX VrefLevel [Byte0]: 42
2729 22:12:44.300343 [Byte1]: 42
2730 22:12:44.304760
2731 22:12:44.305221 Set Vref, RX VrefLevel [Byte0]: 43
2732 22:12:44.307757 [Byte1]: 43
2733 22:12:44.313289
2734 22:12:44.313802 Set Vref, RX VrefLevel [Byte0]: 44
2735 22:12:44.315840 [Byte1]: 44
2736 22:12:44.320564
2737 22:12:44.321043 Set Vref, RX VrefLevel [Byte0]: 45
2738 22:12:44.323988 [Byte1]: 45
2739 22:12:44.329268
2740 22:12:44.329773 Set Vref, RX VrefLevel [Byte0]: 46
2741 22:12:44.331636 [Byte1]: 46
2742 22:12:44.336843
2743 22:12:44.337367 Set Vref, RX VrefLevel [Byte0]: 47
2744 22:12:44.339721 [Byte1]: 47
2745 22:12:44.344729
2746 22:12:44.345279 Set Vref, RX VrefLevel [Byte0]: 48
2747 22:12:44.348312 [Byte1]: 48
2748 22:12:44.352088
2749 22:12:44.352545 Set Vref, RX VrefLevel [Byte0]: 49
2750 22:12:44.356349 [Byte1]: 49
2751 22:12:44.360050
2752 22:12:44.360504 Set Vref, RX VrefLevel [Byte0]: 50
2753 22:12:44.363732 [Byte1]: 50
2754 22:12:44.368243
2755 22:12:44.368687 Set Vref, RX VrefLevel [Byte0]: 51
2756 22:12:44.371548 [Byte1]: 51
2757 22:12:44.376650
2758 22:12:44.377166 Set Vref, RX VrefLevel [Byte0]: 52
2759 22:12:44.379301 [Byte1]: 52
2760 22:12:44.384847
2761 22:12:44.385295 Set Vref, RX VrefLevel [Byte0]: 53
2762 22:12:44.388088 [Byte1]: 53
2763 22:12:44.391934
2764 22:12:44.392345 Set Vref, RX VrefLevel [Byte0]: 54
2765 22:12:44.395316 [Byte1]: 54
2766 22:12:44.399788
2767 22:12:44.400214 Set Vref, RX VrefLevel [Byte0]: 55
2768 22:12:44.403256 [Byte1]: 55
2769 22:12:44.407782
2770 22:12:44.408197 Set Vref, RX VrefLevel [Byte0]: 56
2771 22:12:44.410813 [Byte1]: 56
2772 22:12:44.415336
2773 22:12:44.415762 Set Vref, RX VrefLevel [Byte0]: 57
2774 22:12:44.418894 [Byte1]: 57
2775 22:12:44.423523
2776 22:12:44.423970 Set Vref, RX VrefLevel [Byte0]: 58
2777 22:12:44.427014 [Byte1]: 58
2778 22:12:44.431565
2779 22:12:44.432016 Set Vref, RX VrefLevel [Byte0]: 59
2780 22:12:44.435109 [Byte1]: 59
2781 22:12:44.439265
2782 22:12:44.439690 Set Vref, RX VrefLevel [Byte0]: 60
2783 22:12:44.442484 [Byte1]: 60
2784 22:12:44.447599
2785 22:12:44.448029 Set Vref, RX VrefLevel [Byte0]: 61
2786 22:12:44.451028 [Byte1]: 61
2787 22:12:44.455903
2788 22:12:44.456440 Set Vref, RX VrefLevel [Byte0]: 62
2789 22:12:44.458591 [Byte1]: 62
2790 22:12:44.463141
2791 22:12:44.463615 Set Vref, RX VrefLevel [Byte0]: 63
2792 22:12:44.466362 [Byte1]: 63
2793 22:12:44.471032
2794 22:12:44.471495 Set Vref, RX VrefLevel [Byte0]: 64
2795 22:12:44.474742 [Byte1]: 64
2796 22:12:44.479632
2797 22:12:44.480145 Set Vref, RX VrefLevel [Byte0]: 65
2798 22:12:44.482650 [Byte1]: 65
2799 22:12:44.486997
2800 22:12:44.487599 Set Vref, RX VrefLevel [Byte0]: 66
2801 22:12:44.490627 [Byte1]: 66
2802 22:12:44.495964
2803 22:12:44.496581 Set Vref, RX VrefLevel [Byte0]: 67
2804 22:12:44.498365 [Byte1]: 67
2805 22:12:44.502976
2806 22:12:44.503571 Final RX Vref Byte 0 = 51 to rank0
2807 22:12:44.506756 Final RX Vref Byte 1 = 59 to rank0
2808 22:12:44.509551 Final RX Vref Byte 0 = 51 to rank1
2809 22:12:44.513529 Final RX Vref Byte 1 = 59 to rank1==
2810 22:12:44.516357 Dram Type= 6, Freq= 0, CH_0, rank 0
2811 22:12:44.523148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2812 22:12:44.523754 ==
2813 22:12:44.524373 DQS Delay:
2814 22:12:44.524750 DQS0 = 0, DQS1 = 0
2815 22:12:44.526136 DQM Delay:
2816 22:12:44.526598 DQM0 = 117, DQM1 = 105
2817 22:12:44.529677 DQ Delay:
2818 22:12:44.532970 DQ0 =118, DQ1 =118, DQ2 =114, DQ3 =114
2819 22:12:44.536189 DQ4 =118, DQ5 =110, DQ6 =124, DQ7 =122
2820 22:12:44.539696 DQ8 =94, DQ9 =90, DQ10 =106, DQ11 =100
2821 22:12:44.543254 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =112
2822 22:12:44.543815
2823 22:12:44.544183
2824 22:12:44.549526 [DQSOSCAuto] RK0, (LSB)MR18= 0x3fe, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 408 ps
2825 22:12:44.553188 CH0 RK0: MR19=403, MR18=3FE
2826 22:12:44.559664 CH0_RK0: MR19=0x403, MR18=0x3FE, DQSOSC=408, MR23=63, INC=39, DEC=26
2827 22:12:44.560121
2828 22:12:44.563344 ----->DramcWriteLeveling(PI) begin...
2829 22:12:44.563805 ==
2830 22:12:44.566154 Dram Type= 6, Freq= 0, CH_0, rank 1
2831 22:12:44.569758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2832 22:12:44.572970 ==
2833 22:12:44.573541 Write leveling (Byte 0): 33 => 33
2834 22:12:44.576711 Write leveling (Byte 1): 25 => 25
2835 22:12:44.579312 DramcWriteLeveling(PI) end<-----
2836 22:12:44.579770
2837 22:12:44.580131 ==
2838 22:12:44.582979 Dram Type= 6, Freq= 0, CH_0, rank 1
2839 22:12:44.589345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2840 22:12:44.589900 ==
2841 22:12:44.592607 [Gating] SW mode calibration
2842 22:12:44.599291 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2843 22:12:44.602320 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2844 22:12:44.608916 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2845 22:12:44.612267 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2846 22:12:44.615474 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2847 22:12:44.622597 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2848 22:12:44.625418 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2849 22:12:44.628986 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2850 22:12:44.635425 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2851 22:12:44.639118 0 15 28 | B1->B0 | 3434 2525 | 0 0 | (0 1) (0 0)
2852 22:12:44.642168 1 0 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
2853 22:12:44.645810 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2854 22:12:44.652076 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2855 22:12:44.655514 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2856 22:12:44.658725 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2857 22:12:44.665511 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2858 22:12:44.668526 1 0 24 | B1->B0 | 2323 3d3d | 0 1 | (0 0) (0 0)
2859 22:12:44.672288 1 0 28 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
2860 22:12:44.679057 1 1 0 | B1->B0 | 4343 4646 | 1 0 | (0 0) (0 0)
2861 22:12:44.682587 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2862 22:12:44.685475 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2863 22:12:44.692423 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2864 22:12:44.695543 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2865 22:12:44.698523 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2866 22:12:44.706262 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2867 22:12:44.708625 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2868 22:12:44.711789 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 22:12:44.719155 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 22:12:44.722110 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 22:12:44.725256 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 22:12:44.732210 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 22:12:44.735402 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 22:12:44.738520 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 22:12:44.744992 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 22:12:44.748151 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 22:12:44.751624 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 22:12:44.758272 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 22:12:44.761408 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 22:12:44.764999 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 22:12:44.771747 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 22:12:44.774429 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2883 22:12:44.778028 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2884 22:12:44.784696 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2885 22:12:44.785263 Total UI for P1: 0, mck2ui 16
2886 22:12:44.791326 best dqsien dly found for B0: ( 1, 3, 26)
2887 22:12:44.794577 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2888 22:12:44.798049 Total UI for P1: 0, mck2ui 16
2889 22:12:44.801150 best dqsien dly found for B1: ( 1, 4, 0)
2890 22:12:44.804170 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2891 22:12:44.808034 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2892 22:12:44.808497
2893 22:12:44.811124 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2894 22:12:44.814673 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2895 22:12:44.817735 [Gating] SW calibration Done
2896 22:12:44.818286 ==
2897 22:12:44.821342 Dram Type= 6, Freq= 0, CH_0, rank 1
2898 22:12:44.824152 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2899 22:12:44.824615 ==
2900 22:12:44.827668 RX Vref Scan: 0
2901 22:12:44.828239
2902 22:12:44.831449 RX Vref 0 -> 0, step: 1
2903 22:12:44.832087
2904 22:12:44.832540 RX Delay -40 -> 252, step: 8
2905 22:12:44.837822 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2906 22:12:44.840822 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2907 22:12:44.844489 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2908 22:12:44.847395 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2909 22:12:44.850731 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2910 22:12:44.857561 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2911 22:12:44.860545 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2912 22:12:44.863947 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
2913 22:12:44.867677 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2914 22:12:44.870584 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2915 22:12:44.877542 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2916 22:12:44.880655 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2917 22:12:44.883991 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2918 22:12:44.887665 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2919 22:12:44.894129 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2920 22:12:44.897119 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2921 22:12:44.897588 ==
2922 22:12:44.900420 Dram Type= 6, Freq= 0, CH_0, rank 1
2923 22:12:44.903352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2924 22:12:44.903818 ==
2925 22:12:44.904185 DQS Delay:
2926 22:12:44.906987 DQS0 = 0, DQS1 = 0
2927 22:12:44.907568 DQM Delay:
2928 22:12:44.910229 DQM0 = 115, DQM1 = 109
2929 22:12:44.910746 DQ Delay:
2930 22:12:44.913952 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =115
2931 22:12:44.917116 DQ4 =119, DQ5 =103, DQ6 =127, DQ7 =119
2932 22:12:44.920297 DQ8 =99, DQ9 =91, DQ10 =111, DQ11 =103
2933 22:12:44.924022 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =115
2934 22:12:44.926858
2935 22:12:44.927449
2936 22:12:44.927820 ==
2937 22:12:44.930230 Dram Type= 6, Freq= 0, CH_0, rank 1
2938 22:12:44.934745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2939 22:12:44.935240 ==
2940 22:12:44.935611
2941 22:12:44.936007
2942 22:12:44.936824 TX Vref Scan disable
2943 22:12:44.937305 == TX Byte 0 ==
2944 22:12:44.943721 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2945 22:12:44.946675 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2946 22:12:44.947098 == TX Byte 1 ==
2947 22:12:44.953415 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2948 22:12:44.957158 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2949 22:12:44.957580 ==
2950 22:12:44.960343 Dram Type= 6, Freq= 0, CH_0, rank 1
2951 22:12:44.963352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2952 22:12:44.963782 ==
2953 22:12:44.976503 TX Vref=22, minBit 10, minWin=25, winSum=420
2954 22:12:44.979932 TX Vref=24, minBit 1, minWin=26, winSum=424
2955 22:12:44.983726 TX Vref=26, minBit 2, minWin=26, winSum=427
2956 22:12:44.986699 TX Vref=28, minBit 2, minWin=26, winSum=429
2957 22:12:44.990101 TX Vref=30, minBit 4, minWin=26, winSum=430
2958 22:12:44.997747 TX Vref=32, minBit 4, minWin=26, winSum=427
2959 22:12:44.999770 [TxChooseVref] Worse bit 4, Min win 26, Win sum 430, Final Vref 30
2960 22:12:45.000237
2961 22:12:45.003447 Final TX Range 1 Vref 30
2962 22:12:45.004013
2963 22:12:45.004383 ==
2964 22:12:45.007592 Dram Type= 6, Freq= 0, CH_0, rank 1
2965 22:12:45.009813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2966 22:12:45.010345 ==
2967 22:12:45.013316
2968 22:12:45.013869
2969 22:12:45.014234 TX Vref Scan disable
2970 22:12:45.016698 == TX Byte 0 ==
2971 22:12:45.020601 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2972 22:12:45.023127 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2973 22:12:45.026499 == TX Byte 1 ==
2974 22:12:45.030463 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2975 22:12:45.033231 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2976 22:12:45.036933
2977 22:12:45.037392 [DATLAT]
2978 22:12:45.037758 Freq=1200, CH0 RK1
2979 22:12:45.038100
2980 22:12:45.040439 DATLAT Default: 0xd
2981 22:12:45.040997 0, 0xFFFF, sum = 0
2982 22:12:45.043348 1, 0xFFFF, sum = 0
2983 22:12:45.043907 2, 0xFFFF, sum = 0
2984 22:12:45.046432 3, 0xFFFF, sum = 0
2985 22:12:45.049633 4, 0xFFFF, sum = 0
2986 22:12:45.050061 5, 0xFFFF, sum = 0
2987 22:12:45.052879 6, 0xFFFF, sum = 0
2988 22:12:45.053304 7, 0xFFFF, sum = 0
2989 22:12:45.056355 8, 0xFFFF, sum = 0
2990 22:12:45.056793 9, 0xFFFF, sum = 0
2991 22:12:45.059664 10, 0xFFFF, sum = 0
2992 22:12:45.060091 11, 0xFFFF, sum = 0
2993 22:12:45.062785 12, 0x0, sum = 1
2994 22:12:45.063263 13, 0x0, sum = 2
2995 22:12:45.066500 14, 0x0, sum = 3
2996 22:12:45.067024 15, 0x0, sum = 4
2997 22:12:45.069715 best_step = 13
2998 22:12:45.070225
2999 22:12:45.070564 ==
3000 22:12:45.072688 Dram Type= 6, Freq= 0, CH_0, rank 1
3001 22:12:45.075971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3002 22:12:45.076394 ==
3003 22:12:45.076755 RX Vref Scan: 0
3004 22:12:45.079865
3005 22:12:45.080284 RX Vref 0 -> 0, step: 1
3006 22:12:45.080660
3007 22:12:45.082678 RX Delay -21 -> 252, step: 4
3008 22:12:45.089538 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
3009 22:12:45.092777 iDelay=195, Bit 1, Center 116 (47 ~ 186) 140
3010 22:12:45.096128 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3011 22:12:45.099417 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3012 22:12:45.102855 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3013 22:12:45.109537 iDelay=195, Bit 5, Center 106 (39 ~ 174) 136
3014 22:12:45.112631 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3015 22:12:45.116094 iDelay=195, Bit 7, Center 120 (55 ~ 186) 132
3016 22:12:45.118970 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3017 22:12:45.122744 iDelay=195, Bit 9, Center 92 (27 ~ 158) 132
3018 22:12:45.125832 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3019 22:12:45.132430 iDelay=195, Bit 11, Center 102 (35 ~ 170) 136
3020 22:12:45.136102 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3021 22:12:45.139153 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3022 22:12:45.142436 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3023 22:12:45.149152 iDelay=195, Bit 15, Center 112 (47 ~ 178) 132
3024 22:12:45.149689 ==
3025 22:12:45.152208 Dram Type= 6, Freq= 0, CH_0, rank 1
3026 22:12:45.155783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3027 22:12:45.156376 ==
3028 22:12:45.156751 DQS Delay:
3029 22:12:45.158920 DQS0 = 0, DQS1 = 0
3030 22:12:45.159626 DQM Delay:
3031 22:12:45.162424 DQM0 = 115, DQM1 = 106
3032 22:12:45.162887 DQ Delay:
3033 22:12:45.165320 DQ0 =114, DQ1 =116, DQ2 =110, DQ3 =112
3034 22:12:45.168854 DQ4 =118, DQ5 =106, DQ6 =126, DQ7 =120
3035 22:12:45.171968 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =102
3036 22:12:45.175229 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =112
3037 22:12:45.175695
3038 22:12:45.176060
3039 22:12:45.185372 [DQSOSCAuto] RK1, (LSB)MR18= 0x1fe, (MSB)MR19= 0x403, tDQSOscB0 = 410 ps tDQSOscB1 = 409 ps
3040 22:12:45.189120 CH0 RK1: MR19=403, MR18=1FE
3041 22:12:45.192306 CH0_RK1: MR19=0x403, MR18=0x1FE, DQSOSC=409, MR23=63, INC=39, DEC=26
3042 22:12:45.196325 [RxdqsGatingPostProcess] freq 1200
3043 22:12:45.202130 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3044 22:12:45.205566 best DQS0 dly(2T, 0.5T) = (0, 11)
3045 22:12:45.209284 best DQS1 dly(2T, 0.5T) = (0, 12)
3046 22:12:45.211805 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3047 22:12:45.215723 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3048 22:12:45.219147 best DQS0 dly(2T, 0.5T) = (0, 11)
3049 22:12:45.222336 best DQS1 dly(2T, 0.5T) = (0, 12)
3050 22:12:45.225978 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3051 22:12:45.228457 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3052 22:12:45.228916 Pre-setting of DQS Precalculation
3053 22:12:45.235652 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3054 22:12:45.236207 ==
3055 22:12:45.239020 Dram Type= 6, Freq= 0, CH_1, rank 0
3056 22:12:45.242187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3057 22:12:45.242744 ==
3058 22:12:45.248583 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3059 22:12:45.255072 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3060 22:12:45.262701 [CA 0] Center 38 (8~68) winsize 61
3061 22:12:45.266086 [CA 1] Center 37 (7~68) winsize 62
3062 22:12:45.269255 [CA 2] Center 35 (5~65) winsize 61
3063 22:12:45.272556 [CA 3] Center 33 (3~64) winsize 62
3064 22:12:45.275793 [CA 4] Center 34 (4~65) winsize 62
3065 22:12:45.279110 [CA 5] Center 33 (3~63) winsize 61
3066 22:12:45.279697
3067 22:12:45.282464 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3068 22:12:45.282921
3069 22:12:45.286103 [CATrainingPosCal] consider 1 rank data
3070 22:12:45.289217 u2DelayCellTimex100 = 270/100 ps
3071 22:12:45.292526 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3072 22:12:45.295885 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3073 22:12:45.303235 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3074 22:12:45.305812 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3075 22:12:45.308770 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3076 22:12:45.312906 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3077 22:12:45.313362
3078 22:12:45.315907 CA PerBit enable=1, Macro0, CA PI delay=33
3079 22:12:45.316463
3080 22:12:45.319501 [CBTSetCACLKResult] CA Dly = 33
3081 22:12:45.322496 CS Dly: 5 (0~36)
3082 22:12:45.323049 ==
3083 22:12:45.325690 Dram Type= 6, Freq= 0, CH_1, rank 1
3084 22:12:45.328552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3085 22:12:45.329011 ==
3086 22:12:45.335414 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3087 22:12:45.338725 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3088 22:12:45.348280 [CA 0] Center 37 (7~68) winsize 62
3089 22:12:45.351560 [CA 1] Center 38 (8~68) winsize 61
3090 22:12:45.355102 [CA 2] Center 34 (4~65) winsize 62
3091 22:12:45.357888 [CA 3] Center 33 (3~64) winsize 62
3092 22:12:45.361839 [CA 4] Center 34 (4~64) winsize 61
3093 22:12:45.365061 [CA 5] Center 33 (3~63) winsize 61
3094 22:12:45.365621
3095 22:12:45.368407 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3096 22:12:45.368963
3097 22:12:45.371333 [CATrainingPosCal] consider 2 rank data
3098 22:12:45.374482 u2DelayCellTimex100 = 270/100 ps
3099 22:12:45.378137 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3100 22:12:45.385126 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3101 22:12:45.388372 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3102 22:12:45.391790 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3103 22:12:45.394630 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3104 22:12:45.398061 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3105 22:12:45.398617
3106 22:12:45.401275 CA PerBit enable=1, Macro0, CA PI delay=33
3107 22:12:45.401836
3108 22:12:45.404355 [CBTSetCACLKResult] CA Dly = 33
3109 22:12:45.404810 CS Dly: 6 (0~39)
3110 22:12:45.407899
3111 22:12:45.411085 ----->DramcWriteLeveling(PI) begin...
3112 22:12:45.411660 ==
3113 22:12:45.414380 Dram Type= 6, Freq= 0, CH_1, rank 0
3114 22:12:45.417754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3115 22:12:45.418333 ==
3116 22:12:45.420838 Write leveling (Byte 0): 26 => 26
3117 22:12:45.424288 Write leveling (Byte 1): 27 => 27
3118 22:12:45.427746 DramcWriteLeveling(PI) end<-----
3119 22:12:45.428159
3120 22:12:45.428482 ==
3121 22:12:45.431715 Dram Type= 6, Freq= 0, CH_1, rank 0
3122 22:12:45.434162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3123 22:12:45.434580 ==
3124 22:12:45.437823 [Gating] SW mode calibration
3125 22:12:45.444537 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3126 22:12:45.450978 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3127 22:12:45.454674 0 15 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
3128 22:12:45.457404 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3129 22:12:45.464453 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3130 22:12:45.467472 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3131 22:12:45.471558 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3132 22:12:45.477786 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3133 22:12:45.480719 0 15 24 | B1->B0 | 3434 3131 | 1 0 | (1 0) (0 0)
3134 22:12:45.483925 0 15 28 | B1->B0 | 2c2c 2727 | 0 0 | (0 1) (0 0)
3135 22:12:45.490834 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3136 22:12:45.494171 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3137 22:12:45.497411 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3138 22:12:45.503996 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3139 22:12:45.507079 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3140 22:12:45.510515 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3141 22:12:45.517332 1 0 24 | B1->B0 | 2424 2a2a | 0 1 | (0 0) (1 1)
3142 22:12:45.520848 1 0 28 | B1->B0 | 3c3c 4545 | 0 1 | (0 0) (0 0)
3143 22:12:45.524679 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3144 22:12:45.527828 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3145 22:12:45.534131 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3146 22:12:45.537550 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3147 22:12:45.540255 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3148 22:12:45.547448 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3149 22:12:45.550313 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3150 22:12:45.554144 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3151 22:12:45.560190 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3152 22:12:45.564108 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 22:12:45.567359 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 22:12:45.573607 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 22:12:45.577618 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 22:12:45.579945 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 22:12:45.586965 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 22:12:45.591034 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 22:12:45.593524 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 22:12:45.600218 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 22:12:45.604145 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 22:12:45.606725 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 22:12:45.613279 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 22:12:45.616846 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 22:12:45.620153 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 22:12:45.626974 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3167 22:12:45.630587 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3168 22:12:45.633697 Total UI for P1: 0, mck2ui 16
3169 22:12:45.637081 best dqsien dly found for B0: ( 1, 3, 28)
3170 22:12:45.639891 Total UI for P1: 0, mck2ui 16
3171 22:12:45.643370 best dqsien dly found for B1: ( 1, 3, 28)
3172 22:12:45.646915 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3173 22:12:45.650136 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3174 22:12:45.650705
3175 22:12:45.653462 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3176 22:12:45.656505 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3177 22:12:45.660258 [Gating] SW calibration Done
3178 22:12:45.660737 ==
3179 22:12:45.663094 Dram Type= 6, Freq= 0, CH_1, rank 0
3180 22:12:45.667081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3181 22:12:45.667724 ==
3182 22:12:45.670268 RX Vref Scan: 0
3183 22:12:45.670835
3184 22:12:45.673308 RX Vref 0 -> 0, step: 1
3185 22:12:45.673784
3186 22:12:45.674258 RX Delay -40 -> 252, step: 8
3187 22:12:45.680039 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3188 22:12:45.683600 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3189 22:12:45.687112 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3190 22:12:45.690438 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3191 22:12:45.693646 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3192 22:12:45.700168 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3193 22:12:45.703854 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3194 22:12:45.707263 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3195 22:12:45.710096 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3196 22:12:45.713230 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3197 22:12:45.719954 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3198 22:12:45.723331 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3199 22:12:45.726926 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3200 22:12:45.730700 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3201 22:12:45.733427 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3202 22:12:45.740627 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3203 22:12:45.741194 ==
3204 22:12:45.742879 Dram Type= 6, Freq= 0, CH_1, rank 0
3205 22:12:45.746764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3206 22:12:45.747429 ==
3207 22:12:45.747918 DQS Delay:
3208 22:12:45.749773 DQS0 = 0, DQS1 = 0
3209 22:12:45.750246 DQM Delay:
3210 22:12:45.753514 DQM0 = 116, DQM1 = 112
3211 22:12:45.754083 DQ Delay:
3212 22:12:45.756725 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =115
3213 22:12:45.760196 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =115
3214 22:12:45.762707 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3215 22:12:45.766815 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3216 22:12:45.767409
3217 22:12:45.770137
3218 22:12:45.770686 ==
3219 22:12:45.772967 Dram Type= 6, Freq= 0, CH_1, rank 0
3220 22:12:45.776544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3221 22:12:45.777104 ==
3222 22:12:45.777469
3223 22:12:45.777806
3224 22:12:45.779775 TX Vref Scan disable
3225 22:12:45.780232 == TX Byte 0 ==
3226 22:12:45.786224 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3227 22:12:45.789724 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3228 22:12:45.790292 == TX Byte 1 ==
3229 22:12:45.796381 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3230 22:12:45.799661 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3231 22:12:45.800217 ==
3232 22:12:45.802804 Dram Type= 6, Freq= 0, CH_1, rank 0
3233 22:12:45.806282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3234 22:12:45.806859 ==
3235 22:12:45.818563 TX Vref=22, minBit 0, minWin=25, winSum=409
3236 22:12:45.822022 TX Vref=24, minBit 2, minWin=25, winSum=416
3237 22:12:45.824873 TX Vref=26, minBit 0, minWin=25, winSum=419
3238 22:12:45.828326 TX Vref=28, minBit 1, minWin=26, winSum=426
3239 22:12:45.831658 TX Vref=30, minBit 1, minWin=25, winSum=423
3240 22:12:45.838350 TX Vref=32, minBit 0, minWin=26, winSum=427
3241 22:12:45.841539 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 32
3242 22:12:45.842092
3243 22:12:45.844899 Final TX Range 1 Vref 32
3244 22:12:45.845455
3245 22:12:45.845820 ==
3246 22:12:45.848102 Dram Type= 6, Freq= 0, CH_1, rank 0
3247 22:12:45.851382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3248 22:12:45.851843 ==
3249 22:12:45.854757
3250 22:12:45.855332
3251 22:12:45.855703 TX Vref Scan disable
3252 22:12:45.858268 == TX Byte 0 ==
3253 22:12:45.861033 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3254 22:12:45.867529 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3255 22:12:45.868076 == TX Byte 1 ==
3256 22:12:45.871302 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3257 22:12:45.878437 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3258 22:12:45.878992
3259 22:12:45.879401 [DATLAT]
3260 22:12:45.879741 Freq=1200, CH1 RK0
3261 22:12:45.880070
3262 22:12:45.881178 DATLAT Default: 0xd
3263 22:12:45.881641 0, 0xFFFF, sum = 0
3264 22:12:45.884191 1, 0xFFFF, sum = 0
3265 22:12:45.884681 2, 0xFFFF, sum = 0
3266 22:12:45.887738 3, 0xFFFF, sum = 0
3267 22:12:45.891125 4, 0xFFFF, sum = 0
3268 22:12:45.891662 5, 0xFFFF, sum = 0
3269 22:12:45.894300 6, 0xFFFF, sum = 0
3270 22:12:45.894720 7, 0xFFFF, sum = 0
3271 22:12:45.898058 8, 0xFFFF, sum = 0
3272 22:12:45.898478 9, 0xFFFF, sum = 0
3273 22:12:45.901781 10, 0xFFFF, sum = 0
3274 22:12:45.902296 11, 0xFFFF, sum = 0
3275 22:12:45.904069 12, 0x0, sum = 1
3276 22:12:45.904491 13, 0x0, sum = 2
3277 22:12:45.907951 14, 0x0, sum = 3
3278 22:12:45.908505 15, 0x0, sum = 4
3279 22:12:45.911032 best_step = 13
3280 22:12:45.911478
3281 22:12:45.911886 ==
3282 22:12:45.914765 Dram Type= 6, Freq= 0, CH_1, rank 0
3283 22:12:45.917678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3284 22:12:45.918185 ==
3285 22:12:45.918517 RX Vref Scan: 1
3286 22:12:45.918836
3287 22:12:45.921038 Set Vref Range= 32 -> 127
3288 22:12:45.921543
3289 22:12:45.924752 RX Vref 32 -> 127, step: 1
3290 22:12:45.925258
3291 22:12:45.927859 RX Delay -13 -> 252, step: 4
3292 22:12:45.928361
3293 22:12:45.930836 Set Vref, RX VrefLevel [Byte0]: 32
3294 22:12:45.934542 [Byte1]: 32
3295 22:12:45.935042
3296 22:12:45.937240 Set Vref, RX VrefLevel [Byte0]: 33
3297 22:12:45.940887 [Byte1]: 33
3298 22:12:45.944053
3299 22:12:45.944465 Set Vref, RX VrefLevel [Byte0]: 34
3300 22:12:45.947776 [Byte1]: 34
3301 22:12:45.952212
3302 22:12:45.952709 Set Vref, RX VrefLevel [Byte0]: 35
3303 22:12:45.955792 [Byte1]: 35
3304 22:12:45.960602
3305 22:12:45.961103 Set Vref, RX VrefLevel [Byte0]: 36
3306 22:12:45.963092 [Byte1]: 36
3307 22:12:45.968385
3308 22:12:45.968952 Set Vref, RX VrefLevel [Byte0]: 37
3309 22:12:45.971072 [Byte1]: 37
3310 22:12:45.975816
3311 22:12:45.976259 Set Vref, RX VrefLevel [Byte0]: 38
3312 22:12:45.979207 [Byte1]: 38
3313 22:12:45.983910
3314 22:12:45.984309 Set Vref, RX VrefLevel [Byte0]: 39
3315 22:12:45.986911 [Byte1]: 39
3316 22:12:45.991485
3317 22:12:45.991886 Set Vref, RX VrefLevel [Byte0]: 40
3318 22:12:45.995351 [Byte1]: 40
3319 22:12:45.999699
3320 22:12:46.000190 Set Vref, RX VrefLevel [Byte0]: 41
3321 22:12:46.002650 [Byte1]: 41
3322 22:12:46.007815
3323 22:12:46.008313 Set Vref, RX VrefLevel [Byte0]: 42
3324 22:12:46.010925 [Byte1]: 42
3325 22:12:46.015136
3326 22:12:46.015577 Set Vref, RX VrefLevel [Byte0]: 43
3327 22:12:46.018576 [Byte1]: 43
3328 22:12:46.023373
3329 22:12:46.023909 Set Vref, RX VrefLevel [Byte0]: 44
3330 22:12:46.026746 [Byte1]: 44
3331 22:12:46.031087
3332 22:12:46.031582 Set Vref, RX VrefLevel [Byte0]: 45
3333 22:12:46.034583 [Byte1]: 45
3334 22:12:46.038759
3335 22:12:46.039350 Set Vref, RX VrefLevel [Byte0]: 46
3336 22:12:46.042543 [Byte1]: 46
3337 22:12:46.047117
3338 22:12:46.047697 Set Vref, RX VrefLevel [Byte0]: 47
3339 22:12:46.050280 [Byte1]: 47
3340 22:12:46.054646
3341 22:12:46.055221 Set Vref, RX VrefLevel [Byte0]: 48
3342 22:12:46.058045 [Byte1]: 48
3343 22:12:46.062354
3344 22:12:46.062800 Set Vref, RX VrefLevel [Byte0]: 49
3345 22:12:46.065955 [Byte1]: 49
3346 22:12:46.070243
3347 22:12:46.070710 Set Vref, RX VrefLevel [Byte0]: 50
3348 22:12:46.073926 [Byte1]: 50
3349 22:12:46.078902
3350 22:12:46.079488 Set Vref, RX VrefLevel [Byte0]: 51
3351 22:12:46.081792 [Byte1]: 51
3352 22:12:46.086608
3353 22:12:46.087148 Set Vref, RX VrefLevel [Byte0]: 52
3354 22:12:46.089960 [Byte1]: 52
3355 22:12:46.094290
3356 22:12:46.094827 Set Vref, RX VrefLevel [Byte0]: 53
3357 22:12:46.097830 [Byte1]: 53
3358 22:12:46.101913
3359 22:12:46.102452 Set Vref, RX VrefLevel [Byte0]: 54
3360 22:12:46.105552 [Byte1]: 54
3361 22:12:46.110248
3362 22:12:46.110790 Set Vref, RX VrefLevel [Byte0]: 55
3363 22:12:46.112961 [Byte1]: 55
3364 22:12:46.118072
3365 22:12:46.118613 Set Vref, RX VrefLevel [Byte0]: 56
3366 22:12:46.121116 [Byte1]: 56
3367 22:12:46.125868
3368 22:12:46.126410 Set Vref, RX VrefLevel [Byte0]: 57
3369 22:12:46.129073 [Byte1]: 57
3370 22:12:46.133675
3371 22:12:46.134214 Set Vref, RX VrefLevel [Byte0]: 58
3372 22:12:46.136872 [Byte1]: 58
3373 22:12:46.141556
3374 22:12:46.142015 Set Vref, RX VrefLevel [Byte0]: 59
3375 22:12:46.144524 [Byte1]: 59
3376 22:12:46.149483
3377 22:12:46.150114 Set Vref, RX VrefLevel [Byte0]: 60
3378 22:12:46.152659 [Byte1]: 60
3379 22:12:46.156919
3380 22:12:46.157373 Set Vref, RX VrefLevel [Byte0]: 61
3381 22:12:46.160486 [Byte1]: 61
3382 22:12:46.164940
3383 22:12:46.165385 Set Vref, RX VrefLevel [Byte0]: 62
3384 22:12:46.169164 [Byte1]: 62
3385 22:12:46.173225
3386 22:12:46.173721 Set Vref, RX VrefLevel [Byte0]: 63
3387 22:12:46.175887 [Byte1]: 63
3388 22:12:46.180563
3389 22:12:46.181054 Set Vref, RX VrefLevel [Byte0]: 64
3390 22:12:46.184514 [Byte1]: 64
3391 22:12:46.188518
3392 22:12:46.188976 Set Vref, RX VrefLevel [Byte0]: 65
3393 22:12:46.191914 [Byte1]: 65
3394 22:12:46.196774
3395 22:12:46.197334 Set Vref, RX VrefLevel [Byte0]: 66
3396 22:12:46.199636 [Byte1]: 66
3397 22:12:46.204250
3398 22:12:46.204710 Final RX Vref Byte 0 = 45 to rank0
3399 22:12:46.208500 Final RX Vref Byte 1 = 53 to rank0
3400 22:12:46.211576 Final RX Vref Byte 0 = 45 to rank1
3401 22:12:46.214205 Final RX Vref Byte 1 = 53 to rank1==
3402 22:12:46.218011 Dram Type= 6, Freq= 0, CH_1, rank 0
3403 22:12:46.224886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3404 22:12:46.225453 ==
3405 22:12:46.225828 DQS Delay:
3406 22:12:46.227362 DQS0 = 0, DQS1 = 0
3407 22:12:46.227824 DQM Delay:
3408 22:12:46.228194 DQM0 = 114, DQM1 = 112
3409 22:12:46.230682 DQ Delay:
3410 22:12:46.234155 DQ0 =122, DQ1 =110, DQ2 =106, DQ3 =114
3411 22:12:46.237927 DQ4 =110, DQ5 =122, DQ6 =124, DQ7 =110
3412 22:12:46.241219 DQ8 =98, DQ9 =102, DQ10 =114, DQ11 =106
3413 22:12:46.243901 DQ12 =120, DQ13 =120, DQ14 =120, DQ15 =122
3414 22:12:46.244363
3415 22:12:46.244729
3416 22:12:46.254063 [DQSOSCAuto] RK0, (LSB)MR18= 0xf804, (MSB)MR19= 0x304, tDQSOscB0 = 408 ps tDQSOscB1 = 413 ps
3417 22:12:46.254622 CH1 RK0: MR19=304, MR18=F804
3418 22:12:46.261003 CH1_RK0: MR19=0x304, MR18=0xF804, DQSOSC=408, MR23=63, INC=39, DEC=26
3419 22:12:46.261602
3420 22:12:46.263845 ----->DramcWriteLeveling(PI) begin...
3421 22:12:46.264318 ==
3422 22:12:46.267253 Dram Type= 6, Freq= 0, CH_1, rank 1
3423 22:12:46.273815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3424 22:12:46.274254 ==
3425 22:12:46.277622 Write leveling (Byte 0): 25 => 25
3426 22:12:46.278181 Write leveling (Byte 1): 28 => 28
3427 22:12:46.280302 DramcWriteLeveling(PI) end<-----
3428 22:12:46.280764
3429 22:12:46.283708 ==
3430 22:12:46.287846 Dram Type= 6, Freq= 0, CH_1, rank 1
3431 22:12:46.290734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3432 22:12:46.291152 ==
3433 22:12:46.294234 [Gating] SW mode calibration
3434 22:12:46.300874 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3435 22:12:46.303893 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3436 22:12:46.310313 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3437 22:12:46.313837 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3438 22:12:46.317103 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3439 22:12:46.323856 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3440 22:12:46.327125 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3441 22:12:46.330416 0 15 20 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
3442 22:12:46.336849 0 15 24 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 0)
3443 22:12:46.340266 0 15 28 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
3444 22:12:46.343629 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3445 22:12:46.350266 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3446 22:12:46.353728 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3447 22:12:46.356784 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3448 22:12:46.363342 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3449 22:12:46.366561 1 0 20 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
3450 22:12:46.370199 1 0 24 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
3451 22:12:46.376707 1 0 28 | B1->B0 | 3939 4646 | 0 0 | (1 1) (0 0)
3452 22:12:46.380152 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3453 22:12:46.383201 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3454 22:12:46.389863 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3455 22:12:46.393080 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3456 22:12:46.396454 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3457 22:12:46.403284 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3458 22:12:46.406210 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3459 22:12:46.409714 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3460 22:12:46.416060 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 22:12:46.419666 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 22:12:46.422818 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 22:12:46.429343 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 22:12:46.432399 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 22:12:46.435394 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 22:12:46.442870 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 22:12:46.445405 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 22:12:46.448692 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 22:12:46.455730 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 22:12:46.458740 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 22:12:46.461753 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 22:12:46.468734 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 22:12:46.472085 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 22:12:46.474972 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3475 22:12:46.481481 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3476 22:12:46.482042 Total UI for P1: 0, mck2ui 16
3477 22:12:46.488562 best dqsien dly found for B0: ( 1, 3, 24)
3478 22:12:46.489191 Total UI for P1: 0, mck2ui 16
3479 22:12:46.495148 best dqsien dly found for B1: ( 1, 3, 26)
3480 22:12:46.498703 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3481 22:12:46.501638 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3482 22:12:46.502204
3483 22:12:46.505206 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3484 22:12:46.508748 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3485 22:12:46.511463 [Gating] SW calibration Done
3486 22:12:46.511928 ==
3487 22:12:46.514361 Dram Type= 6, Freq= 0, CH_1, rank 1
3488 22:12:46.517921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3489 22:12:46.518388 ==
3490 22:12:46.521545 RX Vref Scan: 0
3491 22:12:46.522009
3492 22:12:46.524654 RX Vref 0 -> 0, step: 1
3493 22:12:46.525115
3494 22:12:46.525479 RX Delay -40 -> 252, step: 8
3495 22:12:46.530825 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3496 22:12:46.534544 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3497 22:12:46.537546 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3498 22:12:46.540481 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3499 22:12:46.544342 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3500 22:12:46.550779 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3501 22:12:46.553951 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3502 22:12:46.557807 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3503 22:12:46.560775 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3504 22:12:46.564143 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3505 22:12:46.570366 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3506 22:12:46.573878 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3507 22:12:46.577224 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3508 22:12:46.580152 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3509 22:12:46.586542 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3510 22:12:46.589887 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3511 22:12:46.590366 ==
3512 22:12:46.593190 Dram Type= 6, Freq= 0, CH_1, rank 1
3513 22:12:46.596764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3514 22:12:46.597199 ==
3515 22:12:46.599904 DQS Delay:
3516 22:12:46.600339 DQS0 = 0, DQS1 = 0
3517 22:12:46.600684 DQM Delay:
3518 22:12:46.603608 DQM0 = 114, DQM1 = 111
3519 22:12:46.604020 DQ Delay:
3520 22:12:46.606692 DQ0 =119, DQ1 =107, DQ2 =103, DQ3 =111
3521 22:12:46.609838 DQ4 =115, DQ5 =123, DQ6 =119, DQ7 =115
3522 22:12:46.613481 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3523 22:12:46.620560 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3524 22:12:46.621028
3525 22:12:46.621435
3526 22:12:46.621755 ==
3527 22:12:46.623296 Dram Type= 6, Freq= 0, CH_1, rank 1
3528 22:12:46.626492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3529 22:12:46.626922 ==
3530 22:12:46.627503
3531 22:12:46.627902
3532 22:12:46.630209 TX Vref Scan disable
3533 22:12:46.630716 == TX Byte 0 ==
3534 22:12:46.636314 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3535 22:12:46.639714 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3536 22:12:46.642778 == TX Byte 1 ==
3537 22:12:46.645892 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3538 22:12:46.649251 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3539 22:12:46.649668 ==
3540 22:12:46.652874 Dram Type= 6, Freq= 0, CH_1, rank 1
3541 22:12:46.655851 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3542 22:12:46.659263 ==
3543 22:12:46.669176 TX Vref=22, minBit 7, minWin=25, winSum=421
3544 22:12:46.672970 TX Vref=24, minBit 0, minWin=26, winSum=427
3545 22:12:46.675626 TX Vref=26, minBit 9, minWin=25, winSum=430
3546 22:12:46.679151 TX Vref=28, minBit 0, minWin=26, winSum=431
3547 22:12:46.682555 TX Vref=30, minBit 0, minWin=26, winSum=430
3548 22:12:46.689033 TX Vref=32, minBit 0, minWin=26, winSum=430
3549 22:12:46.691964 [TxChooseVref] Worse bit 0, Min win 26, Win sum 431, Final Vref 28
3550 22:12:46.692433
3551 22:12:46.695204 Final TX Range 1 Vref 28
3552 22:12:46.695623
3553 22:12:46.696034 ==
3554 22:12:46.699308 Dram Type= 6, Freq= 0, CH_1, rank 1
3555 22:12:46.706040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3556 22:12:46.706528 ==
3557 22:12:46.706958
3558 22:12:46.707382
3559 22:12:46.707768 TX Vref Scan disable
3560 22:12:46.709519 == TX Byte 0 ==
3561 22:12:46.712172 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3562 22:12:46.718823 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3563 22:12:46.719273 == TX Byte 1 ==
3564 22:12:46.722116 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3565 22:12:46.728541 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3566 22:12:46.728960
3567 22:12:46.729411 [DATLAT]
3568 22:12:46.729728 Freq=1200, CH1 RK1
3569 22:12:46.730112
3570 22:12:46.732029 DATLAT Default: 0xd
3571 22:12:46.734961 0, 0xFFFF, sum = 0
3572 22:12:46.735468 1, 0xFFFF, sum = 0
3573 22:12:46.738795 2, 0xFFFF, sum = 0
3574 22:12:46.739299 3, 0xFFFF, sum = 0
3575 22:12:46.741587 4, 0xFFFF, sum = 0
3576 22:12:46.742066 5, 0xFFFF, sum = 0
3577 22:12:46.745315 6, 0xFFFF, sum = 0
3578 22:12:46.745772 7, 0xFFFF, sum = 0
3579 22:12:46.748570 8, 0xFFFF, sum = 0
3580 22:12:46.749064 9, 0xFFFF, sum = 0
3581 22:12:46.751397 10, 0xFFFF, sum = 0
3582 22:12:46.751883 11, 0xFFFF, sum = 0
3583 22:12:46.754759 12, 0x0, sum = 1
3584 22:12:46.755251 13, 0x0, sum = 2
3585 22:12:46.758050 14, 0x0, sum = 3
3586 22:12:46.758466 15, 0x0, sum = 4
3587 22:12:46.761774 best_step = 13
3588 22:12:46.762345
3589 22:12:46.762735 ==
3590 22:12:46.764777 Dram Type= 6, Freq= 0, CH_1, rank 1
3591 22:12:46.768215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3592 22:12:46.768654 ==
3593 22:12:46.771575 RX Vref Scan: 0
3594 22:12:46.772056
3595 22:12:46.772429 RX Vref 0 -> 0, step: 1
3596 22:12:46.772976
3597 22:12:46.774719 RX Delay -13 -> 252, step: 4
3598 22:12:46.781706 iDelay=191, Bit 0, Center 118 (51 ~ 186) 136
3599 22:12:46.784474 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3600 22:12:46.787656 iDelay=191, Bit 2, Center 104 (39 ~ 170) 132
3601 22:12:46.790728 iDelay=191, Bit 3, Center 112 (43 ~ 182) 140
3602 22:12:46.797377 iDelay=191, Bit 4, Center 114 (47 ~ 182) 136
3603 22:12:46.800643 iDelay=191, Bit 5, Center 120 (51 ~ 190) 140
3604 22:12:46.803955 iDelay=191, Bit 6, Center 120 (55 ~ 186) 132
3605 22:12:46.807497 iDelay=191, Bit 7, Center 110 (43 ~ 178) 136
3606 22:12:46.810927 iDelay=191, Bit 8, Center 98 (35 ~ 162) 128
3607 22:12:46.817173 iDelay=191, Bit 9, Center 100 (35 ~ 166) 132
3608 22:12:46.820765 iDelay=191, Bit 10, Center 114 (51 ~ 178) 128
3609 22:12:46.824138 iDelay=191, Bit 11, Center 106 (43 ~ 170) 128
3610 22:12:46.827332 iDelay=191, Bit 12, Center 120 (59 ~ 182) 124
3611 22:12:46.831410 iDelay=191, Bit 13, Center 118 (55 ~ 182) 128
3612 22:12:46.837452 iDelay=191, Bit 14, Center 116 (55 ~ 178) 124
3613 22:12:46.840559 iDelay=191, Bit 15, Center 120 (55 ~ 186) 132
3614 22:12:46.840972 ==
3615 22:12:46.843326 Dram Type= 6, Freq= 0, CH_1, rank 1
3616 22:12:46.846805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3617 22:12:46.847243 ==
3618 22:12:46.850399 DQS Delay:
3619 22:12:46.850830 DQS0 = 0, DQS1 = 0
3620 22:12:46.851156 DQM Delay:
3621 22:12:46.853458 DQM0 = 113, DQM1 = 111
3622 22:12:46.853869 DQ Delay:
3623 22:12:46.857689 DQ0 =118, DQ1 =110, DQ2 =104, DQ3 =112
3624 22:12:46.859973 DQ4 =114, DQ5 =120, DQ6 =120, DQ7 =110
3625 22:12:46.866575 DQ8 =98, DQ9 =100, DQ10 =114, DQ11 =106
3626 22:12:46.870091 DQ12 =120, DQ13 =118, DQ14 =116, DQ15 =120
3627 22:12:46.870504
3628 22:12:46.870827
3629 22:12:46.876394 [DQSOSCAuto] RK1, (LSB)MR18= 0xfc0d, (MSB)MR19= 0x304, tDQSOscB0 = 405 ps tDQSOscB1 = 411 ps
3630 22:12:46.880003 CH1 RK1: MR19=304, MR18=FC0D
3631 22:12:46.886257 CH1_RK1: MR19=0x304, MR18=0xFC0D, DQSOSC=405, MR23=63, INC=39, DEC=26
3632 22:12:46.889959 [RxdqsGatingPostProcess] freq 1200
3633 22:12:46.896890 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3634 22:12:46.897319 best DQS0 dly(2T, 0.5T) = (0, 11)
3635 22:12:46.899528 best DQS1 dly(2T, 0.5T) = (0, 11)
3636 22:12:46.902567 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3637 22:12:46.905817 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3638 22:12:46.909554 best DQS0 dly(2T, 0.5T) = (0, 11)
3639 22:12:46.912669 best DQS1 dly(2T, 0.5T) = (0, 11)
3640 22:12:46.916195 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3641 22:12:46.919114 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3642 22:12:46.922256 Pre-setting of DQS Precalculation
3643 22:12:46.929069 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3644 22:12:46.936012 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3645 22:12:46.942066 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3646 22:12:46.942488
3647 22:12:46.942818
3648 22:12:46.945266 [Calibration Summary] 2400 Mbps
3649 22:12:46.945682 CH 0, Rank 0
3650 22:12:46.948799 SW Impedance : PASS
3651 22:12:46.952364 DUTY Scan : NO K
3652 22:12:46.952782 ZQ Calibration : PASS
3653 22:12:46.955358 Jitter Meter : NO K
3654 22:12:46.959014 CBT Training : PASS
3655 22:12:46.959547 Write leveling : PASS
3656 22:12:46.962216 RX DQS gating : PASS
3657 22:12:46.965347 RX DQ/DQS(RDDQC) : PASS
3658 22:12:46.965945 TX DQ/DQS : PASS
3659 22:12:46.968856 RX DATLAT : PASS
3660 22:12:46.972264 RX DQ/DQS(Engine): PASS
3661 22:12:46.972683 TX OE : NO K
3662 22:12:46.975452 All Pass.
3663 22:12:46.975890
3664 22:12:46.976325 CH 0, Rank 1
3665 22:12:46.978779 SW Impedance : PASS
3666 22:12:46.979241 DUTY Scan : NO K
3667 22:12:46.981555 ZQ Calibration : PASS
3668 22:12:46.984968 Jitter Meter : NO K
3669 22:12:46.985401 CBT Training : PASS
3670 22:12:46.988118 Write leveling : PASS
3671 22:12:46.991708 RX DQS gating : PASS
3672 22:12:46.992144 RX DQ/DQS(RDDQC) : PASS
3673 22:12:46.994983 TX DQ/DQS : PASS
3674 22:12:46.998175 RX DATLAT : PASS
3675 22:12:46.998621 RX DQ/DQS(Engine): PASS
3676 22:12:47.001652 TX OE : NO K
3677 22:12:47.002073 All Pass.
3678 22:12:47.002408
3679 22:12:47.004575 CH 1, Rank 0
3680 22:12:47.004996 SW Impedance : PASS
3681 22:12:47.008051 DUTY Scan : NO K
3682 22:12:47.008470 ZQ Calibration : PASS
3683 22:12:47.011098 Jitter Meter : NO K
3684 22:12:47.014687 CBT Training : PASS
3685 22:12:47.015112 Write leveling : PASS
3686 22:12:47.017692 RX DQS gating : PASS
3687 22:12:47.020972 RX DQ/DQS(RDDQC) : PASS
3688 22:12:47.021405 TX DQ/DQS : PASS
3689 22:12:47.024609 RX DATLAT : PASS
3690 22:12:47.027995 RX DQ/DQS(Engine): PASS
3691 22:12:47.028436 TX OE : NO K
3692 22:12:47.030737 All Pass.
3693 22:12:47.031166
3694 22:12:47.031625 CH 1, Rank 1
3695 22:12:47.034294 SW Impedance : PASS
3696 22:12:47.034773 DUTY Scan : NO K
3697 22:12:47.037709 ZQ Calibration : PASS
3698 22:12:47.040865 Jitter Meter : NO K
3699 22:12:47.041301 CBT Training : PASS
3700 22:12:47.044315 Write leveling : PASS
3701 22:12:47.047604 RX DQS gating : PASS
3702 22:12:47.048036 RX DQ/DQS(RDDQC) : PASS
3703 22:12:47.050631 TX DQ/DQS : PASS
3704 22:12:47.054147 RX DATLAT : PASS
3705 22:12:47.054580 RX DQ/DQS(Engine): PASS
3706 22:12:47.057178 TX OE : NO K
3707 22:12:47.057613 All Pass.
3708 22:12:47.058050
3709 22:12:47.060686 DramC Write-DBI off
3710 22:12:47.064170 PER_BANK_REFRESH: Hybrid Mode
3711 22:12:47.064604 TX_TRACKING: ON
3712 22:12:47.073589 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3713 22:12:47.076940 [FAST_K] Save calibration result to emmc
3714 22:12:47.080204 dramc_set_vcore_voltage set vcore to 650000
3715 22:12:47.083606 Read voltage for 600, 5
3716 22:12:47.084037 Vio18 = 0
3717 22:12:47.084370 Vcore = 650000
3718 22:12:47.087136 Vdram = 0
3719 22:12:47.087598 Vddq = 0
3720 22:12:47.087946 Vmddr = 0
3721 22:12:47.093594 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3722 22:12:47.096762 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3723 22:12:47.100131 MEM_TYPE=3, freq_sel=19
3724 22:12:47.103364 sv_algorithm_assistance_LP4_1600
3725 22:12:47.106745 ============ PULL DRAM RESETB DOWN ============
3726 22:12:47.113222 ========== PULL DRAM RESETB DOWN end =========
3727 22:12:47.116492 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3728 22:12:47.120063 ===================================
3729 22:12:47.123484 LPDDR4 DRAM CONFIGURATION
3730 22:12:47.126409 ===================================
3731 22:12:47.126848 EX_ROW_EN[0] = 0x0
3732 22:12:47.130373 EX_ROW_EN[1] = 0x0
3733 22:12:47.130801 LP4Y_EN = 0x0
3734 22:12:47.133038 WORK_FSP = 0x0
3735 22:12:47.133454 WL = 0x2
3736 22:12:47.136141 RL = 0x2
3737 22:12:47.136591 BL = 0x2
3738 22:12:47.139572 RPST = 0x0
3739 22:12:47.143114 RD_PRE = 0x0
3740 22:12:47.143590 WR_PRE = 0x1
3741 22:12:47.146370 WR_PST = 0x0
3742 22:12:47.146795 DBI_WR = 0x0
3743 22:12:47.149644 DBI_RD = 0x0
3744 22:12:47.150054 OTF = 0x1
3745 22:12:47.152920 ===================================
3746 22:12:47.156194 ===================================
3747 22:12:47.159773 ANA top config
3748 22:12:47.162972 ===================================
3749 22:12:47.163591 DLL_ASYNC_EN = 0
3750 22:12:47.165917 ALL_SLAVE_EN = 1
3751 22:12:47.169029 NEW_RANK_MODE = 1
3752 22:12:47.172875 DLL_IDLE_MODE = 1
3753 22:12:47.173351 LP45_APHY_COMB_EN = 1
3754 22:12:47.176315 TX_ODT_DIS = 1
3755 22:12:47.179230 NEW_8X_MODE = 1
3756 22:12:47.182241 ===================================
3757 22:12:47.185882 ===================================
3758 22:12:47.189109 data_rate = 1200
3759 22:12:47.192132 CKR = 1
3760 22:12:47.195361 DQ_P2S_RATIO = 8
3761 22:12:47.198733 ===================================
3762 22:12:47.199275 CA_P2S_RATIO = 8
3763 22:12:47.201919 DQ_CA_OPEN = 0
3764 22:12:47.206150 DQ_SEMI_OPEN = 0
3765 22:12:47.209159 CA_SEMI_OPEN = 0
3766 22:12:47.211935 CA_FULL_RATE = 0
3767 22:12:47.215257 DQ_CKDIV4_EN = 1
3768 22:12:47.218731 CA_CKDIV4_EN = 1
3769 22:12:47.219162 CA_PREDIV_EN = 0
3770 22:12:47.222003 PH8_DLY = 0
3771 22:12:47.225338 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3772 22:12:47.228273 DQ_AAMCK_DIV = 4
3773 22:12:47.232034 CA_AAMCK_DIV = 4
3774 22:12:47.234814 CA_ADMCK_DIV = 4
3775 22:12:47.235274 DQ_TRACK_CA_EN = 0
3776 22:12:47.238177 CA_PICK = 600
3777 22:12:47.241408 CA_MCKIO = 600
3778 22:12:47.244801 MCKIO_SEMI = 0
3779 22:12:47.248044 PLL_FREQ = 2288
3780 22:12:47.251573 DQ_UI_PI_RATIO = 32
3781 22:12:47.254891 CA_UI_PI_RATIO = 0
3782 22:12:47.257811 ===================================
3783 22:12:47.261078 ===================================
3784 22:12:47.261581 memory_type:LPDDR4
3785 22:12:47.264678 GP_NUM : 10
3786 22:12:47.267742 SRAM_EN : 1
3787 22:12:47.268244 MD32_EN : 0
3788 22:12:47.271221 ===================================
3789 22:12:47.274279 [ANA_INIT] >>>>>>>>>>>>>>
3790 22:12:47.277815 <<<<<< [CONFIGURE PHASE]: ANA_TX
3791 22:12:47.281189 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3792 22:12:47.284161 ===================================
3793 22:12:47.287416 data_rate = 1200,PCW = 0X5800
3794 22:12:47.290810 ===================================
3795 22:12:47.294465 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3796 22:12:47.297154 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3797 22:12:47.303956 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3798 22:12:47.310365 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3799 22:12:47.313535 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3800 22:12:47.317126 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3801 22:12:47.317637 [ANA_INIT] flow start
3802 22:12:47.320370 [ANA_INIT] PLL >>>>>>>>
3803 22:12:47.323531 [ANA_INIT] PLL <<<<<<<<
3804 22:12:47.323969 [ANA_INIT] MIDPI >>>>>>>>
3805 22:12:47.326698 [ANA_INIT] MIDPI <<<<<<<<
3806 22:12:47.330366 [ANA_INIT] DLL >>>>>>>>
3807 22:12:47.330927 [ANA_INIT] flow end
3808 22:12:47.337332 ============ LP4 DIFF to SE enter ============
3809 22:12:47.340132 ============ LP4 DIFF to SE exit ============
3810 22:12:47.343330 [ANA_INIT] <<<<<<<<<<<<<
3811 22:12:47.346735 [Flow] Enable top DCM control >>>>>
3812 22:12:47.349898 [Flow] Enable top DCM control <<<<<
3813 22:12:47.350330 Enable DLL master slave shuffle
3814 22:12:47.356332 ==============================================================
3815 22:12:47.359843 Gating Mode config
3816 22:12:47.362928 ==============================================================
3817 22:12:47.366609 Config description:
3818 22:12:47.376665 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3819 22:12:47.382945 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3820 22:12:47.385934 SELPH_MODE 0: By rank 1: By Phase
3821 22:12:47.392589 ==============================================================
3822 22:12:47.395791 GAT_TRACK_EN = 1
3823 22:12:47.399267 RX_GATING_MODE = 2
3824 22:12:47.402325 RX_GATING_TRACK_MODE = 2
3825 22:12:47.405982 SELPH_MODE = 1
3826 22:12:47.409256 PICG_EARLY_EN = 1
3827 22:12:47.412830 VALID_LAT_VALUE = 1
3828 22:12:47.416466 ==============================================================
3829 22:12:47.419299 Enter into Gating configuration >>>>
3830 22:12:47.422325 Exit from Gating configuration <<<<
3831 22:12:47.425444 Enter into DVFS_PRE_config >>>>>
3832 22:12:47.438415 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3833 22:12:47.441988 Exit from DVFS_PRE_config <<<<<
3834 22:12:47.442410 Enter into PICG configuration >>>>
3835 22:12:47.445105 Exit from PICG configuration <<<<
3836 22:12:47.448263 [RX_INPUT] configuration >>>>>
3837 22:12:47.451460 [RX_INPUT] configuration <<<<<
3838 22:12:47.458415 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3839 22:12:47.461507 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3840 22:12:47.468360 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3841 22:12:47.474586 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3842 22:12:47.481286 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3843 22:12:47.487801 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3844 22:12:47.490925 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3845 22:12:47.494099 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3846 22:12:47.501609 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3847 22:12:47.504066 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3848 22:12:47.507466 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3849 22:12:47.511213 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3850 22:12:47.514223 ===================================
3851 22:12:47.517466 LPDDR4 DRAM CONFIGURATION
3852 22:12:47.520849 ===================================
3853 22:12:47.523998 EX_ROW_EN[0] = 0x0
3854 22:12:47.524420 EX_ROW_EN[1] = 0x0
3855 22:12:47.527448 LP4Y_EN = 0x0
3856 22:12:47.527869 WORK_FSP = 0x0
3857 22:12:47.530560 WL = 0x2
3858 22:12:47.531000 RL = 0x2
3859 22:12:47.533945 BL = 0x2
3860 22:12:47.537410 RPST = 0x0
3861 22:12:47.538001 RD_PRE = 0x0
3862 22:12:47.540496 WR_PRE = 0x1
3863 22:12:47.540920 WR_PST = 0x0
3864 22:12:47.543853 DBI_WR = 0x0
3865 22:12:47.544270 DBI_RD = 0x0
3866 22:12:47.546973 OTF = 0x1
3867 22:12:47.550271 ===================================
3868 22:12:47.553809 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3869 22:12:47.557185 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3870 22:12:47.560263 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3871 22:12:47.563642 ===================================
3872 22:12:47.567258 LPDDR4 DRAM CONFIGURATION
3873 22:12:47.570443 ===================================
3874 22:12:47.573372 EX_ROW_EN[0] = 0x10
3875 22:12:47.573783 EX_ROW_EN[1] = 0x0
3876 22:12:47.576458 LP4Y_EN = 0x0
3877 22:12:47.577037 WORK_FSP = 0x0
3878 22:12:47.579991 WL = 0x2
3879 22:12:47.583165 RL = 0x2
3880 22:12:47.583600 BL = 0x2
3881 22:12:47.586441 RPST = 0x0
3882 22:12:47.586895 RD_PRE = 0x0
3883 22:12:47.590107 WR_PRE = 0x1
3884 22:12:47.590518 WR_PST = 0x0
3885 22:12:47.593210 DBI_WR = 0x0
3886 22:12:47.593661 DBI_RD = 0x0
3887 22:12:47.596837 OTF = 0x1
3888 22:12:47.599507 ===================================
3889 22:12:47.606270 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3890 22:12:47.609655 nWR fixed to 30
3891 22:12:47.610073 [ModeRegInit_LP4] CH0 RK0
3892 22:12:47.613000 [ModeRegInit_LP4] CH0 RK1
3893 22:12:47.616055 [ModeRegInit_LP4] CH1 RK0
3894 22:12:47.619412 [ModeRegInit_LP4] CH1 RK1
3895 22:12:47.619823 match AC timing 17
3896 22:12:47.622677 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3897 22:12:47.629730 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3898 22:12:47.633016 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3899 22:12:47.639081 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3900 22:12:47.642669 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3901 22:12:47.643084 ==
3902 22:12:47.646052 Dram Type= 6, Freq= 0, CH_0, rank 0
3903 22:12:47.648985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3904 22:12:47.649406 ==
3905 22:12:47.655470 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3906 22:12:47.662337 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3907 22:12:47.665397 [CA 0] Center 36 (6~67) winsize 62
3908 22:12:47.669199 [CA 1] Center 35 (5~66) winsize 62
3909 22:12:47.672581 [CA 2] Center 34 (4~65) winsize 62
3910 22:12:47.675630 [CA 3] Center 34 (4~65) winsize 62
3911 22:12:47.678720 [CA 4] Center 33 (3~64) winsize 62
3912 22:12:47.682454 [CA 5] Center 33 (3~64) winsize 62
3913 22:12:47.682870
3914 22:12:47.685674 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3915 22:12:47.686091
3916 22:12:47.688743 [CATrainingPosCal] consider 1 rank data
3917 22:12:47.691628 u2DelayCellTimex100 = 270/100 ps
3918 22:12:47.695298 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3919 22:12:47.698295 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3920 22:12:47.701606 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3921 22:12:47.704967 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3922 22:12:47.708641 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3923 22:12:47.711634 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3924 22:12:47.714735
3925 22:12:47.718678 CA PerBit enable=1, Macro0, CA PI delay=33
3926 22:12:47.719244
3927 22:12:47.721801 [CBTSetCACLKResult] CA Dly = 33
3928 22:12:47.722323 CS Dly: 5 (0~36)
3929 22:12:47.722677 ==
3930 22:12:47.725207 Dram Type= 6, Freq= 0, CH_0, rank 1
3931 22:12:47.728264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3932 22:12:47.731468 ==
3933 22:12:47.735341 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3934 22:12:47.741328 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3935 22:12:47.744941 [CA 0] Center 36 (6~67) winsize 62
3936 22:12:47.747732 [CA 1] Center 36 (6~67) winsize 62
3937 22:12:47.751585 [CA 2] Center 34 (4~65) winsize 62
3938 22:12:47.754530 [CA 3] Center 34 (4~65) winsize 62
3939 22:12:47.758566 [CA 4] Center 33 (3~64) winsize 62
3940 22:12:47.761399 [CA 5] Center 33 (3~64) winsize 62
3941 22:12:47.761818
3942 22:12:47.764438 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3943 22:12:47.764934
3944 22:12:47.767985 [CATrainingPosCal] consider 2 rank data
3945 22:12:47.771017 u2DelayCellTimex100 = 270/100 ps
3946 22:12:47.774342 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3947 22:12:47.778082 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3948 22:12:47.784291 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3949 22:12:47.787222 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3950 22:12:47.790348 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3951 22:12:47.794311 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3952 22:12:47.794730
3953 22:12:47.797183 CA PerBit enable=1, Macro0, CA PI delay=33
3954 22:12:47.797602
3955 22:12:47.800670 [CBTSetCACLKResult] CA Dly = 33
3956 22:12:47.801089 CS Dly: 5 (0~37)
3957 22:12:47.803503
3958 22:12:47.806937 ----->DramcWriteLeveling(PI) begin...
3959 22:12:47.807394 ==
3960 22:12:47.810183 Dram Type= 6, Freq= 0, CH_0, rank 0
3961 22:12:47.813727 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3962 22:12:47.814151 ==
3963 22:12:47.816796 Write leveling (Byte 0): 35 => 35
3964 22:12:47.820310 Write leveling (Byte 1): 28 => 28
3965 22:12:47.823649 DramcWriteLeveling(PI) end<-----
3966 22:12:47.824069
3967 22:12:47.824399 ==
3968 22:12:47.826753 Dram Type= 6, Freq= 0, CH_0, rank 0
3969 22:12:47.830072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3970 22:12:47.830491 ==
3971 22:12:47.833129 [Gating] SW mode calibration
3972 22:12:47.839968 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3973 22:12:47.846577 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3974 22:12:47.849501 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3975 22:12:47.852965 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3976 22:12:47.859639 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3977 22:12:47.862919 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
3978 22:12:47.866116 0 9 16 | B1->B0 | 2e2e 2a2a | 0 0 | (1 0) (0 0)
3979 22:12:47.872714 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3980 22:12:47.876114 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3981 22:12:47.879156 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3982 22:12:47.886034 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 22:12:47.889060 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3984 22:12:47.892117 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3985 22:12:47.898873 0 10 12 | B1->B0 | 2525 2c2c | 0 0 | (0 0) (0 0)
3986 22:12:47.902677 0 10 16 | B1->B0 | 3a3a 4242 | 0 0 | (0 0) (1 1)
3987 22:12:47.905415 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3988 22:12:47.911927 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3989 22:12:47.915531 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3990 22:12:47.918989 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 22:12:47.925520 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 22:12:47.928826 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3993 22:12:47.931793 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3994 22:12:47.938634 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3995 22:12:47.941933 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 22:12:47.945605 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 22:12:47.951960 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 22:12:47.954686 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 22:12:47.958292 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 22:12:47.964780 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 22:12:47.969042 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 22:12:47.972163 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 22:12:47.978164 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 22:12:47.981549 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 22:12:47.984624 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 22:12:47.991234 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 22:12:47.994502 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 22:12:47.997767 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 22:12:48.004270 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4010 22:12:48.007549 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4011 22:12:48.011293 Total UI for P1: 0, mck2ui 16
4012 22:12:48.014690 best dqsien dly found for B0: ( 0, 13, 12)
4013 22:12:48.017518 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4014 22:12:48.020841 Total UI for P1: 0, mck2ui 16
4015 22:12:48.024081 best dqsien dly found for B1: ( 0, 13, 16)
4016 22:12:48.030443 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4017 22:12:48.033961 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4018 22:12:48.034476
4019 22:12:48.036994 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4020 22:12:48.040402 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4021 22:12:48.043758 [Gating] SW calibration Done
4022 22:12:48.044172 ==
4023 22:12:48.047276 Dram Type= 6, Freq= 0, CH_0, rank 0
4024 22:12:48.050255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4025 22:12:48.050676 ==
4026 22:12:48.053602 RX Vref Scan: 0
4027 22:12:48.054017
4028 22:12:48.054345 RX Vref 0 -> 0, step: 1
4029 22:12:48.054675
4030 22:12:48.057817 RX Delay -230 -> 252, step: 16
4031 22:12:48.063346 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4032 22:12:48.066717 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4033 22:12:48.069894 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4034 22:12:48.073861 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4035 22:12:48.077317 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4036 22:12:48.083480 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4037 22:12:48.086324 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4038 22:12:48.090302 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4039 22:12:48.093055 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4040 22:12:48.099841 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4041 22:12:48.102739 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4042 22:12:48.106421 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4043 22:12:48.109598 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4044 22:12:48.116390 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4045 22:12:48.119480 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4046 22:12:48.122644 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4047 22:12:48.123058 ==
4048 22:12:48.126007 Dram Type= 6, Freq= 0, CH_0, rank 0
4049 22:12:48.129365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4050 22:12:48.132818 ==
4051 22:12:48.133230 DQS Delay:
4052 22:12:48.133555 DQS0 = 0, DQS1 = 0
4053 22:12:48.135921 DQM Delay:
4054 22:12:48.136330 DQM0 = 40, DQM1 = 35
4055 22:12:48.138897 DQ Delay:
4056 22:12:48.142646 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4057 22:12:48.145390 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4058 22:12:48.148769 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33
4059 22:12:48.152493 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4060 22:12:48.152907
4061 22:12:48.153233
4062 22:12:48.153535 ==
4063 22:12:48.155239 Dram Type= 6, Freq= 0, CH_0, rank 0
4064 22:12:48.158839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4065 22:12:48.159307 ==
4066 22:12:48.159650
4067 22:12:48.159957
4068 22:12:48.162124 TX Vref Scan disable
4069 22:12:48.162536 == TX Byte 0 ==
4070 22:12:48.168795 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4071 22:12:48.171827 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4072 22:12:48.175627 == TX Byte 1 ==
4073 22:12:48.178484 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4074 22:12:48.181597 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4075 22:12:48.182014 ==
4076 22:12:48.185197 Dram Type= 6, Freq= 0, CH_0, rank 0
4077 22:12:48.188602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4078 22:12:48.191729 ==
4079 22:12:48.192159
4080 22:12:48.192489
4081 22:12:48.192914 TX Vref Scan disable
4082 22:12:48.195573 == TX Byte 0 ==
4083 22:12:48.198849 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4084 22:12:48.206596 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4085 22:12:48.207012 == TX Byte 1 ==
4086 22:12:48.209031 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4087 22:12:48.215741 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4088 22:12:48.216178
4089 22:12:48.216504 [DATLAT]
4090 22:12:48.216808 Freq=600, CH0 RK0
4091 22:12:48.217141
4092 22:12:48.218456 DATLAT Default: 0x9
4093 22:12:48.222029 0, 0xFFFF, sum = 0
4094 22:12:48.222448 1, 0xFFFF, sum = 0
4095 22:12:48.225356 2, 0xFFFF, sum = 0
4096 22:12:48.225775 3, 0xFFFF, sum = 0
4097 22:12:48.228744 4, 0xFFFF, sum = 0
4098 22:12:48.229168 5, 0xFFFF, sum = 0
4099 22:12:48.231947 6, 0xFFFF, sum = 0
4100 22:12:48.232367 7, 0xFFFF, sum = 0
4101 22:12:48.234911 8, 0x0, sum = 1
4102 22:12:48.235510 9, 0x0, sum = 2
4103 22:12:48.238659 10, 0x0, sum = 3
4104 22:12:48.239080 11, 0x0, sum = 4
4105 22:12:48.239472 best_step = 9
4106 22:12:48.239785
4107 22:12:48.241634 ==
4108 22:12:48.244883 Dram Type= 6, Freq= 0, CH_0, rank 0
4109 22:12:48.248021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4110 22:12:48.248434 ==
4111 22:12:48.248765 RX Vref Scan: 1
4112 22:12:48.249072
4113 22:12:48.251301 RX Vref 0 -> 0, step: 1
4114 22:12:48.251713
4115 22:12:48.254902 RX Delay -195 -> 252, step: 8
4116 22:12:48.255354
4117 22:12:48.258122 Set Vref, RX VrefLevel [Byte0]: 51
4118 22:12:48.261115 [Byte1]: 59
4119 22:12:48.261524
4120 22:12:48.264784 Final RX Vref Byte 0 = 51 to rank0
4121 22:12:48.268221 Final RX Vref Byte 1 = 59 to rank0
4122 22:12:48.271073 Final RX Vref Byte 0 = 51 to rank1
4123 22:12:48.274765 Final RX Vref Byte 1 = 59 to rank1==
4124 22:12:48.278095 Dram Type= 6, Freq= 0, CH_0, rank 0
4125 22:12:48.281406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4126 22:12:48.284858 ==
4127 22:12:48.285272 DQS Delay:
4128 22:12:48.285625 DQS0 = 0, DQS1 = 0
4129 22:12:48.288033 DQM Delay:
4130 22:12:48.288444 DQM0 = 41, DQM1 = 33
4131 22:12:48.290943 DQ Delay:
4132 22:12:48.294655 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =36
4133 22:12:48.297648 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4134 22:12:48.298238 DQ8 =24, DQ9 =16, DQ10 =32, DQ11 =28
4135 22:12:48.304946 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4136 22:12:48.305361
4137 22:12:48.305684
4138 22:12:48.310708 [DQSOSCAuto] RK0, (LSB)MR18= 0x463e, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
4139 22:12:48.314070 CH0 RK0: MR19=808, MR18=463E
4140 22:12:48.320758 CH0_RK0: MR19=0x808, MR18=0x463E, DQSOSC=396, MR23=63, INC=167, DEC=111
4141 22:12:48.321178
4142 22:12:48.324192 ----->DramcWriteLeveling(PI) begin...
4143 22:12:48.324609 ==
4144 22:12:48.327435 Dram Type= 6, Freq= 0, CH_0, rank 1
4145 22:12:48.330511 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4146 22:12:48.330963 ==
4147 22:12:48.334170 Write leveling (Byte 0): 36 => 36
4148 22:12:48.337765 Write leveling (Byte 1): 28 => 28
4149 22:12:48.340769 DramcWriteLeveling(PI) end<-----
4150 22:12:48.341205
4151 22:12:48.341534 ==
4152 22:12:48.344107 Dram Type= 6, Freq= 0, CH_0, rank 1
4153 22:12:48.347068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4154 22:12:48.350186 ==
4155 22:12:48.350599 [Gating] SW mode calibration
4156 22:12:48.359790 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4157 22:12:48.363489 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4158 22:12:48.366626 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4159 22:12:48.373222 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4160 22:12:48.376720 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4161 22:12:48.379715 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 0)
4162 22:12:48.386422 0 9 16 | B1->B0 | 2c2c 2323 | 0 0 | (0 1) (0 0)
4163 22:12:48.389563 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4164 22:12:48.393067 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4165 22:12:48.400855 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4166 22:12:48.403144 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4167 22:12:48.406377 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4168 22:12:48.412688 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4169 22:12:48.416033 0 10 12 | B1->B0 | 2929 3534 | 0 1 | (0 0) (1 1)
4170 22:12:48.419764 0 10 16 | B1->B0 | 3e3e 4545 | 1 0 | (0 0) (0 0)
4171 22:12:48.426391 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4172 22:12:48.429558 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4173 22:12:48.432811 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4174 22:12:48.439673 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4175 22:12:48.442564 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4176 22:12:48.445398 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4177 22:12:48.452687 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4178 22:12:48.455711 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 22:12:48.458977 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 22:12:48.465705 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 22:12:48.468821 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 22:12:48.472231 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 22:12:48.478827 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 22:12:48.482039 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 22:12:48.485277 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 22:12:48.491957 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 22:12:48.495291 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 22:12:48.498779 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 22:12:48.505078 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 22:12:48.508508 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 22:12:48.512046 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 22:12:48.518031 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4193 22:12:48.521817 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4194 22:12:48.525145 Total UI for P1: 0, mck2ui 16
4195 22:12:48.528208 best dqsien dly found for B0: ( 0, 13, 8)
4196 22:12:48.532417 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4197 22:12:48.538149 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4198 22:12:48.541047 Total UI for P1: 0, mck2ui 16
4199 22:12:48.544762 best dqsien dly found for B1: ( 0, 13, 14)
4200 22:12:48.547760 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4201 22:12:48.551125 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4202 22:12:48.551591
4203 22:12:48.554769 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4204 22:12:48.557827 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4205 22:12:48.561368 [Gating] SW calibration Done
4206 22:12:48.561787 ==
4207 22:12:48.564612 Dram Type= 6, Freq= 0, CH_0, rank 1
4208 22:12:48.567838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4209 22:12:48.568258 ==
4210 22:12:48.571011 RX Vref Scan: 0
4211 22:12:48.571467
4212 22:12:48.571805 RX Vref 0 -> 0, step: 1
4213 22:12:48.574526
4214 22:12:48.574958 RX Delay -230 -> 252, step: 16
4215 22:12:48.581726 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4216 22:12:48.584074 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4217 22:12:48.587983 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4218 22:12:48.591199 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4219 22:12:48.597605 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4220 22:12:48.600925 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4221 22:12:48.604313 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4222 22:12:48.607608 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4223 22:12:48.613934 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4224 22:12:48.617164 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4225 22:12:48.620517 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4226 22:12:48.623669 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4227 22:12:48.630317 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4228 22:12:48.633519 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4229 22:12:48.637559 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4230 22:12:48.640292 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4231 22:12:48.640739 ==
4232 22:12:48.644747 Dram Type= 6, Freq= 0, CH_0, rank 1
4233 22:12:48.650304 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4234 22:12:48.650726 ==
4235 22:12:48.651062 DQS Delay:
4236 22:12:48.653875 DQS0 = 0, DQS1 = 0
4237 22:12:48.654292 DQM Delay:
4238 22:12:48.654627 DQM0 = 43, DQM1 = 36
4239 22:12:48.656832 DQ Delay:
4240 22:12:48.660896 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4241 22:12:48.663424 DQ4 =41, DQ5 =41, DQ6 =49, DQ7 =49
4242 22:12:48.666653 DQ8 =25, DQ9 =17, DQ10 =41, DQ11 =33
4243 22:12:48.669997 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4244 22:12:48.670415
4245 22:12:48.670744
4246 22:12:48.671048 ==
4247 22:12:48.673244 Dram Type= 6, Freq= 0, CH_0, rank 1
4248 22:12:48.676407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4249 22:12:48.676827 ==
4250 22:12:48.677160
4251 22:12:48.677467
4252 22:12:48.680260 TX Vref Scan disable
4253 22:12:48.683301 == TX Byte 0 ==
4254 22:12:48.686338 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
4255 22:12:48.689936 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
4256 22:12:48.693636 == TX Byte 1 ==
4257 22:12:48.696282 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4258 22:12:48.699666 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4259 22:12:48.700192 ==
4260 22:12:48.702722 Dram Type= 6, Freq= 0, CH_0, rank 1
4261 22:12:48.709513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4262 22:12:48.709934 ==
4263 22:12:48.710267
4264 22:12:48.710572
4265 22:12:48.710867 TX Vref Scan disable
4266 22:12:48.713768 == TX Byte 0 ==
4267 22:12:48.716997 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
4268 22:12:48.724203 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
4269 22:12:48.724759 == TX Byte 1 ==
4270 22:12:48.728033 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4271 22:12:48.733721 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4272 22:12:48.734146
4273 22:12:48.734501 [DATLAT]
4274 22:12:48.734810 Freq=600, CH0 RK1
4275 22:12:48.735114
4276 22:12:48.736964 DATLAT Default: 0x9
4277 22:12:48.740339 0, 0xFFFF, sum = 0
4278 22:12:48.740851 1, 0xFFFF, sum = 0
4279 22:12:48.743160 2, 0xFFFF, sum = 0
4280 22:12:48.743605 3, 0xFFFF, sum = 0
4281 22:12:48.746747 4, 0xFFFF, sum = 0
4282 22:12:48.747167 5, 0xFFFF, sum = 0
4283 22:12:48.749978 6, 0xFFFF, sum = 0
4284 22:12:48.750447 7, 0xFFFF, sum = 0
4285 22:12:48.753238 8, 0x0, sum = 1
4286 22:12:48.753661 9, 0x0, sum = 2
4287 22:12:48.756417 10, 0x0, sum = 3
4288 22:12:48.756930 11, 0x0, sum = 4
4289 22:12:48.757273 best_step = 9
4290 22:12:48.757585
4291 22:12:48.759626 ==
4292 22:12:48.763015 Dram Type= 6, Freq= 0, CH_0, rank 1
4293 22:12:48.766204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4294 22:12:48.766645 ==
4295 22:12:48.766978 RX Vref Scan: 0
4296 22:12:48.767329
4297 22:12:48.770100 RX Vref 0 -> 0, step: 1
4298 22:12:48.770522
4299 22:12:48.772828 RX Delay -195 -> 252, step: 8
4300 22:12:48.779687 iDelay=197, Bit 0, Center 40 (-107 ~ 188) 296
4301 22:12:48.783198 iDelay=197, Bit 1, Center 44 (-107 ~ 196) 304
4302 22:12:48.786282 iDelay=197, Bit 2, Center 36 (-115 ~ 188) 304
4303 22:12:48.789329 iDelay=197, Bit 3, Center 40 (-107 ~ 188) 296
4304 22:12:48.792589 iDelay=197, Bit 4, Center 44 (-107 ~ 196) 304
4305 22:12:48.800104 iDelay=197, Bit 5, Center 32 (-115 ~ 180) 296
4306 22:12:48.802415 iDelay=197, Bit 6, Center 52 (-91 ~ 196) 288
4307 22:12:48.806045 iDelay=197, Bit 7, Center 44 (-107 ~ 196) 304
4308 22:12:48.809134 iDelay=197, Bit 8, Center 24 (-131 ~ 180) 312
4309 22:12:48.815671 iDelay=197, Bit 9, Center 16 (-139 ~ 172) 312
4310 22:12:48.819335 iDelay=197, Bit 10, Center 36 (-123 ~ 196) 320
4311 22:12:48.822117 iDelay=197, Bit 11, Center 28 (-123 ~ 180) 304
4312 22:12:48.825657 iDelay=197, Bit 12, Center 40 (-115 ~ 196) 312
4313 22:12:48.832579 iDelay=197, Bit 13, Center 40 (-115 ~ 196) 312
4314 22:12:48.835335 iDelay=197, Bit 14, Center 40 (-115 ~ 196) 312
4315 22:12:48.838711 iDelay=197, Bit 15, Center 40 (-115 ~ 196) 312
4316 22:12:48.839125 ==
4317 22:12:48.842205 Dram Type= 6, Freq= 0, CH_0, rank 1
4318 22:12:48.845497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4319 22:12:48.848457 ==
4320 22:12:48.848871 DQS Delay:
4321 22:12:48.849279 DQS0 = 0, DQS1 = 0
4322 22:12:48.852064 DQM Delay:
4323 22:12:48.852475 DQM0 = 41, DQM1 = 33
4324 22:12:48.855158 DQ Delay:
4325 22:12:48.858341 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4326 22:12:48.862161 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =44
4327 22:12:48.864999 DQ8 =24, DQ9 =16, DQ10 =36, DQ11 =28
4328 22:12:48.868020 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4329 22:12:48.868430
4330 22:12:48.868781
4331 22:12:48.875649 [DQSOSCAuto] RK1, (LSB)MR18= 0x403a, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
4332 22:12:48.878018 CH0 RK1: MR19=808, MR18=403A
4333 22:12:48.884577 CH0_RK1: MR19=0x808, MR18=0x403A, DQSOSC=397, MR23=63, INC=166, DEC=110
4334 22:12:48.887979 [RxdqsGatingPostProcess] freq 600
4335 22:12:48.891728 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4336 22:12:48.894556 Pre-setting of DQS Precalculation
4337 22:12:48.901400 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4338 22:12:48.901814 ==
4339 22:12:48.904297 Dram Type= 6, Freq= 0, CH_1, rank 0
4340 22:12:48.908343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4341 22:12:48.908860 ==
4342 22:12:48.914162 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4343 22:12:48.921127 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4344 22:12:48.925016 [CA 0] Center 36 (6~66) winsize 61
4345 22:12:48.928239 [CA 1] Center 35 (5~66) winsize 62
4346 22:12:48.930643 [CA 2] Center 34 (4~65) winsize 62
4347 22:12:48.934600 [CA 3] Center 34 (3~65) winsize 63
4348 22:12:48.937578 [CA 4] Center 34 (4~65) winsize 62
4349 22:12:48.940497 [CA 5] Center 33 (3~64) winsize 62
4350 22:12:48.940917
4351 22:12:48.944399 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4352 22:12:48.944811
4353 22:12:48.946990 [CATrainingPosCal] consider 1 rank data
4354 22:12:48.950631 u2DelayCellTimex100 = 270/100 ps
4355 22:12:48.953619 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4356 22:12:48.957804 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4357 22:12:48.960287 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4358 22:12:48.963514 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4359 22:12:48.967340 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4360 22:12:48.970514 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4361 22:12:48.973371
4362 22:12:48.976826 CA PerBit enable=1, Macro0, CA PI delay=33
4363 22:12:48.977241
4364 22:12:48.980276 [CBTSetCACLKResult] CA Dly = 33
4365 22:12:48.980697 CS Dly: 5 (0~36)
4366 22:12:48.981031 ==
4367 22:12:48.983396 Dram Type= 6, Freq= 0, CH_1, rank 1
4368 22:12:48.986798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4369 22:12:48.989908 ==
4370 22:12:48.993574 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4371 22:12:48.999766 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4372 22:12:49.003457 [CA 0] Center 35 (5~66) winsize 62
4373 22:12:49.006409 [CA 1] Center 35 (5~66) winsize 62
4374 22:12:49.010386 [CA 2] Center 34 (4~65) winsize 62
4375 22:12:49.013120 [CA 3] Center 34 (3~65) winsize 63
4376 22:12:49.016507 [CA 4] Center 34 (3~65) winsize 63
4377 22:12:49.020280 [CA 5] Center 33 (3~64) winsize 62
4378 22:12:49.020692
4379 22:12:49.023311 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4380 22:12:49.023756
4381 22:12:49.026412 [CATrainingPosCal] consider 2 rank data
4382 22:12:49.029810 u2DelayCellTimex100 = 270/100 ps
4383 22:12:49.032975 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4384 22:12:49.036787 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4385 22:12:49.039474 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4386 22:12:49.046782 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4387 22:12:49.049478 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4388 22:12:49.053200 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4389 22:12:49.053612
4390 22:12:49.056225 CA PerBit enable=1, Macro0, CA PI delay=33
4391 22:12:49.056670
4392 22:12:49.059345 [CBTSetCACLKResult] CA Dly = 33
4393 22:12:49.059760 CS Dly: 5 (0~36)
4394 22:12:49.060185
4395 22:12:49.063273 ----->DramcWriteLeveling(PI) begin...
4396 22:12:49.063833 ==
4397 22:12:49.066114 Dram Type= 6, Freq= 0, CH_1, rank 0
4398 22:12:49.072775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4399 22:12:49.073190 ==
4400 22:12:49.076411 Write leveling (Byte 0): 27 => 27
4401 22:12:49.079393 Write leveling (Byte 1): 31 => 31
4402 22:12:49.082738 DramcWriteLeveling(PI) end<-----
4403 22:12:49.083149
4404 22:12:49.083564 ==
4405 22:12:49.086199 Dram Type= 6, Freq= 0, CH_1, rank 0
4406 22:12:49.089215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4407 22:12:49.089655 ==
4408 22:12:49.092386 [Gating] SW mode calibration
4409 22:12:49.099498 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4410 22:12:49.105500 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4411 22:12:49.108923 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4412 22:12:49.112032 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4413 22:12:49.119104 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4414 22:12:49.122113 0 9 12 | B1->B0 | 3131 2b2b | 0 0 | (0 0) (0 1)
4415 22:12:49.125605 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4416 22:12:49.132105 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4417 22:12:49.135684 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 22:12:49.138777 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4419 22:12:49.144875 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4420 22:12:49.148696 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4421 22:12:49.151733 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4422 22:12:49.158458 0 10 12 | B1->B0 | 3232 3838 | 1 1 | (0 0) (0 0)
4423 22:12:49.161443 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4424 22:12:49.165633 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 22:12:49.171784 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 22:12:49.174524 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 22:12:49.178710 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 22:12:49.184676 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 22:12:49.187963 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 22:12:49.191234 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4431 22:12:49.197891 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 22:12:49.201086 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 22:12:49.204723 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 22:12:49.210933 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 22:12:49.214415 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 22:12:49.217760 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 22:12:49.224661 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 22:12:49.227526 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 22:12:49.230992 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 22:12:49.237155 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 22:12:49.240593 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 22:12:49.243521 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 22:12:49.250325 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 22:12:49.253991 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 22:12:49.256899 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 22:12:49.263513 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4447 22:12:49.266889 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4448 22:12:49.270313 Total UI for P1: 0, mck2ui 16
4449 22:12:49.273757 best dqsien dly found for B0: ( 0, 13, 12)
4450 22:12:49.276531 Total UI for P1: 0, mck2ui 16
4451 22:12:49.280297 best dqsien dly found for B1: ( 0, 13, 12)
4452 22:12:49.283394 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4453 22:12:49.286723 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4454 22:12:49.287139
4455 22:12:49.290142 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4456 22:12:49.293460 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4457 22:12:49.297190 [Gating] SW calibration Done
4458 22:12:49.297608 ==
4459 22:12:49.299755 Dram Type= 6, Freq= 0, CH_1, rank 0
4460 22:12:49.302958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4461 22:12:49.306668 ==
4462 22:12:49.307085 RX Vref Scan: 0
4463 22:12:49.307463
4464 22:12:49.309409 RX Vref 0 -> 0, step: 1
4465 22:12:49.309823
4466 22:12:49.313607 RX Delay -230 -> 252, step: 16
4467 22:12:49.316771 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4468 22:12:49.319418 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4469 22:12:49.322520 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4470 22:12:49.329515 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4471 22:12:49.332396 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4472 22:12:49.335894 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4473 22:12:49.338931 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4474 22:12:49.346001 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4475 22:12:49.348956 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4476 22:12:49.352303 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4477 22:12:49.355485 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4478 22:12:49.362110 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4479 22:12:49.365893 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4480 22:12:49.369303 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4481 22:12:49.372828 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4482 22:12:49.379027 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4483 22:12:49.379511 ==
4484 22:12:49.382446 Dram Type= 6, Freq= 0, CH_1, rank 0
4485 22:12:49.385233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4486 22:12:49.385654 ==
4487 22:12:49.385985 DQS Delay:
4488 22:12:49.388738 DQS0 = 0, DQS1 = 0
4489 22:12:49.389156 DQM Delay:
4490 22:12:49.392444 DQM0 = 43, DQM1 = 39
4491 22:12:49.392862 DQ Delay:
4492 22:12:49.395937 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4493 22:12:49.398579 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4494 22:12:49.401489 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4495 22:12:49.404664 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4496 22:12:49.405082
4497 22:12:49.405412
4498 22:12:49.405720 ==
4499 22:12:49.408628 Dram Type= 6, Freq= 0, CH_1, rank 0
4500 22:12:49.412193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4501 22:12:49.415483 ==
4502 22:12:49.415901
4503 22:12:49.416228
4504 22:12:49.416535 TX Vref Scan disable
4505 22:12:49.418180 == TX Byte 0 ==
4506 22:12:49.422106 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4507 22:12:49.424668 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4508 22:12:49.428198 == TX Byte 1 ==
4509 22:12:49.431443 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4510 22:12:49.434885 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4511 22:12:49.438064 ==
4512 22:12:49.441694 Dram Type= 6, Freq= 0, CH_1, rank 0
4513 22:12:49.444849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4514 22:12:49.445269 ==
4515 22:12:49.445600
4516 22:12:49.445908
4517 22:12:49.447812 TX Vref Scan disable
4518 22:12:49.451772 == TX Byte 0 ==
4519 22:12:49.454854 Update DQ dly =572 (2 ,1, 28) DQ OEN =(1 ,6)
4520 22:12:49.457895 Update DQM dly =572 (2 ,1, 28) DQM OEN =(1 ,6)
4521 22:12:49.460859 == TX Byte 1 ==
4522 22:12:49.464599 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4523 22:12:49.467733 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4524 22:12:49.468154
4525 22:12:49.468487 [DATLAT]
4526 22:12:49.470776 Freq=600, CH1 RK0
4527 22:12:49.471220
4528 22:12:49.474195 DATLAT Default: 0x9
4529 22:12:49.474608 0, 0xFFFF, sum = 0
4530 22:12:49.478235 1, 0xFFFF, sum = 0
4531 22:12:49.478855 2, 0xFFFF, sum = 0
4532 22:12:49.481105 3, 0xFFFF, sum = 0
4533 22:12:49.481525 4, 0xFFFF, sum = 0
4534 22:12:49.483915 5, 0xFFFF, sum = 0
4535 22:12:49.484337 6, 0xFFFF, sum = 0
4536 22:12:49.487709 7, 0xFFFF, sum = 0
4537 22:12:49.488132 8, 0x0, sum = 1
4538 22:12:49.490802 9, 0x0, sum = 2
4539 22:12:49.491257 10, 0x0, sum = 3
4540 22:12:49.494088 11, 0x0, sum = 4
4541 22:12:49.494510 best_step = 9
4542 22:12:49.494838
4543 22:12:49.495143 ==
4544 22:12:49.497571 Dram Type= 6, Freq= 0, CH_1, rank 0
4545 22:12:49.500864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4546 22:12:49.501288 ==
4547 22:12:49.503978 RX Vref Scan: 1
4548 22:12:49.504395
4549 22:12:49.507225 RX Vref 0 -> 0, step: 1
4550 22:12:49.507646
4551 22:12:49.507976 RX Delay -179 -> 252, step: 8
4552 22:12:49.510743
4553 22:12:49.511157 Set Vref, RX VrefLevel [Byte0]: 45
4554 22:12:49.513447 [Byte1]: 53
4555 22:12:49.518653
4556 22:12:49.519069 Final RX Vref Byte 0 = 45 to rank0
4557 22:12:49.521648 Final RX Vref Byte 1 = 53 to rank0
4558 22:12:49.525151 Final RX Vref Byte 0 = 45 to rank1
4559 22:12:49.528169 Final RX Vref Byte 1 = 53 to rank1==
4560 22:12:49.531847 Dram Type= 6, Freq= 0, CH_1, rank 0
4561 22:12:49.538521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4562 22:12:49.539037 ==
4563 22:12:49.539428 DQS Delay:
4564 22:12:49.541924 DQS0 = 0, DQS1 = 0
4565 22:12:49.542342 DQM Delay:
4566 22:12:49.542674 DQM0 = 41, DQM1 = 33
4567 22:12:49.544705 DQ Delay:
4568 22:12:49.548807 DQ0 =44, DQ1 =36, DQ2 =32, DQ3 =44
4569 22:12:49.551571 DQ4 =40, DQ5 =48, DQ6 =52, DQ7 =36
4570 22:12:49.555043 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =28
4571 22:12:49.558579 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =40
4572 22:12:49.559083
4573 22:12:49.559484
4574 22:12:49.564358 [DQSOSCAuto] RK0, (LSB)MR18= 0x324b, (MSB)MR19= 0x808, tDQSOscB0 = 395 ps tDQSOscB1 = 400 ps
4575 22:12:49.567814 CH1 RK0: MR19=808, MR18=324B
4576 22:12:49.574437 CH1_RK0: MR19=0x808, MR18=0x324B, DQSOSC=395, MR23=63, INC=168, DEC=112
4577 22:12:49.574859
4578 22:12:49.577678 ----->DramcWriteLeveling(PI) begin...
4579 22:12:49.578101 ==
4580 22:12:49.580916 Dram Type= 6, Freq= 0, CH_1, rank 1
4581 22:12:49.584335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4582 22:12:49.584755 ==
4583 22:12:49.587741 Write leveling (Byte 0): 29 => 29
4584 22:12:49.591603 Write leveling (Byte 1): 29 => 29
4585 22:12:49.594449 DramcWriteLeveling(PI) end<-----
4586 22:12:49.594868
4587 22:12:49.595227 ==
4588 22:12:49.597734 Dram Type= 6, Freq= 0, CH_1, rank 1
4589 22:12:49.604103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4590 22:12:49.604572 ==
4591 22:12:49.604930 [Gating] SW mode calibration
4592 22:12:49.614018 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4593 22:12:49.617389 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4594 22:12:49.620679 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4595 22:12:49.626994 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4596 22:12:49.630125 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4597 22:12:49.636991 0 9 12 | B1->B0 | 3030 2e2e | 0 1 | (0 1) (1 0)
4598 22:12:49.639813 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4599 22:12:49.643363 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4600 22:12:49.649942 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4601 22:12:49.653253 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4602 22:12:49.656593 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4603 22:12:49.663500 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4604 22:12:49.666105 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4605 22:12:49.669350 0 10 12 | B1->B0 | 3232 3f3f | 0 0 | (1 1) (0 0)
4606 22:12:49.676060 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4607 22:12:49.679424 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4608 22:12:49.682743 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4609 22:12:49.689340 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4610 22:12:49.693275 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4611 22:12:49.696176 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4612 22:12:49.702623 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4613 22:12:49.705945 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4614 22:12:49.709276 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 22:12:49.715562 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 22:12:49.719216 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 22:12:49.722391 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 22:12:49.729218 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 22:12:49.732700 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 22:12:49.735662 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 22:12:49.741819 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 22:12:49.745186 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 22:12:49.748986 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 22:12:49.755124 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 22:12:49.758966 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 22:12:49.761680 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 22:12:49.768314 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 22:12:49.771507 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4629 22:12:49.774980 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4630 22:12:49.778348 Total UI for P1: 0, mck2ui 16
4631 22:12:49.781594 best dqsien dly found for B0: ( 0, 13, 8)
4632 22:12:49.788353 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4633 22:12:49.788775 Total UI for P1: 0, mck2ui 16
4634 22:12:49.791698 best dqsien dly found for B1: ( 0, 13, 12)
4635 22:12:49.797786 best DQS0 dly(MCK, UI, PI) = (0, 13, 8)
4636 22:12:49.801320 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4637 22:12:49.801739
4638 22:12:49.804564 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 8)
4639 22:12:49.807801 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4640 22:12:49.811103 [Gating] SW calibration Done
4641 22:12:49.811534 ==
4642 22:12:49.814527 Dram Type= 6, Freq= 0, CH_1, rank 1
4643 22:12:49.817558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4644 22:12:49.817785 ==
4645 22:12:49.820826 RX Vref Scan: 0
4646 22:12:49.821051
4647 22:12:49.821243 RX Vref 0 -> 0, step: 1
4648 22:12:49.821412
4649 22:12:49.824248 RX Delay -230 -> 252, step: 16
4650 22:12:49.830667 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4651 22:12:49.834009 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4652 22:12:49.837248 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4653 22:12:49.840775 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4654 22:12:49.844028 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4655 22:12:49.850510 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4656 22:12:49.853791 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4657 22:12:49.857741 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4658 22:12:49.860590 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4659 22:12:49.866749 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4660 22:12:49.870010 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4661 22:12:49.873631 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4662 22:12:49.876819 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4663 22:12:49.883268 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4664 22:12:49.886448 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4665 22:12:49.889924 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4666 22:12:49.890241 ==
4667 22:12:49.893456 Dram Type= 6, Freq= 0, CH_1, rank 1
4668 22:12:49.896385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4669 22:12:49.899601 ==
4670 22:12:49.899682 DQS Delay:
4671 22:12:49.899747 DQS0 = 0, DQS1 = 0
4672 22:12:49.903161 DQM Delay:
4673 22:12:49.903278 DQM0 = 42, DQM1 = 38
4674 22:12:49.906489 DQ Delay:
4675 22:12:49.906572 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4676 22:12:49.909630 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4677 22:12:49.913335 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4678 22:12:49.916315 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4679 22:12:49.919946
4680 22:12:49.920030
4681 22:12:49.920114 ==
4682 22:12:49.923030 Dram Type= 6, Freq= 0, CH_1, rank 1
4683 22:12:49.926343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4684 22:12:49.926419 ==
4685 22:12:49.926500
4686 22:12:49.926577
4687 22:12:49.929608 TX Vref Scan disable
4688 22:12:49.929691 == TX Byte 0 ==
4689 22:12:49.936249 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4690 22:12:49.939546 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4691 22:12:49.939672 == TX Byte 1 ==
4692 22:12:49.946009 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4693 22:12:49.949214 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4694 22:12:49.949320 ==
4695 22:12:49.952849 Dram Type= 6, Freq= 0, CH_1, rank 1
4696 22:12:49.955766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4697 22:12:49.955881 ==
4698 22:12:49.955993
4699 22:12:49.959052
4700 22:12:49.959222 TX Vref Scan disable
4701 22:12:49.962974 == TX Byte 0 ==
4702 22:12:49.965689 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4703 22:12:49.972441 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4704 22:12:49.972569 == TX Byte 1 ==
4705 22:12:49.975453 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4706 22:12:49.982591 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4707 22:12:49.982684
4708 22:12:49.982751 [DATLAT]
4709 22:12:49.982811 Freq=600, CH1 RK1
4710 22:12:49.982871
4711 22:12:49.985847 DATLAT Default: 0x9
4712 22:12:49.988992 0, 0xFFFF, sum = 0
4713 22:12:49.989073 1, 0xFFFF, sum = 0
4714 22:12:49.991924 2, 0xFFFF, sum = 0
4715 22:12:49.992000 3, 0xFFFF, sum = 0
4716 22:12:49.995306 4, 0xFFFF, sum = 0
4717 22:12:49.995406 5, 0xFFFF, sum = 0
4718 22:12:49.998651 6, 0xFFFF, sum = 0
4719 22:12:49.998761 7, 0xFFFF, sum = 0
4720 22:12:50.001816 8, 0x0, sum = 1
4721 22:12:50.001890 9, 0x0, sum = 2
4722 22:12:50.005255 10, 0x0, sum = 3
4723 22:12:50.005325 11, 0x0, sum = 4
4724 22:12:50.005385 best_step = 9
4725 22:12:50.005443
4726 22:12:50.008887 ==
4727 22:12:50.011458 Dram Type= 6, Freq= 0, CH_1, rank 1
4728 22:12:50.015966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4729 22:12:50.016052 ==
4730 22:12:50.016116 RX Vref Scan: 0
4731 22:12:50.016176
4732 22:12:50.018175 RX Vref 0 -> 0, step: 1
4733 22:12:50.018257
4734 22:12:50.021425 RX Delay -179 -> 252, step: 8
4735 22:12:50.028239 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4736 22:12:50.031414 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4737 22:12:50.035107 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4738 22:12:50.037954 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4739 22:12:50.045053 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4740 22:12:50.047904 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4741 22:12:50.051570 iDelay=205, Bit 6, Center 44 (-107 ~ 196) 304
4742 22:12:50.054572 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4743 22:12:50.058216 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4744 22:12:50.064262 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4745 22:12:50.067584 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4746 22:12:50.071459 iDelay=205, Bit 11, Center 28 (-131 ~ 188) 320
4747 22:12:50.074203 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4748 22:12:50.080885 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4749 22:12:50.084235 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4750 22:12:50.087587 iDelay=205, Bit 15, Center 44 (-115 ~ 204) 320
4751 22:12:50.087764 ==
4752 22:12:50.090809 Dram Type= 6, Freq= 0, CH_1, rank 1
4753 22:12:50.097583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4754 22:12:50.097754 ==
4755 22:12:50.097909 DQS Delay:
4756 22:12:50.098037 DQS0 = 0, DQS1 = 0
4757 22:12:50.100747 DQM Delay:
4758 22:12:50.100916 DQM0 = 37, DQM1 = 36
4759 22:12:50.103906 DQ Delay:
4760 22:12:50.107261 DQ0 =44, DQ1 =32, DQ2 =24, DQ3 =36
4761 22:12:50.110655 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =32
4762 22:12:50.114283 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4763 22:12:50.117137 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =44
4764 22:12:50.117513
4765 22:12:50.117846
4766 22:12:50.123943 [DQSOSCAuto] RK1, (LSB)MR18= 0x3156, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 400 ps
4767 22:12:50.127470 CH1 RK1: MR19=808, MR18=3156
4768 22:12:50.133636 CH1_RK1: MR19=0x808, MR18=0x3156, DQSOSC=393, MR23=63, INC=169, DEC=113
4769 22:12:50.137024 [RxdqsGatingPostProcess] freq 600
4770 22:12:50.140385 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4771 22:12:50.143620 Pre-setting of DQS Precalculation
4772 22:12:50.150718 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4773 22:12:50.156908 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4774 22:12:50.164029 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4775 22:12:50.164482
4776 22:12:50.164820
4777 22:12:50.166755 [Calibration Summary] 1200 Mbps
4778 22:12:50.170195 CH 0, Rank 0
4779 22:12:50.170629 SW Impedance : PASS
4780 22:12:50.173582 DUTY Scan : NO K
4781 22:12:50.173994 ZQ Calibration : PASS
4782 22:12:50.176423 Jitter Meter : NO K
4783 22:12:50.179920 CBT Training : PASS
4784 22:12:50.180319 Write leveling : PASS
4785 22:12:50.183371 RX DQS gating : PASS
4786 22:12:50.186521 RX DQ/DQS(RDDQC) : PASS
4787 22:12:50.186943 TX DQ/DQS : PASS
4788 22:12:50.189968 RX DATLAT : PASS
4789 22:12:50.192874 RX DQ/DQS(Engine): PASS
4790 22:12:50.193314 TX OE : NO K
4791 22:12:50.197123 All Pass.
4792 22:12:50.197560
4793 22:12:50.197916 CH 0, Rank 1
4794 22:12:50.200221 SW Impedance : PASS
4795 22:12:50.200769 DUTY Scan : NO K
4796 22:12:50.203213 ZQ Calibration : PASS
4797 22:12:50.206537 Jitter Meter : NO K
4798 22:12:50.206960 CBT Training : PASS
4799 22:12:50.209835 Write leveling : PASS
4800 22:12:50.212952 RX DQS gating : PASS
4801 22:12:50.213520 RX DQ/DQS(RDDQC) : PASS
4802 22:12:50.216216 TX DQ/DQS : PASS
4803 22:12:50.219226 RX DATLAT : PASS
4804 22:12:50.219690 RX DQ/DQS(Engine): PASS
4805 22:12:50.223522 TX OE : NO K
4806 22:12:50.223947 All Pass.
4807 22:12:50.224299
4808 22:12:50.225963 CH 1, Rank 0
4809 22:12:50.226406 SW Impedance : PASS
4810 22:12:50.229248 DUTY Scan : NO K
4811 22:12:50.232733 ZQ Calibration : PASS
4812 22:12:50.233273 Jitter Meter : NO K
4813 22:12:50.235889 CBT Training : PASS
4814 22:12:50.239378 Write leveling : PASS
4815 22:12:50.239802 RX DQS gating : PASS
4816 22:12:50.242853 RX DQ/DQS(RDDQC) : PASS
4817 22:12:50.243314 TX DQ/DQS : PASS
4818 22:12:50.245742 RX DATLAT : PASS
4819 22:12:50.250203 RX DQ/DQS(Engine): PASS
4820 22:12:50.250621 TX OE : NO K
4821 22:12:50.252426 All Pass.
4822 22:12:50.252845
4823 22:12:50.253177 CH 1, Rank 1
4824 22:12:50.255676 SW Impedance : PASS
4825 22:12:50.256092 DUTY Scan : NO K
4826 22:12:50.258904 ZQ Calibration : PASS
4827 22:12:50.262464 Jitter Meter : NO K
4828 22:12:50.262986 CBT Training : PASS
4829 22:12:50.265590 Write leveling : PASS
4830 22:12:50.269394 RX DQS gating : PASS
4831 22:12:50.269814 RX DQ/DQS(RDDQC) : PASS
4832 22:12:50.272364 TX DQ/DQS : PASS
4833 22:12:50.275593 RX DATLAT : PASS
4834 22:12:50.276012 RX DQ/DQS(Engine): PASS
4835 22:12:50.278952 TX OE : NO K
4836 22:12:50.279402 All Pass.
4837 22:12:50.279755
4838 22:12:50.281972 DramC Write-DBI off
4839 22:12:50.285298 PER_BANK_REFRESH: Hybrid Mode
4840 22:12:50.285714 TX_TRACKING: ON
4841 22:12:50.295841 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4842 22:12:50.298498 [FAST_K] Save calibration result to emmc
4843 22:12:50.303036 dramc_set_vcore_voltage set vcore to 662500
4844 22:12:50.305152 Read voltage for 933, 3
4845 22:12:50.305567 Vio18 = 0
4846 22:12:50.305900 Vcore = 662500
4847 22:12:50.308629 Vdram = 0
4848 22:12:50.309151 Vddq = 0
4849 22:12:50.309489 Vmddr = 0
4850 22:12:50.315085 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4851 22:12:50.318460 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4852 22:12:50.321416 MEM_TYPE=3, freq_sel=17
4853 22:12:50.325252 sv_algorithm_assistance_LP4_1600
4854 22:12:50.328177 ============ PULL DRAM RESETB DOWN ============
4855 22:12:50.334801 ========== PULL DRAM RESETB DOWN end =========
4856 22:12:50.338140 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4857 22:12:50.341143 ===================================
4858 22:12:50.344895 LPDDR4 DRAM CONFIGURATION
4859 22:12:50.348117 ===================================
4860 22:12:50.348536 EX_ROW_EN[0] = 0x0
4861 22:12:50.351278 EX_ROW_EN[1] = 0x0
4862 22:12:50.351696 LP4Y_EN = 0x0
4863 22:12:50.354528 WORK_FSP = 0x0
4864 22:12:50.357465 WL = 0x3
4865 22:12:50.357882 RL = 0x3
4866 22:12:50.360844 BL = 0x2
4867 22:12:50.361262 RPST = 0x0
4868 22:12:50.364730 RD_PRE = 0x0
4869 22:12:50.365148 WR_PRE = 0x1
4870 22:12:50.367285 WR_PST = 0x0
4871 22:12:50.367707 DBI_WR = 0x0
4872 22:12:50.370782 DBI_RD = 0x0
4873 22:12:50.371234 OTF = 0x1
4874 22:12:50.374157 ===================================
4875 22:12:50.377372 ===================================
4876 22:12:50.380738 ANA top config
4877 22:12:50.384161 ===================================
4878 22:12:50.384580 DLL_ASYNC_EN = 0
4879 22:12:50.387285 ALL_SLAVE_EN = 1
4880 22:12:50.390644 NEW_RANK_MODE = 1
4881 22:12:50.394305 DLL_IDLE_MODE = 1
4882 22:12:50.397428 LP45_APHY_COMB_EN = 1
4883 22:12:50.397846 TX_ODT_DIS = 1
4884 22:12:50.400328 NEW_8X_MODE = 1
4885 22:12:50.404121 ===================================
4886 22:12:50.406931 ===================================
4887 22:12:50.410445 data_rate = 1866
4888 22:12:50.413517 CKR = 1
4889 22:12:50.416767 DQ_P2S_RATIO = 8
4890 22:12:50.420107 ===================================
4891 22:12:50.424021 CA_P2S_RATIO = 8
4892 22:12:50.424546 DQ_CA_OPEN = 0
4893 22:12:50.426601 DQ_SEMI_OPEN = 0
4894 22:12:50.430210 CA_SEMI_OPEN = 0
4895 22:12:50.433332 CA_FULL_RATE = 0
4896 22:12:50.437155 DQ_CKDIV4_EN = 1
4897 22:12:50.440276 CA_CKDIV4_EN = 1
4898 22:12:50.440806 CA_PREDIV_EN = 0
4899 22:12:50.444346 PH8_DLY = 0
4900 22:12:50.446716 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4901 22:12:50.449785 DQ_AAMCK_DIV = 4
4902 22:12:50.453445 CA_AAMCK_DIV = 4
4903 22:12:50.456238 CA_ADMCK_DIV = 4
4904 22:12:50.456655 DQ_TRACK_CA_EN = 0
4905 22:12:50.460436 CA_PICK = 933
4906 22:12:50.462778 CA_MCKIO = 933
4907 22:12:50.466402 MCKIO_SEMI = 0
4908 22:12:50.469880 PLL_FREQ = 3732
4909 22:12:50.472629 DQ_UI_PI_RATIO = 32
4910 22:12:50.475923 CA_UI_PI_RATIO = 0
4911 22:12:50.479557 ===================================
4912 22:12:50.482526 ===================================
4913 22:12:50.483010 memory_type:LPDDR4
4914 22:12:50.486019 GP_NUM : 10
4915 22:12:50.489284 SRAM_EN : 1
4916 22:12:50.489894 MD32_EN : 0
4917 22:12:50.492430 ===================================
4918 22:12:50.495777 [ANA_INIT] >>>>>>>>>>>>>>
4919 22:12:50.498970 <<<<<< [CONFIGURE PHASE]: ANA_TX
4920 22:12:50.502434 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4921 22:12:50.505664 ===================================
4922 22:12:50.509200 data_rate = 1866,PCW = 0X8f00
4923 22:12:50.512259 ===================================
4924 22:12:50.515283 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4925 22:12:50.518989 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4926 22:12:50.525501 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4927 22:12:50.532459 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4928 22:12:50.535289 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4929 22:12:50.538370 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4930 22:12:50.538791 [ANA_INIT] flow start
4931 22:12:50.541797 [ANA_INIT] PLL >>>>>>>>
4932 22:12:50.545066 [ANA_INIT] PLL <<<<<<<<
4933 22:12:50.545483 [ANA_INIT] MIDPI >>>>>>>>
4934 22:12:50.548086 [ANA_INIT] MIDPI <<<<<<<<
4935 22:12:50.551666 [ANA_INIT] DLL >>>>>>>>
4936 22:12:50.552083 [ANA_INIT] flow end
4937 22:12:50.558163 ============ LP4 DIFF to SE enter ============
4938 22:12:50.561281 ============ LP4 DIFF to SE exit ============
4939 22:12:50.565015 [ANA_INIT] <<<<<<<<<<<<<
4940 22:12:50.568039 [Flow] Enable top DCM control >>>>>
4941 22:12:50.572000 [Flow] Enable top DCM control <<<<<
4942 22:12:50.572421 Enable DLL master slave shuffle
4943 22:12:50.577895 ==============================================================
4944 22:12:50.581096 Gating Mode config
4945 22:12:50.584609 ==============================================================
4946 22:12:50.588013 Config description:
4947 22:12:50.597669 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4948 22:12:50.603918 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4949 22:12:50.607325 SELPH_MODE 0: By rank 1: By Phase
4950 22:12:50.613905 ==============================================================
4951 22:12:50.617149 GAT_TRACK_EN = 1
4952 22:12:50.620312 RX_GATING_MODE = 2
4953 22:12:50.623803 RX_GATING_TRACK_MODE = 2
4954 22:12:50.626866 SELPH_MODE = 1
4955 22:12:50.630349 PICG_EARLY_EN = 1
4956 22:12:50.633725 VALID_LAT_VALUE = 1
4957 22:12:50.636977 ==============================================================
4958 22:12:50.640165 Enter into Gating configuration >>>>
4959 22:12:50.643408 Exit from Gating configuration <<<<
4960 22:12:50.646789 Enter into DVFS_PRE_config >>>>>
4961 22:12:50.659963 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4962 22:12:50.662966 Exit from DVFS_PRE_config <<<<<
4963 22:12:50.663484 Enter into PICG configuration >>>>
4964 22:12:50.666397 Exit from PICG configuration <<<<
4965 22:12:50.669674 [RX_INPUT] configuration >>>>>
4966 22:12:50.673068 [RX_INPUT] configuration <<<<<
4967 22:12:50.680261 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4968 22:12:50.683036 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4969 22:12:50.689395 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4970 22:12:50.696811 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4971 22:12:50.702807 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4972 22:12:50.709609 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4973 22:12:50.712519 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4974 22:12:50.716182 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4975 22:12:50.722326 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4976 22:12:50.725496 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4977 22:12:50.728813 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4978 22:12:50.732432 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4979 22:12:50.735656 ===================================
4980 22:12:50.738903 LPDDR4 DRAM CONFIGURATION
4981 22:12:50.742693 ===================================
4982 22:12:50.745433 EX_ROW_EN[0] = 0x0
4983 22:12:50.745847 EX_ROW_EN[1] = 0x0
4984 22:12:50.748967 LP4Y_EN = 0x0
4985 22:12:50.749386 WORK_FSP = 0x0
4986 22:12:50.751951 WL = 0x3
4987 22:12:50.752372 RL = 0x3
4988 22:12:50.755642 BL = 0x2
4989 22:12:50.758766 RPST = 0x0
4990 22:12:50.759223 RD_PRE = 0x0
4991 22:12:50.761722 WR_PRE = 0x1
4992 22:12:50.762143 WR_PST = 0x0
4993 22:12:50.765437 DBI_WR = 0x0
4994 22:12:50.765858 DBI_RD = 0x0
4995 22:12:50.768844 OTF = 0x1
4996 22:12:50.772008 ===================================
4997 22:12:50.775115 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4998 22:12:50.778353 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4999 22:12:50.785695 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5000 22:12:50.788203 ===================================
5001 22:12:50.788622 LPDDR4 DRAM CONFIGURATION
5002 22:12:50.791469 ===================================
5003 22:12:50.795099 EX_ROW_EN[0] = 0x10
5004 22:12:50.795558 EX_ROW_EN[1] = 0x0
5005 22:12:50.797891 LP4Y_EN = 0x0
5006 22:12:50.798307 WORK_FSP = 0x0
5007 22:12:50.801928 WL = 0x3
5008 22:12:50.804648 RL = 0x3
5009 22:12:50.805064 BL = 0x2
5010 22:12:50.808029 RPST = 0x0
5011 22:12:50.808445 RD_PRE = 0x0
5012 22:12:50.811429 WR_PRE = 0x1
5013 22:12:50.811973 WR_PST = 0x0
5014 22:12:50.814330 DBI_WR = 0x0
5015 22:12:50.814745 DBI_RD = 0x0
5016 22:12:50.817648 OTF = 0x1
5017 22:12:50.820946 ===================================
5018 22:12:50.828381 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5019 22:12:50.830922 nWR fixed to 30
5020 22:12:50.831365 [ModeRegInit_LP4] CH0 RK0
5021 22:12:50.834771 [ModeRegInit_LP4] CH0 RK1
5022 22:12:50.837560 [ModeRegInit_LP4] CH1 RK0
5023 22:12:50.837978 [ModeRegInit_LP4] CH1 RK1
5024 22:12:50.841133 match AC timing 9
5025 22:12:50.844522 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5026 22:12:50.847635 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5027 22:12:50.854339 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5028 22:12:50.857408 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5029 22:12:50.864297 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5030 22:12:50.864718 ==
5031 22:12:50.867555 Dram Type= 6, Freq= 0, CH_0, rank 0
5032 22:12:50.870728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5033 22:12:50.871157 ==
5034 22:12:50.877188 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5035 22:12:50.884002 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5036 22:12:50.887130 [CA 0] Center 37 (7~68) winsize 62
5037 22:12:50.890691 [CA 1] Center 37 (7~68) winsize 62
5038 22:12:50.893674 [CA 2] Center 34 (5~64) winsize 60
5039 22:12:50.896996 [CA 3] Center 34 (4~65) winsize 62
5040 22:12:50.900327 [CA 4] Center 33 (3~63) winsize 61
5041 22:12:50.903929 [CA 5] Center 32 (2~63) winsize 62
5042 22:12:50.904355
5043 22:12:50.906935 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5044 22:12:50.907393
5045 22:12:50.910023 [CATrainingPosCal] consider 1 rank data
5046 22:12:50.913402 u2DelayCellTimex100 = 270/100 ps
5047 22:12:50.916367 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5048 22:12:50.920314 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5049 22:12:50.923641 CA2 delay=34 (5~64),Diff = 2 PI (12 cell)
5050 22:12:50.926513 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5051 22:12:50.930500 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5052 22:12:50.933148 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5053 22:12:50.933564
5054 22:12:50.940000 CA PerBit enable=1, Macro0, CA PI delay=32
5055 22:12:50.940421
5056 22:12:50.943474 [CBTSetCACLKResult] CA Dly = 32
5057 22:12:50.943891 CS Dly: 6 (0~37)
5058 22:12:50.944223 ==
5059 22:12:50.946309 Dram Type= 6, Freq= 0, CH_0, rank 1
5060 22:12:50.950301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5061 22:12:50.950724 ==
5062 22:12:50.956900 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5063 22:12:50.963115 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5064 22:12:50.966988 [CA 0] Center 37 (7~68) winsize 62
5065 22:12:50.969768 [CA 1] Center 37 (7~68) winsize 62
5066 22:12:50.973150 [CA 2] Center 34 (4~65) winsize 62
5067 22:12:50.976077 [CA 3] Center 34 (4~65) winsize 62
5068 22:12:50.979385 [CA 4] Center 33 (3~64) winsize 62
5069 22:12:50.983046 [CA 5] Center 32 (2~63) winsize 62
5070 22:12:50.983530
5071 22:12:50.985945 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5072 22:12:50.986411
5073 22:12:50.989149 [CATrainingPosCal] consider 2 rank data
5074 22:12:50.992539 u2DelayCellTimex100 = 270/100 ps
5075 22:12:50.995900 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5076 22:12:50.999037 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5077 22:12:51.002344 CA2 delay=34 (5~64),Diff = 2 PI (12 cell)
5078 22:12:51.009446 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5079 22:12:51.012316 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5080 22:12:51.015915 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5081 22:12:51.016331
5082 22:12:51.018865 CA PerBit enable=1, Macro0, CA PI delay=32
5083 22:12:51.019458
5084 22:12:51.022308 [CBTSetCACLKResult] CA Dly = 32
5085 22:12:51.022810 CS Dly: 7 (0~39)
5086 22:12:51.023149
5087 22:12:51.026149 ----->DramcWriteLeveling(PI) begin...
5088 22:12:51.029009 ==
5089 22:12:51.032124 Dram Type= 6, Freq= 0, CH_0, rank 0
5090 22:12:51.035307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5091 22:12:51.035727 ==
5092 22:12:51.038735 Write leveling (Byte 0): 34 => 34
5093 22:12:51.042378 Write leveling (Byte 1): 29 => 29
5094 22:12:51.045179 DramcWriteLeveling(PI) end<-----
5095 22:12:51.045591
5096 22:12:51.045920 ==
5097 22:12:51.048477 Dram Type= 6, Freq= 0, CH_0, rank 0
5098 22:12:51.051723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5099 22:12:51.052138 ==
5100 22:12:51.055431 [Gating] SW mode calibration
5101 22:12:51.061549 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5102 22:12:51.068400 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5103 22:12:51.072125 0 14 0 | B1->B0 | 2424 3333 | 1 1 | (1 1) (1 1)
5104 22:12:51.074839 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5105 22:12:51.081282 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5106 22:12:51.084948 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5107 22:12:51.088233 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5108 22:12:51.094445 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5109 22:12:51.097767 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
5110 22:12:51.101031 0 14 28 | B1->B0 | 3333 2c2c | 1 0 | (1 1) (1 1)
5111 22:12:51.108037 0 15 0 | B1->B0 | 3030 2323 | 1 0 | (1 1) (0 0)
5112 22:12:51.110936 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5113 22:12:51.114145 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5114 22:12:51.121114 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5115 22:12:51.124259 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5116 22:12:51.127609 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5117 22:12:51.133704 0 15 24 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
5118 22:12:51.137073 0 15 28 | B1->B0 | 2323 3a3a | 0 1 | (0 0) (0 0)
5119 22:12:51.140570 1 0 0 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
5120 22:12:51.146962 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5121 22:12:51.150260 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5122 22:12:51.153681 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5123 22:12:51.160448 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5124 22:12:51.163551 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5125 22:12:51.166692 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5126 22:12:51.173451 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5127 22:12:51.176496 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5128 22:12:51.179731 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 22:12:51.186473 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 22:12:51.189776 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 22:12:51.193611 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 22:12:51.199579 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 22:12:51.203021 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 22:12:51.206591 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 22:12:51.214363 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 22:12:51.216598 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 22:12:51.219873 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 22:12:51.226634 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 22:12:51.229924 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 22:12:51.232759 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 22:12:51.239467 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 22:12:51.242536 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5143 22:12:51.246117 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5144 22:12:51.249011 Total UI for P1: 0, mck2ui 16
5145 22:12:51.252403 best dqsien dly found for B0: ( 1, 2, 28)
5146 22:12:51.259615 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5147 22:12:51.262494 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5148 22:12:51.265700 Total UI for P1: 0, mck2ui 16
5149 22:12:51.269019 best dqsien dly found for B1: ( 1, 3, 2)
5150 22:12:51.272147 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5151 22:12:51.276102 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5152 22:12:51.276516
5153 22:12:51.279055 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5154 22:12:51.282275 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5155 22:12:51.285166 [Gating] SW calibration Done
5156 22:12:51.285580 ==
5157 22:12:51.288650 Dram Type= 6, Freq= 0, CH_0, rank 0
5158 22:12:51.295276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5159 22:12:51.295692 ==
5160 22:12:51.296046 RX Vref Scan: 0
5161 22:12:51.296362
5162 22:12:51.298454 RX Vref 0 -> 0, step: 1
5163 22:12:51.298865
5164 22:12:51.302079 RX Delay -80 -> 252, step: 8
5165 22:12:51.305583 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5166 22:12:51.308701 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5167 22:12:51.311971 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5168 22:12:51.315622 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5169 22:12:51.318273 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5170 22:12:51.325035 iDelay=208, Bit 5, Center 91 (-8 ~ 191) 200
5171 22:12:51.328594 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5172 22:12:51.331729 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5173 22:12:51.335168 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5174 22:12:51.338016 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5175 22:12:51.344598 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5176 22:12:51.348352 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5177 22:12:51.351410 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5178 22:12:51.354403 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5179 22:12:51.358055 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5180 22:12:51.365215 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5181 22:12:51.365629 ==
5182 22:12:51.368017 Dram Type= 6, Freq= 0, CH_0, rank 0
5183 22:12:51.371139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5184 22:12:51.371590 ==
5185 22:12:51.371921 DQS Delay:
5186 22:12:51.374217 DQS0 = 0, DQS1 = 0
5187 22:12:51.374628 DQM Delay:
5188 22:12:51.377621 DQM0 = 100, DQM1 = 88
5189 22:12:51.378033 DQ Delay:
5190 22:12:51.381081 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =95
5191 22:12:51.384363 DQ4 =103, DQ5 =91, DQ6 =111, DQ7 =107
5192 22:12:51.388037 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5193 22:12:51.390916 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5194 22:12:51.391368
5195 22:12:51.391699
5196 22:12:51.392001 ==
5197 22:12:51.394080 Dram Type= 6, Freq= 0, CH_0, rank 0
5198 22:12:51.397751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5199 22:12:51.400918 ==
5200 22:12:51.401329
5201 22:12:51.401656
5202 22:12:51.401962 TX Vref Scan disable
5203 22:12:51.403907 == TX Byte 0 ==
5204 22:12:51.408159 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5205 22:12:51.410797 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5206 22:12:51.414021 == TX Byte 1 ==
5207 22:12:51.417323 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5208 22:12:51.420620 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5209 22:12:51.423903 ==
5210 22:12:51.427434 Dram Type= 6, Freq= 0, CH_0, rank 0
5211 22:12:51.430781 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5212 22:12:51.431505 ==
5213 22:12:51.431861
5214 22:12:51.432174
5215 22:12:51.434806 TX Vref Scan disable
5216 22:12:51.435269 == TX Byte 0 ==
5217 22:12:51.441008 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5218 22:12:51.443607 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5219 22:12:51.444023 == TX Byte 1 ==
5220 22:12:51.449915 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5221 22:12:51.453789 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5222 22:12:51.454202
5223 22:12:51.454530 [DATLAT]
5224 22:12:51.457411 Freq=933, CH0 RK0
5225 22:12:51.457825
5226 22:12:51.458153 DATLAT Default: 0xd
5227 22:12:51.460275 0, 0xFFFF, sum = 0
5228 22:12:51.463098 1, 0xFFFF, sum = 0
5229 22:12:51.463588 2, 0xFFFF, sum = 0
5230 22:12:51.466962 3, 0xFFFF, sum = 0
5231 22:12:51.467484 4, 0xFFFF, sum = 0
5232 22:12:51.469735 5, 0xFFFF, sum = 0
5233 22:12:51.470170 6, 0xFFFF, sum = 0
5234 22:12:51.473451 7, 0xFFFF, sum = 0
5235 22:12:51.473887 8, 0xFFFF, sum = 0
5236 22:12:51.476715 9, 0xFFFF, sum = 0
5237 22:12:51.477243 10, 0x0, sum = 1
5238 22:12:51.479832 11, 0x0, sum = 2
5239 22:12:51.480269 12, 0x0, sum = 3
5240 22:12:51.483263 13, 0x0, sum = 4
5241 22:12:51.483698 best_step = 11
5242 22:12:51.484127
5243 22:12:51.484529 ==
5244 22:12:51.486358 Dram Type= 6, Freq= 0, CH_0, rank 0
5245 22:12:51.489747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5246 22:12:51.492626 ==
5247 22:12:51.493054 RX Vref Scan: 1
5248 22:12:51.493485
5249 22:12:51.496170 RX Vref 0 -> 0, step: 1
5250 22:12:51.496596
5251 22:12:51.499902 RX Delay -61 -> 252, step: 4
5252 22:12:51.500346
5253 22:12:51.503237 Set Vref, RX VrefLevel [Byte0]: 51
5254 22:12:51.505747 [Byte1]: 59
5255 22:12:51.506174
5256 22:12:51.509119 Final RX Vref Byte 0 = 51 to rank0
5257 22:12:51.512310 Final RX Vref Byte 1 = 59 to rank0
5258 22:12:51.515710 Final RX Vref Byte 0 = 51 to rank1
5259 22:12:51.519073 Final RX Vref Byte 1 = 59 to rank1==
5260 22:12:51.527466 Dram Type= 6, Freq= 0, CH_0, rank 0
5261 22:12:51.527899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5262 22:12:51.528336 ==
5263 22:12:51.529057 DQS Delay:
5264 22:12:51.529420 DQS0 = 0, DQS1 = 0
5265 22:12:51.529817 DQM Delay:
5266 22:12:51.532662 DQM0 = 99, DQM1 = 87
5267 22:12:51.533088 DQ Delay:
5268 22:12:51.535853 DQ0 =100, DQ1 =100, DQ2 =94, DQ3 =96
5269 22:12:51.539798 DQ4 =100, DQ5 =90, DQ6 =110, DQ7 =106
5270 22:12:51.542425 DQ8 =78, DQ9 =74, DQ10 =88, DQ11 =82
5271 22:12:51.545303 DQ12 =96, DQ13 =92, DQ14 =98, DQ15 =92
5272 22:12:51.545733
5273 22:12:51.546159
5274 22:12:51.554928 [DQSOSCAuto] RK0, (LSB)MR18= 0x1711, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 414 ps
5275 22:12:51.558590 CH0 RK0: MR19=505, MR18=1711
5276 22:12:51.565190 CH0_RK0: MR19=0x505, MR18=0x1711, DQSOSC=414, MR23=63, INC=63, DEC=42
5277 22:12:51.565629
5278 22:12:51.568342 ----->DramcWriteLeveling(PI) begin...
5279 22:12:51.568771 ==
5280 22:12:51.571752 Dram Type= 6, Freq= 0, CH_0, rank 1
5281 22:12:51.575115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5282 22:12:51.575593 ==
5283 22:12:51.578447 Write leveling (Byte 0): 31 => 31
5284 22:12:51.581893 Write leveling (Byte 1): 29 => 29
5285 22:12:51.585251 DramcWriteLeveling(PI) end<-----
5286 22:12:51.585689
5287 22:12:51.586197 ==
5288 22:12:51.588693 Dram Type= 6, Freq= 0, CH_0, rank 1
5289 22:12:51.591560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5290 22:12:51.591979 ==
5291 22:12:51.595140 [Gating] SW mode calibration
5292 22:12:51.601592 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5293 22:12:51.608567 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5294 22:12:51.611763 0 14 0 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
5295 22:12:51.615063 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5296 22:12:51.621175 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5297 22:12:51.624604 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5298 22:12:51.628021 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5299 22:12:51.634431 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5300 22:12:51.638082 0 14 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
5301 22:12:51.642064 0 14 28 | B1->B0 | 3434 2c2c | 1 1 | (1 0) (1 0)
5302 22:12:51.647916 0 15 0 | B1->B0 | 2f2f 2525 | 0 0 | (1 1) (0 0)
5303 22:12:51.652387 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5304 22:12:51.654383 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5305 22:12:51.661183 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5306 22:12:51.664251 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5307 22:12:51.667601 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5308 22:12:51.674293 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5309 22:12:51.677406 0 15 28 | B1->B0 | 2828 4040 | 0 0 | (0 0) (0 0)
5310 22:12:51.680884 1 0 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5311 22:12:51.687786 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5312 22:12:51.690938 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5313 22:12:51.694183 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5314 22:12:51.700549 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5315 22:12:51.703619 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5316 22:12:51.707229 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5317 22:12:51.714281 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5318 22:12:51.716705 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5319 22:12:51.720447 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 22:12:51.726969 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 22:12:51.730193 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 22:12:51.733803 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 22:12:51.740303 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 22:12:51.743211 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 22:12:51.746650 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 22:12:51.753155 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 22:12:51.756576 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 22:12:51.760075 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 22:12:51.766374 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 22:12:51.769610 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 22:12:51.773448 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 22:12:51.779496 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5333 22:12:51.782798 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5334 22:12:51.786102 Total UI for P1: 0, mck2ui 16
5335 22:12:51.789457 best dqsien dly found for B0: ( 1, 2, 24)
5336 22:12:51.792854 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5337 22:12:51.799027 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5338 22:12:51.802658 Total UI for P1: 0, mck2ui 16
5339 22:12:51.805478 best dqsien dly found for B1: ( 1, 2, 30)
5340 22:12:51.808972 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5341 22:12:51.812511 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5342 22:12:51.812917
5343 22:12:51.815563 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5344 22:12:51.818655 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5345 22:12:51.822059 [Gating] SW calibration Done
5346 22:12:51.822506 ==
5347 22:12:51.825663 Dram Type= 6, Freq= 0, CH_0, rank 1
5348 22:12:51.829472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5349 22:12:51.829882 ==
5350 22:12:51.832379 RX Vref Scan: 0
5351 22:12:51.832785
5352 22:12:51.835465 RX Vref 0 -> 0, step: 1
5353 22:12:51.835880
5354 22:12:51.836210 RX Delay -80 -> 252, step: 8
5355 22:12:51.841995 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5356 22:12:51.845165 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5357 22:12:51.848733 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5358 22:12:51.852172 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5359 22:12:51.855313 iDelay=200, Bit 4, Center 99 (0 ~ 199) 200
5360 22:12:51.858419 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5361 22:12:51.864753 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5362 22:12:51.869026 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5363 22:12:51.871407 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5364 22:12:51.874966 iDelay=200, Bit 9, Center 79 (-8 ~ 167) 176
5365 22:12:51.878271 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5366 22:12:51.884753 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5367 22:12:51.887628 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5368 22:12:51.891317 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5369 22:12:51.894693 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5370 22:12:51.898106 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5371 22:12:51.898536 ==
5372 22:12:51.901121 Dram Type= 6, Freq= 0, CH_0, rank 1
5373 22:12:51.907785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5374 22:12:51.908205 ==
5375 22:12:51.908534 DQS Delay:
5376 22:12:51.911277 DQS0 = 0, DQS1 = 0
5377 22:12:51.911695 DQM Delay:
5378 22:12:51.912029 DQM0 = 97, DQM1 = 90
5379 22:12:51.914681 DQ Delay:
5380 22:12:51.918121 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5381 22:12:51.920946 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =103
5382 22:12:51.924390 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =83
5383 22:12:51.927716 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =95
5384 22:12:51.928132
5385 22:12:51.928461
5386 22:12:51.928767 ==
5387 22:12:51.930782 Dram Type= 6, Freq= 0, CH_0, rank 1
5388 22:12:51.934553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5389 22:12:51.934972 ==
5390 22:12:51.935335
5391 22:12:51.935645
5392 22:12:51.937218 TX Vref Scan disable
5393 22:12:51.940460 == TX Byte 0 ==
5394 22:12:51.943867 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5395 22:12:51.947278 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5396 22:12:51.950590 == TX Byte 1 ==
5397 22:12:51.953954 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5398 22:12:51.957111 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5399 22:12:51.957528 ==
5400 22:12:51.960410 Dram Type= 6, Freq= 0, CH_0, rank 1
5401 22:12:51.966645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5402 22:12:51.967061 ==
5403 22:12:51.967420
5404 22:12:51.967777
5405 22:12:51.968074 TX Vref Scan disable
5406 22:12:51.970819 == TX Byte 0 ==
5407 22:12:51.974114 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5408 22:12:51.980907 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5409 22:12:51.981323 == TX Byte 1 ==
5410 22:12:51.983751 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5411 22:12:51.990574 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5412 22:12:51.990988
5413 22:12:51.991370 [DATLAT]
5414 22:12:51.991770 Freq=933, CH0 RK1
5415 22:12:51.992228
5416 22:12:51.993903 DATLAT Default: 0xb
5417 22:12:51.997426 0, 0xFFFF, sum = 0
5418 22:12:51.997896 1, 0xFFFF, sum = 0
5419 22:12:52.000161 2, 0xFFFF, sum = 0
5420 22:12:52.000582 3, 0xFFFF, sum = 0
5421 22:12:52.003671 4, 0xFFFF, sum = 0
5422 22:12:52.004092 5, 0xFFFF, sum = 0
5423 22:12:52.007229 6, 0xFFFF, sum = 0
5424 22:12:52.007650 7, 0xFFFF, sum = 0
5425 22:12:52.010083 8, 0xFFFF, sum = 0
5426 22:12:52.010524 9, 0xFFFF, sum = 0
5427 22:12:52.013668 10, 0x0, sum = 1
5428 22:12:52.014086 11, 0x0, sum = 2
5429 22:12:52.017229 12, 0x0, sum = 3
5430 22:12:52.017646 13, 0x0, sum = 4
5431 22:12:52.020232 best_step = 11
5432 22:12:52.020644
5433 22:12:52.020967 ==
5434 22:12:52.023730 Dram Type= 6, Freq= 0, CH_0, rank 1
5435 22:12:52.026524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5436 22:12:52.026943 ==
5437 22:12:52.027308 RX Vref Scan: 0
5438 22:12:52.030219
5439 22:12:52.030633 RX Vref 0 -> 0, step: 1
5440 22:12:52.030962
5441 22:12:52.033751 RX Delay -53 -> 252, step: 4
5442 22:12:52.039799 iDelay=195, Bit 0, Center 96 (11 ~ 182) 172
5443 22:12:52.043485 iDelay=195, Bit 1, Center 98 (7 ~ 190) 184
5444 22:12:52.046220 iDelay=195, Bit 2, Center 94 (3 ~ 186) 184
5445 22:12:52.049651 iDelay=195, Bit 3, Center 94 (7 ~ 182) 176
5446 22:12:52.053214 iDelay=195, Bit 4, Center 102 (11 ~ 194) 184
5447 22:12:52.056841 iDelay=195, Bit 5, Center 86 (-5 ~ 178) 184
5448 22:12:52.062867 iDelay=195, Bit 6, Center 106 (19 ~ 194) 176
5449 22:12:52.066100 iDelay=195, Bit 7, Center 106 (19 ~ 194) 176
5450 22:12:52.069762 iDelay=195, Bit 8, Center 80 (-5 ~ 166) 172
5451 22:12:52.073250 iDelay=195, Bit 9, Center 76 (-9 ~ 162) 172
5452 22:12:52.076461 iDelay=195, Bit 10, Center 90 (-1 ~ 182) 184
5453 22:12:52.082789 iDelay=195, Bit 11, Center 84 (-5 ~ 174) 180
5454 22:12:52.086246 iDelay=195, Bit 12, Center 94 (7 ~ 182) 176
5455 22:12:52.090143 iDelay=195, Bit 13, Center 94 (3 ~ 186) 184
5456 22:12:52.092792 iDelay=195, Bit 14, Center 98 (7 ~ 190) 184
5457 22:12:52.096015 iDelay=195, Bit 15, Center 96 (7 ~ 186) 180
5458 22:12:52.096484 ==
5459 22:12:52.099105 Dram Type= 6, Freq= 0, CH_0, rank 1
5460 22:12:52.105753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5461 22:12:52.106177 ==
5462 22:12:52.106552 DQS Delay:
5463 22:12:52.109231 DQS0 = 0, DQS1 = 0
5464 22:12:52.109742 DQM Delay:
5465 22:12:52.110104 DQM0 = 97, DQM1 = 89
5466 22:12:52.112407 DQ Delay:
5467 22:12:52.115766 DQ0 =96, DQ1 =98, DQ2 =94, DQ3 =94
5468 22:12:52.118917 DQ4 =102, DQ5 =86, DQ6 =106, DQ7 =106
5469 22:12:52.122106 DQ8 =80, DQ9 =76, DQ10 =90, DQ11 =84
5470 22:12:52.125432 DQ12 =94, DQ13 =94, DQ14 =98, DQ15 =96
5471 22:12:52.125869
5472 22:12:52.126303
5473 22:12:52.132247 [DQSOSCAuto] RK1, (LSB)MR18= 0x1613, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 414 ps
5474 22:12:52.135707 CH0 RK1: MR19=505, MR18=1613
5475 22:12:52.142416 CH0_RK1: MR19=0x505, MR18=0x1613, DQSOSC=414, MR23=63, INC=63, DEC=42
5476 22:12:52.145513 [RxdqsGatingPostProcess] freq 933
5477 22:12:52.152267 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5478 22:12:52.155669 best DQS0 dly(2T, 0.5T) = (0, 10)
5479 22:12:52.156104 best DQS1 dly(2T, 0.5T) = (0, 11)
5480 22:12:52.158315 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5481 22:12:52.161508 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5482 22:12:52.164847 best DQS0 dly(2T, 0.5T) = (0, 10)
5483 22:12:52.168342 best DQS1 dly(2T, 0.5T) = (0, 10)
5484 22:12:52.171432 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5485 22:12:52.174577 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5486 22:12:52.178402 Pre-setting of DQS Precalculation
5487 22:12:52.184625 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5488 22:12:52.185106 ==
5489 22:12:52.188119 Dram Type= 6, Freq= 0, CH_1, rank 0
5490 22:12:52.191158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5491 22:12:52.191662 ==
5492 22:12:52.197804 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5493 22:12:52.204159 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5494 22:12:52.208006 [CA 0] Center 36 (6~67) winsize 62
5495 22:12:52.211002 [CA 1] Center 36 (6~67) winsize 62
5496 22:12:52.214374 [CA 2] Center 34 (4~65) winsize 62
5497 22:12:52.217599 [CA 3] Center 33 (3~64) winsize 62
5498 22:12:52.220943 [CA 4] Center 34 (4~65) winsize 62
5499 22:12:52.224107 [CA 5] Center 33 (3~64) winsize 62
5500 22:12:52.224530
5501 22:12:52.227642 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5502 22:12:52.228065
5503 22:12:52.230714 [CATrainingPosCal] consider 1 rank data
5504 22:12:52.233937 u2DelayCellTimex100 = 270/100 ps
5505 22:12:52.237376 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5506 22:12:52.241415 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5507 22:12:52.243772 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5508 22:12:52.246860 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5509 22:12:52.250239 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5510 22:12:52.254026 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5511 22:12:52.254579
5512 22:12:52.260456 CA PerBit enable=1, Macro0, CA PI delay=33
5513 22:12:52.260968
5514 22:12:52.263918 [CBTSetCACLKResult] CA Dly = 33
5515 22:12:52.264342 CS Dly: 5 (0~36)
5516 22:12:52.264680 ==
5517 22:12:52.267072 Dram Type= 6, Freq= 0, CH_1, rank 1
5518 22:12:52.270194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5519 22:12:52.270748 ==
5520 22:12:52.277326 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5521 22:12:52.284834 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5522 22:12:52.286850 [CA 0] Center 36 (6~67) winsize 62
5523 22:12:52.290130 [CA 1] Center 36 (6~67) winsize 62
5524 22:12:52.293256 [CA 2] Center 34 (4~65) winsize 62
5525 22:12:52.296817 [CA 3] Center 33 (3~64) winsize 62
5526 22:12:52.300412 [CA 4] Center 33 (3~64) winsize 62
5527 22:12:52.303959 [CA 5] Center 33 (3~64) winsize 62
5528 22:12:52.304409
5529 22:12:52.306629 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5530 22:12:52.307043
5531 22:12:52.310140 [CATrainingPosCal] consider 2 rank data
5532 22:12:52.313246 u2DelayCellTimex100 = 270/100 ps
5533 22:12:52.316385 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5534 22:12:52.320054 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5535 22:12:52.323574 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5536 22:12:52.326185 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5537 22:12:52.333184 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5538 22:12:52.336186 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5539 22:12:52.336605
5540 22:12:52.339536 CA PerBit enable=1, Macro0, CA PI delay=33
5541 22:12:52.339956
5542 22:12:52.342821 [CBTSetCACLKResult] CA Dly = 33
5543 22:12:52.343268 CS Dly: 6 (0~38)
5544 22:12:52.343602
5545 22:12:52.346365 ----->DramcWriteLeveling(PI) begin...
5546 22:12:52.346789 ==
5547 22:12:52.349398 Dram Type= 6, Freq= 0, CH_1, rank 0
5548 22:12:52.356433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5549 22:12:52.356964 ==
5550 22:12:52.359627 Write leveling (Byte 0): 29 => 29
5551 22:12:52.362523 Write leveling (Byte 1): 31 => 31
5552 22:12:52.362961 DramcWriteLeveling(PI) end<-----
5553 22:12:52.363329
5554 22:12:52.365855 ==
5555 22:12:52.369398 Dram Type= 6, Freq= 0, CH_1, rank 0
5556 22:12:52.372527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5557 22:12:52.372943 ==
5558 22:12:52.375397 [Gating] SW mode calibration
5559 22:12:52.382199 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5560 22:12:52.385447 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5561 22:12:52.391914 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5562 22:12:52.395404 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5563 22:12:52.398759 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5564 22:12:52.405105 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5565 22:12:52.408774 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5566 22:12:52.415060 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5567 22:12:52.418485 0 14 24 | B1->B0 | 3434 3131 | 0 1 | (0 0) (1 1)
5568 22:12:52.421836 0 14 28 | B1->B0 | 2a2a 2626 | 0 0 | (1 0) (1 0)
5569 22:12:52.428002 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5570 22:12:52.431309 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5571 22:12:52.435357 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5572 22:12:52.441232 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5573 22:12:52.444729 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5574 22:12:52.447727 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5575 22:12:52.454568 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
5576 22:12:52.457752 0 15 28 | B1->B0 | 3b3b 4242 | 0 0 | (0 0) (0 0)
5577 22:12:52.461030 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5578 22:12:52.467812 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5579 22:12:52.471136 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5580 22:12:52.474368 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5581 22:12:52.480825 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5582 22:12:52.484025 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5583 22:12:52.487674 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5584 22:12:52.493779 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5585 22:12:52.497633 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5586 22:12:52.500235 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 22:12:52.506915 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 22:12:52.510371 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 22:12:52.514068 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 22:12:52.520841 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 22:12:52.523715 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 22:12:52.526713 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 22:12:52.533292 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 22:12:52.536794 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 22:12:52.539895 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 22:12:52.546809 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 22:12:52.550321 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 22:12:52.553161 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 22:12:52.559657 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5600 22:12:52.563095 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5601 22:12:52.566419 Total UI for P1: 0, mck2ui 16
5602 22:12:52.569932 best dqsien dly found for B0: ( 1, 2, 24)
5603 22:12:52.573325 Total UI for P1: 0, mck2ui 16
5604 22:12:52.576366 best dqsien dly found for B1: ( 1, 2, 24)
5605 22:12:52.579606 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5606 22:12:52.582951 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5607 22:12:52.583409
5608 22:12:52.586258 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5609 22:12:52.589639 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5610 22:12:52.592530 [Gating] SW calibration Done
5611 22:12:52.593091 ==
5612 22:12:52.595996 Dram Type= 6, Freq= 0, CH_1, rank 0
5613 22:12:52.599365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5614 22:12:52.602761 ==
5615 22:12:52.603209 RX Vref Scan: 0
5616 22:12:52.603554
5617 22:12:52.605823 RX Vref 0 -> 0, step: 1
5618 22:12:52.606308
5619 22:12:52.609653 RX Delay -80 -> 252, step: 8
5620 22:12:52.612273 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5621 22:12:52.615557 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5622 22:12:52.619088 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5623 22:12:52.622099 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5624 22:12:52.625371 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5625 22:12:52.632394 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5626 22:12:52.635522 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5627 22:12:52.638762 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5628 22:12:52.642520 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5629 22:12:52.645705 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5630 22:12:52.651854 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5631 22:12:52.655561 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5632 22:12:52.658688 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5633 22:12:52.662104 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5634 22:12:52.665421 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5635 22:12:52.669260 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5636 22:12:52.671890 ==
5637 22:12:52.675333 Dram Type= 6, Freq= 0, CH_1, rank 0
5638 22:12:52.678420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5639 22:12:52.678944 ==
5640 22:12:52.679327 DQS Delay:
5641 22:12:52.681695 DQS0 = 0, DQS1 = 0
5642 22:12:52.682249 DQM Delay:
5643 22:12:52.684912 DQM0 = 100, DQM1 = 95
5644 22:12:52.685473 DQ Delay:
5645 22:12:52.688136 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5646 22:12:52.692457 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5647 22:12:52.695265 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =87
5648 22:12:52.698357 DQ12 =99, DQ13 =103, DQ14 =103, DQ15 =103
5649 22:12:52.698775
5650 22:12:52.699103
5651 22:12:52.699461 ==
5652 22:12:52.701314 Dram Type= 6, Freq= 0, CH_1, rank 0
5653 22:12:52.704896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5654 22:12:52.708552 ==
5655 22:12:52.708968
5656 22:12:52.709294
5657 22:12:52.709598 TX Vref Scan disable
5658 22:12:52.711600 == TX Byte 0 ==
5659 22:12:52.714682 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5660 22:12:52.717958 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5661 22:12:52.721432 == TX Byte 1 ==
5662 22:12:52.724398 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5663 22:12:52.732355 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5664 22:12:52.732772 ==
5665 22:12:52.734547 Dram Type= 6, Freq= 0, CH_1, rank 0
5666 22:12:52.737697 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5667 22:12:52.738118 ==
5668 22:12:52.738453
5669 22:12:52.738757
5670 22:12:52.740839 TX Vref Scan disable
5671 22:12:52.741358 == TX Byte 0 ==
5672 22:12:52.747926 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5673 22:12:52.751569 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5674 22:12:52.752008 == TX Byte 1 ==
5675 22:12:52.757555 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5676 22:12:52.760863 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5677 22:12:52.761283
5678 22:12:52.761642 [DATLAT]
5679 22:12:52.763840 Freq=933, CH1 RK0
5680 22:12:52.764295
5681 22:12:52.764793 DATLAT Default: 0xd
5682 22:12:52.767211 0, 0xFFFF, sum = 0
5683 22:12:52.767639 1, 0xFFFF, sum = 0
5684 22:12:52.771076 2, 0xFFFF, sum = 0
5685 22:12:52.774117 3, 0xFFFF, sum = 0
5686 22:12:52.774539 4, 0xFFFF, sum = 0
5687 22:12:52.777446 5, 0xFFFF, sum = 0
5688 22:12:52.777871 6, 0xFFFF, sum = 0
5689 22:12:52.780900 7, 0xFFFF, sum = 0
5690 22:12:52.781427 8, 0xFFFF, sum = 0
5691 22:12:52.783791 9, 0xFFFF, sum = 0
5692 22:12:52.784215 10, 0x0, sum = 1
5693 22:12:52.787205 11, 0x0, sum = 2
5694 22:12:52.787776 12, 0x0, sum = 3
5695 22:12:52.790686 13, 0x0, sum = 4
5696 22:12:52.791110 best_step = 11
5697 22:12:52.791502
5698 22:12:52.791861 ==
5699 22:12:52.793557 Dram Type= 6, Freq= 0, CH_1, rank 0
5700 22:12:52.796987 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5701 22:12:52.797405 ==
5702 22:12:52.800302 RX Vref Scan: 1
5703 22:12:52.800728
5704 22:12:52.803607 RX Vref 0 -> 0, step: 1
5705 22:12:52.804018
5706 22:12:52.804385 RX Delay -53 -> 252, step: 4
5707 22:12:52.804702
5708 22:12:52.806866 Set Vref, RX VrefLevel [Byte0]: 45
5709 22:12:52.810364 [Byte1]: 53
5710 22:12:52.814990
5711 22:12:52.815451 Final RX Vref Byte 0 = 45 to rank0
5712 22:12:52.818361 Final RX Vref Byte 1 = 53 to rank0
5713 22:12:52.822110 Final RX Vref Byte 0 = 45 to rank1
5714 22:12:52.824867 Final RX Vref Byte 1 = 53 to rank1==
5715 22:12:52.828261 Dram Type= 6, Freq= 0, CH_1, rank 0
5716 22:12:52.834673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5717 22:12:52.835094 ==
5718 22:12:52.835556 DQS Delay:
5719 22:12:52.838388 DQS0 = 0, DQS1 = 0
5720 22:12:52.838929 DQM Delay:
5721 22:12:52.839340 DQM0 = 98, DQM1 = 94
5722 22:12:52.841375 DQ Delay:
5723 22:12:52.844692 DQ0 =104, DQ1 =96, DQ2 =88, DQ3 =98
5724 22:12:52.847811 DQ4 =94, DQ5 =106, DQ6 =110, DQ7 =92
5725 22:12:52.851305 DQ8 =80, DQ9 =84, DQ10 =96, DQ11 =88
5726 22:12:52.854717 DQ12 =102, DQ13 =102, DQ14 =102, DQ15 =104
5727 22:12:52.855240
5728 22:12:52.855627
5729 22:12:52.861042 [DQSOSCAuto] RK0, (LSB)MR18= 0x717, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 419 ps
5730 22:12:52.864319 CH1 RK0: MR19=505, MR18=717
5731 22:12:52.870845 CH1_RK0: MR19=0x505, MR18=0x717, DQSOSC=414, MR23=63, INC=63, DEC=42
5732 22:12:52.871297
5733 22:12:52.874403 ----->DramcWriteLeveling(PI) begin...
5734 22:12:52.874874 ==
5735 22:12:52.877683 Dram Type= 6, Freq= 0, CH_1, rank 1
5736 22:12:52.880934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5737 22:12:52.881474 ==
5738 22:12:52.884241 Write leveling (Byte 0): 27 => 27
5739 22:12:52.887363 Write leveling (Byte 1): 27 => 27
5740 22:12:52.890759 DramcWriteLeveling(PI) end<-----
5741 22:12:52.891245
5742 22:12:52.891598 ==
5743 22:12:52.894123 Dram Type= 6, Freq= 0, CH_1, rank 1
5744 22:12:52.900495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5745 22:12:52.900920 ==
5746 22:12:52.901276 [Gating] SW mode calibration
5747 22:12:52.910505 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5748 22:12:52.913634 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5749 22:12:52.920192 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5750 22:12:52.923856 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5751 22:12:52.927698 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5752 22:12:52.933387 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5753 22:12:52.936948 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5754 22:12:52.940823 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5755 22:12:52.943740 0 14 24 | B1->B0 | 3434 2f2f | 0 1 | (0 0) (1 1)
5756 22:12:52.950341 0 14 28 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5757 22:12:52.953654 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5758 22:12:52.957071 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5759 22:12:52.963291 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5760 22:12:52.966708 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5761 22:12:52.970016 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5762 22:12:52.976733 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5763 22:12:52.979620 0 15 24 | B1->B0 | 2424 2f2f | 0 0 | (0 0) (0 0)
5764 22:12:52.986694 0 15 28 | B1->B0 | 3938 4646 | 1 0 | (0 0) (0 0)
5765 22:12:52.989641 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5766 22:12:52.992739 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5767 22:12:52.999657 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5768 22:12:53.002654 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5769 22:12:53.006049 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5770 22:12:53.012702 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5771 22:12:53.015894 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5772 22:12:53.019348 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5773 22:12:53.025638 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 22:12:53.029903 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 22:12:53.032793 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 22:12:53.039243 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 22:12:53.042575 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 22:12:53.045737 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 22:12:53.052093 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 22:12:53.055483 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 22:12:53.059595 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 22:12:53.065759 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 22:12:53.068834 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 22:12:53.071795 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 22:12:53.078372 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 22:12:53.081805 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 22:12:53.085069 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 22:12:53.091829 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5789 22:12:53.092287 Total UI for P1: 0, mck2ui 16
5790 22:12:53.095195 best dqsien dly found for B0: ( 1, 2, 26)
5791 22:12:53.101781 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5792 22:12:53.105061 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5793 22:12:53.108194 Total UI for P1: 0, mck2ui 16
5794 22:12:53.111618 best dqsien dly found for B1: ( 1, 2, 30)
5795 22:12:53.114897 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5796 22:12:53.117903 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5797 22:12:53.118323
5798 22:12:53.121433 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5799 22:12:53.127872 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5800 22:12:53.128289 [Gating] SW calibration Done
5801 22:12:53.128623 ==
5802 22:12:53.131200 Dram Type= 6, Freq= 0, CH_1, rank 1
5803 22:12:53.138318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5804 22:12:53.138737 ==
5805 22:12:53.139070 RX Vref Scan: 0
5806 22:12:53.139411
5807 22:12:53.140997 RX Vref 0 -> 0, step: 1
5808 22:12:53.141416
5809 22:12:53.144193 RX Delay -80 -> 252, step: 8
5810 22:12:53.147873 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5811 22:12:53.150661 iDelay=200, Bit 1, Center 95 (0 ~ 191) 192
5812 22:12:53.154407 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5813 22:12:53.160879 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5814 22:12:53.164363 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5815 22:12:53.167389 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5816 22:12:53.171353 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5817 22:12:53.174304 iDelay=200, Bit 7, Center 95 (0 ~ 191) 192
5818 22:12:53.177450 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5819 22:12:53.183692 iDelay=200, Bit 9, Center 83 (-8 ~ 175) 184
5820 22:12:53.186888 iDelay=200, Bit 10, Center 95 (0 ~ 191) 192
5821 22:12:53.190495 iDelay=200, Bit 11, Center 87 (-8 ~ 183) 192
5822 22:12:53.193691 iDelay=200, Bit 12, Center 103 (8 ~ 199) 192
5823 22:12:53.197105 iDelay=200, Bit 13, Center 103 (8 ~ 199) 192
5824 22:12:53.200836 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5825 22:12:53.207050 iDelay=200, Bit 15, Center 103 (8 ~ 199) 192
5826 22:12:53.207537 ==
5827 22:12:53.210439 Dram Type= 6, Freq= 0, CH_1, rank 1
5828 22:12:53.214674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5829 22:12:53.215242 ==
5830 22:12:53.215597 DQS Delay:
5831 22:12:53.216845 DQS0 = 0, DQS1 = 0
5832 22:12:53.217257 DQM Delay:
5833 22:12:53.219993 DQM0 = 96, DQM1 = 94
5834 22:12:53.220419 DQ Delay:
5835 22:12:53.223359 DQ0 =99, DQ1 =95, DQ2 =87, DQ3 =95
5836 22:12:53.226540 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =95
5837 22:12:53.230382 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5838 22:12:53.233216 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5839 22:12:53.233744
5840 22:12:53.234080
5841 22:12:53.234390 ==
5842 22:12:53.236521 Dram Type= 6, Freq= 0, CH_1, rank 1
5843 22:12:53.243341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5844 22:12:53.243917 ==
5845 22:12:53.244292
5846 22:12:53.244633
5847 22:12:53.246358 TX Vref Scan disable
5848 22:12:53.246819 == TX Byte 0 ==
5849 22:12:53.249708 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5850 22:12:53.256221 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5851 22:12:53.256644 == TX Byte 1 ==
5852 22:12:53.262515 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5853 22:12:53.266261 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5854 22:12:53.266683 ==
5855 22:12:53.269289 Dram Type= 6, Freq= 0, CH_1, rank 1
5856 22:12:53.272532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5857 22:12:53.272956 ==
5858 22:12:53.273308
5859 22:12:53.273621
5860 22:12:53.275734 TX Vref Scan disable
5861 22:12:53.279530 == TX Byte 0 ==
5862 22:12:53.282729 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5863 22:12:53.285557 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5864 22:12:53.288757 == TX Byte 1 ==
5865 22:12:53.292160 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5866 22:12:53.295427 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5867 22:12:53.295848
5868 22:12:53.298689 [DATLAT]
5869 22:12:53.299108 Freq=933, CH1 RK1
5870 22:12:53.299497
5871 22:12:53.301954 DATLAT Default: 0xb
5872 22:12:53.302379 0, 0xFFFF, sum = 0
5873 22:12:53.305402 1, 0xFFFF, sum = 0
5874 22:12:53.305849 2, 0xFFFF, sum = 0
5875 22:12:53.308692 3, 0xFFFF, sum = 0
5876 22:12:53.309137 4, 0xFFFF, sum = 0
5877 22:12:53.311683 5, 0xFFFF, sum = 0
5878 22:12:53.312134 6, 0xFFFF, sum = 0
5879 22:12:53.315716 7, 0xFFFF, sum = 0
5880 22:12:53.316157 8, 0xFFFF, sum = 0
5881 22:12:53.319283 9, 0xFFFF, sum = 0
5882 22:12:53.319725 10, 0x0, sum = 1
5883 22:12:53.321741 11, 0x0, sum = 2
5884 22:12:53.322187 12, 0x0, sum = 3
5885 22:12:53.324887 13, 0x0, sum = 4
5886 22:12:53.325314 best_step = 11
5887 22:12:53.325648
5888 22:12:53.325973 ==
5889 22:12:53.328460 Dram Type= 6, Freq= 0, CH_1, rank 1
5890 22:12:53.335324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5891 22:12:53.335868 ==
5892 22:12:53.336215 RX Vref Scan: 0
5893 22:12:53.336531
5894 22:12:53.338549 RX Vref 0 -> 0, step: 1
5895 22:12:53.339060
5896 22:12:53.341645 RX Delay -53 -> 252, step: 4
5897 22:12:53.344760 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5898 22:12:53.351398 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5899 22:12:53.355013 iDelay=199, Bit 2, Center 86 (-5 ~ 178) 184
5900 22:12:53.358263 iDelay=199, Bit 3, Center 94 (3 ~ 186) 184
5901 22:12:53.361076 iDelay=199, Bit 4, Center 98 (7 ~ 190) 184
5902 22:12:53.364628 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5903 22:12:53.367707 iDelay=199, Bit 6, Center 104 (15 ~ 194) 180
5904 22:12:53.374424 iDelay=199, Bit 7, Center 94 (3 ~ 186) 184
5905 22:12:53.377599 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5906 22:12:53.380862 iDelay=199, Bit 9, Center 84 (-9 ~ 178) 188
5907 22:12:53.384392 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5908 22:12:53.387594 iDelay=199, Bit 11, Center 84 (-9 ~ 178) 188
5909 22:12:53.394372 iDelay=199, Bit 12, Center 98 (7 ~ 190) 184
5910 22:12:53.397136 iDelay=199, Bit 13, Center 100 (11 ~ 190) 180
5911 22:12:53.400465 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5912 22:12:53.404202 iDelay=199, Bit 15, Center 102 (11 ~ 194) 184
5913 22:12:53.404622 ==
5914 22:12:53.407326 Dram Type= 6, Freq= 0, CH_1, rank 1
5915 22:12:53.414182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5916 22:12:53.414858 ==
5917 22:12:53.415262 DQS Delay:
5918 22:12:53.415587 DQS0 = 0, DQS1 = 0
5919 22:12:53.417372 DQM Delay:
5920 22:12:53.417789 DQM0 = 97, DQM1 = 92
5921 22:12:53.420779 DQ Delay:
5922 22:12:53.423838 DQ0 =102, DQ1 =94, DQ2 =86, DQ3 =94
5923 22:12:53.426927 DQ4 =98, DQ5 =106, DQ6 =104, DQ7 =94
5924 22:12:53.430247 DQ8 =80, DQ9 =84, DQ10 =92, DQ11 =84
5925 22:12:53.434223 DQ12 =98, DQ13 =100, DQ14 =98, DQ15 =102
5926 22:12:53.434752
5927 22:12:53.435091
5928 22:12:53.440026 [DQSOSCAuto] RK1, (LSB)MR18= 0xe25, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 417 ps
5929 22:12:53.443673 CH1 RK1: MR19=505, MR18=E25
5930 22:12:53.450176 CH1_RK1: MR19=0x505, MR18=0xE25, DQSOSC=410, MR23=63, INC=64, DEC=42
5931 22:12:53.453225 [RxdqsGatingPostProcess] freq 933
5932 22:12:53.456751 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5933 22:12:53.460189 best DQS0 dly(2T, 0.5T) = (0, 10)
5934 22:12:53.463277 best DQS1 dly(2T, 0.5T) = (0, 10)
5935 22:12:53.466522 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5936 22:12:53.470278 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5937 22:12:53.473182 best DQS0 dly(2T, 0.5T) = (0, 10)
5938 22:12:53.476322 best DQS1 dly(2T, 0.5T) = (0, 10)
5939 22:12:53.480043 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5940 22:12:53.482828 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5941 22:12:53.486200 Pre-setting of DQS Precalculation
5942 22:12:53.492563 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5943 22:12:53.499002 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5944 22:12:53.505599 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5945 22:12:53.506026
5946 22:12:53.506407
5947 22:12:53.509009 [Calibration Summary] 1866 Mbps
5948 22:12:53.509430 CH 0, Rank 0
5949 22:12:53.512661 SW Impedance : PASS
5950 22:12:53.516373 DUTY Scan : NO K
5951 22:12:53.516983 ZQ Calibration : PASS
5952 22:12:53.519110 Jitter Meter : NO K
5953 22:12:53.522394 CBT Training : PASS
5954 22:12:53.522817 Write leveling : PASS
5955 22:12:53.525524 RX DQS gating : PASS
5956 22:12:53.528675 RX DQ/DQS(RDDQC) : PASS
5957 22:12:53.529101 TX DQ/DQS : PASS
5958 22:12:53.532211 RX DATLAT : PASS
5959 22:12:53.532673 RX DQ/DQS(Engine): PASS
5960 22:12:53.535697 TX OE : NO K
5961 22:12:53.536137 All Pass.
5962 22:12:53.536477
5963 22:12:53.538877 CH 0, Rank 1
5964 22:12:53.539324 SW Impedance : PASS
5965 22:12:53.542098 DUTY Scan : NO K
5966 22:12:53.545497 ZQ Calibration : PASS
5967 22:12:53.546031 Jitter Meter : NO K
5968 22:12:53.548868 CBT Training : PASS
5969 22:12:53.551782 Write leveling : PASS
5970 22:12:53.552204 RX DQS gating : PASS
5971 22:12:53.555199 RX DQ/DQS(RDDQC) : PASS
5972 22:12:53.558789 TX DQ/DQS : PASS
5973 22:12:53.559354 RX DATLAT : PASS
5974 22:12:53.561516 RX DQ/DQS(Engine): PASS
5975 22:12:53.565091 TX OE : NO K
5976 22:12:53.565516 All Pass.
5977 22:12:53.565872
5978 22:12:53.566186 CH 1, Rank 0
5979 22:12:53.569045 SW Impedance : PASS
5980 22:12:53.571324 DUTY Scan : NO K
5981 22:12:53.571748 ZQ Calibration : PASS
5982 22:12:53.575134 Jitter Meter : NO K
5983 22:12:53.578734 CBT Training : PASS
5984 22:12:53.579158 Write leveling : PASS
5985 22:12:53.581561 RX DQS gating : PASS
5986 22:12:53.585540 RX DQ/DQS(RDDQC) : PASS
5987 22:12:53.586043 TX DQ/DQS : PASS
5988 22:12:53.588503 RX DATLAT : PASS
5989 22:12:53.591666 RX DQ/DQS(Engine): PASS
5990 22:12:53.592091 TX OE : NO K
5991 22:12:53.595002 All Pass.
5992 22:12:53.595526
5993 22:12:53.595878 CH 1, Rank 1
5994 22:12:53.598140 SW Impedance : PASS
5995 22:12:53.598571 DUTY Scan : NO K
5996 22:12:53.601914 ZQ Calibration : PASS
5997 22:12:53.604730 Jitter Meter : NO K
5998 22:12:53.605167 CBT Training : PASS
5999 22:12:53.608323 Write leveling : PASS
6000 22:12:53.611233 RX DQS gating : PASS
6001 22:12:53.611654 RX DQ/DQS(RDDQC) : PASS
6002 22:12:53.614394 TX DQ/DQS : PASS
6003 22:12:53.617991 RX DATLAT : PASS
6004 22:12:53.618436 RX DQ/DQS(Engine): PASS
6005 22:12:53.621262 TX OE : NO K
6006 22:12:53.621729 All Pass.
6007 22:12:53.622083
6008 22:12:53.624453 DramC Write-DBI off
6009 22:12:53.627953 PER_BANK_REFRESH: Hybrid Mode
6010 22:12:53.628377 TX_TRACKING: ON
6011 22:12:53.637396 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6012 22:12:53.640693 [FAST_K] Save calibration result to emmc
6013 22:12:53.644005 dramc_set_vcore_voltage set vcore to 650000
6014 22:12:53.647280 Read voltage for 400, 6
6015 22:12:53.647706 Vio18 = 0
6016 22:12:53.648045 Vcore = 650000
6017 22:12:53.650302 Vdram = 0
6018 22:12:53.650722 Vddq = 0
6019 22:12:53.651056 Vmddr = 0
6020 22:12:53.657420 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6021 22:12:53.660385 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6022 22:12:53.663866 MEM_TYPE=3, freq_sel=20
6023 22:12:53.667298 sv_algorithm_assistance_LP4_800
6024 22:12:53.670211 ============ PULL DRAM RESETB DOWN ============
6025 22:12:53.673559 ========== PULL DRAM RESETB DOWN end =========
6026 22:12:53.679966 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6027 22:12:53.683725 ===================================
6028 22:12:53.686717 LPDDR4 DRAM CONFIGURATION
6029 22:12:53.690543 ===================================
6030 22:12:53.690966 EX_ROW_EN[0] = 0x0
6031 22:12:53.693675 EX_ROW_EN[1] = 0x0
6032 22:12:53.694113 LP4Y_EN = 0x0
6033 22:12:53.696314 WORK_FSP = 0x0
6034 22:12:53.696737 WL = 0x2
6035 22:12:53.700049 RL = 0x2
6036 22:12:53.700489 BL = 0x2
6037 22:12:53.703441 RPST = 0x0
6038 22:12:53.703879 RD_PRE = 0x0
6039 22:12:53.706398 WR_PRE = 0x1
6040 22:12:53.706835 WR_PST = 0x0
6041 22:12:53.709917 DBI_WR = 0x0
6042 22:12:53.713465 DBI_RD = 0x0
6043 22:12:53.713905 OTF = 0x1
6044 22:12:53.716242 ===================================
6045 22:12:53.719535 ===================================
6046 22:12:53.719962 ANA top config
6047 22:12:53.723116 ===================================
6048 22:12:53.726176 DLL_ASYNC_EN = 0
6049 22:12:53.730057 ALL_SLAVE_EN = 1
6050 22:12:53.732850 NEW_RANK_MODE = 1
6051 22:12:53.736115 DLL_IDLE_MODE = 1
6052 22:12:53.736557 LP45_APHY_COMB_EN = 1
6053 22:12:53.739502 TX_ODT_DIS = 1
6054 22:12:53.742782 NEW_8X_MODE = 1
6055 22:12:53.745940 ===================================
6056 22:12:53.749615 ===================================
6057 22:12:53.752403 data_rate = 800
6058 22:12:53.755874 CKR = 1
6059 22:12:53.759823 DQ_P2S_RATIO = 4
6060 22:12:53.762332 ===================================
6061 22:12:53.762759 CA_P2S_RATIO = 4
6062 22:12:53.765875 DQ_CA_OPEN = 0
6063 22:12:53.769075 DQ_SEMI_OPEN = 1
6064 22:12:53.772397 CA_SEMI_OPEN = 1
6065 22:12:53.775618 CA_FULL_RATE = 0
6066 22:12:53.779032 DQ_CKDIV4_EN = 0
6067 22:12:53.779472 CA_CKDIV4_EN = 1
6068 22:12:53.782179 CA_PREDIV_EN = 0
6069 22:12:53.785171 PH8_DLY = 0
6070 22:12:53.788781 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6071 22:12:53.792274 DQ_AAMCK_DIV = 0
6072 22:12:53.795314 CA_AAMCK_DIV = 0
6073 22:12:53.795784 CA_ADMCK_DIV = 4
6074 22:12:53.798520 DQ_TRACK_CA_EN = 0
6075 22:12:53.802386 CA_PICK = 800
6076 22:12:53.804891 CA_MCKIO = 400
6077 22:12:53.808822 MCKIO_SEMI = 400
6078 22:12:53.811983 PLL_FREQ = 3016
6079 22:12:53.815267 DQ_UI_PI_RATIO = 32
6080 22:12:53.818689 CA_UI_PI_RATIO = 32
6081 22:12:53.821873 ===================================
6082 22:12:53.824871 ===================================
6083 22:12:53.825323 memory_type:LPDDR4
6084 22:12:53.828747 GP_NUM : 10
6085 22:12:53.831611 SRAM_EN : 1
6086 22:12:53.832089 MD32_EN : 0
6087 22:12:53.834694 ===================================
6088 22:12:53.838072 [ANA_INIT] >>>>>>>>>>>>>>
6089 22:12:53.841526 <<<<<< [CONFIGURE PHASE]: ANA_TX
6090 22:12:53.844630 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6091 22:12:53.847742 ===================================
6092 22:12:53.851053 data_rate = 800,PCW = 0X7400
6093 22:12:53.854772 ===================================
6094 22:12:53.857886 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6095 22:12:53.861190 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6096 22:12:53.874479 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6097 22:12:53.878148 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6098 22:12:53.881542 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6099 22:12:53.884407 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6100 22:12:53.887719 [ANA_INIT] flow start
6101 22:12:53.891258 [ANA_INIT] PLL >>>>>>>>
6102 22:12:53.891842 [ANA_INIT] PLL <<<<<<<<
6103 22:12:53.894217 [ANA_INIT] MIDPI >>>>>>>>
6104 22:12:53.897758 [ANA_INIT] MIDPI <<<<<<<<
6105 22:12:53.898413 [ANA_INIT] DLL >>>>>>>>
6106 22:12:53.900665 [ANA_INIT] flow end
6107 22:12:53.904027 ============ LP4 DIFF to SE enter ============
6108 22:12:53.907701 ============ LP4 DIFF to SE exit ============
6109 22:12:53.910738 [ANA_INIT] <<<<<<<<<<<<<
6110 22:12:53.913765 [Flow] Enable top DCM control >>>>>
6111 22:12:53.917162 [Flow] Enable top DCM control <<<<<
6112 22:12:53.920504 Enable DLL master slave shuffle
6113 22:12:53.926850 ==============================================================
6114 22:12:53.927396 Gating Mode config
6115 22:12:53.934166 ==============================================================
6116 22:12:53.936856 Config description:
6117 22:12:53.943676 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6118 22:12:53.949906 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6119 22:12:53.956718 SELPH_MODE 0: By rank 1: By Phase
6120 22:12:53.962925 ==============================================================
6121 22:12:53.966690 GAT_TRACK_EN = 0
6122 22:12:53.967112 RX_GATING_MODE = 2
6123 22:12:53.969716 RX_GATING_TRACK_MODE = 2
6124 22:12:53.973073 SELPH_MODE = 1
6125 22:12:53.976508 PICG_EARLY_EN = 1
6126 22:12:53.980670 VALID_LAT_VALUE = 1
6127 22:12:53.986718 ==============================================================
6128 22:12:53.989792 Enter into Gating configuration >>>>
6129 22:12:53.993174 Exit from Gating configuration <<<<
6130 22:12:53.996087 Enter into DVFS_PRE_config >>>>>
6131 22:12:54.005880 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6132 22:12:54.009713 Exit from DVFS_PRE_config <<<<<
6133 22:12:54.012897 Enter into PICG configuration >>>>
6134 22:12:54.015937 Exit from PICG configuration <<<<
6135 22:12:54.019748 [RX_INPUT] configuration >>>>>
6136 22:12:54.022802 [RX_INPUT] configuration <<<<<
6137 22:12:54.025729 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6138 22:12:54.032376 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6139 22:12:54.039734 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6140 22:12:54.045534 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6141 22:12:54.051883 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6142 22:12:54.055544 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6143 22:12:54.062355 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6144 22:12:54.065192 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6145 22:12:54.069266 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6146 22:12:54.071867 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6147 22:12:54.078736 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6148 22:12:54.082230 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6149 22:12:54.085664 ===================================
6150 22:12:54.089023 LPDDR4 DRAM CONFIGURATION
6151 22:12:54.091726 ===================================
6152 22:12:54.092148 EX_ROW_EN[0] = 0x0
6153 22:12:54.095494 EX_ROW_EN[1] = 0x0
6154 22:12:54.095994 LP4Y_EN = 0x0
6155 22:12:54.098114 WORK_FSP = 0x0
6156 22:12:54.098736 WL = 0x2
6157 22:12:54.101375 RL = 0x2
6158 22:12:54.101909 BL = 0x2
6159 22:12:54.105516 RPST = 0x0
6160 22:12:54.108865 RD_PRE = 0x0
6161 22:12:54.109380 WR_PRE = 0x1
6162 22:12:54.111639 WR_PST = 0x0
6163 22:12:54.112058 DBI_WR = 0x0
6164 22:12:54.114445 DBI_RD = 0x0
6165 22:12:54.114860 OTF = 0x1
6166 22:12:54.117841 ===================================
6167 22:12:54.121239 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6168 22:12:54.127929 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6169 22:12:54.131323 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6170 22:12:54.134563 ===================================
6171 22:12:54.137757 LPDDR4 DRAM CONFIGURATION
6172 22:12:54.141153 ===================================
6173 22:12:54.141575 EX_ROW_EN[0] = 0x10
6174 22:12:54.144462 EX_ROW_EN[1] = 0x0
6175 22:12:54.144878 LP4Y_EN = 0x0
6176 22:12:54.147451 WORK_FSP = 0x0
6177 22:12:54.150942 WL = 0x2
6178 22:12:54.151436 RL = 0x2
6179 22:12:54.153927 BL = 0x2
6180 22:12:54.154410 RPST = 0x0
6181 22:12:54.157335 RD_PRE = 0x0
6182 22:12:54.157872 WR_PRE = 0x1
6183 22:12:54.161017 WR_PST = 0x0
6184 22:12:54.161432 DBI_WR = 0x0
6185 22:12:54.163946 DBI_RD = 0x0
6186 22:12:54.164365 OTF = 0x1
6187 22:12:54.167099 ===================================
6188 22:12:54.173978 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6189 22:12:54.177964 nWR fixed to 30
6190 22:12:54.181164 [ModeRegInit_LP4] CH0 RK0
6191 22:12:54.181585 [ModeRegInit_LP4] CH0 RK1
6192 22:12:54.185126 [ModeRegInit_LP4] CH1 RK0
6193 22:12:54.187592 [ModeRegInit_LP4] CH1 RK1
6194 22:12:54.188013 match AC timing 19
6195 22:12:54.194889 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6196 22:12:54.197649 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6197 22:12:54.200899 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6198 22:12:54.207645 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6199 22:12:54.210627 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6200 22:12:54.211045 ==
6201 22:12:54.214081 Dram Type= 6, Freq= 0, CH_0, rank 0
6202 22:12:54.217395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6203 22:12:54.217916 ==
6204 22:12:54.223999 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6205 22:12:54.230478 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6206 22:12:54.233902 [CA 0] Center 36 (8~64) winsize 57
6207 22:12:54.236978 [CA 1] Center 36 (8~64) winsize 57
6208 22:12:54.241039 [CA 2] Center 36 (8~64) winsize 57
6209 22:12:54.243580 [CA 3] Center 36 (8~64) winsize 57
6210 22:12:54.247112 [CA 4] Center 36 (8~64) winsize 57
6211 22:12:54.250035 [CA 5] Center 36 (8~64) winsize 57
6212 22:12:54.250457
6213 22:12:54.253378 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6214 22:12:54.253839
6215 22:12:54.257305 [CATrainingPosCal] consider 1 rank data
6216 22:12:54.260054 u2DelayCellTimex100 = 270/100 ps
6217 22:12:54.263493 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6218 22:12:54.266858 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6219 22:12:54.269649 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6220 22:12:54.273179 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6221 22:12:54.276507 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6222 22:12:54.279789 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6223 22:12:54.280206
6224 22:12:54.286202 CA PerBit enable=1, Macro0, CA PI delay=36
6225 22:12:54.286622
6226 22:12:54.289994 [CBTSetCACLKResult] CA Dly = 36
6227 22:12:54.290410 CS Dly: 1 (0~32)
6228 22:12:54.290742 ==
6229 22:12:54.292890 Dram Type= 6, Freq= 0, CH_0, rank 1
6230 22:12:54.296334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6231 22:12:54.296878 ==
6232 22:12:54.303426 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6233 22:12:54.309760 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6234 22:12:54.313000 [CA 0] Center 36 (8~64) winsize 57
6235 22:12:54.316699 [CA 1] Center 36 (8~64) winsize 57
6236 22:12:54.319445 [CA 2] Center 36 (8~64) winsize 57
6237 22:12:54.322882 [CA 3] Center 36 (8~64) winsize 57
6238 22:12:54.326122 [CA 4] Center 36 (8~64) winsize 57
6239 22:12:54.329720 [CA 5] Center 36 (8~64) winsize 57
6240 22:12:54.330292
6241 22:12:54.332930 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6242 22:12:54.333445
6243 22:12:54.336091 [CATrainingPosCal] consider 2 rank data
6244 22:12:54.339242 u2DelayCellTimex100 = 270/100 ps
6245 22:12:54.342970 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 22:12:54.345675 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 22:12:54.349001 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 22:12:54.352074 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 22:12:54.355281 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 22:12:54.358890 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 22:12:54.359495
6252 22:12:54.365580 CA PerBit enable=1, Macro0, CA PI delay=36
6253 22:12:54.365994
6254 22:12:54.366320 [CBTSetCACLKResult] CA Dly = 36
6255 22:12:54.369227 CS Dly: 1 (0~32)
6256 22:12:54.369762
6257 22:12:54.371826 ----->DramcWriteLeveling(PI) begin...
6258 22:12:54.372245 ==
6259 22:12:54.375126 Dram Type= 6, Freq= 0, CH_0, rank 0
6260 22:12:54.378643 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6261 22:12:54.379123 ==
6262 22:12:54.382112 Write leveling (Byte 0): 40 => 8
6263 22:12:54.385224 Write leveling (Byte 1): 40 => 8
6264 22:12:54.388604 DramcWriteLeveling(PI) end<-----
6265 22:12:54.389078
6266 22:12:54.389416 ==
6267 22:12:54.391753 Dram Type= 6, Freq= 0, CH_0, rank 0
6268 22:12:54.394800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6269 22:12:54.398362 ==
6270 22:12:54.398784 [Gating] SW mode calibration
6271 22:12:54.408136 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6272 22:12:54.410980 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6273 22:12:54.414589 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6274 22:12:54.421260 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6275 22:12:54.424302 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6276 22:12:54.427775 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6277 22:12:54.434660 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6278 22:12:54.438111 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6279 22:12:54.441231 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6280 22:12:54.447724 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6281 22:12:54.451347 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6282 22:12:54.455103 Total UI for P1: 0, mck2ui 16
6283 22:12:54.457338 best dqsien dly found for B0: ( 0, 14, 24)
6284 22:12:54.460983 Total UI for P1: 0, mck2ui 16
6285 22:12:54.464227 best dqsien dly found for B1: ( 0, 14, 24)
6286 22:12:54.467301 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6287 22:12:54.470485 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6288 22:12:54.470924
6289 22:12:54.474481 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6290 22:12:54.480460 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6291 22:12:54.480903 [Gating] SW calibration Done
6292 22:12:54.483779 ==
6293 22:12:54.484220 Dram Type= 6, Freq= 0, CH_0, rank 0
6294 22:12:54.490195 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6295 22:12:54.490635 ==
6296 22:12:54.490971 RX Vref Scan: 0
6297 22:12:54.491352
6298 22:12:54.493790 RX Vref 0 -> 0, step: 1
6299 22:12:54.494232
6300 22:12:54.497195 RX Delay -410 -> 252, step: 16
6301 22:12:54.500469 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6302 22:12:54.503512 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6303 22:12:54.510472 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6304 22:12:54.513568 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6305 22:12:54.516871 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6306 22:12:54.523474 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6307 22:12:54.526616 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6308 22:12:54.529543 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6309 22:12:54.532875 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6310 22:12:54.539430 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6311 22:12:54.543469 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6312 22:12:54.546832 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6313 22:12:54.549683 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6314 22:12:54.556188 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6315 22:12:54.559212 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6316 22:12:54.562533 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6317 22:12:54.562940 ==
6318 22:12:54.565811 Dram Type= 6, Freq= 0, CH_0, rank 0
6319 22:12:54.572734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6320 22:12:54.573142 ==
6321 22:12:54.573465 DQS Delay:
6322 22:12:54.575891 DQS0 = 35, DQS1 = 51
6323 22:12:54.576294 DQM Delay:
6324 22:12:54.576616 DQM0 = 4, DQM1 = 10
6325 22:12:54.579034 DQ Delay:
6326 22:12:54.583062 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6327 22:12:54.583506 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6328 22:12:54.586199 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6329 22:12:54.589061 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6330 22:12:54.589538
6331 22:12:54.592217
6332 22:12:54.592643 ==
6333 22:12:54.595863 Dram Type= 6, Freq= 0, CH_0, rank 0
6334 22:12:54.598746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6335 22:12:54.599391 ==
6336 22:12:54.599752
6337 22:12:54.600061
6338 22:12:54.602210 TX Vref Scan disable
6339 22:12:54.602569 == TX Byte 0 ==
6340 22:12:54.605408 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6341 22:12:54.612240 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6342 22:12:54.612783 == TX Byte 1 ==
6343 22:12:54.615318 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6344 22:12:54.622160 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6345 22:12:54.622593 ==
6346 22:12:54.625370 Dram Type= 6, Freq= 0, CH_0, rank 0
6347 22:12:54.628854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6348 22:12:54.629268 ==
6349 22:12:54.629613
6350 22:12:54.629923
6351 22:12:54.631783 TX Vref Scan disable
6352 22:12:54.632193 == TX Byte 0 ==
6353 22:12:54.638584 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6354 22:12:54.642100 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6355 22:12:54.642533 == TX Byte 1 ==
6356 22:12:54.648783 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6357 22:12:54.651961 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6358 22:12:54.652373
6359 22:12:54.652722 [DATLAT]
6360 22:12:54.654817 Freq=400, CH0 RK0
6361 22:12:54.655277
6362 22:12:54.655634 DATLAT Default: 0xf
6363 22:12:54.657995 0, 0xFFFF, sum = 0
6364 22:12:54.658433 1, 0xFFFF, sum = 0
6365 22:12:54.661454 2, 0xFFFF, sum = 0
6366 22:12:54.661892 3, 0xFFFF, sum = 0
6367 22:12:54.665061 4, 0xFFFF, sum = 0
6368 22:12:54.665499 5, 0xFFFF, sum = 0
6369 22:12:54.668471 6, 0xFFFF, sum = 0
6370 22:12:54.668916 7, 0xFFFF, sum = 0
6371 22:12:54.671340 8, 0xFFFF, sum = 0
6372 22:12:54.671789 9, 0xFFFF, sum = 0
6373 22:12:54.675107 10, 0xFFFF, sum = 0
6374 22:12:54.678045 11, 0xFFFF, sum = 0
6375 22:12:54.678470 12, 0xFFFF, sum = 0
6376 22:12:54.681293 13, 0x0, sum = 1
6377 22:12:54.681722 14, 0x0, sum = 2
6378 22:12:54.682078 15, 0x0, sum = 3
6379 22:12:54.684822 16, 0x0, sum = 4
6380 22:12:54.685253 best_step = 14
6381 22:12:54.685636
6382 22:12:54.687998 ==
6383 22:12:54.688432 Dram Type= 6, Freq= 0, CH_0, rank 0
6384 22:12:54.694712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6385 22:12:54.695157 ==
6386 22:12:54.695576 RX Vref Scan: 1
6387 22:12:54.695899
6388 22:12:54.697421 RX Vref 0 -> 0, step: 1
6389 22:12:54.697860
6390 22:12:54.701214 RX Delay -343 -> 252, step: 8
6391 22:12:54.701682
6392 22:12:54.704533 Set Vref, RX VrefLevel [Byte0]: 51
6393 22:12:54.707522 [Byte1]: 59
6394 22:12:54.711473
6395 22:12:54.711899 Final RX Vref Byte 0 = 51 to rank0
6396 22:12:54.715040 Final RX Vref Byte 1 = 59 to rank0
6397 22:12:54.718137 Final RX Vref Byte 0 = 51 to rank1
6398 22:12:54.720799 Final RX Vref Byte 1 = 59 to rank1==
6399 22:12:54.724248 Dram Type= 6, Freq= 0, CH_0, rank 0
6400 22:12:54.730800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6401 22:12:54.731427 ==
6402 22:12:54.731950 DQS Delay:
6403 22:12:54.734602 DQS0 = 44, DQS1 = 60
6404 22:12:54.735035 DQM Delay:
6405 22:12:54.737820 DQM0 = 10, DQM1 = 17
6406 22:12:54.738238 DQ Delay:
6407 22:12:54.740669 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6408 22:12:54.744091 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6409 22:12:54.747047 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =8
6410 22:12:54.750802 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =24
6411 22:12:54.751319
6412 22:12:54.751679
6413 22:12:54.757457 [DQSOSCAuto] RK0, (LSB)MR18= 0x978a, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
6414 22:12:54.760147 CH0 RK0: MR19=C0C, MR18=978A
6415 22:12:54.767160 CH0_RK0: MR19=0xC0C, MR18=0x978A, DQSOSC=390, MR23=63, INC=388, DEC=258
6416 22:12:54.767620 ==
6417 22:12:54.770574 Dram Type= 6, Freq= 0, CH_0, rank 1
6418 22:12:54.773475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6419 22:12:54.773916 ==
6420 22:12:54.776903 [Gating] SW mode calibration
6421 22:12:54.783126 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6422 22:12:54.789863 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6423 22:12:54.794391 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6424 22:12:54.796558 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6425 22:12:54.803113 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6426 22:12:54.806714 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6427 22:12:54.809776 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6428 22:12:54.816395 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6429 22:12:54.819547 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6430 22:12:54.823010 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6431 22:12:54.830023 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6432 22:12:54.833017 Total UI for P1: 0, mck2ui 16
6433 22:12:54.836337 best dqsien dly found for B0: ( 0, 14, 24)
6434 22:12:54.839525 Total UI for P1: 0, mck2ui 16
6435 22:12:54.842560 best dqsien dly found for B1: ( 0, 14, 24)
6436 22:12:54.846094 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6437 22:12:54.849411 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6438 22:12:54.849828
6439 22:12:54.852881 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6440 22:12:54.855945 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6441 22:12:54.859201 [Gating] SW calibration Done
6442 22:12:54.859617 ==
6443 22:12:54.862565 Dram Type= 6, Freq= 0, CH_0, rank 1
6444 22:12:54.865802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6445 22:12:54.866222 ==
6446 22:12:54.869155 RX Vref Scan: 0
6447 22:12:54.869579
6448 22:12:54.872656 RX Vref 0 -> 0, step: 1
6449 22:12:54.873236
6450 22:12:54.875771 RX Delay -410 -> 252, step: 16
6451 22:12:54.879091 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6452 22:12:54.882295 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6453 22:12:54.885990 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6454 22:12:54.892653 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6455 22:12:54.895491 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6456 22:12:54.898977 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6457 22:12:54.902558 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6458 22:12:54.908311 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6459 22:12:54.911778 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6460 22:12:54.915191 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6461 22:12:54.921749 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6462 22:12:54.925184 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6463 22:12:54.928431 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6464 22:12:54.931693 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6465 22:12:54.937943 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6466 22:12:54.941249 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6467 22:12:54.941666 ==
6468 22:12:54.944715 Dram Type= 6, Freq= 0, CH_0, rank 1
6469 22:12:54.947844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6470 22:12:54.948267 ==
6471 22:12:54.951216 DQS Delay:
6472 22:12:54.951720 DQS0 = 35, DQS1 = 59
6473 22:12:54.954630 DQM Delay:
6474 22:12:54.955047 DQM0 = 7, DQM1 = 16
6475 22:12:54.955452 DQ Delay:
6476 22:12:54.957674 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6477 22:12:54.961358 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6478 22:12:54.964571 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6479 22:12:54.967833 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6480 22:12:54.968249
6481 22:12:54.968577
6482 22:12:54.968887 ==
6483 22:12:54.970899 Dram Type= 6, Freq= 0, CH_0, rank 1
6484 22:12:54.978187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6485 22:12:54.978708 ==
6486 22:12:54.979049
6487 22:12:54.979389
6488 22:12:54.979687 TX Vref Scan disable
6489 22:12:54.981104 == TX Byte 0 ==
6490 22:12:54.983923 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6491 22:12:54.987246 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6492 22:12:54.990746 == TX Byte 1 ==
6493 22:12:54.994163 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6494 22:12:54.997414 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6495 22:12:54.997839 ==
6496 22:12:55.001012 Dram Type= 6, Freq= 0, CH_0, rank 1
6497 22:12:55.007139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6498 22:12:55.007600 ==
6499 22:12:55.007935
6500 22:12:55.008240
6501 22:12:55.010339 TX Vref Scan disable
6502 22:12:55.010754 == TX Byte 0 ==
6503 22:12:55.013543 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6504 22:12:55.017260 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6505 22:12:55.020086 == TX Byte 1 ==
6506 22:12:55.023386 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6507 22:12:55.026666 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6508 22:12:55.030065
6509 22:12:55.030497 [DATLAT]
6510 22:12:55.030826 Freq=400, CH0 RK1
6511 22:12:55.031137
6512 22:12:55.033460 DATLAT Default: 0xe
6513 22:12:55.033876 0, 0xFFFF, sum = 0
6514 22:12:55.036512 1, 0xFFFF, sum = 0
6515 22:12:55.036935 2, 0xFFFF, sum = 0
6516 22:12:55.040063 3, 0xFFFF, sum = 0
6517 22:12:55.043662 4, 0xFFFF, sum = 0
6518 22:12:55.044085 5, 0xFFFF, sum = 0
6519 22:12:55.047068 6, 0xFFFF, sum = 0
6520 22:12:55.047541 7, 0xFFFF, sum = 0
6521 22:12:55.049692 8, 0xFFFF, sum = 0
6522 22:12:55.050114 9, 0xFFFF, sum = 0
6523 22:12:55.053477 10, 0xFFFF, sum = 0
6524 22:12:55.054001 11, 0xFFFF, sum = 0
6525 22:12:55.056818 12, 0xFFFF, sum = 0
6526 22:12:55.057245 13, 0x0, sum = 1
6527 22:12:55.059709 14, 0x0, sum = 2
6528 22:12:55.060133 15, 0x0, sum = 3
6529 22:12:55.062817 16, 0x0, sum = 4
6530 22:12:55.063257 best_step = 14
6531 22:12:55.063590
6532 22:12:55.063899 ==
6533 22:12:55.066673 Dram Type= 6, Freq= 0, CH_0, rank 1
6534 22:12:55.069518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6535 22:12:55.072810 ==
6536 22:12:55.073229 RX Vref Scan: 0
6537 22:12:55.073558
6538 22:12:55.076594 RX Vref 0 -> 0, step: 1
6539 22:12:55.077110
6540 22:12:55.079200 RX Delay -359 -> 252, step: 8
6541 22:12:55.086572 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6542 22:12:55.089025 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6543 22:12:55.092629 iDelay=209, Bit 2, Center -40 (-279 ~ 200) 480
6544 22:12:55.096317 iDelay=209, Bit 3, Center -36 (-271 ~ 200) 472
6545 22:12:55.102474 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6546 22:12:55.105475 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6547 22:12:55.109159 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6548 22:12:55.111957 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6549 22:12:55.118758 iDelay=209, Bit 8, Center -52 (-295 ~ 192) 488
6550 22:12:55.121950 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6551 22:12:55.125211 iDelay=209, Bit 10, Center -44 (-287 ~ 200) 488
6552 22:12:55.128860 iDelay=209, Bit 11, Center -52 (-295 ~ 192) 488
6553 22:12:55.136121 iDelay=209, Bit 12, Center -40 (-287 ~ 208) 496
6554 22:12:55.138521 iDelay=209, Bit 13, Center -36 (-279 ~ 208) 488
6555 22:12:55.141814 iDelay=209, Bit 14, Center -36 (-279 ~ 208) 488
6556 22:12:55.148538 iDelay=209, Bit 15, Center -36 (-279 ~ 208) 488
6557 22:12:55.149052 ==
6558 22:12:55.151921 Dram Type= 6, Freq= 0, CH_0, rank 1
6559 22:12:55.155112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6560 22:12:55.155601 ==
6561 22:12:55.155997 DQS Delay:
6562 22:12:55.158318 DQS0 = 44, DQS1 = 60
6563 22:12:55.158739 DQM Delay:
6564 22:12:55.162078 DQM0 = 9, DQM1 = 15
6565 22:12:55.162497 DQ Delay:
6566 22:12:55.164995 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6567 22:12:55.168349 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6568 22:12:55.171818 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6569 22:12:55.174637 DQ12 =20, DQ13 =24, DQ14 =24, DQ15 =24
6570 22:12:55.175052
6571 22:12:55.175413
6572 22:12:55.181169 [DQSOSCAuto] RK1, (LSB)MR18= 0x8781, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6573 22:12:55.184360 CH0 RK1: MR19=C0C, MR18=8781
6574 22:12:55.191416 CH0_RK1: MR19=0xC0C, MR18=0x8781, DQSOSC=392, MR23=63, INC=384, DEC=256
6575 22:12:55.194866 [RxdqsGatingPostProcess] freq 400
6576 22:12:55.201185 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6577 22:12:55.204421 best DQS0 dly(2T, 0.5T) = (0, 10)
6578 22:12:55.207665 best DQS1 dly(2T, 0.5T) = (0, 10)
6579 22:12:55.211239 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6580 22:12:55.214620 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6581 22:12:55.215032 best DQS0 dly(2T, 0.5T) = (0, 10)
6582 22:12:55.217648 best DQS1 dly(2T, 0.5T) = (0, 10)
6583 22:12:55.221143 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6584 22:12:55.223982 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6585 22:12:55.227554 Pre-setting of DQS Precalculation
6586 22:12:55.234648 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6587 22:12:55.235103 ==
6588 22:12:55.237612 Dram Type= 6, Freq= 0, CH_1, rank 0
6589 22:12:55.240298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6590 22:12:55.240752 ==
6591 22:12:55.247110 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6592 22:12:55.254069 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6593 22:12:55.257000 [CA 0] Center 36 (8~64) winsize 57
6594 22:12:55.260225 [CA 1] Center 36 (8~64) winsize 57
6595 22:12:55.260776 [CA 2] Center 36 (8~64) winsize 57
6596 22:12:55.263700 [CA 3] Center 36 (8~64) winsize 57
6597 22:12:55.267236 [CA 4] Center 36 (8~64) winsize 57
6598 22:12:55.270360 [CA 5] Center 36 (8~64) winsize 57
6599 22:12:55.270783
6600 22:12:55.273451 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6601 22:12:55.273879
6602 22:12:55.280348 [CATrainingPosCal] consider 1 rank data
6603 22:12:55.280770 u2DelayCellTimex100 = 270/100 ps
6604 22:12:55.286731 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6605 22:12:55.290538 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6606 22:12:55.293234 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6607 22:12:55.297317 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6608 22:12:55.300042 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6609 22:12:55.303347 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6610 22:12:55.303795
6611 22:12:55.306508 CA PerBit enable=1, Macro0, CA PI delay=36
6612 22:12:55.306928
6613 22:12:55.310350 [CBTSetCACLKResult] CA Dly = 36
6614 22:12:55.313701 CS Dly: 1 (0~32)
6615 22:12:55.314210 ==
6616 22:12:55.316998 Dram Type= 6, Freq= 0, CH_1, rank 1
6617 22:12:55.319705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6618 22:12:55.320143 ==
6619 22:12:55.326884 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6620 22:12:55.329846 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6621 22:12:55.332960 [CA 0] Center 36 (8~64) winsize 57
6622 22:12:55.336720 [CA 1] Center 36 (8~64) winsize 57
6623 22:12:55.339826 [CA 2] Center 36 (8~64) winsize 57
6624 22:12:55.342884 [CA 3] Center 36 (8~64) winsize 57
6625 22:12:55.346112 [CA 4] Center 36 (8~64) winsize 57
6626 22:12:55.349813 [CA 5] Center 36 (8~64) winsize 57
6627 22:12:55.350332
6628 22:12:55.352826 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6629 22:12:55.353427
6630 22:12:55.356021 [CATrainingPosCal] consider 2 rank data
6631 22:12:55.359101 u2DelayCellTimex100 = 270/100 ps
6632 22:12:55.362390 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 22:12:55.369259 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 22:12:55.372779 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 22:12:55.376028 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 22:12:55.379390 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 22:12:55.382260 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 22:12:55.382705
6639 22:12:55.385705 CA PerBit enable=1, Macro0, CA PI delay=36
6640 22:12:55.386223
6641 22:12:55.388943 [CBTSetCACLKResult] CA Dly = 36
6642 22:12:55.389380 CS Dly: 1 (0~32)
6643 22:12:55.392390
6644 22:12:55.395826 ----->DramcWriteLeveling(PI) begin...
6645 22:12:55.396266 ==
6646 22:12:55.399770 Dram Type= 6, Freq= 0, CH_1, rank 0
6647 22:12:55.402546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6648 22:12:55.402989 ==
6649 22:12:55.405785 Write leveling (Byte 0): 40 => 8
6650 22:12:55.409067 Write leveling (Byte 1): 40 => 8
6651 22:12:55.412351 DramcWriteLeveling(PI) end<-----
6652 22:12:55.412784
6653 22:12:55.413123 ==
6654 22:12:55.415254 Dram Type= 6, Freq= 0, CH_1, rank 0
6655 22:12:55.418893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6656 22:12:55.419354 ==
6657 22:12:55.422399 [Gating] SW mode calibration
6658 22:12:55.428821 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6659 22:12:55.435295 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6660 22:12:55.438657 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6661 22:12:55.442004 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6662 22:12:55.449071 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6663 22:12:55.452292 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6664 22:12:55.455253 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6665 22:12:55.461758 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6666 22:12:55.465980 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6667 22:12:55.467954 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6668 22:12:55.474683 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6669 22:12:55.475102 Total UI for P1: 0, mck2ui 16
6670 22:12:55.481127 best dqsien dly found for B0: ( 0, 14, 24)
6671 22:12:55.481563 Total UI for P1: 0, mck2ui 16
6672 22:12:55.488199 best dqsien dly found for B1: ( 0, 14, 24)
6673 22:12:55.491304 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6674 22:12:55.494472 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6675 22:12:55.495001
6676 22:12:55.497787 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6677 22:12:55.500989 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6678 22:12:55.504320 [Gating] SW calibration Done
6679 22:12:55.504737 ==
6680 22:12:55.507685 Dram Type= 6, Freq= 0, CH_1, rank 0
6681 22:12:55.510917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6682 22:12:55.511387 ==
6683 22:12:55.514360 RX Vref Scan: 0
6684 22:12:55.514774
6685 22:12:55.515101 RX Vref 0 -> 0, step: 1
6686 22:12:55.517675
6687 22:12:55.518180 RX Delay -410 -> 252, step: 16
6688 22:12:55.524239 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6689 22:12:55.527825 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6690 22:12:55.530697 iDelay=230, Bit 2, Center -43 (-282 ~ 197) 480
6691 22:12:55.534177 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6692 22:12:55.540781 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6693 22:12:55.544473 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6694 22:12:55.547604 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6695 22:12:55.550856 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6696 22:12:55.557447 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6697 22:12:55.561284 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6698 22:12:55.564148 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6699 22:12:55.567200 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6700 22:12:55.574258 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6701 22:12:55.577360 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6702 22:12:55.581000 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6703 22:12:55.587279 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6704 22:12:55.587701 ==
6705 22:12:55.590329 Dram Type= 6, Freq= 0, CH_1, rank 0
6706 22:12:55.593552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6707 22:12:55.593971 ==
6708 22:12:55.594303 DQS Delay:
6709 22:12:55.597340 DQS0 = 43, DQS1 = 51
6710 22:12:55.597800 DQM Delay:
6711 22:12:55.600622 DQM0 = 13, DQM1 = 13
6712 22:12:55.601038 DQ Delay:
6713 22:12:55.603585 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6714 22:12:55.606729 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6715 22:12:55.610088 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6716 22:12:55.613958 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =16
6717 22:12:55.614371
6718 22:12:55.614698
6719 22:12:55.614999 ==
6720 22:12:55.616652 Dram Type= 6, Freq= 0, CH_1, rank 0
6721 22:12:55.620199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6722 22:12:55.620614 ==
6723 22:12:55.620942
6724 22:12:55.621244
6725 22:12:55.623400 TX Vref Scan disable
6726 22:12:55.623813 == TX Byte 0 ==
6727 22:12:55.630280 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6728 22:12:55.633414 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6729 22:12:55.633830 == TX Byte 1 ==
6730 22:12:55.639827 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6731 22:12:55.643489 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6732 22:12:55.644011 ==
6733 22:12:55.646993 Dram Type= 6, Freq= 0, CH_1, rank 0
6734 22:12:55.650364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6735 22:12:55.650890 ==
6736 22:12:55.651267
6737 22:12:55.653509
6738 22:12:55.654034 TX Vref Scan disable
6739 22:12:55.656274 == TX Byte 0 ==
6740 22:12:55.659948 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6741 22:12:55.663279 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6742 22:12:55.666748 == TX Byte 1 ==
6743 22:12:55.669568 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6744 22:12:55.672773 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6745 22:12:55.673192
6746 22:12:55.673524 [DATLAT]
6747 22:12:55.676454 Freq=400, CH1 RK0
6748 22:12:55.676873
6749 22:12:55.680796 DATLAT Default: 0xf
6750 22:12:55.681213 0, 0xFFFF, sum = 0
6751 22:12:55.682963 1, 0xFFFF, sum = 0
6752 22:12:55.683419 2, 0xFFFF, sum = 0
6753 22:12:55.685880 3, 0xFFFF, sum = 0
6754 22:12:55.686304 4, 0xFFFF, sum = 0
6755 22:12:55.689518 5, 0xFFFF, sum = 0
6756 22:12:55.689943 6, 0xFFFF, sum = 0
6757 22:12:55.692537 7, 0xFFFF, sum = 0
6758 22:12:55.693000 8, 0xFFFF, sum = 0
6759 22:12:55.695968 9, 0xFFFF, sum = 0
6760 22:12:55.696414 10, 0xFFFF, sum = 0
6761 22:12:55.699563 11, 0xFFFF, sum = 0
6762 22:12:55.700009 12, 0xFFFF, sum = 0
6763 22:12:55.702528 13, 0x0, sum = 1
6764 22:12:55.702973 14, 0x0, sum = 2
6765 22:12:55.706486 15, 0x0, sum = 3
6766 22:12:55.706967 16, 0x0, sum = 4
6767 22:12:55.709304 best_step = 14
6768 22:12:55.709765
6769 22:12:55.710228 ==
6770 22:12:55.712675 Dram Type= 6, Freq= 0, CH_1, rank 0
6771 22:12:55.715985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6772 22:12:55.716458 ==
6773 22:12:55.718917 RX Vref Scan: 1
6774 22:12:55.719450
6775 22:12:55.719909 RX Vref 0 -> 0, step: 1
6776 22:12:55.720351
6777 22:12:55.722871 RX Delay -343 -> 252, step: 8
6778 22:12:55.723392
6779 22:12:55.725471 Set Vref, RX VrefLevel [Byte0]: 45
6780 22:12:55.729005 [Byte1]: 53
6781 22:12:55.733916
6782 22:12:55.734338 Final RX Vref Byte 0 = 45 to rank0
6783 22:12:55.737023 Final RX Vref Byte 1 = 53 to rank0
6784 22:12:55.740203 Final RX Vref Byte 0 = 45 to rank1
6785 22:12:55.743735 Final RX Vref Byte 1 = 53 to rank1==
6786 22:12:55.746944 Dram Type= 6, Freq= 0, CH_1, rank 0
6787 22:12:55.753567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6788 22:12:55.754118 ==
6789 22:12:55.754555 DQS Delay:
6790 22:12:55.756866 DQS0 = 44, DQS1 = 52
6791 22:12:55.757292 DQM Delay:
6792 22:12:55.757742 DQM0 = 11, DQM1 = 11
6793 22:12:55.759854 DQ Delay:
6794 22:12:55.763818 DQ0 =20, DQ1 =4, DQ2 =0, DQ3 =12
6795 22:12:55.766573 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =4
6796 22:12:55.767048 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6797 22:12:55.773548 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6798 22:12:55.774015
6799 22:12:55.774442
6800 22:12:55.779808 [DQSOSCAuto] RK0, (LSB)MR18= 0x678e, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 396 ps
6801 22:12:55.782957 CH1 RK0: MR19=C0C, MR18=678E
6802 22:12:55.789619 CH1_RK0: MR19=0xC0C, MR18=0x678E, DQSOSC=392, MR23=63, INC=384, DEC=256
6803 22:12:55.790114 ==
6804 22:12:55.793003 Dram Type= 6, Freq= 0, CH_1, rank 1
6805 22:12:55.796282 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6806 22:12:55.796779 ==
6807 22:12:55.799505 [Gating] SW mode calibration
6808 22:12:55.806332 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6809 22:12:55.813172 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6810 22:12:55.815939 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6811 22:12:55.819408 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6812 22:12:55.825966 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6813 22:12:55.829200 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6814 22:12:55.832330 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6815 22:12:55.839091 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6816 22:12:55.842000 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6817 22:12:55.845598 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6818 22:12:55.852136 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6819 22:12:55.855450 Total UI for P1: 0, mck2ui 16
6820 22:12:55.858797 best dqsien dly found for B0: ( 0, 14, 24)
6821 22:12:55.862574 Total UI for P1: 0, mck2ui 16
6822 22:12:55.865412 best dqsien dly found for B1: ( 0, 14, 24)
6823 22:12:55.869019 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6824 22:12:55.871863 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6825 22:12:55.872345
6826 22:12:55.875515 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6827 22:12:55.878352 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6828 22:12:55.881974 [Gating] SW calibration Done
6829 22:12:55.882396 ==
6830 22:12:55.885489 Dram Type= 6, Freq= 0, CH_1, rank 1
6831 22:12:55.888187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6832 22:12:55.888626 ==
6833 22:12:55.891864 RX Vref Scan: 0
6834 22:12:55.892360
6835 22:12:55.894806 RX Vref 0 -> 0, step: 1
6836 22:12:55.895417
6837 22:12:55.898240 RX Delay -410 -> 252, step: 16
6838 22:12:55.901385 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6839 22:12:55.904843 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6840 22:12:55.908014 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6841 22:12:55.914511 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6842 22:12:55.918085 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6843 22:12:55.921103 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6844 22:12:55.924463 iDelay=230, Bit 6, Center -35 (-282 ~ 213) 496
6845 22:12:55.931247 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6846 22:12:55.934388 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6847 22:12:55.937529 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6848 22:12:55.940903 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6849 22:12:55.947699 iDelay=230, Bit 11, Center -35 (-282 ~ 213) 496
6850 22:12:55.951272 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6851 22:12:55.953846 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6852 22:12:55.960591 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6853 22:12:55.964856 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6854 22:12:55.965455 ==
6855 22:12:55.967258 Dram Type= 6, Freq= 0, CH_1, rank 1
6856 22:12:55.970731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6857 22:12:55.971160 ==
6858 22:12:55.974736 DQS Delay:
6859 22:12:55.975342 DQS0 = 51, DQS1 = 51
6860 22:12:55.975781 DQM Delay:
6861 22:12:55.977313 DQM0 = 16, DQM1 = 15
6862 22:12:55.977908 DQ Delay:
6863 22:12:55.980519 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6864 22:12:55.983580 DQ4 =16, DQ5 =32, DQ6 =16, DQ7 =16
6865 22:12:55.986860 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6866 22:12:55.990309 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6867 22:12:55.990875
6868 22:12:55.991440
6869 22:12:55.991873 ==
6870 22:12:55.993739 Dram Type= 6, Freq= 0, CH_1, rank 1
6871 22:12:55.999890 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6872 22:12:56.000489 ==
6873 22:12:56.000898
6874 22:12:56.001224
6875 22:12:56.001636 TX Vref Scan disable
6876 22:12:56.003522 == TX Byte 0 ==
6877 22:12:56.006983 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6878 22:12:56.010269 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6879 22:12:56.013120 == TX Byte 1 ==
6880 22:12:56.017027 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6881 22:12:56.020035 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6882 22:12:56.023163 ==
6883 22:12:56.026205 Dram Type= 6, Freq= 0, CH_1, rank 1
6884 22:12:56.029807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6885 22:12:56.030376 ==
6886 22:12:56.030877
6887 22:12:56.031339
6888 22:12:56.032974 TX Vref Scan disable
6889 22:12:56.033394 == TX Byte 0 ==
6890 22:12:56.036251 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6891 22:12:56.042974 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6892 22:12:56.043511 == TX Byte 1 ==
6893 22:12:56.045922 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6894 22:12:56.052507 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6895 22:12:56.053017
6896 22:12:56.053426 [DATLAT]
6897 22:12:56.053892 Freq=400, CH1 RK1
6898 22:12:56.054398
6899 22:12:56.056564 DATLAT Default: 0xe
6900 22:12:56.059029 0, 0xFFFF, sum = 0
6901 22:12:56.059505 1, 0xFFFF, sum = 0
6902 22:12:56.062787 2, 0xFFFF, sum = 0
6903 22:12:56.063353 3, 0xFFFF, sum = 0
6904 22:12:56.065790 4, 0xFFFF, sum = 0
6905 22:12:56.066360 5, 0xFFFF, sum = 0
6906 22:12:56.069044 6, 0xFFFF, sum = 0
6907 22:12:56.069560 7, 0xFFFF, sum = 0
6908 22:12:56.072719 8, 0xFFFF, sum = 0
6909 22:12:56.073164 9, 0xFFFF, sum = 0
6910 22:12:56.076195 10, 0xFFFF, sum = 0
6911 22:12:56.076801 11, 0xFFFF, sum = 0
6912 22:12:56.078874 12, 0xFFFF, sum = 0
6913 22:12:56.079394 13, 0x0, sum = 1
6914 22:12:56.082451 14, 0x0, sum = 2
6915 22:12:56.083058 15, 0x0, sum = 3
6916 22:12:56.086140 16, 0x0, sum = 4
6917 22:12:56.086713 best_step = 14
6918 22:12:56.087270
6919 22:12:56.087693 ==
6920 22:12:56.089179 Dram Type= 6, Freq= 0, CH_1, rank 1
6921 22:12:56.095535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6922 22:12:56.096133 ==
6923 22:12:56.096536 RX Vref Scan: 0
6924 22:12:56.096873
6925 22:12:56.098662 RX Vref 0 -> 0, step: 1
6926 22:12:56.099084
6927 22:12:56.102151 RX Delay -343 -> 252, step: 8
6928 22:12:56.109304 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6929 22:12:56.112055 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6930 22:12:56.115297 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6931 22:12:56.118370 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6932 22:12:56.125351 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6933 22:12:56.128497 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6934 22:12:56.132210 iDelay=217, Bit 6, Center -32 (-271 ~ 208) 480
6935 22:12:56.134960 iDelay=217, Bit 7, Center -40 (-279 ~ 200) 480
6936 22:12:56.141860 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6937 22:12:56.144997 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6938 22:12:56.148140 iDelay=217, Bit 10, Center -36 (-279 ~ 208) 488
6939 22:12:56.151312 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6940 22:12:56.158558 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6941 22:12:56.161353 iDelay=217, Bit 13, Center -32 (-271 ~ 208) 480
6942 22:12:56.165064 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6943 22:12:56.171994 iDelay=217, Bit 15, Center -32 (-279 ~ 216) 496
6944 22:12:56.172421 ==
6945 22:12:56.174828 Dram Type= 6, Freq= 0, CH_1, rank 1
6946 22:12:56.178126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6947 22:12:56.178544 ==
6948 22:12:56.178875 DQS Delay:
6949 22:12:56.181245 DQS0 = 52, DQS1 = 52
6950 22:12:56.181662 DQM Delay:
6951 22:12:56.184218 DQM0 = 14, DQM1 = 11
6952 22:12:56.184634 DQ Delay:
6953 22:12:56.187997 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =16
6954 22:12:56.190965 DQ4 =16, DQ5 =24, DQ6 =20, DQ7 =12
6955 22:12:56.195053 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6956 22:12:56.197953 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =20
6957 22:12:56.198368
6958 22:12:56.198695
6959 22:12:56.204563 [DQSOSCAuto] RK1, (LSB)MR18= 0x78ae, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 394 ps
6960 22:12:56.207608 CH1 RK1: MR19=C0C, MR18=78AE
6961 22:12:56.214044 CH1_RK1: MR19=0xC0C, MR18=0x78AE, DQSOSC=388, MR23=63, INC=392, DEC=261
6962 22:12:56.217971 [RxdqsGatingPostProcess] freq 400
6963 22:12:56.224131 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6964 22:12:56.226889 best DQS0 dly(2T, 0.5T) = (0, 10)
6965 22:12:56.230352 best DQS1 dly(2T, 0.5T) = (0, 10)
6966 22:12:56.233547 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6967 22:12:56.237215 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6968 22:12:56.240594 best DQS0 dly(2T, 0.5T) = (0, 10)
6969 22:12:56.241011 best DQS1 dly(2T, 0.5T) = (0, 10)
6970 22:12:56.243389 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6971 22:12:56.246910 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6972 22:12:56.250640 Pre-setting of DQS Precalculation
6973 22:12:56.256953 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6974 22:12:56.263904 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6975 22:12:56.269940 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6976 22:12:56.270366
6977 22:12:56.270719
6978 22:12:56.273756 [Calibration Summary] 800 Mbps
6979 22:12:56.276720 CH 0, Rank 0
6980 22:12:56.277263 SW Impedance : PASS
6981 22:12:56.280064 DUTY Scan : NO K
6982 22:12:56.283280 ZQ Calibration : PASS
6983 22:12:56.283705 Jitter Meter : NO K
6984 22:12:56.286824 CBT Training : PASS
6985 22:12:56.289660 Write leveling : PASS
6986 22:12:56.290080 RX DQS gating : PASS
6987 22:12:56.292962 RX DQ/DQS(RDDQC) : PASS
6988 22:12:56.293406 TX DQ/DQS : PASS
6989 22:12:56.296349 RX DATLAT : PASS
6990 22:12:56.299559 RX DQ/DQS(Engine): PASS
6991 22:12:56.300077 TX OE : NO K
6992 22:12:56.302804 All Pass.
6993 22:12:56.303303
6994 22:12:56.303648 CH 0, Rank 1
6995 22:12:56.306017 SW Impedance : PASS
6996 22:12:56.306438 DUTY Scan : NO K
6997 22:12:56.309527 ZQ Calibration : PASS
6998 22:12:56.313208 Jitter Meter : NO K
6999 22:12:56.313646 CBT Training : PASS
7000 22:12:56.316022 Write leveling : NO K
7001 22:12:56.319301 RX DQS gating : PASS
7002 22:12:56.319722 RX DQ/DQS(RDDQC) : PASS
7003 22:12:56.322726 TX DQ/DQS : PASS
7004 22:12:56.326213 RX DATLAT : PASS
7005 22:12:56.326727 RX DQ/DQS(Engine): PASS
7006 22:12:56.329479 TX OE : NO K
7007 22:12:56.329920 All Pass.
7008 22:12:56.330335
7009 22:12:56.332422 CH 1, Rank 0
7010 22:12:56.332844 SW Impedance : PASS
7011 22:12:56.336381 DUTY Scan : NO K
7012 22:12:56.338993 ZQ Calibration : PASS
7013 22:12:56.339473 Jitter Meter : NO K
7014 22:12:56.342280 CBT Training : PASS
7015 22:12:56.345838 Write leveling : PASS
7016 22:12:56.346259 RX DQS gating : PASS
7017 22:12:56.348875 RX DQ/DQS(RDDQC) : PASS
7018 22:12:56.352177 TX DQ/DQS : PASS
7019 22:12:56.352621 RX DATLAT : PASS
7020 22:12:56.355629 RX DQ/DQS(Engine): PASS
7021 22:12:56.359278 TX OE : NO K
7022 22:12:56.359723 All Pass.
7023 22:12:56.360076
7024 22:12:56.360389 CH 1, Rank 1
7025 22:12:56.362223 SW Impedance : PASS
7026 22:12:56.365620 DUTY Scan : NO K
7027 22:12:56.366061 ZQ Calibration : PASS
7028 22:12:56.369181 Jitter Meter : NO K
7029 22:12:56.372637 CBT Training : PASS
7030 22:12:56.373060 Write leveling : NO K
7031 22:12:56.375013 RX DQS gating : PASS
7032 22:12:56.379153 RX DQ/DQS(RDDQC) : PASS
7033 22:12:56.379685 TX DQ/DQS : PASS
7034 22:12:56.382332 RX DATLAT : PASS
7035 22:12:56.382773 RX DQ/DQS(Engine): PASS
7036 22:12:56.385361 TX OE : NO K
7037 22:12:56.385903 All Pass.
7038 22:12:56.386240
7039 22:12:56.388189 DramC Write-DBI off
7040 22:12:56.391822 PER_BANK_REFRESH: Hybrid Mode
7041 22:12:56.392264 TX_TRACKING: ON
7042 22:12:56.401540 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7043 22:12:56.404987 [FAST_K] Save calibration result to emmc
7044 22:12:56.408172 dramc_set_vcore_voltage set vcore to 725000
7045 22:12:56.411805 Read voltage for 1600, 0
7046 22:12:56.412220 Vio18 = 0
7047 22:12:56.414694 Vcore = 725000
7048 22:12:56.415106 Vdram = 0
7049 22:12:56.415532 Vddq = 0
7050 22:12:56.415841 Vmddr = 0
7051 22:12:56.421587 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7052 22:12:56.427988 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7053 22:12:56.428446 MEM_TYPE=3, freq_sel=13
7054 22:12:56.431017 sv_algorithm_assistance_LP4_3733
7055 22:12:56.434369 ============ PULL DRAM RESETB DOWN ============
7056 22:12:56.441699 ========== PULL DRAM RESETB DOWN end =========
7057 22:12:56.444277 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7058 22:12:56.447755 ===================================
7059 22:12:56.451240 LPDDR4 DRAM CONFIGURATION
7060 22:12:56.454819 ===================================
7061 22:12:56.455313 EX_ROW_EN[0] = 0x0
7062 22:12:56.457866 EX_ROW_EN[1] = 0x0
7063 22:12:56.460688 LP4Y_EN = 0x0
7064 22:12:56.461128 WORK_FSP = 0x1
7065 22:12:56.464293 WL = 0x5
7066 22:12:56.464839 RL = 0x5
7067 22:12:56.467423 BL = 0x2
7068 22:12:56.467845 RPST = 0x0
7069 22:12:56.470749 RD_PRE = 0x0
7070 22:12:56.471165 WR_PRE = 0x1
7071 22:12:56.474411 WR_PST = 0x1
7072 22:12:56.474933 DBI_WR = 0x0
7073 22:12:56.477706 DBI_RD = 0x0
7074 22:12:56.478205 OTF = 0x1
7075 22:12:56.481229 ===================================
7076 22:12:56.484195 ===================================
7077 22:12:56.487315 ANA top config
7078 22:12:56.490521 ===================================
7079 22:12:56.490936 DLL_ASYNC_EN = 0
7080 22:12:56.493961 ALL_SLAVE_EN = 0
7081 22:12:56.498041 NEW_RANK_MODE = 1
7082 22:12:56.500902 DLL_IDLE_MODE = 1
7083 22:12:56.504103 LP45_APHY_COMB_EN = 1
7084 22:12:56.504526 TX_ODT_DIS = 0
7085 22:12:56.507129 NEW_8X_MODE = 1
7086 22:12:56.510735 ===================================
7087 22:12:56.513455 ===================================
7088 22:12:56.516786 data_rate = 3200
7089 22:12:56.520156 CKR = 1
7090 22:12:56.523323 DQ_P2S_RATIO = 8
7091 22:12:56.527043 ===================================
7092 22:12:56.530258 CA_P2S_RATIO = 8
7093 22:12:56.530703 DQ_CA_OPEN = 0
7094 22:12:56.533647 DQ_SEMI_OPEN = 0
7095 22:12:56.536873 CA_SEMI_OPEN = 0
7096 22:12:56.539835 CA_FULL_RATE = 0
7097 22:12:56.543100 DQ_CKDIV4_EN = 0
7098 22:12:56.546511 CA_CKDIV4_EN = 0
7099 22:12:56.547042 CA_PREDIV_EN = 0
7100 22:12:56.549801 PH8_DLY = 12
7101 22:12:56.553592 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7102 22:12:56.556393 DQ_AAMCK_DIV = 4
7103 22:12:56.559535 CA_AAMCK_DIV = 4
7104 22:12:56.563136 CA_ADMCK_DIV = 4
7105 22:12:56.563597 DQ_TRACK_CA_EN = 0
7106 22:12:56.566670 CA_PICK = 1600
7107 22:12:56.569674 CA_MCKIO = 1600
7108 22:12:56.572903 MCKIO_SEMI = 0
7109 22:12:56.576164 PLL_FREQ = 3068
7110 22:12:56.579328 DQ_UI_PI_RATIO = 32
7111 22:12:56.582819 CA_UI_PI_RATIO = 0
7112 22:12:56.586151 ===================================
7113 22:12:56.589233 ===================================
7114 22:12:56.593078 memory_type:LPDDR4
7115 22:12:56.593563 GP_NUM : 10
7116 22:12:56.596379 SRAM_EN : 1
7117 22:12:56.596827 MD32_EN : 0
7118 22:12:56.599032 ===================================
7119 22:12:56.602498 [ANA_INIT] >>>>>>>>>>>>>>
7120 22:12:56.606000 <<<<<< [CONFIGURE PHASE]: ANA_TX
7121 22:12:56.609127 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7122 22:12:56.612582 ===================================
7123 22:12:56.615458 data_rate = 3200,PCW = 0X7600
7124 22:12:56.618825 ===================================
7125 22:12:56.622514 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7126 22:12:56.628723 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7127 22:12:56.632066 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7128 22:12:56.638320 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7129 22:12:56.642014 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7130 22:12:56.645344 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7131 22:12:56.645760 [ANA_INIT] flow start
7132 22:12:56.648637 [ANA_INIT] PLL >>>>>>>>
7133 22:12:56.651948 [ANA_INIT] PLL <<<<<<<<
7134 22:12:56.652417 [ANA_INIT] MIDPI >>>>>>>>
7135 22:12:56.655011 [ANA_INIT] MIDPI <<<<<<<<
7136 22:12:56.658271 [ANA_INIT] DLL >>>>>>>>
7137 22:12:56.661430 [ANA_INIT] DLL <<<<<<<<
7138 22:12:56.661843 [ANA_INIT] flow end
7139 22:12:56.664976 ============ LP4 DIFF to SE enter ============
7140 22:12:56.671471 ============ LP4 DIFF to SE exit ============
7141 22:12:56.671902 [ANA_INIT] <<<<<<<<<<<<<
7142 22:12:56.674840 [Flow] Enable top DCM control >>>>>
7143 22:12:56.677972 [Flow] Enable top DCM control <<<<<
7144 22:12:56.681147 Enable DLL master slave shuffle
7145 22:12:56.688354 ==============================================================
7146 22:12:56.688791 Gating Mode config
7147 22:12:56.694447 ==============================================================
7148 22:12:56.697562 Config description:
7149 22:12:56.707336 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7150 22:12:56.714238 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7151 22:12:56.717504 SELPH_MODE 0: By rank 1: By Phase
7152 22:12:56.724564 ==============================================================
7153 22:12:56.727452 GAT_TRACK_EN = 1
7154 22:12:56.730983 RX_GATING_MODE = 2
7155 22:12:56.734240 RX_GATING_TRACK_MODE = 2
7156 22:12:56.737528 SELPH_MODE = 1
7157 22:12:56.738055 PICG_EARLY_EN = 1
7158 22:12:56.741175 VALID_LAT_VALUE = 1
7159 22:12:56.747240 ==============================================================
7160 22:12:56.750572 Enter into Gating configuration >>>>
7161 22:12:56.753875 Exit from Gating configuration <<<<
7162 22:12:56.757573 Enter into DVFS_PRE_config >>>>>
7163 22:12:56.767133 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7164 22:12:56.770215 Exit from DVFS_PRE_config <<<<<
7165 22:12:56.773437 Enter into PICG configuration >>>>
7166 22:12:56.776940 Exit from PICG configuration <<<<
7167 22:12:56.779958 [RX_INPUT] configuration >>>>>
7168 22:12:56.783249 [RX_INPUT] configuration <<<<<
7169 22:12:56.789975 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7170 22:12:56.792968 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7171 22:12:56.799658 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7172 22:12:56.806595 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7173 22:12:56.813099 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7174 22:12:56.819377 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7175 22:12:56.822871 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7176 22:12:56.826781 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7177 22:12:56.829480 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7178 22:12:56.836090 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7179 22:12:56.839130 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7180 22:12:56.842349 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7181 22:12:56.845509 ===================================
7182 22:12:56.849432 LPDDR4 DRAM CONFIGURATION
7183 22:12:56.852374 ===================================
7184 22:12:56.855963 EX_ROW_EN[0] = 0x0
7185 22:12:56.856518 EX_ROW_EN[1] = 0x0
7186 22:12:56.859120 LP4Y_EN = 0x0
7187 22:12:56.859689 WORK_FSP = 0x1
7188 22:12:56.862458 WL = 0x5
7189 22:12:56.862892 RL = 0x5
7190 22:12:56.865690 BL = 0x2
7191 22:12:56.866145 RPST = 0x0
7192 22:12:56.868662 RD_PRE = 0x0
7193 22:12:56.869095 WR_PRE = 0x1
7194 22:12:56.871890 WR_PST = 0x1
7195 22:12:56.872325 DBI_WR = 0x0
7196 22:12:56.875480 DBI_RD = 0x0
7197 22:12:56.875913 OTF = 0x1
7198 22:12:56.878382 ===================================
7199 22:12:56.885792 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7200 22:12:56.888521 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7201 22:12:56.891714 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7202 22:12:56.895001 ===================================
7203 22:12:56.898288 LPDDR4 DRAM CONFIGURATION
7204 22:12:56.902249 ===================================
7205 22:12:56.904966 EX_ROW_EN[0] = 0x10
7206 22:12:56.905420 EX_ROW_EN[1] = 0x0
7207 22:12:56.908668 LP4Y_EN = 0x0
7208 22:12:56.909086 WORK_FSP = 0x1
7209 22:12:56.911868 WL = 0x5
7210 22:12:56.912342 RL = 0x5
7211 22:12:56.914786 BL = 0x2
7212 22:12:56.915409 RPST = 0x0
7213 22:12:56.918326 RD_PRE = 0x0
7214 22:12:56.918871 WR_PRE = 0x1
7215 22:12:56.921921 WR_PST = 0x1
7216 22:12:56.922371 DBI_WR = 0x0
7217 22:12:56.924865 DBI_RD = 0x0
7218 22:12:56.925427 OTF = 0x1
7219 22:12:56.927872 ===================================
7220 22:12:56.934935 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7221 22:12:56.935406 ==
7222 22:12:56.937726 Dram Type= 6, Freq= 0, CH_0, rank 0
7223 22:12:56.944662 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7224 22:12:56.945223 ==
7225 22:12:56.945589 [Duty_Offset_Calibration]
7226 22:12:56.947526 B0:2 B1:0 CA:4
7227 22:12:56.947936
7228 22:12:56.950755 [DutyScan_Calibration_Flow] k_type=0
7229 22:12:56.959894
7230 22:12:56.960544 ==CLK 0==
7231 22:12:56.963296 Final CLK duty delay cell = -4
7232 22:12:56.966843 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7233 22:12:56.969610 [-4] MIN Duty = 4844%(X100), DQS PI = 6
7234 22:12:56.973190 [-4] AVG Duty = 4937%(X100)
7235 22:12:56.973725
7236 22:12:56.977429 CH0 CLK Duty spec in!! Max-Min= 187%
7237 22:12:56.979745 [DutyScan_Calibration_Flow] ====Done====
7238 22:12:56.980212
7239 22:12:56.982726 [DutyScan_Calibration_Flow] k_type=1
7240 22:12:56.999482
7241 22:12:57.000020 ==DQS 0 ==
7242 22:12:57.002451 Final DQS duty delay cell = -4
7243 22:12:57.005986 [-4] MAX Duty = 4907%(X100), DQS PI = 46
7244 22:12:57.009277 [-4] MIN Duty = 4782%(X100), DQS PI = 26
7245 22:12:57.012276 [-4] AVG Duty = 4844%(X100)
7246 22:12:57.012745
7247 22:12:57.013073 ==DQS 1 ==
7248 22:12:57.015643 Final DQS duty delay cell = 0
7249 22:12:57.019089 [0] MAX Duty = 5187%(X100), DQS PI = 0
7250 22:12:57.022088 [0] MIN Duty = 4969%(X100), DQS PI = 10
7251 22:12:57.025547 [0] AVG Duty = 5078%(X100)
7252 22:12:57.025997
7253 22:12:57.029288 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7254 22:12:57.029713
7255 22:12:57.032284 CH0 DQS 1 Duty spec in!! Max-Min= 218%
7256 22:12:57.035458 [DutyScan_Calibration_Flow] ====Done====
7257 22:12:57.035888
7258 22:12:57.038885 [DutyScan_Calibration_Flow] k_type=3
7259 22:12:57.057433
7260 22:12:57.057938 ==DQM 0 ==
7261 22:12:57.060509 Final DQM duty delay cell = 0
7262 22:12:57.063529 [0] MAX Duty = 5124%(X100), DQS PI = 22
7263 22:12:57.066709 [0] MIN Duty = 4875%(X100), DQS PI = 56
7264 22:12:57.069806 [0] AVG Duty = 4999%(X100)
7265 22:12:57.070219
7266 22:12:57.070546 ==DQM 1 ==
7267 22:12:57.073291 Final DQM duty delay cell = 0
7268 22:12:57.076466 [0] MAX Duty = 4969%(X100), DQS PI = 0
7269 22:12:57.079864 [0] MIN Duty = 4844%(X100), DQS PI = 10
7270 22:12:57.083040 [0] AVG Duty = 4906%(X100)
7271 22:12:57.083482
7272 22:12:57.086960 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7273 22:12:57.087424
7274 22:12:57.089871 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7275 22:12:57.092919 [DutyScan_Calibration_Flow] ====Done====
7276 22:12:57.093333
7277 22:12:57.097100 [DutyScan_Calibration_Flow] k_type=2
7278 22:12:57.113819
7279 22:12:57.114330 ==DQ 0 ==
7280 22:12:57.117279 Final DQ duty delay cell = 0
7281 22:12:57.120755 [0] MAX Duty = 5124%(X100), DQS PI = 20
7282 22:12:57.123564 [0] MIN Duty = 4938%(X100), DQS PI = 12
7283 22:12:57.126962 [0] AVG Duty = 5031%(X100)
7284 22:12:57.127457
7285 22:12:57.127807 ==DQ 1 ==
7286 22:12:57.130374 Final DQ duty delay cell = 0
7287 22:12:57.133578 [0] MAX Duty = 5187%(X100), DQS PI = 2
7288 22:12:57.136840 [0] MIN Duty = 4938%(X100), DQS PI = 12
7289 22:12:57.137254 [0] AVG Duty = 5062%(X100)
7290 22:12:57.140436
7291 22:12:57.143674 CH0 DQ 0 Duty spec in!! Max-Min= 186%
7292 22:12:57.144127
7293 22:12:57.147066 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7294 22:12:57.150509 [DutyScan_Calibration_Flow] ====Done====
7295 22:12:57.150917 ==
7296 22:12:57.153178 Dram Type= 6, Freq= 0, CH_1, rank 0
7297 22:12:57.157179 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7298 22:12:57.157593 ==
7299 22:12:57.159654 [Duty_Offset_Calibration]
7300 22:12:57.160063 B0:0 B1:-1 CA:3
7301 22:12:57.160391
7302 22:12:57.163459 [DutyScan_Calibration_Flow] k_type=0
7303 22:12:57.173377
7304 22:12:57.173890 ==CLK 0==
7305 22:12:57.176824 Final CLK duty delay cell = -4
7306 22:12:57.180259 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7307 22:12:57.183214 [-4] MIN Duty = 4875%(X100), DQS PI = 12
7308 22:12:57.186304 [-4] AVG Duty = 4953%(X100)
7309 22:12:57.186716
7310 22:12:57.189659 CH1 CLK Duty spec in!! Max-Min= 156%
7311 22:12:57.193508 [DutyScan_Calibration_Flow] ====Done====
7312 22:12:57.193994
7313 22:12:57.196342 [DutyScan_Calibration_Flow] k_type=1
7314 22:12:57.212709
7315 22:12:57.213126 ==DQS 0 ==
7316 22:12:57.215865 Final DQS duty delay cell = 0
7317 22:12:57.219064 [0] MAX Duty = 5250%(X100), DQS PI = 30
7318 22:12:57.222675 [0] MIN Duty = 4938%(X100), DQS PI = 58
7319 22:12:57.226072 [0] AVG Duty = 5094%(X100)
7320 22:12:57.226487
7321 22:12:57.226943 ==DQS 1 ==
7322 22:12:57.228946 Final DQS duty delay cell = -4
7323 22:12:57.232327 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7324 22:12:57.235862 [-4] MIN Duty = 4844%(X100), DQS PI = 16
7325 22:12:57.239102 [-4] AVG Duty = 4922%(X100)
7326 22:12:57.239525
7327 22:12:57.243031 CH1 DQS 0 Duty spec in!! Max-Min= 312%
7328 22:12:57.243521
7329 22:12:57.246023 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7330 22:12:57.248880 [DutyScan_Calibration_Flow] ====Done====
7331 22:12:57.249293
7332 22:12:57.252389 [DutyScan_Calibration_Flow] k_type=3
7333 22:12:57.270257
7334 22:12:57.270730 ==DQM 0 ==
7335 22:12:57.273218 Final DQM duty delay cell = 0
7336 22:12:57.276973 [0] MAX Duty = 5062%(X100), DQS PI = 30
7337 22:12:57.279581 [0] MIN Duty = 4782%(X100), DQS PI = 40
7338 22:12:57.282943 [0] AVG Duty = 4922%(X100)
7339 22:12:57.283556
7340 22:12:57.283885 ==DQM 1 ==
7341 22:12:57.286303 Final DQM duty delay cell = 0
7342 22:12:57.289998 [0] MAX Duty = 5000%(X100), DQS PI = 30
7343 22:12:57.292825 [0] MIN Duty = 4813%(X100), DQS PI = 0
7344 22:12:57.296056 [0] AVG Duty = 4906%(X100)
7345 22:12:57.296459
7346 22:12:57.299702 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7347 22:12:57.300220
7348 22:12:57.302644 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7349 22:12:57.306272 [DutyScan_Calibration_Flow] ====Done====
7350 22:12:57.306768
7351 22:12:57.309165 [DutyScan_Calibration_Flow] k_type=2
7352 22:12:57.326187
7353 22:12:57.326727 ==DQ 0 ==
7354 22:12:57.329486 Final DQ duty delay cell = -4
7355 22:12:57.332477 [-4] MAX Duty = 4969%(X100), DQS PI = 32
7356 22:12:57.335700 [-4] MIN Duty = 4813%(X100), DQS PI = 38
7357 22:12:57.338924 [-4] AVG Duty = 4891%(X100)
7358 22:12:57.339558
7359 22:12:57.339910 ==DQ 1 ==
7360 22:12:57.342866 Final DQ duty delay cell = 0
7361 22:12:57.345446 [0] MAX Duty = 5062%(X100), DQS PI = 32
7362 22:12:57.349871 [0] MIN Duty = 4875%(X100), DQS PI = 58
7363 22:12:57.352503 [0] AVG Duty = 4968%(X100)
7364 22:12:57.353033
7365 22:12:57.355284 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7366 22:12:57.355699
7367 22:12:57.358796 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7368 22:12:57.362014 [DutyScan_Calibration_Flow] ====Done====
7369 22:12:57.365652 nWR fixed to 30
7370 22:12:57.368859 [ModeRegInit_LP4] CH0 RK0
7371 22:12:57.369275 [ModeRegInit_LP4] CH0 RK1
7372 22:12:57.371748 [ModeRegInit_LP4] CH1 RK0
7373 22:12:57.375105 [ModeRegInit_LP4] CH1 RK1
7374 22:12:57.375553 match AC timing 5
7375 22:12:57.381809 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7376 22:12:57.385652 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7377 22:12:57.388777 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7378 22:12:57.395394 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7379 22:12:57.398640 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7380 22:12:57.401504 [MiockJmeterHQA]
7381 22:12:57.401946
7382 22:12:57.405439 [DramcMiockJmeter] u1RxGatingPI = 0
7383 22:12:57.405949 0 : 4255, 4026
7384 22:12:57.406315 4 : 4252, 4027
7385 22:12:57.408188 8 : 4363, 4137
7386 22:12:57.408608 12 : 4253, 4026
7387 22:12:57.411527 16 : 4252, 4027
7388 22:12:57.412012 20 : 4363, 4138
7389 22:12:57.415147 24 : 4363, 4138
7390 22:12:57.415611 28 : 4253, 4026
7391 22:12:57.415949 32 : 4252, 4027
7392 22:12:57.418484 36 : 4252, 4027
7393 22:12:57.418902 40 : 4361, 4137
7394 22:12:57.421630 44 : 4252, 4027
7395 22:12:57.422048 48 : 4361, 4137
7396 22:12:57.425048 52 : 4253, 4026
7397 22:12:57.425465 56 : 4250, 4026
7398 22:12:57.427989 60 : 4250, 4026
7399 22:12:57.428407 64 : 4252, 4030
7400 22:12:57.428742 68 : 4361, 4138
7401 22:12:57.431654 72 : 4252, 4029
7402 22:12:57.432074 76 : 4361, 4137
7403 22:12:57.434349 80 : 4250, 4026
7404 22:12:57.434768 84 : 4250, 4027
7405 22:12:57.437817 88 : 4250, 4026
7406 22:12:57.438239 92 : 4361, 4137
7407 22:12:57.441554 96 : 4250, 3287
7408 22:12:57.441993 100 : 4360, 0
7409 22:12:57.442331 104 : 4252, 0
7410 22:12:57.444385 108 : 4363, 0
7411 22:12:57.444811 112 : 4253, 0
7412 22:12:57.447719 116 : 4250, 0
7413 22:12:57.448143 120 : 4253, 0
7414 22:12:57.448477 124 : 4250, 0
7415 22:12:57.451430 128 : 4250, 0
7416 22:12:57.452002 132 : 4252, 0
7417 22:12:57.452359 136 : 4361, 0
7418 22:12:57.454603 140 : 4250, 0
7419 22:12:57.455027 144 : 4249, 0
7420 22:12:57.457527 148 : 4250, 0
7421 22:12:57.458118 152 : 4360, 0
7422 22:12:57.458477 156 : 4361, 0
7423 22:12:57.461135 160 : 4250, 0
7424 22:12:57.461594 164 : 4250, 0
7425 22:12:57.464904 168 : 4250, 0
7426 22:12:57.465328 172 : 4252, 0
7427 22:12:57.465687 176 : 4250, 0
7428 22:12:57.467762 180 : 4250, 0
7429 22:12:57.468188 184 : 4252, 0
7430 22:12:57.470877 188 : 4361, 0
7431 22:12:57.471329 192 : 4249, 0
7432 22:12:57.471691 196 : 4250, 0
7433 22:12:57.474280 200 : 4250, 0
7434 22:12:57.474821 204 : 4360, 0
7435 22:12:57.477724 208 : 4360, 0
7436 22:12:57.478151 212 : 4250, 0
7437 22:12:57.478489 216 : 4250, 0
7438 22:12:57.480617 220 : 4363, 512
7439 22:12:57.481040 224 : 4250, 3970
7440 22:12:57.484030 228 : 4250, 4027
7441 22:12:57.484457 232 : 4250, 4027
7442 22:12:57.488393 236 : 4250, 4027
7443 22:12:57.488923 240 : 4250, 4026
7444 22:12:57.490486 244 : 4252, 4027
7445 22:12:57.490912 248 : 4252, 4029
7446 22:12:57.494061 252 : 4249, 4027
7447 22:12:57.494514 256 : 4360, 4137
7448 22:12:57.494850 260 : 4361, 4137
7449 22:12:57.497272 264 : 4250, 4027
7450 22:12:57.497863 268 : 4363, 4140
7451 22:12:57.501023 272 : 4250, 4027
7452 22:12:57.501551 276 : 4250, 4026
7453 22:12:57.504170 280 : 4250, 4027
7454 22:12:57.504592 284 : 4252, 4030
7455 22:12:57.507392 288 : 4251, 4027
7456 22:12:57.507817 292 : 4250, 4026
7457 22:12:57.510160 296 : 4250, 4027
7458 22:12:57.510603 300 : 4252, 4030
7459 22:12:57.513516 304 : 4249, 4027
7460 22:12:57.513958 308 : 4360, 4137
7461 22:12:57.516954 312 : 4361, 4137
7462 22:12:57.517400 316 : 4250, 4027
7463 22:12:57.520123 320 : 4363, 4140
7464 22:12:57.520562 324 : 4250, 4027
7465 22:12:57.523719 328 : 4250, 4026
7466 22:12:57.524192 332 : 4250, 4021
7467 22:12:57.524540 336 : 4252, 2044
7468 22:12:57.526957
7469 22:12:57.527470 MIOCK jitter meter ch=0
7470 22:12:57.527882
7471 22:12:57.530568 1T = (336-100) = 236 dly cells
7472 22:12:57.536765 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7473 22:12:57.537185 ==
7474 22:12:57.540072 Dram Type= 6, Freq= 0, CH_0, rank 0
7475 22:12:57.543492 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7476 22:12:57.543913 ==
7477 22:12:57.550253 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7478 22:12:57.553148 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7479 22:12:57.556364 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7480 22:12:57.563633 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7481 22:12:57.572946 [CA 0] Center 43 (13~74) winsize 62
7482 22:12:57.576219 [CA 1] Center 42 (12~73) winsize 62
7483 22:12:57.579072 [CA 2] Center 37 (8~67) winsize 60
7484 22:12:57.582649 [CA 3] Center 37 (8~67) winsize 60
7485 22:12:57.585703 [CA 4] Center 36 (6~66) winsize 61
7486 22:12:57.589186 [CA 5] Center 35 (5~66) winsize 62
7487 22:12:57.589667
7488 22:12:57.592342 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7489 22:12:57.592758
7490 22:12:57.595959 [CATrainingPosCal] consider 1 rank data
7491 22:12:57.598999 u2DelayCellTimex100 = 275/100 ps
7492 22:12:57.605892 CA0 delay=43 (13~74),Diff = 8 PI (28 cell)
7493 22:12:57.609073 CA1 delay=42 (12~73),Diff = 7 PI (24 cell)
7494 22:12:57.612083 CA2 delay=37 (8~67),Diff = 2 PI (7 cell)
7495 22:12:57.615554 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7496 22:12:57.618511 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7497 22:12:57.622049 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7498 22:12:57.622481
7499 22:12:57.625569 CA PerBit enable=1, Macro0, CA PI delay=35
7500 22:12:57.625997
7501 22:12:57.628882 [CBTSetCACLKResult] CA Dly = 35
7502 22:12:57.631714 CS Dly: 11 (0~42)
7503 22:12:57.635230 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7504 22:12:57.638683 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7505 22:12:57.639110 ==
7506 22:12:57.642191 Dram Type= 6, Freq= 0, CH_0, rank 1
7507 22:12:57.648207 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7508 22:12:57.648640 ==
7509 22:12:57.651654 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7510 22:12:57.658322 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7511 22:12:57.661884 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7512 22:12:57.668069 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7513 22:12:57.676282 [CA 0] Center 43 (13~74) winsize 62
7514 22:12:57.679136 [CA 1] Center 43 (13~73) winsize 61
7515 22:12:57.682722 [CA 2] Center 38 (9~68) winsize 60
7516 22:12:57.685952 [CA 3] Center 38 (9~68) winsize 60
7517 22:12:57.689169 [CA 4] Center 36 (7~66) winsize 60
7518 22:12:57.692697 [CA 5] Center 36 (7~66) winsize 60
7519 22:12:57.693125
7520 22:12:57.695780 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7521 22:12:57.696211
7522 22:12:57.702218 [CATrainingPosCal] consider 2 rank data
7523 22:12:57.702649 u2DelayCellTimex100 = 275/100 ps
7524 22:12:57.708852 CA0 delay=43 (13~74),Diff = 7 PI (24 cell)
7525 22:12:57.712827 CA1 delay=43 (13~73),Diff = 7 PI (24 cell)
7526 22:12:57.715501 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
7527 22:12:57.718966 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7528 22:12:57.721993 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7529 22:12:57.725261 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7530 22:12:57.725689
7531 22:12:57.728892 CA PerBit enable=1, Macro0, CA PI delay=36
7532 22:12:57.729319
7533 22:12:57.731902 [CBTSetCACLKResult] CA Dly = 36
7534 22:12:57.735117 CS Dly: 11 (0~43)
7535 22:12:57.738313 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7536 22:12:57.741614 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7537 22:12:57.742039
7538 22:12:57.745039 ----->DramcWriteLeveling(PI) begin...
7539 22:12:57.748149 ==
7540 22:12:57.748579 Dram Type= 6, Freq= 0, CH_0, rank 0
7541 22:12:57.755001 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7542 22:12:57.755472 ==
7543 22:12:57.757991 Write leveling (Byte 0): 36 => 36
7544 22:12:57.761391 Write leveling (Byte 1): 26 => 26
7545 22:12:57.764983 DramcWriteLeveling(PI) end<-----
7546 22:12:57.765412
7547 22:12:57.765842 ==
7548 22:12:57.767608 Dram Type= 6, Freq= 0, CH_0, rank 0
7549 22:12:57.770991 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7550 22:12:57.771467 ==
7551 22:12:57.774379 [Gating] SW mode calibration
7552 22:12:57.780917 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7553 22:12:57.788393 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7554 22:12:57.791126 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7555 22:12:57.794488 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7556 22:12:57.800885 1 4 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
7557 22:12:57.804222 1 4 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
7558 22:12:57.808025 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7559 22:12:57.814030 1 4 20 | B1->B0 | 2c2c 3434 | 1 1 | (0 0) (1 1)
7560 22:12:57.817082 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7561 22:12:57.820910 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7562 22:12:57.827553 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7563 22:12:57.830486 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7564 22:12:57.833590 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
7565 22:12:57.840201 1 5 12 | B1->B0 | 3434 2929 | 1 1 | (1 1) (1 0)
7566 22:12:57.843837 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7567 22:12:57.847305 1 5 20 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
7568 22:12:57.853368 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7569 22:12:57.857178 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7570 22:12:57.860416 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7571 22:12:57.866860 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7572 22:12:57.869883 1 6 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
7573 22:12:57.873285 1 6 12 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
7574 22:12:57.879672 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7575 22:12:57.883071 1 6 20 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
7576 22:12:57.886390 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7577 22:12:57.892809 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7578 22:12:57.896153 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7579 22:12:57.899709 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7580 22:12:57.906629 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7581 22:12:57.909351 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7582 22:12:57.912960 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7583 22:12:57.919326 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7584 22:12:57.922951 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7585 22:12:57.926242 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 22:12:57.932842 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 22:12:57.936145 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 22:12:57.939334 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 22:12:57.945812 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 22:12:57.948829 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 22:12:57.952170 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 22:12:57.959237 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 22:12:57.962123 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7594 22:12:57.965426 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7595 22:12:57.972135 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 22:12:57.975912 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7597 22:12:57.978490 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7598 22:12:57.981903 Total UI for P1: 0, mck2ui 16
7599 22:12:57.985121 best dqsien dly found for B0: ( 1, 9, 8)
7600 22:12:57.991706 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7601 22:12:57.995999 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7602 22:12:57.998339 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7603 22:12:58.001713 Total UI for P1: 0, mck2ui 16
7604 22:12:58.004966 best dqsien dly found for B1: ( 1, 9, 18)
7605 22:12:58.008519 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7606 22:12:58.011928 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
7607 22:12:58.012340
7608 22:12:58.018558 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7609 22:12:58.021588 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
7610 22:12:58.022001 [Gating] SW calibration Done
7611 22:12:58.024778 ==
7612 22:12:58.028155 Dram Type= 6, Freq= 0, CH_0, rank 0
7613 22:12:58.031501 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7614 22:12:58.032073 ==
7615 22:12:58.032415 RX Vref Scan: 0
7616 22:12:58.032726
7617 22:12:58.034735 RX Vref 0 -> 0, step: 1
7618 22:12:58.035147
7619 22:12:58.038050 RX Delay 0 -> 252, step: 8
7620 22:12:58.041350 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7621 22:12:58.044676 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7622 22:12:58.047982 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7623 22:12:58.055017 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7624 22:12:58.058126 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7625 22:12:58.061071 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7626 22:12:58.064387 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7627 22:12:58.067813 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
7628 22:12:58.074507 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
7629 22:12:58.078408 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7630 22:12:58.081215 iDelay=192, Bit 10, Center 123 (72 ~ 175) 104
7631 22:12:58.084321 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
7632 22:12:58.091290 iDelay=192, Bit 12, Center 131 (72 ~ 191) 120
7633 22:12:58.094565 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7634 22:12:58.097213 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7635 22:12:58.101108 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7636 22:12:58.101541 ==
7637 22:12:58.104230 Dram Type= 6, Freq= 0, CH_0, rank 0
7638 22:12:58.110703 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7639 22:12:58.111139 ==
7640 22:12:58.111503 DQS Delay:
7641 22:12:58.113675 DQS0 = 0, DQS1 = 0
7642 22:12:58.114093 DQM Delay:
7643 22:12:58.114423 DQM0 = 131, DQM1 = 125
7644 22:12:58.117160 DQ Delay:
7645 22:12:58.120820 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7646 22:12:58.124012 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
7647 22:12:58.126878 DQ8 =119, DQ9 =111, DQ10 =123, DQ11 =119
7648 22:12:58.130840 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7649 22:12:58.131293
7650 22:12:58.131628
7651 22:12:58.132024 ==
7652 22:12:58.133367 Dram Type= 6, Freq= 0, CH_0, rank 0
7653 22:12:58.140016 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7654 22:12:58.140433 ==
7655 22:12:58.140762
7656 22:12:58.141067
7657 22:12:58.141357 TX Vref Scan disable
7658 22:12:58.144035 == TX Byte 0 ==
7659 22:12:58.146780 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7660 22:12:58.153656 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7661 22:12:58.154179 == TX Byte 1 ==
7662 22:12:58.156896 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7663 22:12:58.163816 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7664 22:12:58.164232 ==
7665 22:12:58.166936 Dram Type= 6, Freq= 0, CH_0, rank 0
7666 22:12:58.169846 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7667 22:12:58.170260 ==
7668 22:12:58.183677
7669 22:12:58.187226 TX Vref early break, caculate TX vref
7670 22:12:58.189926 TX Vref=16, minBit 1, minWin=21, winSum=359
7671 22:12:58.194163 TX Vref=18, minBit 1, minWin=22, winSum=375
7672 22:12:58.196747 TX Vref=20, minBit 1, minWin=22, winSum=381
7673 22:12:58.199717 TX Vref=22, minBit 1, minWin=22, winSum=394
7674 22:12:58.203092 TX Vref=24, minBit 0, minWin=23, winSum=402
7675 22:12:58.210034 TX Vref=26, minBit 1, minWin=23, winSum=405
7676 22:12:58.213349 TX Vref=28, minBit 1, minWin=24, winSum=411
7677 22:12:58.216581 TX Vref=30, minBit 1, minWin=24, winSum=407
7678 22:12:58.219452 TX Vref=32, minBit 0, minWin=23, winSum=397
7679 22:12:58.222812 TX Vref=34, minBit 4, minWin=22, winSum=386
7680 22:12:58.229531 [TxChooseVref] Worse bit 1, Min win 24, Win sum 411, Final Vref 28
7681 22:12:58.229950
7682 22:12:58.232742 Final TX Range 0 Vref 28
7683 22:12:58.233162
7684 22:12:58.233552 ==
7685 22:12:58.236109 Dram Type= 6, Freq= 0, CH_0, rank 0
7686 22:12:58.239304 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7687 22:12:58.239725 ==
7688 22:12:58.240054
7689 22:12:58.240356
7690 22:12:58.242797 TX Vref Scan disable
7691 22:12:58.249483 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7692 22:12:58.249899 == TX Byte 0 ==
7693 22:12:58.252848 u2DelayCellOfst[0]=10 cells (3 PI)
7694 22:12:58.255903 u2DelayCellOfst[1]=14 cells (4 PI)
7695 22:12:58.259211 u2DelayCellOfst[2]=10 cells (3 PI)
7696 22:12:58.262764 u2DelayCellOfst[3]=10 cells (3 PI)
7697 22:12:58.265720 u2DelayCellOfst[4]=7 cells (2 PI)
7698 22:12:58.269355 u2DelayCellOfst[5]=0 cells (0 PI)
7699 22:12:58.272216 u2DelayCellOfst[6]=14 cells (4 PI)
7700 22:12:58.275591 u2DelayCellOfst[7]=14 cells (4 PI)
7701 22:12:58.279293 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7702 22:12:58.282469 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7703 22:12:58.285545 == TX Byte 1 ==
7704 22:12:58.289087 u2DelayCellOfst[8]=0 cells (0 PI)
7705 22:12:58.291869 u2DelayCellOfst[9]=0 cells (0 PI)
7706 22:12:58.295150 u2DelayCellOfst[10]=3 cells (1 PI)
7707 22:12:58.298867 u2DelayCellOfst[11]=3 cells (1 PI)
7708 22:12:58.302169 u2DelayCellOfst[12]=10 cells (3 PI)
7709 22:12:58.302613 u2DelayCellOfst[13]=10 cells (3 PI)
7710 22:12:58.305331 u2DelayCellOfst[14]=14 cells (4 PI)
7711 22:12:58.308547 u2DelayCellOfst[15]=10 cells (3 PI)
7712 22:12:58.315466 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7713 22:12:58.318625 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7714 22:12:58.321958 DramC Write-DBI on
7715 22:12:58.322375 ==
7716 22:12:58.324767 Dram Type= 6, Freq= 0, CH_0, rank 0
7717 22:12:58.328339 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7718 22:12:58.328760 ==
7719 22:12:58.329094
7720 22:12:58.329401
7721 22:12:58.331697 TX Vref Scan disable
7722 22:12:58.332127 == TX Byte 0 ==
7723 22:12:58.338014 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7724 22:12:58.338425 == TX Byte 1 ==
7725 22:12:58.341577 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7726 22:12:58.345141 DramC Write-DBI off
7727 22:12:58.345551
7728 22:12:58.345911 [DATLAT]
7729 22:12:58.348139 Freq=1600, CH0 RK0
7730 22:12:58.348588
7731 22:12:58.348918 DATLAT Default: 0xf
7732 22:12:58.351479 0, 0xFFFF, sum = 0
7733 22:12:58.354939 1, 0xFFFF, sum = 0
7734 22:12:58.355412 2, 0xFFFF, sum = 0
7735 22:12:58.357964 3, 0xFFFF, sum = 0
7736 22:12:58.358510 4, 0xFFFF, sum = 0
7737 22:12:58.361440 5, 0xFFFF, sum = 0
7738 22:12:58.362001 6, 0xFFFF, sum = 0
7739 22:12:58.364673 7, 0xFFFF, sum = 0
7740 22:12:58.365089 8, 0xFFFF, sum = 0
7741 22:12:58.367665 9, 0xFFFF, sum = 0
7742 22:12:58.368116 10, 0xFFFF, sum = 0
7743 22:12:58.371154 11, 0xFFFF, sum = 0
7744 22:12:58.371730 12, 0xFFFF, sum = 0
7745 22:12:58.374526 13, 0xFFFF, sum = 0
7746 22:12:58.375108 14, 0x0, sum = 1
7747 22:12:58.377537 15, 0x0, sum = 2
7748 22:12:58.377953 16, 0x0, sum = 3
7749 22:12:58.381062 17, 0x0, sum = 4
7750 22:12:58.381482 best_step = 15
7751 22:12:58.381850
7752 22:12:58.382159 ==
7753 22:12:58.384740 Dram Type= 6, Freq= 0, CH_0, rank 0
7754 22:12:58.391639 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7755 22:12:58.392052 ==
7756 22:12:58.392416 RX Vref Scan: 1
7757 22:12:58.392724
7758 22:12:58.394275 Set Vref Range= 24 -> 127
7759 22:12:58.394682
7760 22:12:58.397357 RX Vref 24 -> 127, step: 1
7761 22:12:58.397809
7762 22:12:58.400672 RX Delay 11 -> 252, step: 4
7763 22:12:58.401081
7764 22:12:58.403788 Set Vref, RX VrefLevel [Byte0]: 24
7765 22:12:58.407458 [Byte1]: 24
7766 22:12:58.407911
7767 22:12:58.410457 Set Vref, RX VrefLevel [Byte0]: 25
7768 22:12:58.413501 [Byte1]: 25
7769 22:12:58.413948
7770 22:12:58.417170 Set Vref, RX VrefLevel [Byte0]: 26
7771 22:12:58.420494 [Byte1]: 26
7772 22:12:58.423542
7773 22:12:58.423955 Set Vref, RX VrefLevel [Byte0]: 27
7774 22:12:58.427429 [Byte1]: 27
7775 22:12:58.431448
7776 22:12:58.431857 Set Vref, RX VrefLevel [Byte0]: 28
7777 22:12:58.434168 [Byte1]: 28
7778 22:12:58.439046
7779 22:12:58.439474 Set Vref, RX VrefLevel [Byte0]: 29
7780 22:12:58.442243 [Byte1]: 29
7781 22:12:58.446186
7782 22:12:58.446596 Set Vref, RX VrefLevel [Byte0]: 30
7783 22:12:58.449997 [Byte1]: 30
7784 22:12:58.454715
7785 22:12:58.455291 Set Vref, RX VrefLevel [Byte0]: 31
7786 22:12:58.457339 [Byte1]: 31
7787 22:12:58.461632
7788 22:12:58.462085 Set Vref, RX VrefLevel [Byte0]: 32
7789 22:12:58.465042 [Byte1]: 32
7790 22:12:58.468947
7791 22:12:58.469354 Set Vref, RX VrefLevel [Byte0]: 33
7792 22:12:58.472479 [Byte1]: 33
7793 22:12:58.477062
7794 22:12:58.477515 Set Vref, RX VrefLevel [Byte0]: 34
7795 22:12:58.479983 [Byte1]: 34
7796 22:12:58.484418
7797 22:12:58.484929 Set Vref, RX VrefLevel [Byte0]: 35
7798 22:12:58.488061 [Byte1]: 35
7799 22:12:58.491874
7800 22:12:58.492326 Set Vref, RX VrefLevel [Byte0]: 36
7801 22:12:58.495566 [Byte1]: 36
7802 22:12:58.499748
7803 22:12:58.500200 Set Vref, RX VrefLevel [Byte0]: 37
7804 22:12:58.502888 [Byte1]: 37
7805 22:12:58.507548
7806 22:12:58.508000 Set Vref, RX VrefLevel [Byte0]: 38
7807 22:12:58.510381 [Byte1]: 38
7808 22:12:58.514909
7809 22:12:58.515398 Set Vref, RX VrefLevel [Byte0]: 39
7810 22:12:58.518059 [Byte1]: 39
7811 22:12:58.522495
7812 22:12:58.522949 Set Vref, RX VrefLevel [Byte0]: 40
7813 22:12:58.525704 [Byte1]: 40
7814 22:12:58.530248
7815 22:12:58.530709 Set Vref, RX VrefLevel [Byte0]: 41
7816 22:12:58.533464 [Byte1]: 41
7817 22:12:58.537930
7818 22:12:58.538381 Set Vref, RX VrefLevel [Byte0]: 42
7819 22:12:58.540939 [Byte1]: 42
7820 22:12:58.545415
7821 22:12:58.545867 Set Vref, RX VrefLevel [Byte0]: 43
7822 22:12:58.548532 [Byte1]: 43
7823 22:12:58.552889
7824 22:12:58.553297 Set Vref, RX VrefLevel [Byte0]: 44
7825 22:12:58.556415 [Byte1]: 44
7826 22:12:58.560489
7827 22:12:58.560941 Set Vref, RX VrefLevel [Byte0]: 45
7828 22:12:58.564171 [Byte1]: 45
7829 22:12:58.568055
7830 22:12:58.568510 Set Vref, RX VrefLevel [Byte0]: 46
7831 22:12:58.571350 [Byte1]: 46
7832 22:12:58.576067
7833 22:12:58.576476 Set Vref, RX VrefLevel [Byte0]: 47
7834 22:12:58.579277 [Byte1]: 47
7835 22:12:58.584172
7836 22:12:58.584716 Set Vref, RX VrefLevel [Byte0]: 48
7837 22:12:58.587029 [Byte1]: 48
7838 22:12:58.590826
7839 22:12:58.591278 Set Vref, RX VrefLevel [Byte0]: 49
7840 22:12:58.593989 [Byte1]: 49
7841 22:12:58.598538
7842 22:12:58.598985 Set Vref, RX VrefLevel [Byte0]: 50
7843 22:12:58.601932 [Byte1]: 50
7844 22:12:58.606336
7845 22:12:58.606746 Set Vref, RX VrefLevel [Byte0]: 51
7846 22:12:58.609705 [Byte1]: 51
7847 22:12:58.614307
7848 22:12:58.614757 Set Vref, RX VrefLevel [Byte0]: 52
7849 22:12:58.617114 [Byte1]: 52
7850 22:12:58.621324
7851 22:12:58.621778 Set Vref, RX VrefLevel [Byte0]: 53
7852 22:12:58.624642 [Byte1]: 53
7853 22:12:58.629215
7854 22:12:58.629662 Set Vref, RX VrefLevel [Byte0]: 54
7855 22:12:58.632521 [Byte1]: 54
7856 22:12:58.637052
7857 22:12:58.637503 Set Vref, RX VrefLevel [Byte0]: 55
7858 22:12:58.639866 [Byte1]: 55
7859 22:12:58.644386
7860 22:12:58.644797 Set Vref, RX VrefLevel [Byte0]: 56
7861 22:12:58.647419 [Byte1]: 56
7862 22:12:58.651765
7863 22:12:58.652219 Set Vref, RX VrefLevel [Byte0]: 57
7864 22:12:58.655230 [Byte1]: 57
7865 22:12:58.659469
7866 22:12:58.659925 Set Vref, RX VrefLevel [Byte0]: 58
7867 22:12:58.662739 [Byte1]: 58
7868 22:12:58.666866
7869 22:12:58.667303 Set Vref, RX VrefLevel [Byte0]: 59
7870 22:12:58.670455 [Byte1]: 59
7871 22:12:58.675022
7872 22:12:58.675502 Set Vref, RX VrefLevel [Byte0]: 60
7873 22:12:58.677863 [Byte1]: 60
7874 22:12:58.682657
7875 22:12:58.683241 Set Vref, RX VrefLevel [Byte0]: 61
7876 22:12:58.685843 [Byte1]: 61
7877 22:12:58.689920
7878 22:12:58.690342 Set Vref, RX VrefLevel [Byte0]: 62
7879 22:12:58.693261 [Byte1]: 62
7880 22:12:58.697469
7881 22:12:58.697919 Set Vref, RX VrefLevel [Byte0]: 63
7882 22:12:58.700953 [Byte1]: 63
7883 22:12:58.705216
7884 22:12:58.705785 Set Vref, RX VrefLevel [Byte0]: 64
7885 22:12:58.708438 [Byte1]: 64
7886 22:12:58.712881
7887 22:12:58.713430 Set Vref, RX VrefLevel [Byte0]: 65
7888 22:12:58.715992 [Byte1]: 65
7889 22:12:58.720094
7890 22:12:58.720547 Set Vref, RX VrefLevel [Byte0]: 66
7891 22:12:58.723529 [Byte1]: 66
7892 22:12:58.727703
7893 22:12:58.728150 Set Vref, RX VrefLevel [Byte0]: 67
7894 22:12:58.731134 [Byte1]: 67
7895 22:12:58.735432
7896 22:12:58.735888 Set Vref, RX VrefLevel [Byte0]: 68
7897 22:12:58.739085 [Byte1]: 68
7898 22:12:58.743365
7899 22:12:58.743776 Set Vref, RX VrefLevel [Byte0]: 69
7900 22:12:58.746682 [Byte1]: 69
7901 22:12:58.751441
7902 22:12:58.751898 Set Vref, RX VrefLevel [Byte0]: 70
7903 22:12:58.753987 [Byte1]: 70
7904 22:12:58.758626
7905 22:12:58.759073 Set Vref, RX VrefLevel [Byte0]: 71
7906 22:12:58.762144 [Byte1]: 71
7907 22:12:58.766161
7908 22:12:58.766615 Set Vref, RX VrefLevel [Byte0]: 72
7909 22:12:58.769769 [Byte1]: 72
7910 22:12:58.773489
7911 22:12:58.773935 Set Vref, RX VrefLevel [Byte0]: 73
7912 22:12:58.777083 [Byte1]: 73
7913 22:12:58.781711
7914 22:12:58.782122 Set Vref, RX VrefLevel [Byte0]: 74
7915 22:12:58.784558 [Byte1]: 74
7916 22:12:58.788883
7917 22:12:58.789331 Set Vref, RX VrefLevel [Byte0]: 75
7918 22:12:58.792192 [Byte1]: 75
7919 22:12:58.796743
7920 22:12:58.797155 Final RX Vref Byte 0 = 56 to rank0
7921 22:12:58.800264 Final RX Vref Byte 1 = 59 to rank0
7922 22:12:58.803346 Final RX Vref Byte 0 = 56 to rank1
7923 22:12:58.806752 Final RX Vref Byte 1 = 59 to rank1==
7924 22:12:58.810084 Dram Type= 6, Freq= 0, CH_0, rank 0
7925 22:12:58.816565 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7926 22:12:58.816986 ==
7927 22:12:58.817319 DQS Delay:
7928 22:12:58.819796 DQS0 = 0, DQS1 = 0
7929 22:12:58.820216 DQM Delay:
7930 22:12:58.820548 DQM0 = 129, DQM1 = 123
7931 22:12:58.823088 DQ Delay:
7932 22:12:58.826500 DQ0 =130, DQ1 =130, DQ2 =128, DQ3 =124
7933 22:12:58.829562 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =134
7934 22:12:58.832827 DQ8 =112, DQ9 =112, DQ10 =124, DQ11 =120
7935 22:12:58.835926 DQ12 =130, DQ13 =128, DQ14 =132, DQ15 =130
7936 22:12:58.836345
7937 22:12:58.836673
7938 22:12:58.836980
7939 22:12:58.839528 [DramC_TX_OE_Calibration] TA2
7940 22:12:58.842387 Original DQ_B0 (3 6) =30, OEN = 27
7941 22:12:58.846074 Original DQ_B1 (3 6) =30, OEN = 27
7942 22:12:58.849123 24, 0x0, End_B0=24 End_B1=24
7943 22:12:58.852393 25, 0x0, End_B0=25 End_B1=25
7944 22:12:58.852819 26, 0x0, End_B0=26 End_B1=26
7945 22:12:58.856376 27, 0x0, End_B0=27 End_B1=27
7946 22:12:58.859276 28, 0x0, End_B0=28 End_B1=28
7947 22:12:58.862496 29, 0x0, End_B0=29 End_B1=29
7948 22:12:58.862921 30, 0x0, End_B0=30 End_B1=30
7949 22:12:58.865546 31, 0x4141, End_B0=30 End_B1=30
7950 22:12:58.869028 Byte0 end_step=30 best_step=27
7951 22:12:58.872259 Byte1 end_step=30 best_step=27
7952 22:12:58.875158 Byte0 TX OE(2T, 0.5T) = (3, 3)
7953 22:12:58.878711 Byte1 TX OE(2T, 0.5T) = (3, 3)
7954 22:12:58.879129
7955 22:12:58.879498
7956 22:12:58.884886 [DQSOSCAuto] RK0, (LSB)MR18= 0x1613, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 398 ps
7957 22:12:58.888797 CH0 RK0: MR19=303, MR18=1613
7958 22:12:58.895255 CH0_RK0: MR19=0x303, MR18=0x1613, DQSOSC=398, MR23=63, INC=23, DEC=15
7959 22:12:58.895674
7960 22:12:58.898355 ----->DramcWriteLeveling(PI) begin...
7961 22:12:58.898901 ==
7962 22:12:58.902067 Dram Type= 6, Freq= 0, CH_0, rank 1
7963 22:12:58.905124 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7964 22:12:58.907814 ==
7965 22:12:58.908231 Write leveling (Byte 0): 36 => 36
7966 22:12:58.911462 Write leveling (Byte 1): 27 => 27
7967 22:12:58.914426 DramcWriteLeveling(PI) end<-----
7968 22:12:58.914843
7969 22:12:58.915205 ==
7970 22:12:58.918166 Dram Type= 6, Freq= 0, CH_0, rank 1
7971 22:12:58.924394 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7972 22:12:58.924814 ==
7973 22:12:58.927736 [Gating] SW mode calibration
7974 22:12:58.934151 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7975 22:12:58.937426 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7976 22:12:58.944067 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7977 22:12:58.947568 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7978 22:12:58.950369 1 4 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7979 22:12:58.957019 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7980 22:12:58.960927 1 4 16 | B1->B0 | 2423 3434 | 1 1 | (0 0) (1 1)
7981 22:12:58.963643 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7982 22:12:58.970301 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7983 22:12:58.974138 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7984 22:12:58.977505 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7985 22:12:58.984036 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7986 22:12:58.986983 1 5 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
7987 22:12:58.990484 1 5 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
7988 22:12:58.996684 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7989 22:12:58.999942 1 5 20 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
7990 22:12:59.003337 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7991 22:12:59.009839 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7992 22:12:59.013139 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7993 22:12:59.016343 1 6 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7994 22:12:59.023287 1 6 8 | B1->B0 | 2323 4141 | 0 0 | (0 0) (0 0)
7995 22:12:59.026773 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7996 22:12:59.029559 1 6 16 | B1->B0 | 2929 4646 | 1 0 | (0 0) (0 0)
7997 22:12:59.036143 1 6 20 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
7998 22:12:59.039469 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7999 22:12:59.042535 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8000 22:12:59.049103 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8001 22:12:59.052662 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8002 22:12:59.055690 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8003 22:12:59.062298 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8004 22:12:59.065581 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8005 22:12:59.069043 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8006 22:12:59.076327 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 22:12:59.078962 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 22:12:59.082380 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8009 22:12:59.089371 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8010 22:12:59.092101 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8011 22:12:59.095244 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8012 22:12:59.101582 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8013 22:12:59.105427 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8014 22:12:59.108523 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8015 22:12:59.115298 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8016 22:12:59.118022 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8017 22:12:59.121776 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8018 22:12:59.128003 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8019 22:12:59.131648 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8020 22:12:59.134975 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8021 22:12:59.138020 Total UI for P1: 0, mck2ui 16
8022 22:12:59.141501 best dqsien dly found for B0: ( 1, 9, 8)
8023 22:12:59.148037 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8024 22:12:59.151216 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8025 22:12:59.155279 Total UI for P1: 0, mck2ui 16
8026 22:12:59.157777 best dqsien dly found for B1: ( 1, 9, 20)
8027 22:12:59.161336 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8028 22:12:59.164371 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
8029 22:12:59.164817
8030 22:12:59.167655 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8031 22:12:59.174262 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
8032 22:12:59.174681 [Gating] SW calibration Done
8033 22:12:59.175009 ==
8034 22:12:59.177570 Dram Type= 6, Freq= 0, CH_0, rank 1
8035 22:12:59.184332 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8036 22:12:59.184915 ==
8037 22:12:59.185266 RX Vref Scan: 0
8038 22:12:59.185606
8039 22:12:59.187066 RX Vref 0 -> 0, step: 1
8040 22:12:59.187513
8041 22:12:59.191327 RX Delay 0 -> 252, step: 8
8042 22:12:59.194049 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8043 22:12:59.197600 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8044 22:12:59.200458 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
8045 22:12:59.207510 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8046 22:12:59.210570 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8047 22:12:59.213684 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8048 22:12:59.216688 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8049 22:12:59.220187 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8050 22:12:59.226758 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8051 22:12:59.230322 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8052 22:12:59.233302 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8053 22:12:59.237080 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8054 22:12:59.243632 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8055 22:12:59.246390 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8056 22:12:59.249963 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8057 22:12:59.253760 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8058 22:12:59.254213 ==
8059 22:12:59.256631 Dram Type= 6, Freq= 0, CH_0, rank 1
8060 22:12:59.262949 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8061 22:12:59.263437 ==
8062 22:12:59.263769 DQS Delay:
8063 22:12:59.264105 DQS0 = 0, DQS1 = 0
8064 22:12:59.266240 DQM Delay:
8065 22:12:59.266696 DQM0 = 133, DQM1 = 123
8066 22:12:59.270434 DQ Delay:
8067 22:12:59.273019 DQ0 =131, DQ1 =135, DQ2 =131, DQ3 =127
8068 22:12:59.276274 DQ4 =139, DQ5 =119, DQ6 =143, DQ7 =139
8069 22:12:59.279723 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =115
8070 22:12:59.282685 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8071 22:12:59.283130
8072 22:12:59.283516
8073 22:12:59.283854 ==
8074 22:12:59.286927 Dram Type= 6, Freq= 0, CH_0, rank 1
8075 22:12:59.289213 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8076 22:12:59.293358 ==
8077 22:12:59.293806
8078 22:12:59.294139
8079 22:12:59.294473 TX Vref Scan disable
8080 22:12:59.296575 == TX Byte 0 ==
8081 22:12:59.299812 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8082 22:12:59.302715 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8083 22:12:59.306457 == TX Byte 1 ==
8084 22:12:59.309839 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8085 22:12:59.312942 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8086 22:12:59.315720 ==
8087 22:12:59.319162 Dram Type= 6, Freq= 0, CH_0, rank 1
8088 22:12:59.322196 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8089 22:12:59.322652 ==
8090 22:12:59.335822
8091 22:12:59.339015 TX Vref early break, caculate TX vref
8092 22:12:59.341931 TX Vref=16, minBit 2, minWin=22, winSum=378
8093 22:12:59.345388 TX Vref=18, minBit 1, minWin=23, winSum=388
8094 22:12:59.348686 TX Vref=20, minBit 0, minWin=24, winSum=395
8095 22:12:59.352171 TX Vref=22, minBit 0, minWin=24, winSum=405
8096 22:12:59.358778 TX Vref=24, minBit 3, minWin=24, winSum=409
8097 22:12:59.361698 TX Vref=26, minBit 0, minWin=25, winSum=418
8098 22:12:59.365689 TX Vref=28, minBit 1, minWin=25, winSum=418
8099 22:12:59.368359 TX Vref=30, minBit 4, minWin=24, winSum=415
8100 22:12:59.372201 TX Vref=32, minBit 4, minWin=23, winSum=404
8101 22:12:59.375304 TX Vref=34, minBit 0, minWin=24, winSum=394
8102 22:12:59.381901 [TxChooseVref] Worse bit 0, Min win 25, Win sum 418, Final Vref 26
8103 22:12:59.382314
8104 22:12:59.385372 Final TX Range 0 Vref 26
8105 22:12:59.385811
8106 22:12:59.386170 ==
8107 22:12:59.388406 Dram Type= 6, Freq= 0, CH_0, rank 1
8108 22:12:59.391293 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8109 22:12:59.391766 ==
8110 22:12:59.392097
8111 22:12:59.392435
8112 22:12:59.395323 TX Vref Scan disable
8113 22:12:59.401848 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8114 22:12:59.402262 == TX Byte 0 ==
8115 22:12:59.404518 u2DelayCellOfst[0]=14 cells (4 PI)
8116 22:12:59.407946 u2DelayCellOfst[1]=17 cells (5 PI)
8117 22:12:59.411516 u2DelayCellOfst[2]=10 cells (3 PI)
8118 22:12:59.414391 u2DelayCellOfst[3]=14 cells (4 PI)
8119 22:12:59.417935 u2DelayCellOfst[4]=7 cells (2 PI)
8120 22:12:59.421498 u2DelayCellOfst[5]=0 cells (0 PI)
8121 22:12:59.424413 u2DelayCellOfst[6]=17 cells (5 PI)
8122 22:12:59.428245 u2DelayCellOfst[7]=17 cells (5 PI)
8123 22:12:59.430888 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8124 22:12:59.434483 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8125 22:12:59.438039 == TX Byte 1 ==
8126 22:12:59.440703 u2DelayCellOfst[8]=0 cells (0 PI)
8127 22:12:59.444183 u2DelayCellOfst[9]=0 cells (0 PI)
8128 22:12:59.447552 u2DelayCellOfst[10]=3 cells (1 PI)
8129 22:12:59.450714 u2DelayCellOfst[11]=3 cells (1 PI)
8130 22:12:59.454345 u2DelayCellOfst[12]=10 cells (3 PI)
8131 22:12:59.457354 u2DelayCellOfst[13]=10 cells (3 PI)
8132 22:12:59.457764 u2DelayCellOfst[14]=14 cells (4 PI)
8133 22:12:59.460833 u2DelayCellOfst[15]=14 cells (4 PI)
8134 22:12:59.466971 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8135 22:12:59.470612 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8136 22:12:59.473864 DramC Write-DBI on
8137 22:12:59.474321 ==
8138 22:12:59.476907 Dram Type= 6, Freq= 0, CH_0, rank 1
8139 22:12:59.480077 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8140 22:12:59.480536 ==
8141 22:12:59.480866
8142 22:12:59.481204
8143 22:12:59.484052 TX Vref Scan disable
8144 22:12:59.487076 == TX Byte 0 ==
8145 22:12:59.490191 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8146 22:12:59.490602 == TX Byte 1 ==
8147 22:12:59.497060 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8148 22:12:59.497578 DramC Write-DBI off
8149 22:12:59.497999
8150 22:12:59.498308 [DATLAT]
8151 22:12:59.499771 Freq=1600, CH0 RK1
8152 22:12:59.500128
8153 22:12:59.503405 DATLAT Default: 0xf
8154 22:12:59.503817 0, 0xFFFF, sum = 0
8155 22:12:59.506774 1, 0xFFFF, sum = 0
8156 22:12:59.507258 2, 0xFFFF, sum = 0
8157 22:12:59.510045 3, 0xFFFF, sum = 0
8158 22:12:59.510465 4, 0xFFFF, sum = 0
8159 22:12:59.513038 5, 0xFFFF, sum = 0
8160 22:12:59.513505 6, 0xFFFF, sum = 0
8161 22:12:59.516729 7, 0xFFFF, sum = 0
8162 22:12:59.517146 8, 0xFFFF, sum = 0
8163 22:12:59.519608 9, 0xFFFF, sum = 0
8164 22:12:59.520048 10, 0xFFFF, sum = 0
8165 22:12:59.522959 11, 0xFFFF, sum = 0
8166 22:12:59.523435 12, 0xFFFF, sum = 0
8167 22:12:59.526764 13, 0xFFFF, sum = 0
8168 22:12:59.527231 14, 0x0, sum = 1
8169 22:12:59.529605 15, 0x0, sum = 2
8170 22:12:59.530051 16, 0x0, sum = 3
8171 22:12:59.532799 17, 0x0, sum = 4
8172 22:12:59.533222 best_step = 15
8173 22:12:59.533554
8174 22:12:59.533863 ==
8175 22:12:59.536326 Dram Type= 6, Freq= 0, CH_0, rank 1
8176 22:12:59.542878 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8177 22:12:59.543343 ==
8178 22:12:59.543686 RX Vref Scan: 0
8179 22:12:59.543998
8180 22:12:59.546126 RX Vref 0 -> 0, step: 1
8181 22:12:59.546544
8182 22:12:59.549639 RX Delay 11 -> 252, step: 4
8183 22:12:59.552688 iDelay=191, Bit 0, Center 128 (79 ~ 178) 100
8184 22:12:59.556496 iDelay=191, Bit 1, Center 132 (79 ~ 186) 108
8185 22:12:59.562494 iDelay=191, Bit 2, Center 124 (75 ~ 174) 100
8186 22:12:59.566182 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8187 22:12:59.569101 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8188 22:12:59.572654 iDelay=191, Bit 5, Center 120 (67 ~ 174) 108
8189 22:12:59.576037 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8190 22:12:59.582928 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8191 22:12:59.586048 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8192 22:12:59.589652 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8193 22:12:59.592327 iDelay=191, Bit 10, Center 126 (75 ~ 178) 104
8194 22:12:59.595842 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8195 22:12:59.602230 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8196 22:12:59.605575 iDelay=191, Bit 13, Center 130 (79 ~ 182) 104
8197 22:12:59.608415 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8198 22:12:59.611997 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8199 22:12:59.612410 ==
8200 22:12:59.615625 Dram Type= 6, Freq= 0, CH_0, rank 1
8201 22:12:59.621995 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8202 22:12:59.622534 ==
8203 22:12:59.622874 DQS Delay:
8204 22:12:59.625326 DQS0 = 0, DQS1 = 0
8205 22:12:59.625739 DQM Delay:
8206 22:12:59.628349 DQM0 = 129, DQM1 = 124
8207 22:12:59.628778 DQ Delay:
8208 22:12:59.632072 DQ0 =128, DQ1 =132, DQ2 =124, DQ3 =126
8209 22:12:59.635312 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =134
8210 22:12:59.638453 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
8211 22:12:59.641646 DQ12 =128, DQ13 =130, DQ14 =134, DQ15 =132
8212 22:12:59.642226
8213 22:12:59.642657
8214 22:12:59.642975
8215 22:12:59.644562 [DramC_TX_OE_Calibration] TA2
8216 22:12:59.648095 Original DQ_B0 (3 6) =30, OEN = 27
8217 22:12:59.651663 Original DQ_B1 (3 6) =30, OEN = 27
8218 22:12:59.654809 24, 0x0, End_B0=24 End_B1=24
8219 22:12:59.657850 25, 0x0, End_B0=25 End_B1=25
8220 22:12:59.658302 26, 0x0, End_B0=26 End_B1=26
8221 22:12:59.661318 27, 0x0, End_B0=27 End_B1=27
8222 22:12:59.664419 28, 0x0, End_B0=28 End_B1=28
8223 22:12:59.667898 29, 0x0, End_B0=29 End_B1=29
8224 22:12:59.671106 30, 0x0, End_B0=30 End_B1=30
8225 22:12:59.671570 31, 0x4141, End_B0=30 End_B1=30
8226 22:12:59.674753 Byte0 end_step=30 best_step=27
8227 22:12:59.677643 Byte1 end_step=30 best_step=27
8228 22:12:59.680784 Byte0 TX OE(2T, 0.5T) = (3, 3)
8229 22:12:59.684575 Byte1 TX OE(2T, 0.5T) = (3, 3)
8230 22:12:59.685023
8231 22:12:59.685347
8232 22:12:59.690670 [DQSOSCAuto] RK1, (LSB)MR18= 0x1412, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
8233 22:12:59.694619 CH0 RK1: MR19=303, MR18=1412
8234 22:12:59.700663 CH0_RK1: MR19=0x303, MR18=0x1412, DQSOSC=399, MR23=63, INC=23, DEC=15
8235 22:12:59.704111 [RxdqsGatingPostProcess] freq 1600
8236 22:12:59.710293 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8237 22:12:59.713502 best DQS0 dly(2T, 0.5T) = (1, 1)
8238 22:12:59.717560 best DQS1 dly(2T, 0.5T) = (1, 1)
8239 22:12:59.720473 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8240 22:12:59.721005 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8241 22:12:59.723734 best DQS0 dly(2T, 0.5T) = (1, 1)
8242 22:12:59.726661 best DQS1 dly(2T, 0.5T) = (1, 1)
8243 22:12:59.730782 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8244 22:12:59.733941 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8245 22:12:59.736489 Pre-setting of DQS Precalculation
8246 22:12:59.743063 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8247 22:12:59.743662 ==
8248 22:12:59.746630 Dram Type= 6, Freq= 0, CH_1, rank 0
8249 22:12:59.750074 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8250 22:12:59.750491 ==
8251 22:12:59.756428 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8252 22:12:59.759773 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8253 22:12:59.763051 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8254 22:12:59.769543 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8255 22:12:59.778468 [CA 0] Center 41 (11~72) winsize 62
8256 22:12:59.782130 [CA 1] Center 41 (11~72) winsize 62
8257 22:12:59.785509 [CA 2] Center 38 (9~67) winsize 59
8258 22:12:59.788942 [CA 3] Center 37 (8~66) winsize 59
8259 22:12:59.791878 [CA 4] Center 37 (8~67) winsize 60
8260 22:12:59.795366 [CA 5] Center 36 (7~66) winsize 60
8261 22:12:59.795908
8262 22:12:59.798356 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8263 22:12:59.798789
8264 22:12:59.801444 [CATrainingPosCal] consider 1 rank data
8265 22:12:59.804945 u2DelayCellTimex100 = 275/100 ps
8266 22:12:59.811312 CA0 delay=41 (11~72),Diff = 5 PI (17 cell)
8267 22:12:59.815510 CA1 delay=41 (11~72),Diff = 5 PI (17 cell)
8268 22:12:59.818107 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8269 22:12:59.821354 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8270 22:12:59.824431 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8271 22:12:59.827541 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8272 22:12:59.827964
8273 22:12:59.831557 CA PerBit enable=1, Macro0, CA PI delay=36
8274 22:12:59.832168
8275 22:12:59.834452 [CBTSetCACLKResult] CA Dly = 36
8276 22:12:59.837668 CS Dly: 8 (0~39)
8277 22:12:59.841025 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8278 22:12:59.844617 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8279 22:12:59.845065 ==
8280 22:12:59.847932 Dram Type= 6, Freq= 0, CH_1, rank 1
8281 22:12:59.854294 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8282 22:12:59.854719 ==
8283 22:12:59.857556 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8284 22:12:59.863985 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8285 22:12:59.867467 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8286 22:12:59.873742 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8287 22:12:59.881425 [CA 0] Center 41 (11~71) winsize 61
8288 22:12:59.884998 [CA 1] Center 42 (13~71) winsize 59
8289 22:12:59.888294 [CA 2] Center 37 (8~67) winsize 60
8290 22:12:59.891791 [CA 3] Center 36 (7~65) winsize 59
8291 22:12:59.894945 [CA 4] Center 37 (7~67) winsize 61
8292 22:12:59.897866 [CA 5] Center 35 (6~65) winsize 60
8293 22:12:59.898287
8294 22:12:59.901369 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8295 22:12:59.901894
8296 22:12:59.908396 [CATrainingPosCal] consider 2 rank data
8297 22:12:59.908930 u2DelayCellTimex100 = 275/100 ps
8298 22:12:59.914483 CA0 delay=41 (11~71),Diff = 5 PI (17 cell)
8299 22:12:59.917699 CA1 delay=42 (13~71),Diff = 6 PI (21 cell)
8300 22:12:59.921331 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8301 22:12:59.924368 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8302 22:12:59.927716 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8303 22:12:59.931002 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
8304 22:12:59.931436
8305 22:12:59.934230 CA PerBit enable=1, Macro0, CA PI delay=36
8306 22:12:59.934644
8307 22:12:59.937267 [CBTSetCACLKResult] CA Dly = 36
8308 22:12:59.941278 CS Dly: 9 (0~42)
8309 22:12:59.943805 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8310 22:12:59.947833 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8311 22:12:59.948324
8312 22:12:59.950341 ----->DramcWriteLeveling(PI) begin...
8313 22:12:59.950749 ==
8314 22:12:59.953649 Dram Type= 6, Freq= 0, CH_1, rank 0
8315 22:12:59.960591 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8316 22:12:59.960998 ==
8317 22:12:59.963589 Write leveling (Byte 0): 24 => 24
8318 22:12:59.966758 Write leveling (Byte 1): 27 => 27
8319 22:12:59.970122 DramcWriteLeveling(PI) end<-----
8320 22:12:59.970410
8321 22:12:59.970640 ==
8322 22:12:59.973338 Dram Type= 6, Freq= 0, CH_1, rank 0
8323 22:12:59.976892 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8324 22:12:59.977198 ==
8325 22:12:59.980261 [Gating] SW mode calibration
8326 22:12:59.986339 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8327 22:12:59.992990 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8328 22:12:59.996207 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8329 22:12:59.999856 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8330 22:13:00.006240 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8331 22:13:00.009624 1 4 12 | B1->B0 | 2626 3232 | 0 1 | (0 0) (1 1)
8332 22:13:00.012917 1 4 16 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
8333 22:13:00.019557 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8334 22:13:00.022947 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8335 22:13:00.026341 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8336 22:13:00.032952 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8337 22:13:00.036033 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8338 22:13:00.039477 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8339 22:13:00.046043 1 5 12 | B1->B0 | 2e2e 2525 | 0 0 | (1 0) (0 0)
8340 22:13:00.049372 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8341 22:13:00.053138 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8342 22:13:00.059207 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8343 22:13:00.062985 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8344 22:13:00.065739 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8345 22:13:00.072396 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8346 22:13:00.075753 1 6 8 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
8347 22:13:00.079161 1 6 12 | B1->B0 | 2f2f 4444 | 0 0 | (0 0) (0 0)
8348 22:13:00.085987 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8349 22:13:00.088974 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8350 22:13:00.092144 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8351 22:13:00.098441 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8352 22:13:00.102176 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8353 22:13:00.105532 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8354 22:13:00.111949 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8355 22:13:00.115476 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8356 22:13:00.118140 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8357 22:13:00.124909 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 22:13:00.128045 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8359 22:13:00.131576 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8360 22:13:00.137944 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 22:13:00.141518 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 22:13:00.145065 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8363 22:13:00.150983 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8364 22:13:00.154371 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8365 22:13:00.157840 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8366 22:13:00.164682 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8367 22:13:00.167883 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8368 22:13:00.171155 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8369 22:13:00.177531 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8370 22:13:00.181129 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8371 22:13:00.184094 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8372 22:13:00.190420 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8373 22:13:00.190846 Total UI for P1: 0, mck2ui 16
8374 22:13:00.197418 best dqsien dly found for B0: ( 1, 9, 10)
8375 22:13:00.200790 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8376 22:13:00.203788 Total UI for P1: 0, mck2ui 16
8377 22:13:00.207210 best dqsien dly found for B1: ( 1, 9, 14)
8378 22:13:00.210552 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8379 22:13:00.213864 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8380 22:13:00.214284
8381 22:13:00.216705 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8382 22:13:00.223982 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8383 22:13:00.224402 [Gating] SW calibration Done
8384 22:13:00.224730 ==
8385 22:13:00.227018 Dram Type= 6, Freq= 0, CH_1, rank 0
8386 22:13:00.233924 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8387 22:13:00.234432 ==
8388 22:13:00.234838 RX Vref Scan: 0
8389 22:13:00.235210
8390 22:13:00.236672 RX Vref 0 -> 0, step: 1
8391 22:13:00.237102
8392 22:13:00.240420 RX Delay 0 -> 252, step: 8
8393 22:13:00.243089 iDelay=200, Bit 0, Center 143 (88 ~ 199) 112
8394 22:13:00.246361 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8395 22:13:00.249878 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8396 22:13:00.257122 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8397 22:13:00.259948 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8398 22:13:00.263303 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8399 22:13:00.267065 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8400 22:13:00.269525 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8401 22:13:00.276241 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8402 22:13:00.279661 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8403 22:13:00.282583 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8404 22:13:00.286738 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8405 22:13:00.289720 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8406 22:13:00.296060 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8407 22:13:00.299677 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8408 22:13:00.302433 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8409 22:13:00.302848 ==
8410 22:13:00.306640 Dram Type= 6, Freq= 0, CH_1, rank 0
8411 22:13:00.308921 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8412 22:13:00.312337 ==
8413 22:13:00.312718 DQS Delay:
8414 22:13:00.313103 DQS0 = 0, DQS1 = 0
8415 22:13:00.315722 DQM Delay:
8416 22:13:00.316091 DQM0 = 135, DQM1 = 132
8417 22:13:00.318932 DQ Delay:
8418 22:13:00.322732 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8419 22:13:00.325907 DQ4 =131, DQ5 =143, DQ6 =147, DQ7 =131
8420 22:13:00.328513 DQ8 =115, DQ9 =123, DQ10 =131, DQ11 =127
8421 22:13:00.331999 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8422 22:13:00.332440
8423 22:13:00.332769
8424 22:13:00.333075 ==
8425 22:13:00.335629 Dram Type= 6, Freq= 0, CH_1, rank 0
8426 22:13:00.338423 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8427 22:13:00.342112 ==
8428 22:13:00.342526
8429 22:13:00.342854
8430 22:13:00.343159 TX Vref Scan disable
8431 22:13:00.345540 == TX Byte 0 ==
8432 22:13:00.349168 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8433 22:13:00.352229 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8434 22:13:00.355336 == TX Byte 1 ==
8435 22:13:00.358597 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8436 22:13:00.361994 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8437 22:13:00.362413 ==
8438 22:13:00.365105 Dram Type= 6, Freq= 0, CH_1, rank 0
8439 22:13:00.372730 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8440 22:13:00.373151 ==
8441 22:13:00.385116
8442 22:13:00.388384 TX Vref early break, caculate TX vref
8443 22:13:00.391422 TX Vref=16, minBit 8, minWin=21, winSum=366
8444 22:13:00.394736 TX Vref=18, minBit 8, minWin=21, winSum=376
8445 22:13:00.397833 TX Vref=20, minBit 9, minWin=22, winSum=387
8446 22:13:00.401673 TX Vref=22, minBit 8, minWin=23, winSum=394
8447 22:13:00.404541 TX Vref=24, minBit 8, minWin=24, winSum=406
8448 22:13:00.411146 TX Vref=26, minBit 3, minWin=25, winSum=414
8449 22:13:00.414388 TX Vref=28, minBit 0, minWin=25, winSum=417
8450 22:13:00.417893 TX Vref=30, minBit 0, minWin=25, winSum=413
8451 22:13:00.421380 TX Vref=32, minBit 0, minWin=24, winSum=406
8452 22:13:00.424368 TX Vref=34, minBit 0, minWin=23, winSum=397
8453 22:13:00.431019 TX Vref=36, minBit 0, minWin=23, winSum=384
8454 22:13:00.434098 [TxChooseVref] Worse bit 0, Min win 25, Win sum 417, Final Vref 28
8455 22:13:00.434514
8456 22:13:00.437543 Final TX Range 0 Vref 28
8457 22:13:00.437991
8458 22:13:00.438356 ==
8459 22:13:00.440697 Dram Type= 6, Freq= 0, CH_1, rank 0
8460 22:13:00.444326 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8461 22:13:00.447357 ==
8462 22:13:00.447735
8463 22:13:00.448054
8464 22:13:00.448350 TX Vref Scan disable
8465 22:13:00.454307 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8466 22:13:00.454685 == TX Byte 0 ==
8467 22:13:00.457236 u2DelayCellOfst[0]=17 cells (5 PI)
8468 22:13:00.460933 u2DelayCellOfst[1]=10 cells (3 PI)
8469 22:13:00.463712 u2DelayCellOfst[2]=0 cells (0 PI)
8470 22:13:00.467109 u2DelayCellOfst[3]=7 cells (2 PI)
8471 22:13:00.470702 u2DelayCellOfst[4]=10 cells (3 PI)
8472 22:13:00.474091 u2DelayCellOfst[5]=17 cells (5 PI)
8473 22:13:00.477196 u2DelayCellOfst[6]=14 cells (4 PI)
8474 22:13:00.480691 u2DelayCellOfst[7]=7 cells (2 PI)
8475 22:13:00.483772 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8476 22:13:00.487474 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8477 22:13:00.490517 == TX Byte 1 ==
8478 22:13:00.493434 u2DelayCellOfst[8]=0 cells (0 PI)
8479 22:13:00.497059 u2DelayCellOfst[9]=7 cells (2 PI)
8480 22:13:00.500265 u2DelayCellOfst[10]=10 cells (3 PI)
8481 22:13:00.503756 u2DelayCellOfst[11]=7 cells (2 PI)
8482 22:13:00.506430 u2DelayCellOfst[12]=14 cells (4 PI)
8483 22:13:00.510404 u2DelayCellOfst[13]=14 cells (4 PI)
8484 22:13:00.514101 u2DelayCellOfst[14]=17 cells (5 PI)
8485 22:13:00.516591 u2DelayCellOfst[15]=17 cells (5 PI)
8486 22:13:00.519645 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8487 22:13:00.523241 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8488 22:13:00.526200 DramC Write-DBI on
8489 22:13:00.526620 ==
8490 22:13:00.529518 Dram Type= 6, Freq= 0, CH_1, rank 0
8491 22:13:00.533030 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8492 22:13:00.533538 ==
8493 22:13:00.533898
8494 22:13:00.534213
8495 22:13:00.536112 TX Vref Scan disable
8496 22:13:00.539490 == TX Byte 0 ==
8497 22:13:00.542730 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8498 22:13:00.543289 == TX Byte 1 ==
8499 22:13:00.549498 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8500 22:13:00.549920 DramC Write-DBI off
8501 22:13:00.550276
8502 22:13:00.550588 [DATLAT]
8503 22:13:00.552596 Freq=1600, CH1 RK0
8504 22:13:00.553032
8505 22:13:00.556560 DATLAT Default: 0xf
8506 22:13:00.557073 0, 0xFFFF, sum = 0
8507 22:13:00.559558 1, 0xFFFF, sum = 0
8508 22:13:00.559986 2, 0xFFFF, sum = 0
8509 22:13:00.562845 3, 0xFFFF, sum = 0
8510 22:13:00.563427 4, 0xFFFF, sum = 0
8511 22:13:00.566251 5, 0xFFFF, sum = 0
8512 22:13:00.566740 6, 0xFFFF, sum = 0
8513 22:13:00.569329 7, 0xFFFF, sum = 0
8514 22:13:00.569861 8, 0xFFFF, sum = 0
8515 22:13:00.572600 9, 0xFFFF, sum = 0
8516 22:13:00.573144 10, 0xFFFF, sum = 0
8517 22:13:00.575978 11, 0xFFFF, sum = 0
8518 22:13:00.576420 12, 0xFFFF, sum = 0
8519 22:13:00.579140 13, 0xFFFF, sum = 0
8520 22:13:00.579626 14, 0x0, sum = 1
8521 22:13:00.583075 15, 0x0, sum = 2
8522 22:13:00.583672 16, 0x0, sum = 3
8523 22:13:00.585881 17, 0x0, sum = 4
8524 22:13:00.586440 best_step = 15
8525 22:13:00.586798
8526 22:13:00.587112 ==
8527 22:13:00.589377 Dram Type= 6, Freq= 0, CH_1, rank 0
8528 22:13:00.596607 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8529 22:13:00.597044 ==
8530 22:13:00.597381 RX Vref Scan: 1
8531 22:13:00.597705
8532 22:13:00.598630 Set Vref Range= 24 -> 127
8533 22:13:00.599050
8534 22:13:00.602445 RX Vref 24 -> 127, step: 1
8535 22:13:00.602877
8536 22:13:00.605516 RX Delay 19 -> 252, step: 4
8537 22:13:00.605935
8538 22:13:00.608613 Set Vref, RX VrefLevel [Byte0]: 24
8539 22:13:00.611539 [Byte1]: 24
8540 22:13:00.611958
8541 22:13:00.615032 Set Vref, RX VrefLevel [Byte0]: 25
8542 22:13:00.619324 [Byte1]: 25
8543 22:13:00.619740
8544 22:13:00.621715 Set Vref, RX VrefLevel [Byte0]: 26
8545 22:13:00.625264 [Byte1]: 26
8546 22:13:00.628430
8547 22:13:00.628843 Set Vref, RX VrefLevel [Byte0]: 27
8548 22:13:00.631625 [Byte1]: 27
8549 22:13:00.635594
8550 22:13:00.636008 Set Vref, RX VrefLevel [Byte0]: 28
8551 22:13:00.639487 [Byte1]: 28
8552 22:13:00.643645
8553 22:13:00.644058 Set Vref, RX VrefLevel [Byte0]: 29
8554 22:13:00.646532 [Byte1]: 29
8555 22:13:00.651623
8556 22:13:00.652039 Set Vref, RX VrefLevel [Byte0]: 30
8557 22:13:00.654109 [Byte1]: 30
8558 22:13:00.658787
8559 22:13:00.659215 Set Vref, RX VrefLevel [Byte0]: 31
8560 22:13:00.662287 [Byte1]: 31
8561 22:13:00.666202
8562 22:13:00.666617 Set Vref, RX VrefLevel [Byte0]: 32
8563 22:13:00.669249 [Byte1]: 32
8564 22:13:00.673586
8565 22:13:00.674000 Set Vref, RX VrefLevel [Byte0]: 33
8566 22:13:00.676918 [Byte1]: 33
8567 22:13:00.681275
8568 22:13:00.681688 Set Vref, RX VrefLevel [Byte0]: 34
8569 22:13:00.684668 [Byte1]: 34
8570 22:13:00.688692
8571 22:13:00.689112 Set Vref, RX VrefLevel [Byte0]: 35
8572 22:13:00.691963 [Byte1]: 35
8573 22:13:00.696531
8574 22:13:00.696945 Set Vref, RX VrefLevel [Byte0]: 36
8575 22:13:00.699648 [Byte1]: 36
8576 22:13:00.704486
8577 22:13:00.704901 Set Vref, RX VrefLevel [Byte0]: 37
8578 22:13:00.707161 [Byte1]: 37
8579 22:13:00.711772
8580 22:13:00.712187 Set Vref, RX VrefLevel [Byte0]: 38
8581 22:13:00.714576 [Byte1]: 38
8582 22:13:00.718811
8583 22:13:00.718894 Set Vref, RX VrefLevel [Byte0]: 39
8584 22:13:00.722512 [Byte1]: 39
8585 22:13:00.726429
8586 22:13:00.726510 Set Vref, RX VrefLevel [Byte0]: 40
8587 22:13:00.729610 [Byte1]: 40
8588 22:13:00.734017
8589 22:13:00.734097 Set Vref, RX VrefLevel [Byte0]: 41
8590 22:13:00.737381 [Byte1]: 41
8591 22:13:00.741465
8592 22:13:00.741546 Set Vref, RX VrefLevel [Byte0]: 42
8593 22:13:00.744655 [Byte1]: 42
8594 22:13:00.749136
8595 22:13:00.749216 Set Vref, RX VrefLevel [Byte0]: 43
8596 22:13:00.752569 [Byte1]: 43
8597 22:13:00.756368
8598 22:13:00.756448 Set Vref, RX VrefLevel [Byte0]: 44
8599 22:13:00.760479 [Byte1]: 44
8600 22:13:00.764079
8601 22:13:00.764160 Set Vref, RX VrefLevel [Byte0]: 45
8602 22:13:00.767786 [Byte1]: 45
8603 22:13:00.771937
8604 22:13:00.772029 Set Vref, RX VrefLevel [Byte0]: 46
8605 22:13:00.775232 [Byte1]: 46
8606 22:13:00.779822
8607 22:13:00.779973 Set Vref, RX VrefLevel [Byte0]: 47
8608 22:13:00.786277 [Byte1]: 47
8609 22:13:00.786461
8610 22:13:00.789030 Set Vref, RX VrefLevel [Byte0]: 48
8611 22:13:00.792367 [Byte1]: 48
8612 22:13:00.792555
8613 22:13:00.795933 Set Vref, RX VrefLevel [Byte0]: 49
8614 22:13:00.799085 [Byte1]: 49
8615 22:13:00.799296
8616 22:13:00.802491 Set Vref, RX VrefLevel [Byte0]: 50
8617 22:13:00.805833 [Byte1]: 50
8618 22:13:00.810234
8619 22:13:00.810481 Set Vref, RX VrefLevel [Byte0]: 51
8620 22:13:00.812811 [Byte1]: 51
8621 22:13:00.817566
8622 22:13:00.817862 Set Vref, RX VrefLevel [Byte0]: 52
8623 22:13:00.820727 [Byte1]: 52
8624 22:13:00.824967
8625 22:13:00.825389 Set Vref, RX VrefLevel [Byte0]: 53
8626 22:13:00.828280 [Byte1]: 53
8627 22:13:00.832866
8628 22:13:00.833281 Set Vref, RX VrefLevel [Byte0]: 54
8629 22:13:00.835987 [Byte1]: 54
8630 22:13:00.840162
8631 22:13:00.840578 Set Vref, RX VrefLevel [Byte0]: 55
8632 22:13:00.843705 [Byte1]: 55
8633 22:13:00.847727
8634 22:13:00.848140 Set Vref, RX VrefLevel [Byte0]: 56
8635 22:13:00.851334 [Byte1]: 56
8636 22:13:00.855284
8637 22:13:00.855701 Set Vref, RX VrefLevel [Byte0]: 57
8638 22:13:00.858538 [Byte1]: 57
8639 22:13:00.863330
8640 22:13:00.863744 Set Vref, RX VrefLevel [Byte0]: 58
8641 22:13:00.866190 [Byte1]: 58
8642 22:13:00.870751
8643 22:13:00.871168 Set Vref, RX VrefLevel [Byte0]: 59
8644 22:13:00.873772 [Byte1]: 59
8645 22:13:00.878306
8646 22:13:00.878720 Set Vref, RX VrefLevel [Byte0]: 60
8647 22:13:00.881630 [Byte1]: 60
8648 22:13:00.885845
8649 22:13:00.886270 Set Vref, RX VrefLevel [Byte0]: 61
8650 22:13:00.889267 [Byte1]: 61
8651 22:13:00.893146
8652 22:13:00.893561 Set Vref, RX VrefLevel [Byte0]: 62
8653 22:13:00.896864 [Byte1]: 62
8654 22:13:00.900708
8655 22:13:00.901123 Set Vref, RX VrefLevel [Byte0]: 63
8656 22:13:00.904108 [Byte1]: 63
8657 22:13:00.908497
8658 22:13:00.908946 Set Vref, RX VrefLevel [Byte0]: 64
8659 22:13:00.912026 [Byte1]: 64
8660 22:13:00.915845
8661 22:13:00.916261 Set Vref, RX VrefLevel [Byte0]: 65
8662 22:13:00.919227 [Byte1]: 65
8663 22:13:00.923426
8664 22:13:00.923842 Set Vref, RX VrefLevel [Byte0]: 66
8665 22:13:00.927094 [Byte1]: 66
8666 22:13:00.931160
8667 22:13:00.931635 Set Vref, RX VrefLevel [Byte0]: 67
8668 22:13:00.934451 [Byte1]: 67
8669 22:13:00.938501
8670 22:13:00.938938 Set Vref, RX VrefLevel [Byte0]: 68
8671 22:13:00.942045 [Byte1]: 68
8672 22:13:00.946506
8673 22:13:00.946933 Set Vref, RX VrefLevel [Byte0]: 69
8674 22:13:00.949682 [Byte1]: 69
8675 22:13:00.954016
8676 22:13:00.954425 Set Vref, RX VrefLevel [Byte0]: 70
8677 22:13:00.957248 [Byte1]: 70
8678 22:13:00.961468
8679 22:13:00.961908 Final RX Vref Byte 0 = 61 to rank0
8680 22:13:00.964947 Final RX Vref Byte 1 = 60 to rank0
8681 22:13:00.967866 Final RX Vref Byte 0 = 61 to rank1
8682 22:13:00.971912 Final RX Vref Byte 1 = 60 to rank1==
8683 22:13:00.974628 Dram Type= 6, Freq= 0, CH_1, rank 0
8684 22:13:00.981453 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8685 22:13:00.981910 ==
8686 22:13:00.982258 DQS Delay:
8687 22:13:00.984683 DQS0 = 0, DQS1 = 0
8688 22:13:00.985142 DQM Delay:
8689 22:13:00.985474 DQM0 = 133, DQM1 = 130
8690 22:13:00.987570 DQ Delay:
8691 22:13:00.991422 DQ0 =138, DQ1 =130, DQ2 =118, DQ3 =132
8692 22:13:00.994264 DQ4 =130, DQ5 =142, DQ6 =146, DQ7 =130
8693 22:13:00.997794 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =122
8694 22:13:01.001342 DQ12 =140, DQ13 =140, DQ14 =136, DQ15 =140
8695 22:13:01.001785
8696 22:13:01.002119
8697 22:13:01.002454
8698 22:13:01.004312 [DramC_TX_OE_Calibration] TA2
8699 22:13:01.007933 Original DQ_B0 (3 6) =30, OEN = 27
8700 22:13:01.010810 Original DQ_B1 (3 6) =30, OEN = 27
8701 22:13:01.014134 24, 0x0, End_B0=24 End_B1=24
8702 22:13:01.017662 25, 0x0, End_B0=25 End_B1=25
8703 22:13:01.018082 26, 0x0, End_B0=26 End_B1=26
8704 22:13:01.020942 27, 0x0, End_B0=27 End_B1=27
8705 22:13:01.024053 28, 0x0, End_B0=28 End_B1=28
8706 22:13:01.027340 29, 0x0, End_B0=29 End_B1=29
8707 22:13:01.027818 30, 0x0, End_B0=30 End_B1=30
8708 22:13:01.030770 31, 0x4141, End_B0=30 End_B1=30
8709 22:13:01.033576 Byte0 end_step=30 best_step=27
8710 22:13:01.037261 Byte1 end_step=30 best_step=27
8711 22:13:01.040497 Byte0 TX OE(2T, 0.5T) = (3, 3)
8712 22:13:01.043736 Byte1 TX OE(2T, 0.5T) = (3, 3)
8713 22:13:01.044329
8714 22:13:01.044766
8715 22:13:01.050094 [DQSOSCAuto] RK0, (LSB)MR18= 0xa13, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 404 ps
8716 22:13:01.053501 CH1 RK0: MR19=303, MR18=A13
8717 22:13:01.060405 CH1_RK0: MR19=0x303, MR18=0xA13, DQSOSC=400, MR23=63, INC=23, DEC=15
8718 22:13:01.060821
8719 22:13:01.063208 ----->DramcWriteLeveling(PI) begin...
8720 22:13:01.063688 ==
8721 22:13:01.066666 Dram Type= 6, Freq= 0, CH_1, rank 1
8722 22:13:01.069944 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8723 22:13:01.070361 ==
8724 22:13:01.073132 Write leveling (Byte 0): 24 => 24
8725 22:13:01.076875 Write leveling (Byte 1): 25 => 25
8726 22:13:01.079636 DramcWriteLeveling(PI) end<-----
8727 22:13:01.080047
8728 22:13:01.080370 ==
8729 22:13:01.082890 Dram Type= 6, Freq= 0, CH_1, rank 1
8730 22:13:01.089442 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8731 22:13:01.089953 ==
8732 22:13:01.090290 [Gating] SW mode calibration
8733 22:13:01.099588 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8734 22:13:01.102554 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8735 22:13:01.106301 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8736 22:13:01.113105 1 4 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8737 22:13:01.116070 1 4 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8738 22:13:01.119149 1 4 12 | B1->B0 | 2a2a 3434 | 1 1 | (0 0) (1 1)
8739 22:13:01.125885 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8740 22:13:01.129326 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8741 22:13:01.132379 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8742 22:13:01.139279 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8743 22:13:01.142741 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8744 22:13:01.145872 1 5 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
8745 22:13:01.152151 1 5 8 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
8746 22:13:01.155715 1 5 12 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
8747 22:13:01.159249 1 5 16 | B1->B0 | 2424 2323 | 0 0 | (0 1) (0 0)
8748 22:13:01.165321 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8749 22:13:01.168948 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8750 22:13:01.172375 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8751 22:13:01.178890 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8752 22:13:01.182025 1 6 4 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
8753 22:13:01.185600 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8754 22:13:01.191742 1 6 12 | B1->B0 | 3535 4646 | 1 0 | (0 0) (0 0)
8755 22:13:01.195524 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8756 22:13:01.198835 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8757 22:13:01.204810 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8758 22:13:01.208169 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8759 22:13:01.211702 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8760 22:13:01.218598 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8761 22:13:01.221719 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8762 22:13:01.224870 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8763 22:13:01.231432 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8764 22:13:01.234889 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8765 22:13:01.237633 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8766 22:13:01.244455 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8767 22:13:01.247845 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8768 22:13:01.252957 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8769 22:13:01.257833 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8770 22:13:01.260696 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8771 22:13:01.267709 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8772 22:13:01.270925 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8773 22:13:01.274221 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8774 22:13:01.280360 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8775 22:13:01.283892 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8776 22:13:01.287482 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8777 22:13:01.290568 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8778 22:13:01.297264 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8779 22:13:01.300402 Total UI for P1: 0, mck2ui 16
8780 22:13:01.304032 best dqsien dly found for B0: ( 1, 9, 6)
8781 22:13:01.306973 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8782 22:13:01.310696 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8783 22:13:01.313639 Total UI for P1: 0, mck2ui 16
8784 22:13:01.316863 best dqsien dly found for B1: ( 1, 9, 14)
8785 22:13:01.320032 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8786 22:13:01.326783 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8787 22:13:01.327238
8788 22:13:01.330100 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8789 22:13:01.333307 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8790 22:13:01.336657 [Gating] SW calibration Done
8791 22:13:01.337073 ==
8792 22:13:01.340051 Dram Type= 6, Freq= 0, CH_1, rank 1
8793 22:13:01.343097 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8794 22:13:01.343593 ==
8795 22:13:01.346603 RX Vref Scan: 0
8796 22:13:01.347022
8797 22:13:01.347407 RX Vref 0 -> 0, step: 1
8798 22:13:01.347727
8799 22:13:01.349646 RX Delay 0 -> 252, step: 8
8800 22:13:01.353365 iDelay=200, Bit 0, Center 143 (88 ~ 199) 112
8801 22:13:01.359960 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8802 22:13:01.363091 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8803 22:13:01.365985 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8804 22:13:01.369653 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8805 22:13:01.372644 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8806 22:13:01.379427 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8807 22:13:01.383091 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8808 22:13:01.386073 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8809 22:13:01.389178 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8810 22:13:01.392396 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8811 22:13:01.399142 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8812 22:13:01.403225 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8813 22:13:01.405683 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8814 22:13:01.409224 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8815 22:13:01.415806 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8816 22:13:01.416325 ==
8817 22:13:01.419505 Dram Type= 6, Freq= 0, CH_1, rank 1
8818 22:13:01.422225 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8819 22:13:01.422729 ==
8820 22:13:01.423066 DQS Delay:
8821 22:13:01.425454 DQS0 = 0, DQS1 = 0
8822 22:13:01.425876 DQM Delay:
8823 22:13:01.428669 DQM0 = 137, DQM1 = 130
8824 22:13:01.429127 DQ Delay:
8825 22:13:01.432148 DQ0 =143, DQ1 =135, DQ2 =123, DQ3 =135
8826 22:13:01.435601 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =135
8827 22:13:01.438621 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8828 22:13:01.442178 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8829 22:13:01.442599
8830 22:13:01.445290
8831 22:13:01.445710 ==
8832 22:13:01.448669 Dram Type= 6, Freq= 0, CH_1, rank 1
8833 22:13:01.451981 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8834 22:13:01.452405 ==
8835 22:13:01.452737
8836 22:13:01.453050
8837 22:13:01.455282 TX Vref Scan disable
8838 22:13:01.455724 == TX Byte 0 ==
8839 22:13:01.461500 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8840 22:13:01.464911 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8841 22:13:01.465335 == TX Byte 1 ==
8842 22:13:01.471678 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8843 22:13:01.474721 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8844 22:13:01.475145 ==
8845 22:13:01.478872 Dram Type= 6, Freq= 0, CH_1, rank 1
8846 22:13:01.482129 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8847 22:13:01.482562 ==
8848 22:13:01.495976
8849 22:13:01.498974 TX Vref early break, caculate TX vref
8850 22:13:01.502306 TX Vref=16, minBit 13, minWin=22, winSum=382
8851 22:13:01.506122 TX Vref=18, minBit 9, minWin=22, winSum=383
8852 22:13:01.509014 TX Vref=20, minBit 9, minWin=22, winSum=395
8853 22:13:01.511976 TX Vref=22, minBit 9, minWin=23, winSum=403
8854 22:13:01.515471 TX Vref=24, minBit 9, minWin=24, winSum=410
8855 22:13:01.522318 TX Vref=26, minBit 9, minWin=24, winSum=418
8856 22:13:01.525369 TX Vref=28, minBit 3, minWin=25, winSum=420
8857 22:13:01.529340 TX Vref=30, minBit 0, minWin=25, winSum=416
8858 22:13:01.532181 TX Vref=32, minBit 0, minWin=24, winSum=409
8859 22:13:01.535553 TX Vref=34, minBit 0, minWin=24, winSum=404
8860 22:13:01.541889 TX Vref=36, minBit 8, minWin=23, winSum=390
8861 22:13:01.545441 [TxChooseVref] Worse bit 3, Min win 25, Win sum 420, Final Vref 28
8862 22:13:01.545865
8863 22:13:01.548556 Final TX Range 0 Vref 28
8864 22:13:01.548976
8865 22:13:01.549309 ==
8866 22:13:01.551596 Dram Type= 6, Freq= 0, CH_1, rank 1
8867 22:13:01.555203 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8868 22:13:01.558483 ==
8869 22:13:01.558899
8870 22:13:01.559269
8871 22:13:01.559585 TX Vref Scan disable
8872 22:13:01.565844 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8873 22:13:01.566276 == TX Byte 0 ==
8874 22:13:01.568473 u2DelayCellOfst[0]=14 cells (4 PI)
8875 22:13:01.572138 u2DelayCellOfst[1]=10 cells (3 PI)
8876 22:13:01.574743 u2DelayCellOfst[2]=0 cells (0 PI)
8877 22:13:01.578172 u2DelayCellOfst[3]=7 cells (2 PI)
8878 22:13:01.581701 u2DelayCellOfst[4]=7 cells (2 PI)
8879 22:13:01.584714 u2DelayCellOfst[5]=14 cells (4 PI)
8880 22:13:01.587802 u2DelayCellOfst[6]=14 cells (4 PI)
8881 22:13:01.591270 u2DelayCellOfst[7]=7 cells (2 PI)
8882 22:13:01.594493 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8883 22:13:01.597721 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8884 22:13:01.601214 == TX Byte 1 ==
8885 22:13:01.604256 u2DelayCellOfst[8]=0 cells (0 PI)
8886 22:13:01.607675 u2DelayCellOfst[9]=3 cells (1 PI)
8887 22:13:01.611075 u2DelayCellOfst[10]=10 cells (3 PI)
8888 22:13:01.614468 u2DelayCellOfst[11]=3 cells (1 PI)
8889 22:13:01.618097 u2DelayCellOfst[12]=14 cells (4 PI)
8890 22:13:01.621685 u2DelayCellOfst[13]=14 cells (4 PI)
8891 22:13:01.624113 u2DelayCellOfst[14]=17 cells (5 PI)
8892 22:13:01.627601 u2DelayCellOfst[15]=17 cells (5 PI)
8893 22:13:01.630796 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8894 22:13:01.634418 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8895 22:13:01.637597 DramC Write-DBI on
8896 22:13:01.638021 ==
8897 22:13:01.641207 Dram Type= 6, Freq= 0, CH_1, rank 1
8898 22:13:01.645147 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8899 22:13:01.645730 ==
8900 22:13:01.646159
8901 22:13:01.646483
8902 22:13:01.647481 TX Vref Scan disable
8903 22:13:01.647904 == TX Byte 0 ==
8904 22:13:01.654142 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8905 22:13:01.654633 == TX Byte 1 ==
8906 22:13:01.657031 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8907 22:13:01.660335 DramC Write-DBI off
8908 22:13:01.660758
8909 22:13:01.661093 [DATLAT]
8910 22:13:01.664155 Freq=1600, CH1 RK1
8911 22:13:01.664606
8912 22:13:01.664944 DATLAT Default: 0xf
8913 22:13:01.667838 0, 0xFFFF, sum = 0
8914 22:13:01.670441 1, 0xFFFF, sum = 0
8915 22:13:01.670867 2, 0xFFFF, sum = 0
8916 22:13:01.673852 3, 0xFFFF, sum = 0
8917 22:13:01.674279 4, 0xFFFF, sum = 0
8918 22:13:01.677434 5, 0xFFFF, sum = 0
8919 22:13:01.677863 6, 0xFFFF, sum = 0
8920 22:13:01.680542 7, 0xFFFF, sum = 0
8921 22:13:01.680970 8, 0xFFFF, sum = 0
8922 22:13:01.683742 9, 0xFFFF, sum = 0
8923 22:13:01.684171 10, 0xFFFF, sum = 0
8924 22:13:01.687825 11, 0xFFFF, sum = 0
8925 22:13:01.688332 12, 0xFFFF, sum = 0
8926 22:13:01.690251 13, 0xFFFF, sum = 0
8927 22:13:01.690682 14, 0x0, sum = 1
8928 22:13:01.693614 15, 0x0, sum = 2
8929 22:13:01.694087 16, 0x0, sum = 3
8930 22:13:01.696685 17, 0x0, sum = 4
8931 22:13:01.697177 best_step = 15
8932 22:13:01.697539
8933 22:13:01.697911 ==
8934 22:13:01.700460 Dram Type= 6, Freq= 0, CH_1, rank 1
8935 22:13:01.706997 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8936 22:13:01.707511 ==
8937 22:13:01.707930 RX Vref Scan: 0
8938 22:13:01.708276
8939 22:13:01.710788 RX Vref 0 -> 0, step: 1
8940 22:13:01.711291
8941 22:13:01.713506 RX Delay 19 -> 252, step: 4
8942 22:13:01.716638 iDelay=195, Bit 0, Center 136 (87 ~ 186) 100
8943 22:13:01.719800 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8944 22:13:01.723346 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8945 22:13:01.730150 iDelay=195, Bit 3, Center 130 (79 ~ 182) 104
8946 22:13:01.732958 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
8947 22:13:01.736697 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8948 22:13:01.739684 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
8949 22:13:01.743329 iDelay=195, Bit 7, Center 130 (79 ~ 182) 104
8950 22:13:01.749320 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8951 22:13:01.752788 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8952 22:13:01.756463 iDelay=195, Bit 10, Center 130 (75 ~ 186) 112
8953 22:13:01.760040 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8954 22:13:01.766222 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8955 22:13:01.769678 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8956 22:13:01.773017 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8957 22:13:01.775937 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8958 22:13:01.776364 ==
8959 22:13:01.779233 Dram Type= 6, Freq= 0, CH_1, rank 1
8960 22:13:01.786047 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8961 22:13:01.786577 ==
8962 22:13:01.786915 DQS Delay:
8963 22:13:01.789001 DQS0 = 0, DQS1 = 0
8964 22:13:01.789421 DQM Delay:
8965 22:13:01.789752 DQM0 = 132, DQM1 = 128
8966 22:13:01.792140 DQ Delay:
8967 22:13:01.796009 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =130
8968 22:13:01.799114 DQ4 =130, DQ5 =144, DQ6 =140, DQ7 =130
8969 22:13:01.802069 DQ8 =114, DQ9 =118, DQ10 =130, DQ11 =120
8970 22:13:01.805270 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =138
8971 22:13:01.805693
8972 22:13:01.806068
8973 22:13:01.806381
8974 22:13:01.808960 [DramC_TX_OE_Calibration] TA2
8975 22:13:01.812414 Original DQ_B0 (3 6) =30, OEN = 27
8976 22:13:01.814902 Original DQ_B1 (3 6) =30, OEN = 27
8977 22:13:01.818458 24, 0x0, End_B0=24 End_B1=24
8978 22:13:01.821698 25, 0x0, End_B0=25 End_B1=25
8979 22:13:01.822149 26, 0x0, End_B0=26 End_B1=26
8980 22:13:01.825084 27, 0x0, End_B0=27 End_B1=27
8981 22:13:01.828418 28, 0x0, End_B0=28 End_B1=28
8982 22:13:01.832478 29, 0x0, End_B0=29 End_B1=29
8983 22:13:01.832898 30, 0x0, End_B0=30 End_B1=30
8984 22:13:01.834896 31, 0x5151, End_B0=30 End_B1=30
8985 22:13:01.838445 Byte0 end_step=30 best_step=27
8986 22:13:01.841686 Byte1 end_step=30 best_step=27
8987 22:13:01.845015 Byte0 TX OE(2T, 0.5T) = (3, 3)
8988 22:13:01.848130 Byte1 TX OE(2T, 0.5T) = (3, 3)
8989 22:13:01.848546
8990 22:13:01.848916
8991 22:13:01.855057 [DQSOSCAuto] RK1, (LSB)MR18= 0xd1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 403 ps
8992 22:13:01.858011 CH1 RK1: MR19=303, MR18=D1B
8993 22:13:01.864669 CH1_RK1: MR19=0x303, MR18=0xD1B, DQSOSC=396, MR23=63, INC=23, DEC=15
8994 22:13:01.868504 [RxdqsGatingPostProcess] freq 1600
8995 22:13:01.874196 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8996 22:13:01.874781 best DQS0 dly(2T, 0.5T) = (1, 1)
8997 22:13:01.878337 best DQS1 dly(2T, 0.5T) = (1, 1)
8998 22:13:01.881104 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8999 22:13:01.885252 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9000 22:13:01.887681 best DQS0 dly(2T, 0.5T) = (1, 1)
9001 22:13:01.891039 best DQS1 dly(2T, 0.5T) = (1, 1)
9002 22:13:01.894339 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9003 22:13:01.897392 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9004 22:13:01.900996 Pre-setting of DQS Precalculation
9005 22:13:01.904133 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9006 22:13:01.913963 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9007 22:13:01.920870 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9008 22:13:01.921305
9009 22:13:01.921730
9010 22:13:01.923711 [Calibration Summary] 3200 Mbps
9011 22:13:01.924139 CH 0, Rank 0
9012 22:13:01.927002 SW Impedance : PASS
9013 22:13:01.927466 DUTY Scan : NO K
9014 22:13:01.930276 ZQ Calibration : PASS
9015 22:13:01.933825 Jitter Meter : NO K
9016 22:13:01.934251 CBT Training : PASS
9017 22:13:01.937021 Write leveling : PASS
9018 22:13:01.940258 RX DQS gating : PASS
9019 22:13:01.940683 RX DQ/DQS(RDDQC) : PASS
9020 22:13:01.943725 TX DQ/DQS : PASS
9021 22:13:01.946745 RX DATLAT : PASS
9022 22:13:01.947164 RX DQ/DQS(Engine): PASS
9023 22:13:01.950069 TX OE : PASS
9024 22:13:01.950491 All Pass.
9025 22:13:01.950824
9026 22:13:01.953400 CH 0, Rank 1
9027 22:13:01.953818 SW Impedance : PASS
9028 22:13:01.957085 DUTY Scan : NO K
9029 22:13:01.960109 ZQ Calibration : PASS
9030 22:13:01.960530 Jitter Meter : NO K
9031 22:13:01.963464 CBT Training : PASS
9032 22:13:01.967003 Write leveling : PASS
9033 22:13:01.967594 RX DQS gating : PASS
9034 22:13:01.970198 RX DQ/DQS(RDDQC) : PASS
9035 22:13:01.973022 TX DQ/DQS : PASS
9036 22:13:01.973450 RX DATLAT : PASS
9037 22:13:01.976258 RX DQ/DQS(Engine): PASS
9038 22:13:01.979490 TX OE : PASS
9039 22:13:01.979916 All Pass.
9040 22:13:01.980249
9041 22:13:01.980564 CH 1, Rank 0
9042 22:13:01.982908 SW Impedance : PASS
9043 22:13:01.986411 DUTY Scan : NO K
9044 22:13:01.986830 ZQ Calibration : PASS
9045 22:13:01.989507 Jitter Meter : NO K
9046 22:13:01.993066 CBT Training : PASS
9047 22:13:01.993599 Write leveling : PASS
9048 22:13:01.995856 RX DQS gating : PASS
9049 22:13:01.999426 RX DQ/DQS(RDDQC) : PASS
9050 22:13:01.999847 TX DQ/DQS : PASS
9051 22:13:02.002790 RX DATLAT : PASS
9052 22:13:02.003248 RX DQ/DQS(Engine): PASS
9053 22:13:02.005886 TX OE : PASS
9054 22:13:02.006309 All Pass.
9055 22:13:02.006644
9056 22:13:02.009161 CH 1, Rank 1
9057 22:13:02.012773 SW Impedance : PASS
9058 22:13:02.013197 DUTY Scan : NO K
9059 22:13:02.015630 ZQ Calibration : PASS
9060 22:13:02.016073 Jitter Meter : NO K
9061 22:13:02.019419 CBT Training : PASS
9062 22:13:02.022685 Write leveling : PASS
9063 22:13:02.023107 RX DQS gating : PASS
9064 22:13:02.025738 RX DQ/DQS(RDDQC) : PASS
9065 22:13:02.029219 TX DQ/DQS : PASS
9066 22:13:02.029647 RX DATLAT : PASS
9067 22:13:02.032501 RX DQ/DQS(Engine): PASS
9068 22:13:02.035633 TX OE : PASS
9069 22:13:02.036204 All Pass.
9070 22:13:02.036574
9071 22:13:02.039345 DramC Write-DBI on
9072 22:13:02.039769 PER_BANK_REFRESH: Hybrid Mode
9073 22:13:02.042193 TX_TRACKING: ON
9074 22:13:02.052061 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9075 22:13:02.058673 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9076 22:13:02.065710 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9077 22:13:02.069215 [FAST_K] Save calibration result to emmc
9078 22:13:02.071919 sync common calibartion params.
9079 22:13:02.075210 sync cbt_mode0:1, 1:1
9080 22:13:02.075631 dram_init: ddr_geometry: 2
9081 22:13:02.078218 dram_init: ddr_geometry: 2
9082 22:13:02.081989 dram_init: ddr_geometry: 2
9083 22:13:02.085127 0:dram_rank_size:100000000
9084 22:13:02.085706 1:dram_rank_size:100000000
9085 22:13:02.092092 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9086 22:13:02.095109 DFS_SHUFFLE_HW_MODE: ON
9087 22:13:02.098451 dramc_set_vcore_voltage set vcore to 725000
9088 22:13:02.101570 Read voltage for 1600, 0
9089 22:13:02.101985 Vio18 = 0
9090 22:13:02.102336 Vcore = 725000
9091 22:13:02.104871 Vdram = 0
9092 22:13:02.105284 Vddq = 0
9093 22:13:02.105616 Vmddr = 0
9094 22:13:02.108533 switch to 3200 Mbps bootup
9095 22:13:02.109083 [DramcRunTimeConfig]
9096 22:13:02.111229 PHYPLL
9097 22:13:02.111643 DPM_CONTROL_AFTERK: ON
9098 22:13:02.114813 PER_BANK_REFRESH: ON
9099 22:13:02.118097 REFRESH_OVERHEAD_REDUCTION: ON
9100 22:13:02.118674 CMD_PICG_NEW_MODE: OFF
9101 22:13:02.121363 XRTWTW_NEW_MODE: ON
9102 22:13:02.121780 XRTRTR_NEW_MODE: ON
9103 22:13:02.124865 TX_TRACKING: ON
9104 22:13:02.125366 RDSEL_TRACKING: OFF
9105 22:13:02.127850 DQS Precalculation for DVFS: ON
9106 22:13:02.131137 RX_TRACKING: OFF
9107 22:13:02.131590 HW_GATING DBG: ON
9108 22:13:02.134526 ZQCS_ENABLE_LP4: ON
9109 22:13:02.134971 RX_PICG_NEW_MODE: ON
9110 22:13:02.137788 TX_PICG_NEW_MODE: ON
9111 22:13:02.141053 ENABLE_RX_DCM_DPHY: ON
9112 22:13:02.144230 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9113 22:13:02.144701 DUMMY_READ_FOR_TRACKING: OFF
9114 22:13:02.147431 !!! SPM_CONTROL_AFTERK: OFF
9115 22:13:02.150911 !!! SPM could not control APHY
9116 22:13:02.154430 IMPEDANCE_TRACKING: ON
9117 22:13:02.154856 TEMP_SENSOR: ON
9118 22:13:02.157512 HW_SAVE_FOR_SR: OFF
9119 22:13:02.157934 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9120 22:13:02.163914 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9121 22:13:02.164345 Read ODT Tracking: ON
9122 22:13:02.167538 Refresh Rate DeBounce: ON
9123 22:13:02.170831 DFS_NO_QUEUE_FLUSH: ON
9124 22:13:02.171300 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9125 22:13:02.174267 ENABLE_DFS_RUNTIME_MRW: OFF
9126 22:13:02.177111 DDR_RESERVE_NEW_MODE: ON
9127 22:13:02.181089 MR_CBT_SWITCH_FREQ: ON
9128 22:13:02.181609 =========================
9129 22:13:02.200646 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9130 22:13:02.203323 dram_init: ddr_geometry: 2
9131 22:13:02.221862 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9132 22:13:02.225523 dram_init: dram init end (result: 0)
9133 22:13:02.231675 DRAM-K: Full calibration passed in 24426 msecs
9134 22:13:02.235007 MRC: failed to locate region type 0.
9135 22:13:02.235483 DRAM rank0 size:0x100000000,
9136 22:13:02.238050 DRAM rank1 size=0x100000000
9137 22:13:02.248086 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9138 22:13:02.255058 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9139 22:13:02.261509 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9140 22:13:02.271086 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9141 22:13:02.271672 DRAM rank0 size:0x100000000,
9142 22:13:02.274953 DRAM rank1 size=0x100000000
9143 22:13:02.275423 CBMEM:
9144 22:13:02.278494 IMD: root @ 0xfffff000 254 entries.
9145 22:13:02.281318 IMD: root @ 0xffffec00 62 entries.
9146 22:13:02.284481 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9147 22:13:02.291207 WARNING: RO_VPD is uninitialized or empty.
9148 22:13:02.294538 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9149 22:13:02.301463 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9150 22:13:02.314955 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9151 22:13:02.326077 BS: romstage times (exec / console): total (unknown) / 23956 ms
9152 22:13:02.326622
9153 22:13:02.327129
9154 22:13:02.336742 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9155 22:13:02.339070 ARM64: Exception handlers installed.
9156 22:13:02.342566 ARM64: Testing exception
9157 22:13:02.345475 ARM64: Done test exception
9158 22:13:02.345907 Enumerating buses...
9159 22:13:02.348834 Show all devs... Before device enumeration.
9160 22:13:02.352186 Root Device: enabled 1
9161 22:13:02.355762 CPU_CLUSTER: 0: enabled 1
9162 22:13:02.356192 CPU: 00: enabled 1
9163 22:13:02.359048 Compare with tree...
9164 22:13:02.359518 Root Device: enabled 1
9165 22:13:02.362528 CPU_CLUSTER: 0: enabled 1
9166 22:13:02.365470 CPU: 00: enabled 1
9167 22:13:02.365888 Root Device scanning...
9168 22:13:02.368879 scan_static_bus for Root Device
9169 22:13:02.372210 CPU_CLUSTER: 0 enabled
9170 22:13:02.375426 scan_static_bus for Root Device done
9171 22:13:02.378457 scan_bus: bus Root Device finished in 8 msecs
9172 22:13:02.378879 done
9173 22:13:02.385529 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9174 22:13:02.389008 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9175 22:13:02.395410 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9176 22:13:02.399037 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9177 22:13:02.401702 Allocating resources...
9178 22:13:02.404928 Reading resources...
9179 22:13:02.408753 Root Device read_resources bus 0 link: 0
9180 22:13:02.411697 DRAM rank0 size:0x100000000,
9181 22:13:02.412143 DRAM rank1 size=0x100000000
9182 22:13:02.418104 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9183 22:13:02.418605 CPU: 00 missing read_resources
9184 22:13:02.424678 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9185 22:13:02.428121 Root Device read_resources bus 0 link: 0 done
9186 22:13:02.431167 Done reading resources.
9187 22:13:02.434952 Show resources in subtree (Root Device)...After reading.
9188 22:13:02.437830 Root Device child on link 0 CPU_CLUSTER: 0
9189 22:13:02.441145 CPU_CLUSTER: 0 child on link 0 CPU: 00
9190 22:13:02.451312 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9191 22:13:02.451793 CPU: 00
9192 22:13:02.454913 Root Device assign_resources, bus 0 link: 0
9193 22:13:02.457946 CPU_CLUSTER: 0 missing set_resources
9194 22:13:02.464140 Root Device assign_resources, bus 0 link: 0 done
9195 22:13:02.464724 Done setting resources.
9196 22:13:02.470855 Show resources in subtree (Root Device)...After assigning values.
9197 22:13:02.473957 Root Device child on link 0 CPU_CLUSTER: 0
9198 22:13:02.480805 CPU_CLUSTER: 0 child on link 0 CPU: 00
9199 22:13:02.487017 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9200 22:13:02.490805 CPU: 00
9201 22:13:02.491280 Done allocating resources.
9202 22:13:02.497407 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9203 22:13:02.497894 Enabling resources...
9204 22:13:02.500676 done.
9205 22:13:02.503687 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9206 22:13:02.507060 Initializing devices...
9207 22:13:02.507699 Root Device init
9208 22:13:02.510701 init hardware done!
9209 22:13:02.511198 0x00000018: ctrlr->caps
9210 22:13:02.513561 52.000 MHz: ctrlr->f_max
9211 22:13:02.517120 0.400 MHz: ctrlr->f_min
9212 22:13:02.520784 0x40ff8080: ctrlr->voltages
9213 22:13:02.521372 sclk: 390625
9214 22:13:02.521790 Bus Width = 1
9215 22:13:02.523731 sclk: 390625
9216 22:13:02.524151 Bus Width = 1
9217 22:13:02.526708 Early init status = 3
9218 22:13:02.529893 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9219 22:13:02.533395 in-header: 03 fc 00 00 01 00 00 00
9220 22:13:02.536998 in-data: 00
9221 22:13:02.539963 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9222 22:13:02.545696 in-header: 03 fd 00 00 00 00 00 00
9223 22:13:02.548953 in-data:
9224 22:13:02.552009 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9225 22:13:02.556158 in-header: 03 fc 00 00 01 00 00 00
9226 22:13:02.559954 in-data: 00
9227 22:13:02.562606 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9228 22:13:02.568337 in-header: 03 fd 00 00 00 00 00 00
9229 22:13:02.571574 in-data:
9230 22:13:02.574972 [SSUSB] Setting up USB HOST controller...
9231 22:13:02.578253 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9232 22:13:02.581712 [SSUSB] phy power-on done.
9233 22:13:02.585081 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9234 22:13:02.591335 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9235 22:13:02.594647 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9236 22:13:02.601842 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9237 22:13:02.608301 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9238 22:13:02.614321 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9239 22:13:02.621518 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9240 22:13:02.627773 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9241 22:13:02.631272 SPM: binary array size = 0x9dc
9242 22:13:02.634381 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9243 22:13:02.640967 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9244 22:13:02.647417 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9245 22:13:02.653886 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9246 22:13:02.657802 configure_display: Starting display init
9247 22:13:02.691319 anx7625_power_on_init: Init interface.
9248 22:13:02.695048 anx7625_disable_pd_protocol: Disabled PD feature.
9249 22:13:02.698177 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9250 22:13:02.726031 anx7625_start_dp_work: Secure OCM version=00
9251 22:13:02.729123 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9252 22:13:02.744279 sp_tx_get_edid_block: EDID Block = 1
9253 22:13:02.846912 Extracted contents:
9254 22:13:02.850028 header: 00 ff ff ff ff ff ff 00
9255 22:13:02.853915 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9256 22:13:02.856700 version: 01 04
9257 22:13:02.860757 basic params: 95 1f 11 78 0a
9258 22:13:02.863315 chroma info: 76 90 94 55 54 90 27 21 50 54
9259 22:13:02.867038 established: 00 00 00
9260 22:13:02.873105 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9261 22:13:02.876351 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9262 22:13:02.883081 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9263 22:13:02.889695 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9264 22:13:02.896092 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9265 22:13:02.899349 extensions: 00
9266 22:13:02.899768 checksum: fb
9267 22:13:02.900098
9268 22:13:02.902690 Manufacturer: IVO Model 57d Serial Number 0
9269 22:13:02.905876 Made week 0 of 2020
9270 22:13:02.909586 EDID version: 1.4
9271 22:13:02.910094 Digital display
9272 22:13:02.912878 6 bits per primary color channel
9273 22:13:02.913301 DisplayPort interface
9274 22:13:02.916314 Maximum image size: 31 cm x 17 cm
9275 22:13:02.919064 Gamma: 220%
9276 22:13:02.919499 Check DPMS levels
9277 22:13:02.925808 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9278 22:13:02.928988 First detailed timing is preferred timing
9279 22:13:02.929406 Established timings supported:
9280 22:13:02.932167 Standard timings supported:
9281 22:13:02.935578 Detailed timings
9282 22:13:02.938858 Hex of detail: 383680a07038204018303c0035ae10000019
9283 22:13:02.945776 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9284 22:13:02.949069 0780 0798 07c8 0820 hborder 0
9285 22:13:02.952076 0438 043b 0447 0458 vborder 0
9286 22:13:02.956045 -hsync -vsync
9287 22:13:02.956462 Did detailed timing
9288 22:13:02.962282 Hex of detail: 000000000000000000000000000000000000
9289 22:13:02.965720 Manufacturer-specified data, tag 0
9290 22:13:02.969090 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9291 22:13:02.973048 ASCII string: InfoVision
9292 22:13:02.975239 Hex of detail: 000000fe00523134304e574635205248200a
9293 22:13:02.979373 ASCII string: R140NWF5 RH
9294 22:13:02.979789 Checksum
9295 22:13:02.982344 Checksum: 0xfb (valid)
9296 22:13:02.985649 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9297 22:13:02.988314 DSI data_rate: 832800000 bps
9298 22:13:02.995147 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9299 22:13:02.998336 anx7625_parse_edid: pixelclock(138800).
9300 22:13:03.002081 hactive(1920), hsync(48), hfp(24), hbp(88)
9301 22:13:03.005276 vactive(1080), vsync(12), vfp(3), vbp(17)
9302 22:13:03.008517 anx7625_dsi_config: config dsi.
9303 22:13:03.014757 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9304 22:13:03.028781 anx7625_dsi_config: success to config DSI
9305 22:13:03.031727 anx7625_dp_start: MIPI phy setup OK.
9306 22:13:03.036131 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9307 22:13:03.038444 mtk_ddp_mode_set invalid vrefresh 60
9308 22:13:03.041812 main_disp_path_setup
9309 22:13:03.042219 ovl_layer_smi_id_en
9310 22:13:03.045375 ovl_layer_smi_id_en
9311 22:13:03.045781 ccorr_config
9312 22:13:03.046101 aal_config
9313 22:13:03.048607 gamma_config
9314 22:13:03.049014 postmask_config
9315 22:13:03.051879 dither_config
9316 22:13:03.055298 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9317 22:13:03.061376 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9318 22:13:03.064756 Root Device init finished in 553 msecs
9319 22:13:03.068842 CPU_CLUSTER: 0 init
9320 22:13:03.074399 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9321 22:13:03.081606 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9322 22:13:03.082014 APU_MBOX 0x190000b0 = 0x10001
9323 22:13:03.084415 APU_MBOX 0x190001b0 = 0x10001
9324 22:13:03.087726 APU_MBOX 0x190005b0 = 0x10001
9325 22:13:03.091524 APU_MBOX 0x190006b0 = 0x10001
9326 22:13:03.097683 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9327 22:13:03.108124 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9328 22:13:03.120586 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9329 22:13:03.126669 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9330 22:13:03.138333 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9331 22:13:03.147884 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9332 22:13:03.150670 CPU_CLUSTER: 0 init finished in 81 msecs
9333 22:13:03.154458 Devices initialized
9334 22:13:03.157761 Show all devs... After init.
9335 22:13:03.158169 Root Device: enabled 1
9336 22:13:03.160896 CPU_CLUSTER: 0: enabled 1
9337 22:13:03.164010 CPU: 00: enabled 1
9338 22:13:03.167398 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9339 22:13:03.170694 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9340 22:13:03.173587 ELOG: NV offset 0x57f000 size 0x1000
9341 22:13:03.180814 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9342 22:13:03.187278 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9343 22:13:03.190521 ELOG: Event(17) added with size 13 at 2023-06-04 22:13:15 UTC
9344 22:13:03.197194 out: cmd=0x121: 03 db 21 01 00 00 00 00
9345 22:13:03.200113 in-header: 03 2b 00 00 2c 00 00 00
9346 22:13:03.210269 in-data: 34 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9347 22:13:03.217261 ELOG: Event(A1) added with size 10 at 2023-06-04 22:13:15 UTC
9348 22:13:03.223450 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9349 22:13:03.230058 ELOG: Event(A0) added with size 9 at 2023-06-04 22:13:15 UTC
9350 22:13:03.233750 elog_add_boot_reason: Logged dev mode boot
9351 22:13:03.240331 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9352 22:13:03.240743 Finalize devices...
9353 22:13:03.243204 Devices finalized
9354 22:13:03.246882 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9355 22:13:03.249684 Writing coreboot table at 0xffe64000
9356 22:13:03.253448 0. 000000000010a000-0000000000113fff: RAMSTAGE
9357 22:13:03.259745 1. 0000000040000000-00000000400fffff: RAM
9358 22:13:03.263116 2. 0000000040100000-000000004032afff: RAMSTAGE
9359 22:13:03.266468 3. 000000004032b000-00000000545fffff: RAM
9360 22:13:03.269541 4. 0000000054600000-000000005465ffff: BL31
9361 22:13:03.272829 5. 0000000054660000-00000000ffe63fff: RAM
9362 22:13:03.279304 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9363 22:13:03.282746 7. 0000000100000000-000000023fffffff: RAM
9364 22:13:03.285759 Passing 5 GPIOs to payload:
9365 22:13:03.289454 NAME | PORT | POLARITY | VALUE
9366 22:13:03.296320 EC in RW | 0x000000aa | low | undefined
9367 22:13:03.298975 EC interrupt | 0x00000005 | low | undefined
9368 22:13:03.305874 TPM interrupt | 0x000000ab | high | undefined
9369 22:13:03.309555 SD card detect | 0x00000011 | high | undefined
9370 22:13:03.312292 speaker enable | 0x00000093 | high | undefined
9371 22:13:03.315586 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9372 22:13:03.319434 in-header: 03 f9 00 00 02 00 00 00
9373 22:13:03.322666 in-data: 02 00
9374 22:13:03.326222 ADC[4]: Raw value=902955 ID=7
9375 22:13:03.329204 ADC[3]: Raw value=213546 ID=1
9376 22:13:03.329609 RAM Code: 0x71
9377 22:13:03.332423 ADC[6]: Raw value=75000 ID=0
9378 22:13:03.336050 ADC[5]: Raw value=213546 ID=1
9379 22:13:03.336467 SKU Code: 0x1
9380 22:13:03.342651 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a51a
9381 22:13:03.343072 coreboot table: 964 bytes.
9382 22:13:03.345734 IMD ROOT 0. 0xfffff000 0x00001000
9383 22:13:03.349838 IMD SMALL 1. 0xffffe000 0x00001000
9384 22:13:03.352563 RO MCACHE 2. 0xffffc000 0x00001104
9385 22:13:03.355777 CONSOLE 3. 0xfff7c000 0x00080000
9386 22:13:03.358674 FMAP 4. 0xfff7b000 0x00000452
9387 22:13:03.362148 TIME STAMP 5. 0xfff7a000 0x00000910
9388 22:13:03.365585 VBOOT WORK 6. 0xfff66000 0x00014000
9389 22:13:03.368738 RAMOOPS 7. 0xffe66000 0x00100000
9390 22:13:03.372203 COREBOOT 8. 0xffe64000 0x00002000
9391 22:13:03.375850 IMD small region:
9392 22:13:03.378858 IMD ROOT 0. 0xffffec00 0x00000400
9393 22:13:03.382478 VPD 1. 0xffffeba0 0x0000004c
9394 22:13:03.385097 MMC STATUS 2. 0xffffeb80 0x00000004
9395 22:13:03.392249 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9396 22:13:03.392756 Probing TPM: done!
9397 22:13:03.399238 Connected to device vid:did:rid of 1ae0:0028:00
9398 22:13:03.405816 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9399 22:13:03.408724 Initialized TPM device CR50 revision 0
9400 22:13:03.412300 Checking cr50 for pending updates
9401 22:13:03.417596 Reading cr50 TPM mode
9402 22:13:03.426278 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9403 22:13:03.432924 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9404 22:13:03.472928 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9405 22:13:03.476071 Checking segment from ROM address 0x40100000
9406 22:13:03.479705 Checking segment from ROM address 0x4010001c
9407 22:13:03.486772 Loading segment from ROM address 0x40100000
9408 22:13:03.487337 code (compression=0)
9409 22:13:03.496499 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9410 22:13:03.502656 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9411 22:13:03.503124 it's not compressed!
9412 22:13:03.509763 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9413 22:13:03.515956 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9414 22:13:03.533400 Loading segment from ROM address 0x4010001c
9415 22:13:03.533864 Entry Point 0x80000000
9416 22:13:03.536993 Loaded segments
9417 22:13:03.540191 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9418 22:13:03.546949 Jumping to boot code at 0x80000000(0xffe64000)
9419 22:13:03.553465 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9420 22:13:03.559981 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9421 22:13:03.567961 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9422 22:13:03.571268 Checking segment from ROM address 0x40100000
9423 22:13:03.574852 Checking segment from ROM address 0x4010001c
9424 22:13:03.581136 Loading segment from ROM address 0x40100000
9425 22:13:03.581671 code (compression=1)
9426 22:13:03.587322 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9427 22:13:03.597773 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9428 22:13:03.598279 using LZMA
9429 22:13:03.606946 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9430 22:13:03.613465 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9431 22:13:03.616022 Loading segment from ROM address 0x4010001c
9432 22:13:03.616440 Entry Point 0x54601000
9433 22:13:03.619351 Loaded segments
9434 22:13:03.622740 NOTICE: MT8192 bl31_setup
9435 22:13:03.629684 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9436 22:13:03.632981 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9437 22:13:03.636272 WARNING: region 0:
9438 22:13:03.639538 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9439 22:13:03.639964 WARNING: region 1:
9440 22:13:03.646265 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9441 22:13:03.650020 WARNING: region 2:
9442 22:13:03.652939 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9443 22:13:03.656735 WARNING: region 3:
9444 22:13:03.659627 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9445 22:13:03.662860 WARNING: region 4:
9446 22:13:03.669774 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9447 22:13:03.670295 WARNING: region 5:
9448 22:13:03.672833 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9449 22:13:03.675999 WARNING: region 6:
9450 22:13:03.679597 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9451 22:13:03.682832 WARNING: region 7:
9452 22:13:03.686117 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9453 22:13:03.692577 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9454 22:13:03.696542 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9455 22:13:03.700006 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9456 22:13:03.706075 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9457 22:13:03.709282 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9458 22:13:03.715791 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9459 22:13:03.719762 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9460 22:13:03.722502 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9461 22:13:03.729082 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9462 22:13:03.732222 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9463 22:13:03.739243 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9464 22:13:03.742171 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9465 22:13:03.745684 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9466 22:13:03.752257 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9467 22:13:03.755314 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9468 22:13:03.758858 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9469 22:13:03.765413 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9470 22:13:03.768995 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9471 22:13:03.775268 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9472 22:13:03.779248 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9473 22:13:03.782177 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9474 22:13:03.788866 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9475 22:13:03.792169 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9476 22:13:03.798763 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9477 22:13:03.802105 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9478 22:13:03.805311 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9479 22:13:03.812032 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9480 22:13:03.815500 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9481 22:13:03.821697 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9482 22:13:03.825313 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9483 22:13:03.828748 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9484 22:13:03.835114 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9485 22:13:03.838435 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9486 22:13:03.841701 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9487 22:13:03.844808 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9488 22:13:03.851737 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9489 22:13:03.854938 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9490 22:13:03.858121 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9491 22:13:03.861653 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9492 22:13:03.868292 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9493 22:13:03.871317 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9494 22:13:03.874806 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9495 22:13:03.878204 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9496 22:13:03.885347 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9497 22:13:03.888259 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9498 22:13:03.891486 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9499 22:13:03.898750 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9500 22:13:03.901751 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9501 22:13:03.904750 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9502 22:13:03.912290 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9503 22:13:03.914870 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9504 22:13:03.921337 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9505 22:13:03.924542 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9506 22:13:03.927921 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9507 22:13:03.934746 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9508 22:13:03.937745 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9509 22:13:03.944347 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9510 22:13:03.947753 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9511 22:13:03.954345 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9512 22:13:03.958100 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9513 22:13:03.961359 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9514 22:13:03.968105 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9515 22:13:03.971861 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9516 22:13:03.977724 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9517 22:13:03.981605 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9518 22:13:03.988576 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9519 22:13:03.991317 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9520 22:13:03.997670 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9521 22:13:04.001031 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9522 22:13:04.004184 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9523 22:13:04.010911 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9524 22:13:04.014055 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9525 22:13:04.021954 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9526 22:13:04.023756 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9527 22:13:04.030706 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9528 22:13:04.034030 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9529 22:13:04.040426 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9530 22:13:04.044061 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9531 22:13:04.047058 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9532 22:13:04.054116 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9533 22:13:04.057140 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9534 22:13:04.063861 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9535 22:13:04.067364 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9536 22:13:04.074424 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9537 22:13:04.077300 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9538 22:13:04.080648 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9539 22:13:04.087226 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9540 22:13:04.090320 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9541 22:13:04.097103 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9542 22:13:04.100291 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9543 22:13:04.107259 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9544 22:13:04.110790 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9545 22:13:04.117167 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9546 22:13:04.120225 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9547 22:13:04.123804 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9548 22:13:04.131001 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9549 22:13:04.134360 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9550 22:13:04.137163 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9551 22:13:04.144012 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9552 22:13:04.146911 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9553 22:13:04.150782 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9554 22:13:04.153605 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9555 22:13:04.160809 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9556 22:13:04.163905 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9557 22:13:04.170248 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9558 22:13:04.173922 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9559 22:13:04.176841 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9560 22:13:04.183726 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9561 22:13:04.186999 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9562 22:13:04.193982 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9563 22:13:04.197246 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9564 22:13:04.200416 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9565 22:13:04.206589 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9566 22:13:04.210028 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9567 22:13:04.217144 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9568 22:13:04.219993 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9569 22:13:04.223565 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9570 22:13:04.230064 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9571 22:13:04.233912 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9572 22:13:04.236977 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9573 22:13:04.240453 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9574 22:13:04.247427 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9575 22:13:04.250168 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9576 22:13:04.253592 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9577 22:13:04.259934 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9578 22:13:04.263622 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9579 22:13:04.267041 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9580 22:13:04.273249 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9581 22:13:04.276871 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9582 22:13:04.283122 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9583 22:13:04.287468 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9584 22:13:04.290063 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9585 22:13:04.296837 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9586 22:13:04.300499 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9587 22:13:04.303278 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9588 22:13:04.309995 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9589 22:13:04.313861 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9590 22:13:04.319891 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9591 22:13:04.323241 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9592 22:13:04.327342 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9593 22:13:04.333352 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9594 22:13:04.336677 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9595 22:13:04.343450 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9596 22:13:04.346732 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9597 22:13:04.349783 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9598 22:13:04.356758 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9599 22:13:04.359920 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9600 22:13:04.366178 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9601 22:13:04.369771 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9602 22:13:04.373000 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9603 22:13:04.379927 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9604 22:13:04.383526 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9605 22:13:04.386322 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9606 22:13:04.393002 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9607 22:13:04.396280 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9608 22:13:04.402732 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9609 22:13:04.406856 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9610 22:13:04.413258 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9611 22:13:04.416040 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9612 22:13:04.419758 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9613 22:13:04.425963 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9614 22:13:04.429205 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9615 22:13:04.433055 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9616 22:13:04.439060 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9617 22:13:04.442637 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9618 22:13:04.448860 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9619 22:13:04.452283 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9620 22:13:04.455569 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9621 22:13:04.462122 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9622 22:13:04.465584 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9623 22:13:04.471878 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9624 22:13:04.476249 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9625 22:13:04.478792 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9626 22:13:04.485551 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9627 22:13:04.488714 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9628 22:13:04.495837 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9629 22:13:04.498495 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9630 22:13:04.501973 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9631 22:13:04.508490 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9632 22:13:04.512340 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9633 22:13:04.518188 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9634 22:13:04.521704 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9635 22:13:04.524935 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9636 22:13:04.531530 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9637 22:13:04.535500 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9638 22:13:04.541903 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9639 22:13:04.544872 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9640 22:13:04.548155 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9641 22:13:04.554831 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9642 22:13:04.558445 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9643 22:13:04.564494 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9644 22:13:04.568084 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9645 22:13:04.574487 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9646 22:13:04.577786 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9647 22:13:04.581222 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9648 22:13:04.587797 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9649 22:13:04.591067 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9650 22:13:04.598240 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9651 22:13:04.601006 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9652 22:13:04.607556 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9653 22:13:04.610970 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9654 22:13:04.614059 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9655 22:13:04.621180 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9656 22:13:04.623985 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9657 22:13:04.630799 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9658 22:13:04.634469 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9659 22:13:04.640767 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9660 22:13:04.643687 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9661 22:13:04.647358 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9662 22:13:04.653557 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9663 22:13:04.656969 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9664 22:13:04.663828 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9665 22:13:04.667758 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9666 22:13:04.674076 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9667 22:13:04.676617 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9668 22:13:04.680281 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9669 22:13:04.686892 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9670 22:13:04.689733 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9671 22:13:04.696578 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9672 22:13:04.699667 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9673 22:13:04.706638 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9674 22:13:04.709827 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9675 22:13:04.713365 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9676 22:13:04.720088 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9677 22:13:04.722744 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9678 22:13:04.729399 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9679 22:13:04.733030 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9680 22:13:04.739563 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9681 22:13:04.742698 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9682 22:13:04.746592 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9683 22:13:04.749451 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9684 22:13:04.755991 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9685 22:13:04.759312 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9686 22:13:04.762247 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9687 22:13:04.765905 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9688 22:13:04.772478 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9689 22:13:04.775795 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9690 22:13:04.782634 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9691 22:13:04.785662 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9692 22:13:04.789595 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9693 22:13:04.795666 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9694 22:13:04.798823 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9695 22:13:04.802432 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9696 22:13:04.808931 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9697 22:13:04.812075 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9698 22:13:04.818632 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9699 22:13:04.822125 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9700 22:13:04.825172 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9701 22:13:04.832039 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9702 22:13:04.835426 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9703 22:13:04.838272 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9704 22:13:04.845311 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9705 22:13:04.848511 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9706 22:13:04.851776 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9707 22:13:04.858682 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9708 22:13:04.861740 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9709 22:13:04.868531 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9710 22:13:04.871701 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9711 22:13:04.875248 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9712 22:13:04.882023 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9713 22:13:04.885224 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9714 22:13:04.888033 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9715 22:13:04.894909 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9716 22:13:04.897948 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9717 22:13:04.904714 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9718 22:13:04.907872 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9719 22:13:04.911693 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9720 22:13:04.917829 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9721 22:13:04.921135 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9722 22:13:04.924560 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9723 22:13:04.927849 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9724 22:13:04.934135 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9725 22:13:04.937993 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9726 22:13:04.941555 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9727 22:13:04.944501 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9728 22:13:04.950753 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9729 22:13:04.953872 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9730 22:13:04.957422 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9731 22:13:04.960849 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9732 22:13:04.967063 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9733 22:13:04.971003 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9734 22:13:04.973696 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9735 22:13:04.980338 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9736 22:13:04.984375 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9737 22:13:04.990242 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9738 22:13:04.993627 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9739 22:13:04.997523 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9740 22:13:05.004021 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9741 22:13:05.007009 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9742 22:13:05.014308 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9743 22:13:05.017059 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9744 22:13:05.020385 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9745 22:13:05.026745 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9746 22:13:05.030359 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9747 22:13:05.037695 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9748 22:13:05.040231 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9749 22:13:05.046917 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9750 22:13:05.049678 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9751 22:13:05.053620 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9752 22:13:05.059844 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9753 22:13:05.062984 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9754 22:13:05.069731 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9755 22:13:05.072720 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9756 22:13:05.079405 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9757 22:13:05.083093 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9758 22:13:05.086266 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9759 22:13:05.092712 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9760 22:13:05.095834 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9761 22:13:05.102830 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9762 22:13:05.105757 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9763 22:13:05.112320 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9764 22:13:05.115589 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9765 22:13:05.119295 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9766 22:13:05.125716 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9767 22:13:05.129298 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9768 22:13:05.135611 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9769 22:13:05.139677 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9770 22:13:05.142805 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9771 22:13:05.148581 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9772 22:13:05.152050 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9773 22:13:05.158895 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9774 22:13:05.161914 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9775 22:13:05.165593 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9776 22:13:05.172125 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9777 22:13:05.175514 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9778 22:13:05.181835 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9779 22:13:05.184989 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9780 22:13:05.191659 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9781 22:13:05.195005 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9782 22:13:05.198322 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9783 22:13:05.204852 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9784 22:13:05.208188 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9785 22:13:05.214810 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9786 22:13:05.218235 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9787 22:13:05.225171 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9788 22:13:05.228024 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9789 22:13:05.231489 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9790 22:13:05.238091 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9791 22:13:05.241322 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9792 22:13:05.247523 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9793 22:13:05.250953 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9794 22:13:05.254308 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9795 22:13:05.261150 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9796 22:13:05.265299 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9797 22:13:05.270808 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9798 22:13:05.274233 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9799 22:13:05.277386 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9800 22:13:05.284229 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9801 22:13:05.287421 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9802 22:13:05.293882 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9803 22:13:05.297484 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9804 22:13:05.303792 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9805 22:13:05.307152 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9806 22:13:05.310007 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9807 22:13:05.316810 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9808 22:13:05.320850 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9809 22:13:05.326840 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9810 22:13:05.330033 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9811 22:13:05.336834 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9812 22:13:05.339741 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9813 22:13:05.346370 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9814 22:13:05.349668 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9815 22:13:05.352895 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9816 22:13:05.359344 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9817 22:13:05.362785 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9818 22:13:05.369381 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9819 22:13:05.373441 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9820 22:13:05.379237 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9821 22:13:05.382397 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9822 22:13:05.386188 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9823 22:13:05.392812 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9824 22:13:05.395853 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9825 22:13:05.402305 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9826 22:13:05.405779 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9827 22:13:05.412668 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9828 22:13:05.416123 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9829 22:13:05.422125 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9830 22:13:05.425598 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9831 22:13:05.429223 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9832 22:13:05.435651 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9833 22:13:05.438678 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9834 22:13:05.444931 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9835 22:13:05.448248 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9836 22:13:05.454940 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9837 22:13:05.458621 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9838 22:13:05.464977 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9839 22:13:05.468109 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9840 22:13:05.475308 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9841 22:13:05.479093 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9842 22:13:05.481485 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9843 22:13:05.488132 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9844 22:13:05.491519 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9845 22:13:05.498295 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9846 22:13:05.501267 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9847 22:13:05.507889 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9848 22:13:05.511369 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9849 22:13:05.518369 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9850 22:13:05.521645 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9851 22:13:05.524618 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9852 22:13:05.531168 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9853 22:13:05.534296 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9854 22:13:05.541115 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9855 22:13:05.544401 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9856 22:13:05.547812 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9857 22:13:05.554191 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9858 22:13:05.557510 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9859 22:13:05.564147 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9860 22:13:05.567462 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9861 22:13:05.573850 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9862 22:13:05.577303 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9863 22:13:05.584542 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9864 22:13:05.587214 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9865 22:13:05.593811 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9866 22:13:05.597169 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9867 22:13:05.603935 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9868 22:13:05.606944 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9869 22:13:05.613673 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9870 22:13:05.617110 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9871 22:13:05.623676 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9872 22:13:05.626882 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9873 22:13:05.633859 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9874 22:13:05.636797 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9875 22:13:05.643647 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9876 22:13:05.646803 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9877 22:13:05.653334 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9878 22:13:05.656575 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9879 22:13:05.663126 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9880 22:13:05.666467 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9881 22:13:05.672841 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9882 22:13:05.676550 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9883 22:13:05.682714 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9884 22:13:05.686296 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9885 22:13:05.692826 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9886 22:13:05.696121 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9887 22:13:05.702874 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9888 22:13:05.703326 INFO: [APUAPC] vio 0
9889 22:13:05.709657 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9890 22:13:05.712975 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9891 22:13:05.716182 INFO: [APUAPC] D0_APC_0: 0x400510
9892 22:13:05.719649 INFO: [APUAPC] D0_APC_1: 0x0
9893 22:13:05.723092 INFO: [APUAPC] D0_APC_2: 0x1540
9894 22:13:05.725859 INFO: [APUAPC] D0_APC_3: 0x0
9895 22:13:05.729673 INFO: [APUAPC] D1_APC_0: 0xffffffff
9896 22:13:05.732561 INFO: [APUAPC] D1_APC_1: 0xffffffff
9897 22:13:05.736008 INFO: [APUAPC] D1_APC_2: 0x3fffff
9898 22:13:05.739218 INFO: [APUAPC] D1_APC_3: 0x0
9899 22:13:05.742387 INFO: [APUAPC] D2_APC_0: 0xffffffff
9900 22:13:05.745814 INFO: [APUAPC] D2_APC_1: 0xffffffff
9901 22:13:05.749147 INFO: [APUAPC] D2_APC_2: 0x3fffff
9902 22:13:05.753048 INFO: [APUAPC] D2_APC_3: 0x0
9903 22:13:05.756053 INFO: [APUAPC] D3_APC_0: 0xffffffff
9904 22:13:05.759282 INFO: [APUAPC] D3_APC_1: 0xffffffff
9905 22:13:05.762579 INFO: [APUAPC] D3_APC_2: 0x3fffff
9906 22:13:05.765454 INFO: [APUAPC] D3_APC_3: 0x0
9907 22:13:05.768979 INFO: [APUAPC] D4_APC_0: 0xffffffff
9908 22:13:05.772118 INFO: [APUAPC] D4_APC_1: 0xffffffff
9909 22:13:05.775693 INFO: [APUAPC] D4_APC_2: 0x3fffff
9910 22:13:05.778593 INFO: [APUAPC] D4_APC_3: 0x0
9911 22:13:05.782432 INFO: [APUAPC] D5_APC_0: 0xffffffff
9912 22:13:05.785713 INFO: [APUAPC] D5_APC_1: 0xffffffff
9913 22:13:05.788736 INFO: [APUAPC] D5_APC_2: 0x3fffff
9914 22:13:05.791922 INFO: [APUAPC] D5_APC_3: 0x0
9915 22:13:05.795271 INFO: [APUAPC] D6_APC_0: 0xffffffff
9916 22:13:05.798495 INFO: [APUAPC] D6_APC_1: 0xffffffff
9917 22:13:05.801862 INFO: [APUAPC] D6_APC_2: 0x3fffff
9918 22:13:05.805079 INFO: [APUAPC] D6_APC_3: 0x0
9919 22:13:05.808352 INFO: [APUAPC] D7_APC_0: 0xffffffff
9920 22:13:05.811856 INFO: [APUAPC] D7_APC_1: 0xffffffff
9921 22:13:05.815375 INFO: [APUAPC] D7_APC_2: 0x3fffff
9922 22:13:05.815786 INFO: [APUAPC] D7_APC_3: 0x0
9923 22:13:05.821474 INFO: [APUAPC] D8_APC_0: 0xffffffff
9924 22:13:05.825138 INFO: [APUAPC] D8_APC_1: 0xffffffff
9925 22:13:05.828297 INFO: [APUAPC] D8_APC_2: 0x3fffff
9926 22:13:05.828738 INFO: [APUAPC] D8_APC_3: 0x0
9927 22:13:05.831364 INFO: [APUAPC] D9_APC_0: 0xffffffff
9928 22:13:05.837762 INFO: [APUAPC] D9_APC_1: 0xffffffff
9929 22:13:05.841565 INFO: [APUAPC] D9_APC_2: 0x3fffff
9930 22:13:05.842000 INFO: [APUAPC] D9_APC_3: 0x0
9931 22:13:05.844814 INFO: [APUAPC] D10_APC_0: 0xffffffff
9932 22:13:05.851228 INFO: [APUAPC] D10_APC_1: 0xffffffff
9933 22:13:05.854802 INFO: [APUAPC] D10_APC_2: 0x3fffff
9934 22:13:05.855261 INFO: [APUAPC] D10_APC_3: 0x0
9935 22:13:05.857908 INFO: [APUAPC] D11_APC_0: 0xffffffff
9936 22:13:05.864404 INFO: [APUAPC] D11_APC_1: 0xffffffff
9937 22:13:05.867657 INFO: [APUAPC] D11_APC_2: 0x3fffff
9938 22:13:05.868096 INFO: [APUAPC] D11_APC_3: 0x0
9939 22:13:05.874514 INFO: [APUAPC] D12_APC_0: 0xffffffff
9940 22:13:05.877602 INFO: [APUAPC] D12_APC_1: 0xffffffff
9941 22:13:05.881610 INFO: [APUAPC] D12_APC_2: 0x3fffff
9942 22:13:05.882070 INFO: [APUAPC] D12_APC_3: 0x0
9943 22:13:05.887678 INFO: [APUAPC] D13_APC_0: 0xffffffff
9944 22:13:05.890944 INFO: [APUAPC] D13_APC_1: 0xffffffff
9945 22:13:05.894339 INFO: [APUAPC] D13_APC_2: 0x3fffff
9946 22:13:05.897338 INFO: [APUAPC] D13_APC_3: 0x0
9947 22:13:05.901008 INFO: [APUAPC] D14_APC_0: 0xffffffff
9948 22:13:05.904446 INFO: [APUAPC] D14_APC_1: 0xffffffff
9949 22:13:05.907925 INFO: [APUAPC] D14_APC_2: 0x3fffff
9950 22:13:05.910438 INFO: [APUAPC] D14_APC_3: 0x0
9951 22:13:05.913957 INFO: [APUAPC] D15_APC_0: 0xffffffff
9952 22:13:05.917559 INFO: [APUAPC] D15_APC_1: 0xffffffff
9953 22:13:05.920531 INFO: [APUAPC] D15_APC_2: 0x3fffff
9954 22:13:05.923943 INFO: [APUAPC] D15_APC_3: 0x0
9955 22:13:05.924409 INFO: [APUAPC] APC_CON: 0x4
9956 22:13:05.927098 INFO: [NOCDAPC] D0_APC_0: 0x0
9957 22:13:05.930946 INFO: [NOCDAPC] D0_APC_1: 0x0
9958 22:13:05.933915 INFO: [NOCDAPC] D1_APC_0: 0x0
9959 22:13:05.937049 INFO: [NOCDAPC] D1_APC_1: 0xfff
9960 22:13:05.940789 INFO: [NOCDAPC] D2_APC_0: 0x0
9961 22:13:05.943733 INFO: [NOCDAPC] D2_APC_1: 0xfff
9962 22:13:05.946863 INFO: [NOCDAPC] D3_APC_0: 0x0
9963 22:13:05.950195 INFO: [NOCDAPC] D3_APC_1: 0xfff
9964 22:13:05.953713 INFO: [NOCDAPC] D4_APC_0: 0x0
9965 22:13:05.957632 INFO: [NOCDAPC] D4_APC_1: 0xfff
9966 22:13:05.958051 INFO: [NOCDAPC] D5_APC_0: 0x0
9967 22:13:05.960516 INFO: [NOCDAPC] D5_APC_1: 0xfff
9968 22:13:05.963869 INFO: [NOCDAPC] D6_APC_0: 0x0
9969 22:13:05.966928 INFO: [NOCDAPC] D6_APC_1: 0xfff
9970 22:13:05.970635 INFO: [NOCDAPC] D7_APC_0: 0x0
9971 22:13:05.973501 INFO: [NOCDAPC] D7_APC_1: 0xfff
9972 22:13:05.976900 INFO: [NOCDAPC] D8_APC_0: 0x0
9973 22:13:05.980150 INFO: [NOCDAPC] D8_APC_1: 0xfff
9974 22:13:05.983124 INFO: [NOCDAPC] D9_APC_0: 0x0
9975 22:13:05.986675 INFO: [NOCDAPC] D9_APC_1: 0xfff
9976 22:13:05.989861 INFO: [NOCDAPC] D10_APC_0: 0x0
9977 22:13:05.993583 INFO: [NOCDAPC] D10_APC_1: 0xfff
9978 22:13:05.994002 INFO: [NOCDAPC] D11_APC_0: 0x0
9979 22:13:05.996836 INFO: [NOCDAPC] D11_APC_1: 0xfff
9980 22:13:05.999825 INFO: [NOCDAPC] D12_APC_0: 0x0
9981 22:13:06.003085 INFO: [NOCDAPC] D12_APC_1: 0xfff
9982 22:13:06.006431 INFO: [NOCDAPC] D13_APC_0: 0x0
9983 22:13:06.009878 INFO: [NOCDAPC] D13_APC_1: 0xfff
9984 22:13:06.012784 INFO: [NOCDAPC] D14_APC_0: 0x0
9985 22:13:06.016358 INFO: [NOCDAPC] D14_APC_1: 0xfff
9986 22:13:06.019405 INFO: [NOCDAPC] D15_APC_0: 0x0
9987 22:13:06.022598 INFO: [NOCDAPC] D15_APC_1: 0xfff
9988 22:13:06.026265 INFO: [NOCDAPC] APC_CON: 0x4
9989 22:13:06.029414 INFO: [APUAPC] set_apusys_apc done
9990 22:13:06.032684 INFO: [DEVAPC] devapc_init done
9991 22:13:06.035904 INFO: GICv3 without legacy support detected.
9992 22:13:06.039343 INFO: ARM GICv3 driver initialized in EL3
9993 22:13:06.042622 INFO: Maximum SPI INTID supported: 639
9994 22:13:06.049015 INFO: BL31: Initializing runtime services
9995 22:13:06.052625 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9996 22:13:06.056335 INFO: SPM: enable CPC mode
9997 22:13:06.062303 INFO: mcdi ready for mcusys-off-idle and system suspend
9998 22:13:06.066065 INFO: BL31: Preparing for EL3 exit to normal world
9999 22:13:06.069106 INFO: Entry point address = 0x80000000
10000 22:13:06.072572 INFO: SPSR = 0x8
10001 22:13:06.078473
10002 22:13:06.078883
10003 22:13:06.079254
10004 22:13:06.081484 Starting depthcharge on Spherion...
10005 22:13:06.081898
10006 22:13:06.082223 Wipe memory regions:
10007 22:13:06.082526
10008 22:13:06.084809 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10009 22:13:06.085309 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10010 22:13:06.085754 Setting prompt string to ['asurada:']
10011 22:13:06.086135 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10012 22:13:06.086775 [0x00000040000000, 0x00000054600000)
10013 22:13:06.206454
10014 22:13:06.206985 [0x00000054660000, 0x00000080000000)
10015 22:13:06.467058
10016 22:13:06.467585 [0x000000821a7280, 0x000000ffe64000)
10017 22:13:07.211593
10018 22:13:07.212116 [0x00000100000000, 0x00000240000000)
10019 22:13:09.101146
10020 22:13:09.104430 Initializing XHCI USB controller at 0x11200000.
10021 22:13:10.141741
10022 22:13:10.145279 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10023 22:13:10.145373
10024 22:13:10.145439
10025 22:13:10.145499
10026 22:13:10.145780 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10028 22:13:10.246125 asurada: tftpboot 192.168.201.1 10583893/tftp-deploy-arhndd4y/kernel/image.itb 10583893/tftp-deploy-arhndd4y/kernel/cmdline
10029 22:13:10.246319 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10030 22:13:10.246427 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10031 22:13:10.250679 tftpboot 192.168.201.1 10583893/tftp-deploy-arhndd4y/kernel/image.ittp-deploy-arhndd4y/kernel/cmdline
10032 22:13:10.250767
10033 22:13:10.250831 Waiting for link
10034 22:13:10.411316
10035 22:13:10.411471 R8152: Initializing
10036 22:13:10.411539
10037 22:13:10.414279 Version 6 (ocp_data = 5c30)
10038 22:13:10.414361
10039 22:13:10.417789 R8152: Done initializing
10040 22:13:10.417871
10041 22:13:10.417936 Adding net device
10042 22:13:12.462089
10043 22:13:12.462241 done.
10044 22:13:12.462310
10045 22:13:12.462370 MAC: 00:24:32:30:7c:7b
10046 22:13:12.462429
10047 22:13:12.465274 Sending DHCP discover... done.
10048 22:13:12.465360
10049 22:13:12.469015 Waiting for reply... done.
10050 22:13:12.469104
10051 22:13:12.471790 Sending DHCP request... done.
10052 22:13:12.471875
10053 22:13:12.477205 Waiting for reply... done.
10054 22:13:12.477290
10055 22:13:12.477355 My ip is 192.168.201.14
10056 22:13:12.477415
10057 22:13:12.480244 The DHCP server ip is 192.168.201.1
10058 22:13:12.480327
10059 22:13:12.486872 TFTP server IP predefined by user: 192.168.201.1
10060 22:13:12.486956
10061 22:13:12.493421 Bootfile predefined by user: 10583893/tftp-deploy-arhndd4y/kernel/image.itb
10062 22:13:12.493504
10063 22:13:12.496488 Sending tftp read request... done.
10064 22:13:12.496571
10065 22:13:12.500402 Waiting for the transfer...
10066 22:13:12.500485
10067 22:13:13.073308 00000000 ################################################################
10068 22:13:13.073489
10069 22:13:13.647904 00080000 ################################################################
10070 22:13:13.648075
10071 22:13:14.212897 00100000 ################################################################
10072 22:13:14.213063
10073 22:13:14.775282 00180000 ################################################################
10074 22:13:14.775451
10075 22:13:15.342380 00200000 ################################################################
10076 22:13:15.342519
10077 22:13:15.916272 00280000 ################################################################
10078 22:13:15.916420
10079 22:13:16.492350 00300000 ################################################################
10080 22:13:16.492499
10081 22:13:17.062163 00380000 ################################################################
10082 22:13:17.062319
10083 22:13:17.631281 00400000 ################################################################
10084 22:13:17.631433
10085 22:13:18.208985 00480000 ################################################################
10086 22:13:18.209135
10087 22:13:18.778764 00500000 ################################################################
10088 22:13:18.778920
10089 22:13:19.349531 00580000 ################################################################
10090 22:13:19.349686
10091 22:13:19.921654 00600000 ################################################################
10092 22:13:19.921805
10093 22:13:20.495008 00680000 ################################################################
10094 22:13:20.495191
10095 22:13:21.066488 00700000 ################################################################
10096 22:13:21.066648
10097 22:13:21.642102 00780000 ################################################################
10098 22:13:21.642258
10099 22:13:22.207907 00800000 ################################################################
10100 22:13:22.208085
10101 22:13:22.780481 00880000 ################################################################
10102 22:13:22.780632
10103 22:13:23.352207 00900000 ################################################################
10104 22:13:23.352359
10105 22:13:23.912938 00980000 ################################################################
10106 22:13:23.913117
10107 22:13:24.484912 00a00000 ################################################################
10108 22:13:24.485064
10109 22:13:25.056495 00a80000 ################################################################
10110 22:13:25.056648
10111 22:13:25.642111 00b00000 ################################################################
10112 22:13:25.642259
10113 22:13:26.211092 00b80000 ################################################################
10114 22:13:26.211295
10115 22:13:26.773967 00c00000 ################################################################
10116 22:13:26.774130
10117 22:13:27.324688 00c80000 ################################################################
10118 22:13:27.324835
10119 22:13:27.872296 00d00000 ################################################################
10120 22:13:27.872448
10121 22:13:28.426473 00d80000 ################################################################
10122 22:13:28.426621
10123 22:13:28.965817 00e00000 ################################################################
10124 22:13:28.965969
10125 22:13:29.499631 00e80000 ################################################################
10126 22:13:29.499784
10127 22:13:30.042906 00f00000 ################################################################
10128 22:13:30.043043
10129 22:13:30.624070 00f80000 ################################################################
10130 22:13:30.624216
10131 22:13:31.234872 01000000 ################################################################
10132 22:13:31.235386
10133 22:13:31.927014 01080000 ################################################################
10134 22:13:31.927558
10135 22:13:32.600719 01100000 ################################################################
10136 22:13:32.601231
10137 22:13:33.272285 01180000 ################################################################
10138 22:13:33.272430
10139 22:13:33.895203 01200000 ################################################################
10140 22:13:33.895592
10141 22:13:34.603069 01280000 ################################################################
10142 22:13:34.603650
10143 22:13:35.282313 01300000 ################################################################
10144 22:13:35.282809
10145 22:13:35.963615 01380000 ################################################################
10146 22:13:35.964162
10147 22:13:36.609062 01400000 ################################################################
10148 22:13:36.609194
10149 22:13:37.175110 01480000 ################################################################
10150 22:13:37.175304
10151 22:13:37.746907 01500000 ################################################################
10152 22:13:37.747089
10153 22:13:38.288444 01580000 ################################################################
10154 22:13:38.288581
10155 22:13:38.930727 01600000 ################################################################
10156 22:13:38.931272
10157 22:13:39.569790 01680000 ################################################################
10158 22:13:39.569929
10159 22:13:40.169740 01700000 ################################################################
10160 22:13:40.169880
10161 22:13:40.750138 01780000 ################################################################
10162 22:13:40.750275
10163 22:13:41.277590 01800000 ################################################################
10164 22:13:41.277743
10165 22:13:41.810211 01880000 ################################################################
10166 22:13:41.810351
10167 22:13:42.341091 01900000 ################################################################
10168 22:13:42.341252
10169 22:13:42.872577 01980000 ################################################################
10170 22:13:42.872710
10171 22:13:43.402732 01a00000 ################################################################
10172 22:13:43.402889
10173 22:13:43.935237 01a80000 ################################################################
10174 22:13:43.935393
10175 22:13:44.465574 01b00000 ################################################################
10176 22:13:44.465730
10177 22:13:45.017262 01b80000 ################################################################
10178 22:13:45.017431
10179 22:13:45.558160 01c00000 ################################################################
10180 22:13:45.558323
10181 22:13:46.090749 01c80000 ################################################################
10182 22:13:46.090884
10183 22:13:46.620462 01d00000 ################################################################
10184 22:13:46.620592
10185 22:13:47.050294 01d80000 ##################################################### done.
10186 22:13:47.050430
10187 22:13:47.053793 The bootfile was 31360918 bytes long.
10188 22:13:47.053867
10189 22:13:47.057423 Sending tftp read request... done.
10190 22:13:47.057506
10191 22:13:47.060672 Waiting for the transfer...
10192 22:13:47.060766
10193 22:13:47.060832 00000000 # done.
10194 22:13:47.060917
10195 22:13:47.070414 Command line loaded dynamically from TFTP file: 10583893/tftp-deploy-arhndd4y/kernel/cmdline
10196 22:13:47.070506
10197 22:13:47.080524 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10198 22:13:47.080610
10199 22:13:47.083763 Loading FIT.
10200 22:13:47.083843
10201 22:13:47.087015 Image ramdisk-1 has 21230232 bytes.
10202 22:13:47.087095
10203 22:13:47.087158 Image fdt-1 has 46924 bytes.
10204 22:13:47.087254
10205 22:13:47.090497 Image kernel-1 has 10081729 bytes.
10206 22:13:47.090578
10207 22:13:47.100413 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10208 22:13:47.100500
10209 22:13:47.116470 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10210 22:13:47.116579
10211 22:13:47.123464 Choosing best match conf-1 for compat google,spherion-rev2.
10212 22:13:47.127341
10213 22:13:47.131769 Connected to device vid:did:rid of 1ae0:0028:00
10214 22:13:47.140068
10215 22:13:47.143596 tpm_get_response: command 0x17b, return code 0x0
10216 22:13:47.143677
10217 22:13:47.146370 ec_init: CrosEC protocol v3 supported (256, 248)
10218 22:13:47.150338
10219 22:13:47.153923 tpm_cleanup: add release locality here.
10220 22:13:47.154004
10221 22:13:47.154068 Shutting down all USB controllers.
10222 22:13:47.157178
10223 22:13:47.157258 Removing current net device
10224 22:13:47.157322
10225 22:13:47.164024 Exiting depthcharge with code 4 at timestamp: 70332185
10226 22:13:47.164105
10227 22:13:47.167158 LZMA decompressing kernel-1 to 0x821a6718
10228 22:13:47.167261
10229 22:13:47.170678 LZMA decompressing kernel-1 to 0x40000000
10230 22:13:48.438005
10231 22:13:48.438139 jumping to kernel
10232 22:13:48.438541 end: 2.2.4 bootloader-commands (duration 00:00:42) [common]
10233 22:13:48.438648 start: 2.2.5 auto-login-action (timeout 00:03:43) [common]
10234 22:13:48.438724 Setting prompt string to ['Linux version [0-9]']
10235 22:13:48.438793 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10236 22:13:48.438862 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10237 22:13:48.519990
10238 22:13:48.522844 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10239 22:13:48.526291 start: 2.2.5.1 login-action (timeout 00:03:43) [common]
10240 22:13:48.526385 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10241 22:13:48.526475 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10242 22:13:48.526552 Using line separator: #'\n'#
10243 22:13:48.526613 No login prompt set.
10244 22:13:48.526673 Parsing kernel messages
10245 22:13:48.526727 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10246 22:13:48.526829 [login-action] Waiting for messages, (timeout 00:03:43)
10247 22:13:48.545855 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1606555-arm64-gcc-10-defconfig-arm64-chromebook-vtq55) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Jun 4 21:56:05 UTC 2023
10248 22:13:48.549002 [ 0.000000] random: crng init done
10249 22:13:48.555414 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10250 22:13:48.558792 [ 0.000000] efi: UEFI not found.
10251 22:13:48.565569 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10252 22:13:48.572014 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10253 22:13:48.581824 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10254 22:13:48.591984 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10255 22:13:48.598247 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10256 22:13:48.604841 [ 0.000000] printk: bootconsole [mtk8250] enabled
10257 22:13:48.611601 [ 0.000000] NUMA: No NUMA configuration found
10258 22:13:48.618038 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10259 22:13:48.621555 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10260 22:13:48.624735 [ 0.000000] Zone ranges:
10261 22:13:48.631333 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10262 22:13:48.634793 [ 0.000000] DMA32 empty
10263 22:13:48.641364 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10264 22:13:48.644380 [ 0.000000] Movable zone start for each node
10265 22:13:48.648157 [ 0.000000] Early memory node ranges
10266 22:13:48.654590 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10267 22:13:48.660902 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10268 22:13:48.667397 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10269 22:13:48.674054 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10270 22:13:48.680807 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10271 22:13:48.687287 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10272 22:13:48.743296 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10273 22:13:48.750092 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10274 22:13:48.756523 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10275 22:13:48.760143 [ 0.000000] psci: probing for conduit method from DT.
10276 22:13:48.766515 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10277 22:13:48.769862 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10278 22:13:48.776507 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10279 22:13:48.780357 [ 0.000000] psci: SMC Calling Convention v1.2
10280 22:13:48.786063 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10281 22:13:48.789821 [ 0.000000] Detected VIPT I-cache on CPU0
10282 22:13:48.796441 [ 0.000000] CPU features: detected: GIC system register CPU interface
10283 22:13:48.803091 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10284 22:13:48.809205 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10285 22:13:48.816109 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10286 22:13:48.825558 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10287 22:13:48.832332 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10288 22:13:48.835728 [ 0.000000] alternatives: applying boot alternatives
10289 22:13:48.842286 [ 0.000000] Fallback order for Node 0: 0
10290 22:13:48.848997 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10291 22:13:48.852512 [ 0.000000] Policy zone: Normal
10292 22:13:48.865593 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10293 22:13:48.875158 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10294 22:13:48.885926 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10295 22:13:48.896058 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10296 22:13:48.902318 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10297 22:13:48.905799 <6>[ 0.000000] software IO TLB: area num 8.
10298 22:13:48.961417 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10299 22:13:49.110611 <6>[ 0.000000] Memory: 7952204K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 400564K reserved, 32768K cma-reserved)
10300 22:13:49.116658 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10301 22:13:49.123356 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10302 22:13:49.126564 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10303 22:13:49.133303 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10304 22:13:49.140159 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10305 22:13:49.143013 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10306 22:13:49.153128 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10307 22:13:49.159340 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10308 22:13:49.166131 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10309 22:13:49.172693 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10310 22:13:49.176297 <6>[ 0.000000] GICv3: 608 SPIs implemented
10311 22:13:49.179423 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10312 22:13:49.185785 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10313 22:13:49.189295 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10314 22:13:49.196424 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10315 22:13:49.209081 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10316 22:13:49.222279 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10317 22:13:49.229005 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10318 22:13:49.236494 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10319 22:13:49.250077 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10320 22:13:49.256586 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10321 22:13:49.263023 <6>[ 0.009227] Console: colour dummy device 80x25
10322 22:13:49.273330 <6>[ 0.013955] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10323 22:13:49.279784 <6>[ 0.024398] pid_max: default: 32768 minimum: 301
10324 22:13:49.283395 <6>[ 0.029271] LSM: Security Framework initializing
10325 22:13:49.289821 <6>[ 0.034239] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10326 22:13:49.299333 <6>[ 0.042102] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10327 22:13:49.309663 <6>[ 0.051533] cblist_init_generic: Setting adjustable number of callback queues.
10328 22:13:49.312772 <6>[ 0.058987] cblist_init_generic: Setting shift to 3 and lim to 1.
10329 22:13:49.319276 <6>[ 0.065326] cblist_init_generic: Setting shift to 3 and lim to 1.
10330 22:13:49.326025 <6>[ 0.071734] rcu: Hierarchical SRCU implementation.
10331 22:13:49.332514 <6>[ 0.076748] rcu: Max phase no-delay instances is 1000.
10332 22:13:49.338801 <6>[ 0.083771] EFI services will not be available.
10333 22:13:49.342117 <6>[ 0.088771] smp: Bringing up secondary CPUs ...
10334 22:13:49.350620 <6>[ 0.093821] Detected VIPT I-cache on CPU1
10335 22:13:49.356812 <6>[ 0.093894] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10336 22:13:49.363337 <6>[ 0.093924] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10337 22:13:49.366645 <6>[ 0.094264] Detected VIPT I-cache on CPU2
10338 22:13:49.376787 <6>[ 0.094313] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10339 22:13:49.383003 <6>[ 0.094330] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10340 22:13:49.386490 <6>[ 0.094595] Detected VIPT I-cache on CPU3
10341 22:13:49.393276 <6>[ 0.094641] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10342 22:13:49.399536 <6>[ 0.094655] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10343 22:13:49.406345 <6>[ 0.094962] CPU features: detected: Spectre-v4
10344 22:13:49.409421 <6>[ 0.094968] CPU features: detected: Spectre-BHB
10345 22:13:49.412673 <6>[ 0.094974] Detected PIPT I-cache on CPU4
10346 22:13:49.419197 <6>[ 0.095031] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10347 22:13:49.426213 <6>[ 0.095048] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10348 22:13:49.432499 <6>[ 0.095342] Detected PIPT I-cache on CPU5
10349 22:13:49.439096 <6>[ 0.095405] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10350 22:13:49.445781 <6>[ 0.095421] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10351 22:13:49.450334 <6>[ 0.095706] Detected PIPT I-cache on CPU6
10352 22:13:49.455588 <6>[ 0.095771] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10353 22:13:49.465673 <6>[ 0.095787] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10354 22:13:49.468899 <6>[ 0.096085] Detected PIPT I-cache on CPU7
10355 22:13:49.475278 <6>[ 0.096150] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10356 22:13:49.482242 <6>[ 0.096166] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10357 22:13:49.485643 <6>[ 0.096212] smp: Brought up 1 node, 8 CPUs
10358 22:13:49.492224 <6>[ 0.237534] SMP: Total of 8 processors activated.
10359 22:13:49.495313 <6>[ 0.242455] CPU features: detected: 32-bit EL0 Support
10360 22:13:49.505235 <6>[ 0.247818] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10361 22:13:49.511481 <6>[ 0.256618] CPU features: detected: Common not Private translations
10362 22:13:49.518187 <6>[ 0.263094] CPU features: detected: CRC32 instructions
10363 22:13:49.524619 <6>[ 0.268445] CPU features: detected: RCpc load-acquire (LDAPR)
10364 22:13:49.527980 <6>[ 0.274404] CPU features: detected: LSE atomic instructions
10365 22:13:49.534623 <6>[ 0.280185] CPU features: detected: Privileged Access Never
10366 22:13:49.541223 <6>[ 0.285965] CPU features: detected: RAS Extension Support
10367 22:13:49.548367 <6>[ 0.291574] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10368 22:13:49.551658 <6>[ 0.298794] CPU: All CPU(s) started at EL2
10369 22:13:49.557975 <6>[ 0.303136] alternatives: applying system-wide alternatives
10370 22:13:49.567739 <6>[ 0.313874] devtmpfs: initialized
10371 22:13:49.583123 <6>[ 0.322641] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10372 22:13:49.589929 <6>[ 0.332606] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10373 22:13:49.596427 <6>[ 0.340578] pinctrl core: initialized pinctrl subsystem
10374 22:13:49.600003 <6>[ 0.347215] DMI not present or invalid.
10375 22:13:49.605999 <6>[ 0.351617] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10376 22:13:49.616054 <6>[ 0.358468] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10377 22:13:49.623061 <6>[ 0.366049] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10378 22:13:49.632480 <6>[ 0.374258] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10379 22:13:49.636097 <6>[ 0.382501] audit: initializing netlink subsys (disabled)
10380 22:13:49.645684 <5>[ 0.388196] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10381 22:13:49.652245 <6>[ 0.388893] thermal_sys: Registered thermal governor 'step_wise'
10382 22:13:49.659484 <6>[ 0.396162] thermal_sys: Registered thermal governor 'power_allocator'
10383 22:13:49.662378 <6>[ 0.402416] cpuidle: using governor menu
10384 22:13:49.669268 <6>[ 0.413377] NET: Registered PF_QIPCRTR protocol family
10385 22:13:49.675509 <6>[ 0.418853] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10386 22:13:49.682145 <6>[ 0.425955] ASID allocator initialised with 32768 entries
10387 22:13:49.685024 <6>[ 0.432514] Serial: AMBA PL011 UART driver
10388 22:13:49.695109 <4>[ 0.441115] Trying to register duplicate clock ID: 134
10389 22:13:49.749340 <6>[ 0.498414] KASLR enabled
10390 22:13:49.763583 <6>[ 0.506154] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10391 22:13:49.770250 <6>[ 0.513169] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10392 22:13:49.776234 <6>[ 0.519660] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10393 22:13:49.783003 <6>[ 0.526666] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10394 22:13:49.789408 <6>[ 0.533153] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10395 22:13:49.795986 <6>[ 0.540158] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10396 22:13:49.802882 <6>[ 0.546645] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10397 22:13:49.809287 <6>[ 0.553652] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10398 22:13:49.812540 <6>[ 0.561162] ACPI: Interpreter disabled.
10399 22:13:49.821156 <6>[ 0.567549] iommu: Default domain type: Translated
10400 22:13:49.828053 <6>[ 0.572661] iommu: DMA domain TLB invalidation policy: strict mode
10401 22:13:49.831482 <5>[ 0.579318] SCSI subsystem initialized
10402 22:13:49.838146 <6>[ 0.583486] usbcore: registered new interface driver usbfs
10403 22:13:49.844436 <6>[ 0.589219] usbcore: registered new interface driver hub
10404 22:13:49.847908 <6>[ 0.594771] usbcore: registered new device driver usb
10405 22:13:49.854839 <6>[ 0.600847] pps_core: LinuxPPS API ver. 1 registered
10406 22:13:49.865097 <6>[ 0.606041] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10407 22:13:49.868662 <6>[ 0.615388] PTP clock support registered
10408 22:13:49.871074 <6>[ 0.619631] EDAC MC: Ver: 3.0.0
10409 22:13:49.878396 <6>[ 0.624765] FPGA manager framework
10410 22:13:49.884951 <6>[ 0.628444] Advanced Linux Sound Architecture Driver Initialized.
10411 22:13:49.888377 <6>[ 0.635218] vgaarb: loaded
10412 22:13:49.895103 <6>[ 0.638382] clocksource: Switched to clocksource arch_sys_counter
10413 22:13:49.898253 <5>[ 0.644821] VFS: Disk quotas dquot_6.6.0
10414 22:13:49.905382 <6>[ 0.649006] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10415 22:13:49.907812 <6>[ 0.656198] pnp: PnP ACPI: disabled
10416 22:13:49.917159 <6>[ 0.662925] NET: Registered PF_INET protocol family
10417 22:13:49.926531 <6>[ 0.668521] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10418 22:13:49.938221 <6>[ 0.680844] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10419 22:13:49.947590 <6>[ 0.689657] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10420 22:13:49.954458 <6>[ 0.697626] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10421 22:13:49.964048 <6>[ 0.706325] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10422 22:13:49.971578 <6>[ 0.716069] TCP: Hash tables configured (established 65536 bind 65536)
10423 22:13:49.977540 <6>[ 0.722927] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10424 22:13:49.987213 <6>[ 0.730126] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10425 22:13:49.994046 <6>[ 0.737830] NET: Registered PF_UNIX/PF_LOCAL protocol family
10426 22:13:50.000483 <6>[ 0.743990] RPC: Registered named UNIX socket transport module.
10427 22:13:50.003579 <6>[ 0.750146] RPC: Registered udp transport module.
10428 22:13:50.010069 <6>[ 0.755079] RPC: Registered tcp transport module.
10429 22:13:50.017156 <6>[ 0.760013] RPC: Registered tcp NFSv4.1 backchannel transport module.
10430 22:13:50.019999 <6>[ 0.766682] PCI: CLS 0 bytes, default 64
10431 22:13:50.023405 <6>[ 0.771030] Unpacking initramfs...
10432 22:13:50.040381 <6>[ 0.782995] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10433 22:13:50.050200 <6>[ 0.791657] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10434 22:13:50.053444 <6>[ 0.800491] kvm [1]: IPA Size Limit: 40 bits
10435 22:13:50.060046 <6>[ 0.805021] kvm [1]: GICv3: no GICV resource entry
10436 22:13:50.063368 <6>[ 0.810044] kvm [1]: disabling GICv2 emulation
10437 22:13:50.069712 <6>[ 0.814733] kvm [1]: GIC system register CPU interface enabled
10438 22:13:50.073724 <6>[ 0.820892] kvm [1]: vgic interrupt IRQ18
10439 22:13:50.080123 <6>[ 0.826449] kvm [1]: VHE mode initialized successfully
10440 22:13:50.087022 <5>[ 0.832844] Initialise system trusted keyrings
10441 22:13:50.093464 <6>[ 0.837625] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10442 22:13:50.102045 <6>[ 0.847824] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10443 22:13:50.108515 <5>[ 0.854204] NFS: Registering the id_resolver key type
10444 22:13:50.111889 <5>[ 0.859503] Key type id_resolver registered
10445 22:13:50.118593 <5>[ 0.863920] Key type id_legacy registered
10446 22:13:50.125086 <6>[ 0.868199] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10447 22:13:50.131600 <6>[ 0.875123] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10448 22:13:50.137877 <6>[ 0.882855] 9p: Installing v9fs 9p2000 file system support
10449 22:13:50.176047 <5>[ 0.921671] Key type asymmetric registered
10450 22:13:50.178651 <5>[ 0.926002] Asymmetric key parser 'x509' registered
10451 22:13:50.189371 <6>[ 0.931160] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10452 22:13:50.192249 <6>[ 0.938778] io scheduler mq-deadline registered
10453 22:13:50.195056 <6>[ 0.943539] io scheduler kyber registered
10454 22:13:50.214465 <6>[ 0.960520] EINJ: ACPI disabled.
10455 22:13:50.246727 <4>[ 0.986099] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10456 22:13:50.256375 <4>[ 0.996716] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10457 22:13:50.271586 <6>[ 1.017635] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10458 22:13:50.279922 <6>[ 1.025831] printk: console [ttyS0] disabled
10459 22:13:50.307735 <6>[ 1.050489] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10460 22:13:50.314108 <6>[ 1.059967] printk: console [ttyS0] enabled
10461 22:13:50.317541 <6>[ 1.059967] printk: console [ttyS0] enabled
10462 22:13:50.324052 <6>[ 1.068862] printk: bootconsole [mtk8250] disabled
10463 22:13:50.327567 <6>[ 1.068862] printk: bootconsole [mtk8250] disabled
10464 22:13:50.334001 <6>[ 1.080142] SuperH (H)SCI(F) driver initialized
10465 22:13:50.337456 <6>[ 1.085435] msm_serial: driver initialized
10466 22:13:50.351432 <6>[ 1.094355] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10467 22:13:50.361806 <6>[ 1.102901] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10468 22:13:50.368136 <6>[ 1.111443] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10469 22:13:50.378093 <6>[ 1.120072] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10470 22:13:50.387743 <6>[ 1.128777] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10471 22:13:50.394233 <6>[ 1.137499] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10472 22:13:50.404430 <6>[ 1.146038] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10473 22:13:50.410747 <6>[ 1.154851] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10474 22:13:50.420955 <6>[ 1.163395] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10475 22:13:50.432398 <6>[ 1.178790] loop: module loaded
10476 22:13:50.438973 <6>[ 1.184809] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10477 22:13:50.462182 <4>[ 1.208123] mtk-pmic-keys: Failed to locate of_node [id: -1]
10478 22:13:50.469021 <6>[ 1.214920] megasas: 07.719.03.00-rc1
10479 22:13:50.478078 <6>[ 1.224431] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10480 22:13:50.488057 <6>[ 1.233769] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10481 22:13:50.504301 <6>[ 1.250530] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10482 22:13:50.561603 <6>[ 1.300912] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10483 22:13:50.909595 <6>[ 1.655837] Freeing initrd memory: 20732K
10484 22:13:50.925315 <6>[ 1.671461] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10485 22:13:50.935821 <6>[ 1.682213] tun: Universal TUN/TAP device driver, 1.6
10486 22:13:50.939391 <6>[ 1.688264] thunder_xcv, ver 1.0
10487 22:13:50.942777 <6>[ 1.691771] thunder_bgx, ver 1.0
10488 22:13:50.945779 <6>[ 1.695268] nicpf, ver 1.0
10489 22:13:50.956336 <6>[ 1.699260] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10490 22:13:50.959802 <6>[ 1.706735] hns3: Copyright (c) 2017 Huawei Corporation.
10491 22:13:50.966290 <6>[ 1.712320] hclge is initializing
10492 22:13:50.969457 <6>[ 1.715900] e1000: Intel(R) PRO/1000 Network Driver
10493 22:13:50.976256 <6>[ 1.721028] e1000: Copyright (c) 1999-2006 Intel Corporation.
10494 22:13:50.979528 <6>[ 1.727041] e1000e: Intel(R) PRO/1000 Network Driver
10495 22:13:50.986017 <6>[ 1.732257] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10496 22:13:50.993145 <6>[ 1.738444] igb: Intel(R) Gigabit Ethernet Network Driver
10497 22:13:50.999384 <6>[ 1.744094] igb: Copyright (c) 2007-2014 Intel Corporation.
10498 22:13:51.006081 <6>[ 1.749930] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10499 22:13:51.012604 <6>[ 1.756447] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10500 22:13:51.016004 <6>[ 1.762906] sky2: driver version 1.30
10501 22:13:51.022588 <6>[ 1.767877] VFIO - User Level meta-driver version: 0.3
10502 22:13:51.029978 <6>[ 1.775993] usbcore: registered new interface driver usb-storage
10503 22:13:51.037409 <6>[ 1.782438] usbcore: registered new device driver onboard-usb-hub
10504 22:13:51.045275 <6>[ 1.791465] mt6397-rtc mt6359-rtc: registered as rtc0
10505 22:13:51.055038 <6>[ 1.796943] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-04T22:14:03 UTC (1685916843)
10506 22:13:51.058934 <6>[ 1.806547] i2c_dev: i2c /dev entries driver
10507 22:13:51.075159 <6>[ 1.818200] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10508 22:13:51.082500 <6>[ 1.828360] sdhci: Secure Digital Host Controller Interface driver
10509 22:13:51.088779 <6>[ 1.834797] sdhci: Copyright(c) Pierre Ossman
10510 22:13:51.095334 <6>[ 1.840187] Synopsys Designware Multimedia Card Interface Driver
10511 22:13:51.098818 <6>[ 1.846809] mmc0: CQHCI version 5.10
10512 22:13:51.105476 <6>[ 1.847335] sdhci-pltfm: SDHCI platform and OF driver helper
10513 22:13:51.112662 <6>[ 1.859075] ledtrig-cpu: registered to indicate activity on CPUs
10514 22:13:51.123262 <6>[ 1.866267] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10515 22:13:51.126991 <6>[ 1.873684] usbcore: registered new interface driver usbhid
10516 22:13:51.133123 <6>[ 1.879514] usbhid: USB HID core driver
10517 22:13:51.140012 <6>[ 1.883760] spi_master spi0: will run message pump with realtime priority
10518 22:13:51.186020 <6>[ 1.925400] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10519 22:13:51.204746 <6>[ 1.940708] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10520 22:13:51.208137 <6>[ 1.954285] mmc0: Command Queue Engine enabled
10521 22:13:51.215128 <6>[ 1.956019] cros-ec-spi spi0.0: Chrome EC device registered
10522 22:13:51.221612 <6>[ 1.959026] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10523 22:13:51.224904 <6>[ 1.972110] mmcblk0: mmc0:0001 DA4128 116 GiB
10524 22:13:51.238658 <6>[ 1.981192] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10525 22:13:51.244791 <6>[ 1.984073] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10526 22:13:51.251503 <6>[ 1.992624] NET: Registered PF_PACKET protocol family
10527 22:13:51.254649 <6>[ 1.997799] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10528 22:13:51.261381 <6>[ 2.001858] 9pnet: Installing 9P2000 support
10529 22:13:51.264594 <6>[ 2.007614] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10530 22:13:51.271140 <5>[ 2.011533] Key type dns_resolver registered
10531 22:13:51.278020 <6>[ 2.017323] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10532 22:13:51.281163 <6>[ 2.021824] registered taskstats version 1
10533 22:13:51.284533 <5>[ 2.032195] Loading compiled-in X.509 certificates
10534 22:13:51.319773 <4>[ 2.059423] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10535 22:13:51.329677 <4>[ 2.070112] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10536 22:13:51.339891 <3>[ 2.082982] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10537 22:13:51.352293 <6>[ 2.098345] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10538 22:13:51.358970 <6>[ 2.105242] xhci-mtk 11200000.usb: xHCI Host Controller
10539 22:13:51.365572 <6>[ 2.110748] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10540 22:13:51.375722 <6>[ 2.118606] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10541 22:13:51.382366 <6>[ 2.128036] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10542 22:13:51.388974 <6>[ 2.134102] xhci-mtk 11200000.usb: xHCI Host Controller
10543 22:13:51.395886 <6>[ 2.139585] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10544 22:13:51.403069 <6>[ 2.147238] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10545 22:13:51.409152 <6>[ 2.154938] hub 1-0:1.0: USB hub found
10546 22:13:51.412504 <6>[ 2.158960] hub 1-0:1.0: 1 port detected
10547 22:13:51.419028 <6>[ 2.163295] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10548 22:13:51.425674 <6>[ 2.172024] hub 2-0:1.0: USB hub found
10549 22:13:51.429283 <6>[ 2.176061] hub 2-0:1.0: 1 port detected
10550 22:13:51.437188 <6>[ 2.183359] mtk-msdc 11f70000.mmc: Got CD GPIO
10551 22:13:51.453864 <6>[ 2.196820] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10552 22:13:51.460323 <6>[ 2.204870] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10553 22:13:51.470501 <4>[ 2.212843] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10554 22:13:51.480162 <6>[ 2.222511] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10555 22:13:51.487480 <6>[ 2.230593] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10556 22:13:51.496758 <6>[ 2.238628] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10557 22:13:51.503771 <6>[ 2.246546] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10558 22:13:51.510418 <6>[ 2.254368] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10559 22:13:51.520180 <6>[ 2.262206] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10560 22:13:51.529779 <6>[ 2.272941] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10561 22:13:51.540094 <6>[ 2.281309] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10562 22:13:51.546535 <6>[ 2.289670] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10563 22:13:51.556494 <6>[ 2.298015] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10564 22:13:51.562809 <6>[ 2.306358] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10565 22:13:51.572900 <6>[ 2.314702] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10566 22:13:51.579727 <6>[ 2.323046] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10567 22:13:51.589856 <6>[ 2.331389] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10568 22:13:51.595992 <6>[ 2.339732] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10569 22:13:51.605987 <6>[ 2.348088] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10570 22:13:51.612851 <6>[ 2.356432] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10571 22:13:51.622913 <6>[ 2.364775] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10572 22:13:51.629260 <6>[ 2.373119] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10573 22:13:51.638878 <6>[ 2.381462] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10574 22:13:51.645528 <6>[ 2.389805] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10575 22:13:51.652581 <6>[ 2.398699] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10576 22:13:51.660031 <6>[ 2.406115] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10577 22:13:51.666800 <6>[ 2.413152] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10578 22:13:51.677202 <6>[ 2.420249] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10579 22:13:51.684157 <6>[ 2.427533] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10580 22:13:51.693704 <6>[ 2.434439] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10581 22:13:51.700557 <6>[ 2.443576] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10582 22:13:51.710486 <6>[ 2.452704] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10583 22:13:51.720189 <6>[ 2.462006] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10584 22:13:51.730104 <6>[ 2.471481] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10585 22:13:51.740028 <6>[ 2.480954] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10586 22:13:51.746661 <6>[ 2.490081] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10587 22:13:51.756525 <6>[ 2.499560] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10588 22:13:51.766377 <6>[ 2.508687] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10589 22:13:51.776557 <6>[ 2.517989] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10590 22:13:51.786165 <6>[ 2.528155] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10591 22:13:51.796986 <6>[ 2.539574] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10592 22:13:51.843651 <6>[ 2.586553] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10593 22:13:51.997342 <6>[ 2.743598] hub 1-1:1.0: USB hub found
10594 22:13:52.000566 <6>[ 2.748045] hub 1-1:1.0: 4 ports detected
10595 22:13:52.123657 <6>[ 2.866854] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10596 22:13:52.148496 <6>[ 2.894961] hub 2-1:1.0: USB hub found
10597 22:13:52.151705 <6>[ 2.899360] hub 2-1:1.0: 3 ports detected
10598 22:13:52.319429 <6>[ 3.062657] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10599 22:13:52.452685 <6>[ 3.198928] hub 1-1.4:1.0: USB hub found
10600 22:13:52.456027 <6>[ 3.203575] hub 1-1.4:1.0: 2 ports detected
10601 22:13:52.531669 <6>[ 3.274890] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10602 22:13:52.751620 <6>[ 3.494661] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10603 22:13:52.943532 <6>[ 3.686661] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10604 22:14:04.076169 <6>[ 14.827209] ALSA device list:
10605 22:14:04.082955 <6>[ 14.830464] No soundcards found.
10606 22:14:04.095587 <6>[ 14.842822] Freeing unused kernel memory: 8384K
10607 22:14:04.098288 <6>[ 14.847754] Run /init as init process
10608 22:14:04.123395 Starting syslogd: OK
10609 22:14:04.128357 Starting klogd: OK
10610 22:14:04.136549 Running sysctl: OK
10611 22:14:04.146513 Populating /dev using udev: <30>[ 14.892939] udevd[185]: starting version 3.2.9
10612 22:14:04.153624 <27>[ 14.900888] udevd[185]: specified user 'tss' unknown
10613 22:14:04.159956 <27>[ 14.906297] udevd[185]: specified group 'tss' unknown
10614 22:14:04.166056 <30>[ 14.912893] udevd[186]: starting eudev-3.2.9
10615 22:14:04.195651 <27>[ 14.943310] udevd[186]: specified user 'tss' unknown
10616 22:14:04.202370 <27>[ 14.948697] udevd[186]: specified group 'tss' unknown
10617 22:14:04.348870 <6>[ 15.093438] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10618 22:14:04.362502 <6>[ 15.109970] remoteproc remoteproc0: scp is available
10619 22:14:04.372232 <4>[ 15.115583] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10620 22:14:04.378961 <6>[ 15.125737] remoteproc remoteproc0: powering up scp
10621 22:14:04.388914 <4>[ 15.130943] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10622 22:14:04.395586 <3>[ 15.140791] remoteproc remoteproc0: request_firmware failed: -2
10623 22:14:04.413618 <3>[ 15.157864] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10624 22:14:04.420486 <3>[ 15.166085] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10625 22:14:04.430495 <6>[ 15.167169] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10626 22:14:04.436645 <3>[ 15.174207] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10627 22:14:04.446486 <3>[ 15.175253] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10628 22:14:04.452994 <6>[ 15.181902] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10629 22:14:04.463117 <3>[ 15.189892] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10630 22:14:04.469456 <3>[ 15.189905] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10631 22:14:04.479263 <3>[ 15.189924] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10632 22:14:04.485900 <6>[ 15.198078] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10633 22:14:04.492525 <6>[ 15.200413] usbcore: registered new interface driver r8152
10634 22:14:04.496247 <6>[ 15.202843] mc: Linux media interface: v0.10
10635 22:14:04.506201 <3>[ 15.206796] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10636 22:14:04.512745 <3>[ 15.206880] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10637 22:14:04.522193 <6>[ 15.210460] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10638 22:14:04.529526 <4>[ 15.231837] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10639 22:14:04.535596 <4>[ 15.231837] Fallback method does not support PEC.
10640 22:14:04.542202 <3>[ 15.239810] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10641 22:14:04.548876 <4>[ 15.258930] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10642 22:14:04.559379 <3>[ 15.266187] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10643 22:14:04.566422 <4>[ 15.274325] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10644 22:14:04.572371 <3>[ 15.287506] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10645 22:14:04.582431 <3>[ 15.287788] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10646 22:14:04.589072 <6>[ 15.294673] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10647 22:14:04.595877 <6>[ 15.304319] videodev: Linux video capture interface: v2.00
10648 22:14:04.602717 <3>[ 15.309461] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10649 22:14:04.613504 <3>[ 15.311189] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10650 22:14:04.620165 <4>[ 15.318073] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10651 22:14:04.629925 <4>[ 15.318085] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10652 22:14:04.639933 <6>[ 15.319917] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10653 22:14:04.646339 <6>[ 15.323776] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10654 22:14:04.652873 <6>[ 15.323789] pci_bus 0000:00: root bus resource [bus 00-ff]
10655 22:14:04.660229 <6>[ 15.323797] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10656 22:14:04.669727 <6>[ 15.323803] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10657 22:14:04.676869 <6>[ 15.323834] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10658 22:14:04.682910 <6>[ 15.323852] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10659 22:14:04.686310 <6>[ 15.323925] pci 0000:00:00.0: supports D1 D2
10660 22:14:04.692903 <6>[ 15.323929] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10661 22:14:04.703095 <6>[ 15.325745] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10662 22:14:04.709554 <6>[ 15.325850] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10663 22:14:04.715993 <6>[ 15.325880] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10664 22:14:04.722811 <6>[ 15.325900] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10665 22:14:04.732470 <6>[ 15.325920] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10666 22:14:04.736114 <6>[ 15.326034] pci 0000:01:00.0: supports D1 D2
10667 22:14:04.742609 <6>[ 15.326038] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10668 22:14:04.752503 <3>[ 15.326709] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10669 22:14:04.759038 <3>[ 15.326724] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10670 22:14:04.766357 <3>[ 15.326735] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10671 22:14:04.775996 <3>[ 15.326823] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10672 22:14:04.782469 <6>[ 15.334490] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10673 22:14:04.792430 <6>[ 15.336045] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10674 22:14:04.799131 <6>[ 15.342530] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10675 22:14:04.808941 <3>[ 15.369094] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10676 22:14:04.815282 <6>[ 15.374175] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10677 22:14:04.821841 <6>[ 15.378560] r8152 2-1.3:1.0 eth0: v1.12.13
10678 22:14:04.828454 <6>[ 15.406679] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10679 22:14:04.838709 <6>[ 15.411993] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10680 22:14:04.841652 <6>[ 15.441072] Bluetooth: Core ver 2.22
10681 22:14:04.848586 <6>[ 15.447397] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10682 22:14:04.854943 <6>[ 15.447479] usbcore: registered new interface driver cdc_ether
10683 22:14:04.861731 <6>[ 15.455341] NET: Registered PF_BLUETOOTH protocol family
10684 22:14:04.868246 <6>[ 15.455801] usbcore: registered new interface driver r8153_ecm
10685 22:14:04.874942 <6>[ 15.461609] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10686 22:14:04.881606 <6>[ 15.461636] pci 0000:00:00.0: PCI bridge to [bus 01]
10687 22:14:04.888058 <6>[ 15.461645] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10688 22:14:04.894603 <6>[ 15.461981] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10689 22:14:04.901407 <6>[ 15.469358] Bluetooth: HCI device and connection manager initialized
10690 22:14:04.907704 <6>[ 15.478012] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10691 22:14:04.910991 <6>[ 15.484369] Bluetooth: HCI socket layer initialized
10692 22:14:04.920943 <6>[ 15.489731] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10693 22:14:04.924887 <6>[ 15.490098] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10694 22:14:04.930943 <6>[ 15.495761] Bluetooth: L2CAP socket layer initialized
10695 22:14:04.937404 <6>[ 15.504765] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10696 22:14:04.950714 <6>[ 15.505362] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10697 22:14:04.954372 <6>[ 15.505519] usbcore: registered new interface driver uvcvideo
10698 22:14:04.960830 <6>[ 15.511947] Bluetooth: SCO socket layer initialized
10699 22:14:04.968087 <5>[ 15.521412] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10700 22:14:04.974279 <6>[ 15.525327] remoteproc remoteproc0: powering up scp
10701 22:14:04.984204 <4>[ 15.525363] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10702 22:14:04.990804 <3>[ 15.525371] remoteproc remoteproc0: request_firmware failed: -2
10703 22:14:04.996901 <3>[ 15.525375] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10704 22:14:05.003772 <6>[ 15.591201] usbcore: registered new interface driver btusb
10705 22:14:05.013704 <4>[ 15.592266] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10706 22:14:05.019952 <3>[ 15.592278] Bluetooth: hci0: Failed to load firmware file (-2)
10707 22:14:05.027025 <3>[ 15.592282] Bluetooth: hci0: Failed to set up firmware (-2)
10708 22:14:05.036704 <4>[ 15.592285] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10709 22:14:05.043456 <5>[ 15.618206] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10710 22:14:05.052737 <4>[ 15.795819] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10711 22:14:05.056446 <6>[ 15.804715] cfg80211: failed to load regulatory.db
10712 22:14:05.102888 <6>[ 15.847308] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10713 22:14:05.109193 <6>[ 15.854817] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10714 22:14:05.134202 <6>[ 15.881717] mt7921e 0000:01:00.0: ASIC revision: 79610010
10715 22:14:05.241990 <4>[ 15.982886] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10716 22:14:05.242098 done
10717 22:14:05.262384 Saving random seed: OK
10718 22:14:05.277560 Starting network: OK
10719 22:14:05.318285 Starting dropbear sshd: <6>[ 16.065812] NET: Registered PF_INET6 protocol family
10720 22:14:05.324645 <6>[ 16.072598] Segment Routing with IPv6
10721 22:14:05.327983 <6>[ 16.076569] In-situ OAM (IOAM) with IPv6
10722 22:14:05.331810 OK
10723 22:14:05.341305 /bin/sh: can't access tty; job control turned off
10724 22:14:05.341695 Matched prompt #10: / #
10726 22:14:05.341915 Setting prompt string to ['/ #']
10727 22:14:05.342004 end: 2.2.5.1 login-action (duration 00:00:17) [common]
10729 22:14:05.342186 end: 2.2.5 auto-login-action (duration 00:00:17) [common]
10730 22:14:05.342267 start: 2.2.6 expect-shell-connection (timeout 00:03:26) [common]
10731 22:14:05.342335 Setting prompt string to ['/ #']
10732 22:14:05.342394 Forcing a shell prompt, looking for ['/ #']
10734 22:14:05.392570 / #
10735 22:14:05.392671 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10736 22:14:05.392745 Waiting using forced prompt support (timeout 00:02:30)
10737 22:14:05.392839 <4>[ 16.104976] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10738 22:14:05.397628
10739 22:14:05.397897 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10740 22:14:05.397987 start: 2.2.7 export-device-env (timeout 00:03:26) [common]
10741 22:14:05.398078 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10742 22:14:05.398164 end: 2.2 depthcharge-retry (duration 00:01:34) [common]
10743 22:14:05.398247 end: 2 depthcharge-action (duration 00:01:34) [common]
10744 22:14:05.398332 start: 3 lava-test-retry (timeout 00:01:00) [common]
10745 22:14:05.398416 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10746 22:14:05.398493 Using namespace: common
10748 22:14:05.498811 / # #
10749 22:14:05.498923 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10750 22:14:05.499027 #<4>[ 16.224947] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10751 22:14:05.504035
10752 22:14:05.504299 Using /lava-10583893
10754 22:14:05.604720 / # export SHELL=/bin/sh
10755 22:14:05.604862 export SHELL=/bin/sh<4>[ 16.344873] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10756 22:14:05.610059
10758 22:14:05.710567 / # . /lava-10583893/environment
10759 22:14:05.723645 . /lava-10583893/environment<4>[ 16.464916] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10760 22:14:05.723738
10762 22:14:05.824215 / # /lava-10583893/bin/lava-test-runner /lava-10583893/0
10763 22:14:05.824324 Test shell timeout: 10s (minimum of the action and connection timeout)
10764 22:14:05.830019 /lava-10583893/bin/lava-test-runner /lava-10583893/0
10765 22:14:05.844019 <4>[ 16.585160] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10766 22:14:05.852509 + export 'TESTRUN_ID=0_dmesg'
10767 22:14:05.862748 + cd /lava-10583893/0/tests/0_dme<8>[ 16.608238] <LAVA_SIGNAL_STARTRUN 0_dmesg 10583893_1.5.2.3.1>
10768 22:14:05.862832 sg
10769 22:14:05.862897 + cat uuid
10770 22:14:05.863130 Received signal: <STARTRUN> 0_dmesg 10583893_1.5.2.3.1
10771 22:14:05.863208 Starting test lava.0_dmesg (10583893_1.5.2.3.1)
10772 22:14:05.863290 Skipping test definition patterns.
10773 22:14:05.865520 + UUID=10583893_1.5.2.3.1
10774 22:14:05.865603 + set +x
10775 22:14:05.872157 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10776 22:14:05.884231 <8>[ 16.628954] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10777 22:14:05.884483 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10779 22:14:05.904998 <8>[ 16.649517] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10780 22:14:05.905248 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10782 22:14:05.925744 <8>[ 16.670305] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10783 22:14:05.925996 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10785 22:14:05.929225 + set +x
10786 22:14:05.932447 <8>[ 16.679792] <LAVA_SIGNAL_ENDRUN 0_dmesg 10583893_1.5.2.3.1>
10787 22:14:05.932695 Received signal: <ENDRUN> 0_dmesg 10583893_1.5.2.3.1
10788 22:14:05.932779 Ending use of test pattern.
10789 22:14:05.932841 Ending test lava.0_dmesg (10583893_1.5.2.3.1), duration 0.07
10791 22:14:05.936097 <LAVA_TEST_RUNNER EXIT>
10792 22:14:05.936348 ok: lava_test_shell seems to have completed
10793 22:14:05.936453 alert: pass
crit: pass
emerg: pass
10794 22:14:05.936540 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10795 22:14:05.936620 end: 3 lava-test-retry (duration 00:00:01) [common]
10796 22:14:05.936703 start: 4 lava-test-retry (timeout 00:01:00) [common]
10797 22:14:05.936782 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
10798 22:14:05.936844 Using namespace: common
10800 22:14:06.037159 / # #
10801 22:14:06.037275 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10802 22:14:06.037373 Using /lava-10583893
10804 22:14:06.137686 export SHELL=/bin/sh
10805 22:14:06.137831 <4>[ 16.717223] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10806 22:14:06.137904 #
10807 22:14:06.137965 / # <4>[ 16.836781] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10809 22:14:06.238462 export SHELL=/bin/sh. /lava-10583893/environment
10810 22:14:06.238606
10811 22:14:06.238697 / # . /lava-10583893/environment<4>[ 16.957018] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10813 22:14:06.339235 /lava-10583893/bin/lava-test-runner /lava-10583893/1
10814 22:14:06.339377 Test shell timeout: 10s (minimum of the action and connection timeout)
10815 22:14:06.339497
10816 22:14:06.339566 / # /lava-10583893/bin/lava-test-runner /lava-10583893/1<4>[ 17.076818] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10817 22:14:06.345621
10818 22:14:06.387344 + export 'TESTRUN_ID=1_bootrr'
10819 22:14:06.387435 <8>[ 17.119827] <LAVA_SIGNAL_STARTRUN 1_bootrr 10583893_1.5.2.3.5>
10820 22:14:06.387501 + cd /lava-10583893/1/tests/1_bootrr
10821 22:14:06.387561 + cat uuid
10822 22:14:06.387653 + UUID=10583893_1.5.2.3.5
10823 22:14:06.387709 + set +x
10824 22:14:06.387940 Received signal: <STARTRUN> 1_bootrr 10583893_1.5.2.3.5
10825 22:14:06.388004 Starting test lava.1_bootrr (10583893_1.5.2.3.5)
10826 22:14:06.388078 Skipping test definition patterns.
10827 22:14:06.390221 + export 'PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-10583893/1/../bin:/sbin:/usr/sbin:/bin:/usr/bin'
10828 22:14:06.396714 <8>[ 17.142385] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
10829 22:14:06.396963 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
10831 22:14:06.400402
10832 22:14:06.400497 + cd /opt/bootrr/libexec/bootrr
10833 22:14:06.403704 + sh helpers/bootrr-auto
10834 22:14:06.406645 /lava-10583893/1/../bin/lava-test-case
10835 22:14:06.416718 /lava-10583893/1/../bin/lava<8>[ 17.162008] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
10836 22:14:06.416798 -test-case
10837 22:14:06.417030 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
10839 22:14:06.422472 /usr/bin/tpm2_getcap
10840 22:14:06.446212 <3>[ 17.195023] mt7921e 0000:01:00.0: hardware init failed
10841 22:14:06.456306 /lava-10583893/1/../bin/lava-test-case
10842 22:14:06.463024 <8>[ 17.208132] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=pass>
10843 22:14:06.463296 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=pass
10845 22:14:06.479043 /lava-10583893/1/../bin/lava-test-case
10846 22:14:06.485681 <8>[ 17.230303] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
10847 22:14:06.485940 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
10849 22:14:06.497359 /lava-10583893/1/../bin/lava-test-case
10850 22:14:06.504104 <8>[ 17.248646] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
10851 22:14:06.504353 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
10853 22:14:06.516178 /lava-10583893/1/../bin/lava-test-case
10854 22:14:06.522518 <8>[ 17.267363] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
10855 22:14:06.522768 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
10857 22:14:06.534052 /lava-10583893/1/../bin/lava-test-case
10858 22:14:06.540358 <8>[ 17.285321] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
10859 22:14:06.540612 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
10861 22:14:06.552140 /lava-10583893/1/../bin/lava-test-case
10862 22:14:06.558772 <8>[ 17.303615] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
10863 22:14:06.559027 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
10865 22:14:06.569463 /lava-10583893/1/../bin/lava-test-case
10866 22:14:06.575549 <8>[ 17.320401] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
10867 22:14:06.575803 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
10869 22:14:06.587443 /lava-10583893/1/../bin/lava-test-case
10870 22:14:06.594310 <8>[ 17.338937] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
10871 22:14:06.594562 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
10873 22:14:06.603382 /lava-10583893/1/../bin/lava-test-case
10874 22:14:06.609934 <8>[ 17.354874] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
10875 22:14:06.610185 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
10877 22:14:06.622581 /lava-10583893/1/../bin/lava-test-case
10878 22:14:06.629113 <8>[ 17.373873] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
10879 22:14:06.629363 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
10881 22:14:06.641729 /lava-10583893/1/../bin/lava-test-case
10882 22:14:06.648161 <8>[ 17.393049] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
10883 22:14:06.648412 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
10885 22:14:06.661068 /lava-10583893/1/../bin/lava-test-case
10886 22:14:06.667559 <8>[ 17.412308] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
10887 22:14:06.667811 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
10889 22:14:06.680332 /lava-10583893/1/../bin/lava-test-case
10890 22:14:06.686077 <8>[ 17.431211] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
10891 22:14:06.686328 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
10893 22:14:06.696941 /lava-10583893/1/../bin/lava-test-case
10894 22:14:06.703155 <8>[ 17.448467] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
10895 22:14:06.703415 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
10897 22:14:06.716258 /lava-10583893/1/../bin/lava-test-case
10898 22:14:06.722486 <8>[ 17.467602] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
10899 22:14:06.722737 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
10901 22:14:06.732583 /lava-10583893/1/../bin/lava-test-case
10902 22:14:06.739050 <8>[ 17.483724] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
10903 22:14:06.739301 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
10905 22:14:06.751392 /lava-10583893/1/../bin/lava-test-case
10906 22:14:06.758371 <8>[ 17.502825] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
10907 22:14:06.758622 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
10909 22:14:06.767708 /lava-10583893/1/../bin/lava-test-case
10910 22:14:06.773927 <8>[ 17.518468] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
10911 22:14:06.774180 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
10913 22:14:06.785222 /lava-10583893/1/../bin/lava-test-case
10914 22:14:06.791612 <8>[ 17.536940] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
10915 22:14:06.791865 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
10917 22:14:06.801325 /lava-10583893/1/../bin/lava-test-case
10918 22:14:06.807337 <8>[ 17.552633] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
10919 22:14:06.807589 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
10921 22:14:06.819597 /lava-10583893/1/../bin/lava-test-case
10922 22:14:06.826321 <8>[ 17.570863] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
10923 22:14:06.826574 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
10925 22:14:06.835203 /lava-10583893/1/../bin/lava-test-case
10926 22:14:06.841617 <8>[ 17.586741] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
10927 22:14:06.841868 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
10929 22:14:06.854104 /lava-10583893/1/../bin/lava-test-case
10930 22:14:06.860760 <8>[ 17.604838] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
10931 22:14:06.861022 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
10933 22:14:06.872651 /lava-10583893/1/../bin/lava-test-case
10934 22:14:06.879083 <8>[ 17.623958] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
10935 22:14:06.879332 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
10937 22:14:06.888160 /lava-10583893/1/../bin/lava-test-case
10938 22:14:06.894943 <8>[ 17.639597] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
10939 22:14:06.895197 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
10941 22:14:06.907455 /lava-10583893/1/../bin/lava-test-case
10942 22:14:06.913753 <8>[ 17.658362] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
10943 22:14:06.914027 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
10945 22:14:06.922931 /lava-10583893/1/../bin/lava-test-case
10946 22:14:06.929675 <8>[ 17.674699] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
10947 22:14:06.929946 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
10949 22:14:06.941517 /lava-10583893/1/../bin/lava-test-case
10950 22:14:06.948100 <8>[ 17.693117] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
10951 22:14:06.948343 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
10953 22:14:06.959322 /lava-10583893/1/../bin/lava-test-case
10954 22:14:06.965851 <8>[ 17.710679] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
10955 22:14:06.966094 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
10957 22:14:06.977786 /lava-10583893/1/../bin/lava-test-case
10958 22:14:06.984037 <8>[ 17.728749] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
10959 22:14:06.984289 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
10961 22:14:06.995506 /lava-10583893/1/../bin/lava-test-case
10962 22:14:07.002210 <8>[ 17.746952] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
10963 22:14:07.002479 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
10965 22:14:07.011527 /lava-10583893/1/../bin/lava-test-case
10966 22:14:07.018439 <8>[ 17.763344] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
10967 22:14:07.018715 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
10969 22:14:07.029996 /lava-10583893/1/../bin/lava-test-case
10970 22:14:07.036348 <8>[ 17.781743] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
10971 22:14:07.036625 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
10973 22:14:07.048239 /lava-10583893/1/../bin/lava-test-case
10974 22:14:07.055104 <8>[ 17.800100] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
10975 22:14:07.055372 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
10977 22:14:07.064659 /lava-10583893/1/../bin/lava-test-case
10978 22:14:07.071162 <8>[ 17.816225] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
10979 22:14:07.071444 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
10981 22:14:07.082938 /lava-10583893/1/../bin/lava-test-case
10982 22:14:07.089682 <8>[ 17.834334] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
10983 22:14:07.089962 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
10985 22:14:07.098860 /lava-10583893/1/../bin/lava-test-case
10986 22:14:07.105383 <8>[ 17.849973] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
10987 22:14:07.105653 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
10989 22:14:07.117187 /lava-10583893/1/../bin/lava-test-case
10990 22:14:07.123392 <8>[ 17.868589] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
10991 22:14:07.123662 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
10993 22:14:07.133078 /lava-10583893/1/../bin/lava-test-case
10994 22:14:07.139688 <8>[ 17.884379] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
10995 22:14:07.139961 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
10997 22:14:07.151875 /lava-10583893/1/../bin/lava-test-case
10998 22:14:07.158272 <8>[ 17.903537] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
10999 22:14:07.158540 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
11001 22:14:07.168106 /lava-10583893/1/../bin/lava-test-case
11002 22:14:07.174576 <8>[ 17.919572] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
11003 22:14:07.174847 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
11005 22:14:07.187406 /lava-10583893/1/../bin/lava-test-case
11006 22:14:07.193843 <8>[ 17.938965] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
11007 22:14:07.194089 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
11009 22:14:07.204044 /lava-10583893/1/../bin/lava-test-case
11010 22:14:07.210423 <8>[ 17.955285] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
11011 22:14:07.210698 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11013 22:14:07.222504 /lava-10583893/1/../bin/lava-test-case
11014 22:14:07.229150 <8>[ 17.973439] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11015 22:14:07.229423 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11017 22:14:07.238113 /lava-10583893/1/../bin/lava-test-case
11018 22:14:07.244601 <8>[ 17.989345] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11019 22:14:07.244845 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11021 22:14:07.255989 /lava-10583893/1/../bin/lava-test-case
11022 22:14:07.262564 <8>[ 18.007442] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11023 22:14:07.262840 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11025 22:14:07.271235 /lava-10583893/1/../bin/lava-test-case
11026 22:14:07.277700 <8>[ 18.022306] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11027 22:14:07.277971 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11029 22:14:07.289436 /lava-10583893/1/../bin/lava-test-case
11030 22:14:07.296656 <8>[ 18.041262] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11031 22:14:07.296928 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11033 22:14:07.307886 /lava-10583893/1/../bin/lava-test-case
11034 22:14:07.314626 <8>[ 18.059665] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11035 22:14:07.314879 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11037 22:14:08.326537 /lava-10583893/1/../bin/lava-test-case
11038 22:14:08.333379 <8>[ 19.079118] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=fail>
11039 22:14:08.333670 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=fail
11041 22:14:09.345720 /lava-10583893/1/../bin/lava-test-case
11042 22:14:09.352413 <8>[ 20.097998] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=blocked>
11043 22:14:09.352680 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=blocked
11044 22:14:09.352767 Bad test result: blocked
11045 22:14:09.362167 /lava-10583893/1/../bin/lava-test-case
11046 22:14:09.369152 <8>[ 20.113775] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11047 22:14:09.369420 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11049 22:14:09.380582 /lava-10583893/1/../bin/lava-test-case
11050 22:14:09.386875 <8>[ 20.131969] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11051 22:14:09.387124 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11053 22:14:09.397790 /lava-10583893/1/../bin/lava-test-case
11054 22:14:09.404174 <8>[ 20.149557] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11055 22:14:09.404423 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11057 22:14:09.415588 /lava-10583893/1/../bin/lava-test-case
11058 22:14:09.421869 <8>[ 20.167077] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11059 22:14:09.422118 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11061 22:14:09.432805 /lava-10583893/1/../bin/lava-test-case
11062 22:14:09.439289 <8>[ 20.184330] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11063 22:14:09.439538 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11065 22:14:09.450930 /lava-10583893/1/../bin/lava-test-case
11066 22:14:09.457451 <8>[ 20.202824] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11067 22:14:09.457700 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11069 22:14:09.466360 /lava-10583893/1/../bin/lava-test-case
11070 22:14:09.473129 <8>[ 20.217969] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11071 22:14:09.473379 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11073 22:14:09.484006 /lava-10583893/1/../bin/lava-test-case
11074 22:14:09.490769 <8>[ 20.235740] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11075 22:14:09.491018 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11077 22:14:09.501685 /lava-10583893/1/../bin/lava-test-case
11078 22:14:09.508479 <8>[ 20.252994] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11079 22:14:09.508736 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11081 22:14:09.517051 /lava-10583893/1/../bin/lava-test-case
11082 22:14:09.523104 <8>[ 20.268657] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11083 22:14:09.523380 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11085 22:14:09.535627 /lava-10583893/1/../bin/lava-test-case
11086 22:14:09.542163 <8>[ 20.287404] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11087 22:14:09.542418 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11089 22:14:09.551730 /lava-10583893/1/../bin/lava-test-case
11090 22:14:09.557952 <8>[ 20.303617] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11091 22:14:09.558201 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11093 22:14:09.571155 /lava-10583893/1/../bin/lava-test-case
11094 22:14:09.577595 <8>[ 20.323018] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11095 22:14:09.577845 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11097 22:14:09.587164 /lava-10583893/1/../bin/lava-test-case
11098 22:14:09.593871 <8>[ 20.339116] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11099 22:14:09.594147 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11101 22:14:09.606932 /lava-10583893/1/../bin/lava-test-case
11102 22:14:09.613044 <8>[ 20.358317] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11103 22:14:09.613284 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11105 22:14:09.624392 /lava-10583893/1/../bin/lava-test-case
11106 22:14:09.630687 <8>[ 20.376300] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11107 22:14:09.630934 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11109 22:14:09.642704 /lava-10583893/1/../bin/lava-test-case
11110 22:14:09.649166 <8>[ 20.394808] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11111 22:14:09.649440 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11113 22:14:09.660728 /lava-10583893/1/../bin/lava-test-case
11114 22:14:09.667053 <8>[ 20.412677] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11115 22:14:09.667327 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11117 22:14:09.679788 /lava-10583893/1/../bin/lava-test-case
11118 22:14:09.686439 <8>[ 20.431223] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11119 22:14:09.686688 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11121 22:14:09.697988 /lava-10583893/1/../bin/lava-test-case
11122 22:14:09.704560 <8>[ 20.449511] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11123 22:14:09.704807 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11125 22:14:09.716432 /lava-10583893/1/../bin/lava-test-case
11126 22:14:09.722729 <8>[ 20.468142] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11127 22:14:09.723009 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11129 22:14:09.735178 /lava-10583893/1/../bin/lava-test-case
11130 22:14:09.741140 <8>[ 20.486397] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11131 22:14:09.741390 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11133 22:14:09.752905 /lava-10583893/1/../bin/lava-test-case
11134 22:14:09.759569 <8>[ 20.505275] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11135 22:14:09.759843 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11137 22:14:09.772051 /lava-10583893/1/../bin/lava-test-case
11138 22:14:09.778351 <8>[ 20.523913] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11139 22:14:09.778614 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11141 22:14:09.791154 /lava-10583893/1/../bin/lava-test-case
11142 22:14:09.797532 <8>[ 20.542402] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11143 22:14:09.797778 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11145 22:14:09.809261 /lava-10583893/1/../bin/lava-test-case
11146 22:14:09.815728 <8>[ 20.561012] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11147 22:14:09.815997 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11149 22:14:09.827069 /lava-10583893/1/../bin/lava-test-case
11150 22:14:09.833967 <8>[ 20.579530] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11151 22:14:09.834210 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11153 22:14:09.845676 /lava-10583893/1/../bin/lava-test-case
11154 22:14:09.851848 <8>[ 20.597488] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11155 22:14:09.852097 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11157 22:14:09.863706 /lava-10583893/1/../bin/lava-test-case
11158 22:14:09.870478 <8>[ 20.616080] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11159 22:14:09.870742 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11161 22:14:09.880347 /lava-10583893/1/../bin/lava-test-case
11162 22:14:09.886555 <8>[ 20.632108] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11163 22:14:09.886809 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11165 22:14:09.898982 /lava-10583893/1/../bin/lava-test-case
11166 22:14:09.905152 <8>[ 20.650150] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11167 22:14:09.905403 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11169 22:14:09.913537 /lava-10583893/1/../bin/lava-test-case
11170 22:14:09.920470 <8>[ 20.665653] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11171 22:14:09.920720 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11173 22:14:09.932370 /lava-10583893/1/../bin/lava-test-case
11174 22:14:09.938863 <8>[ 20.684141] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11175 22:14:09.939114 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11177 22:14:09.948112 /lava-10583893/1/../bin/lava-test-case
11178 22:14:09.954332 <8>[ 20.699707] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11179 22:14:09.954583 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11181 22:14:09.967220 /lava-10583893/1/../bin/lava-test-case
11182 22:14:09.973574 <8>[ 20.719212] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11183 22:14:09.973826 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11185 22:14:09.984182 /lava-10583893/1/../bin/lava-test-case
11186 22:14:09.990177 <8>[ 20.735648] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11187 22:14:09.990430 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11189 22:14:10.003124 /lava-10583893/1/../bin/lava-test-case
11190 22:14:10.009827 <8>[ 20.754919] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11191 22:14:10.010082 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11193 22:14:10.018987 /lava-10583893/1/../bin/lava-test-case
11194 22:14:10.025629 <8>[ 20.770661] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11195 22:14:10.025882 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11197 22:14:10.037531 /lava-10583893/1/../bin/lava-test-case
11198 22:14:10.044142 <8>[ 20.788983] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11199 22:14:10.044394 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11201 22:14:10.053258 /lava-10583893/1/../bin/lava-test-case
11202 22:14:10.060126 <8>[ 20.804767] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11203 22:14:10.060378 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11205 22:14:10.071638 /lava-10583893/1/../bin/lava-test-case
11206 22:14:10.078321 <8>[ 20.823881] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11207 22:14:10.078588 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11209 22:14:10.090859 /lava-10583893/1/../bin/lava-test-case
11210 22:14:10.097794 <8>[ 20.843046] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11211 22:14:10.098046 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11213 22:14:10.107500 /lava-10583893/1/../bin/lava-test-case
11214 22:14:10.114282 <8>[ 20.859678] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11215 22:14:10.114534 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11217 22:14:10.126741 /lava-10583893/1/../bin/lava-test-case
11218 22:14:10.133160 <8>[ 20.878234] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11219 22:14:10.133412 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11221 22:14:10.142577 /lava-10583893/1/../bin/lava-test-case
11222 22:14:10.148804 <8>[ 20.894479] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11223 22:14:10.149058 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11225 22:14:10.160726 /lava-10583893/1/../bin/lava-test-case
11226 22:14:10.166907 <8>[ 20.912603] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11227 22:14:10.167158 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11229 22:14:10.176256 /lava-10583893/1/../bin/lava-test-case
11230 22:14:10.182770 <8>[ 20.928209] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11231 22:14:10.183022 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11233 22:14:11.197215 /lava-10583893/1/../bin/lava-test-case
11234 22:14:11.203342 <8>[ 21.949879] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11235 22:14:11.203615 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11237 22:14:11.213277 /lava-10583893/1/../bin/lava-test-case
11238 22:14:11.219410 <8>[ 21.965398] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11239 22:14:11.219654 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11241 22:14:12.233088 /lava-10583893/1/../bin/lava-test-case
11242 22:14:12.239716 <8>[ 22.985928] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11243 22:14:12.239981 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11245 22:14:12.249395 /lava-10583893/1/../bin/lava-test-case
11246 22:14:12.256071 <8>[ 23.001766] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11247 22:14:12.256324 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11249 22:14:13.270628 /lava-10583893/1/../bin/lava-test-case
11250 22:14:13.277285 <8>[ 24.023853] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11251 22:14:13.277554 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11253 22:14:13.287633 /lava-10583893/1/../bin/lava-test-case
11254 22:14:13.294434 <8>[ 24.040387] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11255 22:14:13.294718 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11257 22:14:14.308320 /lava-10583893/1/../bin/lava-test-case
11258 22:14:14.315307 <8>[ 25.061479] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11259 22:14:14.315573 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11261 22:14:14.324164 /lava-10583893/1/../bin/lava-test-case
11262 22:14:14.330813 <8>[ 25.077245] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11263 22:14:14.331067 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11265 22:14:15.345103 /lava-10583893/1/../bin/lava-test-case
11266 22:14:15.351856 <8>[ 26.098252] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11267 22:14:15.352579 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11269 22:14:15.361996 /lava-10583893/1/../bin/lava-test-case
11270 22:14:15.368184 <8>[ 26.113433] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11271 22:14:15.368856 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11273 22:14:16.383241 /lava-10583893/1/../bin/lava-test-case
11274 22:14:16.389543 <8>[ 27.135982] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11275 22:14:16.390294 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11277 22:14:16.400050 /lava-10583893/1/../bin/lava-test-case
11278 22:14:16.406428 <8>[ 27.152550] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11279 22:14:16.407283 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11281 22:14:17.420576 /lava-10583893/1/../bin/lava-test-case
11282 22:14:17.427121 <8>[ 28.173985] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11283 22:14:17.427419 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11285 22:14:17.437082 /lava-10583893/1/../bin/lava-test-case
11286 22:14:17.443825 <8>[ 28.189284] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11287 22:14:17.444177 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11289 22:14:17.452718 /lava-10583893/1/../bin/lava-test-case
11290 22:14:17.459541 <8>[ 28.204926] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11291 22:14:17.459989 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11293 22:14:18.473990 /lava-10583893/1/../bin/lava-test-case
11294 22:14:18.479825 <8>[ 29.226187] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11295 22:14:18.480626 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11297 22:14:18.490373 /lava-10583893/1/../bin/lava-test-case
11298 22:14:18.496814 <8>[ 29.243233] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11299 22:14:18.497545 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11301 22:14:18.509315 /lava-10583893/1/../bin/lava-test-case
11302 22:14:18.516046 <8>[ 29.261974] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11303 22:14:18.516774 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11305 22:14:18.525905 /lava-10583893/1/../bin/lava-test-case
11306 22:14:18.532235 <8>[ 29.278176] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11307 22:14:18.533090 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11309 22:14:18.544743 /lava-10583893/1/../bin/lava-test-case
11310 22:14:18.551127 <8>[ 29.296851] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11311 22:14:18.552002 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11313 22:14:18.563141 /lava-10583893/1/../bin/lava-test-case
11314 22:14:18.569385 <8>[ 29.315072] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11315 22:14:18.570236 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11317 22:14:18.581414 /lava-10583893/1/../bin/lava-test-case
11318 22:14:18.587879 <8>[ 29.333506] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11319 22:14:18.588625 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11321 22:14:18.597859 /lava-10583893/1/../bin/lava-test-case
11322 22:14:18.604445 <8>[ 29.349684] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11323 22:14:18.605277 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11325 22:14:18.616329 /lava-10583893/1/../bin/lava-test-case
11326 22:14:18.623474 <8>[ 29.369030] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11327 22:14:18.624304 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11329 22:14:18.635092 /lava-10583893/1/../bin/lava-test-case
11330 22:14:18.641435 <8>[ 29.387624] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11331 22:14:18.642271 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11333 22:14:18.651594 /lava-10583893/1/../bin/lava-test-case
11334 22:14:18.658266 <8>[ 29.404159] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11335 22:14:18.659126 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11337 22:14:18.671317 /lava-10583893/1/../bin/lava-test-case
11338 22:14:18.677355 <8>[ 29.423453] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11339 22:14:18.678188 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11341 22:14:18.687320 /lava-10583893/1/../bin/lava-test-case
11342 22:14:18.693762 <8>[ 29.439733] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11343 22:14:18.694615 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11345 22:14:18.706607 /lava-10583893/1/../bin/lava-test-case
11346 22:14:18.713477 <8>[ 29.459657] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11347 22:14:18.714249 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11349 22:14:18.723454 /lava-10583893/1/../bin/lava-test-case
11350 22:14:18.730381 <8>[ 29.476110] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11351 22:14:18.731214 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11353 22:14:18.742981 /lava-10583893/1/../bin/lava-test-case
11354 22:14:18.749437 <8>[ 29.495593] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11355 22:14:18.750248 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11357 22:14:18.759811 /lava-10583893/1/../bin/lava-test-case
11358 22:14:18.766112 <8>[ 29.512333] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11359 22:14:18.766946 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11361 22:14:18.779690 /lava-10583893/1/../bin/lava-test-case
11362 22:14:18.785802 <8>[ 29.532218] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11363 22:14:18.786531 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11365 22:14:18.796280 /lava-10583893/1/../bin/lava-test-case
11366 22:14:18.802884 <8>[ 29.548963] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11367 22:14:18.803854 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11369 22:14:18.815756 /lava-10583893/1/../bin/lava-test-case
11370 22:14:18.821724 <8>[ 29.567790] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11371 22:14:18.822562 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11373 22:14:18.831135 /lava-10583893/1/../bin/lava-test-case
11374 22:14:18.837660 <8>[ 29.583612] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11375 22:14:18.838500 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11377 22:14:19.851900 /lava-10583893/1/../bin/lava-test-case
11378 22:14:19.858632 <8>[ 30.605568] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11379 22:14:19.859425 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11381 22:14:20.872765 /lava-10583893/1/../bin/lava-test-case
11382 22:14:20.879007 <8>[ 31.625758] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11383 22:14:20.879267 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11385 22:14:20.888202 /lava-10583893/1/../bin/lava-test-case
11386 22:14:20.895121 <8>[ 31.641477] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11387 22:14:20.895431 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11389 22:14:20.906383 /lava-10583893/1/../bin/lava-test-case
11390 22:14:20.912989 <8>[ 31.659338] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11391 22:14:20.913243 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11393 22:14:20.921612 /lava-10583893/1/../bin/lava-test-case
11394 22:14:20.928147 <8>[ 31.674682] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11395 22:14:20.928435 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11397 22:14:20.941323 /lava-10583893/1/../bin/lava-test-case
11398 22:14:20.947097 <8>[ 31.693594] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11399 22:14:20.947483 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11401 22:14:20.956770 /lava-10583893/1/../bin/lava-test-case
11402 22:14:20.963201 <8>[ 31.709378] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11403 22:14:20.963659 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11405 22:14:20.974127 /lava-10583893/1/../bin/lava-test-case
11406 22:14:20.980924 <8>[ 31.727108] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11407 22:14:20.981701 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11409 22:14:20.990105 /lava-10583893/1/../bin/lava-test-case
11410 22:14:20.996355 <8>[ 31.741922] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11411 22:14:20.996846 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11413 22:14:21.007675 /lava-10583893/1/../bin/lava-test-case
11414 22:14:21.014436 <8>[ 31.761054] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11415 22:14:21.014780 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11417 22:14:21.023829 /lava-10583893/1/../bin/lava-test-case
11418 22:14:21.030232 <8>[ 31.776770] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11419 22:14:21.030501 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11421 22:14:21.042023 /lava-10583893/1/../bin/lava-test-case
11422 22:14:21.048715 <8>[ 31.795204] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11423 22:14:21.048975 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11425 22:14:21.057405 /lava-10583893/1/../bin/lava-test-case
11426 22:14:21.064025 <8>[ 31.810528] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11427 22:14:21.064315 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11429 22:14:21.075888 /lava-10583893/1/../bin/lava-test-case
11430 22:14:21.082541 <8>[ 31.828977] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11431 22:14:21.082859 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11433 22:14:21.091346 /lava-10583893/1/../bin/lava-test-case
11434 22:14:21.098105 <8>[ 31.844580] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11435 22:14:21.098357 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11437 22:14:21.110046 /lava-10583893/1/../bin/lava-test-case
11438 22:14:21.116643 <8>[ 31.863125] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11439 22:14:21.116897 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11441 22:14:21.125444 /lava-10583893/1/../bin/lava-test-case
11442 22:14:21.132092 <8>[ 31.878997] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11443 22:14:21.132344 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11445 22:14:21.144176 /lava-10583893/1/../bin/lava-test-case
11446 22:14:21.150847 <8>[ 31.896961] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11447 22:14:21.151099 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11449 22:14:21.159297 /lava-10583893/1/../bin/lava-test-case
11450 22:14:21.166452 <8>[ 31.912311] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11451 22:14:21.166705 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11453 22:14:21.178237 /lava-10583893/1/../bin/lava-test-case
11454 22:14:21.184370 <8>[ 31.930894] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11455 22:14:21.184623 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11457 22:14:21.193824 /lava-10583893/1/../bin/lava-test-case
11458 22:14:21.199606 <8>[ 31.945934] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11459 22:14:21.199858 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11461 22:14:21.212006 /lava-10583893/1/../bin/lava-test-case
11462 22:14:21.218695 <8>[ 31.965119] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11463 22:14:21.218949 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11465 22:14:22.229921 /lava-10583893/1/../bin/lava-test-case
11466 22:14:22.236686 <8>[ 32.983186] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11467 22:14:22.237517 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11469 22:14:23.249142 /lava-10583893/1/../bin/lava-test-case
11470 22:14:23.255665 <8>[ 34.003284] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11471 22:14:23.256627 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11472 22:14:23.257227 Bad test result: blocked
11473 22:14:23.266784 /lava-10583893/1/../bin/lava-test-case
11474 22:14:23.273134 <8>[ 34.019679] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11475 22:14:23.273970 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11477 22:14:24.286610 /lava-10583893/1/../bin/lava-test-case
11478 22:14:24.293644 <8>[ 35.040575] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11479 22:14:24.294477 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11481 22:14:24.303392 /lava-10583893/1/../bin/lava-test-case
11482 22:14:24.309910 <8>[ 35.056356] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11483 22:14:24.310733 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11485 22:14:24.321970 /lava-10583893/1/../bin/lava-test-case
11486 22:14:24.328327 <8>[ 35.074356] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11487 22:14:24.329149 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11489 22:14:24.338388 /lava-10583893/1/../bin/lava-test-case
11490 22:14:24.344970 <8>[ 35.091243] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11491 22:14:24.345796 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11493 22:14:24.354207 /lava-10583893/1/../bin/lava-test-case
11494 22:14:24.360831 <8>[ 35.107213] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11495 22:14:24.361565 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11497 22:14:24.372600 /lava-10583893/1/../bin/lava-test-case
11498 22:14:24.378523 <8>[ 35.125326] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11499 22:14:24.379276 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11501 22:14:24.388365 /lava-10583893/1/../bin/lava-test-case
11502 22:14:24.395274 <8>[ 35.141180] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11503 22:14:24.396112 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11505 22:14:25.408375 /lava-10583893/1/../bin/lava-test-case
11506 22:14:25.414737 <8>[ 36.161986] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11507 22:14:25.415604 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11509 22:14:25.424570 /lava-10583893/1/../bin/lava-test-case
11510 22:14:25.430868 <8>[ 36.177664] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11511 22:14:25.431758 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11513 22:14:26.444412 /lava-10583893/1/../bin/lava-test-case
11514 22:14:26.450045 <8>[ 37.197481] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11515 22:14:26.450337 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11517 22:14:26.459642 /lava-10583893/1/../bin/lava-test-case
11518 22:14:26.466679 <8>[ 37.213265] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11519 22:14:26.467041 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11521 22:14:27.480467 /lava-10583893/1/../bin/lava-test-case
11522 22:14:27.487533 <8>[ 38.233939] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11523 22:14:27.488398 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11525 22:14:27.496544 /lava-10583893/1/../bin/lava-test-case
11526 22:14:27.503202 <8>[ 38.249722] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11527 22:14:27.504074 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11529 22:14:28.516998 /lava-10583893/1/../bin/lava-test-case
11530 22:14:28.522957 <8>[ 39.270847] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11531 22:14:28.523888 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11533 22:14:28.533741 /lava-10583893/1/../bin/lava-test-case
11534 22:14:28.540491 <8>[ 39.286921] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11535 22:14:28.541332 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11537 22:14:28.551899 /lava-10583893/1/../bin/lava-test-case
11538 22:14:28.558629 <8>[ 39.304537] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11539 22:14:28.559496 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11541 22:14:28.569038 /lava-10583893/1/../bin/lava-test-case
11542 22:14:28.575551 <8>[ 39.322014] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11543 22:14:28.576385 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11545 22:14:28.584313 /lava-10583893/1/../bin/lava-test-case
11546 22:14:28.590881 <8>[ 39.337301] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11547 22:14:28.591783 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11549 22:14:28.601295 /lava-10583893/1/../bin/lava-test-case
11550 22:14:28.607856 <8>[ 39.354983] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11551 22:14:28.608676 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11553 22:14:28.616589 /lava-10583893/1/../bin/lava-test-case
11554 22:14:28.624060 <8>[ 39.369973] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11555 22:14:28.624899 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11557 22:14:28.635069 /lava-10583893/1/../bin/lava-test-case
11558 22:14:28.641938 <8>[ 39.388161] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11559 22:14:28.642788 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11561 22:14:28.651316 /lava-10583893/1/../bin/lava-test-case
11562 22:14:28.657402 <8>[ 39.404293] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11563 22:14:28.658242 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11565 22:14:29.671476 /lava-10583893/1/../bin/lava-test-case
11566 22:14:29.678591 <8>[ 40.425726] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=fail>
11567 22:14:29.679475 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=fail
11569 22:14:29.682553 + set +x
11570 22:14:29.686054 Received signal: <ENDRUN> 1_bootrr 10583893_1.5.2.3.5
11571 22:14:29.686631 Ending use of test pattern.
11572 22:14:29.687007 Ending test lava.1_bootrr (10583893_1.5.2.3.5), duration 23.30
11574 22:14:29.689023 <8>[ 40.435825] <LAVA_SIGNAL_ENDRUN 1_bootrr 10583893_1.5.2.3.5>
11575 22:14:29.689486 <LAVA_TEST_RUNNER EXIT>
11576 22:14:29.690087 ok: lava_test_shell seems to have completed
11577 22:14:29.695765 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: fail
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: fail
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: pass
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11578 22:14:29.696549 end: 4.1 lava-test-shell (duration 00:00:24) [common]
11579 22:14:29.697028 end: 4 lava-test-retry (duration 00:00:24) [common]
11580 22:14:29.697512 start: 5 finalize (timeout 00:07:42) [common]
11581 22:14:29.697999 start: 5.1 power-off (timeout 00:00:30) [common]
11582 22:14:29.698839 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
11583 22:14:29.784295 >> Command sent successfully.
11584 22:14:29.789010 Returned 0 in 0 seconds
11585 22:14:29.890030 end: 5.1 power-off (duration 00:00:00) [common]
11587 22:14:29.891656 start: 5.2 read-feedback (timeout 00:07:42) [common]
11588 22:14:29.892914 Listened to connection for namespace 'common' for up to 1s
11589 22:14:29.893911 Listened to connection for namespace 'common' for up to 1s
11590 22:14:30.893524 Finalising connection for namespace 'common'
11591 22:14:30.894215 Disconnecting from shell: Finalise
11592 22:14:30.894644 / #
11593 22:14:30.995783 end: 5.2 read-feedback (duration 00:00:01) [common]
11594 22:14:30.996523 end: 5 finalize (duration 00:00:01) [common]
11595 22:14:30.997109 Cleaning after the job
11596 22:14:30.997651 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583893/tftp-deploy-arhndd4y/ramdisk
11597 22:14:31.008176 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583893/tftp-deploy-arhndd4y/kernel
11598 22:14:31.030331 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583893/tftp-deploy-arhndd4y/dtb
11599 22:14:31.030745 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583893/tftp-deploy-arhndd4y/modules
11600 22:14:31.041080 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10583893
11601 22:14:31.082409 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10583893
11602 22:14:31.082592 Job finished correctly