Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 39
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 30
1 22:15:48.182833 lava-dispatcher, installed at version: 2023.03
2 22:15:48.183035 start: 0 validate
3 22:15:48.183167 Start time: 2023-06-04 22:15:48.183159+00:00 (UTC)
4 22:15:48.183284 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:15:48.183410 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
6 22:15:48.510259 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:15:48.511055 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1281-g84d5372e0f314%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:15:48.801651 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:15:48.802446 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1281-g84d5372e0f314%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:15:49.094158 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:15:49.094955 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 22:15:49.390695 Using caching service: 'http://localhost/cache/?uri=%s'
13 22:15:49.391487 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1281-g84d5372e0f314%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 22:15:49.684380 validate duration: 1.50
16 22:15:49.685658 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 22:15:49.686327 start: 1.1 download-retry (timeout 00:10:00) [common]
18 22:15:49.686941 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 22:15:49.687611 Not decompressing ramdisk as can be used compressed.
20 22:15:49.688110 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/initrd.cpio.gz
21 22:15:49.688481 saving as /var/lib/lava/dispatcher/tmp/10583921/tftp-deploy-y7em0uqj/ramdisk/initrd.cpio.gz
22 22:15:49.688836 total size: 4665601 (4MB)
23 22:15:49.694813 progress 0% (0MB)
24 22:15:49.703312 progress 5% (0MB)
25 22:15:49.709894 progress 10% (0MB)
26 22:15:49.714447 progress 15% (0MB)
27 22:15:49.717958 progress 20% (0MB)
28 22:15:49.720968 progress 25% (1MB)
29 22:15:49.723779 progress 30% (1MB)
30 22:15:49.726106 progress 35% (1MB)
31 22:15:49.728443 progress 40% (1MB)
32 22:15:49.730760 progress 45% (2MB)
33 22:15:49.732771 progress 50% (2MB)
34 22:15:49.734635 progress 55% (2MB)
35 22:15:49.736638 progress 60% (2MB)
36 22:15:49.738407 progress 65% (2MB)
37 22:15:49.740253 progress 70% (3MB)
38 22:15:49.741836 progress 75% (3MB)
39 22:15:49.743396 progress 80% (3MB)
40 22:15:49.745037 progress 85% (3MB)
41 22:15:49.746431 progress 90% (4MB)
42 22:15:49.747853 progress 95% (4MB)
43 22:15:49.749222 progress 100% (4MB)
44 22:15:49.749380 4MB downloaded in 0.06s (73.49MB/s)
45 22:15:49.749530 end: 1.1.1 http-download (duration 00:00:00) [common]
47 22:15:49.749776 end: 1.1 download-retry (duration 00:00:00) [common]
48 22:15:49.749868 start: 1.2 download-retry (timeout 00:10:00) [common]
49 22:15:49.749956 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 22:15:49.750079 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1281-g84d5372e0f314/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 22:15:49.750154 saving as /var/lib/lava/dispatcher/tmp/10583921/tftp-deploy-y7em0uqj/kernel/Image
52 22:15:49.750217 total size: 45746688 (43MB)
53 22:15:49.750279 No compression specified
54 22:15:49.751499 progress 0% (0MB)
55 22:15:49.763192 progress 5% (2MB)
56 22:15:49.774511 progress 10% (4MB)
57 22:15:49.785802 progress 15% (6MB)
58 22:15:49.797312 progress 20% (8MB)
59 22:15:49.808846 progress 25% (10MB)
60 22:15:49.820176 progress 30% (13MB)
61 22:15:49.831580 progress 35% (15MB)
62 22:15:49.843044 progress 40% (17MB)
63 22:15:49.854499 progress 45% (19MB)
64 22:15:49.865940 progress 50% (21MB)
65 22:15:49.877158 progress 55% (24MB)
66 22:15:49.888471 progress 60% (26MB)
67 22:15:49.899963 progress 65% (28MB)
68 22:15:49.911317 progress 70% (30MB)
69 22:15:49.922948 progress 75% (32MB)
70 22:15:49.934298 progress 80% (34MB)
71 22:15:49.945693 progress 85% (37MB)
72 22:15:49.957119 progress 90% (39MB)
73 22:15:49.968352 progress 95% (41MB)
74 22:15:49.979454 progress 100% (43MB)
75 22:15:49.979575 43MB downloaded in 0.23s (190.22MB/s)
76 22:15:49.979762 end: 1.2.1 http-download (duration 00:00:00) [common]
78 22:15:49.979989 end: 1.2 download-retry (duration 00:00:00) [common]
79 22:15:49.980075 start: 1.3 download-retry (timeout 00:10:00) [common]
80 22:15:49.980165 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 22:15:49.980298 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1281-g84d5372e0f314/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 22:15:49.980368 saving as /var/lib/lava/dispatcher/tmp/10583921/tftp-deploy-y7em0uqj/dtb/mt8192-asurada-spherion-r0.dtb
83 22:15:49.980428 total size: 46924 (0MB)
84 22:15:49.980487 No compression specified
85 22:15:49.981517 progress 69% (0MB)
86 22:15:49.981778 progress 100% (0MB)
87 22:15:49.981926 0MB downloaded in 0.00s (29.93MB/s)
88 22:15:49.982043 end: 1.3.1 http-download (duration 00:00:00) [common]
90 22:15:49.982263 end: 1.3 download-retry (duration 00:00:00) [common]
91 22:15:49.982348 start: 1.4 download-retry (timeout 00:10:00) [common]
92 22:15:49.982429 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 22:15:49.982533 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/full.rootfs.tar.xz
94 22:15:49.982600 saving as /var/lib/lava/dispatcher/tmp/10583921/tftp-deploy-y7em0uqj/nfsrootfs/full.rootfs.tar
95 22:15:49.982661 total size: 200770336 (191MB)
96 22:15:49.982719 Using unxz to decompress xz
97 22:15:49.986407 progress 0% (0MB)
98 22:15:50.503885 progress 5% (9MB)
99 22:15:51.008468 progress 10% (19MB)
100 22:15:51.577351 progress 15% (28MB)
101 22:15:51.935312 progress 20% (38MB)
102 22:15:52.252663 progress 25% (47MB)
103 22:15:52.831930 progress 30% (57MB)
104 22:15:53.367659 progress 35% (67MB)
105 22:15:53.944843 progress 40% (76MB)
106 22:15:54.490914 progress 45% (86MB)
107 22:15:55.059516 progress 50% (95MB)
108 22:15:55.669002 progress 55% (105MB)
109 22:15:56.304870 progress 60% (114MB)
110 22:15:56.420272 progress 65% (124MB)
111 22:15:56.557999 progress 70% (134MB)
112 22:15:56.652168 progress 75% (143MB)
113 22:15:56.725019 progress 80% (153MB)
114 22:15:56.792582 progress 85% (162MB)
115 22:15:56.889168 progress 90% (172MB)
116 22:15:57.159473 progress 95% (181MB)
117 22:15:57.736300 progress 100% (191MB)
118 22:15:57.740954 191MB downloaded in 7.76s (24.68MB/s)
119 22:15:57.741267 end: 1.4.1 http-download (duration 00:00:08) [common]
121 22:15:57.741538 end: 1.4 download-retry (duration 00:00:08) [common]
122 22:15:57.741631 start: 1.5 download-retry (timeout 00:09:52) [common]
123 22:15:57.741732 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 22:15:57.741924 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1281-g84d5372e0f314/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 22:15:57.742035 saving as /var/lib/lava/dispatcher/tmp/10583921/tftp-deploy-y7em0uqj/modules/modules.tar
126 22:15:57.742133 total size: 8541948 (8MB)
127 22:15:57.742232 Using unxz to decompress xz
128 22:15:57.746075 progress 0% (0MB)
129 22:15:57.767918 progress 5% (0MB)
130 22:15:57.792917 progress 10% (0MB)
131 22:15:57.818051 progress 15% (1MB)
132 22:15:57.842530 progress 20% (1MB)
133 22:15:57.866551 progress 25% (2MB)
134 22:15:57.896002 progress 30% (2MB)
135 22:15:57.920578 progress 35% (2MB)
136 22:15:57.945138 progress 40% (3MB)
137 22:15:57.970753 progress 45% (3MB)
138 22:15:57.998550 progress 50% (4MB)
139 22:15:58.022763 progress 55% (4MB)
140 22:15:58.048161 progress 60% (4MB)
141 22:15:58.073682 progress 65% (5MB)
142 22:15:58.098171 progress 70% (5MB)
143 22:15:58.121604 progress 75% (6MB)
144 22:15:58.145350 progress 80% (6MB)
145 22:15:58.170325 progress 85% (6MB)
146 22:15:58.199259 progress 90% (7MB)
147 22:15:58.225377 progress 95% (7MB)
148 22:15:58.249436 progress 100% (8MB)
149 22:15:58.255286 8MB downloaded in 0.51s (15.88MB/s)
150 22:15:58.255580 end: 1.5.1 http-download (duration 00:00:01) [common]
152 22:15:58.255866 end: 1.5 download-retry (duration 00:00:01) [common]
153 22:15:58.255963 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 22:15:58.256061 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 22:16:01.501598 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10583921/extract-nfsrootfs-dpv56toy
156 22:16:01.501810 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 22:16:01.501920 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 22:16:01.502081 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10583921/lava-overlay-vk0dx_io
159 22:16:01.502203 makedir: /var/lib/lava/dispatcher/tmp/10583921/lava-overlay-vk0dx_io/lava-10583921/bin
160 22:16:01.502300 makedir: /var/lib/lava/dispatcher/tmp/10583921/lava-overlay-vk0dx_io/lava-10583921/tests
161 22:16:01.502393 makedir: /var/lib/lava/dispatcher/tmp/10583921/lava-overlay-vk0dx_io/lava-10583921/results
162 22:16:01.502492 Creating /var/lib/lava/dispatcher/tmp/10583921/lava-overlay-vk0dx_io/lava-10583921/bin/lava-add-keys
163 22:16:01.502631 Creating /var/lib/lava/dispatcher/tmp/10583921/lava-overlay-vk0dx_io/lava-10583921/bin/lava-add-sources
164 22:16:01.502756 Creating /var/lib/lava/dispatcher/tmp/10583921/lava-overlay-vk0dx_io/lava-10583921/bin/lava-background-process-start
165 22:16:01.502878 Creating /var/lib/lava/dispatcher/tmp/10583921/lava-overlay-vk0dx_io/lava-10583921/bin/lava-background-process-stop
166 22:16:01.502999 Creating /var/lib/lava/dispatcher/tmp/10583921/lava-overlay-vk0dx_io/lava-10583921/bin/lava-common-functions
167 22:16:01.503118 Creating /var/lib/lava/dispatcher/tmp/10583921/lava-overlay-vk0dx_io/lava-10583921/bin/lava-echo-ipv4
168 22:16:01.503238 Creating /var/lib/lava/dispatcher/tmp/10583921/lava-overlay-vk0dx_io/lava-10583921/bin/lava-install-packages
169 22:16:01.503356 Creating /var/lib/lava/dispatcher/tmp/10583921/lava-overlay-vk0dx_io/lava-10583921/bin/lava-installed-packages
170 22:16:01.503475 Creating /var/lib/lava/dispatcher/tmp/10583921/lava-overlay-vk0dx_io/lava-10583921/bin/lava-os-build
171 22:16:01.503773 Creating /var/lib/lava/dispatcher/tmp/10583921/lava-overlay-vk0dx_io/lava-10583921/bin/lava-probe-channel
172 22:16:01.503897 Creating /var/lib/lava/dispatcher/tmp/10583921/lava-overlay-vk0dx_io/lava-10583921/bin/lava-probe-ip
173 22:16:01.504017 Creating /var/lib/lava/dispatcher/tmp/10583921/lava-overlay-vk0dx_io/lava-10583921/bin/lava-target-ip
174 22:16:01.504136 Creating /var/lib/lava/dispatcher/tmp/10583921/lava-overlay-vk0dx_io/lava-10583921/bin/lava-target-mac
175 22:16:01.504255 Creating /var/lib/lava/dispatcher/tmp/10583921/lava-overlay-vk0dx_io/lava-10583921/bin/lava-target-storage
176 22:16:01.504376 Creating /var/lib/lava/dispatcher/tmp/10583921/lava-overlay-vk0dx_io/lava-10583921/bin/lava-test-case
177 22:16:01.504496 Creating /var/lib/lava/dispatcher/tmp/10583921/lava-overlay-vk0dx_io/lava-10583921/bin/lava-test-event
178 22:16:01.504613 Creating /var/lib/lava/dispatcher/tmp/10583921/lava-overlay-vk0dx_io/lava-10583921/bin/lava-test-feedback
179 22:16:01.504732 Creating /var/lib/lava/dispatcher/tmp/10583921/lava-overlay-vk0dx_io/lava-10583921/bin/lava-test-raise
180 22:16:01.504849 Creating /var/lib/lava/dispatcher/tmp/10583921/lava-overlay-vk0dx_io/lava-10583921/bin/lava-test-reference
181 22:16:01.504968 Creating /var/lib/lava/dispatcher/tmp/10583921/lava-overlay-vk0dx_io/lava-10583921/bin/lava-test-runner
182 22:16:01.505097 Creating /var/lib/lava/dispatcher/tmp/10583921/lava-overlay-vk0dx_io/lava-10583921/bin/lava-test-set
183 22:16:01.505226 Creating /var/lib/lava/dispatcher/tmp/10583921/lava-overlay-vk0dx_io/lava-10583921/bin/lava-test-shell
184 22:16:01.505351 Updating /var/lib/lava/dispatcher/tmp/10583921/lava-overlay-vk0dx_io/lava-10583921/bin/lava-add-keys (debian)
185 22:16:01.505500 Updating /var/lib/lava/dispatcher/tmp/10583921/lava-overlay-vk0dx_io/lava-10583921/bin/lava-add-sources (debian)
186 22:16:01.505642 Updating /var/lib/lava/dispatcher/tmp/10583921/lava-overlay-vk0dx_io/lava-10583921/bin/lava-install-packages (debian)
187 22:16:01.505784 Updating /var/lib/lava/dispatcher/tmp/10583921/lava-overlay-vk0dx_io/lava-10583921/bin/lava-installed-packages (debian)
188 22:16:01.505916 Updating /var/lib/lava/dispatcher/tmp/10583921/lava-overlay-vk0dx_io/lava-10583921/bin/lava-os-build (debian)
189 22:16:01.506035 Creating /var/lib/lava/dispatcher/tmp/10583921/lava-overlay-vk0dx_io/lava-10583921/environment
190 22:16:01.506131 LAVA metadata
191 22:16:01.506199 - LAVA_JOB_ID=10583921
192 22:16:01.506262 - LAVA_DISPATCHER_IP=192.168.201.1
193 22:16:01.506358 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 22:16:01.506424 skipped lava-vland-overlay
195 22:16:01.506497 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 22:16:01.506575 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 22:16:01.506635 skipped lava-multinode-overlay
198 22:16:01.506705 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 22:16:01.506781 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 22:16:01.506851 Loading test definitions
201 22:16:01.506938 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 22:16:01.507017 Using /lava-10583921 at stage 0
203 22:16:01.507282 uuid=10583921_1.6.2.3.1 testdef=None
204 22:16:01.507368 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 22:16:01.507451 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 22:16:01.507944 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 22:16:01.508161 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 22:16:01.508697 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 22:16:01.508928 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 22:16:01.509506 runner path: /var/lib/lava/dispatcher/tmp/10583921/lava-overlay-vk0dx_io/lava-10583921/0/tests/0_timesync-off test_uuid 10583921_1.6.2.3.1
213 22:16:01.509655 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 22:16:01.509876 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 22:16:01.509947 Using /lava-10583921 at stage 0
217 22:16:01.510045 Fetching tests from https://github.com/kernelci/test-definitions.git
218 22:16:01.510120 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/10583921/lava-overlay-vk0dx_io/lava-10583921/0/tests/1_kselftest-rtc'
219 22:16:04.330230 Running '/usr/bin/git checkout kernelci.org
220 22:16:04.473698 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10583921/lava-overlay-vk0dx_io/lava-10583921/0/tests/1_kselftest-rtc/automated/linux/kselftest/kselftest.yaml
221 22:16:04.474427 uuid=10583921_1.6.2.3.5 testdef=None
222 22:16:04.474593 end: 1.6.2.3.5 git-repo-action (duration 00:00:03) [common]
224 22:16:04.474853 start: 1.6.2.3.6 test-overlay (timeout 00:09:45) [common]
225 22:16:04.475624 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 22:16:04.476031 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:45) [common]
228 22:16:04.477041 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 22:16:04.477280 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:45) [common]
231 22:16:04.478213 runner path: /var/lib/lava/dispatcher/tmp/10583921/lava-overlay-vk0dx_io/lava-10583921/0/tests/1_kselftest-rtc test_uuid 10583921_1.6.2.3.5
232 22:16:04.478305 BOARD='mt8192-asurada-spherion-r0'
233 22:16:04.478371 BRANCH='cip'
234 22:16:04.478432 SKIPFILE='/dev/null'
235 22:16:04.478491 SKIP_INSTALL='True'
236 22:16:04.478549 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1281-g84d5372e0f314/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 22:16:04.478607 TST_CASENAME=''
238 22:16:04.478663 TST_CMDFILES='rtc'
239 22:16:04.478802 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 22:16:04.479013 Creating lava-test-runner.conf files
242 22:16:04.479079 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10583921/lava-overlay-vk0dx_io/lava-10583921/0 for stage 0
243 22:16:04.479171 - 0_timesync-off
244 22:16:04.479243 - 1_kselftest-rtc
245 22:16:04.479337 end: 1.6.2.3 test-definition (duration 00:00:03) [common]
246 22:16:04.479426 start: 1.6.2.4 compress-overlay (timeout 00:09:45) [common]
247 22:16:11.995823 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 22:16:11.995985 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:38) [common]
249 22:16:11.996078 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 22:16:11.996184 end: 1.6.2 lava-overlay (duration 00:00:10) [common]
251 22:16:11.996275 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:38) [common]
252 22:16:12.110607 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 22:16:12.110979 start: 1.6.4 extract-modules (timeout 00:09:38) [common]
254 22:16:12.111098 extracting modules file /var/lib/lava/dispatcher/tmp/10583921/tftp-deploy-y7em0uqj/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10583921/extract-nfsrootfs-dpv56toy
255 22:16:12.315479 extracting modules file /var/lib/lava/dispatcher/tmp/10583921/tftp-deploy-y7em0uqj/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10583921/extract-overlay-ramdisk-4_l4lwzu/ramdisk
256 22:16:12.532827 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 22:16:12.533015 start: 1.6.5 apply-overlay-tftp (timeout 00:09:37) [common]
258 22:16:12.533110 [common] Applying overlay to NFS
259 22:16:12.533180 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10583921/compress-overlay-3ryej5vo/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10583921/extract-nfsrootfs-dpv56toy
260 22:16:13.430906 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 22:16:13.431084 start: 1.6.6 configure-preseed-file (timeout 00:09:36) [common]
262 22:16:13.431185 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 22:16:13.431278 start: 1.6.7 compress-ramdisk (timeout 00:09:36) [common]
264 22:16:13.431365 Building ramdisk /var/lib/lava/dispatcher/tmp/10583921/extract-overlay-ramdisk-4_l4lwzu/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10583921/extract-overlay-ramdisk-4_l4lwzu/ramdisk
265 22:16:13.701725 >> 117799 blocks
266 22:16:15.610473 rename /var/lib/lava/dispatcher/tmp/10583921/extract-overlay-ramdisk-4_l4lwzu/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10583921/tftp-deploy-y7em0uqj/ramdisk/ramdisk.cpio.gz
267 22:16:15.610903 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 22:16:15.611030 start: 1.6.8 prepare-kernel (timeout 00:09:34) [common]
269 22:16:15.611127 start: 1.6.8.1 prepare-fit (timeout 00:09:34) [common]
270 22:16:15.611233 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10583921/tftp-deploy-y7em0uqj/kernel/Image'
271 22:16:27.125147 Returned 0 in 11 seconds
272 22:16:27.225778 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10583921/tftp-deploy-y7em0uqj/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10583921/tftp-deploy-y7em0uqj/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10583921/tftp-deploy-y7em0uqj/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10583921/tftp-deploy-y7em0uqj/kernel/image.itb
273 22:16:27.536990 output: FIT description: Kernel Image image with one or more FDT blobs
274 22:16:27.537352 output: Created: Sun Jun 4 23:16:27 2023
275 22:16:27.537430 output: Image 0 (kernel-1)
276 22:16:27.537501 output: Description:
277 22:16:27.537566 output: Created: Sun Jun 4 23:16:27 2023
278 22:16:27.537628 output: Type: Kernel Image
279 22:16:27.537689 output: Compression: lzma compressed
280 22:16:27.537751 output: Data Size: 10081729 Bytes = 9845.44 KiB = 9.61 MiB
281 22:16:27.537813 output: Architecture: AArch64
282 22:16:27.537872 output: OS: Linux
283 22:16:27.537931 output: Load Address: 0x00000000
284 22:16:27.537989 output: Entry Point: 0x00000000
285 22:16:27.538048 output: Hash algo: crc32
286 22:16:27.538104 output: Hash value: 3b3111d8
287 22:16:27.538159 output: Image 1 (fdt-1)
288 22:16:27.538213 output: Description: mt8192-asurada-spherion-r0
289 22:16:27.538267 output: Created: Sun Jun 4 23:16:27 2023
290 22:16:27.538321 output: Type: Flat Device Tree
291 22:16:27.538376 output: Compression: uncompressed
292 22:16:27.538430 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
293 22:16:27.538485 output: Architecture: AArch64
294 22:16:27.538538 output: Hash algo: crc32
295 22:16:27.538593 output: Hash value: 1df858fa
296 22:16:27.538647 output: Image 2 (ramdisk-1)
297 22:16:27.538701 output: Description: unavailable
298 22:16:27.538755 output: Created: Sun Jun 4 23:16:27 2023
299 22:16:27.538809 output: Type: RAMDisk Image
300 22:16:27.538873 output: Compression: Unknown Compression
301 22:16:27.538931 output: Data Size: 17643081 Bytes = 17229.57 KiB = 16.83 MiB
302 22:16:27.538986 output: Architecture: AArch64
303 22:16:27.539040 output: OS: Linux
304 22:16:27.539094 output: Load Address: unavailable
305 22:16:27.539149 output: Entry Point: unavailable
306 22:16:27.539203 output: Hash algo: crc32
307 22:16:27.539257 output: Hash value: 827dab09
308 22:16:27.539312 output: Default Configuration: 'conf-1'
309 22:16:27.539366 output: Configuration 0 (conf-1)
310 22:16:27.539420 output: Description: mt8192-asurada-spherion-r0
311 22:16:27.539474 output: Kernel: kernel-1
312 22:16:27.539527 output: Init Ramdisk: ramdisk-1
313 22:16:27.539586 output: FDT: fdt-1
314 22:16:27.539675 output: Loadables: kernel-1
315 22:16:27.539728 output:
316 22:16:27.539919 end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
317 22:16:27.540018 end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
318 22:16:27.540126 end: 1.6 prepare-tftp-overlay (duration 00:00:29) [common]
319 22:16:27.540224 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:22) [common]
320 22:16:27.540303 No LXC device requested
321 22:16:27.540385 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 22:16:27.540472 start: 1.8 deploy-device-env (timeout 00:09:22) [common]
323 22:16:27.540552 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 22:16:27.540623 Checking files for TFTP limit of 4294967296 bytes.
325 22:16:27.541133 end: 1 tftp-deploy (duration 00:00:38) [common]
326 22:16:27.541246 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 22:16:27.541339 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 22:16:27.541467 substitutions:
329 22:16:27.541537 - {DTB}: 10583921/tftp-deploy-y7em0uqj/dtb/mt8192-asurada-spherion-r0.dtb
330 22:16:27.541602 - {INITRD}: 10583921/tftp-deploy-y7em0uqj/ramdisk/ramdisk.cpio.gz
331 22:16:27.541663 - {KERNEL}: 10583921/tftp-deploy-y7em0uqj/kernel/Image
332 22:16:27.541723 - {LAVA_MAC}: None
333 22:16:27.541781 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10583921/extract-nfsrootfs-dpv56toy
334 22:16:27.541840 - {NFS_SERVER_IP}: 192.168.201.1
335 22:16:27.541898 - {PRESEED_CONFIG}: None
336 22:16:27.541955 - {PRESEED_LOCAL}: None
337 22:16:27.542011 - {RAMDISK}: 10583921/tftp-deploy-y7em0uqj/ramdisk/ramdisk.cpio.gz
338 22:16:27.542067 - {ROOT_PART}: None
339 22:16:27.542122 - {ROOT}: None
340 22:16:27.542178 - {SERVER_IP}: 192.168.201.1
341 22:16:27.542232 - {TEE}: None
342 22:16:27.542288 Parsed boot commands:
343 22:16:27.542342 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 22:16:27.542528 Parsed boot commands: tftpboot 192.168.201.1 10583921/tftp-deploy-y7em0uqj/kernel/image.itb 10583921/tftp-deploy-y7em0uqj/kernel/cmdline
345 22:16:27.542620 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 22:16:27.542705 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 22:16:27.542798 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 22:16:27.542884 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 22:16:27.542959 Not connected, no need to disconnect.
350 22:16:27.543035 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 22:16:27.543117 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 22:16:27.543184 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-8'
353 22:16:27.546674 Setting prompt string to ['lava-test: # ']
354 22:16:27.547014 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 22:16:27.547127 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 22:16:27.547226 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 22:16:27.547318 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 22:16:27.547517 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
359 22:16:32.681856 >> Command sent successfully.
360 22:16:32.684343 Returned 0 in 5 seconds
361 22:16:32.784755 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 22:16:32.785138 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 22:16:32.785263 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 22:16:32.785360 Setting prompt string to 'Starting depthcharge on Spherion...'
366 22:16:32.785443 Changing prompt to 'Starting depthcharge on Spherion...'
367 22:16:32.785533 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 22:16:32.785893 [Enter `^Ec?' for help]
369 22:16:32.955839
370 22:16:32.956008
371 22:16:32.956112 F0: 102B 0000
372 22:16:32.956195
373 22:16:32.956275 F3: 1001 0000 [0200]
374 22:16:32.956353
375 22:16:32.959318 F3: 1001 0000
376 22:16:32.959404
377 22:16:32.959508 F7: 102D 0000
378 22:16:32.959614
379 22:16:32.959695 F1: 0000 0000
380 22:16:32.959773
381 22:16:32.963365 V0: 0000 0000 [0001]
382 22:16:32.963480
383 22:16:32.963600 00: 0007 8000
384 22:16:32.963688
385 22:16:32.966549 01: 0000 0000
386 22:16:32.966652
387 22:16:32.966733 BP: 0C00 0209 [0000]
388 22:16:32.966810
389 22:16:32.970093 G0: 1182 0000
390 22:16:32.970183
391 22:16:32.970287 EC: 0000 0021 [4000]
392 22:16:32.970388
393 22:16:32.973851 S7: 0000 0000 [0000]
394 22:16:32.973937
395 22:16:32.974040 CC: 0000 0000 [0001]
396 22:16:32.974148
397 22:16:32.977164 T0: 0000 0040 [010F]
398 22:16:32.977250
399 22:16:32.977336 Jump to BL
400 22:16:32.977433
401 22:16:33.001679
402 22:16:33.001770
403 22:16:33.001858
404 22:16:33.011827 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 22:16:33.015480 ARM64: Exception handlers installed.
406 22:16:33.015613 ARM64: Testing exception
407 22:16:33.019086 ARM64: Done test exception
408 22:16:33.026488 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 22:16:33.037620 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 22:16:33.043952 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 22:16:33.053823 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 22:16:33.060817 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 22:16:33.067259 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 22:16:33.079081 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 22:16:33.086045 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 22:16:33.104892 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 22:16:33.108304 WDT: Last reset was cold boot
418 22:16:33.111545 SPI1(PAD0) initialized at 2873684 Hz
419 22:16:33.115073 SPI5(PAD0) initialized at 992727 Hz
420 22:16:33.118221 VBOOT: Loading verstage.
421 22:16:33.124874 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 22:16:33.128284 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 22:16:33.131498 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 22:16:33.134722 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 22:16:33.142390 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 22:16:33.149282 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 22:16:33.160000 read SPI 0x96554 0xa1eb: 4594 us, 9022 KB/s, 72.176 Mbps
428 22:16:33.160088
429 22:16:33.160174
430 22:16:33.170123 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 22:16:33.173174 ARM64: Exception handlers installed.
432 22:16:33.176685 ARM64: Testing exception
433 22:16:33.176771 ARM64: Done test exception
434 22:16:33.183309 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 22:16:33.186681 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 22:16:33.201145 Probing TPM: . done!
437 22:16:33.201232 TPM ready after 0 ms
438 22:16:33.207530 Connected to device vid:did:rid of 1ae0:0028:00
439 22:16:33.256956 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
440 22:16:33.257074 Initialized TPM device CR50 revision 0
441 22:16:33.269025 tlcl_send_startup: Startup return code is 0
442 22:16:33.269116 TPM: setup succeeded
443 22:16:33.280235 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 22:16:33.289305 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 22:16:33.300378 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 22:16:33.310347 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 22:16:33.313433 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 22:16:33.317248 in-header: 03 07 00 00 08 00 00 00
449 22:16:33.320489 in-data: aa e4 47 04 13 02 00 00
450 22:16:33.324119 Chrome EC: UHEPI supported
451 22:16:33.330739 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 22:16:33.334595 in-header: 03 9d 00 00 08 00 00 00
453 22:16:33.338150 in-data: 10 20 20 08 00 00 00 00
454 22:16:33.341733 Phase 1
455 22:16:33.345490 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 22:16:33.348904 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 22:16:33.355939 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 22:16:33.360327 Recovery requested (1009000e)
459 22:16:33.366127 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 22:16:33.370675 tlcl_extend: response is 0
461 22:16:33.379373 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 22:16:33.384081 tlcl_extend: response is 0
463 22:16:33.390838 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 22:16:33.412278 read SPI 0x210d4 0x2173b: 15146 us, 9046 KB/s, 72.368 Mbps
465 22:16:33.419072 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 22:16:33.419178
467 22:16:33.419279
468 22:16:33.429944 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 22:16:33.430034 ARM64: Exception handlers installed.
470 22:16:33.433514 ARM64: Testing exception
471 22:16:33.437339 ARM64: Done test exception
472 22:16:33.457407 pmic_efuse_setting: Set efuses in 11 msecs
473 22:16:33.460703 pmwrap_interface_init: Select PMIF_VLD_RDY
474 22:16:33.468532 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 22:16:33.471450 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 22:16:33.475288 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 22:16:33.482626 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 22:16:33.486196 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 22:16:33.489728 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 22:16:33.496323 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 22:16:33.499694 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 22:16:33.503202 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 22:16:33.510254 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 22:16:33.513407 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 22:16:33.519878 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 22:16:33.523299 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 22:16:33.529678 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 22:16:33.536267 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 22:16:33.539710 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 22:16:33.546666 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 22:16:33.553274 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 22:16:33.556530 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 22:16:33.563963 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 22:16:33.567274 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 22:16:33.574795 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 22:16:33.581054 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 22:16:33.584513 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 22:16:33.591524 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 22:16:33.598742 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 22:16:33.601675 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 22:16:33.604772 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 22:16:33.611882 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 22:16:33.615417 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 22:16:33.622503 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 22:16:33.626096 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 22:16:33.633071 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 22:16:33.636336 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 22:16:33.640119 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 22:16:33.647025 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 22:16:33.650675 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 22:16:33.657450 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 22:16:33.660625 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 22:16:33.663866 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 22:16:33.670543 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 22:16:33.674065 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 22:16:33.676988 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 22:16:33.683524 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 22:16:33.687043 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 22:16:33.690237 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 22:16:33.693764 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 22:16:33.700299 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 22:16:33.703929 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 22:16:33.706839 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 22:16:33.710069 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 22:16:33.720067 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 22:16:33.726816 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 22:16:33.733640 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 22:16:33.740018 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 22:16:33.749904 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 22:16:33.753304 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 22:16:33.760171 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 22:16:33.763185 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 22:16:33.769871 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x20
534 22:16:33.777066 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 22:16:33.779840 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
536 22:16:33.783075 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 22:16:33.794127 [RTC]rtc_get_frequency_meter,154: input=15, output=793
538 22:16:33.797265 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
539 22:16:33.803937 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
540 22:16:33.807414 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
541 22:16:33.810729 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
542 22:16:33.814140 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
543 22:16:33.817513 ADC[4]: Raw value=894821 ID=7
544 22:16:33.821212 ADC[3]: Raw value=212700 ID=1
545 22:16:33.821297 RAM Code: 0x71
546 22:16:33.827713 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
547 22:16:33.830735 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
548 22:16:33.841342 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
549 22:16:33.848388 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
550 22:16:33.851557 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
551 22:16:33.854423 in-header: 03 07 00 00 08 00 00 00
552 22:16:33.857704 in-data: aa e4 47 04 13 02 00 00
553 22:16:33.861135 Chrome EC: UHEPI supported
554 22:16:33.864985 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
555 22:16:33.869033 in-header: 03 d5 00 00 08 00 00 00
556 22:16:33.872367 in-data: 98 20 60 08 00 00 00 00
557 22:16:33.876005 MRC: failed to locate region type 0.
558 22:16:33.883222 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
559 22:16:33.886558 DRAM-K: Running full calibration
560 22:16:33.893328 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
561 22:16:33.893413 header.status = 0x0
562 22:16:33.896738 header.version = 0x6 (expected: 0x6)
563 22:16:33.899797 header.size = 0xd00 (expected: 0xd00)
564 22:16:33.903581 header.flags = 0x0
565 22:16:33.907078 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
566 22:16:33.926680 read SPI 0x72590 0x1c583: 12504 us, 9284 KB/s, 74.272 Mbps
567 22:16:33.932814 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
568 22:16:33.936456 dram_init: ddr_geometry: 2
569 22:16:33.939966 [EMI] MDL number = 2
570 22:16:33.940052 [EMI] Get MDL freq = 0
571 22:16:33.942783 dram_init: ddr_type: 0
572 22:16:33.942867 is_discrete_lpddr4: 1
573 22:16:33.946238 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
574 22:16:33.946322
575 22:16:33.949258
576 22:16:33.949342 [Bian_co] ETT version 0.0.0.1
577 22:16:33.956377 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
578 22:16:33.956462
579 22:16:33.959267 dramc_set_vcore_voltage set vcore to 650000
580 22:16:33.962816 Read voltage for 800, 4
581 22:16:33.962900 Vio18 = 0
582 22:16:33.962967 Vcore = 650000
583 22:16:33.966049 Vdram = 0
584 22:16:33.966133 Vddq = 0
585 22:16:33.966201 Vmddr = 0
586 22:16:33.969545 dram_init: config_dvfs: 1
587 22:16:33.972425 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
588 22:16:33.979176 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
589 22:16:33.982500 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
590 22:16:33.986263 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
591 22:16:33.989451 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
592 22:16:33.996085 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
593 22:16:33.996172 MEM_TYPE=3, freq_sel=18
594 22:16:33.999425 sv_algorithm_assistance_LP4_1600
595 22:16:34.002324 ============ PULL DRAM RESETB DOWN ============
596 22:16:34.009202 ========== PULL DRAM RESETB DOWN end =========
597 22:16:34.012616 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
598 22:16:34.015976 ===================================
599 22:16:34.019359 LPDDR4 DRAM CONFIGURATION
600 22:16:34.022479 ===================================
601 22:16:34.022564 EX_ROW_EN[0] = 0x0
602 22:16:34.025571 EX_ROW_EN[1] = 0x0
603 22:16:34.025655 LP4Y_EN = 0x0
604 22:16:34.029456 WORK_FSP = 0x0
605 22:16:34.029541 WL = 0x2
606 22:16:34.032283 RL = 0x2
607 22:16:34.032367 BL = 0x2
608 22:16:34.035628 RPST = 0x0
609 22:16:34.035712 RD_PRE = 0x0
610 22:16:34.038950 WR_PRE = 0x1
611 22:16:34.042419 WR_PST = 0x0
612 22:16:34.042504 DBI_WR = 0x0
613 22:16:34.046169 DBI_RD = 0x0
614 22:16:34.046253 OTF = 0x1
615 22:16:34.048994 ===================================
616 22:16:34.052559 ===================================
617 22:16:34.052663 ANA top config
618 22:16:34.055916 ===================================
619 22:16:34.059569 DLL_ASYNC_EN = 0
620 22:16:34.064094 ALL_SLAVE_EN = 1
621 22:16:34.064178 NEW_RANK_MODE = 1
622 22:16:34.067199 DLL_IDLE_MODE = 1
623 22:16:34.070999 LP45_APHY_COMB_EN = 1
624 22:16:34.074351 TX_ODT_DIS = 1
625 22:16:34.074468 NEW_8X_MODE = 1
626 22:16:34.078122 ===================================
627 22:16:34.081636 ===================================
628 22:16:34.085458 data_rate = 1600
629 22:16:34.088876 CKR = 1
630 22:16:34.088963 DQ_P2S_RATIO = 8
631 22:16:34.092750 ===================================
632 22:16:34.095993 CA_P2S_RATIO = 8
633 22:16:34.099856 DQ_CA_OPEN = 0
634 22:16:34.103353 DQ_SEMI_OPEN = 0
635 22:16:34.103439 CA_SEMI_OPEN = 0
636 22:16:34.107097 CA_FULL_RATE = 0
637 22:16:34.110623 DQ_CKDIV4_EN = 1
638 22:16:34.114331 CA_CKDIV4_EN = 1
639 22:16:34.114417 CA_PREDIV_EN = 0
640 22:16:34.118325 PH8_DLY = 0
641 22:16:34.121891 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
642 22:16:34.125430 DQ_AAMCK_DIV = 4
643 22:16:34.125527 CA_AAMCK_DIV = 4
644 22:16:34.128991 CA_ADMCK_DIV = 4
645 22:16:34.132888 DQ_TRACK_CA_EN = 0
646 22:16:34.136748 CA_PICK = 800
647 22:16:34.136842 CA_MCKIO = 800
648 22:16:34.140061 MCKIO_SEMI = 0
649 22:16:34.143602 PLL_FREQ = 3068
650 22:16:34.146601 DQ_UI_PI_RATIO = 32
651 22:16:34.149945 CA_UI_PI_RATIO = 0
652 22:16:34.153678 ===================================
653 22:16:34.156485 ===================================
654 22:16:34.160041 memory_type:LPDDR4
655 22:16:34.160127 GP_NUM : 10
656 22:16:34.163673 SRAM_EN : 1
657 22:16:34.163759 MD32_EN : 0
658 22:16:34.166582 ===================================
659 22:16:34.169911 [ANA_INIT] >>>>>>>>>>>>>>
660 22:16:34.173171 <<<<<< [CONFIGURE PHASE]: ANA_TX
661 22:16:34.177015 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
662 22:16:34.180281 ===================================
663 22:16:34.183299 data_rate = 1600,PCW = 0X7600
664 22:16:34.186671 ===================================
665 22:16:34.189470 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
666 22:16:34.196385 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
667 22:16:34.199340 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
668 22:16:34.206051 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
669 22:16:34.210503 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
670 22:16:34.210590 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
671 22:16:34.214047 [ANA_INIT] flow start
672 22:16:34.216889 [ANA_INIT] PLL >>>>>>>>
673 22:16:34.216975 [ANA_INIT] PLL <<<<<<<<
674 22:16:34.220586 [ANA_INIT] MIDPI >>>>>>>>
675 22:16:34.224390 [ANA_INIT] MIDPI <<<<<<<<
676 22:16:34.224476 [ANA_INIT] DLL >>>>>>>>
677 22:16:34.227286 [ANA_INIT] flow end
678 22:16:34.230944 ============ LP4 DIFF to SE enter ============
679 22:16:34.233994 ============ LP4 DIFF to SE exit ============
680 22:16:34.237752 [ANA_INIT] <<<<<<<<<<<<<
681 22:16:34.241427 [Flow] Enable top DCM control >>>>>
682 22:16:34.245264 [Flow] Enable top DCM control <<<<<
683 22:16:34.249118 Enable DLL master slave shuffle
684 22:16:34.252549 ==============================================================
685 22:16:34.256111 Gating Mode config
686 22:16:34.259733 ==============================================================
687 22:16:34.262605 Config description:
688 22:16:34.272590 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
689 22:16:34.279499 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
690 22:16:34.282871 SELPH_MODE 0: By rank 1: By Phase
691 22:16:34.289731 ==============================================================
692 22:16:34.292770 GAT_TRACK_EN = 1
693 22:16:34.296042 RX_GATING_MODE = 2
694 22:16:34.296124 RX_GATING_TRACK_MODE = 2
695 22:16:34.299459 SELPH_MODE = 1
696 22:16:34.302648 PICG_EARLY_EN = 1
697 22:16:34.305765 VALID_LAT_VALUE = 1
698 22:16:34.312338 ==============================================================
699 22:16:34.315754 Enter into Gating configuration >>>>
700 22:16:34.319755 Exit from Gating configuration <<<<
701 22:16:34.322473 Enter into DVFS_PRE_config >>>>>
702 22:16:34.332370 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
703 22:16:34.335708 Exit from DVFS_PRE_config <<<<<
704 22:16:34.339269 Enter into PICG configuration >>>>
705 22:16:34.342831 Exit from PICG configuration <<<<
706 22:16:34.345761 [RX_INPUT] configuration >>>>>
707 22:16:34.349198 [RX_INPUT] configuration <<<<<
708 22:16:34.352782 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
709 22:16:34.359554 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
710 22:16:34.365806 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
711 22:16:34.372344 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
712 22:16:34.375685 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
713 22:16:34.382521 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
714 22:16:34.385431 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
715 22:16:34.392401 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
716 22:16:34.396023 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
717 22:16:34.399486 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
718 22:16:34.402382 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
719 22:16:34.409340 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
720 22:16:34.413160 ===================================
721 22:16:34.413265 LPDDR4 DRAM CONFIGURATION
722 22:16:34.416874 ===================================
723 22:16:34.420282 EX_ROW_EN[0] = 0x0
724 22:16:34.420387 EX_ROW_EN[1] = 0x0
725 22:16:34.424169 LP4Y_EN = 0x0
726 22:16:34.424253 WORK_FSP = 0x0
727 22:16:34.428190 WL = 0x2
728 22:16:34.428295 RL = 0x2
729 22:16:34.431563 BL = 0x2
730 22:16:34.431646 RPST = 0x0
731 22:16:34.431708 RD_PRE = 0x0
732 22:16:34.435323 WR_PRE = 0x1
733 22:16:34.435430 WR_PST = 0x0
734 22:16:34.438955 DBI_WR = 0x0
735 22:16:34.439060 DBI_RD = 0x0
736 22:16:34.442373 OTF = 0x1
737 22:16:34.445881 ===================================
738 22:16:34.449415 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
739 22:16:34.452844 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
740 22:16:34.456749 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
741 22:16:34.460209 ===================================
742 22:16:34.463919 LPDDR4 DRAM CONFIGURATION
743 22:16:34.467479 ===================================
744 22:16:34.467597 EX_ROW_EN[0] = 0x10
745 22:16:34.471640 EX_ROW_EN[1] = 0x0
746 22:16:34.471758 LP4Y_EN = 0x0
747 22:16:34.475212 WORK_FSP = 0x0
748 22:16:34.475286 WL = 0x2
749 22:16:34.478694 RL = 0x2
750 22:16:34.478769 BL = 0x2
751 22:16:34.481931 RPST = 0x0
752 22:16:34.482002 RD_PRE = 0x0
753 22:16:34.486000 WR_PRE = 0x1
754 22:16:34.486073 WR_PST = 0x0
755 22:16:34.489640 DBI_WR = 0x0
756 22:16:34.489711 DBI_RD = 0x0
757 22:16:34.493034 OTF = 0x1
758 22:16:34.493111 ===================================
759 22:16:34.500276 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
760 22:16:34.504816 nWR fixed to 40
761 22:16:34.508473 [ModeRegInit_LP4] CH0 RK0
762 22:16:34.508548 [ModeRegInit_LP4] CH0 RK1
763 22:16:34.512267 [ModeRegInit_LP4] CH1 RK0
764 22:16:34.515951 [ModeRegInit_LP4] CH1 RK1
765 22:16:34.516023 match AC timing 13
766 22:16:34.519735 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
767 22:16:34.523182 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
768 22:16:34.529834 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
769 22:16:34.533177 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
770 22:16:34.537312 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
771 22:16:34.541098 [EMI DOE] emi_dcm 0
772 22:16:34.544714 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
773 22:16:34.544804 ==
774 22:16:34.548284 Dram Type= 6, Freq= 0, CH_0, rank 0
775 22:16:34.551767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
776 22:16:34.551934 ==
777 22:16:34.555250 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
778 22:16:34.562794 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
779 22:16:34.572643 [CA 0] Center 38 (7~69) winsize 63
780 22:16:34.576628 [CA 1] Center 37 (7~68) winsize 62
781 22:16:34.580302 [CA 2] Center 35 (5~66) winsize 62
782 22:16:34.583621 [CA 3] Center 35 (5~66) winsize 62
783 22:16:34.587162 [CA 4] Center 34 (4~65) winsize 62
784 22:16:34.591219 [CA 5] Center 34 (4~65) winsize 62
785 22:16:34.591540
786 22:16:34.594909 [CmdBusTrainingLP45] Vref(ca) range 1: 34
787 22:16:34.595219
788 22:16:34.598326 [CATrainingPosCal] consider 1 rank data
789 22:16:34.598731 u2DelayCellTimex100 = 270/100 ps
790 22:16:34.602289 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
791 22:16:34.605718 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
792 22:16:34.609597 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
793 22:16:34.613388 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
794 22:16:34.616991 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
795 22:16:34.620190 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
796 22:16:34.620717
797 22:16:34.627826 CA PerBit enable=1, Macro0, CA PI delay=34
798 22:16:34.628357
799 22:16:34.628773 [CBTSetCACLKResult] CA Dly = 34
800 22:16:34.631306 CS Dly: 6 (0~37)
801 22:16:34.632047 ==
802 22:16:34.635037 Dram Type= 6, Freq= 0, CH_0, rank 1
803 22:16:34.638436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
804 22:16:34.638979 ==
805 22:16:34.642101 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
806 22:16:34.649707 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
807 22:16:34.659177 [CA 0] Center 38 (7~69) winsize 63
808 22:16:34.662979 [CA 1] Center 38 (7~69) winsize 63
809 22:16:34.666450 [CA 2] Center 35 (5~66) winsize 62
810 22:16:34.669826 [CA 3] Center 35 (5~66) winsize 62
811 22:16:34.673937 [CA 4] Center 34 (4~65) winsize 62
812 22:16:34.674151 [CA 5] Center 34 (4~65) winsize 62
813 22:16:34.677645
814 22:16:34.681364 [CmdBusTrainingLP45] Vref(ca) range 1: 32
815 22:16:34.681557
816 22:16:34.684850 [CATrainingPosCal] consider 2 rank data
817 22:16:34.685040 u2DelayCellTimex100 = 270/100 ps
818 22:16:34.688967 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
819 22:16:34.691716 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
820 22:16:34.695666 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
821 22:16:34.702121 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
822 22:16:34.705513 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
823 22:16:34.708507 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
824 22:16:34.708620
825 22:16:34.712042 CA PerBit enable=1, Macro0, CA PI delay=34
826 22:16:34.712135
827 22:16:34.715394 [CBTSetCACLKResult] CA Dly = 34
828 22:16:34.715499 CS Dly: 6 (0~38)
829 22:16:34.715610
830 22:16:34.718976 ----->DramcWriteLeveling(PI) begin...
831 22:16:34.719067 ==
832 22:16:34.721665 Dram Type= 6, Freq= 0, CH_0, rank 0
833 22:16:34.728758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
834 22:16:34.728891 ==
835 22:16:34.732017 Write leveling (Byte 0): 34 => 34
836 22:16:34.735160 Write leveling (Byte 1): 29 => 29
837 22:16:34.738590 DramcWriteLeveling(PI) end<-----
838 22:16:34.738719
839 22:16:34.738789 ==
840 22:16:34.742123 Dram Type= 6, Freq= 0, CH_0, rank 0
841 22:16:34.745556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
842 22:16:34.745659 ==
843 22:16:34.748749 [Gating] SW mode calibration
844 22:16:34.755304 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
845 22:16:34.758421 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
846 22:16:34.765235 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
847 22:16:34.768252 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
848 22:16:34.771506 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
849 22:16:34.778228 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
850 22:16:34.782038 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
851 22:16:34.784849 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
852 22:16:34.791863 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
853 22:16:34.794670 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 22:16:34.798699 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 22:16:34.805503 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 22:16:34.808964 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 22:16:34.812610 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 22:16:34.816184 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 22:16:34.822520 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 22:16:34.826043 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 22:16:34.829523 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 22:16:34.835985 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 22:16:34.839588 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
864 22:16:34.842984 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
865 22:16:34.849605 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 22:16:34.852770 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 22:16:34.856225 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 22:16:34.862236 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 22:16:34.865525 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 22:16:34.869166 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 22:16:34.875936 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 22:16:34.878726 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 22:16:34.882395 0 9 12 | B1->B0 | 2828 3232 | 0 0 | (0 0) (0 0)
874 22:16:34.889079 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
875 22:16:34.892270 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
876 22:16:34.895356 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
877 22:16:34.898951 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
878 22:16:34.905969 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 22:16:34.908782 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 22:16:34.911913 0 10 8 | B1->B0 | 3333 2f2f | 1 0 | (1 1) (0 0)
881 22:16:34.918508 0 10 12 | B1->B0 | 2f2f 2424 | 1 0 | (1 0) (0 0)
882 22:16:34.922299 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
883 22:16:34.925477 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
884 22:16:34.932123 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
885 22:16:34.935253 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
886 22:16:34.938644 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
887 22:16:34.945019 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 22:16:34.948492 0 11 8 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
889 22:16:34.952011 0 11 12 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
890 22:16:34.958875 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
891 22:16:34.961460 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
892 22:16:34.964852 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
893 22:16:34.971911 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
894 22:16:34.974840 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
895 22:16:34.978272 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 22:16:34.985161 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 22:16:34.988291 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
898 22:16:34.991567 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
899 22:16:34.998287 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
900 22:16:35.001732 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
901 22:16:35.005262 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
902 22:16:35.011439 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 22:16:35.015019 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 22:16:35.018526 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 22:16:35.024704 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 22:16:35.028358 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 22:16:35.031791 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 22:16:35.038014 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 22:16:35.041565 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 22:16:35.044819 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 22:16:35.051537 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 22:16:35.054710 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
913 22:16:35.058048 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
914 22:16:35.061443 Total UI for P1: 0, mck2ui 16
915 22:16:35.064671 best dqsien dly found for B0: ( 0, 14, 8)
916 22:16:35.067923 Total UI for P1: 0, mck2ui 16
917 22:16:35.071268 best dqsien dly found for B1: ( 0, 14, 10)
918 22:16:35.074547 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
919 22:16:35.077953 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
920 22:16:35.078038
921 22:16:35.081228 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
922 22:16:35.087510 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
923 22:16:35.087623 [Gating] SW calibration Done
924 22:16:35.087694 ==
925 22:16:35.091198 Dram Type= 6, Freq= 0, CH_0, rank 0
926 22:16:35.097632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
927 22:16:35.097716 ==
928 22:16:35.097785 RX Vref Scan: 0
929 22:16:35.097848
930 22:16:35.100688 RX Vref 0 -> 0, step: 1
931 22:16:35.100772
932 22:16:35.104309 RX Delay -130 -> 252, step: 16
933 22:16:35.107430 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
934 22:16:35.110999 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
935 22:16:35.114024 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
936 22:16:35.120711 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
937 22:16:35.124208 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
938 22:16:35.127135 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
939 22:16:35.131050 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
940 22:16:35.134014 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
941 22:16:35.141070 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
942 22:16:35.144547 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
943 22:16:35.147878 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
944 22:16:35.150413 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
945 22:16:35.154152 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
946 22:16:35.160273 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
947 22:16:35.163971 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
948 22:16:35.167045 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
949 22:16:35.167130 ==
950 22:16:35.170603 Dram Type= 6, Freq= 0, CH_0, rank 0
951 22:16:35.173765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
952 22:16:35.177073 ==
953 22:16:35.177159 DQS Delay:
954 22:16:35.177227 DQS0 = 0, DQS1 = 0
955 22:16:35.180336 DQM Delay:
956 22:16:35.180427 DQM0 = 81, DQM1 = 69
957 22:16:35.183807 DQ Delay:
958 22:16:35.183942 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
959 22:16:35.187135 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
960 22:16:35.190640 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
961 22:16:35.193685 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
962 22:16:35.193782
963 22:16:35.197307
964 22:16:35.197398 ==
965 22:16:35.200567 Dram Type= 6, Freq= 0, CH_0, rank 0
966 22:16:35.204560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 22:16:35.204660 ==
968 22:16:35.204731
969 22:16:35.204794
970 22:16:35.207789 TX Vref Scan disable
971 22:16:35.207874 == TX Byte 0 ==
972 22:16:35.211043 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
973 22:16:35.217647 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
974 22:16:35.217736 == TX Byte 1 ==
975 22:16:35.221017 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
976 22:16:35.228144 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
977 22:16:35.228228 ==
978 22:16:35.231557 Dram Type= 6, Freq= 0, CH_0, rank 0
979 22:16:35.234337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
980 22:16:35.234447 ==
981 22:16:35.247811 TX Vref=22, minBit 0, minWin=27, winSum=438
982 22:16:35.251198 TX Vref=24, minBit 0, minWin=27, winSum=440
983 22:16:35.254661 TX Vref=26, minBit 9, minWin=26, winSum=442
984 22:16:35.257544 TX Vref=28, minBit 5, minWin=27, winSum=444
985 22:16:35.261003 TX Vref=30, minBit 9, minWin=27, winSum=442
986 22:16:35.267340 TX Vref=32, minBit 9, minWin=27, winSum=442
987 22:16:35.270967 [TxChooseVref] Worse bit 5, Min win 27, Win sum 444, Final Vref 28
988 22:16:35.271054
989 22:16:35.273965 Final TX Range 1 Vref 28
990 22:16:35.274050
991 22:16:35.274118 ==
992 22:16:35.277260 Dram Type= 6, Freq= 0, CH_0, rank 0
993 22:16:35.280636 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
994 22:16:35.284010 ==
995 22:16:35.284089
996 22:16:35.284155
997 22:16:35.284224 TX Vref Scan disable
998 22:16:35.288033 == TX Byte 0 ==
999 22:16:35.290873 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1000 22:16:35.297486 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1001 22:16:35.297563 == TX Byte 1 ==
1002 22:16:35.300896 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1003 22:16:35.307283 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1004 22:16:35.307363
1005 22:16:35.307435 [DATLAT]
1006 22:16:35.307507 Freq=800, CH0 RK0
1007 22:16:35.307568
1008 22:16:35.310911 DATLAT Default: 0xa
1009 22:16:35.310992 0, 0xFFFF, sum = 0
1010 22:16:35.314449 1, 0xFFFF, sum = 0
1011 22:16:35.314542 2, 0xFFFF, sum = 0
1012 22:16:35.317480 3, 0xFFFF, sum = 0
1013 22:16:35.321067 4, 0xFFFF, sum = 0
1014 22:16:35.321144 5, 0xFFFF, sum = 0
1015 22:16:35.324615 6, 0xFFFF, sum = 0
1016 22:16:35.324687 7, 0xFFFF, sum = 0
1017 22:16:35.327279 8, 0xFFFF, sum = 0
1018 22:16:35.327356 9, 0x0, sum = 1
1019 22:16:35.330642 10, 0x0, sum = 2
1020 22:16:35.330714 11, 0x0, sum = 3
1021 22:16:35.330775 12, 0x0, sum = 4
1022 22:16:35.334203 best_step = 10
1023 22:16:35.334275
1024 22:16:35.334337 ==
1025 22:16:35.337573 Dram Type= 6, Freq= 0, CH_0, rank 0
1026 22:16:35.340438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1027 22:16:35.340514 ==
1028 22:16:35.343857 RX Vref Scan: 1
1029 22:16:35.343930
1030 22:16:35.347513 Set Vref Range= 32 -> 127
1031 22:16:35.347587
1032 22:16:35.347646 RX Vref 32 -> 127, step: 1
1033 22:16:35.347716
1034 22:16:35.350990 RX Delay -111 -> 252, step: 8
1035 22:16:35.351063
1036 22:16:35.353813 Set Vref, RX VrefLevel [Byte0]: 32
1037 22:16:35.357371 [Byte1]: 32
1038 22:16:35.360788
1039 22:16:35.360856 Set Vref, RX VrefLevel [Byte0]: 33
1040 22:16:35.363903 [Byte1]: 33
1041 22:16:35.368091
1042 22:16:35.368164 Set Vref, RX VrefLevel [Byte0]: 34
1043 22:16:35.371355 [Byte1]: 34
1044 22:16:35.376192
1045 22:16:35.376277 Set Vref, RX VrefLevel [Byte0]: 35
1046 22:16:35.379269 [Byte1]: 35
1047 22:16:35.383461
1048 22:16:35.383532 Set Vref, RX VrefLevel [Byte0]: 36
1049 22:16:35.386812 [Byte1]: 36
1050 22:16:35.391010
1051 22:16:35.391091 Set Vref, RX VrefLevel [Byte0]: 37
1052 22:16:35.394490 [Byte1]: 37
1053 22:16:35.398745
1054 22:16:35.398820 Set Vref, RX VrefLevel [Byte0]: 38
1055 22:16:35.402035 [Byte1]: 38
1056 22:16:35.406281
1057 22:16:35.406352 Set Vref, RX VrefLevel [Byte0]: 39
1058 22:16:35.409860 [Byte1]: 39
1059 22:16:35.414074
1060 22:16:35.414155 Set Vref, RX VrefLevel [Byte0]: 40
1061 22:16:35.417215 [Byte1]: 40
1062 22:16:35.422013
1063 22:16:35.422083 Set Vref, RX VrefLevel [Byte0]: 41
1064 22:16:35.425306 [Byte1]: 41
1065 22:16:35.429344
1066 22:16:35.429413 Set Vref, RX VrefLevel [Byte0]: 42
1067 22:16:35.432581 [Byte1]: 42
1068 22:16:35.437193
1069 22:16:35.437265 Set Vref, RX VrefLevel [Byte0]: 43
1070 22:16:35.440314 [Byte1]: 43
1071 22:16:35.444408
1072 22:16:35.444483 Set Vref, RX VrefLevel [Byte0]: 44
1073 22:16:35.447857 [Byte1]: 44
1074 22:16:35.452237
1075 22:16:35.452314 Set Vref, RX VrefLevel [Byte0]: 45
1076 22:16:35.455529 [Byte1]: 45
1077 22:16:35.460169
1078 22:16:35.460241 Set Vref, RX VrefLevel [Byte0]: 46
1079 22:16:35.463814 [Byte1]: 46
1080 22:16:35.467845
1081 22:16:35.471110 Set Vref, RX VrefLevel [Byte0]: 47
1082 22:16:35.471215 [Byte1]: 47
1083 22:16:35.475868
1084 22:16:35.475953 Set Vref, RX VrefLevel [Byte0]: 48
1085 22:16:35.479022 [Byte1]: 48
1086 22:16:35.483090
1087 22:16:35.483164 Set Vref, RX VrefLevel [Byte0]: 49
1088 22:16:35.486418 [Byte1]: 49
1089 22:16:35.491303
1090 22:16:35.491375 Set Vref, RX VrefLevel [Byte0]: 50
1091 22:16:35.494139 [Byte1]: 50
1092 22:16:35.498841
1093 22:16:35.498915 Set Vref, RX VrefLevel [Byte0]: 51
1094 22:16:35.501577 [Byte1]: 51
1095 22:16:35.505835
1096 22:16:35.505916 Set Vref, RX VrefLevel [Byte0]: 52
1097 22:16:35.508937 [Byte1]: 52
1098 22:16:35.513531
1099 22:16:35.513610 Set Vref, RX VrefLevel [Byte0]: 53
1100 22:16:35.516699 [Byte1]: 53
1101 22:16:35.521434
1102 22:16:35.521503 Set Vref, RX VrefLevel [Byte0]: 54
1103 22:16:35.524402 [Byte1]: 54
1104 22:16:35.528573
1105 22:16:35.528644 Set Vref, RX VrefLevel [Byte0]: 55
1106 22:16:35.531912 [Byte1]: 55
1107 22:16:35.536276
1108 22:16:35.536348 Set Vref, RX VrefLevel [Byte0]: 56
1109 22:16:35.539712 [Byte1]: 56
1110 22:16:35.543810
1111 22:16:35.543887 Set Vref, RX VrefLevel [Byte0]: 57
1112 22:16:35.547319 [Byte1]: 57
1113 22:16:35.551845
1114 22:16:35.551913 Set Vref, RX VrefLevel [Byte0]: 58
1115 22:16:35.554981 [Byte1]: 58
1116 22:16:35.559573
1117 22:16:35.559694 Set Vref, RX VrefLevel [Byte0]: 59
1118 22:16:35.563102 [Byte1]: 59
1119 22:16:35.567266
1120 22:16:35.567358 Set Vref, RX VrefLevel [Byte0]: 60
1121 22:16:35.570697 [Byte1]: 60
1122 22:16:35.574658
1123 22:16:35.574766 Set Vref, RX VrefLevel [Byte0]: 61
1124 22:16:35.578551 [Byte1]: 61
1125 22:16:35.582277
1126 22:16:35.582391 Set Vref, RX VrefLevel [Byte0]: 62
1127 22:16:35.585663 [Byte1]: 62
1128 22:16:35.590087
1129 22:16:35.590169 Set Vref, RX VrefLevel [Byte0]: 63
1130 22:16:35.593526 [Byte1]: 63
1131 22:16:35.597929
1132 22:16:35.598041 Set Vref, RX VrefLevel [Byte0]: 64
1133 22:16:35.600675 [Byte1]: 64
1134 22:16:35.605484
1135 22:16:35.605561 Set Vref, RX VrefLevel [Byte0]: 65
1136 22:16:35.608698 [Byte1]: 65
1137 22:16:35.612750
1138 22:16:35.612833 Set Vref, RX VrefLevel [Byte0]: 66
1139 22:16:35.615925 [Byte1]: 66
1140 22:16:35.620725
1141 22:16:35.620798 Set Vref, RX VrefLevel [Byte0]: 67
1142 22:16:35.623790 [Byte1]: 67
1143 22:16:35.627993
1144 22:16:35.628064 Set Vref, RX VrefLevel [Byte0]: 68
1145 22:16:35.631551 [Byte1]: 68
1146 22:16:35.635952
1147 22:16:35.636027 Set Vref, RX VrefLevel [Byte0]: 69
1148 22:16:35.639174 [Byte1]: 69
1149 22:16:35.643507
1150 22:16:35.643592 Set Vref, RX VrefLevel [Byte0]: 70
1151 22:16:35.646947 [Byte1]: 70
1152 22:16:35.650808
1153 22:16:35.650882 Set Vref, RX VrefLevel [Byte0]: 71
1154 22:16:35.654504 [Byte1]: 71
1155 22:16:35.659150
1156 22:16:35.659216 Set Vref, RX VrefLevel [Byte0]: 72
1157 22:16:35.661867 [Byte1]: 72
1158 22:16:35.666217
1159 22:16:35.666293 Set Vref, RX VrefLevel [Byte0]: 73
1160 22:16:35.669711 [Byte1]: 73
1161 22:16:35.673809
1162 22:16:35.673886 Set Vref, RX VrefLevel [Byte0]: 74
1163 22:16:35.677290 [Byte1]: 74
1164 22:16:35.681595
1165 22:16:35.681668 Set Vref, RX VrefLevel [Byte0]: 75
1166 22:16:35.685208 [Byte1]: 75
1167 22:16:35.689332
1168 22:16:35.689405 Set Vref, RX VrefLevel [Byte0]: 76
1169 22:16:35.692696 [Byte1]: 76
1170 22:16:35.696994
1171 22:16:35.697067 Set Vref, RX VrefLevel [Byte0]: 77
1172 22:16:35.700272 [Byte1]: 77
1173 22:16:35.704856
1174 22:16:35.704928 Set Vref, RX VrefLevel [Byte0]: 78
1175 22:16:35.708186 [Byte1]: 78
1176 22:16:35.712217
1177 22:16:35.712287 Set Vref, RX VrefLevel [Byte0]: 79
1178 22:16:35.715475 [Byte1]: 79
1179 22:16:35.719879
1180 22:16:35.719951 Set Vref, RX VrefLevel [Byte0]: 80
1181 22:16:35.723262 [Byte1]: 80
1182 22:16:35.727397
1183 22:16:35.727466 Final RX Vref Byte 0 = 58 to rank0
1184 22:16:35.730719 Final RX Vref Byte 1 = 61 to rank0
1185 22:16:35.734215 Final RX Vref Byte 0 = 58 to rank1
1186 22:16:35.737779 Final RX Vref Byte 1 = 61 to rank1==
1187 22:16:35.741039 Dram Type= 6, Freq= 0, CH_0, rank 0
1188 22:16:35.747547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1189 22:16:35.747660 ==
1190 22:16:35.747724 DQS Delay:
1191 22:16:35.747784 DQS0 = 0, DQS1 = 0
1192 22:16:35.751089 DQM Delay:
1193 22:16:35.751438 DQM0 = 82, DQM1 = 68
1194 22:16:35.754794 DQ Delay:
1195 22:16:35.758024 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1196 22:16:35.761644 DQ4 =80, DQ5 =68, DQ6 =92, DQ7 =92
1197 22:16:35.764627 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1198 22:16:35.767807 DQ12 =76, DQ13 =72, DQ14 =76, DQ15 =76
1199 22:16:35.768267
1200 22:16:35.768632
1201 22:16:35.774730 [DQSOSCAuto] RK0, (LSB)MR18= 0x2625, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
1202 22:16:35.777947 CH0 RK0: MR19=606, MR18=2625
1203 22:16:35.784232 CH0_RK0: MR19=0x606, MR18=0x2625, DQSOSC=400, MR23=63, INC=92, DEC=61
1204 22:16:35.784732
1205 22:16:35.787553 ----->DramcWriteLeveling(PI) begin...
1206 22:16:35.788080 ==
1207 22:16:35.791168 Dram Type= 6, Freq= 0, CH_0, rank 1
1208 22:16:35.794509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1209 22:16:35.794985 ==
1210 22:16:35.797676 Write leveling (Byte 0): 33 => 33
1211 22:16:35.801085 Write leveling (Byte 1): 30 => 30
1212 22:16:35.804469 DramcWriteLeveling(PI) end<-----
1213 22:16:35.804941
1214 22:16:35.805314 ==
1215 22:16:35.807851 Dram Type= 6, Freq= 0, CH_0, rank 1
1216 22:16:35.810899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1217 22:16:35.811371 ==
1218 22:16:35.814643 [Gating] SW mode calibration
1219 22:16:35.820812 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1220 22:16:35.827604 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1221 22:16:35.830910 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1222 22:16:35.834456 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1223 22:16:35.840675 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1224 22:16:35.844102 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 22:16:35.847576 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 22:16:35.853686 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 22:16:35.857221 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 22:16:35.860532 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 22:16:35.867008 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 22:16:35.870339 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 22:16:35.873261 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 22:16:35.879964 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 22:16:35.924264 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 22:16:35.924547 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 22:16:35.924618 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 22:16:35.924690 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1237 22:16:35.925376 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1238 22:16:35.925619 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1239 22:16:35.926218 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1240 22:16:35.926300 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 22:16:35.926533 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 22:16:35.926594 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 22:16:35.943424 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 22:16:35.943702 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 22:16:35.943772 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 22:16:35.943835 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 22:16:35.947234 0 9 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
1248 22:16:35.950044 0 9 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
1249 22:16:35.953874 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 22:16:35.957251 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 22:16:35.963411 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 22:16:35.966805 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1253 22:16:35.970245 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1254 22:16:35.976857 0 10 4 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
1255 22:16:35.980358 0 10 8 | B1->B0 | 2f2f 2424 | 1 0 | (1 0) (1 0)
1256 22:16:35.983228 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 22:16:35.990149 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 22:16:35.993587 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 22:16:35.996570 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 22:16:36.003545 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 22:16:36.006597 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1262 22:16:36.010002 0 11 4 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
1263 22:16:36.016418 0 11 8 | B1->B0 | 3232 4646 | 1 0 | (0 0) (0 0)
1264 22:16:36.020264 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1265 22:16:36.023183 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 22:16:36.029445 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 22:16:36.032986 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 22:16:36.036255 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 22:16:36.043765 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1270 22:16:36.047481 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1271 22:16:36.051195 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1272 22:16:36.054611 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 22:16:36.057810 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 22:16:36.064400 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 22:16:36.067912 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 22:16:36.071490 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 22:16:36.077451 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 22:16:36.081070 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 22:16:36.084623 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 22:16:36.091068 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 22:16:36.094428 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 22:16:36.097922 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 22:16:36.104187 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 22:16:36.108024 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 22:16:36.110989 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 22:16:36.117225 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 22:16:36.120501 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1288 22:16:36.124302 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1289 22:16:36.127544 Total UI for P1: 0, mck2ui 16
1290 22:16:36.130693 best dqsien dly found for B0: ( 0, 14, 8)
1291 22:16:36.134054 Total UI for P1: 0, mck2ui 16
1292 22:16:36.137372 best dqsien dly found for B1: ( 0, 14, 10)
1293 22:16:36.140540 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1294 22:16:36.143866 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1295 22:16:36.147672
1296 22:16:36.150620 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1297 22:16:36.154073 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1298 22:16:36.156879 [Gating] SW calibration Done
1299 22:16:36.156960 ==
1300 22:16:36.160439 Dram Type= 6, Freq= 0, CH_0, rank 1
1301 22:16:36.163919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1302 22:16:36.164002 ==
1303 22:16:36.164066 RX Vref Scan: 0
1304 22:16:36.164129
1305 22:16:36.167516 RX Vref 0 -> 0, step: 1
1306 22:16:36.167627
1307 22:16:36.170819 RX Delay -130 -> 252, step: 16
1308 22:16:36.173679 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1309 22:16:36.176970 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1310 22:16:36.183861 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1311 22:16:36.186695 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1312 22:16:36.190058 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1313 22:16:36.193524 iDelay=222, Bit 5, Center 61 (-66 ~ 189) 256
1314 22:16:36.196982 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
1315 22:16:36.203511 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1316 22:16:36.207145 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1317 22:16:36.209822 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1318 22:16:36.213312 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1319 22:16:36.216376 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
1320 22:16:36.223336 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1321 22:16:36.226786 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1322 22:16:36.229760 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1323 22:16:36.233239 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1324 22:16:36.236310 ==
1325 22:16:36.236412 Dram Type= 6, Freq= 0, CH_0, rank 1
1326 22:16:36.242923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1327 22:16:36.243033 ==
1328 22:16:36.243126 DQS Delay:
1329 22:16:36.246697 DQS0 = 0, DQS1 = 0
1330 22:16:36.246794 DQM Delay:
1331 22:16:36.249899 DQM0 = 80, DQM1 = 70
1332 22:16:36.250004 DQ Delay:
1333 22:16:36.252925 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =69
1334 22:16:36.256022 DQ4 =85, DQ5 =61, DQ6 =85, DQ7 =93
1335 22:16:36.259492 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1336 22:16:36.262869 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =77
1337 22:16:36.262951
1338 22:16:36.263016
1339 22:16:36.263077 ==
1340 22:16:36.265984 Dram Type= 6, Freq= 0, CH_0, rank 1
1341 22:16:36.269262 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1342 22:16:36.269346 ==
1343 22:16:36.269412
1344 22:16:36.269472
1345 22:16:36.272857 TX Vref Scan disable
1346 22:16:36.276216 == TX Byte 0 ==
1347 22:16:36.279522 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1348 22:16:36.282577 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1349 22:16:36.286122 == TX Byte 1 ==
1350 22:16:36.289422 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1351 22:16:36.292943 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1352 22:16:36.293025 ==
1353 22:16:36.295904 Dram Type= 6, Freq= 0, CH_0, rank 1
1354 22:16:36.299592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1355 22:16:36.302797 ==
1356 22:16:36.314666 TX Vref=22, minBit 5, minWin=26, winSum=434
1357 22:16:36.317539 TX Vref=24, minBit 1, minWin=27, winSum=437
1358 22:16:36.320929 TX Vref=26, minBit 1, minWin=27, winSum=441
1359 22:16:36.324198 TX Vref=28, minBit 1, minWin=27, winSum=442
1360 22:16:36.327291 TX Vref=30, minBit 1, minWin=27, winSum=444
1361 22:16:36.334152 TX Vref=32, minBit 11, minWin=26, winSum=441
1362 22:16:36.337197 [TxChooseVref] Worse bit 1, Min win 27, Win sum 444, Final Vref 30
1363 22:16:36.337279
1364 22:16:36.340465 Final TX Range 1 Vref 30
1365 22:16:36.340547
1366 22:16:36.340610 ==
1367 22:16:36.343643 Dram Type= 6, Freq= 0, CH_0, rank 1
1368 22:16:36.347493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1369 22:16:36.350294 ==
1370 22:16:36.350374
1371 22:16:36.350438
1372 22:16:36.350497 TX Vref Scan disable
1373 22:16:36.354058 == TX Byte 0 ==
1374 22:16:36.357619 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1375 22:16:36.364112 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1376 22:16:36.364193 == TX Byte 1 ==
1377 22:16:36.367232 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1378 22:16:36.374255 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1379 22:16:36.374337
1380 22:16:36.374400 [DATLAT]
1381 22:16:36.374460 Freq=800, CH0 RK1
1382 22:16:36.374517
1383 22:16:36.377082 DATLAT Default: 0xa
1384 22:16:36.377162 0, 0xFFFF, sum = 0
1385 22:16:36.380811 1, 0xFFFF, sum = 0
1386 22:16:36.383857 2, 0xFFFF, sum = 0
1387 22:16:36.383938 3, 0xFFFF, sum = 0
1388 22:16:36.387462 4, 0xFFFF, sum = 0
1389 22:16:36.387544 5, 0xFFFF, sum = 0
1390 22:16:36.390270 6, 0xFFFF, sum = 0
1391 22:16:36.390353 7, 0xFFFF, sum = 0
1392 22:16:36.393727 8, 0xFFFF, sum = 0
1393 22:16:36.393810 9, 0x0, sum = 1
1394 22:16:36.397304 10, 0x0, sum = 2
1395 22:16:36.397385 11, 0x0, sum = 3
1396 22:16:36.397451 12, 0x0, sum = 4
1397 22:16:36.400599 best_step = 10
1398 22:16:36.400678
1399 22:16:36.400742 ==
1400 22:16:36.404084 Dram Type= 6, Freq= 0, CH_0, rank 1
1401 22:16:36.407200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1402 22:16:36.407285 ==
1403 22:16:36.410223 RX Vref Scan: 0
1404 22:16:36.410304
1405 22:16:36.413581 RX Vref 0 -> 0, step: 1
1406 22:16:36.413661
1407 22:16:36.413724 RX Delay -111 -> 252, step: 8
1408 22:16:36.420799 iDelay=209, Bit 0, Center 76 (-39 ~ 192) 232
1409 22:16:36.424150 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1410 22:16:36.427770 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1411 22:16:36.431164 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1412 22:16:36.433960 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1413 22:16:36.440677 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1414 22:16:36.444143 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1415 22:16:36.447565 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1416 22:16:36.451211 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
1417 22:16:36.454015 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1418 22:16:36.460680 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1419 22:16:36.463908 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1420 22:16:36.467494 iDelay=209, Bit 12, Center 72 (-47 ~ 192) 240
1421 22:16:36.470735 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1422 22:16:36.476915 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1423 22:16:36.480717 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1424 22:16:36.480799 ==
1425 22:16:36.483924 Dram Type= 6, Freq= 0, CH_0, rank 1
1426 22:16:36.487335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1427 22:16:36.487418 ==
1428 22:16:36.490245 DQS Delay:
1429 22:16:36.490327 DQS0 = 0, DQS1 = 0
1430 22:16:36.490393 DQM Delay:
1431 22:16:36.493770 DQM0 = 78, DQM1 = 70
1432 22:16:36.493852 DQ Delay:
1433 22:16:36.497078 DQ0 =76, DQ1 =84, DQ2 =76, DQ3 =72
1434 22:16:36.500514 DQ4 =80, DQ5 =64, DQ6 =88, DQ7 =88
1435 22:16:36.503968 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1436 22:16:36.506812 DQ12 =72, DQ13 =76, DQ14 =80, DQ15 =80
1437 22:16:36.506895
1438 22:16:36.506960
1439 22:16:36.517069 [DQSOSCAuto] RK1, (LSB)MR18= 0x4520, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
1440 22:16:36.517153 CH0 RK1: MR19=606, MR18=4520
1441 22:16:36.523321 CH0_RK1: MR19=0x606, MR18=0x4520, DQSOSC=392, MR23=63, INC=96, DEC=64
1442 22:16:36.526967 [RxdqsGatingPostProcess] freq 800
1443 22:16:36.533269 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1444 22:16:36.536806 Pre-setting of DQS Precalculation
1445 22:16:36.540294 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1446 22:16:36.540376 ==
1447 22:16:36.543601 Dram Type= 6, Freq= 0, CH_1, rank 0
1448 22:16:36.550214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1449 22:16:36.550296 ==
1450 22:16:36.553556 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1451 22:16:36.560003 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1452 22:16:36.569214 [CA 0] Center 36 (6~66) winsize 61
1453 22:16:36.572867 [CA 1] Center 36 (6~67) winsize 62
1454 22:16:36.575893 [CA 2] Center 34 (4~64) winsize 61
1455 22:16:36.579391 [CA 3] Center 34 (4~64) winsize 61
1456 22:16:36.582748 [CA 4] Center 34 (4~64) winsize 61
1457 22:16:36.585986 [CA 5] Center 33 (3~64) winsize 62
1458 22:16:36.586069
1459 22:16:36.589136 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1460 22:16:36.589218
1461 22:16:36.592621 [CATrainingPosCal] consider 1 rank data
1462 22:16:36.595875 u2DelayCellTimex100 = 270/100 ps
1463 22:16:36.599265 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1464 22:16:36.602690 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1465 22:16:36.608892 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1466 22:16:36.612424 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1467 22:16:36.616218 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
1468 22:16:36.619379 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1469 22:16:36.619461
1470 22:16:36.622466 CA PerBit enable=1, Macro0, CA PI delay=33
1471 22:16:36.622549
1472 22:16:36.625798 [CBTSetCACLKResult] CA Dly = 33
1473 22:16:36.625880 CS Dly: 5 (0~36)
1474 22:16:36.629334 ==
1475 22:16:36.629417 Dram Type= 6, Freq= 0, CH_1, rank 1
1476 22:16:36.635564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1477 22:16:36.635657 ==
1478 22:16:36.639267 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1479 22:16:36.645770 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1480 22:16:36.655512 [CA 0] Center 36 (7~66) winsize 60
1481 22:16:36.659218 [CA 1] Center 37 (7~67) winsize 61
1482 22:16:36.662061 [CA 2] Center 34 (4~65) winsize 62
1483 22:16:36.665657 [CA 3] Center 33 (3~64) winsize 62
1484 22:16:36.669060 [CA 4] Center 34 (4~65) winsize 62
1485 22:16:36.672289 [CA 5] Center 33 (3~64) winsize 62
1486 22:16:36.672372
1487 22:16:36.675405 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1488 22:16:36.675526
1489 22:16:36.678894 [CATrainingPosCal] consider 2 rank data
1490 22:16:36.682076 u2DelayCellTimex100 = 270/100 ps
1491 22:16:36.685299 CA0 delay=36 (7~66),Diff = 3 PI (21 cell)
1492 22:16:36.692125 CA1 delay=37 (7~67),Diff = 4 PI (28 cell)
1493 22:16:36.695137 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1494 22:16:36.698669 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1495 22:16:36.702493 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
1496 22:16:36.706066 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1497 22:16:36.706167
1498 22:16:36.709310 CA PerBit enable=1, Macro0, CA PI delay=33
1499 22:16:36.709411
1500 22:16:36.712787 [CBTSetCACLKResult] CA Dly = 33
1501 22:16:36.712858 CS Dly: 6 (0~38)
1502 22:16:36.712919
1503 22:16:36.716720 ----->DramcWriteLeveling(PI) begin...
1504 22:16:36.716821 ==
1505 22:16:36.720102 Dram Type= 6, Freq= 0, CH_1, rank 0
1506 22:16:36.724170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1507 22:16:36.724268 ==
1508 22:16:36.727739 Write leveling (Byte 0): 26 => 26
1509 22:16:36.731327 Write leveling (Byte 1): 32 => 32
1510 22:16:36.734996 DramcWriteLeveling(PI) end<-----
1511 22:16:36.735079
1512 22:16:36.735144 ==
1513 22:16:36.738853 Dram Type= 6, Freq= 0, CH_1, rank 0
1514 22:16:36.741733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1515 22:16:36.741839 ==
1516 22:16:36.745183 [Gating] SW mode calibration
1517 22:16:36.751541 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1518 22:16:36.758596 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1519 22:16:36.761832 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1520 22:16:36.764908 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1521 22:16:36.768381 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1522 22:16:36.775037 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 22:16:36.778267 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 22:16:36.781875 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 22:16:36.788621 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 22:16:36.791863 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 22:16:36.794749 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 22:16:36.801704 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 22:16:36.804796 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 22:16:36.807946 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 22:16:36.814915 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 22:16:36.818283 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 22:16:36.821793 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 22:16:36.827901 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 22:16:36.831572 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 22:16:36.835111 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1537 22:16:36.841582 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1538 22:16:36.844858 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 22:16:36.847830 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 22:16:36.854353 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 22:16:36.857826 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 22:16:36.861263 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 22:16:36.867795 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 22:16:36.871480 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 22:16:36.874877 0 9 8 | B1->B0 | 2929 2424 | 1 1 | (1 1) (1 1)
1546 22:16:36.881469 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 22:16:36.884491 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 22:16:36.887806 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 22:16:36.894543 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 22:16:36.897436 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1551 22:16:36.901186 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1552 22:16:36.907795 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1553 22:16:36.911006 0 10 8 | B1->B0 | 2f2f 2f2f | 0 0 | (0 0) (0 0)
1554 22:16:36.914484 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 22:16:36.920721 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 22:16:36.924223 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 22:16:36.927830 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 22:16:36.934085 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 22:16:36.937000 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1560 22:16:36.940687 0 11 4 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
1561 22:16:36.947495 0 11 8 | B1->B0 | 3636 3838 | 1 0 | (0 0) (0 0)
1562 22:16:36.951030 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 22:16:36.954019 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 22:16:36.960312 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 22:16:36.963939 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 22:16:36.967188 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1567 22:16:36.970734 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1568 22:16:36.977258 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1569 22:16:36.980227 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1570 22:16:36.983505 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 22:16:36.990462 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 22:16:36.993509 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 22:16:36.997328 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 22:16:37.004010 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 22:16:37.007165 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 22:16:37.010284 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 22:16:37.016821 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 22:16:37.020310 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 22:16:37.023835 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 22:16:37.030370 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 22:16:37.033705 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 22:16:37.036937 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1583 22:16:37.043742 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 22:16:37.047013 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 22:16:37.050338 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1586 22:16:37.057273 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1587 22:16:37.057738 Total UI for P1: 0, mck2ui 16
1588 22:16:37.063998 best dqsien dly found for B0: ( 0, 14, 8)
1589 22:16:37.064463 Total UI for P1: 0, mck2ui 16
1590 22:16:37.070394 best dqsien dly found for B1: ( 0, 14, 10)
1591 22:16:37.073489 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1592 22:16:37.077077 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1593 22:16:37.077540
1594 22:16:37.079993 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1595 22:16:37.083531 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1596 22:16:37.087296 [Gating] SW calibration Done
1597 22:16:37.087798 ==
1598 22:16:37.089875 Dram Type= 6, Freq= 0, CH_1, rank 0
1599 22:16:37.093377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1600 22:16:37.093846 ==
1601 22:16:37.096656 RX Vref Scan: 0
1602 22:16:37.097321
1603 22:16:37.097853 RX Vref 0 -> 0, step: 1
1604 22:16:37.098321
1605 22:16:37.099872 RX Delay -130 -> 252, step: 16
1606 22:16:37.106817 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1607 22:16:37.110404 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1608 22:16:37.113024 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1609 22:16:37.116582 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1610 22:16:37.119919 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1611 22:16:37.126418 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1612 22:16:37.129741 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1613 22:16:37.132665 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1614 22:16:37.136255 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1615 22:16:37.139751 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1616 22:16:37.146446 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1617 22:16:37.149492 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1618 22:16:37.153053 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1619 22:16:37.156406 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1620 22:16:37.159455 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1621 22:16:37.165893 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1622 22:16:37.165976 ==
1623 22:16:37.169548 Dram Type= 6, Freq= 0, CH_1, rank 0
1624 22:16:37.172406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1625 22:16:37.172490 ==
1626 22:16:37.172557 DQS Delay:
1627 22:16:37.175843 DQS0 = 0, DQS1 = 0
1628 22:16:37.175926 DQM Delay:
1629 22:16:37.179002 DQM0 = 80, DQM1 = 71
1630 22:16:37.179085 DQ Delay:
1631 22:16:37.182617 DQ0 =77, DQ1 =77, DQ2 =69, DQ3 =77
1632 22:16:37.186329 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1633 22:16:37.189158 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1634 22:16:37.192710 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1635 22:16:37.192793
1636 22:16:37.192858
1637 22:16:37.192920 ==
1638 22:16:37.196153 Dram Type= 6, Freq= 0, CH_1, rank 0
1639 22:16:37.198871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1640 22:16:37.198955 ==
1641 22:16:37.199021
1642 22:16:37.202428
1643 22:16:37.202510 TX Vref Scan disable
1644 22:16:37.205778 == TX Byte 0 ==
1645 22:16:37.209462 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1646 22:16:37.212246 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1647 22:16:37.216058 == TX Byte 1 ==
1648 22:16:37.219117 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1649 22:16:37.222452 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1650 22:16:37.222535 ==
1651 22:16:37.225659 Dram Type= 6, Freq= 0, CH_1, rank 0
1652 22:16:37.232272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1653 22:16:37.232358 ==
1654 22:16:37.244864 TX Vref=22, minBit 1, minWin=26, winSum=442
1655 22:16:37.248179 TX Vref=24, minBit 1, minWin=27, winSum=444
1656 22:16:37.251459 TX Vref=26, minBit 1, minWin=27, winSum=446
1657 22:16:37.254815 TX Vref=28, minBit 8, minWin=27, winSum=448
1658 22:16:37.258230 TX Vref=30, minBit 9, minWin=27, winSum=455
1659 22:16:37.264799 TX Vref=32, minBit 5, minWin=27, winSum=446
1660 22:16:37.268020 [TxChooseVref] Worse bit 9, Min win 27, Win sum 455, Final Vref 30
1661 22:16:37.268106
1662 22:16:37.271158 Final TX Range 1 Vref 30
1663 22:16:37.271241
1664 22:16:37.271306 ==
1665 22:16:37.274740 Dram Type= 6, Freq= 0, CH_1, rank 0
1666 22:16:37.278161 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1667 22:16:37.278244 ==
1668 22:16:37.278310
1669 22:16:37.278369
1670 22:16:37.281324 TX Vref Scan disable
1671 22:16:37.285073 == TX Byte 0 ==
1672 22:16:37.288064 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1673 22:16:37.292027 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1674 22:16:37.294970 == TX Byte 1 ==
1675 22:16:37.298328 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1676 22:16:37.301567 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1677 22:16:37.305113
1678 22:16:37.305196 [DATLAT]
1679 22:16:37.305261 Freq=800, CH1 RK0
1680 22:16:37.305323
1681 22:16:37.308007 DATLAT Default: 0xa
1682 22:16:37.308090 0, 0xFFFF, sum = 0
1683 22:16:37.311434 1, 0xFFFF, sum = 0
1684 22:16:37.311518 2, 0xFFFF, sum = 0
1685 22:16:37.314962 3, 0xFFFF, sum = 0
1686 22:16:37.315046 4, 0xFFFF, sum = 0
1687 22:16:37.318010 5, 0xFFFF, sum = 0
1688 22:16:37.321299 6, 0xFFFF, sum = 0
1689 22:16:37.321384 7, 0xFFFF, sum = 0
1690 22:16:37.324507 8, 0xFFFF, sum = 0
1691 22:16:37.324591 9, 0x0, sum = 1
1692 22:16:37.324658 10, 0x0, sum = 2
1693 22:16:37.328040 11, 0x0, sum = 3
1694 22:16:37.328124 12, 0x0, sum = 4
1695 22:16:37.331080 best_step = 10
1696 22:16:37.331162
1697 22:16:37.331227 ==
1698 22:16:37.334373 Dram Type= 6, Freq= 0, CH_1, rank 0
1699 22:16:37.338010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1700 22:16:37.338094 ==
1701 22:16:37.341428 RX Vref Scan: 1
1702 22:16:37.341510
1703 22:16:37.341575 Set Vref Range= 32 -> 127
1704 22:16:37.344876
1705 22:16:37.344959 RX Vref 32 -> 127, step: 1
1706 22:16:37.345025
1707 22:16:37.347828 RX Delay -111 -> 252, step: 8
1708 22:16:37.347910
1709 22:16:37.351507 Set Vref, RX VrefLevel [Byte0]: 32
1710 22:16:37.354314 [Byte1]: 32
1711 22:16:37.354397
1712 22:16:37.358016 Set Vref, RX VrefLevel [Byte0]: 33
1713 22:16:37.361008 [Byte1]: 33
1714 22:16:37.365677
1715 22:16:37.365759 Set Vref, RX VrefLevel [Byte0]: 34
1716 22:16:37.368337 [Byte1]: 34
1717 22:16:37.373081
1718 22:16:37.373163 Set Vref, RX VrefLevel [Byte0]: 35
1719 22:16:37.376025 [Byte1]: 35
1720 22:16:37.380705
1721 22:16:37.380788 Set Vref, RX VrefLevel [Byte0]: 36
1722 22:16:37.383552 [Byte1]: 36
1723 22:16:37.387959
1724 22:16:37.388041 Set Vref, RX VrefLevel [Byte0]: 37
1725 22:16:37.391516 [Byte1]: 37
1726 22:16:37.395699
1727 22:16:37.395781 Set Vref, RX VrefLevel [Byte0]: 38
1728 22:16:37.399111 [Byte1]: 38
1729 22:16:37.403803
1730 22:16:37.403885 Set Vref, RX VrefLevel [Byte0]: 39
1731 22:16:37.406560 [Byte1]: 39
1732 22:16:37.411358
1733 22:16:37.411440 Set Vref, RX VrefLevel [Byte0]: 40
1734 22:16:37.414751 [Byte1]: 40
1735 22:16:37.418815
1736 22:16:37.418898 Set Vref, RX VrefLevel [Byte0]: 41
1737 22:16:37.422270 [Byte1]: 41
1738 22:16:37.426387
1739 22:16:37.426469 Set Vref, RX VrefLevel [Byte0]: 42
1740 22:16:37.429666 [Byte1]: 42
1741 22:16:37.434020
1742 22:16:37.437027 Set Vref, RX VrefLevel [Byte0]: 43
1743 22:16:37.440459 [Byte1]: 43
1744 22:16:37.440541
1745 22:16:37.443500 Set Vref, RX VrefLevel [Byte0]: 44
1746 22:16:37.447373 [Byte1]: 44
1747 22:16:37.447455
1748 22:16:37.450626 Set Vref, RX VrefLevel [Byte0]: 45
1749 22:16:37.453432 [Byte1]: 45
1750 22:16:37.456947
1751 22:16:37.457030 Set Vref, RX VrefLevel [Byte0]: 46
1752 22:16:37.460326 [Byte1]: 46
1753 22:16:37.464500
1754 22:16:37.464582 Set Vref, RX VrefLevel [Byte0]: 47
1755 22:16:37.468085 [Byte1]: 47
1756 22:16:37.472302
1757 22:16:37.472384 Set Vref, RX VrefLevel [Byte0]: 48
1758 22:16:37.475712 [Byte1]: 48
1759 22:16:37.479810
1760 22:16:37.479893 Set Vref, RX VrefLevel [Byte0]: 49
1761 22:16:37.482979 [Byte1]: 49
1762 22:16:37.487737
1763 22:16:37.487819 Set Vref, RX VrefLevel [Byte0]: 50
1764 22:16:37.491082 [Byte1]: 50
1765 22:16:37.495114
1766 22:16:37.495196 Set Vref, RX VrefLevel [Byte0]: 51
1767 22:16:37.498749 [Byte1]: 51
1768 22:16:37.502899
1769 22:16:37.502981 Set Vref, RX VrefLevel [Byte0]: 52
1770 22:16:37.506184 [Byte1]: 52
1771 22:16:37.510771
1772 22:16:37.510853 Set Vref, RX VrefLevel [Byte0]: 53
1773 22:16:37.513660 [Byte1]: 53
1774 22:16:37.518143
1775 22:16:37.518226 Set Vref, RX VrefLevel [Byte0]: 54
1776 22:16:37.521682 [Byte1]: 54
1777 22:16:37.525769
1778 22:16:37.525851 Set Vref, RX VrefLevel [Byte0]: 55
1779 22:16:37.529156 [Byte1]: 55
1780 22:16:37.533491
1781 22:16:37.536967 Set Vref, RX VrefLevel [Byte0]: 56
1782 22:16:37.540055 [Byte1]: 56
1783 22:16:37.540138
1784 22:16:37.543203 Set Vref, RX VrefLevel [Byte0]: 57
1785 22:16:37.546462 [Byte1]: 57
1786 22:16:37.546545
1787 22:16:37.549845 Set Vref, RX VrefLevel [Byte0]: 58
1788 22:16:37.553114 [Byte1]: 58
1789 22:16:37.556348
1790 22:16:37.556430 Set Vref, RX VrefLevel [Byte0]: 59
1791 22:16:37.559821 [Byte1]: 59
1792 22:16:37.563760
1793 22:16:37.563842 Set Vref, RX VrefLevel [Byte0]: 60
1794 22:16:37.567389 [Byte1]: 60
1795 22:16:37.571574
1796 22:16:37.571699 Set Vref, RX VrefLevel [Byte0]: 61
1797 22:16:37.575010 [Byte1]: 61
1798 22:16:37.579137
1799 22:16:37.579220 Set Vref, RX VrefLevel [Byte0]: 62
1800 22:16:37.582356 [Byte1]: 62
1801 22:16:37.586870
1802 22:16:37.586952 Set Vref, RX VrefLevel [Byte0]: 63
1803 22:16:37.590237 [Byte1]: 63
1804 22:16:37.594715
1805 22:16:37.594797 Set Vref, RX VrefLevel [Byte0]: 64
1806 22:16:37.597901 [Byte1]: 64
1807 22:16:37.602241
1808 22:16:37.602323 Set Vref, RX VrefLevel [Byte0]: 65
1809 22:16:37.605326 [Byte1]: 65
1810 22:16:37.609891
1811 22:16:37.609973 Set Vref, RX VrefLevel [Byte0]: 66
1812 22:16:37.613715 [Byte1]: 66
1813 22:16:37.617474
1814 22:16:37.617556 Set Vref, RX VrefLevel [Byte0]: 67
1815 22:16:37.621022 [Byte1]: 67
1816 22:16:37.625011
1817 22:16:37.625093 Set Vref, RX VrefLevel [Byte0]: 68
1818 22:16:37.628600 [Byte1]: 68
1819 22:16:37.632753
1820 22:16:37.636283 Set Vref, RX VrefLevel [Byte0]: 69
1821 22:16:37.639368 [Byte1]: 69
1822 22:16:37.639450
1823 22:16:37.642372 Set Vref, RX VrefLevel [Byte0]: 70
1824 22:16:37.645799 [Byte1]: 70
1825 22:16:37.645882
1826 22:16:37.649451 Set Vref, RX VrefLevel [Byte0]: 71
1827 22:16:37.652623 [Byte1]: 71
1828 22:16:37.655819
1829 22:16:37.655901 Set Vref, RX VrefLevel [Byte0]: 72
1830 22:16:37.659205 [Byte1]: 72
1831 22:16:37.663566
1832 22:16:37.663687 Set Vref, RX VrefLevel [Byte0]: 73
1833 22:16:37.666538 [Byte1]: 73
1834 22:16:37.671075
1835 22:16:37.671157 Set Vref, RX VrefLevel [Byte0]: 74
1836 22:16:37.674537 [Byte1]: 74
1837 22:16:37.678535
1838 22:16:37.678637 Final RX Vref Byte 0 = 61 to rank0
1839 22:16:37.682494 Final RX Vref Byte 1 = 54 to rank0
1840 22:16:37.685362 Final RX Vref Byte 0 = 61 to rank1
1841 22:16:37.688853 Final RX Vref Byte 1 = 54 to rank1==
1842 22:16:37.691897 Dram Type= 6, Freq= 0, CH_1, rank 0
1843 22:16:37.698900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1844 22:16:37.699005 ==
1845 22:16:37.699099 DQS Delay:
1846 22:16:37.699188 DQS0 = 0, DQS1 = 0
1847 22:16:37.702086 DQM Delay:
1848 22:16:37.702168 DQM0 = 80, DQM1 = 72
1849 22:16:37.705637 DQ Delay:
1850 22:16:37.708579 DQ0 =88, DQ1 =76, DQ2 =68, DQ3 =76
1851 22:16:37.711961 DQ4 =76, DQ5 =92, DQ6 =92, DQ7 =76
1852 22:16:37.715740 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =68
1853 22:16:37.718650 DQ12 =80, DQ13 =80, DQ14 =76, DQ15 =80
1854 22:16:37.718732
1855 22:16:37.718797
1856 22:16:37.724984 [DQSOSCAuto] RK0, (LSB)MR18= 0x111b, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 405 ps
1857 22:16:37.728432 CH1 RK0: MR19=606, MR18=111B
1858 22:16:37.734781 CH1_RK0: MR19=0x606, MR18=0x111B, DQSOSC=403, MR23=63, INC=90, DEC=60
1859 22:16:37.734867
1860 22:16:37.738387 ----->DramcWriteLeveling(PI) begin...
1861 22:16:37.738470 ==
1862 22:16:37.741827 Dram Type= 6, Freq= 0, CH_1, rank 1
1863 22:16:37.745174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1864 22:16:37.745256 ==
1865 22:16:37.748298 Write leveling (Byte 0): 30 => 30
1866 22:16:37.751583 Write leveling (Byte 1): 29 => 29
1867 22:16:37.754750 DramcWriteLeveling(PI) end<-----
1868 22:16:37.754833
1869 22:16:37.754897 ==
1870 22:16:37.758543 Dram Type= 6, Freq= 0, CH_1, rank 1
1871 22:16:37.761791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1872 22:16:37.761874 ==
1873 22:16:37.764771 [Gating] SW mode calibration
1874 22:16:37.771294 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1875 22:16:37.778162 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1876 22:16:37.781607 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1877 22:16:37.788109 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1878 22:16:37.791590 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1879 22:16:37.794890 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 22:16:37.801157 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 22:16:37.805070 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 22:16:37.808017 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 22:16:37.811542 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 22:16:37.817890 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 22:16:37.821259 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 22:16:37.824606 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 22:16:37.831115 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 22:16:37.834471 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 22:16:37.838119 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 22:16:37.844421 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1891 22:16:37.848141 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 22:16:37.851123 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 22:16:37.858113 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1894 22:16:37.861224 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1895 22:16:37.864571 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 22:16:37.870910 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 22:16:37.874212 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 22:16:37.877744 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 22:16:37.884016 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 22:16:37.887499 0 9 0 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1901 22:16:37.890664 0 9 4 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
1902 22:16:37.897684 0 9 8 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
1903 22:16:37.900604 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1904 22:16:37.904029 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1905 22:16:37.910951 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1906 22:16:37.914129 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1907 22:16:37.917319 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1908 22:16:37.924027 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1909 22:16:37.927184 0 10 4 | B1->B0 | 3333 2f2f | 0 0 | (1 0) (0 0)
1910 22:16:37.930525 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1911 22:16:37.937400 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 22:16:37.940204 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 22:16:37.943897 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 22:16:37.950375 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 22:16:37.953217 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 22:16:37.956630 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 22:16:37.963589 0 11 4 | B1->B0 | 2a2a 3636 | 0 0 | (0 0) (0 0)
1918 22:16:37.966829 0 11 8 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
1919 22:16:37.970181 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1920 22:16:37.977123 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1921 22:16:37.979819 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1922 22:16:37.983674 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1923 22:16:37.990196 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1924 22:16:37.993090 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1925 22:16:37.996851 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1926 22:16:38.003575 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 22:16:38.006353 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 22:16:38.009684 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 22:16:38.017024 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 22:16:38.019794 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1931 22:16:38.022984 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1932 22:16:38.030005 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1933 22:16:38.032968 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1934 22:16:38.036411 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1935 22:16:38.039854 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1936 22:16:38.046555 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1937 22:16:38.049482 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1938 22:16:38.053043 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1939 22:16:38.059731 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1940 22:16:38.062676 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 22:16:38.066280 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1942 22:16:38.072698 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1943 22:16:38.076169 Total UI for P1: 0, mck2ui 16
1944 22:16:38.079882 best dqsien dly found for B0: ( 0, 14, 4)
1945 22:16:38.083186 Total UI for P1: 0, mck2ui 16
1946 22:16:38.085884 best dqsien dly found for B1: ( 0, 14, 6)
1947 22:16:38.089500 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1948 22:16:38.092621 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1949 22:16:38.092704
1950 22:16:38.096016 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1951 22:16:38.099472 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1952 22:16:38.102348 [Gating] SW calibration Done
1953 22:16:38.102430 ==
1954 22:16:38.105813 Dram Type= 6, Freq= 0, CH_1, rank 1
1955 22:16:38.109228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1956 22:16:38.109311 ==
1957 22:16:38.112477 RX Vref Scan: 0
1958 22:16:38.112560
1959 22:16:38.112625 RX Vref 0 -> 0, step: 1
1960 22:16:38.112685
1961 22:16:38.115709 RX Delay -130 -> 252, step: 16
1962 22:16:38.122688 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1963 22:16:38.125818 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1964 22:16:38.129266 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1965 22:16:38.132475 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1966 22:16:38.135872 iDelay=222, Bit 4, Center 69 (-50 ~ 189) 240
1967 22:16:38.142757 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1968 22:16:38.145651 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1969 22:16:38.149295 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1970 22:16:38.152761 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1971 22:16:38.155520 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1972 22:16:38.159109 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1973 22:16:38.165651 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1974 22:16:38.169384 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1975 22:16:38.172595 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1976 22:16:38.175810 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1977 22:16:38.182455 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1978 22:16:38.182542 ==
1979 22:16:38.185592 Dram Type= 6, Freq= 0, CH_1, rank 1
1980 22:16:38.189068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1981 22:16:38.189151 ==
1982 22:16:38.189218 DQS Delay:
1983 22:16:38.192261 DQS0 = 0, DQS1 = 0
1984 22:16:38.192343 DQM Delay:
1985 22:16:38.195453 DQM0 = 78, DQM1 = 72
1986 22:16:38.195536 DQ Delay:
1987 22:16:38.199102 DQ0 =85, DQ1 =69, DQ2 =69, DQ3 =77
1988 22:16:38.202046 DQ4 =69, DQ5 =85, DQ6 =93, DQ7 =77
1989 22:16:38.205476 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
1990 22:16:38.208472 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1991 22:16:38.208555
1992 22:16:38.208621
1993 22:16:38.208682 ==
1994 22:16:38.212043 Dram Type= 6, Freq= 0, CH_1, rank 1
1995 22:16:38.215385 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1996 22:16:38.218935 ==
1997 22:16:38.219017
1998 22:16:38.219083
1999 22:16:38.219144 TX Vref Scan disable
2000 22:16:38.221794 == TX Byte 0 ==
2001 22:16:38.225204 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
2002 22:16:38.228498 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
2003 22:16:38.232023 == TX Byte 1 ==
2004 22:16:38.235046 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2005 22:16:38.238560 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2006 22:16:38.241780 ==
2007 22:16:38.241862 Dram Type= 6, Freq= 0, CH_1, rank 1
2008 22:16:38.248434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2009 22:16:38.248517 ==
2010 22:16:38.260710 TX Vref=22, minBit 1, minWin=27, winSum=445
2011 22:16:38.263913 TX Vref=24, minBit 1, minWin=27, winSum=446
2012 22:16:38.267501 TX Vref=26, minBit 1, minWin=27, winSum=452
2013 22:16:38.270552 TX Vref=28, minBit 5, minWin=27, winSum=455
2014 22:16:38.273970 TX Vref=30, minBit 1, minWin=27, winSum=456
2015 22:16:38.277308 TX Vref=32, minBit 1, minWin=27, winSum=455
2016 22:16:38.283755 [TxChooseVref] Worse bit 1, Min win 27, Win sum 456, Final Vref 30
2017 22:16:38.283842
2018 22:16:38.287450 Final TX Range 1 Vref 30
2019 22:16:38.287533
2020 22:16:38.287642 ==
2021 22:16:38.290732 Dram Type= 6, Freq= 0, CH_1, rank 1
2022 22:16:38.293978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2023 22:16:38.294062 ==
2024 22:16:38.294127
2025 22:16:38.294188
2026 22:16:38.297275 TX Vref Scan disable
2027 22:16:38.300554 == TX Byte 0 ==
2028 22:16:38.303843 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2029 22:16:38.307482 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2030 22:16:38.310352 == TX Byte 1 ==
2031 22:16:38.313977 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2032 22:16:38.317242 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2033 22:16:38.320725
2034 22:16:38.320807 [DATLAT]
2035 22:16:38.320873 Freq=800, CH1 RK1
2036 22:16:38.320935
2037 22:16:38.323751 DATLAT Default: 0xa
2038 22:16:38.323844 0, 0xFFFF, sum = 0
2039 22:16:38.327307 1, 0xFFFF, sum = 0
2040 22:16:38.327417 2, 0xFFFF, sum = 0
2041 22:16:38.330140 3, 0xFFFF, sum = 0
2042 22:16:38.330242 4, 0xFFFF, sum = 0
2043 22:16:38.333557 5, 0xFFFF, sum = 0
2044 22:16:38.337465 6, 0xFFFF, sum = 0
2045 22:16:38.337549 7, 0xFFFF, sum = 0
2046 22:16:38.340578 8, 0xFFFF, sum = 0
2047 22:16:38.340662 9, 0x0, sum = 1
2048 22:16:38.340729 10, 0x0, sum = 2
2049 22:16:38.343910 11, 0x0, sum = 3
2050 22:16:38.343994 12, 0x0, sum = 4
2051 22:16:38.347059 best_step = 10
2052 22:16:38.347141
2053 22:16:38.347207 ==
2054 22:16:38.350635 Dram Type= 6, Freq= 0, CH_1, rank 1
2055 22:16:38.353768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2056 22:16:38.353851 ==
2057 22:16:38.357296 RX Vref Scan: 0
2058 22:16:38.357378
2059 22:16:38.357444 RX Vref 0 -> 0, step: 1
2060 22:16:38.357506
2061 22:16:38.360218 RX Delay -111 -> 252, step: 8
2062 22:16:38.367204 iDelay=209, Bit 0, Center 84 (-39 ~ 208) 248
2063 22:16:38.370206 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
2064 22:16:38.373818 iDelay=209, Bit 2, Center 68 (-55 ~ 192) 248
2065 22:16:38.377252 iDelay=209, Bit 3, Center 76 (-47 ~ 200) 248
2066 22:16:38.380320 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
2067 22:16:38.386826 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
2068 22:16:38.390664 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
2069 22:16:38.393364 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
2070 22:16:38.397104 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
2071 22:16:38.400166 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2072 22:16:38.406664 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2073 22:16:38.410191 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2074 22:16:38.413671 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2075 22:16:38.416578 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2076 22:16:38.423531 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2077 22:16:38.426854 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2078 22:16:38.426937 ==
2079 22:16:38.430040 Dram Type= 6, Freq= 0, CH_1, rank 1
2080 22:16:38.433593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2081 22:16:38.433676 ==
2082 22:16:38.433743 DQS Delay:
2083 22:16:38.436994 DQS0 = 0, DQS1 = 0
2084 22:16:38.437077 DQM Delay:
2085 22:16:38.440269 DQM0 = 78, DQM1 = 73
2086 22:16:38.440351 DQ Delay:
2087 22:16:38.443169 DQ0 =84, DQ1 =72, DQ2 =68, DQ3 =76
2088 22:16:38.446720 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2089 22:16:38.450278 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
2090 22:16:38.453487 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
2091 22:16:38.453570
2092 22:16:38.453636
2093 22:16:38.463186 [DQSOSCAuto] RK1, (LSB)MR18= 0x223b, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
2094 22:16:38.463271 CH1 RK1: MR19=606, MR18=223B
2095 22:16:38.470288 CH1_RK1: MR19=0x606, MR18=0x223B, DQSOSC=394, MR23=63, INC=95, DEC=63
2096 22:16:38.473326 [RxdqsGatingPostProcess] freq 800
2097 22:16:38.480364 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2098 22:16:38.483249 Pre-setting of DQS Precalculation
2099 22:16:38.486631 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2100 22:16:38.492936 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2101 22:16:38.503174 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2102 22:16:38.503259
2103 22:16:38.503325
2104 22:16:38.506209 [Calibration Summary] 1600 Mbps
2105 22:16:38.506292 CH 0, Rank 0
2106 22:16:38.509660 SW Impedance : PASS
2107 22:16:38.509743 DUTY Scan : NO K
2108 22:16:38.512912 ZQ Calibration : PASS
2109 22:16:38.512995 Jitter Meter : NO K
2110 22:16:38.516367 CBT Training : PASS
2111 22:16:38.519688 Write leveling : PASS
2112 22:16:38.519771 RX DQS gating : PASS
2113 22:16:38.523311 RX DQ/DQS(RDDQC) : PASS
2114 22:16:38.526258 TX DQ/DQS : PASS
2115 22:16:38.526341 RX DATLAT : PASS
2116 22:16:38.529976 RX DQ/DQS(Engine): PASS
2117 22:16:38.532886 TX OE : NO K
2118 22:16:38.532970 All Pass.
2119 22:16:38.533036
2120 22:16:38.533097 CH 0, Rank 1
2121 22:16:38.535973 SW Impedance : PASS
2122 22:16:38.539889 DUTY Scan : NO K
2123 22:16:38.539971 ZQ Calibration : PASS
2124 22:16:38.542722 Jitter Meter : NO K
2125 22:16:38.546022 CBT Training : PASS
2126 22:16:38.546105 Write leveling : PASS
2127 22:16:38.549580 RX DQS gating : PASS
2128 22:16:38.552978 RX DQ/DQS(RDDQC) : PASS
2129 22:16:38.553061 TX DQ/DQS : PASS
2130 22:16:38.556427 RX DATLAT : PASS
2131 22:16:38.559984 RX DQ/DQS(Engine): PASS
2132 22:16:38.560067 TX OE : NO K
2133 22:16:38.560133 All Pass.
2134 22:16:38.562927
2135 22:16:38.563009 CH 1, Rank 0
2136 22:16:38.566219 SW Impedance : PASS
2137 22:16:38.566302 DUTY Scan : NO K
2138 22:16:38.569511 ZQ Calibration : PASS
2139 22:16:38.572821 Jitter Meter : NO K
2140 22:16:38.572904 CBT Training : PASS
2141 22:16:38.575864 Write leveling : PASS
2142 22:16:38.575947 RX DQS gating : PASS
2143 22:16:38.579377 RX DQ/DQS(RDDQC) : PASS
2144 22:16:38.582798 TX DQ/DQS : PASS
2145 22:16:38.582881 RX DATLAT : PASS
2146 22:16:38.586235 RX DQ/DQS(Engine): PASS
2147 22:16:38.589293 TX OE : NO K
2148 22:16:38.589377 All Pass.
2149 22:16:38.589442
2150 22:16:38.589503 CH 1, Rank 1
2151 22:16:38.592620 SW Impedance : PASS
2152 22:16:38.595985 DUTY Scan : NO K
2153 22:16:38.596068 ZQ Calibration : PASS
2154 22:16:38.599142 Jitter Meter : NO K
2155 22:16:38.602260 CBT Training : PASS
2156 22:16:38.602343 Write leveling : PASS
2157 22:16:38.606151 RX DQS gating : PASS
2158 22:16:38.609324 RX DQ/DQS(RDDQC) : PASS
2159 22:16:38.609406 TX DQ/DQS : PASS
2160 22:16:38.612658 RX DATLAT : PASS
2161 22:16:38.615950 RX DQ/DQS(Engine): PASS
2162 22:16:38.616033 TX OE : NO K
2163 22:16:38.616098 All Pass.
2164 22:16:38.619106
2165 22:16:38.619188 DramC Write-DBI off
2166 22:16:38.622436 PER_BANK_REFRESH: Hybrid Mode
2167 22:16:38.622520 TX_TRACKING: ON
2168 22:16:38.625995 [GetDramInforAfterCalByMRR] Vendor 6.
2169 22:16:38.629248 [GetDramInforAfterCalByMRR] Revision 606.
2170 22:16:38.635509 [GetDramInforAfterCalByMRR] Revision 2 0.
2171 22:16:38.635598 MR0 0x3b3b
2172 22:16:38.635666 MR8 0x5151
2173 22:16:38.639227 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2174 22:16:38.639310
2175 22:16:38.642627 MR0 0x3b3b
2176 22:16:38.642709 MR8 0x5151
2177 22:16:38.645765 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2178 22:16:38.645848
2179 22:16:38.655794 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2180 22:16:38.658726 [FAST_K] Save calibration result to emmc
2181 22:16:38.662266 [FAST_K] Save calibration result to emmc
2182 22:16:38.665642 dram_init: config_dvfs: 1
2183 22:16:38.668557 dramc_set_vcore_voltage set vcore to 662500
2184 22:16:38.671991 Read voltage for 1200, 2
2185 22:16:38.672073 Vio18 = 0
2186 22:16:38.672139 Vcore = 662500
2187 22:16:38.675484 Vdram = 0
2188 22:16:38.675567 Vddq = 0
2189 22:16:38.675644 Vmddr = 0
2190 22:16:38.682093 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2191 22:16:38.685093 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2192 22:16:38.688577 MEM_TYPE=3, freq_sel=15
2193 22:16:38.692116 sv_algorithm_assistance_LP4_1600
2194 22:16:38.695010 ============ PULL DRAM RESETB DOWN ============
2195 22:16:38.698553 ========== PULL DRAM RESETB DOWN end =========
2196 22:16:38.705188 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2197 22:16:38.708420 ===================================
2198 22:16:38.708503 LPDDR4 DRAM CONFIGURATION
2199 22:16:38.712101 ===================================
2200 22:16:38.714929 EX_ROW_EN[0] = 0x0
2201 22:16:38.718582 EX_ROW_EN[1] = 0x0
2202 22:16:38.718665 LP4Y_EN = 0x0
2203 22:16:38.721912 WORK_FSP = 0x0
2204 22:16:38.721994 WL = 0x4
2205 22:16:38.725099 RL = 0x4
2206 22:16:38.725181 BL = 0x2
2207 22:16:38.728563 RPST = 0x0
2208 22:16:38.728646 RD_PRE = 0x0
2209 22:16:38.731981 WR_PRE = 0x1
2210 22:16:38.732084 WR_PST = 0x0
2211 22:16:38.734853 DBI_WR = 0x0
2212 22:16:38.734974 DBI_RD = 0x0
2213 22:16:38.738241 OTF = 0x1
2214 22:16:38.741596 ===================================
2215 22:16:38.745416 ===================================
2216 22:16:38.745533 ANA top config
2217 22:16:38.748067 ===================================
2218 22:16:38.751483 DLL_ASYNC_EN = 0
2219 22:16:38.754564 ALL_SLAVE_EN = 0
2220 22:16:38.758265 NEW_RANK_MODE = 1
2221 22:16:38.758351 DLL_IDLE_MODE = 1
2222 22:16:38.761726 LP45_APHY_COMB_EN = 1
2223 22:16:38.764678 TX_ODT_DIS = 1
2224 22:16:38.768176 NEW_8X_MODE = 1
2225 22:16:38.771475 ===================================
2226 22:16:38.774483 ===================================
2227 22:16:38.778005 data_rate = 2400
2228 22:16:38.778084 CKR = 1
2229 22:16:38.781337 DQ_P2S_RATIO = 8
2230 22:16:38.784525 ===================================
2231 22:16:38.787875 CA_P2S_RATIO = 8
2232 22:16:38.791462 DQ_CA_OPEN = 0
2233 22:16:38.794350 DQ_SEMI_OPEN = 0
2234 22:16:38.797878 CA_SEMI_OPEN = 0
2235 22:16:38.797995 CA_FULL_RATE = 0
2236 22:16:38.801314 DQ_CKDIV4_EN = 0
2237 22:16:38.804285 CA_CKDIV4_EN = 0
2238 22:16:38.807900 CA_PREDIV_EN = 0
2239 22:16:38.811106 PH8_DLY = 17
2240 22:16:38.814421 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2241 22:16:38.817600 DQ_AAMCK_DIV = 4
2242 22:16:38.817697 CA_AAMCK_DIV = 4
2243 22:16:38.821176 CA_ADMCK_DIV = 4
2244 22:16:38.824500 DQ_TRACK_CA_EN = 0
2245 22:16:38.827836 CA_PICK = 1200
2246 22:16:38.830942 CA_MCKIO = 1200
2247 22:16:38.834275 MCKIO_SEMI = 0
2248 22:16:38.837415 PLL_FREQ = 2366
2249 22:16:38.837516 DQ_UI_PI_RATIO = 32
2250 22:16:38.840931 CA_UI_PI_RATIO = 0
2251 22:16:38.844343 ===================================
2252 22:16:38.847931 ===================================
2253 22:16:38.850853 memory_type:LPDDR4
2254 22:16:38.854201 GP_NUM : 10
2255 22:16:38.854284 SRAM_EN : 1
2256 22:16:38.857724 MD32_EN : 0
2257 22:16:38.860547 ===================================
2258 22:16:38.863844 [ANA_INIT] >>>>>>>>>>>>>>
2259 22:16:38.863927 <<<<<< [CONFIGURE PHASE]: ANA_TX
2260 22:16:38.867491 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2261 22:16:38.870572 ===================================
2262 22:16:38.873874 data_rate = 2400,PCW = 0X5b00
2263 22:16:38.877243 ===================================
2264 22:16:38.880840 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2265 22:16:38.887294 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2266 22:16:38.893621 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2267 22:16:38.897104 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2268 22:16:38.900695 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2269 22:16:38.903815 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2270 22:16:38.907216 [ANA_INIT] flow start
2271 22:16:38.907299 [ANA_INIT] PLL >>>>>>>>
2272 22:16:38.910842 [ANA_INIT] PLL <<<<<<<<
2273 22:16:38.913781 [ANA_INIT] MIDPI >>>>>>>>
2274 22:16:38.913863 [ANA_INIT] MIDPI <<<<<<<<
2275 22:16:38.917256 [ANA_INIT] DLL >>>>>>>>
2276 22:16:38.920315 [ANA_INIT] DLL <<<<<<<<
2277 22:16:38.920398 [ANA_INIT] flow end
2278 22:16:38.927043 ============ LP4 DIFF to SE enter ============
2279 22:16:38.930119 ============ LP4 DIFF to SE exit ============
2280 22:16:38.933845 [ANA_INIT] <<<<<<<<<<<<<
2281 22:16:38.936558 [Flow] Enable top DCM control >>>>>
2282 22:16:38.940328 [Flow] Enable top DCM control <<<<<
2283 22:16:38.940412 Enable DLL master slave shuffle
2284 22:16:38.947273 ==============================================================
2285 22:16:38.950004 Gating Mode config
2286 22:16:38.953711 ==============================================================
2287 22:16:38.956521 Config description:
2288 22:16:38.966677 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2289 22:16:38.973715 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2290 22:16:38.976774 SELPH_MODE 0: By rank 1: By Phase
2291 22:16:38.983273 ==============================================================
2292 22:16:38.986808 GAT_TRACK_EN = 1
2293 22:16:38.989857 RX_GATING_MODE = 2
2294 22:16:38.993298 RX_GATING_TRACK_MODE = 2
2295 22:16:38.996505 SELPH_MODE = 1
2296 22:16:39.000776 PICG_EARLY_EN = 1
2297 22:16:39.001268 VALID_LAT_VALUE = 1
2298 22:16:39.006648 ==============================================================
2299 22:16:39.010190 Enter into Gating configuration >>>>
2300 22:16:39.013665 Exit from Gating configuration <<<<
2301 22:16:39.017050 Enter into DVFS_PRE_config >>>>>
2302 22:16:39.026544 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2303 22:16:39.030069 Exit from DVFS_PRE_config <<<<<
2304 22:16:39.033273 Enter into PICG configuration >>>>
2305 22:16:39.036321 Exit from PICG configuration <<<<
2306 22:16:39.040008 [RX_INPUT] configuration >>>>>
2307 22:16:39.043274 [RX_INPUT] configuration <<<<<
2308 22:16:39.049697 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2309 22:16:39.053046 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2310 22:16:39.060052 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2311 22:16:39.066352 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2312 22:16:39.073398 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2313 22:16:39.079816 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2314 22:16:39.082933 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2315 22:16:39.086332 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2316 22:16:39.089804 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2317 22:16:39.095948 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2318 22:16:39.099842 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2319 22:16:39.102589 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2320 22:16:39.105927 ===================================
2321 22:16:39.109298 LPDDR4 DRAM CONFIGURATION
2322 22:16:39.112299 ===================================
2323 22:16:39.112497 EX_ROW_EN[0] = 0x0
2324 22:16:39.115765 EX_ROW_EN[1] = 0x0
2325 22:16:39.119461 LP4Y_EN = 0x0
2326 22:16:39.119569 WORK_FSP = 0x0
2327 22:16:39.122283 WL = 0x4
2328 22:16:39.122368 RL = 0x4
2329 22:16:39.125436 BL = 0x2
2330 22:16:39.125534 RPST = 0x0
2331 22:16:39.128805 RD_PRE = 0x0
2332 22:16:39.128888 WR_PRE = 0x1
2333 22:16:39.132220 WR_PST = 0x0
2334 22:16:39.132304 DBI_WR = 0x0
2335 22:16:39.135289 DBI_RD = 0x0
2336 22:16:39.135373 OTF = 0x1
2337 22:16:39.138618 ===================================
2338 22:16:39.142024 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2339 22:16:39.148848 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2340 22:16:39.152467 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2341 22:16:39.155250 ===================================
2342 22:16:39.158607 LPDDR4 DRAM CONFIGURATION
2343 22:16:39.161953 ===================================
2344 22:16:39.162037 EX_ROW_EN[0] = 0x10
2345 22:16:39.164974 EX_ROW_EN[1] = 0x0
2346 22:16:39.165059 LP4Y_EN = 0x0
2347 22:16:39.168419 WORK_FSP = 0x0
2348 22:16:39.171903 WL = 0x4
2349 22:16:39.171988 RL = 0x4
2350 22:16:39.175509 BL = 0x2
2351 22:16:39.175622 RPST = 0x0
2352 22:16:39.178255 RD_PRE = 0x0
2353 22:16:39.178340 WR_PRE = 0x1
2354 22:16:39.181787 WR_PST = 0x0
2355 22:16:39.181874 DBI_WR = 0x0
2356 22:16:39.185135 DBI_RD = 0x0
2357 22:16:39.185216 OTF = 0x1
2358 22:16:39.188425 ===================================
2359 22:16:39.195182 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2360 22:16:39.195266 ==
2361 22:16:39.198302 Dram Type= 6, Freq= 0, CH_0, rank 0
2362 22:16:39.201573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2363 22:16:39.204967 ==
2364 22:16:39.205047 [Duty_Offset_Calibration]
2365 22:16:39.208013 B0:2 B1:0 CA:3
2366 22:16:39.208093
2367 22:16:39.211371 [DutyScan_Calibration_Flow] k_type=0
2368 22:16:39.219955
2369 22:16:39.220035 ==CLK 0==
2370 22:16:39.223534 Final CLK duty delay cell = 0
2371 22:16:39.226260 [0] MAX Duty = 5031%(X100), DQS PI = 12
2372 22:16:39.229655 [0] MIN Duty = 4875%(X100), DQS PI = 58
2373 22:16:39.233396 [0] AVG Duty = 4953%(X100)
2374 22:16:39.233495
2375 22:16:39.236441 CH0 CLK Duty spec in!! Max-Min= 156%
2376 22:16:39.239648 [DutyScan_Calibration_Flow] ====Done====
2377 22:16:39.239729
2378 22:16:39.242942 [DutyScan_Calibration_Flow] k_type=1
2379 22:16:39.258657
2380 22:16:39.258737 ==DQS 0 ==
2381 22:16:39.261756 Final DQS duty delay cell = 0
2382 22:16:39.265158 [0] MAX Duty = 5093%(X100), DQS PI = 28
2383 22:16:39.268423 [0] MIN Duty = 4907%(X100), DQS PI = 2
2384 22:16:39.268504 [0] AVG Duty = 5000%(X100)
2385 22:16:39.272079
2386 22:16:39.272159 ==DQS 1 ==
2387 22:16:39.274864 Final DQS duty delay cell = -4
2388 22:16:39.278591 [-4] MAX Duty = 4969%(X100), DQS PI = 22
2389 22:16:39.281800 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2390 22:16:39.285218 [-4] AVG Duty = 4922%(X100)
2391 22:16:39.285298
2392 22:16:39.287980 CH0 DQS 0 Duty spec in!! Max-Min= 186%
2393 22:16:39.288061
2394 22:16:39.291511 CH0 DQS 1 Duty spec in!! Max-Min= 94%
2395 22:16:39.294902 [DutyScan_Calibration_Flow] ====Done====
2396 22:16:39.294984
2397 22:16:39.298142 [DutyScan_Calibration_Flow] k_type=3
2398 22:16:39.315833
2399 22:16:39.315920 ==DQM 0 ==
2400 22:16:39.319189 Final DQM duty delay cell = 0
2401 22:16:39.322169 [0] MAX Duty = 5124%(X100), DQS PI = 28
2402 22:16:39.325702 [0] MIN Duty = 4876%(X100), DQS PI = 0
2403 22:16:39.328846 [0] AVG Duty = 5000%(X100)
2404 22:16:39.328927
2405 22:16:39.328990 ==DQM 1 ==
2406 22:16:39.332329 Final DQM duty delay cell = 4
2407 22:16:39.335719 [4] MAX Duty = 5124%(X100), DQS PI = 0
2408 22:16:39.338695 [4] MIN Duty = 5031%(X100), DQS PI = 12
2409 22:16:39.342027 [4] AVG Duty = 5077%(X100)
2410 22:16:39.342109
2411 22:16:39.346016 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2412 22:16:39.346099
2413 22:16:39.348764 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2414 22:16:39.352041 [DutyScan_Calibration_Flow] ====Done====
2415 22:16:39.352124
2416 22:16:39.355145 [DutyScan_Calibration_Flow] k_type=2
2417 22:16:39.370305
2418 22:16:39.370388 ==DQ 0 ==
2419 22:16:39.373778 Final DQ duty delay cell = -4
2420 22:16:39.377288 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2421 22:16:39.380192 [-4] MIN Duty = 4907%(X100), DQS PI = 52
2422 22:16:39.384104 [-4] AVG Duty = 4969%(X100)
2423 22:16:39.384187
2424 22:16:39.384252 ==DQ 1 ==
2425 22:16:39.386782 Final DQ duty delay cell = -4
2426 22:16:39.390342 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2427 22:16:39.393975 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2428 22:16:39.396879 [-4] AVG Duty = 4938%(X100)
2429 22:16:39.396961
2430 22:16:39.400261 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2431 22:16:39.400343
2432 22:16:39.403279 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2433 22:16:39.406815 [DutyScan_Calibration_Flow] ====Done====
2434 22:16:39.406937 ==
2435 22:16:39.410324 Dram Type= 6, Freq= 0, CH_1, rank 0
2436 22:16:39.413616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2437 22:16:39.413733 ==
2438 22:16:39.417096 [Duty_Offset_Calibration]
2439 22:16:39.417181 B0:1 B1:-2 CA:0
2440 22:16:39.419940
2441 22:16:39.422985 [DutyScan_Calibration_Flow] k_type=0
2442 22:16:39.431335
2443 22:16:39.431448 ==CLK 0==
2444 22:16:39.434212 Final CLK duty delay cell = 0
2445 22:16:39.437605 [0] MAX Duty = 5031%(X100), DQS PI = 18
2446 22:16:39.441060 [0] MIN Duty = 4844%(X100), DQS PI = 58
2447 22:16:39.444239 [0] AVG Duty = 4937%(X100)
2448 22:16:39.444343
2449 22:16:39.447538 CH1 CLK Duty spec in!! Max-Min= 187%
2450 22:16:39.451132 [DutyScan_Calibration_Flow] ====Done====
2451 22:16:39.451237
2452 22:16:39.454314 [DutyScan_Calibration_Flow] k_type=1
2453 22:16:39.469500
2454 22:16:39.469577 ==DQS 0 ==
2455 22:16:39.472782 Final DQS duty delay cell = -4
2456 22:16:39.476378 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2457 22:16:39.479775 [-4] MIN Duty = 4907%(X100), DQS PI = 2
2458 22:16:39.482627 [-4] AVG Duty = 4969%(X100)
2459 22:16:39.482740
2460 22:16:39.482833 ==DQS 1 ==
2461 22:16:39.485870 Final DQS duty delay cell = 0
2462 22:16:39.489306 [0] MAX Duty = 5093%(X100), DQS PI = 2
2463 22:16:39.492693 [0] MIN Duty = 4875%(X100), DQS PI = 26
2464 22:16:39.496288 [0] AVG Duty = 4984%(X100)
2465 22:16:39.496401
2466 22:16:39.499131 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2467 22:16:39.499233
2468 22:16:39.502607 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2469 22:16:39.505580 [DutyScan_Calibration_Flow] ====Done====
2470 22:16:39.505651
2471 22:16:39.508914 [DutyScan_Calibration_Flow] k_type=3
2472 22:16:39.526235
2473 22:16:39.526343 ==DQM 0 ==
2474 22:16:39.529590 Final DQM duty delay cell = 0
2475 22:16:39.532849 [0] MAX Duty = 5000%(X100), DQS PI = 22
2476 22:16:39.536350 [0] MIN Duty = 4844%(X100), DQS PI = 52
2477 22:16:39.539323 [0] AVG Duty = 4922%(X100)
2478 22:16:39.539425
2479 22:16:39.539515 ==DQM 1 ==
2480 22:16:39.542965 Final DQM duty delay cell = 0
2481 22:16:39.546393 [0] MAX Duty = 5031%(X100), DQS PI = 36
2482 22:16:39.549404 [0] MIN Duty = 4907%(X100), DQS PI = 0
2483 22:16:39.552794 [0] AVG Duty = 4969%(X100)
2484 22:16:39.552865
2485 22:16:39.556433 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2486 22:16:39.556507
2487 22:16:39.559388 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2488 22:16:39.562388 [DutyScan_Calibration_Flow] ====Done====
2489 22:16:39.562460
2490 22:16:39.565646 [DutyScan_Calibration_Flow] k_type=2
2491 22:16:39.582572
2492 22:16:39.582684 ==DQ 0 ==
2493 22:16:39.586157 Final DQ duty delay cell = 0
2494 22:16:39.588927 [0] MAX Duty = 5093%(X100), DQS PI = 32
2495 22:16:39.592490 [0] MIN Duty = 4938%(X100), DQS PI = 56
2496 22:16:39.595825 [0] AVG Duty = 5015%(X100)
2497 22:16:39.595925
2498 22:16:39.596016 ==DQ 1 ==
2499 22:16:39.599195 Final DQ duty delay cell = 0
2500 22:16:39.602350 [0] MAX Duty = 5125%(X100), DQS PI = 36
2501 22:16:39.605784 [0] MIN Duty = 4969%(X100), DQS PI = 26
2502 22:16:39.605887 [0] AVG Duty = 5047%(X100)
2503 22:16:39.605985
2504 22:16:39.612633 CH1 DQ 0 Duty spec in!! Max-Min= 155%
2505 22:16:39.612742
2506 22:16:39.615662 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2507 22:16:39.619177 [DutyScan_Calibration_Flow] ====Done====
2508 22:16:39.622150 nWR fixed to 30
2509 22:16:39.622252 [ModeRegInit_LP4] CH0 RK0
2510 22:16:39.625659 [ModeRegInit_LP4] CH0 RK1
2511 22:16:39.628985 [ModeRegInit_LP4] CH1 RK0
2512 22:16:39.632285 [ModeRegInit_LP4] CH1 RK1
2513 22:16:39.632363 match AC timing 7
2514 22:16:39.638863 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2515 22:16:39.641882 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2516 22:16:39.645176 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2517 22:16:39.652304 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2518 22:16:39.655545 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2519 22:16:39.655636 ==
2520 22:16:39.658936 Dram Type= 6, Freq= 0, CH_0, rank 0
2521 22:16:39.661845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2522 22:16:39.661948 ==
2523 22:16:39.668776 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2524 22:16:39.675238 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2525 22:16:39.682923 [CA 0] Center 40 (10~71) winsize 62
2526 22:16:39.685760 [CA 1] Center 39 (9~70) winsize 62
2527 22:16:39.689210 [CA 2] Center 36 (6~66) winsize 61
2528 22:16:39.692377 [CA 3] Center 35 (5~66) winsize 62
2529 22:16:39.696104 [CA 4] Center 34 (4~65) winsize 62
2530 22:16:39.699318 [CA 5] Center 33 (3~63) winsize 61
2531 22:16:39.699419
2532 22:16:39.702609 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2533 22:16:39.702709
2534 22:16:39.705964 [CATrainingPosCal] consider 1 rank data
2535 22:16:39.709600 u2DelayCellTimex100 = 270/100 ps
2536 22:16:39.713015 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2537 22:16:39.715901 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2538 22:16:39.722934 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2539 22:16:39.725942 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2540 22:16:39.729060 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2541 22:16:39.732443 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2542 22:16:39.732539
2543 22:16:39.735974 CA PerBit enable=1, Macro0, CA PI delay=33
2544 22:16:39.736057
2545 22:16:39.739501 [CBTSetCACLKResult] CA Dly = 33
2546 22:16:39.739648 CS Dly: 7 (0~38)
2547 22:16:39.742602 ==
2548 22:16:39.746321 Dram Type= 6, Freq= 0, CH_0, rank 1
2549 22:16:39.749192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2550 22:16:39.749297 ==
2551 22:16:39.752721 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2552 22:16:39.758972 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2553 22:16:39.768533 [CA 0] Center 40 (10~70) winsize 61
2554 22:16:39.771596 [CA 1] Center 40 (10~70) winsize 61
2555 22:16:39.775521 [CA 2] Center 35 (5~66) winsize 62
2556 22:16:39.778971 [CA 3] Center 35 (5~66) winsize 62
2557 22:16:39.782657 [CA 4] Center 34 (4~65) winsize 62
2558 22:16:39.785371 [CA 5] Center 33 (3~64) winsize 62
2559 22:16:39.785475
2560 22:16:39.788408 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2561 22:16:39.788507
2562 22:16:39.791547 [CATrainingPosCal] consider 2 rank data
2563 22:16:39.794964 u2DelayCellTimex100 = 270/100 ps
2564 22:16:39.798269 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2565 22:16:39.805084 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2566 22:16:39.808705 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2567 22:16:39.811566 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2568 22:16:39.815170 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2569 22:16:39.818192 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2570 22:16:39.818267
2571 22:16:39.821763 CA PerBit enable=1, Macro0, CA PI delay=33
2572 22:16:39.821869
2573 22:16:39.825221 [CBTSetCACLKResult] CA Dly = 33
2574 22:16:39.828702 CS Dly: 8 (0~40)
2575 22:16:39.828785
2576 22:16:39.831479 ----->DramcWriteLeveling(PI) begin...
2577 22:16:39.831593 ==
2578 22:16:39.834995 Dram Type= 6, Freq= 0, CH_0, rank 0
2579 22:16:39.838602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2580 22:16:39.838717 ==
2581 22:16:39.841757 Write leveling (Byte 0): 32 => 32
2582 22:16:39.845279 Write leveling (Byte 1): 30 => 30
2583 22:16:39.848709 DramcWriteLeveling(PI) end<-----
2584 22:16:39.848808
2585 22:16:39.848914 ==
2586 22:16:39.852095 Dram Type= 6, Freq= 0, CH_0, rank 0
2587 22:16:39.854937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2588 22:16:39.855052 ==
2589 22:16:39.858485 [Gating] SW mode calibration
2590 22:16:39.865297 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2591 22:16:39.871720 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2592 22:16:39.874667 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2593 22:16:39.878414 0 15 4 | B1->B0 | 2828 3333 | 0 1 | (1 1) (1 1)
2594 22:16:39.885515 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2595 22:16:39.888272 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2596 22:16:39.891438 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2597 22:16:39.898401 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2598 22:16:39.901626 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2599 22:16:39.905004 0 15 28 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
2600 22:16:39.911740 1 0 0 | B1->B0 | 3030 2727 | 0 0 | (0 0) (0 0)
2601 22:16:39.914832 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2602 22:16:39.918091 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2603 22:16:39.925052 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2604 22:16:39.927972 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2605 22:16:39.931320 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2606 22:16:39.938465 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2607 22:16:39.941392 1 0 28 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2608 22:16:39.944585 1 1 0 | B1->B0 | 2b2b 3535 | 1 1 | (0 0) (0 0)
2609 22:16:39.951666 1 1 4 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
2610 22:16:39.954972 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2611 22:16:39.957646 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2612 22:16:39.964329 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2613 22:16:39.967667 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2614 22:16:39.971134 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2615 22:16:39.974689 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2616 22:16:39.980966 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2617 22:16:39.984534 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2618 22:16:39.987872 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 22:16:39.994531 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2620 22:16:39.997680 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2621 22:16:40.000847 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2622 22:16:40.007434 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2623 22:16:40.010450 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2624 22:16:40.014344 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2625 22:16:40.020881 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2626 22:16:40.023844 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2627 22:16:40.027197 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2628 22:16:40.034038 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2629 22:16:40.037639 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2630 22:16:40.040301 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2631 22:16:40.047404 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2632 22:16:40.050633 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2633 22:16:40.053879 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2634 22:16:40.057570 Total UI for P1: 0, mck2ui 16
2635 22:16:40.060239 best dqsien dly found for B0: ( 1, 3, 30)
2636 22:16:40.063506 Total UI for P1: 0, mck2ui 16
2637 22:16:40.067015 best dqsien dly found for B1: ( 1, 4, 2)
2638 22:16:40.070467 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2639 22:16:40.073942 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2640 22:16:40.074024
2641 22:16:40.080384 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2642 22:16:40.083911 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2643 22:16:40.083993 [Gating] SW calibration Done
2644 22:16:40.086710 ==
2645 22:16:40.090164 Dram Type= 6, Freq= 0, CH_0, rank 0
2646 22:16:40.093572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2647 22:16:40.093655 ==
2648 22:16:40.093722 RX Vref Scan: 0
2649 22:16:40.093783
2650 22:16:40.096847 RX Vref 0 -> 0, step: 1
2651 22:16:40.096928
2652 22:16:40.100212 RX Delay -40 -> 252, step: 8
2653 22:16:40.103363 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2654 22:16:40.106735 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2655 22:16:40.113202 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2656 22:16:40.116609 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2657 22:16:40.120204 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2658 22:16:40.123874 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2659 22:16:40.126445 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2660 22:16:40.130398 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2661 22:16:40.136543 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2662 22:16:40.140183 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2663 22:16:40.143154 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2664 22:16:40.146543 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2665 22:16:40.149980 iDelay=200, Bit 12, Center 107 (32 ~ 183) 152
2666 22:16:40.157004 iDelay=200, Bit 13, Center 107 (32 ~ 183) 152
2667 22:16:40.159764 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2668 22:16:40.163239 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2669 22:16:40.163392 ==
2670 22:16:40.166498 Dram Type= 6, Freq= 0, CH_0, rank 0
2671 22:16:40.169772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2672 22:16:40.173329 ==
2673 22:16:40.173411 DQS Delay:
2674 22:16:40.173477 DQS0 = 0, DQS1 = 0
2675 22:16:40.176615 DQM Delay:
2676 22:16:40.176697 DQM0 = 113, DQM1 = 102
2677 22:16:40.180189 DQ Delay:
2678 22:16:40.183203 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2679 22:16:40.186557 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2680 22:16:40.190086 DQ8 =95, DQ9 =83, DQ10 =103, DQ11 =95
2681 22:16:40.193332 DQ12 =107, DQ13 =107, DQ14 =115, DQ15 =111
2682 22:16:40.193415
2683 22:16:40.193480
2684 22:16:40.193541 ==
2685 22:16:40.196844 Dram Type= 6, Freq= 0, CH_0, rank 0
2686 22:16:40.200207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2687 22:16:40.200291 ==
2688 22:16:40.200356
2689 22:16:40.200416
2690 22:16:40.203536 TX Vref Scan disable
2691 22:16:40.206734 == TX Byte 0 ==
2692 22:16:40.209654 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2693 22:16:40.213062 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2694 22:16:40.216469 == TX Byte 1 ==
2695 22:16:40.219869 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2696 22:16:40.223491 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2697 22:16:40.223605 ==
2698 22:16:40.226868 Dram Type= 6, Freq= 0, CH_0, rank 0
2699 22:16:40.229773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2700 22:16:40.229856 ==
2701 22:16:40.243251 TX Vref=22, minBit 5, minWin=25, winSum=417
2702 22:16:40.246711 TX Vref=24, minBit 1, minWin=26, winSum=422
2703 22:16:40.249524 TX Vref=26, minBit 8, minWin=26, winSum=430
2704 22:16:40.252958 TX Vref=28, minBit 13, minWin=26, winSum=434
2705 22:16:40.256443 TX Vref=30, minBit 8, minWin=26, winSum=433
2706 22:16:40.262683 TX Vref=32, minBit 10, minWin=25, winSum=430
2707 22:16:40.266248 [TxChooseVref] Worse bit 13, Min win 26, Win sum 434, Final Vref 28
2708 22:16:40.266334
2709 22:16:40.269472 Final TX Range 1 Vref 28
2710 22:16:40.269554
2711 22:16:40.269618 ==
2712 22:16:40.272731 Dram Type= 6, Freq= 0, CH_0, rank 0
2713 22:16:40.276165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2714 22:16:40.279076 ==
2715 22:16:40.279158
2716 22:16:40.279222
2717 22:16:40.279282 TX Vref Scan disable
2718 22:16:40.282818 == TX Byte 0 ==
2719 22:16:40.286379 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2720 22:16:40.292755 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2721 22:16:40.292838 == TX Byte 1 ==
2722 22:16:40.296050 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2723 22:16:40.302968 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2724 22:16:40.303051
2725 22:16:40.303117 [DATLAT]
2726 22:16:40.303177 Freq=1200, CH0 RK0
2727 22:16:40.303236
2728 22:16:40.306246 DATLAT Default: 0xd
2729 22:16:40.309422 0, 0xFFFF, sum = 0
2730 22:16:40.309506 1, 0xFFFF, sum = 0
2731 22:16:40.312832 2, 0xFFFF, sum = 0
2732 22:16:40.312915 3, 0xFFFF, sum = 0
2733 22:16:40.315829 4, 0xFFFF, sum = 0
2734 22:16:40.315912 5, 0xFFFF, sum = 0
2735 22:16:40.319248 6, 0xFFFF, sum = 0
2736 22:16:40.319331 7, 0xFFFF, sum = 0
2737 22:16:40.322410 8, 0xFFFF, sum = 0
2738 22:16:40.322494 9, 0xFFFF, sum = 0
2739 22:16:40.325739 10, 0xFFFF, sum = 0
2740 22:16:40.325823 11, 0xFFFF, sum = 0
2741 22:16:40.329209 12, 0x0, sum = 1
2742 22:16:40.329293 13, 0x0, sum = 2
2743 22:16:40.332554 14, 0x0, sum = 3
2744 22:16:40.332638 15, 0x0, sum = 4
2745 22:16:40.335865 best_step = 13
2746 22:16:40.335947
2747 22:16:40.336011 ==
2748 22:16:40.339166 Dram Type= 6, Freq= 0, CH_0, rank 0
2749 22:16:40.342412 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2750 22:16:40.342496 ==
2751 22:16:40.345665 RX Vref Scan: 1
2752 22:16:40.345748
2753 22:16:40.345813 Set Vref Range= 32 -> 127
2754 22:16:40.345873
2755 22:16:40.349292 RX Vref 32 -> 127, step: 1
2756 22:16:40.349374
2757 22:16:40.352744 RX Delay -37 -> 252, step: 4
2758 22:16:40.352828
2759 22:16:40.355672 Set Vref, RX VrefLevel [Byte0]: 32
2760 22:16:40.359149 [Byte1]: 32
2761 22:16:40.359231
2762 22:16:40.362390 Set Vref, RX VrefLevel [Byte0]: 33
2763 22:16:40.365438 [Byte1]: 33
2764 22:16:40.369907
2765 22:16:40.369989 Set Vref, RX VrefLevel [Byte0]: 34
2766 22:16:40.372873 [Byte1]: 34
2767 22:16:40.377572
2768 22:16:40.377654 Set Vref, RX VrefLevel [Byte0]: 35
2769 22:16:40.381247 [Byte1]: 35
2770 22:16:40.385908
2771 22:16:40.385990 Set Vref, RX VrefLevel [Byte0]: 36
2772 22:16:40.388848 [Byte1]: 36
2773 22:16:40.393487
2774 22:16:40.393569 Set Vref, RX VrefLevel [Byte0]: 37
2775 22:16:40.397147 [Byte1]: 37
2776 22:16:40.401909
2777 22:16:40.401991 Set Vref, RX VrefLevel [Byte0]: 38
2778 22:16:40.405108 [Byte1]: 38
2779 22:16:40.409555
2780 22:16:40.409637 Set Vref, RX VrefLevel [Byte0]: 39
2781 22:16:40.413006 [Byte1]: 39
2782 22:16:40.418142
2783 22:16:40.418224 Set Vref, RX VrefLevel [Byte0]: 40
2784 22:16:40.420772 [Byte1]: 40
2785 22:16:40.425694
2786 22:16:40.425777 Set Vref, RX VrefLevel [Byte0]: 41
2787 22:16:40.429040 [Byte1]: 41
2788 22:16:40.433488
2789 22:16:40.433570 Set Vref, RX VrefLevel [Byte0]: 42
2790 22:16:40.436940 [Byte1]: 42
2791 22:16:40.441451
2792 22:16:40.441535 Set Vref, RX VrefLevel [Byte0]: 43
2793 22:16:40.448238 [Byte1]: 43
2794 22:16:40.448323
2795 22:16:40.451748 Set Vref, RX VrefLevel [Byte0]: 44
2796 22:16:40.454634 [Byte1]: 44
2797 22:16:40.454736
2798 22:16:40.458094 Set Vref, RX VrefLevel [Byte0]: 45
2799 22:16:40.461404 [Byte1]: 45
2800 22:16:40.465566
2801 22:16:40.465650 Set Vref, RX VrefLevel [Byte0]: 46
2802 22:16:40.468994 [Byte1]: 46
2803 22:16:40.473741
2804 22:16:40.473824 Set Vref, RX VrefLevel [Byte0]: 47
2805 22:16:40.477012 [Byte1]: 47
2806 22:16:40.481930
2807 22:16:40.482014 Set Vref, RX VrefLevel [Byte0]: 48
2808 22:16:40.485209 [Byte1]: 48
2809 22:16:40.489706
2810 22:16:40.489790 Set Vref, RX VrefLevel [Byte0]: 49
2811 22:16:40.493038 [Byte1]: 49
2812 22:16:40.497925
2813 22:16:40.498008 Set Vref, RX VrefLevel [Byte0]: 50
2814 22:16:40.501150 [Byte1]: 50
2815 22:16:40.505678
2816 22:16:40.505761 Set Vref, RX VrefLevel [Byte0]: 51
2817 22:16:40.508993 [Byte1]: 51
2818 22:16:40.513774
2819 22:16:40.513857 Set Vref, RX VrefLevel [Byte0]: 52
2820 22:16:40.517329 [Byte1]: 52
2821 22:16:40.522076
2822 22:16:40.522160 Set Vref, RX VrefLevel [Byte0]: 53
2823 22:16:40.524810 [Byte1]: 53
2824 22:16:40.529827
2825 22:16:40.529911 Set Vref, RX VrefLevel [Byte0]: 54
2826 22:16:40.533055 [Byte1]: 54
2827 22:16:40.537464
2828 22:16:40.537548 Set Vref, RX VrefLevel [Byte0]: 55
2829 22:16:40.541051 [Byte1]: 55
2830 22:16:40.545475
2831 22:16:40.545559 Set Vref, RX VrefLevel [Byte0]: 56
2832 22:16:40.548905 [Byte1]: 56
2833 22:16:40.553633
2834 22:16:40.553717 Set Vref, RX VrefLevel [Byte0]: 57
2835 22:16:40.557274 [Byte1]: 57
2836 22:16:40.561771
2837 22:16:40.561855 Set Vref, RX VrefLevel [Byte0]: 58
2838 22:16:40.565285 [Byte1]: 58
2839 22:16:40.569518
2840 22:16:40.569602 Set Vref, RX VrefLevel [Byte0]: 59
2841 22:16:40.572947 [Byte1]: 59
2842 22:16:40.577462
2843 22:16:40.577546 Set Vref, RX VrefLevel [Byte0]: 60
2844 22:16:40.581029 [Byte1]: 60
2845 22:16:40.585553
2846 22:16:40.585636 Set Vref, RX VrefLevel [Byte0]: 61
2847 22:16:40.589141 [Byte1]: 61
2848 22:16:40.593532
2849 22:16:40.593615 Set Vref, RX VrefLevel [Byte0]: 62
2850 22:16:40.597208 [Byte1]: 62
2851 22:16:40.601833
2852 22:16:40.601916 Set Vref, RX VrefLevel [Byte0]: 63
2853 22:16:40.605494 [Byte1]: 63
2854 22:16:40.609781
2855 22:16:40.613053 Set Vref, RX VrefLevel [Byte0]: 64
2856 22:16:40.616074 [Byte1]: 64
2857 22:16:40.616157
2858 22:16:40.619449 Set Vref, RX VrefLevel [Byte0]: 65
2859 22:16:40.623065 [Byte1]: 65
2860 22:16:40.623150
2861 22:16:40.626583 Set Vref, RX VrefLevel [Byte0]: 66
2862 22:16:40.629342 [Byte1]: 66
2863 22:16:40.633717
2864 22:16:40.633801 Set Vref, RX VrefLevel [Byte0]: 67
2865 22:16:40.637167 [Byte1]: 67
2866 22:16:40.641714
2867 22:16:40.641797 Set Vref, RX VrefLevel [Byte0]: 68
2868 22:16:40.645310 [Byte1]: 68
2869 22:16:40.649601
2870 22:16:40.649686 Set Vref, RX VrefLevel [Byte0]: 69
2871 22:16:40.652919 [Byte1]: 69
2872 22:16:40.657648
2873 22:16:40.657731 Set Vref, RX VrefLevel [Byte0]: 70
2874 22:16:40.660953 [Byte1]: 70
2875 22:16:40.665784
2876 22:16:40.665868 Set Vref, RX VrefLevel [Byte0]: 71
2877 22:16:40.668783 [Byte1]: 71
2878 22:16:40.673497
2879 22:16:40.673581 Set Vref, RX VrefLevel [Byte0]: 72
2880 22:16:40.677170 [Byte1]: 72
2881 22:16:40.681879
2882 22:16:40.681964 Set Vref, RX VrefLevel [Byte0]: 73
2883 22:16:40.684945 [Byte1]: 73
2884 22:16:40.690201
2885 22:16:40.690284 Set Vref, RX VrefLevel [Byte0]: 74
2886 22:16:40.693110 [Byte1]: 74
2887 22:16:40.697691
2888 22:16:40.697801 Final RX Vref Byte 0 = 61 to rank0
2889 22:16:40.700997 Final RX Vref Byte 1 = 56 to rank0
2890 22:16:40.704170 Final RX Vref Byte 0 = 61 to rank1
2891 22:16:40.707489 Final RX Vref Byte 1 = 56 to rank1==
2892 22:16:40.711486 Dram Type= 6, Freq= 0, CH_0, rank 0
2893 22:16:40.717959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2894 22:16:40.718591 ==
2895 22:16:40.719193 DQS Delay:
2896 22:16:40.721514 DQS0 = 0, DQS1 = 0
2897 22:16:40.722047 DQM Delay:
2898 22:16:40.722624 DQM0 = 112, DQM1 = 102
2899 22:16:40.724755 DQ Delay:
2900 22:16:40.727546 DQ0 =112, DQ1 =112, DQ2 =110, DQ3 =108
2901 22:16:40.730901 DQ4 =112, DQ5 =104, DQ6 =120, DQ7 =120
2902 22:16:40.734589 DQ8 =94, DQ9 =86, DQ10 =102, DQ11 =94
2903 22:16:40.738018 DQ12 =108, DQ13 =106, DQ14 =116, DQ15 =110
2904 22:16:40.738572
2905 22:16:40.739109
2906 22:16:40.747714 [DQSOSCAuto] RK0, (LSB)MR18= 0xfdfc, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 411 ps
2907 22:16:40.748309 CH0 RK0: MR19=303, MR18=FDFC
2908 22:16:40.754287 CH0_RK0: MR19=0x303, MR18=0xFDFC, DQSOSC=411, MR23=63, INC=38, DEC=25
2909 22:16:40.754881
2910 22:16:40.757475 ----->DramcWriteLeveling(PI) begin...
2911 22:16:40.757987 ==
2912 22:16:40.761252 Dram Type= 6, Freq= 0, CH_0, rank 1
2913 22:16:40.767621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2914 22:16:40.768119 ==
2915 22:16:40.771020 Write leveling (Byte 0): 30 => 30
2916 22:16:40.771440 Write leveling (Byte 1): 30 => 30
2917 22:16:40.774287 DramcWriteLeveling(PI) end<-----
2918 22:16:40.774707
2919 22:16:40.775041 ==
2920 22:16:40.777794 Dram Type= 6, Freq= 0, CH_0, rank 1
2921 22:16:40.784270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2922 22:16:40.784699 ==
2923 22:16:40.787734 [Gating] SW mode calibration
2924 22:16:40.794402 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2925 22:16:40.797497 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2926 22:16:40.804277 0 15 0 | B1->B0 | 2828 3434 | 1 1 | (0 0) (1 1)
2927 22:16:40.807689 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2928 22:16:40.810861 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2929 22:16:40.814147 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2930 22:16:40.821118 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2931 22:16:40.824485 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2932 22:16:40.828096 0 15 24 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 0)
2933 22:16:40.834416 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
2934 22:16:40.837427 1 0 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
2935 22:16:40.840870 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2936 22:16:40.847657 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2937 22:16:40.850457 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2938 22:16:40.854003 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2939 22:16:40.860499 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2940 22:16:40.864188 1 0 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (1 1)
2941 22:16:40.867037 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2942 22:16:40.873837 1 1 0 | B1->B0 | 4141 4646 | 0 0 | (1 1) (0 0)
2943 22:16:40.877192 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2944 22:16:40.880484 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2945 22:16:40.886647 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2946 22:16:40.890308 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2947 22:16:40.893518 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2948 22:16:40.900049 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2949 22:16:40.903934 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2950 22:16:40.906759 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2951 22:16:40.913491 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2952 22:16:40.917205 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2953 22:16:40.920147 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2954 22:16:40.926776 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2955 22:16:40.930007 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2956 22:16:40.933476 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2957 22:16:40.939906 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2958 22:16:40.943359 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2959 22:16:40.946305 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2960 22:16:40.953200 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2961 22:16:40.956205 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2962 22:16:40.959614 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2963 22:16:40.966359 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2964 22:16:40.969685 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2965 22:16:40.972999 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2966 22:16:40.979458 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2967 22:16:40.979785 Total UI for P1: 0, mck2ui 16
2968 22:16:40.986197 best dqsien dly found for B0: ( 1, 3, 28)
2969 22:16:40.986502 Total UI for P1: 0, mck2ui 16
2970 22:16:40.993090 best dqsien dly found for B1: ( 1, 3, 30)
2971 22:16:40.996052 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2972 22:16:40.999527 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2973 22:16:40.999859
2974 22:16:41.002918 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2975 22:16:41.006405 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2976 22:16:41.009819 [Gating] SW calibration Done
2977 22:16:41.010122 ==
2978 22:16:41.012855 Dram Type= 6, Freq= 0, CH_0, rank 1
2979 22:16:41.015970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2980 22:16:41.016276 ==
2981 22:16:41.019998 RX Vref Scan: 0
2982 22:16:41.020301
2983 22:16:41.020541 RX Vref 0 -> 0, step: 1
2984 22:16:41.020766
2985 22:16:41.022821 RX Delay -40 -> 252, step: 8
2986 22:16:41.025999 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2987 22:16:41.032592 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2988 22:16:41.035796 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2989 22:16:41.039553 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2990 22:16:41.042514 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2991 22:16:41.046048 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2992 22:16:41.052449 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2993 22:16:41.055942 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2994 22:16:41.059236 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2995 22:16:41.062625 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2996 22:16:41.065919 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2997 22:16:41.069640 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2998 22:16:41.076094 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2999 22:16:41.079454 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3000 22:16:41.082657 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3001 22:16:41.085981 iDelay=200, Bit 15, Center 107 (32 ~ 183) 152
3002 22:16:41.089290 ==
3003 22:16:41.089597 Dram Type= 6, Freq= 0, CH_0, rank 1
3004 22:16:41.095979 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3005 22:16:41.096290 ==
3006 22:16:41.096607 DQS Delay:
3007 22:16:41.098896 DQS0 = 0, DQS1 = 0
3008 22:16:41.099204 DQM Delay:
3009 22:16:41.102167 DQM0 = 112, DQM1 = 102
3010 22:16:41.102474 DQ Delay:
3011 22:16:41.105872 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
3012 22:16:41.108788 DQ4 =115, DQ5 =103, DQ6 =119, DQ7 =123
3013 22:16:41.112266 DQ8 =91, DQ9 =83, DQ10 =107, DQ11 =95
3014 22:16:41.115645 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =107
3015 22:16:41.116044
3016 22:16:41.116439
3017 22:16:41.116812 ==
3018 22:16:41.119042 Dram Type= 6, Freq= 0, CH_0, rank 1
3019 22:16:41.125665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3020 22:16:41.126064 ==
3021 22:16:41.126463
3022 22:16:41.126837
3023 22:16:41.127205 TX Vref Scan disable
3024 22:16:41.128826 == TX Byte 0 ==
3025 22:16:41.132275 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
3026 22:16:41.135551 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
3027 22:16:41.138860 == TX Byte 1 ==
3028 22:16:41.142194 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3029 22:16:41.148689 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3030 22:16:41.149088 ==
3031 22:16:41.152105 Dram Type= 6, Freq= 0, CH_0, rank 1
3032 22:16:41.155414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3033 22:16:41.155681 ==
3034 22:16:41.166718 TX Vref=22, minBit 0, minWin=26, winSum=423
3035 22:16:41.169746 TX Vref=24, minBit 1, minWin=26, winSum=432
3036 22:16:41.173071 TX Vref=26, minBit 2, minWin=26, winSum=435
3037 22:16:41.176479 TX Vref=28, minBit 2, minWin=27, winSum=442
3038 22:16:41.179625 TX Vref=30, minBit 2, minWin=27, winSum=443
3039 22:16:41.186402 TX Vref=32, minBit 8, minWin=26, winSum=443
3040 22:16:41.189434 [TxChooseVref] Worse bit 2, Min win 27, Win sum 443, Final Vref 30
3041 22:16:41.189658
3042 22:16:41.193260 Final TX Range 1 Vref 30
3043 22:16:41.193477
3044 22:16:41.193649 ==
3045 22:16:41.196390 Dram Type= 6, Freq= 0, CH_0, rank 1
3046 22:16:41.199610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3047 22:16:41.199828 ==
3048 22:16:41.202810
3049 22:16:41.203024
3050 22:16:41.203194 TX Vref Scan disable
3051 22:16:41.206505 == TX Byte 0 ==
3052 22:16:41.209452 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
3053 22:16:41.216427 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
3054 22:16:41.216643 == TX Byte 1 ==
3055 22:16:41.219246 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3056 22:16:41.225931 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3057 22:16:41.226148
3058 22:16:41.226320 [DATLAT]
3059 22:16:41.226575 Freq=1200, CH0 RK1
3060 22:16:41.226764
3061 22:16:41.229141 DATLAT Default: 0xd
3062 22:16:41.229385 0, 0xFFFF, sum = 0
3063 22:16:41.232776 1, 0xFFFF, sum = 0
3064 22:16:41.236354 2, 0xFFFF, sum = 0
3065 22:16:41.236573 3, 0xFFFF, sum = 0
3066 22:16:41.239035 4, 0xFFFF, sum = 0
3067 22:16:41.239252 5, 0xFFFF, sum = 0
3068 22:16:41.242432 6, 0xFFFF, sum = 0
3069 22:16:41.242651 7, 0xFFFF, sum = 0
3070 22:16:41.245946 8, 0xFFFF, sum = 0
3071 22:16:41.246165 9, 0xFFFF, sum = 0
3072 22:16:41.249262 10, 0xFFFF, sum = 0
3073 22:16:41.249482 11, 0xFFFF, sum = 0
3074 22:16:41.252390 12, 0x0, sum = 1
3075 22:16:41.252609 13, 0x0, sum = 2
3076 22:16:41.255838 14, 0x0, sum = 3
3077 22:16:41.256057 15, 0x0, sum = 4
3078 22:16:41.259354 best_step = 13
3079 22:16:41.259570
3080 22:16:41.259757 ==
3081 22:16:41.262355 Dram Type= 6, Freq= 0, CH_0, rank 1
3082 22:16:41.265874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3083 22:16:41.266091 ==
3084 22:16:41.266265 RX Vref Scan: 0
3085 22:16:41.269388
3086 22:16:41.269602 RX Vref 0 -> 0, step: 1
3087 22:16:41.269774
3088 22:16:41.272810 RX Delay -37 -> 252, step: 4
3089 22:16:41.278838 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3090 22:16:41.281973 iDelay=195, Bit 1, Center 110 (39 ~ 182) 144
3091 22:16:41.285567 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3092 22:16:41.288901 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3093 22:16:41.291889 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3094 22:16:41.298898 iDelay=195, Bit 5, Center 102 (35 ~ 170) 136
3095 22:16:41.302427 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3096 22:16:41.305432 iDelay=195, Bit 7, Center 118 (43 ~ 194) 152
3097 22:16:41.308714 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3098 22:16:41.312336 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3099 22:16:41.318799 iDelay=195, Bit 10, Center 104 (35 ~ 174) 140
3100 22:16:41.322426 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3101 22:16:41.325234 iDelay=195, Bit 12, Center 108 (39 ~ 178) 140
3102 22:16:41.328605 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3103 22:16:41.331840 iDelay=195, Bit 14, Center 114 (47 ~ 182) 136
3104 22:16:41.338420 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3105 22:16:41.338635 ==
3106 22:16:41.342162 Dram Type= 6, Freq= 0, CH_0, rank 1
3107 22:16:41.345443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3108 22:16:41.345661 ==
3109 22:16:41.345833 DQS Delay:
3110 22:16:41.348527 DQS0 = 0, DQS1 = 0
3111 22:16:41.348743 DQM Delay:
3112 22:16:41.352151 DQM0 = 110, DQM1 = 101
3113 22:16:41.352366 DQ Delay:
3114 22:16:41.355447 DQ0 =108, DQ1 =110, DQ2 =108, DQ3 =108
3115 22:16:41.358686 DQ4 =112, DQ5 =102, DQ6 =120, DQ7 =118
3116 22:16:41.361618 DQ8 =90, DQ9 =84, DQ10 =104, DQ11 =94
3117 22:16:41.365121 DQ12 =108, DQ13 =108, DQ14 =114, DQ15 =110
3118 22:16:41.365337
3119 22:16:41.365507
3120 22:16:41.375571 [DQSOSCAuto] RK1, (LSB)MR18= 0x14fc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 402 ps
3121 22:16:41.378303 CH0 RK1: MR19=403, MR18=14FC
3122 22:16:41.382551 CH0_RK1: MR19=0x403, MR18=0x14FC, DQSOSC=402, MR23=63, INC=40, DEC=27
3123 22:16:41.385314 [RxdqsGatingPostProcess] freq 1200
3124 22:16:41.391873 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3125 22:16:41.395185 best DQS0 dly(2T, 0.5T) = (0, 11)
3126 22:16:41.398521 best DQS1 dly(2T, 0.5T) = (0, 12)
3127 22:16:41.401892 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3128 22:16:41.405054 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3129 22:16:41.408535 best DQS0 dly(2T, 0.5T) = (0, 11)
3130 22:16:41.411985 best DQS1 dly(2T, 0.5T) = (0, 11)
3131 22:16:41.414730 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3132 22:16:41.418381 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3133 22:16:41.421909 Pre-setting of DQS Precalculation
3134 22:16:41.424943 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3135 22:16:41.425607 ==
3136 22:16:41.428148 Dram Type= 6, Freq= 0, CH_1, rank 0
3137 22:16:41.431461 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3138 22:16:41.434180 ==
3139 22:16:41.437470 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3140 22:16:41.444392 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3141 22:16:41.452630 [CA 0] Center 37 (7~67) winsize 61
3142 22:16:41.455482 [CA 1] Center 37 (7~68) winsize 62
3143 22:16:41.458974 [CA 2] Center 34 (4~64) winsize 61
3144 22:16:41.462312 [CA 3] Center 33 (3~64) winsize 62
3145 22:16:41.465694 [CA 4] Center 34 (4~64) winsize 61
3146 22:16:41.469021 [CA 5] Center 33 (3~63) winsize 61
3147 22:16:41.469104
3148 22:16:41.472174 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3149 22:16:41.472257
3150 22:16:41.475466 [CATrainingPosCal] consider 1 rank data
3151 22:16:41.478944 u2DelayCellTimex100 = 270/100 ps
3152 22:16:41.482595 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3153 22:16:41.485483 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3154 22:16:41.492354 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3155 22:16:41.495462 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3156 22:16:41.499165 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3157 22:16:41.502114 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3158 22:16:41.502198
3159 22:16:41.505458 CA PerBit enable=1, Macro0, CA PI delay=33
3160 22:16:41.505540
3161 22:16:41.508631 [CBTSetCACLKResult] CA Dly = 33
3162 22:16:41.508714 CS Dly: 6 (0~37)
3163 22:16:41.512043 ==
3164 22:16:41.515081 Dram Type= 6, Freq= 0, CH_1, rank 1
3165 22:16:41.518652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3166 22:16:41.518736 ==
3167 22:16:41.521922 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3168 22:16:41.528710 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3169 22:16:41.538264 [CA 0] Center 37 (8~67) winsize 60
3170 22:16:41.541014 [CA 1] Center 37 (7~68) winsize 62
3171 22:16:41.544951 [CA 2] Center 34 (4~65) winsize 62
3172 22:16:41.548400 [CA 3] Center 33 (3~64) winsize 62
3173 22:16:41.551463 [CA 4] Center 34 (4~65) winsize 62
3174 22:16:41.554286 [CA 5] Center 32 (2~63) winsize 62
3175 22:16:41.554368
3176 22:16:41.557988 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3177 22:16:41.558070
3178 22:16:41.561345 [CATrainingPosCal] consider 2 rank data
3179 22:16:41.564560 u2DelayCellTimex100 = 270/100 ps
3180 22:16:41.567687 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3181 22:16:41.574282 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3182 22:16:41.577856 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3183 22:16:41.581403 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3184 22:16:41.584709 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3185 22:16:41.587786 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3186 22:16:41.587869
3187 22:16:41.591220 CA PerBit enable=1, Macro0, CA PI delay=33
3188 22:16:41.591303
3189 22:16:41.594068 [CBTSetCACLKResult] CA Dly = 33
3190 22:16:41.594151 CS Dly: 7 (0~40)
3191 22:16:41.597594
3192 22:16:41.600717 ----->DramcWriteLeveling(PI) begin...
3193 22:16:41.600801 ==
3194 22:16:41.603958 Dram Type= 6, Freq= 0, CH_1, rank 0
3195 22:16:41.607956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3196 22:16:41.608040 ==
3197 22:16:41.610897 Write leveling (Byte 0): 26 => 26
3198 22:16:41.614100 Write leveling (Byte 1): 29 => 29
3199 22:16:41.617412 DramcWriteLeveling(PI) end<-----
3200 22:16:41.617495
3201 22:16:41.617560 ==
3202 22:16:41.620940 Dram Type= 6, Freq= 0, CH_1, rank 0
3203 22:16:41.624242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3204 22:16:41.624325 ==
3205 22:16:41.627256 [Gating] SW mode calibration
3206 22:16:41.634184 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3207 22:16:41.640762 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3208 22:16:41.644149 0 15 0 | B1->B0 | 3232 2e2e | 1 1 | (0 0) (1 1)
3209 22:16:41.647596 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3210 22:16:41.654226 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3211 22:16:41.657534 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3212 22:16:41.660501 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3213 22:16:41.667431 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3214 22:16:41.670993 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3215 22:16:41.673818 0 15 28 | B1->B0 | 2e2e 3030 | 0 0 | (0 1) (0 1)
3216 22:16:41.680429 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3217 22:16:41.683945 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3218 22:16:41.686957 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3219 22:16:41.693974 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3220 22:16:41.697303 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3221 22:16:41.700235 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3222 22:16:41.703910 1 0 24 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3223 22:16:41.710193 1 0 28 | B1->B0 | 3c3c 3938 | 0 1 | (0 0) (0 0)
3224 22:16:41.713980 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3225 22:16:41.717174 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3226 22:16:41.723363 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3227 22:16:41.727075 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3228 22:16:41.730266 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3229 22:16:41.737296 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3230 22:16:41.740071 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3231 22:16:41.743550 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3232 22:16:41.749878 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3233 22:16:41.753361 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3234 22:16:41.756723 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3235 22:16:41.763281 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3236 22:16:41.767216 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3237 22:16:41.770069 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3238 22:16:41.776813 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3239 22:16:41.780231 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3240 22:16:41.783151 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3241 22:16:41.789983 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3242 22:16:41.793486 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3243 22:16:41.797038 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3244 22:16:41.803348 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3245 22:16:41.806887 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3246 22:16:41.809761 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3247 22:16:41.816668 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3248 22:16:41.819770 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3249 22:16:41.822989 Total UI for P1: 0, mck2ui 16
3250 22:16:41.826106 best dqsien dly found for B1: ( 1, 3, 28)
3251 22:16:41.829953 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3252 22:16:41.832713 Total UI for P1: 0, mck2ui 16
3253 22:16:41.836402 best dqsien dly found for B0: ( 1, 3, 30)
3254 22:16:41.839809 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3255 22:16:41.843150 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3256 22:16:41.843232
3257 22:16:41.846081 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3258 22:16:41.853172 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3259 22:16:41.853255 [Gating] SW calibration Done
3260 22:16:41.856247 ==
3261 22:16:41.856329 Dram Type= 6, Freq= 0, CH_1, rank 0
3262 22:16:41.862553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3263 22:16:41.862637 ==
3264 22:16:41.862703 RX Vref Scan: 0
3265 22:16:41.862762
3266 22:16:41.866247 RX Vref 0 -> 0, step: 1
3267 22:16:41.866328
3268 22:16:41.869671 RX Delay -40 -> 252, step: 8
3269 22:16:41.873082 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3270 22:16:41.876217 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3271 22:16:41.879322 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3272 22:16:41.886297 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3273 22:16:41.889207 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3274 22:16:41.892981 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3275 22:16:41.895832 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3276 22:16:41.899496 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3277 22:16:41.905934 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3278 22:16:41.909190 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3279 22:16:41.912713 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3280 22:16:41.916038 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3281 22:16:41.918954 iDelay=200, Bit 12, Center 115 (40 ~ 191) 152
3282 22:16:41.926019 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3283 22:16:41.929370 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3284 22:16:41.932493 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3285 22:16:41.932574 ==
3286 22:16:41.936037 Dram Type= 6, Freq= 0, CH_1, rank 0
3287 22:16:41.939264 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3288 22:16:41.939347 ==
3289 22:16:41.942514 DQS Delay:
3290 22:16:41.942595 DQS0 = 0, DQS1 = 0
3291 22:16:41.945843 DQM Delay:
3292 22:16:41.945924 DQM0 = 113, DQM1 = 106
3293 22:16:41.948891 DQ Delay:
3294 22:16:41.952277 DQ0 =119, DQ1 =107, DQ2 =99, DQ3 =111
3295 22:16:41.955665 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3296 22:16:41.959139 DQ8 =95, DQ9 =99, DQ10 =103, DQ11 =103
3297 22:16:41.962731 DQ12 =115, DQ13 =115, DQ14 =111, DQ15 =111
3298 22:16:41.962812
3299 22:16:41.962877
3300 22:16:41.962936 ==
3301 22:16:41.965601 Dram Type= 6, Freq= 0, CH_1, rank 0
3302 22:16:41.968981 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3303 22:16:41.969063 ==
3304 22:16:41.969128
3305 22:16:41.969187
3306 22:16:41.972486 TX Vref Scan disable
3307 22:16:41.975361 == TX Byte 0 ==
3308 22:16:41.978714 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3309 22:16:41.982666 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3310 22:16:41.985765 == TX Byte 1 ==
3311 22:16:41.988723 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3312 22:16:41.992009 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3313 22:16:41.992091 ==
3314 22:16:41.995520 Dram Type= 6, Freq= 0, CH_1, rank 0
3315 22:16:41.998961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3316 22:16:42.001936 ==
3317 22:16:42.012419 TX Vref=22, minBit 1, minWin=25, winSum=412
3318 22:16:42.015372 TX Vref=24, minBit 11, minWin=24, winSum=416
3319 22:16:42.018839 TX Vref=26, minBit 9, minWin=25, winSum=426
3320 22:16:42.022396 TX Vref=28, minBit 9, minWin=25, winSum=423
3321 22:16:42.025861 TX Vref=30, minBit 8, minWin=25, winSum=428
3322 22:16:42.028787 TX Vref=32, minBit 9, minWin=25, winSum=424
3323 22:16:42.035877 [TxChooseVref] Worse bit 8, Min win 25, Win sum 428, Final Vref 30
3324 22:16:42.035961
3325 22:16:42.039389 Final TX Range 1 Vref 30
3326 22:16:42.039471
3327 22:16:42.039535 ==
3328 22:16:42.042180 Dram Type= 6, Freq= 0, CH_1, rank 0
3329 22:16:42.045404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3330 22:16:42.045486 ==
3331 22:16:42.045551
3332 22:16:42.048885
3333 22:16:42.048966 TX Vref Scan disable
3334 22:16:42.052494 == TX Byte 0 ==
3335 22:16:42.055514 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3336 22:16:42.058901 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3337 22:16:42.062185 == TX Byte 1 ==
3338 22:16:42.065055 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3339 22:16:42.071825 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3340 22:16:42.071907
3341 22:16:42.071971 [DATLAT]
3342 22:16:42.072033 Freq=1200, CH1 RK0
3343 22:16:42.072092
3344 22:16:42.075256 DATLAT Default: 0xd
3345 22:16:42.075337 0, 0xFFFF, sum = 0
3346 22:16:42.078202 1, 0xFFFF, sum = 0
3347 22:16:42.081651 2, 0xFFFF, sum = 0
3348 22:16:42.081733 3, 0xFFFF, sum = 0
3349 22:16:42.085268 4, 0xFFFF, sum = 0
3350 22:16:42.085352 5, 0xFFFF, sum = 0
3351 22:16:42.088552 6, 0xFFFF, sum = 0
3352 22:16:42.088635 7, 0xFFFF, sum = 0
3353 22:16:42.091887 8, 0xFFFF, sum = 0
3354 22:16:42.091970 9, 0xFFFF, sum = 0
3355 22:16:42.094790 10, 0xFFFF, sum = 0
3356 22:16:42.094872 11, 0xFFFF, sum = 0
3357 22:16:42.098526 12, 0x0, sum = 1
3358 22:16:42.098608 13, 0x0, sum = 2
3359 22:16:42.101679 14, 0x0, sum = 3
3360 22:16:42.101760 15, 0x0, sum = 4
3361 22:16:42.105218 best_step = 13
3362 22:16:42.105299
3363 22:16:42.105363 ==
3364 22:16:42.107992 Dram Type= 6, Freq= 0, CH_1, rank 0
3365 22:16:42.111410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3366 22:16:42.111491 ==
3367 22:16:42.111555 RX Vref Scan: 1
3368 22:16:42.114777
3369 22:16:42.114857 Set Vref Range= 32 -> 127
3370 22:16:42.114921
3371 22:16:42.118345 RX Vref 32 -> 127, step: 1
3372 22:16:42.118425
3373 22:16:42.121622 RX Delay -21 -> 252, step: 4
3374 22:16:42.121702
3375 22:16:42.124642 Set Vref, RX VrefLevel [Byte0]: 32
3376 22:16:42.127975 [Byte1]: 32
3377 22:16:42.128056
3378 22:16:42.131254 Set Vref, RX VrefLevel [Byte0]: 33
3379 22:16:42.134686 [Byte1]: 33
3380 22:16:42.138367
3381 22:16:42.138447 Set Vref, RX VrefLevel [Byte0]: 34
3382 22:16:42.141829 [Byte1]: 34
3383 22:16:42.146220
3384 22:16:42.146300 Set Vref, RX VrefLevel [Byte0]: 35
3385 22:16:42.149576 [Byte1]: 35
3386 22:16:42.154205
3387 22:16:42.154305 Set Vref, RX VrefLevel [Byte0]: 36
3388 22:16:42.157365 [Byte1]: 36
3389 22:16:42.162653
3390 22:16:42.162745 Set Vref, RX VrefLevel [Byte0]: 37
3391 22:16:42.165624 [Byte1]: 37
3392 22:16:42.170197
3393 22:16:42.170330 Set Vref, RX VrefLevel [Byte0]: 38
3394 22:16:42.173318 [Byte1]: 38
3395 22:16:42.177823
3396 22:16:42.177965 Set Vref, RX VrefLevel [Byte0]: 39
3397 22:16:42.181205 [Byte1]: 39
3398 22:16:42.185771
3399 22:16:42.185921 Set Vref, RX VrefLevel [Byte0]: 40
3400 22:16:42.189551 [Byte1]: 40
3401 22:16:42.194085
3402 22:16:42.194308 Set Vref, RX VrefLevel [Byte0]: 41
3403 22:16:42.197624 [Byte1]: 41
3404 22:16:42.201827
3405 22:16:42.202063 Set Vref, RX VrefLevel [Byte0]: 42
3406 22:16:42.205569 [Byte1]: 42
3407 22:16:42.210053
3408 22:16:42.210350 Set Vref, RX VrefLevel [Byte0]: 43
3409 22:16:42.213401 [Byte1]: 43
3410 22:16:42.218135
3411 22:16:42.218594 Set Vref, RX VrefLevel [Byte0]: 44
3412 22:16:42.221513 [Byte1]: 44
3413 22:16:42.226070
3414 22:16:42.226596 Set Vref, RX VrefLevel [Byte0]: 45
3415 22:16:42.229610 [Byte1]: 45
3416 22:16:42.233812
3417 22:16:42.234322 Set Vref, RX VrefLevel [Byte0]: 46
3418 22:16:42.237151 [Byte1]: 46
3419 22:16:42.241924
3420 22:16:42.242381 Set Vref, RX VrefLevel [Byte0]: 47
3421 22:16:42.244731 [Byte1]: 47
3422 22:16:42.249439
3423 22:16:42.249519 Set Vref, RX VrefLevel [Byte0]: 48
3424 22:16:42.252801 [Byte1]: 48
3425 22:16:42.257149
3426 22:16:42.257229 Set Vref, RX VrefLevel [Byte0]: 49
3427 22:16:42.260282 [Byte1]: 49
3428 22:16:42.265253
3429 22:16:42.265339 Set Vref, RX VrefLevel [Byte0]: 50
3430 22:16:42.268763 [Byte1]: 50
3431 22:16:42.272847
3432 22:16:42.272947 Set Vref, RX VrefLevel [Byte0]: 51
3433 22:16:42.276714 [Byte1]: 51
3434 22:16:42.281000
3435 22:16:42.281119 Set Vref, RX VrefLevel [Byte0]: 52
3436 22:16:42.284545 [Byte1]: 52
3437 22:16:42.289274
3438 22:16:42.289407 Set Vref, RX VrefLevel [Byte0]: 53
3439 22:16:42.292281 [Byte1]: 53
3440 22:16:42.296921
3441 22:16:42.297090 Set Vref, RX VrefLevel [Byte0]: 54
3442 22:16:42.300377 [Byte1]: 54
3443 22:16:42.304995
3444 22:16:42.305205 Set Vref, RX VrefLevel [Byte0]: 55
3445 22:16:42.308091 [Byte1]: 55
3446 22:16:42.312615
3447 22:16:42.312813 Set Vref, RX VrefLevel [Byte0]: 56
3448 22:16:42.315887 [Byte1]: 56
3449 22:16:42.320822
3450 22:16:42.321019 Set Vref, RX VrefLevel [Byte0]: 57
3451 22:16:42.324402 [Byte1]: 57
3452 22:16:42.329084
3453 22:16:42.329282 Set Vref, RX VrefLevel [Byte0]: 58
3454 22:16:42.331908 [Byte1]: 58
3455 22:16:42.336657
3456 22:16:42.336738 Set Vref, RX VrefLevel [Byte0]: 59
3457 22:16:42.340039 [Byte1]: 59
3458 22:16:42.344567
3459 22:16:42.344647 Set Vref, RX VrefLevel [Byte0]: 60
3460 22:16:42.347629 [Byte1]: 60
3461 22:16:42.352203
3462 22:16:42.352283 Set Vref, RX VrefLevel [Byte0]: 61
3463 22:16:42.355628 [Byte1]: 61
3464 22:16:42.360467
3465 22:16:42.360554 Set Vref, RX VrefLevel [Byte0]: 62
3466 22:16:42.363276 [Byte1]: 62
3467 22:16:42.367899
3468 22:16:42.367981 Set Vref, RX VrefLevel [Byte0]: 63
3469 22:16:42.371748 [Byte1]: 63
3470 22:16:42.376142
3471 22:16:42.376237 Set Vref, RX VrefLevel [Byte0]: 64
3472 22:16:42.379083 [Byte1]: 64
3473 22:16:42.384105
3474 22:16:42.384208 Set Vref, RX VrefLevel [Byte0]: 65
3475 22:16:42.387426 [Byte1]: 65
3476 22:16:42.392506
3477 22:16:42.392632 Set Vref, RX VrefLevel [Byte0]: 66
3478 22:16:42.395748 [Byte1]: 66
3479 22:16:42.399617
3480 22:16:42.399753 Set Vref, RX VrefLevel [Byte0]: 67
3481 22:16:42.403183 [Byte1]: 67
3482 22:16:42.407549
3483 22:16:42.407740 Set Vref, RX VrefLevel [Byte0]: 68
3484 22:16:42.411180 [Byte1]: 68
3485 22:16:42.415524
3486 22:16:42.415793 Final RX Vref Byte 0 = 55 to rank0
3487 22:16:42.419549 Final RX Vref Byte 1 = 50 to rank0
3488 22:16:42.422288 Final RX Vref Byte 0 = 55 to rank1
3489 22:16:42.425995 Final RX Vref Byte 1 = 50 to rank1==
3490 22:16:42.428818 Dram Type= 6, Freq= 0, CH_1, rank 0
3491 22:16:42.435562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3492 22:16:42.436062 ==
3493 22:16:42.436478 DQS Delay:
3494 22:16:42.439152 DQS0 = 0, DQS1 = 0
3495 22:16:42.439645 DQM Delay:
3496 22:16:42.440027 DQM0 = 114, DQM1 = 105
3497 22:16:42.442119 DQ Delay:
3498 22:16:42.445570 DQ0 =118, DQ1 =108, DQ2 =104, DQ3 =112
3499 22:16:42.449124 DQ4 =112, DQ5 =120, DQ6 =128, DQ7 =112
3500 22:16:42.452031 DQ8 =94, DQ9 =96, DQ10 =104, DQ11 =102
3501 22:16:42.455637 DQ12 =114, DQ13 =110, DQ14 =114, DQ15 =110
3502 22:16:42.456124
3503 22:16:42.456499
3504 22:16:42.465669 [DQSOSCAuto] RK0, (LSB)MR18= 0xedf4, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 417 ps
3505 22:16:42.466101 CH1 RK0: MR19=303, MR18=EDF4
3506 22:16:42.472038 CH1_RK0: MR19=0x303, MR18=0xEDF4, DQSOSC=415, MR23=63, INC=38, DEC=25
3507 22:16:42.472491
3508 22:16:42.475334 ----->DramcWriteLeveling(PI) begin...
3509 22:16:42.475725 ==
3510 22:16:42.478755 Dram Type= 6, Freq= 0, CH_1, rank 1
3511 22:16:42.485139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3512 22:16:42.485374 ==
3513 22:16:42.488641 Write leveling (Byte 0): 23 => 23
3514 22:16:42.492013 Write leveling (Byte 1): 27 => 27
3515 22:16:42.492196 DramcWriteLeveling(PI) end<-----
3516 22:16:42.492341
3517 22:16:42.495210 ==
3518 22:16:42.498246 Dram Type= 6, Freq= 0, CH_1, rank 1
3519 22:16:42.502090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3520 22:16:42.502273 ==
3521 22:16:42.505173 [Gating] SW mode calibration
3522 22:16:42.511840 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3523 22:16:42.515034 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3524 22:16:42.521240 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3525 22:16:42.524688 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3526 22:16:42.528154 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3527 22:16:42.535209 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3528 22:16:42.537966 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3529 22:16:42.541224 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3530 22:16:42.547706 0 15 24 | B1->B0 | 3333 2323 | 0 0 | (0 1) (1 0)
3531 22:16:42.551230 0 15 28 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3532 22:16:42.554350 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3533 22:16:42.560874 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3534 22:16:42.564340 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3535 22:16:42.567840 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3536 22:16:42.574146 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3537 22:16:42.577688 1 0 20 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
3538 22:16:42.580970 1 0 24 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
3539 22:16:42.587489 1 0 28 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
3540 22:16:42.590326 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3541 22:16:42.594116 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3542 22:16:42.600466 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3543 22:16:42.603682 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3544 22:16:42.606866 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3545 22:16:42.614060 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3546 22:16:42.616862 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3547 22:16:42.620112 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3548 22:16:42.627264 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3549 22:16:42.629959 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3550 22:16:42.633582 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3551 22:16:42.639886 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3552 22:16:42.643822 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3553 22:16:42.646805 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3554 22:16:42.653062 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3555 22:16:42.656523 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3556 22:16:42.660035 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3557 22:16:42.666430 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3558 22:16:42.670082 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3559 22:16:42.672804 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3560 22:16:42.679935 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3561 22:16:42.682915 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3562 22:16:42.686414 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3563 22:16:42.692846 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3564 22:16:42.696257 Total UI for P1: 0, mck2ui 16
3565 22:16:42.699566 best dqsien dly found for B0: ( 1, 3, 24)
3566 22:16:42.702502 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3567 22:16:42.705860 Total UI for P1: 0, mck2ui 16
3568 22:16:42.709146 best dqsien dly found for B1: ( 1, 3, 26)
3569 22:16:42.712467 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3570 22:16:42.716096 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3571 22:16:42.716342
3572 22:16:42.719402 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3573 22:16:42.722403 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3574 22:16:42.725846 [Gating] SW calibration Done
3575 22:16:42.726089 ==
3576 22:16:42.729510 Dram Type= 6, Freq= 0, CH_1, rank 1
3577 22:16:42.735588 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3578 22:16:42.735837 ==
3579 22:16:42.736031 RX Vref Scan: 0
3580 22:16:42.736213
3581 22:16:42.739261 RX Vref 0 -> 0, step: 1
3582 22:16:42.739504
3583 22:16:42.742598 RX Delay -40 -> 252, step: 8
3584 22:16:42.745951 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3585 22:16:42.748987 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3586 22:16:42.752312 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3587 22:16:42.755764 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3588 22:16:42.762580 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3589 22:16:42.765468 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3590 22:16:42.769121 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3591 22:16:42.771894 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3592 22:16:42.775589 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3593 22:16:42.781785 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3594 22:16:42.785384 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3595 22:16:42.788755 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3596 22:16:42.791741 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3597 22:16:42.798887 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3598 22:16:42.801873 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3599 22:16:42.805127 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3600 22:16:42.805373 ==
3601 22:16:42.808296 Dram Type= 6, Freq= 0, CH_1, rank 1
3602 22:16:42.811961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3603 22:16:42.812282 ==
3604 22:16:42.815355 DQS Delay:
3605 22:16:42.815610 DQS0 = 0, DQS1 = 0
3606 22:16:42.818063 DQM Delay:
3607 22:16:42.818306 DQM0 = 111, DQM1 = 105
3608 22:16:42.818500 DQ Delay:
3609 22:16:42.821834 DQ0 =115, DQ1 =111, DQ2 =99, DQ3 =111
3610 22:16:42.828233 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =111
3611 22:16:42.831415 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =99
3612 22:16:42.834778 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
3613 22:16:42.835024
3614 22:16:42.835218
3615 22:16:42.835398 ==
3616 22:16:42.838061 Dram Type= 6, Freq= 0, CH_1, rank 1
3617 22:16:42.841522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3618 22:16:42.841917 ==
3619 22:16:42.842230
3620 22:16:42.842523
3621 22:16:42.845000 TX Vref Scan disable
3622 22:16:42.848479 == TX Byte 0 ==
3623 22:16:42.851318 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3624 22:16:42.854864 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3625 22:16:42.858237 == TX Byte 1 ==
3626 22:16:42.861303 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3627 22:16:42.865053 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3628 22:16:42.865674 ==
3629 22:16:42.868089 Dram Type= 6, Freq= 0, CH_1, rank 1
3630 22:16:42.871647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3631 22:16:42.874563 ==
3632 22:16:42.885009 TX Vref=22, minBit 9, minWin=25, winSum=417
3633 22:16:42.888000 TX Vref=24, minBit 0, minWin=26, winSum=425
3634 22:16:42.891423 TX Vref=26, minBit 8, minWin=26, winSum=428
3635 22:16:42.894420 TX Vref=28, minBit 8, minWin=26, winSum=430
3636 22:16:42.898001 TX Vref=30, minBit 9, minWin=26, winSum=434
3637 22:16:42.904176 TX Vref=32, minBit 3, minWin=26, winSum=431
3638 22:16:42.907543 [TxChooseVref] Worse bit 9, Min win 26, Win sum 434, Final Vref 30
3639 22:16:42.907741
3640 22:16:42.910880 Final TX Range 1 Vref 30
3641 22:16:42.911054
3642 22:16:42.911215 ==
3643 22:16:42.914572 Dram Type= 6, Freq= 0, CH_1, rank 1
3644 22:16:42.917405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3645 22:16:42.920840 ==
3646 22:16:42.921067
3647 22:16:42.921273
3648 22:16:42.921475 TX Vref Scan disable
3649 22:16:42.924245 == TX Byte 0 ==
3650 22:16:42.927622 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3651 22:16:42.934195 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3652 22:16:42.934420 == TX Byte 1 ==
3653 22:16:42.937816 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3654 22:16:42.943859 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3655 22:16:42.944089
3656 22:16:42.944250 [DATLAT]
3657 22:16:42.944396 Freq=1200, CH1 RK1
3658 22:16:42.944529
3659 22:16:42.947725 DATLAT Default: 0xd
3660 22:16:42.950944 0, 0xFFFF, sum = 0
3661 22:16:42.951175 1, 0xFFFF, sum = 0
3662 22:16:42.953949 2, 0xFFFF, sum = 0
3663 22:16:42.954135 3, 0xFFFF, sum = 0
3664 22:16:42.957316 4, 0xFFFF, sum = 0
3665 22:16:42.957500 5, 0xFFFF, sum = 0
3666 22:16:42.960850 6, 0xFFFF, sum = 0
3667 22:16:42.961033 7, 0xFFFF, sum = 0
3668 22:16:42.963861 8, 0xFFFF, sum = 0
3669 22:16:42.964044 9, 0xFFFF, sum = 0
3670 22:16:42.967013 10, 0xFFFF, sum = 0
3671 22:16:42.967096 11, 0xFFFF, sum = 0
3672 22:16:42.970559 12, 0x0, sum = 1
3673 22:16:42.970641 13, 0x0, sum = 2
3674 22:16:42.973802 14, 0x0, sum = 3
3675 22:16:42.973885 15, 0x0, sum = 4
3676 22:16:42.977381 best_step = 13
3677 22:16:42.977462
3678 22:16:42.977527 ==
3679 22:16:42.980301 Dram Type= 6, Freq= 0, CH_1, rank 1
3680 22:16:42.983766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3681 22:16:42.983848 ==
3682 22:16:42.987413 RX Vref Scan: 0
3683 22:16:42.987520
3684 22:16:42.987645 RX Vref 0 -> 0, step: 1
3685 22:16:42.987708
3686 22:16:42.990404 RX Delay -21 -> 252, step: 4
3687 22:16:42.996770 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3688 22:16:43.000377 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3689 22:16:43.003463 iDelay=195, Bit 2, Center 102 (35 ~ 170) 136
3690 22:16:43.007057 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3691 22:16:43.010031 iDelay=195, Bit 4, Center 108 (39 ~ 178) 140
3692 22:16:43.016358 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3693 22:16:43.019598 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3694 22:16:43.023436 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3695 22:16:43.026665 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3696 22:16:43.029639 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3697 22:16:43.036541 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3698 22:16:43.039837 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3699 22:16:43.043031 iDelay=195, Bit 12, Center 116 (51 ~ 182) 132
3700 22:16:43.046339 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3701 22:16:43.052728 iDelay=195, Bit 14, Center 114 (51 ~ 178) 128
3702 22:16:43.056343 iDelay=195, Bit 15, Center 116 (51 ~ 182) 132
3703 22:16:43.056425 ==
3704 22:16:43.059322 Dram Type= 6, Freq= 0, CH_1, rank 1
3705 22:16:43.062553 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3706 22:16:43.062635 ==
3707 22:16:43.066205 DQS Delay:
3708 22:16:43.066286 DQS0 = 0, DQS1 = 0
3709 22:16:43.066351 DQM Delay:
3710 22:16:43.069792 DQM0 = 111, DQM1 = 109
3711 22:16:43.069874 DQ Delay:
3712 22:16:43.072626 DQ0 =114, DQ1 =110, DQ2 =102, DQ3 =108
3713 22:16:43.075873 DQ4 =108, DQ5 =120, DQ6 =120, DQ7 =110
3714 22:16:43.079307 DQ8 =98, DQ9 =102, DQ10 =110, DQ11 =104
3715 22:16:43.085585 DQ12 =116, DQ13 =116, DQ14 =114, DQ15 =116
3716 22:16:43.085667
3717 22:16:43.085731
3718 22:16:43.092523 [DQSOSCAuto] RK1, (LSB)MR18= 0xf908, (MSB)MR19= 0x304, tDQSOscB0 = 406 ps tDQSOscB1 = 412 ps
3719 22:16:43.095680 CH1 RK1: MR19=304, MR18=F908
3720 22:16:43.102056 CH1_RK1: MR19=0x304, MR18=0xF908, DQSOSC=406, MR23=63, INC=39, DEC=26
3721 22:16:43.105451 [RxdqsGatingPostProcess] freq 1200
3722 22:16:43.109127 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3723 22:16:43.112004 best DQS0 dly(2T, 0.5T) = (0, 11)
3724 22:16:43.115535 best DQS1 dly(2T, 0.5T) = (0, 11)
3725 22:16:43.118701 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3726 22:16:43.121982 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3727 22:16:43.125287 best DQS0 dly(2T, 0.5T) = (0, 11)
3728 22:16:43.128650 best DQS1 dly(2T, 0.5T) = (0, 11)
3729 22:16:43.131815 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3730 22:16:43.135218 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3731 22:16:43.138288 Pre-setting of DQS Precalculation
3732 22:16:43.141605 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3733 22:16:43.152082 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3734 22:16:43.158416 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3735 22:16:43.158499
3736 22:16:43.158564
3737 22:16:43.161422 [Calibration Summary] 2400 Mbps
3738 22:16:43.161503 CH 0, Rank 0
3739 22:16:43.164922 SW Impedance : PASS
3740 22:16:43.168097 DUTY Scan : NO K
3741 22:16:43.168180 ZQ Calibration : PASS
3742 22:16:43.171318 Jitter Meter : NO K
3743 22:16:43.174610 CBT Training : PASS
3744 22:16:43.174691 Write leveling : PASS
3745 22:16:43.178231 RX DQS gating : PASS
3746 22:16:43.178313 RX DQ/DQS(RDDQC) : PASS
3747 22:16:43.181482 TX DQ/DQS : PASS
3748 22:16:43.184806 RX DATLAT : PASS
3749 22:16:43.184889 RX DQ/DQS(Engine): PASS
3750 22:16:43.187550 TX OE : NO K
3751 22:16:43.187673 All Pass.
3752 22:16:43.187739
3753 22:16:43.191203 CH 0, Rank 1
3754 22:16:43.191285 SW Impedance : PASS
3755 22:16:43.194761 DUTY Scan : NO K
3756 22:16:43.197566 ZQ Calibration : PASS
3757 22:16:43.197648 Jitter Meter : NO K
3758 22:16:43.201009 CBT Training : PASS
3759 22:16:43.204081 Write leveling : PASS
3760 22:16:43.204163 RX DQS gating : PASS
3761 22:16:43.207756 RX DQ/DQS(RDDQC) : PASS
3762 22:16:43.210646 TX DQ/DQS : PASS
3763 22:16:43.210728 RX DATLAT : PASS
3764 22:16:43.214027 RX DQ/DQS(Engine): PASS
3765 22:16:43.217552 TX OE : NO K
3766 22:16:43.217634 All Pass.
3767 22:16:43.217699
3768 22:16:43.217759 CH 1, Rank 0
3769 22:16:43.220989 SW Impedance : PASS
3770 22:16:43.224051 DUTY Scan : NO K
3771 22:16:43.224133 ZQ Calibration : PASS
3772 22:16:43.227324 Jitter Meter : NO K
3773 22:16:43.230932 CBT Training : PASS
3774 22:16:43.231015 Write leveling : PASS
3775 22:16:43.233773 RX DQS gating : PASS
3776 22:16:43.237124 RX DQ/DQS(RDDQC) : PASS
3777 22:16:43.237206 TX DQ/DQS : PASS
3778 22:16:43.240610 RX DATLAT : PASS
3779 22:16:43.243558 RX DQ/DQS(Engine): PASS
3780 22:16:43.243649 TX OE : NO K
3781 22:16:43.246913 All Pass.
3782 22:16:43.246995
3783 22:16:43.247060 CH 1, Rank 1
3784 22:16:43.250408 SW Impedance : PASS
3785 22:16:43.250490 DUTY Scan : NO K
3786 22:16:43.253582 ZQ Calibration : PASS
3787 22:16:43.256869 Jitter Meter : NO K
3788 22:16:43.256951 CBT Training : PASS
3789 22:16:43.260131 Write leveling : PASS
3790 22:16:43.263619 RX DQS gating : PASS
3791 22:16:43.263701 RX DQ/DQS(RDDQC) : PASS
3792 22:16:43.266880 TX DQ/DQS : PASS
3793 22:16:43.269744 RX DATLAT : PASS
3794 22:16:43.269823 RX DQ/DQS(Engine): PASS
3795 22:16:43.273403 TX OE : NO K
3796 22:16:43.273484 All Pass.
3797 22:16:43.273546
3798 22:16:43.276370 DramC Write-DBI off
3799 22:16:43.280225 PER_BANK_REFRESH: Hybrid Mode
3800 22:16:43.280299 TX_TRACKING: ON
3801 22:16:43.289611 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3802 22:16:43.293386 [FAST_K] Save calibration result to emmc
3803 22:16:43.296380 dramc_set_vcore_voltage set vcore to 650000
3804 22:16:43.299746 Read voltage for 600, 5
3805 22:16:43.299819 Vio18 = 0
3806 22:16:43.299880 Vcore = 650000
3807 22:16:43.302883 Vdram = 0
3808 22:16:43.302951 Vddq = 0
3809 22:16:43.303017 Vmddr = 0
3810 22:16:43.309265 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3811 22:16:43.312553 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3812 22:16:43.316187 MEM_TYPE=3, freq_sel=19
3813 22:16:43.319108 sv_algorithm_assistance_LP4_1600
3814 22:16:43.322529 ============ PULL DRAM RESETB DOWN ============
3815 22:16:43.326112 ========== PULL DRAM RESETB DOWN end =========
3816 22:16:43.332423 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3817 22:16:43.335607 ===================================
3818 22:16:43.335679 LPDDR4 DRAM CONFIGURATION
3819 22:16:43.339452 ===================================
3820 22:16:43.342345 EX_ROW_EN[0] = 0x0
3821 22:16:43.345909 EX_ROW_EN[1] = 0x0
3822 22:16:43.345982 LP4Y_EN = 0x0
3823 22:16:43.348985 WORK_FSP = 0x0
3824 22:16:43.349060 WL = 0x2
3825 22:16:43.352414 RL = 0x2
3826 22:16:43.352485 BL = 0x2
3827 22:16:43.355775 RPST = 0x0
3828 22:16:43.355856 RD_PRE = 0x0
3829 22:16:43.358953 WR_PRE = 0x1
3830 22:16:43.359021 WR_PST = 0x0
3831 22:16:43.362455 DBI_WR = 0x0
3832 22:16:43.362526 DBI_RD = 0x0
3833 22:16:43.365675 OTF = 0x1
3834 22:16:43.368936 ===================================
3835 22:16:43.372306 ===================================
3836 22:16:43.372384 ANA top config
3837 22:16:43.375190 ===================================
3838 22:16:43.379085 DLL_ASYNC_EN = 0
3839 22:16:43.381806 ALL_SLAVE_EN = 1
3840 22:16:43.385370 NEW_RANK_MODE = 1
3841 22:16:43.385462 DLL_IDLE_MODE = 1
3842 22:16:43.388956 LP45_APHY_COMB_EN = 1
3843 22:16:43.392159 TX_ODT_DIS = 1
3844 22:16:43.396090 NEW_8X_MODE = 1
3845 22:16:43.398777 ===================================
3846 22:16:43.402542 ===================================
3847 22:16:43.406026 data_rate = 1200
3848 22:16:43.408654 CKR = 1
3849 22:16:43.409194 DQ_P2S_RATIO = 8
3850 22:16:43.412112 ===================================
3851 22:16:43.415669 CA_P2S_RATIO = 8
3852 22:16:43.418632 DQ_CA_OPEN = 0
3853 22:16:43.422039 DQ_SEMI_OPEN = 0
3854 22:16:43.425151 CA_SEMI_OPEN = 0
3855 22:16:43.428700 CA_FULL_RATE = 0
3856 22:16:43.429257 DQ_CKDIV4_EN = 1
3857 22:16:43.432160 CA_CKDIV4_EN = 1
3858 22:16:43.434986 CA_PREDIV_EN = 0
3859 22:16:43.438660 PH8_DLY = 0
3860 22:16:43.441575 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3861 22:16:43.444865 DQ_AAMCK_DIV = 4
3862 22:16:43.445447 CA_AAMCK_DIV = 4
3863 22:16:43.448101 CA_ADMCK_DIV = 4
3864 22:16:43.451572 DQ_TRACK_CA_EN = 0
3865 22:16:43.455057 CA_PICK = 600
3866 22:16:43.458148 CA_MCKIO = 600
3867 22:16:43.461271 MCKIO_SEMI = 0
3868 22:16:43.465232 PLL_FREQ = 2288
3869 22:16:43.467806 DQ_UI_PI_RATIO = 32
3870 22:16:43.468294 CA_UI_PI_RATIO = 0
3871 22:16:43.471486 ===================================
3872 22:16:43.474712 ===================================
3873 22:16:43.478306 memory_type:LPDDR4
3874 22:16:43.480887 GP_NUM : 10
3875 22:16:43.481132 SRAM_EN : 1
3876 22:16:43.484852 MD32_EN : 0
3877 22:16:43.487432 ===================================
3878 22:16:43.491215 [ANA_INIT] >>>>>>>>>>>>>>
3879 22:16:43.493874 <<<<<< [CONFIGURE PHASE]: ANA_TX
3880 22:16:43.497435 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3881 22:16:43.500546 ===================================
3882 22:16:43.500787 data_rate = 1200,PCW = 0X5800
3883 22:16:43.504235 ===================================
3884 22:16:43.507543 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3885 22:16:43.513987 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3886 22:16:43.520198 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3887 22:16:43.523733 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3888 22:16:43.526831 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3889 22:16:43.530321 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3890 22:16:43.533633 [ANA_INIT] flow start
3891 22:16:43.536615 [ANA_INIT] PLL >>>>>>>>
3892 22:16:43.536795 [ANA_INIT] PLL <<<<<<<<
3893 22:16:43.540118 [ANA_INIT] MIDPI >>>>>>>>
3894 22:16:43.543719 [ANA_INIT] MIDPI <<<<<<<<
3895 22:16:43.543968 [ANA_INIT] DLL >>>>>>>>
3896 22:16:43.546423 [ANA_INIT] flow end
3897 22:16:43.550099 ============ LP4 DIFF to SE enter ============
3898 22:16:43.556667 ============ LP4 DIFF to SE exit ============
3899 22:16:43.557041 [ANA_INIT] <<<<<<<<<<<<<
3900 22:16:43.559721 [Flow] Enable top DCM control >>>>>
3901 22:16:43.563082 [Flow] Enable top DCM control <<<<<
3902 22:16:43.566756 Enable DLL master slave shuffle
3903 22:16:43.573276 ==============================================================
3904 22:16:43.573644 Gating Mode config
3905 22:16:43.579789 ==============================================================
3906 22:16:43.583416 Config description:
3907 22:16:43.592825 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3908 22:16:43.599222 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3909 22:16:43.602487 SELPH_MODE 0: By rank 1: By Phase
3910 22:16:43.609153 ==============================================================
3911 22:16:43.612560 GAT_TRACK_EN = 1
3912 22:16:43.615601 RX_GATING_MODE = 2
3913 22:16:43.615775 RX_GATING_TRACK_MODE = 2
3914 22:16:43.619191 SELPH_MODE = 1
3915 22:16:43.622412 PICG_EARLY_EN = 1
3916 22:16:43.625676 VALID_LAT_VALUE = 1
3917 22:16:43.632063 ==============================================================
3918 22:16:43.635629 Enter into Gating configuration >>>>
3919 22:16:43.638981 Exit from Gating configuration <<<<
3920 22:16:43.642588 Enter into DVFS_PRE_config >>>>>
3921 22:16:43.651987 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3922 22:16:43.655513 Exit from DVFS_PRE_config <<<<<
3923 22:16:43.659022 Enter into PICG configuration >>>>
3924 22:16:43.662072 Exit from PICG configuration <<<<
3925 22:16:43.665176 [RX_INPUT] configuration >>>>>
3926 22:16:43.669043 [RX_INPUT] configuration <<<<<
3927 22:16:43.672212 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3928 22:16:43.678874 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3929 22:16:43.685536 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3930 22:16:43.691675 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3931 22:16:43.698099 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3932 22:16:43.704890 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3933 22:16:43.708265 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3934 22:16:43.711632 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3935 22:16:43.714962 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3936 22:16:43.721292 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3937 22:16:43.724543 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3938 22:16:43.728202 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3939 22:16:43.731201 ===================================
3940 22:16:43.734675 LPDDR4 DRAM CONFIGURATION
3941 22:16:43.738159 ===================================
3942 22:16:43.738801 EX_ROW_EN[0] = 0x0
3943 22:16:43.741316 EX_ROW_EN[1] = 0x0
3944 22:16:43.741871 LP4Y_EN = 0x0
3945 22:16:43.744294 WORK_FSP = 0x0
3946 22:16:43.747713 WL = 0x2
3947 22:16:43.748318 RL = 0x2
3948 22:16:43.750665 BL = 0x2
3949 22:16:43.751260 RPST = 0x0
3950 22:16:43.754289 RD_PRE = 0x0
3951 22:16:43.754752 WR_PRE = 0x1
3952 22:16:43.757363 WR_PST = 0x0
3953 22:16:43.757954 DBI_WR = 0x0
3954 22:16:43.760743 DBI_RD = 0x0
3955 22:16:43.761224 OTF = 0x1
3956 22:16:43.764079 ===================================
3957 22:16:43.767448 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3958 22:16:43.774017 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3959 22:16:43.776751 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3960 22:16:43.780215 ===================================
3961 22:16:43.783400 LPDDR4 DRAM CONFIGURATION
3962 22:16:43.786797 ===================================
3963 22:16:43.787004 EX_ROW_EN[0] = 0x10
3964 22:16:43.789966 EX_ROW_EN[1] = 0x0
3965 22:16:43.793984 LP4Y_EN = 0x0
3966 22:16:43.794227 WORK_FSP = 0x0
3967 22:16:43.796539 WL = 0x2
3968 22:16:43.796788 RL = 0x2
3969 22:16:43.799819 BL = 0x2
3970 22:16:43.800016 RPST = 0x0
3971 22:16:43.803421 RD_PRE = 0x0
3972 22:16:43.803681 WR_PRE = 0x1
3973 22:16:43.806608 WR_PST = 0x0
3974 22:16:43.806854 DBI_WR = 0x0
3975 22:16:43.809958 DBI_RD = 0x0
3976 22:16:43.810206 OTF = 0x1
3977 22:16:43.813506 ===================================
3978 22:16:43.819642 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3979 22:16:43.824261 nWR fixed to 30
3980 22:16:43.827532 [ModeRegInit_LP4] CH0 RK0
3981 22:16:43.827620 [ModeRegInit_LP4] CH0 RK1
3982 22:16:43.831148 [ModeRegInit_LP4] CH1 RK0
3983 22:16:43.834071 [ModeRegInit_LP4] CH1 RK1
3984 22:16:43.834160 match AC timing 17
3985 22:16:43.840498 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3986 22:16:43.844057 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3987 22:16:43.847404 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3988 22:16:43.853756 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3989 22:16:43.857313 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3990 22:16:43.857420 ==
3991 22:16:43.860642 Dram Type= 6, Freq= 0, CH_0, rank 0
3992 22:16:43.863757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3993 22:16:43.863843 ==
3994 22:16:43.870024 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3995 22:16:43.877370 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3996 22:16:43.879883 [CA 0] Center 37 (7~67) winsize 61
3997 22:16:43.883326 [CA 1] Center 37 (7~67) winsize 61
3998 22:16:43.887065 [CA 2] Center 35 (5~65) winsize 61
3999 22:16:43.889964 [CA 3] Center 34 (4~65) winsize 62
4000 22:16:43.893328 [CA 4] Center 34 (4~65) winsize 62
4001 22:16:43.896373 [CA 5] Center 34 (4~64) winsize 61
4002 22:16:43.896456
4003 22:16:43.899679 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4004 22:16:43.899761
4005 22:16:43.903591 [CATrainingPosCal] consider 1 rank data
4006 22:16:43.906148 u2DelayCellTimex100 = 270/100 ps
4007 22:16:43.909424 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4008 22:16:43.912787 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
4009 22:16:43.916224 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4010 22:16:43.922814 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4011 22:16:43.926319 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4012 22:16:43.929573 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4013 22:16:43.929655
4014 22:16:43.933109 CA PerBit enable=1, Macro0, CA PI delay=34
4015 22:16:43.933191
4016 22:16:43.936129 [CBTSetCACLKResult] CA Dly = 34
4017 22:16:43.936212 CS Dly: 4 (0~35)
4018 22:16:43.936284 ==
4019 22:16:43.939440 Dram Type= 6, Freq= 0, CH_0, rank 1
4020 22:16:43.945990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4021 22:16:43.946073 ==
4022 22:16:43.949447 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4023 22:16:43.955890 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4024 22:16:43.959381 [CA 0] Center 37 (7~67) winsize 61
4025 22:16:43.962923 [CA 1] Center 37 (7~67) winsize 61
4026 22:16:43.966404 [CA 2] Center 35 (5~65) winsize 61
4027 22:16:43.969381 [CA 3] Center 35 (5~65) winsize 61
4028 22:16:43.972799 [CA 4] Center 34 (3~65) winsize 63
4029 22:16:43.976284 [CA 5] Center 33 (3~64) winsize 62
4030 22:16:43.976367
4031 22:16:43.979303 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4032 22:16:43.979386
4033 22:16:43.983002 [CATrainingPosCal] consider 2 rank data
4034 22:16:43.986075 u2DelayCellTimex100 = 270/100 ps
4035 22:16:43.989260 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
4036 22:16:43.995850 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
4037 22:16:43.999335 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
4038 22:16:44.002349 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
4039 22:16:44.005503 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4040 22:16:44.009314 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4041 22:16:44.009422
4042 22:16:44.012119 CA PerBit enable=1, Macro0, CA PI delay=34
4043 22:16:44.012196
4044 22:16:44.015295 [CBTSetCACLKResult] CA Dly = 34
4045 22:16:44.019056 CS Dly: 5 (0~37)
4046 22:16:44.019134
4047 22:16:44.022025 ----->DramcWriteLeveling(PI) begin...
4048 22:16:44.022098 ==
4049 22:16:44.025434 Dram Type= 6, Freq= 0, CH_0, rank 0
4050 22:16:44.028733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4051 22:16:44.028808 ==
4052 22:16:44.032218 Write leveling (Byte 0): 34 => 34
4053 22:16:44.035366 Write leveling (Byte 1): 29 => 29
4054 22:16:44.038494 DramcWriteLeveling(PI) end<-----
4055 22:16:44.038570
4056 22:16:44.038630 ==
4057 22:16:44.041813 Dram Type= 6, Freq= 0, CH_0, rank 0
4058 22:16:44.045399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4059 22:16:44.045476 ==
4060 22:16:44.048450 [Gating] SW mode calibration
4061 22:16:44.055414 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4062 22:16:44.061574 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4063 22:16:44.065174 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4064 22:16:44.068152 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4065 22:16:44.075049 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4066 22:16:44.078489 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
4067 22:16:44.081405 0 9 16 | B1->B0 | 3131 2f2f | 0 0 | (0 1) (1 1)
4068 22:16:44.088132 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4069 22:16:44.091286 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4070 22:16:44.094564 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4071 22:16:44.100949 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4072 22:16:44.104338 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4073 22:16:44.107555 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4074 22:16:44.114699 0 10 12 | B1->B0 | 2525 2c2c | 0 0 | (0 0) (0 0)
4075 22:16:44.117959 0 10 16 | B1->B0 | 3535 3a3a | 0 0 | (0 0) (0 0)
4076 22:16:44.121089 0 10 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4077 22:16:44.127536 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4078 22:16:44.130788 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4079 22:16:44.134062 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4080 22:16:44.140597 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4081 22:16:44.144361 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4082 22:16:44.147323 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4083 22:16:44.153808 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4084 22:16:44.157188 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4085 22:16:44.160470 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4086 22:16:44.166945 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4087 22:16:44.170339 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4088 22:16:44.173337 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4089 22:16:44.180182 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4090 22:16:44.183507 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4091 22:16:44.190144 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4092 22:16:44.193150 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4093 22:16:44.196852 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4094 22:16:44.199778 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4095 22:16:44.206326 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4096 22:16:44.209713 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4097 22:16:44.216299 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4098 22:16:44.219367 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4099 22:16:44.223155 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4100 22:16:44.226441 Total UI for P1: 0, mck2ui 16
4101 22:16:44.229511 best dqsien dly found for B0: ( 0, 13, 14)
4102 22:16:44.232484 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4103 22:16:44.235873 Total UI for P1: 0, mck2ui 16
4104 22:16:44.239265 best dqsien dly found for B1: ( 0, 13, 16)
4105 22:16:44.245487 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4106 22:16:44.249183 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4107 22:16:44.249266
4108 22:16:44.252205 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4109 22:16:44.255629 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4110 22:16:44.258744 [Gating] SW calibration Done
4111 22:16:44.258827 ==
4112 22:16:44.262329 Dram Type= 6, Freq= 0, CH_0, rank 0
4113 22:16:44.265568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4114 22:16:44.265652 ==
4115 22:16:44.268608 RX Vref Scan: 0
4116 22:16:44.268690
4117 22:16:44.268756 RX Vref 0 -> 0, step: 1
4118 22:16:44.268819
4119 22:16:44.272524 RX Delay -230 -> 252, step: 16
4120 22:16:44.278801 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4121 22:16:44.282219 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4122 22:16:44.285142 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4123 22:16:44.288639 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4124 22:16:44.292292 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4125 22:16:44.298724 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4126 22:16:44.301990 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4127 22:16:44.305602 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4128 22:16:44.308508 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4129 22:16:44.314950 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4130 22:16:44.318163 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4131 22:16:44.321489 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4132 22:16:44.325166 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4133 22:16:44.331216 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4134 22:16:44.334553 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4135 22:16:44.338355 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4136 22:16:44.338438 ==
4137 22:16:44.341370 Dram Type= 6, Freq= 0, CH_0, rank 0
4138 22:16:44.344640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4139 22:16:44.348287 ==
4140 22:16:44.348370 DQS Delay:
4141 22:16:44.348436 DQS0 = 0, DQS1 = 0
4142 22:16:44.351492 DQM Delay:
4143 22:16:44.351575 DQM0 = 38, DQM1 = 29
4144 22:16:44.354509 DQ Delay:
4145 22:16:44.357804 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4146 22:16:44.357886 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4147 22:16:44.361183 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4148 22:16:44.367562 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4149 22:16:44.367661
4150 22:16:44.367727
4151 22:16:44.367787 ==
4152 22:16:44.370826 Dram Type= 6, Freq= 0, CH_0, rank 0
4153 22:16:44.374664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4154 22:16:44.374747 ==
4155 22:16:44.374813
4156 22:16:44.374874
4157 22:16:44.377531 TX Vref Scan disable
4158 22:16:44.377613 == TX Byte 0 ==
4159 22:16:44.384475 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4160 22:16:44.387415 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4161 22:16:44.390845 == TX Byte 1 ==
4162 22:16:44.393998 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4163 22:16:44.397513 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4164 22:16:44.397635 ==
4165 22:16:44.400650 Dram Type= 6, Freq= 0, CH_0, rank 0
4166 22:16:44.404103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4167 22:16:44.406880 ==
4168 22:16:44.406996
4169 22:16:44.407064
4170 22:16:44.407132 TX Vref Scan disable
4171 22:16:44.410908 == TX Byte 0 ==
4172 22:16:44.414610 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4173 22:16:44.421161 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4174 22:16:44.421236 == TX Byte 1 ==
4175 22:16:44.424183 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4176 22:16:44.430784 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4177 22:16:44.430861
4178 22:16:44.430975 [DATLAT]
4179 22:16:44.431067 Freq=600, CH0 RK0
4180 22:16:44.431170
4181 22:16:44.434628 DATLAT Default: 0x9
4182 22:16:44.434701 0, 0xFFFF, sum = 0
4183 22:16:44.437927 1, 0xFFFF, sum = 0
4184 22:16:44.440789 2, 0xFFFF, sum = 0
4185 22:16:44.440878 3, 0xFFFF, sum = 0
4186 22:16:44.444146 4, 0xFFFF, sum = 0
4187 22:16:44.444244 5, 0xFFFF, sum = 0
4188 22:16:44.447384 6, 0xFFFF, sum = 0
4189 22:16:44.447503 7, 0xFFFF, sum = 0
4190 22:16:44.450534 8, 0x0, sum = 1
4191 22:16:44.450610 9, 0x0, sum = 2
4192 22:16:44.450674 10, 0x0, sum = 3
4193 22:16:44.454038 11, 0x0, sum = 4
4194 22:16:44.454110 best_step = 9
4195 22:16:44.454177
4196 22:16:44.454236 ==
4197 22:16:44.457324 Dram Type= 6, Freq= 0, CH_0, rank 0
4198 22:16:44.464263 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4199 22:16:44.464343 ==
4200 22:16:44.464406 RX Vref Scan: 1
4201 22:16:44.464464
4202 22:16:44.467237 RX Vref 0 -> 0, step: 1
4203 22:16:44.467303
4204 22:16:44.470317 RX Delay -195 -> 252, step: 8
4205 22:16:44.470384
4206 22:16:44.473611 Set Vref, RX VrefLevel [Byte0]: 61
4207 22:16:44.477047 [Byte1]: 56
4208 22:16:44.477117
4209 22:16:44.480613 Final RX Vref Byte 0 = 61 to rank0
4210 22:16:44.483499 Final RX Vref Byte 1 = 56 to rank0
4211 22:16:44.487255 Final RX Vref Byte 0 = 61 to rank1
4212 22:16:44.490563 Final RX Vref Byte 1 = 56 to rank1==
4213 22:16:44.493793 Dram Type= 6, Freq= 0, CH_0, rank 0
4214 22:16:44.496808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4215 22:16:44.500283 ==
4216 22:16:44.500366 DQS Delay:
4217 22:16:44.500431 DQS0 = 0, DQS1 = 0
4218 22:16:44.503435 DQM Delay:
4219 22:16:44.503517 DQM0 = 35, DQM1 = 29
4220 22:16:44.506670 DQ Delay:
4221 22:16:44.506756 DQ0 =36, DQ1 =36, DQ2 =36, DQ3 =32
4222 22:16:44.510089 DQ4 =32, DQ5 =24, DQ6 =44, DQ7 =44
4223 22:16:44.513633 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4224 22:16:44.517084 DQ12 =36, DQ13 =36, DQ14 =40, DQ15 =36
4225 22:16:44.517167
4226 22:16:44.520529
4227 22:16:44.526813 [DQSOSCAuto] RK0, (LSB)MR18= 0x4342, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 397 ps
4228 22:16:44.529844 CH0 RK0: MR19=808, MR18=4342
4229 22:16:44.536543 CH0_RK0: MR19=0x808, MR18=0x4342, DQSOSC=397, MR23=63, INC=166, DEC=110
4230 22:16:44.536628
4231 22:16:44.540187 ----->DramcWriteLeveling(PI) begin...
4232 22:16:44.540270 ==
4233 22:16:44.543452 Dram Type= 6, Freq= 0, CH_0, rank 1
4234 22:16:44.546568 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4235 22:16:44.546651 ==
4236 22:16:44.549910 Write leveling (Byte 0): 32 => 32
4237 22:16:44.553133 Write leveling (Byte 1): 32 => 32
4238 22:16:44.556575 DramcWriteLeveling(PI) end<-----
4239 22:16:44.556658
4240 22:16:44.556723 ==
4241 22:16:44.559870 Dram Type= 6, Freq= 0, CH_0, rank 1
4242 22:16:44.563064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4243 22:16:44.563163 ==
4244 22:16:44.566517 [Gating] SW mode calibration
4245 22:16:44.573073 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4246 22:16:44.579972 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4247 22:16:44.582798 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4248 22:16:44.586359 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4249 22:16:44.592551 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4250 22:16:44.596194 0 9 12 | B1->B0 | 3232 2f2f | 1 1 | (1 1) (1 1)
4251 22:16:44.599223 0 9 16 | B1->B0 | 2f2f 2727 | 1 0 | (0 0) (0 0)
4252 22:16:44.606187 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4253 22:16:44.609031 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4254 22:16:44.612653 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4255 22:16:44.618934 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4256 22:16:44.622295 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4257 22:16:44.626042 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4258 22:16:44.632279 0 10 12 | B1->B0 | 2727 3737 | 0 0 | (0 0) (0 0)
4259 22:16:44.635598 0 10 16 | B1->B0 | 4141 4444 | 0 0 | (0 0) (0 0)
4260 22:16:44.642084 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4261 22:16:44.645352 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4262 22:16:44.648645 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4263 22:16:44.655224 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4264 22:16:44.658514 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4265 22:16:44.661789 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4266 22:16:44.668812 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4267 22:16:44.671847 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4268 22:16:44.675555 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4269 22:16:44.681856 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4270 22:16:44.685336 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4271 22:16:44.688221 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4272 22:16:44.694893 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4273 22:16:44.698415 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4274 22:16:44.701765 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4275 22:16:44.708073 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4276 22:16:44.711009 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4277 22:16:44.714368 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4278 22:16:44.720879 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4279 22:16:44.724312 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4280 22:16:44.727651 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4281 22:16:44.734394 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4282 22:16:44.737388 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4283 22:16:44.740905 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4284 22:16:44.744044 Total UI for P1: 0, mck2ui 16
4285 22:16:44.747599 best dqsien dly found for B0: ( 0, 13, 12)
4286 22:16:44.750893 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4287 22:16:44.754164 Total UI for P1: 0, mck2ui 16
4288 22:16:44.757344 best dqsien dly found for B1: ( 0, 13, 16)
4289 22:16:44.763968 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4290 22:16:44.767215 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4291 22:16:44.767298
4292 22:16:44.770624 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4293 22:16:44.773886 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4294 22:16:44.777451 [Gating] SW calibration Done
4295 22:16:44.777535 ==
4296 22:16:44.780705 Dram Type= 6, Freq= 0, CH_0, rank 1
4297 22:16:44.783551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4298 22:16:44.783660 ==
4299 22:16:44.786850 RX Vref Scan: 0
4300 22:16:44.786933
4301 22:16:44.786998 RX Vref 0 -> 0, step: 1
4302 22:16:44.787060
4303 22:16:44.790476 RX Delay -230 -> 252, step: 16
4304 22:16:44.796849 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4305 22:16:44.800370 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4306 22:16:44.803219 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4307 22:16:44.807159 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4308 22:16:44.809933 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4309 22:16:44.816984 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4310 22:16:44.820176 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4311 22:16:44.823562 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4312 22:16:44.826888 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4313 22:16:44.833295 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4314 22:16:44.836210 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4315 22:16:44.840278 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4316 22:16:44.843077 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4317 22:16:44.849567 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4318 22:16:44.852771 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4319 22:16:44.856055 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4320 22:16:44.856137 ==
4321 22:16:44.859394 Dram Type= 6, Freq= 0, CH_0, rank 1
4322 22:16:44.862493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4323 22:16:44.865960 ==
4324 22:16:44.866043 DQS Delay:
4325 22:16:44.866109 DQS0 = 0, DQS1 = 0
4326 22:16:44.869225 DQM Delay:
4327 22:16:44.869307 DQM0 = 36, DQM1 = 28
4328 22:16:44.872347 DQ Delay:
4329 22:16:44.875701 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4330 22:16:44.875784 DQ4 =33, DQ5 =25, DQ6 =49, DQ7 =49
4331 22:16:44.879221 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4332 22:16:44.886051 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4333 22:16:44.886134
4334 22:16:44.886199
4335 22:16:44.886261 ==
4336 22:16:44.888894 Dram Type= 6, Freq= 0, CH_0, rank 1
4337 22:16:44.892138 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4338 22:16:44.892222 ==
4339 22:16:44.892288
4340 22:16:44.892350
4341 22:16:44.895709 TX Vref Scan disable
4342 22:16:44.895792 == TX Byte 0 ==
4343 22:16:44.902189 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4344 22:16:44.905687 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4345 22:16:44.905771 == TX Byte 1 ==
4346 22:16:44.911937 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4347 22:16:44.915627 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4348 22:16:44.915710 ==
4349 22:16:44.918558 Dram Type= 6, Freq= 0, CH_0, rank 1
4350 22:16:44.922120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4351 22:16:44.922204 ==
4352 22:16:44.924980
4353 22:16:44.925063
4354 22:16:44.925128 TX Vref Scan disable
4355 22:16:44.929153 == TX Byte 0 ==
4356 22:16:44.932271 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4357 22:16:44.938910 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4358 22:16:44.938993 == TX Byte 1 ==
4359 22:16:44.942176 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4360 22:16:44.949069 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4361 22:16:44.949158
4362 22:16:44.949227 [DATLAT]
4363 22:16:44.949291 Freq=600, CH0 RK1
4364 22:16:44.949354
4365 22:16:44.952036 DATLAT Default: 0x9
4366 22:16:44.952128 0, 0xFFFF, sum = 0
4367 22:16:44.955402 1, 0xFFFF, sum = 0
4368 22:16:44.958561 2, 0xFFFF, sum = 0
4369 22:16:44.958662 3, 0xFFFF, sum = 0
4370 22:16:44.962057 4, 0xFFFF, sum = 0
4371 22:16:44.962167 5, 0xFFFF, sum = 0
4372 22:16:44.965291 6, 0xFFFF, sum = 0
4373 22:16:44.965401 7, 0xFFFF, sum = 0
4374 22:16:44.968398 8, 0x0, sum = 1
4375 22:16:44.968520 9, 0x0, sum = 2
4376 22:16:44.971739 10, 0x0, sum = 3
4377 22:16:44.971873 11, 0x0, sum = 4
4378 22:16:44.971979 best_step = 9
4379 22:16:44.972077
4380 22:16:44.974924 ==
4381 22:16:44.975056 Dram Type= 6, Freq= 0, CH_0, rank 1
4382 22:16:44.981507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4383 22:16:44.981677 ==
4384 22:16:44.981813 RX Vref Scan: 0
4385 22:16:44.981938
4386 22:16:44.985430 RX Vref 0 -> 0, step: 1
4387 22:16:44.985598
4388 22:16:44.988261 RX Delay -195 -> 252, step: 8
4389 22:16:44.994843 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4390 22:16:44.998109 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4391 22:16:45.001706 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4392 22:16:45.004667 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4393 22:16:45.011185 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4394 22:16:45.014385 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4395 22:16:45.018107 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4396 22:16:45.021200 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4397 22:16:45.024539 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4398 22:16:45.030951 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4399 22:16:45.034310 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4400 22:16:45.037884 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4401 22:16:45.041243 iDelay=205, Bit 12, Center 32 (-131 ~ 196) 328
4402 22:16:45.047991 iDelay=205, Bit 13, Center 32 (-131 ~ 196) 328
4403 22:16:45.051144 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4404 22:16:45.054802 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4405 22:16:45.055234 ==
4406 22:16:45.057434 Dram Type= 6, Freq= 0, CH_0, rank 1
4407 22:16:45.064548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4408 22:16:45.065095 ==
4409 22:16:45.065584 DQS Delay:
4410 22:16:45.065907 DQS0 = 0, DQS1 = 0
4411 22:16:45.067255 DQM Delay:
4412 22:16:45.067705 DQM0 = 34, DQM1 = 27
4413 22:16:45.070531 DQ Delay:
4414 22:16:45.074050 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4415 22:16:45.077252 DQ4 =36, DQ5 =20, DQ6 =44, DQ7 =44
4416 22:16:45.080680 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4417 22:16:45.083908 DQ12 =32, DQ13 =32, DQ14 =36, DQ15 =36
4418 22:16:45.084321
4419 22:16:45.084641
4420 22:16:45.090398 [DQSOSCAuto] RK1, (LSB)MR18= 0x6836, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
4421 22:16:45.094055 CH0 RK1: MR19=808, MR18=6836
4422 22:16:45.100447 CH0_RK1: MR19=0x808, MR18=0x6836, DQSOSC=390, MR23=63, INC=172, DEC=114
4423 22:16:45.103903 [RxdqsGatingPostProcess] freq 600
4424 22:16:45.106881 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4425 22:16:45.110444 Pre-setting of DQS Precalculation
4426 22:16:45.116883 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4427 22:16:45.117327 ==
4428 22:16:45.120108 Dram Type= 6, Freq= 0, CH_1, rank 0
4429 22:16:45.123670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4430 22:16:45.124096 ==
4431 22:16:45.130056 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4432 22:16:45.136640 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4433 22:16:45.139917 [CA 0] Center 35 (5~66) winsize 62
4434 22:16:45.143333 [CA 1] Center 36 (6~66) winsize 61
4435 22:16:45.146930 [CA 2] Center 34 (4~65) winsize 62
4436 22:16:45.149821 [CA 3] Center 34 (3~65) winsize 63
4437 22:16:45.153020 [CA 4] Center 34 (4~65) winsize 62
4438 22:16:45.156651 [CA 5] Center 33 (3~64) winsize 62
4439 22:16:45.157072
4440 22:16:45.159875 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4441 22:16:45.160301
4442 22:16:45.163197 [CATrainingPosCal] consider 1 rank data
4443 22:16:45.166341 u2DelayCellTimex100 = 270/100 ps
4444 22:16:45.169540 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4445 22:16:45.173301 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4446 22:16:45.176147 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4447 22:16:45.179858 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4448 22:16:45.183113 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4449 22:16:45.186230 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4450 22:16:45.186659
4451 22:16:45.192988 CA PerBit enable=1, Macro0, CA PI delay=33
4452 22:16:45.193416
4453 22:16:45.196122 [CBTSetCACLKResult] CA Dly = 33
4454 22:16:45.196543 CS Dly: 4 (0~35)
4455 22:16:45.196880 ==
4456 22:16:45.199327 Dram Type= 6, Freq= 0, CH_1, rank 1
4457 22:16:45.202662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4458 22:16:45.203087 ==
4459 22:16:45.209743 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4460 22:16:45.216014 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4461 22:16:45.219057 [CA 0] Center 36 (6~66) winsize 61
4462 22:16:45.222206 [CA 1] Center 36 (6~66) winsize 61
4463 22:16:45.225557 [CA 2] Center 34 (4~65) winsize 62
4464 22:16:45.228981 [CA 3] Center 34 (3~65) winsize 63
4465 22:16:45.232604 [CA 4] Center 34 (4~65) winsize 62
4466 22:16:45.235332 [CA 5] Center 33 (3~64) winsize 62
4467 22:16:45.235514
4468 22:16:45.238417 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4469 22:16:45.238499
4470 22:16:45.242364 [CATrainingPosCal] consider 2 rank data
4471 22:16:45.245284 u2DelayCellTimex100 = 270/100 ps
4472 22:16:45.248700 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4473 22:16:45.251693 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4474 22:16:45.255472 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4475 22:16:45.258415 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4476 22:16:45.265111 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4477 22:16:45.268466 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4478 22:16:45.268541
4479 22:16:45.271829 CA PerBit enable=1, Macro0, CA PI delay=33
4480 22:16:45.271928
4481 22:16:45.275061 [CBTSetCACLKResult] CA Dly = 33
4482 22:16:45.275140 CS Dly: 5 (0~37)
4483 22:16:45.275203
4484 22:16:45.278186 ----->DramcWriteLeveling(PI) begin...
4485 22:16:45.278261 ==
4486 22:16:45.281618 Dram Type= 6, Freq= 0, CH_1, rank 0
4487 22:16:45.288194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4488 22:16:45.288272 ==
4489 22:16:45.291303 Write leveling (Byte 0): 29 => 29
4490 22:16:45.294623 Write leveling (Byte 1): 29 => 29
4491 22:16:45.298004 DramcWriteLeveling(PI) end<-----
4492 22:16:45.298078
4493 22:16:45.298151 ==
4494 22:16:45.301520 Dram Type= 6, Freq= 0, CH_1, rank 0
4495 22:16:45.304407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4496 22:16:45.304493 ==
4497 22:16:45.307869 [Gating] SW mode calibration
4498 22:16:45.314513 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4499 22:16:45.321237 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4500 22:16:45.324185 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4501 22:16:45.327520 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4502 22:16:45.334386 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4503 22:16:45.337275 0 9 12 | B1->B0 | 3131 3232 | 0 0 | (0 0) (0 0)
4504 22:16:45.340803 0 9 16 | B1->B0 | 2525 2929 | 0 0 | (1 0) (0 0)
4505 22:16:45.344419 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4506 22:16:45.350611 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4507 22:16:45.353913 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4508 22:16:45.360652 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4509 22:16:45.364225 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4510 22:16:45.367035 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4511 22:16:45.370543 0 10 12 | B1->B0 | 2e2e 2f2f | 0 0 | (0 0) (1 1)
4512 22:16:45.377046 0 10 16 | B1->B0 | 4444 4444 | 0 0 | (0 0) (0 0)
4513 22:16:45.380308 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4514 22:16:45.386991 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4515 22:16:45.390021 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4516 22:16:45.393916 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4517 22:16:45.400228 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4518 22:16:45.403427 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4519 22:16:45.406898 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4520 22:16:45.412875 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4521 22:16:45.416498 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4522 22:16:45.419709 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4523 22:16:45.426572 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4524 22:16:45.429372 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4525 22:16:45.432695 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4526 22:16:45.439366 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4527 22:16:45.442377 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4528 22:16:45.445694 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4529 22:16:45.452880 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4530 22:16:45.455666 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4531 22:16:45.459398 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4532 22:16:45.465984 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4533 22:16:45.469609 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4534 22:16:45.472320 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4535 22:16:45.479549 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4536 22:16:45.482390 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4537 22:16:45.485965 Total UI for P1: 0, mck2ui 16
4538 22:16:45.489107 best dqsien dly found for B1: ( 0, 13, 12)
4539 22:16:45.492697 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4540 22:16:45.496049 Total UI for P1: 0, mck2ui 16
4541 22:16:45.498967 best dqsien dly found for B0: ( 0, 13, 16)
4542 22:16:45.502051 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4543 22:16:45.505318 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4544 22:16:45.505909
4545 22:16:45.512180 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4546 22:16:45.515651 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4547 22:16:45.518724 [Gating] SW calibration Done
4548 22:16:45.519182 ==
4549 22:16:45.521801 Dram Type= 6, Freq= 0, CH_1, rank 0
4550 22:16:45.525225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4551 22:16:45.525689 ==
4552 22:16:45.526055 RX Vref Scan: 0
4553 22:16:45.526397
4554 22:16:45.528762 RX Vref 0 -> 0, step: 1
4555 22:16:45.529224
4556 22:16:45.532009 RX Delay -230 -> 252, step: 16
4557 22:16:45.535098 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4558 22:16:45.541640 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4559 22:16:45.545076 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4560 22:16:45.548142 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4561 22:16:45.551610 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4562 22:16:45.554819 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4563 22:16:45.561307 iDelay=218, Bit 6, Center 41 (-134 ~ 217) 352
4564 22:16:45.564615 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4565 22:16:45.567817 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4566 22:16:45.571189 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4567 22:16:45.577690 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4568 22:16:45.581073 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4569 22:16:45.584617 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4570 22:16:45.587845 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4571 22:16:45.594466 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4572 22:16:45.597321 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4573 22:16:45.597512 ==
4574 22:16:45.600828 Dram Type= 6, Freq= 0, CH_1, rank 0
4575 22:16:45.604216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4576 22:16:45.604422 ==
4577 22:16:45.607312 DQS Delay:
4578 22:16:45.607500 DQS0 = 0, DQS1 = 0
4579 22:16:45.607673 DQM Delay:
4580 22:16:45.610776 DQM0 = 37, DQM1 = 28
4581 22:16:45.610999 DQ Delay:
4582 22:16:45.613902 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4583 22:16:45.617114 DQ4 =33, DQ5 =49, DQ6 =41, DQ7 =33
4584 22:16:45.620562 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4585 22:16:45.623724 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4586 22:16:45.623998
4587 22:16:45.624214
4588 22:16:45.624415 ==
4589 22:16:45.627097 Dram Type= 6, Freq= 0, CH_1, rank 0
4590 22:16:45.633915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4591 22:16:45.634192 ==
4592 22:16:45.634411
4593 22:16:45.634614
4594 22:16:45.637259 TX Vref Scan disable
4595 22:16:45.637634 == TX Byte 0 ==
4596 22:16:45.640516 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4597 22:16:45.646817 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4598 22:16:45.647091 == TX Byte 1 ==
4599 22:16:45.650208 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4600 22:16:45.656658 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4601 22:16:45.656939 ==
4602 22:16:45.660042 Dram Type= 6, Freq= 0, CH_1, rank 0
4603 22:16:45.663395 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4604 22:16:45.663700 ==
4605 22:16:45.663925
4606 22:16:45.664132
4607 22:16:45.667175 TX Vref Scan disable
4608 22:16:45.669914 == TX Byte 0 ==
4609 22:16:45.673424 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4610 22:16:45.676757 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4611 22:16:45.679847 == TX Byte 1 ==
4612 22:16:45.683147 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4613 22:16:45.686381 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4614 22:16:45.686467
4615 22:16:45.689640 [DATLAT]
4616 22:16:45.689728 Freq=600, CH1 RK0
4617 22:16:45.689795
4618 22:16:45.692816 DATLAT Default: 0x9
4619 22:16:45.692909 0, 0xFFFF, sum = 0
4620 22:16:45.696773 1, 0xFFFF, sum = 0
4621 22:16:45.696876 2, 0xFFFF, sum = 0
4622 22:16:45.699218 3, 0xFFFF, sum = 0
4623 22:16:45.699388 4, 0xFFFF, sum = 0
4624 22:16:45.702570 5, 0xFFFF, sum = 0
4625 22:16:45.702659 6, 0xFFFF, sum = 0
4626 22:16:45.706051 7, 0xFFFF, sum = 0
4627 22:16:45.706135 8, 0x0, sum = 1
4628 22:16:45.709221 9, 0x0, sum = 2
4629 22:16:45.709306 10, 0x0, sum = 3
4630 22:16:45.712844 11, 0x0, sum = 4
4631 22:16:45.712927 best_step = 9
4632 22:16:45.712992
4633 22:16:45.713053 ==
4634 22:16:45.716119 Dram Type= 6, Freq= 0, CH_1, rank 0
4635 22:16:45.722544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4636 22:16:45.722658 ==
4637 22:16:45.722725 RX Vref Scan: 1
4638 22:16:45.722786
4639 22:16:45.725900 RX Vref 0 -> 0, step: 1
4640 22:16:45.726002
4641 22:16:45.728907 RX Delay -195 -> 252, step: 8
4642 22:16:45.728989
4643 22:16:45.732128 Set Vref, RX VrefLevel [Byte0]: 55
4644 22:16:45.735531 [Byte1]: 50
4645 22:16:45.735663
4646 22:16:45.738967 Final RX Vref Byte 0 = 55 to rank0
4647 22:16:45.742385 Final RX Vref Byte 1 = 50 to rank0
4648 22:16:45.745397 Final RX Vref Byte 0 = 55 to rank1
4649 22:16:45.748675 Final RX Vref Byte 1 = 50 to rank1==
4650 22:16:45.752190 Dram Type= 6, Freq= 0, CH_1, rank 0
4651 22:16:45.755128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4652 22:16:45.755211 ==
4653 22:16:45.758749 DQS Delay:
4654 22:16:45.758832 DQS0 = 0, DQS1 = 0
4655 22:16:45.762232 DQM Delay:
4656 22:16:45.762317 DQM0 = 39, DQM1 = 28
4657 22:16:45.762383 DQ Delay:
4658 22:16:45.765174 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =36
4659 22:16:45.768543 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36
4660 22:16:45.772202 DQ8 =16, DQ9 =16, DQ10 =28, DQ11 =20
4661 22:16:45.775093 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4662 22:16:45.775179
4663 22:16:45.775244
4664 22:16:45.785038 [DQSOSCAuto] RK0, (LSB)MR18= 0x1e2b, (MSB)MR19= 0x808, tDQSOscB0 = 401 ps tDQSOscB1 = 404 ps
4665 22:16:45.788227 CH1 RK0: MR19=808, MR18=1E2B
4666 22:16:45.794684 CH1_RK0: MR19=0x808, MR18=0x1E2B, DQSOSC=401, MR23=63, INC=163, DEC=108
4667 22:16:45.794770
4668 22:16:45.798110 ----->DramcWriteLeveling(PI) begin...
4669 22:16:45.798194 ==
4670 22:16:45.801848 Dram Type= 6, Freq= 0, CH_1, rank 1
4671 22:16:45.805081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4672 22:16:45.805165 ==
4673 22:16:45.808094 Write leveling (Byte 0): 31 => 31
4674 22:16:45.811337 Write leveling (Byte 1): 31 => 31
4675 22:16:45.814547 DramcWriteLeveling(PI) end<-----
4676 22:16:45.814630
4677 22:16:45.814696 ==
4678 22:16:45.818220 Dram Type= 6, Freq= 0, CH_1, rank 1
4679 22:16:45.821041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4680 22:16:45.821124 ==
4681 22:16:45.824655 [Gating] SW mode calibration
4682 22:16:45.830875 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4683 22:16:45.837394 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4684 22:16:45.841038 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4685 22:16:45.868289 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4686 22:16:45.868377 0 9 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
4687 22:16:45.868474 0 9 12 | B1->B0 | 3232 2f2f | 1 0 | (1 1) (0 0)
4688 22:16:45.868578 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4689 22:16:45.868651 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4690 22:16:45.868717 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4691 22:16:45.870896 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4692 22:16:45.877156 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4693 22:16:45.880834 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4694 22:16:45.883969 0 10 8 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
4695 22:16:45.891047 0 10 12 | B1->B0 | 3030 4140 | 0 1 | (1 1) (0 0)
4696 22:16:45.893758 0 10 16 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
4697 22:16:45.897531 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4698 22:16:45.903883 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4699 22:16:45.907245 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4700 22:16:45.910632 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4701 22:16:45.917176 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4702 22:16:45.920418 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4703 22:16:45.923538 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4704 22:16:45.930149 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 22:16:45.933187 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4706 22:16:45.936423 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4707 22:16:45.943125 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4708 22:16:45.946603 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4709 22:16:45.949856 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4710 22:16:45.956173 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4711 22:16:45.959711 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4712 22:16:45.963089 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4713 22:16:45.969452 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4714 22:16:45.973024 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4715 22:16:45.979354 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4716 22:16:45.982805 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4717 22:16:45.986138 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4718 22:16:45.992802 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4719 22:16:45.996206 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4720 22:16:45.999243 Total UI for P1: 0, mck2ui 16
4721 22:16:46.002724 best dqsien dly found for B0: ( 0, 13, 10)
4722 22:16:46.005735 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4723 22:16:46.009203 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4724 22:16:46.012609 Total UI for P1: 0, mck2ui 16
4725 22:16:46.016243 best dqsien dly found for B1: ( 0, 13, 14)
4726 22:16:46.022252 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4727 22:16:46.025804 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4728 22:16:46.025887
4729 22:16:46.028612 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4730 22:16:46.032258 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4731 22:16:46.035728 [Gating] SW calibration Done
4732 22:16:46.035810 ==
4733 22:16:46.038785 Dram Type= 6, Freq= 0, CH_1, rank 1
4734 22:16:46.041918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4735 22:16:46.042002 ==
4736 22:16:46.045565 RX Vref Scan: 0
4737 22:16:46.045648
4738 22:16:46.045713 RX Vref 0 -> 0, step: 1
4739 22:16:46.045773
4740 22:16:46.048812 RX Delay -230 -> 252, step: 16
4741 22:16:46.055467 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4742 22:16:46.058572 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4743 22:16:46.061631 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4744 22:16:46.065329 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4745 22:16:46.068602 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4746 22:16:46.075536 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4747 22:16:46.078428 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4748 22:16:46.081911 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4749 22:16:46.085031 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4750 22:16:46.092000 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4751 22:16:46.094795 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4752 22:16:46.098240 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4753 22:16:46.101431 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4754 22:16:46.107854 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4755 22:16:46.111382 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4756 22:16:46.114821 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4757 22:16:46.114903 ==
4758 22:16:46.117763 Dram Type= 6, Freq= 0, CH_1, rank 1
4759 22:16:46.121089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4760 22:16:46.124868 ==
4761 22:16:46.124950 DQS Delay:
4762 22:16:46.125015 DQS0 = 0, DQS1 = 0
4763 22:16:46.127740 DQM Delay:
4764 22:16:46.127822 DQM0 = 36, DQM1 = 30
4765 22:16:46.131117 DQ Delay:
4766 22:16:46.131199 DQ0 =41, DQ1 =33, DQ2 =17, DQ3 =33
4767 22:16:46.134261 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4768 22:16:46.137564 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4769 22:16:46.141399 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =33
4770 22:16:46.141482
4771 22:16:46.144360
4772 22:16:46.144442 ==
4773 22:16:46.147678 Dram Type= 6, Freq= 0, CH_1, rank 1
4774 22:16:46.150730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4775 22:16:46.150813 ==
4776 22:16:46.150879
4777 22:16:46.150938
4778 22:16:46.154362 TX Vref Scan disable
4779 22:16:46.154445 == TX Byte 0 ==
4780 22:16:46.160502 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4781 22:16:46.164281 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4782 22:16:46.164364 == TX Byte 1 ==
4783 22:16:46.171130 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4784 22:16:46.174281 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4785 22:16:46.174363 ==
4786 22:16:46.177094 Dram Type= 6, Freq= 0, CH_1, rank 1
4787 22:16:46.180477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4788 22:16:46.180560 ==
4789 22:16:46.180625
4790 22:16:46.183955
4791 22:16:46.184036 TX Vref Scan disable
4792 22:16:46.187293 == TX Byte 0 ==
4793 22:16:46.190375 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4794 22:16:46.196847 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4795 22:16:46.196931 == TX Byte 1 ==
4796 22:16:46.200212 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4797 22:16:46.206631 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4798 22:16:46.206714
4799 22:16:46.206780 [DATLAT]
4800 22:16:46.206841 Freq=600, CH1 RK1
4801 22:16:46.206900
4802 22:16:46.210221 DATLAT Default: 0x9
4803 22:16:46.210303 0, 0xFFFF, sum = 0
4804 22:16:46.213634 1, 0xFFFF, sum = 0
4805 22:16:46.216652 2, 0xFFFF, sum = 0
4806 22:16:46.216735 3, 0xFFFF, sum = 0
4807 22:16:46.219988 4, 0xFFFF, sum = 0
4808 22:16:46.220072 5, 0xFFFF, sum = 0
4809 22:16:46.223575 6, 0xFFFF, sum = 0
4810 22:16:46.223681 7, 0xFFFF, sum = 0
4811 22:16:46.226609 8, 0x0, sum = 1
4812 22:16:46.226693 9, 0x0, sum = 2
4813 22:16:46.229886 10, 0x0, sum = 3
4814 22:16:46.229969 11, 0x0, sum = 4
4815 22:16:46.230036 best_step = 9
4816 22:16:46.230095
4817 22:16:46.233311 ==
4818 22:16:46.236405 Dram Type= 6, Freq= 0, CH_1, rank 1
4819 22:16:46.239973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4820 22:16:46.240073 ==
4821 22:16:46.240139 RX Vref Scan: 0
4822 22:16:46.240199
4823 22:16:46.243171 RX Vref 0 -> 0, step: 1
4824 22:16:46.243253
4825 22:16:46.246405 RX Delay -195 -> 252, step: 8
4826 22:16:46.252643 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4827 22:16:46.256132 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4828 22:16:46.259411 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4829 22:16:46.262598 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4830 22:16:46.269148 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4831 22:16:46.272434 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4832 22:16:46.275831 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4833 22:16:46.279046 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4834 22:16:46.282455 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4835 22:16:46.289377 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4836 22:16:46.292141 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4837 22:16:46.296210 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4838 22:16:46.299728 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4839 22:16:46.306121 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4840 22:16:46.309125 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4841 22:16:46.312676 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4842 22:16:46.313148 ==
4843 22:16:46.315723 Dram Type= 6, Freq= 0, CH_1, rank 1
4844 22:16:46.319266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4845 22:16:46.322474 ==
4846 22:16:46.323063 DQS Delay:
4847 22:16:46.323529 DQS0 = 0, DQS1 = 0
4848 22:16:46.325884 DQM Delay:
4849 22:16:46.326563 DQM0 = 36, DQM1 = 30
4850 22:16:46.328954 DQ Delay:
4851 22:16:46.332483 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4852 22:16:46.332956 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =32
4853 22:16:46.335958 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =20
4854 22:16:46.342583 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4855 22:16:46.343010
4856 22:16:46.343348
4857 22:16:46.348957 [DQSOSCAuto] RK1, (LSB)MR18= 0x3556, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 399 ps
4858 22:16:46.351886 CH1 RK1: MR19=808, MR18=3556
4859 22:16:46.358897 CH1_RK1: MR19=0x808, MR18=0x3556, DQSOSC=393, MR23=63, INC=169, DEC=113
4860 22:16:46.362206 [RxdqsGatingPostProcess] freq 600
4861 22:16:46.365313 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4862 22:16:46.368461 Pre-setting of DQS Precalculation
4863 22:16:46.375044 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4864 22:16:46.381805 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4865 22:16:46.388472 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4866 22:16:46.388909
4867 22:16:46.389350
4868 22:16:46.391651 [Calibration Summary] 1200 Mbps
4869 22:16:46.392083 CH 0, Rank 0
4870 22:16:46.395066 SW Impedance : PASS
4871 22:16:46.398056 DUTY Scan : NO K
4872 22:16:46.398491 ZQ Calibration : PASS
4873 22:16:46.401606 Jitter Meter : NO K
4874 22:16:46.404609 CBT Training : PASS
4875 22:16:46.405033 Write leveling : PASS
4876 22:16:46.407959 RX DQS gating : PASS
4877 22:16:46.411137 RX DQ/DQS(RDDQC) : PASS
4878 22:16:46.411559 TX DQ/DQS : PASS
4879 22:16:46.414552 RX DATLAT : PASS
4880 22:16:46.418108 RX DQ/DQS(Engine): PASS
4881 22:16:46.418528 TX OE : NO K
4882 22:16:46.421088 All Pass.
4883 22:16:46.421511
4884 22:16:46.421844 CH 0, Rank 1
4885 22:16:46.424696 SW Impedance : PASS
4886 22:16:46.425156 DUTY Scan : NO K
4887 22:16:46.427958 ZQ Calibration : PASS
4888 22:16:46.430915 Jitter Meter : NO K
4889 22:16:46.431336 CBT Training : PASS
4890 22:16:46.434419 Write leveling : PASS
4891 22:16:46.437932 RX DQS gating : PASS
4892 22:16:46.438401 RX DQ/DQS(RDDQC) : PASS
4893 22:16:46.440849 TX DQ/DQS : PASS
4894 22:16:46.444133 RX DATLAT : PASS
4895 22:16:46.444602 RX DQ/DQS(Engine): PASS
4896 22:16:46.447330 TX OE : NO K
4897 22:16:46.447799 All Pass.
4898 22:16:46.448181
4899 22:16:46.450826 CH 1, Rank 0
4900 22:16:46.451413 SW Impedance : PASS
4901 22:16:46.454123 DUTY Scan : NO K
4902 22:16:46.457332 ZQ Calibration : PASS
4903 22:16:46.457834 Jitter Meter : NO K
4904 22:16:46.460740 CBT Training : PASS
4905 22:16:46.464062 Write leveling : PASS
4906 22:16:46.464584 RX DQS gating : PASS
4907 22:16:46.466922 RX DQ/DQS(RDDQC) : PASS
4908 22:16:46.470171 TX DQ/DQS : PASS
4909 22:16:46.470620 RX DATLAT : PASS
4910 22:16:46.473630 RX DQ/DQS(Engine): PASS
4911 22:16:46.476920 TX OE : NO K
4912 22:16:46.477377 All Pass.
4913 22:16:46.477819
4914 22:16:46.478194 CH 1, Rank 1
4915 22:16:46.480250 SW Impedance : PASS
4916 22:16:46.483830 DUTY Scan : NO K
4917 22:16:46.484385 ZQ Calibration : PASS
4918 22:16:46.486956 Jitter Meter : NO K
4919 22:16:46.490094 CBT Training : PASS
4920 22:16:46.490571 Write leveling : PASS
4921 22:16:46.493248 RX DQS gating : PASS
4922 22:16:46.493778 RX DQ/DQS(RDDQC) : PASS
4923 22:16:46.496524 TX DQ/DQS : PASS
4924 22:16:46.499750 RX DATLAT : PASS
4925 22:16:46.500276 RX DQ/DQS(Engine): PASS
4926 22:16:46.503158 TX OE : NO K
4927 22:16:46.503856 All Pass.
4928 22:16:46.504295
4929 22:16:46.506526 DramC Write-DBI off
4930 22:16:46.510102 PER_BANK_REFRESH: Hybrid Mode
4931 22:16:46.510580 TX_TRACKING: ON
4932 22:16:46.519981 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4933 22:16:46.522991 [FAST_K] Save calibration result to emmc
4934 22:16:46.526444 dramc_set_vcore_voltage set vcore to 662500
4935 22:16:46.529577 Read voltage for 933, 3
4936 22:16:46.530094 Vio18 = 0
4937 22:16:46.532522 Vcore = 662500
4938 22:16:46.532850 Vdram = 0
4939 22:16:46.533162 Vddq = 0
4940 22:16:46.533418 Vmddr = 0
4941 22:16:46.539061 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4942 22:16:46.545873 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4943 22:16:46.546072 MEM_TYPE=3, freq_sel=17
4944 22:16:46.549361 sv_algorithm_assistance_LP4_1600
4945 22:16:46.552371 ============ PULL DRAM RESETB DOWN ============
4946 22:16:46.558968 ========== PULL DRAM RESETB DOWN end =========
4947 22:16:46.562293 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4948 22:16:46.565675 ===================================
4949 22:16:46.569249 LPDDR4 DRAM CONFIGURATION
4950 22:16:46.571804 ===================================
4951 22:16:46.572071 EX_ROW_EN[0] = 0x0
4952 22:16:46.575406 EX_ROW_EN[1] = 0x0
4953 22:16:46.578506 LP4Y_EN = 0x0
4954 22:16:46.578720 WORK_FSP = 0x0
4955 22:16:46.581734 WL = 0x3
4956 22:16:46.582044 RL = 0x3
4957 22:16:46.584962 BL = 0x2
4958 22:16:46.585301 RPST = 0x0
4959 22:16:46.588492 RD_PRE = 0x0
4960 22:16:46.588922 WR_PRE = 0x1
4961 22:16:46.591990 WR_PST = 0x0
4962 22:16:46.592611 DBI_WR = 0x0
4963 22:16:46.595415 DBI_RD = 0x0
4964 22:16:46.596078 OTF = 0x1
4965 22:16:46.598271 ===================================
4966 22:16:46.601493 ===================================
4967 22:16:46.605328 ANA top config
4968 22:16:46.608148 ===================================
4969 22:16:46.611313 DLL_ASYNC_EN = 0
4970 22:16:46.611802 ALL_SLAVE_EN = 1
4971 22:16:46.614919 NEW_RANK_MODE = 1
4972 22:16:46.618131 DLL_IDLE_MODE = 1
4973 22:16:46.621087 LP45_APHY_COMB_EN = 1
4974 22:16:46.621516 TX_ODT_DIS = 1
4975 22:16:46.624807 NEW_8X_MODE = 1
4976 22:16:46.627654 ===================================
4977 22:16:46.631006 ===================================
4978 22:16:46.634536 data_rate = 1866
4979 22:16:46.638014 CKR = 1
4980 22:16:46.641089 DQ_P2S_RATIO = 8
4981 22:16:46.644512 ===================================
4982 22:16:46.648236 CA_P2S_RATIO = 8
4983 22:16:46.648659 DQ_CA_OPEN = 0
4984 22:16:46.650745 DQ_SEMI_OPEN = 0
4985 22:16:46.654450 CA_SEMI_OPEN = 0
4986 22:16:46.657523 CA_FULL_RATE = 0
4987 22:16:46.660950 DQ_CKDIV4_EN = 1
4988 22:16:46.664356 CA_CKDIV4_EN = 1
4989 22:16:46.664783 CA_PREDIV_EN = 0
4990 22:16:46.667330 PH8_DLY = 0
4991 22:16:46.670651 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4992 22:16:46.674170 DQ_AAMCK_DIV = 4
4993 22:16:46.677460 CA_AAMCK_DIV = 4
4994 22:16:46.680776 CA_ADMCK_DIV = 4
4995 22:16:46.681203 DQ_TRACK_CA_EN = 0
4996 22:16:46.684007 CA_PICK = 933
4997 22:16:46.687616 CA_MCKIO = 933
4998 22:16:46.690455 MCKIO_SEMI = 0
4999 22:16:46.694402 PLL_FREQ = 3732
5000 22:16:46.697355 DQ_UI_PI_RATIO = 32
5001 22:16:46.700731 CA_UI_PI_RATIO = 0
5002 22:16:46.704332 ===================================
5003 22:16:46.707058 ===================================
5004 22:16:46.707484 memory_type:LPDDR4
5005 22:16:46.710524 GP_NUM : 10
5006 22:16:46.713591 SRAM_EN : 1
5007 22:16:46.714017 MD32_EN : 0
5008 22:16:46.716902 ===================================
5009 22:16:46.720596 [ANA_INIT] >>>>>>>>>>>>>>
5010 22:16:46.723531 <<<<<< [CONFIGURE PHASE]: ANA_TX
5011 22:16:46.727087 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5012 22:16:46.730110 ===================================
5013 22:16:46.733592 data_rate = 1866,PCW = 0X8f00
5014 22:16:46.736958 ===================================
5015 22:16:46.740117 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5016 22:16:46.743320 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5017 22:16:46.750338 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5018 22:16:46.756548 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5019 22:16:46.760057 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5020 22:16:46.763521 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5021 22:16:46.764007 [ANA_INIT] flow start
5022 22:16:46.766429 [ANA_INIT] PLL >>>>>>>>
5023 22:16:46.769946 [ANA_INIT] PLL <<<<<<<<
5024 22:16:46.770366 [ANA_INIT] MIDPI >>>>>>>>
5025 22:16:46.772933 [ANA_INIT] MIDPI <<<<<<<<
5026 22:16:46.776364 [ANA_INIT] DLL >>>>>>>>
5027 22:16:46.776785 [ANA_INIT] flow end
5028 22:16:46.783218 ============ LP4 DIFF to SE enter ============
5029 22:16:46.786121 ============ LP4 DIFF to SE exit ============
5030 22:16:46.789644 [ANA_INIT] <<<<<<<<<<<<<
5031 22:16:46.792860 [Flow] Enable top DCM control >>>>>
5032 22:16:46.793287 [Flow] Enable top DCM control <<<<<
5033 22:16:46.796131 Enable DLL master slave shuffle
5034 22:16:46.802968 ==============================================================
5035 22:16:46.806249 Gating Mode config
5036 22:16:46.809255 ==============================================================
5037 22:16:46.812640 Config description:
5038 22:16:46.822981 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5039 22:16:46.829007 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5040 22:16:46.832571 SELPH_MODE 0: By rank 1: By Phase
5041 22:16:46.838853 ==============================================================
5042 22:16:46.842486 GAT_TRACK_EN = 1
5043 22:16:46.845785 RX_GATING_MODE = 2
5044 22:16:46.849206 RX_GATING_TRACK_MODE = 2
5045 22:16:46.852128 SELPH_MODE = 1
5046 22:16:46.855659 PICG_EARLY_EN = 1
5047 22:16:46.855885 VALID_LAT_VALUE = 1
5048 22:16:46.862359 ==============================================================
5049 22:16:46.865305 Enter into Gating configuration >>>>
5050 22:16:46.868317 Exit from Gating configuration <<<<
5051 22:16:46.871613 Enter into DVFS_PRE_config >>>>>
5052 22:16:46.881636 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5053 22:16:46.884930 Exit from DVFS_PRE_config <<<<<
5054 22:16:46.888241 Enter into PICG configuration >>>>
5055 22:16:46.891280 Exit from PICG configuration <<<<
5056 22:16:46.894912 [RX_INPUT] configuration >>>>>
5057 22:16:46.898318 [RX_INPUT] configuration <<<<<
5058 22:16:46.904833 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5059 22:16:46.908137 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5060 22:16:46.914622 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5061 22:16:46.921173 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5062 22:16:46.927479 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5063 22:16:46.934371 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5064 22:16:46.937237 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5065 22:16:46.940661 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5066 22:16:46.944354 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5067 22:16:46.950704 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5068 22:16:46.954218 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5069 22:16:46.957298 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5070 22:16:46.960545 ===================================
5071 22:16:46.963600 LPDDR4 DRAM CONFIGURATION
5072 22:16:46.967028 ===================================
5073 22:16:46.970402 EX_ROW_EN[0] = 0x0
5074 22:16:46.970484 EX_ROW_EN[1] = 0x0
5075 22:16:46.973354 LP4Y_EN = 0x0
5076 22:16:46.973435 WORK_FSP = 0x0
5077 22:16:46.976672 WL = 0x3
5078 22:16:46.976753 RL = 0x3
5079 22:16:46.980893 BL = 0x2
5080 22:16:46.980974 RPST = 0x0
5081 22:16:46.983893 RD_PRE = 0x0
5082 22:16:46.983975 WR_PRE = 0x1
5083 22:16:46.986836 WR_PST = 0x0
5084 22:16:46.986917 DBI_WR = 0x0
5085 22:16:46.990386 DBI_RD = 0x0
5086 22:16:46.993731 OTF = 0x1
5087 22:16:46.997217 ===================================
5088 22:16:47.000373 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5089 22:16:47.003109 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5090 22:16:47.006898 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5091 22:16:47.009782 ===================================
5092 22:16:47.012977 LPDDR4 DRAM CONFIGURATION
5093 22:16:47.016320 ===================================
5094 22:16:47.019681 EX_ROW_EN[0] = 0x10
5095 22:16:47.019767 EX_ROW_EN[1] = 0x0
5096 22:16:47.023245 LP4Y_EN = 0x0
5097 22:16:47.023326 WORK_FSP = 0x0
5098 22:16:47.026324 WL = 0x3
5099 22:16:47.026405 RL = 0x3
5100 22:16:47.029611 BL = 0x2
5101 22:16:47.029692 RPST = 0x0
5102 22:16:47.033127 RD_PRE = 0x0
5103 22:16:47.033208 WR_PRE = 0x1
5104 22:16:47.036192 WR_PST = 0x0
5105 22:16:47.036274 DBI_WR = 0x0
5106 22:16:47.039355 DBI_RD = 0x0
5107 22:16:47.042833 OTF = 0x1
5108 22:16:47.046405 ===================================
5109 22:16:47.049252 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5110 22:16:47.054329 nWR fixed to 30
5111 22:16:47.058210 [ModeRegInit_LP4] CH0 RK0
5112 22:16:47.058292 [ModeRegInit_LP4] CH0 RK1
5113 22:16:47.061424 [ModeRegInit_LP4] CH1 RK0
5114 22:16:47.064890 [ModeRegInit_LP4] CH1 RK1
5115 22:16:47.064971 match AC timing 9
5116 22:16:47.071367 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5117 22:16:47.074240 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5118 22:16:47.077914 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5119 22:16:47.084072 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5120 22:16:47.087494 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5121 22:16:47.087636 ==
5122 22:16:47.090984 Dram Type= 6, Freq= 0, CH_0, rank 0
5123 22:16:47.094402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5124 22:16:47.094485 ==
5125 22:16:47.101102 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5126 22:16:47.107551 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5127 22:16:47.110830 [CA 0] Center 38 (8~69) winsize 62
5128 22:16:47.114195 [CA 1] Center 38 (7~69) winsize 63
5129 22:16:47.117294 [CA 2] Center 36 (6~66) winsize 61
5130 22:16:47.120690 [CA 3] Center 35 (4~66) winsize 63
5131 22:16:47.124161 [CA 4] Center 34 (4~65) winsize 62
5132 22:16:47.127059 [CA 5] Center 34 (4~64) winsize 61
5133 22:16:47.127141
5134 22:16:47.130476 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5135 22:16:47.130560
5136 22:16:47.134071 [CATrainingPosCal] consider 1 rank data
5137 22:16:47.137139 u2DelayCellTimex100 = 270/100 ps
5138 22:16:47.140537 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5139 22:16:47.143993 CA1 delay=38 (7~69),Diff = 4 PI (24 cell)
5140 22:16:47.146637 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5141 22:16:47.153871 CA3 delay=35 (4~66),Diff = 1 PI (6 cell)
5142 22:16:47.156785 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5143 22:16:47.160138 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5144 22:16:47.160220
5145 22:16:47.163257 CA PerBit enable=1, Macro0, CA PI delay=34
5146 22:16:47.163339
5147 22:16:47.166732 [CBTSetCACLKResult] CA Dly = 34
5148 22:16:47.166813 CS Dly: 7 (0~38)
5149 22:16:47.166878 ==
5150 22:16:47.170078 Dram Type= 6, Freq= 0, CH_0, rank 1
5151 22:16:47.176296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5152 22:16:47.176378 ==
5153 22:16:47.179853 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5154 22:16:47.186278 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5155 22:16:47.189899 [CA 0] Center 38 (8~69) winsize 62
5156 22:16:47.192787 [CA 1] Center 38 (8~69) winsize 62
5157 22:16:47.196551 [CA 2] Center 35 (5~66) winsize 62
5158 22:16:47.199300 [CA 3] Center 35 (5~66) winsize 62
5159 22:16:47.203192 [CA 4] Center 34 (4~65) winsize 62
5160 22:16:47.206466 [CA 5] Center 34 (4~64) winsize 61
5161 22:16:47.206548
5162 22:16:47.209241 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5163 22:16:47.209323
5164 22:16:47.212945 [CATrainingPosCal] consider 2 rank data
5165 22:16:47.216187 u2DelayCellTimex100 = 270/100 ps
5166 22:16:47.219087 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5167 22:16:47.226023 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5168 22:16:47.229401 CA2 delay=36 (6~66),Diff = 2 PI (12 cell)
5169 22:16:47.232797 CA3 delay=35 (5~66),Diff = 1 PI (6 cell)
5170 22:16:47.235783 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5171 22:16:47.239177 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5172 22:16:47.239259
5173 22:16:47.242829 CA PerBit enable=1, Macro0, CA PI delay=34
5174 22:16:47.242910
5175 22:16:47.245620 [CBTSetCACLKResult] CA Dly = 34
5176 22:16:47.248791 CS Dly: 7 (0~39)
5177 22:16:47.248873
5178 22:16:47.252238 ----->DramcWriteLeveling(PI) begin...
5179 22:16:47.252321 ==
5180 22:16:47.255627 Dram Type= 6, Freq= 0, CH_0, rank 0
5181 22:16:47.259031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5182 22:16:47.259113 ==
5183 22:16:47.262150 Write leveling (Byte 0): 33 => 33
5184 22:16:47.265252 Write leveling (Byte 1): 32 => 32
5185 22:16:47.268547 DramcWriteLeveling(PI) end<-----
5186 22:16:47.268628
5187 22:16:47.268693 ==
5188 22:16:47.271736 Dram Type= 6, Freq= 0, CH_0, rank 0
5189 22:16:47.275478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5190 22:16:47.275633 ==
5191 22:16:47.278591 [Gating] SW mode calibration
5192 22:16:47.285043 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5193 22:16:47.291620 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5194 22:16:47.295093 0 14 0 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
5195 22:16:47.301659 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5196 22:16:47.305158 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5197 22:16:47.308322 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5198 22:16:47.314683 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5199 22:16:47.317938 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5200 22:16:47.321456 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5201 22:16:47.327917 0 14 28 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
5202 22:16:47.331172 0 15 0 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 0)
5203 22:16:47.334702 0 15 4 | B1->B0 | 2828 2323 | 0 0 | (1 0) (0 0)
5204 22:16:47.341118 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5205 22:16:47.344991 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5206 22:16:47.347997 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5207 22:16:47.354364 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5208 22:16:47.357885 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5209 22:16:47.360769 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5210 22:16:47.367643 1 0 0 | B1->B0 | 2929 3939 | 0 0 | (0 0) (1 1)
5211 22:16:47.370611 1 0 4 | B1->B0 | 4444 4646 | 1 0 | (0 0) (0 0)
5212 22:16:47.374267 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5213 22:16:47.380531 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5214 22:16:47.384302 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5215 22:16:47.387086 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5216 22:16:47.393798 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5217 22:16:47.397418 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5218 22:16:47.400829 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5219 22:16:47.407562 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5220 22:16:47.410613 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5221 22:16:47.414178 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5222 22:16:47.420523 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5223 22:16:47.423874 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5224 22:16:47.427132 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5225 22:16:47.433828 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5226 22:16:47.436962 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5227 22:16:47.440126 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5228 22:16:47.447052 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5229 22:16:47.449943 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5230 22:16:47.453270 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5231 22:16:47.460320 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5232 22:16:47.463197 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5233 22:16:47.466852 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5234 22:16:47.472926 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5235 22:16:47.476174 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5236 22:16:47.479879 Total UI for P1: 0, mck2ui 16
5237 22:16:47.482729 best dqsien dly found for B0: ( 1, 2, 30)
5238 22:16:47.486268 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5239 22:16:47.489650 Total UI for P1: 0, mck2ui 16
5240 22:16:47.493155 best dqsien dly found for B1: ( 1, 3, 4)
5241 22:16:47.496070 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5242 22:16:47.499420 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5243 22:16:47.499619
5244 22:16:47.502544 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5245 22:16:47.509378 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5246 22:16:47.509573 [Gating] SW calibration Done
5247 22:16:47.509735 ==
5248 22:16:47.512396 Dram Type= 6, Freq= 0, CH_0, rank 0
5249 22:16:47.519356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5250 22:16:47.519545 ==
5251 22:16:47.519737 RX Vref Scan: 0
5252 22:16:47.519876
5253 22:16:47.522401 RX Vref 0 -> 0, step: 1
5254 22:16:47.522577
5255 22:16:47.525777 RX Delay -80 -> 252, step: 8
5256 22:16:47.528985 iDelay=208, Bit 0, Center 99 (8 ~ 191) 184
5257 22:16:47.532400 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5258 22:16:47.535715 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5259 22:16:47.542394 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5260 22:16:47.545585 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5261 22:16:47.548733 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5262 22:16:47.552419 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5263 22:16:47.555430 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5264 22:16:47.559057 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5265 22:16:47.565310 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5266 22:16:47.568817 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5267 22:16:47.571571 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5268 22:16:47.574857 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5269 22:16:47.581485 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5270 22:16:47.585388 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5271 22:16:47.588099 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5272 22:16:47.588666 ==
5273 22:16:47.591936 Dram Type= 6, Freq= 0, CH_0, rank 0
5274 22:16:47.594985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5275 22:16:47.595383 ==
5276 22:16:47.597884 DQS Delay:
5277 22:16:47.598279 DQS0 = 0, DQS1 = 0
5278 22:16:47.601434 DQM Delay:
5279 22:16:47.601812 DQM0 = 96, DQM1 = 84
5280 22:16:47.602137 DQ Delay:
5281 22:16:47.604691 DQ0 =99, DQ1 =95, DQ2 =95, DQ3 =91
5282 22:16:47.607765 DQ4 =99, DQ5 =79, DQ6 =103, DQ7 =107
5283 22:16:47.611395 DQ8 =79, DQ9 =71, DQ10 =83, DQ11 =79
5284 22:16:47.614494 DQ12 =91, DQ13 =87, DQ14 =91, DQ15 =91
5285 22:16:47.614845
5286 22:16:47.615144
5287 22:16:47.617567 ==
5288 22:16:47.620949 Dram Type= 6, Freq= 0, CH_0, rank 0
5289 22:16:47.624641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5290 22:16:47.624995 ==
5291 22:16:47.625248
5292 22:16:47.625486
5293 22:16:47.627864 TX Vref Scan disable
5294 22:16:47.628184 == TX Byte 0 ==
5295 22:16:47.634616 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5296 22:16:47.637754 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5297 22:16:47.638296 == TX Byte 1 ==
5298 22:16:47.644329 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5299 22:16:47.647817 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5300 22:16:47.648368 ==
5301 22:16:47.651052 Dram Type= 6, Freq= 0, CH_0, rank 0
5302 22:16:47.653794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5303 22:16:47.654296 ==
5304 22:16:47.654756
5305 22:16:47.655196
5306 22:16:47.657068 TX Vref Scan disable
5307 22:16:47.660542 == TX Byte 0 ==
5308 22:16:47.664045 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5309 22:16:47.666908 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5310 22:16:47.670513 == TX Byte 1 ==
5311 22:16:47.673833 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5312 22:16:47.677006 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5313 22:16:47.677484
5314 22:16:47.680392 [DATLAT]
5315 22:16:47.680728 Freq=933, CH0 RK0
5316 22:16:47.680985
5317 22:16:47.683567 DATLAT Default: 0xd
5318 22:16:47.683918 0, 0xFFFF, sum = 0
5319 22:16:47.687010 1, 0xFFFF, sum = 0
5320 22:16:47.687337 2, 0xFFFF, sum = 0
5321 22:16:47.690489 3, 0xFFFF, sum = 0
5322 22:16:47.690815 4, 0xFFFF, sum = 0
5323 22:16:47.693918 5, 0xFFFF, sum = 0
5324 22:16:47.697106 6, 0xFFFF, sum = 0
5325 22:16:47.697437 7, 0xFFFF, sum = 0
5326 22:16:47.699884 8, 0xFFFF, sum = 0
5327 22:16:47.700209 9, 0xFFFF, sum = 0
5328 22:16:47.703500 10, 0x0, sum = 1
5329 22:16:47.703857 11, 0x0, sum = 2
5330 22:16:47.706407 12, 0x0, sum = 3
5331 22:16:47.706733 13, 0x0, sum = 4
5332 22:16:47.706990 best_step = 11
5333 22:16:47.707230
5334 22:16:47.710003 ==
5335 22:16:47.713033 Dram Type= 6, Freq= 0, CH_0, rank 0
5336 22:16:47.716707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5337 22:16:47.717034 ==
5338 22:16:47.717293 RX Vref Scan: 1
5339 22:16:47.717537
5340 22:16:47.719576 RX Vref 0 -> 0, step: 1
5341 22:16:47.719953
5342 22:16:47.723041 RX Delay -69 -> 252, step: 4
5343 22:16:47.723367
5344 22:16:47.726527 Set Vref, RX VrefLevel [Byte0]: 61
5345 22:16:47.730067 [Byte1]: 56
5346 22:16:47.730411
5347 22:16:47.732837 Final RX Vref Byte 0 = 61 to rank0
5348 22:16:47.736437 Final RX Vref Byte 1 = 56 to rank0
5349 22:16:47.739695 Final RX Vref Byte 0 = 61 to rank1
5350 22:16:47.742927 Final RX Vref Byte 1 = 56 to rank1==
5351 22:16:47.745934 Dram Type= 6, Freq= 0, CH_0, rank 0
5352 22:16:47.752744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5353 22:16:47.753082 ==
5354 22:16:47.753346 DQS Delay:
5355 22:16:47.753590 DQS0 = 0, DQS1 = 0
5356 22:16:47.755979 DQM Delay:
5357 22:16:47.756310 DQM0 = 95, DQM1 = 83
5358 22:16:47.759456 DQ Delay:
5359 22:16:47.762579 DQ0 =92, DQ1 =98, DQ2 =92, DQ3 =92
5360 22:16:47.766003 DQ4 =96, DQ5 =84, DQ6 =104, DQ7 =108
5361 22:16:47.769366 DQ8 =78, DQ9 =70, DQ10 =82, DQ11 =80
5362 22:16:47.772125 DQ12 =86, DQ13 =86, DQ14 =92, DQ15 =90
5363 22:16:47.772445
5364 22:16:47.772699
5365 22:16:47.779376 [DQSOSCAuto] RK0, (LSB)MR18= 0x1212, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 416 ps
5366 22:16:47.782412 CH0 RK0: MR19=505, MR18=1212
5367 22:16:47.789117 CH0_RK0: MR19=0x505, MR18=0x1212, DQSOSC=416, MR23=63, INC=62, DEC=41
5368 22:16:47.789450
5369 22:16:47.791774 ----->DramcWriteLeveling(PI) begin...
5370 22:16:47.792098 ==
5371 22:16:47.795247 Dram Type= 6, Freq= 0, CH_0, rank 1
5372 22:16:47.798737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5373 22:16:47.799060 ==
5374 22:16:47.802114 Write leveling (Byte 0): 31 => 31
5375 22:16:47.805175 Write leveling (Byte 1): 30 => 30
5376 22:16:47.808331 DramcWriteLeveling(PI) end<-----
5377 22:16:47.808652
5378 22:16:47.808908 ==
5379 22:16:47.811985 Dram Type= 6, Freq= 0, CH_0, rank 1
5380 22:16:47.815124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5381 22:16:47.818257 ==
5382 22:16:47.818578 [Gating] SW mode calibration
5383 22:16:47.828333 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5384 22:16:47.831637 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5385 22:16:47.835038 0 14 0 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
5386 22:16:47.841493 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5387 22:16:47.844853 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5388 22:16:47.847975 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5389 22:16:47.854284 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5390 22:16:47.857686 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5391 22:16:47.864299 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5392 22:16:47.867542 0 14 28 | B1->B0 | 3131 2727 | 1 0 | (1 1) (1 0)
5393 22:16:47.870664 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
5394 22:16:47.877329 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5395 22:16:47.880941 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5396 22:16:47.884346 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5397 22:16:47.890350 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5398 22:16:47.893718 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5399 22:16:47.897169 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5400 22:16:47.903870 0 15 28 | B1->B0 | 2828 3737 | 0 0 | (0 0) (0 0)
5401 22:16:47.906797 1 0 0 | B1->B0 | 3535 4646 | 1 0 | (0 0) (0 0)
5402 22:16:47.910158 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5403 22:16:47.916807 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5404 22:16:47.920407 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5405 22:16:47.923426 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5406 22:16:47.930105 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5407 22:16:47.933146 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5408 22:16:47.936627 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5409 22:16:47.943378 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5410 22:16:47.946710 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5411 22:16:47.949923 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5412 22:16:47.956687 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5413 22:16:47.959760 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5414 22:16:47.962981 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5415 22:16:47.969721 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5416 22:16:47.973002 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5417 22:16:47.976457 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5418 22:16:47.983091 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5419 22:16:47.985964 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5420 22:16:47.989647 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5421 22:16:47.995928 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5422 22:16:47.999304 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5423 22:16:48.002309 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5424 22:16:48.009293 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5425 22:16:48.009439 Total UI for P1: 0, mck2ui 16
5426 22:16:48.012690 best dqsien dly found for B0: ( 1, 2, 26)
5427 22:16:48.018972 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5428 22:16:48.022409 Total UI for P1: 0, mck2ui 16
5429 22:16:48.025734 best dqsien dly found for B1: ( 1, 2, 28)
5430 22:16:48.028691 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5431 22:16:48.032100 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5432 22:16:48.032242
5433 22:16:48.035475 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5434 22:16:48.038735 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5435 22:16:48.042215 [Gating] SW calibration Done
5436 22:16:48.042401 ==
5437 22:16:48.045351 Dram Type= 6, Freq= 0, CH_0, rank 1
5438 22:16:48.048335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5439 22:16:48.051821 ==
5440 22:16:48.052009 RX Vref Scan: 0
5441 22:16:48.052177
5442 22:16:48.055211 RX Vref 0 -> 0, step: 1
5443 22:16:48.055357
5444 22:16:48.055472 RX Delay -80 -> 252, step: 8
5445 22:16:48.062322 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5446 22:16:48.065437 iDelay=208, Bit 1, Center 95 (-8 ~ 199) 208
5447 22:16:48.068804 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5448 22:16:48.071897 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5449 22:16:48.075390 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5450 22:16:48.081958 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5451 22:16:48.085158 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5452 22:16:48.088126 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5453 22:16:48.091371 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5454 22:16:48.095164 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5455 22:16:48.101389 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5456 22:16:48.104687 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5457 22:16:48.107918 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5458 22:16:48.111249 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5459 22:16:48.114400 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5460 22:16:48.121248 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5461 22:16:48.121334 ==
5462 22:16:48.124601 Dram Type= 6, Freq= 0, CH_0, rank 1
5463 22:16:48.127954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5464 22:16:48.128039 ==
5465 22:16:48.128125 DQS Delay:
5466 22:16:48.130820 DQS0 = 0, DQS1 = 0
5467 22:16:48.130905 DQM Delay:
5468 22:16:48.134532 DQM0 = 92, DQM1 = 83
5469 22:16:48.134617 DQ Delay:
5470 22:16:48.138032 DQ0 =91, DQ1 =95, DQ2 =87, DQ3 =87
5471 22:16:48.140965 DQ4 =91, DQ5 =75, DQ6 =103, DQ7 =107
5472 22:16:48.144650 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =75
5473 22:16:48.147915 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5474 22:16:48.147996
5475 22:16:48.148061
5476 22:16:48.148120 ==
5477 22:16:48.151289 Dram Type= 6, Freq= 0, CH_0, rank 1
5478 22:16:48.154649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5479 22:16:48.157689 ==
5480 22:16:48.157770
5481 22:16:48.157835
5482 22:16:48.157896 TX Vref Scan disable
5483 22:16:48.160947 == TX Byte 0 ==
5484 22:16:48.164133 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5485 22:16:48.167504 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5486 22:16:48.170608 == TX Byte 1 ==
5487 22:16:48.174091 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5488 22:16:48.177180 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5489 22:16:48.180518 ==
5490 22:16:48.184068 Dram Type= 6, Freq= 0, CH_0, rank 1
5491 22:16:48.186913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5492 22:16:48.186985 ==
5493 22:16:48.187053
5494 22:16:48.187111
5495 22:16:48.190329 TX Vref Scan disable
5496 22:16:48.190426 == TX Byte 0 ==
5497 22:16:48.197300 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5498 22:16:48.200250 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5499 22:16:48.200333 == TX Byte 1 ==
5500 22:16:48.206959 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5501 22:16:48.210347 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5502 22:16:48.210429
5503 22:16:48.210493 [DATLAT]
5504 22:16:48.213717 Freq=933, CH0 RK1
5505 22:16:48.213798
5506 22:16:48.213863 DATLAT Default: 0xb
5507 22:16:48.217172 0, 0xFFFF, sum = 0
5508 22:16:48.217254 1, 0xFFFF, sum = 0
5509 22:16:48.220270 2, 0xFFFF, sum = 0
5510 22:16:48.220352 3, 0xFFFF, sum = 0
5511 22:16:48.223702 4, 0xFFFF, sum = 0
5512 22:16:48.227256 5, 0xFFFF, sum = 0
5513 22:16:48.227339 6, 0xFFFF, sum = 0
5514 22:16:48.230619 7, 0xFFFF, sum = 0
5515 22:16:48.230702 8, 0xFFFF, sum = 0
5516 22:16:48.233613 9, 0xFFFF, sum = 0
5517 22:16:48.233696 10, 0x0, sum = 1
5518 22:16:48.237259 11, 0x0, sum = 2
5519 22:16:48.237342 12, 0x0, sum = 3
5520 22:16:48.237407 13, 0x0, sum = 4
5521 22:16:48.240235 best_step = 11
5522 22:16:48.240317
5523 22:16:48.240380 ==
5524 22:16:48.243713 Dram Type= 6, Freq= 0, CH_0, rank 1
5525 22:16:48.247147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5526 22:16:48.247230 ==
5527 22:16:48.250200 RX Vref Scan: 0
5528 22:16:48.250281
5529 22:16:48.253562 RX Vref 0 -> 0, step: 1
5530 22:16:48.253643
5531 22:16:48.253707 RX Delay -77 -> 252, step: 4
5532 22:16:48.261264 iDelay=199, Bit 0, Center 90 (-5 ~ 186) 192
5533 22:16:48.264542 iDelay=199, Bit 1, Center 92 (-1 ~ 186) 188
5534 22:16:48.267930 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5535 22:16:48.271208 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5536 22:16:48.274478 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5537 22:16:48.280956 iDelay=199, Bit 5, Center 82 (-9 ~ 174) 184
5538 22:16:48.284009 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5539 22:16:48.287388 iDelay=199, Bit 7, Center 102 (7 ~ 198) 192
5540 22:16:48.290680 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5541 22:16:48.293797 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180
5542 22:16:48.300366 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5543 22:16:48.304031 iDelay=199, Bit 11, Center 78 (-13 ~ 170) 184
5544 22:16:48.307455 iDelay=199, Bit 12, Center 92 (-1 ~ 186) 188
5545 22:16:48.310444 iDelay=199, Bit 13, Center 92 (-1 ~ 186) 188
5546 22:16:48.313969 iDelay=199, Bit 14, Center 92 (-1 ~ 186) 188
5547 22:16:48.320301 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5548 22:16:48.320383 ==
5549 22:16:48.323895 Dram Type= 6, Freq= 0, CH_0, rank 1
5550 22:16:48.326856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5551 22:16:48.326938 ==
5552 22:16:48.327002 DQS Delay:
5553 22:16:48.329990 DQS0 = 0, DQS1 = 0
5554 22:16:48.330071 DQM Delay:
5555 22:16:48.333437 DQM0 = 92, DQM1 = 85
5556 22:16:48.333517 DQ Delay:
5557 22:16:48.336749 DQ0 =90, DQ1 =92, DQ2 =88, DQ3 =88
5558 22:16:48.339778 DQ4 =90, DQ5 =82, DQ6 =104, DQ7 =102
5559 22:16:48.343157 DQ8 =78, DQ9 =72, DQ10 =86, DQ11 =78
5560 22:16:48.346891 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
5561 22:16:48.346973
5562 22:16:48.347037
5563 22:16:48.356818 [DQSOSCAuto] RK1, (LSB)MR18= 0x3113, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 406 ps
5564 22:16:48.356900 CH0 RK1: MR19=505, MR18=3113
5565 22:16:48.363459 CH0_RK1: MR19=0x505, MR18=0x3113, DQSOSC=406, MR23=63, INC=65, DEC=43
5566 22:16:48.366664 [RxdqsGatingPostProcess] freq 933
5567 22:16:48.372950 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5568 22:16:48.376149 best DQS0 dly(2T, 0.5T) = (0, 10)
5569 22:16:48.379699 best DQS1 dly(2T, 0.5T) = (0, 11)
5570 22:16:48.382842 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5571 22:16:48.385976 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5572 22:16:48.389578 best DQS0 dly(2T, 0.5T) = (0, 10)
5573 22:16:48.389659 best DQS1 dly(2T, 0.5T) = (0, 10)
5574 22:16:48.392987 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5575 22:16:48.396211 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5576 22:16:48.399349 Pre-setting of DQS Precalculation
5577 22:16:48.406317 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5578 22:16:48.406399 ==
5579 22:16:48.409151 Dram Type= 6, Freq= 0, CH_1, rank 0
5580 22:16:48.412738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5581 22:16:48.412820 ==
5582 22:16:48.419228 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5583 22:16:48.426090 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5584 22:16:48.428901 [CA 0] Center 37 (7~67) winsize 61
5585 22:16:48.432431 [CA 1] Center 37 (7~68) winsize 62
5586 22:16:48.435832 [CA 2] Center 34 (5~64) winsize 60
5587 22:16:48.438955 [CA 3] Center 34 (5~64) winsize 60
5588 22:16:48.442261 [CA 4] Center 34 (5~64) winsize 60
5589 22:16:48.445406 [CA 5] Center 33 (4~63) winsize 60
5590 22:16:48.445487
5591 22:16:48.448624 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5592 22:16:48.448705
5593 22:16:48.451869 [CATrainingPosCal] consider 1 rank data
5594 22:16:48.455490 u2DelayCellTimex100 = 270/100 ps
5595 22:16:48.458394 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5596 22:16:48.461782 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5597 22:16:48.465479 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5598 22:16:48.468408 CA3 delay=34 (5~64),Diff = 1 PI (6 cell)
5599 22:16:48.471865 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5600 22:16:48.478239 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5601 22:16:48.478320
5602 22:16:48.481590 CA PerBit enable=1, Macro0, CA PI delay=33
5603 22:16:48.481671
5604 22:16:48.485268 [CBTSetCACLKResult] CA Dly = 33
5605 22:16:48.485349 CS Dly: 5 (0~36)
5606 22:16:48.485414 ==
5607 22:16:48.488490 Dram Type= 6, Freq= 0, CH_1, rank 1
5608 22:16:48.491664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5609 22:16:48.494838 ==
5610 22:16:48.497939 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5611 22:16:48.504614 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5612 22:16:48.507885 [CA 0] Center 37 (8~67) winsize 60
5613 22:16:48.511678 [CA 1] Center 37 (7~68) winsize 62
5614 22:16:48.514735 [CA 2] Center 35 (6~65) winsize 60
5615 22:16:48.517789 [CA 3] Center 34 (4~64) winsize 61
5616 22:16:48.521341 [CA 4] Center 35 (5~65) winsize 61
5617 22:16:48.524286 [CA 5] Center 34 (4~64) winsize 61
5618 22:16:48.524367
5619 22:16:48.527701 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5620 22:16:48.527782
5621 22:16:48.531244 [CATrainingPosCal] consider 2 rank data
5622 22:16:48.534242 u2DelayCellTimex100 = 270/100 ps
5623 22:16:48.537568 CA0 delay=37 (8~67),Diff = 4 PI (24 cell)
5624 22:16:48.540924 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5625 22:16:48.547412 CA2 delay=35 (6~64),Diff = 2 PI (12 cell)
5626 22:16:48.550616 CA3 delay=34 (5~64),Diff = 1 PI (6 cell)
5627 22:16:48.554360 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5628 22:16:48.557530 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5629 22:16:48.557611
5630 22:16:48.560461 CA PerBit enable=1, Macro0, CA PI delay=33
5631 22:16:48.560542
5632 22:16:48.563899 [CBTSetCACLKResult] CA Dly = 33
5633 22:16:48.563980 CS Dly: 6 (0~39)
5634 22:16:48.567498
5635 22:16:48.570535 ----->DramcWriteLeveling(PI) begin...
5636 22:16:48.570617 ==
5637 22:16:48.573953 Dram Type= 6, Freq= 0, CH_1, rank 0
5638 22:16:48.577245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5639 22:16:48.577326 ==
5640 22:16:48.580040 Write leveling (Byte 0): 23 => 23
5641 22:16:48.583491 Write leveling (Byte 1): 29 => 29
5642 22:16:48.587591 DramcWriteLeveling(PI) end<-----
5643 22:16:48.587686
5644 22:16:48.587750 ==
5645 22:16:48.590468 Dram Type= 6, Freq= 0, CH_1, rank 0
5646 22:16:48.593593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5647 22:16:48.593701 ==
5648 22:16:48.596924 [Gating] SW mode calibration
5649 22:16:48.603132 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5650 22:16:48.610048 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5651 22:16:48.613694 0 14 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5652 22:16:48.616365 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5653 22:16:48.623127 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5654 22:16:48.626645 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5655 22:16:48.630036 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5656 22:16:48.636637 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5657 22:16:48.639829 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
5658 22:16:48.643236 0 14 28 | B1->B0 | 2f2f 2e2e | 0 1 | (1 1) (0 1)
5659 22:16:48.649359 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5660 22:16:48.652953 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5661 22:16:48.656203 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5662 22:16:48.663042 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5663 22:16:48.666069 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5664 22:16:48.669774 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5665 22:16:48.676021 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5666 22:16:48.679556 0 15 28 | B1->B0 | 2f2f 3030 | 0 0 | (0 0) (0 0)
5667 22:16:48.683054 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5668 22:16:48.689602 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5669 22:16:48.692418 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5670 22:16:48.695779 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5671 22:16:48.702314 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5672 22:16:48.706002 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5673 22:16:48.709134 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5674 22:16:48.715764 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5675 22:16:48.718870 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5676 22:16:48.722231 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5677 22:16:48.728706 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5678 22:16:48.732133 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5679 22:16:48.735424 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5680 22:16:48.742297 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5681 22:16:48.745149 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5682 22:16:48.748459 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5683 22:16:48.755520 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5684 22:16:48.758306 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5685 22:16:48.761926 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5686 22:16:48.768213 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5687 22:16:48.771541 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5688 22:16:48.775119 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5689 22:16:48.781524 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5690 22:16:48.784895 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5691 22:16:48.788502 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5692 22:16:48.791489 Total UI for P1: 0, mck2ui 16
5693 22:16:48.794963 best dqsien dly found for B0: ( 1, 2, 28)
5694 22:16:48.801247 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5695 22:16:48.801866 Total UI for P1: 0, mck2ui 16
5696 22:16:48.808116 best dqsien dly found for B1: ( 1, 2, 30)
5697 22:16:48.812250 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5698 22:16:48.814667 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5699 22:16:48.815232
5700 22:16:48.818339 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5701 22:16:48.820980 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5702 22:16:48.824666 [Gating] SW calibration Done
5703 22:16:48.824987 ==
5704 22:16:48.827993 Dram Type= 6, Freq= 0, CH_1, rank 0
5705 22:16:48.831059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5706 22:16:48.831268 ==
5707 22:16:48.834419 RX Vref Scan: 0
5708 22:16:48.834597
5709 22:16:48.834764 RX Vref 0 -> 0, step: 1
5710 22:16:48.837443
5711 22:16:48.837611 RX Delay -80 -> 252, step: 8
5712 22:16:48.844282 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5713 22:16:48.847380 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5714 22:16:48.851213 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5715 22:16:48.853873 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5716 22:16:48.857421 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5717 22:16:48.860493 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5718 22:16:48.867614 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5719 22:16:48.870524 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5720 22:16:48.873985 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5721 22:16:48.877393 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5722 22:16:48.880280 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5723 22:16:48.887113 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5724 22:16:48.890362 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5725 22:16:48.894125 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5726 22:16:48.896877 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5727 22:16:48.900447 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5728 22:16:48.900671 ==
5729 22:16:48.903385 Dram Type= 6, Freq= 0, CH_1, rank 0
5730 22:16:48.910225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5731 22:16:48.910449 ==
5732 22:16:48.910627 DQS Delay:
5733 22:16:48.913073 DQS0 = 0, DQS1 = 0
5734 22:16:48.913299 DQM Delay:
5735 22:16:48.916527 DQM0 = 95, DQM1 = 87
5736 22:16:48.916750 DQ Delay:
5737 22:16:48.919900 DQ0 =99, DQ1 =91, DQ2 =83, DQ3 =99
5738 22:16:48.922899 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =95
5739 22:16:48.926440 DQ8 =75, DQ9 =79, DQ10 =87, DQ11 =83
5740 22:16:48.929556 DQ12 =95, DQ13 =95, DQ14 =91, DQ15 =91
5741 22:16:48.929781
5742 22:16:48.929959
5743 22:16:48.930122 ==
5744 22:16:48.933120 Dram Type= 6, Freq= 0, CH_1, rank 0
5745 22:16:48.936225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5746 22:16:48.936484 ==
5747 22:16:48.936688
5748 22:16:48.936884
5749 22:16:48.939996 TX Vref Scan disable
5750 22:16:48.942717 == TX Byte 0 ==
5751 22:16:48.946264 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5752 22:16:48.949711 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5753 22:16:48.953117 == TX Byte 1 ==
5754 22:16:48.956111 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5755 22:16:48.959084 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5756 22:16:48.959191 ==
5757 22:16:48.962562 Dram Type= 6, Freq= 0, CH_1, rank 0
5758 22:16:48.969120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5759 22:16:48.969227 ==
5760 22:16:48.969319
5761 22:16:48.969408
5762 22:16:48.969496 TX Vref Scan disable
5763 22:16:48.973256 == TX Byte 0 ==
5764 22:16:48.976616 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5765 22:16:48.983125 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5766 22:16:48.983198 == TX Byte 1 ==
5767 22:16:48.986671 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5768 22:16:48.993239 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5769 22:16:48.993321
5770 22:16:48.993382 [DATLAT]
5771 22:16:48.993443 Freq=933, CH1 RK0
5772 22:16:48.993540
5773 22:16:48.996439 DATLAT Default: 0xd
5774 22:16:48.999968 0, 0xFFFF, sum = 0
5775 22:16:49.000081 1, 0xFFFF, sum = 0
5776 22:16:49.003064 2, 0xFFFF, sum = 0
5777 22:16:49.003136 3, 0xFFFF, sum = 0
5778 22:16:49.006621 4, 0xFFFF, sum = 0
5779 22:16:49.006694 5, 0xFFFF, sum = 0
5780 22:16:49.009521 6, 0xFFFF, sum = 0
5781 22:16:49.009603 7, 0xFFFF, sum = 0
5782 22:16:49.012869 8, 0xFFFF, sum = 0
5783 22:16:49.012951 9, 0xFFFF, sum = 0
5784 22:16:49.016117 10, 0x0, sum = 1
5785 22:16:49.016199 11, 0x0, sum = 2
5786 22:16:49.019799 12, 0x0, sum = 3
5787 22:16:49.019881 13, 0x0, sum = 4
5788 22:16:49.019946 best_step = 11
5789 22:16:49.022770
5790 22:16:49.022850 ==
5791 22:16:49.026006 Dram Type= 6, Freq= 0, CH_1, rank 0
5792 22:16:49.029575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5793 22:16:49.029657 ==
5794 22:16:49.029721 RX Vref Scan: 1
5795 22:16:49.029780
5796 22:16:49.032906 RX Vref 0 -> 0, step: 1
5797 22:16:49.032986
5798 22:16:49.035956 RX Delay -69 -> 252, step: 4
5799 22:16:49.036037
5800 22:16:49.039778 Set Vref, RX VrefLevel [Byte0]: 55
5801 22:16:49.042504 [Byte1]: 50
5802 22:16:49.046087
5803 22:16:49.046168 Final RX Vref Byte 0 = 55 to rank0
5804 22:16:49.049445 Final RX Vref Byte 1 = 50 to rank0
5805 22:16:49.052758 Final RX Vref Byte 0 = 55 to rank1
5806 22:16:49.055844 Final RX Vref Byte 1 = 50 to rank1==
5807 22:16:49.059298 Dram Type= 6, Freq= 0, CH_1, rank 0
5808 22:16:49.065898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5809 22:16:49.065980 ==
5810 22:16:49.066044 DQS Delay:
5811 22:16:49.068848 DQS0 = 0, DQS1 = 0
5812 22:16:49.068928 DQM Delay:
5813 22:16:49.068993 DQM0 = 96, DQM1 = 88
5814 22:16:49.072304 DQ Delay:
5815 22:16:49.075898 DQ0 =102, DQ1 =92, DQ2 =84, DQ3 =92
5816 22:16:49.078638 DQ4 =94, DQ5 =106, DQ6 =108, DQ7 =94
5817 22:16:49.082119 DQ8 =76, DQ9 =80, DQ10 =88, DQ11 =80
5818 22:16:49.085823 DQ12 =98, DQ13 =94, DQ14 =98, DQ15 =94
5819 22:16:49.085904
5820 22:16:49.085968
5821 22:16:49.091924 [DQSOSCAuto] RK0, (LSB)MR18= 0xfe07, (MSB)MR19= 0x405, tDQSOscB0 = 419 ps tDQSOscB1 = 422 ps
5822 22:16:49.095532 CH1 RK0: MR19=405, MR18=FE07
5823 22:16:49.102220 CH1_RK0: MR19=0x405, MR18=0xFE07, DQSOSC=419, MR23=63, INC=61, DEC=41
5824 22:16:49.102304
5825 22:16:49.105386 ----->DramcWriteLeveling(PI) begin...
5826 22:16:49.105468 ==
5827 22:16:49.108879 Dram Type= 6, Freq= 0, CH_1, rank 1
5828 22:16:49.111774 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5829 22:16:49.111855 ==
5830 22:16:49.115372 Write leveling (Byte 0): 26 => 26
5831 22:16:49.118576 Write leveling (Byte 1): 29 => 29
5832 22:16:49.122231 DramcWriteLeveling(PI) end<-----
5833 22:16:49.122313
5834 22:16:49.122376 ==
5835 22:16:49.125207 Dram Type= 6, Freq= 0, CH_1, rank 1
5836 22:16:49.131336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5837 22:16:49.131418 ==
5838 22:16:49.131483 [Gating] SW mode calibration
5839 22:16:49.141625 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5840 22:16:49.144789 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5841 22:16:49.148179 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5842 22:16:49.154641 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5843 22:16:49.157996 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5844 22:16:49.161303 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5845 22:16:49.167994 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5846 22:16:49.171451 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5847 22:16:49.177840 0 14 24 | B1->B0 | 3434 3131 | 1 1 | (0 0) (0 1)
5848 22:16:49.180817 0 14 28 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
5849 22:16:49.184370 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5850 22:16:49.190858 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5851 22:16:49.194570 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5852 22:16:49.197434 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5853 22:16:49.200649 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5854 22:16:49.207324 0 15 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5855 22:16:49.210860 0 15 24 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
5856 22:16:49.217193 0 15 28 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5857 22:16:49.220731 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5858 22:16:49.223957 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5859 22:16:49.227143 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5860 22:16:49.233486 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5861 22:16:49.237124 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5862 22:16:49.240354 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5863 22:16:49.246846 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5864 22:16:49.250286 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5865 22:16:49.253408 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5866 22:16:49.260184 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5867 22:16:49.263550 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5868 22:16:49.266670 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5869 22:16:49.273769 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5870 22:16:49.276849 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5871 22:16:49.280366 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5872 22:16:49.286802 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5873 22:16:49.290209 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5874 22:16:49.293387 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5875 22:16:49.299823 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5876 22:16:49.303168 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5877 22:16:49.306198 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5878 22:16:49.313122 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5879 22:16:49.316575 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5880 22:16:49.319468 Total UI for P1: 0, mck2ui 16
5881 22:16:49.322822 best dqsien dly found for B0: ( 1, 2, 22)
5882 22:16:49.326210 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5883 22:16:49.332744 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5884 22:16:49.336280 Total UI for P1: 0, mck2ui 16
5885 22:16:49.339315 best dqsien dly found for B1: ( 1, 2, 30)
5886 22:16:49.342643 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5887 22:16:49.346273 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5888 22:16:49.346356
5889 22:16:49.349361 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5890 22:16:49.352157 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5891 22:16:49.355610 [Gating] SW calibration Done
5892 22:16:49.355693 ==
5893 22:16:49.359048 Dram Type= 6, Freq= 0, CH_1, rank 1
5894 22:16:49.362725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5895 22:16:49.363198 ==
5896 22:16:49.366108 RX Vref Scan: 0
5897 22:16:49.366679
5898 22:16:49.369212 RX Vref 0 -> 0, step: 1
5899 22:16:49.369684
5900 22:16:49.370057 RX Delay -80 -> 252, step: 8
5901 22:16:49.376097 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5902 22:16:49.379345 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5903 22:16:49.382647 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5904 22:16:49.386107 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5905 22:16:49.388983 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5906 22:16:49.395919 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5907 22:16:49.398923 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5908 22:16:49.402612 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5909 22:16:49.405644 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5910 22:16:49.408904 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5911 22:16:49.415558 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5912 22:16:49.419149 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5913 22:16:49.422348 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5914 22:16:49.425693 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5915 22:16:49.428839 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5916 22:16:49.431962 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5917 22:16:49.435539 ==
5918 22:16:49.438819 Dram Type= 6, Freq= 0, CH_1, rank 1
5919 22:16:49.442028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5920 22:16:49.442628 ==
5921 22:16:49.443195 DQS Delay:
5922 22:16:49.445165 DQS0 = 0, DQS1 = 0
5923 22:16:49.445749 DQM Delay:
5924 22:16:49.448642 DQM0 = 93, DQM1 = 87
5925 22:16:49.449108 DQ Delay:
5926 22:16:49.452060 DQ0 =95, DQ1 =91, DQ2 =83, DQ3 =91
5927 22:16:49.455524 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5928 22:16:49.458365 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =83
5929 22:16:49.461530 DQ12 =95, DQ13 =95, DQ14 =91, DQ15 =91
5930 22:16:49.461999
5931 22:16:49.462371
5932 22:16:49.462717 ==
5933 22:16:49.465328 Dram Type= 6, Freq= 0, CH_1, rank 1
5934 22:16:49.468407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5935 22:16:49.471845 ==
5936 22:16:49.472316
5937 22:16:49.472685
5938 22:16:49.473025 TX Vref Scan disable
5939 22:16:49.474623 == TX Byte 0 ==
5940 22:16:49.478416 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5941 22:16:49.481338 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5942 22:16:49.484528 == TX Byte 1 ==
5943 22:16:49.487907 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5944 22:16:49.491198 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5945 22:16:49.494307 ==
5946 22:16:49.497923 Dram Type= 6, Freq= 0, CH_1, rank 1
5947 22:16:49.500805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5948 22:16:49.501200 ==
5949 22:16:49.501465
5950 22:16:49.501707
5951 22:16:49.504385 TX Vref Scan disable
5952 22:16:49.504712 == TX Byte 0 ==
5953 22:16:49.510831 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5954 22:16:49.514320 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5955 22:16:49.514646 == TX Byte 1 ==
5956 22:16:49.520892 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5957 22:16:49.523798 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5958 22:16:49.524173
5959 22:16:49.524479 [DATLAT]
5960 22:16:49.527422 Freq=933, CH1 RK1
5961 22:16:49.527826
5962 22:16:49.528090 DATLAT Default: 0xb
5963 22:16:49.530578 0, 0xFFFF, sum = 0
5964 22:16:49.531001 1, 0xFFFF, sum = 0
5965 22:16:49.533423 2, 0xFFFF, sum = 0
5966 22:16:49.536828 3, 0xFFFF, sum = 0
5967 22:16:49.537159 4, 0xFFFF, sum = 0
5968 22:16:49.540346 5, 0xFFFF, sum = 0
5969 22:16:49.540675 6, 0xFFFF, sum = 0
5970 22:16:49.543338 7, 0xFFFF, sum = 0
5971 22:16:49.543698 8, 0xFFFF, sum = 0
5972 22:16:49.546634 9, 0xFFFF, sum = 0
5973 22:16:49.546966 10, 0x0, sum = 1
5974 22:16:49.550192 11, 0x0, sum = 2
5975 22:16:49.550520 12, 0x0, sum = 3
5976 22:16:49.553118 13, 0x0, sum = 4
5977 22:16:49.553446 best_step = 11
5978 22:16:49.553704
5979 22:16:49.553966 ==
5980 22:16:49.556446 Dram Type= 6, Freq= 0, CH_1, rank 1
5981 22:16:49.559832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5982 22:16:49.560160 ==
5983 22:16:49.563595 RX Vref Scan: 0
5984 22:16:49.563925
5985 22:16:49.566333 RX Vref 0 -> 0, step: 1
5986 22:16:49.566657
5987 22:16:49.566913 RX Delay -69 -> 252, step: 4
5988 22:16:49.575007 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5989 22:16:49.577599 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5990 22:16:49.581379 iDelay=203, Bit 2, Center 80 (-17 ~ 178) 196
5991 22:16:49.584616 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5992 22:16:49.587841 iDelay=203, Bit 4, Center 88 (-9 ~ 186) 196
5993 22:16:49.594404 iDelay=203, Bit 5, Center 100 (3 ~ 198) 196
5994 22:16:49.597562 iDelay=203, Bit 6, Center 100 (-1 ~ 202) 204
5995 22:16:49.601104 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5996 22:16:49.604460 iDelay=203, Bit 8, Center 76 (-17 ~ 170) 188
5997 22:16:49.607214 iDelay=203, Bit 9, Center 82 (-13 ~ 178) 192
5998 22:16:49.613779 iDelay=203, Bit 10, Center 90 (-5 ~ 186) 192
5999 22:16:49.617245 iDelay=203, Bit 11, Center 82 (-13 ~ 178) 192
6000 22:16:49.620775 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
6001 22:16:49.623557 iDelay=203, Bit 13, Center 94 (-1 ~ 190) 192
6002 22:16:49.626987 iDelay=203, Bit 14, Center 96 (3 ~ 190) 188
6003 22:16:49.633892 iDelay=203, Bit 15, Center 96 (3 ~ 190) 188
6004 22:16:49.634222 ==
6005 22:16:49.636791 Dram Type= 6, Freq= 0, CH_1, rank 1
6006 22:16:49.640546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6007 22:16:49.640896 ==
6008 22:16:49.641164 DQS Delay:
6009 22:16:49.643787 DQS0 = 0, DQS1 = 0
6010 22:16:49.644112 DQM Delay:
6011 22:16:49.646653 DQM0 = 90, DQM1 = 89
6012 22:16:49.646976 DQ Delay:
6013 22:16:49.650241 DQ0 =96, DQ1 =86, DQ2 =80, DQ3 =88
6014 22:16:49.653212 DQ4 =88, DQ5 =100, DQ6 =100, DQ7 =88
6015 22:16:49.656679 DQ8 =76, DQ9 =82, DQ10 =90, DQ11 =82
6016 22:16:49.659963 DQ12 =96, DQ13 =94, DQ14 =96, DQ15 =96
6017 22:16:49.660289
6018 22:16:49.660564
6019 22:16:49.669838 [DQSOSCAuto] RK1, (LSB)MR18= 0xe23, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 417 ps
6020 22:16:49.670170 CH1 RK1: MR19=505, MR18=E23
6021 22:16:49.676364 CH1_RK1: MR19=0x505, MR18=0xE23, DQSOSC=410, MR23=63, INC=64, DEC=42
6022 22:16:49.679942 [RxdqsGatingPostProcess] freq 933
6023 22:16:49.686093 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6024 22:16:49.689303 best DQS0 dly(2T, 0.5T) = (0, 10)
6025 22:16:49.692878 best DQS1 dly(2T, 0.5T) = (0, 10)
6026 22:16:49.696123 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6027 22:16:49.699446 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6028 22:16:49.702630 best DQS0 dly(2T, 0.5T) = (0, 10)
6029 22:16:49.702963 best DQS1 dly(2T, 0.5T) = (0, 10)
6030 22:16:49.706032 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6031 22:16:49.709125 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6032 22:16:49.712242 Pre-setting of DQS Precalculation
6033 22:16:49.718848 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6034 22:16:49.726058 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6035 22:16:49.732146 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6036 22:16:49.732481
6037 22:16:49.732785
6038 22:16:49.735056 [Calibration Summary] 1866 Mbps
6039 22:16:49.738518 CH 0, Rank 0
6040 22:16:49.738858 SW Impedance : PASS
6041 22:16:49.741981 DUTY Scan : NO K
6042 22:16:49.745441 ZQ Calibration : PASS
6043 22:16:49.745817 Jitter Meter : NO K
6044 22:16:49.748686 CBT Training : PASS
6045 22:16:49.751729 Write leveling : PASS
6046 22:16:49.752170 RX DQS gating : PASS
6047 22:16:49.755396 RX DQ/DQS(RDDQC) : PASS
6048 22:16:49.758265 TX DQ/DQS : PASS
6049 22:16:49.758576 RX DATLAT : PASS
6050 22:16:49.761852 RX DQ/DQS(Engine): PASS
6051 22:16:49.765059 TX OE : NO K
6052 22:16:49.765496 All Pass.
6053 22:16:49.765916
6054 22:16:49.766326 CH 0, Rank 1
6055 22:16:49.768513 SW Impedance : PASS
6056 22:16:49.771485 DUTY Scan : NO K
6057 22:16:49.771972 ZQ Calibration : PASS
6058 22:16:49.775043 Jitter Meter : NO K
6059 22:16:49.777939 CBT Training : PASS
6060 22:16:49.778406 Write leveling : PASS
6061 22:16:49.781834 RX DQS gating : PASS
6062 22:16:49.782315 RX DQ/DQS(RDDQC) : PASS
6063 22:16:49.784578 TX DQ/DQS : PASS
6064 22:16:49.787692 RX DATLAT : PASS
6065 22:16:49.788151 RX DQ/DQS(Engine): PASS
6066 22:16:49.791289 TX OE : NO K
6067 22:16:49.791843 All Pass.
6068 22:16:49.792328
6069 22:16:49.794608 CH 1, Rank 0
6070 22:16:49.795089 SW Impedance : PASS
6071 22:16:49.797879 DUTY Scan : NO K
6072 22:16:49.801032 ZQ Calibration : PASS
6073 22:16:49.801572 Jitter Meter : NO K
6074 22:16:49.804679 CBT Training : PASS
6075 22:16:49.807785 Write leveling : PASS
6076 22:16:49.808304 RX DQS gating : PASS
6077 22:16:49.810999 RX DQ/DQS(RDDQC) : PASS
6078 22:16:49.813915 TX DQ/DQS : PASS
6079 22:16:49.814166 RX DATLAT : PASS
6080 22:16:49.817749 RX DQ/DQS(Engine): PASS
6081 22:16:49.820706 TX OE : NO K
6082 22:16:49.820870 All Pass.
6083 22:16:49.821032
6084 22:16:49.821184 CH 1, Rank 1
6085 22:16:49.824142 SW Impedance : PASS
6086 22:16:49.827010 DUTY Scan : NO K
6087 22:16:49.827173 ZQ Calibration : PASS
6088 22:16:49.830659 Jitter Meter : NO K
6089 22:16:49.833945 CBT Training : PASS
6090 22:16:49.834107 Write leveling : PASS
6091 22:16:49.837443 RX DQS gating : PASS
6092 22:16:49.840347 RX DQ/DQS(RDDQC) : PASS
6093 22:16:49.840509 TX DQ/DQS : PASS
6094 22:16:49.843847 RX DATLAT : PASS
6095 22:16:49.847034 RX DQ/DQS(Engine): PASS
6096 22:16:49.847196 TX OE : NO K
6097 22:16:49.847359 All Pass.
6098 22:16:49.850294
6099 22:16:49.850456 DramC Write-DBI off
6100 22:16:49.853848 PER_BANK_REFRESH: Hybrid Mode
6101 22:16:49.854021 TX_TRACKING: ON
6102 22:16:49.863442 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6103 22:16:49.866556 [FAST_K] Save calibration result to emmc
6104 22:16:49.869951 dramc_set_vcore_voltage set vcore to 650000
6105 22:16:49.873175 Read voltage for 400, 6
6106 22:16:49.873259 Vio18 = 0
6107 22:16:49.876790 Vcore = 650000
6108 22:16:49.876874 Vdram = 0
6109 22:16:49.876957 Vddq = 0
6110 22:16:49.879627 Vmddr = 0
6111 22:16:49.883095 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6112 22:16:49.889275 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6113 22:16:49.889360 MEM_TYPE=3, freq_sel=20
6114 22:16:49.892942 sv_algorithm_assistance_LP4_800
6115 22:16:49.899206 ============ PULL DRAM RESETB DOWN ============
6116 22:16:49.902738 ========== PULL DRAM RESETB DOWN end =========
6117 22:16:49.906008 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6118 22:16:49.909207 ===================================
6119 22:16:49.912500 LPDDR4 DRAM CONFIGURATION
6120 22:16:49.916065 ===================================
6121 22:16:49.919506 EX_ROW_EN[0] = 0x0
6122 22:16:49.919615 EX_ROW_EN[1] = 0x0
6123 22:16:49.922692 LP4Y_EN = 0x0
6124 22:16:49.922774 WORK_FSP = 0x0
6125 22:16:49.925950 WL = 0x2
6126 22:16:49.926033 RL = 0x2
6127 22:16:49.929251 BL = 0x2
6128 22:16:49.929334 RPST = 0x0
6129 22:16:49.932305 RD_PRE = 0x0
6130 22:16:49.932387 WR_PRE = 0x1
6131 22:16:49.935921 WR_PST = 0x0
6132 22:16:49.936031 DBI_WR = 0x0
6133 22:16:49.938787 DBI_RD = 0x0
6134 22:16:49.938868 OTF = 0x1
6135 22:16:49.942144 ===================================
6136 22:16:49.945619 ===================================
6137 22:16:49.949125 ANA top config
6138 22:16:49.951864 ===================================
6139 22:16:49.955145 DLL_ASYNC_EN = 0
6140 22:16:49.955253 ALL_SLAVE_EN = 1
6141 22:16:49.958899 NEW_RANK_MODE = 1
6142 22:16:49.962316 DLL_IDLE_MODE = 1
6143 22:16:49.964992 LP45_APHY_COMB_EN = 1
6144 22:16:49.968244 TX_ODT_DIS = 1
6145 22:16:49.968327 NEW_8X_MODE = 1
6146 22:16:49.971839 ===================================
6147 22:16:49.974977 ===================================
6148 22:16:49.978702 data_rate = 800
6149 22:16:49.981524 CKR = 1
6150 22:16:49.985268 DQ_P2S_RATIO = 4
6151 22:16:49.988485 ===================================
6152 22:16:49.991606 CA_P2S_RATIO = 4
6153 22:16:49.995053 DQ_CA_OPEN = 0
6154 22:16:49.995135 DQ_SEMI_OPEN = 1
6155 22:16:49.997880 CA_SEMI_OPEN = 1
6156 22:16:50.001147 CA_FULL_RATE = 0
6157 22:16:50.004754 DQ_CKDIV4_EN = 0
6158 22:16:50.008388 CA_CKDIV4_EN = 1
6159 22:16:50.011514 CA_PREDIV_EN = 0
6160 22:16:50.011656 PH8_DLY = 0
6161 22:16:50.014726 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6162 22:16:50.018026 DQ_AAMCK_DIV = 0
6163 22:16:50.021346 CA_AAMCK_DIV = 0
6164 22:16:50.024738 CA_ADMCK_DIV = 4
6165 22:16:50.027844 DQ_TRACK_CA_EN = 0
6166 22:16:50.030964 CA_PICK = 800
6167 22:16:50.031046 CA_MCKIO = 400
6168 22:16:50.034384 MCKIO_SEMI = 400
6169 22:16:50.037711 PLL_FREQ = 3016
6170 22:16:50.041311 DQ_UI_PI_RATIO = 32
6171 22:16:50.044079 CA_UI_PI_RATIO = 32
6172 22:16:50.047452 ===================================
6173 22:16:50.051018 ===================================
6174 22:16:50.054054 memory_type:LPDDR4
6175 22:16:50.054136 GP_NUM : 10
6176 22:16:50.057469 SRAM_EN : 1
6177 22:16:50.060360 MD32_EN : 0
6178 22:16:50.063848 ===================================
6179 22:16:50.063943 [ANA_INIT] >>>>>>>>>>>>>>
6180 22:16:50.067272 <<<<<< [CONFIGURE PHASE]: ANA_TX
6181 22:16:50.070215 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6182 22:16:50.074188 ===================================
6183 22:16:50.076857 data_rate = 800,PCW = 0X7400
6184 22:16:50.080447 ===================================
6185 22:16:50.083909 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6186 22:16:50.090051 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6187 22:16:50.100473 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6188 22:16:50.106870 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6189 22:16:50.110239 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6190 22:16:50.113705 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6191 22:16:50.113776 [ANA_INIT] flow start
6192 22:16:50.116838 [ANA_INIT] PLL >>>>>>>>
6193 22:16:50.120302 [ANA_INIT] PLL <<<<<<<<
6194 22:16:50.120383 [ANA_INIT] MIDPI >>>>>>>>
6195 22:16:50.123422 [ANA_INIT] MIDPI <<<<<<<<
6196 22:16:50.126809 [ANA_INIT] DLL >>>>>>>>
6197 22:16:50.126879 [ANA_INIT] flow end
6198 22:16:50.133420 ============ LP4 DIFF to SE enter ============
6199 22:16:50.136665 ============ LP4 DIFF to SE exit ============
6200 22:16:50.139555 [ANA_INIT] <<<<<<<<<<<<<
6201 22:16:50.142856 [Flow] Enable top DCM control >>>>>
6202 22:16:50.146121 [Flow] Enable top DCM control <<<<<
6203 22:16:50.146203 Enable DLL master slave shuffle
6204 22:16:50.153414 ==============================================================
6205 22:16:50.156175 Gating Mode config
6206 22:16:50.159743 ==============================================================
6207 22:16:50.163199 Config description:
6208 22:16:50.172572 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6209 22:16:50.179425 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6210 22:16:50.182453 SELPH_MODE 0: By rank 1: By Phase
6211 22:16:50.189134 ==============================================================
6212 22:16:50.192447 GAT_TRACK_EN = 0
6213 22:16:50.195711 RX_GATING_MODE = 2
6214 22:16:50.199220 RX_GATING_TRACK_MODE = 2
6215 22:16:50.202355 SELPH_MODE = 1
6216 22:16:50.205848 PICG_EARLY_EN = 1
6217 22:16:50.205930 VALID_LAT_VALUE = 1
6218 22:16:50.212221 ==============================================================
6219 22:16:50.215750 Enter into Gating configuration >>>>
6220 22:16:50.219277 Exit from Gating configuration <<<<
6221 22:16:50.222690 Enter into DVFS_PRE_config >>>>>
6222 22:16:50.232219 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6223 22:16:50.235510 Exit from DVFS_PRE_config <<<<<
6224 22:16:50.238747 Enter into PICG configuration >>>>
6225 22:16:50.242217 Exit from PICG configuration <<<<
6226 22:16:50.245450 [RX_INPUT] configuration >>>>>
6227 22:16:50.248764 [RX_INPUT] configuration <<<<<
6228 22:16:50.255371 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6229 22:16:50.258933 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6230 22:16:50.265210 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6231 22:16:50.272092 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6232 22:16:50.278565 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6233 22:16:50.285804 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6234 22:16:50.288637 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6235 22:16:50.291672 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6236 22:16:50.295012 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6237 22:16:50.301844 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6238 22:16:50.305460 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6239 22:16:50.308316 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6240 22:16:50.311319 ===================================
6241 22:16:50.314648 LPDDR4 DRAM CONFIGURATION
6242 22:16:50.318150 ===================================
6243 22:16:50.318231 EX_ROW_EN[0] = 0x0
6244 22:16:50.321480 EX_ROW_EN[1] = 0x0
6245 22:16:50.324478 LP4Y_EN = 0x0
6246 22:16:50.324560 WORK_FSP = 0x0
6247 22:16:50.328091 WL = 0x2
6248 22:16:50.328173 RL = 0x2
6249 22:16:50.331621 BL = 0x2
6250 22:16:50.331702 RPST = 0x0
6251 22:16:50.334468 RD_PRE = 0x0
6252 22:16:50.334549 WR_PRE = 0x1
6253 22:16:50.337951 WR_PST = 0x0
6254 22:16:50.338038 DBI_WR = 0x0
6255 22:16:50.340994 DBI_RD = 0x0
6256 22:16:50.341076 OTF = 0x1
6257 22:16:50.344330 ===================================
6258 22:16:50.347668 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6259 22:16:50.354384 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6260 22:16:50.357606 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6261 22:16:50.360613 ===================================
6262 22:16:50.364128 LPDDR4 DRAM CONFIGURATION
6263 22:16:50.367503 ===================================
6264 22:16:50.370571 EX_ROW_EN[0] = 0x10
6265 22:16:50.370674 EX_ROW_EN[1] = 0x0
6266 22:16:50.374180 LP4Y_EN = 0x0
6267 22:16:50.374251 WORK_FSP = 0x0
6268 22:16:50.377121 WL = 0x2
6269 22:16:50.377216 RL = 0x2
6270 22:16:50.380391 BL = 0x2
6271 22:16:50.380473 RPST = 0x0
6272 22:16:50.384261 RD_PRE = 0x0
6273 22:16:50.384356 WR_PRE = 0x1
6274 22:16:50.387515 WR_PST = 0x0
6275 22:16:50.387603 DBI_WR = 0x0
6276 22:16:50.390348 DBI_RD = 0x0
6277 22:16:50.390429 OTF = 0x1
6278 22:16:50.394209 ===================================
6279 22:16:50.400088 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6280 22:16:50.405058 nWR fixed to 30
6281 22:16:50.408531 [ModeRegInit_LP4] CH0 RK0
6282 22:16:50.408613 [ModeRegInit_LP4] CH0 RK1
6283 22:16:50.411985 [ModeRegInit_LP4] CH1 RK0
6284 22:16:50.414947 [ModeRegInit_LP4] CH1 RK1
6285 22:16:50.415028 match AC timing 19
6286 22:16:50.421897 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6287 22:16:50.424672 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6288 22:16:50.428144 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6289 22:16:50.434533 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6290 22:16:50.438147 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6291 22:16:50.438230 ==
6292 22:16:50.441229 Dram Type= 6, Freq= 0, CH_0, rank 0
6293 22:16:50.444368 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6294 22:16:50.444450 ==
6295 22:16:50.451124 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6296 22:16:50.457996 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6297 22:16:50.461347 [CA 0] Center 36 (8~64) winsize 57
6298 22:16:50.464682 [CA 1] Center 36 (8~64) winsize 57
6299 22:16:50.467519 [CA 2] Center 36 (8~64) winsize 57
6300 22:16:50.471170 [CA 3] Center 36 (8~64) winsize 57
6301 22:16:50.474012 [CA 4] Center 36 (8~64) winsize 57
6302 22:16:50.477597 [CA 5] Center 36 (8~64) winsize 57
6303 22:16:50.477678
6304 22:16:50.480639 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6305 22:16:50.480721
6306 22:16:50.483981 [CATrainingPosCal] consider 1 rank data
6307 22:16:50.487426 u2DelayCellTimex100 = 270/100 ps
6308 22:16:50.490926 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6309 22:16:50.494313 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6310 22:16:50.497726 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6311 22:16:50.500510 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6312 22:16:50.504261 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6313 22:16:50.507187 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6314 22:16:50.507269
6315 22:16:50.513975 CA PerBit enable=1, Macro0, CA PI delay=36
6316 22:16:50.514060
6317 22:16:50.514125 [CBTSetCACLKResult] CA Dly = 36
6318 22:16:50.516895 CS Dly: 1 (0~32)
6319 22:16:50.516977 ==
6320 22:16:50.520315 Dram Type= 6, Freq= 0, CH_0, rank 1
6321 22:16:50.523719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6322 22:16:50.523802 ==
6323 22:16:50.530312 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6324 22:16:50.537357 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6325 22:16:50.540171 [CA 0] Center 36 (8~64) winsize 57
6326 22:16:50.543759 [CA 1] Center 36 (8~64) winsize 57
6327 22:16:50.546681 [CA 2] Center 36 (8~64) winsize 57
6328 22:16:50.550577 [CA 3] Center 36 (8~64) winsize 57
6329 22:16:50.550658 [CA 4] Center 36 (8~64) winsize 57
6330 22:16:50.553651 [CA 5] Center 36 (8~64) winsize 57
6331 22:16:50.553733
6332 22:16:50.560083 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6333 22:16:50.560164
6334 22:16:50.563429 [CATrainingPosCal] consider 2 rank data
6335 22:16:50.566534 u2DelayCellTimex100 = 270/100 ps
6336 22:16:50.569999 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6337 22:16:50.573450 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6338 22:16:50.576760 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6339 22:16:50.580397 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6340 22:16:50.583364 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6341 22:16:50.586755 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6342 22:16:50.586925
6343 22:16:50.590411 CA PerBit enable=1, Macro0, CA PI delay=36
6344 22:16:50.590617
6345 22:16:50.593122 [CBTSetCACLKResult] CA Dly = 36
6346 22:16:50.596504 CS Dly: 1 (0~32)
6347 22:16:50.596718
6348 22:16:50.599616 ----->DramcWriteLeveling(PI) begin...
6349 22:16:50.599729 ==
6350 22:16:50.603150 Dram Type= 6, Freq= 0, CH_0, rank 0
6351 22:16:50.606132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6352 22:16:50.606273 ==
6353 22:16:50.609385 Write leveling (Byte 0): 40 => 8
6354 22:16:50.612598 Write leveling (Byte 1): 40 => 8
6355 22:16:50.616119 DramcWriteLeveling(PI) end<-----
6356 22:16:50.616196
6357 22:16:50.616293 ==
6358 22:16:50.619572 Dram Type= 6, Freq= 0, CH_0, rank 0
6359 22:16:50.622487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6360 22:16:50.622570 ==
6361 22:16:50.625808 [Gating] SW mode calibration
6362 22:16:50.632929 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6363 22:16:50.639209 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6364 22:16:50.642586 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6365 22:16:50.648826 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6366 22:16:50.652159 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6367 22:16:50.655503 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6368 22:16:50.662574 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6369 22:16:50.665515 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6370 22:16:50.668646 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6371 22:16:50.675198 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6372 22:16:50.678629 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6373 22:16:50.681831 Total UI for P1: 0, mck2ui 16
6374 22:16:50.685313 best dqsien dly found for B0: ( 0, 14, 24)
6375 22:16:50.688836 Total UI for P1: 0, mck2ui 16
6376 22:16:50.691712 best dqsien dly found for B1: ( 0, 14, 24)
6377 22:16:50.695042 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6378 22:16:50.698560 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6379 22:16:50.698640
6380 22:16:50.701983 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6381 22:16:50.705310 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6382 22:16:50.708214 [Gating] SW calibration Done
6383 22:16:50.708295 ==
6384 22:16:50.711630 Dram Type= 6, Freq= 0, CH_0, rank 0
6385 22:16:50.718234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6386 22:16:50.718315 ==
6387 22:16:50.718379 RX Vref Scan: 0
6388 22:16:50.718437
6389 22:16:50.721396 RX Vref 0 -> 0, step: 1
6390 22:16:50.721476
6391 22:16:50.724512 RX Delay -410 -> 252, step: 16
6392 22:16:50.727868 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6393 22:16:50.731274 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6394 22:16:50.737779 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6395 22:16:50.741324 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6396 22:16:50.744881 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6397 22:16:50.747903 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6398 22:16:50.754863 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6399 22:16:50.757607 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6400 22:16:50.761112 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6401 22:16:50.764190 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6402 22:16:50.771132 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6403 22:16:50.774025 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6404 22:16:50.777854 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6405 22:16:50.780547 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6406 22:16:50.787514 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6407 22:16:50.790516 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6408 22:16:50.790598 ==
6409 22:16:50.794126 Dram Type= 6, Freq= 0, CH_0, rank 0
6410 22:16:50.796818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6411 22:16:50.800247 ==
6412 22:16:50.800328 DQS Delay:
6413 22:16:50.800392 DQS0 = 59, DQS1 = 59
6414 22:16:50.803895 DQM Delay:
6415 22:16:50.803976 DQM0 = 18, DQM1 = 11
6416 22:16:50.806799 DQ Delay:
6417 22:16:50.809982 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6418 22:16:50.810063 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6419 22:16:50.813290 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6420 22:16:50.816929 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6421 22:16:50.817010
6422 22:16:50.820217
6423 22:16:50.820299 ==
6424 22:16:50.823166 Dram Type= 6, Freq= 0, CH_0, rank 0
6425 22:16:50.826748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6426 22:16:50.826824 ==
6427 22:16:50.826886
6428 22:16:50.826945
6429 22:16:50.830121 TX Vref Scan disable
6430 22:16:50.830202 == TX Byte 0 ==
6431 22:16:50.833271 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6432 22:16:50.839941 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6433 22:16:50.840022 == TX Byte 1 ==
6434 22:16:50.843406 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6435 22:16:50.849891 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6436 22:16:50.849971 ==
6437 22:16:50.852838 Dram Type= 6, Freq= 0, CH_0, rank 0
6438 22:16:50.856854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6439 22:16:50.856935 ==
6440 22:16:50.856999
6441 22:16:50.857058
6442 22:16:50.859796 TX Vref Scan disable
6443 22:16:50.859876 == TX Byte 0 ==
6444 22:16:50.866127 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6445 22:16:50.869586 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6446 22:16:50.869667 == TX Byte 1 ==
6447 22:16:50.873166 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6448 22:16:50.879200 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6449 22:16:50.879281
6450 22:16:50.879345 [DATLAT]
6451 22:16:50.883121 Freq=400, CH0 RK0
6452 22:16:50.883202
6453 22:16:50.883265 DATLAT Default: 0xf
6454 22:16:50.886278 0, 0xFFFF, sum = 0
6455 22:16:50.886360 1, 0xFFFF, sum = 0
6456 22:16:50.889444 2, 0xFFFF, sum = 0
6457 22:16:50.889525 3, 0xFFFF, sum = 0
6458 22:16:50.893008 4, 0xFFFF, sum = 0
6459 22:16:50.893090 5, 0xFFFF, sum = 0
6460 22:16:50.896299 6, 0xFFFF, sum = 0
6461 22:16:50.896380 7, 0xFFFF, sum = 0
6462 22:16:50.899074 8, 0xFFFF, sum = 0
6463 22:16:50.899155 9, 0xFFFF, sum = 0
6464 22:16:50.902288 10, 0xFFFF, sum = 0
6465 22:16:50.902369 11, 0xFFFF, sum = 0
6466 22:16:50.905944 12, 0xFFFF, sum = 0
6467 22:16:50.906027 13, 0x0, sum = 1
6468 22:16:50.909446 14, 0x0, sum = 2
6469 22:16:50.909533 15, 0x0, sum = 3
6470 22:16:50.912279 16, 0x0, sum = 4
6471 22:16:50.912363 best_step = 14
6472 22:16:50.912428
6473 22:16:50.912489 ==
6474 22:16:50.915904 Dram Type= 6, Freq= 0, CH_0, rank 0
6475 22:16:50.922621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6476 22:16:50.922704 ==
6477 22:16:50.922769 RX Vref Scan: 1
6478 22:16:50.922830
6479 22:16:50.925352 RX Vref 0 -> 0, step: 1
6480 22:16:50.925434
6481 22:16:50.929039 RX Delay -359 -> 252, step: 8
6482 22:16:50.929122
6483 22:16:50.932195 Set Vref, RX VrefLevel [Byte0]: 61
6484 22:16:50.935269 [Byte1]: 56
6485 22:16:50.939193
6486 22:16:50.939275 Final RX Vref Byte 0 = 61 to rank0
6487 22:16:50.942359 Final RX Vref Byte 1 = 56 to rank0
6488 22:16:50.945800 Final RX Vref Byte 0 = 61 to rank1
6489 22:16:50.949273 Final RX Vref Byte 1 = 56 to rank1==
6490 22:16:50.951928 Dram Type= 6, Freq= 0, CH_0, rank 0
6491 22:16:50.958752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6492 22:16:50.958835 ==
6493 22:16:50.958901 DQS Delay:
6494 22:16:50.962170 DQS0 = 60, DQS1 = 68
6495 22:16:50.962252 DQM Delay:
6496 22:16:50.962317 DQM0 = 14, DQM1 = 14
6497 22:16:50.965557 DQ Delay:
6498 22:16:50.968945 DQ0 =12, DQ1 =16, DQ2 =12, DQ3 =12
6499 22:16:50.971876 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6500 22:16:50.975039 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6501 22:16:50.978328 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =20
6502 22:16:50.978409
6503 22:16:50.978472
6504 22:16:50.984906 [DQSOSCAuto] RK0, (LSB)MR18= 0x8281, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6505 22:16:50.988282 CH0 RK0: MR19=C0C, MR18=8281
6506 22:16:50.994953 CH0_RK0: MR19=0xC0C, MR18=0x8281, DQSOSC=393, MR23=63, INC=382, DEC=254
6507 22:16:50.995036 ==
6508 22:16:50.998194 Dram Type= 6, Freq= 0, CH_0, rank 1
6509 22:16:51.001543 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6510 22:16:51.001624 ==
6511 22:16:51.004843 [Gating] SW mode calibration
6512 22:16:51.011667 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6513 22:16:51.018014 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6514 22:16:51.021342 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6515 22:16:51.024918 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6516 22:16:51.031461 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6517 22:16:51.034698 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6518 22:16:51.038274 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6519 22:16:51.044443 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6520 22:16:51.047981 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6521 22:16:51.051330 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6522 22:16:51.057695 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6523 22:16:51.061129 Total UI for P1: 0, mck2ui 16
6524 22:16:51.064570 best dqsien dly found for B0: ( 0, 14, 24)
6525 22:16:51.068080 Total UI for P1: 0, mck2ui 16
6526 22:16:51.070941 best dqsien dly found for B1: ( 0, 14, 24)
6527 22:16:51.074411 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6528 22:16:51.077961 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6529 22:16:51.078043
6530 22:16:51.080968 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6531 22:16:51.084535 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6532 22:16:51.087306 [Gating] SW calibration Done
6533 22:16:51.087388 ==
6534 22:16:51.090722 Dram Type= 6, Freq= 0, CH_0, rank 1
6535 22:16:51.094240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6536 22:16:51.094326 ==
6537 22:16:51.097529 RX Vref Scan: 0
6538 22:16:51.097632
6539 22:16:51.100916 RX Vref 0 -> 0, step: 1
6540 22:16:51.101015
6541 22:16:51.101083 RX Delay -410 -> 252, step: 16
6542 22:16:51.107585 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6543 22:16:51.110959 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6544 22:16:51.114287 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6545 22:16:51.120706 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6546 22:16:51.124317 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6547 22:16:51.127235 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6548 22:16:51.130464 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6549 22:16:51.137252 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6550 22:16:51.140524 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6551 22:16:51.143760 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6552 22:16:51.147200 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6553 22:16:51.154020 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6554 22:16:51.156901 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6555 22:16:51.160577 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6556 22:16:51.163691 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6557 22:16:51.170401 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6558 22:16:51.170824 ==
6559 22:16:51.174042 Dram Type= 6, Freq= 0, CH_0, rank 1
6560 22:16:51.176715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6561 22:16:51.177185 ==
6562 22:16:51.177552 DQS Delay:
6563 22:16:51.180188 DQS0 = 59, DQS1 = 59
6564 22:16:51.180651 DQM Delay:
6565 22:16:51.183890 DQM0 = 16, DQM1 = 10
6566 22:16:51.184357 DQ Delay:
6567 22:16:51.186843 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6568 22:16:51.190189 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6569 22:16:51.193646 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6570 22:16:51.196842 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6571 22:16:51.197317
6572 22:16:51.197657
6573 22:16:51.197971 ==
6574 22:16:51.200408 Dram Type= 6, Freq= 0, CH_0, rank 1
6575 22:16:51.203240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6576 22:16:51.206944 ==
6577 22:16:51.207417
6578 22:16:51.207807
6579 22:16:51.208127 TX Vref Scan disable
6580 22:16:51.210105 == TX Byte 0 ==
6581 22:16:51.213266 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6582 22:16:51.216478 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6583 22:16:51.219860 == TX Byte 1 ==
6584 22:16:51.223087 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6585 22:16:51.226041 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6586 22:16:51.226337 ==
6587 22:16:51.229424 Dram Type= 6, Freq= 0, CH_0, rank 1
6588 22:16:51.236136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6589 22:16:51.236358 ==
6590 22:16:51.236546
6591 22:16:51.236737
6592 22:16:51.236989 TX Vref Scan disable
6593 22:16:51.239217 == TX Byte 0 ==
6594 22:16:51.242922 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6595 22:16:51.245714 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6596 22:16:51.249394 == TX Byte 1 ==
6597 22:16:51.252880 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6598 22:16:51.256276 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6599 22:16:51.256502
6600 22:16:51.259093 [DATLAT]
6601 22:16:51.259315 Freq=400, CH0 RK1
6602 22:16:51.259493
6603 22:16:51.262538 DATLAT Default: 0xe
6604 22:16:51.262763 0, 0xFFFF, sum = 0
6605 22:16:51.266016 1, 0xFFFF, sum = 0
6606 22:16:51.266438 2, 0xFFFF, sum = 0
6607 22:16:51.269433 3, 0xFFFF, sum = 0
6608 22:16:51.269853 4, 0xFFFF, sum = 0
6609 22:16:51.272803 5, 0xFFFF, sum = 0
6610 22:16:51.273226 6, 0xFFFF, sum = 0
6611 22:16:51.275891 7, 0xFFFF, sum = 0
6612 22:16:51.276314 8, 0xFFFF, sum = 0
6613 22:16:51.279433 9, 0xFFFF, sum = 0
6614 22:16:51.282830 10, 0xFFFF, sum = 0
6615 22:16:51.283389 11, 0xFFFF, sum = 0
6616 22:16:51.285851 12, 0xFFFF, sum = 0
6617 22:16:51.286319 13, 0x0, sum = 1
6618 22:16:51.289346 14, 0x0, sum = 2
6619 22:16:51.289922 15, 0x0, sum = 3
6620 22:16:51.290298 16, 0x0, sum = 4
6621 22:16:51.292687 best_step = 14
6622 22:16:51.293147
6623 22:16:51.293515 ==
6624 22:16:51.296071 Dram Type= 6, Freq= 0, CH_0, rank 1
6625 22:16:51.299181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6626 22:16:51.299679 ==
6627 22:16:51.302601 RX Vref Scan: 0
6628 22:16:51.303059
6629 22:16:51.305715 RX Vref 0 -> 0, step: 1
6630 22:16:51.306176
6631 22:16:51.306543 RX Delay -359 -> 252, step: 8
6632 22:16:51.314514 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6633 22:16:51.317500 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6634 22:16:51.320650 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6635 22:16:51.324540 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6636 22:16:51.331200 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6637 22:16:51.334239 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6638 22:16:51.337731 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6639 22:16:51.340999 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6640 22:16:51.347569 iDelay=217, Bit 8, Center -60 (-311 ~ 192) 504
6641 22:16:51.350473 iDelay=217, Bit 9, Center -68 (-319 ~ 184) 504
6642 22:16:51.354316 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6643 22:16:51.360247 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6644 22:16:51.363636 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6645 22:16:51.366595 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6646 22:16:51.370375 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6647 22:16:51.376760 iDelay=217, Bit 15, Center -44 (-295 ~ 208) 504
6648 22:16:51.377011 ==
6649 22:16:51.379817 Dram Type= 6, Freq= 0, CH_0, rank 1
6650 22:16:51.383341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6651 22:16:51.383624 ==
6652 22:16:51.386689 DQS Delay:
6653 22:16:51.386915 DQS0 = 60, DQS1 = 68
6654 22:16:51.387147 DQM Delay:
6655 22:16:51.389597 DQM0 = 12, DQM1 = 15
6656 22:16:51.389839 DQ Delay:
6657 22:16:51.392987 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6658 22:16:51.396142 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6659 22:16:51.399541 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6660 22:16:51.402982 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6661 22:16:51.403210
6662 22:16:51.403400
6663 22:16:51.413160 [DQSOSCAuto] RK1, (LSB)MR18= 0xcd82, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 384 ps
6664 22:16:51.413444 CH0 RK1: MR19=C0C, MR18=CD82
6665 22:16:51.419219 CH0_RK1: MR19=0xC0C, MR18=0xCD82, DQSOSC=384, MR23=63, INC=400, DEC=267
6666 22:16:51.422703 [RxdqsGatingPostProcess] freq 400
6667 22:16:51.429341 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6668 22:16:51.433068 best DQS0 dly(2T, 0.5T) = (0, 10)
6669 22:16:51.435998 best DQS1 dly(2T, 0.5T) = (0, 10)
6670 22:16:51.439532 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6671 22:16:51.442395 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6672 22:16:51.446191 best DQS0 dly(2T, 0.5T) = (0, 10)
6673 22:16:51.446476 best DQS1 dly(2T, 0.5T) = (0, 10)
6674 22:16:51.449382 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6675 22:16:51.452336 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6676 22:16:51.455622 Pre-setting of DQS Precalculation
6677 22:16:51.462315 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6678 22:16:51.462425 ==
6679 22:16:51.465340 Dram Type= 6, Freq= 0, CH_1, rank 0
6680 22:16:51.469168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6681 22:16:51.469269 ==
6682 22:16:51.475274 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6683 22:16:51.481970 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6684 22:16:51.485381 [CA 0] Center 36 (8~64) winsize 57
6685 22:16:51.488377 [CA 1] Center 36 (8~64) winsize 57
6686 22:16:51.491831 [CA 2] Center 36 (8~64) winsize 57
6687 22:16:51.495186 [CA 3] Center 36 (8~64) winsize 57
6688 22:16:51.495262 [CA 4] Center 36 (8~64) winsize 57
6689 22:16:51.498186 [CA 5] Center 36 (8~64) winsize 57
6690 22:16:51.498282
6691 22:16:51.505141 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6692 22:16:51.505240
6693 22:16:51.508198 [CATrainingPosCal] consider 1 rank data
6694 22:16:51.511863 u2DelayCellTimex100 = 270/100 ps
6695 22:16:51.514673 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6696 22:16:51.517899 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6697 22:16:51.521405 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6698 22:16:51.524719 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6699 22:16:51.527771 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6700 22:16:51.530940 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6701 22:16:51.531050
6702 22:16:51.534557 CA PerBit enable=1, Macro0, CA PI delay=36
6703 22:16:51.534669
6704 22:16:51.537865 [CBTSetCACLKResult] CA Dly = 36
6705 22:16:51.541155 CS Dly: 1 (0~32)
6706 22:16:51.541261 ==
6707 22:16:51.544298 Dram Type= 6, Freq= 0, CH_1, rank 1
6708 22:16:51.547644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6709 22:16:51.547718 ==
6710 22:16:51.554276 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6711 22:16:51.560773 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6712 22:16:51.564021 [CA 0] Center 36 (8~64) winsize 57
6713 22:16:51.567181 [CA 1] Center 36 (8~64) winsize 57
6714 22:16:51.570414 [CA 2] Center 36 (8~64) winsize 57
6715 22:16:51.570517 [CA 3] Center 36 (8~64) winsize 57
6716 22:16:51.573741 [CA 4] Center 36 (8~64) winsize 57
6717 22:16:51.577510 [CA 5] Center 36 (8~64) winsize 57
6718 22:16:51.577616
6719 22:16:51.584215 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6720 22:16:51.584309
6721 22:16:51.586929 [CATrainingPosCal] consider 2 rank data
6722 22:16:51.590796 u2DelayCellTimex100 = 270/100 ps
6723 22:16:51.593533 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6724 22:16:51.597051 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6725 22:16:51.600493 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6726 22:16:51.603366 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6727 22:16:51.606785 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6728 22:16:51.610189 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6729 22:16:51.610301
6730 22:16:51.613767 CA PerBit enable=1, Macro0, CA PI delay=36
6731 22:16:51.613870
6732 22:16:51.616539 [CBTSetCACLKResult] CA Dly = 36
6733 22:16:51.620173 CS Dly: 1 (0~32)
6734 22:16:51.620277
6735 22:16:51.623503 ----->DramcWriteLeveling(PI) begin...
6736 22:16:51.623649 ==
6737 22:16:51.626463 Dram Type= 6, Freq= 0, CH_1, rank 0
6738 22:16:51.629880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6739 22:16:51.629978 ==
6740 22:16:51.633194 Write leveling (Byte 0): 40 => 8
6741 22:16:51.636344 Write leveling (Byte 1): 40 => 8
6742 22:16:51.640131 DramcWriteLeveling(PI) end<-----
6743 22:16:51.640214
6744 22:16:51.640278 ==
6745 22:16:51.643241 Dram Type= 6, Freq= 0, CH_1, rank 0
6746 22:16:51.646577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6747 22:16:51.646675 ==
6748 22:16:51.649739 [Gating] SW mode calibration
6749 22:16:51.656394 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6750 22:16:51.663162 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6751 22:16:51.666312 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6752 22:16:51.672905 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6753 22:16:51.676236 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6754 22:16:51.679256 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6755 22:16:51.685825 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6756 22:16:51.689436 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6757 22:16:51.692627 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6758 22:16:51.699025 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6759 22:16:51.702591 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6760 22:16:51.705472 Total UI for P1: 0, mck2ui 16
6761 22:16:51.708938 best dqsien dly found for B0: ( 0, 14, 24)
6762 22:16:51.712502 Total UI for P1: 0, mck2ui 16
6763 22:16:51.715487 best dqsien dly found for B1: ( 0, 14, 24)
6764 22:16:51.718793 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6765 22:16:51.722479 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6766 22:16:51.722560
6767 22:16:51.725831 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6768 22:16:51.728718 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6769 22:16:51.732260 [Gating] SW calibration Done
6770 22:16:51.732342 ==
6771 22:16:51.736541 Dram Type= 6, Freq= 0, CH_1, rank 0
6772 22:16:51.738967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6773 22:16:51.741978 ==
6774 22:16:51.742060 RX Vref Scan: 0
6775 22:16:51.742125
6776 22:16:51.745588 RX Vref 0 -> 0, step: 1
6777 22:16:51.745669
6778 22:16:51.748886 RX Delay -410 -> 252, step: 16
6779 22:16:51.752131 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6780 22:16:51.755491 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6781 22:16:51.758315 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6782 22:16:51.764838 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6783 22:16:51.768563 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6784 22:16:51.771887 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6785 22:16:51.774871 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6786 22:16:51.781656 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6787 22:16:51.785127 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6788 22:16:51.788063 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6789 22:16:51.794882 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6790 22:16:51.797875 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6791 22:16:51.801162 iDelay=230, Bit 12, Center -35 (-298 ~ 229) 528
6792 22:16:51.804403 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6793 22:16:51.811004 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6794 22:16:51.814630 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6795 22:16:51.814712 ==
6796 22:16:51.817551 Dram Type= 6, Freq= 0, CH_1, rank 0
6797 22:16:51.821188 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6798 22:16:51.821271 ==
6799 22:16:51.824616 DQS Delay:
6800 22:16:51.824698 DQS0 = 51, DQS1 = 67
6801 22:16:51.827842 DQM Delay:
6802 22:16:51.827924 DQM0 = 13, DQM1 = 18
6803 22:16:51.827988 DQ Delay:
6804 22:16:51.830661 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6805 22:16:51.834118 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6806 22:16:51.837195 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6807 22:16:51.840529 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =24
6808 22:16:51.840610
6809 22:16:51.840675
6810 22:16:51.840774 ==
6811 22:16:51.843965 Dram Type= 6, Freq= 0, CH_1, rank 0
6812 22:16:51.850678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6813 22:16:51.850760 ==
6814 22:16:51.850824
6815 22:16:51.850884
6816 22:16:51.850944 TX Vref Scan disable
6817 22:16:51.853818 == TX Byte 0 ==
6818 22:16:51.857224 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6819 22:16:51.860254 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6820 22:16:51.863764 == TX Byte 1 ==
6821 22:16:51.867411 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6822 22:16:51.870712 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6823 22:16:51.873925 ==
6824 22:16:51.877116 Dram Type= 6, Freq= 0, CH_1, rank 0
6825 22:16:51.879995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6826 22:16:51.880077 ==
6827 22:16:51.880142
6828 22:16:51.880203
6829 22:16:51.883429 TX Vref Scan disable
6830 22:16:51.883510 == TX Byte 0 ==
6831 22:16:51.887121 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6832 22:16:51.893406 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6833 22:16:51.893487 == TX Byte 1 ==
6834 22:16:51.896583 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6835 22:16:51.903508 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6836 22:16:51.903617
6837 22:16:51.903697 [DATLAT]
6838 22:16:51.903758 Freq=400, CH1 RK0
6839 22:16:51.903816
6840 22:16:51.907048 DATLAT Default: 0xf
6841 22:16:51.907129 0, 0xFFFF, sum = 0
6842 22:16:51.909820 1, 0xFFFF, sum = 0
6843 22:16:51.913459 2, 0xFFFF, sum = 0
6844 22:16:51.913543 3, 0xFFFF, sum = 0
6845 22:16:51.917051 4, 0xFFFF, sum = 0
6846 22:16:51.917135 5, 0xFFFF, sum = 0
6847 22:16:51.920310 6, 0xFFFF, sum = 0
6848 22:16:51.920393 7, 0xFFFF, sum = 0
6849 22:16:51.923382 8, 0xFFFF, sum = 0
6850 22:16:51.923467 9, 0xFFFF, sum = 0
6851 22:16:51.927037 10, 0xFFFF, sum = 0
6852 22:16:51.927123 11, 0xFFFF, sum = 0
6853 22:16:51.929807 12, 0xFFFF, sum = 0
6854 22:16:51.929893 13, 0x0, sum = 1
6855 22:16:51.933347 14, 0x0, sum = 2
6856 22:16:51.933433 15, 0x0, sum = 3
6857 22:16:51.936368 16, 0x0, sum = 4
6858 22:16:51.936455 best_step = 14
6859 22:16:51.936539
6860 22:16:51.936619 ==
6861 22:16:51.939938 Dram Type= 6, Freq= 0, CH_1, rank 0
6862 22:16:51.942874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6863 22:16:51.946264 ==
6864 22:16:51.946349 RX Vref Scan: 1
6865 22:16:51.946435
6866 22:16:51.950006 RX Vref 0 -> 0, step: 1
6867 22:16:51.950091
6868 22:16:51.952944 RX Delay -375 -> 252, step: 8
6869 22:16:51.953029
6870 22:16:51.956474 Set Vref, RX VrefLevel [Byte0]: 55
6871 22:16:51.959814 [Byte1]: 50
6872 22:16:51.959899
6873 22:16:51.963050 Final RX Vref Byte 0 = 55 to rank0
6874 22:16:51.966115 Final RX Vref Byte 1 = 50 to rank0
6875 22:16:51.969984 Final RX Vref Byte 0 = 55 to rank1
6876 22:16:51.972760 Final RX Vref Byte 1 = 50 to rank1==
6877 22:16:51.975848 Dram Type= 6, Freq= 0, CH_1, rank 0
6878 22:16:51.979254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6879 22:16:51.982974 ==
6880 22:16:51.983056 DQS Delay:
6881 22:16:51.983122 DQS0 = 52, DQS1 = 64
6882 22:16:51.986218 DQM Delay:
6883 22:16:51.986300 DQM0 = 9, DQM1 = 11
6884 22:16:51.989037 DQ Delay:
6885 22:16:51.989119 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6886 22:16:51.992526 DQ4 =8, DQ5 =16, DQ6 =20, DQ7 =8
6887 22:16:51.996134 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6888 22:16:51.998998 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6889 22:16:51.999080
6890 22:16:51.999144
6891 22:16:52.008991 [DQSOSCAuto] RK0, (LSB)MR18= 0x576a, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 398 ps
6892 22:16:52.012045 CH1 RK0: MR19=C0C, MR18=576A
6893 22:16:52.018698 CH1_RK0: MR19=0xC0C, MR18=0x576A, DQSOSC=396, MR23=63, INC=376, DEC=251
6894 22:16:52.018792 ==
6895 22:16:52.021991 Dram Type= 6, Freq= 0, CH_1, rank 1
6896 22:16:52.025360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6897 22:16:52.025443 ==
6898 22:16:52.029049 [Gating] SW mode calibration
6899 22:16:52.035406 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6900 22:16:52.042056 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6901 22:16:52.045171 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6902 22:16:52.048615 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6903 22:16:52.054863 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6904 22:16:52.058466 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6905 22:16:52.061722 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6906 22:16:52.068244 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6907 22:16:52.071526 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6908 22:16:52.074879 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6909 22:16:52.081629 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6910 22:16:52.081712 Total UI for P1: 0, mck2ui 16
6911 22:16:52.084745 best dqsien dly found for B0: ( 0, 14, 24)
6912 22:16:52.088474 Total UI for P1: 0, mck2ui 16
6913 22:16:52.091212 best dqsien dly found for B1: ( 0, 14, 24)
6914 22:16:52.098231 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6915 22:16:52.101237 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6916 22:16:52.101320
6917 22:16:52.104774 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6918 22:16:52.107911 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6919 22:16:52.111305 [Gating] SW calibration Done
6920 22:16:52.111388 ==
6921 22:16:52.114741 Dram Type= 6, Freq= 0, CH_1, rank 1
6922 22:16:52.117590 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6923 22:16:52.117673 ==
6924 22:16:52.120995 RX Vref Scan: 0
6925 22:16:52.121077
6926 22:16:52.121142 RX Vref 0 -> 0, step: 1
6927 22:16:52.121201
6928 22:16:52.124572 RX Delay -410 -> 252, step: 16
6929 22:16:52.131281 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6930 22:16:52.134244 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6931 22:16:52.137726 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6932 22:16:52.140946 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6933 22:16:52.147431 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6934 22:16:52.150831 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6935 22:16:52.154523 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6936 22:16:52.157259 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6937 22:16:52.163899 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6938 22:16:52.167182 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6939 22:16:52.170417 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6940 22:16:52.174276 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6941 22:16:52.180712 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6942 22:16:52.183595 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6943 22:16:52.186805 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6944 22:16:52.193374 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6945 22:16:52.193457 ==
6946 22:16:52.196772 Dram Type= 6, Freq= 0, CH_1, rank 1
6947 22:16:52.200260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6948 22:16:52.200343 ==
6949 22:16:52.200442 DQS Delay:
6950 22:16:52.203127 DQS0 = 59, DQS1 = 59
6951 22:16:52.203210 DQM Delay:
6952 22:16:52.206784 DQM0 = 19, DQM1 = 13
6953 22:16:52.206896 DQ Delay:
6954 22:16:52.209615 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6955 22:16:52.212916 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6956 22:16:52.216313 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6957 22:16:52.219768 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =16
6958 22:16:52.219851
6959 22:16:52.219916
6960 22:16:52.219975 ==
6961 22:16:52.222966 Dram Type= 6, Freq= 0, CH_1, rank 1
6962 22:16:52.226425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6963 22:16:52.226508 ==
6964 22:16:52.226573
6965 22:16:52.230157
6966 22:16:52.230239 TX Vref Scan disable
6967 22:16:52.233217 == TX Byte 0 ==
6968 22:16:52.236299 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6969 22:16:52.239819 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6970 22:16:52.243140 == TX Byte 1 ==
6971 22:16:52.246404 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6972 22:16:52.249426 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6973 22:16:52.249509 ==
6974 22:16:52.252861 Dram Type= 6, Freq= 0, CH_1, rank 1
6975 22:16:52.255884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6976 22:16:52.259418 ==
6977 22:16:52.259500
6978 22:16:52.259566
6979 22:16:52.259641 TX Vref Scan disable
6980 22:16:52.262825 == TX Byte 0 ==
6981 22:16:52.265923 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6982 22:16:52.269439 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6983 22:16:52.272719 == TX Byte 1 ==
6984 22:16:52.275538 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6985 22:16:52.279528 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6986 22:16:52.279667
6987 22:16:52.282283 [DATLAT]
6988 22:16:52.282365 Freq=400, CH1 RK1
6989 22:16:52.282431
6990 22:16:52.285614 DATLAT Default: 0xe
6991 22:16:52.285697 0, 0xFFFF, sum = 0
6992 22:16:52.288976 1, 0xFFFF, sum = 0
6993 22:16:52.289059 2, 0xFFFF, sum = 0
6994 22:16:52.292297 3, 0xFFFF, sum = 0
6995 22:16:52.292381 4, 0xFFFF, sum = 0
6996 22:16:52.295499 5, 0xFFFF, sum = 0
6997 22:16:52.295588 6, 0xFFFF, sum = 0
6998 22:16:52.298603 7, 0xFFFF, sum = 0
6999 22:16:52.298687 8, 0xFFFF, sum = 0
7000 22:16:52.302122 9, 0xFFFF, sum = 0
7001 22:16:52.302205 10, 0xFFFF, sum = 0
7002 22:16:52.305592 11, 0xFFFF, sum = 0
7003 22:16:52.308908 12, 0xFFFF, sum = 0
7004 22:16:52.308991 13, 0x0, sum = 1
7005 22:16:52.309058 14, 0x0, sum = 2
7006 22:16:52.311661 15, 0x0, sum = 3
7007 22:16:52.311745 16, 0x0, sum = 4
7008 22:16:52.315493 best_step = 14
7009 22:16:52.315575
7010 22:16:52.315686 ==
7011 22:16:52.318308 Dram Type= 6, Freq= 0, CH_1, rank 1
7012 22:16:52.322137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7013 22:16:52.322220 ==
7014 22:16:52.324928 RX Vref Scan: 0
7015 22:16:52.325010
7016 22:16:52.328389 RX Vref 0 -> 0, step: 1
7017 22:16:52.328472
7018 22:16:52.328535 RX Delay -359 -> 252, step: 8
7019 22:16:52.336918 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
7020 22:16:52.340315 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
7021 22:16:52.343763 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
7022 22:16:52.350014 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
7023 22:16:52.353574 iDelay=217, Bit 4, Center -44 (-295 ~ 208) 504
7024 22:16:52.356458 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
7025 22:16:52.360081 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
7026 22:16:52.366529 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
7027 22:16:52.369985 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
7028 22:16:52.372949 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
7029 22:16:52.376206 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
7030 22:16:52.382862 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
7031 22:16:52.386185 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
7032 22:16:52.389593 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
7033 22:16:52.392890 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
7034 22:16:52.399321 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
7035 22:16:52.399404 ==
7036 22:16:52.402692 Dram Type= 6, Freq= 0, CH_1, rank 1
7037 22:16:52.406329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7038 22:16:52.406413 ==
7039 22:16:52.406479 DQS Delay:
7040 22:16:52.409301 DQS0 = 60, DQS1 = 64
7041 22:16:52.409383 DQM Delay:
7042 22:16:52.412841 DQM0 = 13, DQM1 = 10
7043 22:16:52.412923 DQ Delay:
7044 22:16:52.416303 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7045 22:16:52.419227 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
7046 22:16:52.422730 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
7047 22:16:52.426163 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
7048 22:16:52.426246
7049 22:16:52.426310
7050 22:16:52.436026 [DQSOSCAuto] RK1, (LSB)MR18= 0x79ab, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 394 ps
7051 22:16:52.436113 CH1 RK1: MR19=C0C, MR18=79AB
7052 22:16:52.442209 CH1_RK1: MR19=0xC0C, MR18=0x79AB, DQSOSC=388, MR23=63, INC=392, DEC=261
7053 22:16:52.445835 [RxdqsGatingPostProcess] freq 400
7054 22:16:52.452510 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7055 22:16:52.455930 best DQS0 dly(2T, 0.5T) = (0, 10)
7056 22:16:52.458704 best DQS1 dly(2T, 0.5T) = (0, 10)
7057 22:16:52.462199 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7058 22:16:52.465190 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7059 22:16:52.468670 best DQS0 dly(2T, 0.5T) = (0, 10)
7060 22:16:52.468744 best DQS1 dly(2T, 0.5T) = (0, 10)
7061 22:16:52.471725 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7062 22:16:52.475107 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7063 22:16:52.478526 Pre-setting of DQS Precalculation
7064 22:16:52.485031 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7065 22:16:52.492265 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7066 22:16:52.498367 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7067 22:16:52.498452
7068 22:16:52.498517
7069 22:16:52.502276 [Calibration Summary] 800 Mbps
7070 22:16:52.505065 CH 0, Rank 0
7071 22:16:52.505134 SW Impedance : PASS
7072 22:16:52.508231 DUTY Scan : NO K
7073 22:16:52.508320 ZQ Calibration : PASS
7074 22:16:52.511648 Jitter Meter : NO K
7075 22:16:52.514945 CBT Training : PASS
7076 22:16:52.515016 Write leveling : PASS
7077 22:16:52.518489 RX DQS gating : PASS
7078 22:16:52.521884 RX DQ/DQS(RDDQC) : PASS
7079 22:16:52.521953 TX DQ/DQS : PASS
7080 22:16:52.524708 RX DATLAT : PASS
7081 22:16:52.528302 RX DQ/DQS(Engine): PASS
7082 22:16:52.528381 TX OE : NO K
7083 22:16:52.531315 All Pass.
7084 22:16:52.531383
7085 22:16:52.531451 CH 0, Rank 1
7086 22:16:52.534468 SW Impedance : PASS
7087 22:16:52.534542 DUTY Scan : NO K
7088 22:16:52.538072 ZQ Calibration : PASS
7089 22:16:52.541602 Jitter Meter : NO K
7090 22:16:52.541673 CBT Training : PASS
7091 22:16:52.544573 Write leveling : NO K
7092 22:16:52.547958 RX DQS gating : PASS
7093 22:16:52.548027 RX DQ/DQS(RDDQC) : PASS
7094 22:16:52.551211 TX DQ/DQS : PASS
7095 22:16:52.554829 RX DATLAT : PASS
7096 22:16:52.554909 RX DQ/DQS(Engine): PASS
7097 22:16:52.557650 TX OE : NO K
7098 22:16:52.557726 All Pass.
7099 22:16:52.557786
7100 22:16:52.561116 CH 1, Rank 0
7101 22:16:52.561196 SW Impedance : PASS
7102 22:16:52.564596 DUTY Scan : NO K
7103 22:16:52.567520 ZQ Calibration : PASS
7104 22:16:52.567595 Jitter Meter : NO K
7105 22:16:52.570942 CBT Training : PASS
7106 22:16:52.574684 Write leveling : PASS
7107 22:16:52.574751 RX DQS gating : PASS
7108 22:16:52.577578 RX DQ/DQS(RDDQC) : PASS
7109 22:16:52.577664 TX DQ/DQS : PASS
7110 22:16:52.580853 RX DATLAT : PASS
7111 22:16:52.584178 RX DQ/DQS(Engine): PASS
7112 22:16:52.584271 TX OE : NO K
7113 22:16:52.587881 All Pass.
7114 22:16:52.587981
7115 22:16:52.588061 CH 1, Rank 1
7116 22:16:52.590968 SW Impedance : PASS
7117 22:16:52.591068 DUTY Scan : NO K
7118 22:16:52.594614 ZQ Calibration : PASS
7119 22:16:52.597528 Jitter Meter : NO K
7120 22:16:52.597720 CBT Training : PASS
7121 22:16:52.600834 Write leveling : NO K
7122 22:16:52.604385 RX DQS gating : PASS
7123 22:16:52.604534 RX DQ/DQS(RDDQC) : PASS
7124 22:16:52.607279 TX DQ/DQS : PASS
7125 22:16:52.610876 RX DATLAT : PASS
7126 22:16:52.611496 RX DQ/DQS(Engine): PASS
7127 22:16:52.614671 TX OE : NO K
7128 22:16:52.615143 All Pass.
7129 22:16:52.615504
7130 22:16:52.617614 DramC Write-DBI off
7131 22:16:52.621132 PER_BANK_REFRESH: Hybrid Mode
7132 22:16:52.621599 TX_TRACKING: ON
7133 22:16:52.630795 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7134 22:16:52.634211 [FAST_K] Save calibration result to emmc
7135 22:16:52.637651 dramc_set_vcore_voltage set vcore to 725000
7136 22:16:52.640555 Read voltage for 1600, 0
7137 22:16:52.641021 Vio18 = 0
7138 22:16:52.641388 Vcore = 725000
7139 22:16:52.644012 Vdram = 0
7140 22:16:52.644475 Vddq = 0
7141 22:16:52.644843 Vmddr = 0
7142 22:16:52.651006 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7143 22:16:52.653899 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7144 22:16:52.657445 MEM_TYPE=3, freq_sel=13
7145 22:16:52.660766 sv_algorithm_assistance_LP4_3733
7146 22:16:52.663863 ============ PULL DRAM RESETB DOWN ============
7147 22:16:52.670630 ========== PULL DRAM RESETB DOWN end =========
7148 22:16:52.673531 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7149 22:16:52.677357 ===================================
7150 22:16:52.680152 LPDDR4 DRAM CONFIGURATION
7151 22:16:52.683739 ===================================
7152 22:16:52.684211 EX_ROW_EN[0] = 0x0
7153 22:16:52.687121 EX_ROW_EN[1] = 0x0
7154 22:16:52.687616 LP4Y_EN = 0x0
7155 22:16:52.690705 WORK_FSP = 0x1
7156 22:16:52.691172 WL = 0x5
7157 22:16:52.693583 RL = 0x5
7158 22:16:52.694009 BL = 0x2
7159 22:16:52.696622 RPST = 0x0
7160 22:16:52.699917 RD_PRE = 0x0
7161 22:16:52.700217 WR_PRE = 0x1
7162 22:16:52.703305 WR_PST = 0x1
7163 22:16:52.703626 DBI_WR = 0x0
7164 22:16:52.706318 DBI_RD = 0x0
7165 22:16:52.706546 OTF = 0x1
7166 22:16:52.710591 ===================================
7167 22:16:52.713114 ===================================
7168 22:16:52.716718 ANA top config
7169 22:16:52.719886 ===================================
7170 22:16:52.719969 DLL_ASYNC_EN = 0
7171 22:16:52.722873 ALL_SLAVE_EN = 0
7172 22:16:52.726098 NEW_RANK_MODE = 1
7173 22:16:52.729228 DLL_IDLE_MODE = 1
7174 22:16:52.729311 LP45_APHY_COMB_EN = 1
7175 22:16:52.732517 TX_ODT_DIS = 0
7176 22:16:52.735857 NEW_8X_MODE = 1
7177 22:16:52.739368 ===================================
7178 22:16:52.742859 ===================================
7179 22:16:52.745552 data_rate = 3200
7180 22:16:52.749171 CKR = 1
7181 22:16:52.752770 DQ_P2S_RATIO = 8
7182 22:16:52.755705 ===================================
7183 22:16:52.755788 CA_P2S_RATIO = 8
7184 22:16:52.758921 DQ_CA_OPEN = 0
7185 22:16:52.762077 DQ_SEMI_OPEN = 0
7186 22:16:52.765696 CA_SEMI_OPEN = 0
7187 22:16:52.768914 CA_FULL_RATE = 0
7188 22:16:52.772419 DQ_CKDIV4_EN = 0
7189 22:16:52.772502 CA_CKDIV4_EN = 0
7190 22:16:52.775250 CA_PREDIV_EN = 0
7191 22:16:52.778861 PH8_DLY = 12
7192 22:16:52.782289 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7193 22:16:52.785218 DQ_AAMCK_DIV = 4
7194 22:16:52.788954 CA_AAMCK_DIV = 4
7195 22:16:52.789036 CA_ADMCK_DIV = 4
7196 22:16:52.792079 DQ_TRACK_CA_EN = 0
7197 22:16:52.795292 CA_PICK = 1600
7198 22:16:52.798564 CA_MCKIO = 1600
7199 22:16:52.802244 MCKIO_SEMI = 0
7200 22:16:52.805161 PLL_FREQ = 3068
7201 22:16:52.808840 DQ_UI_PI_RATIO = 32
7202 22:16:52.812116 CA_UI_PI_RATIO = 0
7203 22:16:52.815148 ===================================
7204 22:16:52.818932 ===================================
7205 22:16:52.819016 memory_type:LPDDR4
7206 22:16:52.821694 GP_NUM : 10
7207 22:16:52.824987 SRAM_EN : 1
7208 22:16:52.825071 MD32_EN : 0
7209 22:16:52.828221 ===================================
7210 22:16:52.831564 [ANA_INIT] >>>>>>>>>>>>>>
7211 22:16:52.834645 <<<<<< [CONFIGURE PHASE]: ANA_TX
7212 22:16:52.838173 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7213 22:16:52.841383 ===================================
7214 22:16:52.844749 data_rate = 3200,PCW = 0X7600
7215 22:16:52.848149 ===================================
7216 22:16:52.851215 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7217 22:16:52.854732 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7218 22:16:52.861678 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7219 22:16:52.864539 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7220 22:16:52.867808 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7221 22:16:52.871199 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7222 22:16:52.874523 [ANA_INIT] flow start
7223 22:16:52.877957 [ANA_INIT] PLL >>>>>>>>
7224 22:16:52.878040 [ANA_INIT] PLL <<<<<<<<
7225 22:16:52.881143 [ANA_INIT] MIDPI >>>>>>>>
7226 22:16:52.884112 [ANA_INIT] MIDPI <<<<<<<<
7227 22:16:52.887426 [ANA_INIT] DLL >>>>>>>>
7228 22:16:52.887527 [ANA_INIT] DLL <<<<<<<<
7229 22:16:52.890887 [ANA_INIT] flow end
7230 22:16:52.894104 ============ LP4 DIFF to SE enter ============
7231 22:16:52.897403 ============ LP4 DIFF to SE exit ============
7232 22:16:52.900821 [ANA_INIT] <<<<<<<<<<<<<
7233 22:16:52.904246 [Flow] Enable top DCM control >>>>>
7234 22:16:52.907147 [Flow] Enable top DCM control <<<<<
7235 22:16:52.910660 Enable DLL master slave shuffle
7236 22:16:52.917155 ==============================================================
7237 22:16:52.917262 Gating Mode config
7238 22:16:52.923926 ==============================================================
7239 22:16:52.927328 Config description:
7240 22:16:52.933806 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7241 22:16:52.940378 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7242 22:16:52.947116 SELPH_MODE 0: By rank 1: By Phase
7243 22:16:52.953354 ==============================================================
7244 22:16:52.953437 GAT_TRACK_EN = 1
7245 22:16:52.956728 RX_GATING_MODE = 2
7246 22:16:52.960166 RX_GATING_TRACK_MODE = 2
7247 22:16:52.963299 SELPH_MODE = 1
7248 22:16:52.966549 PICG_EARLY_EN = 1
7249 22:16:52.970032 VALID_LAT_VALUE = 1
7250 22:16:52.976352 ==============================================================
7251 22:16:52.980146 Enter into Gating configuration >>>>
7252 22:16:52.983152 Exit from Gating configuration <<<<
7253 22:16:52.986556 Enter into DVFS_PRE_config >>>>>
7254 22:16:52.996410 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7255 22:16:52.999847 Exit from DVFS_PRE_config <<<<<
7256 22:16:53.003138 Enter into PICG configuration >>>>
7257 22:16:53.006623 Exit from PICG configuration <<<<
7258 22:16:53.009604 [RX_INPUT] configuration >>>>>
7259 22:16:53.013082 [RX_INPUT] configuration <<<<<
7260 22:16:53.016022 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7261 22:16:53.023034 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7262 22:16:53.029302 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7263 22:16:53.035859 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7264 22:16:53.039338 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7265 22:16:53.046117 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7266 22:16:53.049109 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7267 22:16:53.055681 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7268 22:16:53.058958 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7269 22:16:53.062266 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7270 22:16:53.065742 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7271 22:16:53.072006 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7272 22:16:53.075403 ===================================
7273 22:16:53.079019 LPDDR4 DRAM CONFIGURATION
7274 22:16:53.082104 ===================================
7275 22:16:53.082207 EX_ROW_EN[0] = 0x0
7276 22:16:53.085408 EX_ROW_EN[1] = 0x0
7277 22:16:53.085511 LP4Y_EN = 0x0
7278 22:16:53.089134 WORK_FSP = 0x1
7279 22:16:53.089232 WL = 0x5
7280 22:16:53.091648 RL = 0x5
7281 22:16:53.091730 BL = 0x2
7282 22:16:53.094944 RPST = 0x0
7283 22:16:53.095025 RD_PRE = 0x0
7284 22:16:53.098495 WR_PRE = 0x1
7285 22:16:53.098577 WR_PST = 0x1
7286 22:16:53.102182 DBI_WR = 0x0
7287 22:16:53.102264 DBI_RD = 0x0
7288 22:16:53.105115 OTF = 0x1
7289 22:16:53.108625 ===================================
7290 22:16:53.111909 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7291 22:16:53.114775 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7292 22:16:53.121303 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7293 22:16:53.124853 ===================================
7294 22:16:53.128112 LPDDR4 DRAM CONFIGURATION
7295 22:16:53.131498 ===================================
7296 22:16:53.131586 EX_ROW_EN[0] = 0x10
7297 22:16:53.135067 EX_ROW_EN[1] = 0x0
7298 22:16:53.135149 LP4Y_EN = 0x0
7299 22:16:53.138012 WORK_FSP = 0x1
7300 22:16:53.138094 WL = 0x5
7301 22:16:53.141341 RL = 0x5
7302 22:16:53.141423 BL = 0x2
7303 22:16:53.145013 RPST = 0x0
7304 22:16:53.145110 RD_PRE = 0x0
7305 22:16:53.148084 WR_PRE = 0x1
7306 22:16:53.148166 WR_PST = 0x1
7307 22:16:53.151412 DBI_WR = 0x0
7308 22:16:53.151494 DBI_RD = 0x0
7309 22:16:53.154743 OTF = 0x1
7310 22:16:53.157947 ===================================
7311 22:16:53.164450 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7312 22:16:53.164537 ==
7313 22:16:53.167756 Dram Type= 6, Freq= 0, CH_0, rank 0
7314 22:16:53.171006 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7315 22:16:53.171089 ==
7316 22:16:53.174539 [Duty_Offset_Calibration]
7317 22:16:53.174620 B0:2 B1:0 CA:3
7318 22:16:53.174685
7319 22:16:53.177992 [DutyScan_Calibration_Flow] k_type=0
7320 22:16:53.188796
7321 22:16:53.188879 ==CLK 0==
7322 22:16:53.192427 Final CLK duty delay cell = 0
7323 22:16:53.195351 [0] MAX Duty = 5031%(X100), DQS PI = 12
7324 22:16:53.199251 [0] MIN Duty = 4907%(X100), DQS PI = 2
7325 22:16:53.202227 [0] AVG Duty = 4969%(X100)
7326 22:16:53.202308
7327 22:16:53.205736 CH0 CLK Duty spec in!! Max-Min= 124%
7328 22:16:53.208852 [DutyScan_Calibration_Flow] ====Done====
7329 22:16:53.208934
7330 22:16:53.212610 [DutyScan_Calibration_Flow] k_type=1
7331 22:16:53.228827
7332 22:16:53.228910 ==DQS 0 ==
7333 22:16:53.232184 Final DQS duty delay cell = 0
7334 22:16:53.235131 [0] MAX Duty = 5125%(X100), DQS PI = 30
7335 22:16:53.238596 [0] MIN Duty = 4875%(X100), DQS PI = 50
7336 22:16:53.242127 [0] AVG Duty = 5000%(X100)
7337 22:16:53.242210
7338 22:16:53.242275 ==DQS 1 ==
7339 22:16:53.245210 Final DQS duty delay cell = 0
7340 22:16:53.248484 [0] MAX Duty = 5156%(X100), DQS PI = 32
7341 22:16:53.251930 [0] MIN Duty = 5031%(X100), DQS PI = 14
7342 22:16:53.255338 [0] AVG Duty = 5093%(X100)
7343 22:16:53.255418
7344 22:16:53.258173 CH0 DQS 0 Duty spec in!! Max-Min= 250%
7345 22:16:53.258253
7346 22:16:53.261890 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7347 22:16:53.265081 [DutyScan_Calibration_Flow] ====Done====
7348 22:16:53.265171
7349 22:16:53.268503 [DutyScan_Calibration_Flow] k_type=3
7350 22:16:53.286562
7351 22:16:53.286663 ==DQM 0 ==
7352 22:16:53.289953 Final DQM duty delay cell = 0
7353 22:16:53.293246 [0] MAX Duty = 5156%(X100), DQS PI = 30
7354 22:16:53.296558 [0] MIN Duty = 4875%(X100), DQS PI = 0
7355 22:16:53.299793 [0] AVG Duty = 5015%(X100)
7356 22:16:53.299869
7357 22:16:53.299938 ==DQM 1 ==
7358 22:16:53.303086 Final DQM duty delay cell = 4
7359 22:16:53.306443 [4] MAX Duty = 5187%(X100), DQS PI = 60
7360 22:16:53.309905 [4] MIN Duty = 5000%(X100), DQS PI = 28
7361 22:16:53.313482 [4] AVG Duty = 5093%(X100)
7362 22:16:53.313565
7363 22:16:53.316179 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7364 22:16:53.316268
7365 22:16:53.319731 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7366 22:16:53.323644 [DutyScan_Calibration_Flow] ====Done====
7367 22:16:53.323818
7368 22:16:53.326389 [DutyScan_Calibration_Flow] k_type=2
7369 22:16:53.343393
7370 22:16:53.344372 ==DQ 0 ==
7371 22:16:53.346358 Final DQ duty delay cell = -4
7372 22:16:53.349539 [-4] MAX Duty = 5000%(X100), DQS PI = 14
7373 22:16:53.353006 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7374 22:16:53.356606 [-4] AVG Duty = 4938%(X100)
7375 22:16:53.357184
7376 22:16:53.357656 ==DQ 1 ==
7377 22:16:53.359749 Final DQ duty delay cell = 0
7378 22:16:53.363040 [0] MAX Duty = 5156%(X100), DQS PI = 60
7379 22:16:53.366138 [0] MIN Duty = 5000%(X100), DQS PI = 16
7380 22:16:53.369381 [0] AVG Duty = 5078%(X100)
7381 22:16:53.369838
7382 22:16:53.372477 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7383 22:16:53.372937
7384 22:16:53.376123 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7385 22:16:53.379339 [DutyScan_Calibration_Flow] ====Done====
7386 22:16:53.379942 ==
7387 22:16:53.382482 Dram Type= 6, Freq= 0, CH_1, rank 0
7388 22:16:53.385701 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7389 22:16:53.386327 ==
7390 22:16:53.389228 [Duty_Offset_Calibration]
7391 22:16:53.389685 B0:1 B1:-2 CA:1
7392 22:16:53.392294
7393 22:16:53.395774 [DutyScan_Calibration_Flow] k_type=0
7394 22:16:53.403718
7395 22:16:53.404174 ==CLK 0==
7396 22:16:53.406829 Final CLK duty delay cell = 0
7397 22:16:53.410199 [0] MAX Duty = 5094%(X100), DQS PI = 22
7398 22:16:53.413344 [0] MIN Duty = 4813%(X100), DQS PI = 60
7399 22:16:53.416774 [0] AVG Duty = 4953%(X100)
7400 22:16:53.416999
7401 22:16:53.420010 CH1 CLK Duty spec in!! Max-Min= 281%
7402 22:16:53.422846 [DutyScan_Calibration_Flow] ====Done====
7403 22:16:53.422928
7404 22:16:53.426217 [DutyScan_Calibration_Flow] k_type=1
7405 22:16:53.441934
7406 22:16:53.442015 ==DQS 0 ==
7407 22:16:53.445327 Final DQS duty delay cell = -4
7408 22:16:53.448849 [-4] MAX Duty = 4969%(X100), DQS PI = 24
7409 22:16:53.451739 [-4] MIN Duty = 4844%(X100), DQS PI = 46
7410 22:16:53.454976 [-4] AVG Duty = 4906%(X100)
7411 22:16:53.455057
7412 22:16:53.455120 ==DQS 1 ==
7413 22:16:53.458533 Final DQS duty delay cell = 0
7414 22:16:53.461545 [0] MAX Duty = 5093%(X100), DQS PI = 58
7415 22:16:53.465399 [0] MIN Duty = 4844%(X100), DQS PI = 24
7416 22:16:53.468449 [0] AVG Duty = 4968%(X100)
7417 22:16:53.468529
7418 22:16:53.471679 CH1 DQS 0 Duty spec in!! Max-Min= 125%
7419 22:16:53.471784
7420 22:16:53.475199 CH1 DQS 1 Duty spec in!! Max-Min= 249%
7421 22:16:53.478232 [DutyScan_Calibration_Flow] ====Done====
7422 22:16:53.478313
7423 22:16:53.481687 [DutyScan_Calibration_Flow] k_type=3
7424 22:16:53.499348
7425 22:16:53.499428 ==DQM 0 ==
7426 22:16:53.502743 Final DQM duty delay cell = 0
7427 22:16:53.506155 [0] MAX Duty = 5031%(X100), DQS PI = 24
7428 22:16:53.508979 [0] MIN Duty = 4813%(X100), DQS PI = 54
7429 22:16:53.512306 [0] AVG Duty = 4922%(X100)
7430 22:16:53.512388
7431 22:16:53.512452 ==DQM 1 ==
7432 22:16:53.515528 Final DQM duty delay cell = 0
7433 22:16:53.518980 [0] MAX Duty = 5062%(X100), DQS PI = 34
7434 22:16:53.522115 [0] MIN Duty = 4875%(X100), DQS PI = 24
7435 22:16:53.525465 [0] AVG Duty = 4968%(X100)
7436 22:16:53.525545
7437 22:16:53.529229 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7438 22:16:53.529310
7439 22:16:53.532165 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7440 22:16:53.535588 [DutyScan_Calibration_Flow] ====Done====
7441 22:16:53.535700
7442 22:16:53.538673 [DutyScan_Calibration_Flow] k_type=2
7443 22:16:53.556370
7444 22:16:53.556451 ==DQ 0 ==
7445 22:16:53.559426 Final DQ duty delay cell = 0
7446 22:16:53.562944 [0] MAX Duty = 5093%(X100), DQS PI = 20
7447 22:16:53.565904 [0] MIN Duty = 4907%(X100), DQS PI = 60
7448 22:16:53.569270 [0] AVG Duty = 5000%(X100)
7449 22:16:53.569352
7450 22:16:53.569417 ==DQ 1 ==
7451 22:16:53.572236 Final DQ duty delay cell = 0
7452 22:16:53.575494 [0] MAX Duty = 5156%(X100), DQS PI = 34
7453 22:16:53.579188 [0] MIN Duty = 4969%(X100), DQS PI = 24
7454 22:16:53.582140 [0] AVG Duty = 5062%(X100)
7455 22:16:53.582246
7456 22:16:53.585570 CH1 DQ 0 Duty spec in!! Max-Min= 186%
7457 22:16:53.585652
7458 22:16:53.589081 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7459 22:16:53.591914 [DutyScan_Calibration_Flow] ====Done====
7460 22:16:53.595261 nWR fixed to 30
7461 22:16:53.598567 [ModeRegInit_LP4] CH0 RK0
7462 22:16:53.598649 [ModeRegInit_LP4] CH0 RK1
7463 22:16:53.601854 [ModeRegInit_LP4] CH1 RK0
7464 22:16:53.605203 [ModeRegInit_LP4] CH1 RK1
7465 22:16:53.605284 match AC timing 5
7466 22:16:53.611733 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7467 22:16:53.615086 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7468 22:16:53.618186 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7469 22:16:53.625156 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7470 22:16:53.628524 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7471 22:16:53.631843 [MiockJmeterHQA]
7472 22:16:53.631946
7473 22:16:53.634486 [DramcMiockJmeter] u1RxGatingPI = 0
7474 22:16:53.634583 0 : 4254, 4027
7475 22:16:53.634676 4 : 4252, 4026
7476 22:16:53.637854 8 : 4257, 4032
7477 22:16:53.637953 12 : 4255, 4029
7478 22:16:53.641418 16 : 4255, 4029
7479 22:16:53.641491 20 : 4368, 4139
7480 22:16:53.644768 24 : 4257, 4029
7481 22:16:53.644870 28 : 4257, 4029
7482 22:16:53.644962 32 : 4255, 4029
7483 22:16:53.648200 36 : 4260, 4032
7484 22:16:53.648303 40 : 4255, 4030
7485 22:16:53.651739 44 : 4363, 4137
7486 22:16:53.651840 48 : 4257, 4030
7487 22:16:53.654586 52 : 4257, 4029
7488 22:16:53.654691 56 : 4257, 4029
7489 22:16:53.657910 60 : 4257, 4030
7490 22:16:53.658007 64 : 4252, 4029
7491 22:16:53.658097 68 : 4258, 4031
7492 22:16:53.660882 72 : 4365, 4139
7493 22:16:53.660954 76 : 4253, 4029
7494 22:16:53.664373 80 : 4253, 4029
7495 22:16:53.664452 84 : 4252, 4029
7496 22:16:53.667958 88 : 4250, 4027
7497 22:16:53.668028 92 : 4368, 4142
7498 22:16:53.671060 96 : 4252, 4029
7499 22:16:53.671155 100 : 4368, 4145
7500 22:16:53.674406 104 : 4252, 3826
7501 22:16:53.674504 108 : 4255, 10
7502 22:16:53.674594 112 : 4257, 0
7503 22:16:53.677854 116 : 4253, 0
7504 22:16:53.677952 120 : 4360, 0
7505 22:16:53.678042 124 : 4253, 0
7506 22:16:53.680818 128 : 4252, 0
7507 22:16:53.680886 132 : 4253, 0
7508 22:16:53.684210 136 : 4252, 0
7509 22:16:53.684283 140 : 4253, 0
7510 22:16:53.684344 144 : 4253, 0
7511 22:16:53.687466 148 : 4255, 0
7512 22:16:53.687565 152 : 4252, 0
7513 22:16:53.691077 156 : 4363, 0
7514 22:16:53.691148 160 : 4250, 0
7515 22:16:53.691231 164 : 4365, 0
7516 22:16:53.694475 168 : 4252, 0
7517 22:16:53.694572 172 : 4253, 0
7518 22:16:53.697664 176 : 4252, 0
7519 22:16:53.697763 180 : 4257, 0
7520 22:16:53.697853 184 : 4253, 0
7521 22:16:53.700701 188 : 4255, 0
7522 22:16:53.700780 192 : 4257, 0
7523 22:16:53.703880 196 : 4253, 0
7524 22:16:53.703950 200 : 4255, 0
7525 22:16:53.704011 204 : 4257, 0
7526 22:16:53.707252 208 : 4363, 0
7527 22:16:53.707355 212 : 4252, 0
7528 22:16:53.710414 216 : 4253, 0
7529 22:16:53.710503 220 : 4252, 0
7530 22:16:53.710569 224 : 4366, 0
7531 22:16:53.714232 228 : 4252, 0
7532 22:16:53.714316 232 : 4253, 0
7533 22:16:53.717415 236 : 4253, 965
7534 22:16:53.717498 240 : 4254, 4030
7535 22:16:53.717564 244 : 4254, 4029
7536 22:16:53.720531 248 : 4252, 4029
7537 22:16:53.720613 252 : 4255, 4029
7538 22:16:53.723949 256 : 4253, 4029
7539 22:16:53.724031 260 : 4368, 4142
7540 22:16:53.727009 264 : 4252, 4029
7541 22:16:53.727092 268 : 4253, 4029
7542 22:16:53.730775 272 : 4253, 4029
7543 22:16:53.730858 276 : 4258, 4031
7544 22:16:53.733570 280 : 4255, 4029
7545 22:16:53.733653 284 : 4366, 4140
7546 22:16:53.736880 288 : 4252, 4029
7547 22:16:53.736962 292 : 4252, 4030
7548 22:16:53.740065 296 : 4257, 4031
7549 22:16:53.740148 300 : 4363, 4137
7550 22:16:53.743435 304 : 4252, 4029
7551 22:16:53.743518 308 : 4365, 4140
7552 22:16:53.743607 312 : 4255, 4029
7553 22:16:53.746903 316 : 4252, 4030
7554 22:16:53.746986 320 : 4252, 4029
7555 22:16:53.750362 324 : 4253, 4029
7556 22:16:53.750444 328 : 4257, 4031
7557 22:16:53.753201 332 : 4255, 4029
7558 22:16:53.753286 336 : 4361, 4137
7559 22:16:53.756809 340 : 4363, 4140
7560 22:16:53.756892 344 : 4252, 4027
7561 22:16:53.760276 348 : 4252, 4027
7562 22:16:53.760359 352 : 4252, 4028
7563 22:16:53.763145 356 : 4252, 3025
7564 22:16:53.763228 360 : 4253, 8
7565 22:16:53.763295
7566 22:16:53.766470 MIOCK jitter meter ch=0
7567 22:16:53.766553
7568 22:16:53.770109 1T = (360-108) = 252 dly cells
7569 22:16:53.773175 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7570 22:16:53.773262 ==
7571 22:16:53.776652 Dram Type= 6, Freq= 0, CH_0, rank 0
7572 22:16:53.783571 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7573 22:16:53.783691 ==
7574 22:16:53.786367 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7575 22:16:53.793079 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7576 22:16:53.796260 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7577 22:16:53.802543 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7578 22:16:53.811175 [CA 0] Center 44 (14~75) winsize 62
7579 22:16:53.814466 [CA 1] Center 43 (13~74) winsize 62
7580 22:16:53.817651 [CA 2] Center 39 (10~69) winsize 60
7581 22:16:53.821010 [CA 3] Center 39 (10~68) winsize 59
7582 22:16:53.823987 [CA 4] Center 37 (8~67) winsize 60
7583 22:16:53.827434 [CA 5] Center 37 (7~67) winsize 61
7584 22:16:53.827517
7585 22:16:53.830870 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7586 22:16:53.830953
7587 22:16:53.837564 [CATrainingPosCal] consider 1 rank data
7588 22:16:53.837647 u2DelayCellTimex100 = 258/100 ps
7589 22:16:53.843985 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7590 22:16:53.847144 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7591 22:16:53.850720 CA2 delay=39 (10~69),Diff = 2 PI (7 cell)
7592 22:16:53.853694 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7593 22:16:53.857212 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7594 22:16:53.860695 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7595 22:16:53.860778
7596 22:16:53.863908 CA PerBit enable=1, Macro0, CA PI delay=37
7597 22:16:53.863990
7598 22:16:53.866859 [CBTSetCACLKResult] CA Dly = 37
7599 22:16:53.870287 CS Dly: 11 (0~42)
7600 22:16:53.873488 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7601 22:16:53.876924 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7602 22:16:53.877007 ==
7603 22:16:53.880444 Dram Type= 6, Freq= 0, CH_0, rank 1
7604 22:16:53.886716 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7605 22:16:53.886799 ==
7606 22:16:53.890141 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7607 22:16:53.897181 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7608 22:16:53.899872 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7609 22:16:53.906599 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7610 22:16:53.914732 [CA 0] Center 44 (13~75) winsize 63
7611 22:16:53.918243 [CA 1] Center 43 (13~74) winsize 62
7612 22:16:53.921663 [CA 2] Center 39 (10~69) winsize 60
7613 22:16:53.924782 [CA 3] Center 39 (10~68) winsize 59
7614 22:16:53.928213 [CA 4] Center 37 (8~67) winsize 60
7615 22:16:53.931155 [CA 5] Center 36 (7~66) winsize 60
7616 22:16:53.931238
7617 22:16:53.934625 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7618 22:16:53.934708
7619 22:16:53.941460 [CATrainingPosCal] consider 2 rank data
7620 22:16:53.941543 u2DelayCellTimex100 = 258/100 ps
7621 22:16:53.947878 CA0 delay=44 (14~75),Diff = 8 PI (30 cell)
7622 22:16:53.951282 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7623 22:16:53.954593 CA2 delay=39 (10~69),Diff = 3 PI (11 cell)
7624 22:16:53.957603 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7625 22:16:53.960907 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
7626 22:16:53.964462 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7627 22:16:53.964544
7628 22:16:53.967854 CA PerBit enable=1, Macro0, CA PI delay=36
7629 22:16:53.970869
7630 22:16:53.970951 [CBTSetCACLKResult] CA Dly = 36
7631 22:16:53.974162 CS Dly: 11 (0~43)
7632 22:16:53.977270 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7633 22:16:53.980677 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7634 22:16:53.984168
7635 22:16:53.987462 ----->DramcWriteLeveling(PI) begin...
7636 22:16:53.987546 ==
7637 22:16:53.990501 Dram Type= 6, Freq= 0, CH_0, rank 0
7638 22:16:53.994128 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7639 22:16:53.994211 ==
7640 22:16:53.997283 Write leveling (Byte 0): 35 => 35
7641 22:16:54.000655 Write leveling (Byte 1): 28 => 28
7642 22:16:54.003710 DramcWriteLeveling(PI) end<-----
7643 22:16:54.003793
7644 22:16:54.003859 ==
7645 22:16:54.007227 Dram Type= 6, Freq= 0, CH_0, rank 0
7646 22:16:54.010253 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7647 22:16:54.010342 ==
7648 22:16:54.013445 [Gating] SW mode calibration
7649 22:16:54.020307 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7650 22:16:54.026793 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7651 22:16:54.030056 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7652 22:16:54.033304 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7653 22:16:54.040535 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7654 22:16:54.043195 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7655 22:16:54.046629 1 4 16 | B1->B0 | 2323 2727 | 0 1 | (0 0) (1 1)
7656 22:16:54.053090 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7657 22:16:54.056595 1 4 24 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
7658 22:16:54.059974 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7659 22:16:54.066441 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7660 22:16:54.069615 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7661 22:16:54.073336 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7662 22:16:54.079754 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7663 22:16:54.082795 1 5 16 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
7664 22:16:54.086195 1 5 20 | B1->B0 | 3333 2323 | 0 0 | (0 0) (0 0)
7665 22:16:54.092915 1 5 24 | B1->B0 | 2727 2323 | 0 0 | (0 0) (0 0)
7666 22:16:54.095892 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7667 22:16:54.099233 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7668 22:16:54.105929 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7669 22:16:54.109579 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7670 22:16:54.112758 1 6 12 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
7671 22:16:54.119358 1 6 16 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
7672 22:16:54.122510 1 6 20 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
7673 22:16:54.125562 1 6 24 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
7674 22:16:54.132106 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7675 22:16:54.135403 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7676 22:16:54.138556 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7677 22:16:54.145747 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7678 22:16:54.148924 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7679 22:16:54.152111 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7680 22:16:54.158609 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7681 22:16:54.161835 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7682 22:16:54.165503 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7683 22:16:54.171466 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7684 22:16:54.174918 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7685 22:16:54.178487 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7686 22:16:54.184652 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7687 22:16:54.188134 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7688 22:16:54.191841 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7689 22:16:54.198141 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7690 22:16:54.201596 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7691 22:16:54.204941 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7692 22:16:54.211293 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7693 22:16:54.214860 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7694 22:16:54.218376 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7695 22:16:54.224726 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7696 22:16:54.227791 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7697 22:16:54.230994 Total UI for P1: 0, mck2ui 16
7698 22:16:54.234368 best dqsien dly found for B0: ( 1, 9, 14)
7699 22:16:54.238214 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7700 22:16:54.240974 Total UI for P1: 0, mck2ui 16
7701 22:16:54.244213 best dqsien dly found for B1: ( 1, 9, 20)
7702 22:16:54.247479 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7703 22:16:54.250899 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7704 22:16:54.250979
7705 22:16:54.257553 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7706 22:16:54.261033 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7707 22:16:54.264314 [Gating] SW calibration Done
7708 22:16:54.264395 ==
7709 22:16:54.267849 Dram Type= 6, Freq= 0, CH_0, rank 0
7710 22:16:54.270790 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7711 22:16:54.270871 ==
7712 22:16:54.270935 RX Vref Scan: 0
7713 22:16:54.270994
7714 22:16:54.274363 RX Vref 0 -> 0, step: 1
7715 22:16:54.274444
7716 22:16:54.277647 RX Delay 0 -> 252, step: 8
7717 22:16:54.280572 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7718 22:16:54.283914 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7719 22:16:54.290691 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7720 22:16:54.293706 iDelay=192, Bit 3, Center 123 (72 ~ 175) 104
7721 22:16:54.297148 iDelay=192, Bit 4, Center 127 (72 ~ 183) 112
7722 22:16:54.300626 iDelay=192, Bit 5, Center 115 (64 ~ 167) 104
7723 22:16:54.303758 iDelay=192, Bit 6, Center 135 (80 ~ 191) 112
7724 22:16:54.310548 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7725 22:16:54.313595 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7726 22:16:54.316688 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7727 22:16:54.319951 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7728 22:16:54.323353 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
7729 22:16:54.330461 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7730 22:16:54.333225 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7731 22:16:54.336827 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7732 22:16:54.340086 iDelay=192, Bit 15, Center 127 (72 ~ 183) 112
7733 22:16:54.340167 ==
7734 22:16:54.343353 Dram Type= 6, Freq= 0, CH_0, rank 0
7735 22:16:54.349741 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7736 22:16:54.349825 ==
7737 22:16:54.349891 DQS Delay:
7738 22:16:54.353310 DQS0 = 0, DQS1 = 0
7739 22:16:54.353393 DQM Delay:
7740 22:16:54.356583 DQM0 = 128, DQM1 = 123
7741 22:16:54.356666 DQ Delay:
7742 22:16:54.359696 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
7743 22:16:54.363346 DQ4 =127, DQ5 =115, DQ6 =135, DQ7 =139
7744 22:16:54.366480 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7745 22:16:54.369814 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =127
7746 22:16:54.369897
7747 22:16:54.369962
7748 22:16:54.370022 ==
7749 22:16:54.373200 Dram Type= 6, Freq= 0, CH_0, rank 0
7750 22:16:54.379610 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7751 22:16:54.379693 ==
7752 22:16:54.379760
7753 22:16:54.379821
7754 22:16:54.379881 TX Vref Scan disable
7755 22:16:54.382937 == TX Byte 0 ==
7756 22:16:54.386483 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7757 22:16:54.393384 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7758 22:16:54.393473 == TX Byte 1 ==
7759 22:16:54.396278 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7760 22:16:54.402462 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7761 22:16:54.402546 ==
7762 22:16:54.405946 Dram Type= 6, Freq= 0, CH_0, rank 0
7763 22:16:54.409603 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7764 22:16:54.409693 ==
7765 22:16:54.422854
7766 22:16:54.426728 TX Vref early break, caculate TX vref
7767 22:16:54.429957 TX Vref=16, minBit 8, minWin=21, winSum=360
7768 22:16:54.433180 TX Vref=18, minBit 8, minWin=22, winSum=370
7769 22:16:54.436026 TX Vref=20, minBit 8, minWin=22, winSum=380
7770 22:16:54.439543 TX Vref=22, minBit 8, minWin=23, winSum=387
7771 22:16:54.442569 TX Vref=24, minBit 8, minWin=24, winSum=401
7772 22:16:54.449059 TX Vref=26, minBit 4, minWin=24, winSum=402
7773 22:16:54.452502 TX Vref=28, minBit 8, minWin=24, winSum=407
7774 22:16:54.456261 TX Vref=30, minBit 3, minWin=24, winSum=399
7775 22:16:54.459760 TX Vref=32, minBit 8, minWin=23, winSum=388
7776 22:16:54.462793 TX Vref=34, minBit 8, minWin=21, winSum=379
7777 22:16:54.469179 [TxChooseVref] Worse bit 8, Min win 24, Win sum 407, Final Vref 28
7778 22:16:54.469757
7779 22:16:54.472560 Final TX Range 0 Vref 28
7780 22:16:54.473130
7781 22:16:54.473566 ==
7782 22:16:54.475898 Dram Type= 6, Freq= 0, CH_0, rank 0
7783 22:16:54.479316 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7784 22:16:54.480039 ==
7785 22:16:54.480484
7786 22:16:54.480932
7787 22:16:54.482741 TX Vref Scan disable
7788 22:16:54.488851 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7789 22:16:54.489409 == TX Byte 0 ==
7790 22:16:54.492533 u2DelayCellOfst[0]=15 cells (4 PI)
7791 22:16:54.495740 u2DelayCellOfst[1]=22 cells (6 PI)
7792 22:16:54.499311 u2DelayCellOfst[2]=11 cells (3 PI)
7793 22:16:54.502216 u2DelayCellOfst[3]=15 cells (4 PI)
7794 22:16:54.505930 u2DelayCellOfst[4]=11 cells (3 PI)
7795 22:16:54.508930 u2DelayCellOfst[5]=0 cells (0 PI)
7796 22:16:54.512590 u2DelayCellOfst[6]=22 cells (6 PI)
7797 22:16:54.515349 u2DelayCellOfst[7]=18 cells (5 PI)
7798 22:16:54.518873 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7799 22:16:54.522236 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7800 22:16:54.525140 == TX Byte 1 ==
7801 22:16:54.528854 u2DelayCellOfst[8]=0 cells (0 PI)
7802 22:16:54.532215 u2DelayCellOfst[9]=3 cells (1 PI)
7803 22:16:54.535005 u2DelayCellOfst[10]=7 cells (2 PI)
7804 22:16:54.535350 u2DelayCellOfst[11]=3 cells (1 PI)
7805 22:16:54.538348 u2DelayCellOfst[12]=15 cells (4 PI)
7806 22:16:54.541929 u2DelayCellOfst[13]=11 cells (3 PI)
7807 22:16:54.545234 u2DelayCellOfst[14]=15 cells (4 PI)
7808 22:16:54.548146 u2DelayCellOfst[15]=11 cells (3 PI)
7809 22:16:54.554832 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7810 22:16:54.558609 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7811 22:16:54.558942 DramC Write-DBI on
7812 22:16:54.559206 ==
7813 22:16:54.561723 Dram Type= 6, Freq= 0, CH_0, rank 0
7814 22:16:54.568452 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7815 22:16:54.568787 ==
7816 22:16:54.569052
7817 22:16:54.569300
7818 22:16:54.571491 TX Vref Scan disable
7819 22:16:54.571844 == TX Byte 0 ==
7820 22:16:54.578253 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7821 22:16:54.578588 == TX Byte 1 ==
7822 22:16:54.581471 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7823 22:16:54.584790 DramC Write-DBI off
7824 22:16:54.585120
7825 22:16:54.585384 [DATLAT]
7826 22:16:54.587826 Freq=1600, CH0 RK0
7827 22:16:54.588168
7828 22:16:54.588595 DATLAT Default: 0xf
7829 22:16:54.591489 0, 0xFFFF, sum = 0
7830 22:16:54.591869 1, 0xFFFF, sum = 0
7831 22:16:54.594448 2, 0xFFFF, sum = 0
7832 22:16:54.594874 3, 0xFFFF, sum = 0
7833 22:16:54.598075 4, 0xFFFF, sum = 0
7834 22:16:54.598412 5, 0xFFFF, sum = 0
7835 22:16:54.601543 6, 0xFFFF, sum = 0
7836 22:16:54.604317 7, 0xFFFF, sum = 0
7837 22:16:54.604695 8, 0xFFFF, sum = 0
7838 22:16:54.607850 9, 0xFFFF, sum = 0
7839 22:16:54.608184 10, 0xFFFF, sum = 0
7840 22:16:54.611144 11, 0xFFFF, sum = 0
7841 22:16:54.611575 12, 0xFFFF, sum = 0
7842 22:16:54.614364 13, 0xEFFF, sum = 0
7843 22:16:54.614817 14, 0x0, sum = 1
7844 22:16:54.617733 15, 0x0, sum = 2
7845 22:16:54.618165 16, 0x0, sum = 3
7846 22:16:54.620564 17, 0x0, sum = 4
7847 22:16:54.620995 best_step = 15
7848 22:16:54.621336
7849 22:16:54.621652 ==
7850 22:16:54.624550 Dram Type= 6, Freq= 0, CH_0, rank 0
7851 22:16:54.627442 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7852 22:16:54.631027 ==
7853 22:16:54.631453 RX Vref Scan: 1
7854 22:16:54.631845
7855 22:16:54.633852 Set Vref Range= 24 -> 127
7856 22:16:54.634277
7857 22:16:54.637417 RX Vref 24 -> 127, step: 1
7858 22:16:54.637845
7859 22:16:54.638182 RX Delay 11 -> 252, step: 4
7860 22:16:54.638499
7861 22:16:54.640820 Set Vref, RX VrefLevel [Byte0]: 24
7862 22:16:54.644009 [Byte1]: 24
7863 22:16:54.648140
7864 22:16:54.648563 Set Vref, RX VrefLevel [Byte0]: 25
7865 22:16:54.651277 [Byte1]: 25
7866 22:16:54.655559
7867 22:16:54.656010 Set Vref, RX VrefLevel [Byte0]: 26
7868 22:16:54.658526 [Byte1]: 26
7869 22:16:54.663031
7870 22:16:54.663457 Set Vref, RX VrefLevel [Byte0]: 27
7871 22:16:54.666360 [Byte1]: 27
7872 22:16:54.670377
7873 22:16:54.670685 Set Vref, RX VrefLevel [Byte0]: 28
7874 22:16:54.674036 [Byte1]: 28
7875 22:16:54.678071
7876 22:16:54.678300 Set Vref, RX VrefLevel [Byte0]: 29
7877 22:16:54.681474 [Byte1]: 29
7878 22:16:54.685835
7879 22:16:54.686063 Set Vref, RX VrefLevel [Byte0]: 30
7880 22:16:54.688858 [Byte1]: 30
7881 22:16:54.693491
7882 22:16:54.693720 Set Vref, RX VrefLevel [Byte0]: 31
7883 22:16:54.696683 [Byte1]: 31
7884 22:16:54.701214
7885 22:16:54.701443 Set Vref, RX VrefLevel [Byte0]: 32
7886 22:16:54.704343 [Byte1]: 32
7887 22:16:54.708535
7888 22:16:54.708814 Set Vref, RX VrefLevel [Byte0]: 33
7889 22:16:54.711882 [Byte1]: 33
7890 22:16:54.716540
7891 22:16:54.716919 Set Vref, RX VrefLevel [Byte0]: 34
7892 22:16:54.719644 [Byte1]: 34
7893 22:16:54.724045
7894 22:16:54.724406 Set Vref, RX VrefLevel [Byte0]: 35
7895 22:16:54.727465 [Byte1]: 35
7896 22:16:54.731659
7897 22:16:54.732143 Set Vref, RX VrefLevel [Byte0]: 36
7898 22:16:54.734922 [Byte1]: 36
7899 22:16:54.739109
7900 22:16:54.739473 Set Vref, RX VrefLevel [Byte0]: 37
7901 22:16:54.742593 [Byte1]: 37
7902 22:16:54.746680
7903 22:16:54.747055 Set Vref, RX VrefLevel [Byte0]: 38
7904 22:16:54.753458 [Byte1]: 38
7905 22:16:54.753936
7906 22:16:54.756328 Set Vref, RX VrefLevel [Byte0]: 39
7907 22:16:54.759827 [Byte1]: 39
7908 22:16:54.760190
7909 22:16:54.762988 Set Vref, RX VrefLevel [Byte0]: 40
7910 22:16:54.766675 [Byte1]: 40
7911 22:16:54.769846
7912 22:16:54.770242 Set Vref, RX VrefLevel [Byte0]: 41
7913 22:16:54.772780 [Byte1]: 41
7914 22:16:54.777594
7915 22:16:54.777954 Set Vref, RX VrefLevel [Byte0]: 42
7916 22:16:54.780371 [Byte1]: 42
7917 22:16:54.785107
7918 22:16:54.785466 Set Vref, RX VrefLevel [Byte0]: 43
7919 22:16:54.787950 [Byte1]: 43
7920 22:16:54.792205
7921 22:16:54.792566 Set Vref, RX VrefLevel [Byte0]: 44
7922 22:16:54.795935 [Byte1]: 44
7923 22:16:54.800098
7924 22:16:54.800460 Set Vref, RX VrefLevel [Byte0]: 45
7925 22:16:54.803321 [Byte1]: 45
7926 22:16:54.807490
7927 22:16:54.807897 Set Vref, RX VrefLevel [Byte0]: 46
7928 22:16:54.811177 [Byte1]: 46
7929 22:16:54.815102
7930 22:16:54.815629 Set Vref, RX VrefLevel [Byte0]: 47
7931 22:16:54.818588 [Byte1]: 47
7932 22:16:54.822644
7933 22:16:54.823067 Set Vref, RX VrefLevel [Byte0]: 48
7934 22:16:54.825968 [Byte1]: 48
7935 22:16:54.830479
7936 22:16:54.830879 Set Vref, RX VrefLevel [Byte0]: 49
7937 22:16:54.833606 [Byte1]: 49
7938 22:16:54.838412
7939 22:16:54.838844 Set Vref, RX VrefLevel [Byte0]: 50
7940 22:16:54.841491 [Byte1]: 50
7941 22:16:54.845941
7942 22:16:54.846533 Set Vref, RX VrefLevel [Byte0]: 51
7943 22:16:54.848992 [Byte1]: 51
7944 22:16:54.853652
7945 22:16:54.854136 Set Vref, RX VrefLevel [Byte0]: 52
7946 22:16:54.856841 [Byte1]: 52
7947 22:16:54.860762
7948 22:16:54.861267 Set Vref, RX VrefLevel [Byte0]: 53
7949 22:16:54.864387 [Byte1]: 53
7950 22:16:54.868286
7951 22:16:54.868721 Set Vref, RX VrefLevel [Byte0]: 54
7952 22:16:54.871469 [Byte1]: 54
7953 22:16:54.875724
7954 22:16:54.875960 Set Vref, RX VrefLevel [Byte0]: 55
7955 22:16:54.879133 [Byte1]: 55
7956 22:16:54.883715
7957 22:16:54.883868 Set Vref, RX VrefLevel [Byte0]: 56
7958 22:16:54.886691 [Byte1]: 56
7959 22:16:54.891450
7960 22:16:54.891600 Set Vref, RX VrefLevel [Byte0]: 57
7961 22:16:54.894362 [Byte1]: 57
7962 22:16:54.899008
7963 22:16:54.899148 Set Vref, RX VrefLevel [Byte0]: 58
7964 22:16:54.902271 [Byte1]: 58
7965 22:16:54.906579
7966 22:16:54.906718 Set Vref, RX VrefLevel [Byte0]: 59
7967 22:16:54.909802 [Byte1]: 59
7968 22:16:54.914355
7969 22:16:54.914521 Set Vref, RX VrefLevel [Byte0]: 60
7970 22:16:54.917134 [Byte1]: 60
7971 22:16:54.921829
7972 22:16:54.922014 Set Vref, RX VrefLevel [Byte0]: 61
7973 22:16:54.924847 [Byte1]: 61
7974 22:16:54.929357
7975 22:16:54.929631 Set Vref, RX VrefLevel [Byte0]: 62
7976 22:16:54.932854 [Byte1]: 62
7977 22:16:54.936858
7978 22:16:54.937186 Set Vref, RX VrefLevel [Byte0]: 63
7979 22:16:54.940606 [Byte1]: 63
7980 22:16:54.944437
7981 22:16:54.944869 Set Vref, RX VrefLevel [Byte0]: 64
7982 22:16:54.948141 [Byte1]: 64
7983 22:16:54.952311
7984 22:16:54.952642 Set Vref, RX VrefLevel [Byte0]: 65
7985 22:16:54.955946 [Byte1]: 65
7986 22:16:54.960160
7987 22:16:54.960491 Set Vref, RX VrefLevel [Byte0]: 66
7988 22:16:54.963459 [Byte1]: 66
7989 22:16:54.967388
7990 22:16:54.967794 Set Vref, RX VrefLevel [Byte0]: 67
7991 22:16:54.971002 [Byte1]: 67
7992 22:16:54.975058
7993 22:16:54.975386 Set Vref, RX VrefLevel [Byte0]: 68
7994 22:16:54.978345 [Byte1]: 68
7995 22:16:54.982837
7996 22:16:54.983167 Set Vref, RX VrefLevel [Byte0]: 69
7997 22:16:54.985994 [Byte1]: 69
7998 22:16:54.990158
7999 22:16:54.990588 Set Vref, RX VrefLevel [Byte0]: 70
8000 22:16:54.993545 [Byte1]: 70
8001 22:16:54.998381
8002 22:16:54.998712 Set Vref, RX VrefLevel [Byte0]: 71
8003 22:16:55.000999 [Byte1]: 71
8004 22:16:55.005536
8005 22:16:55.005865 Set Vref, RX VrefLevel [Byte0]: 72
8006 22:16:55.008539 [Byte1]: 72
8007 22:16:55.012975
8008 22:16:55.013304 Set Vref, RX VrefLevel [Byte0]: 73
8009 22:16:55.016522 [Byte1]: 73
8010 22:16:55.020850
8011 22:16:55.021178 Set Vref, RX VrefLevel [Byte0]: 74
8012 22:16:55.023991 [Byte1]: 74
8013 22:16:55.028336
8014 22:16:55.028661 Set Vref, RX VrefLevel [Byte0]: 75
8015 22:16:55.031697 [Byte1]: 75
8016 22:16:55.035841
8017 22:16:55.036166 Set Vref, RX VrefLevel [Byte0]: 76
8018 22:16:55.039257 [Byte1]: 76
8019 22:16:55.043405
8020 22:16:55.043759 Set Vref, RX VrefLevel [Byte0]: 77
8021 22:16:55.046814 [Byte1]: 77
8022 22:16:55.051658
8023 22:16:55.051986 Set Vref, RX VrefLevel [Byte0]: 78
8024 22:16:55.054340 [Byte1]: 78
8025 22:16:55.058846
8026 22:16:55.059087 Final RX Vref Byte 0 = 64 to rank0
8027 22:16:55.061839 Final RX Vref Byte 1 = 60 to rank0
8028 22:16:55.065339 Final RX Vref Byte 0 = 64 to rank1
8029 22:16:55.068874 Final RX Vref Byte 1 = 60 to rank1==
8030 22:16:55.071630 Dram Type= 6, Freq= 0, CH_0, rank 0
8031 22:16:55.078694 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8032 22:16:55.078940 ==
8033 22:16:55.079135 DQS Delay:
8034 22:16:55.081936 DQS0 = 0, DQS1 = 0
8035 22:16:55.082178 DQM Delay:
8036 22:16:55.082377 DQM0 = 126, DQM1 = 120
8037 22:16:55.085113 DQ Delay:
8038 22:16:55.088270 DQ0 =126, DQ1 =126, DQ2 =126, DQ3 =122
8039 22:16:55.091737 DQ4 =126, DQ5 =112, DQ6 =134, DQ7 =138
8040 22:16:55.095081 DQ8 =112, DQ9 =108, DQ10 =120, DQ11 =114
8041 22:16:55.098474 DQ12 =126, DQ13 =124, DQ14 =130, DQ15 =128
8042 22:16:55.098774
8043 22:16:55.099013
8044 22:16:55.099237
8045 22:16:55.101773 [DramC_TX_OE_Calibration] TA2
8046 22:16:55.105212 Original DQ_B0 (3 6) =30, OEN = 27
8047 22:16:55.108121 Original DQ_B1 (3 6) =30, OEN = 27
8048 22:16:55.111406 24, 0x0, End_B0=24 End_B1=24
8049 22:16:55.111738 25, 0x0, End_B0=25 End_B1=25
8050 22:16:55.115048 26, 0x0, End_B0=26 End_B1=26
8051 22:16:55.118343 27, 0x0, End_B0=27 End_B1=27
8052 22:16:55.121579 28, 0x0, End_B0=28 End_B1=28
8053 22:16:55.124750 29, 0x0, End_B0=29 End_B1=29
8054 22:16:55.125055 30, 0x0, End_B0=30 End_B1=30
8055 22:16:55.128567 31, 0x4141, End_B0=30 End_B1=30
8056 22:16:55.131457 Byte0 end_step=30 best_step=27
8057 22:16:55.134984 Byte1 end_step=30 best_step=27
8058 22:16:55.138029 Byte0 TX OE(2T, 0.5T) = (3, 3)
8059 22:16:55.141254 Byte1 TX OE(2T, 0.5T) = (3, 3)
8060 22:16:55.141554
8061 22:16:55.141792
8062 22:16:55.148098 [DQSOSCAuto] RK0, (LSB)MR18= 0x1414, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
8063 22:16:55.151038 CH0 RK0: MR19=303, MR18=1414
8064 22:16:55.157578 CH0_RK0: MR19=0x303, MR18=0x1414, DQSOSC=399, MR23=63, INC=23, DEC=15
8065 22:16:55.157767
8066 22:16:55.161051 ----->DramcWriteLeveling(PI) begin...
8067 22:16:55.161235 ==
8068 22:16:55.164090 Dram Type= 6, Freq= 0, CH_0, rank 1
8069 22:16:55.167301 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8070 22:16:55.167483 ==
8071 22:16:55.171008 Write leveling (Byte 0): 32 => 32
8072 22:16:55.174387 Write leveling (Byte 1): 26 => 26
8073 22:16:55.177704 DramcWriteLeveling(PI) end<-----
8074 22:16:55.177886
8075 22:16:55.178031 ==
8076 22:16:55.180733 Dram Type= 6, Freq= 0, CH_0, rank 1
8077 22:16:55.184470 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8078 22:16:55.187426 ==
8079 22:16:55.187623 [Gating] SW mode calibration
8080 22:16:55.197165 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8081 22:16:55.200802 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8082 22:16:55.204135 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8083 22:16:55.210517 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8084 22:16:55.213780 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8085 22:16:55.217373 1 4 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8086 22:16:55.223832 1 4 16 | B1->B0 | 2726 3434 | 1 1 | (0 0) (1 1)
8087 22:16:55.227346 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8088 22:16:55.230375 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8089 22:16:55.237384 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8090 22:16:55.239997 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8091 22:16:55.243519 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8092 22:16:55.250248 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8093 22:16:55.253493 1 5 12 | B1->B0 | 3434 2525 | 1 1 | (1 1) (1 0)
8094 22:16:55.256728 1 5 16 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
8095 22:16:55.263094 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8096 22:16:55.266786 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8097 22:16:55.269793 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8098 22:16:55.276373 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8099 22:16:55.279791 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8100 22:16:55.282899 1 6 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8101 22:16:55.289702 1 6 12 | B1->B0 | 2323 4040 | 0 0 | (0 0) (0 0)
8102 22:16:55.292986 1 6 16 | B1->B0 | 3030 4646 | 1 0 | (0 0) (0 0)
8103 22:16:55.296219 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8104 22:16:55.303148 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8105 22:16:55.306109 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8106 22:16:55.309369 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8107 22:16:55.316138 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8108 22:16:55.319130 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8109 22:16:55.322759 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8110 22:16:55.329498 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8111 22:16:55.332513 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8112 22:16:55.336029 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8113 22:16:55.342857 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8114 22:16:55.345723 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8115 22:16:55.349073 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8116 22:16:55.355462 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8117 22:16:55.358915 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8118 22:16:55.362344 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8119 22:16:55.368738 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8120 22:16:55.371850 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8121 22:16:55.375275 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8122 22:16:55.381740 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8123 22:16:55.385349 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8124 22:16:55.387874 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8125 22:16:55.394670 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8126 22:16:55.398123 Total UI for P1: 0, mck2ui 16
8127 22:16:55.401356 best dqsien dly found for B0: ( 1, 9, 8)
8128 22:16:55.404571 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8129 22:16:55.407615 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8130 22:16:55.414217 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8131 22:16:55.417433 Total UI for P1: 0, mck2ui 16
8132 22:16:55.420952 best dqsien dly found for B1: ( 1, 9, 18)
8133 22:16:55.424380 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8134 22:16:55.427413 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8135 22:16:55.427488
8136 22:16:55.430766 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8137 22:16:55.434132 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8138 22:16:55.437265 [Gating] SW calibration Done
8139 22:16:55.437344 ==
8140 22:16:55.440860 Dram Type= 6, Freq= 0, CH_0, rank 1
8141 22:16:55.443718 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8142 22:16:55.447050 ==
8143 22:16:55.447132 RX Vref Scan: 0
8144 22:16:55.447194
8145 22:16:55.450562 RX Vref 0 -> 0, step: 1
8146 22:16:55.450632
8147 22:16:55.450691 RX Delay 0 -> 252, step: 8
8148 22:16:55.457045 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8149 22:16:55.460242 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8150 22:16:55.463436 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8151 22:16:55.466891 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8152 22:16:55.473360 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8153 22:16:55.476897 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
8154 22:16:55.480038 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8155 22:16:55.483122 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8156 22:16:55.486455 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8157 22:16:55.493146 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8158 22:16:55.496753 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8159 22:16:55.499510 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8160 22:16:55.502824 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8161 22:16:55.509524 iDelay=200, Bit 13, Center 127 (72 ~ 183) 112
8162 22:16:55.512725 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8163 22:16:55.516252 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8164 22:16:55.516335 ==
8165 22:16:55.519509 Dram Type= 6, Freq= 0, CH_0, rank 1
8166 22:16:55.522778 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8167 22:16:55.522860 ==
8168 22:16:55.525681 DQS Delay:
8169 22:16:55.525762 DQS0 = 0, DQS1 = 0
8170 22:16:55.529069 DQM Delay:
8171 22:16:55.529150 DQM0 = 128, DQM1 = 121
8172 22:16:55.529214 DQ Delay:
8173 22:16:55.536054 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
8174 22:16:55.539535 DQ4 =127, DQ5 =111, DQ6 =139, DQ7 =139
8175 22:16:55.542571 DQ8 =111, DQ9 =107, DQ10 =123, DQ11 =115
8176 22:16:55.545714 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8177 22:16:55.545795
8178 22:16:55.545859
8179 22:16:55.545918 ==
8180 22:16:55.549130 Dram Type= 6, Freq= 0, CH_0, rank 1
8181 22:16:55.552227 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8182 22:16:55.552309 ==
8183 22:16:55.552373
8184 22:16:55.552433
8185 22:16:55.555486 TX Vref Scan disable
8186 22:16:55.558913 == TX Byte 0 ==
8187 22:16:55.562271 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8188 22:16:55.565799 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
8189 22:16:55.568754 == TX Byte 1 ==
8190 22:16:55.572081 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8191 22:16:55.575065 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8192 22:16:55.575159 ==
8193 22:16:55.578879 Dram Type= 6, Freq= 0, CH_0, rank 1
8194 22:16:55.585386 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8195 22:16:55.585490 ==
8196 22:16:55.597419
8197 22:16:55.600823 TX Vref early break, caculate TX vref
8198 22:16:55.604167 TX Vref=16, minBit 1, minWin=22, winSum=366
8199 22:16:55.607094 TX Vref=18, minBit 0, minWin=22, winSum=370
8200 22:16:55.610712 TX Vref=20, minBit 8, minWin=22, winSum=377
8201 22:16:55.613921 TX Vref=22, minBit 1, minWin=23, winSum=391
8202 22:16:55.617361 TX Vref=24, minBit 0, minWin=24, winSum=398
8203 22:16:55.624178 TX Vref=26, minBit 0, minWin=24, winSum=402
8204 22:16:55.626972 TX Vref=28, minBit 8, minWin=25, winSum=414
8205 22:16:55.630937 TX Vref=30, minBit 8, minWin=24, winSum=403
8206 22:16:55.633592 TX Vref=32, minBit 8, minWin=23, winSum=394
8207 22:16:55.637175 TX Vref=34, minBit 8, minWin=22, winSum=386
8208 22:16:55.643842 [TxChooseVref] Worse bit 8, Min win 25, Win sum 414, Final Vref 28
8209 22:16:55.643930
8210 22:16:55.647207 Final TX Range 0 Vref 28
8211 22:16:55.647291
8212 22:16:55.647358 ==
8213 22:16:55.650745 Dram Type= 6, Freq= 0, CH_0, rank 1
8214 22:16:55.653541 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8215 22:16:55.653639 ==
8216 22:16:55.653704
8217 22:16:55.653766
8218 22:16:55.656625 TX Vref Scan disable
8219 22:16:55.663788 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8220 22:16:55.663874 == TX Byte 0 ==
8221 22:16:55.666934 u2DelayCellOfst[0]=11 cells (3 PI)
8222 22:16:55.670090 u2DelayCellOfst[1]=18 cells (5 PI)
8223 22:16:55.673570 u2DelayCellOfst[2]=11 cells (3 PI)
8224 22:16:55.676599 u2DelayCellOfst[3]=11 cells (3 PI)
8225 22:16:55.680180 u2DelayCellOfst[4]=7 cells (2 PI)
8226 22:16:55.683138 u2DelayCellOfst[5]=0 cells (0 PI)
8227 22:16:55.686704 u2DelayCellOfst[6]=18 cells (5 PI)
8228 22:16:55.690112 u2DelayCellOfst[7]=18 cells (5 PI)
8229 22:16:55.692851 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8230 22:16:55.696090 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8231 22:16:55.699765 == TX Byte 1 ==
8232 22:16:55.703183 u2DelayCellOfst[8]=0 cells (0 PI)
8233 22:16:55.706337 u2DelayCellOfst[9]=0 cells (0 PI)
8234 22:16:55.709506 u2DelayCellOfst[10]=11 cells (3 PI)
8235 22:16:55.709583 u2DelayCellOfst[11]=7 cells (2 PI)
8236 22:16:55.712722 u2DelayCellOfst[12]=11 cells (3 PI)
8237 22:16:55.715937 u2DelayCellOfst[13]=11 cells (3 PI)
8238 22:16:55.719210 u2DelayCellOfst[14]=15 cells (4 PI)
8239 22:16:55.722751 u2DelayCellOfst[15]=11 cells (3 PI)
8240 22:16:55.729396 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8241 22:16:55.732811 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8242 22:16:55.733073 DramC Write-DBI on
8243 22:16:55.735549 ==
8244 22:16:55.739002 Dram Type= 6, Freq= 0, CH_0, rank 1
8245 22:16:55.742266 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8246 22:16:55.742350 ==
8247 22:16:55.742416
8248 22:16:55.742477
8249 22:16:55.745490 TX Vref Scan disable
8250 22:16:55.745634 == TX Byte 0 ==
8251 22:16:55.752128 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
8252 22:16:55.752211 == TX Byte 1 ==
8253 22:16:55.755735 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8254 22:16:55.758515 DramC Write-DBI off
8255 22:16:55.758598
8256 22:16:55.758664 [DATLAT]
8257 22:16:55.762113 Freq=1600, CH0 RK1
8258 22:16:55.762197
8259 22:16:55.762258 DATLAT Default: 0xf
8260 22:16:55.765889 0, 0xFFFF, sum = 0
8261 22:16:55.765972 1, 0xFFFF, sum = 0
8262 22:16:55.768628 2, 0xFFFF, sum = 0
8263 22:16:55.768726 3, 0xFFFF, sum = 0
8264 22:16:55.772244 4, 0xFFFF, sum = 0
8265 22:16:55.775499 5, 0xFFFF, sum = 0
8266 22:16:55.775590 6, 0xFFFF, sum = 0
8267 22:16:55.778822 7, 0xFFFF, sum = 0
8268 22:16:55.778911 8, 0xFFFF, sum = 0
8269 22:16:55.782034 9, 0xFFFF, sum = 0
8270 22:16:55.782113 10, 0xFFFF, sum = 0
8271 22:16:55.785126 11, 0xFFFF, sum = 0
8272 22:16:55.785199 12, 0xFFFF, sum = 0
8273 22:16:55.788514 13, 0xCFFF, sum = 0
8274 22:16:55.788587 14, 0x0, sum = 1
8275 22:16:55.791506 15, 0x0, sum = 2
8276 22:16:55.791634 16, 0x0, sum = 3
8277 22:16:55.795345 17, 0x0, sum = 4
8278 22:16:55.795417 best_step = 15
8279 22:16:55.795477
8280 22:16:55.795534 ==
8281 22:16:55.797956 Dram Type= 6, Freq= 0, CH_0, rank 1
8282 22:16:55.804559 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8283 22:16:55.804636 ==
8284 22:16:55.804698 RX Vref Scan: 0
8285 22:16:55.804757
8286 22:16:55.808174 RX Vref 0 -> 0, step: 1
8287 22:16:55.808256
8288 22:16:55.811706 RX Delay 3 -> 252, step: 4
8289 22:16:55.815311 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8290 22:16:55.818127 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
8291 22:16:55.821326 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8292 22:16:55.827656 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8293 22:16:55.831488 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8294 22:16:55.834221 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8295 22:16:55.837797 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8296 22:16:55.840979 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8297 22:16:55.847560 iDelay=191, Bit 8, Center 110 (55 ~ 166) 112
8298 22:16:55.851137 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8299 22:16:55.854365 iDelay=191, Bit 10, Center 118 (59 ~ 178) 120
8300 22:16:55.857735 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8301 22:16:55.864197 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8302 22:16:55.867716 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8303 22:16:55.870755 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8304 22:16:55.873704 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8305 22:16:55.873789 ==
8306 22:16:55.877329 Dram Type= 6, Freq= 0, CH_0, rank 1
8307 22:16:55.883555 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8308 22:16:55.883670 ==
8309 22:16:55.883750 DQS Delay:
8310 22:16:55.886762 DQS0 = 0, DQS1 = 0
8311 22:16:55.886865 DQM Delay:
8312 22:16:55.890143 DQM0 = 124, DQM1 = 117
8313 22:16:55.890220 DQ Delay:
8314 22:16:55.893489 DQ0 =124, DQ1 =124, DQ2 =122, DQ3 =122
8315 22:16:55.896690 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8316 22:16:55.900002 DQ8 =110, DQ9 =104, DQ10 =118, DQ11 =112
8317 22:16:55.903456 DQ12 =124, DQ13 =122, DQ14 =128, DQ15 =124
8318 22:16:55.903541
8319 22:16:55.903614
8320 22:16:55.903677
8321 22:16:55.906482 [DramC_TX_OE_Calibration] TA2
8322 22:16:55.910020 Original DQ_B0 (3 6) =30, OEN = 27
8323 22:16:55.913478 Original DQ_B1 (3 6) =30, OEN = 27
8324 22:16:55.916879 24, 0x0, End_B0=24 End_B1=24
8325 22:16:55.920138 25, 0x0, End_B0=25 End_B1=25
8326 22:16:55.920225 26, 0x0, End_B0=26 End_B1=26
8327 22:16:55.923880 27, 0x0, End_B0=27 End_B1=27
8328 22:16:55.926179 28, 0x0, End_B0=28 End_B1=28
8329 22:16:55.929817 29, 0x0, End_B0=29 End_B1=29
8330 22:16:55.929902 30, 0x0, End_B0=30 End_B1=30
8331 22:16:55.933165 31, 0x4141, End_B0=30 End_B1=30
8332 22:16:55.936446 Byte0 end_step=30 best_step=27
8333 22:16:55.939467 Byte1 end_step=30 best_step=27
8334 22:16:55.943038 Byte0 TX OE(2T, 0.5T) = (3, 3)
8335 22:16:55.946324 Byte1 TX OE(2T, 0.5T) = (3, 3)
8336 22:16:55.946437
8337 22:16:55.946535
8338 22:16:55.952910 [DQSOSCAuto] RK1, (LSB)MR18= 0x220f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 392 ps
8339 22:16:55.956206 CH0 RK1: MR19=303, MR18=220F
8340 22:16:55.962465 CH0_RK1: MR19=0x303, MR18=0x220F, DQSOSC=392, MR23=63, INC=24, DEC=16
8341 22:16:55.966137 [RxdqsGatingPostProcess] freq 1600
8342 22:16:55.972670 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8343 22:16:55.972768 best DQS0 dly(2T, 0.5T) = (1, 1)
8344 22:16:55.975644 best DQS1 dly(2T, 0.5T) = (1, 1)
8345 22:16:55.979183 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8346 22:16:55.982710 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8347 22:16:55.985398 best DQS0 dly(2T, 0.5T) = (1, 1)
8348 22:16:55.989147 best DQS1 dly(2T, 0.5T) = (1, 1)
8349 22:16:55.992078 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8350 22:16:55.996023 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8351 22:16:55.999168 Pre-setting of DQS Precalculation
8352 22:16:56.002040 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8353 22:16:56.005663 ==
8354 22:16:56.005739 Dram Type= 6, Freq= 0, CH_1, rank 0
8355 22:16:56.011954 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8356 22:16:56.012068 ==
8357 22:16:56.015343 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8358 22:16:56.022291 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8359 22:16:56.025316 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8360 22:16:56.031756 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8361 22:16:56.040158 [CA 0] Center 42 (13~71) winsize 59
8362 22:16:56.043235 [CA 1] Center 42 (13~72) winsize 60
8363 22:16:56.046588 [CA 2] Center 38 (9~67) winsize 59
8364 22:16:56.050227 [CA 3] Center 37 (8~66) winsize 59
8365 22:16:56.053109 [CA 4] Center 37 (8~67) winsize 60
8366 22:16:56.056855 [CA 5] Center 36 (7~66) winsize 60
8367 22:16:56.056936
8368 22:16:56.060172 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8369 22:16:56.060252
8370 22:16:56.066326 [CATrainingPosCal] consider 1 rank data
8371 22:16:56.066407 u2DelayCellTimex100 = 258/100 ps
8372 22:16:56.072837 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8373 22:16:56.076281 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8374 22:16:56.079845 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8375 22:16:56.082672 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8376 22:16:56.086019 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8377 22:16:56.089503 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8378 22:16:56.089582
8379 22:16:56.093094 CA PerBit enable=1, Macro0, CA PI delay=36
8380 22:16:56.093174
8381 22:16:56.096073 [CBTSetCACLKResult] CA Dly = 36
8382 22:16:56.099466 CS Dly: 10 (0~41)
8383 22:16:56.102939 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8384 22:16:56.106001 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8385 22:16:56.106081 ==
8386 22:16:56.109551 Dram Type= 6, Freq= 0, CH_1, rank 1
8387 22:16:56.115993 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8388 22:16:56.116076 ==
8389 22:16:56.119093 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8390 22:16:56.125954 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8391 22:16:56.129044 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8392 22:16:56.135864 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8393 22:16:56.143564 [CA 0] Center 42 (13~71) winsize 59
8394 22:16:56.147200 [CA 1] Center 42 (13~72) winsize 60
8395 22:16:56.150249 [CA 2] Center 38 (9~68) winsize 60
8396 22:16:56.153598 [CA 3] Center 37 (8~67) winsize 60
8397 22:16:56.156726 [CA 4] Center 38 (8~68) winsize 61
8398 22:16:56.159906 [CA 5] Center 37 (7~67) winsize 61
8399 22:16:56.160320
8400 22:16:56.163468 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8401 22:16:56.163955
8402 22:16:56.166665 [CATrainingPosCal] consider 2 rank data
8403 22:16:56.170203 u2DelayCellTimex100 = 258/100 ps
8404 22:16:56.176547 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8405 22:16:56.180079 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8406 22:16:56.183356 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8407 22:16:56.186482 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8408 22:16:56.189727 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8409 22:16:56.193202 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8410 22:16:56.193657
8411 22:16:56.196208 CA PerBit enable=1, Macro0, CA PI delay=36
8412 22:16:56.196665
8413 22:16:56.199625 [CBTSetCACLKResult] CA Dly = 36
8414 22:16:56.203042 CS Dly: 11 (0~43)
8415 22:16:56.206352 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8416 22:16:56.209959 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8417 22:16:56.210459
8418 22:16:56.212653 ----->DramcWriteLeveling(PI) begin...
8419 22:16:56.213116 ==
8420 22:16:56.216037 Dram Type= 6, Freq= 0, CH_1, rank 0
8421 22:16:56.222627 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8422 22:16:56.223223 ==
8423 22:16:56.225732 Write leveling (Byte 0): 23 => 23
8424 22:16:56.228884 Write leveling (Byte 1): 27 => 27
8425 22:16:56.232132 DramcWriteLeveling(PI) end<-----
8426 22:16:56.232369
8427 22:16:56.232565 ==
8428 22:16:56.235217 Dram Type= 6, Freq= 0, CH_1, rank 0
8429 22:16:56.238613 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8430 22:16:56.238807 ==
8431 22:16:56.241832 [Gating] SW mode calibration
8432 22:16:56.248795 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8433 22:16:56.255956 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8434 22:16:56.258172 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8435 22:16:56.261855 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8436 22:16:56.268459 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8437 22:16:56.271532 1 4 12 | B1->B0 | 2424 2424 | 1 0 | (0 0) (1 1)
8438 22:16:56.274790 1 4 16 | B1->B0 | 3333 3131 | 1 1 | (1 1) (1 1)
8439 22:16:56.281765 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8440 22:16:56.284998 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8441 22:16:56.287936 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8442 22:16:56.294729 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8443 22:16:56.298185 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8444 22:16:56.301170 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8445 22:16:56.308121 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8446 22:16:56.311443 1 5 16 | B1->B0 | 2424 2424 | 0 0 | (1 0) (1 0)
8447 22:16:56.314265 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8448 22:16:56.321266 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8449 22:16:56.324228 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8450 22:16:56.327975 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8451 22:16:56.334283 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8452 22:16:56.337367 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8453 22:16:56.340878 1 6 12 | B1->B0 | 2a2a 2a2a | 0 1 | (0 0) (0 0)
8454 22:16:56.347373 1 6 16 | B1->B0 | 4343 4545 | 0 0 | (0 0) (0 0)
8455 22:16:56.350374 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8456 22:16:56.353863 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8457 22:16:56.361139 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8458 22:16:56.364510 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8459 22:16:56.367312 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8460 22:16:56.374340 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8461 22:16:56.377486 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8462 22:16:56.380760 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8463 22:16:56.387605 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8464 22:16:56.390518 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8465 22:16:56.393710 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8466 22:16:56.400698 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8467 22:16:56.403672 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8468 22:16:56.407081 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8469 22:16:56.413473 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8470 22:16:56.416847 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8471 22:16:56.420250 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8472 22:16:56.426548 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8473 22:16:56.429923 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8474 22:16:56.433211 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8475 22:16:56.439508 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8476 22:16:56.442959 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8477 22:16:56.446274 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8478 22:16:56.453085 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8479 22:16:56.456203 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8480 22:16:56.459554 Total UI for P1: 0, mck2ui 16
8481 22:16:56.462428 best dqsien dly found for B0: ( 1, 9, 14)
8482 22:16:56.466059 Total UI for P1: 0, mck2ui 16
8483 22:16:56.469255 best dqsien dly found for B1: ( 1, 9, 14)
8484 22:16:56.472577 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8485 22:16:56.475829 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8486 22:16:56.476019
8487 22:16:56.478910 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8488 22:16:56.482470 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8489 22:16:56.485996 [Gating] SW calibration Done
8490 22:16:56.486198 ==
8491 22:16:56.488861 Dram Type= 6, Freq= 0, CH_1, rank 0
8492 22:16:56.496112 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8493 22:16:56.496305 ==
8494 22:16:56.496456 RX Vref Scan: 0
8495 22:16:56.496597
8496 22:16:56.498883 RX Vref 0 -> 0, step: 1
8497 22:16:56.499071
8498 22:16:56.502274 RX Delay 0 -> 252, step: 8
8499 22:16:56.505611 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8500 22:16:56.508604 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8501 22:16:56.511866 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8502 22:16:56.515128 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8503 22:16:56.521440 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8504 22:16:56.524875 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8505 22:16:56.528524 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8506 22:16:56.531293 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8507 22:16:56.538445 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8508 22:16:56.541614 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8509 22:16:56.544538 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8510 22:16:56.547830 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8511 22:16:56.551794 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
8512 22:16:56.557654 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8513 22:16:56.561138 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8514 22:16:56.564421 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8515 22:16:56.564503 ==
8516 22:16:56.568001 Dram Type= 6, Freq= 0, CH_1, rank 0
8517 22:16:56.570955 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8518 22:16:56.574015 ==
8519 22:16:56.574096 DQS Delay:
8520 22:16:56.574160 DQS0 = 0, DQS1 = 0
8521 22:16:56.577391 DQM Delay:
8522 22:16:56.577472 DQM0 = 132, DQM1 = 125
8523 22:16:56.580651 DQ Delay:
8524 22:16:56.584014 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8525 22:16:56.587211 DQ4 =127, DQ5 =139, DQ6 =143, DQ7 =131
8526 22:16:56.590536 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8527 22:16:56.593830 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
8528 22:16:56.593911
8529 22:16:56.593976
8530 22:16:56.594035 ==
8531 22:16:56.597264 Dram Type= 6, Freq= 0, CH_1, rank 0
8532 22:16:56.600472 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8533 22:16:56.603858 ==
8534 22:16:56.603939
8535 22:16:56.604003
8536 22:16:56.604062 TX Vref Scan disable
8537 22:16:56.607075 == TX Byte 0 ==
8538 22:16:56.610256 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8539 22:16:56.613287 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8540 22:16:56.616855 == TX Byte 1 ==
8541 22:16:56.620406 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8542 22:16:56.623716 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8543 22:16:56.626708 ==
8544 22:16:56.630036 Dram Type= 6, Freq= 0, CH_1, rank 0
8545 22:16:56.632899 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8546 22:16:56.632981 ==
8547 22:16:56.645298
8548 22:16:56.648601 TX Vref early break, caculate TX vref
8549 22:16:56.652162 TX Vref=16, minBit 1, minWin=20, winSum=359
8550 22:16:56.655571 TX Vref=18, minBit 1, minWin=21, winSum=368
8551 22:16:56.658978 TX Vref=20, minBit 1, minWin=23, winSum=380
8552 22:16:56.661980 TX Vref=22, minBit 5, minWin=23, winSum=392
8553 22:16:56.665224 TX Vref=24, minBit 1, minWin=24, winSum=403
8554 22:16:56.671857 TX Vref=26, minBit 1, minWin=24, winSum=409
8555 22:16:56.674851 TX Vref=28, minBit 0, minWin=24, winSum=413
8556 22:16:56.678421 TX Vref=30, minBit 6, minWin=23, winSum=408
8557 22:16:56.681741 TX Vref=32, minBit 1, minWin=23, winSum=403
8558 22:16:56.684893 TX Vref=34, minBit 0, minWin=22, winSum=388
8559 22:16:56.691738 [TxChooseVref] Worse bit 0, Min win 24, Win sum 413, Final Vref 28
8560 22:16:56.691822
8561 22:16:56.694573 Final TX Range 0 Vref 28
8562 22:16:56.694654
8563 22:16:56.694718 ==
8564 22:16:56.698440 Dram Type= 6, Freq= 0, CH_1, rank 0
8565 22:16:56.701310 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8566 22:16:56.701392 ==
8567 22:16:56.701456
8568 22:16:56.701514
8569 22:16:56.704651 TX Vref Scan disable
8570 22:16:56.711292 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8571 22:16:56.711373 == TX Byte 0 ==
8572 22:16:56.714454 u2DelayCellOfst[0]=18 cells (5 PI)
8573 22:16:56.717917 u2DelayCellOfst[1]=15 cells (4 PI)
8574 22:16:56.721039 u2DelayCellOfst[2]=0 cells (0 PI)
8575 22:16:56.724357 u2DelayCellOfst[3]=7 cells (2 PI)
8576 22:16:56.727805 u2DelayCellOfst[4]=7 cells (2 PI)
8577 22:16:56.731100 u2DelayCellOfst[5]=22 cells (6 PI)
8578 22:16:56.734274 u2DelayCellOfst[6]=22 cells (6 PI)
8579 22:16:56.737698 u2DelayCellOfst[7]=7 cells (2 PI)
8580 22:16:56.740729 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8581 22:16:56.744099 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8582 22:16:56.747358 == TX Byte 1 ==
8583 22:16:56.750770 u2DelayCellOfst[8]=0 cells (0 PI)
8584 22:16:56.754080 u2DelayCellOfst[9]=3 cells (1 PI)
8585 22:16:56.757210 u2DelayCellOfst[10]=11 cells (3 PI)
8586 22:16:56.760915 u2DelayCellOfst[11]=7 cells (2 PI)
8587 22:16:56.763646 u2DelayCellOfst[12]=15 cells (4 PI)
8588 22:16:56.763727 u2DelayCellOfst[13]=18 cells (5 PI)
8589 22:16:56.767295 u2DelayCellOfst[14]=18 cells (5 PI)
8590 22:16:56.770442 u2DelayCellOfst[15]=18 cells (5 PI)
8591 22:16:56.777019 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8592 22:16:56.779963 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8593 22:16:56.783516 DramC Write-DBI on
8594 22:16:56.783603 ==
8595 22:16:56.786654 Dram Type= 6, Freq= 0, CH_1, rank 0
8596 22:16:56.789912 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8597 22:16:56.789993 ==
8598 22:16:56.790058
8599 22:16:56.790118
8600 22:16:56.793344 TX Vref Scan disable
8601 22:16:56.793425 == TX Byte 0 ==
8602 22:16:56.799867 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8603 22:16:56.799948 == TX Byte 1 ==
8604 22:16:56.803187 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8605 22:16:56.806317 DramC Write-DBI off
8606 22:16:56.806398
8607 22:16:56.806463 [DATLAT]
8608 22:16:56.809579 Freq=1600, CH1 RK0
8609 22:16:56.809661
8610 22:16:56.809725 DATLAT Default: 0xf
8611 22:16:56.812910 0, 0xFFFF, sum = 0
8612 22:16:56.816148 1, 0xFFFF, sum = 0
8613 22:16:56.816230 2, 0xFFFF, sum = 0
8614 22:16:56.819443 3, 0xFFFF, sum = 0
8615 22:16:56.819527 4, 0xFFFF, sum = 0
8616 22:16:56.822797 5, 0xFFFF, sum = 0
8617 22:16:56.822880 6, 0xFFFF, sum = 0
8618 22:16:56.826307 7, 0xFFFF, sum = 0
8619 22:16:56.826391 8, 0xFFFF, sum = 0
8620 22:16:56.829654 9, 0xFFFF, sum = 0
8621 22:16:56.829736 10, 0xFFFF, sum = 0
8622 22:16:56.832611 11, 0xFFFF, sum = 0
8623 22:16:56.832693 12, 0xFFFF, sum = 0
8624 22:16:56.836144 13, 0x8FFF, sum = 0
8625 22:16:56.836226 14, 0x0, sum = 1
8626 22:16:56.839567 15, 0x0, sum = 2
8627 22:16:56.839686 16, 0x0, sum = 3
8628 22:16:56.842564 17, 0x0, sum = 4
8629 22:16:56.842646 best_step = 15
8630 22:16:56.842711
8631 22:16:56.842771 ==
8632 22:16:56.846067 Dram Type= 6, Freq= 0, CH_1, rank 0
8633 22:16:56.852853 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8634 22:16:56.852935 ==
8635 22:16:56.852999 RX Vref Scan: 1
8636 22:16:56.853058
8637 22:16:56.855703 Set Vref Range= 24 -> 127
8638 22:16:56.855784
8639 22:16:56.859022 RX Vref 24 -> 127, step: 1
8640 22:16:56.859117
8641 22:16:56.859207 RX Delay 11 -> 252, step: 4
8642 22:16:56.862604
8643 22:16:56.862685 Set Vref, RX VrefLevel [Byte0]: 24
8644 22:16:56.865779 [Byte1]: 24
8645 22:16:56.869886
8646 22:16:56.869967 Set Vref, RX VrefLevel [Byte0]: 25
8647 22:16:56.873238 [Byte1]: 25
8648 22:16:56.877469
8649 22:16:56.877549 Set Vref, RX VrefLevel [Byte0]: 26
8650 22:16:56.881024 [Byte1]: 26
8651 22:16:56.885102
8652 22:16:56.885183 Set Vref, RX VrefLevel [Byte0]: 27
8653 22:16:56.888562 [Byte1]: 27
8654 22:16:56.892901
8655 22:16:56.892982 Set Vref, RX VrefLevel [Byte0]: 28
8656 22:16:56.896166 [Byte1]: 28
8657 22:16:56.900505
8658 22:16:56.900586 Set Vref, RX VrefLevel [Byte0]: 29
8659 22:16:56.903731 [Byte1]: 29
8660 22:16:56.908103
8661 22:16:56.908184 Set Vref, RX VrefLevel [Byte0]: 30
8662 22:16:56.911379 [Byte1]: 30
8663 22:16:56.915749
8664 22:16:56.915831 Set Vref, RX VrefLevel [Byte0]: 31
8665 22:16:56.919158 [Byte1]: 31
8666 22:16:56.923612
8667 22:16:56.923693 Set Vref, RX VrefLevel [Byte0]: 32
8668 22:16:56.926344 [Byte1]: 32
8669 22:16:56.930602
8670 22:16:56.930699 Set Vref, RX VrefLevel [Byte0]: 33
8671 22:16:56.934156 [Byte1]: 33
8672 22:16:56.938231
8673 22:16:56.938315 Set Vref, RX VrefLevel [Byte0]: 34
8674 22:16:56.941675 [Byte1]: 34
8675 22:16:56.945972
8676 22:16:56.946053 Set Vref, RX VrefLevel [Byte0]: 35
8677 22:16:56.949509 [Byte1]: 35
8678 22:16:56.953438
8679 22:16:56.953519 Set Vref, RX VrefLevel [Byte0]: 36
8680 22:16:56.956790 [Byte1]: 36
8681 22:16:56.961344
8682 22:16:56.961424 Set Vref, RX VrefLevel [Byte0]: 37
8683 22:16:56.964757 [Byte1]: 37
8684 22:16:56.969285
8685 22:16:56.969386 Set Vref, RX VrefLevel [Byte0]: 38
8686 22:16:56.972188 [Byte1]: 38
8687 22:16:56.976596
8688 22:16:56.976676 Set Vref, RX VrefLevel [Byte0]: 39
8689 22:16:56.979615 [Byte1]: 39
8690 22:16:56.984109
8691 22:16:56.984189 Set Vref, RX VrefLevel [Byte0]: 40
8692 22:16:56.987229 [Byte1]: 40
8693 22:16:56.991769
8694 22:16:56.991849 Set Vref, RX VrefLevel [Byte0]: 41
8695 22:16:56.995325 [Byte1]: 41
8696 22:16:56.999148
8697 22:16:56.999229 Set Vref, RX VrefLevel [Byte0]: 42
8698 22:16:57.002655 [Byte1]: 42
8699 22:16:57.007171
8700 22:16:57.007252 Set Vref, RX VrefLevel [Byte0]: 43
8701 22:16:57.010200 [Byte1]: 43
8702 22:16:57.014541
8703 22:16:57.014622 Set Vref, RX VrefLevel [Byte0]: 44
8704 22:16:57.017846 [Byte1]: 44
8705 22:16:57.022227
8706 22:16:57.022310 Set Vref, RX VrefLevel [Byte0]: 45
8707 22:16:57.025847 [Byte1]: 45
8708 22:16:57.029832
8709 22:16:57.029912 Set Vref, RX VrefLevel [Byte0]: 46
8710 22:16:57.033124 [Byte1]: 46
8711 22:16:57.037188
8712 22:16:57.037269 Set Vref, RX VrefLevel [Byte0]: 47
8713 22:16:57.040937 [Byte1]: 47
8714 22:16:57.044790
8715 22:16:57.044871 Set Vref, RX VrefLevel [Byte0]: 48
8716 22:16:57.048446 [Byte1]: 48
8717 22:16:57.052416
8718 22:16:57.052497 Set Vref, RX VrefLevel [Byte0]: 49
8719 22:16:57.056055 [Byte1]: 49
8720 22:16:57.060107
8721 22:16:57.060187 Set Vref, RX VrefLevel [Byte0]: 50
8722 22:16:57.063410 [Byte1]: 50
8723 22:16:57.067999
8724 22:16:57.068080 Set Vref, RX VrefLevel [Byte0]: 51
8725 22:16:57.070936 [Byte1]: 51
8726 22:16:57.075594
8727 22:16:57.075682 Set Vref, RX VrefLevel [Byte0]: 52
8728 22:16:57.079092 [Byte1]: 52
8729 22:16:57.082888
8730 22:16:57.082970 Set Vref, RX VrefLevel [Byte0]: 53
8731 22:16:57.086361 [Byte1]: 53
8732 22:16:57.090553
8733 22:16:57.090634 Set Vref, RX VrefLevel [Byte0]: 54
8734 22:16:57.094072 [Byte1]: 54
8735 22:16:57.098636
8736 22:16:57.098721 Set Vref, RX VrefLevel [Byte0]: 55
8737 22:16:57.101510 [Byte1]: 55
8738 22:16:57.105818
8739 22:16:57.105899 Set Vref, RX VrefLevel [Byte0]: 56
8740 22:16:57.108998 [Byte1]: 56
8741 22:16:57.113308
8742 22:16:57.113390 Set Vref, RX VrefLevel [Byte0]: 57
8743 22:16:57.116616 [Byte1]: 57
8744 22:16:57.120854
8745 22:16:57.120936 Set Vref, RX VrefLevel [Byte0]: 58
8746 22:16:57.124657 [Byte1]: 58
8747 22:16:57.128743
8748 22:16:57.128825 Set Vref, RX VrefLevel [Byte0]: 59
8749 22:16:57.132456 [Byte1]: 59
8750 22:16:57.136302
8751 22:16:57.136384 Set Vref, RX VrefLevel [Byte0]: 60
8752 22:16:57.139611 [Byte1]: 60
8753 22:16:57.143992
8754 22:16:57.144074 Set Vref, RX VrefLevel [Byte0]: 61
8755 22:16:57.147416 [Byte1]: 61
8756 22:16:57.151460
8757 22:16:57.151542 Set Vref, RX VrefLevel [Byte0]: 62
8758 22:16:57.155123 [Byte1]: 62
8759 22:16:57.159107
8760 22:16:57.159188 Set Vref, RX VrefLevel [Byte0]: 63
8761 22:16:57.162679 [Byte1]: 63
8762 22:16:57.166843
8763 22:16:57.166924 Set Vref, RX VrefLevel [Byte0]: 64
8764 22:16:57.169965 [Byte1]: 64
8765 22:16:57.174220
8766 22:16:57.174301 Set Vref, RX VrefLevel [Byte0]: 65
8767 22:16:57.177744 [Byte1]: 65
8768 22:16:57.181778
8769 22:16:57.181860 Set Vref, RX VrefLevel [Byte0]: 66
8770 22:16:57.185324 [Byte1]: 66
8771 22:16:57.189977
8772 22:16:57.190058 Set Vref, RX VrefLevel [Byte0]: 67
8773 22:16:57.192924 [Byte1]: 67
8774 22:16:57.197265
8775 22:16:57.197346 Set Vref, RX VrefLevel [Byte0]: 68
8776 22:16:57.200922 [Byte1]: 68
8777 22:16:57.204878
8778 22:16:57.204960 Set Vref, RX VrefLevel [Byte0]: 69
8779 22:16:57.208443 [Byte1]: 69
8780 22:16:57.212600
8781 22:16:57.212681 Final RX Vref Byte 0 = 55 to rank0
8782 22:16:57.215953 Final RX Vref Byte 1 = 54 to rank0
8783 22:16:57.219084 Final RX Vref Byte 0 = 55 to rank1
8784 22:16:57.222405 Final RX Vref Byte 1 = 54 to rank1==
8785 22:16:57.225627 Dram Type= 6, Freq= 0, CH_1, rank 0
8786 22:16:57.232432 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8787 22:16:57.232515 ==
8788 22:16:57.232580 DQS Delay:
8789 22:16:57.235485 DQS0 = 0, DQS1 = 0
8790 22:16:57.235604 DQM Delay:
8791 22:16:57.235676 DQM0 = 131, DQM1 = 123
8792 22:16:57.239036 DQ Delay:
8793 22:16:57.242313 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =128
8794 22:16:57.245727 DQ4 =126, DQ5 =142, DQ6 =142, DQ7 =128
8795 22:16:57.249073 DQ8 =108, DQ9 =112, DQ10 =122, DQ11 =116
8796 22:16:57.252528 DQ12 =132, DQ13 =132, DQ14 =132, DQ15 =132
8797 22:16:57.252696
8798 22:16:57.252782
8799 22:16:57.252864
8800 22:16:57.255424 [DramC_TX_OE_Calibration] TA2
8801 22:16:57.258497 Original DQ_B0 (3 6) =30, OEN = 27
8802 22:16:57.261935 Original DQ_B1 (3 6) =30, OEN = 27
8803 22:16:57.265480 24, 0x0, End_B0=24 End_B1=24
8804 22:16:57.269000 25, 0x0, End_B0=25 End_B1=25
8805 22:16:57.269154 26, 0x0, End_B0=26 End_B1=26
8806 22:16:57.272210 27, 0x0, End_B0=27 End_B1=27
8807 22:16:57.275254 28, 0x0, End_B0=28 End_B1=28
8808 22:16:57.278704 29, 0x0, End_B0=29 End_B1=29
8809 22:16:57.279004 30, 0x0, End_B0=30 End_B1=30
8810 22:16:57.282267 31, 0x4141, End_B0=30 End_B1=30
8811 22:16:57.285094 Byte0 end_step=30 best_step=27
8812 22:16:57.288852 Byte1 end_step=30 best_step=27
8813 22:16:57.291728 Byte0 TX OE(2T, 0.5T) = (3, 3)
8814 22:16:57.295014 Byte1 TX OE(2T, 0.5T) = (3, 3)
8815 22:16:57.295481
8816 22:16:57.295911
8817 22:16:57.301987 [DQSOSCAuto] RK0, (LSB)MR18= 0xb0f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 404 ps
8818 22:16:57.305259 CH1 RK0: MR19=303, MR18=B0F
8819 22:16:57.311902 CH1_RK0: MR19=0x303, MR18=0xB0F, DQSOSC=402, MR23=63, INC=22, DEC=15
8820 22:16:57.312383
8821 22:16:57.314921 ----->DramcWriteLeveling(PI) begin...
8822 22:16:57.315393 ==
8823 22:16:57.318325 Dram Type= 6, Freq= 0, CH_1, rank 1
8824 22:16:57.321572 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8825 22:16:57.322044 ==
8826 22:16:57.324983 Write leveling (Byte 0): 24 => 24
8827 22:16:57.328083 Write leveling (Byte 1): 29 => 29
8828 22:16:57.331531 DramcWriteLeveling(PI) end<-----
8829 22:16:57.332042
8830 22:16:57.332413 ==
8831 22:16:57.334732 Dram Type= 6, Freq= 0, CH_1, rank 1
8832 22:16:57.338013 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8833 22:16:57.341381 ==
8834 22:16:57.341851 [Gating] SW mode calibration
8835 22:16:57.351054 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8836 22:16:57.354179 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8837 22:16:57.357586 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8838 22:16:57.363916 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8839 22:16:57.367634 1 4 8 | B1->B0 | 2322 2f2e | 1 1 | (0 0) (0 0)
8840 22:16:57.371171 1 4 12 | B1->B0 | 3434 3534 | 1 1 | (1 1) (0 0)
8841 22:16:57.377342 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8842 22:16:57.380745 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8843 22:16:57.384582 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8844 22:16:57.390820 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8845 22:16:57.394052 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8846 22:16:57.397457 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8847 22:16:57.403876 1 5 8 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
8848 22:16:57.407014 1 5 12 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
8849 22:16:57.410395 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8850 22:16:57.416885 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8851 22:16:57.420578 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8852 22:16:57.423857 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8853 22:16:57.429874 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8854 22:16:57.433070 1 6 4 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
8855 22:16:57.436761 1 6 8 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
8856 22:16:57.443331 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8857 22:16:57.446201 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8858 22:16:57.449932 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8859 22:16:57.456487 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8860 22:16:57.459350 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8861 22:16:57.462849 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8862 22:16:57.469426 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8863 22:16:57.473117 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8864 22:16:57.475875 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8865 22:16:57.482587 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8866 22:16:57.485869 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8867 22:16:57.489310 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8868 22:16:57.496304 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8869 22:16:57.499087 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8870 22:16:57.502575 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8871 22:16:57.508788 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8872 22:16:57.512483 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8873 22:16:57.518725 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8874 22:16:57.522014 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8875 22:16:57.525534 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8876 22:16:57.531939 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8877 22:16:57.534912 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8878 22:16:57.538227 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8879 22:16:57.545259 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8880 22:16:57.548442 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8881 22:16:57.551311 Total UI for P1: 0, mck2ui 16
8882 22:16:57.554948 best dqsien dly found for B0: ( 1, 9, 8)
8883 22:16:57.558007 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8884 22:16:57.561520 Total UI for P1: 0, mck2ui 16
8885 22:16:57.564750 best dqsien dly found for B1: ( 1, 9, 12)
8886 22:16:57.567765 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8887 22:16:57.571244 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8888 22:16:57.571352
8889 22:16:57.574630 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8890 22:16:57.581030 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8891 22:16:57.581113 [Gating] SW calibration Done
8892 22:16:57.584554 ==
8893 22:16:57.584637 Dram Type= 6, Freq= 0, CH_1, rank 1
8894 22:16:57.591007 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8895 22:16:57.591093 ==
8896 22:16:57.591159 RX Vref Scan: 0
8897 22:16:57.591220
8898 22:16:57.594429 RX Vref 0 -> 0, step: 1
8899 22:16:57.594512
8900 22:16:57.597940 RX Delay 0 -> 252, step: 8
8901 22:16:57.601217 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8902 22:16:57.603938 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8903 22:16:57.607544 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8904 22:16:57.613700 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8905 22:16:57.617132 iDelay=200, Bit 4, Center 123 (64 ~ 183) 120
8906 22:16:57.620341 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8907 22:16:57.623712 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8908 22:16:57.627101 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8909 22:16:57.633555 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8910 22:16:57.636874 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8911 22:16:57.640467 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8912 22:16:57.643819 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8913 22:16:57.650370 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8914 22:16:57.653428 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8915 22:16:57.656700 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8916 22:16:57.660104 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8917 22:16:57.660187 ==
8918 22:16:57.663135 Dram Type= 6, Freq= 0, CH_1, rank 1
8919 22:16:57.669853 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8920 22:16:57.669936 ==
8921 22:16:57.670002 DQS Delay:
8922 22:16:57.672966 DQS0 = 0, DQS1 = 0
8923 22:16:57.673049 DQM Delay:
8924 22:16:57.673115 DQM0 = 132, DQM1 = 129
8925 22:16:57.676318 DQ Delay:
8926 22:16:57.679854 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8927 22:16:57.683286 DQ4 =123, DQ5 =143, DQ6 =143, DQ7 =131
8928 22:16:57.686173 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8929 22:16:57.689702 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =139
8930 22:16:57.689784
8931 22:16:57.689849
8932 22:16:57.689909 ==
8933 22:16:57.692685 Dram Type= 6, Freq= 0, CH_1, rank 1
8934 22:16:57.699712 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8935 22:16:57.699795 ==
8936 22:16:57.699861
8937 22:16:57.699921
8938 22:16:57.699980 TX Vref Scan disable
8939 22:16:57.703019 == TX Byte 0 ==
8940 22:16:57.706143 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8941 22:16:57.712561 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8942 22:16:57.712644 == TX Byte 1 ==
8943 22:16:57.715778 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8944 22:16:57.722528 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8945 22:16:57.722616 ==
8946 22:16:57.725477 Dram Type= 6, Freq= 0, CH_1, rank 1
8947 22:16:57.728778 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8948 22:16:57.728861 ==
8949 22:16:57.743055
8950 22:16:57.746463 TX Vref early break, caculate TX vref
8951 22:16:57.749540 TX Vref=16, minBit 0, minWin=23, winSum=381
8952 22:16:57.752896 TX Vref=18, minBit 0, minWin=23, winSum=387
8953 22:16:57.756155 TX Vref=20, minBit 0, minWin=24, winSum=398
8954 22:16:57.759896 TX Vref=22, minBit 0, minWin=24, winSum=405
8955 22:16:57.763345 TX Vref=24, minBit 0, minWin=25, winSum=414
8956 22:16:57.769326 TX Vref=26, minBit 0, minWin=24, winSum=415
8957 22:16:57.772589 TX Vref=28, minBit 1, minWin=25, winSum=420
8958 22:16:57.775866 TX Vref=30, minBit 0, minWin=25, winSum=418
8959 22:16:57.779135 TX Vref=32, minBit 5, minWin=23, winSum=404
8960 22:16:57.782540 TX Vref=34, minBit 8, minWin=23, winSum=399
8961 22:16:57.786178 TX Vref=36, minBit 1, minWin=22, winSum=390
8962 22:16:57.792642 [TxChooseVref] Worse bit 1, Min win 25, Win sum 420, Final Vref 28
8963 22:16:57.792728
8964 22:16:57.796251 Final TX Range 0 Vref 28
8965 22:16:57.796334
8966 22:16:57.796399 ==
8967 22:16:57.799318 Dram Type= 6, Freq= 0, CH_1, rank 1
8968 22:16:57.802805 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8969 22:16:57.802888 ==
8970 22:16:57.805631
8971 22:16:57.805713
8972 22:16:57.805778 TX Vref Scan disable
8973 22:16:57.812074 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8974 22:16:57.812159 == TX Byte 0 ==
8975 22:16:57.815841 u2DelayCellOfst[0]=18 cells (5 PI)
8976 22:16:57.818833 u2DelayCellOfst[1]=15 cells (4 PI)
8977 22:16:57.822181 u2DelayCellOfst[2]=0 cells (0 PI)
8978 22:16:57.825656 u2DelayCellOfst[3]=7 cells (2 PI)
8979 22:16:57.828711 u2DelayCellOfst[4]=11 cells (3 PI)
8980 22:16:57.832493 u2DelayCellOfst[5]=26 cells (7 PI)
8981 22:16:57.835366 u2DelayCellOfst[6]=22 cells (6 PI)
8982 22:16:57.838887 u2DelayCellOfst[7]=11 cells (3 PI)
8983 22:16:57.841956 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8984 22:16:57.845391 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8985 22:16:57.848758 == TX Byte 1 ==
8986 22:16:57.851939 u2DelayCellOfst[8]=0 cells (0 PI)
8987 22:16:57.855213 u2DelayCellOfst[9]=3 cells (1 PI)
8988 22:16:57.858347 u2DelayCellOfst[10]=11 cells (3 PI)
8989 22:16:57.861566 u2DelayCellOfst[11]=3 cells (1 PI)
8990 22:16:57.865138 u2DelayCellOfst[12]=15 cells (4 PI)
8991 22:16:57.868469 u2DelayCellOfst[13]=15 cells (4 PI)
8992 22:16:57.871630 u2DelayCellOfst[14]=18 cells (5 PI)
8993 22:16:57.874718 u2DelayCellOfst[15]=15 cells (4 PI)
8994 22:16:57.878065 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8995 22:16:57.881421 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8996 22:16:57.884755 DramC Write-DBI on
8997 22:16:57.884838 ==
8998 22:16:57.888109 Dram Type= 6, Freq= 0, CH_1, rank 1
8999 22:16:57.891478 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9000 22:16:57.891561 ==
9001 22:16:57.891670
9002 22:16:57.891730
9003 22:16:57.894556 TX Vref Scan disable
9004 22:16:57.897923 == TX Byte 0 ==
9005 22:16:57.901545 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9006 22:16:57.901628 == TX Byte 1 ==
9007 22:16:57.907923 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
9008 22:16:57.908006 DramC Write-DBI off
9009 22:16:57.908072
9010 22:16:57.908132 [DATLAT]
9011 22:16:57.911284 Freq=1600, CH1 RK1
9012 22:16:57.911367
9013 22:16:57.914565 DATLAT Default: 0xf
9014 22:16:57.914652 0, 0xFFFF, sum = 0
9015 22:16:57.917647 1, 0xFFFF, sum = 0
9016 22:16:57.917731 2, 0xFFFF, sum = 0
9017 22:16:57.921111 3, 0xFFFF, sum = 0
9018 22:16:57.921195 4, 0xFFFF, sum = 0
9019 22:16:57.923996 5, 0xFFFF, sum = 0
9020 22:16:57.924079 6, 0xFFFF, sum = 0
9021 22:16:57.927467 7, 0xFFFF, sum = 0
9022 22:16:57.927589 8, 0xFFFF, sum = 0
9023 22:16:57.930774 9, 0xFFFF, sum = 0
9024 22:16:57.930857 10, 0xFFFF, sum = 0
9025 22:16:57.933899 11, 0xFFFF, sum = 0
9026 22:16:57.933983 12, 0xFFFF, sum = 0
9027 22:16:57.937283 13, 0x8FFF, sum = 0
9028 22:16:57.937367 14, 0x0, sum = 1
9029 22:16:57.940679 15, 0x0, sum = 2
9030 22:16:57.940763 16, 0x0, sum = 3
9031 22:16:57.944131 17, 0x0, sum = 4
9032 22:16:57.944215 best_step = 15
9033 22:16:57.944281
9034 22:16:57.944340 ==
9035 22:16:57.947519 Dram Type= 6, Freq= 0, CH_1, rank 1
9036 22:16:57.953873 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9037 22:16:57.953956 ==
9038 22:16:57.954022 RX Vref Scan: 0
9039 22:16:57.954081
9040 22:16:57.956926 RX Vref 0 -> 0, step: 1
9041 22:16:57.957009
9042 22:16:57.960260 RX Delay 11 -> 252, step: 4
9043 22:16:57.963530 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
9044 22:16:57.966513 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
9045 22:16:57.973110 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
9046 22:16:57.976443 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
9047 22:16:57.979838 iDelay=195, Bit 4, Center 126 (71 ~ 182) 112
9048 22:16:57.983177 iDelay=195, Bit 5, Center 140 (87 ~ 194) 108
9049 22:16:57.990131 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
9050 22:16:57.993277 iDelay=195, Bit 7, Center 126 (75 ~ 178) 104
9051 22:16:57.996656 iDelay=195, Bit 8, Center 110 (55 ~ 166) 112
9052 22:16:57.999729 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
9053 22:16:58.003213 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
9054 22:16:58.009582 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9055 22:16:58.012580 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
9056 22:16:58.015861 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
9057 22:16:58.019106 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
9058 22:16:58.025671 iDelay=195, Bit 15, Center 134 (79 ~ 190) 112
9059 22:16:58.025757 ==
9060 22:16:58.029300 Dram Type= 6, Freq= 0, CH_1, rank 1
9061 22:16:58.032791 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9062 22:16:58.032875 ==
9063 22:16:58.032940 DQS Delay:
9064 22:16:58.035637 DQS0 = 0, DQS1 = 0
9065 22:16:58.035720 DQM Delay:
9066 22:16:58.039181 DQM0 = 129, DQM1 = 125
9067 22:16:58.039270 DQ Delay:
9068 22:16:58.042540 DQ0 =134, DQ1 =128, DQ2 =118, DQ3 =126
9069 22:16:58.045957 DQ4 =126, DQ5 =140, DQ6 =140, DQ7 =126
9070 22:16:58.048863 DQ8 =110, DQ9 =112, DQ10 =128, DQ11 =120
9071 22:16:58.052438 DQ12 =132, DQ13 =136, DQ14 =130, DQ15 =134
9072 22:16:58.052521
9073 22:16:58.052587
9074 22:16:58.055995
9075 22:16:58.056077 [DramC_TX_OE_Calibration] TA2
9076 22:16:58.058871 Original DQ_B0 (3 6) =30, OEN = 27
9077 22:16:58.062209 Original DQ_B1 (3 6) =30, OEN = 27
9078 22:16:58.065366 24, 0x0, End_B0=24 End_B1=24
9079 22:16:58.068604 25, 0x0, End_B0=25 End_B1=25
9080 22:16:58.071876 26, 0x0, End_B0=26 End_B1=26
9081 22:16:58.071959 27, 0x0, End_B0=27 End_B1=27
9082 22:16:58.075210 28, 0x0, End_B0=28 End_B1=28
9083 22:16:58.078550 29, 0x0, End_B0=29 End_B1=29
9084 22:16:58.082030 30, 0x0, End_B0=30 End_B1=30
9085 22:16:58.085466 31, 0x4545, End_B0=30 End_B1=30
9086 22:16:58.085551 Byte0 end_step=30 best_step=27
9087 22:16:58.088240 Byte1 end_step=30 best_step=27
9088 22:16:58.091520 Byte0 TX OE(2T, 0.5T) = (3, 3)
9089 22:16:58.095067 Byte1 TX OE(2T, 0.5T) = (3, 3)
9090 22:16:58.095149
9091 22:16:58.095216
9092 22:16:58.105015 [DQSOSCAuto] RK1, (LSB)MR18= 0x111d, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
9093 22:16:58.105099 CH1 RK1: MR19=303, MR18=111D
9094 22:16:58.111457 CH1_RK1: MR19=0x303, MR18=0x111D, DQSOSC=395, MR23=63, INC=23, DEC=15
9095 22:16:58.115019 [RxdqsGatingPostProcess] freq 1600
9096 22:16:58.121424 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9097 22:16:58.125348 best DQS0 dly(2T, 0.5T) = (1, 1)
9098 22:16:58.128022 best DQS1 dly(2T, 0.5T) = (1, 1)
9099 22:16:58.131394 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9100 22:16:58.134697 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9101 22:16:58.134780 best DQS0 dly(2T, 0.5T) = (1, 1)
9102 22:16:58.137944 best DQS1 dly(2T, 0.5T) = (1, 1)
9103 22:16:58.141055 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9104 22:16:58.144540 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9105 22:16:58.147792 Pre-setting of DQS Precalculation
9106 22:16:58.154475 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9107 22:16:58.160983 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9108 22:16:58.168007 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9109 22:16:58.168091
9110 22:16:58.168156
9111 22:16:58.171259 [Calibration Summary] 3200 Mbps
9112 22:16:58.171342 CH 0, Rank 0
9113 22:16:58.174354 SW Impedance : PASS
9114 22:16:58.177750 DUTY Scan : NO K
9115 22:16:58.177832 ZQ Calibration : PASS
9116 22:16:58.180960 Jitter Meter : NO K
9117 22:16:58.183728 CBT Training : PASS
9118 22:16:58.183811 Write leveling : PASS
9119 22:16:58.187476 RX DQS gating : PASS
9120 22:16:58.190662 RX DQ/DQS(RDDQC) : PASS
9121 22:16:58.190744 TX DQ/DQS : PASS
9122 22:16:58.193986 RX DATLAT : PASS
9123 22:16:58.197365 RX DQ/DQS(Engine): PASS
9124 22:16:58.197448 TX OE : PASS
9125 22:16:58.200610 All Pass.
9126 22:16:58.200693
9127 22:16:58.200758 CH 0, Rank 1
9128 22:16:58.203812 SW Impedance : PASS
9129 22:16:58.203894 DUTY Scan : NO K
9130 22:16:58.207115 ZQ Calibration : PASS
9131 22:16:58.210192 Jitter Meter : NO K
9132 22:16:58.210274 CBT Training : PASS
9133 22:16:58.213503 Write leveling : PASS
9134 22:16:58.217063 RX DQS gating : PASS
9135 22:16:58.217146 RX DQ/DQS(RDDQC) : PASS
9136 22:16:58.220004 TX DQ/DQS : PASS
9137 22:16:58.223371 RX DATLAT : PASS
9138 22:16:58.223454 RX DQ/DQS(Engine): PASS
9139 22:16:58.226726 TX OE : PASS
9140 22:16:58.226809 All Pass.
9141 22:16:58.226873
9142 22:16:58.230362 CH 1, Rank 0
9143 22:16:58.230444 SW Impedance : PASS
9144 22:16:58.233654 DUTY Scan : NO K
9145 22:16:58.236727 ZQ Calibration : PASS
9146 22:16:58.236810 Jitter Meter : NO K
9147 22:16:58.239972 CBT Training : PASS
9148 22:16:58.240056 Write leveling : PASS
9149 22:16:58.243400 RX DQS gating : PASS
9150 22:16:58.246837 RX DQ/DQS(RDDQC) : PASS
9151 22:16:58.246920 TX DQ/DQS : PASS
9152 22:16:58.249806 RX DATLAT : PASS
9153 22:16:58.253164 RX DQ/DQS(Engine): PASS
9154 22:16:58.253246 TX OE : PASS
9155 22:16:58.256503 All Pass.
9156 22:16:58.256585
9157 22:16:58.256651 CH 1, Rank 1
9158 22:16:58.259489 SW Impedance : PASS
9159 22:16:58.259571 DUTY Scan : NO K
9160 22:16:58.262776 ZQ Calibration : PASS
9161 22:16:58.266530 Jitter Meter : NO K
9162 22:16:58.266613 CBT Training : PASS
9163 22:16:58.269422 Write leveling : PASS
9164 22:16:58.272613 RX DQS gating : PASS
9165 22:16:58.272695 RX DQ/DQS(RDDQC) : PASS
9166 22:16:58.275941 TX DQ/DQS : PASS
9167 22:16:58.279462 RX DATLAT : PASS
9168 22:16:58.279561 RX DQ/DQS(Engine): PASS
9169 22:16:58.282545 TX OE : PASS
9170 22:16:58.282628 All Pass.
9171 22:16:58.282694
9172 22:16:58.285877 DramC Write-DBI on
9173 22:16:58.289117 PER_BANK_REFRESH: Hybrid Mode
9174 22:16:58.289200 TX_TRACKING: ON
9175 22:16:58.299205 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9176 22:16:58.306062 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9177 22:16:58.312436 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9178 22:16:58.318834 [FAST_K] Save calibration result to emmc
9179 22:16:58.318917 sync common calibartion params.
9180 22:16:58.322408 sync cbt_mode0:1, 1:1
9181 22:16:58.325807 dram_init: ddr_geometry: 2
9182 22:16:58.325889 dram_init: ddr_geometry: 2
9183 22:16:58.328726 dram_init: ddr_geometry: 2
9184 22:16:58.332125 0:dram_rank_size:100000000
9185 22:16:58.335307 1:dram_rank_size:100000000
9186 22:16:58.339196 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9187 22:16:58.342103 DFS_SHUFFLE_HW_MODE: ON
9188 22:16:58.345176 dramc_set_vcore_voltage set vcore to 725000
9189 22:16:58.348617 Read voltage for 1600, 0
9190 22:16:58.348699 Vio18 = 0
9191 22:16:58.352137 Vcore = 725000
9192 22:16:58.352219 Vdram = 0
9193 22:16:58.352285 Vddq = 0
9194 22:16:58.352345 Vmddr = 0
9195 22:16:58.355072 switch to 3200 Mbps bootup
9196 22:16:58.358723 [DramcRunTimeConfig]
9197 22:16:58.358805 PHYPLL
9198 22:16:58.358870 DPM_CONTROL_AFTERK: ON
9199 22:16:58.362098 PER_BANK_REFRESH: ON
9200 22:16:58.365282 REFRESH_OVERHEAD_REDUCTION: ON
9201 22:16:58.368275 CMD_PICG_NEW_MODE: OFF
9202 22:16:58.368358 XRTWTW_NEW_MODE: ON
9203 22:16:58.371747 XRTRTR_NEW_MODE: ON
9204 22:16:58.371829 TX_TRACKING: ON
9205 22:16:58.374857 RDSEL_TRACKING: OFF
9206 22:16:58.378711 DQS Precalculation for DVFS: ON
9207 22:16:58.378794 RX_TRACKING: OFF
9208 22:16:58.378860 HW_GATING DBG: ON
9209 22:16:58.381433 ZQCS_ENABLE_LP4: ON
9210 22:16:58.384972 RX_PICG_NEW_MODE: ON
9211 22:16:58.385055 TX_PICG_NEW_MODE: ON
9212 22:16:58.388078 ENABLE_RX_DCM_DPHY: ON
9213 22:16:58.391500 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9214 22:16:58.394689 DUMMY_READ_FOR_TRACKING: OFF
9215 22:16:58.394772 !!! SPM_CONTROL_AFTERK: OFF
9216 22:16:58.398017 !!! SPM could not control APHY
9217 22:16:58.401576 IMPEDANCE_TRACKING: ON
9218 22:16:58.401658 TEMP_SENSOR: ON
9219 22:16:58.404727 HW_SAVE_FOR_SR: OFF
9220 22:16:58.407769 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9221 22:16:58.411157 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9222 22:16:58.411239 Read ODT Tracking: ON
9223 22:16:58.414399 Refresh Rate DeBounce: ON
9224 22:16:58.417659 DFS_NO_QUEUE_FLUSH: ON
9225 22:16:58.421137 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9226 22:16:58.421220 ENABLE_DFS_RUNTIME_MRW: OFF
9227 22:16:58.424755 DDR_RESERVE_NEW_MODE: ON
9228 22:16:58.427567 MR_CBT_SWITCH_FREQ: ON
9229 22:16:58.427688 =========================
9230 22:16:58.447905 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9231 22:16:58.451293 dram_init: ddr_geometry: 2
9232 22:16:58.469587 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9233 22:16:58.473027 dram_init: dram init end (result: 0)
9234 22:16:58.479504 DRAM-K: Full calibration passed in 24581 msecs
9235 22:16:58.483086 MRC: failed to locate region type 0.
9236 22:16:58.483169 DRAM rank0 size:0x100000000,
9237 22:16:58.485937 DRAM rank1 size=0x100000000
9238 22:16:58.495736 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9239 22:16:58.502709 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9240 22:16:58.509090 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9241 22:16:58.518821 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9242 22:16:58.518905 DRAM rank0 size:0x100000000,
9243 22:16:58.522080 DRAM rank1 size=0x100000000
9244 22:16:58.522163 CBMEM:
9245 22:16:58.525526 IMD: root @ 0xfffff000 254 entries.
9246 22:16:58.528976 IMD: root @ 0xffffec00 62 entries.
9247 22:16:58.532059 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9248 22:16:58.538883 WARNING: RO_VPD is uninitialized or empty.
9249 22:16:58.542011 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9250 22:16:58.549483 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9251 22:16:58.562130 read SPI 0x42894 0xe01e: 6227 us, 9213 KB/s, 73.704 Mbps
9252 22:16:58.573570 BS: romstage times (exec / console): total (unknown) / 24044 ms
9253 22:16:58.573658
9254 22:16:58.573724
9255 22:16:58.583378 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9256 22:16:58.587116 ARM64: Exception handlers installed.
9257 22:16:58.589911 ARM64: Testing exception
9258 22:16:58.594250 ARM64: Done test exception
9259 22:16:58.594333 Enumerating buses...
9260 22:16:58.596881 Show all devs... Before device enumeration.
9261 22:16:58.600061 Root Device: enabled 1
9262 22:16:58.603603 CPU_CLUSTER: 0: enabled 1
9263 22:16:58.603787 CPU: 00: enabled 1
9264 22:16:58.606512 Compare with tree...
9265 22:16:58.606666 Root Device: enabled 1
9266 22:16:58.610204 CPU_CLUSTER: 0: enabled 1
9267 22:16:58.613575 CPU: 00: enabled 1
9268 22:16:58.613765 Root Device scanning...
9269 22:16:58.616655 scan_static_bus for Root Device
9270 22:16:58.619655 CPU_CLUSTER: 0 enabled
9271 22:16:58.623233 scan_static_bus for Root Device done
9272 22:16:58.626552 scan_bus: bus Root Device finished in 8 msecs
9273 22:16:58.626638 done
9274 22:16:58.633035 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9275 22:16:58.636175 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9276 22:16:58.643160 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9277 22:16:58.649673 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9278 22:16:58.649758 Allocating resources...
9279 22:16:58.652490 Reading resources...
9280 22:16:58.656241 Root Device read_resources bus 0 link: 0
9281 22:16:58.659531 DRAM rank0 size:0x100000000,
9282 22:16:58.659653 DRAM rank1 size=0x100000000
9283 22:16:58.665943 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9284 22:16:58.666026 CPU: 00 missing read_resources
9285 22:16:58.672256 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9286 22:16:58.675704 Root Device read_resources bus 0 link: 0 done
9287 22:16:58.679109 Done reading resources.
9288 22:16:58.682490 Show resources in subtree (Root Device)...After reading.
9289 22:16:58.685378 Root Device child on link 0 CPU_CLUSTER: 0
9290 22:16:58.688739 CPU_CLUSTER: 0 child on link 0 CPU: 00
9291 22:16:58.698855 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9292 22:16:58.698939 CPU: 00
9293 22:16:58.705408 Root Device assign_resources, bus 0 link: 0
9294 22:16:58.708515 CPU_CLUSTER: 0 missing set_resources
9295 22:16:58.711947 Root Device assign_resources, bus 0 link: 0 done
9296 22:16:58.715179 Done setting resources.
9297 22:16:58.718421 Show resources in subtree (Root Device)...After assigning values.
9298 22:16:58.721583 Root Device child on link 0 CPU_CLUSTER: 0
9299 22:16:58.728148 CPU_CLUSTER: 0 child on link 0 CPU: 00
9300 22:16:58.734711 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9301 22:16:58.738221 CPU: 00
9302 22:16:58.738334 Done allocating resources.
9303 22:16:58.744662 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9304 22:16:58.744746 Enabling resources...
9305 22:16:58.748282 done.
9306 22:16:58.751869 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9307 22:16:58.754433 Initializing devices...
9308 22:16:58.754515 Root Device init
9309 22:16:58.758003 init hardware done!
9310 22:16:58.758086 0x00000018: ctrlr->caps
9311 22:16:58.761532 52.000 MHz: ctrlr->f_max
9312 22:16:58.764530 0.400 MHz: ctrlr->f_min
9313 22:16:58.767979 0x40ff8080: ctrlr->voltages
9314 22:16:58.768063 sclk: 390625
9315 22:16:58.768129 Bus Width = 1
9316 22:16:58.770961 sclk: 390625
9317 22:16:58.771044 Bus Width = 1
9318 22:16:58.774200 Early init status = 3
9319 22:16:58.777422 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9320 22:16:58.782127 in-header: 03 fc 00 00 01 00 00 00
9321 22:16:58.785595 in-data: 00
9322 22:16:58.788670 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9323 22:16:58.794709 in-header: 03 fd 00 00 00 00 00 00
9324 22:16:58.797580 in-data:
9325 22:16:58.801160 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9326 22:16:58.805472 in-header: 03 fc 00 00 01 00 00 00
9327 22:16:58.808641 in-data: 00
9328 22:16:58.811912 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9329 22:16:58.817442 in-header: 03 fd 00 00 00 00 00 00
9330 22:16:58.820827 in-data:
9331 22:16:58.824050 [SSUSB] Setting up USB HOST controller...
9332 22:16:58.827314 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9333 22:16:58.830748 [SSUSB] phy power-on done.
9334 22:16:58.834136 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9335 22:16:58.840705 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9336 22:16:58.843996 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9337 22:16:58.851043 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9338 22:16:58.856880 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9339 22:16:58.863567 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9340 22:16:58.870154 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9341 22:16:58.877213 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9342 22:16:58.880171 SPM: binary array size = 0x9dc
9343 22:16:58.883770 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9344 22:16:58.889939 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9345 22:16:58.896575 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9346 22:16:58.903477 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9347 22:16:58.906488 configure_display: Starting display init
9348 22:16:58.940974 anx7625_power_on_init: Init interface.
9349 22:16:58.944234 anx7625_disable_pd_protocol: Disabled PD feature.
9350 22:16:58.947600 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9351 22:16:58.975711 anx7625_start_dp_work: Secure OCM version=00
9352 22:16:58.978530 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9353 22:16:58.993994 sp_tx_get_edid_block: EDID Block = 1
9354 22:16:59.096130 Extracted contents:
9355 22:16:59.099425 header: 00 ff ff ff ff ff ff 00
9356 22:16:59.102779 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9357 22:16:59.105635 version: 01 04
9358 22:16:59.108857 basic params: 95 1f 11 78 0a
9359 22:16:59.112435 chroma info: 76 90 94 55 54 90 27 21 50 54
9360 22:16:59.115670 established: 00 00 00
9361 22:16:59.122468 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9362 22:16:59.128995 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9363 22:16:59.132288 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9364 22:16:59.138845 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9365 22:16:59.145457 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9366 22:16:59.148682 extensions: 00
9367 22:16:59.148763 checksum: fb
9368 22:16:59.148828
9369 22:16:59.152274 Manufacturer: IVO Model 57d Serial Number 0
9370 22:16:59.155133 Made week 0 of 2020
9371 22:16:59.158330 EDID version: 1.4
9372 22:16:59.158411 Digital display
9373 22:16:59.161589 6 bits per primary color channel
9374 22:16:59.161671 DisplayPort interface
9375 22:16:59.165107 Maximum image size: 31 cm x 17 cm
9376 22:16:59.168180 Gamma: 220%
9377 22:16:59.168261 Check DPMS levels
9378 22:16:59.174957 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9379 22:16:59.178238 First detailed timing is preferred timing
9380 22:16:59.181248 Established timings supported:
9381 22:16:59.181329 Standard timings supported:
9382 22:16:59.184804 Detailed timings
9383 22:16:59.188254 Hex of detail: 383680a07038204018303c0035ae10000019
9384 22:16:59.194602 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9385 22:16:59.197695 0780 0798 07c8 0820 hborder 0
9386 22:16:59.201046 0438 043b 0447 0458 vborder 0
9387 22:16:59.204418 -hsync -vsync
9388 22:16:59.204499 Did detailed timing
9389 22:16:59.211158 Hex of detail: 000000000000000000000000000000000000
9390 22:16:59.214118 Manufacturer-specified data, tag 0
9391 22:16:59.217480 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9392 22:16:59.220911 ASCII string: InfoVision
9393 22:16:59.224442 Hex of detail: 000000fe00523134304e574635205248200a
9394 22:16:59.227518 ASCII string: R140NWF5 RH
9395 22:16:59.227635 Checksum
9396 22:16:59.230710 Checksum: 0xfb (valid)
9397 22:16:59.233929 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9398 22:16:59.237465 DSI data_rate: 832800000 bps
9399 22:16:59.243748 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9400 22:16:59.246922 anx7625_parse_edid: pixelclock(138800).
9401 22:16:59.250304 hactive(1920), hsync(48), hfp(24), hbp(88)
9402 22:16:59.253673 vactive(1080), vsync(12), vfp(3), vbp(17)
9403 22:16:59.257026 anx7625_dsi_config: config dsi.
9404 22:16:59.263449 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9405 22:16:59.277811 anx7625_dsi_config: success to config DSI
9406 22:16:59.281367 anx7625_dp_start: MIPI phy setup OK.
9407 22:16:59.284812 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9408 22:16:59.287964 mtk_ddp_mode_set invalid vrefresh 60
9409 22:16:59.291634 main_disp_path_setup
9410 22:16:59.291717 ovl_layer_smi_id_en
9411 22:16:59.294407 ovl_layer_smi_id_en
9412 22:16:59.294508 ccorr_config
9413 22:16:59.294578 aal_config
9414 22:16:59.298075 gamma_config
9415 22:16:59.298163 postmask_config
9416 22:16:59.301763 dither_config
9417 22:16:59.304456 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9418 22:16:59.311407 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9419 22:16:59.314204 Root Device init finished in 555 msecs
9420 22:16:59.317381 CPU_CLUSTER: 0 init
9421 22:16:59.324333 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9422 22:16:59.330687 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9423 22:16:59.330865 APU_MBOX 0x190000b0 = 0x10001
9424 22:16:59.334293 APU_MBOX 0x190001b0 = 0x10001
9425 22:16:59.337272 APU_MBOX 0x190005b0 = 0x10001
9426 22:16:59.340855 APU_MBOX 0x190006b0 = 0x10001
9427 22:16:59.347006 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9428 22:16:59.357477 read SPI 0x539f4 0xe237: 6250 us, 9265 KB/s, 74.120 Mbps
9429 22:16:59.369730 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9430 22:16:59.376610 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9431 22:16:59.387819 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9432 22:16:59.397246 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9433 22:16:59.400266 CPU_CLUSTER: 0 init finished in 81 msecs
9434 22:16:59.403644 Devices initialized
9435 22:16:59.407146 Show all devs... After init.
9436 22:16:59.407666 Root Device: enabled 1
9437 22:16:59.410417 CPU_CLUSTER: 0: enabled 1
9438 22:16:59.413264 CPU: 00: enabled 1
9439 22:16:59.416826 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9440 22:16:59.420054 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9441 22:16:59.423642 ELOG: NV offset 0x57f000 size 0x1000
9442 22:16:59.430286 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9443 22:16:59.436605 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9444 22:16:59.440063 ELOG: Event(17) added with size 13 at 2023-06-04 22:16:59 UTC
9445 22:16:59.446600 out: cmd=0x121: 03 db 21 01 00 00 00 00
9446 22:16:59.449561 in-header: 03 4c 00 00 2c 00 00 00
9447 22:16:59.459392 in-data: 12 69 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9448 22:16:59.466045 ELOG: Event(A1) added with size 10 at 2023-06-04 22:16:59 UTC
9449 22:16:59.472666 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9450 22:16:59.479575 ELOG: Event(A0) added with size 9 at 2023-06-04 22:16:59 UTC
9451 22:16:59.482998 elog_add_boot_reason: Logged dev mode boot
9452 22:16:59.489278 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9453 22:16:59.489460 Finalize devices...
9454 22:16:59.492418 Devices finalized
9455 22:16:59.495825 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9456 22:16:59.499269 Writing coreboot table at 0xffe64000
9457 22:16:59.502251 0. 000000000010a000-0000000000113fff: RAMSTAGE
9458 22:16:59.509211 1. 0000000040000000-00000000400fffff: RAM
9459 22:16:59.512532 2. 0000000040100000-000000004032afff: RAMSTAGE
9460 22:16:59.515776 3. 000000004032b000-00000000545fffff: RAM
9461 22:16:59.518741 4. 0000000054600000-000000005465ffff: BL31
9462 22:16:59.522046 5. 0000000054660000-00000000ffe63fff: RAM
9463 22:16:59.529150 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9464 22:16:59.532184 7. 0000000100000000-000000023fffffff: RAM
9465 22:16:59.535438 Passing 5 GPIOs to payload:
9466 22:16:59.538621 NAME | PORT | POLARITY | VALUE
9467 22:16:59.545453 EC in RW | 0x000000aa | low | undefined
9468 22:16:59.548486 EC interrupt | 0x00000005 | low | undefined
9469 22:16:59.554901 TPM interrupt | 0x000000ab | high | undefined
9470 22:16:59.558111 SD card detect | 0x00000011 | high | undefined
9471 22:16:59.561966 speaker enable | 0x00000093 | high | undefined
9472 22:16:59.564938 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9473 22:16:59.568536 in-header: 03 f9 00 00 02 00 00 00
9474 22:16:59.571978 in-data: 02 00
9475 22:16:59.575379 ADC[4]: Raw value=897780 ID=7
9476 22:16:59.578684 ADC[3]: Raw value=212700 ID=1
9477 22:16:59.579106 RAM Code: 0x71
9478 22:16:59.582062 ADC[6]: Raw value=74722 ID=0
9479 22:16:59.585142 ADC[5]: Raw value=212700 ID=1
9480 22:16:59.585611 SKU Code: 0x1
9481 22:16:59.592071 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 7dbf
9482 22:16:59.592542 coreboot table: 964 bytes.
9483 22:16:59.594933 IMD ROOT 0. 0xfffff000 0x00001000
9484 22:16:59.598440 IMD SMALL 1. 0xffffe000 0x00001000
9485 22:16:59.601451 RO MCACHE 2. 0xffffc000 0x00001104
9486 22:16:59.604937 CONSOLE 3. 0xfff7c000 0x00080000
9487 22:16:59.608312 FMAP 4. 0xfff7b000 0x00000452
9488 22:16:59.611414 TIME STAMP 5. 0xfff7a000 0x00000910
9489 22:16:59.614757 VBOOT WORK 6. 0xfff66000 0x00014000
9490 22:16:59.617703 RAMOOPS 7. 0xffe66000 0x00100000
9491 22:16:59.621444 COREBOOT 8. 0xffe64000 0x00002000
9492 22:16:59.624554 IMD small region:
9493 22:16:59.627933 IMD ROOT 0. 0xffffec00 0x00000400
9494 22:16:59.631223 VPD 1. 0xffffeba0 0x0000004c
9495 22:16:59.634659 MMC STATUS 2. 0xffffeb80 0x00000004
9496 22:16:59.640417 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9497 22:16:59.640505 Probing TPM: done!
9498 22:16:59.647470 Connected to device vid:did:rid of 1ae0:0028:00
9499 22:16:59.654399 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9500 22:16:59.657802 Initialized TPM device CR50 revision 0
9501 22:16:59.661177 Checking cr50 for pending updates
9502 22:16:59.666519 Reading cr50 TPM mode
9503 22:16:59.674620 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9504 22:16:59.681434 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9505 22:16:59.721936 read SPI 0x3990ec 0x4f1b0: 34859 us, 9295 KB/s, 74.360 Mbps
9506 22:16:59.725233 Checking segment from ROM address 0x40100000
9507 22:16:59.728227 Checking segment from ROM address 0x4010001c
9508 22:16:59.735250 Loading segment from ROM address 0x40100000
9509 22:16:59.735333 code (compression=0)
9510 22:16:59.745332 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9511 22:16:59.751477 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9512 22:16:59.751569 it's not compressed!
9513 22:16:59.758323 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9514 22:16:59.764875 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9515 22:16:59.782679 Loading segment from ROM address 0x4010001c
9516 22:16:59.782835 Entry Point 0x80000000
9517 22:16:59.785295 Loaded segments
9518 22:16:59.788922 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9519 22:16:59.795620 Jumping to boot code at 0x80000000(0xffe64000)
9520 22:16:59.802219 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9521 22:16:59.809087 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9522 22:16:59.816867 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9523 22:16:59.820586 Checking segment from ROM address 0x40100000
9524 22:16:59.823494 Checking segment from ROM address 0x4010001c
9525 22:16:59.830646 Loading segment from ROM address 0x40100000
9526 22:16:59.831120 code (compression=1)
9527 22:16:59.836603 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9528 22:16:59.846422 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9529 22:16:59.846894 using LZMA
9530 22:16:59.855559 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9531 22:16:59.862106 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9532 22:16:59.865103 Loading segment from ROM address 0x4010001c
9533 22:16:59.865530 Entry Point 0x54601000
9534 22:16:59.868382 Loaded segments
9535 22:16:59.871530 NOTICE: MT8192 bl31_setup
9536 22:16:59.878944 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9537 22:16:59.882289 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9538 22:16:59.885557 WARNING: region 0:
9539 22:16:59.888792 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9540 22:16:59.889221 WARNING: region 1:
9541 22:16:59.895837 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9542 22:16:59.898567 WARNING: region 2:
9543 22:16:59.902266 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9544 22:16:59.905202 WARNING: region 3:
9545 22:16:59.908780 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9546 22:16:59.912156 WARNING: region 4:
9547 22:16:59.918313 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9548 22:16:59.918736 WARNING: region 5:
9549 22:16:59.922052 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9550 22:16:59.925694 WARNING: region 6:
9551 22:16:59.928881 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9552 22:16:59.931700 WARNING: region 7:
9553 22:16:59.935002 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9554 22:16:59.942050 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9555 22:16:59.945239 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9556 22:16:59.948639 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9557 22:16:59.955282 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9558 22:16:59.958539 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9559 22:16:59.961759 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9560 22:16:59.969024 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9561 22:16:59.971563 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9562 22:16:59.978900 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9563 22:16:59.982060 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9564 22:16:59.985035 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9565 22:16:59.991506 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9566 22:16:59.994820 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9567 22:16:59.998139 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9568 22:17:00.005291 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9569 22:17:00.008473 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9570 22:17:00.015050 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9571 22:17:00.018378 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9572 22:17:00.021941 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9573 22:17:00.028371 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9574 22:17:00.031934 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9575 22:17:00.038062 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9576 22:17:00.041601 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9577 22:17:00.044779 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9578 22:17:00.051358 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9579 22:17:00.055030 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9580 22:17:00.061352 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9581 22:17:00.064793 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9582 22:17:00.068496 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9583 22:17:00.074624 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9584 22:17:00.077875 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9585 22:17:00.084574 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9586 22:17:00.087884 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9587 22:17:00.091123 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9588 22:17:00.094506 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9589 22:17:00.100898 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9590 22:17:00.104118 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9591 22:17:00.107437 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9592 22:17:00.110837 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9593 22:17:00.117910 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9594 22:17:00.121082 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9595 22:17:00.123970 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9596 22:17:00.127763 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9597 22:17:00.133952 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9598 22:17:00.137318 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9599 22:17:00.140826 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9600 22:17:00.144299 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9601 22:17:00.150645 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9602 22:17:00.153540 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9603 22:17:00.160547 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9604 22:17:00.164166 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9605 22:17:00.167336 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9606 22:17:00.174290 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9607 22:17:00.177124 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9608 22:17:00.183459 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9609 22:17:00.187249 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9610 22:17:00.193579 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9611 22:17:00.196864 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9612 22:17:00.203982 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9613 22:17:00.207395 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9614 22:17:00.210109 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9615 22:17:00.217099 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9616 22:17:00.220492 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9617 22:17:00.227044 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9618 22:17:00.230216 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9619 22:17:00.237030 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9620 22:17:00.239994 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9621 22:17:00.246645 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9622 22:17:00.250100 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9623 22:17:00.253205 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9624 22:17:00.259702 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9625 22:17:00.263052 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9626 22:17:00.269644 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9627 22:17:00.272766 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9628 22:17:00.279505 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9629 22:17:00.282885 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9630 22:17:00.286445 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9631 22:17:00.293016 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9632 22:17:00.295962 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9633 22:17:00.302985 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9634 22:17:00.306262 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9635 22:17:00.312839 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9636 22:17:00.316268 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9637 22:17:00.323043 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9638 22:17:00.326466 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9639 22:17:00.329777 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9640 22:17:00.336208 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9641 22:17:00.339491 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9642 22:17:00.346068 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9643 22:17:00.349257 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9644 22:17:00.356420 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9645 22:17:00.359226 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9646 22:17:00.366348 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9647 22:17:00.369308 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9648 22:17:00.372593 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9649 22:17:00.378990 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9650 22:17:00.382572 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9651 22:17:00.385926 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9652 22:17:00.392287 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9653 22:17:00.395784 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9654 22:17:00.399164 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9655 22:17:00.405947 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9656 22:17:00.409041 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9657 22:17:00.412358 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9658 22:17:00.419124 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9659 22:17:00.422472 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9660 22:17:00.428854 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9661 22:17:00.432265 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9662 22:17:00.435757 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9663 22:17:00.442269 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9664 22:17:00.445275 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9665 22:17:00.451702 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9666 22:17:00.455527 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9667 22:17:00.458422 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9668 22:17:00.465513 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9669 22:17:00.468447 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9670 22:17:00.471856 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9671 22:17:00.478308 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9672 22:17:00.481860 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9673 22:17:00.485080 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9674 22:17:00.492072 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9675 22:17:00.494931 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9676 22:17:00.498537 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9677 22:17:00.501489 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9678 22:17:00.508857 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9679 22:17:00.511930 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9680 22:17:00.518086 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9681 22:17:00.521389 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9682 22:17:00.524568 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9683 22:17:00.531288 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9684 22:17:00.534918 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9685 22:17:00.538539 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9686 22:17:00.544941 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9687 22:17:00.548082 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9688 22:17:00.554764 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9689 22:17:00.557666 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9690 22:17:00.564706 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9691 22:17:00.567940 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9692 22:17:00.571650 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9693 22:17:00.577928 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9694 22:17:00.580871 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9695 22:17:00.584461 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9696 22:17:00.591245 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9697 22:17:00.594648 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9698 22:17:00.600836 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9699 22:17:00.604222 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9700 22:17:00.607958 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9701 22:17:00.614311 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9702 22:17:00.617618 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9703 22:17:00.623936 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9704 22:17:00.627519 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9705 22:17:00.630741 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9706 22:17:00.637294 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9707 22:17:00.640958 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9708 22:17:00.647332 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9709 22:17:00.650586 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9710 22:17:00.654386 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9711 22:17:00.660746 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9712 22:17:00.664132 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9713 22:17:00.670734 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9714 22:17:00.673833 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9715 22:17:00.677331 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9716 22:17:00.683590 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9717 22:17:00.687075 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9718 22:17:00.693352 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9719 22:17:00.696757 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9720 22:17:00.700081 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9721 22:17:00.706819 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9722 22:17:00.710266 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9723 22:17:00.716772 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9724 22:17:00.719782 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9725 22:17:00.723334 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9726 22:17:00.730221 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9727 22:17:00.732993 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9728 22:17:00.739872 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9729 22:17:00.743055 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9730 22:17:00.746488 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9731 22:17:00.752812 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9732 22:17:00.756267 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9733 22:17:00.762847 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9734 22:17:00.766109 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9735 22:17:00.769694 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9736 22:17:00.775876 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9737 22:17:00.779418 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9738 22:17:00.786118 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9739 22:17:00.788935 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9740 22:17:00.792550 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9741 22:17:00.798925 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9742 22:17:00.802557 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9743 22:17:00.808653 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9744 22:17:00.812090 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9745 22:17:00.818906 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9746 22:17:00.821949 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9747 22:17:00.825436 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9748 22:17:00.832129 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9749 22:17:00.835542 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9750 22:17:00.842055 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9751 22:17:00.845075 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9752 22:17:00.851483 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9753 22:17:00.855209 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9754 22:17:00.858449 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9755 22:17:00.864918 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9756 22:17:00.868363 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9757 22:17:00.874644 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9758 22:17:00.878342 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9759 22:17:00.884777 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9760 22:17:00.888324 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9761 22:17:00.891595 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9762 22:17:00.898160 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9763 22:17:00.901348 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9764 22:17:00.908215 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9765 22:17:00.911284 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9766 22:17:00.917661 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9767 22:17:00.920914 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9768 22:17:00.924220 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9769 22:17:00.930622 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9770 22:17:00.934194 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9771 22:17:00.940793 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9772 22:17:00.944030 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9773 22:17:00.950786 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9774 22:17:00.953920 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9775 22:17:00.957289 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9776 22:17:00.963804 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9777 22:17:00.967012 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9778 22:17:00.973621 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9779 22:17:00.976886 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9780 22:17:00.980161 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9781 22:17:00.986613 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9782 22:17:00.990168 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9783 22:17:00.996521 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9784 22:17:01.000135 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9785 22:17:01.003469 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9786 22:17:01.006504 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9787 22:17:01.010036 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9788 22:17:01.016863 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9789 22:17:01.019563 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9790 22:17:01.026493 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9791 22:17:01.029571 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9792 22:17:01.032914 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9793 22:17:01.039688 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9794 22:17:01.042790 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9795 22:17:01.046110 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9796 22:17:01.053020 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9797 22:17:01.056069 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9798 22:17:01.062661 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9799 22:17:01.066379 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9800 22:17:01.069751 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9801 22:17:01.075964 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9802 22:17:01.079022 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9803 22:17:01.082516 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9804 22:17:01.088966 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9805 22:17:01.092381 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9806 22:17:01.098824 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9807 22:17:01.102278 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9808 22:17:01.105810 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9809 22:17:01.112153 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9810 22:17:01.115645 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9811 22:17:01.121983 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9812 22:17:01.125247 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9813 22:17:01.128561 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9814 22:17:01.135576 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9815 22:17:01.138425 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9816 22:17:01.141748 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9817 22:17:01.148827 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9818 22:17:01.151666 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9819 22:17:01.155207 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9820 22:17:01.161659 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9821 22:17:01.165100 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9822 22:17:01.171402 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9823 22:17:01.174545 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9824 22:17:01.177900 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9825 22:17:01.181300 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9826 22:17:01.184782 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9827 22:17:01.191217 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9828 22:17:01.194293 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9829 22:17:01.197710 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9830 22:17:01.200914 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9831 22:17:01.207598 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9832 22:17:01.211213 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9833 22:17:01.214175 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9834 22:17:01.221244 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9835 22:17:01.224142 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9836 22:17:01.227487 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9837 22:17:01.234121 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9838 22:17:01.237535 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9839 22:17:01.243709 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9840 22:17:01.247306 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9841 22:17:01.250620 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9842 22:17:01.257115 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9843 22:17:01.260592 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9844 22:17:01.266915 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9845 22:17:01.270548 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9846 22:17:01.277114 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9847 22:17:01.280562 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9848 22:17:01.283790 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9849 22:17:01.290460 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9850 22:17:01.293189 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9851 22:17:01.299884 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9852 22:17:01.303608 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9853 22:17:01.306962 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9854 22:17:01.313247 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9855 22:17:01.316222 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9856 22:17:01.322829 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9857 22:17:01.326367 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9858 22:17:01.333310 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9859 22:17:01.336732 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9860 22:17:01.339487 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9861 22:17:01.346355 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9862 22:17:01.349622 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9863 22:17:01.356063 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9864 22:17:01.359600 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9865 22:17:01.366132 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9866 22:17:01.369402 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9867 22:17:01.372681 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9868 22:17:01.379359 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9869 22:17:01.382563 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9870 22:17:01.389231 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9871 22:17:01.392572 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9872 22:17:01.395366 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9873 22:17:01.402540 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9874 22:17:01.405233 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9875 22:17:01.412368 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9876 22:17:01.415328 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9877 22:17:01.418770 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9878 22:17:01.425435 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9879 22:17:01.428289 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9880 22:17:01.435404 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9881 22:17:01.438338 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9882 22:17:01.444807 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9883 22:17:01.448039 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9884 22:17:01.451539 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9885 22:17:01.457784 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9886 22:17:01.461165 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9887 22:17:01.467691 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9888 22:17:01.471160 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9889 22:17:01.477874 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9890 22:17:01.480996 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9891 22:17:01.484340 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9892 22:17:01.491080 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9893 22:17:01.494257 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9894 22:17:01.500669 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9895 22:17:01.504396 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9896 22:17:01.510604 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9897 22:17:01.514067 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9898 22:17:01.517330 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9899 22:17:01.523855 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9900 22:17:01.527112 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9901 22:17:01.533727 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9902 22:17:01.536796 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9903 22:17:01.540360 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9904 22:17:01.547166 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9905 22:17:01.550371 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9906 22:17:01.556322 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9907 22:17:01.559824 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9908 22:17:01.566474 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9909 22:17:01.569592 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9910 22:17:01.576405 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9911 22:17:01.579920 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9912 22:17:01.582914 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9913 22:17:01.589356 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9914 22:17:01.593301 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9915 22:17:01.599283 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9916 22:17:01.602714 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9917 22:17:01.609109 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9918 22:17:01.612789 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9919 22:17:01.618978 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9920 22:17:01.622598 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9921 22:17:01.626056 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9922 22:17:01.632557 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9923 22:17:01.636088 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9924 22:17:01.642536 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9925 22:17:01.645460 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9926 22:17:01.652156 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9927 22:17:01.655686 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9928 22:17:01.661726 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9929 22:17:01.665415 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9930 22:17:01.671450 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9931 22:17:01.675019 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9932 22:17:01.678571 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9933 22:17:01.684963 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9934 22:17:01.687995 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9935 22:17:01.694856 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9936 22:17:01.697862 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9937 22:17:01.704571 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9938 22:17:01.707629 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9939 22:17:01.710990 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9940 22:17:01.718100 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9941 22:17:01.721304 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9942 22:17:01.727472 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9943 22:17:01.731004 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9944 22:17:01.737551 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9945 22:17:01.740948 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9946 22:17:01.747517 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9947 22:17:01.751012 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9948 22:17:01.754108 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9949 22:17:01.760925 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9950 22:17:01.764234 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9951 22:17:01.770458 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9952 22:17:01.773732 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9953 22:17:01.780661 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9954 22:17:01.783741 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9955 22:17:01.790265 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9956 22:17:01.793771 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9957 22:17:01.797668 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9958 22:17:01.803348 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9959 22:17:01.806750 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9960 22:17:01.813557 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9961 22:17:01.816830 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9962 22:17:01.823660 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9963 22:17:01.826966 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9964 22:17:01.833387 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9965 22:17:01.836551 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9966 22:17:01.843478 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9967 22:17:01.846436 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9968 22:17:01.852847 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9969 22:17:01.856367 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9970 22:17:01.862896 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9971 22:17:01.866084 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9972 22:17:01.873076 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9973 22:17:01.875848 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9974 22:17:01.882761 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9975 22:17:01.885997 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9976 22:17:01.892994 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9977 22:17:01.896242 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9978 22:17:01.902905 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9979 22:17:01.906188 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9980 22:17:01.912654 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9981 22:17:01.915882 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9982 22:17:01.922519 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9983 22:17:01.925869 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9984 22:17:01.932499 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9985 22:17:01.935815 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9986 22:17:01.942326 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9987 22:17:01.945180 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9988 22:17:01.952088 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9989 22:17:01.952172 INFO: [APUAPC] vio 0
9990 22:17:01.958672 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9991 22:17:01.961679 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9992 22:17:01.965192 INFO: [APUAPC] D0_APC_0: 0x400510
9993 22:17:01.968727 INFO: [APUAPC] D0_APC_1: 0x0
9994 22:17:01.971692 INFO: [APUAPC] D0_APC_2: 0x1540
9995 22:17:01.975181 INFO: [APUAPC] D0_APC_3: 0x0
9996 22:17:01.978574 INFO: [APUAPC] D1_APC_0: 0xffffffff
9997 22:17:01.981930 INFO: [APUAPC] D1_APC_1: 0xffffffff
9998 22:17:01.984850 INFO: [APUAPC] D1_APC_2: 0x3fffff
9999 22:17:01.988240 INFO: [APUAPC] D1_APC_3: 0x0
10000 22:17:01.992142 INFO: [APUAPC] D2_APC_0: 0xffffffff
10001 22:17:01.994866 INFO: [APUAPC] D2_APC_1: 0xffffffff
10002 22:17:01.998328 INFO: [APUAPC] D2_APC_2: 0x3fffff
10003 22:17:02.001684 INFO: [APUAPC] D2_APC_3: 0x0
10004 22:17:02.004724 INFO: [APUAPC] D3_APC_0: 0xffffffff
10005 22:17:02.008317 INFO: [APUAPC] D3_APC_1: 0xffffffff
10006 22:17:02.011670 INFO: [APUAPC] D3_APC_2: 0x3fffff
10007 22:17:02.015092 INFO: [APUAPC] D3_APC_3: 0x0
10008 22:17:02.018289 INFO: [APUAPC] D4_APC_0: 0xffffffff
10009 22:17:02.021473 INFO: [APUAPC] D4_APC_1: 0xffffffff
10010 22:17:02.025134 INFO: [APUAPC] D4_APC_2: 0x3fffff
10011 22:17:02.025217 INFO: [APUAPC] D4_APC_3: 0x0
10012 22:17:02.031224 INFO: [APUAPC] D5_APC_0: 0xffffffff
10013 22:17:02.034630 INFO: [APUAPC] D5_APC_1: 0xffffffff
10014 22:17:02.038240 INFO: [APUAPC] D5_APC_2: 0x3fffff
10015 22:17:02.038325 INFO: [APUAPC] D5_APC_3: 0x0
10016 22:17:02.040976 INFO: [APUAPC] D6_APC_0: 0xffffffff
10017 22:17:02.048056 INFO: [APUAPC] D6_APC_1: 0xffffffff
10018 22:17:02.051138 INFO: [APUAPC] D6_APC_2: 0x3fffff
10019 22:17:02.051221 INFO: [APUAPC] D6_APC_3: 0x0
10020 22:17:02.054703 INFO: [APUAPC] D7_APC_0: 0xffffffff
10021 22:17:02.057682 INFO: [APUAPC] D7_APC_1: 0xffffffff
10022 22:17:02.061062 INFO: [APUAPC] D7_APC_2: 0x3fffff
10023 22:17:02.064162 INFO: [APUAPC] D7_APC_3: 0x0
10024 22:17:02.067484 INFO: [APUAPC] D8_APC_0: 0xffffffff
10025 22:17:02.071085 INFO: [APUAPC] D8_APC_1: 0xffffffff
10026 22:17:02.074536 INFO: [APUAPC] D8_APC_2: 0x3fffff
10027 22:17:02.077870 INFO: [APUAPC] D8_APC_3: 0x0
10028 22:17:02.081196 INFO: [APUAPC] D9_APC_0: 0xffffffff
10029 22:17:02.084000 INFO: [APUAPC] D9_APC_1: 0xffffffff
10030 22:17:02.087791 INFO: [APUAPC] D9_APC_2: 0x3fffff
10031 22:17:02.090470 INFO: [APUAPC] D9_APC_3: 0x0
10032 22:17:02.094127 INFO: [APUAPC] D10_APC_0: 0xffffffff
10033 22:17:02.097035 INFO: [APUAPC] D10_APC_1: 0xffffffff
10034 22:17:02.100869 INFO: [APUAPC] D10_APC_2: 0x3fffff
10035 22:17:02.103790 INFO: [APUAPC] D10_APC_3: 0x0
10036 22:17:02.107318 INFO: [APUAPC] D11_APC_0: 0xffffffff
10037 22:17:02.110688 INFO: [APUAPC] D11_APC_1: 0xffffffff
10038 22:17:02.113754 INFO: [APUAPC] D11_APC_2: 0x3fffff
10039 22:17:02.117380 INFO: [APUAPC] D11_APC_3: 0x0
10040 22:17:02.120478 INFO: [APUAPC] D12_APC_0: 0xffffffff
10041 22:17:02.123900 INFO: [APUAPC] D12_APC_1: 0xffffffff
10042 22:17:02.127457 INFO: [APUAPC] D12_APC_2: 0x3fffff
10043 22:17:02.130558 INFO: [APUAPC] D12_APC_3: 0x0
10044 22:17:02.133820 INFO: [APUAPC] D13_APC_0: 0xffffffff
10045 22:17:02.137107 INFO: [APUAPC] D13_APC_1: 0xffffffff
10046 22:17:02.140467 INFO: [APUAPC] D13_APC_2: 0x3fffff
10047 22:17:02.143846 INFO: [APUAPC] D13_APC_3: 0x0
10048 22:17:02.147001 INFO: [APUAPC] D14_APC_0: 0xffffffff
10049 22:17:02.150229 INFO: [APUAPC] D14_APC_1: 0xffffffff
10050 22:17:02.153659 INFO: [APUAPC] D14_APC_2: 0x3fffff
10051 22:17:02.156837 INFO: [APUAPC] D14_APC_3: 0x0
10052 22:17:02.160110 INFO: [APUAPC] D15_APC_0: 0xffffffff
10053 22:17:02.166680 INFO: [APUAPC] D15_APC_1: 0xffffffff
10054 22:17:02.170214 INFO: [APUAPC] D15_APC_2: 0x3fffff
10055 22:17:02.170297 INFO: [APUAPC] D15_APC_3: 0x0
10056 22:17:02.173745 INFO: [APUAPC] APC_CON: 0x4
10057 22:17:02.176445 INFO: [NOCDAPC] D0_APC_0: 0x0
10058 22:17:02.180195 INFO: [NOCDAPC] D0_APC_1: 0x0
10059 22:17:02.183581 INFO: [NOCDAPC] D1_APC_0: 0x0
10060 22:17:02.186717 INFO: [NOCDAPC] D1_APC_1: 0xfff
10061 22:17:02.189793 INFO: [NOCDAPC] D2_APC_0: 0x0
10062 22:17:02.193313 INFO: [NOCDAPC] D2_APC_1: 0xfff
10063 22:17:02.196903 INFO: [NOCDAPC] D3_APC_0: 0x0
10064 22:17:02.199859 INFO: [NOCDAPC] D3_APC_1: 0xfff
10065 22:17:02.199943 INFO: [NOCDAPC] D4_APC_0: 0x0
10066 22:17:02.203266 INFO: [NOCDAPC] D4_APC_1: 0xfff
10067 22:17:02.206458 INFO: [NOCDAPC] D5_APC_0: 0x0
10068 22:17:02.210101 INFO: [NOCDAPC] D5_APC_1: 0xfff
10069 22:17:02.213413 INFO: [NOCDAPC] D6_APC_0: 0x0
10070 22:17:02.216130 INFO: [NOCDAPC] D6_APC_1: 0xfff
10071 22:17:02.219713 INFO: [NOCDAPC] D7_APC_0: 0x0
10072 22:17:02.223182 INFO: [NOCDAPC] D7_APC_1: 0xfff
10073 22:17:02.226130 INFO: [NOCDAPC] D8_APC_0: 0x0
10074 22:17:02.229280 INFO: [NOCDAPC] D8_APC_1: 0xfff
10075 22:17:02.233036 INFO: [NOCDAPC] D9_APC_0: 0x0
10076 22:17:02.236270 INFO: [NOCDAPC] D9_APC_1: 0xfff
10077 22:17:02.236353 INFO: [NOCDAPC] D10_APC_0: 0x0
10078 22:17:02.239121 INFO: [NOCDAPC] D10_APC_1: 0xfff
10079 22:17:02.242740 INFO: [NOCDAPC] D11_APC_0: 0x0
10080 22:17:02.245613 INFO: [NOCDAPC] D11_APC_1: 0xfff
10081 22:17:02.249008 INFO: [NOCDAPC] D12_APC_0: 0x0
10082 22:17:02.252279 INFO: [NOCDAPC] D12_APC_1: 0xfff
10083 22:17:02.256169 INFO: [NOCDAPC] D13_APC_0: 0x0
10084 22:17:02.259374 INFO: [NOCDAPC] D13_APC_1: 0xfff
10085 22:17:02.262628 INFO: [NOCDAPC] D14_APC_0: 0x0
10086 22:17:02.266086 INFO: [NOCDAPC] D14_APC_1: 0xfff
10087 22:17:02.269094 INFO: [NOCDAPC] D15_APC_0: 0x0
10088 22:17:02.272815 INFO: [NOCDAPC] D15_APC_1: 0xfff
10089 22:17:02.275843 INFO: [NOCDAPC] APC_CON: 0x4
10090 22:17:02.279285 INFO: [APUAPC] set_apusys_apc done
10091 22:17:02.282359 INFO: [DEVAPC] devapc_init done
10092 22:17:02.285765 INFO: GICv3 without legacy support detected.
10093 22:17:02.288763 INFO: ARM GICv3 driver initialized in EL3
10094 22:17:02.292242 INFO: Maximum SPI INTID supported: 639
10095 22:17:02.295318 INFO: BL31: Initializing runtime services
10096 22:17:02.302255 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10097 22:17:02.305376 INFO: SPM: enable CPC mode
10098 22:17:02.311902 INFO: mcdi ready for mcusys-off-idle and system suspend
10099 22:17:02.315440 INFO: BL31: Preparing for EL3 exit to normal world
10100 22:17:02.319097 INFO: Entry point address = 0x80000000
10101 22:17:02.322031 INFO: SPSR = 0x8
10102 22:17:02.326889
10103 22:17:02.327282
10104 22:17:02.327629
10105 22:17:02.330253 Starting depthcharge on Spherion...
10106 22:17:02.330722
10107 22:17:02.331097 Wipe memory regions:
10108 22:17:02.331453
10109 22:17:02.335211 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10110 22:17:02.335856 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10111 22:17:02.336319 Setting prompt string to ['asurada:']
10112 22:17:02.336794 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10113 22:17:02.337812 [0x00000040000000, 0x00000054600000)
10114 22:17:02.455406
10115 22:17:02.455656 [0x00000054660000, 0x00000080000000)
10116 22:17:02.716158
10117 22:17:02.716427 [0x000000821a7280, 0x000000ffe64000)
10118 22:17:03.460836
10119 22:17:03.461433 [0x00000100000000, 0x00000240000000)
10120 22:17:05.349391
10121 22:17:05.352693 Initializing XHCI USB controller at 0x11200000.
10122 22:17:06.391026
10123 22:17:06.394449 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10124 22:17:06.394801
10125 22:17:06.395045
10126 22:17:06.395271
10127 22:17:06.395849 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10129 22:17:06.496761 asurada: tftpboot 192.168.201.1 10583921/tftp-deploy-y7em0uqj/kernel/image.itb 10583921/tftp-deploy-y7em0uqj/kernel/cmdline
10130 22:17:06.497402 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10131 22:17:06.497854 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10132 22:17:06.502154 tftpboot 192.168.201.1 10583921/tftp-deploy-y7em0uqj/kernel/image.itp-deploy-y7em0uqj/kernel/cmdline
10133 22:17:06.502636
10134 22:17:06.503007 Waiting for link
10135 22:17:06.662642
10136 22:17:06.662925 R8152: Initializing
10137 22:17:06.663102
10138 22:17:06.665841 Version 6 (ocp_data = 5c30)
10139 22:17:06.666162
10140 22:17:06.669294 R8152: Done initializing
10141 22:17:06.669555
10142 22:17:06.669762 Adding net device
10143 22:17:08.570370
10144 22:17:08.570725 done.
10145 22:17:08.570928
10146 22:17:08.571221 MAC: 00:24:32:30:78:ff
10147 22:17:08.571534
10148 22:17:08.573382 Sending DHCP discover... done.
10149 22:17:08.573590
10150 22:17:16.196017 Waiting for reply... done.
10151 22:17:16.196202
10152 22:17:16.196272 Sending DHCP request... done.
10153 22:17:16.199786
10154 22:17:16.199863 Waiting for reply... done.
10155 22:17:16.199926
10156 22:17:16.203071 My ip is 192.168.201.21
10157 22:17:16.203141
10158 22:17:16.205927 The DHCP server ip is 192.168.201.1
10159 22:17:16.205999
10160 22:17:16.209560 TFTP server IP predefined by user: 192.168.201.1
10161 22:17:16.209648
10162 22:17:16.215816 Bootfile predefined by user: 10583921/tftp-deploy-y7em0uqj/kernel/image.itb
10163 22:17:16.215899
10164 22:17:16.219393 Sending tftp read request... done.
10165 22:17:16.219475
10166 22:17:16.222211 Waiting for the transfer...
10167 22:17:16.222294
10168 22:17:16.769688 00000000 ################################################################
10169 22:17:16.769867
10170 22:17:17.340414 00080000 ################################################################
10171 22:17:17.340690
10172 22:17:17.891952 00100000 ################################################################
10173 22:17:17.892086
10174 22:17:18.437417 00180000 ################################################################
10175 22:17:18.437563
10176 22:17:18.976082 00200000 ################################################################
10177 22:17:18.976232
10178 22:17:19.526212 00280000 ################################################################
10179 22:17:19.526357
10180 22:17:20.071907 00300000 ################################################################
10181 22:17:20.072066
10182 22:17:20.628480 00380000 ################################################################
10183 22:17:20.628619
10184 22:17:21.179532 00400000 ################################################################
10185 22:17:21.179715
10186 22:17:21.717154 00480000 ################################################################
10187 22:17:21.717321
10188 22:17:22.245313 00500000 ################################################################
10189 22:17:22.245460
10190 22:17:22.811929 00580000 ################################################################
10191 22:17:22.812077
10192 22:17:23.371813 00600000 ################################################################
10193 22:17:23.371949
10194 22:17:23.915897 00680000 ################################################################
10195 22:17:23.916058
10196 22:17:24.466322 00700000 ################################################################
10197 22:17:24.466474
10198 22:17:25.025155 00780000 ################################################################
10199 22:17:25.025300
10200 22:17:25.559270 00800000 ################################################################
10201 22:17:25.559424
10202 22:17:26.105090 00880000 ################################################################
10203 22:17:26.105224
10204 22:17:26.653269 00900000 ################################################################
10205 22:17:26.653413
10206 22:17:27.208306 00980000 ################################################################
10207 22:17:27.208443
10208 22:17:27.750441 00a00000 ################################################################
10209 22:17:27.750584
10210 22:17:28.289421 00a80000 ################################################################
10211 22:17:28.289559
10212 22:17:28.815134 00b00000 ################################################################
10213 22:17:28.815269
10214 22:17:29.346697 00b80000 ################################################################
10215 22:17:29.346832
10216 22:17:29.866859 00c00000 ################################################################
10217 22:17:29.866999
10218 22:17:30.399411 00c80000 ################################################################
10219 22:17:30.399622
10220 22:17:30.943669 00d00000 ################################################################
10221 22:17:30.943838
10222 22:17:31.516372 00d80000 ################################################################
10223 22:17:31.516505
10224 22:17:32.053693 00e00000 ################################################################
10225 22:17:32.053853
10226 22:17:32.606069 00e80000 ################################################################
10227 22:17:32.606214
10228 22:17:33.223699 00f00000 ################################################################
10229 22:17:33.224133
10230 22:17:33.823352 00f80000 ################################################################
10231 22:17:33.823487
10232 22:17:34.384932 01000000 ################################################################
10233 22:17:34.385089
10234 22:17:34.974240 01080000 ################################################################
10235 22:17:34.975045
10236 22:17:35.559540 01100000 ################################################################
10237 22:17:35.559696
10238 22:17:36.132461 01180000 ################################################################
10239 22:17:36.132600
10240 22:17:36.726388 01200000 ################################################################
10241 22:17:36.726927
10242 22:17:37.449864 01280000 ################################################################
10243 22:17:37.450422
10244 22:17:38.172422 01300000 ################################################################
10245 22:17:38.173013
10246 22:17:38.898250 01380000 ################################################################
10247 22:17:38.898816
10248 22:17:39.597562 01400000 ################################################################
10249 22:17:39.597722
10250 22:17:40.322105 01480000 ################################################################
10251 22:17:40.322746
10252 22:17:41.046408 01500000 ################################################################
10253 22:17:41.046980
10254 22:17:41.770863 01580000 ################################################################
10255 22:17:41.771461
10256 22:17:42.497474 01600000 ################################################################
10257 22:17:42.498163
10258 22:17:43.224000 01680000 ################################################################
10259 22:17:43.224560
10260 22:17:43.953150 01700000 ################################################################
10261 22:17:43.953745
10262 22:17:44.680714 01780000 ################################################################
10263 22:17:44.681312
10264 22:17:45.409992 01800000 ################################################################
10265 22:17:45.410577
10266 22:17:46.074428 01880000 ################################################################
10267 22:17:46.074919
10268 22:17:46.790183 01900000 ################################################################
10269 22:17:46.790781
10270 22:17:47.519121 01980000 ################################################################
10271 22:17:47.519791
10272 22:17:48.226421 01a00000 ############################################################### done.
10273 22:17:48.226998
10274 22:17:48.229922 The bootfile was 27773770 bytes long.
10275 22:17:48.230422
10276 22:17:48.233721 Sending tftp read request... done.
10277 22:17:48.234302
10278 22:17:48.237063 Waiting for the transfer...
10279 22:17:48.237522
10280 22:17:48.237888 00000000 # done.
10281 22:17:48.238245
10282 22:17:48.243164 Command line loaded dynamically from TFTP file: 10583921/tftp-deploy-y7em0uqj/kernel/cmdline
10283 22:17:48.246747
10284 22:17:48.263146 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10583921/extract-nfsrootfs-dpv56toy,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10285 22:17:48.263734
10286 22:17:48.266598 Loading FIT.
10287 22:17:48.267056
10288 22:17:48.270175 Image ramdisk-1 has 17643081 bytes.
10289 22:17:48.270738
10290 22:17:48.273097 Image fdt-1 has 46924 bytes.
10291 22:17:48.273560
10292 22:17:48.273924 Image kernel-1 has 10081729 bytes.
10293 22:17:48.276168
10294 22:17:48.282723 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10295 22:17:48.283279
10296 22:17:48.303001 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10297 22:17:48.303627
10298 22:17:48.305914 Choosing best match conf-1 for compat google,spherion-rev2.
10299 22:17:48.310978
10300 22:17:48.314962 Connected to device vid:did:rid of 1ae0:0028:00
10301 22:17:48.321816
10302 22:17:48.324922 tpm_get_response: command 0x17b, return code 0x0
10303 22:17:48.325386
10304 22:17:48.328558 ec_init: CrosEC protocol v3 supported (256, 248)
10305 22:17:48.332694
10306 22:17:48.335895 tpm_cleanup: add release locality here.
10307 22:17:48.336357
10308 22:17:48.336722 Shutting down all USB controllers.
10309 22:17:48.339052
10310 22:17:48.339508 Removing current net device
10311 22:17:48.339973
10312 22:17:48.345748 Exiting depthcharge with code 4 at timestamp: 75339572
10313 22:17:48.346207
10314 22:17:48.349701 LZMA decompressing kernel-1 to 0x821a6718
10315 22:17:48.350161
10316 22:17:48.352317 LZMA decompressing kernel-1 to 0x40000000
10317 22:17:49.620365
10318 22:17:49.620919 jumping to kernel
10319 22:17:49.622364 end: 2.2.4 bootloader-commands (duration 00:00:47) [common]
10320 22:17:49.622903 start: 2.2.5 auto-login-action (timeout 00:03:38) [common]
10321 22:17:49.623314 Setting prompt string to ['Linux version [0-9]']
10322 22:17:49.623724 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10323 22:17:49.624114 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10324 22:17:49.701964
10325 22:17:49.705513 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10326 22:17:49.708832 start: 2.2.5.1 login-action (timeout 00:03:38) [common]
10327 22:17:49.709159 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10328 22:17:49.709467 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10329 22:17:49.709709 Using line separator: #'\n'#
10330 22:17:49.709913 No login prompt set.
10331 22:17:49.710119 Parsing kernel messages
10332 22:17:49.710307 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10333 22:17:49.710647 [login-action] Waiting for messages, (timeout 00:03:38)
10334 22:17:49.728879 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1606555-arm64-gcc-10-defconfig-arm64-chromebook-vtq55) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Jun 4 21:56:05 UTC 2023
10335 22:17:49.731651 [ 0.000000] random: crng init done
10336 22:17:49.738402 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10337 22:17:49.741824 [ 0.000000] efi: UEFI not found.
10338 22:17:49.748068 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10339 22:17:49.754807 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10340 22:17:49.764997 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10341 22:17:49.774698 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10342 22:17:49.781220 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10343 22:17:49.788082 [ 0.000000] printk: bootconsole [mtk8250] enabled
10344 22:17:49.794639 [ 0.000000] NUMA: No NUMA configuration found
10345 22:17:49.800994 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10346 22:17:49.804494 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10347 22:17:49.807863 [ 0.000000] Zone ranges:
10348 22:17:49.814582 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10349 22:17:49.817571 [ 0.000000] DMA32 empty
10350 22:17:49.824007 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10351 22:17:49.827172 [ 0.000000] Movable zone start for each node
10352 22:17:49.830686 [ 0.000000] Early memory node ranges
10353 22:17:49.837460 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10354 22:17:49.843649 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10355 22:17:49.850356 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10356 22:17:49.856561 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10357 22:17:49.863155 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10358 22:17:49.869913 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10359 22:17:49.926332 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10360 22:17:49.932605 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10361 22:17:49.939186 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10362 22:17:49.942922 [ 0.000000] psci: probing for conduit method from DT.
10363 22:17:49.949348 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10364 22:17:49.952197 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10365 22:17:49.959412 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10366 22:17:49.962207 [ 0.000000] psci: SMC Calling Convention v1.2
10367 22:17:49.968874 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10368 22:17:49.972352 [ 0.000000] Detected VIPT I-cache on CPU0
10369 22:17:49.979253 [ 0.000000] CPU features: detected: GIC system register CPU interface
10370 22:17:49.986064 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10371 22:17:49.992367 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10372 22:17:49.999144 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10373 22:17:50.008477 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10374 22:17:50.015407 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10375 22:17:50.018658 [ 0.000000] alternatives: applying boot alternatives
10376 22:17:50.025397 [ 0.000000] Fallback order for Node 0: 0
10377 22:17:50.031681 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10378 22:17:50.035552 [ 0.000000] Policy zone: Normal
10379 22:17:50.055625 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10583921/extract-nfsrootfs-dpv56toy,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10380 22:17:50.064796 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10381 22:17:50.076869 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10382 22:17:50.086610 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10383 22:17:50.093442 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10384 22:17:50.096039 <6>[ 0.000000] software IO TLB: area num 8.
10385 22:17:50.154190 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10386 22:17:50.304024 <6>[ 0.000000] Memory: 7955712K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397056K reserved, 32768K cma-reserved)
10387 22:17:50.309891 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10388 22:17:50.316257 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10389 22:17:50.320094 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10390 22:17:50.326075 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10391 22:17:50.333628 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10392 22:17:50.336359 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10393 22:17:50.346107 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10394 22:17:50.352849 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10395 22:17:50.359340 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10396 22:17:50.365799 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10397 22:17:50.369067 <6>[ 0.000000] GICv3: 608 SPIs implemented
10398 22:17:50.372679 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10399 22:17:50.378694 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10400 22:17:50.382984 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10401 22:17:50.389251 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10402 22:17:50.401927 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10403 22:17:50.415476 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10404 22:17:50.421443 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10405 22:17:50.430105 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10406 22:17:50.443443 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10407 22:17:50.449830 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10408 22:17:50.456573 <6>[ 0.009178] Console: colour dummy device 80x25
10409 22:17:50.466491 <6>[ 0.013905] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10410 22:17:50.472732 <6>[ 0.024348] pid_max: default: 32768 minimum: 301
10411 22:17:50.476026 <6>[ 0.029252] LSM: Security Framework initializing
10412 22:17:50.482753 <6>[ 0.034219] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10413 22:17:50.492881 <6>[ 0.042080] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10414 22:17:50.502963 <6>[ 0.051518] cblist_init_generic: Setting adjustable number of callback queues.
10415 22:17:50.505873 <6>[ 0.059018] cblist_init_generic: Setting shift to 3 and lim to 1.
10416 22:17:50.512959 <6>[ 0.065356] cblist_init_generic: Setting shift to 3 and lim to 1.
10417 22:17:50.519472 <6>[ 0.071766] rcu: Hierarchical SRCU implementation.
10418 22:17:50.526213 <6>[ 0.076811] rcu: Max phase no-delay instances is 1000.
10419 22:17:50.532978 <6>[ 0.083862] EFI services will not be available.
10420 22:17:50.535575 <6>[ 0.088832] smp: Bringing up secondary CPUs ...
10421 22:17:50.543794 <6>[ 0.093884] Detected VIPT I-cache on CPU1
10422 22:17:50.550246 <6>[ 0.093957] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10423 22:17:50.557069 <6>[ 0.093988] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10424 22:17:50.559881 <6>[ 0.094322] Detected VIPT I-cache on CPU2
10425 22:17:50.566908 <6>[ 0.094377] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10426 22:17:50.573795 <6>[ 0.094395] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10427 22:17:50.579755 <6>[ 0.094656] Detected VIPT I-cache on CPU3
10428 22:17:50.587172 <6>[ 0.094704] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10429 22:17:50.593062 <6>[ 0.094720] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10430 22:17:50.596143 <6>[ 0.095023] CPU features: detected: Spectre-v4
10431 22:17:50.603363 <6>[ 0.095029] CPU features: detected: Spectre-BHB
10432 22:17:50.606471 <6>[ 0.095034] Detected PIPT I-cache on CPU4
10433 22:17:50.612577 <6>[ 0.095093] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10434 22:17:50.619912 <6>[ 0.095109] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10435 22:17:50.626305 <6>[ 0.095403] Detected PIPT I-cache on CPU5
10436 22:17:50.632985 <6>[ 0.095465] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10437 22:17:50.639062 <6>[ 0.095482] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10438 22:17:50.642879 <6>[ 0.095768] Detected PIPT I-cache on CPU6
10439 22:17:50.652047 <6>[ 0.095832] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10440 22:17:50.659188 <6>[ 0.095849] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10441 22:17:50.662560 <6>[ 0.096147] Detected PIPT I-cache on CPU7
10442 22:17:50.668872 <6>[ 0.096211] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10443 22:17:50.675273 <6>[ 0.096227] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10444 22:17:50.678615 <6>[ 0.096273] smp: Brought up 1 node, 8 CPUs
10445 22:17:50.685506 <6>[ 0.237671] SMP: Total of 8 processors activated.
10446 22:17:50.692048 <6>[ 0.242593] CPU features: detected: 32-bit EL0 Support
10447 22:17:50.698285 <6>[ 0.247956] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10448 22:17:50.705322 <6>[ 0.256810] CPU features: detected: Common not Private translations
10449 22:17:50.711385 <6>[ 0.263326] CPU features: detected: CRC32 instructions
10450 22:17:50.718179 <6>[ 0.268684] CPU features: detected: RCpc load-acquire (LDAPR)
10451 22:17:50.721631 <6>[ 0.274681] CPU features: detected: LSE atomic instructions
10452 22:17:50.727847 <6>[ 0.280498] CPU features: detected: Privileged Access Never
10453 22:17:50.734827 <6>[ 0.286278] CPU features: detected: RAS Extension Support
10454 22:17:50.741690 <6>[ 0.291886] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10455 22:17:50.744684 <6>[ 0.299106] CPU: All CPU(s) started at EL2
10456 22:17:50.751662 <6>[ 0.303449] alternatives: applying system-wide alternatives
10457 22:17:50.761377 <6>[ 0.314179] devtmpfs: initialized
10458 22:17:50.776706 <6>[ 0.322986] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10459 22:17:50.783498 <6>[ 0.332954] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10460 22:17:50.790408 <6>[ 0.340866] pinctrl core: initialized pinctrl subsystem
10461 22:17:50.793687 <6>[ 0.347515] DMI not present or invalid.
10462 22:17:50.800383 <6>[ 0.351919] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10463 22:17:50.810103 <6>[ 0.358806] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10464 22:17:50.815981 <6>[ 0.366385] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10465 22:17:50.825893 <6>[ 0.374598] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10466 22:17:50.829204 <6>[ 0.382843] audit: initializing netlink subsys (disabled)
10467 22:17:50.839157 <5>[ 0.388536] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10468 22:17:50.845849 <6>[ 0.389233] thermal_sys: Registered thermal governor 'step_wise'
10469 22:17:50.852274 <6>[ 0.396505] thermal_sys: Registered thermal governor 'power_allocator'
10470 22:17:50.855633 <6>[ 0.402761] cpuidle: using governor menu
10471 22:17:50.862475 <6>[ 0.413720] NET: Registered PF_QIPCRTR protocol family
10472 22:17:50.868908 <6>[ 0.419207] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10473 22:17:50.875531 <6>[ 0.426310] ASID allocator initialised with 32768 entries
10474 22:17:50.878366 <6>[ 0.432862] Serial: AMBA PL011 UART driver
10475 22:17:50.888246 <4>[ 0.441473] Trying to register duplicate clock ID: 134
10476 22:17:50.942687 <6>[ 0.498754] KASLR enabled
10477 22:17:50.957150 <6>[ 0.506440] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10478 22:17:50.963654 <6>[ 0.513454] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10479 22:17:50.970265 <6>[ 0.519941] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10480 22:17:50.976757 <6>[ 0.526946] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10481 22:17:50.983458 <6>[ 0.533432] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10482 22:17:50.990495 <6>[ 0.540437] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10483 22:17:50.996918 <6>[ 0.546926] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10484 22:17:51.003365 <6>[ 0.553934] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10485 22:17:51.006502 <6>[ 0.561405] ACPI: Interpreter disabled.
10486 22:17:51.015206 <6>[ 0.567837] iommu: Default domain type: Translated
10487 22:17:51.021643 <6>[ 0.572950] iommu: DMA domain TLB invalidation policy: strict mode
10488 22:17:51.024761 <5>[ 0.579615] SCSI subsystem initialized
10489 22:17:51.031823 <6>[ 0.583849] usbcore: registered new interface driver usbfs
10490 22:17:51.038060 <6>[ 0.589578] usbcore: registered new interface driver hub
10491 22:17:51.041414 <6>[ 0.595130] usbcore: registered new device driver usb
10492 22:17:51.048417 <6>[ 0.601227] pps_core: LinuxPPS API ver. 1 registered
10493 22:17:51.058444 <6>[ 0.606421] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10494 22:17:51.061294 <6>[ 0.615763] PTP clock support registered
10495 22:17:51.064856 <6>[ 0.620004] EDAC MC: Ver: 3.0.0
10496 22:17:51.072454 <6>[ 0.625194] FPGA manager framework
10497 22:17:51.078901 <6>[ 0.628872] Advanced Linux Sound Architecture Driver Initialized.
10498 22:17:51.081963 <6>[ 0.635639] vgaarb: loaded
10499 22:17:51.088818 <6>[ 0.638807] clocksource: Switched to clocksource arch_sys_counter
10500 22:17:51.091832 <5>[ 0.645255] VFS: Disk quotas dquot_6.6.0
10501 22:17:51.098749 <6>[ 0.649443] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10502 22:17:51.101988 <6>[ 0.656637] pnp: PnP ACPI: disabled
10503 22:17:51.110470 <6>[ 0.663287] NET: Registered PF_INET protocol family
10504 22:17:51.120964 <6>[ 0.668874] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10505 22:17:51.131889 <6>[ 0.681155] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10506 22:17:51.141418 <6>[ 0.689974] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10507 22:17:51.148111 <6>[ 0.697946] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10508 22:17:51.157756 <6>[ 0.706650] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10509 22:17:51.164311 <6>[ 0.716403] TCP: Hash tables configured (established 65536 bind 65536)
10510 22:17:51.173842 <6>[ 0.723263] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10511 22:17:51.180535 <6>[ 0.730460] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10512 22:17:51.187272 <6>[ 0.738163] NET: Registered PF_UNIX/PF_LOCAL protocol family
10513 22:17:51.193655 <6>[ 0.744328] RPC: Registered named UNIX socket transport module.
10514 22:17:51.197031 <6>[ 0.750481] RPC: Registered udp transport module.
10515 22:17:51.203524 <6>[ 0.755412] RPC: Registered tcp transport module.
10516 22:17:51.210418 <6>[ 0.760346] RPC: Registered tcp NFSv4.1 backchannel transport module.
10517 22:17:51.213304 <6>[ 0.767018] PCI: CLS 0 bytes, default 64
10518 22:17:51.216677 <6>[ 0.771410] Unpacking initramfs...
10519 22:17:51.226588 <6>[ 0.775223] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10520 22:17:51.233359 <6>[ 0.783876] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10521 22:17:51.239912 <6>[ 0.792703] kvm [1]: IPA Size Limit: 40 bits
10522 22:17:51.243004 <6>[ 0.797230] kvm [1]: GICv3: no GICV resource entry
10523 22:17:51.249596 <6>[ 0.802249] kvm [1]: disabling GICv2 emulation
10524 22:17:51.256142 <6>[ 0.806934] kvm [1]: GIC system register CPU interface enabled
10525 22:17:51.259548 <6>[ 0.813101] kvm [1]: vgic interrupt IRQ18
10526 22:17:51.265976 <6>[ 0.817461] kvm [1]: VHE mode initialized successfully
10527 22:17:51.269431 <5>[ 0.823946] Initialise system trusted keyrings
10528 22:17:51.275833 <6>[ 0.828758] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10529 22:17:51.286227 <6>[ 0.838843] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10530 22:17:51.292270 <5>[ 0.845243] NFS: Registering the id_resolver key type
10531 22:17:51.295735 <5>[ 0.850544] Key type id_resolver registered
10532 22:17:51.302460 <5>[ 0.854960] Key type id_legacy registered
10533 22:17:51.309595 <6>[ 0.859242] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10534 22:17:51.315295 <6>[ 0.866165] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10535 22:17:51.322411 <6>[ 0.873911] 9p: Installing v9fs 9p2000 file system support
10536 22:17:51.358967 <5>[ 0.911813] Key type asymmetric registered
10537 22:17:51.362034 <5>[ 0.916147] Asymmetric key parser 'x509' registered
10538 22:17:51.372342 <6>[ 0.921294] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10539 22:17:51.375827 <6>[ 0.928909] io scheduler mq-deadline registered
10540 22:17:51.378381 <6>[ 0.933670] io scheduler kyber registered
10541 22:17:51.397828 <6>[ 0.950609] EINJ: ACPI disabled.
10542 22:17:51.430325 <4>[ 0.976051] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10543 22:17:51.439673 <4>[ 0.986708] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10544 22:17:51.454588 <6>[ 1.007566] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10545 22:17:51.462428 <6>[ 1.015565] printk: console [ttyS0] disabled
10546 22:17:51.490299 <6>[ 1.040210] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10547 22:17:51.497482 <6>[ 1.049687] printk: console [ttyS0] enabled
10548 22:17:51.500665 <6>[ 1.049687] printk: console [ttyS0] enabled
10549 22:17:51.507236 <6>[ 1.058582] printk: bootconsole [mtk8250] disabled
10550 22:17:51.510618 <6>[ 1.058582] printk: bootconsole [mtk8250] disabled
10551 22:17:51.517093 <6>[ 1.069805] SuperH (H)SCI(F) driver initialized
10552 22:17:51.520557 <6>[ 1.075085] msm_serial: driver initialized
10553 22:17:51.534578 <6>[ 1.083977] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10554 22:17:51.544811 <6>[ 1.092523] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10555 22:17:51.551101 <6>[ 1.101065] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10556 22:17:51.560736 <6>[ 1.109692] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10557 22:17:51.570906 <6>[ 1.118402] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10558 22:17:51.577394 <6>[ 1.127124] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10559 22:17:51.587217 <6>[ 1.135667] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10560 22:17:51.593873 <6>[ 1.144479] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10561 22:17:51.603323 <6>[ 1.153022] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10562 22:17:51.615626 <6>[ 1.168460] loop: module loaded
10563 22:17:51.622262 <6>[ 1.174523] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10564 22:17:51.644955 <4>[ 1.197852] mtk-pmic-keys: Failed to locate of_node [id: -1]
10565 22:17:51.651923 <6>[ 1.204663] megasas: 07.719.03.00-rc1
10566 22:17:51.661595 <6>[ 1.214165] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10567 22:17:51.669475 <6>[ 1.222192] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10568 22:17:51.686160 <6>[ 1.238933] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10569 22:17:51.746927 <6>[ 1.293059] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10570 22:17:51.951968 <6>[ 1.504759] Freeing initrd memory: 17228K
10571 22:17:51.962295 <6>[ 1.515002] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10572 22:17:51.973081 <6>[ 1.525763] tun: Universal TUN/TAP device driver, 1.6
10573 22:17:51.976454 <6>[ 1.531807] thunder_xcv, ver 1.0
10574 22:17:51.979835 <6>[ 1.535315] thunder_bgx, ver 1.0
10575 22:17:51.983235 <6>[ 1.538810] nicpf, ver 1.0
10576 22:17:51.993330 <6>[ 1.542817] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10577 22:17:51.997102 <6>[ 1.550291] hns3: Copyright (c) 2017 Huawei Corporation.
10578 22:17:51.999842 <6>[ 1.555877] hclge is initializing
10579 22:17:52.006900 <6>[ 1.559451] e1000: Intel(R) PRO/1000 Network Driver
10580 22:17:52.013363 <6>[ 1.564579] e1000: Copyright (c) 1999-2006 Intel Corporation.
10581 22:17:52.016477 <6>[ 1.570610] e1000e: Intel(R) PRO/1000 Network Driver
10582 22:17:52.023021 <6>[ 1.575825] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10583 22:17:52.030204 <6>[ 1.582010] igb: Intel(R) Gigabit Ethernet Network Driver
10584 22:17:52.036208 <6>[ 1.587659] igb: Copyright (c) 2007-2014 Intel Corporation.
10585 22:17:52.043109 <6>[ 1.593496] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10586 22:17:52.049627 <6>[ 1.600014] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10587 22:17:52.052758 <6>[ 1.606470] sky2: driver version 1.30
10588 22:17:52.059114 <6>[ 1.611449] VFIO - User Level meta-driver version: 0.3
10589 22:17:52.066657 <6>[ 1.619585] usbcore: registered new interface driver usb-storage
10590 22:17:52.073316 <6>[ 1.626033] usbcore: registered new device driver onboard-usb-hub
10591 22:17:52.082489 <6>[ 1.635034] mt6397-rtc mt6359-rtc: registered as rtc0
10592 22:17:52.092264 <6>[ 1.640499] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-04T22:17:52 UTC (1685917072)
10593 22:17:52.095510 <6>[ 1.650054] i2c_dev: i2c /dev entries driver
10594 22:17:52.112049 <6>[ 1.661688] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10595 22:17:52.119009 <6>[ 1.671886] sdhci: Secure Digital Host Controller Interface driver
10596 22:17:52.125795 <6>[ 1.678324] sdhci: Copyright(c) Pierre Ossman
10597 22:17:52.133064 <6>[ 1.683722] Synopsys Designware Multimedia Card Interface Driver
10598 22:17:52.135678 <6>[ 1.690312] mmc0: CQHCI version 5.10
10599 22:17:52.142193 <6>[ 1.690883] sdhci-pltfm: SDHCI platform and OF driver helper
10600 22:17:52.149677 <6>[ 1.702237] ledtrig-cpu: registered to indicate activity on CPUs
10601 22:17:52.160902 <6>[ 1.709561] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10602 22:17:52.163499 <6>[ 1.716939] usbcore: registered new interface driver usbhid
10603 22:17:52.169751 <6>[ 1.722766] usbhid: USB HID core driver
10604 22:17:52.176654 <6>[ 1.727012] spi_master spi0: will run message pump with realtime priority
10605 22:17:52.223011 <6>[ 1.769112] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10606 22:17:52.241437 <6>[ 1.784209] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10607 22:17:52.245197 <6>[ 1.797778] mmc0: Command Queue Engine enabled
10608 22:17:52.251891 <6>[ 1.799078] cros-ec-spi spi0.0: Chrome EC device registered
10609 22:17:52.255166 <6>[ 1.802520] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10610 22:17:52.262368 <6>[ 1.815501] mmcblk0: mmc0:0001 DA4128 116 GiB
10611 22:17:52.272601 <6>[ 1.825503] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10612 22:17:52.283144 <6>[ 1.826123] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10613 22:17:52.289309 <6>[ 1.832854] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10614 22:17:52.292610 <6>[ 1.842808] NET: Registered PF_PACKET protocol family
10615 22:17:52.299400 <6>[ 1.846634] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10616 22:17:52.302739 <6>[ 1.851373] 9pnet: Installing 9P2000 support
10617 22:17:52.309022 <6>[ 1.857141] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10618 22:17:52.315427 <5>[ 1.861033] Key type dns_resolver registered
10619 22:17:52.319046 <6>[ 1.872584] registered taskstats version 1
10620 22:17:52.325480 <5>[ 1.876968] Loading compiled-in X.509 certificates
10621 22:17:52.364082 <4>[ 1.910208] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10622 22:17:52.374083 <4>[ 1.920900] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10623 22:17:52.383979 <3>[ 1.933517] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10624 22:17:52.395955 <6>[ 1.949002] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10625 22:17:52.403033 <6>[ 1.955849] xhci-mtk 11200000.usb: xHCI Host Controller
10626 22:17:52.409497 <6>[ 1.961377] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10627 22:17:52.419955 <6>[ 1.969320] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10628 22:17:52.426471 <6>[ 1.978770] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10629 22:17:52.432907 <6>[ 1.984860] xhci-mtk 11200000.usb: xHCI Host Controller
10630 22:17:52.439485 <6>[ 1.990342] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10631 22:17:52.446325 <6>[ 1.997997] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10632 22:17:52.452858 <6>[ 2.005883] hub 1-0:1.0: USB hub found
10633 22:17:52.456148 <6>[ 2.009916] hub 1-0:1.0: 1 port detected
10634 22:17:52.466129 <6>[ 2.014263] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10635 22:17:52.469659 <6>[ 2.023090] hub 2-0:1.0: USB hub found
10636 22:17:52.472947 <6>[ 2.027121] hub 2-0:1.0: 1 port detected
10637 22:17:52.481570 <6>[ 2.034290] mtk-msdc 11f70000.mmc: Got CD GPIO
10638 22:17:52.499138 <6>[ 2.048688] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10639 22:17:52.505940 <6>[ 2.056714] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10640 22:17:52.515392 <4>[ 2.064698] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10641 22:17:52.525549 <6>[ 2.074369] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10642 22:17:52.532802 <6>[ 2.082451] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10643 22:17:52.541989 <6>[ 2.090489] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10644 22:17:52.548961 <6>[ 2.098404] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10645 22:17:52.554974 <6>[ 2.106225] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10646 22:17:52.564658 <6>[ 2.114045] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10647 22:17:52.575453 <6>[ 2.124819] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10648 22:17:52.585649 <6>[ 2.133190] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10649 22:17:52.591686 <6>[ 2.141543] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10650 22:17:52.602155 <6>[ 2.149887] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10651 22:17:52.608471 <6>[ 2.158229] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10652 22:17:52.618718 <6>[ 2.166572] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10653 22:17:52.624933 <6>[ 2.174916] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10654 22:17:52.634887 <6>[ 2.183259] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10655 22:17:52.641870 <6>[ 2.191603] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10656 22:17:52.651388 <6>[ 2.199946] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10657 22:17:52.658698 <6>[ 2.208289] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10658 22:17:52.668244 <6>[ 2.216632] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10659 22:17:52.674682 <6>[ 2.224976] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10660 22:17:52.684544 <6>[ 2.233319] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10661 22:17:52.691288 <6>[ 2.241665] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10662 22:17:52.697728 <6>[ 2.250598] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10663 22:17:52.704854 <6>[ 2.258036] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10664 22:17:52.712590 <6>[ 2.265050] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10665 22:17:52.722570 <6>[ 2.272164] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10666 22:17:52.728836 <6>[ 2.279440] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10667 22:17:52.738992 <6>[ 2.286340] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10668 22:17:52.745229 <6>[ 2.295493] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10669 22:17:52.755073 <6>[ 2.304620] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10670 22:17:52.765181 <6>[ 2.313921] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10671 22:17:52.774911 <6>[ 2.323396] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10672 22:17:52.785538 <6>[ 2.332870] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10673 22:17:52.794674 <6>[ 2.341998] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10674 22:17:52.801764 <6>[ 2.351473] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10675 22:17:52.811415 <6>[ 2.360600] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10676 22:17:52.821592 <6>[ 2.369901] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10677 22:17:52.831235 <6>[ 2.380067] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10678 22:17:52.842290 <6>[ 2.391715] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10679 22:17:52.848160 <6>[ 2.401647] Trying to probe devices needed for running init ...
10680 22:17:52.881148 <6>[ 2.430876] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10681 22:17:53.034336 <6>[ 2.587022] hub 1-1:1.0: USB hub found
10682 22:17:53.037647 <6>[ 2.591374] hub 1-1:1.0: 4 ports detected
10683 22:17:53.161799 <6>[ 2.711432] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10684 22:17:53.187777 <6>[ 2.740603] hub 2-1:1.0: USB hub found
10685 22:17:53.190671 <6>[ 2.745090] hub 2-1:1.0: 3 ports detected
10686 22:17:53.357199 <6>[ 2.907081] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10687 22:17:53.489841 <6>[ 3.043046] hub 1-1.4:1.0: USB hub found
10688 22:17:53.493141 <6>[ 3.047677] hub 1-1.4:1.0: 2 ports detected
10689 22:17:53.569245 <6>[ 3.119108] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10690 22:17:53.789289 <6>[ 3.339052] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10691 22:17:53.973236 <6>[ 3.523052] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10692 22:18:05.142204 <6>[ 14.699634] ALSA device list:
10693 22:18:05.148370 <6>[ 14.702892] No soundcards found.
10694 22:18:05.160534 <6>[ 14.715307] Freeing unused kernel memory: 8384K
10695 22:18:05.163845 <6>[ 14.720241] Run /init as init process
10696 22:18:05.175090 Loading, please wait...
10697 22:18:05.194588 Starting version 247.3-7+deb11u2
10698 22:18:05.515381 <6>[ 15.066408] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10699 22:18:05.531132 <6>[ 15.085507] remoteproc remoteproc0: scp is available
10700 22:18:05.541037 <4>[ 15.091077] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10701 22:18:05.547464 <6>[ 15.100929] remoteproc remoteproc0: powering up scp
10702 22:18:05.557477 <4>[ 15.106089] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10703 22:18:05.564195 <3>[ 15.116006] remoteproc remoteproc0: request_firmware failed: -2
10704 22:18:05.574078 <3>[ 15.124523] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10705 22:18:05.580080 <6>[ 15.132623] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10706 22:18:05.590701 <6>[ 15.132672] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10707 22:18:05.597006 <3>[ 15.140259] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10708 22:18:05.606720 <3>[ 15.140269] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10709 22:18:05.613473 <6>[ 15.149001] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10710 22:18:05.625289 <3>[ 15.176453] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10711 22:18:05.628853 <6>[ 15.177713] mc: Linux media interface: v0.10
10712 22:18:05.638828 <4>[ 15.178226] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10713 22:18:05.645236 <4>[ 15.181558] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10714 22:18:05.651888 <3>[ 15.184971] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10715 22:18:05.662079 <6>[ 15.186391] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10716 22:18:05.665312 <6>[ 15.199192] usbcore: registered new interface driver r8152
10717 22:18:05.674779 <3>[ 15.204137] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10718 22:18:05.682830 <3>[ 15.204153] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10719 22:18:05.692667 <4>[ 15.213161] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10720 22:18:05.695471 <4>[ 15.213161] Fallback method does not support PEC.
10721 22:18:05.705411 <3>[ 15.219891] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10722 22:18:05.712032 <3>[ 15.220031] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10723 22:18:05.722431 <3>[ 15.242495] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10724 22:18:05.729105 <3>[ 15.255478] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10725 22:18:05.738842 <3>[ 15.285346] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10726 22:18:05.745386 <3>[ 15.288443] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10727 22:18:05.752261 <6>[ 15.291254] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10728 22:18:05.758787 <6>[ 15.296178] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10729 22:18:05.765079 <6>[ 15.296185] pci_bus 0000:00: root bus resource [bus 00-ff]
10730 22:18:05.771832 <6>[ 15.296192] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10731 22:18:05.782441 <6>[ 15.296198] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10732 22:18:05.788813 <6>[ 15.296233] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10733 22:18:05.794912 <6>[ 15.296254] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10734 22:18:05.801929 <6>[ 15.296343] pci 0000:00:00.0: supports D1 D2
10735 22:18:05.808224 <6>[ 15.296347] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10736 22:18:05.814885 <6>[ 15.298038] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10737 22:18:05.824503 <6>[ 15.298741] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10738 22:18:05.835054 <3>[ 15.305330] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10739 22:18:05.844160 <6>[ 15.307647] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10740 22:18:05.854267 <6>[ 15.308072] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10741 22:18:05.860647 <6>[ 15.312706] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10742 22:18:05.867319 <4>[ 15.314986] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10743 22:18:05.877995 <4>[ 15.314997] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10744 22:18:05.883879 <3>[ 15.319426] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10745 22:18:05.893799 <3>[ 15.319435] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10746 22:18:05.900927 <3>[ 15.319443] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10747 22:18:05.907273 <3>[ 15.319451] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10748 22:18:05.917146 <3>[ 15.319457] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10749 22:18:05.923526 <6>[ 15.320202] videodev: Linux video capture interface: v2.00
10750 22:18:05.930425 <6>[ 15.325423] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10751 22:18:05.937298 <6>[ 15.325689] usbcore: registered new interface driver cdc_ether
10752 22:18:05.943537 <3>[ 15.332519] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10753 22:18:05.949972 <6>[ 15.333608] usbcore: registered new interface driver r8153_ecm
10754 22:18:05.956680 <6>[ 15.342755] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10755 22:18:05.960440 <6>[ 15.349646] Bluetooth: Core ver 2.22
10756 22:18:05.970273 <6>[ 15.356260] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10757 22:18:05.973693 <6>[ 15.360814] NET: Registered PF_BLUETOOTH protocol family
10758 22:18:05.980162 <6>[ 15.367755] pci 0000:01:00.0: supports D1 D2
10759 22:18:05.986697 <6>[ 15.375907] Bluetooth: HCI device and connection manager initialized
10760 22:18:05.989566 <6>[ 15.376093] r8152 2-1.3:1.0 eth0: v1.12.13
10761 22:18:05.996140 <6>[ 15.384684] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10762 22:18:06.003023 <6>[ 15.385177] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10763 22:18:06.009412 <6>[ 15.398986] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10764 22:18:06.016585 <6>[ 15.403495] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10765 22:18:06.022889 <6>[ 15.403517] Bluetooth: HCI socket layer initialized
10766 22:18:06.026200 <6>[ 15.403535] Bluetooth: L2CAP socket layer initialized
10767 22:18:06.032685 <6>[ 15.403559] Bluetooth: SCO socket layer initialized
10768 22:18:06.039701 <6>[ 15.404393] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10769 22:18:06.045788 <6>[ 15.412497] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10770 22:18:06.059618 <6>[ 15.420482] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10771 22:18:06.068829 <6>[ 15.427797] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10772 22:18:06.075353 <6>[ 15.427813] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10773 22:18:06.081861 <6>[ 15.436166] usbcore: registered new interface driver uvcvideo
10774 22:18:06.088779 <6>[ 15.443979] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10775 22:18:06.095650 <6>[ 15.468893] usbcore: registered new interface driver btusb
10776 22:18:06.105466 <4>[ 15.469691] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10777 22:18:06.111776 <3>[ 15.469701] Bluetooth: hci0: Failed to load firmware file (-2)
10778 22:18:06.118746 <3>[ 15.469705] Bluetooth: hci0: Failed to set up firmware (-2)
10779 22:18:06.128291 <4>[ 15.469708] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10780 22:18:06.135025 <6>[ 15.476325] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10781 22:18:06.141762 <6>[ 15.695512] pci 0000:00:00.0: PCI bridge to [bus 01]
10782 22:18:06.148583 <6>[ 15.700739] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10783 22:18:06.155139 <6>[ 15.708905] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10784 22:18:06.161326 <6>[ 15.716101] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10785 22:18:06.168402 <6>[ 15.722526] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10786 22:18:06.186648 <5>[ 15.738076] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10787 22:18:06.206811 <5>[ 15.757843] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10788 22:18:06.213469 <4>[ 15.764737] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10789 22:18:06.219571 <6>[ 15.773629] cfg80211: failed to load regulatory.db
10790 22:18:06.261968 <6>[ 15.813415] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10791 22:18:06.268464 <6>[ 15.820945] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10792 22:18:06.293223 <6>[ 15.847657] mt7921e 0000:01:00.0: ASIC revision: 79610010
10793 22:18:06.398583 <4>[ 15.946690] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10794 22:18:06.416194 Begin: Loading essential drivers ... done.
10795 22:18:06.419830 Begin: Running /scripts/init-premount ... done.
10796 22:18:06.426508 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10797 22:18:06.436832 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10798 22:18:06.439163 Device /sys/class/net/enx0024323078ff found
10799 22:18:06.439603 done.
10800 22:18:06.483713 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10801 22:18:06.516859 <4>[ 16.065225] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10802 22:18:06.636591 <4>[ 16.184744] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10803 22:18:06.752473 <4>[ 16.300613] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10804 22:18:06.868203 <4>[ 16.416503] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10805 22:18:06.984225 <4>[ 16.532495] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10806 22:18:07.099959 <4>[ 16.648386] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10807 22:18:07.215930 <4>[ 16.764394] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10808 22:18:07.332191 <4>[ 16.880272] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10809 22:18:07.447718 <4>[ 16.996189] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10810 22:18:07.555303 <3>[ 17.110100] mt7921e 0000:01:00.0: hardware init failed
10811 22:18:07.586313 IP-Config: no response after 2 secs - giving up
10812 22:18:07.605565 <6>[ 17.160614] r8152 2-1.3:1.0 enx0024323078ff: carrier on
10813 22:18:07.627185 IP-Config: enx0024323078ff hardware address 00:24:32:30:78:ff mtu 1500 DHCP
10814 22:18:07.630848 IP-Config: enx0024323078ff complete (dhcp from 192.168.201.1):
10815 22:18:07.637507 address: 192.168.201.21 broadcast: 192.168.201.255 netmask: 255.255.255.0
10816 22:18:07.647162 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10817 22:18:07.653783 host : mt8192-asurada-spherion-r0-cbg-8
10818 22:18:07.660439 domain : lava-rack
10819 22:18:07.664132 rootserver: 192.168.201.1 rootpath:
10820 22:18:07.664561 filename :
10821 22:18:07.729759 done.
10822 22:18:07.739522 Begin: Running /scripts/nfs-bottom ... done.
10823 22:18:07.758164 Begin: Running /scripts/init-bottom ... done.
10824 22:18:08.944554 <6>[ 18.499317] NET: Registered PF_INET6 protocol family
10825 22:18:08.951196 <6>[ 18.506229] Segment Routing with IPv6
10826 22:18:08.954587 <6>[ 18.510193] In-situ OAM (IOAM) with IPv6
10827 22:18:09.083520 <30>[ 18.618499] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10828 22:18:09.086652 <30>[ 18.642271] systemd[1]: Detected architecture arm64.
10829 22:18:09.109355
10830 22:18:09.112525 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10831 22:18:09.113072
10832 22:18:09.131887 <30>[ 18.686435] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10833 22:18:09.835697 <30>[ 19.387550] systemd[1]: Queued start job for default target Graphical Interface.
10834 22:18:09.861512 <30>[ 19.416193] systemd[1]: Created slice system-getty.slice.
10835 22:18:09.867998 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10836 22:18:09.884863 <30>[ 19.439838] systemd[1]: Created slice system-modprobe.slice.
10837 22:18:09.891679 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10838 22:18:09.908791 <30>[ 19.463783] systemd[1]: Created slice system-serial\x2dgetty.slice.
10839 22:18:09.918860 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10840 22:18:09.933298 <30>[ 19.488144] systemd[1]: Created slice User and Session Slice.
10841 22:18:09.940046 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10842 22:18:09.959851 <30>[ 19.511658] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10843 22:18:09.969923 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10844 22:18:09.988166 <30>[ 19.539601] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10845 22:18:09.994699 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10846 22:18:10.015165 <30>[ 19.563183] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10847 22:18:10.021401 <30>[ 19.575242] systemd[1]: Reached target Local Encrypted Volumes.
10848 22:18:10.028217 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10849 22:18:10.044205 <30>[ 19.599460] systemd[1]: Reached target Paths.
10850 22:18:10.048059 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10851 22:18:10.064239 <30>[ 19.619142] systemd[1]: Reached target Remote File Systems.
10852 22:18:10.070632 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10853 22:18:10.088286 <30>[ 19.643364] systemd[1]: Reached target Slices.
10854 22:18:10.094940 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10855 22:18:10.107944 <30>[ 19.663140] systemd[1]: Reached target Swap.
10856 22:18:10.111508 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10857 22:18:10.132190 <30>[ 19.683443] systemd[1]: Listening on initctl Compatibility Named Pipe.
10858 22:18:10.138226 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10859 22:18:10.144625 <30>[ 19.699381] systemd[1]: Listening on Journal Audit Socket.
10860 22:18:10.151470 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10861 22:18:10.169412 <30>[ 19.724241] systemd[1]: Listening on Journal Socket (/dev/log).
10862 22:18:10.176462 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10863 22:18:10.193241 <30>[ 19.747889] systemd[1]: Listening on Journal Socket.
10864 22:18:10.199684 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10865 22:18:10.217600 <30>[ 19.768717] systemd[1]: Listening on Network Service Netlink Socket.
10866 22:18:10.223970 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10867 22:18:10.239672 <30>[ 19.794424] systemd[1]: Listening on udev Control Socket.
10868 22:18:10.246303 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10869 22:18:10.261039 <30>[ 19.815489] systemd[1]: Listening on udev Kernel Socket.
10870 22:18:10.267214 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10871 22:18:10.300880 <30>[ 19.855477] systemd[1]: Mounting Huge Pages File System...
10872 22:18:10.307050 Mounting [0;1;39mHuge Pages File System[0m...
10873 22:18:10.322656 <30>[ 19.877522] systemd[1]: Mounting POSIX Message Queue File System...
10874 22:18:10.329202 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10875 22:18:10.346181 <30>[ 19.901483] systemd[1]: Mounting Kernel Debug File System...
10876 22:18:10.353473 Mounting [0;1;39mKernel Debug File System[0m...
10877 22:18:10.371441 <30>[ 19.923443] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10878 22:18:10.386531 <30>[ 19.937904] systemd[1]: Starting Create list of static device nodes for the current kernel...
10879 22:18:10.392343 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10880 22:18:10.410972 <30>[ 19.966159] systemd[1]: Starting Load Kernel Module configfs...
10881 22:18:10.417577 Starting [0;1;39mLoad Kernel Module configfs[0m...
10882 22:18:10.434984 <30>[ 19.989662] systemd[1]: Starting Load Kernel Module drm...
10883 22:18:10.441198 Starting [0;1;39mLoad Kernel Module drm[0m...
10884 22:18:10.458993 <30>[ 20.013651] systemd[1]: Starting Load Kernel Module fuse...
10885 22:18:10.465113 Starting [0;1;39mLoad Kernel Module fuse[0m...
10886 22:18:10.489493 <30>[ 20.041368] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10887 22:18:10.500153 <30>[ 20.055452] systemd[1]: Starting Journal Service...
10888 22:18:10.506925 Startin<6>[ 20.061609] fuse: init (API version 7.37)
10889 22:18:10.510116 g [0;1;39mJournal Service[0m...
10890 22:18:10.564860 <30>[ 20.119656] systemd[1]: Starting Load Kernel Modules...
10891 22:18:10.570830 Starting [0;1;39mLoad Kernel Modules[0m...
10892 22:18:10.590418 <30>[ 20.142048] systemd[1]: Starting Remount Root and Kernel File Systems...
10893 22:18:10.596984 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10894 22:18:10.614666 <30>[ 20.170068] systemd[1]: Starting Coldplug All udev Devices...
10895 22:18:10.621533 Starting [0;1;39mColdplug All udev Devices[0m...
10896 22:18:10.638996 <30>[ 20.194076] systemd[1]: Mounted Huge Pages File System.
10897 22:18:10.645606 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10898 22:18:10.660595 <30>[ 20.215745] systemd[1]: Mounted POSIX Message Queue File System.
10899 22:18:10.670530 <3>[ 20.219811] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10900 22:18:10.677201 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10901 22:18:10.692648 <30>[ 20.247590] systemd[1]: Mounted Kernel Debug File System.
10902 22:18:10.702563 <3>[ 20.251174] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10903 22:18:10.709417 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10904 22:18:10.728162 <30>[ 20.279930] systemd[1]: Finished Create list of static device nodes for the current kernel.
10905 22:18:10.738702 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10906 22:18:10.749178 <3>[ 20.300539] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10907 22:18:10.755598 <30>[ 20.310840] systemd[1]: modprobe@configfs.service: Succeeded.
10908 22:18:10.762515 <30>[ 20.317563] systemd[1]: Finished Load Kernel Module configfs.
10909 22:18:10.769519 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10910 22:18:10.779902 <3>[ 20.330195] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10911 22:18:10.786360 <30>[ 20.340012] systemd[1]: modprobe@drm.service: Succeeded.
10912 22:18:10.793109 <30>[ 20.346469] systemd[1]: Finished Load Kernel Module drm.
10913 22:18:10.799951 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10914 22:18:10.809315 <3>[ 20.360348] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10915 22:18:10.816123 <30>[ 20.370250] systemd[1]: modprobe@fuse.service: Succeeded.
10916 22:18:10.822777 <30>[ 20.376817] systemd[1]: Finished Load Kernel Module fuse.
10917 22:18:10.829981 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10918 22:18:10.836373 <3>[ 20.389570] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10919 22:18:10.846542 <30>[ 20.401192] systemd[1]: Finished Load Kernel Modules.
10920 22:18:10.852824 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10921 22:18:10.872783 <3>[ 20.424181] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10922 22:18:10.878956 <30>[ 20.424194] systemd[1]: Finished Remount Root and Kernel File Systems.
10923 22:18:10.885307 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10924 22:18:10.902276 <3>[ 20.453255] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10925 22:18:10.931526 <3>[ 20.483340] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10926 22:18:10.940572 <30>[ 20.495473] systemd[1]: Mounting FUSE Control File System...
10927 22:18:10.946852 Mounting [0;1;39mFUSE Control File System[0m...
10928 22:18:10.960969 <3>[ 20.512661] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10929 22:18:10.972161 <30>[ 20.524133] systemd[1]: Mounting Kernel Configuration File System...
10930 22:18:10.975739 Mounting [0;1;39mKernel Configuration File System[0m...
10931 22:18:10.989918 <3>[ 20.542090] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10932 22:18:11.006601 <30>[ 20.557744] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10933 22:18:11.016841 <30>[ 20.566737] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10934 22:18:11.032573 <30>[ 20.587522] systemd[1]: Starting Load/Save Random Seed...
10935 22:18:11.039827 Starting [0;1;39mLoad/Save Random Seed[0m...
10936 22:18:11.054208 <30>[ 20.609527] systemd[1]: Starting Apply Kernel Variables...
10937 22:18:11.060870 Starting [0;1;39mApply Kernel Variables[0m...
10938 22:18:11.079956 <30>[ 20.634704] systemd[1]: Starting Create System Users...
10939 22:18:11.086443 Starting [0;1;39mCreate System Users[0m...
10940 22:18:11.101299 <30>[ 20.656564] systemd[1]: Started Journal Service.
10941 22:18:11.108153 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10942 22:18:11.153217 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10943 22:18:11.168755 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10944 22:18:11.185114 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10945 22:18:11.200858 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10946 22:18:11.221790 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10947 22:18:11.268747 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10948 22:18:11.290953 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10949 22:18:11.339079 <46>[ 20.890950] systemd-journald[295]: Received client request to flush runtime journal.
10950 22:18:11.359630 <4>[ 20.904933] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10951 22:18:11.368860 <3>[ 20.920619] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10952 22:18:11.397164 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10953 22:18:11.411276 See 'systemctl status systemd-udev-trigger.service' for details.
10954 22:18:12.099335 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10955 22:18:12.111777 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10956 22:18:12.127527 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10957 22:18:12.179478 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10958 22:18:12.742351 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10959 22:18:12.784447 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10960 22:18:12.837270 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10961 22:18:12.897629 Starting [0;1;39mNetwork Service[0m...
10962 22:18:13.107733 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10963 22:18:13.163163 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10964 22:18:13.186680 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10965 22:18:13.389424 <6>[ 22.945518] remoteproc remoteproc0: powering up scp
10966 22:18:13.430611 <4>[ 22.983201] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10967 22:18:13.437837 <3>[ 22.993096] remoteproc remoteproc0: request_firmware failed: -2
10968 22:18:13.446770 <3>[ 22.999284] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10969 22:18:13.583787 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10970 22:18:13.602974 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10971 22:18:13.620486 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10972 22:18:13.641338 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10973 22:18:13.696898 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10974 22:18:13.720074 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10975 22:18:13.768691 Starting [0;1;39mNetwork Name Resolution[0m...
10976 22:18:13.793311 Starting [0;1;39mNetwork Time Synchronization[0m...
10977 22:18:13.810663 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10978 22:18:13.832700 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10979 22:18:13.863463 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10980 22:18:14.048959 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10981 22:18:14.063450 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10982 22:18:14.087359 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10983 22:18:14.099697 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10984 22:18:14.115395 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10985 22:18:14.244822 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10986 22:18:14.273363 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10987 22:18:14.319870 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10988 22:18:14.705198 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10989 22:18:14.720014 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10990 22:18:14.973334 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10991 22:18:14.991492 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10992 22:18:15.006864 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10993 22:18:15.039500 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10994 22:18:15.143361 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10995 22:18:15.475605 Starting [0;1;39mUser Login Management[0m...
10996 22:18:15.496377 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10997 22:18:15.516949 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10998 22:18:15.538679 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10999 22:18:15.579573 Starting [0;1;39mPermit User Sessions[0m...
11000 22:18:15.689772 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11001 22:18:15.717040 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
11002 22:18:15.767905 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11003 22:18:15.789806 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11004 22:18:15.811685 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11005 22:18:15.832970 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11006 22:18:15.848789 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11007 22:18:15.867779 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11008 22:18:15.919343 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11009 22:18:15.965077 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11010 22:18:16.070381
11011 22:18:16.071074
11012 22:18:16.073438 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11013 22:18:16.074051
11014 22:18:16.076409 debian-bullseye-arm64 login: root (automatic login)
11015 22:18:16.076885
11016 22:18:16.077294
11017 22:18:16.439565 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Sun Jun 4 21:56:05 UTC 2023 aarch64
11018 22:18:16.440326
11019 22:18:16.446146 The programs included with the Debian GNU/Linux system are free software;
11020 22:18:16.452243 the exact distribution terms for each program are described in the
11021 22:18:16.455919 individual files in /usr/share/doc/*/copyright.
11022 22:18:16.456007
11023 22:18:16.462001 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11024 22:18:16.465271 permitted by applicable law.
11025 22:18:17.350691 Matched prompt #10: / #
11027 22:18:17.351986 Setting prompt string to ['/ #']
11028 22:18:17.352467 end: 2.2.5.1 login-action (duration 00:00:28) [common]
11030 22:18:17.353572 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
11031 22:18:17.354063 start: 2.2.6 expect-shell-connection (timeout 00:03:10) [common]
11032 22:18:17.354454 Setting prompt string to ['/ #']
11033 22:18:17.354796 Forcing a shell prompt, looking for ['/ #']
11035 22:18:17.405663 / #
11036 22:18:17.406317 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11037 22:18:17.406750 Waiting using forced prompt support (timeout 00:02:30)
11038 22:18:17.412153
11039 22:18:17.413089 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11040 22:18:17.413600 start: 2.2.7 export-device-env (timeout 00:03:10) [common]
11042 22:18:17.514867 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10583921/extract-nfsrootfs-dpv56toy'
11043 22:18:17.521585 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10583921/extract-nfsrootfs-dpv56toy'
11045 22:18:17.623356 / # export NFS_SERVER_IP='192.168.201.1'
11046 22:18:17.630345 export NFS_SERVER_IP='192.168.201.1'
11047 22:18:17.631292 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11048 22:18:17.631872 end: 2.2 depthcharge-retry (duration 00:01:50) [common]
11049 22:18:17.632366 end: 2 depthcharge-action (duration 00:01:50) [common]
11050 22:18:17.632864 start: 3 lava-test-retry (timeout 00:07:32) [common]
11051 22:18:17.633358 start: 3.1 lava-test-shell (timeout 00:07:32) [common]
11052 22:18:17.633783 Using namespace: common
11054 22:18:17.734979 / # #
11055 22:18:17.735691 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11056 22:18:17.742099 #
11057 22:18:17.742986 Using /lava-10583921
11059 22:18:17.844409 / # export SHELL=/bin/bash
11060 22:18:17.850891 export SHELL=/bin/bash
11062 22:18:17.952657 / # . /lava-10583921/environment
11063 22:18:17.959127 . /lava-10583921/environment
11065 22:18:18.066608 / # /lava-10583921/bin/lava-test-runner /lava-10583921/0
11066 22:18:18.067256 Test shell timeout: 10s (minimum of the action and connection timeout)
11067 22:18:18.072524 /lava-10583921/bin/lava-test-runner /lava-10583921/0
11068 22:18:18.416928 + export TESTRUN_ID=0_timesync-off
11069 22:18:18.420639 + TESTRUN_ID=0_timesync-off
11070 22:18:18.423848 + cd /lava-10583921/0/tests/0_timesync-off
11071 22:18:18.426586 ++ cat uuid
11072 22:18:18.438650 + UUID=10583921_1.6.2.3.1
11073 22:18:18.439075 + set +x
11074 22:18:18.445324 <LAVA_SIGNAL_STARTRUN 0_timesync-off 10583921_1.6.2.3.1>
11075 22:18:18.446017 Received signal: <STARTRUN> 0_timesync-off 10583921_1.6.2.3.1
11076 22:18:18.446389 Starting test lava.0_timesync-off (10583921_1.6.2.3.1)
11077 22:18:18.446860 Skipping test definition patterns.
11078 22:18:18.448546 + systemctl stop systemd-timesyncd
11079 22:18:18.495266 + set +x
11080 22:18:18.498452 <LAVA_SIGNAL_ENDRUN 0_timesync-off 10583921_1.6.2.3.1>
11081 22:18:18.499135 Received signal: <ENDRUN> 0_timesync-off 10583921_1.6.2.3.1
11082 22:18:18.499542 Ending use of test pattern.
11083 22:18:18.499903 Ending test lava.0_timesync-off (10583921_1.6.2.3.1), duration 0.05
11085 22:18:18.603427 + export TESTRUN_ID=1_kselftest-rtc
11086 22:18:18.605994 + TESTRUN_ID=1_kselftest-rtc
11087 22:18:18.609525 + cd /lava-10583921/0/tests/1_kselftest-rtc
11088 22:18:18.612725 ++ cat uuid
11089 22:18:18.623687 + UUID=10583921_1.6.2.3.5
11090 22:18:18.624157 + set +x
11091 22:18:18.630642 <LAVA_SIGNAL_STARTRUN 1_kselftest-rtc 10583921_1.6.2.3.5>
11092 22:18:18.631375 Received signal: <STARTRUN> 1_kselftest-rtc 10583921_1.6.2.3.5
11093 22:18:18.631797 Starting test lava.1_kselftest-rtc (10583921_1.6.2.3.5)
11094 22:18:18.632229 Skipping test definition patterns.
11095 22:18:18.633758 + cd ./automated/linux/kselftest/
11096 22:18:18.660554 + ./kselftest.sh -c rtc -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1281-g84d5372e0f314/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11097 22:18:18.715319 INFO: install_deps skipped
11098 22:18:18.851983 --2023-06-04 22:18:18-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1281-g84d5372e0f314/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11099 22:18:18.860212 Resolving storage.kernelci.org (storage.kernelci.org)... 52.250.1.28
11100 22:18:19.002170 Connecting to storage.kernelci.org (storage.kernelci.org)|52.250.1.28|:80... connected.
11101 22:18:19.143338 HTTP request sent, awaiting response... 200 OK
11102 22:18:19.146439 Length: 2860264 (2.7M) [application/octet-stream]
11103 22:18:19.149467 Saving to: 'kselftest.tar.xz'
11104 22:18:19.149929
11105 22:18:19.150296
11106 22:18:19.426271 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11107 22:18:19.708315 kselftest.tar.xz 1%[ ] 47.81K 170KB/s
11108 22:18:19.990207 kselftest.tar.xz 7%[> ] 217.50K 386KB/s
11109 22:18:20.334440 kselftest.tar.xz 32%[=====> ] 896.25K 1.03MB/s
11110 22:18:20.341458 kselftest.tar.xz 48%[========> ] 1.33M 1.12MB/s
11111 22:18:20.347677 kselftest.tar.xz 100%[===================>] 2.73M 2.28MB/s in 1.2s
11112 22:18:20.348265
11113 22:18:20.596910 2023-06-04 22:18:20 (2.28 MB/s) - 'kselftest.tar.xz' saved [2860264/2860264]
11114 22:18:20.597073
11115 22:18:27.283712 skiplist:
11116 22:18:27.287119 ========================================
11117 22:18:27.289820 ========================================
11118 22:18:27.347572 rtc:rtctest
11119 22:18:27.369889 ============== Tests to run ===============
11120 22:18:27.372821 rtc:rtctest
11121 22:18:27.376181 ===========End Tests to run ===============
11122 22:18:27.493612 <12>[ 37.050440] kselftest: Running tests in rtc
11123 22:18:27.505177 TAP version 13
11124 22:18:27.520477 1..1
11125 22:18:27.562747 # selftests: rtc: rtctest
11126 22:18:27.989635 # TAP version 13
11127 22:18:27.990197 # 1..8
11128 22:18:27.992696 # # Starting 8 tests from 2 test cases.
11129 22:18:27.996429 # # RUN rtc.date_read ...
11130 22:18:28.002779 # # rtctest.c:49:date_read:Current RTC date/time is 04/06/2023 22:18:27.
11131 22:18:28.005933 # # OK rtc.date_read
11132 22:18:28.009523 # ok 1 rtc.date_read
11133 22:18:28.012559 # # RUN rtc.date_read_loop ...
11134 22:18:28.022119 # # rtctest.c:88:date_read_loop:Continuously reading RTC time for 30s (with 11ms breaks after every read).
11135 22:18:36.593116 <6>[ 46.155005] vpu: disabling
11136 22:18:36.596650 <6>[ 46.158052] vproc2: disabling
11137 22:18:36.599856 <6>[ 46.161322] vproc1: disabling
11138 22:18:36.602908 <6>[ 46.164586] vaud18: disabling
11139 22:18:36.610153 <6>[ 46.167996] vsram_others: disabling
11140 22:18:36.612908 <6>[ 46.171872] va09: disabling
11141 22:18:36.616267 <6>[ 46.174978] vsram_md: disabling
11142 22:18:36.619539 <6>[ 46.178463] Vgpu: disabling
11143 22:18:58.022536 # # rtctest.c:115:date_read_loop:Performed 2698 RTC time reads.
11144 22:18:58.025739 # # OK rtc.date_read_loop
11145 22:18:58.029277 # ok 2 rtc.date_read_loop
11146 22:18:58.032356 # # RUN rtc.uie_read ...
11147 22:19:00.999768 # # OK rtc.uie_read
11148 22:19:01.002938 # ok 3 rtc.uie_read
11149 22:19:01.006033 # # RUN rtc.uie_select ...
11150 22:19:03.998818 # # OK rtc.uie_select
11151 22:19:04.002170 # ok 4 rtc.uie_select
11152 22:19:04.005456 # # RUN rtc.alarm_alm_set ...
11153 22:19:04.012255 # # rtctest.c:202:alarm_alm_set:Alarm time now set to 22:19:07.
11154 22:19:04.015545 # # rtctest.c:207:alarm_alm_set:Expected -1 (-1) != rc (-1)
11155 22:19:04.022495 # # alarm_alm_set: Test terminated by assertion
11156 22:19:04.025445 # # FAIL rtc.alarm_alm_set
11157 22:19:04.028600 # not ok 5 rtc.alarm_alm_set
11158 22:19:04.032081 # # RUN rtc.alarm_wkalm_set ...
11159 22:19:04.038425 # # rtctest.c:258:alarm_wkalm_set:Alarm time now set to 04/06/2023 22:19:07.
11160 22:19:07.001510 # # OK rtc.alarm_wkalm_set
11161 22:19:07.001658 # ok 6 rtc.alarm_wkalm_set
11162 22:19:07.007972 # # RUN rtc.alarm_alm_set_minute ...
11163 22:19:07.011344 # # rtctest.c:304:alarm_alm_set_minute:Alarm time now set to 22:20:00.
11164 22:19:07.017774 # # rtctest.c:309:alarm_alm_set_minute:Expected -1 (-1) != rc (-1)
11165 22:19:07.024766 # # alarm_alm_set_minute: Test terminated by assertion
11166 22:19:07.027480 # # FAIL rtc.alarm_alm_set_minute
11167 22:19:07.031057 # not ok 7 rtc.alarm_alm_set_minute
11168 22:19:07.034537 # # RUN rtc.alarm_wkalm_set_minute ...
11169 22:19:07.040990 # # rtctest.c:360:alarm_wkalm_set_minute:Alarm time now set to 04/06/2023 22:20:00.
11170 22:19:59.995915 # # OK rtc.alarm_wkalm_set_minute
11171 22:19:59.999247 # ok 8 rtc.alarm_wkalm_set_minute
11172 22:20:00.002918 # # FAILED: 6 / 8 tests passed.
11173 22:20:00.006292 # # Totals: pass:6 fail:2 xfail:0 xpass:0 skip:0 error:0
11174 22:20:00.009060 not ok 1 selftests: rtc: rtctest # exit=1
11175 22:20:00.615675 rtc_rtctest_rtc_date_read pass
11176 22:20:00.618977 rtc_rtctest_rtc_date_read_loop pass
11177 22:20:00.622422 rtc_rtctest_rtc_uie_read pass
11178 22:20:00.625881 rtc_rtctest_rtc_uie_select pass
11179 22:20:00.629191 rtc_rtctest_rtc_alarm_alm_set fail
11180 22:20:00.632373 rtc_rtctest_rtc_alarm_wkalm_set pass
11181 22:20:00.635527 rtc_rtctest_rtc_alarm_alm_set_minute fail
11182 22:20:00.638866 rtc_rtctest_rtc_alarm_wkalm_set_minute pass
11183 22:20:00.642591 rtc_rtctest fail
11184 22:20:00.645454 + ../../utils/send-to-lava.sh ./output/result.txt
11185 22:20:00.724469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass>
11186 22:20:00.725232 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read RESULT=pass
11188 22:20:00.797889 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass>
11189 22:20:00.798680 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_date_read_loop RESULT=pass
11191 22:20:00.858193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass>
11192 22:20:00.858990 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_read RESULT=pass
11194 22:20:00.924536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass>
11195 22:20:00.925523 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_uie_select RESULT=pass
11197 22:20:00.987982 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail>
11198 22:20:00.988714 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set RESULT=fail
11200 22:20:01.056829 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass>
11201 22:20:01.057589 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set RESULT=pass
11203 22:20:01.121055 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail>
11204 22:20:01.121770 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_alm_set_minute RESULT=fail
11206 22:20:01.188918 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass>
11207 22:20:01.189688 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest_rtc_alarm_wkalm_set_minute RESULT=pass
11209 22:20:01.249332 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rtc_rtctest RESULT=fail>
11210 22:20:01.249777 + set +x
11211 22:20:01.250372 Received signal: <TESTCASE> TEST_CASE_ID=rtc_rtctest RESULT=fail
11213 22:20:01.255848 <LAVA_SIGNAL_ENDRUN 1_kselftest-rtc 10583921_1.6.2.3.5>
11214 22:20:01.256534 Received signal: <ENDRUN> 1_kselftest-rtc 10583921_1.6.2.3.5
11215 22:20:01.256952 Ending use of test pattern.
11216 22:20:01.257403 Ending test lava.1_kselftest-rtc (10583921_1.6.2.3.5), duration 102.63
11218 22:20:01.258733 ok: lava_test_shell seems to have completed
11219 22:20:01.259445 rtc_rtctest: fail
rtc_rtctest_rtc_alarm_alm_set: fail
rtc_rtctest_rtc_alarm_alm_set_minute: fail
rtc_rtctest_rtc_alarm_wkalm_set: pass
rtc_rtctest_rtc_alarm_wkalm_set_minute: pass
rtc_rtctest_rtc_date_read: pass
rtc_rtctest_rtc_date_read_loop: pass
rtc_rtctest_rtc_uie_read: pass
rtc_rtctest_rtc_uie_select: pass
11220 22:20:01.259908 end: 3.1 lava-test-shell (duration 00:01:44) [common]
11221 22:20:01.260326 end: 3 lava-test-retry (duration 00:01:44) [common]
11222 22:20:01.260764 start: 4 finalize (timeout 00:05:48) [common]
11223 22:20:01.261254 start: 4.1 power-off (timeout 00:00:30) [common]
11224 22:20:01.262056 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11225 22:20:01.379678 >> Command sent successfully.
11226 22:20:01.391159 Returned 0 in 0 seconds
11227 22:20:01.492439 end: 4.1 power-off (duration 00:00:00) [common]
11229 22:20:01.494009 start: 4.2 read-feedback (timeout 00:05:48) [common]
11231 22:20:01.496284 Listened to connection for namespace 'common' for up to 1s
11232 22:20:02.495880 Finalising connection for namespace 'common'
11233 22:20:02.496574 Disconnecting from shell: Finalise
11234 22:20:02.496984 / #
11235 22:20:02.597991 end: 4.2 read-feedback (duration 00:00:01) [common]
11236 22:20:02.598717 end: 4 finalize (duration 00:00:01) [common]
11237 22:20:02.599322 Cleaning after the job
11238 22:20:02.599881 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583921/tftp-deploy-y7em0uqj/ramdisk
11239 22:20:02.610880 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583921/tftp-deploy-y7em0uqj/kernel
11240 22:20:02.641073 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583921/tftp-deploy-y7em0uqj/dtb
11241 22:20:02.641451 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583921/tftp-deploy-y7em0uqj/nfsrootfs
11242 22:20:02.714019 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583921/tftp-deploy-y7em0uqj/modules
11243 22:20:02.719359 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10583921
11244 22:20:03.216145 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10583921
11245 22:20:03.216334 Job finished correctly