Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 38
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 30
1 22:14:49.543475 lava-dispatcher, installed at version: 2023.03
2 22:14:49.543668 start: 0 validate
3 22:14:49.543803 Start time: 2023-06-04 22:14:49.543796+00:00 (UTC)
4 22:14:49.543921 Using caching service: 'http://localhost/cache/?uri=%s'
5 22:14:49.544047 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
6 22:14:49.825761 Using caching service: 'http://localhost/cache/?uri=%s'
7 22:14:49.825935 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1281-g84d5372e0f314%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 22:14:50.116176 Using caching service: 'http://localhost/cache/?uri=%s'
9 22:14:50.116348 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1281-g84d5372e0f314%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 22:14:50.400209 Using caching service: 'http://localhost/cache/?uri=%s'
11 22:14:50.400380 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 22:14:50.690064 Using caching service: 'http://localhost/cache/?uri=%s'
13 22:14:50.690225 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1281-g84d5372e0f314%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 22:14:50.976578 validate duration: 1.43
16 22:14:50.976834 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 22:14:50.976932 start: 1.1 download-retry (timeout 00:10:00) [common]
18 22:14:50.977018 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 22:14:50.977141 Not decompressing ramdisk as can be used compressed.
20 22:14:50.977225 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/initrd.cpio.gz
21 22:14:50.977289 saving as /var/lib/lava/dispatcher/tmp/10583894/tftp-deploy-tapz7bnq/ramdisk/initrd.cpio.gz
22 22:14:50.977398 total size: 4665601 (4MB)
23 22:14:50.978519 progress 0% (0MB)
24 22:14:50.980008 progress 5% (0MB)
25 22:14:50.981268 progress 10% (0MB)
26 22:14:50.982608 progress 15% (0MB)
27 22:14:50.983897 progress 20% (0MB)
28 22:14:50.985107 progress 25% (1MB)
29 22:14:50.986344 progress 30% (1MB)
30 22:14:50.987620 progress 35% (1MB)
31 22:14:50.988826 progress 40% (1MB)
32 22:14:50.990277 progress 45% (2MB)
33 22:14:50.991532 progress 50% (2MB)
34 22:14:50.992730 progress 55% (2MB)
35 22:14:50.994026 progress 60% (2MB)
36 22:14:50.995426 progress 65% (2MB)
37 22:14:50.996733 progress 70% (3MB)
38 22:14:50.998044 progress 75% (3MB)
39 22:14:50.999238 progress 80% (3MB)
40 22:14:51.000593 progress 85% (3MB)
41 22:14:51.001857 progress 90% (4MB)
42 22:14:51.003048 progress 95% (4MB)
43 22:14:51.004323 progress 100% (4MB)
44 22:14:51.004479 4MB downloaded in 0.03s (164.32MB/s)
45 22:14:51.004657 end: 1.1.1 http-download (duration 00:00:00) [common]
47 22:14:51.004903 end: 1.1 download-retry (duration 00:00:00) [common]
48 22:14:51.005045 start: 1.2 download-retry (timeout 00:10:00) [common]
49 22:14:51.005132 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 22:14:51.005357 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1281-g84d5372e0f314/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 22:14:51.005430 saving as /var/lib/lava/dispatcher/tmp/10583894/tftp-deploy-tapz7bnq/kernel/Image
52 22:14:51.005492 total size: 45746688 (43MB)
53 22:14:51.005578 No compression specified
54 22:14:51.006757 progress 0% (0MB)
55 22:14:51.018730 progress 5% (2MB)
56 22:14:51.030472 progress 10% (4MB)
57 22:14:51.042290 progress 15% (6MB)
58 22:14:51.053964 progress 20% (8MB)
59 22:14:51.065910 progress 25% (10MB)
60 22:14:51.077453 progress 30% (13MB)
61 22:14:51.089247 progress 35% (15MB)
62 22:14:51.101429 progress 40% (17MB)
63 22:14:51.113245 progress 45% (19MB)
64 22:14:51.125213 progress 50% (21MB)
65 22:14:51.136875 progress 55% (24MB)
66 22:14:51.148996 progress 60% (26MB)
67 22:14:51.161024 progress 65% (28MB)
68 22:14:51.172918 progress 70% (30MB)
69 22:14:51.184715 progress 75% (32MB)
70 22:14:51.196336 progress 80% (34MB)
71 22:14:51.208068 progress 85% (37MB)
72 22:14:51.220000 progress 90% (39MB)
73 22:14:51.231636 progress 95% (41MB)
74 22:14:51.243163 progress 100% (43MB)
75 22:14:51.243319 43MB downloaded in 0.24s (183.44MB/s)
76 22:14:51.243468 end: 1.2.1 http-download (duration 00:00:00) [common]
78 22:14:51.243695 end: 1.2 download-retry (duration 00:00:00) [common]
79 22:14:51.243781 start: 1.3 download-retry (timeout 00:10:00) [common]
80 22:14:51.243874 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 22:14:51.244002 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1281-g84d5372e0f314/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 22:14:51.244072 saving as /var/lib/lava/dispatcher/tmp/10583894/tftp-deploy-tapz7bnq/dtb/mt8192-asurada-spherion-r0.dtb
83 22:14:51.244133 total size: 46924 (0MB)
84 22:14:51.244193 No compression specified
85 22:14:51.245220 progress 69% (0MB)
86 22:14:51.245504 progress 100% (0MB)
87 22:14:51.245676 0MB downloaded in 0.00s (29.04MB/s)
88 22:14:51.245795 end: 1.3.1 http-download (duration 00:00:00) [common]
90 22:14:51.246019 end: 1.3 download-retry (duration 00:00:00) [common]
91 22:14:51.246103 start: 1.4 download-retry (timeout 00:10:00) [common]
92 22:14:51.246184 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 22:14:51.246308 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/full.rootfs.tar.xz
94 22:14:51.246419 saving as /var/lib/lava/dispatcher/tmp/10583894/tftp-deploy-tapz7bnq/nfsrootfs/full.rootfs.tar
95 22:14:51.246483 total size: 200770336 (191MB)
96 22:14:51.246543 Using unxz to decompress xz
97 22:14:51.250446 progress 0% (0MB)
98 22:14:51.798011 progress 5% (9MB)
99 22:14:52.330458 progress 10% (19MB)
100 22:14:52.924603 progress 15% (28MB)
101 22:14:53.300553 progress 20% (38MB)
102 22:14:53.634296 progress 25% (47MB)
103 22:14:54.228538 progress 30% (57MB)
104 22:14:54.828296 progress 35% (67MB)
105 22:14:55.412152 progress 40% (76MB)
106 22:14:55.964775 progress 45% (86MB)
107 22:14:56.539965 progress 50% (95MB)
108 22:14:57.165722 progress 55% (105MB)
109 22:14:57.820380 progress 60% (114MB)
110 22:14:57.937722 progress 65% (124MB)
111 22:14:58.077855 progress 70% (134MB)
112 22:14:58.173338 progress 75% (143MB)
113 22:14:58.247474 progress 80% (153MB)
114 22:14:58.315814 progress 85% (162MB)
115 22:14:58.413409 progress 90% (172MB)
116 22:14:58.691323 progress 95% (181MB)
117 22:14:59.268799 progress 100% (191MB)
118 22:14:59.273412 191MB downloaded in 8.03s (23.85MB/s)
119 22:14:59.273801 end: 1.4.1 http-download (duration 00:00:08) [common]
121 22:14:59.274140 end: 1.4 download-retry (duration 00:00:08) [common]
122 22:14:59.274235 start: 1.5 download-retry (timeout 00:09:52) [common]
123 22:14:59.274324 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 22:14:59.274471 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1281-g84d5372e0f314/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 22:14:59.274559 saving as /var/lib/lava/dispatcher/tmp/10583894/tftp-deploy-tapz7bnq/modules/modules.tar
126 22:14:59.274638 total size: 8541948 (8MB)
127 22:14:59.274700 Using unxz to decompress xz
128 22:14:59.278593 progress 0% (0MB)
129 22:14:59.300309 progress 5% (0MB)
130 22:14:59.325833 progress 10% (0MB)
131 22:14:59.351539 progress 15% (1MB)
132 22:14:59.376935 progress 20% (1MB)
133 22:14:59.400568 progress 25% (2MB)
134 22:14:59.427232 progress 30% (2MB)
135 22:14:59.452203 progress 35% (2MB)
136 22:14:59.476770 progress 40% (3MB)
137 22:14:59.500985 progress 45% (3MB)
138 22:14:59.525780 progress 50% (4MB)
139 22:14:59.549230 progress 55% (4MB)
140 22:14:59.573707 progress 60% (4MB)
141 22:14:59.599441 progress 65% (5MB)
142 22:14:59.624579 progress 70% (5MB)
143 22:14:59.648410 progress 75% (6MB)
144 22:14:59.672692 progress 80% (6MB)
145 22:14:59.697945 progress 85% (6MB)
146 22:14:59.726924 progress 90% (7MB)
147 22:14:59.752377 progress 95% (7MB)
148 22:14:59.776611 progress 100% (8MB)
149 22:14:59.782447 8MB downloaded in 0.51s (16.04MB/s)
150 22:14:59.782763 end: 1.5.1 http-download (duration 00:00:01) [common]
152 22:14:59.783041 end: 1.5 download-retry (duration 00:00:01) [common]
153 22:14:59.783138 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 22:14:59.783236 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 22:15:03.051462 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10583894/extract-nfsrootfs-wh9mu87m
156 22:15:03.051701 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 22:15:03.051845 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 22:15:03.052083 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10583894/lava-overlay-g2jzsoh6
159 22:15:03.052268 makedir: /var/lib/lava/dispatcher/tmp/10583894/lava-overlay-g2jzsoh6/lava-10583894/bin
160 22:15:03.052413 makedir: /var/lib/lava/dispatcher/tmp/10583894/lava-overlay-g2jzsoh6/lava-10583894/tests
161 22:15:03.052553 makedir: /var/lib/lava/dispatcher/tmp/10583894/lava-overlay-g2jzsoh6/lava-10583894/results
162 22:15:03.052706 Creating /var/lib/lava/dispatcher/tmp/10583894/lava-overlay-g2jzsoh6/lava-10583894/bin/lava-add-keys
163 22:15:03.052912 Creating /var/lib/lava/dispatcher/tmp/10583894/lava-overlay-g2jzsoh6/lava-10583894/bin/lava-add-sources
164 22:15:03.053097 Creating /var/lib/lava/dispatcher/tmp/10583894/lava-overlay-g2jzsoh6/lava-10583894/bin/lava-background-process-start
165 22:15:03.053278 Creating /var/lib/lava/dispatcher/tmp/10583894/lava-overlay-g2jzsoh6/lava-10583894/bin/lava-background-process-stop
166 22:15:03.053436 Creating /var/lib/lava/dispatcher/tmp/10583894/lava-overlay-g2jzsoh6/lava-10583894/bin/lava-common-functions
167 22:15:03.053792 Creating /var/lib/lava/dispatcher/tmp/10583894/lava-overlay-g2jzsoh6/lava-10583894/bin/lava-echo-ipv4
168 22:15:03.053918 Creating /var/lib/lava/dispatcher/tmp/10583894/lava-overlay-g2jzsoh6/lava-10583894/bin/lava-install-packages
169 22:15:03.054039 Creating /var/lib/lava/dispatcher/tmp/10583894/lava-overlay-g2jzsoh6/lava-10583894/bin/lava-installed-packages
170 22:15:03.054159 Creating /var/lib/lava/dispatcher/tmp/10583894/lava-overlay-g2jzsoh6/lava-10583894/bin/lava-os-build
171 22:15:03.054280 Creating /var/lib/lava/dispatcher/tmp/10583894/lava-overlay-g2jzsoh6/lava-10583894/bin/lava-probe-channel
172 22:15:03.054400 Creating /var/lib/lava/dispatcher/tmp/10583894/lava-overlay-g2jzsoh6/lava-10583894/bin/lava-probe-ip
173 22:15:03.054519 Creating /var/lib/lava/dispatcher/tmp/10583894/lava-overlay-g2jzsoh6/lava-10583894/bin/lava-target-ip
174 22:15:03.054638 Creating /var/lib/lava/dispatcher/tmp/10583894/lava-overlay-g2jzsoh6/lava-10583894/bin/lava-target-mac
175 22:15:03.054755 Creating /var/lib/lava/dispatcher/tmp/10583894/lava-overlay-g2jzsoh6/lava-10583894/bin/lava-target-storage
176 22:15:03.054875 Creating /var/lib/lava/dispatcher/tmp/10583894/lava-overlay-g2jzsoh6/lava-10583894/bin/lava-test-case
177 22:15:03.054993 Creating /var/lib/lava/dispatcher/tmp/10583894/lava-overlay-g2jzsoh6/lava-10583894/bin/lava-test-event
178 22:15:03.055115 Creating /var/lib/lava/dispatcher/tmp/10583894/lava-overlay-g2jzsoh6/lava-10583894/bin/lava-test-feedback
179 22:15:03.055241 Creating /var/lib/lava/dispatcher/tmp/10583894/lava-overlay-g2jzsoh6/lava-10583894/bin/lava-test-raise
180 22:15:03.055358 Creating /var/lib/lava/dispatcher/tmp/10583894/lava-overlay-g2jzsoh6/lava-10583894/bin/lava-test-reference
181 22:15:03.055480 Creating /var/lib/lava/dispatcher/tmp/10583894/lava-overlay-g2jzsoh6/lava-10583894/bin/lava-test-runner
182 22:15:03.055598 Creating /var/lib/lava/dispatcher/tmp/10583894/lava-overlay-g2jzsoh6/lava-10583894/bin/lava-test-set
183 22:15:03.055718 Creating /var/lib/lava/dispatcher/tmp/10583894/lava-overlay-g2jzsoh6/lava-10583894/bin/lava-test-shell
184 22:15:03.055838 Updating /var/lib/lava/dispatcher/tmp/10583894/lava-overlay-g2jzsoh6/lava-10583894/bin/lava-add-keys (debian)
185 22:15:03.055993 Updating /var/lib/lava/dispatcher/tmp/10583894/lava-overlay-g2jzsoh6/lava-10583894/bin/lava-add-sources (debian)
186 22:15:03.056135 Updating /var/lib/lava/dispatcher/tmp/10583894/lava-overlay-g2jzsoh6/lava-10583894/bin/lava-install-packages (debian)
187 22:15:03.056272 Updating /var/lib/lava/dispatcher/tmp/10583894/lava-overlay-g2jzsoh6/lava-10583894/bin/lava-installed-packages (debian)
188 22:15:03.056408 Updating /var/lib/lava/dispatcher/tmp/10583894/lava-overlay-g2jzsoh6/lava-10583894/bin/lava-os-build (debian)
189 22:15:03.056527 Creating /var/lib/lava/dispatcher/tmp/10583894/lava-overlay-g2jzsoh6/lava-10583894/environment
190 22:15:03.056626 LAVA metadata
191 22:15:03.056697 - LAVA_JOB_ID=10583894
192 22:15:03.056761 - LAVA_DISPATCHER_IP=192.168.201.1
193 22:15:03.056872 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 22:15:03.056938 skipped lava-vland-overlay
195 22:15:03.057013 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 22:15:03.057092 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 22:15:03.057154 skipped lava-multinode-overlay
198 22:15:03.057225 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 22:15:03.057302 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 22:15:03.057377 Loading test definitions
201 22:15:03.057468 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 22:15:03.057572 Using /lava-10583894 at stage 0
203 22:15:03.057867 uuid=10583894_1.6.2.3.1 testdef=None
204 22:15:03.057955 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 22:15:03.058039 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 22:15:03.058480 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 22:15:03.058698 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 22:15:03.059252 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 22:15:03.059487 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 22:15:03.060013 runner path: /var/lib/lava/dispatcher/tmp/10583894/lava-overlay-g2jzsoh6/lava-10583894/0/tests/0_timesync-off test_uuid 10583894_1.6.2.3.1
213 22:15:03.060167 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 22:15:03.060393 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 22:15:03.060464 Using /lava-10583894 at stage 0
217 22:15:03.060564 Fetching tests from https://github.com/kernelci/test-definitions.git
218 22:15:03.060642 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/10583894/lava-overlay-g2jzsoh6/lava-10583894/0/tests/1_kselftest-tpm2'
219 22:15:06.957914 Running '/usr/bin/git checkout kernelci.org
220 22:15:07.102464 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10583894/lava-overlay-g2jzsoh6/lava-10583894/0/tests/1_kselftest-tpm2/automated/linux/kselftest/kselftest.yaml
221 22:15:07.103213 uuid=10583894_1.6.2.3.5 testdef=None
222 22:15:07.103385 end: 1.6.2.3.5 git-repo-action (duration 00:00:04) [common]
224 22:15:07.103671 start: 1.6.2.3.6 test-overlay (timeout 00:09:44) [common]
225 22:15:07.104437 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 22:15:07.104701 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:44) [common]
228 22:15:07.105729 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 22:15:07.105993 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:44) [common]
231 22:15:07.107097 runner path: /var/lib/lava/dispatcher/tmp/10583894/lava-overlay-g2jzsoh6/lava-10583894/0/tests/1_kselftest-tpm2 test_uuid 10583894_1.6.2.3.5
232 22:15:07.107198 BOARD='mt8192-asurada-spherion-r0'
233 22:15:07.107275 BRANCH='cip'
234 22:15:07.107354 SKIPFILE='/dev/null'
235 22:15:07.107431 SKIP_INSTALL='True'
236 22:15:07.107507 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1281-g84d5372e0f314/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 22:15:07.107605 TST_CASENAME=''
238 22:15:07.107700 TST_CMDFILES='tpm2'
239 22:15:07.107901 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 22:15:07.108260 Creating lava-test-runner.conf files
242 22:15:07.108363 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10583894/lava-overlay-g2jzsoh6/lava-10583894/0 for stage 0
243 22:15:07.108501 - 0_timesync-off
244 22:15:07.108606 - 1_kselftest-tpm2
245 22:15:07.108752 end: 1.6.2.3 test-definition (duration 00:00:04) [common]
246 22:15:07.108884 start: 1.6.2.4 compress-overlay (timeout 00:09:44) [common]
247 22:15:14.714593 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 22:15:14.714750 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:36) [common]
249 22:15:14.714842 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 22:15:14.714939 end: 1.6.2 lava-overlay (duration 00:00:12) [common]
251 22:15:14.715029 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:36) [common]
252 22:15:14.828510 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 22:15:14.828858 start: 1.6.4 extract-modules (timeout 00:09:36) [common]
254 22:15:14.829024 extracting modules file /var/lib/lava/dispatcher/tmp/10583894/tftp-deploy-tapz7bnq/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10583894/extract-nfsrootfs-wh9mu87m
255 22:15:15.030611 extracting modules file /var/lib/lava/dispatcher/tmp/10583894/tftp-deploy-tapz7bnq/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10583894/extract-overlay-ramdisk-tzb9vjnp/ramdisk
256 22:15:15.236371 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 22:15:15.236526 start: 1.6.5 apply-overlay-tftp (timeout 00:09:36) [common]
258 22:15:15.236620 [common] Applying overlay to NFS
259 22:15:15.236686 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10583894/compress-overlay-rv0jyu0i/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10583894/extract-nfsrootfs-wh9mu87m
260 22:15:16.136254 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 22:15:16.136415 start: 1.6.6 configure-preseed-file (timeout 00:09:35) [common]
262 22:15:16.136509 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 22:15:16.136602 start: 1.6.7 compress-ramdisk (timeout 00:09:35) [common]
264 22:15:16.136684 Building ramdisk /var/lib/lava/dispatcher/tmp/10583894/extract-overlay-ramdisk-tzb9vjnp/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10583894/extract-overlay-ramdisk-tzb9vjnp/ramdisk
265 22:15:16.437154 >> 117799 blocks
266 22:15:18.383076 rename /var/lib/lava/dispatcher/tmp/10583894/extract-overlay-ramdisk-tzb9vjnp/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10583894/tftp-deploy-tapz7bnq/ramdisk/ramdisk.cpio.gz
267 22:15:18.383496 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 22:15:18.383618 start: 1.6.8 prepare-kernel (timeout 00:09:33) [common]
269 22:15:18.383723 start: 1.6.8.1 prepare-fit (timeout 00:09:33) [common]
270 22:15:18.383828 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10583894/tftp-deploy-tapz7bnq/kernel/Image'
271 22:15:30.205766 Returned 0 in 11 seconds
272 22:15:30.306374 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10583894/tftp-deploy-tapz7bnq/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10583894/tftp-deploy-tapz7bnq/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10583894/tftp-deploy-tapz7bnq/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10583894/tftp-deploy-tapz7bnq/kernel/image.itb
273 22:15:30.644359 output: FIT description: Kernel Image image with one or more FDT blobs
274 22:15:30.644705 output: Created: Sun Jun 4 23:15:30 2023
275 22:15:30.644813 output: Image 0 (kernel-1)
276 22:15:30.644900 output: Description:
277 22:15:30.644982 output: Created: Sun Jun 4 23:15:30 2023
278 22:15:30.645065 output: Type: Kernel Image
279 22:15:30.645148 output: Compression: lzma compressed
280 22:15:30.645249 output: Data Size: 10081729 Bytes = 9845.44 KiB = 9.61 MiB
281 22:15:30.645353 output: Architecture: AArch64
282 22:15:30.645453 output: OS: Linux
283 22:15:30.645590 output: Load Address: 0x00000000
284 22:15:30.645690 output: Entry Point: 0x00000000
285 22:15:30.645788 output: Hash algo: crc32
286 22:15:30.645919 output: Hash value: 3b3111d8
287 22:15:30.646012 output: Image 1 (fdt-1)
288 22:15:30.646108 output: Description: mt8192-asurada-spherion-r0
289 22:15:30.646202 output: Created: Sun Jun 4 23:15:30 2023
290 22:15:30.646317 output: Type: Flat Device Tree
291 22:15:30.646415 output: Compression: uncompressed
292 22:15:30.646489 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
293 22:15:30.646582 output: Architecture: AArch64
294 22:15:30.646677 output: Hash algo: crc32
295 22:15:30.646770 output: Hash value: 1df858fa
296 22:15:30.646865 output: Image 2 (ramdisk-1)
297 22:15:30.646958 output: Description: unavailable
298 22:15:30.647050 output: Created: Sun Jun 4 23:15:30 2023
299 22:15:30.647145 output: Type: RAMDisk Image
300 22:15:30.647237 output: Compression: Unknown Compression
301 22:15:30.647329 output: Data Size: 17641781 Bytes = 17228.30 KiB = 16.82 MiB
302 22:15:30.647422 output: Architecture: AArch64
303 22:15:30.647514 output: OS: Linux
304 22:15:30.647606 output: Load Address: unavailable
305 22:15:30.647697 output: Entry Point: unavailable
306 22:15:30.647791 output: Hash algo: crc32
307 22:15:30.647883 output: Hash value: 4081aa06
308 22:15:30.647974 output: Default Configuration: 'conf-1'
309 22:15:30.648066 output: Configuration 0 (conf-1)
310 22:15:30.648158 output: Description: mt8192-asurada-spherion-r0
311 22:15:30.648250 output: Kernel: kernel-1
312 22:15:30.648342 output: Init Ramdisk: ramdisk-1
313 22:15:30.648434 output: FDT: fdt-1
314 22:15:30.648525 output: Loadables: kernel-1
315 22:15:30.648618 output:
316 22:15:30.648860 end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
317 22:15:30.648998 end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
318 22:15:30.649151 end: 1.6 prepare-tftp-overlay (duration 00:00:31) [common]
319 22:15:30.649292 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:20) [common]
320 22:15:30.649406 No LXC device requested
321 22:15:30.649573 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 22:15:30.649684 start: 1.8 deploy-device-env (timeout 00:09:20) [common]
323 22:15:30.649804 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 22:15:30.649896 Checking files for TFTP limit of 4294967296 bytes.
325 22:15:30.650516 end: 1 tftp-deploy (duration 00:00:40) [common]
326 22:15:30.650643 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 22:15:30.650751 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 22:15:30.650894 substitutions:
329 22:15:30.650970 - {DTB}: 10583894/tftp-deploy-tapz7bnq/dtb/mt8192-asurada-spherion-r0.dtb
330 22:15:30.651061 - {INITRD}: 10583894/tftp-deploy-tapz7bnq/ramdisk/ramdisk.cpio.gz
331 22:15:30.651162 - {KERNEL}: 10583894/tftp-deploy-tapz7bnq/kernel/Image
332 22:15:30.651263 - {LAVA_MAC}: None
333 22:15:30.651362 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10583894/extract-nfsrootfs-wh9mu87m
334 22:15:30.651459 - {NFS_SERVER_IP}: 192.168.201.1
335 22:15:30.651559 - {PRESEED_CONFIG}: None
336 22:15:30.651656 - {PRESEED_LOCAL}: None
337 22:15:30.651752 - {RAMDISK}: 10583894/tftp-deploy-tapz7bnq/ramdisk/ramdisk.cpio.gz
338 22:15:30.651854 - {ROOT_PART}: None
339 22:15:30.651952 - {ROOT}: None
340 22:15:30.652048 - {SERVER_IP}: 192.168.201.1
341 22:15:30.652146 - {TEE}: None
342 22:15:30.652242 Parsed boot commands:
343 22:15:30.652336 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 22:15:30.652571 Parsed boot commands: tftpboot 192.168.201.1 10583894/tftp-deploy-tapz7bnq/kernel/image.itb 10583894/tftp-deploy-tapz7bnq/kernel/cmdline
345 22:15:30.652698 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 22:15:30.652829 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 22:15:30.652965 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 22:15:30.653099 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 22:15:30.653209 Not connected, no need to disconnect.
350 22:15:30.653333 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 22:15:30.653476 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 22:15:30.653596 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-0'
353 22:15:30.657203 Setting prompt string to ['lava-test: # ']
354 22:15:30.657668 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 22:15:30.657795 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 22:15:30.657910 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 22:15:30.658024 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 22:15:30.658389 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
359 22:15:35.796354 >> Command sent successfully.
360 22:15:35.798997 Returned 0 in 5 seconds
361 22:15:35.899397 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 22:15:35.899788 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 22:15:35.899897 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 22:15:35.899983 Setting prompt string to 'Starting depthcharge on Spherion...'
366 22:15:35.900049 Changing prompt to 'Starting depthcharge on Spherion...'
367 22:15:35.900120 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 22:15:35.900391 [Enter `^Ec?' for help]
369 22:15:36.075298
370 22:15:36.075438
371 22:15:36.075506 F0: 102B 0000
372 22:15:36.075571
373 22:15:36.075632 F3: 1001 0000 [0200]
374 22:15:36.075691
375 22:15:36.078373 F3: 1001 0000
376 22:15:36.078459
377 22:15:36.078525 F7: 102D 0000
378 22:15:36.078589
379 22:15:36.081878 F1: 0000 0000
380 22:15:36.081962
381 22:15:36.082029 V0: 0000 0000 [0001]
382 22:15:36.082094
383 22:15:36.082155 00: 0007 8000
384 22:15:36.085274
385 22:15:36.085357 01: 0000 0000
386 22:15:36.085425
387 22:15:36.085487 BP: 0C00 0209 [0000]
388 22:15:36.088604
389 22:15:36.088687 G0: 1182 0000
390 22:15:36.088753
391 22:15:36.088814 EC: 0000 0021 [4000]
392 22:15:36.088875
393 22:15:36.092473 S7: 0000 0000 [0000]
394 22:15:36.092586
395 22:15:36.092687 CC: 0000 0000 [0001]
396 22:15:36.095412
397 22:15:36.095525 T0: 0000 0040 [010F]
398 22:15:36.095626
399 22:15:36.095723 Jump to BL
400 22:15:36.095808
401 22:15:36.121881
402 22:15:36.121974
403 22:15:36.122041
404 22:15:36.129969 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 22:15:36.133698 ARM64: Exception handlers installed.
406 22:15:36.137462 ARM64: Testing exception
407 22:15:36.137611 ARM64: Done test exception
408 22:15:36.147605 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 22:15:36.157775 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 22:15:36.164323 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 22:15:36.174305 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 22:15:36.180672 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 22:15:36.187809 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 22:15:36.199107 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 22:15:36.206035 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 22:15:36.224799 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 22:15:36.228553 WDT: Last reset was cold boot
418 22:15:36.231780 SPI1(PAD0) initialized at 2873684 Hz
419 22:15:36.235185 SPI5(PAD0) initialized at 992727 Hz
420 22:15:36.238806 VBOOT: Loading verstage.
421 22:15:36.245108 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 22:15:36.248653 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 22:15:36.251644 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 22:15:36.255258 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 22:15:36.262053 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 22:15:36.268952 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 22:15:36.279643 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 22:15:36.279733
429 22:15:36.279820
430 22:15:36.290716 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 22:15:36.293713 ARM64: Exception handlers installed.
432 22:15:36.293800 ARM64: Testing exception
433 22:15:36.297153 ARM64: Done test exception
434 22:15:36.300575 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 22:15:36.307246 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 22:15:36.320885 Probing TPM: . done!
437 22:15:36.320973 TPM ready after 0 ms
438 22:15:36.328635 Connected to device vid:did:rid of 1ae0:0028:00
439 22:15:36.335229 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9b9523
440 22:15:36.396675 Initialized TPM device CR50 revision 0
441 22:15:36.405444 tlcl_send_startup: Startup return code is 0
442 22:15:36.405588 TPM: setup succeeded
443 22:15:36.417044 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 22:15:36.426323 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 22:15:36.437984 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 22:15:36.448326 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 22:15:36.452140 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 22:15:36.455562 in-header: 03 07 00 00 08 00 00 00
449 22:15:36.459803 in-data: aa e4 47 04 13 02 00 00
450 22:15:36.463363 Chrome EC: UHEPI supported
451 22:15:36.466764 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 22:15:36.470936 in-header: 03 95 00 00 08 00 00 00
453 22:15:36.474463 in-data: 18 20 20 08 00 00 00 00
454 22:15:36.474547 Phase 1
455 22:15:36.478313 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 22:15:36.485830 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 22:15:36.492909 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 22:15:36.492995 Recovery requested (1009000e)
459 22:15:36.503514 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 22:15:36.508986 tlcl_extend: response is 0
461 22:15:36.518984 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 22:15:36.523503 tlcl_extend: response is 0
463 22:15:36.530954 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 22:15:36.550125 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 22:15:36.557022 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 22:15:36.557108
467 22:15:36.557175
468 22:15:36.567107 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 22:15:36.570694 ARM64: Exception handlers installed.
470 22:15:36.573841 ARM64: Testing exception
471 22:15:36.573946 ARM64: Done test exception
472 22:15:36.595877 pmic_efuse_setting: Set efuses in 11 msecs
473 22:15:36.598828 pmwrap_interface_init: Select PMIF_VLD_RDY
474 22:15:36.605708 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 22:15:36.608983 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 22:15:36.616799 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 22:15:36.620245 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 22:15:36.624033 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 22:15:36.630890 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 22:15:36.634904 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 22:15:36.638178 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 22:15:36.642298 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 22:15:36.649882 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 22:15:36.653987 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 22:15:36.657182 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 22:15:36.660772 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 22:15:36.667914 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 22:15:36.675869 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 22:15:36.679401 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 22:15:36.687104 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 22:15:36.690596 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 22:15:36.697985 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 22:15:36.701488 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 22:15:36.709684 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 22:15:36.713092 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 22:15:36.720710 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 22:15:36.723984 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 22:15:36.728270 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 22:15:36.735421 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 22:15:36.739148 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 22:15:36.746337 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 22:15:36.749956 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 22:15:36.753726 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 22:15:36.760756 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 22:15:36.764543 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 22:15:36.768295 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 22:15:36.775962 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 22:15:36.779364 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 22:15:36.786119 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 22:15:36.790357 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 22:15:36.794280 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 22:15:36.797964 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 22:15:36.805306 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 22:15:36.809158 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 22:15:36.813232 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 22:15:36.816573 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 22:15:36.820679 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 22:15:36.824413 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 22:15:36.831949 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 22:15:36.835413 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 22:15:36.839416 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 22:15:36.843236 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 22:15:36.846679 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 22:15:36.850734 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 22:15:36.857519 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 22:15:36.869245 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 22:15:36.872887 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 22:15:36.880115 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 22:15:36.887326 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 22:15:36.895095 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 22:15:36.898354 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 22:15:36.901904 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 22:15:36.909681 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
534 22:15:36.913218 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 22:15:36.920879 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 22:15:36.924335 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 22:15:36.933646 [RTC]rtc_get_frequency_meter,154: input=15, output=757
538 22:15:36.942786 [RTC]rtc_get_frequency_meter,154: input=23, output=941
539 22:15:36.952536 [RTC]rtc_get_frequency_meter,154: input=19, output=850
540 22:15:36.961997 [RTC]rtc_get_frequency_meter,154: input=17, output=803
541 22:15:36.971363 [RTC]rtc_get_frequency_meter,154: input=16, output=781
542 22:15:36.980952 [RTC]rtc_get_frequency_meter,154: input=16, output=783
543 22:15:36.991102 [RTC]rtc_get_frequency_meter,154: input=17, output=806
544 22:15:36.994632 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
545 22:15:36.998534 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
546 22:15:37.002497 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 22:15:37.010297 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 22:15:37.013296 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 22:15:37.017385 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 22:15:37.021033 ADC[4]: Raw value=906573 ID=7
551 22:15:37.021118 ADC[3]: Raw value=213441 ID=1
552 22:15:37.024546 RAM Code: 0x71
553 22:15:37.028326 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 22:15:37.031738 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 22:15:37.043366 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 22:15:37.047029 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 22:15:37.049985 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 22:15:37.054720 in-header: 03 07 00 00 08 00 00 00
559 22:15:37.058244 in-data: aa e4 47 04 13 02 00 00
560 22:15:37.062214 Chrome EC: UHEPI supported
561 22:15:37.069079 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 22:15:37.072851 in-header: 03 95 00 00 08 00 00 00
563 22:15:37.076364 in-data: 18 20 20 08 00 00 00 00
564 22:15:37.080245 MRC: failed to locate region type 0.
565 22:15:37.083793 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 22:15:37.087933 DRAM-K: Running full calibration
567 22:15:37.095146 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 22:15:37.095228 header.status = 0x0
569 22:15:37.098941 header.version = 0x6 (expected: 0x6)
570 22:15:37.102963 header.size = 0xd00 (expected: 0xd00)
571 22:15:37.103048 header.flags = 0x0
572 22:15:37.110736 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 22:15:37.128678 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
574 22:15:37.136397 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 22:15:37.136482 dram_init: ddr_geometry: 2
576 22:15:37.140177 [EMI] MDL number = 2
577 22:15:37.143670 [EMI] Get MDL freq = 0
578 22:15:37.143756 dram_init: ddr_type: 0
579 22:15:37.147363 is_discrete_lpddr4: 1
580 22:15:37.150957 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 22:15:37.151041
582 22:15:37.151107
583 22:15:37.151167 [Bian_co] ETT version 0.0.0.1
584 22:15:37.154967 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 22:15:37.158977
586 22:15:37.163063 dramc_set_vcore_voltage set vcore to 650000
587 22:15:37.163148 Read voltage for 800, 4
588 22:15:37.163215 Vio18 = 0
589 22:15:37.166691 Vcore = 650000
590 22:15:37.166774 Vdram = 0
591 22:15:37.166841 Vddq = 0
592 22:15:37.166904 Vmddr = 0
593 22:15:37.169966 dram_init: config_dvfs: 1
594 22:15:37.173851 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 22:15:37.180991 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 22:15:37.184588 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
597 22:15:37.188874 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
598 22:15:37.192216 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
599 22:15:37.195899 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
600 22:15:37.199669 MEM_TYPE=3, freq_sel=18
601 22:15:37.199757 sv_algorithm_assistance_LP4_1600
602 22:15:37.206127 ============ PULL DRAM RESETB DOWN ============
603 22:15:37.210109 ========== PULL DRAM RESETB DOWN end =========
604 22:15:37.212921 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 22:15:37.216514 ===================================
606 22:15:37.220545 LPDDR4 DRAM CONFIGURATION
607 22:15:37.224116 ===================================
608 22:15:37.224201 EX_ROW_EN[0] = 0x0
609 22:15:37.228287 EX_ROW_EN[1] = 0x0
610 22:15:37.228370 LP4Y_EN = 0x0
611 22:15:37.231952 WORK_FSP = 0x0
612 22:15:37.232036 WL = 0x2
613 22:15:37.235613 RL = 0x2
614 22:15:37.235696 BL = 0x2
615 22:15:37.235763 RPST = 0x0
616 22:15:37.239460 RD_PRE = 0x0
617 22:15:37.239548 WR_PRE = 0x1
618 22:15:37.242991 WR_PST = 0x0
619 22:15:37.243078 DBI_WR = 0x0
620 22:15:37.246368 DBI_RD = 0x0
621 22:15:37.246453 OTF = 0x1
622 22:15:37.249467 ===================================
623 22:15:37.253080 ===================================
624 22:15:37.256407 ANA top config
625 22:15:37.259422 ===================================
626 22:15:37.262985 DLL_ASYNC_EN = 0
627 22:15:37.263070 ALL_SLAVE_EN = 1
628 22:15:37.266058 NEW_RANK_MODE = 1
629 22:15:37.269434 DLL_IDLE_MODE = 1
630 22:15:37.273139 LP45_APHY_COMB_EN = 1
631 22:15:37.273223 TX_ODT_DIS = 1
632 22:15:37.276615 NEW_8X_MODE = 1
633 22:15:37.279995 ===================================
634 22:15:37.283368 ===================================
635 22:15:37.286722 data_rate = 1600
636 22:15:37.290043 CKR = 1
637 22:15:37.293449 DQ_P2S_RATIO = 8
638 22:15:37.296944 ===================================
639 22:15:37.297028 CA_P2S_RATIO = 8
640 22:15:37.300130 DQ_CA_OPEN = 0
641 22:15:37.303643 DQ_SEMI_OPEN = 0
642 22:15:37.307219 CA_SEMI_OPEN = 0
643 22:15:37.310430 CA_FULL_RATE = 0
644 22:15:37.310514 DQ_CKDIV4_EN = 1
645 22:15:37.313839 CA_CKDIV4_EN = 1
646 22:15:37.317305 CA_PREDIV_EN = 0
647 22:15:37.320556 PH8_DLY = 0
648 22:15:37.323564 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 22:15:37.327285 DQ_AAMCK_DIV = 4
650 22:15:37.327368 CA_AAMCK_DIV = 4
651 22:15:37.330217 CA_ADMCK_DIV = 4
652 22:15:37.333704 DQ_TRACK_CA_EN = 0
653 22:15:37.336795 CA_PICK = 800
654 22:15:37.340231 CA_MCKIO = 800
655 22:15:37.344502 MCKIO_SEMI = 0
656 22:15:37.344590 PLL_FREQ = 3068
657 22:15:37.348645 DQ_UI_PI_RATIO = 32
658 22:15:37.352166 CA_UI_PI_RATIO = 0
659 22:15:37.355846 ===================================
660 22:15:37.359429 ===================================
661 22:15:37.359514 memory_type:LPDDR4
662 22:15:37.363595 GP_NUM : 10
663 22:15:37.363678 SRAM_EN : 1
664 22:15:37.367137 MD32_EN : 0
665 22:15:37.370940 ===================================
666 22:15:37.371033 [ANA_INIT] >>>>>>>>>>>>>>
667 22:15:37.374466 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 22:15:37.378432 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 22:15:37.381994 ===================================
670 22:15:37.384681 data_rate = 1600,PCW = 0X7600
671 22:15:37.388180 ===================================
672 22:15:37.391688 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 22:15:37.398432 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 22:15:37.401274 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 22:15:37.408394 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 22:15:37.411460 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 22:15:37.414839 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 22:15:37.414924 [ANA_INIT] flow start
679 22:15:37.418080 [ANA_INIT] PLL >>>>>>>>
680 22:15:37.421858 [ANA_INIT] PLL <<<<<<<<
681 22:15:37.421941 [ANA_INIT] MIDPI >>>>>>>>
682 22:15:37.425346 [ANA_INIT] MIDPI <<<<<<<<
683 22:15:37.428368 [ANA_INIT] DLL >>>>>>>>
684 22:15:37.428461 [ANA_INIT] flow end
685 22:15:37.432260 ============ LP4 DIFF to SE enter ============
686 22:15:37.438362 ============ LP4 DIFF to SE exit ============
687 22:15:37.438446 [ANA_INIT] <<<<<<<<<<<<<
688 22:15:37.441674 [Flow] Enable top DCM control >>>>>
689 22:15:37.445411 [Flow] Enable top DCM control <<<<<
690 22:15:37.448479 Enable DLL master slave shuffle
691 22:15:37.455432 ==============================================================
692 22:15:37.455516 Gating Mode config
693 22:15:37.462023 ==============================================================
694 22:15:37.465651 Config description:
695 22:15:37.471888 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 22:15:37.478674 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 22:15:37.485470 SELPH_MODE 0: By rank 1: By Phase
698 22:15:37.492061 ==============================================================
699 22:15:37.492152 GAT_TRACK_EN = 1
700 22:15:37.495328 RX_GATING_MODE = 2
701 22:15:37.498700 RX_GATING_TRACK_MODE = 2
702 22:15:37.501926 SELPH_MODE = 1
703 22:15:37.505072 PICG_EARLY_EN = 1
704 22:15:37.508330 VALID_LAT_VALUE = 1
705 22:15:37.515258 ==============================================================
706 22:15:37.518827 Enter into Gating configuration >>>>
707 22:15:37.521955 Exit from Gating configuration <<<<
708 22:15:37.525275 Enter into DVFS_PRE_config >>>>>
709 22:15:37.535217 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 22:15:37.538498 Exit from DVFS_PRE_config <<<<<
711 22:15:37.542096 Enter into PICG configuration >>>>
712 22:15:37.545419 Exit from PICG configuration <<<<
713 22:15:37.545491 [RX_INPUT] configuration >>>>>
714 22:15:37.549060 [RX_INPUT] configuration <<<<<
715 22:15:37.555440 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 22:15:37.558776 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 22:15:37.565953 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 22:15:37.572326 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 22:15:37.578953 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 22:15:37.585906 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 22:15:37.589099 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 22:15:37.592571 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 22:15:37.595424 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 22:15:37.602670 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 22:15:37.606187 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 22:15:37.608983 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 22:15:37.612560 ===================================
728 22:15:37.615823 LPDDR4 DRAM CONFIGURATION
729 22:15:37.619104 ===================================
730 22:15:37.622626 EX_ROW_EN[0] = 0x0
731 22:15:37.622697 EX_ROW_EN[1] = 0x0
732 22:15:37.625737 LP4Y_EN = 0x0
733 22:15:37.625813 WORK_FSP = 0x0
734 22:15:37.629254 WL = 0x2
735 22:15:37.629329 RL = 0x2
736 22:15:37.632377 BL = 0x2
737 22:15:37.632449 RPST = 0x0
738 22:15:37.635703 RD_PRE = 0x0
739 22:15:37.635776 WR_PRE = 0x1
740 22:15:37.639286 WR_PST = 0x0
741 22:15:37.639367 DBI_WR = 0x0
742 22:15:37.642229 DBI_RD = 0x0
743 22:15:37.642302 OTF = 0x1
744 22:15:37.645820 ===================================
745 22:15:37.649025 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 22:15:37.656096 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 22:15:37.659101 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 22:15:37.662686 ===================================
749 22:15:37.666069 LPDDR4 DRAM CONFIGURATION
750 22:15:37.668944 ===================================
751 22:15:37.669022 EX_ROW_EN[0] = 0x10
752 22:15:37.672407 EX_ROW_EN[1] = 0x0
753 22:15:37.676072 LP4Y_EN = 0x0
754 22:15:37.676142 WORK_FSP = 0x0
755 22:15:37.678963 WL = 0x2
756 22:15:37.679041 RL = 0x2
757 22:15:37.682330 BL = 0x2
758 22:15:37.682399 RPST = 0x0
759 22:15:37.686140 RD_PRE = 0x0
760 22:15:37.686208 WR_PRE = 0x1
761 22:15:37.689037 WR_PST = 0x0
762 22:15:37.689105 DBI_WR = 0x0
763 22:15:37.692584 DBI_RD = 0x0
764 22:15:37.692656 OTF = 0x1
765 22:15:37.695871 ===================================
766 22:15:37.702667 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 22:15:37.706612 nWR fixed to 40
768 22:15:37.709884 [ModeRegInit_LP4] CH0 RK0
769 22:15:37.709956 [ModeRegInit_LP4] CH0 RK1
770 22:15:37.713141 [ModeRegInit_LP4] CH1 RK0
771 22:15:37.716561 [ModeRegInit_LP4] CH1 RK1
772 22:15:37.716637 match AC timing 13
773 22:15:37.723107 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 22:15:37.726904 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 22:15:37.730107 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 22:15:37.736294 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 22:15:37.740005 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 22:15:37.740087 [EMI DOE] emi_dcm 0
779 22:15:37.746699 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 22:15:37.746781 ==
781 22:15:37.750133 Dram Type= 6, Freq= 0, CH_0, rank 0
782 22:15:37.753358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 22:15:37.753436 ==
784 22:15:37.760140 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 22:15:37.766771 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 22:15:37.773521 [CA 0] Center 36 (6~67) winsize 62
787 22:15:37.777404 [CA 1] Center 36 (6~67) winsize 62
788 22:15:37.780355 [CA 2] Center 34 (4~65) winsize 62
789 22:15:37.783835 [CA 3] Center 33 (3~64) winsize 62
790 22:15:37.787214 [CA 4] Center 32 (2~63) winsize 62
791 22:15:37.790486 [CA 5] Center 32 (2~62) winsize 61
792 22:15:37.790560
793 22:15:37.794061 [CmdBusTrainingLP45] Vref(ca) range 1: 32
794 22:15:37.794135
795 22:15:37.797164 [CATrainingPosCal] consider 1 rank data
796 22:15:37.800902 u2DelayCellTimex100 = 270/100 ps
797 22:15:37.804293 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
798 22:15:37.807477 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
799 22:15:37.814284 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
800 22:15:37.817689 CA3 delay=33 (3~64),Diff = 1 PI (7 cell)
801 22:15:37.820437 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
802 22:15:37.824167 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
803 22:15:37.824274
804 22:15:37.827441 CA PerBit enable=1, Macro0, CA PI delay=32
805 22:15:37.827548
806 22:15:37.830634 [CBTSetCACLKResult] CA Dly = 32
807 22:15:37.830710 CS Dly: 4 (0~35)
808 22:15:37.830791 ==
809 22:15:37.834291 Dram Type= 6, Freq= 0, CH_0, rank 1
810 22:15:37.840845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 22:15:37.840926 ==
812 22:15:37.844019 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 22:15:37.850615 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 22:15:37.860081 [CA 0] Center 36 (6~67) winsize 62
815 22:15:37.863585 [CA 1] Center 36 (6~67) winsize 62
816 22:15:37.866772 [CA 2] Center 34 (4~65) winsize 62
817 22:15:37.869941 [CA 3] Center 34 (4~65) winsize 62
818 22:15:37.873330 [CA 4] Center 33 (2~64) winsize 63
819 22:15:37.876487 [CA 5] Center 32 (2~63) winsize 62
820 22:15:37.876568
821 22:15:37.898086 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 22:15:37.898166
823 22:15:37.898231 [CATrainingPosCal] consider 2 rank data
824 22:15:37.898304 u2DelayCellTimex100 = 270/100 ps
825 22:15:37.898395 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
826 22:15:37.898483 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
827 22:15:37.900106 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
828 22:15:37.903622 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
829 22:15:37.906587 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
830 22:15:37.910032 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
831 22:15:37.910132
832 22:15:37.913389 CA PerBit enable=1, Macro0, CA PI delay=32
833 22:15:37.913487
834 22:15:37.916685 [CBTSetCACLKResult] CA Dly = 32
835 22:15:37.916784 CS Dly: 5 (0~37)
836 22:15:37.916885
837 22:15:37.920292 ----->DramcWriteLeveling(PI) begin...
838 22:15:37.920399 ==
839 22:15:37.924288 Dram Type= 6, Freq= 0, CH_0, rank 0
840 22:15:37.928148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 22:15:37.928253 ==
842 22:15:37.931643 Write leveling (Byte 0): 33 => 33
843 22:15:37.935622 Write leveling (Byte 1): 27 => 27
844 22:15:37.939057 DramcWriteLeveling(PI) end<-----
845 22:15:37.939143
846 22:15:37.939209 ==
847 22:15:37.942537 Dram Type= 6, Freq= 0, CH_0, rank 0
848 22:15:37.946043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 22:15:37.946127 ==
850 22:15:37.949597 [Gating] SW mode calibration
851 22:15:37.956535 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 22:15:37.963107 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 22:15:37.966632 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 22:15:37.969635 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
855 22:15:37.973260 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
856 22:15:37.979874 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 22:15:37.983015 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 22:15:37.986693 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 22:15:37.993176 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 22:15:37.996981 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 22:15:37.999930 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 22:15:38.006985 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 22:15:38.009936 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 22:15:38.013263 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 22:15:38.020642 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 22:15:38.023383 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 22:15:38.027044 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 22:15:38.033384 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 22:15:38.036712 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 22:15:38.040152 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 22:15:38.044079 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
872 22:15:38.050648 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
873 22:15:38.053533 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 22:15:38.056903 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 22:15:38.063473 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 22:15:38.067241 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 22:15:38.070190 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 22:15:38.077440 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 22:15:38.080291 0 9 8 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
880 22:15:38.083536 0 9 12 | B1->B0 | 2f2f 3434 | 1 1 | (1 1) (1 1)
881 22:15:38.090253 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 22:15:38.093436 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 22:15:38.096951 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 22:15:38.103614 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 22:15:38.107152 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 22:15:38.110669 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
887 22:15:38.117386 0 10 8 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
888 22:15:38.120216 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 22:15:38.123895 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 22:15:38.126973 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 22:15:38.133694 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 22:15:38.137300 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 22:15:38.140626 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 22:15:38.147223 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
895 22:15:38.150620 0 11 8 | B1->B0 | 2c2c 4141 | 1 0 | (0 0) (0 0)
896 22:15:38.153715 0 11 12 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
897 22:15:38.161055 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 22:15:38.164042 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 22:15:38.167687 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 22:15:38.174211 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 22:15:38.177344 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 22:15:38.180492 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
903 22:15:38.187204 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
904 22:15:38.190653 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
905 22:15:38.194365 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 22:15:38.197449 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 22:15:38.204302 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 22:15:38.207508 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 22:15:38.210831 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 22:15:38.217195 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 22:15:38.220821 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 22:15:38.224030 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 22:15:38.230906 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 22:15:38.234160 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 22:15:38.237339 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 22:15:38.244223 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 22:15:38.247698 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 22:15:38.250848 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
919 22:15:38.257602 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
920 22:15:38.257679 Total UI for P1: 0, mck2ui 16
921 22:15:38.261302 best dqsien dly found for B0: ( 0, 14, 6)
922 22:15:38.267643 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
923 22:15:38.271019 Total UI for P1: 0, mck2ui 16
924 22:15:38.274372 best dqsien dly found for B1: ( 0, 14, 8)
925 22:15:38.278074 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
926 22:15:38.281940 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
927 22:15:38.282023
928 22:15:38.285476 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
929 22:15:38.288743 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
930 22:15:38.291834 [Gating] SW calibration Done
931 22:15:38.291908 ==
932 22:15:38.295377 Dram Type= 6, Freq= 0, CH_0, rank 0
933 22:15:38.298538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 22:15:38.298617 ==
935 22:15:38.298681 RX Vref Scan: 0
936 22:15:38.298743
937 22:15:38.301929 RX Vref 0 -> 0, step: 1
938 22:15:38.302031
939 22:15:38.305282 RX Delay -130 -> 252, step: 16
940 22:15:38.308992 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
941 22:15:38.311822 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
942 22:15:38.318902 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
943 22:15:38.321922 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
944 22:15:38.325443 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
945 22:15:38.328605 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
946 22:15:38.331907 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
947 22:15:38.338663 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
948 22:15:38.341782 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
949 22:15:38.344983 iDelay=206, Bit 9, Center 77 (-34 ~ 189) 224
950 22:15:38.348632 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
951 22:15:38.351937 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
952 22:15:38.358677 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
953 22:15:38.361933 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
954 22:15:38.365412 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
955 22:15:38.368956 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
956 22:15:38.369038 ==
957 22:15:38.371945 Dram Type= 6, Freq= 0, CH_0, rank 0
958 22:15:38.375433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 22:15:38.378628 ==
960 22:15:38.378710 DQS Delay:
961 22:15:38.378776 DQS0 = 0, DQS1 = 0
962 22:15:38.382113 DQM Delay:
963 22:15:38.382195 DQM0 = 88, DQM1 = 82
964 22:15:38.385381 DQ Delay:
965 22:15:38.388640 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
966 22:15:38.388723 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
967 22:15:38.392203 DQ8 =77, DQ9 =77, DQ10 =77, DQ11 =77
968 22:15:38.395849 DQ12 =85, DQ13 =85, DQ14 =93, DQ15 =85
969 22:15:38.395931
970 22:15:38.398789
971 22:15:38.398871 ==
972 22:15:38.402336 Dram Type= 6, Freq= 0, CH_0, rank 0
973 22:15:38.405709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 22:15:38.405792 ==
975 22:15:38.405858
976 22:15:38.405919
977 22:15:38.408629 TX Vref Scan disable
978 22:15:38.408712 == TX Byte 0 ==
979 22:15:38.416041 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
980 22:15:38.419358 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
981 22:15:38.419441 == TX Byte 1 ==
982 22:15:38.422297 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
983 22:15:38.429072 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
984 22:15:38.429155 ==
985 22:15:38.432413 Dram Type= 6, Freq= 0, CH_0, rank 0
986 22:15:38.435624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 22:15:38.435708 ==
988 22:15:38.449285 TX Vref=22, minBit 7, minWin=27, winSum=448
989 22:15:38.453133 TX Vref=24, minBit 8, minWin=27, winSum=451
990 22:15:38.456118 TX Vref=26, minBit 8, minWin=27, winSum=454
991 22:15:38.459492 TX Vref=28, minBit 10, minWin=27, winSum=454
992 22:15:38.462871 TX Vref=30, minBit 5, minWin=28, winSum=459
993 22:15:38.469461 TX Vref=32, minBit 4, minWin=28, winSum=456
994 22:15:38.472652 [TxChooseVref] Worse bit 5, Min win 28, Win sum 459, Final Vref 30
995 22:15:38.472736
996 22:15:38.476222 Final TX Range 1 Vref 30
997 22:15:38.476305
998 22:15:38.476372 ==
999 22:15:38.479369 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 22:15:38.483033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 22:15:38.483117 ==
1002 22:15:38.486090
1003 22:15:38.486173
1004 22:15:38.486238 TX Vref Scan disable
1005 22:15:38.489477 == TX Byte 0 ==
1006 22:15:38.492778 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1007 22:15:38.496281 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1008 22:15:38.499923 == TX Byte 1 ==
1009 22:15:38.502963 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1010 22:15:38.506135 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1011 22:15:38.509402
1012 22:15:38.509485 [DATLAT]
1013 22:15:38.509561 Freq=800, CH0 RK0
1014 22:15:38.509622
1015 22:15:38.513158 DATLAT Default: 0xa
1016 22:15:38.513239 0, 0xFFFF, sum = 0
1017 22:15:38.516301 1, 0xFFFF, sum = 0
1018 22:15:38.516389 2, 0xFFFF, sum = 0
1019 22:15:38.519845 3, 0xFFFF, sum = 0
1020 22:15:38.519929 4, 0xFFFF, sum = 0
1021 22:15:38.522906 5, 0xFFFF, sum = 0
1022 22:15:38.523021 6, 0xFFFF, sum = 0
1023 22:15:38.526254 7, 0xFFFF, sum = 0
1024 22:15:38.529941 8, 0xFFFF, sum = 0
1025 22:15:38.530031 9, 0x0, sum = 1
1026 22:15:38.530099 10, 0x0, sum = 2
1027 22:15:38.532946 11, 0x0, sum = 3
1028 22:15:38.533029 12, 0x0, sum = 4
1029 22:15:38.536416 best_step = 10
1030 22:15:38.536496
1031 22:15:38.536561 ==
1032 22:15:38.540043 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 22:15:38.543366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 22:15:38.543484 ==
1035 22:15:38.546872 RX Vref Scan: 1
1036 22:15:38.546954
1037 22:15:38.547047 Set Vref Range= 32 -> 127
1038 22:15:38.547138
1039 22:15:38.549496 RX Vref 32 -> 127, step: 1
1040 22:15:38.549594
1041 22:15:38.553150 RX Delay -79 -> 252, step: 8
1042 22:15:38.553250
1043 22:15:38.556381 Set Vref, RX VrefLevel [Byte0]: 32
1044 22:15:38.559797 [Byte1]: 32
1045 22:15:38.559893
1046 22:15:38.563322 Set Vref, RX VrefLevel [Byte0]: 33
1047 22:15:38.566381 [Byte1]: 33
1048 22:15:38.569791
1049 22:15:38.569871 Set Vref, RX VrefLevel [Byte0]: 34
1050 22:15:38.573322 [Byte1]: 34
1051 22:15:38.577335
1052 22:15:38.577434 Set Vref, RX VrefLevel [Byte0]: 35
1053 22:15:38.580731 [Byte1]: 35
1054 22:15:38.585496
1055 22:15:38.585608 Set Vref, RX VrefLevel [Byte0]: 36
1056 22:15:38.588308 [Byte1]: 36
1057 22:15:38.592535
1058 22:15:38.592635 Set Vref, RX VrefLevel [Byte0]: 37
1059 22:15:38.595766 [Byte1]: 37
1060 22:15:38.600021
1061 22:15:38.600123 Set Vref, RX VrefLevel [Byte0]: 38
1062 22:15:38.603402 [Byte1]: 38
1063 22:15:38.608076
1064 22:15:38.608177 Set Vref, RX VrefLevel [Byte0]: 39
1065 22:15:38.611252 [Byte1]: 39
1066 22:15:38.615613
1067 22:15:38.615714 Set Vref, RX VrefLevel [Byte0]: 40
1068 22:15:38.618657 [Byte1]: 40
1069 22:15:38.622900
1070 22:15:38.623011 Set Vref, RX VrefLevel [Byte0]: 41
1071 22:15:38.625725 [Byte1]: 41
1072 22:15:38.630323
1073 22:15:38.630398 Set Vref, RX VrefLevel [Byte0]: 42
1074 22:15:38.633260 [Byte1]: 42
1075 22:15:38.637638
1076 22:15:38.637743 Set Vref, RX VrefLevel [Byte0]: 43
1077 22:15:38.640806 [Byte1]: 43
1078 22:15:38.645684
1079 22:15:38.645788 Set Vref, RX VrefLevel [Byte0]: 44
1080 22:15:38.648467 [Byte1]: 44
1081 22:15:38.653013
1082 22:15:38.653112 Set Vref, RX VrefLevel [Byte0]: 45
1083 22:15:38.656145 [Byte1]: 45
1084 22:15:38.660655
1085 22:15:38.660763 Set Vref, RX VrefLevel [Byte0]: 46
1086 22:15:38.663944 [Byte1]: 46
1087 22:15:38.667874
1088 22:15:38.667975 Set Vref, RX VrefLevel [Byte0]: 47
1089 22:15:38.671348 [Byte1]: 47
1090 22:15:38.675722
1091 22:15:38.675829 Set Vref, RX VrefLevel [Byte0]: 48
1092 22:15:38.678525 [Byte1]: 48
1093 22:15:38.683094
1094 22:15:38.683195 Set Vref, RX VrefLevel [Byte0]: 49
1095 22:15:38.686652 [Byte1]: 49
1096 22:15:38.690510
1097 22:15:38.690587 Set Vref, RX VrefLevel [Byte0]: 50
1098 22:15:38.694195 [Byte1]: 50
1099 22:15:38.698322
1100 22:15:38.698429 Set Vref, RX VrefLevel [Byte0]: 51
1101 22:15:38.701344 [Byte1]: 51
1102 22:15:38.705616
1103 22:15:38.705719 Set Vref, RX VrefLevel [Byte0]: 52
1104 22:15:38.709345 [Byte1]: 52
1105 22:15:38.712992
1106 22:15:38.713090 Set Vref, RX VrefLevel [Byte0]: 53
1107 22:15:38.716547 [Byte1]: 53
1108 22:15:38.720678
1109 22:15:38.720780 Set Vref, RX VrefLevel [Byte0]: 54
1110 22:15:38.724504 [Byte1]: 54
1111 22:15:38.728177
1112 22:15:38.728278 Set Vref, RX VrefLevel [Byte0]: 55
1113 22:15:38.731500 [Byte1]: 55
1114 22:15:38.736007
1115 22:15:38.736111 Set Vref, RX VrefLevel [Byte0]: 56
1116 22:15:38.739151 [Byte1]: 56
1117 22:15:38.743246
1118 22:15:38.743353 Set Vref, RX VrefLevel [Byte0]: 57
1119 22:15:38.750316 [Byte1]: 57
1120 22:15:38.750426
1121 22:15:38.753369 Set Vref, RX VrefLevel [Byte0]: 58
1122 22:15:38.756795 [Byte1]: 58
1123 22:15:38.756902
1124 22:15:38.760220 Set Vref, RX VrefLevel [Byte0]: 59
1125 22:15:38.763318 [Byte1]: 59
1126 22:15:38.763423
1127 22:15:38.766786 Set Vref, RX VrefLevel [Byte0]: 60
1128 22:15:38.770038 [Byte1]: 60
1129 22:15:38.773895
1130 22:15:38.773995 Set Vref, RX VrefLevel [Byte0]: 61
1131 22:15:38.777371 [Byte1]: 61
1132 22:15:38.781098
1133 22:15:38.781203 Set Vref, RX VrefLevel [Byte0]: 62
1134 22:15:38.784495 [Byte1]: 62
1135 22:15:38.788732
1136 22:15:38.788833 Set Vref, RX VrefLevel [Byte0]: 63
1137 22:15:38.792124 [Byte1]: 63
1138 22:15:38.796052
1139 22:15:38.796161 Set Vref, RX VrefLevel [Byte0]: 64
1140 22:15:38.799420 [Byte1]: 64
1141 22:15:38.803924
1142 22:15:38.804024 Set Vref, RX VrefLevel [Byte0]: 65
1143 22:15:38.807421 [Byte1]: 65
1144 22:15:38.811467
1145 22:15:38.811565 Set Vref, RX VrefLevel [Byte0]: 66
1146 22:15:38.814830 [Byte1]: 66
1147 22:15:38.819025
1148 22:15:38.819134 Set Vref, RX VrefLevel [Byte0]: 67
1149 22:15:38.822194 [Byte1]: 67
1150 22:15:38.826268
1151 22:15:38.826343 Set Vref, RX VrefLevel [Byte0]: 68
1152 22:15:38.830264 [Byte1]: 68
1153 22:15:38.834452
1154 22:15:38.834552 Set Vref, RX VrefLevel [Byte0]: 69
1155 22:15:38.837345 [Byte1]: 69
1156 22:15:38.841662
1157 22:15:38.841767 Set Vref, RX VrefLevel [Byte0]: 70
1158 22:15:38.844681 [Byte1]: 70
1159 22:15:38.849028
1160 22:15:38.849112 Set Vref, RX VrefLevel [Byte0]: 71
1161 22:15:38.852500 [Byte1]: 71
1162 22:15:38.856743
1163 22:15:38.856827 Set Vref, RX VrefLevel [Byte0]: 72
1164 22:15:38.859859 [Byte1]: 72
1165 22:15:38.864593
1166 22:15:38.864674 Set Vref, RX VrefLevel [Byte0]: 73
1167 22:15:38.868226 [Byte1]: 73
1168 22:15:38.872106
1169 22:15:38.872196 Set Vref, RX VrefLevel [Byte0]: 74
1170 22:15:38.874926 [Byte1]: 74
1171 22:15:38.879178
1172 22:15:38.879289 Final RX Vref Byte 0 = 62 to rank0
1173 22:15:38.882709 Final RX Vref Byte 1 = 58 to rank0
1174 22:15:38.885951 Final RX Vref Byte 0 = 62 to rank1
1175 22:15:38.889374 Final RX Vref Byte 1 = 58 to rank1==
1176 22:15:38.892649 Dram Type= 6, Freq= 0, CH_0, rank 0
1177 22:15:38.899208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1178 22:15:38.899292 ==
1179 22:15:38.899358 DQS Delay:
1180 22:15:38.899421 DQS0 = 0, DQS1 = 0
1181 22:15:38.902546 DQM Delay:
1182 22:15:38.902628 DQM0 = 91, DQM1 = 84
1183 22:15:38.905856 DQ Delay:
1184 22:15:38.909295 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1185 22:15:38.909377 DQ4 =96, DQ5 =80, DQ6 =96, DQ7 =96
1186 22:15:38.912427 DQ8 =72, DQ9 =76, DQ10 =84, DQ11 =76
1187 22:15:38.916270 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1188 22:15:38.919227
1189 22:15:38.919309
1190 22:15:38.925824 [DQSOSCAuto] RK0, (LSB)MR18= 0x4f45, (MSB)MR19= 0x606, tDQSOscB0 = 392 ps tDQSOscB1 = 390 ps
1191 22:15:38.929438 CH0 RK0: MR19=606, MR18=4F45
1192 22:15:38.936278 CH0_RK0: MR19=0x606, MR18=0x4F45, DQSOSC=390, MR23=63, INC=97, DEC=64
1193 22:15:38.936361
1194 22:15:38.939218 ----->DramcWriteLeveling(PI) begin...
1195 22:15:38.939327 ==
1196 22:15:38.942830 Dram Type= 6, Freq= 0, CH_0, rank 1
1197 22:15:38.946404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1198 22:15:38.946488 ==
1199 22:15:38.949475 Write leveling (Byte 0): 33 => 33
1200 22:15:38.953016 Write leveling (Byte 1): 29 => 29
1201 22:15:38.956320 DramcWriteLeveling(PI) end<-----
1202 22:15:38.956402
1203 22:15:38.956467 ==
1204 22:15:38.959335 Dram Type= 6, Freq= 0, CH_0, rank 1
1205 22:15:38.963021 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1206 22:15:38.963104 ==
1207 22:15:38.965990 [Gating] SW mode calibration
1208 22:15:38.973487 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1209 22:15:38.979635 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1210 22:15:38.983005 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1211 22:15:38.986232 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1212 22:15:38.993101 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1213 22:15:38.996088 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1214 22:15:39.040418 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1215 22:15:39.040706 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1216 22:15:39.040794 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1217 22:15:39.040958 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1218 22:15:39.041062 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1219 22:15:39.041206 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1220 22:15:39.041482 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1221 22:15:39.042181 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1222 22:15:39.042319 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1223 22:15:39.042584 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 22:15:39.084341 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 22:15:39.084652 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 22:15:39.084726 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 22:15:39.084834 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1228 22:15:39.084992 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1229 22:15:39.085073 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 22:15:39.085163 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 22:15:39.085236 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 22:15:39.085373 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 22:15:39.085462 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 22:15:39.103828 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 22:15:39.104382 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 22:15:39.104485 0 9 8 | B1->B0 | 3131 3434 | 0 0 | (0 0) (0 0)
1237 22:15:39.104732 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1238 22:15:39.107742 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1239 22:15:39.110596 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1240 22:15:39.113950 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1241 22:15:39.117346 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1242 22:15:39.123877 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1243 22:15:39.127236 0 10 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
1244 22:15:39.130919 0 10 8 | B1->B0 | 2626 2828 | 0 0 | (0 0) (1 0)
1245 22:15:39.137643 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1246 22:15:39.140756 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 22:15:39.144109 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 22:15:39.150638 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 22:15:39.154113 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 22:15:39.157386 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 22:15:39.164536 0 11 4 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1252 22:15:39.167649 0 11 8 | B1->B0 | 3b3b 4242 | 0 0 | (1 1) (0 0)
1253 22:15:39.171948 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1254 22:15:39.175642 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1255 22:15:39.179272 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1256 22:15:39.186445 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1257 22:15:39.189329 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1258 22:15:39.193118 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1259 22:15:39.196682 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1260 22:15:39.203229 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1261 22:15:39.207047 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1262 22:15:39.210313 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1263 22:15:39.216940 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1264 22:15:39.220387 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1265 22:15:39.223561 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1266 22:15:39.230186 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1267 22:15:39.233617 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1268 22:15:39.236698 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1269 22:15:39.240227 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1270 22:15:39.247154 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 22:15:39.250184 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 22:15:39.253874 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 22:15:39.260482 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 22:15:39.263698 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 22:15:39.266701 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 22:15:39.273686 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1277 22:15:39.276833 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1278 22:15:39.280051 Total UI for P1: 0, mck2ui 16
1279 22:15:39.283649 best dqsien dly found for B0: ( 0, 14, 8)
1280 22:15:39.287185 Total UI for P1: 0, mck2ui 16
1281 22:15:39.290087 best dqsien dly found for B1: ( 0, 14, 8)
1282 22:15:39.293585 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1283 22:15:39.297074 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1284 22:15:39.297154
1285 22:15:39.300226 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1286 22:15:39.303529 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1287 22:15:39.307347 [Gating] SW calibration Done
1288 22:15:39.307427 ==
1289 22:15:39.310254 Dram Type= 6, Freq= 0, CH_0, rank 1
1290 22:15:39.313566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1291 22:15:39.313671 ==
1292 22:15:39.316885 RX Vref Scan: 0
1293 22:15:39.316960
1294 22:15:39.320336 RX Vref 0 -> 0, step: 1
1295 22:15:39.320417
1296 22:15:39.320482 RX Delay -130 -> 252, step: 16
1297 22:15:39.327163 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1298 22:15:39.330246 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
1299 22:15:39.333630 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
1300 22:15:39.336890 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1301 22:15:39.340225 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1302 22:15:39.347199 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1303 22:15:39.350490 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1304 22:15:39.353800 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1305 22:15:39.357388 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1306 22:15:39.360165 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1307 22:15:39.367468 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1308 22:15:39.370492 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1309 22:15:39.374105 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1310 22:15:39.376941 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1311 22:15:39.380639 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1312 22:15:39.387124 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1313 22:15:39.387203 ==
1314 22:15:39.390579 Dram Type= 6, Freq= 0, CH_0, rank 1
1315 22:15:39.393640 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1316 22:15:39.393715 ==
1317 22:15:39.393778 DQS Delay:
1318 22:15:39.397216 DQS0 = 0, DQS1 = 0
1319 22:15:39.397287 DQM Delay:
1320 22:15:39.400851 DQM0 = 93, DQM1 = 86
1321 22:15:39.400927 DQ Delay:
1322 22:15:39.403859 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
1323 22:15:39.407384 DQ4 =93, DQ5 =85, DQ6 =93, DQ7 =101
1324 22:15:39.410946 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1325 22:15:39.413822 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1326 22:15:39.413900
1327 22:15:39.413992
1328 22:15:39.414082 ==
1329 22:15:39.416979 Dram Type= 6, Freq= 0, CH_0, rank 1
1330 22:15:39.420174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1331 22:15:39.420254 ==
1332 22:15:39.423996
1333 22:15:39.424071
1334 22:15:39.424138 TX Vref Scan disable
1335 22:15:39.427365 == TX Byte 0 ==
1336 22:15:39.430784 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1337 22:15:39.434329 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1338 22:15:39.437154 == TX Byte 1 ==
1339 22:15:39.440614 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1340 22:15:39.444113 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1341 22:15:39.444196 ==
1342 22:15:39.447356 Dram Type= 6, Freq= 0, CH_0, rank 1
1343 22:15:39.454546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1344 22:15:39.454629 ==
1345 22:15:39.465955 TX Vref=22, minBit 10, minWin=27, winSum=450
1346 22:15:39.469368 TX Vref=24, minBit 1, minWin=28, winSum=453
1347 22:15:39.473083 TX Vref=26, minBit 1, minWin=28, winSum=452
1348 22:15:39.476592 TX Vref=28, minBit 2, minWin=28, winSum=453
1349 22:15:39.479808 TX Vref=30, minBit 3, minWin=28, winSum=456
1350 22:15:39.483228 TX Vref=32, minBit 2, minWin=28, winSum=455
1351 22:15:39.489462 [TxChooseVref] Worse bit 3, Min win 28, Win sum 456, Final Vref 30
1352 22:15:39.489595
1353 22:15:39.492989 Final TX Range 1 Vref 30
1354 22:15:39.493087
1355 22:15:39.493176 ==
1356 22:15:39.496546 Dram Type= 6, Freq= 0, CH_0, rank 1
1357 22:15:39.499832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1358 22:15:39.499906 ==
1359 22:15:39.499973
1360 22:15:39.500033
1361 22:15:39.503352 TX Vref Scan disable
1362 22:15:39.506873 == TX Byte 0 ==
1363 22:15:39.510015 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1364 22:15:39.513157 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1365 22:15:39.516263 == TX Byte 1 ==
1366 22:15:39.519823 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1367 22:15:39.522943 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1368 22:15:39.523017
1369 22:15:39.526648 [DATLAT]
1370 22:15:39.526754 Freq=800, CH0 RK1
1371 22:15:39.526830
1372 22:15:39.530153 DATLAT Default: 0xa
1373 22:15:39.530235 0, 0xFFFF, sum = 0
1374 22:15:39.533129 1, 0xFFFF, sum = 0
1375 22:15:39.533211 2, 0xFFFF, sum = 0
1376 22:15:39.536373 3, 0xFFFF, sum = 0
1377 22:15:39.536473 4, 0xFFFF, sum = 0
1378 22:15:39.540287 5, 0xFFFF, sum = 0
1379 22:15:39.540407 6, 0xFFFF, sum = 0
1380 22:15:39.543490 7, 0xFFFF, sum = 0
1381 22:15:39.543572 8, 0xFFFF, sum = 0
1382 22:15:39.546828 9, 0x0, sum = 1
1383 22:15:39.546910 10, 0x0, sum = 2
1384 22:15:39.550132 11, 0x0, sum = 3
1385 22:15:39.550232 12, 0x0, sum = 4
1386 22:15:39.553772 best_step = 10
1387 22:15:39.553852
1388 22:15:39.553916 ==
1389 22:15:39.556710 Dram Type= 6, Freq= 0, CH_0, rank 1
1390 22:15:39.560367 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1391 22:15:39.560448 ==
1392 22:15:39.563216 RX Vref Scan: 0
1393 22:15:39.563296
1394 22:15:39.563360 RX Vref 0 -> 0, step: 1
1395 22:15:39.563420
1396 22:15:39.566691 RX Delay -79 -> 252, step: 8
1397 22:15:39.573371 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1398 22:15:39.576567 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1399 22:15:39.580015 iDelay=209, Bit 2, Center 92 (-15 ~ 200) 216
1400 22:15:39.583224 iDelay=209, Bit 3, Center 88 (-23 ~ 200) 224
1401 22:15:39.586938 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1402 22:15:39.590408 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1403 22:15:39.596780 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1404 22:15:39.600282 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1405 22:15:39.603277 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1406 22:15:39.606729 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1407 22:15:39.610099 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1408 22:15:39.616868 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1409 22:15:39.620328 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1410 22:15:39.623324 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
1411 22:15:39.627069 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1412 22:15:39.630087 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1413 22:15:39.633463 ==
1414 22:15:39.633583 Dram Type= 6, Freq= 0, CH_0, rank 1
1415 22:15:39.640118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1416 22:15:39.640268 ==
1417 22:15:39.640360 DQS Delay:
1418 22:15:39.643416 DQS0 = 0, DQS1 = 0
1419 22:15:39.643497 DQM Delay:
1420 22:15:39.646845 DQM0 = 93, DQM1 = 82
1421 22:15:39.646925 DQ Delay:
1422 22:15:39.650240 DQ0 =92, DQ1 =96, DQ2 =92, DQ3 =88
1423 22:15:39.653611 DQ4 =92, DQ5 =84, DQ6 =100, DQ7 =100
1424 22:15:39.656816 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1425 22:15:39.660484 DQ12 =84, DQ13 =88, DQ14 =92, DQ15 =88
1426 22:15:39.660565
1427 22:15:39.660628
1428 22:15:39.666788 [DQSOSCAuto] RK1, (LSB)MR18= 0x4212, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
1429 22:15:39.670354 CH0 RK1: MR19=606, MR18=4212
1430 22:15:39.676947 CH0_RK1: MR19=0x606, MR18=0x4212, DQSOSC=393, MR23=63, INC=95, DEC=63
1431 22:15:39.680317 [RxdqsGatingPostProcess] freq 800
1432 22:15:39.684057 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1433 22:15:39.687182 Pre-setting of DQS Precalculation
1434 22:15:39.693636 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1435 22:15:39.693726 ==
1436 22:15:39.697054 Dram Type= 6, Freq= 0, CH_1, rank 0
1437 22:15:39.700421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1438 22:15:39.700502 ==
1439 22:15:39.706992 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1440 22:15:39.713932 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1441 22:15:39.721336 [CA 0] Center 36 (6~67) winsize 62
1442 22:15:39.724900 [CA 1] Center 36 (6~67) winsize 62
1443 22:15:39.727786 [CA 2] Center 35 (5~65) winsize 61
1444 22:15:39.730902 [CA 3] Center 35 (5~65) winsize 61
1445 22:15:39.734547 [CA 4] Center 35 (5~65) winsize 61
1446 22:15:39.738255 [CA 5] Center 34 (4~65) winsize 62
1447 22:15:39.738336
1448 22:15:39.740989 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1449 22:15:39.741070
1450 22:15:39.744718 [CATrainingPosCal] consider 1 rank data
1451 22:15:39.747569 u2DelayCellTimex100 = 270/100 ps
1452 22:15:39.751474 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1453 22:15:39.754598 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1454 22:15:39.761035 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1455 22:15:39.764888 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
1456 22:15:39.768008 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1457 22:15:39.771544 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1458 22:15:39.771624
1459 22:15:39.774552 CA PerBit enable=1, Macro0, CA PI delay=34
1460 22:15:39.774632
1461 22:15:39.777918 [CBTSetCACLKResult] CA Dly = 34
1462 22:15:39.777998 CS Dly: 6 (0~37)
1463 22:15:39.778062 ==
1464 22:15:39.781590 Dram Type= 6, Freq= 0, CH_1, rank 1
1465 22:15:39.787803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1466 22:15:39.787883 ==
1467 22:15:39.791377 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1468 22:15:39.797937 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1469 22:15:39.807505 [CA 0] Center 36 (6~67) winsize 62
1470 22:15:39.810988 [CA 1] Center 37 (6~68) winsize 63
1471 22:15:39.813893 [CA 2] Center 35 (5~66) winsize 62
1472 22:15:39.817481 [CA 3] Center 34 (4~65) winsize 62
1473 22:15:39.820934 [CA 4] Center 35 (5~66) winsize 62
1474 22:15:39.824011 [CA 5] Center 34 (4~65) winsize 62
1475 22:15:39.824090
1476 22:15:39.827460 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1477 22:15:39.827539
1478 22:15:39.831134 [CATrainingPosCal] consider 2 rank data
1479 22:15:39.834959 u2DelayCellTimex100 = 270/100 ps
1480 22:15:39.838565 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1481 22:15:39.841889 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1482 22:15:39.845430 CA2 delay=35 (5~65),Diff = 1 PI (7 cell)
1483 22:15:39.849455 CA3 delay=35 (5~65),Diff = 1 PI (7 cell)
1484 22:15:39.853594 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1485 22:15:39.857066 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1486 22:15:39.857147
1487 22:15:39.860336 CA PerBit enable=1, Macro0, CA PI delay=34
1488 22:15:39.860445
1489 22:15:39.864423 [CBTSetCACLKResult] CA Dly = 34
1490 22:15:39.864533 CS Dly: 6 (0~38)
1491 22:15:39.864625
1492 22:15:39.867798 ----->DramcWriteLeveling(PI) begin...
1493 22:15:39.867900 ==
1494 22:15:39.871405 Dram Type= 6, Freq= 0, CH_1, rank 0
1495 22:15:39.877647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1496 22:15:39.877750 ==
1497 22:15:39.881127 Write leveling (Byte 0): 28 => 28
1498 22:15:39.881225 Write leveling (Byte 1): 28 => 28
1499 22:15:39.884828 DramcWriteLeveling(PI) end<-----
1500 22:15:39.884937
1501 22:15:39.885030 ==
1502 22:15:39.887804 Dram Type= 6, Freq= 0, CH_1, rank 0
1503 22:15:39.894641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1504 22:15:39.894724 ==
1505 22:15:39.898183 [Gating] SW mode calibration
1506 22:15:39.904872 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1507 22:15:39.907924 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1508 22:15:39.914549 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1509 22:15:39.918229 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1510 22:15:39.921376 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 22:15:39.924977 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1512 22:15:39.931457 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1513 22:15:39.934534 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1514 22:15:39.938315 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1515 22:15:39.944971 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1516 22:15:39.948241 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1517 22:15:39.951541 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1518 22:15:39.958427 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1519 22:15:39.961708 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1520 22:15:39.965182 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 22:15:39.971280 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 22:15:39.975025 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 22:15:39.978303 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 22:15:39.984882 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1525 22:15:39.988184 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1526 22:15:39.991394 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 22:15:39.998169 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 22:15:40.001721 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 22:15:40.004907 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 22:15:40.008485 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 22:15:40.014625 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 22:15:40.018154 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 22:15:40.021718 0 9 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1534 22:15:40.028373 0 9 8 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
1535 22:15:40.031533 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1536 22:15:40.035202 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1537 22:15:40.042018 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1538 22:15:40.044892 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1539 22:15:40.048304 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1540 22:15:40.055219 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1541 22:15:40.058422 0 10 4 | B1->B0 | 3232 3030 | 0 1 | (0 1) (0 1)
1542 22:15:40.062076 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1543 22:15:40.068413 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 22:15:40.071800 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 22:15:40.075418 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 22:15:40.081949 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 22:15:40.085096 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 22:15:40.088476 0 11 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1549 22:15:40.091580 0 11 4 | B1->B0 | 2828 3535 | 0 0 | (0 0) (0 0)
1550 22:15:40.098703 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1551 22:15:40.101980 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1552 22:15:40.105109 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1553 22:15:40.111964 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1554 22:15:40.115397 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1555 22:15:40.118434 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1556 22:15:40.125122 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1557 22:15:40.128532 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1558 22:15:40.132165 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1559 22:15:40.138372 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1560 22:15:40.142023 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1561 22:15:40.145228 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1562 22:15:40.152129 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1563 22:15:40.155226 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1564 22:15:40.158372 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1565 22:15:40.161775 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1566 22:15:40.168511 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1567 22:15:40.171976 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1568 22:15:40.175270 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 22:15:40.182182 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 22:15:40.185079 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 22:15:40.188546 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 22:15:40.195306 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 22:15:40.198645 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1574 22:15:40.202179 Total UI for P1: 0, mck2ui 16
1575 22:15:40.205823 best dqsien dly found for B1: ( 0, 14, 2)
1576 22:15:40.208828 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1577 22:15:40.212137 Total UI for P1: 0, mck2ui 16
1578 22:15:40.215871 best dqsien dly found for B0: ( 0, 14, 4)
1579 22:15:40.218791 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1580 22:15:40.221927 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1581 22:15:40.222025
1582 22:15:40.225309 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1583 22:15:40.232061 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1584 22:15:40.232143 [Gating] SW calibration Done
1585 22:15:40.232209 ==
1586 22:15:40.235498 Dram Type= 6, Freq= 0, CH_1, rank 0
1587 22:15:40.242380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1588 22:15:40.242462 ==
1589 22:15:40.242527 RX Vref Scan: 0
1590 22:15:40.242587
1591 22:15:40.245352 RX Vref 0 -> 0, step: 1
1592 22:15:40.245459
1593 22:15:40.249040 RX Delay -130 -> 252, step: 16
1594 22:15:40.252270 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1595 22:15:40.255497 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1596 22:15:40.258456 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1597 22:15:40.265432 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1598 22:15:40.269096 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1599 22:15:40.272389 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1600 22:15:40.275559 iDelay=222, Bit 6, Center 93 (-18 ~ 205) 224
1601 22:15:40.278854 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1602 22:15:40.282094 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1603 22:15:40.288882 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1604 22:15:40.292779 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1605 22:15:40.295933 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1606 22:15:40.299212 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1607 22:15:40.302842 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1608 22:15:40.308985 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1609 22:15:40.313005 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1610 22:15:40.313087 ==
1611 22:15:40.315866 Dram Type= 6, Freq= 0, CH_1, rank 0
1612 22:15:40.319083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1613 22:15:40.319165 ==
1614 22:15:40.322947 DQS Delay:
1615 22:15:40.323028 DQS0 = 0, DQS1 = 0
1616 22:15:40.323092 DQM Delay:
1617 22:15:40.325963 DQM0 = 92, DQM1 = 88
1618 22:15:40.326044 DQ Delay:
1619 22:15:40.329674 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1620 22:15:40.332620 DQ4 =93, DQ5 =109, DQ6 =93, DQ7 =93
1621 22:15:40.336301 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1622 22:15:40.339147 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =101
1623 22:15:40.339228
1624 22:15:40.339292
1625 22:15:40.339351 ==
1626 22:15:40.342712 Dram Type= 6, Freq= 0, CH_1, rank 0
1627 22:15:40.349378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1628 22:15:40.349471 ==
1629 22:15:40.349574
1630 22:15:40.349638
1631 22:15:40.349697 TX Vref Scan disable
1632 22:15:40.352748 == TX Byte 0 ==
1633 22:15:40.356120 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1634 22:15:40.359592 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1635 22:15:40.362601 == TX Byte 1 ==
1636 22:15:40.365864 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1637 22:15:40.369353 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1638 22:15:40.373097 ==
1639 22:15:40.375983 Dram Type= 6, Freq= 0, CH_1, rank 0
1640 22:15:40.379488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1641 22:15:40.379571 ==
1642 22:15:40.391958 TX Vref=22, minBit 0, minWin=26, winSum=440
1643 22:15:40.394926 TX Vref=24, minBit 1, minWin=26, winSum=439
1644 22:15:40.398334 TX Vref=26, minBit 3, minWin=26, winSum=444
1645 22:15:40.401393 TX Vref=28, minBit 1, minWin=27, winSum=449
1646 22:15:40.405036 TX Vref=30, minBit 1, minWin=27, winSum=449
1647 22:15:40.408016 TX Vref=32, minBit 0, minWin=27, winSum=446
1648 22:15:40.415617 [TxChooseVref] Worse bit 1, Min win 27, Win sum 449, Final Vref 28
1649 22:15:40.415724
1650 22:15:40.419248 Final TX Range 1 Vref 28
1651 22:15:40.419326
1652 22:15:40.419390 ==
1653 22:15:40.422459 Dram Type= 6, Freq= 0, CH_1, rank 0
1654 22:15:40.425984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1655 22:15:40.426082 ==
1656 22:15:40.426173
1657 22:15:40.426259
1658 22:15:40.429506 TX Vref Scan disable
1659 22:15:40.432345 == TX Byte 0 ==
1660 22:15:40.435893 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1661 22:15:40.439011 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1662 22:15:40.442754 == TX Byte 1 ==
1663 22:15:40.445787 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1664 22:15:40.449174 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1665 22:15:40.449272
1666 22:15:40.449366 [DATLAT]
1667 22:15:40.452285 Freq=800, CH1 RK0
1668 22:15:40.452382
1669 22:15:40.455954 DATLAT Default: 0xa
1670 22:15:40.456048 0, 0xFFFF, sum = 0
1671 22:15:40.459297 1, 0xFFFF, sum = 0
1672 22:15:40.459371 2, 0xFFFF, sum = 0
1673 22:15:40.462672 3, 0xFFFF, sum = 0
1674 22:15:40.462744 4, 0xFFFF, sum = 0
1675 22:15:40.465710 5, 0xFFFF, sum = 0
1676 22:15:40.465807 6, 0xFFFF, sum = 0
1677 22:15:40.469256 7, 0xFFFF, sum = 0
1678 22:15:40.469356 8, 0xFFFF, sum = 0
1679 22:15:40.472883 9, 0x0, sum = 1
1680 22:15:40.472980 10, 0x0, sum = 2
1681 22:15:40.475893 11, 0x0, sum = 3
1682 22:15:40.475988 12, 0x0, sum = 4
1683 22:15:40.476080 best_step = 10
1684 22:15:40.478948
1685 22:15:40.479043 ==
1686 22:15:40.482481 Dram Type= 6, Freq= 0, CH_1, rank 0
1687 22:15:40.485925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1688 22:15:40.485998 ==
1689 22:15:40.486069 RX Vref Scan: 1
1690 22:15:40.486132
1691 22:15:40.489195 Set Vref Range= 32 -> 127
1692 22:15:40.489287
1693 22:15:40.492200 RX Vref 32 -> 127, step: 1
1694 22:15:40.492269
1695 22:15:40.495853 RX Delay -79 -> 252, step: 8
1696 22:15:40.495947
1697 22:15:40.499288 Set Vref, RX VrefLevel [Byte0]: 32
1698 22:15:40.502540 [Byte1]: 32
1699 22:15:40.502616
1700 22:15:40.506047 Set Vref, RX VrefLevel [Byte0]: 33
1701 22:15:40.509267 [Byte1]: 33
1702 22:15:40.509364
1703 22:15:40.512727 Set Vref, RX VrefLevel [Byte0]: 34
1704 22:15:40.516120 [Byte1]: 34
1705 22:15:40.518921
1706 22:15:40.518997 Set Vref, RX VrefLevel [Byte0]: 35
1707 22:15:40.522623 [Byte1]: 35
1708 22:15:40.526778
1709 22:15:40.526877 Set Vref, RX VrefLevel [Byte0]: 36
1710 22:15:40.529921 [Byte1]: 36
1711 22:15:40.534383
1712 22:15:40.534461 Set Vref, RX VrefLevel [Byte0]: 37
1713 22:15:40.537466 [Byte1]: 37
1714 22:15:40.541946
1715 22:15:40.542046 Set Vref, RX VrefLevel [Byte0]: 38
1716 22:15:40.544929 [Byte1]: 38
1717 22:15:40.549625
1718 22:15:40.549701 Set Vref, RX VrefLevel [Byte0]: 39
1719 22:15:40.552523 [Byte1]: 39
1720 22:15:40.556781
1721 22:15:40.556877 Set Vref, RX VrefLevel [Byte0]: 40
1722 22:15:40.560194 [Byte1]: 40
1723 22:15:40.564689
1724 22:15:40.564785 Set Vref, RX VrefLevel [Byte0]: 41
1725 22:15:40.567533 [Byte1]: 41
1726 22:15:40.572133
1727 22:15:40.572234 Set Vref, RX VrefLevel [Byte0]: 42
1728 22:15:40.575049 [Byte1]: 42
1729 22:15:40.579816
1730 22:15:40.579913 Set Vref, RX VrefLevel [Byte0]: 43
1731 22:15:40.582837 [Byte1]: 43
1732 22:15:40.587031
1733 22:15:40.587101 Set Vref, RX VrefLevel [Byte0]: 44
1734 22:15:40.590653 [Byte1]: 44
1735 22:15:40.594678
1736 22:15:40.594750 Set Vref, RX VrefLevel [Byte0]: 45
1737 22:15:40.597719 [Byte1]: 45
1738 22:15:40.602321
1739 22:15:40.602392 Set Vref, RX VrefLevel [Byte0]: 46
1740 22:15:40.605717 [Byte1]: 46
1741 22:15:40.610154
1742 22:15:40.610227 Set Vref, RX VrefLevel [Byte0]: 47
1743 22:15:40.613432 [Byte1]: 47
1744 22:15:40.617300
1745 22:15:40.617392 Set Vref, RX VrefLevel [Byte0]: 48
1746 22:15:40.620492 [Byte1]: 48
1747 22:15:40.625017
1748 22:15:40.625114 Set Vref, RX VrefLevel [Byte0]: 49
1749 22:15:40.628371 [Byte1]: 49
1750 22:15:40.632322
1751 22:15:40.632430 Set Vref, RX VrefLevel [Byte0]: 50
1752 22:15:40.635581 [Byte1]: 50
1753 22:15:40.640176
1754 22:15:40.640259 Set Vref, RX VrefLevel [Byte0]: 51
1755 22:15:40.643585 [Byte1]: 51
1756 22:15:40.647457
1757 22:15:40.647548 Set Vref, RX VrefLevel [Byte0]: 52
1758 22:15:40.651125 [Byte1]: 52
1759 22:15:40.655161
1760 22:15:40.655245 Set Vref, RX VrefLevel [Byte0]: 53
1761 22:15:40.658233 [Byte1]: 53
1762 22:15:40.662282
1763 22:15:40.662365 Set Vref, RX VrefLevel [Byte0]: 54
1764 22:15:40.666200 [Byte1]: 54
1765 22:15:40.670205
1766 22:15:40.670288 Set Vref, RX VrefLevel [Byte0]: 55
1767 22:15:40.673219 [Byte1]: 55
1768 22:15:40.677423
1769 22:15:40.677506 Set Vref, RX VrefLevel [Byte0]: 56
1770 22:15:40.681331 [Byte1]: 56
1771 22:15:40.685433
1772 22:15:40.685537 Set Vref, RX VrefLevel [Byte0]: 57
1773 22:15:40.688521 [Byte1]: 57
1774 22:15:40.693123
1775 22:15:40.693207 Set Vref, RX VrefLevel [Byte0]: 58
1776 22:15:40.696177 [Byte1]: 58
1777 22:15:40.700521
1778 22:15:40.700604 Set Vref, RX VrefLevel [Byte0]: 59
1779 22:15:40.703489 [Byte1]: 59
1780 22:15:40.707611
1781 22:15:40.707741 Set Vref, RX VrefLevel [Byte0]: 60
1782 22:15:40.711221 [Byte1]: 60
1783 22:15:40.715473
1784 22:15:40.715557 Set Vref, RX VrefLevel [Byte0]: 61
1785 22:15:40.719059 [Byte1]: 61
1786 22:15:40.722858
1787 22:15:40.722941 Set Vref, RX VrefLevel [Byte0]: 62
1788 22:15:40.726172 [Byte1]: 62
1789 22:15:40.730813
1790 22:15:40.730897 Set Vref, RX VrefLevel [Byte0]: 63
1791 22:15:40.733816 [Byte1]: 63
1792 22:15:40.738064
1793 22:15:40.738148 Set Vref, RX VrefLevel [Byte0]: 64
1794 22:15:40.741885 [Byte1]: 64
1795 22:15:40.745497
1796 22:15:40.745602 Set Vref, RX VrefLevel [Byte0]: 65
1797 22:15:40.748732 [Byte1]: 65
1798 22:15:40.753610
1799 22:15:40.753694 Set Vref, RX VrefLevel [Byte0]: 66
1800 22:15:40.756431 [Byte1]: 66
1801 22:15:40.760699
1802 22:15:40.760782 Set Vref, RX VrefLevel [Byte0]: 67
1803 22:15:40.763894 [Byte1]: 67
1804 22:15:40.768558
1805 22:15:40.768642 Set Vref, RX VrefLevel [Byte0]: 68
1806 22:15:40.771704 [Byte1]: 68
1807 22:15:40.775642
1808 22:15:40.775725 Set Vref, RX VrefLevel [Byte0]: 69
1809 22:15:40.779370 [Byte1]: 69
1810 22:15:40.783617
1811 22:15:40.783700 Set Vref, RX VrefLevel [Byte0]: 70
1812 22:15:40.787005 [Byte1]: 70
1813 22:15:40.791296
1814 22:15:40.791379 Set Vref, RX VrefLevel [Byte0]: 71
1815 22:15:40.794125 [Byte1]: 71
1816 22:15:40.798258
1817 22:15:40.798341 Set Vref, RX VrefLevel [Byte0]: 72
1818 22:15:40.801800 [Byte1]: 72
1819 22:15:40.806047
1820 22:15:40.806130 Final RX Vref Byte 0 = 61 to rank0
1821 22:15:40.809632 Final RX Vref Byte 1 = 55 to rank0
1822 22:15:40.812668 Final RX Vref Byte 0 = 61 to rank1
1823 22:15:40.816086 Final RX Vref Byte 1 = 55 to rank1==
1824 22:15:40.819637 Dram Type= 6, Freq= 0, CH_1, rank 0
1825 22:15:40.825876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1826 22:15:40.825961 ==
1827 22:15:40.826046 DQS Delay:
1828 22:15:40.826125 DQS0 = 0, DQS1 = 0
1829 22:15:40.829288 DQM Delay:
1830 22:15:40.829370 DQM0 = 95, DQM1 = 90
1831 22:15:40.832606 DQ Delay:
1832 22:15:40.835977 DQ0 =100, DQ1 =88, DQ2 =84, DQ3 =88
1833 22:15:40.839431 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =92
1834 22:15:40.839521 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1835 22:15:40.846329 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =100
1836 22:15:40.846412
1837 22:15:40.846495
1838 22:15:40.853333 [DQSOSCAuto] RK0, (LSB)MR18= 0x304c, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1839 22:15:40.856157 CH1 RK0: MR19=606, MR18=304C
1840 22:15:40.863070 CH1_RK0: MR19=0x606, MR18=0x304C, DQSOSC=390, MR23=63, INC=97, DEC=64
1841 22:15:40.863157
1842 22:15:40.866188 ----->DramcWriteLeveling(PI) begin...
1843 22:15:40.866273 ==
1844 22:15:40.869504 Dram Type= 6, Freq= 0, CH_1, rank 1
1845 22:15:40.873130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1846 22:15:40.873214 ==
1847 22:15:40.876648 Write leveling (Byte 0): 29 => 29
1848 22:15:40.879637 Write leveling (Byte 1): 29 => 29
1849 22:15:40.883217 DramcWriteLeveling(PI) end<-----
1850 22:15:40.883300
1851 22:15:40.883384 ==
1852 22:15:40.886406 Dram Type= 6, Freq= 0, CH_1, rank 1
1853 22:15:40.889788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1854 22:15:40.889873 ==
1855 22:15:40.892984 [Gating] SW mode calibration
1856 22:15:40.900267 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1857 22:15:40.906951 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1858 22:15:40.910062 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1859 22:15:40.913622 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1860 22:15:40.920141 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 22:15:40.923716 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 22:15:40.926674 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 22:15:40.930084 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1864 22:15:40.936740 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1865 22:15:40.940447 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1866 22:15:40.943564 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1867 22:15:40.950200 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 22:15:40.953436 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 22:15:40.956828 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 22:15:40.963440 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 22:15:40.966783 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 22:15:40.970016 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 22:15:40.976904 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1874 22:15:40.979960 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1875 22:15:40.983493 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 22:15:40.990136 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 22:15:40.993379 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 22:15:40.996836 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 22:15:41.003279 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 22:15:41.006849 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 22:15:41.010467 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1882 22:15:41.013602 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1883 22:15:41.020494 0 9 4 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
1884 22:15:41.023965 0 9 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1885 22:15:41.027202 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1886 22:15:41.033923 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1887 22:15:41.037413 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1888 22:15:41.040415 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1889 22:15:41.047416 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1890 22:15:41.050573 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1891 22:15:41.054023 0 10 4 | B1->B0 | 2424 3131 | 0 0 | (1 0) (0 1)
1892 22:15:41.060921 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1893 22:15:41.064283 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 22:15:41.067231 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 22:15:41.074282 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 22:15:41.077233 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 22:15:41.080387 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 22:15:41.083965 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 22:15:41.090497 0 11 4 | B1->B0 | 3838 2828 | 0 0 | (0 0) (0 0)
1900 22:15:41.094040 0 11 8 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
1901 22:15:41.097280 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1902 22:15:41.103991 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1903 22:15:41.107009 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1904 22:15:41.110483 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1905 22:15:41.117256 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1906 22:15:41.120754 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1907 22:15:41.124175 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1908 22:15:41.130553 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1909 22:15:41.134017 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1910 22:15:41.137460 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1911 22:15:41.144250 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1912 22:15:41.147334 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1913 22:15:41.150589 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1914 22:15:41.154210 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1915 22:15:41.160986 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 22:15:41.164311 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 22:15:41.167510 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 22:15:41.173859 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 22:15:41.177178 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 22:15:41.181070 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 22:15:41.187386 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 22:15:41.190646 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1923 22:15:41.194443 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1924 22:15:41.197343 Total UI for P1: 0, mck2ui 16
1925 22:15:41.201157 best dqsien dly found for B0: ( 0, 14, 2)
1926 22:15:41.204040 Total UI for P1: 0, mck2ui 16
1927 22:15:41.207497 best dqsien dly found for B1: ( 0, 14, 0)
1928 22:15:41.210523 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1929 22:15:41.214522 best DQS1 dly(MCK, UI, PI) = (0, 14, 0)
1930 22:15:41.214604
1931 22:15:41.217341 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1932 22:15:41.224556 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 0)
1933 22:15:41.224638 [Gating] SW calibration Done
1934 22:15:41.224703 ==
1935 22:15:41.227640 Dram Type= 6, Freq= 0, CH_1, rank 1
1936 22:15:41.234769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1937 22:15:41.234852 ==
1938 22:15:41.234918 RX Vref Scan: 0
1939 22:15:41.234978
1940 22:15:41.237867 RX Vref 0 -> 0, step: 1
1941 22:15:41.237949
1942 22:15:41.240766 RX Delay -130 -> 252, step: 16
1943 22:15:41.244427 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1944 22:15:41.247977 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1945 22:15:41.251264 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1946 22:15:41.254337 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1947 22:15:41.260934 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1948 22:15:41.264878 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1949 22:15:41.267878 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1950 22:15:41.271089 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1951 22:15:41.274231 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1952 22:15:41.281019 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1953 22:15:41.284485 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1954 22:15:41.287851 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1955 22:15:41.290925 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1956 22:15:41.294356 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1957 22:15:41.300912 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1958 22:15:41.304707 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1959 22:15:41.304789 ==
1960 22:15:41.307643 Dram Type= 6, Freq= 0, CH_1, rank 1
1961 22:15:41.311221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1962 22:15:41.311307 ==
1963 22:15:41.314250 DQS Delay:
1964 22:15:41.314380 DQS0 = 0, DQS1 = 0
1965 22:15:41.314510 DQM Delay:
1966 22:15:41.317810 DQM0 = 92, DQM1 = 87
1967 22:15:41.317891 DQ Delay:
1968 22:15:41.320954 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =85
1969 22:15:41.324254 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1970 22:15:41.327907 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =77
1971 22:15:41.331459 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1972 22:15:41.331540
1973 22:15:41.331606
1974 22:15:41.331666 ==
1975 22:15:41.334525 Dram Type= 6, Freq= 0, CH_1, rank 1
1976 22:15:41.341133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1977 22:15:41.341215 ==
1978 22:15:41.341280
1979 22:15:41.341340
1980 22:15:41.341398 TX Vref Scan disable
1981 22:15:41.344736 == TX Byte 0 ==
1982 22:15:41.348460 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1983 22:15:41.351934 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1984 22:15:41.354692 == TX Byte 1 ==
1985 22:15:41.358259 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1986 22:15:41.361824 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1987 22:15:41.365349 ==
1988 22:15:41.368660 Dram Type= 6, Freq= 0, CH_1, rank 1
1989 22:15:41.371903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1990 22:15:41.371986 ==
1991 22:15:41.383990 TX Vref=22, minBit 1, minWin=26, winSum=442
1992 22:15:41.387576 TX Vref=24, minBit 2, minWin=27, winSum=450
1993 22:15:41.390567 TX Vref=26, minBit 2, minWin=27, winSum=450
1994 22:15:41.393928 TX Vref=28, minBit 2, minWin=27, winSum=450
1995 22:15:41.397433 TX Vref=30, minBit 2, minWin=27, winSum=449
1996 22:15:41.400568 TX Vref=32, minBit 2, minWin=27, winSum=450
1997 22:15:41.407071 [TxChooseVref] Worse bit 2, Min win 27, Win sum 450, Final Vref 24
1998 22:15:41.407155
1999 22:15:41.410611 Final TX Range 1 Vref 24
2000 22:15:41.410695
2001 22:15:41.410760 ==
2002 22:15:41.414301 Dram Type= 6, Freq= 0, CH_1, rank 1
2003 22:15:41.417375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2004 22:15:41.417458 ==
2005 22:15:41.417546
2006 22:15:41.420409
2007 22:15:41.420490 TX Vref Scan disable
2008 22:15:41.423917 == TX Byte 0 ==
2009 22:15:41.427280 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2010 22:15:41.430469 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2011 22:15:41.434002 == TX Byte 1 ==
2012 22:15:41.437061 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2013 22:15:41.440622 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2014 22:15:41.443717
2015 22:15:41.443799 [DATLAT]
2016 22:15:41.443865 Freq=800, CH1 RK1
2017 22:15:41.443928
2018 22:15:41.447344 DATLAT Default: 0xa
2019 22:15:41.447426 0, 0xFFFF, sum = 0
2020 22:15:41.450501 1, 0xFFFF, sum = 0
2021 22:15:41.450585 2, 0xFFFF, sum = 0
2022 22:15:41.453810 3, 0xFFFF, sum = 0
2023 22:15:41.453894 4, 0xFFFF, sum = 0
2024 22:15:41.457217 5, 0xFFFF, sum = 0
2025 22:15:41.457301 6, 0xFFFF, sum = 0
2026 22:15:41.460484 7, 0xFFFF, sum = 0
2027 22:15:41.464026 8, 0xFFFF, sum = 0
2028 22:15:41.464110 9, 0x0, sum = 1
2029 22:15:41.464176 10, 0x0, sum = 2
2030 22:15:41.467567 11, 0x0, sum = 3
2031 22:15:41.467651 12, 0x0, sum = 4
2032 22:15:41.470633 best_step = 10
2033 22:15:41.470716
2034 22:15:41.470781 ==
2035 22:15:41.473805 Dram Type= 6, Freq= 0, CH_1, rank 1
2036 22:15:41.477164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2037 22:15:41.477247 ==
2038 22:15:41.480737 RX Vref Scan: 0
2039 22:15:41.480819
2040 22:15:41.480885 RX Vref 0 -> 0, step: 1
2041 22:15:41.480946
2042 22:15:41.483584 RX Delay -79 -> 252, step: 8
2043 22:15:41.490560 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2044 22:15:41.494114 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2045 22:15:41.497059 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2046 22:15:41.500754 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2047 22:15:41.504023 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2048 22:15:41.507184 iDelay=209, Bit 5, Center 108 (9 ~ 208) 200
2049 22:15:41.513928 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2050 22:15:41.517149 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2051 22:15:41.520566 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2052 22:15:41.524148 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2053 22:15:41.527251 iDelay=209, Bit 10, Center 92 (-15 ~ 200) 216
2054 22:15:41.534125 iDelay=209, Bit 11, Center 88 (-15 ~ 192) 208
2055 22:15:41.537398 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2056 22:15:41.540397 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2057 22:15:41.543791 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2058 22:15:41.547524 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2059 22:15:41.547660 ==
2060 22:15:41.550817 Dram Type= 6, Freq= 0, CH_1, rank 1
2061 22:15:41.556971 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2062 22:15:41.557055 ==
2063 22:15:41.557122 DQS Delay:
2064 22:15:41.560393 DQS0 = 0, DQS1 = 0
2065 22:15:41.560476 DQM Delay:
2066 22:15:41.560541 DQM0 = 97, DQM1 = 91
2067 22:15:41.564074 DQ Delay:
2068 22:15:41.567237 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2069 22:15:41.570668 DQ4 =92, DQ5 =108, DQ6 =108, DQ7 =96
2070 22:15:41.574211 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =88
2071 22:15:41.577690 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2072 22:15:41.577772
2073 22:15:41.577838
2074 22:15:41.584011 [DQSOSCAuto] RK1, (LSB)MR18= 0x4a13, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
2075 22:15:41.587303 CH1 RK1: MR19=606, MR18=4A13
2076 22:15:41.593977 CH1_RK1: MR19=0x606, MR18=0x4A13, DQSOSC=391, MR23=63, INC=96, DEC=64
2077 22:15:41.597671 [RxdqsGatingPostProcess] freq 800
2078 22:15:41.600659 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2079 22:15:41.603954 Pre-setting of DQS Precalculation
2080 22:15:41.611381 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2081 22:15:41.617344 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2082 22:15:41.624248 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2083 22:15:41.624330
2084 22:15:41.624395
2085 22:15:41.627772 [Calibration Summary] 1600 Mbps
2086 22:15:41.627853 CH 0, Rank 0
2087 22:15:41.630916 SW Impedance : PASS
2088 22:15:41.634331 DUTY Scan : NO K
2089 22:15:41.634412 ZQ Calibration : PASS
2090 22:15:41.638043 Jitter Meter : NO K
2091 22:15:41.641192 CBT Training : PASS
2092 22:15:41.641273 Write leveling : PASS
2093 22:15:41.644186 RX DQS gating : PASS
2094 22:15:41.647727 RX DQ/DQS(RDDQC) : PASS
2095 22:15:41.647809 TX DQ/DQS : PASS
2096 22:15:41.650920 RX DATLAT : PASS
2097 22:15:41.651071 RX DQ/DQS(Engine): PASS
2098 22:15:41.654033 TX OE : NO K
2099 22:15:41.654115 All Pass.
2100 22:15:41.654179
2101 22:15:41.657837 CH 0, Rank 1
2102 22:15:41.660834 SW Impedance : PASS
2103 22:15:41.660915 DUTY Scan : NO K
2104 22:15:41.664253 ZQ Calibration : PASS
2105 22:15:41.664334 Jitter Meter : NO K
2106 22:15:41.667266 CBT Training : PASS
2107 22:15:41.670934 Write leveling : PASS
2108 22:15:41.671015 RX DQS gating : PASS
2109 22:15:41.674485 RX DQ/DQS(RDDQC) : PASS
2110 22:15:41.678083 TX DQ/DQS : PASS
2111 22:15:41.678168 RX DATLAT : PASS
2112 22:15:41.680799 RX DQ/DQS(Engine): PASS
2113 22:15:41.684150 TX OE : NO K
2114 22:15:41.684233 All Pass.
2115 22:15:41.684299
2116 22:15:41.684358 CH 1, Rank 0
2117 22:15:41.687620 SW Impedance : PASS
2118 22:15:41.691379 DUTY Scan : NO K
2119 22:15:41.691459 ZQ Calibration : PASS
2120 22:15:41.694388 Jitter Meter : NO K
2121 22:15:41.697466 CBT Training : PASS
2122 22:15:41.697556 Write leveling : PASS
2123 22:15:41.701107 RX DQS gating : PASS
2124 22:15:41.701188 RX DQ/DQS(RDDQC) : PASS
2125 22:15:41.704451 TX DQ/DQS : PASS
2126 22:15:41.707863 RX DATLAT : PASS
2127 22:15:41.707944 RX DQ/DQS(Engine): PASS
2128 22:15:41.711291 TX OE : NO K
2129 22:15:41.711372 All Pass.
2130 22:15:41.711441
2131 22:15:41.714646 CH 1, Rank 1
2132 22:15:41.714727 SW Impedance : PASS
2133 22:15:41.718035 DUTY Scan : NO K
2134 22:15:41.721084 ZQ Calibration : PASS
2135 22:15:41.721165 Jitter Meter : NO K
2136 22:15:41.724297 CBT Training : PASS
2137 22:15:41.727952 Write leveling : PASS
2138 22:15:41.728033 RX DQS gating : PASS
2139 22:15:41.730968 RX DQ/DQS(RDDQC) : PASS
2140 22:15:41.734430 TX DQ/DQS : PASS
2141 22:15:41.734512 RX DATLAT : PASS
2142 22:15:41.738323 RX DQ/DQS(Engine): PASS
2143 22:15:41.738404 TX OE : NO K
2144 22:15:41.740950 All Pass.
2145 22:15:41.741031
2146 22:15:41.741095 DramC Write-DBI off
2147 22:15:41.744363 PER_BANK_REFRESH: Hybrid Mode
2148 22:15:41.747838 TX_TRACKING: ON
2149 22:15:41.751152 [GetDramInforAfterCalByMRR] Vendor 6.
2150 22:15:41.754381 [GetDramInforAfterCalByMRR] Revision 606.
2151 22:15:41.757597 [GetDramInforAfterCalByMRR] Revision 2 0.
2152 22:15:41.757706 MR0 0x3b3b
2153 22:15:41.757782 MR8 0x5151
2154 22:15:41.764346 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2155 22:15:41.764427
2156 22:15:41.764492 MR0 0x3b3b
2157 22:15:41.764551 MR8 0x5151
2158 22:15:41.767877 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2159 22:15:41.767958
2160 22:15:41.777829 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2161 22:15:41.781309 [FAST_K] Save calibration result to emmc
2162 22:15:41.784777 [FAST_K] Save calibration result to emmc
2163 22:15:41.787701 dram_init: config_dvfs: 1
2164 22:15:41.791337 dramc_set_vcore_voltage set vcore to 662500
2165 22:15:41.795039 Read voltage for 1200, 2
2166 22:15:41.795121 Vio18 = 0
2167 22:15:41.795185 Vcore = 662500
2168 22:15:41.797711 Vdram = 0
2169 22:15:41.797792 Vddq = 0
2170 22:15:41.797856 Vmddr = 0
2171 22:15:41.804565 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2172 22:15:41.808029 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2173 22:15:41.811269 MEM_TYPE=3, freq_sel=15
2174 22:15:41.814815 sv_algorithm_assistance_LP4_1600
2175 22:15:41.818213 ============ PULL DRAM RESETB DOWN ============
2176 22:15:41.821746 ========== PULL DRAM RESETB DOWN end =========
2177 22:15:41.827803 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2178 22:15:41.831185 ===================================
2179 22:15:41.831268 LPDDR4 DRAM CONFIGURATION
2180 22:15:41.834526 ===================================
2181 22:15:41.838128 EX_ROW_EN[0] = 0x0
2182 22:15:41.841075 EX_ROW_EN[1] = 0x0
2183 22:15:41.841184 LP4Y_EN = 0x0
2184 22:15:41.844611 WORK_FSP = 0x0
2185 22:15:41.844724 WL = 0x4
2186 22:15:41.848093 RL = 0x4
2187 22:15:41.848197 BL = 0x2
2188 22:15:41.851659 RPST = 0x0
2189 22:15:41.851754 RD_PRE = 0x0
2190 22:15:41.854369 WR_PRE = 0x1
2191 22:15:41.854466 WR_PST = 0x0
2192 22:15:41.857753 DBI_WR = 0x0
2193 22:15:41.857823 DBI_RD = 0x0
2194 22:15:41.861596 OTF = 0x1
2195 22:15:41.864673 ===================================
2196 22:15:41.868097 ===================================
2197 22:15:41.868202 ANA top config
2198 22:15:41.871775 ===================================
2199 22:15:41.874876 DLL_ASYNC_EN = 0
2200 22:15:41.877834 ALL_SLAVE_EN = 0
2201 22:15:41.877903 NEW_RANK_MODE = 1
2202 22:15:41.881405 DLL_IDLE_MODE = 1
2203 22:15:41.884994 LP45_APHY_COMB_EN = 1
2204 22:15:41.887929 TX_ODT_DIS = 1
2205 22:15:41.891795 NEW_8X_MODE = 1
2206 22:15:41.895042 ===================================
2207 22:15:41.895114 ===================================
2208 22:15:41.898032 data_rate = 2400
2209 22:15:41.901526 CKR = 1
2210 22:15:41.904923 DQ_P2S_RATIO = 8
2211 22:15:41.908248 ===================================
2212 22:15:41.911535 CA_P2S_RATIO = 8
2213 22:15:41.915187 DQ_CA_OPEN = 0
2214 22:15:41.918527 DQ_SEMI_OPEN = 0
2215 22:15:41.918601 CA_SEMI_OPEN = 0
2216 22:15:41.921504 CA_FULL_RATE = 0
2217 22:15:41.924978 DQ_CKDIV4_EN = 0
2218 22:15:41.928346 CA_CKDIV4_EN = 0
2219 22:15:41.931533 CA_PREDIV_EN = 0
2220 22:15:41.931634 PH8_DLY = 17
2221 22:15:41.935006 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2222 22:15:41.938138 DQ_AAMCK_DIV = 4
2223 22:15:41.941700 CA_AAMCK_DIV = 4
2224 22:15:41.945222 CA_ADMCK_DIV = 4
2225 22:15:41.948431 DQ_TRACK_CA_EN = 0
2226 22:15:41.951934 CA_PICK = 1200
2227 22:15:41.952031 CA_MCKIO = 1200
2228 22:15:41.954930 MCKIO_SEMI = 0
2229 22:15:41.958560 PLL_FREQ = 2366
2230 22:15:41.961862 DQ_UI_PI_RATIO = 32
2231 22:15:41.965201 CA_UI_PI_RATIO = 0
2232 22:15:41.968541 ===================================
2233 22:15:41.971658 ===================================
2234 22:15:41.975162 memory_type:LPDDR4
2235 22:15:41.975258 GP_NUM : 10
2236 22:15:41.978608 SRAM_EN : 1
2237 22:15:41.978685 MD32_EN : 0
2238 22:15:41.981588 ===================================
2239 22:15:41.985287 [ANA_INIT] >>>>>>>>>>>>>>
2240 22:15:41.988309 <<<<<< [CONFIGURE PHASE]: ANA_TX
2241 22:15:41.991966 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2242 22:15:41.994746 ===================================
2243 22:15:41.998264 data_rate = 2400,PCW = 0X5b00
2244 22:15:42.001719 ===================================
2245 22:15:42.005055 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2246 22:15:42.008311 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2247 22:15:42.014878 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2248 22:15:42.018528 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2249 22:15:42.021882 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2250 22:15:42.028681 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2251 22:15:42.028780 [ANA_INIT] flow start
2252 22:15:42.032109 [ANA_INIT] PLL >>>>>>>>
2253 22:15:42.032209 [ANA_INIT] PLL <<<<<<<<
2254 22:15:42.035336 [ANA_INIT] MIDPI >>>>>>>>
2255 22:15:42.038689 [ANA_INIT] MIDPI <<<<<<<<
2256 22:15:42.041929 [ANA_INIT] DLL >>>>>>>>
2257 22:15:42.042028 [ANA_INIT] DLL <<<<<<<<
2258 22:15:42.045256 [ANA_INIT] flow end
2259 22:15:42.048259 ============ LP4 DIFF to SE enter ============
2260 22:15:42.051827 ============ LP4 DIFF to SE exit ============
2261 22:15:42.055111 [ANA_INIT] <<<<<<<<<<<<<
2262 22:15:42.058383 [Flow] Enable top DCM control >>>>>
2263 22:15:42.061789 [Flow] Enable top DCM control <<<<<
2264 22:15:42.064931 Enable DLL master slave shuffle
2265 22:15:42.068777 ==============================================================
2266 22:15:42.071835 Gating Mode config
2267 22:15:42.078544 ==============================================================
2268 22:15:42.078621 Config description:
2269 22:15:42.088560 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2270 22:15:42.094925 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2271 22:15:42.101853 SELPH_MODE 0: By rank 1: By Phase
2272 22:15:42.105109 ==============================================================
2273 22:15:42.108758 GAT_TRACK_EN = 1
2274 22:15:42.112423 RX_GATING_MODE = 2
2275 22:15:42.114918 RX_GATING_TRACK_MODE = 2
2276 22:15:42.118486 SELPH_MODE = 1
2277 22:15:42.121703 PICG_EARLY_EN = 1
2278 22:15:42.124938 VALID_LAT_VALUE = 1
2279 22:15:42.128838 ==============================================================
2280 22:15:42.131784 Enter into Gating configuration >>>>
2281 22:15:42.135050 Exit from Gating configuration <<<<
2282 22:15:42.138208 Enter into DVFS_PRE_config >>>>>
2283 22:15:42.151623 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2284 22:15:42.151731 Exit from DVFS_PRE_config <<<<<
2285 22:15:42.154993 Enter into PICG configuration >>>>
2286 22:15:42.158494 Exit from PICG configuration <<<<
2287 22:15:42.162059 [RX_INPUT] configuration >>>>>
2288 22:15:42.165265 [RX_INPUT] configuration <<<<<
2289 22:15:42.171849 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2290 22:15:42.175048 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2291 22:15:42.181645 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2292 22:15:42.188613 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2293 22:15:42.195338 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2294 22:15:42.201956 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2295 22:15:42.204981 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2296 22:15:42.208470 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2297 22:15:42.212162 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2298 22:15:42.218485 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2299 22:15:42.221868 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2300 22:15:42.225243 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2301 22:15:42.228457 ===================================
2302 22:15:42.232032 LPDDR4 DRAM CONFIGURATION
2303 22:15:42.235420 ===================================
2304 22:15:42.235521 EX_ROW_EN[0] = 0x0
2305 22:15:42.238265 EX_ROW_EN[1] = 0x0
2306 22:15:42.238343 LP4Y_EN = 0x0
2307 22:15:42.242358 WORK_FSP = 0x0
2308 22:15:42.245535 WL = 0x4
2309 22:15:42.245626 RL = 0x4
2310 22:15:42.248713 BL = 0x2
2311 22:15:42.248798 RPST = 0x0
2312 22:15:42.252187 RD_PRE = 0x0
2313 22:15:42.252287 WR_PRE = 0x1
2314 22:15:42.255323 WR_PST = 0x0
2315 22:15:42.255422 DBI_WR = 0x0
2316 22:15:42.258374 DBI_RD = 0x0
2317 22:15:42.258448 OTF = 0x1
2318 22:15:42.262357 ===================================
2319 22:15:42.265495 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2320 22:15:42.272286 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2321 22:15:42.275310 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2322 22:15:42.278832 ===================================
2323 22:15:42.281929 LPDDR4 DRAM CONFIGURATION
2324 22:15:42.285473 ===================================
2325 22:15:42.285615 EX_ROW_EN[0] = 0x10
2326 22:15:42.289158 EX_ROW_EN[1] = 0x0
2327 22:15:42.289237 LP4Y_EN = 0x0
2328 22:15:42.292156 WORK_FSP = 0x0
2329 22:15:42.292259 WL = 0x4
2330 22:15:42.295535 RL = 0x4
2331 22:15:42.295610 BL = 0x2
2332 22:15:42.298921 RPST = 0x0
2333 22:15:42.298995 RD_PRE = 0x0
2334 22:15:42.301785 WR_PRE = 0x1
2335 22:15:42.301883 WR_PST = 0x0
2336 22:15:42.305454 DBI_WR = 0x0
2337 22:15:42.305564 DBI_RD = 0x0
2338 22:15:42.308935 OTF = 0x1
2339 22:15:42.311888 ===================================
2340 22:15:42.318893 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2341 22:15:42.318983 ==
2342 22:15:42.322274 Dram Type= 6, Freq= 0, CH_0, rank 0
2343 22:15:42.325343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2344 22:15:42.325445 ==
2345 22:15:42.329041 [Duty_Offset_Calibration]
2346 22:15:42.329141 B0:2 B1:1 CA:1
2347 22:15:42.329234
2348 22:15:42.331927 [DutyScan_Calibration_Flow] k_type=0
2349 22:15:42.342915
2350 22:15:42.343015 ==CLK 0==
2351 22:15:42.345823 Final CLK duty delay cell = 0
2352 22:15:42.349424 [0] MAX Duty = 5218%(X100), DQS PI = 24
2353 22:15:42.352902 [0] MIN Duty = 4844%(X100), DQS PI = 48
2354 22:15:42.352975 [0] AVG Duty = 5031%(X100)
2355 22:15:42.355789
2356 22:15:42.355889 CH0 CLK Duty spec in!! Max-Min= 374%
2357 22:15:42.362801 [DutyScan_Calibration_Flow] ====Done====
2358 22:15:42.362902
2359 22:15:42.366112 [DutyScan_Calibration_Flow] k_type=1
2360 22:15:42.380201
2361 22:15:42.380301 ==DQS 0 ==
2362 22:15:42.383883 Final DQS duty delay cell = -4
2363 22:15:42.387147 [-4] MAX Duty = 5124%(X100), DQS PI = 22
2364 22:15:42.390423 [-4] MIN Duty = 4751%(X100), DQS PI = 0
2365 22:15:42.393415 [-4] AVG Duty = 4937%(X100)
2366 22:15:42.393513
2367 22:15:42.393582 ==DQS 1 ==
2368 22:15:42.397122 Final DQS duty delay cell = -4
2369 22:15:42.400378 [-4] MAX Duty = 4969%(X100), DQS PI = 0
2370 22:15:42.404149 [-4] MIN Duty = 4844%(X100), DQS PI = 32
2371 22:15:42.407409 [-4] AVG Duty = 4906%(X100)
2372 22:15:42.407480
2373 22:15:42.410836 CH0 DQS 0 Duty spec in!! Max-Min= 373%
2374 22:15:42.410907
2375 22:15:42.413817 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2376 22:15:42.417239 [DutyScan_Calibration_Flow] ====Done====
2377 22:15:42.417306
2378 22:15:42.420722 [DutyScan_Calibration_Flow] k_type=3
2379 22:15:42.437423
2380 22:15:42.437580 ==DQM 0 ==
2381 22:15:42.440763 Final DQM duty delay cell = 0
2382 22:15:42.444263 [0] MAX Duty = 5156%(X100), DQS PI = 30
2383 22:15:42.447553 [0] MIN Duty = 4938%(X100), DQS PI = 0
2384 22:15:42.447656 [0] AVG Duty = 5047%(X100)
2385 22:15:42.451087
2386 22:15:42.451189 ==DQM 1 ==
2387 22:15:42.453986 Final DQM duty delay cell = 0
2388 22:15:42.457248 [0] MAX Duty = 5093%(X100), DQS PI = 0
2389 22:15:42.461272 [0] MIN Duty = 5031%(X100), DQS PI = 34
2390 22:15:42.461368 [0] AVG Duty = 5062%(X100)
2391 22:15:42.461459
2392 22:15:42.467316 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2393 22:15:42.467412
2394 22:15:42.470578 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2395 22:15:42.473734 [DutyScan_Calibration_Flow] ====Done====
2396 22:15:42.473804
2397 22:15:42.477613 [DutyScan_Calibration_Flow] k_type=2
2398 22:15:42.493610
2399 22:15:42.493706 ==DQ 0 ==
2400 22:15:42.497165 Final DQ duty delay cell = 0
2401 22:15:42.500231 [0] MAX Duty = 5031%(X100), DQS PI = 26
2402 22:15:42.503566 [0] MIN Duty = 4875%(X100), DQS PI = 62
2403 22:15:42.506826 [0] AVG Duty = 4953%(X100)
2404 22:15:42.506905
2405 22:15:42.506974 ==DQ 1 ==
2406 22:15:42.510498 Final DQ duty delay cell = 0
2407 22:15:42.513549 [0] MAX Duty = 5093%(X100), DQS PI = 24
2408 22:15:42.517111 [0] MIN Duty = 4938%(X100), DQS PI = 36
2409 22:15:42.517213 [0] AVG Duty = 5015%(X100)
2410 22:15:42.520248
2411 22:15:42.523981 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2412 22:15:42.524075
2413 22:15:42.527081 CH0 DQ 1 Duty spec in!! Max-Min= 155%
2414 22:15:42.530532 [DutyScan_Calibration_Flow] ====Done====
2415 22:15:42.530625 ==
2416 22:15:42.533495 Dram Type= 6, Freq= 0, CH_1, rank 0
2417 22:15:42.536689 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2418 22:15:42.536787 ==
2419 22:15:42.539827 [Duty_Offset_Calibration]
2420 22:15:42.539931 B0:1 B1:0 CA:0
2421 22:15:42.540021
2422 22:15:42.543145 [DutyScan_Calibration_Flow] k_type=0
2423 22:15:42.552736
2424 22:15:42.552816 ==CLK 0==
2425 22:15:42.556564 Final CLK duty delay cell = -4
2426 22:15:42.559417 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2427 22:15:42.563385 [-4] MIN Duty = 4907%(X100), DQS PI = 12
2428 22:15:42.566341 [-4] AVG Duty = 4969%(X100)
2429 22:15:42.566425
2430 22:15:42.569723 CH1 CLK Duty spec in!! Max-Min= 124%
2431 22:15:42.573164 [DutyScan_Calibration_Flow] ====Done====
2432 22:15:42.573259
2433 22:15:42.576778 [DutyScan_Calibration_Flow] k_type=1
2434 22:15:42.593095
2435 22:15:42.593198 ==DQS 0 ==
2436 22:15:42.596118 Final DQS duty delay cell = 0
2437 22:15:42.599566 [0] MAX Duty = 5062%(X100), DQS PI = 24
2438 22:15:42.603317 [0] MIN Duty = 4844%(X100), DQS PI = 0
2439 22:15:42.603422 [0] AVG Duty = 4953%(X100)
2440 22:15:42.606391
2441 22:15:42.606473 ==DQS 1 ==
2442 22:15:42.609797 Final DQS duty delay cell = 0
2443 22:15:42.613038 [0] MAX Duty = 5218%(X100), DQS PI = 20
2444 22:15:42.616078 [0] MIN Duty = 4969%(X100), DQS PI = 8
2445 22:15:42.616186 [0] AVG Duty = 5093%(X100)
2446 22:15:42.616278
2447 22:15:42.623051 CH1 DQS 0 Duty spec in!! Max-Min= 218%
2448 22:15:42.623126
2449 22:15:42.626022 CH1 DQS 1 Duty spec in!! Max-Min= 249%
2450 22:15:42.629664 [DutyScan_Calibration_Flow] ====Done====
2451 22:15:42.629762
2452 22:15:42.632824 [DutyScan_Calibration_Flow] k_type=3
2453 22:15:42.649091
2454 22:15:42.649204 ==DQM 0 ==
2455 22:15:42.652540 Final DQM duty delay cell = 0
2456 22:15:42.656239 [0] MAX Duty = 5156%(X100), DQS PI = 4
2457 22:15:42.659307 [0] MIN Duty = 5031%(X100), DQS PI = 0
2458 22:15:42.659382 [0] AVG Duty = 5093%(X100)
2459 22:15:42.659475
2460 22:15:42.662611 ==DQM 1 ==
2461 22:15:42.665971 Final DQM duty delay cell = 0
2462 22:15:42.669233 [0] MAX Duty = 5031%(X100), DQS PI = 16
2463 22:15:42.672604 [0] MIN Duty = 4907%(X100), DQS PI = 36
2464 22:15:42.672702 [0] AVG Duty = 4969%(X100)
2465 22:15:42.675954
2466 22:15:42.679517 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2467 22:15:42.679611
2468 22:15:42.682481 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2469 22:15:42.686393 [DutyScan_Calibration_Flow] ====Done====
2470 22:15:42.686488
2471 22:15:42.689176 [DutyScan_Calibration_Flow] k_type=2
2472 22:15:42.705539
2473 22:15:42.705640 ==DQ 0 ==
2474 22:15:42.708447 Final DQ duty delay cell = -4
2475 22:15:42.712112 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2476 22:15:42.714991 [-4] MIN Duty = 4906%(X100), DQS PI = 46
2477 22:15:42.718616 [-4] AVG Duty = 4984%(X100)
2478 22:15:42.718703
2479 22:15:42.718767 ==DQ 1 ==
2480 22:15:42.722028 Final DQ duty delay cell = 0
2481 22:15:42.724959 [0] MAX Duty = 5125%(X100), DQS PI = 20
2482 22:15:42.728324 [0] MIN Duty = 4969%(X100), DQS PI = 32
2483 22:15:42.728430 [0] AVG Duty = 5047%(X100)
2484 22:15:42.728522
2485 22:15:42.731492 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2486 22:15:42.735172
2487 22:15:42.738768 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2488 22:15:42.741764 [DutyScan_Calibration_Flow] ====Done====
2489 22:15:42.745478 nWR fixed to 30
2490 22:15:42.745602 [ModeRegInit_LP4] CH0 RK0
2491 22:15:42.748483 [ModeRegInit_LP4] CH0 RK1
2492 22:15:42.752006 [ModeRegInit_LP4] CH1 RK0
2493 22:15:42.752109 [ModeRegInit_LP4] CH1 RK1
2494 22:15:42.755221 match AC timing 7
2495 22:15:42.758738 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2496 22:15:42.762063 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2497 22:15:42.768495 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2498 22:15:42.772333 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2499 22:15:42.778605 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2500 22:15:42.778682 ==
2501 22:15:42.781903 Dram Type= 6, Freq= 0, CH_0, rank 0
2502 22:15:42.785755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2503 22:15:42.785854 ==
2504 22:15:42.792007 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2505 22:15:42.795729 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2506 22:15:42.805482 [CA 0] Center 39 (8~70) winsize 63
2507 22:15:42.808585 [CA 1] Center 39 (8~70) winsize 63
2508 22:15:42.812196 [CA 2] Center 35 (5~66) winsize 62
2509 22:15:42.815206 [CA 3] Center 34 (4~65) winsize 62
2510 22:15:42.818821 [CA 4] Center 33 (3~64) winsize 62
2511 22:15:42.822301 [CA 5] Center 32 (3~62) winsize 60
2512 22:15:42.822400
2513 22:15:42.825358 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2514 22:15:42.825460
2515 22:15:42.828807 [CATrainingPosCal] consider 1 rank data
2516 22:15:42.831899 u2DelayCellTimex100 = 270/100 ps
2517 22:15:42.835131 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2518 22:15:42.838733 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2519 22:15:42.845289 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2520 22:15:42.848880 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2521 22:15:42.852001 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2522 22:15:42.855180 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2523 22:15:42.855286
2524 22:15:42.858847 CA PerBit enable=1, Macro0, CA PI delay=32
2525 22:15:42.858956
2526 22:15:42.862068 [CBTSetCACLKResult] CA Dly = 32
2527 22:15:42.862140 CS Dly: 6 (0~37)
2528 22:15:42.862202 ==
2529 22:15:42.865620 Dram Type= 6, Freq= 0, CH_0, rank 1
2530 22:15:42.871928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2531 22:15:42.872027 ==
2532 22:15:42.876020 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2533 22:15:42.882076 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2534 22:15:42.891063 [CA 0] Center 38 (8~69) winsize 62
2535 22:15:42.894320 [CA 1] Center 38 (8~69) winsize 62
2536 22:15:42.897639 [CA 2] Center 35 (5~66) winsize 62
2537 22:15:42.900909 [CA 3] Center 34 (4~65) winsize 62
2538 22:15:42.904774 [CA 4] Center 33 (3~64) winsize 62
2539 22:15:42.907892 [CA 5] Center 32 (3~62) winsize 60
2540 22:15:42.907988
2541 22:15:42.911385 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2542 22:15:42.911456
2543 22:15:42.914209 [CATrainingPosCal] consider 2 rank data
2544 22:15:42.917828 u2DelayCellTimex100 = 270/100 ps
2545 22:15:42.920901 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2546 22:15:42.924476 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2547 22:15:42.931221 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2548 22:15:42.934510 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2549 22:15:42.937803 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2550 22:15:42.941299 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2551 22:15:42.941372
2552 22:15:42.944312 CA PerBit enable=1, Macro0, CA PI delay=32
2553 22:15:42.944385
2554 22:15:42.947912 [CBTSetCACLKResult] CA Dly = 32
2555 22:15:42.948015 CS Dly: 6 (0~38)
2556 22:15:42.948109
2557 22:15:42.951171 ----->DramcWriteLeveling(PI) begin...
2558 22:15:42.954564 ==
2559 22:15:42.954663 Dram Type= 6, Freq= 0, CH_0, rank 0
2560 22:15:42.961226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2561 22:15:42.961305 ==
2562 22:15:42.964775 Write leveling (Byte 0): 35 => 35
2563 22:15:42.967686 Write leveling (Byte 1): 27 => 27
2564 22:15:42.967786 DramcWriteLeveling(PI) end<-----
2565 22:15:42.971294
2566 22:15:42.971367 ==
2567 22:15:42.974397 Dram Type= 6, Freq= 0, CH_0, rank 0
2568 22:15:42.977993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2569 22:15:42.978094 ==
2570 22:15:42.981527 [Gating] SW mode calibration
2571 22:15:42.987986 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2572 22:15:42.991114 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2573 22:15:42.998012 0 15 0 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
2574 22:15:43.001211 0 15 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2575 22:15:43.004397 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2576 22:15:43.011210 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2577 22:15:43.014528 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2578 22:15:43.017718 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2579 22:15:43.024272 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
2580 22:15:43.027444 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 0)
2581 22:15:43.031210 1 0 0 | B1->B0 | 2929 2323 | 0 0 | (0 1) (0 0)
2582 22:15:43.037842 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2583 22:15:43.041277 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2584 22:15:43.044187 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2585 22:15:43.051325 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2586 22:15:43.054315 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2587 22:15:43.057899 1 0 24 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
2588 22:15:43.064493 1 0 28 | B1->B0 | 2e2e 4646 | 1 0 | (0 0) (0 0)
2589 22:15:43.067478 1 1 0 | B1->B0 | 3838 4646 | 1 0 | (0 0) (0 0)
2590 22:15:43.070894 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2591 22:15:43.077365 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2592 22:15:43.081167 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2593 22:15:43.084900 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2594 22:15:43.087708 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2595 22:15:43.094679 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2596 22:15:43.098100 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2597 22:15:43.100878 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2598 22:15:43.108010 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2599 22:15:43.111280 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2600 22:15:43.114656 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2601 22:15:43.121113 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2602 22:15:43.124415 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2603 22:15:43.127856 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2604 22:15:43.134251 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2605 22:15:43.138256 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2606 22:15:43.141239 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 22:15:43.148176 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 22:15:43.151668 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 22:15:43.154572 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 22:15:43.158203 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 22:15:43.164914 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 22:15:43.168157 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2613 22:15:43.171688 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2614 22:15:43.174523 Total UI for P1: 0, mck2ui 16
2615 22:15:43.177948 best dqsien dly found for B0: ( 1, 3, 28)
2616 22:15:43.181265 Total UI for P1: 0, mck2ui 16
2617 22:15:43.184753 best dqsien dly found for B1: ( 1, 3, 30)
2618 22:15:43.187866 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2619 22:15:43.191360 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2620 22:15:43.191467
2621 22:15:43.198146 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2622 22:15:43.201601 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2623 22:15:43.201703 [Gating] SW calibration Done
2624 22:15:43.205023 ==
2625 22:15:43.207936 Dram Type= 6, Freq= 0, CH_0, rank 0
2626 22:15:43.211438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2627 22:15:43.211515 ==
2628 22:15:43.211578 RX Vref Scan: 0
2629 22:15:43.211638
2630 22:15:43.214468 RX Vref 0 -> 0, step: 1
2631 22:15:43.214540
2632 22:15:43.218033 RX Delay -40 -> 252, step: 8
2633 22:15:43.221237 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2634 22:15:43.224577 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2635 22:15:43.228209 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2636 22:15:43.234974 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2637 22:15:43.237829 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2638 22:15:43.241480 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2639 22:15:43.244437 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2640 22:15:43.248241 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2641 22:15:43.254695 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2642 22:15:43.258062 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2643 22:15:43.261479 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2644 22:15:43.264458 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2645 22:15:43.268138 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2646 22:15:43.274550 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2647 22:15:43.278148 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2648 22:15:43.281177 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2649 22:15:43.281250 ==
2650 22:15:43.284625 Dram Type= 6, Freq= 0, CH_0, rank 0
2651 22:15:43.288163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2652 22:15:43.288261 ==
2653 22:15:43.291419 DQS Delay:
2654 22:15:43.291492 DQS0 = 0, DQS1 = 0
2655 22:15:43.294984 DQM Delay:
2656 22:15:43.295081 DQM0 = 121, DQM1 = 113
2657 22:15:43.295172 DQ Delay:
2658 22:15:43.301624 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2659 22:15:43.304950 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2660 22:15:43.308304 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2661 22:15:43.311493 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2662 22:15:43.311595
2663 22:15:43.311683
2664 22:15:43.311746 ==
2665 22:15:43.314687 Dram Type= 6, Freq= 0, CH_0, rank 0
2666 22:15:43.318027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2667 22:15:43.318104 ==
2668 22:15:43.318168
2669 22:15:43.318227
2670 22:15:43.321355 TX Vref Scan disable
2671 22:15:43.324816 == TX Byte 0 ==
2672 22:15:43.328118 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2673 22:15:43.331446 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2674 22:15:43.334696 == TX Byte 1 ==
2675 22:15:43.337952 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2676 22:15:43.341555 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2677 22:15:43.341638 ==
2678 22:15:43.344893 Dram Type= 6, Freq= 0, CH_0, rank 0
2679 22:15:43.348211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2680 22:15:43.351110 ==
2681 22:15:43.361747 TX Vref=22, minBit 3, minWin=24, winSum=409
2682 22:15:43.365474 TX Vref=24, minBit 5, minWin=24, winSum=419
2683 22:15:43.368583 TX Vref=26, minBit 3, minWin=25, winSum=425
2684 22:15:43.372043 TX Vref=28, minBit 0, minWin=26, winSum=424
2685 22:15:43.375139 TX Vref=30, minBit 0, minWin=26, winSum=423
2686 22:15:43.378539 TX Vref=32, minBit 4, minWin=25, winSum=424
2687 22:15:43.385523 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 28
2688 22:15:43.385615
2689 22:15:43.388427 Final TX Range 1 Vref 28
2690 22:15:43.388510
2691 22:15:43.388613 ==
2692 22:15:43.392011 Dram Type= 6, Freq= 0, CH_0, rank 0
2693 22:15:43.395042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2694 22:15:43.395131 ==
2695 22:15:43.395197
2696 22:15:43.398719
2697 22:15:43.398801 TX Vref Scan disable
2698 22:15:43.402013 == TX Byte 0 ==
2699 22:15:43.405020 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2700 22:15:43.408800 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2701 22:15:43.412191 == TX Byte 1 ==
2702 22:15:43.415311 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2703 22:15:43.418809 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2704 22:15:43.418892
2705 22:15:43.421852 [DATLAT]
2706 22:15:43.421934 Freq=1200, CH0 RK0
2707 22:15:43.422000
2708 22:15:43.425517 DATLAT Default: 0xd
2709 22:15:43.425600 0, 0xFFFF, sum = 0
2710 22:15:43.428610 1, 0xFFFF, sum = 0
2711 22:15:43.428693 2, 0xFFFF, sum = 0
2712 22:15:43.432073 3, 0xFFFF, sum = 0
2713 22:15:43.432157 4, 0xFFFF, sum = 0
2714 22:15:43.435001 5, 0xFFFF, sum = 0
2715 22:15:43.435085 6, 0xFFFF, sum = 0
2716 22:15:43.438360 7, 0xFFFF, sum = 0
2717 22:15:43.441728 8, 0xFFFF, sum = 0
2718 22:15:43.441812 9, 0xFFFF, sum = 0
2719 22:15:43.445632 10, 0xFFFF, sum = 0
2720 22:15:43.445716 11, 0xFFFF, sum = 0
2721 22:15:43.448377 12, 0x0, sum = 1
2722 22:15:43.448461 13, 0x0, sum = 2
2723 22:15:43.451810 14, 0x0, sum = 3
2724 22:15:43.451895 15, 0x0, sum = 4
2725 22:15:43.451961 best_step = 13
2726 22:15:43.452024
2727 22:15:43.455341 ==
2728 22:15:43.455424 Dram Type= 6, Freq= 0, CH_0, rank 0
2729 22:15:43.462189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2730 22:15:43.462273 ==
2731 22:15:43.462339 RX Vref Scan: 1
2732 22:15:43.462400
2733 22:15:43.465439 Set Vref Range= 32 -> 127
2734 22:15:43.465528
2735 22:15:43.468875 RX Vref 32 -> 127, step: 1
2736 22:15:43.468957
2737 22:15:43.472133 RX Delay -13 -> 252, step: 4
2738 22:15:43.472215
2739 22:15:43.475647 Set Vref, RX VrefLevel [Byte0]: 32
2740 22:15:43.478635 [Byte1]: 32
2741 22:15:43.478717
2742 22:15:43.482522 Set Vref, RX VrefLevel [Byte0]: 33
2743 22:15:43.485318 [Byte1]: 33
2744 22:15:43.485400
2745 22:15:43.488868 Set Vref, RX VrefLevel [Byte0]: 34
2746 22:15:43.491799 [Byte1]: 34
2747 22:15:43.496419
2748 22:15:43.496502 Set Vref, RX VrefLevel [Byte0]: 35
2749 22:15:43.499389 [Byte1]: 35
2750 22:15:43.504203
2751 22:15:43.504285 Set Vref, RX VrefLevel [Byte0]: 36
2752 22:15:43.507781 [Byte1]: 36
2753 22:15:43.511904
2754 22:15:43.511987 Set Vref, RX VrefLevel [Byte0]: 37
2755 22:15:43.514997 [Byte1]: 37
2756 22:15:43.520087
2757 22:15:43.520169 Set Vref, RX VrefLevel [Byte0]: 38
2758 22:15:43.523318 [Byte1]: 38
2759 22:15:43.527890
2760 22:15:43.527972 Set Vref, RX VrefLevel [Byte0]: 39
2761 22:15:43.530881 [Byte1]: 39
2762 22:15:43.535282
2763 22:15:43.535364 Set Vref, RX VrefLevel [Byte0]: 40
2764 22:15:43.538996 [Byte1]: 40
2765 22:15:43.543228
2766 22:15:43.543310 Set Vref, RX VrefLevel [Byte0]: 41
2767 22:15:43.546652 [Byte1]: 41
2768 22:15:43.551431
2769 22:15:43.551514 Set Vref, RX VrefLevel [Byte0]: 42
2770 22:15:43.554703 [Byte1]: 42
2771 22:15:43.559142
2772 22:15:43.559224 Set Vref, RX VrefLevel [Byte0]: 43
2773 22:15:43.562436 [Byte1]: 43
2774 22:15:43.567137
2775 22:15:43.567219 Set Vref, RX VrefLevel [Byte0]: 44
2776 22:15:43.570645 [Byte1]: 44
2777 22:15:43.574853
2778 22:15:43.574935 Set Vref, RX VrefLevel [Byte0]: 45
2779 22:15:43.578139 [Byte1]: 45
2780 22:15:43.582805
2781 22:15:43.582887 Set Vref, RX VrefLevel [Byte0]: 46
2782 22:15:43.586234 [Byte1]: 46
2783 22:15:43.591001
2784 22:15:43.591084 Set Vref, RX VrefLevel [Byte0]: 47
2785 22:15:43.593903 [Byte1]: 47
2786 22:15:43.598699
2787 22:15:43.598781 Set Vref, RX VrefLevel [Byte0]: 48
2788 22:15:43.601765 [Byte1]: 48
2789 22:15:43.606873
2790 22:15:43.606955 Set Vref, RX VrefLevel [Byte0]: 49
2791 22:15:43.609821 [Byte1]: 49
2792 22:15:43.614387
2793 22:15:43.614469 Set Vref, RX VrefLevel [Byte0]: 50
2794 22:15:43.617707 [Byte1]: 50
2795 22:15:43.622388
2796 22:15:43.622470 Set Vref, RX VrefLevel [Byte0]: 51
2797 22:15:43.625314 [Byte1]: 51
2798 22:15:43.630089
2799 22:15:43.630171 Set Vref, RX VrefLevel [Byte0]: 52
2800 22:15:43.633651 [Byte1]: 52
2801 22:15:43.638140
2802 22:15:43.638222 Set Vref, RX VrefLevel [Byte0]: 53
2803 22:15:43.641169 [Byte1]: 53
2804 22:15:43.646023
2805 22:15:43.646104 Set Vref, RX VrefLevel [Byte0]: 54
2806 22:15:43.649185 [Byte1]: 54
2807 22:15:43.653774
2808 22:15:43.653856 Set Vref, RX VrefLevel [Byte0]: 55
2809 22:15:43.657552 [Byte1]: 55
2810 22:15:43.661821
2811 22:15:43.661903 Set Vref, RX VrefLevel [Byte0]: 56
2812 22:15:43.665049 [Byte1]: 56
2813 22:15:43.669419
2814 22:15:43.669502 Set Vref, RX VrefLevel [Byte0]: 57
2815 22:15:43.673120 [Byte1]: 57
2816 22:15:43.677350
2817 22:15:43.677460 Set Vref, RX VrefLevel [Byte0]: 58
2818 22:15:43.680904 [Byte1]: 58
2819 22:15:43.685207
2820 22:15:43.685289 Set Vref, RX VrefLevel [Byte0]: 59
2821 22:15:43.689076 [Byte1]: 59
2822 22:15:43.693481
2823 22:15:43.693585 Set Vref, RX VrefLevel [Byte0]: 60
2824 22:15:43.696540 [Byte1]: 60
2825 22:15:43.701054
2826 22:15:43.701157 Set Vref, RX VrefLevel [Byte0]: 61
2827 22:15:43.704650 [Byte1]: 61
2828 22:15:43.708907
2829 22:15:43.708989 Set Vref, RX VrefLevel [Byte0]: 62
2830 22:15:43.712346 [Byte1]: 62
2831 22:15:43.717224
2832 22:15:43.717306 Set Vref, RX VrefLevel [Byte0]: 63
2833 22:15:43.720217 [Byte1]: 63
2834 22:15:43.725060
2835 22:15:43.725142 Set Vref, RX VrefLevel [Byte0]: 64
2836 22:15:43.728051 [Byte1]: 64
2837 22:15:43.732689
2838 22:15:43.732771 Set Vref, RX VrefLevel [Byte0]: 65
2839 22:15:43.735932 [Byte1]: 65
2840 22:15:43.740400
2841 22:15:43.740482 Set Vref, RX VrefLevel [Byte0]: 66
2842 22:15:43.743877 [Byte1]: 66
2843 22:15:43.748907
2844 22:15:43.748990 Set Vref, RX VrefLevel [Byte0]: 67
2845 22:15:43.751493 [Byte1]: 67
2846 22:15:43.756612
2847 22:15:43.756694 Set Vref, RX VrefLevel [Byte0]: 68
2848 22:15:43.759599 [Byte1]: 68
2849 22:15:43.764509
2850 22:15:43.764591 Set Vref, RX VrefLevel [Byte0]: 69
2851 22:15:43.767372 [Byte1]: 69
2852 22:15:43.771999
2853 22:15:43.772082 Final RX Vref Byte 0 = 56 to rank0
2854 22:15:43.775323 Final RX Vref Byte 1 = 48 to rank0
2855 22:15:43.778901 Final RX Vref Byte 0 = 56 to rank1
2856 22:15:43.781877 Final RX Vref Byte 1 = 48 to rank1==
2857 22:15:43.785501 Dram Type= 6, Freq= 0, CH_0, rank 0
2858 22:15:43.788990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2859 22:15:43.792121 ==
2860 22:15:43.792204 DQS Delay:
2861 22:15:43.792269 DQS0 = 0, DQS1 = 0
2862 22:15:43.795340 DQM Delay:
2863 22:15:43.795422 DQM0 = 121, DQM1 = 112
2864 22:15:43.798938 DQ Delay:
2865 22:15:43.802209 DQ0 =120, DQ1 =122, DQ2 =120, DQ3 =120
2866 22:15:43.805684 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =126
2867 22:15:43.808832 DQ8 =100, DQ9 =102, DQ10 =112, DQ11 =106
2868 22:15:43.812328 DQ12 =116, DQ13 =116, DQ14 =124, DQ15 =120
2869 22:15:43.812410
2870 22:15:43.812475
2871 22:15:43.818842 [DQSOSCAuto] RK0, (LSB)MR18= 0x1710, (MSB)MR19= 0x404, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
2872 22:15:43.822414 CH0 RK0: MR19=404, MR18=1710
2873 22:15:43.828991 CH0_RK0: MR19=0x404, MR18=0x1710, DQSOSC=401, MR23=63, INC=40, DEC=27
2874 22:15:43.829081
2875 22:15:43.832424 ----->DramcWriteLeveling(PI) begin...
2876 22:15:43.832509 ==
2877 22:15:43.835533 Dram Type= 6, Freq= 0, CH_0, rank 1
2878 22:15:43.839198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2879 22:15:43.839280 ==
2880 22:15:43.842906 Write leveling (Byte 0): 34 => 34
2881 22:15:43.845681 Write leveling (Byte 1): 29 => 29
2882 22:15:43.848999 DramcWriteLeveling(PI) end<-----
2883 22:15:43.849081
2884 22:15:43.849146 ==
2885 22:15:43.852722 Dram Type= 6, Freq= 0, CH_0, rank 1
2886 22:15:43.858845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2887 22:15:43.858928 ==
2888 22:15:43.858994 [Gating] SW mode calibration
2889 22:15:43.869072 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2890 22:15:43.872384 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2891 22:15:43.875731 0 15 0 | B1->B0 | 3232 2e2e | 0 0 | (0 0) (0 0)
2892 22:15:43.882321 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2893 22:15:43.885550 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2894 22:15:43.888994 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2895 22:15:43.895662 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2896 22:15:43.899298 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2897 22:15:43.902588 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2898 22:15:43.909170 0 15 28 | B1->B0 | 2d2d 2c2c | 0 0 | (0 0) (0 0)
2899 22:15:43.912548 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
2900 22:15:43.916111 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2901 22:15:43.922538 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2902 22:15:43.925687 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2903 22:15:43.929260 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2904 22:15:43.935823 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2905 22:15:43.939618 1 0 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
2906 22:15:43.942376 1 0 28 | B1->B0 | 4040 3c3c | 1 1 | (0 0) (0 0)
2907 22:15:43.946041 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2908 22:15:43.952544 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2909 22:15:43.956195 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2910 22:15:43.959093 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2911 22:15:43.965712 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2912 22:15:43.969240 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2913 22:15:43.972388 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2914 22:15:43.979339 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
2915 22:15:43.982355 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 22:15:43.985908 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 22:15:43.992519 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 22:15:43.995838 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 22:15:43.999374 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 22:15:44.005905 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 22:15:44.009543 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 22:15:44.012355 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 22:15:44.019128 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2924 22:15:44.022836 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2925 22:15:44.025974 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 22:15:44.029546 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 22:15:44.036353 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 22:15:44.039795 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 22:15:44.042867 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 22:15:44.049375 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2931 22:15:44.052854 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2932 22:15:44.056001 Total UI for P1: 0, mck2ui 16
2933 22:15:44.059422 best dqsien dly found for B1: ( 1, 3, 28)
2934 22:15:44.063163 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2935 22:15:44.066226 Total UI for P1: 0, mck2ui 16
2936 22:15:44.069459 best dqsien dly found for B0: ( 1, 3, 30)
2937 22:15:44.072896 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2938 22:15:44.076116 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2939 22:15:44.076194
2940 22:15:44.079592 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2941 22:15:44.085952 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2942 22:15:44.086032 [Gating] SW calibration Done
2943 22:15:44.089414 ==
2944 22:15:44.089503 Dram Type= 6, Freq= 0, CH_0, rank 1
2945 22:15:44.096205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2946 22:15:44.096281 ==
2947 22:15:44.096345 RX Vref Scan: 0
2948 22:15:44.096410
2949 22:15:44.099728 RX Vref 0 -> 0, step: 1
2950 22:15:44.099797
2951 22:15:44.102637 RX Delay -40 -> 252, step: 8
2952 22:15:44.106317 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2953 22:15:44.109387 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2954 22:15:44.112805 iDelay=200, Bit 2, Center 123 (56 ~ 191) 136
2955 22:15:44.119893 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2956 22:15:44.122710 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2957 22:15:44.126195 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2958 22:15:44.129828 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2959 22:15:44.132937 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2960 22:15:44.139581 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2961 22:15:44.143005 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2962 22:15:44.146741 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2963 22:15:44.149472 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2964 22:15:44.153147 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2965 22:15:44.159568 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
2966 22:15:44.163154 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2967 22:15:44.166242 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2968 22:15:44.166325 ==
2969 22:15:44.170003 Dram Type= 6, Freq= 0, CH_0, rank 1
2970 22:15:44.172696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2971 22:15:44.172779 ==
2972 22:15:44.176306 DQS Delay:
2973 22:15:44.176389 DQS0 = 0, DQS1 = 0
2974 22:15:44.179590 DQM Delay:
2975 22:15:44.179672 DQM0 = 122, DQM1 = 112
2976 22:15:44.179737 DQ Delay:
2977 22:15:44.182743 DQ0 =119, DQ1 =119, DQ2 =123, DQ3 =119
2978 22:15:44.189405 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2979 22:15:44.192690 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
2980 22:15:44.196270 DQ12 =115, DQ13 =119, DQ14 =123, DQ15 =123
2981 22:15:44.196352
2982 22:15:44.196417
2983 22:15:44.196478 ==
2984 22:15:44.199802 Dram Type= 6, Freq= 0, CH_0, rank 1
2985 22:15:44.202670 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2986 22:15:44.202753 ==
2987 22:15:44.202866
2988 22:15:44.202958
2989 22:15:44.206513 TX Vref Scan disable
2990 22:15:44.206596 == TX Byte 0 ==
2991 22:15:44.212918 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2992 22:15:44.216535 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2993 22:15:44.219492 == TX Byte 1 ==
2994 22:15:44.222990 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2995 22:15:44.226597 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2996 22:15:44.226680 ==
2997 22:15:44.230035 Dram Type= 6, Freq= 0, CH_0, rank 1
2998 22:15:44.232956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2999 22:15:44.233039 ==
3000 22:15:44.246489 TX Vref=22, minBit 2, minWin=25, winSum=420
3001 22:15:44.249912 TX Vref=24, minBit 3, minWin=24, winSum=426
3002 22:15:44.253265 TX Vref=26, minBit 1, minWin=26, winSum=428
3003 22:15:44.256869 TX Vref=28, minBit 1, minWin=26, winSum=427
3004 22:15:44.259998 TX Vref=30, minBit 1, minWin=26, winSum=430
3005 22:15:44.263056 TX Vref=32, minBit 2, minWin=26, winSum=429
3006 22:15:44.270114 [TxChooseVref] Worse bit 1, Min win 26, Win sum 430, Final Vref 30
3007 22:15:44.270199
3008 22:15:44.273394 Final TX Range 1 Vref 30
3009 22:15:44.273477
3010 22:15:44.273585 ==
3011 22:15:44.276259 Dram Type= 6, Freq= 0, CH_0, rank 1
3012 22:15:44.279853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3013 22:15:44.279936 ==
3014 22:15:44.280001
3015 22:15:44.280060
3016 22:15:44.283296 TX Vref Scan disable
3017 22:15:44.286653 == TX Byte 0 ==
3018 22:15:44.289718 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
3019 22:15:44.293054 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
3020 22:15:44.296684 == TX Byte 1 ==
3021 22:15:44.300060 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3022 22:15:44.303335 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3023 22:15:44.303419
3024 22:15:44.306622 [DATLAT]
3025 22:15:44.306730 Freq=1200, CH0 RK1
3026 22:15:44.306814
3027 22:15:44.310376 DATLAT Default: 0xd
3028 22:15:44.310483 0, 0xFFFF, sum = 0
3029 22:15:44.313050 1, 0xFFFF, sum = 0
3030 22:15:44.313135 2, 0xFFFF, sum = 0
3031 22:15:44.316493 3, 0xFFFF, sum = 0
3032 22:15:44.316597 4, 0xFFFF, sum = 0
3033 22:15:44.319572 5, 0xFFFF, sum = 0
3034 22:15:44.319657 6, 0xFFFF, sum = 0
3035 22:15:44.323067 7, 0xFFFF, sum = 0
3036 22:15:44.323153 8, 0xFFFF, sum = 0
3037 22:15:44.326481 9, 0xFFFF, sum = 0
3038 22:15:44.329664 10, 0xFFFF, sum = 0
3039 22:15:44.329774 11, 0xFFFF, sum = 0
3040 22:15:44.333242 12, 0x0, sum = 1
3041 22:15:44.333352 13, 0x0, sum = 2
3042 22:15:44.333457 14, 0x0, sum = 3
3043 22:15:44.336684 15, 0x0, sum = 4
3044 22:15:44.336770 best_step = 13
3045 22:15:44.336853
3046 22:15:44.339829 ==
3047 22:15:44.339919 Dram Type= 6, Freq= 0, CH_0, rank 1
3048 22:15:44.346807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3049 22:15:44.346892 ==
3050 22:15:44.346975 RX Vref Scan: 0
3051 22:15:44.347054
3052 22:15:44.349647 RX Vref 0 -> 0, step: 1
3053 22:15:44.349731
3054 22:15:44.353086 RX Delay -13 -> 252, step: 4
3055 22:15:44.356524 iDelay=195, Bit 0, Center 120 (51 ~ 190) 140
3056 22:15:44.359860 iDelay=195, Bit 1, Center 122 (59 ~ 186) 128
3057 22:15:44.366781 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3058 22:15:44.369729 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3059 22:15:44.373525 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3060 22:15:44.376655 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3061 22:15:44.379973 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3062 22:15:44.386641 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3063 22:15:44.390251 iDelay=195, Bit 8, Center 100 (35 ~ 166) 132
3064 22:15:44.393154 iDelay=195, Bit 9, Center 98 (31 ~ 166) 136
3065 22:15:44.396587 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3066 22:15:44.399993 iDelay=195, Bit 11, Center 102 (39 ~ 166) 128
3067 22:15:44.406758 iDelay=195, Bit 12, Center 114 (51 ~ 178) 128
3068 22:15:44.409905 iDelay=195, Bit 13, Center 116 (55 ~ 178) 124
3069 22:15:44.413343 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3070 22:15:44.416867 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3071 22:15:44.416949 ==
3072 22:15:44.420415 Dram Type= 6, Freq= 0, CH_0, rank 1
3073 22:15:44.423433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3074 22:15:44.426940 ==
3075 22:15:44.427022 DQS Delay:
3076 22:15:44.427086 DQS0 = 0, DQS1 = 0
3077 22:15:44.430529 DQM Delay:
3078 22:15:44.430610 DQM0 = 121, DQM1 = 110
3079 22:15:44.433465 DQ Delay:
3080 22:15:44.437028 DQ0 =120, DQ1 =122, DQ2 =118, DQ3 =118
3081 22:15:44.440021 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =126
3082 22:15:44.443500 DQ8 =100, DQ9 =98, DQ10 =110, DQ11 =102
3083 22:15:44.447141 DQ12 =114, DQ13 =116, DQ14 =122, DQ15 =120
3084 22:15:44.447223
3085 22:15:44.447289
3086 22:15:44.453828 [DQSOSCAuto] RK1, (LSB)MR18= 0x10f1, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 403 ps
3087 22:15:44.456697 CH0 RK1: MR19=403, MR18=10F1
3088 22:15:44.463561 CH0_RK1: MR19=0x403, MR18=0x10F1, DQSOSC=403, MR23=63, INC=40, DEC=26
3089 22:15:44.466800 [RxdqsGatingPostProcess] freq 1200
3090 22:15:44.473650 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3091 22:15:44.477186 best DQS0 dly(2T, 0.5T) = (0, 11)
3092 22:15:44.477269 best DQS1 dly(2T, 0.5T) = (0, 11)
3093 22:15:44.480280 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3094 22:15:44.483198 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3095 22:15:44.486904 best DQS0 dly(2T, 0.5T) = (0, 11)
3096 22:15:44.489963 best DQS1 dly(2T, 0.5T) = (0, 11)
3097 22:15:44.493601 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3098 22:15:44.496550 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3099 22:15:44.500105 Pre-setting of DQS Precalculation
3100 22:15:44.507250 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3101 22:15:44.507358 ==
3102 22:15:44.510085 Dram Type= 6, Freq= 0, CH_1, rank 0
3103 22:15:44.513742 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3104 22:15:44.513824 ==
3105 22:15:44.517062 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3106 22:15:44.523682 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3107 22:15:44.532978 [CA 0] Center 37 (7~68) winsize 62
3108 22:15:44.536242 [CA 1] Center 37 (7~68) winsize 62
3109 22:15:44.539424 [CA 2] Center 35 (5~65) winsize 61
3110 22:15:44.543114 [CA 3] Center 34 (4~64) winsize 61
3111 22:15:44.546028 [CA 4] Center 34 (4~64) winsize 61
3112 22:15:44.549270 [CA 5] Center 33 (3~63) winsize 61
3113 22:15:44.549382
3114 22:15:44.552879 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3115 22:15:44.552961
3116 22:15:44.556497 [CATrainingPosCal] consider 1 rank data
3117 22:15:44.559283 u2DelayCellTimex100 = 270/100 ps
3118 22:15:44.562928 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3119 22:15:44.566326 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3120 22:15:44.572687 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3121 22:15:44.576168 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3122 22:15:44.579548 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3123 22:15:44.583256 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3124 22:15:44.583339
3125 22:15:44.586252 CA PerBit enable=1, Macro0, CA PI delay=33
3126 22:15:44.586334
3127 22:15:44.589790 [CBTSetCACLKResult] CA Dly = 33
3128 22:15:44.589872 CS Dly: 7 (0~38)
3129 22:15:44.589938 ==
3130 22:15:44.592881 Dram Type= 6, Freq= 0, CH_1, rank 1
3131 22:15:44.600174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3132 22:15:44.600257 ==
3133 22:15:44.603091 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3134 22:15:44.609617 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3135 22:15:44.618526 [CA 0] Center 37 (7~68) winsize 62
3136 22:15:44.621929 [CA 1] Center 38 (8~68) winsize 61
3137 22:15:44.625140 [CA 2] Center 35 (5~65) winsize 61
3138 22:15:44.628530 [CA 3] Center 34 (4~65) winsize 62
3139 22:15:44.632106 [CA 4] Center 35 (5~65) winsize 61
3140 22:15:44.634910 [CA 5] Center 34 (4~64) winsize 61
3141 22:15:44.634987
3142 22:15:44.638223 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3143 22:15:44.638301
3144 22:15:44.642145 [CATrainingPosCal] consider 2 rank data
3145 22:15:44.645770 u2DelayCellTimex100 = 270/100 ps
3146 22:15:44.648944 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3147 22:15:44.652223 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3148 22:15:44.655015 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3149 22:15:44.662122 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3150 22:15:44.665607 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3151 22:15:44.668559 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3152 22:15:44.668636
3153 22:15:44.672184 CA PerBit enable=1, Macro0, CA PI delay=33
3154 22:15:44.672262
3155 22:15:44.675237 [CBTSetCACLKResult] CA Dly = 33
3156 22:15:44.675310 CS Dly: 8 (0~41)
3157 22:15:44.675372
3158 22:15:44.678553 ----->DramcWriteLeveling(PI) begin...
3159 22:15:44.681908 ==
3160 22:15:44.681985 Dram Type= 6, Freq= 0, CH_1, rank 0
3161 22:15:44.688569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3162 22:15:44.688652 ==
3163 22:15:44.692343 Write leveling (Byte 0): 25 => 25
3164 22:15:44.695263 Write leveling (Byte 1): 27 => 27
3165 22:15:44.695334 DramcWriteLeveling(PI) end<-----
3166 22:15:44.698809
3167 22:15:44.698882 ==
3168 22:15:44.701767 Dram Type= 6, Freq= 0, CH_1, rank 0
3169 22:15:44.705022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3170 22:15:44.705089 ==
3171 22:15:44.708455 [Gating] SW mode calibration
3172 22:15:44.715872 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3173 22:15:44.718769 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3174 22:15:44.725738 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3175 22:15:44.729338 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3176 22:15:44.732525 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3177 22:15:44.738700 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3178 22:15:44.742221 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3179 22:15:44.745622 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3180 22:15:44.752078 0 15 24 | B1->B0 | 3232 2d2d | 0 0 | (0 1) (0 1)
3181 22:15:44.755952 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3182 22:15:44.758960 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3183 22:15:44.762377 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3184 22:15:44.768924 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3185 22:15:44.772615 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3186 22:15:44.775634 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3187 22:15:44.782681 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3188 22:15:44.785884 1 0 24 | B1->B0 | 3434 4040 | 0 1 | (0 0) (0 0)
3189 22:15:44.789415 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3190 22:15:44.795939 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3191 22:15:44.798938 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3192 22:15:44.802512 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3193 22:15:44.809087 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3194 22:15:44.812291 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3195 22:15:44.815720 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3196 22:15:44.822618 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3197 22:15:44.825554 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3198 22:15:44.829047 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3199 22:15:44.835594 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3200 22:15:44.839350 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3201 22:15:44.842625 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 22:15:44.845839 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 22:15:44.852240 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 22:15:44.855578 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3205 22:15:44.859136 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 22:15:44.866068 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 22:15:44.869185 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 22:15:44.872748 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 22:15:44.879350 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 22:15:44.882879 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 22:15:44.886319 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 22:15:44.892737 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3213 22:15:44.896345 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3214 22:15:44.899169 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3215 22:15:44.902743 Total UI for P1: 0, mck2ui 16
3216 22:15:44.905864 best dqsien dly found for B0: ( 1, 3, 26)
3217 22:15:44.909287 Total UI for P1: 0, mck2ui 16
3218 22:15:44.912895 best dqsien dly found for B1: ( 1, 3, 26)
3219 22:15:44.916063 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3220 22:15:44.919630 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3221 22:15:44.919712
3222 22:15:44.922451 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3223 22:15:44.929023 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3224 22:15:44.929106 [Gating] SW calibration Done
3225 22:15:44.929172 ==
3226 22:15:44.932588 Dram Type= 6, Freq= 0, CH_1, rank 0
3227 22:15:44.939347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3228 22:15:44.939430 ==
3229 22:15:44.939496 RX Vref Scan: 0
3230 22:15:44.939556
3231 22:15:44.942529 RX Vref 0 -> 0, step: 1
3232 22:15:44.942611
3233 22:15:44.946039 RX Delay -40 -> 252, step: 8
3234 22:15:44.949212 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3235 22:15:44.952467 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3236 22:15:44.956035 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3237 22:15:44.962784 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3238 22:15:44.966710 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3239 22:15:44.969499 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3240 22:15:44.972482 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3241 22:15:44.976017 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3242 22:15:44.979480 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3243 22:15:44.986110 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3244 22:15:44.989393 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3245 22:15:44.993241 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3246 22:15:44.996050 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3247 22:15:44.999696 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3248 22:15:45.006586 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3249 22:15:45.009404 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3250 22:15:45.009489 ==
3251 22:15:45.012924 Dram Type= 6, Freq= 0, CH_1, rank 0
3252 22:15:45.016120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3253 22:15:45.016203 ==
3254 22:15:45.019876 DQS Delay:
3255 22:15:45.019958 DQS0 = 0, DQS1 = 0
3256 22:15:45.020024 DQM Delay:
3257 22:15:45.022722 DQM0 = 120, DQM1 = 116
3258 22:15:45.022804 DQ Delay:
3259 22:15:45.026290 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3260 22:15:45.029777 DQ4 =119, DQ5 =127, DQ6 =131, DQ7 =123
3261 22:15:45.032802 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =111
3262 22:15:45.039358 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3263 22:15:45.039440
3264 22:15:45.039505
3265 22:15:45.039567 ==
3266 22:15:45.043026 Dram Type= 6, Freq= 0, CH_1, rank 0
3267 22:15:45.046339 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3268 22:15:45.046421 ==
3269 22:15:45.046487
3270 22:15:45.046556
3271 22:15:45.049771 TX Vref Scan disable
3272 22:15:45.049852 == TX Byte 0 ==
3273 22:15:45.056054 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3274 22:15:45.059760 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3275 22:15:45.059842 == TX Byte 1 ==
3276 22:15:45.066079 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3277 22:15:45.069415 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3278 22:15:45.069519 ==
3279 22:15:45.073004 Dram Type= 6, Freq= 0, CH_1, rank 0
3280 22:15:45.076638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3281 22:15:45.076720 ==
3282 22:15:45.089025 TX Vref=22, minBit 9, minWin=24, winSum=411
3283 22:15:45.091932 TX Vref=24, minBit 9, minWin=24, winSum=418
3284 22:15:45.095397 TX Vref=26, minBit 9, minWin=25, winSum=424
3285 22:15:45.099023 TX Vref=28, minBit 2, minWin=26, winSum=429
3286 22:15:45.102375 TX Vref=30, minBit 2, minWin=26, winSum=429
3287 22:15:45.105442 TX Vref=32, minBit 10, minWin=26, winSum=427
3288 22:15:45.112428 [TxChooseVref] Worse bit 2, Min win 26, Win sum 429, Final Vref 28
3289 22:15:45.112512
3290 22:15:45.115768 Final TX Range 1 Vref 28
3291 22:15:45.115849
3292 22:15:45.115914 ==
3293 22:15:45.119234 Dram Type= 6, Freq= 0, CH_1, rank 0
3294 22:15:45.122317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3295 22:15:45.122399 ==
3296 22:15:45.122465
3297 22:15:45.122524
3298 22:15:45.125760 TX Vref Scan disable
3299 22:15:45.129089 == TX Byte 0 ==
3300 22:15:45.132005 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3301 22:15:45.135664 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3302 22:15:45.138735 == TX Byte 1 ==
3303 22:15:45.142329 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3304 22:15:45.145987 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3305 22:15:45.146069
3306 22:15:45.148812 [DATLAT]
3307 22:15:45.148893 Freq=1200, CH1 RK0
3308 22:15:45.148957
3309 22:15:45.152138 DATLAT Default: 0xd
3310 22:15:45.152219 0, 0xFFFF, sum = 0
3311 22:15:45.155393 1, 0xFFFF, sum = 0
3312 22:15:45.155476 2, 0xFFFF, sum = 0
3313 22:15:45.158821 3, 0xFFFF, sum = 0
3314 22:15:45.158904 4, 0xFFFF, sum = 0
3315 22:15:45.162221 5, 0xFFFF, sum = 0
3316 22:15:45.162329 6, 0xFFFF, sum = 0
3317 22:15:45.165454 7, 0xFFFF, sum = 0
3318 22:15:45.165574 8, 0xFFFF, sum = 0
3319 22:15:45.169197 9, 0xFFFF, sum = 0
3320 22:15:45.169279 10, 0xFFFF, sum = 0
3321 22:15:45.172116 11, 0xFFFF, sum = 0
3322 22:15:45.172199 12, 0x0, sum = 1
3323 22:15:45.175653 13, 0x0, sum = 2
3324 22:15:45.175736 14, 0x0, sum = 3
3325 22:15:45.178945 15, 0x0, sum = 4
3326 22:15:45.179027 best_step = 13
3327 22:15:45.179091
3328 22:15:45.179150 ==
3329 22:15:45.182363 Dram Type= 6, Freq= 0, CH_1, rank 0
3330 22:15:45.188835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3331 22:15:45.188917 ==
3332 22:15:45.188983 RX Vref Scan: 1
3333 22:15:45.189042
3334 22:15:45.192187 Set Vref Range= 32 -> 127
3335 22:15:45.192268
3336 22:15:45.195447 RX Vref 32 -> 127, step: 1
3337 22:15:45.195528
3338 22:15:45.195593 RX Delay -5 -> 252, step: 4
3339 22:15:45.198913
3340 22:15:45.198993 Set Vref, RX VrefLevel [Byte0]: 32
3341 22:15:45.202337 [Byte1]: 32
3342 22:15:45.207197
3343 22:15:45.207278 Set Vref, RX VrefLevel [Byte0]: 33
3344 22:15:45.210222 [Byte1]: 33
3345 22:15:45.215023
3346 22:15:45.215104 Set Vref, RX VrefLevel [Byte0]: 34
3347 22:15:45.217820 [Byte1]: 34
3348 22:15:45.222499
3349 22:15:45.222581 Set Vref, RX VrefLevel [Byte0]: 35
3350 22:15:45.225682 [Byte1]: 35
3351 22:15:45.230382
3352 22:15:45.230462 Set Vref, RX VrefLevel [Byte0]: 36
3353 22:15:45.233951 [Byte1]: 36
3354 22:15:45.238149
3355 22:15:45.238231 Set Vref, RX VrefLevel [Byte0]: 37
3356 22:15:45.241730 [Byte1]: 37
3357 22:15:45.245847
3358 22:15:45.245928 Set Vref, RX VrefLevel [Byte0]: 38
3359 22:15:45.249787 [Byte1]: 38
3360 22:15:45.253978
3361 22:15:45.254058 Set Vref, RX VrefLevel [Byte0]: 39
3362 22:15:45.256983 [Byte1]: 39
3363 22:15:45.261570
3364 22:15:45.261663 Set Vref, RX VrefLevel [Byte0]: 40
3365 22:15:45.265111 [Byte1]: 40
3366 22:15:45.269586
3367 22:15:45.269665 Set Vref, RX VrefLevel [Byte0]: 41
3368 22:15:45.273243 [Byte1]: 41
3369 22:15:45.277448
3370 22:15:45.277582 Set Vref, RX VrefLevel [Byte0]: 42
3371 22:15:45.280893 [Byte1]: 42
3372 22:15:45.285791
3373 22:15:45.285870 Set Vref, RX VrefLevel [Byte0]: 43
3374 22:15:45.288760 [Byte1]: 43
3375 22:15:45.293097
3376 22:15:45.293176 Set Vref, RX VrefLevel [Byte0]: 44
3377 22:15:45.296820 [Byte1]: 44
3378 22:15:45.301011
3379 22:15:45.301090 Set Vref, RX VrefLevel [Byte0]: 45
3380 22:15:45.304371 [Byte1]: 45
3381 22:15:45.308960
3382 22:15:45.309039 Set Vref, RX VrefLevel [Byte0]: 46
3383 22:15:45.312068 [Byte1]: 46
3384 22:15:45.316945
3385 22:15:45.317024 Set Vref, RX VrefLevel [Byte0]: 47
3386 22:15:45.319918 [Byte1]: 47
3387 22:15:45.324506
3388 22:15:45.324585 Set Vref, RX VrefLevel [Byte0]: 48
3389 22:15:45.327826 [Byte1]: 48
3390 22:15:45.332459
3391 22:15:45.332538 Set Vref, RX VrefLevel [Byte0]: 49
3392 22:15:45.336101 [Byte1]: 49
3393 22:15:45.340192
3394 22:15:45.340271 Set Vref, RX VrefLevel [Byte0]: 50
3395 22:15:45.343836 [Byte1]: 50
3396 22:15:45.348271
3397 22:15:45.348350 Set Vref, RX VrefLevel [Byte0]: 51
3398 22:15:45.351315 [Byte1]: 51
3399 22:15:45.355967
3400 22:15:45.356046 Set Vref, RX VrefLevel [Byte0]: 52
3401 22:15:45.359461 [Byte1]: 52
3402 22:15:45.364078
3403 22:15:45.364158 Set Vref, RX VrefLevel [Byte0]: 53
3404 22:15:45.367623 [Byte1]: 53
3405 22:15:45.371551
3406 22:15:45.371634 Set Vref, RX VrefLevel [Byte0]: 54
3407 22:15:45.374907 [Byte1]: 54
3408 22:15:45.379445
3409 22:15:45.379524 Set Vref, RX VrefLevel [Byte0]: 55
3410 22:15:45.382760 [Byte1]: 55
3411 22:15:45.387227
3412 22:15:45.387306 Set Vref, RX VrefLevel [Byte0]: 56
3413 22:15:45.390774 [Byte1]: 56
3414 22:15:45.395485
3415 22:15:45.395568 Set Vref, RX VrefLevel [Byte0]: 57
3416 22:15:45.398862 [Byte1]: 57
3417 22:15:45.403226
3418 22:15:45.403305 Set Vref, RX VrefLevel [Byte0]: 58
3419 22:15:45.406505 [Byte1]: 58
3420 22:15:45.410991
3421 22:15:45.411071 Set Vref, RX VrefLevel [Byte0]: 59
3422 22:15:45.414449 [Byte1]: 59
3423 22:15:45.418682
3424 22:15:45.418763 Set Vref, RX VrefLevel [Byte0]: 60
3425 22:15:45.422399 [Byte1]: 60
3426 22:15:45.427005
3427 22:15:45.427086 Set Vref, RX VrefLevel [Byte0]: 61
3428 22:15:45.429971 [Byte1]: 61
3429 22:15:45.434190
3430 22:15:45.434271 Set Vref, RX VrefLevel [Byte0]: 62
3431 22:15:45.437804 [Byte1]: 62
3432 22:15:45.442186
3433 22:15:45.442268 Set Vref, RX VrefLevel [Byte0]: 63
3434 22:15:45.445449 [Byte1]: 63
3435 22:15:45.450252
3436 22:15:45.450333 Set Vref, RX VrefLevel [Byte0]: 64
3437 22:15:45.453245 [Byte1]: 64
3438 22:15:45.458234
3439 22:15:45.458317 Set Vref, RX VrefLevel [Byte0]: 65
3440 22:15:45.461202 [Byte1]: 65
3441 22:15:45.465823
3442 22:15:45.465904 Set Vref, RX VrefLevel [Byte0]: 66
3443 22:15:45.469313 [Byte1]: 66
3444 22:15:45.474011
3445 22:15:45.474095 Set Vref, RX VrefLevel [Byte0]: 67
3446 22:15:45.476839 [Byte1]: 67
3447 22:15:45.481742
3448 22:15:45.481828 Set Vref, RX VrefLevel [Byte0]: 68
3449 22:15:45.484997 [Byte1]: 68
3450 22:15:45.489415
3451 22:15:45.489497 Set Vref, RX VrefLevel [Byte0]: 69
3452 22:15:45.492917 [Byte1]: 69
3453 22:15:45.497495
3454 22:15:45.497616 Final RX Vref Byte 0 = 55 to rank0
3455 22:15:45.500367 Final RX Vref Byte 1 = 54 to rank0
3456 22:15:45.504168 Final RX Vref Byte 0 = 55 to rank1
3457 22:15:45.506999 Final RX Vref Byte 1 = 54 to rank1==
3458 22:15:45.510469 Dram Type= 6, Freq= 0, CH_1, rank 0
3459 22:15:45.517029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3460 22:15:45.517141 ==
3461 22:15:45.517207 DQS Delay:
3462 22:15:45.517267 DQS0 = 0, DQS1 = 0
3463 22:15:45.520507 DQM Delay:
3464 22:15:45.520590 DQM0 = 120, DQM1 = 117
3465 22:15:45.524221 DQ Delay:
3466 22:15:45.527059 DQ0 =124, DQ1 =114, DQ2 =110, DQ3 =118
3467 22:15:45.530789 DQ4 =118, DQ5 =128, DQ6 =128, DQ7 =120
3468 22:15:45.533755 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =112
3469 22:15:45.537436 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3470 22:15:45.537526
3471 22:15:45.537607
3472 22:15:45.544383 [DQSOSCAuto] RK0, (LSB)MR18= 0x316, (MSB)MR19= 0x404, tDQSOscB0 = 401 ps tDQSOscB1 = 408 ps
3473 22:15:45.547864 CH1 RK0: MR19=404, MR18=316
3474 22:15:45.553979 CH1_RK0: MR19=0x404, MR18=0x316, DQSOSC=401, MR23=63, INC=40, DEC=27
3475 22:15:45.554065
3476 22:15:45.557566 ----->DramcWriteLeveling(PI) begin...
3477 22:15:45.557650 ==
3478 22:15:45.560659 Dram Type= 6, Freq= 0, CH_1, rank 1
3479 22:15:45.564227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3480 22:15:45.564311 ==
3481 22:15:45.567915 Write leveling (Byte 0): 26 => 26
3482 22:15:45.570781 Write leveling (Byte 1): 28 => 28
3483 22:15:45.574346 DramcWriteLeveling(PI) end<-----
3484 22:15:45.574429
3485 22:15:45.574495 ==
3486 22:15:45.577548 Dram Type= 6, Freq= 0, CH_1, rank 1
3487 22:15:45.581387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3488 22:15:45.584373 ==
3489 22:15:45.584480 [Gating] SW mode calibration
3490 22:15:45.591254 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3491 22:15:45.597450 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3492 22:15:45.601125 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3493 22:15:45.607626 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3494 22:15:45.611330 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3495 22:15:45.614723 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3496 22:15:45.621044 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3497 22:15:45.624269 0 15 20 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
3498 22:15:45.628269 0 15 24 | B1->B0 | 2828 3232 | 0 1 | (1 0) (1 0)
3499 22:15:45.634168 0 15 28 | B1->B0 | 2323 2626 | 0 0 | (0 0) (1 0)
3500 22:15:45.637328 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3501 22:15:45.641069 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3502 22:15:45.647443 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3503 22:15:45.651091 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3504 22:15:45.654280 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3505 22:15:45.657623 1 0 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3506 22:15:45.664556 1 0 24 | B1->B0 | 4545 2e2e | 0 0 | (0 0) (0 0)
3507 22:15:45.668114 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3508 22:15:45.671059 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3509 22:15:45.677388 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3510 22:15:45.681011 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3511 22:15:45.684176 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3512 22:15:45.691154 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3513 22:15:45.694531 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3514 22:15:45.697624 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3515 22:15:45.704441 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3516 22:15:45.707896 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 22:15:45.710978 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 22:15:45.717810 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 22:15:45.720554 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 22:15:45.724118 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 22:15:45.730695 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 22:15:45.734159 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 22:15:45.737212 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 22:15:45.743914 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 22:15:45.747545 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 22:15:45.750660 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 22:15:45.757156 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 22:15:45.760683 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 22:15:45.763700 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3530 22:15:45.770199 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3531 22:15:45.773746 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3532 22:15:45.777239 Total UI for P1: 0, mck2ui 16
3533 22:15:45.780873 best dqsien dly found for B1: ( 1, 3, 22)
3534 22:15:45.783753 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3535 22:15:45.787145 Total UI for P1: 0, mck2ui 16
3536 22:15:45.790255 best dqsien dly found for B0: ( 1, 3, 28)
3537 22:15:45.793667 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3538 22:15:45.797040 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3539 22:15:45.797123
3540 22:15:45.800409 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3541 22:15:45.807441 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3542 22:15:45.807524 [Gating] SW calibration Done
3543 22:15:45.807590 ==
3544 22:15:45.810816 Dram Type= 6, Freq= 0, CH_1, rank 1
3545 22:15:45.817109 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3546 22:15:45.817192 ==
3547 22:15:45.817258 RX Vref Scan: 0
3548 22:15:45.817318
3549 22:15:45.820639 RX Vref 0 -> 0, step: 1
3550 22:15:45.820721
3551 22:15:45.823959 RX Delay -40 -> 252, step: 8
3552 22:15:45.827193 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3553 22:15:45.830962 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3554 22:15:45.833878 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3555 22:15:45.836947 iDelay=200, Bit 3, Center 119 (56 ~ 183) 128
3556 22:15:45.843835 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3557 22:15:45.847265 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3558 22:15:45.850478 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3559 22:15:45.853542 iDelay=200, Bit 7, Center 123 (56 ~ 191) 136
3560 22:15:45.856876 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3561 22:15:45.863813 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3562 22:15:45.867407 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3563 22:15:45.870361 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3564 22:15:45.873676 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3565 22:15:45.877392 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3566 22:15:45.883794 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3567 22:15:45.887166 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3568 22:15:45.887249 ==
3569 22:15:45.890552 Dram Type= 6, Freq= 0, CH_1, rank 1
3570 22:15:45.893808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3571 22:15:45.893891 ==
3572 22:15:45.897373 DQS Delay:
3573 22:15:45.897455 DQS0 = 0, DQS1 = 0
3574 22:15:45.897542 DQM Delay:
3575 22:15:45.900439 DQM0 = 121, DQM1 = 117
3576 22:15:45.900546 DQ Delay:
3577 22:15:45.903451 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3578 22:15:45.906968 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =123
3579 22:15:45.913512 DQ8 =103, DQ9 =107, DQ10 =115, DQ11 =115
3580 22:15:45.916777 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3581 22:15:45.916860
3582 22:15:45.916926
3583 22:15:45.916986 ==
3584 22:15:45.920119 Dram Type= 6, Freq= 0, CH_1, rank 1
3585 22:15:45.923463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3586 22:15:45.923546 ==
3587 22:15:45.923612
3588 22:15:45.923685
3589 22:15:45.927014 TX Vref Scan disable
3590 22:15:45.930152 == TX Byte 0 ==
3591 22:15:45.933408 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3592 22:15:45.936612 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3593 22:15:45.940350 == TX Byte 1 ==
3594 22:15:45.943905 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3595 22:15:45.946732 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3596 22:15:45.946815 ==
3597 22:15:45.950111 Dram Type= 6, Freq= 0, CH_1, rank 1
3598 22:15:45.953601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3599 22:15:45.953720 ==
3600 22:15:45.966458 TX Vref=22, minBit 9, minWin=25, winSum=420
3601 22:15:45.970150 TX Vref=24, minBit 0, minWin=26, winSum=425
3602 22:15:45.973108 TX Vref=26, minBit 8, minWin=26, winSum=429
3603 22:15:45.976762 TX Vref=28, minBit 2, minWin=26, winSum=431
3604 22:15:45.979900 TX Vref=30, minBit 6, minWin=26, winSum=431
3605 22:15:45.983003 TX Vref=32, minBit 9, minWin=26, winSum=430
3606 22:15:45.990019 [TxChooseVref] Worse bit 2, Min win 26, Win sum 431, Final Vref 28
3607 22:15:45.990117
3608 22:15:45.992917 Final TX Range 1 Vref 28
3609 22:15:45.992999
3610 22:15:45.993064 ==
3611 22:15:45.996611 Dram Type= 6, Freq= 0, CH_1, rank 1
3612 22:15:45.999608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3613 22:15:45.999692 ==
3614 22:15:45.999758
3615 22:15:46.003319
3616 22:15:46.003400 TX Vref Scan disable
3617 22:15:46.006489 == TX Byte 0 ==
3618 22:15:46.009790 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3619 22:15:46.012954 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3620 22:15:46.016402 == TX Byte 1 ==
3621 22:15:46.019372 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3622 22:15:46.022920 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3623 22:15:46.023003
3624 22:15:46.026270 [DATLAT]
3625 22:15:46.026352 Freq=1200, CH1 RK1
3626 22:15:46.026418
3627 22:15:46.030027 DATLAT Default: 0xd
3628 22:15:46.030117 0, 0xFFFF, sum = 0
3629 22:15:46.033150 1, 0xFFFF, sum = 0
3630 22:15:46.033234 2, 0xFFFF, sum = 0
3631 22:15:46.036256 3, 0xFFFF, sum = 0
3632 22:15:46.036340 4, 0xFFFF, sum = 0
3633 22:15:46.039972 5, 0xFFFF, sum = 0
3634 22:15:46.040056 6, 0xFFFF, sum = 0
3635 22:15:46.042959 7, 0xFFFF, sum = 0
3636 22:15:46.043043 8, 0xFFFF, sum = 0
3637 22:15:46.046461 9, 0xFFFF, sum = 0
3638 22:15:46.046571 10, 0xFFFF, sum = 0
3639 22:15:46.049840 11, 0xFFFF, sum = 0
3640 22:15:46.053028 12, 0x0, sum = 1
3641 22:15:46.053133 13, 0x0, sum = 2
3642 22:15:46.053227 14, 0x0, sum = 3
3643 22:15:46.056260 15, 0x0, sum = 4
3644 22:15:46.056343 best_step = 13
3645 22:15:46.056407
3646 22:15:46.056467 ==
3647 22:15:46.059582 Dram Type= 6, Freq= 0, CH_1, rank 1
3648 22:15:46.066496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3649 22:15:46.066621 ==
3650 22:15:46.066740 RX Vref Scan: 0
3651 22:15:46.066855
3652 22:15:46.070307 RX Vref 0 -> 0, step: 1
3653 22:15:46.070439
3654 22:15:46.073208 RX Delay -5 -> 252, step: 4
3655 22:15:46.076717 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3656 22:15:46.079868 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3657 22:15:46.086317 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3658 22:15:46.089801 iDelay=195, Bit 3, Center 118 (59 ~ 178) 120
3659 22:15:46.093267 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3660 22:15:46.096375 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3661 22:15:46.099541 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3662 22:15:46.106731 iDelay=195, Bit 7, Center 120 (59 ~ 182) 124
3663 22:15:46.109776 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3664 22:15:46.112682 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3665 22:15:46.116681 iDelay=195, Bit 10, Center 118 (59 ~ 178) 120
3666 22:15:46.119853 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3667 22:15:46.126308 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3668 22:15:46.129680 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3669 22:15:46.132777 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3670 22:15:46.136268 iDelay=195, Bit 15, Center 128 (67 ~ 190) 124
3671 22:15:46.136350 ==
3672 22:15:46.139478 Dram Type= 6, Freq= 0, CH_1, rank 1
3673 22:15:46.146112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3674 22:15:46.146196 ==
3675 22:15:46.146261 DQS Delay:
3676 22:15:46.146321 DQS0 = 0, DQS1 = 0
3677 22:15:46.149474 DQM Delay:
3678 22:15:46.149606 DQM0 = 120, DQM1 = 118
3679 22:15:46.152862 DQ Delay:
3680 22:15:46.156409 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =118
3681 22:15:46.159721 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =120
3682 22:15:46.163179 DQ8 =106, DQ9 =108, DQ10 =118, DQ11 =112
3683 22:15:46.166481 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =128
3684 22:15:46.166562
3685 22:15:46.166627
3686 22:15:46.176362 [DQSOSCAuto] RK1, (LSB)MR18= 0x13f0, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 402 ps
3687 22:15:46.176448 CH1 RK1: MR19=403, MR18=13F0
3688 22:15:46.183153 CH1_RK1: MR19=0x403, MR18=0x13F0, DQSOSC=402, MR23=63, INC=40, DEC=27
3689 22:15:46.186254 [RxdqsGatingPostProcess] freq 1200
3690 22:15:46.192900 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3691 22:15:46.196311 best DQS0 dly(2T, 0.5T) = (0, 11)
3692 22:15:46.199818 best DQS1 dly(2T, 0.5T) = (0, 11)
3693 22:15:46.202944 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3694 22:15:46.205940 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3695 22:15:46.206022 best DQS0 dly(2T, 0.5T) = (0, 11)
3696 22:15:46.209399 best DQS1 dly(2T, 0.5T) = (0, 11)
3697 22:15:46.212959 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3698 22:15:46.215963 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3699 22:15:46.219745 Pre-setting of DQS Precalculation
3700 22:15:46.226296 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3701 22:15:46.232575 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3702 22:15:46.239379 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3703 22:15:46.239461
3704 22:15:46.239557
3705 22:15:46.242634 [Calibration Summary] 2400 Mbps
3706 22:15:46.242716 CH 0, Rank 0
3707 22:15:46.246283 SW Impedance : PASS
3708 22:15:46.249266 DUTY Scan : NO K
3709 22:15:46.249347 ZQ Calibration : PASS
3710 22:15:46.252461 Jitter Meter : NO K
3711 22:15:46.255880 CBT Training : PASS
3712 22:15:46.255993 Write leveling : PASS
3713 22:15:46.259661 RX DQS gating : PASS
3714 22:15:46.262482 RX DQ/DQS(RDDQC) : PASS
3715 22:15:46.262564 TX DQ/DQS : PASS
3716 22:15:46.266327 RX DATLAT : PASS
3717 22:15:46.269685 RX DQ/DQS(Engine): PASS
3718 22:15:46.269766 TX OE : NO K
3719 22:15:46.269832 All Pass.
3720 22:15:46.272473
3721 22:15:46.272554 CH 0, Rank 1
3722 22:15:46.276021 SW Impedance : PASS
3723 22:15:46.276102 DUTY Scan : NO K
3724 22:15:46.279273 ZQ Calibration : PASS
3725 22:15:46.279354 Jitter Meter : NO K
3726 22:15:46.282951 CBT Training : PASS
3727 22:15:46.286051 Write leveling : PASS
3728 22:15:46.286132 RX DQS gating : PASS
3729 22:15:46.289115 RX DQ/DQS(RDDQC) : PASS
3730 22:15:46.292642 TX DQ/DQS : PASS
3731 22:15:46.292724 RX DATLAT : PASS
3732 22:15:46.295645 RX DQ/DQS(Engine): PASS
3733 22:15:46.299148 TX OE : NO K
3734 22:15:46.299230 All Pass.
3735 22:15:46.299295
3736 22:15:46.299356 CH 1, Rank 0
3737 22:15:46.302411 SW Impedance : PASS
3738 22:15:46.305939 DUTY Scan : NO K
3739 22:15:46.306020 ZQ Calibration : PASS
3740 22:15:46.309137 Jitter Meter : NO K
3741 22:15:46.312569 CBT Training : PASS
3742 22:15:46.312650 Write leveling : PASS
3743 22:15:46.315826 RX DQS gating : PASS
3744 22:15:46.319217 RX DQ/DQS(RDDQC) : PASS
3745 22:15:46.319299 TX DQ/DQS : PASS
3746 22:15:46.322236 RX DATLAT : PASS
3747 22:15:46.325640 RX DQ/DQS(Engine): PASS
3748 22:15:46.325721 TX OE : NO K
3749 22:15:46.325786 All Pass.
3750 22:15:46.328840
3751 22:15:46.328920 CH 1, Rank 1
3752 22:15:46.332189 SW Impedance : PASS
3753 22:15:46.332270 DUTY Scan : NO K
3754 22:15:46.335399 ZQ Calibration : PASS
3755 22:15:46.335481 Jitter Meter : NO K
3756 22:15:46.338818 CBT Training : PASS
3757 22:15:46.342335 Write leveling : PASS
3758 22:15:46.342442 RX DQS gating : PASS
3759 22:15:46.345459 RX DQ/DQS(RDDQC) : PASS
3760 22:15:46.349183 TX DQ/DQS : PASS
3761 22:15:46.349264 RX DATLAT : PASS
3762 22:15:46.352421 RX DQ/DQS(Engine): PASS
3763 22:15:46.355712 TX OE : NO K
3764 22:15:46.355798 All Pass.
3765 22:15:46.355867
3766 22:15:46.359022 DramC Write-DBI off
3767 22:15:46.359104 PER_BANK_REFRESH: Hybrid Mode
3768 22:15:46.362024 TX_TRACKING: ON
3769 22:15:46.369177 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3770 22:15:46.375429 [FAST_K] Save calibration result to emmc
3771 22:15:46.379040 dramc_set_vcore_voltage set vcore to 650000
3772 22:15:46.379122 Read voltage for 600, 5
3773 22:15:46.382384 Vio18 = 0
3774 22:15:46.382465 Vcore = 650000
3775 22:15:46.382530 Vdram = 0
3776 22:15:46.385979 Vddq = 0
3777 22:15:46.386060 Vmddr = 0
3778 22:15:46.389078 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3779 22:15:46.395603 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3780 22:15:46.399098 MEM_TYPE=3, freq_sel=19
3781 22:15:46.402231 sv_algorithm_assistance_LP4_1600
3782 22:15:46.405698 ============ PULL DRAM RESETB DOWN ============
3783 22:15:46.408872 ========== PULL DRAM RESETB DOWN end =========
3784 22:15:46.412577 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3785 22:15:46.415541 ===================================
3786 22:15:46.419097 LPDDR4 DRAM CONFIGURATION
3787 22:15:46.422489 ===================================
3788 22:15:46.425732 EX_ROW_EN[0] = 0x0
3789 22:15:46.425832 EX_ROW_EN[1] = 0x0
3790 22:15:46.429321 LP4Y_EN = 0x0
3791 22:15:46.429421 WORK_FSP = 0x0
3792 22:15:46.432436 WL = 0x2
3793 22:15:46.432512 RL = 0x2
3794 22:15:46.435865 BL = 0x2
3795 22:15:46.435935 RPST = 0x0
3796 22:15:46.438665 RD_PRE = 0x0
3797 22:15:46.438753 WR_PRE = 0x1
3798 22:15:46.442263 WR_PST = 0x0
3799 22:15:46.442370 DBI_WR = 0x0
3800 22:15:46.445419 DBI_RD = 0x0
3801 22:15:46.448639 OTF = 0x1
3802 22:15:46.452292 ===================================
3803 22:15:46.452394 ===================================
3804 22:15:46.455872 ANA top config
3805 22:15:46.458889 ===================================
3806 22:15:46.462165 DLL_ASYNC_EN = 0
3807 22:15:46.462244 ALL_SLAVE_EN = 1
3808 22:15:46.465317 NEW_RANK_MODE = 1
3809 22:15:46.469009 DLL_IDLE_MODE = 1
3810 22:15:46.471983 LP45_APHY_COMB_EN = 1
3811 22:15:46.475338 TX_ODT_DIS = 1
3812 22:15:46.475441 NEW_8X_MODE = 1
3813 22:15:46.478642 ===================================
3814 22:15:46.481874 ===================================
3815 22:15:46.485536 data_rate = 1200
3816 22:15:46.488708 CKR = 1
3817 22:15:46.491977 DQ_P2S_RATIO = 8
3818 22:15:46.495524 ===================================
3819 22:15:46.498635 CA_P2S_RATIO = 8
3820 22:15:46.501818 DQ_CA_OPEN = 0
3821 22:15:46.501892 DQ_SEMI_OPEN = 0
3822 22:15:46.505262 CA_SEMI_OPEN = 0
3823 22:15:46.508695 CA_FULL_RATE = 0
3824 22:15:46.512101 DQ_CKDIV4_EN = 1
3825 22:15:46.515605 CA_CKDIV4_EN = 1
3826 22:15:46.515713 CA_PREDIV_EN = 0
3827 22:15:46.518777 PH8_DLY = 0
3828 22:15:46.521822 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3829 22:15:46.525177 DQ_AAMCK_DIV = 4
3830 22:15:46.528609 CA_AAMCK_DIV = 4
3831 22:15:46.531858 CA_ADMCK_DIV = 4
3832 22:15:46.531969 DQ_TRACK_CA_EN = 0
3833 22:15:46.535539 CA_PICK = 600
3834 22:15:46.538953 CA_MCKIO = 600
3835 22:15:46.542299 MCKIO_SEMI = 0
3836 22:15:46.545372 PLL_FREQ = 2288
3837 22:15:46.548464 DQ_UI_PI_RATIO = 32
3838 22:15:46.551828 CA_UI_PI_RATIO = 0
3839 22:15:46.555449 ===================================
3840 22:15:46.558367 ===================================
3841 22:15:46.558473 memory_type:LPDDR4
3842 22:15:46.562109 GP_NUM : 10
3843 22:15:46.565017 SRAM_EN : 1
3844 22:15:46.565115 MD32_EN : 0
3845 22:15:46.568730 ===================================
3846 22:15:46.571944 [ANA_INIT] >>>>>>>>>>>>>>
3847 22:15:46.575436 <<<<<< [CONFIGURE PHASE]: ANA_TX
3848 22:15:46.578503 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3849 22:15:46.581689 ===================================
3850 22:15:46.585213 data_rate = 1200,PCW = 0X5800
3851 22:15:46.588118 ===================================
3852 22:15:46.591610 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3853 22:15:46.594794 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3854 22:15:46.601661 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3855 22:15:46.604999 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3856 22:15:46.608078 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3857 22:15:46.611638 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3858 22:15:46.614791 [ANA_INIT] flow start
3859 22:15:46.618293 [ANA_INIT] PLL >>>>>>>>
3860 22:15:46.618400 [ANA_INIT] PLL <<<<<<<<
3861 22:15:46.621825 [ANA_INIT] MIDPI >>>>>>>>
3862 22:15:46.624876 [ANA_INIT] MIDPI <<<<<<<<
3863 22:15:46.624971 [ANA_INIT] DLL >>>>>>>>
3864 22:15:46.628412 [ANA_INIT] flow end
3865 22:15:46.631870 ============ LP4 DIFF to SE enter ============
3866 22:15:46.638380 ============ LP4 DIFF to SE exit ============
3867 22:15:46.638485 [ANA_INIT] <<<<<<<<<<<<<
3868 22:15:46.641863 [Flow] Enable top DCM control >>>>>
3869 22:15:46.644737 [Flow] Enable top DCM control <<<<<
3870 22:15:46.647865 Enable DLL master slave shuffle
3871 22:15:46.654985 ==============================================================
3872 22:15:46.655090 Gating Mode config
3873 22:15:46.661845 ==============================================================
3874 22:15:46.664747 Config description:
3875 22:15:46.671334 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3876 22:15:46.678089 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3877 22:15:46.684835 SELPH_MODE 0: By rank 1: By Phase
3878 22:15:46.691630 ==============================================================
3879 22:15:46.691719 GAT_TRACK_EN = 1
3880 22:15:46.694929 RX_GATING_MODE = 2
3881 22:15:46.698320 RX_GATING_TRACK_MODE = 2
3882 22:15:46.701239 SELPH_MODE = 1
3883 22:15:46.704560 PICG_EARLY_EN = 1
3884 22:15:46.708017 VALID_LAT_VALUE = 1
3885 22:15:46.714504 ==============================================================
3886 22:15:46.718166 Enter into Gating configuration >>>>
3887 22:15:46.721056 Exit from Gating configuration <<<<
3888 22:15:46.724516 Enter into DVFS_PRE_config >>>>>
3889 22:15:46.734666 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3890 22:15:46.737815 Exit from DVFS_PRE_config <<<<<
3891 22:15:46.741213 Enter into PICG configuration >>>>
3892 22:15:46.744685 Exit from PICG configuration <<<<
3893 22:15:46.747935 [RX_INPUT] configuration >>>>>
3894 22:15:46.748034 [RX_INPUT] configuration <<<<<
3895 22:15:46.754123 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3896 22:15:46.761254 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3897 22:15:46.767847 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3898 22:15:46.770969 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3899 22:15:46.777827 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3900 22:15:46.784511 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3901 22:15:46.787547 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3902 22:15:46.791051 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3903 22:15:46.797819 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3904 22:15:46.801160 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3905 22:15:46.804663 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3906 22:15:46.811023 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3907 22:15:46.814802 ===================================
3908 22:15:46.814881 LPDDR4 DRAM CONFIGURATION
3909 22:15:46.817461 ===================================
3910 22:15:46.821249 EX_ROW_EN[0] = 0x0
3911 22:15:46.821326 EX_ROW_EN[1] = 0x0
3912 22:15:46.824138 LP4Y_EN = 0x0
3913 22:15:46.824210 WORK_FSP = 0x0
3914 22:15:46.827936 WL = 0x2
3915 22:15:46.828035 RL = 0x2
3916 22:15:46.830850 BL = 0x2
3917 22:15:46.834452 RPST = 0x0
3918 22:15:46.834552 RD_PRE = 0x0
3919 22:15:46.837826 WR_PRE = 0x1
3920 22:15:46.837929 WR_PST = 0x0
3921 22:15:46.841234 DBI_WR = 0x0
3922 22:15:46.841338 DBI_RD = 0x0
3923 22:15:46.844210 OTF = 0x1
3924 22:15:46.847385 ===================================
3925 22:15:46.850845 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3926 22:15:46.854026 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3927 22:15:46.860587 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3928 22:15:46.860669 ===================================
3929 22:15:46.864065 LPDDR4 DRAM CONFIGURATION
3930 22:15:46.867523 ===================================
3931 22:15:46.870687 EX_ROW_EN[0] = 0x10
3932 22:15:46.870769 EX_ROW_EN[1] = 0x0
3933 22:15:46.874145 LP4Y_EN = 0x0
3934 22:15:46.874226 WORK_FSP = 0x0
3935 22:15:46.877277 WL = 0x2
3936 22:15:46.877386 RL = 0x2
3937 22:15:46.880658 BL = 0x2
3938 22:15:46.880739 RPST = 0x0
3939 22:15:46.884550 RD_PRE = 0x0
3940 22:15:46.887831 WR_PRE = 0x1
3941 22:15:46.887912 WR_PST = 0x0
3942 22:15:46.890597 DBI_WR = 0x0
3943 22:15:46.890678 DBI_RD = 0x0
3944 22:15:46.894110 OTF = 0x1
3945 22:15:46.897375 ===================================
3946 22:15:46.900818 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3947 22:15:46.905931 nWR fixed to 30
3948 22:15:46.909803 [ModeRegInit_LP4] CH0 RK0
3949 22:15:46.909884 [ModeRegInit_LP4] CH0 RK1
3950 22:15:46.912679 [ModeRegInit_LP4] CH1 RK0
3951 22:15:46.916349 [ModeRegInit_LP4] CH1 RK1
3952 22:15:46.916430 match AC timing 17
3953 22:15:46.923254 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3954 22:15:46.926055 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3955 22:15:46.929482 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3956 22:15:46.936158 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3957 22:15:46.939669 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3958 22:15:46.939751 ==
3959 22:15:46.943106 Dram Type= 6, Freq= 0, CH_0, rank 0
3960 22:15:46.946180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3961 22:15:46.946263 ==
3962 22:15:46.953087 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3963 22:15:46.959483 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3964 22:15:46.962623 [CA 0] Center 35 (5~66) winsize 62
3965 22:15:46.965916 [CA 1] Center 35 (5~66) winsize 62
3966 22:15:46.969062 [CA 2] Center 33 (3~64) winsize 62
3967 22:15:46.972740 [CA 3] Center 33 (2~64) winsize 63
3968 22:15:46.976190 [CA 4] Center 33 (2~64) winsize 63
3969 22:15:46.979254 [CA 5] Center 32 (2~63) winsize 62
3970 22:15:46.979333
3971 22:15:46.982221 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3972 22:15:46.982291
3973 22:15:46.985620 [CATrainingPosCal] consider 1 rank data
3974 22:15:46.988727 u2DelayCellTimex100 = 270/100 ps
3975 22:15:46.992278 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3976 22:15:46.995414 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3977 22:15:46.998799 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3978 22:15:47.002511 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3979 22:15:47.005214 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3980 22:15:47.012322 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3981 22:15:47.012404
3982 22:15:47.015426 CA PerBit enable=1, Macro0, CA PI delay=32
3983 22:15:47.015509
3984 22:15:47.018760 [CBTSetCACLKResult] CA Dly = 32
3985 22:15:47.018843 CS Dly: 4 (0~35)
3986 22:15:47.018909 ==
3987 22:15:47.022323 Dram Type= 6, Freq= 0, CH_0, rank 1
3988 22:15:47.025708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3989 22:15:47.025791 ==
3990 22:15:47.031949 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3991 22:15:47.039184 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3992 22:15:47.042159 [CA 0] Center 35 (5~66) winsize 62
3993 22:15:47.045092 [CA 1] Center 35 (5~66) winsize 62
3994 22:15:47.048634 [CA 2] Center 34 (3~65) winsize 63
3995 22:15:47.052147 [CA 3] Center 33 (3~64) winsize 62
3996 22:15:47.055656 [CA 4] Center 33 (2~64) winsize 63
3997 22:15:47.058702 [CA 5] Center 32 (2~63) winsize 62
3998 22:15:47.058784
3999 22:15:47.061773 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4000 22:15:47.061855
4001 22:15:47.065389 [CATrainingPosCal] consider 2 rank data
4002 22:15:47.068734 u2DelayCellTimex100 = 270/100 ps
4003 22:15:47.072414 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4004 22:15:47.075610 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
4005 22:15:47.078841 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4006 22:15:47.082164 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4007 22:15:47.085123 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
4008 22:15:47.092094 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4009 22:15:47.092176
4010 22:15:47.095775 CA PerBit enable=1, Macro0, CA PI delay=32
4011 22:15:47.095857
4012 22:15:47.098726 [CBTSetCACLKResult] CA Dly = 32
4013 22:15:47.098809 CS Dly: 4 (0~36)
4014 22:15:47.098875
4015 22:15:47.102343 ----->DramcWriteLeveling(PI) begin...
4016 22:15:47.102427 ==
4017 22:15:47.105360 Dram Type= 6, Freq= 0, CH_0, rank 0
4018 22:15:47.111769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4019 22:15:47.111852 ==
4020 22:15:47.115202 Write leveling (Byte 0): 35 => 35
4021 22:15:47.115288 Write leveling (Byte 1): 32 => 32
4022 22:15:47.118547 DramcWriteLeveling(PI) end<-----
4023 22:15:47.118629
4024 22:15:47.118694 ==
4025 22:15:47.122209 Dram Type= 6, Freq= 0, CH_0, rank 0
4026 22:15:47.128272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4027 22:15:47.128354 ==
4028 22:15:47.131918 [Gating] SW mode calibration
4029 22:15:47.138587 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4030 22:15:47.142142 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4031 22:15:47.148228 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4032 22:15:47.152217 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4033 22:15:47.155326 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4034 22:15:47.158672 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (0 0)
4035 22:15:47.165403 0 9 16 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
4036 22:15:47.168404 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4037 22:15:47.172093 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4038 22:15:47.178508 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4039 22:15:47.182160 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4040 22:15:47.185447 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4041 22:15:47.191913 0 10 8 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
4042 22:15:47.195124 0 10 12 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
4043 22:15:47.198694 0 10 16 | B1->B0 | 3232 4646 | 1 0 | (0 0) (0 0)
4044 22:15:47.205340 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4045 22:15:47.208358 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4046 22:15:47.211990 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4047 22:15:47.218578 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4048 22:15:47.221842 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4049 22:15:47.225351 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4050 22:15:47.232338 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4051 22:15:47.235336 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4052 22:15:47.238420 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4053 22:15:47.245014 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4054 22:15:47.248257 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4055 22:15:47.251997 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4056 22:15:47.258390 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4057 22:15:47.261776 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4058 22:15:47.264700 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4059 22:15:47.271278 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4060 22:15:47.275053 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4061 22:15:47.278109 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4062 22:15:47.285208 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 22:15:47.288607 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 22:15:47.291520 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 22:15:47.295045 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 22:15:47.302131 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4067 22:15:47.305011 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4068 22:15:47.308608 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4069 22:15:47.311586 Total UI for P1: 0, mck2ui 16
4070 22:15:47.315095 best dqsien dly found for B0: ( 0, 13, 14)
4071 22:15:47.318601 Total UI for P1: 0, mck2ui 16
4072 22:15:47.322042 best dqsien dly found for B1: ( 0, 13, 16)
4073 22:15:47.325090 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4074 22:15:47.328568 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4075 22:15:47.328651
4076 22:15:47.335278 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4077 22:15:47.338634 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4078 22:15:47.338717 [Gating] SW calibration Done
4079 22:15:47.342103 ==
4080 22:15:47.345031 Dram Type= 6, Freq= 0, CH_0, rank 0
4081 22:15:47.348473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4082 22:15:47.348556 ==
4083 22:15:47.348622 RX Vref Scan: 0
4084 22:15:47.348683
4085 22:15:47.351722 RX Vref 0 -> 0, step: 1
4086 22:15:47.351804
4087 22:15:47.355068 RX Delay -230 -> 252, step: 16
4088 22:15:47.358407 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4089 22:15:47.361459 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4090 22:15:47.368447 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4091 22:15:47.372056 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4092 22:15:47.375024 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4093 22:15:47.378620 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4094 22:15:47.381763 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4095 22:15:47.388506 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4096 22:15:47.391498 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4097 22:15:47.395247 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4098 22:15:47.398901 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4099 22:15:47.405210 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4100 22:15:47.408264 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4101 22:15:47.411677 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4102 22:15:47.415163 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4103 22:15:47.421915 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4104 22:15:47.421996 ==
4105 22:15:47.424836 Dram Type= 6, Freq= 0, CH_0, rank 0
4106 22:15:47.428197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4107 22:15:47.428298 ==
4108 22:15:47.428399 DQS Delay:
4109 22:15:47.431641 DQS0 = 0, DQS1 = 0
4110 22:15:47.431721 DQM Delay:
4111 22:15:47.434928 DQM0 = 49, DQM1 = 45
4112 22:15:47.435029 DQ Delay:
4113 22:15:47.438220 DQ0 =49, DQ1 =57, DQ2 =41, DQ3 =41
4114 22:15:47.441527 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4115 22:15:47.445015 DQ8 =33, DQ9 =33, DQ10 =41, DQ11 =41
4116 22:15:47.448499 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =57
4117 22:15:47.448595
4118 22:15:47.448684
4119 22:15:47.448770 ==
4120 22:15:47.451524 Dram Type= 6, Freq= 0, CH_0, rank 0
4121 22:15:47.454891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4122 22:15:47.454991 ==
4123 22:15:47.455083
4124 22:15:47.455171
4125 22:15:47.458437 TX Vref Scan disable
4126 22:15:47.461743 == TX Byte 0 ==
4127 22:15:47.464999 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4128 22:15:47.468131 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4129 22:15:47.471450 == TX Byte 1 ==
4130 22:15:47.475058 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4131 22:15:47.478040 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4132 22:15:47.478113 ==
4133 22:15:47.481602 Dram Type= 6, Freq= 0, CH_0, rank 0
4134 22:15:47.488192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4135 22:15:47.488296 ==
4136 22:15:47.488390
4137 22:15:47.488480
4138 22:15:47.488567 TX Vref Scan disable
4139 22:15:47.492750 == TX Byte 0 ==
4140 22:15:47.495895 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4141 22:15:47.502599 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4142 22:15:47.502674 == TX Byte 1 ==
4143 22:15:47.506164 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4144 22:15:47.512537 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4145 22:15:47.512640
4146 22:15:47.512733 [DATLAT]
4147 22:15:47.512822 Freq=600, CH0 RK0
4148 22:15:47.512911
4149 22:15:47.516160 DATLAT Default: 0x9
4150 22:15:47.516257 0, 0xFFFF, sum = 0
4151 22:15:47.519255 1, 0xFFFF, sum = 0
4152 22:15:47.519332 2, 0xFFFF, sum = 0
4153 22:15:47.522964 3, 0xFFFF, sum = 0
4154 22:15:47.525898 4, 0xFFFF, sum = 0
4155 22:15:47.525971 5, 0xFFFF, sum = 0
4156 22:15:47.529273 6, 0xFFFF, sum = 0
4157 22:15:47.529373 7, 0xFFFF, sum = 0
4158 22:15:47.532331 8, 0x0, sum = 1
4159 22:15:47.532432 9, 0x0, sum = 2
4160 22:15:47.532525 10, 0x0, sum = 3
4161 22:15:47.535855 11, 0x0, sum = 4
4162 22:15:47.535954 best_step = 9
4163 22:15:47.536042
4164 22:15:47.536130 ==
4165 22:15:47.539729 Dram Type= 6, Freq= 0, CH_0, rank 0
4166 22:15:47.545852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4167 22:15:47.545931 ==
4168 22:15:47.545996 RX Vref Scan: 1
4169 22:15:47.546056
4170 22:15:47.549133 RX Vref 0 -> 0, step: 1
4171 22:15:47.549228
4172 22:15:47.552537 RX Delay -163 -> 252, step: 8
4173 22:15:47.552621
4174 22:15:47.555845 Set Vref, RX VrefLevel [Byte0]: 56
4175 22:15:47.559127 [Byte1]: 48
4176 22:15:47.559210
4177 22:15:47.562619 Final RX Vref Byte 0 = 56 to rank0
4178 22:15:47.565757 Final RX Vref Byte 1 = 48 to rank0
4179 22:15:47.569265 Final RX Vref Byte 0 = 56 to rank1
4180 22:15:47.572445 Final RX Vref Byte 1 = 48 to rank1==
4181 22:15:47.575961 Dram Type= 6, Freq= 0, CH_0, rank 0
4182 22:15:47.579208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4183 22:15:47.579291 ==
4184 22:15:47.582542 DQS Delay:
4185 22:15:47.582625 DQS0 = 0, DQS1 = 0
4186 22:15:47.585553 DQM Delay:
4187 22:15:47.585660 DQM0 = 52, DQM1 = 45
4188 22:15:47.585739 DQ Delay:
4189 22:15:47.588802 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =48
4190 22:15:47.592189 DQ4 =52, DQ5 =44, DQ6 =60, DQ7 =60
4191 22:15:47.596139 DQ8 =32, DQ9 =36, DQ10 =48, DQ11 =40
4192 22:15:47.598975 DQ12 =52, DQ13 =48, DQ14 =56, DQ15 =52
4193 22:15:47.599074
4194 22:15:47.599165
4195 22:15:47.608765 [DQSOSCAuto] RK0, (LSB)MR18= 0x6f62, (MSB)MR19= 0x808, tDQSOscB0 = 391 ps tDQSOscB1 = 389 ps
4196 22:15:47.612063 CH0 RK0: MR19=808, MR18=6F62
4197 22:15:47.618560 CH0_RK0: MR19=0x808, MR18=0x6F62, DQSOSC=389, MR23=63, INC=173, DEC=115
4198 22:15:47.618664
4199 22:15:47.622307 ----->DramcWriteLeveling(PI) begin...
4200 22:15:47.622406 ==
4201 22:15:47.625063 Dram Type= 6, Freq= 0, CH_0, rank 1
4202 22:15:47.628299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4203 22:15:47.628399 ==
4204 22:15:47.631862 Write leveling (Byte 0): 35 => 35
4205 22:15:47.635206 Write leveling (Byte 1): 33 => 33
4206 22:15:47.638529 DramcWriteLeveling(PI) end<-----
4207 22:15:47.638600
4208 22:15:47.638661 ==
4209 22:15:47.642021 Dram Type= 6, Freq= 0, CH_0, rank 1
4210 22:15:47.645061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4211 22:15:47.645157 ==
4212 22:15:47.648808 [Gating] SW mode calibration
4213 22:15:47.654917 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4214 22:15:47.661584 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4215 22:15:47.665023 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4216 22:15:47.668619 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4217 22:15:47.675173 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4218 22:15:47.678539 0 9 12 | B1->B0 | 3333 3434 | 1 0 | (1 1) (0 0)
4219 22:15:47.681966 0 9 16 | B1->B0 | 2b2b 2727 | 0 0 | (0 0) (0 0)
4220 22:15:47.688083 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4221 22:15:47.691815 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4222 22:15:47.694910 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4223 22:15:47.698717 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4224 22:15:47.705110 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4225 22:15:47.708802 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4226 22:15:47.711714 0 10 12 | B1->B0 | 2525 2d2d | 0 1 | (0 0) (0 0)
4227 22:15:47.718450 0 10 16 | B1->B0 | 3f3f 4343 | 0 0 | (0 0) (0 0)
4228 22:15:47.722207 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4229 22:15:47.725273 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4230 22:15:47.731945 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4231 22:15:47.735355 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4232 22:15:47.738479 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4233 22:15:47.745330 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4234 22:15:47.748830 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4235 22:15:47.751715 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4236 22:15:47.758614 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4237 22:15:47.761952 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4238 22:15:47.764858 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4239 22:15:47.771471 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4240 22:15:47.774961 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4241 22:15:47.778508 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4242 22:15:47.785114 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4243 22:15:47.788432 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4244 22:15:47.792188 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4245 22:15:47.798136 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4246 22:15:47.801684 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4247 22:15:47.805399 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4248 22:15:47.808415 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4249 22:15:47.814763 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 22:15:47.818505 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4251 22:15:47.821972 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4252 22:15:47.825175 Total UI for P1: 0, mck2ui 16
4253 22:15:47.827990 best dqsien dly found for B0: ( 0, 13, 12)
4254 22:15:47.831540 Total UI for P1: 0, mck2ui 16
4255 22:15:47.835227 best dqsien dly found for B1: ( 0, 13, 14)
4256 22:15:47.838139 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4257 22:15:47.844728 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4258 22:15:47.844810
4259 22:15:47.848225 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4260 22:15:47.851331 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4261 22:15:47.855052 [Gating] SW calibration Done
4262 22:15:47.855134 ==
4263 22:15:47.858048 Dram Type= 6, Freq= 0, CH_0, rank 1
4264 22:15:47.861298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4265 22:15:47.861381 ==
4266 22:15:47.861446 RX Vref Scan: 0
4267 22:15:47.864780
4268 22:15:47.864862 RX Vref 0 -> 0, step: 1
4269 22:15:47.864927
4270 22:15:47.867856 RX Delay -230 -> 252, step: 16
4271 22:15:47.871370 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4272 22:15:47.878221 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4273 22:15:47.881213 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4274 22:15:47.884543 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4275 22:15:47.887894 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4276 22:15:47.891161 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4277 22:15:47.898009 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4278 22:15:47.900928 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4279 22:15:47.904895 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4280 22:15:47.907788 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4281 22:15:47.915005 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4282 22:15:47.917892 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4283 22:15:47.921010 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4284 22:15:47.924717 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4285 22:15:47.931275 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4286 22:15:47.934256 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4287 22:15:47.934337 ==
4288 22:15:47.937970 Dram Type= 6, Freq= 0, CH_0, rank 1
4289 22:15:47.941142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4290 22:15:47.941227 ==
4291 22:15:47.944681 DQS Delay:
4292 22:15:47.944762 DQS0 = 0, DQS1 = 0
4293 22:15:47.944827 DQM Delay:
4294 22:15:47.948022 DQM0 = 52, DQM1 = 43
4295 22:15:47.948103 DQ Delay:
4296 22:15:47.951003 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =49
4297 22:15:47.954192 DQ4 =57, DQ5 =49, DQ6 =57, DQ7 =57
4298 22:15:47.957697 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =33
4299 22:15:47.961258 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4300 22:15:47.961340
4301 22:15:47.961404
4302 22:15:47.961464 ==
4303 22:15:47.964536 Dram Type= 6, Freq= 0, CH_0, rank 1
4304 22:15:47.970831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4305 22:15:47.970913 ==
4306 22:15:47.970978
4307 22:15:47.971039
4308 22:15:47.971097 TX Vref Scan disable
4309 22:15:47.974376 == TX Byte 0 ==
4310 22:15:47.977720 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4311 22:15:47.984600 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4312 22:15:47.984682 == TX Byte 1 ==
4313 22:15:47.987901 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4314 22:15:47.994003 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4315 22:15:47.994085 ==
4316 22:15:47.997529 Dram Type= 6, Freq= 0, CH_0, rank 1
4317 22:15:48.000999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4318 22:15:48.001081 ==
4319 22:15:48.001170
4320 22:15:48.001244
4321 22:15:48.004583 TX Vref Scan disable
4322 22:15:48.004665 == TX Byte 0 ==
4323 22:15:48.011237 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4324 22:15:48.014139 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4325 22:15:48.014221 == TX Byte 1 ==
4326 22:15:48.021232 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4327 22:15:48.024057 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4328 22:15:48.024139
4329 22:15:48.024204 [DATLAT]
4330 22:15:48.027578 Freq=600, CH0 RK1
4331 22:15:48.027660
4332 22:15:48.027724 DATLAT Default: 0x9
4333 22:15:48.030870 0, 0xFFFF, sum = 0
4334 22:15:48.034050 1, 0xFFFF, sum = 0
4335 22:15:48.034132 2, 0xFFFF, sum = 0
4336 22:15:48.037374 3, 0xFFFF, sum = 0
4337 22:15:48.037483 4, 0xFFFF, sum = 0
4338 22:15:48.040930 5, 0xFFFF, sum = 0
4339 22:15:48.041012 6, 0xFFFF, sum = 0
4340 22:15:48.043924 7, 0xFFFF, sum = 0
4341 22:15:48.044007 8, 0x0, sum = 1
4342 22:15:48.047168 9, 0x0, sum = 2
4343 22:15:48.047251 10, 0x0, sum = 3
4344 22:15:48.047317 11, 0x0, sum = 4
4345 22:15:48.050818 best_step = 9
4346 22:15:48.050898
4347 22:15:48.050963 ==
4348 22:15:48.054239 Dram Type= 6, Freq= 0, CH_0, rank 1
4349 22:15:48.057061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4350 22:15:48.057143 ==
4351 22:15:48.060763 RX Vref Scan: 0
4352 22:15:48.060844
4353 22:15:48.060909 RX Vref 0 -> 0, step: 1
4354 22:15:48.060971
4355 22:15:48.063755 RX Delay -163 -> 252, step: 8
4356 22:15:48.071307 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4357 22:15:48.074515 iDelay=205, Bit 1, Center 56 (-83 ~ 196) 280
4358 22:15:48.077719 iDelay=205, Bit 2, Center 52 (-91 ~ 196) 288
4359 22:15:48.081800 iDelay=205, Bit 3, Center 52 (-91 ~ 196) 288
4360 22:15:48.084591 iDelay=205, Bit 4, Center 56 (-83 ~ 196) 280
4361 22:15:48.091323 iDelay=205, Bit 5, Center 44 (-99 ~ 188) 288
4362 22:15:48.094736 iDelay=205, Bit 6, Center 60 (-75 ~ 196) 272
4363 22:15:48.097932 iDelay=205, Bit 7, Center 60 (-83 ~ 204) 288
4364 22:15:48.101478 iDelay=205, Bit 8, Center 36 (-107 ~ 180) 288
4365 22:15:48.104414 iDelay=205, Bit 9, Center 36 (-107 ~ 180) 288
4366 22:15:48.111643 iDelay=205, Bit 10, Center 48 (-91 ~ 188) 280
4367 22:15:48.114747 iDelay=205, Bit 11, Center 40 (-99 ~ 180) 280
4368 22:15:48.117920 iDelay=205, Bit 12, Center 48 (-91 ~ 188) 280
4369 22:15:48.121196 iDelay=205, Bit 13, Center 56 (-83 ~ 196) 280
4370 22:15:48.127936 iDelay=205, Bit 14, Center 56 (-83 ~ 196) 280
4371 22:15:48.131107 iDelay=205, Bit 15, Center 52 (-91 ~ 196) 288
4372 22:15:48.131187 ==
4373 22:15:48.134449 Dram Type= 6, Freq= 0, CH_0, rank 1
4374 22:15:48.137975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4375 22:15:48.138055 ==
4376 22:15:48.140998 DQS Delay:
4377 22:15:48.141077 DQS0 = 0, DQS1 = 0
4378 22:15:48.141140 DQM Delay:
4379 22:15:48.144576 DQM0 = 54, DQM1 = 46
4380 22:15:48.144660 DQ Delay:
4381 22:15:48.148132 DQ0 =52, DQ1 =56, DQ2 =52, DQ3 =52
4382 22:15:48.150884 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =60
4383 22:15:48.154566 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =40
4384 22:15:48.157944 DQ12 =48, DQ13 =56, DQ14 =56, DQ15 =52
4385 22:15:48.158024
4386 22:15:48.158087
4387 22:15:48.167722 [DQSOSCAuto] RK1, (LSB)MR18= 0x6222, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4388 22:15:48.167802 CH0 RK1: MR19=808, MR18=6222
4389 22:15:48.174211 CH0_RK1: MR19=0x808, MR18=0x6222, DQSOSC=391, MR23=63, INC=171, DEC=114
4390 22:15:48.177441 [RxdqsGatingPostProcess] freq 600
4391 22:15:48.184288 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4392 22:15:48.187410 Pre-setting of DQS Precalculation
4393 22:15:48.190860 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4394 22:15:48.190940 ==
4395 22:15:48.194109 Dram Type= 6, Freq= 0, CH_1, rank 0
4396 22:15:48.197416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4397 22:15:48.201438 ==
4398 22:15:48.204066 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4399 22:15:48.211151 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4400 22:15:48.214287 [CA 0] Center 36 (5~67) winsize 63
4401 22:15:48.217730 [CA 1] Center 36 (5~67) winsize 63
4402 22:15:48.221231 [CA 2] Center 34 (4~65) winsize 62
4403 22:15:48.224240 [CA 3] Center 34 (4~65) winsize 62
4404 22:15:48.227505 [CA 4] Center 34 (4~65) winsize 62
4405 22:15:48.231377 [CA 5] Center 33 (3~64) winsize 62
4406 22:15:48.231457
4407 22:15:48.234137 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4408 22:15:48.234216
4409 22:15:48.237737 [CATrainingPosCal] consider 1 rank data
4410 22:15:48.240650 u2DelayCellTimex100 = 270/100 ps
4411 22:15:48.244205 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
4412 22:15:48.247935 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4413 22:15:48.250969 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4414 22:15:48.254010 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4415 22:15:48.260979 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4416 22:15:48.264290 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4417 22:15:48.264370
4418 22:15:48.267372 CA PerBit enable=1, Macro0, CA PI delay=33
4419 22:15:48.267451
4420 22:15:48.271072 [CBTSetCACLKResult] CA Dly = 33
4421 22:15:48.271152 CS Dly: 5 (0~36)
4422 22:15:48.271215 ==
4423 22:15:48.273871 Dram Type= 6, Freq= 0, CH_1, rank 1
4424 22:15:48.281022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4425 22:15:48.281103 ==
4426 22:15:48.283964 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4427 22:15:48.290580 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4428 22:15:48.294120 [CA 0] Center 36 (5~67) winsize 63
4429 22:15:48.297348 [CA 1] Center 36 (5~67) winsize 63
4430 22:15:48.300702 [CA 2] Center 34 (4~65) winsize 62
4431 22:15:48.304055 [CA 3] Center 34 (4~65) winsize 62
4432 22:15:48.307297 [CA 4] Center 34 (4~65) winsize 62
4433 22:15:48.310313 [CA 5] Center 34 (3~65) winsize 63
4434 22:15:48.310393
4435 22:15:48.313724 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4436 22:15:48.313804
4437 22:15:48.317348 [CATrainingPosCal] consider 2 rank data
4438 22:15:48.320507 u2DelayCellTimex100 = 270/100 ps
4439 22:15:48.323951 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
4440 22:15:48.326899 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4441 22:15:48.333925 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4442 22:15:48.337065 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4443 22:15:48.340261 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4444 22:15:48.343587 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4445 22:15:48.343669
4446 22:15:48.347217 CA PerBit enable=1, Macro0, CA PI delay=33
4447 22:15:48.347299
4448 22:15:48.350259 [CBTSetCACLKResult] CA Dly = 33
4449 22:15:48.350368 CS Dly: 5 (0~37)
4450 22:15:48.350441
4451 22:15:48.353833 ----->DramcWriteLeveling(PI) begin...
4452 22:15:48.357299 ==
4453 22:15:48.360251 Dram Type= 6, Freq= 0, CH_1, rank 0
4454 22:15:48.363790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4455 22:15:48.363872 ==
4456 22:15:48.366716 Write leveling (Byte 0): 29 => 29
4457 22:15:48.370332 Write leveling (Byte 1): 30 => 30
4458 22:15:48.373668 DramcWriteLeveling(PI) end<-----
4459 22:15:48.373749
4460 22:15:48.373840 ==
4461 22:15:48.376647 Dram Type= 6, Freq= 0, CH_1, rank 0
4462 22:15:48.380508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4463 22:15:48.380590 ==
4464 22:15:48.383331 [Gating] SW mode calibration
4465 22:15:48.390222 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4466 22:15:48.397000 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4467 22:15:48.399891 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4468 22:15:48.403367 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4469 22:15:48.409883 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4470 22:15:48.413278 0 9 12 | B1->B0 | 2f2f 2d2d | 1 1 | (1 0) (1 1)
4471 22:15:48.416559 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4472 22:15:48.419915 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4473 22:15:48.426564 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4474 22:15:48.430103 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4475 22:15:48.433146 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4476 22:15:48.439789 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4477 22:15:48.443362 0 10 8 | B1->B0 | 2424 2525 | 0 0 | (0 0) (1 1)
4478 22:15:48.446939 0 10 12 | B1->B0 | 3535 3a3a | 1 1 | (0 0) (0 0)
4479 22:15:48.453463 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4480 22:15:48.456443 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4481 22:15:48.459874 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4482 22:15:48.466429 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4483 22:15:48.469950 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4484 22:15:48.472980 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4485 22:15:48.480112 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4486 22:15:48.483227 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4487 22:15:48.486890 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4488 22:15:48.493417 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4489 22:15:48.496293 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4490 22:15:48.499887 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4491 22:15:48.506723 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4492 22:15:48.509577 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4493 22:15:48.512883 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4494 22:15:48.519275 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4495 22:15:48.522714 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4496 22:15:48.526075 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4497 22:15:48.532705 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4498 22:15:48.536341 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4499 22:15:48.539361 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4500 22:15:48.546337 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4501 22:15:48.549273 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4502 22:15:48.552696 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4503 22:15:48.556205 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4504 22:15:48.559321 Total UI for P1: 0, mck2ui 16
4505 22:15:48.562920 best dqsien dly found for B0: ( 0, 13, 10)
4506 22:15:48.566043 Total UI for P1: 0, mck2ui 16
4507 22:15:48.569372 best dqsien dly found for B1: ( 0, 13, 12)
4508 22:15:48.572610 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4509 22:15:48.579161 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4510 22:15:48.579243
4511 22:15:48.582470 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4512 22:15:48.586028 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4513 22:15:48.589263 [Gating] SW calibration Done
4514 22:15:48.589344 ==
4515 22:15:48.592556 Dram Type= 6, Freq= 0, CH_1, rank 0
4516 22:15:48.596070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4517 22:15:48.596152 ==
4518 22:15:48.599139 RX Vref Scan: 0
4519 22:15:48.599220
4520 22:15:48.599286 RX Vref 0 -> 0, step: 1
4521 22:15:48.599346
4522 22:15:48.602440 RX Delay -230 -> 252, step: 16
4523 22:15:48.605891 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4524 22:15:48.612724 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4525 22:15:48.615846 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4526 22:15:48.619381 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4527 22:15:48.622383 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4528 22:15:48.625735 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4529 22:15:48.632347 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4530 22:15:48.635928 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4531 22:15:48.638934 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4532 22:15:48.643046 iDelay=218, Bit 9, Center 41 (-102 ~ 185) 288
4533 22:15:48.649446 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4534 22:15:48.652460 iDelay=218, Bit 11, Center 49 (-102 ~ 201) 304
4535 22:15:48.655879 iDelay=218, Bit 12, Center 65 (-86 ~ 217) 304
4536 22:15:48.659389 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4537 22:15:48.662736 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4538 22:15:48.669138 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4539 22:15:48.669219 ==
4540 22:15:48.672331 Dram Type= 6, Freq= 0, CH_1, rank 0
4541 22:15:48.675609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4542 22:15:48.675691 ==
4543 22:15:48.675757 DQS Delay:
4544 22:15:48.679149 DQS0 = 0, DQS1 = 0
4545 22:15:48.679230 DQM Delay:
4546 22:15:48.682277 DQM0 = 54, DQM1 = 52
4547 22:15:48.682358 DQ Delay:
4548 22:15:48.685710 DQ0 =57, DQ1 =49, DQ2 =49, DQ3 =49
4549 22:15:48.689084 DQ4 =49, DQ5 =65, DQ6 =65, DQ7 =49
4550 22:15:48.692473 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =49
4551 22:15:48.695615 DQ12 =65, DQ13 =57, DQ14 =57, DQ15 =65
4552 22:15:48.695696
4553 22:15:48.695762
4554 22:15:48.695822 ==
4555 22:15:48.698715 Dram Type= 6, Freq= 0, CH_1, rank 0
4556 22:15:48.702246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4557 22:15:48.705735 ==
4558 22:15:48.705816
4559 22:15:48.705881
4560 22:15:48.705941 TX Vref Scan disable
4561 22:15:48.708901 == TX Byte 0 ==
4562 22:15:48.712356 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4563 22:15:48.715690 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4564 22:15:48.718883 == TX Byte 1 ==
4565 22:15:48.722426 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4566 22:15:48.725108 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4567 22:15:48.728646 ==
4568 22:15:48.731941 Dram Type= 6, Freq= 0, CH_1, rank 0
4569 22:15:48.735255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4570 22:15:48.735339 ==
4571 22:15:48.735414
4572 22:15:48.735476
4573 22:15:48.738554 TX Vref Scan disable
4574 22:15:48.738624 == TX Byte 0 ==
4575 22:15:48.745237 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4576 22:15:48.748580 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4577 22:15:48.748683 == TX Byte 1 ==
4578 22:15:48.755189 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4579 22:15:48.758322 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4580 22:15:48.758423
4581 22:15:48.758515 [DATLAT]
4582 22:15:48.761795 Freq=600, CH1 RK0
4583 22:15:48.761868
4584 22:15:48.761937 DATLAT Default: 0x9
4585 22:15:48.765289 0, 0xFFFF, sum = 0
4586 22:15:48.765384 1, 0xFFFF, sum = 0
4587 22:15:48.768283 2, 0xFFFF, sum = 0
4588 22:15:48.768357 3, 0xFFFF, sum = 0
4589 22:15:48.771775 4, 0xFFFF, sum = 0
4590 22:15:48.775073 5, 0xFFFF, sum = 0
4591 22:15:48.775150 6, 0xFFFF, sum = 0
4592 22:15:48.778645 7, 0xFFFF, sum = 0
4593 22:15:48.778719 8, 0x0, sum = 1
4594 22:15:48.778782 9, 0x0, sum = 2
4595 22:15:48.781709 10, 0x0, sum = 3
4596 22:15:48.781781 11, 0x0, sum = 4
4597 22:15:48.785098 best_step = 9
4598 22:15:48.785196
4599 22:15:48.785284 ==
4600 22:15:48.788239 Dram Type= 6, Freq= 0, CH_1, rank 0
4601 22:15:48.791769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4602 22:15:48.791872 ==
4603 22:15:48.795205 RX Vref Scan: 1
4604 22:15:48.795281
4605 22:15:48.795352 RX Vref 0 -> 0, step: 1
4606 22:15:48.795443
4607 22:15:48.798157 RX Delay -163 -> 252, step: 8
4608 22:15:48.798235
4609 22:15:48.801734 Set Vref, RX VrefLevel [Byte0]: 55
4610 22:15:48.804729 [Byte1]: 54
4611 22:15:48.809077
4612 22:15:48.809182 Final RX Vref Byte 0 = 55 to rank0
4613 22:15:48.812907 Final RX Vref Byte 1 = 54 to rank0
4614 22:15:48.815297 Final RX Vref Byte 0 = 55 to rank1
4615 22:15:48.818776 Final RX Vref Byte 1 = 54 to rank1==
4616 22:15:48.822151 Dram Type= 6, Freq= 0, CH_1, rank 0
4617 22:15:48.828978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4618 22:15:48.829079 ==
4619 22:15:48.829182 DQS Delay:
4620 22:15:48.829272 DQS0 = 0, DQS1 = 0
4621 22:15:48.831996 DQM Delay:
4622 22:15:48.832091 DQM0 = 47, DQM1 = 45
4623 22:15:48.835654 DQ Delay:
4624 22:15:48.838844 DQ0 =48, DQ1 =40, DQ2 =36, DQ3 =44
4625 22:15:48.838928 DQ4 =48, DQ5 =56, DQ6 =56, DQ7 =48
4626 22:15:48.842108 DQ8 =36, DQ9 =36, DQ10 =44, DQ11 =36
4627 22:15:48.848529 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4628 22:15:48.848628
4629 22:15:48.848728
4630 22:15:48.855929 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a70, (MSB)MR19= 0x808, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
4631 22:15:48.858543 CH1 RK0: MR19=808, MR18=4A70
4632 22:15:48.865467 CH1_RK0: MR19=0x808, MR18=0x4A70, DQSOSC=388, MR23=63, INC=174, DEC=116
4633 22:15:48.865613
4634 22:15:48.869156 ----->DramcWriteLeveling(PI) begin...
4635 22:15:48.869254 ==
4636 22:15:48.871816 Dram Type= 6, Freq= 0, CH_1, rank 1
4637 22:15:48.875316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4638 22:15:48.875394 ==
4639 22:15:48.879081 Write leveling (Byte 0): 30 => 30
4640 22:15:48.881815 Write leveling (Byte 1): 33 => 33
4641 22:15:48.885197 DramcWriteLeveling(PI) end<-----
4642 22:15:48.885293
4643 22:15:48.885382 ==
4644 22:15:48.888864 Dram Type= 6, Freq= 0, CH_1, rank 1
4645 22:15:48.891749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4646 22:15:48.891850 ==
4647 22:15:48.895523 [Gating] SW mode calibration
4648 22:15:48.902118 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4649 22:15:48.908595 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4650 22:15:48.911586 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4651 22:15:48.915292 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4652 22:15:48.922184 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4653 22:15:48.924881 0 9 12 | B1->B0 | 2b2b 2e2e | 0 0 | (0 0) (0 0)
4654 22:15:48.928226 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4655 22:15:48.934872 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4656 22:15:48.938436 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4657 22:15:48.941488 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4658 22:15:48.948371 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4659 22:15:48.951915 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4660 22:15:48.955100 0 10 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
4661 22:15:48.962037 0 10 12 | B1->B0 | 3838 3636 | 0 0 | (0 0) (1 1)
4662 22:15:48.964871 0 10 16 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
4663 22:15:48.968213 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4664 22:15:48.975068 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4665 22:15:48.978238 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4666 22:15:48.981303 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4667 22:15:48.988319 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4668 22:15:48.991532 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4669 22:15:48.994623 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4670 22:15:49.001374 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4671 22:15:49.004552 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4672 22:15:49.007795 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4673 22:15:49.014495 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4674 22:15:49.018003 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4675 22:15:49.021037 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4676 22:15:49.028028 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4677 22:15:49.031233 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4678 22:15:49.034568 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4679 22:15:49.041475 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4680 22:15:49.044794 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4681 22:15:49.048315 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4682 22:15:49.054498 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4683 22:15:49.057828 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 22:15:49.061110 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4685 22:15:49.064648 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4686 22:15:49.067739 Total UI for P1: 0, mck2ui 16
4687 22:15:49.071457 best dqsien dly found for B0: ( 0, 13, 10)
4688 22:15:49.074797 Total UI for P1: 0, mck2ui 16
4689 22:15:49.078338 best dqsien dly found for B1: ( 0, 13, 10)
4690 22:15:49.081408 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4691 22:15:49.088060 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4692 22:15:49.088159
4693 22:15:49.091061 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4694 22:15:49.094678 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4695 22:15:49.097855 [Gating] SW calibration Done
4696 22:15:49.097937 ==
4697 22:15:49.101052 Dram Type= 6, Freq= 0, CH_1, rank 1
4698 22:15:49.104377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4699 22:15:49.104488 ==
4700 22:15:49.107873 RX Vref Scan: 0
4701 22:15:49.107955
4702 22:15:49.108020 RX Vref 0 -> 0, step: 1
4703 22:15:49.108081
4704 22:15:49.111362 RX Delay -230 -> 252, step: 16
4705 22:15:49.115004 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4706 22:15:49.121475 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4707 22:15:49.124398 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4708 22:15:49.128072 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4709 22:15:49.131562 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4710 22:15:49.134394 iDelay=218, Bit 5, Center 65 (-86 ~ 217) 304
4711 22:15:49.141134 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4712 22:15:49.144719 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4713 22:15:49.147618 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4714 22:15:49.150981 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4715 22:15:49.154336 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4716 22:15:49.161217 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4717 22:15:49.164544 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4718 22:15:49.167479 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4719 22:15:49.171091 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4720 22:15:49.177899 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4721 22:15:49.177981 ==
4722 22:15:49.180977 Dram Type= 6, Freq= 0, CH_1, rank 1
4723 22:15:49.184366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4724 22:15:49.184448 ==
4725 22:15:49.184514 DQS Delay:
4726 22:15:49.188093 DQS0 = 0, DQS1 = 0
4727 22:15:49.188174 DQM Delay:
4728 22:15:49.190979 DQM0 = 49, DQM1 = 48
4729 22:15:49.191061 DQ Delay:
4730 22:15:49.194645 DQ0 =57, DQ1 =41, DQ2 =33, DQ3 =41
4731 22:15:49.197598 DQ4 =41, DQ5 =65, DQ6 =65, DQ7 =49
4732 22:15:49.201450 DQ8 =33, DQ9 =41, DQ10 =49, DQ11 =41
4733 22:15:49.204349 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4734 22:15:49.204438
4735 22:15:49.204504
4736 22:15:49.204564 ==
4737 22:15:49.207532 Dram Type= 6, Freq= 0, CH_1, rank 1
4738 22:15:49.211151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4739 22:15:49.211233 ==
4740 22:15:49.214441
4741 22:15:49.214522
4742 22:15:49.214587 TX Vref Scan disable
4743 22:15:49.217789 == TX Byte 0 ==
4744 22:15:49.220723 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4745 22:15:49.224285 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4746 22:15:49.227188 == TX Byte 1 ==
4747 22:15:49.230985 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4748 22:15:49.233921 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4749 22:15:49.237466 ==
4750 22:15:49.240707 Dram Type= 6, Freq= 0, CH_1, rank 1
4751 22:15:49.244083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4752 22:15:49.244168 ==
4753 22:15:49.244254
4754 22:15:49.244334
4755 22:15:49.246953 TX Vref Scan disable
4756 22:15:49.247040 == TX Byte 0 ==
4757 22:15:49.254110 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4758 22:15:49.257357 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4759 22:15:49.257465 == TX Byte 1 ==
4760 22:15:49.264308 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4761 22:15:49.267212 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4762 22:15:49.267297
4763 22:15:49.267381 [DATLAT]
4764 22:15:49.270589 Freq=600, CH1 RK1
4765 22:15:49.270674
4766 22:15:49.270758 DATLAT Default: 0x9
4767 22:15:49.273631 0, 0xFFFF, sum = 0
4768 22:15:49.273759 1, 0xFFFF, sum = 0
4769 22:15:49.276916 2, 0xFFFF, sum = 0
4770 22:15:49.280851 3, 0xFFFF, sum = 0
4771 22:15:49.280937 4, 0xFFFF, sum = 0
4772 22:15:49.283757 5, 0xFFFF, sum = 0
4773 22:15:49.283844 6, 0xFFFF, sum = 0
4774 22:15:49.286823 7, 0xFFFF, sum = 0
4775 22:15:49.286910 8, 0x0, sum = 1
4776 22:15:49.286996 9, 0x0, sum = 2
4777 22:15:49.290596 10, 0x0, sum = 3
4778 22:15:49.290681 11, 0x0, sum = 4
4779 22:15:49.294005 best_step = 9
4780 22:15:49.294089
4781 22:15:49.294174 ==
4782 22:15:49.297172 Dram Type= 6, Freq= 0, CH_1, rank 1
4783 22:15:49.300096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4784 22:15:49.300182 ==
4785 22:15:49.303681 RX Vref Scan: 0
4786 22:15:49.303765
4787 22:15:49.303850 RX Vref 0 -> 0, step: 1
4788 22:15:49.303929
4789 22:15:49.306916 RX Delay -163 -> 252, step: 8
4790 22:15:49.314002 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4791 22:15:49.317465 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4792 22:15:49.321000 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4793 22:15:49.324168 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4794 22:15:49.327662 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4795 22:15:49.334173 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4796 22:15:49.337326 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4797 22:15:49.341113 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4798 22:15:49.344020 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4799 22:15:49.351181 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4800 22:15:49.354021 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4801 22:15:49.357350 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4802 22:15:49.360826 iDelay=205, Bit 12, Center 56 (-91 ~ 204) 296
4803 22:15:49.364232 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4804 22:15:49.370440 iDelay=205, Bit 14, Center 52 (-91 ~ 196) 288
4805 22:15:49.373758 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4806 22:15:49.373831 ==
4807 22:15:49.377335 Dram Type= 6, Freq= 0, CH_1, rank 1
4808 22:15:49.380629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4809 22:15:49.380703 ==
4810 22:15:49.384050 DQS Delay:
4811 22:15:49.384132 DQS0 = 0, DQS1 = 0
4812 22:15:49.384197 DQM Delay:
4813 22:15:49.387269 DQM0 = 48, DQM1 = 46
4814 22:15:49.387339 DQ Delay:
4815 22:15:49.390521 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4816 22:15:49.394073 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4817 22:15:49.397224 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4818 22:15:49.400670 DQ12 =56, DQ13 =52, DQ14 =52, DQ15 =56
4819 22:15:49.400740
4820 22:15:49.400801
4821 22:15:49.410285 [DQSOSCAuto] RK1, (LSB)MR18= 0x671e, (MSB)MR19= 0x808, tDQSOscB0 = 404 ps tDQSOscB1 = 390 ps
4822 22:15:49.410361 CH1 RK1: MR19=808, MR18=671E
4823 22:15:49.417132 CH1_RK1: MR19=0x808, MR18=0x671E, DQSOSC=390, MR23=63, INC=172, DEC=114
4824 22:15:49.420629 [RxdqsGatingPostProcess] freq 600
4825 22:15:49.427047 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4826 22:15:49.430388 Pre-setting of DQS Precalculation
4827 22:15:49.433785 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4828 22:15:49.440177 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4829 22:15:49.450078 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4830 22:15:49.450161
4831 22:15:49.450226
4832 22:15:49.453391 [Calibration Summary] 1200 Mbps
4833 22:15:49.453479 CH 0, Rank 0
4834 22:15:49.456846 SW Impedance : PASS
4835 22:15:49.456927 DUTY Scan : NO K
4836 22:15:49.460547 ZQ Calibration : PASS
4837 22:15:49.463387 Jitter Meter : NO K
4838 22:15:49.463462 CBT Training : PASS
4839 22:15:49.467025 Write leveling : PASS
4840 22:15:49.467097 RX DQS gating : PASS
4841 22:15:49.470397 RX DQ/DQS(RDDQC) : PASS
4842 22:15:49.473826 TX DQ/DQS : PASS
4843 22:15:49.473899 RX DATLAT : PASS
4844 22:15:49.477421 RX DQ/DQS(Engine): PASS
4845 22:15:49.480240 TX OE : NO K
4846 22:15:49.480317 All Pass.
4847 22:15:49.480378
4848 22:15:49.480436 CH 0, Rank 1
4849 22:15:49.483546 SW Impedance : PASS
4850 22:15:49.487088 DUTY Scan : NO K
4851 22:15:49.487160 ZQ Calibration : PASS
4852 22:15:49.490488 Jitter Meter : NO K
4853 22:15:49.493785 CBT Training : PASS
4854 22:15:49.493860 Write leveling : PASS
4855 22:15:49.497261 RX DQS gating : PASS
4856 22:15:49.500307 RX DQ/DQS(RDDQC) : PASS
4857 22:15:49.500378 TX DQ/DQS : PASS
4858 22:15:49.503936 RX DATLAT : PASS
4859 22:15:49.506764 RX DQ/DQS(Engine): PASS
4860 22:15:49.506835 TX OE : NO K
4861 22:15:49.506897 All Pass.
4862 22:15:49.506956
4863 22:15:49.510082 CH 1, Rank 0
4864 22:15:49.513529 SW Impedance : PASS
4865 22:15:49.513600 DUTY Scan : NO K
4866 22:15:49.516638 ZQ Calibration : PASS
4867 22:15:49.516708 Jitter Meter : NO K
4868 22:15:49.519974 CBT Training : PASS
4869 22:15:49.523823 Write leveling : PASS
4870 22:15:49.523894 RX DQS gating : PASS
4871 22:15:49.526827 RX DQ/DQS(RDDQC) : PASS
4872 22:15:49.530253 TX DQ/DQS : PASS
4873 22:15:49.530337 RX DATLAT : PASS
4874 22:15:49.533426 RX DQ/DQS(Engine): PASS
4875 22:15:49.537128 TX OE : NO K
4876 22:15:49.537198 All Pass.
4877 22:15:49.537266
4878 22:15:49.537324 CH 1, Rank 1
4879 22:15:49.540486 SW Impedance : PASS
4880 22:15:49.544046 DUTY Scan : NO K
4881 22:15:49.544120 ZQ Calibration : PASS
4882 22:15:49.547162 Jitter Meter : NO K
4883 22:15:49.550491 CBT Training : PASS
4884 22:15:49.550568 Write leveling : PASS
4885 22:15:49.553426 RX DQS gating : PASS
4886 22:15:49.556613 RX DQ/DQS(RDDQC) : PASS
4887 22:15:49.556689 TX DQ/DQS : PASS
4888 22:15:49.559954 RX DATLAT : PASS
4889 22:15:49.560033 RX DQ/DQS(Engine): PASS
4890 22:15:49.563198 TX OE : NO K
4891 22:15:49.563277 All Pass.
4892 22:15:49.563341
4893 22:15:49.566716 DramC Write-DBI off
4894 22:15:49.570289 PER_BANK_REFRESH: Hybrid Mode
4895 22:15:49.570361 TX_TRACKING: ON
4896 22:15:49.579923 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4897 22:15:49.583233 [FAST_K] Save calibration result to emmc
4898 22:15:49.586822 dramc_set_vcore_voltage set vcore to 662500
4899 22:15:49.590067 Read voltage for 933, 3
4900 22:15:49.590153 Vio18 = 0
4901 22:15:49.593291 Vcore = 662500
4902 22:15:49.593365 Vdram = 0
4903 22:15:49.593430 Vddq = 0
4904 22:15:49.593491 Vmddr = 0
4905 22:15:49.599617 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4906 22:15:49.606531 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4907 22:15:49.606609 MEM_TYPE=3, freq_sel=17
4908 22:15:49.609505 sv_algorithm_assistance_LP4_1600
4909 22:15:49.612915 ============ PULL DRAM RESETB DOWN ============
4910 22:15:49.619531 ========== PULL DRAM RESETB DOWN end =========
4911 22:15:49.623403 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4912 22:15:49.626250 ===================================
4913 22:15:49.629400 LPDDR4 DRAM CONFIGURATION
4914 22:15:49.632910 ===================================
4915 22:15:49.632977 EX_ROW_EN[0] = 0x0
4916 22:15:49.636395 EX_ROW_EN[1] = 0x0
4917 22:15:49.636470 LP4Y_EN = 0x0
4918 22:15:49.639330 WORK_FSP = 0x0
4919 22:15:49.639403 WL = 0x3
4920 22:15:49.643162 RL = 0x3
4921 22:15:49.643240 BL = 0x2
4922 22:15:49.646066 RPST = 0x0
4923 22:15:49.649443 RD_PRE = 0x0
4924 22:15:49.649518 WR_PRE = 0x1
4925 22:15:49.653160 WR_PST = 0x0
4926 22:15:49.653226 DBI_WR = 0x0
4927 22:15:49.656341 DBI_RD = 0x0
4928 22:15:49.656422 OTF = 0x1
4929 22:15:49.660021 ===================================
4930 22:15:49.663146 ===================================
4931 22:15:49.663220 ANA top config
4932 22:15:49.666100 ===================================
4933 22:15:49.669905 DLL_ASYNC_EN = 0
4934 22:15:49.672760 ALL_SLAVE_EN = 1
4935 22:15:49.676234 NEW_RANK_MODE = 1
4936 22:15:49.679725 DLL_IDLE_MODE = 1
4937 22:15:49.679808 LP45_APHY_COMB_EN = 1
4938 22:15:49.683066 TX_ODT_DIS = 1
4939 22:15:49.685947 NEW_8X_MODE = 1
4940 22:15:49.689714 ===================================
4941 22:15:49.692671 ===================================
4942 22:15:49.696314 data_rate = 1866
4943 22:15:49.699399 CKR = 1
4944 22:15:49.699482 DQ_P2S_RATIO = 8
4945 22:15:49.702693 ===================================
4946 22:15:49.706051 CA_P2S_RATIO = 8
4947 22:15:49.709396 DQ_CA_OPEN = 0
4948 22:15:49.713010 DQ_SEMI_OPEN = 0
4949 22:15:49.716698 CA_SEMI_OPEN = 0
4950 22:15:49.719496 CA_FULL_RATE = 0
4951 22:15:49.719579 DQ_CKDIV4_EN = 1
4952 22:15:49.723043 CA_CKDIV4_EN = 1
4953 22:15:49.726209 CA_PREDIV_EN = 0
4954 22:15:49.729956 PH8_DLY = 0
4955 22:15:49.732959 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4956 22:15:49.733042 DQ_AAMCK_DIV = 4
4957 22:15:49.736084 CA_AAMCK_DIV = 4
4958 22:15:49.739578 CA_ADMCK_DIV = 4
4959 22:15:49.743076 DQ_TRACK_CA_EN = 0
4960 22:15:49.746372 CA_PICK = 933
4961 22:15:49.749751 CA_MCKIO = 933
4962 22:15:49.752684 MCKIO_SEMI = 0
4963 22:15:49.752765 PLL_FREQ = 3732
4964 22:15:49.756274 DQ_UI_PI_RATIO = 32
4965 22:15:49.759174 CA_UI_PI_RATIO = 0
4966 22:15:49.762804 ===================================
4967 22:15:49.766295 ===================================
4968 22:15:49.769212 memory_type:LPDDR4
4969 22:15:49.772667 GP_NUM : 10
4970 22:15:49.772748 SRAM_EN : 1
4971 22:15:49.775855 MD32_EN : 0
4972 22:15:49.779031 ===================================
4973 22:15:49.779113 [ANA_INIT] >>>>>>>>>>>>>>
4974 22:15:49.782942 <<<<<< [CONFIGURE PHASE]: ANA_TX
4975 22:15:49.785945 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4976 22:15:49.789411 ===================================
4977 22:15:49.792656 data_rate = 1866,PCW = 0X8f00
4978 22:15:49.795986 ===================================
4979 22:15:49.799513 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4980 22:15:49.805881 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4981 22:15:49.809793 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4982 22:15:49.815813 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4983 22:15:49.819516 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4984 22:15:49.822649 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4985 22:15:49.825833 [ANA_INIT] flow start
4986 22:15:49.825915 [ANA_INIT] PLL >>>>>>>>
4987 22:15:49.829110 [ANA_INIT] PLL <<<<<<<<
4988 22:15:49.832680 [ANA_INIT] MIDPI >>>>>>>>
4989 22:15:49.832761 [ANA_INIT] MIDPI <<<<<<<<
4990 22:15:49.836221 [ANA_INIT] DLL >>>>>>>>
4991 22:15:49.839251 [ANA_INIT] flow end
4992 22:15:49.842755 ============ LP4 DIFF to SE enter ============
4993 22:15:49.846025 ============ LP4 DIFF to SE exit ============
4994 22:15:49.849006 [ANA_INIT] <<<<<<<<<<<<<
4995 22:15:49.852407 [Flow] Enable top DCM control >>>>>
4996 22:15:49.855766 [Flow] Enable top DCM control <<<<<
4997 22:15:49.859359 Enable DLL master slave shuffle
4998 22:15:49.862179 ==============================================================
4999 22:15:49.865721 Gating Mode config
5000 22:15:49.872049 ==============================================================
5001 22:15:49.872131 Config description:
5002 22:15:49.882353 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5003 22:15:49.888890 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5004 22:15:49.892420 SELPH_MODE 0: By rank 1: By Phase
5005 22:15:49.899013 ==============================================================
5006 22:15:49.902376 GAT_TRACK_EN = 1
5007 22:15:49.905366 RX_GATING_MODE = 2
5008 22:15:49.909150 RX_GATING_TRACK_MODE = 2
5009 22:15:49.911956 SELPH_MODE = 1
5010 22:15:49.915425 PICG_EARLY_EN = 1
5011 22:15:49.918546 VALID_LAT_VALUE = 1
5012 22:15:49.922079 ==============================================================
5013 22:15:49.925281 Enter into Gating configuration >>>>
5014 22:15:49.928899 Exit from Gating configuration <<<<
5015 22:15:49.931812 Enter into DVFS_PRE_config >>>>>
5016 22:15:49.942306 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5017 22:15:49.945869 Exit from DVFS_PRE_config <<<<<
5018 22:15:49.948604 Enter into PICG configuration >>>>
5019 22:15:49.952160 Exit from PICG configuration <<<<
5020 22:15:49.955220 [RX_INPUT] configuration >>>>>
5021 22:15:49.958683 [RX_INPUT] configuration <<<<<
5022 22:15:49.965229 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5023 22:15:49.968811 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5024 22:15:49.975510 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5025 22:15:49.982009 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5026 22:15:49.988642 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5027 22:15:49.994985 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5028 22:15:49.998778 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5029 22:15:50.001899 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5030 22:15:50.004909 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5031 22:15:50.011686 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5032 22:15:50.015256 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5033 22:15:50.018622 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5034 22:15:50.021834 ===================================
5035 22:15:50.025371 LPDDR4 DRAM CONFIGURATION
5036 22:15:50.028709 ===================================
5037 22:15:50.028791 EX_ROW_EN[0] = 0x0
5038 22:15:50.031598 EX_ROW_EN[1] = 0x0
5039 22:15:50.034976 LP4Y_EN = 0x0
5040 22:15:50.035058 WORK_FSP = 0x0
5041 22:15:50.038573 WL = 0x3
5042 22:15:50.038655 RL = 0x3
5043 22:15:50.041685 BL = 0x2
5044 22:15:50.041767 RPST = 0x0
5045 22:15:50.044900 RD_PRE = 0x0
5046 22:15:50.044981 WR_PRE = 0x1
5047 22:15:50.048285 WR_PST = 0x0
5048 22:15:50.048366 DBI_WR = 0x0
5049 22:15:50.051692 DBI_RD = 0x0
5050 22:15:50.051774 OTF = 0x1
5051 22:15:50.055244 ===================================
5052 22:15:50.058159 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5053 22:15:50.064722 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5054 22:15:50.068377 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5055 22:15:50.071584 ===================================
5056 22:15:50.074855 LPDDR4 DRAM CONFIGURATION
5057 22:15:50.078009 ===================================
5058 22:15:50.078091 EX_ROW_EN[0] = 0x10
5059 22:15:50.081249 EX_ROW_EN[1] = 0x0
5060 22:15:50.081330 LP4Y_EN = 0x0
5061 22:15:50.084814 WORK_FSP = 0x0
5062 22:15:50.084895 WL = 0x3
5063 22:15:50.088249 RL = 0x3
5064 22:15:50.091331 BL = 0x2
5065 22:15:50.091438 RPST = 0x0
5066 22:15:50.094930 RD_PRE = 0x0
5067 22:15:50.095012 WR_PRE = 0x1
5068 22:15:50.097851 WR_PST = 0x0
5069 22:15:50.097933 DBI_WR = 0x0
5070 22:15:50.101490 DBI_RD = 0x0
5071 22:15:50.101579 OTF = 0x1
5072 22:15:50.104518 ===================================
5073 22:15:50.111454 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5074 22:15:50.115210 nWR fixed to 30
5075 22:15:50.118454 [ModeRegInit_LP4] CH0 RK0
5076 22:15:50.118548 [ModeRegInit_LP4] CH0 RK1
5077 22:15:50.121878 [ModeRegInit_LP4] CH1 RK0
5078 22:15:50.125063 [ModeRegInit_LP4] CH1 RK1
5079 22:15:50.125145 match AC timing 9
5080 22:15:50.131701 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5081 22:15:50.135376 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5082 22:15:50.138719 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5083 22:15:50.145024 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5084 22:15:50.148576 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5085 22:15:50.148659 ==
5086 22:15:50.151721 Dram Type= 6, Freq= 0, CH_0, rank 0
5087 22:15:50.155054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5088 22:15:50.155137 ==
5089 22:15:50.161457 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5090 22:15:50.168256 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5091 22:15:50.171478 [CA 0] Center 37 (6~68) winsize 63
5092 22:15:50.175067 [CA 1] Center 37 (7~68) winsize 62
5093 22:15:50.178409 [CA 2] Center 34 (4~65) winsize 62
5094 22:15:50.181940 [CA 3] Center 34 (3~65) winsize 63
5095 22:15:50.184859 [CA 4] Center 33 (3~64) winsize 62
5096 22:15:50.188511 [CA 5] Center 32 (2~62) winsize 61
5097 22:15:50.188593
5098 22:15:50.191604 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5099 22:15:50.191686
5100 22:15:50.195214 [CATrainingPosCal] consider 1 rank data
5101 22:15:50.198259 u2DelayCellTimex100 = 270/100 ps
5102 22:15:50.201870 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5103 22:15:50.205264 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5104 22:15:50.208338 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5105 22:15:50.211854 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5106 22:15:50.215114 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5107 22:15:50.218273 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5108 22:15:50.221949
5109 22:15:50.225190 CA PerBit enable=1, Macro0, CA PI delay=32
5110 22:15:50.225271
5111 22:15:50.228113 [CBTSetCACLKResult] CA Dly = 32
5112 22:15:50.228194 CS Dly: 5 (0~36)
5113 22:15:50.228259 ==
5114 22:15:50.231436 Dram Type= 6, Freq= 0, CH_0, rank 1
5115 22:15:50.234829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5116 22:15:50.234911 ==
5117 22:15:50.241882 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5118 22:15:50.248020 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5119 22:15:50.251444 [CA 0] Center 37 (6~68) winsize 63
5120 22:15:50.255136 [CA 1] Center 37 (7~68) winsize 62
5121 22:15:50.258055 [CA 2] Center 34 (4~65) winsize 62
5122 22:15:50.261532 [CA 3] Center 34 (4~65) winsize 62
5123 22:15:50.264590 [CA 4] Center 32 (2~63) winsize 62
5124 22:15:50.268239 [CA 5] Center 32 (2~62) winsize 61
5125 22:15:50.268320
5126 22:15:50.271984 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5127 22:15:50.272066
5128 22:15:50.274821 [CATrainingPosCal] consider 2 rank data
5129 22:15:50.278412 u2DelayCellTimex100 = 270/100 ps
5130 22:15:50.281434 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5131 22:15:50.285064 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5132 22:15:50.287986 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5133 22:15:50.291163 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5134 22:15:50.294873 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5135 22:15:50.301374 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5136 22:15:50.301457
5137 22:15:50.304989 CA PerBit enable=1, Macro0, CA PI delay=32
5138 22:15:50.305072
5139 22:15:50.308226 [CBTSetCACLKResult] CA Dly = 32
5140 22:15:50.308310 CS Dly: 5 (0~37)
5141 22:15:50.308383
5142 22:15:50.311482 ----->DramcWriteLeveling(PI) begin...
5143 22:15:50.311557 ==
5144 22:15:50.315161 Dram Type= 6, Freq= 0, CH_0, rank 0
5145 22:15:50.318147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5146 22:15:50.321204 ==
5147 22:15:50.321280 Write leveling (Byte 0): 33 => 33
5148 22:15:50.324984 Write leveling (Byte 1): 29 => 29
5149 22:15:50.328007 DramcWriteLeveling(PI) end<-----
5150 22:15:50.328081
5151 22:15:50.328153 ==
5152 22:15:50.331256 Dram Type= 6, Freq= 0, CH_0, rank 0
5153 22:15:50.337926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5154 22:15:50.338028 ==
5155 22:15:50.338124 [Gating] SW mode calibration
5156 22:15:50.348048 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5157 22:15:50.351478 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5158 22:15:50.358149 0 14 0 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
5159 22:15:50.361151 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5160 22:15:50.364875 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5161 22:15:50.371001 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5162 22:15:50.374548 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5163 22:15:50.378078 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5164 22:15:50.381410 0 14 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 0)
5165 22:15:50.388028 0 14 28 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 1)
5166 22:15:50.391421 0 15 0 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
5167 22:15:50.394451 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5168 22:15:50.401013 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5169 22:15:50.404213 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5170 22:15:50.407673 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5171 22:15:50.414459 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5172 22:15:50.418113 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5173 22:15:50.421130 0 15 28 | B1->B0 | 2a2a 3b3b | 0 0 | (0 0) (0 0)
5174 22:15:50.428110 1 0 0 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
5175 22:15:50.431058 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5176 22:15:50.434068 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5177 22:15:50.441310 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5178 22:15:50.444202 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5179 22:15:50.447429 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5180 22:15:50.454193 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5181 22:15:50.457708 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5182 22:15:50.460913 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5183 22:15:50.467693 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5184 22:15:50.470748 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5185 22:15:50.474732 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5186 22:15:50.480776 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5187 22:15:50.484447 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5188 22:15:50.487487 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5189 22:15:50.494349 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5190 22:15:50.497500 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5191 22:15:50.500443 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5192 22:15:50.507323 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5193 22:15:50.510686 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5194 22:15:50.514051 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5195 22:15:50.521009 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5196 22:15:50.523863 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5197 22:15:50.527109 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5198 22:15:50.531014 Total UI for P1: 0, mck2ui 16
5199 22:15:50.533852 best dqsien dly found for B0: ( 1, 2, 24)
5200 22:15:50.537454 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5201 22:15:50.543816 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5202 22:15:50.547120 Total UI for P1: 0, mck2ui 16
5203 22:15:50.550399 best dqsien dly found for B1: ( 1, 2, 30)
5204 22:15:50.553689 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5205 22:15:50.556872 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5206 22:15:50.556955
5207 22:15:50.560230 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5208 22:15:50.563804 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5209 22:15:50.567053 [Gating] SW calibration Done
5210 22:15:50.567135 ==
5211 22:15:50.570534 Dram Type= 6, Freq= 0, CH_0, rank 0
5212 22:15:50.573762 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5213 22:15:50.573845 ==
5214 22:15:50.577014 RX Vref Scan: 0
5215 22:15:50.577136
5216 22:15:50.580517 RX Vref 0 -> 0, step: 1
5217 22:15:50.580599
5218 22:15:50.580665 RX Delay -80 -> 252, step: 8
5219 22:15:50.586705 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5220 22:15:50.590473 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5221 22:15:50.593319 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5222 22:15:50.597018 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5223 22:15:50.600528 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5224 22:15:50.603580 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5225 22:15:50.610468 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5226 22:15:50.613681 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5227 22:15:50.617118 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5228 22:15:50.619932 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5229 22:15:50.623287 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5230 22:15:50.627090 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5231 22:15:50.633667 iDelay=208, Bit 12, Center 103 (16 ~ 191) 176
5232 22:15:50.637260 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5233 22:15:50.640154 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5234 22:15:50.643403 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5235 22:15:50.643484 ==
5236 22:15:50.646979 Dram Type= 6, Freq= 0, CH_0, rank 0
5237 22:15:50.653545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5238 22:15:50.653641 ==
5239 22:15:50.653707 DQS Delay:
5240 22:15:50.656969 DQS0 = 0, DQS1 = 0
5241 22:15:50.657049 DQM Delay:
5242 22:15:50.657122 DQM0 = 104, DQM1 = 96
5243 22:15:50.660553 DQ Delay:
5244 22:15:50.664098 DQ0 =107, DQ1 =107, DQ2 =99, DQ3 =99
5245 22:15:50.666802 DQ4 =107, DQ5 =91, DQ6 =111, DQ7 =115
5246 22:15:50.669995 DQ8 =87, DQ9 =83, DQ10 =95, DQ11 =91
5247 22:15:50.673365 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5248 22:15:50.673472
5249 22:15:50.673586
5250 22:15:50.673648 ==
5251 22:15:50.676618 Dram Type= 6, Freq= 0, CH_0, rank 0
5252 22:15:50.680085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5253 22:15:50.680167 ==
5254 22:15:50.680232
5255 22:15:50.680292
5256 22:15:50.683733 TX Vref Scan disable
5257 22:15:50.686930 == TX Byte 0 ==
5258 22:15:50.690068 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5259 22:15:50.693765 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5260 22:15:50.696879 == TX Byte 1 ==
5261 22:15:50.699906 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5262 22:15:50.703730 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5263 22:15:50.703813 ==
5264 22:15:50.706598 Dram Type= 6, Freq= 0, CH_0, rank 0
5265 22:15:50.713309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5266 22:15:50.713422 ==
5267 22:15:50.713528
5268 22:15:50.713634
5269 22:15:50.713724 TX Vref Scan disable
5270 22:15:50.717254 == TX Byte 0 ==
5271 22:15:50.720640 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5272 22:15:50.727633 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5273 22:15:50.727716 == TX Byte 1 ==
5274 22:15:50.730926 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5275 22:15:50.737290 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5276 22:15:50.737373
5277 22:15:50.737458 [DATLAT]
5278 22:15:50.737578 Freq=933, CH0 RK0
5279 22:15:50.737673
5280 22:15:50.740925 DATLAT Default: 0xd
5281 22:15:50.741007 0, 0xFFFF, sum = 0
5282 22:15:50.743994 1, 0xFFFF, sum = 0
5283 22:15:50.744078 2, 0xFFFF, sum = 0
5284 22:15:50.747790 3, 0xFFFF, sum = 0
5285 22:15:50.750553 4, 0xFFFF, sum = 0
5286 22:15:50.750636 5, 0xFFFF, sum = 0
5287 22:15:50.753998 6, 0xFFFF, sum = 0
5288 22:15:50.754109 7, 0xFFFF, sum = 0
5289 22:15:50.757428 8, 0xFFFF, sum = 0
5290 22:15:50.757521 9, 0xFFFF, sum = 0
5291 22:15:50.760434 10, 0x0, sum = 1
5292 22:15:50.760518 11, 0x0, sum = 2
5293 22:15:50.760586 12, 0x0, sum = 3
5294 22:15:50.763914 13, 0x0, sum = 4
5295 22:15:50.763997 best_step = 11
5296 22:15:50.764064
5297 22:15:50.767219 ==
5298 22:15:50.770597 Dram Type= 6, Freq= 0, CH_0, rank 0
5299 22:15:50.773454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5300 22:15:50.773559 ==
5301 22:15:50.773626 RX Vref Scan: 1
5302 22:15:50.773688
5303 22:15:50.776745 RX Vref 0 -> 0, step: 1
5304 22:15:50.776827
5305 22:15:50.780420 RX Delay -53 -> 252, step: 4
5306 22:15:50.780503
5307 22:15:50.783847 Set Vref, RX VrefLevel [Byte0]: 56
5308 22:15:50.786731 [Byte1]: 48
5309 22:15:50.786814
5310 22:15:50.790493 Final RX Vref Byte 0 = 56 to rank0
5311 22:15:50.793341 Final RX Vref Byte 1 = 48 to rank0
5312 22:15:50.796812 Final RX Vref Byte 0 = 56 to rank1
5313 22:15:50.800554 Final RX Vref Byte 1 = 48 to rank1==
5314 22:15:50.803533 Dram Type= 6, Freq= 0, CH_0, rank 0
5315 22:15:50.806432 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5316 22:15:50.809824 ==
5317 22:15:50.809906 DQS Delay:
5318 22:15:50.809971 DQS0 = 0, DQS1 = 0
5319 22:15:50.813291 DQM Delay:
5320 22:15:50.813373 DQM0 = 104, DQM1 = 95
5321 22:15:50.816433 DQ Delay:
5322 22:15:50.819862 DQ0 =104, DQ1 =106, DQ2 =100, DQ3 =102
5323 22:15:50.823045 DQ4 =106, DQ5 =96, DQ6 =112, DQ7 =110
5324 22:15:50.826706 DQ8 =84, DQ9 =86, DQ10 =98, DQ11 =90
5325 22:15:50.829949 DQ12 =100, DQ13 =98, DQ14 =106, DQ15 =102
5326 22:15:50.830032
5327 22:15:50.830097
5328 22:15:50.836313 [DQSOSCAuto] RK0, (LSB)MR18= 0x332b, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 405 ps
5329 22:15:50.839751 CH0 RK0: MR19=505, MR18=332B
5330 22:15:50.846682 CH0_RK0: MR19=0x505, MR18=0x332B, DQSOSC=405, MR23=63, INC=66, DEC=44
5331 22:15:50.846768
5332 22:15:50.849724 ----->DramcWriteLeveling(PI) begin...
5333 22:15:50.849807 ==
5334 22:15:50.853162 Dram Type= 6, Freq= 0, CH_0, rank 1
5335 22:15:50.856207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5336 22:15:50.856290 ==
5337 22:15:50.859486 Write leveling (Byte 0): 36 => 36
5338 22:15:50.863029 Write leveling (Byte 1): 29 => 29
5339 22:15:50.866231 DramcWriteLeveling(PI) end<-----
5340 22:15:50.866339
5341 22:15:50.866426 ==
5342 22:15:50.869666 Dram Type= 6, Freq= 0, CH_0, rank 1
5343 22:15:50.873184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5344 22:15:50.876553 ==
5345 22:15:50.876637 [Gating] SW mode calibration
5346 22:15:50.886218 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5347 22:15:50.889445 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5348 22:15:50.892928 0 14 0 | B1->B0 | 3434 2e2e | 1 1 | (0 0) (1 1)
5349 22:15:50.899975 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5350 22:15:50.903006 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5351 22:15:50.906031 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5352 22:15:50.913080 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5353 22:15:50.915959 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5354 22:15:50.919223 0 14 24 | B1->B0 | 3333 3434 | 1 0 | (1 1) (0 0)
5355 22:15:50.925800 0 14 28 | B1->B0 | 2d2d 2d2d | 0 0 | (1 0) (1 0)
5356 22:15:50.929107 0 15 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 0)
5357 22:15:50.932743 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5358 22:15:50.939017 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5359 22:15:50.942317 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5360 22:15:50.945854 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5361 22:15:50.952612 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5362 22:15:50.955564 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5363 22:15:50.959416 0 15 28 | B1->B0 | 3939 3535 | 0 0 | (1 1) (0 0)
5364 22:15:50.965878 1 0 0 | B1->B0 | 4545 4141 | 0 0 | (0 0) (0 0)
5365 22:15:50.968960 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5366 22:15:50.972022 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5367 22:15:50.978986 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5368 22:15:50.982341 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5369 22:15:50.985408 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5370 22:15:50.992149 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5371 22:15:50.995909 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5372 22:15:50.998666 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5373 22:15:51.005458 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5374 22:15:51.008905 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5375 22:15:51.012605 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5376 22:15:51.015526 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5377 22:15:51.021958 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5378 22:15:51.025823 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5379 22:15:51.028840 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5380 22:15:51.035723 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5381 22:15:51.038989 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5382 22:15:51.042046 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5383 22:15:51.048744 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5384 22:15:51.052270 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5385 22:15:51.055252 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5386 22:15:51.061903 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 22:15:51.065398 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 22:15:51.069054 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5389 22:15:51.071955 Total UI for P1: 0, mck2ui 16
5390 22:15:51.075422 best dqsien dly found for B1: ( 1, 2, 30)
5391 22:15:51.082096 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5392 22:15:51.082174 Total UI for P1: 0, mck2ui 16
5393 22:15:51.088949 best dqsien dly found for B0: ( 1, 3, 0)
5394 22:15:51.092032 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5395 22:15:51.095059 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5396 22:15:51.095137
5397 22:15:51.098886 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5398 22:15:51.101809 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5399 22:15:51.105021 [Gating] SW calibration Done
5400 22:15:51.105094 ==
5401 22:15:51.108739 Dram Type= 6, Freq= 0, CH_0, rank 1
5402 22:15:51.111555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5403 22:15:51.111633 ==
5404 22:15:51.115410 RX Vref Scan: 0
5405 22:15:51.115480
5406 22:15:51.115540 RX Vref 0 -> 0, step: 1
5407 22:15:51.115598
5408 22:15:51.118749 RX Delay -80 -> 252, step: 8
5409 22:15:51.121560 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5410 22:15:51.128458 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5411 22:15:51.131720 iDelay=208, Bit 2, Center 103 (8 ~ 199) 192
5412 22:15:51.135293 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5413 22:15:51.138256 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5414 22:15:51.141740 iDelay=208, Bit 5, Center 99 (8 ~ 191) 184
5415 22:15:51.145144 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5416 22:15:51.151612 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5417 22:15:51.155291 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5418 22:15:51.158315 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5419 22:15:51.162197 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5420 22:15:51.164695 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5421 22:15:51.171294 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5422 22:15:51.174824 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5423 22:15:51.177957 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5424 22:15:51.181185 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5425 22:15:51.181261 ==
5426 22:15:51.184728 Dram Type= 6, Freq= 0, CH_0, rank 1
5427 22:15:51.188504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5428 22:15:51.188575 ==
5429 22:15:51.191424 DQS Delay:
5430 22:15:51.191500 DQS0 = 0, DQS1 = 0
5431 22:15:51.194395 DQM Delay:
5432 22:15:51.194469 DQM0 = 105, DQM1 = 93
5433 22:15:51.194530 DQ Delay:
5434 22:15:51.198190 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =99
5435 22:15:51.201407 DQ4 =107, DQ5 =99, DQ6 =111, DQ7 =115
5436 22:15:51.204484 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5437 22:15:51.211069 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =99
5438 22:15:51.211150
5439 22:15:51.211215
5440 22:15:51.211275 ==
5441 22:15:51.214732 Dram Type= 6, Freq= 0, CH_0, rank 1
5442 22:15:51.218000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5443 22:15:51.218078 ==
5444 22:15:51.218144
5445 22:15:51.218205
5446 22:15:51.221337 TX Vref Scan disable
5447 22:15:51.221411 == TX Byte 0 ==
5448 22:15:51.227526 Update DQ dly =721 (2 ,6, 17) DQ OEN =(2 ,3)
5449 22:15:51.231258 Update DQM dly =721 (2 ,6, 17) DQM OEN =(2 ,3)
5450 22:15:51.231336 == TX Byte 1 ==
5451 22:15:51.237557 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5452 22:15:51.241233 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5453 22:15:51.241312 ==
5454 22:15:51.244632 Dram Type= 6, Freq= 0, CH_0, rank 1
5455 22:15:51.247659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5456 22:15:51.247738 ==
5457 22:15:51.247804
5458 22:15:51.247863
5459 22:15:51.251284 TX Vref Scan disable
5460 22:15:51.254348 == TX Byte 0 ==
5461 22:15:51.257810 Update DQ dly =720 (2 ,6, 16) DQ OEN =(2 ,3)
5462 22:15:51.260892 Update DQM dly =720 (2 ,6, 16) DQM OEN =(2 ,3)
5463 22:15:51.264475 == TX Byte 1 ==
5464 22:15:51.267927 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5465 22:15:51.270967 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5466 22:15:51.271045
5467 22:15:51.274749 [DATLAT]
5468 22:15:51.274821 Freq=933, CH0 RK1
5469 22:15:51.274884
5470 22:15:51.277632 DATLAT Default: 0xb
5471 22:15:51.277704 0, 0xFFFF, sum = 0
5472 22:15:51.281438 1, 0xFFFF, sum = 0
5473 22:15:51.281575 2, 0xFFFF, sum = 0
5474 22:15:51.284200 3, 0xFFFF, sum = 0
5475 22:15:51.284276 4, 0xFFFF, sum = 0
5476 22:15:51.288226 5, 0xFFFF, sum = 0
5477 22:15:51.288301 6, 0xFFFF, sum = 0
5478 22:15:51.291084 7, 0xFFFF, sum = 0
5479 22:15:51.291157 8, 0xFFFF, sum = 0
5480 22:15:51.294205 9, 0xFFFF, sum = 0
5481 22:15:51.294286 10, 0x0, sum = 1
5482 22:15:51.297803 11, 0x0, sum = 2
5483 22:15:51.297883 12, 0x0, sum = 3
5484 22:15:51.301005 13, 0x0, sum = 4
5485 22:15:51.301078 best_step = 11
5486 22:15:51.301141
5487 22:15:51.301199 ==
5488 22:15:51.304321 Dram Type= 6, Freq= 0, CH_0, rank 1
5489 22:15:51.310754 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5490 22:15:51.310833 ==
5491 22:15:51.310898 RX Vref Scan: 0
5492 22:15:51.310959
5493 22:15:51.314106 RX Vref 0 -> 0, step: 1
5494 22:15:51.314183
5495 22:15:51.317695 RX Delay -53 -> 252, step: 4
5496 22:15:51.320504 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5497 22:15:51.327218 iDelay=199, Bit 1, Center 108 (23 ~ 194) 172
5498 22:15:51.330865 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5499 22:15:51.334321 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5500 22:15:51.337502 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5501 22:15:51.340628 iDelay=199, Bit 5, Center 96 (7 ~ 186) 180
5502 22:15:51.344034 iDelay=199, Bit 6, Center 108 (23 ~ 194) 172
5503 22:15:51.350736 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5504 22:15:51.354015 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5505 22:15:51.357096 iDelay=199, Bit 9, Center 82 (-1 ~ 166) 168
5506 22:15:51.360631 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5507 22:15:51.363747 iDelay=199, Bit 11, Center 88 (7 ~ 170) 164
5508 22:15:51.370510 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5509 22:15:51.374125 iDelay=199, Bit 13, Center 98 (15 ~ 182) 168
5510 22:15:51.377019 iDelay=199, Bit 14, Center 102 (19 ~ 186) 168
5511 22:15:51.380616 iDelay=199, Bit 15, Center 102 (19 ~ 186) 168
5512 22:15:51.380699 ==
5513 22:15:51.384408 Dram Type= 6, Freq= 0, CH_0, rank 1
5514 22:15:51.390694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5515 22:15:51.390777 ==
5516 22:15:51.390842 DQS Delay:
5517 22:15:51.390903 DQS0 = 0, DQS1 = 0
5518 22:15:51.394157 DQM Delay:
5519 22:15:51.394239 DQM0 = 104, DQM1 = 93
5520 22:15:51.397191 DQ Delay:
5521 22:15:51.400291 DQ0 =102, DQ1 =108, DQ2 =102, DQ3 =102
5522 22:15:51.403941 DQ4 =106, DQ5 =96, DQ6 =108, DQ7 =112
5523 22:15:51.407604 DQ8 =84, DQ9 =82, DQ10 =94, DQ11 =88
5524 22:15:51.410541 DQ12 =100, DQ13 =98, DQ14 =102, DQ15 =102
5525 22:15:51.410624
5526 22:15:51.410689
5527 22:15:51.417156 [DQSOSCAuto] RK1, (LSB)MR18= 0x2a02, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 408 ps
5528 22:15:51.420504 CH0 RK1: MR19=505, MR18=2A02
5529 22:15:51.427004 CH0_RK1: MR19=0x505, MR18=0x2A02, DQSOSC=408, MR23=63, INC=65, DEC=43
5530 22:15:51.430929 [RxdqsGatingPostProcess] freq 933
5531 22:15:51.437369 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5532 22:15:51.437451 best DQS0 dly(2T, 0.5T) = (0, 10)
5533 22:15:51.440166 best DQS1 dly(2T, 0.5T) = (0, 10)
5534 22:15:51.443923 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5535 22:15:51.446796 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5536 22:15:51.450570 best DQS0 dly(2T, 0.5T) = (0, 11)
5537 22:15:51.453622 best DQS1 dly(2T, 0.5T) = (0, 10)
5538 22:15:51.456893 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5539 22:15:51.460127 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5540 22:15:51.463645 Pre-setting of DQS Precalculation
5541 22:15:51.470603 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5542 22:15:51.470686 ==
5543 22:15:51.473845 Dram Type= 6, Freq= 0, CH_1, rank 0
5544 22:15:51.476886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5545 22:15:51.476970 ==
5546 22:15:51.480471 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5547 22:15:51.487065 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5548 22:15:51.490665 [CA 0] Center 36 (6~67) winsize 62
5549 22:15:51.493734 [CA 1] Center 37 (6~68) winsize 63
5550 22:15:51.497274 [CA 2] Center 34 (4~65) winsize 62
5551 22:15:51.501043 [CA 3] Center 34 (4~65) winsize 62
5552 22:15:51.503970 [CA 4] Center 34 (4~65) winsize 62
5553 22:15:51.506898 [CA 5] Center 33 (3~64) winsize 62
5554 22:15:51.506980
5555 22:15:51.510606 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5556 22:15:51.510688
5557 22:15:51.513995 [CATrainingPosCal] consider 1 rank data
5558 22:15:51.517282 u2DelayCellTimex100 = 270/100 ps
5559 22:15:51.520283 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5560 22:15:51.524290 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5561 22:15:51.530948 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5562 22:15:51.534000 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5563 22:15:51.537434 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5564 22:15:51.540612 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5565 22:15:51.540710
5566 22:15:51.543927 CA PerBit enable=1, Macro0, CA PI delay=33
5567 22:15:51.544010
5568 22:15:51.547405 [CBTSetCACLKResult] CA Dly = 33
5569 22:15:51.547488 CS Dly: 6 (0~37)
5570 22:15:51.550536 ==
5571 22:15:51.550619 Dram Type= 6, Freq= 0, CH_1, rank 1
5572 22:15:51.557434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5573 22:15:51.557538 ==
5574 22:15:51.560476 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5575 22:15:51.567498 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5576 22:15:51.570861 [CA 0] Center 36 (6~67) winsize 62
5577 22:15:51.573837 [CA 1] Center 37 (7~67) winsize 61
5578 22:15:51.577268 [CA 2] Center 35 (5~65) winsize 61
5579 22:15:51.580637 [CA 3] Center 34 (4~65) winsize 62
5580 22:15:51.584115 [CA 4] Center 34 (4~65) winsize 62
5581 22:15:51.587658 [CA 5] Center 34 (4~64) winsize 61
5582 22:15:51.587740
5583 22:15:51.590735 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5584 22:15:51.590819
5585 22:15:51.594271 [CATrainingPosCal] consider 2 rank data
5586 22:15:51.597428 u2DelayCellTimex100 = 270/100 ps
5587 22:15:51.600837 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5588 22:15:51.603904 CA1 delay=37 (7~67),Diff = 3 PI (18 cell)
5589 22:15:51.610669 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5590 22:15:51.613620 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5591 22:15:51.617249 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5592 22:15:51.620409 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5593 22:15:51.620496
5594 22:15:51.623913 CA PerBit enable=1, Macro0, CA PI delay=34
5595 22:15:51.623995
5596 22:15:51.627014 [CBTSetCACLKResult] CA Dly = 34
5597 22:15:51.627096 CS Dly: 7 (0~39)
5598 22:15:51.627162
5599 22:15:51.630529 ----->DramcWriteLeveling(PI) begin...
5600 22:15:51.634039 ==
5601 22:15:51.637139 Dram Type= 6, Freq= 0, CH_1, rank 0
5602 22:15:51.640787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5603 22:15:51.640871 ==
5604 22:15:51.643593 Write leveling (Byte 0): 26 => 26
5605 22:15:51.647013 Write leveling (Byte 1): 28 => 28
5606 22:15:51.650225 DramcWriteLeveling(PI) end<-----
5607 22:15:51.650307
5608 22:15:51.650372 ==
5609 22:15:51.653808 Dram Type= 6, Freq= 0, CH_1, rank 0
5610 22:15:51.657046 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5611 22:15:51.657128 ==
5612 22:15:51.660391 [Gating] SW mode calibration
5613 22:15:51.667052 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5614 22:15:51.670466 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5615 22:15:51.676957 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5616 22:15:51.680440 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5617 22:15:51.683663 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5618 22:15:51.690470 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5619 22:15:51.693483 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5620 22:15:51.697029 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5621 22:15:51.703980 0 14 24 | B1->B0 | 3333 2f2f | 0 0 | (0 1) (0 0)
5622 22:15:51.706816 0 14 28 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5623 22:15:51.710635 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5624 22:15:51.717212 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5625 22:15:51.720226 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5626 22:15:51.723983 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5627 22:15:51.730015 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5628 22:15:51.733456 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5629 22:15:51.737064 0 15 24 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
5630 22:15:51.743515 0 15 28 | B1->B0 | 3737 4646 | 1 0 | (0 0) (0 0)
5631 22:15:51.746573 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5632 22:15:51.749915 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5633 22:15:51.756851 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5634 22:15:51.760118 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5635 22:15:51.763496 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5636 22:15:51.769916 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5637 22:15:51.773264 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5638 22:15:51.776869 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5639 22:15:51.783279 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5640 22:15:51.786556 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5641 22:15:51.789847 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5642 22:15:51.796840 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5643 22:15:51.799976 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5644 22:15:51.803241 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5645 22:15:51.809814 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5646 22:15:51.813055 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5647 22:15:51.816657 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5648 22:15:51.820164 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5649 22:15:51.826334 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5650 22:15:51.829914 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5651 22:15:51.833022 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 22:15:51.840268 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 22:15:51.843199 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5654 22:15:51.846781 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5655 22:15:51.849603 Total UI for P1: 0, mck2ui 16
5656 22:15:51.852913 best dqsien dly found for B0: ( 1, 2, 24)
5657 22:15:51.856283 Total UI for P1: 0, mck2ui 16
5658 22:15:51.859517 best dqsien dly found for B1: ( 1, 2, 26)
5659 22:15:51.862924 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5660 22:15:51.866215 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5661 22:15:51.866297
5662 22:15:51.873111 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5663 22:15:51.876305 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5664 22:15:51.879461 [Gating] SW calibration Done
5665 22:15:51.879543 ==
5666 22:15:51.883150 Dram Type= 6, Freq= 0, CH_1, rank 0
5667 22:15:51.886335 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5668 22:15:51.886443 ==
5669 22:15:51.886541 RX Vref Scan: 0
5670 22:15:51.886604
5671 22:15:51.889854 RX Vref 0 -> 0, step: 1
5672 22:15:51.889936
5673 22:15:51.893061 RX Delay -80 -> 252, step: 8
5674 22:15:51.896664 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5675 22:15:51.900229 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5676 22:15:51.903104 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5677 22:15:51.909772 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5678 22:15:51.913074 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5679 22:15:51.916271 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5680 22:15:51.919588 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5681 22:15:51.923159 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5682 22:15:51.926068 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5683 22:15:51.933066 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5684 22:15:51.936196 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5685 22:15:51.939767 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5686 22:15:51.942804 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5687 22:15:51.946353 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5688 22:15:51.949449 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5689 22:15:51.955938 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5690 22:15:51.956019 ==
5691 22:15:51.959366 Dram Type= 6, Freq= 0, CH_1, rank 0
5692 22:15:51.963073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5693 22:15:51.963155 ==
5694 22:15:51.963221 DQS Delay:
5695 22:15:51.965891 DQS0 = 0, DQS1 = 0
5696 22:15:51.965974 DQM Delay:
5697 22:15:51.969160 DQM0 = 101, DQM1 = 97
5698 22:15:51.969241 DQ Delay:
5699 22:15:51.972467 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5700 22:15:51.976012 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =103
5701 22:15:51.979593 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =91
5702 22:15:51.982414 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =107
5703 22:15:51.982496
5704 22:15:51.982561
5705 22:15:51.982622 ==
5706 22:15:51.985790 Dram Type= 6, Freq= 0, CH_1, rank 0
5707 22:15:51.992600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5708 22:15:51.992683 ==
5709 22:15:51.992749
5710 22:15:51.992809
5711 22:15:51.992868 TX Vref Scan disable
5712 22:15:51.996307 == TX Byte 0 ==
5713 22:15:51.999731 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5714 22:15:52.006602 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5715 22:15:52.006685 == TX Byte 1 ==
5716 22:15:52.009945 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5717 22:15:52.016270 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5718 22:15:52.016353 ==
5719 22:15:52.019880 Dram Type= 6, Freq= 0, CH_1, rank 0
5720 22:15:52.022966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5721 22:15:52.023049 ==
5722 22:15:52.023115
5723 22:15:52.023176
5724 22:15:52.026769 TX Vref Scan disable
5725 22:15:52.026851 == TX Byte 0 ==
5726 22:15:52.032903 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5727 22:15:52.036156 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5728 22:15:52.036239 == TX Byte 1 ==
5729 22:15:52.042811 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5730 22:15:52.046387 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5731 22:15:52.046470
5732 22:15:52.046536 [DATLAT]
5733 22:15:52.049435 Freq=933, CH1 RK0
5734 22:15:52.049541
5735 22:15:52.049621 DATLAT Default: 0xd
5736 22:15:52.053028 0, 0xFFFF, sum = 0
5737 22:15:52.053112 1, 0xFFFF, sum = 0
5738 22:15:52.056057 2, 0xFFFF, sum = 0
5739 22:15:52.056140 3, 0xFFFF, sum = 0
5740 22:15:52.059626 4, 0xFFFF, sum = 0
5741 22:15:52.059710 5, 0xFFFF, sum = 0
5742 22:15:52.062636 6, 0xFFFF, sum = 0
5743 22:15:52.066285 7, 0xFFFF, sum = 0
5744 22:15:52.066370 8, 0xFFFF, sum = 0
5745 22:15:52.069398 9, 0xFFFF, sum = 0
5746 22:15:52.069513 10, 0x0, sum = 1
5747 22:15:52.069617 11, 0x0, sum = 2
5748 22:15:52.072698 12, 0x0, sum = 3
5749 22:15:52.072782 13, 0x0, sum = 4
5750 22:15:52.076024 best_step = 11
5751 22:15:52.076106
5752 22:15:52.076171 ==
5753 22:15:52.079314 Dram Type= 6, Freq= 0, CH_1, rank 0
5754 22:15:52.082579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5755 22:15:52.082663 ==
5756 22:15:52.085984 RX Vref Scan: 1
5757 22:15:52.086071
5758 22:15:52.086141 RX Vref 0 -> 0, step: 1
5759 22:15:52.086202
5760 22:15:52.089234 RX Delay -45 -> 252, step: 4
5761 22:15:52.089316
5762 22:15:52.092924 Set Vref, RX VrefLevel [Byte0]: 55
5763 22:15:52.096249 [Byte1]: 54
5764 22:15:52.100464
5765 22:15:52.100545 Final RX Vref Byte 0 = 55 to rank0
5766 22:15:52.103573 Final RX Vref Byte 1 = 54 to rank0
5767 22:15:52.107147 Final RX Vref Byte 0 = 55 to rank1
5768 22:15:52.110053 Final RX Vref Byte 1 = 54 to rank1==
5769 22:15:52.114233 Dram Type= 6, Freq= 0, CH_1, rank 0
5770 22:15:52.120218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5771 22:15:52.120301 ==
5772 22:15:52.120366 DQS Delay:
5773 22:15:52.120428 DQS0 = 0, DQS1 = 0
5774 22:15:52.123246 DQM Delay:
5775 22:15:52.123328 DQM0 = 103, DQM1 = 99
5776 22:15:52.126716 DQ Delay:
5777 22:15:52.129971 DQ0 =106, DQ1 =98, DQ2 =94, DQ3 =102
5778 22:15:52.133657 DQ4 =104, DQ5 =112, DQ6 =110, DQ7 =104
5779 22:15:52.137440 DQ8 =90, DQ9 =92, DQ10 =102, DQ11 =92
5780 22:15:52.140342 DQ12 =104, DQ13 =102, DQ14 =106, DQ15 =106
5781 22:15:52.140423
5782 22:15:52.140489
5783 22:15:52.147010 [DQSOSCAuto] RK0, (LSB)MR18= 0x1830, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 414 ps
5784 22:15:52.150018 CH1 RK0: MR19=505, MR18=1830
5785 22:15:52.157076 CH1_RK0: MR19=0x505, MR18=0x1830, DQSOSC=406, MR23=63, INC=65, DEC=43
5786 22:15:52.157162
5787 22:15:52.160058 ----->DramcWriteLeveling(PI) begin...
5788 22:15:52.160141 ==
5789 22:15:52.163261 Dram Type= 6, Freq= 0, CH_1, rank 1
5790 22:15:52.166749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5791 22:15:52.166831 ==
5792 22:15:52.170859 Write leveling (Byte 0): 29 => 29
5793 22:15:52.173150 Write leveling (Byte 1): 28 => 28
5794 22:15:52.176404 DramcWriteLeveling(PI) end<-----
5795 22:15:52.176486
5796 22:15:52.176551 ==
5797 22:15:52.180000 Dram Type= 6, Freq= 0, CH_1, rank 1
5798 22:15:52.186349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5799 22:15:52.186432 ==
5800 22:15:52.186498 [Gating] SW mode calibration
5801 22:15:52.196853 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5802 22:15:52.199745 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5803 22:15:52.202943 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5804 22:15:52.209665 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5805 22:15:52.213096 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5806 22:15:52.216505 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5807 22:15:52.223136 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5808 22:15:52.226353 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5809 22:15:52.229622 0 14 24 | B1->B0 | 2e2e 3232 | 0 1 | (0 0) (1 0)
5810 22:15:52.236341 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5811 22:15:52.239568 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5812 22:15:52.242855 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5813 22:15:52.250245 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5814 22:15:52.253067 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5815 22:15:52.256735 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5816 22:15:52.263321 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5817 22:15:52.266248 0 15 24 | B1->B0 | 3737 2c2c | 0 0 | (1 1) (0 0)
5818 22:15:52.269912 0 15 28 | B1->B0 | 4646 4141 | 0 0 | (0 0) (0 0)
5819 22:15:52.276261 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5820 22:15:52.279429 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5821 22:15:52.283025 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5822 22:15:52.289883 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5823 22:15:52.292798 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5824 22:15:52.296112 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5825 22:15:52.302708 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5826 22:15:52.306196 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5827 22:15:52.309501 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 22:15:52.315970 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 22:15:52.319368 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 22:15:52.323042 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 22:15:52.326304 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 22:15:52.332658 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 22:15:52.335865 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 22:15:52.339642 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5835 22:15:52.345722 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5836 22:15:52.349240 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5837 22:15:52.352893 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5838 22:15:52.359616 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5839 22:15:52.362611 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5840 22:15:52.365933 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5841 22:15:52.372743 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5842 22:15:52.375924 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5843 22:15:52.378953 Total UI for P1: 0, mck2ui 16
5844 22:15:52.382092 best dqsien dly found for B0: ( 1, 2, 26)
5845 22:15:52.385570 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5846 22:15:52.389013 Total UI for P1: 0, mck2ui 16
5847 22:15:52.392016 best dqsien dly found for B1: ( 1, 2, 28)
5848 22:15:52.395373 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5849 22:15:52.398818 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5850 22:15:52.402190
5851 22:15:52.405623 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5852 22:15:52.409018 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5853 22:15:52.411866 [Gating] SW calibration Done
5854 22:15:52.411948 ==
5855 22:15:52.415962 Dram Type= 6, Freq= 0, CH_1, rank 1
5856 22:15:52.418745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5857 22:15:52.418859 ==
5858 22:15:52.418956 RX Vref Scan: 0
5859 22:15:52.419017
5860 22:15:52.422164 RX Vref 0 -> 0, step: 1
5861 22:15:52.422246
5862 22:15:52.425228 RX Delay -80 -> 252, step: 8
5863 22:15:52.428801 iDelay=208, Bit 0, Center 111 (24 ~ 199) 176
5864 22:15:52.432566 iDelay=208, Bit 1, Center 103 (16 ~ 191) 176
5865 22:15:52.438847 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5866 22:15:52.441810 iDelay=208, Bit 3, Center 99 (16 ~ 183) 168
5867 22:15:52.445447 iDelay=208, Bit 4, Center 99 (16 ~ 183) 168
5868 22:15:52.448423 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5869 22:15:52.451874 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5870 22:15:52.458649 iDelay=208, Bit 7, Center 103 (16 ~ 191) 176
5871 22:15:52.462253 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5872 22:15:52.465363 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5873 22:15:52.468850 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5874 22:15:52.471984 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5875 22:15:52.475083 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5876 22:15:52.481628 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5877 22:15:52.485269 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5878 22:15:52.488305 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5879 22:15:52.488387 ==
5880 22:15:52.491609 Dram Type= 6, Freq= 0, CH_1, rank 1
5881 22:15:52.494872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5882 22:15:52.494957 ==
5883 22:15:52.498131 DQS Delay:
5884 22:15:52.498214 DQS0 = 0, DQS1 = 0
5885 22:15:52.501776 DQM Delay:
5886 22:15:52.501857 DQM0 = 104, DQM1 = 99
5887 22:15:52.501923 DQ Delay:
5888 22:15:52.505199 DQ0 =111, DQ1 =103, DQ2 =91, DQ3 =99
5889 22:15:52.508744 DQ4 =99, DQ5 =115, DQ6 =115, DQ7 =103
5890 22:15:52.511632 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5891 22:15:52.518377 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5892 22:15:52.518485
5893 22:15:52.518577
5894 22:15:52.518665 ==
5895 22:15:52.521784 Dram Type= 6, Freq= 0, CH_1, rank 1
5896 22:15:52.524579 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5897 22:15:52.524662 ==
5898 22:15:52.524728
5899 22:15:52.524789
5900 22:15:52.528348 TX Vref Scan disable
5901 22:15:52.528430 == TX Byte 0 ==
5902 22:15:52.534940 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5903 22:15:52.538117 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5904 22:15:52.538200 == TX Byte 1 ==
5905 22:15:52.544775 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5906 22:15:52.548133 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5907 22:15:52.548216 ==
5908 22:15:52.551483 Dram Type= 6, Freq= 0, CH_1, rank 1
5909 22:15:52.555098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5910 22:15:52.555181 ==
5911 22:15:52.555247
5912 22:15:52.557927
5913 22:15:52.558009 TX Vref Scan disable
5914 22:15:52.561431 == TX Byte 0 ==
5915 22:15:52.564941 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5916 22:15:52.568123 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5917 22:15:52.571577 == TX Byte 1 ==
5918 22:15:52.574525 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5919 22:15:52.578213 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5920 22:15:52.578287
5921 22:15:52.581183 [DATLAT]
5922 22:15:52.581257 Freq=933, CH1 RK1
5923 22:15:52.581327
5924 22:15:52.584825 DATLAT Default: 0xb
5925 22:15:52.584897 0, 0xFFFF, sum = 0
5926 22:15:52.588285 1, 0xFFFF, sum = 0
5927 22:15:52.588363 2, 0xFFFF, sum = 0
5928 22:15:52.591410 3, 0xFFFF, sum = 0
5929 22:15:52.591482 4, 0xFFFF, sum = 0
5930 22:15:52.594366 5, 0xFFFF, sum = 0
5931 22:15:52.594439 6, 0xFFFF, sum = 0
5932 22:15:52.597860 7, 0xFFFF, sum = 0
5933 22:15:52.600992 8, 0xFFFF, sum = 0
5934 22:15:52.601068 9, 0xFFFF, sum = 0
5935 22:15:52.601162 10, 0x0, sum = 1
5936 22:15:52.604477 11, 0x0, sum = 2
5937 22:15:52.604579 12, 0x0, sum = 3
5938 22:15:52.607771 13, 0x0, sum = 4
5939 22:15:52.607862 best_step = 11
5940 22:15:52.607928
5941 22:15:52.607988 ==
5942 22:15:52.610918 Dram Type= 6, Freq= 0, CH_1, rank 1
5943 22:15:52.617641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5944 22:15:52.617719 ==
5945 22:15:52.617785 RX Vref Scan: 0
5946 22:15:52.617853
5947 22:15:52.620974 RX Vref 0 -> 0, step: 1
5948 22:15:52.621074
5949 22:15:52.624324 RX Delay -45 -> 252, step: 4
5950 22:15:52.627700 iDelay=203, Bit 0, Center 108 (27 ~ 190) 164
5951 22:15:52.634812 iDelay=203, Bit 1, Center 102 (19 ~ 186) 168
5952 22:15:52.637428 iDelay=203, Bit 2, Center 94 (11 ~ 178) 168
5953 22:15:52.640823 iDelay=203, Bit 3, Center 100 (19 ~ 182) 164
5954 22:15:52.644189 iDelay=203, Bit 4, Center 100 (19 ~ 182) 164
5955 22:15:52.647431 iDelay=203, Bit 5, Center 118 (35 ~ 202) 168
5956 22:15:52.654472 iDelay=203, Bit 6, Center 112 (27 ~ 198) 172
5957 22:15:52.657468 iDelay=203, Bit 7, Center 104 (19 ~ 190) 172
5958 22:15:52.660895 iDelay=203, Bit 8, Center 90 (7 ~ 174) 168
5959 22:15:52.664264 iDelay=203, Bit 9, Center 92 (7 ~ 178) 172
5960 22:15:52.667463 iDelay=203, Bit 10, Center 100 (15 ~ 186) 172
5961 22:15:52.671000 iDelay=203, Bit 11, Center 94 (11 ~ 178) 168
5962 22:15:52.677712 iDelay=203, Bit 12, Center 110 (23 ~ 198) 176
5963 22:15:52.680582 iDelay=203, Bit 13, Center 106 (23 ~ 190) 168
5964 22:15:52.684251 iDelay=203, Bit 14, Center 104 (23 ~ 186) 164
5965 22:15:52.687519 iDelay=203, Bit 15, Center 108 (23 ~ 194) 172
5966 22:15:52.687602 ==
5967 22:15:52.690486 Dram Type= 6, Freq= 0, CH_1, rank 1
5968 22:15:52.697479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5969 22:15:52.697594 ==
5970 22:15:52.697659 DQS Delay:
5971 22:15:52.701144 DQS0 = 0, DQS1 = 0
5972 22:15:52.701236 DQM Delay:
5973 22:15:52.701327 DQM0 = 104, DQM1 = 100
5974 22:15:52.704193 DQ Delay:
5975 22:15:52.707564 DQ0 =108, DQ1 =102, DQ2 =94, DQ3 =100
5976 22:15:52.710608 DQ4 =100, DQ5 =118, DQ6 =112, DQ7 =104
5977 22:15:52.714287 DQ8 =90, DQ9 =92, DQ10 =100, DQ11 =94
5978 22:15:52.717827 DQ12 =110, DQ13 =106, DQ14 =104, DQ15 =108
5979 22:15:52.717900
5980 22:15:52.717962
5981 22:15:52.723957 [DQSOSCAuto] RK1, (LSB)MR18= 0x2e02, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 407 ps
5982 22:15:52.727239 CH1 RK1: MR19=505, MR18=2E02
5983 22:15:52.734511 CH1_RK1: MR19=0x505, MR18=0x2E02, DQSOSC=407, MR23=63, INC=65, DEC=43
5984 22:15:52.737392 [RxdqsGatingPostProcess] freq 933
5985 22:15:52.743865 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5986 22:15:52.747635 best DQS0 dly(2T, 0.5T) = (0, 10)
5987 22:15:52.750730 best DQS1 dly(2T, 0.5T) = (0, 10)
5988 22:15:52.753820 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5989 22:15:52.757119 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5990 22:15:52.757216 best DQS0 dly(2T, 0.5T) = (0, 10)
5991 22:15:52.760502 best DQS1 dly(2T, 0.5T) = (0, 10)
5992 22:15:52.763720 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5993 22:15:52.767084 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5994 22:15:52.770599 Pre-setting of DQS Precalculation
5995 22:15:52.777303 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5996 22:15:52.784293 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5997 22:15:52.790836 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5998 22:15:52.790912
5999 22:15:52.790976
6000 22:15:52.793647 [Calibration Summary] 1866 Mbps
6001 22:15:52.793721 CH 0, Rank 0
6002 22:15:52.797383 SW Impedance : PASS
6003 22:15:52.800357 DUTY Scan : NO K
6004 22:15:52.800455 ZQ Calibration : PASS
6005 22:15:52.804045 Jitter Meter : NO K
6006 22:15:52.807462 CBT Training : PASS
6007 22:15:52.807535 Write leveling : PASS
6008 22:15:52.810488 RX DQS gating : PASS
6009 22:15:52.813693 RX DQ/DQS(RDDQC) : PASS
6010 22:15:52.813765 TX DQ/DQS : PASS
6011 22:15:52.817395 RX DATLAT : PASS
6012 22:15:52.817496 RX DQ/DQS(Engine): PASS
6013 22:15:52.820637 TX OE : NO K
6014 22:15:52.820740 All Pass.
6015 22:15:52.820831
6016 22:15:52.824109 CH 0, Rank 1
6017 22:15:52.824186 SW Impedance : PASS
6018 22:15:52.826865 DUTY Scan : NO K
6019 22:15:52.830228 ZQ Calibration : PASS
6020 22:15:52.830301 Jitter Meter : NO K
6021 22:15:52.834090 CBT Training : PASS
6022 22:15:52.837542 Write leveling : PASS
6023 22:15:52.837641 RX DQS gating : PASS
6024 22:15:52.840247 RX DQ/DQS(RDDQC) : PASS
6025 22:15:52.843528 TX DQ/DQS : PASS
6026 22:15:52.843604 RX DATLAT : PASS
6027 22:15:52.846880 RX DQ/DQS(Engine): PASS
6028 22:15:52.850154 TX OE : NO K
6029 22:15:52.850264 All Pass.
6030 22:15:52.850356
6031 22:15:52.850447 CH 1, Rank 0
6032 22:15:52.853866 SW Impedance : PASS
6033 22:15:52.856837 DUTY Scan : NO K
6034 22:15:52.856911 ZQ Calibration : PASS
6035 22:15:52.860337 Jitter Meter : NO K
6036 22:15:52.863684 CBT Training : PASS
6037 22:15:52.863785 Write leveling : PASS
6038 22:15:52.867121 RX DQS gating : PASS
6039 22:15:52.867200 RX DQ/DQS(RDDQC) : PASS
6040 22:15:52.870136 TX DQ/DQS : PASS
6041 22:15:52.873734 RX DATLAT : PASS
6042 22:15:52.873824 RX DQ/DQS(Engine): PASS
6043 22:15:52.876606 TX OE : NO K
6044 22:15:52.876678 All Pass.
6045 22:15:52.876745
6046 22:15:52.880326 CH 1, Rank 1
6047 22:15:52.880423 SW Impedance : PASS
6048 22:15:52.883252 DUTY Scan : NO K
6049 22:15:52.886800 ZQ Calibration : PASS
6050 22:15:52.886873 Jitter Meter : NO K
6051 22:15:52.889887 CBT Training : PASS
6052 22:15:52.893418 Write leveling : PASS
6053 22:15:52.893523 RX DQS gating : PASS
6054 22:15:52.896575 RX DQ/DQS(RDDQC) : PASS
6055 22:15:52.900290 TX DQ/DQS : PASS
6056 22:15:52.900389 RX DATLAT : PASS
6057 22:15:52.903325 RX DQ/DQS(Engine): PASS
6058 22:15:52.906436 TX OE : NO K
6059 22:15:52.906534 All Pass.
6060 22:15:52.906623
6061 22:15:52.906709 DramC Write-DBI off
6062 22:15:52.909869 PER_BANK_REFRESH: Hybrid Mode
6063 22:15:52.913388 TX_TRACKING: ON
6064 22:15:52.919980 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6065 22:15:52.923489 [FAST_K] Save calibration result to emmc
6066 22:15:52.929949 dramc_set_vcore_voltage set vcore to 650000
6067 22:15:52.930026 Read voltage for 400, 6
6068 22:15:52.933417 Vio18 = 0
6069 22:15:52.933525 Vcore = 650000
6070 22:15:52.933592 Vdram = 0
6071 22:15:52.936543 Vddq = 0
6072 22:15:52.936639 Vmddr = 0
6073 22:15:52.939882 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6074 22:15:52.946615 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6075 22:15:52.949894 MEM_TYPE=3, freq_sel=20
6076 22:15:52.949971 sv_algorithm_assistance_LP4_800
6077 22:15:52.956942 ============ PULL DRAM RESETB DOWN ============
6078 22:15:52.960199 ========== PULL DRAM RESETB DOWN end =========
6079 22:15:52.963636 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6080 22:15:52.966400 ===================================
6081 22:15:52.969793 LPDDR4 DRAM CONFIGURATION
6082 22:15:52.973333 ===================================
6083 22:15:52.976558 EX_ROW_EN[0] = 0x0
6084 22:15:52.976656 EX_ROW_EN[1] = 0x0
6085 22:15:52.980307 LP4Y_EN = 0x0
6086 22:15:52.980405 WORK_FSP = 0x0
6087 22:15:52.982956 WL = 0x2
6088 22:15:52.983052 RL = 0x2
6089 22:15:52.986590 BL = 0x2
6090 22:15:52.986661 RPST = 0x0
6091 22:15:52.989595 RD_PRE = 0x0
6092 22:15:52.989697 WR_PRE = 0x1
6093 22:15:52.993046 WR_PST = 0x0
6094 22:15:52.993141 DBI_WR = 0x0
6095 22:15:52.996940 DBI_RD = 0x0
6096 22:15:52.997037 OTF = 0x1
6097 22:15:52.999899 ===================================
6098 22:15:53.003053 ===================================
6099 22:15:53.006063 ANA top config
6100 22:15:53.009528 ===================================
6101 22:15:53.013068 DLL_ASYNC_EN = 0
6102 22:15:53.013165 ALL_SLAVE_EN = 1
6103 22:15:53.016196 NEW_RANK_MODE = 1
6104 22:15:53.019786 DLL_IDLE_MODE = 1
6105 22:15:53.022759 LP45_APHY_COMB_EN = 1
6106 22:15:53.026407 TX_ODT_DIS = 1
6107 22:15:53.026499 NEW_8X_MODE = 1
6108 22:15:53.029930 ===================================
6109 22:15:53.032919 ===================================
6110 22:15:53.036234 data_rate = 800
6111 22:15:53.039199 CKR = 1
6112 22:15:53.042736 DQ_P2S_RATIO = 4
6113 22:15:53.046465 ===================================
6114 22:15:53.049477 CA_P2S_RATIO = 4
6115 22:15:53.049597 DQ_CA_OPEN = 0
6116 22:15:53.052773 DQ_SEMI_OPEN = 1
6117 22:15:53.056301 CA_SEMI_OPEN = 1
6118 22:15:53.059300 CA_FULL_RATE = 0
6119 22:15:53.062765 DQ_CKDIV4_EN = 0
6120 22:15:53.066084 CA_CKDIV4_EN = 1
6121 22:15:53.066163 CA_PREDIV_EN = 0
6122 22:15:53.069598 PH8_DLY = 0
6123 22:15:53.072846 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6124 22:15:53.075818 DQ_AAMCK_DIV = 0
6125 22:15:53.079145 CA_AAMCK_DIV = 0
6126 22:15:53.082719 CA_ADMCK_DIV = 4
6127 22:15:53.082824 DQ_TRACK_CA_EN = 0
6128 22:15:53.086094 CA_PICK = 800
6129 22:15:53.089600 CA_MCKIO = 400
6130 22:15:53.093076 MCKIO_SEMI = 400
6131 22:15:53.096234 PLL_FREQ = 3016
6132 22:15:53.099354 DQ_UI_PI_RATIO = 32
6133 22:15:53.102896 CA_UI_PI_RATIO = 32
6134 22:15:53.105836 ===================================
6135 22:15:53.109434 ===================================
6136 22:15:53.109538 memory_type:LPDDR4
6137 22:15:53.112381 GP_NUM : 10
6138 22:15:53.115859 SRAM_EN : 1
6139 22:15:53.115934 MD32_EN : 0
6140 22:15:53.119511 ===================================
6141 22:15:53.122404 [ANA_INIT] >>>>>>>>>>>>>>
6142 22:15:53.125982 <<<<<< [CONFIGURE PHASE]: ANA_TX
6143 22:15:53.129072 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6144 22:15:53.132617 ===================================
6145 22:15:53.136365 data_rate = 800,PCW = 0X7400
6146 22:15:53.139190 ===================================
6147 22:15:53.142859 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6148 22:15:53.146067 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6149 22:15:53.159373 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6150 22:15:53.162665 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6151 22:15:53.166135 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6152 22:15:53.169432 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6153 22:15:53.172402 [ANA_INIT] flow start
6154 22:15:53.175911 [ANA_INIT] PLL >>>>>>>>
6155 22:15:53.176015 [ANA_INIT] PLL <<<<<<<<
6156 22:15:53.179348 [ANA_INIT] MIDPI >>>>>>>>
6157 22:15:53.182413 [ANA_INIT] MIDPI <<<<<<<<
6158 22:15:53.182486 [ANA_INIT] DLL >>>>>>>>
6159 22:15:53.185852 [ANA_INIT] flow end
6160 22:15:53.189016 ============ LP4 DIFF to SE enter ============
6161 22:15:53.192591 ============ LP4 DIFF to SE exit ============
6162 22:15:53.195570 [ANA_INIT] <<<<<<<<<<<<<
6163 22:15:53.199055 [Flow] Enable top DCM control >>>>>
6164 22:15:53.202609 [Flow] Enable top DCM control <<<<<
6165 22:15:53.205602 Enable DLL master slave shuffle
6166 22:15:53.212330 ==============================================================
6167 22:15:53.212407 Gating Mode config
6168 22:15:53.219420 ==============================================================
6169 22:15:53.219498 Config description:
6170 22:15:53.228932 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6171 22:15:53.235373 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6172 22:15:53.242455 SELPH_MODE 0: By rank 1: By Phase
6173 22:15:53.245951 ==============================================================
6174 22:15:53.248860 GAT_TRACK_EN = 0
6175 22:15:53.252367 RX_GATING_MODE = 2
6176 22:15:53.255739 RX_GATING_TRACK_MODE = 2
6177 22:15:53.259233 SELPH_MODE = 1
6178 22:15:53.262100 PICG_EARLY_EN = 1
6179 22:15:53.265937 VALID_LAT_VALUE = 1
6180 22:15:53.268678 ==============================================================
6181 22:15:53.272226 Enter into Gating configuration >>>>
6182 22:15:53.275694 Exit from Gating configuration <<<<
6183 22:15:53.279012 Enter into DVFS_PRE_config >>>>>
6184 22:15:53.292649 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6185 22:15:53.295786 Exit from DVFS_PRE_config <<<<<
6186 22:15:53.298962 Enter into PICG configuration >>>>
6187 22:15:53.299044 Exit from PICG configuration <<<<
6188 22:15:53.302204 [RX_INPUT] configuration >>>>>
6189 22:15:53.305817 [RX_INPUT] configuration <<<<<
6190 22:15:53.312089 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6191 22:15:53.315637 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6192 22:15:53.321777 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6193 22:15:53.328610 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6194 22:15:53.335555 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6195 22:15:53.341840 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6196 22:15:53.345474 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6197 22:15:53.348521 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6198 22:15:53.355034 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6199 22:15:53.358448 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6200 22:15:53.361758 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6201 22:15:53.364923 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6202 22:15:53.368594 ===================================
6203 22:15:53.371943 LPDDR4 DRAM CONFIGURATION
6204 22:15:53.375215 ===================================
6205 22:15:53.378494 EX_ROW_EN[0] = 0x0
6206 22:15:53.378571 EX_ROW_EN[1] = 0x0
6207 22:15:53.381746 LP4Y_EN = 0x0
6208 22:15:53.381822 WORK_FSP = 0x0
6209 22:15:53.385008 WL = 0x2
6210 22:15:53.385086 RL = 0x2
6211 22:15:53.388420 BL = 0x2
6212 22:15:53.388496 RPST = 0x0
6213 22:15:53.391877 RD_PRE = 0x0
6214 22:15:53.391960 WR_PRE = 0x1
6215 22:15:53.395325 WR_PST = 0x0
6216 22:15:53.395401 DBI_WR = 0x0
6217 22:15:53.398825 DBI_RD = 0x0
6218 22:15:53.398902 OTF = 0x1
6219 22:15:53.401488 ===================================
6220 22:15:53.408194 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6221 22:15:53.411753 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6222 22:15:53.414883 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6223 22:15:53.418503 ===================================
6224 22:15:53.421518 LPDDR4 DRAM CONFIGURATION
6225 22:15:53.425332 ===================================
6226 22:15:53.428201 EX_ROW_EN[0] = 0x10
6227 22:15:53.428278 EX_ROW_EN[1] = 0x0
6228 22:15:53.431803 LP4Y_EN = 0x0
6229 22:15:53.431879 WORK_FSP = 0x0
6230 22:15:53.435237 WL = 0x2
6231 22:15:53.435313 RL = 0x2
6232 22:15:53.438237 BL = 0x2
6233 22:15:53.438312 RPST = 0x0
6234 22:15:53.441781 RD_PRE = 0x0
6235 22:15:53.441855 WR_PRE = 0x1
6236 22:15:53.444800 WR_PST = 0x0
6237 22:15:53.444876 DBI_WR = 0x0
6238 22:15:53.448373 DBI_RD = 0x0
6239 22:15:53.448460 OTF = 0x1
6240 22:15:53.451464 ===================================
6241 22:15:53.458748 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6242 22:15:53.462936 nWR fixed to 30
6243 22:15:53.466628 [ModeRegInit_LP4] CH0 RK0
6244 22:15:53.466710 [ModeRegInit_LP4] CH0 RK1
6245 22:15:53.469814 [ModeRegInit_LP4] CH1 RK0
6246 22:15:53.472839 [ModeRegInit_LP4] CH1 RK1
6247 22:15:53.472922 match AC timing 19
6248 22:15:53.479467 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6249 22:15:53.482833 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6250 22:15:53.485881 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6251 22:15:53.493077 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6252 22:15:53.496280 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6253 22:15:53.496363 ==
6254 22:15:53.499511 Dram Type= 6, Freq= 0, CH_0, rank 0
6255 22:15:53.503170 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6256 22:15:53.503253 ==
6257 22:15:53.509211 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6258 22:15:53.515693 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6259 22:15:53.519401 [CA 0] Center 36 (8~64) winsize 57
6260 22:15:53.523137 [CA 1] Center 36 (8~64) winsize 57
6261 22:15:53.526200 [CA 2] Center 36 (8~64) winsize 57
6262 22:15:53.526282 [CA 3] Center 36 (8~64) winsize 57
6263 22:15:53.529662 [CA 4] Center 36 (8~64) winsize 57
6264 22:15:53.532736 [CA 5] Center 36 (8~64) winsize 57
6265 22:15:53.532818
6266 22:15:53.539181 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6267 22:15:53.539263
6268 22:15:53.542752 [CATrainingPosCal] consider 1 rank data
6269 22:15:53.542834 u2DelayCellTimex100 = 270/100 ps
6270 22:15:53.549441 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6271 22:15:53.553023 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6272 22:15:53.556056 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6273 22:15:53.559137 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 22:15:53.562587 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 22:15:53.566236 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 22:15:53.566318
6277 22:15:53.569079 CA PerBit enable=1, Macro0, CA PI delay=36
6278 22:15:53.569160
6279 22:15:53.572416 [CBTSetCACLKResult] CA Dly = 36
6280 22:15:53.575972 CS Dly: 1 (0~32)
6281 22:15:53.576053 ==
6282 22:15:53.579255 Dram Type= 6, Freq= 0, CH_0, rank 1
6283 22:15:53.582584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6284 22:15:53.582692 ==
6285 22:15:53.589529 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6286 22:15:53.592678 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6287 22:15:53.596070 [CA 0] Center 36 (8~64) winsize 57
6288 22:15:53.599336 [CA 1] Center 36 (8~64) winsize 57
6289 22:15:53.602367 [CA 2] Center 36 (8~64) winsize 57
6290 22:15:53.605751 [CA 3] Center 36 (8~64) winsize 57
6291 22:15:53.609100 [CA 4] Center 36 (8~64) winsize 57
6292 22:15:53.612878 [CA 5] Center 36 (8~64) winsize 57
6293 22:15:53.612959
6294 22:15:53.616134 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6295 22:15:53.616216
6296 22:15:53.619177 [CATrainingPosCal] consider 2 rank data
6297 22:15:53.622501 u2DelayCellTimex100 = 270/100 ps
6298 22:15:53.626234 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6299 22:15:53.629192 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6300 22:15:53.632720 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6301 22:15:53.635625 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6302 22:15:53.642692 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6303 22:15:53.645645 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6304 22:15:53.645727
6305 22:15:53.649387 CA PerBit enable=1, Macro0, CA PI delay=36
6306 22:15:53.649469
6307 22:15:53.652150 [CBTSetCACLKResult] CA Dly = 36
6308 22:15:53.652231 CS Dly: 1 (0~32)
6309 22:15:53.652297
6310 22:15:53.655852 ----->DramcWriteLeveling(PI) begin...
6311 22:15:53.655936 ==
6312 22:15:53.658829 Dram Type= 6, Freq= 0, CH_0, rank 0
6313 22:15:53.665434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6314 22:15:53.665538 ==
6315 22:15:53.669203 Write leveling (Byte 0): 40 => 8
6316 22:15:53.672063 Write leveling (Byte 1): 40 => 8
6317 22:15:53.672145 DramcWriteLeveling(PI) end<-----
6318 22:15:53.672210
6319 22:15:53.675428 ==
6320 22:15:53.679089 Dram Type= 6, Freq= 0, CH_0, rank 0
6321 22:15:53.682353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6322 22:15:53.682435 ==
6323 22:15:53.685793 [Gating] SW mode calibration
6324 22:15:53.692439 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6325 22:15:53.695530 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6326 22:15:53.701991 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6327 22:15:53.705820 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6328 22:15:53.709116 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6329 22:15:53.715380 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6330 22:15:53.718487 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6331 22:15:53.722226 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6332 22:15:53.729090 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6333 22:15:53.731997 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6334 22:15:53.735668 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6335 22:15:53.738807 Total UI for P1: 0, mck2ui 16
6336 22:15:53.742187 best dqsien dly found for B0: ( 0, 14, 24)
6337 22:15:53.745221 Total UI for P1: 0, mck2ui 16
6338 22:15:53.748955 best dqsien dly found for B1: ( 0, 14, 24)
6339 22:15:53.751902 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6340 22:15:53.755584 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6341 22:15:53.755666
6342 22:15:53.762080 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6343 22:15:53.765077 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6344 22:15:53.765179 [Gating] SW calibration Done
6345 22:15:53.768312 ==
6346 22:15:53.771416 Dram Type= 6, Freq= 0, CH_0, rank 0
6347 22:15:53.774935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6348 22:15:53.775044 ==
6349 22:15:53.775137 RX Vref Scan: 0
6350 22:15:53.775229
6351 22:15:53.778326 RX Vref 0 -> 0, step: 1
6352 22:15:53.778397
6353 22:15:53.781580 RX Delay -410 -> 252, step: 16
6354 22:15:53.784812 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6355 22:15:53.791758 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6356 22:15:53.794635 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6357 22:15:53.797872 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6358 22:15:53.801730 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6359 22:15:53.808154 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6360 22:15:53.811819 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6361 22:15:53.815035 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6362 22:15:53.818439 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6363 22:15:53.821845 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6364 22:15:53.828263 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6365 22:15:53.831451 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6366 22:15:53.835058 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6367 22:15:53.841760 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6368 22:15:53.845002 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6369 22:15:53.847966 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6370 22:15:53.848067 ==
6371 22:15:53.851721 Dram Type= 6, Freq= 0, CH_0, rank 0
6372 22:15:53.854791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6373 22:15:53.854863 ==
6374 22:15:53.858213 DQS Delay:
6375 22:15:53.858282 DQS0 = 27, DQS1 = 35
6376 22:15:53.861322 DQM Delay:
6377 22:15:53.861422 DQM0 = 12, DQM1 = 11
6378 22:15:53.864344 DQ Delay:
6379 22:15:53.864438 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6380 22:15:53.868100 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6381 22:15:53.871797 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6382 22:15:53.874848 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6383 22:15:53.874916
6384 22:15:53.874979
6385 22:15:53.875037 ==
6386 22:15:53.878440 Dram Type= 6, Freq= 0, CH_0, rank 0
6387 22:15:53.884921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6388 22:15:53.885017 ==
6389 22:15:53.885105
6390 22:15:53.885189
6391 22:15:53.885274 TX Vref Scan disable
6392 22:15:53.888144 == TX Byte 0 ==
6393 22:15:53.891196 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6394 22:15:53.894948 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6395 22:15:53.897742 == TX Byte 1 ==
6396 22:15:53.901664 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6397 22:15:53.904387 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6398 22:15:53.904463 ==
6399 22:15:53.907679 Dram Type= 6, Freq= 0, CH_0, rank 0
6400 22:15:53.914455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6401 22:15:53.914530 ==
6402 22:15:53.914592
6403 22:15:53.914651
6404 22:15:53.914711 TX Vref Scan disable
6405 22:15:53.918231 == TX Byte 0 ==
6406 22:15:53.921289 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6407 22:15:53.924366 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6408 22:15:53.927809 == TX Byte 1 ==
6409 22:15:53.931749 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6410 22:15:53.934528 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6411 22:15:53.934598
6412 22:15:53.937879 [DATLAT]
6413 22:15:53.937949 Freq=400, CH0 RK0
6414 22:15:53.938013
6415 22:15:53.941477 DATLAT Default: 0xf
6416 22:15:53.941597 0, 0xFFFF, sum = 0
6417 22:15:53.944354 1, 0xFFFF, sum = 0
6418 22:15:53.944451 2, 0xFFFF, sum = 0
6419 22:15:53.947904 3, 0xFFFF, sum = 0
6420 22:15:53.948006 4, 0xFFFF, sum = 0
6421 22:15:53.951630 5, 0xFFFF, sum = 0
6422 22:15:53.951734 6, 0xFFFF, sum = 0
6423 22:15:53.954933 7, 0xFFFF, sum = 0
6424 22:15:53.955033 8, 0xFFFF, sum = 0
6425 22:15:53.957837 9, 0xFFFF, sum = 0
6426 22:15:53.957934 10, 0xFFFF, sum = 0
6427 22:15:53.961101 11, 0xFFFF, sum = 0
6428 22:15:53.964479 12, 0xFFFF, sum = 0
6429 22:15:53.964557 13, 0x0, sum = 1
6430 22:15:53.964621 14, 0x0, sum = 2
6431 22:15:53.968185 15, 0x0, sum = 3
6432 22:15:53.968285 16, 0x0, sum = 4
6433 22:15:53.971178 best_step = 14
6434 22:15:53.971274
6435 22:15:53.971362 ==
6436 22:15:53.975150 Dram Type= 6, Freq= 0, CH_0, rank 0
6437 22:15:53.978065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6438 22:15:53.978135 ==
6439 22:15:53.981187 RX Vref Scan: 1
6440 22:15:53.981283
6441 22:15:53.981369 RX Vref 0 -> 0, step: 1
6442 22:15:53.981454
6443 22:15:53.984618 RX Delay -311 -> 252, step: 8
6444 22:15:53.984687
6445 22:15:53.988144 Set Vref, RX VrefLevel [Byte0]: 56
6446 22:15:53.990935 [Byte1]: 48
6447 22:15:53.996100
6448 22:15:53.996174 Final RX Vref Byte 0 = 56 to rank0
6449 22:15:53.999517 Final RX Vref Byte 1 = 48 to rank0
6450 22:15:54.002656 Final RX Vref Byte 0 = 56 to rank1
6451 22:15:54.006081 Final RX Vref Byte 1 = 48 to rank1==
6452 22:15:54.009540 Dram Type= 6, Freq= 0, CH_0, rank 0
6453 22:15:54.016163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6454 22:15:54.016260 ==
6455 22:15:54.016325 DQS Delay:
6456 22:15:54.016384 DQS0 = 28, DQS1 = 36
6457 22:15:54.019700 DQM Delay:
6458 22:15:54.019801 DQM0 = 11, DQM1 = 13
6459 22:15:54.022462 DQ Delay:
6460 22:15:54.026421 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =8
6461 22:15:54.026494 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6462 22:15:54.029194 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6463 22:15:54.032474 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6464 22:15:54.032566
6465 22:15:54.036220
6466 22:15:54.043074 [DQSOSCAuto] RK0, (LSB)MR18= 0xcbb8, (MSB)MR19= 0xc0c, tDQSOscB0 = 386 ps tDQSOscB1 = 384 ps
6467 22:15:54.046032 CH0 RK0: MR19=C0C, MR18=CBB8
6468 22:15:54.052522 CH0_RK0: MR19=0xC0C, MR18=0xCBB8, DQSOSC=384, MR23=63, INC=400, DEC=267
6469 22:15:54.052629 ==
6470 22:15:54.055967 Dram Type= 6, Freq= 0, CH_0, rank 1
6471 22:15:54.059285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6472 22:15:54.059382 ==
6473 22:15:54.062853 [Gating] SW mode calibration
6474 22:15:54.069673 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6475 22:15:54.072681 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6476 22:15:54.079493 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6477 22:15:54.082962 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6478 22:15:54.086071 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6479 22:15:54.092629 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6480 22:15:54.096576 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6481 22:15:54.099357 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6482 22:15:54.106065 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6483 22:15:54.108961 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6484 22:15:54.112956 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6485 22:15:54.115652 Total UI for P1: 0, mck2ui 16
6486 22:15:54.119734 best dqsien dly found for B0: ( 0, 14, 24)
6487 22:15:54.122630 Total UI for P1: 0, mck2ui 16
6488 22:15:54.125864 best dqsien dly found for B1: ( 0, 14, 24)
6489 22:15:54.128853 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6490 22:15:54.132187 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6491 22:15:54.135676
6492 22:15:54.138883 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6493 22:15:54.142871 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6494 22:15:54.145857 [Gating] SW calibration Done
6495 22:15:54.145925 ==
6496 22:15:54.149211 Dram Type= 6, Freq= 0, CH_0, rank 1
6497 22:15:54.152770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6498 22:15:54.152863 ==
6499 22:15:54.152955 RX Vref Scan: 0
6500 22:15:54.153043
6501 22:15:54.155849 RX Vref 0 -> 0, step: 1
6502 22:15:54.155943
6503 22:15:54.159445 RX Delay -410 -> 252, step: 16
6504 22:15:54.162401 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6505 22:15:54.168929 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6506 22:15:54.172496 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6507 22:15:54.175844 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6508 22:15:54.178725 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6509 22:15:54.186166 iDelay=230, Bit 5, Center -19 (-250 ~ 213) 464
6510 22:15:54.188516 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6511 22:15:54.192168 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6512 22:15:54.195688 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6513 22:15:54.202084 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6514 22:15:54.205397 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6515 22:15:54.208928 iDelay=230, Bit 11, Center -27 (-250 ~ 197) 448
6516 22:15:54.212175 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6517 22:15:54.218746 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6518 22:15:54.221979 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6519 22:15:54.225220 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6520 22:15:54.225319 ==
6521 22:15:54.228793 Dram Type= 6, Freq= 0, CH_0, rank 1
6522 22:15:54.231798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6523 22:15:54.235384 ==
6524 22:15:54.235458 DQS Delay:
6525 22:15:54.235521 DQS0 = 19, DQS1 = 35
6526 22:15:54.238379 DQM Delay:
6527 22:15:54.238447 DQM0 = 5, DQM1 = 12
6528 22:15:54.242073 DQ Delay:
6529 22:15:54.242144 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6530 22:15:54.245156 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6531 22:15:54.248407 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6532 22:15:54.251845 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6533 22:15:54.251945
6534 22:15:54.252035
6535 22:15:54.252126 ==
6536 22:15:54.255519 Dram Type= 6, Freq= 0, CH_0, rank 1
6537 22:15:54.261891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6538 22:15:54.261964 ==
6539 22:15:54.262026
6540 22:15:54.262088
6541 22:15:54.262154 TX Vref Scan disable
6542 22:15:54.265092 == TX Byte 0 ==
6543 22:15:54.268810 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6544 22:15:54.271781 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6545 22:15:54.275137 == TX Byte 1 ==
6546 22:15:54.278250 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6547 22:15:54.281867 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6548 22:15:54.284762 ==
6549 22:15:54.284859 Dram Type= 6, Freq= 0, CH_0, rank 1
6550 22:15:54.291492 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6551 22:15:54.291566 ==
6552 22:15:54.291657
6553 22:15:54.291743
6554 22:15:54.295199 TX Vref Scan disable
6555 22:15:54.295291 == TX Byte 0 ==
6556 22:15:54.298273 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6557 22:15:54.304754 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6558 22:15:54.304856 == TX Byte 1 ==
6559 22:15:54.308325 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6560 22:15:54.311683 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6561 22:15:54.314910
6562 22:15:54.315005 [DATLAT]
6563 22:15:54.315096 Freq=400, CH0 RK1
6564 22:15:54.315185
6565 22:15:54.317901 DATLAT Default: 0xe
6566 22:15:54.317993 0, 0xFFFF, sum = 0
6567 22:15:54.321361 1, 0xFFFF, sum = 0
6568 22:15:54.321460 2, 0xFFFF, sum = 0
6569 22:15:54.324661 3, 0xFFFF, sum = 0
6570 22:15:54.324732 4, 0xFFFF, sum = 0
6571 22:15:54.328064 5, 0xFFFF, sum = 0
6572 22:15:54.331266 6, 0xFFFF, sum = 0
6573 22:15:54.331364 7, 0xFFFF, sum = 0
6574 22:15:54.334777 8, 0xFFFF, sum = 0
6575 22:15:54.334850 9, 0xFFFF, sum = 0
6576 22:15:54.338076 10, 0xFFFF, sum = 0
6577 22:15:54.338147 11, 0xFFFF, sum = 0
6578 22:15:54.341323 12, 0xFFFF, sum = 0
6579 22:15:54.341423 13, 0x0, sum = 1
6580 22:15:54.344847 14, 0x0, sum = 2
6581 22:15:54.344917 15, 0x0, sum = 3
6582 22:15:54.347815 16, 0x0, sum = 4
6583 22:15:54.347916 best_step = 14
6584 22:15:54.348006
6585 22:15:54.348094 ==
6586 22:15:54.351178 Dram Type= 6, Freq= 0, CH_0, rank 1
6587 22:15:54.354566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6588 22:15:54.354663 ==
6589 22:15:54.358066 RX Vref Scan: 0
6590 22:15:54.358161
6591 22:15:54.361370 RX Vref 0 -> 0, step: 1
6592 22:15:54.361465
6593 22:15:54.361593 RX Delay -311 -> 252, step: 8
6594 22:15:54.369975 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6595 22:15:54.373106 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6596 22:15:54.376557 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6597 22:15:54.383049 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6598 22:15:54.386646 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6599 22:15:54.389536 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6600 22:15:54.393352 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6601 22:15:54.396265 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6602 22:15:54.402787 iDelay=217, Bit 8, Center -28 (-247 ~ 192) 440
6603 22:15:54.406462 iDelay=217, Bit 9, Center -36 (-255 ~ 184) 440
6604 22:15:54.410018 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6605 22:15:54.416429 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6606 22:15:54.419821 iDelay=217, Bit 12, Center -20 (-239 ~ 200) 440
6607 22:15:54.422864 iDelay=217, Bit 13, Center -20 (-239 ~ 200) 440
6608 22:15:54.426324 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6609 22:15:54.432887 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6610 22:15:54.432988 ==
6611 22:15:54.436182 Dram Type= 6, Freq= 0, CH_0, rank 1
6612 22:15:54.439761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6613 22:15:54.439857 ==
6614 22:15:54.439949 DQS Delay:
6615 22:15:54.442889 DQS0 = 24, DQS1 = 36
6616 22:15:54.442960 DQM Delay:
6617 22:15:54.446225 DQM0 = 8, DQM1 = 13
6618 22:15:54.446323 DQ Delay:
6619 22:15:54.449307 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6620 22:15:54.452682 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6621 22:15:54.456158 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6622 22:15:54.459399 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6623 22:15:54.459497
6624 22:15:54.459619
6625 22:15:54.466005 [DQSOSCAuto] RK1, (LSB)MR18= 0xba5a, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6626 22:15:54.469638 CH0 RK1: MR19=C0C, MR18=BA5A
6627 22:15:54.476436 CH0_RK1: MR19=0xC0C, MR18=0xBA5A, DQSOSC=386, MR23=63, INC=396, DEC=264
6628 22:15:54.479322 [RxdqsGatingPostProcess] freq 400
6629 22:15:54.485959 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6630 22:15:54.486039 best DQS0 dly(2T, 0.5T) = (0, 10)
6631 22:15:54.489040 best DQS1 dly(2T, 0.5T) = (0, 10)
6632 22:15:54.492635 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6633 22:15:54.496362 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6634 22:15:54.499229 best DQS0 dly(2T, 0.5T) = (0, 10)
6635 22:15:54.502505 best DQS1 dly(2T, 0.5T) = (0, 10)
6636 22:15:54.506205 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6637 22:15:54.509096 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6638 22:15:54.512268 Pre-setting of DQS Precalculation
6639 22:15:54.519371 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6640 22:15:54.519482 ==
6641 22:15:54.522394 Dram Type= 6, Freq= 0, CH_1, rank 0
6642 22:15:54.525677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6643 22:15:54.525753 ==
6644 22:15:54.532117 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6645 22:15:54.535665 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6646 22:15:54.538789 [CA 0] Center 36 (8~64) winsize 57
6647 22:15:54.542299 [CA 1] Center 36 (8~64) winsize 57
6648 22:15:54.545896 [CA 2] Center 36 (8~64) winsize 57
6649 22:15:54.549189 [CA 3] Center 36 (8~64) winsize 57
6650 22:15:54.552318 [CA 4] Center 36 (8~64) winsize 57
6651 22:15:54.555430 [CA 5] Center 36 (8~64) winsize 57
6652 22:15:54.555529
6653 22:15:54.558862 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6654 22:15:54.558935
6655 22:15:54.562350 [CATrainingPosCal] consider 1 rank data
6656 22:15:54.565696 u2DelayCellTimex100 = 270/100 ps
6657 22:15:54.568743 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6658 22:15:54.572250 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6659 22:15:54.575498 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6660 22:15:54.579308 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 22:15:54.585359 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 22:15:54.589316 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 22:15:54.589416
6664 22:15:54.592356 CA PerBit enable=1, Macro0, CA PI delay=36
6665 22:15:54.592452
6666 22:15:54.595525 [CBTSetCACLKResult] CA Dly = 36
6667 22:15:54.595619 CS Dly: 1 (0~32)
6668 22:15:54.595703 ==
6669 22:15:54.598935 Dram Type= 6, Freq= 0, CH_1, rank 1
6670 22:15:54.605790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6671 22:15:54.605861 ==
6672 22:15:54.608681 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6673 22:15:54.615223 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6674 22:15:54.618441 [CA 0] Center 36 (8~64) winsize 57
6675 22:15:54.622217 [CA 1] Center 36 (8~64) winsize 57
6676 22:15:54.625534 [CA 2] Center 36 (8~64) winsize 57
6677 22:15:54.628510 [CA 3] Center 36 (8~64) winsize 57
6678 22:15:54.631838 [CA 4] Center 36 (8~64) winsize 57
6679 22:15:54.635456 [CA 5] Center 36 (8~64) winsize 57
6680 22:15:54.635558
6681 22:15:54.638589 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6682 22:15:54.638686
6683 22:15:54.642111 [CATrainingPosCal] consider 2 rank data
6684 22:15:54.645033 u2DelayCellTimex100 = 270/100 ps
6685 22:15:54.648399 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6686 22:15:54.651724 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6687 22:15:54.655542 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6688 22:15:54.658309 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6689 22:15:54.662037 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6690 22:15:54.665428 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6691 22:15:54.665548
6692 22:15:54.671570 CA PerBit enable=1, Macro0, CA PI delay=36
6693 22:15:54.671670
6694 22:15:54.671763 [CBTSetCACLKResult] CA Dly = 36
6695 22:15:54.675177 CS Dly: 1 (0~32)
6696 22:15:54.675273
6697 22:15:54.678505 ----->DramcWriteLeveling(PI) begin...
6698 22:15:54.678581 ==
6699 22:15:54.681904 Dram Type= 6, Freq= 0, CH_1, rank 0
6700 22:15:54.685389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6701 22:15:54.685485 ==
6702 22:15:54.688844 Write leveling (Byte 0): 40 => 8
6703 22:15:54.691981 Write leveling (Byte 1): 40 => 8
6704 22:15:54.695318 DramcWriteLeveling(PI) end<-----
6705 22:15:54.695412
6706 22:15:54.695502 ==
6707 22:15:54.698881 Dram Type= 6, Freq= 0, CH_1, rank 0
6708 22:15:54.701759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6709 22:15:54.705316 ==
6710 22:15:54.705419 [Gating] SW mode calibration
6711 22:15:54.712154 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6712 22:15:54.718732 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6713 22:15:54.721861 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6714 22:15:54.729092 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6715 22:15:54.731984 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6716 22:15:54.735445 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6717 22:15:54.738690 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6718 22:15:54.745305 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6719 22:15:54.748663 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6720 22:15:54.752145 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6721 22:15:54.758859 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6722 22:15:54.762051 Total UI for P1: 0, mck2ui 16
6723 22:15:54.766071 best dqsien dly found for B0: ( 0, 14, 24)
6724 22:15:54.769112 Total UI for P1: 0, mck2ui 16
6725 22:15:54.771862 best dqsien dly found for B1: ( 0, 14, 24)
6726 22:15:54.775181 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6727 22:15:54.778526 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6728 22:15:54.778616
6729 22:15:54.782213 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6730 22:15:54.785834 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6731 22:15:54.788698 [Gating] SW calibration Done
6732 22:15:54.788780 ==
6733 22:15:54.792158 Dram Type= 6, Freq= 0, CH_1, rank 0
6734 22:15:54.795067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6735 22:15:54.795158 ==
6736 22:15:54.798564 RX Vref Scan: 0
6737 22:15:54.798650
6738 22:15:54.801795 RX Vref 0 -> 0, step: 1
6739 22:15:54.801878
6740 22:15:54.801943 RX Delay -410 -> 252, step: 16
6741 22:15:54.808286 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6742 22:15:54.811947 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6743 22:15:54.815073 iDelay=230, Bit 2, Center -27 (-250 ~ 197) 448
6744 22:15:54.821514 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6745 22:15:54.824805 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6746 22:15:54.828306 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6747 22:15:54.831464 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6748 22:15:54.838138 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6749 22:15:54.841155 iDelay=230, Bit 8, Center -27 (-250 ~ 197) 448
6750 22:15:54.844633 iDelay=230, Bit 9, Center -27 (-250 ~ 197) 448
6751 22:15:54.848475 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6752 22:15:54.854939 iDelay=230, Bit 11, Center -19 (-250 ~ 213) 464
6753 22:15:54.858113 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6754 22:15:54.861407 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6755 22:15:54.864751 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6756 22:15:54.871826 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6757 22:15:54.871908 ==
6758 22:15:54.874646 Dram Type= 6, Freq= 0, CH_1, rank 0
6759 22:15:54.878095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6760 22:15:54.878178 ==
6761 22:15:54.878245 DQS Delay:
6762 22:15:54.881435 DQS0 = 27, DQS1 = 27
6763 22:15:54.881573 DQM Delay:
6764 22:15:54.884831 DQM0 = 11, DQM1 = 7
6765 22:15:54.884913 DQ Delay:
6766 22:15:54.887845 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6767 22:15:54.891373 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6768 22:15:54.894388 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =8
6769 22:15:54.897811 DQ12 =16, DQ13 =8, DQ14 =8, DQ15 =8
6770 22:15:54.897893
6771 22:15:54.897958
6772 22:15:54.898020 ==
6773 22:15:54.901395 Dram Type= 6, Freq= 0, CH_1, rank 0
6774 22:15:54.904992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6775 22:15:54.905075 ==
6776 22:15:54.905141
6777 22:15:54.905200
6778 22:15:54.907678 TX Vref Scan disable
6779 22:15:54.907760 == TX Byte 0 ==
6780 22:15:54.914711 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6781 22:15:54.917502 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6782 22:15:54.917593 == TX Byte 1 ==
6783 22:15:54.924439 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6784 22:15:54.928050 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6785 22:15:54.928133 ==
6786 22:15:54.931008 Dram Type= 6, Freq= 0, CH_1, rank 0
6787 22:15:54.934679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6788 22:15:54.934762 ==
6789 22:15:54.934828
6790 22:15:54.934889
6791 22:15:54.937940 TX Vref Scan disable
6792 22:15:54.938023 == TX Byte 0 ==
6793 22:15:54.944774 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6794 22:15:54.947682 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6795 22:15:54.947765 == TX Byte 1 ==
6796 22:15:54.954133 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6797 22:15:54.957784 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6798 22:15:54.957866
6799 22:15:54.957931 [DATLAT]
6800 22:15:54.960930 Freq=400, CH1 RK0
6801 22:15:54.961012
6802 22:15:54.961076 DATLAT Default: 0xf
6803 22:15:54.964293 0, 0xFFFF, sum = 0
6804 22:15:54.964377 1, 0xFFFF, sum = 0
6805 22:15:54.967878 2, 0xFFFF, sum = 0
6806 22:15:54.967961 3, 0xFFFF, sum = 0
6807 22:15:54.970804 4, 0xFFFF, sum = 0
6808 22:15:54.970887 5, 0xFFFF, sum = 0
6809 22:15:54.974579 6, 0xFFFF, sum = 0
6810 22:15:54.974663 7, 0xFFFF, sum = 0
6811 22:15:54.977804 8, 0xFFFF, sum = 0
6812 22:15:54.977888 9, 0xFFFF, sum = 0
6813 22:15:54.980753 10, 0xFFFF, sum = 0
6814 22:15:54.984215 11, 0xFFFF, sum = 0
6815 22:15:54.984299 12, 0xFFFF, sum = 0
6816 22:15:54.987625 13, 0x0, sum = 1
6817 22:15:54.987708 14, 0x0, sum = 2
6818 22:15:54.987775 15, 0x0, sum = 3
6819 22:15:54.990765 16, 0x0, sum = 4
6820 22:15:54.990849 best_step = 14
6821 22:15:54.990914
6822 22:15:54.994141 ==
6823 22:15:54.994224 Dram Type= 6, Freq= 0, CH_1, rank 0
6824 22:15:55.000633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6825 22:15:55.000716 ==
6826 22:15:55.000782 RX Vref Scan: 1
6827 22:15:55.000842
6828 22:15:55.004299 RX Vref 0 -> 0, step: 1
6829 22:15:55.004381
6830 22:15:55.007553 RX Delay -295 -> 252, step: 8
6831 22:15:55.007637
6832 22:15:55.010937 Set Vref, RX VrefLevel [Byte0]: 55
6833 22:15:55.014236 [Byte1]: 54
6834 22:15:55.014319
6835 22:15:55.017868 Final RX Vref Byte 0 = 55 to rank0
6836 22:15:55.020929 Final RX Vref Byte 1 = 54 to rank0
6837 22:15:55.024120 Final RX Vref Byte 0 = 55 to rank1
6838 22:15:55.027754 Final RX Vref Byte 1 = 54 to rank1==
6839 22:15:55.030757 Dram Type= 6, Freq= 0, CH_1, rank 0
6840 22:15:55.034413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6841 22:15:55.037435 ==
6842 22:15:55.037545 DQS Delay:
6843 22:15:55.037613 DQS0 = 28, DQS1 = 32
6844 22:15:55.041148 DQM Delay:
6845 22:15:55.041230 DQM0 = 10, DQM1 = 9
6846 22:15:55.044208 DQ Delay:
6847 22:15:55.044289 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =8
6848 22:15:55.047341 DQ4 =12, DQ5 =20, DQ6 =16, DQ7 =8
6849 22:15:55.050742 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6850 22:15:55.054316 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6851 22:15:55.054398
6852 22:15:55.054463
6853 22:15:55.064195 [DQSOSCAuto] RK0, (LSB)MR18= 0x92cc, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6854 22:15:55.067361 CH1 RK0: MR19=C0C, MR18=92CC
6855 22:15:55.070928 CH1_RK0: MR19=0xC0C, MR18=0x92CC, DQSOSC=384, MR23=63, INC=400, DEC=267
6856 22:15:55.074275 ==
6857 22:15:55.077704 Dram Type= 6, Freq= 0, CH_1, rank 1
6858 22:15:55.081034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6859 22:15:55.081117 ==
6860 22:15:55.084208 [Gating] SW mode calibration
6861 22:15:55.090654 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6862 22:15:55.094038 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6863 22:15:55.100693 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6864 22:15:55.104321 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6865 22:15:55.107262 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6866 22:15:55.114087 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6867 22:15:55.117923 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6868 22:15:55.120786 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6869 22:15:55.127251 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6870 22:15:55.130736 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6871 22:15:55.133977 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6872 22:15:55.137067 Total UI for P1: 0, mck2ui 16
6873 22:15:55.140654 best dqsien dly found for B0: ( 0, 14, 24)
6874 22:15:55.144361 Total UI for P1: 0, mck2ui 16
6875 22:15:55.147557 best dqsien dly found for B1: ( 0, 14, 24)
6876 22:15:55.150710 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6877 22:15:55.153930 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6878 22:15:55.154042
6879 22:15:55.160515 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6880 22:15:55.164163 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6881 22:15:55.164276 [Gating] SW calibration Done
6882 22:15:55.167557 ==
6883 22:15:55.167670 Dram Type= 6, Freq= 0, CH_1, rank 1
6884 22:15:55.174387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6885 22:15:55.174500 ==
6886 22:15:55.174590 RX Vref Scan: 0
6887 22:15:55.174673
6888 22:15:55.177796 RX Vref 0 -> 0, step: 1
6889 22:15:55.177907
6890 22:15:55.180553 RX Delay -410 -> 252, step: 16
6891 22:15:55.184159 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6892 22:15:55.187570 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6893 22:15:55.194200 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6894 22:15:55.197651 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6895 22:15:55.200654 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6896 22:15:55.204184 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6897 22:15:55.211083 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6898 22:15:55.214584 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6899 22:15:55.217464 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6900 22:15:55.220920 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6901 22:15:55.227599 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6902 22:15:55.231087 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6903 22:15:55.234465 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6904 22:15:55.238242 iDelay=230, Bit 13, Center -11 (-250 ~ 229) 480
6905 22:15:55.244449 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6906 22:15:55.247551 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6907 22:15:55.248044 ==
6908 22:15:55.251138 Dram Type= 6, Freq= 0, CH_1, rank 1
6909 22:15:55.254122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6910 22:15:55.254595 ==
6911 22:15:55.257135 DQS Delay:
6912 22:15:55.257571 DQS0 = 35, DQS1 = 35
6913 22:15:55.261024 DQM Delay:
6914 22:15:55.261567 DQM0 = 19, DQM1 = 15
6915 22:15:55.261949 DQ Delay:
6916 22:15:55.263867 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6917 22:15:55.266988 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6918 22:15:55.270423 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6919 22:15:55.274062 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6920 22:15:55.274528
6921 22:15:55.274911
6922 22:15:55.275224 ==
6923 22:15:55.277283 Dram Type= 6, Freq= 0, CH_1, rank 1
6924 22:15:55.284038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6925 22:15:55.284612 ==
6926 22:15:55.284990
6927 22:15:55.285341
6928 22:15:55.285733 TX Vref Scan disable
6929 22:15:55.287531 == TX Byte 0 ==
6930 22:15:55.290297 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6931 22:15:55.293654 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6932 22:15:55.297329 == TX Byte 1 ==
6933 22:15:55.300489 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6934 22:15:55.303946 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6935 22:15:55.306880 ==
6936 22:15:55.307306 Dram Type= 6, Freq= 0, CH_1, rank 1
6937 22:15:55.313594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6938 22:15:55.314135 ==
6939 22:15:55.314482
6940 22:15:55.314798
6941 22:15:55.315104 TX Vref Scan disable
6942 22:15:55.316994 == TX Byte 0 ==
6943 22:15:55.320426 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6944 22:15:55.323678 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6945 22:15:55.326640 == TX Byte 1 ==
6946 22:15:55.329968 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6947 22:15:55.334075 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6948 22:15:55.334600
6949 22:15:55.337663 [DATLAT]
6950 22:15:55.338234 Freq=400, CH1 RK1
6951 22:15:55.338610
6952 22:15:55.340604 DATLAT Default: 0xe
6953 22:15:55.341067 0, 0xFFFF, sum = 0
6954 22:15:55.344350 1, 0xFFFF, sum = 0
6955 22:15:55.344922 2, 0xFFFF, sum = 0
6956 22:15:55.347066 3, 0xFFFF, sum = 0
6957 22:15:55.347538 4, 0xFFFF, sum = 0
6958 22:15:55.350568 5, 0xFFFF, sum = 0
6959 22:15:55.351040 6, 0xFFFF, sum = 0
6960 22:15:55.353702 7, 0xFFFF, sum = 0
6961 22:15:55.357679 8, 0xFFFF, sum = 0
6962 22:15:55.358247 9, 0xFFFF, sum = 0
6963 22:15:55.360380 10, 0xFFFF, sum = 0
6964 22:15:55.360954 11, 0xFFFF, sum = 0
6965 22:15:55.363837 12, 0xFFFF, sum = 0
6966 22:15:55.364310 13, 0x0, sum = 1
6967 22:15:55.366828 14, 0x0, sum = 2
6968 22:15:55.367299 15, 0x0, sum = 3
6969 22:15:55.370415 16, 0x0, sum = 4
6970 22:15:55.370887 best_step = 14
6971 22:15:55.371257
6972 22:15:55.371662 ==
6973 22:15:55.373365 Dram Type= 6, Freq= 0, CH_1, rank 1
6974 22:15:55.376831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6975 22:15:55.377398 ==
6976 22:15:55.380286 RX Vref Scan: 0
6977 22:15:55.380847
6978 22:15:55.383595 RX Vref 0 -> 0, step: 1
6979 22:15:55.384129
6980 22:15:55.384502 RX Delay -311 -> 252, step: 8
6981 22:15:55.392458 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6982 22:15:55.395659 iDelay=217, Bit 1, Center -20 (-239 ~ 200) 440
6983 22:15:55.398916 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6984 22:15:55.401885 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6985 22:15:55.408979 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
6986 22:15:55.412134 iDelay=217, Bit 5, Center -8 (-231 ~ 216) 448
6987 22:15:55.415301 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6988 22:15:55.418428 iDelay=217, Bit 7, Center -16 (-239 ~ 208) 448
6989 22:15:55.425732 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6990 22:15:55.428962 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6991 22:15:55.432285 iDelay=217, Bit 10, Center -20 (-247 ~ 208) 456
6992 22:15:55.435698 iDelay=217, Bit 11, Center -24 (-247 ~ 200) 448
6993 22:15:55.441977 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
6994 22:15:55.445329 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6995 22:15:55.448697 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6996 22:15:55.455698 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6997 22:15:55.456259 ==
6998 22:15:55.458756 Dram Type= 6, Freq= 0, CH_1, rank 1
6999 22:15:55.461415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7000 22:15:55.461952 ==
7001 22:15:55.462328 DQS Delay:
7002 22:15:55.465076 DQS0 = 28, DQS1 = 36
7003 22:15:55.465605 DQM Delay:
7004 22:15:55.468554 DQM0 = 11, DQM1 = 14
7005 22:15:55.469304 DQ Delay:
7006 22:15:55.472007 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7007 22:15:55.475262 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =12
7008 22:15:55.478347 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =12
7009 22:15:55.482195 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
7010 22:15:55.482724
7011 22:15:55.483094
7012 22:15:55.488285 [DQSOSCAuto] RK1, (LSB)MR18= 0xc455, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 385 ps
7013 22:15:55.491698 CH1 RK1: MR19=C0C, MR18=C455
7014 22:15:55.498337 CH1_RK1: MR19=0xC0C, MR18=0xC455, DQSOSC=385, MR23=63, INC=398, DEC=265
7015 22:15:55.501453 [RxdqsGatingPostProcess] freq 400
7016 22:15:55.508392 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7017 22:15:55.508994 best DQS0 dly(2T, 0.5T) = (0, 10)
7018 22:15:55.511229 best DQS1 dly(2T, 0.5T) = (0, 10)
7019 22:15:55.515210 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7020 22:15:55.518240 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7021 22:15:55.521616 best DQS0 dly(2T, 0.5T) = (0, 10)
7022 22:15:55.524468 best DQS1 dly(2T, 0.5T) = (0, 10)
7023 22:15:55.527736 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7024 22:15:55.531528 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7025 22:15:55.535088 Pre-setting of DQS Precalculation
7026 22:15:55.541381 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7027 22:15:55.547928 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7028 22:15:55.554750 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7029 22:15:55.555326
7030 22:15:55.555700
7031 22:15:55.557669 [Calibration Summary] 800 Mbps
7032 22:15:55.558135 CH 0, Rank 0
7033 22:15:55.561294 SW Impedance : PASS
7034 22:15:55.561805 DUTY Scan : NO K
7035 22:15:55.564297 ZQ Calibration : PASS
7036 22:15:55.567943 Jitter Meter : NO K
7037 22:15:55.568408 CBT Training : PASS
7038 22:15:55.571003 Write leveling : PASS
7039 22:15:55.574879 RX DQS gating : PASS
7040 22:15:55.575440 RX DQ/DQS(RDDQC) : PASS
7041 22:15:55.577578 TX DQ/DQS : PASS
7042 22:15:55.581716 RX DATLAT : PASS
7043 22:15:55.582274 RX DQ/DQS(Engine): PASS
7044 22:15:55.584984 TX OE : NO K
7045 22:15:55.585593 All Pass.
7046 22:15:55.585976
7047 22:15:55.587774 CH 0, Rank 1
7048 22:15:55.588236 SW Impedance : PASS
7049 22:15:55.591169 DUTY Scan : NO K
7050 22:15:55.594561 ZQ Calibration : PASS
7051 22:15:55.595118 Jitter Meter : NO K
7052 22:15:55.597996 CBT Training : PASS
7053 22:15:55.601346 Write leveling : NO K
7054 22:15:55.601858 RX DQS gating : PASS
7055 22:15:55.605051 RX DQ/DQS(RDDQC) : PASS
7056 22:15:55.605666 TX DQ/DQS : PASS
7057 22:15:55.608198 RX DATLAT : PASS
7058 22:15:55.610790 RX DQ/DQS(Engine): PASS
7059 22:15:55.611254 TX OE : NO K
7060 22:15:55.614218 All Pass.
7061 22:15:55.614678
7062 22:15:55.615047 CH 1, Rank 0
7063 22:15:55.618170 SW Impedance : PASS
7064 22:15:55.618793 DUTY Scan : NO K
7065 22:15:55.621175 ZQ Calibration : PASS
7066 22:15:55.624292 Jitter Meter : NO K
7067 22:15:55.624732 CBT Training : PASS
7068 22:15:55.628004 Write leveling : PASS
7069 22:15:55.631439 RX DQS gating : PASS
7070 22:15:55.631977 RX DQ/DQS(RDDQC) : PASS
7071 22:15:55.634185 TX DQ/DQS : PASS
7072 22:15:55.638099 RX DATLAT : PASS
7073 22:15:55.638630 RX DQ/DQS(Engine): PASS
7074 22:15:55.640861 TX OE : NO K
7075 22:15:55.641290 All Pass.
7076 22:15:55.641683
7077 22:15:55.644824 CH 1, Rank 1
7078 22:15:55.645360 SW Impedance : PASS
7079 22:15:55.648192 DUTY Scan : NO K
7080 22:15:55.651105 ZQ Calibration : PASS
7081 22:15:55.651534 Jitter Meter : NO K
7082 22:15:55.654574 CBT Training : PASS
7083 22:15:55.655005 Write leveling : NO K
7084 22:15:55.657961 RX DQS gating : PASS
7085 22:15:55.660883 RX DQ/DQS(RDDQC) : PASS
7086 22:15:55.661310 TX DQ/DQS : PASS
7087 22:15:55.664489 RX DATLAT : PASS
7088 22:15:55.667678 RX DQ/DQS(Engine): PASS
7089 22:15:55.668107 TX OE : NO K
7090 22:15:55.671397 All Pass.
7091 22:15:55.671820
7092 22:15:55.672161 DramC Write-DBI off
7093 22:15:55.674281 PER_BANK_REFRESH: Hybrid Mode
7094 22:15:55.677317 TX_TRACKING: ON
7095 22:15:55.684208 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7096 22:15:55.687685 [FAST_K] Save calibration result to emmc
7097 22:15:55.691320 dramc_set_vcore_voltage set vcore to 725000
7098 22:15:55.694122 Read voltage for 1600, 0
7099 22:15:55.694594 Vio18 = 0
7100 22:15:55.697687 Vcore = 725000
7101 22:15:55.698244 Vdram = 0
7102 22:15:55.698642 Vddq = 0
7103 22:15:55.701190 Vmddr = 0
7104 22:15:55.704504 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7105 22:15:55.710910 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7106 22:15:55.711344 MEM_TYPE=3, freq_sel=13
7107 22:15:55.714302 sv_algorithm_assistance_LP4_3733
7108 22:15:55.720906 ============ PULL DRAM RESETB DOWN ============
7109 22:15:55.724077 ========== PULL DRAM RESETB DOWN end =========
7110 22:15:55.727085 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7111 22:15:55.730826 ===================================
7112 22:15:55.734512 LPDDR4 DRAM CONFIGURATION
7113 22:15:55.737642 ===================================
7114 22:15:55.740672 EX_ROW_EN[0] = 0x0
7115 22:15:55.741141 EX_ROW_EN[1] = 0x0
7116 22:15:55.744076 LP4Y_EN = 0x0
7117 22:15:55.744552 WORK_FSP = 0x1
7118 22:15:55.747530 WL = 0x5
7119 22:15:55.748000 RL = 0x5
7120 22:15:55.750466 BL = 0x2
7121 22:15:55.750893 RPST = 0x0
7122 22:15:55.753833 RD_PRE = 0x0
7123 22:15:55.754258 WR_PRE = 0x1
7124 22:15:55.757884 WR_PST = 0x1
7125 22:15:55.758412 DBI_WR = 0x0
7126 22:15:55.760719 DBI_RD = 0x0
7127 22:15:55.761144 OTF = 0x1
7128 22:15:55.764167 ===================================
7129 22:15:55.767065 ===================================
7130 22:15:55.770441 ANA top config
7131 22:15:55.773697 ===================================
7132 22:15:55.774214 DLL_ASYNC_EN = 0
7133 22:15:55.777559 ALL_SLAVE_EN = 0
7134 22:15:55.780582 NEW_RANK_MODE = 1
7135 22:15:55.784200 DLL_IDLE_MODE = 1
7136 22:15:55.787933 LP45_APHY_COMB_EN = 1
7137 22:15:55.788457 TX_ODT_DIS = 0
7138 22:15:55.790919 NEW_8X_MODE = 1
7139 22:15:55.793435 ===================================
7140 22:15:55.797588 ===================================
7141 22:15:55.800990 data_rate = 3200
7142 22:15:55.803835 CKR = 1
7143 22:15:55.807201 DQ_P2S_RATIO = 8
7144 22:15:55.810225 ===================================
7145 22:15:55.814056 CA_P2S_RATIO = 8
7146 22:15:55.814518 DQ_CA_OPEN = 0
7147 22:15:55.817265 DQ_SEMI_OPEN = 0
7148 22:15:55.820344 CA_SEMI_OPEN = 0
7149 22:15:55.824107 CA_FULL_RATE = 0
7150 22:15:55.827617 DQ_CKDIV4_EN = 0
7151 22:15:55.828189 CA_CKDIV4_EN = 0
7152 22:15:55.830455 CA_PREDIV_EN = 0
7153 22:15:55.834229 PH8_DLY = 12
7154 22:15:55.837547 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7155 22:15:55.840437 DQ_AAMCK_DIV = 4
7156 22:15:55.843888 CA_AAMCK_DIV = 4
7157 22:15:55.844499 CA_ADMCK_DIV = 4
7158 22:15:55.846778 DQ_TRACK_CA_EN = 0
7159 22:15:55.850172 CA_PICK = 1600
7160 22:15:55.853794 CA_MCKIO = 1600
7161 22:15:55.857615 MCKIO_SEMI = 0
7162 22:15:55.860196 PLL_FREQ = 3068
7163 22:15:55.863813 DQ_UI_PI_RATIO = 32
7164 22:15:55.867179 CA_UI_PI_RATIO = 0
7165 22:15:55.870389 ===================================
7166 22:15:55.873405 ===================================
7167 22:15:55.874035 memory_type:LPDDR4
7168 22:15:55.876951 GP_NUM : 10
7169 22:15:55.877413 SRAM_EN : 1
7170 22:15:55.880153 MD32_EN : 0
7171 22:15:55.884064 ===================================
7172 22:15:55.887163 [ANA_INIT] >>>>>>>>>>>>>>
7173 22:15:55.890696 <<<<<< [CONFIGURE PHASE]: ANA_TX
7174 22:15:55.893610 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7175 22:15:55.897266 ===================================
7176 22:15:55.897967 data_rate = 3200,PCW = 0X7600
7177 22:15:55.900771 ===================================
7178 22:15:55.903432 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7179 22:15:55.910457 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7180 22:15:55.916884 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7181 22:15:55.920039 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7182 22:15:55.923205 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7183 22:15:55.926795 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7184 22:15:55.930291 [ANA_INIT] flow start
7185 22:15:55.933673 [ANA_INIT] PLL >>>>>>>>
7186 22:15:55.934204 [ANA_INIT] PLL <<<<<<<<
7187 22:15:55.936619 [ANA_INIT] MIDPI >>>>>>>>
7188 22:15:55.940307 [ANA_INIT] MIDPI <<<<<<<<
7189 22:15:55.940829 [ANA_INIT] DLL >>>>>>>>
7190 22:15:55.943799 [ANA_INIT] DLL <<<<<<<<
7191 22:15:55.946780 [ANA_INIT] flow end
7192 22:15:55.949949 ============ LP4 DIFF to SE enter ============
7193 22:15:55.953150 ============ LP4 DIFF to SE exit ============
7194 22:15:55.956542 [ANA_INIT] <<<<<<<<<<<<<
7195 22:15:55.960033 [Flow] Enable top DCM control >>>>>
7196 22:15:55.963398 [Flow] Enable top DCM control <<<<<
7197 22:15:55.966697 Enable DLL master slave shuffle
7198 22:15:55.969612 ==============================================================
7199 22:15:55.973172 Gating Mode config
7200 22:15:55.979931 ==============================================================
7201 22:15:55.980451 Config description:
7202 22:15:55.990084 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7203 22:15:55.997033 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7204 22:15:55.999842 SELPH_MODE 0: By rank 1: By Phase
7205 22:15:56.006446 ==============================================================
7206 22:15:56.010413 GAT_TRACK_EN = 1
7207 22:15:56.013236 RX_GATING_MODE = 2
7208 22:15:56.016659 RX_GATING_TRACK_MODE = 2
7209 22:15:56.019941 SELPH_MODE = 1
7210 22:15:56.023507 PICG_EARLY_EN = 1
7211 22:15:56.026474 VALID_LAT_VALUE = 1
7212 22:15:56.029786 ==============================================================
7213 22:15:56.033091 Enter into Gating configuration >>>>
7214 22:15:56.036722 Exit from Gating configuration <<<<
7215 22:15:56.039893 Enter into DVFS_PRE_config >>>>>
7216 22:15:56.053165 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7217 22:15:56.053641 Exit from DVFS_PRE_config <<<<<
7218 22:15:56.056273 Enter into PICG configuration >>>>
7219 22:15:56.059778 Exit from PICG configuration <<<<
7220 22:15:56.062816 [RX_INPUT] configuration >>>>>
7221 22:15:56.066104 [RX_INPUT] configuration <<<<<
7222 22:15:56.073258 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7223 22:15:56.076428 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7224 22:15:56.082751 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7225 22:15:56.089597 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7226 22:15:56.096402 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7227 22:15:56.102603 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7228 22:15:56.106352 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7229 22:15:56.109614 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7230 22:15:56.113028 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7231 22:15:56.120035 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7232 22:15:56.122586 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7233 22:15:56.126159 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7234 22:15:56.129634 ===================================
7235 22:15:56.132916 LPDDR4 DRAM CONFIGURATION
7236 22:15:56.136005 ===================================
7237 22:15:56.136526 EX_ROW_EN[0] = 0x0
7238 22:15:56.139372 EX_ROW_EN[1] = 0x0
7239 22:15:56.142601 LP4Y_EN = 0x0
7240 22:15:56.143044 WORK_FSP = 0x1
7241 22:15:56.146141 WL = 0x5
7242 22:15:56.146681 RL = 0x5
7243 22:15:56.149214 BL = 0x2
7244 22:15:56.149772 RPST = 0x0
7245 22:15:56.152578 RD_PRE = 0x0
7246 22:15:56.153000 WR_PRE = 0x1
7247 22:15:56.156150 WR_PST = 0x1
7248 22:15:56.156679 DBI_WR = 0x0
7249 22:15:56.159591 DBI_RD = 0x0
7250 22:15:56.160122 OTF = 0x1
7251 22:15:56.162259 ===================================
7252 22:15:56.165584 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7253 22:15:56.172482 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7254 22:15:56.175916 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7255 22:15:56.179566 ===================================
7256 22:15:56.182383 LPDDR4 DRAM CONFIGURATION
7257 22:15:56.186104 ===================================
7258 22:15:56.186638 EX_ROW_EN[0] = 0x10
7259 22:15:56.188968 EX_ROW_EN[1] = 0x0
7260 22:15:56.189385 LP4Y_EN = 0x0
7261 22:15:56.193063 WORK_FSP = 0x1
7262 22:15:56.193618 WL = 0x5
7263 22:15:56.196273 RL = 0x5
7264 22:15:56.199273 BL = 0x2
7265 22:15:56.199801 RPST = 0x0
7266 22:15:56.202149 RD_PRE = 0x0
7267 22:15:56.202573 WR_PRE = 0x1
7268 22:15:56.206169 WR_PST = 0x1
7269 22:15:56.206692 DBI_WR = 0x0
7270 22:15:56.209873 DBI_RD = 0x0
7271 22:15:56.210422 OTF = 0x1
7272 22:15:56.212484 ===================================
7273 22:15:56.219815 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7274 22:15:56.220360 ==
7275 22:15:56.222470 Dram Type= 6, Freq= 0, CH_0, rank 0
7276 22:15:56.225981 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7277 22:15:56.226404 ==
7278 22:15:56.229101 [Duty_Offset_Calibration]
7279 22:15:56.232420 B0:2 B1:1 CA:1
7280 22:15:56.232944
7281 22:15:56.236051 [DutyScan_Calibration_Flow] k_type=0
7282 22:15:56.244019
7283 22:15:56.244547 ==CLK 0==
7284 22:15:56.247180 Final CLK duty delay cell = 0
7285 22:15:56.250550 [0] MAX Duty = 5156%(X100), DQS PI = 22
7286 22:15:56.253853 [0] MIN Duty = 4907%(X100), DQS PI = 0
7287 22:15:56.254276 [0] AVG Duty = 5031%(X100)
7288 22:15:56.257311
7289 22:15:56.260509 CH0 CLK Duty spec in!! Max-Min= 249%
7290 22:15:56.264062 [DutyScan_Calibration_Flow] ====Done====
7291 22:15:56.264581
7292 22:15:56.267132 [DutyScan_Calibration_Flow] k_type=1
7293 22:15:56.283646
7294 22:15:56.284176 ==DQS 0 ==
7295 22:15:56.287023 Final DQS duty delay cell = -4
7296 22:15:56.290119 [-4] MAX Duty = 5125%(X100), DQS PI = 26
7297 22:15:56.293059 [-4] MIN Duty = 4657%(X100), DQS PI = 0
7298 22:15:56.296541 [-4] AVG Duty = 4891%(X100)
7299 22:15:56.296961
7300 22:15:56.297296 ==DQS 1 ==
7301 22:15:56.300038 Final DQS duty delay cell = 0
7302 22:15:56.302669 [0] MAX Duty = 5218%(X100), DQS PI = 22
7303 22:15:56.306037 [0] MIN Duty = 5062%(X100), DQS PI = 34
7304 22:15:56.309860 [0] AVG Duty = 5140%(X100)
7305 22:15:56.310371
7306 22:15:56.313461 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7307 22:15:56.314028
7308 22:15:56.316084 CH0 DQS 1 Duty spec in!! Max-Min= 156%
7309 22:15:56.319906 [DutyScan_Calibration_Flow] ====Done====
7310 22:15:56.320427
7311 22:15:56.322601 [DutyScan_Calibration_Flow] k_type=3
7312 22:15:56.339945
7313 22:15:56.340492 ==DQM 0 ==
7314 22:15:56.343120 Final DQM duty delay cell = 0
7315 22:15:56.346472 [0] MAX Duty = 5218%(X100), DQS PI = 34
7316 22:15:56.349796 [0] MIN Duty = 4907%(X100), DQS PI = 56
7317 22:15:56.350263 [0] AVG Duty = 5062%(X100)
7318 22:15:56.353268
7319 22:15:56.353779 ==DQM 1 ==
7320 22:15:56.356508 Final DQM duty delay cell = -4
7321 22:15:56.360229 [-4] MAX Duty = 4969%(X100), DQS PI = 22
7322 22:15:56.363437 [-4] MIN Duty = 4844%(X100), DQS PI = 34
7323 22:15:56.366460 [-4] AVG Duty = 4906%(X100)
7324 22:15:56.366884
7325 22:15:56.369988 CH0 DQM 0 Duty spec in!! Max-Min= 311%
7326 22:15:56.370411
7327 22:15:56.372936 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7328 22:15:56.376329 [DutyScan_Calibration_Flow] ====Done====
7329 22:15:56.376752
7330 22:15:56.379588 [DutyScan_Calibration_Flow] k_type=2
7331 22:15:56.397555
7332 22:15:56.398082 ==DQ 0 ==
7333 22:15:56.401074 Final DQ duty delay cell = 0
7334 22:15:56.403794 [0] MAX Duty = 5062%(X100), DQS PI = 26
7335 22:15:56.407578 [0] MIN Duty = 4907%(X100), DQS PI = 0
7336 22:15:56.408104 [0] AVG Duty = 4984%(X100)
7337 22:15:56.408445
7338 22:15:56.410455 ==DQ 1 ==
7339 22:15:56.414112 Final DQ duty delay cell = 0
7340 22:15:56.417327 [0] MAX Duty = 5125%(X100), DQS PI = 6
7341 22:15:56.420829 [0] MIN Duty = 4938%(X100), DQS PI = 34
7342 22:15:56.421354 [0] AVG Duty = 5031%(X100)
7343 22:15:56.421879
7344 22:15:56.424250 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7345 22:15:56.427088
7346 22:15:56.430648 CH0 DQ 1 Duty spec in!! Max-Min= 187%
7347 22:15:56.434453 [DutyScan_Calibration_Flow] ====Done====
7348 22:15:56.434976 ==
7349 22:15:56.437322 Dram Type= 6, Freq= 0, CH_1, rank 0
7350 22:15:56.440668 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7351 22:15:56.441091 ==
7352 22:15:56.444470 [Duty_Offset_Calibration]
7353 22:15:56.444996 B0:1 B1:0 CA:0
7354 22:15:56.445337
7355 22:15:56.447587 [DutyScan_Calibration_Flow] k_type=0
7356 22:15:56.456508
7357 22:15:56.457038 ==CLK 0==
7358 22:15:56.459980 Final CLK duty delay cell = -4
7359 22:15:56.462972 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7360 22:15:56.466350 [-4] MIN Duty = 4844%(X100), DQS PI = 50
7361 22:15:56.469687 [-4] AVG Duty = 4922%(X100)
7362 22:15:56.470148
7363 22:15:56.472951 CH1 CLK Duty spec in!! Max-Min= 156%
7364 22:15:56.476140 [DutyScan_Calibration_Flow] ====Done====
7365 22:15:56.476552
7366 22:15:56.479594 [DutyScan_Calibration_Flow] k_type=1
7367 22:15:56.496913
7368 22:15:56.497421 ==DQS 0 ==
7369 22:15:56.500085 Final DQS duty delay cell = 0
7370 22:15:56.503308 [0] MAX Duty = 5094%(X100), DQS PI = 22
7371 22:15:56.506985 [0] MIN Duty = 4844%(X100), DQS PI = 44
7372 22:15:56.510096 [0] AVG Duty = 4969%(X100)
7373 22:15:56.510613
7374 22:15:56.510944 ==DQS 1 ==
7375 22:15:56.513173 Final DQS duty delay cell = 0
7376 22:15:56.516432 [0] MAX Duty = 5249%(X100), DQS PI = 16
7377 22:15:56.520173 [0] MIN Duty = 4969%(X100), DQS PI = 6
7378 22:15:56.523513 [0] AVG Duty = 5109%(X100)
7379 22:15:56.524034
7380 22:15:56.526332 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7381 22:15:56.526798
7382 22:15:56.529609 CH1 DQS 1 Duty spec in!! Max-Min= 280%
7383 22:15:56.533692 [DutyScan_Calibration_Flow] ====Done====
7384 22:15:56.534206
7385 22:15:56.536635 [DutyScan_Calibration_Flow] k_type=3
7386 22:15:56.553652
7387 22:15:56.554201 ==DQM 0 ==
7388 22:15:56.556944 Final DQM duty delay cell = 0
7389 22:15:56.560419 [0] MAX Duty = 5218%(X100), DQS PI = 16
7390 22:15:56.563691 [0] MIN Duty = 4969%(X100), DQS PI = 48
7391 22:15:56.564149 [0] AVG Duty = 5093%(X100)
7392 22:15:56.566984
7393 22:15:56.567437 ==DQM 1 ==
7394 22:15:56.570367 Final DQM duty delay cell = 0
7395 22:15:56.573603 [0] MAX Duty = 5093%(X100), DQS PI = 40
7396 22:15:56.577108 [0] MIN Duty = 4938%(X100), DQS PI = 32
7397 22:15:56.580361 [0] AVG Duty = 5015%(X100)
7398 22:15:56.580948
7399 22:15:56.583389 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7400 22:15:56.583801
7401 22:15:56.587018 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7402 22:15:56.590464 [DutyScan_Calibration_Flow] ====Done====
7403 22:15:56.590883
7404 22:15:56.593751 [DutyScan_Calibration_Flow] k_type=2
7405 22:15:56.610448
7406 22:15:56.610958 ==DQ 0 ==
7407 22:15:56.613160 Final DQ duty delay cell = -4
7408 22:15:56.616258 [-4] MAX Duty = 5062%(X100), DQS PI = 12
7409 22:15:56.619887 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7410 22:15:56.623079 [-4] AVG Duty = 4968%(X100)
7411 22:15:56.623549
7412 22:15:56.623930 ==DQ 1 ==
7413 22:15:56.626244 Final DQ duty delay cell = 0
7414 22:15:56.629629 [0] MAX Duty = 5124%(X100), DQS PI = 18
7415 22:15:56.632884 [0] MIN Duty = 4938%(X100), DQS PI = 10
7416 22:15:56.636638 [0] AVG Duty = 5031%(X100)
7417 22:15:56.637163
7418 22:15:56.639940 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7419 22:15:56.640465
7420 22:15:56.643191 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7421 22:15:56.646752 [DutyScan_Calibration_Flow] ====Done====
7422 22:15:56.649444 nWR fixed to 30
7423 22:15:56.653240 [ModeRegInit_LP4] CH0 RK0
7424 22:15:56.653823 [ModeRegInit_LP4] CH0 RK1
7425 22:15:56.656742 [ModeRegInit_LP4] CH1 RK0
7426 22:15:56.659462 [ModeRegInit_LP4] CH1 RK1
7427 22:15:56.659886 match AC timing 5
7428 22:15:56.665999 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7429 22:15:56.669471 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7430 22:15:56.672852 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7431 22:15:56.679401 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7432 22:15:56.682724 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7433 22:15:56.683145 [MiockJmeterHQA]
7434 22:15:56.683482
7435 22:15:56.685862 [DramcMiockJmeter] u1RxGatingPI = 0
7436 22:15:56.689481 0 : 4255, 4027
7437 22:15:56.690074 4 : 4363, 4137
7438 22:15:56.692799 8 : 4252, 4027
7439 22:15:56.693228 12 : 4363, 4137
7440 22:15:56.693600 16 : 4252, 4027
7441 22:15:56.696190 20 : 4253, 4026
7442 22:15:56.696596 24 : 4252, 4027
7443 22:15:56.699664 28 : 4363, 4137
7444 22:15:56.700235 32 : 4363, 4137
7445 22:15:56.702715 36 : 4252, 4027
7446 22:15:56.703143 40 : 4253, 4026
7447 22:15:56.706323 44 : 4252, 4027
7448 22:15:56.706748 48 : 4252, 4027
7449 22:15:56.707088 52 : 4255, 4030
7450 22:15:56.709819 56 : 4363, 4137
7451 22:15:56.710249 60 : 4253, 4026
7452 22:15:56.712392 64 : 4252, 4027
7453 22:15:56.712828 68 : 4253, 4029
7454 22:15:56.716262 72 : 4252, 4030
7455 22:15:56.716801 76 : 4250, 4027
7456 22:15:56.719909 80 : 4360, 4137
7457 22:15:56.720447 84 : 4361, 4137
7458 22:15:56.720796 88 : 4253, 115
7459 22:15:56.722752 92 : 4250, 0
7460 22:15:56.723292 96 : 4253, 0
7461 22:15:56.723642 100 : 4250, 0
7462 22:15:56.726006 104 : 4361, 0
7463 22:15:56.726441 108 : 4361, 0
7464 22:15:56.729348 112 : 4250, 0
7465 22:15:56.729814 116 : 4250, 0
7466 22:15:56.730166 120 : 4250, 0
7467 22:15:56.732906 124 : 4250, 0
7468 22:15:56.733333 128 : 4250, 0
7469 22:15:56.736220 132 : 4250, 0
7470 22:15:56.736755 136 : 4250, 0
7471 22:15:56.737107 140 : 4252, 0
7472 22:15:56.739622 144 : 4250, 0
7473 22:15:56.740158 148 : 4253, 0
7474 22:15:56.742411 152 : 4360, 0
7475 22:15:56.743075 156 : 4250, 0
7476 22:15:56.743442 160 : 4250, 0
7477 22:15:56.746123 164 : 4361, 0
7478 22:15:56.746554 168 : 4250, 0
7479 22:15:56.749616 172 : 4250, 0
7480 22:15:56.750083 176 : 4250, 0
7481 22:15:56.750439 180 : 4250, 0
7482 22:15:56.753060 184 : 4250, 0
7483 22:15:56.753645 188 : 4253, 0
7484 22:15:56.753999 192 : 4250, 0
7485 22:15:56.755673 196 : 4250, 0
7486 22:15:56.756107 200 : 4252, 0
7487 22:15:56.759430 204 : 4250, 1551
7488 22:15:56.759864 208 : 4250, 4007
7489 22:15:56.762430 212 : 4361, 4137
7490 22:15:56.762862 216 : 4361, 4138
7491 22:15:56.766186 220 : 4250, 4027
7492 22:15:56.766619 224 : 4250, 4026
7493 22:15:56.766968 228 : 4363, 4140
7494 22:15:56.769332 232 : 4250, 4027
7495 22:15:56.769785 236 : 4250, 4027
7496 22:15:56.772456 240 : 4250, 4026
7497 22:15:56.772891 244 : 4253, 4029
7498 22:15:56.776133 248 : 4250, 4027
7499 22:15:56.776730 252 : 4250, 4027
7500 22:15:56.779410 256 : 4360, 4137
7501 22:15:56.779843 260 : 4250, 4027
7502 22:15:56.782666 264 : 4250, 4027
7503 22:15:56.783102 268 : 4361, 4137
7504 22:15:56.786101 272 : 4250, 4027
7505 22:15:56.786579 276 : 4250, 4027
7506 22:15:56.789004 280 : 4363, 4140
7507 22:15:56.789438 284 : 4250, 4026
7508 22:15:56.789823 288 : 4250, 4027
7509 22:15:56.792332 292 : 4250, 4026
7510 22:15:56.792769 296 : 4253, 4029
7511 22:15:56.796622 300 : 4250, 4027
7512 22:15:56.797167 304 : 4250, 4027
7513 22:15:56.799059 308 : 4360, 4108
7514 22:15:56.799499 312 : 4250, 1893
7515 22:15:56.799852
7516 22:15:56.802683 MIOCK jitter meter ch=0
7517 22:15:56.803250
7518 22:15:56.806158 1T = (312-88) = 224 dly cells
7519 22:15:56.812413 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7520 22:15:56.812971 ==
7521 22:15:56.815844 Dram Type= 6, Freq= 0, CH_0, rank 0
7522 22:15:56.819238 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7523 22:15:56.819781 ==
7524 22:15:56.826006 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7525 22:15:56.829624 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7526 22:15:56.832795 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7527 22:15:56.839174 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7528 22:15:56.847639 [CA 0] Center 42 (12~73) winsize 62
7529 22:15:56.850756 [CA 1] Center 43 (12~74) winsize 63
7530 22:15:56.854458 [CA 2] Center 37 (8~67) winsize 60
7531 22:15:56.857314 [CA 3] Center 37 (7~67) winsize 61
7532 22:15:56.861104 [CA 4] Center 36 (6~66) winsize 61
7533 22:15:56.864462 [CA 5] Center 35 (6~64) winsize 59
7534 22:15:56.864998
7535 22:15:56.867437 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7536 22:15:56.867868
7537 22:15:56.871009 [CATrainingPosCal] consider 1 rank data
7538 22:15:56.874055 u2DelayCellTimex100 = 290/100 ps
7539 22:15:56.877644 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7540 22:15:56.884550 CA1 delay=43 (12~74),Diff = 8 PI (26 cell)
7541 22:15:56.887955 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7542 22:15:56.890377 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7543 22:15:56.894274 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7544 22:15:56.897199 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7545 22:15:56.897778
7546 22:15:56.900960 CA PerBit enable=1, Macro0, CA PI delay=35
7547 22:15:56.901500
7548 22:15:56.903955 [CBTSetCACLKResult] CA Dly = 35
7549 22:15:56.907346 CS Dly: 9 (0~40)
7550 22:15:56.910738 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7551 22:15:56.914029 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7552 22:15:56.914568 ==
7553 22:15:56.917121 Dram Type= 6, Freq= 0, CH_0, rank 1
7554 22:15:56.920541 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7555 22:15:56.921081 ==
7556 22:15:56.927168 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7557 22:15:56.930856 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7558 22:15:56.937215 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7559 22:15:56.940164 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7560 22:15:56.950967 [CA 0] Center 43 (13~73) winsize 61
7561 22:15:56.954121 [CA 1] Center 43 (13~73) winsize 61
7562 22:15:56.957069 [CA 2] Center 38 (8~68) winsize 61
7563 22:15:56.961142 [CA 3] Center 38 (8~68) winsize 61
7564 22:15:56.964178 [CA 4] Center 36 (6~66) winsize 61
7565 22:15:56.967469 [CA 5] Center 35 (6~65) winsize 60
7566 22:15:56.967900
7567 22:15:56.970564 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7568 22:15:56.971195
7569 22:15:56.974050 [CATrainingPosCal] consider 2 rank data
7570 22:15:56.977430 u2DelayCellTimex100 = 290/100 ps
7571 22:15:56.980260 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7572 22:15:56.986841 CA1 delay=43 (13~73),Diff = 8 PI (26 cell)
7573 22:15:56.990380 CA2 delay=37 (8~67),Diff = 2 PI (6 cell)
7574 22:15:56.994124 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7575 22:15:56.997432 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7576 22:15:57.001118 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7577 22:15:57.001689
7578 22:15:57.003885 CA PerBit enable=1, Macro0, CA PI delay=35
7579 22:15:57.004316
7580 22:15:57.007373 [CBTSetCACLKResult] CA Dly = 35
7581 22:15:57.010627 CS Dly: 10 (0~42)
7582 22:15:57.013915 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7583 22:15:57.017159 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7584 22:15:57.017622
7585 22:15:57.020978 ----->DramcWriteLeveling(PI) begin...
7586 22:15:57.021544 ==
7587 22:15:57.024290 Dram Type= 6, Freq= 0, CH_0, rank 0
7588 22:15:57.027041 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7589 22:15:57.030389 ==
7590 22:15:57.034042 Write leveling (Byte 0): 39 => 39
7591 22:15:57.034570 Write leveling (Byte 1): 29 => 29
7592 22:15:57.037028 DramcWriteLeveling(PI) end<-----
7593 22:15:57.037587
7594 22:15:57.037936 ==
7595 22:15:57.040294 Dram Type= 6, Freq= 0, CH_0, rank 0
7596 22:15:57.047193 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7597 22:15:57.047724 ==
7598 22:15:57.050350 [Gating] SW mode calibration
7599 22:15:57.057407 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7600 22:15:57.060223 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7601 22:15:57.066679 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7602 22:15:57.070501 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7603 22:15:57.073770 1 4 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
7604 22:15:57.077599 1 4 12 | B1->B0 | 2323 3535 | 0 1 | (0 0) (1 1)
7605 22:15:57.083918 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7606 22:15:57.087216 1 4 20 | B1->B0 | 3434 3635 | 1 1 | (1 1) (0 0)
7607 22:15:57.090806 1 4 24 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7608 22:15:57.097118 1 4 28 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7609 22:15:57.100635 1 5 0 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
7610 22:15:57.103999 1 5 4 | B1->B0 | 3434 3535 | 1 1 | (1 1) (0 0)
7611 22:15:57.109948 1 5 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
7612 22:15:57.113851 1 5 12 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
7613 22:15:57.117301 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7614 22:15:57.123983 1 5 20 | B1->B0 | 2626 2424 | 0 0 | (0 0) (0 0)
7615 22:15:57.126881 1 5 24 | B1->B0 | 2323 2928 | 0 1 | (0 0) (1 1)
7616 22:15:57.130063 1 5 28 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7617 22:15:57.136933 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7618 22:15:57.140020 1 6 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
7619 22:15:57.143594 1 6 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (1 1)
7620 22:15:57.149940 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7621 22:15:57.153799 1 6 16 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
7622 22:15:57.156777 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7623 22:15:57.163056 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7624 22:15:57.166624 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7625 22:15:57.170356 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7626 22:15:57.177015 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7627 22:15:57.179919 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7628 22:15:57.183597 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7629 22:15:57.189548 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7630 22:15:57.193335 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7631 22:15:57.196295 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7632 22:15:57.203371 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7633 22:15:57.206503 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7634 22:15:57.209577 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7635 22:15:57.213506 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7636 22:15:57.219633 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7637 22:15:57.223127 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7638 22:15:57.226610 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7639 22:15:57.232984 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7640 22:15:57.236862 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7641 22:15:57.239854 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7642 22:15:57.246252 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7643 22:15:57.249758 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7644 22:15:57.253081 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7645 22:15:57.259795 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7646 22:15:57.262963 Total UI for P1: 0, mck2ui 16
7647 22:15:57.266469 best dqsien dly found for B0: ( 1, 9, 12)
7648 22:15:57.269620 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7649 22:15:57.272991 Total UI for P1: 0, mck2ui 16
7650 22:15:57.276168 best dqsien dly found for B1: ( 1, 9, 16)
7651 22:15:57.279960 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7652 22:15:57.282767 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
7653 22:15:57.283198
7654 22:15:57.285830 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7655 22:15:57.289624 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
7656 22:15:57.292677 [Gating] SW calibration Done
7657 22:15:57.293259 ==
7658 22:15:57.295659 Dram Type= 6, Freq= 0, CH_0, rank 0
7659 22:15:57.302324 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7660 22:15:57.302947 ==
7661 22:15:57.303435 RX Vref Scan: 0
7662 22:15:57.303913
7663 22:15:57.305607 RX Vref 0 -> 0, step: 1
7664 22:15:57.306192
7665 22:15:57.308978 RX Delay 0 -> 252, step: 8
7666 22:15:57.312527 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7667 22:15:57.315931 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7668 22:15:57.319177 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
7669 22:15:57.322624 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7670 22:15:57.328824 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7671 22:15:57.332294 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7672 22:15:57.335716 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7673 22:15:57.338883 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7674 22:15:57.342095 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7675 22:15:57.349113 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7676 22:15:57.352420 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7677 22:15:57.355383 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7678 22:15:57.358997 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
7679 22:15:57.362260 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7680 22:15:57.368668 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7681 22:15:57.372400 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7682 22:15:57.372839 ==
7683 22:15:57.375378 Dram Type= 6, Freq= 0, CH_0, rank 0
7684 22:15:57.379325 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7685 22:15:57.379759 ==
7686 22:15:57.382161 DQS Delay:
7687 22:15:57.382589 DQS0 = 0, DQS1 = 0
7688 22:15:57.382938 DQM Delay:
7689 22:15:57.385819 DQM0 = 137, DQM1 = 130
7690 22:15:57.386289 DQ Delay:
7691 22:15:57.388598 DQ0 =135, DQ1 =143, DQ2 =135, DQ3 =131
7692 22:15:57.392311 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =143
7693 22:15:57.395357 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =123
7694 22:15:57.402802 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =135
7695 22:15:57.403232
7696 22:15:57.403572
7697 22:15:57.403888 ==
7698 22:15:57.405844 Dram Type= 6, Freq= 0, CH_0, rank 0
7699 22:15:57.408811 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7700 22:15:57.409241 ==
7701 22:15:57.409616
7702 22:15:57.409942
7703 22:15:57.412562 TX Vref Scan disable
7704 22:15:57.413097 == TX Byte 0 ==
7705 22:15:57.418489 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
7706 22:15:57.421930 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
7707 22:15:57.422535 == TX Byte 1 ==
7708 22:15:57.428742 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7709 22:15:57.432308 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7710 22:15:57.432750 ==
7711 22:15:57.435361 Dram Type= 6, Freq= 0, CH_0, rank 0
7712 22:15:57.438748 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7713 22:15:57.439183 ==
7714 22:15:57.453831
7715 22:15:57.456663 TX Vref early break, caculate TX vref
7716 22:15:57.460080 TX Vref=16, minBit 4, minWin=22, winSum=377
7717 22:15:57.463565 TX Vref=18, minBit 0, minWin=23, winSum=386
7718 22:15:57.466643 TX Vref=20, minBit 0, minWin=24, winSum=399
7719 22:15:57.470280 TX Vref=22, minBit 3, minWin=24, winSum=408
7720 22:15:57.473213 TX Vref=24, minBit 0, minWin=25, winSum=414
7721 22:15:57.480264 TX Vref=26, minBit 3, minWin=25, winSum=424
7722 22:15:57.483702 TX Vref=28, minBit 2, minWin=25, winSum=423
7723 22:15:57.487250 TX Vref=30, minBit 4, minWin=24, winSum=408
7724 22:15:57.490007 TX Vref=32, minBit 4, minWin=24, winSum=403
7725 22:15:57.493659 TX Vref=34, minBit 4, minWin=23, winSum=392
7726 22:15:57.500476 [TxChooseVref] Worse bit 3, Min win 25, Win sum 424, Final Vref 26
7727 22:15:57.500920
7728 22:15:57.503362 Final TX Range 0 Vref 26
7729 22:15:57.503792
7730 22:15:57.504136 ==
7731 22:15:57.506896 Dram Type= 6, Freq= 0, CH_0, rank 0
7732 22:15:57.510094 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7733 22:15:57.510529 ==
7734 22:15:57.510880
7735 22:15:57.511202
7736 22:15:57.513751 TX Vref Scan disable
7737 22:15:57.520145 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7738 22:15:57.520454 == TX Byte 0 ==
7739 22:15:57.523571 u2DelayCellOfst[0]=13 cells (4 PI)
7740 22:15:57.526759 u2DelayCellOfst[1]=16 cells (5 PI)
7741 22:15:57.530368 u2DelayCellOfst[2]=13 cells (4 PI)
7742 22:15:57.533248 u2DelayCellOfst[3]=10 cells (3 PI)
7743 22:15:57.536715 u2DelayCellOfst[4]=10 cells (3 PI)
7744 22:15:57.539921 u2DelayCellOfst[5]=0 cells (0 PI)
7745 22:15:57.543520 u2DelayCellOfst[6]=16 cells (5 PI)
7746 22:15:57.543757 u2DelayCellOfst[7]=16 cells (5 PI)
7747 22:15:57.550190 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7748 22:15:57.553453 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
7749 22:15:57.553689 == TX Byte 1 ==
7750 22:15:57.556755 u2DelayCellOfst[8]=0 cells (0 PI)
7751 22:15:57.560348 u2DelayCellOfst[9]=0 cells (0 PI)
7752 22:15:57.563702 u2DelayCellOfst[10]=6 cells (2 PI)
7753 22:15:57.566546 u2DelayCellOfst[11]=3 cells (1 PI)
7754 22:15:57.569945 u2DelayCellOfst[12]=10 cells (3 PI)
7755 22:15:57.573741 u2DelayCellOfst[13]=10 cells (3 PI)
7756 22:15:57.576849 u2DelayCellOfst[14]=13 cells (4 PI)
7757 22:15:57.580211 u2DelayCellOfst[15]=10 cells (3 PI)
7758 22:15:57.583142 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7759 22:15:57.590556 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7760 22:15:57.591031 DramC Write-DBI on
7761 22:15:57.591332 ==
7762 22:15:57.593446 Dram Type= 6, Freq= 0, CH_0, rank 0
7763 22:15:57.597381 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7764 22:15:57.597966 ==
7765 22:15:57.600147
7766 22:15:57.600691
7767 22:15:57.601037 TX Vref Scan disable
7768 22:15:57.603406 == TX Byte 0 ==
7769 22:15:57.606540 Update DQM dly =738 (2 ,6, 34) DQM OEN =(3 ,3)
7770 22:15:57.610222 == TX Byte 1 ==
7771 22:15:57.614029 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7772 22:15:57.614558 DramC Write-DBI off
7773 22:15:57.617072
7774 22:15:57.617622 [DATLAT]
7775 22:15:57.617974 Freq=1600, CH0 RK0
7776 22:15:57.618301
7777 22:15:57.620825 DATLAT Default: 0xf
7778 22:15:57.621495 0, 0xFFFF, sum = 0
7779 22:15:57.623246 1, 0xFFFF, sum = 0
7780 22:15:57.623868 2, 0xFFFF, sum = 0
7781 22:15:57.626901 3, 0xFFFF, sum = 0
7782 22:15:57.629854 4, 0xFFFF, sum = 0
7783 22:15:57.630473 5, 0xFFFF, sum = 0
7784 22:15:57.633421 6, 0xFFFF, sum = 0
7785 22:15:57.634022 7, 0xFFFF, sum = 0
7786 22:15:57.636246 8, 0xFFFF, sum = 0
7787 22:15:57.636849 9, 0xFFFF, sum = 0
7788 22:15:57.639764 10, 0xFFFF, sum = 0
7789 22:15:57.640276 11, 0xFFFF, sum = 0
7790 22:15:57.643302 12, 0xFFFF, sum = 0
7791 22:15:57.643921 13, 0xFFFF, sum = 0
7792 22:15:57.646306 14, 0x0, sum = 1
7793 22:15:57.646769 15, 0x0, sum = 2
7794 22:15:57.649504 16, 0x0, sum = 3
7795 22:15:57.650098 17, 0x0, sum = 4
7796 22:15:57.653076 best_step = 15
7797 22:15:57.653451
7798 22:15:57.653818 ==
7799 22:15:57.656158 Dram Type= 6, Freq= 0, CH_0, rank 0
7800 22:15:57.659546 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7801 22:15:57.659978 ==
7802 22:15:57.662789 RX Vref Scan: 1
7803 22:15:57.663244
7804 22:15:57.663590 Set Vref Range= 24 -> 127
7805 22:15:57.663987
7806 22:15:57.666290 RX Vref 24 -> 127, step: 1
7807 22:15:57.666716
7808 22:15:57.669577 RX Delay 19 -> 252, step: 4
7809 22:15:57.670108
7810 22:15:57.672718 Set Vref, RX VrefLevel [Byte0]: 24
7811 22:15:57.676391 [Byte1]: 24
7812 22:15:57.676872
7813 22:15:57.679689 Set Vref, RX VrefLevel [Byte0]: 25
7814 22:15:57.683311 [Byte1]: 25
7815 22:15:57.683744
7816 22:15:57.686162 Set Vref, RX VrefLevel [Byte0]: 26
7817 22:15:57.689350 [Byte1]: 26
7818 22:15:57.693392
7819 22:15:57.693867 Set Vref, RX VrefLevel [Byte0]: 27
7820 22:15:57.696901 [Byte1]: 27
7821 22:15:57.701244
7822 22:15:57.701712 Set Vref, RX VrefLevel [Byte0]: 28
7823 22:15:57.704087 [Byte1]: 28
7824 22:15:57.708617
7825 22:15:57.709049 Set Vref, RX VrefLevel [Byte0]: 29
7826 22:15:57.711960 [Byte1]: 29
7827 22:15:57.716068
7828 22:15:57.716498 Set Vref, RX VrefLevel [Byte0]: 30
7829 22:15:57.719876 [Byte1]: 30
7830 22:15:57.723670
7831 22:15:57.724100 Set Vref, RX VrefLevel [Byte0]: 31
7832 22:15:57.727141 [Byte1]: 31
7833 22:15:57.731499
7834 22:15:57.731928 Set Vref, RX VrefLevel [Byte0]: 32
7835 22:15:57.735048 [Byte1]: 32
7836 22:15:57.738997
7837 22:15:57.739427 Set Vref, RX VrefLevel [Byte0]: 33
7838 22:15:57.742332 [Byte1]: 33
7839 22:15:57.746392
7840 22:15:57.746818 Set Vref, RX VrefLevel [Byte0]: 34
7841 22:15:57.749656 [Byte1]: 34
7842 22:15:57.754229
7843 22:15:57.754657 Set Vref, RX VrefLevel [Byte0]: 35
7844 22:15:57.757745 [Byte1]: 35
7845 22:15:57.761563
7846 22:15:57.761989 Set Vref, RX VrefLevel [Byte0]: 36
7847 22:15:57.764928 [Byte1]: 36
7848 22:15:57.769333
7849 22:15:57.769817 Set Vref, RX VrefLevel [Byte0]: 37
7850 22:15:57.772549 [Byte1]: 37
7851 22:15:57.776913
7852 22:15:57.777337 Set Vref, RX VrefLevel [Byte0]: 38
7853 22:15:57.780033 [Byte1]: 38
7854 22:15:57.784149
7855 22:15:57.784720 Set Vref, RX VrefLevel [Byte0]: 39
7856 22:15:57.787699 [Byte1]: 39
7857 22:15:57.791721
7858 22:15:57.792284 Set Vref, RX VrefLevel [Byte0]: 40
7859 22:15:57.795126 [Byte1]: 40
7860 22:15:57.799448
7861 22:15:57.799953 Set Vref, RX VrefLevel [Byte0]: 41
7862 22:15:57.802993 [Byte1]: 41
7863 22:15:57.807429
7864 22:15:57.807982 Set Vref, RX VrefLevel [Byte0]: 42
7865 22:15:57.810651 [Byte1]: 42
7866 22:15:57.814726
7867 22:15:57.815157 Set Vref, RX VrefLevel [Byte0]: 43
7868 22:15:57.818185 [Byte1]: 43
7869 22:15:57.822494
7870 22:15:57.822988 Set Vref, RX VrefLevel [Byte0]: 44
7871 22:15:57.825701 [Byte1]: 44
7872 22:15:57.830507
7873 22:15:57.831054 Set Vref, RX VrefLevel [Byte0]: 45
7874 22:15:57.833435 [Byte1]: 45
7875 22:15:57.838002
7876 22:15:57.838558 Set Vref, RX VrefLevel [Byte0]: 46
7877 22:15:57.840754 [Byte1]: 46
7878 22:15:57.845097
7879 22:15:57.845561 Set Vref, RX VrefLevel [Byte0]: 47
7880 22:15:57.848366 [Byte1]: 47
7881 22:15:57.852752
7882 22:15:57.853169 Set Vref, RX VrefLevel [Byte0]: 48
7883 22:15:57.855820 [Byte1]: 48
7884 22:15:57.860750
7885 22:15:57.861268 Set Vref, RX VrefLevel [Byte0]: 49
7886 22:15:57.863305 [Byte1]: 49
7887 22:15:57.867890
7888 22:15:57.868309 Set Vref, RX VrefLevel [Byte0]: 50
7889 22:15:57.871446 [Byte1]: 50
7890 22:15:57.875384
7891 22:15:57.876024 Set Vref, RX VrefLevel [Byte0]: 51
7892 22:15:57.878657 [Byte1]: 51
7893 22:15:57.883220
7894 22:15:57.883642 Set Vref, RX VrefLevel [Byte0]: 52
7895 22:15:57.885960 [Byte1]: 52
7896 22:15:57.890548
7897 22:15:57.890967 Set Vref, RX VrefLevel [Byte0]: 53
7898 22:15:57.893915 [Byte1]: 53
7899 22:15:57.898059
7900 22:15:57.898574 Set Vref, RX VrefLevel [Byte0]: 54
7901 22:15:57.901450 [Byte1]: 54
7902 22:15:57.906033
7903 22:15:57.906546 Set Vref, RX VrefLevel [Byte0]: 55
7904 22:15:57.909578 [Byte1]: 55
7905 22:15:57.913119
7906 22:15:57.913820 Set Vref, RX VrefLevel [Byte0]: 56
7907 22:15:57.916681 [Byte1]: 56
7908 22:15:57.921189
7909 22:15:57.921688 Set Vref, RX VrefLevel [Byte0]: 57
7910 22:15:57.924309 [Byte1]: 57
7911 22:15:57.928031
7912 22:15:57.928525 Set Vref, RX VrefLevel [Byte0]: 58
7913 22:15:57.931851 [Byte1]: 58
7914 22:15:57.936203
7915 22:15:57.936753 Set Vref, RX VrefLevel [Byte0]: 59
7916 22:15:57.939305 [Byte1]: 59
7917 22:15:57.943327
7918 22:15:57.943813 Set Vref, RX VrefLevel [Byte0]: 60
7919 22:15:57.946823 [Byte1]: 60
7920 22:15:57.950712
7921 22:15:57.950802 Set Vref, RX VrefLevel [Byte0]: 61
7922 22:15:57.953937 [Byte1]: 61
7923 22:15:57.958482
7924 22:15:57.958565 Set Vref, RX VrefLevel [Byte0]: 62
7925 22:15:57.961329 [Byte1]: 62
7926 22:15:57.965726
7927 22:15:57.965809 Set Vref, RX VrefLevel [Byte0]: 63
7928 22:15:57.969033 [Byte1]: 63
7929 22:15:57.973421
7930 22:15:57.973527 Set Vref, RX VrefLevel [Byte0]: 64
7931 22:15:57.976650 [Byte1]: 64
7932 22:15:57.980850
7933 22:15:57.980935 Set Vref, RX VrefLevel [Byte0]: 65
7934 22:15:57.984490 [Byte1]: 65
7935 22:15:57.988329
7936 22:15:57.988416 Set Vref, RX VrefLevel [Byte0]: 66
7937 22:15:57.991755 [Byte1]: 66
7938 22:15:57.996636
7939 22:15:57.996725 Set Vref, RX VrefLevel [Byte0]: 67
7940 22:15:57.999471 [Byte1]: 67
7941 22:15:58.003719
7942 22:15:58.003815 Set Vref, RX VrefLevel [Byte0]: 68
7943 22:15:58.006871 [Byte1]: 68
7944 22:15:58.011288
7945 22:15:58.011402 Set Vref, RX VrefLevel [Byte0]: 69
7946 22:15:58.014416 [Byte1]: 69
7947 22:15:58.018738
7948 22:15:58.018862 Set Vref, RX VrefLevel [Byte0]: 70
7949 22:15:58.022271 [Byte1]: 70
7950 22:15:58.026368
7951 22:15:58.026528 Set Vref, RX VrefLevel [Byte0]: 71
7952 22:15:58.029959 [Byte1]: 71
7953 22:15:58.034331
7954 22:15:58.034598 Set Vref, RX VrefLevel [Byte0]: 72
7955 22:15:58.037475 [Byte1]: 72
7956 22:15:58.041890
7957 22:15:58.042131 Set Vref, RX VrefLevel [Byte0]: 73
7958 22:15:58.045089 [Byte1]: 73
7959 22:15:58.049297
7960 22:15:58.049745 Set Vref, RX VrefLevel [Byte0]: 74
7961 22:15:58.052589 [Byte1]: 74
7962 22:15:58.056717
7963 22:15:58.057149 Set Vref, RX VrefLevel [Byte0]: 75
7964 22:15:58.060160 [Byte1]: 75
7965 22:15:58.064581
7966 22:15:58.065009 Set Vref, RX VrefLevel [Byte0]: 76
7967 22:15:58.068163 [Byte1]: 76
7968 22:15:58.071903
7969 22:15:58.072523 Set Vref, RX VrefLevel [Byte0]: 77
7970 22:15:58.075521 [Byte1]: 77
7971 22:15:58.079774
7972 22:15:58.080207 Set Vref, RX VrefLevel [Byte0]: 78
7973 22:15:58.082835 [Byte1]: 78
7974 22:15:58.087459
7975 22:15:58.087886 Final RX Vref Byte 0 = 54 to rank0
7976 22:15:58.090408 Final RX Vref Byte 1 = 61 to rank0
7977 22:15:58.093747 Final RX Vref Byte 0 = 54 to rank1
7978 22:15:58.097075 Final RX Vref Byte 1 = 61 to rank1==
7979 22:15:58.100520 Dram Type= 6, Freq= 0, CH_0, rank 0
7980 22:15:58.107492 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7981 22:15:58.107947 ==
7982 22:15:58.108401 DQS Delay:
7983 22:15:58.108908 DQS0 = 0, DQS1 = 0
7984 22:15:58.110350 DQM Delay:
7985 22:15:58.110776 DQM0 = 133, DQM1 = 127
7986 22:15:58.113986 DQ Delay:
7987 22:15:58.117317 DQ0 =134, DQ1 =136, DQ2 =132, DQ3 =130
7988 22:15:58.120283 DQ4 =132, DQ5 =122, DQ6 =142, DQ7 =138
7989 22:15:58.123751 DQ8 =116, DQ9 =118, DQ10 =128, DQ11 =120
7990 22:15:58.127694 DQ12 =130, DQ13 =132, DQ14 =138, DQ15 =134
7991 22:15:58.128286
7992 22:15:58.128821
7993 22:15:58.129345
7994 22:15:58.130388 [DramC_TX_OE_Calibration] TA2
7995 22:15:58.133724 Original DQ_B0 (3 6) =30, OEN = 27
7996 22:15:58.137383 Original DQ_B1 (3 6) =30, OEN = 27
7997 22:15:58.140415 24, 0x0, End_B0=24 End_B1=24
7998 22:15:58.140988 25, 0x0, End_B0=25 End_B1=25
7999 22:15:58.144091 26, 0x0, End_B0=26 End_B1=26
8000 22:15:58.147153 27, 0x0, End_B0=27 End_B1=27
8001 22:15:58.150266 28, 0x0, End_B0=28 End_B1=28
8002 22:15:58.150684 29, 0x0, End_B0=29 End_B1=29
8003 22:15:58.154021 30, 0x0, End_B0=30 End_B1=30
8004 22:15:58.156811 31, 0x4141, End_B0=30 End_B1=30
8005 22:15:58.160848 Byte0 end_step=30 best_step=27
8006 22:15:58.163452 Byte1 end_step=30 best_step=27
8007 22:15:58.166752 Byte0 TX OE(2T, 0.5T) = (3, 3)
8008 22:15:58.167149 Byte1 TX OE(2T, 0.5T) = (3, 3)
8009 22:15:58.170426
8010 22:15:58.170763
8011 22:15:58.176916 [DQSOSCAuto] RK0, (LSB)MR18= 0x2521, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
8012 22:15:58.179810 CH0 RK0: MR19=303, MR18=2521
8013 22:15:58.186536 CH0_RK0: MR19=0x303, MR18=0x2521, DQSOSC=391, MR23=63, INC=24, DEC=16
8014 22:15:58.186628
8015 22:15:58.190401 ----->DramcWriteLeveling(PI) begin...
8016 22:15:58.190511 ==
8017 22:15:58.193355 Dram Type= 6, Freq= 0, CH_0, rank 1
8018 22:15:58.196574 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8019 22:15:58.196660 ==
8020 22:15:58.200046 Write leveling (Byte 0): 34 => 34
8021 22:15:58.203321 Write leveling (Byte 1): 30 => 30
8022 22:15:58.206251 DramcWriteLeveling(PI) end<-----
8023 22:15:58.206334
8024 22:15:58.206400 ==
8025 22:15:58.210233 Dram Type= 6, Freq= 0, CH_0, rank 1
8026 22:15:58.213085 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8027 22:15:58.213169 ==
8028 22:15:58.216810 [Gating] SW mode calibration
8029 22:15:58.223705 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8030 22:15:58.230167 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8031 22:15:58.233096 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8032 22:15:58.236477 1 4 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8033 22:15:58.243191 1 4 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
8034 22:15:58.247007 1 4 12 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (1 1)
8035 22:15:58.249837 1 4 16 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
8036 22:15:58.256647 1 4 20 | B1->B0 | 3434 3837 | 1 1 | (1 1) (1 1)
8037 22:15:58.259905 1 4 24 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
8038 22:15:58.262959 1 4 28 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
8039 22:15:58.269937 1 5 0 | B1->B0 | 3434 3635 | 1 1 | (1 1) (0 0)
8040 22:15:58.273288 1 5 4 | B1->B0 | 3434 3737 | 1 0 | (1 1) (0 0)
8041 22:15:58.276534 1 5 8 | B1->B0 | 3434 3838 | 1 1 | (1 1) (0 0)
8042 22:15:58.283244 1 5 12 | B1->B0 | 3434 3131 | 1 1 | (1 0) (1 0)
8043 22:15:58.286020 1 5 16 | B1->B0 | 3030 2929 | 1 0 | (1 1) (0 0)
8044 22:15:58.289879 1 5 20 | B1->B0 | 2323 302f | 0 1 | (0 0) (0 0)
8045 22:15:58.295922 1 5 24 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8046 22:15:58.299532 1 5 28 | B1->B0 | 2323 2625 | 0 1 | (0 0) (0 0)
8047 22:15:58.302894 1 6 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8048 22:15:58.309162 1 6 4 | B1->B0 | 2323 2a29 | 0 1 | (0 0) (0 0)
8049 22:15:58.312432 1 6 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
8050 22:15:58.316244 1 6 12 | B1->B0 | 2323 3636 | 0 0 | (0 0) (0 0)
8051 22:15:58.322316 1 6 16 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
8052 22:15:58.326006 1 6 20 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8053 22:15:58.329031 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8054 22:15:58.335760 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8055 22:15:58.339596 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8056 22:15:58.342620 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8057 22:15:58.349384 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8058 22:15:58.352439 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8059 22:15:58.355556 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8060 22:15:58.362550 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8061 22:15:58.366076 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8062 22:15:58.369272 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 22:15:58.375551 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 22:15:58.379038 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 22:15:58.382418 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 22:15:58.389030 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 22:15:58.392346 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 22:15:58.395623 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 22:15:58.402433 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 22:15:58.405145 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 22:15:58.408782 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 22:15:58.412254 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 22:15:58.418888 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 22:15:58.421920 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8075 22:15:58.425663 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8076 22:15:58.428649 Total UI for P1: 0, mck2ui 16
8077 22:15:58.431837 best dqsien dly found for B0: ( 1, 9, 12)
8078 22:15:58.438473 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8079 22:15:58.442299 Total UI for P1: 0, mck2ui 16
8080 22:15:58.445007 best dqsien dly found for B1: ( 1, 9, 16)
8081 22:15:58.448611 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8082 22:15:58.451911 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8083 22:15:58.452514
8084 22:15:58.455658 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8085 22:15:58.458820 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8086 22:15:58.462425 [Gating] SW calibration Done
8087 22:15:58.462888 ==
8088 22:15:58.465025 Dram Type= 6, Freq= 0, CH_0, rank 1
8089 22:15:58.468522 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8090 22:15:58.469071 ==
8091 22:15:58.472368 RX Vref Scan: 0
8092 22:15:58.472764
8093 22:15:58.475455 RX Vref 0 -> 0, step: 1
8094 22:15:58.475851
8095 22:15:58.476171 RX Delay 0 -> 252, step: 8
8096 22:15:58.481979 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8097 22:15:58.485827 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8098 22:15:58.488769 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8099 22:15:58.491924 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8100 22:15:58.495346 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8101 22:15:58.501554 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8102 22:15:58.505460 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8103 22:15:58.508522 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8104 22:15:58.511588 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8105 22:15:58.515300 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8106 22:15:58.521600 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8107 22:15:58.524947 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8108 22:15:58.528332 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8109 22:15:58.531688 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8110 22:15:58.534797 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8111 22:15:58.541566 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8112 22:15:58.541781 ==
8113 22:15:58.544564 Dram Type= 6, Freq= 0, CH_0, rank 1
8114 22:15:58.548167 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8115 22:15:58.548466 ==
8116 22:15:58.548721 DQS Delay:
8117 22:15:58.551365 DQS0 = 0, DQS1 = 0
8118 22:15:58.551580 DQM Delay:
8119 22:15:58.554399 DQM0 = 136, DQM1 = 128
8120 22:15:58.554615 DQ Delay:
8121 22:15:58.557871 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8122 22:15:58.561481 DQ4 =139, DQ5 =127, DQ6 =139, DQ7 =143
8123 22:15:58.565094 DQ8 =119, DQ9 =119, DQ10 =127, DQ11 =119
8124 22:15:58.568327 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8125 22:15:58.568548
8126 22:15:58.571047
8127 22:15:58.571283 ==
8128 22:15:58.574874 Dram Type= 6, Freq= 0, CH_0, rank 1
8129 22:15:58.577909 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8130 22:15:58.578130 ==
8131 22:15:58.578305
8132 22:15:58.578468
8133 22:15:58.581117 TX Vref Scan disable
8134 22:15:58.581405 == TX Byte 0 ==
8135 22:15:58.588288 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8136 22:15:58.591356 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8137 22:15:58.591622 == TX Byte 1 ==
8138 22:15:58.597683 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8139 22:15:58.600864 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8140 22:15:58.601131 ==
8141 22:15:58.604685 Dram Type= 6, Freq= 0, CH_0, rank 1
8142 22:15:58.608087 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8143 22:15:58.608354 ==
8144 22:15:58.621570
8145 22:15:58.624931 TX Vref early break, caculate TX vref
8146 22:15:58.628364 TX Vref=16, minBit 0, minWin=23, winSum=386
8147 22:15:58.631694 TX Vref=18, minBit 1, minWin=24, winSum=398
8148 22:15:58.635106 TX Vref=20, minBit 0, minWin=24, winSum=405
8149 22:15:58.638677 TX Vref=22, minBit 0, minWin=25, winSum=418
8150 22:15:58.641799 TX Vref=24, minBit 1, minWin=25, winSum=426
8151 22:15:58.648300 TX Vref=26, minBit 1, minWin=25, winSum=426
8152 22:15:58.651608 TX Vref=28, minBit 1, minWin=26, winSum=429
8153 22:15:58.654974 TX Vref=30, minBit 1, minWin=25, winSum=418
8154 22:15:58.658339 TX Vref=32, minBit 0, minWin=25, winSum=410
8155 22:15:58.661716 TX Vref=34, minBit 7, minWin=24, winSum=400
8156 22:15:58.668537 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 28
8157 22:15:58.668810
8158 22:15:58.671440 Final TX Range 0 Vref 28
8159 22:15:58.671758
8160 22:15:58.672044 ==
8161 22:15:58.675251 Dram Type= 6, Freq= 0, CH_0, rank 1
8162 22:15:58.678382 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8163 22:15:58.678649 ==
8164 22:15:58.678874
8165 22:15:58.679090
8166 22:15:58.681420 TX Vref Scan disable
8167 22:15:58.688163 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8168 22:15:58.688428 == TX Byte 0 ==
8169 22:15:58.691477 u2DelayCellOfst[0]=13 cells (4 PI)
8170 22:15:58.694639 u2DelayCellOfst[1]=13 cells (4 PI)
8171 22:15:58.698174 u2DelayCellOfst[2]=10 cells (3 PI)
8172 22:15:58.701582 u2DelayCellOfst[3]=10 cells (3 PI)
8173 22:15:58.704578 u2DelayCellOfst[4]=6 cells (2 PI)
8174 22:15:58.708040 u2DelayCellOfst[5]=0 cells (0 PI)
8175 22:15:58.711293 u2DelayCellOfst[6]=16 cells (5 PI)
8176 22:15:58.711555 u2DelayCellOfst[7]=16 cells (5 PI)
8177 22:15:58.717986 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8178 22:15:58.721497 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8179 22:15:58.721780 == TX Byte 1 ==
8180 22:15:58.724896 u2DelayCellOfst[8]=0 cells (0 PI)
8181 22:15:58.728203 u2DelayCellOfst[9]=0 cells (0 PI)
8182 22:15:58.731607 u2DelayCellOfst[10]=6 cells (2 PI)
8183 22:15:58.734580 u2DelayCellOfst[11]=3 cells (1 PI)
8184 22:15:58.737922 u2DelayCellOfst[12]=13 cells (4 PI)
8185 22:15:58.741601 u2DelayCellOfst[13]=10 cells (3 PI)
8186 22:15:58.744379 u2DelayCellOfst[14]=13 cells (4 PI)
8187 22:15:58.747917 u2DelayCellOfst[15]=10 cells (3 PI)
8188 22:15:58.751092 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8189 22:15:58.758036 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8190 22:15:58.758121 DramC Write-DBI on
8191 22:15:58.758188 ==
8192 22:15:58.761517 Dram Type= 6, Freq= 0, CH_0, rank 1
8193 22:15:58.764288 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8194 22:15:58.764372 ==
8195 22:15:58.764439
8196 22:15:58.767846
8197 22:15:58.767929 TX Vref Scan disable
8198 22:15:58.770926 == TX Byte 0 ==
8199 22:15:58.774562 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8200 22:15:58.777689 == TX Byte 1 ==
8201 22:15:58.780865 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8202 22:15:58.780948 DramC Write-DBI off
8203 22:15:58.784504
8204 22:15:58.784587 [DATLAT]
8205 22:15:58.784653 Freq=1600, CH0 RK1
8206 22:15:58.784716
8207 22:15:58.787556 DATLAT Default: 0xf
8208 22:15:58.787639 0, 0xFFFF, sum = 0
8209 22:15:58.791264 1, 0xFFFF, sum = 0
8210 22:15:58.791349 2, 0xFFFF, sum = 0
8211 22:15:58.794355 3, 0xFFFF, sum = 0
8212 22:15:58.794441 4, 0xFFFF, sum = 0
8213 22:15:58.797402 5, 0xFFFF, sum = 0
8214 22:15:58.800781 6, 0xFFFF, sum = 0
8215 22:15:58.800866 7, 0xFFFF, sum = 0
8216 22:15:58.804262 8, 0xFFFF, sum = 0
8217 22:15:58.804358 9, 0xFFFF, sum = 0
8218 22:15:58.807696 10, 0xFFFF, sum = 0
8219 22:15:58.807794 11, 0xFFFF, sum = 0
8220 22:15:58.810994 12, 0xFFFF, sum = 0
8221 22:15:58.811100 13, 0xFFFF, sum = 0
8222 22:15:58.814568 14, 0x0, sum = 1
8223 22:15:58.814674 15, 0x0, sum = 2
8224 22:15:58.817771 16, 0x0, sum = 3
8225 22:15:58.817912 17, 0x0, sum = 4
8226 22:15:58.821226 best_step = 15
8227 22:15:58.821349
8228 22:15:58.821465 ==
8229 22:15:58.824353 Dram Type= 6, Freq= 0, CH_0, rank 1
8230 22:15:58.827381 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8231 22:15:58.827560 ==
8232 22:15:58.827717 RX Vref Scan: 0
8233 22:15:58.830871
8234 22:15:58.831036 RX Vref 0 -> 0, step: 1
8235 22:15:58.831162
8236 22:15:58.833852 RX Delay 19 -> 252, step: 4
8237 22:15:58.837580 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8238 22:15:58.844359 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8239 22:15:58.847483 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8240 22:15:58.851004 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8241 22:15:58.854112 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8242 22:15:58.857888 iDelay=191, Bit 5, Center 124 (71 ~ 178) 108
8243 22:15:58.864078 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8244 22:15:58.868064 iDelay=191, Bit 7, Center 142 (95 ~ 190) 96
8245 22:15:58.871197 iDelay=191, Bit 8, Center 118 (67 ~ 170) 104
8246 22:15:58.874167 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8247 22:15:58.877573 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8248 22:15:58.884068 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8249 22:15:58.887602 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8250 22:15:58.890829 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8251 22:15:58.894422 iDelay=191, Bit 14, Center 136 (83 ~ 190) 108
8252 22:15:58.897496 iDelay=191, Bit 15, Center 136 (87 ~ 186) 100
8253 22:15:58.897980 ==
8254 22:15:58.901124 Dram Type= 6, Freq= 0, CH_0, rank 1
8255 22:15:58.907668 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8256 22:15:58.908098 ==
8257 22:15:58.908442 DQS Delay:
8258 22:15:58.911123 DQS0 = 0, DQS1 = 0
8259 22:15:58.911550 DQM Delay:
8260 22:15:58.914291 DQM0 = 134, DQM1 = 127
8261 22:15:58.914774 DQ Delay:
8262 22:15:58.917318 DQ0 =134, DQ1 =136, DQ2 =130, DQ3 =134
8263 22:15:58.920685 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =142
8264 22:15:58.924265 DQ8 =118, DQ9 =116, DQ10 =128, DQ11 =118
8265 22:15:58.927355 DQ12 =134, DQ13 =134, DQ14 =136, DQ15 =136
8266 22:15:58.927809
8267 22:15:58.928203
8268 22:15:58.928551
8269 22:15:58.930893 [DramC_TX_OE_Calibration] TA2
8270 22:15:58.934284 Original DQ_B0 (3 6) =30, OEN = 27
8271 22:15:58.937206 Original DQ_B1 (3 6) =30, OEN = 27
8272 22:15:58.940964 24, 0x0, End_B0=24 End_B1=24
8273 22:15:58.944381 25, 0x0, End_B0=25 End_B1=25
8274 22:15:58.944893 26, 0x0, End_B0=26 End_B1=26
8275 22:15:58.947109 27, 0x0, End_B0=27 End_B1=27
8276 22:15:58.950452 28, 0x0, End_B0=28 End_B1=28
8277 22:15:58.953875 29, 0x0, End_B0=29 End_B1=29
8278 22:15:58.954037 30, 0x0, End_B0=30 End_B1=30
8279 22:15:58.956692 31, 0x4141, End_B0=30 End_B1=30
8280 22:15:58.960284 Byte0 end_step=30 best_step=27
8281 22:15:58.963950 Byte1 end_step=30 best_step=27
8282 22:15:58.967137 Byte0 TX OE(2T, 0.5T) = (3, 3)
8283 22:15:58.970613 Byte1 TX OE(2T, 0.5T) = (3, 3)
8284 22:15:58.970697
8285 22:15:58.970763
8286 22:15:58.977125 [DQSOSCAuto] RK1, (LSB)MR18= 0x2008, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
8287 22:15:58.980265 CH0 RK1: MR19=303, MR18=2008
8288 22:15:58.987030 CH0_RK1: MR19=0x303, MR18=0x2008, DQSOSC=393, MR23=63, INC=23, DEC=15
8289 22:15:58.990267 [RxdqsGatingPostProcess] freq 1600
8290 22:15:58.993748 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8291 22:15:58.997073 best DQS0 dly(2T, 0.5T) = (1, 1)
8292 22:15:59.000072 best DQS1 dly(2T, 0.5T) = (1, 1)
8293 22:15:59.003266 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8294 22:15:59.006948 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8295 22:15:59.010661 best DQS0 dly(2T, 0.5T) = (1, 1)
8296 22:15:59.013482 best DQS1 dly(2T, 0.5T) = (1, 1)
8297 22:15:59.016809 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8298 22:15:59.020202 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8299 22:15:59.023782 Pre-setting of DQS Precalculation
8300 22:15:59.026660 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8301 22:15:59.026822 ==
8302 22:15:59.030194 Dram Type= 6, Freq= 0, CH_1, rank 0
8303 22:15:59.036792 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8304 22:15:59.037008 ==
8305 22:15:59.040057 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8306 22:15:59.043910 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8307 22:15:59.050176 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8308 22:15:59.056847 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8309 22:15:59.064425 [CA 0] Center 42 (13~72) winsize 60
8310 22:15:59.067845 [CA 1] Center 42 (13~72) winsize 60
8311 22:15:59.070801 [CA 2] Center 38 (9~68) winsize 60
8312 22:15:59.074219 [CA 3] Center 38 (9~68) winsize 60
8313 22:15:59.077154 [CA 4] Center 39 (10~68) winsize 59
8314 22:15:59.081138 [CA 5] Center 37 (8~67) winsize 60
8315 22:15:59.081737
8316 22:15:59.084090 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8317 22:15:59.084548
8318 22:15:59.087713 [CATrainingPosCal] consider 1 rank data
8319 22:15:59.090743 u2DelayCellTimex100 = 290/100 ps
8320 22:15:59.094480 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8321 22:15:59.101163 CA1 delay=42 (13~72),Diff = 5 PI (16 cell)
8322 22:15:59.104021 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8323 22:15:59.107929 CA3 delay=38 (9~68),Diff = 1 PI (3 cell)
8324 22:15:59.110937 CA4 delay=39 (10~68),Diff = 2 PI (6 cell)
8325 22:15:59.114049 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8326 22:15:59.114629
8327 22:15:59.117741 CA PerBit enable=1, Macro0, CA PI delay=37
8328 22:15:59.118169
8329 22:15:59.120603 [CBTSetCACLKResult] CA Dly = 37
8330 22:15:59.124095 CS Dly: 11 (0~42)
8331 22:15:59.127280 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8332 22:15:59.130443 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8333 22:15:59.130873 ==
8334 22:15:59.133789 Dram Type= 6, Freq= 0, CH_1, rank 1
8335 22:15:59.137415 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8336 22:15:59.140697 ==
8337 22:15:59.144199 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8338 22:15:59.147117 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8339 22:15:59.153557 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8340 22:15:59.160307 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8341 22:15:59.167489 [CA 0] Center 42 (12~72) winsize 61
8342 22:15:59.170772 [CA 1] Center 41 (12~71) winsize 60
8343 22:15:59.174486 [CA 2] Center 38 (9~68) winsize 60
8344 22:15:59.177616 [CA 3] Center 38 (8~68) winsize 61
8345 22:15:59.181273 [CA 4] Center 38 (8~68) winsize 61
8346 22:15:59.184499 [CA 5] Center 37 (7~67) winsize 61
8347 22:15:59.184917
8348 22:15:59.187664 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8349 22:15:59.188085
8350 22:15:59.190871 [CATrainingPosCal] consider 2 rank data
8351 22:15:59.194331 u2DelayCellTimex100 = 290/100 ps
8352 22:15:59.198092 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8353 22:15:59.204426 CA1 delay=42 (13~71),Diff = 5 PI (16 cell)
8354 22:15:59.207483 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8355 22:15:59.211087 CA3 delay=38 (9~68),Diff = 1 PI (3 cell)
8356 22:15:59.214063 CA4 delay=39 (10~68),Diff = 2 PI (6 cell)
8357 22:15:59.217554 CA5 delay=37 (8~67),Diff = 0 PI (0 cell)
8358 22:15:59.217995
8359 22:15:59.220605 CA PerBit enable=1, Macro0, CA PI delay=37
8360 22:15:59.221099
8361 22:15:59.223887 [CBTSetCACLKResult] CA Dly = 37
8362 22:15:59.227092 CS Dly: 12 (0~44)
8363 22:15:59.230756 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8364 22:15:59.234069 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8365 22:15:59.234582
8366 22:15:59.237587 ----->DramcWriteLeveling(PI) begin...
8367 22:15:59.238087 ==
8368 22:15:59.240440 Dram Type= 6, Freq= 0, CH_1, rank 0
8369 22:15:59.247243 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8370 22:15:59.247539 ==
8371 22:15:59.250278 Write leveling (Byte 0): 27 => 27
8372 22:15:59.250678 Write leveling (Byte 1): 26 => 26
8373 22:15:59.253986 DramcWriteLeveling(PI) end<-----
8374 22:15:59.254292
8375 22:15:59.254532 ==
8376 22:15:59.257114 Dram Type= 6, Freq= 0, CH_1, rank 0
8377 22:15:59.263608 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8378 22:15:59.263901 ==
8379 22:15:59.266972 [Gating] SW mode calibration
8380 22:15:59.273842 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8381 22:15:59.276781 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8382 22:15:59.284098 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8383 22:15:59.287105 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8384 22:15:59.290222 1 4 8 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
8385 22:15:59.296959 1 4 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8386 22:15:59.300205 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8387 22:15:59.303558 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8388 22:15:59.310509 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8389 22:15:59.313767 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8390 22:15:59.316831 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8391 22:15:59.320546 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8392 22:15:59.327391 1 5 8 | B1->B0 | 3434 3131 | 1 1 | (1 0) (1 0)
8393 22:15:59.330395 1 5 12 | B1->B0 | 2424 2323 | 0 0 | (1 0) (1 0)
8394 22:15:59.333637 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8395 22:15:59.340645 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8396 22:15:59.344079 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8397 22:15:59.347418 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8398 22:15:59.353837 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8399 22:15:59.357750 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8400 22:15:59.361112 1 6 8 | B1->B0 | 2525 4141 | 0 0 | (0 0) (0 0)
8401 22:15:59.367247 1 6 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
8402 22:15:59.370455 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8403 22:15:59.373932 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8404 22:15:59.380702 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8405 22:15:59.383613 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8406 22:15:59.387562 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8407 22:15:59.394052 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8408 22:15:59.397190 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8409 22:15:59.400445 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8410 22:15:59.407154 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8411 22:15:59.410344 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8412 22:15:59.413778 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8413 22:15:59.420556 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 22:15:59.423342 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 22:15:59.427351 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 22:15:59.434119 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 22:15:59.437430 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 22:15:59.440148 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 22:15:59.443720 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 22:15:59.450281 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 22:15:59.453938 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 22:15:59.457066 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 22:15:59.463351 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 22:15:59.467053 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8425 22:15:59.470217 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8426 22:15:59.477143 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8427 22:15:59.477699 Total UI for P1: 0, mck2ui 16
8428 22:15:59.483903 best dqsien dly found for B0: ( 1, 9, 10)
8429 22:15:59.484346 Total UI for P1: 0, mck2ui 16
8430 22:15:59.490577 best dqsien dly found for B1: ( 1, 9, 10)
8431 22:15:59.493608 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8432 22:15:59.496955 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8433 22:15:59.497472
8434 22:15:59.500617 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8435 22:15:59.504131 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8436 22:15:59.507013 [Gating] SW calibration Done
8437 22:15:59.507440 ==
8438 22:15:59.510309 Dram Type= 6, Freq= 0, CH_1, rank 0
8439 22:15:59.513820 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8440 22:15:59.514244 ==
8441 22:15:59.517552 RX Vref Scan: 0
8442 22:15:59.518092
8443 22:15:59.518434 RX Vref 0 -> 0, step: 1
8444 22:15:59.518753
8445 22:15:59.520268 RX Delay 0 -> 252, step: 8
8446 22:15:59.523761 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8447 22:15:59.530394 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8448 22:15:59.533901 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8449 22:15:59.536788 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8450 22:15:59.540790 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8451 22:15:59.544308 iDelay=200, Bit 5, Center 151 (104 ~ 199) 96
8452 22:15:59.551075 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8453 22:15:59.553376 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8454 22:15:59.556820 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8455 22:15:59.560049 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8456 22:15:59.563494 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8457 22:15:59.567390 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8458 22:15:59.573727 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8459 22:15:59.577218 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8460 22:15:59.580279 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8461 22:15:59.583627 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8462 22:15:59.584050 ==
8463 22:15:59.587011 Dram Type= 6, Freq= 0, CH_1, rank 0
8464 22:15:59.593601 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8465 22:15:59.594027 ==
8466 22:15:59.594367 DQS Delay:
8467 22:15:59.596798 DQS0 = 0, DQS1 = 0
8468 22:15:59.597317 DQM Delay:
8469 22:15:59.597703 DQM0 = 136, DQM1 = 132
8470 22:15:59.600760 DQ Delay:
8471 22:15:59.603743 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8472 22:15:59.606951 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8473 22:15:59.609931 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8474 22:15:59.613717 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8475 22:15:59.614239
8476 22:15:59.614581
8477 22:15:59.614895 ==
8478 22:15:59.616887 Dram Type= 6, Freq= 0, CH_1, rank 0
8479 22:15:59.619846 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8480 22:15:59.623194 ==
8481 22:15:59.623616
8482 22:15:59.623951
8483 22:15:59.624268 TX Vref Scan disable
8484 22:15:59.627114 == TX Byte 0 ==
8485 22:15:59.630043 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8486 22:15:59.633710 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8487 22:15:59.637088 == TX Byte 1 ==
8488 22:15:59.640609 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8489 22:15:59.644097 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8490 22:15:59.646956 ==
8491 22:15:59.647494 Dram Type= 6, Freq= 0, CH_1, rank 0
8492 22:15:59.653650 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8493 22:15:59.654186 ==
8494 22:15:59.665201
8495 22:15:59.668540 TX Vref early break, caculate TX vref
8496 22:15:59.671900 TX Vref=16, minBit 0, minWin=23, winSum=379
8497 22:15:59.675564 TX Vref=18, minBit 0, minWin=23, winSum=387
8498 22:15:59.678624 TX Vref=20, minBit 0, minWin=23, winSum=398
8499 22:15:59.681593 TX Vref=22, minBit 1, minWin=24, winSum=407
8500 22:15:59.684831 TX Vref=24, minBit 0, minWin=25, winSum=417
8501 22:15:59.691686 TX Vref=26, minBit 1, minWin=25, winSum=423
8502 22:15:59.695110 TX Vref=28, minBit 0, minWin=25, winSum=427
8503 22:15:59.698553 TX Vref=30, minBit 0, minWin=25, winSum=424
8504 22:15:59.701941 TX Vref=32, minBit 0, minWin=24, winSum=413
8505 22:15:59.704866 TX Vref=34, minBit 0, minWin=23, winSum=403
8506 22:15:59.712250 [TxChooseVref] Worse bit 0, Min win 25, Win sum 427, Final Vref 28
8507 22:15:59.712796
8508 22:15:59.715225 Final TX Range 0 Vref 28
8509 22:15:59.715748
8510 22:15:59.716089 ==
8511 22:15:59.718592 Dram Type= 6, Freq= 0, CH_1, rank 0
8512 22:15:59.722083 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8513 22:15:59.722614 ==
8514 22:15:59.722961
8515 22:15:59.723280
8516 22:15:59.724869 TX Vref Scan disable
8517 22:15:59.731851 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8518 22:15:59.732366 == TX Byte 0 ==
8519 22:15:59.734826 u2DelayCellOfst[0]=20 cells (6 PI)
8520 22:15:59.738282 u2DelayCellOfst[1]=13 cells (4 PI)
8521 22:15:59.742005 u2DelayCellOfst[2]=0 cells (0 PI)
8522 22:15:59.744978 u2DelayCellOfst[3]=10 cells (3 PI)
8523 22:15:59.748672 u2DelayCellOfst[4]=13 cells (4 PI)
8524 22:15:59.751453 u2DelayCellOfst[5]=20 cells (6 PI)
8525 22:15:59.755016 u2DelayCellOfst[6]=20 cells (6 PI)
8526 22:15:59.755446 u2DelayCellOfst[7]=10 cells (3 PI)
8527 22:15:59.761680 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8528 22:15:59.765257 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8529 22:15:59.765825 == TX Byte 1 ==
8530 22:15:59.768111 u2DelayCellOfst[8]=0 cells (0 PI)
8531 22:15:59.771493 u2DelayCellOfst[9]=3 cells (1 PI)
8532 22:15:59.774860 u2DelayCellOfst[10]=10 cells (3 PI)
8533 22:15:59.778283 u2DelayCellOfst[11]=3 cells (1 PI)
8534 22:15:59.781734 u2DelayCellOfst[12]=16 cells (5 PI)
8535 22:15:59.785036 u2DelayCellOfst[13]=16 cells (5 PI)
8536 22:15:59.788272 u2DelayCellOfst[14]=16 cells (5 PI)
8537 22:15:59.791479 u2DelayCellOfst[15]=16 cells (5 PI)
8538 22:15:59.794751 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8539 22:15:59.802093 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8540 22:15:59.802621 DramC Write-DBI on
8541 22:15:59.802964 ==
8542 22:15:59.804527 Dram Type= 6, Freq= 0, CH_1, rank 0
8543 22:15:59.808336 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8544 22:15:59.808765 ==
8545 22:15:59.811259
8546 22:15:59.811679
8547 22:15:59.812017 TX Vref Scan disable
8548 22:15:59.815327 == TX Byte 0 ==
8549 22:15:59.818067 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8550 22:15:59.821739 == TX Byte 1 ==
8551 22:15:59.825114 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8552 22:15:59.825683 DramC Write-DBI off
8553 22:15:59.828243
8554 22:15:59.828761 [DATLAT]
8555 22:15:59.829103 Freq=1600, CH1 RK0
8556 22:15:59.829486
8557 22:15:59.831529 DATLAT Default: 0xf
8558 22:15:59.831971 0, 0xFFFF, sum = 0
8559 22:15:59.834964 1, 0xFFFF, sum = 0
8560 22:15:59.835420 2, 0xFFFF, sum = 0
8561 22:15:59.837997 3, 0xFFFF, sum = 0
8562 22:15:59.838529 4, 0xFFFF, sum = 0
8563 22:15:59.841837 5, 0xFFFF, sum = 0
8564 22:15:59.842370 6, 0xFFFF, sum = 0
8565 22:15:59.845262 7, 0xFFFF, sum = 0
8566 22:15:59.848966 8, 0xFFFF, sum = 0
8567 22:15:59.849493 9, 0xFFFF, sum = 0
8568 22:15:59.851842 10, 0xFFFF, sum = 0
8569 22:15:59.852377 11, 0xFFFF, sum = 0
8570 22:15:59.854917 12, 0xFFFF, sum = 0
8571 22:15:59.855446 13, 0xFFFF, sum = 0
8572 22:15:59.858532 14, 0x0, sum = 1
8573 22:15:59.859062 15, 0x0, sum = 2
8574 22:15:59.861445 16, 0x0, sum = 3
8575 22:15:59.862083 17, 0x0, sum = 4
8576 22:15:59.864623 best_step = 15
8577 22:15:59.865143
8578 22:15:59.865485 ==
8579 22:15:59.868270 Dram Type= 6, Freq= 0, CH_1, rank 0
8580 22:15:59.871156 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8581 22:15:59.871582 ==
8582 22:15:59.871917 RX Vref Scan: 1
8583 22:15:59.872278
8584 22:15:59.874599 Set Vref Range= 24 -> 127
8585 22:15:59.875019
8586 22:15:59.878070 RX Vref 24 -> 127, step: 1
8587 22:15:59.878490
8588 22:15:59.881405 RX Delay 27 -> 252, step: 4
8589 22:15:59.881874
8590 22:15:59.884676 Set Vref, RX VrefLevel [Byte0]: 24
8591 22:15:59.888031 [Byte1]: 24
8592 22:15:59.888470
8593 22:15:59.891249 Set Vref, RX VrefLevel [Byte0]: 25
8594 22:15:59.894558 [Byte1]: 25
8595 22:15:59.894999
8596 22:15:59.897931 Set Vref, RX VrefLevel [Byte0]: 26
8597 22:15:59.901028 [Byte1]: 26
8598 22:15:59.905037
8599 22:15:59.905599 Set Vref, RX VrefLevel [Byte0]: 27
8600 22:15:59.908389 [Byte1]: 27
8601 22:15:59.912856
8602 22:15:59.913376 Set Vref, RX VrefLevel [Byte0]: 28
8603 22:15:59.916278 [Byte1]: 28
8604 22:15:59.919472
8605 22:15:59.919899 Set Vref, RX VrefLevel [Byte0]: 29
8606 22:15:59.923306 [Byte1]: 29
8607 22:15:59.927531
8608 22:15:59.928045 Set Vref, RX VrefLevel [Byte0]: 30
8609 22:15:59.931171 [Byte1]: 30
8610 22:15:59.935100
8611 22:15:59.935519 Set Vref, RX VrefLevel [Byte0]: 31
8612 22:15:59.938059 [Byte1]: 31
8613 22:15:59.942405
8614 22:15:59.942920 Set Vref, RX VrefLevel [Byte0]: 32
8615 22:15:59.945872 [Byte1]: 32
8616 22:15:59.950199
8617 22:15:59.950722 Set Vref, RX VrefLevel [Byte0]: 33
8618 22:15:59.953931 [Byte1]: 33
8619 22:15:59.958098
8620 22:15:59.958618 Set Vref, RX VrefLevel [Byte0]: 34
8621 22:15:59.961078 [Byte1]: 34
8622 22:15:59.965376
8623 22:15:59.966020 Set Vref, RX VrefLevel [Byte0]: 35
8624 22:15:59.968582 [Byte1]: 35
8625 22:15:59.972744
8626 22:15:59.973166 Set Vref, RX VrefLevel [Byte0]: 36
8627 22:15:59.975841 [Byte1]: 36
8628 22:15:59.980187
8629 22:15:59.980608 Set Vref, RX VrefLevel [Byte0]: 37
8630 22:15:59.983313 [Byte1]: 37
8631 22:15:59.987724
8632 22:15:59.988247 Set Vref, RX VrefLevel [Byte0]: 38
8633 22:15:59.991405 [Byte1]: 38
8634 22:15:59.994889
8635 22:15:59.995306 Set Vref, RX VrefLevel [Byte0]: 39
8636 22:15:59.998606 [Byte1]: 39
8637 22:16:00.003045
8638 22:16:00.003567 Set Vref, RX VrefLevel [Byte0]: 40
8639 22:16:00.006175 [Byte1]: 40
8640 22:16:00.010025
8641 22:16:00.010445 Set Vref, RX VrefLevel [Byte0]: 41
8642 22:16:00.013639 [Byte1]: 41
8643 22:16:00.018205
8644 22:16:00.018724 Set Vref, RX VrefLevel [Byte0]: 42
8645 22:16:00.021259 [Byte1]: 42
8646 22:16:00.025950
8647 22:16:00.026470 Set Vref, RX VrefLevel [Byte0]: 43
8648 22:16:00.028590 [Byte1]: 43
8649 22:16:00.032929
8650 22:16:00.033348 Set Vref, RX VrefLevel [Byte0]: 44
8651 22:16:00.036366 [Byte1]: 44
8652 22:16:00.041082
8653 22:16:00.041639 Set Vref, RX VrefLevel [Byte0]: 45
8654 22:16:00.043887 [Byte1]: 45
8655 22:16:00.048186
8656 22:16:00.048705 Set Vref, RX VrefLevel [Byte0]: 46
8657 22:16:00.051448 [Byte1]: 46
8658 22:16:00.055642
8659 22:16:00.056162 Set Vref, RX VrefLevel [Byte0]: 47
8660 22:16:00.059079 [Byte1]: 47
8661 22:16:00.063085
8662 22:16:00.063521 Set Vref, RX VrefLevel [Byte0]: 48
8663 22:16:00.066968 [Byte1]: 48
8664 22:16:00.070375
8665 22:16:00.070897 Set Vref, RX VrefLevel [Byte0]: 49
8666 22:16:00.074043 [Byte1]: 49
8667 22:16:00.078481
8668 22:16:00.079006 Set Vref, RX VrefLevel [Byte0]: 50
8669 22:16:00.081779 [Byte1]: 50
8670 22:16:00.085492
8671 22:16:00.085944 Set Vref, RX VrefLevel [Byte0]: 51
8672 22:16:00.088851 [Byte1]: 51
8673 22:16:00.093439
8674 22:16:00.093904 Set Vref, RX VrefLevel [Byte0]: 52
8675 22:16:00.096847 [Byte1]: 52
8676 22:16:00.101016
8677 22:16:00.101594 Set Vref, RX VrefLevel [Byte0]: 53
8678 22:16:00.104700 [Byte1]: 53
8679 22:16:00.108492
8680 22:16:00.109018 Set Vref, RX VrefLevel [Byte0]: 54
8681 22:16:00.111368 [Byte1]: 54
8682 22:16:00.115744
8683 22:16:00.116270 Set Vref, RX VrefLevel [Byte0]: 55
8684 22:16:00.119342 [Byte1]: 55
8685 22:16:00.123353
8686 22:16:00.123891 Set Vref, RX VrefLevel [Byte0]: 56
8687 22:16:00.126770 [Byte1]: 56
8688 22:16:00.131104
8689 22:16:00.131682 Set Vref, RX VrefLevel [Byte0]: 57
8690 22:16:00.133868 [Byte1]: 57
8691 22:16:00.138188
8692 22:16:00.138606 Set Vref, RX VrefLevel [Byte0]: 58
8693 22:16:00.141958 [Byte1]: 58
8694 22:16:00.146241
8695 22:16:00.146765 Set Vref, RX VrefLevel [Byte0]: 59
8696 22:16:00.149372 [Byte1]: 59
8697 22:16:00.153722
8698 22:16:00.154143 Set Vref, RX VrefLevel [Byte0]: 60
8699 22:16:00.156690 [Byte1]: 60
8700 22:16:00.160743
8701 22:16:00.161159 Set Vref, RX VrefLevel [Byte0]: 61
8702 22:16:00.164165 [Byte1]: 61
8703 22:16:00.168672
8704 22:16:00.169200 Set Vref, RX VrefLevel [Byte0]: 62
8705 22:16:00.172093 [Byte1]: 62
8706 22:16:00.176356
8707 22:16:00.176878 Set Vref, RX VrefLevel [Byte0]: 63
8708 22:16:00.179681 [Byte1]: 63
8709 22:16:00.183932
8710 22:16:00.184476 Set Vref, RX VrefLevel [Byte0]: 64
8711 22:16:00.186861 [Byte1]: 64
8712 22:16:00.190738
8713 22:16:00.191179 Set Vref, RX VrefLevel [Byte0]: 65
8714 22:16:00.194061 [Byte1]: 65
8715 22:16:00.198590
8716 22:16:00.199010 Set Vref, RX VrefLevel [Byte0]: 66
8717 22:16:00.201986 [Byte1]: 66
8718 22:16:00.205792
8719 22:16:00.206322 Set Vref, RX VrefLevel [Byte0]: 67
8720 22:16:00.209420 [Byte1]: 67
8721 22:16:00.213193
8722 22:16:00.213641 Set Vref, RX VrefLevel [Byte0]: 68
8723 22:16:00.216825 [Byte1]: 68
8724 22:16:00.221115
8725 22:16:00.221564 Set Vref, RX VrefLevel [Byte0]: 69
8726 22:16:00.224543 [Byte1]: 69
8727 22:16:00.228439
8728 22:16:00.228857 Set Vref, RX VrefLevel [Byte0]: 70
8729 22:16:00.232133 [Byte1]: 70
8730 22:16:00.236291
8731 22:16:00.236709 Set Vref, RX VrefLevel [Byte0]: 71
8732 22:16:00.240081 [Byte1]: 71
8733 22:16:00.243860
8734 22:16:00.244384 Set Vref, RX VrefLevel [Byte0]: 72
8735 22:16:00.247490 [Byte1]: 72
8736 22:16:00.251591
8737 22:16:00.252138 Set Vref, RX VrefLevel [Byte0]: 73
8738 22:16:00.254228 [Byte1]: 73
8739 22:16:00.259076
8740 22:16:00.259686 Set Vref, RX VrefLevel [Byte0]: 74
8741 22:16:00.261835 [Byte1]: 74
8742 22:16:00.266563
8743 22:16:00.266982 Set Vref, RX VrefLevel [Byte0]: 75
8744 22:16:00.269677 [Byte1]: 75
8745 22:16:00.273761
8746 22:16:00.274189 Set Vref, RX VrefLevel [Byte0]: 76
8747 22:16:00.277790 [Byte1]: 76
8748 22:16:00.281485
8749 22:16:00.282052 Set Vref, RX VrefLevel [Byte0]: 77
8750 22:16:00.284810 [Byte1]: 77
8751 22:16:00.289100
8752 22:16:00.289547 Set Vref, RX VrefLevel [Byte0]: 78
8753 22:16:00.292365 [Byte1]: 78
8754 22:16:00.296703
8755 22:16:00.297245 Final RX Vref Byte 0 = 58 to rank0
8756 22:16:00.300141 Final RX Vref Byte 1 = 57 to rank0
8757 22:16:00.302993 Final RX Vref Byte 0 = 58 to rank1
8758 22:16:00.306711 Final RX Vref Byte 1 = 57 to rank1==
8759 22:16:00.309777 Dram Type= 6, Freq= 0, CH_1, rank 0
8760 22:16:00.317058 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8761 22:16:00.317620 ==
8762 22:16:00.317968 DQS Delay:
8763 22:16:00.318296 DQS0 = 0, DQS1 = 0
8764 22:16:00.319521 DQM Delay:
8765 22:16:00.319944 DQM0 = 134, DQM1 = 131
8766 22:16:00.323268 DQ Delay:
8767 22:16:00.326657 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8768 22:16:00.329720 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =134
8769 22:16:00.333088 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8770 22:16:00.336689 DQ12 =138, DQ13 =140, DQ14 =140, DQ15 =140
8771 22:16:00.337160
8772 22:16:00.337558
8773 22:16:00.337916
8774 22:16:00.340308 [DramC_TX_OE_Calibration] TA2
8775 22:16:00.343158 Original DQ_B0 (3 6) =30, OEN = 27
8776 22:16:00.346795 Original DQ_B1 (3 6) =30, OEN = 27
8777 22:16:00.350448 24, 0x0, End_B0=24 End_B1=24
8778 22:16:00.350990 25, 0x0, End_B0=25 End_B1=25
8779 22:16:00.353357 26, 0x0, End_B0=26 End_B1=26
8780 22:16:00.356469 27, 0x0, End_B0=27 End_B1=27
8781 22:16:00.359671 28, 0x0, End_B0=28 End_B1=28
8782 22:16:00.360110 29, 0x0, End_B0=29 End_B1=29
8783 22:16:00.363320 30, 0x0, End_B0=30 End_B1=30
8784 22:16:00.366134 31, 0x4141, End_B0=30 End_B1=30
8785 22:16:00.369935 Byte0 end_step=30 best_step=27
8786 22:16:00.373095 Byte1 end_step=30 best_step=27
8787 22:16:00.376739 Byte0 TX OE(2T, 0.5T) = (3, 3)
8788 22:16:00.377263 Byte1 TX OE(2T, 0.5T) = (3, 3)
8789 22:16:00.379774
8790 22:16:00.380293
8791 22:16:00.386113 [DQSOSCAuto] RK0, (LSB)MR18= 0x1422, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
8792 22:16:00.389746 CH1 RK0: MR19=303, MR18=1422
8793 22:16:00.396450 CH1_RK0: MR19=0x303, MR18=0x1422, DQSOSC=392, MR23=63, INC=24, DEC=16
8794 22:16:00.397042
8795 22:16:00.399436 ----->DramcWriteLeveling(PI) begin...
8796 22:16:00.399967 ==
8797 22:16:00.402573 Dram Type= 6, Freq= 0, CH_1, rank 1
8798 22:16:00.406428 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8799 22:16:00.406958 ==
8800 22:16:00.409869 Write leveling (Byte 0): 26 => 26
8801 22:16:00.413019 Write leveling (Byte 1): 28 => 28
8802 22:16:00.416583 DramcWriteLeveling(PI) end<-----
8803 22:16:00.417129
8804 22:16:00.417479 ==
8805 22:16:00.419260 Dram Type= 6, Freq= 0, CH_1, rank 1
8806 22:16:00.422507 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8807 22:16:00.422937 ==
8808 22:16:00.426382 [Gating] SW mode calibration
8809 22:16:00.432569 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8810 22:16:00.439458 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8811 22:16:00.442660 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8812 22:16:00.445824 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8813 22:16:00.452863 1 4 8 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
8814 22:16:00.456049 1 4 12 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
8815 22:16:00.459705 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8816 22:16:00.466201 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8817 22:16:00.469100 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8818 22:16:00.472609 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8819 22:16:00.479580 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8820 22:16:00.482306 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8821 22:16:00.486134 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8822 22:16:00.492885 1 5 12 | B1->B0 | 2323 2727 | 0 1 | (0 0) (1 0)
8823 22:16:00.496347 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
8824 22:16:00.499000 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8825 22:16:00.505927 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8826 22:16:00.509405 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8827 22:16:00.512765 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8828 22:16:00.518655 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8829 22:16:00.522301 1 6 8 | B1->B0 | 3e3e 2424 | 0 0 | (0 0) (0 0)
8830 22:16:00.525746 1 6 12 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
8831 22:16:00.532683 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8832 22:16:00.535265 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8833 22:16:00.538661 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8834 22:16:00.545718 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8835 22:16:00.549128 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8836 22:16:00.552375 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8837 22:16:00.558818 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8838 22:16:00.562263 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8839 22:16:00.566051 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8840 22:16:00.569069 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8841 22:16:00.575828 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8842 22:16:00.579049 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8843 22:16:00.582317 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8844 22:16:00.588823 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8845 22:16:00.591845 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8846 22:16:00.595402 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8847 22:16:00.602500 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8848 22:16:00.605402 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8849 22:16:00.609166 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8850 22:16:00.615123 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8851 22:16:00.618433 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8852 22:16:00.621760 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8853 22:16:00.628948 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8854 22:16:00.632010 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8855 22:16:00.635316 Total UI for P1: 0, mck2ui 16
8856 22:16:00.638589 best dqsien dly found for B1: ( 1, 9, 6)
8857 22:16:00.641899 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8858 22:16:00.645713 Total UI for P1: 0, mck2ui 16
8859 22:16:00.648715 best dqsien dly found for B0: ( 1, 9, 12)
8860 22:16:00.651954 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8861 22:16:00.655389 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8862 22:16:00.655821
8863 22:16:00.658682 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8864 22:16:00.665333 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8865 22:16:00.665947 [Gating] SW calibration Done
8866 22:16:00.668729 ==
8867 22:16:00.669157 Dram Type= 6, Freq= 0, CH_1, rank 1
8868 22:16:00.675428 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8869 22:16:00.675899 ==
8870 22:16:00.676244 RX Vref Scan: 0
8871 22:16:00.676564
8872 22:16:00.678590 RX Vref 0 -> 0, step: 1
8873 22:16:00.679016
8874 22:16:00.682025 RX Delay 0 -> 252, step: 8
8875 22:16:00.685880 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8876 22:16:00.688625 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8877 22:16:00.691901 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8878 22:16:00.698341 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8879 22:16:00.702257 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8880 22:16:00.705241 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8881 22:16:00.708925 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8882 22:16:00.711618 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8883 22:16:00.718439 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8884 22:16:00.721666 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8885 22:16:00.725069 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8886 22:16:00.728496 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8887 22:16:00.731350 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8888 22:16:00.738085 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8889 22:16:00.741377 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8890 22:16:00.744758 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8891 22:16:00.745277 ==
8892 22:16:00.747782 Dram Type= 6, Freq= 0, CH_1, rank 1
8893 22:16:00.751470 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8894 22:16:00.751896 ==
8895 22:16:00.755079 DQS Delay:
8896 22:16:00.755592 DQS0 = 0, DQS1 = 0
8897 22:16:00.757739 DQM Delay:
8898 22:16:00.758193 DQM0 = 136, DQM1 = 133
8899 22:16:00.761498 DQ Delay:
8900 22:16:00.765212 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8901 22:16:00.767809 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
8902 22:16:00.771694 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8903 22:16:00.774813 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8904 22:16:00.775247
8905 22:16:00.775671
8906 22:16:00.776073 ==
8907 22:16:00.778248 Dram Type= 6, Freq= 0, CH_1, rank 1
8908 22:16:00.781185 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8909 22:16:00.781675 ==
8910 22:16:00.782109
8911 22:16:00.782514
8912 22:16:00.784850 TX Vref Scan disable
8913 22:16:00.788126 == TX Byte 0 ==
8914 22:16:00.791607 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8915 22:16:00.794506 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8916 22:16:00.798054 == TX Byte 1 ==
8917 22:16:00.801282 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8918 22:16:00.805176 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8919 22:16:00.805761 ==
8920 22:16:00.808142 Dram Type= 6, Freq= 0, CH_1, rank 1
8921 22:16:00.814608 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8922 22:16:00.815127 ==
8923 22:16:00.825574
8924 22:16:00.829142 TX Vref early break, caculate TX vref
8925 22:16:00.832163 TX Vref=16, minBit 0, minWin=23, winSum=382
8926 22:16:00.835535 TX Vref=18, minBit 0, minWin=23, winSum=390
8927 22:16:00.838998 TX Vref=20, minBit 6, minWin=24, winSum=406
8928 22:16:00.842457 TX Vref=22, minBit 0, minWin=25, winSum=410
8929 22:16:00.845728 TX Vref=24, minBit 0, minWin=24, winSum=419
8930 22:16:00.852304 TX Vref=26, minBit 0, minWin=26, winSum=428
8931 22:16:00.855881 TX Vref=28, minBit 6, minWin=25, winSum=427
8932 22:16:00.859063 TX Vref=30, minBit 0, minWin=25, winSum=422
8933 22:16:00.862539 TX Vref=32, minBit 0, minWin=25, winSum=413
8934 22:16:00.866046 TX Vref=34, minBit 0, minWin=24, winSum=403
8935 22:16:00.872598 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 26
8936 22:16:00.873147
8937 22:16:00.875284 Final TX Range 0 Vref 26
8938 22:16:00.875850
8939 22:16:00.876253 ==
8940 22:16:00.878917 Dram Type= 6, Freq= 0, CH_1, rank 1
8941 22:16:00.882236 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8942 22:16:00.882665 ==
8943 22:16:00.883006
8944 22:16:00.883317
8945 22:16:00.885224 TX Vref Scan disable
8946 22:16:00.892561 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8947 22:16:00.893094 == TX Byte 0 ==
8948 22:16:00.895254 u2DelayCellOfst[0]=16 cells (5 PI)
8949 22:16:00.898730 u2DelayCellOfst[1]=10 cells (3 PI)
8950 22:16:00.901993 u2DelayCellOfst[2]=0 cells (0 PI)
8951 22:16:00.905668 u2DelayCellOfst[3]=6 cells (2 PI)
8952 22:16:00.909160 u2DelayCellOfst[4]=10 cells (3 PI)
8953 22:16:00.911945 u2DelayCellOfst[5]=16 cells (5 PI)
8954 22:16:00.915621 u2DelayCellOfst[6]=16 cells (5 PI)
8955 22:16:00.916041 u2DelayCellOfst[7]=6 cells (2 PI)
8956 22:16:00.921825 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8957 22:16:00.925568 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8958 22:16:00.926104 == TX Byte 1 ==
8959 22:16:00.929143 u2DelayCellOfst[8]=0 cells (0 PI)
8960 22:16:00.931880 u2DelayCellOfst[9]=3 cells (1 PI)
8961 22:16:00.935250 u2DelayCellOfst[10]=10 cells (3 PI)
8962 22:16:00.938346 u2DelayCellOfst[11]=3 cells (1 PI)
8963 22:16:00.941700 u2DelayCellOfst[12]=13 cells (4 PI)
8964 22:16:00.945604 u2DelayCellOfst[13]=16 cells (5 PI)
8965 22:16:00.948271 u2DelayCellOfst[14]=16 cells (5 PI)
8966 22:16:00.951938 u2DelayCellOfst[15]=16 cells (5 PI)
8967 22:16:00.955028 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8968 22:16:00.961684 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8969 22:16:00.962281 DramC Write-DBI on
8970 22:16:00.962766 ==
8971 22:16:00.964752 Dram Type= 6, Freq= 0, CH_1, rank 1
8972 22:16:00.968104 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8973 22:16:00.971523 ==
8974 22:16:00.971950
8975 22:16:00.972291
8976 22:16:00.972609 TX Vref Scan disable
8977 22:16:00.975059 == TX Byte 0 ==
8978 22:16:00.978472 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8979 22:16:00.981739 == TX Byte 1 ==
8980 22:16:00.985093 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8981 22:16:00.988340 DramC Write-DBI off
8982 22:16:00.988828
8983 22:16:00.989309 [DATLAT]
8984 22:16:00.989770 Freq=1600, CH1 RK1
8985 22:16:00.990237
8986 22:16:00.991478 DATLAT Default: 0xf
8987 22:16:00.992032 0, 0xFFFF, sum = 0
8988 22:16:00.995092 1, 0xFFFF, sum = 0
8989 22:16:00.995529 2, 0xFFFF, sum = 0
8990 22:16:00.998142 3, 0xFFFF, sum = 0
8991 22:16:00.998587 4, 0xFFFF, sum = 0
8992 22:16:01.001269 5, 0xFFFF, sum = 0
8993 22:16:01.004579 6, 0xFFFF, sum = 0
8994 22:16:01.005017 7, 0xFFFF, sum = 0
8995 22:16:01.007943 8, 0xFFFF, sum = 0
8996 22:16:01.008379 9, 0xFFFF, sum = 0
8997 22:16:01.011555 10, 0xFFFF, sum = 0
8998 22:16:01.011994 11, 0xFFFF, sum = 0
8999 22:16:01.015234 12, 0xFFFF, sum = 0
9000 22:16:01.015807 13, 0xFFFF, sum = 0
9001 22:16:01.018019 14, 0x0, sum = 1
9002 22:16:01.018534 15, 0x0, sum = 2
9003 22:16:01.021173 16, 0x0, sum = 3
9004 22:16:01.021694 17, 0x0, sum = 4
9005 22:16:01.024842 best_step = 15
9006 22:16:01.025265
9007 22:16:01.025741 ==
9008 22:16:01.028139 Dram Type= 6, Freq= 0, CH_1, rank 1
9009 22:16:01.031579 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9010 22:16:01.032005 ==
9011 22:16:01.032344 RX Vref Scan: 0
9012 22:16:01.032657
9013 22:16:01.034644 RX Vref 0 -> 0, step: 1
9014 22:16:01.035068
9015 22:16:01.037955 RX Delay 19 -> 252, step: 4
9016 22:16:01.041571 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
9017 22:16:01.044903 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
9018 22:16:01.051486 iDelay=195, Bit 2, Center 124 (75 ~ 174) 100
9019 22:16:01.054906 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9020 22:16:01.057838 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
9021 22:16:01.061314 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9022 22:16:01.064484 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
9023 22:16:01.071221 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
9024 22:16:01.074287 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
9025 22:16:01.077666 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9026 22:16:01.080687 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
9027 22:16:01.084435 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9028 22:16:01.091295 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
9029 22:16:01.094038 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9030 22:16:01.097833 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9031 22:16:01.100764 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
9032 22:16:01.101175 ==
9033 22:16:01.104605 Dram Type= 6, Freq= 0, CH_1, rank 1
9034 22:16:01.110554 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9035 22:16:01.110971 ==
9036 22:16:01.111355 DQS Delay:
9037 22:16:01.114105 DQS0 = 0, DQS1 = 0
9038 22:16:01.114475 DQM Delay:
9039 22:16:01.117040 DQM0 = 134, DQM1 = 130
9040 22:16:01.117387 DQ Delay:
9041 22:16:01.120625 DQ0 =138, DQ1 =130, DQ2 =124, DQ3 =130
9042 22:16:01.124382 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
9043 22:16:01.127429 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =124
9044 22:16:01.130368 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =138
9045 22:16:01.130844
9046 22:16:01.131195
9047 22:16:01.131550
9048 22:16:01.134057 [DramC_TX_OE_Calibration] TA2
9049 22:16:01.137224 Original DQ_B0 (3 6) =30, OEN = 27
9050 22:16:01.141122 Original DQ_B1 (3 6) =30, OEN = 27
9051 22:16:01.144222 24, 0x0, End_B0=24 End_B1=24
9052 22:16:01.147172 25, 0x0, End_B0=25 End_B1=25
9053 22:16:01.147555 26, 0x0, End_B0=26 End_B1=26
9054 22:16:01.150568 27, 0x0, End_B0=27 End_B1=27
9055 22:16:01.153720 28, 0x0, End_B0=28 End_B1=28
9056 22:16:01.156979 29, 0x0, End_B0=29 End_B1=29
9057 22:16:01.157383 30, 0x0, End_B0=30 End_B1=30
9058 22:16:01.160434 31, 0x4141, End_B0=30 End_B1=30
9059 22:16:01.163892 Byte0 end_step=30 best_step=27
9060 22:16:01.167420 Byte1 end_step=30 best_step=27
9061 22:16:01.170832 Byte0 TX OE(2T, 0.5T) = (3, 3)
9062 22:16:01.173452 Byte1 TX OE(2T, 0.5T) = (3, 3)
9063 22:16:01.173933
9064 22:16:01.174217
9065 22:16:01.180113 [DQSOSCAuto] RK1, (LSB)MR18= 0x240b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 391 ps
9066 22:16:01.183451 CH1 RK1: MR19=303, MR18=240B
9067 22:16:01.190300 CH1_RK1: MR19=0x303, MR18=0x240B, DQSOSC=391, MR23=63, INC=24, DEC=16
9068 22:16:01.193472 [RxdqsGatingPostProcess] freq 1600
9069 22:16:01.196767 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9070 22:16:01.200328 best DQS0 dly(2T, 0.5T) = (1, 1)
9071 22:16:01.203940 best DQS1 dly(2T, 0.5T) = (1, 1)
9072 22:16:01.207127 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9073 22:16:01.210178 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9074 22:16:01.213919 best DQS0 dly(2T, 0.5T) = (1, 1)
9075 22:16:01.216692 best DQS1 dly(2T, 0.5T) = (1, 1)
9076 22:16:01.220017 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9077 22:16:01.223716 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9078 22:16:01.226951 Pre-setting of DQS Precalculation
9079 22:16:01.230599 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9080 22:16:01.236695 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9081 22:16:01.246690 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9082 22:16:01.247093
9083 22:16:01.247361
9084 22:16:01.250339 [Calibration Summary] 3200 Mbps
9085 22:16:01.250650 CH 0, Rank 0
9086 22:16:01.253346 SW Impedance : PASS
9087 22:16:01.253688 DUTY Scan : NO K
9088 22:16:01.256854 ZQ Calibration : PASS
9089 22:16:01.260107 Jitter Meter : NO K
9090 22:16:01.260415 CBT Training : PASS
9091 22:16:01.263543 Write leveling : PASS
9092 22:16:01.263850 RX DQS gating : PASS
9093 22:16:01.266799 RX DQ/DQS(RDDQC) : PASS
9094 22:16:01.269814 TX DQ/DQS : PASS
9095 22:16:01.270122 RX DATLAT : PASS
9096 22:16:01.273153 RX DQ/DQS(Engine): PASS
9097 22:16:01.276629 TX OE : PASS
9098 22:16:01.276933 All Pass.
9099 22:16:01.277176
9100 22:16:01.277404 CH 0, Rank 1
9101 22:16:01.279984 SW Impedance : PASS
9102 22:16:01.283129 DUTY Scan : NO K
9103 22:16:01.283430 ZQ Calibration : PASS
9104 22:16:01.286515 Jitter Meter : NO K
9105 22:16:01.290079 CBT Training : PASS
9106 22:16:01.290432 Write leveling : PASS
9107 22:16:01.293487 RX DQS gating : PASS
9108 22:16:01.296428 RX DQ/DQS(RDDQC) : PASS
9109 22:16:01.296730 TX DQ/DQS : PASS
9110 22:16:01.300392 RX DATLAT : PASS
9111 22:16:01.303087 RX DQ/DQS(Engine): PASS
9112 22:16:01.303393 TX OE : PASS
9113 22:16:01.306514 All Pass.
9114 22:16:01.306906
9115 22:16:01.307245 CH 1, Rank 0
9116 22:16:01.309393 SW Impedance : PASS
9117 22:16:01.309763 DUTY Scan : NO K
9118 22:16:01.313218 ZQ Calibration : PASS
9119 22:16:01.316452 Jitter Meter : NO K
9120 22:16:01.316752 CBT Training : PASS
9121 22:16:01.319903 Write leveling : PASS
9122 22:16:01.320218 RX DQS gating : PASS
9123 22:16:01.323344 RX DQ/DQS(RDDQC) : PASS
9124 22:16:01.326136 TX DQ/DQS : PASS
9125 22:16:01.326406 RX DATLAT : PASS
9126 22:16:01.329582 RX DQ/DQS(Engine): PASS
9127 22:16:01.332970 TX OE : PASS
9128 22:16:01.333327 All Pass.
9129 22:16:01.333682
9130 22:16:01.333992 CH 1, Rank 1
9131 22:16:01.336119 SW Impedance : PASS
9132 22:16:01.339531 DUTY Scan : NO K
9133 22:16:01.339600 ZQ Calibration : PASS
9134 22:16:01.342799 Jitter Meter : NO K
9135 22:16:01.345793 CBT Training : PASS
9136 22:16:01.345867 Write leveling : PASS
9137 22:16:01.349161 RX DQS gating : PASS
9138 22:16:01.352504 RX DQ/DQS(RDDQC) : PASS
9139 22:16:01.352573 TX DQ/DQS : PASS
9140 22:16:01.356525 RX DATLAT : PASS
9141 22:16:01.359353 RX DQ/DQS(Engine): PASS
9142 22:16:01.359440 TX OE : PASS
9143 22:16:01.362524 All Pass.
9144 22:16:01.362622
9145 22:16:01.362703 DramC Write-DBI on
9146 22:16:01.366207 PER_BANK_REFRESH: Hybrid Mode
9147 22:16:01.366309 TX_TRACKING: ON
9148 22:16:01.376115 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9149 22:16:01.382759 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9150 22:16:01.392574 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9151 22:16:01.395948 [FAST_K] Save calibration result to emmc
9152 22:16:01.399710 sync common calibartion params.
9153 22:16:01.399920 sync cbt_mode0:1, 1:1
9154 22:16:01.402676 dram_init: ddr_geometry: 2
9155 22:16:01.406029 dram_init: ddr_geometry: 2
9156 22:16:01.406115 dram_init: ddr_geometry: 2
9157 22:16:01.409269 0:dram_rank_size:100000000
9158 22:16:01.412802 1:dram_rank_size:100000000
9159 22:16:01.415854 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9160 22:16:01.419353 DFS_SHUFFLE_HW_MODE: ON
9161 22:16:01.422839 dramc_set_vcore_voltage set vcore to 725000
9162 22:16:01.425789 Read voltage for 1600, 0
9163 22:16:01.425992 Vio18 = 0
9164 22:16:01.429261 Vcore = 725000
9165 22:16:01.429450 Vdram = 0
9166 22:16:01.429559 Vddq = 0
9167 22:16:01.429655 Vmddr = 0
9168 22:16:01.432714 switch to 3200 Mbps bootup
9169 22:16:01.435865 [DramcRunTimeConfig]
9170 22:16:01.436061 PHYPLL
9171 22:16:01.439503 DPM_CONTROL_AFTERK: ON
9172 22:16:01.439766 PER_BANK_REFRESH: ON
9173 22:16:01.442824 REFRESH_OVERHEAD_REDUCTION: ON
9174 22:16:01.446366 CMD_PICG_NEW_MODE: OFF
9175 22:16:01.446805 XRTWTW_NEW_MODE: ON
9176 22:16:01.449457 XRTRTR_NEW_MODE: ON
9177 22:16:01.449928 TX_TRACKING: ON
9178 22:16:01.453327 RDSEL_TRACKING: OFF
9179 22:16:01.456384 DQS Precalculation for DVFS: ON
9180 22:16:01.456952 RX_TRACKING: OFF
9181 22:16:01.457399 HW_GATING DBG: ON
9182 22:16:01.459742 ZQCS_ENABLE_LP4: ON
9183 22:16:01.463219 RX_PICG_NEW_MODE: ON
9184 22:16:01.463707 TX_PICG_NEW_MODE: ON
9185 22:16:01.466182 ENABLE_RX_DCM_DPHY: ON
9186 22:16:01.469576 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9187 22:16:01.472691 DUMMY_READ_FOR_TRACKING: OFF
9188 22:16:01.473146 !!! SPM_CONTROL_AFTERK: OFF
9189 22:16:01.476372 !!! SPM could not control APHY
9190 22:16:01.479511 IMPEDANCE_TRACKING: ON
9191 22:16:01.479947 TEMP_SENSOR: ON
9192 22:16:01.482463 HW_SAVE_FOR_SR: OFF
9193 22:16:01.485981 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9194 22:16:01.489759 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9195 22:16:01.490179 Read ODT Tracking: ON
9196 22:16:01.493127 Refresh Rate DeBounce: ON
9197 22:16:01.496269 DFS_NO_QUEUE_FLUSH: ON
9198 22:16:01.499338 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9199 22:16:01.499804 ENABLE_DFS_RUNTIME_MRW: OFF
9200 22:16:01.502362 DDR_RESERVE_NEW_MODE: ON
9201 22:16:01.505620 MR_CBT_SWITCH_FREQ: ON
9202 22:16:01.505923 =========================
9203 22:16:01.525553 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9204 22:16:01.529099 dram_init: ddr_geometry: 2
9205 22:16:01.547157 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9206 22:16:01.550642 dram_init: dram init end (result: 0)
9207 22:16:01.557310 DRAM-K: Full calibration passed in 24457 msecs
9208 22:16:01.560393 MRC: failed to locate region type 0.
9209 22:16:01.560481 DRAM rank0 size:0x100000000,
9210 22:16:01.564008 DRAM rank1 size=0x100000000
9211 22:16:01.573727 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9212 22:16:01.580464 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9213 22:16:01.587134 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9214 22:16:01.593249 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9215 22:16:01.597379 DRAM rank0 size:0x100000000,
9216 22:16:01.600477 DRAM rank1 size=0x100000000
9217 22:16:01.600668 CBMEM:
9218 22:16:01.603465 IMD: root @ 0xfffff000 254 entries.
9219 22:16:01.606684 IMD: root @ 0xffffec00 62 entries.
9220 22:16:01.610638 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9221 22:16:01.613201 WARNING: RO_VPD is uninitialized or empty.
9222 22:16:01.620211 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9223 22:16:01.626967 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9224 22:16:01.639649 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9225 22:16:01.651126 BS: romstage times (exec / console): total (unknown) / 23988 ms
9226 22:16:01.651215
9227 22:16:01.651281
9228 22:16:01.661103 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9229 22:16:01.664734 ARM64: Exception handlers installed.
9230 22:16:01.667869 ARM64: Testing exception
9231 22:16:01.671017 ARM64: Done test exception
9232 22:16:01.671100 Enumerating buses...
9233 22:16:01.674542 Show all devs... Before device enumeration.
9234 22:16:01.677868 Root Device: enabled 1
9235 22:16:01.680797 CPU_CLUSTER: 0: enabled 1
9236 22:16:01.680879 CPU: 00: enabled 1
9237 22:16:01.684877 Compare with tree...
9238 22:16:01.684959 Root Device: enabled 1
9239 22:16:01.687640 CPU_CLUSTER: 0: enabled 1
9240 22:16:01.690989 CPU: 00: enabled 1
9241 22:16:01.691135 Root Device scanning...
9242 22:16:01.694242 scan_static_bus for Root Device
9243 22:16:01.697875 CPU_CLUSTER: 0 enabled
9244 22:16:01.701275 scan_static_bus for Root Device done
9245 22:16:01.704386 scan_bus: bus Root Device finished in 8 msecs
9246 22:16:01.704468 done
9247 22:16:01.711324 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9248 22:16:01.714656 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9249 22:16:01.720957 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9250 22:16:01.724427 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9251 22:16:01.727656 Allocating resources...
9252 22:16:01.731184 Reading resources...
9253 22:16:01.734442 Root Device read_resources bus 0 link: 0
9254 22:16:01.734538 DRAM rank0 size:0x100000000,
9255 22:16:01.737535 DRAM rank1 size=0x100000000
9256 22:16:01.741264 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9257 22:16:01.744220 CPU: 00 missing read_resources
9258 22:16:01.747316 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9259 22:16:01.754200 Root Device read_resources bus 0 link: 0 done
9260 22:16:01.754301 Done reading resources.
9261 22:16:01.760591 Show resources in subtree (Root Device)...After reading.
9262 22:16:01.764236 Root Device child on link 0 CPU_CLUSTER: 0
9263 22:16:01.767450 CPU_CLUSTER: 0 child on link 0 CPU: 00
9264 22:16:01.777323 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9265 22:16:01.777406 CPU: 00
9266 22:16:01.780988 Root Device assign_resources, bus 0 link: 0
9267 22:16:01.783869 CPU_CLUSTER: 0 missing set_resources
9268 22:16:01.787467 Root Device assign_resources, bus 0 link: 0 done
9269 22:16:01.791023 Done setting resources.
9270 22:16:01.797361 Show resources in subtree (Root Device)...After assigning values.
9271 22:16:01.800981 Root Device child on link 0 CPU_CLUSTER: 0
9272 22:16:01.804074 CPU_CLUSTER: 0 child on link 0 CPU: 00
9273 22:16:01.814410 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9274 22:16:01.814493 CPU: 00
9275 22:16:01.817378 Done allocating resources.
9276 22:16:01.820835 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9277 22:16:01.823821 Enabling resources...
9278 22:16:01.823902 done.
9279 22:16:01.830849 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9280 22:16:01.830931 Initializing devices...
9281 22:16:01.834080 Root Device init
9282 22:16:01.834161 init hardware done!
9283 22:16:01.837071 0x00000018: ctrlr->caps
9284 22:16:01.840480 52.000 MHz: ctrlr->f_max
9285 22:16:01.840564 0.400 MHz: ctrlr->f_min
9286 22:16:01.843996 0x40ff8080: ctrlr->voltages
9287 22:16:01.844079 sclk: 390625
9288 22:16:01.847348 Bus Width = 1
9289 22:16:01.847429 sclk: 390625
9290 22:16:01.850228 Bus Width = 1
9291 22:16:01.850303 Early init status = 3
9292 22:16:01.857240 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9293 22:16:01.860558 in-header: 03 fc 00 00 01 00 00 00
9294 22:16:01.860640 in-data: 00
9295 22:16:01.867026 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9296 22:16:01.870157 in-header: 03 fd 00 00 00 00 00 00
9297 22:16:01.873881 in-data:
9298 22:16:01.876936 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9299 22:16:01.881166 in-header: 03 fc 00 00 01 00 00 00
9300 22:16:01.884083 in-data: 00
9301 22:16:01.887852 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9302 22:16:01.893136 in-header: 03 fd 00 00 00 00 00 00
9303 22:16:01.896447 in-data:
9304 22:16:01.900155 [SSUSB] Setting up USB HOST controller...
9305 22:16:01.903400 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9306 22:16:01.906578 [SSUSB] phy power-on done.
9307 22:16:01.910165 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9308 22:16:01.916106 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9309 22:16:01.920196 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9310 22:16:01.926482 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9311 22:16:01.933347 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9312 22:16:01.939817 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9313 22:16:01.946576 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9314 22:16:01.953108 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9315 22:16:01.956696 SPM: binary array size = 0x9dc
9316 22:16:01.959755 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9317 22:16:01.966394 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9318 22:16:01.973298 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9319 22:16:01.976830 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9320 22:16:01.982744 configure_display: Starting display init
9321 22:16:02.013680 anx7625_power_on_init: Init interface.
9322 22:16:02.020655 anx7625_disable_pd_protocol: Disabled PD feature.
9323 22:16:02.023625 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9324 22:16:02.050667 anx7625_start_dp_work: Secure OCM version=00
9325 22:16:02.053959 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9326 22:16:02.068848 sp_tx_get_edid_block: EDID Block = 1
9327 22:16:02.171915 Extracted contents:
9328 22:16:02.175600 header: 00 ff ff ff ff ff ff 00
9329 22:16:02.178710 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9330 22:16:02.181886 version: 01 04
9331 22:16:02.185074 basic params: 95 1f 11 78 0a
9332 22:16:02.188203 chroma info: 76 90 94 55 54 90 27 21 50 54
9333 22:16:02.191754 established: 00 00 00
9334 22:16:02.198750 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9335 22:16:02.201677 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9336 22:16:02.208532 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9337 22:16:02.214244 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9338 22:16:02.221204 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9339 22:16:02.224414 extensions: 00
9340 22:16:02.224834 checksum: fb
9341 22:16:02.225223
9342 22:16:02.227911 Manufacturer: IVO Model 57d Serial Number 0
9343 22:16:02.231273 Made week 0 of 2020
9344 22:16:02.231716 EDID version: 1.4
9345 22:16:02.234685 Digital display
9346 22:16:02.237630 6 bits per primary color channel
9347 22:16:02.238151 DisplayPort interface
9348 22:16:02.241207 Maximum image size: 31 cm x 17 cm
9349 22:16:02.244533 Gamma: 220%
9350 22:16:02.244951 Check DPMS levels
9351 22:16:02.247649 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9352 22:16:02.254772 First detailed timing is preferred timing
9353 22:16:02.255198 Established timings supported:
9354 22:16:02.257890 Standard timings supported:
9355 22:16:02.260767 Detailed timings
9356 22:16:02.264165 Hex of detail: 383680a07038204018303c0035ae10000019
9357 22:16:02.267702 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9358 22:16:02.274209 0780 0798 07c8 0820 hborder 0
9359 22:16:02.277927 0438 043b 0447 0458 vborder 0
9360 22:16:02.280805 -hsync -vsync
9361 22:16:02.281213 Did detailed timing
9362 22:16:02.288069 Hex of detail: 000000000000000000000000000000000000
9363 22:16:02.288484 Manufacturer-specified data, tag 0
9364 22:16:02.294442 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9365 22:16:02.297887 ASCII string: InfoVision
9366 22:16:02.300950 Hex of detail: 000000fe00523134304e574635205248200a
9367 22:16:02.304077 ASCII string: R140NWF5 RH
9368 22:16:02.304489 Checksum
9369 22:16:02.307473 Checksum: 0xfb (valid)
9370 22:16:02.311188 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9371 22:16:02.314122 DSI data_rate: 832800000 bps
9372 22:16:02.320564 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9373 22:16:02.324348 anx7625_parse_edid: pixelclock(138800).
9374 22:16:02.327859 hactive(1920), hsync(48), hfp(24), hbp(88)
9375 22:16:02.331041 vactive(1080), vsync(12), vfp(3), vbp(17)
9376 22:16:02.334030 anx7625_dsi_config: config dsi.
9377 22:16:02.340826 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9378 22:16:02.353823 anx7625_dsi_config: success to config DSI
9379 22:16:02.357181 anx7625_dp_start: MIPI phy setup OK.
9380 22:16:02.360558 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9381 22:16:02.363447 mtk_ddp_mode_set invalid vrefresh 60
9382 22:16:02.366810 main_disp_path_setup
9383 22:16:02.367229 ovl_layer_smi_id_en
9384 22:16:02.370262 ovl_layer_smi_id_en
9385 22:16:02.370672 ccorr_config
9386 22:16:02.370996 aal_config
9387 22:16:02.373700 gamma_config
9388 22:16:02.374108 postmask_config
9389 22:16:02.376739 dither_config
9390 22:16:02.380545 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9391 22:16:02.386726 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9392 22:16:02.390179 Root Device init finished in 553 msecs
9393 22:16:02.393892 CPU_CLUSTER: 0 init
9394 22:16:02.400066 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9395 22:16:02.403552 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9396 22:16:02.406756 APU_MBOX 0x190000b0 = 0x10001
9397 22:16:02.409745 APU_MBOX 0x190001b0 = 0x10001
9398 22:16:02.413349 APU_MBOX 0x190005b0 = 0x10001
9399 22:16:02.416872 APU_MBOX 0x190006b0 = 0x10001
9400 22:16:02.419917 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9401 22:16:02.432876 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9402 22:16:02.445040 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9403 22:16:02.451556 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9404 22:16:02.463331 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9405 22:16:02.472202 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9406 22:16:02.475624 CPU_CLUSTER: 0 init finished in 81 msecs
9407 22:16:02.478968 Devices initialized
9408 22:16:02.482681 Show all devs... After init.
9409 22:16:02.483095 Root Device: enabled 1
9410 22:16:02.486124 CPU_CLUSTER: 0: enabled 1
9411 22:16:02.488911 CPU: 00: enabled 1
9412 22:16:02.492731 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9413 22:16:02.495681 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9414 22:16:02.499178 ELOG: NV offset 0x57f000 size 0x1000
9415 22:16:02.505897 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9416 22:16:02.512551 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9417 22:16:02.515610 ELOG: Event(17) added with size 13 at 2023-06-04 22:16:02 UTC
9418 22:16:02.519166 out: cmd=0x121: 03 db 21 01 00 00 00 00
9419 22:16:02.522669 in-header: 03 da 00 00 2c 00 00 00
9420 22:16:02.535928 in-data: 85 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9421 22:16:02.542715 ELOG: Event(A1) added with size 10 at 2023-06-04 22:16:02 UTC
9422 22:16:02.549431 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9423 22:16:02.555595 ELOG: Event(A0) added with size 9 at 2023-06-04 22:16:02 UTC
9424 22:16:02.559135 elog_add_boot_reason: Logged dev mode boot
9425 22:16:02.562618 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9426 22:16:02.566252 Finalize devices...
9427 22:16:02.566661 Devices finalized
9428 22:16:02.572394 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9429 22:16:02.575733 Writing coreboot table at 0xffe64000
9430 22:16:02.579187 0. 000000000010a000-0000000000113fff: RAMSTAGE
9431 22:16:02.582497 1. 0000000040000000-00000000400fffff: RAM
9432 22:16:02.589169 2. 0000000040100000-000000004032afff: RAMSTAGE
9433 22:16:02.592496 3. 000000004032b000-00000000545fffff: RAM
9434 22:16:02.595579 4. 0000000054600000-000000005465ffff: BL31
9435 22:16:02.599236 5. 0000000054660000-00000000ffe63fff: RAM
9436 22:16:02.605256 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9437 22:16:02.608941 7. 0000000100000000-000000023fffffff: RAM
9438 22:16:02.612293 Passing 5 GPIOs to payload:
9439 22:16:02.615246 NAME | PORT | POLARITY | VALUE
9440 22:16:02.618917 EC in RW | 0x000000aa | low | undefined
9441 22:16:02.625634 EC interrupt | 0x00000005 | low | undefined
9442 22:16:02.628648 TPM interrupt | 0x000000ab | high | undefined
9443 22:16:02.635297 SD card detect | 0x00000011 | high | undefined
9444 22:16:02.638845 speaker enable | 0x00000093 | high | undefined
9445 22:16:02.641630 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9446 22:16:02.644959 in-header: 03 f9 00 00 02 00 00 00
9447 22:16:02.648385 in-data: 02 00
9448 22:16:02.648803 ADC[4]: Raw value=904726 ID=7
9449 22:16:02.651748 ADC[3]: Raw value=213441 ID=1
9450 22:16:02.655192 RAM Code: 0x71
9451 22:16:02.655612 ADC[6]: Raw value=75701 ID=0
9452 22:16:02.658529 ADC[5]: Raw value=212703 ID=1
9453 22:16:02.661460 SKU Code: 0x1
9454 22:16:02.664997 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum d697
9455 22:16:02.668453 coreboot table: 964 bytes.
9456 22:16:02.671767 IMD ROOT 0. 0xfffff000 0x00001000
9457 22:16:02.675217 IMD SMALL 1. 0xffffe000 0x00001000
9458 22:16:02.678470 RO MCACHE 2. 0xffffc000 0x00001104
9459 22:16:02.681295 CONSOLE 3. 0xfff7c000 0x00080000
9460 22:16:02.685018 FMAP 4. 0xfff7b000 0x00000452
9461 22:16:02.688111 TIME STAMP 5. 0xfff7a000 0x00000910
9462 22:16:02.691507 VBOOT WORK 6. 0xfff66000 0x00014000
9463 22:16:02.695043 RAMOOPS 7. 0xffe66000 0x00100000
9464 22:16:02.697971 COREBOOT 8. 0xffe64000 0x00002000
9465 22:16:02.698463 IMD small region:
9466 22:16:02.701744 IMD ROOT 0. 0xffffec00 0x00000400
9467 22:16:02.704647 VPD 1. 0xffffeba0 0x0000004c
9468 22:16:02.708178 MMC STATUS 2. 0xffffeb80 0x00000004
9469 22:16:02.715005 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9470 22:16:02.718466 Probing TPM: done!
9471 22:16:02.721791 Connected to device vid:did:rid of 1ae0:0028:00
9472 22:16:02.731537 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9b9523
9473 22:16:02.735136 Initialized TPM device CR50 revision 0
9474 22:16:02.738945 Checking cr50 for pending updates
9475 22:16:02.742427 Reading cr50 TPM mode
9476 22:16:02.751259 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9477 22:16:02.757966 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9478 22:16:02.797611 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9479 22:16:02.801083 Checking segment from ROM address 0x40100000
9480 22:16:02.804424 Checking segment from ROM address 0x4010001c
9481 22:16:02.811010 Loading segment from ROM address 0x40100000
9482 22:16:02.811541 code (compression=0)
9483 22:16:02.821098 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9484 22:16:02.828055 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9485 22:16:02.828574 it's not compressed!
9486 22:16:02.834499 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9487 22:16:02.837652 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9488 22:16:02.858202 Loading segment from ROM address 0x4010001c
9489 22:16:02.858630 Entry Point 0x80000000
9490 22:16:02.861559 Loaded segments
9491 22:16:02.864834 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9492 22:16:02.871581 Jumping to boot code at 0x80000000(0xffe64000)
9493 22:16:02.877882 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9494 22:16:02.884426 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9495 22:16:02.892658 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9496 22:16:02.896183 Checking segment from ROM address 0x40100000
9497 22:16:02.899028 Checking segment from ROM address 0x4010001c
9498 22:16:02.906000 Loading segment from ROM address 0x40100000
9499 22:16:02.906513 code (compression=1)
9500 22:16:02.912787 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9501 22:16:02.922926 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9502 22:16:02.923462 using LZMA
9503 22:16:02.931273 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9504 22:16:02.938211 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9505 22:16:02.941059 Loading segment from ROM address 0x4010001c
9506 22:16:02.941583 Entry Point 0x54601000
9507 22:16:02.944199 Loaded segments
9508 22:16:02.947656 NOTICE: MT8192 bl31_setup
9509 22:16:02.954709 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9510 22:16:02.958173 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9511 22:16:02.961719 WARNING: region 0:
9512 22:16:02.964750 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9513 22:16:02.965175 WARNING: region 1:
9514 22:16:02.971466 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9515 22:16:02.974906 WARNING: region 2:
9516 22:16:02.977812 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9517 22:16:02.981269 WARNING: region 3:
9518 22:16:02.984874 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9519 22:16:02.987945 WARNING: region 4:
9520 22:16:02.991340 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9521 22:16:02.994940 WARNING: region 5:
9522 22:16:02.998045 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9523 22:16:03.001606 WARNING: region 6:
9524 22:16:03.004686 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9525 22:16:03.005112 WARNING: region 7:
9526 22:16:03.011479 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9527 22:16:03.017914 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9528 22:16:03.021327 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9529 22:16:03.025003 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9530 22:16:03.028736 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9531 22:16:03.035336 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9532 22:16:03.038688 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9533 22:16:03.045501 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9534 22:16:03.048826 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9535 22:16:03.051971 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9536 22:16:03.058486 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9537 22:16:03.062251 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9538 22:16:03.065227 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9539 22:16:03.072303 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9540 22:16:03.075332 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9541 22:16:03.081812 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9542 22:16:03.085266 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9543 22:16:03.088497 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9544 22:16:03.094922 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9545 22:16:03.098386 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9546 22:16:03.101573 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9547 22:16:03.108285 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9548 22:16:03.111828 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9549 22:16:03.118617 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9550 22:16:03.121966 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9551 22:16:03.125008 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9552 22:16:03.131849 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9553 22:16:03.135390 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9554 22:16:03.138254 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9555 22:16:03.145491 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9556 22:16:03.148426 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9557 22:16:03.155152 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9558 22:16:03.158831 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9559 22:16:03.162032 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9560 22:16:03.168560 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9561 22:16:03.172203 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9562 22:16:03.175620 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9563 22:16:03.178961 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9564 22:16:03.181663 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9565 22:16:03.188552 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9566 22:16:03.191899 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9567 22:16:03.195366 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9568 22:16:03.198692 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9569 22:16:03.205479 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9570 22:16:03.208356 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9571 22:16:03.212287 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9572 22:16:03.218449 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9573 22:16:03.221981 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9574 22:16:03.225228 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9575 22:16:03.229099 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9576 22:16:03.235337 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9577 22:16:03.238500 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9578 22:16:03.245599 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9579 22:16:03.249252 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9580 22:16:03.255796 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9581 22:16:03.258591 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9582 22:16:03.262215 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9583 22:16:03.268974 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9584 22:16:03.272427 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9585 22:16:03.278975 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9586 22:16:03.282325 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9587 22:16:03.288685 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9588 22:16:03.292027 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9589 22:16:03.295372 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9590 22:16:03.302104 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9591 22:16:03.305605 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9592 22:16:03.312350 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9593 22:16:03.315483 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9594 22:16:03.322218 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9595 22:16:03.325634 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9596 22:16:03.328915 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9597 22:16:03.335635 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9598 22:16:03.338759 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9599 22:16:03.345818 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9600 22:16:03.348809 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9601 22:16:03.355459 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9602 22:16:03.358885 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9603 22:16:03.362276 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9604 22:16:03.368636 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9605 22:16:03.372225 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9606 22:16:03.378734 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9607 22:16:03.382624 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9608 22:16:03.388934 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9609 22:16:03.391902 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9610 22:16:03.395535 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9611 22:16:03.402147 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9612 22:16:03.405572 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9613 22:16:03.412337 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9614 22:16:03.415206 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9615 22:16:03.422600 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9616 22:16:03.425363 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9617 22:16:03.428966 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9618 22:16:03.435843 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9619 22:16:03.438684 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9620 22:16:03.445291 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9621 22:16:03.448898 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9622 22:16:03.455606 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9623 22:16:03.459269 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9624 22:16:03.462093 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9625 22:16:03.465693 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9626 22:16:03.472669 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9627 22:16:03.475655 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9628 22:16:03.479346 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9629 22:16:03.485467 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9630 22:16:03.489009 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9631 22:16:03.496035 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9632 22:16:03.499203 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9633 22:16:03.502209 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9634 22:16:03.509057 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9635 22:16:03.512310 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9636 22:16:03.515637 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9637 22:16:03.522137 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9638 22:16:03.525828 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9639 22:16:03.532627 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9640 22:16:03.535725 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9641 22:16:03.539282 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9642 22:16:03.545998 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9643 22:16:03.549244 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9644 22:16:03.553022 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9645 22:16:03.559518 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9646 22:16:03.563179 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9647 22:16:03.566250 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9648 22:16:03.570026 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9649 22:16:03.573562 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9650 22:16:03.580111 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9651 22:16:03.583369 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9652 22:16:03.586894 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9653 22:16:03.593021 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9654 22:16:03.596654 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9655 22:16:03.602961 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9656 22:16:03.606421 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9657 22:16:03.609664 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9658 22:16:03.616377 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9659 22:16:03.619645 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9660 22:16:03.626459 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9661 22:16:03.630195 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9662 22:16:03.633107 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9663 22:16:03.639909 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9664 22:16:03.642855 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9665 22:16:03.646596 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9666 22:16:03.653399 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9667 22:16:03.656566 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9668 22:16:03.662963 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9669 22:16:03.666599 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9670 22:16:03.670420 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9671 22:16:03.676445 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9672 22:16:03.679975 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9673 22:16:03.683110 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9674 22:16:03.689819 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9675 22:16:03.693286 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9676 22:16:03.699793 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9677 22:16:03.703401 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9678 22:16:03.706638 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9679 22:16:03.713435 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9680 22:16:03.716819 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9681 22:16:03.723473 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9682 22:16:03.726824 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9683 22:16:03.730179 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9684 22:16:03.736686 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9685 22:16:03.739999 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9686 22:16:03.743376 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9687 22:16:03.749767 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9688 22:16:03.753029 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9689 22:16:03.759805 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9690 22:16:03.763059 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9691 22:16:03.766890 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9692 22:16:03.773301 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9693 22:16:03.776308 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9694 22:16:03.783320 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9695 22:16:03.786800 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9696 22:16:03.789705 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9697 22:16:03.796315 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9698 22:16:03.799728 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9699 22:16:03.803447 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9700 22:16:03.810014 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9701 22:16:03.812914 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9702 22:16:03.819937 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9703 22:16:03.823143 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9704 22:16:03.829676 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9705 22:16:03.833094 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9706 22:16:03.836609 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9707 22:16:03.842734 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9708 22:16:03.846197 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9709 22:16:03.849283 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9710 22:16:03.856986 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9711 22:16:03.859912 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9712 22:16:03.866146 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9713 22:16:03.869994 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9714 22:16:03.872937 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9715 22:16:03.879319 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9716 22:16:03.882840 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9717 22:16:03.889754 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9718 22:16:03.892739 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9719 22:16:03.899746 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9720 22:16:03.902827 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9721 22:16:03.906000 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9722 22:16:03.913030 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9723 22:16:03.916887 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9724 22:16:03.923345 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9725 22:16:03.926269 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9726 22:16:03.929505 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9727 22:16:03.936544 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9728 22:16:03.939865 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9729 22:16:03.946483 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9730 22:16:03.949791 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9731 22:16:03.952729 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9732 22:16:03.958986 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9733 22:16:03.962686 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9734 22:16:03.969217 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9735 22:16:03.972923 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9736 22:16:03.979164 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9737 22:16:03.982559 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9738 22:16:03.985779 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9739 22:16:03.992679 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9740 22:16:03.995871 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9741 22:16:04.002425 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9742 22:16:04.005908 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9743 22:16:04.009239 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9744 22:16:04.016123 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9745 22:16:04.019516 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9746 22:16:04.025690 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9747 22:16:04.029425 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9748 22:16:04.032369 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9749 22:16:04.039447 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9750 22:16:04.042268 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9751 22:16:04.049757 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9752 22:16:04.052828 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9753 22:16:04.059316 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9754 22:16:04.062637 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9755 22:16:04.066181 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9756 22:16:04.072297 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9757 22:16:04.075880 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9758 22:16:04.078996 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9759 22:16:04.082291 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9760 22:16:04.085465 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9761 22:16:04.092511 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9762 22:16:04.095838 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9763 22:16:04.102329 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9764 22:16:04.106181 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9765 22:16:04.108962 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9766 22:16:04.115526 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9767 22:16:04.119159 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9768 22:16:04.125935 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9769 22:16:04.129032 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9770 22:16:04.132151 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9771 22:16:04.138958 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9772 22:16:04.141946 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9773 22:16:04.145671 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9774 22:16:04.152075 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9775 22:16:04.155221 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9776 22:16:04.158478 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9777 22:16:04.165286 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9778 22:16:04.168928 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9779 22:16:04.175510 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9780 22:16:04.178760 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9781 22:16:04.181830 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9782 22:16:04.188375 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9783 22:16:04.191932 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9784 22:16:04.195042 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9785 22:16:04.201748 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9786 22:16:04.205245 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9787 22:16:04.208221 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9788 22:16:04.215234 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9789 22:16:04.218095 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9790 22:16:04.222002 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9791 22:16:04.229032 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9792 22:16:04.231742 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9793 22:16:04.238242 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9794 22:16:04.241707 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9795 22:16:04.244916 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9796 22:16:04.251611 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9797 22:16:04.255228 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9798 22:16:04.257730 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9799 22:16:04.261622 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9800 22:16:04.264432 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9801 22:16:04.271336 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9802 22:16:04.274853 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9803 22:16:04.278272 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9804 22:16:04.281589 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9805 22:16:04.288065 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9806 22:16:04.291820 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9807 22:16:04.295061 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9808 22:16:04.298332 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9809 22:16:04.304752 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9810 22:16:04.308801 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9811 22:16:04.315014 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9812 22:16:04.318083 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9813 22:16:04.324922 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9814 22:16:04.328011 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9815 22:16:04.331539 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9816 22:16:04.338194 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9817 22:16:04.341107 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9818 22:16:04.348644 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9819 22:16:04.351199 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9820 22:16:04.354468 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9821 22:16:04.360889 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9822 22:16:04.364600 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9823 22:16:04.370978 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9824 22:16:04.374396 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9825 22:16:04.377547 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9826 22:16:04.384110 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9827 22:16:04.387949 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9828 22:16:04.394669 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9829 22:16:04.397863 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9830 22:16:04.404377 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9831 22:16:04.407907 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9832 22:16:04.411137 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9833 22:16:04.417725 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9834 22:16:04.420634 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9835 22:16:04.427470 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9836 22:16:04.430681 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9837 22:16:04.434226 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9838 22:16:04.440506 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9839 22:16:04.443927 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9840 22:16:04.450514 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9841 22:16:04.453700 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9842 22:16:04.457259 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9843 22:16:04.463555 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9844 22:16:04.467586 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9845 22:16:04.473916 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9846 22:16:04.476971 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9847 22:16:04.484058 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9848 22:16:04.486747 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9849 22:16:04.490513 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9850 22:16:04.497206 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9851 22:16:04.500586 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9852 22:16:04.506844 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9853 22:16:04.510101 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9854 22:16:04.513671 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9855 22:16:04.520601 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9856 22:16:04.523506 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9857 22:16:04.530399 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9858 22:16:04.533658 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9859 22:16:04.537218 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9860 22:16:04.543765 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9861 22:16:04.546897 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9862 22:16:04.553648 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9863 22:16:04.557266 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9864 22:16:04.560118 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9865 22:16:04.567249 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9866 22:16:04.569979 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9867 22:16:04.577065 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9868 22:16:04.579939 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9869 22:16:04.583288 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9870 22:16:04.589952 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9871 22:16:04.593265 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9872 22:16:04.600373 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9873 22:16:04.603719 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9874 22:16:04.606953 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9875 22:16:04.613269 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9876 22:16:04.616900 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9877 22:16:04.623976 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9878 22:16:04.626947 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9879 22:16:04.633612 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9880 22:16:04.636885 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9881 22:16:04.640057 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9882 22:16:04.646768 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9883 22:16:04.649730 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9884 22:16:04.656602 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9885 22:16:04.660436 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9886 22:16:04.666630 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9887 22:16:04.669856 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9888 22:16:04.673155 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9889 22:16:04.679978 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9890 22:16:04.682782 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9891 22:16:04.689393 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9892 22:16:04.692999 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9893 22:16:04.699739 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9894 22:16:04.702863 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9895 22:16:04.709681 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9896 22:16:04.712924 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9897 22:16:04.716412 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9898 22:16:04.723252 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9899 22:16:04.726425 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9900 22:16:04.733134 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9901 22:16:04.736192 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9902 22:16:04.742548 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9903 22:16:04.746093 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9904 22:16:04.749496 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9905 22:16:04.756198 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9906 22:16:04.759304 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9907 22:16:04.766040 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9908 22:16:04.769043 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9909 22:16:04.775743 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9910 22:16:04.779055 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9911 22:16:04.782868 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9912 22:16:04.789681 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9913 22:16:04.792381 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9914 22:16:04.798895 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9915 22:16:04.802696 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9916 22:16:04.808981 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9917 22:16:04.812859 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9918 22:16:04.815684 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9919 22:16:04.822198 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9920 22:16:04.825591 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9921 22:16:04.832310 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9922 22:16:04.835719 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9923 22:16:04.842194 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9924 22:16:04.846113 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9925 22:16:04.849154 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9926 22:16:04.855858 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9927 22:16:04.858927 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9928 22:16:04.865667 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9929 22:16:04.869330 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9930 22:16:04.872239 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9931 22:16:04.878871 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9932 22:16:04.882768 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9933 22:16:04.889096 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9934 22:16:04.892464 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9935 22:16:04.899050 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9936 22:16:04.902219 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9937 22:16:04.909165 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9938 22:16:04.912697 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9939 22:16:04.919540 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9940 22:16:04.922260 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9941 22:16:04.929152 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9942 22:16:04.932351 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9943 22:16:04.939214 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9944 22:16:04.942400 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9945 22:16:04.948959 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9946 22:16:04.952234 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9947 22:16:04.956147 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9948 22:16:04.962484 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9949 22:16:04.966261 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9950 22:16:04.972367 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9951 22:16:04.975969 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9952 22:16:04.982666 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9953 22:16:04.985548 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9954 22:16:04.992318 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9955 22:16:04.995846 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9956 22:16:05.002560 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9957 22:16:05.006018 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9958 22:16:05.012578 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9959 22:16:05.015576 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9960 22:16:05.022273 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9961 22:16:05.025611 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9962 22:16:05.028903 INFO: [APUAPC] vio 0
9963 22:16:05.032186 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9964 22:16:05.038951 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9965 22:16:05.042409 INFO: [APUAPC] D0_APC_0: 0x400510
9966 22:16:05.045535 INFO: [APUAPC] D0_APC_1: 0x0
9967 22:16:05.045960 INFO: [APUAPC] D0_APC_2: 0x1540
9968 22:16:05.049452 INFO: [APUAPC] D0_APC_3: 0x0
9969 22:16:05.052383 INFO: [APUAPC] D1_APC_0: 0xffffffff
9970 22:16:05.055517 INFO: [APUAPC] D1_APC_1: 0xffffffff
9971 22:16:05.058988 INFO: [APUAPC] D1_APC_2: 0x3fffff
9972 22:16:05.062620 INFO: [APUAPC] D1_APC_3: 0x0
9973 22:16:05.065783 INFO: [APUAPC] D2_APC_0: 0xffffffff
9974 22:16:05.068763 INFO: [APUAPC] D2_APC_1: 0xffffffff
9975 22:16:05.072406 INFO: [APUAPC] D2_APC_2: 0x3fffff
9976 22:16:05.075944 INFO: [APUAPC] D2_APC_3: 0x0
9977 22:16:05.078790 INFO: [APUAPC] D3_APC_0: 0xffffffff
9978 22:16:05.082656 INFO: [APUAPC] D3_APC_1: 0xffffffff
9979 22:16:05.085637 INFO: [APUAPC] D3_APC_2: 0x3fffff
9980 22:16:05.088777 INFO: [APUAPC] D3_APC_3: 0x0
9981 22:16:05.092292 INFO: [APUAPC] D4_APC_0: 0xffffffff
9982 22:16:05.095250 INFO: [APUAPC] D4_APC_1: 0xffffffff
9983 22:16:05.098482 INFO: [APUAPC] D4_APC_2: 0x3fffff
9984 22:16:05.101950 INFO: [APUAPC] D4_APC_3: 0x0
9985 22:16:05.105293 INFO: [APUAPC] D5_APC_0: 0xffffffff
9986 22:16:05.108743 INFO: [APUAPC] D5_APC_1: 0xffffffff
9987 22:16:05.112177 INFO: [APUAPC] D5_APC_2: 0x3fffff
9988 22:16:05.115397 INFO: [APUAPC] D5_APC_3: 0x0
9989 22:16:05.118749 INFO: [APUAPC] D6_APC_0: 0xffffffff
9990 22:16:05.121888 INFO: [APUAPC] D6_APC_1: 0xffffffff
9991 22:16:05.125328 INFO: [APUAPC] D6_APC_2: 0x3fffff
9992 22:16:05.129004 INFO: [APUAPC] D6_APC_3: 0x0
9993 22:16:05.131967 INFO: [APUAPC] D7_APC_0: 0xffffffff
9994 22:16:05.135271 INFO: [APUAPC] D7_APC_1: 0xffffffff
9995 22:16:05.138585 INFO: [APUAPC] D7_APC_2: 0x3fffff
9996 22:16:05.142066 INFO: [APUAPC] D7_APC_3: 0x0
9997 22:16:05.145345 INFO: [APUAPC] D8_APC_0: 0xffffffff
9998 22:16:05.148714 INFO: [APUAPC] D8_APC_1: 0xffffffff
9999 22:16:05.151871 INFO: [APUAPC] D8_APC_2: 0x3fffff
10000 22:16:05.155449 INFO: [APUAPC] D8_APC_3: 0x0
10001 22:16:05.158865 INFO: [APUAPC] D9_APC_0: 0xffffffff
10002 22:16:05.161941 INFO: [APUAPC] D9_APC_1: 0xffffffff
10003 22:16:05.165466 INFO: [APUAPC] D9_APC_2: 0x3fffff
10004 22:16:05.168986 INFO: [APUAPC] D9_APC_3: 0x0
10005 22:16:05.172196 INFO: [APUAPC] D10_APC_0: 0xffffffff
10006 22:16:05.175158 INFO: [APUAPC] D10_APC_1: 0xffffffff
10007 22:16:05.178797 INFO: [APUAPC] D10_APC_2: 0x3fffff
10008 22:16:05.181993 INFO: [APUAPC] D10_APC_3: 0x0
10009 22:16:05.185257 INFO: [APUAPC] D11_APC_0: 0xffffffff
10010 22:16:05.188856 INFO: [APUAPC] D11_APC_1: 0xffffffff
10011 22:16:05.192172 INFO: [APUAPC] D11_APC_2: 0x3fffff
10012 22:16:05.195231 INFO: [APUAPC] D11_APC_3: 0x0
10013 22:16:05.198845 INFO: [APUAPC] D12_APC_0: 0xffffffff
10014 22:16:05.202113 INFO: [APUAPC] D12_APC_1: 0xffffffff
10015 22:16:05.205210 INFO: [APUAPC] D12_APC_2: 0x3fffff
10016 22:16:05.208703 INFO: [APUAPC] D12_APC_3: 0x0
10017 22:16:05.212059 INFO: [APUAPC] D13_APC_0: 0xffffffff
10018 22:16:05.215270 INFO: [APUAPC] D13_APC_1: 0xffffffff
10019 22:16:05.218502 INFO: [APUAPC] D13_APC_2: 0x3fffff
10020 22:16:05.221981 INFO: [APUAPC] D13_APC_3: 0x0
10021 22:16:05.225291 INFO: [APUAPC] D14_APC_0: 0xffffffff
10022 22:16:05.228381 INFO: [APUAPC] D14_APC_1: 0xffffffff
10023 22:16:05.231693 INFO: [APUAPC] D14_APC_2: 0x3fffff
10024 22:16:05.235053 INFO: [APUAPC] D14_APC_3: 0x0
10025 22:16:05.238394 INFO: [APUAPC] D15_APC_0: 0xffffffff
10026 22:16:05.241817 INFO: [APUAPC] D15_APC_1: 0xffffffff
10027 22:16:05.244710 INFO: [APUAPC] D15_APC_2: 0x3fffff
10028 22:16:05.248606 INFO: [APUAPC] D15_APC_3: 0x0
10029 22:16:05.251565 INFO: [APUAPC] APC_CON: 0x4
10030 22:16:05.252030 INFO: [NOCDAPC] D0_APC_0: 0x0
10031 22:16:05.255119 INFO: [NOCDAPC] D0_APC_1: 0x0
10032 22:16:05.258435 INFO: [NOCDAPC] D1_APC_0: 0x0
10033 22:16:05.262028 INFO: [NOCDAPC] D1_APC_1: 0xfff
10034 22:16:05.264983 INFO: [NOCDAPC] D2_APC_0: 0x0
10035 22:16:05.267962 INFO: [NOCDAPC] D2_APC_1: 0xfff
10036 22:16:05.271823 INFO: [NOCDAPC] D3_APC_0: 0x0
10037 22:16:05.274776 INFO: [NOCDAPC] D3_APC_1: 0xfff
10038 22:16:05.278143 INFO: [NOCDAPC] D4_APC_0: 0x0
10039 22:16:05.281296 INFO: [NOCDAPC] D4_APC_1: 0xfff
10040 22:16:05.281784 INFO: [NOCDAPC] D5_APC_0: 0x0
10041 22:16:05.285325 INFO: [NOCDAPC] D5_APC_1: 0xfff
10042 22:16:05.288920 INFO: [NOCDAPC] D6_APC_0: 0x0
10043 22:16:05.291550 INFO: [NOCDAPC] D6_APC_1: 0xfff
10044 22:16:05.295239 INFO: [NOCDAPC] D7_APC_0: 0x0
10045 22:16:05.298447 INFO: [NOCDAPC] D7_APC_1: 0xfff
10046 22:16:05.301591 INFO: [NOCDAPC] D8_APC_0: 0x0
10047 22:16:05.304561 INFO: [NOCDAPC] D8_APC_1: 0xfff
10048 22:16:05.308314 INFO: [NOCDAPC] D9_APC_0: 0x0
10049 22:16:05.311241 INFO: [NOCDAPC] D9_APC_1: 0xfff
10050 22:16:05.314451 INFO: [NOCDAPC] D10_APC_0: 0x0
10051 22:16:05.314905 INFO: [NOCDAPC] D10_APC_1: 0xfff
10052 22:16:05.318019 INFO: [NOCDAPC] D11_APC_0: 0x0
10053 22:16:05.321201 INFO: [NOCDAPC] D11_APC_1: 0xfff
10054 22:16:05.325085 INFO: [NOCDAPC] D12_APC_0: 0x0
10055 22:16:05.327851 INFO: [NOCDAPC] D12_APC_1: 0xfff
10056 22:16:05.331250 INFO: [NOCDAPC] D13_APC_0: 0x0
10057 22:16:05.334831 INFO: [NOCDAPC] D13_APC_1: 0xfff
10058 22:16:05.338394 INFO: [NOCDAPC] D14_APC_0: 0x0
10059 22:16:05.341451 INFO: [NOCDAPC] D14_APC_1: 0xfff
10060 22:16:05.344804 INFO: [NOCDAPC] D15_APC_0: 0x0
10061 22:16:05.348048 INFO: [NOCDAPC] D15_APC_1: 0xfff
10062 22:16:05.351466 INFO: [NOCDAPC] APC_CON: 0x4
10063 22:16:05.354589 INFO: [APUAPC] set_apusys_apc done
10064 22:16:05.357807 INFO: [DEVAPC] devapc_init done
10065 22:16:05.361663 INFO: GICv3 without legacy support detected.
10066 22:16:05.364776 INFO: ARM GICv3 driver initialized in EL3
10067 22:16:05.368025 INFO: Maximum SPI INTID supported: 639
10068 22:16:05.371066 INFO: BL31: Initializing runtime services
10069 22:16:05.377696 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10070 22:16:05.380912 INFO: SPM: enable CPC mode
10071 22:16:05.387982 INFO: mcdi ready for mcusys-off-idle and system suspend
10072 22:16:05.391175 INFO: BL31: Preparing for EL3 exit to normal world
10073 22:16:05.394649 INFO: Entry point address = 0x80000000
10074 22:16:05.397670 INFO: SPSR = 0x8
10075 22:16:05.402612
10076 22:16:05.403181
10077 22:16:05.403665
10078 22:16:05.405589 Starting depthcharge on Spherion...
10079 22:16:05.406012
10080 22:16:05.406358 Wipe memory regions:
10081 22:16:05.406933
10082 22:16:05.409747 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10083 22:16:05.410465 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10084 22:16:05.410920 Setting prompt string to ['asurada:']
10085 22:16:05.411340 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10086 22:16:05.412022 [0x00000040000000, 0x00000054600000)
10087 22:16:05.531026
10088 22:16:05.531164 [0x00000054660000, 0x00000080000000)
10089 22:16:05.791671
10090 22:16:05.791836 [0x000000821a7280, 0x000000ffe64000)
10091 22:16:06.535935
10092 22:16:06.536109 [0x00000100000000, 0x00000240000000)
10093 22:16:08.426218
10094 22:16:08.428782 Initializing XHCI USB controller at 0x11200000.
10095 22:16:09.467178
10096 22:16:09.470190 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10097 22:16:09.470624
10098 22:16:09.470964
10099 22:16:09.471285
10100 22:16:09.472031 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10102 22:16:09.573197 asurada: tftpboot 192.168.201.1 10583894/tftp-deploy-tapz7bnq/kernel/image.itb 10583894/tftp-deploy-tapz7bnq/kernel/cmdline
10103 22:16:09.573766 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10104 22:16:09.574167 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10105 22:16:09.578887 tftpboot 192.168.201.1 10583894/tftp-deploy-tapz7bnq/kernel/image.ittp-deploy-tapz7bnq/kernel/cmdline
10106 22:16:09.579323
10107 22:16:09.579658 Waiting for link
10108 22:16:09.738927
10109 22:16:09.739419 R8152: Initializing
10110 22:16:09.739820
10111 22:16:09.742269 Version 9 (ocp_data = 6010)
10112 22:16:09.742695
10113 22:16:09.745562 R8152: Done initializing
10114 22:16:09.745998
10115 22:16:09.746339 Adding net device
10116 22:16:11.688766
10117 22:16:11.689284 done.
10118 22:16:11.689938
10119 22:16:11.690289 MAC: 00:e0:4c:78:7a:aa
10120 22:16:11.690612
10121 22:16:11.691990 Sending DHCP discover... done.
10122 22:16:11.692418
10123 22:16:11.695255 Waiting for reply... done.
10124 22:16:11.695686
10125 22:16:11.698446 Sending DHCP request... done.
10126 22:16:11.698876
10127 22:16:11.702255 Waiting for reply... done.
10128 22:16:11.702682
10129 22:16:11.703020 My ip is 192.168.201.12
10130 22:16:11.703337
10131 22:16:11.705579 The DHCP server ip is 192.168.201.1
10132 22:16:11.706006
10133 22:16:11.711787 TFTP server IP predefined by user: 192.168.201.1
10134 22:16:11.712218
10135 22:16:11.718643 Bootfile predefined by user: 10583894/tftp-deploy-tapz7bnq/kernel/image.itb
10136 22:16:11.719095
10137 22:16:11.721372 Sending tftp read request... done.
10138 22:16:11.721974
10139 22:16:11.727267 Waiting for the transfer...
10140 22:16:11.727849
10141 22:16:12.024270 00000000 ################################################################
10142 22:16:12.024410
10143 22:16:12.281319 00080000 ################################################################
10144 22:16:12.281483
10145 22:16:12.531710 00100000 ################################################################
10146 22:16:12.531840
10147 22:16:12.805912 00180000 ################################################################
10148 22:16:12.806046
10149 22:16:13.061356 00200000 ################################################################
10150 22:16:13.061493
10151 22:16:13.321490 00280000 ################################################################
10152 22:16:13.321660
10153 22:16:13.598372 00300000 ################################################################
10154 22:16:13.598506
10155 22:16:13.869453 00380000 ################################################################
10156 22:16:13.869599
10157 22:16:14.117857 00400000 ################################################################
10158 22:16:14.118009
10159 22:16:14.372238 00480000 ################################################################
10160 22:16:14.372376
10161 22:16:14.637276 00500000 ################################################################
10162 22:16:14.637426
10163 22:16:14.914550 00580000 ################################################################
10164 22:16:14.914698
10165 22:16:15.190156 00600000 ################################################################
10166 22:16:15.190301
10167 22:16:15.467584 00680000 ################################################################
10168 22:16:15.467734
10169 22:16:15.746093 00700000 ################################################################
10170 22:16:15.746245
10171 22:16:16.024723 00780000 ################################################################
10172 22:16:16.024885
10173 22:16:16.274784 00800000 ################################################################
10174 22:16:16.274931
10175 22:16:16.535055 00880000 ################################################################
10176 22:16:16.535205
10177 22:16:16.815572 00900000 ################################################################
10178 22:16:16.815747
10179 22:16:17.087264 00980000 ################################################################
10180 22:16:17.087417
10181 22:16:17.339352 00a00000 ################################################################
10182 22:16:17.339498
10183 22:16:17.608045 00a80000 ################################################################
10184 22:16:17.608197
10185 22:16:17.873286 00b00000 ################################################################
10186 22:16:17.873439
10187 22:16:18.145626 00b80000 ################################################################
10188 22:16:18.145784
10189 22:16:18.409784 00c00000 ################################################################
10190 22:16:18.409937
10191 22:16:18.686566 00c80000 ################################################################
10192 22:16:18.686725
10193 22:16:18.965157 00d00000 ################################################################
10194 22:16:18.965308
10195 22:16:19.242177 00d80000 ################################################################
10196 22:16:19.242327
10197 22:16:19.506739 00e00000 ################################################################
10198 22:16:19.506876
10199 22:16:19.798102 00e80000 ################################################################
10200 22:16:19.798239
10201 22:16:20.080433 00f00000 ################################################################
10202 22:16:20.080609
10203 22:16:20.372640 00f80000 ################################################################
10204 22:16:20.372806
10205 22:16:20.636226 01000000 ################################################################
10206 22:16:20.636409
10207 22:16:20.893089 01080000 ################################################################
10208 22:16:20.893226
10209 22:16:21.179405 01100000 ################################################################
10210 22:16:21.179540
10211 22:16:21.450183 01180000 ################################################################
10212 22:16:21.450329
10213 22:16:21.699093 01200000 ################################################################
10214 22:16:21.699226
10215 22:16:21.963400 01280000 ################################################################
10216 22:16:21.963538
10217 22:16:22.212622 01300000 ################################################################
10218 22:16:22.212755
10219 22:16:22.463417 01380000 ################################################################
10220 22:16:22.463554
10221 22:16:22.756343 01400000 ################################################################
10222 22:16:22.756490
10223 22:16:23.043860 01480000 ################################################################
10224 22:16:23.044004
10225 22:16:23.320501 01500000 ################################################################
10226 22:16:23.320643
10227 22:16:23.601749 01580000 ################################################################
10228 22:16:23.601895
10229 22:16:23.867788 01600000 ################################################################
10230 22:16:23.867971
10231 22:16:24.141135 01680000 ################################################################
10232 22:16:24.141285
10233 22:16:24.430236 01700000 ################################################################
10234 22:16:24.430383
10235 22:16:24.715246 01780000 ################################################################
10236 22:16:24.715392
10237 22:16:24.982395 01800000 ################################################################
10238 22:16:24.982526
10239 22:16:25.264349 01880000 ################################################################
10240 22:16:25.264511
10241 22:16:25.537240 01900000 ################################################################
10242 22:16:25.537395
10243 22:16:25.826001 01980000 ################################################################
10244 22:16:25.826142
10245 22:16:26.102142 01a00000 ############################################################### done.
10246 22:16:26.102273
10247 22:16:26.105644 The bootfile was 27772470 bytes long.
10248 22:16:26.105718
10249 22:16:26.109104 Sending tftp read request... done.
10250 22:16:26.109189
10251 22:16:26.112432 Waiting for the transfer...
10252 22:16:26.112521
10253 22:16:26.112591 00000000 # done.
10254 22:16:26.112658
10255 22:16:26.122309 Command line loaded dynamically from TFTP file: 10583894/tftp-deploy-tapz7bnq/kernel/cmdline
10256 22:16:26.122479
10257 22:16:26.142322 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10583894/extract-nfsrootfs-wh9mu87m,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10258 22:16:26.142571
10259 22:16:26.142710 Loading FIT.
10260 22:16:26.142832
10261 22:16:26.145957 Image ramdisk-1 has 17641781 bytes.
10262 22:16:26.146113
10263 22:16:26.149305 Image fdt-1 has 46924 bytes.
10264 22:16:26.149479
10265 22:16:26.152841 Image kernel-1 has 10081729 bytes.
10266 22:16:26.153045
10267 22:16:26.158858 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10268 22:16:26.159104
10269 22:16:26.179194 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10270 22:16:26.179774
10271 22:16:26.182222 Choosing best match conf-1 for compat google,spherion-rev2.
10272 22:16:26.186714
10273 22:16:26.191677 Connected to device vid:did:rid of 1ae0:0028:00
10274 22:16:26.199843
10275 22:16:26.202961 tpm_get_response: command 0x17b, return code 0x0
10276 22:16:26.203436
10277 22:16:26.206406 ec_init: CrosEC protocol v3 supported (256, 248)
10278 22:16:26.210951
10279 22:16:26.214514 tpm_cleanup: add release locality here.
10280 22:16:26.214939
10281 22:16:26.215273 Shutting down all USB controllers.
10282 22:16:26.217645
10283 22:16:26.218067 Removing current net device
10284 22:16:26.218408
10285 22:16:26.224432 Exiting depthcharge with code 4 at timestamp: 50098055
10286 22:16:26.224858
10287 22:16:26.227578 LZMA decompressing kernel-1 to 0x821a6718
10288 22:16:26.228000
10289 22:16:26.230730 LZMA decompressing kernel-1 to 0x40000000
10290 22:16:27.498274
10291 22:16:27.498809 jumping to kernel
10292 22:16:27.500297 end: 2.2.4 bootloader-commands (duration 00:00:22) [common]
10293 22:16:27.501025 start: 2.2.5 auto-login-action (timeout 00:04:03) [common]
10294 22:16:27.501669 Setting prompt string to ['Linux version [0-9]']
10295 22:16:27.502048 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10296 22:16:27.502443 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10297 22:16:27.580704
10298 22:16:27.583649 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10299 22:16:27.587761 start: 2.2.5.1 login-action (timeout 00:04:03) [common]
10300 22:16:27.588223 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10301 22:16:27.588735 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10302 22:16:27.589214 Using line separator: #'\n'#
10303 22:16:27.589732 No login prompt set.
10304 22:16:27.590191 Parsing kernel messages
10305 22:16:27.590653 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10306 22:16:27.591619 [login-action] Waiting for messages, (timeout 00:04:03)
10307 22:16:27.606609 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1606555-arm64-gcc-10-defconfig-arm64-chromebook-vtq55) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Sun Jun 4 21:56:05 UTC 2023
10308 22:16:27.609863 [ 0.000000] random: crng init done
10309 22:16:27.613469 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10310 22:16:27.616465 [ 0.000000] efi: UEFI not found.
10311 22:16:27.626928 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10312 22:16:27.632998 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10313 22:16:27.642976 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10314 22:16:27.652984 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10315 22:16:27.659650 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10316 22:16:27.666215 [ 0.000000] printk: bootconsole [mtk8250] enabled
10317 22:16:27.669445 [ 0.000000] NUMA: No NUMA configuration found
10318 22:16:27.679467 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10319 22:16:27.682593 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10320 22:16:27.686025 [ 0.000000] Zone ranges:
10321 22:16:27.692447 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10322 22:16:27.696212 [ 0.000000] DMA32 empty
10323 22:16:27.702392 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10324 22:16:27.705888 [ 0.000000] Movable zone start for each node
10325 22:16:27.708810 [ 0.000000] Early memory node ranges
10326 22:16:27.715790 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10327 22:16:27.722524 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10328 22:16:27.728861 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10329 22:16:27.735682 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10330 22:16:27.738686 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10331 22:16:27.748676 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10332 22:16:27.804624 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10333 22:16:27.810877 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10334 22:16:27.817265 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10335 22:16:27.820986 [ 0.000000] psci: probing for conduit method from DT.
10336 22:16:27.827279 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10337 22:16:27.830518 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10338 22:16:27.837228 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10339 22:16:27.840503 [ 0.000000] psci: SMC Calling Convention v1.2
10340 22:16:27.846840 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10341 22:16:27.850696 [ 0.000000] Detected VIPT I-cache on CPU0
10342 22:16:27.857190 [ 0.000000] CPU features: detected: GIC system register CPU interface
10343 22:16:27.864005 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10344 22:16:27.870027 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10345 22:16:27.876806 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10346 22:16:27.886821 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10347 22:16:27.893589 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10348 22:16:27.897287 [ 0.000000] alternatives: applying boot alternatives
10349 22:16:27.903504 [ 0.000000] Fallback order for Node 0: 0
10350 22:16:27.909898 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10351 22:16:27.913439 [ 0.000000] Policy zone: Normal
10352 22:16:27.933212 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10583894/extract-nfsrootfs-wh9mu87m,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10353 22:16:27.943439 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10354 22:16:27.955368 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10355 22:16:27.965627 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10356 22:16:27.972269 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10357 22:16:27.975061 <6>[ 0.000000] software IO TLB: area num 8.
10358 22:16:28.031468 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10359 22:16:28.180549 <6>[ 0.000000] Memory: 7955712K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397056K reserved, 32768K cma-reserved)
10360 22:16:28.186948 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10361 22:16:28.193649 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10362 22:16:28.197309 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10363 22:16:28.204271 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10364 22:16:28.210240 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10365 22:16:28.214050 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10366 22:16:28.223649 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10367 22:16:28.229936 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10368 22:16:28.236674 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10369 22:16:28.243436 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10370 22:16:28.246321 <6>[ 0.000000] GICv3: 608 SPIs implemented
10371 22:16:28.249755 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10372 22:16:28.256095 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10373 22:16:28.259382 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10374 22:16:28.266338 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10375 22:16:28.279319 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10376 22:16:28.293571 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10377 22:16:28.299935 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10378 22:16:28.307800 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10379 22:16:28.320457 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10380 22:16:28.327246 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10381 22:16:28.333097 <6>[ 0.009232] Console: colour dummy device 80x25
10382 22:16:28.343513 <6>[ 0.013975] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10383 22:16:28.350002 <6>[ 0.024482] pid_max: default: 32768 minimum: 301
10384 22:16:28.353247 <6>[ 0.029386] LSM: Security Framework initializing
10385 22:16:28.359863 <6>[ 0.034324] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10386 22:16:28.369856 <6>[ 0.042138] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10387 22:16:28.380057 <6>[ 0.051572] cblist_init_generic: Setting adjustable number of callback queues.
10388 22:16:28.383397 <6>[ 0.059026] cblist_init_generic: Setting shift to 3 and lim to 1.
10389 22:16:28.389784 <6>[ 0.065403] cblist_init_generic: Setting shift to 3 and lim to 1.
10390 22:16:28.396745 <6>[ 0.071810] rcu: Hierarchical SRCU implementation.
10391 22:16:28.402969 <6>[ 0.076855] rcu: Max phase no-delay instances is 1000.
10392 22:16:28.409409 <6>[ 0.083878] EFI services will not be available.
10393 22:16:28.412751 <6>[ 0.088848] smp: Bringing up secondary CPUs ...
10394 22:16:28.420648 <6>[ 0.093901] Detected VIPT I-cache on CPU1
10395 22:16:28.427777 <6>[ 0.093974] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10396 22:16:28.434194 <6>[ 0.094004] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10397 22:16:28.437615 <6>[ 0.094345] Detected VIPT I-cache on CPU2
10398 22:16:28.443928 <6>[ 0.094398] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10399 22:16:28.450704 <6>[ 0.094415] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10400 22:16:28.457281 <6>[ 0.094672] Detected VIPT I-cache on CPU3
10401 22:16:28.463640 <6>[ 0.094720] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10402 22:16:28.470129 <6>[ 0.094734] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10403 22:16:28.473587 <6>[ 0.095043] CPU features: detected: Spectre-v4
10404 22:16:28.480376 <6>[ 0.095049] CPU features: detected: Spectre-BHB
10405 22:16:28.483457 <6>[ 0.095055] Detected PIPT I-cache on CPU4
10406 22:16:28.489876 <6>[ 0.095110] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10407 22:16:28.496910 <6>[ 0.095128] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10408 22:16:28.503274 <6>[ 0.095428] Detected PIPT I-cache on CPU5
10409 22:16:28.510289 <6>[ 0.095491] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10410 22:16:28.516743 <6>[ 0.095507] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10411 22:16:28.520060 <6>[ 0.095790] Detected PIPT I-cache on CPU6
10412 22:16:28.526829 <6>[ 0.095854] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10413 22:16:28.533641 <6>[ 0.095870] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10414 22:16:28.539789 <6>[ 0.096170] Detected PIPT I-cache on CPU7
10415 22:16:28.546447 <6>[ 0.096236] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10416 22:16:28.553140 <6>[ 0.096252] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10417 22:16:28.556336 <6>[ 0.096300] smp: Brought up 1 node, 8 CPUs
10418 22:16:28.562726 <6>[ 0.237649] SMP: Total of 8 processors activated.
10419 22:16:28.566192 <6>[ 0.242570] CPU features: detected: 32-bit EL0 Support
10420 22:16:28.576306 <6>[ 0.247932] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10421 22:16:28.582606 <6>[ 0.256733] CPU features: detected: Common not Private translations
10422 22:16:28.589353 <6>[ 0.263208] CPU features: detected: CRC32 instructions
10423 22:16:28.592548 <6>[ 0.268560] CPU features: detected: RCpc load-acquire (LDAPR)
10424 22:16:28.599091 <6>[ 0.274519] CPU features: detected: LSE atomic instructions
10425 22:16:28.605957 <6>[ 0.280300] CPU features: detected: Privileged Access Never
10426 22:16:28.612196 <6>[ 0.286080] CPU features: detected: RAS Extension Support
10427 22:16:28.619182 <6>[ 0.291723] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10428 22:16:28.622670 <6>[ 0.298942] CPU: All CPU(s) started at EL2
10429 22:16:28.628859 <6>[ 0.303259] alternatives: applying system-wide alternatives
10430 22:16:28.638171 <6>[ 0.313996] devtmpfs: initialized
10431 22:16:28.650732 <6>[ 0.322866] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10432 22:16:28.660251 <6>[ 0.332830] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10433 22:16:28.667204 <6>[ 0.341025] pinctrl core: initialized pinctrl subsystem
10434 22:16:28.670315 <6>[ 0.347690] DMI not present or invalid.
10435 22:16:28.677172 <6>[ 0.352116] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10436 22:16:28.687079 <6>[ 0.359016] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10437 22:16:28.693420 <6>[ 0.366604] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10438 22:16:28.704022 <6>[ 0.374834] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10439 22:16:28.707657 <6>[ 0.383085] audit: initializing netlink subsys (disabled)
10440 22:16:28.717261 <5>[ 0.388788] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10441 22:16:28.723616 <6>[ 0.389502] thermal_sys: Registered thermal governor 'step_wise'
10442 22:16:28.730103 <6>[ 0.396755] thermal_sys: Registered thermal governor 'power_allocator'
10443 22:16:28.733495 <6>[ 0.403013] cpuidle: using governor menu
10444 22:16:28.740232 <6>[ 0.413978] NET: Registered PF_QIPCRTR protocol family
10445 22:16:28.746440 <6>[ 0.419486] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10446 22:16:28.752758 <6>[ 0.426592] ASID allocator initialised with 32768 entries
10447 22:16:28.756978 <6>[ 0.433165] Serial: AMBA PL011 UART driver
10448 22:16:28.766065 <4>[ 0.441852] Trying to register duplicate clock ID: 134
10449 22:16:28.822767 <6>[ 0.501399] KASLR enabled
10450 22:16:28.837468 <6>[ 0.509270] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10451 22:16:28.843669 <6>[ 0.516282] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10452 22:16:28.850333 <6>[ 0.522772] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10453 22:16:28.857081 <6>[ 0.529778] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10454 22:16:28.863676 <6>[ 0.536266] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10455 22:16:28.870051 <6>[ 0.543273] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10456 22:16:28.876470 <6>[ 0.549760] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10457 22:16:28.883265 <6>[ 0.556767] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10458 22:16:28.886709 <6>[ 0.564294] ACPI: Interpreter disabled.
10459 22:16:28.895001 <6>[ 0.570687] iommu: Default domain type: Translated
10460 22:16:28.901832 <6>[ 0.575802] iommu: DMA domain TLB invalidation policy: strict mode
10461 22:16:28.904552 <5>[ 0.582461] SCSI subsystem initialized
10462 22:16:28.911717 <6>[ 0.586630] usbcore: registered new interface driver usbfs
10463 22:16:28.918244 <6>[ 0.592363] usbcore: registered new interface driver hub
10464 22:16:28.920980 <6>[ 0.597916] usbcore: registered new device driver usb
10465 22:16:28.928699 <6>[ 0.603996] pps_core: LinuxPPS API ver. 1 registered
10466 22:16:28.938044 <6>[ 0.609190] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10467 22:16:28.941572 <6>[ 0.618537] PTP clock support registered
10468 22:16:28.944656 <6>[ 0.622780] EDAC MC: Ver: 3.0.0
10469 22:16:28.952463 <6>[ 0.627923] FPGA manager framework
10470 22:16:28.958723 <6>[ 0.631604] Advanced Linux Sound Architecture Driver Initialized.
10471 22:16:28.962202 <6>[ 0.638373] vgaarb: loaded
10472 22:16:28.969171 <6>[ 0.641554] clocksource: Switched to clocksource arch_sys_counter
10473 22:16:28.973023 <5>[ 0.647991] VFS: Disk quotas dquot_6.6.0
10474 22:16:28.979070 <6>[ 0.652177] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10475 22:16:28.982195 <6>[ 0.659369] pnp: PnP ACPI: disabled
10476 22:16:28.990241 <6>[ 0.666061] NET: Registered PF_INET protocol family
10477 22:16:29.000279 <6>[ 0.671645] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10478 22:16:29.012135 <6>[ 0.683927] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10479 22:16:29.021780 <6>[ 0.692742] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10480 22:16:29.028341 <6>[ 0.700713] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10481 22:16:29.034829 <6>[ 0.709414] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10482 22:16:29.047543 <6>[ 0.719163] TCP: Hash tables configured (established 65536 bind 65536)
10483 22:16:29.053370 <6>[ 0.726018] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10484 22:16:29.059712 <6>[ 0.733217] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10485 22:16:29.066900 <6>[ 0.740919] NET: Registered PF_UNIX/PF_LOCAL protocol family
10486 22:16:29.073697 <6>[ 0.747095] RPC: Registered named UNIX socket transport module.
10487 22:16:29.077452 <6>[ 0.753250] RPC: Registered udp transport module.
10488 22:16:29.083522 <6>[ 0.758183] RPC: Registered tcp transport module.
10489 22:16:29.089894 <6>[ 0.763115] RPC: Registered tcp NFSv4.1 backchannel transport module.
10490 22:16:29.093391 <6>[ 0.769788] PCI: CLS 0 bytes, default 64
10491 22:16:29.096393 <6>[ 0.774142] Unpacking initramfs...
10492 22:16:29.106383 <6>[ 0.778278] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10493 22:16:29.113105 <6>[ 0.786940] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10494 22:16:29.119802 <6>[ 0.795800] kvm [1]: IPA Size Limit: 40 bits
10495 22:16:29.123312 <6>[ 0.800327] kvm [1]: GICv3: no GICV resource entry
10496 22:16:29.129905 <6>[ 0.805348] kvm [1]: disabling GICv2 emulation
10497 22:16:29.136620 <6>[ 0.810033] kvm [1]: GIC system register CPU interface enabled
10498 22:16:29.140120 <6>[ 0.816195] kvm [1]: vgic interrupt IRQ18
10499 22:16:29.146380 <6>[ 0.820549] kvm [1]: VHE mode initialized successfully
10500 22:16:29.149961 <5>[ 0.827048] Initialise system trusted keyrings
10501 22:16:29.156457 <6>[ 0.831830] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10502 22:16:29.166482 <6>[ 0.841843] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10503 22:16:29.173470 <5>[ 0.848263] NFS: Registering the id_resolver key type
10504 22:16:29.176264 <5>[ 0.853574] Key type id_resolver registered
10505 22:16:29.182573 <5>[ 0.857992] Key type id_legacy registered
10506 22:16:29.189291 <6>[ 0.862269] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10507 22:16:29.196138 <6>[ 0.869189] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10508 22:16:29.202444 <6>[ 0.876919] 9p: Installing v9fs 9p2000 file system support
10509 22:16:29.239325 <5>[ 0.914432] Key type asymmetric registered
10510 22:16:29.242232 <5>[ 0.918762] Asymmetric key parser 'x509' registered
10511 22:16:29.252173 <6>[ 0.923906] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10512 22:16:29.255928 <6>[ 0.931520] io scheduler mq-deadline registered
10513 22:16:29.258749 <6>[ 0.936282] io scheduler kyber registered
10514 22:16:29.277740 <6>[ 0.953246] EINJ: ACPI disabled.
10515 22:16:29.309629 <4>[ 0.978864] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10516 22:16:29.319341 <4>[ 0.989511] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10517 22:16:29.334651 <6>[ 1.010512] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10518 22:16:29.343046 <6>[ 1.018566] printk: console [ttyS0] disabled
10519 22:16:29.370908 <6>[ 1.043219] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10520 22:16:29.377437 <6>[ 1.052692] printk: console [ttyS0] enabled
10521 22:16:29.380556 <6>[ 1.052692] printk: console [ttyS0] enabled
10522 22:16:29.387501 <6>[ 1.061586] printk: bootconsole [mtk8250] disabled
10523 22:16:29.390369 <6>[ 1.061586] printk: bootconsole [mtk8250] disabled
10524 22:16:29.397312 <6>[ 1.072867] SuperH (H)SCI(F) driver initialized
10525 22:16:29.400380 <6>[ 1.078143] msm_serial: driver initialized
10526 22:16:29.414740 <6>[ 1.087112] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10527 22:16:29.424676 <6>[ 1.095660] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10528 22:16:29.431407 <6>[ 1.104202] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10529 22:16:29.441242 <6>[ 1.112830] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10530 22:16:29.448062 <6>[ 1.121536] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10531 22:16:29.457793 <6>[ 1.130260] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10532 22:16:29.468010 <6>[ 1.138802] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10533 22:16:29.474525 <6>[ 1.147610] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10534 22:16:29.484633 <6>[ 1.156154] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10535 22:16:29.496454 <6>[ 1.171887] loop: module loaded
10536 22:16:29.503074 <6>[ 1.177934] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10537 22:16:29.525776 <4>[ 1.201359] mtk-pmic-keys: Failed to locate of_node [id: -1]
10538 22:16:29.532442 <6>[ 1.208176] megasas: 07.719.03.00-rc1
10539 22:16:29.541921 <6>[ 1.217701] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10540 22:16:29.549172 <6>[ 1.224929] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10541 22:16:29.566296 <6>[ 1.241812] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10542 22:16:29.621699 <6>[ 1.290301] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9
10543 22:16:29.869428 <6>[ 1.545122] Freeing initrd memory: 17228K
10544 22:16:29.879876 <6>[ 1.555463] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10545 22:16:29.890572 <6>[ 1.566597] tun: Universal TUN/TAP device driver, 1.6
10546 22:16:29.894304 <6>[ 1.572656] thunder_xcv, ver 1.0
10547 22:16:29.897409 <6>[ 1.576159] thunder_bgx, ver 1.0
10548 22:16:29.900798 <6>[ 1.579657] nicpf, ver 1.0
10549 22:16:29.911411 <6>[ 1.583683] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10550 22:16:29.914802 <6>[ 1.591159] hns3: Copyright (c) 2017 Huawei Corporation.
10551 22:16:29.921370 <6>[ 1.596748] hclge is initializing
10552 22:16:29.924792 <6>[ 1.600329] e1000: Intel(R) PRO/1000 Network Driver
10553 22:16:29.930963 <6>[ 1.605458] e1000: Copyright (c) 1999-2006 Intel Corporation.
10554 22:16:29.934676 <6>[ 1.611474] e1000e: Intel(R) PRO/1000 Network Driver
10555 22:16:29.940691 <6>[ 1.616689] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10556 22:16:29.947751 <6>[ 1.622876] igb: Intel(R) Gigabit Ethernet Network Driver
10557 22:16:29.954024 <6>[ 1.628525] igb: Copyright (c) 2007-2014 Intel Corporation.
10558 22:16:29.961131 <6>[ 1.634362] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10559 22:16:29.967622 <6>[ 1.640880] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10560 22:16:29.970920 <6>[ 1.647342] sky2: driver version 1.30
10561 22:16:29.977080 <6>[ 1.652346] VFIO - User Level meta-driver version: 0.3
10562 22:16:29.984979 <6>[ 1.660509] usbcore: registered new interface driver usb-storage
10563 22:16:29.991629 <6>[ 1.666963] usbcore: registered new device driver onboard-usb-hub
10564 22:16:30.000637 <6>[ 1.676036] mt6397-rtc mt6359-rtc: registered as rtc0
10565 22:16:30.009844 <6>[ 1.681503] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-04T22:16:30 UTC (1685916990)
10566 22:16:30.013476 <6>[ 1.691064] i2c_dev: i2c /dev entries driver
10567 22:16:30.031025 <6>[ 1.702903] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10568 22:16:30.037664 <6>[ 1.713188] sdhci: Secure Digital Host Controller Interface driver
10569 22:16:30.044419 <6>[ 1.719627] sdhci: Copyright(c) Pierre Ossman
10570 22:16:30.050340 <6>[ 1.725030] Synopsys Designware Multimedia Card Interface Driver
10571 22:16:30.053732 <6>[ 1.731629] mmc0: CQHCI version 5.10
10572 22:16:30.060400 <6>[ 1.732180] sdhci-pltfm: SDHCI platform and OF driver helper
10573 22:16:30.067690 <6>[ 1.743488] ledtrig-cpu: registered to indicate activity on CPUs
10574 22:16:30.078174 <6>[ 1.750850] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10575 22:16:30.081922 <6>[ 1.758244] usbcore: registered new interface driver usbhid
10576 22:16:30.088684 <6>[ 1.764070] usbhid: USB HID core driver
10577 22:16:30.095325 <6>[ 1.768317] spi_master spi0: will run message pump with realtime priority
10578 22:16:30.139153 <6>[ 1.808364] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10579 22:16:30.155638 <6>[ 1.824589] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10580 22:16:30.163075 <6>[ 1.838171] mmc0: Command Queue Engine enabled
10581 22:16:30.169991 <6>[ 1.839415] cros-ec-spi spi0.0: Chrome EC device registered
10582 22:16:30.173223 <6>[ 1.842909] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10583 22:16:30.180430 <6>[ 1.856060] mmcblk0: mmc0:0001 DA4128 116 GiB
10584 22:16:30.192663 <6>[ 1.864765] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10585 22:16:30.199329 <6>[ 1.866465] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10586 22:16:30.206457 <6>[ 1.876141] NET: Registered PF_PACKET protocol family
10587 22:16:30.209459 <6>[ 1.881303] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10588 22:16:30.216339 <6>[ 1.885411] 9pnet: Installing 9P2000 support
10589 22:16:30.219133 <6>[ 1.891173] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10590 22:16:30.222944 <5>[ 1.895096] Key type dns_resolver registered
10591 22:16:30.228752 <6>[ 1.900915] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10592 22:16:30.236063 <6>[ 1.905453] registered taskstats version 1
10593 22:16:30.238916 <5>[ 1.915739] Loading compiled-in X.509 certificates
10594 22:16:30.275530 <4>[ 1.944480] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10595 22:16:30.285057 <4>[ 1.955173] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10596 22:16:30.295571 <3>[ 1.968070] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10597 22:16:30.307099 <6>[ 1.982936] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10598 22:16:30.314091 <6>[ 1.989707] xhci-mtk 11200000.usb: xHCI Host Controller
10599 22:16:30.321012 <6>[ 1.995210] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10600 22:16:30.330598 <6>[ 2.003061] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10601 22:16:30.337263 <6>[ 2.012495] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10602 22:16:30.344032 <6>[ 2.018561] xhci-mtk 11200000.usb: xHCI Host Controller
10603 22:16:30.350560 <6>[ 2.024043] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10604 22:16:30.357087 <6>[ 2.031694] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10605 22:16:30.364507 <6>[ 2.039409] hub 1-0:1.0: USB hub found
10606 22:16:30.367302 <6>[ 2.043432] hub 1-0:1.0: 1 port detected
10607 22:16:30.374338 <6>[ 2.047776] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10608 22:16:30.380836 <6>[ 2.056367] hub 2-0:1.0: USB hub found
10609 22:16:30.384096 <6>[ 2.060381] hub 2-0:1.0: 1 port detected
10610 22:16:30.391457 <6>[ 2.067489] mtk-msdc 11f70000.mmc: Got CD GPIO
10611 22:16:30.409345 <6>[ 2.081779] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10612 22:16:30.415913 <6>[ 2.089816] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10613 22:16:30.425629 <4>[ 2.097817] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10614 22:16:30.435754 <6>[ 2.107479] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10615 22:16:30.441821 <6>[ 2.115562] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10616 22:16:30.448971 <6>[ 2.123599] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10617 22:16:30.459260 <6>[ 2.131513] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10618 22:16:30.466149 <6>[ 2.139335] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10619 22:16:30.475641 <6>[ 2.147157] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10620 22:16:30.485715 <6>[ 2.157912] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10621 22:16:30.492735 <6>[ 2.166292] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10622 22:16:30.502690 <6>[ 2.174636] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10623 22:16:30.509312 <6>[ 2.182979] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10624 22:16:30.519223 <6>[ 2.191322] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10625 22:16:30.525909 <6>[ 2.199665] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10626 22:16:30.536213 <6>[ 2.208008] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10627 22:16:30.542962 <6>[ 2.216351] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10628 22:16:30.552715 <6>[ 2.224694] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10629 22:16:30.559685 <6>[ 2.233037] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10630 22:16:30.569782 <6>[ 2.241380] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10631 22:16:30.576425 <6>[ 2.249728] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10632 22:16:30.586211 <6>[ 2.258072] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10633 22:16:30.593065 <6>[ 2.266417] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10634 22:16:30.603097 <6>[ 2.274767] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10635 22:16:30.609677 <6>[ 2.283680] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10636 22:16:30.616267 <6>[ 2.291145] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10637 22:16:30.623207 <6>[ 2.298158] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10638 22:16:30.629833 <6>[ 2.305239] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10639 22:16:30.639592 <6>[ 2.312519] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10640 22:16:30.646424 <6>[ 2.319473] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10641 22:16:30.656422 <6>[ 2.328625] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10642 22:16:30.666388 <6>[ 2.337752] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10643 22:16:30.676395 <6>[ 2.347063] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10644 22:16:30.686419 <6>[ 2.356539] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10645 22:16:30.692681 <6>[ 2.366013] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10646 22:16:30.703002 <6>[ 2.375140] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10647 22:16:30.713111 <6>[ 2.384614] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10648 22:16:30.722579 <6>[ 2.393741] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10649 22:16:30.732582 <6>[ 2.403043] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10650 22:16:30.742650 <6>[ 2.413209] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10651 22:16:30.752487 <6>[ 2.424664] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10652 22:16:30.758879 <6>[ 2.434696] Trying to probe devices needed for running init ...
10653 22:16:30.773635 <6>[ 2.445985] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10654 22:16:30.802104 <6>[ 2.478001] hub 2-1:1.0: USB hub found
10655 22:16:30.805885 <6>[ 2.482468] hub 2-1:1.0: 3 ports detected
10656 22:16:30.924954 <6>[ 2.597799] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10657 22:16:31.078418 <6>[ 2.754022] hub 1-1:1.0: USB hub found
10658 22:16:31.081765 <6>[ 2.758378] hub 1-1:1.0: 4 ports detected
10659 22:16:31.157482 <6>[ 2.830078] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10660 22:16:31.401378 <6>[ 3.073825] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10661 22:16:31.534035 <6>[ 3.210157] hub 1-1.4:1.0: USB hub found
10662 22:16:31.537566 <6>[ 3.214848] hub 1-1.4:1.0: 2 ports detected
10663 22:16:31.837720 <6>[ 3.509825] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10664 22:16:32.029059 <6>[ 3.701827] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10665 22:16:43.050097 <6>[ 14.730381] ALSA device list:
10666 22:16:43.056084 <6>[ 14.733636] No soundcards found.
10667 22:16:43.068617 <6>[ 14.746035] Freeing unused kernel memory: 8384K
10668 22:16:43.072147 <6>[ 14.750970] Run /init as init process
10669 22:16:43.082252 Loading, please wait...
10670 22:16:43.100499 Starting version 247.3-7+deb11u2
10671 22:16:43.443719 <6>[ 15.118053] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10672 22:16:43.457388 <6>[ 15.131400] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10673 22:16:43.464079 <6>[ 15.131432] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10674 22:16:43.470281 <6>[ 15.136100] usbcore: registered new interface driver r8152
10675 22:16:43.476656 <4>[ 15.140947] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10676 22:16:43.486763 <6>[ 15.147766] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10677 22:16:43.493983 <3>[ 15.147884] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10678 22:16:43.501036 <3>[ 15.147899] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10679 22:16:43.510952 <3>[ 15.147908] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10680 22:16:43.517491 <4>[ 15.159509] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10681 22:16:43.524837 <4>[ 15.159509] Fallback method does not support PEC.
10682 22:16:43.531279 <6>[ 15.159891] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10683 22:16:43.538603 <4>[ 15.179000] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10684 22:16:43.548244 <3>[ 15.179913] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10685 22:16:43.555411 <3>[ 15.179941] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10686 22:16:43.564625 <3>[ 15.179950] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10687 22:16:43.571558 <3>[ 15.179973] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10688 22:16:43.582056 <3>[ 15.179986] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10689 22:16:43.588352 <3>[ 15.182019] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10690 22:16:43.598205 <3>[ 15.185452] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10691 22:16:43.601647 <6>[ 15.197351] remoteproc remoteproc0: scp is available
10692 22:16:43.611587 <3>[ 15.206573] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10693 22:16:43.617632 <3>[ 15.208485] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10694 22:16:43.628291 <4>[ 15.215337] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10695 22:16:43.634396 <6>[ 15.222234] mc: Linux media interface: v0.10
10696 22:16:43.640431 <3>[ 15.222484] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10697 22:16:43.647286 <6>[ 15.230577] remoteproc remoteproc0: powering up scp
10698 22:16:43.654287 <3>[ 15.238699] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10699 22:16:43.660818 <6>[ 15.239590] videodev: Linux video capture interface: v2.00
10700 22:16:43.670683 <4>[ 15.246842] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10701 22:16:43.677311 <3>[ 15.254935] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10702 22:16:43.683972 <3>[ 15.262923] remoteproc remoteproc0: request_firmware failed: -2
10703 22:16:43.693803 <3>[ 15.271002] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10704 22:16:43.700526 <6>[ 15.274251] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10705 22:16:43.710790 <4>[ 15.297412] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10706 22:16:43.717715 <3>[ 15.301846] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10707 22:16:43.727123 <6>[ 15.302052] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10708 22:16:43.736936 <6>[ 15.302471] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10709 22:16:43.744037 <6>[ 15.306921] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10710 22:16:43.750240 <6>[ 15.306928] pci_bus 0000:00: root bus resource [bus 00-ff]
10711 22:16:43.756817 <6>[ 15.306935] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10712 22:16:43.767022 <6>[ 15.306941] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10713 22:16:43.773651 <6>[ 15.306974] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10714 22:16:43.780420 <6>[ 15.306994] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10715 22:16:43.784101 <6>[ 15.307084] pci 0000:00:00.0: supports D1 D2
10716 22:16:43.790052 <6>[ 15.307087] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10717 22:16:43.800318 <6>[ 15.308444] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10718 22:16:43.810056 <6>[ 15.308747] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10719 22:16:43.816853 <6>[ 15.308896] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10720 22:16:43.823398 <6>[ 15.308929] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10721 22:16:43.830088 <6>[ 15.308950] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10722 22:16:43.836686 <6>[ 15.308969] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10723 22:16:43.843473 <6>[ 15.309091] pci 0000:01:00.0: supports D1 D2
10724 22:16:43.849940 <6>[ 15.309095] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10725 22:16:43.856718 <4>[ 15.312037] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10726 22:16:43.866684 <3>[ 15.316200] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10727 22:16:43.870030 <6>[ 15.316808] usbcore: registered new interface driver cdc_ether
10728 22:16:43.879698 <6>[ 15.324497] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10729 22:16:43.886695 <3>[ 15.329419] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10730 22:16:43.892961 <3>[ 15.329455] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10731 22:16:43.899590 <6>[ 15.329873] usbcore: registered new interface driver r8153_ecm
10732 22:16:43.909818 <6>[ 15.337966] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10733 22:16:43.912910 <6>[ 15.354322] Bluetooth: Core ver 2.22
10734 22:16:43.919839 <6>[ 15.361906] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10735 22:16:43.926326 <6>[ 15.367772] NET: Registered PF_BLUETOOTH protocol family
10736 22:16:43.932912 <6>[ 15.375762] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10737 22:16:43.939728 <6>[ 15.382917] Bluetooth: HCI device and connection manager initialized
10738 22:16:43.946236 <6>[ 15.382981] Bluetooth: HCI socket layer initialized
10739 22:16:43.949622 <6>[ 15.382996] Bluetooth: L2CAP socket layer initialized
10740 22:16:43.956372 <6>[ 15.383037] Bluetooth: SCO socket layer initialized
10741 22:16:43.962957 <6>[ 15.383057] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10742 22:16:43.969798 <6>[ 15.393359] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10743 22:16:43.979760 <6>[ 15.400390] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10744 22:16:43.989146 <6>[ 15.401922] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10745 22:16:43.995889 <6>[ 15.402073] usbcore: registered new interface driver uvcvideo
10746 22:16:44.002454 <6>[ 15.432657] usbcore: registered new interface driver btusb
10747 22:16:44.012610 <4>[ 15.433215] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10748 22:16:44.019209 <3>[ 15.433224] Bluetooth: hci0: Failed to load firmware file (-2)
10749 22:16:44.025583 <3>[ 15.433227] Bluetooth: hci0: Failed to set up firmware (-2)
10750 22:16:44.036198 <4>[ 15.433230] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10751 22:16:44.042293 <6>[ 15.439178] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10752 22:16:44.046062 <6>[ 15.453799] r8152 2-1.3:1.0 eth0: v1.12.13
10753 22:16:44.052587 <6>[ 15.455342] pci 0000:00:00.0: PCI bridge to [bus 01]
10754 22:16:44.058879 <6>[ 15.471501] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10755 22:16:44.065611 <6>[ 15.474183] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10756 22:16:44.072492 <6>[ 15.474370] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10757 22:16:44.079087 <6>[ 15.756079] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10758 22:16:44.085212 <6>[ 15.762876] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10759 22:16:44.109562 <5>[ 15.783752] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10760 22:16:44.127789 <5>[ 15.802033] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10761 22:16:44.134621 <4>[ 15.808919] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10762 22:16:44.141168 <6>[ 15.817802] cfg80211: failed to load regulatory.db
10763 22:16:44.184275 <6>[ 15.858078] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10764 22:16:44.190810 <6>[ 15.865619] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10765 22:16:44.214996 <6>[ 15.892332] mt7921e 0000:01:00.0: ASIC revision: 79610010
10766 22:16:44.322741 <4>[ 15.993343] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10767 22:16:44.326085 Begin: Loading essential drivers ... done.
10768 22:16:44.332411 Begin: Running /scripts/init-premount ... done.
10769 22:16:44.339270 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10770 22:16:44.345616 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10771 22:16:44.349136 Device /sys/class/net/enx00e04c787aaa found
10772 22:16:44.352034 done.
10773 22:16:44.419691 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10774 22:16:44.441061 <4>[ 16.112204] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10775 22:16:44.560353 <4>[ 16.231524] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10776 22:16:44.676675 <4>[ 16.347364] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10777 22:16:44.792626 <4>[ 16.463361] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10778 22:16:44.908349 <4>[ 16.579269] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10779 22:16:45.024093 <4>[ 16.695221] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10780 22:16:45.139977 <4>[ 16.811116] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10781 22:16:45.256892 <4>[ 16.927116] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10782 22:16:45.372978 <4>[ 17.043240] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10783 22:16:45.438499 <6>[ 17.116135] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
10784 22:16:45.479750 <3>[ 17.156931] mt7921e 0000:01:00.0: hardware init failed
10785 22:16:45.504306 IP-Config: no response after 2 secs - giving up
10786 22:16:45.551432 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10787 22:16:46.660783 IP-Config: enx00e04c787aaa complete (dhcp from 192.168.201.1):
10788 22:16:46.667453 address: 192.168.201.12 broadcast: 192.168.201.255 netmask: 255.255.255.0
10789 22:16:46.674605 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10790 22:16:46.680545 host : mt8192-asurada-spherion-r0-cbg-0
10791 22:16:46.687143 domain : lava-rack
10792 22:16:46.690573 rootserver: 192.168.201.1 rootpath:
10793 22:16:46.693704 filename :
10794 22:16:46.727684 done.
10795 22:16:46.734426 Begin: Running /scripts/nfs-bottom ... done.
10796 22:16:46.751971 Begin: Running /scripts/init-bottom ... done.
10797 22:16:47.855052 <6>[ 19.532744] NET: Registered PF_INET6 protocol family
10798 22:16:47.862137 <6>[ 19.539052] Segment Routing with IPv6
10799 22:16:47.864596 <6>[ 19.543054] In-situ OAM (IOAM) with IPv6
10800 22:16:47.981237 <30>[ 19.639050] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10801 22:16:47.984202 <30>[ 19.662812] systemd[1]: Detected architecture arm64.
10802 22:16:48.004087
10803 22:16:48.007558 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10804 22:16:48.008147
10805 22:16:48.021386 <30>[ 19.699526] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10806 22:16:48.606296 <30>[ 20.280736] systemd[1]: Queued start job for default target Graphical Interface.
10807 22:16:48.625154 <30>[ 20.302801] systemd[1]: Created slice system-getty.slice.
10808 22:16:48.632077 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10809 22:16:48.648529 <30>[ 20.326347] systemd[1]: Created slice system-modprobe.slice.
10810 22:16:48.654870 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10811 22:16:48.672371 <30>[ 20.350151] systemd[1]: Created slice system-serial\x2dgetty.slice.
10812 22:16:48.682390 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10813 22:16:48.697214 <30>[ 20.374892] systemd[1]: Created slice User and Session Slice.
10814 22:16:48.703688 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10815 22:16:48.723830 <30>[ 20.398338] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10816 22:16:48.733756 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10817 22:16:48.751808 <30>[ 20.426325] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10818 22:16:48.758217 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10819 22:16:48.778726 <30>[ 20.449763] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10820 22:16:48.785093 <30>[ 20.461766] systemd[1]: Reached target Local Encrypted Volumes.
10821 22:16:48.791455 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10822 22:16:48.807946 <30>[ 20.485728] systemd[1]: Reached target Paths.
10823 22:16:48.811107 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10824 22:16:48.827816 <30>[ 20.505672] systemd[1]: Reached target Remote File Systems.
10825 22:16:48.834586 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10826 22:16:48.847973 <30>[ 20.525663] systemd[1]: Reached target Slices.
10827 22:16:48.850942 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10828 22:16:48.867435 <30>[ 20.545681] systemd[1]: Reached target Swap.
10829 22:16:48.871127 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10830 22:16:48.891481 <30>[ 20.565913] systemd[1]: Listening on initctl Compatibility Named Pipe.
10831 22:16:48.898371 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10832 22:16:48.914165 <30>[ 20.591671] systemd[1]: Listening on Journal Audit Socket.
10833 22:16:48.920345 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10834 22:16:48.936839 <30>[ 20.614801] systemd[1]: Listening on Journal Socket (/dev/log).
10835 22:16:48.944001 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10836 22:16:48.960546 <30>[ 20.638645] systemd[1]: Listening on Journal Socket.
10837 22:16:48.967166 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10838 22:16:48.984600 <30>[ 20.658915] systemd[1]: Listening on Network Service Netlink Socket.
10839 22:16:48.991275 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10840 22:16:49.006301 <30>[ 20.684183] systemd[1]: Listening on udev Control Socket.
10841 22:16:49.012887 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10842 22:16:49.027770 <30>[ 20.705856] systemd[1]: Listening on udev Kernel Socket.
10843 22:16:49.034232 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10844 22:16:49.064332 <30>[ 20.741828] systemd[1]: Mounting Huge Pages File System...
10845 22:16:49.070482 Mounting [0;1;39mHuge Pages File System[0m...
10846 22:16:49.085832 <30>[ 20.763815] systemd[1]: Mounting POSIX Message Queue File System...
10847 22:16:49.092514 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10848 22:16:49.110140 <30>[ 20.788191] systemd[1]: Mounting Kernel Debug File System...
10849 22:16:49.116673 Mounting [0;1;39mKernel Debug File System[0m...
10850 22:16:49.135424 <30>[ 20.810193] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10851 22:16:49.191940 <30>[ 20.866494] systemd[1]: Starting Create list of static device nodes for the current kernel...
10852 22:16:49.198249 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10853 22:16:49.218228 <30>[ 20.896379] systemd[1]: Starting Load Kernel Module configfs...
10854 22:16:49.224729 Starting [0;1;39mLoad Kernel Module configfs[0m...
10855 22:16:49.242142 <30>[ 20.920188] systemd[1]: Starting Load Kernel Module drm...
10856 22:16:49.248460 Starting [0;1;39mLoad Kernel Module drm[0m...
10857 22:16:49.266386 <30>[ 20.944320] systemd[1]: Starting Load Kernel Module fuse...
10858 22:16:49.272857 Starting [0;1;39mLoad Kernel Module fuse[0m...
10859 22:16:49.304122 <6>[ 20.981902] fuse: init (API version 7.37)
10860 22:16:49.314202 <30>[ 20.982845] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10861 22:16:49.321928 <30>[ 21.000051] systemd[1]: Starting Journal Service...
10862 22:16:49.325410 Starting [0;1;39mJournal Service[0m...
10863 22:16:49.351999 <30>[ 21.029797] systemd[1]: Starting Load Kernel Modules...
10864 22:16:49.358393 Starting [0;1;39mLoad Kernel Modules[0m...
10865 22:16:49.377428 <30>[ 21.052319] systemd[1]: Starting Remount Root and Kernel File Systems...
10866 22:16:49.383831 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10867 22:16:49.399584 <30>[ 21.077349] systemd[1]: Starting Coldplug All udev Devices...
10868 22:16:49.405903 Starting [0;1;39mColdplug All udev Devices[0m...
10869 22:16:49.422705 <30>[ 21.100884] systemd[1]: Mounted Huge Pages File System.
10870 22:16:49.429361 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10871 22:16:49.444128 <30>[ 21.122191] systemd[1]: Mounted POSIX Message Queue File System.
10872 22:16:49.451020 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10873 22:16:49.472233 <30>[ 21.150225] systemd[1]: Mounted Kernel Debug File System.
10874 22:16:49.482150 <3>[ 21.150858] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10875 22:16:49.488911 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10876 22:16:49.508461 <30>[ 21.182741] systemd[1]: Finished Create list of static device nodes for the current kernel.
10877 22:16:49.518346 <3>[ 21.185934] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10878 22:16:49.524769 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10879 22:16:49.540564 <30>[ 21.218825] systemd[1]: modprobe@configfs.service: Succeeded.
10880 22:16:49.547578 <30>[ 21.225496] systemd[1]: Finished Load Kernel Module configfs.
10881 22:16:49.554070 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10882 22:16:49.567685 <3>[ 21.242178] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10883 22:16:49.574442 <30>[ 21.252406] systemd[1]: modprobe@drm.service: Succeeded.
10884 22:16:49.581371 <30>[ 21.258607] systemd[1]: Finished Load Kernel Module drm.
10885 22:16:49.588233 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10886 22:16:49.599306 <3>[ 21.273498] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10887 22:16:49.605717 <30>[ 21.283431] systemd[1]: modprobe@fuse.service: Succeeded.
10888 22:16:49.612390 <30>[ 21.289939] systemd[1]: Finished Load Kernel Module fuse.
10889 22:16:49.619237 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10890 22:16:49.629021 <3>[ 21.304025] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10891 22:16:49.636914 <30>[ 21.314906] systemd[1]: Finished Load Kernel Modules.
10892 22:16:49.643424 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10893 22:16:49.659745 <30>[ 21.334756] systemd[1]: Finished Remount Root and Kernel File Systems.
10894 22:16:49.666413 <3>[ 21.336352] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10895 22:16:49.676644 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10896 22:16:49.699547 <3>[ 21.373943] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10897 22:16:49.708574 <30>[ 21.386517] systemd[1]: Mounting FUSE Control File System...
10898 22:16:49.715109 Mounting [0;1;39mFUSE Control File System[0m...
10899 22:16:49.729783 <3>[ 21.404555] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10900 22:16:49.740955 <30>[ 21.416102] systemd[1]: Mounting Kernel Configuration File System...
10901 22:16:49.744548 Mounting [0;1;39mKernel Configuration File System[0m...
10902 22:16:49.759573 <3>[ 21.434400] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10903 22:16:49.774374 <30>[ 21.449212] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10904 22:16:49.785479 <30>[ 21.458195] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10905 22:16:49.791925 <3>[ 21.465211] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10906 22:16:49.798615 <30>[ 21.470177] systemd[1]: Starting Load/Save Random Seed...
10907 22:16:49.805054 Starting [0;1;39mLoad/Save Random Seed[0m...
10908 22:16:49.822195 <30>[ 21.500417] systemd[1]: Starting Apply Kernel Variables...
10909 22:16:49.828917 Starting [0;1;39mApply Kernel Variables[0m...
10910 22:16:49.846736 <30>[ 21.524961] systemd[1]: Starting Create System Users...
10911 22:16:49.853356 Starting [0;1;39mCreate System Users[0m...
10912 22:16:49.869043 <30>[ 21.547301] systemd[1]: Started Journal Service.
10913 22:16:49.875667 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10914 22:16:49.891652 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10915 22:16:49.908209 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10916 22:16:49.924206 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10917 22:16:49.940954 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10918 22:16:49.961651 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10919 22:16:50.000732 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10920 22:16:50.022865 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10921 22:16:50.060424 <46>[ 21.734887] systemd-journald[298]: Received client request to flush runtime journal.
10922 22:16:50.099741 <4>[ 21.768523] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10923 22:16:50.110132 <3>[ 21.784209] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10924 22:16:50.137785 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10925 22:16:50.151698 See 'systemctl status systemd-udev-trigger.service' for details.
10926 22:16:50.276935 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10927 22:16:50.295751 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10928 22:16:50.315166 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10929 22:16:50.375186 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10930 22:16:51.459448 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10931 22:16:51.491649 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10932 22:16:51.513270 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10933 22:16:51.541971 Starting [0;1;39mNetwork Service[0m...
10934 22:16:51.859939 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10935 22:16:51.886037 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10936 22:16:51.941900 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10937 22:16:52.102786 <6>[ 23.781586] remoteproc remoteproc0: powering up scp
10938 22:16:52.125998 <4>[ 23.801437] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10939 22:16:52.133126 <3>[ 23.811332] remoteproc remoteproc0: request_firmware failed: -2
10940 22:16:52.142532 <3>[ 23.817519] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10941 22:16:52.222697 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10942 22:16:52.243009 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10943 22:16:52.276095 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10944 22:16:52.295830 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10945 22:16:52.320072 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10946 22:16:52.344787 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10947 22:16:52.360100 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10948 22:16:52.407976 Starting [0;1;39mNetwork Name Resolution[0m...
10949 22:16:52.433129 Starting [0;1;39mNetwork Time Synchronization[0m...
10950 22:16:52.450468 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10951 22:16:52.494615 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10952 22:16:52.679880 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10953 22:16:52.696344 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10954 22:16:52.715004 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10955 22:16:52.727622 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10956 22:16:52.743559 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10957 22:16:52.845266 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10958 22:16:52.900838 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10959 22:16:52.925091 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10960 22:16:52.950643 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10961 22:16:52.967469 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10962 22:16:52.991485 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10963 22:16:53.004009 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10964 22:16:53.020043 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10965 22:16:53.055836 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10966 22:16:53.093629 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10967 22:16:53.144176 Starting [0;1;39mUser Login Management[0m...
10968 22:16:53.160698 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10969 22:16:53.179703 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10970 22:16:53.198310 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10971 22:16:53.260569 Starting [0;1;39mPermit User Sessions[0m...
10972 22:16:53.391468 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10973 22:16:53.428673 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10974 22:16:53.447612 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10975 22:16:53.463617 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10976 22:16:53.485000 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10977 22:16:53.501893 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10978 22:16:53.521373 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10979 22:16:53.536076 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10980 22:16:53.573350 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10981 22:16:53.616545 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10982 22:16:53.668847
10983 22:16:53.669397
10984 22:16:53.671980 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10985 22:16:53.672435
10986 22:16:53.675098 debian-bullseye-arm64 login: root (automatic login)
10987 22:16:53.675584
10988 22:16:53.676241
10989 22:16:53.977059 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Sun Jun 4 21:56:05 UTC 2023 aarch64
10990 22:16:53.977824
10991 22:16:53.983468 The programs included with the Debian GNU/Linux system are free software;
10992 22:16:53.990158 the exact distribution terms for each program are described in the
10993 22:16:53.993605 individual files in /usr/share/doc/*/copyright.
10994 22:16:53.994027
10995 22:16:54.000227 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10996 22:16:54.000669 permitted by applicable law.
10997 22:16:54.819239 Matched prompt #10: / #
10999 22:16:54.820431 Setting prompt string to ['/ #']
11000 22:16:54.820877 end: 2.2.5.1 login-action (duration 00:00:27) [common]
11002 22:16:54.821929 end: 2.2.5 auto-login-action (duration 00:00:27) [common]
11003 22:16:54.822392 start: 2.2.6 expect-shell-connection (timeout 00:03:36) [common]
11004 22:16:54.822756 Setting prompt string to ['/ #']
11005 22:16:54.823070 Forcing a shell prompt, looking for ['/ #']
11007 22:16:54.873815 / #
11008 22:16:54.874517 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11009 22:16:54.875006 Waiting using forced prompt support (timeout 00:02:30)
11010 22:16:54.879989
11011 22:16:54.880848 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11012 22:16:54.881374 start: 2.2.7 export-device-env (timeout 00:03:36) [common]
11014 22:16:54.982731 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10583894/extract-nfsrootfs-wh9mu87m'
11015 22:16:54.989859 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10583894/extract-nfsrootfs-wh9mu87m'
11017 22:16:55.091426 / # export NFS_SERVER_IP='192.168.201.1'
11018 22:16:55.098044 export NFS_SERVER_IP='192.168.201.1'
11019 22:16:55.099077 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11020 22:16:55.099707 end: 2.2 depthcharge-retry (duration 00:01:24) [common]
11021 22:16:55.100457 end: 2 depthcharge-action (duration 00:01:24) [common]
11022 22:16:55.101045 start: 3 lava-test-retry (timeout 00:07:56) [common]
11023 22:16:55.101690 start: 3.1 lava-test-shell (timeout 00:07:56) [common]
11024 22:16:55.102186 Using namespace: common
11026 22:16:55.203556 / # #
11027 22:16:55.204279 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11028 22:16:55.210182 #
11029 22:16:55.210980 Using /lava-10583894
11031 22:16:55.312359 / # export SHELL=/bin/bash
11032 22:16:55.318789 export SHELL=/bin/bash
11034 22:16:55.420412 / # . /lava-10583894/environment
11035 22:16:55.425809 . /lava-10583894/environment
11037 22:16:55.529986 / # /lava-10583894/bin/lava-test-runner /lava-10583894/0
11038 22:16:55.530773 Test shell timeout: 10s (minimum of the action and connection timeout)
11039 22:16:55.536644 /lava-10583894/bin/lava-test-runner /lava-10583894/0
11040 22:16:55.793459 + export TESTRUN_ID=0_timesync-off
11041 22:16:55.796739 + TESTRUN_ID=0_timesync-off
11042 22:16:55.800251 + cd /lava-10583894/0/tests/0_timesync-off
11043 22:16:55.803631 ++ cat uuid
11044 22:16:55.808854 + UUID=10583894_1.6.2.3.1
11045 22:16:55.809303 + set +x
11046 22:16:55.815095 <LAVA_SIGNAL_STARTRUN 0_timesync-off 10583894_1.6.2.3.1>
11047 22:16:55.815829 Received signal: <STARTRUN> 0_timesync-off 10583894_1.6.2.3.1
11048 22:16:55.816252 Starting test lava.0_timesync-off (10583894_1.6.2.3.1)
11049 22:16:55.816800 Skipping test definition patterns.
11050 22:16:55.818403 + systemctl stop systemd-timesyncd
11051 22:16:55.854773 + set +x
11052 22:16:55.858055 <LAVA_SIGNAL_ENDRUN 0_timesync-off 10583894_1.6.2.3.1>
11053 22:16:55.858778 Received signal: <ENDRUN> 0_timesync-off 10583894_1.6.2.3.1
11054 22:16:55.859251 Ending use of test pattern.
11055 22:16:55.859656 Ending test lava.0_timesync-off (10583894_1.6.2.3.1), duration 0.04
11057 22:16:55.920010 + export TESTRUN_ID=1_kselftest-tpm2
11058 22:16:55.923231 + TESTRUN_ID=1_kselftest-tpm2
11059 22:16:55.929901 + cd /lava-10583894/0/tests/1_kselftest-tpm2
11060 22:16:55.930357 ++ cat uuid
11061 22:16:55.933421 + UUID=10583894_1.6.2.3.5
11062 22:16:55.933944 + set +x
11063 22:16:55.940155 <LAVA_SIGNAL_STARTRUN 1_kselftest-tpm2 10583894_1.6.2.3.5>
11064 22:16:55.940888 Received signal: <STARTRUN> 1_kselftest-tpm2 10583894_1.6.2.3.5
11065 22:16:55.941308 Starting test lava.1_kselftest-tpm2 (10583894_1.6.2.3.5)
11066 22:16:55.941927 Skipping test definition patterns.
11067 22:16:55.943671 + cd ./automated/linux/kselftest/
11068 22:16:55.970330 + ./kselftest.sh -c tpm2 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1281-g84d5372e0f314/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11069 22:16:56.003712 INFO: install_deps skipped
11070 22:16:56.117661 --2023-06-04 22:16:56-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1281-g84d5372e0f314/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11071 22:16:56.144011 Resolving storage.kernelci.org (storage.kernelci.org)... 52.250.1.28
11072 22:16:56.286669 Connecting to storage.kernelci.org (storage.kernelci.org)|52.250.1.28|:80... connected.
11073 22:16:56.436422 HTTP request sent, awaiting response... 200 OK
11074 22:16:56.439241 Length: 2860264 (2.7M) [application/octet-stream]
11075 22:16:56.442586 Saving to: 'kselftest.tar.xz'
11076 22:16:56.443074
11077 22:16:56.443557
11078 22:16:56.721439 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11079 22:16:57.008008 kselftest.tar.xz 1%[ ] 47.81K 170KB/s
11080 22:16:57.483630 kselftest.tar.xz 7%[> ] 217.50K 385KB/s
11081 22:16:57.780277 kselftest.tar.xz 29%[====> ] 815.16K 787KB/s
11082 22:16:57.786295 kselftest.tar.xz 86%[================> ] 2.35M 1.77MB/s
11083 22:16:57.793037 kselftest.tar.xz 100%[===================>] 2.73M 2.05MB/s in 1.3s
11084 22:16:57.793671
11085 22:16:58.042851 2023-06-04 22:16:58 (2.05 MB/s) - 'kselftest.tar.xz' saved [2860264/2860264]
11086 22:16:58.043010
11087 22:17:02.892050 skiplist:
11088 22:17:02.895689 ========================================
11089 22:17:02.898887 ========================================
11090 22:17:02.949462 tpm2:test_smoke.sh
11091 22:17:02.952333 tpm2:test_space.sh
11092 22:17:02.967940 ============== Tests to run ===============
11093 22:17:02.968536 tpm2:test_smoke.sh
11094 22:17:02.971186 tpm2:test_space.sh
11095 22:17:02.974323 ===========End Tests to run ===============
11096 22:17:03.075903 <12>[ 34.755482] kselftest: Running tests in tpm2
11097 22:17:03.084944 TAP version 13
11098 22:17:03.097828 1..2
11099 22:17:03.127824 # selftests: tpm2: test_smoke.sh
11100 22:17:04.333666 # test_read_partial_overwrite (tpm2_tests.SmokeTest) ... ERROR
11101 22:17:04.336667 # test_read_partial_resp (tpm2_tests.SmokeTest) ... ERROR
11102 22:17:04.343520 # Exception ignored in: <function Client.__del__ at 0xffff899a3d30>
11103 22:17:04.347003 # Traceback (most recent call last):
11104 22:17:04.356998 # File "/lava-10583894/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11105 22:17:04.357798 # if self.tpm:
11106 22:17:04.363676 # AttributeError: 'Client' object has no attribute 'tpm'
11107 22:17:04.366827 # test_seal_with_auth (tpm2_tests.SmokeTest) ... ERROR
11108 22:17:04.373713 # Exception ignored in: <function Client.__del__ at 0xffff899a3d30>
11109 22:17:04.376470 # Traceback (most recent call last):
11110 22:17:04.386708 # File "/lava-10583894/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11111 22:17:04.390089 # if self.tpm:
11112 22:17:04.392905 # AttributeError: 'Client' object has no attribute 'tpm'
11113 22:17:04.399833 # test_seal_with_policy (tpm2_tests.SmokeTest) ... ERROR
11114 22:17:04.406430 # Exception ignored in: <function Client.__del__ at 0xffff899a3d30>
11115 22:17:04.409902 # Traceback (most recent call last):
11116 22:17:04.416499 # File "/lava-10583894/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11117 22:17:04.419850 # if self.tpm:
11118 22:17:04.426782 # AttributeError: 'Client' object has no attribute 'tpm'
11119 22:17:04.430016 # test_seal_with_too_long_auth (tpm2_tests.SmokeTest) ... ERROR
11120 22:17:04.436224 # Exception ignored in: <function Client.__del__ at 0xffff899a3d30>
11121 22:17:04.439877 # Traceback (most recent call last):
11122 22:17:04.449774 # File "/lava-10583894/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11123 22:17:04.450341 # if self.tpm:
11124 22:17:04.456473 # AttributeError: 'Client' object has no attribute 'tpm'
11125 22:17:04.459994 # test_send_two_cmds (tpm2_tests.SmokeTest) ... ERROR
11126 22:17:04.466926 # Exception ignored in: <function Client.__del__ at 0xffff899a3d30>
11127 22:17:04.470148 # Traceback (most recent call last):
11128 22:17:04.480084 # File "/lava-10583894/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11129 22:17:04.483595 # if self.tpm:
11130 22:17:04.486714 # AttributeError: 'Client' object has no attribute 'tpm'
11131 22:17:04.493706 # test_too_short_cmd (tpm2_tests.SmokeTest) ... ERROR
11132 22:17:04.496984 # Exception ignored in: <function Client.__del__ at 0xffff899a3d30>
11133 22:17:04.499884 # Traceback (most recent call last):
11134 22:17:04.510159 # File "/lava-10583894/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11135 22:17:04.513743 # if self.tpm:
11136 22:17:04.516810 # AttributeError: 'Client' object has no attribute 'tpm'
11137 22:17:04.523748 # test_unseal_with_wrong_auth (tpm2_tests.SmokeTest) ... ERROR
11138 22:17:04.530642 # Exception ignored in: <function Client.__del__ at 0xffff899a3d30>
11139 22:17:04.533497 # Traceback (most recent call last):
11140 22:17:04.544096 # File "/lava-10583894/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11141 22:17:04.544673 # if self.tpm:
11142 22:17:04.550925 # AttributeError: 'Client' object has no attribute 'tpm'
11143 22:17:04.553643 # test_unseal_with_wrong_policy (tpm2_tests.SmokeTest) ... ERROR
11144 22:17:04.560466 # Exception ignored in: <function Client.__del__ at 0xffff899a3d30>
11145 22:17:04.563980 # Traceback (most recent call last):
11146 22:17:04.573410 # File "/lava-10583894/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11147 22:17:04.576627 # if self.tpm:
11148 22:17:04.580272 # AttributeError: 'Client' object has no attribute 'tpm'
11149 22:17:04.580749 #
11150 22:17:04.586852 # ======================================================================
11151 22:17:04.593969 # ERROR: test_read_partial_overwrite (tpm2_tests.SmokeTest)
11152 22:17:04.600570 # ----------------------------------------------------------------------
11153 22:17:04.603810 # Traceback (most recent call last):
11154 22:17:04.613986 # File "/lava-10583894/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 16, in setUp
11155 22:17:04.616814 # self.root_key = self.client.create_root_key()
11156 22:17:04.626488 # File "/lava-10583894/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11157 22:17:04.636135 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11158 22:17:04.644211 # File "/lava-10583894/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11159 22:17:04.647865 # raise ProtocolError(cc, rc)
11160 22:17:04.654018 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11161 22:17:04.654507 #
11162 22:17:04.660535 # ======================================================================
11163 22:17:04.664435 # ERROR: test_read_partial_resp (tpm2_tests.SmokeTest)
11164 22:17:04.670910 # ----------------------------------------------------------------------
11165 22:17:04.674484 # Traceback (most recent call last):
11166 22:17:04.684142 # File "/lava-10583894/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11167 22:17:04.687641 # self.client = tpm2.Client()
11168 22:17:04.697884 # File "/lava-10583894/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11169 22:17:04.700757 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11170 22:17:04.707403 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11171 22:17:04.707874 #
11172 22:17:04.714159 # ======================================================================
11173 22:17:04.717498 # ERROR: test_seal_with_auth (tpm2_tests.SmokeTest)
11174 22:17:04.724298 # ----------------------------------------------------------------------
11175 22:17:04.727556 # Traceback (most recent call last):
11176 22:17:04.737604 # File "/lava-10583894/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11177 22:17:04.740512 # self.client = tpm2.Client()
11178 22:17:04.751616 # File "/lava-10583894/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11179 22:17:04.757768 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11180 22:17:04.760927 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11181 22:17:04.761424 #
11182 22:17:04.767626 # ======================================================================
11183 22:17:04.774125 # ERROR: test_seal_with_policy (tpm2_tests.SmokeTest)
11184 22:17:04.780533 # ----------------------------------------------------------------------
11185 22:17:04.784086 # Traceback (most recent call last):
11186 22:17:04.794143 # File "/lava-10583894/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11187 22:17:04.797392 # self.client = tpm2.Client()
11188 22:17:04.807185 # File "/lava-10583894/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11189 22:17:04.810742 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11190 22:17:04.817629 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11191 22:17:04.818259 #
11192 22:17:04.824008 # ======================================================================
11193 22:17:04.827699 # ERROR: test_seal_with_too_long_auth (tpm2_tests.SmokeTest)
11194 22:17:04.834099 # ----------------------------------------------------------------------
11195 22:17:04.837202 # Traceback (most recent call last):
11196 22:17:04.847715 # File "/lava-10583894/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11197 22:17:04.850660 # self.client = tpm2.Client()
11198 22:17:04.860571 # File "/lava-10583894/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11199 22:17:04.864040 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11200 22:17:04.870955 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11201 22:17:04.871525 #
11202 22:17:04.877246 # ======================================================================
11203 22:17:04.880717 # ERROR: test_send_two_cmds (tpm2_tests.SmokeTest)
11204 22:17:04.887832 # ----------------------------------------------------------------------
11205 22:17:04.890547 # Traceback (most recent call last):
11206 22:17:04.900883 # File "/lava-10583894/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11207 22:17:04.904212 # self.client = tpm2.Client()
11208 22:17:04.914675 # File "/lava-10583894/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11209 22:17:04.921437 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11210 22:17:04.924218 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11211 22:17:04.924847 #
11212 22:17:04.931196 # ======================================================================
11213 22:17:04.937507 # ERROR: test_too_short_cmd (tpm2_tests.SmokeTest)
11214 22:17:04.949099 # ----------------------------------------------------------------------
11215 22:17:04.949721 # Traceback (most recent call last):
11216 22:17:04.956002 # File "/lava-10583894/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11217 22:17:04.963852 # self.client = tpm2.Client()
11218 22:17:04.975307 # File "/lava-10583894/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11219 22:17:04.975876 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11220 22:17:04.978800 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11221 22:17:04.979270 #
11222 22:17:04.987445 # ======================================================================
11223 22:17:04.991506 # ERROR: test_unseal_with_wrong_auth (tpm2_tests.SmokeTest)
11224 22:17:04.998274 # ----------------------------------------------------------------------
11225 22:17:05.001976 # Traceback (most recent call last):
11226 22:17:05.011672 # File "/lava-10583894/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11227 22:17:05.015438 # self.client = tpm2.Client()
11228 22:17:05.024894 # File "/lava-10583894/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11229 22:17:05.028484 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11230 22:17:05.034782 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11231 22:17:05.035254 #
11232 22:17:05.041322 # ======================================================================
11233 22:17:05.044722 # ERROR: test_unseal_with_wrong_policy (tpm2_tests.SmokeTest)
11234 22:17:05.051909 # ----------------------------------------------------------------------
11235 22:17:05.054508 # Traceback (most recent call last):
11236 22:17:05.065272 # File "/lava-10583894/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11237 22:17:05.068057 # self.client = tpm2.Client()
11238 22:17:05.077895 # File "/lava-10583894/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11239 22:17:05.084784 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11240 22:17:05.088238 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11241 22:17:05.088709 #
11242 22:17:05.094337 # ----------------------------------------------------------------------
11243 22:17:05.098392 # Ran 9 tests in 0.029s
11244 22:17:05.098972 #
11245 22:17:05.101198 # FAILED (errors=9)
11246 22:17:05.104577 # test_async (tpm2_tests.AsyncTest) ... ok
11247 22:17:05.108354 # test_flush_invalid_context (tpm2_tests.AsyncTest) ... ok
11248 22:17:05.108928 #
11249 22:17:05.115040 # ----------------------------------------------------------------------
11250 22:17:05.118152 # Ran 2 tests in 0.033s
11251 22:17:05.118724 #
11252 22:17:05.119094 # OK
11253 22:17:05.121292 ok 1 selftests: tpm2: test_smoke.sh
11254 22:17:05.124714 # selftests: tpm2: test_space.sh
11255 22:17:05.131410 # test_flush_context (tpm2_tests.SpaceTest) ... ERROR
11256 22:17:05.134629 # test_get_handles (tpm2_tests.SpaceTest) ... ERROR
11257 22:17:05.138061 # test_invalid_cc (tpm2_tests.SpaceTest) ... ERROR
11258 22:17:05.144645 # test_make_two_spaces (tpm2_tests.SpaceTest) ... ERROR
11259 22:17:05.145218 #
11260 22:17:05.151564 # ======================================================================
11261 22:17:05.154446 # ERROR: test_flush_context (tpm2_tests.SpaceTest)
11262 22:17:05.161043 # ----------------------------------------------------------------------
11263 22:17:05.164643 # Traceback (most recent call last):
11264 22:17:05.177993 # File "/lava-10583894/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 261, in test_flush_context
11265 22:17:05.181652 # root1 = space1.create_root_key()
11266 22:17:05.191205 # File "/lava-10583894/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11267 22:17:05.194534 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11268 22:17:05.204437 # File "/lava-10583894/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11269 22:17:05.208088 # raise ProtocolError(cc, rc)
11270 22:17:05.214965 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11271 22:17:05.215551 #
11272 22:17:05.221119 # ======================================================================
11273 22:17:05.224605 # ERROR: test_get_handles (tpm2_tests.SpaceTest)
11274 22:17:05.231130 # ----------------------------------------------------------------------
11275 22:17:05.234412 # Traceback (most recent call last):
11276 22:17:05.248395 # File "/lava-10583894/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 271, in test_get_handles
11277 22:17:05.248979 # space1.create_root_key()
11278 22:17:05.261324 # File "/lava-10583894/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11279 22:17:05.264740 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11280 22:17:05.274741 # File "/lava-10583894/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11281 22:17:05.277916 # raise ProtocolError(cc, rc)
11282 22:17:05.284421 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11283 22:17:05.284991 #
11284 22:17:05.291108 # ======================================================================
11285 22:17:05.294178 # ERROR: test_invalid_cc (tpm2_tests.SpaceTest)
11286 22:17:05.301175 # ----------------------------------------------------------------------
11287 22:17:05.304835 # Traceback (most recent call last):
11288 22:17:05.317388 # File "/lava-10583894/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 290, in test_invalid_cc
11289 22:17:05.320634 # root1 = space1.create_root_key()
11290 22:17:05.331075 # File "/lava-10583894/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11291 22:17:05.334072 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11292 22:17:05.344704 # File "/lava-10583894/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11293 22:17:05.347999 # raise ProtocolError(cc, rc)
11294 22:17:05.354475 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11295 22:17:05.354948 #
11296 22:17:05.360745 # ======================================================================
11297 22:17:05.364096 # ERROR: test_make_two_spaces (tpm2_tests.SpaceTest)
11298 22:17:05.370873 # ----------------------------------------------------------------------
11299 22:17:05.374515 # Traceback (most recent call last):
11300 22:17:05.387995 # File "/lava-10583894/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 247, in test_make_two_spaces
11301 22:17:05.391101 # root1 = space1.create_root_key()
11302 22:17:05.401291 # File "/lava-10583894/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11303 22:17:05.407971 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11304 22:17:05.417597 # File "/lava-10583894/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11305 22:17:05.421050 # raise ProtocolError(cc, rc)
11306 22:17:05.424512 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11307 22:17:05.424984 #
11308 22:17:05.431233 # ----------------------------------------------------------------------
11309 22:17:05.434849 # Ran 4 tests in 0.055s
11310 22:17:05.435313 #
11311 22:17:05.438141 # FAILED (errors=4)
11312 22:17:05.441348 not ok 2 selftests: tpm2: test_space.sh # exit=1
11313 22:17:05.468534 tpm2_test_smoke_sh pass
11314 22:17:05.471475 tpm2_test_space_sh fail
11315 22:17:05.487297 + ../../utils/send-to-lava.sh ./output/result.txt
11316 22:17:05.556034 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass>
11317 22:17:05.556795 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass
11319 22:17:05.616815 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_space_sh RESULT=fail>
11320 22:17:05.617503 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_space_sh RESULT=fail
11322 22:17:05.619933 + set +x
11323 22:17:05.623620 <LAVA_SIGNAL_ENDRUN 1_kselftest-tpm2 10583894_1.6.2.3.5>
11324 22:17:05.624292 Received signal: <ENDRUN> 1_kselftest-tpm2 10583894_1.6.2.3.5
11325 22:17:05.624660 Ending use of test pattern.
11326 22:17:05.624985 Ending test lava.1_kselftest-tpm2 (10583894_1.6.2.3.5), duration 9.68
11328 22:17:05.626731 <LAVA_TEST_RUNNER EXIT>
11329 22:17:05.627395 ok: lava_test_shell seems to have completed
11330 22:17:05.627919 tpm2_test_smoke_sh: pass
tpm2_test_space_sh: fail
11331 22:17:05.628335 end: 3.1 lava-test-shell (duration 00:00:11) [common]
11332 22:17:05.628753 end: 3 lava-test-retry (duration 00:00:11) [common]
11333 22:17:05.629190 start: 4 finalize (timeout 00:07:45) [common]
11334 22:17:05.629691 start: 4.1 power-off (timeout 00:00:30) [common]
11335 22:17:05.630444 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11336 22:17:05.751061 >> Command sent successfully.
11337 22:17:05.762234 Returned 0 in 0 seconds
11338 22:17:05.863550 end: 4.1 power-off (duration 00:00:00) [common]
11340 22:17:05.865198 start: 4.2 read-feedback (timeout 00:07:45) [common]
11341 22:17:05.866555 Listened to connection for namespace 'common' for up to 1s
11342 22:17:06.867151 Finalising connection for namespace 'common'
11343 22:17:06.867835 Disconnecting from shell: Finalise
11344 22:17:06.868261 / #
11345 22:17:06.969262 end: 4.2 read-feedback (duration 00:00:01) [common]
11346 22:17:06.970003 end: 4 finalize (duration 00:00:01) [common]
11347 22:17:06.970631 Cleaning after the job
11348 22:17:06.971160 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583894/tftp-deploy-tapz7bnq/ramdisk
11349 22:17:06.981800 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583894/tftp-deploy-tapz7bnq/kernel
11350 22:17:07.012984 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583894/tftp-deploy-tapz7bnq/dtb
11351 22:17:07.013360 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583894/tftp-deploy-tapz7bnq/nfsrootfs
11352 22:17:07.086932 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10583894/tftp-deploy-tapz7bnq/modules
11353 22:17:07.092289 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10583894
11354 22:17:07.622343 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10583894
11355 22:17:07.622529 Job finished correctly