Boot log: mt8192-asurada-spherion-r0
- Errors: 2
- Kernel Errors: 26
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 22
1 11:11:59.625730 lava-dispatcher, installed at version: 2023.05.1
2 11:11:59.625948 start: 0 validate
3 11:11:59.626083 Start time: 2023-06-05 11:11:59.626070+00:00 (UTC)
4 11:11:59.626215 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:11:59.626345 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 11:11:59.923096 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:11:59.923817 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:12:24.237769 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:12:24.238478 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:12:24.533668 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:12:24.534437 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 11:12:27.832827 validate duration: 28.21
14 11:12:27.833082 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 11:12:27.833179 start: 1.1 download-retry (timeout 00:10:00) [common]
16 11:12:27.833270 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 11:12:27.833397 Not decompressing ramdisk as can be used compressed.
18 11:12:27.833482 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20230527.0/arm64/rootfs.cpio.gz
19 11:12:27.833546 saving as /var/lib/lava/dispatcher/tmp/10591271/tftp-deploy-9g1e0xbk/ramdisk/rootfs.cpio.gz
20 11:12:27.833606 total size: 8186575 (7MB)
21 11:12:28.123710 progress 0% (0MB)
22 11:12:28.125984 progress 5% (0MB)
23 11:12:28.128009 progress 10% (0MB)
24 11:12:28.130210 progress 15% (1MB)
25 11:12:28.132229 progress 20% (1MB)
26 11:12:28.134407 progress 25% (1MB)
27 11:12:28.136416 progress 30% (2MB)
28 11:12:28.138581 progress 35% (2MB)
29 11:12:28.140628 progress 40% (3MB)
30 11:12:28.142798 progress 45% (3MB)
31 11:12:28.144862 progress 50% (3MB)
32 11:12:28.147060 progress 55% (4MB)
33 11:12:28.149061 progress 60% (4MB)
34 11:12:28.151199 progress 65% (5MB)
35 11:12:28.153174 progress 70% (5MB)
36 11:12:28.155300 progress 75% (5MB)
37 11:12:28.157287 progress 80% (6MB)
38 11:12:28.159466 progress 85% (6MB)
39 11:12:28.161499 progress 90% (7MB)
40 11:12:28.163623 progress 95% (7MB)
41 11:12:28.165665 progress 100% (7MB)
42 11:12:28.165880 7MB downloaded in 0.33s (23.50MB/s)
43 11:12:28.166028 end: 1.1.1 http-download (duration 00:00:00) [common]
45 11:12:28.166266 end: 1.1 download-retry (duration 00:00:00) [common]
46 11:12:28.166352 start: 1.2 download-retry (timeout 00:10:00) [common]
47 11:12:28.166436 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 11:12:28.166569 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 11:12:28.166639 saving as /var/lib/lava/dispatcher/tmp/10591271/tftp-deploy-9g1e0xbk/kernel/Image
50 11:12:28.166700 total size: 45746688 (43MB)
51 11:12:28.166760 No compression specified
52 11:12:28.167845 progress 0% (0MB)
53 11:12:28.179212 progress 5% (2MB)
54 11:12:28.190707 progress 10% (4MB)
55 11:12:28.202187 progress 15% (6MB)
56 11:12:28.213681 progress 20% (8MB)
57 11:12:28.225331 progress 25% (10MB)
58 11:12:28.236744 progress 30% (13MB)
59 11:12:28.248350 progress 35% (15MB)
60 11:12:28.259926 progress 40% (17MB)
61 11:12:28.271468 progress 45% (19MB)
62 11:12:28.283020 progress 50% (21MB)
63 11:12:28.294371 progress 55% (24MB)
64 11:12:28.305864 progress 60% (26MB)
65 11:12:28.317462 progress 65% (28MB)
66 11:12:28.329392 progress 70% (30MB)
67 11:12:28.341113 progress 75% (32MB)
68 11:12:28.352600 progress 80% (34MB)
69 11:12:28.364398 progress 85% (37MB)
70 11:12:28.375932 progress 90% (39MB)
71 11:12:28.387334 progress 95% (41MB)
72 11:12:28.398771 progress 100% (43MB)
73 11:12:28.398927 43MB downloaded in 0.23s (187.87MB/s)
74 11:12:28.399081 end: 1.2.1 http-download (duration 00:00:00) [common]
76 11:12:28.399314 end: 1.2 download-retry (duration 00:00:00) [common]
77 11:12:28.399405 start: 1.3 download-retry (timeout 00:09:59) [common]
78 11:12:28.399493 start: 1.3.1 http-download (timeout 00:09:59) [common]
79 11:12:28.399631 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 11:12:28.399700 saving as /var/lib/lava/dispatcher/tmp/10591271/tftp-deploy-9g1e0xbk/dtb/mt8192-asurada-spherion-r0.dtb
81 11:12:28.399761 total size: 46924 (0MB)
82 11:12:28.399821 No compression specified
83 11:12:28.401036 progress 69% (0MB)
84 11:12:28.401320 progress 100% (0MB)
85 11:12:28.401477 0MB downloaded in 0.00s (26.11MB/s)
86 11:12:28.401597 end: 1.3.1 http-download (duration 00:00:00) [common]
88 11:12:28.401827 end: 1.3 download-retry (duration 00:00:00) [common]
89 11:12:28.401913 start: 1.4 download-retry (timeout 00:09:59) [common]
90 11:12:28.401995 start: 1.4.1 http-download (timeout 00:09:59) [common]
91 11:12:28.402109 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 11:12:28.402177 saving as /var/lib/lava/dispatcher/tmp/10591271/tftp-deploy-9g1e0xbk/modules/modules.tar
93 11:12:28.402237 total size: 8547328 (8MB)
94 11:12:28.402304 Using unxz to decompress xz
95 11:12:28.405973 progress 0% (0MB)
96 11:12:28.428319 progress 5% (0MB)
97 11:12:28.453551 progress 10% (0MB)
98 11:12:28.480256 progress 15% (1MB)
99 11:12:28.504499 progress 20% (1MB)
100 11:12:28.530345 progress 25% (2MB)
101 11:12:28.555903 progress 30% (2MB)
102 11:12:28.582261 progress 35% (2MB)
103 11:12:28.607934 progress 40% (3MB)
104 11:12:28.633980 progress 45% (3MB)
105 11:12:28.658484 progress 50% (4MB)
106 11:12:28.681799 progress 55% (4MB)
107 11:12:28.707194 progress 60% (4MB)
108 11:12:28.732544 progress 65% (5MB)
109 11:12:28.757957 progress 70% (5MB)
110 11:12:28.784917 progress 75% (6MB)
111 11:12:28.814180 progress 80% (6MB)
112 11:12:28.836662 progress 85% (6MB)
113 11:12:28.863463 progress 90% (7MB)
114 11:12:28.886883 progress 95% (7MB)
115 11:12:28.910285 progress 100% (8MB)
116 11:12:28.916174 8MB downloaded in 0.51s (15.86MB/s)
117 11:12:28.916532 end: 1.4.1 http-download (duration 00:00:01) [common]
119 11:12:28.916922 end: 1.4 download-retry (duration 00:00:01) [common]
120 11:12:28.917062 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 11:12:28.917195 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 11:12:28.917321 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 11:12:28.917450 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 11:12:28.917750 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10591271/lava-overlay-laobq7rw
125 11:12:28.917943 makedir: /var/lib/lava/dispatcher/tmp/10591271/lava-overlay-laobq7rw/lava-10591271/bin
126 11:12:28.918100 makedir: /var/lib/lava/dispatcher/tmp/10591271/lava-overlay-laobq7rw/lava-10591271/tests
127 11:12:28.918240 makedir: /var/lib/lava/dispatcher/tmp/10591271/lava-overlay-laobq7rw/lava-10591271/results
128 11:12:28.918408 Creating /var/lib/lava/dispatcher/tmp/10591271/lava-overlay-laobq7rw/lava-10591271/bin/lava-add-keys
129 11:12:28.918599 Creating /var/lib/lava/dispatcher/tmp/10591271/lava-overlay-laobq7rw/lava-10591271/bin/lava-add-sources
130 11:12:28.918773 Creating /var/lib/lava/dispatcher/tmp/10591271/lava-overlay-laobq7rw/lava-10591271/bin/lava-background-process-start
131 11:12:28.918953 Creating /var/lib/lava/dispatcher/tmp/10591271/lava-overlay-laobq7rw/lava-10591271/bin/lava-background-process-stop
132 11:12:28.919134 Creating /var/lib/lava/dispatcher/tmp/10591271/lava-overlay-laobq7rw/lava-10591271/bin/lava-common-functions
133 11:12:28.919298 Creating /var/lib/lava/dispatcher/tmp/10591271/lava-overlay-laobq7rw/lava-10591271/bin/lava-echo-ipv4
134 11:12:28.919473 Creating /var/lib/lava/dispatcher/tmp/10591271/lava-overlay-laobq7rw/lava-10591271/bin/lava-install-packages
135 11:12:28.919641 Creating /var/lib/lava/dispatcher/tmp/10591271/lava-overlay-laobq7rw/lava-10591271/bin/lava-installed-packages
136 11:12:28.919813 Creating /var/lib/lava/dispatcher/tmp/10591271/lava-overlay-laobq7rw/lava-10591271/bin/lava-os-build
137 11:12:28.919981 Creating /var/lib/lava/dispatcher/tmp/10591271/lava-overlay-laobq7rw/lava-10591271/bin/lava-probe-channel
138 11:12:28.920191 Creating /var/lib/lava/dispatcher/tmp/10591271/lava-overlay-laobq7rw/lava-10591271/bin/lava-probe-ip
139 11:12:28.920369 Creating /var/lib/lava/dispatcher/tmp/10591271/lava-overlay-laobq7rw/lava-10591271/bin/lava-target-ip
140 11:12:28.920541 Creating /var/lib/lava/dispatcher/tmp/10591271/lava-overlay-laobq7rw/lava-10591271/bin/lava-target-mac
141 11:12:28.920711 Creating /var/lib/lava/dispatcher/tmp/10591271/lava-overlay-laobq7rw/lava-10591271/bin/lava-target-storage
142 11:12:28.920889 Creating /var/lib/lava/dispatcher/tmp/10591271/lava-overlay-laobq7rw/lava-10591271/bin/lava-test-case
143 11:12:28.921067 Creating /var/lib/lava/dispatcher/tmp/10591271/lava-overlay-laobq7rw/lava-10591271/bin/lava-test-event
144 11:12:28.921236 Creating /var/lib/lava/dispatcher/tmp/10591271/lava-overlay-laobq7rw/lava-10591271/bin/lava-test-feedback
145 11:12:28.921405 Creating /var/lib/lava/dispatcher/tmp/10591271/lava-overlay-laobq7rw/lava-10591271/bin/lava-test-raise
146 11:12:28.921580 Creating /var/lib/lava/dispatcher/tmp/10591271/lava-overlay-laobq7rw/lava-10591271/bin/lava-test-reference
147 11:12:28.921754 Creating /var/lib/lava/dispatcher/tmp/10591271/lava-overlay-laobq7rw/lava-10591271/bin/lava-test-runner
148 11:12:28.921922 Creating /var/lib/lava/dispatcher/tmp/10591271/lava-overlay-laobq7rw/lava-10591271/bin/lava-test-set
149 11:12:28.922089 Creating /var/lib/lava/dispatcher/tmp/10591271/lava-overlay-laobq7rw/lava-10591271/bin/lava-test-shell
150 11:12:28.922270 Updating /var/lib/lava/dispatcher/tmp/10591271/lava-overlay-laobq7rw/lava-10591271/bin/lava-install-packages (oe)
151 11:12:28.922520 Updating /var/lib/lava/dispatcher/tmp/10591271/lava-overlay-laobq7rw/lava-10591271/bin/lava-installed-packages (oe)
152 11:12:28.922685 Creating /var/lib/lava/dispatcher/tmp/10591271/lava-overlay-laobq7rw/lava-10591271/environment
153 11:12:28.922832 LAVA metadata
154 11:12:28.922937 - LAVA_JOB_ID=10591271
155 11:12:28.923039 - LAVA_DISPATCHER_IP=192.168.201.1
156 11:12:28.923187 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 11:12:28.923295 skipped lava-vland-overlay
158 11:12:28.923406 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 11:12:28.923534 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 11:12:28.923627 skipped lava-multinode-overlay
161 11:12:28.923748 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 11:12:28.923871 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 11:12:28.923992 Loading test definitions
164 11:12:28.924167 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 11:12:28.924283 Using /lava-10591271 at stage 0
166 11:12:28.924734 uuid=10591271_1.5.2.3.1 testdef=None
167 11:12:28.924859 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 11:12:28.924976 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 11:12:28.925732 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 11:12:28.926074 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 11:12:28.927000 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 11:12:28.927348 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 11:12:28.928284 runner path: /var/lib/lava/dispatcher/tmp/10591271/lava-overlay-laobq7rw/lava-10591271/0/tests/0_dmesg test_uuid 10591271_1.5.2.3.1
176 11:12:28.928487 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 11:12:28.928831 start: 1.5.2.3.5 inline-repo-action (timeout 00:09:59) [common]
179 11:12:28.928942 Using /lava-10591271 at stage 1
180 11:12:28.929375 uuid=10591271_1.5.2.3.5 testdef=None
181 11:12:28.929497 end: 1.5.2.3.5 inline-repo-action (duration 00:00:00) [common]
182 11:12:28.929618 start: 1.5.2.3.6 test-overlay (timeout 00:09:59) [common]
183 11:12:28.930296 end: 1.5.2.3.6 test-overlay (duration 00:00:00) [common]
185 11:12:28.930628 start: 1.5.2.3.7 test-install-overlay (timeout 00:09:59) [common]
186 11:12:28.932167 end: 1.5.2.3.7 test-install-overlay (duration 00:00:00) [common]
188 11:12:28.932517 start: 1.5.2.3.8 test-runscript-overlay (timeout 00:09:59) [common]
189 11:12:28.933410 runner path: /var/lib/lava/dispatcher/tmp/10591271/lava-overlay-laobq7rw/lava-10591271/1/tests/1_bootrr test_uuid 10591271_1.5.2.3.5
190 11:12:28.933610 end: 1.5.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
192 11:12:28.933931 Creating lava-test-runner.conf files
193 11:12:28.934033 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10591271/lava-overlay-laobq7rw/lava-10591271/0 for stage 0
194 11:12:28.934161 - 0_dmesg
195 11:12:28.934271 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10591271/lava-overlay-laobq7rw/lava-10591271/1 for stage 1
196 11:12:28.934405 - 1_bootrr
197 11:12:28.934541 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
198 11:12:28.934673 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
199 11:12:28.945711 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
200 11:12:28.945853 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
201 11:12:28.945977 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
202 11:12:28.946097 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
203 11:12:28.946223 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
204 11:12:29.185373 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
205 11:12:29.185788 start: 1.5.4 extract-modules (timeout 00:09:59) [common]
206 11:12:29.185909 extracting modules file /var/lib/lava/dispatcher/tmp/10591271/tftp-deploy-9g1e0xbk/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10591271/extract-overlay-ramdisk-c9m4cr06/ramdisk
207 11:12:29.407830 end: 1.5.4 extract-modules (duration 00:00:00) [common]
208 11:12:29.407994 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
209 11:12:29.408139 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10591271/compress-overlay-1k_jwyxa/overlay-1.5.2.4.tar.gz to ramdisk
210 11:12:29.408214 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10591271/compress-overlay-1k_jwyxa/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10591271/extract-overlay-ramdisk-c9m4cr06/ramdisk
211 11:12:29.416520 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
212 11:12:29.416660 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
213 11:12:29.416755 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
214 11:12:29.416842 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
215 11:12:29.416924 Building ramdisk /var/lib/lava/dispatcher/tmp/10591271/extract-overlay-ramdisk-c9m4cr06/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10591271/extract-overlay-ramdisk-c9m4cr06/ramdisk
216 11:12:29.756472 >> 143713 blocks
217 11:12:32.019284 rename /var/lib/lava/dispatcher/tmp/10591271/extract-overlay-ramdisk-c9m4cr06/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10591271/tftp-deploy-9g1e0xbk/ramdisk/ramdisk.cpio.gz
218 11:12:32.019713 end: 1.5.7 compress-ramdisk (duration 00:00:03) [common]
219 11:12:32.019836 start: 1.5.8 prepare-kernel (timeout 00:09:56) [common]
220 11:12:32.019932 start: 1.5.8.1 prepare-fit (timeout 00:09:56) [common]
221 11:12:32.020064 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10591271/tftp-deploy-9g1e0xbk/kernel/Image'
222 11:12:44.507340 Returned 0 in 12 seconds
223 11:12:44.607966 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10591271/tftp-deploy-9g1e0xbk/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10591271/tftp-deploy-9g1e0xbk/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10591271/tftp-deploy-9g1e0xbk/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10591271/tftp-deploy-9g1e0xbk/kernel/image.itb
224 11:12:44.964065 output: FIT description: Kernel Image image with one or more FDT blobs
225 11:12:44.964406 output: Created: Mon Jun 5 12:12:44 2023
226 11:12:44.964482 output: Image 0 (kernel-1)
227 11:12:44.964547 output: Description:
228 11:12:44.964609 output: Created: Mon Jun 5 12:12:44 2023
229 11:12:44.964670 output: Type: Kernel Image
230 11:12:44.964731 output: Compression: lzma compressed
231 11:12:44.964785 output: Data Size: 10086024 Bytes = 9849.63 KiB = 9.62 MiB
232 11:12:44.964845 output: Architecture: AArch64
233 11:12:44.964902 output: OS: Linux
234 11:12:44.964959 output: Load Address: 0x00000000
235 11:12:44.965014 output: Entry Point: 0x00000000
236 11:12:44.965071 output: Hash algo: crc32
237 11:12:44.965126 output: Hash value: eb1cf9b8
238 11:12:44.965179 output: Image 1 (fdt-1)
239 11:12:44.965231 output: Description: mt8192-asurada-spherion-r0
240 11:12:44.965284 output: Created: Mon Jun 5 12:12:44 2023
241 11:12:44.965337 output: Type: Flat Device Tree
242 11:12:44.965390 output: Compression: uncompressed
243 11:12:44.965442 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
244 11:12:44.965495 output: Architecture: AArch64
245 11:12:44.965547 output: Hash algo: crc32
246 11:12:44.965599 output: Hash value: 1df858fa
247 11:12:44.965651 output: Image 2 (ramdisk-1)
248 11:12:44.965703 output: Description: unavailable
249 11:12:44.965755 output: Created: Mon Jun 5 12:12:44 2023
250 11:12:44.965807 output: Type: RAMDisk Image
251 11:12:44.965859 output: Compression: Unknown Compression
252 11:12:44.965912 output: Data Size: 21232676 Bytes = 20735.04 KiB = 20.25 MiB
253 11:12:44.965964 output: Architecture: AArch64
254 11:12:44.966015 output: OS: Linux
255 11:12:44.966067 output: Load Address: unavailable
256 11:12:44.966119 output: Entry Point: unavailable
257 11:12:44.966171 output: Hash algo: crc32
258 11:12:44.966222 output: Hash value: a2dde859
259 11:12:44.966274 output: Default Configuration: 'conf-1'
260 11:12:44.966326 output: Configuration 0 (conf-1)
261 11:12:44.966378 output: Description: mt8192-asurada-spherion-r0
262 11:12:44.966431 output: Kernel: kernel-1
263 11:12:44.966482 output: Init Ramdisk: ramdisk-1
264 11:12:44.966534 output: FDT: fdt-1
265 11:12:44.966586 output: Loadables: kernel-1
266 11:12:44.966638 output:
267 11:12:44.966835 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
268 11:12:44.966931 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
269 11:12:44.967033 end: 1.5 prepare-tftp-overlay (duration 00:00:16) [common]
270 11:12:44.967124 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:43) [common]
271 11:12:44.967201 No LXC device requested
272 11:12:44.967280 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
273 11:12:44.967367 start: 1.7 deploy-device-env (timeout 00:09:43) [common]
274 11:12:44.967443 end: 1.7 deploy-device-env (duration 00:00:00) [common]
275 11:12:44.967514 Checking files for TFTP limit of 4294967296 bytes.
276 11:12:44.967995 end: 1 tftp-deploy (duration 00:00:17) [common]
277 11:12:44.968140 start: 2 depthcharge-action (timeout 00:05:00) [common]
278 11:12:44.968231 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
279 11:12:44.968356 substitutions:
280 11:12:44.968423 - {DTB}: 10591271/tftp-deploy-9g1e0xbk/dtb/mt8192-asurada-spherion-r0.dtb
281 11:12:44.968486 - {INITRD}: 10591271/tftp-deploy-9g1e0xbk/ramdisk/ramdisk.cpio.gz
282 11:12:44.968544 - {KERNEL}: 10591271/tftp-deploy-9g1e0xbk/kernel/Image
283 11:12:44.968601 - {LAVA_MAC}: None
284 11:12:44.968657 - {PRESEED_CONFIG}: None
285 11:12:44.968711 - {PRESEED_LOCAL}: None
286 11:12:44.968766 - {RAMDISK}: 10591271/tftp-deploy-9g1e0xbk/ramdisk/ramdisk.cpio.gz
287 11:12:44.968820 - {ROOT_PART}: None
288 11:12:44.968874 - {ROOT}: None
289 11:12:44.968927 - {SERVER_IP}: 192.168.201.1
290 11:12:44.968981 - {TEE}: None
291 11:12:44.969034 Parsed boot commands:
292 11:12:44.969087 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
293 11:12:44.969251 Parsed boot commands: tftpboot 192.168.201.1 10591271/tftp-deploy-9g1e0xbk/kernel/image.itb 10591271/tftp-deploy-9g1e0xbk/kernel/cmdline
294 11:12:44.969341 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
295 11:12:44.969430 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
296 11:12:44.969520 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
297 11:12:44.969604 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
298 11:12:44.969674 Not connected, no need to disconnect.
299 11:12:44.969748 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
300 11:12:44.969833 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
301 11:12:44.969898 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-2'
302 11:12:44.973689 Setting prompt string to ['lava-test: # ']
303 11:12:44.974234 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
304 11:12:44.974335 end: 2.2.1 reset-connection (duration 00:00:00) [common]
305 11:12:44.974431 start: 2.2.2 reset-device (timeout 00:05:00) [common]
306 11:12:44.974518 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
307 11:12:44.974706 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
308 11:12:50.106260 >> Command sent successfully.
309 11:12:50.108603 Returned 0 in 5 seconds
310 11:12:50.209018 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
312 11:12:50.209501 end: 2.2.2 reset-device (duration 00:00:05) [common]
313 11:12:50.209646 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
314 11:12:50.209778 Setting prompt string to 'Starting depthcharge on Spherion...'
315 11:12:50.209882 Changing prompt to 'Starting depthcharge on Spherion...'
316 11:12:50.209983 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
317 11:12:50.210350 [Enter `^Ec?' for help]
318 11:12:50.382653
319 11:12:50.382856
320 11:12:50.382959 F0: 102B 0000
321 11:12:50.383053
322 11:12:50.383143 F3: 1001 0000 [0200]
323 11:12:50.386687
324 11:12:50.386797 F3: 1001 0000
325 11:12:50.386930
326 11:12:50.387021 F7: 102D 0000
327 11:12:50.387112
328 11:12:50.390043 F1: 0000 0000
329 11:12:50.390153
330 11:12:50.390247 V0: 0000 0000 [0001]
331 11:12:50.390337
332 11:12:50.390427 00: 0007 8000
333 11:12:50.393902
334 11:12:50.394010 01: 0000 0000
335 11:12:50.394107
336 11:12:50.394199 BP: 0C00 0209 [0000]
337 11:12:50.394289
338 11:12:50.397714 G0: 1182 0000
339 11:12:50.397866
340 11:12:50.397960 EC: 0000 0021 [4000]
341 11:12:50.398050
342 11:12:50.401063 S7: 0000 0000 [0000]
343 11:12:50.401176
344 11:12:50.401271 CC: 0000 0000 [0001]
345 11:12:50.401362
346 11:12:50.404546 T0: 0000 0040 [010F]
347 11:12:50.404654
348 11:12:50.404749 Jump to BL
349 11:12:50.404840
350 11:12:50.429929
351 11:12:50.430066
352 11:12:50.430167
353 11:12:50.437833 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
354 11:12:50.441476 ARM64: Exception handlers installed.
355 11:12:50.445219 ARM64: Testing exception
356 11:12:50.445302 ARM64: Done test exception
357 11:12:50.456006 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
358 11:12:50.462570 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
359 11:12:50.469672 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
360 11:12:50.480722 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
361 11:12:50.487040 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
362 11:12:50.497598 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
363 11:12:50.507806 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
364 11:12:50.514238 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
365 11:12:50.532607 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
366 11:12:50.535870 WDT: Last reset was cold boot
367 11:12:50.539222 SPI1(PAD0) initialized at 2873684 Hz
368 11:12:50.542607 SPI5(PAD0) initialized at 992727 Hz
369 11:12:50.545897 VBOOT: Loading verstage.
370 11:12:50.552744 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
371 11:12:50.556049 FMAP: Found "FLASH" version 1.1 at 0x20000.
372 11:12:50.559148 FMAP: base = 0x0 size = 0x800000 #areas = 25
373 11:12:50.562232 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
374 11:12:50.570072 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
375 11:12:50.576870 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
376 11:12:50.587755 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
377 11:12:50.587868
378 11:12:50.587966
379 11:12:50.597559 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
380 11:12:50.600990 ARM64: Exception handlers installed.
381 11:12:50.604051 ARM64: Testing exception
382 11:12:50.604132 ARM64: Done test exception
383 11:12:50.611549 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
384 11:12:50.614392 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
385 11:12:50.628205 Probing TPM: . done!
386 11:12:50.628287 TPM ready after 0 ms
387 11:12:50.636350 Connected to device vid:did:rid of 1ae0:0028:00
388 11:12:50.642909 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
389 11:12:50.700947 Initialized TPM device CR50 revision 0
390 11:12:50.712532 tlcl_send_startup: Startup return code is 0
391 11:12:50.712634 TPM: setup succeeded
392 11:12:50.724684 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
393 11:12:50.732780 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
394 11:12:50.745837 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
395 11:12:50.755549 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
396 11:12:50.758178 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
397 11:12:50.762959 in-header: 03 07 00 00 08 00 00 00
398 11:12:50.766924 in-data: aa e4 47 04 13 02 00 00
399 11:12:50.770310 Chrome EC: UHEPI supported
400 11:12:50.777702 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
401 11:12:50.781704 in-header: 03 95 00 00 08 00 00 00
402 11:12:50.781791 in-data: 18 20 20 08 00 00 00 00
403 11:12:50.785358 Phase 1
404 11:12:50.788780 FMAP: area GBB found @ 3f5000 (12032 bytes)
405 11:12:50.792351 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
406 11:12:50.800233 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
407 11:12:50.803543 Recovery requested (1009000e)
408 11:12:50.811265 TPM: Extending digest for VBOOT: boot mode into PCR 0
409 11:12:50.816761 tlcl_extend: response is 0
410 11:12:50.825888 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
411 11:12:50.831912 tlcl_extend: response is 0
412 11:12:50.838410 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
413 11:12:50.858480 read SPI 0x210d4 0x2173b: 15142 us, 9048 KB/s, 72.384 Mbps
414 11:12:50.865230 BS: bootblock times (exec / console): total (unknown) / 148 ms
415 11:12:50.865315
416 11:12:50.865382
417 11:12:50.875559 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
418 11:12:50.878807 ARM64: Exception handlers installed.
419 11:12:50.882201 ARM64: Testing exception
420 11:12:50.882287 ARM64: Done test exception
421 11:12:50.904167 pmic_efuse_setting: Set efuses in 11 msecs
422 11:12:50.907540 pmwrap_interface_init: Select PMIF_VLD_RDY
423 11:12:50.913645 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
424 11:12:50.917304 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
425 11:12:50.924188 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
426 11:12:50.927959 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
427 11:12:50.931396 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
428 11:12:50.938885 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
429 11:12:50.942777 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
430 11:12:50.946596 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
431 11:12:50.950231 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
432 11:12:50.957358 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
433 11:12:50.961045 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
434 11:12:50.964783 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
435 11:12:50.968224 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
436 11:12:50.976466 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
437 11:12:50.983471 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
438 11:12:50.987345 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
439 11:12:50.994598 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
440 11:12:50.998787 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
441 11:12:51.006120 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
442 11:12:51.010046 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
443 11:12:51.016797 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
444 11:12:51.020569 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
445 11:12:51.027665 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
446 11:12:51.031969 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
447 11:12:51.038848 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
448 11:12:51.042248 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
449 11:12:51.049671 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
450 11:12:51.053494 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
451 11:12:51.056848 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
452 11:12:51.064161 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
453 11:12:51.068006 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
454 11:12:51.071594 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
455 11:12:51.078770 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
456 11:12:51.082166 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
457 11:12:51.089343 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
458 11:12:51.093564 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
459 11:12:51.096785 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
460 11:12:51.103876 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
461 11:12:51.107673 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
462 11:12:51.111148 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
463 11:12:51.115014 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
464 11:12:51.122633 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
465 11:12:51.126055 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
466 11:12:51.130127 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
467 11:12:51.133953 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
468 11:12:51.137076 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
469 11:12:51.140565 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
470 11:12:51.147455 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
471 11:12:51.151546 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
472 11:12:51.154719 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
473 11:12:51.158662 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
474 11:12:51.165866 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
475 11:12:51.177346 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
476 11:12:51.180430 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
477 11:12:51.187956 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
478 11:12:51.195240 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
479 11:12:51.202630 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
480 11:12:51.206767 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
481 11:12:51.209820 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
482 11:12:51.217086 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x3
483 11:12:51.220647 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
484 11:12:51.229183 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
485 11:12:51.232109 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
486 11:12:51.240898 [RTC]rtc_get_frequency_meter,154: input=15, output=852
487 11:12:51.251627 [RTC]rtc_get_frequency_meter,154: input=7, output=723
488 11:12:51.260122 [RTC]rtc_get_frequency_meter,154: input=11, output=788
489 11:12:51.269968 [RTC]rtc_get_frequency_meter,154: input=13, output=820
490 11:12:51.279139 [RTC]rtc_get_frequency_meter,154: input=12, output=805
491 11:12:51.289065 [RTC]rtc_get_frequency_meter,154: input=11, output=788
492 11:12:51.298696 [RTC]rtc_get_frequency_meter,154: input=12, output=804
493 11:12:51.302259 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
494 11:12:51.306167 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
495 11:12:51.310002 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
496 11:12:51.317271 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
497 11:12:51.320612 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
498 11:12:51.324158 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
499 11:12:51.327550 ADC[4]: Raw value=904064 ID=7
500 11:12:51.330840 ADC[3]: Raw value=213916 ID=1
501 11:12:51.330944 RAM Code: 0x71
502 11:12:51.334755 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
503 11:12:51.342406 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
504 11:12:51.349546 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
505 11:12:51.357478 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
506 11:12:51.360899 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
507 11:12:51.364110 in-header: 03 07 00 00 08 00 00 00
508 11:12:51.368049 in-data: aa e4 47 04 13 02 00 00
509 11:12:51.368147 Chrome EC: UHEPI supported
510 11:12:51.375654 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
511 11:12:51.379170 in-header: 03 95 00 00 08 00 00 00
512 11:12:51.382674 in-data: 18 20 20 08 00 00 00 00
513 11:12:51.386818 MRC: failed to locate region type 0.
514 11:12:51.390120 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
515 11:12:51.393900 DRAM-K: Running full calibration
516 11:12:51.401006 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
517 11:12:51.404949 header.status = 0x0
518 11:12:51.405036 header.version = 0x6 (expected: 0x6)
519 11:12:51.408493 header.size = 0xd00 (expected: 0xd00)
520 11:12:51.411826 header.flags = 0x0
521 11:12:51.418815 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
522 11:12:51.436286 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
523 11:12:51.443274 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
524 11:12:51.447128 dram_init: ddr_geometry: 2
525 11:12:51.447211 [EMI] MDL number = 2
526 11:12:51.450518 [EMI] Get MDL freq = 0
527 11:12:51.450607 dram_init: ddr_type: 0
528 11:12:51.454416 is_discrete_lpddr4: 1
529 11:12:51.458307 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
530 11:12:51.458390
531 11:12:51.458456
532 11:12:51.458517 [Bian_co] ETT version 0.0.0.1
533 11:12:51.464895 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
534 11:12:51.464979
535 11:12:51.468055 dramc_set_vcore_voltage set vcore to 650000
536 11:12:51.471241 Read voltage for 800, 4
537 11:12:51.471324 Vio18 = 0
538 11:12:51.471390 Vcore = 650000
539 11:12:51.474963 Vdram = 0
540 11:12:51.475045 Vddq = 0
541 11:12:51.475111 Vmddr = 0
542 11:12:51.478318 dram_init: config_dvfs: 1
543 11:12:51.481534 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
544 11:12:51.489246 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
545 11:12:51.493248 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
546 11:12:51.497088 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
547 11:12:51.500196 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
548 11:12:51.503378 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
549 11:12:51.506728 MEM_TYPE=3, freq_sel=18
550 11:12:51.506812 sv_algorithm_assistance_LP4_1600
551 11:12:51.513518 ============ PULL DRAM RESETB DOWN ============
552 11:12:51.516735 ========== PULL DRAM RESETB DOWN end =========
553 11:12:51.520584 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
554 11:12:51.524522 ===================================
555 11:12:51.527671 LPDDR4 DRAM CONFIGURATION
556 11:12:51.531077 ===================================
557 11:12:51.531156 EX_ROW_EN[0] = 0x0
558 11:12:51.534465 EX_ROW_EN[1] = 0x0
559 11:12:51.534568 LP4Y_EN = 0x0
560 11:12:51.537857 WORK_FSP = 0x0
561 11:12:51.537927 WL = 0x2
562 11:12:51.540915 RL = 0x2
563 11:12:51.540998 BL = 0x2
564 11:12:51.544380 RPST = 0x0
565 11:12:51.547671 RD_PRE = 0x0
566 11:12:51.547754 WR_PRE = 0x1
567 11:12:51.550931 WR_PST = 0x0
568 11:12:51.551013 DBI_WR = 0x0
569 11:12:51.554293 DBI_RD = 0x0
570 11:12:51.554375 OTF = 0x1
571 11:12:51.557696 ===================================
572 11:12:51.561084 ===================================
573 11:12:51.564528 ANA top config
574 11:12:51.567841 ===================================
575 11:12:51.567950 DLL_ASYNC_EN = 0
576 11:12:51.570636 ALL_SLAVE_EN = 1
577 11:12:51.574301 NEW_RANK_MODE = 1
578 11:12:51.577679 DLL_IDLE_MODE = 1
579 11:12:51.577761 LP45_APHY_COMB_EN = 1
580 11:12:51.580931 TX_ODT_DIS = 1
581 11:12:51.584305 NEW_8X_MODE = 1
582 11:12:51.587309 ===================================
583 11:12:51.590916 ===================================
584 11:12:51.594120 data_rate = 1600
585 11:12:51.597494 CKR = 1
586 11:12:51.597577 DQ_P2S_RATIO = 8
587 11:12:51.600697 ===================================
588 11:12:51.604019 CA_P2S_RATIO = 8
589 11:12:51.607703 DQ_CA_OPEN = 0
590 11:12:51.611598 DQ_SEMI_OPEN = 0
591 11:12:51.614999 CA_SEMI_OPEN = 0
592 11:12:51.615082 CA_FULL_RATE = 0
593 11:12:51.618270 DQ_CKDIV4_EN = 1
594 11:12:51.621424 CA_CKDIV4_EN = 1
595 11:12:51.624938 CA_PREDIV_EN = 0
596 11:12:51.628063 PH8_DLY = 0
597 11:12:51.631144 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
598 11:12:51.631227 DQ_AAMCK_DIV = 4
599 11:12:51.634415 CA_AAMCK_DIV = 4
600 11:12:51.637970 CA_ADMCK_DIV = 4
601 11:12:51.641257 DQ_TRACK_CA_EN = 0
602 11:12:51.644629 CA_PICK = 800
603 11:12:51.647860 CA_MCKIO = 800
604 11:12:51.651748 MCKIO_SEMI = 0
605 11:12:51.651831 PLL_FREQ = 3068
606 11:12:51.655044 DQ_UI_PI_RATIO = 32
607 11:12:51.659040 CA_UI_PI_RATIO = 0
608 11:12:51.662944 ===================================
609 11:12:51.666472 ===================================
610 11:12:51.666554 memory_type:LPDDR4
611 11:12:51.670140 GP_NUM : 10
612 11:12:51.670223 SRAM_EN : 1
613 11:12:51.674111 MD32_EN : 0
614 11:12:51.677763 ===================================
615 11:12:51.677846 [ANA_INIT] >>>>>>>>>>>>>>
616 11:12:51.681508 <<<<<< [CONFIGURE PHASE]: ANA_TX
617 11:12:51.684942 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
618 11:12:51.688778 ===================================
619 11:12:51.691989 data_rate = 1600,PCW = 0X7600
620 11:12:51.695447 ===================================
621 11:12:51.698777 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
622 11:12:51.705224 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
623 11:12:51.708330 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
624 11:12:51.715457 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
625 11:12:51.718335 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
626 11:12:51.721647 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
627 11:12:51.721731 [ANA_INIT] flow start
628 11:12:51.724903 [ANA_INIT] PLL >>>>>>>>
629 11:12:51.728213 [ANA_INIT] PLL <<<<<<<<
630 11:12:51.728296 [ANA_INIT] MIDPI >>>>>>>>
631 11:12:51.731566 [ANA_INIT] MIDPI <<<<<<<<
632 11:12:51.735270 [ANA_INIT] DLL >>>>>>>>
633 11:12:51.735356 [ANA_INIT] flow end
634 11:12:51.741558 ============ LP4 DIFF to SE enter ============
635 11:12:51.745156 ============ LP4 DIFF to SE exit ============
636 11:12:51.745239 [ANA_INIT] <<<<<<<<<<<<<
637 11:12:51.748526 [Flow] Enable top DCM control >>>>>
638 11:12:51.751793 [Flow] Enable top DCM control <<<<<
639 11:12:51.755273 Enable DLL master slave shuffle
640 11:12:51.761681 ==============================================================
641 11:12:51.765173 Gating Mode config
642 11:12:51.768071 ==============================================================
643 11:12:51.771500 Config description:
644 11:12:51.781517 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
645 11:12:51.787932 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
646 11:12:51.791195 SELPH_MODE 0: By rank 1: By Phase
647 11:12:51.798453 ==============================================================
648 11:12:51.801086 GAT_TRACK_EN = 1
649 11:12:51.804635 RX_GATING_MODE = 2
650 11:12:51.808115 RX_GATING_TRACK_MODE = 2
651 11:12:51.808199 SELPH_MODE = 1
652 11:12:51.811450 PICG_EARLY_EN = 1
653 11:12:51.814650 VALID_LAT_VALUE = 1
654 11:12:51.821590 ==============================================================
655 11:12:51.824297 Enter into Gating configuration >>>>
656 11:12:51.827686 Exit from Gating configuration <<<<
657 11:12:51.831088 Enter into DVFS_PRE_config >>>>>
658 11:12:51.840943 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
659 11:12:51.844325 Exit from DVFS_PRE_config <<<<<
660 11:12:51.847919 Enter into PICG configuration >>>>
661 11:12:51.851259 Exit from PICG configuration <<<<
662 11:12:51.854143 [RX_INPUT] configuration >>>>>
663 11:12:51.857548 [RX_INPUT] configuration <<<<<
664 11:12:51.861002 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
665 11:12:51.867245 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
666 11:12:51.874174 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
667 11:12:51.880630 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
668 11:12:51.887611 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
669 11:12:51.891558 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
670 11:12:51.897452 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
671 11:12:51.900891 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
672 11:12:51.904216 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
673 11:12:51.907824 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
674 11:12:51.914196 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
675 11:12:51.917685 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
676 11:12:51.920480 ===================================
677 11:12:51.923860 LPDDR4 DRAM CONFIGURATION
678 11:12:51.927493 ===================================
679 11:12:51.927576 EX_ROW_EN[0] = 0x0
680 11:12:51.930501 EX_ROW_EN[1] = 0x0
681 11:12:51.930583 LP4Y_EN = 0x0
682 11:12:51.933809 WORK_FSP = 0x0
683 11:12:51.933893 WL = 0x2
684 11:12:51.937068 RL = 0x2
685 11:12:51.937154 BL = 0x2
686 11:12:51.940767 RPST = 0x0
687 11:12:51.940876 RD_PRE = 0x0
688 11:12:51.944074 WR_PRE = 0x1
689 11:12:51.947053 WR_PST = 0x0
690 11:12:51.947137 DBI_WR = 0x0
691 11:12:51.950498 DBI_RD = 0x0
692 11:12:51.950612 OTF = 0x1
693 11:12:51.953902 ===================================
694 11:12:51.957388 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
695 11:12:51.960612 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
696 11:12:51.966960 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
697 11:12:51.970292 ===================================
698 11:12:51.973891 LPDDR4 DRAM CONFIGURATION
699 11:12:51.977322 ===================================
700 11:12:51.977408 EX_ROW_EN[0] = 0x10
701 11:12:51.980553 EX_ROW_EN[1] = 0x0
702 11:12:51.980666 LP4Y_EN = 0x0
703 11:12:51.984003 WORK_FSP = 0x0
704 11:12:51.984106 WL = 0x2
705 11:12:51.986741 RL = 0x2
706 11:12:51.986825 BL = 0x2
707 11:12:51.990587 RPST = 0x0
708 11:12:51.990686 RD_PRE = 0x0
709 11:12:51.993464 WR_PRE = 0x1
710 11:12:51.993576 WR_PST = 0x0
711 11:12:51.997350 DBI_WR = 0x0
712 11:12:51.997449 DBI_RD = 0x0
713 11:12:52.000222 OTF = 0x1
714 11:12:52.003328 ===================================
715 11:12:52.009983 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
716 11:12:52.013493 nWR fixed to 40
717 11:12:52.016702 [ModeRegInit_LP4] CH0 RK0
718 11:12:52.016799 [ModeRegInit_LP4] CH0 RK1
719 11:12:52.020079 [ModeRegInit_LP4] CH1 RK0
720 11:12:52.023466 [ModeRegInit_LP4] CH1 RK1
721 11:12:52.023587 match AC timing 13
722 11:12:52.030349 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
723 11:12:52.033082 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
724 11:12:52.036597 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
725 11:12:52.043105 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
726 11:12:52.046504 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
727 11:12:52.049916 [EMI DOE] emi_dcm 0
728 11:12:52.053287 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
729 11:12:52.053389 ==
730 11:12:52.056625 Dram Type= 6, Freq= 0, CH_0, rank 0
731 11:12:52.060106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
732 11:12:52.060182 ==
733 11:12:52.066504 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
734 11:12:52.072896 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
735 11:12:52.080931 [CA 0] Center 38 (7~69) winsize 63
736 11:12:52.084367 [CA 1] Center 37 (7~68) winsize 62
737 11:12:52.087684 [CA 2] Center 34 (4~65) winsize 62
738 11:12:52.091015 [CA 3] Center 35 (4~66) winsize 63
739 11:12:52.094403 [CA 4] Center 33 (3~64) winsize 62
740 11:12:52.097498 [CA 5] Center 33 (3~64) winsize 62
741 11:12:52.097581
742 11:12:52.100803 [CmdBusTrainingLP45] Vref(ca) range 1: 34
743 11:12:52.100887
744 11:12:52.103864 [CATrainingPosCal] consider 1 rank data
745 11:12:52.107186 u2DelayCellTimex100 = 270/100 ps
746 11:12:52.110791 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
747 11:12:52.117541 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
748 11:12:52.120404 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
749 11:12:52.123613 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
750 11:12:52.126900 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
751 11:12:52.130582 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
752 11:12:52.130671
753 11:12:52.133866 CA PerBit enable=1, Macro0, CA PI delay=33
754 11:12:52.133978
755 11:12:52.137101 [CBTSetCACLKResult] CA Dly = 33
756 11:12:52.140163 CS Dly: 6 (0~37)
757 11:12:52.140246 ==
758 11:12:52.143689 Dram Type= 6, Freq= 0, CH_0, rank 1
759 11:12:52.146907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
760 11:12:52.146990 ==
761 11:12:52.153653 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
762 11:12:52.157221 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
763 11:12:52.167237 [CA 0] Center 38 (7~69) winsize 63
764 11:12:52.170648 [CA 1] Center 37 (7~68) winsize 62
765 11:12:52.173885 [CA 2] Center 35 (4~66) winsize 63
766 11:12:52.177304 [CA 3] Center 35 (4~66) winsize 63
767 11:12:52.180585 [CA 4] Center 34 (3~65) winsize 63
768 11:12:52.183865 [CA 5] Center 33 (3~64) winsize 62
769 11:12:52.183988
770 11:12:52.187458 [CmdBusTrainingLP45] Vref(ca) range 1: 32
771 11:12:52.187559
772 11:12:52.190662 [CATrainingPosCal] consider 2 rank data
773 11:12:52.194027 u2DelayCellTimex100 = 270/100 ps
774 11:12:52.197401 CA0 delay=38 (7~69),Diff = 5 PI (36 cell)
775 11:12:52.203963 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
776 11:12:52.207135 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
777 11:12:52.210660 CA3 delay=35 (4~66),Diff = 2 PI (14 cell)
778 11:12:52.214012 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
779 11:12:52.217220 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
780 11:12:52.217323
781 11:12:52.220699 CA PerBit enable=1, Macro0, CA PI delay=33
782 11:12:52.220791
783 11:12:52.224552 [CBTSetCACLKResult] CA Dly = 33
784 11:12:52.224635 CS Dly: 6 (0~38)
785 11:12:52.227096
786 11:12:52.230799 ----->DramcWriteLeveling(PI) begin...
787 11:12:52.230906 ==
788 11:12:52.234235 Dram Type= 6, Freq= 0, CH_0, rank 0
789 11:12:52.238399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
790 11:12:52.238510 ==
791 11:12:52.242130 Write leveling (Byte 0): 30 => 30
792 11:12:52.242225 Write leveling (Byte 1): 29 => 29
793 11:12:52.245570 DramcWriteLeveling(PI) end<-----
794 11:12:52.245703
795 11:12:52.245807 ==
796 11:12:52.249106 Dram Type= 6, Freq= 0, CH_0, rank 0
797 11:12:52.253284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
798 11:12:52.253389 ==
799 11:12:52.255810 [Gating] SW mode calibration
800 11:12:52.263133 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
801 11:12:52.269856 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
802 11:12:52.273335 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
803 11:12:52.276852 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
804 11:12:52.283164 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
805 11:12:52.286694 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 11:12:52.289798 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 11:12:52.296575 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 11:12:52.299817 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 11:12:52.303625 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 11:12:52.309920 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 11:12:52.312995 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 11:12:52.316794 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 11:12:52.323282 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 11:12:52.326658 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 11:12:52.329773 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 11:12:52.336384 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 11:12:52.339596 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 11:12:52.343064 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 11:12:52.349822 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
820 11:12:52.353040 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
821 11:12:52.356406 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 11:12:52.359522 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 11:12:52.366117 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 11:12:52.369511 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 11:12:52.372795 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 11:12:52.379465 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 11:12:52.382911 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 11:12:52.385909 0 9 8 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
829 11:12:52.392689 0 9 12 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
830 11:12:52.396097 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
831 11:12:52.399338 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
832 11:12:52.406074 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
833 11:12:52.409089 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
834 11:12:52.412358 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
835 11:12:52.418975 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 0)
836 11:12:52.422864 0 10 8 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
837 11:12:52.426011 0 10 12 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
838 11:12:52.432619 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 11:12:52.435652 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 11:12:52.438910 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 11:12:52.445738 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
842 11:12:52.449162 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
843 11:12:52.452642 0 11 4 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
844 11:12:52.458930 0 11 8 | B1->B0 | 2c2c 4545 | 1 1 | (0 0) (0 0)
845 11:12:52.462755 0 11 12 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
846 11:12:52.465550 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
847 11:12:52.472110 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
848 11:12:52.475391 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
849 11:12:52.478691 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 11:12:52.485630 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
851 11:12:52.489035 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
852 11:12:52.492506 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
853 11:12:52.498713 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
854 11:12:52.502061 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 11:12:52.505139 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 11:12:52.511947 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 11:12:52.515270 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 11:12:52.518600 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
859 11:12:52.525090 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
860 11:12:52.528731 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
861 11:12:52.532131 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
862 11:12:52.535282 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
863 11:12:52.541786 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
864 11:12:52.545060 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
865 11:12:52.548448 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
866 11:12:52.555302 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
867 11:12:52.558484 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
868 11:12:52.561793 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
869 11:12:52.565099 Total UI for P1: 0, mck2ui 16
870 11:12:52.568441 best dqsien dly found for B0: ( 0, 14, 4)
871 11:12:52.575228 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
872 11:12:52.578621 Total UI for P1: 0, mck2ui 16
873 11:12:52.581921 best dqsien dly found for B1: ( 0, 14, 8)
874 11:12:52.585086 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
875 11:12:52.588063 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
876 11:12:52.588148
877 11:12:52.591771 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
878 11:12:52.594661 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
879 11:12:52.598044 [Gating] SW calibration Done
880 11:12:52.598129 ==
881 11:12:52.601456 Dram Type= 6, Freq= 0, CH_0, rank 0
882 11:12:52.604795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
883 11:12:52.604882 ==
884 11:12:52.608754 RX Vref Scan: 0
885 11:12:52.608840
886 11:12:52.608924 RX Vref 0 -> 0, step: 1
887 11:12:52.609004
888 11:12:52.612000 RX Delay -130 -> 252, step: 16
889 11:12:52.615151 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
890 11:12:52.621858 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
891 11:12:52.625251 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
892 11:12:52.628551 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
893 11:12:52.632065 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
894 11:12:52.635483 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
895 11:12:52.642177 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
896 11:12:52.645317 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
897 11:12:52.648521 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
898 11:12:52.651780 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
899 11:12:52.655209 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
900 11:12:52.661927 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
901 11:12:52.665185 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
902 11:12:52.668287 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
903 11:12:52.671479 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
904 11:12:52.678236 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
905 11:12:52.678318 ==
906 11:12:52.681663 Dram Type= 6, Freq= 0, CH_0, rank 0
907 11:12:52.685043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
908 11:12:52.685126 ==
909 11:12:52.685192 DQS Delay:
910 11:12:52.688237 DQS0 = 0, DQS1 = 0
911 11:12:52.688319 DQM Delay:
912 11:12:52.691546 DQM0 = 89, DQM1 = 74
913 11:12:52.691627 DQ Delay:
914 11:12:52.694861 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =85
915 11:12:52.698126 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
916 11:12:52.701396 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
917 11:12:52.704693 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
918 11:12:52.704775
919 11:12:52.704839
920 11:12:52.704899 ==
921 11:12:52.708179 Dram Type= 6, Freq= 0, CH_0, rank 0
922 11:12:52.711525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
923 11:12:52.711608 ==
924 11:12:52.711671
925 11:12:52.711731
926 11:12:52.714866 TX Vref Scan disable
927 11:12:52.718105 == TX Byte 0 ==
928 11:12:52.721097 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
929 11:12:52.724928 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
930 11:12:52.727708 == TX Byte 1 ==
931 11:12:52.731485 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
932 11:12:52.734429 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
933 11:12:52.734516 ==
934 11:12:52.737906 Dram Type= 6, Freq= 0, CH_0, rank 0
935 11:12:52.744654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
936 11:12:52.744739 ==
937 11:12:52.756565 TX Vref=22, minBit 0, minWin=27, winSum=442
938 11:12:52.759326 TX Vref=24, minBit 0, minWin=27, winSum=442
939 11:12:52.762715 TX Vref=26, minBit 1, minWin=27, winSum=445
940 11:12:52.766012 TX Vref=28, minBit 1, minWin=27, winSum=449
941 11:12:52.769267 TX Vref=30, minBit 2, minWin=27, winSum=451
942 11:12:52.776279 TX Vref=32, minBit 1, minWin=27, winSum=446
943 11:12:52.779068 [TxChooseVref] Worse bit 2, Min win 27, Win sum 451, Final Vref 30
944 11:12:52.779157
945 11:12:52.782519 Final TX Range 1 Vref 30
946 11:12:52.782603
947 11:12:52.782669 ==
948 11:12:52.785929 Dram Type= 6, Freq= 0, CH_0, rank 0
949 11:12:52.789168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
950 11:12:52.789253 ==
951 11:12:52.792394
952 11:12:52.792479
953 11:12:52.792544 TX Vref Scan disable
954 11:12:52.796281 == TX Byte 0 ==
955 11:12:52.799095 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
956 11:12:52.805829 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
957 11:12:52.805930 == TX Byte 1 ==
958 11:12:52.809250 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
959 11:12:52.816188 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
960 11:12:52.816281
961 11:12:52.816347 [DATLAT]
962 11:12:52.816407 Freq=800, CH0 RK0
963 11:12:52.816466
964 11:12:52.819131 DATLAT Default: 0xa
965 11:12:52.819213 0, 0xFFFF, sum = 0
966 11:12:52.822775 1, 0xFFFF, sum = 0
967 11:12:52.822866 2, 0xFFFF, sum = 0
968 11:12:52.826115 3, 0xFFFF, sum = 0
969 11:12:52.829307 4, 0xFFFF, sum = 0
970 11:12:52.829393 5, 0xFFFF, sum = 0
971 11:12:52.832750 6, 0xFFFF, sum = 0
972 11:12:52.832835 7, 0xFFFF, sum = 0
973 11:12:52.835914 8, 0xFFFF, sum = 0
974 11:12:52.836025 9, 0x0, sum = 1
975 11:12:52.836148 10, 0x0, sum = 2
976 11:12:52.839350 11, 0x0, sum = 3
977 11:12:52.839435 12, 0x0, sum = 4
978 11:12:52.842491 best_step = 10
979 11:12:52.842575
980 11:12:52.842659 ==
981 11:12:52.845902 Dram Type= 6, Freq= 0, CH_0, rank 0
982 11:12:52.849350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
983 11:12:52.849435 ==
984 11:12:52.852320 RX Vref Scan: 1
985 11:12:52.852407
986 11:12:52.855542 Set Vref Range= 32 -> 127
987 11:12:52.855626
988 11:12:52.855727 RX Vref 32 -> 127, step: 1
989 11:12:52.855826
990 11:12:52.858836 RX Delay -111 -> 252, step: 8
991 11:12:52.858920
992 11:12:52.862801 Set Vref, RX VrefLevel [Byte0]: 32
993 11:12:52.865954 [Byte1]: 32
994 11:12:52.866037
995 11:12:52.869381 Set Vref, RX VrefLevel [Byte0]: 33
996 11:12:52.872101 [Byte1]: 33
997 11:12:52.876525
998 11:12:52.876608 Set Vref, RX VrefLevel [Byte0]: 34
999 11:12:52.879800 [Byte1]: 34
1000 11:12:52.884109
1001 11:12:52.884192 Set Vref, RX VrefLevel [Byte0]: 35
1002 11:12:52.887536 [Byte1]: 35
1003 11:12:52.891989
1004 11:12:52.892093 Set Vref, RX VrefLevel [Byte0]: 36
1005 11:12:52.895244 [Byte1]: 36
1006 11:12:52.900361
1007 11:12:52.900444 Set Vref, RX VrefLevel [Byte0]: 37
1008 11:12:52.903069 [Byte1]: 37
1009 11:12:52.907567
1010 11:12:52.907652 Set Vref, RX VrefLevel [Byte0]: 38
1011 11:12:52.910964 [Byte1]: 38
1012 11:12:52.914886
1013 11:12:52.914969 Set Vref, RX VrefLevel [Byte0]: 39
1014 11:12:52.918339 [Byte1]: 39
1015 11:12:52.922743
1016 11:12:52.922827 Set Vref, RX VrefLevel [Byte0]: 40
1017 11:12:52.926114 [Byte1]: 40
1018 11:12:52.930362
1019 11:12:52.930452 Set Vref, RX VrefLevel [Byte0]: 41
1020 11:12:52.933776 [Byte1]: 41
1021 11:12:52.937496
1022 11:12:52.937587 Set Vref, RX VrefLevel [Byte0]: 42
1023 11:12:52.941026 [Byte1]: 42
1024 11:12:52.945360
1025 11:12:52.945450 Set Vref, RX VrefLevel [Byte0]: 43
1026 11:12:52.948677 [Byte1]: 43
1027 11:12:52.953116
1028 11:12:52.953201 Set Vref, RX VrefLevel [Byte0]: 44
1029 11:12:52.956550 [Byte1]: 44
1030 11:12:52.960643
1031 11:12:52.960729 Set Vref, RX VrefLevel [Byte0]: 45
1032 11:12:52.963961 [Byte1]: 45
1033 11:12:52.968516
1034 11:12:52.968601 Set Vref, RX VrefLevel [Byte0]: 46
1035 11:12:52.971389 [Byte1]: 46
1036 11:12:52.975747
1037 11:12:52.978969 Set Vref, RX VrefLevel [Byte0]: 47
1038 11:12:52.982273 [Byte1]: 47
1039 11:12:52.982366
1040 11:12:52.985435 Set Vref, RX VrefLevel [Byte0]: 48
1041 11:12:52.988750 [Byte1]: 48
1042 11:12:52.988834
1043 11:12:52.992078 Set Vref, RX VrefLevel [Byte0]: 49
1044 11:12:52.995576 [Byte1]: 49
1045 11:12:52.998791
1046 11:12:52.998878 Set Vref, RX VrefLevel [Byte0]: 50
1047 11:12:53.002176 [Byte1]: 50
1048 11:12:53.006674
1049 11:12:53.006765 Set Vref, RX VrefLevel [Byte0]: 51
1050 11:12:53.009955 [Byte1]: 51
1051 11:12:53.013916
1052 11:12:53.014003 Set Vref, RX VrefLevel [Byte0]: 52
1053 11:12:53.017280 [Byte1]: 52
1054 11:12:53.021924
1055 11:12:53.022014 Set Vref, RX VrefLevel [Byte0]: 53
1056 11:12:53.024981 [Byte1]: 53
1057 11:12:53.029476
1058 11:12:53.029559 Set Vref, RX VrefLevel [Byte0]: 54
1059 11:12:53.032592 [Byte1]: 54
1060 11:12:53.037186
1061 11:12:53.037270 Set Vref, RX VrefLevel [Byte0]: 55
1062 11:12:53.040283 [Byte1]: 55
1063 11:12:53.044566
1064 11:12:53.044649 Set Vref, RX VrefLevel [Byte0]: 56
1065 11:12:53.047862 [Byte1]: 56
1066 11:12:53.052146
1067 11:12:53.052233 Set Vref, RX VrefLevel [Byte0]: 57
1068 11:12:53.055475 [Byte1]: 57
1069 11:12:53.060412
1070 11:12:53.060494 Set Vref, RX VrefLevel [Byte0]: 58
1071 11:12:53.063412 [Byte1]: 58
1072 11:12:53.067845
1073 11:12:53.067926 Set Vref, RX VrefLevel [Byte0]: 59
1074 11:12:53.071304 [Byte1]: 59
1075 11:12:53.075314
1076 11:12:53.075396 Set Vref, RX VrefLevel [Byte0]: 60
1077 11:12:53.078573 [Byte1]: 60
1078 11:12:53.082912
1079 11:12:53.082994 Set Vref, RX VrefLevel [Byte0]: 61
1080 11:12:53.086231 [Byte1]: 61
1081 11:12:53.090608
1082 11:12:53.090689 Set Vref, RX VrefLevel [Byte0]: 62
1083 11:12:53.093765 [Byte1]: 62
1084 11:12:53.098347
1085 11:12:53.098428 Set Vref, RX VrefLevel [Byte0]: 63
1086 11:12:53.101628 [Byte1]: 63
1087 11:12:53.105980
1088 11:12:53.106063 Set Vref, RX VrefLevel [Byte0]: 64
1089 11:12:53.109474 [Byte1]: 64
1090 11:12:53.113496
1091 11:12:53.113578 Set Vref, RX VrefLevel [Byte0]: 65
1092 11:12:53.116790 [Byte1]: 65
1093 11:12:53.121219
1094 11:12:53.121301 Set Vref, RX VrefLevel [Byte0]: 66
1095 11:12:53.124511 [Byte1]: 66
1096 11:12:53.128960
1097 11:12:53.129041 Set Vref, RX VrefLevel [Byte0]: 67
1098 11:12:53.132175 [Byte1]: 67
1099 11:12:53.136376
1100 11:12:53.136458 Set Vref, RX VrefLevel [Byte0]: 68
1101 11:12:53.139580 [Byte1]: 68
1102 11:12:53.143945
1103 11:12:53.144027 Set Vref, RX VrefLevel [Byte0]: 69
1104 11:12:53.147849 [Byte1]: 69
1105 11:12:53.151467
1106 11:12:53.151549 Set Vref, RX VrefLevel [Byte0]: 70
1107 11:12:53.154660 [Byte1]: 70
1108 11:12:53.159190
1109 11:12:53.159272 Set Vref, RX VrefLevel [Byte0]: 71
1110 11:12:53.162653 [Byte1]: 71
1111 11:12:53.167127
1112 11:12:53.167214 Set Vref, RX VrefLevel [Byte0]: 72
1113 11:12:53.170178 [Byte1]: 72
1114 11:12:53.174576
1115 11:12:53.174657 Set Vref, RX VrefLevel [Byte0]: 73
1116 11:12:53.177964 [Byte1]: 73
1117 11:12:53.182237
1118 11:12:53.182322 Set Vref, RX VrefLevel [Byte0]: 74
1119 11:12:53.185587 [Byte1]: 74
1120 11:12:53.190187
1121 11:12:53.190281 Set Vref, RX VrefLevel [Byte0]: 75
1122 11:12:53.193280 [Byte1]: 75
1123 11:12:53.197828
1124 11:12:53.197910 Final RX Vref Byte 0 = 54 to rank0
1125 11:12:53.200642 Final RX Vref Byte 1 = 60 to rank0
1126 11:12:53.203874 Final RX Vref Byte 0 = 54 to rank1
1127 11:12:53.207683 Final RX Vref Byte 1 = 60 to rank1==
1128 11:12:53.210910 Dram Type= 6, Freq= 0, CH_0, rank 0
1129 11:12:53.217625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1130 11:12:53.217723 ==
1131 11:12:53.217790 DQS Delay:
1132 11:12:53.217851 DQS0 = 0, DQS1 = 0
1133 11:12:53.220983 DQM Delay:
1134 11:12:53.221064 DQM0 = 88, DQM1 = 76
1135 11:12:53.223826 DQ Delay:
1136 11:12:53.227196 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =88
1137 11:12:53.230538 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1138 11:12:53.234037 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =72
1139 11:12:53.237224 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =84
1140 11:12:53.237306
1141 11:12:53.237371
1142 11:12:53.243736 [DQSOSCAuto] RK0, (LSB)MR18= 0x332b, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
1143 11:12:53.247034 CH0 RK0: MR19=606, MR18=332B
1144 11:12:53.253731 CH0_RK0: MR19=0x606, MR18=0x332B, DQSOSC=396, MR23=63, INC=94, DEC=62
1145 11:12:53.253903
1146 11:12:53.256908 ----->DramcWriteLeveling(PI) begin...
1147 11:12:53.257012 ==
1148 11:12:53.260303 Dram Type= 6, Freq= 0, CH_0, rank 1
1149 11:12:53.263798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1150 11:12:53.263906 ==
1151 11:12:53.267459 Write leveling (Byte 0): 34 => 34
1152 11:12:53.270759 Write leveling (Byte 1): 29 => 29
1153 11:12:53.273916 DramcWriteLeveling(PI) end<-----
1154 11:12:53.273997
1155 11:12:53.274060 ==
1156 11:12:53.277272 Dram Type= 6, Freq= 0, CH_0, rank 1
1157 11:12:53.280318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1158 11:12:53.280402 ==
1159 11:12:53.283939 [Gating] SW mode calibration
1160 11:12:53.290640 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1161 11:12:53.337871 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1162 11:12:53.338144 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1163 11:12:53.338230 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1164 11:12:53.338306 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1165 11:12:53.338399 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 11:12:53.338502 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 11:12:53.338570 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 11:12:53.338668 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 11:12:53.338734 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 11:12:53.338833 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 11:12:53.382036 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 11:12:53.382137 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 11:12:53.382382 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 11:12:53.382448 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 11:12:53.382507 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 11:12:53.382575 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 11:12:53.382636 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 11:12:53.382879 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1179 11:12:53.382944 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1180 11:12:53.383049 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 11:12:53.423405 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 11:12:53.423493 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 11:12:53.423740 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 11:12:53.423819 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 11:12:53.423923 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 11:12:53.423983 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 11:12:53.424061 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1188 11:12:53.424131 0 9 8 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
1189 11:12:53.424366 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
1190 11:12:53.427733 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1191 11:12:53.431274 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1192 11:12:53.433995 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1193 11:12:53.437341 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1194 11:12:53.440865 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1195 11:12:53.447275 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
1196 11:12:53.450916 0 10 8 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
1197 11:12:53.454240 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1198 11:12:53.460637 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 11:12:53.463896 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 11:12:53.467620 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 11:12:53.470899 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 11:12:53.477863 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 11:12:53.481138 0 11 4 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
1204 11:12:53.485088 0 11 8 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
1205 11:12:53.489010 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1206 11:12:53.495594 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1207 11:12:53.498837 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1208 11:12:53.502077 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1209 11:12:53.509760 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1210 11:12:53.512625 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1211 11:12:53.515933 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1212 11:12:53.519731 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1213 11:12:53.525895 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 11:12:53.529354 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 11:12:53.532779 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 11:12:53.539468 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 11:12:53.542808 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 11:12:53.545763 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 11:12:53.552780 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 11:12:53.555765 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1221 11:12:53.558952 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 11:12:53.565845 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 11:12:53.569014 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 11:12:53.572759 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1225 11:12:53.578896 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 11:12:53.582593 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 11:12:53.585666 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1228 11:12:53.592734 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1229 11:12:53.592818 Total UI for P1: 0, mck2ui 16
1230 11:12:53.598872 best dqsien dly found for B0: ( 0, 14, 4)
1231 11:12:53.602119 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1232 11:12:53.605322 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1233 11:12:53.608526 Total UI for P1: 0, mck2ui 16
1234 11:12:53.612290 best dqsien dly found for B1: ( 0, 14, 10)
1235 11:12:53.615262 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1236 11:12:53.618494 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1237 11:12:53.618578
1238 11:12:53.622323 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1239 11:12:53.628807 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1240 11:12:53.628914 [Gating] SW calibration Done
1241 11:12:53.631869 ==
1242 11:12:53.631952 Dram Type= 6, Freq= 0, CH_0, rank 1
1243 11:12:53.638747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1244 11:12:53.638832 ==
1245 11:12:53.638898 RX Vref Scan: 0
1246 11:12:53.638959
1247 11:12:53.642222 RX Vref 0 -> 0, step: 1
1248 11:12:53.642304
1249 11:12:53.645532 RX Delay -130 -> 252, step: 16
1250 11:12:53.648916 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1251 11:12:53.652103 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1252 11:12:53.655693 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1253 11:12:53.661895 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1254 11:12:53.665192 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1255 11:12:53.668314 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1256 11:12:53.671620 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1257 11:12:53.675271 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1258 11:12:53.681816 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1259 11:12:53.684671 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1260 11:12:53.688311 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1261 11:12:53.691493 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1262 11:12:53.698077 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1263 11:12:53.701375 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1264 11:12:53.704599 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1265 11:12:53.707906 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1266 11:12:53.708017 ==
1267 11:12:53.711170 Dram Type= 6, Freq= 0, CH_0, rank 1
1268 11:12:53.717841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1269 11:12:53.717926 ==
1270 11:12:53.717993 DQS Delay:
1271 11:12:53.718055 DQS0 = 0, DQS1 = 0
1272 11:12:53.721380 DQM Delay:
1273 11:12:53.721463 DQM0 = 86, DQM1 = 76
1274 11:12:53.724730 DQ Delay:
1275 11:12:53.727877 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1276 11:12:53.727985 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1277 11:12:53.731233 DQ8 =69, DQ9 =61, DQ10 =69, DQ11 =69
1278 11:12:53.734985 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1279 11:12:53.738316
1280 11:12:53.738399
1281 11:12:53.738464 ==
1282 11:12:53.741710 Dram Type= 6, Freq= 0, CH_0, rank 1
1283 11:12:53.744575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1284 11:12:53.744657 ==
1285 11:12:53.744723
1286 11:12:53.744782
1287 11:12:53.747941 TX Vref Scan disable
1288 11:12:53.748023 == TX Byte 0 ==
1289 11:12:53.754643 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1290 11:12:53.758703 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1291 11:12:53.758786 == TX Byte 1 ==
1292 11:12:53.764744 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1293 11:12:53.767938 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1294 11:12:53.768020 ==
1295 11:12:53.771513 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 11:12:53.774831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 11:12:53.774915 ==
1298 11:12:53.788746 TX Vref=22, minBit 1, minWin=27, winSum=446
1299 11:12:53.792315 TX Vref=24, minBit 1, minWin=27, winSum=442
1300 11:12:53.795421 TX Vref=26, minBit 4, minWin=27, winSum=451
1301 11:12:53.798824 TX Vref=28, minBit 5, minWin=27, winSum=453
1302 11:12:53.802158 TX Vref=30, minBit 4, minWin=27, winSum=451
1303 11:12:53.808689 TX Vref=32, minBit 5, minWin=27, winSum=454
1304 11:12:53.811947 [TxChooseVref] Worse bit 5, Min win 27, Win sum 454, Final Vref 32
1305 11:12:53.812091
1306 11:12:53.815230 Final TX Range 1 Vref 32
1307 11:12:53.815313
1308 11:12:53.815379 ==
1309 11:12:53.818906 Dram Type= 6, Freq= 0, CH_0, rank 1
1310 11:12:53.822277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1311 11:12:53.822362 ==
1312 11:12:53.825129
1313 11:12:53.825210
1314 11:12:53.825273 TX Vref Scan disable
1315 11:12:53.829005 == TX Byte 0 ==
1316 11:12:53.832243 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1317 11:12:53.838993 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1318 11:12:53.839075 == TX Byte 1 ==
1319 11:12:53.842128 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1320 11:12:53.848849 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1321 11:12:53.848931
1322 11:12:53.848995 [DATLAT]
1323 11:12:53.849054 Freq=800, CH0 RK1
1324 11:12:53.849111
1325 11:12:53.852238 DATLAT Default: 0xa
1326 11:12:53.852329 0, 0xFFFF, sum = 0
1327 11:12:53.855627 1, 0xFFFF, sum = 0
1328 11:12:53.855709 2, 0xFFFF, sum = 0
1329 11:12:53.858967 3, 0xFFFF, sum = 0
1330 11:12:53.861870 4, 0xFFFF, sum = 0
1331 11:12:53.861952 5, 0xFFFF, sum = 0
1332 11:12:53.865189 6, 0xFFFF, sum = 0
1333 11:12:53.865282 7, 0xFFFF, sum = 0
1334 11:12:53.868750 8, 0xFFFF, sum = 0
1335 11:12:53.868832 9, 0x0, sum = 1
1336 11:12:53.871739 10, 0x0, sum = 2
1337 11:12:53.871820 11, 0x0, sum = 3
1338 11:12:53.871897 12, 0x0, sum = 4
1339 11:12:53.875271 best_step = 10
1340 11:12:53.875351
1341 11:12:53.875413 ==
1342 11:12:53.878628 Dram Type= 6, Freq= 0, CH_0, rank 1
1343 11:12:53.881849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1344 11:12:53.881931 ==
1345 11:12:53.885368 RX Vref Scan: 0
1346 11:12:53.885441
1347 11:12:53.885502 RX Vref 0 -> 0, step: 1
1348 11:12:53.888695
1349 11:12:53.888770 RX Delay -95 -> 252, step: 8
1350 11:12:53.895660 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1351 11:12:53.899020 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1352 11:12:53.902433 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1353 11:12:53.905309 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1354 11:12:53.908711 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1355 11:12:53.915358 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1356 11:12:53.918741 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1357 11:12:53.922059 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1358 11:12:53.925032 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1359 11:12:53.928501 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1360 11:12:53.935527 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1361 11:12:53.938673 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1362 11:12:53.942084 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1363 11:12:53.945503 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1364 11:12:53.951994 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1365 11:12:53.954871 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1366 11:12:53.954970 ==
1367 11:12:53.958237 Dram Type= 6, Freq= 0, CH_0, rank 1
1368 11:12:53.961691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1369 11:12:53.961773 ==
1370 11:12:53.964962 DQS Delay:
1371 11:12:53.965043 DQS0 = 0, DQS1 = 0
1372 11:12:53.965106 DQM Delay:
1373 11:12:53.968182 DQM0 = 86, DQM1 = 77
1374 11:12:53.968262 DQ Delay:
1375 11:12:53.971694 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1376 11:12:53.974768 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1377 11:12:53.977905 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =72
1378 11:12:53.981279 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =84
1379 11:12:53.981360
1380 11:12:53.981422
1381 11:12:53.991680 [DQSOSCAuto] RK1, (LSB)MR18= 0x2925, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 399 ps
1382 11:12:53.994549 CH0 RK1: MR19=606, MR18=2925
1383 11:12:53.997819 CH0_RK1: MR19=0x606, MR18=0x2925, DQSOSC=399, MR23=63, INC=92, DEC=61
1384 11:12:54.000954 [RxdqsGatingPostProcess] freq 800
1385 11:12:54.007941 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1386 11:12:54.011242 Pre-setting of DQS Precalculation
1387 11:12:54.014448 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1388 11:12:54.014575 ==
1389 11:12:54.017724 Dram Type= 6, Freq= 0, CH_1, rank 0
1390 11:12:54.024609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1391 11:12:54.024694 ==
1392 11:12:54.028114 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1393 11:12:54.034272 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1394 11:12:54.043673 [CA 0] Center 36 (6~67) winsize 62
1395 11:12:54.047179 [CA 1] Center 37 (6~68) winsize 63
1396 11:12:54.050557 [CA 2] Center 34 (4~65) winsize 62
1397 11:12:54.053971 [CA 3] Center 34 (4~65) winsize 62
1398 11:12:54.057451 [CA 4] Center 34 (4~65) winsize 62
1399 11:12:54.060911 [CA 5] Center 33 (3~64) winsize 62
1400 11:12:54.061019
1401 11:12:54.063812 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1402 11:12:54.063934
1403 11:12:54.067368 [CATrainingPosCal] consider 1 rank data
1404 11:12:54.070832 u2DelayCellTimex100 = 270/100 ps
1405 11:12:54.074211 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1406 11:12:54.077002 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1407 11:12:54.083525 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1408 11:12:54.086904 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1409 11:12:54.090226 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1410 11:12:54.093572 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1411 11:12:54.093675
1412 11:12:54.097045 CA PerBit enable=1, Macro0, CA PI delay=33
1413 11:12:54.097129
1414 11:12:54.100270 [CBTSetCACLKResult] CA Dly = 33
1415 11:12:54.100347 CS Dly: 4 (0~35)
1416 11:12:54.103361 ==
1417 11:12:54.103446 Dram Type= 6, Freq= 0, CH_1, rank 1
1418 11:12:54.109976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1419 11:12:54.110071 ==
1420 11:12:54.113125 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1421 11:12:54.119828 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1422 11:12:54.129921 [CA 0] Center 36 (6~67) winsize 62
1423 11:12:54.133068 [CA 1] Center 36 (6~67) winsize 62
1424 11:12:54.136528 [CA 2] Center 34 (4~65) winsize 62
1425 11:12:54.139778 [CA 3] Center 34 (3~65) winsize 63
1426 11:12:54.143760 [CA 4] Center 34 (3~65) winsize 63
1427 11:12:54.147128 [CA 5] Center 34 (3~65) winsize 63
1428 11:12:54.147214
1429 11:12:54.150562 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1430 11:12:54.150646
1431 11:12:54.153897 [CATrainingPosCal] consider 2 rank data
1432 11:12:54.157999 u2DelayCellTimex100 = 270/100 ps
1433 11:12:54.161364 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1434 11:12:54.164906 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1435 11:12:54.168846 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1436 11:12:54.172872 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1437 11:12:54.176121 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1438 11:12:54.179582 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1439 11:12:54.179689
1440 11:12:54.183062 CA PerBit enable=1, Macro0, CA PI delay=33
1441 11:12:54.183167
1442 11:12:54.186436 [CBTSetCACLKResult] CA Dly = 33
1443 11:12:54.186539 CS Dly: 5 (0~37)
1444 11:12:54.189483
1445 11:12:54.192735 ----->DramcWriteLeveling(PI) begin...
1446 11:12:54.192846 ==
1447 11:12:54.196216 Dram Type= 6, Freq= 0, CH_1, rank 0
1448 11:12:54.199667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1449 11:12:54.199773 ==
1450 11:12:54.202969 Write leveling (Byte 0): 25 => 25
1451 11:12:54.206170 Write leveling (Byte 1): 30 => 30
1452 11:12:54.209377 DramcWriteLeveling(PI) end<-----
1453 11:12:54.209498
1454 11:12:54.209595 ==
1455 11:12:54.212583 Dram Type= 6, Freq= 0, CH_1, rank 0
1456 11:12:54.215985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1457 11:12:54.216094 ==
1458 11:12:54.219392 [Gating] SW mode calibration
1459 11:12:54.226193 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1460 11:12:54.232480 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1461 11:12:54.236273 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1462 11:12:54.239424 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1463 11:12:54.246100 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 11:12:54.248962 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 11:12:54.252750 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 11:12:54.259005 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 11:12:54.262345 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 11:12:54.265692 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 11:12:54.272472 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 11:12:54.275814 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 11:12:54.278636 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 11:12:54.285504 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 11:12:54.288857 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 11:12:54.291964 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 11:12:54.298574 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 11:12:54.302177 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 11:12:54.305404 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1478 11:12:54.311883 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1479 11:12:54.314958 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1480 11:12:54.318574 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 11:12:54.324999 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 11:12:54.328758 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 11:12:54.331620 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 11:12:54.335418 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 11:12:54.341974 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 11:12:54.345329 0 9 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1487 11:12:54.348418 0 9 8 | B1->B0 | 2b2b 3333 | 1 0 | (1 1) (0 0)
1488 11:12:54.355325 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1489 11:12:54.358078 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1490 11:12:54.361448 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1491 11:12:54.368143 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1492 11:12:54.371465 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1493 11:12:54.374887 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1494 11:12:54.381800 0 10 4 | B1->B0 | 3232 2f2f | 0 1 | (0 0) (1 0)
1495 11:12:54.384749 0 10 8 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
1496 11:12:54.388522 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1497 11:12:54.395060 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1498 11:12:54.398237 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1499 11:12:54.401370 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1500 11:12:54.408580 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1501 11:12:54.411234 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1502 11:12:54.415053 0 11 4 | B1->B0 | 2a2a 3030 | 0 0 | (0 0) (1 1)
1503 11:12:54.421133 0 11 8 | B1->B0 | 3d3d 4343 | 1 0 | (1 1) (0 0)
1504 11:12:54.425014 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1505 11:12:54.428179 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1506 11:12:54.434621 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1507 11:12:54.437857 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1508 11:12:54.441067 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1509 11:12:54.448136 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1510 11:12:54.451455 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1511 11:12:54.454359 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 11:12:54.461436 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1513 11:12:54.464962 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 11:12:54.467692 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 11:12:54.474536 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 11:12:54.477992 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1517 11:12:54.481305 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1518 11:12:54.487839 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1519 11:12:54.490819 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1520 11:12:54.494434 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1521 11:12:54.497632 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 11:12:54.504169 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 11:12:54.508045 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 11:12:54.511266 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 11:12:54.517584 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 11:12:54.521281 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1527 11:12:54.524544 Total UI for P1: 0, mck2ui 16
1528 11:12:54.527717 best dqsien dly found for B0: ( 0, 14, 2)
1529 11:12:54.531231 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1530 11:12:54.534076 Total UI for P1: 0, mck2ui 16
1531 11:12:54.537981 best dqsien dly found for B1: ( 0, 14, 4)
1532 11:12:54.541090 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1533 11:12:54.544404 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1534 11:12:54.547719
1535 11:12:54.550944 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1536 11:12:54.554243 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1537 11:12:54.557638 [Gating] SW calibration Done
1538 11:12:54.557769 ==
1539 11:12:54.560855 Dram Type= 6, Freq= 0, CH_1, rank 0
1540 11:12:54.564121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1541 11:12:54.564217 ==
1542 11:12:54.564305 RX Vref Scan: 0
1543 11:12:54.564398
1544 11:12:54.567611 RX Vref 0 -> 0, step: 1
1545 11:12:54.567678
1546 11:12:54.570923 RX Delay -130 -> 252, step: 16
1547 11:12:54.574216 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1548 11:12:54.577580 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1549 11:12:54.583890 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1550 11:12:54.587264 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1551 11:12:54.590694 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1552 11:12:54.594039 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1553 11:12:54.597358 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1554 11:12:54.603523 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1555 11:12:54.606798 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1556 11:12:54.610768 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1557 11:12:54.613568 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1558 11:12:54.616873 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1559 11:12:54.623874 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1560 11:12:54.626841 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1561 11:12:54.630109 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1562 11:12:54.633346 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1563 11:12:54.633443 ==
1564 11:12:54.636861 Dram Type= 6, Freq= 0, CH_1, rank 0
1565 11:12:54.643802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1566 11:12:54.643919 ==
1567 11:12:54.644009 DQS Delay:
1568 11:12:54.646928 DQS0 = 0, DQS1 = 0
1569 11:12:54.647022 DQM Delay:
1570 11:12:54.647109 DQM0 = 87, DQM1 = 82
1571 11:12:54.650519 DQ Delay:
1572 11:12:54.653654 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1573 11:12:54.656834 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1574 11:12:54.660247 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1575 11:12:54.663643 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1576 11:12:54.663740
1577 11:12:54.663826
1578 11:12:54.663919 ==
1579 11:12:54.666872 Dram Type= 6, Freq= 0, CH_1, rank 0
1580 11:12:54.670197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1581 11:12:54.670267 ==
1582 11:12:54.670326
1583 11:12:54.670394
1584 11:12:54.673557 TX Vref Scan disable
1585 11:12:54.676848 == TX Byte 0 ==
1586 11:12:54.680273 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1587 11:12:54.683188 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1588 11:12:54.686627 == TX Byte 1 ==
1589 11:12:54.690043 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1590 11:12:54.693390 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1591 11:12:54.693485 ==
1592 11:12:54.696761 Dram Type= 6, Freq= 0, CH_1, rank 0
1593 11:12:54.699591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1594 11:12:54.702978 ==
1595 11:12:54.715317 TX Vref=22, minBit 0, minWin=27, winSum=439
1596 11:12:54.718168 TX Vref=24, minBit 1, minWin=27, winSum=443
1597 11:12:54.721513 TX Vref=26, minBit 2, minWin=27, winSum=449
1598 11:12:54.725297 TX Vref=28, minBit 6, minWin=27, winSum=455
1599 11:12:54.728959 TX Vref=30, minBit 0, minWin=28, winSum=455
1600 11:12:54.732329 TX Vref=32, minBit 0, minWin=27, winSum=452
1601 11:12:54.738657 [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 30
1602 11:12:54.738759
1603 11:12:54.742126 Final TX Range 1 Vref 30
1604 11:12:54.742231
1605 11:12:54.742351 ==
1606 11:12:54.745719 Dram Type= 6, Freq= 0, CH_1, rank 0
1607 11:12:54.748958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1608 11:12:54.749053 ==
1609 11:12:54.749140
1610 11:12:54.749231
1611 11:12:54.752181 TX Vref Scan disable
1612 11:12:54.755515 == TX Byte 0 ==
1613 11:12:54.758994 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1614 11:12:54.762068 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1615 11:12:54.765426 == TX Byte 1 ==
1616 11:12:54.768775 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1617 11:12:54.772075 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1618 11:12:54.772156
1619 11:12:54.775383 [DATLAT]
1620 11:12:54.775463 Freq=800, CH1 RK0
1621 11:12:54.775528
1622 11:12:54.778724 DATLAT Default: 0xa
1623 11:12:54.778804 0, 0xFFFF, sum = 0
1624 11:12:54.782056 1, 0xFFFF, sum = 0
1625 11:12:54.782138 2, 0xFFFF, sum = 0
1626 11:12:54.785501 3, 0xFFFF, sum = 0
1627 11:12:54.785584 4, 0xFFFF, sum = 0
1628 11:12:54.788711 5, 0xFFFF, sum = 0
1629 11:12:54.788812 6, 0xFFFF, sum = 0
1630 11:12:54.792252 7, 0xFFFF, sum = 0
1631 11:12:54.792352 8, 0xFFFF, sum = 0
1632 11:12:54.795615 9, 0x0, sum = 1
1633 11:12:54.795697 10, 0x0, sum = 2
1634 11:12:54.798397 11, 0x0, sum = 3
1635 11:12:54.798478 12, 0x0, sum = 4
1636 11:12:54.801937 best_step = 10
1637 11:12:54.802017
1638 11:12:54.802081 ==
1639 11:12:54.805300 Dram Type= 6, Freq= 0, CH_1, rank 0
1640 11:12:54.808725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1641 11:12:54.808808 ==
1642 11:12:54.811919 RX Vref Scan: 1
1643 11:12:54.812016
1644 11:12:54.812088 Set Vref Range= 32 -> 127
1645 11:12:54.812150
1646 11:12:54.815178 RX Vref 32 -> 127, step: 1
1647 11:12:54.815258
1648 11:12:54.818556 RX Delay -95 -> 252, step: 8
1649 11:12:54.818637
1650 11:12:54.821991 Set Vref, RX VrefLevel [Byte0]: 32
1651 11:12:54.825424 [Byte1]: 32
1652 11:12:54.825505
1653 11:12:54.828651 Set Vref, RX VrefLevel [Byte0]: 33
1654 11:12:54.831879 [Byte1]: 33
1655 11:12:54.835106
1656 11:12:54.835186 Set Vref, RX VrefLevel [Byte0]: 34
1657 11:12:54.838433 [Byte1]: 34
1658 11:12:54.842556
1659 11:12:54.842637 Set Vref, RX VrefLevel [Byte0]: 35
1660 11:12:54.845877 [Byte1]: 35
1661 11:12:54.850377
1662 11:12:54.850458 Set Vref, RX VrefLevel [Byte0]: 36
1663 11:12:54.853780 [Byte1]: 36
1664 11:12:54.857858
1665 11:12:54.857940 Set Vref, RX VrefLevel [Byte0]: 37
1666 11:12:54.861202 [Byte1]: 37
1667 11:12:54.865459
1668 11:12:54.865540 Set Vref, RX VrefLevel [Byte0]: 38
1669 11:12:54.869035 [Byte1]: 38
1670 11:12:54.872932
1671 11:12:54.873013 Set Vref, RX VrefLevel [Byte0]: 39
1672 11:12:54.876780 [Byte1]: 39
1673 11:12:54.880729
1674 11:12:54.880810 Set Vref, RX VrefLevel [Byte0]: 40
1675 11:12:54.884158 [Byte1]: 40
1676 11:12:54.888539
1677 11:12:54.888623 Set Vref, RX VrefLevel [Byte0]: 41
1678 11:12:54.891894 [Byte1]: 41
1679 11:12:54.895765
1680 11:12:54.895845 Set Vref, RX VrefLevel [Byte0]: 42
1681 11:12:54.899152 [Byte1]: 42
1682 11:12:54.903565
1683 11:12:54.903647 Set Vref, RX VrefLevel [Byte0]: 43
1684 11:12:54.907063 [Byte1]: 43
1685 11:12:54.910974
1686 11:12:54.911060 Set Vref, RX VrefLevel [Byte0]: 44
1687 11:12:54.914275 [Byte1]: 44
1688 11:12:54.918712
1689 11:12:54.918794 Set Vref, RX VrefLevel [Byte0]: 45
1690 11:12:54.922045 [Byte1]: 45
1691 11:12:54.926657
1692 11:12:54.926737 Set Vref, RX VrefLevel [Byte0]: 46
1693 11:12:54.929901 [Byte1]: 46
1694 11:12:54.933834
1695 11:12:54.933915 Set Vref, RX VrefLevel [Byte0]: 47
1696 11:12:54.937622 [Byte1]: 47
1697 11:12:54.941834
1698 11:12:54.941915 Set Vref, RX VrefLevel [Byte0]: 48
1699 11:12:54.944866 [Byte1]: 48
1700 11:12:54.949413
1701 11:12:54.949490 Set Vref, RX VrefLevel [Byte0]: 49
1702 11:12:54.952651 [Byte1]: 49
1703 11:12:54.956878
1704 11:12:54.956953 Set Vref, RX VrefLevel [Byte0]: 50
1705 11:12:54.959913 [Byte1]: 50
1706 11:12:54.964113
1707 11:12:54.964197 Set Vref, RX VrefLevel [Byte0]: 51
1708 11:12:54.967917 [Byte1]: 51
1709 11:12:54.971828
1710 11:12:54.971911 Set Vref, RX VrefLevel [Byte0]: 52
1711 11:12:54.975467 [Byte1]: 52
1712 11:12:54.979659
1713 11:12:54.979742 Set Vref, RX VrefLevel [Byte0]: 53
1714 11:12:54.982888 [Byte1]: 53
1715 11:12:54.987497
1716 11:12:54.987579 Set Vref, RX VrefLevel [Byte0]: 54
1717 11:12:54.990327 [Byte1]: 54
1718 11:12:54.994887
1719 11:12:54.994969 Set Vref, RX VrefLevel [Byte0]: 55
1720 11:12:54.998185 [Byte1]: 55
1721 11:12:55.002824
1722 11:12:55.002905 Set Vref, RX VrefLevel [Byte0]: 56
1723 11:12:55.005587 [Byte1]: 56
1724 11:12:55.010043
1725 11:12:55.010125 Set Vref, RX VrefLevel [Byte0]: 57
1726 11:12:55.013428 [Byte1]: 57
1727 11:12:55.017803
1728 11:12:55.017885 Set Vref, RX VrefLevel [Byte0]: 58
1729 11:12:55.021079 [Byte1]: 58
1730 11:12:55.025169
1731 11:12:55.025250 Set Vref, RX VrefLevel [Byte0]: 59
1732 11:12:55.028418 [Byte1]: 59
1733 11:12:55.033022
1734 11:12:55.033103 Set Vref, RX VrefLevel [Byte0]: 60
1735 11:12:55.035945 [Byte1]: 60
1736 11:12:55.040326
1737 11:12:55.040408 Set Vref, RX VrefLevel [Byte0]: 61
1738 11:12:55.043648 [Byte1]: 61
1739 11:12:55.047902
1740 11:12:55.048037 Set Vref, RX VrefLevel [Byte0]: 62
1741 11:12:55.051303 [Byte1]: 62
1742 11:12:55.055676
1743 11:12:55.055764 Set Vref, RX VrefLevel [Byte0]: 63
1744 11:12:55.059111 [Byte1]: 63
1745 11:12:55.063375
1746 11:12:55.063443 Set Vref, RX VrefLevel [Byte0]: 64
1747 11:12:55.066505 [Byte1]: 64
1748 11:12:55.070693
1749 11:12:55.070761 Set Vref, RX VrefLevel [Byte0]: 65
1750 11:12:55.074381 [Byte1]: 65
1751 11:12:55.078245
1752 11:12:55.078320 Set Vref, RX VrefLevel [Byte0]: 66
1753 11:12:55.081584 [Byte1]: 66
1754 11:12:55.086132
1755 11:12:55.086236 Set Vref, RX VrefLevel [Byte0]: 67
1756 11:12:55.089455 [Byte1]: 67
1757 11:12:55.093351
1758 11:12:55.093439 Set Vref, RX VrefLevel [Byte0]: 68
1759 11:12:55.096686 [Byte1]: 68
1760 11:12:55.101140
1761 11:12:55.101209 Set Vref, RX VrefLevel [Byte0]: 69
1762 11:12:55.104665 [Byte1]: 69
1763 11:12:55.108604
1764 11:12:55.108688 Set Vref, RX VrefLevel [Byte0]: 70
1765 11:12:55.112166 [Byte1]: 70
1766 11:12:55.116466
1767 11:12:55.116550 Set Vref, RX VrefLevel [Byte0]: 71
1768 11:12:55.119395 [Byte1]: 71
1769 11:12:55.123689
1770 11:12:55.123769 Set Vref, RX VrefLevel [Byte0]: 72
1771 11:12:55.127042 [Byte1]: 72
1772 11:12:55.131587
1773 11:12:55.131668 Final RX Vref Byte 0 = 58 to rank0
1774 11:12:55.135062 Final RX Vref Byte 1 = 58 to rank0
1775 11:12:55.138001 Final RX Vref Byte 0 = 58 to rank1
1776 11:12:55.141461 Final RX Vref Byte 1 = 58 to rank1==
1777 11:12:55.145131 Dram Type= 6, Freq= 0, CH_1, rank 0
1778 11:12:55.151637 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1779 11:12:55.151719 ==
1780 11:12:55.151784 DQS Delay:
1781 11:12:55.151844 DQS0 = 0, DQS1 = 0
1782 11:12:55.154686 DQM Delay:
1783 11:12:55.154768 DQM0 = 86, DQM1 = 80
1784 11:12:55.158088 DQ Delay:
1785 11:12:55.161319 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1786 11:12:55.164593 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
1787 11:12:55.167840 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =72
1788 11:12:55.171518 DQ12 =88, DQ13 =92, DQ14 =84, DQ15 =88
1789 11:12:55.171600
1790 11:12:55.171664
1791 11:12:55.177822 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d2f, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
1792 11:12:55.181440 CH1 RK0: MR19=606, MR18=1D2F
1793 11:12:55.187913 CH1_RK0: MR19=0x606, MR18=0x1D2F, DQSOSC=397, MR23=63, INC=93, DEC=62
1794 11:12:55.188020
1795 11:12:55.191274 ----->DramcWriteLeveling(PI) begin...
1796 11:12:55.191381 ==
1797 11:12:55.194762 Dram Type= 6, Freq= 0, CH_1, rank 1
1798 11:12:55.198251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1799 11:12:55.198356 ==
1800 11:12:55.201166 Write leveling (Byte 0): 25 => 25
1801 11:12:55.204521 Write leveling (Byte 1): 29 => 29
1802 11:12:55.207827 DramcWriteLeveling(PI) end<-----
1803 11:12:55.207930
1804 11:12:55.208019 ==
1805 11:12:55.211238 Dram Type= 6, Freq= 0, CH_1, rank 1
1806 11:12:55.214723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1807 11:12:55.214805 ==
1808 11:12:55.217935 [Gating] SW mode calibration
1809 11:12:55.224723 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1810 11:12:55.230686 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1811 11:12:55.234130 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1812 11:12:55.240890 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1813 11:12:55.244367 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1814 11:12:55.247705 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 11:12:55.254126 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 11:12:55.257406 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 11:12:55.260813 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 11:12:55.263970 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 11:12:55.270579 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 11:12:55.273872 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 11:12:55.277567 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 11:12:55.283943 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 11:12:55.287067 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 11:12:55.290760 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 11:12:55.297148 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 11:12:55.300276 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 11:12:55.304150 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1828 11:12:55.310293 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1829 11:12:55.313714 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 11:12:55.317077 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 11:12:55.323369 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 11:12:55.326708 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 11:12:55.330098 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 11:12:55.336835 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 11:12:55.340097 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 11:12:55.343496 0 9 4 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
1837 11:12:55.350281 0 9 8 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
1838 11:12:55.353584 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1839 11:12:55.356779 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1840 11:12:55.363369 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1841 11:12:55.366743 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1842 11:12:55.369958 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1843 11:12:55.376461 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1844 11:12:55.379634 0 10 4 | B1->B0 | 3434 2d2d | 1 0 | (1 0) (1 0)
1845 11:12:55.383579 0 10 8 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1846 11:12:55.389982 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 11:12:55.393434 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 11:12:55.396456 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 11:12:55.402821 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 11:12:55.406396 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 11:12:55.409685 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 11:12:55.416559 0 11 4 | B1->B0 | 2626 3e3e | 0 1 | (0 0) (0 0)
1853 11:12:55.419979 0 11 8 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
1854 11:12:55.422724 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1855 11:12:55.429597 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1856 11:12:55.432929 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1857 11:12:55.436072 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1858 11:12:55.442830 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1859 11:12:55.446079 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1860 11:12:55.449562 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1861 11:12:55.455781 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1862 11:12:55.459062 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 11:12:55.462329 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 11:12:55.468819 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 11:12:55.472723 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 11:12:55.475939 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 11:12:55.482118 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 11:12:55.485923 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 11:12:55.488751 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 11:12:55.495618 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1871 11:12:55.499002 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1872 11:12:55.502102 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1873 11:12:55.509091 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 11:12:55.512105 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 11:12:55.515417 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 11:12:55.522283 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1877 11:12:55.522365 Total UI for P1: 0, mck2ui 16
1878 11:12:55.525287 best dqsien dly found for B0: ( 0, 14, 2)
1879 11:12:55.531826 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1880 11:12:55.535213 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1881 11:12:55.538529 Total UI for P1: 0, mck2ui 16
1882 11:12:55.541704 best dqsien dly found for B1: ( 0, 14, 6)
1883 11:12:55.545188 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1884 11:12:55.548629 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1885 11:12:55.548711
1886 11:12:55.552106 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1887 11:12:55.555369 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1888 11:12:55.558774 [Gating] SW calibration Done
1889 11:12:55.558855 ==
1890 11:12:55.562165 Dram Type= 6, Freq= 0, CH_1, rank 1
1891 11:12:55.568839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1892 11:12:55.568920 ==
1893 11:12:55.568985 RX Vref Scan: 0
1894 11:12:55.569043
1895 11:12:55.571942 RX Vref 0 -> 0, step: 1
1896 11:12:55.572070
1897 11:12:55.575270 RX Delay -130 -> 252, step: 16
1898 11:12:55.578492 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1899 11:12:55.581599 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1900 11:12:55.585211 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1901 11:12:55.591740 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1902 11:12:55.595240 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1903 11:12:55.598254 iDelay=206, Bit 5, Center 85 (-34 ~ 205) 240
1904 11:12:55.601574 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1905 11:12:55.605432 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1906 11:12:55.608178 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1907 11:12:55.615183 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1908 11:12:55.618231 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1909 11:12:55.621519 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1910 11:12:55.624843 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1911 11:12:55.631724 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1912 11:12:55.635011 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1913 11:12:55.638493 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1914 11:12:55.638577 ==
1915 11:12:55.641293 Dram Type= 6, Freq= 0, CH_1, rank 1
1916 11:12:55.645115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1917 11:12:55.645200 ==
1918 11:12:55.647931 DQS Delay:
1919 11:12:55.648015 DQS0 = 0, DQS1 = 0
1920 11:12:55.651259 DQM Delay:
1921 11:12:55.651343 DQM0 = 83, DQM1 = 80
1922 11:12:55.651427 DQ Delay:
1923 11:12:55.654626 DQ0 =85, DQ1 =85, DQ2 =69, DQ3 =85
1924 11:12:55.658400 DQ4 =85, DQ5 =85, DQ6 =85, DQ7 =85
1925 11:12:55.661255 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1926 11:12:55.664559 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1927 11:12:55.664643
1928 11:12:55.664726
1929 11:12:55.667934 ==
1930 11:12:55.668019 Dram Type= 6, Freq= 0, CH_1, rank 1
1931 11:12:55.674565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1932 11:12:55.674650 ==
1933 11:12:55.674733
1934 11:12:55.674813
1935 11:12:55.678404 TX Vref Scan disable
1936 11:12:55.678487 == TX Byte 0 ==
1937 11:12:55.681513 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1938 11:12:55.687930 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1939 11:12:55.688016 == TX Byte 1 ==
1940 11:12:55.694524 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1941 11:12:55.697762 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1942 11:12:55.697846 ==
1943 11:12:55.700909 Dram Type= 6, Freq= 0, CH_1, rank 1
1944 11:12:55.704401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1945 11:12:55.704485 ==
1946 11:12:55.717884 TX Vref=22, minBit 3, minWin=26, winSum=442
1947 11:12:55.721505 TX Vref=24, minBit 1, minWin=27, winSum=447
1948 11:12:55.724601 TX Vref=26, minBit 1, minWin=27, winSum=451
1949 11:12:55.727950 TX Vref=28, minBit 6, minWin=27, winSum=453
1950 11:12:55.731327 TX Vref=30, minBit 0, minWin=28, winSum=456
1951 11:12:55.738216 TX Vref=32, minBit 0, minWin=27, winSum=452
1952 11:12:55.740968 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 30
1953 11:12:55.741047
1954 11:12:55.744541 Final TX Range 1 Vref 30
1955 11:12:55.744623
1956 11:12:55.744686 ==
1957 11:12:55.748174 Dram Type= 6, Freq= 0, CH_1, rank 1
1958 11:12:55.750963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1959 11:12:55.754163 ==
1960 11:12:55.754239
1961 11:12:55.754318
1962 11:12:55.754411 TX Vref Scan disable
1963 11:12:55.757720 == TX Byte 0 ==
1964 11:12:55.761488 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1965 11:12:55.767718 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1966 11:12:55.767792 == TX Byte 1 ==
1967 11:12:55.771335 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1968 11:12:55.777962 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1969 11:12:55.778039
1970 11:12:55.778103 [DATLAT]
1971 11:12:55.778162 Freq=800, CH1 RK1
1972 11:12:55.778220
1973 11:12:55.781484 DATLAT Default: 0xa
1974 11:12:55.781549 0, 0xFFFF, sum = 0
1975 11:12:55.784935 1, 0xFFFF, sum = 0
1976 11:12:55.785019 2, 0xFFFF, sum = 0
1977 11:12:55.788004 3, 0xFFFF, sum = 0
1978 11:12:55.791369 4, 0xFFFF, sum = 0
1979 11:12:55.791452 5, 0xFFFF, sum = 0
1980 11:12:55.794430 6, 0xFFFF, sum = 0
1981 11:12:55.794536 7, 0xFFFF, sum = 0
1982 11:12:55.797598 8, 0xFFFF, sum = 0
1983 11:12:55.797681 9, 0x0, sum = 1
1984 11:12:55.801073 10, 0x0, sum = 2
1985 11:12:55.801156 11, 0x0, sum = 3
1986 11:12:55.801222 12, 0x0, sum = 4
1987 11:12:55.804268 best_step = 10
1988 11:12:55.804349
1989 11:12:55.804451 ==
1990 11:12:55.807815 Dram Type= 6, Freq= 0, CH_1, rank 1
1991 11:12:55.811015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1992 11:12:55.811097 ==
1993 11:12:55.814250 RX Vref Scan: 0
1994 11:12:55.814348
1995 11:12:55.817593 RX Vref 0 -> 0, step: 1
1996 11:12:55.817665
1997 11:12:55.817726 RX Delay -95 -> 252, step: 8
1998 11:12:55.824472 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
1999 11:12:55.828080 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
2000 11:12:55.831105 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2001 11:12:55.834480 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
2002 11:12:55.837882 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2003 11:12:55.844818 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2004 11:12:55.848061 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
2005 11:12:55.851402 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2006 11:12:55.854721 iDelay=209, Bit 8, Center 72 (-39 ~ 184) 224
2007 11:12:55.858046 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2008 11:12:55.864244 iDelay=209, Bit 10, Center 84 (-31 ~ 200) 232
2009 11:12:55.867587 iDelay=209, Bit 11, Center 76 (-39 ~ 192) 232
2010 11:12:55.871013 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2011 11:12:55.874713 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2012 11:12:55.881256 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2013 11:12:55.884532 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2014 11:12:55.884614 ==
2015 11:12:55.887761 Dram Type= 6, Freq= 0, CH_1, rank 1
2016 11:12:55.891031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2017 11:12:55.891113 ==
2018 11:12:55.894214 DQS Delay:
2019 11:12:55.894311 DQS0 = 0, DQS1 = 0
2020 11:12:55.894390 DQM Delay:
2021 11:12:55.897982 DQM0 = 87, DQM1 = 82
2022 11:12:55.898063 DQ Delay:
2023 11:12:55.901132 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =84
2024 11:12:55.904539 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
2025 11:12:55.907837 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =76
2026 11:12:55.911034 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
2027 11:12:55.911117
2028 11:12:55.911181
2029 11:12:55.920979 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a36, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 403 ps
2030 11:12:55.921063 CH1 RK1: MR19=606, MR18=1A36
2031 11:12:55.927215 CH1_RK1: MR19=0x606, MR18=0x1A36, DQSOSC=396, MR23=63, INC=94, DEC=62
2032 11:12:55.931113 [RxdqsGatingPostProcess] freq 800
2033 11:12:55.937499 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2034 11:12:55.940969 Pre-setting of DQS Precalculation
2035 11:12:55.943791 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2036 11:12:55.950987 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2037 11:12:55.960867 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2038 11:12:55.960950
2039 11:12:55.961014
2040 11:12:55.961072 [Calibration Summary] 1600 Mbps
2041 11:12:55.963814 CH 0, Rank 0
2042 11:12:55.967181 SW Impedance : PASS
2043 11:12:55.967251 DUTY Scan : NO K
2044 11:12:55.970506 ZQ Calibration : PASS
2045 11:12:55.970581 Jitter Meter : NO K
2046 11:12:55.973934 CBT Training : PASS
2047 11:12:55.977410 Write leveling : PASS
2048 11:12:55.977490 RX DQS gating : PASS
2049 11:12:55.980696 RX DQ/DQS(RDDQC) : PASS
2050 11:12:55.983878 TX DQ/DQS : PASS
2051 11:12:55.983978 RX DATLAT : PASS
2052 11:12:55.987098 RX DQ/DQS(Engine): PASS
2053 11:12:55.990458 TX OE : NO K
2054 11:12:55.990532 All Pass.
2055 11:12:55.990601
2056 11:12:55.990660 CH 0, Rank 1
2057 11:12:55.993884 SW Impedance : PASS
2058 11:12:55.997083 DUTY Scan : NO K
2059 11:12:55.997157 ZQ Calibration : PASS
2060 11:12:56.000207 Jitter Meter : NO K
2061 11:12:56.003279 CBT Training : PASS
2062 11:12:56.003350 Write leveling : PASS
2063 11:12:56.006572 RX DQS gating : PASS
2064 11:12:56.010565 RX DQ/DQS(RDDQC) : PASS
2065 11:12:56.010650 TX DQ/DQS : PASS
2066 11:12:56.013308 RX DATLAT : PASS
2067 11:12:56.017002 RX DQ/DQS(Engine): PASS
2068 11:12:56.017073 TX OE : NO K
2069 11:12:56.020300 All Pass.
2070 11:12:56.020377
2071 11:12:56.020439 CH 1, Rank 0
2072 11:12:56.023553 SW Impedance : PASS
2073 11:12:56.023624 DUTY Scan : NO K
2074 11:12:56.026900 ZQ Calibration : PASS
2075 11:12:56.029933 Jitter Meter : NO K
2076 11:12:56.030002 CBT Training : PASS
2077 11:12:56.033090 Write leveling : PASS
2078 11:12:56.036479 RX DQS gating : PASS
2079 11:12:56.036557 RX DQ/DQS(RDDQC) : PASS
2080 11:12:56.040168 TX DQ/DQS : PASS
2081 11:12:56.040239 RX DATLAT : PASS
2082 11:12:56.043134 RX DQ/DQS(Engine): PASS
2083 11:12:56.046597 TX OE : NO K
2084 11:12:56.046669 All Pass.
2085 11:12:56.046737
2086 11:12:56.046795 CH 1, Rank 1
2087 11:12:56.049986 SW Impedance : PASS
2088 11:12:56.053188 DUTY Scan : NO K
2089 11:12:56.053258 ZQ Calibration : PASS
2090 11:12:56.056693 Jitter Meter : NO K
2091 11:12:56.059988 CBT Training : PASS
2092 11:12:56.060110 Write leveling : PASS
2093 11:12:56.063373 RX DQS gating : PASS
2094 11:12:56.066578 RX DQ/DQS(RDDQC) : PASS
2095 11:12:56.066653 TX DQ/DQS : PASS
2096 11:12:56.070014 RX DATLAT : PASS
2097 11:12:56.073172 RX DQ/DQS(Engine): PASS
2098 11:12:56.073268 TX OE : NO K
2099 11:12:56.076496 All Pass.
2100 11:12:56.076567
2101 11:12:56.076626 DramC Write-DBI off
2102 11:12:56.079986 PER_BANK_REFRESH: Hybrid Mode
2103 11:12:56.080099 TX_TRACKING: ON
2104 11:12:56.082790 [GetDramInforAfterCalByMRR] Vendor 6.
2105 11:12:56.089887 [GetDramInforAfterCalByMRR] Revision 606.
2106 11:12:56.092682 [GetDramInforAfterCalByMRR] Revision 2 0.
2107 11:12:56.092796 MR0 0x3b3b
2108 11:12:56.092880 MR8 0x5151
2109 11:12:56.096404 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2110 11:12:56.096495
2111 11:12:56.099796 MR0 0x3b3b
2112 11:12:56.099976 MR8 0x5151
2113 11:12:56.103127 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2114 11:12:56.103236
2115 11:12:56.113054 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2116 11:12:56.115875 [FAST_K] Save calibration result to emmc
2117 11:12:56.119501 [FAST_K] Save calibration result to emmc
2118 11:12:56.122627 dram_init: config_dvfs: 1
2119 11:12:56.125968 dramc_set_vcore_voltage set vcore to 662500
2120 11:12:56.129366 Read voltage for 1200, 2
2121 11:12:56.129483 Vio18 = 0
2122 11:12:56.129585 Vcore = 662500
2123 11:12:56.132773 Vdram = 0
2124 11:12:56.132866 Vddq = 0
2125 11:12:56.132931 Vmddr = 0
2126 11:12:56.139081 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2127 11:12:56.142439 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2128 11:12:56.146160 MEM_TYPE=3, freq_sel=15
2129 11:12:56.149141 sv_algorithm_assistance_LP4_1600
2130 11:12:56.152472 ============ PULL DRAM RESETB DOWN ============
2131 11:12:56.155854 ========== PULL DRAM RESETB DOWN end =========
2132 11:12:56.162666 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2133 11:12:56.165971 ===================================
2134 11:12:56.169491 LPDDR4 DRAM CONFIGURATION
2135 11:12:56.172183 ===================================
2136 11:12:56.172277 EX_ROW_EN[0] = 0x0
2137 11:12:56.175700 EX_ROW_EN[1] = 0x0
2138 11:12:56.175815 LP4Y_EN = 0x0
2139 11:12:56.179181 WORK_FSP = 0x0
2140 11:12:56.179291 WL = 0x4
2141 11:12:56.182270 RL = 0x4
2142 11:12:56.182348 BL = 0x2
2143 11:12:56.185616 RPST = 0x0
2144 11:12:56.185691 RD_PRE = 0x0
2145 11:12:56.189275 WR_PRE = 0x1
2146 11:12:56.189371 WR_PST = 0x0
2147 11:12:56.192291 DBI_WR = 0x0
2148 11:12:56.192369 DBI_RD = 0x0
2149 11:12:56.195560 OTF = 0x1
2150 11:12:56.198723 ===================================
2151 11:12:56.202040 ===================================
2152 11:12:56.202121 ANA top config
2153 11:12:56.205412 ===================================
2154 11:12:56.208966 DLL_ASYNC_EN = 0
2155 11:12:56.212209 ALL_SLAVE_EN = 0
2156 11:12:56.215516 NEW_RANK_MODE = 1
2157 11:12:56.215596 DLL_IDLE_MODE = 1
2158 11:12:56.218778 LP45_APHY_COMB_EN = 1
2159 11:12:56.221942 TX_ODT_DIS = 1
2160 11:12:56.225149 NEW_8X_MODE = 1
2161 11:12:56.228325 ===================================
2162 11:12:56.231652 ===================================
2163 11:12:56.234976 data_rate = 2400
2164 11:12:56.238830 CKR = 1
2165 11:12:56.238917 DQ_P2S_RATIO = 8
2166 11:12:56.242208 ===================================
2167 11:12:56.245130 CA_P2S_RATIO = 8
2168 11:12:56.248438 DQ_CA_OPEN = 0
2169 11:12:56.251627 DQ_SEMI_OPEN = 0
2170 11:12:56.255147 CA_SEMI_OPEN = 0
2171 11:12:56.258587 CA_FULL_RATE = 0
2172 11:12:56.258666 DQ_CKDIV4_EN = 0
2173 11:12:56.261922 CA_CKDIV4_EN = 0
2174 11:12:56.265378 CA_PREDIV_EN = 0
2175 11:12:56.268653 PH8_DLY = 17
2176 11:12:56.271785 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2177 11:12:56.275189 DQ_AAMCK_DIV = 4
2178 11:12:56.275291 CA_AAMCK_DIV = 4
2179 11:12:56.278504 CA_ADMCK_DIV = 4
2180 11:12:56.281862 DQ_TRACK_CA_EN = 0
2181 11:12:56.285186 CA_PICK = 1200
2182 11:12:56.288129 CA_MCKIO = 1200
2183 11:12:56.291463 MCKIO_SEMI = 0
2184 11:12:56.295220 PLL_FREQ = 2366
2185 11:12:56.295304 DQ_UI_PI_RATIO = 32
2186 11:12:56.298740 CA_UI_PI_RATIO = 0
2187 11:12:56.301944 ===================================
2188 11:12:56.305168 ===================================
2189 11:12:56.307973 memory_type:LPDDR4
2190 11:12:56.311612 GP_NUM : 10
2191 11:12:56.311709 SRAM_EN : 1
2192 11:12:56.314977 MD32_EN : 0
2193 11:12:56.318100 ===================================
2194 11:12:56.321358 [ANA_INIT] >>>>>>>>>>>>>>
2195 11:12:56.321441 <<<<<< [CONFIGURE PHASE]: ANA_TX
2196 11:12:56.324795 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2197 11:12:56.327940 ===================================
2198 11:12:56.331818 data_rate = 2400,PCW = 0X5b00
2199 11:12:56.334513 ===================================
2200 11:12:56.337866 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2201 11:12:56.344493 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2202 11:12:56.351198 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2203 11:12:56.354662 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2204 11:12:56.357775 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2205 11:12:56.360932 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2206 11:12:56.364763 [ANA_INIT] flow start
2207 11:12:56.364843 [ANA_INIT] PLL >>>>>>>>
2208 11:12:56.368063 [ANA_INIT] PLL <<<<<<<<
2209 11:12:56.371419 [ANA_INIT] MIDPI >>>>>>>>
2210 11:12:56.374749 [ANA_INIT] MIDPI <<<<<<<<
2211 11:12:56.374829 [ANA_INIT] DLL >>>>>>>>
2212 11:12:56.377628 [ANA_INIT] DLL <<<<<<<<
2213 11:12:56.377700 [ANA_INIT] flow end
2214 11:12:56.384411 ============ LP4 DIFF to SE enter ============
2215 11:12:56.387663 ============ LP4 DIFF to SE exit ============
2216 11:12:56.391103 [ANA_INIT] <<<<<<<<<<<<<
2217 11:12:56.394600 [Flow] Enable top DCM control >>>>>
2218 11:12:56.397425 [Flow] Enable top DCM control <<<<<
2219 11:12:56.401180 Enable DLL master slave shuffle
2220 11:12:56.404491 ==============================================================
2221 11:12:56.407907 Gating Mode config
2222 11:12:56.410826 ==============================================================
2223 11:12:56.414157 Config description:
2224 11:12:56.424387 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2225 11:12:56.430841 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2226 11:12:56.434840 SELPH_MODE 0: By rank 1: By Phase
2227 11:12:56.441225 ==============================================================
2228 11:12:56.444108 GAT_TRACK_EN = 1
2229 11:12:56.447783 RX_GATING_MODE = 2
2230 11:12:56.450932 RX_GATING_TRACK_MODE = 2
2231 11:12:56.454328 SELPH_MODE = 1
2232 11:12:56.454415 PICG_EARLY_EN = 1
2233 11:12:56.457764 VALID_LAT_VALUE = 1
2234 11:12:56.464182 ==============================================================
2235 11:12:56.467600 Enter into Gating configuration >>>>
2236 11:12:56.470919 Exit from Gating configuration <<<<
2237 11:12:56.474186 Enter into DVFS_PRE_config >>>>>
2238 11:12:56.483981 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2239 11:12:56.487498 Exit from DVFS_PRE_config <<<<<
2240 11:12:56.490944 Enter into PICG configuration >>>>
2241 11:12:56.493709 Exit from PICG configuration <<<<
2242 11:12:56.497109 [RX_INPUT] configuration >>>>>
2243 11:12:56.500677 [RX_INPUT] configuration <<<<<
2244 11:12:56.503716 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2245 11:12:56.510405 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2246 11:12:56.517432 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2247 11:12:56.523977 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2248 11:12:56.530935 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2249 11:12:56.533924 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2250 11:12:56.540579 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2251 11:12:56.543576 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2252 11:12:56.546988 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2253 11:12:56.550334 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2254 11:12:56.557100 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2255 11:12:56.560525 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2256 11:12:56.563982 ===================================
2257 11:12:56.567388 LPDDR4 DRAM CONFIGURATION
2258 11:12:56.570491 ===================================
2259 11:12:56.570608 EX_ROW_EN[0] = 0x0
2260 11:12:56.573523 EX_ROW_EN[1] = 0x0
2261 11:12:56.573610 LP4Y_EN = 0x0
2262 11:12:56.576845 WORK_FSP = 0x0
2263 11:12:56.576929 WL = 0x4
2264 11:12:56.580664 RL = 0x4
2265 11:12:56.580748 BL = 0x2
2266 11:12:56.583873 RPST = 0x0
2267 11:12:56.583957 RD_PRE = 0x0
2268 11:12:56.586744 WR_PRE = 0x1
2269 11:12:56.590068 WR_PST = 0x0
2270 11:12:56.590153 DBI_WR = 0x0
2271 11:12:56.593425 DBI_RD = 0x0
2272 11:12:56.593507 OTF = 0x1
2273 11:12:56.596783 ===================================
2274 11:12:56.600212 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2275 11:12:56.606687 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2276 11:12:56.609963 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2277 11:12:56.613434 ===================================
2278 11:12:56.616918 LPDDR4 DRAM CONFIGURATION
2279 11:12:56.620476 ===================================
2280 11:12:56.620563 EX_ROW_EN[0] = 0x10
2281 11:12:56.623501 EX_ROW_EN[1] = 0x0
2282 11:12:56.623594 LP4Y_EN = 0x0
2283 11:12:56.626548 WORK_FSP = 0x0
2284 11:12:56.626631 WL = 0x4
2285 11:12:56.630455 RL = 0x4
2286 11:12:56.630527 BL = 0x2
2287 11:12:56.633572 RPST = 0x0
2288 11:12:56.633667 RD_PRE = 0x0
2289 11:12:56.636960 WR_PRE = 0x1
2290 11:12:56.637042 WR_PST = 0x0
2291 11:12:56.640152 DBI_WR = 0x0
2292 11:12:56.640223 DBI_RD = 0x0
2293 11:12:56.643451 OTF = 0x1
2294 11:12:56.646794 ===================================
2295 11:12:56.653444 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2296 11:12:56.653539 ==
2297 11:12:56.656819 Dram Type= 6, Freq= 0, CH_0, rank 0
2298 11:12:56.659657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2299 11:12:56.659730 ==
2300 11:12:56.663096 [Duty_Offset_Calibration]
2301 11:12:56.663170 B0:2 B1:0 CA:4
2302 11:12:56.663239
2303 11:12:56.666428 [DutyScan_Calibration_Flow] k_type=0
2304 11:12:56.676631
2305 11:12:56.676738 ==CLK 0==
2306 11:12:56.679657 Final CLK duty delay cell = -4
2307 11:12:56.682956 [-4] MAX Duty = 5031%(X100), DQS PI = 14
2308 11:12:56.686715 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2309 11:12:56.689976 [-4] AVG Duty = 4937%(X100)
2310 11:12:56.690055
2311 11:12:56.693455 CH0 CLK Duty spec in!! Max-Min= 187%
2312 11:12:56.696216 [DutyScan_Calibration_Flow] ====Done====
2313 11:12:56.696286
2314 11:12:56.699626 [DutyScan_Calibration_Flow] k_type=1
2315 11:12:56.716060
2316 11:12:56.716215 ==DQS 0 ==
2317 11:12:56.719326 Final DQS duty delay cell = 0
2318 11:12:56.722830 [0] MAX Duty = 5156%(X100), DQS PI = 18
2319 11:12:56.726107 [0] MIN Duty = 5093%(X100), DQS PI = 2
2320 11:12:56.729280 [0] AVG Duty = 5124%(X100)
2321 11:12:56.729387
2322 11:12:56.729453 ==DQS 1 ==
2323 11:12:56.732893 Final DQS duty delay cell = 0
2324 11:12:56.736174 [0] MAX Duty = 5125%(X100), DQS PI = 4
2325 11:12:56.739385 [0] MIN Duty = 5000%(X100), DQS PI = 0
2326 11:12:56.742608 [0] AVG Duty = 5062%(X100)
2327 11:12:56.742687
2328 11:12:56.746244 CH0 DQS 0 Duty spec in!! Max-Min= 63%
2329 11:12:56.746322
2330 11:12:56.749440 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2331 11:12:56.752800 [DutyScan_Calibration_Flow] ====Done====
2332 11:12:56.752880
2333 11:12:56.756131 [DutyScan_Calibration_Flow] k_type=3
2334 11:12:56.772328
2335 11:12:56.772467 ==DQM 0 ==
2336 11:12:56.775666 Final DQM duty delay cell = 0
2337 11:12:56.778999 [0] MAX Duty = 5093%(X100), DQS PI = 18
2338 11:12:56.782229 [0] MIN Duty = 4844%(X100), DQS PI = 56
2339 11:12:56.785645 [0] AVG Duty = 4968%(X100)
2340 11:12:56.785750
2341 11:12:56.785854 ==DQM 1 ==
2342 11:12:56.788912 Final DQM duty delay cell = 0
2343 11:12:56.792662 [0] MAX Duty = 4969%(X100), DQS PI = 0
2344 11:12:56.795384 [0] MIN Duty = 4876%(X100), DQS PI = 20
2345 11:12:56.798730 [0] AVG Duty = 4922%(X100)
2346 11:12:56.798807
2347 11:12:56.802141 CH0 DQM 0 Duty spec in!! Max-Min= 249%
2348 11:12:56.802232
2349 11:12:56.805583 CH0 DQM 1 Duty spec in!! Max-Min= 93%
2350 11:12:56.809159 [DutyScan_Calibration_Flow] ====Done====
2351 11:12:56.809248
2352 11:12:56.812402 [DutyScan_Calibration_Flow] k_type=2
2353 11:12:56.828626
2354 11:12:56.828767 ==DQ 0 ==
2355 11:12:56.831995 Final DQ duty delay cell = 0
2356 11:12:56.835289 [0] MAX Duty = 5125%(X100), DQS PI = 18
2357 11:12:56.839048 [0] MIN Duty = 5000%(X100), DQS PI = 8
2358 11:12:56.839141 [0] AVG Duty = 5062%(X100)
2359 11:12:56.839204
2360 11:12:56.842222 ==DQ 1 ==
2361 11:12:56.845614 Final DQ duty delay cell = 0
2362 11:12:56.848949 [0] MAX Duty = 5125%(X100), DQS PI = 4
2363 11:12:56.852563 [0] MIN Duty = 4938%(X100), DQS PI = 16
2364 11:12:56.852653 [0] AVG Duty = 5031%(X100)
2365 11:12:56.852719
2366 11:12:56.855546 CH0 DQ 0 Duty spec in!! Max-Min= 125%
2367 11:12:56.855620
2368 11:12:56.862313 CH0 DQ 1 Duty spec in!! Max-Min= 187%
2369 11:12:56.865491 [DutyScan_Calibration_Flow] ====Done====
2370 11:12:56.865572 ==
2371 11:12:56.868948 Dram Type= 6, Freq= 0, CH_1, rank 0
2372 11:12:56.872256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2373 11:12:56.872363 ==
2374 11:12:56.875647 [Duty_Offset_Calibration]
2375 11:12:56.875735 B0:0 B1:-1 CA:3
2376 11:12:56.875801
2377 11:12:56.878468 [DutyScan_Calibration_Flow] k_type=0
2378 11:12:56.888257
2379 11:12:56.888413 ==CLK 0==
2380 11:12:56.891319 Final CLK duty delay cell = -4
2381 11:12:56.894756 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2382 11:12:56.897877 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2383 11:12:56.901195 [-4] AVG Duty = 4938%(X100)
2384 11:12:56.901278
2385 11:12:56.904706 CH1 CLK Duty spec in!! Max-Min= 124%
2386 11:12:56.907721 [DutyScan_Calibration_Flow] ====Done====
2387 11:12:56.907807
2388 11:12:56.911392 [DutyScan_Calibration_Flow] k_type=1
2389 11:12:56.926653
2390 11:12:56.926837 ==DQS 0 ==
2391 11:12:56.929941 Final DQS duty delay cell = 0
2392 11:12:56.933271 [0] MAX Duty = 5187%(X100), DQS PI = 18
2393 11:12:56.936566 [0] MIN Duty = 4907%(X100), DQS PI = 38
2394 11:12:56.940286 [0] AVG Duty = 5047%(X100)
2395 11:12:56.940392
2396 11:12:56.940461 ==DQS 1 ==
2397 11:12:56.943537 Final DQS duty delay cell = -4
2398 11:12:56.946746 [-4] MAX Duty = 5000%(X100), DQS PI = 32
2399 11:12:56.950070 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2400 11:12:56.953288 [-4] AVG Duty = 4937%(X100)
2401 11:12:56.953378
2402 11:12:56.956535 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2403 11:12:56.956626
2404 11:12:56.959758 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2405 11:12:56.963073 [DutyScan_Calibration_Flow] ====Done====
2406 11:12:56.963163
2407 11:12:56.966498 [DutyScan_Calibration_Flow] k_type=3
2408 11:12:56.983926
2409 11:12:56.984085 ==DQM 0 ==
2410 11:12:56.986691 Final DQM duty delay cell = 0
2411 11:12:56.990022 [0] MAX Duty = 5031%(X100), DQS PI = 28
2412 11:12:56.993393 [0] MIN Duty = 4813%(X100), DQS PI = 38
2413 11:12:56.993486 [0] AVG Duty = 4922%(X100)
2414 11:12:56.997038
2415 11:12:56.997154 ==DQM 1 ==
2416 11:12:57.000040 Final DQM duty delay cell = 0
2417 11:12:57.003696 [0] MAX Duty = 5000%(X100), DQS PI = 34
2418 11:12:57.006907 [0] MIN Duty = 4844%(X100), DQS PI = 0
2419 11:12:57.006997 [0] AVG Duty = 4922%(X100)
2420 11:12:57.010389
2421 11:12:57.013651 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2422 11:12:57.013747
2423 11:12:57.017009 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2424 11:12:57.020402 [DutyScan_Calibration_Flow] ====Done====
2425 11:12:57.020533
2426 11:12:57.023567 [DutyScan_Calibration_Flow] k_type=2
2427 11:12:57.039202
2428 11:12:57.039348 ==DQ 0 ==
2429 11:12:57.042401 Final DQ duty delay cell = -4
2430 11:12:57.046009 [-4] MAX Duty = 5031%(X100), DQS PI = 30
2431 11:12:57.049147 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2432 11:12:57.052505 [-4] AVG Duty = 4937%(X100)
2433 11:12:57.052596
2434 11:12:57.052662 ==DQ 1 ==
2435 11:12:57.055707 Final DQ duty delay cell = 0
2436 11:12:57.058882 [0] MAX Duty = 5031%(X100), DQS PI = 10
2437 11:12:57.062188 [0] MIN Duty = 4844%(X100), DQS PI = 0
2438 11:12:57.065463 [0] AVG Duty = 4937%(X100)
2439 11:12:57.065607
2440 11:12:57.068833 CH1 DQ 0 Duty spec in!! Max-Min= 187%
2441 11:12:57.068920
2442 11:12:57.072233 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2443 11:12:57.075514 [DutyScan_Calibration_Flow] ====Done====
2444 11:12:57.078814 nWR fixed to 30
2445 11:12:57.082391 [ModeRegInit_LP4] CH0 RK0
2446 11:12:57.082479 [ModeRegInit_LP4] CH0 RK1
2447 11:12:57.085727 [ModeRegInit_LP4] CH1 RK0
2448 11:12:57.089043 [ModeRegInit_LP4] CH1 RK1
2449 11:12:57.089131 match AC timing 7
2450 11:12:57.095417 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2451 11:12:57.098629 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2452 11:12:57.101916 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2453 11:12:57.108824 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2454 11:12:57.112177 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2455 11:12:57.112273 ==
2456 11:12:57.115677 Dram Type= 6, Freq= 0, CH_0, rank 0
2457 11:12:57.118797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2458 11:12:57.118885 ==
2459 11:12:57.125533 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2460 11:12:57.131873 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2461 11:12:57.139653 [CA 0] Center 39 (9~70) winsize 62
2462 11:12:57.142789 [CA 1] Center 39 (8~70) winsize 63
2463 11:12:57.145925 [CA 2] Center 35 (5~66) winsize 62
2464 11:12:57.149734 [CA 3] Center 35 (5~66) winsize 62
2465 11:12:57.152895 [CA 4] Center 33 (3~64) winsize 62
2466 11:12:57.156248 [CA 5] Center 33 (3~64) winsize 62
2467 11:12:57.156340
2468 11:12:57.159532 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2469 11:12:57.159617
2470 11:12:57.162853 [CATrainingPosCal] consider 1 rank data
2471 11:12:57.166157 u2DelayCellTimex100 = 270/100 ps
2472 11:12:57.169381 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2473 11:12:57.176261 CA1 delay=39 (8~70),Diff = 6 PI (28 cell)
2474 11:12:57.179527 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2475 11:12:57.182513 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2476 11:12:57.185747 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2477 11:12:57.189234 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2478 11:12:57.189325
2479 11:12:57.192420 CA PerBit enable=1, Macro0, CA PI delay=33
2480 11:12:57.192519
2481 11:12:57.195941 [CBTSetCACLKResult] CA Dly = 33
2482 11:12:57.196084 CS Dly: 7 (0~38)
2483 11:12:57.199269 ==
2484 11:12:57.202597 Dram Type= 6, Freq= 0, CH_0, rank 1
2485 11:12:57.205714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2486 11:12:57.205858 ==
2487 11:12:57.209184 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2488 11:12:57.215410 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2489 11:12:57.225664 [CA 0] Center 39 (9~70) winsize 62
2490 11:12:57.228382 [CA 1] Center 39 (9~70) winsize 62
2491 11:12:57.231939 [CA 2] Center 35 (5~66) winsize 62
2492 11:12:57.235427 [CA 3] Center 35 (5~66) winsize 62
2493 11:12:57.238802 [CA 4] Center 34 (4~65) winsize 62
2494 11:12:57.241954 [CA 5] Center 33 (3~64) winsize 62
2495 11:12:57.242065
2496 11:12:57.245378 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2497 11:12:57.245466
2498 11:12:57.248539 [CATrainingPosCal] consider 2 rank data
2499 11:12:57.251637 u2DelayCellTimex100 = 270/100 ps
2500 11:12:57.255321 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2501 11:12:57.262087 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2502 11:12:57.265239 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2503 11:12:57.268430 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2504 11:12:57.271646 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2505 11:12:57.274976 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2506 11:12:57.275073
2507 11:12:57.278660 CA PerBit enable=1, Macro0, CA PI delay=33
2508 11:12:57.278737
2509 11:12:57.281240 [CBTSetCACLKResult] CA Dly = 33
2510 11:12:57.284637 CS Dly: 8 (0~41)
2511 11:12:57.284723
2512 11:12:57.287924 ----->DramcWriteLeveling(PI) begin...
2513 11:12:57.288011 ==
2514 11:12:57.291418 Dram Type= 6, Freq= 0, CH_0, rank 0
2515 11:12:57.294738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2516 11:12:57.294841 ==
2517 11:12:57.298134 Write leveling (Byte 0): 32 => 32
2518 11:12:57.301462 Write leveling (Byte 1): 27 => 27
2519 11:12:57.304918 DramcWriteLeveling(PI) end<-----
2520 11:12:57.305010
2521 11:12:57.305107 ==
2522 11:12:57.308066 Dram Type= 6, Freq= 0, CH_0, rank 0
2523 11:12:57.311406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2524 11:12:57.311556 ==
2525 11:12:57.314758 [Gating] SW mode calibration
2526 11:12:57.321655 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2527 11:12:57.327865 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2528 11:12:57.331323 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2529 11:12:57.334878 0 15 4 | B1->B0 | 2b2b 3434 | 1 1 | (0 0) (1 1)
2530 11:12:57.341112 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2531 11:12:57.344434 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2532 11:12:57.347843 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2533 11:12:57.354823 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2534 11:12:57.358014 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2535 11:12:57.361179 0 15 28 | B1->B0 | 3434 2727 | 1 0 | (1 1) (0 0)
2536 11:12:57.367757 1 0 0 | B1->B0 | 2f2f 2323 | 0 0 | (0 1) (0 0)
2537 11:12:57.371032 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2538 11:12:57.374668 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 11:12:57.377924 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2540 11:12:57.384693 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2541 11:12:57.387651 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2542 11:12:57.394537 1 0 24 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
2543 11:12:57.397941 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2544 11:12:57.401206 1 1 0 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
2545 11:12:57.404129 1 1 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
2546 11:12:57.410639 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2547 11:12:57.414425 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2548 11:12:57.417674 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2549 11:12:57.424202 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2550 11:12:57.427561 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2551 11:12:57.430867 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2552 11:12:57.437715 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2553 11:12:57.440626 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2554 11:12:57.444231 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 11:12:57.450551 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 11:12:57.453898 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 11:12:57.457222 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 11:12:57.464064 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 11:12:57.467336 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 11:12:57.470711 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 11:12:57.477152 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2562 11:12:57.480307 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2563 11:12:57.483724 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2564 11:12:57.490548 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 11:12:57.494082 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 11:12:57.496957 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2567 11:12:57.503644 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2568 11:12:57.506887 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2569 11:12:57.510135 Total UI for P1: 0, mck2ui 16
2570 11:12:57.513594 best dqsien dly found for B0: ( 1, 3, 26)
2571 11:12:57.516910 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2572 11:12:57.520182 Total UI for P1: 0, mck2ui 16
2573 11:12:57.523420 best dqsien dly found for B1: ( 1, 4, 0)
2574 11:12:57.526600 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2575 11:12:57.530033 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2576 11:12:57.530124
2577 11:12:57.536782 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2578 11:12:57.540279 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2579 11:12:57.540374 [Gating] SW calibration Done
2580 11:12:57.543736 ==
2581 11:12:57.543824 Dram Type= 6, Freq= 0, CH_0, rank 0
2582 11:12:57.549943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2583 11:12:57.550046 ==
2584 11:12:57.550115 RX Vref Scan: 0
2585 11:12:57.550177
2586 11:12:57.553319 RX Vref 0 -> 0, step: 1
2587 11:12:57.553405
2588 11:12:57.556660 RX Delay -40 -> 252, step: 8
2589 11:12:57.559888 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2590 11:12:57.563076 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2591 11:12:57.566622 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2592 11:12:57.573122 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2593 11:12:57.576286 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2594 11:12:57.580304 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2595 11:12:57.583394 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2596 11:12:57.586814 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2597 11:12:57.593519 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2598 11:12:57.596959 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2599 11:12:57.599844 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2600 11:12:57.603100 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2601 11:12:57.606521 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2602 11:12:57.613245 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2603 11:12:57.616551 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
2604 11:12:57.619870 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2605 11:12:57.619960 ==
2606 11:12:57.623120 Dram Type= 6, Freq= 0, CH_0, rank 0
2607 11:12:57.626524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2608 11:12:57.626639 ==
2609 11:12:57.629715 DQS Delay:
2610 11:12:57.629791 DQS0 = 0, DQS1 = 0
2611 11:12:57.632895 DQM Delay:
2612 11:12:57.632976 DQM0 = 117, DQM1 = 107
2613 11:12:57.636247 DQ Delay:
2614 11:12:57.639692 DQ0 =115, DQ1 =119, DQ2 =119, DQ3 =111
2615 11:12:57.643274 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
2616 11:12:57.646540 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2617 11:12:57.649709 DQ12 =115, DQ13 =111, DQ14 =115, DQ15 =115
2618 11:12:57.649789
2619 11:12:57.649850
2620 11:12:57.649908 ==
2621 11:12:57.652869 Dram Type= 6, Freq= 0, CH_0, rank 0
2622 11:12:57.656156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2623 11:12:57.656237 ==
2624 11:12:57.656305
2625 11:12:57.656366
2626 11:12:57.659495 TX Vref Scan disable
2627 11:12:57.662751 == TX Byte 0 ==
2628 11:12:57.666110 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2629 11:12:57.669717 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2630 11:12:57.672807 == TX Byte 1 ==
2631 11:12:57.676404 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2632 11:12:57.679642 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2633 11:12:57.679734 ==
2634 11:12:57.682816 Dram Type= 6, Freq= 0, CH_0, rank 0
2635 11:12:57.686113 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2636 11:12:57.689256 ==
2637 11:12:57.700027 TX Vref=22, minBit 5, minWin=25, winSum=411
2638 11:12:57.703426 TX Vref=24, minBit 8, minWin=25, winSum=419
2639 11:12:57.706225 TX Vref=26, minBit 1, minWin=26, winSum=426
2640 11:12:57.709571 TX Vref=28, minBit 1, minWin=26, winSum=427
2641 11:12:57.712987 TX Vref=30, minBit 10, minWin=26, winSum=434
2642 11:12:57.719645 TX Vref=32, minBit 0, minWin=26, winSum=429
2643 11:12:57.723186 [TxChooseVref] Worse bit 10, Min win 26, Win sum 434, Final Vref 30
2644 11:12:57.723289
2645 11:12:57.726178 Final TX Range 1 Vref 30
2646 11:12:57.726299
2647 11:12:57.726400 ==
2648 11:12:57.729591 Dram Type= 6, Freq= 0, CH_0, rank 0
2649 11:12:57.732899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2650 11:12:57.736156 ==
2651 11:12:57.736247
2652 11:12:57.736314
2653 11:12:57.736376 TX Vref Scan disable
2654 11:12:57.739937 == TX Byte 0 ==
2655 11:12:57.743138 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2656 11:12:57.746473 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2657 11:12:57.749973 == TX Byte 1 ==
2658 11:12:57.753427 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2659 11:12:57.756431 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2660 11:12:57.759817
2661 11:12:57.759935 [DATLAT]
2662 11:12:57.760029 Freq=1200, CH0 RK0
2663 11:12:57.760132
2664 11:12:57.763169 DATLAT Default: 0xd
2665 11:12:57.763318 0, 0xFFFF, sum = 0
2666 11:12:57.766235 1, 0xFFFF, sum = 0
2667 11:12:57.766323 2, 0xFFFF, sum = 0
2668 11:12:57.769618 3, 0xFFFF, sum = 0
2669 11:12:57.773258 4, 0xFFFF, sum = 0
2670 11:12:57.773349 5, 0xFFFF, sum = 0
2671 11:12:57.776454 6, 0xFFFF, sum = 0
2672 11:12:57.776563 7, 0xFFFF, sum = 0
2673 11:12:57.779662 8, 0xFFFF, sum = 0
2674 11:12:57.779750 9, 0xFFFF, sum = 0
2675 11:12:57.782972 10, 0xFFFF, sum = 0
2676 11:12:57.783060 11, 0xFFFF, sum = 0
2677 11:12:57.785993 12, 0x0, sum = 1
2678 11:12:57.786080 13, 0x0, sum = 2
2679 11:12:57.789387 14, 0x0, sum = 3
2680 11:12:57.789475 15, 0x0, sum = 4
2681 11:12:57.789544 best_step = 13
2682 11:12:57.793177
2683 11:12:57.793276 ==
2684 11:12:57.796609 Dram Type= 6, Freq= 0, CH_0, rank 0
2685 11:12:57.799810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2686 11:12:57.799920 ==
2687 11:12:57.800020 RX Vref Scan: 1
2688 11:12:57.800125
2689 11:12:57.802736 Set Vref Range= 32 -> 127
2690 11:12:57.802821
2691 11:12:57.806160 RX Vref 32 -> 127, step: 1
2692 11:12:57.806240
2693 11:12:57.809564 RX Delay -21 -> 252, step: 4
2694 11:12:57.809658
2695 11:12:57.812843 Set Vref, RX VrefLevel [Byte0]: 32
2696 11:12:57.816203 [Byte1]: 32
2697 11:12:57.816338
2698 11:12:57.819719 Set Vref, RX VrefLevel [Byte0]: 33
2699 11:12:57.822615 [Byte1]: 33
2700 11:12:57.826429
2701 11:12:57.826548 Set Vref, RX VrefLevel [Byte0]: 34
2702 11:12:57.829798 [Byte1]: 34
2703 11:12:57.834021
2704 11:12:57.834109 Set Vref, RX VrefLevel [Byte0]: 35
2705 11:12:57.837370 [Byte1]: 35
2706 11:12:57.841940
2707 11:12:57.842057 Set Vref, RX VrefLevel [Byte0]: 36
2708 11:12:57.845216 [Byte1]: 36
2709 11:12:57.850182
2710 11:12:57.850301 Set Vref, RX VrefLevel [Byte0]: 37
2711 11:12:57.853060 [Byte1]: 37
2712 11:12:57.857997
2713 11:12:57.858081 Set Vref, RX VrefLevel [Byte0]: 38
2714 11:12:57.861249 [Byte1]: 38
2715 11:12:57.865666
2716 11:12:57.865764 Set Vref, RX VrefLevel [Byte0]: 39
2717 11:12:57.868946 [Byte1]: 39
2718 11:12:57.873820
2719 11:12:57.873951 Set Vref, RX VrefLevel [Byte0]: 40
2720 11:12:57.876963 [Byte1]: 40
2721 11:12:57.881738
2722 11:12:57.881934 Set Vref, RX VrefLevel [Byte0]: 41
2723 11:12:57.885074 [Byte1]: 41
2724 11:12:57.889771
2725 11:12:57.889878 Set Vref, RX VrefLevel [Byte0]: 42
2726 11:12:57.893272 [Byte1]: 42
2727 11:12:57.897448
2728 11:12:57.897538 Set Vref, RX VrefLevel [Byte0]: 43
2729 11:12:57.900803 [Byte1]: 43
2730 11:12:57.905310
2731 11:12:57.905450 Set Vref, RX VrefLevel [Byte0]: 44
2732 11:12:57.908635 [Byte1]: 44
2733 11:12:57.913762
2734 11:12:57.913921 Set Vref, RX VrefLevel [Byte0]: 45
2735 11:12:57.916529 [Byte1]: 45
2736 11:12:57.921615
2737 11:12:57.921748 Set Vref, RX VrefLevel [Byte0]: 46
2738 11:12:57.924687 [Byte1]: 46
2739 11:12:57.929570
2740 11:12:57.929729 Set Vref, RX VrefLevel [Byte0]: 47
2741 11:12:57.932858 [Byte1]: 47
2742 11:12:57.937339
2743 11:12:57.937469 Set Vref, RX VrefLevel [Byte0]: 48
2744 11:12:57.940357 [Byte1]: 48
2745 11:12:57.945350
2746 11:12:57.945480 Set Vref, RX VrefLevel [Byte0]: 49
2747 11:12:57.948561 [Byte1]: 49
2748 11:12:57.953118
2749 11:12:57.953213 Set Vref, RX VrefLevel [Byte0]: 50
2750 11:12:57.956570 [Byte1]: 50
2751 11:12:57.961005
2752 11:12:57.961104 Set Vref, RX VrefLevel [Byte0]: 51
2753 11:12:57.964497 [Byte1]: 51
2754 11:12:57.968804
2755 11:12:57.968910 Set Vref, RX VrefLevel [Byte0]: 52
2756 11:12:57.972314 [Byte1]: 52
2757 11:12:57.976845
2758 11:12:57.976946 Set Vref, RX VrefLevel [Byte0]: 53
2759 11:12:57.979936 [Byte1]: 53
2760 11:12:57.984685
2761 11:12:57.984789 Set Vref, RX VrefLevel [Byte0]: 54
2762 11:12:57.987992 [Byte1]: 54
2763 11:12:57.992839
2764 11:12:57.992981 Set Vref, RX VrefLevel [Byte0]: 55
2765 11:12:57.995927 [Byte1]: 55
2766 11:12:58.001108
2767 11:12:58.001206 Set Vref, RX VrefLevel [Byte0]: 56
2768 11:12:58.004111 [Byte1]: 56
2769 11:12:58.008513
2770 11:12:58.008608 Set Vref, RX VrefLevel [Byte0]: 57
2771 11:12:58.011928 [Byte1]: 57
2772 11:12:58.016319
2773 11:12:58.016429 Set Vref, RX VrefLevel [Byte0]: 58
2774 11:12:58.019799 [Byte1]: 58
2775 11:12:58.024300
2776 11:12:58.024421 Set Vref, RX VrefLevel [Byte0]: 59
2777 11:12:58.027588 [Byte1]: 59
2778 11:12:58.032124
2779 11:12:58.032222 Set Vref, RX VrefLevel [Byte0]: 60
2780 11:12:58.035408 [Byte1]: 60
2781 11:12:58.040328
2782 11:12:58.040435 Set Vref, RX VrefLevel [Byte0]: 61
2783 11:12:58.043505 [Byte1]: 61
2784 11:12:58.048101
2785 11:12:58.048229 Set Vref, RX VrefLevel [Byte0]: 62
2786 11:12:58.051411 [Byte1]: 62
2787 11:12:58.055867
2788 11:12:58.055983 Set Vref, RX VrefLevel [Byte0]: 63
2789 11:12:58.059314 [Byte1]: 63
2790 11:12:58.063760
2791 11:12:58.063880 Set Vref, RX VrefLevel [Byte0]: 64
2792 11:12:58.067239 [Byte1]: 64
2793 11:12:58.071891
2794 11:12:58.072016 Set Vref, RX VrefLevel [Byte0]: 65
2795 11:12:58.075024 [Byte1]: 65
2796 11:12:58.079893
2797 11:12:58.080026 Set Vref, RX VrefLevel [Byte0]: 66
2798 11:12:58.083061 [Byte1]: 66
2799 11:12:58.087797
2800 11:12:58.087927 Set Vref, RX VrefLevel [Byte0]: 67
2801 11:12:58.090839 [Byte1]: 67
2802 11:12:58.095802
2803 11:12:58.095934 Set Vref, RX VrefLevel [Byte0]: 68
2804 11:12:58.099127 [Byte1]: 68
2805 11:12:58.103913
2806 11:12:58.104028 Final RX Vref Byte 0 = 51 to rank0
2807 11:12:58.107147 Final RX Vref Byte 1 = 47 to rank0
2808 11:12:58.110644 Final RX Vref Byte 0 = 51 to rank1
2809 11:12:58.113713 Final RX Vref Byte 1 = 47 to rank1==
2810 11:12:58.117107 Dram Type= 6, Freq= 0, CH_0, rank 0
2811 11:12:58.123899 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2812 11:12:58.124042 ==
2813 11:12:58.124142 DQS Delay:
2814 11:12:58.124236 DQS0 = 0, DQS1 = 0
2815 11:12:58.126648 DQM Delay:
2816 11:12:58.126749 DQM0 = 117, DQM1 = 103
2817 11:12:58.129953 DQ Delay:
2818 11:12:58.133486 DQ0 =118, DQ1 =116, DQ2 =114, DQ3 =114
2819 11:12:58.136896 DQ4 =118, DQ5 =110, DQ6 =126, DQ7 =122
2820 11:12:58.140348 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =98
2821 11:12:58.143417 DQ12 =110, DQ13 =108, DQ14 =112, DQ15 =110
2822 11:12:58.143557
2823 11:12:58.143628
2824 11:12:58.150135 [DQSOSCAuto] RK0, (LSB)MR18= 0x1fc, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 409 ps
2825 11:12:58.153600 CH0 RK0: MR19=403, MR18=1FC
2826 11:12:58.159952 CH0_RK0: MR19=0x403, MR18=0x1FC, DQSOSC=409, MR23=63, INC=39, DEC=26
2827 11:12:58.160068
2828 11:12:58.163389 ----->DramcWriteLeveling(PI) begin...
2829 11:12:58.163471 ==
2830 11:12:58.166780 Dram Type= 6, Freq= 0, CH_0, rank 1
2831 11:12:58.170524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2832 11:12:58.173154 ==
2833 11:12:58.173290 Write leveling (Byte 0): 34 => 34
2834 11:12:58.176372 Write leveling (Byte 1): 25 => 25
2835 11:12:58.179787 DramcWriteLeveling(PI) end<-----
2836 11:12:58.179944
2837 11:12:58.180053 ==
2838 11:12:58.183366 Dram Type= 6, Freq= 0, CH_0, rank 1
2839 11:12:58.189785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2840 11:12:58.189976 ==
2841 11:12:58.190082 [Gating] SW mode calibration
2842 11:12:58.200052 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2843 11:12:58.203368 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2844 11:12:58.206458 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2845 11:12:58.213115 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2846 11:12:58.216640 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2847 11:12:58.219867 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2848 11:12:58.226667 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2849 11:12:58.230097 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2850 11:12:58.232955 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2851 11:12:58.239628 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
2852 11:12:58.243030 1 0 0 | B1->B0 | 2a2a 2323 | 1 0 | (1 0) (0 0)
2853 11:12:58.246654 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2854 11:12:58.252813 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2855 11:12:58.256059 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2856 11:12:58.259846 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2857 11:12:58.265982 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2858 11:12:58.269408 1 0 24 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
2859 11:12:58.272852 1 0 28 | B1->B0 | 2d2d 4646 | 1 0 | (0 0) (0 0)
2860 11:12:58.279159 1 1 0 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
2861 11:12:58.282732 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2862 11:12:58.286256 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2863 11:12:58.292493 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2864 11:12:58.296144 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2865 11:12:58.299363 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2866 11:12:58.305905 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2867 11:12:58.309361 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2868 11:12:58.312257 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 11:12:58.319396 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 11:12:58.322714 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 11:12:58.326061 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 11:12:58.332404 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 11:12:58.335776 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 11:12:58.339159 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 11:12:58.346023 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 11:12:58.349179 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 11:12:58.352405 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 11:12:58.358776 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 11:12:58.362434 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 11:12:58.365780 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 11:12:58.372628 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 11:12:58.375910 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2883 11:12:58.379194 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2884 11:12:58.382800 Total UI for P1: 0, mck2ui 16
2885 11:12:58.385534 best dqsien dly found for B0: ( 1, 3, 24)
2886 11:12:58.388841 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2887 11:12:58.395846 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2888 11:12:58.399025 Total UI for P1: 0, mck2ui 16
2889 11:12:58.402094 best dqsien dly found for B1: ( 1, 4, 0)
2890 11:12:58.405236 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2891 11:12:58.409015 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2892 11:12:58.409128
2893 11:12:58.412457 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2894 11:12:58.415461 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2895 11:12:58.418588 [Gating] SW calibration Done
2896 11:12:58.418676 ==
2897 11:12:58.422125 Dram Type= 6, Freq= 0, CH_0, rank 1
2898 11:12:58.425158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2899 11:12:58.425243 ==
2900 11:12:58.428482 RX Vref Scan: 0
2901 11:12:58.428566
2902 11:12:58.428637 RX Vref 0 -> 0, step: 1
2903 11:12:58.431859
2904 11:12:58.431960 RX Delay -40 -> 252, step: 8
2905 11:12:58.438550 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2906 11:12:58.441858 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2907 11:12:58.445154 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2908 11:12:58.448563 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2909 11:12:58.451907 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2910 11:12:58.458327 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2911 11:12:58.461700 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2912 11:12:58.465373 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
2913 11:12:58.468811 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2914 11:12:58.471695 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2915 11:12:58.475112 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2916 11:12:58.481939 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2917 11:12:58.485242 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2918 11:12:58.488489 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2919 11:12:58.491787 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2920 11:12:58.498451 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2921 11:12:58.498587 ==
2922 11:12:58.501879 Dram Type= 6, Freq= 0, CH_0, rank 1
2923 11:12:58.505061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2924 11:12:58.505173 ==
2925 11:12:58.505270 DQS Delay:
2926 11:12:58.508330 DQS0 = 0, DQS1 = 0
2927 11:12:58.508431 DQM Delay:
2928 11:12:58.511351 DQM0 = 115, DQM1 = 106
2929 11:12:58.511453 DQ Delay:
2930 11:12:58.515004 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =111
2931 11:12:58.518074 DQ4 =119, DQ5 =103, DQ6 =127, DQ7 =119
2932 11:12:58.521238 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2933 11:12:58.525131 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2934 11:12:58.525216
2935 11:12:58.525280
2936 11:12:58.527905 ==
2937 11:12:58.528006 Dram Type= 6, Freq= 0, CH_0, rank 1
2938 11:12:58.534807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2939 11:12:58.534927 ==
2940 11:12:58.535021
2941 11:12:58.535106
2942 11:12:58.537676 TX Vref Scan disable
2943 11:12:58.537805 == TX Byte 0 ==
2944 11:12:58.541026 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2945 11:12:58.547787 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2946 11:12:58.547909 == TX Byte 1 ==
2947 11:12:58.551146 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2948 11:12:58.557805 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2949 11:12:58.557933 ==
2950 11:12:58.561095 Dram Type= 6, Freq= 0, CH_0, rank 1
2951 11:12:58.564527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2952 11:12:58.564636 ==
2953 11:12:58.577092 TX Vref=22, minBit 8, minWin=25, winSum=417
2954 11:12:58.580519 TX Vref=24, minBit 12, minWin=25, winSum=421
2955 11:12:58.583940 TX Vref=26, minBit 0, minWin=26, winSum=428
2956 11:12:58.587246 TX Vref=28, minBit 10, minWin=25, winSum=428
2957 11:12:58.590559 TX Vref=30, minBit 4, minWin=26, winSum=429
2958 11:12:58.597255 TX Vref=32, minBit 13, minWin=26, winSum=432
2959 11:12:58.600746 [TxChooseVref] Worse bit 13, Min win 26, Win sum 432, Final Vref 32
2960 11:12:58.600835
2961 11:12:58.603786 Final TX Range 1 Vref 32
2962 11:12:58.603905
2963 11:12:58.603995 ==
2964 11:12:58.606685 Dram Type= 6, Freq= 0, CH_0, rank 1
2965 11:12:58.613693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2966 11:12:58.613822 ==
2967 11:12:58.613916
2968 11:12:58.614006
2969 11:12:58.614158 TX Vref Scan disable
2970 11:12:58.617528 == TX Byte 0 ==
2971 11:12:58.620642 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2972 11:12:58.627460 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2973 11:12:58.627570 == TX Byte 1 ==
2974 11:12:58.630766 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2975 11:12:58.637343 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2976 11:12:58.637458
2977 11:12:58.637526 [DATLAT]
2978 11:12:58.637588 Freq=1200, CH0 RK1
2979 11:12:58.637647
2980 11:12:58.640531 DATLAT Default: 0xd
2981 11:12:58.640617 0, 0xFFFF, sum = 0
2982 11:12:58.643750 1, 0xFFFF, sum = 0
2983 11:12:58.647157 2, 0xFFFF, sum = 0
2984 11:12:58.647245 3, 0xFFFF, sum = 0
2985 11:12:58.650418 4, 0xFFFF, sum = 0
2986 11:12:58.650504 5, 0xFFFF, sum = 0
2987 11:12:58.653859 6, 0xFFFF, sum = 0
2988 11:12:58.653946 7, 0xFFFF, sum = 0
2989 11:12:58.657403 8, 0xFFFF, sum = 0
2990 11:12:58.657490 9, 0xFFFF, sum = 0
2991 11:12:58.660604 10, 0xFFFF, sum = 0
2992 11:12:58.660690 11, 0xFFFF, sum = 0
2993 11:12:58.663821 12, 0x0, sum = 1
2994 11:12:58.663908 13, 0x0, sum = 2
2995 11:12:58.667212 14, 0x0, sum = 3
2996 11:12:58.667298 15, 0x0, sum = 4
2997 11:12:58.670365 best_step = 13
2998 11:12:58.670494
2999 11:12:58.670588 ==
3000 11:12:58.673596 Dram Type= 6, Freq= 0, CH_0, rank 1
3001 11:12:58.676809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3002 11:12:58.676896 ==
3003 11:12:58.676962 RX Vref Scan: 0
3004 11:12:58.677023
3005 11:12:58.680196 RX Vref 0 -> 0, step: 1
3006 11:12:58.680279
3007 11:12:58.683564 RX Delay -21 -> 252, step: 4
3008 11:12:58.690280 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
3009 11:12:58.693648 iDelay=195, Bit 1, Center 116 (47 ~ 186) 140
3010 11:12:58.697028 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3011 11:12:58.700433 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3012 11:12:58.703453 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3013 11:12:58.706750 iDelay=195, Bit 5, Center 108 (43 ~ 174) 132
3014 11:12:58.713508 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3015 11:12:58.716688 iDelay=195, Bit 7, Center 120 (55 ~ 186) 132
3016 11:12:58.719925 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3017 11:12:58.723431 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3018 11:12:58.726503 iDelay=195, Bit 10, Center 108 (43 ~ 174) 132
3019 11:12:58.733461 iDelay=195, Bit 11, Center 98 (31 ~ 166) 136
3020 11:12:58.736847 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3021 11:12:58.739757 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3022 11:12:58.743439 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3023 11:12:58.749831 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3024 11:12:58.749974 ==
3025 11:12:58.753209 Dram Type= 6, Freq= 0, CH_0, rank 1
3026 11:12:58.756713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3027 11:12:58.756833 ==
3028 11:12:58.756917 DQS Delay:
3029 11:12:58.759906 DQS0 = 0, DQS1 = 0
3030 11:12:58.760005 DQM Delay:
3031 11:12:58.763241 DQM0 = 115, DQM1 = 104
3032 11:12:58.763332 DQ Delay:
3033 11:12:58.766538 DQ0 =114, DQ1 =116, DQ2 =110, DQ3 =112
3034 11:12:58.769697 DQ4 =118, DQ5 =108, DQ6 =126, DQ7 =120
3035 11:12:58.772954 DQ8 =94, DQ9 =92, DQ10 =108, DQ11 =98
3036 11:12:58.776253 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =110
3037 11:12:58.776347
3038 11:12:58.776412
3039 11:12:58.786244 [DQSOSCAuto] RK1, (LSB)MR18= 0xfd, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
3040 11:12:58.789238 CH0 RK1: MR19=403, MR18=FD
3041 11:12:58.793089 CH0_RK1: MR19=0x403, MR18=0xFD, DQSOSC=410, MR23=63, INC=39, DEC=26
3042 11:12:58.796272 [RxdqsGatingPostProcess] freq 1200
3043 11:12:58.802491 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3044 11:12:58.805871 best DQS0 dly(2T, 0.5T) = (0, 11)
3045 11:12:58.809181 best DQS1 dly(2T, 0.5T) = (0, 12)
3046 11:12:58.812519 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3047 11:12:58.815789 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3048 11:12:58.819171 best DQS0 dly(2T, 0.5T) = (0, 11)
3049 11:12:58.822501 best DQS1 dly(2T, 0.5T) = (0, 12)
3050 11:12:58.825613 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3051 11:12:58.825703 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3052 11:12:58.829391 Pre-setting of DQS Precalculation
3053 11:12:58.835728 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3054 11:12:58.835837 ==
3055 11:12:58.838980 Dram Type= 6, Freq= 0, CH_1, rank 0
3056 11:12:58.842607 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3057 11:12:58.842746 ==
3058 11:12:58.849509 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3059 11:12:58.855495 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3060 11:12:58.862884 [CA 0] Center 38 (8~68) winsize 61
3061 11:12:58.866241 [CA 1] Center 37 (7~68) winsize 62
3062 11:12:58.869571 [CA 2] Center 35 (5~65) winsize 61
3063 11:12:58.872909 [CA 3] Center 34 (4~64) winsize 61
3064 11:12:58.876246 [CA 4] Center 35 (5~65) winsize 61
3065 11:12:58.879847 [CA 5] Center 33 (3~63) winsize 61
3066 11:12:58.879936
3067 11:12:58.883101 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3068 11:12:58.883177
3069 11:12:58.886482 [CATrainingPosCal] consider 1 rank data
3070 11:12:58.889915 u2DelayCellTimex100 = 270/100 ps
3071 11:12:58.892706 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3072 11:12:58.895990 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3073 11:12:58.902784 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3074 11:12:58.906110 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3075 11:12:58.909408 CA4 delay=35 (5~65),Diff = 2 PI (9 cell)
3076 11:12:58.912778 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3077 11:12:58.912867
3078 11:12:58.916203 CA PerBit enable=1, Macro0, CA PI delay=33
3079 11:12:58.916319
3080 11:12:58.919446 [CBTSetCACLKResult] CA Dly = 33
3081 11:12:58.919530 CS Dly: 5 (0~36)
3082 11:12:58.922899 ==
3083 11:12:58.926269 Dram Type= 6, Freq= 0, CH_1, rank 1
3084 11:12:58.929150 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3085 11:12:58.929242 ==
3086 11:12:58.932910 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3087 11:12:58.939033 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3088 11:12:58.948965 [CA 0] Center 38 (8~68) winsize 61
3089 11:12:58.952000 [CA 1] Center 38 (8~68) winsize 61
3090 11:12:58.955485 [CA 2] Center 34 (4~65) winsize 62
3091 11:12:58.958589 [CA 3] Center 33 (3~64) winsize 62
3092 11:12:58.961954 [CA 4] Center 34 (4~64) winsize 61
3093 11:12:58.965264 [CA 5] Center 33 (3~63) winsize 61
3094 11:12:58.965389
3095 11:12:58.968665 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3096 11:12:58.968753
3097 11:12:58.971495 [CATrainingPosCal] consider 2 rank data
3098 11:12:58.974799 u2DelayCellTimex100 = 270/100 ps
3099 11:12:58.978706 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3100 11:12:58.985152 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3101 11:12:58.988474 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3102 11:12:58.991707 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3103 11:12:58.994482 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3104 11:12:58.997832 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3105 11:12:58.997942
3106 11:12:59.001286 CA PerBit enable=1, Macro0, CA PI delay=33
3107 11:12:59.001399
3108 11:12:59.004630 [CBTSetCACLKResult] CA Dly = 33
3109 11:12:59.008229 CS Dly: 6 (0~39)
3110 11:12:59.008322
3111 11:12:59.011016 ----->DramcWriteLeveling(PI) begin...
3112 11:12:59.011130 ==
3113 11:12:59.014224 Dram Type= 6, Freq= 0, CH_1, rank 0
3114 11:12:59.017717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3115 11:12:59.017840 ==
3116 11:12:59.021004 Write leveling (Byte 0): 25 => 25
3117 11:12:59.024241 Write leveling (Byte 1): 26 => 26
3118 11:12:59.027489 DramcWriteLeveling(PI) end<-----
3119 11:12:59.027603
3120 11:12:59.027695 ==
3121 11:12:59.030921 Dram Type= 6, Freq= 0, CH_1, rank 0
3122 11:12:59.034323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3123 11:12:59.034457 ==
3124 11:12:59.037686 [Gating] SW mode calibration
3125 11:12:59.044094 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3126 11:12:59.051060 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3127 11:12:59.054243 0 15 0 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
3128 11:12:59.057339 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3129 11:12:59.064372 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3130 11:12:59.067184 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3131 11:12:59.071073 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3132 11:12:59.077684 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3133 11:12:59.080823 0 15 24 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
3134 11:12:59.084076 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (0 0) (1 0)
3135 11:12:59.091023 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3136 11:12:59.093953 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3137 11:12:59.097760 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3138 11:12:59.103894 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3139 11:12:59.107411 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3140 11:12:59.110670 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3141 11:12:59.117536 1 0 24 | B1->B0 | 2525 3434 | 0 0 | (0 0) (0 0)
3142 11:12:59.120357 1 0 28 | B1->B0 | 3e3e 4343 | 0 0 | (0 0) (0 0)
3143 11:12:59.123751 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3144 11:12:59.130574 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3145 11:12:59.133674 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3146 11:12:59.136891 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3147 11:12:59.143613 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3148 11:12:59.147432 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3149 11:12:59.150831 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3150 11:12:59.157378 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3151 11:12:59.160648 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 11:12:59.163902 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 11:12:59.167146 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 11:12:59.173963 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 11:12:59.177074 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 11:12:59.180335 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 11:12:59.187270 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 11:12:59.190468 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 11:12:59.193670 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 11:12:59.200166 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 11:12:59.203717 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 11:12:59.207111 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 11:12:59.213335 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 11:12:59.216903 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 11:12:59.220104 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3166 11:12:59.227015 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3167 11:12:59.230330 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3168 11:12:59.233555 Total UI for P1: 0, mck2ui 16
3169 11:12:59.237006 best dqsien dly found for B0: ( 1, 3, 26)
3170 11:12:59.240357 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3171 11:12:59.243600 Total UI for P1: 0, mck2ui 16
3172 11:12:59.247062 best dqsien dly found for B1: ( 1, 3, 28)
3173 11:12:59.250427 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3174 11:12:59.253375 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3175 11:12:59.253465
3176 11:12:59.260443 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3177 11:12:59.263393 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3178 11:12:59.263496 [Gating] SW calibration Done
3179 11:12:59.266580 ==
3180 11:12:59.266664 Dram Type= 6, Freq= 0, CH_1, rank 0
3181 11:12:59.273287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3182 11:12:59.273431 ==
3183 11:12:59.273532 RX Vref Scan: 0
3184 11:12:59.273624
3185 11:12:59.276501 RX Vref 0 -> 0, step: 1
3186 11:12:59.276604
3187 11:12:59.279990 RX Delay -40 -> 252, step: 8
3188 11:12:59.283457 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3189 11:12:59.286590 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3190 11:12:59.289922 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3191 11:12:59.296512 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3192 11:12:59.299999 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3193 11:12:59.303190 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3194 11:12:59.306709 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3195 11:12:59.310091 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3196 11:12:59.316853 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3197 11:12:59.319590 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3198 11:12:59.323139 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3199 11:12:59.326522 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3200 11:12:59.330013 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3201 11:12:59.336547 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3202 11:12:59.339974 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3203 11:12:59.343448 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3204 11:12:59.343561 ==
3205 11:12:59.346720 Dram Type= 6, Freq= 0, CH_1, rank 0
3206 11:12:59.349633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3207 11:12:59.352897 ==
3208 11:12:59.352991 DQS Delay:
3209 11:12:59.353094 DQS0 = 0, DQS1 = 0
3210 11:12:59.356244 DQM Delay:
3211 11:12:59.356334 DQM0 = 115, DQM1 = 112
3212 11:12:59.359603 DQ Delay:
3213 11:12:59.362941 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =115
3214 11:12:59.366697 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3215 11:12:59.370159 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3216 11:12:59.373180 DQ12 =123, DQ13 =119, DQ14 =119, DQ15 =119
3217 11:12:59.373275
3218 11:12:59.373362
3219 11:12:59.373443 ==
3220 11:12:59.376447 Dram Type= 6, Freq= 0, CH_1, rank 0
3221 11:12:59.379430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3222 11:12:59.379543 ==
3223 11:12:59.379642
3224 11:12:59.382690
3225 11:12:59.382796 TX Vref Scan disable
3226 11:12:59.386196 == TX Byte 0 ==
3227 11:12:59.389311 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3228 11:12:59.392967 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3229 11:12:59.396040 == TX Byte 1 ==
3230 11:12:59.399203 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3231 11:12:59.402484 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3232 11:12:59.402570 ==
3233 11:12:59.406020 Dram Type= 6, Freq= 0, CH_1, rank 0
3234 11:12:59.412622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3235 11:12:59.412727 ==
3236 11:12:59.423235 TX Vref=22, minBit 9, minWin=23, winSum=403
3237 11:12:59.426447 TX Vref=24, minBit 8, minWin=24, winSum=413
3238 11:12:59.429926 TX Vref=26, minBit 9, minWin=24, winSum=419
3239 11:12:59.433208 TX Vref=28, minBit 9, minWin=24, winSum=424
3240 11:12:59.436597 TX Vref=30, minBit 9, minWin=24, winSum=422
3241 11:12:59.442572 TX Vref=32, minBit 8, minWin=25, winSum=422
3242 11:12:59.445932 [TxChooseVref] Worse bit 8, Min win 25, Win sum 422, Final Vref 32
3243 11:12:59.446022
3244 11:12:59.449342 Final TX Range 1 Vref 32
3245 11:12:59.449429
3246 11:12:59.449497 ==
3247 11:12:59.452576 Dram Type= 6, Freq= 0, CH_1, rank 0
3248 11:12:59.455974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3249 11:12:59.456080 ==
3250 11:12:59.459252
3251 11:12:59.459334
3252 11:12:59.459396 TX Vref Scan disable
3253 11:12:59.462810 == TX Byte 0 ==
3254 11:12:59.465976 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3255 11:12:59.472725 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3256 11:12:59.472831 == TX Byte 1 ==
3257 11:12:59.475989 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3258 11:12:59.482370 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3259 11:12:59.482471
3260 11:12:59.482541 [DATLAT]
3261 11:12:59.482604 Freq=1200, CH1 RK0
3262 11:12:59.482662
3263 11:12:59.485703 DATLAT Default: 0xd
3264 11:12:59.488881 0, 0xFFFF, sum = 0
3265 11:12:59.488967 1, 0xFFFF, sum = 0
3266 11:12:59.492399 2, 0xFFFF, sum = 0
3267 11:12:59.492484 3, 0xFFFF, sum = 0
3268 11:12:59.495620 4, 0xFFFF, sum = 0
3269 11:12:59.495703 5, 0xFFFF, sum = 0
3270 11:12:59.498835 6, 0xFFFF, sum = 0
3271 11:12:59.498911 7, 0xFFFF, sum = 0
3272 11:12:59.502011 8, 0xFFFF, sum = 0
3273 11:12:59.502088 9, 0xFFFF, sum = 0
3274 11:12:59.505239 10, 0xFFFF, sum = 0
3275 11:12:59.505364 11, 0xFFFF, sum = 0
3276 11:12:59.508885 12, 0x0, sum = 1
3277 11:12:59.508973 13, 0x0, sum = 2
3278 11:12:59.511960 14, 0x0, sum = 3
3279 11:12:59.512117 15, 0x0, sum = 4
3280 11:12:59.515110 best_step = 13
3281 11:12:59.515252
3282 11:12:59.515350 ==
3283 11:12:59.518552 Dram Type= 6, Freq= 0, CH_1, rank 0
3284 11:12:59.522480 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3285 11:12:59.522580 ==
3286 11:12:59.525212 RX Vref Scan: 1
3287 11:12:59.525307
3288 11:12:59.525405 Set Vref Range= 32 -> 127
3289 11:12:59.525469
3290 11:12:59.528718 RX Vref 32 -> 127, step: 1
3291 11:12:59.528794
3292 11:12:59.532151 RX Delay -13 -> 252, step: 4
3293 11:12:59.532227
3294 11:12:59.535475 Set Vref, RX VrefLevel [Byte0]: 32
3295 11:12:59.538840 [Byte1]: 32
3296 11:12:59.538932
3297 11:12:59.541671 Set Vref, RX VrefLevel [Byte0]: 33
3298 11:12:59.545045 [Byte1]: 33
3299 11:12:59.548928
3300 11:12:59.549027 Set Vref, RX VrefLevel [Byte0]: 34
3301 11:12:59.552372 [Byte1]: 34
3302 11:12:59.556855
3303 11:12:59.556948 Set Vref, RX VrefLevel [Byte0]: 35
3304 11:12:59.560275 [Byte1]: 35
3305 11:12:59.564703
3306 11:12:59.564804 Set Vref, RX VrefLevel [Byte0]: 36
3307 11:12:59.567980 [Byte1]: 36
3308 11:12:59.572539
3309 11:12:59.572651 Set Vref, RX VrefLevel [Byte0]: 37
3310 11:12:59.575812 [Byte1]: 37
3311 11:12:59.580366
3312 11:12:59.580495 Set Vref, RX VrefLevel [Byte0]: 38
3313 11:12:59.583853 [Byte1]: 38
3314 11:12:59.588330
3315 11:12:59.588459 Set Vref, RX VrefLevel [Byte0]: 39
3316 11:12:59.591923 [Byte1]: 39
3317 11:12:59.596579
3318 11:12:59.596676 Set Vref, RX VrefLevel [Byte0]: 40
3319 11:12:59.599626 [Byte1]: 40
3320 11:12:59.604220
3321 11:12:59.604339 Set Vref, RX VrefLevel [Byte0]: 41
3322 11:12:59.607544 [Byte1]: 41
3323 11:12:59.612189
3324 11:12:59.612285 Set Vref, RX VrefLevel [Byte0]: 42
3325 11:12:59.615626 [Byte1]: 42
3326 11:12:59.620241
3327 11:12:59.620349 Set Vref, RX VrefLevel [Byte0]: 43
3328 11:12:59.623517 [Byte1]: 43
3329 11:12:59.628006
3330 11:12:59.628125 Set Vref, RX VrefLevel [Byte0]: 44
3331 11:12:59.631391 [Byte1]: 44
3332 11:12:59.635830
3333 11:12:59.635945 Set Vref, RX VrefLevel [Byte0]: 45
3334 11:12:59.639269 [Byte1]: 45
3335 11:12:59.643702
3336 11:12:59.643793 Set Vref, RX VrefLevel [Byte0]: 46
3337 11:12:59.647363 [Byte1]: 46
3338 11:12:59.651504
3339 11:12:59.651595 Set Vref, RX VrefLevel [Byte0]: 47
3340 11:12:59.654864 [Byte1]: 47
3341 11:12:59.659445
3342 11:12:59.659526 Set Vref, RX VrefLevel [Byte0]: 48
3343 11:12:59.662893 [Byte1]: 48
3344 11:12:59.667376
3345 11:12:59.667495 Set Vref, RX VrefLevel [Byte0]: 49
3346 11:12:59.670741 [Byte1]: 49
3347 11:12:59.675279
3348 11:12:59.675368 Set Vref, RX VrefLevel [Byte0]: 50
3349 11:12:59.678629 [Byte1]: 50
3350 11:12:59.683065
3351 11:12:59.683157 Set Vref, RX VrefLevel [Byte0]: 51
3352 11:12:59.686328 [Byte1]: 51
3353 11:12:59.691241
3354 11:12:59.691361 Set Vref, RX VrefLevel [Byte0]: 52
3355 11:12:59.694658 [Byte1]: 52
3356 11:12:59.698782
3357 11:12:59.698892 Set Vref, RX VrefLevel [Byte0]: 53
3358 11:12:59.705192 [Byte1]: 53
3359 11:12:59.705294
3360 11:12:59.708963 Set Vref, RX VrefLevel [Byte0]: 54
3361 11:12:59.711862 [Byte1]: 54
3362 11:12:59.711966
3363 11:12:59.715064 Set Vref, RX VrefLevel [Byte0]: 55
3364 11:12:59.718890 [Byte1]: 55
3365 11:12:59.722470
3366 11:12:59.722591 Set Vref, RX VrefLevel [Byte0]: 56
3367 11:12:59.725559 [Byte1]: 56
3368 11:12:59.730562
3369 11:12:59.730659 Set Vref, RX VrefLevel [Byte0]: 57
3370 11:12:59.733970 [Byte1]: 57
3371 11:12:59.738470
3372 11:12:59.738561 Set Vref, RX VrefLevel [Byte0]: 58
3373 11:12:59.741820 [Byte1]: 58
3374 11:12:59.746273
3375 11:12:59.746363 Set Vref, RX VrefLevel [Byte0]: 59
3376 11:12:59.749693 [Byte1]: 59
3377 11:12:59.753970
3378 11:12:59.754067 Set Vref, RX VrefLevel [Byte0]: 60
3379 11:12:59.757256 [Byte1]: 60
3380 11:12:59.761804
3381 11:12:59.761910 Set Vref, RX VrefLevel [Byte0]: 61
3382 11:12:59.765110 [Byte1]: 61
3383 11:12:59.769552
3384 11:12:59.769644 Set Vref, RX VrefLevel [Byte0]: 62
3385 11:12:59.772849 [Byte1]: 62
3386 11:12:59.777445
3387 11:12:59.777549 Set Vref, RX VrefLevel [Byte0]: 63
3388 11:12:59.780882 [Byte1]: 63
3389 11:12:59.785725
3390 11:12:59.785840 Set Vref, RX VrefLevel [Byte0]: 64
3391 11:12:59.788595 [Byte1]: 64
3392 11:12:59.793588
3393 11:12:59.793701 Final RX Vref Byte 0 = 52 to rank0
3394 11:12:59.796880 Final RX Vref Byte 1 = 52 to rank0
3395 11:12:59.800334 Final RX Vref Byte 0 = 52 to rank1
3396 11:12:59.803208 Final RX Vref Byte 1 = 52 to rank1==
3397 11:12:59.806794 Dram Type= 6, Freq= 0, CH_1, rank 0
3398 11:12:59.813501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3399 11:12:59.813638 ==
3400 11:12:59.813733 DQS Delay:
3401 11:12:59.813821 DQS0 = 0, DQS1 = 0
3402 11:12:59.816691 DQM Delay:
3403 11:12:59.816815 DQM0 = 114, DQM1 = 113
3404 11:12:59.819811 DQ Delay:
3405 11:12:59.823365 DQ0 =120, DQ1 =112, DQ2 =106, DQ3 =114
3406 11:12:59.826511 DQ4 =110, DQ5 =122, DQ6 =124, DQ7 =110
3407 11:12:59.830327 DQ8 =100, DQ9 =104, DQ10 =114, DQ11 =106
3408 11:12:59.833385 DQ12 =122, DQ13 =122, DQ14 =120, DQ15 =122
3409 11:12:59.833472
3410 11:12:59.833536
3411 11:12:59.843161 [DQSOSCAuto] RK0, (LSB)MR18= 0xf1fe, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 416 ps
3412 11:12:59.843305 CH1 RK0: MR19=303, MR18=F1FE
3413 11:12:59.849979 CH1_RK0: MR19=0x303, MR18=0xF1FE, DQSOSC=410, MR23=63, INC=39, DEC=26
3414 11:12:59.850087
3415 11:12:59.852878 ----->DramcWriteLeveling(PI) begin...
3416 11:12:59.852965 ==
3417 11:12:59.856308 Dram Type= 6, Freq= 0, CH_1, rank 1
3418 11:12:59.863119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3419 11:12:59.863227 ==
3420 11:12:59.866371 Write leveling (Byte 0): 26 => 26
3421 11:12:59.869753 Write leveling (Byte 1): 28 => 28
3422 11:12:59.869843 DramcWriteLeveling(PI) end<-----
3423 11:12:59.869909
3424 11:12:59.873093 ==
3425 11:12:59.875976 Dram Type= 6, Freq= 0, CH_1, rank 1
3426 11:12:59.879388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3427 11:12:59.879477 ==
3428 11:12:59.882707 [Gating] SW mode calibration
3429 11:12:59.889384 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3430 11:12:59.892888 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3431 11:12:59.899372 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3432 11:12:59.902393 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3433 11:12:59.905945 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3434 11:12:59.912443 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3435 11:12:59.915686 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3436 11:12:59.918770 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3437 11:12:59.925862 0 15 24 | B1->B0 | 3434 2a2a | 0 0 | (0 0) (0 0)
3438 11:12:59.929102 0 15 28 | B1->B0 | 3131 2323 | 0 0 | (0 0) (0 0)
3439 11:12:59.932293 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3440 11:12:59.938990 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3441 11:12:59.942251 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3442 11:12:59.945599 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3443 11:12:59.952297 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3444 11:12:59.955733 1 0 20 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (1 1)
3445 11:12:59.958956 1 0 24 | B1->B0 | 2525 4646 | 0 0 | (0 0) (0 0)
3446 11:12:59.965587 1 0 28 | B1->B0 | 3636 4646 | 1 0 | (0 0) (0 0)
3447 11:12:59.968875 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3448 11:12:59.971801 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3449 11:12:59.978449 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3450 11:12:59.981896 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3451 11:12:59.985165 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3452 11:12:59.991806 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3453 11:12:59.995151 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3454 11:12:59.998645 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3455 11:13:00.004815 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3456 11:13:00.007956 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3457 11:13:00.011325 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3458 11:13:00.018217 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3459 11:13:00.021462 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 11:13:00.024502 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 11:13:00.031527 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 11:13:00.034598 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 11:13:00.037745 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 11:13:00.044551 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 11:13:00.047626 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 11:13:00.050880 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 11:13:00.057616 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 11:13:00.061036 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3469 11:13:00.064115 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3470 11:13:00.070957 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3471 11:13:00.073727 Total UI for P1: 0, mck2ui 16
3472 11:13:00.077128 best dqsien dly found for B0: ( 1, 3, 22)
3473 11:13:00.080492 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3474 11:13:00.083958 Total UI for P1: 0, mck2ui 16
3475 11:13:00.087226 best dqsien dly found for B1: ( 1, 3, 28)
3476 11:13:00.090733 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3477 11:13:00.094000 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3478 11:13:00.094087
3479 11:13:00.096703 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3480 11:13:00.100041 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3481 11:13:00.103722 [Gating] SW calibration Done
3482 11:13:00.103838 ==
3483 11:13:00.106768 Dram Type= 6, Freq= 0, CH_1, rank 1
3484 11:13:00.113317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3485 11:13:00.113448 ==
3486 11:13:00.113541 RX Vref Scan: 0
3487 11:13:00.113642
3488 11:13:00.116998 RX Vref 0 -> 0, step: 1
3489 11:13:00.117125
3490 11:13:00.119895 RX Delay -40 -> 252, step: 8
3491 11:13:00.122960 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3492 11:13:00.126761 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3493 11:13:00.129981 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3494 11:13:00.136233 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3495 11:13:00.139518 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3496 11:13:00.142798 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3497 11:13:00.146060 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3498 11:13:00.149604 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3499 11:13:00.156109 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3500 11:13:00.159564 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3501 11:13:00.162425 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3502 11:13:00.165784 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3503 11:13:00.169114 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3504 11:13:00.175836 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3505 11:13:00.179147 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3506 11:13:00.182474 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3507 11:13:00.182588 ==
3508 11:13:00.185805 Dram Type= 6, Freq= 0, CH_1, rank 1
3509 11:13:00.191965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3510 11:13:00.192095 ==
3511 11:13:00.192193 DQS Delay:
3512 11:13:00.192284 DQS0 = 0, DQS1 = 0
3513 11:13:00.195455 DQM Delay:
3514 11:13:00.195563 DQM0 = 115, DQM1 = 111
3515 11:13:00.198462 DQ Delay:
3516 11:13:00.202017 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3517 11:13:00.205237 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =115
3518 11:13:00.208562 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =107
3519 11:13:00.211920 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3520 11:13:00.212043
3521 11:13:00.212119
3522 11:13:00.212193 ==
3523 11:13:00.215306 Dram Type= 6, Freq= 0, CH_1, rank 1
3524 11:13:00.218137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3525 11:13:00.221791 ==
3526 11:13:00.221916
3527 11:13:00.222022
3528 11:13:00.222137 TX Vref Scan disable
3529 11:13:00.224996 == TX Byte 0 ==
3530 11:13:00.228187 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3531 11:13:00.231461 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3532 11:13:00.234592 == TX Byte 1 ==
3533 11:13:00.238275 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3534 11:13:00.241451 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3535 11:13:00.244933 ==
3536 11:13:00.247950 Dram Type= 6, Freq= 0, CH_1, rank 1
3537 11:13:00.251027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3538 11:13:00.251146 ==
3539 11:13:00.262139 TX Vref=22, minBit 9, minWin=25, winSum=417
3540 11:13:00.265602 TX Vref=24, minBit 9, minWin=24, winSum=423
3541 11:13:00.269002 TX Vref=26, minBit 1, minWin=26, winSum=426
3542 11:13:00.272279 TX Vref=28, minBit 1, minWin=26, winSum=429
3543 11:13:00.275601 TX Vref=30, minBit 1, minWin=26, winSum=428
3544 11:13:00.282305 TX Vref=32, minBit 1, minWin=26, winSum=428
3545 11:13:00.285636 [TxChooseVref] Worse bit 1, Min win 26, Win sum 429, Final Vref 28
3546 11:13:00.285760
3547 11:13:00.289094 Final TX Range 1 Vref 28
3548 11:13:00.289205
3549 11:13:00.289299 ==
3550 11:13:00.292323 Dram Type= 6, Freq= 0, CH_1, rank 1
3551 11:13:00.295173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3552 11:13:00.298532 ==
3553 11:13:00.298650
3554 11:13:00.298746
3555 11:13:00.298836 TX Vref Scan disable
3556 11:13:00.301843 == TX Byte 0 ==
3557 11:13:00.305234 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3558 11:13:00.311902 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3559 11:13:00.312061 == TX Byte 1 ==
3560 11:13:00.315349 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3561 11:13:00.322098 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3562 11:13:00.322224
3563 11:13:00.322305 [DATLAT]
3564 11:13:00.322370 Freq=1200, CH1 RK1
3565 11:13:00.322430
3566 11:13:00.324842 DATLAT Default: 0xd
3567 11:13:00.328302 0, 0xFFFF, sum = 0
3568 11:13:00.328393 1, 0xFFFF, sum = 0
3569 11:13:00.331821 2, 0xFFFF, sum = 0
3570 11:13:00.331911 3, 0xFFFF, sum = 0
3571 11:13:00.335080 4, 0xFFFF, sum = 0
3572 11:13:00.335172 5, 0xFFFF, sum = 0
3573 11:13:00.338112 6, 0xFFFF, sum = 0
3574 11:13:00.338200 7, 0xFFFF, sum = 0
3575 11:13:00.341548 8, 0xFFFF, sum = 0
3576 11:13:00.341636 9, 0xFFFF, sum = 0
3577 11:13:00.344895 10, 0xFFFF, sum = 0
3578 11:13:00.345020 11, 0xFFFF, sum = 0
3579 11:13:00.348139 12, 0x0, sum = 1
3580 11:13:00.348227 13, 0x0, sum = 2
3581 11:13:00.351444 14, 0x0, sum = 3
3582 11:13:00.351559 15, 0x0, sum = 4
3583 11:13:00.354563 best_step = 13
3584 11:13:00.354644
3585 11:13:00.354721 ==
3586 11:13:00.357831 Dram Type= 6, Freq= 0, CH_1, rank 1
3587 11:13:00.361485 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3588 11:13:00.361600 ==
3589 11:13:00.364615 RX Vref Scan: 0
3590 11:13:00.364715
3591 11:13:00.364784 RX Vref 0 -> 0, step: 1
3592 11:13:00.364846
3593 11:13:00.367514 RX Delay -13 -> 252, step: 4
3594 11:13:00.374265 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3595 11:13:00.377763 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3596 11:13:00.380767 iDelay=195, Bit 2, Center 106 (39 ~ 174) 136
3597 11:13:00.384233 iDelay=195, Bit 3, Center 116 (51 ~ 182) 132
3598 11:13:00.390610 iDelay=195, Bit 4, Center 116 (51 ~ 182) 132
3599 11:13:00.394029 iDelay=195, Bit 5, Center 124 (55 ~ 194) 140
3600 11:13:00.397410 iDelay=195, Bit 6, Center 122 (55 ~ 190) 136
3601 11:13:00.400676 iDelay=195, Bit 7, Center 112 (43 ~ 182) 140
3602 11:13:00.404263 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3603 11:13:00.410733 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3604 11:13:00.414186 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3605 11:13:00.417058 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3606 11:13:00.420391 iDelay=195, Bit 12, Center 120 (59 ~ 182) 124
3607 11:13:00.423712 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3608 11:13:00.430612 iDelay=195, Bit 14, Center 116 (55 ~ 178) 124
3609 11:13:00.433457 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3610 11:13:00.433551 ==
3611 11:13:00.436592 Dram Type= 6, Freq= 0, CH_1, rank 1
3612 11:13:00.440190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3613 11:13:00.440298 ==
3614 11:13:00.443257 DQS Delay:
3615 11:13:00.443344 DQS0 = 0, DQS1 = 0
3616 11:13:00.446489 DQM Delay:
3617 11:13:00.446592 DQM0 = 115, DQM1 = 112
3618 11:13:00.446658 DQ Delay:
3619 11:13:00.449961 DQ0 =118, DQ1 =112, DQ2 =106, DQ3 =116
3620 11:13:00.456451 DQ4 =116, DQ5 =124, DQ6 =122, DQ7 =112
3621 11:13:00.459903 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3622 11:13:00.463233 DQ12 =120, DQ13 =118, DQ14 =116, DQ15 =120
3623 11:13:00.463337
3624 11:13:00.463433
3625 11:13:00.469762 [DQSOSCAuto] RK1, (LSB)MR18= 0xf405, (MSB)MR19= 0x304, tDQSOscB0 = 408 ps tDQSOscB1 = 415 ps
3626 11:13:00.472960 CH1 RK1: MR19=304, MR18=F405
3627 11:13:00.479651 CH1_RK1: MR19=0x304, MR18=0xF405, DQSOSC=408, MR23=63, INC=39, DEC=26
3628 11:13:00.483154 [RxdqsGatingPostProcess] freq 1200
3629 11:13:00.489914 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3630 11:13:00.493152 best DQS0 dly(2T, 0.5T) = (0, 11)
3631 11:13:00.493262 best DQS1 dly(2T, 0.5T) = (0, 11)
3632 11:13:00.495844 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3633 11:13:00.499239 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3634 11:13:00.502626 best DQS0 dly(2T, 0.5T) = (0, 11)
3635 11:13:00.505999 best DQS1 dly(2T, 0.5T) = (0, 11)
3636 11:13:00.509189 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3637 11:13:00.512608 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3638 11:13:00.515933 Pre-setting of DQS Precalculation
3639 11:13:00.522210 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3640 11:13:00.528846 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3641 11:13:00.535727 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3642 11:13:00.535855
3643 11:13:00.535925
3644 11:13:00.538696 [Calibration Summary] 2400 Mbps
3645 11:13:00.538782 CH 0, Rank 0
3646 11:13:00.542590 SW Impedance : PASS
3647 11:13:00.545126 DUTY Scan : NO K
3648 11:13:00.545218 ZQ Calibration : PASS
3649 11:13:00.549010 Jitter Meter : NO K
3650 11:13:00.552272 CBT Training : PASS
3651 11:13:00.552364 Write leveling : PASS
3652 11:13:00.555307 RX DQS gating : PASS
3653 11:13:00.558835 RX DQ/DQS(RDDQC) : PASS
3654 11:13:00.558926 TX DQ/DQS : PASS
3655 11:13:00.562019 RX DATLAT : PASS
3656 11:13:00.565147 RX DQ/DQS(Engine): PASS
3657 11:13:00.565237 TX OE : NO K
3658 11:13:00.568667 All Pass.
3659 11:13:00.568757
3660 11:13:00.568823 CH 0, Rank 1
3661 11:13:00.571768 SW Impedance : PASS
3662 11:13:00.571853 DUTY Scan : NO K
3663 11:13:00.575300 ZQ Calibration : PASS
3664 11:13:00.578552 Jitter Meter : NO K
3665 11:13:00.578641 CBT Training : PASS
3666 11:13:00.581945 Write leveling : PASS
3667 11:13:00.584757 RX DQS gating : PASS
3668 11:13:00.584844 RX DQ/DQS(RDDQC) : PASS
3669 11:13:00.587908 TX DQ/DQS : PASS
3670 11:13:00.591284 RX DATLAT : PASS
3671 11:13:00.591373 RX DQ/DQS(Engine): PASS
3672 11:13:00.594775 TX OE : NO K
3673 11:13:00.594863 All Pass.
3674 11:13:00.594929
3675 11:13:00.598171 CH 1, Rank 0
3676 11:13:00.598256 SW Impedance : PASS
3677 11:13:00.601397 DUTY Scan : NO K
3678 11:13:00.604773 ZQ Calibration : PASS
3679 11:13:00.604867 Jitter Meter : NO K
3680 11:13:00.608057 CBT Training : PASS
3681 11:13:00.611694 Write leveling : PASS
3682 11:13:00.611780 RX DQS gating : PASS
3683 11:13:00.614320 RX DQ/DQS(RDDQC) : PASS
3684 11:13:00.614404 TX DQ/DQS : PASS
3685 11:13:00.617642 RX DATLAT : PASS
3686 11:13:00.620910 RX DQ/DQS(Engine): PASS
3687 11:13:00.621006 TX OE : NO K
3688 11:13:00.624283 All Pass.
3689 11:13:00.624370
3690 11:13:00.624437 CH 1, Rank 1
3691 11:13:00.627768 SW Impedance : PASS
3692 11:13:00.627853 DUTY Scan : NO K
3693 11:13:00.630994 ZQ Calibration : PASS
3694 11:13:00.633971 Jitter Meter : NO K
3695 11:13:00.634058 CBT Training : PASS
3696 11:13:00.637855 Write leveling : PASS
3697 11:13:00.640617 RX DQS gating : PASS
3698 11:13:00.640704 RX DQ/DQS(RDDQC) : PASS
3699 11:13:00.644110 TX DQ/DQS : PASS
3700 11:13:00.647159 RX DATLAT : PASS
3701 11:13:00.647246 RX DQ/DQS(Engine): PASS
3702 11:13:00.650807 TX OE : NO K
3703 11:13:00.650896 All Pass.
3704 11:13:00.650962
3705 11:13:00.654066 DramC Write-DBI off
3706 11:13:00.657275 PER_BANK_REFRESH: Hybrid Mode
3707 11:13:00.657363 TX_TRACKING: ON
3708 11:13:00.666929 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3709 11:13:00.670169 [FAST_K] Save calibration result to emmc
3710 11:13:00.673523 dramc_set_vcore_voltage set vcore to 650000
3711 11:13:00.677025 Read voltage for 600, 5
3712 11:13:00.677114 Vio18 = 0
3713 11:13:00.680014 Vcore = 650000
3714 11:13:00.680123 Vdram = 0
3715 11:13:00.680215 Vddq = 0
3716 11:13:00.680278 Vmddr = 0
3717 11:13:00.686764 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3718 11:13:00.693147 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3719 11:13:00.693264 MEM_TYPE=3, freq_sel=19
3720 11:13:00.696554 sv_algorithm_assistance_LP4_1600
3721 11:13:00.699910 ============ PULL DRAM RESETB DOWN ============
3722 11:13:00.706747 ========== PULL DRAM RESETB DOWN end =========
3723 11:13:00.710043 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3724 11:13:00.712881 ===================================
3725 11:13:00.716414 LPDDR4 DRAM CONFIGURATION
3726 11:13:00.719796 ===================================
3727 11:13:00.719925 EX_ROW_EN[0] = 0x0
3728 11:13:00.722967 EX_ROW_EN[1] = 0x0
3729 11:13:00.723074 LP4Y_EN = 0x0
3730 11:13:00.726247 WORK_FSP = 0x0
3731 11:13:00.729674 WL = 0x2
3732 11:13:00.729780 RL = 0x2
3733 11:13:00.732536 BL = 0x2
3734 11:13:00.732609 RPST = 0x0
3735 11:13:00.735958 RD_PRE = 0x0
3736 11:13:00.736063 WR_PRE = 0x1
3737 11:13:00.739230 WR_PST = 0x0
3738 11:13:00.739304 DBI_WR = 0x0
3739 11:13:00.742687 DBI_RD = 0x0
3740 11:13:00.742789 OTF = 0x1
3741 11:13:00.746077 ===================================
3742 11:13:00.749473 ===================================
3743 11:13:00.752791 ANA top config
3744 11:13:00.755711 ===================================
3745 11:13:00.755820 DLL_ASYNC_EN = 0
3746 11:13:00.758892 ALL_SLAVE_EN = 1
3747 11:13:00.762250 NEW_RANK_MODE = 1
3748 11:13:00.765299 DLL_IDLE_MODE = 1
3749 11:13:00.768757 LP45_APHY_COMB_EN = 1
3750 11:13:00.768867 TX_ODT_DIS = 1
3751 11:13:00.771871 NEW_8X_MODE = 1
3752 11:13:00.775327 ===================================
3753 11:13:00.779016 ===================================
3754 11:13:00.782145 data_rate = 1200
3755 11:13:00.785129 CKR = 1
3756 11:13:00.788778 DQ_P2S_RATIO = 8
3757 11:13:00.791887 ===================================
3758 11:13:00.795253 CA_P2S_RATIO = 8
3759 11:13:00.795368 DQ_CA_OPEN = 0
3760 11:13:00.798590 DQ_SEMI_OPEN = 0
3761 11:13:00.801751 CA_SEMI_OPEN = 0
3762 11:13:00.805114 CA_FULL_RATE = 0
3763 11:13:00.808623 DQ_CKDIV4_EN = 1
3764 11:13:00.811552 CA_CKDIV4_EN = 1
3765 11:13:00.811659 CA_PREDIV_EN = 0
3766 11:13:00.814799 PH8_DLY = 0
3767 11:13:00.818184 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3768 11:13:00.821544 DQ_AAMCK_DIV = 4
3769 11:13:00.824660 CA_AAMCK_DIV = 4
3770 11:13:00.828176 CA_ADMCK_DIV = 4
3771 11:13:00.831531 DQ_TRACK_CA_EN = 0
3772 11:13:00.831639 CA_PICK = 600
3773 11:13:00.834853 CA_MCKIO = 600
3774 11:13:00.837682 MCKIO_SEMI = 0
3775 11:13:00.841169 PLL_FREQ = 2288
3776 11:13:00.844536 DQ_UI_PI_RATIO = 32
3777 11:13:00.847954 CA_UI_PI_RATIO = 0
3778 11:13:00.851312 ===================================
3779 11:13:00.854185 ===================================
3780 11:13:00.854262 memory_type:LPDDR4
3781 11:13:00.857506 GP_NUM : 10
3782 11:13:00.860777 SRAM_EN : 1
3783 11:13:00.860854 MD32_EN : 0
3784 11:13:00.864295 ===================================
3785 11:13:00.867355 [ANA_INIT] >>>>>>>>>>>>>>
3786 11:13:00.870792 <<<<<< [CONFIGURE PHASE]: ANA_TX
3787 11:13:00.874135 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3788 11:13:00.877295 ===================================
3789 11:13:00.880911 data_rate = 1200,PCW = 0X5800
3790 11:13:00.884016 ===================================
3791 11:13:00.887109 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3792 11:13:00.890407 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3793 11:13:00.897505 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3794 11:13:00.904209 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3795 11:13:00.907441 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3796 11:13:00.910178 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3797 11:13:00.910288 [ANA_INIT] flow start
3798 11:13:00.913580 [ANA_INIT] PLL >>>>>>>>
3799 11:13:00.917003 [ANA_INIT] PLL <<<<<<<<
3800 11:13:00.917109 [ANA_INIT] MIDPI >>>>>>>>
3801 11:13:00.920539 [ANA_INIT] MIDPI <<<<<<<<
3802 11:13:00.923623 [ANA_INIT] DLL >>>>>>>>
3803 11:13:00.923710 [ANA_INIT] flow end
3804 11:13:00.930303 ============ LP4 DIFF to SE enter ============
3805 11:13:00.933251 ============ LP4 DIFF to SE exit ============
3806 11:13:00.936668 [ANA_INIT] <<<<<<<<<<<<<
3807 11:13:00.939885 [Flow] Enable top DCM control >>>>>
3808 11:13:00.943278 [Flow] Enable top DCM control <<<<<
3809 11:13:00.943380 Enable DLL master slave shuffle
3810 11:13:00.949999 ==============================================================
3811 11:13:00.952810 Gating Mode config
3812 11:13:00.956136 ==============================================================
3813 11:13:00.959502 Config description:
3814 11:13:00.969656 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3815 11:13:00.976046 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3816 11:13:00.979105 SELPH_MODE 0: By rank 1: By Phase
3817 11:13:00.985827 ==============================================================
3818 11:13:00.988915 GAT_TRACK_EN = 1
3819 11:13:00.992589 RX_GATING_MODE = 2
3820 11:13:00.996274 RX_GATING_TRACK_MODE = 2
3821 11:13:00.999122 SELPH_MODE = 1
3822 11:13:01.002808 PICG_EARLY_EN = 1
3823 11:13:01.005776 VALID_LAT_VALUE = 1
3824 11:13:01.008867 ==============================================================
3825 11:13:01.012568 Enter into Gating configuration >>>>
3826 11:13:01.015911 Exit from Gating configuration <<<<
3827 11:13:01.018829 Enter into DVFS_PRE_config >>>>>
3828 11:13:01.032307 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3829 11:13:01.032456 Exit from DVFS_PRE_config <<<<<
3830 11:13:01.035602 Enter into PICG configuration >>>>
3831 11:13:01.038920 Exit from PICG configuration <<<<
3832 11:13:01.042360 [RX_INPUT] configuration >>>>>
3833 11:13:01.045100 [RX_INPUT] configuration <<<<<
3834 11:13:01.051856 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3835 11:13:01.055317 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3836 11:13:01.061520 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3837 11:13:01.068149 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3838 11:13:01.074934 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3839 11:13:01.081728 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3840 11:13:01.084831 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3841 11:13:01.087930 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3842 11:13:01.091510 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3843 11:13:01.098063 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3844 11:13:01.101037 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3845 11:13:01.104522 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3846 11:13:01.107845 ===================================
3847 11:13:01.110986 LPDDR4 DRAM CONFIGURATION
3848 11:13:01.114655 ===================================
3849 11:13:01.117688 EX_ROW_EN[0] = 0x0
3850 11:13:01.117843 EX_ROW_EN[1] = 0x0
3851 11:13:01.120913 LP4Y_EN = 0x0
3852 11:13:01.121008 WORK_FSP = 0x0
3853 11:13:01.124276 WL = 0x2
3854 11:13:01.124355 RL = 0x2
3855 11:13:01.127714 BL = 0x2
3856 11:13:01.127799 RPST = 0x0
3857 11:13:01.130927 RD_PRE = 0x0
3858 11:13:01.131027 WR_PRE = 0x1
3859 11:13:01.134270 WR_PST = 0x0
3860 11:13:01.137600 DBI_WR = 0x0
3861 11:13:01.137680 DBI_RD = 0x0
3862 11:13:01.140974 OTF = 0x1
3863 11:13:01.144142 ===================================
3864 11:13:01.147191 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3865 11:13:01.150484 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3866 11:13:01.153838 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3867 11:13:01.157097 ===================================
3868 11:13:01.160551 LPDDR4 DRAM CONFIGURATION
3869 11:13:01.163897 ===================================
3870 11:13:01.166862 EX_ROW_EN[0] = 0x10
3871 11:13:01.166965 EX_ROW_EN[1] = 0x0
3872 11:13:01.170099 LP4Y_EN = 0x0
3873 11:13:01.170185 WORK_FSP = 0x0
3874 11:13:01.173420 WL = 0x2
3875 11:13:01.173504 RL = 0x2
3876 11:13:01.176808 BL = 0x2
3877 11:13:01.176895 RPST = 0x0
3878 11:13:01.180264 RD_PRE = 0x0
3879 11:13:01.183529 WR_PRE = 0x1
3880 11:13:01.183616 WR_PST = 0x0
3881 11:13:01.186835 DBI_WR = 0x0
3882 11:13:01.186947 DBI_RD = 0x0
3883 11:13:01.190423 OTF = 0x1
3884 11:13:01.193285 ===================================
3885 11:13:01.196990 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3886 11:13:01.202049 nWR fixed to 30
3887 11:13:01.205271 [ModeRegInit_LP4] CH0 RK0
3888 11:13:01.205384 [ModeRegInit_LP4] CH0 RK1
3889 11:13:01.208897 [ModeRegInit_LP4] CH1 RK0
3890 11:13:01.211980 [ModeRegInit_LP4] CH1 RK1
3891 11:13:01.212102 match AC timing 17
3892 11:13:01.218782 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3893 11:13:01.221934 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3894 11:13:01.224982 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3895 11:13:01.231791 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3896 11:13:01.235130 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3897 11:13:01.235233 ==
3898 11:13:01.238570 Dram Type= 6, Freq= 0, CH_0, rank 0
3899 11:13:01.241908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3900 11:13:01.242004 ==
3901 11:13:01.248069 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3902 11:13:01.254886 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3903 11:13:01.258295 [CA 0] Center 36 (6~67) winsize 62
3904 11:13:01.261148 [CA 1] Center 36 (5~67) winsize 63
3905 11:13:01.264470 [CA 2] Center 34 (4~65) winsize 62
3906 11:13:01.267929 [CA 3] Center 34 (4~65) winsize 62
3907 11:13:01.271192 [CA 4] Center 33 (3~64) winsize 62
3908 11:13:01.274523 [CA 5] Center 33 (3~64) winsize 62
3909 11:13:01.274617
3910 11:13:01.277904 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3911 11:13:01.278021
3912 11:13:01.281239 [CATrainingPosCal] consider 1 rank data
3913 11:13:01.284610 u2DelayCellTimex100 = 270/100 ps
3914 11:13:01.287488 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3915 11:13:01.290762 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
3916 11:13:01.294044 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3917 11:13:01.300744 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3918 11:13:01.303941 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3919 11:13:01.307544 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3920 11:13:01.307643
3921 11:13:01.310714 CA PerBit enable=1, Macro0, CA PI delay=33
3922 11:13:01.310835
3923 11:13:01.314277 [CBTSetCACLKResult] CA Dly = 33
3924 11:13:01.314412 CS Dly: 5 (0~36)
3925 11:13:01.317131 ==
3926 11:13:01.317238 Dram Type= 6, Freq= 0, CH_0, rank 1
3927 11:13:01.323647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3928 11:13:01.323761 ==
3929 11:13:01.327383 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3930 11:13:01.333432 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3931 11:13:01.337442 [CA 0] Center 36 (6~67) winsize 62
3932 11:13:01.340534 [CA 1] Center 36 (6~67) winsize 62
3933 11:13:01.343859 [CA 2] Center 34 (4~65) winsize 62
3934 11:13:01.347178 [CA 3] Center 34 (4~65) winsize 62
3935 11:13:01.350541 [CA 4] Center 34 (3~65) winsize 63
3936 11:13:01.354002 [CA 5] Center 33 (3~64) winsize 62
3937 11:13:01.354085
3938 11:13:01.357391 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3939 11:13:01.357473
3940 11:13:01.360806 [CATrainingPosCal] consider 2 rank data
3941 11:13:01.364232 u2DelayCellTimex100 = 270/100 ps
3942 11:13:01.367043 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3943 11:13:01.373898 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3944 11:13:01.377186 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3945 11:13:01.380382 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3946 11:13:01.383676 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3947 11:13:01.387016 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3948 11:13:01.387108
3949 11:13:01.389877 CA PerBit enable=1, Macro0, CA PI delay=33
3950 11:13:01.389969
3951 11:13:01.393373 [CBTSetCACLKResult] CA Dly = 33
3952 11:13:01.396538 CS Dly: 5 (0~37)
3953 11:13:01.396634
3954 11:13:01.399842 ----->DramcWriteLeveling(PI) begin...
3955 11:13:01.399933 ==
3956 11:13:01.403146 Dram Type= 6, Freq= 0, CH_0, rank 0
3957 11:13:01.406524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3958 11:13:01.406617 ==
3959 11:13:01.409970 Write leveling (Byte 0): 34 => 34
3960 11:13:01.413194 Write leveling (Byte 1): 33 => 33
3961 11:13:01.416347 DramcWriteLeveling(PI) end<-----
3962 11:13:01.416444
3963 11:13:01.416511 ==
3964 11:13:01.419823 Dram Type= 6, Freq= 0, CH_0, rank 0
3965 11:13:01.423142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3966 11:13:01.423238 ==
3967 11:13:01.426394 [Gating] SW mode calibration
3968 11:13:01.432904 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3969 11:13:01.439451 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3970 11:13:01.442740 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3971 11:13:01.445819 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3972 11:13:01.452900 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3973 11:13:01.455725 0 9 12 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 0)
3974 11:13:01.462595 0 9 16 | B1->B0 | 2e2e 2727 | 0 0 | (0 1) (1 1)
3975 11:13:01.466055 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3976 11:13:01.468996 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3977 11:13:01.475725 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3978 11:13:01.479185 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3979 11:13:01.482489 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3980 11:13:01.485946 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3981 11:13:01.492606 0 10 12 | B1->B0 | 2323 2d2c | 0 1 | (0 0) (0 0)
3982 11:13:01.495417 0 10 16 | B1->B0 | 3939 4444 | 0 0 | (1 1) (0 0)
3983 11:13:01.498815 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3984 11:13:01.505162 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3985 11:13:01.508529 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3986 11:13:01.511996 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3987 11:13:01.518571 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3988 11:13:01.521805 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3989 11:13:01.525169 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3990 11:13:01.531536 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3991 11:13:01.535116 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3992 11:13:01.538272 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3993 11:13:01.544950 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3994 11:13:01.548486 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 11:13:01.551576 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 11:13:01.558180 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 11:13:01.561231 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 11:13:01.564664 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 11:13:01.571255 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 11:13:01.574821 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 11:13:01.581001 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 11:13:01.584568 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 11:13:01.587748 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 11:13:01.594532 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 11:13:01.597430 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 11:13:01.601171 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4007 11:13:01.604554 Total UI for P1: 0, mck2ui 16
4008 11:13:01.607866 best dqsien dly found for B0: ( 0, 13, 14)
4009 11:13:01.610621 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4010 11:13:01.613994 Total UI for P1: 0, mck2ui 16
4011 11:13:01.617552 best dqsien dly found for B1: ( 0, 13, 16)
4012 11:13:01.624005 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4013 11:13:01.627309 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4014 11:13:01.627446
4015 11:13:01.631017 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4016 11:13:01.633859 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4017 11:13:01.637042 [Gating] SW calibration Done
4018 11:13:01.637156 ==
4019 11:13:01.640279 Dram Type= 6, Freq= 0, CH_0, rank 0
4020 11:13:01.643388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4021 11:13:01.643472 ==
4022 11:13:01.647019 RX Vref Scan: 0
4023 11:13:01.647095
4024 11:13:01.647155 RX Vref 0 -> 0, step: 1
4025 11:13:01.647212
4026 11:13:01.650127 RX Delay -230 -> 252, step: 16
4027 11:13:01.656714 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4028 11:13:01.660270 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4029 11:13:01.663442 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4030 11:13:01.666591 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4031 11:13:01.673425 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4032 11:13:01.676292 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4033 11:13:01.679979 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4034 11:13:01.683359 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4035 11:13:01.686797 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4036 11:13:01.693011 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4037 11:13:01.696342 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4038 11:13:01.699782 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4039 11:13:01.703231 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4040 11:13:01.709750 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4041 11:13:01.712638 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4042 11:13:01.716554 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4043 11:13:01.716665 ==
4044 11:13:01.719261 Dram Type= 6, Freq= 0, CH_0, rank 0
4045 11:13:01.722703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4046 11:13:01.725878 ==
4047 11:13:01.725994 DQS Delay:
4048 11:13:01.726087 DQS0 = 0, DQS1 = 0
4049 11:13:01.729347 DQM Delay:
4050 11:13:01.729426 DQM0 = 43, DQM1 = 33
4051 11:13:01.732664 DQ Delay:
4052 11:13:01.735829 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4053 11:13:01.735931 DQ4 =49, DQ5 =33, DQ6 =57, DQ7 =57
4054 11:13:01.739197 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33
4055 11:13:01.742754 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =33
4056 11:13:01.745918
4057 11:13:01.745995
4058 11:13:01.746060 ==
4059 11:13:01.749021 Dram Type= 6, Freq= 0, CH_0, rank 0
4060 11:13:01.752411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4061 11:13:01.752496 ==
4062 11:13:01.752559
4063 11:13:01.752619
4064 11:13:01.755866 TX Vref Scan disable
4065 11:13:01.755936 == TX Byte 0 ==
4066 11:13:01.762162 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4067 11:13:01.765320 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4068 11:13:01.765403 == TX Byte 1 ==
4069 11:13:01.772122 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4070 11:13:01.775476 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4071 11:13:01.775560 ==
4072 11:13:01.778987 Dram Type= 6, Freq= 0, CH_0, rank 0
4073 11:13:01.782327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4074 11:13:01.782418 ==
4075 11:13:01.785011
4076 11:13:01.785082
4077 11:13:01.785147 TX Vref Scan disable
4078 11:13:01.788931 == TX Byte 0 ==
4079 11:13:01.792459 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4080 11:13:01.799240 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4081 11:13:01.799348 == TX Byte 1 ==
4082 11:13:01.801830 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4083 11:13:01.808603 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4084 11:13:01.808719
4085 11:13:01.808788 [DATLAT]
4086 11:13:01.808848 Freq=600, CH0 RK0
4087 11:13:01.808922
4088 11:13:01.812233 DATLAT Default: 0x9
4089 11:13:01.815210 0, 0xFFFF, sum = 0
4090 11:13:01.815315 1, 0xFFFF, sum = 0
4091 11:13:01.818525 2, 0xFFFF, sum = 0
4092 11:13:01.818614 3, 0xFFFF, sum = 0
4093 11:13:01.821917 4, 0xFFFF, sum = 0
4094 11:13:01.822017 5, 0xFFFF, sum = 0
4095 11:13:01.824852 6, 0xFFFF, sum = 0
4096 11:13:01.824934 7, 0xFFFF, sum = 0
4097 11:13:01.828147 8, 0x0, sum = 1
4098 11:13:01.828223 9, 0x0, sum = 2
4099 11:13:01.831450 10, 0x0, sum = 3
4100 11:13:01.831527 11, 0x0, sum = 4
4101 11:13:01.831590 best_step = 9
4102 11:13:01.831648
4103 11:13:01.834566 ==
4104 11:13:01.838091 Dram Type= 6, Freq= 0, CH_0, rank 0
4105 11:13:01.841506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4106 11:13:01.841601 ==
4107 11:13:01.841669 RX Vref Scan: 1
4108 11:13:01.841730
4109 11:13:01.844890 RX Vref 0 -> 0, step: 1
4110 11:13:01.844973
4111 11:13:01.848151 RX Delay -195 -> 252, step: 8
4112 11:13:01.848311
4113 11:13:01.851495 Set Vref, RX VrefLevel [Byte0]: 51
4114 11:13:01.854815 [Byte1]: 47
4115 11:13:01.854906
4116 11:13:01.857838 Final RX Vref Byte 0 = 51 to rank0
4117 11:13:01.861076 Final RX Vref Byte 1 = 47 to rank0
4118 11:13:01.864258 Final RX Vref Byte 0 = 51 to rank1
4119 11:13:01.867952 Final RX Vref Byte 1 = 47 to rank1==
4120 11:13:01.871181 Dram Type= 6, Freq= 0, CH_0, rank 0
4121 11:13:01.877769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4122 11:13:01.877884 ==
4123 11:13:01.877953 DQS Delay:
4124 11:13:01.878014 DQS0 = 0, DQS1 = 0
4125 11:13:01.881050 DQM Delay:
4126 11:13:01.881136 DQM0 = 42, DQM1 = 34
4127 11:13:01.884382 DQ Delay:
4128 11:13:01.887730 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =40
4129 11:13:01.890605 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4130 11:13:01.894089 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =28
4131 11:13:01.897452 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =44
4132 11:13:01.897545
4133 11:13:01.897611
4134 11:13:01.903987 [DQSOSCAuto] RK0, (LSB)MR18= 0x4940, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 396 ps
4135 11:13:01.906970 CH0 RK0: MR19=808, MR18=4940
4136 11:13:01.913696 CH0_RK0: MR19=0x808, MR18=0x4940, DQSOSC=396, MR23=63, INC=167, DEC=111
4137 11:13:01.913804
4138 11:13:01.916849 ----->DramcWriteLeveling(PI) begin...
4139 11:13:01.916982 ==
4140 11:13:01.920760 Dram Type= 6, Freq= 0, CH_0, rank 1
4141 11:13:01.923556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4142 11:13:01.923652 ==
4143 11:13:01.926856 Write leveling (Byte 0): 33 => 33
4144 11:13:01.930226 Write leveling (Byte 1): 33 => 33
4145 11:13:01.933609 DramcWriteLeveling(PI) end<-----
4146 11:13:01.933700
4147 11:13:01.933766 ==
4148 11:13:01.936815 Dram Type= 6, Freq= 0, CH_0, rank 1
4149 11:13:01.940014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4150 11:13:01.943527 ==
4151 11:13:01.943617 [Gating] SW mode calibration
4152 11:13:01.953146 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4153 11:13:01.956837 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4154 11:13:01.959883 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4155 11:13:01.966132 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4156 11:13:01.969507 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4157 11:13:01.973093 0 9 12 | B1->B0 | 3434 3232 | 0 1 | (0 1) (1 0)
4158 11:13:01.979396 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (1 1) (0 0)
4159 11:13:01.982754 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4160 11:13:01.986129 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4161 11:13:01.992679 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4162 11:13:01.996192 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4163 11:13:01.999065 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4164 11:13:02.005532 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4165 11:13:02.008833 0 10 12 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
4166 11:13:02.012344 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4167 11:13:02.018974 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4168 11:13:02.022201 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4169 11:13:02.025529 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4170 11:13:02.032163 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4171 11:13:02.035507 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4172 11:13:02.038959 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4173 11:13:02.045410 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4174 11:13:02.048743 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4175 11:13:02.052054 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4176 11:13:02.058962 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4177 11:13:02.061670 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4178 11:13:02.065351 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 11:13:02.071701 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 11:13:02.074842 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 11:13:02.078429 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 11:13:02.084869 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 11:13:02.088228 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 11:13:02.091825 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 11:13:02.097848 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 11:13:02.101841 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 11:13:02.105045 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 11:13:02.111181 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 11:13:02.114578 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 11:13:02.117994 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4191 11:13:02.121517 Total UI for P1: 0, mck2ui 16
4192 11:13:02.124802 best dqsien dly found for B0: ( 0, 13, 14)
4193 11:13:02.127920 Total UI for P1: 0, mck2ui 16
4194 11:13:02.130951 best dqsien dly found for B1: ( 0, 13, 14)
4195 11:13:02.134204 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4196 11:13:02.140729 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4197 11:13:02.140839
4198 11:13:02.144040 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4199 11:13:02.147390 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4200 11:13:02.150642 [Gating] SW calibration Done
4201 11:13:02.150747 ==
4202 11:13:02.154105 Dram Type= 6, Freq= 0, CH_0, rank 1
4203 11:13:02.157595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4204 11:13:02.157674 ==
4205 11:13:02.160564 RX Vref Scan: 0
4206 11:13:02.160650
4207 11:13:02.160710 RX Vref 0 -> 0, step: 1
4208 11:13:02.160768
4209 11:13:02.164231 RX Delay -230 -> 252, step: 16
4210 11:13:02.167709 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4211 11:13:02.174133 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4212 11:13:02.177218 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4213 11:13:02.180885 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4214 11:13:02.183848 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4215 11:13:02.190657 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4216 11:13:02.193478 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4217 11:13:02.196995 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4218 11:13:02.200454 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4219 11:13:02.206604 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4220 11:13:02.209860 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4221 11:13:02.213274 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4222 11:13:02.216638 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4223 11:13:02.223193 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4224 11:13:02.226604 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4225 11:13:02.229823 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4226 11:13:02.229909 ==
4227 11:13:02.233049 Dram Type= 6, Freq= 0, CH_0, rank 1
4228 11:13:02.236623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4229 11:13:02.239945 ==
4230 11:13:02.240039 DQS Delay:
4231 11:13:02.240108 DQS0 = 0, DQS1 = 0
4232 11:13:02.242743 DQM Delay:
4233 11:13:02.242825 DQM0 = 41, DQM1 = 32
4234 11:13:02.246023 DQ Delay:
4235 11:13:02.249348 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4236 11:13:02.249440 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4237 11:13:02.252698 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4238 11:13:02.259534 DQ12 =33, DQ13 =41, DQ14 =41, DQ15 =41
4239 11:13:02.259634
4240 11:13:02.259702
4241 11:13:02.259768 ==
4242 11:13:02.262310 Dram Type= 6, Freq= 0, CH_0, rank 1
4243 11:13:02.265639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4244 11:13:02.265727 ==
4245 11:13:02.265795
4246 11:13:02.265856
4247 11:13:02.268939 TX Vref Scan disable
4248 11:13:02.269020 == TX Byte 0 ==
4249 11:13:02.275562 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4250 11:13:02.278922 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4251 11:13:02.279021 == TX Byte 1 ==
4252 11:13:02.285620 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4253 11:13:02.288812 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4254 11:13:02.288910 ==
4255 11:13:02.292370 Dram Type= 6, Freq= 0, CH_0, rank 1
4256 11:13:02.295560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4257 11:13:02.295657 ==
4258 11:13:02.295724
4259 11:13:02.298636
4260 11:13:02.298723 TX Vref Scan disable
4261 11:13:02.302278 == TX Byte 0 ==
4262 11:13:02.305604 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4263 11:13:02.312424 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4264 11:13:02.312533 == TX Byte 1 ==
4265 11:13:02.315732 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4266 11:13:02.321956 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4267 11:13:02.322076
4268 11:13:02.322143 [DATLAT]
4269 11:13:02.322205 Freq=600, CH0 RK1
4270 11:13:02.322265
4271 11:13:02.325311 DATLAT Default: 0x9
4272 11:13:02.328654 0, 0xFFFF, sum = 0
4273 11:13:02.328747 1, 0xFFFF, sum = 0
4274 11:13:02.331980 2, 0xFFFF, sum = 0
4275 11:13:02.332083 3, 0xFFFF, sum = 0
4276 11:13:02.335221 4, 0xFFFF, sum = 0
4277 11:13:02.335310 5, 0xFFFF, sum = 0
4278 11:13:02.338782 6, 0xFFFF, sum = 0
4279 11:13:02.338897 7, 0xFFFF, sum = 0
4280 11:13:02.342132 8, 0x0, sum = 1
4281 11:13:02.342220 9, 0x0, sum = 2
4282 11:13:02.345590 10, 0x0, sum = 3
4283 11:13:02.345691 11, 0x0, sum = 4
4284 11:13:02.345759 best_step = 9
4285 11:13:02.345820
4286 11:13:02.348354 ==
4287 11:13:02.351764 Dram Type= 6, Freq= 0, CH_0, rank 1
4288 11:13:02.354804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4289 11:13:02.354923 ==
4290 11:13:02.354990 RX Vref Scan: 0
4291 11:13:02.355051
4292 11:13:02.358102 RX Vref 0 -> 0, step: 1
4293 11:13:02.358230
4294 11:13:02.361395 RX Delay -195 -> 252, step: 8
4295 11:13:02.368042 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4296 11:13:02.371481 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4297 11:13:02.374928 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4298 11:13:02.378277 iDelay=205, Bit 3, Center 40 (-107 ~ 188) 296
4299 11:13:02.381578 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4300 11:13:02.387939 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4301 11:13:02.391757 iDelay=205, Bit 6, Center 52 (-99 ~ 204) 304
4302 11:13:02.394839 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4303 11:13:02.397893 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4304 11:13:02.404715 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4305 11:13:02.407955 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4306 11:13:02.411329 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4307 11:13:02.414168 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4308 11:13:02.420978 iDelay=205, Bit 13, Center 40 (-107 ~ 188) 296
4309 11:13:02.424325 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4310 11:13:02.427582 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4311 11:13:02.427735 ==
4312 11:13:02.430993 Dram Type= 6, Freq= 0, CH_0, rank 1
4313 11:13:02.433973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4314 11:13:02.437578 ==
4315 11:13:02.437687 DQS Delay:
4316 11:13:02.437778 DQS0 = 0, DQS1 = 0
4317 11:13:02.441048 DQM Delay:
4318 11:13:02.441158 DQM0 = 41, DQM1 = 34
4319 11:13:02.444057 DQ Delay:
4320 11:13:02.447394 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4321 11:13:02.447477 DQ4 =44, DQ5 =28, DQ6 =52, DQ7 =44
4322 11:13:02.450678 DQ8 =24, DQ9 =20, DQ10 =36, DQ11 =28
4323 11:13:02.457196 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4324 11:13:02.457315
4325 11:13:02.457408
4326 11:13:02.463920 [DQSOSCAuto] RK1, (LSB)MR18= 0x443e, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
4327 11:13:02.467608 CH0 RK1: MR19=808, MR18=443E
4328 11:13:02.473672 CH0_RK1: MR19=0x808, MR18=0x443E, DQSOSC=396, MR23=63, INC=167, DEC=111
4329 11:13:02.476974 [RxdqsGatingPostProcess] freq 600
4330 11:13:02.480222 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4331 11:13:02.483558 Pre-setting of DQS Precalculation
4332 11:13:02.490080 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4333 11:13:02.490214 ==
4334 11:13:02.493342 Dram Type= 6, Freq= 0, CH_1, rank 0
4335 11:13:02.496571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4336 11:13:02.496660 ==
4337 11:13:02.503548 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4338 11:13:02.509668 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4339 11:13:02.513108 [CA 0] Center 35 (5~66) winsize 62
4340 11:13:02.516502 [CA 1] Center 35 (5~66) winsize 62
4341 11:13:02.519933 [CA 2] Center 34 (4~65) winsize 62
4342 11:13:02.522925 [CA 3] Center 34 (4~65) winsize 62
4343 11:13:02.525981 [CA 4] Center 34 (4~65) winsize 62
4344 11:13:02.529351 [CA 5] Center 34 (3~65) winsize 63
4345 11:13:02.529456
4346 11:13:02.532778 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4347 11:13:02.532851
4348 11:13:02.536062 [CATrainingPosCal] consider 1 rank data
4349 11:13:02.539197 u2DelayCellTimex100 = 270/100 ps
4350 11:13:02.542617 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4351 11:13:02.545737 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4352 11:13:02.549035 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4353 11:13:02.552448 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4354 11:13:02.555910 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4355 11:13:02.559165 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4356 11:13:02.559268
4357 11:13:02.565612 CA PerBit enable=1, Macro0, CA PI delay=34
4358 11:13:02.565703
4359 11:13:02.565768 [CBTSetCACLKResult] CA Dly = 34
4360 11:13:02.569014 CS Dly: 4 (0~35)
4361 11:13:02.569101 ==
4362 11:13:02.572320 Dram Type= 6, Freq= 0, CH_1, rank 1
4363 11:13:02.575650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4364 11:13:02.575754 ==
4365 11:13:02.582580 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4366 11:13:02.588603 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4367 11:13:02.592274 [CA 0] Center 35 (5~66) winsize 62
4368 11:13:02.595242 [CA 1] Center 36 (6~66) winsize 61
4369 11:13:02.598871 [CA 2] Center 34 (4~65) winsize 62
4370 11:13:02.602176 [CA 3] Center 34 (3~65) winsize 63
4371 11:13:02.605382 [CA 4] Center 34 (4~65) winsize 62
4372 11:13:02.608503 [CA 5] Center 34 (3~65) winsize 63
4373 11:13:02.608601
4374 11:13:02.612260 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4375 11:13:02.612355
4376 11:13:02.615370 [CATrainingPosCal] consider 2 rank data
4377 11:13:02.618410 u2DelayCellTimex100 = 270/100 ps
4378 11:13:02.621535 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4379 11:13:02.625119 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4380 11:13:02.628285 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4381 11:13:02.631628 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4382 11:13:02.638509 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4383 11:13:02.641272 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4384 11:13:02.641358
4385 11:13:02.644712 CA PerBit enable=1, Macro0, CA PI delay=34
4386 11:13:02.644795
4387 11:13:02.647875 [CBTSetCACLKResult] CA Dly = 34
4388 11:13:02.647955 CS Dly: 4 (0~36)
4389 11:13:02.648018
4390 11:13:02.651421 ----->DramcWriteLeveling(PI) begin...
4391 11:13:02.651514 ==
4392 11:13:02.654757 Dram Type= 6, Freq= 0, CH_1, rank 0
4393 11:13:02.661009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4394 11:13:02.661110 ==
4395 11:13:02.664379 Write leveling (Byte 0): 29 => 29
4396 11:13:02.668120 Write leveling (Byte 1): 31 => 31
4397 11:13:02.668215 DramcWriteLeveling(PI) end<-----
4398 11:13:02.671035
4399 11:13:02.671115 ==
4400 11:13:02.674394 Dram Type= 6, Freq= 0, CH_1, rank 0
4401 11:13:02.677650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4402 11:13:02.677738 ==
4403 11:13:02.680989 [Gating] SW mode calibration
4404 11:13:02.687789 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4405 11:13:02.690649 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4406 11:13:02.697486 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4407 11:13:02.700794 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4408 11:13:02.703952 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4409 11:13:02.710407 0 9 12 | B1->B0 | 2f2f 2f2f | 1 0 | (1 0) (0 0)
4410 11:13:02.714012 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4411 11:13:02.717131 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4412 11:13:02.723524 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4413 11:13:02.727138 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4414 11:13:02.730328 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4415 11:13:02.736872 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4416 11:13:02.740214 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4417 11:13:02.743575 0 10 12 | B1->B0 | 2b2b 3838 | 0 0 | (0 0) (0 0)
4418 11:13:02.750268 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4419 11:13:02.753489 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4420 11:13:02.756836 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4421 11:13:02.763546 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4422 11:13:02.767076 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4423 11:13:02.770208 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4424 11:13:02.776901 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 11:13:02.780337 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4426 11:13:02.783197 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4427 11:13:02.789942 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4428 11:13:02.793341 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4429 11:13:02.796749 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 11:13:02.802879 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 11:13:02.806378 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 11:13:02.809522 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 11:13:02.815931 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 11:13:02.819460 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 11:13:02.822547 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 11:13:02.829684 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 11:13:02.832515 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 11:13:02.835617 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 11:13:02.842512 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 11:13:02.846039 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 11:13:02.852179 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4442 11:13:02.852289 Total UI for P1: 0, mck2ui 16
4443 11:13:02.855621 best dqsien dly found for B0: ( 0, 13, 10)
4444 11:13:02.862085 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4445 11:13:02.865390 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4446 11:13:02.868813 Total UI for P1: 0, mck2ui 16
4447 11:13:02.872027 best dqsien dly found for B1: ( 0, 13, 14)
4448 11:13:02.875372 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4449 11:13:02.878484 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4450 11:13:02.878580
4451 11:13:02.885326 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4452 11:13:02.888729 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4453 11:13:02.888835 [Gating] SW calibration Done
4454 11:13:02.891619 ==
4455 11:13:02.894957 Dram Type= 6, Freq= 0, CH_1, rank 0
4456 11:13:02.898316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4457 11:13:02.898426 ==
4458 11:13:02.898528 RX Vref Scan: 0
4459 11:13:02.898617
4460 11:13:02.901690 RX Vref 0 -> 0, step: 1
4461 11:13:02.901787
4462 11:13:02.905078 RX Delay -230 -> 252, step: 16
4463 11:13:02.908549 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4464 11:13:02.911713 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4465 11:13:02.918341 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4466 11:13:02.921356 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4467 11:13:02.924905 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4468 11:13:02.927996 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4469 11:13:02.934662 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4470 11:13:02.937948 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4471 11:13:02.941060 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4472 11:13:02.944089 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4473 11:13:02.950869 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4474 11:13:02.954269 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4475 11:13:02.957641 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4476 11:13:02.960864 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4477 11:13:02.967597 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4478 11:13:02.970987 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4479 11:13:02.971081 ==
4480 11:13:02.973811 Dram Type= 6, Freq= 0, CH_1, rank 0
4481 11:13:02.977107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4482 11:13:02.977189 ==
4483 11:13:02.980799 DQS Delay:
4484 11:13:02.980883 DQS0 = 0, DQS1 = 0
4485 11:13:02.980947 DQM Delay:
4486 11:13:02.984007 DQM0 = 43, DQM1 = 39
4487 11:13:02.984099 DQ Delay:
4488 11:13:02.987018 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4489 11:13:02.990308 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4490 11:13:02.993665 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4491 11:13:02.997209 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4492 11:13:02.997303
4493 11:13:02.997369
4494 11:13:02.997445 ==
4495 11:13:03.000619 Dram Type= 6, Freq= 0, CH_1, rank 0
4496 11:13:03.006860 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4497 11:13:03.006954 ==
4498 11:13:03.007020
4499 11:13:03.007084
4500 11:13:03.007143 TX Vref Scan disable
4501 11:13:03.010783 == TX Byte 0 ==
4502 11:13:03.014129 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4503 11:13:03.020538 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4504 11:13:03.020645 == TX Byte 1 ==
4505 11:13:03.024179 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4506 11:13:03.030439 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4507 11:13:03.030559 ==
4508 11:13:03.033690 Dram Type= 6, Freq= 0, CH_1, rank 0
4509 11:13:03.036818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4510 11:13:03.036928 ==
4511 11:13:03.036998
4512 11:13:03.037060
4513 11:13:03.040229 TX Vref Scan disable
4514 11:13:03.043885 == TX Byte 0 ==
4515 11:13:03.046926 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4516 11:13:03.050039 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4517 11:13:03.053823 == TX Byte 1 ==
4518 11:13:03.056961 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4519 11:13:03.059993 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4520 11:13:03.060078
4521 11:13:03.060140 [DATLAT]
4522 11:13:03.063350 Freq=600, CH1 RK0
4523 11:13:03.063452
4524 11:13:03.066932 DATLAT Default: 0x9
4525 11:13:03.067004 0, 0xFFFF, sum = 0
4526 11:13:03.069863 1, 0xFFFF, sum = 0
4527 11:13:03.069941 2, 0xFFFF, sum = 0
4528 11:13:03.073350 3, 0xFFFF, sum = 0
4529 11:13:03.073424 4, 0xFFFF, sum = 0
4530 11:13:03.076680 5, 0xFFFF, sum = 0
4531 11:13:03.076786 6, 0xFFFF, sum = 0
4532 11:13:03.080012 7, 0xFFFF, sum = 0
4533 11:13:03.080112 8, 0x0, sum = 1
4534 11:13:03.083150 9, 0x0, sum = 2
4535 11:13:03.083221 10, 0x0, sum = 3
4536 11:13:03.086404 11, 0x0, sum = 4
4537 11:13:03.086506 best_step = 9
4538 11:13:03.086567
4539 11:13:03.086640 ==
4540 11:13:03.089839 Dram Type= 6, Freq= 0, CH_1, rank 0
4541 11:13:03.093270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4542 11:13:03.093360 ==
4543 11:13:03.096070 RX Vref Scan: 1
4544 11:13:03.096176
4545 11:13:03.099482 RX Vref 0 -> 0, step: 1
4546 11:13:03.099551
4547 11:13:03.102910 RX Delay -179 -> 252, step: 8
4548 11:13:03.102991
4549 11:13:03.106199 Set Vref, RX VrefLevel [Byte0]: 52
4550 11:13:03.106267 [Byte1]: 52
4551 11:13:03.111325
4552 11:13:03.111409 Final RX Vref Byte 0 = 52 to rank0
4553 11:13:03.114765 Final RX Vref Byte 1 = 52 to rank0
4554 11:13:03.118096 Final RX Vref Byte 0 = 52 to rank1
4555 11:13:03.121233 Final RX Vref Byte 1 = 52 to rank1==
4556 11:13:03.124560 Dram Type= 6, Freq= 0, CH_1, rank 0
4557 11:13:03.131387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4558 11:13:03.131512 ==
4559 11:13:03.131581 DQS Delay:
4560 11:13:03.131654 DQS0 = 0, DQS1 = 0
4561 11:13:03.134335 DQM Delay:
4562 11:13:03.134426 DQM0 = 42, DQM1 = 34
4563 11:13:03.137383 DQ Delay:
4564 11:13:03.141031 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4565 11:13:03.144129 DQ4 =36, DQ5 =48, DQ6 =56, DQ7 =36
4566 11:13:03.147648 DQ8 =20, DQ9 =24, DQ10 =32, DQ11 =28
4567 11:13:03.150562 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =40
4568 11:13:03.150651
4569 11:13:03.150724
4570 11:13:03.157483 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b44, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 401 ps
4571 11:13:03.161034 CH1 RK0: MR19=808, MR18=2B44
4572 11:13:03.167589 CH1_RK0: MR19=0x808, MR18=0x2B44, DQSOSC=396, MR23=63, INC=167, DEC=111
4573 11:13:03.167672
4574 11:13:03.170364 ----->DramcWriteLeveling(PI) begin...
4575 11:13:03.170441 ==
4576 11:13:03.173981 Dram Type= 6, Freq= 0, CH_1, rank 1
4577 11:13:03.177294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4578 11:13:03.177364 ==
4579 11:13:03.180694 Write leveling (Byte 0): 30 => 30
4580 11:13:03.184039 Write leveling (Byte 1): 32 => 32
4581 11:13:03.187365 DramcWriteLeveling(PI) end<-----
4582 11:13:03.187432
4583 11:13:03.187493 ==
4584 11:13:03.190565 Dram Type= 6, Freq= 0, CH_1, rank 1
4585 11:13:03.193952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4586 11:13:03.197333 ==
4587 11:13:03.197417 [Gating] SW mode calibration
4588 11:13:03.207270 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4589 11:13:03.210415 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4590 11:13:03.213707 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4591 11:13:03.219836 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4592 11:13:03.223121 0 9 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
4593 11:13:03.226511 0 9 12 | B1->B0 | 3131 2c2c | 1 1 | (1 1) (1 0)
4594 11:13:03.233048 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4595 11:13:03.236533 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4596 11:13:03.239873 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4597 11:13:03.246459 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4598 11:13:03.249906 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4599 11:13:03.253205 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4600 11:13:03.259335 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4601 11:13:03.263010 0 10 12 | B1->B0 | 2727 3a3a | 0 0 | (0 0) (1 1)
4602 11:13:03.266215 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4603 11:13:03.273065 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4604 11:13:03.276093 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4605 11:13:03.279547 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4606 11:13:03.286112 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4607 11:13:03.289374 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4608 11:13:03.292539 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4609 11:13:03.299277 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4610 11:13:03.302626 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4611 11:13:03.305460 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4612 11:13:03.312165 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 11:13:03.315614 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 11:13:03.319011 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 11:13:03.325644 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 11:13:03.329182 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 11:13:03.332212 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 11:13:03.338266 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 11:13:03.341812 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 11:13:03.345146 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 11:13:03.351921 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 11:13:03.355218 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 11:13:03.358220 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 11:13:03.364758 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 11:13:03.368365 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4626 11:13:03.371368 Total UI for P1: 0, mck2ui 16
4627 11:13:03.374492 best dqsien dly found for B0: ( 0, 13, 10)
4628 11:13:03.377709 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4629 11:13:03.381430 Total UI for P1: 0, mck2ui 16
4630 11:13:03.384471 best dqsien dly found for B1: ( 0, 13, 12)
4631 11:13:03.387956 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4632 11:13:03.394398 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4633 11:13:03.394501
4634 11:13:03.397521 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4635 11:13:03.400984 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4636 11:13:03.404293 [Gating] SW calibration Done
4637 11:13:03.404367 ==
4638 11:13:03.407366 Dram Type= 6, Freq= 0, CH_1, rank 1
4639 11:13:03.410610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4640 11:13:03.410682 ==
4641 11:13:03.413879 RX Vref Scan: 0
4642 11:13:03.413949
4643 11:13:03.414010 RX Vref 0 -> 0, step: 1
4644 11:13:03.414106
4645 11:13:03.417262 RX Delay -230 -> 252, step: 16
4646 11:13:03.423938 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4647 11:13:03.427401 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4648 11:13:03.430832 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4649 11:13:03.434150 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4650 11:13:03.437332 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4651 11:13:03.443667 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4652 11:13:03.446866 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4653 11:13:03.450329 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4654 11:13:03.453686 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4655 11:13:03.460076 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4656 11:13:03.463536 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4657 11:13:03.466751 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4658 11:13:03.470017 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4659 11:13:03.476567 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4660 11:13:03.479929 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4661 11:13:03.483554 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4662 11:13:03.483628 ==
4663 11:13:03.486304 Dram Type= 6, Freq= 0, CH_1, rank 1
4664 11:13:03.490053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4665 11:13:03.492983 ==
4666 11:13:03.493059 DQS Delay:
4667 11:13:03.493123 DQS0 = 0, DQS1 = 0
4668 11:13:03.496213 DQM Delay:
4669 11:13:03.496287 DQM0 = 42, DQM1 = 38
4670 11:13:03.499380 DQ Delay:
4671 11:13:03.502872 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4672 11:13:03.502971 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4673 11:13:03.506203 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4674 11:13:03.512732 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4675 11:13:03.512808
4676 11:13:03.512875
4677 11:13:03.512934 ==
4678 11:13:03.516164 Dram Type= 6, Freq= 0, CH_1, rank 1
4679 11:13:03.519644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4680 11:13:03.519743 ==
4681 11:13:03.519836
4682 11:13:03.519950
4683 11:13:03.522595 TX Vref Scan disable
4684 11:13:03.522691 == TX Byte 0 ==
4685 11:13:03.529179 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4686 11:13:03.532677 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4687 11:13:03.532764 == TX Byte 1 ==
4688 11:13:03.539313 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4689 11:13:03.542616 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4690 11:13:03.542734 ==
4691 11:13:03.545539 Dram Type= 6, Freq= 0, CH_1, rank 1
4692 11:13:03.548952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4693 11:13:03.549029 ==
4694 11:13:03.549093
4695 11:13:03.552439
4696 11:13:03.552511 TX Vref Scan disable
4697 11:13:03.555717 == TX Byte 0 ==
4698 11:13:03.559050 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4699 11:13:03.565648 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4700 11:13:03.565745 == TX Byte 1 ==
4701 11:13:03.568974 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4702 11:13:03.575453 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4703 11:13:03.575557
4704 11:13:03.575647 [DATLAT]
4705 11:13:03.575735 Freq=600, CH1 RK1
4706 11:13:03.575824
4707 11:13:03.578952 DATLAT Default: 0x9
4708 11:13:03.579064 0, 0xFFFF, sum = 0
4709 11:13:03.581988 1, 0xFFFF, sum = 0
4710 11:13:03.585609 2, 0xFFFF, sum = 0
4711 11:13:03.585683 3, 0xFFFF, sum = 0
4712 11:13:03.588755 4, 0xFFFF, sum = 0
4713 11:13:03.588831 5, 0xFFFF, sum = 0
4714 11:13:03.591806 6, 0xFFFF, sum = 0
4715 11:13:03.591906 7, 0xFFFF, sum = 0
4716 11:13:03.595536 8, 0x0, sum = 1
4717 11:13:03.595610 9, 0x0, sum = 2
4718 11:13:03.598698 10, 0x0, sum = 3
4719 11:13:03.598815 11, 0x0, sum = 4
4720 11:13:03.598914 best_step = 9
4721 11:13:03.599014
4722 11:13:03.601813 ==
4723 11:13:03.605249 Dram Type= 6, Freq= 0, CH_1, rank 1
4724 11:13:03.608388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4725 11:13:03.608477 ==
4726 11:13:03.608542 RX Vref Scan: 0
4727 11:13:03.608600
4728 11:13:03.611936 RX Vref 0 -> 0, step: 1
4729 11:13:03.612040
4730 11:13:03.614705 RX Delay -179 -> 252, step: 8
4731 11:13:03.621572 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4732 11:13:03.624867 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4733 11:13:03.628291 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4734 11:13:03.631635 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4735 11:13:03.637794 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4736 11:13:03.641124 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4737 11:13:03.644361 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4738 11:13:03.647616 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4739 11:13:03.651010 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4740 11:13:03.657867 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4741 11:13:03.660708 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4742 11:13:03.664039 iDelay=205, Bit 11, Center 28 (-131 ~ 188) 320
4743 11:13:03.667587 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4744 11:13:03.674161 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4745 11:13:03.677555 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4746 11:13:03.680794 iDelay=205, Bit 15, Center 44 (-115 ~ 204) 320
4747 11:13:03.680870 ==
4748 11:13:03.683980 Dram Type= 6, Freq= 0, CH_1, rank 1
4749 11:13:03.690703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4750 11:13:03.690802 ==
4751 11:13:03.690890 DQS Delay:
4752 11:13:03.690971 DQS0 = 0, DQS1 = 0
4753 11:13:03.693752 DQM Delay:
4754 11:13:03.693837 DQM0 = 38, DQM1 = 35
4755 11:13:03.697554 DQ Delay:
4756 11:13:03.700672 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =36
4757 11:13:03.703871 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =32
4758 11:13:03.706937 DQ8 =20, DQ9 =24, DQ10 =40, DQ11 =28
4759 11:13:03.710502 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =44
4760 11:13:03.710605
4761 11:13:03.710706
4762 11:13:03.717008 [DQSOSCAuto] RK1, (LSB)MR18= 0x3559, (MSB)MR19= 0x808, tDQSOscB0 = 393 ps tDQSOscB1 = 399 ps
4763 11:13:03.720486 CH1 RK1: MR19=808, MR18=3559
4764 11:13:03.726646 CH1_RK1: MR19=0x808, MR18=0x3559, DQSOSC=393, MR23=63, INC=169, DEC=113
4765 11:13:03.730039 [RxdqsGatingPostProcess] freq 600
4766 11:13:03.733507 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4767 11:13:03.736763 Pre-setting of DQS Precalculation
4768 11:13:03.743861 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4769 11:13:03.749809 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4770 11:13:03.756566 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4771 11:13:03.756652
4772 11:13:03.756718
4773 11:13:03.759452 [Calibration Summary] 1200 Mbps
4774 11:13:03.762975 CH 0, Rank 0
4775 11:13:03.763048 SW Impedance : PASS
4776 11:13:03.766136 DUTY Scan : NO K
4777 11:13:03.769473 ZQ Calibration : PASS
4778 11:13:03.769545 Jitter Meter : NO K
4779 11:13:03.772808 CBT Training : PASS
4780 11:13:03.772898 Write leveling : PASS
4781 11:13:03.776055 RX DQS gating : PASS
4782 11:13:03.779571 RX DQ/DQS(RDDQC) : PASS
4783 11:13:03.779656 TX DQ/DQS : PASS
4784 11:13:03.782808 RX DATLAT : PASS
4785 11:13:03.786076 RX DQ/DQS(Engine): PASS
4786 11:13:03.786160 TX OE : NO K
4787 11:13:03.789195 All Pass.
4788 11:13:03.789280
4789 11:13:03.789347 CH 0, Rank 1
4790 11:13:03.792994 SW Impedance : PASS
4791 11:13:03.793090 DUTY Scan : NO K
4792 11:13:03.796053 ZQ Calibration : PASS
4793 11:13:03.799387 Jitter Meter : NO K
4794 11:13:03.799472 CBT Training : PASS
4795 11:13:03.803018 Write leveling : PASS
4796 11:13:03.806167 RX DQS gating : PASS
4797 11:13:03.806251 RX DQ/DQS(RDDQC) : PASS
4798 11:13:03.809477 TX DQ/DQS : PASS
4799 11:13:03.812747 RX DATLAT : PASS
4800 11:13:03.812831 RX DQ/DQS(Engine): PASS
4801 11:13:03.815781 TX OE : NO K
4802 11:13:03.815865 All Pass.
4803 11:13:03.815931
4804 11:13:03.819045 CH 1, Rank 0
4805 11:13:03.819129 SW Impedance : PASS
4806 11:13:03.822472 DUTY Scan : NO K
4807 11:13:03.825867 ZQ Calibration : PASS
4808 11:13:03.825952 Jitter Meter : NO K
4809 11:13:03.829292 CBT Training : PASS
4810 11:13:03.832073 Write leveling : PASS
4811 11:13:03.832159 RX DQS gating : PASS
4812 11:13:03.835524 RX DQ/DQS(RDDQC) : PASS
4813 11:13:03.839005 TX DQ/DQS : PASS
4814 11:13:03.839086 RX DATLAT : PASS
4815 11:13:03.842320 RX DQ/DQS(Engine): PASS
4816 11:13:03.842398 TX OE : NO K
4817 11:13:03.845069 All Pass.
4818 11:13:03.845149
4819 11:13:03.845213 CH 1, Rank 1
4820 11:13:03.848495 SW Impedance : PASS
4821 11:13:03.851707 DUTY Scan : NO K
4822 11:13:03.851787 ZQ Calibration : PASS
4823 11:13:03.854979 Jitter Meter : NO K
4824 11:13:03.855053 CBT Training : PASS
4825 11:13:03.858424 Write leveling : PASS
4826 11:13:03.861609 RX DQS gating : PASS
4827 11:13:03.861688 RX DQ/DQS(RDDQC) : PASS
4828 11:13:03.864992 TX DQ/DQS : PASS
4829 11:13:03.868698 RX DATLAT : PASS
4830 11:13:03.868770 RX DQ/DQS(Engine): PASS
4831 11:13:03.871799 TX OE : NO K
4832 11:13:03.871897 All Pass.
4833 11:13:03.871961
4834 11:13:03.875173 DramC Write-DBI off
4835 11:13:03.878566 PER_BANK_REFRESH: Hybrid Mode
4836 11:13:03.878641 TX_TRACKING: ON
4837 11:13:03.888197 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4838 11:13:03.891336 [FAST_K] Save calibration result to emmc
4839 11:13:03.894944 dramc_set_vcore_voltage set vcore to 662500
4840 11:13:03.898452 Read voltage for 933, 3
4841 11:13:03.898530 Vio18 = 0
4842 11:13:03.898593 Vcore = 662500
4843 11:13:03.901260 Vdram = 0
4844 11:13:03.901332 Vddq = 0
4845 11:13:03.901393 Vmddr = 0
4846 11:13:03.908168 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4847 11:13:03.911470 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4848 11:13:03.914550 MEM_TYPE=3, freq_sel=17
4849 11:13:03.917956 sv_algorithm_assistance_LP4_1600
4850 11:13:03.921144 ============ PULL DRAM RESETB DOWN ============
4851 11:13:03.927716 ========== PULL DRAM RESETB DOWN end =========
4852 11:13:03.931013 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4853 11:13:03.934612 ===================================
4854 11:13:03.937690 LPDDR4 DRAM CONFIGURATION
4855 11:13:03.941043 ===================================
4856 11:13:03.941138 EX_ROW_EN[0] = 0x0
4857 11:13:03.943876 EX_ROW_EN[1] = 0x0
4858 11:13:03.943950 LP4Y_EN = 0x0
4859 11:13:03.947200 WORK_FSP = 0x0
4860 11:13:03.950624 WL = 0x3
4861 11:13:03.950711 RL = 0x3
4862 11:13:03.953839 BL = 0x2
4863 11:13:03.953943 RPST = 0x0
4864 11:13:03.957176 RD_PRE = 0x0
4865 11:13:03.957290 WR_PRE = 0x1
4866 11:13:03.960569 WR_PST = 0x0
4867 11:13:03.960640 DBI_WR = 0x0
4868 11:13:03.964048 DBI_RD = 0x0
4869 11:13:03.964132 OTF = 0x1
4870 11:13:03.967454 ===================================
4871 11:13:03.970852 ===================================
4872 11:13:03.973633 ANA top config
4873 11:13:03.977036 ===================================
4874 11:13:03.977182 DLL_ASYNC_EN = 0
4875 11:13:03.980382 ALL_SLAVE_EN = 1
4876 11:13:03.983560 NEW_RANK_MODE = 1
4877 11:13:03.986820 DLL_IDLE_MODE = 1
4878 11:13:03.990298 LP45_APHY_COMB_EN = 1
4879 11:13:03.990370 TX_ODT_DIS = 1
4880 11:13:03.993682 NEW_8X_MODE = 1
4881 11:13:03.996988 ===================================
4882 11:13:04.000470 ===================================
4883 11:13:04.003069 data_rate = 1866
4884 11:13:04.006407 CKR = 1
4885 11:13:04.009829 DQ_P2S_RATIO = 8
4886 11:13:04.013216 ===================================
4887 11:13:04.016752 CA_P2S_RATIO = 8
4888 11:13:04.016848 DQ_CA_OPEN = 0
4889 11:13:04.019899 DQ_SEMI_OPEN = 0
4890 11:13:04.023333 CA_SEMI_OPEN = 0
4891 11:13:04.026456 CA_FULL_RATE = 0
4892 11:13:04.029568 DQ_CKDIV4_EN = 1
4893 11:13:04.032814 CA_CKDIV4_EN = 1
4894 11:13:04.032906 CA_PREDIV_EN = 0
4895 11:13:04.036264 PH8_DLY = 0
4896 11:13:04.039366 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4897 11:13:04.042846 DQ_AAMCK_DIV = 4
4898 11:13:04.046110 CA_AAMCK_DIV = 4
4899 11:13:04.049573 CA_ADMCK_DIV = 4
4900 11:13:04.049661 DQ_TRACK_CA_EN = 0
4901 11:13:04.053007 CA_PICK = 933
4902 11:13:04.056141 CA_MCKIO = 933
4903 11:13:04.059630 MCKIO_SEMI = 0
4904 11:13:04.062327 PLL_FREQ = 3732
4905 11:13:04.065819 DQ_UI_PI_RATIO = 32
4906 11:13:04.069142 CA_UI_PI_RATIO = 0
4907 11:13:04.072086 ===================================
4908 11:13:04.075478 ===================================
4909 11:13:04.075562 memory_type:LPDDR4
4910 11:13:04.078750 GP_NUM : 10
4911 11:13:04.082106 SRAM_EN : 1
4912 11:13:04.082190 MD32_EN : 0
4913 11:13:04.085449 ===================================
4914 11:13:04.088869 [ANA_INIT] >>>>>>>>>>>>>>
4915 11:13:04.092285 <<<<<< [CONFIGURE PHASE]: ANA_TX
4916 11:13:04.094998 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4917 11:13:04.098428 ===================================
4918 11:13:04.101853 data_rate = 1866,PCW = 0X8f00
4919 11:13:04.105148 ===================================
4920 11:13:04.108495 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4921 11:13:04.114940 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4922 11:13:04.118041 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4923 11:13:04.124635 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4924 11:13:04.127867 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4925 11:13:04.131608 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4926 11:13:04.131702 [ANA_INIT] flow start
4927 11:13:04.134526 [ANA_INIT] PLL >>>>>>>>
4928 11:13:04.138063 [ANA_INIT] PLL <<<<<<<<
4929 11:13:04.138147 [ANA_INIT] MIDPI >>>>>>>>
4930 11:13:04.141256 [ANA_INIT] MIDPI <<<<<<<<
4931 11:13:04.144702 [ANA_INIT] DLL >>>>>>>>
4932 11:13:04.144786 [ANA_INIT] flow end
4933 11:13:04.151431 ============ LP4 DIFF to SE enter ============
4934 11:13:04.154312 ============ LP4 DIFF to SE exit ============
4935 11:13:04.157648 [ANA_INIT] <<<<<<<<<<<<<
4936 11:13:04.160953 [Flow] Enable top DCM control >>>>>
4937 11:13:04.163963 [Flow] Enable top DCM control <<<<<
4938 11:13:04.167408 Enable DLL master slave shuffle
4939 11:13:04.170731 ==============================================================
4940 11:13:04.174121 Gating Mode config
4941 11:13:04.177439 ==============================================================
4942 11:13:04.180854 Config description:
4943 11:13:04.190374 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4944 11:13:04.196878 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4945 11:13:04.200245 SELPH_MODE 0: By rank 1: By Phase
4946 11:13:04.206979 ==============================================================
4947 11:13:04.210410 GAT_TRACK_EN = 1
4948 11:13:04.213780 RX_GATING_MODE = 2
4949 11:13:04.216455 RX_GATING_TRACK_MODE = 2
4950 11:13:04.220080 SELPH_MODE = 1
4951 11:13:04.223209 PICG_EARLY_EN = 1
4952 11:13:04.226459 VALID_LAT_VALUE = 1
4953 11:13:04.230313 ==============================================================
4954 11:13:04.233065 Enter into Gating configuration >>>>
4955 11:13:04.236436 Exit from Gating configuration <<<<
4956 11:13:04.239614 Enter into DVFS_PRE_config >>>>>
4957 11:13:04.252895 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4958 11:13:04.255984 Exit from DVFS_PRE_config <<<<<
4959 11:13:04.259475 Enter into PICG configuration >>>>
4960 11:13:04.259576 Exit from PICG configuration <<<<
4961 11:13:04.262789 [RX_INPUT] configuration >>>>>
4962 11:13:04.265984 [RX_INPUT] configuration <<<<<
4963 11:13:04.272579 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4964 11:13:04.275953 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4965 11:13:04.282662 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4966 11:13:04.288903 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4967 11:13:04.295499 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4968 11:13:04.302457 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4969 11:13:04.305806 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4970 11:13:04.308643 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4971 11:13:04.315372 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4972 11:13:04.318671 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4973 11:13:04.322063 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4974 11:13:04.325451 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4975 11:13:04.328665 ===================================
4976 11:13:04.331910 LPDDR4 DRAM CONFIGURATION
4977 11:13:04.334976 ===================================
4978 11:13:04.338548 EX_ROW_EN[0] = 0x0
4979 11:13:04.338675 EX_ROW_EN[1] = 0x0
4980 11:13:04.341567 LP4Y_EN = 0x0
4981 11:13:04.341678 WORK_FSP = 0x0
4982 11:13:04.345230 WL = 0x3
4983 11:13:04.348433 RL = 0x3
4984 11:13:04.348518 BL = 0x2
4985 11:13:04.351519 RPST = 0x0
4986 11:13:04.351630 RD_PRE = 0x0
4987 11:13:04.354876 WR_PRE = 0x1
4988 11:13:04.354988 WR_PST = 0x0
4989 11:13:04.358138 DBI_WR = 0x0
4990 11:13:04.358231 DBI_RD = 0x0
4991 11:13:04.361113 OTF = 0x1
4992 11:13:04.364890 ===================================
4993 11:13:04.367667 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4994 11:13:04.370937 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4995 11:13:04.377738 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4996 11:13:04.381100 ===================================
4997 11:13:04.381207 LPDDR4 DRAM CONFIGURATION
4998 11:13:04.384452 ===================================
4999 11:13:04.387495 EX_ROW_EN[0] = 0x10
5000 11:13:04.390749 EX_ROW_EN[1] = 0x0
5001 11:13:04.390864 LP4Y_EN = 0x0
5002 11:13:04.394180 WORK_FSP = 0x0
5003 11:13:04.394267 WL = 0x3
5004 11:13:04.397422 RL = 0x3
5005 11:13:04.397508 BL = 0x2
5006 11:13:04.400628 RPST = 0x0
5007 11:13:04.400741 RD_PRE = 0x0
5008 11:13:04.404040 WR_PRE = 0x1
5009 11:13:04.404156 WR_PST = 0x0
5010 11:13:04.407493 DBI_WR = 0x0
5011 11:13:04.407579 DBI_RD = 0x0
5012 11:13:04.410725 OTF = 0x1
5013 11:13:04.414284 ===================================
5014 11:13:04.420427 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5015 11:13:04.423794 nWR fixed to 30
5016 11:13:04.423884 [ModeRegInit_LP4] CH0 RK0
5017 11:13:04.427158 [ModeRegInit_LP4] CH0 RK1
5018 11:13:04.430653 [ModeRegInit_LP4] CH1 RK0
5019 11:13:04.433891 [ModeRegInit_LP4] CH1 RK1
5020 11:13:04.433978 match AC timing 9
5021 11:13:04.440401 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5022 11:13:04.443675 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5023 11:13:04.446667 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5024 11:13:04.453696 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5025 11:13:04.456723 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5026 11:13:04.456835 ==
5027 11:13:04.459890 Dram Type= 6, Freq= 0, CH_0, rank 0
5028 11:13:04.463098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5029 11:13:04.463188 ==
5030 11:13:04.469900 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5031 11:13:04.476464 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5032 11:13:04.479838 [CA 0] Center 37 (7~68) winsize 62
5033 11:13:04.483404 [CA 1] Center 37 (7~68) winsize 62
5034 11:13:04.486550 [CA 2] Center 34 (4~65) winsize 62
5035 11:13:04.489454 [CA 3] Center 34 (4~65) winsize 62
5036 11:13:04.492765 [CA 4] Center 32 (2~63) winsize 62
5037 11:13:04.496021 [CA 5] Center 32 (2~63) winsize 62
5038 11:13:04.496117
5039 11:13:04.499455 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5040 11:13:04.499541
5041 11:13:04.502929 [CATrainingPosCal] consider 1 rank data
5042 11:13:04.505928 u2DelayCellTimex100 = 270/100 ps
5043 11:13:04.509241 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5044 11:13:04.512562 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5045 11:13:04.515992 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5046 11:13:04.519240 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5047 11:13:04.526146 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5048 11:13:04.528900 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5049 11:13:04.528988
5050 11:13:04.532207 CA PerBit enable=1, Macro0, CA PI delay=32
5051 11:13:04.532294
5052 11:13:04.535548 [CBTSetCACLKResult] CA Dly = 32
5053 11:13:04.535634 CS Dly: 5 (0~36)
5054 11:13:04.535719 ==
5055 11:13:04.539275 Dram Type= 6, Freq= 0, CH_0, rank 1
5056 11:13:04.545479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5057 11:13:04.545566 ==
5058 11:13:04.549054 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5059 11:13:04.555547 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5060 11:13:04.558706 [CA 0] Center 37 (7~68) winsize 62
5061 11:13:04.562111 [CA 1] Center 37 (7~68) winsize 62
5062 11:13:04.565212 [CA 2] Center 35 (5~65) winsize 61
5063 11:13:04.568985 [CA 3] Center 34 (4~65) winsize 62
5064 11:13:04.571896 [CA 4] Center 33 (3~64) winsize 62
5065 11:13:04.575085 [CA 5] Center 32 (2~63) winsize 62
5066 11:13:04.575184
5067 11:13:04.578329 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5068 11:13:04.578413
5069 11:13:04.581380 [CATrainingPosCal] consider 2 rank data
5070 11:13:04.584793 u2DelayCellTimex100 = 270/100 ps
5071 11:13:04.588163 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5072 11:13:04.595063 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5073 11:13:04.598447 CA2 delay=35 (5~65),Diff = 3 PI (18 cell)
5074 11:13:04.601296 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5075 11:13:04.604650 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5076 11:13:04.607762 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5077 11:13:04.607876
5078 11:13:04.611559 CA PerBit enable=1, Macro0, CA PI delay=32
5079 11:13:04.611645
5080 11:13:04.614432 [CBTSetCACLKResult] CA Dly = 32
5081 11:13:04.617756 CS Dly: 6 (0~39)
5082 11:13:04.617838
5083 11:13:04.621247 ----->DramcWriteLeveling(PI) begin...
5084 11:13:04.621403 ==
5085 11:13:04.624608 Dram Type= 6, Freq= 0, CH_0, rank 0
5086 11:13:04.627483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5087 11:13:04.627593 ==
5088 11:13:04.630940 Write leveling (Byte 0): 34 => 34
5089 11:13:04.634278 Write leveling (Byte 1): 26 => 26
5090 11:13:04.637537 DramcWriteLeveling(PI) end<-----
5091 11:13:04.637622
5092 11:13:04.637685 ==
5093 11:13:04.640924 Dram Type= 6, Freq= 0, CH_0, rank 0
5094 11:13:04.644233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5095 11:13:04.644334 ==
5096 11:13:04.647047 [Gating] SW mode calibration
5097 11:13:04.654174 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5098 11:13:04.660764 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5099 11:13:04.663747 0 14 0 | B1->B0 | 2525 3434 | 1 1 | (1 1) (1 1)
5100 11:13:04.670230 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5101 11:13:04.673906 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5102 11:13:04.676976 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5103 11:13:04.683696 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5104 11:13:04.687325 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5105 11:13:04.689979 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5106 11:13:04.696815 0 14 28 | B1->B0 | 3434 2828 | 0 1 | (0 0) (1 0)
5107 11:13:04.700141 0 15 0 | B1->B0 | 3131 2424 | 0 0 | (0 0) (0 0)
5108 11:13:04.703628 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5109 11:13:04.709896 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5110 11:13:04.713131 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5111 11:13:04.716980 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5112 11:13:04.719768 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5113 11:13:04.726476 0 15 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5114 11:13:04.729940 0 15 28 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
5115 11:13:04.733332 1 0 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5116 11:13:04.739578 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5117 11:13:04.742931 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5118 11:13:04.749366 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5119 11:13:04.752987 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5120 11:13:04.756131 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5121 11:13:04.762637 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5122 11:13:04.766295 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5123 11:13:04.769399 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5124 11:13:04.775755 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5125 11:13:04.779047 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5126 11:13:04.782958 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 11:13:04.788984 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 11:13:04.792402 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 11:13:04.795849 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 11:13:04.802055 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 11:13:04.805408 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 11:13:04.808750 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 11:13:04.815543 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 11:13:04.818804 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 11:13:04.822257 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 11:13:04.828826 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 11:13:04.832140 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5138 11:13:04.835015 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5139 11:13:04.841806 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5140 11:13:04.845199 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5141 11:13:04.848404 Total UI for P1: 0, mck2ui 16
5142 11:13:04.851645 best dqsien dly found for B0: ( 1, 2, 28)
5143 11:13:04.855045 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5144 11:13:04.857978 Total UI for P1: 0, mck2ui 16
5145 11:13:04.861322 best dqsien dly found for B1: ( 1, 3, 4)
5146 11:13:04.864660 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5147 11:13:04.868070 best DQS1 dly(MCK, UI, PI) = (1, 3, 4)
5148 11:13:04.868168
5149 11:13:04.871304 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5150 11:13:04.877783 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 4)
5151 11:13:04.877878 [Gating] SW calibration Done
5152 11:13:04.877972 ==
5153 11:13:04.881036 Dram Type= 6, Freq= 0, CH_0, rank 0
5154 11:13:04.887816 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5155 11:13:04.887937 ==
5156 11:13:04.888052 RX Vref Scan: 0
5157 11:13:04.888147
5158 11:13:04.891061 RX Vref 0 -> 0, step: 1
5159 11:13:04.891137
5160 11:13:04.894729 RX Delay -80 -> 252, step: 8
5161 11:13:04.897734 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5162 11:13:04.900994 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5163 11:13:04.904341 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5164 11:13:04.907813 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5165 11:13:04.914004 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5166 11:13:04.917547 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5167 11:13:04.920833 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5168 11:13:04.924205 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5169 11:13:04.927477 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5170 11:13:04.934174 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5171 11:13:04.936948 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5172 11:13:04.940406 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5173 11:13:04.943844 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5174 11:13:04.946983 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5175 11:13:04.953591 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5176 11:13:04.956773 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5177 11:13:04.956869 ==
5178 11:13:04.960300 Dram Type= 6, Freq= 0, CH_0, rank 0
5179 11:13:04.963723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5180 11:13:04.963837 ==
5181 11:13:04.963932 DQS Delay:
5182 11:13:04.967086 DQS0 = 0, DQS1 = 0
5183 11:13:04.967184 DQM Delay:
5184 11:13:04.970626 DQM0 = 99, DQM1 = 88
5185 11:13:04.970743 DQ Delay:
5186 11:13:04.973704 DQ0 =103, DQ1 =99, DQ2 =95, DQ3 =95
5187 11:13:04.976638 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =107
5188 11:13:04.980382 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5189 11:13:04.983268 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5190 11:13:04.983388
5191 11:13:04.983484
5192 11:13:04.983575 ==
5193 11:13:04.986627 Dram Type= 6, Freq= 0, CH_0, rank 0
5194 11:13:04.993224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5195 11:13:04.993337 ==
5196 11:13:04.993405
5197 11:13:04.993467
5198 11:13:04.993527 TX Vref Scan disable
5199 11:13:04.996911 == TX Byte 0 ==
5200 11:13:05.000071 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5201 11:13:05.006377 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5202 11:13:05.006514 == TX Byte 1 ==
5203 11:13:05.009778 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5204 11:13:05.016400 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5205 11:13:05.016526 ==
5206 11:13:05.019674 Dram Type= 6, Freq= 0, CH_0, rank 0
5207 11:13:05.023051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5208 11:13:05.023166 ==
5209 11:13:05.023265
5210 11:13:05.023356
5211 11:13:05.026445 TX Vref Scan disable
5212 11:13:05.029561 == TX Byte 0 ==
5213 11:13:05.033039 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5214 11:13:05.036461 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5215 11:13:05.039928 == TX Byte 1 ==
5216 11:13:05.043148 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5217 11:13:05.046024 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5218 11:13:05.046137
5219 11:13:05.046232 [DATLAT]
5220 11:13:05.049356 Freq=933, CH0 RK0
5221 11:13:05.049469
5222 11:13:05.052669 DATLAT Default: 0xd
5223 11:13:05.052770 0, 0xFFFF, sum = 0
5224 11:13:05.055880 1, 0xFFFF, sum = 0
5225 11:13:05.055982 2, 0xFFFF, sum = 0
5226 11:13:05.059611 3, 0xFFFF, sum = 0
5227 11:13:05.059721 4, 0xFFFF, sum = 0
5228 11:13:05.062917 5, 0xFFFF, sum = 0
5229 11:13:05.063023 6, 0xFFFF, sum = 0
5230 11:13:05.065821 7, 0xFFFF, sum = 0
5231 11:13:05.065925 8, 0xFFFF, sum = 0
5232 11:13:05.069272 9, 0xFFFF, sum = 0
5233 11:13:05.069383 10, 0x0, sum = 1
5234 11:13:05.072190 11, 0x0, sum = 2
5235 11:13:05.072297 12, 0x0, sum = 3
5236 11:13:05.075488 13, 0x0, sum = 4
5237 11:13:05.075592 best_step = 11
5238 11:13:05.075685
5239 11:13:05.075784 ==
5240 11:13:05.079327 Dram Type= 6, Freq= 0, CH_0, rank 0
5241 11:13:05.082249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5242 11:13:05.085400 ==
5243 11:13:05.085521 RX Vref Scan: 1
5244 11:13:05.085620
5245 11:13:05.088977 RX Vref 0 -> 0, step: 1
5246 11:13:05.089079
5247 11:13:05.092079 RX Delay -61 -> 252, step: 4
5248 11:13:05.092182
5249 11:13:05.095749 Set Vref, RX VrefLevel [Byte0]: 51
5250 11:13:05.099055 [Byte1]: 47
5251 11:13:05.099171
5252 11:13:05.102163 Final RX Vref Byte 0 = 51 to rank0
5253 11:13:05.105685 Final RX Vref Byte 1 = 47 to rank0
5254 11:13:05.108931 Final RX Vref Byte 0 = 51 to rank1
5255 11:13:05.112317 Final RX Vref Byte 1 = 47 to rank1==
5256 11:13:05.115215 Dram Type= 6, Freq= 0, CH_0, rank 0
5257 11:13:05.118491 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5258 11:13:05.118579 ==
5259 11:13:05.121783 DQS Delay:
5260 11:13:05.121895 DQS0 = 0, DQS1 = 0
5261 11:13:05.121990 DQM Delay:
5262 11:13:05.125345 DQM0 = 99, DQM1 = 86
5263 11:13:05.125450 DQ Delay:
5264 11:13:05.128721 DQ0 =100, DQ1 =100, DQ2 =94, DQ3 =96
5265 11:13:05.131886 DQ4 =100, DQ5 =90, DQ6 =108, DQ7 =106
5266 11:13:05.135248 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =80
5267 11:13:05.138622 DQ12 =94, DQ13 =90, DQ14 =94, DQ15 =96
5268 11:13:05.138710
5269 11:13:05.138778
5270 11:13:05.148166 [DQSOSCAuto] RK0, (LSB)MR18= 0x1d17, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 412 ps
5271 11:13:05.151581 CH0 RK0: MR19=505, MR18=1D17
5272 11:13:05.158314 CH0_RK0: MR19=0x505, MR18=0x1D17, DQSOSC=412, MR23=63, INC=63, DEC=42
5273 11:13:05.158405
5274 11:13:05.161637 ----->DramcWriteLeveling(PI) begin...
5275 11:13:05.161723 ==
5276 11:13:05.164886 Dram Type= 6, Freq= 0, CH_0, rank 1
5277 11:13:05.168054 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5278 11:13:05.168140 ==
5279 11:13:05.171600 Write leveling (Byte 0): 33 => 33
5280 11:13:05.174357 Write leveling (Byte 1): 26 => 26
5281 11:13:05.177771 DramcWriteLeveling(PI) end<-----
5282 11:13:05.177856
5283 11:13:05.177923 ==
5284 11:13:05.181082 Dram Type= 6, Freq= 0, CH_0, rank 1
5285 11:13:05.184515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5286 11:13:05.184601 ==
5287 11:13:05.187732 [Gating] SW mode calibration
5288 11:13:05.194381 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5289 11:13:05.200998 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5290 11:13:05.204034 0 14 0 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
5291 11:13:05.210846 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5292 11:13:05.213920 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5293 11:13:05.217572 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5294 11:13:05.223882 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5295 11:13:05.226956 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5296 11:13:05.230250 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (1 0)
5297 11:13:05.236798 0 14 28 | B1->B0 | 3434 2e2e | 0 0 | (0 1) (0 0)
5298 11:13:05.240268 0 15 0 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
5299 11:13:05.243767 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5300 11:13:05.250459 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5301 11:13:05.253804 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5302 11:13:05.256572 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5303 11:13:05.263341 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5304 11:13:05.266620 0 15 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5305 11:13:05.269891 0 15 28 | B1->B0 | 2c2c 3e3e | 0 1 | (1 1) (0 0)
5306 11:13:05.276570 1 0 0 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
5307 11:13:05.279477 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5308 11:13:05.283383 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5309 11:13:05.289573 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5310 11:13:05.292863 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5311 11:13:05.296162 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5312 11:13:05.303057 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5313 11:13:05.306202 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5314 11:13:05.309361 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5315 11:13:05.316459 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5316 11:13:05.319356 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 11:13:05.322460 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 11:13:05.329008 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 11:13:05.332600 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 11:13:05.335555 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 11:13:05.342301 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 11:13:05.345686 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 11:13:05.349193 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 11:13:05.355349 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 11:13:05.358653 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 11:13:05.362117 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 11:13:05.368803 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 11:13:05.371931 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 11:13:05.375223 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5330 11:13:05.378639 Total UI for P1: 0, mck2ui 16
5331 11:13:05.382110 best dqsien dly found for B0: ( 1, 2, 26)
5332 11:13:05.388316 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5333 11:13:05.391875 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5334 11:13:05.395129 Total UI for P1: 0, mck2ui 16
5335 11:13:05.398376 best dqsien dly found for B1: ( 1, 2, 30)
5336 11:13:05.401732 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5337 11:13:05.404659 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5338 11:13:05.404741
5339 11:13:05.408475 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5340 11:13:05.411395 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5341 11:13:05.414888 [Gating] SW calibration Done
5342 11:13:05.414969 ==
5343 11:13:05.418468 Dram Type= 6, Freq= 0, CH_0, rank 1
5344 11:13:05.424325 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5345 11:13:05.424424 ==
5346 11:13:05.424489 RX Vref Scan: 0
5347 11:13:05.424549
5348 11:13:05.428023 RX Vref 0 -> 0, step: 1
5349 11:13:05.428138
5350 11:13:05.431065 RX Delay -80 -> 252, step: 8
5351 11:13:05.434546 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5352 11:13:05.437564 iDelay=200, Bit 1, Center 99 (0 ~ 199) 200
5353 11:13:05.441053 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5354 11:13:05.444205 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5355 11:13:05.447400 iDelay=200, Bit 4, Center 99 (0 ~ 199) 200
5356 11:13:05.453744 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5357 11:13:05.457471 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5358 11:13:05.460380 iDelay=200, Bit 7, Center 107 (16 ~ 199) 184
5359 11:13:05.463685 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5360 11:13:05.466978 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5361 11:13:05.473759 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5362 11:13:05.477040 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5363 11:13:05.480665 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5364 11:13:05.483744 iDelay=200, Bit 13, Center 91 (0 ~ 183) 184
5365 11:13:05.487187 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5366 11:13:05.493384 iDelay=200, Bit 15, Center 91 (0 ~ 183) 184
5367 11:13:05.493464 ==
5368 11:13:05.496921 Dram Type= 6, Freq= 0, CH_0, rank 1
5369 11:13:05.500100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5370 11:13:05.500192 ==
5371 11:13:05.500258 DQS Delay:
5372 11:13:05.503268 DQS0 = 0, DQS1 = 0
5373 11:13:05.503344 DQM Delay:
5374 11:13:05.506578 DQM0 = 97, DQM1 = 88
5375 11:13:05.506650 DQ Delay:
5376 11:13:05.509932 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =95
5377 11:13:05.513324 DQ4 =99, DQ5 =87, DQ6 =103, DQ7 =107
5378 11:13:05.516535 DQ8 =83, DQ9 =75, DQ10 =91, DQ11 =83
5379 11:13:05.519772 DQ12 =95, DQ13 =91, DQ14 =99, DQ15 =91
5380 11:13:05.519886
5381 11:13:05.519985
5382 11:13:05.520087 ==
5383 11:13:05.522954 Dram Type= 6, Freq= 0, CH_0, rank 1
5384 11:13:05.526148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5385 11:13:05.529661 ==
5386 11:13:05.529766
5387 11:13:05.529861
5388 11:13:05.529949 TX Vref Scan disable
5389 11:13:05.532740 == TX Byte 0 ==
5390 11:13:05.536520 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5391 11:13:05.539605 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5392 11:13:05.542652 == TX Byte 1 ==
5393 11:13:05.546080 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5394 11:13:05.549724 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5395 11:13:05.552832 ==
5396 11:13:05.555808 Dram Type= 6, Freq= 0, CH_0, rank 1
5397 11:13:05.559154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5398 11:13:05.559242 ==
5399 11:13:05.559314
5400 11:13:05.559376
5401 11:13:05.562550 TX Vref Scan disable
5402 11:13:05.562649 == TX Byte 0 ==
5403 11:13:05.569219 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5404 11:13:05.572668 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5405 11:13:05.572744 == TX Byte 1 ==
5406 11:13:05.578771 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5407 11:13:05.582042 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5408 11:13:05.582125
5409 11:13:05.582191 [DATLAT]
5410 11:13:05.585391 Freq=933, CH0 RK1
5411 11:13:05.585475
5412 11:13:05.585540 DATLAT Default: 0xb
5413 11:13:05.588766 0, 0xFFFF, sum = 0
5414 11:13:05.588855 1, 0xFFFF, sum = 0
5415 11:13:05.592144 2, 0xFFFF, sum = 0
5416 11:13:05.595729 3, 0xFFFF, sum = 0
5417 11:13:05.595841 4, 0xFFFF, sum = 0
5418 11:13:05.598905 5, 0xFFFF, sum = 0
5419 11:13:05.598990 6, 0xFFFF, sum = 0
5420 11:13:05.602295 7, 0xFFFF, sum = 0
5421 11:13:05.602381 8, 0xFFFF, sum = 0
5422 11:13:05.605493 9, 0xFFFF, sum = 0
5423 11:13:05.605578 10, 0x0, sum = 1
5424 11:13:05.608353 11, 0x0, sum = 2
5425 11:13:05.608449 12, 0x0, sum = 3
5426 11:13:05.611663 13, 0x0, sum = 4
5427 11:13:05.611746 best_step = 11
5428 11:13:05.611820
5429 11:13:05.611914 ==
5430 11:13:05.615110 Dram Type= 6, Freq= 0, CH_0, rank 1
5431 11:13:05.618626 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5432 11:13:05.618709 ==
5433 11:13:05.621775 RX Vref Scan: 0
5434 11:13:05.621857
5435 11:13:05.624969 RX Vref 0 -> 0, step: 1
5436 11:13:05.625052
5437 11:13:05.625117 RX Delay -61 -> 252, step: 4
5438 11:13:05.633389 iDelay=195, Bit 0, Center 94 (7 ~ 182) 176
5439 11:13:05.636419 iDelay=195, Bit 1, Center 100 (11 ~ 190) 180
5440 11:13:05.639564 iDelay=195, Bit 2, Center 92 (3 ~ 182) 180
5441 11:13:05.642989 iDelay=195, Bit 3, Center 96 (7 ~ 186) 180
5442 11:13:05.646122 iDelay=195, Bit 4, Center 102 (11 ~ 194) 184
5443 11:13:05.652645 iDelay=195, Bit 5, Center 88 (-1 ~ 178) 180
5444 11:13:05.655795 iDelay=195, Bit 6, Center 106 (19 ~ 194) 176
5445 11:13:05.659315 iDelay=195, Bit 7, Center 104 (15 ~ 194) 180
5446 11:13:05.662391 iDelay=195, Bit 8, Center 76 (-13 ~ 166) 180
5447 11:13:05.665586 iDelay=195, Bit 9, Center 76 (-13 ~ 166) 180
5448 11:13:05.672673 iDelay=195, Bit 10, Center 88 (-1 ~ 178) 180
5449 11:13:05.675995 iDelay=195, Bit 11, Center 82 (-5 ~ 170) 176
5450 11:13:05.678923 iDelay=195, Bit 12, Center 90 (-1 ~ 182) 184
5451 11:13:05.682101 iDelay=195, Bit 13, Center 90 (3 ~ 178) 176
5452 11:13:05.685480 iDelay=195, Bit 14, Center 98 (11 ~ 186) 176
5453 11:13:05.692115 iDelay=195, Bit 15, Center 94 (7 ~ 182) 176
5454 11:13:05.692220 ==
5455 11:13:05.695418 Dram Type= 6, Freq= 0, CH_0, rank 1
5456 11:13:05.698764 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5457 11:13:05.698878 ==
5458 11:13:05.698976 DQS Delay:
5459 11:13:05.702141 DQS0 = 0, DQS1 = 0
5460 11:13:05.702243 DQM Delay:
5461 11:13:05.705045 DQM0 = 97, DQM1 = 86
5462 11:13:05.705146 DQ Delay:
5463 11:13:05.708374 DQ0 =94, DQ1 =100, DQ2 =92, DQ3 =96
5464 11:13:05.712105 DQ4 =102, DQ5 =88, DQ6 =106, DQ7 =104
5465 11:13:05.715487 DQ8 =76, DQ9 =76, DQ10 =88, DQ11 =82
5466 11:13:05.718294 DQ12 =90, DQ13 =90, DQ14 =98, DQ15 =94
5467 11:13:05.718399
5468 11:13:05.718491
5469 11:13:05.728280 [DQSOSCAuto] RK1, (LSB)MR18= 0x1310, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 415 ps
5470 11:13:05.728411 CH0 RK1: MR19=505, MR18=1310
5471 11:13:05.734814 CH0_RK1: MR19=0x505, MR18=0x1310, DQSOSC=415, MR23=63, INC=62, DEC=41
5472 11:13:05.738135 [RxdqsGatingPostProcess] freq 933
5473 11:13:05.744814 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5474 11:13:05.748119 best DQS0 dly(2T, 0.5T) = (0, 10)
5475 11:13:05.751718 best DQS1 dly(2T, 0.5T) = (0, 11)
5476 11:13:05.754647 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5477 11:13:05.758128 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5478 11:13:05.761292 best DQS0 dly(2T, 0.5T) = (0, 10)
5479 11:13:05.761394 best DQS1 dly(2T, 0.5T) = (0, 10)
5480 11:13:05.764502 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5481 11:13:05.767985 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5482 11:13:05.771036 Pre-setting of DQS Precalculation
5483 11:13:05.777627 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5484 11:13:05.777731 ==
5485 11:13:05.781032 Dram Type= 6, Freq= 0, CH_1, rank 0
5486 11:13:05.784375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5487 11:13:05.784449 ==
5488 11:13:05.790956 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5489 11:13:05.797764 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5490 11:13:05.801123 [CA 0] Center 36 (6~67) winsize 62
5491 11:13:05.803976 [CA 1] Center 36 (6~67) winsize 62
5492 11:13:05.807386 [CA 2] Center 34 (4~65) winsize 62
5493 11:13:05.810712 [CA 3] Center 33 (3~64) winsize 62
5494 11:13:05.813925 [CA 4] Center 34 (3~65) winsize 63
5495 11:13:05.817168 [CA 5] Center 33 (3~64) winsize 62
5496 11:13:05.817280
5497 11:13:05.820576 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5498 11:13:05.820664
5499 11:13:05.823886 [CATrainingPosCal] consider 1 rank data
5500 11:13:05.827375 u2DelayCellTimex100 = 270/100 ps
5501 11:13:05.830746 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5502 11:13:05.833981 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5503 11:13:05.837278 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5504 11:13:05.840641 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5505 11:13:05.843743 CA4 delay=34 (3~65),Diff = 1 PI (6 cell)
5506 11:13:05.850516 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5507 11:13:05.850624
5508 11:13:05.853464 CA PerBit enable=1, Macro0, CA PI delay=33
5509 11:13:05.853567
5510 11:13:05.856684 [CBTSetCACLKResult] CA Dly = 33
5511 11:13:05.856768 CS Dly: 5 (0~36)
5512 11:13:05.856832 ==
5513 11:13:05.859981 Dram Type= 6, Freq= 0, CH_1, rank 1
5514 11:13:05.863672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5515 11:13:05.866835 ==
5516 11:13:05.870238 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5517 11:13:05.876294 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5518 11:13:05.879589 [CA 0] Center 36 (6~67) winsize 62
5519 11:13:05.883135 [CA 1] Center 37 (6~68) winsize 63
5520 11:13:05.886653 [CA 2] Center 34 (4~65) winsize 62
5521 11:13:05.889337 [CA 3] Center 33 (3~64) winsize 62
5522 11:13:05.892600 [CA 4] Center 33 (3~64) winsize 62
5523 11:13:05.896573 [CA 5] Center 33 (3~64) winsize 62
5524 11:13:05.896657
5525 11:13:05.899441 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5526 11:13:05.899524
5527 11:13:05.902701 [CATrainingPosCal] consider 2 rank data
5528 11:13:05.905981 u2DelayCellTimex100 = 270/100 ps
5529 11:13:05.909414 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5530 11:13:05.912627 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5531 11:13:05.919043 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5532 11:13:05.922494 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5533 11:13:05.925890 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5534 11:13:05.929408 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5535 11:13:05.929499
5536 11:13:05.932700 CA PerBit enable=1, Macro0, CA PI delay=33
5537 11:13:05.932786
5538 11:13:05.935868 [CBTSetCACLKResult] CA Dly = 33
5539 11:13:05.935977 CS Dly: 6 (0~38)
5540 11:13:05.939192
5541 11:13:05.941969 ----->DramcWriteLeveling(PI) begin...
5542 11:13:05.942074 ==
5543 11:13:05.945366 Dram Type= 6, Freq= 0, CH_1, rank 0
5544 11:13:05.948622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5545 11:13:05.948719 ==
5546 11:13:05.952558 Write leveling (Byte 0): 27 => 27
5547 11:13:05.955349 Write leveling (Byte 1): 27 => 27
5548 11:13:05.958644 DramcWriteLeveling(PI) end<-----
5549 11:13:05.958728
5550 11:13:05.958795 ==
5551 11:13:05.961943 Dram Type= 6, Freq= 0, CH_1, rank 0
5552 11:13:05.965803 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5553 11:13:05.965896 ==
5554 11:13:05.968948 [Gating] SW mode calibration
5555 11:13:05.974988 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5556 11:13:05.981628 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5557 11:13:05.985270 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5558 11:13:05.988343 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5559 11:13:05.994848 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5560 11:13:05.998149 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5561 11:13:06.001427 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5562 11:13:06.008042 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5563 11:13:06.011438 0 14 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
5564 11:13:06.014955 0 14 28 | B1->B0 | 2e2e 2626 | 0 0 | (0 1) (1 0)
5565 11:13:06.021089 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5566 11:13:06.024481 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5567 11:13:06.027881 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5568 11:13:06.034137 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5569 11:13:06.037433 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5570 11:13:06.041088 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5571 11:13:06.047377 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5572 11:13:06.050580 0 15 28 | B1->B0 | 3535 3f3f | 0 0 | (0 0) (0 0)
5573 11:13:06.053952 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5574 11:13:06.060512 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5575 11:13:06.063887 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5576 11:13:06.067323 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5577 11:13:06.073818 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5578 11:13:06.076966 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5579 11:13:06.080496 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5580 11:13:06.086824 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5581 11:13:06.090324 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5582 11:13:06.093487 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 11:13:06.100366 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 11:13:06.103163 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 11:13:06.106402 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 11:13:06.113079 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 11:13:06.116330 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 11:13:06.119699 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 11:13:06.126420 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 11:13:06.129652 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 11:13:06.132913 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 11:13:06.139625 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 11:13:06.142907 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 11:13:06.146170 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 11:13:06.152830 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5596 11:13:06.156203 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5597 11:13:06.162309 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5598 11:13:06.162418 Total UI for P1: 0, mck2ui 16
5599 11:13:06.165751 best dqsien dly found for B0: ( 1, 2, 26)
5600 11:13:06.169149 Total UI for P1: 0, mck2ui 16
5601 11:13:06.172602 best dqsien dly found for B1: ( 1, 2, 26)
5602 11:13:06.179239 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5603 11:13:06.182110 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5604 11:13:06.182211
5605 11:13:06.185481 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5606 11:13:06.188465 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5607 11:13:06.192045 [Gating] SW calibration Done
5608 11:13:06.192125 ==
5609 11:13:06.195300 Dram Type= 6, Freq= 0, CH_1, rank 0
5610 11:13:06.198794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5611 11:13:06.198894 ==
5612 11:13:06.201970 RX Vref Scan: 0
5613 11:13:06.202072
5614 11:13:06.202166 RX Vref 0 -> 0, step: 1
5615 11:13:06.202263
5616 11:13:06.205028 RX Delay -80 -> 252, step: 8
5617 11:13:06.208645 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5618 11:13:06.215011 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5619 11:13:06.218484 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5620 11:13:06.221735 iDelay=208, Bit 3, Center 103 (8 ~ 199) 192
5621 11:13:06.225214 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5622 11:13:06.228560 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5623 11:13:06.231831 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5624 11:13:06.238608 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5625 11:13:06.241655 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5626 11:13:06.244945 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5627 11:13:06.248113 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5628 11:13:06.251491 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5629 11:13:06.258220 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5630 11:13:06.261719 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5631 11:13:06.264742 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5632 11:13:06.268137 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5633 11:13:06.268226 ==
5634 11:13:06.270959 Dram Type= 6, Freq= 0, CH_1, rank 0
5635 11:13:06.277595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5636 11:13:06.277678 ==
5637 11:13:06.277743 DQS Delay:
5638 11:13:06.277818 DQS0 = 0, DQS1 = 0
5639 11:13:06.280956 DQM Delay:
5640 11:13:06.281051 DQM0 = 100, DQM1 = 95
5641 11:13:06.284286 DQ Delay:
5642 11:13:06.287633 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =103
5643 11:13:06.290612 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5644 11:13:06.293804 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =87
5645 11:13:06.297818 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5646 11:13:06.297896
5647 11:13:06.297959
5648 11:13:06.298023 ==
5649 11:13:06.300636 Dram Type= 6, Freq= 0, CH_1, rank 0
5650 11:13:06.303709 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5651 11:13:06.303784 ==
5652 11:13:06.303850
5653 11:13:06.303910
5654 11:13:06.307438 TX Vref Scan disable
5655 11:13:06.310809 == TX Byte 0 ==
5656 11:13:06.314059 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5657 11:13:06.317022 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5658 11:13:06.320276 == TX Byte 1 ==
5659 11:13:06.323515 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5660 11:13:06.327023 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5661 11:13:06.327097 ==
5662 11:13:06.330319 Dram Type= 6, Freq= 0, CH_1, rank 0
5663 11:13:06.336906 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5664 11:13:06.336987 ==
5665 11:13:06.337052
5666 11:13:06.337113
5667 11:13:06.337180 TX Vref Scan disable
5668 11:13:06.341262 == TX Byte 0 ==
5669 11:13:06.344620 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5670 11:13:06.347541 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5671 11:13:06.351222 == TX Byte 1 ==
5672 11:13:06.354538 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5673 11:13:06.360622 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5674 11:13:06.360709
5675 11:13:06.360775 [DATLAT]
5676 11:13:06.360835 Freq=933, CH1 RK0
5677 11:13:06.360894
5678 11:13:06.364454 DATLAT Default: 0xd
5679 11:13:06.364533 0, 0xFFFF, sum = 0
5680 11:13:06.367296 1, 0xFFFF, sum = 0
5681 11:13:06.367375 2, 0xFFFF, sum = 0
5682 11:13:06.370679 3, 0xFFFF, sum = 0
5683 11:13:06.374061 4, 0xFFFF, sum = 0
5684 11:13:06.374140 5, 0xFFFF, sum = 0
5685 11:13:06.377499 6, 0xFFFF, sum = 0
5686 11:13:06.377574 7, 0xFFFF, sum = 0
5687 11:13:06.380737 8, 0xFFFF, sum = 0
5688 11:13:06.380817 9, 0xFFFF, sum = 0
5689 11:13:06.384248 10, 0x0, sum = 1
5690 11:13:06.384357 11, 0x0, sum = 2
5691 11:13:06.387482 12, 0x0, sum = 3
5692 11:13:06.387558 13, 0x0, sum = 4
5693 11:13:06.387621 best_step = 11
5694 11:13:06.387680
5695 11:13:06.390806 ==
5696 11:13:06.394155 Dram Type= 6, Freq= 0, CH_1, rank 0
5697 11:13:06.397087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5698 11:13:06.397187 ==
5699 11:13:06.397287 RX Vref Scan: 1
5700 11:13:06.397378
5701 11:13:06.400409 RX Vref 0 -> 0, step: 1
5702 11:13:06.400479
5703 11:13:06.403587 RX Delay -53 -> 252, step: 4
5704 11:13:06.403689
5705 11:13:06.406787 Set Vref, RX VrefLevel [Byte0]: 52
5706 11:13:06.410435 [Byte1]: 52
5707 11:13:06.410534
5708 11:13:06.413381 Final RX Vref Byte 0 = 52 to rank0
5709 11:13:06.416813 Final RX Vref Byte 1 = 52 to rank0
5710 11:13:06.419921 Final RX Vref Byte 0 = 52 to rank1
5711 11:13:06.423299 Final RX Vref Byte 1 = 52 to rank1==
5712 11:13:06.426913 Dram Type= 6, Freq= 0, CH_1, rank 0
5713 11:13:06.433633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5714 11:13:06.433752 ==
5715 11:13:06.433859 DQS Delay:
5716 11:13:06.436518 DQS0 = 0, DQS1 = 0
5717 11:13:06.436595 DQM Delay:
5718 11:13:06.436659 DQM0 = 99, DQM1 = 94
5719 11:13:06.440325 DQ Delay:
5720 11:13:06.443161 DQ0 =104, DQ1 =94, DQ2 =88, DQ3 =100
5721 11:13:06.446437 DQ4 =96, DQ5 =108, DQ6 =108, DQ7 =94
5722 11:13:06.449601 DQ8 =80, DQ9 =84, DQ10 =92, DQ11 =88
5723 11:13:06.453015 DQ12 =102, DQ13 =102, DQ14 =102, DQ15 =104
5724 11:13:06.453095
5725 11:13:06.453159
5726 11:13:06.459529 [DQSOSCAuto] RK0, (LSB)MR18= 0x717, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 419 ps
5727 11:13:06.462988 CH1 RK0: MR19=505, MR18=717
5728 11:13:06.469568 CH1_RK0: MR19=0x505, MR18=0x717, DQSOSC=414, MR23=63, INC=63, DEC=42
5729 11:13:06.469670
5730 11:13:06.472719 ----->DramcWriteLeveling(PI) begin...
5731 11:13:06.472801 ==
5732 11:13:06.476093 Dram Type= 6, Freq= 0, CH_1, rank 1
5733 11:13:06.479426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5734 11:13:06.479504 ==
5735 11:13:06.482769 Write leveling (Byte 0): 25 => 25
5736 11:13:06.486067 Write leveling (Byte 1): 31 => 31
5737 11:13:06.489316 DramcWriteLeveling(PI) end<-----
5738 11:13:06.489390
5739 11:13:06.489455 ==
5740 11:13:06.492727 Dram Type= 6, Freq= 0, CH_1, rank 1
5741 11:13:06.498985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5742 11:13:06.499059 ==
5743 11:13:06.499127 [Gating] SW mode calibration
5744 11:13:06.509335 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5745 11:13:06.512658 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5746 11:13:06.518989 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5747 11:13:06.522116 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5748 11:13:06.525537 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5749 11:13:06.532418 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5750 11:13:06.535411 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5751 11:13:06.538723 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5752 11:13:06.545395 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 0)
5753 11:13:06.548856 0 14 28 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
5754 11:13:06.551617 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5755 11:13:06.558459 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5756 11:13:06.561543 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5757 11:13:06.564856 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5758 11:13:06.571551 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5759 11:13:06.574757 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5760 11:13:06.578049 0 15 24 | B1->B0 | 2424 3131 | 0 1 | (0 0) (0 0)
5761 11:13:06.584774 0 15 28 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
5762 11:13:06.588055 1 0 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5763 11:13:06.591394 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5764 11:13:06.598054 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5765 11:13:06.601064 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5766 11:13:06.604446 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5767 11:13:06.610965 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5768 11:13:06.614353 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5769 11:13:06.617261 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5770 11:13:06.624028 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5771 11:13:06.627218 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 11:13:06.630583 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 11:13:06.637049 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 11:13:06.640338 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 11:13:06.643471 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 11:13:06.650453 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 11:13:06.653824 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 11:13:06.656739 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 11:13:06.663500 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 11:13:06.666650 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 11:13:06.669921 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 11:13:06.676579 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 11:13:06.679755 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 11:13:06.682885 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5785 11:13:06.689798 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5786 11:13:06.689884 Total UI for P1: 0, mck2ui 16
5787 11:13:06.696323 best dqsien dly found for B0: ( 1, 2, 24)
5788 11:13:06.696409 Total UI for P1: 0, mck2ui 16
5789 11:13:06.703062 best dqsien dly found for B1: ( 1, 2, 26)
5790 11:13:06.706720 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5791 11:13:06.709381 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5792 11:13:06.709455
5793 11:13:06.712789 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5794 11:13:06.715948 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5795 11:13:06.719412 [Gating] SW calibration Done
5796 11:13:06.719486 ==
5797 11:13:06.722783 Dram Type= 6, Freq= 0, CH_1, rank 1
5798 11:13:06.726289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5799 11:13:06.726388 ==
5800 11:13:06.729400 RX Vref Scan: 0
5801 11:13:06.729514
5802 11:13:06.732468 RX Vref 0 -> 0, step: 1
5803 11:13:06.732542
5804 11:13:06.732603 RX Delay -80 -> 252, step: 8
5805 11:13:06.739020 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5806 11:13:06.742452 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5807 11:13:06.745501 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5808 11:13:06.748830 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5809 11:13:06.752050 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5810 11:13:06.755678 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5811 11:13:06.762557 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5812 11:13:06.765678 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5813 11:13:06.768976 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5814 11:13:06.772296 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5815 11:13:06.775583 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5816 11:13:06.778877 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5817 11:13:06.785398 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5818 11:13:06.788442 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5819 11:13:06.791717 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5820 11:13:06.794988 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5821 11:13:06.795060 ==
5822 11:13:06.798282 Dram Type= 6, Freq= 0, CH_1, rank 1
5823 11:13:06.805034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5824 11:13:06.805115 ==
5825 11:13:06.805180 DQS Delay:
5826 11:13:06.808315 DQS0 = 0, DQS1 = 0
5827 11:13:06.808388 DQM Delay:
5828 11:13:06.808449 DQM0 = 97, DQM1 = 94
5829 11:13:06.811746 DQ Delay:
5830 11:13:06.815051 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5831 11:13:06.817729 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5832 11:13:06.821108 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5833 11:13:06.824392 DQ12 =103, DQ13 =103, DQ14 =95, DQ15 =103
5834 11:13:06.824465
5835 11:13:06.824527
5836 11:13:06.824590 ==
5837 11:13:06.827886 Dram Type= 6, Freq= 0, CH_1, rank 1
5838 11:13:06.831283 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5839 11:13:06.831401 ==
5840 11:13:06.831510
5841 11:13:06.834514
5842 11:13:06.834617 TX Vref Scan disable
5843 11:13:06.837610 == TX Byte 0 ==
5844 11:13:06.841167 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5845 11:13:06.844218 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5846 11:13:06.847366 == TX Byte 1 ==
5847 11:13:06.850839 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5848 11:13:06.854077 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5849 11:13:06.854171 ==
5850 11:13:06.857225 Dram Type= 6, Freq= 0, CH_1, rank 1
5851 11:13:06.864186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5852 11:13:06.864265 ==
5853 11:13:06.864331
5854 11:13:06.864398
5855 11:13:06.867451 TX Vref Scan disable
5856 11:13:06.867539 == TX Byte 0 ==
5857 11:13:06.873972 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5858 11:13:06.877358 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5859 11:13:06.877448 == TX Byte 1 ==
5860 11:13:06.883674 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5861 11:13:06.887022 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5862 11:13:06.887106
5863 11:13:06.887171 [DATLAT]
5864 11:13:06.890072 Freq=933, CH1 RK1
5865 11:13:06.890174
5866 11:13:06.890269 DATLAT Default: 0xb
5867 11:13:06.893401 0, 0xFFFF, sum = 0
5868 11:13:06.893481 1, 0xFFFF, sum = 0
5869 11:13:06.896849 2, 0xFFFF, sum = 0
5870 11:13:06.896953 3, 0xFFFF, sum = 0
5871 11:13:06.900192 4, 0xFFFF, sum = 0
5872 11:13:06.900291 5, 0xFFFF, sum = 0
5873 11:13:06.903365 6, 0xFFFF, sum = 0
5874 11:13:06.906879 7, 0xFFFF, sum = 0
5875 11:13:06.906986 8, 0xFFFF, sum = 0
5876 11:13:06.910231 9, 0xFFFF, sum = 0
5877 11:13:06.910308 10, 0x0, sum = 1
5878 11:13:06.913542 11, 0x0, sum = 2
5879 11:13:06.913620 12, 0x0, sum = 3
5880 11:13:06.913684 13, 0x0, sum = 4
5881 11:13:06.916891 best_step = 11
5882 11:13:06.916972
5883 11:13:06.917036 ==
5884 11:13:06.919779 Dram Type= 6, Freq= 0, CH_1, rank 1
5885 11:13:06.923582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5886 11:13:06.923687 ==
5887 11:13:06.926410 RX Vref Scan: 0
5888 11:13:06.926509
5889 11:13:06.929883 RX Vref 0 -> 0, step: 1
5890 11:13:06.929986
5891 11:13:06.930053 RX Delay -53 -> 252, step: 4
5892 11:13:06.937594 iDelay=203, Bit 0, Center 102 (11 ~ 194) 184
5893 11:13:06.940953 iDelay=203, Bit 1, Center 94 (-1 ~ 190) 192
5894 11:13:06.944271 iDelay=203, Bit 2, Center 86 (-5 ~ 178) 184
5895 11:13:06.947454 iDelay=203, Bit 3, Center 94 (3 ~ 186) 184
5896 11:13:06.950668 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5897 11:13:06.957534 iDelay=203, Bit 5, Center 108 (15 ~ 202) 188
5898 11:13:06.960733 iDelay=203, Bit 6, Center 104 (11 ~ 198) 188
5899 11:13:06.963920 iDelay=203, Bit 7, Center 92 (-1 ~ 186) 188
5900 11:13:06.967109 iDelay=203, Bit 8, Center 80 (-9 ~ 170) 180
5901 11:13:06.970340 iDelay=203, Bit 9, Center 82 (-9 ~ 174) 184
5902 11:13:06.977055 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5903 11:13:06.980330 iDelay=203, Bit 11, Center 86 (-5 ~ 178) 184
5904 11:13:06.983868 iDelay=203, Bit 12, Center 100 (11 ~ 190) 180
5905 11:13:06.986944 iDelay=203, Bit 13, Center 102 (11 ~ 194) 184
5906 11:13:06.990345 iDelay=203, Bit 14, Center 96 (7 ~ 186) 180
5907 11:13:06.996870 iDelay=203, Bit 15, Center 102 (11 ~ 194) 184
5908 11:13:06.996964 ==
5909 11:13:06.999779 Dram Type= 6, Freq= 0, CH_1, rank 1
5910 11:13:07.002963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5911 11:13:07.003075 ==
5912 11:13:07.003178 DQS Delay:
5913 11:13:07.006315 DQS0 = 0, DQS1 = 0
5914 11:13:07.006390 DQM Delay:
5915 11:13:07.009614 DQM0 = 97, DQM1 = 92
5916 11:13:07.009693 DQ Delay:
5917 11:13:07.013145 DQ0 =102, DQ1 =94, DQ2 =86, DQ3 =94
5918 11:13:07.016503 DQ4 =96, DQ5 =108, DQ6 =104, DQ7 =92
5919 11:13:07.019835 DQ8 =80, DQ9 =82, DQ10 =92, DQ11 =86
5920 11:13:07.022618 DQ12 =100, DQ13 =102, DQ14 =96, DQ15 =102
5921 11:13:07.022691
5922 11:13:07.022754
5923 11:13:07.032714 [DQSOSCAuto] RK1, (LSB)MR18= 0x71e, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 419 ps
5924 11:13:07.032813 CH1 RK1: MR19=505, MR18=71E
5925 11:13:07.039429 CH1_RK1: MR19=0x505, MR18=0x71E, DQSOSC=412, MR23=63, INC=63, DEC=42
5926 11:13:07.042727 [RxdqsGatingPostProcess] freq 933
5927 11:13:07.049380 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5928 11:13:07.052674 best DQS0 dly(2T, 0.5T) = (0, 10)
5929 11:13:07.055750 best DQS1 dly(2T, 0.5T) = (0, 10)
5930 11:13:07.058871 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5931 11:13:07.062343 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5932 11:13:07.065681 best DQS0 dly(2T, 0.5T) = (0, 10)
5933 11:13:07.068851 best DQS1 dly(2T, 0.5T) = (0, 10)
5934 11:13:07.072061 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5935 11:13:07.075141 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5936 11:13:07.078425 Pre-setting of DQS Precalculation
5937 11:13:07.082067 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5938 11:13:07.088304 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5939 11:13:07.094844 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5940 11:13:07.094929
5941 11:13:07.098252
5942 11:13:07.098342 [Calibration Summary] 1866 Mbps
5943 11:13:07.101939 CH 0, Rank 0
5944 11:13:07.102024 SW Impedance : PASS
5945 11:13:07.105008 DUTY Scan : NO K
5946 11:13:07.108225 ZQ Calibration : PASS
5947 11:13:07.108299 Jitter Meter : NO K
5948 11:13:07.111549 CBT Training : PASS
5949 11:13:07.114952 Write leveling : PASS
5950 11:13:07.115032 RX DQS gating : PASS
5951 11:13:07.118196 RX DQ/DQS(RDDQC) : PASS
5952 11:13:07.121574 TX DQ/DQS : PASS
5953 11:13:07.121646 RX DATLAT : PASS
5954 11:13:07.124549 RX DQ/DQS(Engine): PASS
5955 11:13:07.128003 TX OE : NO K
5956 11:13:07.128096 All Pass.
5957 11:13:07.128160
5958 11:13:07.128219 CH 0, Rank 1
5959 11:13:07.131202 SW Impedance : PASS
5960 11:13:07.134606 DUTY Scan : NO K
5961 11:13:07.134697 ZQ Calibration : PASS
5962 11:13:07.137971 Jitter Meter : NO K
5963 11:13:07.141240 CBT Training : PASS
5964 11:13:07.141342 Write leveling : PASS
5965 11:13:07.144623 RX DQS gating : PASS
5966 11:13:07.147776 RX DQ/DQS(RDDQC) : PASS
5967 11:13:07.147881 TX DQ/DQS : PASS
5968 11:13:07.151115 RX DATLAT : PASS
5969 11:13:07.151191 RX DQ/DQS(Engine): PASS
5970 11:13:07.154462 TX OE : NO K
5971 11:13:07.154569 All Pass.
5972 11:13:07.154667
5973 11:13:07.157845 CH 1, Rank 0
5974 11:13:07.157924 SW Impedance : PASS
5975 11:13:07.160926 DUTY Scan : NO K
5976 11:13:07.164065 ZQ Calibration : PASS
5977 11:13:07.164144 Jitter Meter : NO K
5978 11:13:07.167599 CBT Training : PASS
5979 11:13:07.170716 Write leveling : PASS
5980 11:13:07.170824 RX DQS gating : PASS
5981 11:13:07.173913 RX DQ/DQS(RDDQC) : PASS
5982 11:13:07.177513 TX DQ/DQS : PASS
5983 11:13:07.177621 RX DATLAT : PASS
5984 11:13:07.180448 RX DQ/DQS(Engine): PASS
5985 11:13:07.184310 TX OE : NO K
5986 11:13:07.184410 All Pass.
5987 11:13:07.184476
5988 11:13:07.184535 CH 1, Rank 1
5989 11:13:07.187460 SW Impedance : PASS
5990 11:13:07.190670 DUTY Scan : NO K
5991 11:13:07.190773 ZQ Calibration : PASS
5992 11:13:07.194112 Jitter Meter : NO K
5993 11:13:07.197601 CBT Training : PASS
5994 11:13:07.197705 Write leveling : PASS
5995 11:13:07.200335 RX DQS gating : PASS
5996 11:13:07.203675 RX DQ/DQS(RDDQC) : PASS
5997 11:13:07.203784 TX DQ/DQS : PASS
5998 11:13:07.207055 RX DATLAT : PASS
5999 11:13:07.210387 RX DQ/DQS(Engine): PASS
6000 11:13:07.210496 TX OE : NO K
6001 11:13:07.213738 All Pass.
6002 11:13:07.213836
6003 11:13:07.213926 DramC Write-DBI off
6004 11:13:07.217153 PER_BANK_REFRESH: Hybrid Mode
6005 11:13:07.217257 TX_TRACKING: ON
6006 11:13:07.226614 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6007 11:13:07.230022 [FAST_K] Save calibration result to emmc
6008 11:13:07.233389 dramc_set_vcore_voltage set vcore to 650000
6009 11:13:07.236572 Read voltage for 400, 6
6010 11:13:07.236681 Vio18 = 0
6011 11:13:07.239984 Vcore = 650000
6012 11:13:07.240095 Vdram = 0
6013 11:13:07.240198 Vddq = 0
6014 11:13:07.243516 Vmddr = 0
6015 11:13:07.246348 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6016 11:13:07.253017 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6017 11:13:07.253135 MEM_TYPE=3, freq_sel=20
6018 11:13:07.256426 sv_algorithm_assistance_LP4_800
6019 11:13:07.263058 ============ PULL DRAM RESETB DOWN ============
6020 11:13:07.266366 ========== PULL DRAM RESETB DOWN end =========
6021 11:13:07.269371 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6022 11:13:07.273081 ===================================
6023 11:13:07.275930 LPDDR4 DRAM CONFIGURATION
6024 11:13:07.279359 ===================================
6025 11:13:07.282903 EX_ROW_EN[0] = 0x0
6026 11:13:07.283008 EX_ROW_EN[1] = 0x0
6027 11:13:07.286054 LP4Y_EN = 0x0
6028 11:13:07.286156 WORK_FSP = 0x0
6029 11:13:07.289123 WL = 0x2
6030 11:13:07.289224 RL = 0x2
6031 11:13:07.292297 BL = 0x2
6032 11:13:07.292375 RPST = 0x0
6033 11:13:07.295681 RD_PRE = 0x0
6034 11:13:07.295785 WR_PRE = 0x1
6035 11:13:07.298915 WR_PST = 0x0
6036 11:13:07.299014 DBI_WR = 0x0
6037 11:13:07.302156 DBI_RD = 0x0
6038 11:13:07.302258 OTF = 0x1
6039 11:13:07.305507 ===================================
6040 11:13:07.308776 ===================================
6041 11:13:07.312159 ANA top config
6042 11:13:07.315504 ===================================
6043 11:13:07.318865 DLL_ASYNC_EN = 0
6044 11:13:07.318950 ALL_SLAVE_EN = 1
6045 11:13:07.322168 NEW_RANK_MODE = 1
6046 11:13:07.325679 DLL_IDLE_MODE = 1
6047 11:13:07.328929 LP45_APHY_COMB_EN = 1
6048 11:13:07.332292 TX_ODT_DIS = 1
6049 11:13:07.332382 NEW_8X_MODE = 1
6050 11:13:07.335088 ===================================
6051 11:13:07.338308 ===================================
6052 11:13:07.341657 data_rate = 800
6053 11:13:07.345063 CKR = 1
6054 11:13:07.348593 DQ_P2S_RATIO = 4
6055 11:13:07.351946 ===================================
6056 11:13:07.355106 CA_P2S_RATIO = 4
6057 11:13:07.358391 DQ_CA_OPEN = 0
6058 11:13:07.358478 DQ_SEMI_OPEN = 1
6059 11:13:07.361895 CA_SEMI_OPEN = 1
6060 11:13:07.365223 CA_FULL_RATE = 0
6061 11:13:07.368618 DQ_CKDIV4_EN = 0
6062 11:13:07.371814 CA_CKDIV4_EN = 1
6063 11:13:07.374944 CA_PREDIV_EN = 0
6064 11:13:07.375030 PH8_DLY = 0
6065 11:13:07.378019 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6066 11:13:07.381568 DQ_AAMCK_DIV = 0
6067 11:13:07.384867 CA_AAMCK_DIV = 0
6068 11:13:07.387988 CA_ADMCK_DIV = 4
6069 11:13:07.391685 DQ_TRACK_CA_EN = 0
6070 11:13:07.391772 CA_PICK = 800
6071 11:13:07.394793 CA_MCKIO = 400
6072 11:13:07.397982 MCKIO_SEMI = 400
6073 11:13:07.401004 PLL_FREQ = 3016
6074 11:13:07.404808 DQ_UI_PI_RATIO = 32
6075 11:13:07.407630 CA_UI_PI_RATIO = 32
6076 11:13:07.411503 ===================================
6077 11:13:07.414261 ===================================
6078 11:13:07.418064 memory_type:LPDDR4
6079 11:13:07.418151 GP_NUM : 10
6080 11:13:07.420901 SRAM_EN : 1
6081 11:13:07.420988 MD32_EN : 0
6082 11:13:07.424653 ===================================
6083 11:13:07.427492 [ANA_INIT] >>>>>>>>>>>>>>
6084 11:13:07.430968 <<<<<< [CONFIGURE PHASE]: ANA_TX
6085 11:13:07.434323 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6086 11:13:07.437652 ===================================
6087 11:13:07.440621 data_rate = 800,PCW = 0X7400
6088 11:13:07.444298 ===================================
6089 11:13:07.447330 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6090 11:13:07.454159 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6091 11:13:07.463843 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6092 11:13:07.470744 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6093 11:13:07.473607 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6094 11:13:07.477161 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6095 11:13:07.477249 [ANA_INIT] flow start
6096 11:13:07.480159 [ANA_INIT] PLL >>>>>>>>
6097 11:13:07.483527 [ANA_INIT] PLL <<<<<<<<
6098 11:13:07.483644 [ANA_INIT] MIDPI >>>>>>>>
6099 11:13:07.487073 [ANA_INIT] MIDPI <<<<<<<<
6100 11:13:07.490296 [ANA_INIT] DLL >>>>>>>>
6101 11:13:07.490404 [ANA_INIT] flow end
6102 11:13:07.496584 ============ LP4 DIFF to SE enter ============
6103 11:13:07.500302 ============ LP4 DIFF to SE exit ============
6104 11:13:07.503570 [ANA_INIT] <<<<<<<<<<<<<
6105 11:13:07.506456 [Flow] Enable top DCM control >>>>>
6106 11:13:07.510224 [Flow] Enable top DCM control <<<<<
6107 11:13:07.510312 Enable DLL master slave shuffle
6108 11:13:07.516622 ==============================================================
6109 11:13:07.519917 Gating Mode config
6110 11:13:07.522939 ==============================================================
6111 11:13:07.526126 Config description:
6112 11:13:07.536258 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6113 11:13:07.543041 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6114 11:13:07.546236 SELPH_MODE 0: By rank 1: By Phase
6115 11:13:07.552448 ==============================================================
6116 11:13:07.556247 GAT_TRACK_EN = 0
6117 11:13:07.559048 RX_GATING_MODE = 2
6118 11:13:07.562512 RX_GATING_TRACK_MODE = 2
6119 11:13:07.565620 SELPH_MODE = 1
6120 11:13:07.569088 PICG_EARLY_EN = 1
6121 11:13:07.572361 VALID_LAT_VALUE = 1
6122 11:13:07.575792 ==============================================================
6123 11:13:07.579151 Enter into Gating configuration >>>>
6124 11:13:07.582358 Exit from Gating configuration <<<<
6125 11:13:07.585552 Enter into DVFS_PRE_config >>>>>
6126 11:13:07.598179 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6127 11:13:07.601988 Exit from DVFS_PRE_config <<<<<
6128 11:13:07.602116 Enter into PICG configuration >>>>
6129 11:13:07.605115 Exit from PICG configuration <<<<
6130 11:13:07.608292 [RX_INPUT] configuration >>>>>
6131 11:13:07.611441 [RX_INPUT] configuration <<<<<
6132 11:13:07.618021 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6133 11:13:07.621522 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6134 11:13:07.628174 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6135 11:13:07.634624 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6136 11:13:07.641346 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6137 11:13:07.648053 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6138 11:13:07.650864 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6139 11:13:07.654254 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6140 11:13:07.661018 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6141 11:13:07.664220 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6142 11:13:07.667581 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6143 11:13:07.670747 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6144 11:13:07.674001 ===================================
6145 11:13:07.677380 LPDDR4 DRAM CONFIGURATION
6146 11:13:07.680857 ===================================
6147 11:13:07.684077 EX_ROW_EN[0] = 0x0
6148 11:13:07.684163 EX_ROW_EN[1] = 0x0
6149 11:13:07.687538 LP4Y_EN = 0x0
6150 11:13:07.687623 WORK_FSP = 0x0
6151 11:13:07.690829 WL = 0x2
6152 11:13:07.690915 RL = 0x2
6153 11:13:07.694115 BL = 0x2
6154 11:13:07.694205 RPST = 0x0
6155 11:13:07.697059 RD_PRE = 0x0
6156 11:13:07.700679 WR_PRE = 0x1
6157 11:13:07.700763 WR_PST = 0x0
6158 11:13:07.703749 DBI_WR = 0x0
6159 11:13:07.703833 DBI_RD = 0x0
6160 11:13:07.707005 OTF = 0x1
6161 11:13:07.710213 ===================================
6162 11:13:07.713347 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6163 11:13:07.716953 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6164 11:13:07.723340 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6165 11:13:07.726940 ===================================
6166 11:13:07.727024 LPDDR4 DRAM CONFIGURATION
6167 11:13:07.730241 ===================================
6168 11:13:07.733073 EX_ROW_EN[0] = 0x10
6169 11:13:07.733159 EX_ROW_EN[1] = 0x0
6170 11:13:07.736826 LP4Y_EN = 0x0
6171 11:13:07.736947 WORK_FSP = 0x0
6172 11:13:07.739668 WL = 0x2
6173 11:13:07.742971 RL = 0x2
6174 11:13:07.743053 BL = 0x2
6175 11:13:07.746442 RPST = 0x0
6176 11:13:07.746524 RD_PRE = 0x0
6177 11:13:07.749796 WR_PRE = 0x1
6178 11:13:07.749877 WR_PST = 0x0
6179 11:13:07.753171 DBI_WR = 0x0
6180 11:13:07.753252 DBI_RD = 0x0
6181 11:13:07.756296 OTF = 0x1
6182 11:13:07.759733 ===================================
6183 11:13:07.766426 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6184 11:13:07.769826 nWR fixed to 30
6185 11:13:07.769909 [ModeRegInit_LP4] CH0 RK0
6186 11:13:07.772903 [ModeRegInit_LP4] CH0 RK1
6187 11:13:07.776334 [ModeRegInit_LP4] CH1 RK0
6188 11:13:07.779789 [ModeRegInit_LP4] CH1 RK1
6189 11:13:07.779871 match AC timing 19
6190 11:13:07.782498 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6191 11:13:07.789358 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6192 11:13:07.792834 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6193 11:13:07.796168 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6194 11:13:07.802399 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6195 11:13:07.802526 ==
6196 11:13:07.805566 Dram Type= 6, Freq= 0, CH_0, rank 0
6197 11:13:07.809125 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6198 11:13:07.809244 ==
6199 11:13:07.815485 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6200 11:13:07.822264 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6201 11:13:07.825399 [CA 0] Center 36 (8~64) winsize 57
6202 11:13:07.828851 [CA 1] Center 36 (8~64) winsize 57
6203 11:13:07.828957 [CA 2] Center 36 (8~64) winsize 57
6204 11:13:07.831920 [CA 3] Center 36 (8~64) winsize 57
6205 11:13:07.835277 [CA 4] Center 36 (8~64) winsize 57
6206 11:13:07.838646 [CA 5] Center 36 (8~64) winsize 57
6207 11:13:07.838720
6208 11:13:07.842117 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6209 11:13:07.845466
6210 11:13:07.848408 [CATrainingPosCal] consider 1 rank data
6211 11:13:07.851798 u2DelayCellTimex100 = 270/100 ps
6212 11:13:07.855196 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6213 11:13:07.858559 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6214 11:13:07.861857 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6215 11:13:07.865409 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6216 11:13:07.868129 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6217 11:13:07.871519 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6218 11:13:07.871603
6219 11:13:07.874886 CA PerBit enable=1, Macro0, CA PI delay=36
6220 11:13:07.874970
6221 11:13:07.878050 [CBTSetCACLKResult] CA Dly = 36
6222 11:13:07.881338 CS Dly: 1 (0~32)
6223 11:13:07.881421 ==
6224 11:13:07.884797 Dram Type= 6, Freq= 0, CH_0, rank 1
6225 11:13:07.888110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6226 11:13:07.888195 ==
6227 11:13:07.894486 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6228 11:13:07.900961 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6229 11:13:07.904185 [CA 0] Center 36 (8~64) winsize 57
6230 11:13:07.907406 [CA 1] Center 36 (8~64) winsize 57
6231 11:13:07.907490 [CA 2] Center 36 (8~64) winsize 57
6232 11:13:07.911111 [CA 3] Center 36 (8~64) winsize 57
6233 11:13:07.914124 [CA 4] Center 36 (8~64) winsize 57
6234 11:13:07.917755 [CA 5] Center 36 (8~64) winsize 57
6235 11:13:07.917848
6236 11:13:07.920985 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6237 11:13:07.921075
6238 11:13:07.927728 [CATrainingPosCal] consider 2 rank data
6239 11:13:07.927806 u2DelayCellTimex100 = 270/100 ps
6240 11:13:07.933891 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6241 11:13:07.937107 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 11:13:07.940846 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 11:13:07.944117 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 11:13:07.946943 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 11:13:07.950265 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 11:13:07.950347
6247 11:13:07.953693 CA PerBit enable=1, Macro0, CA PI delay=36
6248 11:13:07.953775
6249 11:13:07.957060 [CBTSetCACLKResult] CA Dly = 36
6250 11:13:07.960284 CS Dly: 1 (0~32)
6251 11:13:07.960394
6252 11:13:07.963658 ----->DramcWriteLeveling(PI) begin...
6253 11:13:07.963742 ==
6254 11:13:07.966906 Dram Type= 6, Freq= 0, CH_0, rank 0
6255 11:13:07.970406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6256 11:13:07.970489 ==
6257 11:13:07.973806 Write leveling (Byte 0): 40 => 8
6258 11:13:07.977084 Write leveling (Byte 1): 40 => 8
6259 11:13:07.979860 DramcWriteLeveling(PI) end<-----
6260 11:13:07.979942
6261 11:13:07.980007 ==
6262 11:13:07.983629 Dram Type= 6, Freq= 0, CH_0, rank 0
6263 11:13:07.986438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6264 11:13:07.986534 ==
6265 11:13:07.989845 [Gating] SW mode calibration
6266 11:13:07.996499 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6267 11:13:08.003228 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6268 11:13:08.006680 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6269 11:13:08.010177 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6270 11:13:08.015980 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6271 11:13:08.019410 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6272 11:13:08.026092 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6273 11:13:08.029306 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6274 11:13:08.032896 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6275 11:13:08.035990 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6276 11:13:08.042823 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6277 11:13:08.046012 Total UI for P1: 0, mck2ui 16
6278 11:13:08.049379 best dqsien dly found for B0: ( 0, 14, 24)
6279 11:13:08.052656 Total UI for P1: 0, mck2ui 16
6280 11:13:08.055468 best dqsien dly found for B1: ( 0, 14, 24)
6281 11:13:08.058843 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6282 11:13:08.062080 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6283 11:13:08.062153
6284 11:13:08.065437 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6285 11:13:08.068669 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6286 11:13:08.071936 [Gating] SW calibration Done
6287 11:13:08.072007 ==
6288 11:13:08.075235 Dram Type= 6, Freq= 0, CH_0, rank 0
6289 11:13:08.078741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6290 11:13:08.082124 ==
6291 11:13:08.082200 RX Vref Scan: 0
6292 11:13:08.082263
6293 11:13:08.085371 RX Vref 0 -> 0, step: 1
6294 11:13:08.085446
6295 11:13:08.088655 RX Delay -410 -> 252, step: 16
6296 11:13:08.092007 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6297 11:13:08.095498 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6298 11:13:08.098747 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6299 11:13:08.105068 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6300 11:13:08.108426 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6301 11:13:08.111811 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6302 11:13:08.115199 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6303 11:13:08.121553 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6304 11:13:08.124658 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6305 11:13:08.127897 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6306 11:13:08.134515 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6307 11:13:08.138306 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6308 11:13:08.141275 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6309 11:13:08.145009 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6310 11:13:08.151461 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6311 11:13:08.154869 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6312 11:13:08.154941 ==
6313 11:13:08.157628 Dram Type= 6, Freq= 0, CH_0, rank 0
6314 11:13:08.160964 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6315 11:13:08.161037 ==
6316 11:13:08.164300 DQS Delay:
6317 11:13:08.164368 DQS0 = 35, DQS1 = 59
6318 11:13:08.167697 DQM Delay:
6319 11:13:08.167767 DQM0 = 4, DQM1 = 17
6320 11:13:08.167827 DQ Delay:
6321 11:13:08.170996 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6322 11:13:08.174190 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6323 11:13:08.177690 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =16
6324 11:13:08.180494 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6325 11:13:08.180564
6326 11:13:08.180624
6327 11:13:08.180680 ==
6328 11:13:08.183785 Dram Type= 6, Freq= 0, CH_0, rank 0
6329 11:13:08.190841 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6330 11:13:08.190918 ==
6331 11:13:08.190988
6332 11:13:08.191047
6333 11:13:08.191103 TX Vref Scan disable
6334 11:13:08.193717 == TX Byte 0 ==
6335 11:13:08.197099 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6336 11:13:08.200550 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6337 11:13:08.203873 == TX Byte 1 ==
6338 11:13:08.206781 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6339 11:13:08.210091 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6340 11:13:08.213536 ==
6341 11:13:08.216959 Dram Type= 6, Freq= 0, CH_0, rank 0
6342 11:13:08.219788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6343 11:13:08.219855 ==
6344 11:13:08.219914
6345 11:13:08.219983
6346 11:13:08.223103 TX Vref Scan disable
6347 11:13:08.223182 == TX Byte 0 ==
6348 11:13:08.227022 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6349 11:13:08.233452 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6350 11:13:08.233609 == TX Byte 1 ==
6351 11:13:08.236571 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6352 11:13:08.243198 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6353 11:13:08.243348
6354 11:13:08.243427 [DATLAT]
6355 11:13:08.243487 Freq=400, CH0 RK0
6356 11:13:08.243544
6357 11:13:08.246620 DATLAT Default: 0xf
6358 11:13:08.249491 0, 0xFFFF, sum = 0
6359 11:13:08.249575 1, 0xFFFF, sum = 0
6360 11:13:08.252851 2, 0xFFFF, sum = 0
6361 11:13:08.252922 3, 0xFFFF, sum = 0
6362 11:13:08.256343 4, 0xFFFF, sum = 0
6363 11:13:08.256439 5, 0xFFFF, sum = 0
6364 11:13:08.259388 6, 0xFFFF, sum = 0
6365 11:13:08.259481 7, 0xFFFF, sum = 0
6366 11:13:08.262777 8, 0xFFFF, sum = 0
6367 11:13:08.262872 9, 0xFFFF, sum = 0
6368 11:13:08.266028 10, 0xFFFF, sum = 0
6369 11:13:08.266102 11, 0xFFFF, sum = 0
6370 11:13:08.269308 12, 0xFFFF, sum = 0
6371 11:13:08.269377 13, 0x0, sum = 1
6372 11:13:08.272765 14, 0x0, sum = 2
6373 11:13:08.272841 15, 0x0, sum = 3
6374 11:13:08.275979 16, 0x0, sum = 4
6375 11:13:08.276087 best_step = 14
6376 11:13:08.276147
6377 11:13:08.276211 ==
6378 11:13:08.279166 Dram Type= 6, Freq= 0, CH_0, rank 0
6379 11:13:08.286044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6380 11:13:08.286135 ==
6381 11:13:08.286196 RX Vref Scan: 1
6382 11:13:08.286253
6383 11:13:08.289365 RX Vref 0 -> 0, step: 1
6384 11:13:08.289432
6385 11:13:08.292636 RX Delay -359 -> 252, step: 8
6386 11:13:08.292725
6387 11:13:08.295906 Set Vref, RX VrefLevel [Byte0]: 51
6388 11:13:08.299329 [Byte1]: 47
6389 11:13:08.299399
6390 11:13:08.302693 Final RX Vref Byte 0 = 51 to rank0
6391 11:13:08.305521 Final RX Vref Byte 1 = 47 to rank0
6392 11:13:08.309084 Final RX Vref Byte 0 = 51 to rank1
6393 11:13:08.312195 Final RX Vref Byte 1 = 47 to rank1==
6394 11:13:08.315541 Dram Type= 6, Freq= 0, CH_0, rank 0
6395 11:13:08.322375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6396 11:13:08.322452 ==
6397 11:13:08.322512 DQS Delay:
6398 11:13:08.322577 DQS0 = 44, DQS1 = 60
6399 11:13:08.325714 DQM Delay:
6400 11:13:08.325781 DQM0 = 10, DQM1 = 18
6401 11:13:08.329135 DQ Delay:
6402 11:13:08.331939 DQ0 =12, DQ1 =12, DQ2 =4, DQ3 =8
6403 11:13:08.332055 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6404 11:13:08.335486 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =12
6405 11:13:08.338905 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6406 11:13:08.342082
6407 11:13:08.342163
6408 11:13:08.348925 [DQSOSCAuto] RK0, (LSB)MR18= 0x9386, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
6409 11:13:08.351899 CH0 RK0: MR19=C0C, MR18=9386
6410 11:13:08.358494 CH0_RK0: MR19=0xC0C, MR18=0x9386, DQSOSC=391, MR23=63, INC=386, DEC=257
6411 11:13:08.358579 ==
6412 11:13:08.361583 Dram Type= 6, Freq= 0, CH_0, rank 1
6413 11:13:08.364975 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6414 11:13:08.365058 ==
6415 11:13:08.368252 [Gating] SW mode calibration
6416 11:13:08.375041 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6417 11:13:08.381731 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6418 11:13:08.384997 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6419 11:13:08.388443 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6420 11:13:08.394711 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6421 11:13:08.397893 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6422 11:13:08.401581 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6423 11:13:08.407763 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6424 11:13:08.411194 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6425 11:13:08.414639 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6426 11:13:08.420857 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6427 11:13:08.420941 Total UI for P1: 0, mck2ui 16
6428 11:13:08.427664 best dqsien dly found for B0: ( 0, 14, 24)
6429 11:13:08.427748 Total UI for P1: 0, mck2ui 16
6430 11:13:08.434264 best dqsien dly found for B1: ( 0, 14, 24)
6431 11:13:08.437542 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6432 11:13:08.440849 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6433 11:13:08.440933
6434 11:13:08.444141 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6435 11:13:08.447385 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6436 11:13:08.450597 [Gating] SW calibration Done
6437 11:13:08.450681 ==
6438 11:13:08.454240 Dram Type= 6, Freq= 0, CH_0, rank 1
6439 11:13:08.457258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6440 11:13:08.457342 ==
6441 11:13:08.460369 RX Vref Scan: 0
6442 11:13:08.460452
6443 11:13:08.463491 RX Vref 0 -> 0, step: 1
6444 11:13:08.463630
6445 11:13:08.463693 RX Delay -410 -> 252, step: 16
6446 11:13:08.470233 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6447 11:13:08.473747 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6448 11:13:08.477091 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6449 11:13:08.483801 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6450 11:13:08.487121 iDelay=230, Bit 4, Center -19 (-266 ~ 229) 496
6451 11:13:08.490570 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6452 11:13:08.493869 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6453 11:13:08.499944 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6454 11:13:08.503401 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6455 11:13:08.506833 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6456 11:13:08.510104 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6457 11:13:08.516919 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6458 11:13:08.519648 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6459 11:13:08.523056 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6460 11:13:08.526489 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6461 11:13:08.533179 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6462 11:13:08.533265 ==
6463 11:13:08.536540 Dram Type= 6, Freq= 0, CH_0, rank 1
6464 11:13:08.539589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6465 11:13:08.539674 ==
6466 11:13:08.539740 DQS Delay:
6467 11:13:08.542722 DQS0 = 35, DQS1 = 59
6468 11:13:08.542812 DQM Delay:
6469 11:13:08.546268 DQM0 = 8, DQM1 = 17
6470 11:13:08.546357 DQ Delay:
6471 11:13:08.549567 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6472 11:13:08.552886 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6473 11:13:08.555969 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6474 11:13:08.559371 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6475 11:13:08.559460
6476 11:13:08.559526
6477 11:13:08.559588 ==
6478 11:13:08.562905 Dram Type= 6, Freq= 0, CH_0, rank 1
6479 11:13:08.566229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6480 11:13:08.566316 ==
6481 11:13:08.566383
6482 11:13:08.569335
6483 11:13:08.569479 TX Vref Scan disable
6484 11:13:08.572557 == TX Byte 0 ==
6485 11:13:08.575801 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6486 11:13:08.579491 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6487 11:13:08.582563 == TX Byte 1 ==
6488 11:13:08.586046 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6489 11:13:08.589090 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6490 11:13:08.589175 ==
6491 11:13:08.592624 Dram Type= 6, Freq= 0, CH_0, rank 1
6492 11:13:08.595951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6493 11:13:08.598856 ==
6494 11:13:08.598972
6495 11:13:08.599066
6496 11:13:08.599157 TX Vref Scan disable
6497 11:13:08.602255 == TX Byte 0 ==
6498 11:13:08.605843 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6499 11:13:08.609066 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6500 11:13:08.612016 == TX Byte 1 ==
6501 11:13:08.615354 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6502 11:13:08.618725 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6503 11:13:08.618830
6504 11:13:08.622139 [DATLAT]
6505 11:13:08.622240 Freq=400, CH0 RK1
6506 11:13:08.622332
6507 11:13:08.625144 DATLAT Default: 0xe
6508 11:13:08.625246 0, 0xFFFF, sum = 0
6509 11:13:08.628640 1, 0xFFFF, sum = 0
6510 11:13:08.628726 2, 0xFFFF, sum = 0
6511 11:13:08.632039 3, 0xFFFF, sum = 0
6512 11:13:08.632124 4, 0xFFFF, sum = 0
6513 11:13:08.635361 5, 0xFFFF, sum = 0
6514 11:13:08.635446 6, 0xFFFF, sum = 0
6515 11:13:08.638714 7, 0xFFFF, sum = 0
6516 11:13:08.638796 8, 0xFFFF, sum = 0
6517 11:13:08.641674 9, 0xFFFF, sum = 0
6518 11:13:08.641757 10, 0xFFFF, sum = 0
6519 11:13:08.645207 11, 0xFFFF, sum = 0
6520 11:13:08.648606 12, 0xFFFF, sum = 0
6521 11:13:08.648690 13, 0x0, sum = 1
6522 11:13:08.648755 14, 0x0, sum = 2
6523 11:13:08.651521 15, 0x0, sum = 3
6524 11:13:08.651604 16, 0x0, sum = 4
6525 11:13:08.655028 best_step = 14
6526 11:13:08.655125
6527 11:13:08.655212 ==
6528 11:13:08.658318 Dram Type= 6, Freq= 0, CH_0, rank 1
6529 11:13:08.661745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6530 11:13:08.661828 ==
6531 11:13:08.664495 RX Vref Scan: 0
6532 11:13:08.664576
6533 11:13:08.667754 RX Vref 0 -> 0, step: 1
6534 11:13:08.667834
6535 11:13:08.667898 RX Delay -359 -> 252, step: 8
6536 11:13:08.676480 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6537 11:13:08.679621 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6538 11:13:08.683494 iDelay=209, Bit 2, Center -40 (-279 ~ 200) 480
6539 11:13:08.686466 iDelay=209, Bit 3, Center -36 (-271 ~ 200) 472
6540 11:13:08.693064 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6541 11:13:08.696398 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6542 11:13:08.699728 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6543 11:13:08.706091 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6544 11:13:08.709432 iDelay=209, Bit 8, Center -52 (-295 ~ 192) 488
6545 11:13:08.712889 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6546 11:13:08.716314 iDelay=209, Bit 10, Center -40 (-279 ~ 200) 480
6547 11:13:08.722561 iDelay=209, Bit 11, Center -48 (-287 ~ 192) 480
6548 11:13:08.726042 iDelay=209, Bit 12, Center -44 (-287 ~ 200) 488
6549 11:13:08.729548 iDelay=209, Bit 13, Center -40 (-279 ~ 200) 480
6550 11:13:08.732457 iDelay=209, Bit 14, Center -32 (-271 ~ 208) 480
6551 11:13:08.739280 iDelay=209, Bit 15, Center -40 (-279 ~ 200) 480
6552 11:13:08.739361 ==
6553 11:13:08.742613 Dram Type= 6, Freq= 0, CH_0, rank 1
6554 11:13:08.745550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6555 11:13:08.745632 ==
6556 11:13:08.745697 DQS Delay:
6557 11:13:08.748971 DQS0 = 44, DQS1 = 60
6558 11:13:08.749052 DQM Delay:
6559 11:13:08.752359 DQM0 = 9, DQM1 = 15
6560 11:13:08.752441 DQ Delay:
6561 11:13:08.755802 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6562 11:13:08.759174 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6563 11:13:08.762422 DQ8 =8, DQ9 =0, DQ10 =20, DQ11 =12
6564 11:13:08.765852 DQ12 =16, DQ13 =20, DQ14 =28, DQ15 =20
6565 11:13:08.765933
6566 11:13:08.765997
6567 11:13:08.775783 [DQSOSCAuto] RK1, (LSB)MR18= 0x827a, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
6568 11:13:08.775867 CH0 RK1: MR19=C0C, MR18=827A
6569 11:13:08.782037 CH0_RK1: MR19=0xC0C, MR18=0x827A, DQSOSC=393, MR23=63, INC=382, DEC=254
6570 11:13:08.785356 [RxdqsGatingPostProcess] freq 400
6571 11:13:08.791598 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6572 11:13:08.795187 best DQS0 dly(2T, 0.5T) = (0, 10)
6573 11:13:08.798487 best DQS1 dly(2T, 0.5T) = (0, 10)
6574 11:13:08.801435 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6575 11:13:08.804793 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6576 11:13:08.807938 best DQS0 dly(2T, 0.5T) = (0, 10)
6577 11:13:08.811279 best DQS1 dly(2T, 0.5T) = (0, 10)
6578 11:13:08.814774 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6579 11:13:08.818195 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6580 11:13:08.818289 Pre-setting of DQS Precalculation
6581 11:13:08.824535 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6582 11:13:08.824604 ==
6583 11:13:08.828068 Dram Type= 6, Freq= 0, CH_1, rank 0
6584 11:13:08.831546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6585 11:13:08.831638 ==
6586 11:13:08.837853 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6587 11:13:08.844726 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6588 11:13:08.848062 [CA 0] Center 36 (8~64) winsize 57
6589 11:13:08.850976 [CA 1] Center 36 (8~64) winsize 57
6590 11:13:08.854327 [CA 2] Center 36 (8~64) winsize 57
6591 11:13:08.857786 [CA 3] Center 36 (8~64) winsize 57
6592 11:13:08.857881 [CA 4] Center 36 (8~64) winsize 57
6593 11:13:08.861136 [CA 5] Center 36 (8~64) winsize 57
6594 11:13:08.861233
6595 11:13:08.867291 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6596 11:13:08.867384
6597 11:13:08.871175 [CATrainingPosCal] consider 1 rank data
6598 11:13:08.873941 u2DelayCellTimex100 = 270/100 ps
6599 11:13:08.877359 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6600 11:13:08.880576 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6601 11:13:08.884358 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6602 11:13:08.887524 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6603 11:13:08.890718 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6604 11:13:08.893937 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6605 11:13:08.894018
6606 11:13:08.897142 CA PerBit enable=1, Macro0, CA PI delay=36
6607 11:13:08.897223
6608 11:13:08.900553 [CBTSetCACLKResult] CA Dly = 36
6609 11:13:08.903778 CS Dly: 1 (0~32)
6610 11:13:08.903858 ==
6611 11:13:08.907549 Dram Type= 6, Freq= 0, CH_1, rank 1
6612 11:13:08.910227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6613 11:13:08.910341 ==
6614 11:13:08.916788 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6615 11:13:08.923505 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6616 11:13:08.926864 [CA 0] Center 36 (8~64) winsize 57
6617 11:13:08.930131 [CA 1] Center 36 (8~64) winsize 57
6618 11:13:08.933625 [CA 2] Center 36 (8~64) winsize 57
6619 11:13:08.933709 [CA 3] Center 36 (8~64) winsize 57
6620 11:13:08.936436 [CA 4] Center 36 (8~64) winsize 57
6621 11:13:08.939883 [CA 5] Center 36 (8~64) winsize 57
6622 11:13:08.939986
6623 11:13:08.946376 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6624 11:13:08.946454
6625 11:13:08.949703 [CATrainingPosCal] consider 2 rank data
6626 11:13:08.953066 u2DelayCellTimex100 = 270/100 ps
6627 11:13:08.956608 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6628 11:13:08.959374 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 11:13:08.962921 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 11:13:08.966209 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 11:13:08.969760 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 11:13:08.972888 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 11:13:08.972969
6634 11:13:08.976239 CA PerBit enable=1, Macro0, CA PI delay=36
6635 11:13:08.976319
6636 11:13:08.979267 [CBTSetCACLKResult] CA Dly = 36
6637 11:13:08.982618 CS Dly: 1 (0~32)
6638 11:13:08.982699
6639 11:13:08.986100 ----->DramcWriteLeveling(PI) begin...
6640 11:13:08.986182 ==
6641 11:13:08.989268 Dram Type= 6, Freq= 0, CH_1, rank 0
6642 11:13:08.992581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6643 11:13:08.992663 ==
6644 11:13:08.995420 Write leveling (Byte 0): 40 => 8
6645 11:13:08.999228 Write leveling (Byte 1): 40 => 8
6646 11:13:09.002561 DramcWriteLeveling(PI) end<-----
6647 11:13:09.002642
6648 11:13:09.002706 ==
6649 11:13:09.005609 Dram Type= 6, Freq= 0, CH_1, rank 0
6650 11:13:09.009214 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6651 11:13:09.009296 ==
6652 11:13:09.012204 [Gating] SW mode calibration
6653 11:13:09.018821 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6654 11:13:09.025511 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6655 11:13:09.029142 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6656 11:13:09.035314 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6657 11:13:09.038729 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6658 11:13:09.041654 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6659 11:13:09.048650 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6660 11:13:09.051457 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6661 11:13:09.054847 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6662 11:13:09.061838 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6663 11:13:09.065154 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6664 11:13:09.067986 Total UI for P1: 0, mck2ui 16
6665 11:13:09.071458 best dqsien dly found for B0: ( 0, 14, 24)
6666 11:13:09.074878 Total UI for P1: 0, mck2ui 16
6667 11:13:09.078154 best dqsien dly found for B1: ( 0, 14, 24)
6668 11:13:09.081509 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6669 11:13:09.085143 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6670 11:13:09.085244
6671 11:13:09.087839 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6672 11:13:09.091092 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6673 11:13:09.094458 [Gating] SW calibration Done
6674 11:13:09.094531 ==
6675 11:13:09.098250 Dram Type= 6, Freq= 0, CH_1, rank 0
6676 11:13:09.101245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6677 11:13:09.104482 ==
6678 11:13:09.104556 RX Vref Scan: 0
6679 11:13:09.104618
6680 11:13:09.108151 RX Vref 0 -> 0, step: 1
6681 11:13:09.108226
6682 11:13:09.111471 RX Delay -410 -> 252, step: 16
6683 11:13:09.114644 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6684 11:13:09.117721 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6685 11:13:09.124405 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6686 11:13:09.127665 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6687 11:13:09.131113 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6688 11:13:09.134430 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6689 11:13:09.137729 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6690 11:13:09.144296 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6691 11:13:09.147524 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6692 11:13:09.150764 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6693 11:13:09.157170 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6694 11:13:09.160626 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6695 11:13:09.164014 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6696 11:13:09.167493 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6697 11:13:09.173698 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6698 11:13:09.177223 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6699 11:13:09.177336 ==
6700 11:13:09.180568 Dram Type= 6, Freq= 0, CH_1, rank 0
6701 11:13:09.183879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6702 11:13:09.183977 ==
6703 11:13:09.187368 DQS Delay:
6704 11:13:09.187453 DQS0 = 35, DQS1 = 51
6705 11:13:09.190235 DQM Delay:
6706 11:13:09.190316 DQM0 = 6, DQM1 = 14
6707 11:13:09.190381 DQ Delay:
6708 11:13:09.193796 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6709 11:13:09.197007 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6710 11:13:09.200442 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6711 11:13:09.203569 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =16
6712 11:13:09.203649
6713 11:13:09.203713
6714 11:13:09.203773 ==
6715 11:13:09.206692 Dram Type= 6, Freq= 0, CH_1, rank 0
6716 11:13:09.213088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6717 11:13:09.213170 ==
6718 11:13:09.213234
6719 11:13:09.213294
6720 11:13:09.213352 TX Vref Scan disable
6721 11:13:09.216753 == TX Byte 0 ==
6722 11:13:09.219840 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6723 11:13:09.223136 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6724 11:13:09.226684 == TX Byte 1 ==
6725 11:13:09.229412 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6726 11:13:09.232994 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6727 11:13:09.236019 ==
6728 11:13:09.239623 Dram Type= 6, Freq= 0, CH_1, rank 0
6729 11:13:09.242961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6730 11:13:09.243037 ==
6731 11:13:09.243101
6732 11:13:09.243162
6733 11:13:09.246413 TX Vref Scan disable
6734 11:13:09.246486 == TX Byte 0 ==
6735 11:13:09.249333 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6736 11:13:09.256023 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6737 11:13:09.256121 == TX Byte 1 ==
6738 11:13:09.259551 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6739 11:13:09.265848 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6740 11:13:09.265947
6741 11:13:09.266032 [DATLAT]
6742 11:13:09.266115 Freq=400, CH1 RK0
6743 11:13:09.266203
6744 11:13:09.269397 DATLAT Default: 0xf
6745 11:13:09.269482 0, 0xFFFF, sum = 0
6746 11:13:09.272635 1, 0xFFFF, sum = 0
6747 11:13:09.276099 2, 0xFFFF, sum = 0
6748 11:13:09.276210 3, 0xFFFF, sum = 0
6749 11:13:09.278900 4, 0xFFFF, sum = 0
6750 11:13:09.278986 5, 0xFFFF, sum = 0
6751 11:13:09.282390 6, 0xFFFF, sum = 0
6752 11:13:09.282475 7, 0xFFFF, sum = 0
6753 11:13:09.285476 8, 0xFFFF, sum = 0
6754 11:13:09.285562 9, 0xFFFF, sum = 0
6755 11:13:09.289103 10, 0xFFFF, sum = 0
6756 11:13:09.289189 11, 0xFFFF, sum = 0
6757 11:13:09.292521 12, 0xFFFF, sum = 0
6758 11:13:09.292606 13, 0x0, sum = 1
6759 11:13:09.295499 14, 0x0, sum = 2
6760 11:13:09.295612 15, 0x0, sum = 3
6761 11:13:09.298878 16, 0x0, sum = 4
6762 11:13:09.298962 best_step = 14
6763 11:13:09.299027
6764 11:13:09.299086 ==
6765 11:13:09.302260 Dram Type= 6, Freq= 0, CH_1, rank 0
6766 11:13:09.308720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6767 11:13:09.308802 ==
6768 11:13:09.308867 RX Vref Scan: 1
6769 11:13:09.308927
6770 11:13:09.311810 RX Vref 0 -> 0, step: 1
6771 11:13:09.311918
6772 11:13:09.314952 RX Delay -343 -> 252, step: 8
6773 11:13:09.315060
6774 11:13:09.318212 Set Vref, RX VrefLevel [Byte0]: 52
6775 11:13:09.321805 [Byte1]: 52
6776 11:13:09.321892
6777 11:13:09.324990 Final RX Vref Byte 0 = 52 to rank0
6778 11:13:09.328299 Final RX Vref Byte 1 = 52 to rank0
6779 11:13:09.331487 Final RX Vref Byte 0 = 52 to rank1
6780 11:13:09.334659 Final RX Vref Byte 1 = 52 to rank1==
6781 11:13:09.338311 Dram Type= 6, Freq= 0, CH_1, rank 0
6782 11:13:09.344752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6783 11:13:09.344830 ==
6784 11:13:09.344895 DQS Delay:
6785 11:13:09.348176 DQS0 = 44, DQS1 = 52
6786 11:13:09.348258 DQM Delay:
6787 11:13:09.348324 DQM0 = 10, DQM1 = 10
6788 11:13:09.351556 DQ Delay:
6789 11:13:09.354633 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =12
6790 11:13:09.354716 DQ4 =4, DQ5 =20, DQ6 =24, DQ7 =4
6791 11:13:09.358100 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6792 11:13:09.361356 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =16
6793 11:13:09.361438
6794 11:13:09.364208
6795 11:13:09.371040 [DQSOSCAuto] RK0, (LSB)MR18= 0x648b, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 397 ps
6796 11:13:09.374508 CH1 RK0: MR19=C0C, MR18=648B
6797 11:13:09.380641 CH1_RK0: MR19=0xC0C, MR18=0x648B, DQSOSC=392, MR23=63, INC=384, DEC=256
6798 11:13:09.380743 ==
6799 11:13:09.383892 Dram Type= 6, Freq= 0, CH_1, rank 1
6800 11:13:09.387419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6801 11:13:09.387501 ==
6802 11:13:09.390541 [Gating] SW mode calibration
6803 11:13:09.397546 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6804 11:13:09.403732 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6805 11:13:09.406949 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6806 11:13:09.410351 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6807 11:13:09.416732 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6808 11:13:09.420311 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6809 11:13:09.423522 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6810 11:13:09.429808 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6811 11:13:09.433083 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6812 11:13:09.436293 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6813 11:13:09.442993 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6814 11:13:09.446370 Total UI for P1: 0, mck2ui 16
6815 11:13:09.449461 best dqsien dly found for B0: ( 0, 14, 24)
6816 11:13:09.452881 Total UI for P1: 0, mck2ui 16
6817 11:13:09.456267 best dqsien dly found for B1: ( 0, 14, 24)
6818 11:13:09.459602 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6819 11:13:09.462623 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6820 11:13:09.462722
6821 11:13:09.466223 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6822 11:13:09.469127 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6823 11:13:09.472516 [Gating] SW calibration Done
6824 11:13:09.472610 ==
6825 11:13:09.475938 Dram Type= 6, Freq= 0, CH_1, rank 1
6826 11:13:09.479014 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6827 11:13:09.482273 ==
6828 11:13:09.482348 RX Vref Scan: 0
6829 11:13:09.482415
6830 11:13:09.485600 RX Vref 0 -> 0, step: 1
6831 11:13:09.485670
6832 11:13:09.488953 RX Delay -410 -> 252, step: 16
6833 11:13:09.492490 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6834 11:13:09.495496 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6835 11:13:09.498540 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6836 11:13:09.505430 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6837 11:13:09.508762 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6838 11:13:09.511747 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6839 11:13:09.518164 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6840 11:13:09.521382 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6841 11:13:09.524654 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6842 11:13:09.528234 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6843 11:13:09.534768 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6844 11:13:09.538259 iDelay=230, Bit 11, Center -35 (-282 ~ 213) 496
6845 11:13:09.541607 iDelay=230, Bit 12, Center -19 (-266 ~ 229) 496
6846 11:13:09.544646 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6847 11:13:09.551168 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6848 11:13:09.554513 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6849 11:13:09.554624 ==
6850 11:13:09.557885 Dram Type= 6, Freq= 0, CH_1, rank 1
6851 11:13:09.560950 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6852 11:13:09.561027 ==
6853 11:13:09.564221 DQS Delay:
6854 11:13:09.564292 DQS0 = 43, DQS1 = 51
6855 11:13:09.567660 DQM Delay:
6856 11:13:09.567736 DQM0 = 9, DQM1 = 16
6857 11:13:09.571008 DQ Delay:
6858 11:13:09.571077 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6859 11:13:09.574446 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6860 11:13:09.577336 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6861 11:13:09.580717 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =24
6862 11:13:09.580806
6863 11:13:09.580871
6864 11:13:09.580930 ==
6865 11:13:09.584050 Dram Type= 6, Freq= 0, CH_1, rank 1
6866 11:13:09.590352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6867 11:13:09.590460 ==
6868 11:13:09.590557
6869 11:13:09.590646
6870 11:13:09.593893 TX Vref Scan disable
6871 11:13:09.593965 == TX Byte 0 ==
6872 11:13:09.597212 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6873 11:13:09.603442 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6874 11:13:09.603521 == TX Byte 1 ==
6875 11:13:09.606881 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6876 11:13:09.610255 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6877 11:13:09.613692 ==
6878 11:13:09.617073 Dram Type= 6, Freq= 0, CH_1, rank 1
6879 11:13:09.619863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6880 11:13:09.619960 ==
6881 11:13:09.620061
6882 11:13:09.620122
6883 11:13:09.623637 TX Vref Scan disable
6884 11:13:09.623713 == TX Byte 0 ==
6885 11:13:09.626387 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6886 11:13:09.632925 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6887 11:13:09.633024 == TX Byte 1 ==
6888 11:13:09.636939 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6889 11:13:09.643073 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6890 11:13:09.643160
6891 11:13:09.643225 [DATLAT]
6892 11:13:09.643286 Freq=400, CH1 RK1
6893 11:13:09.643352
6894 11:13:09.646214 DATLAT Default: 0xe
6895 11:13:09.649927 0, 0xFFFF, sum = 0
6896 11:13:09.650013 1, 0xFFFF, sum = 0
6897 11:13:09.653458 2, 0xFFFF, sum = 0
6898 11:13:09.653535 3, 0xFFFF, sum = 0
6899 11:13:09.656428 4, 0xFFFF, sum = 0
6900 11:13:09.656512 5, 0xFFFF, sum = 0
6901 11:13:09.659840 6, 0xFFFF, sum = 0
6902 11:13:09.659944 7, 0xFFFF, sum = 0
6903 11:13:09.663032 8, 0xFFFF, sum = 0
6904 11:13:09.663142 9, 0xFFFF, sum = 0
6905 11:13:09.666387 10, 0xFFFF, sum = 0
6906 11:13:09.666469 11, 0xFFFF, sum = 0
6907 11:13:09.669379 12, 0xFFFF, sum = 0
6908 11:13:09.669454 13, 0x0, sum = 1
6909 11:13:09.672590 14, 0x0, sum = 2
6910 11:13:09.672660 15, 0x0, sum = 3
6911 11:13:09.676118 16, 0x0, sum = 4
6912 11:13:09.676220 best_step = 14
6913 11:13:09.676319
6914 11:13:09.676407 ==
6915 11:13:09.679037 Dram Type= 6, Freq= 0, CH_1, rank 1
6916 11:13:09.685768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6917 11:13:09.685844 ==
6918 11:13:09.685914 RX Vref Scan: 0
6919 11:13:09.685973
6920 11:13:09.689238 RX Vref 0 -> 0, step: 1
6921 11:13:09.689314
6922 11:13:09.692507 RX Delay -343 -> 252, step: 8
6923 11:13:09.698722 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6924 11:13:09.701979 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6925 11:13:09.705409 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6926 11:13:09.711753 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6927 11:13:09.715269 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6928 11:13:09.718766 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6929 11:13:09.721644 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6930 11:13:09.728342 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6931 11:13:09.731547 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6932 11:13:09.735012 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6933 11:13:09.738105 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6934 11:13:09.745086 iDelay=217, Bit 11, Center -48 (-287 ~ 192) 480
6935 11:13:09.748240 iDelay=217, Bit 12, Center -36 (-279 ~ 208) 488
6936 11:13:09.751322 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6937 11:13:09.758200 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6938 11:13:09.761018 iDelay=217, Bit 15, Center -32 (-279 ~ 216) 496
6939 11:13:09.761094 ==
6940 11:13:09.764630 Dram Type= 6, Freq= 0, CH_1, rank 1
6941 11:13:09.767549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6942 11:13:09.767619 ==
6943 11:13:09.771002 DQS Delay:
6944 11:13:09.771078 DQS0 = 48, DQS1 = 52
6945 11:13:09.771149 DQM Delay:
6946 11:13:09.774463 DQM0 = 11, DQM1 = 10
6947 11:13:09.774539 DQ Delay:
6948 11:13:09.777331 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =8
6949 11:13:09.780650 DQ4 =12, DQ5 =20, DQ6 =20, DQ7 =8
6950 11:13:09.784037 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6951 11:13:09.787503 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =20
6952 11:13:09.787576
6953 11:13:09.787635
6954 11:13:09.797630 [DQSOSCAuto] RK1, (LSB)MR18= 0x6ca4, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
6955 11:13:09.797714 CH1 RK1: MR19=C0C, MR18=6CA4
6956 11:13:09.803983 CH1_RK1: MR19=0xC0C, MR18=0x6CA4, DQSOSC=389, MR23=63, INC=390, DEC=260
6957 11:13:09.807305 [RxdqsGatingPostProcess] freq 400
6958 11:13:09.813783 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6959 11:13:09.816830 best DQS0 dly(2T, 0.5T) = (0, 10)
6960 11:13:09.820399 best DQS1 dly(2T, 0.5T) = (0, 10)
6961 11:13:09.823466 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6962 11:13:09.826957 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6963 11:13:09.830188 best DQS0 dly(2T, 0.5T) = (0, 10)
6964 11:13:09.833365 best DQS1 dly(2T, 0.5T) = (0, 10)
6965 11:13:09.836794 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6966 11:13:09.840090 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6967 11:13:09.843428 Pre-setting of DQS Precalculation
6968 11:13:09.846255 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6969 11:13:09.852935 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6970 11:13:09.862945 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6971 11:13:09.863051
6972 11:13:09.863144
6973 11:13:09.863233 [Calibration Summary] 800 Mbps
6974 11:13:09.865968 CH 0, Rank 0
6975 11:13:09.866075 SW Impedance : PASS
6976 11:13:09.869401 DUTY Scan : NO K
6977 11:13:09.872661 ZQ Calibration : PASS
6978 11:13:09.872744 Jitter Meter : NO K
6979 11:13:09.875910 CBT Training : PASS
6980 11:13:09.879241 Write leveling : PASS
6981 11:13:09.879329 RX DQS gating : PASS
6982 11:13:09.882895 RX DQ/DQS(RDDQC) : PASS
6983 11:13:09.886221 TX DQ/DQS : PASS
6984 11:13:09.886388 RX DATLAT : PASS
6985 11:13:09.889534 RX DQ/DQS(Engine): PASS
6986 11:13:09.892991 TX OE : NO K
6987 11:13:09.893166 All Pass.
6988 11:13:09.893255
6989 11:13:09.893336 CH 0, Rank 1
6990 11:13:09.895993 SW Impedance : PASS
6991 11:13:09.899417 DUTY Scan : NO K
6992 11:13:09.899611 ZQ Calibration : PASS
6993 11:13:09.902475 Jitter Meter : NO K
6994 11:13:09.905917 CBT Training : PASS
6995 11:13:09.906018 Write leveling : NO K
6996 11:13:09.908844 RX DQS gating : PASS
6997 11:13:09.912112 RX DQ/DQS(RDDQC) : PASS
6998 11:13:09.912202 TX DQ/DQS : PASS
6999 11:13:09.915478 RX DATLAT : PASS
7000 11:13:09.918928 RX DQ/DQS(Engine): PASS
7001 11:13:09.919018 TX OE : NO K
7002 11:13:09.922429 All Pass.
7003 11:13:09.922612
7004 11:13:09.922708 CH 1, Rank 0
7005 11:13:09.926053 SW Impedance : PASS
7006 11:13:09.926248 DUTY Scan : NO K
7007 11:13:09.928528 ZQ Calibration : PASS
7008 11:13:09.931928 Jitter Meter : NO K
7009 11:13:09.932128 CBT Training : PASS
7010 11:13:09.935329 Write leveling : PASS
7011 11:13:09.938748 RX DQS gating : PASS
7012 11:13:09.938912 RX DQ/DQS(RDDQC) : PASS
7013 11:13:09.942362 TX DQ/DQS : PASS
7014 11:13:09.942661 RX DATLAT : PASS
7015 11:13:09.945395 RX DQ/DQS(Engine): PASS
7016 11:13:09.948584 TX OE : NO K
7017 11:13:09.948821 All Pass.
7018 11:13:09.949019
7019 11:13:09.951803 CH 1, Rank 1
7020 11:13:09.952080 SW Impedance : PASS
7021 11:13:09.955067 DUTY Scan : NO K
7022 11:13:09.955342 ZQ Calibration : PASS
7023 11:13:09.958761 Jitter Meter : NO K
7024 11:13:09.962015 CBT Training : PASS
7025 11:13:09.962409 Write leveling : NO K
7026 11:13:09.965245 RX DQS gating : PASS
7027 11:13:09.968509 RX DQ/DQS(RDDQC) : PASS
7028 11:13:09.968958 TX DQ/DQS : PASS
7029 11:13:09.971999 RX DATLAT : PASS
7030 11:13:09.975248 RX DQ/DQS(Engine): PASS
7031 11:13:09.975857 TX OE : NO K
7032 11:13:09.978511 All Pass.
7033 11:13:09.979114
7034 11:13:09.979631 DramC Write-DBI off
7035 11:13:09.981956 PER_BANK_REFRESH: Hybrid Mode
7036 11:13:09.985068 TX_TRACKING: ON
7037 11:13:09.991844 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7038 11:13:09.994635 [FAST_K] Save calibration result to emmc
7039 11:13:09.997983 dramc_set_vcore_voltage set vcore to 725000
7040 11:13:10.001805 Read voltage for 1600, 0
7041 11:13:10.002350 Vio18 = 0
7042 11:13:10.004965 Vcore = 725000
7043 11:13:10.005468 Vdram = 0
7044 11:13:10.005834 Vddq = 0
7045 11:13:10.007892 Vmddr = 0
7046 11:13:10.011084 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7047 11:13:10.018019 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7048 11:13:10.021106 MEM_TYPE=3, freq_sel=13
7049 11:13:10.021588 sv_algorithm_assistance_LP4_3733
7050 11:13:10.027777 ============ PULL DRAM RESETB DOWN ============
7051 11:13:10.031189 ========== PULL DRAM RESETB DOWN end =========
7052 11:13:10.034122 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7053 11:13:10.037737 ===================================
7054 11:13:10.040805 LPDDR4 DRAM CONFIGURATION
7055 11:13:10.044353 ===================================
7056 11:13:10.047630 EX_ROW_EN[0] = 0x0
7057 11:13:10.048106 EX_ROW_EN[1] = 0x0
7058 11:13:10.051141 LP4Y_EN = 0x0
7059 11:13:10.051693 WORK_FSP = 0x1
7060 11:13:10.054273 WL = 0x5
7061 11:13:10.054802 RL = 0x5
7062 11:13:10.057295 BL = 0x2
7063 11:13:10.057718 RPST = 0x0
7064 11:13:10.060632 RD_PRE = 0x0
7065 11:13:10.064002 WR_PRE = 0x1
7066 11:13:10.064601 WR_PST = 0x1
7067 11:13:10.067007 DBI_WR = 0x0
7068 11:13:10.067481 DBI_RD = 0x0
7069 11:13:10.070712 OTF = 0x1
7070 11:13:10.073809 ===================================
7071 11:13:10.076853 ===================================
7072 11:13:10.077280 ANA top config
7073 11:13:10.079971 ===================================
7074 11:13:10.083505 DLL_ASYNC_EN = 0
7075 11:13:10.086732 ALL_SLAVE_EN = 0
7076 11:13:10.087257 NEW_RANK_MODE = 1
7077 11:13:10.090292 DLL_IDLE_MODE = 1
7078 11:13:10.093203 LP45_APHY_COMB_EN = 1
7079 11:13:10.096528 TX_ODT_DIS = 0
7080 11:13:10.099841 NEW_8X_MODE = 1
7081 11:13:10.103234 ===================================
7082 11:13:10.106632 ===================================
7083 11:13:10.107089 data_rate = 3200
7084 11:13:10.110190 CKR = 1
7085 11:13:10.113186 DQ_P2S_RATIO = 8
7086 11:13:10.116576 ===================================
7087 11:13:10.119752 CA_P2S_RATIO = 8
7088 11:13:10.123024 DQ_CA_OPEN = 0
7089 11:13:10.126444 DQ_SEMI_OPEN = 0
7090 11:13:10.126861 CA_SEMI_OPEN = 0
7091 11:13:10.129313 CA_FULL_RATE = 0
7092 11:13:10.132545 DQ_CKDIV4_EN = 0
7093 11:13:10.136125 CA_CKDIV4_EN = 0
7094 11:13:10.139502 CA_PREDIV_EN = 0
7095 11:13:10.142964 PH8_DLY = 12
7096 11:13:10.146218 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7097 11:13:10.146637 DQ_AAMCK_DIV = 4
7098 11:13:10.149062 CA_AAMCK_DIV = 4
7099 11:13:10.152474 CA_ADMCK_DIV = 4
7100 11:13:10.155807 DQ_TRACK_CA_EN = 0
7101 11:13:10.159028 CA_PICK = 1600
7102 11:13:10.162187 CA_MCKIO = 1600
7103 11:13:10.165605 MCKIO_SEMI = 0
7104 11:13:10.166020 PLL_FREQ = 3068
7105 11:13:10.168949 DQ_UI_PI_RATIO = 32
7106 11:13:10.172211 CA_UI_PI_RATIO = 0
7107 11:13:10.175737 ===================================
7108 11:13:10.178995 ===================================
7109 11:13:10.182050 memory_type:LPDDR4
7110 11:13:10.185261 GP_NUM : 10
7111 11:13:10.185677 SRAM_EN : 1
7112 11:13:10.188344 MD32_EN : 0
7113 11:13:10.192320 ===================================
7114 11:13:10.195449 [ANA_INIT] >>>>>>>>>>>>>>
7115 11:13:10.195866 <<<<<< [CONFIGURE PHASE]: ANA_TX
7116 11:13:10.198710 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7117 11:13:10.202007 ===================================
7118 11:13:10.204837 data_rate = 3200,PCW = 0X7600
7119 11:13:10.208186 ===================================
7120 11:13:10.211694 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7121 11:13:10.218004 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7122 11:13:10.224537 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7123 11:13:10.228073 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7124 11:13:10.231366 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7125 11:13:10.234634 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7126 11:13:10.237852 [ANA_INIT] flow start
7127 11:13:10.237934 [ANA_INIT] PLL >>>>>>>>
7128 11:13:10.241494 [ANA_INIT] PLL <<<<<<<<
7129 11:13:10.244166 [ANA_INIT] MIDPI >>>>>>>>
7130 11:13:10.247829 [ANA_INIT] MIDPI <<<<<<<<
7131 11:13:10.248255 [ANA_INIT] DLL >>>>>>>>
7132 11:13:10.251218 [ANA_INIT] DLL <<<<<<<<
7133 11:13:10.254749 [ANA_INIT] flow end
7134 11:13:10.257441 ============ LP4 DIFF to SE enter ============
7135 11:13:10.260939 ============ LP4 DIFF to SE exit ============
7136 11:13:10.264332 [ANA_INIT] <<<<<<<<<<<<<
7137 11:13:10.267670 [Flow] Enable top DCM control >>>>>
7138 11:13:10.270730 [Flow] Enable top DCM control <<<<<
7139 11:13:10.273971 Enable DLL master slave shuffle
7140 11:13:10.277271 ==============================================================
7141 11:13:10.280481 Gating Mode config
7142 11:13:10.287583 ==============================================================
7143 11:13:10.288190 Config description:
7144 11:13:10.296872 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7145 11:13:10.303631 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7146 11:13:10.310152 SELPH_MODE 0: By rank 1: By Phase
7147 11:13:10.313553 ==============================================================
7148 11:13:10.316945 GAT_TRACK_EN = 1
7149 11:13:10.320469 RX_GATING_MODE = 2
7150 11:13:10.323144 RX_GATING_TRACK_MODE = 2
7151 11:13:10.326785 SELPH_MODE = 1
7152 11:13:10.330017 PICG_EARLY_EN = 1
7153 11:13:10.333394 VALID_LAT_VALUE = 1
7154 11:13:10.336250 ==============================================================
7155 11:13:10.339718 Enter into Gating configuration >>>>
7156 11:13:10.342956 Exit from Gating configuration <<<<
7157 11:13:10.346317 Enter into DVFS_PRE_config >>>>>
7158 11:13:10.359414 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7159 11:13:10.362912 Exit from DVFS_PRE_config <<<<<
7160 11:13:10.366325 Enter into PICG configuration >>>>
7161 11:13:10.369589 Exit from PICG configuration <<<<
7162 11:13:10.369970 [RX_INPUT] configuration >>>>>
7163 11:13:10.372981 [RX_INPUT] configuration <<<<<
7164 11:13:10.379269 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7165 11:13:10.382871 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7166 11:13:10.389314 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7167 11:13:10.395628 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7168 11:13:10.402012 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7169 11:13:10.409005 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7170 11:13:10.412084 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7171 11:13:10.415562 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7172 11:13:10.421626 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7173 11:13:10.425141 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7174 11:13:10.428474 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7175 11:13:10.434998 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7176 11:13:10.438288 ===================================
7177 11:13:10.438676 LPDDR4 DRAM CONFIGURATION
7178 11:13:10.441786 ===================================
7179 11:13:10.445215 EX_ROW_EN[0] = 0x0
7180 11:13:10.447996 EX_ROW_EN[1] = 0x0
7181 11:13:10.448420 LP4Y_EN = 0x0
7182 11:13:10.451538 WORK_FSP = 0x1
7183 11:13:10.451924 WL = 0x5
7184 11:13:10.454945 RL = 0x5
7185 11:13:10.455330 BL = 0x2
7186 11:13:10.457768 RPST = 0x0
7187 11:13:10.458151 RD_PRE = 0x0
7188 11:13:10.461170 WR_PRE = 0x1
7189 11:13:10.461553 WR_PST = 0x1
7190 11:13:10.464454 DBI_WR = 0x0
7191 11:13:10.464840 DBI_RD = 0x0
7192 11:13:10.467653 OTF = 0x1
7193 11:13:10.470929 ===================================
7194 11:13:10.474332 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7195 11:13:10.477650 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7196 11:13:10.484231 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7197 11:13:10.487643 ===================================
7198 11:13:10.487724 LPDDR4 DRAM CONFIGURATION
7199 11:13:10.490894 ===================================
7200 11:13:10.494207 EX_ROW_EN[0] = 0x10
7201 11:13:10.497430 EX_ROW_EN[1] = 0x0
7202 11:13:10.497511 LP4Y_EN = 0x0
7203 11:13:10.500499 WORK_FSP = 0x1
7204 11:13:10.500580 WL = 0x5
7205 11:13:10.503970 RL = 0x5
7206 11:13:10.504092 BL = 0x2
7207 11:13:10.507342 RPST = 0x0
7208 11:13:10.507440 RD_PRE = 0x0
7209 11:13:10.510951 WR_PRE = 0x1
7210 11:13:10.511047 WR_PST = 0x1
7211 11:13:10.513877 DBI_WR = 0x0
7212 11:13:10.513972 DBI_RD = 0x0
7213 11:13:10.516949 OTF = 0x1
7214 11:13:10.520513 ===================================
7215 11:13:10.527183 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7216 11:13:10.527308 ==
7217 11:13:10.530700 Dram Type= 6, Freq= 0, CH_0, rank 0
7218 11:13:10.533478 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7219 11:13:10.533619 ==
7220 11:13:10.536851 [Duty_Offset_Calibration]
7221 11:13:10.537009 B0:2 B1:0 CA:4
7222 11:13:10.537133
7223 11:13:10.540014 [DutyScan_Calibration_Flow] k_type=0
7224 11:13:10.550345
7225 11:13:10.550603 ==CLK 0==
7226 11:13:10.553802 Final CLK duty delay cell = -4
7227 11:13:10.557182 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7228 11:13:10.560702 [-4] MIN Duty = 4844%(X100), DQS PI = 6
7229 11:13:10.563587 [-4] AVG Duty = 4937%(X100)
7230 11:13:10.564007
7231 11:13:10.566880 CH0 CLK Duty spec in!! Max-Min= 187%
7232 11:13:10.570422 [DutyScan_Calibration_Flow] ====Done====
7233 11:13:10.570840
7234 11:13:10.573215 [DutyScan_Calibration_Flow] k_type=1
7235 11:13:10.590782
7236 11:13:10.591199 ==DQS 0 ==
7237 11:13:10.593891 Final DQS duty delay cell = 0
7238 11:13:10.597558 [0] MAX Duty = 5218%(X100), DQS PI = 22
7239 11:13:10.600712 [0] MIN Duty = 5093%(X100), DQS PI = 14
7240 11:13:10.603998 [0] AVG Duty = 5155%(X100)
7241 11:13:10.604446
7242 11:13:10.604779 ==DQS 1 ==
7243 11:13:10.607080 Final DQS duty delay cell = 0
7244 11:13:10.610770 [0] MAX Duty = 5187%(X100), DQS PI = 2
7245 11:13:10.614097 [0] MIN Duty = 4969%(X100), DQS PI = 10
7246 11:13:10.617191 [0] AVG Duty = 5078%(X100)
7247 11:13:10.617610
7248 11:13:10.620225 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7249 11:13:10.620647
7250 11:13:10.623654 CH0 DQS 1 Duty spec in!! Max-Min= 218%
7251 11:13:10.626968 [DutyScan_Calibration_Flow] ====Done====
7252 11:13:10.627385
7253 11:13:10.630122 [DutyScan_Calibration_Flow] k_type=3
7254 11:13:10.647908
7255 11:13:10.648465 ==DQM 0 ==
7256 11:13:10.651332 Final DQM duty delay cell = 0
7257 11:13:10.654741 [0] MAX Duty = 5156%(X100), DQS PI = 22
7258 11:13:10.657887 [0] MIN Duty = 4875%(X100), DQS PI = 54
7259 11:13:10.661193 [0] AVG Duty = 5015%(X100)
7260 11:13:10.661776
7261 11:13:10.662279 ==DQM 1 ==
7262 11:13:10.664396 Final DQM duty delay cell = 0
7263 11:13:10.667429 [0] MAX Duty = 4969%(X100), DQS PI = 0
7264 11:13:10.670839 [0] MIN Duty = 4844%(X100), DQS PI = 10
7265 11:13:10.674503 [0] AVG Duty = 4906%(X100)
7266 11:13:10.675102
7267 11:13:10.677018 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7268 11:13:10.677099
7269 11:13:10.680708 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7270 11:13:10.684245 [DutyScan_Calibration_Flow] ====Done====
7271 11:13:10.684664
7272 11:13:10.687485 [DutyScan_Calibration_Flow] k_type=2
7273 11:13:10.704924
7274 11:13:10.705417 ==DQ 0 ==
7275 11:13:10.708801 Final DQ duty delay cell = 0
7276 11:13:10.711923 [0] MAX Duty = 5156%(X100), DQS PI = 22
7277 11:13:10.714965 [0] MIN Duty = 4938%(X100), DQS PI = 12
7278 11:13:10.715388 [0] AVG Duty = 5047%(X100)
7279 11:13:10.718663
7280 11:13:10.719100 ==DQ 1 ==
7281 11:13:10.721937 Final DQ duty delay cell = 0
7282 11:13:10.725220 [0] MAX Duty = 5218%(X100), DQS PI = 2
7283 11:13:10.728240 [0] MIN Duty = 4938%(X100), DQS PI = 12
7284 11:13:10.728658 [0] AVG Duty = 5078%(X100)
7285 11:13:10.731583
7286 11:13:10.734950 CH0 DQ 0 Duty spec in!! Max-Min= 218%
7287 11:13:10.735506
7288 11:13:10.738242 CH0 DQ 1 Duty spec in!! Max-Min= 280%
7289 11:13:10.741546 [DutyScan_Calibration_Flow] ====Done====
7290 11:13:10.741966 ==
7291 11:13:10.744951 Dram Type= 6, Freq= 0, CH_1, rank 0
7292 11:13:10.748094 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7293 11:13:10.748518 ==
7294 11:13:10.751374 [Duty_Offset_Calibration]
7295 11:13:10.751793 B0:0 B1:-1 CA:3
7296 11:13:10.752162
7297 11:13:10.754272 [DutyScan_Calibration_Flow] k_type=0
7298 11:13:10.764424
7299 11:13:10.764839 ==CLK 0==
7300 11:13:10.768152 Final CLK duty delay cell = -4
7301 11:13:10.770905 [-4] MAX Duty = 5062%(X100), DQS PI = 34
7302 11:13:10.774235 [-4] MIN Duty = 4813%(X100), DQS PI = 4
7303 11:13:10.777941 [-4] AVG Duty = 4937%(X100)
7304 11:13:10.778447
7305 11:13:10.781206 CH1 CLK Duty spec in!! Max-Min= 249%
7306 11:13:10.783846 [DutyScan_Calibration_Flow] ====Done====
7307 11:13:10.783927
7308 11:13:10.787188 [DutyScan_Calibration_Flow] k_type=1
7309 11:13:10.803654
7310 11:13:10.803735 ==DQS 0 ==
7311 11:13:10.807039 Final DQS duty delay cell = 0
7312 11:13:10.809676 [0] MAX Duty = 5187%(X100), DQS PI = 60
7313 11:13:10.813111 [0] MIN Duty = 4938%(X100), DQS PI = 8
7314 11:13:10.816668 [0] AVG Duty = 5062%(X100)
7315 11:13:10.816736
7316 11:13:10.816793 ==DQS 1 ==
7317 11:13:10.820172 Final DQS duty delay cell = -4
7318 11:13:10.823418 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7319 11:13:10.826543 [-4] MIN Duty = 4813%(X100), DQS PI = 50
7320 11:13:10.829804 [-4] AVG Duty = 4922%(X100)
7321 11:13:10.830155
7322 11:13:10.833628 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7323 11:13:10.834160
7324 11:13:10.836928 CH1 DQS 1 Duty spec in!! Max-Min= 218%
7325 11:13:10.840263 [DutyScan_Calibration_Flow] ====Done====
7326 11:13:10.840719
7327 11:13:10.842872 [DutyScan_Calibration_Flow] k_type=3
7328 11:13:10.861164
7329 11:13:10.861759 ==DQM 0 ==
7330 11:13:10.864398 Final DQM duty delay cell = 0
7331 11:13:10.867294 [0] MAX Duty = 5031%(X100), DQS PI = 38
7332 11:13:10.870648 [0] MIN Duty = 4750%(X100), DQS PI = 8
7333 11:13:10.873934 [0] AVG Duty = 4890%(X100)
7334 11:13:10.874471
7335 11:13:10.874936 ==DQM 1 ==
7336 11:13:10.877471 Final DQM duty delay cell = 0
7337 11:13:10.880799 [0] MAX Duty = 5000%(X100), DQS PI = 14
7338 11:13:10.883808 [0] MIN Duty = 4813%(X100), DQS PI = 30
7339 11:13:10.887218 [0] AVG Duty = 4906%(X100)
7340 11:13:10.887794
7341 11:13:10.890681 CH1 DQM 0 Duty spec in!! Max-Min= 281%
7342 11:13:10.891254
7343 11:13:10.893660 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7344 11:13:10.897032 [DutyScan_Calibration_Flow] ====Done====
7345 11:13:10.897567
7346 11:13:10.900138 [DutyScan_Calibration_Flow] k_type=2
7347 11:13:10.918064
7348 11:13:10.918653 ==DQ 0 ==
7349 11:13:10.921391 Final DQ duty delay cell = 0
7350 11:13:10.924487 [0] MAX Duty = 5187%(X100), DQS PI = 0
7351 11:13:10.927805 [0] MIN Duty = 5000%(X100), DQS PI = 6
7352 11:13:10.928358 [0] AVG Duty = 5093%(X100)
7353 11:13:10.928856
7354 11:13:10.930998 ==DQ 1 ==
7355 11:13:10.934104 Final DQ duty delay cell = 0
7356 11:13:10.937266 [0] MAX Duty = 5031%(X100), DQS PI = 0
7357 11:13:10.940486 [0] MIN Duty = 4875%(X100), DQS PI = 26
7358 11:13:10.940893 [0] AVG Duty = 4953%(X100)
7359 11:13:10.941238
7360 11:13:10.944282 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7361 11:13:10.947536
7362 11:13:10.951056 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7363 11:13:10.953993 [DutyScan_Calibration_Flow] ====Done====
7364 11:13:10.957277 nWR fixed to 30
7365 11:13:10.957756 [ModeRegInit_LP4] CH0 RK0
7366 11:13:10.960555 [ModeRegInit_LP4] CH0 RK1
7367 11:13:10.964078 [ModeRegInit_LP4] CH1 RK0
7368 11:13:10.967401 [ModeRegInit_LP4] CH1 RK1
7369 11:13:10.967908 match AC timing 5
7370 11:13:10.970843 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7371 11:13:10.976944 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7372 11:13:10.980534 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7373 11:13:10.987219 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7374 11:13:10.990138 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7375 11:13:10.990684 [MiockJmeterHQA]
7376 11:13:10.991195
7377 11:13:10.993466 [DramcMiockJmeter] u1RxGatingPI = 0
7378 11:13:10.996841 0 : 4363, 4137
7379 11:13:10.997422 4 : 4252, 4027
7380 11:13:11.000271 8 : 4253, 4026
7381 11:13:11.000789 12 : 4255, 4030
7382 11:13:11.001242 16 : 4253, 4026
7383 11:13:11.003483 20 : 4253, 4027
7384 11:13:11.004094 24 : 4253, 4026
7385 11:13:11.006477 28 : 4365, 4140
7386 11:13:11.007036 32 : 4258, 4029
7387 11:13:11.010070 36 : 4255, 4029
7388 11:13:11.010641 40 : 4252, 4027
7389 11:13:11.013393 44 : 4253, 4029
7390 11:13:11.013847 48 : 4255, 4029
7391 11:13:11.014347 52 : 4363, 4137
7392 11:13:11.016864 56 : 4363, 4137
7393 11:13:11.017413 60 : 4250, 4027
7394 11:13:11.019692 64 : 4250, 4026
7395 11:13:11.020351 68 : 4250, 4027
7396 11:13:11.022987 72 : 4249, 4027
7397 11:13:11.023555 76 : 4250, 4026
7398 11:13:11.026332 80 : 4250, 4027
7399 11:13:11.026877 84 : 4250, 4026
7400 11:13:11.027395 88 : 4250, 4027
7401 11:13:11.029599 92 : 4250, 4027
7402 11:13:11.030143 96 : 4253, 3583
7403 11:13:11.032961 100 : 4250, 0
7404 11:13:11.033371 104 : 4250, 0
7405 11:13:11.036473 108 : 4253, 0
7406 11:13:11.036890 112 : 4250, 0
7407 11:13:11.037217 116 : 4250, 0
7408 11:13:11.039570 120 : 4250, 0
7409 11:13:11.040278 124 : 4250, 0
7410 11:13:11.042806 128 : 4255, 0
7411 11:13:11.043357 132 : 4254, 0
7412 11:13:11.043830 136 : 4250, 0
7413 11:13:11.046349 140 : 4361, 0
7414 11:13:11.046761 144 : 4360, 0
7415 11:13:11.047206 148 : 4249, 0
7416 11:13:11.049744 152 : 4250, 0
7417 11:13:11.050183 156 : 4250, 0
7418 11:13:11.052888 160 : 4252, 0
7419 11:13:11.053322 164 : 4250, 0
7420 11:13:11.053655 168 : 4250, 0
7421 11:13:11.056061 172 : 4250, 0
7422 11:13:11.056481 176 : 4250, 0
7423 11:13:11.059159 180 : 4250, 0
7424 11:13:11.059573 184 : 4252, 0
7425 11:13:11.060084 188 : 4250, 0
7426 11:13:11.062855 192 : 4360, 0
7427 11:13:11.063348 196 : 4360, 0
7428 11:13:11.065672 200 : 4250, 0
7429 11:13:11.066233 204 : 4250, 0
7430 11:13:11.066724 208 : 4250, 0
7431 11:13:11.069152 212 : 4252, 0
7432 11:13:11.069698 216 : 4250, 0
7433 11:13:11.072678 220 : 4250, 579
7434 11:13:11.073113 224 : 4363, 4068
7435 11:13:11.076064 228 : 4363, 4140
7436 11:13:11.076481 232 : 4250, 4027
7437 11:13:11.076822 236 : 4361, 4137
7438 11:13:11.079007 240 : 4250, 4027
7439 11:13:11.079568 244 : 4250, 4027
7440 11:13:11.082406 248 : 4250, 4026
7441 11:13:11.082967 252 : 4250, 4026
7442 11:13:11.085928 256 : 4255, 4029
7443 11:13:11.086460 260 : 4250, 4027
7444 11:13:11.089340 264 : 4252, 4029
7445 11:13:11.089905 268 : 4250, 4026
7446 11:13:11.092614 272 : 4255, 4029
7447 11:13:11.093044 276 : 4361, 4138
7448 11:13:11.095477 280 : 4250, 4027
7449 11:13:11.096132 284 : 4360, 4137
7450 11:13:11.098767 288 : 4255, 4029
7451 11:13:11.099372 292 : 4250, 4027
7452 11:13:11.102282 296 : 4250, 4027
7453 11:13:11.102886 300 : 4250, 4026
7454 11:13:11.103408 304 : 4250, 4026
7455 11:13:11.105731 308 : 4250, 4027
7456 11:13:11.106281 312 : 4249, 4027
7457 11:13:11.109104 316 : 4252, 4029
7458 11:13:11.109517 320 : 4250, 4026
7459 11:13:11.112279 324 : 4250, 4027
7460 11:13:11.112720 328 : 4360, 4138
7461 11:13:11.115751 332 : 4250, 4024
7462 11:13:11.116197 336 : 4360, 2370
7463 11:13:11.118578 340 : 4250, 43
7464 11:13:11.118989
7465 11:13:11.119330 MIOCK jitter meter ch=0
7466 11:13:11.119632
7467 11:13:11.121896 1T = (340-100) = 240 dly cells
7468 11:13:11.128703 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 271/100 ps
7469 11:13:11.129111 ==
7470 11:13:11.131926 Dram Type= 6, Freq= 0, CH_0, rank 0
7471 11:13:11.135228 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7472 11:13:11.135633 ==
7473 11:13:11.141627 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7474 11:13:11.144848 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7475 11:13:11.151592 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7476 11:13:11.154938 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7477 11:13:11.164974 [CA 0] Center 44 (14~74) winsize 61
7478 11:13:11.168823 [CA 1] Center 43 (13~74) winsize 62
7479 11:13:11.171752 [CA 2] Center 39 (10~68) winsize 59
7480 11:13:11.175431 [CA 3] Center 38 (9~68) winsize 60
7481 11:13:11.178766 [CA 4] Center 36 (7~66) winsize 60
7482 11:13:11.182161 [CA 5] Center 36 (6~66) winsize 61
7483 11:13:11.182655
7484 11:13:11.184942 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7485 11:13:11.185513
7486 11:13:11.191903 [CATrainingPosCal] consider 1 rank data
7487 11:13:11.192361 u2DelayCellTimex100 = 271/100 ps
7488 11:13:11.198218 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7489 11:13:11.201617 CA1 delay=43 (13~74),Diff = 7 PI (25 cell)
7490 11:13:11.205062 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7491 11:13:11.207798 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7492 11:13:11.211263 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7493 11:13:11.214521 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7494 11:13:11.215065
7495 11:13:11.217647 CA PerBit enable=1, Macro0, CA PI delay=36
7496 11:13:11.218063
7497 11:13:11.221092 [CBTSetCACLKResult] CA Dly = 36
7498 11:13:11.224500 CS Dly: 10 (0~41)
7499 11:13:11.227934 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7500 11:13:11.231288 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7501 11:13:11.231704 ==
7502 11:13:11.234190 Dram Type= 6, Freq= 0, CH_0, rank 1
7503 11:13:11.240582 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7504 11:13:11.241188 ==
7505 11:13:11.244351 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7506 11:13:11.250855 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7507 11:13:11.253933 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7508 11:13:11.260481 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7509 11:13:11.268526 [CA 0] Center 43 (13~74) winsize 62
7510 11:13:11.271911 [CA 1] Center 43 (13~73) winsize 61
7511 11:13:11.275239 [CA 2] Center 38 (9~68) winsize 60
7512 11:13:11.278408 [CA 3] Center 38 (9~68) winsize 60
7513 11:13:11.281849 [CA 4] Center 37 (7~67) winsize 61
7514 11:13:11.285290 [CA 5] Center 36 (6~66) winsize 61
7515 11:13:11.285708
7516 11:13:11.288633 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7517 11:13:11.289053
7518 11:13:11.295036 [CATrainingPosCal] consider 2 rank data
7519 11:13:11.295520 u2DelayCellTimex100 = 271/100 ps
7520 11:13:11.301668 CA0 delay=44 (14~74),Diff = 8 PI (28 cell)
7521 11:13:11.305016 CA1 delay=43 (13~73),Diff = 7 PI (25 cell)
7522 11:13:11.308540 CA2 delay=39 (10~68),Diff = 3 PI (10 cell)
7523 11:13:11.311820 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7524 11:13:11.315125 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7525 11:13:11.318038 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7526 11:13:11.318455
7527 11:13:11.321272 CA PerBit enable=1, Macro0, CA PI delay=36
7528 11:13:11.321692
7529 11:13:11.324510 [CBTSetCACLKResult] CA Dly = 36
7530 11:13:11.327870 CS Dly: 11 (0~44)
7531 11:13:11.331308 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7532 11:13:11.334868 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7533 11:13:11.335288
7534 11:13:11.338188 ----->DramcWriteLeveling(PI) begin...
7535 11:13:11.341119 ==
7536 11:13:11.341562 Dram Type= 6, Freq= 0, CH_0, rank 0
7537 11:13:11.347940 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7538 11:13:11.348523 ==
7539 11:13:11.350921 Write leveling (Byte 0): 34 => 34
7540 11:13:11.354259 Write leveling (Byte 1): 27 => 27
7541 11:13:11.358006 DramcWriteLeveling(PI) end<-----
7542 11:13:11.358423
7543 11:13:11.358758 ==
7544 11:13:11.361041 Dram Type= 6, Freq= 0, CH_0, rank 0
7545 11:13:11.364146 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7546 11:13:11.364566 ==
7547 11:13:11.367632 [Gating] SW mode calibration
7548 11:13:11.374357 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7549 11:13:11.381087 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7550 11:13:11.384461 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7551 11:13:11.387290 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7552 11:13:11.394123 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7553 11:13:11.397118 1 4 12 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
7554 11:13:11.400577 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7555 11:13:11.407298 1 4 20 | B1->B0 | 2828 3434 | 1 1 | (1 1) (1 1)
7556 11:13:11.410598 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7557 11:13:11.414329 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7558 11:13:11.420260 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7559 11:13:11.423546 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7560 11:13:11.426921 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7561 11:13:11.433696 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
7562 11:13:11.437454 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7563 11:13:11.440195 1 5 20 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
7564 11:13:11.446555 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
7565 11:13:11.449867 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7566 11:13:11.453373 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7567 11:13:11.459322 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7568 11:13:11.463114 1 6 8 | B1->B0 | 2323 2c2b | 0 1 | (0 0) (0 0)
7569 11:13:11.466292 1 6 12 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
7570 11:13:11.473052 1 6 16 | B1->B0 | 2525 4646 | 1 0 | (0 0) (0 0)
7571 11:13:11.475835 1 6 20 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
7572 11:13:11.479447 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7573 11:13:11.485952 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7574 11:13:11.489173 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7575 11:13:11.492513 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7576 11:13:11.499450 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7577 11:13:11.502432 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7578 11:13:11.505680 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7579 11:13:11.512464 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7580 11:13:11.515285 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 11:13:11.518712 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 11:13:11.525508 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 11:13:11.528882 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 11:13:11.531953 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 11:13:11.538465 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 11:13:11.541792 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 11:13:11.545306 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 11:13:11.552001 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 11:13:11.555440 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 11:13:11.558197 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 11:13:11.565131 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 11:13:11.568763 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7593 11:13:11.571827 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7594 11:13:11.578364 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7595 11:13:11.578799 Total UI for P1: 0, mck2ui 16
7596 11:13:11.584836 best dqsien dly found for B0: ( 1, 9, 12)
7597 11:13:11.587970 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7598 11:13:11.592195 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7599 11:13:11.597881 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7600 11:13:11.598366 Total UI for P1: 0, mck2ui 16
7601 11:13:11.604372 best dqsien dly found for B1: ( 1, 9, 20)
7602 11:13:11.607900 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7603 11:13:11.611518 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7604 11:13:11.612096
7605 11:13:11.614308 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7606 11:13:11.617447 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7607 11:13:11.621024 [Gating] SW calibration Done
7608 11:13:11.621439 ==
7609 11:13:11.624482 Dram Type= 6, Freq= 0, CH_0, rank 0
7610 11:13:11.627368 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7611 11:13:11.627786 ==
7612 11:13:11.630689 RX Vref Scan: 0
7613 11:13:11.631123
7614 11:13:11.634109 RX Vref 0 -> 0, step: 1
7615 11:13:11.634524
7616 11:13:11.634850 RX Delay 0 -> 252, step: 8
7617 11:13:11.640743 iDelay=192, Bit 0, Center 135 (80 ~ 191) 112
7618 11:13:11.643459 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7619 11:13:11.646957 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7620 11:13:11.650249 iDelay=192, Bit 3, Center 123 (72 ~ 175) 104
7621 11:13:11.653705 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7622 11:13:11.660668 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7623 11:13:11.663980 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7624 11:13:11.667134 iDelay=192, Bit 7, Center 135 (80 ~ 191) 112
7625 11:13:11.670485 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
7626 11:13:11.673358 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7627 11:13:11.679915 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7628 11:13:11.683632 iDelay=192, Bit 11, Center 119 (64 ~ 175) 112
7629 11:13:11.686631 iDelay=192, Bit 12, Center 131 (72 ~ 191) 120
7630 11:13:11.689702 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7631 11:13:11.696845 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7632 11:13:11.699828 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7633 11:13:11.700388 ==
7634 11:13:11.703061 Dram Type= 6, Freq= 0, CH_0, rank 0
7635 11:13:11.706227 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7636 11:13:11.706759 ==
7637 11:13:11.709583 DQS Delay:
7638 11:13:11.710099 DQS0 = 0, DQS1 = 0
7639 11:13:11.710479 DQM Delay:
7640 11:13:11.713076 DQM0 = 131, DQM1 = 126
7641 11:13:11.713545 DQ Delay:
7642 11:13:11.716467 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =123
7643 11:13:11.719772 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =135
7644 11:13:11.722712 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =119
7645 11:13:11.729438 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7646 11:13:11.730036
7647 11:13:11.730568
7648 11:13:11.731075 ==
7649 11:13:11.732952 Dram Type= 6, Freq= 0, CH_0, rank 0
7650 11:13:11.735668 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7651 11:13:11.736163 ==
7652 11:13:11.736539
7653 11:13:11.736871
7654 11:13:11.739165 TX Vref Scan disable
7655 11:13:11.742654 == TX Byte 0 ==
7656 11:13:11.745519 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7657 11:13:11.748952 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7658 11:13:11.752774 == TX Byte 1 ==
7659 11:13:11.755388 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7660 11:13:11.758998 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7661 11:13:11.759428 ==
7662 11:13:11.762062 Dram Type= 6, Freq= 0, CH_0, rank 0
7663 11:13:11.765639 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7664 11:13:11.768468 ==
7665 11:13:11.781662
7666 11:13:11.784735 TX Vref early break, caculate TX vref
7667 11:13:11.788358 TX Vref=16, minBit 10, minWin=22, winSum=372
7668 11:13:11.791017 TX Vref=18, minBit 7, minWin=23, winSum=383
7669 11:13:11.794500 TX Vref=20, minBit 8, minWin=23, winSum=392
7670 11:13:11.797810 TX Vref=22, minBit 8, minWin=23, winSum=402
7671 11:13:11.801166 TX Vref=24, minBit 1, minWin=24, winSum=408
7672 11:13:11.807973 TX Vref=26, minBit 1, minWin=25, winSum=416
7673 11:13:11.811287 TX Vref=28, minBit 2, minWin=25, winSum=421
7674 11:13:11.814611 TX Vref=30, minBit 2, minWin=25, winSum=418
7675 11:13:11.817635 TX Vref=32, minBit 4, minWin=24, winSum=408
7676 11:13:11.820983 TX Vref=34, minBit 1, minWin=24, winSum=401
7677 11:13:11.827345 TX Vref=36, minBit 2, minWin=23, winSum=389
7678 11:13:11.830942 [TxChooseVref] Worse bit 2, Min win 25, Win sum 421, Final Vref 28
7679 11:13:11.831024
7680 11:13:11.834314 Final TX Range 0 Vref 28
7681 11:13:11.834401
7682 11:13:11.834470 ==
7683 11:13:11.837665 Dram Type= 6, Freq= 0, CH_0, rank 0
7684 11:13:11.841081 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7685 11:13:11.844232 ==
7686 11:13:11.844334
7687 11:13:11.844414
7688 11:13:11.844492 TX Vref Scan disable
7689 11:13:11.850852 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
7690 11:13:11.850962 == TX Byte 0 ==
7691 11:13:11.854363 u2DelayCellOfst[0]=10 cells (3 PI)
7692 11:13:11.857206 u2DelayCellOfst[1]=14 cells (4 PI)
7693 11:13:11.860756 u2DelayCellOfst[2]=10 cells (3 PI)
7694 11:13:11.863740 u2DelayCellOfst[3]=10 cells (3 PI)
7695 11:13:11.867078 u2DelayCellOfst[4]=7 cells (2 PI)
7696 11:13:11.870208 u2DelayCellOfst[5]=0 cells (0 PI)
7697 11:13:11.873548 u2DelayCellOfst[6]=14 cells (4 PI)
7698 11:13:11.877135 u2DelayCellOfst[7]=14 cells (4 PI)
7699 11:13:11.880483 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7700 11:13:11.883434 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7701 11:13:11.887114 == TX Byte 1 ==
7702 11:13:11.890616 u2DelayCellOfst[8]=0 cells (0 PI)
7703 11:13:11.893638 u2DelayCellOfst[9]=0 cells (0 PI)
7704 11:13:11.897081 u2DelayCellOfst[10]=7 cells (2 PI)
7705 11:13:11.900334 u2DelayCellOfst[11]=3 cells (1 PI)
7706 11:13:11.903674 u2DelayCellOfst[12]=10 cells (3 PI)
7707 11:13:11.906896 u2DelayCellOfst[13]=10 cells (3 PI)
7708 11:13:11.909966 u2DelayCellOfst[14]=14 cells (4 PI)
7709 11:13:11.913495 u2DelayCellOfst[15]=10 cells (3 PI)
7710 11:13:11.916997 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7711 11:13:11.919667 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7712 11:13:11.923613 DramC Write-DBI on
7713 11:13:11.924060 ==
7714 11:13:11.926451 Dram Type= 6, Freq= 0, CH_0, rank 0
7715 11:13:11.929630 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7716 11:13:11.930053 ==
7717 11:13:11.930388
7718 11:13:11.930697
7719 11:13:11.933017 TX Vref Scan disable
7720 11:13:11.936485 == TX Byte 0 ==
7721 11:13:11.939348 Update DQM dly =733 (2 ,6, 29) DQM OEN =(3 ,3)
7722 11:13:11.939793 == TX Byte 1 ==
7723 11:13:11.945967 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7724 11:13:11.946412 DramC Write-DBI off
7725 11:13:11.946747
7726 11:13:11.947055 [DATLAT]
7727 11:13:11.949293 Freq=1600, CH0 RK0
7728 11:13:11.949714
7729 11:13:11.952772 DATLAT Default: 0xf
7730 11:13:11.953189 0, 0xFFFF, sum = 0
7731 11:13:11.955850 1, 0xFFFF, sum = 0
7732 11:13:11.956326 2, 0xFFFF, sum = 0
7733 11:13:11.959405 3, 0xFFFF, sum = 0
7734 11:13:11.959828 4, 0xFFFF, sum = 0
7735 11:13:11.962748 5, 0xFFFF, sum = 0
7736 11:13:11.963191 6, 0xFFFF, sum = 0
7737 11:13:11.965791 7, 0xFFFF, sum = 0
7738 11:13:11.966169 8, 0xFFFF, sum = 0
7739 11:13:11.968943 9, 0xFFFF, sum = 0
7740 11:13:11.969025 10, 0xFFFF, sum = 0
7741 11:13:11.972435 11, 0xFFFF, sum = 0
7742 11:13:11.972518 12, 0xFFFF, sum = 0
7743 11:13:11.975353 13, 0xFFFF, sum = 0
7744 11:13:11.975446 14, 0x0, sum = 1
7745 11:13:11.978841 15, 0x0, sum = 2
7746 11:13:11.978915 16, 0x0, sum = 3
7747 11:13:11.982514 17, 0x0, sum = 4
7748 11:13:11.982584 best_step = 15
7749 11:13:11.982642
7750 11:13:11.982701 ==
7751 11:13:11.986230 Dram Type= 6, Freq= 0, CH_0, rank 0
7752 11:13:11.992550 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7753 11:13:11.992975 ==
7754 11:13:11.993306 RX Vref Scan: 1
7755 11:13:11.993638
7756 11:13:11.995967 Set Vref Range= 24 -> 127
7757 11:13:11.996440
7758 11:13:11.998942 RX Vref 24 -> 127, step: 1
7759 11:13:11.999362
7760 11:13:12.002480 RX Delay 11 -> 252, step: 4
7761 11:13:12.002903
7762 11:13:12.006011 Set Vref, RX VrefLevel [Byte0]: 24
7763 11:13:12.008678 [Byte1]: 24
7764 11:13:12.009267
7765 11:13:12.012169 Set Vref, RX VrefLevel [Byte0]: 25
7766 11:13:12.015597 [Byte1]: 25
7767 11:13:12.016015
7768 11:13:12.018644 Set Vref, RX VrefLevel [Byte0]: 26
7769 11:13:12.021936 [Byte1]: 26
7770 11:13:12.025713
7771 11:13:12.026143 Set Vref, RX VrefLevel [Byte0]: 27
7772 11:13:12.031695 [Byte1]: 27
7773 11:13:12.032152
7774 11:13:12.035240 Set Vref, RX VrefLevel [Byte0]: 28
7775 11:13:12.038347 [Byte1]: 28
7776 11:13:12.038760
7777 11:13:12.041568 Set Vref, RX VrefLevel [Byte0]: 29
7778 11:13:12.044986 [Byte1]: 29
7779 11:13:12.048357
7780 11:13:12.048768 Set Vref, RX VrefLevel [Byte0]: 30
7781 11:13:12.051562 [Byte1]: 30
7782 11:13:12.055905
7783 11:13:12.056541 Set Vref, RX VrefLevel [Byte0]: 31
7784 11:13:12.059250 [Byte1]: 31
7785 11:13:12.063824
7786 11:13:12.064431 Set Vref, RX VrefLevel [Byte0]: 32
7787 11:13:12.066790 [Byte1]: 32
7788 11:13:12.071028
7789 11:13:12.071568 Set Vref, RX VrefLevel [Byte0]: 33
7790 11:13:12.074633 [Byte1]: 33
7791 11:13:12.078780
7792 11:13:12.079341 Set Vref, RX VrefLevel [Byte0]: 34
7793 11:13:12.081759 [Byte1]: 34
7794 11:13:12.086336
7795 11:13:12.086443 Set Vref, RX VrefLevel [Byte0]: 35
7796 11:13:12.089877 [Byte1]: 35
7797 11:13:12.093585
7798 11:13:12.093667 Set Vref, RX VrefLevel [Byte0]: 36
7799 11:13:12.097301 [Byte1]: 36
7800 11:13:12.101536
7801 11:13:12.101619 Set Vref, RX VrefLevel [Byte0]: 37
7802 11:13:12.104346 [Byte1]: 37
7803 11:13:12.109197
7804 11:13:12.109279 Set Vref, RX VrefLevel [Byte0]: 38
7805 11:13:12.111978 [Byte1]: 38
7806 11:13:12.116339
7807 11:13:12.116419 Set Vref, RX VrefLevel [Byte0]: 39
7808 11:13:12.119698 [Byte1]: 39
7809 11:13:12.124340
7810 11:13:12.124420 Set Vref, RX VrefLevel [Byte0]: 40
7811 11:13:12.127235 [Byte1]: 40
7812 11:13:12.131563
7813 11:13:12.131644 Set Vref, RX VrefLevel [Byte0]: 41
7814 11:13:12.134905 [Byte1]: 41
7815 11:13:12.139437
7816 11:13:12.139517 Set Vref, RX VrefLevel [Byte0]: 42
7817 11:13:12.142765 [Byte1]: 42
7818 11:13:12.147333
7819 11:13:12.147750 Set Vref, RX VrefLevel [Byte0]: 43
7820 11:13:12.150941 [Byte1]: 43
7821 11:13:12.154889
7822 11:13:12.155301 Set Vref, RX VrefLevel [Byte0]: 44
7823 11:13:12.157958 [Byte1]: 44
7824 11:13:12.162636
7825 11:13:12.163153 Set Vref, RX VrefLevel [Byte0]: 45
7826 11:13:12.166075 [Byte1]: 45
7827 11:13:12.170019
7828 11:13:12.170525 Set Vref, RX VrefLevel [Byte0]: 46
7829 11:13:12.173463 [Byte1]: 46
7830 11:13:12.177509
7831 11:13:12.177925 Set Vref, RX VrefLevel [Byte0]: 47
7832 11:13:12.181063 [Byte1]: 47
7833 11:13:12.185303
7834 11:13:12.185746 Set Vref, RX VrefLevel [Byte0]: 48
7835 11:13:12.188650 [Byte1]: 48
7836 11:13:12.192711
7837 11:13:12.193124 Set Vref, RX VrefLevel [Byte0]: 49
7838 11:13:12.196178 [Byte1]: 49
7839 11:13:12.200799
7840 11:13:12.201274 Set Vref, RX VrefLevel [Byte0]: 50
7841 11:13:12.203490 [Byte1]: 50
7842 11:13:12.208229
7843 11:13:12.208741 Set Vref, RX VrefLevel [Byte0]: 51
7844 11:13:12.210846 [Byte1]: 51
7845 11:13:12.215416
7846 11:13:12.215544 Set Vref, RX VrefLevel [Byte0]: 52
7847 11:13:12.218739 [Byte1]: 52
7848 11:13:12.223087
7849 11:13:12.223180 Set Vref, RX VrefLevel [Byte0]: 53
7850 11:13:12.226550 [Byte1]: 53
7851 11:13:12.230581
7852 11:13:12.230671 Set Vref, RX VrefLevel [Byte0]: 54
7853 11:13:12.233781 [Byte1]: 54
7854 11:13:12.238365
7855 11:13:12.238449 Set Vref, RX VrefLevel [Byte0]: 55
7856 11:13:12.241636 [Byte1]: 55
7857 11:13:12.245706
7858 11:13:12.245839 Set Vref, RX VrefLevel [Byte0]: 56
7859 11:13:12.248939 [Byte1]: 56
7860 11:13:12.253584
7861 11:13:12.253660 Set Vref, RX VrefLevel [Byte0]: 57
7862 11:13:12.256611 [Byte1]: 57
7863 11:13:12.261299
7864 11:13:12.261408 Set Vref, RX VrefLevel [Byte0]: 58
7865 11:13:12.264717 [Byte1]: 58
7866 11:13:12.268908
7867 11:13:12.269015 Set Vref, RX VrefLevel [Byte0]: 59
7868 11:13:12.271743 [Byte1]: 59
7869 11:13:12.276164
7870 11:13:12.276245 Set Vref, RX VrefLevel [Byte0]: 60
7871 11:13:12.279708 [Byte1]: 60
7872 11:13:12.283739
7873 11:13:12.283832 Set Vref, RX VrefLevel [Byte0]: 61
7874 11:13:12.287411 [Byte1]: 61
7875 11:13:12.291632
7876 11:13:12.291731 Set Vref, RX VrefLevel [Byte0]: 62
7877 11:13:12.295018 [Byte1]: 62
7878 11:13:12.299063
7879 11:13:12.299144 Set Vref, RX VrefLevel [Byte0]: 63
7880 11:13:12.302643 [Byte1]: 63
7881 11:13:12.306820
7882 11:13:12.306901 Set Vref, RX VrefLevel [Byte0]: 64
7883 11:13:12.310120 [Byte1]: 64
7884 11:13:12.314335
7885 11:13:12.314416 Set Vref, RX VrefLevel [Byte0]: 65
7886 11:13:12.317873 [Byte1]: 65
7887 11:13:12.322226
7888 11:13:12.322307 Set Vref, RX VrefLevel [Byte0]: 66
7889 11:13:12.325145 [Byte1]: 66
7890 11:13:12.329991
7891 11:13:12.330071 Set Vref, RX VrefLevel [Byte0]: 67
7892 11:13:12.332841 [Byte1]: 67
7893 11:13:12.337389
7894 11:13:12.337469 Set Vref, RX VrefLevel [Byte0]: 68
7895 11:13:12.340453 [Byte1]: 68
7896 11:13:12.344766
7897 11:13:12.344862 Set Vref, RX VrefLevel [Byte0]: 69
7898 11:13:12.348185 [Byte1]: 69
7899 11:13:12.352397
7900 11:13:12.352479 Set Vref, RX VrefLevel [Byte0]: 70
7901 11:13:12.355932 [Byte1]: 70
7902 11:13:12.360035
7903 11:13:12.360144 Set Vref, RX VrefLevel [Byte0]: 71
7904 11:13:12.363685 [Byte1]: 71
7905 11:13:12.367391
7906 11:13:12.367503 Set Vref, RX VrefLevel [Byte0]: 72
7907 11:13:12.370892 [Byte1]: 72
7908 11:13:12.375054
7909 11:13:12.375155 Set Vref, RX VrefLevel [Byte0]: 73
7910 11:13:12.378571 [Byte1]: 73
7911 11:13:12.382710
7912 11:13:12.382821 Final RX Vref Byte 0 = 54 to rank0
7913 11:13:12.386438 Final RX Vref Byte 1 = 61 to rank0
7914 11:13:12.389291 Final RX Vref Byte 0 = 54 to rank1
7915 11:13:12.392772 Final RX Vref Byte 1 = 61 to rank1==
7916 11:13:12.396284 Dram Type= 6, Freq= 0, CH_0, rank 0
7917 11:13:12.402660 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7918 11:13:12.402751 ==
7919 11:13:12.402845 DQS Delay:
7920 11:13:12.406105 DQS0 = 0, DQS1 = 0
7921 11:13:12.406213 DQM Delay:
7922 11:13:12.406311 DQM0 = 128, DQM1 = 124
7923 11:13:12.408947 DQ Delay:
7924 11:13:12.412515 DQ0 =130, DQ1 =130, DQ2 =126, DQ3 =124
7925 11:13:12.415511 DQ4 =130, DQ5 =118, DQ6 =136, DQ7 =134
7926 11:13:12.419045 DQ8 =112, DQ9 =112, DQ10 =126, DQ11 =120
7927 11:13:12.422045 DQ12 =132, DQ13 =128, DQ14 =132, DQ15 =130
7928 11:13:12.422122
7929 11:13:12.422185
7930 11:13:12.422244
7931 11:13:12.425299 [DramC_TX_OE_Calibration] TA2
7932 11:13:12.428675 Original DQ_B0 (3 6) =30, OEN = 27
7933 11:13:12.432364 Original DQ_B1 (3 6) =30, OEN = 27
7934 11:13:12.435208 24, 0x0, End_B0=24 End_B1=24
7935 11:13:12.438634 25, 0x0, End_B0=25 End_B1=25
7936 11:13:12.438708 26, 0x0, End_B0=26 End_B1=26
7937 11:13:12.441860 27, 0x0, End_B0=27 End_B1=27
7938 11:13:12.445148 28, 0x0, End_B0=28 End_B1=28
7939 11:13:12.448295 29, 0x0, End_B0=29 End_B1=29
7940 11:13:12.451556 30, 0x0, End_B0=30 End_B1=30
7941 11:13:12.451666 31, 0x4141, End_B0=30 End_B1=30
7942 11:13:12.455323 Byte0 end_step=30 best_step=27
7943 11:13:12.458233 Byte1 end_step=30 best_step=27
7944 11:13:12.461589 Byte0 TX OE(2T, 0.5T) = (3, 3)
7945 11:13:12.464982 Byte1 TX OE(2T, 0.5T) = (3, 3)
7946 11:13:12.465102
7947 11:13:12.465243
7948 11:13:12.471420 [DQSOSCAuto] RK0, (LSB)MR18= 0x1613, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 398 ps
7949 11:13:12.474854 CH0 RK0: MR19=303, MR18=1613
7950 11:13:12.481372 CH0_RK0: MR19=0x303, MR18=0x1613, DQSOSC=398, MR23=63, INC=23, DEC=15
7951 11:13:12.481456
7952 11:13:12.484871 ----->DramcWriteLeveling(PI) begin...
7953 11:13:12.484956 ==
7954 11:13:12.487907 Dram Type= 6, Freq= 0, CH_0, rank 1
7955 11:13:12.490952 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7956 11:13:12.494496 ==
7957 11:13:12.494607 Write leveling (Byte 0): 36 => 36
7958 11:13:12.498086 Write leveling (Byte 1): 25 => 25
7959 11:13:12.500939 DramcWriteLeveling(PI) end<-----
7960 11:13:12.501029
7961 11:13:12.501140 ==
7962 11:13:12.504446 Dram Type= 6, Freq= 0, CH_0, rank 1
7963 11:13:12.510869 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7964 11:13:12.510961 ==
7965 11:13:12.514363 [Gating] SW mode calibration
7966 11:13:12.520914 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7967 11:13:12.523971 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7968 11:13:12.530662 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7969 11:13:12.533855 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7970 11:13:12.537266 1 4 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
7971 11:13:12.543669 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7972 11:13:12.546901 1 4 16 | B1->B0 | 2525 3434 | 1 1 | (1 1) (1 1)
7973 11:13:12.550678 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7974 11:13:12.556666 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7975 11:13:12.560168 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7976 11:13:12.564021 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7977 11:13:12.570341 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7978 11:13:12.573330 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7979 11:13:12.576825 1 5 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 0)
7980 11:13:12.582921 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7981 11:13:12.586554 1 5 20 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
7982 11:13:12.590046 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7983 11:13:12.596597 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7984 11:13:12.599623 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7985 11:13:12.602939 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7986 11:13:12.609820 1 6 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (1 1)
7987 11:13:12.612863 1 6 12 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
7988 11:13:12.616271 1 6 16 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
7989 11:13:12.622812 1 6 20 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
7990 11:13:12.626299 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7991 11:13:12.629547 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7992 11:13:12.635712 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7993 11:13:12.639240 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7994 11:13:12.642898 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7995 11:13:12.649211 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7996 11:13:12.652599 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7997 11:13:12.655530 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7998 11:13:12.661951 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7999 11:13:12.665345 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 11:13:12.668591 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 11:13:12.675307 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 11:13:12.678815 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 11:13:12.682111 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 11:13:12.688796 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8005 11:13:12.692025 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 11:13:12.695083 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 11:13:12.702023 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 11:13:12.705045 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8009 11:13:12.708127 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8010 11:13:12.714671 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8011 11:13:12.718116 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8012 11:13:12.721575 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8013 11:13:12.724513 Total UI for P1: 0, mck2ui 16
8014 11:13:12.728056 best dqsien dly found for B0: ( 1, 9, 10)
8015 11:13:12.734695 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8016 11:13:12.737442 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8017 11:13:12.740874 Total UI for P1: 0, mck2ui 16
8018 11:13:12.744446 best dqsien dly found for B1: ( 1, 9, 18)
8019 11:13:12.747340 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8020 11:13:12.750816 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8021 11:13:12.750894
8022 11:13:12.754322 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8023 11:13:12.760632 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8024 11:13:12.760740 [Gating] SW calibration Done
8025 11:13:12.760832 ==
8026 11:13:12.764223 Dram Type= 6, Freq= 0, CH_0, rank 1
8027 11:13:12.770626 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8028 11:13:12.770736 ==
8029 11:13:12.770834 RX Vref Scan: 0
8030 11:13:12.770933
8031 11:13:12.773952 RX Vref 0 -> 0, step: 1
8032 11:13:12.774028
8033 11:13:12.777442 RX Delay 0 -> 252, step: 8
8034 11:13:12.780655 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8035 11:13:12.783797 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8036 11:13:12.787312 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8037 11:13:12.793591 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8038 11:13:12.797255 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8039 11:13:12.800189 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8040 11:13:12.803613 iDelay=200, Bit 6, Center 139 (88 ~ 191) 104
8041 11:13:12.807056 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8042 11:13:12.813334 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8043 11:13:12.816678 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8044 11:13:12.820169 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8045 11:13:12.823596 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8046 11:13:12.826504 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8047 11:13:12.833535 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8048 11:13:12.836463 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8049 11:13:12.839982 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8050 11:13:12.840099 ==
8051 11:13:12.843282 Dram Type= 6, Freq= 0, CH_0, rank 1
8052 11:13:12.846840 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8053 11:13:12.849713 ==
8054 11:13:12.849825 DQS Delay:
8055 11:13:12.849925 DQS0 = 0, DQS1 = 0
8056 11:13:12.853150 DQM Delay:
8057 11:13:12.853254 DQM0 = 131, DQM1 = 128
8058 11:13:12.856119 DQ Delay:
8059 11:13:12.859604 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
8060 11:13:12.863061 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
8061 11:13:12.866015 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =119
8062 11:13:12.869515 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =135
8063 11:13:12.869597
8064 11:13:12.869661
8065 11:13:12.869721 ==
8066 11:13:12.872957 Dram Type= 6, Freq= 0, CH_0, rank 1
8067 11:13:12.875735 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8068 11:13:12.879233 ==
8069 11:13:12.879314
8070 11:13:12.879379
8071 11:13:12.879439 TX Vref Scan disable
8072 11:13:12.882394 == TX Byte 0 ==
8073 11:13:12.885791 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8074 11:13:12.889138 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8075 11:13:12.892443 == TX Byte 1 ==
8076 11:13:12.895909 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8077 11:13:12.902342 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8078 11:13:12.902421 ==
8079 11:13:12.906005 Dram Type= 6, Freq= 0, CH_0, rank 1
8080 11:13:12.908934 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8081 11:13:12.909054 ==
8082 11:13:12.922376
8083 11:13:12.925641 TX Vref early break, caculate TX vref
8084 11:13:12.929538 TX Vref=16, minBit 2, minWin=23, winSum=382
8085 11:13:12.932481 TX Vref=18, minBit 2, minWin=23, winSum=389
8086 11:13:12.936016 TX Vref=20, minBit 9, minWin=23, winSum=389
8087 11:13:12.939313 TX Vref=22, minBit 13, minWin=24, winSum=402
8088 11:13:12.942133 TX Vref=24, minBit 10, minWin=24, winSum=406
8089 11:13:12.949031 TX Vref=26, minBit 4, minWin=25, winSum=418
8090 11:13:12.952455 TX Vref=28, minBit 3, minWin=25, winSum=412
8091 11:13:12.955810 TX Vref=30, minBit 1, minWin=25, winSum=412
8092 11:13:12.958783 TX Vref=32, minBit 1, minWin=24, winSum=402
8093 11:13:12.962312 TX Vref=34, minBit 1, minWin=24, winSum=396
8094 11:13:12.968784 [TxChooseVref] Worse bit 4, Min win 25, Win sum 418, Final Vref 26
8095 11:13:12.968930
8096 11:13:12.972483 Final TX Range 0 Vref 26
8097 11:13:12.972595
8098 11:13:12.972683 ==
8099 11:13:12.975192 Dram Type= 6, Freq= 0, CH_0, rank 1
8100 11:13:12.978738 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8101 11:13:12.978845 ==
8102 11:13:12.978939
8103 11:13:12.979027
8104 11:13:12.981851 TX Vref Scan disable
8105 11:13:12.988577 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8106 11:13:12.988662 == TX Byte 0 ==
8107 11:13:12.991616 u2DelayCellOfst[0]=10 cells (3 PI)
8108 11:13:12.994920 u2DelayCellOfst[1]=14 cells (4 PI)
8109 11:13:12.998471 u2DelayCellOfst[2]=7 cells (2 PI)
8110 11:13:13.001810 u2DelayCellOfst[3]=10 cells (3 PI)
8111 11:13:13.005252 u2DelayCellOfst[4]=7 cells (2 PI)
8112 11:13:13.008642 u2DelayCellOfst[5]=0 cells (0 PI)
8113 11:13:13.011511 u2DelayCellOfst[6]=14 cells (4 PI)
8114 11:13:13.015030 u2DelayCellOfst[7]=14 cells (4 PI)
8115 11:13:13.018484 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8116 11:13:13.021370 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8117 11:13:13.024692 == TX Byte 1 ==
8118 11:13:13.027758 u2DelayCellOfst[8]=0 cells (0 PI)
8119 11:13:13.031011 u2DelayCellOfst[9]=0 cells (0 PI)
8120 11:13:13.034470 u2DelayCellOfst[10]=7 cells (2 PI)
8121 11:13:13.038041 u2DelayCellOfst[11]=3 cells (1 PI)
8122 11:13:13.038117 u2DelayCellOfst[12]=7 cells (2 PI)
8123 11:13:13.040964 u2DelayCellOfst[13]=7 cells (2 PI)
8124 11:13:13.044359 u2DelayCellOfst[14]=14 cells (4 PI)
8125 11:13:13.047631 u2DelayCellOfst[15]=10 cells (3 PI)
8126 11:13:13.054485 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8127 11:13:13.057465 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8128 11:13:13.057563 DramC Write-DBI on
8129 11:13:13.060449 ==
8130 11:13:13.063911 Dram Type= 6, Freq= 0, CH_0, rank 1
8131 11:13:13.067222 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8132 11:13:13.067304 ==
8133 11:13:13.067370
8134 11:13:13.067430
8135 11:13:13.070667 TX Vref Scan disable
8136 11:13:13.070755 == TX Byte 0 ==
8137 11:13:13.077096 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8138 11:13:13.077190 == TX Byte 1 ==
8139 11:13:13.080619 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8140 11:13:13.084108 DramC Write-DBI off
8141 11:13:13.084621
8142 11:13:13.085010 [DATLAT]
8143 11:13:13.087708 Freq=1600, CH0 RK1
8144 11:13:13.088263
8145 11:13:13.088604 DATLAT Default: 0xf
8146 11:13:13.090499 0, 0xFFFF, sum = 0
8147 11:13:13.094027 1, 0xFFFF, sum = 0
8148 11:13:13.094453 2, 0xFFFF, sum = 0
8149 11:13:13.096967 3, 0xFFFF, sum = 0
8150 11:13:13.097431 4, 0xFFFF, sum = 0
8151 11:13:13.100837 5, 0xFFFF, sum = 0
8152 11:13:13.101265 6, 0xFFFF, sum = 0
8153 11:13:13.103961 7, 0xFFFF, sum = 0
8154 11:13:13.104423 8, 0xFFFF, sum = 0
8155 11:13:13.107223 9, 0xFFFF, sum = 0
8156 11:13:13.107649 10, 0xFFFF, sum = 0
8157 11:13:13.110373 11, 0xFFFF, sum = 0
8158 11:13:13.111009 12, 0xFFFF, sum = 0
8159 11:13:13.113526 13, 0xFFFF, sum = 0
8160 11:13:13.113956 14, 0x0, sum = 1
8161 11:13:13.116898 15, 0x0, sum = 2
8162 11:13:13.117389 16, 0x0, sum = 3
8163 11:13:13.120190 17, 0x0, sum = 4
8164 11:13:13.120618 best_step = 15
8165 11:13:13.120955
8166 11:13:13.121268 ==
8167 11:13:13.123795 Dram Type= 6, Freq= 0, CH_0, rank 1
8168 11:13:13.130029 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8169 11:13:13.130483 ==
8170 11:13:13.130865 RX Vref Scan: 0
8171 11:13:13.131186
8172 11:13:13.133477 RX Vref 0 -> 0, step: 1
8173 11:13:13.133937
8174 11:13:13.136674 RX Delay 19 -> 252, step: 4
8175 11:13:13.140005 iDelay=187, Bit 0, Center 124 (75 ~ 174) 100
8176 11:13:13.143737 iDelay=187, Bit 1, Center 130 (79 ~ 182) 104
8177 11:13:13.146950 iDelay=187, Bit 2, Center 124 (71 ~ 178) 108
8178 11:13:13.153491 iDelay=187, Bit 3, Center 126 (75 ~ 178) 104
8179 11:13:13.156162 iDelay=187, Bit 4, Center 132 (83 ~ 182) 100
8180 11:13:13.159415 iDelay=187, Bit 5, Center 118 (63 ~ 174) 112
8181 11:13:13.163013 iDelay=187, Bit 6, Center 136 (87 ~ 186) 100
8182 11:13:13.166510 iDelay=187, Bit 7, Center 134 (83 ~ 186) 104
8183 11:13:13.172844 iDelay=187, Bit 8, Center 114 (63 ~ 166) 104
8184 11:13:13.176228 iDelay=187, Bit 9, Center 110 (59 ~ 162) 104
8185 11:13:13.179667 iDelay=187, Bit 10, Center 126 (71 ~ 182) 112
8186 11:13:13.182553 iDelay=187, Bit 11, Center 118 (67 ~ 170) 104
8187 11:13:13.189737 iDelay=187, Bit 12, Center 126 (75 ~ 178) 104
8188 11:13:13.192724 iDelay=187, Bit 13, Center 128 (75 ~ 182) 108
8189 11:13:13.196460 iDelay=187, Bit 14, Center 134 (83 ~ 186) 104
8190 11:13:13.199356 iDelay=187, Bit 15, Center 128 (75 ~ 182) 108
8191 11:13:13.199913 ==
8192 11:13:13.202814 Dram Type= 6, Freq= 0, CH_0, rank 1
8193 11:13:13.209572 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8194 11:13:13.210016 ==
8195 11:13:13.210357 DQS Delay:
8196 11:13:13.212436 DQS0 = 0, DQS1 = 0
8197 11:13:13.212965 DQM Delay:
8198 11:13:13.213388 DQM0 = 128, DQM1 = 123
8199 11:13:13.215809 DQ Delay:
8200 11:13:13.219134 DQ0 =124, DQ1 =130, DQ2 =124, DQ3 =126
8201 11:13:13.223021 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =134
8202 11:13:13.225858 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
8203 11:13:13.229364 DQ12 =126, DQ13 =128, DQ14 =134, DQ15 =128
8204 11:13:13.229948
8205 11:13:13.230450
8206 11:13:13.231009
8207 11:13:13.232643 [DramC_TX_OE_Calibration] TA2
8208 11:13:13.235658 Original DQ_B0 (3 6) =30, OEN = 27
8209 11:13:13.239106 Original DQ_B1 (3 6) =30, OEN = 27
8210 11:13:13.241940 24, 0x0, End_B0=24 End_B1=24
8211 11:13:13.245231 25, 0x0, End_B0=25 End_B1=25
8212 11:13:13.245767 26, 0x0, End_B0=26 End_B1=26
8213 11:13:13.248715 27, 0x0, End_B0=27 End_B1=27
8214 11:13:13.252366 28, 0x0, End_B0=28 End_B1=28
8215 11:13:13.255770 29, 0x0, End_B0=29 End_B1=29
8216 11:13:13.256222 30, 0x0, End_B0=30 End_B1=30
8217 11:13:13.258561 31, 0x4141, End_B0=30 End_B1=30
8218 11:13:13.261889 Byte0 end_step=30 best_step=27
8219 11:13:13.265084 Byte1 end_step=30 best_step=27
8220 11:13:13.268613 Byte0 TX OE(2T, 0.5T) = (3, 3)
8221 11:13:13.271668 Byte1 TX OE(2T, 0.5T) = (3, 3)
8222 11:13:13.272108
8223 11:13:13.272447
8224 11:13:13.278335 [DQSOSCAuto] RK1, (LSB)MR18= 0x120f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 400 ps
8225 11:13:13.281741 CH0 RK1: MR19=303, MR18=120F
8226 11:13:13.288466 CH0_RK1: MR19=0x303, MR18=0x120F, DQSOSC=400, MR23=63, INC=23, DEC=15
8227 11:13:13.291937 [RxdqsGatingPostProcess] freq 1600
8228 11:13:13.298084 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8229 11:13:13.298503 best DQS0 dly(2T, 0.5T) = (1, 1)
8230 11:13:13.301791 best DQS1 dly(2T, 0.5T) = (1, 1)
8231 11:13:13.304603 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8232 11:13:13.308133 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8233 11:13:13.311425 best DQS0 dly(2T, 0.5T) = (1, 1)
8234 11:13:13.314608 best DQS1 dly(2T, 0.5T) = (1, 1)
8235 11:13:13.317883 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8236 11:13:13.321124 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8237 11:13:13.324338 Pre-setting of DQS Precalculation
8238 11:13:13.327994 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8239 11:13:13.328441 ==
8240 11:13:13.330934 Dram Type= 6, Freq= 0, CH_1, rank 0
8241 11:13:13.337535 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8242 11:13:13.337954 ==
8243 11:13:13.340901 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8244 11:13:13.347604 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8245 11:13:13.350956 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8246 11:13:13.357228 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8247 11:13:13.365889 [CA 0] Center 42 (12~72) winsize 61
8248 11:13:13.369070 [CA 1] Center 41 (11~72) winsize 62
8249 11:13:13.372359 [CA 2] Center 38 (9~67) winsize 59
8250 11:13:13.375829 [CA 3] Center 37 (8~66) winsize 59
8251 11:13:13.378719 [CA 4] Center 37 (8~67) winsize 60
8252 11:13:13.382067 [CA 5] Center 36 (7~66) winsize 60
8253 11:13:13.382593
8254 11:13:13.385232 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8255 11:13:13.385658
8256 11:13:13.391687 [CATrainingPosCal] consider 1 rank data
8257 11:13:13.392269 u2DelayCellTimex100 = 271/100 ps
8258 11:13:13.398737 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8259 11:13:13.402242 CA1 delay=41 (11~72),Diff = 5 PI (18 cell)
8260 11:13:13.405279 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8261 11:13:13.408500 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8262 11:13:13.411874 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8263 11:13:13.414697 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8264 11:13:13.415149
8265 11:13:13.418301 CA PerBit enable=1, Macro0, CA PI delay=36
8266 11:13:13.418885
8267 11:13:13.421550 [CBTSetCACLKResult] CA Dly = 36
8268 11:13:13.424559 CS Dly: 8 (0~39)
8269 11:13:13.427704 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8270 11:13:13.431108 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8271 11:13:13.431535 ==
8272 11:13:13.434816 Dram Type= 6, Freq= 0, CH_1, rank 1
8273 11:13:13.441328 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8274 11:13:13.441831 ==
8275 11:13:13.444856 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8276 11:13:13.451250 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8277 11:13:13.454161 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8278 11:13:13.460850 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8279 11:13:13.468921 [CA 0] Center 42 (12~72) winsize 61
8280 11:13:13.472505 [CA 1] Center 42 (13~72) winsize 60
8281 11:13:13.475443 [CA 2] Center 38 (9~68) winsize 60
8282 11:13:13.478757 [CA 3] Center 37 (8~66) winsize 59
8283 11:13:13.481935 [CA 4] Center 37 (7~68) winsize 62
8284 11:13:13.485079 [CA 5] Center 37 (7~67) winsize 61
8285 11:13:13.485530
8286 11:13:13.488160 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8287 11:13:13.488587
8288 11:13:13.495062 [CATrainingPosCal] consider 2 rank data
8289 11:13:13.495489 u2DelayCellTimex100 = 271/100 ps
8290 11:13:13.501707 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8291 11:13:13.504923 CA1 delay=42 (13~72),Diff = 6 PI (21 cell)
8292 11:13:13.508383 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8293 11:13:13.511650 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8294 11:13:13.515404 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8295 11:13:13.518547 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8296 11:13:13.518973
8297 11:13:13.521556 CA PerBit enable=1, Macro0, CA PI delay=36
8298 11:13:13.522197
8299 11:13:13.524591 [CBTSetCACLKResult] CA Dly = 36
8300 11:13:13.527703 CS Dly: 9 (0~42)
8301 11:13:13.531030 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8302 11:13:13.534498 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8303 11:13:13.534925
8304 11:13:13.538030 ----->DramcWriteLeveling(PI) begin...
8305 11:13:13.538463 ==
8306 11:13:13.541086 Dram Type= 6, Freq= 0, CH_1, rank 0
8307 11:13:13.547444 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8308 11:13:13.547870 ==
8309 11:13:13.550761 Write leveling (Byte 0): 25 => 25
8310 11:13:13.554057 Write leveling (Byte 1): 27 => 27
8311 11:13:13.554619 DramcWriteLeveling(PI) end<-----
8312 11:13:13.557258
8313 11:13:13.557817 ==
8314 11:13:13.560754 Dram Type= 6, Freq= 0, CH_1, rank 0
8315 11:13:13.563904 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8316 11:13:13.564010 ==
8317 11:13:13.567485 [Gating] SW mode calibration
8318 11:13:13.573676 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8319 11:13:13.580175 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8320 11:13:13.583867 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8321 11:13:13.586948 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8322 11:13:13.593281 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8323 11:13:13.596976 1 4 12 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
8324 11:13:13.600578 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8325 11:13:13.607051 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8326 11:13:13.610321 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8327 11:13:13.613582 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8328 11:13:13.619824 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8329 11:13:13.623231 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8330 11:13:13.626680 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8331 11:13:13.633126 1 5 12 | B1->B0 | 3434 2929 | 0 0 | (0 1) (0 1)
8332 11:13:13.636870 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8333 11:13:13.639850 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8334 11:13:13.646223 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8335 11:13:13.649377 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8336 11:13:13.652582 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8337 11:13:13.659169 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8338 11:13:13.662792 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8339 11:13:13.666155 1 6 12 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
8340 11:13:13.672927 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8341 11:13:13.675737 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8342 11:13:13.679208 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8343 11:13:13.685433 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8344 11:13:13.689211 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8345 11:13:13.691996 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8346 11:13:13.698960 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8347 11:13:13.702038 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8348 11:13:13.705691 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8349 11:13:13.711937 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 11:13:13.715041 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 11:13:13.718252 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 11:13:13.725296 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 11:13:13.728191 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 11:13:13.731677 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 11:13:13.737999 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 11:13:13.741519 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 11:13:13.744816 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 11:13:13.751266 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8359 11:13:13.754500 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8360 11:13:13.757664 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 11:13:13.764618 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 11:13:13.767812 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8363 11:13:13.770672 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8364 11:13:13.777660 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8365 11:13:13.781016 Total UI for P1: 0, mck2ui 16
8366 11:13:13.784361 best dqsien dly found for B0: ( 1, 9, 10)
8367 11:13:13.787575 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8368 11:13:13.791027 Total UI for P1: 0, mck2ui 16
8369 11:13:13.794456 best dqsien dly found for B1: ( 1, 9, 12)
8370 11:13:13.797376 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8371 11:13:13.800703 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8372 11:13:13.801120
8373 11:13:13.804095 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8374 11:13:13.810762 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8375 11:13:13.811265 [Gating] SW calibration Done
8376 11:13:13.811606 ==
8377 11:13:13.813702 Dram Type= 6, Freq= 0, CH_1, rank 0
8378 11:13:13.820321 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8379 11:13:13.820854 ==
8380 11:13:13.821232 RX Vref Scan: 0
8381 11:13:13.821548
8382 11:13:13.823769 RX Vref 0 -> 0, step: 1
8383 11:13:13.824219
8384 11:13:13.827141 RX Delay 0 -> 252, step: 8
8385 11:13:13.830532 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8386 11:13:13.833951 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8387 11:13:13.837099 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8388 11:13:13.843892 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8389 11:13:13.846977 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8390 11:13:13.850036 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8391 11:13:13.853463 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8392 11:13:13.856700 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8393 11:13:13.863248 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8394 11:13:13.866603 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8395 11:13:13.869610 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8396 11:13:13.873446 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8397 11:13:13.876016 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8398 11:13:13.883033 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8399 11:13:13.886156 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8400 11:13:13.889524 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8401 11:13:13.890030 ==
8402 11:13:13.892894 Dram Type= 6, Freq= 0, CH_1, rank 0
8403 11:13:13.895975 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8404 11:13:13.899495 ==
8405 11:13:13.900127 DQS Delay:
8406 11:13:13.900674 DQS0 = 0, DQS1 = 0
8407 11:13:13.902564 DQM Delay:
8408 11:13:13.903149 DQM0 = 134, DQM1 = 130
8409 11:13:13.905914 DQ Delay:
8410 11:13:13.909083 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8411 11:13:13.912523 DQ4 =131, DQ5 =143, DQ6 =147, DQ7 =127
8412 11:13:13.916138 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8413 11:13:13.918980 DQ12 =139, DQ13 =143, DQ14 =135, DQ15 =135
8414 11:13:13.919526
8415 11:13:13.920065
8416 11:13:13.920585 ==
8417 11:13:13.922720 Dram Type= 6, Freq= 0, CH_1, rank 0
8418 11:13:13.925365 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8419 11:13:13.928712 ==
8420 11:13:13.928808
8421 11:13:13.928903
8422 11:13:13.928996 TX Vref Scan disable
8423 11:13:13.932085 == TX Byte 0 ==
8424 11:13:13.935021 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8425 11:13:13.938667 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8426 11:13:13.941492 == TX Byte 1 ==
8427 11:13:13.945241 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8428 11:13:13.947935 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8429 11:13:13.951582 ==
8430 11:13:13.955009 Dram Type= 6, Freq= 0, CH_1, rank 0
8431 11:13:13.957963 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8432 11:13:13.958049 ==
8433 11:13:13.970164
8434 11:13:13.973671 TX Vref early break, caculate TX vref
8435 11:13:13.976994 TX Vref=16, minBit 8, minWin=21, winSum=371
8436 11:13:13.980159 TX Vref=18, minBit 8, minWin=21, winSum=379
8437 11:13:13.983537 TX Vref=20, minBit 8, minWin=23, winSum=390
8438 11:13:13.986683 TX Vref=22, minBit 3, minWin=24, winSum=399
8439 11:13:13.990245 TX Vref=24, minBit 6, minWin=24, winSum=407
8440 11:13:13.996622 TX Vref=26, minBit 8, minWin=24, winSum=414
8441 11:13:14.000229 TX Vref=28, minBit 1, minWin=25, winSum=419
8442 11:13:14.003215 TX Vref=30, minBit 1, minWin=25, winSum=414
8443 11:13:14.006678 TX Vref=32, minBit 6, minWin=24, winSum=405
8444 11:13:14.010102 TX Vref=34, minBit 1, minWin=23, winSum=391
8445 11:13:14.016639 [TxChooseVref] Worse bit 1, Min win 25, Win sum 419, Final Vref 28
8446 11:13:14.016734
8447 11:13:14.019954 Final TX Range 0 Vref 28
8448 11:13:14.020091
8449 11:13:14.020173 ==
8450 11:13:14.023571 Dram Type= 6, Freq= 0, CH_1, rank 0
8451 11:13:14.026434 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8452 11:13:14.026539 ==
8453 11:13:14.026632
8454 11:13:14.026721
8455 11:13:14.029839 TX Vref Scan disable
8456 11:13:14.036614 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8457 11:13:14.036703 == TX Byte 0 ==
8458 11:13:14.039942 u2DelayCellOfst[0]=18 cells (5 PI)
8459 11:13:14.042748 u2DelayCellOfst[1]=14 cells (4 PI)
8460 11:13:14.046188 u2DelayCellOfst[2]=0 cells (0 PI)
8461 11:13:14.049569 u2DelayCellOfst[3]=10 cells (3 PI)
8462 11:13:14.052970 u2DelayCellOfst[4]=10 cells (3 PI)
8463 11:13:14.056539 u2DelayCellOfst[5]=21 cells (6 PI)
8464 11:13:14.059329 u2DelayCellOfst[6]=18 cells (5 PI)
8465 11:13:14.062811 u2DelayCellOfst[7]=7 cells (2 PI)
8466 11:13:14.066134 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8467 11:13:14.069139 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8468 11:13:14.072558 == TX Byte 1 ==
8469 11:13:14.075803 u2DelayCellOfst[8]=0 cells (0 PI)
8470 11:13:14.079407 u2DelayCellOfst[9]=3 cells (1 PI)
8471 11:13:14.082682 u2DelayCellOfst[10]=14 cells (4 PI)
8472 11:13:14.085762 u2DelayCellOfst[11]=7 cells (2 PI)
8473 11:13:14.088848 u2DelayCellOfst[12]=14 cells (4 PI)
8474 11:13:14.089241 u2DelayCellOfst[13]=14 cells (4 PI)
8475 11:13:14.092441 u2DelayCellOfst[14]=18 cells (5 PI)
8476 11:13:14.095913 u2DelayCellOfst[15]=18 cells (5 PI)
8477 11:13:14.102200 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8478 11:13:14.105887 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8479 11:13:14.106309 DramC Write-DBI on
8480 11:13:14.108641 ==
8481 11:13:14.112009 Dram Type= 6, Freq= 0, CH_1, rank 0
8482 11:13:14.114985 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8483 11:13:14.115068 ==
8484 11:13:14.115133
8485 11:13:14.115193
8486 11:13:14.118138 TX Vref Scan disable
8487 11:13:14.118222 == TX Byte 0 ==
8488 11:13:14.125293 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8489 11:13:14.125777 == TX Byte 1 ==
8490 11:13:14.128836 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8491 11:13:14.131931 DramC Write-DBI off
8492 11:13:14.132383
8493 11:13:14.132817 [DATLAT]
8494 11:13:14.135188 Freq=1600, CH1 RK0
8495 11:13:14.135788
8496 11:13:14.136397 DATLAT Default: 0xf
8497 11:13:14.138675 0, 0xFFFF, sum = 0
8498 11:13:14.139124 1, 0xFFFF, sum = 0
8499 11:13:14.142091 2, 0xFFFF, sum = 0
8500 11:13:14.142516 3, 0xFFFF, sum = 0
8501 11:13:14.144996 4, 0xFFFF, sum = 0
8502 11:13:14.148430 5, 0xFFFF, sum = 0
8503 11:13:14.148854 6, 0xFFFF, sum = 0
8504 11:13:14.151298 7, 0xFFFF, sum = 0
8505 11:13:14.151950 8, 0xFFFF, sum = 0
8506 11:13:14.154943 9, 0xFFFF, sum = 0
8507 11:13:14.155504 10, 0xFFFF, sum = 0
8508 11:13:14.158424 11, 0xFFFF, sum = 0
8509 11:13:14.158859 12, 0xFFFF, sum = 0
8510 11:13:14.161772 13, 0xFFFF, sum = 0
8511 11:13:14.162206 14, 0x0, sum = 1
8512 11:13:14.165181 15, 0x0, sum = 2
8513 11:13:14.165615 16, 0x0, sum = 3
8514 11:13:14.168068 17, 0x0, sum = 4
8515 11:13:14.168616 best_step = 15
8516 11:13:14.169033
8517 11:13:14.169412 ==
8518 11:13:14.171513 Dram Type= 6, Freq= 0, CH_1, rank 0
8519 11:13:14.178293 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8520 11:13:14.178923 ==
8521 11:13:14.179437 RX Vref Scan: 1
8522 11:13:14.180022
8523 11:13:14.181455 Set Vref Range= 24 -> 127
8524 11:13:14.182073
8525 11:13:14.184466 RX Vref 24 -> 127, step: 1
8526 11:13:14.184955
8527 11:13:14.185335 RX Delay 19 -> 252, step: 4
8528 11:13:14.185700
8529 11:13:14.188136 Set Vref, RX VrefLevel [Byte0]: 24
8530 11:13:14.191120 [Byte1]: 24
8531 11:13:14.195087
8532 11:13:14.195574 Set Vref, RX VrefLevel [Byte0]: 25
8533 11:13:14.198507 [Byte1]: 25
8534 11:13:14.203083
8535 11:13:14.203496 Set Vref, RX VrefLevel [Byte0]: 26
8536 11:13:14.205944 [Byte1]: 26
8537 11:13:14.210231
8538 11:13:14.210652 Set Vref, RX VrefLevel [Byte0]: 27
8539 11:13:14.213763 [Byte1]: 27
8540 11:13:14.218279
8541 11:13:14.218742 Set Vref, RX VrefLevel [Byte0]: 28
8542 11:13:14.221455 [Byte1]: 28
8543 11:13:14.225832
8544 11:13:14.226303 Set Vref, RX VrefLevel [Byte0]: 29
8545 11:13:14.228655 [Byte1]: 29
8546 11:13:14.233112
8547 11:13:14.233552 Set Vref, RX VrefLevel [Byte0]: 30
8548 11:13:14.236571 [Byte1]: 30
8549 11:13:14.240468
8550 11:13:14.240911 Set Vref, RX VrefLevel [Byte0]: 31
8551 11:13:14.243603 [Byte1]: 31
8552 11:13:14.248206
8553 11:13:14.248644 Set Vref, RX VrefLevel [Byte0]: 32
8554 11:13:14.251659 [Byte1]: 32
8555 11:13:14.255889
8556 11:13:14.256424 Set Vref, RX VrefLevel [Byte0]: 33
8557 11:13:14.259205 [Byte1]: 33
8558 11:13:14.263699
8559 11:13:14.264140 Set Vref, RX VrefLevel [Byte0]: 34
8560 11:13:14.267253 [Byte1]: 34
8561 11:13:14.271090
8562 11:13:14.271510 Set Vref, RX VrefLevel [Byte0]: 35
8563 11:13:14.274642 [Byte1]: 35
8564 11:13:14.278462
8565 11:13:14.278885 Set Vref, RX VrefLevel [Byte0]: 36
8566 11:13:14.281726 [Byte1]: 36
8567 11:13:14.286091
8568 11:13:14.286538 Set Vref, RX VrefLevel [Byte0]: 37
8569 11:13:14.289266 [Byte1]: 37
8570 11:13:14.293428
8571 11:13:14.293885 Set Vref, RX VrefLevel [Byte0]: 38
8572 11:13:14.296921 [Byte1]: 38
8573 11:13:14.301215
8574 11:13:14.301677 Set Vref, RX VrefLevel [Byte0]: 39
8575 11:13:14.304658 [Byte1]: 39
8576 11:13:14.308701
8577 11:13:14.309126 Set Vref, RX VrefLevel [Byte0]: 40
8578 11:13:14.312484 [Byte1]: 40
8579 11:13:14.316548
8580 11:13:14.316968 Set Vref, RX VrefLevel [Byte0]: 41
8581 11:13:14.319342 [Byte1]: 41
8582 11:13:14.323886
8583 11:13:14.324357 Set Vref, RX VrefLevel [Byte0]: 42
8584 11:13:14.327035 [Byte1]: 42
8585 11:13:14.331356
8586 11:13:14.331780 Set Vref, RX VrefLevel [Byte0]: 43
8587 11:13:14.334932 [Byte1]: 43
8588 11:13:14.338738
8589 11:13:14.339347 Set Vref, RX VrefLevel [Byte0]: 44
8590 11:13:14.342098 [Byte1]: 44
8591 11:13:14.346507
8592 11:13:14.346944 Set Vref, RX VrefLevel [Byte0]: 45
8593 11:13:14.349926 [Byte1]: 45
8594 11:13:14.354099
8595 11:13:14.354522 Set Vref, RX VrefLevel [Byte0]: 46
8596 11:13:14.357370 [Byte1]: 46
8597 11:13:14.361751
8598 11:13:14.362175 Set Vref, RX VrefLevel [Byte0]: 47
8599 11:13:14.365185 [Byte1]: 47
8600 11:13:14.369201
8601 11:13:14.369624 Set Vref, RX VrefLevel [Byte0]: 48
8602 11:13:14.372444 [Byte1]: 48
8603 11:13:14.377258
8604 11:13:14.377800 Set Vref, RX VrefLevel [Byte0]: 49
8605 11:13:14.380346 [Byte1]: 49
8606 11:13:14.384323
8607 11:13:14.384745 Set Vref, RX VrefLevel [Byte0]: 50
8608 11:13:14.387613 [Byte1]: 50
8609 11:13:14.392101
8610 11:13:14.392523 Set Vref, RX VrefLevel [Byte0]: 51
8611 11:13:14.398757 [Byte1]: 51
8612 11:13:14.399200
8613 11:13:14.401691 Set Vref, RX VrefLevel [Byte0]: 52
8614 11:13:14.405131 [Byte1]: 52
8615 11:13:14.405633
8616 11:13:14.408193 Set Vref, RX VrefLevel [Byte0]: 53
8617 11:13:14.411568 [Byte1]: 53
8618 11:13:14.414907
8619 11:13:14.415331 Set Vref, RX VrefLevel [Byte0]: 54
8620 11:13:14.418523 [Byte1]: 54
8621 11:13:14.422685
8622 11:13:14.423177 Set Vref, RX VrefLevel [Byte0]: 55
8623 11:13:14.426005 [Byte1]: 55
8624 11:13:14.429629
8625 11:13:14.430129 Set Vref, RX VrefLevel [Byte0]: 56
8626 11:13:14.433100 [Byte1]: 56
8627 11:13:14.437595
8628 11:13:14.438035 Set Vref, RX VrefLevel [Byte0]: 57
8629 11:13:14.441036 [Byte1]: 57
8630 11:13:14.445029
8631 11:13:14.445456 Set Vref, RX VrefLevel [Byte0]: 58
8632 11:13:14.448430 [Byte1]: 58
8633 11:13:14.452742
8634 11:13:14.453209 Set Vref, RX VrefLevel [Byte0]: 59
8635 11:13:14.456108 [Byte1]: 59
8636 11:13:14.460258
8637 11:13:14.460700 Set Vref, RX VrefLevel [Byte0]: 60
8638 11:13:14.463686 [Byte1]: 60
8639 11:13:14.467804
8640 11:13:14.468278 Set Vref, RX VrefLevel [Byte0]: 61
8641 11:13:14.471041 [Byte1]: 61
8642 11:13:14.475521
8643 11:13:14.475953 Set Vref, RX VrefLevel [Byte0]: 62
8644 11:13:14.479062 [Byte1]: 62
8645 11:13:14.482871
8646 11:13:14.483310 Set Vref, RX VrefLevel [Byte0]: 63
8647 11:13:14.486485 [Byte1]: 63
8648 11:13:14.490362
8649 11:13:14.490836 Set Vref, RX VrefLevel [Byte0]: 64
8650 11:13:14.497271 [Byte1]: 64
8651 11:13:14.497856
8652 11:13:14.500428 Set Vref, RX VrefLevel [Byte0]: 65
8653 11:13:14.503608 [Byte1]: 65
8654 11:13:14.504124
8655 11:13:14.507201 Set Vref, RX VrefLevel [Byte0]: 66
8656 11:13:14.510065 [Byte1]: 66
8657 11:13:14.510499
8658 11:13:14.513527 Set Vref, RX VrefLevel [Byte0]: 67
8659 11:13:14.516839 [Byte1]: 67
8660 11:13:14.520809
8661 11:13:14.521369 Set Vref, RX VrefLevel [Byte0]: 68
8662 11:13:14.524241 [Byte1]: 68
8663 11:13:14.528227
8664 11:13:14.528641 Set Vref, RX VrefLevel [Byte0]: 69
8665 11:13:14.531872 [Byte1]: 69
8666 11:13:14.535748
8667 11:13:14.536322 Set Vref, RX VrefLevel [Byte0]: 70
8668 11:13:14.539159 [Byte1]: 70
8669 11:13:14.543941
8670 11:13:14.544405 Final RX Vref Byte 0 = 55 to rank0
8671 11:13:14.546822 Final RX Vref Byte 1 = 61 to rank0
8672 11:13:14.550018 Final RX Vref Byte 0 = 55 to rank1
8673 11:13:14.553486 Final RX Vref Byte 1 = 61 to rank1==
8674 11:13:14.556827 Dram Type= 6, Freq= 0, CH_1, rank 0
8675 11:13:14.563557 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8676 11:13:14.564014 ==
8677 11:13:14.564408 DQS Delay:
8678 11:13:14.566367 DQS0 = 0, DQS1 = 0
8679 11:13:14.566784 DQM Delay:
8680 11:13:14.567117 DQM0 = 132, DQM1 = 128
8681 11:13:14.569839 DQ Delay:
8682 11:13:14.573282 DQ0 =138, DQ1 =128, DQ2 =120, DQ3 =130
8683 11:13:14.576266 DQ4 =128, DQ5 =142, DQ6 =144, DQ7 =126
8684 11:13:14.579617 DQ8 =114, DQ9 =118, DQ10 =128, DQ11 =120
8685 11:13:14.582708 DQ12 =138, DQ13 =138, DQ14 =136, DQ15 =138
8686 11:13:14.583282
8687 11:13:14.583809
8688 11:13:14.584267
8689 11:13:14.586042 [DramC_TX_OE_Calibration] TA2
8690 11:13:14.589601 Original DQ_B0 (3 6) =30, OEN = 27
8691 11:13:14.592469 Original DQ_B1 (3 6) =30, OEN = 27
8692 11:13:14.596082 24, 0x0, End_B0=24 End_B1=24
8693 11:13:14.599354 25, 0x0, End_B0=25 End_B1=25
8694 11:13:14.599779 26, 0x0, End_B0=26 End_B1=26
8695 11:13:14.602463 27, 0x0, End_B0=27 End_B1=27
8696 11:13:14.605832 28, 0x0, End_B0=28 End_B1=28
8697 11:13:14.609082 29, 0x0, End_B0=29 End_B1=29
8698 11:13:14.609514 30, 0x0, End_B0=30 End_B1=30
8699 11:13:14.612583 31, 0x4141, End_B0=30 End_B1=30
8700 11:13:14.615477 Byte0 end_step=30 best_step=27
8701 11:13:14.619034 Byte1 end_step=30 best_step=27
8702 11:13:14.622330 Byte0 TX OE(2T, 0.5T) = (3, 3)
8703 11:13:14.625615 Byte1 TX OE(2T, 0.5T) = (3, 3)
8704 11:13:14.625913
8705 11:13:14.626153
8706 11:13:14.632404 [DQSOSCAuto] RK0, (LSB)MR18= 0xd17, (MSB)MR19= 0x303, tDQSOscB0 = 398 ps tDQSOscB1 = 403 ps
8707 11:13:14.635268 CH1 RK0: MR19=303, MR18=D17
8708 11:13:14.642245 CH1_RK0: MR19=0x303, MR18=0xD17, DQSOSC=398, MR23=63, INC=23, DEC=15
8709 11:13:14.642544
8710 11:13:14.645153 ----->DramcWriteLeveling(PI) begin...
8711 11:13:14.645457 ==
8712 11:13:14.648707 Dram Type= 6, Freq= 0, CH_1, rank 1
8713 11:13:14.652151 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8714 11:13:14.652457 ==
8715 11:13:14.655009 Write leveling (Byte 0): 25 => 25
8716 11:13:14.658536 Write leveling (Byte 1): 25 => 25
8717 11:13:14.661957 DramcWriteLeveling(PI) end<-----
8718 11:13:14.662256
8719 11:13:14.662491 ==
8720 11:13:14.665057 Dram Type= 6, Freq= 0, CH_1, rank 1
8721 11:13:14.668766 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8722 11:13:14.671418 ==
8723 11:13:14.671718 [Gating] SW mode calibration
8724 11:13:14.681278 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8725 11:13:14.684738 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8726 11:13:14.687829 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8727 11:13:14.694336 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8728 11:13:14.697860 1 4 8 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
8729 11:13:14.701210 1 4 12 | B1->B0 | 2626 3434 | 1 1 | (1 1) (1 1)
8730 11:13:14.707548 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8731 11:13:14.710894 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8732 11:13:14.717798 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8733 11:13:14.720727 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8734 11:13:14.724169 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8735 11:13:14.730600 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8736 11:13:14.734194 1 5 8 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8737 11:13:14.737261 1 5 12 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
8738 11:13:14.743559 1 5 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
8739 11:13:14.746972 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8740 11:13:14.750641 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8741 11:13:14.756892 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8742 11:13:14.760546 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8743 11:13:14.763335 1 6 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
8744 11:13:14.770104 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8745 11:13:14.773664 1 6 12 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
8746 11:13:14.776697 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8747 11:13:14.783068 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8748 11:13:14.786583 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8749 11:13:14.789426 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8750 11:13:14.796603 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8751 11:13:14.799514 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8752 11:13:14.803219 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8753 11:13:14.809259 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8754 11:13:14.812535 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8755 11:13:14.815824 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8756 11:13:14.822449 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8757 11:13:14.825454 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8758 11:13:14.828695 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8759 11:13:14.835190 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8760 11:13:14.839002 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8761 11:13:14.841865 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8762 11:13:14.848664 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8763 11:13:14.852182 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8764 11:13:14.855496 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8765 11:13:14.861760 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8766 11:13:14.865257 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8767 11:13:14.868760 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8768 11:13:14.874839 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8769 11:13:14.878276 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8770 11:13:14.881646 Total UI for P1: 0, mck2ui 16
8771 11:13:14.885018 best dqsien dly found for B0: ( 1, 9, 6)
8772 11:13:14.887819 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8773 11:13:14.891186 Total UI for P1: 0, mck2ui 16
8774 11:13:14.894778 best dqsien dly found for B1: ( 1, 9, 12)
8775 11:13:14.897634 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8776 11:13:14.904483 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8777 11:13:14.904758
8778 11:13:14.907497 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8779 11:13:14.910903 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8780 11:13:14.913728 [Gating] SW calibration Done
8781 11:13:14.913937 ==
8782 11:13:14.917464 Dram Type= 6, Freq= 0, CH_1, rank 1
8783 11:13:14.920677 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8784 11:13:14.920836 ==
8785 11:13:14.924055 RX Vref Scan: 0
8786 11:13:14.924191
8787 11:13:14.924313 RX Vref 0 -> 0, step: 1
8788 11:13:14.924433
8789 11:13:14.926930 RX Delay 0 -> 252, step: 8
8790 11:13:14.930396 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8791 11:13:14.936855 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8792 11:13:14.940208 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8793 11:13:14.943553 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8794 11:13:14.947096 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8795 11:13:14.950082 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8796 11:13:14.956880 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8797 11:13:14.959842 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8798 11:13:14.963315 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8799 11:13:14.966799 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8800 11:13:14.969703 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8801 11:13:14.976357 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8802 11:13:14.979777 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8803 11:13:14.983306 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8804 11:13:14.986402 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8805 11:13:14.992931 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8806 11:13:14.993048 ==
8807 11:13:14.996520 Dram Type= 6, Freq= 0, CH_1, rank 1
8808 11:13:14.999243 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8809 11:13:14.999330 ==
8810 11:13:14.999451 DQS Delay:
8811 11:13:15.002737 DQS0 = 0, DQS1 = 0
8812 11:13:15.002886 DQM Delay:
8813 11:13:15.006295 DQM0 = 133, DQM1 = 130
8814 11:13:15.006414 DQ Delay:
8815 11:13:15.009372 DQ0 =135, DQ1 =131, DQ2 =123, DQ3 =131
8816 11:13:15.012775 DQ4 =131, DQ5 =143, DQ6 =139, DQ7 =131
8817 11:13:15.015682 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8818 11:13:15.019136 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8819 11:13:15.022476
8820 11:13:15.022584
8821 11:13:15.022677 ==
8822 11:13:15.025815 Dram Type= 6, Freq= 0, CH_1, rank 1
8823 11:13:15.029174 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8824 11:13:15.029288 ==
8825 11:13:15.029382
8826 11:13:15.029471
8827 11:13:15.032121 TX Vref Scan disable
8828 11:13:15.032204 == TX Byte 0 ==
8829 11:13:15.038780 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8830 11:13:15.042069 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8831 11:13:15.042189 == TX Byte 1 ==
8832 11:13:15.048786 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8833 11:13:15.052147 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8834 11:13:15.052267 ==
8835 11:13:15.055047 Dram Type= 6, Freq= 0, CH_1, rank 1
8836 11:13:15.058325 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8837 11:13:15.058444 ==
8838 11:13:15.072263
8839 11:13:15.075664 TX Vref early break, caculate TX vref
8840 11:13:15.078895 TX Vref=16, minBit 9, minWin=22, winSum=381
8841 11:13:15.081655 TX Vref=18, minBit 9, minWin=22, winSum=390
8842 11:13:15.085189 TX Vref=20, minBit 9, minWin=23, winSum=398
8843 11:13:15.088090 TX Vref=22, minBit 9, minWin=23, winSum=405
8844 11:13:15.095016 TX Vref=24, minBit 9, minWin=24, winSum=412
8845 11:13:15.097920 TX Vref=26, minBit 9, minWin=25, winSum=421
8846 11:13:15.101186 TX Vref=28, minBit 0, minWin=25, winSum=425
8847 11:13:15.104713 TX Vref=30, minBit 9, minWin=24, winSum=415
8848 11:13:15.108235 TX Vref=32, minBit 5, minWin=24, winSum=407
8849 11:13:15.111116 TX Vref=34, minBit 5, minWin=24, winSum=402
8850 11:13:15.117851 [TxChooseVref] Worse bit 0, Min win 25, Win sum 425, Final Vref 28
8851 11:13:15.117939
8852 11:13:15.121330 Final TX Range 0 Vref 28
8853 11:13:15.121428
8854 11:13:15.121497 ==
8855 11:13:15.124486 Dram Type= 6, Freq= 0, CH_1, rank 1
8856 11:13:15.127813 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8857 11:13:15.127921 ==
8858 11:13:15.131111
8859 11:13:15.131196
8860 11:13:15.131270 TX Vref Scan disable
8861 11:13:15.137715 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =271/100 ps
8862 11:13:15.137828 == TX Byte 0 ==
8863 11:13:15.140552 u2DelayCellOfst[0]=14 cells (4 PI)
8864 11:13:15.143930 u2DelayCellOfst[1]=10 cells (3 PI)
8865 11:13:15.147251 u2DelayCellOfst[2]=0 cells (0 PI)
8866 11:13:15.150553 u2DelayCellOfst[3]=7 cells (2 PI)
8867 11:13:15.153906 u2DelayCellOfst[4]=7 cells (2 PI)
8868 11:13:15.157351 u2DelayCellOfst[5]=18 cells (5 PI)
8869 11:13:15.160976 u2DelayCellOfst[6]=18 cells (5 PI)
8870 11:13:15.164261 u2DelayCellOfst[7]=7 cells (2 PI)
8871 11:13:15.167531 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8872 11:13:15.170294 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8873 11:13:15.173712 == TX Byte 1 ==
8874 11:13:15.177126 u2DelayCellOfst[8]=0 cells (0 PI)
8875 11:13:15.180526 u2DelayCellOfst[9]=0 cells (0 PI)
8876 11:13:15.183663 u2DelayCellOfst[10]=10 cells (3 PI)
8877 11:13:15.187131 u2DelayCellOfst[11]=3 cells (1 PI)
8878 11:13:15.190660 u2DelayCellOfst[12]=10 cells (3 PI)
8879 11:13:15.193548 u2DelayCellOfst[13]=14 cells (4 PI)
8880 11:13:15.197070 u2DelayCellOfst[14]=14 cells (4 PI)
8881 11:13:15.200162 u2DelayCellOfst[15]=14 cells (4 PI)
8882 11:13:15.203621 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8883 11:13:15.206712 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8884 11:13:15.210107 DramC Write-DBI on
8885 11:13:15.210672 ==
8886 11:13:15.213572 Dram Type= 6, Freq= 0, CH_1, rank 1
8887 11:13:15.216269 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8888 11:13:15.216634 ==
8889 11:13:15.216919
8890 11:13:15.217185
8891 11:13:15.219542 TX Vref Scan disable
8892 11:13:15.219840 == TX Byte 0 ==
8893 11:13:15.226282 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8894 11:13:15.226486 == TX Byte 1 ==
8895 11:13:15.232978 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8896 11:13:15.233175 DramC Write-DBI off
8897 11:13:15.233346
8898 11:13:15.233510 [DATLAT]
8899 11:13:15.236398 Freq=1600, CH1 RK1
8900 11:13:15.236530
8901 11:13:15.239498 DATLAT Default: 0xf
8902 11:13:15.239614 0, 0xFFFF, sum = 0
8903 11:13:15.243004 1, 0xFFFF, sum = 0
8904 11:13:15.243124 2, 0xFFFF, sum = 0
8905 11:13:15.245968 3, 0xFFFF, sum = 0
8906 11:13:15.246073 4, 0xFFFF, sum = 0
8907 11:13:15.249215 5, 0xFFFF, sum = 0
8908 11:13:15.249309 6, 0xFFFF, sum = 0
8909 11:13:15.252619 7, 0xFFFF, sum = 0
8910 11:13:15.252714 8, 0xFFFF, sum = 0
8911 11:13:15.255812 9, 0xFFFF, sum = 0
8912 11:13:15.255929 10, 0xFFFF, sum = 0
8913 11:13:15.259470 11, 0xFFFF, sum = 0
8914 11:13:15.259557 12, 0xFFFF, sum = 0
8915 11:13:15.262121 13, 0xFFFF, sum = 0
8916 11:13:15.262206 14, 0x0, sum = 1
8917 11:13:15.265417 15, 0x0, sum = 2
8918 11:13:15.265503 16, 0x0, sum = 3
8919 11:13:15.269365 17, 0x0, sum = 4
8920 11:13:15.269450 best_step = 15
8921 11:13:15.269517
8922 11:13:15.269578 ==
8923 11:13:15.271902 Dram Type= 6, Freq= 0, CH_1, rank 1
8924 11:13:15.278921 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8925 11:13:15.279022 ==
8926 11:13:15.279091 RX Vref Scan: 0
8927 11:13:15.279154
8928 11:13:15.282335 RX Vref 0 -> 0, step: 1
8929 11:13:15.282421
8930 11:13:15.285804 RX Delay 19 -> 252, step: 4
8931 11:13:15.289031 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8932 11:13:15.291847 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8933 11:13:15.298903 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8934 11:13:15.302378 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8935 11:13:15.305147 iDelay=195, Bit 4, Center 130 (75 ~ 186) 112
8936 11:13:15.308830 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
8937 11:13:15.311992 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
8938 11:13:15.318534 iDelay=195, Bit 7, Center 128 (75 ~ 182) 108
8939 11:13:15.321679 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8940 11:13:15.324749 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
8941 11:13:15.328582 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8942 11:13:15.331736 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8943 11:13:15.338330 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8944 11:13:15.341518 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8945 11:13:15.345092 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8946 11:13:15.347793 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8947 11:13:15.348189 ==
8948 11:13:15.351716 Dram Type= 6, Freq= 0, CH_1, rank 1
8949 11:13:15.357723 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8950 11:13:15.358174 ==
8951 11:13:15.358505 DQS Delay:
8952 11:13:15.361154 DQS0 = 0, DQS1 = 0
8953 11:13:15.361520 DQM Delay:
8954 11:13:15.364765 DQM0 = 131, DQM1 = 128
8955 11:13:15.365225 DQ Delay:
8956 11:13:15.367692 DQ0 =134, DQ1 =130, DQ2 =120, DQ3 =128
8957 11:13:15.371192 DQ4 =130, DQ5 =142, DQ6 =140, DQ7 =128
8958 11:13:15.374614 DQ8 =114, DQ9 =118, DQ10 =130, DQ11 =120
8959 11:13:15.377361 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =138
8960 11:13:15.377858
8961 11:13:15.378227
8962 11:13:15.378575
8963 11:13:15.380778 [DramC_TX_OE_Calibration] TA2
8964 11:13:15.384305 Original DQ_B0 (3 6) =30, OEN = 27
8965 11:13:15.387718 Original DQ_B1 (3 6) =30, OEN = 27
8966 11:13:15.390932 24, 0x0, End_B0=24 End_B1=24
8967 11:13:15.394472 25, 0x0, End_B0=25 End_B1=25
8968 11:13:15.394851 26, 0x0, End_B0=26 End_B1=26
8969 11:13:15.397740 27, 0x0, End_B0=27 End_B1=27
8970 11:13:15.400678 28, 0x0, End_B0=28 End_B1=28
8971 11:13:15.404092 29, 0x0, End_B0=29 End_B1=29
8972 11:13:15.407700 30, 0x0, End_B0=30 End_B1=30
8973 11:13:15.408406 31, 0x4141, End_B0=30 End_B1=30
8974 11:13:15.410481 Byte0 end_step=30 best_step=27
8975 11:13:15.414065 Byte1 end_step=30 best_step=27
8976 11:13:15.417242 Byte0 TX OE(2T, 0.5T) = (3, 3)
8977 11:13:15.420491 Byte1 TX OE(2T, 0.5T) = (3, 3)
8978 11:13:15.421170
8979 11:13:15.421755
8980 11:13:15.426945 [DQSOSCAuto] RK1, (LSB)MR18= 0xc1b, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 403 ps
8981 11:13:15.430255 CH1 RK1: MR19=303, MR18=C1B
8982 11:13:15.436988 CH1_RK1: MR19=0x303, MR18=0xC1B, DQSOSC=396, MR23=63, INC=23, DEC=15
8983 11:13:15.440063 [RxdqsGatingPostProcess] freq 1600
8984 11:13:15.446812 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8985 11:13:15.449723 best DQS0 dly(2T, 0.5T) = (1, 1)
8986 11:13:15.450028 best DQS1 dly(2T, 0.5T) = (1, 1)
8987 11:13:15.453114 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8988 11:13:15.456171 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8989 11:13:15.459545 best DQS0 dly(2T, 0.5T) = (1, 1)
8990 11:13:15.462983 best DQS1 dly(2T, 0.5T) = (1, 1)
8991 11:13:15.466279 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8992 11:13:15.469688 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8993 11:13:15.472964 Pre-setting of DQS Precalculation
8994 11:13:15.479721 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8995 11:13:15.486147 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
8996 11:13:15.492471 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
8997 11:13:15.492797
8998 11:13:15.493056
8999 11:13:15.495805 [Calibration Summary] 3200 Mbps
9000 11:13:15.496150 CH 0, Rank 0
9001 11:13:15.499104 SW Impedance : PASS
9002 11:13:15.502688 DUTY Scan : NO K
9003 11:13:15.503015 ZQ Calibration : PASS
9004 11:13:15.505570 Jitter Meter : NO K
9005 11:13:15.509152 CBT Training : PASS
9006 11:13:15.509569 Write leveling : PASS
9007 11:13:15.512530 RX DQS gating : PASS
9008 11:13:15.515418 RX DQ/DQS(RDDQC) : PASS
9009 11:13:15.515842 TX DQ/DQS : PASS
9010 11:13:15.518804 RX DATLAT : PASS
9011 11:13:15.522115 RX DQ/DQS(Engine): PASS
9012 11:13:15.522589 TX OE : PASS
9013 11:13:15.522974 All Pass.
9014 11:13:15.525385
9015 11:13:15.525857 CH 0, Rank 1
9016 11:13:15.529174 SW Impedance : PASS
9017 11:13:15.529645 DUTY Scan : NO K
9018 11:13:15.532375 ZQ Calibration : PASS
9019 11:13:15.535639 Jitter Meter : NO K
9020 11:13:15.536122 CBT Training : PASS
9021 11:13:15.538451 Write leveling : PASS
9022 11:13:15.538908 RX DQS gating : PASS
9023 11:13:15.541698 RX DQ/DQS(RDDQC) : PASS
9024 11:13:15.545110 TX DQ/DQS : PASS
9025 11:13:15.545232 RX DATLAT : PASS
9026 11:13:15.548417 RX DQ/DQS(Engine): PASS
9027 11:13:15.551552 TX OE : PASS
9028 11:13:15.551634 All Pass.
9029 11:13:15.551698
9030 11:13:15.551757 CH 1, Rank 0
9031 11:13:15.554896 SW Impedance : PASS
9032 11:13:15.558341 DUTY Scan : NO K
9033 11:13:15.558423 ZQ Calibration : PASS
9034 11:13:15.561175 Jitter Meter : NO K
9035 11:13:15.565141 CBT Training : PASS
9036 11:13:15.565562 Write leveling : PASS
9037 11:13:15.568389 RX DQS gating : PASS
9038 11:13:15.571664 RX DQ/DQS(RDDQC) : PASS
9039 11:13:15.572229 TX DQ/DQS : PASS
9040 11:13:15.574985 RX DATLAT : PASS
9041 11:13:15.577968 RX DQ/DQS(Engine): PASS
9042 11:13:15.578408 TX OE : PASS
9043 11:13:15.581535 All Pass.
9044 11:13:15.582060
9045 11:13:15.582404 CH 1, Rank 1
9046 11:13:15.584577 SW Impedance : PASS
9047 11:13:15.585077 DUTY Scan : NO K
9048 11:13:15.587964 ZQ Calibration : PASS
9049 11:13:15.591435 Jitter Meter : NO K
9050 11:13:15.591857 CBT Training : PASS
9051 11:13:15.594784 Write leveling : PASS
9052 11:13:15.597544 RX DQS gating : PASS
9053 11:13:15.597984 RX DQ/DQS(RDDQC) : PASS
9054 11:13:15.601089 TX DQ/DQS : PASS
9055 11:13:15.604437 RX DATLAT : PASS
9056 11:13:15.604935 RX DQ/DQS(Engine): PASS
9057 11:13:15.607550 TX OE : PASS
9058 11:13:15.608005 All Pass.
9059 11:13:15.608389
9060 11:13:15.611036 DramC Write-DBI on
9061 11:13:15.614392 PER_BANK_REFRESH: Hybrid Mode
9062 11:13:15.614867 TX_TRACKING: ON
9063 11:13:15.624292 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9064 11:13:15.631016 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9065 11:13:15.637412 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9066 11:13:15.640224 [FAST_K] Save calibration result to emmc
9067 11:13:15.643563 sync common calibartion params.
9068 11:13:15.647077 sync cbt_mode0:1, 1:1
9069 11:13:15.650210 dram_init: ddr_geometry: 2
9070 11:13:15.650304 dram_init: ddr_geometry: 2
9071 11:13:15.653257 dram_init: ddr_geometry: 2
9072 11:13:15.656678 0:dram_rank_size:100000000
9073 11:13:15.660152 1:dram_rank_size:100000000
9074 11:13:15.663291 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9075 11:13:15.666950 DFS_SHUFFLE_HW_MODE: ON
9076 11:13:15.670172 dramc_set_vcore_voltage set vcore to 725000
9077 11:13:15.673385 Read voltage for 1600, 0
9078 11:13:15.673547 Vio18 = 0
9079 11:13:15.676881 Vcore = 725000
9080 11:13:15.677032 Vdram = 0
9081 11:13:15.677152 Vddq = 0
9082 11:13:15.677263 Vmddr = 0
9083 11:13:15.679749 switch to 3200 Mbps bootup
9084 11:13:15.683226 [DramcRunTimeConfig]
9085 11:13:15.683398 PHYPLL
9086 11:13:15.686708 DPM_CONTROL_AFTERK: ON
9087 11:13:15.687058 PER_BANK_REFRESH: ON
9088 11:13:15.689680 REFRESH_OVERHEAD_REDUCTION: ON
9089 11:13:15.693232 CMD_PICG_NEW_MODE: OFF
9090 11:13:15.693472 XRTWTW_NEW_MODE: ON
9091 11:13:15.696545 XRTRTR_NEW_MODE: ON
9092 11:13:15.696859 TX_TRACKING: ON
9093 11:13:15.699979 RDSEL_TRACKING: OFF
9094 11:13:15.703030 DQS Precalculation for DVFS: ON
9095 11:13:15.703410 RX_TRACKING: OFF
9096 11:13:15.706297 HW_GATING DBG: ON
9097 11:13:15.706753 ZQCS_ENABLE_LP4: ON
9098 11:13:15.709669 RX_PICG_NEW_MODE: ON
9099 11:13:15.710086 TX_PICG_NEW_MODE: ON
9100 11:13:15.713171 ENABLE_RX_DCM_DPHY: ON
9101 11:13:15.716551 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9102 11:13:15.719546 DUMMY_READ_FOR_TRACKING: OFF
9103 11:13:15.719962 !!! SPM_CONTROL_AFTERK: OFF
9104 11:13:15.722916 !!! SPM could not control APHY
9105 11:13:15.726398 IMPEDANCE_TRACKING: ON
9106 11:13:15.726814 TEMP_SENSOR: ON
9107 11:13:15.730076 HW_SAVE_FOR_SR: OFF
9108 11:13:15.733123 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9109 11:13:15.736455 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9110 11:13:15.736873 Read ODT Tracking: ON
9111 11:13:15.739544 Refresh Rate DeBounce: ON
9112 11:13:15.743052 DFS_NO_QUEUE_FLUSH: ON
9113 11:13:15.745981 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9114 11:13:15.746404 ENABLE_DFS_RUNTIME_MRW: OFF
9115 11:13:15.749339 DDR_RESERVE_NEW_MODE: ON
9116 11:13:15.752724 MR_CBT_SWITCH_FREQ: ON
9117 11:13:15.753143 =========================
9118 11:13:15.773081 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9119 11:13:15.776144 dram_init: ddr_geometry: 2
9120 11:13:15.794226 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9121 11:13:15.797583 dram_init: dram init end (result: 0)
9122 11:13:15.804633 DRAM-K: Full calibration passed in 24397 msecs
9123 11:13:15.807533 MRC: failed to locate region type 0.
9124 11:13:15.807949 DRAM rank0 size:0x100000000,
9125 11:13:15.810875 DRAM rank1 size=0x100000000
9126 11:13:15.820975 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9127 11:13:15.827236 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9128 11:13:15.837228 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9129 11:13:15.843542 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9130 11:13:15.843986 DRAM rank0 size:0x100000000,
9131 11:13:15.846996 DRAM rank1 size=0x100000000
9132 11:13:15.847413 CBMEM:
9133 11:13:15.850244 IMD: root @ 0xfffff000 254 entries.
9134 11:13:15.853693 IMD: root @ 0xffffec00 62 entries.
9135 11:13:15.860010 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9136 11:13:15.863300 WARNING: RO_VPD is uninitialized or empty.
9137 11:13:15.866553 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9138 11:13:15.874754 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9139 11:13:15.887509 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9140 11:13:15.898747 BS: romstage times (exec / console): total (unknown) / 23933 ms
9141 11:13:15.899267
9142 11:13:15.899811
9143 11:13:15.908729 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9144 11:13:15.911990 ARM64: Exception handlers installed.
9145 11:13:15.915129 ARM64: Testing exception
9146 11:13:15.918430 ARM64: Done test exception
9147 11:13:15.918850 Enumerating buses...
9148 11:13:15.921634 Show all devs... Before device enumeration.
9149 11:13:15.924440 Root Device: enabled 1
9150 11:13:15.928008 CPU_CLUSTER: 0: enabled 1
9151 11:13:15.928129 CPU: 00: enabled 1
9152 11:13:15.931357 Compare with tree...
9153 11:13:15.931438 Root Device: enabled 1
9154 11:13:15.934794 CPU_CLUSTER: 0: enabled 1
9155 11:13:15.937693 CPU: 00: enabled 1
9156 11:13:15.937774 Root Device scanning...
9157 11:13:15.940975 scan_static_bus for Root Device
9158 11:13:15.944402 CPU_CLUSTER: 0 enabled
9159 11:13:15.947838 scan_static_bus for Root Device done
9160 11:13:15.951259 scan_bus: bus Root Device finished in 8 msecs
9161 11:13:15.951332 done
9162 11:13:15.957374 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9163 11:13:15.960649 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9164 11:13:15.967336 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9165 11:13:15.973972 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9166 11:13:15.974055 Allocating resources...
9167 11:13:15.977439 Reading resources...
9168 11:13:15.980636 Root Device read_resources bus 0 link: 0
9169 11:13:15.983872 DRAM rank0 size:0x100000000,
9170 11:13:15.983970 DRAM rank1 size=0x100000000
9171 11:13:15.990378 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9172 11:13:15.990460 CPU: 00 missing read_resources
9173 11:13:15.996593 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9174 11:13:15.999887 Root Device read_resources bus 0 link: 0 done
9175 11:13:16.003271 Done reading resources.
9176 11:13:16.006773 Show resources in subtree (Root Device)...After reading.
9177 11:13:16.010095 Root Device child on link 0 CPU_CLUSTER: 0
9178 11:13:16.012960 CPU_CLUSTER: 0 child on link 0 CPU: 00
9179 11:13:16.023267 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9180 11:13:16.023351 CPU: 00
9181 11:13:16.029581 Root Device assign_resources, bus 0 link: 0
9182 11:13:16.032955 CPU_CLUSTER: 0 missing set_resources
9183 11:13:16.036308 Root Device assign_resources, bus 0 link: 0 done
9184 11:13:16.039669 Done setting resources.
9185 11:13:16.042562 Show resources in subtree (Root Device)...After assigning values.
9186 11:13:16.049242 Root Device child on link 0 CPU_CLUSTER: 0
9187 11:13:16.052628 CPU_CLUSTER: 0 child on link 0 CPU: 00
9188 11:13:16.059327 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9189 11:13:16.062641 CPU: 00
9190 11:13:16.062739 Done allocating resources.
9191 11:13:16.069237 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9192 11:13:16.072525 Enabling resources...
9193 11:13:16.072606 done.
9194 11:13:16.075701 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9195 11:13:16.078901 Initializing devices...
9196 11:13:16.078983 Root Device init
9197 11:13:16.082256 init hardware done!
9198 11:13:16.085576 0x00000018: ctrlr->caps
9199 11:13:16.085660 52.000 MHz: ctrlr->f_max
9200 11:13:16.088825 0.400 MHz: ctrlr->f_min
9201 11:13:16.092169 0x40ff8080: ctrlr->voltages
9202 11:13:16.092252 sclk: 390625
9203 11:13:16.092319 Bus Width = 1
9204 11:13:16.095534 sclk: 390625
9205 11:13:16.095614 Bus Width = 1
9206 11:13:16.098883 Early init status = 3
9207 11:13:16.102193 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9208 11:13:16.106550 in-header: 03 fc 00 00 01 00 00 00
9209 11:13:16.109874 in-data: 00
9210 11:13:16.113377 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9211 11:13:16.118495 in-header: 03 fd 00 00 00 00 00 00
9212 11:13:16.122550 in-data:
9213 11:13:16.125055 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9214 11:13:16.129722 in-header: 03 fc 00 00 01 00 00 00
9215 11:13:16.133220 in-data: 00
9216 11:13:16.136042 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9217 11:13:16.142203 in-header: 03 fd 00 00 00 00 00 00
9218 11:13:16.145150 in-data:
9219 11:13:16.148523 [SSUSB] Setting up USB HOST controller...
9220 11:13:16.151974 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9221 11:13:16.155374 [SSUSB] phy power-on done.
9222 11:13:16.158353 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9223 11:13:16.165002 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9224 11:13:16.168156 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9225 11:13:16.174815 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9226 11:13:16.182023 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9227 11:13:16.188538 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9228 11:13:16.194946 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9229 11:13:16.201822 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9230 11:13:16.205209 SPM: binary array size = 0x9dc
9231 11:13:16.207978 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9232 11:13:16.214645 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9233 11:13:16.221370 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9234 11:13:16.228353 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9235 11:13:16.231317 configure_display: Starting display init
9236 11:13:16.265896 anx7625_power_on_init: Init interface.
9237 11:13:16.269237 anx7625_disable_pd_protocol: Disabled PD feature.
9238 11:13:16.271991 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9239 11:13:16.299766 anx7625_start_dp_work: Secure OCM version=00
9240 11:13:16.303085 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9241 11:13:16.318127 sp_tx_get_edid_block: EDID Block = 1
9242 11:13:16.420466 Extracted contents:
9243 11:13:16.423366 header: 00 ff ff ff ff ff ff 00
9244 11:13:16.426763 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9245 11:13:16.430312 version: 01 04
9246 11:13:16.433681 basic params: 95 1f 11 78 0a
9247 11:13:16.436760 chroma info: 76 90 94 55 54 90 27 21 50 54
9248 11:13:16.440177 established: 00 00 00
9249 11:13:16.446755 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9250 11:13:16.453064 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9251 11:13:16.456499 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9252 11:13:16.463478 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9253 11:13:16.470348 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9254 11:13:16.473241 extensions: 00
9255 11:13:16.473727 checksum: fb
9256 11:13:16.474073
9257 11:13:16.479839 Manufacturer: IVO Model 57d Serial Number 0
9258 11:13:16.480432 Made week 0 of 2020
9259 11:13:16.482984 EDID version: 1.4
9260 11:13:16.483404 Digital display
9261 11:13:16.486551 6 bits per primary color channel
9262 11:13:16.489765 DisplayPort interface
9263 11:13:16.490185 Maximum image size: 31 cm x 17 cm
9264 11:13:16.493188 Gamma: 220%
9265 11:13:16.493607 Check DPMS levels
9266 11:13:16.499637 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9267 11:13:16.503071 First detailed timing is preferred timing
9268 11:13:16.503522 Established timings supported:
9269 11:13:16.506442 Standard timings supported:
9270 11:13:16.509462 Detailed timings
9271 11:13:16.512760 Hex of detail: 383680a07038204018303c0035ae10000019
9272 11:13:16.519452 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9273 11:13:16.522928 0780 0798 07c8 0820 hborder 0
9274 11:13:16.526237 0438 043b 0447 0458 vborder 0
9275 11:13:16.529877 -hsync -vsync
9276 11:13:16.530471 Did detailed timing
9277 11:13:16.535784 Hex of detail: 000000000000000000000000000000000000
9278 11:13:16.539637 Manufacturer-specified data, tag 0
9279 11:13:16.542858 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9280 11:13:16.546160 ASCII string: InfoVision
9281 11:13:16.548846 Hex of detail: 000000fe00523134304e574635205248200a
9282 11:13:16.552234 ASCII string: R140NWF5 RH
9283 11:13:16.552648 Checksum
9284 11:13:16.555795 Checksum: 0xfb (valid)
9285 11:13:16.559265 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9286 11:13:16.562101 DSI data_rate: 832800000 bps
9287 11:13:16.568874 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9288 11:13:16.572287 anx7625_parse_edid: pixelclock(138800).
9289 11:13:16.575690 hactive(1920), hsync(48), hfp(24), hbp(88)
9290 11:13:16.578833 vactive(1080), vsync(12), vfp(3), vbp(17)
9291 11:13:16.582230 anx7625_dsi_config: config dsi.
9292 11:13:16.588493 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9293 11:13:16.602800 anx7625_dsi_config: success to config DSI
9294 11:13:16.605868 anx7625_dp_start: MIPI phy setup OK.
9295 11:13:16.609051 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9296 11:13:16.612461 mtk_ddp_mode_set invalid vrefresh 60
9297 11:13:16.616099 main_disp_path_setup
9298 11:13:16.616615 ovl_layer_smi_id_en
9299 11:13:16.618976 ovl_layer_smi_id_en
9300 11:13:16.619395 ccorr_config
9301 11:13:16.619931 aal_config
9302 11:13:16.622282 gamma_config
9303 11:13:16.622767 postmask_config
9304 11:13:16.625639 dither_config
9305 11:13:16.629097 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9306 11:13:16.635712 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9307 11:13:16.638570 Root Device init finished in 555 msecs
9308 11:13:16.641948 CPU_CLUSTER: 0 init
9309 11:13:16.648717 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9310 11:13:16.655537 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9311 11:13:16.655951 APU_MBOX 0x190000b0 = 0x10001
9312 11:13:16.658319 APU_MBOX 0x190001b0 = 0x10001
9313 11:13:16.662081 APU_MBOX 0x190005b0 = 0x10001
9314 11:13:16.664880 APU_MBOX 0x190006b0 = 0x10001
9315 11:13:16.671680 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9316 11:13:16.681237 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9317 11:13:16.693639 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9318 11:13:16.700115 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9319 11:13:16.712396 read SPI 0x61c74 0xe8ef: 6411 us, 9301 KB/s, 74.408 Mbps
9320 11:13:16.721204 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9321 11:13:16.724489 CPU_CLUSTER: 0 init finished in 81 msecs
9322 11:13:16.727933 Devices initialized
9323 11:13:16.730982 Show all devs... After init.
9324 11:13:16.731480 Root Device: enabled 1
9325 11:13:16.734832 CPU_CLUSTER: 0: enabled 1
9326 11:13:16.737678 CPU: 00: enabled 1
9327 11:13:16.741112 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9328 11:13:16.744507 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9329 11:13:16.747569 ELOG: NV offset 0x57f000 size 0x1000
9330 11:13:16.754914 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9331 11:13:16.761130 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9332 11:13:16.764469 ELOG: Event(17) added with size 13 at 2023-06-05 11:13:16 UTC
9333 11:13:16.770909 out: cmd=0x121: 03 db 21 01 00 00 00 00
9334 11:13:16.774417 in-header: 03 45 00 00 2c 00 00 00
9335 11:13:16.783944 in-data: 1a 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9336 11:13:16.790969 ELOG: Event(A1) added with size 10 at 2023-06-05 11:13:16 UTC
9337 11:13:16.797482 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9338 11:13:16.803971 ELOG: Event(A0) added with size 9 at 2023-06-05 11:13:16 UTC
9339 11:13:16.807140 elog_add_boot_reason: Logged dev mode boot
9340 11:13:16.813639 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9341 11:13:16.814052 Finalize devices...
9342 11:13:16.816908 Devices finalized
9343 11:13:16.820137 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9344 11:13:16.823637 Writing coreboot table at 0xffe64000
9345 11:13:16.826884 0. 000000000010a000-0000000000113fff: RAMSTAGE
9346 11:13:16.833681 1. 0000000040000000-00000000400fffff: RAM
9347 11:13:16.836882 2. 0000000040100000-000000004032afff: RAMSTAGE
9348 11:13:16.840285 3. 000000004032b000-00000000545fffff: RAM
9349 11:13:16.843147 4. 0000000054600000-000000005465ffff: BL31
9350 11:13:16.846619 5. 0000000054660000-00000000ffe63fff: RAM
9351 11:13:16.853250 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9352 11:13:16.856672 7. 0000000100000000-000000023fffffff: RAM
9353 11:13:16.859959 Passing 5 GPIOs to payload:
9354 11:13:16.862965 NAME | PORT | POLARITY | VALUE
9355 11:13:16.869868 EC in RW | 0x000000aa | low | undefined
9356 11:13:16.872708 EC interrupt | 0x00000005 | low | undefined
9357 11:13:16.879542 TPM interrupt | 0x000000ab | high | undefined
9358 11:13:16.882811 SD card detect | 0x00000011 | high | undefined
9359 11:13:16.886099 speaker enable | 0x00000093 | high | undefined
9360 11:13:16.889525 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9361 11:13:16.892913 in-header: 03 f9 00 00 02 00 00 00
9362 11:13:16.896343 in-data: 02 00
9363 11:13:16.899644 ADC[4]: Raw value=903694 ID=7
9364 11:13:16.902976 ADC[3]: Raw value=213916 ID=1
9365 11:13:16.903387 RAM Code: 0x71
9366 11:13:16.906285 ADC[6]: Raw value=74630 ID=0
9367 11:13:16.909525 ADC[5]: Raw value=213546 ID=1
9368 11:13:16.909939 SKU Code: 0x1
9369 11:13:16.915932 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a53a
9370 11:13:16.916375 coreboot table: 964 bytes.
9371 11:13:16.919289 IMD ROOT 0. 0xfffff000 0x00001000
9372 11:13:16.922563 IMD SMALL 1. 0xffffe000 0x00001000
9373 11:13:16.926108 RO MCACHE 2. 0xffffc000 0x00001104
9374 11:13:16.929284 CONSOLE 3. 0xfff7c000 0x00080000
9375 11:13:16.932305 FMAP 4. 0xfff7b000 0x00000452
9376 11:13:16.935881 TIME STAMP 5. 0xfff7a000 0x00000910
9377 11:13:16.938927 VBOOT WORK 6. 0xfff66000 0x00014000
9378 11:13:16.942124 RAMOOPS 7. 0xffe66000 0x00100000
9379 11:13:16.945694 COREBOOT 8. 0xffe64000 0x00002000
9380 11:13:16.948890 IMD small region:
9381 11:13:16.952238 IMD ROOT 0. 0xffffec00 0x00000400
9382 11:13:16.955721 VPD 1. 0xffffeba0 0x0000004c
9383 11:13:16.958534 MMC STATUS 2. 0xffffeb80 0x00000004
9384 11:13:16.965585 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9385 11:13:16.966025 Probing TPM: done!
9386 11:13:16.971947 Connected to device vid:did:rid of 1ae0:0028:00
9387 11:13:16.979017 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9388 11:13:16.982512 Initialized TPM device CR50 revision 0
9389 11:13:16.986109 Checking cr50 for pending updates
9390 11:13:16.991789 Reading cr50 TPM mode
9391 11:13:16.999678 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9392 11:13:17.006316 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9393 11:13:17.046578 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9394 11:13:17.049917 Checking segment from ROM address 0x40100000
9395 11:13:17.053385 Checking segment from ROM address 0x4010001c
9396 11:13:17.059500 Loading segment from ROM address 0x40100000
9397 11:13:17.060104 code (compression=0)
9398 11:13:17.069646 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9399 11:13:17.076612 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9400 11:13:17.077115 it's not compressed!
9401 11:13:17.083639 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9402 11:13:17.089568 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9403 11:13:17.107279 Loading segment from ROM address 0x4010001c
9404 11:13:17.107773 Entry Point 0x80000000
9405 11:13:17.110418 Loaded segments
9406 11:13:17.113847 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9407 11:13:17.120151 Jumping to boot code at 0x80000000(0xffe64000)
9408 11:13:17.126647 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9409 11:13:17.133756 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9410 11:13:17.141377 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9411 11:13:17.144742 Checking segment from ROM address 0x40100000
9412 11:13:17.148061 Checking segment from ROM address 0x4010001c
9413 11:13:17.154768 Loading segment from ROM address 0x40100000
9414 11:13:17.155195 code (compression=1)
9415 11:13:17.160902 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9416 11:13:17.171065 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9417 11:13:17.171712 using LZMA
9418 11:13:17.179590 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9419 11:13:17.186484 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9420 11:13:17.189995 Loading segment from ROM address 0x4010001c
9421 11:13:17.190460 Entry Point 0x54601000
9422 11:13:17.192773 Loaded segments
9423 11:13:17.196135 NOTICE: MT8192 bl31_setup
9424 11:13:17.203452 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9425 11:13:17.206957 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9426 11:13:17.209758 WARNING: region 0:
9427 11:13:17.213154 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9428 11:13:17.213632 WARNING: region 1:
9429 11:13:17.219684 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9430 11:13:17.222956 WARNING: region 2:
9431 11:13:17.226677 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9432 11:13:17.230068 WARNING: region 3:
9433 11:13:17.233273 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9434 11:13:17.236441 WARNING: region 4:
9435 11:13:17.242979 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9436 11:13:17.243396 WARNING: region 5:
9437 11:13:17.246711 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9438 11:13:17.250154 WARNING: region 6:
9439 11:13:17.253137 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9440 11:13:17.256376 WARNING: region 7:
9441 11:13:17.259538 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9442 11:13:17.266262 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9443 11:13:17.269716 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9444 11:13:17.273267 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9445 11:13:17.279886 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9446 11:13:17.283067 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9447 11:13:17.289384 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9448 11:13:17.292603 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9449 11:13:17.296003 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9450 11:13:17.302862 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9451 11:13:17.306043 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9452 11:13:17.309441 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9453 11:13:17.316258 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9454 11:13:17.319541 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9455 11:13:17.326053 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9456 11:13:17.329387 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9457 11:13:17.332554 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9458 11:13:17.339101 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9459 11:13:17.342402 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9460 11:13:17.345895 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9461 11:13:17.352347 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9462 11:13:17.356183 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9463 11:13:17.362348 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9464 11:13:17.365495 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9465 11:13:17.368998 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9466 11:13:17.376091 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9467 11:13:17.379382 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9468 11:13:17.385858 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9469 11:13:17.389058 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9470 11:13:17.392476 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9471 11:13:17.399474 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9472 11:13:17.402653 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9473 11:13:17.409213 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9474 11:13:17.412430 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9475 11:13:17.415934 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9476 11:13:17.419630 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9477 11:13:17.425634 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9478 11:13:17.429006 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9479 11:13:17.432510 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9480 11:13:17.436157 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9481 11:13:17.442285 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9482 11:13:17.445478 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9483 11:13:17.448897 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9484 11:13:17.452356 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9485 11:13:17.459232 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9486 11:13:17.462109 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9487 11:13:17.465317 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9488 11:13:17.469057 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9489 11:13:17.475399 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9490 11:13:17.478918 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9491 11:13:17.485144 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9492 11:13:17.488498 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9493 11:13:17.492086 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9494 11:13:17.498871 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9495 11:13:17.502384 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9496 11:13:17.508594 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9497 11:13:17.512173 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9498 11:13:17.518716 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9499 11:13:17.522332 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9500 11:13:17.525027 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9501 11:13:17.532066 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9502 11:13:17.535534 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9503 11:13:17.541915 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9504 11:13:17.545185 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9505 11:13:17.552066 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9506 11:13:17.555264 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9507 11:13:17.561508 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9508 11:13:17.564581 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9509 11:13:17.568159 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9510 11:13:17.574561 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9511 11:13:17.578079 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9512 11:13:17.584714 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9513 11:13:17.588012 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9514 11:13:17.594897 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9515 11:13:17.597720 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9516 11:13:17.604471 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9517 11:13:17.607959 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9518 11:13:17.611164 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9519 11:13:17.617935 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9520 11:13:17.621104 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9521 11:13:17.627470 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9522 11:13:17.630924 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9523 11:13:17.638121 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9524 11:13:17.640727 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9525 11:13:17.647859 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9526 11:13:17.651226 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9527 11:13:17.654594 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9528 11:13:17.660929 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9529 11:13:17.664167 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9530 11:13:17.670847 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9531 11:13:17.674088 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9532 11:13:17.680813 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9533 11:13:17.684197 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9534 11:13:17.687540 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9535 11:13:17.693758 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9536 11:13:17.696903 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9537 11:13:17.704004 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9538 11:13:17.707308 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9539 11:13:17.710842 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9540 11:13:17.716949 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9541 11:13:17.720406 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9542 11:13:17.723786 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9543 11:13:17.730772 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9544 11:13:17.733558 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9545 11:13:17.737006 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9546 11:13:17.743379 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9547 11:13:17.747431 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9548 11:13:17.753995 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9549 11:13:17.757245 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9550 11:13:17.760700 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9551 11:13:17.766748 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9552 11:13:17.770496 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9553 11:13:17.777218 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9554 11:13:17.780489 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9555 11:13:17.783717 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9556 11:13:17.790429 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9557 11:13:17.793852 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9558 11:13:17.797075 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9559 11:13:17.803925 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9560 11:13:17.806754 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9561 11:13:17.810100 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9562 11:13:17.813560 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9563 11:13:17.820242 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9564 11:13:17.823819 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9565 11:13:17.827290 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9566 11:13:17.833365 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9567 11:13:17.836876 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9568 11:13:17.840257 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9569 11:13:17.846783 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9570 11:13:17.850052 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9571 11:13:17.856547 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9572 11:13:17.859953 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9573 11:13:17.863152 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9574 11:13:17.869790 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9575 11:13:17.873388 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9576 11:13:17.880141 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9577 11:13:17.883173 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9578 11:13:17.886441 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9579 11:13:17.893130 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9580 11:13:17.896525 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9581 11:13:17.903173 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9582 11:13:17.906329 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9583 11:13:17.909797 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9584 11:13:17.916117 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9585 11:13:17.919597 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9586 11:13:17.922829 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9587 11:13:17.929972 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9588 11:13:17.933062 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9589 11:13:17.939935 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9590 11:13:17.942939 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9591 11:13:17.946310 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9592 11:13:17.952869 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9593 11:13:17.956161 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9594 11:13:17.962735 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9595 11:13:17.966159 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9596 11:13:17.969281 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9597 11:13:17.976433 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9598 11:13:17.979600 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9599 11:13:17.986274 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9600 11:13:17.989947 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9601 11:13:17.992846 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9602 11:13:17.999189 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9603 11:13:18.002470 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9604 11:13:18.009095 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9605 11:13:18.012623 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9606 11:13:18.015820 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9607 11:13:18.022172 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9608 11:13:18.025510 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9609 11:13:18.032381 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9610 11:13:18.035230 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9611 11:13:18.038684 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9612 11:13:18.045432 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9613 11:13:18.048763 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9614 11:13:18.055481 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9615 11:13:18.058767 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9616 11:13:18.061633 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9617 11:13:18.068316 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9618 11:13:18.071677 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9619 11:13:18.078032 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9620 11:13:18.081377 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9621 11:13:18.085030 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9622 11:13:18.091268 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9623 11:13:18.094609 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9624 11:13:18.101255 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9625 11:13:18.104701 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9626 11:13:18.108084 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9627 11:13:18.114496 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9628 11:13:18.118204 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9629 11:13:18.124344 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9630 11:13:18.127774 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9631 11:13:18.134211 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9632 11:13:18.137632 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9633 11:13:18.140960 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9634 11:13:18.147519 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9635 11:13:18.151019 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9636 11:13:18.157129 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9637 11:13:18.160424 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9638 11:13:18.167013 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9639 11:13:18.170242 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9640 11:13:18.173481 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9641 11:13:18.180101 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9642 11:13:18.183408 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9643 11:13:18.190015 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9644 11:13:18.193697 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9645 11:13:18.199817 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9646 11:13:18.203309 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9647 11:13:18.206635 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9648 11:13:18.213366 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9649 11:13:18.216825 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9650 11:13:18.223471 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9651 11:13:18.226471 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9652 11:13:18.233197 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9653 11:13:18.235893 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9654 11:13:18.239375 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9655 11:13:18.246298 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9656 11:13:18.249874 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9657 11:13:18.255499 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9658 11:13:18.258916 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9659 11:13:18.265731 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9660 11:13:18.268880 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9661 11:13:18.272574 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9662 11:13:18.279188 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9663 11:13:18.282353 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9664 11:13:18.288743 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9665 11:13:18.291949 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9666 11:13:18.298522 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9667 11:13:18.302008 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9668 11:13:18.305365 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9669 11:13:18.311603 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9670 11:13:18.315046 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9671 11:13:18.318558 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9672 11:13:18.325075 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9673 11:13:18.328501 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9674 11:13:18.331737 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9675 11:13:18.334524 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9676 11:13:18.341615 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9677 11:13:18.344581 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9678 11:13:18.351607 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9679 11:13:18.354199 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9680 11:13:18.357707 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9681 11:13:18.364144 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9682 11:13:18.367712 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9683 11:13:18.374287 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9684 11:13:18.377082 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9685 11:13:18.380362 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9686 11:13:18.387140 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9687 11:13:18.390349 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9688 11:13:18.393763 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9689 11:13:18.400220 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9690 11:13:18.403555 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9691 11:13:18.410498 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9692 11:13:18.413925 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9693 11:13:18.417109 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9694 11:13:18.423415 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9695 11:13:18.426861 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9696 11:13:18.430194 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9697 11:13:18.437016 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9698 11:13:18.440348 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9699 11:13:18.446552 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9700 11:13:18.450177 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9701 11:13:18.453301 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9702 11:13:18.459654 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9703 11:13:18.463053 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9704 11:13:18.469684 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9705 11:13:18.472854 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9706 11:13:18.476186 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9707 11:13:18.482914 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9708 11:13:18.485988 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9709 11:13:18.488984 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9710 11:13:18.495560 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9711 11:13:18.499320 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9712 11:13:18.502420 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9713 11:13:18.505806 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9714 11:13:18.511849 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9715 11:13:18.515142 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9716 11:13:18.518940 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9717 11:13:18.521884 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9718 11:13:18.528854 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9719 11:13:18.531764 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9720 11:13:18.535395 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9721 11:13:18.538285 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9722 11:13:18.545124 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9723 11:13:18.548595 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9724 11:13:18.551900 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9725 11:13:18.558215 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9726 11:13:18.561574 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9727 11:13:18.568227 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9728 11:13:18.571563 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9729 11:13:18.577862 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9730 11:13:18.581168 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9731 11:13:18.584553 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9732 11:13:18.591119 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9733 11:13:18.594476 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9734 11:13:18.601010 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9735 11:13:18.604508 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9736 11:13:18.611054 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9737 11:13:18.614379 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9738 11:13:18.617781 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9739 11:13:18.624564 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9740 11:13:18.627419 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9741 11:13:18.634396 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9742 11:13:18.637711 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9743 11:13:18.640906 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9744 11:13:18.647426 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9745 11:13:18.650316 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9746 11:13:18.657488 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9747 11:13:18.660682 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9748 11:13:18.666843 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9749 11:13:18.670235 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9750 11:13:18.673725 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9751 11:13:18.680295 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9752 11:13:18.683450 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9753 11:13:18.689867 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9754 11:13:18.693074 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9755 11:13:18.696408 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9756 11:13:18.703084 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9757 11:13:18.706551 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9758 11:13:18.713060 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9759 11:13:18.715884 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9760 11:13:18.722686 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9761 11:13:18.726012 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9762 11:13:18.732391 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9763 11:13:18.735842 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9764 11:13:18.739388 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9765 11:13:18.745606 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9766 11:13:18.748875 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9767 11:13:18.755127 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9768 11:13:18.758660 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9769 11:13:18.765428 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9770 11:13:18.768300 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9771 11:13:18.771888 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9772 11:13:18.778731 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9773 11:13:18.781913 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9774 11:13:18.788446 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9775 11:13:18.791795 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9776 11:13:18.794844 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9777 11:13:18.801551 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9778 11:13:18.804804 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9779 11:13:18.811514 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9780 11:13:18.814771 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9781 11:13:18.817951 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9782 11:13:18.824306 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9783 11:13:18.827982 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9784 11:13:18.834606 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9785 11:13:18.837521 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9786 11:13:18.844268 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9787 11:13:18.847310 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9788 11:13:18.850848 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9789 11:13:18.857338 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9790 11:13:18.860727 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9791 11:13:18.867021 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9792 11:13:18.870487 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9793 11:13:18.876858 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9794 11:13:18.880284 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9795 11:13:18.883725 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9796 11:13:18.889888 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9797 11:13:18.893110 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9798 11:13:18.900153 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9799 11:13:18.903430 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9800 11:13:18.909824 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9801 11:13:18.913173 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9802 11:13:18.919783 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9803 11:13:18.923114 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9804 11:13:18.926337 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9805 11:13:18.933013 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9806 11:13:18.936379 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9807 11:13:18.943035 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9808 11:13:18.945955 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9809 11:13:18.952747 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9810 11:13:18.956110 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9811 11:13:18.959551 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9812 11:13:18.966047 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9813 11:13:18.969352 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9814 11:13:18.975663 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9815 11:13:18.979325 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9816 11:13:18.985723 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9817 11:13:18.989134 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9818 11:13:18.995498 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9819 11:13:18.999186 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9820 11:13:19.005803 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9821 11:13:19.009006 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9822 11:13:19.012356 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9823 11:13:19.019041 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9824 11:13:19.022423 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9825 11:13:19.028739 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9826 11:13:19.031928 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9827 11:13:19.038733 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9828 11:13:19.042005 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9829 11:13:19.048465 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9830 11:13:19.051437 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9831 11:13:19.058249 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9832 11:13:19.061567 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9833 11:13:19.064875 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9834 11:13:19.071082 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9835 11:13:19.074584 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9836 11:13:19.081420 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9837 11:13:19.084227 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9838 11:13:19.091171 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9839 11:13:19.094581 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9840 11:13:19.100935 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9841 11:13:19.104427 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9842 11:13:19.110676 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9843 11:13:19.113935 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9844 11:13:19.117117 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9845 11:13:19.123648 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9846 11:13:19.126990 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9847 11:13:19.133930 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9848 11:13:19.137102 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9849 11:13:19.143909 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9850 11:13:19.146951 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9851 11:13:19.153485 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9852 11:13:19.157051 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9853 11:13:19.163090 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9854 11:13:19.166259 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9855 11:13:19.173141 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9856 11:13:19.176716 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9857 11:13:19.182807 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9858 11:13:19.186208 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9859 11:13:19.193040 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9860 11:13:19.195920 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9861 11:13:19.202807 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9862 11:13:19.206145 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9863 11:13:19.212821 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9864 11:13:19.216089 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9865 11:13:19.222508 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9866 11:13:19.225602 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9867 11:13:19.232524 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9868 11:13:19.235858 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9869 11:13:19.242269 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9870 11:13:19.245538 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9871 11:13:19.252507 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9872 11:13:19.255211 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9873 11:13:19.261729 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9874 11:13:19.265033 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9875 11:13:19.271748 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9876 11:13:19.275154 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9877 11:13:19.278086 INFO: [APUAPC] vio 0
9878 11:13:19.281521 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9879 11:13:19.287895 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9880 11:13:19.291337 INFO: [APUAPC] D0_APC_0: 0x400510
9881 11:13:19.291421 INFO: [APUAPC] D0_APC_1: 0x0
9882 11:13:19.294872 INFO: [APUAPC] D0_APC_2: 0x1540
9883 11:13:19.297697 INFO: [APUAPC] D0_APC_3: 0x0
9884 11:13:19.300999 INFO: [APUAPC] D1_APC_0: 0xffffffff
9885 11:13:19.304490 INFO: [APUAPC] D1_APC_1: 0xffffffff
9886 11:13:19.307752 INFO: [APUAPC] D1_APC_2: 0x3fffff
9887 11:13:19.311142 INFO: [APUAPC] D1_APC_3: 0x0
9888 11:13:19.314604 INFO: [APUAPC] D2_APC_0: 0xffffffff
9889 11:13:19.317427 INFO: [APUAPC] D2_APC_1: 0xffffffff
9890 11:13:19.321286 INFO: [APUAPC] D2_APC_2: 0x3fffff
9891 11:13:19.324045 INFO: [APUAPC] D2_APC_3: 0x0
9892 11:13:19.327674 INFO: [APUAPC] D3_APC_0: 0xffffffff
9893 11:13:19.330889 INFO: [APUAPC] D3_APC_1: 0xffffffff
9894 11:13:19.334106 INFO: [APUAPC] D3_APC_2: 0x3fffff
9895 11:13:19.337307 INFO: [APUAPC] D3_APC_3: 0x0
9896 11:13:19.340895 INFO: [APUAPC] D4_APC_0: 0xffffffff
9897 11:13:19.344235 INFO: [APUAPC] D4_APC_1: 0xffffffff
9898 11:13:19.347488 INFO: [APUAPC] D4_APC_2: 0x3fffff
9899 11:13:19.350665 INFO: [APUAPC] D4_APC_3: 0x0
9900 11:13:19.353592 INFO: [APUAPC] D5_APC_0: 0xffffffff
9901 11:13:19.357030 INFO: [APUAPC] D5_APC_1: 0xffffffff
9902 11:13:19.360567 INFO: [APUAPC] D5_APC_2: 0x3fffff
9903 11:13:19.363753 INFO: [APUAPC] D5_APC_3: 0x0
9904 11:13:19.367237 INFO: [APUAPC] D6_APC_0: 0xffffffff
9905 11:13:19.370133 INFO: [APUAPC] D6_APC_1: 0xffffffff
9906 11:13:19.373374 INFO: [APUAPC] D6_APC_2: 0x3fffff
9907 11:13:19.376694 INFO: [APUAPC] D6_APC_3: 0x0
9908 11:13:19.380068 INFO: [APUAPC] D7_APC_0: 0xffffffff
9909 11:13:19.383687 INFO: [APUAPC] D7_APC_1: 0xffffffff
9910 11:13:19.387029 INFO: [APUAPC] D7_APC_2: 0x3fffff
9911 11:13:19.390103 INFO: [APUAPC] D7_APC_3: 0x0
9912 11:13:19.394826 INFO: [APUAPC] D8_APC_0: 0xffffffff
9913 11:13:19.396956 INFO: [APUAPC] D8_APC_1: 0xffffffff
9914 11:13:19.400784 INFO: [APUAPC] D8_APC_2: 0x3fffff
9915 11:13:19.403589 INFO: [APUAPC] D8_APC_3: 0x0
9916 11:13:19.406891 INFO: [APUAPC] D9_APC_0: 0xffffffff
9917 11:13:19.410288 INFO: [APUAPC] D9_APC_1: 0xffffffff
9918 11:13:19.413945 INFO: [APUAPC] D9_APC_2: 0x3fffff
9919 11:13:19.416756 INFO: [APUAPC] D9_APC_3: 0x0
9920 11:13:19.420148 INFO: [APUAPC] D10_APC_0: 0xffffffff
9921 11:13:19.423657 INFO: [APUAPC] D10_APC_1: 0xffffffff
9922 11:13:19.427004 INFO: [APUAPC] D10_APC_2: 0x3fffff
9923 11:13:19.429784 INFO: [APUAPC] D10_APC_3: 0x0
9924 11:13:19.433734 INFO: [APUAPC] D11_APC_0: 0xffffffff
9925 11:13:19.436928 INFO: [APUAPC] D11_APC_1: 0xffffffff
9926 11:13:19.439952 INFO: [APUAPC] D11_APC_2: 0x3fffff
9927 11:13:19.443104 INFO: [APUAPC] D11_APC_3: 0x0
9928 11:13:19.446720 INFO: [APUAPC] D12_APC_0: 0xffffffff
9929 11:13:19.449883 INFO: [APUAPC] D12_APC_1: 0xffffffff
9930 11:13:19.453136 INFO: [APUAPC] D12_APC_2: 0x3fffff
9931 11:13:19.456274 INFO: [APUAPC] D12_APC_3: 0x0
9932 11:13:19.459623 INFO: [APUAPC] D13_APC_0: 0xffffffff
9933 11:13:19.462809 INFO: [APUAPC] D13_APC_1: 0xffffffff
9934 11:13:19.466494 INFO: [APUAPC] D13_APC_2: 0x3fffff
9935 11:13:19.469269 INFO: [APUAPC] D13_APC_3: 0x0
9936 11:13:19.472632 INFO: [APUAPC] D14_APC_0: 0xffffffff
9937 11:13:19.476166 INFO: [APUAPC] D14_APC_1: 0xffffffff
9938 11:13:19.479138 INFO: [APUAPC] D14_APC_2: 0x3fffff
9939 11:13:19.482476 INFO: [APUAPC] D14_APC_3: 0x0
9940 11:13:19.486055 INFO: [APUAPC] D15_APC_0: 0xffffffff
9941 11:13:19.489392 INFO: [APUAPC] D15_APC_1: 0xffffffff
9942 11:13:19.492308 INFO: [APUAPC] D15_APC_2: 0x3fffff
9943 11:13:19.495759 INFO: [APUAPC] D15_APC_3: 0x0
9944 11:13:19.499160 INFO: [APUAPC] APC_CON: 0x4
9945 11:13:19.502627 INFO: [NOCDAPC] D0_APC_0: 0x0
9946 11:13:19.505588 INFO: [NOCDAPC] D0_APC_1: 0x0
9947 11:13:19.509016 INFO: [NOCDAPC] D1_APC_0: 0x0
9948 11:13:19.512613 INFO: [NOCDAPC] D1_APC_1: 0xfff
9949 11:13:19.515353 INFO: [NOCDAPC] D2_APC_0: 0x0
9950 11:13:19.515844 INFO: [NOCDAPC] D2_APC_1: 0xfff
9951 11:13:19.518722 INFO: [NOCDAPC] D3_APC_0: 0x0
9952 11:13:19.522065 INFO: [NOCDAPC] D3_APC_1: 0xfff
9953 11:13:19.525158 INFO: [NOCDAPC] D4_APC_0: 0x0
9954 11:13:19.528532 INFO: [NOCDAPC] D4_APC_1: 0xfff
9955 11:13:19.531375 INFO: [NOCDAPC] D5_APC_0: 0x0
9956 11:13:19.534648 INFO: [NOCDAPC] D5_APC_1: 0xfff
9957 11:13:19.538159 INFO: [NOCDAPC] D6_APC_0: 0x0
9958 11:13:19.541667 INFO: [NOCDAPC] D6_APC_1: 0xfff
9959 11:13:19.545005 INFO: [NOCDAPC] D7_APC_0: 0x0
9960 11:13:19.548069 INFO: [NOCDAPC] D7_APC_1: 0xfff
9961 11:13:19.548178 INFO: [NOCDAPC] D8_APC_0: 0x0
9962 11:13:19.551393 INFO: [NOCDAPC] D8_APC_1: 0xfff
9963 11:13:19.554944 INFO: [NOCDAPC] D9_APC_0: 0x0
9964 11:13:19.557969 INFO: [NOCDAPC] D9_APC_1: 0xfff
9965 11:13:19.561340 INFO: [NOCDAPC] D10_APC_0: 0x0
9966 11:13:19.564432 INFO: [NOCDAPC] D10_APC_1: 0xfff
9967 11:13:19.567870 INFO: [NOCDAPC] D11_APC_0: 0x0
9968 11:13:19.571449 INFO: [NOCDAPC] D11_APC_1: 0xfff
9969 11:13:19.574559 INFO: [NOCDAPC] D12_APC_0: 0x0
9970 11:13:19.577639 INFO: [NOCDAPC] D12_APC_1: 0xfff
9971 11:13:19.581477 INFO: [NOCDAPC] D13_APC_0: 0x0
9972 11:13:19.584519 INFO: [NOCDAPC] D13_APC_1: 0xfff
9973 11:13:19.588003 INFO: [NOCDAPC] D14_APC_0: 0x0
9974 11:13:19.591470 INFO: [NOCDAPC] D14_APC_1: 0xfff
9975 11:13:19.594425 INFO: [NOCDAPC] D15_APC_0: 0x0
9976 11:13:19.597711 INFO: [NOCDAPC] D15_APC_1: 0xfff
9977 11:13:19.597835 INFO: [NOCDAPC] APC_CON: 0x4
9978 11:13:19.601287 INFO: [APUAPC] set_apusys_apc done
9979 11:13:19.604665 INFO: [DEVAPC] devapc_init done
9980 11:13:19.611396 INFO: GICv3 without legacy support detected.
9981 11:13:19.614248 INFO: ARM GICv3 driver initialized in EL3
9982 11:13:19.617588 INFO: Maximum SPI INTID supported: 639
9983 11:13:19.621025 INFO: BL31: Initializing runtime services
9984 11:13:19.627766 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9985 11:13:19.630962 INFO: SPM: enable CPC mode
9986 11:13:19.634404 INFO: mcdi ready for mcusys-off-idle and system suspend
9987 11:13:19.640901 INFO: BL31: Preparing for EL3 exit to normal world
9988 11:13:19.644330 INFO: Entry point address = 0x80000000
9989 11:13:19.644917 INFO: SPSR = 0x8
9990 11:13:19.651515
9991 11:13:19.651978
9992 11:13:19.652341
9993 11:13:19.654728 Starting depthcharge on Spherion...
9994 11:13:19.655150
9995 11:13:19.655530 Wipe memory regions:
9996 11:13:19.655846
9997 11:13:19.658333 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
9998 11:13:19.658906 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
9999 11:13:19.659426 Setting prompt string to ['asurada:']
10000 11:13:19.659829 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10001 11:13:19.660615 [0x00000040000000, 0x00000054600000)
10002 11:13:19.779839
10003 11:13:19.779997 [0x00000054660000, 0x00000080000000)
10004 11:13:20.040958
10005 11:13:20.041522 [0x000000821a7280, 0x000000ffe64000)
10006 11:13:20.785586
10007 11:13:20.786108 [0x00000100000000, 0x00000240000000)
10008 11:13:22.674593
10009 11:13:22.677801 Initializing XHCI USB controller at 0x11200000.
10010 11:13:23.715613
10011 11:13:23.718998 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10012 11:13:23.719435
10013 11:13:23.719759
10014 11:13:23.720095
10015 11:13:23.720814 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10017 11:13:23.821772 asurada: tftpboot 192.168.201.1 10591271/tftp-deploy-9g1e0xbk/kernel/image.itb 10591271/tftp-deploy-9g1e0xbk/kernel/cmdline
10018 11:13:23.822323 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10019 11:13:23.822739 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10020 11:13:23.827481 tftpboot 192.168.201.1 10591271/tftp-deploy-9g1e0xbk/kernel/image.ittp-deploy-9g1e0xbk/kernel/cmdline
10021 11:13:23.827907
10022 11:13:23.828311 Waiting for link
10023 11:13:23.987705
10024 11:13:23.988262 R8152: Initializing
10025 11:13:23.988606
10026 11:13:23.990825 Version 6 (ocp_data = 5c30)
10027 11:13:23.991315
10028 11:13:23.994011 R8152: Done initializing
10029 11:13:23.994482
10030 11:13:23.994926 Adding net device
10031 11:13:25.863072
10032 11:13:25.863561 done.
10033 11:13:25.863960
10034 11:13:25.864324 MAC: 00:24:32:30:7c:7b
10035 11:13:25.864819
10036 11:13:25.865906 Sending DHCP discover... done.
10037 11:13:25.866548
10038 11:13:25.869276 Waiting for reply... done.
10039 11:13:25.869725
10040 11:13:25.872197 Sending DHCP request... done.
10041 11:13:25.872701
10042 11:13:25.873047 Waiting for reply... done.
10043 11:13:25.873432
10044 11:13:25.875569 My ip is 192.168.201.14
10045 11:13:25.875974
10046 11:13:25.879023 The DHCP server ip is 192.168.201.1
10047 11:13:25.879469
10048 11:13:25.882313 TFTP server IP predefined by user: 192.168.201.1
10049 11:13:25.882736
10050 11:13:25.888969 Bootfile predefined by user: 10591271/tftp-deploy-9g1e0xbk/kernel/image.itb
10051 11:13:25.889447
10052 11:13:25.892815 Sending tftp read request... done.
10053 11:13:25.893283
10054 11:13:25.900918 Waiting for the transfer...
10055 11:13:25.901480
10056 11:13:26.495119 00000000 ################################################################
10057 11:13:26.495254
10058 11:13:27.059726 00080000 ################################################################
10059 11:13:27.059860
10060 11:13:27.603356 00100000 ################################################################
10061 11:13:27.603488
10062 11:13:28.213394 00180000 ################################################################
10063 11:13:28.213958
10064 11:13:28.848484 00200000 ################################################################
10065 11:13:28.849070
10066 11:13:29.429785 00280000 ################################################################
10067 11:13:29.429922
10068 11:13:30.039421 00300000 ################################################################
10069 11:13:30.039559
10070 11:13:30.584567 00380000 ################################################################
10071 11:13:30.584699
10072 11:13:31.150638 00400000 ################################################################
10073 11:13:31.150798
10074 11:13:31.733286 00480000 ################################################################
10075 11:13:31.733445
10076 11:13:32.296233 00500000 ################################################################
10077 11:13:32.296368
10078 11:13:32.871589 00580000 ################################################################
10079 11:13:32.871719
10080 11:13:33.452443 00600000 ################################################################
10081 11:13:33.452621
10082 11:13:34.022399 00680000 ################################################################
10083 11:13:34.022536
10084 11:13:34.563054 00700000 ################################################################
10085 11:13:34.563186
10086 11:13:35.107809 00780000 ################################################################
10087 11:13:35.107947
10088 11:13:35.716101 00800000 ################################################################
10089 11:13:35.716384
10090 11:13:36.340501 00880000 ################################################################
10091 11:13:36.340998
10092 11:13:36.977504 00900000 ################################################################
10093 11:13:36.977639
10094 11:13:37.553382 00980000 ################################################################
10095 11:13:37.553534
10096 11:13:38.114362 00a00000 ################################################################
10097 11:13:38.114530
10098 11:13:38.681408 00a80000 ################################################################
10099 11:13:38.681551
10100 11:13:39.256760 00b00000 ################################################################
10101 11:13:39.256891
10102 11:13:39.802622 00b80000 ################################################################
10103 11:13:39.802758
10104 11:13:40.363391 00c00000 ################################################################
10105 11:13:40.363667
10106 11:13:40.977130 00c80000 ################################################################
10107 11:13:40.977267
10108 11:13:41.597128 00d00000 ################################################################
10109 11:13:41.597266
10110 11:13:42.129236 00d80000 ################################################################
10111 11:13:42.129402
10112 11:13:42.714746 00e00000 ################################################################
10113 11:13:42.714887
10114 11:13:43.286716 00e80000 ################################################################
10115 11:13:43.286854
10116 11:13:43.876162 00f00000 ################################################################
10117 11:13:43.876300
10118 11:13:44.445866 00f80000 ################################################################
10119 11:13:44.446002
10120 11:13:45.002994 01000000 ################################################################
10121 11:13:45.003126
10122 11:13:45.573195 01080000 ################################################################
10123 11:13:45.573332
10124 11:13:46.122226 01100000 ################################################################
10125 11:13:46.122360
10126 11:13:46.695065 01180000 ################################################################
10127 11:13:46.695198
10128 11:13:47.275895 01200000 ################################################################
10129 11:13:47.276467
10130 11:13:47.850569 01280000 ################################################################
10131 11:13:47.850705
10132 11:13:48.429909 01300000 ################################################################
10133 11:13:48.430048
10134 11:13:48.980915 01380000 ################################################################
10135 11:13:48.981051
10136 11:13:49.552403 01400000 ################################################################
10137 11:13:49.552538
10138 11:13:50.156130 01480000 ################################################################
10139 11:13:50.156269
10140 11:13:50.752927 01500000 ################################################################
10141 11:13:50.753065
10142 11:13:51.312381 01580000 ################################################################
10143 11:13:51.312515
10144 11:13:51.862597 01600000 ################################################################
10145 11:13:51.862757
10146 11:13:52.436697 01680000 ################################################################
10147 11:13:52.437198
10148 11:13:53.090507 01700000 ################################################################
10149 11:13:53.091012
10150 11:13:53.706858 01780000 ################################################################
10151 11:13:53.707017
10152 11:13:54.297541 01800000 ################################################################
10153 11:13:54.298152
10154 11:13:54.895883 01880000 ################################################################
10155 11:13:54.896406
10156 11:13:55.520857 01900000 ################################################################
10157 11:13:55.521018
10158 11:13:56.192908 01980000 ################################################################
10159 11:13:56.193049
10160 11:13:56.825828 01a00000 ################################################################
10161 11:13:56.826312
10162 11:13:57.393389 01a80000 ################################################################
10163 11:13:57.393582
10164 11:13:58.010841 01b00000 ################################################################
10165 11:13:58.011342
10166 11:13:58.676877 01b80000 ################################################################
10167 11:13:58.677518
10168 11:13:59.349040 01c00000 ################################################################
10169 11:13:59.349620
10170 11:14:00.010395 01c80000 ################################################################
10171 11:14:00.010933
10172 11:14:00.663292 01d00000 ################################################################
10173 11:14:00.663933
10174 11:14:01.214677 01d80000 ###################################################### done.
10175 11:14:01.215196
10176 11:14:01.218039 The bootfile was 31367654 bytes long.
10177 11:14:01.218465
10178 11:14:01.220626 Sending tftp read request... done.
10179 11:14:01.221124
10180 11:14:01.225083 Waiting for the transfer...
10181 11:14:01.225508
10182 11:14:01.225840 00000000 # done.
10183 11:14:01.226162
10184 11:14:01.231306 Command line loaded dynamically from TFTP file: 10591271/tftp-deploy-9g1e0xbk/kernel/cmdline
10185 11:14:01.234696
10186 11:14:01.244632 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10187 11:14:01.245059
10188 11:14:01.245391 Loading FIT.
10189 11:14:01.245704
10190 11:14:01.247860 Image ramdisk-1 has 21232676 bytes.
10191 11:14:01.248340
10192 11:14:01.251268 Image fdt-1 has 46924 bytes.
10193 11:14:01.251689
10194 11:14:01.254415 Image kernel-1 has 10086024 bytes.
10195 11:14:01.254835
10196 11:14:01.264591 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10197 11:14:01.265022
10198 11:14:01.280722 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10199 11:14:01.281166
10200 11:14:01.284100 Choosing best match conf-1 for compat google,spherion-rev2.
10201 11:14:01.287836
10202 11:14:01.290674 Connected to device vid:did:rid of 1ae0:0028:00
10203 11:14:01.302617
10204 11:14:01.306147 tpm_get_response: command 0x17b, return code 0x0
10205 11:14:01.306668
10206 11:14:01.309756 ec_init: CrosEC protocol v3 supported (256, 248)
10207 11:14:01.313602
10208 11:14:01.316839 tpm_cleanup: add release locality here.
10209 11:14:01.317399
10210 11:14:01.317741 Shutting down all USB controllers.
10211 11:14:01.319922
10212 11:14:01.320534 Removing current net device
10213 11:14:01.320934
10214 11:14:01.326473 Exiting depthcharge with code 4 at timestamp: 70893013
10215 11:14:01.326896
10216 11:14:01.329756 LZMA decompressing kernel-1 to 0x821a6718
10217 11:14:01.330177
10218 11:14:01.332881 LZMA decompressing kernel-1 to 0x40000000
10219 11:14:02.600265
10220 11:14:02.600780 jumping to kernel
10221 11:14:02.602153 end: 2.2.4 bootloader-commands (duration 00:00:43) [common]
10222 11:14:02.602652 start: 2.2.5 auto-login-action (timeout 00:03:42) [common]
10223 11:14:02.603038 Setting prompt string to ['Linux version [0-9]']
10224 11:14:02.603384 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10225 11:14:02.603736 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10226 11:14:02.682167
10227 11:14:02.685426 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10228 11:14:02.689104 start: 2.2.5.1 login-action (timeout 00:03:42) [common]
10229 11:14:02.689568 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10230 11:14:02.690007 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10231 11:14:02.690380 Using line separator: #'\n'#
10232 11:14:02.690726 No login prompt set.
10233 11:14:02.691089 Parsing kernel messages
10234 11:14:02.691562 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10235 11:14:02.692173 [login-action] Waiting for messages, (timeout 00:03:42)
10236 11:14:02.708205 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1609115-arm64-gcc-10-defconfig-arm64-chromebook-dplkv) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 10:57:14 UTC 2023
10237 11:14:02.711720 [ 0.000000] random: crng init done
10238 11:14:02.718187 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10239 11:14:02.718637 [ 0.000000] efi: UEFI not found.
10240 11:14:02.728057 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10241 11:14:02.734283 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10242 11:14:02.744306 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10243 11:14:02.754330 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10244 11:14:02.760414 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10245 11:14:02.767049 [ 0.000000] printk: bootconsole [mtk8250] enabled
10246 11:14:02.774068 [ 0.000000] NUMA: No NUMA configuration found
10247 11:14:02.780166 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10248 11:14:02.783609 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10249 11:14:02.786863 [ 0.000000] Zone ranges:
10250 11:14:02.793484 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10251 11:14:02.796545 [ 0.000000] DMA32 empty
10252 11:14:02.803431 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10253 11:14:02.806526 [ 0.000000] Movable zone start for each node
10254 11:14:02.810322 [ 0.000000] Early memory node ranges
10255 11:14:02.816225 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10256 11:14:02.822653 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10257 11:14:02.829401 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10258 11:14:02.836520 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10259 11:14:02.842735 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10260 11:14:02.849049 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10261 11:14:02.905602 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10262 11:14:02.911897 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10263 11:14:02.918813 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10264 11:14:02.921676 [ 0.000000] psci: probing for conduit method from DT.
10265 11:14:02.928802 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10266 11:14:02.931709 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10267 11:14:02.938244 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10268 11:14:02.942206 [ 0.000000] psci: SMC Calling Convention v1.2
10269 11:14:02.948477 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10270 11:14:02.951489 [ 0.000000] Detected VIPT I-cache on CPU0
10271 11:14:02.958594 [ 0.000000] CPU features: detected: GIC system register CPU interface
10272 11:14:02.965168 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10273 11:14:02.971864 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10274 11:14:02.978640 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10275 11:14:02.988369 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10276 11:14:02.994865 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10277 11:14:02.998512 [ 0.000000] alternatives: applying boot alternatives
10278 11:14:03.004575 [ 0.000000] Fallback order for Node 0: 0
10279 11:14:03.011765 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10280 11:14:03.015071 [ 0.000000] Policy zone: Normal
10281 11:14:03.024533 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10282 11:14:03.037956 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10283 11:14:03.048668 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10284 11:14:03.057639 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10285 11:14:03.064679 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10286 11:14:03.067746 <6>[ 0.000000] software IO TLB: area num 8.
10287 11:14:03.124240 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10288 11:14:03.273926 <6>[ 0.000000] Memory: 7952208K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 400560K reserved, 32768K cma-reserved)
10289 11:14:03.280593 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10290 11:14:03.287127 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10291 11:14:03.290542 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10292 11:14:03.296701 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10293 11:14:03.303090 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10294 11:14:03.306860 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10295 11:14:03.316621 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10296 11:14:03.323321 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10297 11:14:03.329734 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10298 11:14:03.336269 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10299 11:14:03.339422 <6>[ 0.000000] GICv3: 608 SPIs implemented
10300 11:14:03.342754 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10301 11:14:03.349290 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10302 11:14:03.352531 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10303 11:14:03.359214 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10304 11:14:03.372725 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10305 11:14:03.385449 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10306 11:14:03.391980 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10307 11:14:03.400268 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10308 11:14:03.413212 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10309 11:14:03.420438 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10310 11:14:03.426844 <6>[ 0.009223] Console: colour dummy device 80x25
10311 11:14:03.436530 <6>[ 0.013979] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10312 11:14:03.443198 <6>[ 0.024422] pid_max: default: 32768 minimum: 301
10313 11:14:03.446342 <6>[ 0.029295] LSM: Security Framework initializing
10314 11:14:03.453402 <6>[ 0.034234] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10315 11:14:03.462822 <6>[ 0.042049] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10316 11:14:03.472904 <6>[ 0.051468] cblist_init_generic: Setting adjustable number of callback queues.
10317 11:14:03.477170 <6>[ 0.058920] cblist_init_generic: Setting shift to 3 and lim to 1.
10318 11:14:03.482804 <6>[ 0.065298] cblist_init_generic: Setting shift to 3 and lim to 1.
10319 11:14:03.489363 <6>[ 0.071706] rcu: Hierarchical SRCU implementation.
10320 11:14:03.496312 <6>[ 0.076751] rcu: Max phase no-delay instances is 1000.
10321 11:14:03.502731 <6>[ 0.083770] EFI services will not be available.
10322 11:14:03.505762 <6>[ 0.088745] smp: Bringing up secondary CPUs ...
10323 11:14:03.513725 <6>[ 0.093797] Detected VIPT I-cache on CPU1
10324 11:14:03.520493 <6>[ 0.093869] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10325 11:14:03.527031 <6>[ 0.093899] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10326 11:14:03.530195 <6>[ 0.094236] Detected VIPT I-cache on CPU2
10327 11:14:03.540319 <6>[ 0.094288] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10328 11:14:03.546874 <6>[ 0.094305] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10329 11:14:03.550147 <6>[ 0.094563] Detected VIPT I-cache on CPU3
10330 11:14:03.556512 <6>[ 0.094609] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10331 11:14:03.563054 <6>[ 0.094623] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10332 11:14:03.569923 <6>[ 0.094926] CPU features: detected: Spectre-v4
10333 11:14:03.573020 <6>[ 0.094932] CPU features: detected: Spectre-BHB
10334 11:14:03.576622 <6>[ 0.094938] Detected PIPT I-cache on CPU4
10335 11:14:03.583171 <6>[ 0.094994] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10336 11:14:03.589980 <6>[ 0.095011] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10337 11:14:03.596117 <6>[ 0.095304] Detected PIPT I-cache on CPU5
10338 11:14:03.602976 <6>[ 0.095368] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10339 11:14:03.609681 <6>[ 0.095385] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10340 11:14:03.612583 <6>[ 0.095667] Detected PIPT I-cache on CPU6
10341 11:14:03.619222 <6>[ 0.095733] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10342 11:14:03.628932 <6>[ 0.095749] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10343 11:14:03.632498 <6>[ 0.096046] Detected PIPT I-cache on CPU7
10344 11:14:03.639064 <6>[ 0.096111] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10345 11:14:03.645547 <6>[ 0.096127] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10346 11:14:03.648771 <6>[ 0.096175] smp: Brought up 1 node, 8 CPUs
10347 11:14:03.655500 <6>[ 0.237445] SMP: Total of 8 processors activated.
10348 11:14:03.661714 <6>[ 0.242366] CPU features: detected: 32-bit EL0 Support
10349 11:14:03.668949 <6>[ 0.247729] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10350 11:14:03.675150 <6>[ 0.256583] CPU features: detected: Common not Private translations
10351 11:14:03.681598 <6>[ 0.263059] CPU features: detected: CRC32 instructions
10352 11:14:03.688260 <6>[ 0.268443] CPU features: detected: RCpc load-acquire (LDAPR)
10353 11:14:03.691695 <6>[ 0.274439] CPU features: detected: LSE atomic instructions
10354 11:14:03.698273 <6>[ 0.280221] CPU features: detected: Privileged Access Never
10355 11:14:03.704943 <6>[ 0.286036] CPU features: detected: RAS Extension Support
10356 11:14:03.711258 <6>[ 0.291679] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10357 11:14:03.714591 <6>[ 0.298899] CPU: All CPU(s) started at EL2
10358 11:14:03.721028 <6>[ 0.303242] alternatives: applying system-wide alternatives
10359 11:14:03.731656 <6>[ 0.313935] devtmpfs: initialized
10360 11:14:03.746994 <6>[ 0.323010] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10361 11:14:03.753544 <6>[ 0.332976] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10362 11:14:03.760147 <6>[ 0.341201] pinctrl core: initialized pinctrl subsystem
10363 11:14:03.763565 <6>[ 0.347870] DMI not present or invalid.
10364 11:14:03.770253 <6>[ 0.352279] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10365 11:14:03.780009 <6>[ 0.359182] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10366 11:14:03.786916 <6>[ 0.366766] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10367 11:14:03.796296 <6>[ 0.375002] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10368 11:14:03.799749 <6>[ 0.383248] audit: initializing netlink subsys (disabled)
10369 11:14:03.810042 <5>[ 0.388947] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10370 11:14:03.816414 <6>[ 0.389658] thermal_sys: Registered thermal governor 'step_wise'
10371 11:14:03.822941 <6>[ 0.396913] thermal_sys: Registered thermal governor 'power_allocator'
10372 11:14:03.826605 <6>[ 0.403168] cpuidle: using governor menu
10373 11:14:03.832674 <6>[ 0.414131] NET: Registered PF_QIPCRTR protocol family
10374 11:14:03.839659 <6>[ 0.419611] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10375 11:14:03.846170 <6>[ 0.426714] ASID allocator initialised with 32768 entries
10376 11:14:03.849109 <6>[ 0.433290] Serial: AMBA PL011 UART driver
10377 11:14:03.859672 <4>[ 0.441960] Trying to register duplicate clock ID: 134
10378 11:14:03.915785 <6>[ 0.501374] KASLR enabled
10379 11:14:03.929810 <6>[ 0.509167] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10380 11:14:03.936512 <6>[ 0.516181] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10381 11:14:03.943064 <6>[ 0.522671] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10382 11:14:03.949531 <6>[ 0.529677] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10383 11:14:03.956091 <6>[ 0.536165] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10384 11:14:03.962740 <6>[ 0.543170] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10385 11:14:03.969253 <6>[ 0.549659] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10386 11:14:03.976213 <6>[ 0.556665] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10387 11:14:03.979497 <6>[ 0.564206] ACPI: Interpreter disabled.
10388 11:14:03.987829 <6>[ 0.570601] iommu: Default domain type: Translated
10389 11:14:03.994344 <6>[ 0.575714] iommu: DMA domain TLB invalidation policy: strict mode
10390 11:14:03.997431 <5>[ 0.582369] SCSI subsystem initialized
10391 11:14:04.004374 <6>[ 0.586533] usbcore: registered new interface driver usbfs
10392 11:14:04.010631 <6>[ 0.592268] usbcore: registered new interface driver hub
10393 11:14:04.014374 <6>[ 0.597819] usbcore: registered new device driver usb
10394 11:14:04.021257 <6>[ 0.603900] pps_core: LinuxPPS API ver. 1 registered
10395 11:14:04.031072 <6>[ 0.609095] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10396 11:14:04.034133 <6>[ 0.618441] PTP clock support registered
10397 11:14:04.037818 <6>[ 0.622677] EDAC MC: Ver: 3.0.0
10398 11:14:04.045352 <6>[ 0.627810] FPGA manager framework
10399 11:14:04.051774 <6>[ 0.631493] Advanced Linux Sound Architecture Driver Initialized.
10400 11:14:04.054939 <6>[ 0.638270] vgaarb: loaded
10401 11:14:04.061921 <6>[ 0.641435] clocksource: Switched to clocksource arch_sys_counter
10402 11:14:04.065025 <5>[ 0.647875] VFS: Disk quotas dquot_6.6.0
10403 11:14:04.071718 <6>[ 0.652059] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10404 11:14:04.074554 <6>[ 0.659247] pnp: PnP ACPI: disabled
10405 11:14:04.083752 <6>[ 0.665993] NET: Registered PF_INET protocol family
10406 11:14:04.093498 <6>[ 0.671593] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10407 11:14:04.104619 <6>[ 0.683907] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10408 11:14:04.114799 <6>[ 0.692723] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10409 11:14:04.120885 <6>[ 0.700693] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10410 11:14:04.131457 <6>[ 0.709392] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10411 11:14:04.137345 <6>[ 0.719137] TCP: Hash tables configured (established 65536 bind 65536)
10412 11:14:04.144290 <6>[ 0.725992] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10413 11:14:04.153979 <6>[ 0.733194] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10414 11:14:04.160673 <6>[ 0.740895] NET: Registered PF_UNIX/PF_LOCAL protocol family
10415 11:14:04.167121 <6>[ 0.747064] RPC: Registered named UNIX socket transport module.
10416 11:14:04.170826 <6>[ 0.753222] RPC: Registered udp transport module.
10417 11:14:04.177305 <6>[ 0.758156] RPC: Registered tcp transport module.
10418 11:14:04.183756 <6>[ 0.763088] RPC: Registered tcp NFSv4.1 backchannel transport module.
10419 11:14:04.186836 <6>[ 0.769756] PCI: CLS 0 bytes, default 64
10420 11:14:04.190549 <6>[ 0.774105] Unpacking initramfs...
10421 11:14:04.206995 <6>[ 0.786044] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10422 11:14:04.216709 <6>[ 0.794710] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10423 11:14:04.220224 <6>[ 0.803555] kvm [1]: IPA Size Limit: 40 bits
10424 11:14:04.226638 <6>[ 0.808086] kvm [1]: GICv3: no GICV resource entry
10425 11:14:04.230147 <6>[ 0.813107] kvm [1]: disabling GICv2 emulation
10426 11:14:04.237007 <6>[ 0.817796] kvm [1]: GIC system register CPU interface enabled
10427 11:14:04.240241 <6>[ 0.823955] kvm [1]: vgic interrupt IRQ18
10428 11:14:04.246356 <6>[ 0.828320] kvm [1]: VHE mode initialized successfully
10429 11:14:04.252827 <5>[ 0.834732] Initialise system trusted keyrings
10430 11:14:04.259869 <6>[ 0.839551] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10431 11:14:04.267036 <6>[ 0.849627] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10432 11:14:04.273840 <5>[ 0.856026] NFS: Registering the id_resolver key type
10433 11:14:04.276906 <5>[ 0.861337] Key type id_resolver registered
10434 11:14:04.283798 <5>[ 0.865755] Key type id_legacy registered
10435 11:14:04.290130 <6>[ 0.870036] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10436 11:14:04.296897 <6>[ 0.876958] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10437 11:14:04.303091 <6>[ 0.884680] 9p: Installing v9fs 9p2000 file system support
10438 11:14:04.339946 <5>[ 0.922572] Key type asymmetric registered
10439 11:14:04.343633 <5>[ 0.926902] Asymmetric key parser 'x509' registered
10440 11:14:04.353046 <6>[ 0.932049] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10441 11:14:04.356671 <6>[ 0.939663] io scheduler mq-deadline registered
10442 11:14:04.359752 <6>[ 0.944449] io scheduler kyber registered
10443 11:14:04.378651 <6>[ 0.961319] EINJ: ACPI disabled.
10444 11:14:04.411271 <4>[ 0.987416] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10445 11:14:04.421281 <4>[ 0.998079] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10446 11:14:04.436397 <6>[ 1.019234] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10447 11:14:04.444875 <6>[ 1.027424] printk: console [ttyS0] disabled
10448 11:14:04.472923 <6>[ 1.052078] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10449 11:14:04.479526 <6>[ 1.061556] printk: console [ttyS0] enabled
10450 11:14:04.482809 <6>[ 1.061556] printk: console [ttyS0] enabled
10451 11:14:04.489479 <6>[ 1.070455] printk: bootconsole [mtk8250] disabled
10452 11:14:04.492758 <6>[ 1.070455] printk: bootconsole [mtk8250] disabled
10453 11:14:04.499124 <6>[ 1.081736] SuperH (H)SCI(F) driver initialized
10454 11:14:04.502287 <6>[ 1.087000] msm_serial: driver initialized
10455 11:14:04.517073 <6>[ 1.095909] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10456 11:14:04.526821 <6>[ 1.104457] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10457 11:14:04.533622 <6>[ 1.113000] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10458 11:14:04.543284 <6>[ 1.121628] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10459 11:14:04.550089 <6>[ 1.130334] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10460 11:14:04.559675 <6>[ 1.139048] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10461 11:14:04.569593 <6>[ 1.147587] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10462 11:14:04.576643 <6>[ 1.156412] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10463 11:14:04.586226 <6>[ 1.164957] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10464 11:14:04.597796 <6>[ 1.180690] loop: module loaded
10465 11:14:04.604788 <6>[ 1.186792] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10466 11:14:04.627452 <4>[ 1.209655] mtk-pmic-keys: Failed to locate of_node [id: -1]
10467 11:14:04.633731 <6>[ 1.216442] megasas: 07.719.03.00-rc1
10468 11:14:04.643986 <6>[ 1.226086] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10469 11:14:04.650385 <6>[ 1.232868] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10470 11:14:04.667241 <6>[ 1.249760] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10471 11:14:04.723941 <6>[ 1.300066] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10472 11:14:05.084028 <6>[ 1.666588] Freeing initrd memory: 20728K
10473 11:14:05.099466 <6>[ 1.682192] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10474 11:14:05.110577 <6>[ 1.693114] tun: Universal TUN/TAP device driver, 1.6
10475 11:14:05.113625 <6>[ 1.699167] thunder_xcv, ver 1.0
10476 11:14:05.117184 <6>[ 1.702674] thunder_bgx, ver 1.0
10477 11:14:05.120367 <6>[ 1.706169] nicpf, ver 1.0
10478 11:14:05.130856 <6>[ 1.710181] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10479 11:14:05.134213 <6>[ 1.717657] hns3: Copyright (c) 2017 Huawei Corporation.
10480 11:14:05.140753 <6>[ 1.723246] hclge is initializing
10481 11:14:05.143980 <6>[ 1.726827] e1000: Intel(R) PRO/1000 Network Driver
10482 11:14:05.150708 <6>[ 1.731956] e1000: Copyright (c) 1999-2006 Intel Corporation.
10483 11:14:05.153959 <6>[ 1.737969] e1000e: Intel(R) PRO/1000 Network Driver
10484 11:14:05.160683 <6>[ 1.743185] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10485 11:14:05.166963 <6>[ 1.749369] igb: Intel(R) Gigabit Ethernet Network Driver
10486 11:14:05.173825 <6>[ 1.755019] igb: Copyright (c) 2007-2014 Intel Corporation.
10487 11:14:05.180828 <6>[ 1.760857] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10488 11:14:05.187352 <6>[ 1.767375] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10489 11:14:05.190717 <6>[ 1.773834] sky2: driver version 1.30
10490 11:14:05.197263 <6>[ 1.778814] VFIO - User Level meta-driver version: 0.3
10491 11:14:05.204197 <6>[ 1.786975] usbcore: registered new interface driver usb-storage
10492 11:14:05.211327 <6>[ 1.793418] usbcore: registered new device driver onboard-usb-hub
10493 11:14:05.219838 <6>[ 1.802464] mt6397-rtc mt6359-rtc: registered as rtc0
10494 11:14:05.230035 <6>[ 1.807931] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-05T11:14:05 UTC (1685963645)
10495 11:14:05.232830 <6>[ 1.817496] i2c_dev: i2c /dev entries driver
10496 11:14:05.249519 <6>[ 1.829064] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10497 11:14:05.256780 <6>[ 1.839281] sdhci: Secure Digital Host Controller Interface driver
10498 11:14:05.263600 <6>[ 1.845718] sdhci: Copyright(c) Pierre Ossman
10499 11:14:05.270266 <6>[ 1.851109] Synopsys Designware Multimedia Card Interface Driver
10500 11:14:05.273203 <6>[ 1.857710] mmc0: CQHCI version 5.10
10501 11:14:05.279862 <6>[ 1.858272] sdhci-pltfm: SDHCI platform and OF driver helper
10502 11:14:05.287263 <6>[ 1.869970] ledtrig-cpu: registered to indicate activity on CPUs
10503 11:14:05.298362 <6>[ 1.877376] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10504 11:14:05.304469 <6>[ 1.884777] usbcore: registered new interface driver usbhid
10505 11:14:05.307767 <6>[ 1.890605] usbhid: USB HID core driver
10506 11:14:05.314425 <6>[ 1.894852] spi_master spi0: will run message pump with realtime priority
10507 11:14:05.360583 <6>[ 1.936497] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10508 11:14:05.379361 <6>[ 1.951507] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10509 11:14:05.383011 <6>[ 1.965079] mmc0: Command Queue Engine enabled
10510 11:14:05.389648 <6>[ 1.967034] cros-ec-spi spi0.0: Chrome EC device registered
10511 11:14:05.396137 <6>[ 1.969816] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10512 11:14:05.399550 <6>[ 1.982883] mmcblk0: mmc0:0001 DA4128 116 GiB
10513 11:14:05.410351 <6>[ 1.992688] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10514 11:14:05.419846 <6>[ 1.993219] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10515 11:14:05.426489 <6>[ 2.000052] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10516 11:14:05.430271 <6>[ 2.010159] NET: Registered PF_PACKET protocol family
10517 11:14:05.436854 <6>[ 2.013828] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10518 11:14:05.440019 <6>[ 2.018586] 9pnet: Installing 9P2000 support
10519 11:14:05.446204 <6>[ 2.024370] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10520 11:14:05.452866 <5>[ 2.028256] Key type dns_resolver registered
10521 11:14:05.456688 <6>[ 2.039868] registered taskstats version 1
10522 11:14:05.462708 <5>[ 2.044289] Loading compiled-in X.509 certificates
10523 11:14:05.496606 <4>[ 2.072345] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10524 11:14:05.506341 <4>[ 2.083162] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10525 11:14:05.516748 <3>[ 2.095873] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10526 11:14:05.528721 <6>[ 2.111486] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10527 11:14:05.535870 <6>[ 2.118499] xhci-mtk 11200000.usb: xHCI Host Controller
10528 11:14:05.542277 <6>[ 2.124030] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10529 11:14:05.552629 <6>[ 2.131996] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10530 11:14:05.559505 <6>[ 2.141450] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10531 11:14:05.565876 <6>[ 2.147545] xhci-mtk 11200000.usb: xHCI Host Controller
10532 11:14:05.572512 <6>[ 2.153028] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10533 11:14:05.579199 <6>[ 2.160682] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10534 11:14:05.585691 <6>[ 2.168571] hub 1-0:1.0: USB hub found
10535 11:14:05.589039 <6>[ 2.172618] hub 1-0:1.0: 1 port detected
10536 11:14:05.599052 <6>[ 2.176970] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10537 11:14:05.602550 <6>[ 2.185858] hub 2-0:1.0: USB hub found
10538 11:14:05.605867 <6>[ 2.189891] hub 2-0:1.0: 1 port detected
10539 11:14:05.614537 <6>[ 2.197204] mtk-msdc 11f70000.mmc: Got CD GPIO
10540 11:14:05.636615 <6>[ 2.216115] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10541 11:14:05.643361 <6>[ 2.224209] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10542 11:14:05.653218 <4>[ 2.232184] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10543 11:14:05.662990 <6>[ 2.241859] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10544 11:14:05.670072 <6>[ 2.249950] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10545 11:14:05.679788 <6>[ 2.257984] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10546 11:14:05.686766 <6>[ 2.265898] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10547 11:14:05.693317 <6>[ 2.273719] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10548 11:14:05.702779 <6>[ 2.281539] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10549 11:14:05.712703 <6>[ 2.292195] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10550 11:14:05.723260 <6>[ 2.300569] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10551 11:14:05.729722 <6>[ 2.308922] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10552 11:14:05.739569 <6>[ 2.317265] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10553 11:14:05.745643 <6>[ 2.325610] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10554 11:14:05.755944 <6>[ 2.333953] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10555 11:14:05.762558 <6>[ 2.342296] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10556 11:14:05.772188 <6>[ 2.350639] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10557 11:14:05.778879 <6>[ 2.358983] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10558 11:14:05.788902 <6>[ 2.367326] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10559 11:14:05.795495 <6>[ 2.375670] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10560 11:14:05.805429 <6>[ 2.384012] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10561 11:14:05.812354 <6>[ 2.392356] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10562 11:14:05.822101 <6>[ 2.400700] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10563 11:14:05.828659 <6>[ 2.409043] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10564 11:14:05.835270 <6>[ 2.417968] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10565 11:14:05.842517 <6>[ 2.425450] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10566 11:14:05.850004 <6>[ 2.432548] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10567 11:14:05.860296 <6>[ 2.439703] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10568 11:14:05.866892 <6>[ 2.447027] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10569 11:14:05.877081 <6>[ 2.453964] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10570 11:14:05.883655 <6>[ 2.463107] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10571 11:14:05.893784 <6>[ 2.472233] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10572 11:14:05.903334 <6>[ 2.481536] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10573 11:14:05.913405 <6>[ 2.491010] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10574 11:14:05.923388 <6>[ 2.500486] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10575 11:14:05.929961 <6>[ 2.509616] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10576 11:14:05.939797 <6>[ 2.519089] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10577 11:14:05.949650 <6>[ 2.528216] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10578 11:14:05.959417 <6>[ 2.537519] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10579 11:14:05.969673 <6>[ 2.547686] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10580 11:14:05.979535 <6>[ 2.559166] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10581 11:14:06.018340 <6>[ 2.597679] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10582 11:14:06.170825 <6>[ 2.753630] hub 1-1:1.0: USB hub found
10583 11:14:06.174488 <6>[ 2.757982] hub 1-1:1.0: 4 ports detected
10584 11:14:06.298667 <6>[ 2.878045] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10585 11:14:06.324817 <6>[ 2.908047] hub 2-1:1.0: USB hub found
10586 11:14:06.328286 <6>[ 2.912570] hub 2-1:1.0: 3 ports detected
10587 11:14:06.493555 <6>[ 3.073731] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10588 11:14:06.626352 <6>[ 3.209371] hub 1-1.4:1.0: USB hub found
10589 11:14:06.629572 <6>[ 3.214035] hub 1-1.4:1.0: 2 ports detected
10590 11:14:06.710001 <6>[ 3.289736] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10591 11:14:06.926097 <6>[ 3.505657] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10592 11:14:07.110384 <6>[ 3.689635] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10593 11:14:18.270371 <6>[ 14.858301] ALSA device list:
10594 11:14:18.277376 <6>[ 14.861556] No soundcards found.
10595 11:14:18.289259 <6>[ 14.873830] Freeing unused kernel memory: 8384K
10596 11:14:18.292534 <6>[ 14.878741] Run /init as init process
10597 11:14:18.318129 Starting syslogd: OK
10598 11:14:18.322368 Starting klogd: OK
10599 11:14:18.332021 Running sysctl: OK
10600 11:14:18.341959 Populating /dev using udev: <30>[ 14.925213] udevd[192]: starting version 3.2.9
10601 11:14:18.348572 <27>[ 14.933290] udevd[192]: specified user 'tss' unknown
10602 11:14:18.355321 <27>[ 14.938664] udevd[192]: specified group 'tss' unknown
10603 11:14:18.358390 <30>[ 14.944998] udevd[193]: starting eudev-3.2.9
10604 11:14:18.388468 <27>[ 14.973094] udevd[193]: specified user 'tss' unknown
10605 11:14:18.395304 <27>[ 14.978477] udevd[193]: specified group 'tss' unknown
10606 11:14:18.547546 <6>[ 15.129057] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10607 11:14:18.558758 <6>[ 15.143262] remoteproc remoteproc0: scp is available
10608 11:14:18.588442 <6>[ 15.169738] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10609 11:14:18.595076 <6>[ 15.177375] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10610 11:14:18.605501 <6>[ 15.186879] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10611 11:14:18.615324 <4>[ 15.194035] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10612 11:14:18.625629 <3>[ 15.200450] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10613 11:14:18.628480 <6>[ 15.205877] remoteproc remoteproc0: powering up scp
10614 11:14:18.638322 <3>[ 15.213634] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10615 11:14:18.648469 <4>[ 15.218979] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10616 11:14:18.655218 <3>[ 15.226897] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10617 11:14:18.661632 <3>[ 15.236796] remoteproc remoteproc0: request_firmware failed: -2
10618 11:14:18.668268 <3>[ 15.245409] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10619 11:14:18.678053 <4>[ 15.246705] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10620 11:14:18.685059 <4>[ 15.246822] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10621 11:14:18.691498 <3>[ 15.273831] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10622 11:14:18.701449 <3>[ 15.282011] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10623 11:14:18.708006 <6>[ 15.284278] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10624 11:14:18.717977 <3>[ 15.290145] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10625 11:14:18.724511 <3>[ 15.306018] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10626 11:14:18.737058 <3>[ 15.318134] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10627 11:14:18.740721 <6>[ 15.318245] mc: Linux media interface: v0.10
10628 11:14:18.747383 <6>[ 15.324527] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10629 11:14:18.754165 <6>[ 15.324539] pci_bus 0000:00: root bus resource [bus 00-ff]
10630 11:14:18.760143 <6>[ 15.324546] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10631 11:14:18.770555 <6>[ 15.324552] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10632 11:14:18.777058 <6>[ 15.324594] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10633 11:14:18.783687 <6>[ 15.324672] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10634 11:14:18.790214 <6>[ 15.324791] pci 0000:00:00.0: supports D1 D2
10635 11:14:18.796710 <6>[ 15.324796] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10636 11:14:18.803279 <3>[ 15.326511] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10637 11:14:18.813053 <6>[ 15.327789] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10638 11:14:18.820103 <6>[ 15.327945] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10639 11:14:18.826642 <6>[ 15.327983] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10640 11:14:18.833182 <6>[ 15.328009] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10641 11:14:18.842948 <6>[ 15.328031] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10642 11:14:18.846265 <6>[ 15.328164] pci 0000:01:00.0: supports D1 D2
10643 11:14:18.852949 <6>[ 15.328169] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10644 11:14:18.859408 <6>[ 15.337609] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10645 11:14:18.869284 <3>[ 15.337719] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10646 11:14:18.875871 <6>[ 15.345335] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10647 11:14:18.882338 <3>[ 15.350681] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10648 11:14:18.892705 <6>[ 15.357536] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10649 11:14:18.902501 <6>[ 15.360547] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10650 11:14:18.909518 <6>[ 15.361252] videodev: Linux video capture interface: v2.00
10651 11:14:18.915873 <3>[ 15.366938] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10652 11:14:18.922348 <6>[ 15.374518] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10653 11:14:18.932472 <3>[ 15.378896] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10654 11:14:18.939022 <6>[ 15.385769] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10655 11:14:18.949280 <3>[ 15.393866] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10656 11:14:18.958879 <6>[ 15.394090] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10657 11:14:18.968534 <6>[ 15.394548] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10658 11:14:18.975281 <6>[ 15.402126] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10659 11:14:18.981445 <6>[ 15.405683] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10660 11:14:18.988648 <3>[ 15.408390] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10661 11:14:18.995276 <6>[ 15.415953] pci 0000:00:00.0: PCI bridge to [bus 01]
10662 11:14:19.002086 <3>[ 15.423412] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10663 11:14:19.012365 <6>[ 15.430863] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10664 11:14:19.016071 <6>[ 15.431795] Bluetooth: Core ver 2.22
10665 11:14:19.019123 <6>[ 15.431859] NET: Registered PF_BLUETOOTH protocol family
10666 11:14:19.025852 <6>[ 15.431863] Bluetooth: HCI device and connection manager initialized
10667 11:14:19.032312 <6>[ 15.431884] Bluetooth: HCI socket layer initialized
10668 11:14:19.039075 <6>[ 15.431889] Bluetooth: L2CAP socket layer initialized
10669 11:14:19.042506 <6>[ 15.431919] Bluetooth: SCO socket layer initialized
10670 11:14:19.052321 <3>[ 15.435490] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10671 11:14:19.058723 <6>[ 15.442946] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10672 11:14:19.065759 <4>[ 15.458900] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10673 11:14:19.075702 <4>[ 15.465384] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10674 11:14:19.078545 <4>[ 15.465384] Fallback method does not support PEC.
10675 11:14:19.085507 <6>[ 15.466444] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10676 11:14:19.092045 <6>[ 15.466680] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10677 11:14:19.102005 <4>[ 15.473537] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10678 11:14:19.108375 <6>[ 15.476064] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10679 11:14:19.111763 <6>[ 15.492224] usbcore: registered new interface driver btusb
10680 11:14:19.121503 <5>[ 15.494173] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10681 11:14:19.131992 <4>[ 15.497531] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10682 11:14:19.138247 <6>[ 15.506461] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10683 11:14:19.145005 <3>[ 15.512959] Bluetooth: hci0: Failed to load firmware file (-2)
10684 11:14:19.151660 <5>[ 15.517558] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10685 11:14:19.161293 <4>[ 15.517627] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10686 11:14:19.164512 <6>[ 15.517634] cfg80211: failed to load regulatory.db
10687 11:14:19.171013 <6>[ 15.528567] remoteproc remoteproc0: powering up scp
10688 11:14:19.174296 <3>[ 15.529250] Bluetooth: hci0: Failed to set up firmware (-2)
10689 11:14:19.184640 <4>[ 15.537242] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10690 11:14:19.197679 <4>[ 15.547285] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10691 11:14:19.200965 <3>[ 15.556307] remoteproc remoteproc0: request_firmware failed: -2
10692 11:14:19.210815 <3>[ 15.556322] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10693 11:14:19.220783 <6>[ 15.564874] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10694 11:14:19.227317 <6>[ 15.571667] r8152 2-1.3:1.0 eth0: v1.12.13
10695 11:14:19.233644 <6>[ 15.579878] usbcore: registered new interface driver uvcvideo
10696 11:14:19.240403 <3>[ 15.584156] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10697 11:14:19.247127 <6>[ 15.585010] usbcore: registered new interface driver r8152
10698 11:14:19.257100 <3>[ 15.605170] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10699 11:14:19.263671 <6>[ 15.614604] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10700 11:14:19.269887 <6>[ 15.627818] usbcore: registered new interface driver cdc_ether
10701 11:14:19.276885 <6>[ 15.632731] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10702 11:14:19.280130 <6>[ 15.647323] usbcore: registered new interface driver r8153_ecm
10703 11:14:19.287051 <6>[ 15.673607] mt7921e 0000:01:00.0: ASIC revision: 79610010
10704 11:14:19.391670 <4>[ 15.969568] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10705 11:14:19.391817 done
10706 11:14:19.411986 Saving random seed: OK
10707 11:14:19.426374 Starting network: OK
10708 11:14:19.466388 Starting dropbear sshd: <6>[ 16.050727] NET: Registered PF_INET6 protocol family
10709 11:14:19.472732 <6>[ 16.057204] Segment Routing with IPv6
10710 11:14:19.476208 <6>[ 16.061166] In-situ OAM (IOAM) with IPv6
10711 11:14:19.479683 OK
10712 11:14:19.488978 /bin/sh: can't access tty; job control turned off
10713 11:14:19.489282 Matched prompt #10: / #
10715 11:14:19.489484 Setting prompt string to ['/ #']
10716 11:14:19.489573 end: 2.2.5.1 login-action (duration 00:00:17) [common]
10718 11:14:19.489763 end: 2.2.5 auto-login-action (duration 00:00:17) [common]
10719 11:14:19.489845 start: 2.2.6 expect-shell-connection (timeout 00:03:25) [common]
10720 11:14:19.489914 Setting prompt string to ['/ #']
10721 11:14:19.489973 Forcing a shell prompt, looking for ['/ #']
10723 11:14:19.540151 / #
10724 11:14:19.540245 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10725 11:14:19.540319 Waiting using forced prompt support (timeout 00:02:30)
10726 11:14:19.540411 <4>[ 16.092018] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10727 11:14:19.544960
10728 11:14:19.545225 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10729 11:14:19.545319 start: 2.2.7 export-device-env (timeout 00:03:25) [common]
10730 11:14:19.545412 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10731 11:14:19.545527 end: 2.2 depthcharge-retry (duration 00:01:35) [common]
10732 11:14:19.545610 end: 2 depthcharge-action (duration 00:01:35) [common]
10733 11:14:19.545720 start: 3 lava-test-retry (timeout 00:01:00) [common]
10734 11:14:19.545817 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10735 11:14:19.545892 Using namespace: common
10737 11:14:19.646210 / # #
10738 11:14:19.646376 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10739 11:14:19.646490 #<4>[ 16.211902] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10740 11:14:19.651896
10741 11:14:19.652176 Using /lava-10591271
10743 11:14:19.752566 / # export SHELL=/bin/sh
10744 11:14:19.753749 export SHELL=/bin/sh<4>[ 16.331879] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10745 11:14:19.796528
10747 11:14:19.897817 / # . /lava-10591271/environment
10748 11:14:19.898027 . /lava-10591271/environment<4>[ 16.452350] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10749 11:14:19.903381
10751 11:14:20.003890 / # /lava-10591271/bin/lava-test-runner /lava-10591271/0
10752 11:14:20.004053 Test shell timeout: 10s (minimum of the action and connection timeout)
10753 11:14:20.004410 /lava-10591271/bin/lava-test-runner /lava-10591271/0<4>[ 16.571732] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10754 11:14:20.009947
10755 11:14:20.052180 + export 'TESTRUN_ID=0_dmesg'
10756 11:14:20.052274 + c<8>[ 16.617347] <LAVA_SIGNAL_STARTRUN 0_dmesg 10591271_1.5.2.3.1>
10757 11:14:20.052342 d /lava-10591271/0/tests/0_dmesg
10758 11:14:20.052402 + cat uuid
10759 11:14:20.052460 + UUID=10591271_1.5.2.3.1
10760 11:14:20.052517 + set +x
10761 11:14:20.052573 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10762 11:14:20.052806 Received signal: <STARTRUN> 0_dmesg 10591271_1.5.2.3.1
10763 11:14:20.052873 Starting test lava.0_dmesg (10591271_1.5.2.3.1)
10764 11:14:20.052952 Skipping test definition patterns.
10765 11:14:20.057670 <8>[ 16.637600] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10766 11:14:20.057923 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10768 11:14:20.076488 <8>[ 16.657891] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10769 11:14:20.076743 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10771 11:14:20.101188 <8>[ 16.682038] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10772 11:14:20.101452 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10774 11:14:20.111059 <4>[ 16.688833] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10775 11:14:20.114099 + set +x
10776 11:14:20.117871 Received signal: <ENDRUN> 0_dmesg 10591271_1.5.2.3.1
10777 11:14:20.117972 Ending use of test pattern.
10778 11:14:20.118039 Ending test lava.0_dmesg (10591271_1.5.2.3.1), duration 0.07
10780 11:14:20.120678 <8>[ 16.702426] <LAVA_SIGNAL_ENDRUN 0_dmesg 10591271_1.5.2.3.1>
10781 11:14:20.123734 <LAVA_TEST_RUNNER EXIT>
10782 11:14:20.124013 ok: lava_test_shell seems to have completed
10783 11:14:20.124199 alert: pass
crit: pass
emerg: pass
10784 11:14:20.124319 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10785 11:14:20.124444 end: 3 lava-test-retry (duration 00:00:01) [common]
10786 11:14:20.124572 start: 4 lava-test-retry (timeout 00:01:00) [common]
10787 11:14:20.124668 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
10788 11:14:20.124734 Using namespace: common
10790 11:14:20.225056 / # #
10791 11:14:20.225226 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10792 11:14:20.225357 Using /lava-10591271
10794 11:14:20.325709 export SHELL=/bin/sh
10795 11:14:20.325922 #<4>[ 16.811879] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10796 11:14:20.326006
10798 11:14:20.426508 / # export SHELL=/bin/sh. /lava-10591271/environment
10799 11:14:20.426717
10800 11:14:20.426800 / # <4>[ 16.932343] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10802 11:14:20.527344 . /lava-10591271/environment/lava-10591271/bin/lava-test-runner /lava-10591271/1
10803 11:14:20.527507 Test shell timeout: 10s (minimum of the action and connection timeout)
10804 11:14:20.527632
10805 11:14:20.527702 / # <4>[ 17.051788] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10806 11:14:20.532074 /lava-10591271/bin/lava-test-runner /lava-10591271/1
10807 11:14:20.576132 + export 'TESTRUN_ID=1_bootrr'
10808 11:14:20.576279 <8>[ 17.140872] <LAVA_SIGNAL_STARTRUN 1_bootrr 10591271_1.5.2.3.5>
10809 11:14:20.576377 + cd /lava-10591271/1/tests/1_bootrr
10810 11:14:20.576468 + cat uuid
10811 11:14:20.576557 + UUID=10591271_1.5.2.3.5
10812 11:14:20.576645 + set +x
10813 11:14:20.576912 Received signal: <STARTRUN> 1_bootrr 10591271_1.5.2.3.5
10814 11:14:20.577005 Starting test lava.1_bootrr (10591271_1.5.2.3.5)
10815 11:14:20.577117 Skipping test definition patterns.
10816 11:14:20.577253 + export 'PATH=/opt/bootrr/libexec/bootrr/helpers:/lava-10591271/1/../bin:/sbin:/usr/sbin:/bin:/usr/bin'
10817 11:14:20.577589 + cd /opt/bootrr/libexec/bootrr
10818 11:14:20.580890 + sh helpers/bootrr-auto
10819 11:14:20.587760 /lava-10591271/1/../<3>[ 17.171356] mt7921e 0000:01:00.0: hardware init failed
10820 11:14:20.597335 bin/lava-test-ca<8>[ 17.171431] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
10821 11:14:20.597419 se
10822 11:14:20.597653 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
10824 11:14:20.608099 /lava-10591271/1/../bin/lava-test-case
10825 11:14:20.615019 <8>[ 17.196730] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
10826 11:14:20.615271 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
10828 11:14:20.619953 /usr/bin/tpm2_getcap
10829 11:14:20.651944 /lava-10591271/1/../bin/lava-test-case
10830 11:14:20.659079 <8>[ 17.240744] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=pass>
10831 11:14:20.659377 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=pass
10833 11:14:20.675960 /lava-10591271/1/../bin/lava-test-case
10834 11:14:20.682105 <8>[ 17.263750] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass>
10835 11:14:20.682360 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-driver-present RESULT=pass
10837 11:14:20.694000 /lava-10591271/1/../bin/lava-test-case
10838 11:14:20.700953 <8>[ 17.282037] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass>
10839 11:14:20.701207 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-topckgen-probed RESULT=pass
10841 11:14:20.711970 /lava-10591271/1/../bin/lava-test-case
10842 11:14:20.718440 <8>[ 17.299975] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass>
10843 11:14:20.718693 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-infracfg-probed RESULT=pass
10845 11:14:20.729658 /lava-10591271/1/../bin/lava-test-case
10846 11:14:20.736052 <8>[ 17.317922] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass>
10847 11:14:20.736330 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-pericfg-probed RESULT=pass
10849 11:14:20.747167 /lava-10591271/1/../bin/lava-test-case
10850 11:14:20.753680 <8>[ 17.335480] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass>
10851 11:14:20.753933 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-apmixedsys-probed RESULT=pass
10853 11:14:20.763323 /lava-10591271/1/../bin/lava-test-case
10854 11:14:20.770257 <8>[ 17.351085] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass>
10855 11:14:20.770995 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-driver-present RESULT=pass
10857 11:14:20.781612 /lava-10591271/1/../bin/lava-test-case
10858 11:14:20.788196 <8>[ 17.369721] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass>
10859 11:14:20.788947 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-aud-probed RESULT=pass
10861 11:14:20.798261 /lava-10591271/1/../bin/lava-test-case
10862 11:14:20.804431 <8>[ 17.385448] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass>
10863 11:14:20.805105 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap-driver-present RESULT=pass
10865 11:14:20.816604 /lava-10591271/1/../bin/lava-test-case
10866 11:14:20.823189 <8>[ 17.404405] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass>
10867 11:14:20.823884 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_n-probed RESULT=pass
10869 11:14:20.835405 /lava-10591271/1/../bin/lava-test-case
10870 11:14:20.841667 <8>[ 17.423161] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass>
10871 11:14:20.842333 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_ws-probed RESULT=pass
10873 11:14:20.853759 /lava-10591271/1/../bin/lava-test-case
10874 11:14:20.860458 <8>[ 17.441273] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass>
10875 11:14:20.861121 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_e-probed RESULT=pass
10877 11:14:20.872618 /lava-10591271/1/../bin/lava-test-case
10878 11:14:20.879050 <8>[ 17.459990] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass>
10879 11:14:20.879725 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-imp_iic_wrap_s-probed RESULT=pass
10881 11:14:20.889021 /lava-10591271/1/../bin/lava-test-case
10882 11:14:20.895519 <8>[ 17.476361] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass>
10883 11:14:20.896148 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-driver-present RESULT=pass
10885 11:14:20.907890 /lava-10591271/1/../bin/lava-test-case
10886 11:14:20.914424 <8>[ 17.495795] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass>
10887 11:14:20.915073 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mfg-probed RESULT=pass
10889 11:14:20.924634 /lava-10591271/1/../bin/lava-test-case
10890 11:14:20.930473 <8>[ 17.511894] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass>
10891 11:14:20.931123 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-driver-present RESULT=pass
10893 11:14:20.941895 /lava-10591271/1/../bin/lava-test-case
10894 11:14:20.948761 <8>[ 17.529739] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass>
10895 11:14:20.949431 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mm-probed RESULT=pass
10897 11:14:20.958494 /lava-10591271/1/../bin/lava-test-case
10898 11:14:20.964336 <8>[ 17.545769] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass>
10899 11:14:20.965007 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-driver-present RESULT=pass
10901 11:14:20.976546 /lava-10591271/1/../bin/lava-test-case
10902 11:14:20.982977 <8>[ 17.563979] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-mmsys-probed RESULT=pass>
10903 11:14:20.983646 Received signal: <TESTCASE> TEST_CASE_ID=mtk-mmsys-probed RESULT=pass
10905 11:14:20.991448 /lava-10591271/1/../bin/lava-test-case
10906 11:14:20.998307 <8>[ 17.579683] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass>
10907 11:14:20.998960 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-driver-present RESULT=pass
10909 11:14:21.010111 /lava-10591271/1/../bin/lava-test-case
10910 11:14:21.016618 <8>[ 17.597626] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass>
10911 11:14:21.017267 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-msdc-probed RESULT=pass
10913 11:14:21.026038 /lava-10591271/1/../bin/lava-test-case
10914 11:14:21.032628 <8>[ 17.613502] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass>
10915 11:14:21.033308 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-driver-present RESULT=pass
10917 11:14:21.043975 /lava-10591271/1/../bin/lava-test-case
10918 11:14:21.050278 <8>[ 17.632249] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass>
10919 11:14:21.050529 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec_soc-probed RESULT=pass
10921 11:14:21.062488 /lava-10591271/1/../bin/lava-test-case
10922 11:14:21.069106 <8>[ 17.650515] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass>
10923 11:14:21.069354 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-vdec-probed RESULT=pass
10925 11:14:21.078060 /lava-10591271/1/../bin/lava-test-case
10926 11:14:21.084705 <8>[ 17.666395] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass>
10927 11:14:21.084959 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-driver-present RESULT=pass
10929 11:14:21.097336 /lava-10591271/1/../bin/lava-test-case
10930 11:14:21.103765 <8>[ 17.685348] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass>
10931 11:14:21.104008 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-venc-probed RESULT=pass
10933 11:14:21.113319 /lava-10591271/1/../bin/lava-test-case
10934 11:14:21.119860 <8>[ 17.701090] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass>
10935 11:14:21.120103 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-driver-present RESULT=pass
10937 11:14:21.131984 /lava-10591271/1/../bin/lava-test-case
10938 11:14:21.139028 <8>[ 17.720640] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass>
10939 11:14:21.139278 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam-probed RESULT=pass
10941 11:14:21.150311 /lava-10591271/1/../bin/lava-test-case
10942 11:14:21.156897 <8>[ 17.738705] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass>
10943 11:14:21.157154 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawa-probed RESULT=pass
10945 11:14:21.169009 /lava-10591271/1/../bin/lava-test-case
10946 11:14:21.175511 <8>[ 17.756812] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass>
10947 11:14:21.175766 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawb-probed RESULT=pass
10949 11:14:21.187985 /lava-10591271/1/../bin/lava-test-case
10950 11:14:21.194592 <8>[ 17.775639] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass>
10951 11:14:21.194849 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-cam_rawc-probed RESULT=pass
10953 11:14:21.203680 /lava-10591271/1/../bin/lava-test-case
10954 11:14:21.210220 <8>[ 17.792011] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass>
10955 11:14:21.210473 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-driver-present RESULT=pass
10957 11:14:21.222082 /lava-10591271/1/../bin/lava-test-case
10958 11:14:21.228679 <8>[ 17.809991] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass>
10959 11:14:21.228931 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img-probed RESULT=pass
10961 11:14:21.240177 /lava-10591271/1/../bin/lava-test-case
10962 11:14:21.246640 <8>[ 17.828386] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass>
10963 11:14:21.246890 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-img2-probed RESULT=pass
10965 11:14:21.256069 /lava-10591271/1/../bin/lava-test-case
10966 11:14:21.262948 <8>[ 17.844406] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass>
10967 11:14:21.263218 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-driver-present RESULT=pass
10969 11:14:21.275381 /lava-10591271/1/../bin/lava-test-case
10970 11:14:21.281943 <8>[ 17.863634] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass>
10971 11:14:21.282211 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-ipe-probed RESULT=pass
10973 11:14:21.291345 /lava-10591271/1/../bin/lava-test-case
10974 11:14:21.298062 <8>[ 17.879505] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass>
10975 11:14:21.298307 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-driver-present RESULT=pass
10977 11:14:21.310118 /lava-10591271/1/../bin/lava-test-case
10978 11:14:21.316627 <8>[ 17.898462] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass>
10979 11:14:21.316885 Received signal: <TESTCASE> TEST_CASE_ID=clk-mt8192-mdp-probed RESULT=pass
10981 11:14:21.326216 /lava-10591271/1/../bin/lava-test-case
10982 11:14:21.332505 <8>[ 17.913897] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass>
10983 11:14:21.332755 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-driver-present RESULT=pass
10985 11:14:21.344922 /lava-10591271/1/../bin/lava-test-case
10986 11:14:21.351388 <8>[ 17.932748] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass>
10987 11:14:21.351639 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-pinctrl-probed RESULT=pass
10989 11:14:21.360070 /lava-10591271/1/../bin/lava-test-case
10990 11:14:21.366490 <8>[ 17.948069] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass>
10991 11:14:21.366741 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-driver-present RESULT=pass
10993 11:14:21.379385 /lava-10591271/1/../bin/lava-test-case
10994 11:14:21.386075 <8>[ 17.967883] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-power-controller-probed RESULT=pass>
10995 11:14:21.386329 Received signal: <TESTCASE> TEST_CASE_ID=mtk-power-controller-probed RESULT=pass
10997 11:14:21.395958 /lava-10591271/1/../bin/lava-test-case
10998 11:14:21.402574 <8>[ 17.983804] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass>
10999 11:14:21.402826 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-driver-present RESULT=pass
11001 11:14:21.414179 /lava-10591271/1/../bin/lava-test-case
11002 11:14:21.421266 <8>[ 18.002865] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass>
11003 11:14:21.421516 Received signal: <TESTCASE> TEST_CASE_ID=mt-pmic-pwrap-probed RESULT=pass
11005 11:14:21.430949 /lava-10591271/1/../bin/lava-test-case
11006 11:14:21.437100 <8>[ 18.018650] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass>
11007 11:14:21.437353 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-driver-present RESULT=pass
11009 11:14:21.449238 /lava-10591271/1/../bin/lava-test-case
11010 11:14:21.455713 <8>[ 18.037004] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=spmi-mtk-probed RESULT=pass>
11011 11:14:21.455964 Received signal: <TESTCASE> TEST_CASE_ID=spmi-mtk-probed RESULT=pass
11013 11:14:21.464398 /lava-10591271/1/../bin/lava-test-case
11014 11:14:21.471044 <8>[ 18.052389] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass>
11015 11:14:21.471294 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator-driver-present RESULT=pass
11017 11:14:21.483895 /lava-10591271/1/../bin/lava-test-case
11018 11:14:21.490124 <8>[ 18.071719] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass>
11019 11:14:21.490376 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator6-probed RESULT=pass
11021 11:14:21.501525 /lava-10591271/1/../bin/lava-test-case
11022 11:14:21.507989 <8>[ 18.089413] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass>
11023 11:14:21.508287 Received signal: <TESTCASE> TEST_CASE_ID=mt6315-regulator7-probed RESULT=pass
11025 11:14:22.519714 /lava-10591271/1/../bin/lava-test-case
11026 11:14:22.526010 <8>[ 19.108419] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=fail>
11027 11:14:22.526336 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-driver-present RESULT=fail
11029 11:14:23.539463 /lava-10591271/1/../bin/lava-test-case
11030 11:14:23.546314 <8>[ 20.128334] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=blocked>
11031 11:14:23.546992 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-rpmsg-probed RESULT=blocked
11032 11:14:23.547406 Bad test result: blocked
11033 11:14:23.556281 /lava-10591271/1/../bin/lava-test-case
11034 11:14:23.562844 <8>[ 20.144242] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass>
11035 11:14:23.563515 Received signal: <TESTCASE> TEST_CASE_ID=i2c-mt65xx-driver-present RESULT=pass
11037 11:14:23.574981 /lava-10591271/1/../bin/lava-test-case
11038 11:14:23.581026 <8>[ 20.163150] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass>
11039 11:14:23.581810 Received signal: <TESTCASE> TEST_CASE_ID=i2c0-mt65xx-probed RESULT=pass
11041 11:14:23.593794 /lava-10591271/1/../bin/lava-test-case
11042 11:14:23.599880 <8>[ 20.182028] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass>
11043 11:14:23.600589 Received signal: <TESTCASE> TEST_CASE_ID=i2c1-mt65xx-probed RESULT=pass
11045 11:14:23.611126 /lava-10591271/1/../bin/lava-test-case
11046 11:14:23.617700 <8>[ 20.199373] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass>
11047 11:14:23.618365 Received signal: <TESTCASE> TEST_CASE_ID=i2c2-mt65xx-probed RESULT=pass
11049 11:14:23.629490 /lava-10591271/1/../bin/lava-test-case
11050 11:14:23.636319 <8>[ 20.217934] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass>
11051 11:14:23.636985 Received signal: <TESTCASE> TEST_CASE_ID=i2c3-mt65xx-probed RESULT=pass
11053 11:14:23.647782 /lava-10591271/1/../bin/lava-test-case
11054 11:14:23.654441 <8>[ 20.235827] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass>
11055 11:14:23.655111 Received signal: <TESTCASE> TEST_CASE_ID=i2c7-mt65xx-probed RESULT=pass
11057 11:14:23.663525 /lava-10591271/1/../bin/lava-test-case
11058 11:14:23.669656 <8>[ 20.251138] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-driver-present RESULT=pass>
11059 11:14:23.670331 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-driver-present RESULT=pass
11061 11:14:23.681803 /lava-10591271/1/../bin/lava-test-case
11062 11:14:23.688566 <8>[ 20.269597] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi1-probed RESULT=pass>
11063 11:14:23.689234 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi1-probed RESULT=pass
11065 11:14:23.698678 /lava-10591271/1/../bin/lava-test-case
11066 11:14:23.705403 <8>[ 20.287013] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi5-probed RESULT=pass>
11067 11:14:23.706071 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi5-probed RESULT=pass
11069 11:14:23.714225 /lava-10591271/1/../bin/lava-test-case
11070 11:14:23.720943 <8>[ 20.302770] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass>
11071 11:14:23.721610 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-driver-present RESULT=pass
11073 11:14:23.732765 /lava-10591271/1/../bin/lava-test-case
11074 11:14:23.739284 <8>[ 20.320740] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt6577-uart-probed RESULT=pass>
11075 11:14:23.740108 Received signal: <TESTCASE> TEST_CASE_ID=mt6577-uart-probed RESULT=pass
11077 11:14:23.748586 /lava-10591271/1/../bin/lava-test-case
11078 11:14:23.754963 <8>[ 20.336522] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass>
11079 11:14:23.755649 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-driver-present RESULT=pass
11081 11:14:23.767726 /lava-10591271/1/../bin/lava-test-case
11082 11:14:23.774114 <8>[ 20.356461] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-common-probed RESULT=pass>
11083 11:14:23.774848 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-common-probed RESULT=pass
11085 11:14:23.784437 /lava-10591271/1/../bin/lava-test-case
11086 11:14:23.790864 <8>[ 20.372390] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass>
11087 11:14:23.791643 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb-driver-present RESULT=pass
11089 11:14:23.804109 /lava-10591271/1/../bin/lava-test-case
11090 11:14:23.810463 <8>[ 20.391588] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass>
11091 11:14:23.811287 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb0-probed RESULT=pass
11093 11:14:23.821518 /lava-10591271/1/../bin/lava-test-case
11094 11:14:23.827941 <8>[ 20.409521] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass>
11095 11:14:23.828755 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb5-probed RESULT=pass
11097 11:14:23.839755 /lava-10591271/1/../bin/lava-test-case
11098 11:14:23.846099 <8>[ 20.427883] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass>
11099 11:14:23.846883 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb14-probed RESULT=pass
11101 11:14:23.858060 /lava-10591271/1/../bin/lava-test-case
11102 11:14:23.864291 <8>[ 20.446082] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass>
11103 11:14:23.864975 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb20-probed RESULT=pass
11105 11:14:23.876510 /lava-10591271/1/../bin/lava-test-case
11106 11:14:23.882442 <8>[ 20.464690] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass>
11107 11:14:23.883148 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb1-probed RESULT=pass
11109 11:14:23.894449 /lava-10591271/1/../bin/lava-test-case
11110 11:14:23.900599 <8>[ 20.482404] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass>
11111 11:14:23.901261 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb4-probed RESULT=pass
11113 11:14:23.912791 /lava-10591271/1/../bin/lava-test-case
11114 11:14:23.919105 <8>[ 20.500642] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass>
11115 11:14:23.919777 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb16-probed RESULT=pass
11117 11:14:23.930969 /lava-10591271/1/../bin/lava-test-case
11118 11:14:23.937240 <8>[ 20.518596] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass>
11119 11:14:23.937489 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb19-probed RESULT=pass
11121 11:14:23.948961 /lava-10591271/1/../bin/lava-test-case
11122 11:14:23.955207 <8>[ 20.537212] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass>
11123 11:14:23.955456 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb9-probed RESULT=pass
11125 11:14:23.966874 /lava-10591271/1/../bin/lava-test-case
11126 11:14:23.973063 <8>[ 20.555649] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass>
11127 11:14:23.973350 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb7-probed RESULT=pass
11129 11:14:23.985882 /lava-10591271/1/../bin/lava-test-case
11130 11:14:23.992276 <8>[ 20.574482] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass>
11131 11:14:23.992543 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb17-probed RESULT=pass
11133 11:14:24.004167 /lava-10591271/1/../bin/lava-test-case
11134 11:14:24.010717 <8>[ 20.592573] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass>
11135 11:14:24.011125 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb2-probed RESULT=pass
11137 11:14:24.021594 /lava-10591271/1/../bin/lava-test-case
11138 11:14:24.028687 <8>[ 20.610197] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass>
11139 11:14:24.029093 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb11-probed RESULT=pass
11141 11:14:24.039593 /lava-10591271/1/../bin/lava-test-case
11142 11:14:24.046587 <8>[ 20.628338] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass>
11143 11:14:24.047394 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb13-probed RESULT=pass
11145 11:14:24.058062 /lava-10591271/1/../bin/lava-test-case
11146 11:14:24.064533 <8>[ 20.646171] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass>
11147 11:14:24.065209 Received signal: <TESTCASE> TEST_CASE_ID=mtk-smi-larb18-probed RESULT=pass
11149 11:14:24.073754 /lava-10591271/1/../bin/lava-test-case
11150 11:14:24.080538 <8>[ 20.662682] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass>
11151 11:14:24.081281 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-driver-present RESULT=pass
11153 11:14:24.092264 /lava-10591271/1/../bin/lava-test-case
11154 11:14:24.098652 <8>[ 20.680808] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-iommu-probed RESULT=pass>
11155 11:14:24.099390 Received signal: <TESTCASE> TEST_CASE_ID=mtk-iommu-probed RESULT=pass
11157 11:14:24.108216 /lava-10591271/1/../bin/lava-test-case
11158 11:14:24.114544 <8>[ 20.695978] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass>
11159 11:14:24.115199 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-driver-present RESULT=pass
11161 11:14:24.125837 /lava-10591271/1/../bin/lava-test-case
11162 11:14:24.132552 <8>[ 20.713933] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-spi-probed RESULT=pass>
11163 11:14:24.133306 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-spi-probed RESULT=pass
11165 11:14:24.141071 /lava-10591271/1/../bin/lava-test-case
11166 11:14:24.147766 <8>[ 20.729353] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass>
11167 11:14:24.148543 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-driver-present RESULT=pass
11169 11:14:24.160090 /lava-10591271/1/../bin/lava-test-case
11170 11:14:24.166320 <8>[ 20.747613] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass>
11171 11:14:24.167087 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-i2c-tunnel-probed RESULT=pass
11173 11:14:24.176246 /lava-10591271/1/../bin/lava-test-case
11174 11:14:24.182961 <8>[ 20.763944] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass>
11175 11:14:24.183767 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-driver-present RESULT=pass
11177 11:14:24.194296 /lava-10591271/1/../bin/lava-test-case
11178 11:14:24.201288 <8>[ 20.782563] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-typec-probed RESULT=pass>
11179 11:14:24.202223 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-typec-probed RESULT=pass
11181 11:14:24.210032 /lava-10591271/1/../bin/lava-test-case
11182 11:14:24.216597 <8>[ 20.798231] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass>
11183 11:14:24.217334 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-driver-present RESULT=pass
11185 11:14:24.228110 /lava-10591271/1/../bin/lava-test-case
11186 11:14:24.234714 <8>[ 20.816322] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass>
11187 11:14:24.235383 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-pwm-probed RESULT=pass
11189 11:14:24.243666 /lava-10591271/1/../bin/lava-test-case
11190 11:14:24.250047 <8>[ 20.832024] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass>
11191 11:14:24.250790 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator-driver-present RESULT=pass
11193 11:14:24.262418 /lava-10591271/1/../bin/lava-test-case
11194 11:14:24.269488 <8>[ 20.851039] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass>
11195 11:14:24.270160 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator0-probed RESULT=pass
11197 11:14:24.281589 /lava-10591271/1/../bin/lava-test-case
11198 11:14:24.287431 <8>[ 20.869491] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass>
11199 11:14:24.288351 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-regulator1-probed RESULT=pass
11201 11:14:24.297073 /lava-10591271/1/../bin/lava-test-case
11202 11:14:24.303660 <8>[ 20.885145] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass>
11203 11:14:24.304378 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-driver-present RESULT=pass
11205 11:14:24.315424 /lava-10591271/1/../bin/lava-test-case
11206 11:14:24.322152 <8>[ 20.904040] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass>
11207 11:14:24.322949 Received signal: <TESTCASE> TEST_CASE_ID=cros-ec-keyb-probed RESULT=pass
11209 11:14:24.330743 /lava-10591271/1/../bin/lava-test-case
11210 11:14:24.337600 <8>[ 20.919529] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-driver-present RESULT=pass>
11211 11:14:24.338266 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-driver-present RESULT=pass
11213 11:14:24.349659 /lava-10591271/1/../bin/lava-test-case
11214 11:14:24.355906 <8>[ 20.937527] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=leds_pwm-probed RESULT=pass>
11215 11:14:24.356601 Received signal: <TESTCASE> TEST_CASE_ID=leds_pwm-probed RESULT=pass
11217 11:14:24.364772 /lava-10591271/1/../bin/lava-test-case
11218 11:14:24.371059 <8>[ 20.952406] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-driver-present RESULT=pass>
11219 11:14:24.371727 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-driver-present RESULT=pass
11221 11:14:25.384023 /lava-10591271/1/../bin/lava-test-case
11222 11:14:25.390927 <8>[ 21.973373] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elan_i2c-probed RESULT=fail>
11223 11:14:25.391268 Received signal: <TESTCASE> TEST_CASE_ID=elan_i2c-probed RESULT=fail
11225 11:14:25.399914 /lava-10591271/1/../bin/lava-test-case
11226 11:14:25.406213 <8>[ 21.988675] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-driver-present RESULT=pass>
11227 11:14:25.406661 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-driver-present RESULT=pass
11229 11:14:26.419971 /lava-10591271/1/../bin/lava-test-case
11230 11:14:26.425851 <8>[ 23.009274] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=elants_i2c-probed RESULT=fail>
11231 11:14:26.426110 Received signal: <TESTCASE> TEST_CASE_ID=elants_i2c-probed RESULT=fail
11233 11:14:26.435524 /lava-10591271/1/../bin/lava-test-case
11234 11:14:26.442331 <8>[ 23.024365] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass>
11235 11:14:26.442584 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-driver-present RESULT=pass
11237 11:14:27.457179 /lava-10591271/1/../bin/lava-test-case
11238 11:14:27.463648 <8>[ 24.047096] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail>
11239 11:14:27.463994 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mipi-tx-probed RESULT=fail
11241 11:14:27.474685 /lava-10591271/1/../bin/lava-test-case
11242 11:14:27.480690 <8>[ 24.062900] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass>
11243 11:14:27.481219 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-driver-present RESULT=pass
11245 11:14:28.494779 /lava-10591271/1/../bin/lava-test-case
11246 11:14:28.501647 <8>[ 25.084553] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-dsi-probed RESULT=fail>
11247 11:14:28.502357 Received signal: <TESTCASE> TEST_CASE_ID=mtk-dsi-probed RESULT=fail
11249 11:14:28.511477 /lava-10591271/1/../bin/lava-test-case
11250 11:14:28.517910 <8>[ 25.099870] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-driver-present RESULT=pass>
11251 11:14:28.518589 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-driver-present RESULT=pass
11253 11:14:29.530349 /lava-10591271/1/../bin/lava-test-case
11254 11:14:29.537246 <8>[ 26.120023] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-3-probed RESULT=fail>
11255 11:14:29.537930 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-3-probed RESULT=fail
11257 11:14:29.546409 /lava-10591271/1/../bin/lava-test-case
11258 11:14:29.552659 <8>[ 26.134993] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass>
11259 11:14:29.553447 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-driver-present RESULT=pass
11261 11:14:30.567217 /lava-10591271/1/../bin/lava-test-case
11262 11:14:30.573839 <8>[ 27.156790] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail>
11263 11:14:30.574121 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-pwm-probed RESULT=fail
11265 11:14:30.583116 /lava-10591271/1/../bin/lava-test-case
11266 11:14:30.589847 <8>[ 27.172134] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass>
11267 11:14:30.590232 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-driver-present RESULT=pass
11269 11:14:31.604135 /lava-10591271/1/../bin/lava-test-case
11270 11:14:31.610352 <8>[ 28.194607] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pwm-backlight-probed RESULT=fail>
11271 11:14:31.610618 Received signal: <TESTCASE> TEST_CASE_ID=pwm-backlight-probed RESULT=fail
11273 11:14:31.621619 /lava-10591271/1/../bin/lava-test-case
11274 11:14:31.627619 <8>[ 28.210129] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-edp-driver-present RESULT=pass>
11275 11:14:31.628443 Received signal: <TESTCASE> TEST_CASE_ID=panel-edp-driver-present RESULT=pass
11277 11:14:31.637504 /lava-10591271/1/../bin/lava-test-case
11278 11:14:31.643692 <8>[ 28.226487] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass>
11279 11:14:31.644528 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-driver-present RESULT=pass
11281 11:14:32.658496 /lava-10591271/1/../bin/lava-test-case
11282 11:14:32.665114 <8>[ 29.247764] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail>
11283 11:14:32.665967 Received signal: <TESTCASE> TEST_CASE_ID=panel-simple-dp-aux-probed RESULT=fail
11285 11:14:32.674380 /lava-10591271/1/../bin/lava-test-case
11286 11:14:32.681173 <8>[ 29.264139] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass>
11287 11:14:32.681890 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-driver-present RESULT=pass
11289 11:14:32.693340 /lava-10591271/1/../bin/lava-test-case
11290 11:14:32.699935 <8>[ 29.282399] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-mutex-probed RESULT=pass>
11291 11:14:32.700666 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-mutex-probed RESULT=pass
11293 11:14:32.709147 /lava-10591271/1/../bin/lava-test-case
11294 11:14:32.715389 <8>[ 29.298450] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass>
11295 11:14:32.716377 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl-driver-present RESULT=pass
11297 11:14:32.728733 /lava-10591271/1/../bin/lava-test-case
11298 11:14:32.735115 <8>[ 29.317987] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass>
11299 11:14:32.735367 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl0-probed RESULT=pass
11301 11:14:32.746804 /lava-10591271/1/../bin/lava-test-case
11302 11:14:32.753561 <8>[ 29.336446] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass>
11303 11:14:32.753815 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l0-probed RESULT=pass
11305 11:14:32.765330 /lava-10591271/1/../bin/lava-test-case
11306 11:14:32.771592 <8>[ 29.354815] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass>
11307 11:14:32.771875 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ovl2l2-probed RESULT=pass
11309 11:14:32.782014 /lava-10591271/1/../bin/lava-test-case
11310 11:14:32.788526 <8>[ 29.371427] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass>
11311 11:14:32.788781 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma-driver-present RESULT=pass
11313 11:14:32.801158 /lava-10591271/1/../bin/lava-test-case
11314 11:14:32.807866 <8>[ 29.390984] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass>
11315 11:14:32.808145 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma0-probed RESULT=pass
11317 11:14:32.820231 /lava-10591271/1/../bin/lava-test-case
11318 11:14:32.826432 <8>[ 29.409150] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass>
11319 11:14:32.826690 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-rdma4-probed RESULT=pass
11321 11:14:32.836146 /lava-10591271/1/../bin/lava-test-case
11322 11:14:32.842529 <8>[ 29.425510] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass>
11323 11:14:32.842775 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-driver-present RESULT=pass
11325 11:14:32.855746 /lava-10591271/1/../bin/lava-test-case
11326 11:14:32.862204 <8>[ 29.445535] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass>
11327 11:14:32.862494 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-aal-probed RESULT=pass
11329 11:14:32.871745 /lava-10591271/1/../bin/lava-test-case
11330 11:14:32.878367 <8>[ 29.461829] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass>
11331 11:14:32.878660 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-driver-present RESULT=pass
11333 11:14:32.891555 /lava-10591271/1/../bin/lava-test-case
11334 11:14:32.898118 <8>[ 29.480943] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass>
11335 11:14:32.898409 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-ccorr-probed RESULT=pass
11337 11:14:32.908000 /lava-10591271/1/../bin/lava-test-case
11338 11:14:32.915216 <8>[ 29.498010] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass>
11339 11:14:32.915489 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-driver-present RESULT=pass
11341 11:14:32.928359 /lava-10591271/1/../bin/lava-test-case
11342 11:14:32.935008 <8>[ 29.517480] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass>
11343 11:14:32.935283 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-color-probed RESULT=pass
11345 11:14:32.944441 /lava-10591271/1/../bin/lava-test-case
11346 11:14:32.951380 <8>[ 29.533980] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass>
11347 11:14:32.951631 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-driver-present RESULT=pass
11349 11:14:32.963677 /lava-10591271/1/../bin/lava-test-case
11350 11:14:32.969815 <8>[ 29.552676] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass>
11351 11:14:32.970062 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-disp-gamma-probed RESULT=pass
11353 11:14:32.979643 /lava-10591271/1/../bin/lava-test-case
11354 11:14:32.986453 <8>[ 29.569344] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass>
11355 11:14:32.986701 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-driver-present RESULT=pass
11357 11:14:32.998125 /lava-10591271/1/../bin/lava-test-case
11358 11:14:33.004940 <8>[ 29.588096] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-drm-probed RESULT=pass>
11359 11:14:33.005208 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-drm-probed RESULT=pass
11361 11:14:33.014301 /lava-10591271/1/../bin/lava-test-case
11362 11:14:33.020869 <8>[ 29.603912] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass>
11363 11:14:33.021114 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-driver-present RESULT=pass
11365 11:14:34.034554 /lava-10591271/1/../bin/lava-test-case
11366 11:14:34.040809 <8>[ 30.624386] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek-dpi-probed RESULT=fail>
11367 11:14:34.041123 Received signal: <TESTCASE> TEST_CASE_ID=mediatek-dpi-probed RESULT=fail
11369 11:14:35.054666 /lava-10591271/1/../bin/lava-test-case
11370 11:14:35.061321 <8>[ 31.645674] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=anx7625-7-probed RESULT=fail>
11371 11:14:35.061601 Received signal: <TESTCASE> TEST_CASE_ID=anx7625-7-probed RESULT=fail
11373 11:14:35.071134 /lava-10591271/1/../bin/lava-test-case
11374 11:14:35.077463 <8>[ 31.660502] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-driver-present RESULT=pass>
11375 11:14:35.077721 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-driver-present RESULT=pass
11377 11:14:35.089528 /lava-10591271/1/../bin/lava-test-case
11378 11:14:35.096405 <8>[ 31.679319] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=sbs-battery-probed RESULT=pass>
11379 11:14:35.096664 Received signal: <TESTCASE> TEST_CASE_ID=sbs-battery-probed RESULT=pass
11381 11:14:35.104979 /lava-10591271/1/../bin/lava-test-case
11382 11:14:35.111710 <8>[ 31.694918] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass>
11383 11:14:35.111968 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-driver-present RESULT=pass
11385 11:14:35.123616 /lava-10591271/1/../bin/lava-test-case
11386 11:14:35.129972 <8>[ 31.713931] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass>
11387 11:14:35.130231 Received signal: <TESTCASE> TEST_CASE_ID=mtk-pcie-gen3-probed RESULT=pass
11389 11:14:35.139758 /lava-10591271/1/../bin/lava-test-case
11390 11:14:35.146625 <8>[ 31.729172] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-driver-present RESULT=pass>
11391 11:14:35.146880 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-driver-present RESULT=pass
11393 11:14:35.157705 /lava-10591271/1/../bin/lava-test-case
11394 11:14:35.164640 <8>[ 31.747527] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt7921e-probed RESULT=pass>
11395 11:14:35.164900 Received signal: <TESTCASE> TEST_CASE_ID=mt7921e-probed RESULT=pass
11397 11:14:35.173682 /lava-10591271/1/../bin/lava-test-case
11398 11:14:35.179693 <8>[ 31.762965] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass>
11399 11:14:35.179948 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-driver-present RESULT=pass
11401 11:14:35.191951 /lava-10591271/1/../bin/lava-test-case
11402 11:14:35.199047 <8>[ 31.781899] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass>
11403 11:14:35.199305 Received signal: <TESTCASE> TEST_CASE_ID=tpm_tis_spi-probed RESULT=pass
11405 11:14:35.209259 /lava-10591271/1/../bin/lava-test-case
11406 11:14:35.214659 <8>[ 31.797333] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass>
11407 11:14:35.214920 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-driver-present RESULT=pass
11409 11:14:35.225900 /lava-10591271/1/../bin/lava-test-case
11410 11:14:35.233030 <8>[ 31.815840] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-msdc-probed RESULT=pass>
11411 11:14:35.233287 Received signal: <TESTCASE> TEST_CASE_ID=mtk-msdc-probed RESULT=pass
11413 11:14:35.241487 /lava-10591271/1/../bin/lava-test-case
11414 11:14:35.247887 <8>[ 31.830642] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass>
11415 11:14:35.248168 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-driver-present RESULT=pass
11417 11:14:35.259406 /lava-10591271/1/../bin/lava-test-case
11418 11:14:35.265986 <8>[ 31.849329] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass>
11419 11:14:35.266249 Received signal: <TESTCASE> TEST_CASE_ID=mtk-spi-nor-probed RESULT=pass
11421 11:14:35.275132 /lava-10591271/1/../bin/lava-test-case
11422 11:14:35.281591 <8>[ 31.864391] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass>
11423 11:14:35.281849 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-driver-present RESULT=pass
11425 11:14:35.293168 /lava-10591271/1/../bin/lava-test-case
11426 11:14:35.299571 <8>[ 31.883016] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-tphy-probed RESULT=pass>
11427 11:14:35.299830 Received signal: <TESTCASE> TEST_CASE_ID=mtk-tphy-probed RESULT=pass
11429 11:14:35.308171 /lava-10591271/1/../bin/lava-test-case
11430 11:14:35.314887 <8>[ 31.898294] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass>
11431 11:14:35.315159 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-driver-present RESULT=pass
11433 11:14:35.326739 /lava-10591271/1/../bin/lava-test-case
11434 11:14:35.333550 <8>[ 31.916716] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=xhci-mtk-probed RESULT=pass>
11435 11:14:35.333811 Received signal: <TESTCASE> TEST_CASE_ID=xhci-mtk-probed RESULT=pass
11437 11:14:35.341905 /lava-10591271/1/../bin/lava-test-case
11438 11:14:35.348835 <8>[ 31.931647] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-driver-present RESULT=pass>
11439 11:14:35.349096 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-driver-present RESULT=pass
11441 11:14:35.360608 /lava-10591271/1/../bin/lava-test-case
11442 11:14:35.366934 <8>[ 31.950173] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-scp-probed RESULT=pass>
11443 11:14:35.367190 Received signal: <TESTCASE> TEST_CASE_ID=mtk-scp-probed RESULT=pass
11445 11:14:35.375686 /lava-10591271/1/../bin/lava-test-case
11446 11:14:35.382343 <8>[ 31.965084] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass>
11447 11:14:35.382602 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-driver-present RESULT=pass
11449 11:14:35.394777 /lava-10591271/1/../bin/lava-test-case
11450 11:14:35.401282 <8>[ 31.984448] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass>
11451 11:14:35.401543 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-enc-probed RESULT=pass
11453 11:14:36.413139 /lava-10591271/1/../bin/lava-test-case
11454 11:14:36.419281 <8>[ 33.003699] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail>
11455 11:14:36.420062 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-driver-present RESULT=fail
11457 11:14:37.432675 /lava-10591271/1/../bin/lava-test-case
11458 11:14:37.439294 <8>[ 34.022819] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked>
11459 11:14:37.440128 Received signal: <TESTCASE> TEST_CASE_ID=mtk-vcodec-dec-probed RESULT=blocked
11460 11:14:37.440572 Bad test result: blocked
11461 11:14:37.450187 /lava-10591271/1/../bin/lava-test-case
11462 11:14:37.456553 <8>[ 34.039428] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-driver-present RESULT=pass>
11463 11:14:37.457246 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-driver-present RESULT=pass
11465 11:14:38.470195 /lava-10591271/1/../bin/lava-test-case
11466 11:14:38.476895 <8>[ 35.060545] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=panfrost-probed RESULT=fail>
11467 11:14:38.477584 Received signal: <TESTCASE> TEST_CASE_ID=panfrost-probed RESULT=fail
11469 11:14:38.486852 /lava-10591271/1/../bin/lava-test-case
11470 11:14:38.492846 <8>[ 35.076391] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo-driver-present RESULT=pass>
11471 11:14:38.493598 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo-driver-present RESULT=pass
11473 11:14:38.503875 /lava-10591271/1/../bin/lava-test-case
11474 11:14:38.510488 <8>[ 35.093619] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo0-probed RESULT=pass>
11475 11:14:38.511193 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo0-probed RESULT=pass
11477 11:14:38.521697 /lava-10591271/1/../bin/lava-test-case
11478 11:14:38.528229 <8>[ 35.111447] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=uvcvideo1-probed RESULT=pass>
11479 11:14:38.528935 Received signal: <TESTCASE> TEST_CASE_ID=uvcvideo1-probed RESULT=pass
11481 11:14:38.537318 /lava-10591271/1/../bin/lava-test-case
11482 11:14:38.543826 <8>[ 35.127025] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass>
11483 11:14:38.544633 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-driver-present RESULT=pass
11485 11:14:38.556843 /lava-10591271/1/../bin/lava-test-case
11486 11:14:38.563179 <8>[ 35.146135] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192-audio-probed RESULT=pass>
11487 11:14:38.563884 Received signal: <TESTCASE> TEST_CASE_ID=mt8192-audio-probed RESULT=pass
11489 11:14:38.572795 /lava-10591271/1/../bin/lava-test-case
11490 11:14:38.579058 <8>[ 35.162057] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-driver-present RESULT=pass>
11491 11:14:38.579790 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-driver-present RESULT=pass
11493 11:14:39.592976 /lava-10591271/1/../bin/lava-test-case
11494 11:14:39.599364 <8>[ 36.184309] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=dmic-codec-probed RESULT=fail>
11495 11:14:39.599670 Received signal: <TESTCASE> TEST_CASE_ID=dmic-codec-probed RESULT=fail
11497 11:14:39.609562 /lava-10591271/1/../bin/lava-test-case
11498 11:14:39.616248 <8>[ 36.199824] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-driver-present RESULT=pass>
11499 11:14:39.616560 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-driver-present RESULT=pass
11501 11:14:40.630106 /lava-10591271/1/../bin/lava-test-case
11502 11:14:40.636665 <8>[ 37.220945] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt5682-probed RESULT=fail>
11503 11:14:40.637099 Received signal: <TESTCASE> TEST_CASE_ID=rt5682-probed RESULT=fail
11505 11:14:40.646001 /lava-10591271/1/../bin/lava-test-case
11506 11:14:40.651963 <8>[ 37.235640] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-driver-present RESULT=pass>
11507 11:14:40.652295 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-driver-present RESULT=pass
11509 11:14:41.665574 /lava-10591271/1/../bin/lava-test-case
11510 11:14:41.672047 <8>[ 38.256455] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=rt1015p-probed RESULT=fail>
11511 11:14:41.672333 Received signal: <TESTCASE> TEST_CASE_ID=rt1015p-probed RESULT=fail
11513 11:14:41.681344 /lava-10591271/1/../bin/lava-test-case
11514 11:14:41.688292 <8>[ 38.272396] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass>
11515 11:14:41.688555 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-driver-present RESULT=pass
11517 11:14:42.703330 /lava-10591271/1/../bin/lava-test-case
11518 11:14:42.709110 <8>[ 39.294184] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail>
11519 11:14:42.709386 Received signal: <TESTCASE> TEST_CASE_ID=mt8192_mt6359-probed RESULT=fail
11521 11:14:42.719264 /lava-10591271/1/../bin/lava-test-case
11522 11:14:42.726052 <8>[ 39.310346] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb-driver-present RESULT=pass>
11523 11:14:42.726311 Received signal: <TESTCASE> TEST_CASE_ID=btusb-driver-present RESULT=pass
11525 11:14:42.738012 /lava-10591271/1/../bin/lava-test-case
11526 11:14:42.743975 <8>[ 39.327977] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb0-probed RESULT=pass>
11527 11:14:42.744261 Received signal: <TESTCASE> TEST_CASE_ID=btusb0-probed RESULT=pass
11529 11:14:42.755224 /lava-10591271/1/../bin/lava-test-case
11530 11:14:42.762086 <8>[ 39.345791] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=btusb1-probed RESULT=pass>
11531 11:14:42.762348 Received signal: <TESTCASE> TEST_CASE_ID=btusb1-probed RESULT=pass
11533 11:14:42.770993 /lava-10591271/1/../bin/lava-test-case
11534 11:14:42.777614 <8>[ 39.361394] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass>
11535 11:14:42.777890 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-driver-present RESULT=pass
11537 11:14:42.789596 /lava-10591271/1/../bin/lava-test-case
11538 11:14:42.795745 <8>[ 39.380078] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-wdt-probed RESULT=pass>
11539 11:14:42.796025 Received signal: <TESTCASE> TEST_CASE_ID=mtk-wdt-probed RESULT=pass
11541 11:14:42.804423 /lava-10591271/1/../bin/lava-test-case
11542 11:14:42.811075 <8>[ 39.394852] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass>
11543 11:14:42.811338 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-driver-present RESULT=pass
11545 11:14:42.823581 /lava-10591271/1/../bin/lava-test-case
11546 11:14:42.830329 <8>[ 39.414040] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mediatek,efuse-probed RESULT=pass>
11547 11:14:42.830616 Received signal: <TESTCASE> TEST_CASE_ID=mediatek,efuse-probed RESULT=pass
11549 11:14:42.839347 /lava-10591271/1/../bin/lava-test-case
11550 11:14:42.845595 <8>[ 39.429885] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass>
11551 11:14:42.845890 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-driver-present RESULT=pass
11553 11:14:43.860583 /lava-10591271/1/../bin/lava-test-case
11554 11:14:43.867141 <8>[ 40.452420] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=fail>
11555 11:14:43.867444 Received signal: <TESTCASE> TEST_CASE_ID=mtk-cpufreq-hw-probed RESULT=fail
11557 11:14:43.871259 + set +x
11558 11:14:43.875190 Received signal: <ENDRUN> 1_bootrr 10591271_1.5.2.3.5
11559 11:14:43.875309 Ending use of test pattern.
11560 11:14:43.875409 Ending test lava.1_bootrr (10591271_1.5.2.3.5), duration 23.30
11562 11:14:43.878256 <8>[ 40.462325] <LAVA_SIGNAL_ENDRUN 1_bootrr 10591271_1.5.2.3.5>
11563 11:14:43.878535 ok: lava_test_shell seems to have completed
11564 11:14:43.880840 all-cpus-are-online: pass
anx7625-3-probed: fail
anx7625-7-probed: fail
anx7625-driver-present: pass
btusb-driver-present: pass
btusb0-probed: pass
btusb1-probed: pass
clk-mt8192-apmixedsys-probed: pass
clk-mt8192-aud-driver-present: pass
clk-mt8192-aud-probed: pass
clk-mt8192-cam-driver-present: pass
clk-mt8192-cam-probed: pass
clk-mt8192-cam_rawa-probed: pass
clk-mt8192-cam_rawb-probed: pass
clk-mt8192-cam_rawc-probed: pass
clk-mt8192-driver-present: pass
clk-mt8192-img-driver-present: pass
clk-mt8192-img-probed: pass
clk-mt8192-img2-probed: pass
clk-mt8192-imp_iic_wrap-driver-present: pass
clk-mt8192-imp_iic_wrap_e-probed: pass
clk-mt8192-imp_iic_wrap_n-probed: pass
clk-mt8192-imp_iic_wrap_s-probed: pass
clk-mt8192-imp_iic_wrap_ws-probed: pass
clk-mt8192-infracfg-probed: pass
clk-mt8192-ipe-driver-present: pass
clk-mt8192-ipe-probed: pass
clk-mt8192-mdp-driver-present: pass
clk-mt8192-mdp-probed: pass
clk-mt8192-mfg-driver-present: pass
clk-mt8192-mfg-probed: pass
clk-mt8192-mm-driver-present: pass
clk-mt8192-mm-probed: pass
clk-mt8192-msdc-driver-present: pass
clk-mt8192-msdc-probed: pass
clk-mt8192-pericfg-probed: pass
clk-mt8192-topckgen-probed: pass
clk-mt8192-vdec-driver-present: pass
clk-mt8192-vdec-probed: pass
clk-mt8192-vdec_soc-probed: pass
clk-mt8192-venc-driver-present: pass
clk-mt8192-venc-probed: pass
cros-ec-i2c-tunnel-driver-present: pass
cros-ec-i2c-tunnel-probed: pass
cros-ec-keyb-driver-present: pass
cros-ec-keyb-probed: pass
cros-ec-pwm-driver-present: pass
cros-ec-pwm-probed: pass
cros-ec-regulator-driver-present: pass
cros-ec-regulator0-probed: pass
cros-ec-regulator1-probed: pass
cros-ec-rpmsg-driver-present: fail
cros-ec-spi-driver-present: pass
cros-ec-spi-probed: pass
cros-ec-typec-driver-present: pass
cros-ec-typec-probed: pass
deferred-probe-empty: pass
dmic-codec-driver-present: pass
dmic-codec-probed: fail
elan_i2c-driver-present: pass
elan_i2c-probed: fail
elants_i2c-driver-present: pass
elants_i2c-probed: fail
i2c-mt65xx-driver-present: pass
i2c0-mt65xx-probed: pass
i2c1-mt65xx-probed: pass
i2c2-mt65xx-probed: pass
i2c3-mt65xx-probed: pass
i2c7-mt65xx-probed: pass
leds_pwm-driver-present: pass
leds_pwm-probed: pass
mediatek,efuse-driver-present: pass
mediatek,efuse-probed: pass
mediatek-disp-aal-driver-present: pass
mediatek-disp-aal-probed: pass
mediatek-disp-ccorr-driver-present: pass
mediatek-disp-ccorr-probed: pass
mediatek-disp-color-driver-present: pass
mediatek-disp-color-probed: pass
mediatek-disp-gamma-driver-present: pass
mediatek-disp-gamma-probed: pass
mediatek-disp-ovl-driver-present: pass
mediatek-disp-ovl0-probed: pass
mediatek-disp-ovl2l0-probed: pass
mediatek-disp-ovl2l2-probed: pass
mediatek-disp-pwm-driver-present: pass
mediatek-disp-pwm-probed: fail
mediatek-disp-rdma-driver-present: pass
mediatek-disp-rdma0-probed: pass
mediatek-disp-rdma4-probed: pass
mediatek-dpi-driver-present: pass
mediatek-dpi-probed: fail
mediatek-drm-driver-present: pass
mediatek-drm-probed: pass
mediatek-mipi-tx-driver-present: pass
mediatek-mipi-tx-probed: fail
mediatek-mutex-driver-present: pass
mediatek-mutex-probed: pass
mt-pmic-pwrap-driver-present: pass
mt-pmic-pwrap-probed: pass
mt6315-regulator-driver-present: pass
mt6315-regulator6-probed: pass
mt6315-regulator7-probed: pass
mt6577-uart-driver-present: pass
mt6577-uart-probed: pass
mt7921e-driver-present: pass
mt7921e-probed: pass
mt8192-audio-driver-present: pass
mt8192-audio-probed: pass
mt8192-pinctrl-driver-present: pass
mt8192-pinctrl-probed: pass
mt8192_mt6359-driver-present: pass
mt8192_mt6359-probed: fail
mtk-cpufreq-hw-driver-present: pass
mtk-cpufreq-hw-probed: fail
mtk-dsi-driver-present: pass
mtk-dsi-probed: fail
mtk-iommu-driver-present: pass
mtk-iommu-probed: pass
mtk-mmsys-driver-present: pass
mtk-mmsys-probed: pass
mtk-msdc-driver-present: pass
mtk-msdc-probed: pass
mtk-pcie-gen3-driver-present: pass
mtk-pcie-gen3-probed: pass
mtk-power-controller-driver-present: pass
mtk-power-controller-probed: pass
mtk-scp-driver-present: pass
mtk-scp-probed: pass
mtk-smi-common-driver-present: pass
mtk-smi-common-probed: pass
mtk-smi-larb-driver-present: pass
mtk-smi-larb0-probed: pass
mtk-smi-larb1-probed: pass
mtk-smi-larb11-probed: pass
mtk-smi-larb13-probed: pass
mtk-smi-larb14-probed: pass
mtk-smi-larb16-probed: pass
mtk-smi-larb17-probed: pass
mtk-smi-larb18-probed: pass
mtk-smi-larb19-probed: pass
mtk-smi-larb2-probed: pass
mtk-smi-larb20-probed: pass
mtk-smi-larb4-probed: pass
mtk-smi-larb5-probed: pass
mtk-smi-larb7-probed: pass
mtk-smi-larb9-probed: pass
mtk-spi-driver-present: pass
mtk-spi-nor-driver-present: pass
mtk-spi-nor-probed: pass
mtk-spi1-probed: pass
mtk-spi5-probed: pass
mtk-tphy-driver-present: pass
mtk-tphy-probed: pass
mtk-vcodec-dec-driver-present: fail
mtk-vcodec-enc-driver-present: pass
mtk-vcodec-enc-probed: pass
mtk-wdt-driver-present: pass
mtk-wdt-probed: pass
panel-edp-driver-present: pass
panel-simple-dp-aux-driver-present: pass
panel-simple-dp-aux-probed: fail
panfrost-driver-present: pass
panfrost-probed: fail
pwm-backlight-driver-present: pass
pwm-backlight-probed: fail
rt1015p-driver-present: pass
rt1015p-probed: fail
rt5682-driver-present: pass
rt5682-probed: fail
sbs-battery-driver-present: pass
sbs-battery-probed: pass
spmi-mtk-driver-present: pass
spmi-mtk-probed: pass
tpm-chip-is-online: pass
tpm_tis_spi-driver-present: pass
tpm_tis_spi-probed: pass
uvcvideo-driver-present: pass
uvcvideo0-probed: pass
uvcvideo1-probed: pass
xhci-mtk-driver-present: pass
xhci-mtk-probed: pass
11565 11:14:43.881047 end: 4.1 lava-test-shell (duration 00:00:24) [common]
11566 11:14:43.881172 end: 4 lava-test-retry (duration 00:00:24) [common]
11567 11:14:43.881293 start: 5 finalize (timeout 00:07:44) [common]
11568 11:14:43.881469 start: 5.1 power-off (timeout 00:00:30) [common]
11569 11:14:43.881769 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
11570 11:14:43.958140 >> Command sent successfully.
11571 11:14:43.960778 Returned 0 in 0 seconds
11572 11:14:44.061195 end: 5.1 power-off (duration 00:00:00) [common]
11574 11:14:44.061667 start: 5.2 read-feedback (timeout 00:07:44) [common]
11576 11:14:44.062360 Listened to connection for namespace 'common' for up to 1s
11577 11:14:45.062949 Finalising connection for namespace 'common'
11578 11:14:45.063127 Disconnecting from shell: Finalise
11579 11:14:45.063211 / #
11580 11:14:45.163549 end: 5.2 read-feedback (duration 00:00:01) [common]
11581 11:14:45.163732 end: 5 finalize (duration 00:00:01) [common]
11582 11:14:45.163842 Cleaning after the job
11583 11:14:45.163947 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591271/tftp-deploy-9g1e0xbk/ramdisk
11584 11:14:45.166333 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591271/tftp-deploy-9g1e0xbk/kernel
11585 11:14:45.172187 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591271/tftp-deploy-9g1e0xbk/dtb
11586 11:14:45.172392 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591271/tftp-deploy-9g1e0xbk/modules
11587 11:14:45.177796 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10591271
11588 11:14:45.214578 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10591271
11589 11:14:45.214758 Job finished correctly