Boot log: mt8192-asurada-spherion-r0
- Errors: 3
- Kernel Errors: 1
- Boot result: FAIL
- Warnings: 1
- Kernel Warnings: 7
1 11:12:01.495816 lava-dispatcher, installed at version: 2023.05.1
2 11:12:01.496034 start: 0 validate
3 11:12:01.496171 Start time: 2023-06-05 11:12:01.496164+00:00 (UTC)
4 11:12:01.496309 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:12:01.496440 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-cros-ec%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 11:12:01.789647 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:12:01.789889 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:12:02.084806 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:12:02.084999 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:12:19.762489 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:12:19.762673 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 11:12:20.339694 validate duration: 18.84
14 11:12:20.340061 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 11:12:20.340161 start: 1.1 download-retry (timeout 00:10:00) [common]
16 11:12:20.340263 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 11:12:20.340390 Not decompressing ramdisk as can be used compressed.
18 11:12:20.340473 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-cros-ec/20230527.0/arm64/rootfs.cpio.gz
19 11:12:20.340599 saving as /var/lib/lava/dispatcher/tmp/10591235/tftp-deploy-qhjhjj89/ramdisk/rootfs.cpio.gz
20 11:12:20.340673 total size: 34405874 (32MB)
21 11:12:24.511750 progress 0% (0MB)
22 11:12:24.521118 progress 5% (1MB)
23 11:12:24.531112 progress 10% (3MB)
24 11:12:24.540651 progress 15% (4MB)
25 11:12:24.550129 progress 20% (6MB)
26 11:12:24.559760 progress 25% (8MB)
27 11:12:24.568936 progress 30% (9MB)
28 11:12:24.578419 progress 35% (11MB)
29 11:12:24.587775 progress 40% (13MB)
30 11:12:24.597330 progress 45% (14MB)
31 11:12:24.606666 progress 50% (16MB)
32 11:12:24.616313 progress 55% (18MB)
33 11:12:24.625611 progress 60% (19MB)
34 11:12:24.634747 progress 65% (21MB)
35 11:12:24.644364 progress 70% (22MB)
36 11:12:24.653692 progress 75% (24MB)
37 11:12:24.662323 progress 80% (26MB)
38 11:12:24.671117 progress 85% (27MB)
39 11:12:24.679703 progress 90% (29MB)
40 11:12:24.688343 progress 95% (31MB)
41 11:12:24.696842 progress 100% (32MB)
42 11:12:24.697107 32MB downloaded in 4.36s (7.53MB/s)
43 11:12:24.697260 end: 1.1.1 http-download (duration 00:00:04) [common]
45 11:12:24.697502 end: 1.1 download-retry (duration 00:00:04) [common]
46 11:12:24.697592 start: 1.2 download-retry (timeout 00:09:56) [common]
47 11:12:24.697678 start: 1.2.1 http-download (timeout 00:09:56) [common]
48 11:12:24.697832 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 11:12:24.697906 saving as /var/lib/lava/dispatcher/tmp/10591235/tftp-deploy-qhjhjj89/kernel/Image
50 11:12:24.697971 total size: 45746688 (43MB)
51 11:12:24.698033 No compression specified
52 11:12:24.987403 progress 0% (0MB)
53 11:12:24.999606 progress 5% (2MB)
54 11:12:25.011560 progress 10% (4MB)
55 11:12:25.023820 progress 15% (6MB)
56 11:12:25.036629 progress 20% (8MB)
57 11:12:25.048489 progress 25% (10MB)
58 11:12:25.060074 progress 30% (13MB)
59 11:12:25.071727 progress 35% (15MB)
60 11:12:25.083392 progress 40% (17MB)
61 11:12:25.095182 progress 45% (19MB)
62 11:12:25.106922 progress 50% (21MB)
63 11:12:25.118424 progress 55% (24MB)
64 11:12:25.130324 progress 60% (26MB)
65 11:12:25.142112 progress 65% (28MB)
66 11:12:25.153874 progress 70% (30MB)
67 11:12:25.165709 progress 75% (32MB)
68 11:12:25.177300 progress 80% (34MB)
69 11:12:25.188843 progress 85% (37MB)
70 11:12:25.200703 progress 90% (39MB)
71 11:12:25.212214 progress 95% (41MB)
72 11:12:25.223574 progress 100% (43MB)
73 11:12:25.223708 43MB downloaded in 0.53s (82.98MB/s)
74 11:12:25.223854 end: 1.2.1 http-download (duration 00:00:01) [common]
76 11:12:25.224083 end: 1.2 download-retry (duration 00:00:01) [common]
77 11:12:25.224198 start: 1.3 download-retry (timeout 00:09:55) [common]
78 11:12:25.224318 start: 1.3.1 http-download (timeout 00:09:55) [common]
79 11:12:25.224516 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 11:12:25.224598 saving as /var/lib/lava/dispatcher/tmp/10591235/tftp-deploy-qhjhjj89/dtb/mt8192-asurada-spherion-r0.dtb
81 11:12:25.224663 total size: 46924 (0MB)
82 11:12:25.224724 No compression specified
83 11:12:25.225834 progress 69% (0MB)
84 11:12:25.226104 progress 100% (0MB)
85 11:12:25.226256 0MB downloaded in 0.00s (28.14MB/s)
86 11:12:25.226374 end: 1.3.1 http-download (duration 00:00:00) [common]
88 11:12:25.226595 end: 1.3 download-retry (duration 00:00:00) [common]
89 11:12:25.226679 start: 1.4 download-retry (timeout 00:09:55) [common]
90 11:12:25.226762 start: 1.4.1 http-download (timeout 00:09:55) [common]
91 11:12:25.226931 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 11:12:25.227001 saving as /var/lib/lava/dispatcher/tmp/10591235/tftp-deploy-qhjhjj89/modules/modules.tar
93 11:12:25.227062 total size: 8547328 (8MB)
94 11:12:25.227122 Using unxz to decompress xz
95 11:12:25.230511 progress 0% (0MB)
96 11:12:25.253392 progress 5% (0MB)
97 11:12:25.280383 progress 10% (0MB)
98 11:12:25.308598 progress 15% (1MB)
99 11:12:25.336506 progress 20% (1MB)
100 11:12:25.365644 progress 25% (2MB)
101 11:12:25.393317 progress 30% (2MB)
102 11:12:25.422486 progress 35% (2MB)
103 11:12:25.450687 progress 40% (3MB)
104 11:12:25.480234 progress 45% (3MB)
105 11:12:25.508596 progress 50% (4MB)
106 11:12:25.535784 progress 55% (4MB)
107 11:12:25.564145 progress 60% (4MB)
108 11:12:25.593127 progress 65% (5MB)
109 11:12:25.622523 progress 70% (5MB)
110 11:12:25.652817 progress 75% (6MB)
111 11:12:25.687439 progress 80% (6MB)
112 11:12:25.713639 progress 85% (6MB)
113 11:12:25.741507 progress 90% (7MB)
114 11:12:25.768277 progress 95% (7MB)
115 11:12:25.795139 progress 100% (8MB)
116 11:12:25.801843 8MB downloaded in 0.57s (14.18MB/s)
117 11:12:25.802126 end: 1.4.1 http-download (duration 00:00:01) [common]
119 11:12:25.802427 end: 1.4 download-retry (duration 00:00:01) [common]
120 11:12:25.802520 start: 1.5 prepare-tftp-overlay (timeout 00:09:55) [common]
121 11:12:25.802615 start: 1.5.1 extract-nfsrootfs (timeout 00:09:55) [common]
122 11:12:25.802698 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 11:12:25.802785 start: 1.5.2 lava-overlay (timeout 00:09:55) [common]
124 11:12:25.803066 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10591235/lava-overlay-g8ct9cva
125 11:12:25.803222 makedir: /var/lib/lava/dispatcher/tmp/10591235/lava-overlay-g8ct9cva/lava-10591235/bin
126 11:12:25.803339 makedir: /var/lib/lava/dispatcher/tmp/10591235/lava-overlay-g8ct9cva/lava-10591235/tests
127 11:12:25.803449 makedir: /var/lib/lava/dispatcher/tmp/10591235/lava-overlay-g8ct9cva/lava-10591235/results
128 11:12:25.803561 Creating /var/lib/lava/dispatcher/tmp/10591235/lava-overlay-g8ct9cva/lava-10591235/bin/lava-add-keys
129 11:12:25.803704 Creating /var/lib/lava/dispatcher/tmp/10591235/lava-overlay-g8ct9cva/lava-10591235/bin/lava-add-sources
130 11:12:25.803830 Creating /var/lib/lava/dispatcher/tmp/10591235/lava-overlay-g8ct9cva/lava-10591235/bin/lava-background-process-start
131 11:12:25.803957 Creating /var/lib/lava/dispatcher/tmp/10591235/lava-overlay-g8ct9cva/lava-10591235/bin/lava-background-process-stop
132 11:12:25.804078 Creating /var/lib/lava/dispatcher/tmp/10591235/lava-overlay-g8ct9cva/lava-10591235/bin/lava-common-functions
133 11:12:25.804199 Creating /var/lib/lava/dispatcher/tmp/10591235/lava-overlay-g8ct9cva/lava-10591235/bin/lava-echo-ipv4
134 11:12:25.804380 Creating /var/lib/lava/dispatcher/tmp/10591235/lava-overlay-g8ct9cva/lava-10591235/bin/lava-install-packages
135 11:12:25.804501 Creating /var/lib/lava/dispatcher/tmp/10591235/lava-overlay-g8ct9cva/lava-10591235/bin/lava-installed-packages
136 11:12:25.804619 Creating /var/lib/lava/dispatcher/tmp/10591235/lava-overlay-g8ct9cva/lava-10591235/bin/lava-os-build
137 11:12:25.804738 Creating /var/lib/lava/dispatcher/tmp/10591235/lava-overlay-g8ct9cva/lava-10591235/bin/lava-probe-channel
138 11:12:25.804859 Creating /var/lib/lava/dispatcher/tmp/10591235/lava-overlay-g8ct9cva/lava-10591235/bin/lava-probe-ip
139 11:12:25.804978 Creating /var/lib/lava/dispatcher/tmp/10591235/lava-overlay-g8ct9cva/lava-10591235/bin/lava-target-ip
140 11:12:25.805098 Creating /var/lib/lava/dispatcher/tmp/10591235/lava-overlay-g8ct9cva/lava-10591235/bin/lava-target-mac
141 11:12:25.805216 Creating /var/lib/lava/dispatcher/tmp/10591235/lava-overlay-g8ct9cva/lava-10591235/bin/lava-target-storage
142 11:12:25.805340 Creating /var/lib/lava/dispatcher/tmp/10591235/lava-overlay-g8ct9cva/lava-10591235/bin/lava-test-case
143 11:12:25.805460 Creating /var/lib/lava/dispatcher/tmp/10591235/lava-overlay-g8ct9cva/lava-10591235/bin/lava-test-event
144 11:12:25.805577 Creating /var/lib/lava/dispatcher/tmp/10591235/lava-overlay-g8ct9cva/lava-10591235/bin/lava-test-feedback
145 11:12:25.805695 Creating /var/lib/lava/dispatcher/tmp/10591235/lava-overlay-g8ct9cva/lava-10591235/bin/lava-test-raise
146 11:12:25.805815 Creating /var/lib/lava/dispatcher/tmp/10591235/lava-overlay-g8ct9cva/lava-10591235/bin/lava-test-reference
147 11:12:25.805933 Creating /var/lib/lava/dispatcher/tmp/10591235/lava-overlay-g8ct9cva/lava-10591235/bin/lava-test-runner
148 11:12:25.806054 Creating /var/lib/lava/dispatcher/tmp/10591235/lava-overlay-g8ct9cva/lava-10591235/bin/lava-test-set
149 11:12:25.806173 Creating /var/lib/lava/dispatcher/tmp/10591235/lava-overlay-g8ct9cva/lava-10591235/bin/lava-test-shell
150 11:12:25.806296 Updating /var/lib/lava/dispatcher/tmp/10591235/lava-overlay-g8ct9cva/lava-10591235/bin/lava-install-packages (oe)
151 11:12:25.806443 Updating /var/lib/lava/dispatcher/tmp/10591235/lava-overlay-g8ct9cva/lava-10591235/bin/lava-installed-packages (oe)
152 11:12:25.806567 Creating /var/lib/lava/dispatcher/tmp/10591235/lava-overlay-g8ct9cva/lava-10591235/environment
153 11:12:25.806670 LAVA metadata
154 11:12:25.806745 - LAVA_JOB_ID=10591235
155 11:12:25.806811 - LAVA_DISPATCHER_IP=192.168.201.1
156 11:12:25.806996 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:55) [common]
157 11:12:25.807064 skipped lava-vland-overlay
158 11:12:25.807139 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 11:12:25.807222 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:55) [common]
160 11:12:25.807285 skipped lava-multinode-overlay
161 11:12:25.807360 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 11:12:25.807445 start: 1.5.2.3 test-definition (timeout 00:09:55) [common]
163 11:12:25.807521 Loading test definitions
164 11:12:25.807611 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:55) [common]
165 11:12:25.807684 Using /lava-10591235 at stage 0
166 11:12:25.808026 uuid=10591235_1.5.2.3.1 testdef=None
167 11:12:25.808114 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 11:12:25.808198 start: 1.5.2.3.2 test-overlay (timeout 00:09:55) [common]
169 11:12:25.808813 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 11:12:25.809035 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:55) [common]
172 11:12:25.809622 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 11:12:25.809851 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:55) [common]
175 11:12:25.810428 runner path: /var/lib/lava/dispatcher/tmp/10591235/lava-overlay-g8ct9cva/lava-10591235/0/tests/0_cros-ec test_uuid 10591235_1.5.2.3.1
176 11:12:25.810577 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 11:12:25.810786 Creating lava-test-runner.conf files
179 11:12:25.810886 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10591235/lava-overlay-g8ct9cva/lava-10591235/0 for stage 0
180 11:12:25.810974 - 0_cros-ec
181 11:12:25.811069 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 11:12:25.811153 start: 1.5.2.4 compress-overlay (timeout 00:09:55) [common]
183 11:12:25.817873 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 11:12:25.817983 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:55) [common]
185 11:12:25.818070 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 11:12:25.818160 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 11:12:25.818253 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:55) [common]
188 11:12:26.773049 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 11:12:26.773469 start: 1.5.4 extract-modules (timeout 00:09:54) [common]
190 11:12:26.773626 extracting modules file /var/lib/lava/dispatcher/tmp/10591235/tftp-deploy-qhjhjj89/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10591235/extract-overlay-ramdisk-di0inau8/ramdisk
191 11:12:27.009949 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 11:12:27.010115 start: 1.5.5 apply-overlay-tftp (timeout 00:09:53) [common]
193 11:12:27.010213 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10591235/compress-overlay-dhmkaf3s/overlay-1.5.2.4.tar.gz to ramdisk
194 11:12:27.010317 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10591235/compress-overlay-dhmkaf3s/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10591235/extract-overlay-ramdisk-di0inau8/ramdisk
195 11:12:27.016978 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 11:12:27.017100 start: 1.5.6 configure-preseed-file (timeout 00:09:53) [common]
197 11:12:27.017217 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 11:12:27.017339 start: 1.5.7 compress-ramdisk (timeout 00:09:53) [common]
199 11:12:27.017435 Building ramdisk /var/lib/lava/dispatcher/tmp/10591235/extract-overlay-ramdisk-di0inau8/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10591235/extract-overlay-ramdisk-di0inau8/ramdisk
200 11:12:27.665225 >> 269469 blocks
201 11:12:32.888768 rename /var/lib/lava/dispatcher/tmp/10591235/extract-overlay-ramdisk-di0inau8/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10591235/tftp-deploy-qhjhjj89/ramdisk/ramdisk.cpio.gz
202 11:12:32.889168 end: 1.5.7 compress-ramdisk (duration 00:00:06) [common]
203 11:12:32.889290 start: 1.5.8 prepare-kernel (timeout 00:09:47) [common]
204 11:12:32.889391 start: 1.5.8.1 prepare-fit (timeout 00:09:47) [common]
205 11:12:32.889504 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10591235/tftp-deploy-qhjhjj89/kernel/Image'
206 11:12:44.640840 Returned 0 in 11 seconds
207 11:12:44.741434 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10591235/tftp-deploy-qhjhjj89/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10591235/tftp-deploy-qhjhjj89/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10591235/tftp-deploy-qhjhjj89/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10591235/tftp-deploy-qhjhjj89/kernel/image.itb
208 11:12:45.379087 output: FIT description: Kernel Image image with one or more FDT blobs
209 11:12:45.379431 output: Created: Mon Jun 5 12:12:45 2023
210 11:12:45.379507 output: Image 0 (kernel-1)
211 11:12:45.379575 output: Description:
212 11:12:45.379637 output: Created: Mon Jun 5 12:12:45 2023
213 11:12:45.379700 output: Type: Kernel Image
214 11:12:45.379762 output: Compression: lzma compressed
215 11:12:45.379821 output: Data Size: 10086024 Bytes = 9849.63 KiB = 9.62 MiB
216 11:12:45.379882 output: Architecture: AArch64
217 11:12:45.379940 output: OS: Linux
218 11:12:45.379997 output: Load Address: 0x00000000
219 11:12:45.380056 output: Entry Point: 0x00000000
220 11:12:45.380114 output: Hash algo: crc32
221 11:12:45.380170 output: Hash value: eb1cf9b8
222 11:12:45.380224 output: Image 1 (fdt-1)
223 11:12:45.380278 output: Description: mt8192-asurada-spherion-r0
224 11:12:45.380332 output: Created: Mon Jun 5 12:12:45 2023
225 11:12:45.380387 output: Type: Flat Device Tree
226 11:12:45.380441 output: Compression: uncompressed
227 11:12:45.380495 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
228 11:12:45.380549 output: Architecture: AArch64
229 11:12:45.380603 output: Hash algo: crc32
230 11:12:45.380657 output: Hash value: 1df858fa
231 11:12:45.380711 output: Image 2 (ramdisk-1)
232 11:12:45.380765 output: Description: unavailable
233 11:12:45.380819 output: Created: Mon Jun 5 12:12:45 2023
234 11:12:45.380874 output: Type: RAMDisk Image
235 11:12:45.380928 output: Compression: Unknown Compression
236 11:12:45.380982 output: Data Size: 47370838 Bytes = 46260.58 KiB = 45.18 MiB
237 11:12:45.381037 output: Architecture: AArch64
238 11:12:45.381091 output: OS: Linux
239 11:12:45.381145 output: Load Address: unavailable
240 11:12:45.381199 output: Entry Point: unavailable
241 11:12:45.381253 output: Hash algo: crc32
242 11:12:45.381306 output: Hash value: 1d078709
243 11:12:45.381360 output: Default Configuration: 'conf-1'
244 11:12:45.381414 output: Configuration 0 (conf-1)
245 11:12:45.381468 output: Description: mt8192-asurada-spherion-r0
246 11:12:45.381522 output: Kernel: kernel-1
247 11:12:45.381576 output: Init Ramdisk: ramdisk-1
248 11:12:45.381629 output: FDT: fdt-1
249 11:12:45.381683 output: Loadables: kernel-1
250 11:12:45.381736 output:
251 11:12:45.381926 end: 1.5.8.1 prepare-fit (duration 00:00:12) [common]
252 11:12:45.382026 end: 1.5.8 prepare-kernel (duration 00:00:12) [common]
253 11:12:45.382131 end: 1.5 prepare-tftp-overlay (duration 00:00:20) [common]
254 11:12:45.382231 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:35) [common]
255 11:12:45.382307 No LXC device requested
256 11:12:45.382386 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 11:12:45.382472 start: 1.7 deploy-device-env (timeout 00:09:35) [common]
258 11:12:45.382552 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 11:12:45.382621 Checking files for TFTP limit of 4294967296 bytes.
260 11:12:45.383143 end: 1 tftp-deploy (duration 00:00:25) [common]
261 11:12:45.383248 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 11:12:45.383340 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 11:12:45.383460 substitutions:
264 11:12:45.383530 - {DTB}: 10591235/tftp-deploy-qhjhjj89/dtb/mt8192-asurada-spherion-r0.dtb
265 11:12:45.383596 - {INITRD}: 10591235/tftp-deploy-qhjhjj89/ramdisk/ramdisk.cpio.gz
266 11:12:45.383657 - {KERNEL}: 10591235/tftp-deploy-qhjhjj89/kernel/Image
267 11:12:45.383715 - {LAVA_MAC}: None
268 11:12:45.383772 - {PRESEED_CONFIG}: None
269 11:12:45.383828 - {PRESEED_LOCAL}: None
270 11:12:45.383883 - {RAMDISK}: 10591235/tftp-deploy-qhjhjj89/ramdisk/ramdisk.cpio.gz
271 11:12:45.383940 - {ROOT_PART}: None
272 11:12:45.383995 - {ROOT}: None
273 11:12:45.384050 - {SERVER_IP}: 192.168.201.1
274 11:12:45.384105 - {TEE}: None
275 11:12:45.384159 Parsed boot commands:
276 11:12:45.384214 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 11:12:45.384382 Parsed boot commands: tftpboot 192.168.201.1 10591235/tftp-deploy-qhjhjj89/kernel/image.itb 10591235/tftp-deploy-qhjhjj89/kernel/cmdline
278 11:12:45.384471 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 11:12:45.384560 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 11:12:45.384651 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 11:12:45.384736 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 11:12:45.384808 Not connected, no need to disconnect.
283 11:12:45.384882 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 11:12:45.384961 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 11:12:45.385028 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-8'
286 11:12:45.388050 Setting prompt string to ['lava-test: # ']
287 11:12:45.388386 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 11:12:45.388494 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 11:12:45.388597 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 11:12:45.388688 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 11:12:45.388889 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
292 11:12:50.522593 >> Command sent successfully.
293 11:12:50.524966 Returned 0 in 5 seconds
294 11:12:50.625315 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 11:12:50.625978 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 11:12:50.626121 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 11:12:50.626241 Setting prompt string to 'Starting depthcharge on Spherion...'
299 11:12:50.626314 Changing prompt to 'Starting depthcharge on Spherion...'
300 11:12:50.626392 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 11:12:50.626662 [Enter `^Ec?' for help]
302 11:12:50.798078
303 11:12:50.798266
304 11:12:50.798379 F0: 102B 0000
305 11:12:50.798473
306 11:12:50.798574 F3: 1001 0000 [0200]
307 11:12:50.800823
308 11:12:50.800932 F3: 1001 0000
309 11:12:50.801033
310 11:12:50.801123 F7: 102D 0000
311 11:12:50.801218
312 11:12:50.804469 F1: 0000 0000
313 11:12:50.804574
314 11:12:50.804672 V0: 0000 0000 [0001]
315 11:12:50.804765
316 11:12:50.807557 00: 0007 8000
317 11:12:50.807668
318 11:12:50.807767 01: 0000 0000
319 11:12:50.807859
320 11:12:50.810803 BP: 0C00 0209 [0000]
321 11:12:50.810937
322 11:12:50.811055 G0: 1182 0000
323 11:12:50.811118
324 11:12:50.814336 EC: 0000 0021 [4000]
325 11:12:50.814420
326 11:12:50.814486 S7: 0000 0000 [0000]
327 11:12:50.814548
328 11:12:50.817737 CC: 0000 0000 [0001]
329 11:12:50.817848
330 11:12:50.817943 T0: 0000 0040 [010F]
331 11:12:50.818035
332 11:12:50.818130 Jump to BL
333 11:12:50.821415
334 11:12:50.845137
335 11:12:50.845224
336 11:12:50.845290
337 11:12:50.852047 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 11:12:50.855882 ARM64: Exception handlers installed.
339 11:12:50.859217 ARM64: Testing exception
340 11:12:50.862726 ARM64: Done test exception
341 11:12:50.869172 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 11:12:50.879433 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 11:12:50.885840 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 11:12:50.895979 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 11:12:50.902768 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 11:12:50.909458 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 11:12:50.921083 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 11:12:50.927937 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 11:12:50.947748 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 11:12:50.950913 WDT: Last reset was cold boot
351 11:12:50.953993 SPI1(PAD0) initialized at 2873684 Hz
352 11:12:50.957462 SPI5(PAD0) initialized at 992727 Hz
353 11:12:50.960880 VBOOT: Loading verstage.
354 11:12:50.967619 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 11:12:50.970595 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 11:12:50.974131 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 11:12:50.977173 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 11:12:50.985237 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 11:12:50.991614 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 11:12:51.002729 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 11:12:51.002815
362 11:12:51.002919
363 11:12:51.012652 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 11:12:51.015541 ARM64: Exception handlers installed.
365 11:12:51.019572 ARM64: Testing exception
366 11:12:51.019645 ARM64: Done test exception
367 11:12:51.026116 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 11:12:51.029683 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 11:12:51.043530 Probing TPM: . done!
370 11:12:51.043614 TPM ready after 0 ms
371 11:12:51.050454 Connected to device vid:did:rid of 1ae0:0028:00
372 11:12:51.060063 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
373 11:12:51.099609 Initialized TPM device CR50 revision 0
374 11:12:51.111154 tlcl_send_startup: Startup return code is 0
375 11:12:51.111243 TPM: setup succeeded
376 11:12:51.122739 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 11:12:51.131401 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 11:12:51.142717 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 11:12:51.153886 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 11:12:51.157243 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 11:12:51.160801 in-header: 03 07 00 00 08 00 00 00
382 11:12:51.164574 in-data: aa e4 47 04 13 02 00 00
383 11:12:51.164680 Chrome EC: UHEPI supported
384 11:12:51.171573 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 11:12:51.175422 in-header: 03 9d 00 00 08 00 00 00
386 11:12:51.178629 in-data: 10 20 20 08 00 00 00 00
387 11:12:51.178712 Phase 1
388 11:12:51.185622 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 11:12:51.189446 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 11:12:51.196564 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 11:12:51.200076 Recovery requested (1009000e)
392 11:12:51.205918 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 11:12:51.211426 tlcl_extend: response is 0
394 11:12:51.219830 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 11:12:51.224924 tlcl_extend: response is 0
396 11:12:51.231405 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 11:12:51.252574 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 11:12:51.258824 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 11:12:51.258915
400 11:12:51.258981
401 11:12:51.269747 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 11:12:51.273493 ARM64: Exception handlers installed.
403 11:12:51.273627 ARM64: Testing exception
404 11:12:51.276703 ARM64: Done test exception
405 11:12:51.297725 pmic_efuse_setting: Set efuses in 11 msecs
406 11:12:51.301001 pmwrap_interface_init: Select PMIF_VLD_RDY
407 11:12:51.308466 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 11:12:51.312144 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 11:12:51.315829 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 11:12:51.323182 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 11:12:51.326995 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 11:12:51.330112 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 11:12:51.337673 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 11:12:51.341508 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 11:12:51.344951 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 11:12:51.351508 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 11:12:51.354476 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 11:12:51.357836 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 11:12:51.364567 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 11:12:51.371064 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 11:12:51.374775 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 11:12:51.381178 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 11:12:51.388072 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 11:12:51.391141 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 11:12:51.397770 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 11:12:51.405052 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 11:12:51.408629 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 11:12:51.415877 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 11:12:51.419518 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 11:12:51.425950 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 11:12:51.429605 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 11:12:51.435901 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 11:12:51.442957 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 11:12:51.446657 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 11:12:51.450367 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 11:12:51.456697 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 11:12:51.460371 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 11:12:51.467025 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 11:12:51.470736 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 11:12:51.478218 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 11:12:51.482100 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 11:12:51.486045 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 11:12:51.492951 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 11:12:51.496078 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 11:12:51.502216 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 11:12:51.505846 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 11:12:51.508873 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 11:12:51.512489 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 11:12:51.518874 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 11:12:51.522320 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 11:12:51.525781 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 11:12:51.532333 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 11:12:51.535204 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 11:12:51.539068 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 11:12:51.545424 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 11:12:51.548526 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 11:12:51.552244 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 11:12:51.561759 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 11:12:51.568592 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 11:12:51.571723 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 11:12:51.582245 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 11:12:51.588550 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 11:12:51.595690 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 11:12:51.598723 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 11:12:51.601968 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 11:12:51.610271 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
467 11:12:51.616865 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 11:12:51.620405 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 11:12:51.623241 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 11:12:51.634558 [RTC]rtc_get_frequency_meter,154: input=15, output=793
471 11:12:51.638140 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
472 11:12:51.644438 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
473 11:12:51.648047 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
474 11:12:51.651280 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
475 11:12:51.654437 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
476 11:12:51.658187 ADC[4]: Raw value=897040 ID=7
477 11:12:51.661519 ADC[3]: Raw value=213440 ID=1
478 11:12:51.664754 RAM Code: 0x71
479 11:12:51.668262 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
480 11:12:51.671779 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
481 11:12:51.682623 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
482 11:12:51.686397 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
483 11:12:51.690122 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
484 11:12:51.694005 in-header: 03 07 00 00 08 00 00 00
485 11:12:51.697043 in-data: aa e4 47 04 13 02 00 00
486 11:12:51.700880 Chrome EC: UHEPI supported
487 11:12:51.708332 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
488 11:12:51.711386 in-header: 03 95 00 00 08 00 00 00
489 11:12:51.715562 in-data: 18 20 20 08 00 00 00 00
490 11:12:51.719147 MRC: failed to locate region type 0.
491 11:12:51.722934 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
492 11:12:51.726355 DRAM-K: Running full calibration
493 11:12:51.733545 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
494 11:12:51.733672 header.status = 0x0
495 11:12:51.737698 header.version = 0x6 (expected: 0x6)
496 11:12:51.741471 header.size = 0xd00 (expected: 0xd00)
497 11:12:51.744952 header.flags = 0x0
498 11:12:51.748599 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
499 11:12:51.766805 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
500 11:12:51.773570 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
501 11:12:51.776727 dram_init: ddr_geometry: 2
502 11:12:51.780239 [EMI] MDL number = 2
503 11:12:51.780326 [EMI] Get MDL freq = 0
504 11:12:51.783673 dram_init: ddr_type: 0
505 11:12:51.783758 is_discrete_lpddr4: 1
506 11:12:51.787441 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
507 11:12:51.787526
508 11:12:51.787662
509 11:12:51.790612 [Bian_co] ETT version 0.0.0.1
510 11:12:51.794407 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
511 11:12:51.794520
512 11:12:51.798194 dramc_set_vcore_voltage set vcore to 650000
513 11:12:51.802053 Read voltage for 800, 4
514 11:12:51.802138 Vio18 = 0
515 11:12:51.805873 Vcore = 650000
516 11:12:51.805959 Vdram = 0
517 11:12:51.806025 Vddq = 0
518 11:12:51.806087 Vmddr = 0
519 11:12:51.809177 dram_init: config_dvfs: 1
520 11:12:51.815475 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
521 11:12:51.819177 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
522 11:12:51.822198 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
523 11:12:51.828735 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
524 11:12:51.832284 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
525 11:12:51.835606 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
526 11:12:51.835691 MEM_TYPE=3, freq_sel=18
527 11:12:51.838665 sv_algorithm_assistance_LP4_1600
528 11:12:51.845127 ============ PULL DRAM RESETB DOWN ============
529 11:12:51.848483 ========== PULL DRAM RESETB DOWN end =========
530 11:12:51.851874 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
531 11:12:51.855461 ===================================
532 11:12:51.858704 LPDDR4 DRAM CONFIGURATION
533 11:12:51.861955 ===================================
534 11:12:51.864907 EX_ROW_EN[0] = 0x0
535 11:12:51.865009 EX_ROW_EN[1] = 0x0
536 11:12:51.868151 LP4Y_EN = 0x0
537 11:12:51.868234 WORK_FSP = 0x0
538 11:12:51.872019 WL = 0x2
539 11:12:51.872104 RL = 0x2
540 11:12:51.874971 BL = 0x2
541 11:12:51.875055 RPST = 0x0
542 11:12:51.877885 RD_PRE = 0x0
543 11:12:51.877984 WR_PRE = 0x1
544 11:12:51.881368 WR_PST = 0x0
545 11:12:51.881452 DBI_WR = 0x0
546 11:12:51.884887 DBI_RD = 0x0
547 11:12:51.887704 OTF = 0x1
548 11:12:51.891328 ===================================
549 11:12:51.894372 ===================================
550 11:12:51.894455 ANA top config
551 11:12:51.898107 ===================================
552 11:12:51.901339 DLL_ASYNC_EN = 0
553 11:12:51.901423 ALL_SLAVE_EN = 1
554 11:12:51.904523 NEW_RANK_MODE = 1
555 11:12:51.907705 DLL_IDLE_MODE = 1
556 11:12:51.911021 LP45_APHY_COMB_EN = 1
557 11:12:51.914621 TX_ODT_DIS = 1
558 11:12:51.914707 NEW_8X_MODE = 1
559 11:12:51.917807 ===================================
560 11:12:51.921029 ===================================
561 11:12:51.924116 data_rate = 1600
562 11:12:51.927825 CKR = 1
563 11:12:51.931232 DQ_P2S_RATIO = 8
564 11:12:51.934731 ===================================
565 11:12:51.937493 CA_P2S_RATIO = 8
566 11:12:51.940980 DQ_CA_OPEN = 0
567 11:12:51.941064 DQ_SEMI_OPEN = 0
568 11:12:51.944380 CA_SEMI_OPEN = 0
569 11:12:51.947386 CA_FULL_RATE = 0
570 11:12:51.950917 DQ_CKDIV4_EN = 1
571 11:12:51.954398 CA_CKDIV4_EN = 1
572 11:12:51.957464 CA_PREDIV_EN = 0
573 11:12:51.957547 PH8_DLY = 0
574 11:12:51.960962 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
575 11:12:51.963865 DQ_AAMCK_DIV = 4
576 11:12:51.967614 CA_AAMCK_DIV = 4
577 11:12:51.970821 CA_ADMCK_DIV = 4
578 11:12:51.973822 DQ_TRACK_CA_EN = 0
579 11:12:51.973906 CA_PICK = 800
580 11:12:51.977552 CA_MCKIO = 800
581 11:12:51.980699 MCKIO_SEMI = 0
582 11:12:51.983767 PLL_FREQ = 3068
583 11:12:51.987234 DQ_UI_PI_RATIO = 32
584 11:12:51.990640 CA_UI_PI_RATIO = 0
585 11:12:51.994143 ===================================
586 11:12:51.997647 ===================================
587 11:12:51.997732 memory_type:LPDDR4
588 11:12:52.001369 GP_NUM : 10
589 11:12:52.004487 SRAM_EN : 1
590 11:12:52.004572 MD32_EN : 0
591 11:12:52.008424 ===================================
592 11:12:52.012110 [ANA_INIT] >>>>>>>>>>>>>>
593 11:12:52.015253 <<<<<< [CONFIGURE PHASE]: ANA_TX
594 11:12:52.015344 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
595 11:12:52.019029 ===================================
596 11:12:52.022713 data_rate = 1600,PCW = 0X7600
597 11:12:52.026551 ===================================
598 11:12:52.030419 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
599 11:12:52.033507 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
600 11:12:52.040878 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
601 11:12:52.044931 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
602 11:12:52.048469 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
603 11:12:52.051906 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
604 11:12:52.055488 [ANA_INIT] flow start
605 11:12:52.055597 [ANA_INIT] PLL >>>>>>>>
606 11:12:52.058971 [ANA_INIT] PLL <<<<<<<<
607 11:12:52.062443 [ANA_INIT] MIDPI >>>>>>>>
608 11:12:52.062551 [ANA_INIT] MIDPI <<<<<<<<
609 11:12:52.066158 [ANA_INIT] DLL >>>>>>>>
610 11:12:52.066273 [ANA_INIT] flow end
611 11:12:52.073636 ============ LP4 DIFF to SE enter ============
612 11:12:52.077158 ============ LP4 DIFF to SE exit ============
613 11:12:52.077275 [ANA_INIT] <<<<<<<<<<<<<
614 11:12:52.081036 [Flow] Enable top DCM control >>>>>
615 11:12:52.084836 [Flow] Enable top DCM control <<<<<
616 11:12:52.088013 Enable DLL master slave shuffle
617 11:12:52.095212 ==============================================================
618 11:12:52.095348 Gating Mode config
619 11:12:52.102769 ==============================================================
620 11:12:52.102930 Config description:
621 11:12:52.113966 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
622 11:12:52.117212 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
623 11:12:52.124920 SELPH_MODE 0: By rank 1: By Phase
624 11:12:52.128691 ==============================================================
625 11:12:52.131912 GAT_TRACK_EN = 1
626 11:12:52.135706 RX_GATING_MODE = 2
627 11:12:52.139474 RX_GATING_TRACK_MODE = 2
628 11:12:52.142502 SELPH_MODE = 1
629 11:12:52.142612 PICG_EARLY_EN = 1
630 11:12:52.146281 VALID_LAT_VALUE = 1
631 11:12:52.154038 ==============================================================
632 11:12:52.157490 Enter into Gating configuration >>>>
633 11:12:52.160987 Exit from Gating configuration <<<<
634 11:12:52.161086 Enter into DVFS_PRE_config >>>>>
635 11:12:52.171998 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
636 11:12:52.175535 Exit from DVFS_PRE_config <<<<<
637 11:12:52.179496 Enter into PICG configuration >>>>
638 11:12:52.183332 Exit from PICG configuration <<<<
639 11:12:52.186506 [RX_INPUT] configuration >>>>>
640 11:12:52.190980 [RX_INPUT] configuration <<<<<
641 11:12:52.194000 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
642 11:12:52.198391 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
643 11:12:52.205201 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
644 11:12:52.212693 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
645 11:12:52.216382 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
646 11:12:52.224176 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
647 11:12:52.227807 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
648 11:12:52.231031 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
649 11:12:52.235490 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
650 11:12:52.238742 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
651 11:12:52.242529 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
652 11:12:52.249984 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
653 11:12:52.253705 ===================================
654 11:12:52.253789 LPDDR4 DRAM CONFIGURATION
655 11:12:52.257475 ===================================
656 11:12:52.260947 EX_ROW_EN[0] = 0x0
657 11:12:52.261058 EX_ROW_EN[1] = 0x0
658 11:12:52.264452 LP4Y_EN = 0x0
659 11:12:52.264558 WORK_FSP = 0x0
660 11:12:52.268535 WL = 0x2
661 11:12:52.268622 RL = 0x2
662 11:12:52.272057 BL = 0x2
663 11:12:52.272141 RPST = 0x0
664 11:12:52.275616 RD_PRE = 0x0
665 11:12:52.275703 WR_PRE = 0x1
666 11:12:52.275776 WR_PST = 0x0
667 11:12:52.279374 DBI_WR = 0x0
668 11:12:52.279459 DBI_RD = 0x0
669 11:12:52.283067 OTF = 0x1
670 11:12:52.286480 ===================================
671 11:12:52.290785 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
672 11:12:52.294563 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
673 11:12:52.298202 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
674 11:12:52.301768 ===================================
675 11:12:52.305506 LPDDR4 DRAM CONFIGURATION
676 11:12:52.309546 ===================================
677 11:12:52.309633 EX_ROW_EN[0] = 0x10
678 11:12:52.312917 EX_ROW_EN[1] = 0x0
679 11:12:52.313003 LP4Y_EN = 0x0
680 11:12:52.316064 WORK_FSP = 0x0
681 11:12:52.316148 WL = 0x2
682 11:12:52.320166 RL = 0x2
683 11:12:52.320250 BL = 0x2
684 11:12:52.323573 RPST = 0x0
685 11:12:52.323658 RD_PRE = 0x0
686 11:12:52.323725 WR_PRE = 0x1
687 11:12:52.327438 WR_PST = 0x0
688 11:12:52.327523 DBI_WR = 0x0
689 11:12:52.330623 DBI_RD = 0x0
690 11:12:52.330707 OTF = 0x1
691 11:12:52.334471 ===================================
692 11:12:52.341422 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
693 11:12:52.345265 nWR fixed to 40
694 11:12:52.348461 [ModeRegInit_LP4] CH0 RK0
695 11:12:52.348546 [ModeRegInit_LP4] CH0 RK1
696 11:12:52.351521 [ModeRegInit_LP4] CH1 RK0
697 11:12:52.355334 [ModeRegInit_LP4] CH1 RK1
698 11:12:52.355418 match AC timing 13
699 11:12:52.361591 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
700 11:12:52.365551 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
701 11:12:52.368211 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
702 11:12:52.375044 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
703 11:12:52.378139 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
704 11:12:52.381704 [EMI DOE] emi_dcm 0
705 11:12:52.384783 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
706 11:12:52.384869 ==
707 11:12:52.388154 Dram Type= 6, Freq= 0, CH_0, rank 0
708 11:12:52.391614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
709 11:12:52.391700 ==
710 11:12:52.398007 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
711 11:12:52.404718 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
712 11:12:52.412788 [CA 0] Center 38 (7~69) winsize 63
713 11:12:52.416485 [CA 1] Center 37 (7~68) winsize 62
714 11:12:52.419550 [CA 2] Center 35 (5~66) winsize 62
715 11:12:52.422587 [CA 3] Center 35 (5~66) winsize 62
716 11:12:52.426112 [CA 4] Center 34 (4~65) winsize 62
717 11:12:52.429560 [CA 5] Center 34 (4~65) winsize 62
718 11:12:52.429645
719 11:12:52.432761 [CmdBusTrainingLP45] Vref(ca) range 1: 34
720 11:12:52.432846
721 11:12:52.435745 [CATrainingPosCal] consider 1 rank data
722 11:12:52.439593 u2DelayCellTimex100 = 270/100 ps
723 11:12:52.442658 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
724 11:12:52.449543 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
725 11:12:52.452867 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
726 11:12:52.455758 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
727 11:12:52.458939 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
728 11:12:52.462640 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
729 11:12:52.462725
730 11:12:52.465791 CA PerBit enable=1, Macro0, CA PI delay=34
731 11:12:52.465876
732 11:12:52.468884 [CBTSetCACLKResult] CA Dly = 34
733 11:12:52.468969 CS Dly: 6 (0~37)
734 11:12:52.472563 ==
735 11:12:52.475491 Dram Type= 6, Freq= 0, CH_0, rank 1
736 11:12:52.479024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
737 11:12:52.479118 ==
738 11:12:52.482431 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
739 11:12:52.488709 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
740 11:12:52.499162 [CA 0] Center 38 (7~69) winsize 63
741 11:12:52.502628 [CA 1] Center 38 (7~69) winsize 63
742 11:12:52.505549 [CA 2] Center 35 (5~66) winsize 62
743 11:12:52.509222 [CA 3] Center 35 (5~66) winsize 62
744 11:12:52.512545 [CA 4] Center 34 (4~65) winsize 62
745 11:12:52.515703 [CA 5] Center 34 (4~65) winsize 62
746 11:12:52.515788
747 11:12:52.519119 [CmdBusTrainingLP45] Vref(ca) range 1: 34
748 11:12:52.519203
749 11:12:52.522491 [CATrainingPosCal] consider 2 rank data
750 11:12:52.525687 u2DelayCellTimex100 = 270/100 ps
751 11:12:52.528844 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
752 11:12:52.535834 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
753 11:12:52.538915 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
754 11:12:52.542150 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
755 11:12:52.546049 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
756 11:12:52.548886 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
757 11:12:52.548971
758 11:12:52.552036 CA PerBit enable=1, Macro0, CA PI delay=34
759 11:12:52.552124
760 11:12:52.555221 [CBTSetCACLKResult] CA Dly = 34
761 11:12:52.555309 CS Dly: 6 (0~38)
762 11:12:52.555385
763 11:12:52.562016 ----->DramcWriteLeveling(PI) begin...
764 11:12:52.562125 ==
765 11:12:52.565195 Dram Type= 6, Freq= 0, CH_0, rank 0
766 11:12:52.568558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
767 11:12:52.568635 ==
768 11:12:52.572140 Write leveling (Byte 0): 32 => 32
769 11:12:52.575384 Write leveling (Byte 1): 29 => 29
770 11:12:52.578497 DramcWriteLeveling(PI) end<-----
771 11:12:52.578608
772 11:12:52.578708 ==
773 11:12:52.582201 Dram Type= 6, Freq= 0, CH_0, rank 0
774 11:12:52.585140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
775 11:12:52.585219 ==
776 11:12:52.588531 [Gating] SW mode calibration
777 11:12:52.595033 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
778 11:12:52.602149 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
779 11:12:52.604782 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
780 11:12:52.608211 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
781 11:12:52.615467 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
782 11:12:52.618223 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
783 11:12:52.621599 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
784 11:12:52.628401 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
785 11:12:52.631787 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 11:12:52.634601 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 11:12:52.641308 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 11:12:52.645016 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 11:12:52.648703 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 11:12:52.651856 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 11:12:52.658779 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 11:12:52.662973 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 11:12:52.666157 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 11:12:52.669388 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 11:12:52.676486 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 11:12:52.679660 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
797 11:12:52.683431 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
798 11:12:52.689613 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
799 11:12:52.693452 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 11:12:52.696590 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 11:12:52.703164 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 11:12:52.706357 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 11:12:52.709862 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 11:12:52.716356 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 11:12:52.719894 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 11:12:52.722963 0 9 12 | B1->B0 | 2525 2d2d | 1 0 | (0 0) (1 1)
807 11:12:52.726483 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
808 11:12:52.732782 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
809 11:12:52.736528 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
810 11:12:52.739593 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
811 11:12:52.746465 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 11:12:52.749434 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 11:12:52.753092 0 10 8 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 0)
814 11:12:52.759470 0 10 12 | B1->B0 | 2f2f 2626 | 0 0 | (0 1) (1 1)
815 11:12:52.762892 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 11:12:52.766282 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 11:12:52.773166 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 11:12:52.776428 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 11:12:52.779657 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 11:12:52.785874 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 11:12:52.789707 0 11 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
822 11:12:52.793027 0 11 12 | B1->B0 | 3636 3c3c | 1 0 | (0 0) (0 0)
823 11:12:52.799571 0 11 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
824 11:12:52.802501 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
825 11:12:52.806076 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
826 11:12:52.812309 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 11:12:52.815698 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 11:12:52.819188 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 11:12:52.825520 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
830 11:12:52.829193 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
831 11:12:52.832213 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
832 11:12:52.839379 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
833 11:12:52.842619 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 11:12:52.845716 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 11:12:52.852504 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 11:12:52.855430 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 11:12:52.859069 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 11:12:52.865439 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 11:12:52.869176 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 11:12:52.872166 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 11:12:52.878565 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 11:12:52.882358 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 11:12:52.885456 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 11:12:52.892422 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 11:12:52.895516 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
846 11:12:52.898634 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
847 11:12:52.902391 Total UI for P1: 0, mck2ui 16
848 11:12:52.905400 best dqsien dly found for B0: ( 0, 14, 8)
849 11:12:52.908418 Total UI for P1: 0, mck2ui 16
850 11:12:52.912206 best dqsien dly found for B1: ( 0, 14, 10)
851 11:12:52.915313 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
852 11:12:52.918972 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
853 11:12:52.919055
854 11:12:52.922057 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
855 11:12:52.928330 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
856 11:12:52.928414 [Gating] SW calibration Done
857 11:12:52.928481 ==
858 11:12:52.931908 Dram Type= 6, Freq= 0, CH_0, rank 0
859 11:12:52.938745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
860 11:12:52.938854 ==
861 11:12:52.938936 RX Vref Scan: 0
862 11:12:52.938998
863 11:12:52.941687 RX Vref 0 -> 0, step: 1
864 11:12:52.941770
865 11:12:52.945122 RX Delay -130 -> 252, step: 16
866 11:12:52.948751 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
867 11:12:52.951978 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
868 11:12:52.954978 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
869 11:12:52.961571 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
870 11:12:52.964863 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
871 11:12:52.968342 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
872 11:12:52.971711 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
873 11:12:52.974665 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
874 11:12:52.981752 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
875 11:12:52.985212 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
876 11:12:52.988028 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
877 11:12:52.991231 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
878 11:12:52.995067 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
879 11:12:53.001407 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
880 11:12:53.005091 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
881 11:12:53.008277 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
882 11:12:53.008362 ==
883 11:12:53.011207 Dram Type= 6, Freq= 0, CH_0, rank 0
884 11:12:53.014809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
885 11:12:53.014932 ==
886 11:12:53.018017 DQS Delay:
887 11:12:53.018100 DQS0 = 0, DQS1 = 0
888 11:12:53.021136 DQM Delay:
889 11:12:53.021220 DQM0 = 80, DQM1 = 69
890 11:12:53.024671 DQ Delay:
891 11:12:53.024754 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
892 11:12:53.027995 DQ4 =77, DQ5 =69, DQ6 =85, DQ7 =93
893 11:12:53.031375 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
894 11:12:53.034291 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
895 11:12:53.034374
896 11:12:53.034441
897 11:12:53.037893 ==
898 11:12:53.041454 Dram Type= 6, Freq= 0, CH_0, rank 0
899 11:12:53.044333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
900 11:12:53.044417 ==
901 11:12:53.044483
902 11:12:53.044545
903 11:12:53.048420 TX Vref Scan disable
904 11:12:53.048503 == TX Byte 0 ==
905 11:12:53.051576 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
906 11:12:53.058144 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
907 11:12:53.058229 == TX Byte 1 ==
908 11:12:53.061367 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
909 11:12:53.068177 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
910 11:12:53.068262 ==
911 11:12:53.071223 Dram Type= 6, Freq= 0, CH_0, rank 0
912 11:12:53.074435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
913 11:12:53.074518 ==
914 11:12:53.088282 TX Vref=22, minBit 1, minWin=27, winSum=434
915 11:12:53.091497 TX Vref=24, minBit 4, minWin=27, winSum=439
916 11:12:53.094640 TX Vref=26, minBit 0, minWin=27, winSum=446
917 11:12:53.097792 TX Vref=28, minBit 5, minWin=27, winSum=445
918 11:12:53.101600 TX Vref=30, minBit 11, minWin=27, winSum=445
919 11:12:53.107971 TX Vref=32, minBit 2, minWin=27, winSum=442
920 11:12:53.111128 [TxChooseVref] Worse bit 0, Min win 27, Win sum 446, Final Vref 26
921 11:12:53.111212
922 11:12:53.114656 Final TX Range 1 Vref 26
923 11:12:53.114740
924 11:12:53.114806 ==
925 11:12:53.117835 Dram Type= 6, Freq= 0, CH_0, rank 0
926 11:12:53.121030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
927 11:12:53.124884 ==
928 11:12:53.124968
929 11:12:53.125034
930 11:12:53.125096 TX Vref Scan disable
931 11:12:53.128006 == TX Byte 0 ==
932 11:12:53.131085 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
933 11:12:53.137967 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
934 11:12:53.138052 == TX Byte 1 ==
935 11:12:53.141272 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
936 11:12:53.147902 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
937 11:12:53.148024
938 11:12:53.148127 [DATLAT]
939 11:12:53.148236 Freq=800, CH0 RK0
940 11:12:53.148337
941 11:12:53.151423 DATLAT Default: 0xa
942 11:12:53.151532 0, 0xFFFF, sum = 0
943 11:12:53.154309 1, 0xFFFF, sum = 0
944 11:12:53.157859 2, 0xFFFF, sum = 0
945 11:12:53.157943 3, 0xFFFF, sum = 0
946 11:12:53.161230 4, 0xFFFF, sum = 0
947 11:12:53.161316 5, 0xFFFF, sum = 0
948 11:12:53.164218 6, 0xFFFF, sum = 0
949 11:12:53.164303 7, 0xFFFF, sum = 0
950 11:12:53.167687 8, 0xFFFF, sum = 0
951 11:12:53.167772 9, 0x0, sum = 1
952 11:12:53.171040 10, 0x0, sum = 2
953 11:12:53.171124 11, 0x0, sum = 3
954 11:12:53.171191 12, 0x0, sum = 4
955 11:12:53.174459 best_step = 10
956 11:12:53.174543
957 11:12:53.174608 ==
958 11:12:53.177457 Dram Type= 6, Freq= 0, CH_0, rank 0
959 11:12:53.181365 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 11:12:53.181505 ==
961 11:12:53.184436 RX Vref Scan: 1
962 11:12:53.184511
963 11:12:53.187636 Set Vref Range= 32 -> 127
964 11:12:53.187723
965 11:12:53.187809 RX Vref 32 -> 127, step: 1
966 11:12:53.187890
967 11:12:53.191394 RX Delay -111 -> 252, step: 8
968 11:12:53.191480
969 11:12:53.194537 Set Vref, RX VrefLevel [Byte0]: 32
970 11:12:53.197657 [Byte1]: 32
971 11:12:53.200757
972 11:12:53.200843 Set Vref, RX VrefLevel [Byte0]: 33
973 11:12:53.204590 [Byte1]: 33
974 11:12:53.208841
975 11:12:53.208930 Set Vref, RX VrefLevel [Byte0]: 34
976 11:12:53.212366 [Byte1]: 34
977 11:12:53.216349
978 11:12:53.216433 Set Vref, RX VrefLevel [Byte0]: 35
979 11:12:53.219462 [Byte1]: 35
980 11:12:53.223861
981 11:12:53.223971 Set Vref, RX VrefLevel [Byte0]: 36
982 11:12:53.227039 [Byte1]: 36
983 11:12:53.231470
984 11:12:53.231549 Set Vref, RX VrefLevel [Byte0]: 37
985 11:12:53.235230 [Byte1]: 37
986 11:12:53.239436
987 11:12:53.239525 Set Vref, RX VrefLevel [Byte0]: 38
988 11:12:53.242227 [Byte1]: 38
989 11:12:53.246751
990 11:12:53.246891 Set Vref, RX VrefLevel [Byte0]: 39
991 11:12:53.250376 [Byte1]: 39
992 11:12:53.254456
993 11:12:53.254546 Set Vref, RX VrefLevel [Byte0]: 40
994 11:12:53.257418 [Byte1]: 40
995 11:12:53.262102
996 11:12:53.262215 Set Vref, RX VrefLevel [Byte0]: 41
997 11:12:53.265522 [Byte1]: 41
998 11:12:53.269787
999 11:12:53.269875 Set Vref, RX VrefLevel [Byte0]: 42
1000 11:12:53.272968 [Byte1]: 42
1001 11:12:53.277294
1002 11:12:53.277411 Set Vref, RX VrefLevel [Byte0]: 43
1003 11:12:53.280811 [Byte1]: 43
1004 11:12:53.285000
1005 11:12:53.285120 Set Vref, RX VrefLevel [Byte0]: 44
1006 11:12:53.288584 [Byte1]: 44
1007 11:12:53.292881
1008 11:12:53.292971 Set Vref, RX VrefLevel [Byte0]: 45
1009 11:12:53.296018 [Byte1]: 45
1010 11:12:53.300430
1011 11:12:53.300509 Set Vref, RX VrefLevel [Byte0]: 46
1012 11:12:53.303568 [Byte1]: 46
1013 11:12:53.308570
1014 11:12:53.308656 Set Vref, RX VrefLevel [Byte0]: 47
1015 11:12:53.311780 [Byte1]: 47
1016 11:12:53.316200
1017 11:12:53.316332 Set Vref, RX VrefLevel [Byte0]: 48
1018 11:12:53.319448 [Byte1]: 48
1019 11:12:53.323584
1020 11:12:53.323694 Set Vref, RX VrefLevel [Byte0]: 49
1021 11:12:53.326714 [Byte1]: 49
1022 11:12:53.331289
1023 11:12:53.331380 Set Vref, RX VrefLevel [Byte0]: 50
1024 11:12:53.334410 [Byte1]: 50
1025 11:12:53.338932
1026 11:12:53.339014 Set Vref, RX VrefLevel [Byte0]: 51
1027 11:12:53.342286 [Byte1]: 51
1028 11:12:53.346343
1029 11:12:53.346424 Set Vref, RX VrefLevel [Byte0]: 52
1030 11:12:53.349366 [Byte1]: 52
1031 11:12:53.353986
1032 11:12:53.354068 Set Vref, RX VrefLevel [Byte0]: 53
1033 11:12:53.357362 [Byte1]: 53
1034 11:12:53.361489
1035 11:12:53.361570 Set Vref, RX VrefLevel [Byte0]: 54
1036 11:12:53.364950 [Byte1]: 54
1037 11:12:53.369102
1038 11:12:53.369184 Set Vref, RX VrefLevel [Byte0]: 55
1039 11:12:53.372675 [Byte1]: 55
1040 11:12:53.376705
1041 11:12:53.376837 Set Vref, RX VrefLevel [Byte0]: 56
1042 11:12:53.380211 [Byte1]: 56
1043 11:12:53.384602
1044 11:12:53.384685 Set Vref, RX VrefLevel [Byte0]: 57
1045 11:12:53.387540 [Byte1]: 57
1046 11:12:53.392249
1047 11:12:53.392331 Set Vref, RX VrefLevel [Byte0]: 58
1048 11:12:53.395190 [Byte1]: 58
1049 11:12:53.399947
1050 11:12:53.400031 Set Vref, RX VrefLevel [Byte0]: 59
1051 11:12:53.403052 [Byte1]: 59
1052 11:12:53.407460
1053 11:12:53.407541 Set Vref, RX VrefLevel [Byte0]: 60
1054 11:12:53.410646 [Byte1]: 60
1055 11:12:53.415196
1056 11:12:53.415277 Set Vref, RX VrefLevel [Byte0]: 61
1057 11:12:53.418251 [Byte1]: 61
1058 11:12:53.422730
1059 11:12:53.422812 Set Vref, RX VrefLevel [Byte0]: 62
1060 11:12:53.428858 [Byte1]: 62
1061 11:12:53.428940
1062 11:12:53.432699 Set Vref, RX VrefLevel [Byte0]: 63
1063 11:12:53.435790 [Byte1]: 63
1064 11:12:53.435872
1065 11:12:53.438914 Set Vref, RX VrefLevel [Byte0]: 64
1066 11:12:53.442660 [Byte1]: 64
1067 11:12:53.442742
1068 11:12:53.445925 Set Vref, RX VrefLevel [Byte0]: 65
1069 11:12:53.448945 [Byte1]: 65
1070 11:12:53.453230
1071 11:12:53.453312 Set Vref, RX VrefLevel [Byte0]: 66
1072 11:12:53.456755 [Byte1]: 66
1073 11:12:53.460866
1074 11:12:53.460948 Set Vref, RX VrefLevel [Byte0]: 67
1075 11:12:53.464236 [Byte1]: 67
1076 11:12:53.468404
1077 11:12:53.468485 Set Vref, RX VrefLevel [Byte0]: 68
1078 11:12:53.471858 [Byte1]: 68
1079 11:12:53.476123
1080 11:12:53.476205 Set Vref, RX VrefLevel [Byte0]: 69
1081 11:12:53.479635 [Byte1]: 69
1082 11:12:53.483837
1083 11:12:53.483919 Set Vref, RX VrefLevel [Byte0]: 70
1084 11:12:53.487090 [Byte1]: 70
1085 11:12:53.491516
1086 11:12:53.491599 Set Vref, RX VrefLevel [Byte0]: 71
1087 11:12:53.495029 [Byte1]: 71
1088 11:12:53.499343
1089 11:12:53.499424 Set Vref, RX VrefLevel [Byte0]: 72
1090 11:12:53.502424 [Byte1]: 72
1091 11:12:53.506563
1092 11:12:53.506646 Set Vref, RX VrefLevel [Byte0]: 73
1093 11:12:53.510368 [Byte1]: 73
1094 11:12:53.514790
1095 11:12:53.514895 Set Vref, RX VrefLevel [Byte0]: 74
1096 11:12:53.517891 [Byte1]: 74
1097 11:12:53.522324
1098 11:12:53.522407 Set Vref, RX VrefLevel [Byte0]: 75
1099 11:12:53.525449 [Byte1]: 75
1100 11:12:53.529887
1101 11:12:53.529968 Set Vref, RX VrefLevel [Byte0]: 76
1102 11:12:53.532915 [Byte1]: 76
1103 11:12:53.537405
1104 11:12:53.537485 Set Vref, RX VrefLevel [Byte0]: 77
1105 11:12:53.540771 [Byte1]: 77
1106 11:12:53.545136
1107 11:12:53.545217 Set Vref, RX VrefLevel [Byte0]: 78
1108 11:12:53.548194 [Byte1]: 78
1109 11:12:53.552594
1110 11:12:53.552676 Set Vref, RX VrefLevel [Byte0]: 79
1111 11:12:53.555812 [Byte1]: 79
1112 11:12:53.560030
1113 11:12:53.560111 Final RX Vref Byte 0 = 58 to rank0
1114 11:12:53.563601 Final RX Vref Byte 1 = 57 to rank0
1115 11:12:53.567160 Final RX Vref Byte 0 = 58 to rank1
1116 11:12:53.570551 Final RX Vref Byte 1 = 57 to rank1==
1117 11:12:53.573550 Dram Type= 6, Freq= 0, CH_0, rank 0
1118 11:12:53.580514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1119 11:12:53.580609 ==
1120 11:12:53.580682 DQS Delay:
1121 11:12:53.580744 DQS0 = 0, DQS1 = 0
1122 11:12:53.583523 DQM Delay:
1123 11:12:53.583605 DQM0 = 81, DQM1 = 67
1124 11:12:53.587027 DQ Delay:
1125 11:12:53.590515 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1126 11:12:53.590619 DQ4 =80, DQ5 =68, DQ6 =88, DQ7 =92
1127 11:12:53.593956 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1128 11:12:53.600225 DQ12 =72, DQ13 =72, DQ14 =76, DQ15 =76
1129 11:12:53.600334
1130 11:12:53.600414
1131 11:12:53.606731 [DQSOSCAuto] RK0, (LSB)MR18= 0x2323, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 401 ps
1132 11:12:53.610387 CH0 RK0: MR19=606, MR18=2323
1133 11:12:53.617151 CH0_RK0: MR19=0x606, MR18=0x2323, DQSOSC=401, MR23=63, INC=91, DEC=61
1134 11:12:53.617226
1135 11:12:53.620263 ----->DramcWriteLeveling(PI) begin...
1136 11:12:53.620362 ==
1137 11:12:53.623430 Dram Type= 6, Freq= 0, CH_0, rank 1
1138 11:12:53.627166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1139 11:12:53.627240 ==
1140 11:12:53.630356 Write leveling (Byte 0): 30 => 30
1141 11:12:53.633489 Write leveling (Byte 1): 30 => 30
1142 11:12:53.636522 DramcWriteLeveling(PI) end<-----
1143 11:12:53.636593
1144 11:12:53.636652 ==
1145 11:12:53.640257 Dram Type= 6, Freq= 0, CH_0, rank 1
1146 11:12:53.643431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1147 11:12:53.643504 ==
1148 11:12:53.646525 [Gating] SW mode calibration
1149 11:12:53.653461 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1150 11:12:53.659908 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1151 11:12:53.663592 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1152 11:12:53.666604 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1153 11:12:53.673104 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1154 11:12:53.676697 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1155 11:12:53.679544 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 11:12:53.686574 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 11:12:53.689481 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 11:12:53.692979 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 11:12:53.699369 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 11:12:53.703146 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 11:12:53.706202 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 11:12:53.712876 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 11:12:53.716513 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 11:12:53.719486 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 11:12:53.766956 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 11:12:53.767074 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 11:12:53.767337 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 11:12:53.767421 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1169 11:12:53.767508 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1170 11:12:53.767750 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 11:12:53.767852 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 11:12:53.767921 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 11:12:53.767980 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 11:12:53.768640 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 11:12:53.810682 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 11:12:53.810845 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 11:12:53.811113 0 9 8 | B1->B0 | 2424 2d2d | 0 0 | (0 0) (0 0)
1178 11:12:53.811183 0 9 12 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
1179 11:12:53.811256 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 11:12:53.811318 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 11:12:53.811377 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 11:12:53.812101 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 11:12:53.812381 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 11:12:53.812453 0 10 4 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
1185 11:12:53.815377 0 10 8 | B1->B0 | 2f2f 2424 | 0 0 | (0 1) (1 0)
1186 11:12:53.818972 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1187 11:12:53.822051 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 11:12:53.825472 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 11:12:53.831873 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 11:12:53.835079 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 11:12:53.838819 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 11:12:53.844965 0 11 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1193 11:12:53.848075 0 11 8 | B1->B0 | 3333 4242 | 0 0 | (0 0) (0 0)
1194 11:12:53.851847 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1195 11:12:53.858108 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 11:12:53.861862 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 11:12:53.865016 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 11:12:53.871510 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 11:12:53.874471 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 11:12:53.878188 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 11:12:53.884689 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1202 11:12:53.888078 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 11:12:53.891723 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 11:12:53.895415 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 11:12:53.902632 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 11:12:53.905526 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 11:12:53.908910 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 11:12:53.915935 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 11:12:53.919687 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 11:12:53.923054 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 11:12:53.926091 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 11:12:53.932761 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 11:12:53.935980 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 11:12:53.939145 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 11:12:53.946248 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 11:12:53.949169 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 11:12:53.952430 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1218 11:12:53.956213 Total UI for P1: 0, mck2ui 16
1219 11:12:53.959498 best dqsien dly found for B0: ( 0, 14, 6)
1220 11:12:53.965974 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1221 11:12:53.966058 Total UI for P1: 0, mck2ui 16
1222 11:12:53.972286 best dqsien dly found for B1: ( 0, 14, 8)
1223 11:12:53.975971 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1224 11:12:53.979158 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1225 11:12:53.979242
1226 11:12:53.982229 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1227 11:12:53.985787 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1228 11:12:53.989216 [Gating] SW calibration Done
1229 11:12:53.989325 ==
1230 11:12:53.992739 Dram Type= 6, Freq= 0, CH_0, rank 1
1231 11:12:53.995595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1232 11:12:53.995680 ==
1233 11:12:53.999127 RX Vref Scan: 0
1234 11:12:53.999210
1235 11:12:53.999276 RX Vref 0 -> 0, step: 1
1236 11:12:53.999336
1237 11:12:54.002165 RX Delay -130 -> 252, step: 16
1238 11:12:54.005537 iDelay=206, Bit 0, Center 77 (-50 ~ 205) 256
1239 11:12:54.012502 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1240 11:12:54.015459 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1241 11:12:54.018696 iDelay=206, Bit 3, Center 69 (-50 ~ 189) 240
1242 11:12:54.022636 iDelay=206, Bit 4, Center 77 (-50 ~ 205) 256
1243 11:12:54.025446 iDelay=206, Bit 5, Center 61 (-66 ~ 189) 256
1244 11:12:54.032340 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1245 11:12:54.035176 iDelay=206, Bit 7, Center 85 (-34 ~ 205) 240
1246 11:12:54.038832 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1247 11:12:54.042060 iDelay=206, Bit 9, Center 53 (-66 ~ 173) 240
1248 11:12:54.045206 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1249 11:12:54.052113 iDelay=206, Bit 11, Center 61 (-66 ~ 189) 256
1250 11:12:54.055265 iDelay=206, Bit 12, Center 77 (-50 ~ 205) 256
1251 11:12:54.058516 iDelay=206, Bit 13, Center 77 (-50 ~ 205) 256
1252 11:12:54.062645 iDelay=206, Bit 14, Center 77 (-50 ~ 205) 256
1253 11:12:54.065588 iDelay=206, Bit 15, Center 77 (-50 ~ 205) 256
1254 11:12:54.068754 ==
1255 11:12:54.071977 Dram Type= 6, Freq= 0, CH_0, rank 1
1256 11:12:54.075673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1257 11:12:54.075757 ==
1258 11:12:54.075823 DQS Delay:
1259 11:12:54.078765 DQS0 = 0, DQS1 = 0
1260 11:12:54.078889 DQM Delay:
1261 11:12:54.081974 DQM0 = 76, DQM1 = 69
1262 11:12:54.082057 DQ Delay:
1263 11:12:54.085147 DQ0 =77, DQ1 =85, DQ2 =69, DQ3 =69
1264 11:12:54.089229 DQ4 =77, DQ5 =61, DQ6 =85, DQ7 =85
1265 11:12:54.092020 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
1266 11:12:54.095728 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1267 11:12:54.095811
1268 11:12:54.095877
1269 11:12:54.095937 ==
1270 11:12:54.098929 Dram Type= 6, Freq= 0, CH_0, rank 1
1271 11:12:54.101892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1272 11:12:54.101976 ==
1273 11:12:54.102043
1274 11:12:54.102102
1275 11:12:54.105297 TX Vref Scan disable
1276 11:12:54.108910 == TX Byte 0 ==
1277 11:12:54.112242 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1278 11:12:54.115124 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1279 11:12:54.118756 == TX Byte 1 ==
1280 11:12:54.121928 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1281 11:12:54.125318 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1282 11:12:54.125402 ==
1283 11:12:54.128738 Dram Type= 6, Freq= 0, CH_0, rank 1
1284 11:12:54.131837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1285 11:12:54.134810 ==
1286 11:12:54.146060 TX Vref=22, minBit 11, minWin=26, winSum=433
1287 11:12:54.149690 TX Vref=24, minBit 13, minWin=26, winSum=434
1288 11:12:54.152913 TX Vref=26, minBit 1, minWin=27, winSum=440
1289 11:12:54.155904 TX Vref=28, minBit 1, minWin=27, winSum=444
1290 11:12:54.159571 TX Vref=30, minBit 1, minWin=27, winSum=439
1291 11:12:54.165843 TX Vref=32, minBit 1, minWin=27, winSum=448
1292 11:12:54.168987 [TxChooseVref] Worse bit 1, Min win 27, Win sum 448, Final Vref 32
1293 11:12:54.169098
1294 11:12:54.172772 Final TX Range 1 Vref 32
1295 11:12:54.172873
1296 11:12:54.172983 ==
1297 11:12:54.175901 Dram Type= 6, Freq= 0, CH_0, rank 1
1298 11:12:54.179123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1299 11:12:54.182398 ==
1300 11:12:54.182478
1301 11:12:54.182541
1302 11:12:54.182600 TX Vref Scan disable
1303 11:12:54.186114 == TX Byte 0 ==
1304 11:12:54.189368 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1305 11:12:54.196237 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1306 11:12:54.196319 == TX Byte 1 ==
1307 11:12:54.199627 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1308 11:12:54.206070 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1309 11:12:54.206152
1310 11:12:54.206216 [DATLAT]
1311 11:12:54.206276 Freq=800, CH0 RK1
1312 11:12:54.206334
1313 11:12:54.209038 DATLAT Default: 0xa
1314 11:12:54.212592 0, 0xFFFF, sum = 0
1315 11:12:54.212674 1, 0xFFFF, sum = 0
1316 11:12:54.216083 2, 0xFFFF, sum = 0
1317 11:12:54.216165 3, 0xFFFF, sum = 0
1318 11:12:54.219509 4, 0xFFFF, sum = 0
1319 11:12:54.219591 5, 0xFFFF, sum = 0
1320 11:12:54.222378 6, 0xFFFF, sum = 0
1321 11:12:54.222460 7, 0xFFFF, sum = 0
1322 11:12:54.225916 8, 0xFFFF, sum = 0
1323 11:12:54.225998 9, 0x0, sum = 1
1324 11:12:54.229397 10, 0x0, sum = 2
1325 11:12:54.229480 11, 0x0, sum = 3
1326 11:12:54.232215 12, 0x0, sum = 4
1327 11:12:54.232297 best_step = 10
1328 11:12:54.232361
1329 11:12:54.232420 ==
1330 11:12:54.235886 Dram Type= 6, Freq= 0, CH_0, rank 1
1331 11:12:54.238963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1332 11:12:54.239046 ==
1333 11:12:54.242592 RX Vref Scan: 0
1334 11:12:54.242672
1335 11:12:54.245691 RX Vref 0 -> 0, step: 1
1336 11:12:54.245771
1337 11:12:54.245836 RX Delay -111 -> 252, step: 8
1338 11:12:54.252916 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
1339 11:12:54.256418 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1340 11:12:54.259612 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1341 11:12:54.262699 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1342 11:12:54.269635 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1343 11:12:54.272806 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1344 11:12:54.275953 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1345 11:12:54.279075 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1346 11:12:54.282875 iDelay=209, Bit 8, Center 60 (-55 ~ 176) 232
1347 11:12:54.289200 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1348 11:12:54.292405 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1349 11:12:54.295651 iDelay=209, Bit 11, Center 60 (-55 ~ 176) 232
1350 11:12:54.299403 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
1351 11:12:54.302416 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1352 11:12:54.308934 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1353 11:12:54.312475 iDelay=209, Bit 15, Center 76 (-39 ~ 192) 232
1354 11:12:54.312556 ==
1355 11:12:54.315789 Dram Type= 6, Freq= 0, CH_0, rank 1
1356 11:12:54.319274 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1357 11:12:54.319380 ==
1358 11:12:54.322247 DQS Delay:
1359 11:12:54.322327 DQS0 = 0, DQS1 = 0
1360 11:12:54.322390 DQM Delay:
1361 11:12:54.325758 DQM0 = 79, DQM1 = 70
1362 11:12:54.325838 DQ Delay:
1363 11:12:54.328695 DQ0 =80, DQ1 =84, DQ2 =76, DQ3 =72
1364 11:12:54.332206 DQ4 =80, DQ5 =64, DQ6 =88, DQ7 =88
1365 11:12:54.335746 DQ8 =60, DQ9 =56, DQ10 =72, DQ11 =60
1366 11:12:54.339086 DQ12 =80, DQ13 =76, DQ14 =80, DQ15 =76
1367 11:12:54.339169
1368 11:12:54.339234
1369 11:12:54.349123 [DQSOSCAuto] RK1, (LSB)MR18= 0x4723, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
1370 11:12:54.352331 CH0 RK1: MR19=606, MR18=4723
1371 11:12:54.355257 CH0_RK1: MR19=0x606, MR18=0x4723, DQSOSC=392, MR23=63, INC=96, DEC=64
1372 11:12:54.358980 [RxdqsGatingPostProcess] freq 800
1373 11:12:54.365469 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1374 11:12:54.368568 Pre-setting of DQS Precalculation
1375 11:12:54.372571 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1376 11:12:54.372654 ==
1377 11:12:54.375526 Dram Type= 6, Freq= 0, CH_1, rank 0
1378 11:12:54.381786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1379 11:12:54.381912 ==
1380 11:12:54.385507 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1381 11:12:54.391845 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1382 11:12:54.401428 [CA 0] Center 36 (6~66) winsize 61
1383 11:12:54.404547 [CA 1] Center 36 (6~67) winsize 62
1384 11:12:54.408166 [CA 2] Center 34 (5~64) winsize 60
1385 11:12:54.411132 [CA 3] Center 34 (4~64) winsize 61
1386 11:12:54.414717 [CA 4] Center 35 (5~65) winsize 61
1387 11:12:54.417714 [CA 5] Center 34 (4~64) winsize 61
1388 11:12:54.417797
1389 11:12:54.421335 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1390 11:12:54.421419
1391 11:12:54.424755 [CATrainingPosCal] consider 1 rank data
1392 11:12:54.427833 u2DelayCellTimex100 = 270/100 ps
1393 11:12:54.430789 CA0 delay=36 (6~66),Diff = 2 PI (14 cell)
1394 11:12:54.438061 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1395 11:12:54.440749 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1396 11:12:54.444285 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1397 11:12:54.447755 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1398 11:12:54.450750 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1399 11:12:54.450915
1400 11:12:54.453924 CA PerBit enable=1, Macro0, CA PI delay=34
1401 11:12:54.454027
1402 11:12:54.457569 [CBTSetCACLKResult] CA Dly = 34
1403 11:12:54.457676 CS Dly: 4 (0~35)
1404 11:12:54.460634 ==
1405 11:12:54.464182 Dram Type= 6, Freq= 0, CH_1, rank 1
1406 11:12:54.467447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1407 11:12:54.467580 ==
1408 11:12:54.470736 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1409 11:12:54.477548 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1410 11:12:54.487556 [CA 0] Center 37 (7~67) winsize 61
1411 11:12:54.490693 [CA 1] Center 36 (6~67) winsize 62
1412 11:12:54.493856 [CA 2] Center 35 (5~65) winsize 61
1413 11:12:54.497044 [CA 3] Center 33 (3~64) winsize 62
1414 11:12:54.500910 [CA 4] Center 34 (4~65) winsize 62
1415 11:12:54.504096 [CA 5] Center 33 (3~64) winsize 62
1416 11:12:54.504180
1417 11:12:54.507258 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1418 11:12:54.507342
1419 11:12:54.510441 [CATrainingPosCal] consider 2 rank data
1420 11:12:54.514112 u2DelayCellTimex100 = 270/100 ps
1421 11:12:54.517180 CA0 delay=36 (7~66),Diff = 2 PI (14 cell)
1422 11:12:54.523938 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1423 11:12:54.526871 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
1424 11:12:54.530449 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
1425 11:12:54.533942 CA4 delay=35 (5~65),Diff = 1 PI (7 cell)
1426 11:12:54.536910 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1427 11:12:54.536993
1428 11:12:54.540263 CA PerBit enable=1, Macro0, CA PI delay=34
1429 11:12:54.540347
1430 11:12:54.543689 [CBTSetCACLKResult] CA Dly = 34
1431 11:12:54.547048 CS Dly: 5 (0~38)
1432 11:12:54.547132
1433 11:12:54.547198 ----->DramcWriteLeveling(PI) begin...
1434 11:12:54.551193 ==
1435 11:12:54.551276 Dram Type= 6, Freq= 0, CH_1, rank 0
1436 11:12:54.558317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1437 11:12:54.558430 ==
1438 11:12:54.558535 Write leveling (Byte 0): 30 => 30
1439 11:12:54.562102 Write leveling (Byte 1): 30 => 30
1440 11:12:54.565147 DramcWriteLeveling(PI) end<-----
1441 11:12:54.565268
1442 11:12:54.565362 ==
1443 11:12:54.569434 Dram Type= 6, Freq= 0, CH_1, rank 0
1444 11:12:54.572515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1445 11:12:54.572621 ==
1446 11:12:54.576160 [Gating] SW mode calibration
1447 11:12:54.583428 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1448 11:12:54.589799 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1449 11:12:54.593652 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1450 11:12:54.596950 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1451 11:12:54.603183 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1452 11:12:54.607032 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 11:12:54.610152 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 11:12:54.616583 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 11:12:54.619809 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 11:12:54.623413 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 11:12:54.630123 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 11:12:54.633211 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 11:12:54.636145 0 7 8 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1460 11:12:54.642643 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 11:12:54.646130 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 11:12:54.649633 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 11:12:54.655954 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 11:12:54.659417 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 11:12:54.663096 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 11:12:54.669404 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1467 11:12:54.673035 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1468 11:12:54.675984 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 11:12:54.683055 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 11:12:54.685869 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 11:12:54.689328 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 11:12:54.692922 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 11:12:54.699370 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 11:12:54.702459 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 11:12:54.705656 0 9 8 | B1->B0 | 2b2b 2929 | 0 0 | (0 0) (0 0)
1476 11:12:54.712580 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 11:12:54.715778 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 11:12:54.718997 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 11:12:54.725829 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 11:12:54.728957 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 11:12:54.732707 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 11:12:54.739122 0 10 4 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
1483 11:12:54.742471 0 10 8 | B1->B0 | 2c2c 2b2b | 0 0 | (0 1) (0 1)
1484 11:12:54.745685 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1485 11:12:54.752463 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 11:12:54.756071 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 11:12:54.759001 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 11:12:54.765379 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 11:12:54.768864 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 11:12:54.771793 0 11 4 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1491 11:12:54.778423 0 11 8 | B1->B0 | 3838 3737 | 1 0 | (0 0) (0 0)
1492 11:12:54.782004 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 11:12:54.785147 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 11:12:54.791921 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 11:12:54.795020 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 11:12:54.798576 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 11:12:54.804932 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 11:12:54.808004 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 11:12:54.811787 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1500 11:12:54.818330 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 11:12:54.821509 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 11:12:54.824679 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 11:12:54.831441 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 11:12:54.834524 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 11:12:54.838169 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 11:12:54.844453 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 11:12:54.847977 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 11:12:54.851347 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 11:12:54.857765 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 11:12:54.861373 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 11:12:54.864248 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 11:12:54.870841 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 11:12:54.874401 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 11:12:54.877513 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1515 11:12:54.884200 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1516 11:12:54.887742 Total UI for P1: 0, mck2ui 16
1517 11:12:54.890876 best dqsien dly found for B0: ( 0, 14, 6)
1518 11:12:54.893863 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1519 11:12:54.897565 Total UI for P1: 0, mck2ui 16
1520 11:12:54.900657 best dqsien dly found for B1: ( 0, 14, 6)
1521 11:12:54.903637 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1522 11:12:54.906690 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1523 11:12:54.906811
1524 11:12:54.910485 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1525 11:12:54.913658 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1526 11:12:54.916860 [Gating] SW calibration Done
1527 11:12:54.916948 ==
1528 11:12:54.920581 Dram Type= 6, Freq= 0, CH_1, rank 0
1529 11:12:54.926951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1530 11:12:54.927040 ==
1531 11:12:54.927107 RX Vref Scan: 0
1532 11:12:54.927168
1533 11:12:54.930148 RX Vref 0 -> 0, step: 1
1534 11:12:54.930231
1535 11:12:54.933236 RX Delay -130 -> 252, step: 16
1536 11:12:54.936986 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1537 11:12:54.940086 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1538 11:12:54.943598 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1539 11:12:54.950229 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1540 11:12:54.953325 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1541 11:12:54.956599 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1542 11:12:54.960087 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1543 11:12:54.963453 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1544 11:12:54.966928 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1545 11:12:54.973252 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1546 11:12:54.976620 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1547 11:12:54.980384 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1548 11:12:54.983068 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1549 11:12:54.990051 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1550 11:12:54.993066 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1551 11:12:54.996577 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1552 11:12:54.996660 ==
1553 11:12:54.999654 Dram Type= 6, Freq= 0, CH_1, rank 0
1554 11:12:55.003211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1555 11:12:55.003294 ==
1556 11:12:55.006352 DQS Delay:
1557 11:12:55.006435 DQS0 = 0, DQS1 = 0
1558 11:12:55.009431 DQM Delay:
1559 11:12:55.009515 DQM0 = 82, DQM1 = 73
1560 11:12:55.013084 DQ Delay:
1561 11:12:55.013168 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1562 11:12:55.016246 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1563 11:12:55.019404 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1564 11:12:55.022571 DQ12 =77, DQ13 =77, DQ14 =85, DQ15 =85
1565 11:12:55.022654
1566 11:12:55.026365
1567 11:12:55.026447 ==
1568 11:12:55.029498 Dram Type= 6, Freq= 0, CH_1, rank 0
1569 11:12:55.032653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1570 11:12:55.032736 ==
1571 11:12:55.032802
1572 11:12:55.032892
1573 11:12:55.035880 TX Vref Scan disable
1574 11:12:55.035963 == TX Byte 0 ==
1575 11:12:55.042718 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1576 11:12:55.045733 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1577 11:12:55.045851 == TX Byte 1 ==
1578 11:12:55.052735 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1579 11:12:55.055913 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1580 11:12:55.055995 ==
1581 11:12:55.058849 Dram Type= 6, Freq= 0, CH_1, rank 0
1582 11:12:55.062496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1583 11:12:55.062579 ==
1584 11:12:55.076205 TX Vref=22, minBit 0, minWin=27, winSum=440
1585 11:12:55.079578 TX Vref=24, minBit 1, minWin=27, winSum=444
1586 11:12:55.082507 TX Vref=26, minBit 1, minWin=27, winSum=443
1587 11:12:55.086023 TX Vref=28, minBit 1, minWin=27, winSum=448
1588 11:12:55.089529 TX Vref=30, minBit 9, minWin=27, winSum=449
1589 11:12:55.095920 TX Vref=32, minBit 6, minWin=27, winSum=447
1590 11:12:55.099503 [TxChooseVref] Worse bit 9, Min win 27, Win sum 449, Final Vref 30
1591 11:12:55.099576
1592 11:12:55.102434 Final TX Range 1 Vref 30
1593 11:12:55.102532
1594 11:12:55.102596 ==
1595 11:12:55.105995 Dram Type= 6, Freq= 0, CH_1, rank 0
1596 11:12:55.108807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1597 11:12:55.112575 ==
1598 11:12:55.112665
1599 11:12:55.112730
1600 11:12:55.112790 TX Vref Scan disable
1601 11:12:55.115666 == TX Byte 0 ==
1602 11:12:55.119477 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1603 11:12:55.126495 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1604 11:12:55.126599 == TX Byte 1 ==
1605 11:12:55.129676 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1606 11:12:55.133467 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1607 11:12:55.133538
1608 11:12:55.136696 [DATLAT]
1609 11:12:55.136772 Freq=800, CH1 RK0
1610 11:12:55.136832
1611 11:12:55.139754 DATLAT Default: 0xa
1612 11:12:55.139828 0, 0xFFFF, sum = 0
1613 11:12:55.142912 1, 0xFFFF, sum = 0
1614 11:12:55.143013 2, 0xFFFF, sum = 0
1615 11:12:55.146048 3, 0xFFFF, sum = 0
1616 11:12:55.146130 4, 0xFFFF, sum = 0
1617 11:12:55.149700 5, 0xFFFF, sum = 0
1618 11:12:55.149778 6, 0xFFFF, sum = 0
1619 11:12:55.152834 7, 0xFFFF, sum = 0
1620 11:12:55.152902 8, 0xFFFF, sum = 0
1621 11:12:55.156033 9, 0x0, sum = 1
1622 11:12:55.156116 10, 0x0, sum = 2
1623 11:12:55.159826 11, 0x0, sum = 3
1624 11:12:55.159909 12, 0x0, sum = 4
1625 11:12:55.162773 best_step = 10
1626 11:12:55.162885
1627 11:12:55.162977 ==
1628 11:12:55.166367 Dram Type= 6, Freq= 0, CH_1, rank 0
1629 11:12:55.169570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1630 11:12:55.169652 ==
1631 11:12:55.172723 RX Vref Scan: 1
1632 11:12:55.172804
1633 11:12:55.172867 Set Vref Range= 32 -> 127
1634 11:12:55.172927
1635 11:12:55.176233 RX Vref 32 -> 127, step: 1
1636 11:12:55.176350
1637 11:12:55.179260 RX Delay -111 -> 252, step: 8
1638 11:12:55.179342
1639 11:12:55.183011 Set Vref, RX VrefLevel [Byte0]: 32
1640 11:12:55.185997 [Byte1]: 32
1641 11:12:55.186070
1642 11:12:55.189364 Set Vref, RX VrefLevel [Byte0]: 33
1643 11:12:55.192837 [Byte1]: 33
1644 11:12:55.196358
1645 11:12:55.196428 Set Vref, RX VrefLevel [Byte0]: 34
1646 11:12:55.199772 [Byte1]: 34
1647 11:12:55.204246
1648 11:12:55.204328 Set Vref, RX VrefLevel [Byte0]: 35
1649 11:12:55.207261 [Byte1]: 35
1650 11:12:55.212000
1651 11:12:55.212078 Set Vref, RX VrefLevel [Byte0]: 36
1652 11:12:55.214852 [Byte1]: 36
1653 11:12:55.219232
1654 11:12:55.219313 Set Vref, RX VrefLevel [Byte0]: 37
1655 11:12:55.222753 [Byte1]: 37
1656 11:12:55.227298
1657 11:12:55.227383 Set Vref, RX VrefLevel [Byte0]: 38
1658 11:12:55.230292 [Byte1]: 38
1659 11:12:55.234565
1660 11:12:55.237695 Set Vref, RX VrefLevel [Byte0]: 39
1661 11:12:55.241078 [Byte1]: 39
1662 11:12:55.241197
1663 11:12:55.244609 Set Vref, RX VrefLevel [Byte0]: 40
1664 11:12:55.247727 [Byte1]: 40
1665 11:12:55.247810
1666 11:12:55.250952 Set Vref, RX VrefLevel [Byte0]: 41
1667 11:12:55.254486 [Byte1]: 41
1668 11:12:55.257710
1669 11:12:55.257788 Set Vref, RX VrefLevel [Byte0]: 42
1670 11:12:55.260949 [Byte1]: 42
1671 11:12:55.265375
1672 11:12:55.265487 Set Vref, RX VrefLevel [Byte0]: 43
1673 11:12:55.268409 [Byte1]: 43
1674 11:12:55.272631
1675 11:12:55.272722 Set Vref, RX VrefLevel [Byte0]: 44
1676 11:12:55.276508 [Byte1]: 44
1677 11:12:55.281012
1678 11:12:55.281100 Set Vref, RX VrefLevel [Byte0]: 45
1679 11:12:55.283880 [Byte1]: 45
1680 11:12:55.288134
1681 11:12:55.288225 Set Vref, RX VrefLevel [Byte0]: 46
1682 11:12:55.291592 [Byte1]: 46
1683 11:12:55.295838
1684 11:12:55.295931 Set Vref, RX VrefLevel [Byte0]: 47
1685 11:12:55.299461 [Byte1]: 47
1686 11:12:55.303597
1687 11:12:55.303691 Set Vref, RX VrefLevel [Byte0]: 48
1688 11:12:55.306665 [Byte1]: 48
1689 11:12:55.311464
1690 11:12:55.311552 Set Vref, RX VrefLevel [Byte0]: 49
1691 11:12:55.314569 [Byte1]: 49
1692 11:12:55.319010
1693 11:12:55.319093 Set Vref, RX VrefLevel [Byte0]: 50
1694 11:12:55.322265 [Byte1]: 50
1695 11:12:55.326509
1696 11:12:55.326591 Set Vref, RX VrefLevel [Byte0]: 51
1697 11:12:55.329410 [Byte1]: 51
1698 11:12:55.333596
1699 11:12:55.337435 Set Vref, RX VrefLevel [Byte0]: 52
1700 11:12:55.340580 [Byte1]: 52
1701 11:12:55.340662
1702 11:12:55.343618 Set Vref, RX VrefLevel [Byte0]: 53
1703 11:12:55.347421 [Byte1]: 53
1704 11:12:55.347503
1705 11:12:55.350576 Set Vref, RX VrefLevel [Byte0]: 54
1706 11:12:55.353745 [Byte1]: 54
1707 11:12:55.356901
1708 11:12:55.356982 Set Vref, RX VrefLevel [Byte0]: 55
1709 11:12:55.360426 [Byte1]: 55
1710 11:12:55.364836
1711 11:12:55.364917 Set Vref, RX VrefLevel [Byte0]: 56
1712 11:12:55.368040 [Byte1]: 56
1713 11:12:55.372296
1714 11:12:55.372377 Set Vref, RX VrefLevel [Byte0]: 57
1715 11:12:55.375300 [Byte1]: 57
1716 11:12:55.379698
1717 11:12:55.379780 Set Vref, RX VrefLevel [Byte0]: 58
1718 11:12:55.383349 [Byte1]: 58
1719 11:12:55.387721
1720 11:12:55.387810 Set Vref, RX VrefLevel [Byte0]: 59
1721 11:12:55.390808 [Byte1]: 59
1722 11:12:55.395009
1723 11:12:55.395153 Set Vref, RX VrefLevel [Byte0]: 60
1724 11:12:55.398536 [Byte1]: 60
1725 11:12:55.402662
1726 11:12:55.402746 Set Vref, RX VrefLevel [Byte0]: 61
1727 11:12:55.406218 [Byte1]: 61
1728 11:12:55.410279
1729 11:12:55.410362 Set Vref, RX VrefLevel [Byte0]: 62
1730 11:12:55.413812 [Byte1]: 62
1731 11:12:55.418018
1732 11:12:55.418100 Set Vref, RX VrefLevel [Byte0]: 63
1733 11:12:55.421132 [Byte1]: 63
1734 11:12:55.425973
1735 11:12:55.426073 Set Vref, RX VrefLevel [Byte0]: 64
1736 11:12:55.428942 [Byte1]: 64
1737 11:12:55.433586
1738 11:12:55.433668 Set Vref, RX VrefLevel [Byte0]: 65
1739 11:12:55.436762 [Byte1]: 65
1740 11:12:55.440945
1741 11:12:55.441027 Set Vref, RX VrefLevel [Byte0]: 66
1742 11:12:55.444128 [Byte1]: 66
1743 11:12:55.448559
1744 11:12:55.448640 Set Vref, RX VrefLevel [Byte0]: 67
1745 11:12:55.452345 [Byte1]: 67
1746 11:12:55.456085
1747 11:12:55.456166 Set Vref, RX VrefLevel [Byte0]: 68
1748 11:12:55.459881 [Byte1]: 68
1749 11:12:55.464200
1750 11:12:55.464285 Set Vref, RX VrefLevel [Byte0]: 69
1751 11:12:55.467410 [Byte1]: 69
1752 11:12:55.471807
1753 11:12:55.471888 Set Vref, RX VrefLevel [Byte0]: 70
1754 11:12:55.474956 [Byte1]: 70
1755 11:12:55.479133
1756 11:12:55.479216 Set Vref, RX VrefLevel [Byte0]: 71
1757 11:12:55.482857 [Byte1]: 71
1758 11:12:55.487181
1759 11:12:55.487264 Set Vref, RX VrefLevel [Byte0]: 72
1760 11:12:55.490270 [Byte1]: 72
1761 11:12:55.494718
1762 11:12:55.494803 Set Vref, RX VrefLevel [Byte0]: 73
1763 11:12:55.497790 [Byte1]: 73
1764 11:12:55.501929
1765 11:12:55.502010 Final RX Vref Byte 0 = 58 to rank0
1766 11:12:55.505846 Final RX Vref Byte 1 = 57 to rank0
1767 11:12:55.508859 Final RX Vref Byte 0 = 58 to rank1
1768 11:12:55.512462 Final RX Vref Byte 1 = 57 to rank1==
1769 11:12:55.515392 Dram Type= 6, Freq= 0, CH_1, rank 0
1770 11:12:55.522360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1771 11:12:55.522443 ==
1772 11:12:55.522509 DQS Delay:
1773 11:12:55.522569 DQS0 = 0, DQS1 = 0
1774 11:12:55.525393 DQM Delay:
1775 11:12:55.525474 DQM0 = 81, DQM1 = 71
1776 11:12:55.528815 DQ Delay:
1777 11:12:55.532253 DQ0 =88, DQ1 =76, DQ2 =68, DQ3 =76
1778 11:12:55.535304 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1779 11:12:55.538771 DQ8 =56, DQ9 =64, DQ10 =72, DQ11 =68
1780 11:12:55.541974 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1781 11:12:55.542056
1782 11:12:55.542121
1783 11:12:55.548578 [DQSOSCAuto] RK0, (LSB)MR18= 0x131d, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 405 ps
1784 11:12:55.551665 CH1 RK0: MR19=606, MR18=131D
1785 11:12:55.558491 CH1_RK0: MR19=0x606, MR18=0x131D, DQSOSC=402, MR23=63, INC=91, DEC=60
1786 11:12:55.558574
1787 11:12:55.561690 ----->DramcWriteLeveling(PI) begin...
1788 11:12:55.561773 ==
1789 11:12:55.564712 Dram Type= 6, Freq= 0, CH_1, rank 1
1790 11:12:55.568326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1791 11:12:55.568416 ==
1792 11:12:55.571524 Write leveling (Byte 0): 29 => 29
1793 11:12:55.575233 Write leveling (Byte 1): 30 => 30
1794 11:12:55.578449 DramcWriteLeveling(PI) end<-----
1795 11:12:55.578531
1796 11:12:55.578614 ==
1797 11:12:55.581359 Dram Type= 6, Freq= 0, CH_1, rank 1
1798 11:12:55.585020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1799 11:12:55.585114 ==
1800 11:12:55.587982 [Gating] SW mode calibration
1801 11:12:55.594574 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1802 11:12:55.601342 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1803 11:12:55.604516 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1804 11:12:55.611072 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1805 11:12:55.614422 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 11:12:55.618163 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 11:12:55.624391 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 11:12:55.627880 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 11:12:55.630917 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 11:12:55.637438 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 11:12:55.641057 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 11:12:55.644025 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 11:12:55.650984 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 11:12:55.654383 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 11:12:55.657505 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 11:12:55.664013 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 11:12:55.667124 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 11:12:55.670776 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 11:12:55.677668 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 11:12:55.680859 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1821 11:12:55.683799 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 11:12:55.690499 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 11:12:55.693635 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 11:12:55.697592 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 11:12:55.703497 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 11:12:55.707290 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 11:12:55.710498 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 11:12:55.717289 0 9 4 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
1829 11:12:55.720121 0 9 8 | B1->B0 | 2e2e 3434 | 0 1 | (0 0) (1 1)
1830 11:12:55.723687 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1831 11:12:55.730352 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1832 11:12:55.733429 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1833 11:12:55.737097 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1834 11:12:55.743343 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1835 11:12:55.746988 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1836 11:12:55.749934 0 10 4 | B1->B0 | 3434 2f2f | 0 0 | (0 0) (0 0)
1837 11:12:55.756358 0 10 8 | B1->B0 | 2b2b 2323 | 0 0 | (1 1) (0 0)
1838 11:12:55.760197 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 11:12:55.763190 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 11:12:55.769508 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 11:12:55.773229 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 11:12:55.776162 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 11:12:55.783135 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 11:12:55.786286 0 11 4 | B1->B0 | 2c2c 3838 | 1 0 | (0 0) (0 0)
1845 11:12:55.789329 0 11 8 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
1846 11:12:55.796219 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1847 11:12:55.799372 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1848 11:12:55.803029 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1849 11:12:55.809377 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1850 11:12:55.812578 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1851 11:12:55.815822 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1852 11:12:55.822465 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1853 11:12:55.826075 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 11:12:55.829059 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 11:12:55.832733 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 11:12:55.839423 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 11:12:55.842207 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 11:12:55.845516 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 11:12:55.852135 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 11:12:55.855499 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 11:12:55.858745 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 11:12:55.865497 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 11:12:55.868637 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 11:12:55.872403 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 11:12:55.878545 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 11:12:55.882235 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 11:12:55.885411 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 11:12:55.892171 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1869 11:12:55.895200 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1870 11:12:55.898420 Total UI for P1: 0, mck2ui 16
1871 11:12:55.902208 best dqsien dly found for B0: ( 0, 14, 4)
1872 11:12:55.905234 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1873 11:12:55.908370 Total UI for P1: 0, mck2ui 16
1874 11:12:55.912077 best dqsien dly found for B1: ( 0, 14, 8)
1875 11:12:55.915238 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1876 11:12:55.918433 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1877 11:12:55.918516
1878 11:12:55.925477 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1879 11:12:55.928350 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1880 11:12:55.931988 [Gating] SW calibration Done
1881 11:12:55.932075 ==
1882 11:12:55.935023 Dram Type= 6, Freq= 0, CH_1, rank 1
1883 11:12:55.938557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1884 11:12:55.938649 ==
1885 11:12:55.938716 RX Vref Scan: 0
1886 11:12:55.938779
1887 11:12:55.941473 RX Vref 0 -> 0, step: 1
1888 11:12:55.941557
1889 11:12:55.944996 RX Delay -130 -> 252, step: 16
1890 11:12:55.948579 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1891 11:12:55.951566 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1892 11:12:55.958043 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1893 11:12:55.961653 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1894 11:12:55.964712 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1895 11:12:55.968246 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1896 11:12:55.971203 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1897 11:12:55.978145 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1898 11:12:55.981201 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1899 11:12:55.985030 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1900 11:12:55.988182 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1901 11:12:55.991406 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1902 11:12:55.998127 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1903 11:12:56.001179 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1904 11:12:56.004439 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1905 11:12:56.008192 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1906 11:12:56.008298 ==
1907 11:12:56.011019 Dram Type= 6, Freq= 0, CH_1, rank 1
1908 11:12:56.017407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1909 11:12:56.017493 ==
1910 11:12:56.017560 DQS Delay:
1911 11:12:56.021174 DQS0 = 0, DQS1 = 0
1912 11:12:56.021257 DQM Delay:
1913 11:12:56.021323 DQM0 = 78, DQM1 = 77
1914 11:12:56.024458 DQ Delay:
1915 11:12:56.027577 DQ0 =85, DQ1 =69, DQ2 =61, DQ3 =77
1916 11:12:56.031170 DQ4 =77, DQ5 =85, DQ6 =93, DQ7 =77
1917 11:12:56.034327 DQ8 =61, DQ9 =61, DQ10 =85, DQ11 =69
1918 11:12:56.037584 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1919 11:12:56.037667
1920 11:12:56.037733
1921 11:12:56.037792 ==
1922 11:12:56.040965 Dram Type= 6, Freq= 0, CH_1, rank 1
1923 11:12:56.044454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1924 11:12:56.044539 ==
1925 11:12:56.044605
1926 11:12:56.044687
1927 11:12:56.047515 TX Vref Scan disable
1928 11:12:56.051007 == TX Byte 0 ==
1929 11:12:56.053980 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1930 11:12:56.057563 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1931 11:12:56.061335 == TX Byte 1 ==
1932 11:12:56.064053 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1933 11:12:56.067635 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1934 11:12:56.067722 ==
1935 11:12:56.070667 Dram Type= 6, Freq= 0, CH_1, rank 1
1936 11:12:56.074149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1937 11:12:56.074233 ==
1938 11:12:56.088352 TX Vref=22, minBit 1, minWin=27, winSum=446
1939 11:12:56.091551 TX Vref=24, minBit 0, minWin=28, winSum=453
1940 11:12:56.094749 TX Vref=26, minBit 1, minWin=27, winSum=455
1941 11:12:56.098619 TX Vref=28, minBit 1, minWin=27, winSum=456
1942 11:12:56.101701 TX Vref=30, minBit 1, minWin=27, winSum=458
1943 11:12:56.105323 TX Vref=32, minBit 1, minWin=27, winSum=455
1944 11:12:56.111833 [TxChooseVref] Worse bit 0, Min win 28, Win sum 453, Final Vref 24
1945 11:12:56.111919
1946 11:12:56.115159 Final TX Range 1 Vref 24
1947 11:12:56.115279
1948 11:12:56.115345 ==
1949 11:12:56.118425 Dram Type= 6, Freq= 0, CH_1, rank 1
1950 11:12:56.121494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1951 11:12:56.121579 ==
1952 11:12:56.124614
1953 11:12:56.124696
1954 11:12:56.124760 TX Vref Scan disable
1955 11:12:56.128403 == TX Byte 0 ==
1956 11:12:56.131542 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1957 11:12:56.138239 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1958 11:12:56.138323 == TX Byte 1 ==
1959 11:12:56.141374 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1960 11:12:56.148052 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1961 11:12:56.148138
1962 11:12:56.148203 [DATLAT]
1963 11:12:56.148263 Freq=800, CH1 RK1
1964 11:12:56.148346
1965 11:12:56.151472 DATLAT Default: 0xa
1966 11:12:56.151579 0, 0xFFFF, sum = 0
1967 11:12:56.154978 1, 0xFFFF, sum = 0
1968 11:12:56.155065 2, 0xFFFF, sum = 0
1969 11:12:56.157958 3, 0xFFFF, sum = 0
1970 11:12:56.158042 4, 0xFFFF, sum = 0
1971 11:12:56.161465 5, 0xFFFF, sum = 0
1972 11:12:56.161549 6, 0xFFFF, sum = 0
1973 11:12:56.165180 7, 0xFFFF, sum = 0
1974 11:12:56.168587 8, 0xFFFF, sum = 0
1975 11:12:56.168671 9, 0x0, sum = 1
1976 11:12:56.168738 10, 0x0, sum = 2
1977 11:12:56.171596 11, 0x0, sum = 3
1978 11:12:56.171680 12, 0x0, sum = 4
1979 11:12:56.175212 best_step = 10
1980 11:12:56.175294
1981 11:12:56.175359 ==
1982 11:12:56.178071 Dram Type= 6, Freq= 0, CH_1, rank 1
1983 11:12:56.181675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1984 11:12:56.181760 ==
1985 11:12:56.184833 RX Vref Scan: 0
1986 11:12:56.184917
1987 11:12:56.184981 RX Vref 0 -> 0, step: 1
1988 11:12:56.185042
1989 11:12:56.188009 RX Delay -111 -> 252, step: 8
1990 11:12:56.194766 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
1991 11:12:56.198538 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
1992 11:12:56.201625 iDelay=209, Bit 2, Center 64 (-55 ~ 184) 240
1993 11:12:56.204687 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1994 11:12:56.208283 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
1995 11:12:56.215150 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
1996 11:12:56.218275 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1997 11:12:56.221362 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
1998 11:12:56.224562 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
1999 11:12:56.228422 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
2000 11:12:56.234764 iDelay=209, Bit 10, Center 76 (-47 ~ 200) 248
2001 11:12:56.237855 iDelay=209, Bit 11, Center 68 (-55 ~ 192) 248
2002 11:12:56.241529 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2003 11:12:56.244625 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2004 11:12:56.251150 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2005 11:12:56.254706 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2006 11:12:56.254814 ==
2007 11:12:56.258055 Dram Type= 6, Freq= 0, CH_1, rank 1
2008 11:12:56.261435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2009 11:12:56.261578 ==
2010 11:12:56.264756 DQS Delay:
2011 11:12:56.264878 DQS0 = 0, DQS1 = 0
2012 11:12:56.264979 DQM Delay:
2013 11:12:56.267753 DQM0 = 77, DQM1 = 73
2014 11:12:56.267880 DQ Delay:
2015 11:12:56.271174 DQ0 =80, DQ1 =72, DQ2 =64, DQ3 =72
2016 11:12:56.274712 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2017 11:12:56.278077 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
2018 11:12:56.281068 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
2019 11:12:56.281176
2020 11:12:56.281289
2021 11:12:56.290984 [DQSOSCAuto] RK1, (LSB)MR18= 0x253d, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
2022 11:12:56.291120 CH1 RK1: MR19=606, MR18=253D
2023 11:12:56.297720 CH1_RK1: MR19=0x606, MR18=0x253D, DQSOSC=394, MR23=63, INC=95, DEC=63
2024 11:12:56.300881 [RxdqsGatingPostProcess] freq 800
2025 11:12:56.307871 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2026 11:12:56.310825 Pre-setting of DQS Precalculation
2027 11:12:56.314447 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2028 11:12:56.320734 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2029 11:12:56.331341 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2030 11:12:56.331424
2031 11:12:56.331489
2032 11:12:56.334264 [Calibration Summary] 1600 Mbps
2033 11:12:56.334346 CH 0, Rank 0
2034 11:12:56.337481 SW Impedance : PASS
2035 11:12:56.337563 DUTY Scan : NO K
2036 11:12:56.341100 ZQ Calibration : PASS
2037 11:12:56.344259 Jitter Meter : NO K
2038 11:12:56.344341 CBT Training : PASS
2039 11:12:56.347401 Write leveling : PASS
2040 11:12:56.350635 RX DQS gating : PASS
2041 11:12:56.350717 RX DQ/DQS(RDDQC) : PASS
2042 11:12:56.354362 TX DQ/DQS : PASS
2043 11:12:56.354444 RX DATLAT : PASS
2044 11:12:56.357545 RX DQ/DQS(Engine): PASS
2045 11:12:56.360447 TX OE : NO K
2046 11:12:56.360530 All Pass.
2047 11:12:56.360594
2048 11:12:56.360653 CH 0, Rank 1
2049 11:12:56.364029 SW Impedance : PASS
2050 11:12:56.367035 DUTY Scan : NO K
2051 11:12:56.367117 ZQ Calibration : PASS
2052 11:12:56.370567 Jitter Meter : NO K
2053 11:12:56.373598 CBT Training : PASS
2054 11:12:56.373681 Write leveling : PASS
2055 11:12:56.377284 RX DQS gating : PASS
2056 11:12:56.380522 RX DQ/DQS(RDDQC) : PASS
2057 11:12:56.380606 TX DQ/DQS : PASS
2058 11:12:56.383458 RX DATLAT : PASS
2059 11:12:56.387339 RX DQ/DQS(Engine): PASS
2060 11:12:56.387431 TX OE : NO K
2061 11:12:56.390115 All Pass.
2062 11:12:56.390197
2063 11:12:56.390261 CH 1, Rank 0
2064 11:12:56.393703 SW Impedance : PASS
2065 11:12:56.393794 DUTY Scan : NO K
2066 11:12:56.396775 ZQ Calibration : PASS
2067 11:12:56.400274 Jitter Meter : NO K
2068 11:12:56.400357 CBT Training : PASS
2069 11:12:56.403734 Write leveling : PASS
2070 11:12:56.406849 RX DQS gating : PASS
2071 11:12:56.406946 RX DQ/DQS(RDDQC) : PASS
2072 11:12:56.410131 TX DQ/DQS : PASS
2073 11:12:56.413756 RX DATLAT : PASS
2074 11:12:56.413838 RX DQ/DQS(Engine): PASS
2075 11:12:56.416608 TX OE : NO K
2076 11:12:56.416690 All Pass.
2077 11:12:56.416756
2078 11:12:56.420474 CH 1, Rank 1
2079 11:12:56.420556 SW Impedance : PASS
2080 11:12:56.423634 DUTY Scan : NO K
2081 11:12:56.423716 ZQ Calibration : PASS
2082 11:12:56.426796 Jitter Meter : NO K
2083 11:12:56.429738 CBT Training : PASS
2084 11:12:56.429819 Write leveling : PASS
2085 11:12:56.433533 RX DQS gating : PASS
2086 11:12:56.436739 RX DQ/DQS(RDDQC) : PASS
2087 11:12:56.436821 TX DQ/DQS : PASS
2088 11:12:56.439885 RX DATLAT : PASS
2089 11:12:56.443079 RX DQ/DQS(Engine): PASS
2090 11:12:56.443161 TX OE : NO K
2091 11:12:56.446175 All Pass.
2092 11:12:56.446257
2093 11:12:56.446325 DramC Write-DBI off
2094 11:12:56.449910 PER_BANK_REFRESH: Hybrid Mode
2095 11:12:56.453067 TX_TRACKING: ON
2096 11:12:56.456225 [GetDramInforAfterCalByMRR] Vendor 6.
2097 11:12:56.460032 [GetDramInforAfterCalByMRR] Revision 606.
2098 11:12:56.463086 [GetDramInforAfterCalByMRR] Revision 2 0.
2099 11:12:56.463163 MR0 0x3b3b
2100 11:12:56.463225 MR8 0x5151
2101 11:12:56.466714 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2102 11:12:56.469914
2103 11:12:56.469990 MR0 0x3b3b
2104 11:12:56.470058 MR8 0x5151
2105 11:12:56.472904 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2106 11:12:56.472983
2107 11:12:56.483162 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2108 11:12:56.485967 [FAST_K] Save calibration result to emmc
2109 11:12:56.489465 [FAST_K] Save calibration result to emmc
2110 11:12:56.492995 dram_init: config_dvfs: 1
2111 11:12:56.495887 dramc_set_vcore_voltage set vcore to 662500
2112 11:12:56.499491 Read voltage for 1200, 2
2113 11:12:56.499573 Vio18 = 0
2114 11:12:56.499638 Vcore = 662500
2115 11:12:56.503083 Vdram = 0
2116 11:12:56.503165 Vddq = 0
2117 11:12:56.503229 Vmddr = 0
2118 11:12:56.509644 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2119 11:12:56.512606 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2120 11:12:56.515711 MEM_TYPE=3, freq_sel=15
2121 11:12:56.519261 sv_algorithm_assistance_LP4_1600
2122 11:12:56.522995 ============ PULL DRAM RESETB DOWN ============
2123 11:12:56.529238 ========== PULL DRAM RESETB DOWN end =========
2124 11:12:56.532802 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2125 11:12:56.536023 ===================================
2126 11:12:56.539175 LPDDR4 DRAM CONFIGURATION
2127 11:12:56.542443 ===================================
2128 11:12:56.542526 EX_ROW_EN[0] = 0x0
2129 11:12:56.545579 EX_ROW_EN[1] = 0x0
2130 11:12:56.545662 LP4Y_EN = 0x0
2131 11:12:56.549226 WORK_FSP = 0x0
2132 11:12:56.549309 WL = 0x4
2133 11:12:56.552235 RL = 0x4
2134 11:12:56.552316 BL = 0x2
2135 11:12:56.555279 RPST = 0x0
2136 11:12:56.559092 RD_PRE = 0x0
2137 11:12:56.559174 WR_PRE = 0x1
2138 11:12:56.562261 WR_PST = 0x0
2139 11:12:56.562344 DBI_WR = 0x0
2140 11:12:56.565481 DBI_RD = 0x0
2141 11:12:56.565563 OTF = 0x1
2142 11:12:56.569116 ===================================
2143 11:12:56.572343 ===================================
2144 11:12:56.572426 ANA top config
2145 11:12:56.575271 ===================================
2146 11:12:56.578867 DLL_ASYNC_EN = 0
2147 11:12:56.582502 ALL_SLAVE_EN = 0
2148 11:12:56.585598 NEW_RANK_MODE = 1
2149 11:12:56.588658 DLL_IDLE_MODE = 1
2150 11:12:56.588741 LP45_APHY_COMB_EN = 1
2151 11:12:56.592101 TX_ODT_DIS = 1
2152 11:12:56.595411 NEW_8X_MODE = 1
2153 11:12:56.599088 ===================================
2154 11:12:56.602008 ===================================
2155 11:12:56.605592 data_rate = 2400
2156 11:12:56.608657 CKR = 1
2157 11:12:56.608740 DQ_P2S_RATIO = 8
2158 11:12:56.612238 ===================================
2159 11:12:56.615158 CA_P2S_RATIO = 8
2160 11:12:56.618716 DQ_CA_OPEN = 0
2161 11:12:56.622213 DQ_SEMI_OPEN = 0
2162 11:12:56.625147 CA_SEMI_OPEN = 0
2163 11:12:56.628621 CA_FULL_RATE = 0
2164 11:12:56.628739 DQ_CKDIV4_EN = 0
2165 11:12:56.632044 CA_CKDIV4_EN = 0
2166 11:12:56.635466 CA_PREDIV_EN = 0
2167 11:12:56.638612 PH8_DLY = 17
2168 11:12:56.641709 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2169 11:12:56.645552 DQ_AAMCK_DIV = 4
2170 11:12:56.645647 CA_AAMCK_DIV = 4
2171 11:12:56.648747 CA_ADMCK_DIV = 4
2172 11:12:56.651929 DQ_TRACK_CA_EN = 0
2173 11:12:56.655042 CA_PICK = 1200
2174 11:12:56.658684 CA_MCKIO = 1200
2175 11:12:56.661903 MCKIO_SEMI = 0
2176 11:12:56.665321 PLL_FREQ = 2366
2177 11:12:56.668255 DQ_UI_PI_RATIO = 32
2178 11:12:56.668354 CA_UI_PI_RATIO = 0
2179 11:12:56.671392 ===================================
2180 11:12:56.675082 ===================================
2181 11:12:56.678138 memory_type:LPDDR4
2182 11:12:56.681986 GP_NUM : 10
2183 11:12:56.682106 SRAM_EN : 1
2184 11:12:56.684860 MD32_EN : 0
2185 11:12:56.688370 ===================================
2186 11:12:56.691516 [ANA_INIT] >>>>>>>>>>>>>>
2187 11:12:56.694711 <<<<<< [CONFIGURE PHASE]: ANA_TX
2188 11:12:56.698265 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2189 11:12:56.701178 ===================================
2190 11:12:56.701263 data_rate = 2400,PCW = 0X5b00
2191 11:12:56.704947 ===================================
2192 11:12:56.707817 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2193 11:12:56.714481 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2194 11:12:56.720997 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2195 11:12:56.724456 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2196 11:12:56.728172 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2197 11:12:56.731274 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2198 11:12:56.734194 [ANA_INIT] flow start
2199 11:12:56.737702 [ANA_INIT] PLL >>>>>>>>
2200 11:12:56.737798 [ANA_INIT] PLL <<<<<<<<
2201 11:12:56.741383 [ANA_INIT] MIDPI >>>>>>>>
2202 11:12:56.744514 [ANA_INIT] MIDPI <<<<<<<<
2203 11:12:56.744609 [ANA_INIT] DLL >>>>>>>>
2204 11:12:56.747718 [ANA_INIT] DLL <<<<<<<<
2205 11:12:56.750962 [ANA_INIT] flow end
2206 11:12:56.754108 ============ LP4 DIFF to SE enter ============
2207 11:12:56.757915 ============ LP4 DIFF to SE exit ============
2208 11:12:56.760882 [ANA_INIT] <<<<<<<<<<<<<
2209 11:12:56.764105 [Flow] Enable top DCM control >>>>>
2210 11:12:56.767859 [Flow] Enable top DCM control <<<<<
2211 11:12:56.771046 Enable DLL master slave shuffle
2212 11:12:56.774169 ==============================================================
2213 11:12:56.777321 Gating Mode config
2214 11:12:56.784089 ==============================================================
2215 11:12:56.784182 Config description:
2216 11:12:56.794323 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2217 11:12:56.800453 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2218 11:12:56.804030 SELPH_MODE 0: By rank 1: By Phase
2219 11:12:56.810599 ==============================================================
2220 11:12:56.813649 GAT_TRACK_EN = 1
2221 11:12:56.817160 RX_GATING_MODE = 2
2222 11:12:56.820454 RX_GATING_TRACK_MODE = 2
2223 11:12:56.823935 SELPH_MODE = 1
2224 11:12:56.826759 PICG_EARLY_EN = 1
2225 11:12:56.830226 VALID_LAT_VALUE = 1
2226 11:12:56.833417 ==============================================================
2227 11:12:56.837162 Enter into Gating configuration >>>>
2228 11:12:56.840040 Exit from Gating configuration <<<<
2229 11:12:56.843572 Enter into DVFS_PRE_config >>>>>
2230 11:12:56.857002 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2231 11:12:56.860154 Exit from DVFS_PRE_config <<<<<
2232 11:12:56.860238 Enter into PICG configuration >>>>
2233 11:12:56.863374 Exit from PICG configuration <<<<
2234 11:12:56.866868 [RX_INPUT] configuration >>>>>
2235 11:12:56.869961 [RX_INPUT] configuration <<<<<
2236 11:12:56.876978 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2237 11:12:56.879987 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2238 11:12:56.886731 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2239 11:12:56.893402 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2240 11:12:56.900122 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2241 11:12:56.906967 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2242 11:12:56.910060 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2243 11:12:56.913155 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2244 11:12:56.916748 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2245 11:12:56.922867 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2246 11:12:56.926599 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2247 11:12:56.929728 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2248 11:12:56.933074 ===================================
2249 11:12:56.936533 LPDDR4 DRAM CONFIGURATION
2250 11:12:56.939826 ===================================
2251 11:12:56.943138 EX_ROW_EN[0] = 0x0
2252 11:12:56.943221 EX_ROW_EN[1] = 0x0
2253 11:12:56.946175 LP4Y_EN = 0x0
2254 11:12:56.946258 WORK_FSP = 0x0
2255 11:12:56.949806 WL = 0x4
2256 11:12:56.949889 RL = 0x4
2257 11:12:56.952710 BL = 0x2
2258 11:12:56.952793 RPST = 0x0
2259 11:12:56.956202 RD_PRE = 0x0
2260 11:12:56.956284 WR_PRE = 0x1
2261 11:12:56.959427 WR_PST = 0x0
2262 11:12:56.959509 DBI_WR = 0x0
2263 11:12:56.962534 DBI_RD = 0x0
2264 11:12:56.962616 OTF = 0x1
2265 11:12:56.966322 ===================================
2266 11:12:56.972473 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2267 11:12:56.976274 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2268 11:12:56.979441 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2269 11:12:56.982461 ===================================
2270 11:12:56.986154 LPDDR4 DRAM CONFIGURATION
2271 11:12:56.989246 ===================================
2272 11:12:56.992427 EX_ROW_EN[0] = 0x10
2273 11:12:56.992529 EX_ROW_EN[1] = 0x0
2274 11:12:56.995965 LP4Y_EN = 0x0
2275 11:12:56.996064 WORK_FSP = 0x0
2276 11:12:56.999530 WL = 0x4
2277 11:12:56.999632 RL = 0x4
2278 11:12:57.002640 BL = 0x2
2279 11:12:57.002715 RPST = 0x0
2280 11:12:57.005834 RD_PRE = 0x0
2281 11:12:57.005930 WR_PRE = 0x1
2282 11:12:57.009500 WR_PST = 0x0
2283 11:12:57.009599 DBI_WR = 0x0
2284 11:12:57.012466 DBI_RD = 0x0
2285 11:12:57.012535 OTF = 0x1
2286 11:12:57.015655 ===================================
2287 11:12:57.022508 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2288 11:12:57.022593 ==
2289 11:12:57.025465 Dram Type= 6, Freq= 0, CH_0, rank 0
2290 11:12:57.032570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2291 11:12:57.032651 ==
2292 11:12:57.032716 [Duty_Offset_Calibration]
2293 11:12:57.035694 B0:2 B1:0 CA:3
2294 11:12:57.035768
2295 11:12:57.039112 [DutyScan_Calibration_Flow] k_type=0
2296 11:12:57.047503
2297 11:12:57.047584 ==CLK 0==
2298 11:12:57.051153 Final CLK duty delay cell = 0
2299 11:12:57.054098 [0] MAX Duty = 5031%(X100), DQS PI = 12
2300 11:12:57.057724 [0] MIN Duty = 4875%(X100), DQS PI = 58
2301 11:12:57.061105 [0] AVG Duty = 4953%(X100)
2302 11:12:57.061180
2303 11:12:57.064421 CH0 CLK Duty spec in!! Max-Min= 156%
2304 11:12:57.067537 [DutyScan_Calibration_Flow] ====Done====
2305 11:12:57.067641
2306 11:12:57.070694 [DutyScan_Calibration_Flow] k_type=1
2307 11:12:57.086316
2308 11:12:57.086445 ==DQS 0 ==
2309 11:12:57.089461 Final DQS duty delay cell = 0
2310 11:12:57.092445 [0] MAX Duty = 5062%(X100), DQS PI = 12
2311 11:12:57.096417 [0] MIN Duty = 4907%(X100), DQS PI = 2
2312 11:12:57.099211 [0] AVG Duty = 4984%(X100)
2313 11:12:57.099306
2314 11:12:57.099371 ==DQS 1 ==
2315 11:12:57.102770 Final DQS duty delay cell = -4
2316 11:12:57.106145 [-4] MAX Duty = 4969%(X100), DQS PI = 22
2317 11:12:57.109098 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2318 11:12:57.112147 [-4] AVG Duty = 4922%(X100)
2319 11:12:57.112258
2320 11:12:57.115758 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2321 11:12:57.115835
2322 11:12:57.119026 CH0 DQS 1 Duty spec in!! Max-Min= 94%
2323 11:12:57.122176 [DutyScan_Calibration_Flow] ====Done====
2324 11:12:57.122293
2325 11:12:57.125272 [DutyScan_Calibration_Flow] k_type=3
2326 11:12:57.143544
2327 11:12:57.143648 ==DQM 0 ==
2328 11:12:57.147170 Final DQM duty delay cell = 0
2329 11:12:57.150184 [0] MAX Duty = 5124%(X100), DQS PI = 28
2330 11:12:57.153549 [0] MIN Duty = 4876%(X100), DQS PI = 0
2331 11:12:57.153634 [0] AVG Duty = 5000%(X100)
2332 11:12:57.157003
2333 11:12:57.157105 ==DQM 1 ==
2334 11:12:57.160564 Final DQM duty delay cell = 4
2335 11:12:57.163481 [4] MAX Duty = 5124%(X100), DQS PI = 50
2336 11:12:57.166770 [4] MIN Duty = 5000%(X100), DQS PI = 14
2337 11:12:57.166877 [4] AVG Duty = 5062%(X100)
2338 11:12:57.170403
2339 11:12:57.173483 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2340 11:12:57.173564
2341 11:12:57.177146 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2342 11:12:57.180271 [DutyScan_Calibration_Flow] ====Done====
2343 11:12:57.180352
2344 11:12:57.183390 [DutyScan_Calibration_Flow] k_type=2
2345 11:12:57.198533
2346 11:12:57.198638 ==DQ 0 ==
2347 11:12:57.201479 Final DQ duty delay cell = -4
2348 11:12:57.205180 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2349 11:12:57.208510 [-4] MIN Duty = 4907%(X100), DQS PI = 44
2350 11:12:57.211447 [-4] AVG Duty = 4969%(X100)
2351 11:12:57.211523
2352 11:12:57.211586 ==DQ 1 ==
2353 11:12:57.215291 Final DQ duty delay cell = -4
2354 11:12:57.218251 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2355 11:12:57.221316 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2356 11:12:57.225095 [-4] AVG Duty = 4938%(X100)
2357 11:12:57.225184
2358 11:12:57.228212 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2359 11:12:57.228291
2360 11:12:57.231320 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2361 11:12:57.234792 [DutyScan_Calibration_Flow] ====Done====
2362 11:12:57.234897 ==
2363 11:12:57.237831 Dram Type= 6, Freq= 0, CH_1, rank 0
2364 11:12:57.241554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2365 11:12:57.241639 ==
2366 11:12:57.244541 [Duty_Offset_Calibration]
2367 11:12:57.244629 B0:1 B1:-3 CA:0
2368 11:12:57.248307
2369 11:12:57.251460 [DutyScan_Calibration_Flow] k_type=0
2370 11:12:57.259186
2371 11:12:57.259270 ==CLK 0==
2372 11:12:57.262103 Final CLK duty delay cell = 0
2373 11:12:57.265609 [0] MAX Duty = 5031%(X100), DQS PI = 18
2374 11:12:57.269291 [0] MIN Duty = 4844%(X100), DQS PI = 2
2375 11:12:57.269375 [0] AVG Duty = 4937%(X100)
2376 11:12:57.272309
2377 11:12:57.275788 CH1 CLK Duty spec in!! Max-Min= 187%
2378 11:12:57.278630 [DutyScan_Calibration_Flow] ====Done====
2379 11:12:57.278715
2380 11:12:57.282265 [DutyScan_Calibration_Flow] k_type=1
2381 11:12:57.297436
2382 11:12:57.297586 ==DQS 0 ==
2383 11:12:57.301179 Final DQS duty delay cell = -4
2384 11:12:57.304180 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2385 11:12:57.307321 [-4] MIN Duty = 4907%(X100), DQS PI = 2
2386 11:12:57.310363 [-4] AVG Duty = 4969%(X100)
2387 11:12:57.310447
2388 11:12:57.310513 ==DQS 1 ==
2389 11:12:57.314079 Final DQS duty delay cell = 0
2390 11:12:57.317302 [0] MAX Duty = 5094%(X100), DQS PI = 0
2391 11:12:57.320699 [0] MIN Duty = 4844%(X100), DQS PI = 26
2392 11:12:57.324013 [0] AVG Duty = 4969%(X100)
2393 11:12:57.324097
2394 11:12:57.327241 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2395 11:12:57.327325
2396 11:12:57.330362 CH1 DQS 1 Duty spec in!! Max-Min= 250%
2397 11:12:57.333498 [DutyScan_Calibration_Flow] ====Done====
2398 11:12:57.333582
2399 11:12:57.337216 [DutyScan_Calibration_Flow] k_type=3
2400 11:12:57.354449
2401 11:12:57.354540 ==DQM 0 ==
2402 11:12:57.357765 Final DQM duty delay cell = 0
2403 11:12:57.360796 [0] MAX Duty = 5000%(X100), DQS PI = 22
2404 11:12:57.363858 [0] MIN Duty = 4876%(X100), DQS PI = 36
2405 11:12:57.367616 [0] AVG Duty = 4938%(X100)
2406 11:12:57.367702
2407 11:12:57.367768 ==DQM 1 ==
2408 11:12:57.370985 Final DQM duty delay cell = 0
2409 11:12:57.373993 [0] MAX Duty = 5031%(X100), DQS PI = 18
2410 11:12:57.377595 [0] MIN Duty = 4907%(X100), DQS PI = 12
2411 11:12:57.380490 [0] AVG Duty = 4969%(X100)
2412 11:12:57.380573
2413 11:12:57.383945 CH1 DQM 0 Duty spec in!! Max-Min= 124%
2414 11:12:57.384033
2415 11:12:57.387406 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2416 11:12:57.390495 [DutyScan_Calibration_Flow] ====Done====
2417 11:12:57.390603
2418 11:12:57.393638 [DutyScan_Calibration_Flow] k_type=2
2419 11:12:57.410954
2420 11:12:57.411043 ==DQ 0 ==
2421 11:12:57.413919 Final DQ duty delay cell = 0
2422 11:12:57.417004 [0] MAX Duty = 5062%(X100), DQS PI = 18
2423 11:12:57.420721 [0] MIN Duty = 4938%(X100), DQS PI = 54
2424 11:12:57.420805 [0] AVG Duty = 5000%(X100)
2425 11:12:57.423843
2426 11:12:57.423926 ==DQ 1 ==
2427 11:12:57.426959 Final DQ duty delay cell = 0
2428 11:12:57.430980 [0] MAX Duty = 5124%(X100), DQS PI = 36
2429 11:12:57.433838 [0] MIN Duty = 4969%(X100), DQS PI = 26
2430 11:12:57.433922 [0] AVG Duty = 5046%(X100)
2431 11:12:57.436917
2432 11:12:57.440706 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2433 11:12:57.440791
2434 11:12:57.443879 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2435 11:12:57.447043 [DutyScan_Calibration_Flow] ====Done====
2436 11:12:57.450604 nWR fixed to 30
2437 11:12:57.450690 [ModeRegInit_LP4] CH0 RK0
2438 11:12:57.453498 [ModeRegInit_LP4] CH0 RK1
2439 11:12:57.456973 [ModeRegInit_LP4] CH1 RK0
2440 11:12:57.460739 [ModeRegInit_LP4] CH1 RK1
2441 11:12:57.460825 match AC timing 7
2442 11:12:57.466862 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2443 11:12:57.469957 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2444 11:12:57.473684 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2445 11:12:57.480202 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2446 11:12:57.483243 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2447 11:12:57.483316 ==
2448 11:12:57.486960 Dram Type= 6, Freq= 0, CH_0, rank 0
2449 11:12:57.489989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2450 11:12:57.490073 ==
2451 11:12:57.496607 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2452 11:12:57.503554 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2453 11:12:57.510729 [CA 0] Center 40 (10~70) winsize 61
2454 11:12:57.513863 [CA 1] Center 39 (9~70) winsize 62
2455 11:12:57.517611 [CA 2] Center 36 (6~66) winsize 61
2456 11:12:57.520657 [CA 3] Center 35 (5~66) winsize 62
2457 11:12:57.523800 [CA 4] Center 34 (4~65) winsize 62
2458 11:12:57.527540 [CA 5] Center 33 (3~63) winsize 61
2459 11:12:57.527623
2460 11:12:57.530577 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2461 11:12:57.530662
2462 11:12:57.534148 [CATrainingPosCal] consider 1 rank data
2463 11:12:57.537402 u2DelayCellTimex100 = 270/100 ps
2464 11:12:57.540538 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2465 11:12:57.547476 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2466 11:12:57.550681 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2467 11:12:57.553968 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2468 11:12:57.557473 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2469 11:12:57.560553 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2470 11:12:57.560635
2471 11:12:57.563864 CA PerBit enable=1, Macro0, CA PI delay=33
2472 11:12:57.563972
2473 11:12:57.567378 [CBTSetCACLKResult] CA Dly = 33
2474 11:12:57.570343 CS Dly: 7 (0~38)
2475 11:12:57.570425 ==
2476 11:12:57.573807 Dram Type= 6, Freq= 0, CH_0, rank 1
2477 11:12:57.576852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2478 11:12:57.576943 ==
2479 11:12:57.583997 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2480 11:12:57.586985 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2481 11:12:57.596485 [CA 0] Center 40 (10~70) winsize 61
2482 11:12:57.600131 [CA 1] Center 39 (9~70) winsize 62
2483 11:12:57.603219 [CA 2] Center 35 (5~66) winsize 62
2484 11:12:57.607041 [CA 3] Center 35 (5~66) winsize 62
2485 11:12:57.610315 [CA 4] Center 34 (4~65) winsize 62
2486 11:12:57.613188 [CA 5] Center 33 (3~64) winsize 62
2487 11:12:57.613301
2488 11:12:57.616854 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2489 11:12:57.616938
2490 11:12:57.620048 [CATrainingPosCal] consider 2 rank data
2491 11:12:57.623557 u2DelayCellTimex100 = 270/100 ps
2492 11:12:57.626625 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2493 11:12:57.633557 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2494 11:12:57.636870 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2495 11:12:57.639962 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2496 11:12:57.643100 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2497 11:12:57.646372 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2498 11:12:57.646455
2499 11:12:57.650092 CA PerBit enable=1, Macro0, CA PI delay=33
2500 11:12:57.650175
2501 11:12:57.653323 [CBTSetCACLKResult] CA Dly = 33
2502 11:12:57.656395 CS Dly: 8 (0~40)
2503 11:12:57.656477
2504 11:12:57.659455 ----->DramcWriteLeveling(PI) begin...
2505 11:12:57.659574 ==
2506 11:12:57.663269 Dram Type= 6, Freq= 0, CH_0, rank 0
2507 11:12:57.666324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2508 11:12:57.666407 ==
2509 11:12:57.669887 Write leveling (Byte 0): 31 => 31
2510 11:12:57.673215 Write leveling (Byte 1): 28 => 28
2511 11:12:57.676062 DramcWriteLeveling(PI) end<-----
2512 11:12:57.676145
2513 11:12:57.676211 ==
2514 11:12:57.679665 Dram Type= 6, Freq= 0, CH_0, rank 0
2515 11:12:57.683144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2516 11:12:57.683242 ==
2517 11:12:57.686064 [Gating] SW mode calibration
2518 11:12:57.692562 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2519 11:12:57.699569 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2520 11:12:57.703118 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2521 11:12:57.705975 0 15 4 | B1->B0 | 2929 3434 | 0 1 | (0 0) (1 1)
2522 11:12:57.712761 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2523 11:12:57.716393 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2524 11:12:57.719409 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2525 11:12:57.726244 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2526 11:12:57.729188 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2527 11:12:57.733006 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2528 11:12:57.739151 1 0 0 | B1->B0 | 3131 2828 | 0 0 | (0 0) (0 0)
2529 11:12:57.743193 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2530 11:12:57.746052 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2531 11:12:57.752375 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2532 11:12:57.756119 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2533 11:12:57.759353 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2534 11:12:57.765983 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2535 11:12:57.768945 1 0 28 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
2536 11:12:57.772648 1 1 0 | B1->B0 | 2424 3030 | 0 0 | (0 0) (0 0)
2537 11:12:57.778726 1 1 4 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
2538 11:12:57.782238 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2539 11:12:57.785776 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2540 11:12:57.792106 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2541 11:12:57.795659 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2542 11:12:57.798489 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2543 11:12:57.805090 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2544 11:12:57.808632 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2545 11:12:57.812284 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2546 11:12:57.818535 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 11:12:57.822121 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 11:12:57.825155 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 11:12:57.831800 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 11:12:57.835040 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 11:12:57.838797 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 11:12:57.841953 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 11:12:57.848582 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 11:12:57.851834 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 11:12:57.855052 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 11:12:57.861977 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 11:12:57.865276 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 11:12:57.868077 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 11:12:57.875062 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2560 11:12:57.878308 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2561 11:12:57.881462 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2562 11:12:57.884534 Total UI for P1: 0, mck2ui 16
2563 11:12:57.888083 best dqsien dly found for B0: ( 1, 3, 30)
2564 11:12:57.891669 Total UI for P1: 0, mck2ui 16
2565 11:12:57.894464 best dqsien dly found for B1: ( 1, 4, 2)
2566 11:12:57.897959 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2567 11:12:57.901487 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2568 11:12:57.904472
2569 11:12:57.908009 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2570 11:12:57.911586 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2571 11:12:57.914468 [Gating] SW calibration Done
2572 11:12:57.914551 ==
2573 11:12:57.918321 Dram Type= 6, Freq= 0, CH_0, rank 0
2574 11:12:57.921070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2575 11:12:57.921153 ==
2576 11:12:57.921219 RX Vref Scan: 0
2577 11:12:57.921281
2578 11:12:57.924587 RX Vref 0 -> 0, step: 1
2579 11:12:57.924670
2580 11:12:57.928048 RX Delay -40 -> 252, step: 8
2581 11:12:57.931477 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2582 11:12:57.934464 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2583 11:12:57.941409 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2584 11:12:57.944597 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2585 11:12:57.947590 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2586 11:12:57.951255 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2587 11:12:57.954436 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2588 11:12:57.961421 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2589 11:12:57.964605 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2590 11:12:57.967681 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2591 11:12:57.970788 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2592 11:12:57.973999 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2593 11:12:57.980826 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2594 11:12:57.983937 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2595 11:12:57.987103 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2596 11:12:57.990977 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2597 11:12:57.991088 ==
2598 11:12:57.994096 Dram Type= 6, Freq= 0, CH_0, rank 0
2599 11:12:58.000771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2600 11:12:58.000855 ==
2601 11:12:58.000963 DQS Delay:
2602 11:12:58.001026 DQS0 = 0, DQS1 = 0
2603 11:12:58.004185 DQM Delay:
2604 11:12:58.004268 DQM0 = 113, DQM1 = 103
2605 11:12:58.007523 DQ Delay:
2606 11:12:58.010430 DQ0 =111, DQ1 =115, DQ2 =115, DQ3 =107
2607 11:12:58.014001 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2608 11:12:58.017385 DQ8 =95, DQ9 =83, DQ10 =103, DQ11 =95
2609 11:12:58.020424 DQ12 =111, DQ13 =111, DQ14 =115, DQ15 =111
2610 11:12:58.020507
2611 11:12:58.020573
2612 11:12:58.020634 ==
2613 11:12:58.023941 Dram Type= 6, Freq= 0, CH_0, rank 0
2614 11:12:58.027402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2615 11:12:58.027486 ==
2616 11:12:58.027551
2617 11:12:58.030402
2618 11:12:58.030483 TX Vref Scan disable
2619 11:12:58.033737 == TX Byte 0 ==
2620 11:12:58.037504 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2621 11:12:58.040284 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2622 11:12:58.043695 == TX Byte 1 ==
2623 11:12:58.046795 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2624 11:12:58.050539 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2625 11:12:58.050622 ==
2626 11:12:58.053566 Dram Type= 6, Freq= 0, CH_0, rank 0
2627 11:12:58.059896 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2628 11:12:58.059979 ==
2629 11:12:58.071368 TX Vref=22, minBit 0, minWin=25, winSum=413
2630 11:12:58.074440 TX Vref=24, minBit 8, minWin=25, winSum=422
2631 11:12:58.077835 TX Vref=26, minBit 4, minWin=26, winSum=428
2632 11:12:58.080765 TX Vref=28, minBit 5, minWin=25, winSum=436
2633 11:12:58.083939 TX Vref=30, minBit 8, minWin=25, winSum=436
2634 11:12:58.090715 TX Vref=32, minBit 8, minWin=25, winSum=430
2635 11:12:58.094326 [TxChooseVref] Worse bit 4, Min win 26, Win sum 428, Final Vref 26
2636 11:12:58.094417
2637 11:12:58.097536 Final TX Range 1 Vref 26
2638 11:12:58.097646
2639 11:12:58.097738 ==
2640 11:12:58.100654 Dram Type= 6, Freq= 0, CH_0, rank 0
2641 11:12:58.104438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2642 11:12:58.107371 ==
2643 11:12:58.107454
2644 11:12:58.107518
2645 11:12:58.107580 TX Vref Scan disable
2646 11:12:58.110720 == TX Byte 0 ==
2647 11:12:58.114122 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2648 11:12:58.120944 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2649 11:12:58.121068 == TX Byte 1 ==
2650 11:12:58.124101 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2651 11:12:58.130810 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2652 11:12:58.130917
2653 11:12:58.130984 [DATLAT]
2654 11:12:58.131045 Freq=1200, CH0 RK0
2655 11:12:58.131118
2656 11:12:58.133822 DATLAT Default: 0xd
2657 11:12:58.137085 0, 0xFFFF, sum = 0
2658 11:12:58.137236 1, 0xFFFF, sum = 0
2659 11:12:58.140580 2, 0xFFFF, sum = 0
2660 11:12:58.140665 3, 0xFFFF, sum = 0
2661 11:12:58.143473 4, 0xFFFF, sum = 0
2662 11:12:58.143546 5, 0xFFFF, sum = 0
2663 11:12:58.146778 6, 0xFFFF, sum = 0
2664 11:12:58.146888 7, 0xFFFF, sum = 0
2665 11:12:58.150152 8, 0xFFFF, sum = 0
2666 11:12:58.150225 9, 0xFFFF, sum = 0
2667 11:12:58.153655 10, 0xFFFF, sum = 0
2668 11:12:58.153726 11, 0xFFFF, sum = 0
2669 11:12:58.156503 12, 0x0, sum = 1
2670 11:12:58.156573 13, 0x0, sum = 2
2671 11:12:58.160276 14, 0x0, sum = 3
2672 11:12:58.160364 15, 0x0, sum = 4
2673 11:12:58.163378 best_step = 13
2674 11:12:58.163460
2675 11:12:58.163525 ==
2676 11:12:58.167062 Dram Type= 6, Freq= 0, CH_0, rank 0
2677 11:12:58.170183 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2678 11:12:58.170266 ==
2679 11:12:58.173384 RX Vref Scan: 1
2680 11:12:58.173466
2681 11:12:58.173531 Set Vref Range= 32 -> 127
2682 11:12:58.173592
2683 11:12:58.176598 RX Vref 32 -> 127, step: 1
2684 11:12:58.176681
2685 11:12:58.179730 RX Delay -37 -> 252, step: 4
2686 11:12:58.179811
2687 11:12:58.183532 Set Vref, RX VrefLevel [Byte0]: 32
2688 11:12:58.186656 [Byte1]: 32
2689 11:12:58.186763
2690 11:12:58.189809 Set Vref, RX VrefLevel [Byte0]: 33
2691 11:12:58.193028 [Byte1]: 33
2692 11:12:58.197385
2693 11:12:58.197467 Set Vref, RX VrefLevel [Byte0]: 34
2694 11:12:58.200737 [Byte1]: 34
2695 11:12:58.205627
2696 11:12:58.205709 Set Vref, RX VrefLevel [Byte0]: 35
2697 11:12:58.208644 [Byte1]: 35
2698 11:12:58.213606
2699 11:12:58.213688 Set Vref, RX VrefLevel [Byte0]: 36
2700 11:12:58.216538 [Byte1]: 36
2701 11:12:58.221629
2702 11:12:58.221710 Set Vref, RX VrefLevel [Byte0]: 37
2703 11:12:58.224444 [Byte1]: 37
2704 11:12:58.229296
2705 11:12:58.229378 Set Vref, RX VrefLevel [Byte0]: 38
2706 11:12:58.232772 [Byte1]: 38
2707 11:12:58.237341
2708 11:12:58.237424 Set Vref, RX VrefLevel [Byte0]: 39
2709 11:12:58.240954 [Byte1]: 39
2710 11:12:58.245659
2711 11:12:58.245742 Set Vref, RX VrefLevel [Byte0]: 40
2712 11:12:58.248700 [Byte1]: 40
2713 11:12:58.253215
2714 11:12:58.253299 Set Vref, RX VrefLevel [Byte0]: 41
2715 11:12:58.256760 [Byte1]: 41
2716 11:12:58.261371
2717 11:12:58.261480 Set Vref, RX VrefLevel [Byte0]: 42
2718 11:12:58.264768 [Byte1]: 42
2719 11:12:58.269783
2720 11:12:58.269882 Set Vref, RX VrefLevel [Byte0]: 43
2721 11:12:58.272980 [Byte1]: 43
2722 11:12:58.277409
2723 11:12:58.277479 Set Vref, RX VrefLevel [Byte0]: 44
2724 11:12:58.280755 [Byte1]: 44
2725 11:12:58.285459
2726 11:12:58.285558 Set Vref, RX VrefLevel [Byte0]: 45
2727 11:12:58.288555 [Byte1]: 45
2728 11:12:58.293645
2729 11:12:58.293747 Set Vref, RX VrefLevel [Byte0]: 46
2730 11:12:58.296782 [Byte1]: 46
2731 11:12:58.301157
2732 11:12:58.301257 Set Vref, RX VrefLevel [Byte0]: 47
2733 11:12:58.304933 [Byte1]: 47
2734 11:12:58.309451
2735 11:12:58.309547 Set Vref, RX VrefLevel [Byte0]: 48
2736 11:12:58.312549 [Byte1]: 48
2737 11:12:58.317514
2738 11:12:58.317609 Set Vref, RX VrefLevel [Byte0]: 49
2739 11:12:58.320499 [Byte1]: 49
2740 11:12:58.325296
2741 11:12:58.325395 Set Vref, RX VrefLevel [Byte0]: 50
2742 11:12:58.328715 [Byte1]: 50
2743 11:12:58.333362
2744 11:12:58.333436 Set Vref, RX VrefLevel [Byte0]: 51
2745 11:12:58.336747 [Byte1]: 51
2746 11:12:58.341522
2747 11:12:58.341592 Set Vref, RX VrefLevel [Byte0]: 52
2748 11:12:58.344481 [Byte1]: 52
2749 11:12:58.349624
2750 11:12:58.349720 Set Vref, RX VrefLevel [Byte0]: 53
2751 11:12:58.352721 [Byte1]: 53
2752 11:12:58.357368
2753 11:12:58.357468 Set Vref, RX VrefLevel [Byte0]: 54
2754 11:12:58.360793 [Byte1]: 54
2755 11:12:58.365534
2756 11:12:58.365631 Set Vref, RX VrefLevel [Byte0]: 55
2757 11:12:58.368524 [Byte1]: 55
2758 11:12:58.373106
2759 11:12:58.373203 Set Vref, RX VrefLevel [Byte0]: 56
2760 11:12:58.376779 [Byte1]: 56
2761 11:12:58.381145
2762 11:12:58.381245 Set Vref, RX VrefLevel [Byte0]: 57
2763 11:12:58.384904 [Byte1]: 57
2764 11:12:58.389341
2765 11:12:58.389448 Set Vref, RX VrefLevel [Byte0]: 58
2766 11:12:58.392412 [Byte1]: 58
2767 11:12:58.397770
2768 11:12:58.397875 Set Vref, RX VrefLevel [Byte0]: 59
2769 11:12:58.400673 [Byte1]: 59
2770 11:12:58.405584
2771 11:12:58.405684 Set Vref, RX VrefLevel [Byte0]: 60
2772 11:12:58.408652 [Byte1]: 60
2773 11:12:58.413125
2774 11:12:58.413231 Set Vref, RX VrefLevel [Byte0]: 61
2775 11:12:58.417140 [Byte1]: 61
2776 11:12:58.421319
2777 11:12:58.421417 Set Vref, RX VrefLevel [Byte0]: 62
2778 11:12:58.424432 [Byte1]: 62
2779 11:12:58.429427
2780 11:12:58.429525 Set Vref, RX VrefLevel [Byte0]: 63
2781 11:12:58.432492 [Byte1]: 63
2782 11:12:58.437555
2783 11:12:58.437655 Set Vref, RX VrefLevel [Byte0]: 64
2784 11:12:58.440584 [Byte1]: 64
2785 11:12:58.445305
2786 11:12:58.445404 Set Vref, RX VrefLevel [Byte0]: 65
2787 11:12:58.448770 [Byte1]: 65
2788 11:12:58.453510
2789 11:12:58.453582 Set Vref, RX VrefLevel [Byte0]: 66
2790 11:12:58.456928 [Byte1]: 66
2791 11:12:58.461557
2792 11:12:58.461656 Set Vref, RX VrefLevel [Byte0]: 67
2793 11:12:58.464501 [Byte1]: 67
2794 11:12:58.469157
2795 11:12:58.469254 Set Vref, RX VrefLevel [Byte0]: 68
2796 11:12:58.472640 [Byte1]: 68
2797 11:12:58.477299
2798 11:12:58.477401 Set Vref, RX VrefLevel [Byte0]: 69
2799 11:12:58.480731 [Byte1]: 69
2800 11:12:58.485430
2801 11:12:58.485537 Set Vref, RX VrefLevel [Byte0]: 70
2802 11:12:58.488772 [Byte1]: 70
2803 11:12:58.493568
2804 11:12:58.493654 Set Vref, RX VrefLevel [Byte0]: 71
2805 11:12:58.496777 [Byte1]: 71
2806 11:12:58.501736
2807 11:12:58.501821 Set Vref, RX VrefLevel [Byte0]: 72
2808 11:12:58.504877 [Byte1]: 72
2809 11:12:58.509185
2810 11:12:58.509267 Set Vref, RX VrefLevel [Byte0]: 73
2811 11:12:58.512877 [Byte1]: 73
2812 11:12:58.517328
2813 11:12:58.517411 Set Vref, RX VrefLevel [Byte0]: 74
2814 11:12:58.520728 [Byte1]: 74
2815 11:12:58.525564
2816 11:12:58.525646 Final RX Vref Byte 0 = 62 to rank0
2817 11:12:58.528695 Final RX Vref Byte 1 = 56 to rank0
2818 11:12:58.531878 Final RX Vref Byte 0 = 62 to rank1
2819 11:12:58.535075 Final RX Vref Byte 1 = 56 to rank1==
2820 11:12:58.538629 Dram Type= 6, Freq= 0, CH_0, rank 0
2821 11:12:58.545357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2822 11:12:58.545442 ==
2823 11:12:58.545508 DQS Delay:
2824 11:12:58.548508 DQS0 = 0, DQS1 = 0
2825 11:12:58.548591 DQM Delay:
2826 11:12:58.548656 DQM0 = 112, DQM1 = 102
2827 11:12:58.551537 DQ Delay:
2828 11:12:58.554992 DQ0 =112, DQ1 =112, DQ2 =114, DQ3 =108
2829 11:12:58.558337 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2830 11:12:58.561401 DQ8 =94, DQ9 =86, DQ10 =104, DQ11 =94
2831 11:12:58.565046 DQ12 =108, DQ13 =108, DQ14 =116, DQ15 =108
2832 11:12:58.565153
2833 11:12:58.565246
2834 11:12:58.575095 [DQSOSCAuto] RK0, (LSB)MR18= 0xf9f9, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 412 ps
2835 11:12:58.575218 CH0 RK0: MR19=303, MR18=F9F9
2836 11:12:58.581694 CH0_RK0: MR19=0x303, MR18=0xF9F9, DQSOSC=412, MR23=63, INC=38, DEC=25
2837 11:12:58.581805
2838 11:12:58.585189 ----->DramcWriteLeveling(PI) begin...
2839 11:12:58.585298 ==
2840 11:12:58.588121 Dram Type= 6, Freq= 0, CH_0, rank 1
2841 11:12:58.595167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2842 11:12:58.595272 ==
2843 11:12:58.598365 Write leveling (Byte 0): 31 => 31
2844 11:12:58.598467 Write leveling (Byte 1): 31 => 31
2845 11:12:58.601697 DramcWriteLeveling(PI) end<-----
2846 11:12:58.601795
2847 11:12:58.601886 ==
2848 11:12:58.605162 Dram Type= 6, Freq= 0, CH_0, rank 1
2849 11:12:58.611363 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2850 11:12:58.611466 ==
2851 11:12:58.615029 [Gating] SW mode calibration
2852 11:12:58.621276 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2853 11:12:58.625027 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2854 11:12:58.631394 0 15 0 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
2855 11:12:58.634459 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2856 11:12:58.638227 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2857 11:12:58.644455 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2858 11:12:58.648083 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2859 11:12:58.651289 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2860 11:12:58.658052 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
2861 11:12:58.660929 0 15 28 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
2862 11:12:58.664389 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2863 11:12:58.671518 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2864 11:12:58.674506 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2865 11:12:58.678367 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2866 11:12:58.684337 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2867 11:12:58.687861 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2868 11:12:58.690696 1 0 24 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
2869 11:12:58.697381 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2870 11:12:58.700748 1 1 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
2871 11:12:58.703804 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2872 11:12:58.710752 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 11:12:58.713852 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 11:12:58.716975 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2875 11:12:58.723822 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2876 11:12:58.726988 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2877 11:12:58.731092 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2878 11:12:58.737179 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 11:12:58.740359 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 11:12:58.744117 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 11:12:58.747497 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 11:12:58.754154 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 11:12:58.757230 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 11:12:58.760686 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 11:12:58.767023 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 11:12:58.770574 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 11:12:58.773479 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 11:12:58.780562 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 11:12:58.783513 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 11:12:58.787061 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 11:12:58.793436 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 11:12:58.796640 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2893 11:12:58.800349 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2894 11:12:58.807033 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2895 11:12:58.810152 Total UI for P1: 0, mck2ui 16
2896 11:12:58.813421 best dqsien dly found for B0: ( 1, 3, 26)
2897 11:12:58.816544 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2898 11:12:58.819696 Total UI for P1: 0, mck2ui 16
2899 11:12:58.823335 best dqsien dly found for B1: ( 1, 4, 0)
2900 11:12:58.826469 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2901 11:12:58.829636 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2902 11:12:58.829720
2903 11:12:58.833410 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2904 11:12:58.836610 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2905 11:12:58.839754 [Gating] SW calibration Done
2906 11:12:58.839837 ==
2907 11:12:58.843019 Dram Type= 6, Freq= 0, CH_0, rank 1
2908 11:12:58.850130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2909 11:12:58.850214 ==
2910 11:12:58.850280 RX Vref Scan: 0
2911 11:12:58.850341
2912 11:12:58.853168 RX Vref 0 -> 0, step: 1
2913 11:12:58.853251
2914 11:12:58.856409 RX Delay -40 -> 252, step: 8
2915 11:12:58.859555 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2916 11:12:58.862682 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2917 11:12:58.866339 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2918 11:12:58.869337 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2919 11:12:58.876345 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2920 11:12:58.879560 iDelay=200, Bit 5, Center 99 (32 ~ 167) 136
2921 11:12:58.882976 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2922 11:12:58.885799 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2923 11:12:58.889308 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2924 11:12:58.896424 iDelay=200, Bit 9, Center 83 (8 ~ 159) 152
2925 11:12:58.899107 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2926 11:12:58.902505 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2927 11:12:58.906307 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2928 11:12:58.909004 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2929 11:12:58.916062 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2930 11:12:58.919140 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2931 11:12:58.919224 ==
2932 11:12:58.922318 Dram Type= 6, Freq= 0, CH_0, rank 1
2933 11:12:58.926381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2934 11:12:58.926465 ==
2935 11:12:58.929413 DQS Delay:
2936 11:12:58.929496 DQS0 = 0, DQS1 = 0
2937 11:12:58.929562 DQM Delay:
2938 11:12:58.932522 DQM0 = 112, DQM1 = 102
2939 11:12:58.932606 DQ Delay:
2940 11:12:58.935705 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2941 11:12:58.938904 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2942 11:12:58.942098 DQ8 =91, DQ9 =83, DQ10 =107, DQ11 =95
2943 11:12:58.949035 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
2944 11:12:58.949144
2945 11:12:58.949228
2946 11:12:58.949290 ==
2947 11:12:58.952161 Dram Type= 6, Freq= 0, CH_0, rank 1
2948 11:12:58.955394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2949 11:12:58.955478 ==
2950 11:12:58.955543
2951 11:12:58.955605
2952 11:12:58.959096 TX Vref Scan disable
2953 11:12:58.959179 == TX Byte 0 ==
2954 11:12:58.965333 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2955 11:12:58.968943 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2956 11:12:58.969027 == TX Byte 1 ==
2957 11:12:58.975086 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2958 11:12:58.978716 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2959 11:12:58.978799 ==
2960 11:12:58.981662 Dram Type= 6, Freq= 0, CH_0, rank 1
2961 11:12:58.985033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2962 11:12:58.985117 ==
2963 11:12:58.998548 TX Vref=22, minBit 2, minWin=26, winSum=428
2964 11:12:59.001443 TX Vref=24, minBit 0, minWin=27, winSum=435
2965 11:12:59.005010 TX Vref=26, minBit 1, minWin=26, winSum=435
2966 11:12:59.008141 TX Vref=28, minBit 5, minWin=26, winSum=440
2967 11:12:59.011595 TX Vref=30, minBit 5, minWin=26, winSum=437
2968 11:12:59.018045 TX Vref=32, minBit 1, minWin=27, winSum=437
2969 11:12:59.021478 [TxChooseVref] Worse bit 1, Min win 27, Win sum 437, Final Vref 32
2970 11:12:59.021562
2971 11:12:59.024408 Final TX Range 1 Vref 32
2972 11:12:59.024491
2973 11:12:59.024555 ==
2974 11:12:59.028042 Dram Type= 6, Freq= 0, CH_0, rank 1
2975 11:12:59.031038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2976 11:12:59.034209 ==
2977 11:12:59.034291
2978 11:12:59.034355
2979 11:12:59.034415 TX Vref Scan disable
2980 11:12:59.037930 == TX Byte 0 ==
2981 11:12:59.041038 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2982 11:12:59.047928 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2983 11:12:59.048017 == TX Byte 1 ==
2984 11:12:59.051125 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
2985 11:12:59.057351 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
2986 11:12:59.057434
2987 11:12:59.057498 [DATLAT]
2988 11:12:59.057558 Freq=1200, CH0 RK1
2989 11:12:59.057617
2990 11:12:59.061102 DATLAT Default: 0xd
2991 11:12:59.061184 0, 0xFFFF, sum = 0
2992 11:12:59.064308 1, 0xFFFF, sum = 0
2993 11:12:59.067571 2, 0xFFFF, sum = 0
2994 11:12:59.067653 3, 0xFFFF, sum = 0
2995 11:12:59.070650 4, 0xFFFF, sum = 0
2996 11:12:59.070732 5, 0xFFFF, sum = 0
2997 11:12:59.074467 6, 0xFFFF, sum = 0
2998 11:12:59.074550 7, 0xFFFF, sum = 0
2999 11:12:59.077515 8, 0xFFFF, sum = 0
3000 11:12:59.077598 9, 0xFFFF, sum = 0
3001 11:12:59.080824 10, 0xFFFF, sum = 0
3002 11:12:59.080906 11, 0xFFFF, sum = 0
3003 11:12:59.083932 12, 0x0, sum = 1
3004 11:12:59.084015 13, 0x0, sum = 2
3005 11:12:59.087719 14, 0x0, sum = 3
3006 11:12:59.087805 15, 0x0, sum = 4
3007 11:12:59.091025 best_step = 13
3008 11:12:59.091112
3009 11:12:59.091177 ==
3010 11:12:59.093955 Dram Type= 6, Freq= 0, CH_0, rank 1
3011 11:12:59.097609 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3012 11:12:59.097692 ==
3013 11:12:59.097771 RX Vref Scan: 0
3014 11:12:59.100544
3015 11:12:59.100630 RX Vref 0 -> 0, step: 1
3016 11:12:59.100696
3017 11:12:59.104052 RX Delay -37 -> 252, step: 4
3018 11:12:59.110427 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3019 11:12:59.113708 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3020 11:12:59.117340 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3021 11:12:59.120822 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3022 11:12:59.124141 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3023 11:12:59.130814 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3024 11:12:59.133672 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3025 11:12:59.137285 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3026 11:12:59.140397 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3027 11:12:59.143521 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3028 11:12:59.147585 iDelay=195, Bit 10, Center 104 (35 ~ 174) 140
3029 11:12:59.153585 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3030 11:12:59.156902 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3031 11:12:59.160485 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3032 11:12:59.163608 iDelay=195, Bit 14, Center 114 (47 ~ 182) 136
3033 11:12:59.170431 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3034 11:12:59.170514 ==
3035 11:12:59.173653 Dram Type= 6, Freq= 0, CH_0, rank 1
3036 11:12:59.176912 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3037 11:12:59.177000 ==
3038 11:12:59.177066 DQS Delay:
3039 11:12:59.179931 DQS0 = 0, DQS1 = 0
3040 11:12:59.180012 DQM Delay:
3041 11:12:59.183771 DQM0 = 111, DQM1 = 101
3042 11:12:59.183853 DQ Delay:
3043 11:12:59.186879 DQ0 =108, DQ1 =112, DQ2 =110, DQ3 =108
3044 11:12:59.189914 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =120
3045 11:12:59.193546 DQ8 =90, DQ9 =84, DQ10 =104, DQ11 =94
3046 11:12:59.196579 DQ12 =110, DQ13 =108, DQ14 =114, DQ15 =110
3047 11:12:59.196691
3048 11:12:59.196759
3049 11:12:59.206276 [DQSOSCAuto] RK1, (LSB)MR18= 0x12fa, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 403 ps
3050 11:12:59.209852 CH0 RK1: MR19=403, MR18=12FA
3051 11:12:59.213401 CH0_RK1: MR19=0x403, MR18=0x12FA, DQSOSC=403, MR23=63, INC=40, DEC=26
3052 11:12:59.216402 [RxdqsGatingPostProcess] freq 1200
3053 11:12:59.223298 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3054 11:12:59.226967 best DQS0 dly(2T, 0.5T) = (0, 11)
3055 11:12:59.229612 best DQS1 dly(2T, 0.5T) = (0, 12)
3056 11:12:59.232961 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3057 11:12:59.236438 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3058 11:12:59.239746 best DQS0 dly(2T, 0.5T) = (0, 11)
3059 11:12:59.243178 best DQS1 dly(2T, 0.5T) = (0, 12)
3060 11:12:59.246643 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3061 11:12:59.249879 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3062 11:12:59.253028 Pre-setting of DQS Precalculation
3063 11:12:59.256115 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3064 11:12:59.256197 ==
3065 11:12:59.259951 Dram Type= 6, Freq= 0, CH_1, rank 0
3066 11:12:59.263088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3067 11:12:59.263170 ==
3068 11:12:59.269446 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3069 11:12:59.276340 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3070 11:12:59.284255 [CA 0] Center 37 (7~67) winsize 61
3071 11:12:59.287474 [CA 1] Center 37 (7~68) winsize 62
3072 11:12:59.290673 [CA 2] Center 34 (5~64) winsize 60
3073 11:12:59.293806 [CA 3] Center 33 (3~64) winsize 62
3074 11:12:59.297413 [CA 4] Center 34 (4~64) winsize 61
3075 11:12:59.300470 [CA 5] Center 33 (3~63) winsize 61
3076 11:12:59.300552
3077 11:12:59.304103 [CmdBusTrainingLP45] Vref(ca) range 1: 31
3078 11:12:59.304239
3079 11:12:59.307130 [CATrainingPosCal] consider 1 rank data
3080 11:12:59.310713 u2DelayCellTimex100 = 270/100 ps
3081 11:12:59.313959 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3082 11:12:59.320460 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3083 11:12:59.323883 CA2 delay=34 (5~64),Diff = 1 PI (4 cell)
3084 11:12:59.326946 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3085 11:12:59.330580 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3086 11:12:59.333724 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3087 11:12:59.333807
3088 11:12:59.337235 CA PerBit enable=1, Macro0, CA PI delay=33
3089 11:12:59.337318
3090 11:12:59.340205 [CBTSetCACLKResult] CA Dly = 33
3091 11:12:59.340287 CS Dly: 5 (0~36)
3092 11:12:59.343655 ==
3093 11:12:59.347274 Dram Type= 6, Freq= 0, CH_1, rank 1
3094 11:12:59.350277 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3095 11:12:59.350360 ==
3096 11:12:59.353619 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3097 11:12:59.360434 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3098 11:12:59.369770 [CA 0] Center 37 (7~67) winsize 61
3099 11:12:59.372957 [CA 1] Center 37 (7~68) winsize 62
3100 11:12:59.376048 [CA 2] Center 34 (4~65) winsize 62
3101 11:12:59.379172 [CA 3] Center 33 (3~64) winsize 62
3102 11:12:59.383054 [CA 4] Center 34 (4~65) winsize 62
3103 11:12:59.386019 [CA 5] Center 32 (2~63) winsize 62
3104 11:12:59.386102
3105 11:12:59.389061 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3106 11:12:59.389145
3107 11:12:59.392851 [CATrainingPosCal] consider 2 rank data
3108 11:12:59.396113 u2DelayCellTimex100 = 270/100 ps
3109 11:12:59.399120 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3110 11:12:59.405919 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3111 11:12:59.408983 CA2 delay=34 (5~64),Diff = 1 PI (4 cell)
3112 11:12:59.412572 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3113 11:12:59.415540 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3114 11:12:59.419195 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3115 11:12:59.419302
3116 11:12:59.422756 CA PerBit enable=1, Macro0, CA PI delay=33
3117 11:12:59.422895
3118 11:12:59.425966 [CBTSetCACLKResult] CA Dly = 33
3119 11:12:59.428794 CS Dly: 6 (0~39)
3120 11:12:59.428907
3121 11:12:59.432276 ----->DramcWriteLeveling(PI) begin...
3122 11:12:59.432386 ==
3123 11:12:59.435962 Dram Type= 6, Freq= 0, CH_1, rank 0
3124 11:12:59.439478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3125 11:12:59.439584 ==
3126 11:12:59.442378 Write leveling (Byte 0): 26 => 26
3127 11:12:59.445454 Write leveling (Byte 1): 26 => 26
3128 11:12:59.448869 DramcWriteLeveling(PI) end<-----
3129 11:12:59.448967
3130 11:12:59.449075 ==
3131 11:12:59.452410 Dram Type= 6, Freq= 0, CH_1, rank 0
3132 11:12:59.455504 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3133 11:12:59.455619 ==
3134 11:12:59.459094 [Gating] SW mode calibration
3135 11:12:59.465205 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3136 11:12:59.472216 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3137 11:12:59.475459 0 15 0 | B1->B0 | 3030 2b2b | 0 0 | (0 0) (0 0)
3138 11:12:59.478538 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3139 11:12:59.485411 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3140 11:12:59.488563 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3141 11:12:59.492246 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3142 11:12:59.498566 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3143 11:12:59.501538 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3144 11:12:59.505095 0 15 28 | B1->B0 | 2d2d 2f2f | 1 0 | (1 0) (0 1)
3145 11:12:59.511972 1 0 0 | B1->B0 | 2323 2323 | 1 0 | (1 0) (1 0)
3146 11:12:59.515089 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3147 11:12:59.518007 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3148 11:12:59.524915 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3149 11:12:59.528041 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3150 11:12:59.531406 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3151 11:12:59.537958 1 0 24 | B1->B0 | 2828 2424 | 0 0 | (0 0) (0 0)
3152 11:12:59.541646 1 0 28 | B1->B0 | 3d3d 3a3a | 1 0 | (0 0) (0 0)
3153 11:12:59.544846 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 11:12:59.551475 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3155 11:12:59.554756 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 11:12:59.557770 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 11:12:59.564444 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3158 11:12:59.568200 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3159 11:12:59.571045 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 11:12:59.578075 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3161 11:12:59.581156 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3162 11:12:59.584275 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 11:12:59.591146 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 11:12:59.594295 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 11:12:59.597303 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 11:12:59.604202 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 11:12:59.607378 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 11:12:59.611020 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 11:12:59.617464 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 11:12:59.620569 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 11:12:59.623716 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 11:12:59.630516 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 11:12:59.633438 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 11:12:59.636993 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 11:12:59.643430 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 11:12:59.646974 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3177 11:12:59.650106 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3178 11:12:59.653640 Total UI for P1: 0, mck2ui 16
3179 11:12:59.656555 best dqsien dly found for B1: ( 1, 3, 28)
3180 11:12:59.663193 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3181 11:12:59.663276 Total UI for P1: 0, mck2ui 16
3182 11:12:59.669685 best dqsien dly found for B0: ( 1, 3, 30)
3183 11:12:59.673563 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3184 11:12:59.676473 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3185 11:12:59.676548
3186 11:12:59.679709 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3187 11:12:59.683489 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3188 11:12:59.686646 [Gating] SW calibration Done
3189 11:12:59.686753 ==
3190 11:12:59.689872 Dram Type= 6, Freq= 0, CH_1, rank 0
3191 11:12:59.693047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3192 11:12:59.693129 ==
3193 11:12:59.696270 RX Vref Scan: 0
3194 11:12:59.696351
3195 11:12:59.696415 RX Vref 0 -> 0, step: 1
3196 11:12:59.696474
3197 11:12:59.700226 RX Delay -40 -> 252, step: 8
3198 11:12:59.706211 iDelay=208, Bit 0, Center 119 (40 ~ 199) 160
3199 11:12:59.709594 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3200 11:12:59.712931 iDelay=208, Bit 2, Center 99 (24 ~ 175) 152
3201 11:12:59.716137 iDelay=208, Bit 3, Center 111 (40 ~ 183) 144
3202 11:12:59.719264 iDelay=208, Bit 4, Center 107 (32 ~ 183) 152
3203 11:12:59.726374 iDelay=208, Bit 5, Center 127 (48 ~ 207) 160
3204 11:12:59.729505 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3205 11:12:59.732961 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3206 11:12:59.735901 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3207 11:12:59.739644 iDelay=208, Bit 9, Center 95 (24 ~ 167) 144
3208 11:12:59.742797 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
3209 11:12:59.749078 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3210 11:12:59.752755 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3211 11:12:59.756202 iDelay=208, Bit 13, Center 115 (40 ~ 191) 152
3212 11:12:59.759215 iDelay=208, Bit 14, Center 111 (40 ~ 183) 144
3213 11:12:59.765625 iDelay=208, Bit 15, Center 111 (40 ~ 183) 144
3214 11:12:59.765797 ==
3215 11:12:59.769303 Dram Type= 6, Freq= 0, CH_1, rank 0
3216 11:12:59.772819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3217 11:12:59.773027 ==
3218 11:12:59.773191 DQS Delay:
3219 11:12:59.775756 DQS0 = 0, DQS1 = 0
3220 11:12:59.776006 DQM Delay:
3221 11:12:59.779575 DQM0 = 114, DQM1 = 106
3222 11:12:59.779964 DQ Delay:
3223 11:12:59.782674 DQ0 =119, DQ1 =111, DQ2 =99, DQ3 =111
3224 11:12:59.785956 DQ4 =107, DQ5 =127, DQ6 =123, DQ7 =115
3225 11:12:59.789173 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
3226 11:12:59.792520 DQ12 =115, DQ13 =115, DQ14 =111, DQ15 =111
3227 11:12:59.793019
3228 11:12:59.793511
3229 11:12:59.794082 ==
3230 11:12:59.796257 Dram Type= 6, Freq= 0, CH_1, rank 0
3231 11:12:59.802470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3232 11:12:59.802997 ==
3233 11:12:59.803479
3234 11:12:59.803929
3235 11:12:59.805537 TX Vref Scan disable
3236 11:12:59.806014 == TX Byte 0 ==
3237 11:12:59.809431 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3238 11:12:59.815867 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3239 11:12:59.816351 == TX Byte 1 ==
3240 11:12:59.819181 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3241 11:12:59.825838 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3242 11:12:59.826324 ==
3243 11:12:59.829110 Dram Type= 6, Freq= 0, CH_1, rank 0
3244 11:12:59.832256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3245 11:12:59.832740 ==
3246 11:12:59.844477 TX Vref=22, minBit 9, minWin=24, winSum=404
3247 11:12:59.847314 TX Vref=24, minBit 10, minWin=24, winSum=412
3248 11:12:59.850544 TX Vref=26, minBit 9, minWin=25, winSum=417
3249 11:12:59.854153 TX Vref=28, minBit 9, minWin=25, winSum=423
3250 11:12:59.857697 TX Vref=30, minBit 9, minWin=25, winSum=422
3251 11:12:59.864049 TX Vref=32, minBit 9, minWin=25, winSum=418
3252 11:12:59.867650 [TxChooseVref] Worse bit 9, Min win 25, Win sum 423, Final Vref 28
3253 11:12:59.868139
3254 11:12:59.870959 Final TX Range 1 Vref 28
3255 11:12:59.871460
3256 11:12:59.871939 ==
3257 11:12:59.874348 Dram Type= 6, Freq= 0, CH_1, rank 0
3258 11:12:59.877330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3259 11:12:59.877669 ==
3260 11:12:59.880746
3261 11:12:59.881085
3262 11:12:59.881420 TX Vref Scan disable
3263 11:12:59.884256 == TX Byte 0 ==
3264 11:12:59.887189 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3265 11:12:59.893867 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3266 11:12:59.894208 == TX Byte 1 ==
3267 11:12:59.897102 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3268 11:12:59.903447 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3269 11:12:59.903785
3270 11:12:59.904121 [DATLAT]
3271 11:12:59.904437 Freq=1200, CH1 RK0
3272 11:12:59.904749
3273 11:12:59.907186 DATLAT Default: 0xd
3274 11:12:59.910295 0, 0xFFFF, sum = 0
3275 11:12:59.910642 1, 0xFFFF, sum = 0
3276 11:12:59.913353 2, 0xFFFF, sum = 0
3277 11:12:59.913696 3, 0xFFFF, sum = 0
3278 11:12:59.917178 4, 0xFFFF, sum = 0
3279 11:12:59.917520 5, 0xFFFF, sum = 0
3280 11:12:59.920194 6, 0xFFFF, sum = 0
3281 11:12:59.920537 7, 0xFFFF, sum = 0
3282 11:12:59.923232 8, 0xFFFF, sum = 0
3283 11:12:59.923593 9, 0xFFFF, sum = 0
3284 11:12:59.927139 10, 0xFFFF, sum = 0
3285 11:12:59.927482 11, 0xFFFF, sum = 0
3286 11:12:59.930354 12, 0x0, sum = 1
3287 11:12:59.930695 13, 0x0, sum = 2
3288 11:12:59.933314 14, 0x0, sum = 3
3289 11:12:59.933656 15, 0x0, sum = 4
3290 11:12:59.936587 best_step = 13
3291 11:12:59.936922
3292 11:12:59.937257 ==
3293 11:12:59.940199 Dram Type= 6, Freq= 0, CH_1, rank 0
3294 11:12:59.943345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3295 11:12:59.943753 ==
3296 11:12:59.944120 RX Vref Scan: 1
3297 11:12:59.946527
3298 11:12:59.946937 Set Vref Range= 32 -> 127
3299 11:12:59.947314
3300 11:12:59.949563 RX Vref 32 -> 127, step: 1
3301 11:12:59.949973
3302 11:12:59.953210 RX Delay -21 -> 252, step: 4
3303 11:12:59.953590
3304 11:12:59.956684 Set Vref, RX VrefLevel [Byte0]: 32
3305 11:12:59.959866 [Byte1]: 32
3306 11:12:59.960102
3307 11:12:59.962743 Set Vref, RX VrefLevel [Byte0]: 33
3308 11:12:59.966241 [Byte1]: 33
3309 11:12:59.970170
3310 11:12:59.970249 Set Vref, RX VrefLevel [Byte0]: 34
3311 11:12:59.973657 [Byte1]: 34
3312 11:12:59.977752
3313 11:12:59.977832 Set Vref, RX VrefLevel [Byte0]: 35
3314 11:12:59.981268 [Byte1]: 35
3315 11:12:59.985882
3316 11:12:59.985962 Set Vref, RX VrefLevel [Byte0]: 36
3317 11:12:59.989453 [Byte1]: 36
3318 11:12:59.994039
3319 11:12:59.994120 Set Vref, RX VrefLevel [Byte0]: 37
3320 11:12:59.996951 [Byte1]: 37
3321 11:13:00.001929
3322 11:13:00.002008 Set Vref, RX VrefLevel [Byte0]: 38
3323 11:13:00.005057 [Byte1]: 38
3324 11:13:00.009513
3325 11:13:00.009593 Set Vref, RX VrefLevel [Byte0]: 39
3326 11:13:00.013180 [Byte1]: 39
3327 11:13:00.017631
3328 11:13:00.017737 Set Vref, RX VrefLevel [Byte0]: 40
3329 11:13:00.020764 [Byte1]: 40
3330 11:13:00.025633
3331 11:13:00.025724 Set Vref, RX VrefLevel [Byte0]: 41
3332 11:13:00.028659 [Byte1]: 41
3333 11:13:00.033706
3334 11:13:00.033780 Set Vref, RX VrefLevel [Byte0]: 42
3335 11:13:00.036874 [Byte1]: 42
3336 11:13:00.041727
3337 11:13:00.041809 Set Vref, RX VrefLevel [Byte0]: 43
3338 11:13:00.044911 [Byte1]: 43
3339 11:13:00.049159
3340 11:13:00.049239 Set Vref, RX VrefLevel [Byte0]: 44
3341 11:13:00.052379 [Byte1]: 44
3342 11:13:00.057383
3343 11:13:00.057463 Set Vref, RX VrefLevel [Byte0]: 45
3344 11:13:00.060403 [Byte1]: 45
3345 11:13:00.065002
3346 11:13:00.065083 Set Vref, RX VrefLevel [Byte0]: 46
3347 11:13:00.068423 [Byte1]: 46
3348 11:13:00.073105
3349 11:13:00.073186 Set Vref, RX VrefLevel [Byte0]: 47
3350 11:13:00.076589 [Byte1]: 47
3351 11:13:00.081145
3352 11:13:00.081226 Set Vref, RX VrefLevel [Byte0]: 48
3353 11:13:00.084796 [Byte1]: 48
3354 11:13:00.088872
3355 11:13:00.088985 Set Vref, RX VrefLevel [Byte0]: 49
3356 11:13:00.092137 [Byte1]: 49
3357 11:13:00.096616
3358 11:13:00.096697 Set Vref, RX VrefLevel [Byte0]: 50
3359 11:13:00.100110 [Byte1]: 50
3360 11:13:00.104639
3361 11:13:00.104721 Set Vref, RX VrefLevel [Byte0]: 51
3362 11:13:00.108562 [Byte1]: 51
3363 11:13:00.112710
3364 11:13:00.112791 Set Vref, RX VrefLevel [Byte0]: 52
3365 11:13:00.115847 [Byte1]: 52
3366 11:13:00.120736
3367 11:13:00.120816 Set Vref, RX VrefLevel [Byte0]: 53
3368 11:13:00.123886 [Byte1]: 53
3369 11:13:00.128787
3370 11:13:00.128870 Set Vref, RX VrefLevel [Byte0]: 54
3371 11:13:00.131889 [Byte1]: 54
3372 11:13:00.136310
3373 11:13:00.136393 Set Vref, RX VrefLevel [Byte0]: 55
3374 11:13:00.140147 [Byte1]: 55
3375 11:13:00.144566
3376 11:13:00.144649 Set Vref, RX VrefLevel [Byte0]: 56
3377 11:13:00.147786 [Byte1]: 56
3378 11:13:00.152161
3379 11:13:00.152244 Set Vref, RX VrefLevel [Byte0]: 57
3380 11:13:00.156392 [Byte1]: 57
3381 11:13:00.160711
3382 11:13:00.161184 Set Vref, RX VrefLevel [Byte0]: 58
3383 11:13:00.163788 [Byte1]: 58
3384 11:13:00.168588
3385 11:13:00.169118 Set Vref, RX VrefLevel [Byte0]: 59
3386 11:13:00.172179 [Byte1]: 59
3387 11:13:00.176481
3388 11:13:00.177078 Set Vref, RX VrefLevel [Byte0]: 60
3389 11:13:00.180024 [Byte1]: 60
3390 11:13:00.184693
3391 11:13:00.185206 Set Vref, RX VrefLevel [Byte0]: 61
3392 11:13:00.187377 [Byte1]: 61
3393 11:13:00.192027
3394 11:13:00.195382 Set Vref, RX VrefLevel [Byte0]: 62
3395 11:13:00.198958 [Byte1]: 62
3396 11:13:00.199730
3397 11:13:00.201845 Set Vref, RX VrefLevel [Byte0]: 63
3398 11:13:00.205251 [Byte1]: 63
3399 11:13:00.205967
3400 11:13:00.208762 Final RX Vref Byte 0 = 57 to rank0
3401 11:13:00.212285 Final RX Vref Byte 1 = 53 to rank0
3402 11:13:00.215394 Final RX Vref Byte 0 = 57 to rank1
3403 11:13:00.218981 Final RX Vref Byte 1 = 53 to rank1==
3404 11:13:00.222019 Dram Type= 6, Freq= 0, CH_1, rank 0
3405 11:13:00.225235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3406 11:13:00.225709 ==
3407 11:13:00.229150 DQS Delay:
3408 11:13:00.229629 DQS0 = 0, DQS1 = 0
3409 11:13:00.232288 DQM Delay:
3410 11:13:00.232782 DQM0 = 114, DQM1 = 106
3411 11:13:00.233155 DQ Delay:
3412 11:13:00.238902 DQ0 =118, DQ1 =108, DQ2 =106, DQ3 =112
3413 11:13:00.242041 DQ4 =112, DQ5 =124, DQ6 =124, DQ7 =112
3414 11:13:00.245200 DQ8 =92, DQ9 =98, DQ10 =106, DQ11 =102
3415 11:13:00.248341 DQ12 =114, DQ13 =112, DQ14 =116, DQ15 =112
3416 11:13:00.248868
3417 11:13:00.249371
3418 11:13:00.255288 [DQSOSCAuto] RK0, (LSB)MR18= 0xebf2, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 418 ps
3419 11:13:00.258353 CH1 RK0: MR19=303, MR18=EBF2
3420 11:13:00.265363 CH1_RK0: MR19=0x303, MR18=0xEBF2, DQSOSC=415, MR23=63, INC=38, DEC=25
3421 11:13:00.265996
3422 11:13:00.268472 ----->DramcWriteLeveling(PI) begin...
3423 11:13:00.269127 ==
3424 11:13:00.271536 Dram Type= 6, Freq= 0, CH_1, rank 1
3425 11:13:00.275338 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3426 11:13:00.275810 ==
3427 11:13:00.278497 Write leveling (Byte 0): 24 => 24
3428 11:13:00.281456 Write leveling (Byte 1): 26 => 26
3429 11:13:00.285075 DramcWriteLeveling(PI) end<-----
3430 11:13:00.285647
3431 11:13:00.286106 ==
3432 11:13:00.288583 Dram Type= 6, Freq= 0, CH_1, rank 1
3433 11:13:00.295124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3434 11:13:00.295730 ==
3435 11:13:00.296190 [Gating] SW mode calibration
3436 11:13:00.304977 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3437 11:13:00.308398 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3438 11:13:00.311485 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3439 11:13:00.318091 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3440 11:13:00.321071 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3441 11:13:00.324637 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3442 11:13:00.331502 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3443 11:13:00.334453 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3444 11:13:00.338115 0 15 24 | B1->B0 | 3232 2727 | 0 0 | (0 0) (0 0)
3445 11:13:00.344458 0 15 28 | B1->B0 | 2727 2323 | 0 0 | (1 1) (0 0)
3446 11:13:00.347628 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3447 11:13:00.351333 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3448 11:13:00.357554 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3449 11:13:00.360641 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3450 11:13:00.363823 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3451 11:13:00.370688 1 0 20 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
3452 11:13:00.373774 1 0 24 | B1->B0 | 2c2c 4646 | 0 0 | (0 0) (0 0)
3453 11:13:00.377374 1 0 28 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
3454 11:13:00.383812 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3455 11:13:00.386886 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3456 11:13:00.390387 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3457 11:13:00.396989 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3458 11:13:00.400603 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3459 11:13:00.403479 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3460 11:13:00.410548 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3461 11:13:00.413675 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3462 11:13:00.416719 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 11:13:00.423537 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 11:13:00.426521 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 11:13:00.430184 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 11:13:00.436628 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 11:13:00.439759 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 11:13:00.443480 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 11:13:00.449775 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 11:13:00.452896 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 11:13:00.456873 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 11:13:00.462933 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 11:13:00.466071 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 11:13:00.469212 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 11:13:00.476135 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 11:13:00.479299 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3477 11:13:00.483087 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3478 11:13:00.485993 Total UI for P1: 0, mck2ui 16
3479 11:13:00.489091 best dqsien dly found for B0: ( 1, 3, 24)
3480 11:13:00.496054 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3481 11:13:00.496178 Total UI for P1: 0, mck2ui 16
3482 11:13:00.502514 best dqsien dly found for B1: ( 1, 3, 26)
3483 11:13:00.506076 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3484 11:13:00.509057 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3485 11:13:00.509159
3486 11:13:00.512532 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3487 11:13:00.516036 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3488 11:13:00.519113 [Gating] SW calibration Done
3489 11:13:00.519213 ==
3490 11:13:00.522190 Dram Type= 6, Freq= 0, CH_1, rank 1
3491 11:13:00.525827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3492 11:13:00.525911 ==
3493 11:13:00.528748 RX Vref Scan: 0
3494 11:13:00.528831
3495 11:13:00.528896 RX Vref 0 -> 0, step: 1
3496 11:13:00.532035
3497 11:13:00.532118 RX Delay -40 -> 252, step: 8
3498 11:13:00.538678 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3499 11:13:00.542167 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3500 11:13:00.545188 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3501 11:13:00.548671 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3502 11:13:00.551755 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3503 11:13:00.558753 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3504 11:13:00.561716 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3505 11:13:00.564921 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3506 11:13:00.568093 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3507 11:13:00.571826 iDelay=200, Bit 9, Center 99 (24 ~ 175) 152
3508 11:13:00.578226 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3509 11:13:00.581460 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3510 11:13:00.585013 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
3511 11:13:00.588064 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3512 11:13:00.591269 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3513 11:13:00.598101 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3514 11:13:00.598185 ==
3515 11:13:00.601173 Dram Type= 6, Freq= 0, CH_1, rank 1
3516 11:13:00.604925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3517 11:13:00.605008 ==
3518 11:13:00.605074 DQS Delay:
3519 11:13:00.607948 DQS0 = 0, DQS1 = 0
3520 11:13:00.608031 DQM Delay:
3521 11:13:00.610951 DQM0 = 110, DQM1 = 108
3522 11:13:00.611033 DQ Delay:
3523 11:13:00.614446 DQ0 =115, DQ1 =107, DQ2 =99, DQ3 =107
3524 11:13:00.617862 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =111
3525 11:13:00.621414 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3526 11:13:00.624404 DQ12 =115, DQ13 =119, DQ14 =111, DQ15 =111
3527 11:13:00.627598
3528 11:13:00.627681
3529 11:13:00.627746 ==
3530 11:13:00.630735 Dram Type= 6, Freq= 0, CH_1, rank 1
3531 11:13:00.634193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3532 11:13:00.634277 ==
3533 11:13:00.634343
3534 11:13:00.634404
3535 11:13:00.637858 TX Vref Scan disable
3536 11:13:00.637942 == TX Byte 0 ==
3537 11:13:00.644180 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3538 11:13:00.647245 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3539 11:13:00.647328 == TX Byte 1 ==
3540 11:13:00.653807 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3541 11:13:00.657272 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3542 11:13:00.657355 ==
3543 11:13:00.660398 Dram Type= 6, Freq= 0, CH_1, rank 1
3544 11:13:00.663872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3545 11:13:00.663956 ==
3546 11:13:00.676504 TX Vref=22, minBit 11, minWin=25, winSum=419
3547 11:13:00.679648 TX Vref=24, minBit 11, minWin=25, winSum=421
3548 11:13:00.683428 TX Vref=26, minBit 1, minWin=26, winSum=431
3549 11:13:00.686536 TX Vref=28, minBit 9, minWin=26, winSum=432
3550 11:13:00.689543 TX Vref=30, minBit 11, minWin=26, winSum=431
3551 11:13:00.696487 TX Vref=32, minBit 9, minWin=25, winSum=427
3552 11:13:00.699560 [TxChooseVref] Worse bit 9, Min win 26, Win sum 432, Final Vref 28
3553 11:13:00.702654
3554 11:13:00.702776 Final TX Range 1 Vref 28
3555 11:13:00.702915
3556 11:13:00.702997 ==
3557 11:13:00.706360 Dram Type= 6, Freq= 0, CH_1, rank 1
3558 11:13:00.712885 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3559 11:13:00.712991 ==
3560 11:13:00.713070
3561 11:13:00.713147
3562 11:13:00.713207 TX Vref Scan disable
3563 11:13:00.716472 == TX Byte 0 ==
3564 11:13:00.719564 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3565 11:13:00.726406 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3566 11:13:00.726514 == TX Byte 1 ==
3567 11:13:00.729916 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3568 11:13:00.736157 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3569 11:13:00.736265
3570 11:13:00.736364 [DATLAT]
3571 11:13:00.736456 Freq=1200, CH1 RK1
3572 11:13:00.736551
3573 11:13:00.739812 DATLAT Default: 0xd
3574 11:13:00.742906 0, 0xFFFF, sum = 0
3575 11:13:00.743017 1, 0xFFFF, sum = 0
3576 11:13:00.745887 2, 0xFFFF, sum = 0
3577 11:13:00.745989 3, 0xFFFF, sum = 0
3578 11:13:00.749362 4, 0xFFFF, sum = 0
3579 11:13:00.749438 5, 0xFFFF, sum = 0
3580 11:13:00.752805 6, 0xFFFF, sum = 0
3581 11:13:00.752907 7, 0xFFFF, sum = 0
3582 11:13:00.755876 8, 0xFFFF, sum = 0
3583 11:13:00.755956 9, 0xFFFF, sum = 0
3584 11:13:00.759430 10, 0xFFFF, sum = 0
3585 11:13:00.759514 11, 0xFFFF, sum = 0
3586 11:13:00.762478 12, 0x0, sum = 1
3587 11:13:00.762552 13, 0x0, sum = 2
3588 11:13:00.765860 14, 0x0, sum = 3
3589 11:13:00.765944 15, 0x0, sum = 4
3590 11:13:00.769323 best_step = 13
3591 11:13:00.769406
3592 11:13:00.769471 ==
3593 11:13:00.772398 Dram Type= 6, Freq= 0, CH_1, rank 1
3594 11:13:00.776268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3595 11:13:00.776352 ==
3596 11:13:00.779455 RX Vref Scan: 0
3597 11:13:00.779538
3598 11:13:00.779603 RX Vref 0 -> 0, step: 1
3599 11:13:00.779665
3600 11:13:00.782483 RX Delay -21 -> 252, step: 4
3601 11:13:00.789513 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3602 11:13:00.792627 iDelay=195, Bit 1, Center 108 (39 ~ 178) 140
3603 11:13:00.795583 iDelay=195, Bit 2, Center 102 (35 ~ 170) 136
3604 11:13:00.799451 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3605 11:13:00.802551 iDelay=195, Bit 4, Center 108 (39 ~ 178) 140
3606 11:13:00.809194 iDelay=195, Bit 5, Center 118 (43 ~ 194) 152
3607 11:13:00.812391 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3608 11:13:00.815521 iDelay=195, Bit 7, Center 108 (39 ~ 178) 140
3609 11:13:00.819253 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3610 11:13:00.822169 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3611 11:13:00.828701 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3612 11:13:00.832208 iDelay=195, Bit 11, Center 102 (35 ~ 170) 136
3613 11:13:00.835159 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3614 11:13:00.838355 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3615 11:13:00.844946 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3616 11:13:00.848758 iDelay=195, Bit 15, Center 120 (55 ~ 186) 132
3617 11:13:00.848842 ==
3618 11:13:00.851923 Dram Type= 6, Freq= 0, CH_1, rank 1
3619 11:13:00.854994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3620 11:13:00.855103 ==
3621 11:13:00.858331 DQS Delay:
3622 11:13:00.858413 DQS0 = 0, DQS1 = 0
3623 11:13:00.858479 DQM Delay:
3624 11:13:00.861744 DQM0 = 111, DQM1 = 110
3625 11:13:00.861827 DQ Delay:
3626 11:13:00.864938 DQ0 =114, DQ1 =108, DQ2 =102, DQ3 =108
3627 11:13:00.868338 DQ4 =108, DQ5 =118, DQ6 =122, DQ7 =108
3628 11:13:00.871425 DQ8 =98, DQ9 =100, DQ10 =110, DQ11 =102
3629 11:13:00.878104 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =120
3630 11:13:00.878186
3631 11:13:00.878251
3632 11:13:00.884501 [DQSOSCAuto] RK1, (LSB)MR18= 0xf707, (MSB)MR19= 0x304, tDQSOscB0 = 407 ps tDQSOscB1 = 413 ps
3633 11:13:00.888008 CH1 RK1: MR19=304, MR18=F707
3634 11:13:00.894665 CH1_RK1: MR19=0x304, MR18=0xF707, DQSOSC=407, MR23=63, INC=39, DEC=26
3635 11:13:00.897641 [RxdqsGatingPostProcess] freq 1200
3636 11:13:00.900859 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3637 11:13:00.904592 best DQS0 dly(2T, 0.5T) = (0, 11)
3638 11:13:00.907654 best DQS1 dly(2T, 0.5T) = (0, 11)
3639 11:13:00.911203 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3640 11:13:00.914260 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3641 11:13:00.917390 best DQS0 dly(2T, 0.5T) = (0, 11)
3642 11:13:00.921153 best DQS1 dly(2T, 0.5T) = (0, 11)
3643 11:13:00.924225 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3644 11:13:00.927264 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3645 11:13:00.930755 Pre-setting of DQS Precalculation
3646 11:13:00.934341 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3647 11:13:00.943905 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3648 11:13:00.950725 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3649 11:13:00.950809
3650 11:13:00.950881
3651 11:13:00.953869 [Calibration Summary] 2400 Mbps
3652 11:13:00.953952 CH 0, Rank 0
3653 11:13:00.957007 SW Impedance : PASS
3654 11:13:00.960628 DUTY Scan : NO K
3655 11:13:00.960711 ZQ Calibration : PASS
3656 11:13:00.963765 Jitter Meter : NO K
3657 11:13:00.963848 CBT Training : PASS
3658 11:13:00.967245 Write leveling : PASS
3659 11:13:00.970244 RX DQS gating : PASS
3660 11:13:00.970327 RX DQ/DQS(RDDQC) : PASS
3661 11:13:00.973742 TX DQ/DQS : PASS
3662 11:13:00.977303 RX DATLAT : PASS
3663 11:13:00.977422 RX DQ/DQS(Engine): PASS
3664 11:13:00.980260 TX OE : NO K
3665 11:13:00.980344 All Pass.
3666 11:13:00.980408
3667 11:13:00.983821 CH 0, Rank 1
3668 11:13:00.983904 SW Impedance : PASS
3669 11:13:00.986772 DUTY Scan : NO K
3670 11:13:00.989939 ZQ Calibration : PASS
3671 11:13:00.990022 Jitter Meter : NO K
3672 11:13:00.993735 CBT Training : PASS
3673 11:13:00.996896 Write leveling : PASS
3674 11:13:00.996979 RX DQS gating : PASS
3675 11:13:00.999991 RX DQ/DQS(RDDQC) : PASS
3676 11:13:01.003656 TX DQ/DQS : PASS
3677 11:13:01.003740 RX DATLAT : PASS
3678 11:13:01.007021 RX DQ/DQS(Engine): PASS
3679 11:13:01.009940 TX OE : NO K
3680 11:13:01.010023 All Pass.
3681 11:13:01.010089
3682 11:13:01.010149 CH 1, Rank 0
3683 11:13:01.012990 SW Impedance : PASS
3684 11:13:01.016583 DUTY Scan : NO K
3685 11:13:01.016666 ZQ Calibration : PASS
3686 11:13:01.019737 Jitter Meter : NO K
3687 11:13:01.022943 CBT Training : PASS
3688 11:13:01.023026 Write leveling : PASS
3689 11:13:01.026632 RX DQS gating : PASS
3690 11:13:01.029767 RX DQ/DQS(RDDQC) : PASS
3691 11:13:01.029850 TX DQ/DQS : PASS
3692 11:13:01.032758 RX DATLAT : PASS
3693 11:13:01.036209 RX DQ/DQS(Engine): PASS
3694 11:13:01.036292 TX OE : NO K
3695 11:13:01.036358 All Pass.
3696 11:13:01.036419
3697 11:13:01.039634 CH 1, Rank 1
3698 11:13:01.042660 SW Impedance : PASS
3699 11:13:01.042742 DUTY Scan : NO K
3700 11:13:01.046098 ZQ Calibration : PASS
3701 11:13:01.046181 Jitter Meter : NO K
3702 11:13:01.049552 CBT Training : PASS
3703 11:13:01.053066 Write leveling : PASS
3704 11:13:01.053150 RX DQS gating : PASS
3705 11:13:01.056229 RX DQ/DQS(RDDQC) : PASS
3706 11:13:01.059479 TX DQ/DQS : PASS
3707 11:13:01.059562 RX DATLAT : PASS
3708 11:13:01.062523 RX DQ/DQS(Engine): PASS
3709 11:13:01.066093 TX OE : NO K
3710 11:13:01.066176 All Pass.
3711 11:13:01.066241
3712 11:13:01.069206 DramC Write-DBI off
3713 11:13:01.069290 PER_BANK_REFRESH: Hybrid Mode
3714 11:13:01.072844 TX_TRACKING: ON
3715 11:13:01.082390 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3716 11:13:01.085772 [FAST_K] Save calibration result to emmc
3717 11:13:01.089138 dramc_set_vcore_voltage set vcore to 650000
3718 11:13:01.089250 Read voltage for 600, 5
3719 11:13:01.092055 Vio18 = 0
3720 11:13:01.092138 Vcore = 650000
3721 11:13:01.092204 Vdram = 0
3722 11:13:01.095886 Vddq = 0
3723 11:13:01.095968 Vmddr = 0
3724 11:13:01.102239 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3725 11:13:01.105927 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3726 11:13:01.109014 MEM_TYPE=3, freq_sel=19
3727 11:13:01.112164 sv_algorithm_assistance_LP4_1600
3728 11:13:01.115316 ============ PULL DRAM RESETB DOWN ============
3729 11:13:01.119075 ========== PULL DRAM RESETB DOWN end =========
3730 11:13:01.125042 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3731 11:13:01.128843 ===================================
3732 11:13:01.128964 LPDDR4 DRAM CONFIGURATION
3733 11:13:01.132078 ===================================
3734 11:13:01.134986 EX_ROW_EN[0] = 0x0
3735 11:13:01.138292 EX_ROW_EN[1] = 0x0
3736 11:13:01.138409 LP4Y_EN = 0x0
3737 11:13:01.141929 WORK_FSP = 0x0
3738 11:13:01.142027 WL = 0x2
3739 11:13:01.144788 RL = 0x2
3740 11:13:01.144907 BL = 0x2
3741 11:13:01.148198 RPST = 0x0
3742 11:13:01.148345 RD_PRE = 0x0
3743 11:13:01.151790 WR_PRE = 0x1
3744 11:13:01.151902 WR_PST = 0x0
3745 11:13:01.154724 DBI_WR = 0x0
3746 11:13:01.154867 DBI_RD = 0x0
3747 11:13:01.158154 OTF = 0x1
3748 11:13:01.161548 ===================================
3749 11:13:01.164785 ===================================
3750 11:13:01.164886 ANA top config
3751 11:13:01.168418 ===================================
3752 11:13:01.171540 DLL_ASYNC_EN = 0
3753 11:13:01.174811 ALL_SLAVE_EN = 1
3754 11:13:01.177841 NEW_RANK_MODE = 1
3755 11:13:01.177943 DLL_IDLE_MODE = 1
3756 11:13:01.181669 LP45_APHY_COMB_EN = 1
3757 11:13:01.185144 TX_ODT_DIS = 1
3758 11:13:01.187929 NEW_8X_MODE = 1
3759 11:13:01.191668 ===================================
3760 11:13:01.194602 ===================================
3761 11:13:01.197734 data_rate = 1200
3762 11:13:01.197817 CKR = 1
3763 11:13:01.201694 DQ_P2S_RATIO = 8
3764 11:13:01.204792 ===================================
3765 11:13:01.208017 CA_P2S_RATIO = 8
3766 11:13:01.211521 DQ_CA_OPEN = 0
3767 11:13:01.214779 DQ_SEMI_OPEN = 0
3768 11:13:01.217873 CA_SEMI_OPEN = 0
3769 11:13:01.218344 CA_FULL_RATE = 0
3770 11:13:01.221692 DQ_CKDIV4_EN = 1
3771 11:13:01.224480 CA_CKDIV4_EN = 1
3772 11:13:01.228283 CA_PREDIV_EN = 0
3773 11:13:01.231463 PH8_DLY = 0
3774 11:13:01.234656 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3775 11:13:01.235174 DQ_AAMCK_DIV = 4
3776 11:13:01.237842 CA_AAMCK_DIV = 4
3777 11:13:01.240988 CA_ADMCK_DIV = 4
3778 11:13:01.244819 DQ_TRACK_CA_EN = 0
3779 11:13:01.247788 CA_PICK = 600
3780 11:13:01.250779 CA_MCKIO = 600
3781 11:13:01.254149 MCKIO_SEMI = 0
3782 11:13:01.257398 PLL_FREQ = 2288
3783 11:13:01.257941 DQ_UI_PI_RATIO = 32
3784 11:13:01.260489 CA_UI_PI_RATIO = 0
3785 11:13:01.264087 ===================================
3786 11:13:01.267355 ===================================
3787 11:13:01.270372 memory_type:LPDDR4
3788 11:13:01.273873 GP_NUM : 10
3789 11:13:01.274336 SRAM_EN : 1
3790 11:13:01.277068 MD32_EN : 0
3791 11:13:01.280241 ===================================
3792 11:13:01.284037 [ANA_INIT] >>>>>>>>>>>>>>
3793 11:13:01.284430 <<<<<< [CONFIGURE PHASE]: ANA_TX
3794 11:13:01.287060 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3795 11:13:01.290632 ===================================
3796 11:13:01.293421 data_rate = 1200,PCW = 0X5800
3797 11:13:01.297055 ===================================
3798 11:13:01.300471 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3799 11:13:01.306783 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3800 11:13:01.313081 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3801 11:13:01.316641 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3802 11:13:01.319830 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3803 11:13:01.323524 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3804 11:13:01.326597 [ANA_INIT] flow start
3805 11:13:01.326810 [ANA_INIT] PLL >>>>>>>>
3806 11:13:01.329697 [ANA_INIT] PLL <<<<<<<<
3807 11:13:01.333413 [ANA_INIT] MIDPI >>>>>>>>
3808 11:13:01.336639 [ANA_INIT] MIDPI <<<<<<<<
3809 11:13:01.336761 [ANA_INIT] DLL >>>>>>>>
3810 11:13:01.339556 [ANA_INIT] flow end
3811 11:13:01.342697 ============ LP4 DIFF to SE enter ============
3812 11:13:01.345927 ============ LP4 DIFF to SE exit ============
3813 11:13:01.349832 [ANA_INIT] <<<<<<<<<<<<<
3814 11:13:01.353010 [Flow] Enable top DCM control >>>>>
3815 11:13:01.356061 [Flow] Enable top DCM control <<<<<
3816 11:13:01.359116 Enable DLL master slave shuffle
3817 11:13:01.366168 ==============================================================
3818 11:13:01.366262 Gating Mode config
3819 11:13:01.372748 ==============================================================
3820 11:13:01.372842 Config description:
3821 11:13:01.382590 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3822 11:13:01.388892 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3823 11:13:01.395741 SELPH_MODE 0: By rank 1: By Phase
3824 11:13:01.398753 ==============================================================
3825 11:13:01.402197 GAT_TRACK_EN = 1
3826 11:13:01.405738 RX_GATING_MODE = 2
3827 11:13:01.408819 RX_GATING_TRACK_MODE = 2
3828 11:13:01.412466 SELPH_MODE = 1
3829 11:13:01.415503 PICG_EARLY_EN = 1
3830 11:13:01.418497 VALID_LAT_VALUE = 1
3831 11:13:01.425227 ==============================================================
3832 11:13:01.428495 Enter into Gating configuration >>>>
3833 11:13:01.431576 Exit from Gating configuration <<<<
3834 11:13:01.435365 Enter into DVFS_PRE_config >>>>>
3835 11:13:01.444834 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3836 11:13:01.447979 Exit from DVFS_PRE_config <<<<<
3837 11:13:01.451101 Enter into PICG configuration >>>>
3838 11:13:01.454962 Exit from PICG configuration <<<<
3839 11:13:01.458090 [RX_INPUT] configuration >>>>>
3840 11:13:01.461069 [RX_INPUT] configuration <<<<<
3841 11:13:01.464850 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3842 11:13:01.471423 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3843 11:13:01.477871 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3844 11:13:01.484202 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3845 11:13:01.487716 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3846 11:13:01.494261 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3847 11:13:01.497631 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3848 11:13:01.504341 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3849 11:13:01.507284 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3850 11:13:01.510753 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3851 11:13:01.514210 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3852 11:13:01.520948 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3853 11:13:01.523983 ===================================
3854 11:13:01.527303 LPDDR4 DRAM CONFIGURATION
3855 11:13:01.530224 ===================================
3856 11:13:01.530318 EX_ROW_EN[0] = 0x0
3857 11:13:01.533975 EX_ROW_EN[1] = 0x0
3858 11:13:01.534060 LP4Y_EN = 0x0
3859 11:13:01.537027 WORK_FSP = 0x0
3860 11:13:01.537110 WL = 0x2
3861 11:13:01.540759 RL = 0x2
3862 11:13:01.540866 BL = 0x2
3863 11:13:01.543916 RPST = 0x0
3864 11:13:01.543999 RD_PRE = 0x0
3865 11:13:01.547138 WR_PRE = 0x1
3866 11:13:01.547237 WR_PST = 0x0
3867 11:13:01.550209 DBI_WR = 0x0
3868 11:13:01.553479 DBI_RD = 0x0
3869 11:13:01.553553 OTF = 0x1
3870 11:13:01.557157 ===================================
3871 11:13:01.560281 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3872 11:13:01.563421 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3873 11:13:01.570171 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3874 11:13:01.573281 ===================================
3875 11:13:01.576916 LPDDR4 DRAM CONFIGURATION
3876 11:13:01.580187 ===================================
3877 11:13:01.580264 EX_ROW_EN[0] = 0x10
3878 11:13:01.583067 EX_ROW_EN[1] = 0x0
3879 11:13:01.583144 LP4Y_EN = 0x0
3880 11:13:01.586709 WORK_FSP = 0x0
3881 11:13:01.586797 WL = 0x2
3882 11:13:01.589665 RL = 0x2
3883 11:13:01.589761 BL = 0x2
3884 11:13:01.593062 RPST = 0x0
3885 11:13:01.593165 RD_PRE = 0x0
3886 11:13:01.596545 WR_PRE = 0x1
3887 11:13:01.596631 WR_PST = 0x0
3888 11:13:01.599913 DBI_WR = 0x0
3889 11:13:01.603172 DBI_RD = 0x0
3890 11:13:01.603278 OTF = 0x1
3891 11:13:01.606455 ===================================
3892 11:13:01.613140 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3893 11:13:01.616236 nWR fixed to 30
3894 11:13:01.619793 [ModeRegInit_LP4] CH0 RK0
3895 11:13:01.619909 [ModeRegInit_LP4] CH0 RK1
3896 11:13:01.623262 [ModeRegInit_LP4] CH1 RK0
3897 11:13:01.626312 [ModeRegInit_LP4] CH1 RK1
3898 11:13:01.626453 match AC timing 17
3899 11:13:01.633026 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3900 11:13:01.636293 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3901 11:13:01.639923 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3902 11:13:01.646055 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3903 11:13:01.649982 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3904 11:13:01.650194 ==
3905 11:13:01.652979 Dram Type= 6, Freq= 0, CH_0, rank 0
3906 11:13:01.656082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3907 11:13:01.656329 ==
3908 11:13:01.662510 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3909 11:13:01.669541 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3910 11:13:01.673082 [CA 0] Center 37 (7~67) winsize 61
3911 11:13:01.676248 [CA 1] Center 37 (7~67) winsize 61
3912 11:13:01.679298 [CA 2] Center 35 (5~65) winsize 61
3913 11:13:01.682321 [CA 3] Center 35 (5~65) winsize 61
3914 11:13:01.685655 [CA 4] Center 34 (4~65) winsize 62
3915 11:13:01.689351 [CA 5] Center 34 (4~64) winsize 61
3916 11:13:01.689464
3917 11:13:01.692232 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3918 11:13:01.692343
3919 11:13:01.695714 [CATrainingPosCal] consider 1 rank data
3920 11:13:01.699192 u2DelayCellTimex100 = 270/100 ps
3921 11:13:01.702143 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3922 11:13:01.705597 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3923 11:13:01.708571 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3924 11:13:01.715417 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3925 11:13:01.718489 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3926 11:13:01.722350 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3927 11:13:01.722431
3928 11:13:01.725391 CA PerBit enable=1, Macro0, CA PI delay=34
3929 11:13:01.725476
3930 11:13:01.728769 [CBTSetCACLKResult] CA Dly = 34
3931 11:13:01.728851 CS Dly: 5 (0~36)
3932 11:13:01.728916 ==
3933 11:13:01.732236 Dram Type= 6, Freq= 0, CH_0, rank 1
3934 11:13:01.738819 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3935 11:13:01.738920 ==
3936 11:13:01.741599 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3937 11:13:01.748662 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3938 11:13:01.751818 [CA 0] Center 37 (7~67) winsize 61
3939 11:13:01.754958 [CA 1] Center 37 (7~67) winsize 61
3940 11:13:01.758697 [CA 2] Center 35 (5~65) winsize 61
3941 11:13:01.761801 [CA 3] Center 35 (5~65) winsize 61
3942 11:13:01.765011 [CA 4] Center 34 (4~65) winsize 62
3943 11:13:01.768177 [CA 5] Center 34 (4~64) winsize 61
3944 11:13:01.768267
3945 11:13:01.771369 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3946 11:13:01.771478
3947 11:13:01.774914 [CATrainingPosCal] consider 2 rank data
3948 11:13:01.777941 u2DelayCellTimex100 = 270/100 ps
3949 11:13:01.781803 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3950 11:13:01.787923 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3951 11:13:01.791017 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3952 11:13:01.794880 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3953 11:13:01.797841 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3954 11:13:01.801263 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3955 11:13:01.801366
3956 11:13:01.804570 CA PerBit enable=1, Macro0, CA PI delay=34
3957 11:13:01.804643
3958 11:13:01.808252 [CBTSetCACLKResult] CA Dly = 34
3959 11:13:01.810888 CS Dly: 5 (0~37)
3960 11:13:01.810988
3961 11:13:01.814450 ----->DramcWriteLeveling(PI) begin...
3962 11:13:01.814536 ==
3963 11:13:01.818008 Dram Type= 6, Freq= 0, CH_0, rank 0
3964 11:13:01.820980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3965 11:13:01.821053 ==
3966 11:13:01.824282 Write leveling (Byte 0): 36 => 36
3967 11:13:01.827398 Write leveling (Byte 1): 31 => 31
3968 11:13:01.831174 DramcWriteLeveling(PI) end<-----
3969 11:13:01.831256
3970 11:13:01.831319 ==
3971 11:13:01.834127 Dram Type= 6, Freq= 0, CH_0, rank 0
3972 11:13:01.837515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3973 11:13:01.837624 ==
3974 11:13:01.840709 [Gating] SW mode calibration
3975 11:13:01.847659 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3976 11:13:01.853963 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3977 11:13:01.857482 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3978 11:13:01.860599 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3979 11:13:01.866793 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3980 11:13:01.870680 0 9 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
3981 11:13:01.873816 0 9 16 | B1->B0 | 2f2f 2d2d | 1 1 | (1 1) (1 0)
3982 11:13:01.880023 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3983 11:13:01.883835 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3984 11:13:01.887114 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3985 11:13:01.893753 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3986 11:13:01.897070 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3987 11:13:01.900151 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3988 11:13:01.906818 0 10 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
3989 11:13:01.909716 0 10 16 | B1->B0 | 3232 3c3c | 0 0 | (0 0) (0 0)
3990 11:13:01.913265 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 11:13:01.919628 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 11:13:01.923181 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3993 11:13:01.926984 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3994 11:13:01.933046 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 11:13:01.936204 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 11:13:01.939637 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3997 11:13:01.946009 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3998 11:13:01.949499 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 11:13:01.952871 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 11:13:01.959476 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 11:13:01.963055 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 11:13:01.966051 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 11:13:01.972441 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 11:13:01.975568 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 11:13:01.979357 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 11:13:01.985382 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 11:13:01.989174 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 11:13:01.992440 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 11:13:01.998481 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 11:13:02.002339 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 11:13:02.008501 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 11:13:02.012290 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 11:13:02.015240 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4014 11:13:02.018678 Total UI for P1: 0, mck2ui 16
4015 11:13:02.021721 best dqsien dly found for B0: ( 0, 13, 14)
4016 11:13:02.025177 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4017 11:13:02.028211 Total UI for P1: 0, mck2ui 16
4018 11:13:02.031749 best dqsien dly found for B1: ( 0, 13, 16)
4019 11:13:02.038311 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4020 11:13:02.041281 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4021 11:13:02.041386
4022 11:13:02.044915 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4023 11:13:02.048051 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4024 11:13:02.051258 [Gating] SW calibration Done
4025 11:13:02.051358 ==
4026 11:13:02.054885 Dram Type= 6, Freq= 0, CH_0, rank 0
4027 11:13:02.057827 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4028 11:13:02.057933 ==
4029 11:13:02.061396 RX Vref Scan: 0
4030 11:13:02.061496
4031 11:13:02.061593 RX Vref 0 -> 0, step: 1
4032 11:13:02.061682
4033 11:13:02.064162 RX Delay -230 -> 252, step: 16
4034 11:13:02.071046 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4035 11:13:02.074125 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4036 11:13:02.077372 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4037 11:13:02.081086 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4038 11:13:02.087927 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4039 11:13:02.090911 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4040 11:13:02.094113 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4041 11:13:02.097175 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4042 11:13:02.100323 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4043 11:13:02.107216 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4044 11:13:02.110405 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4045 11:13:02.113598 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4046 11:13:02.117340 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4047 11:13:02.123874 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4048 11:13:02.126885 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4049 11:13:02.130321 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4050 11:13:02.130427 ==
4051 11:13:02.133359 Dram Type= 6, Freq= 0, CH_0, rank 0
4052 11:13:02.140003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4053 11:13:02.140108 ==
4054 11:13:02.140221 DQS Delay:
4055 11:13:02.140325 DQS0 = 0, DQS1 = 0
4056 11:13:02.143546 DQM Delay:
4057 11:13:02.143665 DQM0 = 38, DQM1 = 29
4058 11:13:02.146573 DQ Delay:
4059 11:13:02.150127 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4060 11:13:02.153306 DQ4 =41, DQ5 =25, DQ6 =49, DQ7 =49
4061 11:13:02.156549 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4062 11:13:02.160147 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4063 11:13:02.160275
4064 11:13:02.160383
4065 11:13:02.160491 ==
4066 11:13:02.163225 Dram Type= 6, Freq= 0, CH_0, rank 0
4067 11:13:02.166399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4068 11:13:02.166502 ==
4069 11:13:02.166596
4070 11:13:02.166684
4071 11:13:02.169857 TX Vref Scan disable
4072 11:13:02.172901 == TX Byte 0 ==
4073 11:13:02.176654 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
4074 11:13:02.179630 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
4075 11:13:02.182748 == TX Byte 1 ==
4076 11:13:02.186517 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4077 11:13:02.189656 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4078 11:13:02.189753 ==
4079 11:13:02.192750 Dram Type= 6, Freq= 0, CH_0, rank 0
4080 11:13:02.196499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4081 11:13:02.199608 ==
4082 11:13:02.199706
4083 11:13:02.199797
4084 11:13:02.199888 TX Vref Scan disable
4085 11:13:02.203405 == TX Byte 0 ==
4086 11:13:02.206497 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4087 11:13:02.213471 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4088 11:13:02.213570 == TX Byte 1 ==
4089 11:13:02.216656 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4090 11:13:02.222772 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4091 11:13:02.222914
4092 11:13:02.223010 [DATLAT]
4093 11:13:02.223099 Freq=600, CH0 RK0
4094 11:13:02.223190
4095 11:13:02.226480 DATLAT Default: 0x9
4096 11:13:02.229668 0, 0xFFFF, sum = 0
4097 11:13:02.229785 1, 0xFFFF, sum = 0
4098 11:13:02.232735 2, 0xFFFF, sum = 0
4099 11:13:02.232852 3, 0xFFFF, sum = 0
4100 11:13:02.236176 4, 0xFFFF, sum = 0
4101 11:13:02.236284 5, 0xFFFF, sum = 0
4102 11:13:02.239576 6, 0xFFFF, sum = 0
4103 11:13:02.239683 7, 0xFFFF, sum = 0
4104 11:13:02.242711 8, 0x0, sum = 1
4105 11:13:02.242816 9, 0x0, sum = 2
4106 11:13:02.246252 10, 0x0, sum = 3
4107 11:13:02.246359 11, 0x0, sum = 4
4108 11:13:02.246452 best_step = 9
4109 11:13:02.246549
4110 11:13:02.249302 ==
4111 11:13:02.252746 Dram Type= 6, Freq= 0, CH_0, rank 0
4112 11:13:02.255826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4113 11:13:02.255933 ==
4114 11:13:02.256025 RX Vref Scan: 1
4115 11:13:02.256117
4116 11:13:02.259582 RX Vref 0 -> 0, step: 1
4117 11:13:02.259651
4118 11:13:02.262605 RX Delay -195 -> 252, step: 8
4119 11:13:02.262699
4120 11:13:02.265580 Set Vref, RX VrefLevel [Byte0]: 62
4121 11:13:02.269229 [Byte1]: 56
4122 11:13:02.269328
4123 11:13:02.272462 Final RX Vref Byte 0 = 62 to rank0
4124 11:13:02.276169 Final RX Vref Byte 1 = 56 to rank0
4125 11:13:02.278957 Final RX Vref Byte 0 = 62 to rank1
4126 11:13:02.281999 Final RX Vref Byte 1 = 56 to rank1==
4127 11:13:02.285556 Dram Type= 6, Freq= 0, CH_0, rank 0
4128 11:13:02.291925 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4129 11:13:02.292029 ==
4130 11:13:02.292121 DQS Delay:
4131 11:13:02.292214 DQS0 = 0, DQS1 = 0
4132 11:13:02.295597 DQM Delay:
4133 11:13:02.295702 DQM0 = 35, DQM1 = 28
4134 11:13:02.298564 DQ Delay:
4135 11:13:02.302413 DQ0 =36, DQ1 =36, DQ2 =36, DQ3 =32
4136 11:13:02.305484 DQ4 =32, DQ5 =24, DQ6 =40, DQ7 =48
4137 11:13:02.305583 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4138 11:13:02.312317 DQ12 =36, DQ13 =32, DQ14 =40, DQ15 =36
4139 11:13:02.312418
4140 11:13:02.312513
4141 11:13:02.319222 [DQSOSCAuto] RK0, (LSB)MR18= 0x3f3e, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
4142 11:13:02.322137 CH0 RK0: MR19=808, MR18=3F3E
4143 11:13:02.328845 CH0_RK0: MR19=0x808, MR18=0x3F3E, DQSOSC=397, MR23=63, INC=166, DEC=110
4144 11:13:02.328947
4145 11:13:02.332052 ----->DramcWriteLeveling(PI) begin...
4146 11:13:02.332132 ==
4147 11:13:02.335101 Dram Type= 6, Freq= 0, CH_0, rank 1
4148 11:13:02.338184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4149 11:13:02.338257 ==
4150 11:13:02.341795 Write leveling (Byte 0): 34 => 34
4151 11:13:02.345316 Write leveling (Byte 1): 30 => 30
4152 11:13:02.348050 DramcWriteLeveling(PI) end<-----
4153 11:13:02.348131
4154 11:13:02.348195 ==
4155 11:13:02.351702 Dram Type= 6, Freq= 0, CH_0, rank 1
4156 11:13:02.355094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4157 11:13:02.358105 ==
4158 11:13:02.358206 [Gating] SW mode calibration
4159 11:13:02.364717 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4160 11:13:02.371387 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4161 11:13:02.374705 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4162 11:13:02.381068 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4163 11:13:02.384108 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4164 11:13:02.387747 0 9 12 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
4165 11:13:02.394463 0 9 16 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
4166 11:13:02.397576 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4167 11:13:02.401210 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4168 11:13:02.407520 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4169 11:13:02.410738 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4170 11:13:02.414381 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4171 11:13:02.420833 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4172 11:13:02.424249 0 10 12 | B1->B0 | 2525 3232 | 0 0 | (0 0) (0 0)
4173 11:13:02.427456 0 10 16 | B1->B0 | 3232 4646 | 1 0 | (0 0) (0 0)
4174 11:13:02.434281 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4175 11:13:02.437482 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4176 11:13:02.440716 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4177 11:13:02.446836 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4178 11:13:02.450636 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4179 11:13:02.454060 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4180 11:13:02.460625 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4181 11:13:02.463536 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4182 11:13:02.466847 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 11:13:02.473611 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 11:13:02.476597 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 11:13:02.480390 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 11:13:02.486617 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 11:13:02.490103 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 11:13:02.493714 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 11:13:02.500490 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 11:13:02.503754 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 11:13:02.506677 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 11:13:02.513520 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 11:13:02.516629 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 11:13:02.520181 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 11:13:02.526339 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 11:13:02.530135 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4197 11:13:02.533255 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4198 11:13:02.536270 Total UI for P1: 0, mck2ui 16
4199 11:13:02.539983 best dqsien dly found for B0: ( 0, 13, 12)
4200 11:13:02.543015 Total UI for P1: 0, mck2ui 16
4201 11:13:02.546142 best dqsien dly found for B1: ( 0, 13, 12)
4202 11:13:02.549937 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4203 11:13:02.553085 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4204 11:13:02.556066
4205 11:13:02.559846 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4206 11:13:02.562410 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4207 11:13:02.566037 [Gating] SW calibration Done
4208 11:13:02.566239 ==
4209 11:13:02.568982 Dram Type= 6, Freq= 0, CH_0, rank 1
4210 11:13:02.572667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4211 11:13:02.572857 ==
4212 11:13:02.573026 RX Vref Scan: 0
4213 11:13:02.575520
4214 11:13:02.575706 RX Vref 0 -> 0, step: 1
4215 11:13:02.575870
4216 11:13:02.579169 RX Delay -230 -> 252, step: 16
4217 11:13:02.582104 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4218 11:13:02.589059 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4219 11:13:02.592287 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4220 11:13:02.595191 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4221 11:13:02.598656 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4222 11:13:02.605363 iDelay=218, Bit 5, Center 17 (-150 ~ 185) 336
4223 11:13:02.609037 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4224 11:13:02.612054 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4225 11:13:02.615276 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4226 11:13:02.618354 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4227 11:13:02.625412 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4228 11:13:02.628921 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4229 11:13:02.631969 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4230 11:13:02.635181 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4231 11:13:02.641838 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4232 11:13:02.644960 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4233 11:13:02.645243 ==
4234 11:13:02.648129 Dram Type= 6, Freq= 0, CH_0, rank 1
4235 11:13:02.651352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4236 11:13:02.651633 ==
4237 11:13:02.655098 DQS Delay:
4238 11:13:02.655378 DQS0 = 0, DQS1 = 0
4239 11:13:02.658139 DQM Delay:
4240 11:13:02.658417 DQM0 = 36, DQM1 = 28
4241 11:13:02.658640 DQ Delay:
4242 11:13:02.661159 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4243 11:13:02.664869 DQ4 =33, DQ5 =17, DQ6 =49, DQ7 =49
4244 11:13:02.668054 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4245 11:13:02.671431 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4246 11:13:02.671711
4247 11:13:02.671932
4248 11:13:02.674412 ==
4249 11:13:02.674694 Dram Type= 6, Freq= 0, CH_0, rank 1
4250 11:13:02.681217 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4251 11:13:02.681584 ==
4252 11:13:02.681871
4253 11:13:02.682135
4254 11:13:02.684668 TX Vref Scan disable
4255 11:13:02.685028 == TX Byte 0 ==
4256 11:13:02.691129 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4257 11:13:02.694386 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4258 11:13:02.694929 == TX Byte 1 ==
4259 11:13:02.701135 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4260 11:13:02.704111 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4261 11:13:02.704583 ==
4262 11:13:02.707533 Dram Type= 6, Freq= 0, CH_0, rank 1
4263 11:13:02.710493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4264 11:13:02.711016 ==
4265 11:13:02.711391
4266 11:13:02.711736
4267 11:13:02.714060 TX Vref Scan disable
4268 11:13:02.717466 == TX Byte 0 ==
4269 11:13:02.720861 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4270 11:13:02.727431 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4271 11:13:02.727908 == TX Byte 1 ==
4272 11:13:02.730714 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4273 11:13:02.737249 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4274 11:13:02.737600
4275 11:13:02.738007 [DATLAT]
4276 11:13:02.738345 Freq=600, CH0 RK1
4277 11:13:02.738594
4278 11:13:02.740371 DATLAT Default: 0x9
4279 11:13:02.743481 0, 0xFFFF, sum = 0
4280 11:13:02.743728 1, 0xFFFF, sum = 0
4281 11:13:02.746986 2, 0xFFFF, sum = 0
4282 11:13:02.747193 3, 0xFFFF, sum = 0
4283 11:13:02.750171 4, 0xFFFF, sum = 0
4284 11:13:02.750333 5, 0xFFFF, sum = 0
4285 11:13:02.753273 6, 0xFFFF, sum = 0
4286 11:13:02.753486 7, 0xFFFF, sum = 0
4287 11:13:02.756421 8, 0x0, sum = 1
4288 11:13:02.756560 9, 0x0, sum = 2
4289 11:13:02.759688 10, 0x0, sum = 3
4290 11:13:02.759824 11, 0x0, sum = 4
4291 11:13:02.759924 best_step = 9
4292 11:13:02.760012
4293 11:13:02.763197 ==
4294 11:13:02.766115 Dram Type= 6, Freq= 0, CH_0, rank 1
4295 11:13:02.769831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4296 11:13:02.769927 ==
4297 11:13:02.770000 RX Vref Scan: 0
4298 11:13:02.770069
4299 11:13:02.772946 RX Vref 0 -> 0, step: 1
4300 11:13:02.773039
4301 11:13:02.776101 RX Delay -195 -> 252, step: 8
4302 11:13:02.782637 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4303 11:13:02.786091 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4304 11:13:02.789074 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4305 11:13:02.792712 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4306 11:13:02.799102 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4307 11:13:02.802256 iDelay=205, Bit 5, Center 20 (-139 ~ 180) 320
4308 11:13:02.805432 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4309 11:13:02.809113 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4310 11:13:02.815742 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4311 11:13:02.818734 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4312 11:13:02.822411 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4313 11:13:02.825264 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4314 11:13:02.832038 iDelay=205, Bit 12, Center 32 (-131 ~ 196) 328
4315 11:13:02.835573 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4316 11:13:02.838840 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4317 11:13:02.841776 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4318 11:13:02.841857 ==
4319 11:13:02.844871 Dram Type= 6, Freq= 0, CH_0, rank 1
4320 11:13:02.851658 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4321 11:13:02.851741 ==
4322 11:13:02.851805 DQS Delay:
4323 11:13:02.854780 DQS0 = 0, DQS1 = 0
4324 11:13:02.854869 DQM Delay:
4325 11:13:02.854933 DQM0 = 33, DQM1 = 27
4326 11:13:02.857966 DQ Delay:
4327 11:13:02.861771 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4328 11:13:02.864815 DQ4 =32, DQ5 =20, DQ6 =44, DQ7 =44
4329 11:13:02.868014 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4330 11:13:02.871281 DQ12 =32, DQ13 =36, DQ14 =36, DQ15 =36
4331 11:13:02.871370
4332 11:13:02.871434
4333 11:13:02.878107 [DQSOSCAuto] RK1, (LSB)MR18= 0x6936, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 390 ps
4334 11:13:02.881267 CH0 RK1: MR19=808, MR18=6936
4335 11:13:02.887637 CH0_RK1: MR19=0x808, MR18=0x6936, DQSOSC=390, MR23=63, INC=172, DEC=114
4336 11:13:02.891408 [RxdqsGatingPostProcess] freq 600
4337 11:13:02.897726 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4338 11:13:02.897856 Pre-setting of DQS Precalculation
4339 11:13:02.904587 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4340 11:13:02.904697 ==
4341 11:13:02.907504 Dram Type= 6, Freq= 0, CH_1, rank 0
4342 11:13:02.910715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4343 11:13:02.910819 ==
4344 11:13:02.917485 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4345 11:13:02.924037 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
4346 11:13:02.927515 [CA 0] Center 36 (6~66) winsize 61
4347 11:13:02.930689 [CA 1] Center 36 (6~66) winsize 61
4348 11:13:02.934212 [CA 2] Center 34 (4~65) winsize 62
4349 11:13:02.937258 [CA 3] Center 34 (3~65) winsize 63
4350 11:13:02.940693 [CA 4] Center 34 (4~65) winsize 62
4351 11:13:02.943840 [CA 5] Center 33 (3~64) winsize 62
4352 11:13:02.943925
4353 11:13:02.946987 [CmdBusTrainingLP45] Vref(ca) range 1: 31
4354 11:13:02.947072
4355 11:13:02.950150 [CATrainingPosCal] consider 1 rank data
4356 11:13:02.953756 u2DelayCellTimex100 = 270/100 ps
4357 11:13:02.956942 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4358 11:13:02.960112 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4359 11:13:02.963404 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4360 11:13:02.967125 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4361 11:13:02.970313 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4362 11:13:02.976777 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4363 11:13:02.976866
4364 11:13:02.980105 CA PerBit enable=1, Macro0, CA PI delay=33
4365 11:13:02.980190
4366 11:13:02.983252 [CBTSetCACLKResult] CA Dly = 33
4367 11:13:02.983335 CS Dly: 4 (0~35)
4368 11:13:02.983401 ==
4369 11:13:02.986432 Dram Type= 6, Freq= 0, CH_1, rank 1
4370 11:13:02.993163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4371 11:13:02.993251 ==
4372 11:13:02.996683 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4373 11:13:03.003052 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4374 11:13:03.006596 [CA 0] Center 36 (6~66) winsize 61
4375 11:13:03.010088 [CA 1] Center 36 (6~67) winsize 62
4376 11:13:03.012809 [CA 2] Center 34 (4~65) winsize 62
4377 11:13:03.016387 [CA 3] Center 34 (3~65) winsize 63
4378 11:13:03.019401 [CA 4] Center 34 (4~65) winsize 62
4379 11:13:03.022567 [CA 5] Center 33 (3~64) winsize 62
4380 11:13:03.022653
4381 11:13:03.026431 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4382 11:13:03.026514
4383 11:13:03.029613 [CATrainingPosCal] consider 2 rank data
4384 11:13:03.032906 u2DelayCellTimex100 = 270/100 ps
4385 11:13:03.035742 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4386 11:13:03.042929 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4387 11:13:03.045618 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4388 11:13:03.049172 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4389 11:13:03.052414 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4390 11:13:03.055481 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4391 11:13:03.055566
4392 11:13:03.059151 CA PerBit enable=1, Macro0, CA PI delay=33
4393 11:13:03.059249
4394 11:13:03.062421 [CBTSetCACLKResult] CA Dly = 33
4395 11:13:03.065581 CS Dly: 5 (0~37)
4396 11:13:03.065664
4397 11:13:03.068699 ----->DramcWriteLeveling(PI) begin...
4398 11:13:03.068783 ==
4399 11:13:03.071864 Dram Type= 6, Freq= 0, CH_1, rank 0
4400 11:13:03.075831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4401 11:13:03.075916 ==
4402 11:13:03.078520 Write leveling (Byte 0): 30 => 30
4403 11:13:03.082196 Write leveling (Byte 1): 30 => 30
4404 11:13:03.085395 DramcWriteLeveling(PI) end<-----
4405 11:13:03.085478
4406 11:13:03.085544 ==
4407 11:13:03.088527 Dram Type= 6, Freq= 0, CH_1, rank 0
4408 11:13:03.091789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4409 11:13:03.091872 ==
4410 11:13:03.094770 [Gating] SW mode calibration
4411 11:13:03.101625 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4412 11:13:03.108056 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4413 11:13:03.111569 0 9 0 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
4414 11:13:03.115081 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4415 11:13:03.121640 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4416 11:13:03.124574 0 9 12 | B1->B0 | 3333 3030 | 1 1 | (1 1) (1 0)
4417 11:13:03.128205 0 9 16 | B1->B0 | 2828 2626 | 0 0 | (0 0) (0 0)
4418 11:13:03.134568 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4419 11:13:03.137626 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4420 11:13:03.141171 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4421 11:13:03.147855 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4422 11:13:03.151312 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4423 11:13:03.154562 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4424 11:13:03.160865 0 10 12 | B1->B0 | 2f2f 2f2f | 0 1 | (0 0) (0 0)
4425 11:13:03.163874 0 10 16 | B1->B0 | 4141 3e3e | 1 1 | (0 0) (1 1)
4426 11:13:03.167713 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 11:13:03.173982 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 11:13:03.177279 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 11:13:03.180727 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 11:13:03.187462 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 11:13:03.190596 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 11:13:03.194125 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4433 11:13:03.200125 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4434 11:13:03.204223 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 11:13:03.207091 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 11:13:03.213771 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 11:13:03.216803 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 11:13:03.219907 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 11:13:03.227002 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 11:13:03.229960 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 11:13:03.236579 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 11:13:03.239627 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 11:13:03.243309 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 11:13:03.249951 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 11:13:03.252851 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 11:13:03.255960 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 11:13:03.262507 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 11:13:03.266247 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4449 11:13:03.269671 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4450 11:13:03.272887 Total UI for P1: 0, mck2ui 16
4451 11:13:03.276000 best dqsien dly found for B0: ( 0, 13, 12)
4452 11:13:03.279050 Total UI for P1: 0, mck2ui 16
4453 11:13:03.282814 best dqsien dly found for B1: ( 0, 13, 12)
4454 11:13:03.285954 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4455 11:13:03.288981 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4456 11:13:03.289064
4457 11:13:03.295842 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4458 11:13:03.299017 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4459 11:13:03.299106 [Gating] SW calibration Done
4460 11:13:03.302177 ==
4461 11:13:03.305966 Dram Type= 6, Freq= 0, CH_1, rank 0
4462 11:13:03.309147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4463 11:13:03.309257 ==
4464 11:13:03.309351 RX Vref Scan: 0
4465 11:13:03.309444
4466 11:13:03.312323 RX Vref 0 -> 0, step: 1
4467 11:13:03.312422
4468 11:13:03.315412 RX Delay -230 -> 252, step: 16
4469 11:13:03.319067 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4470 11:13:03.322017 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4471 11:13:03.328532 iDelay=218, Bit 2, Center 25 (-150 ~ 201) 352
4472 11:13:03.332116 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4473 11:13:03.335131 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4474 11:13:03.338606 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4475 11:13:03.345298 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4476 11:13:03.348510 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4477 11:13:03.351938 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4478 11:13:03.355102 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4479 11:13:03.361821 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4480 11:13:03.364776 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4481 11:13:03.368024 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4482 11:13:03.371665 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4483 11:13:03.378145 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4484 11:13:03.381280 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4485 11:13:03.381391 ==
4486 11:13:03.384884 Dram Type= 6, Freq= 0, CH_1, rank 0
4487 11:13:03.387977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4488 11:13:03.388078 ==
4489 11:13:03.391051 DQS Delay:
4490 11:13:03.391126 DQS0 = 0, DQS1 = 0
4491 11:13:03.391189 DQM Delay:
4492 11:13:03.394668 DQM0 = 37, DQM1 = 28
4493 11:13:03.394796 DQ Delay:
4494 11:13:03.397857 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =33
4495 11:13:03.401127 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4496 11:13:03.404720 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4497 11:13:03.408116 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4498 11:13:03.408202
4499 11:13:03.408268
4500 11:13:03.408328 ==
4501 11:13:03.411091 Dram Type= 6, Freq= 0, CH_1, rank 0
4502 11:13:03.417313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4503 11:13:03.417400 ==
4504 11:13:03.417466
4505 11:13:03.417527
4506 11:13:03.417587 TX Vref Scan disable
4507 11:13:03.421643 == TX Byte 0 ==
4508 11:13:03.424768 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4509 11:13:03.431352 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4510 11:13:03.431444 == TX Byte 1 ==
4511 11:13:03.434345 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4512 11:13:03.441169 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4513 11:13:03.441255 ==
4514 11:13:03.444177 Dram Type= 6, Freq= 0, CH_1, rank 0
4515 11:13:03.447612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4516 11:13:03.447713 ==
4517 11:13:03.447782
4518 11:13:03.447843
4519 11:13:03.450628 TX Vref Scan disable
4520 11:13:03.454074 == TX Byte 0 ==
4521 11:13:03.457313 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4522 11:13:03.460662 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4523 11:13:03.464037 == TX Byte 1 ==
4524 11:13:03.467031 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4525 11:13:03.470747 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4526 11:13:03.470856
4527 11:13:03.473866 [DATLAT]
4528 11:13:03.473950 Freq=600, CH1 RK0
4529 11:13:03.474016
4530 11:13:03.477033 DATLAT Default: 0x9
4531 11:13:03.477117 0, 0xFFFF, sum = 0
4532 11:13:03.480633 1, 0xFFFF, sum = 0
4533 11:13:03.480719 2, 0xFFFF, sum = 0
4534 11:13:03.483692 3, 0xFFFF, sum = 0
4535 11:13:03.483777 4, 0xFFFF, sum = 0
4536 11:13:03.487187 5, 0xFFFF, sum = 0
4537 11:13:03.487303 6, 0xFFFF, sum = 0
4538 11:13:03.490365 7, 0xFFFF, sum = 0
4539 11:13:03.490450 8, 0x0, sum = 1
4540 11:13:03.494037 9, 0x0, sum = 2
4541 11:13:03.494123 10, 0x0, sum = 3
4542 11:13:03.497033 11, 0x0, sum = 4
4543 11:13:03.497123 best_step = 9
4544 11:13:03.497191
4545 11:13:03.497253 ==
4546 11:13:03.500753 Dram Type= 6, Freq= 0, CH_1, rank 0
4547 11:13:03.503845 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4548 11:13:03.503932 ==
4549 11:13:03.507055 RX Vref Scan: 1
4550 11:13:03.507139
4551 11:13:03.510178 RX Vref 0 -> 0, step: 1
4552 11:13:03.510262
4553 11:13:03.510328 RX Delay -195 -> 252, step: 8
4554 11:13:03.513385
4555 11:13:03.513468 Set Vref, RX VrefLevel [Byte0]: 57
4556 11:13:03.517243 [Byte1]: 53
4557 11:13:03.521565
4558 11:13:03.521653 Final RX Vref Byte 0 = 57 to rank0
4559 11:13:03.524903 Final RX Vref Byte 1 = 53 to rank0
4560 11:13:03.528680 Final RX Vref Byte 0 = 57 to rank1
4561 11:13:03.531868 Final RX Vref Byte 1 = 53 to rank1==
4562 11:13:03.534960 Dram Type= 6, Freq= 0, CH_1, rank 0
4563 11:13:03.541473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4564 11:13:03.541565 ==
4565 11:13:03.541632 DQS Delay:
4566 11:13:03.545009 DQS0 = 0, DQS1 = 0
4567 11:13:03.545093 DQM Delay:
4568 11:13:03.545159 DQM0 = 39, DQM1 = 27
4569 11:13:03.548375 DQ Delay:
4570 11:13:03.551221 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =36
4571 11:13:03.554755 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36
4572 11:13:03.557909 DQ8 =12, DQ9 =16, DQ10 =28, DQ11 =20
4573 11:13:03.561641 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4574 11:13:03.561727
4575 11:13:03.561793
4576 11:13:03.567836 [DQSOSCAuto] RK0, (LSB)MR18= 0x2634, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 402 ps
4577 11:13:03.570926 CH1 RK0: MR19=808, MR18=2634
4578 11:13:03.578026 CH1_RK0: MR19=0x808, MR18=0x2634, DQSOSC=400, MR23=63, INC=163, DEC=109
4579 11:13:03.578121
4580 11:13:03.581196 ----->DramcWriteLeveling(PI) begin...
4581 11:13:03.581284 ==
4582 11:13:03.584138 Dram Type= 6, Freq= 0, CH_1, rank 1
4583 11:13:03.587887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4584 11:13:03.587973 ==
4585 11:13:03.590942 Write leveling (Byte 0): 31 => 31
4586 11:13:03.594016 Write leveling (Byte 1): 31 => 31
4587 11:13:03.597760 DramcWriteLeveling(PI) end<-----
4588 11:13:03.597849
4589 11:13:03.597917 ==
4590 11:13:03.600900 Dram Type= 6, Freq= 0, CH_1, rank 1
4591 11:13:03.603969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4592 11:13:03.607674 ==
4593 11:13:03.607760 [Gating] SW mode calibration
4594 11:13:03.617244 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4595 11:13:03.620375 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4596 11:13:03.624151 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4597 11:13:03.630279 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4598 11:13:03.633481 0 9 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
4599 11:13:03.637338 0 9 12 | B1->B0 | 2f2f 2c2c | 1 1 | (1 0) (1 0)
4600 11:13:03.643531 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4601 11:13:03.646986 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4602 11:13:03.650485 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4603 11:13:03.656855 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4604 11:13:03.660373 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4605 11:13:03.663381 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4606 11:13:03.670258 0 10 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
4607 11:13:03.673403 0 10 12 | B1->B0 | 3030 3838 | 0 0 | (0 0) (0 0)
4608 11:13:03.676459 0 10 16 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
4609 11:13:03.683340 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4610 11:13:03.686137 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4611 11:13:03.689964 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4612 11:13:03.696377 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4613 11:13:03.699459 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4614 11:13:03.703056 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4615 11:13:03.709234 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4616 11:13:03.713330 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 11:13:03.716272 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 11:13:03.722501 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 11:13:03.726306 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 11:13:03.729446 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 11:13:03.735598 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 11:13:03.738970 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 11:13:03.742701 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 11:13:03.749064 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 11:13:03.752725 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 11:13:03.755566 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 11:13:03.762433 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 11:13:03.765835 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 11:13:03.768698 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 11:13:03.775285 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 11:13:03.778660 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4632 11:13:03.782384 Total UI for P1: 0, mck2ui 16
4633 11:13:03.785500 best dqsien dly found for B0: ( 0, 13, 10)
4634 11:13:03.788953 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4635 11:13:03.792246 Total UI for P1: 0, mck2ui 16
4636 11:13:03.795161 best dqsien dly found for B1: ( 0, 13, 12)
4637 11:13:03.798612 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4638 11:13:03.805365 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4639 11:13:03.805455
4640 11:13:03.808229 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4641 11:13:03.811755 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4642 11:13:03.814797 [Gating] SW calibration Done
4643 11:13:03.814927 ==
4644 11:13:03.818643 Dram Type= 6, Freq= 0, CH_1, rank 1
4645 11:13:03.821834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4646 11:13:03.821935 ==
4647 11:13:03.825041 RX Vref Scan: 0
4648 11:13:03.825123
4649 11:13:03.825188 RX Vref 0 -> 0, step: 1
4650 11:13:03.825248
4651 11:13:03.828198 RX Delay -230 -> 252, step: 16
4652 11:13:03.831381 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4653 11:13:03.838048 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4654 11:13:03.841167 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4655 11:13:03.844976 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4656 11:13:03.848158 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4657 11:13:03.854590 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4658 11:13:03.857605 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4659 11:13:03.861174 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4660 11:13:03.864162 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4661 11:13:03.871063 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4662 11:13:03.874386 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4663 11:13:03.877629 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4664 11:13:03.880632 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4665 11:13:03.887737 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4666 11:13:03.890939 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4667 11:13:03.894006 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4668 11:13:03.894089 ==
4669 11:13:03.897490 Dram Type= 6, Freq= 0, CH_1, rank 1
4670 11:13:03.900646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4671 11:13:03.900732 ==
4672 11:13:03.903792 DQS Delay:
4673 11:13:03.903905 DQS0 = 0, DQS1 = 0
4674 11:13:03.907527 DQM Delay:
4675 11:13:03.907606 DQM0 = 36, DQM1 = 29
4676 11:13:03.907681 DQ Delay:
4677 11:13:03.910408 DQ0 =41, DQ1 =33, DQ2 =17, DQ3 =33
4678 11:13:03.913837 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4679 11:13:03.917431 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4680 11:13:03.920455 DQ12 =33, DQ13 =41, DQ14 =33, DQ15 =33
4681 11:13:03.920541
4682 11:13:03.920607
4683 11:13:03.924221 ==
4684 11:13:03.927353 Dram Type= 6, Freq= 0, CH_1, rank 1
4685 11:13:03.930505 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4686 11:13:03.930619 ==
4687 11:13:03.930720
4688 11:13:03.930810
4689 11:13:03.933596 TX Vref Scan disable
4690 11:13:03.933697 == TX Byte 0 ==
4691 11:13:03.940526 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4692 11:13:03.943674 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4693 11:13:03.943790 == TX Byte 1 ==
4694 11:13:03.949890 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4695 11:13:03.953744 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4696 11:13:03.953853 ==
4697 11:13:03.956850 Dram Type= 6, Freq= 0, CH_1, rank 1
4698 11:13:03.960037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4699 11:13:03.960142 ==
4700 11:13:03.960235
4701 11:13:03.960323
4702 11:13:03.963069 TX Vref Scan disable
4703 11:13:03.966672 == TX Byte 0 ==
4704 11:13:03.969696 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4705 11:13:03.973560 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4706 11:13:03.976432 == TX Byte 1 ==
4707 11:13:03.979849 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4708 11:13:03.986254 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4709 11:13:03.986342
4710 11:13:03.986406 [DATLAT]
4711 11:13:03.986467 Freq=600, CH1 RK1
4712 11:13:03.986527
4713 11:13:03.989769 DATLAT Default: 0x9
4714 11:13:03.989869 0, 0xFFFF, sum = 0
4715 11:13:03.992704 1, 0xFFFF, sum = 0
4716 11:13:03.992788 2, 0xFFFF, sum = 0
4717 11:13:03.996465 3, 0xFFFF, sum = 0
4718 11:13:03.999516 4, 0xFFFF, sum = 0
4719 11:13:03.999605 5, 0xFFFF, sum = 0
4720 11:13:04.003199 6, 0xFFFF, sum = 0
4721 11:13:04.003285 7, 0xFFFF, sum = 0
4722 11:13:04.006473 8, 0x0, sum = 1
4723 11:13:04.006557 9, 0x0, sum = 2
4724 11:13:04.006624 10, 0x0, sum = 3
4725 11:13:04.009214 11, 0x0, sum = 4
4726 11:13:04.009298 best_step = 9
4727 11:13:04.009363
4728 11:13:04.009423 ==
4729 11:13:04.012606 Dram Type= 6, Freq= 0, CH_1, rank 1
4730 11:13:04.019017 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4731 11:13:04.019104 ==
4732 11:13:04.019171 RX Vref Scan: 0
4733 11:13:04.019258
4734 11:13:04.022563 RX Vref 0 -> 0, step: 1
4735 11:13:04.022639
4736 11:13:04.025766 RX Delay -195 -> 252, step: 8
4737 11:13:04.032705 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4738 11:13:04.035759 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4739 11:13:04.039027 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4740 11:13:04.042048 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4741 11:13:04.045619 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4742 11:13:04.051970 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4743 11:13:04.055702 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4744 11:13:04.058838 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4745 11:13:04.061980 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4746 11:13:04.068296 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4747 11:13:04.071800 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4748 11:13:04.075086 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4749 11:13:04.078781 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4750 11:13:04.085105 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4751 11:13:04.088036 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4752 11:13:04.091534 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4753 11:13:04.091628 ==
4754 11:13:04.094565 Dram Type= 6, Freq= 0, CH_1, rank 1
4755 11:13:04.101702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4756 11:13:04.101834 ==
4757 11:13:04.101905 DQS Delay:
4758 11:13:04.101970 DQS0 = 0, DQS1 = 0
4759 11:13:04.104904 DQM Delay:
4760 11:13:04.105005 DQM0 = 37, DQM1 = 29
4761 11:13:04.108385 DQ Delay:
4762 11:13:04.111615 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4763 11:13:04.111700 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =36
4764 11:13:04.114686 DQ8 =16, DQ9 =20, DQ10 =36, DQ11 =20
4765 11:13:04.121467 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4766 11:13:04.121554
4767 11:13:04.121620
4768 11:13:04.127987 [DQSOSCAuto] RK1, (LSB)MR18= 0x3353, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
4769 11:13:04.131055 CH1 RK1: MR19=808, MR18=3353
4770 11:13:04.137844 CH1_RK1: MR19=0x808, MR18=0x3353, DQSOSC=394, MR23=63, INC=168, DEC=112
4771 11:13:04.140994 [RxdqsGatingPostProcess] freq 600
4772 11:13:04.144092 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4773 11:13:04.147743 Pre-setting of DQS Precalculation
4774 11:13:04.154019 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4775 11:13:04.161003 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4776 11:13:04.167370 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4777 11:13:04.167467
4778 11:13:04.167554
4779 11:13:04.170485 [Calibration Summary] 1200 Mbps
4780 11:13:04.170571 CH 0, Rank 0
4781 11:13:04.174180 SW Impedance : PASS
4782 11:13:04.177428 DUTY Scan : NO K
4783 11:13:04.177513 ZQ Calibration : PASS
4784 11:13:04.180278 Jitter Meter : NO K
4785 11:13:04.184066 CBT Training : PASS
4786 11:13:04.184152 Write leveling : PASS
4787 11:13:04.187071 RX DQS gating : PASS
4788 11:13:04.190439 RX DQ/DQS(RDDQC) : PASS
4789 11:13:04.190557 TX DQ/DQS : PASS
4790 11:13:04.193541 RX DATLAT : PASS
4791 11:13:04.196997 RX DQ/DQS(Engine): PASS
4792 11:13:04.197110 TX OE : NO K
4793 11:13:04.200794 All Pass.
4794 11:13:04.200920
4795 11:13:04.201001 CH 0, Rank 1
4796 11:13:04.203484 SW Impedance : PASS
4797 11:13:04.203571 DUTY Scan : NO K
4798 11:13:04.207175 ZQ Calibration : PASS
4799 11:13:04.210428 Jitter Meter : NO K
4800 11:13:04.210502 CBT Training : PASS
4801 11:13:04.213552 Write leveling : PASS
4802 11:13:04.216693 RX DQS gating : PASS
4803 11:13:04.216805 RX DQ/DQS(RDDQC) : PASS
4804 11:13:04.219701 TX DQ/DQS : PASS
4805 11:13:04.223418 RX DATLAT : PASS
4806 11:13:04.223507 RX DQ/DQS(Engine): PASS
4807 11:13:04.226519 TX OE : NO K
4808 11:13:04.226636 All Pass.
4809 11:13:04.226726
4810 11:13:04.229910 CH 1, Rank 0
4811 11:13:04.230007 SW Impedance : PASS
4812 11:13:04.232986 DUTY Scan : NO K
4813 11:13:04.236657 ZQ Calibration : PASS
4814 11:13:04.236759 Jitter Meter : NO K
4815 11:13:04.239698 CBT Training : PASS
4816 11:13:04.239810 Write leveling : PASS
4817 11:13:04.242872 RX DQS gating : PASS
4818 11:13:04.246603 RX DQ/DQS(RDDQC) : PASS
4819 11:13:04.246700 TX DQ/DQS : PASS
4820 11:13:04.249712 RX DATLAT : PASS
4821 11:13:04.253393 RX DQ/DQS(Engine): PASS
4822 11:13:04.253505 TX OE : NO K
4823 11:13:04.256496 All Pass.
4824 11:13:04.256621
4825 11:13:04.256726 CH 1, Rank 1
4826 11:13:04.259748 SW Impedance : PASS
4827 11:13:04.259859 DUTY Scan : NO K
4828 11:13:04.262938 ZQ Calibration : PASS
4829 11:13:04.266123 Jitter Meter : NO K
4830 11:13:04.266234 CBT Training : PASS
4831 11:13:04.269304 Write leveling : PASS
4832 11:13:04.272524 RX DQS gating : PASS
4833 11:13:04.272653 RX DQ/DQS(RDDQC) : PASS
4834 11:13:04.275722 TX DQ/DQS : PASS
4835 11:13:04.279434 RX DATLAT : PASS
4836 11:13:04.279546 RX DQ/DQS(Engine): PASS
4837 11:13:04.282533 TX OE : NO K
4838 11:13:04.282657 All Pass.
4839 11:13:04.282758
4840 11:13:04.285579 DramC Write-DBI off
4841 11:13:04.289351 PER_BANK_REFRESH: Hybrid Mode
4842 11:13:04.289472 TX_TRACKING: ON
4843 11:13:04.299005 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4844 11:13:04.302362 [FAST_K] Save calibration result to emmc
4845 11:13:04.305425 dramc_set_vcore_voltage set vcore to 662500
4846 11:13:04.308924 Read voltage for 933, 3
4847 11:13:04.309039 Vio18 = 0
4848 11:13:04.309138 Vcore = 662500
4849 11:13:04.312373 Vdram = 0
4850 11:13:04.312486 Vddq = 0
4851 11:13:04.312600 Vmddr = 0
4852 11:13:04.318653 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4853 11:13:04.322421 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4854 11:13:04.325652 MEM_TYPE=3, freq_sel=17
4855 11:13:04.328502 sv_algorithm_assistance_LP4_1600
4856 11:13:04.332183 ============ PULL DRAM RESETB DOWN ============
4857 11:13:04.338745 ========== PULL DRAM RESETB DOWN end =========
4858 11:13:04.342302 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4859 11:13:04.345074 ===================================
4860 11:13:04.348173 LPDDR4 DRAM CONFIGURATION
4861 11:13:04.351862 ===================================
4862 11:13:04.351973 EX_ROW_EN[0] = 0x0
4863 11:13:04.354968 EX_ROW_EN[1] = 0x0
4864 11:13:04.355078 LP4Y_EN = 0x0
4865 11:13:04.358650 WORK_FSP = 0x0
4866 11:13:04.358760 WL = 0x3
4867 11:13:04.361823 RL = 0x3
4868 11:13:04.361935 BL = 0x2
4869 11:13:04.365076 RPST = 0x0
4870 11:13:04.368188 RD_PRE = 0x0
4871 11:13:04.368310 WR_PRE = 0x1
4872 11:13:04.371504 WR_PST = 0x0
4873 11:13:04.371616 DBI_WR = 0x0
4874 11:13:04.374639 DBI_RD = 0x0
4875 11:13:04.374748 OTF = 0x1
4876 11:13:04.378395 ===================================
4877 11:13:04.381485 ===================================
4878 11:13:04.384692 ANA top config
4879 11:13:04.387506 ===================================
4880 11:13:04.387623 DLL_ASYNC_EN = 0
4881 11:13:04.391189 ALL_SLAVE_EN = 1
4882 11:13:04.394328 NEW_RANK_MODE = 1
4883 11:13:04.397455 DLL_IDLE_MODE = 1
4884 11:13:04.401038 LP45_APHY_COMB_EN = 1
4885 11:13:04.401173 TX_ODT_DIS = 1
4886 11:13:04.404105 NEW_8X_MODE = 1
4887 11:13:04.407623 ===================================
4888 11:13:04.410493 ===================================
4889 11:13:04.414197 data_rate = 1866
4890 11:13:04.417593 CKR = 1
4891 11:13:04.420574 DQ_P2S_RATIO = 8
4892 11:13:04.423531 ===================================
4893 11:13:04.427214 CA_P2S_RATIO = 8
4894 11:13:04.427337 DQ_CA_OPEN = 0
4895 11:13:04.430352 DQ_SEMI_OPEN = 0
4896 11:13:04.434063 CA_SEMI_OPEN = 0
4897 11:13:04.437240 CA_FULL_RATE = 0
4898 11:13:04.440389 DQ_CKDIV4_EN = 1
4899 11:13:04.443395 CA_CKDIV4_EN = 1
4900 11:13:04.443514 CA_PREDIV_EN = 0
4901 11:13:04.446854 PH8_DLY = 0
4902 11:13:04.450406 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4903 11:13:04.453292 DQ_AAMCK_DIV = 4
4904 11:13:04.457043 CA_AAMCK_DIV = 4
4905 11:13:04.460065 CA_ADMCK_DIV = 4
4906 11:13:04.460177 DQ_TRACK_CA_EN = 0
4907 11:13:04.463090 CA_PICK = 933
4908 11:13:04.466303 CA_MCKIO = 933
4909 11:13:04.470009 MCKIO_SEMI = 0
4910 11:13:04.473240 PLL_FREQ = 3732
4911 11:13:04.476414 DQ_UI_PI_RATIO = 32
4912 11:13:04.479465 CA_UI_PI_RATIO = 0
4913 11:13:04.483319 ===================================
4914 11:13:04.486495 ===================================
4915 11:13:04.486604 memory_type:LPDDR4
4916 11:13:04.489576 GP_NUM : 10
4917 11:13:04.492663 SRAM_EN : 1
4918 11:13:04.492774 MD32_EN : 0
4919 11:13:04.496452 ===================================
4920 11:13:04.499629 [ANA_INIT] >>>>>>>>>>>>>>
4921 11:13:04.502727 <<<<<< [CONFIGURE PHASE]: ANA_TX
4922 11:13:04.505794 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4923 11:13:04.509493 ===================================
4924 11:13:04.512833 data_rate = 1866,PCW = 0X8f00
4925 11:13:04.515737 ===================================
4926 11:13:04.519343 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4927 11:13:04.522307 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4928 11:13:04.529346 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4929 11:13:04.532320 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4930 11:13:04.538990 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4931 11:13:04.542117 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4932 11:13:04.542239 [ANA_INIT] flow start
4933 11:13:04.545889 [ANA_INIT] PLL >>>>>>>>
4934 11:13:04.548993 [ANA_INIT] PLL <<<<<<<<
4935 11:13:04.549114 [ANA_INIT] MIDPI >>>>>>>>
4936 11:13:04.551966 [ANA_INIT] MIDPI <<<<<<<<
4937 11:13:04.555565 [ANA_INIT] DLL >>>>>>>>
4938 11:13:04.555682 [ANA_INIT] flow end
4939 11:13:04.562005 ============ LP4 DIFF to SE enter ============
4940 11:13:04.565710 ============ LP4 DIFF to SE exit ============
4941 11:13:04.565829 [ANA_INIT] <<<<<<<<<<<<<
4942 11:13:04.568854 [Flow] Enable top DCM control >>>>>
4943 11:13:04.571987 [Flow] Enable top DCM control <<<<<
4944 11:13:04.575166 Enable DLL master slave shuffle
4945 11:13:04.582259 ==============================================================
4946 11:13:04.586065 Gating Mode config
4947 11:13:04.588667 ==============================================================
4948 11:13:04.592064 Config description:
4949 11:13:04.602312 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4950 11:13:04.608415 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4951 11:13:04.611410 SELPH_MODE 0: By rank 1: By Phase
4952 11:13:04.618522 ==============================================================
4953 11:13:04.621591 GAT_TRACK_EN = 1
4954 11:13:04.624939 RX_GATING_MODE = 2
4955 11:13:04.627973 RX_GATING_TRACK_MODE = 2
4956 11:13:04.631406 SELPH_MODE = 1
4957 11:13:04.631535 PICG_EARLY_EN = 1
4958 11:13:04.634893 VALID_LAT_VALUE = 1
4959 11:13:04.641336 ==============================================================
4960 11:13:04.644576 Enter into Gating configuration >>>>
4961 11:13:04.647672 Exit from Gating configuration <<<<
4962 11:13:04.651563 Enter into DVFS_PRE_config >>>>>
4963 11:13:04.661156 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4964 11:13:04.664085 Exit from DVFS_PRE_config <<<<<
4965 11:13:04.667666 Enter into PICG configuration >>>>
4966 11:13:04.670629 Exit from PICG configuration <<<<
4967 11:13:04.674189 [RX_INPUT] configuration >>>>>
4968 11:13:04.677341 [RX_INPUT] configuration <<<<<
4969 11:13:04.684093 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4970 11:13:04.687330 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4971 11:13:04.694213 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4972 11:13:04.700483 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4973 11:13:04.707471 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4974 11:13:04.713824 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4975 11:13:04.716910 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4976 11:13:04.720331 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4977 11:13:04.723455 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4978 11:13:04.730366 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4979 11:13:04.733430 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4980 11:13:04.737011 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4981 11:13:04.739939 ===================================
4982 11:13:04.743459 LPDDR4 DRAM CONFIGURATION
4983 11:13:04.746409 ===================================
4984 11:13:04.749994 EX_ROW_EN[0] = 0x0
4985 11:13:04.750120 EX_ROW_EN[1] = 0x0
4986 11:13:04.753174 LP4Y_EN = 0x0
4987 11:13:04.753285 WORK_FSP = 0x0
4988 11:13:04.756402 WL = 0x3
4989 11:13:04.756514 RL = 0x3
4990 11:13:04.760012 BL = 0x2
4991 11:13:04.760137 RPST = 0x0
4992 11:13:04.763080 RD_PRE = 0x0
4993 11:13:04.763192 WR_PRE = 0x1
4994 11:13:04.766223 WR_PST = 0x0
4995 11:13:04.766336 DBI_WR = 0x0
4996 11:13:04.769802 DBI_RD = 0x0
4997 11:13:04.769921 OTF = 0x1
4998 11:13:04.772921 ===================================
4999 11:13:04.779433 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5000 11:13:04.782917 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5001 11:13:04.786584 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5002 11:13:04.789760 ===================================
5003 11:13:04.792926 LPDDR4 DRAM CONFIGURATION
5004 11:13:04.795972 ===================================
5005 11:13:04.799724 EX_ROW_EN[0] = 0x10
5006 11:13:04.799841 EX_ROW_EN[1] = 0x0
5007 11:13:04.802779 LP4Y_EN = 0x0
5008 11:13:04.802940 WORK_FSP = 0x0
5009 11:13:04.805877 WL = 0x3
5010 11:13:04.805994 RL = 0x3
5011 11:13:04.809967 BL = 0x2
5012 11:13:04.810089 RPST = 0x0
5013 11:13:04.812859 RD_PRE = 0x0
5014 11:13:04.812980 WR_PRE = 0x1
5015 11:13:04.816073 WR_PST = 0x0
5016 11:13:04.816185 DBI_WR = 0x0
5017 11:13:04.819167 DBI_RD = 0x0
5018 11:13:04.819280 OTF = 0x1
5019 11:13:04.822806 ===================================
5020 11:13:04.829270 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5021 11:13:04.833935 nWR fixed to 30
5022 11:13:04.837031 [ModeRegInit_LP4] CH0 RK0
5023 11:13:04.837143 [ModeRegInit_LP4] CH0 RK1
5024 11:13:04.840406 [ModeRegInit_LP4] CH1 RK0
5025 11:13:04.843796 [ModeRegInit_LP4] CH1 RK1
5026 11:13:04.843915 match AC timing 9
5027 11:13:04.850131 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5028 11:13:04.853543 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5029 11:13:04.856681 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5030 11:13:04.863486 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5031 11:13:04.866986 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5032 11:13:04.867100 ==
5033 11:13:04.870229 Dram Type= 6, Freq= 0, CH_0, rank 0
5034 11:13:04.873540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5035 11:13:04.873652 ==
5036 11:13:04.880148 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5037 11:13:04.886746 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5038 11:13:04.890201 [CA 0] Center 38 (8~69) winsize 62
5039 11:13:04.893311 [CA 1] Center 38 (7~69) winsize 63
5040 11:13:04.896302 [CA 2] Center 35 (5~65) winsize 61
5041 11:13:04.900079 [CA 3] Center 35 (5~65) winsize 61
5042 11:13:04.903328 [CA 4] Center 34 (4~65) winsize 62
5043 11:13:04.906442 [CA 5] Center 33 (3~64) winsize 62
5044 11:13:04.906565
5045 11:13:04.909634 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5046 11:13:04.909743
5047 11:13:04.913166 [CATrainingPosCal] consider 1 rank data
5048 11:13:04.916389 u2DelayCellTimex100 = 270/100 ps
5049 11:13:04.919535 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5050 11:13:04.922736 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5051 11:13:04.926106 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5052 11:13:04.932559 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5053 11:13:04.936133 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5054 11:13:04.939104 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5055 11:13:04.939214
5056 11:13:04.942653 CA PerBit enable=1, Macro0, CA PI delay=33
5057 11:13:04.942763
5058 11:13:04.945698 [CBTSetCACLKResult] CA Dly = 33
5059 11:13:04.945807 CS Dly: 7 (0~38)
5060 11:13:04.945904 ==
5061 11:13:04.949121 Dram Type= 6, Freq= 0, CH_0, rank 1
5062 11:13:04.955714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5063 11:13:04.955830 ==
5064 11:13:04.959119 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5065 11:13:04.965933 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5066 11:13:04.968867 [CA 0] Center 38 (8~69) winsize 62
5067 11:13:04.972714 [CA 1] Center 38 (8~69) winsize 62
5068 11:13:04.975748 [CA 2] Center 35 (5~66) winsize 62
5069 11:13:04.978764 [CA 3] Center 35 (5~66) winsize 62
5070 11:13:04.981807 [CA 4] Center 34 (4~65) winsize 62
5071 11:13:04.985397 [CA 5] Center 33 (3~64) winsize 62
5072 11:13:04.985506
5073 11:13:04.988523 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5074 11:13:04.988638
5075 11:13:04.992135 [CATrainingPosCal] consider 2 rank data
5076 11:13:04.995168 u2DelayCellTimex100 = 270/100 ps
5077 11:13:05.001709 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5078 11:13:05.005501 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5079 11:13:05.008616 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5080 11:13:05.011668 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5081 11:13:05.014798 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5082 11:13:05.018000 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5083 11:13:05.018111
5084 11:13:05.021754 CA PerBit enable=1, Macro0, CA PI delay=33
5085 11:13:05.021868
5086 11:13:05.024928 [CBTSetCACLKResult] CA Dly = 33
5087 11:13:05.028120 CS Dly: 7 (0~39)
5088 11:13:05.028230
5089 11:13:05.031115 ----->DramcWriteLeveling(PI) begin...
5090 11:13:05.031241 ==
5091 11:13:05.034822 Dram Type= 6, Freq= 0, CH_0, rank 0
5092 11:13:05.037947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5093 11:13:05.038058 ==
5094 11:13:05.041347 Write leveling (Byte 0): 32 => 32
5095 11:13:05.044766 Write leveling (Byte 1): 31 => 31
5096 11:13:05.047635 DramcWriteLeveling(PI) end<-----
5097 11:13:05.047754
5098 11:13:05.047909 ==
5099 11:13:05.051297 Dram Type= 6, Freq= 0, CH_0, rank 0
5100 11:13:05.054135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5101 11:13:05.054246 ==
5102 11:13:05.057642 [Gating] SW mode calibration
5103 11:13:05.064188 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5104 11:13:05.070767 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5105 11:13:05.073859 0 14 0 | B1->B0 | 2323 2b2b | 1 0 | (1 1) (0 0)
5106 11:13:05.080530 0 14 4 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
5107 11:13:05.084211 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5108 11:13:05.087193 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5109 11:13:05.093893 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5110 11:13:05.096834 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5111 11:13:05.100517 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5112 11:13:05.107164 0 14 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
5113 11:13:05.110593 0 15 0 | B1->B0 | 3434 2a2a | 1 1 | (1 1) (1 0)
5114 11:13:05.113454 0 15 4 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
5115 11:13:05.120356 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5116 11:13:05.123693 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5117 11:13:05.126711 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5118 11:13:05.133691 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5119 11:13:05.136802 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5120 11:13:05.140012 0 15 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5121 11:13:05.146724 1 0 0 | B1->B0 | 2b2b 3b3b | 0 0 | (0 0) (0 0)
5122 11:13:05.149708 1 0 4 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
5123 11:13:05.152973 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5124 11:13:05.159562 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5125 11:13:05.163058 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5126 11:13:05.166601 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5127 11:13:05.173060 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5128 11:13:05.175983 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5129 11:13:05.179638 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5130 11:13:05.185965 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5131 11:13:05.189078 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 11:13:05.192832 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 11:13:05.199377 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 11:13:05.202708 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 11:13:05.206143 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 11:13:05.212350 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 11:13:05.216205 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 11:13:05.219165 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 11:13:05.225412 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 11:13:05.229280 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 11:13:05.232455 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 11:13:05.238580 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 11:13:05.242447 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 11:13:05.245610 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5145 11:13:05.251909 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5146 11:13:05.255540 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5147 11:13:05.258932 Total UI for P1: 0, mck2ui 16
5148 11:13:05.261757 best dqsien dly found for B0: ( 1, 2, 30)
5149 11:13:05.265296 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5150 11:13:05.268821 Total UI for P1: 0, mck2ui 16
5151 11:13:05.271688 best dqsien dly found for B1: ( 1, 3, 2)
5152 11:13:05.275152 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5153 11:13:05.278153 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5154 11:13:05.278240
5155 11:13:05.284913 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5156 11:13:05.288555 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5157 11:13:05.288639 [Gating] SW calibration Done
5158 11:13:05.291695 ==
5159 11:13:05.294774 Dram Type= 6, Freq= 0, CH_0, rank 0
5160 11:13:05.297918 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5161 11:13:05.298002 ==
5162 11:13:05.298068 RX Vref Scan: 0
5163 11:13:05.298130
5164 11:13:05.301478 RX Vref 0 -> 0, step: 1
5165 11:13:05.301576
5166 11:13:05.304965 RX Delay -80 -> 252, step: 8
5167 11:13:05.308291 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5168 11:13:05.311558 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5169 11:13:05.314578 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5170 11:13:05.321183 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5171 11:13:05.324372 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5172 11:13:05.328100 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5173 11:13:05.331368 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5174 11:13:05.334558 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5175 11:13:05.340798 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5176 11:13:05.344553 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5177 11:13:05.347714 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5178 11:13:05.351119 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5179 11:13:05.354085 iDelay=208, Bit 12, Center 87 (-16 ~ 191) 208
5180 11:13:05.360728 iDelay=208, Bit 13, Center 87 (-16 ~ 191) 208
5181 11:13:05.363769 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5182 11:13:05.367178 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5183 11:13:05.367262 ==
5184 11:13:05.370704 Dram Type= 6, Freq= 0, CH_0, rank 0
5185 11:13:05.373739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5186 11:13:05.377033 ==
5187 11:13:05.377117 DQS Delay:
5188 11:13:05.377181 DQS0 = 0, DQS1 = 0
5189 11:13:05.380113 DQM Delay:
5190 11:13:05.380194 DQM0 = 94, DQM1 = 82
5191 11:13:05.383638 DQ Delay:
5192 11:13:05.387035 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5193 11:13:05.390010 DQ4 =95, DQ5 =79, DQ6 =103, DQ7 =107
5194 11:13:05.393510 DQ8 =75, DQ9 =71, DQ10 =83, DQ11 =75
5195 11:13:05.396615 DQ12 =87, DQ13 =87, DQ14 =91, DQ15 =91
5196 11:13:05.396698
5197 11:13:05.396770
5198 11:13:05.396844 ==
5199 11:13:05.399819 Dram Type= 6, Freq= 0, CH_0, rank 0
5200 11:13:05.403582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5201 11:13:05.403733 ==
5202 11:13:05.403885
5203 11:13:05.404007
5204 11:13:05.406571 TX Vref Scan disable
5205 11:13:05.406685 == TX Byte 0 ==
5206 11:13:05.413186 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5207 11:13:05.416633 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5208 11:13:05.416717 == TX Byte 1 ==
5209 11:13:05.422813 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5210 11:13:05.426486 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5211 11:13:05.426595 ==
5212 11:13:05.429516 Dram Type= 6, Freq= 0, CH_0, rank 0
5213 11:13:05.432707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5214 11:13:05.436508 ==
5215 11:13:05.436590
5216 11:13:05.436654
5217 11:13:05.436736 TX Vref Scan disable
5218 11:13:05.439673 == TX Byte 0 ==
5219 11:13:05.442802 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5220 11:13:05.449279 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5221 11:13:05.449365 == TX Byte 1 ==
5222 11:13:05.452436 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5223 11:13:05.459406 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5224 11:13:05.459492
5225 11:13:05.459557 [DATLAT]
5226 11:13:05.459615 Freq=933, CH0 RK0
5227 11:13:05.459674
5228 11:13:05.462588 DATLAT Default: 0xd
5229 11:13:05.465867 0, 0xFFFF, sum = 0
5230 11:13:05.465951 1, 0xFFFF, sum = 0
5231 11:13:05.469356 2, 0xFFFF, sum = 0
5232 11:13:05.469439 3, 0xFFFF, sum = 0
5233 11:13:05.472484 4, 0xFFFF, sum = 0
5234 11:13:05.472567 5, 0xFFFF, sum = 0
5235 11:13:05.476111 6, 0xFFFF, sum = 0
5236 11:13:05.476194 7, 0xFFFF, sum = 0
5237 11:13:05.479021 8, 0xFFFF, sum = 0
5238 11:13:05.479104 9, 0xFFFF, sum = 0
5239 11:13:05.482576 10, 0x0, sum = 1
5240 11:13:05.482660 11, 0x0, sum = 2
5241 11:13:05.486005 12, 0x0, sum = 3
5242 11:13:05.486087 13, 0x0, sum = 4
5243 11:13:05.488989 best_step = 11
5244 11:13:05.489070
5245 11:13:05.489134 ==
5246 11:13:05.492512 Dram Type= 6, Freq= 0, CH_0, rank 0
5247 11:13:05.495427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5248 11:13:05.495510 ==
5249 11:13:05.495575 RX Vref Scan: 1
5250 11:13:05.498946
5251 11:13:05.499028 RX Vref 0 -> 0, step: 1
5252 11:13:05.499093
5253 11:13:05.502545 RX Delay -69 -> 252, step: 4
5254 11:13:05.502627
5255 11:13:05.505660 Set Vref, RX VrefLevel [Byte0]: 62
5256 11:13:05.508719 [Byte1]: 56
5257 11:13:05.512521
5258 11:13:05.512604 Final RX Vref Byte 0 = 62 to rank0
5259 11:13:05.515663 Final RX Vref Byte 1 = 56 to rank0
5260 11:13:05.518921 Final RX Vref Byte 0 = 62 to rank1
5261 11:13:05.521866 Final RX Vref Byte 1 = 56 to rank1==
5262 11:13:05.525668 Dram Type= 6, Freq= 0, CH_0, rank 0
5263 11:13:05.531837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5264 11:13:05.531922 ==
5265 11:13:05.531988 DQS Delay:
5266 11:13:05.534809 DQS0 = 0, DQS1 = 0
5267 11:13:05.534936 DQM Delay:
5268 11:13:05.535002 DQM0 = 95, DQM1 = 84
5269 11:13:05.538524 DQ Delay:
5270 11:13:05.541602 DQ0 =94, DQ1 =98, DQ2 =94, DQ3 =92
5271 11:13:05.544838 DQ4 =94, DQ5 =84, DQ6 =104, DQ7 =106
5272 11:13:05.548632 DQ8 =78, DQ9 =72, DQ10 =84, DQ11 =80
5273 11:13:05.551791 DQ12 =86, DQ13 =88, DQ14 =96, DQ15 =90
5274 11:13:05.551873
5275 11:13:05.551937
5276 11:13:05.558108 [DQSOSCAuto] RK0, (LSB)MR18= 0x1212, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 416 ps
5277 11:13:05.561289 CH0 RK0: MR19=505, MR18=1212
5278 11:13:05.568201 CH0_RK0: MR19=0x505, MR18=0x1212, DQSOSC=416, MR23=63, INC=62, DEC=41
5279 11:13:05.568311
5280 11:13:05.571381 ----->DramcWriteLeveling(PI) begin...
5281 11:13:05.571479 ==
5282 11:13:05.574419 Dram Type= 6, Freq= 0, CH_0, rank 1
5283 11:13:05.577972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5284 11:13:05.578071 ==
5285 11:13:05.580945 Write leveling (Byte 0): 29 => 29
5286 11:13:05.584562 Write leveling (Byte 1): 29 => 29
5287 11:13:05.587542 DramcWriteLeveling(PI) end<-----
5288 11:13:05.587625
5289 11:13:05.587689 ==
5290 11:13:05.591097 Dram Type= 6, Freq= 0, CH_0, rank 1
5291 11:13:05.597573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5292 11:13:05.597688 ==
5293 11:13:05.597753 [Gating] SW mode calibration
5294 11:13:05.607383 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5295 11:13:05.611074 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5296 11:13:05.617474 0 14 0 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
5297 11:13:05.620882 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5298 11:13:05.623872 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5299 11:13:05.630473 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5300 11:13:05.633586 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5301 11:13:05.637153 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5302 11:13:05.643636 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5303 11:13:05.647265 0 14 28 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 1)
5304 11:13:05.650525 0 15 0 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
5305 11:13:05.656681 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5306 11:13:05.660728 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5307 11:13:05.663674 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5308 11:13:05.670014 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5309 11:13:05.673754 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5310 11:13:05.676818 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5311 11:13:05.683521 0 15 28 | B1->B0 | 2c2c 3434 | 0 0 | (1 1) (0 0)
5312 11:13:05.686534 1 0 0 | B1->B0 | 3b3b 4646 | 0 0 | (0 0) (0 0)
5313 11:13:05.690084 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5314 11:13:05.696511 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5315 11:13:05.700082 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5316 11:13:05.702919 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5317 11:13:05.709454 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5318 11:13:05.712843 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5319 11:13:05.716498 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5320 11:13:05.723182 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 11:13:05.726391 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 11:13:05.729501 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 11:13:05.736150 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 11:13:05.739421 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 11:13:05.742452 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 11:13:05.749389 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 11:13:05.752412 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 11:13:05.756085 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 11:13:05.759175 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 11:13:05.766152 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 11:13:05.769385 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 11:13:05.772518 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 11:13:05.779019 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 11:13:05.782502 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5335 11:13:05.788798 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 11:13:05.791821 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5337 11:13:05.795425 Total UI for P1: 0, mck2ui 16
5338 11:13:05.798496 best dqsien dly found for B0: ( 1, 2, 30)
5339 11:13:05.801987 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5340 11:13:05.805563 Total UI for P1: 0, mck2ui 16
5341 11:13:05.808478 best dqsien dly found for B1: ( 1, 3, 0)
5342 11:13:05.811924 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5343 11:13:05.815010 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5344 11:13:05.815095
5345 11:13:05.818321 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5346 11:13:05.825354 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5347 11:13:05.825437 [Gating] SW calibration Done
5348 11:13:05.825502 ==
5349 11:13:05.828524 Dram Type= 6, Freq= 0, CH_0, rank 1
5350 11:13:05.835437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5351 11:13:05.835546 ==
5352 11:13:05.835644 RX Vref Scan: 0
5353 11:13:05.835735
5354 11:13:05.838195 RX Vref 0 -> 0, step: 1
5355 11:13:05.838299
5356 11:13:05.841303 RX Delay -80 -> 252, step: 8
5357 11:13:05.845095 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5358 11:13:05.848195 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5359 11:13:05.851299 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5360 11:13:05.858341 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5361 11:13:05.861490 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5362 11:13:05.864778 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5363 11:13:05.867922 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5364 11:13:05.871027 iDelay=208, Bit 7, Center 103 (0 ~ 207) 208
5365 11:13:05.874750 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5366 11:13:05.881187 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5367 11:13:05.884319 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5368 11:13:05.887884 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5369 11:13:05.891048 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5370 11:13:05.897927 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5371 11:13:05.900891 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5372 11:13:05.904518 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5373 11:13:05.904608 ==
5374 11:13:05.907457 Dram Type= 6, Freq= 0, CH_0, rank 1
5375 11:13:05.911132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5376 11:13:05.911215 ==
5377 11:13:05.914068 DQS Delay:
5378 11:13:05.914151 DQS0 = 0, DQS1 = 0
5379 11:13:05.917332 DQM Delay:
5380 11:13:05.917452 DQM0 = 91, DQM1 = 83
5381 11:13:05.917517 DQ Delay:
5382 11:13:05.920907 DQ0 =91, DQ1 =91, DQ2 =87, DQ3 =87
5383 11:13:05.923882 DQ4 =91, DQ5 =79, DQ6 =103, DQ7 =103
5384 11:13:05.927046 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =75
5385 11:13:05.930465 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5386 11:13:05.930547
5387 11:13:05.930613
5388 11:13:05.933593 ==
5389 11:13:05.937334 Dram Type= 6, Freq= 0, CH_0, rank 1
5390 11:13:05.940454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5391 11:13:05.940614 ==
5392 11:13:05.940766
5393 11:13:05.940858
5394 11:13:05.943371 TX Vref Scan disable
5395 11:13:05.943454 == TX Byte 0 ==
5396 11:13:05.950068 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5397 11:13:05.953768 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5398 11:13:05.953851 == TX Byte 1 ==
5399 11:13:05.960496 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5400 11:13:05.963163 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5401 11:13:05.963247 ==
5402 11:13:05.966524 Dram Type= 6, Freq= 0, CH_0, rank 1
5403 11:13:05.970205 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5404 11:13:05.970289 ==
5405 11:13:05.970354
5406 11:13:05.970414
5407 11:13:05.973384 TX Vref Scan disable
5408 11:13:05.976530 == TX Byte 0 ==
5409 11:13:05.979779 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5410 11:13:05.982977 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5411 11:13:05.986149 == TX Byte 1 ==
5412 11:13:05.989759 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5413 11:13:05.992811 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5414 11:13:05.992895
5415 11:13:05.996593 [DATLAT]
5416 11:13:05.996691 Freq=933, CH0 RK1
5417 11:13:05.996788
5418 11:13:05.999699 DATLAT Default: 0xb
5419 11:13:05.999788 0, 0xFFFF, sum = 0
5420 11:13:06.002783 1, 0xFFFF, sum = 0
5421 11:13:06.002904 2, 0xFFFF, sum = 0
5422 11:13:06.006392 3, 0xFFFF, sum = 0
5423 11:13:06.006476 4, 0xFFFF, sum = 0
5424 11:13:06.009133 5, 0xFFFF, sum = 0
5425 11:13:06.009264 6, 0xFFFF, sum = 0
5426 11:13:06.012660 7, 0xFFFF, sum = 0
5427 11:13:06.016161 8, 0xFFFF, sum = 0
5428 11:13:06.016248 9, 0xFFFF, sum = 0
5429 11:13:06.019106 10, 0x0, sum = 1
5430 11:13:06.019190 11, 0x0, sum = 2
5431 11:13:06.019257 12, 0x0, sum = 3
5432 11:13:06.022603 13, 0x0, sum = 4
5433 11:13:06.022714 best_step = 11
5434 11:13:06.022820
5435 11:13:06.026053 ==
5436 11:13:06.026137 Dram Type= 6, Freq= 0, CH_0, rank 1
5437 11:13:06.032496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5438 11:13:06.032585 ==
5439 11:13:06.032651 RX Vref Scan: 0
5440 11:13:06.032712
5441 11:13:06.035907 RX Vref 0 -> 0, step: 1
5442 11:13:06.035990
5443 11:13:06.039027 RX Delay -77 -> 252, step: 4
5444 11:13:06.042165 iDelay=199, Bit 0, Center 90 (-5 ~ 186) 192
5445 11:13:06.049079 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5446 11:13:06.052345 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5447 11:13:06.055404 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5448 11:13:06.059194 iDelay=199, Bit 4, Center 90 (-5 ~ 186) 192
5449 11:13:06.062185 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5450 11:13:06.068912 iDelay=199, Bit 6, Center 106 (15 ~ 198) 184
5451 11:13:06.071892 iDelay=199, Bit 7, Center 104 (11 ~ 198) 188
5452 11:13:06.075107 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5453 11:13:06.078303 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180
5454 11:13:06.081483 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5455 11:13:06.088677 iDelay=199, Bit 11, Center 78 (-13 ~ 170) 184
5456 11:13:06.091581 iDelay=199, Bit 12, Center 92 (-1 ~ 186) 188
5457 11:13:06.095247 iDelay=199, Bit 13, Center 88 (-5 ~ 182) 188
5458 11:13:06.098206 iDelay=199, Bit 14, Center 92 (-1 ~ 186) 188
5459 11:13:06.101365 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5460 11:13:06.104532 ==
5461 11:13:06.104611 Dram Type= 6, Freq= 0, CH_0, rank 1
5462 11:13:06.111527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5463 11:13:06.111612 ==
5464 11:13:06.111677 DQS Delay:
5465 11:13:06.114518 DQS0 = 0, DQS1 = 0
5466 11:13:06.114626 DQM Delay:
5467 11:13:06.117844 DQM0 = 92, DQM1 = 85
5468 11:13:06.117927 DQ Delay:
5469 11:13:06.121292 DQ0 =90, DQ1 =94, DQ2 =88, DQ3 =88
5470 11:13:06.124823 DQ4 =90, DQ5 =80, DQ6 =106, DQ7 =104
5471 11:13:06.128361 DQ8 =80, DQ9 =72, DQ10 =86, DQ11 =78
5472 11:13:06.131329 DQ12 =92, DQ13 =88, DQ14 =92, DQ15 =92
5473 11:13:06.131436
5474 11:13:06.131532
5475 11:13:06.137801 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b0c, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 408 ps
5476 11:13:06.141266 CH0 RK1: MR19=505, MR18=2B0C
5477 11:13:06.147352 CH0_RK1: MR19=0x505, MR18=0x2B0C, DQSOSC=408, MR23=63, INC=65, DEC=43
5478 11:13:06.151152 [RxdqsGatingPostProcess] freq 933
5479 11:13:06.157586 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5480 11:13:06.160751 best DQS0 dly(2T, 0.5T) = (0, 10)
5481 11:13:06.164291 best DQS1 dly(2T, 0.5T) = (0, 11)
5482 11:13:06.167356 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5483 11:13:06.170475 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5484 11:13:06.170559 best DQS0 dly(2T, 0.5T) = (0, 10)
5485 11:13:06.173466 best DQS1 dly(2T, 0.5T) = (0, 11)
5486 11:13:06.176937 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5487 11:13:06.180100 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5488 11:13:06.183309 Pre-setting of DQS Precalculation
5489 11:13:06.190307 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5490 11:13:06.190395 ==
5491 11:13:06.193499 Dram Type= 6, Freq= 0, CH_1, rank 0
5492 11:13:06.196569 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5493 11:13:06.196656 ==
5494 11:13:06.203139 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5495 11:13:06.210112 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
5496 11:13:06.213247 [CA 0] Center 36 (7~66) winsize 60
5497 11:13:06.216392 [CA 1] Center 37 (7~68) winsize 62
5498 11:13:06.219967 [CA 2] Center 34 (5~64) winsize 60
5499 11:13:06.223013 [CA 3] Center 34 (4~64) winsize 61
5500 11:13:06.226557 [CA 4] Center 34 (4~64) winsize 61
5501 11:13:06.229553 [CA 5] Center 34 (4~64) winsize 61
5502 11:13:06.229647
5503 11:13:06.232893 [CmdBusTrainingLP45] Vref(ca) range 1: 31
5504 11:13:06.232969
5505 11:13:06.236416 [CATrainingPosCal] consider 1 rank data
5506 11:13:06.239610 u2DelayCellTimex100 = 270/100 ps
5507 11:13:06.242894 CA0 delay=36 (7~66),Diff = 2 PI (12 cell)
5508 11:13:06.246284 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5509 11:13:06.249700 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5510 11:13:06.252546 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5511 11:13:06.256377 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5512 11:13:06.259465 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5513 11:13:06.262519
5514 11:13:06.266566 CA PerBit enable=1, Macro0, CA PI delay=34
5515 11:13:06.266648
5516 11:13:06.269163 [CBTSetCACLKResult] CA Dly = 34
5517 11:13:06.269245 CS Dly: 6 (0~37)
5518 11:13:06.269309 ==
5519 11:13:06.272858 Dram Type= 6, Freq= 0, CH_1, rank 1
5520 11:13:06.275943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5521 11:13:06.276020 ==
5522 11:13:06.282458 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5523 11:13:06.289353 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5524 11:13:06.292483 [CA 0] Center 37 (7~67) winsize 61
5525 11:13:06.295535 [CA 1] Center 37 (7~68) winsize 62
5526 11:13:06.298714 [CA 2] Center 35 (5~65) winsize 61
5527 11:13:06.302401 [CA 3] Center 34 (4~64) winsize 61
5528 11:13:06.305387 [CA 4] Center 34 (4~65) winsize 62
5529 11:13:06.309077 [CA 5] Center 33 (3~64) winsize 62
5530 11:13:06.309183
5531 11:13:06.312302 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5532 11:13:06.312388
5533 11:13:06.315456 [CATrainingPosCal] consider 2 rank data
5534 11:13:06.318637 u2DelayCellTimex100 = 270/100 ps
5535 11:13:06.321677 CA0 delay=36 (7~66),Diff = 2 PI (12 cell)
5536 11:13:06.325284 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5537 11:13:06.328281 CA2 delay=34 (5~64),Diff = 0 PI (0 cell)
5538 11:13:06.334763 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
5539 11:13:06.338718 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5540 11:13:06.341572 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5541 11:13:06.341658
5542 11:13:06.345267 CA PerBit enable=1, Macro0, CA PI delay=34
5543 11:13:06.345369
5544 11:13:06.348416 [CBTSetCACLKResult] CA Dly = 34
5545 11:13:06.348499 CS Dly: 7 (0~39)
5546 11:13:06.348565
5547 11:13:06.351348 ----->DramcWriteLeveling(PI) begin...
5548 11:13:06.354766 ==
5549 11:13:06.354870 Dram Type= 6, Freq= 0, CH_1, rank 0
5550 11:13:06.361476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5551 11:13:06.361562 ==
5552 11:13:06.364651 Write leveling (Byte 0): 27 => 27
5553 11:13:06.367741 Write leveling (Byte 1): 28 => 28
5554 11:13:06.371513 DramcWriteLeveling(PI) end<-----
5555 11:13:06.371597
5556 11:13:06.371676 ==
5557 11:13:06.374740 Dram Type= 6, Freq= 0, CH_1, rank 0
5558 11:13:06.378154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5559 11:13:06.378236 ==
5560 11:13:06.381173 [Gating] SW mode calibration
5561 11:13:06.387877 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5562 11:13:06.394612 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5563 11:13:06.397807 0 14 0 | B1->B0 | 3333 3030 | 1 1 | (1 1) (0 0)
5564 11:13:06.400894 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5565 11:13:06.407646 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5566 11:13:06.410748 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5567 11:13:06.414040 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5568 11:13:06.420865 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5569 11:13:06.424033 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5570 11:13:06.427180 0 14 28 | B1->B0 | 3030 3030 | 0 0 | (0 0) (0 0)
5571 11:13:06.434040 0 15 0 | B1->B0 | 2424 2727 | 0 0 | (0 0) (1 0)
5572 11:13:06.436961 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5573 11:13:06.440532 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5574 11:13:06.446721 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5575 11:13:06.450169 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5576 11:13:06.453568 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5577 11:13:06.460179 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5578 11:13:06.463101 0 15 28 | B1->B0 | 3232 3232 | 0 0 | (1 1) (0 0)
5579 11:13:06.466815 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5580 11:13:06.473426 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5581 11:13:06.476491 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5582 11:13:06.479661 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5583 11:13:06.486191 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5584 11:13:06.489877 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5585 11:13:06.492976 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5586 11:13:06.499721 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5587 11:13:06.502797 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5588 11:13:06.505872 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 11:13:06.512773 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 11:13:06.515974 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 11:13:06.519155 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 11:13:06.526180 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 11:13:06.529374 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 11:13:06.532473 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 11:13:06.539349 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 11:13:06.542236 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 11:13:06.545577 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 11:13:06.552240 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 11:13:06.555842 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 11:13:06.559244 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 11:13:06.566132 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 11:13:06.568897 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5603 11:13:06.572555 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5604 11:13:06.578993 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5605 11:13:06.579079 Total UI for P1: 0, mck2ui 16
5606 11:13:06.585257 best dqsien dly found for B0: ( 1, 2, 30)
5607 11:13:06.585342 Total UI for P1: 0, mck2ui 16
5608 11:13:06.592356 best dqsien dly found for B1: ( 1, 2, 30)
5609 11:13:06.595665 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5610 11:13:06.598768 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5611 11:13:06.598914
5612 11:13:06.601858 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5613 11:13:06.605390 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5614 11:13:06.608415 [Gating] SW calibration Done
5615 11:13:06.608508 ==
5616 11:13:06.611716 Dram Type= 6, Freq= 0, CH_1, rank 0
5617 11:13:06.614738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5618 11:13:06.614883 ==
5619 11:13:06.618487 RX Vref Scan: 0
5620 11:13:06.618569
5621 11:13:06.618634 RX Vref 0 -> 0, step: 1
5622 11:13:06.618695
5623 11:13:06.621628 RX Delay -80 -> 252, step: 8
5624 11:13:06.624885 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5625 11:13:06.631795 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5626 11:13:06.635232 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5627 11:13:06.638102 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5628 11:13:06.641520 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5629 11:13:06.645073 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5630 11:13:06.648051 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5631 11:13:06.654670 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5632 11:13:06.658450 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5633 11:13:06.661355 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5634 11:13:06.664579 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5635 11:13:06.668033 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5636 11:13:06.674202 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5637 11:13:06.677831 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5638 11:13:06.681109 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5639 11:13:06.684071 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5640 11:13:06.684184 ==
5641 11:13:06.687756 Dram Type= 6, Freq= 0, CH_1, rank 0
5642 11:13:06.691068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5643 11:13:06.694463 ==
5644 11:13:06.694547 DQS Delay:
5645 11:13:06.694615 DQS0 = 0, DQS1 = 0
5646 11:13:06.697540 DQM Delay:
5647 11:13:06.697650 DQM0 = 94, DQM1 = 90
5648 11:13:06.700893 DQ Delay:
5649 11:13:06.704114 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =91
5650 11:13:06.707138 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5651 11:13:06.710656 DQ8 =83, DQ9 =83, DQ10 =91, DQ11 =83
5652 11:13:06.713678 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5653 11:13:06.713772
5654 11:13:06.713840
5655 11:13:06.713901 ==
5656 11:13:06.716902 Dram Type= 6, Freq= 0, CH_1, rank 0
5657 11:13:06.720408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5658 11:13:06.720494 ==
5659 11:13:06.720559
5660 11:13:06.720621
5661 11:13:06.723671 TX Vref Scan disable
5662 11:13:06.723787 == TX Byte 0 ==
5663 11:13:06.730604 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5664 11:13:06.733760 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5665 11:13:06.733852 == TX Byte 1 ==
5666 11:13:06.740036 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5667 11:13:06.743329 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5668 11:13:06.743406 ==
5669 11:13:06.746522 Dram Type= 6, Freq= 0, CH_1, rank 0
5670 11:13:06.750210 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5671 11:13:06.750294 ==
5672 11:13:06.753379
5673 11:13:06.753462
5674 11:13:06.753527 TX Vref Scan disable
5675 11:13:06.756849 == TX Byte 0 ==
5676 11:13:06.759714 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5677 11:13:06.766701 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5678 11:13:06.766786 == TX Byte 1 ==
5679 11:13:06.769823 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5680 11:13:06.776254 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5681 11:13:06.776338
5682 11:13:06.776403 [DATLAT]
5683 11:13:06.776463 Freq=933, CH1 RK0
5684 11:13:06.776522
5685 11:13:06.779768 DATLAT Default: 0xd
5686 11:13:06.783358 0, 0xFFFF, sum = 0
5687 11:13:06.783446 1, 0xFFFF, sum = 0
5688 11:13:06.786306 2, 0xFFFF, sum = 0
5689 11:13:06.786390 3, 0xFFFF, sum = 0
5690 11:13:06.789467 4, 0xFFFF, sum = 0
5691 11:13:06.789568 5, 0xFFFF, sum = 0
5692 11:13:06.793005 6, 0xFFFF, sum = 0
5693 11:13:06.793090 7, 0xFFFF, sum = 0
5694 11:13:06.796177 8, 0xFFFF, sum = 0
5695 11:13:06.796261 9, 0xFFFF, sum = 0
5696 11:13:06.799277 10, 0x0, sum = 1
5697 11:13:06.799363 11, 0x0, sum = 2
5698 11:13:06.802741 12, 0x0, sum = 3
5699 11:13:06.802850 13, 0x0, sum = 4
5700 11:13:06.806071 best_step = 11
5701 11:13:06.806156
5702 11:13:06.806221 ==
5703 11:13:06.809043 Dram Type= 6, Freq= 0, CH_1, rank 0
5704 11:13:06.812794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5705 11:13:06.812878 ==
5706 11:13:06.812943 RX Vref Scan: 1
5707 11:13:06.815747
5708 11:13:06.815831 RX Vref 0 -> 0, step: 1
5709 11:13:06.815897
5710 11:13:06.819476 RX Delay -53 -> 252, step: 4
5711 11:13:06.819577
5712 11:13:06.822553 Set Vref, RX VrefLevel [Byte0]: 57
5713 11:13:06.825573 [Byte1]: 53
5714 11:13:06.829355
5715 11:13:06.829454 Final RX Vref Byte 0 = 57 to rank0
5716 11:13:06.832548 Final RX Vref Byte 1 = 53 to rank0
5717 11:13:06.835721 Final RX Vref Byte 0 = 57 to rank1
5718 11:13:06.838980 Final RX Vref Byte 1 = 53 to rank1==
5719 11:13:06.842108 Dram Type= 6, Freq= 0, CH_1, rank 0
5720 11:13:06.849048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5721 11:13:06.849133 ==
5722 11:13:06.849199 DQS Delay:
5723 11:13:06.852197 DQS0 = 0, DQS1 = 0
5724 11:13:06.852280 DQM Delay:
5725 11:13:06.852344 DQM0 = 96, DQM1 = 88
5726 11:13:06.855491 DQ Delay:
5727 11:13:06.858706 DQ0 =102, DQ1 =90, DQ2 =86, DQ3 =92
5728 11:13:06.862300 DQ4 =94, DQ5 =106, DQ6 =108, DQ7 =94
5729 11:13:06.865167 DQ8 =76, DQ9 =80, DQ10 =88, DQ11 =82
5730 11:13:06.868848 DQ12 =96, DQ13 =94, DQ14 =94, DQ15 =94
5731 11:13:06.868932
5732 11:13:06.868996
5733 11:13:06.875412 [DQSOSCAuto] RK0, (LSB)MR18= 0x9, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 422 ps
5734 11:13:06.878776 CH1 RK0: MR19=505, MR18=9
5735 11:13:06.885152 CH1_RK0: MR19=0x505, MR18=0x9, DQSOSC=419, MR23=63, INC=61, DEC=41
5736 11:13:06.885265
5737 11:13:06.888552 ----->DramcWriteLeveling(PI) begin...
5738 11:13:06.888642 ==
5739 11:13:06.891562 Dram Type= 6, Freq= 0, CH_1, rank 1
5740 11:13:06.895053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5741 11:13:06.895146 ==
5742 11:13:06.898514 Write leveling (Byte 0): 27 => 27
5743 11:13:06.901738 Write leveling (Byte 1): 29 => 29
5744 11:13:06.904921 DramcWriteLeveling(PI) end<-----
5745 11:13:06.905062
5746 11:13:06.905157 ==
5747 11:13:06.908124 Dram Type= 6, Freq= 0, CH_1, rank 1
5748 11:13:06.911722 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5749 11:13:06.911837 ==
5750 11:13:06.914758 [Gating] SW mode calibration
5751 11:13:06.921196 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5752 11:13:06.928122 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5753 11:13:06.931179 0 14 0 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5754 11:13:06.938091 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5755 11:13:06.941351 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5756 11:13:06.944495 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5757 11:13:06.951365 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5758 11:13:06.954566 0 14 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5759 11:13:06.957679 0 14 24 | B1->B0 | 3232 2f2f | 1 0 | (1 1) (1 0)
5760 11:13:06.964523 0 14 28 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5761 11:13:06.967501 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5762 11:13:06.971016 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5763 11:13:06.977714 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5764 11:13:06.980735 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5765 11:13:06.984240 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5766 11:13:06.990649 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5767 11:13:06.994243 0 15 24 | B1->B0 | 2929 3333 | 0 1 | (0 0) (0 0)
5768 11:13:06.997310 0 15 28 | B1->B0 | 3c3b 4646 | 1 0 | (0 0) (0 0)
5769 11:13:07.003754 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5770 11:13:07.007656 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5771 11:13:07.010480 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5772 11:13:07.017273 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5773 11:13:07.020293 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5774 11:13:07.023645 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5775 11:13:07.030093 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5776 11:13:07.033718 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5777 11:13:07.036815 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 11:13:07.043310 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 11:13:07.046460 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 11:13:07.050240 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 11:13:07.056542 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 11:13:07.059761 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 11:13:07.063003 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 11:13:07.069756 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 11:13:07.072839 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 11:13:07.076499 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 11:13:07.082636 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 11:13:07.086300 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 11:13:07.089292 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 11:13:07.095874 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 11:13:07.099315 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5792 11:13:07.102333 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5793 11:13:07.105621 Total UI for P1: 0, mck2ui 16
5794 11:13:07.109167 best dqsien dly found for B0: ( 1, 2, 24)
5795 11:13:07.112337 Total UI for P1: 0, mck2ui 16
5796 11:13:07.115952 best dqsien dly found for B1: ( 1, 2, 26)
5797 11:13:07.119199 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5798 11:13:07.122052 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5799 11:13:07.122168
5800 11:13:07.128885 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5801 11:13:07.131987 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5802 11:13:07.132113 [Gating] SW calibration Done
5803 11:13:07.135586 ==
5804 11:13:07.138555 Dram Type= 6, Freq= 0, CH_1, rank 1
5805 11:13:07.142011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5806 11:13:07.142124 ==
5807 11:13:07.142219 RX Vref Scan: 0
5808 11:13:07.142309
5809 11:13:07.145170 RX Vref 0 -> 0, step: 1
5810 11:13:07.145253
5811 11:13:07.148924 RX Delay -80 -> 252, step: 8
5812 11:13:07.152022 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5813 11:13:07.155132 iDelay=208, Bit 1, Center 87 (-8 ~ 183) 192
5814 11:13:07.158233 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5815 11:13:07.165423 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5816 11:13:07.168390 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5817 11:13:07.171500 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5818 11:13:07.175097 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5819 11:13:07.178815 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5820 11:13:07.184872 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5821 11:13:07.188518 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5822 11:13:07.191480 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5823 11:13:07.194537 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5824 11:13:07.198170 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5825 11:13:07.204723 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5826 11:13:07.208250 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5827 11:13:07.211117 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5828 11:13:07.211196 ==
5829 11:13:07.214687 Dram Type= 6, Freq= 0, CH_1, rank 1
5830 11:13:07.218193 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5831 11:13:07.218282 ==
5832 11:13:07.221255 DQS Delay:
5833 11:13:07.221341 DQS0 = 0, DQS1 = 0
5834 11:13:07.224810 DQM Delay:
5835 11:13:07.224896 DQM0 = 94, DQM1 = 89
5836 11:13:07.224981 DQ Delay:
5837 11:13:07.227948 DQ0 =99, DQ1 =87, DQ2 =83, DQ3 =91
5838 11:13:07.231044 DQ4 =91, DQ5 =103, DQ6 =107, DQ7 =91
5839 11:13:07.234104 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5840 11:13:07.237657 DQ12 =99, DQ13 =99, DQ14 =91, DQ15 =91
5841 11:13:07.237743
5842 11:13:07.240819
5843 11:13:07.240904 ==
5844 11:13:07.244457 Dram Type= 6, Freq= 0, CH_1, rank 1
5845 11:13:07.247307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5846 11:13:07.247394 ==
5847 11:13:07.247479
5848 11:13:07.247575
5849 11:13:07.250957 TX Vref Scan disable
5850 11:13:07.251042 == TX Byte 0 ==
5851 11:13:07.257273 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5852 11:13:07.260381 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5853 11:13:07.260467 == TX Byte 1 ==
5854 11:13:07.267203 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5855 11:13:07.270377 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5856 11:13:07.270462 ==
5857 11:13:07.273590 Dram Type= 6, Freq= 0, CH_1, rank 1
5858 11:13:07.276702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5859 11:13:07.276834 ==
5860 11:13:07.276918
5861 11:13:07.276998
5862 11:13:07.280275 TX Vref Scan disable
5863 11:13:07.283739 == TX Byte 0 ==
5864 11:13:07.286883 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5865 11:13:07.289962 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5866 11:13:07.293099 == TX Byte 1 ==
5867 11:13:07.296598 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5868 11:13:07.299761 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5869 11:13:07.303253
5870 11:13:07.303344 [DATLAT]
5871 11:13:07.303430 Freq=933, CH1 RK1
5872 11:13:07.303511
5873 11:13:07.306630 DATLAT Default: 0xb
5874 11:13:07.306716 0, 0xFFFF, sum = 0
5875 11:13:07.309528 1, 0xFFFF, sum = 0
5876 11:13:07.309616 2, 0xFFFF, sum = 0
5877 11:13:07.313103 3, 0xFFFF, sum = 0
5878 11:13:07.316638 4, 0xFFFF, sum = 0
5879 11:13:07.316727 5, 0xFFFF, sum = 0
5880 11:13:07.319446 6, 0xFFFF, sum = 0
5881 11:13:07.319535 7, 0xFFFF, sum = 0
5882 11:13:07.322834 8, 0xFFFF, sum = 0
5883 11:13:07.322925 9, 0xFFFF, sum = 0
5884 11:13:07.326467 10, 0x0, sum = 1
5885 11:13:07.326553 11, 0x0, sum = 2
5886 11:13:07.329507 12, 0x0, sum = 3
5887 11:13:07.329594 13, 0x0, sum = 4
5888 11:13:07.329681 best_step = 11
5889 11:13:07.329761
5890 11:13:07.332641 ==
5891 11:13:07.336104 Dram Type= 6, Freq= 0, CH_1, rank 1
5892 11:13:07.339549 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5893 11:13:07.339634 ==
5894 11:13:07.339719 RX Vref Scan: 0
5895 11:13:07.339800
5896 11:13:07.342501 RX Vref 0 -> 0, step: 1
5897 11:13:07.342586
5898 11:13:07.346216 RX Delay -61 -> 252, step: 4
5899 11:13:07.352318 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5900 11:13:07.355806 iDelay=203, Bit 1, Center 88 (-5 ~ 182) 188
5901 11:13:07.359023 iDelay=203, Bit 2, Center 84 (-9 ~ 178) 188
5902 11:13:07.362804 iDelay=203, Bit 3, Center 90 (-5 ~ 186) 192
5903 11:13:07.366003 iDelay=203, Bit 4, Center 90 (-5 ~ 186) 192
5904 11:13:07.369087 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5905 11:13:07.375924 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5906 11:13:07.379010 iDelay=203, Bit 7, Center 90 (-5 ~ 186) 192
5907 11:13:07.382369 iDelay=203, Bit 8, Center 78 (-17 ~ 174) 192
5908 11:13:07.385773 iDelay=203, Bit 9, Center 80 (-13 ~ 174) 188
5909 11:13:07.388793 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5910 11:13:07.395117 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
5911 11:13:07.398995 iDelay=203, Bit 12, Center 98 (7 ~ 190) 184
5912 11:13:07.401944 iDelay=203, Bit 13, Center 98 (3 ~ 194) 192
5913 11:13:07.405483 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5914 11:13:07.408506 iDelay=203, Bit 15, Center 96 (3 ~ 190) 188
5915 11:13:07.408599 ==
5916 11:13:07.412095 Dram Type= 6, Freq= 0, CH_1, rank 1
5917 11:13:07.418619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5918 11:13:07.418706 ==
5919 11:13:07.418809 DQS Delay:
5920 11:13:07.421555 DQS0 = 0, DQS1 = 0
5921 11:13:07.421641 DQM Delay:
5922 11:13:07.425067 DQM0 = 93, DQM1 = 90
5923 11:13:07.425153 DQ Delay:
5924 11:13:07.428024 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =90
5925 11:13:07.431446 DQ4 =90, DQ5 =102, DQ6 =106, DQ7 =90
5926 11:13:07.435008 DQ8 =78, DQ9 =80, DQ10 =92, DQ11 =84
5927 11:13:07.438115 DQ12 =98, DQ13 =98, DQ14 =98, DQ15 =96
5928 11:13:07.438200
5929 11:13:07.438285
5930 11:13:07.444967 [DQSOSCAuto] RK1, (LSB)MR18= 0xa1f, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 418 ps
5931 11:13:07.447827 CH1 RK1: MR19=505, MR18=A1F
5932 11:13:07.454799 CH1_RK1: MR19=0x505, MR18=0xA1F, DQSOSC=412, MR23=63, INC=63, DEC=42
5933 11:13:07.457721 [RxdqsGatingPostProcess] freq 933
5934 11:13:07.464516 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5935 11:13:07.464615 best DQS0 dly(2T, 0.5T) = (0, 10)
5936 11:13:07.467697 best DQS1 dly(2T, 0.5T) = (0, 10)
5937 11:13:07.471435 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5938 11:13:07.474567 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5939 11:13:07.477798 best DQS0 dly(2T, 0.5T) = (0, 10)
5940 11:13:07.481028 best DQS1 dly(2T, 0.5T) = (0, 10)
5941 11:13:07.484341 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5942 11:13:07.487677 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5943 11:13:07.490725 Pre-setting of DQS Precalculation
5944 11:13:07.497548 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5945 11:13:07.503984 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5946 11:13:07.510405 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5947 11:13:07.510496
5948 11:13:07.510597
5949 11:13:07.513933 [Calibration Summary] 1866 Mbps
5950 11:13:07.514018 CH 0, Rank 0
5951 11:13:07.516889 SW Impedance : PASS
5952 11:13:07.520492 DUTY Scan : NO K
5953 11:13:07.520577 ZQ Calibration : PASS
5954 11:13:07.523807 Jitter Meter : NO K
5955 11:13:07.526863 CBT Training : PASS
5956 11:13:07.526962 Write leveling : PASS
5957 11:13:07.530287 RX DQS gating : PASS
5958 11:13:07.533786 RX DQ/DQS(RDDQC) : PASS
5959 11:13:07.533873 TX DQ/DQS : PASS
5960 11:13:07.536675 RX DATLAT : PASS
5961 11:13:07.540302 RX DQ/DQS(Engine): PASS
5962 11:13:07.540389 TX OE : NO K
5963 11:13:07.540474 All Pass.
5964 11:13:07.543349
5965 11:13:07.543434 CH 0, Rank 1
5966 11:13:07.546497 SW Impedance : PASS
5967 11:13:07.546582 DUTY Scan : NO K
5968 11:13:07.550211 ZQ Calibration : PASS
5969 11:13:07.550297 Jitter Meter : NO K
5970 11:13:07.553308 CBT Training : PASS
5971 11:13:07.556991 Write leveling : PASS
5972 11:13:07.557077 RX DQS gating : PASS
5973 11:13:07.559846 RX DQ/DQS(RDDQC) : PASS
5974 11:13:07.562866 TX DQ/DQS : PASS
5975 11:13:07.562966 RX DATLAT : PASS
5976 11:13:07.566631 RX DQ/DQS(Engine): PASS
5977 11:13:07.569615 TX OE : NO K
5978 11:13:07.569701 All Pass.
5979 11:13:07.569786
5980 11:13:07.569867 CH 1, Rank 0
5981 11:13:07.572746 SW Impedance : PASS
5982 11:13:07.576479 DUTY Scan : NO K
5983 11:13:07.576564 ZQ Calibration : PASS
5984 11:13:07.579545 Jitter Meter : NO K
5985 11:13:07.582600 CBT Training : PASS
5986 11:13:07.582684 Write leveling : PASS
5987 11:13:07.586099 RX DQS gating : PASS
5988 11:13:07.589502 RX DQ/DQS(RDDQC) : PASS
5989 11:13:07.589591 TX DQ/DQS : PASS
5990 11:13:07.592666 RX DATLAT : PASS
5991 11:13:07.596513 RX DQ/DQS(Engine): PASS
5992 11:13:07.596599 TX OE : NO K
5993 11:13:07.599415 All Pass.
5994 11:13:07.599500
5995 11:13:07.599584 CH 1, Rank 1
5996 11:13:07.602540 SW Impedance : PASS
5997 11:13:07.602625 DUTY Scan : NO K
5998 11:13:07.605920 ZQ Calibration : PASS
5999 11:13:07.609670 Jitter Meter : NO K
6000 11:13:07.609757 CBT Training : PASS
6001 11:13:07.612590 Write leveling : PASS
6002 11:13:07.615643 RX DQS gating : PASS
6003 11:13:07.615726 RX DQ/DQS(RDDQC) : PASS
6004 11:13:07.619265 TX DQ/DQS : PASS
6005 11:13:07.622550 RX DATLAT : PASS
6006 11:13:07.622632 RX DQ/DQS(Engine): PASS
6007 11:13:07.625478 TX OE : NO K
6008 11:13:07.625562 All Pass.
6009 11:13:07.625627
6010 11:13:07.629013 DramC Write-DBI off
6011 11:13:07.632378 PER_BANK_REFRESH: Hybrid Mode
6012 11:13:07.632461 TX_TRACKING: ON
6013 11:13:07.642260 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6014 11:13:07.645258 [FAST_K] Save calibration result to emmc
6015 11:13:07.648848 dramc_set_vcore_voltage set vcore to 650000
6016 11:13:07.651886 Read voltage for 400, 6
6017 11:13:07.651969 Vio18 = 0
6018 11:13:07.652035 Vcore = 650000
6019 11:13:07.655699 Vdram = 0
6020 11:13:07.655782 Vddq = 0
6021 11:13:07.655846 Vmddr = 0
6022 11:13:07.661713 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6023 11:13:07.665486 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6024 11:13:07.668391 MEM_TYPE=3, freq_sel=20
6025 11:13:07.671635 sv_algorithm_assistance_LP4_800
6026 11:13:07.675070 ============ PULL DRAM RESETB DOWN ============
6027 11:13:07.678217 ========== PULL DRAM RESETB DOWN end =========
6028 11:13:07.685193 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6029 11:13:07.688369 ===================================
6030 11:13:07.688481 LPDDR4 DRAM CONFIGURATION
6031 11:13:07.691342 ===================================
6032 11:13:07.695183 EX_ROW_EN[0] = 0x0
6033 11:13:07.698270 EX_ROW_EN[1] = 0x0
6034 11:13:07.698375 LP4Y_EN = 0x0
6035 11:13:07.701313 WORK_FSP = 0x0
6036 11:13:07.701417 WL = 0x2
6037 11:13:07.704574 RL = 0x2
6038 11:13:07.704679 BL = 0x2
6039 11:13:07.708394 RPST = 0x0
6040 11:13:07.708472 RD_PRE = 0x0
6041 11:13:07.711519 WR_PRE = 0x1
6042 11:13:07.711616 WR_PST = 0x0
6043 11:13:07.714615 DBI_WR = 0x0
6044 11:13:07.714699 DBI_RD = 0x0
6045 11:13:07.717826 OTF = 0x1
6046 11:13:07.721590 ===================================
6047 11:13:07.724701 ===================================
6048 11:13:07.724786 ANA top config
6049 11:13:07.728181 ===================================
6050 11:13:07.731125 DLL_ASYNC_EN = 0
6051 11:13:07.734569 ALL_SLAVE_EN = 1
6052 11:13:07.737982 NEW_RANK_MODE = 1
6053 11:13:07.741054 DLL_IDLE_MODE = 1
6054 11:13:07.741138 LP45_APHY_COMB_EN = 1
6055 11:13:07.744521 TX_ODT_DIS = 1
6056 11:13:07.747566 NEW_8X_MODE = 1
6057 11:13:07.751063 ===================================
6058 11:13:07.754563 ===================================
6059 11:13:07.757427 data_rate = 800
6060 11:13:07.761189 CKR = 1
6061 11:13:07.761300 DQ_P2S_RATIO = 4
6062 11:13:07.764209 ===================================
6063 11:13:07.767667 CA_P2S_RATIO = 4
6064 11:13:07.770855 DQ_CA_OPEN = 0
6065 11:13:07.773881 DQ_SEMI_OPEN = 1
6066 11:13:07.777609 CA_SEMI_OPEN = 1
6067 11:13:07.780573 CA_FULL_RATE = 0
6068 11:13:07.780658 DQ_CKDIV4_EN = 0
6069 11:13:07.784494 CA_CKDIV4_EN = 1
6070 11:13:07.787417 CA_PREDIV_EN = 0
6071 11:13:07.790566 PH8_DLY = 0
6072 11:13:07.794257 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6073 11:13:07.797290 DQ_AAMCK_DIV = 0
6074 11:13:07.797399 CA_AAMCK_DIV = 0
6075 11:13:07.800393 CA_ADMCK_DIV = 4
6076 11:13:07.804003 DQ_TRACK_CA_EN = 0
6077 11:13:07.807427 CA_PICK = 800
6078 11:13:07.810408 CA_MCKIO = 400
6079 11:13:07.813459 MCKIO_SEMI = 400
6080 11:13:07.816733 PLL_FREQ = 3016
6081 11:13:07.820440 DQ_UI_PI_RATIO = 32
6082 11:13:07.820551 CA_UI_PI_RATIO = 32
6083 11:13:07.823603 ===================================
6084 11:13:07.826637 ===================================
6085 11:13:07.830456 memory_type:LPDDR4
6086 11:13:07.833427 GP_NUM : 10
6087 11:13:07.833542 SRAM_EN : 1
6088 11:13:07.836543 MD32_EN : 0
6089 11:13:07.840055 ===================================
6090 11:13:07.843465 [ANA_INIT] >>>>>>>>>>>>>>
6091 11:13:07.846424 <<<<<< [CONFIGURE PHASE]: ANA_TX
6092 11:13:07.849898 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6093 11:13:07.853207 ===================================
6094 11:13:07.853293 data_rate = 800,PCW = 0X7400
6095 11:13:07.856689 ===================================
6096 11:13:07.859604 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6097 11:13:07.866624 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6098 11:13:07.879417 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6099 11:13:07.883040 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6100 11:13:07.886048 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6101 11:13:07.889715 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6102 11:13:07.892988 [ANA_INIT] flow start
6103 11:13:07.893072 [ANA_INIT] PLL >>>>>>>>
6104 11:13:07.896066 [ANA_INIT] PLL <<<<<<<<
6105 11:13:07.899221 [ANA_INIT] MIDPI >>>>>>>>
6106 11:13:07.902390 [ANA_INIT] MIDPI <<<<<<<<
6107 11:13:07.902473 [ANA_INIT] DLL >>>>>>>>
6108 11:13:07.906057 [ANA_INIT] flow end
6109 11:13:07.908980 ============ LP4 DIFF to SE enter ============
6110 11:13:07.912945 ============ LP4 DIFF to SE exit ============
6111 11:13:07.915952 [ANA_INIT] <<<<<<<<<<<<<
6112 11:13:07.919020 [Flow] Enable top DCM control >>>>>
6113 11:13:07.922201 [Flow] Enable top DCM control <<<<<
6114 11:13:07.925369 Enable DLL master slave shuffle
6115 11:13:07.932299 ==============================================================
6116 11:13:07.932383 Gating Mode config
6117 11:13:07.938544 ==============================================================
6118 11:13:07.938628 Config description:
6119 11:13:07.948831 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6120 11:13:07.955614 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6121 11:13:07.962068 SELPH_MODE 0: By rank 1: By Phase
6122 11:13:07.965072 ==============================================================
6123 11:13:07.968617 GAT_TRACK_EN = 0
6124 11:13:07.972057 RX_GATING_MODE = 2
6125 11:13:07.975065 RX_GATING_TRACK_MODE = 2
6126 11:13:07.978475 SELPH_MODE = 1
6127 11:13:07.981979 PICG_EARLY_EN = 1
6128 11:13:07.985409 VALID_LAT_VALUE = 1
6129 11:13:07.991678 ==============================================================
6130 11:13:07.995108 Enter into Gating configuration >>>>
6131 11:13:07.997989 Exit from Gating configuration <<<<
6132 11:13:08.001688 Enter into DVFS_PRE_config >>>>>
6133 11:13:08.011129 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6134 11:13:08.014733 Exit from DVFS_PRE_config <<<<<
6135 11:13:08.017835 Enter into PICG configuration >>>>
6136 11:13:08.020967 Exit from PICG configuration <<<<
6137 11:13:08.024815 [RX_INPUT] configuration >>>>>
6138 11:13:08.027888 [RX_INPUT] configuration <<<<<
6139 11:13:08.030980 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6140 11:13:08.038262 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6141 11:13:08.044457 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6142 11:13:08.047456 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6143 11:13:08.054095 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6144 11:13:08.060709 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6145 11:13:08.064146 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6146 11:13:08.070536 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6147 11:13:08.073582 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6148 11:13:08.077056 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6149 11:13:08.080517 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6150 11:13:08.087035 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6151 11:13:08.089922 ===================================
6152 11:13:08.093404 LPDDR4 DRAM CONFIGURATION
6153 11:13:08.096412 ===================================
6154 11:13:08.096537 EX_ROW_EN[0] = 0x0
6155 11:13:08.100075 EX_ROW_EN[1] = 0x0
6156 11:13:08.100237 LP4Y_EN = 0x0
6157 11:13:08.103056 WORK_FSP = 0x0
6158 11:13:08.103229 WL = 0x2
6159 11:13:08.106814 RL = 0x2
6160 11:13:08.106973 BL = 0x2
6161 11:13:08.110011 RPST = 0x0
6162 11:13:08.110193 RD_PRE = 0x0
6163 11:13:08.113145 WR_PRE = 0x1
6164 11:13:08.113271 WR_PST = 0x0
6165 11:13:08.116715 DBI_WR = 0x0
6166 11:13:08.119744 DBI_RD = 0x0
6167 11:13:08.119849 OTF = 0x1
6168 11:13:08.122867 ===================================
6169 11:13:08.126033 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6170 11:13:08.129764 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6171 11:13:08.136562 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6172 11:13:08.139798 ===================================
6173 11:13:08.143124 LPDDR4 DRAM CONFIGURATION
6174 11:13:08.146406 ===================================
6175 11:13:08.146519 EX_ROW_EN[0] = 0x10
6176 11:13:08.149517 EX_ROW_EN[1] = 0x0
6177 11:13:08.149625 LP4Y_EN = 0x0
6178 11:13:08.152675 WORK_FSP = 0x0
6179 11:13:08.152793 WL = 0x2
6180 11:13:08.156339 RL = 0x2
6181 11:13:08.156449 BL = 0x2
6182 11:13:08.159155 RPST = 0x0
6183 11:13:08.159236 RD_PRE = 0x0
6184 11:13:08.162835 WR_PRE = 0x1
6185 11:13:08.166045 WR_PST = 0x0
6186 11:13:08.166132 DBI_WR = 0x0
6187 11:13:08.168984 DBI_RD = 0x0
6188 11:13:08.169085 OTF = 0x1
6189 11:13:08.172461 ===================================
6190 11:13:08.178750 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6191 11:13:08.182843 nWR fixed to 30
6192 11:13:08.185799 [ModeRegInit_LP4] CH0 RK0
6193 11:13:08.185889 [ModeRegInit_LP4] CH0 RK1
6194 11:13:08.189310 [ModeRegInit_LP4] CH1 RK0
6195 11:13:08.192411 [ModeRegInit_LP4] CH1 RK1
6196 11:13:08.192528 match AC timing 19
6197 11:13:08.199378 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6198 11:13:08.202249 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6199 11:13:08.205758 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6200 11:13:08.212429 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6201 11:13:08.215472 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6202 11:13:08.215558 ==
6203 11:13:08.219068 Dram Type= 6, Freq= 0, CH_0, rank 0
6204 11:13:08.221914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6205 11:13:08.225582 ==
6206 11:13:08.228698 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6207 11:13:08.235232 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6208 11:13:08.238613 [CA 0] Center 36 (8~64) winsize 57
6209 11:13:08.241762 [CA 1] Center 36 (8~64) winsize 57
6210 11:13:08.244910 [CA 2] Center 36 (8~64) winsize 57
6211 11:13:08.248508 [CA 3] Center 36 (8~64) winsize 57
6212 11:13:08.251624 [CA 4] Center 36 (8~64) winsize 57
6213 11:13:08.254785 [CA 5] Center 36 (8~64) winsize 57
6214 11:13:08.254890
6215 11:13:08.257913 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6216 11:13:08.257996
6217 11:13:08.261628 [CATrainingPosCal] consider 1 rank data
6218 11:13:08.264655 u2DelayCellTimex100 = 270/100 ps
6219 11:13:08.268657 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6220 11:13:08.271483 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6221 11:13:08.274533 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6222 11:13:08.278157 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6223 11:13:08.281022 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6224 11:13:08.284471 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6225 11:13:08.284555
6226 11:13:08.290909 CA PerBit enable=1, Macro0, CA PI delay=36
6227 11:13:08.291021
6228 11:13:08.294325 [CBTSetCACLKResult] CA Dly = 36
6229 11:13:08.294413 CS Dly: 1 (0~32)
6230 11:13:08.294478 ==
6231 11:13:08.297692 Dram Type= 6, Freq= 0, CH_0, rank 1
6232 11:13:08.300814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6233 11:13:08.300908 ==
6234 11:13:08.307743 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6235 11:13:08.313940 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6236 11:13:08.317519 [CA 0] Center 36 (8~64) winsize 57
6237 11:13:08.320707 [CA 1] Center 36 (8~64) winsize 57
6238 11:13:08.323724 [CA 2] Center 36 (8~64) winsize 57
6239 11:13:08.327296 [CA 3] Center 36 (8~64) winsize 57
6240 11:13:08.330493 [CA 4] Center 36 (8~64) winsize 57
6241 11:13:08.333664 [CA 5] Center 36 (8~64) winsize 57
6242 11:13:08.333741
6243 11:13:08.336811 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6244 11:13:08.336885
6245 11:13:08.340600 [CATrainingPosCal] consider 2 rank data
6246 11:13:08.343834 u2DelayCellTimex100 = 270/100 ps
6247 11:13:08.346976 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 11:13:08.350103 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 11:13:08.353740 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 11:13:08.356898 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 11:13:08.359973 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 11:13:08.363703 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 11:13:08.363787
6254 11:13:08.369889 CA PerBit enable=1, Macro0, CA PI delay=36
6255 11:13:08.370004
6256 11:13:08.370069 [CBTSetCACLKResult] CA Dly = 36
6257 11:13:08.373615 CS Dly: 1 (0~32)
6258 11:13:08.373698
6259 11:13:08.376754 ----->DramcWriteLeveling(PI) begin...
6260 11:13:08.376838 ==
6261 11:13:08.379940 Dram Type= 6, Freq= 0, CH_0, rank 0
6262 11:13:08.383015 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6263 11:13:08.383099 ==
6264 11:13:08.386548 Write leveling (Byte 0): 40 => 8
6265 11:13:08.389959 Write leveling (Byte 1): 32 => 0
6266 11:13:08.392823 DramcWriteLeveling(PI) end<-----
6267 11:13:08.392895
6268 11:13:08.392956 ==
6269 11:13:08.396295 Dram Type= 6, Freq= 0, CH_0, rank 0
6270 11:13:08.402970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6271 11:13:08.403055 ==
6272 11:13:08.403121 [Gating] SW mode calibration
6273 11:13:08.413278 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6274 11:13:08.416001 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6275 11:13:08.419552 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6276 11:13:08.426452 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6277 11:13:08.429108 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6278 11:13:08.432812 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6279 11:13:08.439151 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6280 11:13:08.442305 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6281 11:13:08.446141 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6282 11:13:08.452309 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6283 11:13:08.455456 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6284 11:13:08.459135 Total UI for P1: 0, mck2ui 16
6285 11:13:08.462185 best dqsien dly found for B0: ( 0, 14, 24)
6286 11:13:08.465363 Total UI for P1: 0, mck2ui 16
6287 11:13:08.469200 best dqsien dly found for B1: ( 0, 14, 24)
6288 11:13:08.472306 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6289 11:13:08.475483 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6290 11:13:08.475558
6291 11:13:08.478649 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6292 11:13:08.485483 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6293 11:13:08.485569 [Gating] SW calibration Done
6294 11:13:08.488586 ==
6295 11:13:08.488683 Dram Type= 6, Freq= 0, CH_0, rank 0
6296 11:13:08.495154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6297 11:13:08.495239 ==
6298 11:13:08.495301 RX Vref Scan: 0
6299 11:13:08.495359
6300 11:13:08.498625 RX Vref 0 -> 0, step: 1
6301 11:13:08.498697
6302 11:13:08.501590 RX Delay -410 -> 252, step: 16
6303 11:13:08.505209 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6304 11:13:08.508142 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6305 11:13:08.514774 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6306 11:13:08.518258 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6307 11:13:08.521371 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6308 11:13:08.527867 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6309 11:13:08.531372 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6310 11:13:08.534378 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6311 11:13:08.537992 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6312 11:13:08.544423 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6313 11:13:08.547548 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6314 11:13:08.551345 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6315 11:13:08.554520 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6316 11:13:08.560705 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6317 11:13:08.564486 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6318 11:13:08.567690 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6319 11:13:08.567771 ==
6320 11:13:08.570986 Dram Type= 6, Freq= 0, CH_0, rank 0
6321 11:13:08.577708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6322 11:13:08.577792 ==
6323 11:13:08.577856 DQS Delay:
6324 11:13:08.580835 DQS0 = 59, DQS1 = 59
6325 11:13:08.580916 DQM Delay:
6326 11:13:08.580979 DQM0 = 18, DQM1 = 11
6327 11:13:08.583909 DQ Delay:
6328 11:13:08.587062 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6329 11:13:08.590415 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6330 11:13:08.594026 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6331 11:13:08.596957 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6332 11:13:08.597044
6333 11:13:08.597108
6334 11:13:08.597167 ==
6335 11:13:08.600648 Dram Type= 6, Freq= 0, CH_0, rank 0
6336 11:13:08.603623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6337 11:13:08.603696 ==
6338 11:13:08.603757
6339 11:13:08.603815
6340 11:13:08.607024 TX Vref Scan disable
6341 11:13:08.607111 == TX Byte 0 ==
6342 11:13:08.613405 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6343 11:13:08.616882 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6344 11:13:08.616967 == TX Byte 1 ==
6345 11:13:08.623330 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6346 11:13:08.626433 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6347 11:13:08.626571 ==
6348 11:13:08.630282 Dram Type= 6, Freq= 0, CH_0, rank 0
6349 11:13:08.633049 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6350 11:13:08.633131 ==
6351 11:13:08.633195
6352 11:13:08.633253
6353 11:13:08.636762 TX Vref Scan disable
6354 11:13:08.639823 == TX Byte 0 ==
6355 11:13:08.643529 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6356 11:13:08.646698 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6357 11:13:08.649859 == TX Byte 1 ==
6358 11:13:08.652995 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6359 11:13:08.656175 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6360 11:13:08.656274
6361 11:13:08.656371 [DATLAT]
6362 11:13:08.659323 Freq=400, CH0 RK0
6363 11:13:08.659405
6364 11:13:08.659485 DATLAT Default: 0xf
6365 11:13:08.663129 0, 0xFFFF, sum = 0
6366 11:13:08.666176 1, 0xFFFF, sum = 0
6367 11:13:08.666260 2, 0xFFFF, sum = 0
6368 11:13:08.669356 3, 0xFFFF, sum = 0
6369 11:13:08.669440 4, 0xFFFF, sum = 0
6370 11:13:08.673071 5, 0xFFFF, sum = 0
6371 11:13:08.673155 6, 0xFFFF, sum = 0
6372 11:13:08.676244 7, 0xFFFF, sum = 0
6373 11:13:08.676328 8, 0xFFFF, sum = 0
6374 11:13:08.679291 9, 0xFFFF, sum = 0
6375 11:13:08.679375 10, 0xFFFF, sum = 0
6376 11:13:08.682968 11, 0xFFFF, sum = 0
6377 11:13:08.683052 12, 0xFFFF, sum = 0
6378 11:13:08.686088 13, 0x0, sum = 1
6379 11:13:08.686171 14, 0x0, sum = 2
6380 11:13:08.689464 15, 0x0, sum = 3
6381 11:13:08.689548 16, 0x0, sum = 4
6382 11:13:08.692456 best_step = 14
6383 11:13:08.692538
6384 11:13:08.692603 ==
6385 11:13:08.696468 Dram Type= 6, Freq= 0, CH_0, rank 0
6386 11:13:08.699320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6387 11:13:08.699403 ==
6388 11:13:08.702254 RX Vref Scan: 1
6389 11:13:08.702336
6390 11:13:08.702401 RX Vref 0 -> 0, step: 1
6391 11:13:08.702461
6392 11:13:08.706077 RX Delay -359 -> 252, step: 8
6393 11:13:08.706164
6394 11:13:08.708926 Set Vref, RX VrefLevel [Byte0]: 62
6395 11:13:08.712493 [Byte1]: 56
6396 11:13:08.717446
6397 11:13:08.717556 Final RX Vref Byte 0 = 62 to rank0
6398 11:13:08.720206 Final RX Vref Byte 1 = 56 to rank0
6399 11:13:08.723650 Final RX Vref Byte 0 = 62 to rank1
6400 11:13:08.727028 Final RX Vref Byte 1 = 56 to rank1==
6401 11:13:08.730591 Dram Type= 6, Freq= 0, CH_0, rank 0
6402 11:13:08.736994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6403 11:13:08.737083 ==
6404 11:13:08.737168 DQS Delay:
6405 11:13:08.739811 DQS0 = 60, DQS1 = 68
6406 11:13:08.739922 DQM Delay:
6407 11:13:08.740019 DQM0 = 15, DQM1 = 14
6408 11:13:08.743495 DQ Delay:
6409 11:13:08.746453 DQ0 =12, DQ1 =16, DQ2 =16, DQ3 =12
6410 11:13:08.749873 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6411 11:13:08.752837 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6412 11:13:08.756589 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =20
6413 11:13:08.756694
6414 11:13:08.756791
6415 11:13:08.763015 [DQSOSCAuto] RK0, (LSB)MR18= 0x8684, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6416 11:13:08.766096 CH0 RK0: MR19=C0C, MR18=8684
6417 11:13:08.772880 CH0_RK0: MR19=0xC0C, MR18=0x8684, DQSOSC=393, MR23=63, INC=382, DEC=254
6418 11:13:08.772994 ==
6419 11:13:08.775929 Dram Type= 6, Freq= 0, CH_0, rank 1
6420 11:13:08.779669 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6421 11:13:08.779776 ==
6422 11:13:08.782716 [Gating] SW mode calibration
6423 11:13:08.789607 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6424 11:13:08.796038 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6425 11:13:08.799036 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6426 11:13:08.805891 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6427 11:13:08.808892 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6428 11:13:08.812538 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6429 11:13:08.818706 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6430 11:13:08.822562 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6431 11:13:08.825329 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6432 11:13:08.831903 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6433 11:13:08.835457 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6434 11:13:08.838314 Total UI for P1: 0, mck2ui 16
6435 11:13:08.841898 best dqsien dly found for B0: ( 0, 14, 24)
6436 11:13:08.844892 Total UI for P1: 0, mck2ui 16
6437 11:13:08.848674 best dqsien dly found for B1: ( 0, 14, 24)
6438 11:13:08.851683 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6439 11:13:08.855217 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6440 11:13:08.855331
6441 11:13:08.858287 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6442 11:13:08.861391 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6443 11:13:08.865231 [Gating] SW calibration Done
6444 11:13:08.865317 ==
6445 11:13:08.868356 Dram Type= 6, Freq= 0, CH_0, rank 1
6446 11:13:08.871393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6447 11:13:08.874958 ==
6448 11:13:08.875046 RX Vref Scan: 0
6449 11:13:08.875125
6450 11:13:08.878084 RX Vref 0 -> 0, step: 1
6451 11:13:08.878171
6452 11:13:08.881424 RX Delay -410 -> 252, step: 16
6453 11:13:08.884577 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6454 11:13:08.888245 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6455 11:13:08.891325 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6456 11:13:08.897706 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6457 11:13:08.901259 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6458 11:13:08.904402 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6459 11:13:08.907571 iDelay=230, Bit 6, Center -35 (-298 ~ 229) 528
6460 11:13:08.914291 iDelay=230, Bit 7, Center -35 (-298 ~ 229) 528
6461 11:13:08.917853 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6462 11:13:08.920829 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6463 11:13:08.927378 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6464 11:13:08.930455 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6465 11:13:08.933939 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6466 11:13:08.937369 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6467 11:13:08.943965 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6468 11:13:08.946930 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6469 11:13:08.947016 ==
6470 11:13:08.950506 Dram Type= 6, Freq= 0, CH_0, rank 1
6471 11:13:08.953624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6472 11:13:08.953732 ==
6473 11:13:08.956688 DQS Delay:
6474 11:13:08.956790 DQS0 = 59, DQS1 = 59
6475 11:13:08.960388 DQM Delay:
6476 11:13:08.960496 DQM0 = 16, DQM1 = 10
6477 11:13:08.963356 DQ Delay:
6478 11:13:08.963436 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6479 11:13:08.966946 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6480 11:13:08.970016 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6481 11:13:08.973869 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6482 11:13:08.973952
6483 11:13:08.974018
6484 11:13:08.974079 ==
6485 11:13:08.977074 Dram Type= 6, Freq= 0, CH_0, rank 1
6486 11:13:08.983873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6487 11:13:08.983966 ==
6488 11:13:08.984034
6489 11:13:08.984095
6490 11:13:08.987106 TX Vref Scan disable
6491 11:13:08.987191 == TX Byte 0 ==
6492 11:13:08.990094 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6493 11:13:08.996401 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6494 11:13:08.996487 == TX Byte 1 ==
6495 11:13:09.000173 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6496 11:13:09.003405 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6497 11:13:09.006546 ==
6498 11:13:09.009917 Dram Type= 6, Freq= 0, CH_0, rank 1
6499 11:13:09.012794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6500 11:13:09.012904 ==
6501 11:13:09.012974
6502 11:13:09.013036
6503 11:13:09.016569 TX Vref Scan disable
6504 11:13:09.016672 == TX Byte 0 ==
6505 11:13:09.019589 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6506 11:13:09.026036 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6507 11:13:09.026136 == TX Byte 1 ==
6508 11:13:09.029478 Update DQ dly =579 (4 ,2, 3) DQ OEN =(3 ,3)
6509 11:13:09.036367 Update DQM dly =579 (4 ,2, 3) DQM OEN =(3 ,3)
6510 11:13:09.036456
6511 11:13:09.036523 [DATLAT]
6512 11:13:09.036585 Freq=400, CH0 RK1
6513 11:13:09.036645
6514 11:13:09.039686 DATLAT Default: 0xe
6515 11:13:09.042626 0, 0xFFFF, sum = 0
6516 11:13:09.042739 1, 0xFFFF, sum = 0
6517 11:13:09.045740 2, 0xFFFF, sum = 0
6518 11:13:09.045832 3, 0xFFFF, sum = 0
6519 11:13:09.049344 4, 0xFFFF, sum = 0
6520 11:13:09.049433 5, 0xFFFF, sum = 0
6521 11:13:09.052328 6, 0xFFFF, sum = 0
6522 11:13:09.052416 7, 0xFFFF, sum = 0
6523 11:13:09.055849 8, 0xFFFF, sum = 0
6524 11:13:09.055939 9, 0xFFFF, sum = 0
6525 11:13:09.059422 10, 0xFFFF, sum = 0
6526 11:13:09.059545 11, 0xFFFF, sum = 0
6527 11:13:09.062476 12, 0xFFFF, sum = 0
6528 11:13:09.062595 13, 0x0, sum = 1
6529 11:13:09.065995 14, 0x0, sum = 2
6530 11:13:09.066115 15, 0x0, sum = 3
6531 11:13:09.069085 16, 0x0, sum = 4
6532 11:13:09.069198 best_step = 14
6533 11:13:09.069298
6534 11:13:09.069390 ==
6535 11:13:09.072701 Dram Type= 6, Freq= 0, CH_0, rank 1
6536 11:13:09.079047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6537 11:13:09.079172 ==
6538 11:13:09.079285 RX Vref Scan: 0
6539 11:13:09.079382
6540 11:13:09.082050 RX Vref 0 -> 0, step: 1
6541 11:13:09.082156
6542 11:13:09.085733 RX Delay -359 -> 252, step: 8
6543 11:13:09.092069 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6544 11:13:09.095775 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6545 11:13:09.099107 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6546 11:13:09.101938 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6547 11:13:09.108754 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6548 11:13:09.111863 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6549 11:13:09.115018 iDelay=217, Bit 6, Center -40 (-295 ~ 216) 512
6550 11:13:09.118768 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6551 11:13:09.124916 iDelay=217, Bit 8, Center -60 (-311 ~ 192) 504
6552 11:13:09.128418 iDelay=217, Bit 9, Center -72 (-319 ~ 176) 496
6553 11:13:09.131450 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6554 11:13:09.138529 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6555 11:13:09.141422 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6556 11:13:09.145026 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6557 11:13:09.147996 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6558 11:13:09.154735 iDelay=217, Bit 15, Center -44 (-295 ~ 208) 504
6559 11:13:09.154851 ==
6560 11:13:09.158089 Dram Type= 6, Freq= 0, CH_0, rank 1
6561 11:13:09.161180 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6562 11:13:09.161272 ==
6563 11:13:09.161341 DQS Delay:
6564 11:13:09.164594 DQS0 = 60, DQS1 = 72
6565 11:13:09.164673 DQM Delay:
6566 11:13:09.168102 DQM0 = 11, DQM1 = 18
6567 11:13:09.168185 DQ Delay:
6568 11:13:09.171537 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6569 11:13:09.174316 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =24
6570 11:13:09.177837 DQ8 =12, DQ9 =0, DQ10 =20, DQ11 =12
6571 11:13:09.180908 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =28
6572 11:13:09.180990
6573 11:13:09.181056
6574 11:13:09.187850 [DQSOSCAuto] RK1, (LSB)MR18= 0xc57b, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 385 ps
6575 11:13:09.191036 CH0 RK1: MR19=C0C, MR18=C57B
6576 11:13:09.197951 CH0_RK1: MR19=0xC0C, MR18=0xC57B, DQSOSC=385, MR23=63, INC=398, DEC=265
6577 11:13:09.200816 [RxdqsGatingPostProcess] freq 400
6578 11:13:09.207599 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6579 11:13:09.211321 best DQS0 dly(2T, 0.5T) = (0, 10)
6580 11:13:09.214482 best DQS1 dly(2T, 0.5T) = (0, 10)
6581 11:13:09.217668 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6582 11:13:09.220714 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6583 11:13:09.220829 best DQS0 dly(2T, 0.5T) = (0, 10)
6584 11:13:09.224433 best DQS1 dly(2T, 0.5T) = (0, 10)
6585 11:13:09.227543 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6586 11:13:09.230663 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6587 11:13:09.234291 Pre-setting of DQS Precalculation
6588 11:13:09.240717 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6589 11:13:09.240843 ==
6590 11:13:09.243669 Dram Type= 6, Freq= 0, CH_1, rank 0
6591 11:13:09.247108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6592 11:13:09.247250 ==
6593 11:13:09.253580 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6594 11:13:09.260205 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=31, u1VrefScanEnd=31
6595 11:13:09.263693 [CA 0] Center 36 (8~64) winsize 57
6596 11:13:09.266560 [CA 1] Center 36 (8~64) winsize 57
6597 11:13:09.270306 [CA 2] Center 36 (8~64) winsize 57
6598 11:13:09.270427 [CA 3] Center 36 (8~64) winsize 57
6599 11:13:09.273992 [CA 4] Center 36 (8~64) winsize 57
6600 11:13:09.276503 [CA 5] Center 36 (8~64) winsize 57
6601 11:13:09.276622
6602 11:13:09.283041 [CmdBusTrainingLP45] Vref(ca) range 1: 31
6603 11:13:09.283167
6604 11:13:09.286574 [CATrainingPosCal] consider 1 rank data
6605 11:13:09.289755 u2DelayCellTimex100 = 270/100 ps
6606 11:13:09.293463 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6607 11:13:09.296740 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6608 11:13:09.299945 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6609 11:13:09.303093 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6610 11:13:09.306054 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6611 11:13:09.309808 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6612 11:13:09.309901
6613 11:13:09.312896 CA PerBit enable=1, Macro0, CA PI delay=36
6614 11:13:09.312974
6615 11:13:09.316623 [CBTSetCACLKResult] CA Dly = 36
6616 11:13:09.319815 CS Dly: 1 (0~32)
6617 11:13:09.319898 ==
6618 11:13:09.323038 Dram Type= 6, Freq= 0, CH_1, rank 1
6619 11:13:09.326140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6620 11:13:09.326235 ==
6621 11:13:09.333048 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6622 11:13:09.339867 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6623 11:13:09.339960 [CA 0] Center 36 (8~64) winsize 57
6624 11:13:09.342693 [CA 1] Center 36 (8~64) winsize 57
6625 11:13:09.346133 [CA 2] Center 36 (8~64) winsize 57
6626 11:13:09.349198 [CA 3] Center 36 (8~64) winsize 57
6627 11:13:09.352910 [CA 4] Center 36 (8~64) winsize 57
6628 11:13:09.356052 [CA 5] Center 36 (8~64) winsize 57
6629 11:13:09.356140
6630 11:13:09.359718 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6631 11:13:09.359832
6632 11:13:09.362635 [CATrainingPosCal] consider 2 rank data
6633 11:13:09.366300 u2DelayCellTimex100 = 270/100 ps
6634 11:13:09.369189 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 11:13:09.375656 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 11:13:09.379269 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 11:13:09.382100 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 11:13:09.385720 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 11:13:09.388816 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 11:13:09.388934
6641 11:13:09.392450 CA PerBit enable=1, Macro0, CA PI delay=36
6642 11:13:09.392556
6643 11:13:09.395508 [CBTSetCACLKResult] CA Dly = 36
6644 11:13:09.398809 CS Dly: 1 (0~32)
6645 11:13:09.398922
6646 11:13:09.402388 ----->DramcWriteLeveling(PI) begin...
6647 11:13:09.402487 ==
6648 11:13:09.405484 Dram Type= 6, Freq= 0, CH_1, rank 0
6649 11:13:09.408496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6650 11:13:09.408615 ==
6651 11:13:09.412017 Write leveling (Byte 0): 40 => 8
6652 11:13:09.415203 Write leveling (Byte 1): 40 => 8
6653 11:13:09.418333 DramcWriteLeveling(PI) end<-----
6654 11:13:09.418440
6655 11:13:09.418509 ==
6656 11:13:09.421464 Dram Type= 6, Freq= 0, CH_1, rank 0
6657 11:13:09.425241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6658 11:13:09.425332 ==
6659 11:13:09.428359 [Gating] SW mode calibration
6660 11:13:09.435349 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6661 11:13:09.441581 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6662 11:13:09.444651 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6663 11:13:09.448363 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6664 11:13:09.454975 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6665 11:13:09.458239 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6666 11:13:09.461259 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6667 11:13:09.467780 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6668 11:13:09.471340 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6669 11:13:09.474397 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6670 11:13:09.480913 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6671 11:13:09.483948 Total UI for P1: 0, mck2ui 16
6672 11:13:09.487654 best dqsien dly found for B0: ( 0, 14, 24)
6673 11:13:09.490573 Total UI for P1: 0, mck2ui 16
6674 11:13:09.494199 best dqsien dly found for B1: ( 0, 14, 24)
6675 11:13:09.497228 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6676 11:13:09.500781 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6677 11:13:09.500863
6678 11:13:09.503963 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6679 11:13:09.506986 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6680 11:13:09.510594 [Gating] SW calibration Done
6681 11:13:09.510703 ==
6682 11:13:09.513635 Dram Type= 6, Freq= 0, CH_1, rank 0
6683 11:13:09.516796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6684 11:13:09.520574 ==
6685 11:13:09.520682 RX Vref Scan: 0
6686 11:13:09.520774
6687 11:13:09.523675 RX Vref 0 -> 0, step: 1
6688 11:13:09.523757
6689 11:13:09.526787 RX Delay -410 -> 252, step: 16
6690 11:13:09.529918 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6691 11:13:09.533109 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6692 11:13:09.536384 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6693 11:13:09.543425 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6694 11:13:09.546518 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6695 11:13:09.549688 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6696 11:13:09.556564 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6697 11:13:09.559442 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6698 11:13:09.563079 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6699 11:13:09.566351 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6700 11:13:09.572640 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6701 11:13:09.576044 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6702 11:13:09.579407 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6703 11:13:09.582321 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6704 11:13:09.589029 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6705 11:13:09.592394 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6706 11:13:09.592481 ==
6707 11:13:09.595860 Dram Type= 6, Freq= 0, CH_1, rank 0
6708 11:13:09.599245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6709 11:13:09.599332 ==
6710 11:13:09.602251 DQS Delay:
6711 11:13:09.602337 DQS0 = 51, DQS1 = 67
6712 11:13:09.605554 DQM Delay:
6713 11:13:09.605639 DQM0 = 13, DQM1 = 18
6714 11:13:09.605706 DQ Delay:
6715 11:13:09.609047 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6716 11:13:09.612204 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6717 11:13:09.615900 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6718 11:13:09.618871 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =32
6719 11:13:09.618960
6720 11:13:09.619027
6721 11:13:09.619089 ==
6722 11:13:09.622506 Dram Type= 6, Freq= 0, CH_1, rank 0
6723 11:13:09.628908 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6724 11:13:09.629000 ==
6725 11:13:09.629068
6726 11:13:09.629131
6727 11:13:09.629190 TX Vref Scan disable
6728 11:13:09.632130 == TX Byte 0 ==
6729 11:13:09.635301 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6730 11:13:09.638976 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6731 11:13:09.642202 == TX Byte 1 ==
6732 11:13:09.645287 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6733 11:13:09.648419 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6734 11:13:09.652267 ==
6735 11:13:09.652353 Dram Type= 6, Freq= 0, CH_1, rank 0
6736 11:13:09.658572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6737 11:13:09.658659 ==
6738 11:13:09.658726
6739 11:13:09.658788
6740 11:13:09.661591 TX Vref Scan disable
6741 11:13:09.661675 == TX Byte 0 ==
6742 11:13:09.665354 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6743 11:13:09.671565 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6744 11:13:09.671654 == TX Byte 1 ==
6745 11:13:09.675047 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6746 11:13:09.681554 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6747 11:13:09.681644
6748 11:13:09.681711 [DATLAT]
6749 11:13:09.681773 Freq=400, CH1 RK0
6750 11:13:09.681834
6751 11:13:09.685011 DATLAT Default: 0xf
6752 11:13:09.688004 0, 0xFFFF, sum = 0
6753 11:13:09.688091 1, 0xFFFF, sum = 0
6754 11:13:09.691598 2, 0xFFFF, sum = 0
6755 11:13:09.691686 3, 0xFFFF, sum = 0
6756 11:13:09.694475 4, 0xFFFF, sum = 0
6757 11:13:09.694562 5, 0xFFFF, sum = 0
6758 11:13:09.698062 6, 0xFFFF, sum = 0
6759 11:13:09.698192 7, 0xFFFF, sum = 0
6760 11:13:09.701330 8, 0xFFFF, sum = 0
6761 11:13:09.701435 9, 0xFFFF, sum = 0
6762 11:13:09.704939 10, 0xFFFF, sum = 0
6763 11:13:09.705028 11, 0xFFFF, sum = 0
6764 11:13:09.707901 12, 0xFFFF, sum = 0
6765 11:13:09.708007 13, 0x0, sum = 1
6766 11:13:09.711501 14, 0x0, sum = 2
6767 11:13:09.711613 15, 0x0, sum = 3
6768 11:13:09.714476 16, 0x0, sum = 4
6769 11:13:09.714561 best_step = 14
6770 11:13:09.714628
6771 11:13:09.714690 ==
6772 11:13:09.718004 Dram Type= 6, Freq= 0, CH_1, rank 0
6773 11:13:09.720921 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6774 11:13:09.724621 ==
6775 11:13:09.724708 RX Vref Scan: 1
6776 11:13:09.724775
6777 11:13:09.727651 RX Vref 0 -> 0, step: 1
6778 11:13:09.727769
6779 11:13:09.730789 RX Delay -375 -> 252, step: 8
6780 11:13:09.730916
6781 11:13:09.734579 Set Vref, RX VrefLevel [Byte0]: 57
6782 11:13:09.737798 [Byte1]: 53
6783 11:13:09.737883
6784 11:13:09.740970 Final RX Vref Byte 0 = 57 to rank0
6785 11:13:09.744087 Final RX Vref Byte 1 = 53 to rank0
6786 11:13:09.747276 Final RX Vref Byte 0 = 57 to rank1
6787 11:13:09.751097 Final RX Vref Byte 1 = 53 to rank1==
6788 11:13:09.754150 Dram Type= 6, Freq= 0, CH_1, rank 0
6789 11:13:09.757319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6790 11:13:09.760425 ==
6791 11:13:09.760544 DQS Delay:
6792 11:13:09.760649 DQS0 = 56, DQS1 = 64
6793 11:13:09.764395 DQM Delay:
6794 11:13:09.764508 DQM0 = 13, DQM1 = 10
6795 11:13:09.767711 DQ Delay:
6796 11:13:09.770536 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6797 11:13:09.770622 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6798 11:13:09.774137 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6799 11:13:09.777086 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6800 11:13:09.777171
6801 11:13:09.780571
6802 11:13:09.787099 [DQSOSCAuto] RK0, (LSB)MR18= 0x5a6d, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 398 ps
6803 11:13:09.790617 CH1 RK0: MR19=C0C, MR18=5A6D
6804 11:13:09.796613 CH1_RK0: MR19=0xC0C, MR18=0x5A6D, DQSOSC=396, MR23=63, INC=376, DEC=251
6805 11:13:09.796705 ==
6806 11:13:09.800085 Dram Type= 6, Freq= 0, CH_1, rank 1
6807 11:13:09.803681 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6808 11:13:09.803766 ==
6809 11:13:09.806735 [Gating] SW mode calibration
6810 11:13:09.813303 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6811 11:13:09.820046 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6812 11:13:09.822892 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6813 11:13:09.826488 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6814 11:13:09.833031 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6815 11:13:09.836135 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6816 11:13:09.839320 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6817 11:13:09.846296 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6818 11:13:09.849417 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6819 11:13:09.852615 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6820 11:13:09.858956 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6821 11:13:09.862699 Total UI for P1: 0, mck2ui 16
6822 11:13:09.865814 best dqsien dly found for B0: ( 0, 14, 24)
6823 11:13:09.865894 Total UI for P1: 0, mck2ui 16
6824 11:13:09.872769 best dqsien dly found for B1: ( 0, 14, 24)
6825 11:13:09.875697 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6826 11:13:09.878748 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6827 11:13:09.878889
6828 11:13:09.882499 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6829 11:13:09.885385 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6830 11:13:09.889003 [Gating] SW calibration Done
6831 11:13:09.889115 ==
6832 11:13:09.891988 Dram Type= 6, Freq= 0, CH_1, rank 1
6833 11:13:09.895512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6834 11:13:09.895648 ==
6835 11:13:09.899124 RX Vref Scan: 0
6836 11:13:09.899202
6837 11:13:09.902031 RX Vref 0 -> 0, step: 1
6838 11:13:09.902109
6839 11:13:09.902173 RX Delay -410 -> 252, step: 16
6840 11:13:09.908547 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6841 11:13:09.912015 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6842 11:13:09.915603 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6843 11:13:09.919187 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6844 11:13:09.925261 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6845 11:13:09.929058 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6846 11:13:09.932138 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6847 11:13:09.935121 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6848 11:13:09.941692 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6849 11:13:09.945462 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6850 11:13:09.948659 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6851 11:13:09.955005 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6852 11:13:09.958098 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6853 11:13:09.961290 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6854 11:13:09.965350 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6855 11:13:09.971595 iDelay=230, Bit 15, Center -35 (-298 ~ 229) 528
6856 11:13:09.971707 ==
6857 11:13:09.974891 Dram Type= 6, Freq= 0, CH_1, rank 1
6858 11:13:09.977919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6859 11:13:09.977997 ==
6860 11:13:09.978060 DQS Delay:
6861 11:13:09.981655 DQS0 = 59, DQS1 = 59
6862 11:13:09.981728 DQM Delay:
6863 11:13:09.984756 DQM0 = 19, DQM1 = 13
6864 11:13:09.984830 DQ Delay:
6865 11:13:09.987760 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6866 11:13:09.990873 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6867 11:13:09.994324 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =8
6868 11:13:09.997719 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =24
6869 11:13:09.997804
6870 11:13:09.997871
6871 11:13:09.997933 ==
6872 11:13:10.001533 Dram Type= 6, Freq= 0, CH_1, rank 1
6873 11:13:10.004443 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6874 11:13:10.007362 ==
6875 11:13:10.007454
6876 11:13:10.007522
6877 11:13:10.007584 TX Vref Scan disable
6878 11:13:10.010869 == TX Byte 0 ==
6879 11:13:10.014363 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6880 11:13:10.017968 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6881 11:13:10.020610 == TX Byte 1 ==
6882 11:13:10.024412 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6883 11:13:10.027455 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6884 11:13:10.027543 ==
6885 11:13:10.031004 Dram Type= 6, Freq= 0, CH_1, rank 1
6886 11:13:10.037206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6887 11:13:10.037335 ==
6888 11:13:10.037432
6889 11:13:10.037539
6890 11:13:10.037631 TX Vref Scan disable
6891 11:13:10.040734 == TX Byte 0 ==
6892 11:13:10.044553 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6893 11:13:10.047539 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6894 11:13:10.050514 == TX Byte 1 ==
6895 11:13:10.053621 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6896 11:13:10.057428 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6897 11:13:10.057520
6898 11:13:10.060614 [DATLAT]
6899 11:13:10.060704 Freq=400, CH1 RK1
6900 11:13:10.060772
6901 11:13:10.063861 DATLAT Default: 0xe
6902 11:13:10.063948 0, 0xFFFF, sum = 0
6903 11:13:10.067081 1, 0xFFFF, sum = 0
6904 11:13:10.067169 2, 0xFFFF, sum = 0
6905 11:13:10.070131 3, 0xFFFF, sum = 0
6906 11:13:10.070218 4, 0xFFFF, sum = 0
6907 11:13:10.073309 5, 0xFFFF, sum = 0
6908 11:13:10.073401 6, 0xFFFF, sum = 0
6909 11:13:10.077102 7, 0xFFFF, sum = 0
6910 11:13:10.077189 8, 0xFFFF, sum = 0
6911 11:13:10.080159 9, 0xFFFF, sum = 0
6912 11:13:10.080246 10, 0xFFFF, sum = 0
6913 11:13:10.083340 11, 0xFFFF, sum = 0
6914 11:13:10.086996 12, 0xFFFF, sum = 0
6915 11:13:10.087086 13, 0x0, sum = 1
6916 11:13:10.090123 14, 0x0, sum = 2
6917 11:13:10.090211 15, 0x0, sum = 3
6918 11:13:10.090280 16, 0x0, sum = 4
6919 11:13:10.093280 best_step = 14
6920 11:13:10.093368
6921 11:13:10.093436 ==
6922 11:13:10.096418 Dram Type= 6, Freq= 0, CH_1, rank 1
6923 11:13:10.099959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6924 11:13:10.100044 ==
6925 11:13:10.103282 RX Vref Scan: 0
6926 11:13:10.103367
6927 11:13:10.106651 RX Vref 0 -> 0, step: 1
6928 11:13:10.106736
6929 11:13:10.106803 RX Delay -359 -> 252, step: 8
6930 11:13:10.115015 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6931 11:13:10.118515 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6932 11:13:10.121480 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6933 11:13:10.128430 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6934 11:13:10.131767 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
6935 11:13:10.134532 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6936 11:13:10.137923 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6937 11:13:10.144903 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
6938 11:13:10.147867 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6939 11:13:10.150813 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6940 11:13:10.154465 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6941 11:13:10.160812 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6942 11:13:10.163951 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6943 11:13:10.167854 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6944 11:13:10.174145 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6945 11:13:10.177285 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6946 11:13:10.177371 ==
6947 11:13:10.180470 Dram Type= 6, Freq= 0, CH_1, rank 1
6948 11:13:10.183584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6949 11:13:10.183690 ==
6950 11:13:10.187444 DQS Delay:
6951 11:13:10.187524 DQS0 = 60, DQS1 = 64
6952 11:13:10.190429 DQM Delay:
6953 11:13:10.190532 DQM0 = 12, DQM1 = 10
6954 11:13:10.190622 DQ Delay:
6955 11:13:10.193500 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6956 11:13:10.197221 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6957 11:13:10.200379 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6958 11:13:10.203375 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6959 11:13:10.203477
6960 11:13:10.203542
6961 11:13:10.213562 [DQSOSCAuto] RK1, (LSB)MR18= 0x7bab, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 394 ps
6962 11:13:10.216535 CH1 RK1: MR19=C0C, MR18=7BAB
6963 11:13:10.220093 CH1_RK1: MR19=0xC0C, MR18=0x7BAB, DQSOSC=388, MR23=63, INC=392, DEC=261
6964 11:13:10.223110 [RxdqsGatingPostProcess] freq 400
6965 11:13:10.229795 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6966 11:13:10.233058 best DQS0 dly(2T, 0.5T) = (0, 10)
6967 11:13:10.236532 best DQS1 dly(2T, 0.5T) = (0, 10)
6968 11:13:10.239476 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6969 11:13:10.243091 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6970 11:13:10.246021 best DQS0 dly(2T, 0.5T) = (0, 10)
6971 11:13:10.249512 best DQS1 dly(2T, 0.5T) = (0, 10)
6972 11:13:10.252509 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6973 11:13:10.256148 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6974 11:13:10.259058 Pre-setting of DQS Precalculation
6975 11:13:10.262739 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6976 11:13:10.269165 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6977 11:13:10.278650 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6978 11:13:10.278747
6979 11:13:10.278816
6980 11:13:10.282425 [Calibration Summary] 800 Mbps
6981 11:13:10.282512 CH 0, Rank 0
6982 11:13:10.285517 SW Impedance : PASS
6983 11:13:10.285602 DUTY Scan : NO K
6984 11:13:10.288630 ZQ Calibration : PASS
6985 11:13:10.288722 Jitter Meter : NO K
6986 11:13:10.292507 CBT Training : PASS
6987 11:13:10.295615 Write leveling : PASS
6988 11:13:10.295704 RX DQS gating : PASS
6989 11:13:10.298718 RX DQ/DQS(RDDQC) : PASS
6990 11:13:10.301823 TX DQ/DQS : PASS
6991 11:13:10.301901 RX DATLAT : PASS
6992 11:13:10.305484 RX DQ/DQS(Engine): PASS
6993 11:13:10.308671 TX OE : NO K
6994 11:13:10.308754 All Pass.
6995 11:13:10.308824
6996 11:13:10.308913 CH 0, Rank 1
6997 11:13:10.311685 SW Impedance : PASS
6998 11:13:10.315432 DUTY Scan : NO K
6999 11:13:10.315512 ZQ Calibration : PASS
7000 11:13:10.318395 Jitter Meter : NO K
7001 11:13:10.321986 CBT Training : PASS
7002 11:13:10.322057 Write leveling : NO K
7003 11:13:10.324979 RX DQS gating : PASS
7004 11:13:10.328508 RX DQ/DQS(RDDQC) : PASS
7005 11:13:10.328584 TX DQ/DQS : PASS
7006 11:13:10.332089 RX DATLAT : PASS
7007 11:13:10.335031 RX DQ/DQS(Engine): PASS
7008 11:13:10.335111 TX OE : NO K
7009 11:13:10.338538 All Pass.
7010 11:13:10.338613
7011 11:13:10.338677 CH 1, Rank 0
7012 11:13:10.341837 SW Impedance : PASS
7013 11:13:10.341915 DUTY Scan : NO K
7014 11:13:10.344856 ZQ Calibration : PASS
7015 11:13:10.347863 Jitter Meter : NO K
7016 11:13:10.347967 CBT Training : PASS
7017 11:13:10.351444 Write leveling : PASS
7018 11:13:10.354908 RX DQS gating : PASS
7019 11:13:10.355011 RX DQ/DQS(RDDQC) : PASS
7020 11:13:10.357622 TX DQ/DQS : PASS
7021 11:13:10.361085 RX DATLAT : PASS
7022 11:13:10.361190 RX DQ/DQS(Engine): PASS
7023 11:13:10.364705 TX OE : NO K
7024 11:13:10.364788 All Pass.
7025 11:13:10.364852
7026 11:13:10.367876 CH 1, Rank 1
7027 11:13:10.367955 SW Impedance : PASS
7028 11:13:10.371026 DUTY Scan : NO K
7029 11:13:10.374327 ZQ Calibration : PASS
7030 11:13:10.374401 Jitter Meter : NO K
7031 11:13:10.377435 CBT Training : PASS
7032 11:13:10.377535 Write leveling : NO K
7033 11:13:10.380628 RX DQS gating : PASS
7034 11:13:10.384757 RX DQ/DQS(RDDQC) : PASS
7035 11:13:10.384862 TX DQ/DQS : PASS
7036 11:13:10.387660 RX DATLAT : PASS
7037 11:13:10.390979 RX DQ/DQS(Engine): PASS
7038 11:13:10.391062 TX OE : NO K
7039 11:13:10.394086 All Pass.
7040 11:13:10.394195
7041 11:13:10.394297 DramC Write-DBI off
7042 11:13:10.397225 PER_BANK_REFRESH: Hybrid Mode
7043 11:13:10.400991 TX_TRACKING: ON
7044 11:13:10.407210 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7045 11:13:10.410548 [FAST_K] Save calibration result to emmc
7046 11:13:10.417230 dramc_set_vcore_voltage set vcore to 725000
7047 11:13:10.417348 Read voltage for 1600, 0
7048 11:13:10.420455 Vio18 = 0
7049 11:13:10.420575 Vcore = 725000
7050 11:13:10.420677 Vdram = 0
7051 11:13:10.420784 Vddq = 0
7052 11:13:10.423494 Vmddr = 0
7053 11:13:10.427238 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7054 11:13:10.433890 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7055 11:13:10.436843 MEM_TYPE=3, freq_sel=13
7056 11:13:10.436961 sv_algorithm_assistance_LP4_3733
7057 11:13:10.443485 ============ PULL DRAM RESETB DOWN ============
7058 11:13:10.447132 ========== PULL DRAM RESETB DOWN end =========
7059 11:13:10.450041 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7060 11:13:10.453119 ===================================
7061 11:13:10.456799 LPDDR4 DRAM CONFIGURATION
7062 11:13:10.459883 ===================================
7063 11:13:10.463334 EX_ROW_EN[0] = 0x0
7064 11:13:10.463447 EX_ROW_EN[1] = 0x0
7065 11:13:10.466747 LP4Y_EN = 0x0
7066 11:13:10.466854 WORK_FSP = 0x1
7067 11:13:10.469786 WL = 0x5
7068 11:13:10.469876 RL = 0x5
7069 11:13:10.473183 BL = 0x2
7070 11:13:10.473287 RPST = 0x0
7071 11:13:10.476379 RD_PRE = 0x0
7072 11:13:10.479440 WR_PRE = 0x1
7073 11:13:10.479524 WR_PST = 0x1
7074 11:13:10.483239 DBI_WR = 0x0
7075 11:13:10.483323 DBI_RD = 0x0
7076 11:13:10.486438 OTF = 0x1
7077 11:13:10.489591 ===================================
7078 11:13:10.492661 ===================================
7079 11:13:10.492746 ANA top config
7080 11:13:10.495829 ===================================
7081 11:13:10.499681 DLL_ASYNC_EN = 0
7082 11:13:10.502655 ALL_SLAVE_EN = 0
7083 11:13:10.502740 NEW_RANK_MODE = 1
7084 11:13:10.505767 DLL_IDLE_MODE = 1
7085 11:13:10.508910 LP45_APHY_COMB_EN = 1
7086 11:13:10.512711 TX_ODT_DIS = 0
7087 11:13:10.515810 NEW_8X_MODE = 1
7088 11:13:10.519421 ===================================
7089 11:13:10.522533 ===================================
7090 11:13:10.522646 data_rate = 3200
7091 11:13:10.525656 CKR = 1
7092 11:13:10.529445 DQ_P2S_RATIO = 8
7093 11:13:10.532432 ===================================
7094 11:13:10.536006 CA_P2S_RATIO = 8
7095 11:13:10.538792 DQ_CA_OPEN = 0
7096 11:13:10.542415 DQ_SEMI_OPEN = 0
7097 11:13:10.542531 CA_SEMI_OPEN = 0
7098 11:13:10.545500 CA_FULL_RATE = 0
7099 11:13:10.549259 DQ_CKDIV4_EN = 0
7100 11:13:10.551954 CA_CKDIV4_EN = 0
7101 11:13:10.555203 CA_PREDIV_EN = 0
7102 11:13:10.558696 PH8_DLY = 12
7103 11:13:10.561669 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7104 11:13:10.561788 DQ_AAMCK_DIV = 4
7105 11:13:10.565508 CA_AAMCK_DIV = 4
7106 11:13:10.568535 CA_ADMCK_DIV = 4
7107 11:13:10.572012 DQ_TRACK_CA_EN = 0
7108 11:13:10.575374 CA_PICK = 1600
7109 11:13:10.578660 CA_MCKIO = 1600
7110 11:13:10.581816 MCKIO_SEMI = 0
7111 11:13:10.581903 PLL_FREQ = 3068
7112 11:13:10.584803 DQ_UI_PI_RATIO = 32
7113 11:13:10.588420 CA_UI_PI_RATIO = 0
7114 11:13:10.591534 ===================================
7115 11:13:10.595134 ===================================
7116 11:13:10.598155 memory_type:LPDDR4
7117 11:13:10.601429 GP_NUM : 10
7118 11:13:10.601535 SRAM_EN : 1
7119 11:13:10.604943 MD32_EN : 0
7120 11:13:10.607876 ===================================
7121 11:13:10.607963 [ANA_INIT] >>>>>>>>>>>>>>
7122 11:13:10.611636 <<<<<< [CONFIGURE PHASE]: ANA_TX
7123 11:13:10.614718 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7124 11:13:10.617822 ===================================
7125 11:13:10.621380 data_rate = 3200,PCW = 0X7600
7126 11:13:10.624269 ===================================
7127 11:13:10.627924 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7128 11:13:10.634158 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7129 11:13:10.641297 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7130 11:13:10.644154 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7131 11:13:10.647698 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7132 11:13:10.651147 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7133 11:13:10.654022 [ANA_INIT] flow start
7134 11:13:10.654107 [ANA_INIT] PLL >>>>>>>>
7135 11:13:10.657754 [ANA_INIT] PLL <<<<<<<<
7136 11:13:10.661047 [ANA_INIT] MIDPI >>>>>>>>
7137 11:13:10.661131 [ANA_INIT] MIDPI <<<<<<<<
7138 11:13:10.664306 [ANA_INIT] DLL >>>>>>>>
7139 11:13:10.667603 [ANA_INIT] DLL <<<<<<<<
7140 11:13:10.667702 [ANA_INIT] flow end
7141 11:13:10.674113 ============ LP4 DIFF to SE enter ============
7142 11:13:10.677105 ============ LP4 DIFF to SE exit ============
7143 11:13:10.680740 [ANA_INIT] <<<<<<<<<<<<<
7144 11:13:10.683812 [Flow] Enable top DCM control >>>>>
7145 11:13:10.687127 [Flow] Enable top DCM control <<<<<
7146 11:13:10.690459 Enable DLL master slave shuffle
7147 11:13:10.693912 ==============================================================
7148 11:13:10.696930 Gating Mode config
7149 11:13:10.700594 ==============================================================
7150 11:13:10.703804 Config description:
7151 11:13:10.713516 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7152 11:13:10.720357 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7153 11:13:10.723442 SELPH_MODE 0: By rank 1: By Phase
7154 11:13:10.730072 ==============================================================
7155 11:13:10.733187 GAT_TRACK_EN = 1
7156 11:13:10.736332 RX_GATING_MODE = 2
7157 11:13:10.739934 RX_GATING_TRACK_MODE = 2
7158 11:13:10.742768 SELPH_MODE = 1
7159 11:13:10.746382 PICG_EARLY_EN = 1
7160 11:13:10.749388 VALID_LAT_VALUE = 1
7161 11:13:10.752852 ==============================================================
7162 11:13:10.756534 Enter into Gating configuration >>>>
7163 11:13:10.759378 Exit from Gating configuration <<<<
7164 11:13:10.762918 Enter into DVFS_PRE_config >>>>>
7165 11:13:10.775878 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7166 11:13:10.779423 Exit from DVFS_PRE_config <<<<<
7167 11:13:10.782399 Enter into PICG configuration >>>>
7168 11:13:10.782478 Exit from PICG configuration <<<<
7169 11:13:10.785986 [RX_INPUT] configuration >>>>>
7170 11:13:10.789016 [RX_INPUT] configuration <<<<<
7171 11:13:10.795669 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7172 11:13:10.798595 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7173 11:13:10.805731 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7174 11:13:10.811918 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7175 11:13:10.818720 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7176 11:13:10.825561 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7177 11:13:10.828538 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7178 11:13:10.831394 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7179 11:13:10.838111 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7180 11:13:10.841228 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7181 11:13:10.844911 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7182 11:13:10.851481 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7183 11:13:10.854501 ===================================
7184 11:13:10.854589 LPDDR4 DRAM CONFIGURATION
7185 11:13:10.857864 ===================================
7186 11:13:10.861458 EX_ROW_EN[0] = 0x0
7187 11:13:10.861542 EX_ROW_EN[1] = 0x0
7188 11:13:10.864388 LP4Y_EN = 0x0
7189 11:13:10.868126 WORK_FSP = 0x1
7190 11:13:10.868239 WL = 0x5
7191 11:13:10.870939 RL = 0x5
7192 11:13:10.871022 BL = 0x2
7193 11:13:10.874054 RPST = 0x0
7194 11:13:10.874137 RD_PRE = 0x0
7195 11:13:10.877531 WR_PRE = 0x1
7196 11:13:10.877614 WR_PST = 0x1
7197 11:13:10.880955 DBI_WR = 0x0
7198 11:13:10.881085 DBI_RD = 0x0
7199 11:13:10.884484 OTF = 0x1
7200 11:13:10.887451 ===================================
7201 11:13:10.890596 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7202 11:13:10.894333 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7203 11:13:10.900612 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7204 11:13:10.903904 ===================================
7205 11:13:10.904021 LPDDR4 DRAM CONFIGURATION
7206 11:13:10.907432 ===================================
7207 11:13:10.910841 EX_ROW_EN[0] = 0x10
7208 11:13:10.914255 EX_ROW_EN[1] = 0x0
7209 11:13:10.914343 LP4Y_EN = 0x0
7210 11:13:10.917235 WORK_FSP = 0x1
7211 11:13:10.917319 WL = 0x5
7212 11:13:10.920563 RL = 0x5
7213 11:13:10.920646 BL = 0x2
7214 11:13:10.923652 RPST = 0x0
7215 11:13:10.923735 RD_PRE = 0x0
7216 11:13:10.927339 WR_PRE = 0x1
7217 11:13:10.927426 WR_PST = 0x1
7218 11:13:10.930382 DBI_WR = 0x0
7219 11:13:10.930465 DBI_RD = 0x0
7220 11:13:10.933482 OTF = 0x1
7221 11:13:10.936936 ===================================
7222 11:13:10.943672 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7223 11:13:10.943757 ==
7224 11:13:10.947077 Dram Type= 6, Freq= 0, CH_0, rank 0
7225 11:13:10.950120 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7226 11:13:10.950209 ==
7227 11:13:10.953626 [Duty_Offset_Calibration]
7228 11:13:10.953709 B0:2 B1:0 CA:3
7229 11:13:10.953775
7230 11:13:10.956722 [DutyScan_Calibration_Flow] k_type=0
7231 11:13:10.967360
7232 11:13:10.967456 ==CLK 0==
7233 11:13:10.970767 Final CLK duty delay cell = 0
7234 11:13:10.974245 [0] MAX Duty = 5031%(X100), DQS PI = 12
7235 11:13:10.977417 [0] MIN Duty = 4907%(X100), DQS PI = 4
7236 11:13:10.977518 [0] AVG Duty = 4969%(X100)
7237 11:13:10.980669
7238 11:13:10.984246 CH0 CLK Duty spec in!! Max-Min= 124%
7239 11:13:10.987375 [DutyScan_Calibration_Flow] ====Done====
7240 11:13:10.987481
7241 11:13:10.990647 [DutyScan_Calibration_Flow] k_type=1
7242 11:13:11.007712
7243 11:13:11.007922 ==DQS 0 ==
7244 11:13:11.010371 Final DQS duty delay cell = 0
7245 11:13:11.013866 [0] MAX Duty = 5094%(X100), DQS PI = 14
7246 11:13:11.017530 [0] MIN Duty = 4875%(X100), DQS PI = 48
7247 11:13:11.020283 [0] AVG Duty = 4984%(X100)
7248 11:13:11.020369
7249 11:13:11.020435 ==DQS 1 ==
7250 11:13:11.023792 Final DQS duty delay cell = 0
7251 11:13:11.026784 [0] MAX Duty = 5156%(X100), DQS PI = 32
7252 11:13:11.030478 [0] MIN Duty = 5031%(X100), DQS PI = 12
7253 11:13:11.033546 [0] AVG Duty = 5093%(X100)
7254 11:13:11.033659
7255 11:13:11.037269 CH0 DQS 0 Duty spec in!! Max-Min= 219%
7256 11:13:11.037381
7257 11:13:11.040211 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7258 11:13:11.043403 [DutyScan_Calibration_Flow] ====Done====
7259 11:13:11.043487
7260 11:13:11.047028 [DutyScan_Calibration_Flow] k_type=3
7261 11:13:11.065305
7262 11:13:11.065469 ==DQM 0 ==
7263 11:13:11.068787 Final DQM duty delay cell = 0
7264 11:13:11.071792 [0] MAX Duty = 5156%(X100), DQS PI = 30
7265 11:13:11.075439 [0] MIN Duty = 4875%(X100), DQS PI = 46
7266 11:13:11.078365 [0] AVG Duty = 5015%(X100)
7267 11:13:11.078483
7268 11:13:11.078581 ==DQM 1 ==
7269 11:13:11.081835 Final DQM duty delay cell = 4
7270 11:13:11.085288 [4] MAX Duty = 5187%(X100), DQS PI = 60
7271 11:13:11.088090 [4] MIN Duty = 5031%(X100), DQS PI = 12
7272 11:13:11.091590 [4] AVG Duty = 5109%(X100)
7273 11:13:11.091696
7274 11:13:11.095034 CH0 DQM 0 Duty spec in!! Max-Min= 281%
7275 11:13:11.095138
7276 11:13:11.098656 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7277 11:13:11.101405 [DutyScan_Calibration_Flow] ====Done====
7278 11:13:11.101517
7279 11:13:11.105020 [DutyScan_Calibration_Flow] k_type=2
7280 11:13:11.121694
7281 11:13:11.121834 ==DQ 0 ==
7282 11:13:11.125158 Final DQ duty delay cell = -4
7283 11:13:11.128658 [-4] MAX Duty = 5000%(X100), DQS PI = 20
7284 11:13:11.131738 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7285 11:13:11.134816 [-4] AVG Duty = 4938%(X100)
7286 11:13:11.134923
7287 11:13:11.134990 ==DQ 1 ==
7288 11:13:11.138512 Final DQ duty delay cell = 0
7289 11:13:11.141659 [0] MAX Duty = 5156%(X100), DQS PI = 60
7290 11:13:11.145183 [0] MIN Duty = 5000%(X100), DQS PI = 16
7291 11:13:11.148194 [0] AVG Duty = 5078%(X100)
7292 11:13:11.148296
7293 11:13:11.151853 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7294 11:13:11.151944
7295 11:13:11.154924 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7296 11:13:11.157854 [DutyScan_Calibration_Flow] ====Done====
7297 11:13:11.157944 ==
7298 11:13:11.161416 Dram Type= 6, Freq= 0, CH_1, rank 0
7299 11:13:11.164718 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7300 11:13:11.164812 ==
7301 11:13:11.168278 [Duty_Offset_Calibration]
7302 11:13:11.168370 B0:1 B1:-2 CA:0
7303 11:13:11.168435
7304 11:13:11.171159 [DutyScan_Calibration_Flow] k_type=0
7305 11:13:11.182752
7306 11:13:11.182911 ==CLK 0==
7307 11:13:11.185858 Final CLK duty delay cell = 0
7308 11:13:11.188921 [0] MAX Duty = 5031%(X100), DQS PI = 0
7309 11:13:11.192156 [0] MIN Duty = 4876%(X100), DQS PI = 26
7310 11:13:11.195641 [0] AVG Duty = 4953%(X100)
7311 11:13:11.195747
7312 11:13:11.198622 CH1 CLK Duty spec in!! Max-Min= 155%
7313 11:13:11.201869 [DutyScan_Calibration_Flow] ====Done====
7314 11:13:11.201955
7315 11:13:11.205495 [DutyScan_Calibration_Flow] k_type=1
7316 11:13:11.221171
7317 11:13:11.221308 ==DQS 0 ==
7318 11:13:11.224515 Final DQS duty delay cell = -4
7319 11:13:11.227483 [-4] MAX Duty = 4938%(X100), DQS PI = 56
7320 11:13:11.231072 [-4] MIN Duty = 4844%(X100), DQS PI = 14
7321 11:13:11.234375 [-4] AVG Duty = 4891%(X100)
7322 11:13:11.234459
7323 11:13:11.234523 ==DQS 1 ==
7324 11:13:11.237709 Final DQS duty delay cell = 0
7325 11:13:11.241212 [0] MAX Duty = 5124%(X100), DQS PI = 30
7326 11:13:11.244346 [0] MIN Duty = 4813%(X100), DQS PI = 58
7327 11:13:11.247278 [0] AVG Duty = 4968%(X100)
7328 11:13:11.247366
7329 11:13:11.250814 CH1 DQS 0 Duty spec in!! Max-Min= 94%
7330 11:13:11.250912
7331 11:13:11.253927 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7332 11:13:11.257657 [DutyScan_Calibration_Flow] ====Done====
7333 11:13:11.257731
7334 11:13:11.260613 [DutyScan_Calibration_Flow] k_type=3
7335 11:13:11.278248
7336 11:13:11.278399 ==DQM 0 ==
7337 11:13:11.281602 Final DQM duty delay cell = 0
7338 11:13:11.285068 [0] MAX Duty = 5000%(X100), DQS PI = 0
7339 11:13:11.288567 [0] MIN Duty = 4844%(X100), DQS PI = 22
7340 11:13:11.291602 [0] AVG Duty = 4922%(X100)
7341 11:13:11.291706
7342 11:13:11.291825 ==DQM 1 ==
7343 11:13:11.295020 Final DQM duty delay cell = 0
7344 11:13:11.298302 [0] MAX Duty = 5062%(X100), DQS PI = 4
7345 11:13:11.301801 [0] MIN Duty = 4875%(X100), DQS PI = 38
7346 11:13:11.304811 [0] AVG Duty = 4968%(X100)
7347 11:13:11.304886
7348 11:13:11.308083 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7349 11:13:11.308159
7350 11:13:11.311591 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7351 11:13:11.314654 [DutyScan_Calibration_Flow] ====Done====
7352 11:13:11.314750
7353 11:13:11.317715 [DutyScan_Calibration_Flow] k_type=2
7354 11:13:11.335278
7355 11:13:11.335439 ==DQ 0 ==
7356 11:13:11.338498 Final DQ duty delay cell = 0
7357 11:13:11.341845 [0] MAX Duty = 5093%(X100), DQS PI = 52
7358 11:13:11.344940 [0] MIN Duty = 4938%(X100), DQS PI = 14
7359 11:13:11.348498 [0] AVG Duty = 5015%(X100)
7360 11:13:11.348601
7361 11:13:11.348670 ==DQ 1 ==
7362 11:13:11.351602 Final DQ duty delay cell = 0
7363 11:13:11.355145 [0] MAX Duty = 5156%(X100), DQS PI = 26
7364 11:13:11.358204 [0] MIN Duty = 4907%(X100), DQS PI = 56
7365 11:13:11.361344 [0] AVG Duty = 5031%(X100)
7366 11:13:11.361425
7367 11:13:11.365000 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7368 11:13:11.365079
7369 11:13:11.367881 CH1 DQ 1 Duty spec in!! Max-Min= 249%
7370 11:13:11.371492 [DutyScan_Calibration_Flow] ====Done====
7371 11:13:11.374508 nWR fixed to 30
7372 11:13:11.378076 [ModeRegInit_LP4] CH0 RK0
7373 11:13:11.378162 [ModeRegInit_LP4] CH0 RK1
7374 11:13:11.381263 [ModeRegInit_LP4] CH1 RK0
7375 11:13:11.384320 [ModeRegInit_LP4] CH1 RK1
7376 11:13:11.384407 match AC timing 5
7377 11:13:11.391795 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7378 11:13:11.394234 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7379 11:13:11.397616 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7380 11:13:11.404538 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7381 11:13:11.407322 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7382 11:13:11.407421 [MiockJmeterHQA]
7383 11:13:11.407486
7384 11:13:11.410710 [DramcMiockJmeter] u1RxGatingPI = 0
7385 11:13:11.414129 0 : 4368, 4140
7386 11:13:11.414224 4 : 4252, 4027
7387 11:13:11.417627 8 : 4252, 4027
7388 11:13:11.417722 12 : 4252, 4027
7389 11:13:11.420681 16 : 4252, 4027
7390 11:13:11.420770 20 : 4253, 4027
7391 11:13:11.420837 24 : 4255, 4029
7392 11:13:11.424331 28 : 4252, 4027
7393 11:13:11.424418 32 : 4252, 4027
7394 11:13:11.427469 36 : 4365, 4140
7395 11:13:11.427556 40 : 4253, 4027
7396 11:13:11.430570 44 : 4255, 4029
7397 11:13:11.430657 48 : 4253, 4026
7398 11:13:11.434219 52 : 4363, 4138
7399 11:13:11.434314 56 : 4252, 4027
7400 11:13:11.434412 60 : 4361, 4137
7401 11:13:11.437606 64 : 4252, 4027
7402 11:13:11.437697 68 : 4250, 4026
7403 11:13:11.440664 72 : 4250, 4027
7404 11:13:11.440755 76 : 4252, 4029
7405 11:13:11.444137 80 : 4361, 4137
7406 11:13:11.444228 84 : 4250, 4026
7407 11:13:11.447567 88 : 4360, 4138
7408 11:13:11.447660 92 : 4250, 4027
7409 11:13:11.447727 96 : 4250, 4027
7410 11:13:11.450737 100 : 4250, 4027
7411 11:13:11.450890 104 : 4250, 3773
7412 11:13:11.454212 108 : 4252, 10
7413 11:13:11.454310 112 : 4250, 0
7414 11:13:11.457048 116 : 4250, 0
7415 11:13:11.457138 120 : 4361, 0
7416 11:13:11.457242 124 : 4250, 0
7417 11:13:11.460621 128 : 4250, 0
7418 11:13:11.460716 132 : 4250, 0
7419 11:13:11.463734 136 : 4360, 0
7420 11:13:11.463822 140 : 4361, 0
7421 11:13:11.463888 144 : 4252, 0
7422 11:13:11.467665 148 : 4250, 0
7423 11:13:11.467755 152 : 4363, 0
7424 11:13:11.467823 156 : 4250, 0
7425 11:13:11.470415 160 : 4250, 0
7426 11:13:11.470502 164 : 4250, 0
7427 11:13:11.474140 168 : 4252, 0
7428 11:13:11.474231 172 : 4250, 0
7429 11:13:11.474299 176 : 4250, 0
7430 11:13:11.477283 180 : 4252, 0
7431 11:13:11.477370 184 : 4361, 0
7432 11:13:11.480377 188 : 4361, 0
7433 11:13:11.480466 192 : 4250, 0
7434 11:13:11.480533 196 : 4250, 0
7435 11:13:11.484043 200 : 4361, 0
7436 11:13:11.484132 204 : 4250, 0
7437 11:13:11.487188 208 : 4250, 0
7438 11:13:11.487278 212 : 4249, 0
7439 11:13:11.487345 216 : 4250, 0
7440 11:13:11.490514 220 : 4252, 0
7441 11:13:11.490602 224 : 4250, 0
7442 11:13:11.493928 228 : 4250, 0
7443 11:13:11.494017 232 : 4252, 0
7444 11:13:11.494085 236 : 4361, 1048
7445 11:13:11.496655 240 : 4250, 4026
7446 11:13:11.496743 244 : 4250, 4027
7447 11:13:11.500109 248 : 4360, 4138
7448 11:13:11.500201 252 : 4361, 4137
7449 11:13:11.503614 256 : 4250, 4026
7450 11:13:11.503706 260 : 4363, 4139
7451 11:13:11.506648 264 : 4361, 4137
7452 11:13:11.506766 268 : 4250, 4027
7453 11:13:11.509900 272 : 4250, 4027
7454 11:13:11.510020 276 : 4253, 4029
7455 11:13:11.513279 280 : 4250, 4027
7456 11:13:11.513402 284 : 4250, 4027
7457 11:13:11.513493 288 : 4250, 4027
7458 11:13:11.516980 292 : 4253, 4029
7459 11:13:11.517083 296 : 4250, 4027
7460 11:13:11.520185 300 : 4360, 4138
7461 11:13:11.520286 304 : 4361, 4137
7462 11:13:11.523103 308 : 4250, 4026
7463 11:13:11.523197 312 : 4363, 4139
7464 11:13:11.526610 316 : 4250, 4027
7465 11:13:11.526706 320 : 4249, 4027
7466 11:13:11.529623 324 : 4250, 4027
7467 11:13:11.529720 328 : 4253, 4029
7468 11:13:11.533392 332 : 4250, 4027
7469 11:13:11.533492 336 : 4250, 4027
7470 11:13:11.536445 340 : 4250, 4027
7471 11:13:11.536547 344 : 4253, 4029
7472 11:13:11.540260 348 : 4250, 4027
7473 11:13:11.540405 352 : 4360, 4136
7474 11:13:11.540516 356 : 4360, 3167
7475 11:13:11.542784 360 : 4250, 4
7476 11:13:11.542906
7477 11:13:11.546456 MIOCK jitter meter ch=0
7478 11:13:11.546547
7479 11:13:11.549510 1T = (360-108) = 252 dly cells
7480 11:13:11.553186 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7481 11:13:11.553284 ==
7482 11:13:11.556105 Dram Type= 6, Freq= 0, CH_0, rank 0
7483 11:13:11.562773 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7484 11:13:11.562917 ==
7485 11:13:11.566023 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7486 11:13:11.569807 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7487 11:13:11.576091 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7488 11:13:11.582710 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7489 11:13:11.590208 [CA 0] Center 44 (14~75) winsize 62
7490 11:13:11.593324 [CA 1] Center 43 (13~74) winsize 62
7491 11:13:11.596861 [CA 2] Center 39 (10~69) winsize 60
7492 11:13:11.600326 [CA 3] Center 39 (10~68) winsize 59
7493 11:13:11.603869 [CA 4] Center 37 (8~67) winsize 60
7494 11:13:11.606666 [CA 5] Center 37 (7~67) winsize 61
7495 11:13:11.606758
7496 11:13:11.610288 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7497 11:13:11.610470
7498 11:13:11.616632 [CATrainingPosCal] consider 1 rank data
7499 11:13:11.616802 u2DelayCellTimex100 = 258/100 ps
7500 11:13:11.623412 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7501 11:13:11.626559 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7502 11:13:11.629906 CA2 delay=39 (10~69),Diff = 2 PI (7 cell)
7503 11:13:11.633591 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7504 11:13:11.636388 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7505 11:13:11.639492 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7506 11:13:11.639637
7507 11:13:11.643163 CA PerBit enable=1, Macro0, CA PI delay=37
7508 11:13:11.643299
7509 11:13:11.646223 [CBTSetCACLKResult] CA Dly = 37
7510 11:13:11.649823 CS Dly: 11 (0~42)
7511 11:13:11.653254 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7512 11:13:11.656320 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7513 11:13:11.656448 ==
7514 11:13:11.659368 Dram Type= 6, Freq= 0, CH_0, rank 1
7515 11:13:11.666366 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7516 11:13:11.666493 ==
7517 11:13:11.669281 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7518 11:13:11.676093 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7519 11:13:11.679156 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7520 11:13:11.685911 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7521 11:13:11.693939 [CA 0] Center 44 (14~75) winsize 62
7522 11:13:11.697618 [CA 1] Center 43 (13~74) winsize 62
7523 11:13:11.700717 [CA 2] Center 39 (10~69) winsize 60
7524 11:13:11.703755 [CA 3] Center 39 (10~69) winsize 60
7525 11:13:11.707258 [CA 4] Center 37 (8~67) winsize 60
7526 11:13:11.710737 [CA 5] Center 37 (7~67) winsize 61
7527 11:13:11.710892
7528 11:13:11.713606 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7529 11:13:11.713752
7530 11:13:11.720807 [CATrainingPosCal] consider 2 rank data
7531 11:13:11.720917 u2DelayCellTimex100 = 258/100 ps
7532 11:13:11.726901 CA0 delay=44 (14~75),Diff = 7 PI (26 cell)
7533 11:13:11.730321 CA1 delay=43 (13~74),Diff = 6 PI (22 cell)
7534 11:13:11.733742 CA2 delay=39 (10~69),Diff = 2 PI (7 cell)
7535 11:13:11.737345 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7536 11:13:11.740137 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7537 11:13:11.743137 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7538 11:13:11.743221
7539 11:13:11.746811 CA PerBit enable=1, Macro0, CA PI delay=37
7540 11:13:11.746917
7541 11:13:11.749869 [CBTSetCACLKResult] CA Dly = 37
7542 11:13:11.753534 CS Dly: 11 (0~43)
7543 11:13:11.756868 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7544 11:13:11.759873 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7545 11:13:11.759957
7546 11:13:11.763592 ----->DramcWriteLeveling(PI) begin...
7547 11:13:11.766582 ==
7548 11:13:11.766666 Dram Type= 6, Freq= 0, CH_0, rank 0
7549 11:13:11.773058 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7550 11:13:11.773146 ==
7551 11:13:11.776574 Write leveling (Byte 0): 36 => 36
7552 11:13:11.779832 Write leveling (Byte 1): 28 => 28
7553 11:13:11.783372 DramcWriteLeveling(PI) end<-----
7554 11:13:11.783457
7555 11:13:11.783523 ==
7556 11:13:11.786453 Dram Type= 6, Freq= 0, CH_0, rank 0
7557 11:13:11.789503 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7558 11:13:11.789595 ==
7559 11:13:11.793200 [Gating] SW mode calibration
7560 11:13:11.799640 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7561 11:13:11.806054 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7562 11:13:11.809119 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7563 11:13:11.812731 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7564 11:13:11.819330 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7565 11:13:11.822434 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7566 11:13:11.825942 1 4 16 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
7567 11:13:11.832222 1 4 20 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
7568 11:13:11.835683 1 4 24 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
7569 11:13:11.839139 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7570 11:13:11.845419 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7571 11:13:11.848483 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7572 11:13:11.852209 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7573 11:13:11.858196 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7574 11:13:11.861883 1 5 16 | B1->B0 | 3434 3030 | 1 0 | (1 1) (1 0)
7575 11:13:11.864909 1 5 20 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
7576 11:13:11.871506 1 5 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
7577 11:13:11.874634 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7578 11:13:11.878298 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7579 11:13:11.884647 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7580 11:13:11.888017 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7581 11:13:11.891156 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7582 11:13:11.897768 1 6 16 | B1->B0 | 2323 3737 | 0 0 | (0 0) (1 1)
7583 11:13:11.900907 1 6 20 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
7584 11:13:11.904611 1 6 24 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
7585 11:13:11.910732 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7586 11:13:11.914460 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7587 11:13:11.917422 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7588 11:13:11.923858 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7589 11:13:11.927120 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7590 11:13:11.930625 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7591 11:13:11.937445 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7592 11:13:11.940444 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7593 11:13:11.943829 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7594 11:13:11.950148 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7595 11:13:11.953683 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 11:13:11.956782 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 11:13:11.963654 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7598 11:13:11.967121 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7599 11:13:11.969996 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7600 11:13:11.976899 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7601 11:13:11.979997 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7602 11:13:11.983661 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7603 11:13:11.990143 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7604 11:13:11.993148 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7605 11:13:11.996560 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7606 11:13:12.002947 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7607 11:13:12.006606 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7608 11:13:12.009737 Total UI for P1: 0, mck2ui 16
7609 11:13:12.013455 best dqsien dly found for B0: ( 1, 9, 14)
7610 11:13:12.016509 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7611 11:13:12.023128 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7612 11:13:12.026478 Total UI for P1: 0, mck2ui 16
7613 11:13:12.029487 best dqsien dly found for B1: ( 1, 9, 22)
7614 11:13:12.032896 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7615 11:13:12.036382 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7616 11:13:12.036466
7617 11:13:12.039786 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7618 11:13:12.042945 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7619 11:13:12.045928 [Gating] SW calibration Done
7620 11:13:12.046015 ==
7621 11:13:12.049481 Dram Type= 6, Freq= 0, CH_0, rank 0
7622 11:13:12.052812 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7623 11:13:12.052897 ==
7624 11:13:12.056100 RX Vref Scan: 0
7625 11:13:12.056210
7626 11:13:12.059159 RX Vref 0 -> 0, step: 1
7627 11:13:12.059246
7628 11:13:12.059319 RX Delay 0 -> 252, step: 8
7629 11:13:12.065799 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
7630 11:13:12.069532 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
7631 11:13:12.072771 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7632 11:13:12.075982 iDelay=200, Bit 3, Center 119 (64 ~ 175) 112
7633 11:13:12.079188 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
7634 11:13:12.085648 iDelay=200, Bit 5, Center 111 (56 ~ 167) 112
7635 11:13:12.088572 iDelay=200, Bit 6, Center 135 (80 ~ 191) 112
7636 11:13:12.092093 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
7637 11:13:12.095334 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7638 11:13:12.099053 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7639 11:13:12.105450 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
7640 11:13:12.108373 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7641 11:13:12.111964 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
7642 11:13:12.115311 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
7643 11:13:12.121890 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7644 11:13:12.125222 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7645 11:13:12.125308 ==
7646 11:13:12.128593 Dram Type= 6, Freq= 0, CH_0, rank 0
7647 11:13:12.131493 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7648 11:13:12.131578 ==
7649 11:13:12.135059 DQS Delay:
7650 11:13:12.135144 DQS0 = 0, DQS1 = 0
7651 11:13:12.135209 DQM Delay:
7652 11:13:12.137955 DQM0 = 127, DQM1 = 124
7653 11:13:12.138038 DQ Delay:
7654 11:13:12.141971 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =119
7655 11:13:12.144747 DQ4 =127, DQ5 =111, DQ6 =135, DQ7 =143
7656 11:13:12.151574 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =119
7657 11:13:12.154467 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
7658 11:13:12.154557
7659 11:13:12.154623
7660 11:13:12.154706 ==
7661 11:13:12.158197 Dram Type= 6, Freq= 0, CH_0, rank 0
7662 11:13:12.161056 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7663 11:13:12.161143 ==
7664 11:13:12.161210
7665 11:13:12.161271
7666 11:13:12.164565 TX Vref Scan disable
7667 11:13:12.167652 == TX Byte 0 ==
7668 11:13:12.171405 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
7669 11:13:12.174569 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
7670 11:13:12.177800 == TX Byte 1 ==
7671 11:13:12.181090 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7672 11:13:12.184521 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7673 11:13:12.184606 ==
7674 11:13:12.187582 Dram Type= 6, Freq= 0, CH_0, rank 0
7675 11:13:12.190604 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7676 11:13:12.194085 ==
7677 11:13:12.206237
7678 11:13:12.209954 TX Vref early break, caculate TX vref
7679 11:13:12.212781 TX Vref=16, minBit 8, minWin=21, winSum=358
7680 11:13:12.216389 TX Vref=18, minBit 11, minWin=21, winSum=371
7681 11:13:12.219453 TX Vref=20, minBit 8, minWin=22, winSum=381
7682 11:13:12.222773 TX Vref=22, minBit 8, minWin=23, winSum=389
7683 11:13:12.226316 TX Vref=24, minBit 8, minWin=24, winSum=403
7684 11:13:12.232652 TX Vref=26, minBit 4, minWin=24, winSum=408
7685 11:13:12.236200 TX Vref=28, minBit 8, minWin=24, winSum=412
7686 11:13:12.239759 TX Vref=30, minBit 8, minWin=24, winSum=402
7687 11:13:12.242742 TX Vref=32, minBit 8, minWin=23, winSum=394
7688 11:13:12.246213 TX Vref=34, minBit 8, minWin=22, winSum=385
7689 11:13:12.252572 [TxChooseVref] Worse bit 8, Min win 24, Win sum 412, Final Vref 28
7690 11:13:12.252676
7691 11:13:12.256003 Final TX Range 0 Vref 28
7692 11:13:12.256085
7693 11:13:12.256149 ==
7694 11:13:12.258811 Dram Type= 6, Freq= 0, CH_0, rank 0
7695 11:13:12.262350 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7696 11:13:12.262429 ==
7697 11:13:12.262499
7698 11:13:12.262560
7699 11:13:12.265810 TX Vref Scan disable
7700 11:13:12.272179 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7701 11:13:12.272264 == TX Byte 0 ==
7702 11:13:12.275355 u2DelayCellOfst[0]=15 cells (4 PI)
7703 11:13:12.279084 u2DelayCellOfst[1]=18 cells (5 PI)
7704 11:13:12.282176 u2DelayCellOfst[2]=11 cells (3 PI)
7705 11:13:12.285353 u2DelayCellOfst[3]=15 cells (4 PI)
7706 11:13:12.288620 u2DelayCellOfst[4]=11 cells (3 PI)
7707 11:13:12.292125 u2DelayCellOfst[5]=0 cells (0 PI)
7708 11:13:12.295124 u2DelayCellOfst[6]=18 cells (5 PI)
7709 11:13:12.298630 u2DelayCellOfst[7]=18 cells (5 PI)
7710 11:13:12.302153 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7711 11:13:12.305185 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7712 11:13:12.308205 == TX Byte 1 ==
7713 11:13:12.311835 u2DelayCellOfst[8]=0 cells (0 PI)
7714 11:13:12.314769 u2DelayCellOfst[9]=3 cells (1 PI)
7715 11:13:12.318367 u2DelayCellOfst[10]=7 cells (2 PI)
7716 11:13:12.321784 u2DelayCellOfst[11]=7 cells (2 PI)
7717 11:13:12.324887 u2DelayCellOfst[12]=15 cells (4 PI)
7718 11:13:12.324971 u2DelayCellOfst[13]=11 cells (3 PI)
7719 11:13:12.328465 u2DelayCellOfst[14]=15 cells (4 PI)
7720 11:13:12.331609 u2DelayCellOfst[15]=11 cells (3 PI)
7721 11:13:12.337836 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7722 11:13:12.341364 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7723 11:13:12.344725 DramC Write-DBI on
7724 11:13:12.344826 ==
7725 11:13:12.348182 Dram Type= 6, Freq= 0, CH_0, rank 0
7726 11:13:12.351593 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7727 11:13:12.351686 ==
7728 11:13:12.351753
7729 11:13:12.351815
7730 11:13:12.354635 TX Vref Scan disable
7731 11:13:12.354745 == TX Byte 0 ==
7732 11:13:12.361407 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
7733 11:13:12.361518 == TX Byte 1 ==
7734 11:13:12.364679 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7735 11:13:12.368022 DramC Write-DBI off
7736 11:13:12.368107
7737 11:13:12.368176 [DATLAT]
7738 11:13:12.371465 Freq=1600, CH0 RK0
7739 11:13:12.371549
7740 11:13:12.371614 DATLAT Default: 0xf
7741 11:13:12.374359 0, 0xFFFF, sum = 0
7742 11:13:12.374444 1, 0xFFFF, sum = 0
7743 11:13:12.377828 2, 0xFFFF, sum = 0
7744 11:13:12.380883 3, 0xFFFF, sum = 0
7745 11:13:12.380966 4, 0xFFFF, sum = 0
7746 11:13:12.384496 5, 0xFFFF, sum = 0
7747 11:13:12.384581 6, 0xFFFF, sum = 0
7748 11:13:12.387559 7, 0xFFFF, sum = 0
7749 11:13:12.387643 8, 0xFFFF, sum = 0
7750 11:13:12.391130 9, 0xFFFF, sum = 0
7751 11:13:12.391214 10, 0xFFFF, sum = 0
7752 11:13:12.394461 11, 0xFFFF, sum = 0
7753 11:13:12.394545 12, 0xFFFF, sum = 0
7754 11:13:12.397401 13, 0xEFFF, sum = 0
7755 11:13:12.397486 14, 0x0, sum = 1
7756 11:13:12.400831 15, 0x0, sum = 2
7757 11:13:12.400916 16, 0x0, sum = 3
7758 11:13:12.404434 17, 0x0, sum = 4
7759 11:13:12.404518 best_step = 15
7760 11:13:12.404584
7761 11:13:12.404645 ==
7762 11:13:12.407529 Dram Type= 6, Freq= 0, CH_0, rank 0
7763 11:13:12.414102 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7764 11:13:12.414198 ==
7765 11:13:12.414265 RX Vref Scan: 1
7766 11:13:12.414327
7767 11:13:12.417041 Set Vref Range= 24 -> 127
7768 11:13:12.417124
7769 11:13:12.420802 RX Vref 24 -> 127, step: 1
7770 11:13:12.420886
7771 11:13:12.420951 RX Delay 11 -> 252, step: 4
7772 11:13:12.423759
7773 11:13:12.423842 Set Vref, RX VrefLevel [Byte0]: 24
7774 11:13:12.427111 [Byte1]: 24
7775 11:13:12.431389
7776 11:13:12.431475 Set Vref, RX VrefLevel [Byte0]: 25
7777 11:13:12.434390 [Byte1]: 25
7778 11:13:12.438821
7779 11:13:12.438930 Set Vref, RX VrefLevel [Byte0]: 26
7780 11:13:12.442360 [Byte1]: 26
7781 11:13:12.446561
7782 11:13:12.446648 Set Vref, RX VrefLevel [Byte0]: 27
7783 11:13:12.450196 [Byte1]: 27
7784 11:13:12.454187
7785 11:13:12.454278 Set Vref, RX VrefLevel [Byte0]: 28
7786 11:13:12.457705 [Byte1]: 28
7787 11:13:12.461937
7788 11:13:12.462028 Set Vref, RX VrefLevel [Byte0]: 29
7789 11:13:12.465258 [Byte1]: 29
7790 11:13:12.469350
7791 11:13:12.469443 Set Vref, RX VrefLevel [Byte0]: 30
7792 11:13:12.472591 [Byte1]: 30
7793 11:13:12.477217
7794 11:13:12.477306 Set Vref, RX VrefLevel [Byte0]: 31
7795 11:13:12.479996 [Byte1]: 31
7796 11:13:12.484373
7797 11:13:12.484465 Set Vref, RX VrefLevel [Byte0]: 32
7798 11:13:12.488124 [Byte1]: 32
7799 11:13:12.492520
7800 11:13:12.492620 Set Vref, RX VrefLevel [Byte0]: 33
7801 11:13:12.495630 [Byte1]: 33
7802 11:13:12.499740
7803 11:13:12.499850 Set Vref, RX VrefLevel [Byte0]: 34
7804 11:13:12.503186 [Byte1]: 34
7805 11:13:12.507177
7806 11:13:12.507276 Set Vref, RX VrefLevel [Byte0]: 35
7807 11:13:12.510894 [Byte1]: 35
7808 11:13:12.515195
7809 11:13:12.515306 Set Vref, RX VrefLevel [Byte0]: 36
7810 11:13:12.518784 [Byte1]: 36
7811 11:13:12.522791
7812 11:13:12.522932 Set Vref, RX VrefLevel [Byte0]: 37
7813 11:13:12.525895 [Byte1]: 37
7814 11:13:12.530182
7815 11:13:12.530283 Set Vref, RX VrefLevel [Byte0]: 38
7816 11:13:12.533773 [Byte1]: 38
7817 11:13:12.538100
7818 11:13:12.538200 Set Vref, RX VrefLevel [Byte0]: 39
7819 11:13:12.541136 [Byte1]: 39
7820 11:13:12.545499
7821 11:13:12.545609 Set Vref, RX VrefLevel [Byte0]: 40
7822 11:13:12.548505 [Byte1]: 40
7823 11:13:12.552974
7824 11:13:12.553125 Set Vref, RX VrefLevel [Byte0]: 41
7825 11:13:12.556301 [Byte1]: 41
7826 11:13:12.560857
7827 11:13:12.560933 Set Vref, RX VrefLevel [Byte0]: 42
7828 11:13:12.563835 [Byte1]: 42
7829 11:13:12.568366
7830 11:13:12.568472 Set Vref, RX VrefLevel [Byte0]: 43
7831 11:13:12.571778 [Byte1]: 43
7832 11:13:12.575711
7833 11:13:12.575826 Set Vref, RX VrefLevel [Byte0]: 44
7834 11:13:12.579038 [Byte1]: 44
7835 11:13:12.583447
7836 11:13:12.583527 Set Vref, RX VrefLevel [Byte0]: 45
7837 11:13:12.586807 [Byte1]: 45
7838 11:13:12.590964
7839 11:13:12.591072 Set Vref, RX VrefLevel [Byte0]: 46
7840 11:13:12.594637 [Byte1]: 46
7841 11:13:12.599286
7842 11:13:12.599399 Set Vref, RX VrefLevel [Byte0]: 47
7843 11:13:12.602218 [Byte1]: 47
7844 11:13:12.606487
7845 11:13:12.606595 Set Vref, RX VrefLevel [Byte0]: 48
7846 11:13:12.609729 [Byte1]: 48
7847 11:13:12.613721
7848 11:13:12.613866 Set Vref, RX VrefLevel [Byte0]: 49
7849 11:13:12.617370 [Byte1]: 49
7850 11:13:12.621519
7851 11:13:12.621622 Set Vref, RX VrefLevel [Byte0]: 50
7852 11:13:12.625058 [Byte1]: 50
7853 11:13:12.629285
7854 11:13:12.629395 Set Vref, RX VrefLevel [Byte0]: 51
7855 11:13:12.632331 [Byte1]: 51
7856 11:13:12.637032
7857 11:13:12.637141 Set Vref, RX VrefLevel [Byte0]: 52
7858 11:13:12.639931 [Byte1]: 52
7859 11:13:12.644430
7860 11:13:12.644535 Set Vref, RX VrefLevel [Byte0]: 53
7861 11:13:12.647979 [Byte1]: 53
7862 11:13:12.652364
7863 11:13:12.652467 Set Vref, RX VrefLevel [Byte0]: 54
7864 11:13:12.655437 [Byte1]: 54
7865 11:13:12.659567
7866 11:13:12.659670 Set Vref, RX VrefLevel [Byte0]: 55
7867 11:13:12.662954 [Byte1]: 55
7868 11:13:12.667006
7869 11:13:12.667155 Set Vref, RX VrefLevel [Byte0]: 56
7870 11:13:12.670480 [Byte1]: 56
7871 11:13:12.674695
7872 11:13:12.674820 Set Vref, RX VrefLevel [Byte0]: 57
7873 11:13:12.678052 [Byte1]: 57
7874 11:13:12.682241
7875 11:13:12.682320 Set Vref, RX VrefLevel [Byte0]: 58
7876 11:13:12.685598 [Byte1]: 58
7877 11:13:12.690215
7878 11:13:12.690297 Set Vref, RX VrefLevel [Byte0]: 59
7879 11:13:12.693049 [Byte1]: 59
7880 11:13:12.697953
7881 11:13:12.698036 Set Vref, RX VrefLevel [Byte0]: 60
7882 11:13:12.701025 [Byte1]: 60
7883 11:13:12.705314
7884 11:13:12.705422 Set Vref, RX VrefLevel [Byte0]: 61
7885 11:13:12.708266 [Byte1]: 61
7886 11:13:12.712811
7887 11:13:12.712899 Set Vref, RX VrefLevel [Byte0]: 62
7888 11:13:12.716386 [Byte1]: 62
7889 11:13:12.720426
7890 11:13:12.720513 Set Vref, RX VrefLevel [Byte0]: 63
7891 11:13:12.724559 [Byte1]: 63
7892 11:13:12.728242
7893 11:13:12.728377 Set Vref, RX VrefLevel [Byte0]: 64
7894 11:13:12.731515 [Byte1]: 64
7895 11:13:12.735760
7896 11:13:12.735922 Set Vref, RX VrefLevel [Byte0]: 65
7897 11:13:12.739467 [Byte1]: 65
7898 11:13:12.743427
7899 11:13:12.743587 Set Vref, RX VrefLevel [Byte0]: 66
7900 11:13:12.746497 [Byte1]: 66
7901 11:13:12.751383
7902 11:13:12.751551 Set Vref, RX VrefLevel [Byte0]: 67
7903 11:13:12.754688 [Byte1]: 67
7904 11:13:12.759022
7905 11:13:12.759200 Set Vref, RX VrefLevel [Byte0]: 68
7906 11:13:12.761967 [Byte1]: 68
7907 11:13:12.766298
7908 11:13:12.766488 Set Vref, RX VrefLevel [Byte0]: 69
7909 11:13:12.769589 [Byte1]: 69
7910 11:13:12.774041
7911 11:13:12.774273 Set Vref, RX VrefLevel [Byte0]: 70
7912 11:13:12.777560 [Byte1]: 70
7913 11:13:12.781593
7914 11:13:12.781749 Set Vref, RX VrefLevel [Byte0]: 71
7915 11:13:12.784967 [Byte1]: 71
7916 11:13:12.788990
7917 11:13:12.789246 Set Vref, RX VrefLevel [Byte0]: 72
7918 11:13:12.792314 [Byte1]: 72
7919 11:13:12.797041
7920 11:13:12.797356 Set Vref, RX VrefLevel [Byte0]: 73
7921 11:13:12.799981 [Byte1]: 73
7922 11:13:12.804807
7923 11:13:12.805184 Set Vref, RX VrefLevel [Byte0]: 74
7924 11:13:12.807788 [Byte1]: 74
7925 11:13:12.812103
7926 11:13:12.812580 Set Vref, RX VrefLevel [Byte0]: 75
7927 11:13:12.815125 [Byte1]: 75
7928 11:13:12.819877
7929 11:13:12.820239 Set Vref, RX VrefLevel [Byte0]: 76
7930 11:13:12.823077 [Byte1]: 76
7931 11:13:12.827201
7932 11:13:12.827559 Final RX Vref Byte 0 = 62 to rank0
7933 11:13:12.830864 Final RX Vref Byte 1 = 58 to rank0
7934 11:13:12.833999 Final RX Vref Byte 0 = 62 to rank1
7935 11:13:12.837461 Final RX Vref Byte 1 = 58 to rank1==
7936 11:13:12.840764 Dram Type= 6, Freq= 0, CH_0, rank 0
7937 11:13:12.847331 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7938 11:13:12.847722 ==
7939 11:13:12.848016 DQS Delay:
7940 11:13:12.851002 DQS0 = 0, DQS1 = 0
7941 11:13:12.851369 DQM Delay:
7942 11:13:12.851724 DQM0 = 126, DQM1 = 120
7943 11:13:12.854025 DQ Delay:
7944 11:13:12.857094 DQ0 =126, DQ1 =128, DQ2 =126, DQ3 =122
7945 11:13:12.860680 DQ4 =126, DQ5 =112, DQ6 =132, DQ7 =138
7946 11:13:12.863583 DQ8 =112, DQ9 =108, DQ10 =120, DQ11 =114
7947 11:13:12.867337 DQ12 =126, DQ13 =124, DQ14 =130, DQ15 =128
7948 11:13:12.867896
7949 11:13:12.868246
7950 11:13:12.868540
7951 11:13:12.870284 [DramC_TX_OE_Calibration] TA2
7952 11:13:12.874013 Original DQ_B0 (3 6) =30, OEN = 27
7953 11:13:12.876820 Original DQ_B1 (3 6) =30, OEN = 27
7954 11:13:12.880224 24, 0x0, End_B0=24 End_B1=24
7955 11:13:12.883547 25, 0x0, End_B0=25 End_B1=25
7956 11:13:12.883944 26, 0x0, End_B0=26 End_B1=26
7957 11:13:12.887349 27, 0x0, End_B0=27 End_B1=27
7958 11:13:12.889981 28, 0x0, End_B0=28 End_B1=28
7959 11:13:12.893513 29, 0x0, End_B0=29 End_B1=29
7960 11:13:12.893903 30, 0x0, End_B0=30 End_B1=30
7961 11:13:12.896753 31, 0x4141, End_B0=30 End_B1=30
7962 11:13:12.899662 Byte0 end_step=30 best_step=27
7963 11:13:12.903074 Byte1 end_step=30 best_step=27
7964 11:13:12.906447 Byte0 TX OE(2T, 0.5T) = (3, 3)
7965 11:13:12.909779 Byte1 TX OE(2T, 0.5T) = (3, 3)
7966 11:13:12.910140
7967 11:13:12.910424
7968 11:13:12.916482 [DQSOSCAuto] RK0, (LSB)MR18= 0x1414, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
7969 11:13:12.919614 CH0 RK0: MR19=303, MR18=1414
7970 11:13:12.926123 CH0_RK0: MR19=0x303, MR18=0x1414, DQSOSC=399, MR23=63, INC=23, DEC=15
7971 11:13:12.926510
7972 11:13:12.929281 ----->DramcWriteLeveling(PI) begin...
7973 11:13:12.929666 ==
7974 11:13:12.932642 Dram Type= 6, Freq= 0, CH_0, rank 1
7975 11:13:12.936147 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7976 11:13:12.936471 ==
7977 11:13:12.939357 Write leveling (Byte 0): 31 => 31
7978 11:13:12.942440 Write leveling (Byte 1): 27 => 27
7979 11:13:12.946171 DramcWriteLeveling(PI) end<-----
7980 11:13:12.946572
7981 11:13:12.946889 ==
7982 11:13:12.949254 Dram Type= 6, Freq= 0, CH_0, rank 1
7983 11:13:12.952543 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7984 11:13:12.955921 ==
7985 11:13:12.956293 [Gating] SW mode calibration
7986 11:13:12.966455 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7987 11:13:12.969304 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7988 11:13:12.972729 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7989 11:13:12.979249 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7990 11:13:12.982371 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7991 11:13:12.985906 1 4 12 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
7992 11:13:12.992094 1 4 16 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
7993 11:13:12.995585 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7994 11:13:12.999058 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7995 11:13:13.005183 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7996 11:13:13.008589 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7997 11:13:13.011968 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7998 11:13:13.018705 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7999 11:13:13.021698 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 0)
8000 11:13:13.025336 1 5 16 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
8001 11:13:13.032206 1 5 20 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
8002 11:13:13.035248 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8003 11:13:13.038453 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8004 11:13:13.045174 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8005 11:13:13.048422 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8006 11:13:13.051581 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8007 11:13:13.058285 1 6 12 | B1->B0 | 2323 4343 | 0 0 | (0 0) (0 0)
8008 11:13:13.061263 1 6 16 | B1->B0 | 2d2d 4646 | 0 0 | (0 0) (0 0)
8009 11:13:13.064696 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8010 11:13:13.071441 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8011 11:13:13.074635 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8012 11:13:13.077676 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8013 11:13:13.084381 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8014 11:13:13.087534 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8015 11:13:13.091039 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8016 11:13:13.097556 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8017 11:13:13.100932 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8018 11:13:13.106444 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8019 11:13:13.110768 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8020 11:13:13.114086 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 11:13:13.117502 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 11:13:13.124284 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 11:13:13.127799 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 11:13:13.130634 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 11:13:13.137104 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 11:13:13.140000 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 11:13:13.143721 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 11:13:13.149945 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 11:13:13.153368 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 11:13:13.156883 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8031 11:13:13.163031 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8032 11:13:13.166644 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8033 11:13:13.169677 Total UI for P1: 0, mck2ui 16
8034 11:13:13.173171 best dqsien dly found for B0: ( 1, 9, 10)
8035 11:13:13.176254 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8036 11:13:13.183144 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8037 11:13:13.186775 Total UI for P1: 0, mck2ui 16
8038 11:13:13.189857 best dqsien dly found for B1: ( 1, 9, 18)
8039 11:13:13.193567 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8040 11:13:13.196660 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8041 11:13:13.197045
8042 11:13:13.199583 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8043 11:13:13.203144 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8044 11:13:13.206580 [Gating] SW calibration Done
8045 11:13:13.206991 ==
8046 11:13:13.209456 Dram Type= 6, Freq= 0, CH_0, rank 1
8047 11:13:13.212900 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8048 11:13:13.216437 ==
8049 11:13:13.216822 RX Vref Scan: 0
8050 11:13:13.217172
8051 11:13:13.219147 RX Vref 0 -> 0, step: 1
8052 11:13:13.219629
8053 11:13:13.219949 RX Delay 0 -> 252, step: 8
8054 11:13:13.225968 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8055 11:13:13.229434 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8056 11:13:13.232791 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8057 11:13:13.236305 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8058 11:13:13.242529 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8059 11:13:13.245908 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8060 11:13:13.249078 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8061 11:13:13.251922 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8062 11:13:13.255520 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8063 11:13:13.262240 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8064 11:13:13.265341 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8065 11:13:13.268742 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8066 11:13:13.271956 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8067 11:13:13.278114 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
8068 11:13:13.281771 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8069 11:13:13.284994 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8070 11:13:13.285170 ==
8071 11:13:13.288447 Dram Type= 6, Freq= 0, CH_0, rank 1
8072 11:13:13.291381 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8073 11:13:13.291484 ==
8074 11:13:13.294549 DQS Delay:
8075 11:13:13.294740 DQS0 = 0, DQS1 = 0
8076 11:13:13.298298 DQM Delay:
8077 11:13:13.298490 DQM0 = 128, DQM1 = 121
8078 11:13:13.298595 DQ Delay:
8079 11:13:13.304385 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
8080 11:13:13.307720 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8081 11:13:13.311397 DQ8 =115, DQ9 =107, DQ10 =123, DQ11 =115
8082 11:13:13.314270 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8083 11:13:13.314444
8084 11:13:13.314582
8085 11:13:13.314712 ==
8086 11:13:13.318052 Dram Type= 6, Freq= 0, CH_0, rank 1
8087 11:13:13.321252 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8088 11:13:13.321457 ==
8089 11:13:13.321618
8090 11:13:13.321766
8091 11:13:13.324382 TX Vref Scan disable
8092 11:13:13.327701 == TX Byte 0 ==
8093 11:13:13.331083 Update DQ dly =987 (3 ,6, 27) DQ OEN =(3 ,3)
8094 11:13:13.334440 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
8095 11:13:13.338073 == TX Byte 1 ==
8096 11:13:13.341469 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8097 11:13:13.344434 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8098 11:13:13.344946 ==
8099 11:13:13.347493 Dram Type= 6, Freq= 0, CH_0, rank 1
8100 11:13:13.353933 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8101 11:13:13.354315 ==
8102 11:13:13.367238
8103 11:13:13.370031 TX Vref early break, caculate TX vref
8104 11:13:13.373728 TX Vref=16, minBit 1, minWin=22, winSum=365
8105 11:13:13.376951 TX Vref=18, minBit 1, minWin=22, winSum=371
8106 11:13:13.380420 TX Vref=20, minBit 0, minWin=23, winSum=378
8107 11:13:13.383319 TX Vref=22, minBit 9, minWin=23, winSum=390
8108 11:13:13.386970 TX Vref=24, minBit 8, minWin=24, winSum=402
8109 11:13:13.393147 TX Vref=26, minBit 8, minWin=24, winSum=405
8110 11:13:13.396799 TX Vref=28, minBit 8, minWin=24, winSum=408
8111 11:13:13.399793 TX Vref=30, minBit 8, minWin=24, winSum=403
8112 11:13:13.403460 TX Vref=32, minBit 9, minWin=23, winSum=398
8113 11:13:13.406655 TX Vref=34, minBit 8, minWin=22, winSum=389
8114 11:13:13.409992 TX Vref=36, minBit 8, minWin=22, winSum=384
8115 11:13:13.416566 [TxChooseVref] Worse bit 8, Min win 24, Win sum 408, Final Vref 28
8116 11:13:13.416676
8117 11:13:13.420108 Final TX Range 0 Vref 28
8118 11:13:13.420191
8119 11:13:13.420255 ==
8120 11:13:13.423085 Dram Type= 6, Freq= 0, CH_0, rank 1
8121 11:13:13.426762 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8122 11:13:13.426887 ==
8123 11:13:13.426955
8124 11:13:13.429731
8125 11:13:13.429812 TX Vref Scan disable
8126 11:13:13.436620 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8127 11:13:13.436702 == TX Byte 0 ==
8128 11:13:13.439888 u2DelayCellOfst[0]=15 cells (4 PI)
8129 11:13:13.443322 u2DelayCellOfst[1]=18 cells (5 PI)
8130 11:13:13.446206 u2DelayCellOfst[2]=11 cells (3 PI)
8131 11:13:13.449689 u2DelayCellOfst[3]=11 cells (3 PI)
8132 11:13:13.452785 u2DelayCellOfst[4]=7 cells (2 PI)
8133 11:13:13.456482 u2DelayCellOfst[5]=0 cells (0 PI)
8134 11:13:13.459579 u2DelayCellOfst[6]=18 cells (5 PI)
8135 11:13:13.462656 u2DelayCellOfst[7]=18 cells (5 PI)
8136 11:13:13.466214 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8137 11:13:13.469596 Update DQM dly =987 (3 ,6, 27) DQM OEN =(3 ,3)
8138 11:13:13.472550 == TX Byte 1 ==
8139 11:13:13.475973 u2DelayCellOfst[8]=0 cells (0 PI)
8140 11:13:13.479439 u2DelayCellOfst[9]=3 cells (1 PI)
8141 11:13:13.482507 u2DelayCellOfst[10]=11 cells (3 PI)
8142 11:13:13.485595 u2DelayCellOfst[11]=3 cells (1 PI)
8143 11:13:13.489058 u2DelayCellOfst[12]=15 cells (4 PI)
8144 11:13:13.492560 u2DelayCellOfst[13]=15 cells (4 PI)
8145 11:13:13.495642 u2DelayCellOfst[14]=18 cells (5 PI)
8146 11:13:13.495798 u2DelayCellOfst[15]=11 cells (3 PI)
8147 11:13:13.502587 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8148 11:13:13.505662 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8149 11:13:13.509002 DramC Write-DBI on
8150 11:13:13.509177 ==
8151 11:13:13.512585 Dram Type= 6, Freq= 0, CH_0, rank 1
8152 11:13:13.515517 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8153 11:13:13.515806 ==
8154 11:13:13.515982
8155 11:13:13.516134
8156 11:13:13.519161 TX Vref Scan disable
8157 11:13:13.519365 == TX Byte 0 ==
8158 11:13:13.525330 Update DQM dly =731 (2 ,6, 27) DQM OEN =(3 ,3)
8159 11:13:13.525535 == TX Byte 1 ==
8160 11:13:13.528770 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8161 11:13:13.532019 DramC Write-DBI off
8162 11:13:13.532310
8163 11:13:13.532565 [DATLAT]
8164 11:13:13.535798 Freq=1600, CH0 RK1
8165 11:13:13.536040
8166 11:13:13.536258 DATLAT Default: 0xf
8167 11:13:13.538426 0, 0xFFFF, sum = 0
8168 11:13:13.541902 1, 0xFFFF, sum = 0
8169 11:13:13.542139 2, 0xFFFF, sum = 0
8170 11:13:13.545269 3, 0xFFFF, sum = 0
8171 11:13:13.545474 4, 0xFFFF, sum = 0
8172 11:13:13.548356 5, 0xFFFF, sum = 0
8173 11:13:13.548572 6, 0xFFFF, sum = 0
8174 11:13:13.551774 7, 0xFFFF, sum = 0
8175 11:13:13.552041 8, 0xFFFF, sum = 0
8176 11:13:13.555266 9, 0xFFFF, sum = 0
8177 11:13:13.555472 10, 0xFFFF, sum = 0
8178 11:13:13.558730 11, 0xFFFF, sum = 0
8179 11:13:13.558959 12, 0xFFFF, sum = 0
8180 11:13:13.561940 13, 0xCFFF, sum = 0
8181 11:13:13.562144 14, 0x0, sum = 1
8182 11:13:13.564952 15, 0x0, sum = 2
8183 11:13:13.565158 16, 0x0, sum = 3
8184 11:13:13.568673 17, 0x0, sum = 4
8185 11:13:13.568879 best_step = 15
8186 11:13:13.569067
8187 11:13:13.569221 ==
8188 11:13:13.571685 Dram Type= 6, Freq= 0, CH_0, rank 1
8189 11:13:13.578593 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8190 11:13:13.578988 ==
8191 11:13:13.579381 RX Vref Scan: 0
8192 11:13:13.579715
8193 11:13:13.581887 RX Vref 0 -> 0, step: 1
8194 11:13:13.582265
8195 11:13:13.584956 RX Delay 3 -> 252, step: 4
8196 11:13:13.588101 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8197 11:13:13.591705 iDelay=191, Bit 1, Center 126 (71 ~ 182) 112
8198 11:13:13.594754 iDelay=191, Bit 2, Center 120 (67 ~ 174) 108
8199 11:13:13.601132 iDelay=191, Bit 3, Center 120 (63 ~ 178) 116
8200 11:13:13.604813 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8201 11:13:13.607912 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8202 11:13:13.610914 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8203 11:13:13.617668 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8204 11:13:13.620602 iDelay=191, Bit 8, Center 108 (51 ~ 166) 116
8205 11:13:13.624219 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8206 11:13:13.627354 iDelay=191, Bit 10, Center 118 (59 ~ 178) 120
8207 11:13:13.631214 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8208 11:13:13.637577 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8209 11:13:13.640896 iDelay=191, Bit 13, Center 124 (67 ~ 182) 116
8210 11:13:13.644280 iDelay=191, Bit 14, Center 128 (71 ~ 186) 116
8211 11:13:13.646986 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8212 11:13:13.647099 ==
8213 11:13:13.650445 Dram Type= 6, Freq= 0, CH_0, rank 1
8214 11:13:13.657168 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8215 11:13:13.657346 ==
8216 11:13:13.657448 DQS Delay:
8217 11:13:13.660721 DQS0 = 0, DQS1 = 0
8218 11:13:13.660843 DQM Delay:
8219 11:13:13.660964 DQM0 = 124, DQM1 = 117
8220 11:13:13.663438 DQ Delay:
8221 11:13:13.666969 DQ0 =124, DQ1 =126, DQ2 =120, DQ3 =120
8222 11:13:13.670622 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8223 11:13:13.673683 DQ8 =108, DQ9 =104, DQ10 =118, DQ11 =112
8224 11:13:13.676717 DQ12 =124, DQ13 =124, DQ14 =128, DQ15 =124
8225 11:13:13.676833
8226 11:13:13.676929
8227 11:13:13.676995
8228 11:13:13.680289 [DramC_TX_OE_Calibration] TA2
8229 11:13:13.683767 Original DQ_B0 (3 6) =30, OEN = 27
8230 11:13:13.687187 Original DQ_B1 (3 6) =30, OEN = 27
8231 11:13:13.690279 24, 0x0, End_B0=24 End_B1=24
8232 11:13:13.693284 25, 0x0, End_B0=25 End_B1=25
8233 11:13:13.693369 26, 0x0, End_B0=26 End_B1=26
8234 11:13:13.696905 27, 0x0, End_B0=27 End_B1=27
8235 11:13:13.699991 28, 0x0, End_B0=28 End_B1=28
8236 11:13:13.703457 29, 0x0, End_B0=29 End_B1=29
8237 11:13:13.703573 30, 0x0, End_B0=30 End_B1=30
8238 11:13:13.706483 31, 0x4141, End_B0=30 End_B1=30
8239 11:13:13.709582 Byte0 end_step=30 best_step=27
8240 11:13:13.713338 Byte1 end_step=30 best_step=27
8241 11:13:13.716294 Byte0 TX OE(2T, 0.5T) = (3, 3)
8242 11:13:13.719918 Byte1 TX OE(2T, 0.5T) = (3, 3)
8243 11:13:13.720003
8244 11:13:13.720068
8245 11:13:13.726372 [DQSOSCAuto] RK1, (LSB)MR18= 0x210f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
8246 11:13:13.729569 CH0 RK1: MR19=303, MR18=210F
8247 11:13:13.735954 CH0_RK1: MR19=0x303, MR18=0x210F, DQSOSC=393, MR23=63, INC=23, DEC=15
8248 11:13:13.739627 [RxdqsGatingPostProcess] freq 1600
8249 11:13:13.746238 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8250 11:13:13.746321 best DQS0 dly(2T, 0.5T) = (1, 1)
8251 11:13:13.749038 best DQS1 dly(2T, 0.5T) = (1, 1)
8252 11:13:13.752667 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8253 11:13:13.755954 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8254 11:13:13.759354 best DQS0 dly(2T, 0.5T) = (1, 1)
8255 11:13:13.762111 best DQS1 dly(2T, 0.5T) = (1, 1)
8256 11:13:13.765483 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8257 11:13:13.768854 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8258 11:13:13.772290 Pre-setting of DQS Precalculation
8259 11:13:13.775656 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8260 11:13:13.778876 ==
8261 11:13:13.782577 Dram Type= 6, Freq= 0, CH_1, rank 0
8262 11:13:13.785275 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8263 11:13:13.785361 ==
8264 11:13:13.788823 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8265 11:13:13.795043 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8266 11:13:13.798559 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8267 11:13:13.805320 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8268 11:13:13.813562 [CA 0] Center 41 (12~71) winsize 60
8269 11:13:13.816592 [CA 1] Center 42 (13~72) winsize 60
8270 11:13:13.820284 [CA 2] Center 37 (9~66) winsize 58
8271 11:13:13.823361 [CA 3] Center 37 (8~66) winsize 59
8272 11:13:13.826443 [CA 4] Center 37 (8~67) winsize 60
8273 11:13:13.829919 [CA 5] Center 37 (8~66) winsize 59
8274 11:13:13.830002
8275 11:13:13.833015 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8276 11:13:13.833128
8277 11:13:13.839693 [CATrainingPosCal] consider 1 rank data
8278 11:13:13.839776 u2DelayCellTimex100 = 258/100 ps
8279 11:13:13.846371 CA0 delay=41 (12~71),Diff = 4 PI (15 cell)
8280 11:13:13.849316 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8281 11:13:13.853009 CA2 delay=37 (9~66),Diff = 0 PI (0 cell)
8282 11:13:13.856477 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8283 11:13:13.859279 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8284 11:13:13.862686 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8285 11:13:13.862769
8286 11:13:13.866127 CA PerBit enable=1, Macro0, CA PI delay=37
8287 11:13:13.866210
8288 11:13:13.869455 [CBTSetCACLKResult] CA Dly = 37
8289 11:13:13.872218 CS Dly: 9 (0~40)
8290 11:13:13.875673 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8291 11:13:13.878970 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8292 11:13:13.879052 ==
8293 11:13:13.882266 Dram Type= 6, Freq= 0, CH_1, rank 1
8294 11:13:13.888896 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8295 11:13:13.888978 ==
8296 11:13:13.892311 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8297 11:13:13.899158 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8298 11:13:13.901848 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8299 11:13:13.908694 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8300 11:13:13.916225 [CA 0] Center 42 (12~72) winsize 61
8301 11:13:13.919914 [CA 1] Center 42 (12~72) winsize 61
8302 11:13:13.923012 [CA 2] Center 37 (8~67) winsize 60
8303 11:13:13.926655 [CA 3] Center 36 (7~66) winsize 60
8304 11:13:13.929733 [CA 4] Center 38 (8~68) winsize 61
8305 11:13:13.932712 [CA 5] Center 36 (6~66) winsize 61
8306 11:13:13.932796
8307 11:13:13.936344 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8308 11:13:13.936424
8309 11:13:13.943135 [CATrainingPosCal] consider 2 rank data
8310 11:13:13.943216 u2DelayCellTimex100 = 258/100 ps
8311 11:13:13.949180 CA0 delay=41 (12~71),Diff = 4 PI (15 cell)
8312 11:13:13.952801 CA1 delay=42 (13~72),Diff = 5 PI (18 cell)
8313 11:13:13.955863 CA2 delay=37 (9~66),Diff = 0 PI (0 cell)
8314 11:13:13.959166 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8315 11:13:13.962397 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8316 11:13:13.966142 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8317 11:13:13.966222
8318 11:13:13.969345 CA PerBit enable=1, Macro0, CA PI delay=37
8319 11:13:13.969451
8320 11:13:13.972380 [CBTSetCACLKResult] CA Dly = 37
8321 11:13:13.975679 CS Dly: 10 (0~43)
8322 11:13:13.979250 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8323 11:13:13.982128 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8324 11:13:13.982217
8325 11:13:13.985473 ----->DramcWriteLeveling(PI) begin...
8326 11:13:13.985554 ==
8327 11:13:13.988880 Dram Type= 6, Freq= 0, CH_1, rank 0
8328 11:13:13.995392 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8329 11:13:13.995470 ==
8330 11:13:13.998721 Write leveling (Byte 0): 24 => 24
8331 11:13:14.002278 Write leveling (Byte 1): 28 => 28
8332 11:13:14.005561 DramcWriteLeveling(PI) end<-----
8333 11:13:14.005660
8334 11:13:14.005748 ==
8335 11:13:14.009016 Dram Type= 6, Freq= 0, CH_1, rank 0
8336 11:13:14.012130 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8337 11:13:14.012201 ==
8338 11:13:14.015234 [Gating] SW mode calibration
8339 11:13:14.021795 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8340 11:13:14.028281 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8341 11:13:14.031996 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8342 11:13:14.035058 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8343 11:13:14.042050 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8344 11:13:14.045147 1 4 12 | B1->B0 | 2322 2323 | 1 0 | (0 0) (0 0)
8345 11:13:14.048268 1 4 16 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
8346 11:13:14.051909 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8347 11:13:14.057932 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8348 11:13:14.061623 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8349 11:13:14.068326 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8350 11:13:14.071468 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8351 11:13:14.074453 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8352 11:13:14.080883 1 5 12 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 0)
8353 11:13:14.084287 1 5 16 | B1->B0 | 2424 2626 | 0 1 | (0 0) (1 0)
8354 11:13:14.087649 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8355 11:13:14.094554 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8356 11:13:14.097803 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8357 11:13:14.100683 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 11:13:14.107650 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8359 11:13:14.111042 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8360 11:13:14.114074 1 6 12 | B1->B0 | 2b2b 2727 | 0 0 | (0 0) (0 0)
8361 11:13:14.120688 1 6 16 | B1->B0 | 4343 3f3f | 0 0 | (0 0) (0 0)
8362 11:13:14.123803 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8363 11:13:14.127312 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8364 11:13:14.133703 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8365 11:13:14.136848 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8366 11:13:14.140456 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8367 11:13:14.146633 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8368 11:13:14.149803 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8369 11:13:14.153561 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8370 11:13:14.159937 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8371 11:13:14.163013 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8372 11:13:14.165996 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 11:13:14.172491 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 11:13:14.176368 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 11:13:14.179284 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 11:13:14.186272 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 11:13:14.189607 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 11:13:14.193113 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 11:13:14.199269 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 11:13:14.202654 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 11:13:14.206162 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 11:13:14.212583 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 11:13:14.216045 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 11:13:14.219394 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8385 11:13:14.226076 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8386 11:13:14.229197 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8387 11:13:14.232786 Total UI for P1: 0, mck2ui 16
8388 11:13:14.235752 best dqsien dly found for B1: ( 1, 9, 14)
8389 11:13:14.238720 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8390 11:13:14.242414 Total UI for P1: 0, mck2ui 16
8391 11:13:14.245435 best dqsien dly found for B0: ( 1, 9, 16)
8392 11:13:14.249076 best DQS0 dly(MCK, UI, PI) = (1, 9, 16)
8393 11:13:14.252188 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8394 11:13:14.252273
8395 11:13:14.258433 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 16)
8396 11:13:14.262092 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8397 11:13:14.265010 [Gating] SW calibration Done
8398 11:13:14.265095 ==
8399 11:13:14.268722 Dram Type= 6, Freq= 0, CH_1, rank 0
8400 11:13:14.271812 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8401 11:13:14.271901 ==
8402 11:13:14.271964 RX Vref Scan: 0
8403 11:13:14.275269
8404 11:13:14.275367 RX Vref 0 -> 0, step: 1
8405 11:13:14.275465
8406 11:13:14.278319 RX Delay 0 -> 252, step: 8
8407 11:13:14.281403 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8408 11:13:14.285082 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8409 11:13:14.291521 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8410 11:13:14.295040 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8411 11:13:14.298392 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8412 11:13:14.301242 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8413 11:13:14.304802 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8414 11:13:14.311533 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8415 11:13:14.314504 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
8416 11:13:14.317794 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8417 11:13:14.321239 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8418 11:13:14.324593 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8419 11:13:14.330837 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8420 11:13:14.334653 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8421 11:13:14.337674 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8422 11:13:14.341242 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8423 11:13:14.341348 ==
8424 11:13:14.344292 Dram Type= 6, Freq= 0, CH_1, rank 0
8425 11:13:14.350840 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8426 11:13:14.350956 ==
8427 11:13:14.351022 DQS Delay:
8428 11:13:14.354485 DQS0 = 0, DQS1 = 0
8429 11:13:14.354574 DQM Delay:
8430 11:13:14.357576 DQM0 = 132, DQM1 = 125
8431 11:13:14.357650 DQ Delay:
8432 11:13:14.360743 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8433 11:13:14.364391 DQ4 =127, DQ5 =143, DQ6 =143, DQ7 =131
8434 11:13:14.367502 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8435 11:13:14.370923 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
8436 11:13:14.371011
8437 11:13:14.371088
8438 11:13:14.371149 ==
8439 11:13:14.374218 Dram Type= 6, Freq= 0, CH_1, rank 0
8440 11:13:14.380585 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8441 11:13:14.380681 ==
8442 11:13:14.380746
8443 11:13:14.380805
8444 11:13:14.380888 TX Vref Scan disable
8445 11:13:14.384371 == TX Byte 0 ==
8446 11:13:14.387426 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8447 11:13:14.394136 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8448 11:13:14.394213 == TX Byte 1 ==
8449 11:13:14.397536 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8450 11:13:14.403939 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8451 11:13:14.404016 ==
8452 11:13:14.407279 Dram Type= 6, Freq= 0, CH_1, rank 0
8453 11:13:14.410173 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8454 11:13:14.410275 ==
8455 11:13:14.423059
8456 11:13:14.426491 TX Vref early break, caculate TX vref
8457 11:13:14.429922 TX Vref=16, minBit 13, minWin=21, winSum=360
8458 11:13:14.433345 TX Vref=18, minBit 10, minWin=21, winSum=373
8459 11:13:14.436244 TX Vref=20, minBit 11, minWin=22, winSum=378
8460 11:13:14.439917 TX Vref=22, minBit 5, minWin=23, winSum=391
8461 11:13:14.446453 TX Vref=24, minBit 1, minWin=24, winSum=402
8462 11:13:14.449353 TX Vref=26, minBit 5, minWin=24, winSum=411
8463 11:13:14.452883 TX Vref=28, minBit 6, minWin=25, winSum=419
8464 11:13:14.456002 TX Vref=30, minBit 6, minWin=24, winSum=414
8465 11:13:14.459786 TX Vref=32, minBit 0, minWin=23, winSum=399
8466 11:13:14.462942 TX Vref=34, minBit 0, minWin=23, winSum=391
8467 11:13:14.469070 [TxChooseVref] Worse bit 6, Min win 25, Win sum 419, Final Vref 28
8468 11:13:14.469153
8469 11:13:14.472498 Final TX Range 0 Vref 28
8470 11:13:14.472573
8471 11:13:14.472635 ==
8472 11:13:14.475702 Dram Type= 6, Freq= 0, CH_1, rank 0
8473 11:13:14.479340 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8474 11:13:14.479422 ==
8475 11:13:14.479491
8476 11:13:14.482730
8477 11:13:14.482833 TX Vref Scan disable
8478 11:13:14.488808 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8479 11:13:14.488890 == TX Byte 0 ==
8480 11:13:14.492548 u2DelayCellOfst[0]=22 cells (6 PI)
8481 11:13:14.495836 u2DelayCellOfst[1]=15 cells (4 PI)
8482 11:13:14.499206 u2DelayCellOfst[2]=0 cells (0 PI)
8483 11:13:14.502210 u2DelayCellOfst[3]=7 cells (2 PI)
8484 11:13:14.505587 u2DelayCellOfst[4]=11 cells (3 PI)
8485 11:13:14.509066 u2DelayCellOfst[5]=22 cells (6 PI)
8486 11:13:14.512361 u2DelayCellOfst[6]=22 cells (6 PI)
8487 11:13:14.515307 u2DelayCellOfst[7]=7 cells (2 PI)
8488 11:13:14.518655 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8489 11:13:14.522135 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8490 11:13:14.525746 == TX Byte 1 ==
8491 11:13:14.528558 u2DelayCellOfst[8]=0 cells (0 PI)
8492 11:13:14.532090 u2DelayCellOfst[9]=3 cells (1 PI)
8493 11:13:14.535400 u2DelayCellOfst[10]=11 cells (3 PI)
8494 11:13:14.535502 u2DelayCellOfst[11]=7 cells (2 PI)
8495 11:13:14.538716 u2DelayCellOfst[12]=15 cells (4 PI)
8496 11:13:14.542044 u2DelayCellOfst[13]=18 cells (5 PI)
8497 11:13:14.545164 u2DelayCellOfst[14]=18 cells (5 PI)
8498 11:13:14.548337 u2DelayCellOfst[15]=18 cells (5 PI)
8499 11:13:14.555364 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8500 11:13:14.558768 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8501 11:13:14.558897 DramC Write-DBI on
8502 11:13:14.561822 ==
8503 11:13:14.564915 Dram Type= 6, Freq= 0, CH_1, rank 0
8504 11:13:14.568640 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8505 11:13:14.568723 ==
8506 11:13:14.568788
8507 11:13:14.568848
8508 11:13:14.571718 TX Vref Scan disable
8509 11:13:14.571843 == TX Byte 0 ==
8510 11:13:14.578291 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8511 11:13:14.578374 == TX Byte 1 ==
8512 11:13:14.581335 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8513 11:13:14.584870 DramC Write-DBI off
8514 11:13:14.584952
8515 11:13:14.585016 [DATLAT]
8516 11:13:14.588093 Freq=1600, CH1 RK0
8517 11:13:14.588176
8518 11:13:14.588241 DATLAT Default: 0xf
8519 11:13:14.591145 0, 0xFFFF, sum = 0
8520 11:13:14.591229 1, 0xFFFF, sum = 0
8521 11:13:14.594812 2, 0xFFFF, sum = 0
8522 11:13:14.594907 3, 0xFFFF, sum = 0
8523 11:13:14.598069 4, 0xFFFF, sum = 0
8524 11:13:14.598158 5, 0xFFFF, sum = 0
8525 11:13:14.601069 6, 0xFFFF, sum = 0
8526 11:13:14.604791 7, 0xFFFF, sum = 0
8527 11:13:14.604874 8, 0xFFFF, sum = 0
8528 11:13:14.607600 9, 0xFFFF, sum = 0
8529 11:13:14.607683 10, 0xFFFF, sum = 0
8530 11:13:14.610999 11, 0xFFFF, sum = 0
8531 11:13:14.611083 12, 0xFFFF, sum = 0
8532 11:13:14.614445 13, 0x8FFF, sum = 0
8533 11:13:14.614528 14, 0x0, sum = 1
8534 11:13:14.617920 15, 0x0, sum = 2
8535 11:13:14.618003 16, 0x0, sum = 3
8536 11:13:14.621009 17, 0x0, sum = 4
8537 11:13:14.621093 best_step = 15
8538 11:13:14.621158
8539 11:13:14.621218 ==
8540 11:13:14.624321 Dram Type= 6, Freq= 0, CH_1, rank 0
8541 11:13:14.627782 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8542 11:13:14.631192 ==
8543 11:13:14.631274 RX Vref Scan: 1
8544 11:13:14.631340
8545 11:13:14.634261 Set Vref Range= 24 -> 127
8546 11:13:14.634344
8547 11:13:14.637393 RX Vref 24 -> 127, step: 1
8548 11:13:14.637475
8549 11:13:14.637545 RX Delay 11 -> 252, step: 4
8550 11:13:14.637607
8551 11:13:14.640965 Set Vref, RX VrefLevel [Byte0]: 24
8552 11:13:14.644363 [Byte1]: 24
8553 11:13:14.647921
8554 11:13:14.648005 Set Vref, RX VrefLevel [Byte0]: 25
8555 11:13:14.651634 [Byte1]: 25
8556 11:13:14.655344
8557 11:13:14.655437 Set Vref, RX VrefLevel [Byte0]: 26
8558 11:13:14.661902 [Byte1]: 26
8559 11:13:14.661990
8560 11:13:14.665390 Set Vref, RX VrefLevel [Byte0]: 27
8561 11:13:14.668885 [Byte1]: 27
8562 11:13:14.668982
8563 11:13:14.671846 Set Vref, RX VrefLevel [Byte0]: 28
8564 11:13:14.675429 [Byte1]: 28
8565 11:13:14.678493
8566 11:13:14.678625 Set Vref, RX VrefLevel [Byte0]: 29
8567 11:13:14.682083 [Byte1]: 29
8568 11:13:14.685939
8569 11:13:14.686069 Set Vref, RX VrefLevel [Byte0]: 30
8570 11:13:14.689278 [Byte1]: 30
8571 11:13:14.693663
8572 11:13:14.693784 Set Vref, RX VrefLevel [Byte0]: 31
8573 11:13:14.696701 [Byte1]: 31
8574 11:13:14.701109
8575 11:13:14.701231 Set Vref, RX VrefLevel [Byte0]: 32
8576 11:13:14.704760 [Byte1]: 32
8577 11:13:14.708932
8578 11:13:14.709053 Set Vref, RX VrefLevel [Byte0]: 33
8579 11:13:14.712565 [Byte1]: 33
8580 11:13:14.716564
8581 11:13:14.716724 Set Vref, RX VrefLevel [Byte0]: 34
8582 11:13:14.720475 [Byte1]: 34
8583 11:13:14.724351
8584 11:13:14.724772 Set Vref, RX VrefLevel [Byte0]: 35
8585 11:13:14.727933 [Byte1]: 35
8586 11:13:14.732069
8587 11:13:14.732151 Set Vref, RX VrefLevel [Byte0]: 36
8588 11:13:14.735211 [Byte1]: 36
8589 11:13:14.739466
8590 11:13:14.739553 Set Vref, RX VrefLevel [Byte0]: 37
8591 11:13:14.742715 [Byte1]: 37
8592 11:13:14.746966
8593 11:13:14.747050 Set Vref, RX VrefLevel [Byte0]: 38
8594 11:13:14.750455 [Byte1]: 38
8595 11:13:14.754333
8596 11:13:14.754415 Set Vref, RX VrefLevel [Byte0]: 39
8597 11:13:14.758002 [Byte1]: 39
8598 11:13:14.762403
8599 11:13:14.762498 Set Vref, RX VrefLevel [Byte0]: 40
8600 11:13:14.765411 [Byte1]: 40
8601 11:13:14.769578
8602 11:13:14.769700 Set Vref, RX VrefLevel [Byte0]: 41
8603 11:13:14.773309 [Byte1]: 41
8604 11:13:14.777874
8605 11:13:14.778078 Set Vref, RX VrefLevel [Byte0]: 42
8606 11:13:14.780801 [Byte1]: 42
8607 11:13:14.785032
8608 11:13:14.785251 Set Vref, RX VrefLevel [Byte0]: 43
8609 11:13:14.788539 [Byte1]: 43
8610 11:13:14.792832
8611 11:13:14.792973 Set Vref, RX VrefLevel [Byte0]: 44
8612 11:13:14.796064 [Byte1]: 44
8613 11:13:14.800311
8614 11:13:14.800409 Set Vref, RX VrefLevel [Byte0]: 45
8615 11:13:14.803498 [Byte1]: 45
8616 11:13:14.807772
8617 11:13:14.807870 Set Vref, RX VrefLevel [Byte0]: 46
8618 11:13:14.810920 [Byte1]: 46
8619 11:13:14.815244
8620 11:13:14.815345 Set Vref, RX VrefLevel [Byte0]: 47
8621 11:13:14.818818 [Byte1]: 47
8622 11:13:14.822838
8623 11:13:14.822953 Set Vref, RX VrefLevel [Byte0]: 48
8624 11:13:14.826374 [Byte1]: 48
8625 11:13:14.830483
8626 11:13:14.830591 Set Vref, RX VrefLevel [Byte0]: 49
8627 11:13:14.833949 [Byte1]: 49
8628 11:13:14.838545
8629 11:13:14.838654 Set Vref, RX VrefLevel [Byte0]: 50
8630 11:13:14.841531 [Byte1]: 50
8631 11:13:14.845732
8632 11:13:14.845847 Set Vref, RX VrefLevel [Byte0]: 51
8633 11:13:14.849046 [Byte1]: 51
8634 11:13:14.853580
8635 11:13:14.853692 Set Vref, RX VrefLevel [Byte0]: 52
8636 11:13:14.856532 [Byte1]: 52
8637 11:13:14.861243
8638 11:13:14.861353 Set Vref, RX VrefLevel [Byte0]: 53
8639 11:13:14.864709 [Byte1]: 53
8640 11:13:14.869061
8641 11:13:14.869175 Set Vref, RX VrefLevel [Byte0]: 54
8642 11:13:14.872034 [Byte1]: 54
8643 11:13:14.876244
8644 11:13:14.876341 Set Vref, RX VrefLevel [Byte0]: 55
8645 11:13:14.879808 [Byte1]: 55
8646 11:13:14.883870
8647 11:13:14.883974 Set Vref, RX VrefLevel [Byte0]: 56
8648 11:13:14.886988 [Byte1]: 56
8649 11:13:14.891779
8650 11:13:14.891879 Set Vref, RX VrefLevel [Byte0]: 57
8651 11:13:14.894931 [Byte1]: 57
8652 11:13:14.899089
8653 11:13:14.899190 Set Vref, RX VrefLevel [Byte0]: 58
8654 11:13:14.902777 [Byte1]: 58
8655 11:13:14.906635
8656 11:13:14.906734 Set Vref, RX VrefLevel [Byte0]: 59
8657 11:13:14.910296 [Byte1]: 59
8658 11:13:14.914604
8659 11:13:14.914706 Set Vref, RX VrefLevel [Byte0]: 60
8660 11:13:14.917732 [Byte1]: 60
8661 11:13:14.921989
8662 11:13:14.922095 Set Vref, RX VrefLevel [Byte0]: 61
8663 11:13:14.925005 [Byte1]: 61
8664 11:13:14.929510
8665 11:13:14.929609 Set Vref, RX VrefLevel [Byte0]: 62
8666 11:13:14.932895 [Byte1]: 62
8667 11:13:14.937465
8668 11:13:14.937569 Set Vref, RX VrefLevel [Byte0]: 63
8669 11:13:14.940227 [Byte1]: 63
8670 11:13:14.945115
8671 11:13:14.945195 Set Vref, RX VrefLevel [Byte0]: 64
8672 11:13:14.948041 [Byte1]: 64
8673 11:13:14.952495
8674 11:13:14.952581 Set Vref, RX VrefLevel [Byte0]: 65
8675 11:13:14.958852 [Byte1]: 65
8676 11:13:14.958952
8677 11:13:14.962303 Set Vref, RX VrefLevel [Byte0]: 66
8678 11:13:14.965576 [Byte1]: 66
8679 11:13:14.965662
8680 11:13:14.968948 Set Vref, RX VrefLevel [Byte0]: 67
8681 11:13:14.972035 [Byte1]: 67
8682 11:13:14.975112
8683 11:13:14.975225 Set Vref, RX VrefLevel [Byte0]: 68
8684 11:13:14.978649 [Byte1]: 68
8685 11:13:14.982790
8686 11:13:14.982936 Set Vref, RX VrefLevel [Byte0]: 69
8687 11:13:14.986399 [Byte1]: 69
8688 11:13:14.990550
8689 11:13:14.990634 Set Vref, RX VrefLevel [Byte0]: 70
8690 11:13:14.993542 [Byte1]: 70
8691 11:13:14.997920
8692 11:13:14.998005 Final RX Vref Byte 0 = 59 to rank0
8693 11:13:15.001757 Final RX Vref Byte 1 = 56 to rank0
8694 11:13:15.004449 Final RX Vref Byte 0 = 59 to rank1
8695 11:13:15.007968 Final RX Vref Byte 1 = 56 to rank1==
8696 11:13:15.011008 Dram Type= 6, Freq= 0, CH_1, rank 0
8697 11:13:15.017637 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8698 11:13:15.017767 ==
8699 11:13:15.017879 DQS Delay:
8700 11:13:15.021450 DQS0 = 0, DQS1 = 0
8701 11:13:15.021535 DQM Delay:
8702 11:13:15.021601 DQM0 = 130, DQM1 = 124
8703 11:13:15.024449 DQ Delay:
8704 11:13:15.027760 DQ0 =136, DQ1 =126, DQ2 =120, DQ3 =126
8705 11:13:15.031311 DQ4 =128, DQ5 =142, DQ6 =142, DQ7 =126
8706 11:13:15.034264 DQ8 =110, DQ9 =114, DQ10 =122, DQ11 =116
8707 11:13:15.037436 DQ12 =134, DQ13 =132, DQ14 =132, DQ15 =132
8708 11:13:15.037519
8709 11:13:15.037584
8710 11:13:15.037645
8711 11:13:15.040920 [DramC_TX_OE_Calibration] TA2
8712 11:13:15.044151 Original DQ_B0 (3 6) =30, OEN = 27
8713 11:13:15.047580 Original DQ_B1 (3 6) =30, OEN = 27
8714 11:13:15.050993 24, 0x0, End_B0=24 End_B1=24
8715 11:13:15.053867 25, 0x0, End_B0=25 End_B1=25
8716 11:13:15.053951 26, 0x0, End_B0=26 End_B1=26
8717 11:13:15.057262 27, 0x0, End_B0=27 End_B1=27
8718 11:13:15.060722 28, 0x0, End_B0=28 End_B1=28
8719 11:13:15.063982 29, 0x0, End_B0=29 End_B1=29
8720 11:13:15.064067 30, 0x0, End_B0=30 End_B1=30
8721 11:13:15.067407 31, 0x5151, End_B0=30 End_B1=30
8722 11:13:15.070417 Byte0 end_step=30 best_step=27
8723 11:13:15.073731 Byte1 end_step=30 best_step=27
8724 11:13:15.077143 Byte0 TX OE(2T, 0.5T) = (3, 3)
8725 11:13:15.080232 Byte1 TX OE(2T, 0.5T) = (3, 3)
8726 11:13:15.080317
8727 11:13:15.080402
8728 11:13:15.086907 [DQSOSCAuto] RK0, (LSB)MR18= 0x80d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 405 ps
8729 11:13:15.090523 CH1 RK0: MR19=303, MR18=80D
8730 11:13:15.096917 CH1_RK0: MR19=0x303, MR18=0x80D, DQSOSC=403, MR23=63, INC=22, DEC=15
8731 11:13:15.097008
8732 11:13:15.099914 ----->DramcWriteLeveling(PI) begin...
8733 11:13:15.099999 ==
8734 11:13:15.103710 Dram Type= 6, Freq= 0, CH_1, rank 1
8735 11:13:15.106457 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8736 11:13:15.106544 ==
8737 11:13:15.110274 Write leveling (Byte 0): 26 => 26
8738 11:13:15.113431 Write leveling (Byte 1): 26 => 26
8739 11:13:15.116498 DramcWriteLeveling(PI) end<-----
8740 11:13:15.116584
8741 11:13:15.116668 ==
8742 11:13:15.120104 Dram Type= 6, Freq= 0, CH_1, rank 1
8743 11:13:15.123143 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8744 11:13:15.126265 ==
8745 11:13:15.126350 [Gating] SW mode calibration
8746 11:13:15.136810 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8747 11:13:15.139672 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8748 11:13:15.142798 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8749 11:13:15.149891 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8750 11:13:15.152895 1 4 8 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
8751 11:13:15.156142 1 4 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
8752 11:13:15.162822 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8753 11:13:15.166395 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8754 11:13:15.169488 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8755 11:13:15.176624 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8756 11:13:15.179311 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8757 11:13:15.182904 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8758 11:13:15.189343 1 5 8 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
8759 11:13:15.192393 1 5 12 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
8760 11:13:15.196096 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8761 11:13:15.202325 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8762 11:13:15.205734 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8763 11:13:15.208755 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8764 11:13:15.215365 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8765 11:13:15.218708 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8766 11:13:15.222197 1 6 8 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
8767 11:13:15.229012 1 6 12 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
8768 11:13:15.232138 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8769 11:13:15.235343 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8770 11:13:15.241895 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8771 11:13:15.245478 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8772 11:13:15.248503 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8773 11:13:15.255208 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8774 11:13:15.258713 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8775 11:13:15.261969 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8776 11:13:15.268877 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8777 11:13:15.271544 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8778 11:13:15.275031 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8779 11:13:15.282057 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8780 11:13:15.285548 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8781 11:13:15.288435 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 11:13:15.294953 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 11:13:15.298545 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 11:13:15.301680 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 11:13:15.308266 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 11:13:15.311618 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 11:13:15.314899 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 11:13:15.321591 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 11:13:15.324728 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 11:13:15.327820 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8791 11:13:15.334504 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8792 11:13:15.337625 Total UI for P1: 0, mck2ui 16
8793 11:13:15.340806 best dqsien dly found for B0: ( 1, 9, 8)
8794 11:13:15.344525 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8795 11:13:15.347330 Total UI for P1: 0, mck2ui 16
8796 11:13:15.350897 best dqsien dly found for B1: ( 1, 9, 12)
8797 11:13:15.353872 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8798 11:13:15.357726 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8799 11:13:15.358154
8800 11:13:15.361014 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8801 11:13:15.367409 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8802 11:13:15.367917 [Gating] SW calibration Done
8803 11:13:15.368401 ==
8804 11:13:15.370470 Dram Type= 6, Freq= 0, CH_1, rank 1
8805 11:13:15.377236 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8806 11:13:15.377672 ==
8807 11:13:15.378011 RX Vref Scan: 0
8808 11:13:15.378330
8809 11:13:15.380903 RX Vref 0 -> 0, step: 1
8810 11:13:15.381331
8811 11:13:15.384041 RX Delay 0 -> 252, step: 8
8812 11:13:15.386894 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8813 11:13:15.390523 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8814 11:13:15.393829 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8815 11:13:15.400551 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8816 11:13:15.403881 iDelay=200, Bit 4, Center 123 (64 ~ 183) 120
8817 11:13:15.406994 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8818 11:13:15.409952 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8819 11:13:15.413776 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8820 11:13:15.420438 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8821 11:13:15.423758 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8822 11:13:15.426276 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8823 11:13:15.430183 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8824 11:13:15.433340 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8825 11:13:15.439484 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8826 11:13:15.443276 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8827 11:13:15.446185 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8828 11:13:15.446750 ==
8829 11:13:15.449841 Dram Type= 6, Freq= 0, CH_1, rank 1
8830 11:13:15.452731 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8831 11:13:15.456080 ==
8832 11:13:15.456498 DQS Delay:
8833 11:13:15.457008 DQS0 = 0, DQS1 = 0
8834 11:13:15.459845 DQM Delay:
8835 11:13:15.460342 DQM0 = 132, DQM1 = 128
8836 11:13:15.462797 DQ Delay:
8837 11:13:15.465892 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8838 11:13:15.469753 DQ4 =123, DQ5 =143, DQ6 =143, DQ7 =131
8839 11:13:15.472597 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8840 11:13:15.475971 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =139
8841 11:13:15.476470
8842 11:13:15.476862
8843 11:13:15.477177 ==
8844 11:13:15.479513 Dram Type= 6, Freq= 0, CH_1, rank 1
8845 11:13:15.482479 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8846 11:13:15.485880 ==
8847 11:13:15.486373
8848 11:13:15.486752
8849 11:13:15.487240 TX Vref Scan disable
8850 11:13:15.489331 == TX Byte 0 ==
8851 11:13:15.492692 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8852 11:13:15.496045 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8853 11:13:15.498878 == TX Byte 1 ==
8854 11:13:15.502243 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8855 11:13:15.505465 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8856 11:13:15.508918 ==
8857 11:13:15.512472 Dram Type= 6, Freq= 0, CH_1, rank 1
8858 11:13:15.515555 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8859 11:13:15.515997 ==
8860 11:13:15.528915
8861 11:13:15.532001 TX Vref early break, caculate TX vref
8862 11:13:15.535083 TX Vref=16, minBit 0, minWin=23, winSum=383
8863 11:13:15.538250 TX Vref=18, minBit 0, minWin=22, winSum=391
8864 11:13:15.541861 TX Vref=20, minBit 0, minWin=23, winSum=404
8865 11:13:15.544961 TX Vref=22, minBit 0, minWin=23, winSum=408
8866 11:13:15.548074 TX Vref=24, minBit 0, minWin=25, winSum=423
8867 11:13:15.554729 TX Vref=26, minBit 0, minWin=25, winSum=427
8868 11:13:15.558202 TX Vref=28, minBit 0, minWin=25, winSum=424
8869 11:13:15.561727 TX Vref=30, minBit 0, minWin=24, winSum=420
8870 11:13:15.564777 TX Vref=32, minBit 1, minWin=24, winSum=412
8871 11:13:15.568029 TX Vref=34, minBit 1, minWin=24, winSum=408
8872 11:13:15.574727 TX Vref=36, minBit 0, minWin=24, winSum=399
8873 11:13:15.578027 [TxChooseVref] Worse bit 0, Min win 25, Win sum 427, Final Vref 26
8874 11:13:15.578662
8875 11:13:15.581689 Final TX Range 0 Vref 26
8876 11:13:15.582111
8877 11:13:15.582440 ==
8878 11:13:15.585084 Dram Type= 6, Freq= 0, CH_1, rank 1
8879 11:13:15.587734 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8880 11:13:15.591209 ==
8881 11:13:15.591813
8882 11:13:15.592425
8883 11:13:15.592953 TX Vref Scan disable
8884 11:13:15.598019 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8885 11:13:15.598446 == TX Byte 0 ==
8886 11:13:15.601347 u2DelayCellOfst[0]=18 cells (5 PI)
8887 11:13:15.604804 u2DelayCellOfst[1]=15 cells (4 PI)
8888 11:13:15.607750 u2DelayCellOfst[2]=0 cells (0 PI)
8889 11:13:15.611118 u2DelayCellOfst[3]=7 cells (2 PI)
8890 11:13:15.614267 u2DelayCellOfst[4]=11 cells (3 PI)
8891 11:13:15.617662 u2DelayCellOfst[5]=22 cells (6 PI)
8892 11:13:15.621007 u2DelayCellOfst[6]=18 cells (5 PI)
8893 11:13:15.624509 u2DelayCellOfst[7]=7 cells (2 PI)
8894 11:13:15.627481 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8895 11:13:15.630599 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8896 11:13:15.634259 == TX Byte 1 ==
8897 11:13:15.637380 u2DelayCellOfst[8]=0 cells (0 PI)
8898 11:13:15.640525 u2DelayCellOfst[9]=7 cells (2 PI)
8899 11:13:15.644271 u2DelayCellOfst[10]=15 cells (4 PI)
8900 11:13:15.647243 u2DelayCellOfst[11]=7 cells (2 PI)
8901 11:13:15.650279 u2DelayCellOfst[12]=15 cells (4 PI)
8902 11:13:15.653929 u2DelayCellOfst[13]=18 cells (5 PI)
8903 11:13:15.657215 u2DelayCellOfst[14]=18 cells (5 PI)
8904 11:13:15.661038 u2DelayCellOfst[15]=18 cells (5 PI)
8905 11:13:15.663468 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8906 11:13:15.667120 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8907 11:13:15.670220 DramC Write-DBI on
8908 11:13:15.670638 ==
8909 11:13:15.673872 Dram Type= 6, Freq= 0, CH_1, rank 1
8910 11:13:15.676835 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8911 11:13:15.677260 ==
8912 11:13:15.677720
8913 11:13:15.678036
8914 11:13:15.680544 TX Vref Scan disable
8915 11:13:15.681113 == TX Byte 0 ==
8916 11:13:15.687167 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8917 11:13:15.687643 == TX Byte 1 ==
8918 11:13:15.690254 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8919 11:13:15.693298 DramC Write-DBI off
8920 11:13:15.693786
8921 11:13:15.694142 [DATLAT]
8922 11:13:15.697079 Freq=1600, CH1 RK1
8923 11:13:15.697563
8924 11:13:15.697962 DATLAT Default: 0xf
8925 11:13:15.700331 0, 0xFFFF, sum = 0
8926 11:13:15.703594 1, 0xFFFF, sum = 0
8927 11:13:15.704051 2, 0xFFFF, sum = 0
8928 11:13:15.706427 3, 0xFFFF, sum = 0
8929 11:13:15.707142 4, 0xFFFF, sum = 0
8930 11:13:15.709876 5, 0xFFFF, sum = 0
8931 11:13:15.710555 6, 0xFFFF, sum = 0
8932 11:13:15.713181 7, 0xFFFF, sum = 0
8933 11:13:15.713670 8, 0xFFFF, sum = 0
8934 11:13:15.716606 9, 0xFFFF, sum = 0
8935 11:13:15.717100 10, 0xFFFF, sum = 0
8936 11:13:15.719884 11, 0xFFFF, sum = 0
8937 11:13:15.720529 12, 0xFFFF, sum = 0
8938 11:13:15.723078 13, 0x8FFF, sum = 0
8939 11:13:15.723656 14, 0x0, sum = 1
8940 11:13:15.726242 15, 0x0, sum = 2
8941 11:13:15.726709 16, 0x0, sum = 3
8942 11:13:15.729707 17, 0x0, sum = 4
8943 11:13:15.730131 best_step = 15
8944 11:13:15.730510
8945 11:13:15.730824 ==
8946 11:13:15.733032 Dram Type= 6, Freq= 0, CH_1, rank 1
8947 11:13:15.739594 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8948 11:13:15.740066 ==
8949 11:13:15.740438 RX Vref Scan: 0
8950 11:13:15.740755
8951 11:13:15.743118 RX Vref 0 -> 0, step: 1
8952 11:13:15.743589
8953 11:13:15.745767 RX Delay 11 -> 252, step: 4
8954 11:13:15.749423 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8955 11:13:15.752336 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
8956 11:13:15.759217 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8957 11:13:15.762253 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8958 11:13:15.765823 iDelay=195, Bit 4, Center 124 (71 ~ 178) 108
8959 11:13:15.768820 iDelay=195, Bit 5, Center 140 (87 ~ 194) 108
8960 11:13:15.772472 iDelay=195, Bit 6, Center 142 (91 ~ 194) 104
8961 11:13:15.779215 iDelay=195, Bit 7, Center 128 (75 ~ 182) 108
8962 11:13:15.782208 iDelay=195, Bit 8, Center 110 (55 ~ 166) 112
8963 11:13:15.785756 iDelay=195, Bit 9, Center 114 (63 ~ 166) 104
8964 11:13:15.788672 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8965 11:13:15.792514 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8966 11:13:15.798655 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8967 11:13:15.801707 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
8968 11:13:15.805359 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
8969 11:13:15.808760 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
8970 11:13:15.809183 ==
8971 11:13:15.812270 Dram Type= 6, Freq= 0, CH_1, rank 1
8972 11:13:15.818284 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8973 11:13:15.818712 ==
8974 11:13:15.819209 DQS Delay:
8975 11:13:15.821586 DQS0 = 0, DQS1 = 0
8976 11:13:15.822191 DQM Delay:
8977 11:13:15.824591 DQM0 = 129, DQM1 = 125
8978 11:13:15.825073 DQ Delay:
8979 11:13:15.828162 DQ0 =134, DQ1 =126, DQ2 =116, DQ3 =128
8980 11:13:15.831500 DQ4 =124, DQ5 =140, DQ6 =142, DQ7 =128
8981 11:13:15.834875 DQ8 =110, DQ9 =114, DQ10 =128, DQ11 =120
8982 11:13:15.838326 DQ12 =132, DQ13 =134, DQ14 =130, DQ15 =136
8983 11:13:15.838757
8984 11:13:15.839209
8985 11:13:15.839539
8986 11:13:15.841135 [DramC_TX_OE_Calibration] TA2
8987 11:13:15.844532 Original DQ_B0 (3 6) =30, OEN = 27
8988 11:13:15.847611 Original DQ_B1 (3 6) =30, OEN = 27
8989 11:13:15.850997 24, 0x0, End_B0=24 End_B1=24
8990 11:13:15.854494 25, 0x0, End_B0=25 End_B1=25
8991 11:13:15.855023 26, 0x0, End_B0=26 End_B1=26
8992 11:13:15.857420 27, 0x0, End_B0=27 End_B1=27
8993 11:13:15.861260 28, 0x0, End_B0=28 End_B1=28
8994 11:13:15.864272 29, 0x0, End_B0=29 End_B1=29
8995 11:13:15.867344 30, 0x0, End_B0=30 End_B1=30
8996 11:13:15.867775 31, 0x5151, End_B0=30 End_B1=30
8997 11:13:15.871099 Byte0 end_step=30 best_step=27
8998 11:13:15.873908 Byte1 end_step=30 best_step=27
8999 11:13:15.877113 Byte0 TX OE(2T, 0.5T) = (3, 3)
9000 11:13:15.880690 Byte1 TX OE(2T, 0.5T) = (3, 3)
9001 11:13:15.881112
9002 11:13:15.881439
9003 11:13:15.887445 [DQSOSCAuto] RK1, (LSB)MR18= 0x101c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
9004 11:13:15.890646 CH1 RK1: MR19=303, MR18=101C
9005 11:13:15.897068 CH1_RK1: MR19=0x303, MR18=0x101C, DQSOSC=395, MR23=63, INC=23, DEC=15
9006 11:13:15.900832 [RxdqsGatingPostProcess] freq 1600
9007 11:13:15.907049 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9008 11:13:15.910042 best DQS0 dly(2T, 0.5T) = (1, 1)
9009 11:13:15.913331 best DQS1 dly(2T, 0.5T) = (1, 1)
9010 11:13:15.913776 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9011 11:13:15.917006 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9012 11:13:15.920122 best DQS0 dly(2T, 0.5T) = (1, 1)
9013 11:13:15.923320 best DQS1 dly(2T, 0.5T) = (1, 1)
9014 11:13:15.926644 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9015 11:13:15.930041 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9016 11:13:15.933149 Pre-setting of DQS Precalculation
9017 11:13:15.940204 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9018 11:13:15.946237 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9019 11:13:15.953134 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9020 11:13:15.953593
9021 11:13:15.953939
9022 11:13:15.956646 [Calibration Summary] 3200 Mbps
9023 11:13:15.957092 CH 0, Rank 0
9024 11:13:15.959870 SW Impedance : PASS
9025 11:13:15.963382 DUTY Scan : NO K
9026 11:13:15.963823 ZQ Calibration : PASS
9027 11:13:15.966404 Jitter Meter : NO K
9028 11:13:15.970012 CBT Training : PASS
9029 11:13:15.970435 Write leveling : PASS
9030 11:13:15.973114 RX DQS gating : PASS
9031 11:13:15.973536 RX DQ/DQS(RDDQC) : PASS
9032 11:13:15.976157 TX DQ/DQS : PASS
9033 11:13:15.979651 RX DATLAT : PASS
9034 11:13:15.980072 RX DQ/DQS(Engine): PASS
9035 11:13:15.982776 TX OE : PASS
9036 11:13:15.983230 All Pass.
9037 11:13:15.983562
9038 11:13:15.986369 CH 0, Rank 1
9039 11:13:15.986790 SW Impedance : PASS
9040 11:13:15.989525 DUTY Scan : NO K
9041 11:13:15.993211 ZQ Calibration : PASS
9042 11:13:15.993632 Jitter Meter : NO K
9043 11:13:15.996245 CBT Training : PASS
9044 11:13:15.999704 Write leveling : PASS
9045 11:13:16.000126 RX DQS gating : PASS
9046 11:13:16.002803 RX DQ/DQS(RDDQC) : PASS
9047 11:13:16.005819 TX DQ/DQS : PASS
9048 11:13:16.006120 RX DATLAT : PASS
9049 11:13:16.009002 RX DQ/DQS(Engine): PASS
9050 11:13:16.012760 TX OE : PASS
9051 11:13:16.013062 All Pass.
9052 11:13:16.013298
9053 11:13:16.013517 CH 1, Rank 0
9054 11:13:16.015830 SW Impedance : PASS
9055 11:13:16.019315 DUTY Scan : NO K
9056 11:13:16.019615 ZQ Calibration : PASS
9057 11:13:16.022326 Jitter Meter : NO K
9058 11:13:16.025939 CBT Training : PASS
9059 11:13:16.026270 Write leveling : PASS
9060 11:13:16.029005 RX DQS gating : PASS
9061 11:13:16.032219 RX DQ/DQS(RDDQC) : PASS
9062 11:13:16.032612 TX DQ/DQS : PASS
9063 11:13:16.035469 RX DATLAT : PASS
9064 11:13:16.039170 RX DQ/DQS(Engine): PASS
9065 11:13:16.039607 TX OE : PASS
9066 11:13:16.039937 All Pass.
9067 11:13:16.042406
9068 11:13:16.042783 CH 1, Rank 1
9069 11:13:16.045295 SW Impedance : PASS
9070 11:13:16.045613 DUTY Scan : NO K
9071 11:13:16.048856 ZQ Calibration : PASS
9072 11:13:16.052186 Jitter Meter : NO K
9073 11:13:16.052529 CBT Training : PASS
9074 11:13:16.055273 Write leveling : PASS
9075 11:13:16.055671 RX DQS gating : PASS
9076 11:13:16.058674 RX DQ/DQS(RDDQC) : PASS
9077 11:13:16.062400 TX DQ/DQS : PASS
9078 11:13:16.062744 RX DATLAT : PASS
9079 11:13:16.065072 RX DQ/DQS(Engine): PASS
9080 11:13:16.068470 TX OE : PASS
9081 11:13:16.068838 All Pass.
9082 11:13:16.069151
9083 11:13:16.071853 DramC Write-DBI on
9084 11:13:16.072152 PER_BANK_REFRESH: Hybrid Mode
9085 11:13:16.074890 TX_TRACKING: ON
9086 11:13:16.085128 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9087 11:13:16.092005 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9088 11:13:16.098652 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9089 11:13:16.101678 [FAST_K] Save calibration result to emmc
9090 11:13:16.105109 sync common calibartion params.
9091 11:13:16.108180 sync cbt_mode0:1, 1:1
9092 11:13:16.108599 dram_init: ddr_geometry: 2
9093 11:13:16.111820 dram_init: ddr_geometry: 2
9094 11:13:16.114805 dram_init: ddr_geometry: 2
9095 11:13:16.117993 0:dram_rank_size:100000000
9096 11:13:16.118515 1:dram_rank_size:100000000
9097 11:13:16.124516 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9098 11:13:16.127732 DFS_SHUFFLE_HW_MODE: ON
9099 11:13:16.131331 dramc_set_vcore_voltage set vcore to 725000
9100 11:13:16.134233 Read voltage for 1600, 0
9101 11:13:16.134781 Vio18 = 0
9102 11:13:16.135352 Vcore = 725000
9103 11:13:16.137648 Vdram = 0
9104 11:13:16.138246 Vddq = 0
9105 11:13:16.138725 Vmddr = 0
9106 11:13:16.141223 switch to 3200 Mbps bootup
9107 11:13:16.144557 [DramcRunTimeConfig]
9108 11:13:16.144979 PHYPLL
9109 11:13:16.145398 DPM_CONTROL_AFTERK: ON
9110 11:13:16.147834 PER_BANK_REFRESH: ON
9111 11:13:16.151261 REFRESH_OVERHEAD_REDUCTION: ON
9112 11:13:16.151699 CMD_PICG_NEW_MODE: OFF
9113 11:13:16.154016 XRTWTW_NEW_MODE: ON
9114 11:13:16.154504 XRTRTR_NEW_MODE: ON
9115 11:13:16.157298 TX_TRACKING: ON
9116 11:13:16.157726 RDSEL_TRACKING: OFF
9117 11:13:16.160644 DQS Precalculation for DVFS: ON
9118 11:13:16.163936 RX_TRACKING: OFF
9119 11:13:16.164399 HW_GATING DBG: ON
9120 11:13:16.167515 ZQCS_ENABLE_LP4: ON
9121 11:13:16.167936 RX_PICG_NEW_MODE: ON
9122 11:13:16.170908 TX_PICG_NEW_MODE: ON
9123 11:13:16.174190 ENABLE_RX_DCM_DPHY: ON
9124 11:13:16.177233 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9125 11:13:16.177658 DUMMY_READ_FOR_TRACKING: OFF
9126 11:13:16.180545 !!! SPM_CONTROL_AFTERK: OFF
9127 11:13:16.184235 !!! SPM could not control APHY
9128 11:13:16.186797 IMPEDANCE_TRACKING: ON
9129 11:13:16.186908 TEMP_SENSOR: ON
9130 11:13:16.190471 HW_SAVE_FOR_SR: OFF
9131 11:13:16.190554 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9132 11:13:16.197354 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9133 11:13:16.197436 Read ODT Tracking: ON
9134 11:13:16.199974 Refresh Rate DeBounce: ON
9135 11:13:16.203647 DFS_NO_QUEUE_FLUSH: ON
9136 11:13:16.206542 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9137 11:13:16.206624 ENABLE_DFS_RUNTIME_MRW: OFF
9138 11:13:16.210285 DDR_RESERVE_NEW_MODE: ON
9139 11:13:16.213438 MR_CBT_SWITCH_FREQ: ON
9140 11:13:16.213610 =========================
9141 11:13:16.232941 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9142 11:13:16.236067 dram_init: ddr_geometry: 2
9143 11:13:16.254345 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9144 11:13:16.257566 dram_init: dram init end (result: 0)
9145 11:13:16.264464 DRAM-K: Full calibration passed in 24525 msecs
9146 11:13:16.267889 MRC: failed to locate region type 0.
9147 11:13:16.267964 DRAM rank0 size:0x100000000,
9148 11:13:16.271321 DRAM rank1 size=0x100000000
9149 11:13:16.280999 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9150 11:13:16.287822 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9151 11:13:16.293926 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9152 11:13:16.304299 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9153 11:13:16.304384 DRAM rank0 size:0x100000000,
9154 11:13:16.307300 DRAM rank1 size=0x100000000
9155 11:13:16.307384 CBMEM:
9156 11:13:16.310671 IMD: root @ 0xfffff000 254 entries.
9157 11:13:16.313844 IMD: root @ 0xffffec00 62 entries.
9158 11:13:16.317610 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9159 11:13:16.323604 WARNING: RO_VPD is uninitialized or empty.
9160 11:13:16.327333 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9161 11:13:16.334825 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9162 11:13:16.347473 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9163 11:13:16.358543 BS: romstage times (exec / console): total (unknown) / 24000 ms
9164 11:13:16.358630
9165 11:13:16.358696
9166 11:13:16.368733 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9167 11:13:16.371745 ARM64: Exception handlers installed.
9168 11:13:16.375377 ARM64: Testing exception
9169 11:13:16.378638 ARM64: Done test exception
9170 11:13:16.378716 Enumerating buses...
9171 11:13:16.381786 Show all devs... Before device enumeration.
9172 11:13:16.385124 Root Device: enabled 1
9173 11:13:16.388508 CPU_CLUSTER: 0: enabled 1
9174 11:13:16.388601 CPU: 00: enabled 1
9175 11:13:16.391849 Compare with tree...
9176 11:13:16.391945 Root Device: enabled 1
9177 11:13:16.395424 CPU_CLUSTER: 0: enabled 1
9178 11:13:16.398027 CPU: 00: enabled 1
9179 11:13:16.398150 Root Device scanning...
9180 11:13:16.402207 scan_static_bus for Root Device
9181 11:13:16.405161 CPU_CLUSTER: 0 enabled
9182 11:13:16.408349 scan_static_bus for Root Device done
9183 11:13:16.411505 scan_bus: bus Root Device finished in 8 msecs
9184 11:13:16.411682 done
9185 11:13:16.418092 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9186 11:13:16.421719 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9187 11:13:16.428069 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9188 11:13:16.434710 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9189 11:13:16.435278 Allocating resources...
9190 11:13:16.438304 Reading resources...
9191 11:13:16.441388 Root Device read_resources bus 0 link: 0
9192 11:13:16.445015 DRAM rank0 size:0x100000000,
9193 11:13:16.445533 DRAM rank1 size=0x100000000
9194 11:13:16.451159 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9195 11:13:16.451627 CPU: 00 missing read_resources
9196 11:13:16.457672 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9197 11:13:16.461223 Root Device read_resources bus 0 link: 0 done
9198 11:13:16.464476 Done reading resources.
9199 11:13:16.467387 Show resources in subtree (Root Device)...After reading.
9200 11:13:16.470780 Root Device child on link 0 CPU_CLUSTER: 0
9201 11:13:16.474175 CPU_CLUSTER: 0 child on link 0 CPU: 00
9202 11:13:16.483776 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9203 11:13:16.484207 CPU: 00
9204 11:13:16.490691 Root Device assign_resources, bus 0 link: 0
9205 11:13:16.494205 CPU_CLUSTER: 0 missing set_resources
9206 11:13:16.497018 Root Device assign_resources, bus 0 link: 0 done
9207 11:13:16.500557 Done setting resources.
9208 11:13:16.504077 Show resources in subtree (Root Device)...After assigning values.
9209 11:13:16.506788 Root Device child on link 0 CPU_CLUSTER: 0
9210 11:13:16.513710 CPU_CLUSTER: 0 child on link 0 CPU: 00
9211 11:13:16.520162 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9212 11:13:16.523827 CPU: 00
9213 11:13:16.524383 Done allocating resources.
9214 11:13:16.530499 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9215 11:13:16.531013 Enabling resources...
9216 11:13:16.533608 done.
9217 11:13:16.536628 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9218 11:13:16.540066 Initializing devices...
9219 11:13:16.540499 Root Device init
9220 11:13:16.543080 init hardware done!
9221 11:13:16.543593 0x00000018: ctrlr->caps
9222 11:13:16.546801 52.000 MHz: ctrlr->f_max
9223 11:13:16.549888 0.400 MHz: ctrlr->f_min
9224 11:13:16.553626 0x40ff8080: ctrlr->voltages
9225 11:13:16.554207 sclk: 390625
9226 11:13:16.554702 Bus Width = 1
9227 11:13:16.556572 sclk: 390625
9228 11:13:16.556999 Bus Width = 1
9229 11:13:16.560093 Early init status = 3
9230 11:13:16.563261 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9231 11:13:16.567380 in-header: 03 fc 00 00 01 00 00 00
9232 11:13:16.570704 in-data: 00
9233 11:13:16.573641 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9234 11:13:16.579999 in-header: 03 fd 00 00 00 00 00 00
9235 11:13:16.583027 in-data:
9236 11:13:16.586610 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9237 11:13:16.590638 in-header: 03 fc 00 00 01 00 00 00
9238 11:13:16.593741 in-data: 00
9239 11:13:16.597416 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9240 11:13:16.603368 in-header: 03 fd 00 00 00 00 00 00
9241 11:13:16.606423 in-data:
9242 11:13:16.609708 [SSUSB] Setting up USB HOST controller...
9243 11:13:16.612692 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9244 11:13:16.616319 [SSUSB] phy power-on done.
9245 11:13:16.619482 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9246 11:13:16.626084 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9247 11:13:16.629224 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9248 11:13:16.635870 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9249 11:13:16.642393 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9250 11:13:16.649242 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9251 11:13:16.655378 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9252 11:13:16.662546 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9253 11:13:16.665582 SPM: binary array size = 0x9dc
9254 11:13:16.668764 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9255 11:13:16.675519 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9256 11:13:16.681863 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9257 11:13:16.688891 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9258 11:13:16.691503 configure_display: Starting display init
9259 11:13:16.726403 anx7625_power_on_init: Init interface.
9260 11:13:16.729543 anx7625_disable_pd_protocol: Disabled PD feature.
9261 11:13:16.732711 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9262 11:13:16.760446 anx7625_start_dp_work: Secure OCM version=00
9263 11:13:16.763406 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9264 11:13:16.778578 sp_tx_get_edid_block: EDID Block = 1
9265 11:13:16.881175 Extracted contents:
9266 11:13:16.884825 header: 00 ff ff ff ff ff ff 00
9267 11:13:16.887721 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9268 11:13:16.891129 version: 01 04
9269 11:13:16.894353 basic params: 95 1f 11 78 0a
9270 11:13:16.897874 chroma info: 76 90 94 55 54 90 27 21 50 54
9271 11:13:16.900820 established: 00 00 00
9272 11:13:16.907805 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9273 11:13:16.914319 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9274 11:13:16.917293 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9275 11:13:16.924054 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9276 11:13:16.930219 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9277 11:13:16.933673 extensions: 00
9278 11:13:16.934099 checksum: fb
9279 11:13:16.934438
9280 11:13:16.940595 Manufacturer: IVO Model 57d Serial Number 0
9281 11:13:16.941025 Made week 0 of 2020
9282 11:13:16.943782 EDID version: 1.4
9283 11:13:16.944277 Digital display
9284 11:13:16.947093 6 bits per primary color channel
9285 11:13:16.950247 DisplayPort interface
9286 11:13:16.950720 Maximum image size: 31 cm x 17 cm
9287 11:13:16.954193 Gamma: 220%
9288 11:13:16.954645 Check DPMS levels
9289 11:13:16.960390 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9290 11:13:16.963546 First detailed timing is preferred timing
9291 11:13:16.966502 Established timings supported:
9292 11:13:16.966999 Standard timings supported:
9293 11:13:16.970295 Detailed timings
9294 11:13:16.973259 Hex of detail: 383680a07038204018303c0035ae10000019
9295 11:13:16.979775 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9296 11:13:16.983489 0780 0798 07c8 0820 hborder 0
9297 11:13:16.986698 0438 043b 0447 0458 vborder 0
9298 11:13:16.989719 -hsync -vsync
9299 11:13:16.990139 Did detailed timing
9300 11:13:16.996144 Hex of detail: 000000000000000000000000000000000000
9301 11:13:16.999524 Manufacturer-specified data, tag 0
9302 11:13:17.002887 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9303 11:13:17.005928 ASCII string: InfoVision
9304 11:13:17.009313 Hex of detail: 000000fe00523134304e574635205248200a
9305 11:13:17.012702 ASCII string: R140NWF5 RH
9306 11:13:17.012929 Checksum
9307 11:13:17.016187 Checksum: 0xfb (valid)
9308 11:13:17.019130 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9309 11:13:17.022791 DSI data_rate: 832800000 bps
9310 11:13:17.029448 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9311 11:13:17.032684 anx7625_parse_edid: pixelclock(138800).
9312 11:13:17.036387 hactive(1920), hsync(48), hfp(24), hbp(88)
9313 11:13:17.039271 vactive(1080), vsync(12), vfp(3), vbp(17)
9314 11:13:17.042897 anx7625_dsi_config: config dsi.
9315 11:13:17.049144 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9316 11:13:17.063390 anx7625_dsi_config: success to config DSI
9317 11:13:17.066400 anx7625_dp_start: MIPI phy setup OK.
9318 11:13:17.070335 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9319 11:13:17.073129 mtk_ddp_mode_set invalid vrefresh 60
9320 11:13:17.075840 main_disp_path_setup
9321 11:13:17.075920 ovl_layer_smi_id_en
9322 11:13:17.079251 ovl_layer_smi_id_en
9323 11:13:17.079331 ccorr_config
9324 11:13:17.079394 aal_config
9325 11:13:17.082780 gamma_config
9326 11:13:17.082915 postmask_config
9327 11:13:17.085858 dither_config
9328 11:13:17.089481 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9329 11:13:17.096070 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9330 11:13:17.099155 Root Device init finished in 555 msecs
9331 11:13:17.102170 CPU_CLUSTER: 0 init
9332 11:13:17.109097 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9333 11:13:17.115706 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9334 11:13:17.115819 APU_MBOX 0x190000b0 = 0x10001
9335 11:13:17.119055 APU_MBOX 0x190001b0 = 0x10001
9336 11:13:17.122400 APU_MBOX 0x190005b0 = 0x10001
9337 11:13:17.125338 APU_MBOX 0x190006b0 = 0x10001
9338 11:13:17.132534 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9339 11:13:17.142426 read SPI 0x539f4 0xe237: 6246 us, 9271 KB/s, 74.168 Mbps
9340 11:13:17.154585 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9341 11:13:17.161174 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9342 11:13:17.172594 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9343 11:13:17.181791 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9344 11:13:17.185299 CPU_CLUSTER: 0 init finished in 81 msecs
9345 11:13:17.188949 Devices initialized
9346 11:13:17.192052 Show all devs... After init.
9347 11:13:17.192532 Root Device: enabled 1
9348 11:13:17.195257 CPU_CLUSTER: 0: enabled 1
9349 11:13:17.198317 CPU: 00: enabled 1
9350 11:13:17.201985 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9351 11:13:17.205098 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9352 11:13:17.208626 ELOG: NV offset 0x57f000 size 0x1000
9353 11:13:17.215229 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9354 11:13:17.221589 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9355 11:13:17.224875 ELOG: Event(17) added with size 13 at 2023-06-05 11:13:17 UTC
9356 11:13:17.231341 out: cmd=0x121: 03 db 21 01 00 00 00 00
9357 11:13:17.234608 in-header: 03 85 00 00 2c 00 00 00
9358 11:13:17.244895 in-data: da 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9359 11:13:17.251472 ELOG: Event(A1) added with size 10 at 2023-06-05 11:13:17 UTC
9360 11:13:17.258099 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9361 11:13:17.264344 ELOG: Event(A0) added with size 9 at 2023-06-05 11:13:17 UTC
9362 11:13:17.267821 elog_add_boot_reason: Logged dev mode boot
9363 11:13:17.274561 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9364 11:13:17.275152 Finalize devices...
9365 11:13:17.277600 Devices finalized
9366 11:13:17.280645 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9367 11:13:17.284608 Writing coreboot table at 0xffe64000
9368 11:13:17.287491 0. 000000000010a000-0000000000113fff: RAMSTAGE
9369 11:13:17.293874 1. 0000000040000000-00000000400fffff: RAM
9370 11:13:17.296921 2. 0000000040100000-000000004032afff: RAMSTAGE
9371 11:13:17.300640 3. 000000004032b000-00000000545fffff: RAM
9372 11:13:17.303650 4. 0000000054600000-000000005465ffff: BL31
9373 11:13:17.306767 5. 0000000054660000-00000000ffe63fff: RAM
9374 11:13:17.313823 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9375 11:13:17.316914 7. 0000000100000000-000000023fffffff: RAM
9376 11:13:17.320586 Passing 5 GPIOs to payload:
9377 11:13:17.323576 NAME | PORT | POLARITY | VALUE
9378 11:13:17.330448 EC in RW | 0x000000aa | low | undefined
9379 11:13:17.333311 EC interrupt | 0x00000005 | low | undefined
9380 11:13:17.336496 TPM interrupt | 0x000000ab | high | undefined
9381 11:13:17.343463 SD card detect | 0x00000011 | high | undefined
9382 11:13:17.346820 speaker enable | 0x00000093 | high | undefined
9383 11:13:17.350438 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9384 11:13:17.353307 in-header: 03 f9 00 00 02 00 00 00
9385 11:13:17.356816 in-data: 02 00
9386 11:13:17.360142 ADC[4]: Raw value=895191 ID=7
9387 11:13:17.360239 ADC[3]: Raw value=213070 ID=1
9388 11:13:17.363044 RAM Code: 0x71
9389 11:13:17.366525 ADC[6]: Raw value=74722 ID=0
9390 11:13:17.369498 ADC[5]: Raw value=212700 ID=1
9391 11:13:17.369619 SKU Code: 0x1
9392 11:13:17.376273 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 7dbf
9393 11:13:17.376401 coreboot table: 964 bytes.
9394 11:13:17.379836 IMD ROOT 0. 0xfffff000 0x00001000
9395 11:13:17.382867 IMD SMALL 1. 0xffffe000 0x00001000
9396 11:13:17.386618 RO MCACHE 2. 0xffffc000 0x00001104
9397 11:13:17.389704 CONSOLE 3. 0xfff7c000 0x00080000
9398 11:13:17.392973 FMAP 4. 0xfff7b000 0x00000452
9399 11:13:17.396080 TIME STAMP 5. 0xfff7a000 0x00000910
9400 11:13:17.399150 VBOOT WORK 6. 0xfff66000 0x00014000
9401 11:13:17.402843 RAMOOPS 7. 0xffe66000 0x00100000
9402 11:13:17.406020 COREBOOT 8. 0xffe64000 0x00002000
9403 11:13:17.409055 IMD small region:
9404 11:13:17.412784 IMD ROOT 0. 0xffffec00 0x00000400
9405 11:13:17.415719 VPD 1. 0xffffeba0 0x0000004c
9406 11:13:17.419213 MMC STATUS 2. 0xffffeb80 0x00000004
9407 11:13:17.425831 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9408 11:13:17.425943 Probing TPM: done!
9409 11:13:17.432272 Connected to device vid:did:rid of 1ae0:0028:00
9410 11:13:17.439233 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9411 11:13:17.442452 Initialized TPM device CR50 revision 0
9412 11:13:17.445687 Checking cr50 for pending updates
9413 11:13:17.451574 Reading cr50 TPM mode
9414 11:13:17.459756 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9415 11:13:17.466652 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9416 11:13:17.506318 read SPI 0x3990ec 0x4f1b0: 34851 us, 9297 KB/s, 74.376 Mbps
9417 11:13:17.510032 Checking segment from ROM address 0x40100000
9418 11:13:17.513025 Checking segment from ROM address 0x4010001c
9419 11:13:17.519717 Loading segment from ROM address 0x40100000
9420 11:13:17.519816 code (compression=0)
9421 11:13:17.529451 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9422 11:13:17.536384 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9423 11:13:17.536479 it's not compressed!
9424 11:13:17.543025 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9425 11:13:17.549030 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9426 11:13:17.566902 Loading segment from ROM address 0x4010001c
9427 11:13:17.567012 Entry Point 0x80000000
9428 11:13:17.570500 Loaded segments
9429 11:13:17.573470 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9430 11:13:17.580102 Jumping to boot code at 0x80000000(0xffe64000)
9431 11:13:17.586545 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9432 11:13:17.593220 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9433 11:13:17.601403 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9434 11:13:17.604462 Checking segment from ROM address 0x40100000
9435 11:13:17.608204 Checking segment from ROM address 0x4010001c
9436 11:13:17.614552 Loading segment from ROM address 0x40100000
9437 11:13:17.614642 code (compression=1)
9438 11:13:17.621113 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9439 11:13:17.630788 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9440 11:13:17.630958 using LZMA
9441 11:13:17.639928 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9442 11:13:17.646668 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9443 11:13:17.649797 Loading segment from ROM address 0x4010001c
9444 11:13:17.649883 Entry Point 0x54601000
9445 11:13:17.652685 Loaded segments
9446 11:13:17.656401 NOTICE: MT8192 bl31_setup
9447 11:13:17.662953 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9448 11:13:17.666254 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9449 11:13:17.669979 WARNING: region 0:
9450 11:13:17.672983 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9451 11:13:17.673069 WARNING: region 1:
9452 11:13:17.680092 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9453 11:13:17.683330 WARNING: region 2:
9454 11:13:17.686058 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9455 11:13:17.689514 WARNING: region 3:
9456 11:13:17.696014 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9457 11:13:17.696123 WARNING: region 4:
9458 11:13:17.703088 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9459 11:13:17.703192 WARNING: region 5:
9460 11:13:17.705964 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9461 11:13:17.709667 WARNING: region 6:
9462 11:13:17.712871 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9463 11:13:17.715885 WARNING: region 7:
9464 11:13:17.719663 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9465 11:13:17.725895 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9466 11:13:17.729587 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9467 11:13:17.736140 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9468 11:13:17.739187 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9469 11:13:17.742333 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9470 11:13:17.749406 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9471 11:13:17.752434 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9472 11:13:17.755953 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9473 11:13:17.762566 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9474 11:13:17.765603 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9475 11:13:17.772508 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9476 11:13:17.775474 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9477 11:13:17.778813 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9478 11:13:17.785798 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9479 11:13:17.789180 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9480 11:13:17.792323 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9481 11:13:17.799019 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9482 11:13:17.802421 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9483 11:13:17.808893 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9484 11:13:17.811947 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9485 11:13:17.815533 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9486 11:13:17.821839 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9487 11:13:17.825475 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9488 11:13:17.831636 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9489 11:13:17.835104 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9490 11:13:17.838725 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9491 11:13:17.845466 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9492 11:13:17.848384 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9493 11:13:17.855243 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9494 11:13:17.858261 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9495 11:13:17.864581 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9496 11:13:17.867666 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9497 11:13:17.871434 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9498 11:13:17.874401 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9499 11:13:17.881149 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9500 11:13:17.884735 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9501 11:13:17.887797 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9502 11:13:17.891195 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9503 11:13:17.897458 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9504 11:13:17.901016 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9505 11:13:17.904319 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9506 11:13:17.907565 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9507 11:13:17.914394 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9508 11:13:17.917786 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9509 11:13:17.921337 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9510 11:13:17.927900 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9511 11:13:17.931011 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9512 11:13:17.934082 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9513 11:13:17.937660 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9514 11:13:17.944438 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9515 11:13:17.947325 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9516 11:13:17.953811 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9517 11:13:17.957577 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9518 11:13:17.964219 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9519 11:13:17.967097 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9520 11:13:17.973938 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9521 11:13:17.977493 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9522 11:13:17.980490 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9523 11:13:17.987191 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9524 11:13:17.990638 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9525 11:13:17.996982 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9526 11:13:18.000533 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9527 11:13:18.006712 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9528 11:13:18.010195 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9529 11:13:18.017316 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9530 11:13:18.020391 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9531 11:13:18.023757 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9532 11:13:18.030093 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9533 11:13:18.033821 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9534 11:13:18.040291 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9535 11:13:18.043606 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9536 11:13:18.050289 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9537 11:13:18.053347 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9538 11:13:18.056959 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9539 11:13:18.063698 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9540 11:13:18.066717 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9541 11:13:18.073314 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9542 11:13:18.077242 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9543 11:13:18.083770 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9544 11:13:18.086663 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9545 11:13:18.093303 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9546 11:13:18.096822 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9547 11:13:18.100008 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9548 11:13:18.106859 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9549 11:13:18.110198 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9550 11:13:18.116643 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9551 11:13:18.119626 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9552 11:13:18.126588 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9553 11:13:18.129636 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9554 11:13:18.133021 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9555 11:13:18.139525 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9556 11:13:18.143201 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9557 11:13:18.149604 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9558 11:13:18.153273 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9559 11:13:18.159435 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9560 11:13:18.163043 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9561 11:13:18.166076 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9562 11:13:18.172778 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9563 11:13:18.176382 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9564 11:13:18.179494 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9565 11:13:18.182587 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9566 11:13:18.189383 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9567 11:13:18.192965 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9568 11:13:18.199523 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9569 11:13:18.202389 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9570 11:13:18.205973 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9571 11:13:18.212193 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9572 11:13:18.215994 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9573 11:13:18.222568 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9574 11:13:18.225477 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9575 11:13:18.229140 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9576 11:13:18.235466 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9577 11:13:18.239149 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9578 11:13:18.245355 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9579 11:13:18.249081 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9580 11:13:18.251941 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9581 11:13:18.259123 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9582 11:13:18.262264 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9583 11:13:18.265187 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9584 11:13:18.271900 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9585 11:13:18.275469 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9586 11:13:18.278859 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9587 11:13:18.281928 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9588 11:13:18.288606 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9589 11:13:18.292194 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9590 11:13:18.295292 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9591 11:13:18.302209 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9592 11:13:18.305088 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9593 11:13:18.312157 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9594 11:13:18.315589 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9595 11:13:18.318640 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9596 11:13:18.325133 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9597 11:13:18.328100 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9598 11:13:18.335034 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9599 11:13:18.337955 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9600 11:13:18.341481 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9601 11:13:18.348576 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9602 11:13:18.351426 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9603 11:13:18.357994 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9604 11:13:18.361613 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9605 11:13:18.364775 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9606 11:13:18.371596 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9607 11:13:18.374625 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9608 11:13:18.381689 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9609 11:13:18.384720 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9610 11:13:18.387770 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9611 11:13:18.394938 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9612 11:13:18.397971 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9613 11:13:18.404793 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9614 11:13:18.407904 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9615 11:13:18.410806 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9616 11:13:18.418131 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9617 11:13:18.420864 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9618 11:13:18.427777 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9619 11:13:18.430730 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9620 11:13:18.434227 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9621 11:13:18.440519 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9622 11:13:18.444018 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9623 11:13:18.447423 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9624 11:13:18.453913 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9625 11:13:18.457368 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9626 11:13:18.463931 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9627 11:13:18.466996 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9628 11:13:18.473678 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9629 11:13:18.477393 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9630 11:13:18.480353 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9631 11:13:18.487063 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9632 11:13:18.490127 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9633 11:13:18.496636 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9634 11:13:18.500227 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9635 11:13:18.503314 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9636 11:13:18.510421 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9637 11:13:18.513200 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9638 11:13:18.516800 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9639 11:13:18.523284 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9640 11:13:18.526721 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9641 11:13:18.533194 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9642 11:13:18.536578 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9643 11:13:18.540056 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9644 11:13:18.546345 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9645 11:13:18.549704 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9646 11:13:18.556299 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9647 11:13:18.559842 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9648 11:13:18.563339 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9649 11:13:18.570019 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9650 11:13:18.573092 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9651 11:13:18.579735 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9652 11:13:18.583036 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9653 11:13:18.586502 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9654 11:13:18.593029 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9655 11:13:18.596133 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9656 11:13:18.602626 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9657 11:13:18.606357 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9658 11:13:18.612527 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9659 11:13:18.616144 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9660 11:13:18.619178 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9661 11:13:18.625677 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9662 11:13:18.629155 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9663 11:13:18.635918 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9664 11:13:18.638763 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9665 11:13:18.645366 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9666 11:13:18.648659 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9667 11:13:18.652236 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9668 11:13:18.658589 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9669 11:13:18.662063 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9670 11:13:18.668633 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9671 11:13:18.672163 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9672 11:13:18.678469 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9673 11:13:18.682036 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9674 11:13:18.685099 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9675 11:13:18.691569 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9676 11:13:18.695074 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9677 11:13:18.701964 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9678 11:13:18.704941 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9679 11:13:18.711601 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9680 11:13:18.714726 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9681 11:13:18.718462 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9682 11:13:18.724920 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9683 11:13:18.727789 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9684 11:13:18.734682 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9685 11:13:18.737577 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9686 11:13:18.744737 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9687 11:13:18.747957 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9688 11:13:18.750723 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9689 11:13:18.757737 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9690 11:13:18.760977 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9691 11:13:18.767467 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9692 11:13:18.771345 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9693 11:13:18.773892 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9694 11:13:18.781147 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9695 11:13:18.783904 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9696 11:13:18.787398 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9697 11:13:18.790523 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9698 11:13:18.797236 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9699 11:13:18.800807 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9700 11:13:18.803937 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9701 11:13:18.810558 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9702 11:13:18.813962 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9703 11:13:18.820412 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9704 11:13:18.823452 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9705 11:13:18.827108 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9706 11:13:18.833942 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9707 11:13:18.836848 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9708 11:13:18.840334 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9709 11:13:18.846626 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9710 11:13:18.850261 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9711 11:13:18.856829 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9712 11:13:18.859761 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9713 11:13:18.863166 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9714 11:13:18.869980 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9715 11:13:18.872899 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9716 11:13:18.876498 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9717 11:13:18.882938 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9718 11:13:18.886236 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9719 11:13:18.892686 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9720 11:13:18.896342 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9721 11:13:18.899408 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9722 11:13:18.906212 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9723 11:13:18.909243 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9724 11:13:18.912887 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9725 11:13:18.919042 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9726 11:13:18.922805 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9727 11:13:18.929022 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9728 11:13:18.932251 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9729 11:13:18.935980 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9730 11:13:18.942146 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9731 11:13:18.945597 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9732 11:13:18.952126 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9733 11:13:18.955597 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9734 11:13:18.959130 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9735 11:13:18.962432 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9736 11:13:18.965775 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9737 11:13:18.972030 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9738 11:13:18.975867 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9739 11:13:18.978803 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9740 11:13:18.981834 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9741 11:13:18.988568 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9742 11:13:18.991985 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9743 11:13:18.995105 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9744 11:13:18.998717 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9745 11:13:19.005275 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9746 11:13:19.008265 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9747 11:13:19.011956 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9748 11:13:19.018380 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9749 11:13:19.021371 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9750 11:13:19.028015 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9751 11:13:19.031640 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9752 11:13:19.037866 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9753 11:13:19.041543 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9754 11:13:19.044782 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9755 11:13:19.051048 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9756 11:13:19.054805 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9757 11:13:19.061246 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9758 11:13:19.064637 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9759 11:13:19.070985 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9760 11:13:19.074351 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9761 11:13:19.077778 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9762 11:13:19.084337 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9763 11:13:19.087888 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9764 11:13:19.094340 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9765 11:13:19.097401 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9766 11:13:19.100924 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9767 11:13:19.107214 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9768 11:13:19.110733 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9769 11:13:19.117487 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9770 11:13:19.120590 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9771 11:13:19.127187 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9772 11:13:19.130266 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9773 11:13:19.133400 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9774 11:13:19.140000 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9775 11:13:19.143675 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9776 11:13:19.150381 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9777 11:13:19.153323 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9778 11:13:19.156812 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9779 11:13:19.163118 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9780 11:13:19.166801 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9781 11:13:19.172960 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9782 11:13:19.176469 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9783 11:13:19.183245 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9784 11:13:19.186118 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9785 11:13:19.192978 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9786 11:13:19.196194 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9787 11:13:19.199679 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9788 11:13:19.205721 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9789 11:13:19.209550 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9790 11:13:19.215689 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9791 11:13:19.219289 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9792 11:13:19.222350 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9793 11:13:19.229021 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9794 11:13:19.232126 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9795 11:13:19.239029 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9796 11:13:19.242072 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9797 11:13:19.248279 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9798 11:13:19.251870 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9799 11:13:19.255073 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9800 11:13:19.261949 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9801 11:13:19.265194 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9802 11:13:19.271822 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9803 11:13:19.274631 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9804 11:13:19.281357 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9805 11:13:19.284278 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9806 11:13:19.287675 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9807 11:13:19.294530 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9808 11:13:19.298112 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9809 11:13:19.304665 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9810 11:13:19.307602 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9811 11:13:19.311191 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9812 11:13:19.317662 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9813 11:13:19.321031 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9814 11:13:19.327568 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9815 11:13:19.330500 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9816 11:13:19.337266 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9817 11:13:19.341074 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9818 11:13:19.344233 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9819 11:13:19.350243 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9820 11:13:19.353856 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9821 11:13:19.360542 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9822 11:13:19.363481 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9823 11:13:19.370495 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9824 11:13:19.373483 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9825 11:13:19.380172 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9826 11:13:19.383623 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9827 11:13:19.386857 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9828 11:13:19.393210 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9829 11:13:19.396649 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9830 11:13:19.402971 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9831 11:13:19.406388 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9832 11:13:19.412950 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9833 11:13:19.416517 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9834 11:13:19.420058 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9835 11:13:19.426270 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9836 11:13:19.429658 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9837 11:13:19.436258 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9838 11:13:19.439264 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9839 11:13:19.446047 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9840 11:13:19.449133 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9841 11:13:19.455948 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9842 11:13:19.459000 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9843 11:13:19.465861 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9844 11:13:19.468786 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9845 11:13:19.472424 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9846 11:13:19.478788 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9847 11:13:19.482337 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9848 11:13:19.488569 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9849 11:13:19.491928 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9850 11:13:19.498220 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9851 11:13:19.501498 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9852 11:13:19.508399 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9853 11:13:19.511299 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9854 11:13:19.518460 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9855 11:13:19.521522 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9856 11:13:19.524535 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9857 11:13:19.531334 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9858 11:13:19.534613 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9859 11:13:19.541415 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9860 11:13:19.544456 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9861 11:13:19.551179 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9862 11:13:19.554223 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9863 11:13:19.561070 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9864 11:13:19.564002 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9865 11:13:19.570682 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9866 11:13:19.573757 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9867 11:13:19.577411 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9868 11:13:19.583834 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9869 11:13:19.586773 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9870 11:13:19.593889 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9871 11:13:19.597438 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9872 11:13:19.603404 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9873 11:13:19.606821 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9874 11:13:19.613297 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9875 11:13:19.616638 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9876 11:13:19.623008 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9877 11:13:19.626704 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9878 11:13:19.632897 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9879 11:13:19.636545 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9880 11:13:19.642988 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9881 11:13:19.645891 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9882 11:13:19.652311 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9883 11:13:19.656003 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9884 11:13:19.662490 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9885 11:13:19.665655 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9886 11:13:19.672560 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9887 11:13:19.675611 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9888 11:13:19.682468 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9889 11:13:19.685453 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9890 11:13:19.691797 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9891 11:13:19.695281 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9892 11:13:19.701721 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9893 11:13:19.705399 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9894 11:13:19.711803 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9895 11:13:19.715319 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9896 11:13:19.721520 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9897 11:13:19.724961 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9898 11:13:19.731149 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9899 11:13:19.734990 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9900 11:13:19.738124 INFO: [APUAPC] vio 0
9901 11:13:19.741216 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9902 11:13:19.747988 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9903 11:13:19.751513 INFO: [APUAPC] D0_APC_0: 0x400510
9904 11:13:19.754381 INFO: [APUAPC] D0_APC_1: 0x0
9905 11:13:19.754462 INFO: [APUAPC] D0_APC_2: 0x1540
9906 11:13:19.757648 INFO: [APUAPC] D0_APC_3: 0x0
9907 11:13:19.761373 INFO: [APUAPC] D1_APC_0: 0xffffffff
9908 11:13:19.764580 INFO: [APUAPC] D1_APC_1: 0xffffffff
9909 11:13:19.767710 INFO: [APUAPC] D1_APC_2: 0x3fffff
9910 11:13:19.771418 INFO: [APUAPC] D1_APC_3: 0x0
9911 11:13:19.774423 INFO: [APUAPC] D2_APC_0: 0xffffffff
9912 11:13:19.777494 INFO: [APUAPC] D2_APC_1: 0xffffffff
9913 11:13:19.781162 INFO: [APUAPC] D2_APC_2: 0x3fffff
9914 11:13:19.784255 INFO: [APUAPC] D2_APC_3: 0x0
9915 11:13:19.787400 INFO: [APUAPC] D3_APC_0: 0xffffffff
9916 11:13:19.790781 INFO: [APUAPC] D3_APC_1: 0xffffffff
9917 11:13:19.794392 INFO: [APUAPC] D3_APC_2: 0x3fffff
9918 11:13:19.797459 INFO: [APUAPC] D3_APC_3: 0x0
9919 11:13:19.800908 INFO: [APUAPC] D4_APC_0: 0xffffffff
9920 11:13:19.803901 INFO: [APUAPC] D4_APC_1: 0xffffffff
9921 11:13:19.807263 INFO: [APUAPC] D4_APC_2: 0x3fffff
9922 11:13:19.810534 INFO: [APUAPC] D4_APC_3: 0x0
9923 11:13:19.814069 INFO: [APUAPC] D5_APC_0: 0xffffffff
9924 11:13:19.816890 INFO: [APUAPC] D5_APC_1: 0xffffffff
9925 11:13:19.820302 INFO: [APUAPC] D5_APC_2: 0x3fffff
9926 11:13:19.823676 INFO: [APUAPC] D5_APC_3: 0x0
9927 11:13:19.826961 INFO: [APUAPC] D6_APC_0: 0xffffffff
9928 11:13:19.830435 INFO: [APUAPC] D6_APC_1: 0xffffffff
9929 11:13:19.833237 INFO: [APUAPC] D6_APC_2: 0x3fffff
9930 11:13:19.836770 INFO: [APUAPC] D6_APC_3: 0x0
9931 11:13:19.840494 INFO: [APUAPC] D7_APC_0: 0xffffffff
9932 11:13:19.843712 INFO: [APUAPC] D7_APC_1: 0xffffffff
9933 11:13:19.846608 INFO: [APUAPC] D7_APC_2: 0x3fffff
9934 11:13:19.850207 INFO: [APUAPC] D7_APC_3: 0x0
9935 11:13:19.853244 INFO: [APUAPC] D8_APC_0: 0xffffffff
9936 11:13:19.856744 INFO: [APUAPC] D8_APC_1: 0xffffffff
9937 11:13:19.859729 INFO: [APUAPC] D8_APC_2: 0x3fffff
9938 11:13:19.863176 INFO: [APUAPC] D8_APC_3: 0x0
9939 11:13:19.866272 INFO: [APUAPC] D9_APC_0: 0xffffffff
9940 11:13:19.869872 INFO: [APUAPC] D9_APC_1: 0xffffffff
9941 11:13:19.872918 INFO: [APUAPC] D9_APC_2: 0x3fffff
9942 11:13:19.876695 INFO: [APUAPC] D9_APC_3: 0x0
9943 11:13:19.879859 INFO: [APUAPC] D10_APC_0: 0xffffffff
9944 11:13:19.882901 INFO: [APUAPC] D10_APC_1: 0xffffffff
9945 11:13:19.886099 INFO: [APUAPC] D10_APC_2: 0x3fffff
9946 11:13:19.889836 INFO: [APUAPC] D10_APC_3: 0x0
9947 11:13:19.892973 INFO: [APUAPC] D11_APC_0: 0xffffffff
9948 11:13:19.896483 INFO: [APUAPC] D11_APC_1: 0xffffffff
9949 11:13:19.899450 INFO: [APUAPC] D11_APC_2: 0x3fffff
9950 11:13:19.903037 INFO: [APUAPC] D11_APC_3: 0x0
9951 11:13:19.905879 INFO: [APUAPC] D12_APC_0: 0xffffffff
9952 11:13:19.909815 INFO: [APUAPC] D12_APC_1: 0xffffffff
9953 11:13:19.912940 INFO: [APUAPC] D12_APC_2: 0x3fffff
9954 11:13:19.916241 INFO: [APUAPC] D12_APC_3: 0x0
9955 11:13:19.919097 INFO: [APUAPC] D13_APC_0: 0xffffffff
9956 11:13:19.922812 INFO: [APUAPC] D13_APC_1: 0xffffffff
9957 11:13:19.926345 INFO: [APUAPC] D13_APC_2: 0x3fffff
9958 11:13:19.929228 INFO: [APUAPC] D13_APC_3: 0x0
9959 11:13:19.932618 INFO: [APUAPC] D14_APC_0: 0xffffffff
9960 11:13:19.936021 INFO: [APUAPC] D14_APC_1: 0xffffffff
9961 11:13:19.938903 INFO: [APUAPC] D14_APC_2: 0x3fffff
9962 11:13:19.942411 INFO: [APUAPC] D14_APC_3: 0x0
9963 11:13:19.945356 INFO: [APUAPC] D15_APC_0: 0xffffffff
9964 11:13:19.949140 INFO: [APUAPC] D15_APC_1: 0xffffffff
9965 11:13:19.952059 INFO: [APUAPC] D15_APC_2: 0x3fffff
9966 11:13:19.955667 INFO: [APUAPC] D15_APC_3: 0x0
9967 11:13:19.958770 INFO: [APUAPC] APC_CON: 0x4
9968 11:13:19.962296 INFO: [NOCDAPC] D0_APC_0: 0x0
9969 11:13:19.965333 INFO: [NOCDAPC] D0_APC_1: 0x0
9970 11:13:19.968831 INFO: [NOCDAPC] D1_APC_0: 0x0
9971 11:13:19.971860 INFO: [NOCDAPC] D1_APC_1: 0xfff
9972 11:13:19.975527 INFO: [NOCDAPC] D2_APC_0: 0x0
9973 11:13:19.975609 INFO: [NOCDAPC] D2_APC_1: 0xfff
9974 11:13:19.978506 INFO: [NOCDAPC] D3_APC_0: 0x0
9975 11:13:19.981599 INFO: [NOCDAPC] D3_APC_1: 0xfff
9976 11:13:19.985403 INFO: [NOCDAPC] D4_APC_0: 0x0
9977 11:13:19.988399 INFO: [NOCDAPC] D4_APC_1: 0xfff
9978 11:13:19.991445 INFO: [NOCDAPC] D5_APC_0: 0x0
9979 11:13:19.995120 INFO: [NOCDAPC] D5_APC_1: 0xfff
9980 11:13:19.998194 INFO: [NOCDAPC] D6_APC_0: 0x0
9981 11:13:20.001822 INFO: [NOCDAPC] D6_APC_1: 0xfff
9982 11:13:20.004766 INFO: [NOCDAPC] D7_APC_0: 0x0
9983 11:13:20.008451 INFO: [NOCDAPC] D7_APC_1: 0xfff
9984 11:13:20.011435 INFO: [NOCDAPC] D8_APC_0: 0x0
9985 11:13:20.015197 INFO: [NOCDAPC] D8_APC_1: 0xfff
9986 11:13:20.015278 INFO: [NOCDAPC] D9_APC_0: 0x0
9987 11:13:20.017854 INFO: [NOCDAPC] D9_APC_1: 0xfff
9988 11:13:20.021193 INFO: [NOCDAPC] D10_APC_0: 0x0
9989 11:13:20.025061 INFO: [NOCDAPC] D10_APC_1: 0xfff
9990 11:13:20.027832 INFO: [NOCDAPC] D11_APC_0: 0x0
9991 11:13:20.031055 INFO: [NOCDAPC] D11_APC_1: 0xfff
9992 11:13:20.034546 INFO: [NOCDAPC] D12_APC_0: 0x0
9993 11:13:20.037990 INFO: [NOCDAPC] D12_APC_1: 0xfff
9994 11:13:20.041461 INFO: [NOCDAPC] D13_APC_0: 0x0
9995 11:13:20.044321 INFO: [NOCDAPC] D13_APC_1: 0xfff
9996 11:13:20.047728 INFO: [NOCDAPC] D14_APC_0: 0x0
9997 11:13:20.051246 INFO: [NOCDAPC] D14_APC_1: 0xfff
9998 11:13:20.054184 INFO: [NOCDAPC] D15_APC_0: 0x0
9999 11:13:20.057714 INFO: [NOCDAPC] D15_APC_1: 0xfff
10000 11:13:20.057795 INFO: [NOCDAPC] APC_CON: 0x4
10001 11:13:20.063912 INFO: [APUAPC] set_apusys_apc done
10002 11:13:20.064005 INFO: [DEVAPC] devapc_init done
10003 11:13:20.070543 INFO: GICv3 without legacy support detected.
10004 11:13:20.074359 INFO: ARM GICv3 driver initialized in EL3
10005 11:13:20.077583 INFO: Maximum SPI INTID supported: 639
10006 11:13:20.080681 INFO: BL31: Initializing runtime services
10007 11:13:20.087408 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10008 11:13:20.090555 INFO: SPM: enable CPC mode
10009 11:13:20.094125 INFO: mcdi ready for mcusys-off-idle and system suspend
10010 11:13:20.100279 INFO: BL31: Preparing for EL3 exit to normal world
10011 11:13:20.103970 INFO: Entry point address = 0x80000000
10012 11:13:20.104051 INFO: SPSR = 0x8
10013 11:13:20.111408
10014 11:13:20.111489
10015 11:13:20.111554
10016 11:13:20.114542 Starting depthcharge on Spherion...
10017 11:13:20.114624
10018 11:13:20.114710 Wipe memory regions:
10019 11:13:20.114772
10020 11:13:20.115370 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10021 11:13:20.115468 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10022 11:13:20.115547 Setting prompt string to ['asurada:']
10023 11:13:20.115622 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10024 11:13:20.118095 [0x00000040000000, 0x00000054600000)
10025 11:13:20.240042
10026 11:13:20.243400 [0x00000054660000, 0x00000080000000)
10027 11:13:20.501030
10028 11:13:20.501168 [0x000000821a7280, 0x000000ffe64000)
10029 11:13:21.245109
10030 11:13:21.245258 [0x00000100000000, 0x00000240000000)
10031 11:13:23.133777
10032 11:13:23.137441 Initializing XHCI USB controller at 0x11200000.
10033 11:13:24.174646
10034 11:13:24.177695 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10035 11:13:24.177782
10036 11:13:24.177847
10037 11:13:24.177907
10038 11:13:24.178181 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10040 11:13:24.278504 asurada: tftpboot 192.168.201.1 10591235/tftp-deploy-qhjhjj89/kernel/image.itb 10591235/tftp-deploy-qhjhjj89/kernel/cmdline
10041 11:13:24.278658 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10042 11:13:24.278756 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10043 11:13:24.283077 tftpboot 192.168.201.1 10591235/tftp-deploy-qhjhjj89/kernel/image.itp-deploy-qhjhjj89/kernel/cmdline
10044 11:13:24.283161
10045 11:13:24.283225 Waiting for link
10046 11:13:24.443459
10047 11:13:24.443601 R8152: Initializing
10048 11:13:24.443670
10049 11:13:24.446442 Version 6 (ocp_data = 5c30)
10050 11:13:24.446513
10051 11:13:24.449599 R8152: Done initializing
10052 11:13:24.449681
10053 11:13:24.449748 Adding net device
10054 11:13:26.353725
10055 11:13:26.353879 done.
10056 11:13:26.353945
10057 11:13:26.354007 MAC: 00:24:32:30:78:ff
10058 11:13:26.354068
10059 11:13:26.357050 Sending DHCP discover... done.
10060 11:13:26.357134
10061 11:13:26.360963 Waiting for reply... done.
10062 11:13:26.361047
10063 11:13:26.363696 Sending DHCP request... done.
10064 11:13:26.363791
10065 11:13:26.367815 Waiting for reply... done.
10066 11:13:26.367893
10067 11:13:26.367974 My ip is 192.168.201.21
10068 11:13:26.368052
10069 11:13:26.371220 The DHCP server ip is 192.168.201.1
10070 11:13:26.371324
10071 11:13:26.377747 TFTP server IP predefined by user: 192.168.201.1
10072 11:13:26.377826
10073 11:13:26.384344 Bootfile predefined by user: 10591235/tftp-deploy-qhjhjj89/kernel/image.itb
10074 11:13:26.384428
10075 11:13:26.387873 Sending tftp read request... done.
10076 11:13:26.387952
10077 11:13:26.391321 Waiting for the transfer...
10078 11:13:26.391406
10079 11:13:26.943763 00000000 ################################################################
10080 11:13:26.943914
10081 11:13:27.550247 00080000 ################################################################
10082 11:13:27.550711
10083 11:13:28.193005 00100000 ################################################################
10084 11:13:28.193156
10085 11:13:28.821411 00180000 ################################################################
10086 11:13:28.821917
10087 11:13:29.442801 00200000 ################################################################
10088 11:13:29.442991
10089 11:13:30.087986 00280000 ################################################################
10090 11:13:30.088502
10091 11:13:30.720163 00300000 ################################################################
10092 11:13:30.720711
10093 11:13:31.353643 00380000 ################################################################
10094 11:13:31.353794
10095 11:13:31.968440 00400000 ################################################################
10096 11:13:31.968991
10097 11:13:32.658119 00480000 ################################################################
10098 11:13:32.658647
10099 11:13:33.348846 00500000 ################################################################
10100 11:13:33.349348
10101 11:13:34.014083 00580000 ################################################################
10102 11:13:34.014602
10103 11:13:34.616361 00600000 ################################################################
10104 11:13:34.616515
10105 11:13:35.227090 00680000 ################################################################
10106 11:13:35.227688
10107 11:13:35.914753 00700000 ################################################################
10108 11:13:35.914921
10109 11:13:36.585467 00780000 ################################################################
10110 11:13:36.586062
10111 11:13:37.249842 00800000 ################################################################
10112 11:13:37.249980
10113 11:13:37.812823 00880000 ################################################################
10114 11:13:37.812960
10115 11:13:38.401651 00900000 ################################################################
10116 11:13:38.401826
10117 11:13:39.061596 00980000 ################################################################
10118 11:13:39.061733
10119 11:13:39.675710 00a00000 ################################################################
10120 11:13:39.676375
10121 11:13:40.307973 00a80000 ################################################################
10122 11:13:40.308519
10123 11:13:40.902317 00b00000 ################################################################
10124 11:13:40.902452
10125 11:13:41.529663 00b80000 ################################################################
10126 11:13:41.530206
10127 11:13:42.141105 00c00000 ################################################################
10128 11:13:42.141690
10129 11:13:42.756391 00c80000 ################################################################
10130 11:13:42.756552
10131 11:13:43.345641 00d00000 ################################################################
10132 11:13:43.345778
10133 11:13:43.885151 00d80000 ################################################################
10134 11:13:43.885296
10135 11:13:44.441255 00e00000 ################################################################
10136 11:13:44.441417
10137 11:13:45.016031 00e80000 ################################################################
10138 11:13:45.016583
10139 11:13:45.649427 00f00000 ################################################################
10140 11:13:45.650108
10141 11:13:46.317244 00f80000 ################################################################
10142 11:13:46.317983
10143 11:13:46.969975 01000000 ################################################################
10144 11:13:46.970697
10145 11:13:47.570332 01080000 ################################################################
10146 11:13:47.570497
10147 11:13:48.115538 01100000 ################################################################
10148 11:13:48.115677
10149 11:13:48.663468 01180000 ################################################################
10150 11:13:48.663613
10151 11:13:49.209566 01200000 ################################################################
10152 11:13:49.209711
10153 11:13:49.743288 01280000 ################################################################
10154 11:13:49.743435
10155 11:13:50.272821 01300000 ################################################################
10156 11:13:50.273007
10157 11:13:50.820483 01380000 ################################################################
10158 11:13:50.820620
10159 11:13:51.352034 01400000 ################################################################
10160 11:13:51.352175
10161 11:13:51.902178 01480000 ################################################################
10162 11:13:51.902338
10163 11:13:52.433706 01500000 ################################################################
10164 11:13:52.433848
10165 11:13:52.960967 01580000 ################################################################
10166 11:13:52.961198
10167 11:13:53.494425 01600000 ################################################################
10168 11:13:53.494585
10169 11:13:54.041449 01680000 ################################################################
10170 11:13:54.041593
10171 11:13:54.597990 01700000 ################################################################
10172 11:13:54.598137
10173 11:13:55.156420 01780000 ################################################################
10174 11:13:55.156601
10175 11:13:55.697346 01800000 ################################################################
10176 11:13:55.697539
10177 11:13:56.238138 01880000 ################################################################
10178 11:13:56.238280
10179 11:13:56.783470 01900000 ################################################################
10180 11:13:56.783647
10181 11:13:57.367996 01980000 ################################################################
10182 11:13:57.368141
10183 11:13:58.005246 01a00000 ################################################################
10184 11:13:58.005394
10185 11:13:58.648632 01a80000 ################################################################
10186 11:13:58.648794
10187 11:13:59.203468 01b00000 ################################################################
10188 11:13:59.203607
10189 11:13:59.770064 01b80000 ################################################################
10190 11:13:59.770214
10191 11:14:00.340500 01c00000 ################################################################
10192 11:14:00.340635
10193 11:14:00.890202 01c80000 ################################################################
10194 11:14:00.890333
10195 11:14:01.451878 01d00000 ################################################################
10196 11:14:01.452019
10197 11:14:02.022845 01d80000 ################################################################
10198 11:14:02.023001
10199 11:14:02.565992 01e00000 ################################################################
10200 11:14:02.566148
10201 11:14:03.116424 01e80000 ################################################################
10202 11:14:03.116614
10203 11:14:03.645917 01f00000 ################################################################
10204 11:14:03.646099
10205 11:14:04.173299 01f80000 ################################################################
10206 11:14:04.173451
10207 11:14:04.704332 02000000 ################################################################
10208 11:14:04.704525
10209 11:14:05.253658 02080000 ################################################################
10210 11:14:05.253849
10211 11:14:05.852556 02100000 ################################################################
10212 11:14:05.852741
10213 11:14:06.437477 02180000 ################################################################
10214 11:14:06.437669
10215 11:14:06.998780 02200000 ################################################################
10216 11:14:06.999006
10217 11:14:07.593952 02280000 ################################################################
10218 11:14:07.594129
10219 11:14:08.163582 02300000 ################################################################
10220 11:14:08.163762
10221 11:14:08.722308 02380000 ################################################################
10222 11:14:08.722473
10223 11:14:09.338183 02400000 ################################################################
10224 11:14:09.338333
10225 11:14:09.916403 02480000 ################################################################
10226 11:14:09.916568
10227 11:14:10.465061 02500000 ################################################################
10228 11:14:10.465204
10229 11:14:11.018795 02580000 ################################################################
10230 11:14:11.018967
10231 11:14:11.565222 02600000 ################################################################
10232 11:14:11.565362
10233 11:14:12.112718 02680000 ################################################################
10234 11:14:12.112880
10235 11:14:12.655062 02700000 ################################################################
10236 11:14:12.655260
10237 11:14:13.203436 02780000 ################################################################
10238 11:14:13.203611
10239 11:14:13.764221 02800000 ################################################################
10240 11:14:13.764400
10241 11:14:14.334070 02880000 ################################################################
10242 11:14:14.334217
10243 11:14:14.945712 02900000 ################################################################
10244 11:14:14.946346
10245 11:14:15.530619 02980000 ################################################################
10246 11:14:15.530768
10247 11:14:16.082363 02a00000 ################################################################
10248 11:14:16.082510
10249 11:14:16.659940 02a80000 ################################################################
10250 11:14:16.660097
10251 11:14:17.255342 02b00000 ################################################################
10252 11:14:17.255533
10253 11:14:17.828251 02b80000 ################################################################
10254 11:14:17.828394
10255 11:14:18.401283 02c00000 ################################################################
10256 11:14:18.401421
10257 11:14:19.025165 02c80000 ################################################################
10258 11:14:19.025786
10259 11:14:19.653101 02d00000 ################################################################
10260 11:14:19.653272
10261 11:14:20.246967 02d80000 ################################################################
10262 11:14:20.247115
10263 11:14:20.821606 02e00000 ################################################################
10264 11:14:20.821755
10265 11:14:21.383382 02e80000 ################################################################
10266 11:14:21.383530
10267 11:14:21.957617 02f00000 ################################################################
10268 11:14:21.957760
10269 11:14:22.532513 02f80000 ################################################################
10270 11:14:22.532650
10271 11:14:23.103625 03000000 ################################################################
10272 11:14:23.103774
10273 11:14:23.667738 03080000 ################################################################
10274 11:14:23.667893
10275 11:14:24.240659 03100000 ################################################################
10276 11:14:24.240810
10277 11:14:24.820383 03180000 ################################################################
10278 11:14:24.820531
10279 11:14:25.404855 03200000 ################################################################
10280 11:14:25.405006
10281 11:14:25.959504 03280000 ################################################################
10282 11:14:25.959654
10283 11:14:26.493302 03300000 ################################################################
10284 11:14:26.493449
10285 11:14:27.063734 03380000 ################################################################
10286 11:14:27.063880
10287 11:14:27.652015 03400000 ################################################################
10288 11:14:27.652157
10289 11:14:28.214164 03480000 ################################################################
10290 11:14:28.214310
10291 11:14:28.760539 03500000 ################################################################
10292 11:14:28.760687
10293 11:14:29.295970 03580000 ################################################################
10294 11:14:29.296156
10295 11:14:29.847670 03600000 ################################################################
10296 11:14:29.847851
10297 11:14:30.227611 03680000 ############################################ done.
10298 11:14:30.227773
10299 11:14:30.230797 The bootfile was 57505818 bytes long.
10300 11:14:30.230992
10301 11:14:30.234713 Sending tftp read request... done.
10302 11:14:30.234868
10303 11:14:30.234975 Waiting for the transfer...
10304 11:14:30.235070
10305 11:14:30.237760 00000000 # done.
10306 11:14:30.237866
10307 11:14:30.244428 Command line loaded dynamically from TFTP file: 10591235/tftp-deploy-qhjhjj89/kernel/cmdline
10308 11:14:30.244526
10309 11:14:30.256997 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10310 11:14:30.257124
10311 11:14:30.257223 Loading FIT.
10312 11:14:30.257323
10313 11:14:30.260560 Image ramdisk-1 has 47370838 bytes.
10314 11:14:30.260644
10315 11:14:30.263647 Image fdt-1 has 46924 bytes.
10316 11:14:30.263731
10317 11:14:30.267165 Image kernel-1 has 10086024 bytes.
10318 11:14:30.267247
10319 11:14:30.277185 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10320 11:14:30.277295
10321 11:14:30.293573 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10322 11:14:30.293680
10323 11:14:30.300250 Choosing best match conf-1 for compat google,spherion-rev2.
10324 11:14:30.300354
10325 11:14:30.303392 Connected to device vid:did:rid of 1ae0:0028:00
10326 11:14:30.314239
10327 11:14:30.317388 tpm_get_response: command 0x17b, return code 0x0
10328 11:14:30.317525
10329 11:14:30.320495 ec_init: CrosEC protocol v3 supported (256, 248)
10330 11:14:30.325529
10331 11:14:30.328854 tpm_cleanup: add release locality here.
10332 11:14:30.329031
10333 11:14:30.329170 Shutting down all USB controllers.
10334 11:14:30.332365
10335 11:14:30.332696 Removing current net device
10336 11:14:30.332958
10337 11:14:30.339507 Exiting depthcharge with code 4 at timestamp: 99490481
10338 11:14:30.339868
10339 11:14:30.342616 LZMA decompressing kernel-1 to 0x821a6718
10340 11:14:30.342987
10341 11:14:30.345778 LZMA decompressing kernel-1 to 0x40000000
10342 11:14:31.612663
10343 11:14:31.612818 jumping to kernel
10344 11:14:31.613268 end: 2.2.4 bootloader-commands (duration 00:01:11) [common]
10345 11:14:31.613372 start: 2.2.5 auto-login-action (timeout 00:03:14) [common]
10346 11:14:31.613453 Setting prompt string to ['Linux version [0-9]']
10347 11:14:31.613524 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10348 11:14:31.613596 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10349 11:14:31.693636
10350 11:14:31.697327 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10351 11:14:31.700664 start: 2.2.5.1 login-action (timeout 00:03:14) [common]
10352 11:14:31.700760 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10353 11:14:31.700855 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10354 11:14:31.700940 Using line separator: #'\n'#
10355 11:14:31.701004 No login prompt set.
10356 11:14:31.701070 Parsing kernel messages
10357 11:14:31.701128 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10358 11:14:31.701236 [login-action] Waiting for messages, (timeout 00:03:14)
10359 11:14:31.719955 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1609115-arm64-gcc-10-defconfig-arm64-chromebook-dplkv) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 10:57:14 UTC 2023
10360 11:14:31.723121 [ 0.000000] random: crng init done
10361 11:14:31.730250 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10362 11:14:31.733422 [ 0.000000] efi: UEFI not found.
10363 11:14:31.739713 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10364 11:14:31.746451 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10365 11:14:31.756238 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10366 11:14:31.766171 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10367 11:14:31.773096 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10368 11:14:31.779580 [ 0.000000] printk: bootconsole [mtk8250] enabled
10369 11:14:31.785922 [ 0.000000] NUMA: No NUMA configuration found
10370 11:14:31.792804 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10371 11:14:31.796139 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10372 11:14:31.799354 [ 0.000000] Zone ranges:
10373 11:14:31.805585 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10374 11:14:31.808844 [ 0.000000] DMA32 empty
10375 11:14:31.815267 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10376 11:14:31.819153 [ 0.000000] Movable zone start for each node
10377 11:14:31.822287 [ 0.000000] Early memory node ranges
10378 11:14:31.828572 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10379 11:14:31.835613 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10380 11:14:31.842120 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10381 11:14:31.848427 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10382 11:14:31.855432 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10383 11:14:31.861800 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10384 11:14:31.918247 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10385 11:14:31.924973 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10386 11:14:31.931577 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10387 11:14:31.934372 [ 0.000000] psci: probing for conduit method from DT.
10388 11:14:31.940862 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10389 11:14:31.944117 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10390 11:14:31.950541 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10391 11:14:31.954229 [ 0.000000] psci: SMC Calling Convention v1.2
10392 11:14:31.960840 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10393 11:14:31.964063 [ 0.000000] Detected VIPT I-cache on CPU0
10394 11:14:31.970373 [ 0.000000] CPU features: detected: GIC system register CPU interface
10395 11:14:31.977447 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10396 11:14:31.983856 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10397 11:14:31.990211 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10398 11:14:32.000067 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10399 11:14:32.006666 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10400 11:14:32.010407 [ 0.000000] alternatives: applying boot alternatives
10401 11:14:32.017103 [ 0.000000] Fallback order for Node 0: 0
10402 11:14:32.023409 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10403 11:14:32.026678 [ 0.000000] Policy zone: Normal
10404 11:14:32.040107 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10405 11:14:32.050002 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10406 11:14:32.060187 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10407 11:14:32.069914 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10408 11:14:32.076301 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10409 11:14:32.079547 <6>[ 0.000000] software IO TLB: area num 8.
10410 11:14:32.136377 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10411 11:14:32.285639 <6>[ 0.000000] Memory: 7926680K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 426088K reserved, 32768K cma-reserved)
10412 11:14:32.292121 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10413 11:14:32.298525 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10414 11:14:32.301776 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10415 11:14:32.308885 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10416 11:14:32.314943 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10417 11:14:32.318133 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10418 11:14:32.328306 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10419 11:14:32.334778 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10420 11:14:32.341672 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10421 11:14:32.348133 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10422 11:14:32.351714 <6>[ 0.000000] GICv3: 608 SPIs implemented
10423 11:14:32.354810 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10424 11:14:32.360885 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10425 11:14:32.363912 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10426 11:14:32.370591 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10427 11:14:32.384063 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10428 11:14:32.396757 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10429 11:14:32.403829 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10430 11:14:32.412083 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10431 11:14:32.425447 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10432 11:14:32.432006 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10433 11:14:32.438688 <6>[ 0.009175] Console: colour dummy device 80x25
10434 11:14:32.448966 <6>[ 0.013902] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10435 11:14:32.455053 <6>[ 0.024344] pid_max: default: 32768 minimum: 301
10436 11:14:32.458387 <6>[ 0.029247] LSM: Security Framework initializing
10437 11:14:32.465049 <6>[ 0.034216] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10438 11:14:32.475523 <6>[ 0.042030] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10439 11:14:32.484653 <6>[ 0.051459] cblist_init_generic: Setting adjustable number of callback queues.
10440 11:14:32.487836 <6>[ 0.058912] cblist_init_generic: Setting shift to 3 and lim to 1.
10441 11:14:32.494997 <6>[ 0.065249] cblist_init_generic: Setting shift to 3 and lim to 1.
10442 11:14:32.501129 <6>[ 0.071657] rcu: Hierarchical SRCU implementation.
10443 11:14:32.507589 <6>[ 0.076670] rcu: Max phase no-delay instances is 1000.
10444 11:14:32.514216 <6>[ 0.083686] EFI services will not be available.
10445 11:14:32.517348 <6>[ 0.088688] smp: Bringing up secondary CPUs ...
10446 11:14:32.525757 <6>[ 0.093743] Detected VIPT I-cache on CPU1
10447 11:14:32.532237 <6>[ 0.093816] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10448 11:14:32.538605 <6>[ 0.093845] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10449 11:14:32.542116 <6>[ 0.094182] Detected VIPT I-cache on CPU2
10450 11:14:32.548822 <6>[ 0.094237] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10451 11:14:32.558221 <6>[ 0.094255] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10452 11:14:32.561934 <6>[ 0.094512] Detected VIPT I-cache on CPU3
10453 11:14:32.568572 <6>[ 0.094557] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10454 11:14:32.575022 <6>[ 0.094571] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10455 11:14:32.578522 <6>[ 0.094875] CPU features: detected: Spectre-v4
10456 11:14:32.585345 <6>[ 0.094881] CPU features: detected: Spectre-BHB
10457 11:14:32.587861 <6>[ 0.094887] Detected PIPT I-cache on CPU4
10458 11:14:32.594592 <6>[ 0.094945] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10459 11:14:32.601087 <6>[ 0.094961] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10460 11:14:32.608074 <6>[ 0.095257] Detected PIPT I-cache on CPU5
10461 11:14:32.614523 <6>[ 0.095318] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10462 11:14:32.620958 <6>[ 0.095334] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10463 11:14:32.624418 <6>[ 0.095616] Detected PIPT I-cache on CPU6
10464 11:14:32.630744 <6>[ 0.095683] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10465 11:14:32.640512 <6>[ 0.095699] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10466 11:14:32.643987 <6>[ 0.096001] Detected PIPT I-cache on CPU7
10467 11:14:32.650618 <6>[ 0.096065] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10468 11:14:32.657219 <6>[ 0.096082] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10469 11:14:32.660795 <6>[ 0.096129] smp: Brought up 1 node, 8 CPUs
10470 11:14:32.666991 <6>[ 0.237479] SMP: Total of 8 processors activated.
10471 11:14:32.673427 <6>[ 0.242401] CPU features: detected: 32-bit EL0 Support
10472 11:14:32.680427 <6>[ 0.247765] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10473 11:14:32.686768 <6>[ 0.256564] CPU features: detected: Common not Private translations
10474 11:14:32.693130 <6>[ 0.263039] CPU features: detected: CRC32 instructions
10475 11:14:32.699732 <6>[ 0.268391] CPU features: detected: RCpc load-acquire (LDAPR)
10476 11:14:32.703575 <6>[ 0.274350] CPU features: detected: LSE atomic instructions
10477 11:14:32.710133 <6>[ 0.280131] CPU features: detected: Privileged Access Never
10478 11:14:32.716687 <6>[ 0.285947] CPU features: detected: RAS Extension Support
10479 11:14:32.723231 <6>[ 0.291555] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10480 11:14:32.726469 <6>[ 0.298819] CPU: All CPU(s) started at EL2
10481 11:14:32.732787 <6>[ 0.303162] alternatives: applying system-wide alternatives
10482 11:14:32.743256 <6>[ 0.313875] devtmpfs: initialized
10483 11:14:32.759076 <6>[ 0.323049] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10484 11:14:32.765592 <6>[ 0.333014] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10485 11:14:32.768609 <6>[ 0.340638] pinctrl core: initialized pinctrl subsystem
10486 11:14:32.776632 <6>[ 0.347315] DMI not present or invalid.
10487 11:14:32.782965 <6>[ 0.351723] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10488 11:14:32.789358 <6>[ 0.358603] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10489 11:14:32.799889 <6>[ 0.366185] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10490 11:14:32.806139 <6>[ 0.374416] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10491 11:14:32.812563 <6>[ 0.382660] audit: initializing netlink subsys (disabled)
10492 11:14:32.819256 <5>[ 0.388355] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10493 11:14:32.825685 <6>[ 0.389067] thermal_sys: Registered thermal governor 'step_wise'
10494 11:14:32.832759 <6>[ 0.396324] thermal_sys: Registered thermal governor 'power_allocator'
10495 11:14:32.839284 <6>[ 0.402580] cpuidle: using governor menu
10496 11:14:32.842600 <6>[ 0.413543] NET: Registered PF_QIPCRTR protocol family
10497 11:14:32.848954 <6>[ 0.419022] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10498 11:14:32.855381 <6>[ 0.426123] ASID allocator initialised with 32768 entries
10499 11:14:32.861981 <6>[ 0.432706] Serial: AMBA PL011 UART driver
10500 11:14:32.870370 <4>[ 0.441396] Trying to register duplicate clock ID: 134
10501 11:14:32.926598 <6>[ 0.500818] KASLR enabled
10502 11:14:32.940799 <6>[ 0.508536] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10503 11:14:32.947942 <6>[ 0.515549] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10504 11:14:32.954293 <6>[ 0.522039] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10505 11:14:32.961069 <6>[ 0.529046] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10506 11:14:32.967695 <6>[ 0.535535] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10507 11:14:32.974801 <6>[ 0.542540] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10508 11:14:32.980893 <6>[ 0.549029] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10509 11:14:32.987494 <6>[ 0.556033] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10510 11:14:32.990586 <6>[ 0.563524] ACPI: Interpreter disabled.
10511 11:14:32.999291 <6>[ 0.569912] iommu: Default domain type: Translated
10512 11:14:33.005823 <6>[ 0.575052] iommu: DMA domain TLB invalidation policy: strict mode
10513 11:14:33.008905 <5>[ 0.581708] SCSI subsystem initialized
10514 11:14:33.015329 <6>[ 0.585946] usbcore: registered new interface driver usbfs
10515 11:14:33.022047 <6>[ 0.591677] usbcore: registered new interface driver hub
10516 11:14:33.025175 <6>[ 0.597232] usbcore: registered new device driver usb
10517 11:14:33.032750 <6>[ 0.603332] pps_core: LinuxPPS API ver. 1 registered
10518 11:14:33.042584 <6>[ 0.608527] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10519 11:14:33.045772 <6>[ 0.617871] PTP clock support registered
10520 11:14:33.048742 <6>[ 0.622113] EDAC MC: Ver: 3.0.0
10521 11:14:33.056524 <6>[ 0.627289] FPGA manager framework
10522 11:14:33.063013 <6>[ 0.630964] Advanced Linux Sound Architecture Driver Initialized.
10523 11:14:33.066150 <6>[ 0.637740] vgaarb: loaded
10524 11:14:33.072925 <6>[ 0.640897] clocksource: Switched to clocksource arch_sys_counter
10525 11:14:33.075784 <5>[ 0.647348] VFS: Disk quotas dquot_6.6.0
10526 11:14:33.082372 <6>[ 0.651534] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10527 11:14:33.085646 <6>[ 0.658716] pnp: PnP ACPI: disabled
10528 11:14:33.094892 <6>[ 0.665419] NET: Registered PF_INET protocol family
10529 11:14:33.104630 <6>[ 0.671008] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10530 11:14:33.115584 <6>[ 0.683338] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10531 11:14:33.125716 <6>[ 0.692154] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10532 11:14:33.132166 <6>[ 0.700127] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10533 11:14:33.142385 <6>[ 0.708826] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10534 11:14:33.148917 <6>[ 0.718575] TCP: Hash tables configured (established 65536 bind 65536)
10535 11:14:33.155373 <6>[ 0.725439] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10536 11:14:33.164941 <6>[ 0.732637] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10537 11:14:33.171266 <6>[ 0.740341] NET: Registered PF_UNIX/PF_LOCAL protocol family
10538 11:14:33.178187 <6>[ 0.746511] RPC: Registered named UNIX socket transport module.
10539 11:14:33.181272 <6>[ 0.752667] RPC: Registered udp transport module.
10540 11:14:33.188516 <6>[ 0.757601] RPC: Registered tcp transport module.
10541 11:14:33.194977 <6>[ 0.762534] RPC: Registered tcp NFSv4.1 backchannel transport module.
10542 11:14:33.197922 <6>[ 0.769205] PCI: CLS 0 bytes, default 64
10543 11:14:33.201233 <6>[ 0.773566] Unpacking initramfs...
10544 11:14:33.222111 <6>[ 0.789639] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10545 11:14:33.231634 <6>[ 0.798313] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10546 11:14:33.235447 <6>[ 0.807207] kvm [1]: IPA Size Limit: 40 bits
10547 11:14:33.241520 <6>[ 0.811738] kvm [1]: GICv3: no GICV resource entry
10548 11:14:33.245821 <6>[ 0.816762] kvm [1]: disabling GICv2 emulation
10549 11:14:33.252000 <6>[ 0.821452] kvm [1]: GIC system register CPU interface enabled
10550 11:14:33.255215 <6>[ 0.827617] kvm [1]: vgic interrupt IRQ18
10551 11:14:33.261557 <6>[ 0.831996] kvm [1]: VHE mode initialized successfully
10552 11:14:33.268146 <5>[ 0.838388] Initialise system trusted keyrings
10553 11:14:33.274512 <6>[ 0.843145] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10554 11:14:33.282757 <6>[ 0.853398] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10555 11:14:33.289216 <5>[ 0.859759] NFS: Registering the id_resolver key type
10556 11:14:33.292514 <5>[ 0.865075] Key type id_resolver registered
10557 11:14:33.298918 <5>[ 0.869491] Key type id_legacy registered
10558 11:14:33.305923 <6>[ 0.873802] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10559 11:14:33.312608 <6>[ 0.880724] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10560 11:14:33.318651 <6>[ 0.888425] 9p: Installing v9fs 9p2000 file system support
10561 11:14:33.355345 <5>[ 0.926437] Key type asymmetric registered
10562 11:14:33.358701 <5>[ 0.930770] Asymmetric key parser 'x509' registered
10563 11:14:33.368551 <6>[ 0.935925] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10564 11:14:33.371868 <6>[ 0.943539] io scheduler mq-deadline registered
10565 11:14:33.375126 <6>[ 0.948315] io scheduler kyber registered
10566 11:14:33.393714 <6>[ 0.965026] EINJ: ACPI disabled.
10567 11:14:33.425905 <4>[ 0.990369] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10568 11:14:33.435575 <4>[ 1.001001] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10569 11:14:33.451280 <6>[ 1.021718] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10570 11:14:33.458631 <6>[ 1.029741] printk: console [ttyS0] disabled
10571 11:14:33.487135 <6>[ 1.054387] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10572 11:14:33.493495 <6>[ 1.063864] printk: console [ttyS0] enabled
10573 11:14:33.496817 <6>[ 1.063864] printk: console [ttyS0] enabled
10574 11:14:33.503157 <6>[ 1.072757] printk: bootconsole [mtk8250] disabled
10575 11:14:33.506928 <6>[ 1.072757] printk: bootconsole [mtk8250] disabled
10576 11:14:33.513272 <6>[ 1.083785] SuperH (H)SCI(F) driver initialized
10577 11:14:33.516372 <6>[ 1.089056] msm_serial: driver initialized
10578 11:14:33.530645 <6>[ 1.097890] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10579 11:14:33.540016 <6>[ 1.106435] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10580 11:14:33.546718 <6>[ 1.114980] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10581 11:14:33.556775 <6>[ 1.123609] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10582 11:14:33.566816 <6>[ 1.132314] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10583 11:14:33.573276 <6>[ 1.141027] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10584 11:14:33.583647 <6>[ 1.149567] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10585 11:14:33.590209 <6>[ 1.158361] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10586 11:14:33.599469 <6>[ 1.166903] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10587 11:14:33.611737 <6>[ 1.182357] loop: module loaded
10588 11:14:33.617862 <6>[ 1.188342] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10589 11:14:33.640900 <4>[ 1.211717] mtk-pmic-keys: Failed to locate of_node [id: -1]
10590 11:14:33.647220 <6>[ 1.218440] megasas: 07.719.03.00-rc1
10591 11:14:33.656855 <6>[ 1.228006] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10592 11:14:33.665422 <6>[ 1.236283] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10593 11:14:33.681799 <6>[ 1.252845] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10594 11:14:33.742561 <6>[ 1.307057] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10595 11:14:35.214965 <6>[ 2.786603] Freeing initrd memory: 46256K
10596 11:14:35.226161 <6>[ 2.797196] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10597 11:14:35.236945 <6>[ 2.808254] tun: Universal TUN/TAP device driver, 1.6
10598 11:14:35.240185 <6>[ 2.814320] thunder_xcv, ver 1.0
10599 11:14:35.243783 <6>[ 2.817825] thunder_bgx, ver 1.0
10600 11:14:35.246763 <6>[ 2.821319] nicpf, ver 1.0
10601 11:14:35.257260 <6>[ 2.825347] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10602 11:14:35.260721 <6>[ 2.832823] hns3: Copyright (c) 2017 Huawei Corporation.
10603 11:14:35.267582 <6>[ 2.838413] hclge is initializing
10604 11:14:35.270901 <6>[ 2.841994] e1000: Intel(R) PRO/1000 Network Driver
10605 11:14:35.277438 <6>[ 2.847123] e1000: Copyright (c) 1999-2006 Intel Corporation.
10606 11:14:35.281072 <6>[ 2.853139] e1000e: Intel(R) PRO/1000 Network Driver
10607 11:14:35.287228 <6>[ 2.858354] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10608 11:14:35.294262 <6>[ 2.864539] igb: Intel(R) Gigabit Ethernet Network Driver
10609 11:14:35.300325 <6>[ 2.870188] igb: Copyright (c) 2007-2014 Intel Corporation.
10610 11:14:35.306726 <6>[ 2.876024] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10611 11:14:35.313813 <6>[ 2.882541] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10612 11:14:35.317046 <6>[ 2.889006] sky2: driver version 1.30
10613 11:14:35.323480 <6>[ 2.893986] VFIO - User Level meta-driver version: 0.3
10614 11:14:35.330672 <6>[ 2.902162] usbcore: registered new interface driver usb-storage
10615 11:14:35.337191 <6>[ 2.908602] usbcore: registered new device driver onboard-usb-hub
10616 11:14:35.346278 <6>[ 2.917663] mt6397-rtc mt6359-rtc: registered as rtc0
10617 11:14:35.356312 <6>[ 2.923128] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-05T11:14:35 UTC (1685963675)
10618 11:14:35.359965 <6>[ 2.932689] i2c_dev: i2c /dev entries driver
10619 11:14:35.376538 <6>[ 2.944445] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10620 11:14:35.383487 <6>[ 2.954695] sdhci: Secure Digital Host Controller Interface driver
10621 11:14:35.390183 <6>[ 2.961134] sdhci: Copyright(c) Pierre Ossman
10622 11:14:35.397012 <6>[ 2.966552] Synopsys Designware Multimedia Card Interface Driver
10623 11:14:35.400166 <6>[ 2.973155] mmc0: CQHCI version 5.10
10624 11:14:35.406496 <6>[ 2.973707] sdhci-pltfm: SDHCI platform and OF driver helper
10625 11:14:35.413760 <6>[ 2.985028] ledtrig-cpu: registered to indicate activity on CPUs
10626 11:14:35.424779 <6>[ 2.992409] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10627 11:14:35.431055 <6>[ 2.999812] usbcore: registered new interface driver usbhid
10628 11:14:35.434295 <6>[ 3.005641] usbhid: USB HID core driver
10629 11:14:35.440963 <6>[ 3.009893] spi_master spi0: will run message pump with realtime priority
10630 11:14:35.487288 <6>[ 3.051872] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10631 11:14:35.506942 <6>[ 3.067502] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10632 11:14:35.510307 <6>[ 3.081083] mmc0: Command Queue Engine enabled
10633 11:14:35.517267 <6>[ 3.082829] cros-ec-spi spi0.0: Chrome EC device registered
10634 11:14:35.523578 <6>[ 3.085832] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10635 11:14:35.526817 <6>[ 3.099108] mmcblk0: mmc0:0001 DA4128 116 GiB
10636 11:14:35.537281 <6>[ 3.108598] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10637 11:14:35.547533 <6>[ 3.109499] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10638 11:14:35.553747 <6>[ 3.115857] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10639 11:14:35.557079 <6>[ 3.125984] NET: Registered PF_PACKET protocol family
10640 11:14:35.563974 <6>[ 3.129679] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10641 11:14:35.567103 <6>[ 3.134478] 9pnet: Installing 9P2000 support
10642 11:14:35.573714 <6>[ 3.140212] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10643 11:14:35.580242 <5>[ 3.144151] Key type dns_resolver registered
10644 11:14:35.583956 <6>[ 3.155750] registered taskstats version 1
10645 11:14:35.589907 <5>[ 3.160138] Loading compiled-in X.509 certificates
10646 11:14:35.624132 <4>[ 3.188740] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10647 11:14:35.633827 <4>[ 3.199432] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10648 11:14:35.644045 <3>[ 3.212159] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10649 11:14:35.656323 <6>[ 3.227565] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10650 11:14:35.663131 <6>[ 3.234313] xhci-mtk 11200000.usb: xHCI Host Controller
10651 11:14:35.672468 <6>[ 3.239807] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10652 11:14:35.679004 <6>[ 3.247669] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10653 11:14:35.685733 <6>[ 3.257098] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10654 11:14:35.692349 <6>[ 3.263331] xhci-mtk 11200000.usb: xHCI Host Controller
10655 11:14:35.698790 <6>[ 3.268830] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10656 11:14:35.708576 <6>[ 3.276496] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10657 11:14:35.711509 <6>[ 3.284400] hub 1-0:1.0: USB hub found
10658 11:14:35.715296 <6>[ 3.288450] hub 1-0:1.0: 1 port detected
10659 11:14:35.725174 <6>[ 3.292802] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10660 11:14:35.728321 <6>[ 3.301621] hub 2-0:1.0: USB hub found
10661 11:14:35.734761 <6>[ 3.305657] hub 2-0:1.0: 1 port detected
10662 11:14:35.741425 <6>[ 3.312877] mtk-msdc 11f70000.mmc: Got CD GPIO
10663 11:14:35.759126 <6>[ 3.326925] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10664 11:14:35.765354 <6>[ 3.334969] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10665 11:14:35.775715 <4>[ 3.342936] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10666 11:14:35.785268 <6>[ 3.352592] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10667 11:14:35.792143 <6>[ 3.360673] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10668 11:14:35.802002 <6>[ 3.368704] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10669 11:14:35.808249 <6>[ 3.376623] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10670 11:14:35.815209 <6>[ 3.384443] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10671 11:14:35.825636 <6>[ 3.392264] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10672 11:14:35.835031 <6>[ 3.402975] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10673 11:14:35.845184 <6>[ 3.411344] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10674 11:14:35.851965 <6>[ 3.419696] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10675 11:14:35.861652 <6>[ 3.428039] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10676 11:14:35.868321 <6>[ 3.436386] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10677 11:14:35.878164 <6>[ 3.444728] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10678 11:14:35.884204 <6>[ 3.453072] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10679 11:14:35.894469 <6>[ 3.461415] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10680 11:14:35.901130 <6>[ 3.469758] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10681 11:14:35.910808 <6>[ 3.478100] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10682 11:14:35.917737 <6>[ 3.486444] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10683 11:14:35.927545 <6>[ 3.494794] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10684 11:14:35.934140 <6>[ 3.503138] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10685 11:14:35.944427 <6>[ 3.511488] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10686 11:14:35.950721 <6>[ 3.519832] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10687 11:14:35.957688 <6>[ 3.528798] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10688 11:14:35.965555 <6>[ 3.536307] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10689 11:14:35.972717 <6>[ 3.543451] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10690 11:14:35.982734 <6>[ 3.550624] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10691 11:14:35.989262 <6>[ 3.557970] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10692 11:14:35.999517 <6>[ 3.564880] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10693 11:14:36.005863 <6>[ 3.574025] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10694 11:14:36.016024 <6>[ 3.583152] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10695 11:14:36.025619 <6>[ 3.592454] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10696 11:14:36.035652 <6>[ 3.601928] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10697 11:14:36.045632 <6>[ 3.611403] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10698 11:14:36.055317 <6>[ 3.620530] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10699 11:14:36.061706 <6>[ 3.630006] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10700 11:14:36.072158 <6>[ 3.639132] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10701 11:14:36.081856 <6>[ 3.648438] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10702 11:14:36.091773 <6>[ 3.658605] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10703 11:14:36.102914 <6>[ 3.670473] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10704 11:14:36.145383 <6>[ 3.713172] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10705 11:14:36.299473 <6>[ 3.870467] hub 1-1:1.0: USB hub found
10706 11:14:36.303009 <6>[ 3.874953] hub 1-1:1.0: 4 ports detected
10707 11:14:36.425694 <6>[ 3.993192] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10708 11:14:36.450415 <6>[ 4.021544] hub 2-1:1.0: USB hub found
10709 11:14:36.453950 <6>[ 4.025938] hub 2-1:1.0: 3 ports detected
10710 11:14:36.625227 <6>[ 4.193173] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10711 11:14:36.757712 <6>[ 4.329090] hub 1-1.4:1.0: USB hub found
10712 11:14:36.761458 <6>[ 4.333755] hub 1-1.4:1.0: 2 ports detected
10713 11:14:36.841660 <6>[ 4.409285] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10714 11:14:37.057331 <6>[ 4.625177] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10715 11:14:37.249352 <6>[ 4.817145] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10716 11:14:48.377740 <6>[ 15.953723] ALSA device list:
10717 11:14:48.384227 <6>[ 15.956981] No soundcards found.
10718 11:14:48.396397 <6>[ 15.969388] Freeing unused kernel memory: 8384K
10719 11:14:48.399452 <6>[ 15.974318] Run /init as init process
10720 11:14:48.429572 <6>[ 16.002597] NET: Registered PF_INET6 protocol family
10721 11:14:48.436024 <6>[ 16.008908] Segment Routing with IPv6
10722 11:14:48.439887 <6>[ 16.012838] In-situ OAM (IOAM) with IPv6
10723 11:14:48.474205 <30>[ 16.027392] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10724 11:14:48.477392 <30>[ 16.051354] systemd[1]: Detected architecture arm64.
10725 11:14:48.481125
10726 11:14:48.484107 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10727 11:14:48.484314
10728 11:14:48.500733 <30>[ 16.073364] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10729 11:14:48.651458 <30>[ 16.221095] systemd[1]: Queued start job for default target Graphical Interface.
10730 11:14:48.689302 <30>[ 16.262400] systemd[1]: Created slice system-getty.slice.
10731 11:14:48.695625 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10732 11:14:48.712581 <30>[ 16.285728] systemd[1]: Created slice system-modprobe.slice.
10733 11:14:48.719312 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10734 11:14:48.737430 <30>[ 16.310297] systemd[1]: Created slice system-serial\x2dgetty.slice.
10735 11:14:48.747078 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10736 11:15:18.582105 <6>[ 46.161240] vpu: disabling
10737 11:15:18.585194 <6>[ 46.164294] vproc2: disabling
10738 11:15:18.588506 <6>[ 46.167564] vproc1: disabling
10739 11:15:18.591520 <6>[ 46.170823] vaud18: disabling
10740 11:15:18.598140 <6>[ 46.174231] vsram_others: disabling
10741 11:15:18.601805 <6>[ 46.178104] va09: disabling
10742 11:15:18.604912 <6>[ 46.181207] vsram_md: disabling
10743 11:15:18.608100 <6>[ 46.184693] Vgpu: disabling
10745 11:17:45.483180 end: 2.2.5.1 login-action (duration 00:03:14) [common]
10747 11:17:45.483380 auto-login-action failed: 1 of 1 attempts. 'wait for prompt timed out'
10749 11:17:45.483524 end: 2.2.5 auto-login-action (duration 00:03:14) [common]
10751 11:17:45.483693 depthcharge-retry failed: 1 of 1 attempts. 'wait for prompt timed out'
10753 11:17:45.483834 end: 2.2 depthcharge-retry (duration 00:05:00) [common]
10756 11:17:45.484098 end: 2 depthcharge-action (duration 00:05:00) [common]
10758 11:17:45.484301 Cleaning after the job
10759 11:17:45.484384 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591235/tftp-deploy-qhjhjj89/ramdisk
10760 11:17:45.489277 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591235/tftp-deploy-qhjhjj89/kernel
10761 11:17:45.500613 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591235/tftp-deploy-qhjhjj89/dtb
10762 11:17:45.500788 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591235/tftp-deploy-qhjhjj89/modules
10763 11:17:45.506087 start: 4.1 power-off (timeout 00:00:30) [common]
10764 11:17:45.506323 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
10765 11:17:45.582226 >> Command sent successfully.
10766 11:17:45.584716 Returned 0 in 0 seconds
10767 11:17:45.685134 end: 4.1 power-off (duration 00:00:00) [common]
10769 11:17:45.685465 start: 4.2 read-feedback (timeout 00:10:00) [common]
10770 11:17:45.685742 Listened to connection for namespace 'common' for up to 1s
10771 11:17:46.686687 Finalising connection for namespace 'common'
10772 11:17:46.686898 Disconnecting from shell: Finalise
10773 11:17:46.787228 end: 4.2 read-feedback (duration 00:00:01) [common]
10774 11:17:46.787379 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10591235
10775 11:17:46.886433 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10591235
10776 11:17:46.886634 JobError: Your job cannot terminate cleanly.