Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 32
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 25
1 11:18:04.645916 lava-dispatcher, installed at version: 2023.05.1
2 11:18:04.646121 start: 0 validate
3 11:18:04.646253 Start time: 2023-06-05 11:18:04.646245+00:00 (UTC)
4 11:18:04.646379 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:18:04.646506 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-igt%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 11:18:04.931450 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:18:04.932214 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:18:05.211763 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:18:05.212114 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:18:05.500620 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:18:05.500951 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 11:18:05.788468 validate duration: 1.14
14 11:18:05.789524 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 11:18:05.789990 start: 1.1 download-retry (timeout 00:10:00) [common]
16 11:18:05.790388 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 11:18:05.790910 Not decompressing ramdisk as can be used compressed.
18 11:18:05.791299 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-igt/20230527.0/arm64/rootfs.cpio.gz
19 11:18:05.791621 saving as /var/lib/lava/dispatcher/tmp/10591276/tftp-deploy-hycd9pjt/ramdisk/rootfs.cpio.gz
20 11:18:05.791910 total size: 43394293 (41MB)
21 11:18:05.796237 progress 0% (0MB)
22 11:18:05.828745 progress 5% (2MB)
23 11:18:05.843932 progress 10% (4MB)
24 11:18:05.855398 progress 15% (6MB)
25 11:18:05.866199 progress 20% (8MB)
26 11:18:05.877201 progress 25% (10MB)
27 11:18:05.888152 progress 30% (12MB)
28 11:18:05.898973 progress 35% (14MB)
29 11:18:05.909876 progress 40% (16MB)
30 11:18:05.920823 progress 45% (18MB)
31 11:18:05.931913 progress 50% (20MB)
32 11:18:05.943003 progress 55% (22MB)
33 11:18:05.953899 progress 60% (24MB)
34 11:18:05.964816 progress 65% (26MB)
35 11:18:05.976015 progress 70% (29MB)
36 11:18:05.986920 progress 75% (31MB)
37 11:18:05.998201 progress 80% (33MB)
38 11:18:06.009074 progress 85% (35MB)
39 11:18:06.019864 progress 90% (37MB)
40 11:18:06.030664 progress 95% (39MB)
41 11:18:06.041504 progress 100% (41MB)
42 11:18:06.041667 41MB downloaded in 0.25s (165.69MB/s)
43 11:18:06.041821 end: 1.1.1 http-download (duration 00:00:00) [common]
45 11:18:06.042059 end: 1.1 download-retry (duration 00:00:00) [common]
46 11:18:06.042237 start: 1.2 download-retry (timeout 00:10:00) [common]
47 11:18:06.042361 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 11:18:06.042526 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 11:18:06.042612 saving as /var/lib/lava/dispatcher/tmp/10591276/tftp-deploy-hycd9pjt/kernel/Image
50 11:18:06.042674 total size: 45746688 (43MB)
51 11:18:06.042736 No compression specified
52 11:18:06.043888 progress 0% (0MB)
53 11:18:06.055811 progress 5% (2MB)
54 11:18:06.067742 progress 10% (4MB)
55 11:18:06.079672 progress 15% (6MB)
56 11:18:06.091796 progress 20% (8MB)
57 11:18:06.103853 progress 25% (10MB)
58 11:18:06.115588 progress 30% (13MB)
59 11:18:06.127725 progress 35% (15MB)
60 11:18:06.139145 progress 40% (17MB)
61 11:18:06.150754 progress 45% (19MB)
62 11:18:06.162241 progress 50% (21MB)
63 11:18:06.173532 progress 55% (24MB)
64 11:18:06.184984 progress 60% (26MB)
65 11:18:06.196437 progress 65% (28MB)
66 11:18:06.207923 progress 70% (30MB)
67 11:18:06.219317 progress 75% (32MB)
68 11:18:06.230584 progress 80% (34MB)
69 11:18:06.242114 progress 85% (37MB)
70 11:18:06.253614 progress 90% (39MB)
71 11:18:06.264982 progress 95% (41MB)
72 11:18:06.276269 progress 100% (43MB)
73 11:18:06.276391 43MB downloaded in 0.23s (186.67MB/s)
74 11:18:06.276535 end: 1.2.1 http-download (duration 00:00:00) [common]
76 11:18:06.276760 end: 1.2 download-retry (duration 00:00:00) [common]
77 11:18:06.276846 start: 1.3 download-retry (timeout 00:10:00) [common]
78 11:18:06.276934 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 11:18:06.277065 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 11:18:06.277140 saving as /var/lib/lava/dispatcher/tmp/10591276/tftp-deploy-hycd9pjt/dtb/mt8192-asurada-spherion-r0.dtb
81 11:18:06.277202 total size: 46924 (0MB)
82 11:18:06.277262 No compression specified
83 11:18:06.278361 progress 69% (0MB)
84 11:18:06.278630 progress 100% (0MB)
85 11:18:06.278781 0MB downloaded in 0.00s (28.38MB/s)
86 11:18:06.278899 end: 1.3.1 http-download (duration 00:00:00) [common]
88 11:18:06.279114 end: 1.3 download-retry (duration 00:00:00) [common]
89 11:18:06.279198 start: 1.4 download-retry (timeout 00:10:00) [common]
90 11:18:06.279279 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 11:18:06.279426 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 11:18:06.279495 saving as /var/lib/lava/dispatcher/tmp/10591276/tftp-deploy-hycd9pjt/modules/modules.tar
93 11:18:06.279556 total size: 8547328 (8MB)
94 11:18:06.279615 Using unxz to decompress xz
95 11:18:06.283148 progress 0% (0MB)
96 11:18:06.304128 progress 5% (0MB)
97 11:18:06.328572 progress 10% (0MB)
98 11:18:06.354399 progress 15% (1MB)
99 11:18:06.378743 progress 20% (1MB)
100 11:18:06.403927 progress 25% (2MB)
101 11:18:06.428559 progress 30% (2MB)
102 11:18:06.453488 progress 35% (2MB)
103 11:18:06.477719 progress 40% (3MB)
104 11:18:06.502363 progress 45% (3MB)
105 11:18:06.525797 progress 50% (4MB)
106 11:18:06.548549 progress 55% (4MB)
107 11:18:06.573173 progress 60% (4MB)
108 11:18:06.597638 progress 65% (5MB)
109 11:18:06.622299 progress 70% (5MB)
110 11:18:06.648745 progress 75% (6MB)
111 11:18:06.677492 progress 80% (6MB)
112 11:18:06.699585 progress 85% (6MB)
113 11:18:06.724254 progress 90% (7MB)
114 11:18:06.747716 progress 95% (7MB)
115 11:18:06.771009 progress 100% (8MB)
116 11:18:06.776854 8MB downloaded in 0.50s (16.39MB/s)
117 11:18:06.777161 end: 1.4.1 http-download (duration 00:00:00) [common]
119 11:18:06.777456 end: 1.4 download-retry (duration 00:00:00) [common]
120 11:18:06.777577 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 11:18:06.777684 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 11:18:06.777781 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 11:18:06.777888 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 11:18:06.778150 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10591276/lava-overlay-bma4v62d
125 11:18:06.778316 makedir: /var/lib/lava/dispatcher/tmp/10591276/lava-overlay-bma4v62d/lava-10591276/bin
126 11:18:06.778453 makedir: /var/lib/lava/dispatcher/tmp/10591276/lava-overlay-bma4v62d/lava-10591276/tests
127 11:18:06.778563 makedir: /var/lib/lava/dispatcher/tmp/10591276/lava-overlay-bma4v62d/lava-10591276/results
128 11:18:06.778689 Creating /var/lib/lava/dispatcher/tmp/10591276/lava-overlay-bma4v62d/lava-10591276/bin/lava-add-keys
129 11:18:06.778872 Creating /var/lib/lava/dispatcher/tmp/10591276/lava-overlay-bma4v62d/lava-10591276/bin/lava-add-sources
130 11:18:06.779013 Creating /var/lib/lava/dispatcher/tmp/10591276/lava-overlay-bma4v62d/lava-10591276/bin/lava-background-process-start
131 11:18:06.779155 Creating /var/lib/lava/dispatcher/tmp/10591276/lava-overlay-bma4v62d/lava-10591276/bin/lava-background-process-stop
132 11:18:06.779294 Creating /var/lib/lava/dispatcher/tmp/10591276/lava-overlay-bma4v62d/lava-10591276/bin/lava-common-functions
133 11:18:06.779509 Creating /var/lib/lava/dispatcher/tmp/10591276/lava-overlay-bma4v62d/lava-10591276/bin/lava-echo-ipv4
134 11:18:06.779680 Creating /var/lib/lava/dispatcher/tmp/10591276/lava-overlay-bma4v62d/lava-10591276/bin/lava-install-packages
135 11:18:06.779825 Creating /var/lib/lava/dispatcher/tmp/10591276/lava-overlay-bma4v62d/lava-10591276/bin/lava-installed-packages
136 11:18:06.779971 Creating /var/lib/lava/dispatcher/tmp/10591276/lava-overlay-bma4v62d/lava-10591276/bin/lava-os-build
137 11:18:06.780131 Creating /var/lib/lava/dispatcher/tmp/10591276/lava-overlay-bma4v62d/lava-10591276/bin/lava-probe-channel
138 11:18:06.780266 Creating /var/lib/lava/dispatcher/tmp/10591276/lava-overlay-bma4v62d/lava-10591276/bin/lava-probe-ip
139 11:18:06.780400 Creating /var/lib/lava/dispatcher/tmp/10591276/lava-overlay-bma4v62d/lava-10591276/bin/lava-target-ip
140 11:18:06.780538 Creating /var/lib/lava/dispatcher/tmp/10591276/lava-overlay-bma4v62d/lava-10591276/bin/lava-target-mac
141 11:18:06.780697 Creating /var/lib/lava/dispatcher/tmp/10591276/lava-overlay-bma4v62d/lava-10591276/bin/lava-target-storage
142 11:18:06.780840 Creating /var/lib/lava/dispatcher/tmp/10591276/lava-overlay-bma4v62d/lava-10591276/bin/lava-test-case
143 11:18:06.781002 Creating /var/lib/lava/dispatcher/tmp/10591276/lava-overlay-bma4v62d/lava-10591276/bin/lava-test-event
144 11:18:06.781135 Creating /var/lib/lava/dispatcher/tmp/10591276/lava-overlay-bma4v62d/lava-10591276/bin/lava-test-feedback
145 11:18:06.781283 Creating /var/lib/lava/dispatcher/tmp/10591276/lava-overlay-bma4v62d/lava-10591276/bin/lava-test-raise
146 11:18:06.781444 Creating /var/lib/lava/dispatcher/tmp/10591276/lava-overlay-bma4v62d/lava-10591276/bin/lava-test-reference
147 11:18:06.781589 Creating /var/lib/lava/dispatcher/tmp/10591276/lava-overlay-bma4v62d/lava-10591276/bin/lava-test-runner
148 11:18:06.781722 Creating /var/lib/lava/dispatcher/tmp/10591276/lava-overlay-bma4v62d/lava-10591276/bin/lava-test-set
149 11:18:06.781861 Creating /var/lib/lava/dispatcher/tmp/10591276/lava-overlay-bma4v62d/lava-10591276/bin/lava-test-shell
150 11:18:06.782025 Updating /var/lib/lava/dispatcher/tmp/10591276/lava-overlay-bma4v62d/lava-10591276/bin/lava-install-packages (oe)
151 11:18:06.782198 Updating /var/lib/lava/dispatcher/tmp/10591276/lava-overlay-bma4v62d/lava-10591276/bin/lava-installed-packages (oe)
152 11:18:06.782356 Creating /var/lib/lava/dispatcher/tmp/10591276/lava-overlay-bma4v62d/lava-10591276/environment
153 11:18:06.782466 LAVA metadata
154 11:18:06.782547 - LAVA_JOB_ID=10591276
155 11:18:06.782648 - LAVA_DISPATCHER_IP=192.168.201.1
156 11:18:06.782798 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 11:18:06.782894 skipped lava-vland-overlay
158 11:18:06.782992 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 11:18:06.783114 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 11:18:06.783210 skipped lava-multinode-overlay
161 11:18:06.783328 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 11:18:06.783478 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 11:18:06.783589 Loading test definitions
164 11:18:06.783710 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 11:18:06.783794 Using /lava-10591276 at stage 0
166 11:18:06.784219 uuid=10591276_1.5.2.3.1 testdef=None
167 11:18:06.784341 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 11:18:06.784465 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 11:18:06.785180 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 11:18:06.785459 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 11:18:06.786331 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 11:18:06.786611 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 11:18:06.787409 runner path: /var/lib/lava/dispatcher/tmp/10591276/lava-overlay-bma4v62d/lava-10591276/0/tests/0_igt-gpu-panfrost test_uuid 10591276_1.5.2.3.1
176 11:18:06.787576 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 11:18:06.787928 Creating lava-test-runner.conf files
179 11:18:06.788010 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10591276/lava-overlay-bma4v62d/lava-10591276/0 for stage 0
180 11:18:06.788122 - 0_igt-gpu-panfrost
181 11:18:06.788258 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 11:18:06.788354 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 11:18:06.795265 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 11:18:06.795425 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 11:18:06.795535 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 11:18:06.795644 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 11:18:06.795761 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 11:18:08.116773 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 11:18:08.117155 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 11:18:08.117287 extracting modules file /var/lib/lava/dispatcher/tmp/10591276/tftp-deploy-hycd9pjt/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10591276/extract-overlay-ramdisk-ksgf8g0j/ramdisk
191 11:18:08.321720 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 11:18:08.321902 start: 1.5.5 apply-overlay-tftp (timeout 00:09:57) [common]
193 11:18:08.322017 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10591276/compress-overlay-2iiow00q/overlay-1.5.2.4.tar.gz to ramdisk
194 11:18:08.322097 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10591276/compress-overlay-2iiow00q/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10591276/extract-overlay-ramdisk-ksgf8g0j/ramdisk
195 11:18:08.328418 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 11:18:08.328530 start: 1.5.6 configure-preseed-file (timeout 00:09:57) [common]
197 11:18:08.328620 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 11:18:08.328708 start: 1.5.7 compress-ramdisk (timeout 00:09:57) [common]
199 11:18:08.328786 Building ramdisk /var/lib/lava/dispatcher/tmp/10591276/extract-overlay-ramdisk-ksgf8g0j/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10591276/extract-overlay-ramdisk-ksgf8g0j/ramdisk
200 11:18:09.272947 >> 369039 blocks
201 11:18:15.011685 rename /var/lib/lava/dispatcher/tmp/10591276/extract-overlay-ramdisk-ksgf8g0j/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10591276/tftp-deploy-hycd9pjt/ramdisk/ramdisk.cpio.gz
202 11:18:15.012119 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 11:18:15.012261 start: 1.5.8 prepare-kernel (timeout 00:09:51) [common]
204 11:18:15.012374 start: 1.5.8.1 prepare-fit (timeout 00:09:51) [common]
205 11:18:15.012496 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10591276/tftp-deploy-hycd9pjt/kernel/Image'
206 11:18:27.133457 Returned 0 in 12 seconds
207 11:18:27.234082 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10591276/tftp-deploy-hycd9pjt/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10591276/tftp-deploy-hycd9pjt/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10591276/tftp-deploy-hycd9pjt/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10591276/tftp-deploy-hycd9pjt/kernel/image.itb
208 11:18:27.999727 output: FIT description: Kernel Image image with one or more FDT blobs
209 11:18:28.000089 output: Created: Mon Jun 5 12:18:27 2023
210 11:18:28.000189 output: Image 0 (kernel-1)
211 11:18:28.000272 output: Description:
212 11:18:28.000353 output: Created: Mon Jun 5 12:18:27 2023
213 11:18:28.000430 output: Type: Kernel Image
214 11:18:28.000506 output: Compression: lzma compressed
215 11:18:28.000584 output: Data Size: 10086024 Bytes = 9849.63 KiB = 9.62 MiB
216 11:18:28.000678 output: Architecture: AArch64
217 11:18:28.000772 output: OS: Linux
218 11:18:28.000867 output: Load Address: 0x00000000
219 11:18:28.000961 output: Entry Point: 0x00000000
220 11:18:28.001053 output: Hash algo: crc32
221 11:18:28.001143 output: Hash value: eb1cf9b8
222 11:18:28.001233 output: Image 1 (fdt-1)
223 11:18:28.001321 output: Description: mt8192-asurada-spherion-r0
224 11:18:28.001420 output: Created: Mon Jun 5 12:18:27 2023
225 11:18:28.001510 output: Type: Flat Device Tree
226 11:18:28.001599 output: Compression: uncompressed
227 11:18:28.001687 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
228 11:18:28.001776 output: Architecture: AArch64
229 11:18:28.001864 output: Hash algo: crc32
230 11:18:28.001952 output: Hash value: 1df858fa
231 11:18:28.002041 output: Image 2 (ramdisk-1)
232 11:18:28.002129 output: Description: unavailable
233 11:18:28.002217 output: Created: Mon Jun 5 12:18:27 2023
234 11:18:28.002306 output: Type: RAMDisk Image
235 11:18:28.002394 output: Compression: Unknown Compression
236 11:18:28.002482 output: Data Size: 56369823 Bytes = 55048.66 KiB = 53.76 MiB
237 11:18:28.002571 output: Architecture: AArch64
238 11:18:28.002658 output: OS: Linux
239 11:18:28.002746 output: Load Address: unavailable
240 11:18:28.002834 output: Entry Point: unavailable
241 11:18:28.002922 output: Hash algo: crc32
242 11:18:28.003009 output: Hash value: 76a603d6
243 11:18:28.003097 output: Default Configuration: 'conf-1'
244 11:18:28.003188 output: Configuration 0 (conf-1)
245 11:18:28.003277 output: Description: mt8192-asurada-spherion-r0
246 11:18:28.003418 output: Kernel: kernel-1
247 11:18:28.003520 output: Init Ramdisk: ramdisk-1
248 11:18:28.003607 output: FDT: fdt-1
249 11:18:28.003689 output: Loadables: kernel-1
250 11:18:28.003770 output:
251 11:18:28.003994 end: 1.5.8.1 prepare-fit (duration 00:00:13) [common]
252 11:18:28.004118 end: 1.5.8 prepare-kernel (duration 00:00:13) [common]
253 11:18:28.004251 end: 1.5 prepare-tftp-overlay (duration 00:00:21) [common]
254 11:18:28.004367 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:38) [common]
255 11:18:28.004472 No LXC device requested
256 11:18:28.004577 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 11:18:28.004691 start: 1.7 deploy-device-env (timeout 00:09:38) [common]
258 11:18:28.004794 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 11:18:28.004890 Checking files for TFTP limit of 4294967296 bytes.
260 11:18:28.005522 end: 1 tftp-deploy (duration 00:00:22) [common]
261 11:18:28.005647 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 11:18:28.005762 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 11:18:28.005918 substitutions:
264 11:18:28.006010 - {DTB}: 10591276/tftp-deploy-hycd9pjt/dtb/mt8192-asurada-spherion-r0.dtb
265 11:18:28.006101 - {INITRD}: 10591276/tftp-deploy-hycd9pjt/ramdisk/ramdisk.cpio.gz
266 11:18:28.006187 - {KERNEL}: 10591276/tftp-deploy-hycd9pjt/kernel/Image
267 11:18:28.006271 - {LAVA_MAC}: None
268 11:18:28.006354 - {PRESEED_CONFIG}: None
269 11:18:28.006437 - {PRESEED_LOCAL}: None
270 11:18:28.006519 - {RAMDISK}: 10591276/tftp-deploy-hycd9pjt/ramdisk/ramdisk.cpio.gz
271 11:18:28.006601 - {ROOT_PART}: None
272 11:18:28.006683 - {ROOT}: None
273 11:18:28.006764 - {SERVER_IP}: 192.168.201.1
274 11:18:28.006845 - {TEE}: None
275 11:18:28.006926 Parsed boot commands:
276 11:18:28.007006 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 11:18:28.007211 Parsed boot commands: tftpboot 192.168.201.1 10591276/tftp-deploy-hycd9pjt/kernel/image.itb 10591276/tftp-deploy-hycd9pjt/kernel/cmdline
278 11:18:28.007325 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 11:18:28.007483 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 11:18:28.007604 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 11:18:28.007719 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 11:18:28.007815 Not connected, no need to disconnect.
283 11:18:28.007915 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 11:18:28.008021 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 11:18:28.008116 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-3'
286 11:18:28.011771 Setting prompt string to ['lava-test: # ']
287 11:18:28.012145 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 11:18:28.012293 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 11:18:28.012454 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 11:18:28.012588 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 11:18:28.012870 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=reboot'
292 11:18:33.148277 >> Command sent successfully.
293 11:18:33.150703 Returned 0 in 5 seconds
294 11:18:33.251088 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 11:18:33.251669 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 11:18:33.251768 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 11:18:33.251857 Setting prompt string to 'Starting depthcharge on Spherion...'
299 11:18:33.251925 Changing prompt to 'Starting depthcharge on Spherion...'
300 11:18:33.251995 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 11:18:33.252247 [Enter `^Ec?' for help]
302 11:18:33.424936
303 11:18:33.425090
304 11:18:33.425161 F0: 102B 0000
305 11:18:33.425224
306 11:18:33.425284 F3: 1001 0000 [0200]
307 11:18:33.428379
308 11:18:33.428462 F3: 1001 0000
309 11:18:33.428529
310 11:18:33.428589 F7: 102D 0000
311 11:18:33.428648
312 11:18:33.431616 F1: 0000 0000
313 11:18:33.431699
314 11:18:33.431764 V0: 0000 0000 [0001]
315 11:18:33.431825
316 11:18:33.435247 00: 0007 8000
317 11:18:33.435331
318 11:18:33.435403 01: 0000 0000
319 11:18:33.435466
320 11:18:33.438218 BP: 0C00 0209 [0000]
321 11:18:33.438301
322 11:18:33.438366 G0: 1182 0000
323 11:18:33.438427
324 11:18:33.441714 EC: 0000 0021 [4000]
325 11:18:33.441800
326 11:18:33.441865 S7: 0000 0000 [0000]
327 11:18:33.441926
328 11:18:33.444713 CC: 0000 0000 [0001]
329 11:18:33.444796
330 11:18:33.444861 T0: 0000 0040 [010F]
331 11:18:33.444921
332 11:18:33.448159 Jump to BL
333 11:18:33.448263
334 11:18:33.471843
335 11:18:33.471926
336 11:18:33.471992
337 11:18:33.479631 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 11:18:33.482940 ARM64: Exception handlers installed.
339 11:18:33.486607 ARM64: Testing exception
340 11:18:33.490272 ARM64: Done test exception
341 11:18:33.496534 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 11:18:33.506963 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 11:18:33.513764 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 11:18:33.523672 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 11:18:33.530358 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 11:18:33.537132 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 11:18:33.548516 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 11:18:33.556021 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 11:18:33.574732 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 11:18:33.578208 WDT: Last reset was cold boot
351 11:18:33.581291 SPI1(PAD0) initialized at 2873684 Hz
352 11:18:33.585058 SPI5(PAD0) initialized at 992727 Hz
353 11:18:33.588258 VBOOT: Loading verstage.
354 11:18:33.594642 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 11:18:33.597885 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 11:18:33.601518 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 11:18:33.604629 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 11:18:33.612289 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 11:18:33.618584 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 11:18:33.629924 read SPI 0x96554 0xa1eb: 4595 us, 9020 KB/s, 72.160 Mbps
361 11:18:33.630009
362 11:18:33.630074
363 11:18:33.639544 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 11:18:33.642775 ARM64: Exception handlers installed.
365 11:18:33.646600 ARM64: Testing exception
366 11:18:33.646681 ARM64: Done test exception
367 11:18:33.653178 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 11:18:33.656276 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 11:18:33.670721 Probing TPM: . done!
370 11:18:33.670817 TPM ready after 0 ms
371 11:18:33.678086 Connected to device vid:did:rid of 1ae0:0028:00
372 11:18:33.684584 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
373 11:18:33.688524 Initialized TPM device CR50 revision 0
374 11:18:33.755734 tlcl_send_startup: Startup return code is 0
375 11:18:33.755838 TPM: setup succeeded
376 11:18:33.767568 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 11:18:33.775896 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 11:18:33.782940 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 11:18:33.798099 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 11:18:33.801658 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 11:18:33.806471 in-header: 03 07 00 00 08 00 00 00
382 11:18:33.810047 in-data: aa e4 47 04 13 02 00 00
383 11:18:33.813330 Chrome EC: UHEPI supported
384 11:18:33.820562 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 11:18:33.824642 in-header: 03 ad 00 00 08 00 00 00
386 11:18:33.827882 in-data: 00 20 20 08 00 00 00 00
387 11:18:33.827963 Phase 1
388 11:18:33.831891 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 11:18:33.838860 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 11:18:33.842518 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 11:18:33.846294 Recovery requested (1009000e)
392 11:18:33.856202 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 11:18:33.862309 tlcl_extend: response is 0
394 11:18:33.872363 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 11:18:33.878475 tlcl_extend: response is 0
396 11:18:33.885170 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 11:18:33.905326 read SPI 0x210d4 0x2173b: 15146 us, 9046 KB/s, 72.368 Mbps
398 11:18:33.911699 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 11:18:33.911786
400 11:18:33.911852
401 11:18:33.922600 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 11:18:33.926290 ARM64: Exception handlers installed.
403 11:18:33.926380 ARM64: Testing exception
404 11:18:33.929554 ARM64: Done test exception
405 11:18:33.950933 pmic_efuse_setting: Set efuses in 11 msecs
406 11:18:33.954291 pmwrap_interface_init: Select PMIF_VLD_RDY
407 11:18:33.961077 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 11:18:33.964458 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 11:18:33.971242 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 11:18:33.975028 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 11:18:33.979288 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 11:18:33.986312 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 11:18:33.989741 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 11:18:33.993141 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 11:18:33.996872 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 11:18:34.004192 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 11:18:34.008141 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 11:18:34.012159 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 11:18:34.015087 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 11:18:34.022743 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 11:18:34.030298 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 11:18:34.034003 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 11:18:34.041434 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 11:18:34.044923 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 11:18:34.052524 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 11:18:34.056265 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 11:18:34.063391 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 11:18:34.067719 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 11:18:34.074977 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 11:18:34.078496 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 11:18:34.086188 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 11:18:34.089590 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 11:18:34.093572 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 11:18:34.100719 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 11:18:34.104352 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 11:18:34.108357 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 11:18:34.114934 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 11:18:34.119184 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 11:18:34.126451 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 11:18:34.129650 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 11:18:34.133321 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 11:18:34.140617 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 11:18:34.144479 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 11:18:34.151389 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 11:18:34.155245 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 11:18:34.158686 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 11:18:34.162867 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 11:18:34.166718 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 11:18:34.173888 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 11:18:34.177711 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 11:18:34.181007 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 11:18:34.184532 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 11:18:34.188456 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 11:18:34.192217 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 11:18:34.199779 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 11:18:34.203032 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 11:18:34.207183 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 11:18:34.214003 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 11:18:34.221568 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 11:18:34.224882 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 11:18:34.236205 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 11:18:34.243843 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 11:18:34.247165 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 11:18:34.250929 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 11:18:34.254806 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 11:18:34.263833 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
467 11:18:34.270674 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 11:18:34.274194 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 11:18:34.277235 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 11:18:34.287948 [RTC]rtc_get_frequency_meter,154: input=15, output=790
471 11:18:34.297722 [RTC]rtc_get_frequency_meter,154: input=23, output=978
472 11:18:34.307195 [RTC]rtc_get_frequency_meter,154: input=19, output=885
473 11:18:34.316392 [RTC]rtc_get_frequency_meter,154: input=17, output=837
474 11:18:34.326070 [RTC]rtc_get_frequency_meter,154: input=16, output=814
475 11:18:34.335703 [RTC]rtc_get_frequency_meter,154: input=15, output=790
476 11:18:34.345528 [RTC]rtc_get_frequency_meter,154: input=16, output=812
477 11:18:34.348557 [RTC]rtc_eosc_cali,47: left: 15, middle: 15, right: 16
478 11:18:34.356016 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
479 11:18:34.360297 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 11:18:34.363746 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 11:18:34.367043 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 11:18:34.370418 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 11:18:34.374068 ADC[4]: Raw value=901328 ID=7
484 11:18:34.377580 ADC[3]: Raw value=213336 ID=1
485 11:18:34.377665 RAM Code: 0x71
486 11:18:34.382074 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 11:18:34.389019 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 11:18:34.396206 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 11:18:34.403615 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 11:18:34.406977 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 11:18:34.410777 in-header: 03 07 00 00 08 00 00 00
492 11:18:34.414860 in-data: aa e4 47 04 13 02 00 00
493 11:18:34.414947 Chrome EC: UHEPI supported
494 11:18:34.422325 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 11:18:34.426138 in-header: 03 ed 00 00 08 00 00 00
496 11:18:34.429536 in-data: 80 20 60 08 00 00 00 00
497 11:18:34.433101 MRC: failed to locate region type 0.
498 11:18:34.440477 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 11:18:34.440561 DRAM-K: Running full calibration
500 11:18:34.448068 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 11:18:34.451600 header.status = 0x0
502 11:18:34.451683 header.version = 0x6 (expected: 0x6)
503 11:18:34.455223 header.size = 0xd00 (expected: 0xd00)
504 11:18:34.458964 header.flags = 0x0
505 11:18:34.465649 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 11:18:34.482289 read SPI 0x72590 0x1c583: 12502 us, 9286 KB/s, 74.288 Mbps
507 11:18:34.489944 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 11:18:34.493283 dram_init: ddr_geometry: 2
509 11:18:34.493367 [EMI] MDL number = 2
510 11:18:34.496838 [EMI] Get MDL freq = 0
511 11:18:34.496923 dram_init: ddr_type: 0
512 11:18:34.500690 is_discrete_lpddr4: 1
513 11:18:34.504388 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 11:18:34.504472
515 11:18:34.504538
516 11:18:34.507778 [Bian_co] ETT version 0.0.0.1
517 11:18:34.511642 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 11:18:34.511726
519 11:18:34.515485 dramc_set_vcore_voltage set vcore to 650000
520 11:18:34.515570 Read voltage for 800, 4
521 11:18:34.519627 Vio18 = 0
522 11:18:34.519728 Vcore = 650000
523 11:18:34.519795 Vdram = 0
524 11:18:34.522766 Vddq = 0
525 11:18:34.522850 Vmddr = 0
526 11:18:34.522917 dram_init: config_dvfs: 1
527 11:18:34.530355 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 11:18:34.533939 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 11:18:34.537177 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=10
530 11:18:34.540868 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=10
531 11:18:34.544634 [SwImpedanceCal] DRVP=12, DRVN=25, ODTN=9
532 11:18:34.550927 freq_region=1, Reg: DRVP=12, DRVN=25, ODTN=9
533 11:18:34.551011 MEM_TYPE=3, freq_sel=18
534 11:18:34.554202 sv_algorithm_assistance_LP4_1600
535 11:18:34.557588 ============ PULL DRAM RESETB DOWN ============
536 11:18:34.564895 ========== PULL DRAM RESETB DOWN end =========
537 11:18:34.567626 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 11:18:34.571174 ===================================
539 11:18:34.574562 LPDDR4 DRAM CONFIGURATION
540 11:18:34.577796 ===================================
541 11:18:34.577880 EX_ROW_EN[0] = 0x0
542 11:18:34.581234 EX_ROW_EN[1] = 0x0
543 11:18:34.581318 LP4Y_EN = 0x0
544 11:18:34.584517 WORK_FSP = 0x0
545 11:18:34.587621 WL = 0x2
546 11:18:34.587704 RL = 0x2
547 11:18:34.591086 BL = 0x2
548 11:18:34.591170 RPST = 0x0
549 11:18:34.594366 RD_PRE = 0x0
550 11:18:34.594450 WR_PRE = 0x1
551 11:18:34.597868 WR_PST = 0x0
552 11:18:34.597957 DBI_WR = 0x0
553 11:18:34.600985 DBI_RD = 0x0
554 11:18:34.601069 OTF = 0x1
555 11:18:34.604247 ===================================
556 11:18:34.608009 ===================================
557 11:18:34.611484 ANA top config
558 11:18:34.614435 ===================================
559 11:18:34.614519 DLL_ASYNC_EN = 0
560 11:18:34.617459 ALL_SLAVE_EN = 1
561 11:18:34.621152 NEW_RANK_MODE = 1
562 11:18:34.624527 DLL_IDLE_MODE = 1
563 11:18:34.624611 LP45_APHY_COMB_EN = 1
564 11:18:34.627487 TX_ODT_DIS = 1
565 11:18:34.630847 NEW_8X_MODE = 1
566 11:18:34.634155 ===================================
567 11:18:34.637613 ===================================
568 11:18:34.640770 data_rate = 1600
569 11:18:34.644357 CKR = 1
570 11:18:34.647751 DQ_P2S_RATIO = 8
571 11:18:34.647835 ===================================
572 11:18:34.650812 CA_P2S_RATIO = 8
573 11:18:34.654390 DQ_CA_OPEN = 0
574 11:18:34.657749 DQ_SEMI_OPEN = 0
575 11:18:34.660952 CA_SEMI_OPEN = 0
576 11:18:34.664397 CA_FULL_RATE = 0
577 11:18:34.664481 DQ_CKDIV4_EN = 1
578 11:18:34.667956 CA_CKDIV4_EN = 1
579 11:18:34.671021 CA_PREDIV_EN = 0
580 11:18:34.674396 PH8_DLY = 0
581 11:18:34.677949 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 11:18:34.681092 DQ_AAMCK_DIV = 4
583 11:18:34.681176 CA_AAMCK_DIV = 4
584 11:18:34.684375 CA_ADMCK_DIV = 4
585 11:18:34.687714 DQ_TRACK_CA_EN = 0
586 11:18:34.690896 CA_PICK = 800
587 11:18:34.693930 CA_MCKIO = 800
588 11:18:34.698003 MCKIO_SEMI = 0
589 11:18:34.701252 PLL_FREQ = 3068
590 11:18:34.701336 DQ_UI_PI_RATIO = 32
591 11:18:34.704847 CA_UI_PI_RATIO = 0
592 11:18:34.708289 ===================================
593 11:18:34.711655 ===================================
594 11:18:34.715597 memory_type:LPDDR4
595 11:18:34.715699 GP_NUM : 10
596 11:18:34.718891 SRAM_EN : 1
597 11:18:34.718976 MD32_EN : 0
598 11:18:34.722739 ===================================
599 11:18:34.726218 [ANA_INIT] >>>>>>>>>>>>>>
600 11:18:34.729850 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 11:18:34.733804 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 11:18:34.733888 ===================================
603 11:18:34.737148 data_rate = 1600,PCW = 0X7600
604 11:18:34.740570 ===================================
605 11:18:34.744407 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 11:18:34.750531 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 11:18:34.757256 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 11:18:34.760475 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 11:18:34.763732 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 11:18:34.767274 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 11:18:34.770475 [ANA_INIT] flow start
612 11:18:34.770558 [ANA_INIT] PLL >>>>>>>>
613 11:18:34.773931 [ANA_INIT] PLL <<<<<<<<
614 11:18:34.777500 [ANA_INIT] MIDPI >>>>>>>>
615 11:18:34.777583 [ANA_INIT] MIDPI <<<<<<<<
616 11:18:34.780516 [ANA_INIT] DLL >>>>>>>>
617 11:18:34.784094 [ANA_INIT] flow end
618 11:18:34.787188 ============ LP4 DIFF to SE enter ============
619 11:18:34.790873 ============ LP4 DIFF to SE exit ============
620 11:18:34.794357 [ANA_INIT] <<<<<<<<<<<<<
621 11:18:34.797435 [Flow] Enable top DCM control >>>>>
622 11:18:34.800599 [Flow] Enable top DCM control <<<<<
623 11:18:34.804180 Enable DLL master slave shuffle
624 11:18:34.807515 ==============================================================
625 11:18:34.810993 Gating Mode config
626 11:18:34.817163 ==============================================================
627 11:18:34.817246 Config description:
628 11:18:34.827507 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 11:18:34.833988 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 11:18:34.837274 SELPH_MODE 0: By rank 1: By Phase
631 11:18:34.844262 ==============================================================
632 11:18:34.847382 GAT_TRACK_EN = 1
633 11:18:34.850761 RX_GATING_MODE = 2
634 11:18:34.853927 RX_GATING_TRACK_MODE = 2
635 11:18:34.857195 SELPH_MODE = 1
636 11:18:34.860580 PICG_EARLY_EN = 1
637 11:18:34.863744 VALID_LAT_VALUE = 1
638 11:18:34.867806 ==============================================================
639 11:18:34.871313 Enter into Gating configuration >>>>
640 11:18:34.873927 Exit from Gating configuration <<<<
641 11:18:34.877222 Enter into DVFS_PRE_config >>>>>
642 11:18:34.887180 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 11:18:34.890695 Exit from DVFS_PRE_config <<<<<
644 11:18:34.894313 Enter into PICG configuration >>>>
645 11:18:34.897164 Exit from PICG configuration <<<<
646 11:18:34.900608 [RX_INPUT] configuration >>>>>
647 11:18:34.904007 [RX_INPUT] configuration <<<<<
648 11:18:34.910528 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 11:18:34.913999 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 11:18:34.920787 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 11:18:34.928000 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 11:18:34.931622 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 11:18:34.937750 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 11:18:34.941197 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 11:18:34.947603 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 11:18:34.950981 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 11:18:34.954442 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 11:18:34.958209 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 11:18:34.964453 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 11:18:34.968622 ===================================
661 11:18:34.968710 LPDDR4 DRAM CONFIGURATION
662 11:18:34.971314 ===================================
663 11:18:34.974713 EX_ROW_EN[0] = 0x0
664 11:18:34.977653 EX_ROW_EN[1] = 0x0
665 11:18:34.977736 LP4Y_EN = 0x0
666 11:18:34.981055 WORK_FSP = 0x0
667 11:18:34.981138 WL = 0x2
668 11:18:34.984396 RL = 0x2
669 11:18:34.984480 BL = 0x2
670 11:18:34.987978 RPST = 0x0
671 11:18:34.988123 RD_PRE = 0x0
672 11:18:34.991603 WR_PRE = 0x1
673 11:18:34.991711 WR_PST = 0x0
674 11:18:34.994249 DBI_WR = 0x0
675 11:18:34.994324 DBI_RD = 0x0
676 11:18:34.997800 OTF = 0x1
677 11:18:35.001424 ===================================
678 11:18:35.004364 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 11:18:35.007897 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 11:18:35.014932 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 11:18:35.017335 ===================================
682 11:18:35.017445 LPDDR4 DRAM CONFIGURATION
683 11:18:35.021119 ===================================
684 11:18:35.024112 EX_ROW_EN[0] = 0x10
685 11:18:35.027718 EX_ROW_EN[1] = 0x0
686 11:18:35.027829 LP4Y_EN = 0x0
687 11:18:35.030606 WORK_FSP = 0x0
688 11:18:35.030714 WL = 0x2
689 11:18:35.034033 RL = 0x2
690 11:18:35.034119 BL = 0x2
691 11:18:35.037864 RPST = 0x0
692 11:18:35.037947 RD_PRE = 0x0
693 11:18:35.040860 WR_PRE = 0x1
694 11:18:35.040943 WR_PST = 0x0
695 11:18:35.044253 DBI_WR = 0x0
696 11:18:35.044336 DBI_RD = 0x0
697 11:18:35.047651 OTF = 0x1
698 11:18:35.050584 ===================================
699 11:18:35.057252 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 11:18:35.060573 nWR fixed to 40
701 11:18:35.064151 [ModeRegInit_LP4] CH0 RK0
702 11:18:35.064234 [ModeRegInit_LP4] CH0 RK1
703 11:18:35.067197 [ModeRegInit_LP4] CH1 RK0
704 11:18:35.070618 [ModeRegInit_LP4] CH1 RK1
705 11:18:35.070701 match AC timing 13
706 11:18:35.077021 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 11:18:35.080645 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 11:18:35.083978 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 11:18:35.090233 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 11:18:35.093938 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 11:18:35.094021 [EMI DOE] emi_dcm 0
712 11:18:35.100921 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 11:18:35.101007 ==
714 11:18:35.104050 Dram Type= 6, Freq= 0, CH_0, rank 0
715 11:18:35.107323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 11:18:35.107442 ==
717 11:18:35.114084 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 11:18:35.117672 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 11:18:35.127726 [CA 0] Center 37 (7~68) winsize 62
720 11:18:35.130911 [CA 1] Center 37 (6~68) winsize 63
721 11:18:35.134251 [CA 2] Center 35 (5~66) winsize 62
722 11:18:35.137788 [CA 3] Center 34 (4~65) winsize 62
723 11:18:35.141099 [CA 4] Center 34 (3~65) winsize 63
724 11:18:35.144495 [CA 5] Center 33 (3~64) winsize 62
725 11:18:35.144587
726 11:18:35.148206 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 11:18:35.148314
728 11:18:35.151544 [CATrainingPosCal] consider 1 rank data
729 11:18:35.154284 u2DelayCellTimex100 = 270/100 ps
730 11:18:35.157554 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
731 11:18:35.161137 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
732 11:18:35.167817 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
733 11:18:35.171076 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
734 11:18:35.174468 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
735 11:18:35.178147 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 11:18:35.178251
737 11:18:35.181433 CA PerBit enable=1, Macro0, CA PI delay=33
738 11:18:35.181535
739 11:18:35.184392 [CBTSetCACLKResult] CA Dly = 33
740 11:18:35.184477 CS Dly: 5 (0~36)
741 11:18:35.187628 ==
742 11:18:35.187739 Dram Type= 6, Freq= 0, CH_0, rank 1
743 11:18:35.194211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 11:18:35.194322 ==
745 11:18:35.197774 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 11:18:35.204554 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 11:18:35.214212 [CA 0] Center 37 (7~68) winsize 62
748 11:18:35.217565 [CA 1] Center 37 (7~68) winsize 62
749 11:18:35.221099 [CA 2] Center 35 (4~66) winsize 63
750 11:18:35.224089 [CA 3] Center 35 (4~66) winsize 63
751 11:18:35.227166 [CA 4] Center 34 (3~65) winsize 63
752 11:18:35.230939 [CA 5] Center 33 (3~64) winsize 62
753 11:18:35.231023
754 11:18:35.234281 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 11:18:35.234365
756 11:18:35.237182 [CATrainingPosCal] consider 2 rank data
757 11:18:35.240596 u2DelayCellTimex100 = 270/100 ps
758 11:18:35.244145 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 11:18:35.247161 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 11:18:35.254002 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
761 11:18:35.257087 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
762 11:18:35.260710 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
763 11:18:35.263666 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 11:18:35.263749
765 11:18:35.267136 CA PerBit enable=1, Macro0, CA PI delay=33
766 11:18:35.267220
767 11:18:35.270502 [CBTSetCACLKResult] CA Dly = 33
768 11:18:35.270585 CS Dly: 6 (0~38)
769 11:18:35.270652
770 11:18:35.273687 ----->DramcWriteLeveling(PI) begin...
771 11:18:35.277430 ==
772 11:18:35.281612 Dram Type= 6, Freq= 0, CH_0, rank 0
773 11:18:35.284343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 11:18:35.284427 ==
775 11:18:35.288468 Write leveling (Byte 0): 31 => 31
776 11:18:35.291507 Write leveling (Byte 1): 32 => 32
777 11:18:35.291590 DramcWriteLeveling(PI) end<-----
778 11:18:35.291655
779 11:18:35.295488 ==
780 11:18:35.295599 Dram Type= 6, Freq= 0, CH_0, rank 0
781 11:18:35.301462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 11:18:35.301547 ==
783 11:18:35.304765 [Gating] SW mode calibration
784 11:18:35.311643 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 11:18:35.315259 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 11:18:35.318722 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 11:18:35.325246 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
788 11:18:35.328706 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
789 11:18:35.332661 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 11:18:35.338865 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 11:18:35.342207 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 11:18:35.345908 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 11:18:35.352004 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 11:18:35.355492 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 11:18:35.358780 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 11:18:35.362445 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 11:18:35.368693 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 11:18:35.372287 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 11:18:35.375964 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 11:18:35.382536 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 11:18:35.385503 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 11:18:35.390237 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 11:18:35.396204 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
804 11:18:35.399305 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
805 11:18:35.402343 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 11:18:35.408890 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 11:18:35.412308 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 11:18:35.415609 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 11:18:35.422595 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 11:18:35.425688 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 11:18:35.429253 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 11:18:35.435601 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 11:18:35.439214 0 9 12 | B1->B0 | 2626 2e2e | 0 1 | (0 0) (1 1)
814 11:18:35.442140 0 9 16 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
815 11:18:35.445963 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 11:18:35.452094 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 11:18:35.455418 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 11:18:35.458786 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 11:18:35.465413 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
820 11:18:35.468927 0 10 8 | B1->B0 | 3333 2f2f | 1 1 | (1 0) (1 0)
821 11:18:35.472802 0 10 12 | B1->B0 | 2d2d 2323 | 0 0 | (1 1) (0 0)
822 11:18:35.479112 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 11:18:35.482133 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 11:18:35.485612 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 11:18:35.492133 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 11:18:35.495712 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 11:18:35.498839 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
828 11:18:35.505507 0 11 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
829 11:18:35.508764 0 11 12 | B1->B0 | 3838 3e3e | 0 0 | (0 0) (0 0)
830 11:18:35.512252 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 11:18:35.519177 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 11:18:35.522499 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 11:18:35.525606 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 11:18:35.532259 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 11:18:35.535773 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
836 11:18:35.539037 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
837 11:18:35.545512 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
838 11:18:35.549151 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 11:18:35.552468 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 11:18:35.555267 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 11:18:35.562038 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 11:18:35.565517 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 11:18:35.569054 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 11:18:35.575891 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 11:18:35.578898 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 11:18:35.582369 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 11:18:35.589213 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 11:18:35.592241 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 11:18:35.595978 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 11:18:35.602345 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 11:18:35.605529 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 11:18:35.609507 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
853 11:18:35.615274 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
854 11:18:35.618292 Total UI for P1: 0, mck2ui 16
855 11:18:35.621707 best dqsien dly found for B0: ( 0, 14, 8)
856 11:18:35.621792 Total UI for P1: 0, mck2ui 16
857 11:18:35.629071 best dqsien dly found for B1: ( 0, 14, 8)
858 11:18:35.632070 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
859 11:18:35.635730 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
860 11:18:35.635814
861 11:18:35.638408 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
862 11:18:35.641975 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
863 11:18:35.645288 [Gating] SW calibration Done
864 11:18:35.645371 ==
865 11:18:35.648489 Dram Type= 6, Freq= 0, CH_0, rank 0
866 11:18:35.651824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 11:18:35.651908 ==
868 11:18:35.655201 RX Vref Scan: 0
869 11:18:35.655285
870 11:18:35.655358 RX Vref 0 -> 0, step: 1
871 11:18:35.655423
872 11:18:35.658363 RX Delay -130 -> 252, step: 16
873 11:18:35.662264 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
874 11:18:35.669023 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
875 11:18:35.672173 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 11:18:35.675330 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 11:18:35.678869 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
878 11:18:35.681950 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
879 11:18:35.688492 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
880 11:18:35.691647 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
881 11:18:35.695299 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
882 11:18:35.698541 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
883 11:18:35.701822 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
884 11:18:35.708827 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
885 11:18:35.711672 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
886 11:18:35.715193 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
887 11:18:35.718360 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
888 11:18:35.721642 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
889 11:18:35.724815 ==
890 11:18:35.728522 Dram Type= 6, Freq= 0, CH_0, rank 0
891 11:18:35.731481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 11:18:35.731565 ==
893 11:18:35.731631 DQS Delay:
894 11:18:35.735477 DQS0 = 0, DQS1 = 0
895 11:18:35.735561 DQM Delay:
896 11:18:35.738091 DQM0 = 85, DQM1 = 77
897 11:18:35.738174 DQ Delay:
898 11:18:35.741982 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
899 11:18:35.745383 DQ4 =85, DQ5 =77, DQ6 =93, DQ7 =85
900 11:18:35.748008 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
901 11:18:35.751779 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =85
902 11:18:35.751862
903 11:18:35.751927
904 11:18:35.751986 ==
905 11:18:35.755120 Dram Type= 6, Freq= 0, CH_0, rank 0
906 11:18:35.758200 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 11:18:35.758284 ==
908 11:18:35.758349
909 11:18:35.758408
910 11:18:35.761436 TX Vref Scan disable
911 11:18:35.764881 == TX Byte 0 ==
912 11:18:35.768297 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
913 11:18:35.771343 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
914 11:18:35.774694 == TX Byte 1 ==
915 11:18:35.778680 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
916 11:18:35.781439 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
917 11:18:35.781523 ==
918 11:18:35.784732 Dram Type= 6, Freq= 0, CH_0, rank 0
919 11:18:35.788039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 11:18:35.791538 ==
921 11:18:35.802888 TX Vref=22, minBit 5, minWin=27, winSum=443
922 11:18:35.806198 TX Vref=24, minBit 7, minWin=27, winSum=446
923 11:18:35.809521 TX Vref=26, minBit 7, minWin=27, winSum=447
924 11:18:35.812776 TX Vref=28, minBit 5, minWin=27, winSum=455
925 11:18:35.816056 TX Vref=30, minBit 1, minWin=28, winSum=455
926 11:18:35.819469 TX Vref=32, minBit 2, minWin=28, winSum=458
927 11:18:35.825739 [TxChooseVref] Worse bit 2, Min win 28, Win sum 458, Final Vref 32
928 11:18:35.825824
929 11:18:35.829028 Final TX Range 1 Vref 32
930 11:18:35.829112
931 11:18:35.829178 ==
932 11:18:35.832519 Dram Type= 6, Freq= 0, CH_0, rank 0
933 11:18:35.835994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 11:18:35.836078 ==
935 11:18:35.839158
936 11:18:35.839241
937 11:18:35.839307 TX Vref Scan disable
938 11:18:35.842504 == TX Byte 0 ==
939 11:18:35.846079 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
940 11:18:35.849422 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
941 11:18:35.852699 == TX Byte 1 ==
942 11:18:35.855944 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
943 11:18:35.859688 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
944 11:18:35.862385
945 11:18:35.862467 [DATLAT]
946 11:18:35.862532 Freq=800, CH0 RK0
947 11:18:35.862592
948 11:18:35.865853 DATLAT Default: 0xa
949 11:18:35.865936 0, 0xFFFF, sum = 0
950 11:18:35.869382 1, 0xFFFF, sum = 0
951 11:18:35.869468 2, 0xFFFF, sum = 0
952 11:18:35.872961 3, 0xFFFF, sum = 0
953 11:18:35.873046 4, 0xFFFF, sum = 0
954 11:18:35.875920 5, 0xFFFF, sum = 0
955 11:18:35.876004 6, 0xFFFF, sum = 0
956 11:18:35.879163 7, 0xFFFF, sum = 0
957 11:18:35.879246 8, 0xFFFF, sum = 0
958 11:18:35.882700 9, 0x0, sum = 1
959 11:18:35.882785 10, 0x0, sum = 2
960 11:18:35.886167 11, 0x0, sum = 3
961 11:18:35.886251 12, 0x0, sum = 4
962 11:18:35.889640 best_step = 10
963 11:18:35.889722
964 11:18:35.889786 ==
965 11:18:35.892840 Dram Type= 6, Freq= 0, CH_0, rank 0
966 11:18:35.896220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 11:18:35.896303 ==
968 11:18:35.899623 RX Vref Scan: 1
969 11:18:35.899731
970 11:18:35.899798 Set Vref Range= 32 -> 127
971 11:18:35.899861
972 11:18:35.902499 RX Vref 32 -> 127, step: 1
973 11:18:35.902581
974 11:18:35.905922 RX Delay -95 -> 252, step: 8
975 11:18:35.906005
976 11:18:35.909487 Set Vref, RX VrefLevel [Byte0]: 32
977 11:18:35.912809 [Byte1]: 32
978 11:18:35.912895
979 11:18:35.916158 Set Vref, RX VrefLevel [Byte0]: 33
980 11:18:35.919159 [Byte1]: 33
981 11:18:35.922834
982 11:18:35.922916 Set Vref, RX VrefLevel [Byte0]: 34
983 11:18:35.926223 [Byte1]: 34
984 11:18:35.930516
985 11:18:35.930599 Set Vref, RX VrefLevel [Byte0]: 35
986 11:18:35.934123 [Byte1]: 35
987 11:18:35.938448
988 11:18:35.938530 Set Vref, RX VrefLevel [Byte0]: 36
989 11:18:35.941744 [Byte1]: 36
990 11:18:35.945509
991 11:18:35.945592 Set Vref, RX VrefLevel [Byte0]: 37
992 11:18:35.949662 [Byte1]: 37
993 11:18:35.953957
994 11:18:35.954039 Set Vref, RX VrefLevel [Byte0]: 38
995 11:18:35.957530 [Byte1]: 38
996 11:18:35.960853
997 11:18:35.960935 Set Vref, RX VrefLevel [Byte0]: 39
998 11:18:35.964029 [Byte1]: 39
999 11:18:35.968752
1000 11:18:35.968834 Set Vref, RX VrefLevel [Byte0]: 40
1001 11:18:35.972168 [Byte1]: 40
1002 11:18:35.976381
1003 11:18:35.976463 Set Vref, RX VrefLevel [Byte0]: 41
1004 11:18:35.979713 [Byte1]: 41
1005 11:18:35.983712
1006 11:18:35.983795 Set Vref, RX VrefLevel [Byte0]: 42
1007 11:18:35.987117 [Byte1]: 42
1008 11:18:35.991221
1009 11:18:35.991303 Set Vref, RX VrefLevel [Byte0]: 43
1010 11:18:35.995214 [Byte1]: 43
1011 11:18:35.998883
1012 11:18:35.998965 Set Vref, RX VrefLevel [Byte0]: 44
1013 11:18:36.002143 [Byte1]: 44
1014 11:18:36.006261
1015 11:18:36.006343 Set Vref, RX VrefLevel [Byte0]: 45
1016 11:18:36.010012 [Byte1]: 45
1017 11:18:36.013662
1018 11:18:36.017344 Set Vref, RX VrefLevel [Byte0]: 46
1019 11:18:36.020323 [Byte1]: 46
1020 11:18:36.020406
1021 11:18:36.023636 Set Vref, RX VrefLevel [Byte0]: 47
1022 11:18:36.027491 [Byte1]: 47
1023 11:18:36.027573
1024 11:18:36.030982 Set Vref, RX VrefLevel [Byte0]: 48
1025 11:18:36.033650 [Byte1]: 48
1026 11:18:36.033731
1027 11:18:36.037754 Set Vref, RX VrefLevel [Byte0]: 49
1028 11:18:36.040292 [Byte1]: 49
1029 11:18:36.044589
1030 11:18:36.044670 Set Vref, RX VrefLevel [Byte0]: 50
1031 11:18:36.047934 [Byte1]: 50
1032 11:18:36.051929
1033 11:18:36.052010 Set Vref, RX VrefLevel [Byte0]: 51
1034 11:18:36.055701 [Byte1]: 51
1035 11:18:36.059751
1036 11:18:36.059835 Set Vref, RX VrefLevel [Byte0]: 52
1037 11:18:36.063076 [Byte1]: 52
1038 11:18:36.067268
1039 11:18:36.067355 Set Vref, RX VrefLevel [Byte0]: 53
1040 11:18:36.070360 [Byte1]: 53
1041 11:18:36.074805
1042 11:18:36.074886 Set Vref, RX VrefLevel [Byte0]: 54
1043 11:18:36.078238 [Byte1]: 54
1044 11:18:36.082513
1045 11:18:36.082595 Set Vref, RX VrefLevel [Byte0]: 55
1046 11:18:36.085670 [Byte1]: 55
1047 11:18:36.089977
1048 11:18:36.090058 Set Vref, RX VrefLevel [Byte0]: 56
1049 11:18:36.093217 [Byte1]: 56
1050 11:18:36.097421
1051 11:18:36.097506 Set Vref, RX VrefLevel [Byte0]: 57
1052 11:18:36.101007 [Byte1]: 57
1053 11:18:36.105052
1054 11:18:36.105145 Set Vref, RX VrefLevel [Byte0]: 58
1055 11:18:36.108609 [Byte1]: 58
1056 11:18:36.113013
1057 11:18:36.113093 Set Vref, RX VrefLevel [Byte0]: 59
1058 11:18:36.116317 [Byte1]: 59
1059 11:18:36.120617
1060 11:18:36.120697 Set Vref, RX VrefLevel [Byte0]: 60
1061 11:18:36.123869 [Byte1]: 60
1062 11:18:36.128158
1063 11:18:36.128237 Set Vref, RX VrefLevel [Byte0]: 61
1064 11:18:36.131567 [Byte1]: 61
1065 11:18:36.135555
1066 11:18:36.135635 Set Vref, RX VrefLevel [Byte0]: 62
1067 11:18:36.138605 [Byte1]: 62
1068 11:18:36.143356
1069 11:18:36.143457 Set Vref, RX VrefLevel [Byte0]: 63
1070 11:18:36.150073 [Byte1]: 63
1071 11:18:36.150153
1072 11:18:36.153439 Set Vref, RX VrefLevel [Byte0]: 64
1073 11:18:36.156793 [Byte1]: 64
1074 11:18:36.156874
1075 11:18:36.159808 Set Vref, RX VrefLevel [Byte0]: 65
1076 11:18:36.162789 [Byte1]: 65
1077 11:18:36.162870
1078 11:18:36.166428 Set Vref, RX VrefLevel [Byte0]: 66
1079 11:18:36.169674 [Byte1]: 66
1080 11:18:36.173333
1081 11:18:36.173414 Set Vref, RX VrefLevel [Byte0]: 67
1082 11:18:36.176642 [Byte1]: 67
1083 11:18:36.180844
1084 11:18:36.180924 Set Vref, RX VrefLevel [Byte0]: 68
1085 11:18:36.184360 [Byte1]: 68
1086 11:18:36.188474
1087 11:18:36.188555 Set Vref, RX VrefLevel [Byte0]: 69
1088 11:18:36.192121 [Byte1]: 69
1089 11:18:36.196856
1090 11:18:36.196951 Set Vref, RX VrefLevel [Byte0]: 70
1091 11:18:36.199617 [Byte1]: 70
1092 11:18:36.203959
1093 11:18:36.204041 Set Vref, RX VrefLevel [Byte0]: 71
1094 11:18:36.207281 [Byte1]: 71
1095 11:18:36.211534
1096 11:18:36.211616 Set Vref, RX VrefLevel [Byte0]: 72
1097 11:18:36.214827 [Byte1]: 72
1098 11:18:36.219294
1099 11:18:36.219415 Set Vref, RX VrefLevel [Byte0]: 73
1100 11:18:36.222441 [Byte1]: 73
1101 11:18:36.226598
1102 11:18:36.226684 Set Vref, RX VrefLevel [Byte0]: 74
1103 11:18:36.229854 [Byte1]: 74
1104 11:18:36.234338
1105 11:18:36.234420 Set Vref, RX VrefLevel [Byte0]: 75
1106 11:18:36.237549 [Byte1]: 75
1107 11:18:36.242078
1108 11:18:36.242160 Set Vref, RX VrefLevel [Byte0]: 76
1109 11:18:36.245254 [Byte1]: 76
1110 11:18:36.249571
1111 11:18:36.249653 Set Vref, RX VrefLevel [Byte0]: 77
1112 11:18:36.252552 [Byte1]: 77
1113 11:18:36.257164
1114 11:18:36.257245 Final RX Vref Byte 0 = 62 to rank0
1115 11:18:36.260267 Final RX Vref Byte 1 = 59 to rank0
1116 11:18:36.263786 Final RX Vref Byte 0 = 62 to rank1
1117 11:18:36.266985 Final RX Vref Byte 1 = 59 to rank1==
1118 11:18:36.270654 Dram Type= 6, Freq= 0, CH_0, rank 0
1119 11:18:36.277029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1120 11:18:36.277112 ==
1121 11:18:36.277177 DQS Delay:
1122 11:18:36.277236 DQS0 = 0, DQS1 = 0
1123 11:18:36.280847 DQM Delay:
1124 11:18:36.280929 DQM0 = 87, DQM1 = 78
1125 11:18:36.283989 DQ Delay:
1126 11:18:36.287338 DQ0 =88, DQ1 =92, DQ2 =84, DQ3 =84
1127 11:18:36.287426 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =92
1128 11:18:36.290490 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =76
1129 11:18:36.294379 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =88
1130 11:18:36.297807
1131 11:18:36.297888
1132 11:18:36.303766 [DQSOSCAuto] RK0, (LSB)MR18= 0x250c, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 400 ps
1133 11:18:36.306978 CH0 RK0: MR19=606, MR18=250C
1134 11:18:36.313920 CH0_RK0: MR19=0x606, MR18=0x250C, DQSOSC=400, MR23=63, INC=92, DEC=61
1135 11:18:36.314003
1136 11:18:36.317238 ----->DramcWriteLeveling(PI) begin...
1137 11:18:36.317336 ==
1138 11:18:36.320490 Dram Type= 6, Freq= 0, CH_0, rank 1
1139 11:18:36.323620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1140 11:18:36.323703 ==
1141 11:18:36.327341 Write leveling (Byte 0): 30 => 30
1142 11:18:36.330272 Write leveling (Byte 1): 26 => 26
1143 11:18:36.334183 DramcWriteLeveling(PI) end<-----
1144 11:18:36.334266
1145 11:18:36.334331 ==
1146 11:18:36.337384 Dram Type= 6, Freq= 0, CH_0, rank 1
1147 11:18:36.340316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1148 11:18:36.340399 ==
1149 11:18:36.343770 [Gating] SW mode calibration
1150 11:18:36.350626 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1151 11:18:36.357323 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1152 11:18:36.401282 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1153 11:18:36.401928 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1154 11:18:36.402010 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1155 11:18:36.402275 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 11:18:36.402605 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 11:18:36.402668 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 11:18:36.403123 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 11:18:36.403246 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 11:18:36.403530 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 11:18:36.403664 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 11:18:36.445259 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 11:18:36.445449 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 11:18:36.445563 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 11:18:36.445848 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 11:18:36.446054 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 11:18:36.446206 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 11:18:36.446329 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1169 11:18:36.446429 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1170 11:18:36.446530 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1171 11:18:36.446820 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 11:18:36.457904 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 11:18:36.458009 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 11:18:36.458265 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 11:18:36.462027 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1176 11:18:36.465020 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 11:18:36.471871 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 11:18:36.474580 0 9 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
1179 11:18:36.478083 0 9 12 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
1180 11:18:36.485065 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 11:18:36.487894 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 11:18:36.491309 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1183 11:18:36.498048 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1184 11:18:36.501477 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1185 11:18:36.505644 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (0 0)
1186 11:18:36.511684 0 10 8 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
1187 11:18:36.514719 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
1188 11:18:36.518251 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 11:18:36.521758 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 11:18:36.528061 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1191 11:18:36.532194 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1192 11:18:36.535237 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1193 11:18:36.539226 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1194 11:18:36.546935 0 11 8 | B1->B0 | 2626 4141 | 0 0 | (1 1) (0 0)
1195 11:18:36.549825 0 11 12 | B1->B0 | 3d3d 4646 | 1 0 | (0 0) (0 0)
1196 11:18:36.553151 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 11:18:36.556566 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 11:18:36.563560 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 11:18:36.567072 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1200 11:18:36.570101 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1201 11:18:36.576860 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1202 11:18:36.580139 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1203 11:18:36.583324 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 11:18:36.589926 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 11:18:36.593779 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 11:18:36.596593 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 11:18:36.603542 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 11:18:36.606949 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 11:18:36.610177 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 11:18:36.616830 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 11:18:36.620172 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 11:18:36.623242 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 11:18:36.630688 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 11:18:36.633159 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 11:18:36.636658 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 11:18:36.639956 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 11:18:36.646851 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1218 11:18:36.649799 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1219 11:18:36.653572 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1220 11:18:36.657148 Total UI for P1: 0, mck2ui 16
1221 11:18:36.660036 best dqsien dly found for B0: ( 0, 14, 6)
1222 11:18:36.663684 Total UI for P1: 0, mck2ui 16
1223 11:18:36.666974 best dqsien dly found for B1: ( 0, 14, 10)
1224 11:18:36.670182 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1225 11:18:36.673481 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1226 11:18:36.676511
1227 11:18:36.679778 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1228 11:18:36.683308 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1229 11:18:36.686952 [Gating] SW calibration Done
1230 11:18:36.687054 ==
1231 11:18:36.690096 Dram Type= 6, Freq= 0, CH_0, rank 1
1232 11:18:36.693603 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1233 11:18:36.693687 ==
1234 11:18:36.693769 RX Vref Scan: 0
1235 11:18:36.693847
1236 11:18:36.696938 RX Vref 0 -> 0, step: 1
1237 11:18:36.697020
1238 11:18:36.700137 RX Delay -130 -> 252, step: 16
1239 11:18:36.703121 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1240 11:18:36.706784 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1241 11:18:36.713467 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1242 11:18:36.716550 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1243 11:18:36.719909 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1244 11:18:36.723222 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1245 11:18:36.726699 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1246 11:18:36.733456 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1247 11:18:36.736737 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1248 11:18:36.740062 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1249 11:18:36.743083 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1250 11:18:36.746360 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1251 11:18:36.753294 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
1252 11:18:36.756512 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1253 11:18:36.759932 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1254 11:18:36.763037 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1255 11:18:36.763120 ==
1256 11:18:36.766531 Dram Type= 6, Freq= 0, CH_0, rank 1
1257 11:18:36.773124 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1258 11:18:36.773208 ==
1259 11:18:36.773290 DQS Delay:
1260 11:18:36.773391 DQS0 = 0, DQS1 = 0
1261 11:18:36.776645 DQM Delay:
1262 11:18:36.776728 DQM0 = 84, DQM1 = 76
1263 11:18:36.779984 DQ Delay:
1264 11:18:36.783215 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1265 11:18:36.783323 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =85
1266 11:18:36.786264 DQ8 =69, DQ9 =69, DQ10 =69, DQ11 =69
1267 11:18:36.789628 DQ12 =77, DQ13 =85, DQ14 =85, DQ15 =85
1268 11:18:36.793200
1269 11:18:36.793282
1270 11:18:36.793363 ==
1271 11:18:36.796475 Dram Type= 6, Freq= 0, CH_0, rank 1
1272 11:18:36.799662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1273 11:18:36.799746 ==
1274 11:18:36.799809
1275 11:18:36.799868
1276 11:18:36.802969 TX Vref Scan disable
1277 11:18:36.803049 == TX Byte 0 ==
1278 11:18:36.809980 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1279 11:18:36.813386 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1280 11:18:36.813467 == TX Byte 1 ==
1281 11:18:36.820158 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1282 11:18:36.823479 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1283 11:18:36.823560 ==
1284 11:18:36.826438 Dram Type= 6, Freq= 0, CH_0, rank 1
1285 11:18:36.829954 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1286 11:18:36.830038 ==
1287 11:18:36.844262 TX Vref=22, minBit 9, minWin=26, winSum=436
1288 11:18:36.847329 TX Vref=24, minBit 8, minWin=26, winSum=440
1289 11:18:36.850934 TX Vref=26, minBit 9, minWin=26, winSum=442
1290 11:18:36.853925 TX Vref=28, minBit 2, minWin=27, winSum=444
1291 11:18:36.857563 TX Vref=30, minBit 8, minWin=27, winSum=454
1292 11:18:36.864314 TX Vref=32, minBit 2, minWin=27, winSum=448
1293 11:18:36.867276 [TxChooseVref] Worse bit 8, Min win 27, Win sum 454, Final Vref 30
1294 11:18:36.867379
1295 11:18:36.870890 Final TX Range 1 Vref 30
1296 11:18:36.870970
1297 11:18:36.871032 ==
1298 11:18:36.874199 Dram Type= 6, Freq= 0, CH_0, rank 1
1299 11:18:36.877266 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1300 11:18:36.877347 ==
1301 11:18:36.877410
1302 11:18:36.880580
1303 11:18:36.880662 TX Vref Scan disable
1304 11:18:36.884053 == TX Byte 0 ==
1305 11:18:36.887678 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1306 11:18:36.890486 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1307 11:18:36.894592 == TX Byte 1 ==
1308 11:18:36.897601 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1309 11:18:36.900887 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1310 11:18:36.900967
1311 11:18:36.904220 [DATLAT]
1312 11:18:36.904300 Freq=800, CH0 RK1
1313 11:18:36.904363
1314 11:18:36.907211 DATLAT Default: 0xa
1315 11:18:36.907291 0, 0xFFFF, sum = 0
1316 11:18:36.911039 1, 0xFFFF, sum = 0
1317 11:18:36.911120 2, 0xFFFF, sum = 0
1318 11:18:36.914086 3, 0xFFFF, sum = 0
1319 11:18:36.914168 4, 0xFFFF, sum = 0
1320 11:18:36.917437 5, 0xFFFF, sum = 0
1321 11:18:36.917519 6, 0xFFFF, sum = 0
1322 11:18:36.921362 7, 0xFFFF, sum = 0
1323 11:18:36.921443 8, 0xFFFF, sum = 0
1324 11:18:36.924274 9, 0x0, sum = 1
1325 11:18:36.924356 10, 0x0, sum = 2
1326 11:18:36.927830 11, 0x0, sum = 3
1327 11:18:36.927911 12, 0x0, sum = 4
1328 11:18:36.930773 best_step = 10
1329 11:18:36.930852
1330 11:18:36.930915 ==
1331 11:18:36.934000 Dram Type= 6, Freq= 0, CH_0, rank 1
1332 11:18:36.937314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1333 11:18:36.937395 ==
1334 11:18:36.940641 RX Vref Scan: 0
1335 11:18:36.940721
1336 11:18:36.940783 RX Vref 0 -> 0, step: 1
1337 11:18:36.940842
1338 11:18:36.943937 RX Delay -95 -> 252, step: 8
1339 11:18:36.950822 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1340 11:18:36.954031 iDelay=209, Bit 1, Center 88 (-23 ~ 200) 224
1341 11:18:36.957314 iDelay=209, Bit 2, Center 84 (-31 ~ 200) 232
1342 11:18:36.960458 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1343 11:18:36.964173 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1344 11:18:36.970566 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1345 11:18:36.973743 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1346 11:18:36.977342 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1347 11:18:36.980615 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
1348 11:18:36.983996 iDelay=209, Bit 9, Center 68 (-39 ~ 176) 216
1349 11:18:36.991088 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1350 11:18:36.994424 iDelay=209, Bit 11, Center 68 (-39 ~ 176) 216
1351 11:18:36.997137 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1352 11:18:37.000734 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
1353 11:18:37.003933 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1354 11:18:37.010710 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
1355 11:18:37.010790 ==
1356 11:18:37.013982 Dram Type= 6, Freq= 0, CH_0, rank 1
1357 11:18:37.017305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1358 11:18:37.017386 ==
1359 11:18:37.017449 DQS Delay:
1360 11:18:37.020902 DQS0 = 0, DQS1 = 0
1361 11:18:37.020981 DQM Delay:
1362 11:18:37.024386 DQM0 = 87, DQM1 = 78
1363 11:18:37.024466 DQ Delay:
1364 11:18:37.027397 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1365 11:18:37.030718 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1366 11:18:37.033901 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1367 11:18:37.037169 DQ12 =80, DQ13 =88, DQ14 =88, DQ15 =88
1368 11:18:37.037250
1369 11:18:37.037314
1370 11:18:37.043829 [DQSOSCAuto] RK1, (LSB)MR18= 0x3019, (MSB)MR19= 0x606, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
1371 11:18:37.047690 CH0 RK1: MR19=606, MR18=3019
1372 11:18:37.054122 CH0_RK1: MR19=0x606, MR18=0x3019, DQSOSC=397, MR23=63, INC=93, DEC=62
1373 11:18:37.057218 [RxdqsGatingPostProcess] freq 800
1374 11:18:37.064280 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1375 11:18:37.067208 Pre-setting of DQS Precalculation
1376 11:18:37.070859 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1377 11:18:37.070941 ==
1378 11:18:37.073829 Dram Type= 6, Freq= 0, CH_1, rank 0
1379 11:18:37.077379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1380 11:18:37.077461 ==
1381 11:18:37.083870 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1382 11:18:37.090386 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1383 11:18:37.098711 [CA 0] Center 36 (6~66) winsize 61
1384 11:18:37.102279 [CA 1] Center 36 (6~66) winsize 61
1385 11:18:37.105090 [CA 2] Center 34 (4~64) winsize 61
1386 11:18:37.108832 [CA 3] Center 33 (3~64) winsize 62
1387 11:18:37.111927 [CA 4] Center 34 (4~65) winsize 62
1388 11:18:37.115225 [CA 5] Center 33 (3~64) winsize 62
1389 11:18:37.115356
1390 11:18:37.118540 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1391 11:18:37.118620
1392 11:18:37.122176 [CATrainingPosCal] consider 1 rank data
1393 11:18:37.125291 u2DelayCellTimex100 = 270/100 ps
1394 11:18:37.128685 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1395 11:18:37.135382 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1396 11:18:37.138453 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1397 11:18:37.142011 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
1398 11:18:37.145048 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1399 11:18:37.148673 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1400 11:18:37.148761
1401 11:18:37.151758 CA PerBit enable=1, Macro0, CA PI delay=33
1402 11:18:37.151839
1403 11:18:37.155161 [CBTSetCACLKResult] CA Dly = 33
1404 11:18:37.155242 CS Dly: 5 (0~36)
1405 11:18:37.158879 ==
1406 11:18:37.161857 Dram Type= 6, Freq= 0, CH_1, rank 1
1407 11:18:37.165103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1408 11:18:37.165184 ==
1409 11:18:37.168372 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1410 11:18:37.175115 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1411 11:18:37.184642 [CA 0] Center 36 (6~66) winsize 61
1412 11:18:37.187952 [CA 1] Center 36 (6~66) winsize 61
1413 11:18:37.191318 [CA 2] Center 34 (4~65) winsize 62
1414 11:18:37.194516 [CA 3] Center 34 (4~65) winsize 62
1415 11:18:37.198363 [CA 4] Center 34 (4~65) winsize 62
1416 11:18:37.201927 [CA 5] Center 33 (3~64) winsize 62
1417 11:18:37.202014
1418 11:18:37.205167 [CmdBusTrainingLP45] Vref(ca) range 1: 30
1419 11:18:37.205247
1420 11:18:37.209221 [CATrainingPosCal] consider 2 rank data
1421 11:18:37.213193 u2DelayCellTimex100 = 270/100 ps
1422 11:18:37.216681 CA0 delay=36 (6~66),Diff = 3 PI (21 cell)
1423 11:18:37.220150 CA1 delay=36 (6~66),Diff = 3 PI (21 cell)
1424 11:18:37.224444 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1425 11:18:37.227696 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1426 11:18:37.231734 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1427 11:18:37.234812 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1428 11:18:37.234894
1429 11:18:37.238073 CA PerBit enable=1, Macro0, CA PI delay=33
1430 11:18:37.238154
1431 11:18:37.241565 [CBTSetCACLKResult] CA Dly = 33
1432 11:18:37.241647 CS Dly: 5 (0~36)
1433 11:18:37.241710
1434 11:18:37.244481 ----->DramcWriteLeveling(PI) begin...
1435 11:18:37.247678 ==
1436 11:18:37.251247 Dram Type= 6, Freq= 0, CH_1, rank 0
1437 11:18:37.255029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1438 11:18:37.255111 ==
1439 11:18:37.258200 Write leveling (Byte 0): 28 => 28
1440 11:18:37.261196 Write leveling (Byte 1): 29 => 29
1441 11:18:37.264908 DramcWriteLeveling(PI) end<-----
1442 11:18:37.264988
1443 11:18:37.265052 ==
1444 11:18:37.267989 Dram Type= 6, Freq= 0, CH_1, rank 0
1445 11:18:37.271293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1446 11:18:37.271412 ==
1447 11:18:37.274496 [Gating] SW mode calibration
1448 11:18:37.281272 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1449 11:18:37.284557 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1450 11:18:37.291329 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1451 11:18:37.294706 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1452 11:18:37.298442 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1453 11:18:37.304495 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 11:18:37.307979 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 11:18:37.311806 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 11:18:37.318067 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 11:18:37.321483 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 11:18:37.324775 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 11:18:37.331313 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 11:18:37.335105 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 11:18:37.337886 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 11:18:37.345172 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 11:18:37.348020 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 11:18:37.351629 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 11:18:37.357864 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 11:18:37.361230 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 11:18:37.364665 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1468 11:18:37.371304 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1469 11:18:37.374585 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 11:18:37.378210 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 11:18:37.381746 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 11:18:37.388026 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 11:18:37.391311 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 11:18:37.394389 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 11:18:37.401457 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 11:18:37.404733 0 9 8 | B1->B0 | 2a2a 2a2a | 1 1 | (0 0) (0 0)
1477 11:18:37.407609 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 11:18:37.414426 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 11:18:37.418155 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 11:18:37.421380 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1481 11:18:37.427768 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1482 11:18:37.431052 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1483 11:18:37.434310 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1484 11:18:37.441627 0 10 8 | B1->B0 | 2f2f 3131 | 0 1 | (0 0) (1 0)
1485 11:18:37.444226 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 11:18:37.447945 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 11:18:37.454224 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 11:18:37.457832 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1489 11:18:37.461198 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 11:18:37.468040 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 11:18:37.471389 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 11:18:37.474436 0 11 8 | B1->B0 | 3131 2f2f | 0 0 | (0 0) (0 0)
1493 11:18:37.480894 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 11:18:37.484475 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 11:18:37.488306 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 11:18:37.494564 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 11:18:37.497435 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1498 11:18:37.500714 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1499 11:18:37.504102 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1500 11:18:37.510686 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1501 11:18:37.514805 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1502 11:18:37.517708 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 11:18:37.524116 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 11:18:37.527951 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 11:18:37.530679 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 11:18:37.537603 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 11:18:37.541419 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 11:18:37.544363 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 11:18:37.550751 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 11:18:37.554193 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 11:18:37.557337 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 11:18:37.564299 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 11:18:37.567640 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1514 11:18:37.570735 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1515 11:18:37.577617 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1516 11:18:37.580823 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1517 11:18:37.584237 Total UI for P1: 0, mck2ui 16
1518 11:18:37.587492 best dqsien dly found for B0: ( 0, 14, 6)
1519 11:18:37.591030 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1520 11:18:37.594036 Total UI for P1: 0, mck2ui 16
1521 11:18:37.597342 best dqsien dly found for B1: ( 0, 14, 8)
1522 11:18:37.600567 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1523 11:18:37.604422 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1524 11:18:37.604504
1525 11:18:37.607388 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1526 11:18:37.610738 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1527 11:18:37.614433 [Gating] SW calibration Done
1528 11:18:37.614514 ==
1529 11:18:37.617586 Dram Type= 6, Freq= 0, CH_1, rank 0
1530 11:18:37.624115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1531 11:18:37.624198 ==
1532 11:18:37.624262 RX Vref Scan: 0
1533 11:18:37.624321
1534 11:18:37.627530 RX Vref 0 -> 0, step: 1
1535 11:18:37.627612
1536 11:18:37.631155 RX Delay -130 -> 252, step: 16
1537 11:18:37.634182 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1538 11:18:37.637423 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1539 11:18:37.640951 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1540 11:18:37.644307 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1541 11:18:37.651138 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1542 11:18:37.654314 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1543 11:18:37.657532 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1544 11:18:37.660940 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1545 11:18:37.664084 iDelay=206, Bit 8, Center 61 (-66 ~ 189) 256
1546 11:18:37.670771 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1547 11:18:37.673850 iDelay=206, Bit 10, Center 69 (-50 ~ 189) 240
1548 11:18:37.677237 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1549 11:18:37.680771 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1550 11:18:37.684357 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1551 11:18:37.690932 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1552 11:18:37.694152 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1553 11:18:37.694234 ==
1554 11:18:37.697170 Dram Type= 6, Freq= 0, CH_1, rank 0
1555 11:18:37.700838 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1556 11:18:37.700921 ==
1557 11:18:37.704228 DQS Delay:
1558 11:18:37.704309 DQS0 = 0, DQS1 = 0
1559 11:18:37.707730 DQM Delay:
1560 11:18:37.707811 DQM0 = 83, DQM1 = 76
1561 11:18:37.707875 DQ Delay:
1562 11:18:37.710475 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
1563 11:18:37.714341 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1564 11:18:37.717636 DQ8 =61, DQ9 =69, DQ10 =69, DQ11 =69
1565 11:18:37.720626 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1566 11:18:37.720708
1567 11:18:37.720771
1568 11:18:37.720829 ==
1569 11:18:37.724127 Dram Type= 6, Freq= 0, CH_1, rank 0
1570 11:18:37.730811 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1571 11:18:37.730893 ==
1572 11:18:37.730957
1573 11:18:37.731015
1574 11:18:37.731072 TX Vref Scan disable
1575 11:18:37.734176 == TX Byte 0 ==
1576 11:18:37.737756 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1577 11:18:37.744316 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1578 11:18:37.744398 == TX Byte 1 ==
1579 11:18:37.747673 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1580 11:18:37.754477 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1581 11:18:37.754559 ==
1582 11:18:37.757445 Dram Type= 6, Freq= 0, CH_1, rank 0
1583 11:18:37.760705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1584 11:18:37.760787 ==
1585 11:18:37.773181 TX Vref=22, minBit 1, minWin=27, winSum=440
1586 11:18:37.776707 TX Vref=24, minBit 4, minWin=27, winSum=442
1587 11:18:37.780199 TX Vref=26, minBit 0, minWin=27, winSum=446
1588 11:18:37.783820 TX Vref=28, minBit 11, minWin=27, winSum=450
1589 11:18:37.787240 TX Vref=30, minBit 0, minWin=28, winSum=455
1590 11:18:37.790679 TX Vref=32, minBit 9, minWin=27, winSum=453
1591 11:18:37.797193 [TxChooseVref] Worse bit 0, Min win 28, Win sum 455, Final Vref 30
1592 11:18:37.797274
1593 11:18:37.800769 Final TX Range 1 Vref 30
1594 11:18:37.800881
1595 11:18:37.800947 ==
1596 11:18:37.803903 Dram Type= 6, Freq= 0, CH_1, rank 0
1597 11:18:37.807260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1598 11:18:37.807405 ==
1599 11:18:37.807472
1600 11:18:37.807533
1601 11:18:37.810419 TX Vref Scan disable
1602 11:18:37.814154 == TX Byte 0 ==
1603 11:18:37.817292 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1604 11:18:37.820810 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1605 11:18:37.823786 == TX Byte 1 ==
1606 11:18:37.827389 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1607 11:18:37.830493 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1608 11:18:37.830574
1609 11:18:37.833782 [DATLAT]
1610 11:18:37.833862 Freq=800, CH1 RK0
1611 11:18:37.833925
1612 11:18:37.837447 DATLAT Default: 0xa
1613 11:18:37.837528 0, 0xFFFF, sum = 0
1614 11:18:37.840481 1, 0xFFFF, sum = 0
1615 11:18:37.840563 2, 0xFFFF, sum = 0
1616 11:18:37.843936 3, 0xFFFF, sum = 0
1617 11:18:37.844018 4, 0xFFFF, sum = 0
1618 11:18:37.847380 5, 0xFFFF, sum = 0
1619 11:18:37.847462 6, 0xFFFF, sum = 0
1620 11:18:37.850326 7, 0xFFFF, sum = 0
1621 11:18:37.850408 8, 0xFFFF, sum = 0
1622 11:18:37.853742 9, 0x0, sum = 1
1623 11:18:37.853825 10, 0x0, sum = 2
1624 11:18:37.856782 11, 0x0, sum = 3
1625 11:18:37.856864 12, 0x0, sum = 4
1626 11:18:37.860305 best_step = 10
1627 11:18:37.860386
1628 11:18:37.860449 ==
1629 11:18:37.863985 Dram Type= 6, Freq= 0, CH_1, rank 0
1630 11:18:37.866796 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1631 11:18:37.866877 ==
1632 11:18:37.870115 RX Vref Scan: 1
1633 11:18:37.870196
1634 11:18:37.870259 Set Vref Range= 32 -> 127
1635 11:18:37.870318
1636 11:18:37.873485 RX Vref 32 -> 127, step: 1
1637 11:18:37.873593
1638 11:18:37.876859 RX Delay -111 -> 252, step: 8
1639 11:18:37.876941
1640 11:18:37.880372 Set Vref, RX VrefLevel [Byte0]: 32
1641 11:18:37.883979 [Byte1]: 32
1642 11:18:37.884060
1643 11:18:37.887144 Set Vref, RX VrefLevel [Byte0]: 33
1644 11:18:37.890055 [Byte1]: 33
1645 11:18:37.893698
1646 11:18:37.893780 Set Vref, RX VrefLevel [Byte0]: 34
1647 11:18:37.896850 [Byte1]: 34
1648 11:18:37.901289
1649 11:18:37.901396 Set Vref, RX VrefLevel [Byte0]: 35
1650 11:18:37.904512 [Byte1]: 35
1651 11:18:37.909572
1652 11:18:37.909653 Set Vref, RX VrefLevel [Byte0]: 36
1653 11:18:37.912541 [Byte1]: 36
1654 11:18:37.916556
1655 11:18:37.916637 Set Vref, RX VrefLevel [Byte0]: 37
1656 11:18:37.920160 [Byte1]: 37
1657 11:18:37.924389
1658 11:18:37.924471 Set Vref, RX VrefLevel [Byte0]: 38
1659 11:18:37.927834 [Byte1]: 38
1660 11:18:37.932385
1661 11:18:37.932466 Set Vref, RX VrefLevel [Byte0]: 39
1662 11:18:37.935382 [Byte1]: 39
1663 11:18:37.939504
1664 11:18:37.939585 Set Vref, RX VrefLevel [Byte0]: 40
1665 11:18:37.943021 [Byte1]: 40
1666 11:18:37.947598
1667 11:18:37.947679 Set Vref, RX VrefLevel [Byte0]: 41
1668 11:18:37.950484 [Byte1]: 41
1669 11:18:37.955192
1670 11:18:37.955273 Set Vref, RX VrefLevel [Byte0]: 42
1671 11:18:37.958322 [Byte1]: 42
1672 11:18:37.962703
1673 11:18:37.962785 Set Vref, RX VrefLevel [Byte0]: 43
1674 11:18:37.966082 [Byte1]: 43
1675 11:18:37.970452
1676 11:18:37.970533 Set Vref, RX VrefLevel [Byte0]: 44
1677 11:18:37.973594 [Byte1]: 44
1678 11:18:37.978084
1679 11:18:37.978165 Set Vref, RX VrefLevel [Byte0]: 45
1680 11:18:37.981092 [Byte1]: 45
1681 11:18:37.985460
1682 11:18:37.985541 Set Vref, RX VrefLevel [Byte0]: 46
1683 11:18:37.989083 [Byte1]: 46
1684 11:18:37.993699
1685 11:18:37.993780 Set Vref, RX VrefLevel [Byte0]: 47
1686 11:18:37.996763 [Byte1]: 47
1687 11:18:38.000943
1688 11:18:38.001025 Set Vref, RX VrefLevel [Byte0]: 48
1689 11:18:38.004033 [Byte1]: 48
1690 11:18:38.008623
1691 11:18:38.008705 Set Vref, RX VrefLevel [Byte0]: 49
1692 11:18:38.011958 [Byte1]: 49
1693 11:18:38.016163
1694 11:18:38.016244 Set Vref, RX VrefLevel [Byte0]: 50
1695 11:18:38.019831 [Byte1]: 50
1696 11:18:38.023828
1697 11:18:38.023910 Set Vref, RX VrefLevel [Byte0]: 51
1698 11:18:38.027041 [Byte1]: 51
1699 11:18:38.031717
1700 11:18:38.031799 Set Vref, RX VrefLevel [Byte0]: 52
1701 11:18:38.034683 [Byte1]: 52
1702 11:18:38.039371
1703 11:18:38.039468 Set Vref, RX VrefLevel [Byte0]: 53
1704 11:18:38.042322 [Byte1]: 53
1705 11:18:38.047076
1706 11:18:38.047158 Set Vref, RX VrefLevel [Byte0]: 54
1707 11:18:38.050182 [Byte1]: 54
1708 11:18:38.054734
1709 11:18:38.054815 Set Vref, RX VrefLevel [Byte0]: 55
1710 11:18:38.058063 [Byte1]: 55
1711 11:18:38.062355
1712 11:18:38.062436 Set Vref, RX VrefLevel [Byte0]: 56
1713 11:18:38.065351 [Byte1]: 56
1714 11:18:38.069567
1715 11:18:38.069649 Set Vref, RX VrefLevel [Byte0]: 57
1716 11:18:38.072901 [Byte1]: 57
1717 11:18:38.077419
1718 11:18:38.077499 Set Vref, RX VrefLevel [Byte0]: 58
1719 11:18:38.080406 [Byte1]: 58
1720 11:18:38.085137
1721 11:18:38.085218 Set Vref, RX VrefLevel [Byte0]: 59
1722 11:18:38.088430 [Byte1]: 59
1723 11:18:38.092735
1724 11:18:38.092816 Set Vref, RX VrefLevel [Byte0]: 60
1725 11:18:38.095814 [Byte1]: 60
1726 11:18:38.100242
1727 11:18:38.100322 Set Vref, RX VrefLevel [Byte0]: 61
1728 11:18:38.103595 [Byte1]: 61
1729 11:18:38.107961
1730 11:18:38.108040 Set Vref, RX VrefLevel [Byte0]: 62
1731 11:18:38.111255 [Byte1]: 62
1732 11:18:38.115551
1733 11:18:38.115654 Set Vref, RX VrefLevel [Byte0]: 63
1734 11:18:38.118768 [Byte1]: 63
1735 11:18:38.123040
1736 11:18:38.123135 Set Vref, RX VrefLevel [Byte0]: 64
1737 11:18:38.126299 [Byte1]: 64
1738 11:18:38.130977
1739 11:18:38.131057 Set Vref, RX VrefLevel [Byte0]: 65
1740 11:18:38.134790 [Byte1]: 65
1741 11:18:38.138425
1742 11:18:38.138504 Set Vref, RX VrefLevel [Byte0]: 66
1743 11:18:38.141825 [Byte1]: 66
1744 11:18:38.146004
1745 11:18:38.146084 Set Vref, RX VrefLevel [Byte0]: 67
1746 11:18:38.149298 [Byte1]: 67
1747 11:18:38.153869
1748 11:18:38.153949 Set Vref, RX VrefLevel [Byte0]: 68
1749 11:18:38.156997 [Byte1]: 68
1750 11:18:38.161463
1751 11:18:38.161596 Set Vref, RX VrefLevel [Byte0]: 69
1752 11:18:38.164820 [Byte1]: 69
1753 11:18:38.169129
1754 11:18:38.169233 Set Vref, RX VrefLevel [Byte0]: 70
1755 11:18:38.172597 [Byte1]: 70
1756 11:18:38.176846
1757 11:18:38.177001 Set Vref, RX VrefLevel [Byte0]: 71
1758 11:18:38.179900 [Byte1]: 71
1759 11:18:38.184571
1760 11:18:38.184666 Set Vref, RX VrefLevel [Byte0]: 72
1761 11:18:38.187557 [Byte1]: 72
1762 11:18:38.191879
1763 11:18:38.191983 Set Vref, RX VrefLevel [Byte0]: 73
1764 11:18:38.195256 [Byte1]: 73
1765 11:18:38.199790
1766 11:18:38.199885 Set Vref, RX VrefLevel [Byte0]: 74
1767 11:18:38.202877 [Byte1]: 74
1768 11:18:38.207503
1769 11:18:38.207583 Set Vref, RX VrefLevel [Byte0]: 75
1770 11:18:38.210828 [Byte1]: 75
1771 11:18:38.214633
1772 11:18:38.214714 Set Vref, RX VrefLevel [Byte0]: 76
1773 11:18:38.218237 [Byte1]: 76
1774 11:18:38.222531
1775 11:18:38.222610 Set Vref, RX VrefLevel [Byte0]: 77
1776 11:18:38.225822 [Byte1]: 77
1777 11:18:38.230406
1778 11:18:38.230487 Set Vref, RX VrefLevel [Byte0]: 78
1779 11:18:38.233399 [Byte1]: 78
1780 11:18:38.237632
1781 11:18:38.237713 Set Vref, RX VrefLevel [Byte0]: 79
1782 11:18:38.241263 [Byte1]: 79
1783 11:18:38.245372
1784 11:18:38.245452 Final RX Vref Byte 0 = 65 to rank0
1785 11:18:38.249103 Final RX Vref Byte 1 = 57 to rank0
1786 11:18:38.252736 Final RX Vref Byte 0 = 65 to rank1
1787 11:18:38.255270 Final RX Vref Byte 1 = 57 to rank1==
1788 11:18:38.258608 Dram Type= 6, Freq= 0, CH_1, rank 0
1789 11:18:38.265416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1790 11:18:38.265498 ==
1791 11:18:38.265562 DQS Delay:
1792 11:18:38.265620 DQS0 = 0, DQS1 = 0
1793 11:18:38.269218 DQM Delay:
1794 11:18:38.269299 DQM0 = 83, DQM1 = 74
1795 11:18:38.272533 DQ Delay:
1796 11:18:38.275469 DQ0 =92, DQ1 =76, DQ2 =72, DQ3 =80
1797 11:18:38.279127 DQ4 =80, DQ5 =96, DQ6 =96, DQ7 =76
1798 11:18:38.279207 DQ8 =60, DQ9 =64, DQ10 =76, DQ11 =68
1799 11:18:38.285463 DQ12 =84, DQ13 =80, DQ14 =84, DQ15 =76
1800 11:18:38.285544
1801 11:18:38.285608
1802 11:18:38.292492 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b01, (MSB)MR19= 0x606, tDQSOscB0 = 409 ps tDQSOscB1 = 398 ps
1803 11:18:38.295777 CH1 RK0: MR19=606, MR18=2B01
1804 11:18:38.302124 CH1_RK0: MR19=0x606, MR18=0x2B01, DQSOSC=398, MR23=63, INC=93, DEC=62
1805 11:18:38.302206
1806 11:18:38.305216 ----->DramcWriteLeveling(PI) begin...
1807 11:18:38.305299 ==
1808 11:18:38.308848 Dram Type= 6, Freq= 0, CH_1, rank 1
1809 11:18:38.312250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1810 11:18:38.312341 ==
1811 11:18:38.315315 Write leveling (Byte 0): 27 => 27
1812 11:18:38.318714 Write leveling (Byte 1): 28 => 28
1813 11:18:38.322044 DramcWriteLeveling(PI) end<-----
1814 11:18:38.322126
1815 11:18:38.322188 ==
1816 11:18:38.325250 Dram Type= 6, Freq= 0, CH_1, rank 1
1817 11:18:38.328617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1818 11:18:38.328699 ==
1819 11:18:38.331843 [Gating] SW mode calibration
1820 11:18:38.338946 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1821 11:18:38.345730 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1822 11:18:38.348986 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1823 11:18:38.351991 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1824 11:18:38.358657 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1825 11:18:38.362144 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 11:18:38.365334 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 11:18:38.372322 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 11:18:38.375294 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 11:18:38.378903 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 11:18:38.385436 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1831 11:18:38.389374 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1832 11:18:38.392298 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1833 11:18:38.395661 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1834 11:18:38.402073 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1835 11:18:38.405475 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1836 11:18:38.409082 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 11:18:38.415622 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 11:18:38.419195 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1839 11:18:38.423032 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1840 11:18:38.429211 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1841 11:18:38.432274 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 11:18:38.435679 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 11:18:38.442464 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 11:18:38.446001 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 11:18:38.449134 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 11:18:38.455833 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 11:18:38.459179 0 9 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
1848 11:18:38.462187 0 9 8 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
1849 11:18:38.469021 0 9 12 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1850 11:18:38.472623 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1851 11:18:38.475456 0 9 20 | B1->B0 | 3535 3434 | 0 1 | (0 0) (1 1)
1852 11:18:38.482247 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1853 11:18:38.485892 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1854 11:18:38.489327 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1855 11:18:38.492494 0 10 4 | B1->B0 | 3131 2a2a | 0 1 | (0 0) (1 0)
1856 11:18:38.498989 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 11:18:38.502726 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 11:18:38.505766 0 10 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1859 11:18:38.512627 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 11:18:38.515635 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 11:18:38.519051 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 11:18:38.525510 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1863 11:18:38.529216 0 11 4 | B1->B0 | 2a2a 3737 | 0 0 | (0 0) (1 1)
1864 11:18:38.532451 0 11 8 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1865 11:18:38.538862 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1866 11:18:38.543214 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1867 11:18:38.545645 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1868 11:18:38.552367 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 11:18:38.556257 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1870 11:18:38.559267 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1871 11:18:38.562564 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1872 11:18:38.569019 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1873 11:18:38.572446 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1874 11:18:38.575834 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1875 11:18:38.582346 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1876 11:18:38.585757 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1877 11:18:38.588938 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1878 11:18:38.595992 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1879 11:18:38.599268 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1880 11:18:38.602877 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1881 11:18:38.609136 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1882 11:18:38.612584 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1883 11:18:38.615922 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1884 11:18:38.622929 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1885 11:18:38.626231 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1886 11:18:38.629292 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1887 11:18:38.635693 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1888 11:18:38.639070 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1889 11:18:38.642887 Total UI for P1: 0, mck2ui 16
1890 11:18:38.645812 best dqsien dly found for B0: ( 0, 14, 6)
1891 11:18:38.649091 Total UI for P1: 0, mck2ui 16
1892 11:18:38.652916 best dqsien dly found for B1: ( 0, 14, 4)
1893 11:18:38.655888 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1894 11:18:38.659641 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1895 11:18:38.659763
1896 11:18:38.662491 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1897 11:18:38.666259 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1898 11:18:38.669532 [Gating] SW calibration Done
1899 11:18:38.669613 ==
1900 11:18:38.672829 Dram Type= 6, Freq= 0, CH_1, rank 1
1901 11:18:38.676085 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1902 11:18:38.676172 ==
1903 11:18:38.679209 RX Vref Scan: 0
1904 11:18:38.679314
1905 11:18:38.679444 RX Vref 0 -> 0, step: 1
1906 11:18:38.682820
1907 11:18:38.682900 RX Delay -130 -> 252, step: 16
1908 11:18:38.689175 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1909 11:18:38.692342 iDelay=206, Bit 1, Center 77 (-34 ~ 189) 224
1910 11:18:38.696203 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1911 11:18:38.699236 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1912 11:18:38.702569 iDelay=206, Bit 4, Center 77 (-34 ~ 189) 224
1913 11:18:38.709179 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1914 11:18:38.712739 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1915 11:18:38.716348 iDelay=206, Bit 7, Center 77 (-34 ~ 189) 224
1916 11:18:38.719235 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1917 11:18:38.722390 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1918 11:18:38.729567 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1919 11:18:38.732474 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1920 11:18:38.735894 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1921 11:18:38.738916 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1922 11:18:38.742728 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1923 11:18:38.749334 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1924 11:18:38.749416 ==
1925 11:18:38.752305 Dram Type= 6, Freq= 0, CH_1, rank 1
1926 11:18:38.755947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1927 11:18:38.756029 ==
1928 11:18:38.756094 DQS Delay:
1929 11:18:38.759230 DQS0 = 0, DQS1 = 0
1930 11:18:38.759337 DQM Delay:
1931 11:18:38.762670 DQM0 = 81, DQM1 = 79
1932 11:18:38.762756 DQ Delay:
1933 11:18:38.765623 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1934 11:18:38.769364 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1935 11:18:38.772402 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1936 11:18:38.775912 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1937 11:18:38.775994
1938 11:18:38.776058
1939 11:18:38.776117 ==
1940 11:18:38.779077 Dram Type= 6, Freq= 0, CH_1, rank 1
1941 11:18:38.782040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1942 11:18:38.782123 ==
1943 11:18:38.782188
1944 11:18:38.785653
1945 11:18:38.785734 TX Vref Scan disable
1946 11:18:38.789414 == TX Byte 0 ==
1947 11:18:38.792270 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1948 11:18:38.795336 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1949 11:18:38.799195 == TX Byte 1 ==
1950 11:18:38.802819 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1951 11:18:38.805628 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1952 11:18:38.805709 ==
1953 11:18:38.808888 Dram Type= 6, Freq= 0, CH_1, rank 1
1954 11:18:38.815499 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1955 11:18:38.815581 ==
1956 11:18:38.827419 TX Vref=22, minBit 1, minWin=27, winSum=438
1957 11:18:38.830551 TX Vref=24, minBit 0, minWin=27, winSum=446
1958 11:18:38.833890 TX Vref=26, minBit 0, minWin=27, winSum=448
1959 11:18:38.837327 TX Vref=28, minBit 0, minWin=28, winSum=453
1960 11:18:38.840421 TX Vref=30, minBit 0, minWin=28, winSum=451
1961 11:18:38.843677 TX Vref=32, minBit 0, minWin=28, winSum=454
1962 11:18:38.851119 [TxChooseVref] Worse bit 0, Min win 28, Win sum 454, Final Vref 32
1963 11:18:38.851201
1964 11:18:38.853941 Final TX Range 1 Vref 32
1965 11:18:38.854024
1966 11:18:38.854088 ==
1967 11:18:38.857598 Dram Type= 6, Freq= 0, CH_1, rank 1
1968 11:18:38.860805 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1969 11:18:38.860919 ==
1970 11:18:38.860987
1971 11:18:38.863701
1972 11:18:38.863782 TX Vref Scan disable
1973 11:18:38.867262 == TX Byte 0 ==
1974 11:18:38.870570 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1975 11:18:38.873897 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1976 11:18:38.877470 == TX Byte 1 ==
1977 11:18:38.880595 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1978 11:18:38.884202 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1979 11:18:38.886877
1980 11:18:38.886958 [DATLAT]
1981 11:18:38.887022 Freq=800, CH1 RK1
1982 11:18:38.887082
1983 11:18:38.890318 DATLAT Default: 0xa
1984 11:18:38.890399 0, 0xFFFF, sum = 0
1985 11:18:38.894176 1, 0xFFFF, sum = 0
1986 11:18:38.894260 2, 0xFFFF, sum = 0
1987 11:18:38.897309 3, 0xFFFF, sum = 0
1988 11:18:38.897392 4, 0xFFFF, sum = 0
1989 11:18:38.900831 5, 0xFFFF, sum = 0
1990 11:18:38.900914 6, 0xFFFF, sum = 0
1991 11:18:38.904244 7, 0xFFFF, sum = 0
1992 11:18:38.907499 8, 0xFFFF, sum = 0
1993 11:18:38.907581 9, 0x0, sum = 1
1994 11:18:38.907647 10, 0x0, sum = 2
1995 11:18:38.910443 11, 0x0, sum = 3
1996 11:18:38.910526 12, 0x0, sum = 4
1997 11:18:38.913762 best_step = 10
1998 11:18:38.913843
1999 11:18:38.913907 ==
2000 11:18:38.917212 Dram Type= 6, Freq= 0, CH_1, rank 1
2001 11:18:38.920429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2002 11:18:38.920511 ==
2003 11:18:38.923650 RX Vref Scan: 0
2004 11:18:38.923732
2005 11:18:38.923795 RX Vref 0 -> 0, step: 1
2006 11:18:38.923855
2007 11:18:38.927136 RX Delay -95 -> 252, step: 8
2008 11:18:38.933708 iDelay=201, Bit 0, Center 84 (-31 ~ 200) 232
2009 11:18:38.937040 iDelay=201, Bit 1, Center 76 (-39 ~ 192) 232
2010 11:18:38.940886 iDelay=201, Bit 2, Center 68 (-47 ~ 184) 232
2011 11:18:38.943602 iDelay=201, Bit 3, Center 80 (-31 ~ 192) 224
2012 11:18:38.947245 iDelay=201, Bit 4, Center 80 (-31 ~ 192) 224
2013 11:18:38.953703 iDelay=201, Bit 5, Center 92 (-15 ~ 200) 216
2014 11:18:38.957204 iDelay=201, Bit 6, Center 88 (-23 ~ 200) 224
2015 11:18:38.960344 iDelay=201, Bit 7, Center 72 (-39 ~ 184) 224
2016 11:18:38.963883 iDelay=201, Bit 8, Center 64 (-55 ~ 184) 240
2017 11:18:38.966839 iDelay=201, Bit 9, Center 64 (-47 ~ 176) 224
2018 11:18:38.973652 iDelay=201, Bit 10, Center 76 (-39 ~ 192) 232
2019 11:18:38.977015 iDelay=201, Bit 11, Center 68 (-47 ~ 184) 232
2020 11:18:38.980496 iDelay=201, Bit 12, Center 80 (-31 ~ 192) 224
2021 11:18:38.983652 iDelay=201, Bit 13, Center 84 (-31 ~ 200) 232
2022 11:18:38.986722 iDelay=201, Bit 14, Center 80 (-39 ~ 200) 240
2023 11:18:38.993502 iDelay=201, Bit 15, Center 84 (-31 ~ 200) 232
2024 11:18:38.993584 ==
2025 11:18:38.997143 Dram Type= 6, Freq= 0, CH_1, rank 1
2026 11:18:39.000198 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2027 11:18:39.000288 ==
2028 11:18:39.000354 DQS Delay:
2029 11:18:39.003624 DQS0 = 0, DQS1 = 0
2030 11:18:39.003719 DQM Delay:
2031 11:18:39.007141 DQM0 = 80, DQM1 = 75
2032 11:18:39.007229 DQ Delay:
2033 11:18:39.009928 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =80
2034 11:18:39.013733 DQ4 =80, DQ5 =92, DQ6 =88, DQ7 =72
2035 11:18:39.017264 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
2036 11:18:39.020119 DQ12 =80, DQ13 =84, DQ14 =80, DQ15 =84
2037 11:18:39.020209
2038 11:18:39.020273
2039 11:18:39.030178 [DQSOSCAuto] RK1, (LSB)MR18= 0x222d, (MSB)MR19= 0x606, tDQSOscB0 = 398 ps tDQSOscB1 = 401 ps
2040 11:18:39.030274 CH1 RK1: MR19=606, MR18=222D
2041 11:18:39.036977 CH1_RK1: MR19=0x606, MR18=0x222D, DQSOSC=398, MR23=63, INC=93, DEC=62
2042 11:18:39.040450 [RxdqsGatingPostProcess] freq 800
2043 11:18:39.046813 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2044 11:18:39.050303 Pre-setting of DQS Precalculation
2045 11:18:39.053747 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2046 11:18:39.060017 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2047 11:18:39.067065 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2048 11:18:39.067171
2049 11:18:39.067265
2050 11:18:39.070255 [Calibration Summary] 1600 Mbps
2051 11:18:39.074178 CH 0, Rank 0
2052 11:18:39.074254 SW Impedance : PASS
2053 11:18:39.077054 DUTY Scan : NO K
2054 11:18:39.080195 ZQ Calibration : PASS
2055 11:18:39.080328 Jitter Meter : NO K
2056 11:18:39.083680 CBT Training : PASS
2057 11:18:39.087407 Write leveling : PASS
2058 11:18:39.087550 RX DQS gating : PASS
2059 11:18:39.090344 RX DQ/DQS(RDDQC) : PASS
2060 11:18:39.090479 TX DQ/DQS : PASS
2061 11:18:39.094230 RX DATLAT : PASS
2062 11:18:39.096984 RX DQ/DQS(Engine): PASS
2063 11:18:39.097091 TX OE : NO K
2064 11:18:39.100312 All Pass.
2065 11:18:39.100388
2066 11:18:39.100449 CH 0, Rank 1
2067 11:18:39.103605 SW Impedance : PASS
2068 11:18:39.103677 DUTY Scan : NO K
2069 11:18:39.106986 ZQ Calibration : PASS
2070 11:18:39.110485 Jitter Meter : NO K
2071 11:18:39.110586 CBT Training : PASS
2072 11:18:39.113505 Write leveling : PASS
2073 11:18:39.116793 RX DQS gating : PASS
2074 11:18:39.116865 RX DQ/DQS(RDDQC) : PASS
2075 11:18:39.120361 TX DQ/DQS : PASS
2076 11:18:39.123501 RX DATLAT : PASS
2077 11:18:39.123582 RX DQ/DQS(Engine): PASS
2078 11:18:39.127056 TX OE : NO K
2079 11:18:39.127137 All Pass.
2080 11:18:39.127200
2081 11:18:39.130705 CH 1, Rank 0
2082 11:18:39.130784 SW Impedance : PASS
2083 11:18:39.133925 DUTY Scan : NO K
2084 11:18:39.136965 ZQ Calibration : PASS
2085 11:18:39.137045 Jitter Meter : NO K
2086 11:18:39.140223 CBT Training : PASS
2087 11:18:39.140303 Write leveling : PASS
2088 11:18:39.143529 RX DQS gating : PASS
2089 11:18:39.146775 RX DQ/DQS(RDDQC) : PASS
2090 11:18:39.146855 TX DQ/DQS : PASS
2091 11:18:39.150299 RX DATLAT : PASS
2092 11:18:39.153653 RX DQ/DQS(Engine): PASS
2093 11:18:39.153733 TX OE : NO K
2094 11:18:39.156892 All Pass.
2095 11:18:39.156972
2096 11:18:39.157035 CH 1, Rank 1
2097 11:18:39.160591 SW Impedance : PASS
2098 11:18:39.160671 DUTY Scan : NO K
2099 11:18:39.163616 ZQ Calibration : PASS
2100 11:18:39.167020 Jitter Meter : NO K
2101 11:18:39.167100 CBT Training : PASS
2102 11:18:39.170404 Write leveling : PASS
2103 11:18:39.173535 RX DQS gating : PASS
2104 11:18:39.173616 RX DQ/DQS(RDDQC) : PASS
2105 11:18:39.177079 TX DQ/DQS : PASS
2106 11:18:39.180249 RX DATLAT : PASS
2107 11:18:39.180331 RX DQ/DQS(Engine): PASS
2108 11:18:39.184152 TX OE : NO K
2109 11:18:39.184234 All Pass.
2110 11:18:39.184298
2111 11:18:39.186793 DramC Write-DBI off
2112 11:18:39.190509 PER_BANK_REFRESH: Hybrid Mode
2113 11:18:39.190591 TX_TRACKING: ON
2114 11:18:39.193834 [GetDramInforAfterCalByMRR] Vendor 6.
2115 11:18:39.197426 [GetDramInforAfterCalByMRR] Revision 606.
2116 11:18:39.200238 [GetDramInforAfterCalByMRR] Revision 2 0.
2117 11:18:39.200319 MR0 0x3b3b
2118 11:18:39.203666 MR8 0x5151
2119 11:18:39.207256 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2120 11:18:39.207338
2121 11:18:39.207448 MR0 0x3b3b
2122 11:18:39.210373 MR8 0x5151
2123 11:18:39.214075 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2124 11:18:39.214157
2125 11:18:39.220299 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2126 11:18:39.223662 [FAST_K] Save calibration result to emmc
2127 11:18:39.230362 [FAST_K] Save calibration result to emmc
2128 11:18:39.230443 dram_init: config_dvfs: 1
2129 11:18:39.233578 dramc_set_vcore_voltage set vcore to 662500
2130 11:18:39.237007 Read voltage for 1200, 2
2131 11:18:39.237089 Vio18 = 0
2132 11:18:39.239960 Vcore = 662500
2133 11:18:39.240042 Vdram = 0
2134 11:18:39.240106 Vddq = 0
2135 11:18:39.243461 Vmddr = 0
2136 11:18:39.247234 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2137 11:18:39.253930 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2138 11:18:39.254012 MEM_TYPE=3, freq_sel=15
2139 11:18:39.256528 sv_algorithm_assistance_LP4_1600
2140 11:18:39.263365 ============ PULL DRAM RESETB DOWN ============
2141 11:18:39.266524 ========== PULL DRAM RESETB DOWN end =========
2142 11:18:39.270114 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2143 11:18:39.273675 ===================================
2144 11:18:39.276738 LPDDR4 DRAM CONFIGURATION
2145 11:18:39.280040 ===================================
2146 11:18:39.280123 EX_ROW_EN[0] = 0x0
2147 11:18:39.283263 EX_ROW_EN[1] = 0x0
2148 11:18:39.286583 LP4Y_EN = 0x0
2149 11:18:39.286665 WORK_FSP = 0x0
2150 11:18:39.290260 WL = 0x4
2151 11:18:39.290342 RL = 0x4
2152 11:18:39.293798 BL = 0x2
2153 11:18:39.293880 RPST = 0x0
2154 11:18:39.296693 RD_PRE = 0x0
2155 11:18:39.296775 WR_PRE = 0x1
2156 11:18:39.300189 WR_PST = 0x0
2157 11:18:39.300270 DBI_WR = 0x0
2158 11:18:39.303283 DBI_RD = 0x0
2159 11:18:39.303452 OTF = 0x1
2160 11:18:39.307004 ===================================
2161 11:18:39.310152 ===================================
2162 11:18:39.313698 ANA top config
2163 11:18:39.316538 ===================================
2164 11:18:39.316621 DLL_ASYNC_EN = 0
2165 11:18:39.320202 ALL_SLAVE_EN = 0
2166 11:18:39.323293 NEW_RANK_MODE = 1
2167 11:18:39.326702 DLL_IDLE_MODE = 1
2168 11:18:39.330331 LP45_APHY_COMB_EN = 1
2169 11:18:39.330412 TX_ODT_DIS = 1
2170 11:18:39.333359 NEW_8X_MODE = 1
2171 11:18:39.336704 ===================================
2172 11:18:39.340199 ===================================
2173 11:18:39.343579 data_rate = 2400
2174 11:18:39.346685 CKR = 1
2175 11:18:39.350257 DQ_P2S_RATIO = 8
2176 11:18:39.353309 ===================================
2177 11:18:39.353391 CA_P2S_RATIO = 8
2178 11:18:39.356594 DQ_CA_OPEN = 0
2179 11:18:39.359658 DQ_SEMI_OPEN = 0
2180 11:18:39.363683 CA_SEMI_OPEN = 0
2181 11:18:39.366492 CA_FULL_RATE = 0
2182 11:18:39.369788 DQ_CKDIV4_EN = 0
2183 11:18:39.369869 CA_CKDIV4_EN = 0
2184 11:18:39.373721 CA_PREDIV_EN = 0
2185 11:18:39.376767 PH8_DLY = 17
2186 11:18:39.380269 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2187 11:18:39.383025 DQ_AAMCK_DIV = 4
2188 11:18:39.386495 CA_AAMCK_DIV = 4
2189 11:18:39.386582 CA_ADMCK_DIV = 4
2190 11:18:39.390036 DQ_TRACK_CA_EN = 0
2191 11:18:39.393168 CA_PICK = 1200
2192 11:18:39.396605 CA_MCKIO = 1200
2193 11:18:39.399677 MCKIO_SEMI = 0
2194 11:18:39.403021 PLL_FREQ = 2366
2195 11:18:39.406291 DQ_UI_PI_RATIO = 32
2196 11:18:39.409612 CA_UI_PI_RATIO = 0
2197 11:18:39.413169 ===================================
2198 11:18:39.416288 ===================================
2199 11:18:39.416371 memory_type:LPDDR4
2200 11:18:39.419601 GP_NUM : 10
2201 11:18:39.419683 SRAM_EN : 1
2202 11:18:39.423231 MD32_EN : 0
2203 11:18:39.426381 ===================================
2204 11:18:39.429714 [ANA_INIT] >>>>>>>>>>>>>>
2205 11:18:39.432957 <<<<<< [CONFIGURE PHASE]: ANA_TX
2206 11:18:39.436441 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2207 11:18:39.440313 ===================================
2208 11:18:39.440395 data_rate = 2400,PCW = 0X5b00
2209 11:18:39.443136 ===================================
2210 11:18:39.446413 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2211 11:18:39.452841 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2212 11:18:39.460112 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2213 11:18:39.462813 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2214 11:18:39.466485 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2215 11:18:39.469497 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2216 11:18:39.472973 [ANA_INIT] flow start
2217 11:18:39.476523 [ANA_INIT] PLL >>>>>>>>
2218 11:18:39.476604 [ANA_INIT] PLL <<<<<<<<
2219 11:18:39.480222 [ANA_INIT] MIDPI >>>>>>>>
2220 11:18:39.483103 [ANA_INIT] MIDPI <<<<<<<<
2221 11:18:39.483184 [ANA_INIT] DLL >>>>>>>>
2222 11:18:39.486456 [ANA_INIT] DLL <<<<<<<<
2223 11:18:39.489783 [ANA_INIT] flow end
2224 11:18:39.493223 ============ LP4 DIFF to SE enter ============
2225 11:18:39.496320 ============ LP4 DIFF to SE exit ============
2226 11:18:39.499654 [ANA_INIT] <<<<<<<<<<<<<
2227 11:18:39.503160 [Flow] Enable top DCM control >>>>>
2228 11:18:39.506458 [Flow] Enable top DCM control <<<<<
2229 11:18:39.510198 Enable DLL master slave shuffle
2230 11:18:39.513023 ==============================================================
2231 11:18:39.516191 Gating Mode config
2232 11:18:39.522914 ==============================================================
2233 11:18:39.522996 Config description:
2234 11:18:39.532809 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2235 11:18:39.539580 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2236 11:18:39.543228 SELPH_MODE 0: By rank 1: By Phase
2237 11:18:39.549846 ==============================================================
2238 11:18:39.552838 GAT_TRACK_EN = 1
2239 11:18:39.556048 RX_GATING_MODE = 2
2240 11:18:39.559627 RX_GATING_TRACK_MODE = 2
2241 11:18:39.562916 SELPH_MODE = 1
2242 11:18:39.566018 PICG_EARLY_EN = 1
2243 11:18:39.569669 VALID_LAT_VALUE = 1
2244 11:18:39.572775 ==============================================================
2245 11:18:39.575988 Enter into Gating configuration >>>>
2246 11:18:39.579475 Exit from Gating configuration <<<<
2247 11:18:39.583070 Enter into DVFS_PRE_config >>>>>
2248 11:18:39.592750 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2249 11:18:39.596155 Exit from DVFS_PRE_config <<<<<
2250 11:18:39.599194 Enter into PICG configuration >>>>
2251 11:18:39.602606 Exit from PICG configuration <<<<
2252 11:18:39.606124 [RX_INPUT] configuration >>>>>
2253 11:18:39.609816 [RX_INPUT] configuration <<<<<
2254 11:18:39.613375 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2255 11:18:39.619129 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2256 11:18:39.626492 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2257 11:18:39.632926 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2258 11:18:39.639781 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2259 11:18:39.646068 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2260 11:18:39.649152 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2261 11:18:39.652918 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2262 11:18:39.656276 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2263 11:18:39.659307 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2264 11:18:39.665746 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2265 11:18:39.669341 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2266 11:18:39.672475 ===================================
2267 11:18:39.676500 LPDDR4 DRAM CONFIGURATION
2268 11:18:39.679283 ===================================
2269 11:18:39.679422 EX_ROW_EN[0] = 0x0
2270 11:18:39.682468 EX_ROW_EN[1] = 0x0
2271 11:18:39.682548 LP4Y_EN = 0x0
2272 11:18:39.686264 WORK_FSP = 0x0
2273 11:18:39.686345 WL = 0x4
2274 11:18:39.689600 RL = 0x4
2275 11:18:39.689682 BL = 0x2
2276 11:18:39.692746 RPST = 0x0
2277 11:18:39.692827 RD_PRE = 0x0
2278 11:18:39.696132 WR_PRE = 0x1
2279 11:18:39.699203 WR_PST = 0x0
2280 11:18:39.699309 DBI_WR = 0x0
2281 11:18:39.702391 DBI_RD = 0x0
2282 11:18:39.702472 OTF = 0x1
2283 11:18:39.706403 ===================================
2284 11:18:39.709452 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2285 11:18:39.713072 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2286 11:18:39.719291 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2287 11:18:39.722640 ===================================
2288 11:18:39.725955 LPDDR4 DRAM CONFIGURATION
2289 11:18:39.729164 ===================================
2290 11:18:39.729245 EX_ROW_EN[0] = 0x10
2291 11:18:39.733556 EX_ROW_EN[1] = 0x0
2292 11:18:39.733636 LP4Y_EN = 0x0
2293 11:18:39.735891 WORK_FSP = 0x0
2294 11:18:39.735971 WL = 0x4
2295 11:18:39.739724 RL = 0x4
2296 11:18:39.739804 BL = 0x2
2297 11:18:39.742683 RPST = 0x0
2298 11:18:39.742762 RD_PRE = 0x0
2299 11:18:39.745753 WR_PRE = 0x1
2300 11:18:39.745832 WR_PST = 0x0
2301 11:18:39.749015 DBI_WR = 0x0
2302 11:18:39.749094 DBI_RD = 0x0
2303 11:18:39.752657 OTF = 0x1
2304 11:18:39.755914 ===================================
2305 11:18:39.762845 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2306 11:18:39.762949 ==
2307 11:18:39.766178 Dram Type= 6, Freq= 0, CH_0, rank 0
2308 11:18:39.769381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2309 11:18:39.769462 ==
2310 11:18:39.772630 [Duty_Offset_Calibration]
2311 11:18:39.772709 B0:3 B1:-1 CA:1
2312 11:18:39.772771
2313 11:18:39.776084 [DutyScan_Calibration_Flow] k_type=0
2314 11:18:39.785814
2315 11:18:39.785893 ==CLK 0==
2316 11:18:39.789059 Final CLK duty delay cell = -4
2317 11:18:39.792453 [-4] MAX Duty = 5031%(X100), DQS PI = 4
2318 11:18:39.796124 [-4] MIN Duty = 4875%(X100), DQS PI = 30
2319 11:18:39.799445 [-4] AVG Duty = 4953%(X100)
2320 11:18:39.799541
2321 11:18:39.803058 CH0 CLK Duty spec in!! Max-Min= 156%
2322 11:18:39.805850 [DutyScan_Calibration_Flow] ====Done====
2323 11:18:39.805930
2324 11:18:39.808919 [DutyScan_Calibration_Flow] k_type=1
2325 11:18:39.824387
2326 11:18:39.824476 ==DQS 0 ==
2327 11:18:39.827705 Final DQS duty delay cell = 0
2328 11:18:39.831296 [0] MAX Duty = 5125%(X100), DQS PI = 46
2329 11:18:39.834649 [0] MIN Duty = 5000%(X100), DQS PI = 12
2330 11:18:39.837726 [0] AVG Duty = 5062%(X100)
2331 11:18:39.837804
2332 11:18:39.837865 ==DQS 1 ==
2333 11:18:39.841019 Final DQS duty delay cell = -4
2334 11:18:39.844787 [-4] MAX Duty = 5093%(X100), DQS PI = 16
2335 11:18:39.848014 [-4] MIN Duty = 5000%(X100), DQS PI = 48
2336 11:18:39.851466 [-4] AVG Duty = 5046%(X100)
2337 11:18:39.851546
2338 11:18:39.854502 CH0 DQS 0 Duty spec in!! Max-Min= 125%
2339 11:18:39.854587
2340 11:18:39.857889 CH0 DQS 1 Duty spec in!! Max-Min= 93%
2341 11:18:39.861440 [DutyScan_Calibration_Flow] ====Done====
2342 11:18:39.861519
2343 11:18:39.864717 [DutyScan_Calibration_Flow] k_type=3
2344 11:18:39.881152
2345 11:18:39.881233 ==DQM 0 ==
2346 11:18:39.884788 Final DQM duty delay cell = 0
2347 11:18:39.888101 [0] MAX Duty = 5000%(X100), DQS PI = 52
2348 11:18:39.891248 [0] MIN Duty = 4906%(X100), DQS PI = 2
2349 11:18:39.891329 [0] AVG Duty = 4953%(X100)
2350 11:18:39.894683
2351 11:18:39.894763 ==DQM 1 ==
2352 11:18:39.898015 Final DQM duty delay cell = 0
2353 11:18:39.901609 [0] MAX Duty = 5124%(X100), DQS PI = 62
2354 11:18:39.904911 [0] MIN Duty = 5000%(X100), DQS PI = 8
2355 11:18:39.904992 [0] AVG Duty = 5062%(X100)
2356 11:18:39.905056
2357 11:18:39.907965 CH0 DQM 0 Duty spec in!! Max-Min= 94%
2358 11:18:39.911257
2359 11:18:39.914713 CH0 DQM 1 Duty spec in!! Max-Min= 124%
2360 11:18:39.918014 [DutyScan_Calibration_Flow] ====Done====
2361 11:18:39.918095
2362 11:18:39.921666 [DutyScan_Calibration_Flow] k_type=2
2363 11:18:39.936822
2364 11:18:39.936903 ==DQ 0 ==
2365 11:18:39.940344 Final DQ duty delay cell = -4
2366 11:18:39.943823 [-4] MAX Duty = 5062%(X100), DQS PI = 54
2367 11:18:39.946929 [-4] MIN Duty = 4875%(X100), DQS PI = 12
2368 11:18:39.950154 [-4] AVG Duty = 4968%(X100)
2369 11:18:39.950235
2370 11:18:39.950329 ==DQ 1 ==
2371 11:18:39.954011 Final DQ duty delay cell = 0
2372 11:18:39.957033 [0] MAX Duty = 5031%(X100), DQS PI = 18
2373 11:18:39.960629 [0] MIN Duty = 4907%(X100), DQS PI = 46
2374 11:18:39.960711 [0] AVG Duty = 4969%(X100)
2375 11:18:39.963736
2376 11:18:39.966907 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2377 11:18:39.966988
2378 11:18:39.970513 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2379 11:18:39.973481 [DutyScan_Calibration_Flow] ====Done====
2380 11:18:39.973562 ==
2381 11:18:39.977468 Dram Type= 6, Freq= 0, CH_1, rank 0
2382 11:18:39.980356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2383 11:18:39.980438 ==
2384 11:18:39.983943 [Duty_Offset_Calibration]
2385 11:18:39.984023 B0:1 B1:1 CA:2
2386 11:18:39.984087
2387 11:18:39.986965 [DutyScan_Calibration_Flow] k_type=0
2388 11:18:39.997456
2389 11:18:39.997536 ==CLK 0==
2390 11:18:40.000482 Final CLK duty delay cell = 0
2391 11:18:40.004346 [0] MAX Duty = 5125%(X100), DQS PI = 24
2392 11:18:40.007641 [0] MIN Duty = 4938%(X100), DQS PI = 40
2393 11:18:40.007722 [0] AVG Duty = 5031%(X100)
2394 11:18:40.010413
2395 11:18:40.014498 CH1 CLK Duty spec in!! Max-Min= 187%
2396 11:18:40.017365 [DutyScan_Calibration_Flow] ====Done====
2397 11:18:40.017446
2398 11:18:40.020592 [DutyScan_Calibration_Flow] k_type=1
2399 11:18:40.036482
2400 11:18:40.036562 ==DQS 0 ==
2401 11:18:40.040151 Final DQS duty delay cell = 0
2402 11:18:40.043707 [0] MAX Duty = 5031%(X100), DQS PI = 18
2403 11:18:40.047161 [0] MIN Duty = 4844%(X100), DQS PI = 50
2404 11:18:40.047241 [0] AVG Duty = 4937%(X100)
2405 11:18:40.049921
2406 11:18:40.050001 ==DQS 1 ==
2407 11:18:40.053251 Final DQS duty delay cell = 0
2408 11:18:40.056600 [0] MAX Duty = 5062%(X100), DQS PI = 36
2409 11:18:40.059949 [0] MIN Duty = 4907%(X100), DQS PI = 14
2410 11:18:40.060029 [0] AVG Duty = 4984%(X100)
2411 11:18:40.063215
2412 11:18:40.066514 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2413 11:18:40.066594
2414 11:18:40.069825 CH1 DQS 1 Duty spec in!! Max-Min= 155%
2415 11:18:40.073161 [DutyScan_Calibration_Flow] ====Done====
2416 11:18:40.073241
2417 11:18:40.076774 [DutyScan_Calibration_Flow] k_type=3
2418 11:18:40.093121
2419 11:18:40.093201 ==DQM 0 ==
2420 11:18:40.097227 Final DQM duty delay cell = 0
2421 11:18:40.099615 [0] MAX Duty = 5093%(X100), DQS PI = 18
2422 11:18:40.103025 [0] MIN Duty = 4907%(X100), DQS PI = 48
2423 11:18:40.103106 [0] AVG Duty = 5000%(X100)
2424 11:18:40.106367
2425 11:18:40.106447 ==DQM 1 ==
2426 11:18:40.110162 Final DQM duty delay cell = 0
2427 11:18:40.113607 [0] MAX Duty = 5156%(X100), DQS PI = 62
2428 11:18:40.116327 [0] MIN Duty = 4938%(X100), DQS PI = 22
2429 11:18:40.119804 [0] AVG Duty = 5047%(X100)
2430 11:18:40.119884
2431 11:18:40.123031 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2432 11:18:40.123110
2433 11:18:40.126500 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2434 11:18:40.129517 [DutyScan_Calibration_Flow] ====Done====
2435 11:18:40.129603
2436 11:18:40.132962 [DutyScan_Calibration_Flow] k_type=2
2437 11:18:40.149511
2438 11:18:40.149591 ==DQ 0 ==
2439 11:18:40.153149 Final DQ duty delay cell = 0
2440 11:18:40.156581 [0] MAX Duty = 5124%(X100), DQS PI = 18
2441 11:18:40.159726 [0] MIN Duty = 4938%(X100), DQS PI = 50
2442 11:18:40.159807 [0] AVG Duty = 5031%(X100)
2443 11:18:40.159870
2444 11:18:40.163022 ==DQ 1 ==
2445 11:18:40.166612 Final DQ duty delay cell = 0
2446 11:18:40.169889 [0] MAX Duty = 5093%(X100), DQS PI = 10
2447 11:18:40.173455 [0] MIN Duty = 5031%(X100), DQS PI = 2
2448 11:18:40.173561 [0] AVG Duty = 5062%(X100)
2449 11:18:40.173660
2450 11:18:40.176482 CH1 DQ 0 Duty spec in!! Max-Min= 186%
2451 11:18:40.176564
2452 11:18:40.179847 CH1 DQ 1 Duty spec in!! Max-Min= 62%
2453 11:18:40.186340 [DutyScan_Calibration_Flow] ====Done====
2454 11:18:40.189811 nWR fixed to 30
2455 11:18:40.189894 [ModeRegInit_LP4] CH0 RK0
2456 11:18:40.193241 [ModeRegInit_LP4] CH0 RK1
2457 11:18:40.197046 [ModeRegInit_LP4] CH1 RK0
2458 11:18:40.197128 [ModeRegInit_LP4] CH1 RK1
2459 11:18:40.199704 match AC timing 7
2460 11:18:40.202959 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2461 11:18:40.206375 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2462 11:18:40.213107 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2463 11:18:40.216467 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2464 11:18:40.223197 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2465 11:18:40.223280 ==
2466 11:18:40.226509 Dram Type= 6, Freq= 0, CH_0, rank 0
2467 11:18:40.229597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2468 11:18:40.229681 ==
2469 11:18:40.236913 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2470 11:18:40.240574 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2471 11:18:40.249464 [CA 0] Center 40 (10~71) winsize 62
2472 11:18:40.252852 [CA 1] Center 39 (9~70) winsize 62
2473 11:18:40.256696 [CA 2] Center 36 (6~67) winsize 62
2474 11:18:40.259742 [CA 3] Center 35 (5~66) winsize 62
2475 11:18:40.263280 [CA 4] Center 34 (4~65) winsize 62
2476 11:18:40.266443 [CA 5] Center 34 (4~64) winsize 61
2477 11:18:40.266527
2478 11:18:40.269435 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2479 11:18:40.269518
2480 11:18:40.272784 [CATrainingPosCal] consider 1 rank data
2481 11:18:40.276492 u2DelayCellTimex100 = 270/100 ps
2482 11:18:40.279286 CA0 delay=40 (10~71),Diff = 6 PI (28 cell)
2483 11:18:40.286316 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2484 11:18:40.289448 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2485 11:18:40.293338 CA3 delay=35 (5~66),Diff = 1 PI (4 cell)
2486 11:18:40.296098 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2487 11:18:40.299547 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2488 11:18:40.299629
2489 11:18:40.302730 CA PerBit enable=1, Macro0, CA PI delay=34
2490 11:18:40.302812
2491 11:18:40.306380 [CBTSetCACLKResult] CA Dly = 34
2492 11:18:40.306462 CS Dly: 7 (0~38)
2493 11:18:40.309528 ==
2494 11:18:40.309612 Dram Type= 6, Freq= 0, CH_0, rank 1
2495 11:18:40.316623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2496 11:18:40.316708 ==
2497 11:18:40.319463 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2498 11:18:40.325764 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2499 11:18:40.335453 [CA 0] Center 39 (9~70) winsize 62
2500 11:18:40.338633 [CA 1] Center 39 (9~70) winsize 62
2501 11:18:40.342262 [CA 2] Center 36 (6~67) winsize 62
2502 11:18:40.346059 [CA 3] Center 36 (6~67) winsize 62
2503 11:18:40.349211 [CA 4] Center 34 (4~65) winsize 62
2504 11:18:40.352099 [CA 5] Center 34 (4~64) winsize 61
2505 11:18:40.352182
2506 11:18:40.355542 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2507 11:18:40.355624
2508 11:18:40.359044 [CATrainingPosCal] consider 2 rank data
2509 11:18:40.362136 u2DelayCellTimex100 = 270/100 ps
2510 11:18:40.365555 CA0 delay=40 (10~70),Diff = 6 PI (28 cell)
2511 11:18:40.368990 CA1 delay=39 (9~70),Diff = 5 PI (24 cell)
2512 11:18:40.375686 CA2 delay=36 (6~67),Diff = 2 PI (9 cell)
2513 11:18:40.378812 CA3 delay=36 (6~66),Diff = 2 PI (9 cell)
2514 11:18:40.382328 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
2515 11:18:40.385601 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
2516 11:18:40.385683
2517 11:18:40.389078 CA PerBit enable=1, Macro0, CA PI delay=34
2518 11:18:40.389160
2519 11:18:40.392126 [CBTSetCACLKResult] CA Dly = 34
2520 11:18:40.392209 CS Dly: 8 (0~41)
2521 11:18:40.392291
2522 11:18:40.395666 ----->DramcWriteLeveling(PI) begin...
2523 11:18:40.398988 ==
2524 11:18:40.399070 Dram Type= 6, Freq= 0, CH_0, rank 0
2525 11:18:40.405428 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2526 11:18:40.405512 ==
2527 11:18:40.408739 Write leveling (Byte 0): 29 => 29
2528 11:18:40.412123 Write leveling (Byte 1): 28 => 28
2529 11:18:40.415560 DramcWriteLeveling(PI) end<-----
2530 11:18:40.415642
2531 11:18:40.415724 ==
2532 11:18:40.419044 Dram Type= 6, Freq= 0, CH_0, rank 0
2533 11:18:40.422166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2534 11:18:40.422249 ==
2535 11:18:40.425273 [Gating] SW mode calibration
2536 11:18:40.432047 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2537 11:18:40.435797 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2538 11:18:40.442414 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2539 11:18:40.445505 0 15 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
2540 11:18:40.448905 0 15 8 | B1->B0 | 3332 3434 | 1 1 | (1 1) (1 1)
2541 11:18:40.455818 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2542 11:18:40.459234 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2543 11:18:40.462170 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2544 11:18:40.468831 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2545 11:18:40.471937 0 15 28 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
2546 11:18:40.475632 1 0 0 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 1)
2547 11:18:40.481976 1 0 4 | B1->B0 | 2828 2323 | 0 0 | (0 1) (1 0)
2548 11:18:40.485617 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2549 11:18:40.488583 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2550 11:18:40.495613 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2551 11:18:40.498757 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2552 11:18:40.501939 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2553 11:18:40.508977 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2554 11:18:40.512193 1 1 0 | B1->B0 | 2424 2929 | 0 0 | (0 0) (1 1)
2555 11:18:40.515368 1 1 4 | B1->B0 | 3b3a 4646 | 1 0 | (0 0) (0 0)
2556 11:18:40.522005 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2557 11:18:40.525543 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2558 11:18:40.528651 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2559 11:18:40.532622 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 11:18:40.538959 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2561 11:18:40.542054 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2562 11:18:40.545864 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2563 11:18:40.552263 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2564 11:18:40.555432 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2565 11:18:40.558960 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2566 11:18:40.565605 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2567 11:18:40.569091 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2568 11:18:40.572319 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2569 11:18:40.578710 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2570 11:18:40.582097 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2571 11:18:40.585439 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2572 11:18:40.592358 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2573 11:18:40.595681 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2574 11:18:40.599408 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2575 11:18:40.605537 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2576 11:18:40.609160 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2577 11:18:40.612112 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2578 11:18:40.618712 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2579 11:18:40.622020 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2580 11:18:40.625434 Total UI for P1: 0, mck2ui 16
2581 11:18:40.628944 best dqsien dly found for B0: ( 1, 4, 0)
2582 11:18:40.632248 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2583 11:18:40.635466 Total UI for P1: 0, mck2ui 16
2584 11:18:40.638667 best dqsien dly found for B1: ( 1, 4, 2)
2585 11:18:40.641978 best DQS0 dly(MCK, UI, PI) = (1, 4, 0)
2586 11:18:40.645100 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2587 11:18:40.645181
2588 11:18:40.648889 best DQS0 P1 dly(MCK, UI, PI) = (1, 8, 0)
2589 11:18:40.651947 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2590 11:18:40.655365 [Gating] SW calibration Done
2591 11:18:40.655460 ==
2592 11:18:40.658905 Dram Type= 6, Freq= 0, CH_0, rank 0
2593 11:18:40.662028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2594 11:18:40.665571 ==
2595 11:18:40.665652 RX Vref Scan: 0
2596 11:18:40.665715
2597 11:18:40.668567 RX Vref 0 -> 0, step: 1
2598 11:18:40.668648
2599 11:18:40.672532 RX Delay -40 -> 252, step: 8
2600 11:18:40.675235 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2601 11:18:40.678704 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2602 11:18:40.681841 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2603 11:18:40.685807 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2604 11:18:40.692126 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2605 11:18:40.695245 iDelay=200, Bit 5, Center 107 (40 ~ 175) 136
2606 11:18:40.698624 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2607 11:18:40.702035 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2608 11:18:40.705176 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2609 11:18:40.708733 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2610 11:18:40.715765 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2611 11:18:40.718783 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2612 11:18:40.722252 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2613 11:18:40.725103 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2614 11:18:40.728836 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2615 11:18:40.735685 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2616 11:18:40.735768 ==
2617 11:18:40.738576 Dram Type= 6, Freq= 0, CH_0, rank 0
2618 11:18:40.742043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2619 11:18:40.742126 ==
2620 11:18:40.742190 DQS Delay:
2621 11:18:40.745166 DQS0 = 0, DQS1 = 0
2622 11:18:40.745247 DQM Delay:
2623 11:18:40.748410 DQM0 = 115, DQM1 = 107
2624 11:18:40.748492 DQ Delay:
2625 11:18:40.751777 DQ0 =115, DQ1 =115, DQ2 =115, DQ3 =111
2626 11:18:40.755484 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2627 11:18:40.758507 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =99
2628 11:18:40.761807 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =115
2629 11:18:40.761890
2630 11:18:40.761953
2631 11:18:40.765404 ==
2632 11:18:40.769071 Dram Type= 6, Freq= 0, CH_0, rank 0
2633 11:18:40.771905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2634 11:18:40.771987 ==
2635 11:18:40.772052
2636 11:18:40.772110
2637 11:18:40.775618 TX Vref Scan disable
2638 11:18:40.775699 == TX Byte 0 ==
2639 11:18:40.778689 Update DQ dly =849 (3 ,2, 17) DQ OEN =(2 ,7)
2640 11:18:40.785273 Update DQM dly =849 (3 ,2, 17) DQM OEN =(2 ,7)
2641 11:18:40.785355 == TX Byte 1 ==
2642 11:18:40.788651 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2643 11:18:40.795444 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2644 11:18:40.795527 ==
2645 11:18:40.799062 Dram Type= 6, Freq= 0, CH_0, rank 0
2646 11:18:40.801927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2647 11:18:40.802010 ==
2648 11:18:40.813931 TX Vref=22, minBit 1, minWin=25, winSum=419
2649 11:18:40.817147 TX Vref=24, minBit 1, minWin=25, winSum=424
2650 11:18:40.820836 TX Vref=26, minBit 1, minWin=25, winSum=425
2651 11:18:40.824071 TX Vref=28, minBit 3, minWin=26, winSum=434
2652 11:18:40.827372 TX Vref=30, minBit 1, minWin=26, winSum=437
2653 11:18:40.830440 TX Vref=32, minBit 1, minWin=26, winSum=437
2654 11:18:40.837586 [TxChooseVref] Worse bit 1, Min win 26, Win sum 437, Final Vref 30
2655 11:18:40.837676
2656 11:18:40.840601 Final TX Range 1 Vref 30
2657 11:18:40.840684
2658 11:18:40.840749 ==
2659 11:18:40.844343 Dram Type= 6, Freq= 0, CH_0, rank 0
2660 11:18:40.847622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2661 11:18:40.847705 ==
2662 11:18:40.847769
2663 11:18:40.850884
2664 11:18:40.850965 TX Vref Scan disable
2665 11:18:40.853925 == TX Byte 0 ==
2666 11:18:40.857269 Update DQ dly =848 (3 ,2, 16) DQ OEN =(2 ,7)
2667 11:18:40.861091 Update DQM dly =848 (3 ,2, 16) DQM OEN =(2 ,7)
2668 11:18:40.864044 == TX Byte 1 ==
2669 11:18:40.867640 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2670 11:18:40.870847 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2671 11:18:40.870929
2672 11:18:40.873765 [DATLAT]
2673 11:18:40.873846 Freq=1200, CH0 RK0
2674 11:18:40.873911
2675 11:18:40.877562 DATLAT Default: 0xd
2676 11:18:40.877645 0, 0xFFFF, sum = 0
2677 11:18:40.880958 1, 0xFFFF, sum = 0
2678 11:18:40.881042 2, 0xFFFF, sum = 0
2679 11:18:40.883833 3, 0xFFFF, sum = 0
2680 11:18:40.883917 4, 0xFFFF, sum = 0
2681 11:18:40.887207 5, 0xFFFF, sum = 0
2682 11:18:40.887290 6, 0xFFFF, sum = 0
2683 11:18:40.890932 7, 0xFFFF, sum = 0
2684 11:18:40.891014 8, 0xFFFF, sum = 0
2685 11:18:40.893728 9, 0xFFFF, sum = 0
2686 11:18:40.897683 10, 0xFFFF, sum = 0
2687 11:18:40.897765 11, 0xFFFF, sum = 0
2688 11:18:40.900745 12, 0x0, sum = 1
2689 11:18:40.900828 13, 0x0, sum = 2
2690 11:18:40.900893 14, 0x0, sum = 3
2691 11:18:40.904170 15, 0x0, sum = 4
2692 11:18:40.904253 best_step = 13
2693 11:18:40.904317
2694 11:18:40.907261 ==
2695 11:18:40.907409 Dram Type= 6, Freq= 0, CH_0, rank 0
2696 11:18:40.914382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2697 11:18:40.914464 ==
2698 11:18:40.914528 RX Vref Scan: 1
2699 11:18:40.914587
2700 11:18:40.917250 Set Vref Range= 32 -> 127
2701 11:18:40.917331
2702 11:18:40.920634 RX Vref 32 -> 127, step: 1
2703 11:18:40.920716
2704 11:18:40.923614 RX Delay -21 -> 252, step: 4
2705 11:18:40.923696
2706 11:18:40.927338 Set Vref, RX VrefLevel [Byte0]: 32
2707 11:18:40.930781 [Byte1]: 32
2708 11:18:40.930862
2709 11:18:40.934153 Set Vref, RX VrefLevel [Byte0]: 33
2710 11:18:40.937794 [Byte1]: 33
2711 11:18:40.937876
2712 11:18:40.940835 Set Vref, RX VrefLevel [Byte0]: 34
2713 11:18:40.944109 [Byte1]: 34
2714 11:18:40.948161
2715 11:18:40.948243 Set Vref, RX VrefLevel [Byte0]: 35
2716 11:18:40.951620 [Byte1]: 35
2717 11:18:40.955709
2718 11:18:40.955790 Set Vref, RX VrefLevel [Byte0]: 36
2719 11:18:40.959189 [Byte1]: 36
2720 11:18:40.964083
2721 11:18:40.964165 Set Vref, RX VrefLevel [Byte0]: 37
2722 11:18:40.967724 [Byte1]: 37
2723 11:18:40.971724
2724 11:18:40.971806 Set Vref, RX VrefLevel [Byte0]: 38
2725 11:18:40.975150 [Byte1]: 38
2726 11:18:40.979681
2727 11:18:40.979763 Set Vref, RX VrefLevel [Byte0]: 39
2728 11:18:40.983158 [Byte1]: 39
2729 11:18:40.988023
2730 11:18:40.988104 Set Vref, RX VrefLevel [Byte0]: 40
2731 11:18:40.991161 [Byte1]: 40
2732 11:18:40.995777
2733 11:18:40.995858 Set Vref, RX VrefLevel [Byte0]: 41
2734 11:18:40.999133 [Byte1]: 41
2735 11:18:41.003646
2736 11:18:41.003727 Set Vref, RX VrefLevel [Byte0]: 42
2737 11:18:41.006710 [Byte1]: 42
2738 11:18:41.011558
2739 11:18:41.011639 Set Vref, RX VrefLevel [Byte0]: 43
2740 11:18:41.014858 [Byte1]: 43
2741 11:18:41.019197
2742 11:18:41.019304 Set Vref, RX VrefLevel [Byte0]: 44
2743 11:18:41.022539 [Byte1]: 44
2744 11:18:41.027625
2745 11:18:41.027705 Set Vref, RX VrefLevel [Byte0]: 45
2746 11:18:41.030692 [Byte1]: 45
2747 11:18:41.035230
2748 11:18:41.035337 Set Vref, RX VrefLevel [Byte0]: 46
2749 11:18:41.038477 [Byte1]: 46
2750 11:18:41.043033
2751 11:18:41.043113 Set Vref, RX VrefLevel [Byte0]: 47
2752 11:18:41.046757 [Byte1]: 47
2753 11:18:41.051084
2754 11:18:41.051165 Set Vref, RX VrefLevel [Byte0]: 48
2755 11:18:41.054308 [Byte1]: 48
2756 11:18:41.059203
2757 11:18:41.059283 Set Vref, RX VrefLevel [Byte0]: 49
2758 11:18:41.062375 [Byte1]: 49
2759 11:18:41.067019
2760 11:18:41.067099 Set Vref, RX VrefLevel [Byte0]: 50
2761 11:18:41.070633 [Byte1]: 50
2762 11:18:41.074933
2763 11:18:41.075013 Set Vref, RX VrefLevel [Byte0]: 51
2764 11:18:41.078087 [Byte1]: 51
2765 11:18:41.083120
2766 11:18:41.083227 Set Vref, RX VrefLevel [Byte0]: 52
2767 11:18:41.086165 [Byte1]: 52
2768 11:18:41.091159
2769 11:18:41.091240 Set Vref, RX VrefLevel [Byte0]: 53
2770 11:18:41.094258 [Byte1]: 53
2771 11:18:41.098696
2772 11:18:41.098776 Set Vref, RX VrefLevel [Byte0]: 54
2773 11:18:41.102297 [Byte1]: 54
2774 11:18:41.106688
2775 11:18:41.106771 Set Vref, RX VrefLevel [Byte0]: 55
2776 11:18:41.109623 [Byte1]: 55
2777 11:18:41.114443
2778 11:18:41.114523 Set Vref, RX VrefLevel [Byte0]: 56
2779 11:18:41.117952 [Byte1]: 56
2780 11:18:41.122546
2781 11:18:41.122626 Set Vref, RX VrefLevel [Byte0]: 57
2782 11:18:41.125547 [Byte1]: 57
2783 11:18:41.130563
2784 11:18:41.130643 Set Vref, RX VrefLevel [Byte0]: 58
2785 11:18:41.133615 [Byte1]: 58
2786 11:18:41.138058
2787 11:18:41.138139 Set Vref, RX VrefLevel [Byte0]: 59
2788 11:18:41.141446 [Byte1]: 59
2789 11:18:41.146200
2790 11:18:41.146281 Set Vref, RX VrefLevel [Byte0]: 60
2791 11:18:41.149281 [Byte1]: 60
2792 11:18:41.154090
2793 11:18:41.154170 Set Vref, RX VrefLevel [Byte0]: 61
2794 11:18:41.157724 [Byte1]: 61
2795 11:18:41.162276
2796 11:18:41.162356 Set Vref, RX VrefLevel [Byte0]: 62
2797 11:18:41.165123 [Byte1]: 62
2798 11:18:41.169966
2799 11:18:41.170046 Set Vref, RX VrefLevel [Byte0]: 63
2800 11:18:41.173284 [Byte1]: 63
2801 11:18:41.177874
2802 11:18:41.177953 Set Vref, RX VrefLevel [Byte0]: 64
2803 11:18:41.181274 [Byte1]: 64
2804 11:18:41.186099
2805 11:18:41.186178 Set Vref, RX VrefLevel [Byte0]: 65
2806 11:18:41.189018 [Byte1]: 65
2807 11:18:41.193714
2808 11:18:41.193820 Set Vref, RX VrefLevel [Byte0]: 66
2809 11:18:41.197358 [Byte1]: 66
2810 11:18:41.201879
2811 11:18:41.202012 Set Vref, RX VrefLevel [Byte0]: 67
2812 11:18:41.205355 [Byte1]: 67
2813 11:18:41.209483
2814 11:18:41.209562 Set Vref, RX VrefLevel [Byte0]: 68
2815 11:18:41.213134 [Byte1]: 68
2816 11:18:41.217505
2817 11:18:41.217583 Set Vref, RX VrefLevel [Byte0]: 69
2818 11:18:41.221078 [Byte1]: 69
2819 11:18:41.225568
2820 11:18:41.225647 Set Vref, RX VrefLevel [Byte0]: 70
2821 11:18:41.228912 [Byte1]: 70
2822 11:18:41.233736
2823 11:18:41.233814 Final RX Vref Byte 0 = 52 to rank0
2824 11:18:41.236700 Final RX Vref Byte 1 = 51 to rank0
2825 11:18:41.240223 Final RX Vref Byte 0 = 52 to rank1
2826 11:18:41.242891 Final RX Vref Byte 1 = 51 to rank1==
2827 11:18:41.246372 Dram Type= 6, Freq= 0, CH_0, rank 0
2828 11:18:41.253319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2829 11:18:41.253399 ==
2830 11:18:41.253461 DQS Delay:
2831 11:18:41.256637 DQS0 = 0, DQS1 = 0
2832 11:18:41.256715 DQM Delay:
2833 11:18:41.256776 DQM0 = 115, DQM1 = 104
2834 11:18:41.259893 DQ Delay:
2835 11:18:41.263114 DQ0 =116, DQ1 =116, DQ2 =112, DQ3 =114
2836 11:18:41.266787 DQ4 =116, DQ5 =108, DQ6 =122, DQ7 =122
2837 11:18:41.269699 DQ8 =92, DQ9 =90, DQ10 =104, DQ11 =96
2838 11:18:41.273160 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2839 11:18:41.273240
2840 11:18:41.273303
2841 11:18:41.282942 [DQSOSCAuto] RK0, (LSB)MR18= 0xfbea, (MSB)MR19= 0x303, tDQSOscB0 = 419 ps tDQSOscB1 = 412 ps
2842 11:18:41.283022 CH0 RK0: MR19=303, MR18=FBEA
2843 11:18:41.289756 CH0_RK0: MR19=0x303, MR18=0xFBEA, DQSOSC=412, MR23=63, INC=38, DEC=25
2844 11:18:41.289836
2845 11:18:41.293321 ----->DramcWriteLeveling(PI) begin...
2846 11:18:41.293403 ==
2847 11:18:41.296593 Dram Type= 6, Freq= 0, CH_0, rank 1
2848 11:18:41.299566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2849 11:18:41.303145 ==
2850 11:18:41.303224 Write leveling (Byte 0): 31 => 31
2851 11:18:41.306664 Write leveling (Byte 1): 29 => 29
2852 11:18:41.309525 DramcWriteLeveling(PI) end<-----
2853 11:18:41.309604
2854 11:18:41.309667 ==
2855 11:18:41.312620 Dram Type= 6, Freq= 0, CH_0, rank 1
2856 11:18:41.319831 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2857 11:18:41.319913 ==
2858 11:18:41.322916 [Gating] SW mode calibration
2859 11:18:41.329668 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2860 11:18:41.332992 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2861 11:18:41.339489 0 15 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
2862 11:18:41.342864 0 15 4 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
2863 11:18:41.346273 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2864 11:18:41.352825 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2865 11:18:41.356457 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2866 11:18:41.359324 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2867 11:18:41.366035 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2868 11:18:41.369967 0 15 28 | B1->B0 | 3434 2727 | 1 0 | (1 0) (1 0)
2869 11:18:41.372991 1 0 0 | B1->B0 | 2d2d 2323 | 1 0 | (1 0) (0 0)
2870 11:18:41.379137 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2871 11:18:41.382842 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2872 11:18:41.386129 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2873 11:18:41.389174 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2874 11:18:41.396003 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2875 11:18:41.399095 1 0 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
2876 11:18:41.402988 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2877 11:18:41.409027 1 1 0 | B1->B0 | 2c2c 3c3c | 0 0 | (0 0) (0 0)
2878 11:18:41.412391 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2879 11:18:41.415707 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2880 11:18:41.422267 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2881 11:18:41.425826 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2882 11:18:41.429077 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2883 11:18:41.436115 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2884 11:18:41.439352 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2885 11:18:41.442252 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2886 11:18:41.449356 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 11:18:41.452383 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 11:18:41.455741 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 11:18:41.462751 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 11:18:41.465909 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 11:18:41.468993 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2892 11:18:41.475544 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2893 11:18:41.478823 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2894 11:18:41.482121 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2895 11:18:41.488729 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2896 11:18:41.492168 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2897 11:18:41.495547 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2898 11:18:41.502110 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2899 11:18:41.505415 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2900 11:18:41.508997 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2901 11:18:41.515199 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2902 11:18:41.515307 Total UI for P1: 0, mck2ui 16
2903 11:18:41.518724 best dqsien dly found for B0: ( 1, 3, 26)
2904 11:18:41.525496 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2905 11:18:41.529168 Total UI for P1: 0, mck2ui 16
2906 11:18:41.532183 best dqsien dly found for B1: ( 1, 4, 0)
2907 11:18:41.535867 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2908 11:18:41.539041 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2909 11:18:41.539122
2910 11:18:41.542677 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2911 11:18:41.545669 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2912 11:18:41.548928 [Gating] SW calibration Done
2913 11:18:41.549010 ==
2914 11:18:41.552173 Dram Type= 6, Freq= 0, CH_0, rank 1
2915 11:18:41.555281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2916 11:18:41.555391 ==
2917 11:18:41.558909 RX Vref Scan: 0
2918 11:18:41.558989
2919 11:18:41.559052 RX Vref 0 -> 0, step: 1
2920 11:18:41.559110
2921 11:18:41.562148 RX Delay -40 -> 252, step: 8
2922 11:18:41.565636 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2923 11:18:41.571971 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
2924 11:18:41.575470 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2925 11:18:41.578714 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2926 11:18:41.582410 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2927 11:18:41.585644 iDelay=200, Bit 5, Center 107 (32 ~ 183) 152
2928 11:18:41.592393 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2929 11:18:41.596048 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2930 11:18:41.598905 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2931 11:18:41.602833 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2932 11:18:41.605338 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2933 11:18:41.612477 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
2934 11:18:41.615638 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2935 11:18:41.618568 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2936 11:18:41.622222 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2937 11:18:41.625790 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2938 11:18:41.628755 ==
2939 11:18:41.628837 Dram Type= 6, Freq= 0, CH_0, rank 1
2940 11:18:41.635535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2941 11:18:41.635616 ==
2942 11:18:41.635679 DQS Delay:
2943 11:18:41.639020 DQS0 = 0, DQS1 = 0
2944 11:18:41.639100 DQM Delay:
2945 11:18:41.642164 DQM0 = 115, DQM1 = 106
2946 11:18:41.642245 DQ Delay:
2947 11:18:41.645592 DQ0 =115, DQ1 =115, DQ2 =111, DQ3 =115
2948 11:18:41.649219 DQ4 =115, DQ5 =107, DQ6 =123, DQ7 =123
2949 11:18:41.652093 DQ8 =95, DQ9 =95, DQ10 =103, DQ11 =99
2950 11:18:41.655380 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2951 11:18:41.655475
2952 11:18:41.655537
2953 11:18:41.655596 ==
2954 11:18:41.658902 Dram Type= 6, Freq= 0, CH_0, rank 1
2955 11:18:41.661956 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2956 11:18:41.665294 ==
2957 11:18:41.665375
2958 11:18:41.665437
2959 11:18:41.665495 TX Vref Scan disable
2960 11:18:41.668917 == TX Byte 0 ==
2961 11:18:41.672213 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2962 11:18:41.675587 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2963 11:18:41.679023 == TX Byte 1 ==
2964 11:18:41.681931 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2965 11:18:41.685248 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2966 11:18:41.688677 ==
2967 11:18:41.688759 Dram Type= 6, Freq= 0, CH_0, rank 1
2968 11:18:41.695134 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2969 11:18:41.695216 ==
2970 11:18:41.706280 TX Vref=22, minBit 5, minWin=25, winSum=426
2971 11:18:41.709556 TX Vref=24, minBit 0, minWin=26, winSum=430
2972 11:18:41.713058 TX Vref=26, minBit 0, minWin=26, winSum=437
2973 11:18:41.716683 TX Vref=28, minBit 7, minWin=26, winSum=437
2974 11:18:41.720050 TX Vref=30, minBit 0, minWin=27, winSum=439
2975 11:18:41.722908 TX Vref=32, minBit 0, minWin=27, winSum=440
2976 11:18:41.729735 [TxChooseVref] Worse bit 0, Min win 27, Win sum 440, Final Vref 32
2977 11:18:41.729817
2978 11:18:41.733068 Final TX Range 1 Vref 32
2979 11:18:41.733150
2980 11:18:41.733213 ==
2981 11:18:41.736704 Dram Type= 6, Freq= 0, CH_0, rank 1
2982 11:18:41.740103 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2983 11:18:41.740185 ==
2984 11:18:41.740249
2985 11:18:41.740306
2986 11:18:41.743217 TX Vref Scan disable
2987 11:18:41.746872 == TX Byte 0 ==
2988 11:18:41.750342 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2989 11:18:41.753396 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2990 11:18:41.757082 == TX Byte 1 ==
2991 11:18:41.759766 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2992 11:18:41.763324 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2993 11:18:41.763416
2994 11:18:41.766669 [DATLAT]
2995 11:18:41.766748 Freq=1200, CH0 RK1
2996 11:18:41.766812
2997 11:18:41.770097 DATLAT Default: 0xd
2998 11:18:41.770177 0, 0xFFFF, sum = 0
2999 11:18:41.773178 1, 0xFFFF, sum = 0
3000 11:18:41.773259 2, 0xFFFF, sum = 0
3001 11:18:41.776813 3, 0xFFFF, sum = 0
3002 11:18:41.776894 4, 0xFFFF, sum = 0
3003 11:18:41.780183 5, 0xFFFF, sum = 0
3004 11:18:41.780265 6, 0xFFFF, sum = 0
3005 11:18:41.783475 7, 0xFFFF, sum = 0
3006 11:18:41.783557 8, 0xFFFF, sum = 0
3007 11:18:41.786957 9, 0xFFFF, sum = 0
3008 11:18:41.787038 10, 0xFFFF, sum = 0
3009 11:18:41.790162 11, 0xFFFF, sum = 0
3010 11:18:41.790256 12, 0x0, sum = 1
3011 11:18:41.793497 13, 0x0, sum = 2
3012 11:18:41.793579 14, 0x0, sum = 3
3013 11:18:41.796774 15, 0x0, sum = 4
3014 11:18:41.796856 best_step = 13
3015 11:18:41.796919
3016 11:18:41.796976 ==
3017 11:18:41.800194 Dram Type= 6, Freq= 0, CH_0, rank 1
3018 11:18:41.806448 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3019 11:18:41.806532 ==
3020 11:18:41.806597 RX Vref Scan: 0
3021 11:18:41.806656
3022 11:18:41.810092 RX Vref 0 -> 0, step: 1
3023 11:18:41.810176
3024 11:18:41.813084 RX Delay -21 -> 252, step: 4
3025 11:18:41.816669 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3026 11:18:41.819928 iDelay=195, Bit 1, Center 114 (43 ~ 186) 144
3027 11:18:41.826436 iDelay=195, Bit 2, Center 110 (39 ~ 182) 144
3028 11:18:41.830108 iDelay=195, Bit 3, Center 114 (43 ~ 186) 144
3029 11:18:41.833266 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3030 11:18:41.836366 iDelay=195, Bit 5, Center 104 (35 ~ 174) 140
3031 11:18:41.840001 iDelay=195, Bit 6, Center 122 (51 ~ 194) 144
3032 11:18:41.846875 iDelay=195, Bit 7, Center 122 (51 ~ 194) 144
3033 11:18:41.850397 iDelay=195, Bit 8, Center 96 (27 ~ 166) 140
3034 11:18:41.853354 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3035 11:18:41.856428 iDelay=195, Bit 10, Center 108 (39 ~ 178) 140
3036 11:18:41.859791 iDelay=195, Bit 11, Center 96 (31 ~ 162) 132
3037 11:18:41.866510 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3038 11:18:41.869780 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3039 11:18:41.873144 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3040 11:18:41.876719 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3041 11:18:41.876809 ==
3042 11:18:41.879860 Dram Type= 6, Freq= 0, CH_0, rank 1
3043 11:18:41.883516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3044 11:18:41.886798 ==
3045 11:18:41.886883 DQS Delay:
3046 11:18:41.886966 DQS0 = 0, DQS1 = 0
3047 11:18:41.890241 DQM Delay:
3048 11:18:41.890324 DQM0 = 114, DQM1 = 105
3049 11:18:41.893679 DQ Delay:
3050 11:18:41.896892 DQ0 =114, DQ1 =114, DQ2 =110, DQ3 =114
3051 11:18:41.900170 DQ4 =112, DQ5 =104, DQ6 =122, DQ7 =122
3052 11:18:41.903533 DQ8 =96, DQ9 =92, DQ10 =108, DQ11 =96
3053 11:18:41.906584 DQ12 =110, DQ13 =110, DQ14 =116, DQ15 =114
3054 11:18:41.906669
3055 11:18:41.906753
3056 11:18:41.913083 [DQSOSCAuto] RK1, (LSB)MR18= 0x2f4, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 409 ps
3057 11:18:41.916717 CH0 RK1: MR19=403, MR18=2F4
3058 11:18:41.923243 CH0_RK1: MR19=0x403, MR18=0x2F4, DQSOSC=409, MR23=63, INC=39, DEC=26
3059 11:18:41.927030 [RxdqsGatingPostProcess] freq 1200
3060 11:18:41.930017 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3061 11:18:41.933985 best DQS0 dly(2T, 0.5T) = (0, 12)
3062 11:18:41.936717 best DQS1 dly(2T, 0.5T) = (0, 12)
3063 11:18:41.939834 best DQS0 P1 dly(2T, 0.5T) = (1, 0)
3064 11:18:41.943054 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3065 11:18:41.946575 best DQS0 dly(2T, 0.5T) = (0, 11)
3066 11:18:41.950324 best DQS1 dly(2T, 0.5T) = (0, 12)
3067 11:18:41.953207 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3068 11:18:41.956418 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3069 11:18:41.959866 Pre-setting of DQS Precalculation
3070 11:18:41.963620 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3071 11:18:41.963703 ==
3072 11:18:41.966618 Dram Type= 6, Freq= 0, CH_1, rank 0
3073 11:18:41.972995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3074 11:18:41.973081 ==
3075 11:18:41.976521 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3076 11:18:41.983087 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3077 11:18:41.991902 [CA 0] Center 38 (8~68) winsize 61
3078 11:18:41.995266 [CA 1] Center 38 (8~68) winsize 61
3079 11:18:41.998795 [CA 2] Center 35 (5~65) winsize 61
3080 11:18:42.002165 [CA 3] Center 34 (4~65) winsize 62
3081 11:18:42.005471 [CA 4] Center 34 (4~65) winsize 62
3082 11:18:42.008496 [CA 5] Center 33 (3~64) winsize 62
3083 11:18:42.008602
3084 11:18:42.011893 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3085 11:18:42.011990
3086 11:18:42.015275 [CATrainingPosCal] consider 1 rank data
3087 11:18:42.018996 u2DelayCellTimex100 = 270/100 ps
3088 11:18:42.021959 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3089 11:18:42.025743 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3090 11:18:42.032066 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3091 11:18:42.035193 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3092 11:18:42.038608 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3093 11:18:42.041965 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3094 11:18:42.042051
3095 11:18:42.045506 CA PerBit enable=1, Macro0, CA PI delay=33
3096 11:18:42.045590
3097 11:18:42.048709 [CBTSetCACLKResult] CA Dly = 33
3098 11:18:42.048805 CS Dly: 6 (0~37)
3099 11:18:42.048872 ==
3100 11:18:42.051880 Dram Type= 6, Freq= 0, CH_1, rank 1
3101 11:18:42.058863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3102 11:18:42.058950 ==
3103 11:18:42.061913 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3104 11:18:42.068390 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
3105 11:18:42.077776 [CA 0] Center 38 (8~68) winsize 61
3106 11:18:42.081126 [CA 1] Center 38 (8~68) winsize 61
3107 11:18:42.084000 [CA 2] Center 35 (5~65) winsize 61
3108 11:18:42.087792 [CA 3] Center 34 (4~65) winsize 62
3109 11:18:42.090570 [CA 4] Center 34 (4~65) winsize 62
3110 11:18:42.094254 [CA 5] Center 33 (3~63) winsize 61
3111 11:18:42.094341
3112 11:18:42.097520 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3113 11:18:42.097604
3114 11:18:42.100648 [CATrainingPosCal] consider 2 rank data
3115 11:18:42.104011 u2DelayCellTimex100 = 270/100 ps
3116 11:18:42.107669 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3117 11:18:42.114193 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3118 11:18:42.117648 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3119 11:18:42.120947 CA3 delay=34 (4~65),Diff = 1 PI (4 cell)
3120 11:18:42.124229 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3121 11:18:42.127673 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3122 11:18:42.127765
3123 11:18:42.130583 CA PerBit enable=1, Macro0, CA PI delay=33
3124 11:18:42.130667
3125 11:18:42.134166 [CBTSetCACLKResult] CA Dly = 33
3126 11:18:42.134252 CS Dly: 7 (0~40)
3127 11:18:42.134316
3128 11:18:42.137501 ----->DramcWriteLeveling(PI) begin...
3129 11:18:42.140719 ==
3130 11:18:42.140831 Dram Type= 6, Freq= 0, CH_1, rank 0
3131 11:18:42.147647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3132 11:18:42.147744 ==
3133 11:18:42.151052 Write leveling (Byte 0): 26 => 26
3134 11:18:42.153996 Write leveling (Byte 1): 27 => 27
3135 11:18:42.157339 DramcWriteLeveling(PI) end<-----
3136 11:18:42.157427
3137 11:18:42.157490 ==
3138 11:18:42.161002 Dram Type= 6, Freq= 0, CH_1, rank 0
3139 11:18:42.164303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3140 11:18:42.164389 ==
3141 11:18:42.167691 [Gating] SW mode calibration
3142 11:18:42.174303 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3143 11:18:42.177257 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3144 11:18:42.183959 0 15 0 | B1->B0 | 2424 2322 | 0 1 | (0 0) (0 0)
3145 11:18:42.187176 0 15 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3146 11:18:42.190824 0 15 8 | B1->B0 | 3534 3434 | 1 1 | (0 0) (1 1)
3147 11:18:42.197406 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3148 11:18:42.200727 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3149 11:18:42.203867 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3150 11:18:42.210770 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3151 11:18:42.213848 0 15 28 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 0)
3152 11:18:42.217283 1 0 0 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
3153 11:18:42.223937 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3154 11:18:42.227295 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3155 11:18:42.230394 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3156 11:18:42.236949 1 0 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3157 11:18:42.240812 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3158 11:18:42.243818 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3159 11:18:42.250217 1 0 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3160 11:18:42.253955 1 1 0 | B1->B0 | 4444 3737 | 0 1 | (0 0) (0 0)
3161 11:18:42.257174 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3162 11:18:42.263946 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3163 11:18:42.267164 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3164 11:18:42.270589 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3165 11:18:42.277671 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3166 11:18:42.281002 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3167 11:18:42.284004 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3168 11:18:42.287284 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3169 11:18:42.293992 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 11:18:42.297179 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 11:18:42.300437 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 11:18:42.307371 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 11:18:42.310807 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3174 11:18:42.314309 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3175 11:18:42.320530 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3176 11:18:42.323999 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3177 11:18:42.327612 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3178 11:18:42.334279 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3179 11:18:42.337347 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3180 11:18:42.340724 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3181 11:18:42.347282 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3182 11:18:42.351040 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3183 11:18:42.353916 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3184 11:18:42.360599 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3185 11:18:42.360702 Total UI for P1: 0, mck2ui 16
3186 11:18:42.364254 best dqsien dly found for B0: ( 1, 3, 28)
3187 11:18:42.367206 Total UI for P1: 0, mck2ui 16
3188 11:18:42.370589 best dqsien dly found for B1: ( 1, 3, 28)
3189 11:18:42.373949 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3190 11:18:42.380565 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3191 11:18:42.380663
3192 11:18:42.384160 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3193 11:18:42.387612 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3194 11:18:42.390887 [Gating] SW calibration Done
3195 11:18:42.390975 ==
3196 11:18:42.394580 Dram Type= 6, Freq= 0, CH_1, rank 0
3197 11:18:42.397186 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3198 11:18:42.397271 ==
3199 11:18:42.397336 RX Vref Scan: 0
3200 11:18:42.400741
3201 11:18:42.400826 RX Vref 0 -> 0, step: 1
3202 11:18:42.400892
3203 11:18:42.404274 RX Delay -40 -> 252, step: 8
3204 11:18:42.407620 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3205 11:18:42.410642 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3206 11:18:42.417176 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3207 11:18:42.420753 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3208 11:18:42.424336 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3209 11:18:42.427940 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3210 11:18:42.430658 iDelay=200, Bit 6, Center 123 (56 ~ 191) 136
3211 11:18:42.437732 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3212 11:18:42.440882 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3213 11:18:42.444062 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3214 11:18:42.447422 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
3215 11:18:42.450557 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3216 11:18:42.457582 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3217 11:18:42.461108 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3218 11:18:42.463980 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3219 11:18:42.467721 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3220 11:18:42.467807 ==
3221 11:18:42.470995 Dram Type= 6, Freq= 0, CH_1, rank 0
3222 11:18:42.477561 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3223 11:18:42.477652 ==
3224 11:18:42.477717 DQS Delay:
3225 11:18:42.477776 DQS0 = 0, DQS1 = 0
3226 11:18:42.480766 DQM Delay:
3227 11:18:42.480847 DQM0 = 116, DQM1 = 108
3228 11:18:42.484337 DQ Delay:
3229 11:18:42.487067 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =119
3230 11:18:42.490459 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =115
3231 11:18:42.493833 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
3232 11:18:42.497409 DQ12 =123, DQ13 =115, DQ14 =111, DQ15 =111
3233 11:18:42.497494
3234 11:18:42.497557
3235 11:18:42.497616 ==
3236 11:18:42.501123 Dram Type= 6, Freq= 0, CH_1, rank 0
3237 11:18:42.504158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3238 11:18:42.504241 ==
3239 11:18:42.504305
3240 11:18:42.507253
3241 11:18:42.507344 TX Vref Scan disable
3242 11:18:42.511025 == TX Byte 0 ==
3243 11:18:42.513992 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3244 11:18:42.517326 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3245 11:18:42.520466 == TX Byte 1 ==
3246 11:18:42.523996 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3247 11:18:42.527482 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3248 11:18:42.527588 ==
3249 11:18:42.530489 Dram Type= 6, Freq= 0, CH_1, rank 0
3250 11:18:42.537260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3251 11:18:42.537354 ==
3252 11:18:42.547602 TX Vref=22, minBit 2, minWin=25, winSum=409
3253 11:18:42.550678 TX Vref=24, minBit 1, minWin=25, winSum=414
3254 11:18:42.554273 TX Vref=26, minBit 8, minWin=25, winSum=420
3255 11:18:42.557461 TX Vref=28, minBit 0, minWin=26, winSum=423
3256 11:18:42.560958 TX Vref=30, minBit 1, minWin=26, winSum=426
3257 11:18:42.564643 TX Vref=32, minBit 0, minWin=26, winSum=426
3258 11:18:42.570928 [TxChooseVref] Worse bit 1, Min win 26, Win sum 426, Final Vref 30
3259 11:18:42.571043
3260 11:18:42.573968 Final TX Range 1 Vref 30
3261 11:18:42.574053
3262 11:18:42.574117 ==
3263 11:18:42.577697 Dram Type= 6, Freq= 0, CH_1, rank 0
3264 11:18:42.580891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3265 11:18:42.580975 ==
3266 11:18:42.581041
3267 11:18:42.584357
3268 11:18:42.584439 TX Vref Scan disable
3269 11:18:42.587205 == TX Byte 0 ==
3270 11:18:42.590813 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3271 11:18:42.594193 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3272 11:18:42.597640 == TX Byte 1 ==
3273 11:18:42.600488 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3274 11:18:42.603991 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3275 11:18:42.607265
3276 11:18:42.607378 [DATLAT]
3277 11:18:42.607474 Freq=1200, CH1 RK0
3278 11:18:42.607565
3279 11:18:42.610865 DATLAT Default: 0xd
3280 11:18:42.610949 0, 0xFFFF, sum = 0
3281 11:18:42.613732 1, 0xFFFF, sum = 0
3282 11:18:42.613815 2, 0xFFFF, sum = 0
3283 11:18:42.617187 3, 0xFFFF, sum = 0
3284 11:18:42.620680 4, 0xFFFF, sum = 0
3285 11:18:42.620765 5, 0xFFFF, sum = 0
3286 11:18:42.623686 6, 0xFFFF, sum = 0
3287 11:18:42.623771 7, 0xFFFF, sum = 0
3288 11:18:42.627298 8, 0xFFFF, sum = 0
3289 11:18:42.627447 9, 0xFFFF, sum = 0
3290 11:18:42.630500 10, 0xFFFF, sum = 0
3291 11:18:42.630585 11, 0xFFFF, sum = 0
3292 11:18:42.634339 12, 0x0, sum = 1
3293 11:18:42.634428 13, 0x0, sum = 2
3294 11:18:42.637434 14, 0x0, sum = 3
3295 11:18:42.637522 15, 0x0, sum = 4
3296 11:18:42.637586 best_step = 13
3297 11:18:42.640932
3298 11:18:42.641013 ==
3299 11:18:42.643701 Dram Type= 6, Freq= 0, CH_1, rank 0
3300 11:18:42.647003 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3301 11:18:42.647088 ==
3302 11:18:42.647152 RX Vref Scan: 1
3303 11:18:42.647218
3304 11:18:42.650429 Set Vref Range= 32 -> 127
3305 11:18:42.650550
3306 11:18:42.653547 RX Vref 32 -> 127, step: 1
3307 11:18:42.653627
3308 11:18:42.657416 RX Delay -21 -> 252, step: 4
3309 11:18:42.657509
3310 11:18:42.660215 Set Vref, RX VrefLevel [Byte0]: 32
3311 11:18:42.663796 [Byte1]: 32
3312 11:18:42.663877
3313 11:18:42.667032 Set Vref, RX VrefLevel [Byte0]: 33
3314 11:18:42.670507 [Byte1]: 33
3315 11:18:42.673781
3316 11:18:42.673862 Set Vref, RX VrefLevel [Byte0]: 34
3317 11:18:42.676871 [Byte1]: 34
3318 11:18:42.681749
3319 11:18:42.681831 Set Vref, RX VrefLevel [Byte0]: 35
3320 11:18:42.684729 [Byte1]: 35
3321 11:18:42.689605
3322 11:18:42.689690 Set Vref, RX VrefLevel [Byte0]: 36
3323 11:18:42.692894 [Byte1]: 36
3324 11:18:42.697990
3325 11:18:42.698076 Set Vref, RX VrefLevel [Byte0]: 37
3326 11:18:42.700503 [Byte1]: 37
3327 11:18:42.705272
3328 11:18:42.705358 Set Vref, RX VrefLevel [Byte0]: 38
3329 11:18:42.708550 [Byte1]: 38
3330 11:18:42.713152
3331 11:18:42.713242 Set Vref, RX VrefLevel [Byte0]: 39
3332 11:18:42.716332 [Byte1]: 39
3333 11:18:42.720932
3334 11:18:42.721019 Set Vref, RX VrefLevel [Byte0]: 40
3335 11:18:42.724529 [Byte1]: 40
3336 11:18:42.729196
3337 11:18:42.729284 Set Vref, RX VrefLevel [Byte0]: 41
3338 11:18:42.732054 [Byte1]: 41
3339 11:18:42.736857
3340 11:18:42.736945 Set Vref, RX VrefLevel [Byte0]: 42
3341 11:18:42.740433 [Byte1]: 42
3342 11:18:42.744740
3343 11:18:42.744839 Set Vref, RX VrefLevel [Byte0]: 43
3344 11:18:42.748389 [Byte1]: 43
3345 11:18:42.753228
3346 11:18:42.753318 Set Vref, RX VrefLevel [Byte0]: 44
3347 11:18:42.755897 [Byte1]: 44
3348 11:18:42.760992
3349 11:18:42.761080 Set Vref, RX VrefLevel [Byte0]: 45
3350 11:18:42.764132 [Byte1]: 45
3351 11:18:42.768676
3352 11:18:42.768764 Set Vref, RX VrefLevel [Byte0]: 46
3353 11:18:42.771902 [Byte1]: 46
3354 11:18:42.777035
3355 11:18:42.777126 Set Vref, RX VrefLevel [Byte0]: 47
3356 11:18:42.779946 [Byte1]: 47
3357 11:18:42.784590
3358 11:18:42.784675 Set Vref, RX VrefLevel [Byte0]: 48
3359 11:18:42.787864 [Byte1]: 48
3360 11:18:42.792321
3361 11:18:42.792408 Set Vref, RX VrefLevel [Byte0]: 49
3362 11:18:42.795813 [Byte1]: 49
3363 11:18:42.800203
3364 11:18:42.800287 Set Vref, RX VrefLevel [Byte0]: 50
3365 11:18:42.804061 [Byte1]: 50
3366 11:18:42.808225
3367 11:18:42.808315 Set Vref, RX VrefLevel [Byte0]: 51
3368 11:18:42.811558 [Byte1]: 51
3369 11:18:42.816314
3370 11:18:42.816402 Set Vref, RX VrefLevel [Byte0]: 52
3371 11:18:42.819469 [Byte1]: 52
3372 11:18:42.824118
3373 11:18:42.824205 Set Vref, RX VrefLevel [Byte0]: 53
3374 11:18:42.827700 [Byte1]: 53
3375 11:18:42.832139
3376 11:18:42.832229 Set Vref, RX VrefLevel [Byte0]: 54
3377 11:18:42.835462 [Byte1]: 54
3378 11:18:42.840004
3379 11:18:42.840093 Set Vref, RX VrefLevel [Byte0]: 55
3380 11:18:42.843044 [Byte1]: 55
3381 11:18:42.848003
3382 11:18:42.848092 Set Vref, RX VrefLevel [Byte0]: 56
3383 11:18:42.851280 [Byte1]: 56
3384 11:18:42.856524
3385 11:18:42.856614 Set Vref, RX VrefLevel [Byte0]: 57
3386 11:18:42.859037 [Byte1]: 57
3387 11:18:42.863554
3388 11:18:42.863641 Set Vref, RX VrefLevel [Byte0]: 58
3389 11:18:42.866911 [Byte1]: 58
3390 11:18:42.871482
3391 11:18:42.871572 Set Vref, RX VrefLevel [Byte0]: 59
3392 11:18:42.874818 [Byte1]: 59
3393 11:18:42.879859
3394 11:18:42.879981 Set Vref, RX VrefLevel [Byte0]: 60
3395 11:18:42.883182 [Byte1]: 60
3396 11:18:42.887289
3397 11:18:42.887400 Set Vref, RX VrefLevel [Byte0]: 61
3398 11:18:42.891085 [Byte1]: 61
3399 11:18:42.895266
3400 11:18:42.895361 Set Vref, RX VrefLevel [Byte0]: 62
3401 11:18:42.898800 [Byte1]: 62
3402 11:18:42.903616
3403 11:18:42.903704 Set Vref, RX VrefLevel [Byte0]: 63
3404 11:18:42.906606 [Byte1]: 63
3405 11:18:42.911257
3406 11:18:42.911419 Set Vref, RX VrefLevel [Byte0]: 64
3407 11:18:42.914565 [Byte1]: 64
3408 11:18:42.919414
3409 11:18:42.919512 Set Vref, RX VrefLevel [Byte0]: 65
3410 11:18:42.922653 [Byte1]: 65
3411 11:18:42.927510
3412 11:18:42.927600 Set Vref, RX VrefLevel [Byte0]: 66
3413 11:18:42.930152 [Byte1]: 66
3414 11:18:42.935099
3415 11:18:42.938000 Set Vref, RX VrefLevel [Byte0]: 67
3416 11:18:42.941421 [Byte1]: 67
3417 11:18:42.941508
3418 11:18:42.944650 Set Vref, RX VrefLevel [Byte0]: 68
3419 11:18:42.948034 [Byte1]: 68
3420 11:18:42.948120
3421 11:18:42.951317 Set Vref, RX VrefLevel [Byte0]: 69
3422 11:18:42.954821 [Byte1]: 69
3423 11:18:42.958607
3424 11:18:42.958694 Final RX Vref Byte 0 = 59 to rank0
3425 11:18:42.962122 Final RX Vref Byte 1 = 48 to rank0
3426 11:18:42.965517 Final RX Vref Byte 0 = 59 to rank1
3427 11:18:42.968708 Final RX Vref Byte 1 = 48 to rank1==
3428 11:18:42.971933 Dram Type= 6, Freq= 0, CH_1, rank 0
3429 11:18:42.978997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3430 11:18:42.979103 ==
3431 11:18:42.979186 DQS Delay:
3432 11:18:42.979274 DQS0 = 0, DQS1 = 0
3433 11:18:42.981890 DQM Delay:
3434 11:18:42.981991 DQM0 = 116, DQM1 = 107
3435 11:18:42.985367 DQ Delay:
3436 11:18:42.988915 DQ0 =118, DQ1 =110, DQ2 =106, DQ3 =116
3437 11:18:42.992160 DQ4 =116, DQ5 =124, DQ6 =126, DQ7 =114
3438 11:18:42.995119 DQ8 =94, DQ9 =94, DQ10 =110, DQ11 =102
3439 11:18:42.998471 DQ12 =116, DQ13 =116, DQ14 =114, DQ15 =114
3440 11:18:42.998557
3441 11:18:42.998620
3442 11:18:43.008681 [DQSOSCAuto] RK0, (LSB)MR18= 0xfce0, (MSB)MR19= 0x303, tDQSOscB0 = 423 ps tDQSOscB1 = 411 ps
3443 11:18:43.008805 CH1 RK0: MR19=303, MR18=FCE0
3444 11:18:43.015130 CH1_RK0: MR19=0x303, MR18=0xFCE0, DQSOSC=411, MR23=63, INC=38, DEC=25
3445 11:18:43.015240
3446 11:18:43.018770 ----->DramcWriteLeveling(PI) begin...
3447 11:18:43.018858 ==
3448 11:18:43.021697 Dram Type= 6, Freq= 0, CH_1, rank 1
3449 11:18:43.028430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3450 11:18:43.028524 ==
3451 11:18:43.032104 Write leveling (Byte 0): 25 => 25
3452 11:18:43.032188 Write leveling (Byte 1): 27 => 27
3453 11:18:43.034865 DramcWriteLeveling(PI) end<-----
3454 11:18:43.034946
3455 11:18:43.038548 ==
3456 11:18:43.038633 Dram Type= 6, Freq= 0, CH_1, rank 1
3457 11:18:43.045086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3458 11:18:43.045194 ==
3459 11:18:43.048159 [Gating] SW mode calibration
3460 11:18:43.054689 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3461 11:18:43.058309 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3462 11:18:43.065090 0 15 0 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
3463 11:18:43.068287 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3464 11:18:43.071065 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3465 11:18:43.077946 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3466 11:18:43.081348 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3467 11:18:43.084410 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3468 11:18:43.090962 0 15 24 | B1->B0 | 3333 2929 | 1 0 | (1 1) (1 0)
3469 11:18:43.094851 0 15 28 | B1->B0 | 2727 2323 | 0 0 | (1 0) (0 0)
3470 11:18:43.097909 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3471 11:18:43.104347 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3472 11:18:43.107869 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3473 11:18:43.110982 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3474 11:18:43.117664 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3475 11:18:43.121226 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3476 11:18:43.124559 1 0 24 | B1->B0 | 2424 3636 | 0 0 | (0 0) (1 1)
3477 11:18:43.127714 1 0 28 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
3478 11:18:43.134335 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3479 11:18:43.137879 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3480 11:18:43.144297 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3481 11:18:43.147917 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3482 11:18:43.151160 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3483 11:18:43.154558 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3484 11:18:43.160917 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3485 11:18:43.164522 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3486 11:18:43.167885 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3487 11:18:43.174083 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3488 11:18:43.177460 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3489 11:18:43.180707 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3490 11:18:43.187262 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3491 11:18:43.191116 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3492 11:18:43.194235 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3493 11:18:43.201006 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3494 11:18:43.204006 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3495 11:18:43.207642 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3496 11:18:43.214272 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3497 11:18:43.217088 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3498 11:18:43.220723 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3499 11:18:43.227286 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3500 11:18:43.230379 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3501 11:18:43.234047 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3502 11:18:43.237389 Total UI for P1: 0, mck2ui 16
3503 11:18:43.240546 best dqsien dly found for B0: ( 1, 3, 22)
3504 11:18:43.246997 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3505 11:18:43.247105 Total UI for P1: 0, mck2ui 16
3506 11:18:43.254079 best dqsien dly found for B1: ( 1, 3, 26)
3507 11:18:43.256978 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3508 11:18:43.260369 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3509 11:18:43.260460
3510 11:18:43.263481 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3511 11:18:43.266722 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3512 11:18:43.270459 [Gating] SW calibration Done
3513 11:18:43.270552 ==
3514 11:18:43.274176 Dram Type= 6, Freq= 0, CH_1, rank 1
3515 11:18:43.277296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3516 11:18:43.277384 ==
3517 11:18:43.280531 RX Vref Scan: 0
3518 11:18:43.280616
3519 11:18:43.280681 RX Vref 0 -> 0, step: 1
3520 11:18:43.280739
3521 11:18:43.283437 RX Delay -40 -> 252, step: 8
3522 11:18:43.287249 iDelay=192, Bit 0, Center 115 (40 ~ 191) 152
3523 11:18:43.293266 iDelay=192, Bit 1, Center 111 (40 ~ 183) 144
3524 11:18:43.296858 iDelay=192, Bit 2, Center 103 (32 ~ 175) 144
3525 11:18:43.300171 iDelay=192, Bit 3, Center 115 (48 ~ 183) 136
3526 11:18:43.303760 iDelay=192, Bit 4, Center 111 (40 ~ 183) 144
3527 11:18:43.306820 iDelay=192, Bit 5, Center 123 (56 ~ 191) 136
3528 11:18:43.313556 iDelay=192, Bit 6, Center 119 (48 ~ 191) 144
3529 11:18:43.316714 iDelay=192, Bit 7, Center 107 (40 ~ 175) 136
3530 11:18:43.319964 iDelay=192, Bit 8, Center 99 (24 ~ 175) 152
3531 11:18:43.323657 iDelay=192, Bit 9, Center 99 (32 ~ 167) 136
3532 11:18:43.326907 iDelay=192, Bit 10, Center 111 (40 ~ 183) 144
3533 11:18:43.333283 iDelay=192, Bit 11, Center 103 (32 ~ 175) 144
3534 11:18:43.336436 iDelay=192, Bit 12, Center 115 (48 ~ 183) 136
3535 11:18:43.339916 iDelay=192, Bit 13, Center 119 (48 ~ 191) 144
3536 11:18:43.343628 iDelay=192, Bit 14, Center 115 (48 ~ 183) 136
3537 11:18:43.346772 iDelay=192, Bit 15, Center 115 (48 ~ 183) 136
3538 11:18:43.349769 ==
3539 11:18:43.353613 Dram Type= 6, Freq= 0, CH_1, rank 1
3540 11:18:43.356377 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3541 11:18:43.356468 ==
3542 11:18:43.356533 DQS Delay:
3543 11:18:43.360069 DQS0 = 0, DQS1 = 0
3544 11:18:43.360154 DQM Delay:
3545 11:18:43.363287 DQM0 = 113, DQM1 = 109
3546 11:18:43.363416 DQ Delay:
3547 11:18:43.366435 DQ0 =115, DQ1 =111, DQ2 =103, DQ3 =115
3548 11:18:43.370011 DQ4 =111, DQ5 =123, DQ6 =119, DQ7 =107
3549 11:18:43.372931 DQ8 =99, DQ9 =99, DQ10 =111, DQ11 =103
3550 11:18:43.376130 DQ12 =115, DQ13 =119, DQ14 =115, DQ15 =115
3551 11:18:43.376231
3552 11:18:43.376298
3553 11:18:43.376358 ==
3554 11:18:43.379795 Dram Type= 6, Freq= 0, CH_1, rank 1
3555 11:18:43.386321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3556 11:18:43.386415 ==
3557 11:18:43.386483
3558 11:18:43.386542
3559 11:18:43.386602 TX Vref Scan disable
3560 11:18:43.389845 == TX Byte 0 ==
3561 11:18:43.393268 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3562 11:18:43.399875 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3563 11:18:43.399979 == TX Byte 1 ==
3564 11:18:43.403152 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3565 11:18:43.409543 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3566 11:18:43.409649 ==
3567 11:18:43.413113 Dram Type= 6, Freq= 0, CH_1, rank 1
3568 11:18:43.416167 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3569 11:18:43.416256 ==
3570 11:18:43.427576 TX Vref=22, minBit 0, minWin=25, winSum=414
3571 11:18:43.431246 TX Vref=24, minBit 1, minWin=25, winSum=418
3572 11:18:43.434312 TX Vref=26, minBit 3, minWin=25, winSum=426
3573 11:18:43.437872 TX Vref=28, minBit 9, minWin=26, winSum=429
3574 11:18:43.441134 TX Vref=30, minBit 9, minWin=26, winSum=433
3575 11:18:43.447497 TX Vref=32, minBit 0, minWin=27, winSum=435
3576 11:18:43.450836 [TxChooseVref] Worse bit 0, Min win 27, Win sum 435, Final Vref 32
3577 11:18:43.450930
3578 11:18:43.454130 Final TX Range 1 Vref 32
3579 11:18:43.454215
3580 11:18:43.454278 ==
3581 11:18:43.457977 Dram Type= 6, Freq= 0, CH_1, rank 1
3582 11:18:43.460794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3583 11:18:43.460881 ==
3584 11:18:43.464270
3585 11:18:43.464361
3586 11:18:43.464465 TX Vref Scan disable
3587 11:18:43.467768 == TX Byte 0 ==
3588 11:18:43.470651 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3589 11:18:43.477308 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3590 11:18:43.477414 == TX Byte 1 ==
3591 11:18:43.481257 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3592 11:18:43.487544 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3593 11:18:43.487643
3594 11:18:43.487711 [DATLAT]
3595 11:18:43.487797 Freq=1200, CH1 RK1
3596 11:18:43.487889
3597 11:18:43.490778 DATLAT Default: 0xd
3598 11:18:43.490860 0, 0xFFFF, sum = 0
3599 11:18:43.494430 1, 0xFFFF, sum = 0
3600 11:18:43.497146 2, 0xFFFF, sum = 0
3601 11:18:43.497233 3, 0xFFFF, sum = 0
3602 11:18:43.500416 4, 0xFFFF, sum = 0
3603 11:18:43.500502 5, 0xFFFF, sum = 0
3604 11:18:43.503630 6, 0xFFFF, sum = 0
3605 11:18:43.503713 7, 0xFFFF, sum = 0
3606 11:18:43.507320 8, 0xFFFF, sum = 0
3607 11:18:43.507443 9, 0xFFFF, sum = 0
3608 11:18:43.510815 10, 0xFFFF, sum = 0
3609 11:18:43.510933 11, 0xFFFF, sum = 0
3610 11:18:43.514210 12, 0x0, sum = 1
3611 11:18:43.514293 13, 0x0, sum = 2
3612 11:18:43.517109 14, 0x0, sum = 3
3613 11:18:43.517192 15, 0x0, sum = 4
3614 11:18:43.520393 best_step = 13
3615 11:18:43.520476
3616 11:18:43.520540 ==
3617 11:18:43.524067 Dram Type= 6, Freq= 0, CH_1, rank 1
3618 11:18:43.527328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3619 11:18:43.527456 ==
3620 11:18:43.527520 RX Vref Scan: 0
3621 11:18:43.527578
3622 11:18:43.530623 RX Vref 0 -> 0, step: 1
3623 11:18:43.530705
3624 11:18:43.533861 RX Delay -21 -> 252, step: 4
3625 11:18:43.537353 iDelay=191, Bit 0, Center 114 (47 ~ 182) 136
3626 11:18:43.543553 iDelay=191, Bit 1, Center 110 (43 ~ 178) 136
3627 11:18:43.547322 iDelay=191, Bit 2, Center 106 (43 ~ 170) 128
3628 11:18:43.550230 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3629 11:18:43.553695 iDelay=191, Bit 4, Center 116 (51 ~ 182) 132
3630 11:18:43.557025 iDelay=191, Bit 5, Center 124 (59 ~ 190) 132
3631 11:18:43.563633 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3632 11:18:43.567072 iDelay=191, Bit 7, Center 110 (47 ~ 174) 128
3633 11:18:43.570874 iDelay=191, Bit 8, Center 96 (31 ~ 162) 132
3634 11:18:43.573506 iDelay=191, Bit 9, Center 98 (35 ~ 162) 128
3635 11:18:43.576851 iDelay=191, Bit 10, Center 110 (43 ~ 178) 136
3636 11:18:43.583525 iDelay=191, Bit 11, Center 100 (35 ~ 166) 132
3637 11:18:43.586752 iDelay=191, Bit 12, Center 114 (51 ~ 178) 128
3638 11:18:43.590064 iDelay=191, Bit 13, Center 118 (55 ~ 182) 128
3639 11:18:43.593261 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3640 11:18:43.600184 iDelay=191, Bit 15, Center 116 (51 ~ 182) 132
3641 11:18:43.600303 ==
3642 11:18:43.603275 Dram Type= 6, Freq= 0, CH_1, rank 1
3643 11:18:43.606623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3644 11:18:43.606715 ==
3645 11:18:43.606787 DQS Delay:
3646 11:18:43.610051 DQS0 = 0, DQS1 = 0
3647 11:18:43.610173 DQM Delay:
3648 11:18:43.613067 DQM0 = 114, DQM1 = 108
3649 11:18:43.613155 DQ Delay:
3650 11:18:43.616515 DQ0 =114, DQ1 =110, DQ2 =106, DQ3 =112
3651 11:18:43.620324 DQ4 =116, DQ5 =124, DQ6 =122, DQ7 =110
3652 11:18:43.623213 DQ8 =96, DQ9 =98, DQ10 =110, DQ11 =100
3653 11:18:43.626813 DQ12 =114, DQ13 =118, DQ14 =118, DQ15 =116
3654 11:18:43.626901
3655 11:18:43.626966
3656 11:18:43.636449 [DQSOSCAuto] RK1, (LSB)MR18= 0xf5fc, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 414 ps
3657 11:18:43.639420 CH1 RK1: MR19=303, MR18=F5FC
3658 11:18:43.643109 CH1_RK1: MR19=0x303, MR18=0xF5FC, DQSOSC=411, MR23=63, INC=38, DEC=25
3659 11:18:43.646217 [RxdqsGatingPostProcess] freq 1200
3660 11:18:43.653152 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3661 11:18:43.656415 best DQS0 dly(2T, 0.5T) = (0, 11)
3662 11:18:43.659606 best DQS1 dly(2T, 0.5T) = (0, 11)
3663 11:18:43.662954 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3664 11:18:43.666029 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3665 11:18:43.669647 best DQS0 dly(2T, 0.5T) = (0, 11)
3666 11:18:43.673054 best DQS1 dly(2T, 0.5T) = (0, 11)
3667 11:18:43.676480 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3668 11:18:43.679368 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3669 11:18:43.682801 Pre-setting of DQS Precalculation
3670 11:18:43.686337 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3671 11:18:43.692848 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3672 11:18:43.699239 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3673 11:18:43.702525
3674 11:18:43.702629
3675 11:18:43.702695 [Calibration Summary] 2400 Mbps
3676 11:18:43.705795 CH 0, Rank 0
3677 11:18:43.705880 SW Impedance : PASS
3678 11:18:43.709396 DUTY Scan : NO K
3679 11:18:43.712541 ZQ Calibration : PASS
3680 11:18:43.712637 Jitter Meter : NO K
3681 11:18:43.715976 CBT Training : PASS
3682 11:18:43.719763 Write leveling : PASS
3683 11:18:43.719854 RX DQS gating : PASS
3684 11:18:43.722770 RX DQ/DQS(RDDQC) : PASS
3685 11:18:43.725835 TX DQ/DQS : PASS
3686 11:18:43.725920 RX DATLAT : PASS
3687 11:18:43.729342 RX DQ/DQS(Engine): PASS
3688 11:18:43.733179 TX OE : NO K
3689 11:18:43.733269 All Pass.
3690 11:18:43.733333
3691 11:18:43.733390 CH 0, Rank 1
3692 11:18:43.735690 SW Impedance : PASS
3693 11:18:43.739164 DUTY Scan : NO K
3694 11:18:43.739249 ZQ Calibration : PASS
3695 11:18:43.742564 Jitter Meter : NO K
3696 11:18:43.745708 CBT Training : PASS
3697 11:18:43.745794 Write leveling : PASS
3698 11:18:43.749450 RX DQS gating : PASS
3699 11:18:43.749547 RX DQ/DQS(RDDQC) : PASS
3700 11:18:43.752727 TX DQ/DQS : PASS
3701 11:18:43.755551 RX DATLAT : PASS
3702 11:18:43.755637 RX DQ/DQS(Engine): PASS
3703 11:18:43.758978 TX OE : NO K
3704 11:18:43.759064 All Pass.
3705 11:18:43.759129
3706 11:18:43.762585 CH 1, Rank 0
3707 11:18:43.762669 SW Impedance : PASS
3708 11:18:43.765629 DUTY Scan : NO K
3709 11:18:43.768805 ZQ Calibration : PASS
3710 11:18:43.768891 Jitter Meter : NO K
3711 11:18:43.772399 CBT Training : PASS
3712 11:18:43.775541 Write leveling : PASS
3713 11:18:43.775630 RX DQS gating : PASS
3714 11:18:43.779140 RX DQ/DQS(RDDQC) : PASS
3715 11:18:43.782151 TX DQ/DQS : PASS
3716 11:18:43.782240 RX DATLAT : PASS
3717 11:18:43.785668 RX DQ/DQS(Engine): PASS
3718 11:18:43.788863 TX OE : NO K
3719 11:18:43.788963 All Pass.
3720 11:18:43.789029
3721 11:18:43.789087 CH 1, Rank 1
3722 11:18:43.792502 SW Impedance : PASS
3723 11:18:43.795388 DUTY Scan : NO K
3724 11:18:43.795472 ZQ Calibration : PASS
3725 11:18:43.798941 Jitter Meter : NO K
3726 11:18:43.802195 CBT Training : PASS
3727 11:18:43.802298 Write leveling : PASS
3728 11:18:43.805301 RX DQS gating : PASS
3729 11:18:43.805387 RX DQ/DQS(RDDQC) : PASS
3730 11:18:43.808777 TX DQ/DQS : PASS
3731 11:18:43.812122 RX DATLAT : PASS
3732 11:18:43.812218 RX DQ/DQS(Engine): PASS
3733 11:18:43.815665 TX OE : NO K
3734 11:18:43.815753 All Pass.
3735 11:18:43.815818
3736 11:18:43.819057 DramC Write-DBI off
3737 11:18:43.822323 PER_BANK_REFRESH: Hybrid Mode
3738 11:18:43.822411 TX_TRACKING: ON
3739 11:18:43.832003 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3740 11:18:43.835399 [FAST_K] Save calibration result to emmc
3741 11:18:43.838502 dramc_set_vcore_voltage set vcore to 650000
3742 11:18:43.842043 Read voltage for 600, 5
3743 11:18:43.842132 Vio18 = 0
3744 11:18:43.844963 Vcore = 650000
3745 11:18:43.845047 Vdram = 0
3746 11:18:43.845112 Vddq = 0
3747 11:18:43.845171 Vmddr = 0
3748 11:18:43.851565 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3749 11:18:43.858696 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3750 11:18:43.858812 MEM_TYPE=3, freq_sel=19
3751 11:18:43.862325 sv_algorithm_assistance_LP4_1600
3752 11:18:43.864947 ============ PULL DRAM RESETB DOWN ============
3753 11:18:43.871647 ========== PULL DRAM RESETB DOWN end =========
3754 11:18:43.874887 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3755 11:18:43.878104 ===================================
3756 11:18:43.881798 LPDDR4 DRAM CONFIGURATION
3757 11:18:43.885320 ===================================
3758 11:18:43.885417 EX_ROW_EN[0] = 0x0
3759 11:18:43.887939 EX_ROW_EN[1] = 0x0
3760 11:18:43.888024 LP4Y_EN = 0x0
3761 11:18:43.891250 WORK_FSP = 0x0
3762 11:18:43.891369 WL = 0x2
3763 11:18:43.895173 RL = 0x2
3764 11:18:43.895262 BL = 0x2
3765 11:18:43.897970 RPST = 0x0
3766 11:18:43.901399 RD_PRE = 0x0
3767 11:18:43.901488 WR_PRE = 0x1
3768 11:18:43.905084 WR_PST = 0x0
3769 11:18:43.905174 DBI_WR = 0x0
3770 11:18:43.908016 DBI_RD = 0x0
3771 11:18:43.908101 OTF = 0x1
3772 11:18:43.911556 ===================================
3773 11:18:43.914821 ===================================
3774 11:18:43.918329 ANA top config
3775 11:18:43.918422 ===================================
3776 11:18:43.921600 DLL_ASYNC_EN = 0
3777 11:18:43.924875 ALL_SLAVE_EN = 1
3778 11:18:43.927976 NEW_RANK_MODE = 1
3779 11:18:43.931270 DLL_IDLE_MODE = 1
3780 11:18:43.931392 LP45_APHY_COMB_EN = 1
3781 11:18:43.934385 TX_ODT_DIS = 1
3782 11:18:43.938071 NEW_8X_MODE = 1
3783 11:18:43.941646 ===================================
3784 11:18:43.944819 ===================================
3785 11:18:43.948346 data_rate = 1200
3786 11:18:43.951045 CKR = 1
3787 11:18:43.951138 DQ_P2S_RATIO = 8
3788 11:18:43.954316 ===================================
3789 11:18:43.957910 CA_P2S_RATIO = 8
3790 11:18:43.961304 DQ_CA_OPEN = 0
3791 11:18:43.964403 DQ_SEMI_OPEN = 0
3792 11:18:43.967702 CA_SEMI_OPEN = 0
3793 11:18:43.971241 CA_FULL_RATE = 0
3794 11:18:43.971331 DQ_CKDIV4_EN = 1
3795 11:18:43.974815 CA_CKDIV4_EN = 1
3796 11:18:43.978218 CA_PREDIV_EN = 0
3797 11:18:43.981007 PH8_DLY = 0
3798 11:18:43.984463 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3799 11:18:43.987681 DQ_AAMCK_DIV = 4
3800 11:18:43.987771 CA_AAMCK_DIV = 4
3801 11:18:43.990971 CA_ADMCK_DIV = 4
3802 11:18:43.994442 DQ_TRACK_CA_EN = 0
3803 11:18:43.998027 CA_PICK = 600
3804 11:18:44.001073 CA_MCKIO = 600
3805 11:18:44.004394 MCKIO_SEMI = 0
3806 11:18:44.007550 PLL_FREQ = 2288
3807 11:18:44.007637 DQ_UI_PI_RATIO = 32
3808 11:18:44.012001 CA_UI_PI_RATIO = 0
3809 11:18:44.014513 ===================================
3810 11:18:44.017848 ===================================
3811 11:18:44.021391 memory_type:LPDDR4
3812 11:18:44.025011 GP_NUM : 10
3813 11:18:44.025101 SRAM_EN : 1
3814 11:18:44.027827 MD32_EN : 0
3815 11:18:44.030964 ===================================
3816 11:18:44.034031 [ANA_INIT] >>>>>>>>>>>>>>
3817 11:18:44.034121 <<<<<< [CONFIGURE PHASE]: ANA_TX
3818 11:18:44.037385 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3819 11:18:44.040794 ===================================
3820 11:18:44.044323 data_rate = 1200,PCW = 0X5800
3821 11:18:44.047647 ===================================
3822 11:18:44.050569 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3823 11:18:44.057768 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3824 11:18:44.064232 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3825 11:18:44.067323 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3826 11:18:44.070513 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3827 11:18:44.074069 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3828 11:18:44.077753 [ANA_INIT] flow start
3829 11:18:44.077836 [ANA_INIT] PLL >>>>>>>>
3830 11:18:44.080641 [ANA_INIT] PLL <<<<<<<<
3831 11:18:44.084035 [ANA_INIT] MIDPI >>>>>>>>
3832 11:18:44.087150 [ANA_INIT] MIDPI <<<<<<<<
3833 11:18:44.087235 [ANA_INIT] DLL >>>>>>>>
3834 11:18:44.090387 [ANA_INIT] flow end
3835 11:18:44.094042 ============ LP4 DIFF to SE enter ============
3836 11:18:44.097124 ============ LP4 DIFF to SE exit ============
3837 11:18:44.100353 [ANA_INIT] <<<<<<<<<<<<<
3838 11:18:44.104079 [Flow] Enable top DCM control >>>>>
3839 11:18:44.107283 [Flow] Enable top DCM control <<<<<
3840 11:18:44.110634 Enable DLL master slave shuffle
3841 11:18:44.117200 ==============================================================
3842 11:18:44.117310 Gating Mode config
3843 11:18:44.123696 ==============================================================
3844 11:18:44.123800 Config description:
3845 11:18:44.133554 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3846 11:18:44.140124 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3847 11:18:44.147051 SELPH_MODE 0: By rank 1: By Phase
3848 11:18:44.150066 ==============================================================
3849 11:18:44.153452 GAT_TRACK_EN = 1
3850 11:18:44.156671 RX_GATING_MODE = 2
3851 11:18:44.159859 RX_GATING_TRACK_MODE = 2
3852 11:18:44.163485 SELPH_MODE = 1
3853 11:18:44.166814 PICG_EARLY_EN = 1
3854 11:18:44.170171 VALID_LAT_VALUE = 1
3855 11:18:44.173222 ==============================================================
3856 11:18:44.176925 Enter into Gating configuration >>>>
3857 11:18:44.179847 Exit from Gating configuration <<<<
3858 11:18:44.183125 Enter into DVFS_PRE_config >>>>>
3859 11:18:44.196281 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3860 11:18:44.200103 Exit from DVFS_PRE_config <<<<<
3861 11:18:44.203445 Enter into PICG configuration >>>>
3862 11:18:44.206730 Exit from PICG configuration <<<<
3863 11:18:44.206823 [RX_INPUT] configuration >>>>>
3864 11:18:44.210163 [RX_INPUT] configuration <<<<<
3865 11:18:44.216484 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3866 11:18:44.220896 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3867 11:18:44.226350 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3868 11:18:44.232810 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3869 11:18:44.239803 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3870 11:18:44.246332 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3871 11:18:44.249723 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3872 11:18:44.253372 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3873 11:18:44.256681 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3874 11:18:44.262943 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3875 11:18:44.266426 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3876 11:18:44.269411 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3877 11:18:44.272820 ===================================
3878 11:18:44.276484 LPDDR4 DRAM CONFIGURATION
3879 11:18:44.280386 ===================================
3880 11:18:44.283038 EX_ROW_EN[0] = 0x0
3881 11:18:44.283131 EX_ROW_EN[1] = 0x0
3882 11:18:44.286441 LP4Y_EN = 0x0
3883 11:18:44.286527 WORK_FSP = 0x0
3884 11:18:44.289356 WL = 0x2
3885 11:18:44.289441 RL = 0x2
3886 11:18:44.292559 BL = 0x2
3887 11:18:44.292644 RPST = 0x0
3888 11:18:44.296262 RD_PRE = 0x0
3889 11:18:44.296349 WR_PRE = 0x1
3890 11:18:44.299588 WR_PST = 0x0
3891 11:18:44.299676 DBI_WR = 0x0
3892 11:18:44.303243 DBI_RD = 0x0
3893 11:18:44.303332 OTF = 0x1
3894 11:18:44.306291 ===================================
3895 11:18:44.313108 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3896 11:18:44.315880 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3897 11:18:44.319381 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3898 11:18:44.322800 ===================================
3899 11:18:44.326215 LPDDR4 DRAM CONFIGURATION
3900 11:18:44.329148 ===================================
3901 11:18:44.332464 EX_ROW_EN[0] = 0x10
3902 11:18:44.332558 EX_ROW_EN[1] = 0x0
3903 11:18:44.335908 LP4Y_EN = 0x0
3904 11:18:44.336010 WORK_FSP = 0x0
3905 11:18:44.340044 WL = 0x2
3906 11:18:44.340139 RL = 0x2
3907 11:18:44.342959 BL = 0x2
3908 11:18:44.343046 RPST = 0x0
3909 11:18:44.346113 RD_PRE = 0x0
3910 11:18:44.346210 WR_PRE = 0x1
3911 11:18:44.349207 WR_PST = 0x0
3912 11:18:44.349295 DBI_WR = 0x0
3913 11:18:44.353092 DBI_RD = 0x0
3914 11:18:44.353181 OTF = 0x1
3915 11:18:44.355771 ===================================
3916 11:18:44.362214 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3917 11:18:44.367171 nWR fixed to 30
3918 11:18:44.370350 [ModeRegInit_LP4] CH0 RK0
3919 11:18:44.370445 [ModeRegInit_LP4] CH0 RK1
3920 11:18:44.373838 [ModeRegInit_LP4] CH1 RK0
3921 11:18:44.376944 [ModeRegInit_LP4] CH1 RK1
3922 11:18:44.377031 match AC timing 17
3923 11:18:44.383487 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3924 11:18:44.386778 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3925 11:18:44.390112 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3926 11:18:44.396998 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3927 11:18:44.400457 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3928 11:18:44.400555 ==
3929 11:18:44.403509 Dram Type= 6, Freq= 0, CH_0, rank 0
3930 11:18:44.406917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3931 11:18:44.407007 ==
3932 11:18:44.413889 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3933 11:18:44.420054 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3934 11:18:44.423839 [CA 0] Center 35 (5~66) winsize 62
3935 11:18:44.426778 [CA 1] Center 35 (5~66) winsize 62
3936 11:18:44.430281 [CA 2] Center 34 (4~65) winsize 62
3937 11:18:44.433980 [CA 3] Center 34 (4~64) winsize 61
3938 11:18:44.436861 [CA 4] Center 33 (3~64) winsize 62
3939 11:18:44.440163 [CA 5] Center 33 (3~64) winsize 62
3940 11:18:44.440253
3941 11:18:44.443232 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3942 11:18:44.443315
3943 11:18:44.446955 [CATrainingPosCal] consider 1 rank data
3944 11:18:44.450241 u2DelayCellTimex100 = 270/100 ps
3945 11:18:44.453540 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
3946 11:18:44.456786 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
3947 11:18:44.460360 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3948 11:18:44.463371 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3949 11:18:44.466569 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3950 11:18:44.472950 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3951 11:18:44.473054
3952 11:18:44.476581 CA PerBit enable=1, Macro0, CA PI delay=33
3953 11:18:44.476672
3954 11:18:44.480280 [CBTSetCACLKResult] CA Dly = 33
3955 11:18:44.480365 CS Dly: 4 (0~35)
3956 11:18:44.480429 ==
3957 11:18:44.482902 Dram Type= 6, Freq= 0, CH_0, rank 1
3958 11:18:44.486242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3959 11:18:44.489660 ==
3960 11:18:44.492994 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3961 11:18:44.500068 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3962 11:18:44.503311 [CA 0] Center 36 (6~66) winsize 61
3963 11:18:44.506142 [CA 1] Center 36 (6~66) winsize 61
3964 11:18:44.509800 [CA 2] Center 34 (4~65) winsize 62
3965 11:18:44.512824 [CA 3] Center 34 (4~65) winsize 62
3966 11:18:44.516308 [CA 4] Center 33 (3~64) winsize 62
3967 11:18:44.519767 [CA 5] Center 33 (3~64) winsize 62
3968 11:18:44.519857
3969 11:18:44.523033 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3970 11:18:44.523116
3971 11:18:44.525909 [CATrainingPosCal] consider 2 rank data
3972 11:18:44.529303 u2DelayCellTimex100 = 270/100 ps
3973 11:18:44.532911 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
3974 11:18:44.536089 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
3975 11:18:44.539333 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3976 11:18:44.546138 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
3977 11:18:44.549316 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3978 11:18:44.552532 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3979 11:18:44.552621
3980 11:18:44.555840 CA PerBit enable=1, Macro0, CA PI delay=33
3981 11:18:44.555925
3982 11:18:44.559360 [CBTSetCACLKResult] CA Dly = 33
3983 11:18:44.559445 CS Dly: 4 (0~36)
3984 11:18:44.559508
3985 11:18:44.562819 ----->DramcWriteLeveling(PI) begin...
3986 11:18:44.566674 ==
3987 11:18:44.566760 Dram Type= 6, Freq= 0, CH_0, rank 0
3988 11:18:44.572341 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3989 11:18:44.572434 ==
3990 11:18:44.575889 Write leveling (Byte 0): 31 => 31
3991 11:18:44.579357 Write leveling (Byte 1): 30 => 30
3992 11:18:44.582347 DramcWriteLeveling(PI) end<-----
3993 11:18:44.582433
3994 11:18:44.582496 ==
3995 11:18:44.585440 Dram Type= 6, Freq= 0, CH_0, rank 0
3996 11:18:44.588989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3997 11:18:44.589075 ==
3998 11:18:44.592177 [Gating] SW mode calibration
3999 11:18:44.599010 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4000 11:18:44.602163 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4001 11:18:44.609142 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4002 11:18:44.612216 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4003 11:18:44.615796 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4004 11:18:44.622042 0 9 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4005 11:18:44.625422 0 9 16 | B1->B0 | 3232 2828 | 0 0 | (0 0) (0 0)
4006 11:18:44.629050 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
4007 11:18:44.635385 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4008 11:18:44.638910 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4009 11:18:44.642021 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4010 11:18:44.648809 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4011 11:18:44.652111 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4012 11:18:44.655268 0 10 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4013 11:18:44.662289 0 10 16 | B1->B0 | 3131 3e3e | 1 0 | (0 0) (0 0)
4014 11:18:44.665574 0 10 20 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
4015 11:18:44.668829 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4016 11:18:44.675972 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4017 11:18:44.678753 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4018 11:18:44.681963 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4019 11:18:44.688791 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4020 11:18:44.691891 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4021 11:18:44.695004 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4022 11:18:44.701743 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4023 11:18:44.705209 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4024 11:18:44.708493 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4025 11:18:44.715159 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4026 11:18:44.718220 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4027 11:18:44.721926 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4028 11:18:44.728195 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4029 11:18:44.731558 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4030 11:18:44.735257 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4031 11:18:44.741599 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4032 11:18:44.744908 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4033 11:18:44.748165 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4034 11:18:44.754895 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4035 11:18:44.758696 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4036 11:18:44.761388 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4037 11:18:44.765243 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4038 11:18:44.771874 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4039 11:18:44.774728 Total UI for P1: 0, mck2ui 16
4040 11:18:44.778350 best dqsien dly found for B0: ( 0, 13, 16)
4041 11:18:44.782044 Total UI for P1: 0, mck2ui 16
4042 11:18:44.784919 best dqsien dly found for B1: ( 0, 13, 16)
4043 11:18:44.788154 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4044 11:18:44.791601 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4045 11:18:44.791693
4046 11:18:44.794874 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4047 11:18:44.798028 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4048 11:18:44.801330 [Gating] SW calibration Done
4049 11:18:44.801420 ==
4050 11:18:44.804769 Dram Type= 6, Freq= 0, CH_0, rank 0
4051 11:18:44.808079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4052 11:18:44.808168 ==
4053 11:18:44.811166 RX Vref Scan: 0
4054 11:18:44.811250
4055 11:18:44.814494 RX Vref 0 -> 0, step: 1
4056 11:18:44.814587
4057 11:18:44.814654 RX Delay -230 -> 252, step: 16
4058 11:18:44.821012 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4059 11:18:44.824636 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4060 11:18:44.827674 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4061 11:18:44.831277 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4062 11:18:44.837687 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4063 11:18:44.841175 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4064 11:18:44.844595 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4065 11:18:44.848056 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4066 11:18:44.851141 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4067 11:18:44.857619 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4068 11:18:44.860736 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4069 11:18:44.865147 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4070 11:18:44.867483 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4071 11:18:44.874297 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4072 11:18:44.877540 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4073 11:18:44.881156 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4074 11:18:44.881252 ==
4075 11:18:44.884304 Dram Type= 6, Freq= 0, CH_0, rank 0
4076 11:18:44.887673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4077 11:18:44.891223 ==
4078 11:18:44.891314 DQS Delay:
4079 11:18:44.891387 DQS0 = 0, DQS1 = 0
4080 11:18:44.894185 DQM Delay:
4081 11:18:44.894269 DQM0 = 39, DQM1 = 31
4082 11:18:44.897442 DQ Delay:
4083 11:18:44.901098 DQ0 =41, DQ1 =33, DQ2 =33, DQ3 =33
4084 11:18:44.901188 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4085 11:18:44.904334 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4086 11:18:44.907480 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =41
4087 11:18:44.911242
4088 11:18:44.911333
4089 11:18:44.911409 ==
4090 11:18:44.914040 Dram Type= 6, Freq= 0, CH_0, rank 0
4091 11:18:44.917977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4092 11:18:44.918072 ==
4093 11:18:44.918139
4094 11:18:44.918197
4095 11:18:44.920809 TX Vref Scan disable
4096 11:18:44.920894 == TX Byte 0 ==
4097 11:18:44.927313 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4098 11:18:44.930694 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4099 11:18:44.930822 == TX Byte 1 ==
4100 11:18:44.936974 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4101 11:18:44.940497 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4102 11:18:44.940593 ==
4103 11:18:44.943999 Dram Type= 6, Freq= 0, CH_0, rank 0
4104 11:18:44.947032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4105 11:18:44.947121 ==
4106 11:18:44.947187
4107 11:18:44.950460
4108 11:18:44.950544 TX Vref Scan disable
4109 11:18:44.953763 == TX Byte 0 ==
4110 11:18:44.957290 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4111 11:18:44.964027 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4112 11:18:44.964132 == TX Byte 1 ==
4113 11:18:44.967120 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4114 11:18:44.973845 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4115 11:18:44.973951
4116 11:18:44.974019 [DATLAT]
4117 11:18:44.974081 Freq=600, CH0 RK0
4118 11:18:44.974138
4119 11:18:44.977313 DATLAT Default: 0x9
4120 11:18:44.977399 0, 0xFFFF, sum = 0
4121 11:18:44.980295 1, 0xFFFF, sum = 0
4122 11:18:44.983663 2, 0xFFFF, sum = 0
4123 11:18:44.983752 3, 0xFFFF, sum = 0
4124 11:18:44.986869 4, 0xFFFF, sum = 0
4125 11:18:44.986955 5, 0xFFFF, sum = 0
4126 11:18:44.990442 6, 0xFFFF, sum = 0
4127 11:18:44.990529 7, 0xFFFF, sum = 0
4128 11:18:44.993457 8, 0x0, sum = 1
4129 11:18:44.993545 9, 0x0, sum = 2
4130 11:18:44.993612 10, 0x0, sum = 3
4131 11:18:44.996711 11, 0x0, sum = 4
4132 11:18:44.996798 best_step = 9
4133 11:18:44.996863
4134 11:18:45.000345 ==
4135 11:18:45.000432 Dram Type= 6, Freq= 0, CH_0, rank 0
4136 11:18:45.006662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4137 11:18:45.006763 ==
4138 11:18:45.006831 RX Vref Scan: 1
4139 11:18:45.006891
4140 11:18:45.010054 RX Vref 0 -> 0, step: 1
4141 11:18:45.010141
4142 11:18:45.013294 RX Delay -195 -> 252, step: 8
4143 11:18:45.013391
4144 11:18:45.016607 Set Vref, RX VrefLevel [Byte0]: 52
4145 11:18:45.019825 [Byte1]: 51
4146 11:18:45.019917
4147 11:18:45.023561 Final RX Vref Byte 0 = 52 to rank0
4148 11:18:45.026398 Final RX Vref Byte 1 = 51 to rank0
4149 11:18:45.029908 Final RX Vref Byte 0 = 52 to rank1
4150 11:18:45.033265 Final RX Vref Byte 1 = 51 to rank1==
4151 11:18:45.036568 Dram Type= 6, Freq= 0, CH_0, rank 0
4152 11:18:45.039719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4153 11:18:45.039810 ==
4154 11:18:45.043066 DQS Delay:
4155 11:18:45.043151 DQS0 = 0, DQS1 = 0
4156 11:18:45.046467 DQM Delay:
4157 11:18:45.046552 DQM0 = 42, DQM1 = 33
4158 11:18:45.049640 DQ Delay:
4159 11:18:45.049724 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =40
4160 11:18:45.053496 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4161 11:18:45.056263 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4162 11:18:45.059486 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4163 11:18:45.059574
4164 11:18:45.063008
4165 11:18:45.070002 [DQSOSCAuto] RK0, (LSB)MR18= 0x3918, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 399 ps
4166 11:18:45.072686 CH0 RK0: MR19=808, MR18=3918
4167 11:18:45.079943 CH0_RK0: MR19=0x808, MR18=0x3918, DQSOSC=399, MR23=63, INC=164, DEC=109
4168 11:18:45.080055
4169 11:18:45.082944 ----->DramcWriteLeveling(PI) begin...
4170 11:18:45.083032 ==
4171 11:18:45.086390 Dram Type= 6, Freq= 0, CH_0, rank 1
4172 11:18:45.089516 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4173 11:18:45.089605 ==
4174 11:18:45.092986 Write leveling (Byte 0): 32 => 32
4175 11:18:45.096206 Write leveling (Byte 1): 32 => 32
4176 11:18:45.099325 DramcWriteLeveling(PI) end<-----
4177 11:18:45.099455
4178 11:18:45.099521 ==
4179 11:18:45.102723 Dram Type= 6, Freq= 0, CH_0, rank 1
4180 11:18:45.106230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4181 11:18:45.106321 ==
4182 11:18:45.109455 [Gating] SW mode calibration
4183 11:18:45.116162 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4184 11:18:45.122736 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4185 11:18:45.126324 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4186 11:18:45.129741 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4187 11:18:45.136018 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4188 11:18:45.139307 0 9 12 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
4189 11:18:45.143081 0 9 16 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
4190 11:18:45.149158 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4191 11:18:45.152904 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4192 11:18:45.155848 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4193 11:18:45.162897 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4194 11:18:45.166198 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4195 11:18:45.169387 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4196 11:18:45.176136 0 10 12 | B1->B0 | 2323 3a3a | 0 0 | (0 0) (0 0)
4197 11:18:45.179018 0 10 16 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
4198 11:18:45.182448 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4199 11:18:45.189655 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4200 11:18:45.192369 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4201 11:18:45.195716 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4202 11:18:45.202218 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4203 11:18:45.205967 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4204 11:18:45.209123 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4205 11:18:45.215525 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4206 11:18:45.218939 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 11:18:45.222270 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 11:18:45.228811 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 11:18:45.232108 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 11:18:45.235271 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 11:18:45.238920 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 11:18:45.245465 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4213 11:18:45.248662 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4214 11:18:45.252209 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4215 11:18:45.258932 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4216 11:18:45.262309 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4217 11:18:45.266217 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4218 11:18:45.272215 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4219 11:18:45.275613 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4220 11:18:45.278651 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4221 11:18:45.285227 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4222 11:18:45.288433 Total UI for P1: 0, mck2ui 16
4223 11:18:45.291930 best dqsien dly found for B0: ( 0, 13, 12)
4224 11:18:45.295474 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4225 11:18:45.298539 Total UI for P1: 0, mck2ui 16
4226 11:18:45.301709 best dqsien dly found for B1: ( 0, 13, 16)
4227 11:18:45.305104 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4228 11:18:45.308434 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4229 11:18:45.308526
4230 11:18:45.311810 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4231 11:18:45.315103 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4232 11:18:45.318443 [Gating] SW calibration Done
4233 11:18:45.318535 ==
4234 11:18:45.321931 Dram Type= 6, Freq= 0, CH_0, rank 1
4235 11:18:45.328686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4236 11:18:45.328790 ==
4237 11:18:45.328857 RX Vref Scan: 0
4238 11:18:45.328917
4239 11:18:45.331751 RX Vref 0 -> 0, step: 1
4240 11:18:45.331835
4241 11:18:45.335102 RX Delay -230 -> 252, step: 16
4242 11:18:45.338413 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4243 11:18:45.341732 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4244 11:18:45.345498 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4245 11:18:45.351760 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4246 11:18:45.354842 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4247 11:18:45.358197 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4248 11:18:45.361545 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4249 11:18:45.368095 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4250 11:18:45.371747 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4251 11:18:45.375260 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4252 11:18:45.378107 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4253 11:18:45.381708 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4254 11:18:45.388015 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4255 11:18:45.391568 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4256 11:18:45.394687 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4257 11:18:45.398573 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4258 11:18:45.398667 ==
4259 11:18:45.401614 Dram Type= 6, Freq= 0, CH_0, rank 1
4260 11:18:45.408406 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4261 11:18:45.408510 ==
4262 11:18:45.408578 DQS Delay:
4263 11:18:45.411621 DQS0 = 0, DQS1 = 0
4264 11:18:45.411706 DQM Delay:
4265 11:18:45.414633 DQM0 = 42, DQM1 = 36
4266 11:18:45.414721 DQ Delay:
4267 11:18:45.418198 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4268 11:18:45.421213 DQ4 =41, DQ5 =25, DQ6 =57, DQ7 =49
4269 11:18:45.424714 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4270 11:18:45.427951 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4271 11:18:45.428040
4272 11:18:45.428106
4273 11:18:45.428166 ==
4274 11:18:45.431538 Dram Type= 6, Freq= 0, CH_0, rank 1
4275 11:18:45.434654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4276 11:18:45.434741 ==
4277 11:18:45.434807
4278 11:18:45.434865
4279 11:18:45.437971 TX Vref Scan disable
4280 11:18:45.441450 == TX Byte 0 ==
4281 11:18:45.444578 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4282 11:18:45.448043 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4283 11:18:45.451239 == TX Byte 1 ==
4284 11:18:45.454614 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4285 11:18:45.457921 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4286 11:18:45.458015 ==
4287 11:18:45.460974 Dram Type= 6, Freq= 0, CH_0, rank 1
4288 11:18:45.464621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4289 11:18:45.467820 ==
4290 11:18:45.467909
4291 11:18:45.467973
4292 11:18:45.468031 TX Vref Scan disable
4293 11:18:45.471915 == TX Byte 0 ==
4294 11:18:45.474800 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4295 11:18:45.481770 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4296 11:18:45.481893 == TX Byte 1 ==
4297 11:18:45.484750 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4298 11:18:45.491558 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4299 11:18:45.491661
4300 11:18:45.491726 [DATLAT]
4301 11:18:45.491787 Freq=600, CH0 RK1
4302 11:18:45.491844
4303 11:18:45.494916 DATLAT Default: 0x9
4304 11:18:45.497996 0, 0xFFFF, sum = 0
4305 11:18:45.498083 1, 0xFFFF, sum = 0
4306 11:18:45.501713 2, 0xFFFF, sum = 0
4307 11:18:45.501802 3, 0xFFFF, sum = 0
4308 11:18:45.504772 4, 0xFFFF, sum = 0
4309 11:18:45.504857 5, 0xFFFF, sum = 0
4310 11:18:45.508050 6, 0xFFFF, sum = 0
4311 11:18:45.508135 7, 0xFFFF, sum = 0
4312 11:18:45.511278 8, 0x0, sum = 1
4313 11:18:45.511402 9, 0x0, sum = 2
4314 11:18:45.514429 10, 0x0, sum = 3
4315 11:18:45.514518 11, 0x0, sum = 4
4316 11:18:45.514583 best_step = 9
4317 11:18:45.514647
4318 11:18:45.517997 ==
4319 11:18:45.518081 Dram Type= 6, Freq= 0, CH_0, rank 1
4320 11:18:45.524548 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4321 11:18:45.524645 ==
4322 11:18:45.524709 RX Vref Scan: 0
4323 11:18:45.524768
4324 11:18:45.528132 RX Vref 0 -> 0, step: 1
4325 11:18:45.528215
4326 11:18:45.530983 RX Delay -179 -> 252, step: 8
4327 11:18:45.537824 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4328 11:18:45.541309 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4329 11:18:45.544620 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4330 11:18:45.547548 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4331 11:18:45.551041 iDelay=205, Bit 4, Center 36 (-115 ~ 188) 304
4332 11:18:45.557463 iDelay=205, Bit 5, Center 28 (-123 ~ 180) 304
4333 11:18:45.560805 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4334 11:18:45.563961 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4335 11:18:45.567321 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4336 11:18:45.574281 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4337 11:18:45.577102 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4338 11:18:45.580688 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4339 11:18:45.584058 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4340 11:18:45.590617 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4341 11:18:45.593968 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4342 11:18:45.597236 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4343 11:18:45.597322 ==
4344 11:18:45.601363 Dram Type= 6, Freq= 0, CH_0, rank 1
4345 11:18:45.604228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4346 11:18:45.604314 ==
4347 11:18:45.607540 DQS Delay:
4348 11:18:45.607624 DQS0 = 0, DQS1 = 0
4349 11:18:45.610603 DQM Delay:
4350 11:18:45.610687 DQM0 = 39, DQM1 = 33
4351 11:18:45.610750 DQ Delay:
4352 11:18:45.614160 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4353 11:18:45.617137 DQ4 =36, DQ5 =28, DQ6 =48, DQ7 =44
4354 11:18:45.620122 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4355 11:18:45.623802 DQ12 =36, DQ13 =40, DQ14 =44, DQ15 =40
4356 11:18:45.623890
4357 11:18:45.627129
4358 11:18:45.633256 [DQSOSCAuto] RK1, (LSB)MR18= 0x4627, (MSB)MR19= 0x808, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
4359 11:18:45.636956 CH0 RK1: MR19=808, MR18=4627
4360 11:18:45.643477 CH0_RK1: MR19=0x808, MR18=0x4627, DQSOSC=396, MR23=63, INC=167, DEC=111
4361 11:18:45.646793 [RxdqsGatingPostProcess] freq 600
4362 11:18:45.649977 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4363 11:18:45.653445 Pre-setting of DQS Precalculation
4364 11:18:45.659930 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4365 11:18:45.660040 ==
4366 11:18:45.663132 Dram Type= 6, Freq= 0, CH_1, rank 0
4367 11:18:45.666695 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4368 11:18:45.666785 ==
4369 11:18:45.673116 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4370 11:18:45.677029 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4371 11:18:45.680454 [CA 0] Center 35 (5~66) winsize 62
4372 11:18:45.683774 [CA 1] Center 35 (5~65) winsize 61
4373 11:18:45.686927 [CA 2] Center 34 (4~65) winsize 62
4374 11:18:45.690227 [CA 3] Center 33 (3~64) winsize 62
4375 11:18:45.693786 [CA 4] Center 34 (3~65) winsize 63
4376 11:18:45.696977 [CA 5] Center 33 (2~64) winsize 63
4377 11:18:45.697066
4378 11:18:45.700168 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4379 11:18:45.700251
4380 11:18:45.703881 [CATrainingPosCal] consider 1 rank data
4381 11:18:45.706885 u2DelayCellTimex100 = 270/100 ps
4382 11:18:45.710122 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4383 11:18:45.717104 CA1 delay=35 (5~65),Diff = 2 PI (19 cell)
4384 11:18:45.719793 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4385 11:18:45.723549 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4386 11:18:45.726649 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4387 11:18:45.730307 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
4388 11:18:45.730396
4389 11:18:45.733307 CA PerBit enable=1, Macro0, CA PI delay=33
4390 11:18:45.733391
4391 11:18:45.736507 [CBTSetCACLKResult] CA Dly = 33
4392 11:18:45.740132 CS Dly: 5 (0~36)
4393 11:18:45.740220 ==
4394 11:18:45.743132 Dram Type= 6, Freq= 0, CH_1, rank 1
4395 11:18:45.746303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4396 11:18:45.746390 ==
4397 11:18:45.752950 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4398 11:18:45.756163 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4399 11:18:45.760740 [CA 0] Center 35 (5~66) winsize 62
4400 11:18:45.764263 [CA 1] Center 36 (6~66) winsize 61
4401 11:18:45.767286 [CA 2] Center 34 (4~65) winsize 62
4402 11:18:45.770536 [CA 3] Center 34 (3~65) winsize 63
4403 11:18:45.774134 [CA 4] Center 34 (3~65) winsize 63
4404 11:18:45.777600 [CA 5] Center 33 (3~64) winsize 62
4405 11:18:45.777689
4406 11:18:45.780570 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4407 11:18:45.780654
4408 11:18:45.784035 [CATrainingPosCal] consider 2 rank data
4409 11:18:45.786976 u2DelayCellTimex100 = 270/100 ps
4410 11:18:45.790376 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4411 11:18:45.796772 CA1 delay=35 (6~65),Diff = 2 PI (19 cell)
4412 11:18:45.800348 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4413 11:18:45.803881 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4414 11:18:45.807489 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4415 11:18:45.810072 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4416 11:18:45.810172
4417 11:18:45.813491 CA PerBit enable=1, Macro0, CA PI delay=33
4418 11:18:45.813574
4419 11:18:45.816802 [CBTSetCACLKResult] CA Dly = 33
4420 11:18:45.820580 CS Dly: 5 (0~36)
4421 11:18:45.820668
4422 11:18:45.823259 ----->DramcWriteLeveling(PI) begin...
4423 11:18:45.823346 ==
4424 11:18:45.826767 Dram Type= 6, Freq= 0, CH_1, rank 0
4425 11:18:45.830244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4426 11:18:45.830332 ==
4427 11:18:45.833653 Write leveling (Byte 0): 30 => 30
4428 11:18:45.836568 Write leveling (Byte 1): 29 => 29
4429 11:18:45.840214 DramcWriteLeveling(PI) end<-----
4430 11:18:45.840299
4431 11:18:45.840362 ==
4432 11:18:45.843253 Dram Type= 6, Freq= 0, CH_1, rank 0
4433 11:18:45.846922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4434 11:18:45.847011 ==
4435 11:18:45.849842 [Gating] SW mode calibration
4436 11:18:45.856437 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4437 11:18:45.863058 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4438 11:18:45.866694 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4439 11:18:45.869782 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4440 11:18:45.876813 0 9 8 | B1->B0 | 3535 3434 | 1 1 | (0 0) (1 1)
4441 11:18:45.880133 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (0 0)
4442 11:18:45.883262 0 9 16 | B1->B0 | 2d2d 2828 | 1 0 | (0 0) (0 0)
4443 11:18:45.889616 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4444 11:18:45.892935 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4445 11:18:45.896329 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4446 11:18:45.903143 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4447 11:18:45.906361 0 10 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4448 11:18:45.909784 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4449 11:18:45.916241 0 10 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
4450 11:18:45.919656 0 10 16 | B1->B0 | 3d3d 4040 | 0 0 | (0 0) (0 0)
4451 11:18:45.923030 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4452 11:18:45.929490 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4453 11:18:45.933209 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4454 11:18:45.936516 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4455 11:18:45.942616 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4456 11:18:45.945880 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4457 11:18:45.949397 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4458 11:18:45.956486 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4459 11:18:45.959628 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4460 11:18:45.962548 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4461 11:18:45.966289 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4462 11:18:45.972309 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4463 11:18:45.975976 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4464 11:18:45.979281 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4465 11:18:45.986127 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4466 11:18:45.989299 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4467 11:18:45.992507 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4468 11:18:45.999702 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4469 11:18:46.002765 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4470 11:18:46.006199 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4471 11:18:46.012815 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4472 11:18:46.015721 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4473 11:18:46.019328 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4474 11:18:46.026238 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4475 11:18:46.026342 Total UI for P1: 0, mck2ui 16
4476 11:18:46.032437 best dqsien dly found for B0: ( 0, 13, 14)
4477 11:18:46.032567 Total UI for P1: 0, mck2ui 16
4478 11:18:46.039579 best dqsien dly found for B1: ( 0, 13, 14)
4479 11:18:46.042497 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4480 11:18:46.045488 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4481 11:18:46.045575
4482 11:18:46.048994 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4483 11:18:46.052163 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4484 11:18:46.055622 [Gating] SW calibration Done
4485 11:18:46.055706 ==
4486 11:18:46.058936 Dram Type= 6, Freq= 0, CH_1, rank 0
4487 11:18:46.062031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4488 11:18:46.062115 ==
4489 11:18:46.065930 RX Vref Scan: 0
4490 11:18:46.066013
4491 11:18:46.066091 RX Vref 0 -> 0, step: 1
4492 11:18:46.068582
4493 11:18:46.068662 RX Delay -230 -> 252, step: 16
4494 11:18:46.075223 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4495 11:18:46.078746 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4496 11:18:46.081946 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4497 11:18:46.085486 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4498 11:18:46.091916 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4499 11:18:46.095432 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4500 11:18:46.098425 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4501 11:18:46.102237 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4502 11:18:46.104918 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4503 11:18:46.112072 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4504 11:18:46.115288 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4505 11:18:46.118699 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4506 11:18:46.121570 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4507 11:18:46.128387 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4508 11:18:46.131704 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4509 11:18:46.134923 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4510 11:18:46.135016 ==
4511 11:18:46.137897 Dram Type= 6, Freq= 0, CH_1, rank 0
4512 11:18:46.141509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4513 11:18:46.145016 ==
4514 11:18:46.145110 DQS Delay:
4515 11:18:46.145195 DQS0 = 0, DQS1 = 0
4516 11:18:46.148380 DQM Delay:
4517 11:18:46.148467 DQM0 = 45, DQM1 = 36
4518 11:18:46.151133 DQ Delay:
4519 11:18:46.154873 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4520 11:18:46.154960 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4521 11:18:46.158381 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4522 11:18:46.161087 DQ12 =49, DQ13 =41, DQ14 =41, DQ15 =41
4523 11:18:46.164838
4524 11:18:46.164928
4525 11:18:46.165011 ==
4526 11:18:46.167938 Dram Type= 6, Freq= 0, CH_1, rank 0
4527 11:18:46.171231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4528 11:18:46.171319 ==
4529 11:18:46.171411
4530 11:18:46.171491
4531 11:18:46.174781 TX Vref Scan disable
4532 11:18:46.174866 == TX Byte 0 ==
4533 11:18:46.181521 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4534 11:18:46.184695 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4535 11:18:46.184788 == TX Byte 1 ==
4536 11:18:46.190998 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4537 11:18:46.194751 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4538 11:18:46.194846 ==
4539 11:18:46.197971 Dram Type= 6, Freq= 0, CH_1, rank 0
4540 11:18:46.201237 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4541 11:18:46.201328 ==
4542 11:18:46.201414
4543 11:18:46.201492
4544 11:18:46.204339 TX Vref Scan disable
4545 11:18:46.207840 == TX Byte 0 ==
4546 11:18:46.211517 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4547 11:18:46.217440 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4548 11:18:46.217552 == TX Byte 1 ==
4549 11:18:46.220905 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4550 11:18:46.227713 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4551 11:18:46.227820
4552 11:18:46.227908 [DATLAT]
4553 11:18:46.227988 Freq=600, CH1 RK0
4554 11:18:46.228066
4555 11:18:46.231041 DATLAT Default: 0x9
4556 11:18:46.231126 0, 0xFFFF, sum = 0
4557 11:18:46.234009 1, 0xFFFF, sum = 0
4558 11:18:46.234097 2, 0xFFFF, sum = 0
4559 11:18:46.237990 3, 0xFFFF, sum = 0
4560 11:18:46.240637 4, 0xFFFF, sum = 0
4561 11:18:46.240726 5, 0xFFFF, sum = 0
4562 11:18:46.244222 6, 0xFFFF, sum = 0
4563 11:18:46.244311 7, 0xFFFF, sum = 0
4564 11:18:46.247405 8, 0x0, sum = 1
4565 11:18:46.247490 9, 0x0, sum = 2
4566 11:18:46.247556 10, 0x0, sum = 3
4567 11:18:46.250971 11, 0x0, sum = 4
4568 11:18:46.251055 best_step = 9
4569 11:18:46.251119
4570 11:18:46.251178 ==
4571 11:18:46.254195 Dram Type= 6, Freq= 0, CH_1, rank 0
4572 11:18:46.260475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4573 11:18:46.260571 ==
4574 11:18:46.260637 RX Vref Scan: 1
4575 11:18:46.260696
4576 11:18:46.263930 RX Vref 0 -> 0, step: 1
4577 11:18:46.264012
4578 11:18:46.267203 RX Delay -179 -> 252, step: 8
4579 11:18:46.267285
4580 11:18:46.270589 Set Vref, RX VrefLevel [Byte0]: 59
4581 11:18:46.274023 [Byte1]: 48
4582 11:18:46.274109
4583 11:18:46.276985 Final RX Vref Byte 0 = 59 to rank0
4584 11:18:46.280297 Final RX Vref Byte 1 = 48 to rank0
4585 11:18:46.283752 Final RX Vref Byte 0 = 59 to rank1
4586 11:18:46.287223 Final RX Vref Byte 1 = 48 to rank1==
4587 11:18:46.290009 Dram Type= 6, Freq= 0, CH_1, rank 0
4588 11:18:46.293707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4589 11:18:46.293795 ==
4590 11:18:46.297177 DQS Delay:
4591 11:18:46.297261 DQS0 = 0, DQS1 = 0
4592 11:18:46.300228 DQM Delay:
4593 11:18:46.300311 DQM0 = 40, DQM1 = 32
4594 11:18:46.300375 DQ Delay:
4595 11:18:46.303489 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =40
4596 11:18:46.307061 DQ4 =40, DQ5 =48, DQ6 =52, DQ7 =36
4597 11:18:46.310359 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =28
4598 11:18:46.313996 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =36
4599 11:18:46.314083
4600 11:18:46.314146
4601 11:18:46.323316 [DQSOSCAuto] RK0, (LSB)MR18= 0x440a, (MSB)MR19= 0x808, tDQSOscB0 = 408 ps tDQSOscB1 = 396 ps
4602 11:18:46.326908 CH1 RK0: MR19=808, MR18=440A
4603 11:18:46.333154 CH1_RK0: MR19=0x808, MR18=0x440A, DQSOSC=396, MR23=63, INC=167, DEC=111
4604 11:18:46.333261
4605 11:18:46.336728 ----->DramcWriteLeveling(PI) begin...
4606 11:18:46.336817 ==
4607 11:18:46.340506 Dram Type= 6, Freq= 0, CH_1, rank 1
4608 11:18:46.343435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4609 11:18:46.343523 ==
4610 11:18:46.346362 Write leveling (Byte 0): 30 => 30
4611 11:18:46.349731 Write leveling (Byte 1): 30 => 30
4612 11:18:46.353165 DramcWriteLeveling(PI) end<-----
4613 11:18:46.353255
4614 11:18:46.353319 ==
4615 11:18:46.356513 Dram Type= 6, Freq= 0, CH_1, rank 1
4616 11:18:46.360050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4617 11:18:46.360140 ==
4618 11:18:46.363394 [Gating] SW mode calibration
4619 11:18:46.369871 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4620 11:18:46.376710 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4621 11:18:46.379859 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4622 11:18:46.383292 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4623 11:18:46.390019 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4624 11:18:46.393302 0 9 12 | B1->B0 | 3030 2929 | 0 0 | (0 1) (1 1)
4625 11:18:46.396405 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4626 11:18:46.403588 0 9 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4627 11:18:46.406442 0 9 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4628 11:18:46.409764 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4629 11:18:46.416131 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4630 11:18:46.419684 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4631 11:18:46.423053 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4632 11:18:46.429622 0 10 12 | B1->B0 | 3232 3c3c | 0 1 | (1 1) (0 0)
4633 11:18:46.432975 0 10 16 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
4634 11:18:46.436061 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4635 11:18:46.443132 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4636 11:18:46.446092 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4637 11:18:46.449806 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4638 11:18:46.456123 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4639 11:18:46.459699 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4640 11:18:46.462826 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4641 11:18:46.466319 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4642 11:18:46.472881 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 11:18:46.476481 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 11:18:46.479254 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 11:18:46.485794 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 11:18:46.489310 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 11:18:46.492560 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 11:18:46.499259 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 11:18:46.502510 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 11:18:46.506036 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 11:18:46.512250 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 11:18:46.515687 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 11:18:46.519019 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 11:18:46.525705 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 11:18:46.529108 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 11:18:46.532235 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4657 11:18:46.538869 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4658 11:18:46.542942 Total UI for P1: 0, mck2ui 16
4659 11:18:46.545837 best dqsien dly found for B0: ( 0, 13, 12)
4660 11:18:46.549221 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4661 11:18:46.552599 Total UI for P1: 0, mck2ui 16
4662 11:18:46.555965 best dqsien dly found for B1: ( 0, 13, 16)
4663 11:18:46.559108 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4664 11:18:46.561867 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4665 11:18:46.561953
4666 11:18:46.565687 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4667 11:18:46.571963 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4668 11:18:46.572066 [Gating] SW calibration Done
4669 11:18:46.572131 ==
4670 11:18:46.575708 Dram Type= 6, Freq= 0, CH_1, rank 1
4671 11:18:46.582600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4672 11:18:46.582708 ==
4673 11:18:46.582774 RX Vref Scan: 0
4674 11:18:46.582833
4675 11:18:46.585197 RX Vref 0 -> 0, step: 1
4676 11:18:46.585280
4677 11:18:46.588973 RX Delay -230 -> 252, step: 16
4678 11:18:46.591930 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4679 11:18:46.595280 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4680 11:18:46.598623 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4681 11:18:46.605479 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4682 11:18:46.608599 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4683 11:18:46.611938 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4684 11:18:46.615346 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4685 11:18:46.621976 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4686 11:18:46.625137 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4687 11:18:46.628521 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4688 11:18:46.632829 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4689 11:18:46.634894 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4690 11:18:46.641518 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4691 11:18:46.645159 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4692 11:18:46.648414 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4693 11:18:46.651979 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4694 11:18:46.655220 ==
4695 11:18:46.658275 Dram Type= 6, Freq= 0, CH_1, rank 1
4696 11:18:46.661630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4697 11:18:46.661723 ==
4698 11:18:46.661788 DQS Delay:
4699 11:18:46.665117 DQS0 = 0, DQS1 = 0
4700 11:18:46.665202 DQM Delay:
4701 11:18:46.668398 DQM0 = 41, DQM1 = 36
4702 11:18:46.668484 DQ Delay:
4703 11:18:46.671474 DQ0 =41, DQ1 =33, DQ2 =25, DQ3 =41
4704 11:18:46.674914 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4705 11:18:46.678509 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =25
4706 11:18:46.681773 DQ12 =41, DQ13 =49, DQ14 =41, DQ15 =41
4707 11:18:46.681862
4708 11:18:46.681926
4709 11:18:46.681985 ==
4710 11:18:46.685277 Dram Type= 6, Freq= 0, CH_1, rank 1
4711 11:18:46.688397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4712 11:18:46.688485 ==
4713 11:18:46.688551
4714 11:18:46.688610
4715 11:18:46.691272 TX Vref Scan disable
4716 11:18:46.694785 == TX Byte 0 ==
4717 11:18:46.698108 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4718 11:18:46.702082 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4719 11:18:46.705100 == TX Byte 1 ==
4720 11:18:46.708342 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4721 11:18:46.711341 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4722 11:18:46.711440 ==
4723 11:18:46.715064 Dram Type= 6, Freq= 0, CH_1, rank 1
4724 11:18:46.718199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4725 11:18:46.721663 ==
4726 11:18:46.721758
4727 11:18:46.721823
4728 11:18:46.721884 TX Vref Scan disable
4729 11:18:46.725343 == TX Byte 0 ==
4730 11:18:46.728884 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4731 11:18:46.735548 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4732 11:18:46.735658 == TX Byte 1 ==
4733 11:18:46.738849 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4734 11:18:46.745258 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4735 11:18:46.745366
4736 11:18:46.745432 [DATLAT]
4737 11:18:46.745493 Freq=600, CH1 RK1
4738 11:18:46.745551
4739 11:18:46.748702 DATLAT Default: 0x9
4740 11:18:46.748788 0, 0xFFFF, sum = 0
4741 11:18:46.751665 1, 0xFFFF, sum = 0
4742 11:18:46.755224 2, 0xFFFF, sum = 0
4743 11:18:46.755315 3, 0xFFFF, sum = 0
4744 11:18:46.758621 4, 0xFFFF, sum = 0
4745 11:18:46.758711 5, 0xFFFF, sum = 0
4746 11:18:46.761585 6, 0xFFFF, sum = 0
4747 11:18:46.761673 7, 0xFFFF, sum = 0
4748 11:18:46.765199 8, 0x0, sum = 1
4749 11:18:46.765289 9, 0x0, sum = 2
4750 11:18:46.768353 10, 0x0, sum = 3
4751 11:18:46.768440 11, 0x0, sum = 4
4752 11:18:46.768506 best_step = 9
4753 11:18:46.768566
4754 11:18:46.771378 ==
4755 11:18:46.771462 Dram Type= 6, Freq= 0, CH_1, rank 1
4756 11:18:46.778494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4757 11:18:46.778602 ==
4758 11:18:46.778671 RX Vref Scan: 0
4759 11:18:46.778732
4760 11:18:46.781829 RX Vref 0 -> 0, step: 1
4761 11:18:46.781914
4762 11:18:46.785000 RX Delay -179 -> 252, step: 8
4763 11:18:46.791494 iDelay=205, Bit 0, Center 44 (-107 ~ 196) 304
4764 11:18:46.794680 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4765 11:18:46.798141 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4766 11:18:46.801903 iDelay=205, Bit 3, Center 36 (-115 ~ 188) 304
4767 11:18:46.804821 iDelay=205, Bit 4, Center 40 (-115 ~ 196) 312
4768 11:18:46.811704 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4769 11:18:46.814936 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4770 11:18:46.817972 iDelay=205, Bit 7, Center 36 (-115 ~ 188) 304
4771 11:18:46.821496 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4772 11:18:46.825102 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4773 11:18:46.831281 iDelay=205, Bit 10, Center 32 (-123 ~ 188) 312
4774 11:18:46.834734 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4775 11:18:46.837874 iDelay=205, Bit 12, Center 40 (-107 ~ 188) 296
4776 11:18:46.841557 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4777 11:18:46.848223 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4778 11:18:46.851645 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4779 11:18:46.851746 ==
4780 11:18:46.854766 Dram Type= 6, Freq= 0, CH_1, rank 1
4781 11:18:46.858069 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4782 11:18:46.858159 ==
4783 11:18:46.861024 DQS Delay:
4784 11:18:46.861113 DQS0 = 0, DQS1 = 0
4785 11:18:46.864325 DQM Delay:
4786 11:18:46.864419 DQM0 = 38, DQM1 = 33
4787 11:18:46.864485 DQ Delay:
4788 11:18:46.867647 DQ0 =44, DQ1 =32, DQ2 =24, DQ3 =36
4789 11:18:46.871039 DQ4 =40, DQ5 =48, DQ6 =48, DQ7 =36
4790 11:18:46.874470 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =28
4791 11:18:46.877838 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4792 11:18:46.877940
4793 11:18:46.878016
4794 11:18:46.887563 [DQSOSCAuto] RK1, (LSB)MR18= 0x3645, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 399 ps
4795 11:18:46.891048 CH1 RK1: MR19=808, MR18=3645
4796 11:18:46.894164 CH1_RK1: MR19=0x808, MR18=0x3645, DQSOSC=396, MR23=63, INC=167, DEC=111
4797 11:18:46.897820 [RxdqsGatingPostProcess] freq 600
4798 11:18:46.904525 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4799 11:18:46.907638 Pre-setting of DQS Precalculation
4800 11:18:46.910607 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4801 11:18:46.920756 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4802 11:18:46.927309 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4803 11:18:46.927470
4804 11:18:46.927538
4805 11:18:46.930743 [Calibration Summary] 1200 Mbps
4806 11:18:46.930828 CH 0, Rank 0
4807 11:18:46.934507 SW Impedance : PASS
4808 11:18:46.934595 DUTY Scan : NO K
4809 11:18:46.937156 ZQ Calibration : PASS
4810 11:18:46.940554 Jitter Meter : NO K
4811 11:18:46.940645 CBT Training : PASS
4812 11:18:46.943741 Write leveling : PASS
4813 11:18:46.947201 RX DQS gating : PASS
4814 11:18:46.947291 RX DQ/DQS(RDDQC) : PASS
4815 11:18:46.950863 TX DQ/DQS : PASS
4816 11:18:46.953617 RX DATLAT : PASS
4817 11:18:46.953705 RX DQ/DQS(Engine): PASS
4818 11:18:46.956966 TX OE : NO K
4819 11:18:46.957052 All Pass.
4820 11:18:46.957117
4821 11:18:46.960321 CH 0, Rank 1
4822 11:18:46.960406 SW Impedance : PASS
4823 11:18:46.964437 DUTY Scan : NO K
4824 11:18:46.967115 ZQ Calibration : PASS
4825 11:18:46.967202 Jitter Meter : NO K
4826 11:18:46.970347 CBT Training : PASS
4827 11:18:46.973879 Write leveling : PASS
4828 11:18:46.973972 RX DQS gating : PASS
4829 11:18:46.977134 RX DQ/DQS(RDDQC) : PASS
4830 11:18:46.980095 TX DQ/DQS : PASS
4831 11:18:46.980183 RX DATLAT : PASS
4832 11:18:46.983477 RX DQ/DQS(Engine): PASS
4833 11:18:46.983563 TX OE : NO K
4834 11:18:46.986644 All Pass.
4835 11:18:46.986728
4836 11:18:46.986791 CH 1, Rank 0
4837 11:18:46.990166 SW Impedance : PASS
4838 11:18:46.990251 DUTY Scan : NO K
4839 11:18:46.993453 ZQ Calibration : PASS
4840 11:18:46.996686 Jitter Meter : NO K
4841 11:18:46.996774 CBT Training : PASS
4842 11:18:47.000529 Write leveling : PASS
4843 11:18:47.003264 RX DQS gating : PASS
4844 11:18:47.003377 RX DQ/DQS(RDDQC) : PASS
4845 11:18:47.006505 TX DQ/DQS : PASS
4846 11:18:47.010063 RX DATLAT : PASS
4847 11:18:47.010153 RX DQ/DQS(Engine): PASS
4848 11:18:47.013428 TX OE : NO K
4849 11:18:47.013514 All Pass.
4850 11:18:47.013576
4851 11:18:47.016548 CH 1, Rank 1
4852 11:18:47.016687 SW Impedance : PASS
4853 11:18:47.019840 DUTY Scan : NO K
4854 11:18:47.023683 ZQ Calibration : PASS
4855 11:18:47.023774 Jitter Meter : NO K
4856 11:18:47.026595 CBT Training : PASS
4857 11:18:47.030194 Write leveling : PASS
4858 11:18:47.030282 RX DQS gating : PASS
4859 11:18:47.033285 RX DQ/DQS(RDDQC) : PASS
4860 11:18:47.033369 TX DQ/DQS : PASS
4861 11:18:47.037174 RX DATLAT : PASS
4862 11:18:47.039782 RX DQ/DQS(Engine): PASS
4863 11:18:47.039867 TX OE : NO K
4864 11:18:47.043290 All Pass.
4865 11:18:47.043414
4866 11:18:47.043491 DramC Write-DBI off
4867 11:18:47.046419 PER_BANK_REFRESH: Hybrid Mode
4868 11:18:47.049527 TX_TRACKING: ON
4869 11:18:47.056565 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4870 11:18:47.059877 [FAST_K] Save calibration result to emmc
4871 11:18:47.066184 dramc_set_vcore_voltage set vcore to 662500
4872 11:18:47.066292 Read voltage for 933, 3
4873 11:18:47.066361 Vio18 = 0
4874 11:18:47.069604 Vcore = 662500
4875 11:18:47.069687 Vdram = 0
4876 11:18:47.069751 Vddq = 0
4877 11:18:47.073054 Vmddr = 0
4878 11:18:47.076427 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4879 11:18:47.082859 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4880 11:18:47.083009 MEM_TYPE=3, freq_sel=17
4881 11:18:47.086089 sv_algorithm_assistance_LP4_1600
4882 11:18:47.092893 ============ PULL DRAM RESETB DOWN ============
4883 11:18:47.096526 ========== PULL DRAM RESETB DOWN end =========
4884 11:18:47.099574 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4885 11:18:47.103088 ===================================
4886 11:18:47.105892 LPDDR4 DRAM CONFIGURATION
4887 11:18:47.109624 ===================================
4888 11:18:47.112682 EX_ROW_EN[0] = 0x0
4889 11:18:47.112776 EX_ROW_EN[1] = 0x0
4890 11:18:47.115887 LP4Y_EN = 0x0
4891 11:18:47.115972 WORK_FSP = 0x0
4892 11:18:47.119277 WL = 0x3
4893 11:18:47.119410 RL = 0x3
4894 11:18:47.122653 BL = 0x2
4895 11:18:47.122738 RPST = 0x0
4896 11:18:47.126274 RD_PRE = 0x0
4897 11:18:47.126362 WR_PRE = 0x1
4898 11:18:47.129554 WR_PST = 0x0
4899 11:18:47.129640 DBI_WR = 0x0
4900 11:18:47.132427 DBI_RD = 0x0
4901 11:18:47.132510 OTF = 0x1
4902 11:18:47.136210 ===================================
4903 11:18:47.139083 ===================================
4904 11:18:47.142686 ANA top config
4905 11:18:47.145725 ===================================
4906 11:18:47.149285 DLL_ASYNC_EN = 0
4907 11:18:47.149370 ALL_SLAVE_EN = 1
4908 11:18:47.152609 NEW_RANK_MODE = 1
4909 11:18:47.155904 DLL_IDLE_MODE = 1
4910 11:18:47.158818 LP45_APHY_COMB_EN = 1
4911 11:18:47.162545 TX_ODT_DIS = 1
4912 11:18:47.162636 NEW_8X_MODE = 1
4913 11:18:47.165904 ===================================
4914 11:18:47.169066 ===================================
4915 11:18:47.172262 data_rate = 1866
4916 11:18:47.175223 CKR = 1
4917 11:18:47.178835 DQ_P2S_RATIO = 8
4918 11:18:47.181955 ===================================
4919 11:18:47.185519 CA_P2S_RATIO = 8
4920 11:18:47.189406 DQ_CA_OPEN = 0
4921 11:18:47.189498 DQ_SEMI_OPEN = 0
4922 11:18:47.192577 CA_SEMI_OPEN = 0
4923 11:18:47.195541 CA_FULL_RATE = 0
4924 11:18:47.198779 DQ_CKDIV4_EN = 1
4925 11:18:47.202175 CA_CKDIV4_EN = 1
4926 11:18:47.205338 CA_PREDIV_EN = 0
4927 11:18:47.205429 PH8_DLY = 0
4928 11:18:47.209371 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4929 11:18:47.211930 DQ_AAMCK_DIV = 4
4930 11:18:47.215271 CA_AAMCK_DIV = 4
4931 11:18:47.218647 CA_ADMCK_DIV = 4
4932 11:18:47.221807 DQ_TRACK_CA_EN = 0
4933 11:18:47.221902 CA_PICK = 933
4934 11:18:47.225282 CA_MCKIO = 933
4935 11:18:47.228677 MCKIO_SEMI = 0
4936 11:18:47.232392 PLL_FREQ = 3732
4937 11:18:47.235322 DQ_UI_PI_RATIO = 32
4938 11:18:47.238793 CA_UI_PI_RATIO = 0
4939 11:18:47.241703 ===================================
4940 11:18:47.246109 ===================================
4941 11:18:47.246203 memory_type:LPDDR4
4942 11:18:47.248734 GP_NUM : 10
4943 11:18:47.251929 SRAM_EN : 1
4944 11:18:47.252018 MD32_EN : 0
4945 11:18:47.255189 ===================================
4946 11:18:47.258255 [ANA_INIT] >>>>>>>>>>>>>>
4947 11:18:47.262059 <<<<<< [CONFIGURE PHASE]: ANA_TX
4948 11:18:47.265096 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4949 11:18:47.268195 ===================================
4950 11:18:47.271678 data_rate = 1866,PCW = 0X8f00
4951 11:18:47.275015 ===================================
4952 11:18:47.278393 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4953 11:18:47.281599 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4954 11:18:47.288115 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4955 11:18:47.291685 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4956 11:18:47.295463 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4957 11:18:47.298326 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4958 11:18:47.301614 [ANA_INIT] flow start
4959 11:18:47.305401 [ANA_INIT] PLL >>>>>>>>
4960 11:18:47.305494 [ANA_INIT] PLL <<<<<<<<
4961 11:18:47.308296 [ANA_INIT] MIDPI >>>>>>>>
4962 11:18:47.311722 [ANA_INIT] MIDPI <<<<<<<<
4963 11:18:47.314851 [ANA_INIT] DLL >>>>>>>>
4964 11:18:47.314942 [ANA_INIT] flow end
4965 11:18:47.318533 ============ LP4 DIFF to SE enter ============
4966 11:18:47.325062 ============ LP4 DIFF to SE exit ============
4967 11:18:47.325176 [ANA_INIT] <<<<<<<<<<<<<
4968 11:18:47.328420 [Flow] Enable top DCM control >>>>>
4969 11:18:47.331573 [Flow] Enable top DCM control <<<<<
4970 11:18:47.335454 Enable DLL master slave shuffle
4971 11:18:47.341295 ==============================================================
4972 11:18:47.341401 Gating Mode config
4973 11:18:47.347862 ==============================================================
4974 11:18:47.351460 Config description:
4975 11:18:47.361401 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4976 11:18:47.368032 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4977 11:18:47.371322 SELPH_MODE 0: By rank 1: By Phase
4978 11:18:47.377941 ==============================================================
4979 11:18:47.381039 GAT_TRACK_EN = 1
4980 11:18:47.384438 RX_GATING_MODE = 2
4981 11:18:47.384527 RX_GATING_TRACK_MODE = 2
4982 11:18:47.388336 SELPH_MODE = 1
4983 11:18:47.390926 PICG_EARLY_EN = 1
4984 11:18:47.394672 VALID_LAT_VALUE = 1
4985 11:18:47.401226 ==============================================================
4986 11:18:47.404293 Enter into Gating configuration >>>>
4987 11:18:47.407522 Exit from Gating configuration <<<<
4988 11:18:47.411181 Enter into DVFS_PRE_config >>>>>
4989 11:18:47.421017 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4990 11:18:47.424715 Exit from DVFS_PRE_config <<<<<
4991 11:18:47.427487 Enter into PICG configuration >>>>
4992 11:18:47.430974 Exit from PICG configuration <<<<
4993 11:18:47.434335 [RX_INPUT] configuration >>>>>
4994 11:18:47.437732 [RX_INPUT] configuration <<<<<
4995 11:18:47.440847 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4996 11:18:47.447561 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4997 11:18:47.454007 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4998 11:18:47.460905 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4999 11:18:47.464037 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5000 11:18:47.470497 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5001 11:18:47.474134 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5002 11:18:47.480543 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5003 11:18:47.483995 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5004 11:18:47.487360 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5005 11:18:47.491004 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5006 11:18:47.497464 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5007 11:18:47.500621 ===================================
5008 11:18:47.500717 LPDDR4 DRAM CONFIGURATION
5009 11:18:47.503795 ===================================
5010 11:18:47.507289 EX_ROW_EN[0] = 0x0
5011 11:18:47.510489 EX_ROW_EN[1] = 0x0
5012 11:18:47.510576 LP4Y_EN = 0x0
5013 11:18:47.514127 WORK_FSP = 0x0
5014 11:18:47.514213 WL = 0x3
5015 11:18:47.517443 RL = 0x3
5016 11:18:47.517561 BL = 0x2
5017 11:18:47.520584 RPST = 0x0
5018 11:18:47.520671 RD_PRE = 0x0
5019 11:18:47.524116 WR_PRE = 0x1
5020 11:18:47.524203 WR_PST = 0x0
5021 11:18:47.527552 DBI_WR = 0x0
5022 11:18:47.527640 DBI_RD = 0x0
5023 11:18:47.530452 OTF = 0x1
5024 11:18:47.534125 ===================================
5025 11:18:47.537462 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5026 11:18:47.540691 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5027 11:18:47.546985 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5028 11:18:47.550524 ===================================
5029 11:18:47.550623 LPDDR4 DRAM CONFIGURATION
5030 11:18:47.553775 ===================================
5031 11:18:47.557190 EX_ROW_EN[0] = 0x10
5032 11:18:47.560338 EX_ROW_EN[1] = 0x0
5033 11:18:47.560428 LP4Y_EN = 0x0
5034 11:18:47.563633 WORK_FSP = 0x0
5035 11:18:47.563718 WL = 0x3
5036 11:18:47.566988 RL = 0x3
5037 11:18:47.567074 BL = 0x2
5038 11:18:47.570698 RPST = 0x0
5039 11:18:47.570786 RD_PRE = 0x0
5040 11:18:47.573514 WR_PRE = 0x1
5041 11:18:47.573597 WR_PST = 0x0
5042 11:18:47.577469 DBI_WR = 0x0
5043 11:18:47.577557 DBI_RD = 0x0
5044 11:18:47.580417 OTF = 0x1
5045 11:18:47.583543 ===================================
5046 11:18:47.590282 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5047 11:18:47.594417 nWR fixed to 30
5048 11:18:47.594512 [ModeRegInit_LP4] CH0 RK0
5049 11:18:47.597175 [ModeRegInit_LP4] CH0 RK1
5050 11:18:47.600287 [ModeRegInit_LP4] CH1 RK0
5051 11:18:47.603371 [ModeRegInit_LP4] CH1 RK1
5052 11:18:47.603473 match AC timing 9
5053 11:18:47.606803 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5054 11:18:47.613465 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5055 11:18:47.616921 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5056 11:18:47.620028 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5057 11:18:47.627076 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5058 11:18:47.627190 ==
5059 11:18:47.630225 Dram Type= 6, Freq= 0, CH_0, rank 0
5060 11:18:47.633705 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5061 11:18:47.633799 ==
5062 11:18:47.639980 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5063 11:18:47.646904 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5064 11:18:47.649961 [CA 0] Center 38 (8~69) winsize 62
5065 11:18:47.653163 [CA 1] Center 38 (7~69) winsize 63
5066 11:18:47.656732 [CA 2] Center 35 (5~66) winsize 62
5067 11:18:47.659707 [CA 3] Center 35 (5~65) winsize 61
5068 11:18:47.663248 [CA 4] Center 34 (4~64) winsize 61
5069 11:18:47.666223 [CA 5] Center 33 (3~64) winsize 62
5070 11:18:47.666310
5071 11:18:47.669486 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5072 11:18:47.669571
5073 11:18:47.673139 [CATrainingPosCal] consider 1 rank data
5074 11:18:47.676122 u2DelayCellTimex100 = 270/100 ps
5075 11:18:47.679542 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5076 11:18:47.682865 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5077 11:18:47.686679 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5078 11:18:47.689903 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5079 11:18:47.693049 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5080 11:18:47.695947 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5081 11:18:47.696036
5082 11:18:47.702744 CA PerBit enable=1, Macro0, CA PI delay=33
5083 11:18:47.702842
5084 11:18:47.702906 [CBTSetCACLKResult] CA Dly = 33
5085 11:18:47.706162 CS Dly: 6 (0~37)
5086 11:18:47.706248 ==
5087 11:18:47.709520 Dram Type= 6, Freq= 0, CH_0, rank 1
5088 11:18:47.712767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5089 11:18:47.712859 ==
5090 11:18:47.719492 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5091 11:18:47.726318 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5092 11:18:47.729550 [CA 0] Center 38 (7~69) winsize 63
5093 11:18:47.732984 [CA 1] Center 38 (7~69) winsize 63
5094 11:18:47.736153 [CA 2] Center 35 (5~66) winsize 62
5095 11:18:47.739587 [CA 3] Center 35 (4~66) winsize 63
5096 11:18:47.742989 [CA 4] Center 34 (3~65) winsize 63
5097 11:18:47.746175 [CA 5] Center 33 (3~64) winsize 62
5098 11:18:47.746262
5099 11:18:47.749754 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5100 11:18:47.749840
5101 11:18:47.752544 [CATrainingPosCal] consider 2 rank data
5102 11:18:47.756304 u2DelayCellTimex100 = 270/100 ps
5103 11:18:47.759602 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5104 11:18:47.762829 CA1 delay=38 (7~69),Diff = 5 PI (31 cell)
5105 11:18:47.766360 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5106 11:18:47.769400 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5107 11:18:47.772635 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5108 11:18:47.776119 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5109 11:18:47.776207
5110 11:18:47.782485 CA PerBit enable=1, Macro0, CA PI delay=33
5111 11:18:47.782584
5112 11:18:47.785956 [CBTSetCACLKResult] CA Dly = 33
5113 11:18:47.786053 CS Dly: 7 (0~39)
5114 11:18:47.786119
5115 11:18:47.789123 ----->DramcWriteLeveling(PI) begin...
5116 11:18:47.789209 ==
5117 11:18:47.792814 Dram Type= 6, Freq= 0, CH_0, rank 0
5118 11:18:47.796567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5119 11:18:47.799287 ==
5120 11:18:47.799380 Write leveling (Byte 0): 32 => 32
5121 11:18:47.803015 Write leveling (Byte 1): 29 => 29
5122 11:18:47.805980 DramcWriteLeveling(PI) end<-----
5123 11:18:47.806065
5124 11:18:47.806128 ==
5125 11:18:47.809261 Dram Type= 6, Freq= 0, CH_0, rank 0
5126 11:18:47.815507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5127 11:18:47.815609 ==
5128 11:18:47.815675 [Gating] SW mode calibration
5129 11:18:47.825740 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5130 11:18:47.829015 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5131 11:18:47.835787 0 14 0 | B1->B0 | 2322 2c2c | 1 0 | (0 0) (0 0)
5132 11:18:47.838982 0 14 4 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
5133 11:18:47.842344 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5134 11:18:47.845702 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5135 11:18:47.852107 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5136 11:18:47.855573 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5137 11:18:47.859037 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5138 11:18:47.865550 0 14 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5139 11:18:47.869139 0 15 0 | B1->B0 | 3030 2e2e | 0 0 | (1 0) (1 0)
5140 11:18:47.872150 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5141 11:18:47.878518 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5142 11:18:47.882211 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5143 11:18:47.885899 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5144 11:18:47.892027 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5145 11:18:47.895305 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5146 11:18:47.898806 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5147 11:18:47.905404 1 0 0 | B1->B0 | 3030 3e3e | 0 1 | (0 0) (0 0)
5148 11:18:47.908636 1 0 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5149 11:18:47.912683 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5150 11:18:47.918969 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5151 11:18:47.921872 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5152 11:18:47.925541 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5153 11:18:47.932014 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5154 11:18:47.935438 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5155 11:18:47.938544 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5156 11:18:47.945544 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5157 11:18:47.948798 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5158 11:18:47.952078 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5159 11:18:47.958559 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5160 11:18:47.961582 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5161 11:18:47.965070 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5162 11:18:47.971796 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5163 11:18:47.975373 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5164 11:18:47.978227 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5165 11:18:47.985063 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5166 11:18:47.988370 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5167 11:18:47.991639 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5168 11:18:47.998361 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5169 11:18:48.001717 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5170 11:18:48.004818 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5171 11:18:48.011913 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5172 11:18:48.014512 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5173 11:18:48.017851 Total UI for P1: 0, mck2ui 16
5174 11:18:48.021296 best dqsien dly found for B0: ( 1, 3, 0)
5175 11:18:48.024662 Total UI for P1: 0, mck2ui 16
5176 11:18:48.027831 best dqsien dly found for B1: ( 1, 3, 0)
5177 11:18:48.031611 best DQS0 dly(MCK, UI, PI) = (1, 3, 0)
5178 11:18:48.034651 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5179 11:18:48.034740
5180 11:18:48.038032 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 0)
5181 11:18:48.041323 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5182 11:18:48.044437 [Gating] SW calibration Done
5183 11:18:48.044525 ==
5184 11:18:48.047633 Dram Type= 6, Freq= 0, CH_0, rank 0
5185 11:18:48.051143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5186 11:18:48.051232 ==
5187 11:18:48.054569 RX Vref Scan: 0
5188 11:18:48.054656
5189 11:18:48.054721 RX Vref 0 -> 0, step: 1
5190 11:18:48.054782
5191 11:18:48.057719 RX Delay -80 -> 252, step: 8
5192 11:18:48.064712 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5193 11:18:48.067711 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5194 11:18:48.071158 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5195 11:18:48.074497 iDelay=200, Bit 3, Center 91 (-8 ~ 191) 200
5196 11:18:48.077574 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5197 11:18:48.081325 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5198 11:18:48.084368 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5199 11:18:48.090939 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5200 11:18:48.094560 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5201 11:18:48.097489 iDelay=200, Bit 9, Center 75 (-16 ~ 167) 184
5202 11:18:48.101152 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5203 11:18:48.104279 iDelay=200, Bit 11, Center 79 (-16 ~ 175) 192
5204 11:18:48.110822 iDelay=200, Bit 12, Center 91 (-8 ~ 191) 200
5205 11:18:48.114551 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5206 11:18:48.117597 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5207 11:18:48.120942 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5208 11:18:48.121056 ==
5209 11:18:48.124271 Dram Type= 6, Freq= 0, CH_0, rank 0
5210 11:18:48.127593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5211 11:18:48.131173 ==
5212 11:18:48.131261 DQS Delay:
5213 11:18:48.131326 DQS0 = 0, DQS1 = 0
5214 11:18:48.134460 DQM Delay:
5215 11:18:48.134544 DQM0 = 97, DQM1 = 87
5216 11:18:48.137381 DQ Delay:
5217 11:18:48.141133 DQ0 =95, DQ1 =103, DQ2 =95, DQ3 =91
5218 11:18:48.144628 DQ4 =103, DQ5 =87, DQ6 =103, DQ7 =103
5219 11:18:48.147696 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5220 11:18:48.151235 DQ12 =91, DQ13 =95, DQ14 =95, DQ15 =95
5221 11:18:48.151323
5222 11:18:48.151457
5223 11:18:48.151530 ==
5224 11:18:48.154055 Dram Type= 6, Freq= 0, CH_0, rank 0
5225 11:18:48.157594 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5226 11:18:48.157682 ==
5227 11:18:48.157748
5228 11:18:48.157807
5229 11:18:48.160798 TX Vref Scan disable
5230 11:18:48.160880 == TX Byte 0 ==
5231 11:18:48.167858 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5232 11:18:48.171096 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5233 11:18:48.171185 == TX Byte 1 ==
5234 11:18:48.177389 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5235 11:18:48.180642 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5236 11:18:48.180733 ==
5237 11:18:48.184280 Dram Type= 6, Freq= 0, CH_0, rank 0
5238 11:18:48.187243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5239 11:18:48.187344 ==
5240 11:18:48.187451
5241 11:18:48.187524
5242 11:18:48.190765 TX Vref Scan disable
5243 11:18:48.194149 == TX Byte 0 ==
5244 11:18:48.197717 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5245 11:18:48.200672 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5246 11:18:48.204196 == TX Byte 1 ==
5247 11:18:48.207483 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5248 11:18:48.210415 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5249 11:18:48.213853
5250 11:18:48.213940 [DATLAT]
5251 11:18:48.214005 Freq=933, CH0 RK0
5252 11:18:48.214066
5253 11:18:48.216993 DATLAT Default: 0xd
5254 11:18:48.217076 0, 0xFFFF, sum = 0
5255 11:18:48.220408 1, 0xFFFF, sum = 0
5256 11:18:48.220502 2, 0xFFFF, sum = 0
5257 11:18:48.223669 3, 0xFFFF, sum = 0
5258 11:18:48.223756 4, 0xFFFF, sum = 0
5259 11:18:48.227045 5, 0xFFFF, sum = 0
5260 11:18:48.230453 6, 0xFFFF, sum = 0
5261 11:18:48.230542 7, 0xFFFF, sum = 0
5262 11:18:48.233571 8, 0xFFFF, sum = 0
5263 11:18:48.233658 9, 0xFFFF, sum = 0
5264 11:18:48.237141 10, 0x0, sum = 1
5265 11:18:48.237229 11, 0x0, sum = 2
5266 11:18:48.237296 12, 0x0, sum = 3
5267 11:18:48.240085 13, 0x0, sum = 4
5268 11:18:48.240171 best_step = 11
5269 11:18:48.240237
5270 11:18:48.243202 ==
5271 11:18:48.247125 Dram Type= 6, Freq= 0, CH_0, rank 0
5272 11:18:48.250082 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5273 11:18:48.250171 ==
5274 11:18:48.250235 RX Vref Scan: 1
5275 11:18:48.250296
5276 11:18:48.253300 RX Vref 0 -> 0, step: 1
5277 11:18:48.253385
5278 11:18:48.256975 RX Delay -61 -> 252, step: 4
5279 11:18:48.257061
5280 11:18:48.259912 Set Vref, RX VrefLevel [Byte0]: 52
5281 11:18:48.263226 [Byte1]: 51
5282 11:18:48.263312
5283 11:18:48.266805 Final RX Vref Byte 0 = 52 to rank0
5284 11:18:48.269854 Final RX Vref Byte 1 = 51 to rank0
5285 11:18:48.273398 Final RX Vref Byte 0 = 52 to rank1
5286 11:18:48.276840 Final RX Vref Byte 1 = 51 to rank1==
5287 11:18:48.279859 Dram Type= 6, Freq= 0, CH_0, rank 0
5288 11:18:48.283225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5289 11:18:48.286226 ==
5290 11:18:48.286317 DQS Delay:
5291 11:18:48.286385 DQS0 = 0, DQS1 = 0
5292 11:18:48.289587 DQM Delay:
5293 11:18:48.289673 DQM0 = 97, DQM1 = 88
5294 11:18:48.293812 DQ Delay:
5295 11:18:48.293902 DQ0 =98, DQ1 =98, DQ2 =92, DQ3 =94
5296 11:18:48.296298 DQ4 =98, DQ5 =86, DQ6 =106, DQ7 =104
5297 11:18:48.299620 DQ8 =80, DQ9 =78, DQ10 =86, DQ11 =80
5298 11:18:48.306496 DQ12 =96, DQ13 =90, DQ14 =100, DQ15 =100
5299 11:18:48.306608
5300 11:18:48.306674
5301 11:18:48.313203 [DQSOSCAuto] RK0, (LSB)MR18= 0x1601, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 414 ps
5302 11:18:48.316792 CH0 RK0: MR19=505, MR18=1601
5303 11:18:48.323315 CH0_RK0: MR19=0x505, MR18=0x1601, DQSOSC=414, MR23=63, INC=63, DEC=42
5304 11:18:48.323474
5305 11:18:48.326418 ----->DramcWriteLeveling(PI) begin...
5306 11:18:48.326505 ==
5307 11:18:48.330029 Dram Type= 6, Freq= 0, CH_0, rank 1
5308 11:18:48.332955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5309 11:18:48.333044 ==
5310 11:18:48.336265 Write leveling (Byte 0): 31 => 31
5311 11:18:48.339837 Write leveling (Byte 1): 31 => 31
5312 11:18:48.342936 DramcWriteLeveling(PI) end<-----
5313 11:18:48.343026
5314 11:18:48.343091 ==
5315 11:18:48.346768 Dram Type= 6, Freq= 0, CH_0, rank 1
5316 11:18:48.349633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5317 11:18:48.349721 ==
5318 11:18:48.352852 [Gating] SW mode calibration
5319 11:18:48.360121 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5320 11:18:48.366070 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5321 11:18:48.369749 0 14 0 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
5322 11:18:48.373475 0 14 4 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
5323 11:18:48.379503 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5324 11:18:48.382852 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5325 11:18:48.386388 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5326 11:18:48.392776 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5327 11:18:48.396247 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5328 11:18:48.399331 0 14 28 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 1)
5329 11:18:48.406201 0 15 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
5330 11:18:48.409670 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5331 11:18:48.412856 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5332 11:18:48.419558 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5333 11:18:48.422782 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5334 11:18:48.425900 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5335 11:18:48.432760 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5336 11:18:48.436455 0 15 28 | B1->B0 | 2929 3b3b | 0 0 | (0 0) (0 0)
5337 11:18:48.439549 1 0 0 | B1->B0 | 3232 4646 | 0 0 | (1 1) (0 0)
5338 11:18:48.446386 1 0 4 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
5339 11:18:48.449136 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5340 11:18:48.452490 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5341 11:18:48.459103 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5342 11:18:48.462734 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5343 11:18:48.465617 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5344 11:18:48.472330 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5345 11:18:48.476288 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5346 11:18:48.479188 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5347 11:18:48.486286 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5348 11:18:48.489393 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5349 11:18:48.492554 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5350 11:18:48.495868 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5351 11:18:48.502442 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5352 11:18:48.505658 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5353 11:18:48.509233 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 11:18:48.515635 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 11:18:48.519065 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 11:18:48.522450 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 11:18:48.528672 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 11:18:48.532092 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 11:18:48.535389 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5360 11:18:48.542350 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5361 11:18:48.545351 Total UI for P1: 0, mck2ui 16
5362 11:18:48.548761 best dqsien dly found for B0: ( 1, 2, 24)
5363 11:18:48.552118 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5364 11:18:48.555344 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5365 11:18:48.558651 Total UI for P1: 0, mck2ui 16
5366 11:18:48.562003 best dqsien dly found for B1: ( 1, 2, 30)
5367 11:18:48.565473 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5368 11:18:48.568998 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5369 11:18:48.569083
5370 11:18:48.575223 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5371 11:18:48.578785 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5372 11:18:48.582174 [Gating] SW calibration Done
5373 11:18:48.582259 ==
5374 11:18:48.585676 Dram Type= 6, Freq= 0, CH_0, rank 1
5375 11:18:48.589002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5376 11:18:48.589088 ==
5377 11:18:48.589173 RX Vref Scan: 0
5378 11:18:48.589254
5379 11:18:48.592110 RX Vref 0 -> 0, step: 1
5380 11:18:48.592193
5381 11:18:48.595404 RX Delay -80 -> 252, step: 8
5382 11:18:48.598516 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5383 11:18:48.602654 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5384 11:18:48.605061 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5385 11:18:48.612049 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5386 11:18:48.615477 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5387 11:18:48.618230 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5388 11:18:48.621915 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5389 11:18:48.625617 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5390 11:18:48.628587 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5391 11:18:48.635269 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5392 11:18:48.638553 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5393 11:18:48.641914 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5394 11:18:48.645133 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5395 11:18:48.648259 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5396 11:18:48.651649 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5397 11:18:48.658171 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5398 11:18:48.658256 ==
5399 11:18:48.661427 Dram Type= 6, Freq= 0, CH_0, rank 1
5400 11:18:48.664759 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5401 11:18:48.664844 ==
5402 11:18:48.664929 DQS Delay:
5403 11:18:48.668585 DQS0 = 0, DQS1 = 0
5404 11:18:48.668670 DQM Delay:
5405 11:18:48.672283 DQM0 = 97, DQM1 = 88
5406 11:18:48.672368 DQ Delay:
5407 11:18:48.674749 DQ0 =95, DQ1 =95, DQ2 =95, DQ3 =95
5408 11:18:48.678158 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =103
5409 11:18:48.681485 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5410 11:18:48.684670 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =95
5411 11:18:48.684754
5412 11:18:48.684839
5413 11:18:48.684918 ==
5414 11:18:48.688382 Dram Type= 6, Freq= 0, CH_0, rank 1
5415 11:18:48.691474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5416 11:18:48.694890 ==
5417 11:18:48.694974
5418 11:18:48.695057
5419 11:18:48.695136 TX Vref Scan disable
5420 11:18:48.698053 == TX Byte 0 ==
5421 11:18:48.701340 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5422 11:18:48.704973 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5423 11:18:48.707870 == TX Byte 1 ==
5424 11:18:48.711831 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5425 11:18:48.714439 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5426 11:18:48.718107 ==
5427 11:18:48.718189 Dram Type= 6, Freq= 0, CH_0, rank 1
5428 11:18:48.724887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5429 11:18:48.724976 ==
5430 11:18:48.725040
5431 11:18:48.725100
5432 11:18:48.727884 TX Vref Scan disable
5433 11:18:48.727965 == TX Byte 0 ==
5434 11:18:48.734772 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5435 11:18:48.737859 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5436 11:18:48.737941 == TX Byte 1 ==
5437 11:18:48.744184 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5438 11:18:48.747722 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5439 11:18:48.747805
5440 11:18:48.747867 [DATLAT]
5441 11:18:48.751261 Freq=933, CH0 RK1
5442 11:18:48.751407
5443 11:18:48.751473 DATLAT Default: 0xb
5444 11:18:48.755021 0, 0xFFFF, sum = 0
5445 11:18:48.755103 1, 0xFFFF, sum = 0
5446 11:18:48.757992 2, 0xFFFF, sum = 0
5447 11:18:48.758074 3, 0xFFFF, sum = 0
5448 11:18:48.761564 4, 0xFFFF, sum = 0
5449 11:18:48.761648 5, 0xFFFF, sum = 0
5450 11:18:48.764314 6, 0xFFFF, sum = 0
5451 11:18:48.764396 7, 0xFFFF, sum = 0
5452 11:18:48.767842 8, 0xFFFF, sum = 0
5453 11:18:48.767925 9, 0xFFFF, sum = 0
5454 11:18:48.771010 10, 0x0, sum = 1
5455 11:18:48.771092 11, 0x0, sum = 2
5456 11:18:48.774205 12, 0x0, sum = 3
5457 11:18:48.774288 13, 0x0, sum = 4
5458 11:18:48.777677 best_step = 11
5459 11:18:48.777758
5460 11:18:48.777821 ==
5461 11:18:48.780929 Dram Type= 6, Freq= 0, CH_0, rank 1
5462 11:18:48.784654 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5463 11:18:48.784737 ==
5464 11:18:48.787584 RX Vref Scan: 0
5465 11:18:48.787664
5466 11:18:48.787727 RX Vref 0 -> 0, step: 1
5467 11:18:48.787786
5468 11:18:48.790515 RX Delay -69 -> 252, step: 4
5469 11:18:48.798276 iDelay=199, Bit 0, Center 96 (3 ~ 190) 188
5470 11:18:48.801164 iDelay=199, Bit 1, Center 96 (3 ~ 190) 188
5471 11:18:48.804862 iDelay=199, Bit 2, Center 92 (-1 ~ 186) 188
5472 11:18:48.808145 iDelay=199, Bit 3, Center 94 (-1 ~ 190) 192
5473 11:18:48.811667 iDelay=199, Bit 4, Center 96 (7 ~ 186) 180
5474 11:18:48.814713 iDelay=199, Bit 5, Center 84 (-9 ~ 178) 188
5475 11:18:48.821266 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5476 11:18:48.824741 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5477 11:18:48.827751 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5478 11:18:48.830986 iDelay=199, Bit 9, Center 80 (-9 ~ 170) 180
5479 11:18:48.834621 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5480 11:18:48.841035 iDelay=199, Bit 11, Center 78 (-9 ~ 166) 176
5481 11:18:48.844177 iDelay=199, Bit 12, Center 92 (3 ~ 182) 180
5482 11:18:48.847803 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5483 11:18:48.851004 iDelay=199, Bit 14, Center 98 (11 ~ 186) 176
5484 11:18:48.854121 iDelay=199, Bit 15, Center 96 (7 ~ 186) 180
5485 11:18:48.854202 ==
5486 11:18:48.857571 Dram Type= 6, Freq= 0, CH_0, rank 1
5487 11:18:48.864071 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5488 11:18:48.864157 ==
5489 11:18:48.864222 DQS Delay:
5490 11:18:48.867464 DQS0 = 0, DQS1 = 0
5491 11:18:48.867546 DQM Delay:
5492 11:18:48.867610 DQM0 = 95, DQM1 = 88
5493 11:18:48.870438 DQ Delay:
5494 11:18:48.873996 DQ0 =96, DQ1 =96, DQ2 =92, DQ3 =94
5495 11:18:48.877621 DQ4 =96, DQ5 =84, DQ6 =104, DQ7 =102
5496 11:18:48.880392 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =78
5497 11:18:48.883962 DQ12 =92, DQ13 =92, DQ14 =98, DQ15 =96
5498 11:18:48.884043
5499 11:18:48.884108
5500 11:18:48.890436 [DQSOSCAuto] RK1, (LSB)MR18= 0x1704, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 414 ps
5501 11:18:48.894419 CH0 RK1: MR19=505, MR18=1704
5502 11:18:48.900502 CH0_RK1: MR19=0x505, MR18=0x1704, DQSOSC=414, MR23=63, INC=63, DEC=42
5503 11:18:48.903766 [RxdqsGatingPostProcess] freq 933
5504 11:18:48.906980 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5505 11:18:48.910542 best DQS0 dly(2T, 0.5T) = (0, 11)
5506 11:18:48.913917 best DQS1 dly(2T, 0.5T) = (0, 11)
5507 11:18:48.917522 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
5508 11:18:48.920341 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5509 11:18:48.923835 best DQS0 dly(2T, 0.5T) = (0, 10)
5510 11:18:48.927234 best DQS1 dly(2T, 0.5T) = (0, 10)
5511 11:18:48.930181 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5512 11:18:48.933680 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5513 11:18:48.937020 Pre-setting of DQS Precalculation
5514 11:18:48.940425 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5515 11:18:48.943501 ==
5516 11:18:48.947460 Dram Type= 6, Freq= 0, CH_1, rank 0
5517 11:18:48.950802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5518 11:18:48.950884 ==
5519 11:18:48.953637 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5520 11:18:48.960625 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5521 11:18:48.963862 [CA 0] Center 36 (6~67) winsize 62
5522 11:18:48.967054 [CA 1] Center 36 (6~67) winsize 62
5523 11:18:48.970595 [CA 2] Center 34 (4~64) winsize 61
5524 11:18:48.973961 [CA 3] Center 33 (3~64) winsize 62
5525 11:18:48.977290 [CA 4] Center 34 (4~64) winsize 61
5526 11:18:48.980218 [CA 5] Center 33 (3~64) winsize 62
5527 11:18:48.980299
5528 11:18:48.984197 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5529 11:18:48.984289
5530 11:18:48.987131 [CATrainingPosCal] consider 1 rank data
5531 11:18:48.990344 u2DelayCellTimex100 = 270/100 ps
5532 11:18:48.994019 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5533 11:18:48.997085 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5534 11:18:49.004267 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5535 11:18:49.006886 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5536 11:18:49.010346 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5537 11:18:49.013796 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5538 11:18:49.013877
5539 11:18:49.016873 CA PerBit enable=1, Macro0, CA PI delay=33
5540 11:18:49.016954
5541 11:18:49.020403 [CBTSetCACLKResult] CA Dly = 33
5542 11:18:49.020486 CS Dly: 4 (0~35)
5543 11:18:49.023539 ==
5544 11:18:49.027034 Dram Type= 6, Freq= 0, CH_1, rank 1
5545 11:18:49.030240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5546 11:18:49.030324 ==
5547 11:18:49.033324 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5548 11:18:49.040405 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5549 11:18:49.043789 [CA 0] Center 36 (6~67) winsize 62
5550 11:18:49.047556 [CA 1] Center 37 (7~67) winsize 61
5551 11:18:49.050255 [CA 2] Center 33 (3~64) winsize 62
5552 11:18:49.053704 [CA 3] Center 33 (3~64) winsize 62
5553 11:18:49.056870 [CA 4] Center 34 (4~64) winsize 61
5554 11:18:49.060472 [CA 5] Center 32 (2~63) winsize 62
5555 11:18:49.060554
5556 11:18:49.063750 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5557 11:18:49.063832
5558 11:18:49.066773 [CATrainingPosCal] consider 2 rank data
5559 11:18:49.070192 u2DelayCellTimex100 = 270/100 ps
5560 11:18:49.073543 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5561 11:18:49.080171 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5562 11:18:49.083143 CA2 delay=34 (4~64),Diff = 1 PI (6 cell)
5563 11:18:49.087377 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5564 11:18:49.090032 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5565 11:18:49.093178 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5566 11:18:49.093261
5567 11:18:49.096414 CA PerBit enable=1, Macro0, CA PI delay=33
5568 11:18:49.096497
5569 11:18:49.100026 [CBTSetCACLKResult] CA Dly = 33
5570 11:18:49.103177 CS Dly: 5 (0~38)
5571 11:18:49.103259
5572 11:18:49.106778 ----->DramcWriteLeveling(PI) begin...
5573 11:18:49.106863 ==
5574 11:18:49.109744 Dram Type= 6, Freq= 0, CH_1, rank 0
5575 11:18:49.113081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5576 11:18:49.113165 ==
5577 11:18:49.116658 Write leveling (Byte 0): 24 => 24
5578 11:18:49.119560 Write leveling (Byte 1): 27 => 27
5579 11:18:49.123224 DramcWriteLeveling(PI) end<-----
5580 11:18:49.123340
5581 11:18:49.123460 ==
5582 11:18:49.126158 Dram Type= 6, Freq= 0, CH_1, rank 0
5583 11:18:49.129487 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5584 11:18:49.129572 ==
5585 11:18:49.132949 [Gating] SW mode calibration
5586 11:18:49.139685 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5587 11:18:49.146220 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5588 11:18:49.149445 0 14 0 | B1->B0 | 3232 3333 | 0 0 | (0 0) (0 0)
5589 11:18:49.152881 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5590 11:18:49.159324 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5591 11:18:49.162448 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5592 11:18:49.165875 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5593 11:18:49.172587 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5594 11:18:49.175681 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5595 11:18:49.178975 0 14 28 | B1->B0 | 3030 3030 | 0 0 | (0 1) (0 1)
5596 11:18:49.185485 0 15 0 | B1->B0 | 2727 2727 | 0 0 | (0 0) (0 0)
5597 11:18:49.188697 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5598 11:18:49.192096 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5599 11:18:49.198698 0 15 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5600 11:18:49.202279 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5601 11:18:49.205177 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5602 11:18:49.211905 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5603 11:18:49.215538 0 15 28 | B1->B0 | 2c2b 2828 | 1 0 | (1 1) (0 0)
5604 11:18:49.218766 1 0 0 | B1->B0 | 3f3f 4141 | 1 1 | (0 0) (0 0)
5605 11:18:49.225349 1 0 4 | B1->B0 | 4645 4646 | 1 0 | (0 0) (0 0)
5606 11:18:49.228878 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5607 11:18:49.232241 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5608 11:18:49.238758 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5609 11:18:49.242159 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5610 11:18:49.245173 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5611 11:18:49.251933 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5612 11:18:49.255385 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5613 11:18:49.258909 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5614 11:18:49.265166 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5615 11:18:49.268458 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5616 11:18:49.271741 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5617 11:18:49.279222 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5618 11:18:49.281613 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5619 11:18:49.285237 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5620 11:18:49.292325 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5621 11:18:49.294966 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5622 11:18:49.298597 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5623 11:18:49.304869 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5624 11:18:49.308335 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5625 11:18:49.311869 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5626 11:18:49.318531 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5627 11:18:49.321804 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5628 11:18:49.324948 Total UI for P1: 0, mck2ui 16
5629 11:18:49.328665 best dqsien dly found for B0: ( 1, 2, 24)
5630 11:18:49.331653 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5631 11:18:49.334706 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5632 11:18:49.338464 Total UI for P1: 0, mck2ui 16
5633 11:18:49.341364 best dqsien dly found for B1: ( 1, 2, 28)
5634 11:18:49.344661 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5635 11:18:49.351338 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5636 11:18:49.351433
5637 11:18:49.354922 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5638 11:18:49.358248 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5639 11:18:49.361220 [Gating] SW calibration Done
5640 11:18:49.361302 ==
5641 11:18:49.365137 Dram Type= 6, Freq= 0, CH_1, rank 0
5642 11:18:49.368091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5643 11:18:49.368174 ==
5644 11:18:49.368239 RX Vref Scan: 0
5645 11:18:49.371281
5646 11:18:49.371385 RX Vref 0 -> 0, step: 1
5647 11:18:49.371465
5648 11:18:49.374581 RX Delay -80 -> 252, step: 8
5649 11:18:49.377864 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5650 11:18:49.381026 iDelay=200, Bit 1, Center 91 (-8 ~ 191) 200
5651 11:18:49.387987 iDelay=200, Bit 2, Center 79 (-16 ~ 175) 192
5652 11:18:49.391117 iDelay=200, Bit 3, Center 99 (8 ~ 191) 184
5653 11:18:49.394331 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5654 11:18:49.397764 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5655 11:18:49.400971 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5656 11:18:49.404605 iDelay=200, Bit 7, Center 91 (-8 ~ 191) 200
5657 11:18:49.410812 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5658 11:18:49.414206 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5659 11:18:49.417978 iDelay=200, Bit 10, Center 91 (-8 ~ 191) 200
5660 11:18:49.421185 iDelay=200, Bit 11, Center 83 (-16 ~ 183) 200
5661 11:18:49.424636 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5662 11:18:49.430624 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5663 11:18:49.434400 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5664 11:18:49.437483 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5665 11:18:49.437568 ==
5666 11:18:49.440748 Dram Type= 6, Freq= 0, CH_1, rank 0
5667 11:18:49.444470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5668 11:18:49.444555 ==
5669 11:18:49.447513 DQS Delay:
5670 11:18:49.447596 DQS0 = 0, DQS1 = 0
5671 11:18:49.450504 DQM Delay:
5672 11:18:49.450586 DQM0 = 95, DQM1 = 89
5673 11:18:49.450652 DQ Delay:
5674 11:18:49.454066 DQ0 =99, DQ1 =91, DQ2 =79, DQ3 =99
5675 11:18:49.457558 DQ4 =95, DQ5 =103, DQ6 =107, DQ7 =91
5676 11:18:49.460839 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5677 11:18:49.463701 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5678 11:18:49.463784
5679 11:18:49.463848
5680 11:18:49.467374 ==
5681 11:18:49.470755 Dram Type= 6, Freq= 0, CH_1, rank 0
5682 11:18:49.474326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5683 11:18:49.474410 ==
5684 11:18:49.474475
5685 11:18:49.474535
5686 11:18:49.477016 TX Vref Scan disable
5687 11:18:49.477099 == TX Byte 0 ==
5688 11:18:49.480823 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5689 11:18:49.487158 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5690 11:18:49.487242 == TX Byte 1 ==
5691 11:18:49.490523 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5692 11:18:49.496788 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5693 11:18:49.496873 ==
5694 11:18:49.500089 Dram Type= 6, Freq= 0, CH_1, rank 0
5695 11:18:49.503506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5696 11:18:49.503590 ==
5697 11:18:49.503656
5698 11:18:49.503715
5699 11:18:49.507217 TX Vref Scan disable
5700 11:18:49.510374 == TX Byte 0 ==
5701 11:18:49.513820 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5702 11:18:49.516701 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5703 11:18:49.520073 == TX Byte 1 ==
5704 11:18:49.523525 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5705 11:18:49.527091 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5706 11:18:49.527176
5707 11:18:49.530287 [DATLAT]
5708 11:18:49.530370 Freq=933, CH1 RK0
5709 11:18:49.530436
5710 11:18:49.533675 DATLAT Default: 0xd
5711 11:18:49.533758 0, 0xFFFF, sum = 0
5712 11:18:49.537099 1, 0xFFFF, sum = 0
5713 11:18:49.537184 2, 0xFFFF, sum = 0
5714 11:18:49.540293 3, 0xFFFF, sum = 0
5715 11:18:49.540381 4, 0xFFFF, sum = 0
5716 11:18:49.543524 5, 0xFFFF, sum = 0
5717 11:18:49.543608 6, 0xFFFF, sum = 0
5718 11:18:49.546510 7, 0xFFFF, sum = 0
5719 11:18:49.546593 8, 0xFFFF, sum = 0
5720 11:18:49.550193 9, 0xFFFF, sum = 0
5721 11:18:49.550280 10, 0x0, sum = 1
5722 11:18:49.553376 11, 0x0, sum = 2
5723 11:18:49.553464 12, 0x0, sum = 3
5724 11:18:49.556560 13, 0x0, sum = 4
5725 11:18:49.556644 best_step = 11
5726 11:18:49.556709
5727 11:18:49.556769 ==
5728 11:18:49.559802 Dram Type= 6, Freq= 0, CH_1, rank 0
5729 11:18:49.566736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5730 11:18:49.566821 ==
5731 11:18:49.566886 RX Vref Scan: 1
5732 11:18:49.566945
5733 11:18:49.569932 RX Vref 0 -> 0, step: 1
5734 11:18:49.570014
5735 11:18:49.573040 RX Delay -61 -> 252, step: 4
5736 11:18:49.573123
5737 11:18:49.576898 Set Vref, RX VrefLevel [Byte0]: 59
5738 11:18:49.580390 [Byte1]: 48
5739 11:18:49.580472
5740 11:18:49.583277 Final RX Vref Byte 0 = 59 to rank0
5741 11:18:49.586388 Final RX Vref Byte 1 = 48 to rank0
5742 11:18:49.589875 Final RX Vref Byte 0 = 59 to rank1
5743 11:18:49.593155 Final RX Vref Byte 1 = 48 to rank1==
5744 11:18:49.596388 Dram Type= 6, Freq= 0, CH_1, rank 0
5745 11:18:49.599809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5746 11:18:49.599893 ==
5747 11:18:49.603024 DQS Delay:
5748 11:18:49.603106 DQS0 = 0, DQS1 = 0
5749 11:18:49.603172 DQM Delay:
5750 11:18:49.606451 DQM0 = 98, DQM1 = 91
5751 11:18:49.606533 DQ Delay:
5752 11:18:49.610095 DQ0 =100, DQ1 =92, DQ2 =88, DQ3 =96
5753 11:18:49.613213 DQ4 =96, DQ5 =108, DQ6 =110, DQ7 =94
5754 11:18:49.616140 DQ8 =82, DQ9 =80, DQ10 =92, DQ11 =84
5755 11:18:49.619627 DQ12 =100, DQ13 =96, DQ14 =100, DQ15 =94
5756 11:18:49.619711
5757 11:18:49.619775
5758 11:18:49.629350 [DQSOSCAuto] RK0, (LSB)MR18= 0x10ec, (MSB)MR19= 0x504, tDQSOscB0 = 428 ps tDQSOscB1 = 416 ps
5759 11:18:49.632741 CH1 RK0: MR19=504, MR18=10EC
5760 11:18:49.636709 CH1_RK0: MR19=0x504, MR18=0x10EC, DQSOSC=416, MR23=63, INC=62, DEC=41
5761 11:18:49.639725
5762 11:18:49.642759 ----->DramcWriteLeveling(PI) begin...
5763 11:18:49.642844 ==
5764 11:18:49.646069 Dram Type= 6, Freq= 0, CH_1, rank 1
5765 11:18:49.649614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5766 11:18:49.649699 ==
5767 11:18:49.652993 Write leveling (Byte 0): 28 => 28
5768 11:18:49.656375 Write leveling (Byte 1): 30 => 30
5769 11:18:49.659776 DramcWriteLeveling(PI) end<-----
5770 11:18:49.659859
5771 11:18:49.659924 ==
5772 11:18:49.662925 Dram Type= 6, Freq= 0, CH_1, rank 1
5773 11:18:49.666000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5774 11:18:49.666084 ==
5775 11:18:49.669295 [Gating] SW mode calibration
5776 11:18:49.675917 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5777 11:18:49.682810 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5778 11:18:49.686257 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5779 11:18:49.689217 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5780 11:18:49.696165 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5781 11:18:49.699484 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5782 11:18:49.702346 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5783 11:18:49.709198 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5784 11:18:49.712598 0 14 24 | B1->B0 | 3333 2e2e | 0 0 | (0 1) (0 0)
5785 11:18:49.716227 0 14 28 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (1 0)
5786 11:18:49.722367 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5787 11:18:49.725502 0 15 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5788 11:18:49.728938 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5789 11:18:49.735726 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5790 11:18:49.738881 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5791 11:18:49.742937 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5792 11:18:49.745813 0 15 24 | B1->B0 | 2626 3b3b | 0 0 | (0 0) (0 0)
5793 11:18:49.752417 0 15 28 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
5794 11:18:49.755802 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5795 11:18:49.758844 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5796 11:18:49.765703 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5797 11:18:49.768814 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5798 11:18:49.772138 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5799 11:18:49.779064 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5800 11:18:49.782076 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5801 11:18:49.785467 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5802 11:18:49.792351 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5803 11:18:49.795745 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5804 11:18:49.798718 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5805 11:18:49.805297 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5806 11:18:49.808949 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5807 11:18:49.812197 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5808 11:18:49.818939 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5809 11:18:49.822081 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5810 11:18:49.825396 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5811 11:18:49.831862 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5812 11:18:49.835483 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5813 11:18:49.838512 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5814 11:18:49.845131 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5815 11:18:49.848617 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5816 11:18:49.852546 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5817 11:18:49.858974 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5818 11:18:49.861699 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5819 11:18:49.865196 Total UI for P1: 0, mck2ui 16
5820 11:18:49.868442 best dqsien dly found for B0: ( 1, 2, 26)
5821 11:18:49.871845 Total UI for P1: 0, mck2ui 16
5822 11:18:49.875082 best dqsien dly found for B1: ( 1, 2, 28)
5823 11:18:49.878393 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5824 11:18:49.881971 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5825 11:18:49.882054
5826 11:18:49.885129 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5827 11:18:49.888650 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5828 11:18:49.892039 [Gating] SW calibration Done
5829 11:18:49.892123 ==
5830 11:18:49.894941 Dram Type= 6, Freq= 0, CH_1, rank 1
5831 11:18:49.898126 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5832 11:18:49.898211 ==
5833 11:18:49.901545 RX Vref Scan: 0
5834 11:18:49.901643
5835 11:18:49.905025 RX Vref 0 -> 0, step: 1
5836 11:18:49.905106
5837 11:18:49.905170 RX Delay -80 -> 252, step: 8
5838 11:18:49.911596 iDelay=200, Bit 0, Center 95 (0 ~ 191) 192
5839 11:18:49.915334 iDelay=200, Bit 1, Center 91 (0 ~ 183) 184
5840 11:18:49.918631 iDelay=200, Bit 2, Center 87 (-8 ~ 183) 192
5841 11:18:49.922094 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5842 11:18:49.925246 iDelay=200, Bit 4, Center 95 (0 ~ 191) 192
5843 11:18:49.928500 iDelay=200, Bit 5, Center 103 (8 ~ 199) 192
5844 11:18:49.935039 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5845 11:18:49.938531 iDelay=200, Bit 7, Center 91 (0 ~ 183) 184
5846 11:18:49.941800 iDelay=200, Bit 8, Center 79 (-16 ~ 175) 192
5847 11:18:49.945046 iDelay=200, Bit 9, Center 79 (-16 ~ 175) 192
5848 11:18:49.948703 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5849 11:18:49.951919 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5850 11:18:49.958873 iDelay=200, Bit 12, Center 99 (8 ~ 191) 184
5851 11:18:49.961606 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5852 11:18:49.964792 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5853 11:18:49.968020 iDelay=200, Bit 15, Center 95 (0 ~ 191) 192
5854 11:18:49.968099 ==
5855 11:18:49.971266 Dram Type= 6, Freq= 0, CH_1, rank 1
5856 11:18:49.974828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5857 11:18:49.978083 ==
5858 11:18:49.978178 DQS Delay:
5859 11:18:49.978271 DQS0 = 0, DQS1 = 0
5860 11:18:49.981472 DQM Delay:
5861 11:18:49.981552 DQM0 = 95, DQM1 = 89
5862 11:18:49.985157 DQ Delay:
5863 11:18:49.985263 DQ0 =95, DQ1 =91, DQ2 =87, DQ3 =95
5864 11:18:49.988018 DQ4 =95, DQ5 =103, DQ6 =103, DQ7 =91
5865 11:18:49.991252 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =83
5866 11:18:49.994744 DQ12 =99, DQ13 =95, DQ14 =95, DQ15 =95
5867 11:18:49.997956
5868 11:18:49.998035
5869 11:18:49.998097 ==
5870 11:18:50.001056 Dram Type= 6, Freq= 0, CH_1, rank 1
5871 11:18:50.004378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5872 11:18:50.004461 ==
5873 11:18:50.004525
5874 11:18:50.004583
5875 11:18:50.007981 TX Vref Scan disable
5876 11:18:50.008063 == TX Byte 0 ==
5877 11:18:50.014977 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5878 11:18:50.017723 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5879 11:18:50.017806 == TX Byte 1 ==
5880 11:18:50.024503 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5881 11:18:50.027790 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5882 11:18:50.027874 ==
5883 11:18:50.031460 Dram Type= 6, Freq= 0, CH_1, rank 1
5884 11:18:50.034674 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5885 11:18:50.034756 ==
5886 11:18:50.034820
5887 11:18:50.034877
5888 11:18:50.037807 TX Vref Scan disable
5889 11:18:50.041285 == TX Byte 0 ==
5890 11:18:50.044632 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5891 11:18:50.047830 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5892 11:18:50.050955 == TX Byte 1 ==
5893 11:18:50.054526 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5894 11:18:50.057713 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5895 11:18:50.057795
5896 11:18:50.061192 [DATLAT]
5897 11:18:50.061273 Freq=933, CH1 RK1
5898 11:18:50.061338
5899 11:18:50.064577 DATLAT Default: 0xb
5900 11:18:50.064658 0, 0xFFFF, sum = 0
5901 11:18:50.068028 1, 0xFFFF, sum = 0
5902 11:18:50.068110 2, 0xFFFF, sum = 0
5903 11:18:50.071008 3, 0xFFFF, sum = 0
5904 11:18:50.071091 4, 0xFFFF, sum = 0
5905 11:18:50.074569 5, 0xFFFF, sum = 0
5906 11:18:50.074652 6, 0xFFFF, sum = 0
5907 11:18:50.077463 7, 0xFFFF, sum = 0
5908 11:18:50.077546 8, 0xFFFF, sum = 0
5909 11:18:50.080925 9, 0xFFFF, sum = 0
5910 11:18:50.081010 10, 0x0, sum = 1
5911 11:18:50.084103 11, 0x0, sum = 2
5912 11:18:50.084186 12, 0x0, sum = 3
5913 11:18:50.087450 13, 0x0, sum = 4
5914 11:18:50.087534 best_step = 11
5915 11:18:50.087598
5916 11:18:50.087657 ==
5917 11:18:50.090732 Dram Type= 6, Freq= 0, CH_1, rank 1
5918 11:18:50.097376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5919 11:18:50.097463 ==
5920 11:18:50.097527 RX Vref Scan: 0
5921 11:18:50.097587
5922 11:18:50.101387 RX Vref 0 -> 0, step: 1
5923 11:18:50.101470
5924 11:18:50.104227 RX Delay -61 -> 252, step: 4
5925 11:18:50.107465 iDelay=195, Bit 0, Center 98 (7 ~ 190) 184
5926 11:18:50.111021 iDelay=195, Bit 1, Center 90 (-1 ~ 182) 184
5927 11:18:50.117816 iDelay=195, Bit 2, Center 86 (-5 ~ 178) 184
5928 11:18:50.120872 iDelay=195, Bit 3, Center 94 (3 ~ 186) 184
5929 11:18:50.124352 iDelay=195, Bit 4, Center 98 (7 ~ 190) 184
5930 11:18:50.127542 iDelay=195, Bit 5, Center 106 (19 ~ 194) 176
5931 11:18:50.130950 iDelay=195, Bit 6, Center 106 (19 ~ 194) 176
5932 11:18:50.134144 iDelay=195, Bit 7, Center 92 (3 ~ 182) 180
5933 11:18:50.137479 iDelay=195, Bit 8, Center 80 (-9 ~ 170) 180
5934 11:18:50.144051 iDelay=195, Bit 9, Center 80 (-9 ~ 170) 180
5935 11:18:50.147459 iDelay=195, Bit 10, Center 90 (-1 ~ 182) 184
5936 11:18:50.150705 iDelay=195, Bit 11, Center 84 (-5 ~ 174) 180
5937 11:18:50.154484 iDelay=195, Bit 12, Center 96 (7 ~ 186) 180
5938 11:18:50.157401 iDelay=195, Bit 13, Center 98 (7 ~ 190) 184
5939 11:18:50.164075 iDelay=195, Bit 14, Center 104 (19 ~ 190) 172
5940 11:18:50.167958 iDelay=195, Bit 15, Center 98 (7 ~ 190) 184
5941 11:18:50.168047 ==
5942 11:18:50.170597 Dram Type= 6, Freq= 0, CH_1, rank 1
5943 11:18:50.174234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5944 11:18:50.174319 ==
5945 11:18:50.177042 DQS Delay:
5946 11:18:50.177124 DQS0 = 0, DQS1 = 0
5947 11:18:50.177188 DQM Delay:
5948 11:18:50.180414 DQM0 = 96, DQM1 = 91
5949 11:18:50.180496 DQ Delay:
5950 11:18:50.184258 DQ0 =98, DQ1 =90, DQ2 =86, DQ3 =94
5951 11:18:50.187316 DQ4 =98, DQ5 =106, DQ6 =106, DQ7 =92
5952 11:18:50.191013 DQ8 =80, DQ9 =80, DQ10 =90, DQ11 =84
5953 11:18:50.193962 DQ12 =96, DQ13 =98, DQ14 =104, DQ15 =98
5954 11:18:50.194046
5955 11:18:50.194110
5956 11:18:50.203684 [DQSOSCAuto] RK1, (LSB)MR18= 0xb14, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 418 ps
5957 11:18:50.203781 CH1 RK1: MR19=505, MR18=B14
5958 11:18:50.210552 CH1_RK1: MR19=0x505, MR18=0xB14, DQSOSC=415, MR23=63, INC=62, DEC=41
5959 11:18:50.213533 [RxdqsGatingPostProcess] freq 933
5960 11:18:50.220316 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5961 11:18:50.223580 best DQS0 dly(2T, 0.5T) = (0, 10)
5962 11:18:50.227324 best DQS1 dly(2T, 0.5T) = (0, 10)
5963 11:18:50.230460 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5964 11:18:50.233804 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5965 11:18:50.237277 best DQS0 dly(2T, 0.5T) = (0, 10)
5966 11:18:50.237363 best DQS1 dly(2T, 0.5T) = (0, 10)
5967 11:18:50.240519 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5968 11:18:50.243736 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5969 11:18:50.247326 Pre-setting of DQS Precalculation
5970 11:18:50.254087 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5971 11:18:50.260208 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5972 11:18:50.266733 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5973 11:18:50.266836
5974 11:18:50.266903
5975 11:18:50.270069 [Calibration Summary] 1866 Mbps
5976 11:18:50.273332 CH 0, Rank 0
5977 11:18:50.273426 SW Impedance : PASS
5978 11:18:50.277266 DUTY Scan : NO K
5979 11:18:50.277357 ZQ Calibration : PASS
5980 11:18:50.280537 Jitter Meter : NO K
5981 11:18:50.283568 CBT Training : PASS
5982 11:18:50.283657 Write leveling : PASS
5983 11:18:50.287097 RX DQS gating : PASS
5984 11:18:50.290063 RX DQ/DQS(RDDQC) : PASS
5985 11:18:50.290151 TX DQ/DQS : PASS
5986 11:18:50.293507 RX DATLAT : PASS
5987 11:18:50.296627 RX DQ/DQS(Engine): PASS
5988 11:18:50.296714 TX OE : NO K
5989 11:18:50.299915 All Pass.
5990 11:18:50.300001
5991 11:18:50.300065 CH 0, Rank 1
5992 11:18:50.303554 SW Impedance : PASS
5993 11:18:50.303640 DUTY Scan : NO K
5994 11:18:50.306732 ZQ Calibration : PASS
5995 11:18:50.309971 Jitter Meter : NO K
5996 11:18:50.310055 CBT Training : PASS
5997 11:18:50.313350 Write leveling : PASS
5998 11:18:50.316792 RX DQS gating : PASS
5999 11:18:50.316877 RX DQ/DQS(RDDQC) : PASS
6000 11:18:50.319763 TX DQ/DQS : PASS
6001 11:18:50.319847 RX DATLAT : PASS
6002 11:18:50.323527 RX DQ/DQS(Engine): PASS
6003 11:18:50.326551 TX OE : NO K
6004 11:18:50.326643 All Pass.
6005 11:18:50.326708
6006 11:18:50.326767 CH 1, Rank 0
6007 11:18:50.330590 SW Impedance : PASS
6008 11:18:50.333153 DUTY Scan : NO K
6009 11:18:50.333237 ZQ Calibration : PASS
6010 11:18:50.336649 Jitter Meter : NO K
6011 11:18:50.339835 CBT Training : PASS
6012 11:18:50.339921 Write leveling : PASS
6013 11:18:50.343346 RX DQS gating : PASS
6014 11:18:50.346646 RX DQ/DQS(RDDQC) : PASS
6015 11:18:50.346728 TX DQ/DQS : PASS
6016 11:18:50.349729 RX DATLAT : PASS
6017 11:18:50.353257 RX DQ/DQS(Engine): PASS
6018 11:18:50.353340 TX OE : NO K
6019 11:18:50.356719 All Pass.
6020 11:18:50.356804
6021 11:18:50.356868 CH 1, Rank 1
6022 11:18:50.359790 SW Impedance : PASS
6023 11:18:50.359872 DUTY Scan : NO K
6024 11:18:50.363189 ZQ Calibration : PASS
6025 11:18:50.366069 Jitter Meter : NO K
6026 11:18:50.366154 CBT Training : PASS
6027 11:18:50.369650 Write leveling : PASS
6028 11:18:50.372974 RX DQS gating : PASS
6029 11:18:50.373057 RX DQ/DQS(RDDQC) : PASS
6030 11:18:50.376180 TX DQ/DQS : PASS
6031 11:18:50.379549 RX DATLAT : PASS
6032 11:18:50.379631 RX DQ/DQS(Engine): PASS
6033 11:18:50.383317 TX OE : NO K
6034 11:18:50.383439 All Pass.
6035 11:18:50.383503
6036 11:18:50.386060 DramC Write-DBI off
6037 11:18:50.389416 PER_BANK_REFRESH: Hybrid Mode
6038 11:18:50.389498 TX_TRACKING: ON
6039 11:18:50.399376 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6040 11:18:50.403243 [FAST_K] Save calibration result to emmc
6041 11:18:50.406074 dramc_set_vcore_voltage set vcore to 650000
6042 11:18:50.409265 Read voltage for 400, 6
6043 11:18:50.409348 Vio18 = 0
6044 11:18:50.409412 Vcore = 650000
6045 11:18:50.412990 Vdram = 0
6046 11:18:50.413075 Vddq = 0
6047 11:18:50.413139 Vmddr = 0
6048 11:18:50.419278 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6049 11:18:50.422531 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6050 11:18:50.426151 MEM_TYPE=3, freq_sel=20
6051 11:18:50.429184 sv_algorithm_assistance_LP4_800
6052 11:18:50.432368 ============ PULL DRAM RESETB DOWN ============
6053 11:18:50.435978 ========== PULL DRAM RESETB DOWN end =========
6054 11:18:50.442971 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6055 11:18:50.446044 ===================================
6056 11:18:50.446130 LPDDR4 DRAM CONFIGURATION
6057 11:18:50.449399 ===================================
6058 11:18:50.452698 EX_ROW_EN[0] = 0x0
6059 11:18:50.455956 EX_ROW_EN[1] = 0x0
6060 11:18:50.456042 LP4Y_EN = 0x0
6061 11:18:50.459281 WORK_FSP = 0x0
6062 11:18:50.459375 WL = 0x2
6063 11:18:50.462431 RL = 0x2
6064 11:18:50.462513 BL = 0x2
6065 11:18:50.466084 RPST = 0x0
6066 11:18:50.466167 RD_PRE = 0x0
6067 11:18:50.469610 WR_PRE = 0x1
6068 11:18:50.469692 WR_PST = 0x0
6069 11:18:50.472627 DBI_WR = 0x0
6070 11:18:50.472710 DBI_RD = 0x0
6071 11:18:50.475827 OTF = 0x1
6072 11:18:50.478860 ===================================
6073 11:18:50.482312 ===================================
6074 11:18:50.482394 ANA top config
6075 11:18:50.485724 ===================================
6076 11:18:50.489499 DLL_ASYNC_EN = 0
6077 11:18:50.492553 ALL_SLAVE_EN = 1
6078 11:18:50.492637 NEW_RANK_MODE = 1
6079 11:18:50.495978 DLL_IDLE_MODE = 1
6080 11:18:50.498833 LP45_APHY_COMB_EN = 1
6081 11:18:50.502151 TX_ODT_DIS = 1
6082 11:18:50.505729 NEW_8X_MODE = 1
6083 11:18:50.508638 ===================================
6084 11:18:50.512073 ===================================
6085 11:18:50.512157 data_rate = 800
6086 11:18:50.515605 CKR = 1
6087 11:18:50.519058 DQ_P2S_RATIO = 4
6088 11:18:50.522553 ===================================
6089 11:18:50.525524 CA_P2S_RATIO = 4
6090 11:18:50.528907 DQ_CA_OPEN = 0
6091 11:18:50.532059 DQ_SEMI_OPEN = 1
6092 11:18:50.532146 CA_SEMI_OPEN = 1
6093 11:18:50.535292 CA_FULL_RATE = 0
6094 11:18:50.539233 DQ_CKDIV4_EN = 0
6095 11:18:50.542228 CA_CKDIV4_EN = 1
6096 11:18:50.545470 CA_PREDIV_EN = 0
6097 11:18:50.548414 PH8_DLY = 0
6098 11:18:50.548496 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6099 11:18:50.551745 DQ_AAMCK_DIV = 0
6100 11:18:50.555305 CA_AAMCK_DIV = 0
6101 11:18:50.558995 CA_ADMCK_DIV = 4
6102 11:18:50.562166 DQ_TRACK_CA_EN = 0
6103 11:18:50.565144 CA_PICK = 800
6104 11:18:50.568279 CA_MCKIO = 400
6105 11:18:50.568362 MCKIO_SEMI = 400
6106 11:18:50.571732 PLL_FREQ = 3016
6107 11:18:50.574843 DQ_UI_PI_RATIO = 32
6108 11:18:50.578544 CA_UI_PI_RATIO = 32
6109 11:18:50.582213 ===================================
6110 11:18:50.585198 ===================================
6111 11:18:50.588401 memory_type:LPDDR4
6112 11:18:50.588484 GP_NUM : 10
6113 11:18:50.591742 SRAM_EN : 1
6114 11:18:50.595135 MD32_EN : 0
6115 11:18:50.598077 ===================================
6116 11:18:50.598161 [ANA_INIT] >>>>>>>>>>>>>>
6117 11:18:50.602284 <<<<<< [CONFIGURE PHASE]: ANA_TX
6118 11:18:50.605489 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6119 11:18:50.608243 ===================================
6120 11:18:50.611647 data_rate = 800,PCW = 0X7400
6121 11:18:50.614604 ===================================
6122 11:18:50.618244 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6123 11:18:50.624973 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6124 11:18:50.634956 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6125 11:18:50.641573 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6126 11:18:50.644736 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6127 11:18:50.649060 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6128 11:18:50.649144 [ANA_INIT] flow start
6129 11:18:50.651628 [ANA_INIT] PLL >>>>>>>>
6130 11:18:50.655148 [ANA_INIT] PLL <<<<<<<<
6131 11:18:50.655246 [ANA_INIT] MIDPI >>>>>>>>
6132 11:18:50.658472 [ANA_INIT] MIDPI <<<<<<<<
6133 11:18:50.661399 [ANA_INIT] DLL >>>>>>>>
6134 11:18:50.661481 [ANA_INIT] flow end
6135 11:18:50.667907 ============ LP4 DIFF to SE enter ============
6136 11:18:50.671241 ============ LP4 DIFF to SE exit ============
6137 11:18:50.671329 [ANA_INIT] <<<<<<<<<<<<<
6138 11:18:50.674360 [Flow] Enable top DCM control >>>>>
6139 11:18:50.678267 [Flow] Enable top DCM control <<<<<
6140 11:18:50.681415 Enable DLL master slave shuffle
6141 11:18:50.688254 ==============================================================
6142 11:18:50.691110 Gating Mode config
6143 11:18:50.694555 ==============================================================
6144 11:18:50.697794 Config description:
6145 11:18:50.708151 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6146 11:18:50.714522 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6147 11:18:50.718022 SELPH_MODE 0: By rank 1: By Phase
6148 11:18:50.724772 ==============================================================
6149 11:18:50.727815 GAT_TRACK_EN = 0
6150 11:18:50.731263 RX_GATING_MODE = 2
6151 11:18:50.734518 RX_GATING_TRACK_MODE = 2
6152 11:18:50.734599 SELPH_MODE = 1
6153 11:18:50.737816 PICG_EARLY_EN = 1
6154 11:18:50.741237 VALID_LAT_VALUE = 1
6155 11:18:50.748180 ==============================================================
6156 11:18:50.750890 Enter into Gating configuration >>>>
6157 11:18:50.754389 Exit from Gating configuration <<<<
6158 11:18:50.757763 Enter into DVFS_PRE_config >>>>>
6159 11:18:50.767663 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6160 11:18:50.771066 Exit from DVFS_PRE_config <<<<<
6161 11:18:50.774430 Enter into PICG configuration >>>>
6162 11:18:50.777547 Exit from PICG configuration <<<<
6163 11:18:50.780777 [RX_INPUT] configuration >>>>>
6164 11:18:50.784295 [RX_INPUT] configuration <<<<<
6165 11:18:50.787366 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6166 11:18:50.794023 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6167 11:18:50.800588 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6168 11:18:50.807331 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6169 11:18:50.810981 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6170 11:18:50.817409 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6171 11:18:50.820881 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6172 11:18:50.827236 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6173 11:18:50.830550 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6174 11:18:50.834053 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6175 11:18:50.837662 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6176 11:18:50.843700 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6177 11:18:50.847239 ===================================
6178 11:18:50.850497 LPDDR4 DRAM CONFIGURATION
6179 11:18:50.854076 ===================================
6180 11:18:50.854159 EX_ROW_EN[0] = 0x0
6181 11:18:50.857312 EX_ROW_EN[1] = 0x0
6182 11:18:50.857394 LP4Y_EN = 0x0
6183 11:18:50.860427 WORK_FSP = 0x0
6184 11:18:50.860508 WL = 0x2
6185 11:18:50.863929 RL = 0x2
6186 11:18:50.864011 BL = 0x2
6187 11:18:50.867158 RPST = 0x0
6188 11:18:50.867240 RD_PRE = 0x0
6189 11:18:50.870481 WR_PRE = 0x1
6190 11:18:50.870563 WR_PST = 0x0
6191 11:18:50.873667 DBI_WR = 0x0
6192 11:18:50.873749 DBI_RD = 0x0
6193 11:18:50.877076 OTF = 0x1
6194 11:18:50.880234 ===================================
6195 11:18:50.883801 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6196 11:18:50.887218 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6197 11:18:50.893461 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6198 11:18:50.896775 ===================================
6199 11:18:50.896857 LPDDR4 DRAM CONFIGURATION
6200 11:18:50.900171 ===================================
6201 11:18:50.903640 EX_ROW_EN[0] = 0x10
6202 11:18:50.906993 EX_ROW_EN[1] = 0x0
6203 11:18:50.907075 LP4Y_EN = 0x0
6204 11:18:50.910012 WORK_FSP = 0x0
6205 11:18:50.910105 WL = 0x2
6206 11:18:50.913127 RL = 0x2
6207 11:18:50.913210 BL = 0x2
6208 11:18:50.916586 RPST = 0x0
6209 11:18:50.916668 RD_PRE = 0x0
6210 11:18:50.920099 WR_PRE = 0x1
6211 11:18:50.920181 WR_PST = 0x0
6212 11:18:50.923223 DBI_WR = 0x0
6213 11:18:50.923306 DBI_RD = 0x0
6214 11:18:50.926604 OTF = 0x1
6215 11:18:50.929557 ===================================
6216 11:18:50.936410 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6217 11:18:50.939813 nWR fixed to 30
6218 11:18:50.942871 [ModeRegInit_LP4] CH0 RK0
6219 11:18:50.942962 [ModeRegInit_LP4] CH0 RK1
6220 11:18:50.946282 [ModeRegInit_LP4] CH1 RK0
6221 11:18:50.949688 [ModeRegInit_LP4] CH1 RK1
6222 11:18:50.949769 match AC timing 19
6223 11:18:50.956245 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6224 11:18:50.959777 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6225 11:18:50.963133 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6226 11:18:50.969930 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6227 11:18:50.972994 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6228 11:18:50.973075 ==
6229 11:18:50.976681 Dram Type= 6, Freq= 0, CH_0, rank 0
6230 11:18:50.980077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6231 11:18:50.980159 ==
6232 11:18:50.986329 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6233 11:18:50.992748 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6234 11:18:50.996069 [CA 0] Center 36 (8~64) winsize 57
6235 11:18:50.999448 [CA 1] Center 36 (8~64) winsize 57
6236 11:18:51.002826 [CA 2] Center 36 (8~64) winsize 57
6237 11:18:51.006659 [CA 3] Center 36 (8~64) winsize 57
6238 11:18:51.006740 [CA 4] Center 36 (8~64) winsize 57
6239 11:18:51.009584 [CA 5] Center 36 (8~64) winsize 57
6240 11:18:51.009665
6241 11:18:51.016025 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6242 11:18:51.016106
6243 11:18:51.019327 [CATrainingPosCal] consider 1 rank data
6244 11:18:51.022488 u2DelayCellTimex100 = 270/100 ps
6245 11:18:51.026154 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 11:18:51.029053 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 11:18:51.032743 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 11:18:51.036233 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 11:18:51.039994 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 11:18:51.042583 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 11:18:51.042664
6252 11:18:51.045903 CA PerBit enable=1, Macro0, CA PI delay=36
6253 11:18:51.045985
6254 11:18:51.048895 [CBTSetCACLKResult] CA Dly = 36
6255 11:18:51.052115 CS Dly: 1 (0~32)
6256 11:18:51.052196 ==
6257 11:18:51.056001 Dram Type= 6, Freq= 0, CH_0, rank 1
6258 11:18:51.059020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6259 11:18:51.059102 ==
6260 11:18:51.065533 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6261 11:18:51.072574 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6262 11:18:51.075990 [CA 0] Center 36 (8~64) winsize 57
6263 11:18:51.076071 [CA 1] Center 36 (8~64) winsize 57
6264 11:18:51.079063 [CA 2] Center 36 (8~64) winsize 57
6265 11:18:51.082291 [CA 3] Center 36 (8~64) winsize 57
6266 11:18:51.086270 [CA 4] Center 36 (8~64) winsize 57
6267 11:18:51.088867 [CA 5] Center 36 (8~64) winsize 57
6268 11:18:51.088948
6269 11:18:51.092021 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6270 11:18:51.092101
6271 11:18:51.095617 [CATrainingPosCal] consider 2 rank data
6272 11:18:51.099017 u2DelayCellTimex100 = 270/100 ps
6273 11:18:51.102272 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6274 11:18:51.108497 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6275 11:18:51.112172 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6276 11:18:51.115770 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6277 11:18:51.118953 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6278 11:18:51.121866 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6279 11:18:51.121966
6280 11:18:51.125199 CA PerBit enable=1, Macro0, CA PI delay=36
6281 11:18:51.125284
6282 11:18:51.128393 [CBTSetCACLKResult] CA Dly = 36
6283 11:18:51.128474 CS Dly: 1 (0~32)
6284 11:18:51.131662
6285 11:18:51.135130 ----->DramcWriteLeveling(PI) begin...
6286 11:18:51.135212 ==
6287 11:18:51.139041 Dram Type= 6, Freq= 0, CH_0, rank 0
6288 11:18:51.142317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6289 11:18:51.142399 ==
6290 11:18:51.145652 Write leveling (Byte 0): 40 => 8
6291 11:18:51.148546 Write leveling (Byte 1): 32 => 0
6292 11:18:51.151930 DramcWriteLeveling(PI) end<-----
6293 11:18:51.152010
6294 11:18:51.152071 ==
6295 11:18:51.155202 Dram Type= 6, Freq= 0, CH_0, rank 0
6296 11:18:51.158473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6297 11:18:51.158553 ==
6298 11:18:51.161708 [Gating] SW mode calibration
6299 11:18:51.168740 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6300 11:18:51.174990 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6301 11:18:51.178431 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6302 11:18:51.181816 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6303 11:18:51.188113 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6304 11:18:51.192050 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6305 11:18:51.194789 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6306 11:18:51.201434 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6307 11:18:51.205003 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6308 11:18:51.208400 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6309 11:18:51.214600 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6310 11:18:51.214680 Total UI for P1: 0, mck2ui 16
6311 11:18:51.218271 best dqsien dly found for B0: ( 0, 14, 24)
6312 11:18:51.221279 Total UI for P1: 0, mck2ui 16
6313 11:18:51.224673 best dqsien dly found for B1: ( 0, 14, 24)
6314 11:18:51.231657 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6315 11:18:51.234847 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6316 11:18:51.234927
6317 11:18:51.238019 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6318 11:18:51.241056 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6319 11:18:51.244465 [Gating] SW calibration Done
6320 11:18:51.244575 ==
6321 11:18:51.248084 Dram Type= 6, Freq= 0, CH_0, rank 0
6322 11:18:51.251165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6323 11:18:51.251270 ==
6324 11:18:51.254664 RX Vref Scan: 0
6325 11:18:51.254742
6326 11:18:51.254803 RX Vref 0 -> 0, step: 1
6327 11:18:51.254861
6328 11:18:51.257740 RX Delay -410 -> 252, step: 16
6329 11:18:51.264429 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6330 11:18:51.267989 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6331 11:18:51.271338 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6332 11:18:51.274232 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6333 11:18:51.280805 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6334 11:18:51.284228 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6335 11:18:51.287332 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6336 11:18:51.290978 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6337 11:18:51.297613 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6338 11:18:51.300900 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6339 11:18:51.304481 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6340 11:18:51.307839 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6341 11:18:51.313909 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6342 11:18:51.317288 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6343 11:18:51.320622 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6344 11:18:51.324293 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6345 11:18:51.327207 ==
6346 11:18:51.327286 Dram Type= 6, Freq= 0, CH_0, rank 0
6347 11:18:51.333770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6348 11:18:51.333862 ==
6349 11:18:51.333923 DQS Delay:
6350 11:18:51.337575 DQS0 = 35, DQS1 = 51
6351 11:18:51.337652 DQM Delay:
6352 11:18:51.340697 DQM0 = 6, DQM1 = 10
6353 11:18:51.340774 DQ Delay:
6354 11:18:51.343797 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =0
6355 11:18:51.347065 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6356 11:18:51.347143 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6357 11:18:51.353586 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6358 11:18:51.353663
6359 11:18:51.353758
6360 11:18:51.353815 ==
6361 11:18:51.357059 Dram Type= 6, Freq= 0, CH_0, rank 0
6362 11:18:51.360098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6363 11:18:51.360177 ==
6364 11:18:51.360236
6365 11:18:51.360291
6366 11:18:51.363717 TX Vref Scan disable
6367 11:18:51.363807 == TX Byte 0 ==
6368 11:18:51.370234 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6369 11:18:51.373656 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6370 11:18:51.373734 == TX Byte 1 ==
6371 11:18:51.380325 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6372 11:18:51.383754 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6373 11:18:51.383832 ==
6374 11:18:51.387048 Dram Type= 6, Freq= 0, CH_0, rank 0
6375 11:18:51.390414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6376 11:18:51.390493 ==
6377 11:18:51.390554
6378 11:18:51.390609
6379 11:18:51.393641 TX Vref Scan disable
6380 11:18:51.393718 == TX Byte 0 ==
6381 11:18:51.400373 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6382 11:18:51.403250 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6383 11:18:51.403329 == TX Byte 1 ==
6384 11:18:51.410012 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6385 11:18:51.413544 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6386 11:18:51.413622
6387 11:18:51.413681 [DATLAT]
6388 11:18:51.416617 Freq=400, CH0 RK0
6389 11:18:51.416695
6390 11:18:51.416755 DATLAT Default: 0xf
6391 11:18:51.419752 0, 0xFFFF, sum = 0
6392 11:18:51.419831 1, 0xFFFF, sum = 0
6393 11:18:51.423443 2, 0xFFFF, sum = 0
6394 11:18:51.423524 3, 0xFFFF, sum = 0
6395 11:18:51.426653 4, 0xFFFF, sum = 0
6396 11:18:51.426732 5, 0xFFFF, sum = 0
6397 11:18:51.429808 6, 0xFFFF, sum = 0
6398 11:18:51.432934 7, 0xFFFF, sum = 0
6399 11:18:51.433012 8, 0xFFFF, sum = 0
6400 11:18:51.436634 9, 0xFFFF, sum = 0
6401 11:18:51.436713 10, 0xFFFF, sum = 0
6402 11:18:51.439853 11, 0xFFFF, sum = 0
6403 11:18:51.440036 12, 0xFFFF, sum = 0
6404 11:18:51.443352 13, 0x0, sum = 1
6405 11:18:51.443482 14, 0x0, sum = 2
6406 11:18:51.446458 15, 0x0, sum = 3
6407 11:18:51.446536 16, 0x0, sum = 4
6408 11:18:51.446597 best_step = 14
6409 11:18:51.449725
6410 11:18:51.449835 ==
6411 11:18:51.453183 Dram Type= 6, Freq= 0, CH_0, rank 0
6412 11:18:51.456508 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6413 11:18:51.456586 ==
6414 11:18:51.456646 RX Vref Scan: 1
6415 11:18:51.456704
6416 11:18:51.459601 RX Vref 0 -> 0, step: 1
6417 11:18:51.459678
6418 11:18:51.462906 RX Delay -343 -> 252, step: 8
6419 11:18:51.462983
6420 11:18:51.466437 Set Vref, RX VrefLevel [Byte0]: 52
6421 11:18:51.469329 [Byte1]: 51
6422 11:18:51.473750
6423 11:18:51.473827 Final RX Vref Byte 0 = 52 to rank0
6424 11:18:51.476547 Final RX Vref Byte 1 = 51 to rank0
6425 11:18:51.480247 Final RX Vref Byte 0 = 52 to rank1
6426 11:18:51.483730 Final RX Vref Byte 1 = 51 to rank1==
6427 11:18:51.486769 Dram Type= 6, Freq= 0, CH_0, rank 0
6428 11:18:51.493333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6429 11:18:51.493412 ==
6430 11:18:51.493473 DQS Delay:
6431 11:18:51.496600 DQS0 = 40, DQS1 = 60
6432 11:18:51.496677 DQM Delay:
6433 11:18:51.496737 DQM0 = 7, DQM1 = 14
6434 11:18:51.500059 DQ Delay:
6435 11:18:51.503514 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =4
6436 11:18:51.503593 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =12
6437 11:18:51.506580 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6438 11:18:51.509419 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6439 11:18:51.509497
6440 11:18:51.513253
6441 11:18:51.519805 [DQSOSCAuto] RK0, (LSB)MR18= 0x824f, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 393 ps
6442 11:18:51.523311 CH0 RK0: MR19=C0C, MR18=824F
6443 11:18:51.530022 CH0_RK0: MR19=0xC0C, MR18=0x824F, DQSOSC=393, MR23=63, INC=382, DEC=254
6444 11:18:51.530108 ==
6445 11:18:51.532769 Dram Type= 6, Freq= 0, CH_0, rank 1
6446 11:18:51.536290 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6447 11:18:51.536371 ==
6448 11:18:51.539761 [Gating] SW mode calibration
6449 11:18:51.546399 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6450 11:18:51.552959 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6451 11:18:51.556419 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6452 11:18:51.559496 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6453 11:18:51.566131 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6454 11:18:51.569507 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6455 11:18:51.572468 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6456 11:18:51.579944 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6457 11:18:51.582763 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6458 11:18:51.586155 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6459 11:18:51.589365 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6460 11:18:51.592723 Total UI for P1: 0, mck2ui 16
6461 11:18:51.596033 best dqsien dly found for B0: ( 0, 14, 24)
6462 11:18:51.599718 Total UI for P1: 0, mck2ui 16
6463 11:18:51.603045 best dqsien dly found for B1: ( 0, 14, 24)
6464 11:18:51.606291 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6465 11:18:51.612766 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6466 11:18:51.612847
6467 11:18:51.615912 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6468 11:18:51.619270 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6469 11:18:51.622305 [Gating] SW calibration Done
6470 11:18:51.622387 ==
6471 11:18:51.625789 Dram Type= 6, Freq= 0, CH_0, rank 1
6472 11:18:51.629142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6473 11:18:51.629225 ==
6474 11:18:51.632135 RX Vref Scan: 0
6475 11:18:51.632214
6476 11:18:51.632275 RX Vref 0 -> 0, step: 1
6477 11:18:51.632333
6478 11:18:51.635623 RX Delay -410 -> 252, step: 16
6479 11:18:51.638923 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6480 11:18:51.645409 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6481 11:18:51.648768 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6482 11:18:51.652124 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6483 11:18:51.655793 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6484 11:18:51.662652 iDelay=230, Bit 5, Center -43 (-282 ~ 197) 480
6485 11:18:51.665586 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6486 11:18:51.669101 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6487 11:18:51.671959 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6488 11:18:51.679055 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6489 11:18:51.682148 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6490 11:18:51.685736 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6491 11:18:51.692163 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6492 11:18:51.695169 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6493 11:18:51.698803 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6494 11:18:51.701705 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6495 11:18:51.701783 ==
6496 11:18:51.705443 Dram Type= 6, Freq= 0, CH_0, rank 1
6497 11:18:51.711920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6498 11:18:51.712000 ==
6499 11:18:51.712063 DQS Delay:
6500 11:18:51.715205 DQS0 = 43, DQS1 = 51
6501 11:18:51.715309 DQM Delay:
6502 11:18:51.718990 DQM0 = 11, DQM1 = 10
6503 11:18:51.719069 DQ Delay:
6504 11:18:51.722093 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6505 11:18:51.725230 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6506 11:18:51.725312 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6507 11:18:51.728239 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6508 11:18:51.731642
6509 11:18:51.731721
6510 11:18:51.731782 ==
6511 11:18:51.735504 Dram Type= 6, Freq= 0, CH_0, rank 1
6512 11:18:51.738319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6513 11:18:51.738399 ==
6514 11:18:51.738460
6515 11:18:51.738517
6516 11:18:51.741806 TX Vref Scan disable
6517 11:18:51.741889 == TX Byte 0 ==
6518 11:18:51.744726 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6519 11:18:51.751311 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6520 11:18:51.751430 == TX Byte 1 ==
6521 11:18:51.754785 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6522 11:18:51.761323 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6523 11:18:51.761403 ==
6524 11:18:51.764867 Dram Type= 6, Freq= 0, CH_0, rank 1
6525 11:18:51.767753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6526 11:18:51.767833 ==
6527 11:18:51.767895
6528 11:18:51.767953
6529 11:18:51.771763 TX Vref Scan disable
6530 11:18:51.771841 == TX Byte 0 ==
6531 11:18:51.778530 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6532 11:18:51.781331 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6533 11:18:51.781410 == TX Byte 1 ==
6534 11:18:51.788280 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6535 11:18:51.791035 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6536 11:18:51.791126
6537 11:18:51.791187 [DATLAT]
6538 11:18:51.794443 Freq=400, CH0 RK1
6539 11:18:51.794524
6540 11:18:51.794585 DATLAT Default: 0xe
6541 11:18:51.797670 0, 0xFFFF, sum = 0
6542 11:18:51.797750 1, 0xFFFF, sum = 0
6543 11:18:51.801216 2, 0xFFFF, sum = 0
6544 11:18:51.801296 3, 0xFFFF, sum = 0
6545 11:18:51.804470 4, 0xFFFF, sum = 0
6546 11:18:51.804550 5, 0xFFFF, sum = 0
6547 11:18:51.807707 6, 0xFFFF, sum = 0
6548 11:18:51.807787 7, 0xFFFF, sum = 0
6549 11:18:51.811050 8, 0xFFFF, sum = 0
6550 11:18:51.811129 9, 0xFFFF, sum = 0
6551 11:18:51.814236 10, 0xFFFF, sum = 0
6552 11:18:51.814315 11, 0xFFFF, sum = 0
6553 11:18:51.817925 12, 0xFFFF, sum = 0
6554 11:18:51.818004 13, 0x0, sum = 1
6555 11:18:51.821151 14, 0x0, sum = 2
6556 11:18:51.821232 15, 0x0, sum = 3
6557 11:18:51.824384 16, 0x0, sum = 4
6558 11:18:51.824464 best_step = 14
6559 11:18:51.824526
6560 11:18:51.824583 ==
6561 11:18:51.828234 Dram Type= 6, Freq= 0, CH_0, rank 1
6562 11:18:51.834281 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6563 11:18:51.834362 ==
6564 11:18:51.834422 RX Vref Scan: 0
6565 11:18:51.834480
6566 11:18:51.837735 RX Vref 0 -> 0, step: 1
6567 11:18:51.837814
6568 11:18:51.840813 RX Delay -343 -> 252, step: 8
6569 11:18:51.847542 iDelay=217, Bit 0, Center -32 (-271 ~ 208) 480
6570 11:18:51.850837 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6571 11:18:51.853851 iDelay=217, Bit 2, Center -36 (-271 ~ 200) 472
6572 11:18:51.860610 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6573 11:18:51.863714 iDelay=217, Bit 4, Center -36 (-271 ~ 200) 472
6574 11:18:51.867522 iDelay=217, Bit 5, Center -48 (-287 ~ 192) 480
6575 11:18:51.871022 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6576 11:18:51.874076 iDelay=217, Bit 7, Center -28 (-263 ~ 208) 472
6577 11:18:51.880477 iDelay=217, Bit 8, Center -56 (-295 ~ 184) 480
6578 11:18:51.883879 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6579 11:18:51.886978 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6580 11:18:51.894072 iDelay=217, Bit 11, Center -56 (-295 ~ 184) 480
6581 11:18:51.897228 iDelay=217, Bit 12, Center -44 (-287 ~ 200) 488
6582 11:18:51.900209 iDelay=217, Bit 13, Center -40 (-279 ~ 200) 480
6583 11:18:51.903684 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6584 11:18:51.910535 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6585 11:18:51.910651 ==
6586 11:18:51.913324 Dram Type= 6, Freq= 0, CH_0, rank 1
6587 11:18:51.917122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6588 11:18:51.917202 ==
6589 11:18:51.917263 DQS Delay:
6590 11:18:51.920061 DQS0 = 48, DQS1 = 56
6591 11:18:51.920139 DQM Delay:
6592 11:18:51.923669 DQM0 = 13, DQM1 = 10
6593 11:18:51.923760 DQ Delay:
6594 11:18:51.927065 DQ0 =16, DQ1 =16, DQ2 =12, DQ3 =12
6595 11:18:51.930029 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6596 11:18:51.933482 DQ8 =0, DQ9 =4, DQ10 =12, DQ11 =0
6597 11:18:51.937179 DQ12 =12, DQ13 =16, DQ14 =20, DQ15 =20
6598 11:18:51.937259
6599 11:18:51.937321
6600 11:18:51.943704 [DQSOSCAuto] RK1, (LSB)MR18= 0x9567, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 391 ps
6601 11:18:51.947070 CH0 RK1: MR19=C0C, MR18=9567
6602 11:18:51.953849 CH0_RK1: MR19=0xC0C, MR18=0x9567, DQSOSC=391, MR23=63, INC=386, DEC=257
6603 11:18:51.957286 [RxdqsGatingPostProcess] freq 400
6604 11:18:51.963244 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6605 11:18:51.966827 best DQS0 dly(2T, 0.5T) = (0, 10)
6606 11:18:51.970204 best DQS1 dly(2T, 0.5T) = (0, 10)
6607 11:18:51.973559 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6608 11:18:51.976735 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6609 11:18:51.976816 best DQS0 dly(2T, 0.5T) = (0, 10)
6610 11:18:51.979894 best DQS1 dly(2T, 0.5T) = (0, 10)
6611 11:18:51.983241 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6612 11:18:51.986599 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6613 11:18:51.989866 Pre-setting of DQS Precalculation
6614 11:18:51.996540 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6615 11:18:51.996625 ==
6616 11:18:51.999904 Dram Type= 6, Freq= 0, CH_1, rank 0
6617 11:18:52.003364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6618 11:18:52.003457 ==
6619 11:18:52.009998 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6620 11:18:52.016223 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6621 11:18:52.019981 [CA 0] Center 36 (8~64) winsize 57
6622 11:18:52.020060 [CA 1] Center 36 (8~64) winsize 57
6623 11:18:52.023032 [CA 2] Center 36 (8~64) winsize 57
6624 11:18:52.026182 [CA 3] Center 36 (8~64) winsize 57
6625 11:18:52.030015 [CA 4] Center 36 (8~64) winsize 57
6626 11:18:52.032783 [CA 5] Center 36 (8~64) winsize 57
6627 11:18:52.032863
6628 11:18:52.036493 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6629 11:18:52.036572
6630 11:18:52.039798 [CATrainingPosCal] consider 1 rank data
6631 11:18:52.043134 u2DelayCellTimex100 = 270/100 ps
6632 11:18:52.046380 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 11:18:52.049996 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 11:18:52.056465 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 11:18:52.059733 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 11:18:52.062874 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 11:18:52.066572 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 11:18:52.066651
6639 11:18:52.069472 CA PerBit enable=1, Macro0, CA PI delay=36
6640 11:18:52.069550
6641 11:18:52.073175 [CBTSetCACLKResult] CA Dly = 36
6642 11:18:52.073253 CS Dly: 1 (0~32)
6643 11:18:52.073314 ==
6644 11:18:52.076455 Dram Type= 6, Freq= 0, CH_1, rank 1
6645 11:18:52.083220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6646 11:18:52.083318 ==
6647 11:18:52.086219 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6648 11:18:52.092740 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6649 11:18:52.095837 [CA 0] Center 36 (8~64) winsize 57
6650 11:18:52.099169 [CA 1] Center 36 (8~64) winsize 57
6651 11:18:52.102710 [CA 2] Center 36 (8~64) winsize 57
6652 11:18:52.106522 [CA 3] Center 36 (8~64) winsize 57
6653 11:18:52.109086 [CA 4] Center 36 (8~64) winsize 57
6654 11:18:52.112442 [CA 5] Center 36 (8~64) winsize 57
6655 11:18:52.112522
6656 11:18:52.116290 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6657 11:18:52.116368
6658 11:18:52.119970 [CATrainingPosCal] consider 2 rank data
6659 11:18:52.122590 u2DelayCellTimex100 = 270/100 ps
6660 11:18:52.126261 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6661 11:18:52.129190 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6662 11:18:52.132627 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6663 11:18:52.136106 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6664 11:18:52.139021 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6665 11:18:52.145935 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6666 11:18:52.146017
6667 11:18:52.149284 CA PerBit enable=1, Macro0, CA PI delay=36
6668 11:18:52.149364
6669 11:18:52.152675 [CBTSetCACLKResult] CA Dly = 36
6670 11:18:52.152755 CS Dly: 1 (0~32)
6671 11:18:52.152815
6672 11:18:52.156156 ----->DramcWriteLeveling(PI) begin...
6673 11:18:52.156250 ==
6674 11:18:52.159019 Dram Type= 6, Freq= 0, CH_1, rank 0
6675 11:18:52.162397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6676 11:18:52.166116 ==
6677 11:18:52.166196 Write leveling (Byte 0): 40 => 8
6678 11:18:52.169185 Write leveling (Byte 1): 40 => 8
6679 11:18:52.172536 DramcWriteLeveling(PI) end<-----
6680 11:18:52.172615
6681 11:18:52.172677 ==
6682 11:18:52.175831 Dram Type= 6, Freq= 0, CH_1, rank 0
6683 11:18:52.182913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6684 11:18:52.182994 ==
6685 11:18:52.183056 [Gating] SW mode calibration
6686 11:18:52.192400 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6687 11:18:52.195877 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6688 11:18:52.202042 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6689 11:18:52.205617 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6690 11:18:52.208760 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6691 11:18:52.215985 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6692 11:18:52.218691 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6693 11:18:52.222355 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6694 11:18:52.228621 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6695 11:18:52.232386 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6696 11:18:52.235608 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6697 11:18:52.238847 Total UI for P1: 0, mck2ui 16
6698 11:18:52.241984 best dqsien dly found for B0: ( 0, 14, 24)
6699 11:18:52.245438 Total UI for P1: 0, mck2ui 16
6700 11:18:52.248660 best dqsien dly found for B1: ( 0, 14, 24)
6701 11:18:52.251962 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6702 11:18:52.255490 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6703 11:18:52.255570
6704 11:18:52.258777 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6705 11:18:52.265375 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6706 11:18:52.265456 [Gating] SW calibration Done
6707 11:18:52.265519 ==
6708 11:18:52.268387 Dram Type= 6, Freq= 0, CH_1, rank 0
6709 11:18:52.275106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6710 11:18:52.275188 ==
6711 11:18:52.275249 RX Vref Scan: 0
6712 11:18:52.275306
6713 11:18:52.278404 RX Vref 0 -> 0, step: 1
6714 11:18:52.278483
6715 11:18:52.282400 RX Delay -410 -> 252, step: 16
6716 11:18:52.285310 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6717 11:18:52.288583 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6718 11:18:52.295325 iDelay=230, Bit 2, Center -43 (-282 ~ 197) 480
6719 11:18:52.298714 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6720 11:18:52.302255 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6721 11:18:52.305244 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6722 11:18:52.311867 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6723 11:18:52.314806 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6724 11:18:52.318426 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6725 11:18:52.321741 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6726 11:18:52.328152 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6727 11:18:52.331497 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6728 11:18:52.334810 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6729 11:18:52.338060 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6730 11:18:52.345061 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6731 11:18:52.348508 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6732 11:18:52.348588 ==
6733 11:18:52.351598 Dram Type= 6, Freq= 0, CH_1, rank 0
6734 11:18:52.354635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6735 11:18:52.354718 ==
6736 11:18:52.358066 DQS Delay:
6737 11:18:52.358145 DQS0 = 43, DQS1 = 59
6738 11:18:52.361355 DQM Delay:
6739 11:18:52.361435 DQM0 = 12, DQM1 = 17
6740 11:18:52.361498 DQ Delay:
6741 11:18:52.364494 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6742 11:18:52.368188 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6743 11:18:52.371288 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =16
6744 11:18:52.375008 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6745 11:18:52.375088
6746 11:18:52.375150
6747 11:18:52.375207 ==
6748 11:18:52.377851 Dram Type= 6, Freq= 0, CH_1, rank 0
6749 11:18:52.385024 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6750 11:18:52.385104 ==
6751 11:18:52.385167
6752 11:18:52.385224
6753 11:18:52.385280 TX Vref Scan disable
6754 11:18:52.387968 == TX Byte 0 ==
6755 11:18:52.391321 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6756 11:18:52.394616 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6757 11:18:52.398283 == TX Byte 1 ==
6758 11:18:52.401226 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6759 11:18:52.404404 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6760 11:18:52.404483 ==
6761 11:18:52.408051 Dram Type= 6, Freq= 0, CH_1, rank 0
6762 11:18:52.414424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6763 11:18:52.414506 ==
6764 11:18:52.414568
6765 11:18:52.414626
6766 11:18:52.414681 TX Vref Scan disable
6767 11:18:52.417595 == TX Byte 0 ==
6768 11:18:52.421540 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6769 11:18:52.424324 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6770 11:18:52.427610 == TX Byte 1 ==
6771 11:18:52.430903 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6772 11:18:52.434090 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6773 11:18:52.434170
6774 11:18:52.437776 [DATLAT]
6775 11:18:52.437855 Freq=400, CH1 RK0
6776 11:18:52.437918
6777 11:18:52.440809 DATLAT Default: 0xf
6778 11:18:52.440888 0, 0xFFFF, sum = 0
6779 11:18:52.444068 1, 0xFFFF, sum = 0
6780 11:18:52.444149 2, 0xFFFF, sum = 0
6781 11:18:52.447611 3, 0xFFFF, sum = 0
6782 11:18:52.447691 4, 0xFFFF, sum = 0
6783 11:18:52.451103 5, 0xFFFF, sum = 0
6784 11:18:52.451183 6, 0xFFFF, sum = 0
6785 11:18:52.454961 7, 0xFFFF, sum = 0
6786 11:18:52.457540 8, 0xFFFF, sum = 0
6787 11:18:52.457620 9, 0xFFFF, sum = 0
6788 11:18:52.460708 10, 0xFFFF, sum = 0
6789 11:18:52.460788 11, 0xFFFF, sum = 0
6790 11:18:52.464523 12, 0xFFFF, sum = 0
6791 11:18:52.464603 13, 0x0, sum = 1
6792 11:18:52.467553 14, 0x0, sum = 2
6793 11:18:52.467634 15, 0x0, sum = 3
6794 11:18:52.470913 16, 0x0, sum = 4
6795 11:18:52.470994 best_step = 14
6796 11:18:52.471057
6797 11:18:52.471116 ==
6798 11:18:52.474182 Dram Type= 6, Freq= 0, CH_1, rank 0
6799 11:18:52.477342 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6800 11:18:52.477424 ==
6801 11:18:52.480957 RX Vref Scan: 1
6802 11:18:52.481037
6803 11:18:52.484614 RX Vref 0 -> 0, step: 1
6804 11:18:52.484694
6805 11:18:52.484756 RX Delay -359 -> 252, step: 8
6806 11:18:52.484815
6807 11:18:52.487650 Set Vref, RX VrefLevel [Byte0]: 59
6808 11:18:52.490361 [Byte1]: 48
6809 11:18:52.496196
6810 11:18:52.496280 Final RX Vref Byte 0 = 59 to rank0
6811 11:18:52.499200 Final RX Vref Byte 1 = 48 to rank0
6812 11:18:52.503136 Final RX Vref Byte 0 = 59 to rank1
6813 11:18:52.505909 Final RX Vref Byte 1 = 48 to rank1==
6814 11:18:52.509216 Dram Type= 6, Freq= 0, CH_1, rank 0
6815 11:18:52.516002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6816 11:18:52.516089 ==
6817 11:18:52.516152 DQS Delay:
6818 11:18:52.519459 DQS0 = 48, DQS1 = 60
6819 11:18:52.519541 DQM Delay:
6820 11:18:52.519604 DQM0 = 12, DQM1 = 12
6821 11:18:52.522765 DQ Delay:
6822 11:18:52.525966 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6823 11:18:52.526074 DQ4 =8, DQ5 =20, DQ6 =24, DQ7 =12
6824 11:18:52.529432 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6825 11:18:52.532441 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6826 11:18:52.535774
6827 11:18:52.535854
6828 11:18:52.542800 [DQSOSCAuto] RK0, (LSB)MR18= 0x8b32, (MSB)MR19= 0xc0c, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
6829 11:18:52.545780 CH1 RK0: MR19=C0C, MR18=8B32
6830 11:18:52.552720 CH1_RK0: MR19=0xC0C, MR18=0x8B32, DQSOSC=392, MR23=63, INC=384, DEC=256
6831 11:18:52.552803 ==
6832 11:18:52.555759 Dram Type= 6, Freq= 0, CH_1, rank 1
6833 11:18:52.559326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6834 11:18:52.559445 ==
6835 11:18:52.562512 [Gating] SW mode calibration
6836 11:18:52.569447 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6837 11:18:52.575385 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6838 11:18:52.578907 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6839 11:18:52.582437 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6840 11:18:52.589186 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6841 11:18:52.592063 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6842 11:18:52.595665 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6843 11:18:52.602574 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6844 11:18:52.605241 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6845 11:18:52.609098 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6846 11:18:52.615270 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6847 11:18:52.615360 Total UI for P1: 0, mck2ui 16
6848 11:18:52.622218 best dqsien dly found for B0: ( 0, 14, 24)
6849 11:18:52.622333 Total UI for P1: 0, mck2ui 16
6850 11:18:52.625003 best dqsien dly found for B1: ( 0, 14, 24)
6851 11:18:52.632077 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6852 11:18:52.635108 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6853 11:18:52.635191
6854 11:18:52.638666 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6855 11:18:52.641561 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6856 11:18:52.644812 [Gating] SW calibration Done
6857 11:18:52.644892 ==
6858 11:18:52.648310 Dram Type= 6, Freq= 0, CH_1, rank 1
6859 11:18:52.651723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6860 11:18:52.651803 ==
6861 11:18:52.655005 RX Vref Scan: 0
6862 11:18:52.655083
6863 11:18:52.655144 RX Vref 0 -> 0, step: 1
6864 11:18:52.655201
6865 11:18:52.658553 RX Delay -410 -> 252, step: 16
6866 11:18:52.664686 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6867 11:18:52.668328 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6868 11:18:52.671309 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6869 11:18:52.674938 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6870 11:18:52.681342 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6871 11:18:52.684515 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6872 11:18:52.688111 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6873 11:18:52.691492 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6874 11:18:52.697742 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6875 11:18:52.701288 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6876 11:18:52.704267 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6877 11:18:52.707639 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6878 11:18:52.714223 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6879 11:18:52.717503 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6880 11:18:52.720836 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6881 11:18:52.728184 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6882 11:18:52.728274 ==
6883 11:18:52.730633 Dram Type= 6, Freq= 0, CH_1, rank 1
6884 11:18:52.733984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6885 11:18:52.734065 ==
6886 11:18:52.734128 DQS Delay:
6887 11:18:52.737497 DQS0 = 43, DQS1 = 51
6888 11:18:52.737576 DQM Delay:
6889 11:18:52.740605 DQM0 = 9, DQM1 = 10
6890 11:18:52.740684 DQ Delay:
6891 11:18:52.744502 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6892 11:18:52.747508 DQ4 =8, DQ5 =24, DQ6 =16, DQ7 =8
6893 11:18:52.751086 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6894 11:18:52.753990 DQ12 =16, DQ13 =24, DQ14 =16, DQ15 =16
6895 11:18:52.754069
6896 11:18:52.754130
6897 11:18:52.754187 ==
6898 11:18:52.757279 Dram Type= 6, Freq= 0, CH_1, rank 1
6899 11:18:52.760666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6900 11:18:52.760745 ==
6901 11:18:52.760807
6902 11:18:52.760863
6903 11:18:52.763807 TX Vref Scan disable
6904 11:18:52.763886 == TX Byte 0 ==
6905 11:18:52.770882 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6906 11:18:52.774058 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6907 11:18:52.774138 == TX Byte 1 ==
6908 11:18:52.780352 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6909 11:18:52.783992 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6910 11:18:52.784072 ==
6911 11:18:52.787895 Dram Type= 6, Freq= 0, CH_1, rank 1
6912 11:18:52.790488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6913 11:18:52.790568 ==
6914 11:18:52.790630
6915 11:18:52.790687
6916 11:18:52.793675 TX Vref Scan disable
6917 11:18:52.793779 == TX Byte 0 ==
6918 11:18:52.800758 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6919 11:18:52.804358 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6920 11:18:52.804438 == TX Byte 1 ==
6921 11:18:52.810438 Update DQ dly =584 (4 ,2, 8) DQ OEN =(3 ,3)
6922 11:18:52.813903 Update DQM dly =584 (4 ,2, 8) DQM OEN =(3 ,3)
6923 11:18:52.813983
6924 11:18:52.814044 [DATLAT]
6925 11:18:52.817312 Freq=400, CH1 RK1
6926 11:18:52.817392
6927 11:18:52.817453 DATLAT Default: 0xe
6928 11:18:52.820622 0, 0xFFFF, sum = 0
6929 11:18:52.820712 1, 0xFFFF, sum = 0
6930 11:18:52.823606 2, 0xFFFF, sum = 0
6931 11:18:52.823686 3, 0xFFFF, sum = 0
6932 11:18:52.827272 4, 0xFFFF, sum = 0
6933 11:18:52.827417 5, 0xFFFF, sum = 0
6934 11:18:52.830534 6, 0xFFFF, sum = 0
6935 11:18:52.830616 7, 0xFFFF, sum = 0
6936 11:19:01.361780 8, 0xFFFF, sum = 0
6937 11:19:01.362242 9, 0xFFFF, sum = 0
6938 11:19:01.362574 10, 0xFFFF, sum = 0
6939 11:19:01.362913 11, 0xFFFF, sum = 0
6940 11:19:01.363216 12, 0xFFFF, sum = 0
6941 11:19:01.363554 13, 0x0, sum = 1
6942 11:19:01.363844 14, 0x0, sum = 2
6943 11:19:01.364205 15, 0x0, sum = 3
6944 11:19:01.364659 16, 0x0, sum = 4
6945 11:19:01.365143 best_step = 14
6946 11:19:01.365450
6947 11:19:01.365730 ==
6948 11:19:01.366005 Dram Type= 6, Freq= 0, CH_1, rank 1
6949 11:19:01.366279 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6950 11:19:01.366555 ==
6951 11:19:01.366823 RX Vref Scan: 0
6952 11:19:01.367091
6953 11:19:01.367465 RX Vref 0 -> 0, step: 1
6954 11:19:01.367966
6955 11:19:01.368258 RX Delay -343 -> 252, step: 8
6956 11:19:01.368552 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6957 11:19:01.368832 iDelay=217, Bit 1, Center -44 (-287 ~ 200) 488
6958 11:19:01.369104 iDelay=217, Bit 2, Center -52 (-295 ~ 192) 488
6959 11:19:01.369375 iDelay=217, Bit 3, Center -40 (-279 ~ 200) 480
6960 11:19:01.369642 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6961 11:19:01.369912 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6962 11:19:01.370181 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6963 11:19:01.370450 iDelay=217, Bit 7, Center -44 (-287 ~ 200) 488
6964 11:19:01.370718 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6965 11:19:01.371002 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6966 11:19:01.371275 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6967 11:19:01.371589 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6968 11:19:01.371860 iDelay=217, Bit 12, Center -40 (-279 ~ 200) 480
6969 11:19:01.372129 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6970 11:19:01.372397 iDelay=217, Bit 14, Center -40 (-287 ~ 208) 496
6971 11:19:01.372667 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6972 11:19:01.372935 ==
6973 11:19:01.373203 Dram Type= 6, Freq= 0, CH_1, rank 1
6974 11:19:01.373472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6975 11:19:01.373739 ==
6976 11:19:01.374006 DQS Delay:
6977 11:19:01.374274 DQS0 = 52, DQS1 = 60
6978 11:19:01.374543 DQM Delay:
6979 11:19:01.374808 DQM0 = 13, DQM1 = 13
6980 11:19:01.375074 DQ Delay:
6981 11:19:01.375339 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6982 11:19:01.375643 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =8
6983 11:19:01.375913 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6984 11:19:01.376181 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
6985 11:19:01.376446
6986 11:19:01.376710
6987 11:19:01.376975 [DQSOSCAuto] RK1, (LSB)MR18= 0x758b, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 395 ps
6988 11:19:01.377247 CH1 RK1: MR19=C0C, MR18=758B
6989 11:19:01.377513 CH1_RK1: MR19=0xC0C, MR18=0x758B, DQSOSC=392, MR23=63, INC=384, DEC=256
6990 11:19:01.377785 [RxdqsGatingPostProcess] freq 400
6991 11:19:01.378053 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6992 11:19:01.378346 best DQS0 dly(2T, 0.5T) = (0, 10)
6993 11:19:01.378616 best DQS1 dly(2T, 0.5T) = (0, 10)
6994 11:19:01.378882 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6995 11:19:01.379149 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6996 11:19:01.379446 best DQS0 dly(2T, 0.5T) = (0, 10)
6997 11:19:01.379720 best DQS1 dly(2T, 0.5T) = (0, 10)
6998 11:19:01.379986 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6999 11:19:01.380256 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7000 11:19:01.380521 Pre-setting of DQS Precalculation
7001 11:19:01.380789 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7002 11:19:01.381059 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7003 11:19:01.381333 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7004 11:19:01.381605
7005 11:19:01.381868
7006 11:19:01.382134 [Calibration Summary] 800 Mbps
7007 11:19:01.382403 CH 0, Rank 0
7008 11:19:01.382670 SW Impedance : PASS
7009 11:19:01.382903 DUTY Scan : NO K
7010 11:19:01.383092 ZQ Calibration : PASS
7011 11:19:01.383283 Jitter Meter : NO K
7012 11:19:01.383493 CBT Training : PASS
7013 11:19:01.383687 Write leveling : PASS
7014 11:19:01.383877 RX DQS gating : PASS
7015 11:19:01.384069 RX DQ/DQS(RDDQC) : PASS
7016 11:19:01.384261 TX DQ/DQS : PASS
7017 11:19:01.384454 RX DATLAT : PASS
7018 11:19:01.384644 RX DQ/DQS(Engine): PASS
7019 11:19:01.384834 TX OE : NO K
7020 11:19:01.385027 All Pass.
7021 11:19:01.385217
7022 11:19:01.385407 CH 0, Rank 1
7023 11:19:01.385596 SW Impedance : PASS
7024 11:19:01.385787 DUTY Scan : NO K
7025 11:19:01.385976 ZQ Calibration : PASS
7026 11:19:01.386167 Jitter Meter : NO K
7027 11:19:01.386356 CBT Training : PASS
7028 11:19:01.386545 Write leveling : NO K
7029 11:19:01.386736 RX DQS gating : PASS
7030 11:19:01.386928 RX DQ/DQS(RDDQC) : PASS
7031 11:19:01.387116 TX DQ/DQS : PASS
7032 11:19:01.387306 RX DATLAT : PASS
7033 11:19:01.387556 RX DQ/DQS(Engine): PASS
7034 11:19:01.387751 TX OE : NO K
7035 11:19:01.387912 All Pass.
7036 11:19:01.388056
7037 11:19:01.388200 CH 1, Rank 0
7038 11:19:01.388343 SW Impedance : PASS
7039 11:19:01.388487 DUTY Scan : NO K
7040 11:19:01.388629 ZQ Calibration : PASS
7041 11:19:01.388771 Jitter Meter : NO K
7042 11:19:01.388915 CBT Training : PASS
7043 11:19:01.389060 Write leveling : PASS
7044 11:19:01.389202 RX DQS gating : PASS
7045 11:19:01.389345 RX DQ/DQS(RDDQC) : PASS
7046 11:19:01.389489 TX DQ/DQS : PASS
7047 11:19:01.389633 RX DATLAT : PASS
7048 11:19:01.389777 RX DQ/DQS(Engine): PASS
7049 11:19:01.389919 TX OE : NO K
7050 11:19:01.390064 All Pass.
7051 11:19:01.390205
7052 11:19:01.390347 CH 1, Rank 1
7053 11:19:01.390489 SW Impedance : PASS
7054 11:19:01.390631 DUTY Scan : NO K
7055 11:19:01.390777 ZQ Calibration : PASS
7056 11:19:01.390921 Jitter Meter : NO K
7057 11:19:01.391063 CBT Training : PASS
7058 11:19:01.391207 Write leveling : NO K
7059 11:19:01.391364 RX DQS gating : PASS
7060 11:19:01.391513 RX DQ/DQS(RDDQC) : PASS
7061 11:19:01.391657 TX DQ/DQS : PASS
7062 11:19:01.391799 RX DATLAT : PASS
7063 11:19:01.391944 RX DQ/DQS(Engine): PASS
7064 11:19:01.392086 TX OE : NO K
7065 11:19:01.392230 All Pass.
7066 11:19:01.392372
7067 11:19:01.392514 DramC Write-DBI off
7068 11:19:01.392657 PER_BANK_REFRESH: Hybrid Mode
7069 11:19:01.392800 TX_TRACKING: ON
7070 11:19:01.392920 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7071 11:19:01.393042 [FAST_K] Save calibration result to emmc
7072 11:19:01.393162 dramc_set_vcore_voltage set vcore to 725000
7073 11:19:01.393282 Read voltage for 1600, 0
7074 11:19:01.393400 Vio18 = 0
7075 11:19:01.393519 Vcore = 725000
7076 11:19:01.393639 Vdram = 0
7077 11:19:01.393759 Vddq = 0
7078 11:19:01.393877 Vmddr = 0
7079 11:19:01.393996 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7080 11:19:01.394343 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7081 11:19:01.394481 MEM_TYPE=3, freq_sel=13
7082 11:19:01.394603 sv_algorithm_assistance_LP4_3733
7083 11:19:01.394725 ============ PULL DRAM RESETB DOWN ============
7084 11:19:01.394846 ========== PULL DRAM RESETB DOWN end =========
7085 11:19:01.394967 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7086 11:19:01.395086 ===================================
7087 11:19:01.395207 LPDDR4 DRAM CONFIGURATION
7088 11:19:01.395325 ===================================
7089 11:19:01.395466 EX_ROW_EN[0] = 0x0
7090 11:19:01.395585 EX_ROW_EN[1] = 0x0
7091 11:19:01.395704 LP4Y_EN = 0x0
7092 11:19:01.395822 WORK_FSP = 0x1
7093 11:19:01.395941 WL = 0x5
7094 11:19:01.396058 RL = 0x5
7095 11:19:01.396176 BL = 0x2
7096 11:19:01.396294 RPST = 0x0
7097 11:19:01.396414 RD_PRE = 0x0
7098 11:19:01.396532 WR_PRE = 0x1
7099 11:19:01.396650 WR_PST = 0x1
7100 11:19:01.396769 DBI_WR = 0x0
7101 11:19:01.396887 DBI_RD = 0x0
7102 11:19:01.397005 OTF = 0x1
7103 11:19:01.397123 ===================================
7104 11:19:01.397242 ===================================
7105 11:19:01.397362 ANA top config
7106 11:19:01.397482 ===================================
7107 11:19:01.397602 DLL_ASYNC_EN = 0
7108 11:19:01.397721 ALL_SLAVE_EN = 0
7109 11:19:01.397836 NEW_RANK_MODE = 1
7110 11:19:01.397937 DLL_IDLE_MODE = 1
7111 11:19:01.398035 LP45_APHY_COMB_EN = 1
7112 11:19:01.398133 TX_ODT_DIS = 0
7113 11:19:01.398233 NEW_8X_MODE = 1
7114 11:19:01.398333 ===================================
7115 11:19:01.398432 ===================================
7116 11:19:01.398532 data_rate = 3200
7117 11:19:01.398631 CKR = 1
7118 11:19:01.398731 DQ_P2S_RATIO = 8
7119 11:19:01.398830 ===================================
7120 11:19:01.398930 CA_P2S_RATIO = 8
7121 11:19:01.399030 DQ_CA_OPEN = 0
7122 11:19:01.399128 DQ_SEMI_OPEN = 0
7123 11:19:01.399227 CA_SEMI_OPEN = 0
7124 11:19:01.399326 CA_FULL_RATE = 0
7125 11:19:01.399436 DQ_CKDIV4_EN = 0
7126 11:19:01.399536 CA_CKDIV4_EN = 0
7127 11:19:01.399635 CA_PREDIV_EN = 0
7128 11:19:01.399734 PH8_DLY = 12
7129 11:19:01.399835 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7130 11:19:01.399934 DQ_AAMCK_DIV = 4
7131 11:19:01.400034 CA_AAMCK_DIV = 4
7132 11:19:01.400134 CA_ADMCK_DIV = 4
7133 11:19:01.400234 DQ_TRACK_CA_EN = 0
7134 11:19:01.400333 CA_PICK = 1600
7135 11:19:01.400434 CA_MCKIO = 1600
7136 11:19:01.400533 MCKIO_SEMI = 0
7137 11:19:01.400633 PLL_FREQ = 3068
7138 11:19:01.400733 DQ_UI_PI_RATIO = 32
7139 11:19:01.400833 CA_UI_PI_RATIO = 0
7140 11:19:01.400932 ===================================
7141 11:19:01.401032 ===================================
7142 11:19:01.401131 memory_type:LPDDR4
7143 11:19:01.401231 GP_NUM : 10
7144 11:19:01.401330 SRAM_EN : 1
7145 11:19:01.401429 MD32_EN : 0
7146 11:19:01.401528 ===================================
7147 11:19:01.401628 [ANA_INIT] >>>>>>>>>>>>>>
7148 11:19:01.401727 <<<<<< [CONFIGURE PHASE]: ANA_TX
7149 11:19:01.401827 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7150 11:19:01.401926 ===================================
7151 11:19:01.402025 data_rate = 3200,PCW = 0X7600
7152 11:19:01.402123 ===================================
7153 11:19:01.402222 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7154 11:19:01.402323 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7155 11:19:01.402424 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7156 11:19:01.402524 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7157 11:19:01.402624 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7158 11:19:01.402723 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7159 11:19:01.402826 [ANA_INIT] flow start
7160 11:19:01.402911 [ANA_INIT] PLL >>>>>>>>
7161 11:19:01.402996 [ANA_INIT] PLL <<<<<<<<
7162 11:19:01.403082 [ANA_INIT] MIDPI >>>>>>>>
7163 11:19:01.403166 [ANA_INIT] MIDPI <<<<<<<<
7164 11:19:01.403251 [ANA_INIT] DLL >>>>>>>>
7165 11:19:01.403334 [ANA_INIT] DLL <<<<<<<<
7166 11:19:01.403457 [ANA_INIT] flow end
7167 11:19:01.403545 ============ LP4 DIFF to SE enter ============
7168 11:19:01.403633 ============ LP4 DIFF to SE exit ============
7169 11:19:01.403719 [ANA_INIT] <<<<<<<<<<<<<
7170 11:19:01.403805 [Flow] Enable top DCM control >>>>>
7171 11:19:01.403891 [Flow] Enable top DCM control <<<<<
7172 11:19:01.403976 Enable DLL master slave shuffle
7173 11:19:01.404061 ==============================================================
7174 11:19:01.404149 Gating Mode config
7175 11:19:01.404234 ==============================================================
7176 11:19:01.404321 Config description:
7177 11:19:01.404406 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7178 11:19:01.404494 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7179 11:19:01.404582 SELPH_MODE 0: By rank 1: By Phase
7180 11:19:01.404668 ==============================================================
7181 11:19:01.404753 GAT_TRACK_EN = 1
7182 11:19:01.404839 RX_GATING_MODE = 2
7183 11:19:01.404925 RX_GATING_TRACK_MODE = 2
7184 11:19:01.405010 SELPH_MODE = 1
7185 11:19:01.405095 PICG_EARLY_EN = 1
7186 11:19:01.405181 VALID_LAT_VALUE = 1
7187 11:19:01.405268 ==============================================================
7188 11:19:01.405354 Enter into Gating configuration >>>>
7189 11:19:01.405440 Exit from Gating configuration <<<<
7190 11:19:01.405526 Enter into DVFS_PRE_config >>>>>
7191 11:19:01.405612 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7192 11:19:01.405700 Exit from DVFS_PRE_config <<<<<
7193 11:19:01.405785 Enter into PICG configuration >>>>
7194 11:19:01.405871 Exit from PICG configuration <<<<
7195 11:19:01.406157 [RX_INPUT] configuration >>>>>
7196 11:19:01.406254 [RX_INPUT] configuration <<<<<
7197 11:19:01.406340 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7198 11:19:01.406427 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7199 11:19:01.406514 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7200 11:19:01.406601 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7201 11:19:01.406687 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7202 11:19:01.406773 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7203 11:19:01.406860 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7204 11:19:01.406945 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7205 11:19:01.407031 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7206 11:19:01.407118 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7207 11:19:01.407204 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7208 11:19:01.407290 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7209 11:19:01.407388 ===================================
7210 11:19:01.407478 LPDDR4 DRAM CONFIGURATION
7211 11:19:01.407562 ===================================
7212 11:19:01.407648 EX_ROW_EN[0] = 0x0
7213 11:19:01.407733 EX_ROW_EN[1] = 0x0
7214 11:19:01.407825 LP4Y_EN = 0x0
7215 11:19:01.407899 WORK_FSP = 0x1
7216 11:19:01.407974 WL = 0x5
7217 11:19:01.408049 RL = 0x5
7218 11:19:01.408123 BL = 0x2
7219 11:19:01.408198 RPST = 0x0
7220 11:19:01.408272 RD_PRE = 0x0
7221 11:19:01.408346 WR_PRE = 0x1
7222 11:19:01.408420 WR_PST = 0x1
7223 11:19:01.408495 DBI_WR = 0x0
7224 11:19:01.408569 DBI_RD = 0x0
7225 11:19:01.408643 OTF = 0x1
7226 11:19:01.408718 ===================================
7227 11:19:01.408793 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7228 11:19:01.408868 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7229 11:19:01.408943 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7230 11:19:01.409018 ===================================
7231 11:19:01.409093 LPDDR4 DRAM CONFIGURATION
7232 11:19:01.409168 ===================================
7233 11:19:01.409244 EX_ROW_EN[0] = 0x10
7234 11:19:01.409319 EX_ROW_EN[1] = 0x0
7235 11:19:01.409394 LP4Y_EN = 0x0
7236 11:19:01.409468 WORK_FSP = 0x1
7237 11:19:01.409543 WL = 0x5
7238 11:19:01.409617 RL = 0x5
7239 11:19:01.409691 BL = 0x2
7240 11:19:01.409765 RPST = 0x0
7241 11:19:01.409839 RD_PRE = 0x0
7242 11:19:01.409913 WR_PRE = 0x1
7243 11:19:01.409988 WR_PST = 0x1
7244 11:19:01.410062 DBI_WR = 0x0
7245 11:19:01.410136 DBI_RD = 0x0
7246 11:19:01.410210 OTF = 0x1
7247 11:19:01.410284 ===================================
7248 11:19:01.410359 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7249 11:19:01.410435 ==
7250 11:19:01.410510 Dram Type= 6, Freq= 0, CH_0, rank 0
7251 11:19:01.410584 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7252 11:19:01.410660 ==
7253 11:19:01.410734 [Duty_Offset_Calibration]
7254 11:19:01.410808 B0:2 B1:-1 CA:1
7255 11:19:01.410883
7256 11:19:01.410956 [DutyScan_Calibration_Flow] k_type=0
7257 11:19:01.411031
7258 11:19:01.411105 ==CLK 0==
7259 11:19:01.411180 Final CLK duty delay cell = -4
7260 11:19:01.411255 [-4] MAX Duty = 5031%(X100), DQS PI = 22
7261 11:19:01.411330 [-4] MIN Duty = 4844%(X100), DQS PI = 32
7262 11:19:01.411417 [-4] AVG Duty = 4937%(X100)
7263 11:19:01.411492
7264 11:19:01.411566 CH0 CLK Duty spec in!! Max-Min= 187%
7265 11:19:01.411641 [DutyScan_Calibration_Flow] ====Done====
7266 11:19:01.411715
7267 11:19:01.411790 [DutyScan_Calibration_Flow] k_type=1
7268 11:19:01.411863
7269 11:19:01.411938 ==DQS 0 ==
7270 11:19:01.412012 Final DQS duty delay cell = 0
7271 11:19:01.412087 [0] MAX Duty = 5125%(X100), DQS PI = 56
7272 11:19:01.412161 [0] MIN Duty = 5000%(X100), DQS PI = 14
7273 11:19:01.412235 [0] AVG Duty = 5062%(X100)
7274 11:19:01.412309
7275 11:19:01.412383 ==DQS 1 ==
7276 11:19:01.412456 Final DQS duty delay cell = -4
7277 11:19:01.412531 [-4] MAX Duty = 5093%(X100), DQS PI = 0
7278 11:19:01.412606 [-4] MIN Duty = 5000%(X100), DQS PI = 40
7279 11:19:01.412681 [-4] AVG Duty = 5046%(X100)
7280 11:19:01.412764
7281 11:19:01.412830 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7282 11:19:01.412896
7283 11:19:01.412961 CH0 DQS 1 Duty spec in!! Max-Min= 93%
7284 11:19:01.413028 [DutyScan_Calibration_Flow] ====Done====
7285 11:19:01.413093
7286 11:19:01.413159 [DutyScan_Calibration_Flow] k_type=3
7287 11:19:01.413225
7288 11:19:01.413291 ==DQM 0 ==
7289 11:19:01.413357 Final DQM duty delay cell = 0
7290 11:19:01.413423 [0] MAX Duty = 5000%(X100), DQS PI = 20
7291 11:19:01.413490 [0] MIN Duty = 4875%(X100), DQS PI = 4
7292 11:19:01.413556 [0] AVG Duty = 4937%(X100)
7293 11:19:01.413621
7294 11:19:01.413686 ==DQM 1 ==
7295 11:19:01.413750 Final DQM duty delay cell = 0
7296 11:19:01.413814 [0] MAX Duty = 5187%(X100), DQS PI = 58
7297 11:19:01.413879 [0] MIN Duty = 4969%(X100), DQS PI = 18
7298 11:19:01.413943 [0] AVG Duty = 5078%(X100)
7299 11:19:01.414007
7300 11:19:01.414070 CH0 DQM 0 Duty spec in!! Max-Min= 125%
7301 11:19:01.414134
7302 11:19:01.414197 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7303 11:19:01.414262 [DutyScan_Calibration_Flow] ====Done====
7304 11:19:01.414326
7305 11:19:01.414389 [DutyScan_Calibration_Flow] k_type=2
7306 11:19:01.414452
7307 11:19:01.414516 ==DQ 0 ==
7308 11:19:01.414580 Final DQ duty delay cell = 0
7309 11:19:01.414644 [0] MAX Duty = 5156%(X100), DQS PI = 0
7310 11:19:01.414707 [0] MIN Duty = 5031%(X100), DQS PI = 12
7311 11:19:01.414771 [0] AVG Duty = 5093%(X100)
7312 11:19:01.414835
7313 11:19:01.414898 ==DQ 1 ==
7314 11:19:01.414962 Final DQ duty delay cell = 0
7315 11:19:01.415026 [0] MAX Duty = 5031%(X100), DQS PI = 30
7316 11:19:01.415091 [0] MIN Duty = 4938%(X100), DQS PI = 4
7317 11:19:01.415155 [0] AVG Duty = 4984%(X100)
7318 11:19:01.415219
7319 11:19:01.415283 CH0 DQ 0 Duty spec in!! Max-Min= 125%
7320 11:19:01.415352
7321 11:19:01.415418 CH0 DQ 1 Duty spec in!! Max-Min= 93%
7322 11:19:01.415482 [DutyScan_Calibration_Flow] ====Done====
7323 11:19:01.415546 ==
7324 11:19:01.415610 Dram Type= 6, Freq= 0, CH_1, rank 0
7325 11:19:01.415674 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7326 11:19:01.415740 ==
7327 11:19:01.415804 [Duty_Offset_Calibration]
7328 11:19:01.415868 B0:1 B1:1 CA:2
7329 11:19:01.415932
7330 11:19:01.415996 [DutyScan_Calibration_Flow] k_type=0
7331 11:19:01.416060
7332 11:19:01.416122 ==CLK 0==
7333 11:19:01.416186 Final CLK duty delay cell = 0
7334 11:19:01.416250 [0] MAX Duty = 5156%(X100), DQS PI = 24
7335 11:19:01.416314 [0] MIN Duty = 4938%(X100), DQS PI = 50
7336 11:19:01.416378 [0] AVG Duty = 5047%(X100)
7337 11:19:01.416444
7338 11:19:01.416508 CH1 CLK Duty spec in!! Max-Min= 218%
7339 11:19:01.416572 [DutyScan_Calibration_Flow] ====Done====
7340 11:19:01.416635
7341 11:19:01.416893 [DutyScan_Calibration_Flow] k_type=1
7342 11:19:01.416972
7343 11:19:01.417038 ==DQS 0 ==
7344 11:19:01.417103 Final DQS duty delay cell = 0
7345 11:19:01.417168 [0] MAX Duty = 5062%(X100), DQS PI = 20
7346 11:19:01.417233 [0] MIN Duty = 4813%(X100), DQS PI = 52
7347 11:19:01.417298 [0] AVG Duty = 4937%(X100)
7348 11:19:01.417362
7349 11:19:01.417426 ==DQS 1 ==
7350 11:19:01.417491 Final DQS duty delay cell = 0
7351 11:19:01.417556 [0] MAX Duty = 5031%(X100), DQS PI = 36
7352 11:19:01.417619 [0] MIN Duty = 4938%(X100), DQS PI = 12
7353 11:19:01.417684 [0] AVG Duty = 4984%(X100)
7354 11:19:01.417760
7355 11:19:01.417817 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7356 11:19:01.417875
7357 11:19:01.417933 CH1 DQS 1 Duty spec in!! Max-Min= 93%
7358 11:19:01.417990 [DutyScan_Calibration_Flow] ====Done====
7359 11:19:01.418048
7360 11:19:01.418105 [DutyScan_Calibration_Flow] k_type=3
7361 11:19:01.418162
7362 11:19:01.418220 ==DQM 0 ==
7363 11:19:01.418278 Final DQM duty delay cell = 0
7364 11:19:01.418336 [0] MAX Duty = 5124%(X100), DQS PI = 18
7365 11:19:01.418393 [0] MIN Duty = 4813%(X100), DQS PI = 50
7366 11:19:01.418451 [0] AVG Duty = 4968%(X100)
7367 11:19:01.418509
7368 11:19:01.418566 ==DQM 1 ==
7369 11:19:01.418624 Final DQM duty delay cell = 0
7370 11:19:01.418682 [0] MAX Duty = 5125%(X100), DQS PI = 8
7371 11:19:01.418740 [0] MIN Duty = 4875%(X100), DQS PI = 22
7372 11:19:01.418798 [0] AVG Duty = 5000%(X100)
7373 11:19:01.418856
7374 11:19:01.418913 CH1 DQM 0 Duty spec in!! Max-Min= 311%
7375 11:19:01.418970
7376 11:19:01.419028 CH1 DQM 1 Duty spec in!! Max-Min= 250%
7377 11:19:01.419086 [DutyScan_Calibration_Flow] ====Done====
7378 11:19:01.419143
7379 11:19:01.419200 [DutyScan_Calibration_Flow] k_type=2
7380 11:19:01.419259
7381 11:19:01.419316 ==DQ 0 ==
7382 11:19:01.419382 Final DQ duty delay cell = 0
7383 11:19:01.419442 [0] MAX Duty = 5156%(X100), DQS PI = 22
7384 11:19:01.419500 [0] MIN Duty = 4907%(X100), DQS PI = 52
7385 11:19:01.419558 [0] AVG Duty = 5031%(X100)
7386 11:19:01.419616
7387 11:19:01.419673 ==DQ 1 ==
7388 11:19:01.419732 Final DQ duty delay cell = 0
7389 11:19:01.419791 [0] MAX Duty = 5124%(X100), DQS PI = 42
7390 11:19:01.419849 [0] MIN Duty = 5031%(X100), DQS PI = 0
7391 11:19:01.419907 [0] AVG Duty = 5077%(X100)
7392 11:19:01.419964
7393 11:19:01.420021 CH1 DQ 0 Duty spec in!! Max-Min= 249%
7394 11:19:01.420079
7395 11:19:01.420136 CH1 DQ 1 Duty spec in!! Max-Min= 93%
7396 11:19:01.420194 [DutyScan_Calibration_Flow] ====Done====
7397 11:19:01.420252 nWR fixed to 30
7398 11:19:01.420311 [ModeRegInit_LP4] CH0 RK0
7399 11:19:01.420369 [ModeRegInit_LP4] CH0 RK1
7400 11:19:01.420426 [ModeRegInit_LP4] CH1 RK0
7401 11:19:01.420484 [ModeRegInit_LP4] CH1 RK1
7402 11:19:01.420541 match AC timing 5
7403 11:19:01.420599 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7404 11:19:01.420657 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7405 11:19:01.420714 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7406 11:19:01.420773 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7407 11:19:01.420831 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7408 11:19:01.420889 [MiockJmeterHQA]
7409 11:19:01.420946
7410 11:19:01.421003 [DramcMiockJmeter] u1RxGatingPI = 0
7411 11:19:01.421061 0 : 4260, 4029
7412 11:19:01.421120 4 : 4252, 4027
7413 11:19:01.421180 8 : 4253, 4026
7414 11:19:01.421239 12 : 4255, 4029
7415 11:19:01.421298 16 : 4363, 4137
7416 11:19:01.421357 20 : 4252, 4027
7417 11:19:01.421415 24 : 4252, 4027
7418 11:19:01.421474 28 : 4252, 4027
7419 11:19:01.421533 32 : 4253, 4026
7420 11:19:01.421591 36 : 4252, 4027
7421 11:19:01.421649 40 : 4250, 4027
7422 11:19:01.421708 44 : 4370, 4143
7423 11:19:01.421767 48 : 4252, 4030
7424 11:19:01.421825 52 : 4250, 4027
7425 11:19:01.421883 56 : 4255, 4029
7426 11:19:01.421942 60 : 4252, 4029
7427 11:19:01.422001 64 : 4258, 4034
7428 11:19:01.422059 68 : 4249, 4027
7429 11:19:01.422117 72 : 4252, 4029
7430 11:19:01.422176 76 : 4255, 4031
7431 11:19:01.422234 80 : 4252, 4029
7432 11:19:01.422293 84 : 4252, 4030
7433 11:19:01.422351 88 : 4253, 4029
7434 11:19:01.422409 92 : 4250, 4027
7435 11:19:01.422467 96 : 4257, 3164
7436 11:19:01.422526 100 : 4252, 0
7437 11:19:01.422586 104 : 4253, 0
7438 11:19:01.422644 108 : 4365, 0
7439 11:19:01.422703 112 : 4253, 0
7440 11:19:01.422774 116 : 4255, 0
7441 11:19:01.422827 120 : 4250, 0
7442 11:19:01.422879 124 : 4363, 0
7443 11:19:01.422932 128 : 4252, 0
7444 11:19:01.422986 132 : 4250, 0
7445 11:19:01.423039 136 : 4364, 0
7446 11:19:01.423092 140 : 4250, 0
7447 11:19:01.423145 144 : 4250, 0
7448 11:19:01.423199 148 : 4250, 0
7449 11:19:01.423252 152 : 4361, 0
7450 11:19:01.423305 156 : 4253, 0
7451 11:19:01.423368 160 : 4252, 0
7452 11:19:01.423424 164 : 4250, 0
7453 11:19:01.423477 168 : 4360, 0
7454 11:19:01.423531 172 : 4250, 0
7455 11:19:01.423584 176 : 4252, 0
7456 11:19:01.423641 180 : 4365, 0
7457 11:19:01.423694 184 : 4250, 0
7458 11:19:01.423748 188 : 4365, 0
7459 11:19:01.423801 192 : 4249, 0
7460 11:19:01.423854 196 : 4255, 0
7461 11:19:01.423907 200 : 4360, 0
7462 11:19:01.423960 204 : 4363, 0
7463 11:19:01.424014 208 : 4255, 0
7464 11:19:01.424067 212 : 4253, 192
7465 11:19:01.424121 216 : 4255, 3877
7466 11:19:01.424174 220 : 4255, 4029
7467 11:19:01.424227 224 : 4250, 4027
7468 11:19:01.424280 228 : 4255, 4029
7469 11:19:01.424335 232 : 4255, 4029
7470 11:19:01.424388 236 : 4363, 4139
7471 11:19:01.424441 240 : 4250, 4027
7472 11:19:01.424494 244 : 4250, 4026
7473 11:19:01.424548 248 : 4255, 4029
7474 11:19:01.424601 252 : 4360, 4138
7475 11:19:01.424654 256 : 4252, 4030
7476 11:19:01.424707 260 : 4361, 4137
7477 11:19:01.424760 264 : 4252, 4029
7478 11:19:01.424813 268 : 4255, 4029
7479 11:19:01.424867 272 : 4360, 4138
7480 11:19:01.424920 276 : 4361, 4138
7481 11:19:01.424973 280 : 4252, 4027
7482 11:19:01.425026 284 : 4250, 4027
7483 11:19:01.425080 288 : 4363, 4140
7484 11:19:01.425133 292 : 4250, 4027
7485 11:19:01.425186 296 : 4255, 4029
7486 11:19:01.425238 300 : 4363, 4140
7487 11:19:01.425292 304 : 4250, 4027
7488 11:19:01.425345 308 : 4360, 4137
7489 11:19:01.425398 312 : 4255, 4029
7490 11:19:01.425452 316 : 4250, 4027
7491 11:19:01.425506 320 : 4360, 4138
7492 11:19:01.425560 324 : 4361, 4137
7493 11:19:01.425613 328 : 4252, 4029
7494 11:19:01.425667 332 : 4250, 2669
7495 11:19:01.425720 336 : 4250, 59
7496 11:19:01.425773
7497 11:19:01.425825 MIOCK jitter meter ch=0
7498 11:19:01.425877
7499 11:19:01.425929 1T = (336-100) = 236 dly cells
7500 11:19:01.425983 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7501 11:19:01.426036 ==
7502 11:19:01.426089 Dram Type= 6, Freq= 0, CH_0, rank 0
7503 11:19:01.426142 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7504 11:19:01.426195 ==
7505 11:19:01.426248 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7506 11:19:01.426301 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7507 11:19:01.426354 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7508 11:19:01.426407 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7509 11:19:01.426460 [CA 0] Center 44 (14~75) winsize 62
7510 11:19:01.426514 [CA 1] Center 44 (13~75) winsize 63
7511 11:19:01.426567 [CA 2] Center 40 (11~69) winsize 59
7512 11:19:01.426620 [CA 3] Center 39 (10~69) winsize 60
7513 11:19:01.426672 [CA 4] Center 38 (8~68) winsize 61
7514 11:19:01.426725 [CA 5] Center 37 (7~67) winsize 61
7515 11:19:01.426777
7516 11:19:01.426830 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7517 11:19:01.426882
7518 11:19:01.426935 [CATrainingPosCal] consider 1 rank data
7519 11:19:01.426988 u2DelayCellTimex100 = 275/100 ps
7520 11:19:01.427224 CA0 delay=44 (14~75),Diff = 7 PI (24 cell)
7521 11:19:01.427285 CA1 delay=44 (13~75),Diff = 7 PI (24 cell)
7522 11:19:01.427339 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7523 11:19:01.427402 CA3 delay=39 (10~69),Diff = 2 PI (7 cell)
7524 11:19:01.427455 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
7525 11:19:01.427509 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7526 11:19:01.427561
7527 11:19:01.427614 CA PerBit enable=1, Macro0, CA PI delay=37
7528 11:19:01.427667
7529 11:19:01.427720 [CBTSetCACLKResult] CA Dly = 37
7530 11:19:01.427786 CS Dly: 10 (0~41)
7531 11:19:01.427867 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7532 11:19:01.427919 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7533 11:19:01.427970 ==
7534 11:19:01.428022 Dram Type= 6, Freq= 0, CH_0, rank 1
7535 11:19:01.428074 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7536 11:19:01.428126 ==
7537 11:19:01.428178 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7538 11:19:01.428230 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7539 11:19:01.428282 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7540 11:19:01.428333 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7541 11:19:01.428385 [CA 0] Center 43 (13~74) winsize 62
7542 11:19:01.428436 [CA 1] Center 43 (13~74) winsize 62
7543 11:19:01.428487 [CA 2] Center 39 (10~69) winsize 60
7544 11:19:01.428539 [CA 3] Center 38 (9~68) winsize 60
7545 11:19:01.428591 [CA 4] Center 37 (7~67) winsize 61
7546 11:19:01.428642 [CA 5] Center 37 (7~67) winsize 61
7547 11:19:01.428694
7548 11:19:01.428745 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7549 11:19:01.428796
7550 11:19:01.428848 [CATrainingPosCal] consider 2 rank data
7551 11:19:01.428900 u2DelayCellTimex100 = 275/100 ps
7552 11:19:01.428952 CA0 delay=44 (14~74),Diff = 7 PI (24 cell)
7553 11:19:01.429004 CA1 delay=43 (13~74),Diff = 6 PI (21 cell)
7554 11:19:01.429055 CA2 delay=40 (11~69),Diff = 3 PI (10 cell)
7555 11:19:01.429107 CA3 delay=39 (10~68),Diff = 2 PI (7 cell)
7556 11:19:01.429159 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
7557 11:19:01.429210 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
7558 11:19:01.429261
7559 11:19:01.429312 CA PerBit enable=1, Macro0, CA PI delay=37
7560 11:19:01.429363
7561 11:19:01.429414 [CBTSetCACLKResult] CA Dly = 37
7562 11:19:01.429465 CS Dly: 11 (0~44)
7563 11:19:01.429517 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7564 11:19:01.429569 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7565 11:19:01.429621
7566 11:19:01.429671 ----->DramcWriteLeveling(PI) begin...
7567 11:19:01.429724 ==
7568 11:19:01.429776 Dram Type= 6, Freq= 0, CH_0, rank 0
7569 11:19:01.429828 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7570 11:19:01.429880 ==
7571 11:19:01.429932 Write leveling (Byte 0): 33 => 33
7572 11:19:01.429983 Write leveling (Byte 1): 28 => 28
7573 11:19:01.430035 DramcWriteLeveling(PI) end<-----
7574 11:19:01.430086
7575 11:19:01.430137 ==
7576 11:19:01.430188 Dram Type= 6, Freq= 0, CH_0, rank 0
7577 11:19:01.430239 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7578 11:19:01.430291 ==
7579 11:19:01.430342 [Gating] SW mode calibration
7580 11:19:01.430394 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7581 11:19:01.430446 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7582 11:19:01.430498 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7583 11:19:01.430549 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7584 11:19:01.430601 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7585 11:19:01.430653 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7586 11:19:01.430705 1 4 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7587 11:19:01.430757 1 4 20 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
7588 11:19:01.430809 1 4 24 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
7589 11:19:01.430861 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7590 11:19:01.430913 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7591 11:19:01.430965 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7592 11:19:01.431016 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7593 11:19:01.431068 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7594 11:19:01.431119 1 5 16 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
7595 11:19:01.431171 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7596 11:19:01.431223 1 5 24 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
7597 11:19:01.431275 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7598 11:19:01.431326 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7599 11:19:01.431415 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7600 11:19:01.431467 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7601 11:19:01.431519 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7602 11:19:01.431570 1 6 16 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
7603 11:19:01.431622 1 6 20 | B1->B0 | 2a2a 4646 | 0 0 | (0 0) (0 0)
7604 11:19:01.431673 1 6 24 | B1->B0 | 3939 4646 | 1 0 | (0 0) (0 0)
7605 11:19:01.431725 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7606 11:19:01.431777 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7607 11:19:01.431828 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7608 11:19:01.431879 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7609 11:19:01.431931 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7610 11:19:01.431983 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7611 11:19:01.432035 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7612 11:19:01.432086 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7613 11:19:01.432137 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7614 11:19:01.432189 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7615 11:19:01.432242 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7616 11:19:01.432293 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7617 11:19:01.432345 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7618 11:19:01.432396 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7619 11:19:01.432448 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7620 11:19:01.432499 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7621 11:19:01.432732 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7622 11:19:01.432792 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7623 11:19:01.432845 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7624 11:19:01.432898 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7625 11:19:01.432949 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7626 11:19:01.433001 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7627 11:19:01.433053 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
7628 11:19:01.433105 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7629 11:19:01.433158 Total UI for P1: 0, mck2ui 16
7630 11:19:01.433210 best dqsien dly found for B0: ( 1, 9, 18)
7631 11:19:01.433262 Total UI for P1: 0, mck2ui 16
7632 11:19:01.433314 best dqsien dly found for B1: ( 1, 9, 20)
7633 11:19:01.433366 best DQS0 dly(MCK, UI, PI) = (1, 9, 18)
7634 11:19:01.433418 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7635 11:19:01.433470
7636 11:19:01.433521 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 18)
7637 11:19:01.433573 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7638 11:19:01.433625 [Gating] SW calibration Done
7639 11:19:01.433676 ==
7640 11:19:01.433728 Dram Type= 6, Freq= 0, CH_0, rank 0
7641 11:19:01.433779 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7642 11:19:01.433831 ==
7643 11:19:01.433883 RX Vref Scan: 0
7644 11:19:01.433934
7645 11:19:01.433985 RX Vref 0 -> 0, step: 1
7646 11:19:01.434037
7647 11:19:01.434088 RX Delay 0 -> 252, step: 8
7648 11:19:01.434139 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7649 11:19:01.434191 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
7650 11:19:01.434242 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
7651 11:19:01.434294 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
7652 11:19:01.434346 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7653 11:19:01.434398 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7654 11:19:01.434449 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
7655 11:19:01.434501 iDelay=200, Bit 7, Center 139 (88 ~ 191) 104
7656 11:19:01.434552 iDelay=200, Bit 8, Center 111 (56 ~ 167) 112
7657 11:19:01.434603 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
7658 11:19:01.434655 iDelay=200, Bit 10, Center 119 (64 ~ 175) 112
7659 11:19:01.434707 iDelay=200, Bit 11, Center 115 (64 ~ 167) 104
7660 11:19:01.434759 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
7661 11:19:01.434811 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7662 11:19:01.434862 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7663 11:19:01.434914 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7664 11:19:01.434966 ==
7665 11:19:01.435017 Dram Type= 6, Freq= 0, CH_0, rank 0
7666 11:19:01.435069 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7667 11:19:01.435121 ==
7668 11:19:01.435172 DQS Delay:
7669 11:19:01.435223 DQS0 = 0, DQS1 = 0
7670 11:19:01.435275 DQM Delay:
7671 11:19:01.435326 DQM0 = 131, DQM1 = 123
7672 11:19:01.435423 DQ Delay:
7673 11:19:01.435476 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =127
7674 11:19:01.435527 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7675 11:19:01.435579 DQ8 =111, DQ9 =111, DQ10 =119, DQ11 =115
7676 11:19:01.435631 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =135
7677 11:19:01.435683
7678 11:19:01.435734
7679 11:19:01.435785 ==
7680 11:19:01.435836 Dram Type= 6, Freq= 0, CH_0, rank 0
7681 11:19:01.435888 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7682 11:19:01.435940 ==
7683 11:19:01.435991
7684 11:19:01.436042
7685 11:19:01.436093 TX Vref Scan disable
7686 11:19:01.436144 == TX Byte 0 ==
7687 11:19:01.436195 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7688 11:19:01.436247 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7689 11:19:01.436299 == TX Byte 1 ==
7690 11:19:01.436351 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
7691 11:19:01.436402 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7692 11:19:01.436454 ==
7693 11:19:01.436505 Dram Type= 6, Freq= 0, CH_0, rank 0
7694 11:19:01.436556 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7695 11:19:01.436608 ==
7696 11:19:01.436659
7697 11:19:01.436711 TX Vref early break, caculate TX vref
7698 11:19:01.436762 TX Vref=16, minBit 4, minWin=21, winSum=359
7699 11:19:01.436815 TX Vref=18, minBit 1, minWin=22, winSum=374
7700 11:19:01.436866 TX Vref=20, minBit 8, minWin=23, winSum=383
7701 11:19:01.436919 TX Vref=22, minBit 0, minWin=24, winSum=392
7702 11:19:01.436971 TX Vref=24, minBit 0, minWin=24, winSum=404
7703 11:19:01.437023 TX Vref=26, minBit 0, minWin=25, winSum=413
7704 11:19:01.437075 TX Vref=28, minBit 4, minWin=24, winSum=417
7705 11:19:01.437126 TX Vref=30, minBit 0, minWin=25, winSum=419
7706 11:19:01.437178 TX Vref=32, minBit 4, minWin=24, winSum=409
7707 11:19:01.437230 TX Vref=34, minBit 0, minWin=24, winSum=401
7708 11:19:01.437281 TX Vref=36, minBit 0, minWin=23, winSum=393
7709 11:19:01.437333 [TxChooseVref] Worse bit 0, Min win 25, Win sum 419, Final Vref 30
7710 11:19:01.437385
7711 11:19:01.437436 Final TX Range 0 Vref 30
7712 11:19:01.437488
7713 11:19:01.437539 ==
7714 11:19:01.437590 Dram Type= 6, Freq= 0, CH_0, rank 0
7715 11:19:01.437642 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7716 11:19:01.437694 ==
7717 11:19:01.437745
7718 11:19:01.437796
7719 11:19:01.437847 TX Vref Scan disable
7720 11:19:01.437898 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7721 11:19:01.437949 == TX Byte 0 ==
7722 11:19:01.438001 u2DelayCellOfst[0]=14 cells (4 PI)
7723 11:19:01.438052 u2DelayCellOfst[1]=21 cells (6 PI)
7724 11:19:01.438104 u2DelayCellOfst[2]=14 cells (4 PI)
7725 11:19:01.438155 u2DelayCellOfst[3]=17 cells (5 PI)
7726 11:19:01.438207 u2DelayCellOfst[4]=10 cells (3 PI)
7727 11:19:01.438258 u2DelayCellOfst[5]=0 cells (0 PI)
7728 11:19:01.438310 u2DelayCellOfst[6]=21 cells (6 PI)
7729 11:19:01.438361 u2DelayCellOfst[7]=21 cells (6 PI)
7730 11:19:01.438413 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7731 11:19:01.438465 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7732 11:19:01.438518 == TX Byte 1 ==
7733 11:19:01.438569 u2DelayCellOfst[8]=0 cells (0 PI)
7734 11:19:01.438621 u2DelayCellOfst[9]=0 cells (0 PI)
7735 11:19:01.438673 u2DelayCellOfst[10]=7 cells (2 PI)
7736 11:19:01.438724 u2DelayCellOfst[11]=0 cells (0 PI)
7737 11:19:01.438776 u2DelayCellOfst[12]=14 cells (4 PI)
7738 11:19:01.438827 u2DelayCellOfst[13]=14 cells (4 PI)
7739 11:19:01.438879 u2DelayCellOfst[14]=17 cells (5 PI)
7740 11:19:01.438931 u2DelayCellOfst[15]=14 cells (4 PI)
7741 11:19:01.438983 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7742 11:19:01.439034 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
7743 11:19:01.439086 DramC Write-DBI on
7744 11:19:01.439137 ==
7745 11:19:01.439375 Dram Type= 6, Freq= 0, CH_0, rank 0
7746 11:19:01.439473 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7747 11:19:01.439526 ==
7748 11:19:01.439578
7749 11:19:01.439629
7750 11:19:01.439680 TX Vref Scan disable
7751 11:19:01.439732 == TX Byte 0 ==
7752 11:19:01.439783 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
7753 11:19:01.439835 == TX Byte 1 ==
7754 11:19:01.439886 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7755 11:19:01.439938 DramC Write-DBI off
7756 11:19:01.439989
7757 11:19:01.440040 [DATLAT]
7758 11:19:01.440091 Freq=1600, CH0 RK0
7759 11:19:01.440143
7760 11:19:01.440194 DATLAT Default: 0xf
7761 11:19:01.440245 0, 0xFFFF, sum = 0
7762 11:19:01.440298 1, 0xFFFF, sum = 0
7763 11:19:01.440350 2, 0xFFFF, sum = 0
7764 11:19:01.440402 3, 0xFFFF, sum = 0
7765 11:19:01.440454 4, 0xFFFF, sum = 0
7766 11:19:01.440506 5, 0xFFFF, sum = 0
7767 11:19:01.440558 6, 0xFFFF, sum = 0
7768 11:19:01.440610 7, 0xFFFF, sum = 0
7769 11:19:01.440662 8, 0xFFFF, sum = 0
7770 11:19:01.440714 9, 0xFFFF, sum = 0
7771 11:19:01.440767 10, 0xFFFF, sum = 0
7772 11:19:01.440819 11, 0xFFFF, sum = 0
7773 11:19:01.440871 12, 0xFFFF, sum = 0
7774 11:19:01.440923 13, 0xFFFF, sum = 0
7775 11:19:01.440975 14, 0x0, sum = 1
7776 11:19:01.441027 15, 0x0, sum = 2
7777 11:19:01.441079 16, 0x0, sum = 3
7778 11:19:01.441131 17, 0x0, sum = 4
7779 11:19:01.441183 best_step = 15
7780 11:19:01.441235
7781 11:19:01.441285 ==
7782 11:19:01.441337 Dram Type= 6, Freq= 0, CH_0, rank 0
7783 11:19:01.441389 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7784 11:19:01.441441 ==
7785 11:19:01.441493 RX Vref Scan: 1
7786 11:19:01.441544
7787 11:19:01.441595 Set Vref Range= 24 -> 127
7788 11:19:01.441646
7789 11:19:01.441697 RX Vref 24 -> 127, step: 1
7790 11:19:01.441748
7791 11:19:01.441800 RX Delay 11 -> 252, step: 4
7792 11:19:01.441851
7793 11:19:01.441902 Set Vref, RX VrefLevel [Byte0]: 24
7794 11:19:01.441953 [Byte1]: 24
7795 11:19:01.442005
7796 11:19:01.442056 Set Vref, RX VrefLevel [Byte0]: 25
7797 11:19:01.442108 [Byte1]: 25
7798 11:19:01.442160
7799 11:19:01.442211 Set Vref, RX VrefLevel [Byte0]: 26
7800 11:19:01.442263 [Byte1]: 26
7801 11:19:01.442314
7802 11:19:01.442366 Set Vref, RX VrefLevel [Byte0]: 27
7803 11:19:01.442417 [Byte1]: 27
7804 11:19:01.442468
7805 11:19:01.442519 Set Vref, RX VrefLevel [Byte0]: 28
7806 11:19:01.442570 [Byte1]: 28
7807 11:19:01.442621
7808 11:19:01.442672 Set Vref, RX VrefLevel [Byte0]: 29
7809 11:19:01.442724 [Byte1]: 29
7810 11:19:01.442775
7811 11:19:01.442826 Set Vref, RX VrefLevel [Byte0]: 30
7812 11:19:01.442877 [Byte1]: 30
7813 11:19:01.442929
7814 11:19:01.442980 Set Vref, RX VrefLevel [Byte0]: 31
7815 11:19:01.443031 [Byte1]: 31
7816 11:19:01.443083
7817 11:19:01.443134 Set Vref, RX VrefLevel [Byte0]: 32
7818 11:19:01.443186 [Byte1]: 32
7819 11:19:01.443238
7820 11:19:01.443288 Set Vref, RX VrefLevel [Byte0]: 33
7821 11:19:01.443340 [Byte1]: 33
7822 11:19:01.443435
7823 11:19:01.443486 Set Vref, RX VrefLevel [Byte0]: 34
7824 11:19:01.443538 [Byte1]: 34
7825 11:19:01.443589
7826 11:19:01.443641 Set Vref, RX VrefLevel [Byte0]: 35
7827 11:19:01.443693 [Byte1]: 35
7828 11:19:01.443745
7829 11:19:01.443796 Set Vref, RX VrefLevel [Byte0]: 36
7830 11:19:01.443848 [Byte1]: 36
7831 11:19:01.443899
7832 11:19:01.443950 Set Vref, RX VrefLevel [Byte0]: 37
7833 11:19:01.444001 [Byte1]: 37
7834 11:19:01.444053
7835 11:19:01.444104 Set Vref, RX VrefLevel [Byte0]: 38
7836 11:19:01.444156 [Byte1]: 38
7837 11:19:01.444207
7838 11:19:01.444258 Set Vref, RX VrefLevel [Byte0]: 39
7839 11:19:01.444310 [Byte1]: 39
7840 11:19:01.444362
7841 11:19:01.444412 Set Vref, RX VrefLevel [Byte0]: 40
7842 11:19:01.444463 [Byte1]: 40
7843 11:19:01.444515
7844 11:19:01.444566 Set Vref, RX VrefLevel [Byte0]: 41
7845 11:19:01.444618 [Byte1]: 41
7846 11:19:01.444669
7847 11:19:01.444720 Set Vref, RX VrefLevel [Byte0]: 42
7848 11:19:01.444771 [Byte1]: 42
7849 11:19:01.444823
7850 11:19:01.444874 Set Vref, RX VrefLevel [Byte0]: 43
7851 11:19:01.444925 [Byte1]: 43
7852 11:19:01.444976
7853 11:19:01.445027 Set Vref, RX VrefLevel [Byte0]: 44
7854 11:19:01.445078 [Byte1]: 44
7855 11:19:01.445130
7856 11:19:01.445181 Set Vref, RX VrefLevel [Byte0]: 45
7857 11:19:01.445233 [Byte1]: 45
7858 11:19:01.445284
7859 11:19:01.445335 Set Vref, RX VrefLevel [Byte0]: 46
7860 11:19:01.445387 [Byte1]: 46
7861 11:19:01.445438
7862 11:19:01.445488 Set Vref, RX VrefLevel [Byte0]: 47
7863 11:19:01.445539 [Byte1]: 47
7864 11:19:01.445591
7865 11:19:01.445642 Set Vref, RX VrefLevel [Byte0]: 48
7866 11:19:01.445693 [Byte1]: 48
7867 11:19:01.445744
7868 11:19:01.445795 Set Vref, RX VrefLevel [Byte0]: 49
7869 11:19:01.445848 [Byte1]: 49
7870 11:19:01.445900
7871 11:19:01.445951 Set Vref, RX VrefLevel [Byte0]: 50
7872 11:19:01.446002 [Byte1]: 50
7873 11:19:01.446054
7874 11:19:01.446105 Set Vref, RX VrefLevel [Byte0]: 51
7875 11:19:01.446156 [Byte1]: 51
7876 11:19:01.446208
7877 11:19:01.446259 Set Vref, RX VrefLevel [Byte0]: 52
7878 11:19:01.446310 [Byte1]: 52
7879 11:19:01.446362
7880 11:19:01.446412 Set Vref, RX VrefLevel [Byte0]: 53
7881 11:19:01.446464 [Byte1]: 53
7882 11:19:01.446515
7883 11:19:01.446567 Set Vref, RX VrefLevel [Byte0]: 54
7884 11:19:01.446618 [Byte1]: 54
7885 11:19:01.446669
7886 11:19:01.446720 Set Vref, RX VrefLevel [Byte0]: 55
7887 11:19:01.446772 [Byte1]: 55
7888 11:19:01.446823
7889 11:19:01.446874 Set Vref, RX VrefLevel [Byte0]: 56
7890 11:19:01.446925 [Byte1]: 56
7891 11:19:01.446977
7892 11:19:01.447028 Set Vref, RX VrefLevel [Byte0]: 57
7893 11:19:01.447079 [Byte1]: 57
7894 11:19:01.447130
7895 11:19:01.447181 Set Vref, RX VrefLevel [Byte0]: 58
7896 11:19:01.447255 [Byte1]: 58
7897 11:19:01.447307
7898 11:19:01.447392 Set Vref, RX VrefLevel [Byte0]: 59
7899 11:19:01.447447 [Byte1]: 59
7900 11:19:01.447499
7901 11:19:01.447550 Set Vref, RX VrefLevel [Byte0]: 60
7902 11:19:01.447601 [Byte1]: 60
7903 11:19:01.447653
7904 11:19:01.447704 Set Vref, RX VrefLevel [Byte0]: 61
7905 11:19:01.447756 [Byte1]: 61
7906 11:19:01.447808
7907 11:19:01.447859 Set Vref, RX VrefLevel [Byte0]: 62
7908 11:19:01.447911 [Byte1]: 62
7909 11:19:01.447962
7910 11:19:01.448013 Set Vref, RX VrefLevel [Byte0]: 63
7911 11:19:01.448066 [Byte1]: 63
7912 11:19:01.448118
7913 11:19:01.448169 Set Vref, RX VrefLevel [Byte0]: 64
7914 11:19:01.448220 [Byte1]: 64
7915 11:19:01.448271
7916 11:19:01.448322 Set Vref, RX VrefLevel [Byte0]: 65
7917 11:19:01.448374 [Byte1]: 65
7918 11:19:01.448425
7919 11:19:01.448661 Set Vref, RX VrefLevel [Byte0]: 66
7920 11:19:01.448724 [Byte1]: 66
7921 11:19:01.448776
7922 11:19:01.448827 Set Vref, RX VrefLevel [Byte0]: 67
7923 11:19:01.448879 [Byte1]: 67
7924 11:19:01.448931
7925 11:19:01.448983 Set Vref, RX VrefLevel [Byte0]: 68
7926 11:19:01.449050 [Byte1]: 68
7927 11:19:01.449116
7928 11:19:01.449167 Set Vref, RX VrefLevel [Byte0]: 69
7929 11:19:01.449218 [Byte1]: 69
7930 11:19:01.449286
7931 11:19:01.449350 Set Vref, RX VrefLevel [Byte0]: 70
7932 11:19:01.449401 [Byte1]: 70
7933 11:19:01.449453
7934 11:19:01.449504 Set Vref, RX VrefLevel [Byte0]: 71
7935 11:19:01.449555 [Byte1]: 71
7936 11:19:01.449606
7937 11:19:01.449658 Set Vref, RX VrefLevel [Byte0]: 72
7938 11:19:01.449710 [Byte1]: 72
7939 11:19:01.449761
7940 11:19:01.449812 Set Vref, RX VrefLevel [Byte0]: 73
7941 11:19:01.449864 [Byte1]: 73
7942 11:19:01.449915
7943 11:19:01.449966 Set Vref, RX VrefLevel [Byte0]: 74
7944 11:19:01.450017 [Byte1]: 74
7945 11:19:01.450068
7946 11:19:01.450119 Set Vref, RX VrefLevel [Byte0]: 75
7947 11:19:01.450171 [Byte1]: 75
7948 11:19:01.450221
7949 11:19:01.450272 Set Vref, RX VrefLevel [Byte0]: 76
7950 11:19:01.450323 [Byte1]: 76
7951 11:19:01.450375
7952 11:19:01.450425 Final RX Vref Byte 0 = 57 to rank0
7953 11:19:02.327876 Final RX Vref Byte 1 = 61 to rank0
7954 11:19:02.328355 Final RX Vref Byte 0 = 57 to rank1
7955 11:19:02.328681 Final RX Vref Byte 1 = 61 to rank1==
7956 11:19:02.328984 Dram Type= 6, Freq= 0, CH_0, rank 0
7957 11:19:02.329276 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7958 11:19:02.329563 ==
7959 11:19:02.329843 DQS Delay:
7960 11:19:02.330114 DQS0 = 0, DQS1 = 0
7961 11:19:02.330386 DQM Delay:
7962 11:19:02.330654 DQM0 = 129, DQM1 = 121
7963 11:19:02.330924 DQ Delay:
7964 11:19:02.331191 DQ0 =130, DQ1 =132, DQ2 =126, DQ3 =126
7965 11:19:02.331500 DQ4 =132, DQ5 =118, DQ6 =136, DQ7 =138
7966 11:19:02.331778 DQ8 =110, DQ9 =110, DQ10 =122, DQ11 =116
7967 11:19:02.332048 DQ12 =126, DQ13 =126, DQ14 =132, DQ15 =132
7968 11:19:02.332317
7969 11:19:02.332584
7970 11:19:02.332851
7971 11:19:02.333115 [DramC_TX_OE_Calibration] TA2
7972 11:19:02.333384 Original DQ_B0 (3 6) =30, OEN = 27
7973 11:19:02.333654 Original DQ_B1 (3 6) =30, OEN = 27
7974 11:19:02.333924 24, 0x0, End_B0=24 End_B1=24
7975 11:19:02.334198 25, 0x0, End_B0=25 End_B1=25
7976 11:19:02.334473 26, 0x0, End_B0=26 End_B1=26
7977 11:19:02.334743 27, 0x0, End_B0=27 End_B1=27
7978 11:19:02.335016 28, 0x0, End_B0=28 End_B1=28
7979 11:19:02.335286 29, 0x0, End_B0=29 End_B1=29
7980 11:19:02.335593 30, 0x0, End_B0=30 End_B1=30
7981 11:19:02.335868 31, 0x4141, End_B0=30 End_B1=30
7982 11:19:02.336141 Byte0 end_step=30 best_step=27
7983 11:19:02.336408 Byte1 end_step=30 best_step=27
7984 11:19:02.336675 Byte0 TX OE(2T, 0.5T) = (3, 3)
7985 11:19:02.336944 Byte1 TX OE(2T, 0.5T) = (3, 3)
7986 11:19:02.337212
7987 11:19:02.337477
7988 11:19:02.337744 [DQSOSCAuto] RK0, (LSB)MR18= 0x1306, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 400 ps
7989 11:19:02.338018 CH0 RK0: MR19=303, MR18=1306
7990 11:19:02.338287 CH0_RK0: MR19=0x303, MR18=0x1306, DQSOSC=400, MR23=63, INC=23, DEC=15
7991 11:19:02.338557
7992 11:19:02.338821 ----->DramcWriteLeveling(PI) begin...
7993 11:19:02.339093 ==
7994 11:19:02.339392 Dram Type= 6, Freq= 0, CH_0, rank 1
7995 11:19:02.339673 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7996 11:19:02.339944 ==
7997 11:19:02.340277 Write leveling (Byte 0): 35 => 35
7998 11:19:02.340556 Write leveling (Byte 1): 27 => 27
7999 11:19:02.340824 DramcWriteLeveling(PI) end<-----
8000 11:19:02.341093
8001 11:19:02.341356 ==
8002 11:19:02.341623 Dram Type= 6, Freq= 0, CH_0, rank 1
8003 11:19:02.341894 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8004 11:19:02.342166 ==
8005 11:19:02.342433 [Gating] SW mode calibration
8006 11:19:02.342701 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8007 11:19:02.342975 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8008 11:19:02.343247 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8009 11:19:02.343556 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8010 11:19:02.343829 1 4 8 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
8011 11:19:02.344100 1 4 12 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
8012 11:19:02.344368 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
8013 11:19:02.344638 1 4 20 | B1->B0 | 2d2d 3434 | 1 1 | (1 1) (1 1)
8014 11:19:02.344905 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8015 11:19:02.345173 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8016 11:19:02.345444 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8017 11:19:02.345713 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8018 11:19:02.345981 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
8019 11:19:02.346251 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 1)
8020 11:19:02.346520 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8021 11:19:02.346792 1 5 20 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
8022 11:19:02.346984 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8023 11:19:02.347177 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8024 11:19:02.347401 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8025 11:19:02.347613 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8026 11:19:02.347807 1 6 8 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8027 11:19:02.348001 1 6 12 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
8028 11:19:02.348194 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8029 11:19:02.348386 1 6 20 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
8030 11:19:02.348577 1 6 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8031 11:19:02.348769 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8032 11:19:02.348961 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8033 11:19:02.349154 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8034 11:19:02.349345 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8035 11:19:02.349538 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8036 11:19:02.349729 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8037 11:19:02.349923 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8038 11:19:02.350114 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8039 11:19:02.350594 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8040 11:19:02.350821 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8041 11:19:02.351017 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8042 11:19:02.351211 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8043 11:19:02.351461 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8044 11:19:02.351663 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8045 11:19:02.351838 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8046 11:19:02.351985 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8047 11:19:02.352132 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8048 11:19:02.352277 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8049 11:19:02.352420 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8050 11:19:02.352565 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8051 11:19:02.352711 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8052 11:19:02.352856 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8053 11:19:02.353000 Total UI for P1: 0, mck2ui 16
8054 11:19:02.353146 best dqsien dly found for B0: ( 1, 9, 10)
8055 11:19:02.353293 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8056 11:19:02.353439 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8057 11:19:02.353584 Total UI for P1: 0, mck2ui 16
8058 11:19:02.353730 best dqsien dly found for B1: ( 1, 9, 18)
8059 11:19:02.353875 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8060 11:19:02.354019 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8061 11:19:02.354171
8062 11:19:02.354332 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8063 11:19:02.354479 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8064 11:19:02.354624 [Gating] SW calibration Done
8065 11:19:02.354769 ==
8066 11:19:02.354911 Dram Type= 6, Freq= 0, CH_0, rank 1
8067 11:19:02.355056 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8068 11:19:02.355201 ==
8069 11:19:02.355346 RX Vref Scan: 0
8070 11:19:02.355522
8071 11:19:02.355666 RX Vref 0 -> 0, step: 1
8072 11:19:02.355809
8073 11:19:02.355952 RX Delay 0 -> 252, step: 8
8074 11:19:02.356097 iDelay=200, Bit 0, Center 131 (72 ~ 191) 120
8075 11:19:02.356257 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8076 11:19:02.356404 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8077 11:19:02.356555 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8078 11:19:02.356705 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8079 11:19:02.356844 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8080 11:19:02.356963 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8081 11:19:02.357082 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8082 11:19:02.357202 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8083 11:19:02.357321 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8084 11:19:02.357440 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8085 11:19:02.357560 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8086 11:19:02.357679 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8087 11:19:02.357799 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8088 11:19:02.357917 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8089 11:19:02.358038 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8090 11:19:02.358164 ==
8091 11:19:02.358284 Dram Type= 6, Freq= 0, CH_0, rank 1
8092 11:19:02.358403 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8093 11:19:02.358523 ==
8094 11:19:02.358642 DQS Delay:
8095 11:19:02.358761 DQS0 = 0, DQS1 = 0
8096 11:19:02.358879 DQM Delay:
8097 11:19:02.358999 DQM0 = 131, DQM1 = 124
8098 11:19:02.359118 DQ Delay:
8099 11:19:02.359238 DQ0 =131, DQ1 =131, DQ2 =127, DQ3 =131
8100 11:19:02.359366 DQ4 =131, DQ5 =119, DQ6 =139, DQ7 =139
8101 11:19:02.359488 DQ8 =115, DQ9 =115, DQ10 =123, DQ11 =115
8102 11:19:02.359609 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8103 11:19:02.359730
8104 11:19:02.359848
8105 11:19:02.359966 ==
8106 11:19:02.360085 Dram Type= 6, Freq= 0, CH_0, rank 1
8107 11:19:02.360257 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8108 11:19:02.360438 ==
8109 11:19:02.360564
8110 11:19:02.360685
8111 11:19:02.360804 TX Vref Scan disable
8112 11:19:02.360924 == TX Byte 0 ==
8113 11:19:02.361043 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8114 11:19:02.361165 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8115 11:19:02.361284 == TX Byte 1 ==
8116 11:19:02.361405 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8117 11:19:02.361526 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8118 11:19:02.361648 ==
8119 11:19:02.361778 Dram Type= 6, Freq= 0, CH_0, rank 1
8120 11:19:02.361878 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8121 11:19:02.361979 ==
8122 11:19:02.362079
8123 11:19:02.362181 TX Vref early break, caculate TX vref
8124 11:19:02.362281 TX Vref=16, minBit 9, minWin=22, winSum=376
8125 11:19:02.362381 TX Vref=18, minBit 9, minWin=23, winSum=388
8126 11:19:02.362482 TX Vref=20, minBit 9, minWin=23, winSum=393
8127 11:19:02.362582 TX Vref=22, minBit 9, minWin=23, winSum=401
8128 11:19:02.362682 TX Vref=24, minBit 9, minWin=24, winSum=410
8129 11:19:02.362783 TX Vref=26, minBit 0, minWin=26, winSum=422
8130 11:19:02.362884 TX Vref=28, minBit 2, minWin=26, winSum=423
8131 11:19:02.362984 TX Vref=30, minBit 4, minWin=25, winSum=422
8132 11:19:02.363085 TX Vref=32, minBit 2, minWin=25, winSum=419
8133 11:19:02.363186 TX Vref=34, minBit 8, minWin=24, winSum=408
8134 11:19:02.363358 TX Vref=36, minBit 4, minWin=24, winSum=399
8135 11:19:02.363476 [TxChooseVref] Worse bit 2, Min win 26, Win sum 423, Final Vref 28
8136 11:19:02.363579
8137 11:19:02.363679 Final TX Range 0 Vref 28
8138 11:19:02.363779
8139 11:19:02.363877 ==
8140 11:19:02.363977 Dram Type= 6, Freq= 0, CH_0, rank 1
8141 11:19:02.364077 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8142 11:19:02.364178 ==
8143 11:19:02.364277
8144 11:19:02.364376
8145 11:19:02.364474 TX Vref Scan disable
8146 11:19:02.364574 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8147 11:19:02.364675 == TX Byte 0 ==
8148 11:19:02.364773 u2DelayCellOfst[0]=14 cells (4 PI)
8149 11:19:02.364873 u2DelayCellOfst[1]=21 cells (6 PI)
8150 11:19:02.364972 u2DelayCellOfst[2]=10 cells (3 PI)
8151 11:19:02.365071 u2DelayCellOfst[3]=14 cells (4 PI)
8152 11:19:02.365170 u2DelayCellOfst[4]=10 cells (3 PI)
8153 11:19:02.365270 u2DelayCellOfst[5]=0 cells (0 PI)
8154 11:19:02.365369 u2DelayCellOfst[6]=17 cells (5 PI)
8155 11:19:02.365468 u2DelayCellOfst[7]=17 cells (5 PI)
8156 11:19:02.365567 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8157 11:19:02.365669 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8158 11:19:02.365769 == TX Byte 1 ==
8159 11:19:02.366079 u2DelayCellOfst[8]=0 cells (0 PI)
8160 11:19:02.366193 u2DelayCellOfst[9]=0 cells (0 PI)
8161 11:19:02.366297 u2DelayCellOfst[10]=7 cells (2 PI)
8162 11:19:02.366397 u2DelayCellOfst[11]=0 cells (0 PI)
8163 11:19:02.366498 u2DelayCellOfst[12]=14 cells (4 PI)
8164 11:19:02.366598 u2DelayCellOfst[13]=10 cells (3 PI)
8165 11:19:02.366697 u2DelayCellOfst[14]=14 cells (4 PI)
8166 11:19:02.366803 u2DelayCellOfst[15]=10 cells (3 PI)
8167 11:19:02.366905 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8168 11:19:02.366993 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8169 11:19:02.367080 DramC Write-DBI on
8170 11:19:02.367165 ==
8171 11:19:02.367251 Dram Type= 6, Freq= 0, CH_0, rank 1
8172 11:19:02.367337 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8173 11:19:02.367444 ==
8174 11:19:02.367532
8175 11:19:02.367617
8176 11:19:02.367702 TX Vref Scan disable
8177 11:19:02.367788 == TX Byte 0 ==
8178 11:19:02.367872 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
8179 11:19:02.367958 == TX Byte 1 ==
8180 11:19:02.368044 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8181 11:19:02.368129 DramC Write-DBI off
8182 11:19:02.368215
8183 11:19:02.368301 [DATLAT]
8184 11:19:02.368387 Freq=1600, CH0 RK1
8185 11:19:02.368472
8186 11:19:02.368558 DATLAT Default: 0xf
8187 11:19:02.368644 0, 0xFFFF, sum = 0
8188 11:19:02.368731 1, 0xFFFF, sum = 0
8189 11:19:02.368818 2, 0xFFFF, sum = 0
8190 11:19:02.368905 3, 0xFFFF, sum = 0
8191 11:19:02.368992 4, 0xFFFF, sum = 0
8192 11:19:02.369079 5, 0xFFFF, sum = 0
8193 11:19:02.369165 6, 0xFFFF, sum = 0
8194 11:19:02.369252 7, 0xFFFF, sum = 0
8195 11:19:02.369338 8, 0xFFFF, sum = 0
8196 11:19:02.369425 9, 0xFFFF, sum = 0
8197 11:19:02.369512 10, 0xFFFF, sum = 0
8198 11:19:02.369598 11, 0xFFFF, sum = 0
8199 11:19:02.369686 12, 0xFFFF, sum = 0
8200 11:19:02.369773 13, 0xFFFF, sum = 0
8201 11:19:02.369860 14, 0x0, sum = 1
8202 11:19:02.369946 15, 0x0, sum = 2
8203 11:19:02.370033 16, 0x0, sum = 3
8204 11:19:02.370119 17, 0x0, sum = 4
8205 11:19:02.370206 best_step = 15
8206 11:19:02.370291
8207 11:19:02.370376 ==
8208 11:19:02.370461 Dram Type= 6, Freq= 0, CH_0, rank 1
8209 11:19:02.370547 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8210 11:19:02.370633 ==
8211 11:19:02.370719 RX Vref Scan: 0
8212 11:19:02.370803
8213 11:19:02.370889 RX Vref 0 -> 0, step: 1
8214 11:19:02.370974
8215 11:19:02.371059 RX Delay 11 -> 252, step: 4
8216 11:19:02.371145 iDelay=191, Bit 0, Center 128 (75 ~ 182) 108
8217 11:19:02.371232 iDelay=191, Bit 1, Center 130 (75 ~ 186) 112
8218 11:19:02.371318 iDelay=191, Bit 2, Center 124 (71 ~ 178) 108
8219 11:19:02.371426 iDelay=191, Bit 3, Center 126 (71 ~ 182) 112
8220 11:19:02.371515 iDelay=191, Bit 4, Center 126 (75 ~ 178) 104
8221 11:19:02.371601 iDelay=191, Bit 5, Center 116 (63 ~ 170) 108
8222 11:19:02.371687 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8223 11:19:02.371784 iDelay=191, Bit 7, Center 136 (83 ~ 190) 108
8224 11:19:02.371859 iDelay=191, Bit 8, Center 112 (59 ~ 166) 108
8225 11:19:02.371934 iDelay=191, Bit 9, Center 110 (55 ~ 166) 112
8226 11:19:02.372010 iDelay=191, Bit 10, Center 122 (67 ~ 178) 112
8227 11:19:02.372085 iDelay=191, Bit 11, Center 116 (63 ~ 170) 108
8228 11:19:02.372160 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8229 11:19:02.372234 iDelay=191, Bit 13, Center 126 (71 ~ 182) 112
8230 11:19:02.372310 iDelay=191, Bit 14, Center 134 (79 ~ 190) 112
8231 11:19:02.372385 iDelay=191, Bit 15, Center 130 (75 ~ 186) 112
8232 11:19:02.372460 ==
8233 11:19:02.372584 Dram Type= 6, Freq= 0, CH_0, rank 1
8234 11:19:02.372690 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8235 11:19:02.372775 ==
8236 11:19:02.372850 DQS Delay:
8237 11:19:02.372925 DQS0 = 0, DQS1 = 0
8238 11:19:02.373000 DQM Delay:
8239 11:19:02.373074 DQM0 = 127, DQM1 = 122
8240 11:19:02.373148 DQ Delay:
8241 11:19:02.373224 DQ0 =128, DQ1 =130, DQ2 =124, DQ3 =126
8242 11:19:02.373299 DQ4 =126, DQ5 =116, DQ6 =134, DQ7 =136
8243 11:19:02.373374 DQ8 =112, DQ9 =110, DQ10 =122, DQ11 =116
8244 11:19:02.373449 DQ12 =126, DQ13 =126, DQ14 =134, DQ15 =130
8245 11:19:02.373523
8246 11:19:02.373598
8247 11:19:02.373671
8248 11:19:02.373745 [DramC_TX_OE_Calibration] TA2
8249 11:19:02.373819 Original DQ_B0 (3 6) =30, OEN = 27
8250 11:19:02.373895 Original DQ_B1 (3 6) =30, OEN = 27
8251 11:19:02.373970 24, 0x0, End_B0=24 End_B1=24
8252 11:19:02.374046 25, 0x0, End_B0=25 End_B1=25
8253 11:19:02.374123 26, 0x0, End_B0=26 End_B1=26
8254 11:19:02.374199 27, 0x0, End_B0=27 End_B1=27
8255 11:19:02.374275 28, 0x0, End_B0=28 End_B1=28
8256 11:19:02.374350 29, 0x0, End_B0=29 End_B1=29
8257 11:19:02.374426 30, 0x0, End_B0=30 End_B1=30
8258 11:19:02.374502 31, 0x4141, End_B0=30 End_B1=30
8259 11:19:02.374578 Byte0 end_step=30 best_step=27
8260 11:19:02.374653 Byte1 end_step=30 best_step=27
8261 11:19:02.374728 Byte0 TX OE(2T, 0.5T) = (3, 3)
8262 11:19:02.374803 Byte1 TX OE(2T, 0.5T) = (3, 3)
8263 11:19:02.374878
8264 11:19:02.374952
8265 11:19:02.375027 [DQSOSCAuto] RK1, (LSB)MR18= 0x190d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 397 ps
8266 11:19:02.375103 CH0 RK1: MR19=303, MR18=190D
8267 11:19:02.375179 CH0_RK1: MR19=0x303, MR18=0x190D, DQSOSC=397, MR23=63, INC=23, DEC=15
8268 11:19:02.375254 [RxdqsGatingPostProcess] freq 1600
8269 11:19:02.375330 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8270 11:19:02.375425 best DQS0 dly(2T, 0.5T) = (1, 1)
8271 11:19:02.375502 best DQS1 dly(2T, 0.5T) = (1, 1)
8272 11:19:02.375577 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8273 11:19:02.375653 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8274 11:19:02.375728 best DQS0 dly(2T, 0.5T) = (1, 1)
8275 11:19:02.375803 best DQS1 dly(2T, 0.5T) = (1, 1)
8276 11:19:02.375878 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8277 11:19:02.375954 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8278 11:19:02.376029 Pre-setting of DQS Precalculation
8279 11:19:02.376104 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8280 11:19:02.376180 ==
8281 11:19:02.376256 Dram Type= 6, Freq= 0, CH_1, rank 0
8282 11:19:02.376331 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8283 11:19:02.376408 ==
8284 11:19:02.376482 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8285 11:19:02.376558 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8286 11:19:02.376634 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8287 11:19:02.376710 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8288 11:19:02.376790 [CA 0] Center 43 (14~72) winsize 59
8289 11:19:02.376857 [CA 1] Center 43 (14~72) winsize 59
8290 11:19:02.376924 [CA 2] Center 39 (11~67) winsize 57
8291 11:19:02.376990 [CA 3] Center 37 (8~66) winsize 59
8292 11:19:02.377055 [CA 4] Center 38 (9~68) winsize 60
8293 11:19:02.377122 [CA 5] Center 37 (9~66) winsize 58
8294 11:19:02.377186
8295 11:19:02.377251 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8296 11:19:02.377315
8297 11:19:02.377572 [CATrainingPosCal] consider 1 rank data
8298 11:19:02.377648 u2DelayCellTimex100 = 275/100 ps
8299 11:19:02.377715 CA0 delay=43 (14~72),Diff = 6 PI (21 cell)
8300 11:19:02.377780 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8301 11:19:02.377844 CA2 delay=39 (11~67),Diff = 2 PI (7 cell)
8302 11:19:02.377908 CA3 delay=37 (8~66),Diff = 0 PI (0 cell)
8303 11:19:02.377973 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8304 11:19:02.378037 CA5 delay=37 (9~66),Diff = 0 PI (0 cell)
8305 11:19:02.378102
8306 11:19:02.378167 CA PerBit enable=1, Macro0, CA PI delay=37
8307 11:19:02.378232
8308 11:19:02.378295 [CBTSetCACLKResult] CA Dly = 37
8309 11:19:02.378360 CS Dly: 9 (0~40)
8310 11:19:02.378425 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8311 11:19:02.378491 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8312 11:19:02.378555 ==
8313 11:19:02.378619 Dram Type= 6, Freq= 0, CH_1, rank 1
8314 11:19:02.378684 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8315 11:19:02.378749 ==
8316 11:19:02.378814 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8317 11:19:02.378878 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8318 11:19:02.378943 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8319 11:19:02.379008 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8320 11:19:02.379073 [CA 0] Center 43 (14~73) winsize 60
8321 11:19:02.379138 [CA 1] Center 43 (14~72) winsize 59
8322 11:19:02.379202 [CA 2] Center 38 (9~67) winsize 59
8323 11:19:02.379266 [CA 3] Center 37 (9~66) winsize 58
8324 11:19:02.379331 [CA 4] Center 38 (9~68) winsize 60
8325 11:19:02.379405 [CA 5] Center 36 (7~66) winsize 60
8326 11:19:02.379470
8327 11:19:02.379534 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8328 11:19:02.379598
8329 11:19:02.379662 [CATrainingPosCal] consider 2 rank data
8330 11:19:02.379727 u2DelayCellTimex100 = 275/100 ps
8331 11:19:02.379791 CA0 delay=43 (14~72),Diff = 6 PI (21 cell)
8332 11:19:02.379855 CA1 delay=43 (14~72),Diff = 6 PI (21 cell)
8333 11:19:02.379922 CA2 delay=39 (11~67),Diff = 2 PI (7 cell)
8334 11:19:02.379987 CA3 delay=37 (9~66),Diff = 0 PI (0 cell)
8335 11:19:02.380051 CA4 delay=38 (9~68),Diff = 1 PI (3 cell)
8336 11:19:02.380115 CA5 delay=37 (9~66),Diff = 0 PI (0 cell)
8337 11:19:02.380180
8338 11:19:02.380244 CA PerBit enable=1, Macro0, CA PI delay=37
8339 11:19:02.380308
8340 11:19:02.380371 [CBTSetCACLKResult] CA Dly = 37
8341 11:19:02.380436 CS Dly: 10 (0~43)
8342 11:19:02.380500 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8343 11:19:02.380565 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8344 11:19:02.380629
8345 11:19:02.380693 ----->DramcWriteLeveling(PI) begin...
8346 11:19:02.380758 ==
8347 11:19:02.380823 Dram Type= 6, Freq= 0, CH_1, rank 0
8348 11:19:02.380888 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8349 11:19:02.380953 ==
8350 11:19:02.381017 Write leveling (Byte 0): 23 => 23
8351 11:19:02.381081 Write leveling (Byte 1): 27 => 27
8352 11:19:02.381145 DramcWriteLeveling(PI) end<-----
8353 11:19:02.381209
8354 11:19:02.381273 ==
8355 11:19:02.381336 Dram Type= 6, Freq= 0, CH_1, rank 0
8356 11:19:02.381401 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8357 11:19:02.381466 ==
8358 11:19:02.381531 [Gating] SW mode calibration
8359 11:19:02.381595 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8360 11:19:02.381661 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8361 11:19:02.381726 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8362 11:19:02.381802 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8363 11:19:02.381860 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8364 11:19:02.381919 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8365 11:19:02.381978 1 4 16 | B1->B0 | 2d2d 2727 | 0 0 | (0 0) (0 0)
8366 11:19:02.382037 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8367 11:19:02.382094 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8368 11:19:02.382153 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8369 11:19:02.382212 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8370 11:19:02.382271 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8371 11:19:02.382330 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8372 11:19:02.382388 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8373 11:19:02.382446 1 5 16 | B1->B0 | 2e2e 3434 | 1 0 | (1 0) (0 1)
8374 11:19:02.382504 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8375 11:19:02.382562 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8376 11:19:02.382621 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8377 11:19:02.382679 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8378 11:19:02.382738 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8379 11:19:02.382796 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8380 11:19:02.382854 1 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8381 11:19:02.382913 1 6 16 | B1->B0 | 4141 3333 | 0 0 | (0 0) (0 0)
8382 11:19:02.382971 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8383 11:19:02.383029 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8384 11:19:02.383087 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8385 11:19:02.383145 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8386 11:19:02.383203 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8387 11:19:02.383261 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8388 11:19:02.383318 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8389 11:19:02.383394 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8390 11:19:02.383454 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8391 11:19:02.383512 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8392 11:19:02.383570 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8393 11:19:02.383629 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8394 11:19:02.383693 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8395 11:19:02.383751 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8396 11:19:02.383809 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8397 11:19:02.383868 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8398 11:19:02.383926 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8399 11:19:02.384177 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8400 11:19:02.384248 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8401 11:19:02.384307 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8402 11:19:02.384366 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8403 11:19:02.384425 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8404 11:19:02.384485 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8405 11:19:02.384544 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8406 11:19:02.384602 Total UI for P1: 0, mck2ui 16
8407 11:19:02.384662 best dqsien dly found for B0: ( 1, 9, 14)
8408 11:19:02.384720 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8409 11:19:02.384779 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8410 11:19:02.384843 Total UI for P1: 0, mck2ui 16
8411 11:19:02.384902 best dqsien dly found for B1: ( 1, 9, 18)
8412 11:19:02.384961 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8413 11:19:02.385020 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8414 11:19:02.385078
8415 11:19:02.385137 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8416 11:19:02.385195 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8417 11:19:02.385253 [Gating] SW calibration Done
8418 11:19:02.385311 ==
8419 11:19:02.385370 Dram Type= 6, Freq= 0, CH_1, rank 0
8420 11:19:02.385428 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8421 11:19:02.385486 ==
8422 11:19:02.385544 RX Vref Scan: 0
8423 11:19:02.385603
8424 11:19:02.385660 RX Vref 0 -> 0, step: 1
8425 11:19:02.385718
8426 11:19:02.385775 RX Delay 0 -> 252, step: 8
8427 11:19:02.385834 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8428 11:19:02.385893 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8429 11:19:02.385952 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8430 11:19:02.386010 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8431 11:19:02.386069 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8432 11:19:02.386127 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8433 11:19:02.386185 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
8434 11:19:02.386243 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8435 11:19:02.386301 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8436 11:19:02.386360 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
8437 11:19:02.386418 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
8438 11:19:02.386476 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8439 11:19:02.386535 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8440 11:19:02.386593 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8441 11:19:02.386651 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8442 11:19:02.386710 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8443 11:19:02.386778 ==
8444 11:19:02.386831 Dram Type= 6, Freq= 0, CH_1, rank 0
8445 11:19:02.386883 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8446 11:19:02.386937 ==
8447 11:19:02.386990 DQS Delay:
8448 11:19:02.387042 DQS0 = 0, DQS1 = 0
8449 11:19:02.387095 DQM Delay:
8450 11:19:02.387147 DQM0 = 133, DQM1 = 127
8451 11:19:02.387200 DQ Delay:
8452 11:19:02.387252 DQ0 =139, DQ1 =127, DQ2 =119, DQ3 =135
8453 11:19:02.387305 DQ4 =135, DQ5 =143, DQ6 =143, DQ7 =127
8454 11:19:02.387369 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =123
8455 11:19:02.387425 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8456 11:19:02.387478
8457 11:19:02.387531
8458 11:19:02.387583 ==
8459 11:19:02.387635 Dram Type= 6, Freq= 0, CH_1, rank 0
8460 11:19:02.387688 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8461 11:19:02.387742 ==
8462 11:19:02.387795
8463 11:19:02.387847
8464 11:19:02.387899 TX Vref Scan disable
8465 11:19:02.387952 == TX Byte 0 ==
8466 11:19:02.388005 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8467 11:19:02.388058 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8468 11:19:02.388111 == TX Byte 1 ==
8469 11:19:02.388164 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8470 11:19:02.388217 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8471 11:19:02.388269 ==
8472 11:19:02.388322 Dram Type= 6, Freq= 0, CH_1, rank 0
8473 11:19:02.388375 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8474 11:19:02.388432 ==
8475 11:19:02.388485
8476 11:19:02.388537 TX Vref early break, caculate TX vref
8477 11:19:02.388591 TX Vref=16, minBit 8, minWin=21, winSum=365
8478 11:19:02.388644 TX Vref=18, minBit 8, minWin=21, winSum=374
8479 11:19:02.388698 TX Vref=20, minBit 8, minWin=22, winSum=386
8480 11:19:02.388751 TX Vref=22, minBit 8, minWin=23, winSum=395
8481 11:19:02.388804 TX Vref=24, minBit 8, minWin=23, winSum=408
8482 11:19:02.388857 TX Vref=26, minBit 8, minWin=25, winSum=414
8483 11:19:02.388912 TX Vref=28, minBit 8, minWin=25, winSum=426
8484 11:19:02.388964 TX Vref=30, minBit 0, minWin=26, winSum=423
8485 11:19:02.389017 TX Vref=32, minBit 5, minWin=25, winSum=414
8486 11:19:02.389070 TX Vref=34, minBit 0, minWin=24, winSum=401
8487 11:19:02.389123 [TxChooseVref] Worse bit 0, Min win 26, Win sum 423, Final Vref 30
8488 11:19:02.389176
8489 11:19:02.389229 Final TX Range 0 Vref 30
8490 11:19:02.389281
8491 11:19:02.389334 ==
8492 11:19:02.389386 Dram Type= 6, Freq= 0, CH_1, rank 0
8493 11:19:02.389439 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8494 11:19:02.389493 ==
8495 11:19:02.389545
8496 11:19:02.389597
8497 11:19:02.389649 TX Vref Scan disable
8498 11:19:02.389702 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8499 11:19:02.389755 == TX Byte 0 ==
8500 11:19:02.389808 u2DelayCellOfst[0]=17 cells (5 PI)
8501 11:19:02.389860 u2DelayCellOfst[1]=14 cells (4 PI)
8502 11:19:02.389913 u2DelayCellOfst[2]=0 cells (0 PI)
8503 11:19:02.389966 u2DelayCellOfst[3]=7 cells (2 PI)
8504 11:19:02.390019 u2DelayCellOfst[4]=7 cells (2 PI)
8505 11:19:02.390071 u2DelayCellOfst[5]=21 cells (6 PI)
8506 11:19:02.390125 u2DelayCellOfst[6]=17 cells (5 PI)
8507 11:19:02.390178 u2DelayCellOfst[7]=7 cells (2 PI)
8508 11:19:02.390231 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8509 11:19:02.390284 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8510 11:19:02.390337 == TX Byte 1 ==
8511 11:19:02.390389 u2DelayCellOfst[8]=0 cells (0 PI)
8512 11:19:02.390442 u2DelayCellOfst[9]=7 cells (2 PI)
8513 11:19:02.390494 u2DelayCellOfst[10]=14 cells (4 PI)
8514 11:19:02.390557 u2DelayCellOfst[11]=10 cells (3 PI)
8515 11:19:02.390611 u2DelayCellOfst[12]=17 cells (5 PI)
8516 11:19:02.390665 u2DelayCellOfst[13]=21 cells (6 PI)
8517 11:19:02.390718 u2DelayCellOfst[14]=21 cells (6 PI)
8518 11:19:02.390771 u2DelayCellOfst[15]=21 cells (6 PI)
8519 11:19:02.390824 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8520 11:19:02.390878 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8521 11:19:02.390931 DramC Write-DBI on
8522 11:19:02.390984 ==
8523 11:19:02.391221 Dram Type= 6, Freq= 0, CH_1, rank 0
8524 11:19:02.391284 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8525 11:19:02.391338 ==
8526 11:19:02.391403
8527 11:19:02.391457
8528 11:19:02.391509 TX Vref Scan disable
8529 11:19:02.391562 == TX Byte 0 ==
8530 11:19:02.391616 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8531 11:19:02.391669 == TX Byte 1 ==
8532 11:19:02.391735 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8533 11:19:02.391785 DramC Write-DBI off
8534 11:19:02.391836
8535 11:19:02.391887 [DATLAT]
8536 11:19:02.391938 Freq=1600, CH1 RK0
8537 11:19:02.392017
8538 11:19:02.392068 DATLAT Default: 0xf
8539 11:19:02.392119 0, 0xFFFF, sum = 0
8540 11:19:02.392171 1, 0xFFFF, sum = 0
8541 11:19:02.392224 2, 0xFFFF, sum = 0
8542 11:19:02.392275 3, 0xFFFF, sum = 0
8543 11:19:02.392326 4, 0xFFFF, sum = 0
8544 11:19:02.392378 5, 0xFFFF, sum = 0
8545 11:19:02.392429 6, 0xFFFF, sum = 0
8546 11:19:02.392481 7, 0xFFFF, sum = 0
8547 11:19:02.392532 8, 0xFFFF, sum = 0
8548 11:19:02.392584 9, 0xFFFF, sum = 0
8549 11:19:02.392636 10, 0xFFFF, sum = 0
8550 11:19:02.392687 11, 0xFFFF, sum = 0
8551 11:19:02.392739 12, 0xFFFF, sum = 0
8552 11:19:02.392790 13, 0xFFFF, sum = 0
8553 11:19:02.392842 14, 0x0, sum = 1
8554 11:19:02.392897 15, 0x0, sum = 2
8555 11:19:02.392949 16, 0x0, sum = 3
8556 11:19:02.393001 17, 0x0, sum = 4
8557 11:19:02.393051 best_step = 15
8558 11:19:02.393102
8559 11:19:02.393152 ==
8560 11:19:02.393203 Dram Type= 6, Freq= 0, CH_1, rank 0
8561 11:19:02.393253 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8562 11:19:02.393305 ==
8563 11:19:02.393356 RX Vref Scan: 1
8564 11:19:02.393406
8565 11:19:02.393456 Set Vref Range= 24 -> 127
8566 11:19:02.393506
8567 11:19:02.393557 RX Vref 24 -> 127, step: 1
8568 11:19:02.393608
8569 11:19:02.393659 RX Delay 11 -> 252, step: 4
8570 11:19:02.393709
8571 11:19:02.393760 Set Vref, RX VrefLevel [Byte0]: 24
8572 11:19:02.393811 [Byte1]: 24
8573 11:19:02.393862
8574 11:19:02.393912 Set Vref, RX VrefLevel [Byte0]: 25
8575 11:19:02.393962 [Byte1]: 25
8576 11:19:02.394013
8577 11:19:02.394064 Set Vref, RX VrefLevel [Byte0]: 26
8578 11:19:02.394114 [Byte1]: 26
8579 11:19:02.394165
8580 11:19:02.394215 Set Vref, RX VrefLevel [Byte0]: 27
8581 11:19:02.394265 [Byte1]: 27
8582 11:19:02.394316
8583 11:19:02.394366 Set Vref, RX VrefLevel [Byte0]: 28
8584 11:19:02.394417 [Byte1]: 28
8585 11:19:02.394468
8586 11:19:02.394518 Set Vref, RX VrefLevel [Byte0]: 29
8587 11:19:02.394569 [Byte1]: 29
8588 11:19:02.394619
8589 11:19:02.394670 Set Vref, RX VrefLevel [Byte0]: 30
8590 11:19:02.394720 [Byte1]: 30
8591 11:19:02.394771
8592 11:19:02.394821 Set Vref, RX VrefLevel [Byte0]: 31
8593 11:19:02.394872 [Byte1]: 31
8594 11:19:02.394923
8595 11:19:02.394973 Set Vref, RX VrefLevel [Byte0]: 32
8596 11:19:02.395023 [Byte1]: 32
8597 11:19:02.395074
8598 11:19:02.395124 Set Vref, RX VrefLevel [Byte0]: 33
8599 11:19:02.395175 [Byte1]: 33
8600 11:19:02.395224
8601 11:19:02.395275 Set Vref, RX VrefLevel [Byte0]: 34
8602 11:19:02.395341 [Byte1]: 34
8603 11:19:02.395449
8604 11:19:02.395501 Set Vref, RX VrefLevel [Byte0]: 35
8605 11:19:02.395552 [Byte1]: 35
8606 11:19:02.395603
8607 11:19:02.395654 Set Vref, RX VrefLevel [Byte0]: 36
8608 11:19:02.395705 [Byte1]: 36
8609 11:19:02.395756
8610 11:19:02.395806 Set Vref, RX VrefLevel [Byte0]: 37
8611 11:19:02.395858 [Byte1]: 37
8612 11:19:02.395909
8613 11:19:02.395959 Set Vref, RX VrefLevel [Byte0]: 38
8614 11:19:02.396010 [Byte1]: 38
8615 11:19:02.396061
8616 11:19:02.396111 Set Vref, RX VrefLevel [Byte0]: 39
8617 11:19:02.396161 [Byte1]: 39
8618 11:19:02.396212
8619 11:19:02.396262 Set Vref, RX VrefLevel [Byte0]: 40
8620 11:19:02.396313 [Byte1]: 40
8621 11:19:02.396363
8622 11:19:02.396413 Set Vref, RX VrefLevel [Byte0]: 41
8623 11:19:02.396464 [Byte1]: 41
8624 11:19:02.396515
8625 11:19:02.396565 Set Vref, RX VrefLevel [Byte0]: 42
8626 11:19:02.396615 [Byte1]: 42
8627 11:19:02.396666
8628 11:19:02.396716 Set Vref, RX VrefLevel [Byte0]: 43
8629 11:19:02.396767 [Byte1]: 43
8630 11:19:02.396818
8631 11:19:02.396868 Set Vref, RX VrefLevel [Byte0]: 44
8632 11:19:02.396919 [Byte1]: 44
8633 11:19:02.396969
8634 11:19:02.397020 Set Vref, RX VrefLevel [Byte0]: 45
8635 11:19:02.397071 [Byte1]: 45
8636 11:19:02.397122
8637 11:19:02.397173 Set Vref, RX VrefLevel [Byte0]: 46
8638 11:19:02.397224 [Byte1]: 46
8639 11:19:02.397274
8640 11:19:02.397324 Set Vref, RX VrefLevel [Byte0]: 47
8641 11:19:02.397376 [Byte1]: 47
8642 11:19:02.397426
8643 11:19:02.397476 Set Vref, RX VrefLevel [Byte0]: 48
8644 11:19:02.397526 [Byte1]: 48
8645 11:19:02.397578
8646 11:19:02.397628 Set Vref, RX VrefLevel [Byte0]: 49
8647 11:19:02.397679 [Byte1]: 49
8648 11:19:02.397729
8649 11:19:02.397780 Set Vref, RX VrefLevel [Byte0]: 50
8650 11:19:02.397830 [Byte1]: 50
8651 11:19:02.397881
8652 11:19:02.397931 Set Vref, RX VrefLevel [Byte0]: 51
8653 11:19:02.397982 [Byte1]: 51
8654 11:19:02.398033
8655 11:19:02.398084 Set Vref, RX VrefLevel [Byte0]: 52
8656 11:19:02.398134 [Byte1]: 52
8657 11:19:02.398185
8658 11:19:02.398235 Set Vref, RX VrefLevel [Byte0]: 53
8659 11:19:02.398304 [Byte1]: 53
8660 11:19:02.398400
8661 11:19:02.398450 Set Vref, RX VrefLevel [Byte0]: 54
8662 11:19:02.398501 [Byte1]: 54
8663 11:19:02.398552
8664 11:19:02.398603 Set Vref, RX VrefLevel [Byte0]: 55
8665 11:19:02.398653 [Byte1]: 55
8666 11:19:02.398704
8667 11:19:02.398754 Set Vref, RX VrefLevel [Byte0]: 56
8668 11:19:02.398805 [Byte1]: 56
8669 11:19:02.398856
8670 11:19:02.398906 Set Vref, RX VrefLevel [Byte0]: 57
8671 11:19:02.398957 [Byte1]: 57
8672 11:19:02.399008
8673 11:19:02.399058 Set Vref, RX VrefLevel [Byte0]: 58
8674 11:19:02.399109 [Byte1]: 58
8675 11:19:02.399159
8676 11:19:02.399210 Set Vref, RX VrefLevel [Byte0]: 59
8677 11:19:02.399260 [Byte1]: 59
8678 11:19:02.399310
8679 11:19:02.399366 Set Vref, RX VrefLevel [Byte0]: 60
8680 11:19:02.399471 [Byte1]: 60
8681 11:19:02.399522
8682 11:19:02.399572 Set Vref, RX VrefLevel [Byte0]: 61
8683 11:19:02.399623 [Byte1]: 61
8684 11:19:02.399674
8685 11:19:02.399724 Set Vref, RX VrefLevel [Byte0]: 62
8686 11:19:02.399775 [Byte1]: 62
8687 11:19:02.399825
8688 11:19:02.399876 Set Vref, RX VrefLevel [Byte0]: 63
8689 11:19:02.399927 [Byte1]: 63
8690 11:19:02.399978
8691 11:19:02.400028 Set Vref, RX VrefLevel [Byte0]: 64
8692 11:19:02.400079 [Byte1]: 64
8693 11:19:02.400129
8694 11:19:02.400180 Set Vref, RX VrefLevel [Byte0]: 65
8695 11:19:02.400231 [Byte1]: 65
8696 11:19:02.400282
8697 11:19:02.400514 Set Vref, RX VrefLevel [Byte0]: 66
8698 11:19:02.400620 [Byte1]: 66
8699 11:19:02.400703
8700 11:19:02.400783 Set Vref, RX VrefLevel [Byte0]: 67
8701 11:19:02.400835 [Byte1]: 67
8702 11:19:02.400899
8703 11:19:02.400949 Set Vref, RX VrefLevel [Byte0]: 68
8704 11:19:02.401016 [Byte1]: 68
8705 11:19:02.401080
8706 11:19:02.401131 Set Vref, RX VrefLevel [Byte0]: 69
8707 11:19:02.401182 [Byte1]: 69
8708 11:19:02.401233
8709 11:19:02.401284 Set Vref, RX VrefLevel [Byte0]: 70
8710 11:19:02.401335 [Byte1]: 70
8711 11:19:02.401386
8712 11:19:02.401449 Set Vref, RX VrefLevel [Byte0]: 71
8713 11:19:02.401501 [Byte1]: 71
8714 11:19:02.401553
8715 11:19:02.401604 Set Vref, RX VrefLevel [Byte0]: 72
8716 11:19:02.401656 [Byte1]: 72
8717 11:19:02.401709
8718 11:19:02.401760 Set Vref, RX VrefLevel [Byte0]: 73
8719 11:19:02.401811 [Byte1]: 73
8720 11:19:02.401863
8721 11:19:02.401914 Final RX Vref Byte 0 = 56 to rank0
8722 11:19:02.401966 Final RX Vref Byte 1 = 56 to rank0
8723 11:19:02.402017 Final RX Vref Byte 0 = 56 to rank1
8724 11:19:02.402069 Final RX Vref Byte 1 = 56 to rank1==
8725 11:19:02.402122 Dram Type= 6, Freq= 0, CH_1, rank 0
8726 11:19:02.402174 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8727 11:19:02.402227 ==
8728 11:19:02.402278 DQS Delay:
8729 11:19:02.402330 DQS0 = 0, DQS1 = 0
8730 11:19:02.402381 DQM Delay:
8731 11:19:02.402432 DQM0 = 131, DQM1 = 124
8732 11:19:02.402484 DQ Delay:
8733 11:19:02.402535 DQ0 =136, DQ1 =124, DQ2 =118, DQ3 =130
8734 11:19:02.402587 DQ4 =130, DQ5 =142, DQ6 =142, DQ7 =128
8735 11:19:02.402638 DQ8 =110, DQ9 =112, DQ10 =128, DQ11 =120
8736 11:19:02.402690 DQ12 =132, DQ13 =132, DQ14 =130, DQ15 =132
8737 11:19:02.402743
8738 11:19:02.402794
8739 11:19:02.402846
8740 11:19:02.402897 [DramC_TX_OE_Calibration] TA2
8741 11:19:02.402948 Original DQ_B0 (3 6) =30, OEN = 27
8742 11:19:02.403000 Original DQ_B1 (3 6) =30, OEN = 27
8743 11:19:02.403052 24, 0x0, End_B0=24 End_B1=24
8744 11:19:02.403105 25, 0x0, End_B0=25 End_B1=25
8745 11:19:02.403158 26, 0x0, End_B0=26 End_B1=26
8746 11:19:02.403210 27, 0x0, End_B0=27 End_B1=27
8747 11:19:02.403263 28, 0x0, End_B0=28 End_B1=28
8748 11:19:02.403315 29, 0x0, End_B0=29 End_B1=29
8749 11:19:02.403406 30, 0x0, End_B0=30 End_B1=30
8750 11:19:02.403474 31, 0x4141, End_B0=30 End_B1=30
8751 11:19:02.403527 Byte0 end_step=30 best_step=27
8752 11:19:02.403579 Byte1 end_step=30 best_step=27
8753 11:19:02.403631 Byte0 TX OE(2T, 0.5T) = (3, 3)
8754 11:19:02.403682 Byte1 TX OE(2T, 0.5T) = (3, 3)
8755 11:19:02.403734
8756 11:19:02.403786
8757 11:19:02.403837 [DQSOSCAuto] RK0, (LSB)MR18= 0x1600, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 398 ps
8758 11:19:02.403890 CH1 RK0: MR19=303, MR18=1600
8759 11:19:02.403942 CH1_RK0: MR19=0x303, MR18=0x1600, DQSOSC=398, MR23=63, INC=23, DEC=15
8760 11:19:02.403994
8761 11:19:02.404046 ----->DramcWriteLeveling(PI) begin...
8762 11:19:02.404098 ==
8763 11:19:02.404151 Dram Type= 6, Freq= 0, CH_1, rank 1
8764 11:19:02.404202 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8765 11:19:02.404255 ==
8766 11:19:02.404307 Write leveling (Byte 0): 27 => 27
8767 11:19:02.404359 Write leveling (Byte 1): 27 => 27
8768 11:19:02.404411 DramcWriteLeveling(PI) end<-----
8769 11:19:02.404463
8770 11:19:02.404514 ==
8771 11:19:02.404566 Dram Type= 6, Freq= 0, CH_1, rank 1
8772 11:19:02.404618 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8773 11:19:02.404670 ==
8774 11:19:02.404721 [Gating] SW mode calibration
8775 11:19:02.404772 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8776 11:19:02.404846 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8777 11:19:02.404901 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8778 11:19:02.404954 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8779 11:19:02.405006 1 4 8 | B1->B0 | 2323 2524 | 0 1 | (0 0) (0 0)
8780 11:19:02.405058 1 4 12 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
8781 11:19:02.405111 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8782 11:19:02.405162 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8783 11:19:02.405214 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8784 11:19:02.405267 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8785 11:19:02.405319 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8786 11:19:02.405370 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8787 11:19:02.405422 1 5 8 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
8788 11:19:02.405474 1 5 12 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
8789 11:19:02.405526 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8790 11:19:02.405578 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8791 11:19:02.405630 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8792 11:19:02.405683 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8793 11:19:02.405735 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8794 11:19:02.405787 1 6 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
8795 11:19:02.405838 1 6 8 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
8796 11:19:02.405891 1 6 12 | B1->B0 | 3333 4646 | 0 0 | (0 0) (0 0)
8797 11:19:02.405943 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8798 11:19:02.405994 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8799 11:19:02.406046 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8800 11:19:02.406097 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8801 11:19:02.406148 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8802 11:19:02.406200 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8803 11:19:02.406251 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8804 11:19:02.406303 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8805 11:19:02.406354 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8806 11:19:02.406407 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8807 11:19:02.406458 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8808 11:19:02.406511 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8809 11:19:02.406562 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8810 11:19:02.406615 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8811 11:19:02.406667 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8812 11:19:02.406905 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8813 11:19:02.406969 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8814 11:19:02.407022 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8815 11:19:02.407074 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8816 11:19:02.407126 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8817 11:19:02.407178 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8818 11:19:02.407230 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8819 11:19:02.407282 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8820 11:19:02.407334 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8821 11:19:02.407429 Total UI for P1: 0, mck2ui 16
8822 11:19:02.407482 best dqsien dly found for B0: ( 1, 9, 8)
8823 11:19:02.407535 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8824 11:19:02.407587 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8825 11:19:02.407639 Total UI for P1: 0, mck2ui 16
8826 11:19:02.407691 best dqsien dly found for B1: ( 1, 9, 14)
8827 11:19:02.407743 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8828 11:19:02.407795 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8829 11:19:02.407847
8830 11:19:02.407899 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8831 11:19:02.407950 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8832 11:19:02.408002 [Gating] SW calibration Done
8833 11:19:02.408054 ==
8834 11:19:02.408105 Dram Type= 6, Freq= 0, CH_1, rank 1
8835 11:19:02.408157 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8836 11:19:02.408210 ==
8837 11:19:02.408261 RX Vref Scan: 0
8838 11:19:02.408313
8839 11:19:02.408364 RX Vref 0 -> 0, step: 1
8840 11:19:02.408415
8841 11:19:02.408466 RX Delay 0 -> 252, step: 8
8842 11:19:02.408518 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8843 11:19:02.408570 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8844 11:19:02.408621 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8845 11:19:02.408673 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8846 11:19:02.408724 iDelay=200, Bit 4, Center 131 (72 ~ 191) 120
8847 11:19:02.408777 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8848 11:19:02.408828 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8849 11:19:02.408880 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8850 11:19:02.408931 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8851 11:19:02.408982 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8852 11:19:02.409033 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8853 11:19:02.409085 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8854 11:19:02.409136 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8855 11:19:02.409188 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8856 11:19:02.409239 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8857 11:19:02.409291 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8858 11:19:02.409342 ==
8859 11:19:02.409394 Dram Type= 6, Freq= 0, CH_1, rank 1
8860 11:19:02.409446 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8861 11:19:02.409498 ==
8862 11:19:02.409549 DQS Delay:
8863 11:19:02.409601 DQS0 = 0, DQS1 = 0
8864 11:19:02.409652 DQM Delay:
8865 11:19:02.409703 DQM0 = 132, DQM1 = 127
8866 11:19:02.409754 DQ Delay:
8867 11:19:02.409806 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8868 11:19:02.409858 DQ4 =131, DQ5 =147, DQ6 =143, DQ7 =127
8869 11:19:02.409909 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8870 11:19:02.409961 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8871 11:19:02.410013
8872 11:19:02.410064
8873 11:19:02.410114 ==
8874 11:19:02.410166 Dram Type= 6, Freq= 0, CH_1, rank 1
8875 11:19:02.410218 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8876 11:19:02.410270 ==
8877 11:19:02.410321
8878 11:19:02.410372
8879 11:19:02.410423 TX Vref Scan disable
8880 11:19:02.410474 == TX Byte 0 ==
8881 11:19:02.410526 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8882 11:19:02.410578 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8883 11:19:02.410630 == TX Byte 1 ==
8884 11:19:02.410681 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8885 11:19:02.410733 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8886 11:19:02.410785 ==
8887 11:19:02.410838 Dram Type= 6, Freq= 0, CH_1, rank 1
8888 11:19:02.410890 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8889 11:19:02.410942 ==
8890 11:19:02.410994
8891 11:19:02.411045 TX Vref early break, caculate TX vref
8892 11:19:02.411097 TX Vref=16, minBit 8, minWin=22, winSum=376
8893 11:19:02.411149 TX Vref=18, minBit 0, minWin=23, winSum=385
8894 11:19:02.411201 TX Vref=20, minBit 3, minWin=24, winSum=393
8895 11:19:02.411252 TX Vref=22, minBit 1, minWin=24, winSum=400
8896 11:19:02.411304 TX Vref=24, minBit 0, minWin=25, winSum=410
8897 11:19:02.411363 TX Vref=26, minBit 0, minWin=26, winSum=419
8898 11:19:02.411417 TX Vref=28, minBit 0, minWin=26, winSum=422
8899 11:19:02.411469 TX Vref=30, minBit 9, minWin=25, winSum=419
8900 11:19:02.411521 TX Vref=32, minBit 0, minWin=24, winSum=412
8901 11:19:02.411574 TX Vref=34, minBit 9, minWin=24, winSum=403
8902 11:19:02.411625 TX Vref=36, minBit 0, minWin=24, winSum=396
8903 11:19:02.411678 [TxChooseVref] Worse bit 0, Min win 26, Win sum 422, Final Vref 28
8904 11:19:02.411730
8905 11:19:02.411782 Final TX Range 0 Vref 28
8906 11:19:02.411834
8907 11:19:02.411885 ==
8908 11:19:02.411938 Dram Type= 6, Freq= 0, CH_1, rank 1
8909 11:19:02.411989 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8910 11:19:02.412041 ==
8911 11:19:02.412092
8912 11:19:02.412144
8913 11:19:02.412195 TX Vref Scan disable
8914 11:19:02.412247 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8915 11:19:02.412299 == TX Byte 0 ==
8916 11:19:02.412350 u2DelayCellOfst[0]=17 cells (5 PI)
8917 11:19:02.412402 u2DelayCellOfst[1]=10 cells (3 PI)
8918 11:19:02.412454 u2DelayCellOfst[2]=0 cells (0 PI)
8919 11:19:02.412505 u2DelayCellOfst[3]=7 cells (2 PI)
8920 11:19:02.412557 u2DelayCellOfst[4]=10 cells (3 PI)
8921 11:19:02.412608 u2DelayCellOfst[5]=21 cells (6 PI)
8922 11:19:02.412660 u2DelayCellOfst[6]=17 cells (5 PI)
8923 11:19:02.412712 u2DelayCellOfst[7]=7 cells (2 PI)
8924 11:19:02.412763 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8925 11:19:02.412816 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8926 11:19:02.534246 == TX Byte 1 ==
8927 11:19:02.534713 u2DelayCellOfst[8]=0 cells (0 PI)
8928 11:19:02.535033 u2DelayCellOfst[9]=7 cells (2 PI)
8929 11:19:02.535335 u2DelayCellOfst[10]=10 cells (3 PI)
8930 11:19:02.535655 u2DelayCellOfst[11]=7 cells (2 PI)
8931 11:19:02.535939 u2DelayCellOfst[12]=14 cells (4 PI)
8932 11:19:02.536216 u2DelayCellOfst[13]=14 cells (4 PI)
8933 11:19:02.536493 u2DelayCellOfst[14]=17 cells (5 PI)
8934 11:19:02.537103 u2DelayCellOfst[15]=17 cells (5 PI)
8935 11:19:02.537410 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8936 11:19:02.537692 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8937 11:19:02.537967 DramC Write-DBI on
8938 11:19:02.538238 ==
8939 11:19:02.538509 Dram Type= 6, Freq= 0, CH_1, rank 1
8940 11:19:02.538779 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8941 11:19:02.539050 ==
8942 11:19:02.539316
8943 11:19:02.539626
8944 11:19:02.539896 TX Vref Scan disable
8945 11:19:02.540163 == TX Byte 0 ==
8946 11:19:02.540431 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8947 11:19:02.540772 == TX Byte 1 ==
8948 11:19:02.541051 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8949 11:19:02.541326 DramC Write-DBI off
8950 11:19:02.541597
8951 11:19:02.541864 [DATLAT]
8952 11:19:02.542129 Freq=1600, CH1 RK1
8953 11:19:02.542400
8954 11:19:02.542665 DATLAT Default: 0xf
8955 11:19:02.542932 0, 0xFFFF, sum = 0
8956 11:19:02.543207 1, 0xFFFF, sum = 0
8957 11:19:02.543526 2, 0xFFFF, sum = 0
8958 11:19:02.543800 3, 0xFFFF, sum = 0
8959 11:19:02.544074 4, 0xFFFF, sum = 0
8960 11:19:02.544343 5, 0xFFFF, sum = 0
8961 11:19:02.544614 6, 0xFFFF, sum = 0
8962 11:19:02.544883 7, 0xFFFF, sum = 0
8963 11:19:02.545155 8, 0xFFFF, sum = 0
8964 11:19:02.545424 9, 0xFFFF, sum = 0
8965 11:19:02.545694 10, 0xFFFF, sum = 0
8966 11:19:02.545966 11, 0xFFFF, sum = 0
8967 11:19:02.546240 12, 0xFFFF, sum = 0
8968 11:19:02.546512 13, 0xFFFF, sum = 0
8969 11:19:02.546785 14, 0x0, sum = 1
8970 11:19:02.547058 15, 0x0, sum = 2
8971 11:19:02.547329 16, 0x0, sum = 3
8972 11:19:02.547633 17, 0x0, sum = 4
8973 11:19:02.547906 best_step = 15
8974 11:19:02.548173
8975 11:19:02.548439 ==
8976 11:19:02.548709 Dram Type= 6, Freq= 0, CH_1, rank 1
8977 11:19:02.548978 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8978 11:19:02.549249 ==
8979 11:19:02.549517 RX Vref Scan: 0
8980 11:19:02.549784
8981 11:19:02.550048 RX Vref 0 -> 0, step: 1
8982 11:19:02.550312
8983 11:19:02.550579 RX Delay 11 -> 252, step: 4
8984 11:19:02.550846 iDelay=195, Bit 0, Center 132 (83 ~ 182) 100
8985 11:19:02.551115 iDelay=195, Bit 1, Center 124 (71 ~ 178) 108
8986 11:19:02.551398 iDelay=195, Bit 2, Center 118 (67 ~ 170) 104
8987 11:19:02.551669 iDelay=195, Bit 3, Center 126 (75 ~ 178) 104
8988 11:19:02.551938 iDelay=195, Bit 4, Center 128 (75 ~ 182) 108
8989 11:19:02.552207 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8990 11:19:02.552474 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
8991 11:19:02.552740 iDelay=195, Bit 7, Center 124 (71 ~ 178) 108
8992 11:19:02.553007 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8993 11:19:02.553275 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8994 11:19:02.553542 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8995 11:19:02.553810 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8996 11:19:02.554078 iDelay=195, Bit 12, Center 134 (83 ~ 186) 104
8997 11:19:02.554348 iDelay=195, Bit 13, Center 134 (83 ~ 186) 104
8998 11:19:02.554614 iDelay=195, Bit 14, Center 134 (83 ~ 186) 104
8999 11:19:02.554880 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
9000 11:19:02.555146 ==
9001 11:19:02.555442 Dram Type= 6, Freq= 0, CH_1, rank 1
9002 11:19:02.555720 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9003 11:19:02.555988 ==
9004 11:19:02.556255 DQS Delay:
9005 11:19:02.556521 DQS0 = 0, DQS1 = 0
9006 11:19:02.556788 DQM Delay:
9007 11:19:02.557052 DQM0 = 129, DQM1 = 126
9008 11:19:02.557317 DQ Delay:
9009 11:19:02.557582 DQ0 =132, DQ1 =124, DQ2 =118, DQ3 =126
9010 11:19:02.557849 DQ4 =128, DQ5 =144, DQ6 =138, DQ7 =124
9011 11:19:02.558112 DQ8 =114, DQ9 =112, DQ10 =128, DQ11 =120
9012 11:19:02.558379 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =136
9013 11:19:02.558645
9014 11:19:02.558873
9015 11:19:02.559061
9016 11:19:02.559249 [DramC_TX_OE_Calibration] TA2
9017 11:19:02.559469 Original DQ_B0 (3 6) =30, OEN = 27
9018 11:19:02.559666 Original DQ_B1 (3 6) =30, OEN = 27
9019 11:19:02.559861 24, 0x0, End_B0=24 End_B1=24
9020 11:19:02.560055 25, 0x0, End_B0=25 End_B1=25
9021 11:19:02.560251 26, 0x0, End_B0=26 End_B1=26
9022 11:19:02.560446 27, 0x0, End_B0=27 End_B1=27
9023 11:19:02.560641 28, 0x0, End_B0=28 End_B1=28
9024 11:19:02.560835 29, 0x0, End_B0=29 End_B1=29
9025 11:19:02.561031 30, 0x0, End_B0=30 End_B1=30
9026 11:19:02.561226 31, 0x4141, End_B0=30 End_B1=30
9027 11:19:02.561420 Byte0 end_step=30 best_step=27
9028 11:19:02.561611 Byte1 end_step=30 best_step=27
9029 11:19:02.561803 Byte0 TX OE(2T, 0.5T) = (3, 3)
9030 11:19:02.561994 Byte1 TX OE(2T, 0.5T) = (3, 3)
9031 11:19:02.562184
9032 11:19:02.562375
9033 11:19:02.562565 [DQSOSCAuto] RK1, (LSB)MR18= 0xe12, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 402 ps
9034 11:19:02.562788 CH1 RK1: MR19=303, MR18=E12
9035 11:19:02.562986 CH1_RK1: MR19=0x303, MR18=0xE12, DQSOSC=400, MR23=63, INC=23, DEC=15
9036 11:19:02.563182 [RxdqsGatingPostProcess] freq 1600
9037 11:19:02.563410 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9038 11:19:02.563708 best DQS0 dly(2T, 0.5T) = (1, 1)
9039 11:19:02.563879 best DQS1 dly(2T, 0.5T) = (1, 1)
9040 11:19:02.564025 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9041 11:19:02.564171 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9042 11:19:02.564316 best DQS0 dly(2T, 0.5T) = (1, 1)
9043 11:19:02.564459 best DQS1 dly(2T, 0.5T) = (1, 1)
9044 11:19:02.564604 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9045 11:19:02.564749 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9046 11:19:02.564988 Pre-setting of DQS Precalculation
9047 11:19:02.565177 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9048 11:19:02.565335 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9049 11:19:02.565489 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9050 11:19:02.565638
9051 11:19:02.565786
9052 11:19:02.565935 [Calibration Summary] 3200 Mbps
9053 11:19:02.566085 CH 0, Rank 0
9054 11:19:02.566234 SW Impedance : PASS
9055 11:19:02.566385 DUTY Scan : NO K
9056 11:19:02.566535 ZQ Calibration : PASS
9057 11:19:02.566684 Jitter Meter : NO K
9058 11:19:02.566832 CBT Training : PASS
9059 11:19:02.566983 Write leveling : PASS
9060 11:19:02.567159 RX DQS gating : PASS
9061 11:19:02.567416 RX DQ/DQS(RDDQC) : PASS
9062 11:19:02.567576 TX DQ/DQS : PASS
9063 11:19:02.567729 RX DATLAT : PASS
9064 11:19:02.567878 RX DQ/DQS(Engine): PASS
9065 11:19:02.568028 TX OE : PASS
9066 11:19:02.568178 All Pass.
9067 11:19:02.568328
9068 11:19:02.568474 CH 0, Rank 1
9069 11:19:02.568624 SW Impedance : PASS
9070 11:19:02.568779 DUTY Scan : NO K
9071 11:19:02.568899 ZQ Calibration : PASS
9072 11:19:02.569018 Jitter Meter : NO K
9073 11:19:02.569138 CBT Training : PASS
9074 11:19:02.569257 Write leveling : PASS
9075 11:19:02.569376 RX DQS gating : PASS
9076 11:19:02.569495 RX DQ/DQS(RDDQC) : PASS
9077 11:19:02.569614 TX DQ/DQS : PASS
9078 11:19:02.569732 RX DATLAT : PASS
9079 11:19:02.569851 RX DQ/DQS(Engine): PASS
9080 11:19:02.569970 TX OE : PASS
9081 11:19:02.570089 All Pass.
9082 11:19:02.570207
9083 11:19:02.570555 CH 1, Rank 0
9084 11:19:02.570703 SW Impedance : PASS
9085 11:19:02.570825 DUTY Scan : NO K
9086 11:19:02.570945 ZQ Calibration : PASS
9087 11:19:02.571065 Jitter Meter : NO K
9088 11:19:02.571186 CBT Training : PASS
9089 11:19:02.571305 Write leveling : PASS
9090 11:19:02.571443 RX DQS gating : PASS
9091 11:19:02.571565 RX DQ/DQS(RDDQC) : PASS
9092 11:19:02.571684 TX DQ/DQS : PASS
9093 11:19:02.571803 RX DATLAT : PASS
9094 11:19:02.571922 RX DQ/DQS(Engine): PASS
9095 11:19:02.572040 TX OE : PASS
9096 11:19:02.572160 All Pass.
9097 11:19:02.572279
9098 11:19:02.572397 CH 1, Rank 1
9099 11:19:02.572514 SW Impedance : PASS
9100 11:19:02.572633 DUTY Scan : NO K
9101 11:19:02.572752 ZQ Calibration : PASS
9102 11:19:02.572872 Jitter Meter : NO K
9103 11:19:02.573057 CBT Training : PASS
9104 11:19:02.573238 Write leveling : PASS
9105 11:19:02.573365 RX DQS gating : PASS
9106 11:19:02.573485 RX DQ/DQS(RDDQC) : PASS
9107 11:19:02.573605 TX DQ/DQS : PASS
9108 11:19:02.573738 RX DATLAT : PASS
9109 11:19:02.573837 RX DQ/DQS(Engine): PASS
9110 11:19:02.573936 TX OE : PASS
9111 11:19:02.574036 All Pass.
9112 11:19:02.574135
9113 11:19:02.574235 DramC Write-DBI on
9114 11:19:02.574334 PER_BANK_REFRESH: Hybrid Mode
9115 11:19:02.574434 TX_TRACKING: ON
9116 11:19:02.574534 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9117 11:19:02.574637 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9118 11:19:02.574739 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9119 11:19:02.574840 [FAST_K] Save calibration result to emmc
9120 11:19:02.574941 sync common calibartion params.
9121 11:19:02.575041 sync cbt_mode0:1, 1:1
9122 11:19:02.575140 dram_init: ddr_geometry: 2
9123 11:19:02.575239 dram_init: ddr_geometry: 2
9124 11:19:02.575338 dram_init: ddr_geometry: 2
9125 11:19:02.575464 0:dram_rank_size:100000000
9126 11:19:02.575568 1:dram_rank_size:100000000
9127 11:19:02.575671 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9128 11:19:02.575773 DFS_SHUFFLE_HW_MODE: ON
9129 11:19:02.575873 dramc_set_vcore_voltage set vcore to 725000
9130 11:19:02.575973 Read voltage for 1600, 0
9131 11:19:02.576072 Vio18 = 0
9132 11:19:02.576172 Vcore = 725000
9133 11:19:02.576272 Vdram = 0
9134 11:19:02.576371 Vddq = 0
9135 11:19:02.576470 Vmddr = 0
9136 11:19:02.576570 switch to 3200 Mbps bootup
9137 11:19:02.576669 [DramcRunTimeConfig]
9138 11:19:02.576768 PHYPLL
9139 11:19:02.576867 DPM_CONTROL_AFTERK: ON
9140 11:19:02.576967 PER_BANK_REFRESH: ON
9141 11:19:02.577066 REFRESH_OVERHEAD_REDUCTION: ON
9142 11:19:02.577165 CMD_PICG_NEW_MODE: OFF
9143 11:19:02.577263 XRTWTW_NEW_MODE: ON
9144 11:19:02.577362 XRTRTR_NEW_MODE: ON
9145 11:19:02.577460 TX_TRACKING: ON
9146 11:19:02.577560 RDSEL_TRACKING: OFF
9147 11:19:02.577659 DQS Precalculation for DVFS: ON
9148 11:19:02.577759 RX_TRACKING: OFF
9149 11:19:02.577858 HW_GATING DBG: ON
9150 11:19:02.577958 ZQCS_ENABLE_LP4: ON
9151 11:19:02.578057 RX_PICG_NEW_MODE: ON
9152 11:19:02.578154 TX_PICG_NEW_MODE: ON
9153 11:19:02.578254 ENABLE_RX_DCM_DPHY: ON
9154 11:19:02.578353 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9155 11:19:02.578452 DUMMY_READ_FOR_TRACKING: OFF
9156 11:19:02.578552 !!! SPM_CONTROL_AFTERK: OFF
9157 11:19:02.578661 !!! SPM could not control APHY
9158 11:19:02.578770 IMPEDANCE_TRACKING: ON
9159 11:19:02.578855 TEMP_SENSOR: ON
9160 11:19:02.578938 HW_SAVE_FOR_SR: OFF
9161 11:19:02.579023 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9162 11:19:02.579108 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9163 11:19:02.579193 Read ODT Tracking: ON
9164 11:19:02.579279 Refresh Rate DeBounce: ON
9165 11:19:02.579372 DFS_NO_QUEUE_FLUSH: ON
9166 11:19:02.579460 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9167 11:19:02.579546 ENABLE_DFS_RUNTIME_MRW: OFF
9168 11:19:02.579631 DDR_RESERVE_NEW_MODE: ON
9169 11:19:02.579716 MR_CBT_SWITCH_FREQ: ON
9170 11:19:02.579801 =========================
9171 11:19:02.579887 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9172 11:19:02.579973 dram_init: ddr_geometry: 2
9173 11:19:02.580057 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9174 11:19:02.580144 dram_init: dram init end (result: 0)
9175 11:19:02.580230 DRAM-K: Full calibration passed in 24584 msecs
9176 11:19:02.580316 MRC: failed to locate region type 0.
9177 11:19:02.580402 DRAM rank0 size:0x100000000,
9178 11:19:02.580488 DRAM rank1 size=0x100000000
9179 11:19:02.580575 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9180 11:19:02.580662 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9181 11:19:02.580749 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9182 11:19:02.580836 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9183 11:19:02.580922 DRAM rank0 size:0x100000000,
9184 11:19:02.581008 DRAM rank1 size=0x100000000
9185 11:19:02.581093 CBMEM:
9186 11:19:02.581178 IMD: root @ 0xfffff000 254 entries.
9187 11:19:02.581265 IMD: root @ 0xffffec00 62 entries.
9188 11:19:02.581350 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9189 11:19:02.581436 WARNING: RO_VPD is uninitialized or empty.
9190 11:19:02.581522 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9191 11:19:02.581608 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9192 11:19:02.581696 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9193 11:19:02.581782 BS: romstage times (exec / console): total (unknown) / 24086 ms
9194 11:19:02.581868
9195 11:19:02.581954
9196 11:19:02.582039 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9197 11:19:02.582127 ARM64: Exception handlers installed.
9198 11:19:02.582212 ARM64: Testing exception
9199 11:19:02.582297 ARM64: Done test exception
9200 11:19:02.582382 Enumerating buses...
9201 11:19:02.582467 Show all devs... Before device enumeration.
9202 11:19:02.582552 Root Device: enabled 1
9203 11:19:02.582637 CPU_CLUSTER: 0: enabled 1
9204 11:19:02.582722 CPU: 00: enabled 1
9205 11:19:02.582808 Compare with tree...
9206 11:19:02.582893 Root Device: enabled 1
9207 11:19:02.582979 CPU_CLUSTER: 0: enabled 1
9208 11:19:02.583063 CPU: 00: enabled 1
9209 11:19:02.583149 Root Device scanning...
9210 11:19:02.583233 scan_static_bus for Root Device
9211 11:19:02.583318 CPU_CLUSTER: 0 enabled
9212 11:19:02.583423 scan_static_bus for Root Device done
9213 11:19:02.583715 scan_bus: bus Root Device finished in 8 msecs
9214 11:19:02.583820 done
9215 11:19:02.583899 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9216 11:19:02.583978 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9217 11:19:02.584056 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9218 11:19:02.584133 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9219 11:19:02.584210 Allocating resources...
9220 11:19:02.584286 Reading resources...
9221 11:19:02.584359 Root Device read_resources bus 0 link: 0
9222 11:19:02.584434 DRAM rank0 size:0x100000000,
9223 11:19:02.584510 DRAM rank1 size=0x100000000
9224 11:19:02.584584 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9225 11:19:02.584659 CPU: 00 missing read_resources
9226 11:19:02.584734 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9227 11:19:02.584816 Root Device read_resources bus 0 link: 0 done
9228 11:19:02.584892 Done reading resources.
9229 11:19:02.584968 Show resources in subtree (Root Device)...After reading.
9230 11:19:02.585044 Root Device child on link 0 CPU_CLUSTER: 0
9231 11:19:02.585119 CPU_CLUSTER: 0 child on link 0 CPU: 00
9232 11:19:02.585194 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9233 11:19:02.585271 CPU: 00
9234 11:19:02.585345 Root Device assign_resources, bus 0 link: 0
9235 11:19:02.585420 CPU_CLUSTER: 0 missing set_resources
9236 11:19:02.585496 Root Device assign_resources, bus 0 link: 0 done
9237 11:19:02.585572 Done setting resources.
9238 11:19:02.585646 Show resources in subtree (Root Device)...After assigning values.
9239 11:19:02.585721 Root Device child on link 0 CPU_CLUSTER: 0
9240 11:19:02.585796 CPU_CLUSTER: 0 child on link 0 CPU: 00
9241 11:19:02.585871 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9242 11:19:02.585946 CPU: 00
9243 11:19:02.586021 Done allocating resources.
9244 11:19:02.586096 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9245 11:19:02.586171 Enabling resources...
9246 11:19:02.586246 done.
9247 11:19:02.586320 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9248 11:19:02.586395 Initializing devices...
9249 11:19:02.586470 Root Device init
9250 11:19:02.586544 init hardware done!
9251 11:19:02.586618 0x00000018: ctrlr->caps
9252 11:19:02.586694 52.000 MHz: ctrlr->f_max
9253 11:19:02.586771 0.400 MHz: ctrlr->f_min
9254 11:19:02.586848 0x40ff8080: ctrlr->voltages
9255 11:19:02.586924 sclk: 390625
9256 11:19:02.586999 Bus Width = 1
9257 11:19:02.587073 sclk: 390625
9258 11:19:02.587147 Bus Width = 1
9259 11:19:02.587221 Early init status = 3
9260 11:19:02.587296 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9261 11:19:02.587391 in-header: 03 fc 00 00 01 00 00 00
9262 11:19:02.587469 in-data: 00
9263 11:19:02.587544 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9264 11:19:02.587620 in-header: 03 fd 00 00 00 00 00 00
9265 11:19:02.587696 in-data:
9266 11:19:02.587771 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9267 11:19:02.587846 in-header: 03 fc 00 00 01 00 00 00
9268 11:19:02.587921 in-data: 00
9269 11:19:02.587995 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9270 11:19:02.588071 in-header: 03 fd 00 00 00 00 00 00
9271 11:19:02.588144 in-data:
9272 11:19:02.588219 [SSUSB] Setting up USB HOST controller...
9273 11:19:02.588294 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9274 11:19:02.588369 [SSUSB] phy power-on done.
9275 11:19:02.588444 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9276 11:19:02.588520 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9277 11:19:02.588596 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9278 11:19:02.588672 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9279 11:19:02.588758 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9280 11:19:02.588825 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9281 11:19:02.588893 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9282 11:19:02.588960 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9283 11:19:02.589027 SPM: binary array size = 0x9dc
9284 11:19:02.589093 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9285 11:19:02.589160 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9286 11:19:02.589228 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9287 11:19:02.589296 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9288 11:19:02.589364 configure_display: Starting display init
9289 11:19:02.589431 anx7625_power_on_init: Init interface.
9290 11:19:02.589498 anx7625_disable_pd_protocol: Disabled PD feature.
9291 11:19:02.589565 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9292 11:19:02.589632 anx7625_start_dp_work: Secure OCM version=00
9293 11:19:02.589699 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9294 11:19:02.589764 sp_tx_get_edid_block: EDID Block = 1
9295 11:19:02.589829 Extracted contents:
9296 11:19:02.589893 header: 00 ff ff ff ff ff ff 00
9297 11:19:02.589959 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9298 11:19:02.590024 version: 01 04
9299 11:19:02.590092 basic params: 95 1f 11 78 0a
9300 11:19:02.590156 chroma info: 76 90 94 55 54 90 27 21 50 54
9301 11:19:02.590220 established: 00 00 00
9302 11:19:02.590284 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9303 11:19:02.590349 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9304 11:19:02.590414 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9305 11:19:02.590479 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9306 11:19:02.590544 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9307 11:19:02.590610 extensions: 00
9308 11:19:02.590673 checksum: fb
9309 11:19:02.590737
9310 11:19:02.590802 Manufacturer: IVO Model 57d Serial Number 0
9311 11:19:02.590867 Made week 0 of 2020
9312 11:19:02.591126 EDID version: 1.4
9313 11:19:02.591203 Digital display
9314 11:19:02.591269 6 bits per primary color channel
9315 11:19:02.591335 DisplayPort interface
9316 11:19:02.591410 Maximum image size: 31 cm x 17 cm
9317 11:19:02.591476 Gamma: 220%
9318 11:19:02.591540 Check DPMS levels
9319 11:19:02.591605 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9320 11:19:02.591670 First detailed timing is preferred timing
9321 11:19:02.591735 Established timings supported:
9322 11:19:02.591800 Standard timings supported:
9323 11:19:02.591865 Detailed timings
9324 11:19:02.591929 Hex of detail: 383680a07038204018303c0035ae10000019
9325 11:19:02.591994 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9326 11:19:02.592060 0780 0798 07c8 0820 hborder 0
9327 11:19:02.592162 0438 043b 0447 0458 vborder 0
9328 11:19:02.592231 -hsync -vsync
9329 11:19:02.592311 Did detailed timing
9330 11:19:02.592394 Hex of detail: 000000000000000000000000000000000000
9331 11:19:02.592463 Manufacturer-specified data, tag 0
9332 11:19:02.592537 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9333 11:19:02.592627 ASCII string: InfoVision
9334 11:19:02.592695 Hex of detail: 000000fe00523134304e574635205248200a
9335 11:19:02.592761 ASCII string: R140NWF5 RH
9336 11:19:02.592858 Checksum
9337 11:19:02.592927 Checksum: 0xfb (valid)
9338 11:19:02.592993 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9339 11:19:02.593059 DSI data_rate: 832800000 bps
9340 11:19:02.593138 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9341 11:19:02.593220 anx7625_parse_edid: pixelclock(138800).
9342 11:19:02.593287 hactive(1920), hsync(48), hfp(24), hbp(88)
9343 11:19:02.593352 vactive(1080), vsync(12), vfp(3), vbp(17)
9344 11:19:02.593417 anx7625_dsi_config: config dsi.
9345 11:19:02.593494 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9346 11:19:02.593579 anx7625_dsi_config: success to config DSI
9347 11:19:02.593646 anx7625_dp_start: MIPI phy setup OK.
9348 11:19:02.593712 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9349 11:19:02.593786 mtk_ddp_mode_set invalid vrefresh 60
9350 11:19:02.593844 main_disp_path_setup
9351 11:19:02.593902 ovl_layer_smi_id_en
9352 11:19:02.593960 ovl_layer_smi_id_en
9353 11:19:02.594019 ccorr_config
9354 11:19:02.594076 aal_config
9355 11:19:02.594133 gamma_config
9356 11:19:02.594191 postmask_config
9357 11:19:02.594257 dither_config
9358 11:19:02.594335 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9359 11:19:02.594397 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9360 11:19:02.594457 Root Device init finished in 554 msecs
9361 11:19:02.594541 CPU_CLUSTER: 0 init
9362 11:19:02.594605 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9363 11:19:02.594690 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9364 11:19:02.594765 APU_MBOX 0x190000b0 = 0x10001
9365 11:19:02.594818 APU_MBOX 0x190001b0 = 0x10001
9366 11:19:02.594907 APU_MBOX 0x190005b0 = 0x10001
9367 11:19:02.594976 APU_MBOX 0x190006b0 = 0x10001
9368 11:19:02.595029 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9369 11:19:02.595090 read SPI 0x539f4 0xe237: 6249 us, 9267 KB/s, 74.136 Mbps
9370 11:19:02.595160 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9371 11:19:02.595215 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9372 11:19:02.595267 read SPI 0x61c74 0xe8ef: 6412 us, 9299 KB/s, 74.392 Mbps
9373 11:19:02.595320 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9374 11:19:02.595416 CPU_CLUSTER: 0 init finished in 81 msecs
9375 11:19:02.595470 Devices initialized
9376 11:19:02.595522 Show all devs... After init.
9377 11:19:02.595601 Root Device: enabled 1
9378 11:19:02.595655 CPU_CLUSTER: 0: enabled 1
9379 11:19:02.595708 CPU: 00: enabled 1
9380 11:19:02.595760 BS: BS_DEV_INIT run times (exec / console): 212 / 447 ms
9381 11:19:02.595812 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9382 11:19:02.595865 ELOG: NV offset 0x57f000 size 0x1000
9383 11:19:02.595917 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9384 11:19:02.595970 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9385 11:19:02.596022 ELOG: Event(17) added with size 13 at 2023-06-05 11:19:00 UTC
9386 11:19:02.596074 out: cmd=0x121: 03 db 21 01 00 00 00 00
9387 11:19:02.596127 in-header: 03 c6 00 00 2c 00 00 00
9388 11:19:02.596208 in-data: 99 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9389 11:19:02.596303 ELOG: Event(A1) added with size 10 at 2023-06-05 11:19:00 UTC
9390 11:19:02.596376 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9391 11:19:02.596431 ELOG: Event(A0) added with size 9 at 2023-06-05 11:19:00 UTC
9392 11:19:02.596491 elog_add_boot_reason: Logged dev mode boot
9393 11:19:02.596580 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9394 11:19:02.596663 Finalize devices...
9395 11:19:02.596753 Devices finalized
9396 11:19:02.596838 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9397 11:19:02.596920 Writing coreboot table at 0xffe64000
9398 11:19:02.597003 0. 000000000010a000-0000000000113fff: RAMSTAGE
9399 11:19:02.597114 1. 0000000040000000-00000000400fffff: RAM
9400 11:19:02.597169 2. 0000000040100000-000000004032afff: RAMSTAGE
9401 11:19:02.597221 3. 000000004032b000-00000000545fffff: RAM
9402 11:19:02.597274 4. 0000000054600000-000000005465ffff: BL31
9403 11:19:02.597327 5. 0000000054660000-00000000ffe63fff: RAM
9404 11:19:02.597379 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9405 11:19:02.597453 7. 0000000100000000-000000023fffffff: RAM
9406 11:19:02.597520 Passing 5 GPIOs to payload:
9407 11:19:02.597599 NAME | PORT | POLARITY | VALUE
9408 11:19:02.597655 EC in RW | 0x000000aa | low | undefined
9409 11:19:02.597893 EC interrupt | 0x00000005 | low | undefined
9410 11:19:02.598006 TPM interrupt | 0x000000ab | high | undefined
9411 11:19:02.598061 SD card detect | 0x00000011 | high | undefined
9412 11:19:02.598115 speaker enable | 0x00000093 | high | undefined
9413 11:19:02.598169 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9414 11:19:02.598223 in-header: 03 f9 00 00 02 00 00 00
9415 11:19:02.598276 in-data: 02 00
9416 11:19:02.598329 ADC[4]: Raw value=899852 ID=7
9417 11:19:02.598382 ADC[3]: Raw value=213336 ID=1
9418 11:19:02.598449 RAM Code: 0x71
9419 11:19:02.598528 ADC[6]: Raw value=74926 ID=0
9420 11:19:02.598582 ADC[5]: Raw value=211860 ID=1
9421 11:19:02.598634 SKU Code: 0x1
9422 11:19:02.598686 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum ded1
9423 11:19:02.598739 coreboot table: 964 bytes.
9424 11:19:02.598791 IMD ROOT 0. 0xfffff000 0x00001000
9425 11:19:02.598842 IMD SMALL 1. 0xffffe000 0x00001000
9426 11:19:02.598894 RO MCACHE 2. 0xffffc000 0x00001104
9427 11:19:02.598946 CONSOLE 3. 0xfff7c000 0x00080000
9428 11:19:02.598998 FMAP 4. 0xfff7b000 0x00000452
9429 11:19:02.599062 TIME STAMP 5. 0xfff7a000 0x00000910
9430 11:19:02.599129 VBOOT WORK 6. 0xfff66000 0x00014000
9431 11:19:02.599182 RAMOOPS 7. 0xffe66000 0x00100000
9432 11:19:02.599235 COREBOOT 8. 0xffe64000 0x00002000
9433 11:19:02.599287 IMD small region:
9434 11:19:02.599339 IMD ROOT 0. 0xffffec00 0x00000400
9435 11:19:02.599433 VPD 1. 0xffffeba0 0x0000004c
9436 11:19:02.599511 MMC STATUS 2. 0xffffeb80 0x00000004
9437 11:19:02.599605 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9438 11:19:02.599664 Probing TPM: done!
9439 11:19:02.599718 Connected to device vid:did:rid of 1ae0:0028:00
9440 11:19:02.599772 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9441 11:19:02.599825 Initialized TPM device CR50 revision 0
9442 11:19:02.599877 Checking cr50 for pending updates
9443 11:19:02.599930 Reading cr50 TPM mode
9444 11:19:02.599982 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9445 11:19:02.600034 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9446 11:19:02.600087 read SPI 0x3990ec 0x4f1b0: 34856 us, 9295 KB/s, 74.360 Mbps
9447 11:19:02.600140 Checking segment from ROM address 0x40100000
9448 11:19:02.600192 Checking segment from ROM address 0x4010001c
9449 11:19:02.600245 Loading segment from ROM address 0x40100000
9450 11:19:02.600296 code (compression=0)
9451 11:19:02.600348 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9452 11:19:02.600414 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9453 11:19:02.600480 it's not compressed!
9454 11:19:02.600531 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9455 11:19:02.600584 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9456 11:19:02.600636 Loading segment from ROM address 0x4010001c
9457 11:19:02.600688 Entry Point 0x80000000
9458 11:19:02.600739 Loaded segments
9459 11:19:02.600791 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9460 11:19:02.600843 Jumping to boot code at 0x80000000(0xffe64000)
9461 11:19:02.600896 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9462 11:19:02.600948 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9463 11:19:02.601000 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9464 11:19:02.601052 Checking segment from ROM address 0x40100000
9465 11:19:02.601104 Checking segment from ROM address 0x4010001c
9466 11:19:02.601156 Loading segment from ROM address 0x40100000
9467 11:19:02.601208 code (compression=1)
9468 11:19:02.601259 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9469 11:19:02.601312 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9470 11:19:02.601363 using LZMA
9471 11:19:02.601415 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9472 11:19:02.601468 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9473 11:19:02.601520 Loading segment from ROM address 0x4010001c
9474 11:19:02.601572 Entry Point 0x54601000
9475 11:19:02.601623 Loaded segments
9476 11:19:02.601675 NOTICE: MT8192 bl31_setup
9477 11:19:02.601728 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9478 11:19:02.601781 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9479 11:19:02.601834 WARNING: region 0:
9480 11:19:02.601886 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9481 11:19:02.601937 WARNING: region 1:
9482 11:19:02.601989 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9483 11:19:02.602041 WARNING: region 2:
9484 11:19:02.602093 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9485 11:19:02.602145 WARNING: region 3:
9486 11:19:02.602196 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9487 11:19:02.602248 WARNING: region 4:
9488 11:19:02.602300 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9489 11:19:02.602351 WARNING: region 5:
9490 11:19:02.602403 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9491 11:19:02.602455 WARNING: region 6:
9492 11:19:02.602506 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9493 11:19:02.602558 WARNING: region 7:
9494 11:19:02.602610 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9495 11:19:02.602662 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9496 11:19:02.602714 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9497 11:19:02.602765 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9498 11:19:02.602817 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9499 11:19:02.602869 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9500 11:19:02.602933 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9501 11:19:02.603171 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9502 11:19:02.603233 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9503 11:19:02.603286 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9504 11:19:02.603338 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9505 11:19:02.603428 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9506 11:19:02.603481 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9507 11:19:02.603534 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9508 11:19:02.603586 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9509 11:19:02.603637 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9510 11:19:02.603689 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9511 11:19:02.603740 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9512 11:19:02.603792 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9513 11:19:02.603844 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9514 11:19:02.603895 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9515 11:19:02.603947 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9516 11:19:02.603999 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9517 11:19:02.604050 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9518 11:19:02.604103 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9519 11:19:02.604155 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9520 11:19:02.604207 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9521 11:19:02.604260 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9522 11:19:02.604311 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9523 11:19:02.604363 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9524 11:19:02.604415 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9525 11:19:02.604467 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9526 11:19:02.604519 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9527 11:19:02.604570 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9528 11:19:02.604622 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9529 11:19:02.604674 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9530 11:19:02.604725 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9531 11:19:02.604777 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9532 11:19:02.604828 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9533 11:19:02.604880 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9534 11:19:02.604931 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9535 11:19:02.604983 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9536 11:19:02.605035 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9537 11:19:02.605087 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9538 11:19:02.605138 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9539 11:19:02.605190 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9540 11:19:02.605242 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9541 11:19:02.605294 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9542 11:19:02.605346 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9543 11:19:02.605398 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9544 11:19:02.605449 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9545 11:19:02.605501 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9546 11:19:02.605552 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9547 11:19:02.605604 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9548 11:19:02.605656 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9549 11:19:02.605708 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9550 11:19:02.605760 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9551 11:19:02.605812 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9552 11:19:02.605863 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9553 11:19:02.605914 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9554 11:19:02.605966 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9555 11:19:02.606018 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9556 11:19:02.606069 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9557 11:19:02.606120 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9558 11:19:02.606172 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9559 11:19:02.606223 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9560 11:19:02.606274 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9561 11:19:02.606326 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9562 11:19:02.606378 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9563 11:19:02.606429 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9564 11:19:02.606481 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9565 11:19:02.606532 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9566 11:19:02.606584 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9567 11:19:02.606636 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9568 11:19:02.606688 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9569 11:19:02.606739 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9570 11:19:02.606791 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9571 11:19:02.606843 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9572 11:19:02.606896 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9573 11:19:02.606947 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9574 11:19:02.606999 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9575 11:19:02.607051 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9576 11:19:02.607102 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9577 11:19:02.607153 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9578 11:19:02.607413 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9579 11:19:02.607472 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9580 11:19:02.607524 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9581 11:19:02.607577 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9582 11:19:02.607629 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9583 11:19:02.607681 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9584 11:19:02.607733 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9585 11:19:02.607785 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9586 11:19:02.607838 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9587 11:19:02.607890 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9588 11:19:02.607942 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9589 11:19:02.607994 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9590 11:19:02.608046 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9591 11:19:02.608098 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9592 11:19:02.608149 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9593 11:19:02.608201 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9594 11:19:02.608253 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9595 11:19:02.608304 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9596 11:19:02.608356 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9597 11:19:02.608408 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9598 11:19:02.608460 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9599 11:19:02.608511 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9600 11:19:02.608563 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9601 11:19:02.608615 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9602 11:19:02.608667 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9603 11:19:02.608719 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9604 11:19:02.608771 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9605 11:19:02.608823 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9606 11:19:02.608875 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9607 11:19:02.608927 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9608 11:19:02.608979 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9609 11:19:02.609030 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9610 11:19:02.609082 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9611 11:19:02.609134 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9612 11:19:02.609186 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9613 11:19:02.609237 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9614 11:19:02.609289 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9615 11:19:02.609341 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9616 11:19:02.609393 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9617 11:19:02.609444 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9618 11:19:02.609496 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9619 11:19:02.609548 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9620 11:19:02.609599 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9621 11:19:02.609651 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9622 11:19:02.609702 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9623 11:19:02.609754 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9624 11:19:02.609806 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9625 11:19:02.609858 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9626 11:19:02.609910 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9627 11:19:02.609962 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9628 11:19:02.610014 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9629 11:19:02.610066 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9630 11:19:02.610117 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9631 11:19:02.610169 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9632 11:19:02.610221 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9633 11:19:02.610273 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9634 11:19:02.610324 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9635 11:19:02.610376 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9636 11:19:02.610428 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9637 11:19:02.610480 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9638 11:19:02.610531 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9639 11:19:02.610583 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9640 11:19:02.610635 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9641 11:19:02.610687 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9642 11:19:02.610738 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9643 11:19:02.610790 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9644 11:19:02.610842 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9645 11:19:02.610894 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9646 11:19:02.610946 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9647 11:19:02.610998 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9648 11:19:02.611050 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9649 11:19:02.611101 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9650 11:19:02.611153 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9651 11:19:02.611205 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9652 11:19:02.611256 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9653 11:19:02.611308 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9654 11:19:02.611388 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9655 11:19:02.611640 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9656 11:19:02.611705 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9657 11:19:02.611758 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9658 11:19:02.611810 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9659 11:19:02.611862 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9660 11:19:02.611914 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9661 11:19:02.611966 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9662 11:19:02.612017 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9663 11:19:02.612070 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9664 11:19:02.612121 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9665 11:19:02.612173 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9666 11:19:02.612225 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9667 11:19:02.612277 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9668 11:19:02.612329 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9669 11:19:02.612381 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9670 11:19:02.612432 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9671 11:19:02.612485 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9672 11:19:02.612537 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9673 11:19:02.612589 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9674 11:19:02.612641 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9675 11:19:02.612693 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9676 11:19:02.612745 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9677 11:19:02.612797 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9678 11:19:02.612849 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9679 11:19:02.612901 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9680 11:19:02.612952 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9681 11:19:02.613004 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9682 11:19:02.613055 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9683 11:19:02.613107 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9684 11:19:02.613159 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9685 11:19:02.613210 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9686 11:19:02.613262 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9687 11:19:02.613314 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9688 11:19:02.613366 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9689 11:19:02.613418 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9690 11:19:02.613469 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9691 11:19:02.613521 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9692 11:19:02.613573 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9693 11:19:02.613625 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9694 11:19:02.613676 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9695 11:19:02.613728 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9696 11:19:02.613780 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9697 11:19:02.613831 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9698 11:19:02.613882 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9699 11:19:02.613934 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9700 11:19:02.613986 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9701 11:19:02.614037 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9702 11:19:02.614089 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9703 11:19:02.614142 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9704 11:19:02.614193 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9705 11:19:02.614245 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9706 11:19:02.614297 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9707 11:19:02.614349 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9708 11:19:02.614400 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9709 11:19:02.614452 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9710 11:19:02.614503 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9711 11:19:02.614555 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9712 11:19:02.614606 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9713 11:19:02.614658 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9714 11:19:02.614710 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9715 11:19:02.614761 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9716 11:19:02.614813 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9717 11:19:02.614864 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9718 11:19:02.614916 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9719 11:19:02.614968 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9720 11:19:02.615019 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9721 11:19:02.615070 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9722 11:19:02.615121 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9723 11:19:02.615173 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9724 11:19:02.615224 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9725 11:19:02.615276 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9726 11:19:02.615328 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9727 11:19:02.615388 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9728 11:19:02.615441 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9729 11:19:02.615493 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9730 11:19:02.615544 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9731 11:19:02.615777 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9732 11:19:02.615835 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9733 11:19:02.615888 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9734 11:19:02.615940 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9735 11:19:02.615992 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9736 11:19:02.616045 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9737 11:19:02.616097 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9738 11:19:02.616150 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9739 11:19:02.616201 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9740 11:19:02.616254 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9741 11:19:02.616305 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9742 11:19:02.616357 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9743 11:19:02.616409 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9744 11:19:02.616462 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9745 11:19:02.616514 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9746 11:19:02.616566 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9747 11:19:02.616618 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9748 11:19:02.616670 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9749 11:19:02.616722 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9750 11:19:02.616774 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9751 11:19:02.616826 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9752 11:19:02.616878 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9753 11:19:02.616930 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9754 11:19:02.616982 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9755 11:19:02.617033 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9756 11:19:02.617085 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9757 11:19:02.617137 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9758 11:19:02.617189 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9759 11:19:02.617241 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9760 11:19:02.617293 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9761 11:19:02.617344 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9762 11:19:02.617395 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9763 11:19:02.617447 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9764 11:19:02.617499 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9765 11:19:02.617551 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9766 11:19:02.617602 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9767 11:19:02.617654 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9768 11:19:02.617706 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9769 11:19:02.617759 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9770 11:19:02.617811 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9771 11:19:02.617862 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9772 11:19:02.617914 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9773 11:19:02.617966 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9774 11:19:02.618017 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9775 11:19:02.618069 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9776 11:19:02.618121 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9777 11:19:02.618174 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9778 11:19:02.618225 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9779 11:19:02.618277 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9780 11:19:02.618329 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9781 11:19:02.618381 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9782 11:19:02.618433 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9783 11:19:02.618484 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9784 11:19:02.618536 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9785 11:19:02.618588 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9786 11:19:02.618640 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9787 11:19:02.618691 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9788 11:19:02.618742 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9789 11:19:02.618795 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9790 11:19:02.618847 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9791 11:19:02.618898 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9792 11:19:02.618950 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9793 11:19:02.619002 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9794 11:19:02.619053 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9795 11:19:02.619104 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9796 11:19:02.619156 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9797 11:19:02.619208 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9798 11:19:02.619260 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9799 11:19:02.619311 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9800 11:19:02.619434 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9801 11:19:02.619493 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9802 11:19:02.619547 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9803 11:19:02.619600 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9804 11:19:02.619653 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9805 11:19:02.619705 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9806 11:19:02.619758 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9807 11:19:02.619810 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9808 11:19:02.619862 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9809 11:19:02.620097 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9810 11:19:02.620158 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9811 11:19:02.620211 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9812 11:19:02.620264 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9813 11:19:02.620316 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9814 11:19:02.620368 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9815 11:19:02.620420 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9816 11:19:02.620472 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9817 11:19:02.620524 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9818 11:19:02.620576 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9819 11:19:02.620627 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9820 11:19:02.620679 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9821 11:19:02.620731 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9822 11:19:02.620783 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9823 11:19:02.620835 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9824 11:19:02.620887 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9825 11:19:02.620939 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9826 11:19:02.620991 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9827 11:19:02.621043 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9828 11:19:02.621095 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9829 11:19:02.621147 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9830 11:19:02.621199 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9831 11:19:02.621251 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9832 11:19:02.621303 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9833 11:19:02.621354 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9834 11:19:02.734495 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9835 11:19:02.734966 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9836 11:19:02.735290 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9837 11:19:02.735630 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9838 11:19:02.735923 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9839 11:19:02.736208 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9840 11:19:02.736486 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9841 11:19:02.736762 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9842 11:19:02.737036 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9843 11:19:02.737311 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9844 11:19:02.737585 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9845 11:19:02.737856 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9846 11:19:02.738229 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9847 11:19:02.738514 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9848 11:19:02.738787 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9849 11:19:02.739058 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9850 11:19:02.739327 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9851 11:19:02.739619 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9852 11:19:02.739892 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9853 11:19:02.740162 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9854 11:19:02.740434 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9855 11:19:02.740704 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9856 11:19:02.741000 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9857 11:19:02.741276 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9858 11:19:02.741546 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9859 11:19:02.741818 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9860 11:19:02.742087 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9861 11:19:02.742357 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9862 11:19:02.742626 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9863 11:19:02.742896 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9864 11:19:02.743165 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9865 11:19:02.743451 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9866 11:19:02.743722 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9867 11:19:02.743993 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9868 11:19:02.744262 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9869 11:19:02.744530 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9870 11:19:02.744796 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9871 11:19:02.745065 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9872 11:19:02.745333 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9873 11:19:02.745602 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9874 11:19:02.745870 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9875 11:19:02.746138 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9876 11:19:02.746405 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9877 11:19:02.746673 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9878 11:19:02.746941 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9879 11:19:02.747210 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9880 11:19:02.747497 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9881 11:19:02.747767 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9882 11:19:02.748035 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9883 11:19:02.748304 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9884 11:19:02.748904 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9885 11:19:02.749204 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9886 11:19:02.749479 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9887 11:19:02.749749 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9888 11:19:02.750020 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9889 11:19:02.750290 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9890 11:19:02.750653 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9891 11:19:02.750931 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9892 11:19:02.751202 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9893 11:19:02.751502 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9894 11:19:02.751773 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9895 11:19:02.752039 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9896 11:19:02.752308 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9897 11:19:02.752575 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9898 11:19:02.752844 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9899 11:19:02.753112 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9900 11:19:02.753380 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9901 11:19:02.753648 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9902 11:19:02.753918 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9903 11:19:02.754187 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9904 11:19:02.754453 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9905 11:19:02.754717 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9906 11:19:02.754984 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9907 11:19:02.755253 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9908 11:19:02.755542 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9909 11:19:02.755810 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9910 11:19:02.756079 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9911 11:19:02.756348 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9912 11:19:02.756614 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9913 11:19:02.756881 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9914 11:19:02.757150 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9915 11:19:02.757418 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9916 11:19:02.757688 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9917 11:19:02.757954 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9918 11:19:02.758224 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9919 11:19:02.758492 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9920 11:19:02.758761 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9921 11:19:02.759026 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9922 11:19:02.759294 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9923 11:19:02.759580 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9924 11:19:02.759849 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9925 11:19:02.760115 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9926 11:19:02.760381 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9927 11:19:02.760649 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9928 11:19:02.760879 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9929 11:19:02.761070 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9930 11:19:02.761260 INFO: [APUAPC] vio 0
9931 11:19:02.761450 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9932 11:19:02.761641 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9933 11:19:02.761831 INFO: [APUAPC] D0_APC_0: 0x400510
9934 11:19:02.762030 INFO: [APUAPC] D0_APC_1: 0x0
9935 11:19:02.762229 INFO: [APUAPC] D0_APC_2: 0x1540
9936 11:19:02.762429 INFO: [APUAPC] D0_APC_3: 0x0
9937 11:19:02.762626 INFO: [APUAPC] D1_APC_0: 0xffffffff
9938 11:19:02.762823 INFO: [APUAPC] D1_APC_1: 0xffffffff
9939 11:19:02.763022 INFO: [APUAPC] D1_APC_2: 0x3fffff
9940 11:19:02.763221 INFO: [APUAPC] D1_APC_3: 0x0
9941 11:19:02.763431 INFO: [APUAPC] D2_APC_0: 0xffffffff
9942 11:19:02.763631 INFO: [APUAPC] D2_APC_1: 0xffffffff
9943 11:19:02.763829 INFO: [APUAPC] D2_APC_2: 0x3fffff
9944 11:19:02.764039 INFO: [APUAPC] D2_APC_3: 0x0
9945 11:19:02.764237 INFO: [APUAPC] D3_APC_0: 0xffffffff
9946 11:19:02.764436 INFO: [APUAPC] D3_APC_1: 0xffffffff
9947 11:19:02.764633 INFO: [APUAPC] D3_APC_2: 0x3fffff
9948 11:19:02.764830 INFO: [APUAPC] D3_APC_3: 0x0
9949 11:19:02.765029 INFO: [APUAPC] D4_APC_0: 0xffffffff
9950 11:19:02.765227 INFO: [APUAPC] D4_APC_1: 0xffffffff
9951 11:19:02.765427 INFO: [APUAPC] D4_APC_2: 0x3fffff
9952 11:19:02.765624 INFO: [APUAPC] D4_APC_3: 0x0
9953 11:19:02.765810 INFO: [APUAPC] D5_APC_0: 0xffffffff
9954 11:19:02.765958 INFO: [APUAPC] D5_APC_1: 0xffffffff
9955 11:19:02.766107 INFO: [APUAPC] D5_APC_2: 0x3fffff
9956 11:19:02.766256 INFO: [APUAPC] D5_APC_3: 0x0
9957 11:19:02.766407 INFO: [APUAPC] D6_APC_0: 0xffffffff
9958 11:19:02.766554 INFO: [APUAPC] D6_APC_1: 0xffffffff
9959 11:19:02.766704 INFO: [APUAPC] D6_APC_2: 0x3fffff
9960 11:19:02.766852 INFO: [APUAPC] D6_APC_3: 0x0
9961 11:19:02.767002 INFO: [APUAPC] D7_APC_0: 0xffffffff
9962 11:19:02.767149 INFO: [APUAPC] D7_APC_1: 0xffffffff
9963 11:19:02.767297 INFO: [APUAPC] D7_APC_2: 0x3fffff
9964 11:19:02.767502 INFO: [APUAPC] D7_APC_3: 0x0
9965 11:19:02.767657 INFO: [APUAPC] D8_APC_0: 0xffffffff
9966 11:19:02.767808 INFO: [APUAPC] D8_APC_1: 0xffffffff
9967 11:19:02.767958 INFO: [APUAPC] D8_APC_2: 0x3fffff
9968 11:19:02.768107 INFO: [APUAPC] D8_APC_3: 0x0
9969 11:19:02.768257 INFO: [APUAPC] D9_APC_0: 0xffffffff
9970 11:19:02.768635 INFO: [APUAPC] D9_APC_1: 0xffffffff
9971 11:19:02.768799 INFO: [APUAPC] D9_APC_2: 0x3fffff
9972 11:19:02.768951 INFO: [APUAPC] D9_APC_3: 0x0
9973 11:19:02.769102 INFO: [APUAPC] D10_APC_0: 0xffffffff
9974 11:19:02.769252 INFO: [APUAPC] D10_APC_1: 0xffffffff
9975 11:19:02.769442 INFO: [APUAPC] D10_APC_2: 0x3fffff
9976 11:19:02.769681 INFO: [APUAPC] D10_APC_3: 0x0
9977 11:19:02.769843 INFO: [APUAPC] D11_APC_0: 0xffffffff
9978 11:19:02.769995 INFO: [APUAPC] D11_APC_1: 0xffffffff
9979 11:19:02.770146 INFO: [APUAPC] D11_APC_2: 0x3fffff
9980 11:19:02.770297 INFO: [APUAPC] D11_APC_3: 0x0
9981 11:19:02.770447 INFO: [APUAPC] D12_APC_0: 0xffffffff
9982 11:19:02.770599 INFO: [APUAPC] D12_APC_1: 0xffffffff
9983 11:19:02.770750 INFO: [APUAPC] D12_APC_2: 0x3fffff
9984 11:19:02.770887 INFO: [APUAPC] D12_APC_3: 0x0
9985 11:19:02.771008 INFO: [APUAPC] D13_APC_0: 0xffffffff
9986 11:19:02.771129 INFO: [APUAPC] D13_APC_1: 0xffffffff
9987 11:19:02.771250 INFO: [APUAPC] D13_APC_2: 0x3fffff
9988 11:19:02.771405 INFO: [APUAPC] D13_APC_3: 0x0
9989 11:19:02.771533 INFO: [APUAPC] D14_APC_0: 0xffffffff
9990 11:19:02.771655 INFO: [APUAPC] D14_APC_1: 0xffffffff
9991 11:19:02.771774 INFO: [APUAPC] D14_APC_2: 0x3fffff
9992 11:19:02.771894 INFO: [APUAPC] D14_APC_3: 0x0
9993 11:19:02.772014 INFO: [APUAPC] D15_APC_0: 0xffffffff
9994 11:19:02.772134 INFO: [APUAPC] D15_APC_1: 0xffffffff
9995 11:19:02.772254 INFO: [APUAPC] D15_APC_2: 0x3fffff
9996 11:19:02.772374 INFO: [APUAPC] D15_APC_3: 0x0
9997 11:19:02.772495 INFO: [APUAPC] APC_CON: 0x4
9998 11:19:02.772616 INFO: [NOCDAPC] D0_APC_0: 0x0
9999 11:19:02.772735 INFO: [NOCDAPC] D0_APC_1: 0x0
10000 11:19:02.772853 INFO: [NOCDAPC] D1_APC_0: 0x0
10001 11:19:02.772972 INFO: [NOCDAPC] D1_APC_1: 0xfff
10002 11:19:02.773092 INFO: [NOCDAPC] D2_APC_0: 0x0
10003 11:19:02.773214 INFO: [NOCDAPC] D2_APC_1: 0xfff
10004 11:19:02.773333 INFO: [NOCDAPC] D3_APC_0: 0x0
10005 11:19:02.773533 INFO: [NOCDAPC] D3_APC_1: 0xfff
10006 11:19:02.773661 INFO: [NOCDAPC] D4_APC_0: 0x0
10007 11:19:02.773783 INFO: [NOCDAPC] D4_APC_1: 0xfff
10008 11:19:02.773903 INFO: [NOCDAPC] D5_APC_0: 0x0
10009 11:19:02.774054 INFO: [NOCDAPC] D5_APC_1: 0xfff
10010 11:19:02.774181 INFO: [NOCDAPC] D6_APC_0: 0x0
10011 11:19:02.774302 INFO: [NOCDAPC] D6_APC_1: 0xfff
10012 11:19:02.777141 INFO: [NOCDAPC] D7_APC_0: 0x0
10013 11:19:02.779714 INFO: [NOCDAPC] D7_APC_1: 0xfff
10014 11:19:02.783411 INFO: [NOCDAPC] D8_APC_0: 0x0
10015 11:19:02.786618 INFO: [NOCDAPC] D8_APC_1: 0xfff
10016 11:19:02.789859 INFO: [NOCDAPC] D9_APC_0: 0x0
10017 11:19:02.793382 INFO: [NOCDAPC] D9_APC_1: 0xfff
10018 11:19:02.796515 INFO: [NOCDAPC] D10_APC_0: 0x0
10019 11:19:02.799622 INFO: [NOCDAPC] D10_APC_1: 0xfff
10020 11:19:02.803478 INFO: [NOCDAPC] D11_APC_0: 0x0
10021 11:19:02.806242 INFO: [NOCDAPC] D11_APC_1: 0xfff
10022 11:19:02.809847 INFO: [NOCDAPC] D12_APC_0: 0x0
10023 11:19:02.813638 INFO: [NOCDAPC] D12_APC_1: 0xfff
10024 11:19:02.813898 INFO: [NOCDAPC] D13_APC_0: 0x0
10025 11:19:02.816908 INFO: [NOCDAPC] D13_APC_1: 0xfff
10026 11:19:02.820060 INFO: [NOCDAPC] D14_APC_0: 0x0
10027 11:19:02.823554 INFO: [NOCDAPC] D14_APC_1: 0xfff
10028 11:19:02.826419 INFO: [NOCDAPC] D15_APC_0: 0x0
10029 11:19:02.830084 INFO: [NOCDAPC] D15_APC_1: 0xfff
10030 11:19:02.833812 INFO: [NOCDAPC] APC_CON: 0x4
10031 11:19:02.836345 INFO: [APUAPC] set_apusys_apc done
10032 11:19:02.840016 INFO: [DEVAPC] devapc_init done
10033 11:19:02.843515 INFO: GICv3 without legacy support detected.
10034 11:19:02.846685 INFO: ARM GICv3 driver initialized in EL3
10035 11:19:02.853046 INFO: Maximum SPI INTID supported: 639
10036 11:19:02.856633 INFO: BL31: Initializing runtime services
10037 11:19:02.859893 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10038 11:19:02.863376 INFO: SPM: enable CPC mode
10039 11:19:02.869797 INFO: mcdi ready for mcusys-off-idle and system suspend
10040 11:19:02.872804 INFO: BL31: Preparing for EL3 exit to normal world
10041 11:19:02.876193 INFO: Entry point address = 0x80000000
10042 11:19:02.879823 INFO: SPSR = 0x8
10043 11:19:02.885383
10044 11:19:02.885897
10045 11:19:02.886283
10046 11:19:02.888457 Starting depthcharge on Spherion...
10047 11:19:02.888871
10048 11:19:02.889251 Wipe memory regions:
10049 11:19:02.889577
10050 11:19:02.891716 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10051 11:19:02.892244 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10052 11:19:02.892665 Setting prompt string to ['asurada:']
10053 11:19:02.893054 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10054 11:19:02.893803 [0x00000040000000, 0x00000054600000)
10055 11:19:03.014275
10056 11:19:03.014834 [0x00000054660000, 0x00000080000000)
10057 11:19:03.274998
10058 11:19:03.275622 [0x000000821a7280, 0x000000ffe64000)
10059 11:19:04.019916
10060 11:19:04.020450 [0x00000100000000, 0x00000240000000)
10061 11:19:05.909709
10062 11:19:05.912605 Initializing XHCI USB controller at 0x11200000.
10063 11:19:06.951786
10064 11:19:06.954791 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10065 11:19:06.954880
10066 11:19:06.954945
10067 11:19:06.955005
10068 11:19:06.955281 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10070 11:19:07.055627 asurada: tftpboot 192.168.201.1 10591276/tftp-deploy-hycd9pjt/kernel/image.itb 10591276/tftp-deploy-hycd9pjt/kernel/cmdline
10071 11:19:07.055753 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10072 11:19:07.055853 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10073 11:19:07.059897 tftpboot 192.168.201.1 10591276/tftp-deploy-hycd9pjt/kernel/image.itp-deploy-hycd9pjt/kernel/cmdline
10074 11:19:07.059982
10075 11:19:07.060047 Waiting for link
10076 11:19:07.220704
10077 11:19:07.220828 R8152: Initializing
10078 11:19:07.220898
10079 11:19:07.223916 Version 6 (ocp_data = 5c30)
10080 11:19:07.223998
10081 11:19:07.227104 R8152: Done initializing
10082 11:19:07.227186
10083 11:19:07.227250 Adding net device
10084 11:19:09.318593
10085 11:19:09.318745 done.
10086 11:19:09.318815
10087 11:19:09.318885 MAC: 00:24:32:30:78:52
10088 11:19:09.318947
10089 11:19:09.321977 Sending DHCP discover... done.
10090 11:19:09.322061
10091 11:19:19.925647 Waiting for reply... R8152: Bulk read error 0xffffffbf
10092 11:19:19.925798
10093 11:19:19.929050 Receive failed.
10094 11:19:19.929134
10095 11:19:19.929197 done.
10096 11:19:19.929258
10097 11:19:19.932286 Sending DHCP request... done.
10098 11:19:19.932370
10099 11:19:19.935455 Waiting for reply... done.
10100 11:19:19.935528
10101 11:19:19.938704 My ip is 192.168.201.14
10102 11:19:19.938781
10103 11:19:19.942212 The DHCP server ip is 192.168.201.1
10104 11:19:19.942288
10105 11:19:19.945327 TFTP server IP predefined by user: 192.168.201.1
10106 11:19:19.945397
10107 11:19:19.952030 Bootfile predefined by user: 10591276/tftp-deploy-hycd9pjt/kernel/image.itb
10108 11:19:19.952122
10109 11:19:19.955346 Sending tftp read request... done.
10110 11:19:19.955458
10111 11:19:19.958587 Waiting for the transfer...
10112 11:19:19.958660
10113 11:19:20.513595 00000000 ################################################################
10114 11:19:20.513730
10115 11:19:21.064339 00080000 ################################################################
10116 11:19:21.064478
10117 11:19:21.612753 00100000 ################################################################
10118 11:19:21.612897
10119 11:19:22.161655 00180000 ################################################################
10120 11:19:22.161801
10121 11:19:22.712699 00200000 ################################################################
10122 11:19:22.712850
10123 11:19:23.260980 00280000 ################################################################
10124 11:19:23.261144
10125 11:19:23.809437 00300000 ################################################################
10126 11:19:23.809573
10127 11:19:24.360883 00380000 ################################################################
10128 11:19:24.361018
10129 11:19:24.914803 00400000 ################################################################
10130 11:19:24.914939
10131 11:19:25.479434 00480000 ################################################################
10132 11:19:25.479569
10133 11:19:26.023920 00500000 ################################################################
10134 11:19:26.024056
10135 11:19:26.576306 00580000 ################################################################
10136 11:19:26.576442
10137 11:19:27.130753 00600000 ################################################################
10138 11:19:27.130891
10139 11:19:27.690904 00680000 ################################################################
10140 11:19:27.691047
10141 11:19:28.243608 00700000 ################################################################
10142 11:19:28.243752
10143 11:19:28.797525 00780000 ################################################################
10144 11:19:28.797703
10145 11:19:29.346829 00800000 ################################################################
10146 11:19:29.346996
10147 11:19:29.891436 00880000 ################################################################
10148 11:19:29.891585
10149 11:19:30.435826 00900000 ################################################################
10150 11:19:30.435960
10151 11:19:30.986172 00980000 ################################################################
10152 11:19:30.986309
10153 11:19:31.538960 00a00000 ################################################################
10154 11:19:31.539097
10155 11:19:32.094030 00a80000 ################################################################
10156 11:19:32.094166
10157 11:19:32.660448 00b00000 ################################################################
10158 11:19:32.660590
10159 11:19:33.213876 00b80000 ################################################################
10160 11:19:33.214036
10161 11:19:33.764628 00c00000 ################################################################
10162 11:19:33.764765
10163 11:19:34.319245 00c80000 ################################################################
10164 11:19:34.319392
10165 11:19:34.866402 00d00000 ################################################################
10166 11:19:34.866540
10167 11:19:35.411111 00d80000 ################################################################
10168 11:19:35.411251
10169 11:19:35.959642 00e00000 ################################################################
10170 11:19:35.959782
10171 11:19:36.512042 00e80000 ################################################################
10172 11:19:36.512176
10173 11:19:37.069831 00f00000 ################################################################
10174 11:19:37.069970
10175 11:19:37.627863 00f80000 ################################################################
10176 11:19:37.628011
10177 11:19:38.187677 01000000 ################################################################
10178 11:19:38.187851
10179 11:19:38.739093 01080000 ################################################################
10180 11:19:38.739286
10181 11:19:39.290155 01100000 ################################################################
10182 11:19:39.290322
10183 11:19:39.839515 01180000 ################################################################
10184 11:19:39.839693
10185 11:19:40.387316 01200000 ################################################################
10186 11:19:40.387503
10187 11:19:40.936211 01280000 ################################################################
10188 11:19:40.936363
10189 11:19:41.496373 01300000 ################################################################
10190 11:19:41.496521
10191 11:19:42.054626 01380000 ################################################################
10192 11:19:42.054780
10193 11:19:42.616454 01400000 ################################################################
10194 11:19:42.616605
10195 11:19:43.178948 01480000 ################################################################
10196 11:19:43.179086
10197 11:19:43.722151 01500000 ################################################################
10198 11:19:43.722289
10199 11:19:44.277819 01580000 ################################################################
10200 11:19:44.277953
10201 11:19:44.827487 01600000 ################################################################
10202 11:19:44.827627
10203 11:19:45.381486 01680000 ################################################################
10204 11:19:45.381628
10205 11:19:45.935684 01700000 ################################################################
10206 11:19:45.935821
10207 11:19:46.488229 01780000 ################################################################
10208 11:19:46.488366
10209 11:19:47.067309 01800000 ################################################################
10210 11:19:47.067493
10211 11:19:47.643505 01880000 ################################################################
10212 11:19:47.643651
10213 11:19:48.194590 01900000 ################################################################
10214 11:19:48.194731
10215 11:19:48.753984 01980000 ################################################################
10216 11:19:48.754131
10217 11:19:49.304530 01a00000 ################################################################
10218 11:19:49.304671
10219 11:19:49.851104 01a80000 ################################################################
10220 11:19:49.851261
10221 11:19:50.402546 01b00000 ################################################################
10222 11:19:50.402699
10223 11:19:50.948843 01b80000 ################################################################
10224 11:19:50.948989
10225 11:19:51.493647 01c00000 ################################################################
10226 11:19:51.493795
10227 11:19:52.038857 01c80000 ################################################################
10228 11:19:52.039006
10229 11:19:52.588949 01d00000 ################################################################
10230 11:19:52.589096
10231 11:19:53.133827 01d80000 ################################################################
10232 11:19:53.133974
10233 11:19:53.692673 01e00000 ################################################################
10234 11:19:53.692804
10235 11:19:54.242383 01e80000 ################################################################
10236 11:19:54.242520
10237 11:19:54.794090 01f00000 ################################################################
10238 11:19:54.794226
10239 11:19:55.338625 01f80000 ################################################################
10240 11:19:55.338775
10241 11:19:55.880245 02000000 ################################################################
10242 11:19:55.880395
10243 11:19:56.424246 02080000 ################################################################
10244 11:19:56.424376
10245 11:19:56.967460 02100000 ################################################################
10246 11:19:56.967598
10247 11:19:57.507458 02180000 ################################################################
10248 11:19:57.507599
10249 11:19:58.055041 02200000 ################################################################
10250 11:19:58.055178
10251 11:19:58.621853 02280000 ################################################################
10252 11:19:58.621997
10253 11:19:59.177798 02300000 ################################################################
10254 11:19:59.177942
10255 11:19:59.731161 02380000 ################################################################
10256 11:19:59.731331
10257 11:20:00.281738 02400000 ################################################################
10258 11:20:00.281901
10259 11:20:00.829992 02480000 ################################################################
10260 11:20:00.830163
10261 11:20:01.436449 02500000 ################################################################
10262 11:20:01.437131
10263 11:20:02.157840 02580000 ################################################################
10264 11:20:02.158428
10265 11:20:02.876783 02600000 ################################################################
10266 11:20:02.877432
10267 11:20:03.590582 02680000 ################################################################
10268 11:20:03.591077
10269 11:20:04.289121 02700000 ################################################################
10270 11:20:04.289641
10271 11:20:04.932054 02780000 ################################################################
10272 11:20:04.932592
10273 11:20:05.666930 02800000 ################################################################
10274 11:20:05.667067
10275 11:20:06.301762 02880000 ################################################################
10276 11:20:06.301899
10277 11:20:06.853842 02900000 ################################################################
10278 11:20:06.853996
10279 11:20:07.449932 02980000 ################################################################
10280 11:20:07.450070
10281 11:20:08.031387 02a00000 ################################################################
10282 11:20:08.031520
10283 11:20:08.622645 02a80000 ################################################################
10284 11:20:08.622781
10285 11:20:09.224275 02b00000 ################################################################
10286 11:20:09.224420
10287 11:20:09.830187 02b80000 ################################################################
10288 11:20:09.830364
10289 11:20:10.417806 02c00000 ################################################################
10290 11:20:10.417957
10291 11:20:11.022743 02c80000 ################################################################
10292 11:20:11.022896
10293 11:20:11.624549 02d00000 ################################################################
10294 11:20:11.624708
10295 11:20:12.214872 02d80000 ################################################################
10296 11:20:12.215026
10297 11:20:12.817623 02e00000 ################################################################
10298 11:20:12.817777
10299 11:20:13.380937 02e80000 ################################################################
10300 11:20:13.381092
10301 11:20:13.982285 02f00000 ################################################################
10302 11:20:13.982441
10303 11:20:14.585216 02f80000 ################################################################
10304 11:20:14.585371
10305 11:20:15.190147 03000000 ################################################################
10306 11:20:15.190301
10307 11:20:15.793187 03080000 ################################################################
10308 11:20:15.793338
10309 11:20:16.394506 03100000 ################################################################
10310 11:20:16.394661
10311 11:20:16.980958 03180000 ################################################################
10312 11:20:16.981117
10313 11:20:17.573847 03200000 ################################################################
10314 11:20:17.574002
10315 11:20:18.169195 03280000 ################################################################
10316 11:20:18.169357
10317 11:20:18.764942 03300000 ################################################################
10318 11:20:18.765110
10319 11:20:19.369698 03380000 ################################################################
10320 11:20:19.369844
10321 11:20:19.959872 03400000 ################################################################
10322 11:20:19.960026
10323 11:20:20.550966 03480000 ################################################################
10324 11:20:20.551118
10325 11:20:21.144712 03500000 ################################################################
10326 11:20:21.144865
10327 11:20:21.750454 03580000 ################################################################
10328 11:20:21.750617
10329 11:20:22.343029 03600000 ################################################################
10330 11:20:22.343166
10331 11:20:22.950286 03680000 ################################################################
10332 11:20:22.950434
10333 11:20:23.586720 03700000 ################################################################
10334 11:20:23.587166
10335 11:20:24.296317 03780000 ################################################################
10336 11:20:24.296781
10337 11:20:25.010395 03800000 ################################################################
10338 11:20:25.010897
10339 11:20:25.709308 03880000 ################################################################
10340 11:20:25.709798
10341 11:20:26.446997 03900000 ################################################################
10342 11:20:26.447594
10343 11:20:27.190817 03980000 ################################################################
10344 11:20:27.191329
10345 11:20:27.940103 03a00000 ################################################################
10346 11:20:27.940621
10347 11:20:28.684875 03a80000 ################################################################
10348 11:20:28.685402
10349 11:20:29.431471 03b00000 ################################################################
10350 11:20:29.431990
10351 11:20:30.104401 03b80000 ################################################################
10352 11:20:30.105015
10353 11:20:30.794990 03c00000 ################################################################
10354 11:20:30.795576
10355 11:20:31.437432 03c80000 ################################################################
10356 11:20:31.437600
10357 11:20:32.135396 03d00000 ################################################################
10358 11:20:32.135891
10359 11:20:32.870119 03d80000 ################################################################
10360 11:20:32.870629
10361 11:20:33.616156 03e00000 ################################################################
10362 11:20:33.616717
10363 11:20:34.357109 03e80000 ################################################################
10364 11:20:34.357689
10365 11:20:34.990250 03f00000 ####################################################### done.
10366 11:20:34.990776
10367 11:20:34.993463 The bootfile was 66504802 bytes long.
10368 11:20:34.993897
10369 11:20:34.994235 Sending tftp read request... done.
10370 11:20:34.996453
10371 11:20:34.996876 Waiting for the transfer...
10372 11:20:34.997238
10373 11:20:34.999920 00000000 # done.
10374 11:20:35.000352
10375 11:20:35.006242 Command line loaded dynamically from TFTP file: 10591276/tftp-deploy-hycd9pjt/kernel/cmdline
10376 11:20:35.006777
10377 11:20:35.019593 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10378 11:20:35.020119
10379 11:20:35.020460 Loading FIT.
10380 11:20:35.020778
10381 11:20:35.022711 Image ramdisk-1 has 56369823 bytes.
10382 11:20:35.023140
10383 11:20:35.026208 Image fdt-1 has 46924 bytes.
10384 11:20:35.026734
10385 11:20:35.029359 Image kernel-1 has 10086024 bytes.
10386 11:20:35.029783
10387 11:20:35.036645 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10388 11:20:35.037182
10389 11:20:35.056139 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10390 11:20:35.056694
10391 11:20:35.059228 Choosing best match conf-1 for compat google,spherion-rev2.
10392 11:20:35.064482
10393 11:20:35.068782 Connected to device vid:did:rid of 1ae0:0028:00
10394 11:20:35.076194
10395 11:20:35.079322 tpm_get_response: command 0x17b, return code 0x0
10396 11:20:35.079800
10397 11:20:35.083206 ec_init: CrosEC protocol v3 supported (256, 248)
10398 11:20:35.086498
10399 11:20:35.090247 tpm_cleanup: add release locality here.
10400 11:20:35.090767
10401 11:20:35.091106 Shutting down all USB controllers.
10402 11:20:35.093024
10403 11:20:35.093446 Removing current net device
10404 11:20:35.093784
10405 11:20:35.100068 Exiting depthcharge with code 4 at timestamp: 121624340
10406 11:20:35.100600
10407 11:20:35.103403 LZMA decompressing kernel-1 to 0x821a6718
10408 11:20:35.103932
10409 11:20:35.106436 LZMA decompressing kernel-1 to 0x40000000
10410 11:20:36.373494
10411 11:20:36.374012 jumping to kernel
10412 11:20:36.375504 end: 2.2.4 bootloader-commands (duration 00:01:33) [common]
10413 11:20:36.375988 start: 2.2.5 auto-login-action (timeout 00:02:52) [common]
10414 11:20:36.376580 Setting prompt string to ['Linux version [0-9]']
10415 11:20:36.377002 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10416 11:20:36.377362 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10417 11:20:36.455382
10418 11:20:36.458268 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10419 11:20:36.462324 start: 2.2.5.1 login-action (timeout 00:02:52) [common]
10420 11:20:36.462792 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10421 11:20:36.463220 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10422 11:20:36.463686 Using line separator: #'\n'#
10423 11:20:36.464006 No login prompt set.
10424 11:20:36.464312 Parsing kernel messages
10425 11:20:36.464599 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10426 11:20:36.465125 [login-action] Waiting for messages, (timeout 00:02:52)
10427 11:20:36.481494 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1609115-arm64-gcc-10-defconfig-arm64-chromebook-dplkv) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 10:57:14 UTC 2023
10428 11:20:36.484726 [ 0.000000] random: crng init done
10429 11:20:36.487963 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10430 11:20:36.491142 [ 0.000000] efi: UEFI not found.
10431 11:20:36.501191 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10432 11:20:36.508062 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10433 11:20:36.517702 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10434 11:20:36.527762 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10435 11:20:36.534660 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10436 11:20:36.538176 [ 0.000000] printk: bootconsole [mtk8250] enabled
10437 11:20:36.546723 [ 0.000000] NUMA: No NUMA configuration found
10438 11:20:36.553291 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10439 11:20:36.559539 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10440 11:20:36.560061 [ 0.000000] Zone ranges:
10441 11:20:36.566796 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10442 11:20:36.570087 [ 0.000000] DMA32 empty
10443 11:20:36.576347 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10444 11:20:36.579657 [ 0.000000] Movable zone start for each node
10445 11:20:36.582971 [ 0.000000] Early memory node ranges
10446 11:20:36.589910 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10447 11:20:36.596349 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10448 11:20:36.602761 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10449 11:20:36.609807 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10450 11:20:36.616174 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10451 11:20:36.622688 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10452 11:20:36.679182 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10453 11:20:36.685352 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10454 11:20:36.691903 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10455 11:20:36.695771 [ 0.000000] psci: probing for conduit method from DT.
10456 11:20:36.702744 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10457 11:20:36.705524 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10458 11:20:36.712227 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10459 11:20:36.714906 [ 0.000000] psci: SMC Calling Convention v1.2
10460 11:20:36.722124 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10461 11:20:36.725472 [ 0.000000] Detected VIPT I-cache on CPU0
10462 11:20:36.732872 [ 0.000000] CPU features: detected: GIC system register CPU interface
10463 11:20:36.738759 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10464 11:20:36.745871 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10465 11:20:36.751966 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10466 11:20:36.758453 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10467 11:20:36.768381 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10468 11:20:36.771580 [ 0.000000] alternatives: applying boot alternatives
10469 11:20:36.778375 [ 0.000000] Fallback order for Node 0: 0
10470 11:20:36.784867 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10471 11:20:36.788194 [ 0.000000] Policy zone: Normal
10472 11:20:36.798992 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10473 11:20:36.808281 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10474 11:20:36.821112 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10475 11:20:36.831413 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10476 11:20:36.837473 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10477 11:20:36.841310 <6>[ 0.000000] software IO TLB: area num 8.
10478 11:20:36.898047 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10479 11:20:37.047130 <6>[ 0.000000] Memory: 7917892K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 434876K reserved, 32768K cma-reserved)
10480 11:20:37.053562 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10481 11:20:37.059503 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10482 11:20:37.063152 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10483 11:20:37.069415 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10484 11:20:37.076327 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10485 11:20:37.079826 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10486 11:20:37.089669 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10487 11:20:37.096376 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10488 11:20:37.099669 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10489 11:20:37.107645 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10490 11:20:37.110990 <6>[ 0.000000] GICv3: 608 SPIs implemented
10491 11:20:37.117503 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10492 11:20:37.120366 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10493 11:20:37.124224 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10494 11:20:37.133917 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10495 11:20:37.143719 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10496 11:20:37.157265 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10497 11:20:37.163735 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10498 11:20:37.172796 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10499 11:20:37.185779 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10500 11:20:37.192779 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10501 11:20:37.199270 <6>[ 0.009232] Console: colour dummy device 80x25
10502 11:20:37.209449 <6>[ 0.013987] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10503 11:20:37.216278 <6>[ 0.024494] pid_max: default: 32768 minimum: 301
10504 11:20:37.219533 <6>[ 0.029397] LSM: Security Framework initializing
10505 11:20:37.226219 <6>[ 0.034336] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10506 11:20:37.235599 <6>[ 0.042151] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10507 11:20:37.242298 <6>[ 0.051567] cblist_init_generic: Setting adjustable number of callback queues.
10508 11:20:37.249231 <6>[ 0.059021] cblist_init_generic: Setting shift to 3 and lim to 1.
10509 11:20:37.255501 <6>[ 0.065360] cblist_init_generic: Setting shift to 3 and lim to 1.
10510 11:20:37.262665 <6>[ 0.071806] rcu: Hierarchical SRCU implementation.
10511 11:20:37.268669 <6>[ 0.076820] rcu: Max phase no-delay instances is 1000.
10512 11:20:37.272256 <6>[ 0.083840] EFI services will not be available.
10513 11:20:37.278923 <6>[ 0.088816] smp: Bringing up secondary CPUs ...
10514 11:20:37.286036 <6>[ 0.093868] Detected VIPT I-cache on CPU1
10515 11:20:37.292711 <6>[ 0.093940] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10516 11:20:37.299504 <6>[ 0.093972] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10517 11:20:37.302873 <6>[ 0.094306] Detected VIPT I-cache on CPU2
10518 11:20:37.309654 <6>[ 0.094358] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10519 11:20:37.319793 <6>[ 0.094374] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10520 11:20:37.322550 <6>[ 0.094632] Detected VIPT I-cache on CPU3
10521 11:20:37.328877 <6>[ 0.094677] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10522 11:20:37.335755 <6>[ 0.094691] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10523 11:20:37.339425 <6>[ 0.094998] CPU features: detected: Spectre-v4
10524 11:20:37.345565 <6>[ 0.095004] CPU features: detected: Spectre-BHB
10525 11:20:37.349429 <6>[ 0.095010] Detected PIPT I-cache on CPU4
10526 11:20:37.356211 <6>[ 0.095067] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10527 11:20:37.362592 <6>[ 0.095084] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10528 11:20:37.368844 <6>[ 0.095376] Detected PIPT I-cache on CPU5
10529 11:20:37.375801 <6>[ 0.095440] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10530 11:20:37.381692 <6>[ 0.095456] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10531 11:20:37.385376 <6>[ 0.095737] Detected PIPT I-cache on CPU6
10532 11:20:37.391961 <6>[ 0.095802] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10533 11:20:37.398900 <6>[ 0.095818] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10534 11:20:37.405164 <6>[ 0.096116] Detected PIPT I-cache on CPU7
10535 11:20:37.411928 <6>[ 0.096181] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10536 11:20:37.418490 <6>[ 0.096198] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10537 11:20:37.421955 <6>[ 0.096245] smp: Brought up 1 node, 8 CPUs
10538 11:20:37.428051 <6>[ 0.237486] SMP: Total of 8 processors activated.
10539 11:20:37.432269 <6>[ 0.242407] CPU features: detected: 32-bit EL0 Support
10540 11:20:37.441742 <6>[ 0.247770] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10541 11:20:37.448576 <6>[ 0.256570] CPU features: detected: Common not Private translations
10542 11:20:37.455297 <6>[ 0.263086] CPU features: detected: CRC32 instructions
10543 11:20:37.458252 <6>[ 0.268437] CPU features: detected: RCpc load-acquire (LDAPR)
10544 11:20:37.465109 <6>[ 0.274396] CPU features: detected: LSE atomic instructions
10545 11:20:37.471473 <6>[ 0.280177] CPU features: detected: Privileged Access Never
10546 11:20:37.478768 <6>[ 0.285957] CPU features: detected: RAS Extension Support
10547 11:20:37.484689 <6>[ 0.291565] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10548 11:20:37.488012 <6>[ 0.298829] CPU: All CPU(s) started at EL2
10549 11:20:37.494890 <6>[ 0.303172] alternatives: applying system-wide alternatives
10550 11:20:37.503897 <6>[ 0.313901] devtmpfs: initialized
10551 11:20:37.519562 <6>[ 0.322911] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10552 11:20:37.526333 <6>[ 0.332873] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10553 11:20:37.532982 <6>[ 0.341084] pinctrl core: initialized pinctrl subsystem
10554 11:20:37.536008 <6>[ 0.347747] DMI not present or invalid.
10555 11:20:37.543076 <6>[ 0.352155] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10556 11:20:37.553103 <6>[ 0.359051] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10557 11:20:37.559821 <6>[ 0.366631] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10558 11:20:37.569762 <6>[ 0.374862] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10559 11:20:37.572858 <6>[ 0.383105] audit: initializing netlink subsys (disabled)
10560 11:20:37.582365 <5>[ 0.388801] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10561 11:20:37.589012 <6>[ 0.389508] thermal_sys: Registered thermal governor 'step_wise'
10562 11:20:37.595317 <6>[ 0.396761] thermal_sys: Registered thermal governor 'power_allocator'
10563 11:20:37.599133 <6>[ 0.403013] cpuidle: using governor menu
10564 11:20:37.605478 <6>[ 0.413972] NET: Registered PF_QIPCRTR protocol family
10565 11:20:37.612437 <6>[ 0.419448] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10566 11:20:37.619496 <6>[ 0.426551] ASID allocator initialised with 32768 entries
10567 11:20:37.621785 <6>[ 0.433138] Serial: AMBA PL011 UART driver
10568 11:20:37.631721 <4>[ 0.441743] Trying to register duplicate clock ID: 134
10569 11:20:37.685877 <6>[ 0.499339] KASLR enabled
10570 11:20:37.700922 <6>[ 0.507096] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10571 11:20:37.706951 <6>[ 0.514112] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10572 11:20:37.713854 <6>[ 0.520601] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10573 11:20:37.720423 <6>[ 0.527606] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10574 11:20:37.726634 <6>[ 0.534094] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10575 11:20:37.733764 <6>[ 0.541098] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10576 11:20:37.740295 <6>[ 0.547588] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10577 11:20:37.746617 <6>[ 0.554591] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10578 11:20:37.750200 <6>[ 0.562106] ACPI: Interpreter disabled.
10579 11:20:37.758821 <6>[ 0.568498] iommu: Default domain type: Translated
10580 11:20:37.765240 <6>[ 0.573611] iommu: DMA domain TLB invalidation policy: strict mode
10581 11:20:37.768323 <5>[ 0.580262] SCSI subsystem initialized
10582 11:20:37.775485 <6>[ 0.584427] usbcore: registered new interface driver usbfs
10583 11:20:37.781926 <6>[ 0.590160] usbcore: registered new interface driver hub
10584 11:20:37.784679 <6>[ 0.595714] usbcore: registered new device driver usb
10585 11:20:37.791589 <6>[ 0.601796] pps_core: LinuxPPS API ver. 1 registered
10586 11:20:37.801837 <6>[ 0.606991] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10587 11:20:37.805381 <6>[ 0.616335] PTP clock support registered
10588 11:20:37.808220 <6>[ 0.620576] EDAC MC: Ver: 3.0.0
10589 11:20:37.815603 <6>[ 0.625725] FPGA manager framework
10590 11:20:37.822385 <6>[ 0.629406] Advanced Linux Sound Architecture Driver Initialized.
10591 11:20:37.825652 <6>[ 0.636176] vgaarb: loaded
10592 11:20:37.832487 <6>[ 0.639341] clocksource: Switched to clocksource arch_sys_counter
10593 11:20:37.835600 <5>[ 0.645774] VFS: Disk quotas dquot_6.6.0
10594 11:20:37.842545 <6>[ 0.649956] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10595 11:20:37.845419 <6>[ 0.657142] pnp: PnP ACPI: disabled
10596 11:20:37.854172 <6>[ 0.663894] NET: Registered PF_INET protocol family
10597 11:20:37.863635 <6>[ 0.669497] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10598 11:20:37.875277 <6>[ 0.681802] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10599 11:20:37.884922 <6>[ 0.690617] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10600 11:20:37.892038 <6>[ 0.698588] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10601 11:20:37.898125 <6>[ 0.707283] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10602 11:20:37.910264 <6>[ 0.717023] TCP: Hash tables configured (established 65536 bind 65536)
10603 11:20:37.916691 <6>[ 0.723879] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10604 11:20:37.923422 <6>[ 0.731074] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10605 11:20:37.930259 <6>[ 0.738774] NET: Registered PF_UNIX/PF_LOCAL protocol family
10606 11:20:37.936628 <6>[ 0.744951] RPC: Registered named UNIX socket transport module.
10607 11:20:37.940614 <6>[ 0.751106] RPC: Registered udp transport module.
10608 11:20:37.946921 <6>[ 0.756041] RPC: Registered tcp transport module.
10609 11:20:37.953580 <6>[ 0.760973] RPC: Registered tcp NFSv4.1 backchannel transport module.
10610 11:20:37.957014 <6>[ 0.767641] PCI: CLS 0 bytes, default 64
10611 11:20:37.960272 <6>[ 0.772037] Unpacking initramfs...
10612 11:20:37.970291 <6>[ 0.775871] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10613 11:20:37.976471 <6>[ 0.784539] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10614 11:20:37.983432 <6>[ 0.793379] kvm [1]: IPA Size Limit: 40 bits
10615 11:20:37.986495 <6>[ 0.797906] kvm [1]: GICv3: no GICV resource entry
10616 11:20:37.993525 <6>[ 0.802930] kvm [1]: disabling GICv2 emulation
10617 11:20:37.999802 <6>[ 0.807618] kvm [1]: GIC system register CPU interface enabled
10618 11:20:38.003066 <6>[ 0.813787] kvm [1]: vgic interrupt IRQ18
10619 11:20:38.009715 <6>[ 0.818146] kvm [1]: VHE mode initialized successfully
10620 11:20:38.013037 <5>[ 0.824576] Initialise system trusted keyrings
10621 11:20:38.019765 <6>[ 0.829356] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10622 11:20:38.029664 <6>[ 0.839390] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10623 11:20:38.035791 <5>[ 0.845775] NFS: Registering the id_resolver key type
10624 11:20:38.039257 <5>[ 0.851092] Key type id_resolver registered
10625 11:20:38.046207 <5>[ 0.855507] Key type id_legacy registered
10626 11:20:38.052473 <6>[ 0.859785] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10627 11:20:38.059501 <6>[ 0.866708] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10628 11:20:38.065366 <6>[ 0.874453] 9p: Installing v9fs 9p2000 file system support
10629 11:20:38.103218 <5>[ 0.913112] Key type asymmetric registered
10630 11:20:38.106794 <5>[ 0.917446] Asymmetric key parser 'x509' registered
10631 11:20:38.116798 <6>[ 0.922608] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10632 11:20:38.119848 <6>[ 0.930223] io scheduler mq-deadline registered
10633 11:20:38.123179 <6>[ 0.934987] io scheduler kyber registered
10634 11:20:38.141856 <6>[ 0.951902] EINJ: ACPI disabled.
10635 11:20:38.174223 <4>[ 0.977385] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10636 11:20:38.184044 <4>[ 0.988037] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10637 11:20:38.198806 <6>[ 1.008590] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10638 11:20:38.206508 <6>[ 1.016562] printk: console [ttyS0] disabled
10639 11:20:38.234823 <6>[ 1.041221] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10640 11:20:38.241198 <6>[ 1.050693] printk: console [ttyS0] enabled
10641 11:20:38.244695 <6>[ 1.050693] printk: console [ttyS0] enabled
10642 11:20:38.251890 <6>[ 1.059588] printk: bootconsole [mtk8250] disabled
10643 11:20:38.254280 <6>[ 1.059588] printk: bootconsole [mtk8250] disabled
10644 11:20:38.260708 <6>[ 1.070753] SuperH (H)SCI(F) driver initialized
10645 11:20:38.264246 <6>[ 1.076026] msm_serial: driver initialized
10646 11:20:38.278181 <6>[ 1.084952] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10647 11:20:38.287882 <6>[ 1.093499] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10648 11:20:38.294912 <6>[ 1.102042] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10649 11:20:38.304829 <6>[ 1.110670] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10650 11:20:38.314666 <6>[ 1.119378] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10651 11:20:38.321511 <6>[ 1.128092] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10652 11:20:38.330955 <6>[ 1.136635] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10653 11:20:38.337988 <6>[ 1.145445] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10654 11:20:38.347537 <6>[ 1.153991] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10655 11:20:38.359094 <6>[ 1.169501] loop: module loaded
10656 11:20:38.366118 <6>[ 1.175504] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10657 11:20:38.388195 <4>[ 1.198828] mtk-pmic-keys: Failed to locate of_node [id: -1]
10658 11:20:38.395388 <6>[ 1.205627] megasas: 07.719.03.00-rc1
10659 11:20:38.404784 <6>[ 1.215137] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10660 11:20:38.412382 <6>[ 1.222717] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10661 11:20:38.428927 <6>[ 1.239431] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10662 11:20:38.489781 <6>[ 1.293148] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10663 11:20:40.349082 <6>[ 3.159701] Freeing initrd memory: 55044K
10664 11:20:40.359296 <6>[ 3.170122] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10665 11:20:40.370086 <6>[ 3.181077] tun: Universal TUN/TAP device driver, 1.6
10666 11:20:40.373860 <6>[ 3.187127] thunder_xcv, ver 1.0
10667 11:20:40.376757 <6>[ 3.190631] thunder_bgx, ver 1.0
10668 11:20:40.380111 <6>[ 3.194127] nicpf, ver 1.0
10669 11:20:40.390732 <6>[ 3.198120] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10670 11:20:40.393890 <6>[ 3.205595] hns3: Copyright (c) 2017 Huawei Corporation.
10671 11:20:40.400556 <6>[ 3.211182] hclge is initializing
10672 11:20:40.403910 <6>[ 3.214767] e1000: Intel(R) PRO/1000 Network Driver
10673 11:20:40.410604 <6>[ 3.219897] e1000: Copyright (c) 1999-2006 Intel Corporation.
10674 11:20:40.413977 <6>[ 3.225911] e1000e: Intel(R) PRO/1000 Network Driver
10675 11:20:40.420310 <6>[ 3.231127] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10676 11:20:40.427493 <6>[ 3.237314] igb: Intel(R) Gigabit Ethernet Network Driver
10677 11:20:40.433660 <6>[ 3.242964] igb: Copyright (c) 2007-2014 Intel Corporation.
10678 11:20:40.440071 <6>[ 3.248800] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10679 11:20:40.447051 <6>[ 3.255318] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10680 11:20:40.450297 <6>[ 3.261782] sky2: driver version 1.30
10681 11:20:40.456937 <6>[ 3.266759] VFIO - User Level meta-driver version: 0.3
10682 11:20:40.464327 <6>[ 3.274907] usbcore: registered new interface driver usb-storage
10683 11:20:40.470630 <6>[ 3.281350] usbcore: registered new device driver onboard-usb-hub
10684 11:20:40.479655 <6>[ 3.290347] mt6397-rtc mt6359-rtc: registered as rtc0
10685 11:20:40.489214 <6>[ 3.295811] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-05T11:20:40 UTC (1685964040)
10686 11:20:40.492599 <6>[ 3.305367] i2c_dev: i2c /dev entries driver
10687 11:20:40.509269 <6>[ 3.317013] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10688 11:20:40.516660 <6>[ 3.327203] sdhci: Secure Digital Host Controller Interface driver
10689 11:20:40.523289 <6>[ 3.333642] sdhci: Copyright(c) Pierre Ossman
10690 11:20:40.529645 <6>[ 3.339043] Synopsys Designware Multimedia Card Interface Driver
10691 11:20:40.532771 <6>[ 3.345673] mmc0: CQHCI version 5.10
10692 11:20:40.540044 <6>[ 3.346194] sdhci-pltfm: SDHCI platform and OF driver helper
10693 11:20:40.546492 <6>[ 3.357599] ledtrig-cpu: registered to indicate activity on CPUs
10694 11:20:40.557569 <6>[ 3.364923] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10695 11:20:40.560894 <6>[ 3.372320] usbcore: registered new interface driver usbhid
10696 11:20:40.567254 <6>[ 3.378147] usbhid: USB HID core driver
10697 11:20:40.573611 <6>[ 3.382400] spi_master spi0: will run message pump with realtime priority
10698 11:20:40.619616 <6>[ 3.423626] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10699 11:20:40.638330 <6>[ 3.438935] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10700 11:20:40.641658 <6>[ 3.452506] mmc0: Command Queue Engine enabled
10701 11:20:40.649118 <6>[ 3.454150] cros-ec-spi spi0.0: Chrome EC device registered
10702 11:20:40.652426 <6>[ 3.457272] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10703 11:20:40.659706 <6>[ 3.470374] mmcblk0: mmc0:0001 DA4128 116 GiB
10704 11:20:40.672689 <6>[ 3.480348] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10705 11:20:40.679647 <6>[ 3.484772] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10706 11:20:40.685997 <6>[ 3.491764] NET: Registered PF_PACKET protocol family
10707 11:20:40.689970 <6>[ 3.496893] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10708 11:20:40.696009 <6>[ 3.501008] 9pnet: Installing 9P2000 support
10709 11:20:40.699195 <6>[ 3.506769] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10710 11:20:40.706314 <5>[ 3.510677] Key type dns_resolver registered
10711 11:20:40.712694 <6>[ 3.516511] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10712 11:20:40.715955 <6>[ 3.520991] registered taskstats version 1
10713 11:20:40.718809 <5>[ 3.531287] Loading compiled-in X.509 certificates
10714 11:20:40.753902 <4>[ 3.558062] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10715 11:20:40.763654 <4>[ 3.568768] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10716 11:20:40.773743 <3>[ 3.581529] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10717 11:20:40.785917 <6>[ 3.597002] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10718 11:20:40.793222 <6>[ 3.603795] xhci-mtk 11200000.usb: xHCI Host Controller
10719 11:20:40.799721 <6>[ 3.609296] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10720 11:20:40.809306 <6>[ 3.617160] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10721 11:20:40.816065 <6>[ 3.626601] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10722 11:20:40.822819 <6>[ 3.632790] xhci-mtk 11200000.usb: xHCI Host Controller
10723 11:20:40.829753 <6>[ 3.638285] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10724 11:20:40.835643 <6>[ 3.645947] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10725 11:20:40.842961 <6>[ 3.653828] hub 1-0:1.0: USB hub found
10726 11:20:40.846122 <6>[ 3.657863] hub 1-0:1.0: 1 port detected
10727 11:20:40.856091 <6>[ 3.662224] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10728 11:20:40.859532 <6>[ 3.671029] hub 2-0:1.0: USB hub found
10729 11:20:40.862892 <6>[ 3.675064] hub 2-0:1.0: 1 port detected
10730 11:20:40.871377 <6>[ 3.682380] mtk-msdc 11f70000.mmc: Got CD GPIO
10731 11:20:40.888861 <6>[ 3.696248] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10732 11:20:40.895838 <6>[ 3.704277] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10733 11:20:40.905316 <4>[ 3.712241] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10734 11:20:40.915506 <6>[ 3.721905] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10735 11:20:40.921620 <6>[ 3.729986] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10736 11:20:40.928426 <6>[ 3.738004] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10737 11:20:40.938319 <6>[ 3.745919] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10738 11:20:40.945051 <6>[ 3.753741] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10739 11:20:40.954869 <6>[ 3.761568] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10740 11:20:40.964782 <6>[ 3.772383] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10741 11:20:40.974866 <6>[ 3.780755] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10742 11:20:40.981259 <6>[ 3.789098] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10743 11:20:40.991087 <6>[ 3.797440] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10744 11:20:40.998019 <6>[ 3.805786] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10745 11:20:41.008060 <6>[ 3.814129] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10746 11:20:41.014660 <6>[ 3.822471] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10747 11:20:41.024461 <6>[ 3.830816] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10748 11:20:41.031044 <6>[ 3.839158] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10749 11:20:41.040537 <6>[ 3.847501] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10750 11:20:41.047575 <6>[ 3.855845] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10751 11:20:41.056954 <6>[ 3.864188] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10752 11:20:41.064007 <6>[ 3.872532] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10753 11:20:41.073571 <6>[ 3.880875] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10754 11:20:41.080506 <6>[ 3.889222] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10755 11:20:41.087442 <6>[ 3.898150] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10756 11:20:41.094528 <6>[ 3.905596] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10757 11:20:41.101722 <6>[ 3.912640] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10758 11:20:41.112208 <6>[ 3.919746] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10759 11:20:41.118984 <6>[ 3.927028] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10760 11:20:41.128792 <6>[ 3.933932] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10761 11:20:41.135060 <6>[ 3.943075] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10762 11:20:41.145272 <6>[ 3.952203] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10763 11:20:41.154902 <6>[ 3.961504] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10764 11:20:41.165038 <6>[ 3.970978] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10765 11:20:41.174947 <6>[ 3.980452] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10766 11:20:41.181456 <6>[ 3.989586] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10767 11:20:41.191558 <6>[ 3.999060] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10768 11:20:41.201449 <6>[ 4.008186] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10769 11:20:41.211930 <6>[ 4.017498] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10770 11:20:41.221433 <6>[ 4.027665] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10771 11:20:41.231934 <6>[ 4.039611] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10772 11:20:41.251607 <6>[ 4.059591] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10773 11:20:41.278689 <6>[ 4.089604] hub 2-1:1.0: USB hub found
10774 11:20:41.282050 <6>[ 4.093971] hub 2-1:1.0: 3 ports detected
10775 11:20:41.403674 <6>[ 4.211586] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10776 11:20:41.557186 <6>[ 4.367953] hub 1-1:1.0: USB hub found
10777 11:20:41.559989 <6>[ 4.372291] hub 1-1:1.0: 4 ports detected
10778 11:20:41.636372 <6>[ 4.443848] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10779 11:20:41.879832 <6>[ 4.687612] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10780 11:20:42.013066 <6>[ 4.823870] hub 1-1.4:1.0: USB hub found
10781 11:20:42.016454 <6>[ 4.828527] hub 1-1.4:1.0: 2 ports detected
10782 11:20:42.316354 <6>[ 5.123613] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10783 11:20:42.507769 <6>[ 5.315613] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10784 11:20:53.516433 <6>[ 16.332161] ALSA device list:
10785 11:20:53.523168 <6>[ 16.335418] No soundcards found.
10786 11:20:53.535222 <6>[ 16.347872] Freeing unused kernel memory: 8384K
10787 11:20:53.538695 <6>[ 16.352804] Run /init as init process
10788 11:20:53.569351 <6>[ 16.381602] NET: Registered PF_INET6 protocol family
10789 11:20:53.575934 <6>[ 16.388149] Segment Routing with IPv6
10790 11:20:53.578890 <6>[ 16.392109] In-situ OAM (IOAM) with IPv6
10791 11:20:53.613494 <30>[ 16.406189] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10792 11:20:53.616855 <30>[ 16.429946] systemd[1]: Detected architecture arm64.
10793 11:20:53.616964
10794 11:20:53.623530 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10795 11:20:53.623613
10796 11:20:53.639202 <30>[ 16.451739] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10797 11:20:53.773501 <30>[ 16.582889] systemd[1]: Queued start job for default target Graphical Interface.
10798 11:20:53.816483 <30>[ 16.628981] systemd[1]: Created slice system-getty.slice.
10799 11:20:53.823012 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10800 11:20:53.839997 <30>[ 16.652171] systemd[1]: Created slice system-modprobe.slice.
10801 11:20:53.846206 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10802 11:20:53.864316 <30>[ 16.676747] systemd[1]: Created slice system-serial\x2dgetty.slice.
10803 11:20:53.874448 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10804 11:20:53.887619 <30>[ 16.700115] systemd[1]: Created slice User and Session Slice.
10805 11:20:53.894570 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10806 11:20:53.915036 <30>[ 16.724174] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10807 11:20:53.925051 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10808 11:20:53.942388 <30>[ 16.751783] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10809 11:20:53.949100 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10810 11:20:53.969983 <30>[ 16.775705] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10811 11:20:53.976684 <30>[ 16.787738] systemd[1]: Reached target Local Encrypted Volumes.
10812 11:20:53.983737 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10813 11:20:53.999524 <30>[ 16.811706] systemd[1]: Reached target Paths.
10814 11:20:54.002575 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10815 11:20:54.019264 <30>[ 16.831648] systemd[1]: Reached target Remote File Systems.
10816 11:20:54.025634 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10817 11:20:54.043793 <30>[ 16.855894] systemd[1]: Reached target Slices.
10818 11:20:54.049670 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10819 11:20:54.062967 <30>[ 16.875674] systemd[1]: Reached target Swap.
10820 11:20:54.066285 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10821 11:20:54.086602 <30>[ 16.895999] systemd[1]: Listening on initctl Compatibility Named Pipe.
10822 11:20:54.093281 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10823 11:20:54.100228 <30>[ 16.910735] systemd[1]: Listening on Journal Audit Socket.
10824 11:20:54.106287 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10825 11:20:54.119226 <30>[ 16.931888] systemd[1]: Listening on Journal Socket (/dev/log).
10826 11:20:54.126055 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10827 11:20:54.143373 <30>[ 16.955927] systemd[1]: Listening on Journal Socket.
10828 11:20:54.149577 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10829 11:20:54.163526 <30>[ 16.975927] systemd[1]: Listening on udev Control Socket.
10830 11:20:54.170036 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10831 11:20:54.187853 <30>[ 17.000276] systemd[1]: Listening on udev Kernel Socket.
10832 11:20:54.194262 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10833 11:20:54.231585 <30>[ 17.043855] systemd[1]: Mounting Huge Pages File System...
10834 11:20:54.238071 Mounting [0;1;39mHuge Pages File System[0m...
10835 11:20:54.253272 <30>[ 17.065615] systemd[1]: Mounting POSIX Message Queue File System...
10836 11:20:54.259791 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10837 11:20:54.276864 <30>[ 17.089595] systemd[1]: Mounting Kernel Debug File System...
10838 11:20:54.283838 Mounting [0;1;39mKernel Debug File System[0m...
10839 11:20:54.302994 <30>[ 17.111920] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10840 11:20:54.342846 <30>[ 17.152120] systemd[1]: Starting Create list of static device nodes for the current kernel...
10841 11:20:54.349639 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10842 11:20:54.369644 <30>[ 17.181916] systemd[1]: Starting Load Kernel Module configfs...
10843 11:20:54.375921 Starting [0;1;39mLoad Kernel Module configfs[0m...
10844 11:20:54.393239 <30>[ 17.205817] systemd[1]: Starting Load Kernel Module drm...
10845 11:20:54.399824 Starting [0;1;39mLoad Kernel Module drm[0m...
10846 11:20:54.418507 <30>[ 17.227832] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10847 11:20:54.429326 <30>[ 17.241419] systemd[1]: Starting Journal Service...
10848 11:20:54.432098 Starting [0;1;39mJournal Service[0m...
10849 11:20:54.449987 <30>[ 17.262225] systemd[1]: Starting Load Kernel Modules...
10850 11:20:54.456563 Starting [0;1;39mLoad Kernel Modules[0m...
10851 11:20:54.477386 <30>[ 17.286419] systemd[1]: Starting Remount Root and Kernel File Systems...
10852 11:20:54.483828 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10853 11:20:54.502029 <30>[ 17.314296] systemd[1]: Starting Coldplug All udev Devices...
10854 11:20:54.508722 Starting [0;1;39mColdplug All udev Devices[0m...
10855 11:20:54.525636 <30>[ 17.338391] systemd[1]: Mounted Huge Pages File System.
10856 11:20:54.532542 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10857 11:20:54.547996 <30>[ 17.360435] systemd[1]: Started Journal Service.
10858 11:20:54.554814 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10859 11:20:54.569262 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10860 11:20:54.584023 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10861 11:20:54.603917 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10862 11:20:54.621058 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10863 11:20:54.637005 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10864 11:20:54.652402 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10865 11:20:54.675770 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10866 11:20:54.694824 See 'systemctl status systemd-remount-fs.service' for details.
10867 11:20:54.752015 Mounting [0;1;39mKernel Configuration File System[0m...
10868 11:20:54.774341 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10869 11:20:54.791589 <46>[ 17.600852] systemd-journald[178]: Received client request to flush runtime journal.
10870 11:20:54.800688 Starting [0;1;39mLoad/Save Random Seed[0m...
10871 11:20:54.818454 Starting [0;1;39mApply Kernel Variables[0m...
10872 11:20:54.838208 Starting [0;1;39mCreate System Users[0m...
10873 11:20:54.856663 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10874 11:20:54.879923 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10875 11:20:54.892461 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10876 11:20:54.908425 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10877 11:20:54.928288 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10878 11:20:54.944516 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10879 11:20:54.995578 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10880 11:20:55.017679 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10881 11:20:55.031528 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10882 11:20:55.051126 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10883 11:20:55.103651 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10884 11:20:55.126967 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10885 11:20:55.144871 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10886 11:20:55.164485 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10887 11:20:55.224741 Starting [0;1;39mNetwork Time Synchronization[0m...
10888 11:20:55.245826 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10889 11:20:55.287213 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10890 11:20:55.332844 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10891 11:20:55.347817 <6>[ 18.157256] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10892 11:20:55.356835 <6>[ 18.169480] remoteproc remoteproc0: scp is available
10893 11:20:55.366603 <4>[ 18.174899] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10894 11:20:55.373319 <6>[ 18.184770] remoteproc remoteproc0: powering up scp
10895 11:20:55.383288 <4>[ 18.190314] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10896 11:20:55.390078 <3>[ 18.200769] remoteproc remoteproc0: request_firmware failed: -2
10897 11:20:55.399633 <3>[ 18.208506] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10898 11:20:55.406529 <3>[ 18.216833] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10899 11:20:55.416429 <3>[ 18.224981] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10900 11:20:55.422912 Startin<6>[ 18.228014] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10901 11:20:55.432865 g [0;1;39mLoad/<6>[ 18.232046] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10902 11:20:55.442483 Save Screen …o<6>[ 18.251475] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10903 11:20:55.452461 f leds:white:kbd<6>[ 18.261339] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10904 11:20:55.462566 <3>[ 18.262735] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10905 11:20:55.472616 _backlight[0m..<3>[ 18.279502] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10906 11:20:55.472694 .
10907 11:20:55.478800 <4>[ 18.281693] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10908 11:20:55.485486 <4>[ 18.281693] Fallback method does not support PEC.
10909 11:20:55.491818 <3>[ 18.288981] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10910 11:20:55.502423 <4>[ 18.304522] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10911 11:20:55.508624 <3>[ 18.311296] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10912 11:20:55.518464 <3>[ 18.311308] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10913 11:20:55.528423 [[0;32m OK [<3>[ 18.336017] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10914 11:20:55.535065 0m] Started [0;<6>[ 18.338598] mc: Linux media interface: v0.10
10915 11:20:55.542010 <4>[ 18.340155] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10916 11:20:55.551486 1;39mNetwork Tim<3>[ 18.349889] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10917 11:20:55.558067 e Synchronizatio<6>[ 18.360785] usbcore: registered new interface driver r8152
10918 11:20:55.558146 n[0m.
10919 11:20:55.564728 <3>[ 18.368072] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10920 11:20:55.574790 <6>[ 18.368121] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10921 11:20:55.584594 <6>[ 18.375343] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10922 11:20:55.595087 <3>[ 18.383832] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10923 11:20:55.598284 <6>[ 18.387682] videodev: Linux video capture interface: v2.00
10924 11:20:55.605102 <6>[ 18.392928] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10925 11:20:55.611559 <6>[ 18.392942] pci_bus 0000:00: root bus resource [bus 00-ff]
10926 11:20:55.618445 <6>[ 18.392951] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10927 11:20:55.628450 <6>[ 18.392957] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10928 11:20:55.635821 <6>[ 18.392996] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10929 11:20:55.642249 <6>[ 18.393017] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10930 11:20:55.648869 <6>[ 18.393108] pci 0000:00:00.0: supports D1 D2
10931 11:20:55.655578 <6>[ 18.393115] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10932 11:20:55.662179 <6>[ 18.394997] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10933 11:20:55.672219 <3>[ 18.409379] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10934 11:20:55.678767 <3>[ 18.411193] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10935 11:20:55.685492 <6>[ 18.412596] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10936 11:20:55.695163 <3>[ 18.417197] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10937 11:20:55.702004 <6>[ 18.424032] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10938 11:20:55.708267 <6>[ 18.424057] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10939 11:20:55.714782 <6>[ 18.424076] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10940 11:20:55.722214 <6>[ 18.424210] pci 0000:01:00.0: supports D1 D2
10941 11:20:55.728115 <3>[ 18.429867] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10942 11:20:55.735172 <6>[ 18.432061] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10943 11:20:55.741449 <6>[ 18.437162] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10944 11:20:55.751642 <3>[ 18.446873] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10945 11:20:55.761973 <3>[ 18.449057] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10946 11:20:55.768752 <3>[ 18.449899] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10947 11:20:55.778796 <4>[ 18.455300] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10948 11:20:55.785972 <3>[ 18.460604] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10949 11:20:55.793356 <3>[ 18.460679] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10950 11:20:55.802902 <4>[ 18.465177] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10951 11:20:55.809882 <6>[ 18.467412] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10952 11:20:55.816666 <6>[ 18.467453] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10953 11:20:55.826647 <6>[ 18.467461] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10954 11:20:55.833557 <6>[ 18.467475] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10955 11:20:55.840029 <6>[ 18.467491] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10956 11:20:55.850578 <6>[ 18.467507] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10957 11:20:55.854127 <6>[ 18.467522] pci 0000:00:00.0: PCI bridge to [bus 01]
10958 11:20:55.864061 <6>[ 18.467530] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10959 11:20:55.870652 <6>[ 18.467702] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10960 11:20:55.873952 <6>[ 18.468574] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10961 11:20:55.880784 <6>[ 18.469075] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10962 11:20:55.890829 <6>[ 18.497452] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10963 11:20:55.894296 <6>[ 18.551402] r8152 2-1.3:1.0 eth0: v1.12.13
10964 11:20:55.901260 <6>[ 18.569832] usbcore: registered new interface driver cdc_ether
10965 11:20:55.907578 <5>[ 18.580839] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10966 11:20:55.915063 <6>[ 18.596568] usbcore: registered new interface driver r8153_ecm
10967 11:20:55.918589 <6>[ 18.604916] Bluetooth: Core ver 2.22
10968 11:20:55.928075 <3>[ 18.605153] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10969 11:20:55.934872 <3>[ 18.605996] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10970 11:20:55.944946 <3>[ 18.610768] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10971 11:20:55.951385 <6>[ 18.614434] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10972 11:20:55.957797 <6>[ 18.620735] NET: Registered PF_BLUETOOTH protocol family
10973 11:20:55.964428 <6>[ 18.621091] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10974 11:20:55.971174 <5>[ 18.621202] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10975 11:20:55.981226 <4>[ 18.621355] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10976 11:20:55.984892 <6>[ 18.621365] cfg80211: failed to load regulatory.db
10977 11:20:55.991060 <6>[ 18.625767] remoteproc remoteproc0: powering up scp
10978 11:20:56.000963 <4>[ 18.625817] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10979 11:20:56.007691 <3>[ 18.625825] remoteproc remoteproc0: request_firmware failed: -2
10980 11:20:56.014567 <3>[ 18.625829] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10981 11:20:56.020964 <6>[ 18.628236] r8152 2-1.3:1.0 enx002432307852: renamed from eth0
10982 11:20:56.031474 <6>[ 18.629415] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10983 11:20:56.037698 <6>[ 18.629593] usbcore: registered new interface driver uvcvideo
10984 11:20:56.045259 <6>[ 18.635325] Bluetooth: HCI device and connection manager initialized
10985 11:20:56.054929 <3>[ 18.635718] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10986 11:20:56.062010 <3>[ 18.670699] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10987 11:20:56.069209 <6>[ 18.672515] Bluetooth: HCI socket layer initialized
10988 11:20:56.075995 <3>[ 18.700578] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10989 11:20:56.083099 <6>[ 18.708130] Bluetooth: L2CAP socket layer initialized
10990 11:20:56.086505 <6>[ 18.708150] Bluetooth: SCO socket layer initialized
10991 11:20:56.096533 <3>[ 18.733676] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10992 11:20:56.102812 <6>[ 18.808956] usbcore: registered new interface driver btusb
10993 11:20:56.113188 <4>[ 18.809823] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10994 11:20:56.119624 <3>[ 18.809838] Bluetooth: hci0: Failed to load firmware file (-2)
10995 11:20:56.122670 <3>[ 18.809843] Bluetooth: hci0: Failed to set up firmware (-2)
10996 11:20:56.132760 <4>[ 18.809848] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10997 11:20:56.142672 <6>[ 18.845850] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10998 11:20:56.149213 <6>[ 18.959273] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10999 11:20:56.155576 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11000 11:20:56.173788 <6>[ 18.986086] mt7921e 0000:01:00.0: ASIC revision: 79610010
11001 11:20:56.184462 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
11002 11:20:56.281027 <4>[ 19.087255] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11003 11:20:56.361032 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11004 11:20:56.375486 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11005 11:20:56.402103 [[0;32m OK [0m] Started [0;<4>[ 19.206365] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11006 11:20:56.405335 1;39mDaily Cleanup of Temporary Directories[0m.
11007 11:20:56.412845 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11008 11:20:56.427505 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11009 11:20:56.447148 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11010 11:20:56.458813 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11011 11:20:56.478903 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11012 11:20:56.491293 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11013 11:20:56.508630 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11014 11:20:56.522231 <4>[ 19.326521] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11015 11:20:56.531801 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11016 11:20:56.567912 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11017 11:20:56.593763 Starting [0;1;39mUser Login Management[0m...
11018 11:20:56.609349 Starting [0;1;39mPermit User Sessions[0m...
11019 11:20:56.645462 Starting [0;1;39mLoad/Save RF Kill Swi<4>[ 19.451412] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11020 11:20:56.648600 tch Status[0m...
11021 11:20:56.665589 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11022 11:20:56.685123 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11023 11:20:56.704255 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11024 11:20:56.768459 <4>[ 19.574089] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11025 11:20:56.774236 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11026 11:20:56.824325 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11027 11:20:56.839174 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11028 11:20:56.854852 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11029 11:20:56.874664 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11030 11:20:56.888530 <4>[ 19.694874] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11031 11:20:56.931550 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11032 11:20:56.955899 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11033 11:20:57.007667 <4>[ 19.814079] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11034 11:20:57.007753
11035 11:20:57.007820
11036 11:20:57.014517 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11037 11:20:57.014620
11038 11:20:57.017518 debian-bullseye-arm64 login: root (automatic login)
11039 11:20:57.017628
11040 11:20:57.017725
11041 11:20:57.042575 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Mon Jun 5 10:57:14 UTC 2023 aarch64
11042 11:20:57.042665
11043 11:20:57.049008 The programs included with the Debian GNU/Linux system are free software;
11044 11:20:57.055529 the exact distribution terms for each program are described in the
11045 11:20:57.058986 individual files in /usr/share/doc/*/copyright.
11046 11:20:57.059069
11047 11:20:57.065403 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11048 11:20:57.065482 permitted by applicable law.
11049 11:20:57.068992 Matched prompt #10: / #
11051 11:20:57.069208 Setting prompt string to ['/ #']
11052 11:20:57.069299 end: 2.2.5.1 login-action (duration 00:00:21) [common]
11054 11:20:57.069502 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11055 11:20:57.069589 start: 2.2.6 expect-shell-connection (timeout 00:02:31) [common]
11056 11:20:57.069667 Setting prompt string to ['/ #']
11057 11:20:57.069728 Forcing a shell prompt, looking for ['/ #']
11059 11:20:57.119911 / #
11060 11:20:57.120013 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11061 11:20:57.120089 Waiting using forced prompt support (timeout 00:02:30)
11062 11:20:57.163446 <4>[ 19.933981] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11063 11:20:57.163540
11064 11:20:57.163796 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11065 11:20:57.163893 start: 2.2.7 export-device-env (timeout 00:02:31) [common]
11066 11:20:57.163996 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11067 11:20:57.164084 end: 2.2 depthcharge-retry (duration 00:02:29) [common]
11068 11:20:57.164162 end: 2 depthcharge-action (duration 00:02:29) [common]
11069 11:20:57.164245 start: 3 lava-test-retry (timeout 00:07:09) [common]
11070 11:20:57.164329 start: 3.1 lava-test-shell (timeout 00:07:09) [common]
11071 11:20:57.164400 Using namespace: common
11073 11:20:57.264659 / # #
11074 11:20:57.264785 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11075 11:20:57.264911 #<4>[ 20.053695] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11076 11:20:57.269450
11077 11:20:57.269705 Using /lava-10591276
11079 11:20:57.369966 / # export SHELL=/bin/sh
11080 11:20:57.370129 export SHELL=/bin/sh<4>[ 20.174075] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11081 11:20:57.375990
11083 11:20:57.519901 / # . /lava-10591276/environment
11084 11:20:57.520057 <3>[ 20.291779] mt7921e 0000:01:00.0: hardware init failed
11085 11:20:57.525094 . /lava-10591276/environment
11087 11:20:57.625540 / # /lava-10591276/bin/lava-test-runner /lava-10591276/0
11088 11:20:57.625658 Test shell timeout: 10s (minimum of the action and connection timeout)
11089 11:20:57.631329 /lava-10591276/bin/lava-test-runner /lava-10591276/0
11090 11:20:57.655809 + export TESTRUN_ID=0_igt-gpu-pa<8>[ 20.466861] <LAVA_SIGNAL_STARTRUN 0_igt-gpu-panfrost 10591276_1.5.2.3.1>
11091 11:20:57.656091 Received signal: <STARTRUN> 0_igt-gpu-panfrost 10591276_1.5.2.3.1
11092 11:20:57.656193 Starting test lava.0_igt-gpu-panfrost (10591276_1.5.2.3.1)
11093 11:20:57.656301 Skipping test definition patterns.
11094 11:20:57.659355 nfrost
11095 11:20:57.662582 + cd /lava-10591276/0/tests/0_igt-gpu-panfrost
11096 11:20:57.662654 + cat uuid
11097 11:20:57.666021 + UUID=10591276_1.5.2.3.1
11098 11:20:57.666090 + set +x
11099 11:20:57.675910 + IGT_FORCE_DRIVER=panfrost /usr/bin/igt-parser.sh panfrost_gem_new panfrost_get_param panfrost_prime panfrost_submit
11100 11:20:57.684404 <8>[ 20.497719] <LAVA_SIGNAL_TESTSET START panfrost_gem_new>
11101 11:20:57.684679 Received signal: <TESTSET> START panfrost_gem_new
11102 11:20:57.684787 Starting test_set panfrost_gem_new
11103 11:20:57.707749 <14>[ 20.520601] [IGT] panfrost_gem_new: executing
11104 11:20:57.717282 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.528831] [IGT] panfrost_gem_new: exiting, ret=77
11105 11:20:57.717391 .1.31 aarch64)
11106 11:20:57.730570 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.541238] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-4096 RESULT=skip>
11107 11:20:57.730853 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-4096 RESULT=skip
11109 11:20:57.734194 b/drmtest.c:621:
11110 11:20:57.734303 Test requirement: !(fd<0)
11111 11:20:57.740860 No known gpu found for chipset flags 0x32 (panfrost)
11112 11:20:57.743925 Last errno: 2, No such file or directory
11113 11:20:57.747140 [1mSubtest gem-new-4096: SKIP (0.000s)[0m
11114 11:20:57.753950 <14>[ 20.566341] [IGT] panfrost_gem_new: executing
11115 11:20:57.763704 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.574745] [IGT] panfrost_gem_new: exiting, ret=77
11116 11:20:57.763786 .1.31 aarch64)
11117 11:20:57.776977 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.586823] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-0 RESULT=skip>
11118 11:20:57.777055 b/drmtest.c:621:
11119 11:20:57.777288 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-0 RESULT=skip
11121 11:20:57.780376 Test requirement: !(fd<0)
11122 11:20:57.786593 No known gpu found for chipset flags 0x32 (panfrost)
11123 11:20:57.790214 Last errno: 2, No such file or directory
11124 11:20:57.793479 [1mSubtest gem-new-0: SKIP (0.000s)[0m
11125 11:20:57.800359 <14>[ 20.612991] [IGT] panfrost_gem_new: executing
11126 11:20:57.809915 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.621142] [IGT] panfrost_gem_new: exiting, ret=77
11127 11:20:57.809992 .1.31 aarch64)
11128 11:20:57.823561 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.633259] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-new-zeroed RESULT=skip>
11129 11:20:57.823814 Received signal: <TESTCASE> TEST_CASE_ID=gem-new-zeroed RESULT=skip
11131 11:20:57.826636 b/drmtest.c:621:
11132 11:20:57.829689 Test requireme<8>[ 20.643173] <LAVA_SIGNAL_TESTSET STOP>
11133 11:20:57.829758 nt: !(fd<0)
11134 11:20:57.829984 Received signal: <TESTSET> STOP
11135 11:20:57.830049 Closing test_set panfrost_gem_new
11136 11:20:57.836754 No known gpu found for chipset flags 0x32 (panfrost)
11137 11:20:57.839897 Last errno: 2, No such file or directory
11138 11:20:57.843080 [1mSubtest gem-new-zeroed: SKIP (0.000s)[0m
11139 11:20:57.856177 <8>[ 20.668910] <LAVA_SIGNAL_TESTSET START panfrost_get_param>
11140 11:20:57.856425 Received signal: <TESTSET> START panfrost_get_param
11141 11:20:57.856509 Starting test_set panfrost_get_param
11142 11:20:57.879465 <14>[ 20.692502] [IGT] panfrost_get_param: executing
11143 11:20:57.889226 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.700886] [IGT] panfrost_get_param: exiting, ret=77
11144 11:20:57.889300 .1.31 aarch64)
11145 11:20:57.902830 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.713185] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=base-params RESULT=skip>
11146 11:20:57.903098 Received signal: <TESTCASE> TEST_CASE_ID=base-params RESULT=skip
11148 11:20:57.905929 b/drmtest.c:621:
11149 11:20:57.905997 Test requirement: !(fd<0)
11150 11:20:57.912619 No known gpu found for chipset flags 0x32 (panfrost)
11151 11:20:57.916047 Last errno: 2, No such file or directory
11152 11:20:57.919294 [1mSubtest base-params: SKIP (0.000s)[0m
11153 11:20:57.925737 <14>[ 20.738540] [IGT] panfrost_get_param: executing
11154 11:20:57.935844 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.746691] [IGT] panfrost_get_param: exiting, ret=77
11155 11:20:57.935932 .1.31 aarch64)
11156 11:20:57.949022 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.759161] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-param RESULT=skip>
11157 11:20:57.949275 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-param RESULT=skip
11159 11:20:57.952408 b/drmtest.c:621:
11160 11:20:57.952488 Test requirement: !(fd<0)
11161 11:20:57.958893 No known gpu found for chipset flags 0x32 (panfrost)
11162 11:20:57.962477 Last errno: 2, No such file or directory
11163 11:20:57.965447 [1mSubtest get-bad-param: SKIP (0.000s)[0m
11164 11:20:57.972439 <14>[ 20.785616] [IGT] panfrost_get_param: executing
11165 11:20:57.982995 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.793976] [IGT] panfrost_get_param: exiting, ret=77
11166 11:20:57.983078 .1.31 aarch64)
11167 11:20:57.996037 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.806336] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=get-bad-padding RESULT=skip>
11168 11:20:57.996292 Received signal: <TESTCASE> TEST_CASE_ID=get-bad-padding RESULT=skip
11170 11:20:57.999532 b/drmtest.c:621:
11171 11:20:58.002439 Test requireme<8>[ 20.816134] <LAVA_SIGNAL_TESTSET STOP>
11172 11:20:58.002689 Received signal: <TESTSET> STOP
11173 11:20:58.002756 Closing test_set panfrost_get_param
11174 11:20:58.005862 nt: !(fd<0)
11175 11:20:58.008997 No known gpu found for chipset flags 0x32 (panfrost)
11176 11:20:58.012496 Last errno: 2, No such file or directory
11177 11:20:58.015751 [1mSubtest get-bad-padding: SKIP (0.000s)[0m
11178 11:20:58.029545 <8>[ 20.842672] <LAVA_SIGNAL_TESTSET START panfrost_prime>
11179 11:20:58.029799 Received signal: <TESTSET> START panfrost_prime
11180 11:20:58.029871 Starting test_set panfrost_prime
11181 11:20:58.053499 <14>[ 20.866301] [IGT] panfrost_prime: executing
11182 11:20:58.063047 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.874329] [IGT] panfrost_prime: exiting, ret=77
11183 11:20:58.063130 .1.31 aarch64)
11184 11:20:58.076618 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.886767] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=gem-prime-import RESULT=skip>
11185 11:20:58.076872 Received signal: <TESTCASE> TEST_CASE_ID=gem-prime-import RESULT=skip
11187 11:20:58.080198 b/drmtest.c:621:
11188 11:20:58.082871 Test requireme<8>[ 20.896350] <LAVA_SIGNAL_TESTSET STOP>
11189 11:20:58.082953 nt: !(fd<0)
11190 11:20:58.083193 Received signal: <TESTSET> STOP
11191 11:20:58.083276 Closing test_set panfrost_prime
11192 11:20:58.089494 No known gpu found for chipset flags 0x32 (panfrost)
11193 11:20:58.093025 Last errno: 2, No such file or directory
11194 11:20:58.096286 [1mSubtest gem-prime-import: SKIP (0.000s)[0m
11195 11:20:58.110310 <8>[ 20.923208] <LAVA_SIGNAL_TESTSET START panfrost_submit>
11196 11:20:58.110561 Received signal: <TESTSET> START panfrost_submit
11197 11:20:58.110629 Starting test_set panfrost_submit
11198 11:20:58.133727 <14>[ 20.946823] [IGT] panfrost_submit: executing
11199 11:20:58.143749 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 20.954896] [IGT] panfrost_submit: exiting, ret=77
11200 11:20:58.143831 .1.31 aarch64)
11201 11:20:58.157070 Test requirement not met in function drm_open_driver, file ../li<8>[ 20.967115] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit RESULT=skip>
11202 11:20:58.157153 b/drmtest.c:621:
11203 11:20:58.157386 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit RESULT=skip
11205 11:20:58.160590 Test requirement: !(fd<0)
11206 11:20:58.163942 No known gpu found for chipset flags 0x32 (panfrost)
11207 11:20:58.170618 Last errno: 2, No such file or directory
11208 11:20:58.173851 [1mSubtest pan-submit: SKIP (0.000s)[0m
11209 11:20:58.177029 <14>[ 20.992012] [IGT] panfrost_submit: executing
11210 11:20:58.187242 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 21.000064] [IGT] panfrost_submit: exiting, ret=77
11211 11:20:58.190583 .1.31 aarch64)
11212 11:20:58.203836 Test requirement not met in function drm_open_driver, file ../li<8>[ 21.012356] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip>
11213 11:20:58.203920 b/drmtest.c:621:
11214 11:20:58.204155 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-no-jc RESULT=skip
11216 11:20:58.206992 Test requirement: !(fd<0)
11217 11:20:58.210542 No known gpu found for chipset flags 0x32 (panfrost)
11218 11:20:58.217130 Last errno: 2, No such file or directory
11219 11:20:58.220034 [1mSubtest pan-submit-error-no-jc: SKIP (0.000s)[0m
11220 11:20:58.223404 <14>[ 21.038382] [IGT] panfrost_submit: executing
11221 11:20:58.233568 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 21.046727] [IGT] panfrost_submit: exiting, ret=77
11222 11:20:58.237071 .1.31 aarch64)
11223 11:20:58.250253 Test requirement not met in function drm_open_driver, file ../li<8>[ 21.058609] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip>
11224 11:20:58.250338 b/drmtest.c:621:
11225 11:20:58.250594 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-in-syncs RESULT=skip
11227 11:20:58.253423 Test requirement: !(fd<0)
11228 11:20:58.260062 No known gpu found for chipset flags 0x32 (panfrost)
11229 11:20:58.263593 Last errno: 2, No such file or directory
11230 11:20:58.266810 [1mSubtest pan-submit-error-bad-in-syncs: SKIP (0.000s)[0m
11231 11:20:58.273715 <14>[ 21.085113] [IGT] panfrost_submit: executing
11232 11:20:58.283053 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 21.093813] [IGT] panfrost_submit: exiting, ret=77
11233 11:20:58.283162 .1.31 aarch64)
11234 11:20:58.296665 Test requirement not met in function drm_open_driver, file ../li<8>[ 21.105939] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip>
11235 11:20:58.296936 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-bo-handles RESULT=skip
11237 11:20:58.299606 b/drmtest.c:621:
11238 11:20:58.299679 Test requirement: !(fd<0)
11239 11:20:58.306378 No known gpu found for chipset flags 0x32 (panfrost)
11240 11:20:58.309667 Last errno: 2, No such file or directory
11241 11:20:58.316165 [1mSubtest pan-submit-error-bad-bo-handles: SKIP (0.000s)[0m
11242 11:20:58.319479 <14>[ 21.133636] [IGT] panfrost_submit: executing
11243 11:20:58.329911 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 21.141945] [IGT] panfrost_submit: exiting, ret=77
11244 11:20:58.330019 .1.31 aarch64)
11245 11:20:58.346295 Test requirement not met in function drm_open_driver, file ../li<8>[ 21.153756] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip>
11246 11:20:58.346433 b/drmtest.c:621:
11247 11:20:58.346679 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-requirements RESULT=skip
11249 11:20:58.349860 Test requirement: !(fd<0)
11250 11:20:58.353066 No known gpu found for chipset flags 0x32 (panfrost)
11251 11:20:58.356205 Last errno: 2, No such file or directory
11252 11:20:58.362678 [1mSubtest pan-submit-error-bad-requirements: SKIP (0.000s)[0m
11253 11:20:58.369737 <14>[ 21.180832] [IGT] panfrost_submit: executing
11254 11:20:58.375845 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 21.189414] [IGT] panfrost_submit: exiting, ret=77
11255 11:20:58.379203 .1.31 aarch64)
11256 11:20:58.392490 Test requirement not met in function drm_open_driver, file ../li<8>[ 21.201487] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip>
11257 11:20:58.392814 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-error-bad-out-sync RESULT=skip
11259 11:20:58.395968 b/drmtest.c:621:
11260 11:20:58.396109 Test requirement: !(fd<0)
11261 11:20:58.402368 No known gpu found for chipset flags 0x32 (panfrost)
11262 11:20:58.406259 Last errno: 2, No such file or directory
11263 11:20:58.409077 [1mSubtest pan-submit-error-bad-out-sync: SKIP (0.000s)[0m
11264 11:20:58.416457 <14>[ 21.228167] [IGT] panfrost_submit: executing
11265 11:20:58.425973 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 21.236598] [IGT] panfrost_submit: exiting, ret=77
11266 11:20:58.426061 .1.31 aarch64)
11267 11:20:58.438820 Test requirement not met in function drm_open_driver, file ../li<8>[ 21.248597] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-reset RESULT=skip>
11268 11:20:58.438905 b/drmtest.c:621:
11269 11:20:58.439146 Received signal: <TESTCASE> TEST_CASE_ID=pan-reset RESULT=skip
11271 11:20:58.442753 Test requirement: !(fd<0)
11272 11:20:58.445866 No known gpu found for chipset flags 0x32 (panfrost)
11273 11:20:58.452003 Last errno: 2, No such file or directory
11274 11:20:58.455371 [1mSubtest pan-reset: SKIP (0.000s)[0m
11275 11:20:58.458914 <14>[ 21.273625] [IGT] panfrost_submit: executing
11276 11:20:58.468664 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 21.281772] [IGT] panfrost_submit: exiting, ret=77
11277 11:20:58.472584 .1.31 aarch64)
11278 11:20:58.486005 Test requirement not met in function drm_open_driver, file ../li<8>[ 21.293710] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-submit-and-close RESULT=skip>
11279 11:20:58.486090 b/drmtest.c:621:
11280 11:20:58.486325 Received signal: <TESTCASE> TEST_CASE_ID=pan-submit-and-close RESULT=skip
11282 11:20:58.488940 Test requirement: !(fd<0)
11283 11:20:58.491991 No known gpu found for chipset flags 0x32 (panfrost)
11284 11:20:58.495311 Last errno: 2, No such file or directory
11285 11:20:58.502184 [1mSubtest pan-submit-and-close: SKIP (0.000s)[0m
11286 11:20:58.505628 <14>[ 21.319812] [IGT] panfrost_submit: executing
11287 11:20:58.515629 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6<14>[ 21.327818] [IGT] panfrost_submit: exiting, ret=77
11288 11:20:58.518466 .1.31 aarch64)
11289 11:20:58.531675 Test requirement not met in function drm_open_driver, file ../li<8>[ 21.339923] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip>
11290 11:20:58.531765 b/drmtest.c:621:
11291 11:20:58.532008 Received signal: <TESTCASE> TEST_CASE_ID=pan-unhandled-pagefault RESULT=skip
11293 11:20:58.538548 Test requireme<8>[ 21.350471] <LAVA_SIGNAL_TESTSET STOP>
11294 11:20:58.538621 nt: !(fd<0)
11295 11:20:58.538856 Received signal: <TESTSET> STOP
11296 11:20:58.538919 Closing test_set panfrost_submit
11297 11:20:58.545382 No <8>[ 21.356333] <LAVA_SIGNAL_ENDRUN 0_igt-gpu-panfrost 10591276_1.5.2.3.1>
11298 11:20:58.545626 Received signal: <ENDRUN> 0_igt-gpu-panfrost 10591276_1.5.2.3.1
11299 11:20:58.545705 Ending use of test pattern.
11300 11:20:58.545771 Ending test lava.0_igt-gpu-panfrost (10591276_1.5.2.3.1), duration 0.89
11302 11:20:58.551631 known gpu found for chipset flags 0x32 (panfrost)
11303 11:20:58.555253 Last errno: 2, No such file or directory
11304 11:20:58.558311 [1mSubtest pan-unhandled-pagefault: SKIP (0.000s)[0m
11305 11:20:58.558386 + set +x
11306 11:20:58.561657 <LAVA_TEST_RUNNER EXIT>
11307 11:20:58.561898 ok: lava_test_shell seems to have completed
11308 11:20:58.562199 base-params:
result: skip
set: panfrost_get_param
gem-new-0:
result: skip
set: panfrost_gem_new
gem-new-4096:
result: skip
set: panfrost_gem_new
gem-new-zeroed:
result: skip
set: panfrost_gem_new
gem-prime-import:
result: skip
set: panfrost_prime
get-bad-padding:
result: skip
set: panfrost_get_param
get-bad-param:
result: skip
set: panfrost_get_param
pan-reset:
result: skip
set: panfrost_submit
pan-submit:
result: skip
set: panfrost_submit
pan-submit-and-close:
result: skip
set: panfrost_submit
pan-submit-error-bad-bo-handles:
result: skip
set: panfrost_submit
pan-submit-error-bad-in-syncs:
result: skip
set: panfrost_submit
pan-submit-error-bad-out-sync:
result: skip
set: panfrost_submit
pan-submit-error-bad-requirements:
result: skip
set: panfrost_submit
pan-submit-error-no-jc:
result: skip
set: panfrost_submit
pan-unhandled-pagefault:
result: skip
set: panfrost_submit
11309 11:20:58.562307 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11310 11:20:58.562391 end: 3 lava-test-retry (duration 00:00:01) [common]
11311 11:20:58.562480 start: 4 finalize (timeout 00:07:07) [common]
11312 11:20:58.562574 start: 4.1 power-off (timeout 00:00:30) [common]
11313 11:20:58.562721 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-3' '--port=1' '--command=off'
11314 11:20:58.638735 >> Command sent successfully.
11315 11:20:58.643313 Returned 0 in 0 seconds
11316 11:20:58.744222 end: 4.1 power-off (duration 00:00:00) [common]
11318 11:20:58.745713 start: 4.2 read-feedback (timeout 00:07:07) [common]
11319 11:20:58.746991 Listened to connection for namespace 'common' for up to 1s
11320 11:20:59.747465 Finalising connection for namespace 'common'
11321 11:20:59.747645 Disconnecting from shell: Finalise
11322 11:20:59.747732 / #
11323 11:20:59.848037 end: 4.2 read-feedback (duration 00:00:01) [common]
11324 11:20:59.848180 end: 4 finalize (duration 00:00:01) [common]
11325 11:20:59.848298 Cleaning after the job
11326 11:20:59.848409 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591276/tftp-deploy-hycd9pjt/ramdisk
11327 11:20:59.854761 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591276/tftp-deploy-hycd9pjt/kernel
11328 11:20:59.860965 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591276/tftp-deploy-hycd9pjt/dtb
11329 11:20:59.861144 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591276/tftp-deploy-hycd9pjt/modules
11330 11:20:59.866705 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10591276
11331 11:20:59.974372 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10591276
11332 11:20:59.974556 Job finished correctly