Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 33
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 24
1 11:17:05.150151 lava-dispatcher, installed at version: 2023.05.1
2 11:17:05.150349 start: 0 validate
3 11:17:05.150476 Start time: 2023-06-05 11:17:05.150469+00:00 (UTC)
4 11:17:05.150593 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:17:05.150721 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-igt%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 11:17:05.439850 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:17:05.440670 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:17:05.738717 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:17:05.739523 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:17:06.029588 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:17:06.030381 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 11:17:06.313681 validate duration: 1.16
14 11:17:06.313939 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 11:17:06.314039 start: 1.1 download-retry (timeout 00:10:00) [common]
16 11:17:06.314123 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 11:17:06.314250 Not decompressing ramdisk as can be used compressed.
18 11:17:06.314338 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-igt/20230527.0/arm64/rootfs.cpio.gz
19 11:17:06.314405 saving as /var/lib/lava/dispatcher/tmp/10591274/tftp-deploy-uqlzbi0t/ramdisk/rootfs.cpio.gz
20 11:17:06.314466 total size: 43394293 (41MB)
21 11:17:06.315481 progress 0% (0MB)
22 11:17:06.326231 progress 5% (2MB)
23 11:17:06.336729 progress 10% (4MB)
24 11:17:06.347264 progress 15% (6MB)
25 11:17:06.357951 progress 20% (8MB)
26 11:17:06.368933 progress 25% (10MB)
27 11:17:06.379592 progress 30% (12MB)
28 11:17:06.390307 progress 35% (14MB)
29 11:17:06.401001 progress 40% (16MB)
30 11:17:06.411516 progress 45% (18MB)
31 11:17:06.422247 progress 50% (20MB)
32 11:17:06.432802 progress 55% (22MB)
33 11:17:06.443406 progress 60% (24MB)
34 11:17:06.454117 progress 65% (26MB)
35 11:17:06.464990 progress 70% (29MB)
36 11:17:06.475700 progress 75% (31MB)
37 11:17:06.486374 progress 80% (33MB)
38 11:17:06.497108 progress 85% (35MB)
39 11:17:06.507651 progress 90% (37MB)
40 11:17:06.518181 progress 95% (39MB)
41 11:17:06.528633 progress 100% (41MB)
42 11:17:06.528782 41MB downloaded in 0.21s (193.10MB/s)
43 11:17:06.528937 end: 1.1.1 http-download (duration 00:00:00) [common]
45 11:17:06.529178 end: 1.1 download-retry (duration 00:00:00) [common]
46 11:17:06.529263 start: 1.2 download-retry (timeout 00:10:00) [common]
47 11:17:06.529346 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 11:17:06.529480 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 11:17:06.529553 saving as /var/lib/lava/dispatcher/tmp/10591274/tftp-deploy-uqlzbi0t/kernel/Image
50 11:17:06.529614 total size: 45746688 (43MB)
51 11:17:06.529673 No compression specified
52 11:17:06.530775 progress 0% (0MB)
53 11:17:06.541924 progress 5% (2MB)
54 11:17:06.553275 progress 10% (4MB)
55 11:17:06.564590 progress 15% (6MB)
56 11:17:06.575997 progress 20% (8MB)
57 11:17:06.587257 progress 25% (10MB)
58 11:17:06.598499 progress 30% (13MB)
59 11:17:06.609827 progress 35% (15MB)
60 11:17:06.620993 progress 40% (17MB)
61 11:17:06.632241 progress 45% (19MB)
62 11:17:06.643415 progress 50% (21MB)
63 11:17:06.654629 progress 55% (24MB)
64 11:17:06.665959 progress 60% (26MB)
65 11:17:06.677274 progress 65% (28MB)
66 11:17:06.688603 progress 70% (30MB)
67 11:17:06.699949 progress 75% (32MB)
68 11:17:06.711083 progress 80% (34MB)
69 11:17:06.722285 progress 85% (37MB)
70 11:17:06.733574 progress 90% (39MB)
71 11:17:06.744576 progress 95% (41MB)
72 11:17:06.755722 progress 100% (43MB)
73 11:17:06.755837 43MB downloaded in 0.23s (192.86MB/s)
74 11:17:06.755982 end: 1.2.1 http-download (duration 00:00:00) [common]
76 11:17:06.756209 end: 1.2 download-retry (duration 00:00:00) [common]
77 11:17:06.756293 start: 1.3 download-retry (timeout 00:10:00) [common]
78 11:17:06.756379 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 11:17:06.756514 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 11:17:06.756588 saving as /var/lib/lava/dispatcher/tmp/10591274/tftp-deploy-uqlzbi0t/dtb/mt8192-asurada-spherion-r0.dtb
81 11:17:06.756650 total size: 46924 (0MB)
82 11:17:06.756709 No compression specified
83 11:17:06.757875 progress 69% (0MB)
84 11:17:06.758143 progress 100% (0MB)
85 11:17:06.758291 0MB downloaded in 0.00s (27.29MB/s)
86 11:17:06.758409 end: 1.3.1 http-download (duration 00:00:00) [common]
88 11:17:06.758625 end: 1.3 download-retry (duration 00:00:00) [common]
89 11:17:06.758709 start: 1.4 download-retry (timeout 00:10:00) [common]
90 11:17:06.758789 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 11:17:06.758941 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 11:17:06.759022 saving as /var/lib/lava/dispatcher/tmp/10591274/tftp-deploy-uqlzbi0t/modules/modules.tar
93 11:17:06.759082 total size: 8547328 (8MB)
94 11:17:06.759141 Using unxz to decompress xz
95 11:17:06.762675 progress 0% (0MB)
96 11:17:06.783985 progress 5% (0MB)
97 11:17:06.808570 progress 10% (0MB)
98 11:17:06.833979 progress 15% (1MB)
99 11:17:06.857652 progress 20% (1MB)
100 11:17:06.883121 progress 25% (2MB)
101 11:17:06.910048 progress 30% (2MB)
102 11:17:06.934891 progress 35% (2MB)
103 11:17:06.959228 progress 40% (3MB)
104 11:17:06.983896 progress 45% (3MB)
105 11:17:07.007304 progress 50% (4MB)
106 11:17:07.029598 progress 55% (4MB)
107 11:17:07.054031 progress 60% (4MB)
108 11:17:07.078299 progress 65% (5MB)
109 11:17:07.102421 progress 70% (5MB)
110 11:17:07.128354 progress 75% (6MB)
111 11:17:07.157084 progress 80% (6MB)
112 11:17:07.178962 progress 85% (6MB)
113 11:17:07.204339 progress 90% (7MB)
114 11:17:07.227447 progress 95% (7MB)
115 11:17:07.252702 progress 100% (8MB)
116 11:17:07.258719 8MB downloaded in 0.50s (16.31MB/s)
117 11:17:07.258992 end: 1.4.1 http-download (duration 00:00:01) [common]
119 11:17:07.259260 end: 1.4 download-retry (duration 00:00:01) [common]
120 11:17:07.259355 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 11:17:07.259452 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 11:17:07.259533 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 11:17:07.259621 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 11:17:07.259835 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10591274/lava-overlay-am35bh10
125 11:17:07.259963 makedir: /var/lib/lava/dispatcher/tmp/10591274/lava-overlay-am35bh10/lava-10591274/bin
126 11:17:07.260065 makedir: /var/lib/lava/dispatcher/tmp/10591274/lava-overlay-am35bh10/lava-10591274/tests
127 11:17:07.260171 makedir: /var/lib/lava/dispatcher/tmp/10591274/lava-overlay-am35bh10/lava-10591274/results
128 11:17:07.260290 Creating /var/lib/lava/dispatcher/tmp/10591274/lava-overlay-am35bh10/lava-10591274/bin/lava-add-keys
129 11:17:07.260436 Creating /var/lib/lava/dispatcher/tmp/10591274/lava-overlay-am35bh10/lava-10591274/bin/lava-add-sources
130 11:17:07.260562 Creating /var/lib/lava/dispatcher/tmp/10591274/lava-overlay-am35bh10/lava-10591274/bin/lava-background-process-start
131 11:17:07.260689 Creating /var/lib/lava/dispatcher/tmp/10591274/lava-overlay-am35bh10/lava-10591274/bin/lava-background-process-stop
132 11:17:07.260854 Creating /var/lib/lava/dispatcher/tmp/10591274/lava-overlay-am35bh10/lava-10591274/bin/lava-common-functions
133 11:17:07.260975 Creating /var/lib/lava/dispatcher/tmp/10591274/lava-overlay-am35bh10/lava-10591274/bin/lava-echo-ipv4
134 11:17:07.261097 Creating /var/lib/lava/dispatcher/tmp/10591274/lava-overlay-am35bh10/lava-10591274/bin/lava-install-packages
135 11:17:07.261218 Creating /var/lib/lava/dispatcher/tmp/10591274/lava-overlay-am35bh10/lava-10591274/bin/lava-installed-packages
136 11:17:07.261337 Creating /var/lib/lava/dispatcher/tmp/10591274/lava-overlay-am35bh10/lava-10591274/bin/lava-os-build
137 11:17:07.261456 Creating /var/lib/lava/dispatcher/tmp/10591274/lava-overlay-am35bh10/lava-10591274/bin/lava-probe-channel
138 11:17:07.261575 Creating /var/lib/lava/dispatcher/tmp/10591274/lava-overlay-am35bh10/lava-10591274/bin/lava-probe-ip
139 11:17:07.261696 Creating /var/lib/lava/dispatcher/tmp/10591274/lava-overlay-am35bh10/lava-10591274/bin/lava-target-ip
140 11:17:07.261814 Creating /var/lib/lava/dispatcher/tmp/10591274/lava-overlay-am35bh10/lava-10591274/bin/lava-target-mac
141 11:17:07.261932 Creating /var/lib/lava/dispatcher/tmp/10591274/lava-overlay-am35bh10/lava-10591274/bin/lava-target-storage
142 11:17:07.262055 Creating /var/lib/lava/dispatcher/tmp/10591274/lava-overlay-am35bh10/lava-10591274/bin/lava-test-case
143 11:17:07.262175 Creating /var/lib/lava/dispatcher/tmp/10591274/lava-overlay-am35bh10/lava-10591274/bin/lava-test-event
144 11:17:07.262293 Creating /var/lib/lava/dispatcher/tmp/10591274/lava-overlay-am35bh10/lava-10591274/bin/lava-test-feedback
145 11:17:07.262412 Creating /var/lib/lava/dispatcher/tmp/10591274/lava-overlay-am35bh10/lava-10591274/bin/lava-test-raise
146 11:17:07.262532 Creating /var/lib/lava/dispatcher/tmp/10591274/lava-overlay-am35bh10/lava-10591274/bin/lava-test-reference
147 11:17:07.262650 Creating /var/lib/lava/dispatcher/tmp/10591274/lava-overlay-am35bh10/lava-10591274/bin/lava-test-runner
148 11:17:07.262768 Creating /var/lib/lava/dispatcher/tmp/10591274/lava-overlay-am35bh10/lava-10591274/bin/lava-test-set
149 11:17:07.262889 Creating /var/lib/lava/dispatcher/tmp/10591274/lava-overlay-am35bh10/lava-10591274/bin/lava-test-shell
150 11:17:07.263012 Updating /var/lib/lava/dispatcher/tmp/10591274/lava-overlay-am35bh10/lava-10591274/bin/lava-install-packages (oe)
151 11:17:07.263157 Updating /var/lib/lava/dispatcher/tmp/10591274/lava-overlay-am35bh10/lava-10591274/bin/lava-installed-packages (oe)
152 11:17:07.263283 Creating /var/lib/lava/dispatcher/tmp/10591274/lava-overlay-am35bh10/lava-10591274/environment
153 11:17:07.263384 LAVA metadata
154 11:17:07.263456 - LAVA_JOB_ID=10591274
155 11:17:07.263520 - LAVA_DISPATCHER_IP=192.168.201.1
156 11:17:07.263626 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 11:17:07.263692 skipped lava-vland-overlay
158 11:17:07.263766 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 11:17:07.263847 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 11:17:07.263909 skipped lava-multinode-overlay
161 11:17:07.263982 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 11:17:07.264064 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 11:17:07.264136 Loading test definitions
164 11:17:07.264228 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 11:17:07.264299 Using /lava-10591274 at stage 0
166 11:17:07.264595 uuid=10591274_1.5.2.3.1 testdef=None
167 11:17:07.264684 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 11:17:07.264772 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 11:17:07.265327 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 11:17:07.265553 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 11:17:07.266164 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 11:17:07.266394 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 11:17:07.266996 runner path: /var/lib/lava/dispatcher/tmp/10591274/lava-overlay-am35bh10/lava-10591274/0/tests/0_igt-kms-mediatek test_uuid 10591274_1.5.2.3.1
176 11:17:07.267157 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 11:17:07.267362 Creating lava-test-runner.conf files
179 11:17:07.267427 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10591274/lava-overlay-am35bh10/lava-10591274/0 for stage 0
180 11:17:07.267515 - 0_igt-kms-mediatek
181 11:17:07.267612 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 11:17:07.267695 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 11:17:07.274217 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 11:17:07.274321 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 11:17:07.274407 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 11:17:07.274492 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 11:17:07.274580 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 11:17:08.546623 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 11:17:08.546994 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 11:17:08.547109 extracting modules file /var/lib/lava/dispatcher/tmp/10591274/tftp-deploy-uqlzbi0t/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10591274/extract-overlay-ramdisk-957r9cks/ramdisk
191 11:17:08.749165 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 11:17:08.749341 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 11:17:08.749438 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10591274/compress-overlay-guy6ry7r/overlay-1.5.2.4.tar.gz to ramdisk
194 11:17:08.749508 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10591274/compress-overlay-guy6ry7r/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10591274/extract-overlay-ramdisk-957r9cks/ramdisk
195 11:17:08.755832 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 11:17:08.755968 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 11:17:08.756071 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 11:17:08.756158 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 11:17:08.756244 Building ramdisk /var/lib/lava/dispatcher/tmp/10591274/extract-overlay-ramdisk-957r9cks/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10591274/extract-overlay-ramdisk-957r9cks/ramdisk
200 11:17:09.660268 >> 369039 blocks
201 11:17:15.255888 rename /var/lib/lava/dispatcher/tmp/10591274/extract-overlay-ramdisk-957r9cks/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10591274/tftp-deploy-uqlzbi0t/ramdisk/ramdisk.cpio.gz
202 11:17:15.256381 end: 1.5.7 compress-ramdisk (duration 00:00:07) [common]
203 11:17:15.256501 start: 1.5.8 prepare-kernel (timeout 00:09:51) [common]
204 11:17:15.256603 start: 1.5.8.1 prepare-fit (timeout 00:09:51) [common]
205 11:17:15.256711 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10591274/tftp-deploy-uqlzbi0t/kernel/Image'
206 11:17:26.408475 Returned 0 in 11 seconds
207 11:17:26.509502 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10591274/tftp-deploy-uqlzbi0t/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10591274/tftp-deploy-uqlzbi0t/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10591274/tftp-deploy-uqlzbi0t/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10591274/tftp-deploy-uqlzbi0t/kernel/image.itb
208 11:17:27.291266 output: FIT description: Kernel Image image with one or more FDT blobs
209 11:17:27.291627 output: Created: Mon Jun 5 12:17:27 2023
210 11:17:27.291701 output: Image 0 (kernel-1)
211 11:17:27.291768 output: Description:
212 11:17:27.291830 output: Created: Mon Jun 5 12:17:27 2023
213 11:17:27.291893 output: Type: Kernel Image
214 11:17:27.291954 output: Compression: lzma compressed
215 11:17:27.292014 output: Data Size: 10086024 Bytes = 9849.63 KiB = 9.62 MiB
216 11:17:27.292073 output: Architecture: AArch64
217 11:17:27.292132 output: OS: Linux
218 11:17:27.292192 output: Load Address: 0x00000000
219 11:17:27.292252 output: Entry Point: 0x00000000
220 11:17:27.292312 output: Hash algo: crc32
221 11:17:27.292366 output: Hash value: eb1cf9b8
222 11:17:27.292420 output: Image 1 (fdt-1)
223 11:17:27.292473 output: Description: mt8192-asurada-spherion-r0
224 11:17:27.292527 output: Created: Mon Jun 5 12:17:27 2023
225 11:17:27.292580 output: Type: Flat Device Tree
226 11:17:27.292633 output: Compression: uncompressed
227 11:17:27.292687 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
228 11:17:27.292740 output: Architecture: AArch64
229 11:17:27.292823 output: Hash algo: crc32
230 11:17:27.292891 output: Hash value: 1df858fa
231 11:17:27.292944 output: Image 2 (ramdisk-1)
232 11:17:27.292997 output: Description: unavailable
233 11:17:27.293050 output: Created: Mon Jun 5 12:17:27 2023
234 11:17:27.293104 output: Type: RAMDisk Image
235 11:17:27.293157 output: Compression: Unknown Compression
236 11:17:27.293210 output: Data Size: 56393850 Bytes = 55072.12 KiB = 53.78 MiB
237 11:17:27.293263 output: Architecture: AArch64
238 11:17:27.293316 output: OS: Linux
239 11:17:27.293368 output: Load Address: unavailable
240 11:17:27.293421 output: Entry Point: unavailable
241 11:17:27.293474 output: Hash algo: crc32
242 11:17:27.293526 output: Hash value: e5f328d3
243 11:17:27.293579 output: Default Configuration: 'conf-1'
244 11:17:27.293632 output: Configuration 0 (conf-1)
245 11:17:27.293684 output: Description: mt8192-asurada-spherion-r0
246 11:17:27.293737 output: Kernel: kernel-1
247 11:17:27.293789 output: Init Ramdisk: ramdisk-1
248 11:17:27.293842 output: FDT: fdt-1
249 11:17:27.293895 output: Loadables: kernel-1
250 11:17:27.293947 output:
251 11:17:27.294136 end: 1.5.8.1 prepare-fit (duration 00:00:12) [common]
252 11:17:27.294240 end: 1.5.8 prepare-kernel (duration 00:00:12) [common]
253 11:17:27.294343 end: 1.5 prepare-tftp-overlay (duration 00:00:20) [common]
254 11:17:27.294441 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:39) [common]
255 11:17:27.294519 No LXC device requested
256 11:17:27.294599 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 11:17:27.294687 start: 1.7 deploy-device-env (timeout 00:09:39) [common]
258 11:17:27.294766 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 11:17:27.294834 Checking files for TFTP limit of 4294967296 bytes.
260 11:17:27.295319 end: 1 tftp-deploy (duration 00:00:21) [common]
261 11:17:27.295430 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 11:17:27.295525 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 11:17:27.295649 substitutions:
264 11:17:27.295718 - {DTB}: 10591274/tftp-deploy-uqlzbi0t/dtb/mt8192-asurada-spherion-r0.dtb
265 11:17:27.295784 - {INITRD}: 10591274/tftp-deploy-uqlzbi0t/ramdisk/ramdisk.cpio.gz
266 11:17:27.295844 - {KERNEL}: 10591274/tftp-deploy-uqlzbi0t/kernel/Image
267 11:17:27.295903 - {LAVA_MAC}: None
268 11:17:27.295960 - {PRESEED_CONFIG}: None
269 11:17:27.296016 - {PRESEED_LOCAL}: None
270 11:17:27.296072 - {RAMDISK}: 10591274/tftp-deploy-uqlzbi0t/ramdisk/ramdisk.cpio.gz
271 11:17:27.296128 - {ROOT_PART}: None
272 11:17:27.296183 - {ROOT}: None
273 11:17:27.296238 - {SERVER_IP}: 192.168.201.1
274 11:17:27.296293 - {TEE}: None
275 11:17:27.296347 Parsed boot commands:
276 11:17:27.296402 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 11:17:27.296574 Parsed boot commands: tftpboot 192.168.201.1 10591274/tftp-deploy-uqlzbi0t/kernel/image.itb 10591274/tftp-deploy-uqlzbi0t/kernel/cmdline
278 11:17:27.296664 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 11:17:27.296749 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 11:17:27.296886 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 11:17:27.296973 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 11:17:27.297045 Not connected, no need to disconnect.
283 11:17:27.297120 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 11:17:27.297201 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 11:17:27.297271 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-1'
286 11:17:27.300522 Setting prompt string to ['lava-test: # ']
287 11:17:27.300887 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 11:17:27.300993 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 11:17:27.301085 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 11:17:27.301181 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 11:17:27.301372 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=reboot'
292 11:17:32.452073 >> Command sent successfully.
293 11:17:32.463395 Returned 0 in 5 seconds
294 11:17:32.564694 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 11:17:32.567769 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 11:17:32.568343 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 11:17:32.568878 Setting prompt string to 'Starting depthcharge on Spherion...'
299 11:17:32.569276 Changing prompt to 'Starting depthcharge on Spherion...'
300 11:17:32.569680 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 11:17:32.571099 [Enter `^Ec?' for help]
302 11:17:32.727821
303 11:17:32.728650
304 11:17:32.729367 F0: 102B 0000
305 11:17:32.729780
306 11:17:32.730143 F3: 1001 0000 [0200]
307 11:17:32.730777
308 11:17:32.731137 F3: 1001 0000
309 11:17:32.731472
310 11:17:32.731796 F7: 102D 0000
311 11:17:32.732118
312 11:17:32.734289 F1: 0000 0000
313 11:17:32.734767
314 11:17:32.735150 V0: 0000 0000 [0001]
315 11:17:32.735522
316 11:17:32.737498 00: 0007 8000
317 11:17:32.737980
318 11:17:32.738357 01: 0000 0000
319 11:17:32.738724
320 11:17:32.740843 BP: 0C00 0209 [0000]
321 11:17:32.741322
322 11:17:32.741700 G0: 1182 0000
323 11:17:32.742049
324 11:17:32.744221 EC: 0000 0021 [4000]
325 11:17:32.744695
326 11:17:32.745130 S7: 0000 0000 [0000]
327 11:17:32.745507
328 11:17:32.747505 CC: 0000 0000 [0001]
329 11:17:32.747985
330 11:17:32.748362 T0: 0000 0040 [010F]
331 11:17:32.748713
332 11:17:32.750851 Jump to BL
333 11:17:32.751453
334 11:17:32.774518
335 11:17:32.775050
336 11:17:32.775395
337 11:17:32.782450 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 11:17:32.785828 ARM64: Exception handlers installed.
339 11:17:32.789435 ARM64: Testing exception
340 11:17:32.792703 ARM64: Done test exception
341 11:17:32.799667 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 11:17:32.809557 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 11:17:32.816374 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 11:17:32.826562 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 11:17:32.833145 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 11:17:32.840037 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 11:17:32.851600 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 11:17:32.858252 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 11:17:32.877380 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 11:17:32.880864 WDT: Last reset was cold boot
351 11:17:32.884112 SPI1(PAD0) initialized at 2873684 Hz
352 11:17:32.887342 SPI5(PAD0) initialized at 992727 Hz
353 11:17:32.891075 VBOOT: Loading verstage.
354 11:17:32.897710 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 11:17:32.900793 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 11:17:32.904352 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 11:17:32.907413 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 11:17:32.914695 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 11:17:32.921571 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 11:17:32.932830 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
361 11:17:32.933402
362 11:17:32.933779
363 11:17:32.942450 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 11:17:32.945713 ARM64: Exception handlers installed.
365 11:17:32.949335 ARM64: Testing exception
366 11:17:32.949911 ARM64: Done test exception
367 11:17:32.956174 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 11:17:32.959138 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 11:17:32.973602 Probing TPM: . done!
370 11:17:32.974180 TPM ready after 0 ms
371 11:17:32.980002 Connected to device vid:did:rid of 1ae0:0028:00
372 11:17:32.987392 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
373 11:17:32.990827 Initialized TPM device CR50 revision 0
374 11:17:33.057670 tlcl_send_startup: Startup return code is 0
375 11:17:33.058260 TPM: setup succeeded
376 11:17:33.068905 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 11:17:33.077863 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 11:17:33.087985 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 11:17:33.097243 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 11:17:33.100914 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 11:17:33.107617 in-header: 03 07 00 00 08 00 00 00
382 11:17:33.111334 in-data: aa e4 47 04 13 02 00 00
383 11:17:33.114583 Chrome EC: UHEPI supported
384 11:17:33.122078 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 11:17:33.125566 in-header: 03 ad 00 00 08 00 00 00
386 11:17:33.129188 in-data: 00 20 20 08 00 00 00 00
387 11:17:33.129658 Phase 1
388 11:17:33.132652 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 11:17:33.140524 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 11:17:33.144493 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 11:17:33.147802 Recovery requested (1009000e)
392 11:17:33.157204 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 11:17:33.163746 tlcl_extend: response is 0
394 11:17:33.173154 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 11:17:33.178509 tlcl_extend: response is 0
396 11:17:33.185541 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 11:17:33.205842 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 11:17:33.212719 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 11:17:33.213333
400 11:17:33.213718
401 11:17:33.222747 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 11:17:33.225557 ARM64: Exception handlers installed.
403 11:17:33.226035 ARM64: Testing exception
404 11:17:33.229169 ARM64: Done test exception
405 11:17:33.251079 pmic_efuse_setting: Set efuses in 11 msecs
406 11:17:33.254468 pmwrap_interface_init: Select PMIF_VLD_RDY
407 11:17:33.261294 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 11:17:33.265179 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 11:17:33.268329 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 11:17:33.274582 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 11:17:33.278306 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 11:17:33.285389 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 11:17:33.288884 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 11:17:33.292603 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 11:17:33.300196 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 11:17:33.304142 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 11:17:33.307386 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 11:17:33.311435 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 11:17:33.317761 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 11:17:33.324408 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 11:17:33.327443 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 11:17:33.334883 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 11:17:33.342025 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 11:17:33.345757 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 11:17:33.352652 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 11:17:33.356077 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 11:17:33.363011 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 11:17:33.370111 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 11:17:33.373454 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 11:17:33.380155 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 11:17:33.383149 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 11:17:33.389743 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 11:17:33.396374 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 11:17:33.399703 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 11:17:33.406312 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 11:17:33.410008 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 11:17:33.416459 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 11:17:33.419743 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 11:17:33.426491 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 11:17:33.429647 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 11:17:33.433011 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 11:17:33.439870 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 11:17:33.446260 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 11:17:33.450070 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 11:17:33.453085 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 11:17:33.459798 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 11:17:33.463909 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 11:17:33.467447 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 11:17:33.471051 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 11:17:33.477427 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 11:17:33.480703 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 11:17:33.484316 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 11:17:33.490951 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 11:17:33.494555 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 11:17:33.497055 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 11:17:33.500323 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 11:17:33.507380 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 11:17:33.514085 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 11:17:33.523943 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 11:17:33.526949 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 11:17:33.533491 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 11:17:33.543871 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 11:17:33.546974 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 11:17:33.553643 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 11:17:33.557214 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 11:17:33.563696 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x7
467 11:17:33.570424 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 11:17:33.573449 [RTC]rtc_osc_init,62: osc32con val = 0xde70
469 11:17:33.577118 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 11:17:33.588754 [RTC]rtc_get_frequency_meter,154: input=15, output=772
471 11:17:33.597612 [RTC]rtc_get_frequency_meter,154: input=23, output=956
472 11:17:33.607644 [RTC]rtc_get_frequency_meter,154: input=19, output=864
473 11:17:33.616760 [RTC]rtc_get_frequency_meter,154: input=17, output=818
474 11:17:33.625999 [RTC]rtc_get_frequency_meter,154: input=16, output=796
475 11:17:33.629515 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde70
476 11:17:33.636142 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
477 11:17:33.639772 [RTC]rtc_boot_common,220: irqsta=1, bbpu=81, con=486
478 11:17:33.643329 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
479 11:17:33.646161 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
480 11:17:33.649459 ADC[4]: Raw value=902876 ID=7
481 11:17:33.652806 ADC[3]: Raw value=213179 ID=1
482 11:17:33.656311 RAM Code: 0x71
483 11:17:33.660112 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
484 11:17:33.663002 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
485 11:17:33.673521 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
486 11:17:33.679509 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
487 11:17:33.682766 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
488 11:17:33.686379 in-header: 03 07 00 00 08 00 00 00
489 11:17:33.689686 in-data: aa e4 47 04 13 02 00 00
490 11:17:33.693150 Chrome EC: UHEPI supported
491 11:17:33.699968 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
492 11:17:33.702888 in-header: 03 ed 00 00 08 00 00 00
493 11:17:33.706035 in-data: 80 20 60 08 00 00 00 00
494 11:17:33.709202 MRC: failed to locate region type 0.
495 11:17:33.716141 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
496 11:17:33.719226 DRAM-K: Running full calibration
497 11:17:33.722648 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
498 11:17:33.725923 header.status = 0x0
499 11:17:33.729326 header.version = 0x6 (expected: 0x6)
500 11:17:33.732490 header.size = 0xd00 (expected: 0xd00)
501 11:17:33.736087 header.flags = 0x0
502 11:17:33.738821 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
503 11:17:33.758811 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
504 11:17:33.765622 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
505 11:17:33.769219 dram_init: ddr_geometry: 2
506 11:17:33.769792 [EMI] MDL number = 2
507 11:17:33.772853 [EMI] Get MDL freq = 0
508 11:17:33.773540 dram_init: ddr_type: 0
509 11:17:33.777123 is_discrete_lpddr4: 1
510 11:17:33.780665 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
511 11:17:33.781387
512 11:17:33.781769
513 11:17:33.784166 [Bian_co] ETT version 0.0.0.1
514 11:17:33.788032 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
515 11:17:33.788646
516 11:17:33.791802 dramc_set_vcore_voltage set vcore to 650000
517 11:17:33.792435 Read voltage for 800, 4
518 11:17:33.795497 Vio18 = 0
519 11:17:33.796225 Vcore = 650000
520 11:17:33.796611 Vdram = 0
521 11:17:33.798624 Vddq = 0
522 11:17:33.799152 Vmddr = 0
523 11:17:33.802813 dram_init: config_dvfs: 1
524 11:17:33.806227 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
525 11:17:33.810352 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
526 11:17:33.813309 [SwImpedanceCal] DRVP=9, DRVN=15, ODTN=9
527 11:17:33.820161 freq_region=0, Reg: DRVP=9, DRVN=15, ODTN=9
528 11:17:33.823380 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
529 11:17:33.826643 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
530 11:17:33.827114 MEM_TYPE=3, freq_sel=18
531 11:17:33.829807 sv_algorithm_assistance_LP4_1600
532 11:17:33.836700 ============ PULL DRAM RESETB DOWN ============
533 11:17:33.839951 ========== PULL DRAM RESETB DOWN end =========
534 11:17:33.843599 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
535 11:17:33.846509 ===================================
536 11:17:33.850061 LPDDR4 DRAM CONFIGURATION
537 11:17:33.853218 ===================================
538 11:17:33.857050 EX_ROW_EN[0] = 0x0
539 11:17:33.857523 EX_ROW_EN[1] = 0x0
540 11:17:33.860680 LP4Y_EN = 0x0
541 11:17:33.861296 WORK_FSP = 0x0
542 11:17:33.863681 WL = 0x2
543 11:17:33.864248 RL = 0x2
544 11:17:33.866772 BL = 0x2
545 11:17:33.867243 RPST = 0x0
546 11:17:33.870029 RD_PRE = 0x0
547 11:17:33.870601 WR_PRE = 0x1
548 11:17:33.873267 WR_PST = 0x0
549 11:17:33.873837 DBI_WR = 0x0
550 11:17:33.876700 DBI_RD = 0x0
551 11:17:33.877311 OTF = 0x1
552 11:17:33.880314 ===================================
553 11:17:33.883820 ===================================
554 11:17:33.887089 ANA top config
555 11:17:33.887563 ===================================
556 11:17:33.890772 DLL_ASYNC_EN = 0
557 11:17:33.894192 ALL_SLAVE_EN = 1
558 11:17:33.897032 NEW_RANK_MODE = 1
559 11:17:33.901080 DLL_IDLE_MODE = 1
560 11:17:33.901666 LP45_APHY_COMB_EN = 1
561 11:17:33.904562 TX_ODT_DIS = 1
562 11:17:33.907811 NEW_8X_MODE = 1
563 11:17:33.911107 ===================================
564 11:17:33.914562 ===================================
565 11:17:33.918262 data_rate = 1600
566 11:17:33.918863 CKR = 1
567 11:17:33.921549 DQ_P2S_RATIO = 8
568 11:17:33.924934 ===================================
569 11:17:33.927916 CA_P2S_RATIO = 8
570 11:17:33.931322 DQ_CA_OPEN = 0
571 11:17:33.934531 DQ_SEMI_OPEN = 0
572 11:17:33.937615 CA_SEMI_OPEN = 0
573 11:17:33.938086 CA_FULL_RATE = 0
574 11:17:33.941231 DQ_CKDIV4_EN = 1
575 11:17:33.944251 CA_CKDIV4_EN = 1
576 11:17:33.948200 CA_PREDIV_EN = 0
577 11:17:33.951161 PH8_DLY = 0
578 11:17:33.954503 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
579 11:17:33.954971 DQ_AAMCK_DIV = 4
580 11:17:33.958200 CA_AAMCK_DIV = 4
581 11:17:33.960964 CA_ADMCK_DIV = 4
582 11:17:33.964945 DQ_TRACK_CA_EN = 0
583 11:17:33.968405 CA_PICK = 800
584 11:17:33.971306 CA_MCKIO = 800
585 11:17:33.971930 MCKIO_SEMI = 0
586 11:17:33.974650 PLL_FREQ = 3068
587 11:17:33.978175 DQ_UI_PI_RATIO = 32
588 11:17:33.981335 CA_UI_PI_RATIO = 0
589 11:17:33.984734 ===================================
590 11:17:33.988145 ===================================
591 11:17:33.991273 memory_type:LPDDR4
592 11:17:33.991843 GP_NUM : 10
593 11:17:33.994242 SRAM_EN : 1
594 11:17:33.997858 MD32_EN : 0
595 11:17:34.001580 ===================================
596 11:17:34.002159 [ANA_INIT] >>>>>>>>>>>>>>
597 11:17:34.005077 <<<<<< [CONFIGURE PHASE]: ANA_TX
598 11:17:34.008985 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
599 11:17:34.012664 ===================================
600 11:17:34.016339 data_rate = 1600,PCW = 0X7600
601 11:17:34.016976 ===================================
602 11:17:34.020031 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
603 11:17:34.027146 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
604 11:17:34.030833 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
605 11:17:34.038321 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
606 11:17:34.041634 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
607 11:17:34.044951 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
608 11:17:34.045558 [ANA_INIT] flow start
609 11:17:34.048192 [ANA_INIT] PLL >>>>>>>>
610 11:17:34.051437 [ANA_INIT] PLL <<<<<<<<
611 11:17:34.051903 [ANA_INIT] MIDPI >>>>>>>>
612 11:17:34.054876 [ANA_INIT] MIDPI <<<<<<<<
613 11:17:34.057990 [ANA_INIT] DLL >>>>>>>>
614 11:17:34.058455 [ANA_INIT] flow end
615 11:17:34.061504 ============ LP4 DIFF to SE enter ============
616 11:17:34.067938 ============ LP4 DIFF to SE exit ============
617 11:17:34.068505 [ANA_INIT] <<<<<<<<<<<<<
618 11:17:34.071196 [Flow] Enable top DCM control >>>>>
619 11:17:34.075084 [Flow] Enable top DCM control <<<<<
620 11:17:34.078323 Enable DLL master slave shuffle
621 11:17:34.084660 ==============================================================
622 11:17:34.088501 Gating Mode config
623 11:17:34.091333 ==============================================================
624 11:17:34.094717 Config description:
625 11:17:34.104842 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
626 11:17:34.111313 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
627 11:17:34.114899 SELPH_MODE 0: By rank 1: By Phase
628 11:17:34.120973 ==============================================================
629 11:17:34.124707 GAT_TRACK_EN = 1
630 11:17:34.127920 RX_GATING_MODE = 2
631 11:17:34.131426 RX_GATING_TRACK_MODE = 2
632 11:17:34.131906 SELPH_MODE = 1
633 11:17:34.134678 PICG_EARLY_EN = 1
634 11:17:34.137909 VALID_LAT_VALUE = 1
635 11:17:34.144555 ==============================================================
636 11:17:34.148019 Enter into Gating configuration >>>>
637 11:17:34.151022 Exit from Gating configuration <<<<
638 11:17:34.154235 Enter into DVFS_PRE_config >>>>>
639 11:17:34.164835 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
640 11:17:34.167962 Exit from DVFS_PRE_config <<<<<
641 11:17:34.170965 Enter into PICG configuration >>>>
642 11:17:34.174645 Exit from PICG configuration <<<<
643 11:17:34.178067 [RX_INPUT] configuration >>>>>
644 11:17:34.181189 [RX_INPUT] configuration <<<<<
645 11:17:34.184890 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
646 11:17:34.191731 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
647 11:17:34.197960 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
648 11:17:34.204852 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
649 11:17:34.207730 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
650 11:17:34.214531 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
651 11:17:34.217671 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
652 11:17:34.224623 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
653 11:17:34.228142 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
654 11:17:34.231816 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
655 11:17:34.234862 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
656 11:17:34.241316 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
657 11:17:34.244833 ===================================
658 11:17:34.245413 LPDDR4 DRAM CONFIGURATION
659 11:17:34.248083 ===================================
660 11:17:34.251645 EX_ROW_EN[0] = 0x0
661 11:17:34.252217 EX_ROW_EN[1] = 0x0
662 11:17:34.255347 LP4Y_EN = 0x0
663 11:17:34.255924 WORK_FSP = 0x0
664 11:17:34.257686 WL = 0x2
665 11:17:34.261662 RL = 0x2
666 11:17:34.262232 BL = 0x2
667 11:17:34.264694 RPST = 0x0
668 11:17:34.265198 RD_PRE = 0x0
669 11:17:34.267930 WR_PRE = 0x1
670 11:17:34.268405 WR_PST = 0x0
671 11:17:34.271786 DBI_WR = 0x0
672 11:17:34.272369 DBI_RD = 0x0
673 11:17:34.274671 OTF = 0x1
674 11:17:34.277698 ===================================
675 11:17:34.281350 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
676 11:17:34.284424 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
677 11:17:34.288891 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
678 11:17:34.292190 ===================================
679 11:17:34.295298 LPDDR4 DRAM CONFIGURATION
680 11:17:34.298385 ===================================
681 11:17:34.302212 EX_ROW_EN[0] = 0x10
682 11:17:34.302774 EX_ROW_EN[1] = 0x0
683 11:17:34.306035 LP4Y_EN = 0x0
684 11:17:34.306603 WORK_FSP = 0x0
685 11:17:34.308757 WL = 0x2
686 11:17:34.309261 RL = 0x2
687 11:17:34.313148 BL = 0x2
688 11:17:34.313719 RPST = 0x0
689 11:17:34.316084 RD_PRE = 0x0
690 11:17:34.316652 WR_PRE = 0x1
691 11:17:34.319487 WR_PST = 0x0
692 11:17:34.320071 DBI_WR = 0x0
693 11:17:34.323221 DBI_RD = 0x0
694 11:17:34.323687 OTF = 0x1
695 11:17:34.326976 ===================================
696 11:17:34.333831 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
697 11:17:34.337349 nWR fixed to 40
698 11:17:34.337894 [ModeRegInit_LP4] CH0 RK0
699 11:17:34.341341 [ModeRegInit_LP4] CH0 RK1
700 11:17:34.344460 [ModeRegInit_LP4] CH1 RK0
701 11:17:34.344962 [ModeRegInit_LP4] CH1 RK1
702 11:17:34.348080 match AC timing 13
703 11:17:34.352029 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
704 11:17:34.355416 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
705 11:17:34.359104 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
706 11:17:34.366972 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
707 11:17:34.370590 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
708 11:17:34.371192 [EMI DOE] emi_dcm 0
709 11:17:34.377419 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
710 11:17:34.377893 ==
711 11:17:34.378273 Dram Type= 6, Freq= 0, CH_0, rank 0
712 11:17:34.385079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
713 11:17:34.385570 ==
714 11:17:34.388813 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
715 11:17:34.396060 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
716 11:17:34.404396 [CA 0] Center 37 (7~68) winsize 62
717 11:17:34.408404 [CA 1] Center 38 (7~69) winsize 63
718 11:17:34.411818 [CA 2] Center 35 (5~66) winsize 62
719 11:17:34.415463 [CA 3] Center 35 (5~66) winsize 62
720 11:17:34.418672 [CA 4] Center 34 (4~65) winsize 62
721 11:17:34.421875 [CA 5] Center 33 (3~64) winsize 62
722 11:17:34.422466
723 11:17:34.425379 [CmdBusTrainingLP45] Vref(ca) range 1: 32
724 11:17:34.425976
725 11:17:34.428916 [CATrainingPosCal] consider 1 rank data
726 11:17:34.433412 u2DelayCellTimex100 = 270/100 ps
727 11:17:34.436571 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
728 11:17:34.440273 CA1 delay=38 (7~69),Diff = 5 PI (36 cell)
729 11:17:34.444094 CA2 delay=35 (5~66),Diff = 2 PI (14 cell)
730 11:17:34.447419 CA3 delay=35 (5~66),Diff = 2 PI (14 cell)
731 11:17:34.451152 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
732 11:17:34.454724 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
733 11:17:34.455202
734 11:17:34.458306 CA PerBit enable=1, Macro0, CA PI delay=33
735 11:17:34.458884
736 11:17:34.462549 [CBTSetCACLKResult] CA Dly = 33
737 11:17:34.463136 CS Dly: 5 (0~36)
738 11:17:34.463529 ==
739 11:17:34.465762 Dram Type= 6, Freq= 0, CH_0, rank 1
740 11:17:34.469678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
741 11:17:34.470265 ==
742 11:17:34.476703 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
743 11:17:34.480087 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
744 11:17:34.490926 [CA 0] Center 38 (7~69) winsize 63
745 11:17:34.494389 [CA 1] Center 38 (7~69) winsize 63
746 11:17:34.497997 [CA 2] Center 36 (5~67) winsize 63
747 11:17:34.501831 [CA 3] Center 35 (5~66) winsize 62
748 11:17:34.505298 [CA 4] Center 35 (4~66) winsize 63
749 11:17:34.508863 [CA 5] Center 34 (4~65) winsize 62
750 11:17:34.509296
751 11:17:34.512963 [CmdBusTrainingLP45] Vref(ca) range 1: 34
752 11:17:34.513416
753 11:17:34.516740 [CATrainingPosCal] consider 2 rank data
754 11:17:34.517422 u2DelayCellTimex100 = 270/100 ps
755 11:17:34.520688 CA0 delay=37 (7~68),Diff = 3 PI (21 cell)
756 11:17:34.524399 CA1 delay=38 (7~69),Diff = 4 PI (28 cell)
757 11:17:34.528017 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
758 11:17:34.531401 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
759 11:17:34.535273 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
760 11:17:34.539054 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
761 11:17:34.539616
762 11:17:34.542877 CA PerBit enable=1, Macro0, CA PI delay=34
763 11:17:34.543441
764 11:17:34.546170 [CBTSetCACLKResult] CA Dly = 34
765 11:17:34.549595 CS Dly: 6 (0~38)
766 11:17:34.550032
767 11:17:34.553600 ----->DramcWriteLeveling(PI) begin...
768 11:17:34.554082 ==
769 11:17:34.557477 Dram Type= 6, Freq= 0, CH_0, rank 0
770 11:17:34.561394 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
771 11:17:34.561995 ==
772 11:17:34.564920 Write leveling (Byte 0): 33 => 33
773 11:17:34.565518 Write leveling (Byte 1): 30 => 30
774 11:17:34.568115 DramcWriteLeveling(PI) end<-----
775 11:17:34.568596
776 11:17:34.569009 ==
777 11:17:34.571676 Dram Type= 6, Freq= 0, CH_0, rank 0
778 11:17:34.575731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
779 11:17:34.576344 ==
780 11:17:34.579234 [Gating] SW mode calibration
781 11:17:34.586769 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
782 11:17:34.590475 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
783 11:17:34.598323 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
784 11:17:34.602131 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
785 11:17:34.605643 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
786 11:17:34.609330 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 11:17:34.612741 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 11:17:34.616686 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 11:17:34.623685 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 11:17:34.626909 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 11:17:34.630053 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 11:17:34.636661 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 11:17:34.640381 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 11:17:34.643287 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 11:17:34.649816 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 11:17:34.653596 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 11:17:34.656627 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 11:17:34.663591 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 11:17:34.666832 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
800 11:17:34.669920 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
801 11:17:34.676413 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
802 11:17:34.680001 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 11:17:34.683279 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 11:17:34.689483 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 11:17:34.693447 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 11:17:34.696320 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 11:17:34.703721 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 11:17:34.706277 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
809 11:17:34.709425 0 9 8 | B1->B0 | 2322 3232 | 1 0 | (1 1) (0 0)
810 11:17:34.716186 0 9 12 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
811 11:17:34.719170 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 11:17:34.722645 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 11:17:34.729619 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
814 11:17:34.732415 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 11:17:34.736127 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 11:17:34.742283 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 0) (1 1)
817 11:17:34.745793 0 10 8 | B1->B0 | 2f2f 2323 | 0 0 | (0 0) (0 0)
818 11:17:34.749139 0 10 12 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
819 11:17:34.755637 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 11:17:34.759426 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 11:17:34.762256 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 11:17:34.768926 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 11:17:34.772452 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 11:17:34.775536 0 11 4 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
825 11:17:34.782230 0 11 8 | B1->B0 | 2e2d 4646 | 1 0 | (0 0) (0 0)
826 11:17:34.785783 0 11 12 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
827 11:17:34.788868 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 11:17:34.795239 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 11:17:34.798600 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
830 11:17:34.801666 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 11:17:34.808483 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 11:17:34.811796 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
833 11:17:34.815204 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
834 11:17:34.821924 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 11:17:34.825242 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 11:17:34.828826 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 11:17:34.831694 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 11:17:34.838615 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 11:17:34.841470 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 11:17:34.845203 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 11:17:34.851758 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 11:17:34.855056 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 11:17:34.858386 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 11:17:34.864923 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 11:17:34.868715 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 11:17:34.871981 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 11:17:34.878562 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
848 11:17:34.881668 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
849 11:17:34.885432 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
850 11:17:34.888432 Total UI for P1: 0, mck2ui 16
851 11:17:34.891668 best dqsien dly found for B0: ( 0, 14, 2)
852 11:17:34.898236 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
853 11:17:34.898839 Total UI for P1: 0, mck2ui 16
854 11:17:34.904732 best dqsien dly found for B1: ( 0, 14, 8)
855 11:17:34.907961 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
856 11:17:34.911619 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
857 11:17:34.912191
858 11:17:34.914614 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
859 11:17:34.918337 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
860 11:17:34.921488 [Gating] SW calibration Done
861 11:17:34.922059 ==
862 11:17:34.924665 Dram Type= 6, Freq= 0, CH_0, rank 0
863 11:17:34.928229 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
864 11:17:34.928704 ==
865 11:17:34.931994 RX Vref Scan: 0
866 11:17:34.932577
867 11:17:34.933010 RX Vref 0 -> 0, step: 1
868 11:17:34.933367
869 11:17:34.935130 RX Delay -130 -> 252, step: 16
870 11:17:34.938134 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
871 11:17:34.944703 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
872 11:17:34.948391 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
873 11:17:34.951406 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
874 11:17:34.954843 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
875 11:17:34.958180 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
876 11:17:34.965050 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
877 11:17:34.967830 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
878 11:17:34.971231 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
879 11:17:34.974910 iDelay=222, Bit 9, Center 69 (-34 ~ 173) 208
880 11:17:34.977778 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
881 11:17:34.984841 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
882 11:17:34.987912 iDelay=222, Bit 12, Center 77 (-34 ~ 189) 224
883 11:17:34.991073 iDelay=222, Bit 13, Center 77 (-34 ~ 189) 224
884 11:17:34.994765 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
885 11:17:35.000888 iDelay=222, Bit 15, Center 77 (-34 ~ 189) 224
886 11:17:35.001464 ==
887 11:17:35.004496 Dram Type= 6, Freq= 0, CH_0, rank 0
888 11:17:35.007623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
889 11:17:35.008094 ==
890 11:17:35.008468 DQS Delay:
891 11:17:35.011393 DQS0 = 0, DQS1 = 0
892 11:17:35.011859 DQM Delay:
893 11:17:35.014116 DQM0 = 89, DQM1 = 78
894 11:17:35.014582 DQ Delay:
895 11:17:35.017405 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
896 11:17:35.020962 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =101
897 11:17:35.024147 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
898 11:17:35.027572 DQ12 =77, DQ13 =77, DQ14 =93, DQ15 =77
899 11:17:35.028142
900 11:17:35.028519
901 11:17:35.028912 ==
902 11:17:35.030919 Dram Type= 6, Freq= 0, CH_0, rank 0
903 11:17:35.034175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
904 11:17:35.034667 ==
905 11:17:35.037701
906 11:17:35.038195
907 11:17:35.038807 TX Vref Scan disable
908 11:17:35.040649 == TX Byte 0 ==
909 11:17:35.044452 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
910 11:17:35.047608 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
911 11:17:35.050985 == TX Byte 1 ==
912 11:17:35.054447 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
913 11:17:35.057370 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
914 11:17:35.057850 ==
915 11:17:35.060624 Dram Type= 6, Freq= 0, CH_0, rank 0
916 11:17:35.067765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
917 11:17:35.068352 ==
918 11:17:35.079661 TX Vref=22, minBit 8, minWin=26, winSum=436
919 11:17:35.083835 TX Vref=24, minBit 11, minWin=26, winSum=443
920 11:17:35.086387 TX Vref=26, minBit 8, minWin=27, winSum=444
921 11:17:35.090035 TX Vref=28, minBit 10, minWin=27, winSum=451
922 11:17:35.093191 TX Vref=30, minBit 3, minWin=28, winSum=454
923 11:17:35.099895 TX Vref=32, minBit 3, minWin=28, winSum=454
924 11:17:35.102870 [TxChooseVref] Worse bit 3, Min win 28, Win sum 454, Final Vref 30
925 11:17:35.103462
926 11:17:35.106228 Final TX Range 1 Vref 30
927 11:17:35.106705
928 11:17:35.107083 ==
929 11:17:35.109371 Dram Type= 6, Freq= 0, CH_0, rank 0
930 11:17:35.112930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
931 11:17:35.116309 ==
932 11:17:35.116929
933 11:17:35.117316
934 11:17:35.117692 TX Vref Scan disable
935 11:17:35.120146 == TX Byte 0 ==
936 11:17:35.122904 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
937 11:17:35.129497 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
938 11:17:35.130068 == TX Byte 1 ==
939 11:17:35.133086 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
940 11:17:35.139507 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
941 11:17:35.140222
942 11:17:35.140837 [DATLAT]
943 11:17:35.141241 Freq=800, CH0 RK0
944 11:17:35.141595
945 11:17:35.143287 DATLAT Default: 0xa
946 11:17:35.143763 0, 0xFFFF, sum = 0
947 11:17:35.146181 1, 0xFFFF, sum = 0
948 11:17:35.146665 2, 0xFFFF, sum = 0
949 11:17:35.150120 3, 0xFFFF, sum = 0
950 11:17:35.150603 4, 0xFFFF, sum = 0
951 11:17:35.152979 5, 0xFFFF, sum = 0
952 11:17:35.156123 6, 0xFFFF, sum = 0
953 11:17:35.156604 7, 0xFFFF, sum = 0
954 11:17:35.159970 8, 0xFFFF, sum = 0
955 11:17:35.160562 9, 0x0, sum = 1
956 11:17:35.161010 10, 0x0, sum = 2
957 11:17:35.163277 11, 0x0, sum = 3
958 11:17:35.163905 12, 0x0, sum = 4
959 11:17:35.166552 best_step = 10
960 11:17:35.167128
961 11:17:35.167511 ==
962 11:17:35.169556 Dram Type= 6, Freq= 0, CH_0, rank 0
963 11:17:35.173464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
964 11:17:35.174052 ==
965 11:17:35.176572 RX Vref Scan: 1
966 11:17:35.177190
967 11:17:35.177574 Set Vref Range= 32 -> 127
968 11:17:35.177929
969 11:17:35.180027 RX Vref 32 -> 127, step: 1
970 11:17:35.180620
971 11:17:35.183404 RX Delay -79 -> 252, step: 8
972 11:17:35.183982
973 11:17:35.186693 Set Vref, RX VrefLevel [Byte0]: 32
974 11:17:35.189970 [Byte1]: 32
975 11:17:35.190554
976 11:17:35.193264 Set Vref, RX VrefLevel [Byte0]: 33
977 11:17:35.196567 [Byte1]: 33
978 11:17:35.200020
979 11:17:35.200604 Set Vref, RX VrefLevel [Byte0]: 34
980 11:17:35.203437 [Byte1]: 34
981 11:17:35.207582
982 11:17:35.208158 Set Vref, RX VrefLevel [Byte0]: 35
983 11:17:35.211099 [Byte1]: 35
984 11:17:35.215273
985 11:17:35.215854 Set Vref, RX VrefLevel [Byte0]: 36
986 11:17:35.218302 [Byte1]: 36
987 11:17:35.222742
988 11:17:35.223377 Set Vref, RX VrefLevel [Byte0]: 37
989 11:17:35.225601 [Byte1]: 37
990 11:17:35.230266
991 11:17:35.230842 Set Vref, RX VrefLevel [Byte0]: 38
992 11:17:35.233564 [Byte1]: 38
993 11:17:35.237689
994 11:17:35.238264 Set Vref, RX VrefLevel [Byte0]: 39
995 11:17:35.240887 [Byte1]: 39
996 11:17:35.245205
997 11:17:35.245797 Set Vref, RX VrefLevel [Byte0]: 40
998 11:17:35.248596 [Byte1]: 40
999 11:17:35.253141
1000 11:17:35.253722 Set Vref, RX VrefLevel [Byte0]: 41
1001 11:17:35.256501 [Byte1]: 41
1002 11:17:35.260612
1003 11:17:35.261399 Set Vref, RX VrefLevel [Byte0]: 42
1004 11:17:35.263906 [Byte1]: 42
1005 11:17:35.268348
1006 11:17:35.269098 Set Vref, RX VrefLevel [Byte0]: 43
1007 11:17:35.271657 [Byte1]: 43
1008 11:17:35.275810
1009 11:17:35.276283 Set Vref, RX VrefLevel [Byte0]: 44
1010 11:17:35.278780 [Byte1]: 44
1011 11:17:35.283508
1012 11:17:35.284084 Set Vref, RX VrefLevel [Byte0]: 45
1013 11:17:35.286341 [Byte1]: 45
1014 11:17:35.290537
1015 11:17:35.291111 Set Vref, RX VrefLevel [Byte0]: 46
1016 11:17:35.294065 [Byte1]: 46
1017 11:17:35.298323
1018 11:17:35.298904 Set Vref, RX VrefLevel [Byte0]: 47
1019 11:17:35.301722 [Byte1]: 47
1020 11:17:35.305621
1021 11:17:35.306202 Set Vref, RX VrefLevel [Byte0]: 48
1022 11:17:35.309082 [Byte1]: 48
1023 11:17:35.313128
1024 11:17:35.313770 Set Vref, RX VrefLevel [Byte0]: 49
1025 11:17:35.316849 [Byte1]: 49
1026 11:17:35.320834
1027 11:17:35.321408 Set Vref, RX VrefLevel [Byte0]: 50
1028 11:17:35.324001 [Byte1]: 50
1029 11:17:35.328342
1030 11:17:35.328959 Set Vref, RX VrefLevel [Byte0]: 51
1031 11:17:35.331763 [Byte1]: 51
1032 11:17:35.336101
1033 11:17:35.336672 Set Vref, RX VrefLevel [Byte0]: 52
1034 11:17:35.339075 [Byte1]: 52
1035 11:17:35.343600
1036 11:17:35.344180 Set Vref, RX VrefLevel [Byte0]: 53
1037 11:17:35.346428 [Byte1]: 53
1038 11:17:35.350765
1039 11:17:35.351229 Set Vref, RX VrefLevel [Byte0]: 54
1040 11:17:35.354043 [Byte1]: 54
1041 11:17:35.358487
1042 11:17:35.358953 Set Vref, RX VrefLevel [Byte0]: 55
1043 11:17:35.362233 [Byte1]: 55
1044 11:17:35.366232
1045 11:17:35.366801 Set Vref, RX VrefLevel [Byte0]: 56
1046 11:17:35.369599 [Byte1]: 56
1047 11:17:35.374020
1048 11:17:35.374622 Set Vref, RX VrefLevel [Byte0]: 57
1049 11:17:35.376870 [Byte1]: 57
1050 11:17:35.381313
1051 11:17:35.381883 Set Vref, RX VrefLevel [Byte0]: 58
1052 11:17:35.384541 [Byte1]: 58
1053 11:17:35.389123
1054 11:17:35.389703 Set Vref, RX VrefLevel [Byte0]: 59
1055 11:17:35.391735 [Byte1]: 59
1056 11:17:35.396462
1057 11:17:35.397121 Set Vref, RX VrefLevel [Byte0]: 60
1058 11:17:35.399481 [Byte1]: 60
1059 11:17:35.403994
1060 11:17:35.404574 Set Vref, RX VrefLevel [Byte0]: 61
1061 11:17:35.407294 [Byte1]: 61
1062 11:17:35.411330
1063 11:17:35.411900 Set Vref, RX VrefLevel [Byte0]: 62
1064 11:17:35.414471 [Byte1]: 62
1065 11:17:35.418987
1066 11:17:35.419556 Set Vref, RX VrefLevel [Byte0]: 63
1067 11:17:35.421905 [Byte1]: 63
1068 11:17:35.426374
1069 11:17:35.426959 Set Vref, RX VrefLevel [Byte0]: 64
1070 11:17:35.429515 [Byte1]: 64
1071 11:17:35.433638
1072 11:17:35.434108 Set Vref, RX VrefLevel [Byte0]: 65
1073 11:17:35.437473 [Byte1]: 65
1074 11:17:35.441466
1075 11:17:35.442028 Set Vref, RX VrefLevel [Byte0]: 66
1076 11:17:35.444920 [Byte1]: 66
1077 11:17:35.449463
1078 11:17:35.450032 Set Vref, RX VrefLevel [Byte0]: 67
1079 11:17:35.452890 [Byte1]: 67
1080 11:17:35.456652
1081 11:17:35.457299 Set Vref, RX VrefLevel [Byte0]: 68
1082 11:17:35.459803 [Byte1]: 68
1083 11:17:35.464247
1084 11:17:35.464848 Set Vref, RX VrefLevel [Byte0]: 69
1085 11:17:35.470637 [Byte1]: 69
1086 11:17:35.471217
1087 11:17:35.473861 Set Vref, RX VrefLevel [Byte0]: 70
1088 11:17:35.476892 [Byte1]: 70
1089 11:17:35.477363
1090 11:17:35.480726 Set Vref, RX VrefLevel [Byte0]: 71
1091 11:17:35.483996 [Byte1]: 71
1092 11:17:35.484568
1093 11:17:35.487316 Set Vref, RX VrefLevel [Byte0]: 72
1094 11:17:35.490680 [Byte1]: 72
1095 11:17:35.494301
1096 11:17:35.494765 Set Vref, RX VrefLevel [Byte0]: 73
1097 11:17:35.498007 [Byte1]: 73
1098 11:17:35.502014
1099 11:17:35.502584 Set Vref, RX VrefLevel [Byte0]: 74
1100 11:17:35.505767 [Byte1]: 74
1101 11:17:35.509641
1102 11:17:35.510111 Set Vref, RX VrefLevel [Byte0]: 75
1103 11:17:35.512737 [Byte1]: 75
1104 11:17:35.517064
1105 11:17:35.517632 Set Vref, RX VrefLevel [Byte0]: 76
1106 11:17:35.520262 [Byte1]: 76
1107 11:17:35.524733
1108 11:17:35.525339 Final RX Vref Byte 0 = 62 to rank0
1109 11:17:35.527826 Final RX Vref Byte 1 = 62 to rank0
1110 11:17:35.531228 Final RX Vref Byte 0 = 62 to rank1
1111 11:17:35.534606 Final RX Vref Byte 1 = 62 to rank1==
1112 11:17:35.537638 Dram Type= 6, Freq= 0, CH_0, rank 0
1113 11:17:35.544806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1114 11:17:35.545376 ==
1115 11:17:35.545751 DQS Delay:
1116 11:17:35.547432 DQS0 = 0, DQS1 = 0
1117 11:17:35.547897 DQM Delay:
1118 11:17:35.548265 DQM0 = 93, DQM1 = 83
1119 11:17:35.550983 DQ Delay:
1120 11:17:35.554280 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =88
1121 11:17:35.557611 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =104
1122 11:17:35.561091 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =80
1123 11:17:35.564214 DQ12 =88, DQ13 =84, DQ14 =92, DQ15 =92
1124 11:17:35.564823
1125 11:17:35.565212
1126 11:17:35.570825 [DQSOSCAuto] RK0, (LSB)MR18= 0x3834, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
1127 11:17:35.574289 CH0 RK0: MR19=606, MR18=3834
1128 11:17:35.581066 CH0_RK0: MR19=0x606, MR18=0x3834, DQSOSC=395, MR23=63, INC=94, DEC=63
1129 11:17:35.581638
1130 11:17:35.584428 ----->DramcWriteLeveling(PI) begin...
1131 11:17:35.585063 ==
1132 11:17:35.587663 Dram Type= 6, Freq= 0, CH_0, rank 1
1133 11:17:35.590907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1134 11:17:35.591382 ==
1135 11:17:35.594065 Write leveling (Byte 0): 33 => 33
1136 11:17:35.597658 Write leveling (Byte 1): 29 => 29
1137 11:17:35.601236 DramcWriteLeveling(PI) end<-----
1138 11:17:35.601800
1139 11:17:35.602169 ==
1140 11:17:35.604313 Dram Type= 6, Freq= 0, CH_0, rank 1
1141 11:17:35.607591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1142 11:17:35.608152 ==
1143 11:17:35.610767 [Gating] SW mode calibration
1144 11:17:35.617648 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1145 11:17:35.624273 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1146 11:17:35.627297 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1147 11:17:35.633779 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1148 11:17:35.637415 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1149 11:17:35.640905 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1150 11:17:35.647204 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 11:17:35.650326 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 11:17:35.694604 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 11:17:35.695510 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 11:17:35.695905 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 11:17:35.696257 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 11:17:35.696590 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 11:17:35.696936 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 11:17:35.697321 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 11:17:35.697728 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 11:17:35.698052 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 11:17:35.698364 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 11:17:35.738681 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1163 11:17:35.739278 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1164 11:17:35.739666 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 11:17:35.740333 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 11:17:35.740698 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 11:17:35.741073 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 11:17:35.741461 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 11:17:35.741846 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 11:17:35.742317 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 11:17:35.742653 0 9 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
1172 11:17:35.744159 0 9 8 | B1->B0 | 2d2d 3333 | 0 1 | (0 0) (0 0)
1173 11:17:35.747432 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1174 11:17:35.750889 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1175 11:17:35.754038 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1176 11:17:35.761127 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1177 11:17:35.764226 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 11:17:35.767896 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 11:17:35.774152 0 10 4 | B1->B0 | 3333 2f2f | 0 1 | (0 1) (1 0)
1180 11:17:35.777444 0 10 8 | B1->B0 | 2d2d 2424 | 0 0 | (1 0) (0 0)
1181 11:17:35.780847 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 11:17:35.787849 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 11:17:35.791376 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 11:17:35.794404 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 11:17:35.801030 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 11:17:35.804444 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 11:17:35.807685 0 11 4 | B1->B0 | 2424 2e2e | 0 0 | (0 0) (0 0)
1188 11:17:35.814650 0 11 8 | B1->B0 | 3b3b 4545 | 0 0 | (1 1) (0 0)
1189 11:17:35.817472 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1190 11:17:35.821299 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1191 11:17:35.824468 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1192 11:17:35.831613 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1193 11:17:35.834534 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 11:17:35.838414 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 11:17:35.842259 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1196 11:17:35.849359 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 11:17:35.852373 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 11:17:35.856136 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 11:17:35.859676 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 11:17:35.866117 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 11:17:35.869508 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 11:17:35.872822 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 11:17:35.879353 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 11:17:35.883098 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 11:17:35.886692 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 11:17:35.893067 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 11:17:35.896348 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 11:17:35.899639 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 11:17:35.906253 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 11:17:35.909629 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 11:17:35.912901 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1212 11:17:35.919577 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1213 11:17:35.920137 Total UI for P1: 0, mck2ui 16
1214 11:17:35.926230 best dqsien dly found for B0: ( 0, 14, 4)
1215 11:17:35.926788 Total UI for P1: 0, mck2ui 16
1216 11:17:35.929672 best dqsien dly found for B1: ( 0, 14, 4)
1217 11:17:35.936095 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1218 11:17:35.939433 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1219 11:17:35.939992
1220 11:17:35.942748 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1221 11:17:35.946257 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1222 11:17:35.949374 [Gating] SW calibration Done
1223 11:17:35.949943 ==
1224 11:17:35.952594 Dram Type= 6, Freq= 0, CH_0, rank 1
1225 11:17:35.956235 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1226 11:17:35.956830 ==
1227 11:17:35.959478 RX Vref Scan: 0
1228 11:17:35.960032
1229 11:17:35.960394 RX Vref 0 -> 0, step: 1
1230 11:17:35.960733
1231 11:17:35.962911 RX Delay -130 -> 252, step: 16
1232 11:17:35.966020 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1233 11:17:35.972701 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1234 11:17:35.975893 iDelay=206, Bit 2, Center 85 (-34 ~ 205) 240
1235 11:17:35.979187 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1236 11:17:35.982476 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1237 11:17:35.985697 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1238 11:17:35.989374 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1239 11:17:35.995434 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1240 11:17:35.998750 iDelay=206, Bit 8, Center 69 (-34 ~ 173) 208
1241 11:17:36.002293 iDelay=206, Bit 9, Center 69 (-34 ~ 173) 208
1242 11:17:36.005671 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1243 11:17:36.012495 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1244 11:17:36.016017 iDelay=206, Bit 12, Center 77 (-34 ~ 189) 224
1245 11:17:36.019281 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1246 11:17:36.022109 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1247 11:17:36.025609 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1248 11:17:36.029031 ==
1249 11:17:36.029597 Dram Type= 6, Freq= 0, CH_0, rank 1
1250 11:17:36.035928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1251 11:17:36.036636 ==
1252 11:17:36.037166 DQS Delay:
1253 11:17:36.039182 DQS0 = 0, DQS1 = 0
1254 11:17:36.039866 DQM Delay:
1255 11:17:36.041940 DQM0 = 87, DQM1 = 80
1256 11:17:36.042405 DQ Delay:
1257 11:17:36.045410 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =77
1258 11:17:36.049190 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1259 11:17:36.051938 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =77
1260 11:17:36.055490 DQ12 =77, DQ13 =85, DQ14 =93, DQ15 =93
1261 11:17:36.055954
1262 11:17:36.056317
1263 11:17:36.056726 ==
1264 11:17:36.058830 Dram Type= 6, Freq= 0, CH_0, rank 1
1265 11:17:36.062347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1266 11:17:36.062917 ==
1267 11:17:36.063291
1268 11:17:36.063634
1269 11:17:36.065935 TX Vref Scan disable
1270 11:17:36.068808 == TX Byte 0 ==
1271 11:17:36.072513 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1272 11:17:36.075674 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1273 11:17:36.079347 == TX Byte 1 ==
1274 11:17:36.082053 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1275 11:17:36.085520 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1276 11:17:36.086103 ==
1277 11:17:36.088640 Dram Type= 6, Freq= 0, CH_0, rank 1
1278 11:17:36.092420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1279 11:17:36.092930 ==
1280 11:17:36.106701 TX Vref=22, minBit 3, minWin=27, winSum=446
1281 11:17:36.110140 TX Vref=24, minBit 8, minWin=26, winSum=446
1282 11:17:36.113274 TX Vref=26, minBit 8, minWin=27, winSum=447
1283 11:17:36.116952 TX Vref=28, minBit 8, minWin=27, winSum=451
1284 11:17:36.120648 TX Vref=30, minBit 1, minWin=28, winSum=456
1285 11:17:36.126858 TX Vref=32, minBit 8, minWin=27, winSum=455
1286 11:17:36.130108 [TxChooseVref] Worse bit 1, Min win 28, Win sum 456, Final Vref 30
1287 11:17:36.130578
1288 11:17:36.133967 Final TX Range 1 Vref 30
1289 11:17:36.134536
1290 11:17:36.134906 ==
1291 11:17:36.136832 Dram Type= 6, Freq= 0, CH_0, rank 1
1292 11:17:36.139898 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1293 11:17:36.143031 ==
1294 11:17:36.143481
1295 11:17:36.143835
1296 11:17:36.144166 TX Vref Scan disable
1297 11:17:36.146858 == TX Byte 0 ==
1298 11:17:36.150047 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1299 11:17:36.156985 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1300 11:17:36.157395 == TX Byte 1 ==
1301 11:17:36.160175 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1302 11:17:36.167321 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1303 11:17:36.167827
1304 11:17:36.168153 [DATLAT]
1305 11:17:36.168456 Freq=800, CH0 RK1
1306 11:17:36.168749
1307 11:17:36.170481 DATLAT Default: 0xa
1308 11:17:36.170989 0, 0xFFFF, sum = 0
1309 11:17:36.173492 1, 0xFFFF, sum = 0
1310 11:17:36.174014 2, 0xFFFF, sum = 0
1311 11:17:36.176631 3, 0xFFFF, sum = 0
1312 11:17:36.180735 4, 0xFFFF, sum = 0
1313 11:17:36.181287 5, 0xFFFF, sum = 0
1314 11:17:36.183524 6, 0xFFFF, sum = 0
1315 11:17:36.184041 7, 0xFFFF, sum = 0
1316 11:17:36.186645 8, 0xFFFF, sum = 0
1317 11:17:36.187060 9, 0x0, sum = 1
1318 11:17:36.187388 10, 0x0, sum = 2
1319 11:17:36.190709 11, 0x0, sum = 3
1320 11:17:36.191231 12, 0x0, sum = 4
1321 11:17:36.193705 best_step = 10
1322 11:17:36.194115
1323 11:17:36.194503 ==
1324 11:17:36.196725 Dram Type= 6, Freq= 0, CH_0, rank 1
1325 11:17:36.200319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1326 11:17:36.201046 ==
1327 11:17:36.203215 RX Vref Scan: 0
1328 11:17:36.203632
1329 11:17:36.203953 RX Vref 0 -> 0, step: 1
1330 11:17:36.204254
1331 11:17:36.206868 RX Delay -79 -> 252, step: 8
1332 11:17:36.213587 iDelay=209, Bit 0, Center 88 (-23 ~ 200) 224
1333 11:17:36.217034 iDelay=209, Bit 1, Center 96 (-15 ~ 208) 224
1334 11:17:36.220463 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1335 11:17:36.223465 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
1336 11:17:36.227402 iDelay=209, Bit 4, Center 92 (-15 ~ 200) 216
1337 11:17:36.233839 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1338 11:17:36.237316 iDelay=209, Bit 6, Center 100 (-7 ~ 208) 216
1339 11:17:36.240577 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1340 11:17:36.243745 iDelay=209, Bit 8, Center 76 (-23 ~ 176) 200
1341 11:17:36.247171 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1342 11:17:36.253654 iDelay=209, Bit 10, Center 84 (-15 ~ 184) 200
1343 11:17:36.257021 iDelay=209, Bit 11, Center 76 (-23 ~ 176) 200
1344 11:17:36.260186 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1345 11:17:36.264110 iDelay=209, Bit 13, Center 88 (-15 ~ 192) 208
1346 11:17:36.267014 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1347 11:17:36.273606 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1348 11:17:36.274165 ==
1349 11:17:36.277110 Dram Type= 6, Freq= 0, CH_0, rank 1
1350 11:17:36.280295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1351 11:17:36.280876 ==
1352 11:17:36.281243 DQS Delay:
1353 11:17:36.283851 DQS0 = 0, DQS1 = 0
1354 11:17:36.284401 DQM Delay:
1355 11:17:36.286788 DQM0 = 92, DQM1 = 83
1356 11:17:36.287338 DQ Delay:
1357 11:17:36.290121 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1358 11:17:36.293308 DQ4 =92, DQ5 =84, DQ6 =100, DQ7 =100
1359 11:17:36.297027 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1360 11:17:36.300479 DQ12 =88, DQ13 =88, DQ14 =92, DQ15 =92
1361 11:17:36.301094
1362 11:17:36.301490
1363 11:17:36.310112 [DQSOSCAuto] RK1, (LSB)MR18= 0x421d, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 393 ps
1364 11:17:36.310680 CH0 RK1: MR19=606, MR18=421D
1365 11:17:36.316372 CH0_RK1: MR19=0x606, MR18=0x421D, DQSOSC=393, MR23=63, INC=95, DEC=63
1366 11:17:36.320004 [RxdqsGatingPostProcess] freq 800
1367 11:17:36.326687 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1368 11:17:36.329809 Pre-setting of DQS Precalculation
1369 11:17:36.333131 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1370 11:17:36.333705 ==
1371 11:17:36.336995 Dram Type= 6, Freq= 0, CH_1, rank 0
1372 11:17:36.342974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1373 11:17:36.343453 ==
1374 11:17:36.346456 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1375 11:17:36.353205 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1376 11:17:36.362210 [CA 0] Center 36 (6~67) winsize 62
1377 11:17:36.365464 [CA 1] Center 36 (6~67) winsize 62
1378 11:17:36.368567 [CA 2] Center 34 (4~65) winsize 62
1379 11:17:36.371835 [CA 3] Center 34 (3~65) winsize 63
1380 11:17:36.374920 [CA 4] Center 34 (4~65) winsize 62
1381 11:17:36.378306 [CA 5] Center 33 (3~64) winsize 62
1382 11:17:36.378732
1383 11:17:36.381855 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1384 11:17:36.382279
1385 11:17:36.385372 [CATrainingPosCal] consider 1 rank data
1386 11:17:36.388242 u2DelayCellTimex100 = 270/100 ps
1387 11:17:36.392204 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1388 11:17:36.399043 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1389 11:17:36.401805 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1390 11:17:36.405169 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1391 11:17:36.408682 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1392 11:17:36.411581 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1393 11:17:36.412054
1394 11:17:36.415403 CA PerBit enable=1, Macro0, CA PI delay=33
1395 11:17:36.416044
1396 11:17:36.418017 [CBTSetCACLKResult] CA Dly = 33
1397 11:17:36.418484 CS Dly: 5 (0~36)
1398 11:17:36.421809 ==
1399 11:17:36.424757 Dram Type= 6, Freq= 0, CH_1, rank 1
1400 11:17:36.428483 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1401 11:17:36.428987 ==
1402 11:17:36.431850 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1403 11:17:36.438472 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1404 11:17:36.448547 [CA 0] Center 36 (6~67) winsize 62
1405 11:17:36.451693 [CA 1] Center 37 (6~68) winsize 63
1406 11:17:36.454982 [CA 2] Center 35 (5~66) winsize 62
1407 11:17:36.457938 [CA 3] Center 34 (4~65) winsize 62
1408 11:17:36.461711 [CA 4] Center 34 (4~65) winsize 62
1409 11:17:36.464866 [CA 5] Center 33 (3~64) winsize 62
1410 11:17:36.465429
1411 11:17:36.468082 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1412 11:17:36.468551
1413 11:17:36.471877 [CATrainingPosCal] consider 2 rank data
1414 11:17:36.474980 u2DelayCellTimex100 = 270/100 ps
1415 11:17:36.478188 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1416 11:17:36.485174 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1417 11:17:36.488217 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1418 11:17:36.491616 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1419 11:17:36.494554 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1420 11:17:36.498455 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1421 11:17:36.499024
1422 11:17:36.502131 CA PerBit enable=1, Macro0, CA PI delay=33
1423 11:17:36.502738
1424 11:17:36.505402 [CBTSetCACLKResult] CA Dly = 33
1425 11:17:36.505863 CS Dly: 6 (0~38)
1426 11:17:36.506250
1427 11:17:36.509130 ----->DramcWriteLeveling(PI) begin...
1428 11:17:36.509603 ==
1429 11:17:36.512825 Dram Type= 6, Freq= 0, CH_1, rank 0
1430 11:17:36.516414 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1431 11:17:36.516919 ==
1432 11:17:36.520587 Write leveling (Byte 0): 27 => 27
1433 11:17:36.523850 Write leveling (Byte 1): 30 => 30
1434 11:17:36.527222 DramcWriteLeveling(PI) end<-----
1435 11:17:36.527697
1436 11:17:36.528111 ==
1437 11:17:36.530771 Dram Type= 6, Freq= 0, CH_1, rank 0
1438 11:17:36.534555 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1439 11:17:36.535019 ==
1440 11:17:36.537984 [Gating] SW mode calibration
1441 11:17:36.544460 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1442 11:17:36.551085 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1443 11:17:36.554638 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1444 11:17:36.558040 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1445 11:17:36.561261 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1446 11:17:36.568140 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 11:17:36.571496 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 11:17:36.574403 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 11:17:36.581676 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 11:17:36.584948 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 11:17:36.588112 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 11:17:36.594656 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 11:17:36.598137 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 11:17:36.601191 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 11:17:36.608236 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 11:17:36.611700 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 11:17:36.614780 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 11:17:36.621164 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 11:17:36.624800 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1460 11:17:36.627836 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1461 11:17:36.634631 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 11:17:36.638259 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 11:17:36.641108 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 11:17:36.647957 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 11:17:36.651368 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1466 11:17:36.654387 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 11:17:36.657696 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 11:17:36.664967 0 9 4 | B1->B0 | 2323 2626 | 0 1 | (0 0) (0 0)
1469 11:17:36.668154 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1470 11:17:36.671546 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1471 11:17:36.678174 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1472 11:17:36.681655 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1473 11:17:36.685011 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1474 11:17:36.691661 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1475 11:17:36.695096 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 11:17:36.698216 0 10 4 | B1->B0 | 3030 2f2f | 1 0 | (1 1) (0 0)
1477 11:17:36.705222 0 10 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1478 11:17:36.707994 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 11:17:36.711269 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 11:17:36.717881 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 11:17:36.721064 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 11:17:36.724739 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 11:17:36.731358 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 11:17:36.734358 0 11 4 | B1->B0 | 2f2f 3e3e | 0 0 | (0 0) (0 0)
1485 11:17:36.737531 0 11 8 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
1486 11:17:36.743951 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1487 11:17:36.747434 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1488 11:17:36.750599 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1489 11:17:36.757282 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1490 11:17:36.761042 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 11:17:36.763869 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1492 11:17:36.770897 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1493 11:17:36.773993 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1494 11:17:36.777333 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1495 11:17:36.784319 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1496 11:17:36.787604 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 11:17:36.790582 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 11:17:36.797243 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 11:17:36.800684 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 11:17:36.804061 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 11:17:36.810346 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 11:17:36.813587 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 11:17:36.817061 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 11:17:36.823852 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 11:17:36.827219 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 11:17:36.830606 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 11:17:36.834098 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 11:17:36.840417 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
1509 11:17:36.843647 Total UI for P1: 0, mck2ui 16
1510 11:17:36.847058 best dqsien dly found for B0: ( 0, 14, 2)
1511 11:17:36.850313 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1512 11:17:36.853751 Total UI for P1: 0, mck2ui 16
1513 11:17:36.857423 best dqsien dly found for B1: ( 0, 14, 6)
1514 11:17:36.860409 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1515 11:17:36.863892 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1516 11:17:36.864448
1517 11:17:36.867259 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1518 11:17:36.870624 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1519 11:17:36.873517 [Gating] SW calibration Done
1520 11:17:36.873980 ==
1521 11:17:36.877154 Dram Type= 6, Freq= 0, CH_1, rank 0
1522 11:17:36.883671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1523 11:17:36.884232 ==
1524 11:17:36.884601 RX Vref Scan: 0
1525 11:17:36.884997
1526 11:17:36.887005 RX Vref 0 -> 0, step: 1
1527 11:17:36.887466
1528 11:17:36.890056 RX Delay -130 -> 252, step: 16
1529 11:17:36.893655 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1530 11:17:36.897163 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1531 11:17:36.900350 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1532 11:17:36.903750 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1533 11:17:36.910053 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1534 11:17:36.913361 iDelay=222, Bit 5, Center 93 (-18 ~ 205) 224
1535 11:17:36.916918 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1536 11:17:36.919980 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1537 11:17:36.924162 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1538 11:17:36.930038 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1539 11:17:36.933350 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1540 11:17:36.936709 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1541 11:17:36.940059 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1542 11:17:36.946387 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1543 11:17:36.949807 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1544 11:17:36.953205 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1545 11:17:36.953793 ==
1546 11:17:36.956633 Dram Type= 6, Freq= 0, CH_1, rank 0
1547 11:17:36.959557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1548 11:17:36.960037 ==
1549 11:17:36.963567 DQS Delay:
1550 11:17:36.964292 DQS0 = 0, DQS1 = 0
1551 11:17:36.966238 DQM Delay:
1552 11:17:36.966640 DQM0 = 90, DQM1 = 82
1553 11:17:36.966984 DQ Delay:
1554 11:17:36.969442 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =93
1555 11:17:36.972895 DQ4 =93, DQ5 =93, DQ6 =101, DQ7 =85
1556 11:17:36.976149 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
1557 11:17:36.979652 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1558 11:17:36.980218
1559 11:17:36.980592
1560 11:17:36.983142 ==
1561 11:17:36.986262 Dram Type= 6, Freq= 0, CH_1, rank 0
1562 11:17:36.989429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1563 11:17:36.990012 ==
1564 11:17:36.990390
1565 11:17:36.990729
1566 11:17:36.993139 TX Vref Scan disable
1567 11:17:36.993702 == TX Byte 0 ==
1568 11:17:37.000220 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1569 11:17:37.002892 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1570 11:17:37.003355 == TX Byte 1 ==
1571 11:17:37.009635 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1572 11:17:37.012735 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1573 11:17:37.013333 ==
1574 11:17:37.016400 Dram Type= 6, Freq= 0, CH_1, rank 0
1575 11:17:37.019130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1576 11:17:37.019598 ==
1577 11:17:37.032701 TX Vref=22, minBit 15, minWin=26, winSum=446
1578 11:17:37.036408 TX Vref=24, minBit 8, minWin=27, winSum=450
1579 11:17:37.039405 TX Vref=26, minBit 15, minWin=27, winSum=454
1580 11:17:37.042725 TX Vref=28, minBit 15, minWin=27, winSum=456
1581 11:17:37.045748 TX Vref=30, minBit 15, minWin=27, winSum=457
1582 11:17:37.052429 TX Vref=32, minBit 9, minWin=27, winSum=456
1583 11:17:37.056027 [TxChooseVref] Worse bit 15, Min win 27, Win sum 457, Final Vref 30
1584 11:17:37.056607
1585 11:17:37.059070 Final TX Range 1 Vref 30
1586 11:17:37.059531
1587 11:17:37.059896 ==
1588 11:17:37.062278 Dram Type= 6, Freq= 0, CH_1, rank 0
1589 11:17:37.068948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1590 11:17:37.069409 ==
1591 11:17:37.069778
1592 11:17:37.070170
1593 11:17:37.070696 TX Vref Scan disable
1594 11:17:37.073184 == TX Byte 0 ==
1595 11:17:37.076305 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1596 11:17:37.080049 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1597 11:17:37.083664 == TX Byte 1 ==
1598 11:17:37.086885 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1599 11:17:37.090269 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1600 11:17:37.090780
1601 11:17:37.093581 [DATLAT]
1602 11:17:37.094006 Freq=800, CH1 RK0
1603 11:17:37.094386
1604 11:17:37.097078 DATLAT Default: 0xa
1605 11:17:37.097590 0, 0xFFFF, sum = 0
1606 11:17:37.100614 1, 0xFFFF, sum = 0
1607 11:17:37.101073 2, 0xFFFF, sum = 0
1608 11:17:37.103630 3, 0xFFFF, sum = 0
1609 11:17:37.104055 4, 0xFFFF, sum = 0
1610 11:17:37.106954 5, 0xFFFF, sum = 0
1611 11:17:37.107470 6, 0xFFFF, sum = 0
1612 11:17:37.110113 7, 0xFFFF, sum = 0
1613 11:17:37.110534 8, 0xFFFF, sum = 0
1614 11:17:37.113916 9, 0x0, sum = 1
1615 11:17:37.114431 10, 0x0, sum = 2
1616 11:17:37.117610 11, 0x0, sum = 3
1617 11:17:37.118448 12, 0x0, sum = 4
1618 11:17:37.120050 best_step = 10
1619 11:17:37.120557
1620 11:17:37.121007 ==
1621 11:17:37.123289 Dram Type= 6, Freq= 0, CH_1, rank 0
1622 11:17:37.126517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1623 11:17:37.127156 ==
1624 11:17:37.129995 RX Vref Scan: 1
1625 11:17:37.130641
1626 11:17:37.131249 Set Vref Range= 32 -> 127
1627 11:17:37.131841
1628 11:17:37.133405 RX Vref 32 -> 127, step: 1
1629 11:17:37.134029
1630 11:17:37.136526 RX Delay -79 -> 252, step: 8
1631 11:17:37.137005
1632 11:17:37.139832 Set Vref, RX VrefLevel [Byte0]: 32
1633 11:17:37.143818 [Byte1]: 32
1634 11:17:37.144381
1635 11:17:37.146587 Set Vref, RX VrefLevel [Byte0]: 33
1636 11:17:37.149558 [Byte1]: 33
1637 11:17:37.153241
1638 11:17:37.153701 Set Vref, RX VrefLevel [Byte0]: 34
1639 11:17:37.156289 [Byte1]: 34
1640 11:17:37.160440
1641 11:17:37.160870 Set Vref, RX VrefLevel [Byte0]: 35
1642 11:17:37.163707 [Byte1]: 35
1643 11:17:37.168375
1644 11:17:37.168741 Set Vref, RX VrefLevel [Byte0]: 36
1645 11:17:37.171880 [Byte1]: 36
1646 11:17:37.175539
1647 11:17:37.175908 Set Vref, RX VrefLevel [Byte0]: 37
1648 11:17:37.178929 [Byte1]: 37
1649 11:17:37.183018
1650 11:17:37.183501 Set Vref, RX VrefLevel [Byte0]: 38
1651 11:17:37.186765 [Byte1]: 38
1652 11:17:37.190857
1653 11:17:37.191244 Set Vref, RX VrefLevel [Byte0]: 39
1654 11:17:37.194249 [Byte1]: 39
1655 11:17:37.198567
1656 11:17:37.201664 Set Vref, RX VrefLevel [Byte0]: 40
1657 11:17:37.204877 [Byte1]: 40
1658 11:17:37.205174
1659 11:17:37.208152 Set Vref, RX VrefLevel [Byte0]: 41
1660 11:17:37.211847 [Byte1]: 41
1661 11:17:37.212241
1662 11:17:37.215037 Set Vref, RX VrefLevel [Byte0]: 42
1663 11:17:37.218093 [Byte1]: 42
1664 11:17:37.218407
1665 11:17:37.221522 Set Vref, RX VrefLevel [Byte0]: 43
1666 11:17:37.225092 [Byte1]: 43
1667 11:17:37.228709
1668 11:17:37.229164 Set Vref, RX VrefLevel [Byte0]: 44
1669 11:17:37.232737 [Byte1]: 44
1670 11:17:37.236517
1671 11:17:37.237081 Set Vref, RX VrefLevel [Byte0]: 45
1672 11:17:37.240087 [Byte1]: 45
1673 11:17:37.243767
1674 11:17:37.244182 Set Vref, RX VrefLevel [Byte0]: 46
1675 11:17:37.247342 [Byte1]: 46
1676 11:17:37.251287
1677 11:17:37.251768 Set Vref, RX VrefLevel [Byte0]: 47
1678 11:17:37.254915 [Byte1]: 47
1679 11:17:37.259088
1680 11:17:37.259684 Set Vref, RX VrefLevel [Byte0]: 48
1681 11:17:37.262301 [Byte1]: 48
1682 11:17:37.267176
1683 11:17:37.267748 Set Vref, RX VrefLevel [Byte0]: 49
1684 11:17:37.270160 [Byte1]: 49
1685 11:17:37.274206
1686 11:17:37.274779 Set Vref, RX VrefLevel [Byte0]: 50
1687 11:17:37.277287 [Byte1]: 50
1688 11:17:37.281604
1689 11:17:37.282172 Set Vref, RX VrefLevel [Byte0]: 51
1690 11:17:37.285089 [Byte1]: 51
1691 11:17:37.289315
1692 11:17:37.289885 Set Vref, RX VrefLevel [Byte0]: 52
1693 11:17:37.292630 [Byte1]: 52
1694 11:17:37.296986
1695 11:17:37.297563 Set Vref, RX VrefLevel [Byte0]: 53
1696 11:17:37.300411 [Byte1]: 53
1697 11:17:37.304416
1698 11:17:37.304923 Set Vref, RX VrefLevel [Byte0]: 54
1699 11:17:37.307767 [Byte1]: 54
1700 11:17:37.312121
1701 11:17:37.312692 Set Vref, RX VrefLevel [Byte0]: 55
1702 11:17:37.315268 [Byte1]: 55
1703 11:17:37.319233
1704 11:17:37.319708 Set Vref, RX VrefLevel [Byte0]: 56
1705 11:17:37.322796 [Byte1]: 56
1706 11:17:37.327338
1707 11:17:37.327908 Set Vref, RX VrefLevel [Byte0]: 57
1708 11:17:37.330236 [Byte1]: 57
1709 11:17:37.334516
1710 11:17:37.335089 Set Vref, RX VrefLevel [Byte0]: 58
1711 11:17:37.338001 [Byte1]: 58
1712 11:17:37.341969
1713 11:17:37.342538 Set Vref, RX VrefLevel [Byte0]: 59
1714 11:17:37.345280 [Byte1]: 59
1715 11:17:37.349550
1716 11:17:37.350127 Set Vref, RX VrefLevel [Byte0]: 60
1717 11:17:37.352914 [Byte1]: 60
1718 11:17:37.357194
1719 11:17:37.357774 Set Vref, RX VrefLevel [Byte0]: 61
1720 11:17:37.360657 [Byte1]: 61
1721 11:17:37.364758
1722 11:17:37.365373 Set Vref, RX VrefLevel [Byte0]: 62
1723 11:17:37.367986 [Byte1]: 62
1724 11:17:37.372198
1725 11:17:37.372807 Set Vref, RX VrefLevel [Byte0]: 63
1726 11:17:37.375787 [Byte1]: 63
1727 11:17:37.380029
1728 11:17:37.380601 Set Vref, RX VrefLevel [Byte0]: 64
1729 11:17:37.383400 [Byte1]: 64
1730 11:17:37.387588
1731 11:17:37.388161 Set Vref, RX VrefLevel [Byte0]: 65
1732 11:17:37.390664 [Byte1]: 65
1733 11:17:37.394766
1734 11:17:37.395336 Set Vref, RX VrefLevel [Byte0]: 66
1735 11:17:37.398341 [Byte1]: 66
1736 11:17:37.402247
1737 11:17:37.402816 Set Vref, RX VrefLevel [Byte0]: 67
1738 11:17:37.405512 [Byte1]: 67
1739 11:17:37.409791
1740 11:17:37.410260 Set Vref, RX VrefLevel [Byte0]: 68
1741 11:17:37.413191 [Byte1]: 68
1742 11:17:37.417407
1743 11:17:37.417934 Set Vref, RX VrefLevel [Byte0]: 69
1744 11:17:37.420809 [Byte1]: 69
1745 11:17:37.424760
1746 11:17:37.425257 Set Vref, RX VrefLevel [Byte0]: 70
1747 11:17:37.429132 [Byte1]: 70
1748 11:17:37.433043
1749 11:17:37.433622 Set Vref, RX VrefLevel [Byte0]: 71
1750 11:17:37.436479 [Byte1]: 71
1751 11:17:37.440570
1752 11:17:37.441184 Set Vref, RX VrefLevel [Byte0]: 72
1753 11:17:37.443259 [Byte1]: 72
1754 11:17:37.447619
1755 11:17:37.448197 Set Vref, RX VrefLevel [Byte0]: 73
1756 11:17:37.451040 [Byte1]: 73
1757 11:17:37.455427
1758 11:17:37.456010 Set Vref, RX VrefLevel [Byte0]: 74
1759 11:17:37.458685 [Byte1]: 74
1760 11:17:37.462720
1761 11:17:37.466145 Set Vref, RX VrefLevel [Byte0]: 75
1762 11:17:37.469505 [Byte1]: 75
1763 11:17:37.470093
1764 11:17:37.472996 Set Vref, RX VrefLevel [Byte0]: 76
1765 11:17:37.475752 [Byte1]: 76
1766 11:17:37.476326
1767 11:17:37.479497 Final RX Vref Byte 0 = 52 to rank0
1768 11:17:37.482728 Final RX Vref Byte 1 = 63 to rank0
1769 11:17:37.485858 Final RX Vref Byte 0 = 52 to rank1
1770 11:17:37.488929 Final RX Vref Byte 1 = 63 to rank1==
1771 11:17:37.492443 Dram Type= 6, Freq= 0, CH_1, rank 0
1772 11:17:37.495901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1773 11:17:37.496483 ==
1774 11:17:37.498631 DQS Delay:
1775 11:17:37.499101 DQS0 = 0, DQS1 = 0
1776 11:17:37.499475 DQM Delay:
1777 11:17:37.502090 DQM0 = 93, DQM1 = 83
1778 11:17:37.502642 DQ Delay:
1779 11:17:37.505584 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =88
1780 11:17:37.509160 DQ4 =92, DQ5 =108, DQ6 =100, DQ7 =88
1781 11:17:37.512358 DQ8 =72, DQ9 =72, DQ10 =84, DQ11 =80
1782 11:17:37.515734 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =88
1783 11:17:37.516221
1784 11:17:37.516592
1785 11:17:37.525311 [DQSOSCAuto] RK0, (LSB)MR18= 0x304d, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1786 11:17:37.528911 CH1 RK0: MR19=606, MR18=304D
1787 11:17:37.532220 CH1_RK0: MR19=0x606, MR18=0x304D, DQSOSC=390, MR23=63, INC=97, DEC=64
1788 11:17:37.535316
1789 11:17:37.538861 ----->DramcWriteLeveling(PI) begin...
1790 11:17:37.539438 ==
1791 11:17:37.541952 Dram Type= 6, Freq= 0, CH_1, rank 1
1792 11:17:37.545149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1793 11:17:37.545626 ==
1794 11:17:37.548929 Write leveling (Byte 0): 26 => 26
1795 11:17:37.552156 Write leveling (Byte 1): 28 => 28
1796 11:17:37.555462 DramcWriteLeveling(PI) end<-----
1797 11:17:37.556039
1798 11:17:37.556420 ==
1799 11:17:37.558363 Dram Type= 6, Freq= 0, CH_1, rank 1
1800 11:17:37.561464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1801 11:17:37.561938 ==
1802 11:17:37.564860 [Gating] SW mode calibration
1803 11:17:37.571740 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1804 11:17:37.578345 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1805 11:17:37.581937 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1806 11:17:37.584599 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1807 11:17:37.591596 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 11:17:37.594732 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 11:17:37.597968 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 11:17:37.604914 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 11:17:37.607909 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 11:17:37.611707 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 11:17:37.618001 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 11:17:37.621585 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 11:17:37.624751 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 11:17:37.631250 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 11:17:37.634304 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 11:17:37.637754 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 11:17:37.644648 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 11:17:37.648455 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 11:17:37.651498 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 11:17:37.654542 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1823 11:17:37.660965 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1824 11:17:37.664377 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 11:17:37.671234 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 11:17:37.674172 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 11:17:37.677485 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 11:17:37.681063 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 11:17:37.687648 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1830 11:17:37.690807 0 9 4 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1831 11:17:37.693962 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1832 11:17:37.700599 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1833 11:17:37.703916 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1834 11:17:37.707418 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1835 11:17:37.713910 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1836 11:17:37.717151 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1837 11:17:37.720720 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1838 11:17:37.727208 0 10 4 | B1->B0 | 2e2e 2f2f | 0 0 | (1 0) (0 1)
1839 11:17:37.730351 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 11:17:37.734083 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 11:17:37.740359 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 11:17:37.743744 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 11:17:37.747151 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 11:17:37.753562 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 11:17:37.757056 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 11:17:37.760404 0 11 4 | B1->B0 | 3434 3535 | 0 0 | (0 0) (0 0)
1847 11:17:37.767233 0 11 8 | B1->B0 | 4545 4343 | 0 0 | (0 0) (0 0)
1848 11:17:37.770765 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1849 11:17:37.774573 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1850 11:17:37.780966 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1851 11:17:37.784205 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1852 11:17:37.787008 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1853 11:17:37.793645 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1854 11:17:37.796967 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1855 11:17:37.800071 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1856 11:17:37.806972 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 11:17:37.810423 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 11:17:37.813666 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 11:17:37.820328 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 11:17:37.823426 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 11:17:37.826743 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 11:17:37.833366 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 11:17:37.836694 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 11:17:37.840465 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 11:17:37.846921 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 11:17:37.849846 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 11:17:37.853648 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 11:17:37.856804 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1869 11:17:37.863287 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1870 11:17:37.866591 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1871 11:17:37.870005 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1872 11:17:37.873418 Total UI for P1: 0, mck2ui 16
1873 11:17:37.876462 best dqsien dly found for B1: ( 0, 14, 4)
1874 11:17:37.883182 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1875 11:17:37.886277 Total UI for P1: 0, mck2ui 16
1876 11:17:37.890185 best dqsien dly found for B0: ( 0, 14, 8)
1877 11:17:37.893353 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1878 11:17:37.896550 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1879 11:17:37.897163
1880 11:17:37.899565 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1881 11:17:37.902951 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1882 11:17:37.906836 [Gating] SW calibration Done
1883 11:17:37.907394 ==
1884 11:17:37.909861 Dram Type= 6, Freq= 0, CH_1, rank 1
1885 11:17:37.913050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1886 11:17:37.913616 ==
1887 11:17:37.916523 RX Vref Scan: 0
1888 11:17:37.917123
1889 11:17:37.917506 RX Vref 0 -> 0, step: 1
1890 11:17:37.917857
1891 11:17:37.919537 RX Delay -130 -> 252, step: 16
1892 11:17:37.926545 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1893 11:17:37.929769 iDelay=206, Bit 1, Center 85 (-18 ~ 189) 208
1894 11:17:37.932998 iDelay=206, Bit 2, Center 85 (-18 ~ 189) 208
1895 11:17:37.936714 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1896 11:17:37.940281 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1897 11:17:37.942993 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1898 11:17:37.949702 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1899 11:17:37.952868 iDelay=206, Bit 7, Center 85 (-18 ~ 189) 208
1900 11:17:37.956417 iDelay=206, Bit 8, Center 61 (-50 ~ 173) 224
1901 11:17:37.959579 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1902 11:17:37.962877 iDelay=206, Bit 10, Center 93 (-18 ~ 205) 224
1903 11:17:37.969404 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1904 11:17:37.973434 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1905 11:17:37.976078 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1906 11:17:37.979567 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1907 11:17:37.985942 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1908 11:17:37.986494 ==
1909 11:17:37.989361 Dram Type= 6, Freq= 0, CH_1, rank 1
1910 11:17:37.992484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1911 11:17:37.992969 ==
1912 11:17:37.993339 DQS Delay:
1913 11:17:37.996054 DQS0 = 0, DQS1 = 0
1914 11:17:37.996663 DQM Delay:
1915 11:17:37.999354 DQM0 = 90, DQM1 = 83
1916 11:17:37.999914 DQ Delay:
1917 11:17:38.002678 DQ0 =93, DQ1 =85, DQ2 =85, DQ3 =93
1918 11:17:38.006066 DQ4 =93, DQ5 =93, DQ6 =93, DQ7 =85
1919 11:17:38.009110 DQ8 =61, DQ9 =69, DQ10 =93, DQ11 =69
1920 11:17:38.012481 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1921 11:17:38.013091
1922 11:17:38.013463
1923 11:17:38.013801 ==
1924 11:17:38.015891 Dram Type= 6, Freq= 0, CH_1, rank 1
1925 11:17:38.019106 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1926 11:17:38.019570 ==
1927 11:17:38.022679
1928 11:17:38.023238
1929 11:17:38.023605 TX Vref Scan disable
1930 11:17:38.025855 == TX Byte 0 ==
1931 11:17:38.029111 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1932 11:17:38.032203 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1933 11:17:38.035473 == TX Byte 1 ==
1934 11:17:38.039108 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1935 11:17:38.042308 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1936 11:17:38.042880 ==
1937 11:17:38.045798 Dram Type= 6, Freq= 0, CH_1, rank 1
1938 11:17:38.052248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1939 11:17:38.052855 ==
1940 11:17:38.064117 TX Vref=22, minBit 11, minWin=27, winSum=451
1941 11:17:38.067616 TX Vref=24, minBit 13, minWin=27, winSum=453
1942 11:17:38.071258 TX Vref=26, minBit 3, minWin=28, winSum=457
1943 11:17:38.074059 TX Vref=28, minBit 8, minWin=28, winSum=460
1944 11:17:38.077628 TX Vref=30, minBit 8, minWin=28, winSum=460
1945 11:17:38.084503 TX Vref=32, minBit 9, minWin=27, winSum=457
1946 11:17:38.087545 [TxChooseVref] Worse bit 8, Min win 28, Win sum 460, Final Vref 28
1947 11:17:38.088112
1948 11:17:38.090792 Final TX Range 1 Vref 28
1949 11:17:38.091354
1950 11:17:38.091727 ==
1951 11:17:38.093809 Dram Type= 6, Freq= 0, CH_1, rank 1
1952 11:17:38.097364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1953 11:17:38.100444 ==
1954 11:17:38.101063
1955 11:17:38.101494
1956 11:17:38.101836 TX Vref Scan disable
1957 11:17:38.104445 == TX Byte 0 ==
1958 11:17:38.107613 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1959 11:17:38.114366 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1960 11:17:38.114936 == TX Byte 1 ==
1961 11:17:38.117806 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1962 11:17:38.124349 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1963 11:17:38.124952
1964 11:17:38.125329 [DATLAT]
1965 11:17:38.125670 Freq=800, CH1 RK1
1966 11:17:38.126008
1967 11:17:38.127313 DATLAT Default: 0xa
1968 11:17:38.127775 0, 0xFFFF, sum = 0
1969 11:17:38.130403 1, 0xFFFF, sum = 0
1970 11:17:38.130828 2, 0xFFFF, sum = 0
1971 11:17:38.134471 3, 0xFFFF, sum = 0
1972 11:17:38.137347 4, 0xFFFF, sum = 0
1973 11:17:38.137865 5, 0xFFFF, sum = 0
1974 11:17:38.140846 6, 0xFFFF, sum = 0
1975 11:17:38.141410 7, 0xFFFF, sum = 0
1976 11:17:38.144074 8, 0xFFFF, sum = 0
1977 11:17:38.144638 9, 0x0, sum = 1
1978 11:17:38.145096 10, 0x0, sum = 2
1979 11:17:38.147322 11, 0x0, sum = 3
1980 11:17:38.147792 12, 0x0, sum = 4
1981 11:17:38.150531 best_step = 10
1982 11:17:38.150993
1983 11:17:38.151362 ==
1984 11:17:38.154106 Dram Type= 6, Freq= 0, CH_1, rank 1
1985 11:17:38.157366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1986 11:17:38.157932 ==
1987 11:17:38.160446 RX Vref Scan: 0
1988 11:17:38.160991
1989 11:17:38.161370 RX Vref 0 -> 0, step: 1
1990 11:17:38.163716
1991 11:17:38.164173 RX Delay -95 -> 252, step: 8
1992 11:17:38.171431 iDelay=209, Bit 0, Center 96 (-7 ~ 200) 208
1993 11:17:38.174071 iDelay=209, Bit 1, Center 84 (-15 ~ 184) 200
1994 11:17:38.177501 iDelay=209, Bit 2, Center 80 (-23 ~ 184) 208
1995 11:17:38.180836 iDelay=209, Bit 3, Center 88 (-15 ~ 192) 208
1996 11:17:38.183817 iDelay=209, Bit 4, Center 96 (-7 ~ 200) 208
1997 11:17:38.190517 iDelay=209, Bit 5, Center 100 (-7 ~ 208) 216
1998 11:17:38.194329 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
1999 11:17:38.197623 iDelay=209, Bit 7, Center 88 (-15 ~ 192) 208
2000 11:17:38.200531 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2001 11:17:38.204195 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2002 11:17:38.210801 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2003 11:17:38.214060 iDelay=209, Bit 11, Center 80 (-31 ~ 192) 224
2004 11:17:38.217237 iDelay=209, Bit 12, Center 92 (-15 ~ 200) 216
2005 11:17:38.220615 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2006 11:17:38.224363 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2007 11:17:38.230796 iDelay=209, Bit 15, Center 96 (-15 ~ 208) 224
2008 11:17:38.231360 ==
2009 11:17:38.233981 Dram Type= 6, Freq= 0, CH_1, rank 1
2010 11:17:38.237648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2011 11:17:38.238215 ==
2012 11:17:38.238584 DQS Delay:
2013 11:17:38.240758 DQS0 = 0, DQS1 = 0
2014 11:17:38.241354 DQM Delay:
2015 11:17:38.244479 DQM0 = 91, DQM1 = 84
2016 11:17:38.245075 DQ Delay:
2017 11:17:38.246969 DQ0 =96, DQ1 =84, DQ2 =80, DQ3 =88
2018 11:17:38.250234 DQ4 =96, DQ5 =100, DQ6 =96, DQ7 =88
2019 11:17:38.254003 DQ8 =68, DQ9 =72, DQ10 =88, DQ11 =80
2020 11:17:38.257413 DQ12 =92, DQ13 =88, DQ14 =88, DQ15 =96
2021 11:17:38.257967
2022 11:17:38.258332
2023 11:17:38.267137 [DQSOSCAuto] RK1, (LSB)MR18= 0x3c11, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 394 ps
2024 11:17:38.267753 CH1 RK1: MR19=606, MR18=3C11
2025 11:17:38.273650 CH1_RK1: MR19=0x606, MR18=0x3C11, DQSOSC=394, MR23=63, INC=95, DEC=63
2026 11:17:38.277293 [RxdqsGatingPostProcess] freq 800
2027 11:17:38.283879 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2028 11:17:38.287200 Pre-setting of DQS Precalculation
2029 11:17:38.290354 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2030 11:17:38.296987 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2031 11:17:38.306634 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2032 11:17:38.307099
2033 11:17:38.307466
2034 11:17:38.307810 [Calibration Summary] 1600 Mbps
2035 11:17:38.309920 CH 0, Rank 0
2036 11:17:38.313611 SW Impedance : PASS
2037 11:17:38.314175 DUTY Scan : NO K
2038 11:17:38.316858 ZQ Calibration : PASS
2039 11:17:38.317409 Jitter Meter : NO K
2040 11:17:38.320113 CBT Training : PASS
2041 11:17:38.323687 Write leveling : PASS
2042 11:17:38.324249 RX DQS gating : PASS
2043 11:17:38.327233 RX DQ/DQS(RDDQC) : PASS
2044 11:17:38.330085 TX DQ/DQS : PASS
2045 11:17:38.330548 RX DATLAT : PASS
2046 11:17:38.333638 RX DQ/DQS(Engine): PASS
2047 11:17:38.336607 TX OE : NO K
2048 11:17:38.337090 All Pass.
2049 11:17:38.337459
2050 11:17:38.337802 CH 0, Rank 1
2051 11:17:38.340216 SW Impedance : PASS
2052 11:17:38.343567 DUTY Scan : NO K
2053 11:17:38.344124 ZQ Calibration : PASS
2054 11:17:38.346975 Jitter Meter : NO K
2055 11:17:38.349981 CBT Training : PASS
2056 11:17:38.350447 Write leveling : PASS
2057 11:17:38.353713 RX DQS gating : PASS
2058 11:17:38.357134 RX DQ/DQS(RDDQC) : PASS
2059 11:17:38.357712 TX DQ/DQS : PASS
2060 11:17:38.360455 RX DATLAT : PASS
2061 11:17:38.361055 RX DQ/DQS(Engine): PASS
2062 11:17:38.363493 TX OE : NO K
2063 11:17:38.364053 All Pass.
2064 11:17:38.364426
2065 11:17:38.366739 CH 1, Rank 0
2066 11:17:38.367199 SW Impedance : PASS
2067 11:17:38.370239 DUTY Scan : NO K
2068 11:17:38.373364 ZQ Calibration : PASS
2069 11:17:38.373937 Jitter Meter : NO K
2070 11:17:38.376442 CBT Training : PASS
2071 11:17:38.380257 Write leveling : PASS
2072 11:17:38.380866 RX DQS gating : PASS
2073 11:17:38.383027 RX DQ/DQS(RDDQC) : PASS
2074 11:17:38.386657 TX DQ/DQS : PASS
2075 11:17:38.387291 RX DATLAT : PASS
2076 11:17:38.390015 RX DQ/DQS(Engine): PASS
2077 11:17:38.393238 TX OE : NO K
2078 11:17:38.393799 All Pass.
2079 11:17:38.394168
2080 11:17:38.394508 CH 1, Rank 1
2081 11:17:38.396256 SW Impedance : PASS
2082 11:17:38.399561 DUTY Scan : NO K
2083 11:17:38.400125 ZQ Calibration : PASS
2084 11:17:38.403458 Jitter Meter : NO K
2085 11:17:38.406466 CBT Training : PASS
2086 11:17:38.407021 Write leveling : PASS
2087 11:17:38.409657 RX DQS gating : PASS
2088 11:17:38.413547 RX DQ/DQS(RDDQC) : PASS
2089 11:17:38.414107 TX DQ/DQS : PASS
2090 11:17:38.416326 RX DATLAT : PASS
2091 11:17:38.416833 RX DQ/DQS(Engine): PASS
2092 11:17:38.419813 TX OE : NO K
2093 11:17:38.420397 All Pass.
2094 11:17:38.420803
2095 11:17:38.423551 DramC Write-DBI off
2096 11:17:38.426731 PER_BANK_REFRESH: Hybrid Mode
2097 11:17:38.427293 TX_TRACKING: ON
2098 11:17:38.429506 [GetDramInforAfterCalByMRR] Vendor 6.
2099 11:17:38.433485 [GetDramInforAfterCalByMRR] Revision 606.
2100 11:17:38.436392 [GetDramInforAfterCalByMRR] Revision 2 0.
2101 11:17:38.439882 MR0 0x3b3b
2102 11:17:38.440460 MR8 0x5151
2103 11:17:38.443358 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2104 11:17:38.443922
2105 11:17:38.446615 MR0 0x3b3b
2106 11:17:38.447175 MR8 0x5151
2107 11:17:38.449342 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2108 11:17:38.449857
2109 11:17:38.459380 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2110 11:17:38.463112 [FAST_K] Save calibration result to emmc
2111 11:17:38.466174 [FAST_K] Save calibration result to emmc
2112 11:17:38.469568 dram_init: config_dvfs: 1
2113 11:17:38.472952 dramc_set_vcore_voltage set vcore to 662500
2114 11:17:38.473510 Read voltage for 1200, 2
2115 11:17:38.476445 Vio18 = 0
2116 11:17:38.477053 Vcore = 662500
2117 11:17:38.477427 Vdram = 0
2118 11:17:38.479377 Vddq = 0
2119 11:17:38.479835 Vmddr = 0
2120 11:17:38.482922 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2121 11:17:38.489694 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2122 11:17:38.492891 MEM_TYPE=3, freq_sel=15
2123 11:17:38.495891 sv_algorithm_assistance_LP4_1600
2124 11:17:38.499617 ============ PULL DRAM RESETB DOWN ============
2125 11:17:38.502828 ========== PULL DRAM RESETB DOWN end =========
2126 11:17:38.509701 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2127 11:17:38.512656 ===================================
2128 11:17:38.513158 LPDDR4 DRAM CONFIGURATION
2129 11:17:38.515916 ===================================
2130 11:17:38.519542 EX_ROW_EN[0] = 0x0
2131 11:17:38.520099 EX_ROW_EN[1] = 0x0
2132 11:17:38.523111 LP4Y_EN = 0x0
2133 11:17:38.523679 WORK_FSP = 0x0
2134 11:17:38.526636 WL = 0x4
2135 11:17:38.527195 RL = 0x4
2136 11:17:38.529450 BL = 0x2
2137 11:17:38.532874 RPST = 0x0
2138 11:17:38.533437 RD_PRE = 0x0
2139 11:17:38.535759 WR_PRE = 0x1
2140 11:17:38.536333 WR_PST = 0x0
2141 11:17:38.539832 DBI_WR = 0x0
2142 11:17:38.540391 DBI_RD = 0x0
2143 11:17:38.542679 OTF = 0x1
2144 11:17:38.546140 ===================================
2145 11:17:38.549616 ===================================
2146 11:17:38.550189 ANA top config
2147 11:17:38.553062 ===================================
2148 11:17:38.556300 DLL_ASYNC_EN = 0
2149 11:17:38.559018 ALL_SLAVE_EN = 0
2150 11:17:38.559525 NEW_RANK_MODE = 1
2151 11:17:38.562398 DLL_IDLE_MODE = 1
2152 11:17:38.565818 LP45_APHY_COMB_EN = 1
2153 11:17:38.569536 TX_ODT_DIS = 1
2154 11:17:38.573147 NEW_8X_MODE = 1
2155 11:17:38.575859 ===================================
2156 11:17:38.576421 ===================================
2157 11:17:38.579131 data_rate = 2400
2158 11:17:38.582344 CKR = 1
2159 11:17:38.585980 DQ_P2S_RATIO = 8
2160 11:17:38.589101 ===================================
2161 11:17:38.592740 CA_P2S_RATIO = 8
2162 11:17:38.595497 DQ_CA_OPEN = 0
2163 11:17:38.598613 DQ_SEMI_OPEN = 0
2164 11:17:38.599172 CA_SEMI_OPEN = 0
2165 11:17:38.602164 CA_FULL_RATE = 0
2166 11:17:38.605829 DQ_CKDIV4_EN = 0
2167 11:17:38.609054 CA_CKDIV4_EN = 0
2168 11:17:38.612348 CA_PREDIV_EN = 0
2169 11:17:38.615464 PH8_DLY = 17
2170 11:17:38.616003 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2171 11:17:38.619106 DQ_AAMCK_DIV = 4
2172 11:17:38.622363 CA_AAMCK_DIV = 4
2173 11:17:38.625682 CA_ADMCK_DIV = 4
2174 11:17:38.628924 DQ_TRACK_CA_EN = 0
2175 11:17:38.632226 CA_PICK = 1200
2176 11:17:38.635906 CA_MCKIO = 1200
2177 11:17:38.636426 MCKIO_SEMI = 0
2178 11:17:38.638977 PLL_FREQ = 2366
2179 11:17:38.641994 DQ_UI_PI_RATIO = 32
2180 11:17:38.645584 CA_UI_PI_RATIO = 0
2181 11:17:38.648752 ===================================
2182 11:17:38.652145 ===================================
2183 11:17:38.655267 memory_type:LPDDR4
2184 11:17:38.655784 GP_NUM : 10
2185 11:17:38.658742 SRAM_EN : 1
2186 11:17:38.659160 MD32_EN : 0
2187 11:17:38.661722 ===================================
2188 11:17:38.664945 [ANA_INIT] >>>>>>>>>>>>>>
2189 11:17:38.668818 <<<<<< [CONFIGURE PHASE]: ANA_TX
2190 11:17:38.671742 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2191 11:17:38.675298 ===================================
2192 11:17:38.678482 data_rate = 2400,PCW = 0X5b00
2193 11:17:38.681971 ===================================
2194 11:17:38.685190 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2195 11:17:38.692018 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2196 11:17:38.695515 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2197 11:17:38.702153 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2198 11:17:38.704944 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2199 11:17:38.708585 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2200 11:17:38.709188 [ANA_INIT] flow start
2201 11:17:38.711604 [ANA_INIT] PLL >>>>>>>>
2202 11:17:38.715025 [ANA_INIT] PLL <<<<<<<<
2203 11:17:38.715487 [ANA_INIT] MIDPI >>>>>>>>
2204 11:17:38.718811 [ANA_INIT] MIDPI <<<<<<<<
2205 11:17:38.721652 [ANA_INIT] DLL >>>>>>>>
2206 11:17:38.724908 [ANA_INIT] DLL <<<<<<<<
2207 11:17:38.725370 [ANA_INIT] flow end
2208 11:17:38.728076 ============ LP4 DIFF to SE enter ============
2209 11:17:38.735173 ============ LP4 DIFF to SE exit ============
2210 11:17:38.735736 [ANA_INIT] <<<<<<<<<<<<<
2211 11:17:38.738113 [Flow] Enable top DCM control >>>>>
2212 11:17:38.741452 [Flow] Enable top DCM control <<<<<
2213 11:17:38.744715 Enable DLL master slave shuffle
2214 11:17:38.751733 ==============================================================
2215 11:17:38.752303 Gating Mode config
2216 11:17:38.758061 ==============================================================
2217 11:17:38.761237 Config description:
2218 11:17:38.771931 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2219 11:17:38.778025 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2220 11:17:38.781124 SELPH_MODE 0: By rank 1: By Phase
2221 11:17:38.787895 ==============================================================
2222 11:17:38.791207 GAT_TRACK_EN = 1
2223 11:17:38.791761 RX_GATING_MODE = 2
2224 11:17:38.794480 RX_GATING_TRACK_MODE = 2
2225 11:17:38.797359 SELPH_MODE = 1
2226 11:17:38.800992 PICG_EARLY_EN = 1
2227 11:17:38.804458 VALID_LAT_VALUE = 1
2228 11:17:38.810944 ==============================================================
2229 11:17:38.814308 Enter into Gating configuration >>>>
2230 11:17:38.817565 Exit from Gating configuration <<<<
2231 11:17:38.821106 Enter into DVFS_PRE_config >>>>>
2232 11:17:38.830699 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2233 11:17:38.834557 Exit from DVFS_PRE_config <<<<<
2234 11:17:38.837723 Enter into PICG configuration >>>>
2235 11:17:38.841548 Exit from PICG configuration <<<<
2236 11:17:38.844282 [RX_INPUT] configuration >>>>>
2237 11:17:38.847550 [RX_INPUT] configuration <<<<<
2238 11:17:38.850967 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2239 11:17:38.857290 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2240 11:17:38.864013 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2241 11:17:38.870805 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2242 11:17:38.874074 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2243 11:17:38.880336 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2244 11:17:38.884140 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2245 11:17:38.890689 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2246 11:17:38.894348 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2247 11:17:38.897336 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2248 11:17:38.901047 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2249 11:17:38.907636 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2250 11:17:38.910473 ===================================
2251 11:17:38.910942 LPDDR4 DRAM CONFIGURATION
2252 11:17:38.914097 ===================================
2253 11:17:38.917398 EX_ROW_EN[0] = 0x0
2254 11:17:38.920619 EX_ROW_EN[1] = 0x0
2255 11:17:38.921215 LP4Y_EN = 0x0
2256 11:17:38.924021 WORK_FSP = 0x0
2257 11:17:38.924583 WL = 0x4
2258 11:17:38.927120 RL = 0x4
2259 11:17:38.927680 BL = 0x2
2260 11:17:38.930489 RPST = 0x0
2261 11:17:38.930948 RD_PRE = 0x0
2262 11:17:38.933832 WR_PRE = 0x1
2263 11:17:38.934413 WR_PST = 0x0
2264 11:17:38.937158 DBI_WR = 0x0
2265 11:17:38.937720 DBI_RD = 0x0
2266 11:17:38.940458 OTF = 0x1
2267 11:17:38.943820 ===================================
2268 11:17:38.946867 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2269 11:17:38.950668 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2270 11:17:38.956917 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2271 11:17:38.960200 ===================================
2272 11:17:38.960700 LPDDR4 DRAM CONFIGURATION
2273 11:17:38.963837 ===================================
2274 11:17:38.967189 EX_ROW_EN[0] = 0x10
2275 11:17:38.970180 EX_ROW_EN[1] = 0x0
2276 11:17:38.970647 LP4Y_EN = 0x0
2277 11:17:38.973618 WORK_FSP = 0x0
2278 11:17:38.974178 WL = 0x4
2279 11:17:38.976916 RL = 0x4
2280 11:17:38.977469 BL = 0x2
2281 11:17:38.980497 RPST = 0x0
2282 11:17:38.981101 RD_PRE = 0x0
2283 11:17:38.983921 WR_PRE = 0x1
2284 11:17:38.984482 WR_PST = 0x0
2285 11:17:38.986564 DBI_WR = 0x0
2286 11:17:38.987031 DBI_RD = 0x0
2287 11:17:38.990472 OTF = 0x1
2288 11:17:38.993694 ===================================
2289 11:17:39.000255 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2290 11:17:39.000858 ==
2291 11:17:39.003375 Dram Type= 6, Freq= 0, CH_0, rank 0
2292 11:17:39.006814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2293 11:17:39.007274 ==
2294 11:17:39.010274 [Duty_Offset_Calibration]
2295 11:17:39.010732 B0:2 B1:0 CA:1
2296 11:17:39.011094
2297 11:17:39.013483 [DutyScan_Calibration_Flow] k_type=0
2298 11:17:39.023080
2299 11:17:39.023536 ==CLK 0==
2300 11:17:39.025759 Final CLK duty delay cell = -4
2301 11:17:39.029043 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2302 11:17:39.032933 [-4] MIN Duty = 4875%(X100), DQS PI = 0
2303 11:17:39.036082 [-4] AVG Duty = 4953%(X100)
2304 11:17:39.036587
2305 11:17:39.039420 CH0 CLK Duty spec in!! Max-Min= 156%
2306 11:17:39.042748 [DutyScan_Calibration_Flow] ====Done====
2307 11:17:39.043256
2308 11:17:39.045803 [DutyScan_Calibration_Flow] k_type=1
2309 11:17:39.061446
2310 11:17:39.061992 ==DQS 0 ==
2311 11:17:39.064980 Final DQS duty delay cell = 0
2312 11:17:39.068153 [0] MAX Duty = 5187%(X100), DQS PI = 30
2313 11:17:39.071171 [0] MIN Duty = 4938%(X100), DQS PI = 2
2314 11:17:39.071747 [0] AVG Duty = 5062%(X100)
2315 11:17:39.075048
2316 11:17:39.075602 ==DQS 1 ==
2317 11:17:39.078221 Final DQS duty delay cell = -4
2318 11:17:39.081513 [-4] MAX Duty = 5124%(X100), DQS PI = 32
2319 11:17:39.084825 [-4] MIN Duty = 4938%(X100), DQS PI = 8
2320 11:17:39.088523 [-4] AVG Duty = 5031%(X100)
2321 11:17:39.089130
2322 11:17:39.091504 CH0 DQS 0 Duty spec in!! Max-Min= 249%
2323 11:17:39.092062
2324 11:17:39.094645 CH0 DQS 1 Duty spec in!! Max-Min= 186%
2325 11:17:39.098150 [DutyScan_Calibration_Flow] ====Done====
2326 11:17:39.098709
2327 11:17:39.101424 [DutyScan_Calibration_Flow] k_type=3
2328 11:17:39.118341
2329 11:17:39.118910 ==DQM 0 ==
2330 11:17:39.121598 Final DQM duty delay cell = 0
2331 11:17:39.125434 [0] MAX Duty = 5062%(X100), DQS PI = 24
2332 11:17:39.128216 [0] MIN Duty = 4844%(X100), DQS PI = 0
2333 11:17:39.131681 [0] AVG Duty = 4953%(X100)
2334 11:17:39.132240
2335 11:17:39.132601 ==DQM 1 ==
2336 11:17:39.134886 Final DQM duty delay cell = 0
2337 11:17:39.138318 [0] MAX Duty = 5218%(X100), DQS PI = 50
2338 11:17:39.141278 [0] MIN Duty = 5000%(X100), DQS PI = 24
2339 11:17:39.144977 [0] AVG Duty = 5109%(X100)
2340 11:17:39.145539
2341 11:17:39.148208 CH0 DQM 0 Duty spec in!! Max-Min= 218%
2342 11:17:39.148790
2343 11:17:39.151966 CH0 DQM 1 Duty spec in!! Max-Min= 218%
2344 11:17:39.155034 [DutyScan_Calibration_Flow] ====Done====
2345 11:17:39.155614
2346 11:17:39.157970 [DutyScan_Calibration_Flow] k_type=2
2347 11:17:39.175751
2348 11:17:39.176341 ==DQ 0 ==
2349 11:17:39.178926 Final DQ duty delay cell = 0
2350 11:17:39.182364 [0] MAX Duty = 5156%(X100), DQS PI = 34
2351 11:17:39.185257 [0] MIN Duty = 5000%(X100), DQS PI = 14
2352 11:17:39.185725 [0] AVG Duty = 5078%(X100)
2353 11:17:39.188827
2354 11:17:39.189388 ==DQ 1 ==
2355 11:17:39.192260 Final DQ duty delay cell = 4
2356 11:17:39.195836 [4] MAX Duty = 5093%(X100), DQS PI = 4
2357 11:17:39.198857 [4] MIN Duty = 5031%(X100), DQS PI = 0
2358 11:17:39.199420 [4] AVG Duty = 5062%(X100)
2359 11:17:39.199797
2360 11:17:39.202029 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2361 11:17:39.202498
2362 11:17:39.205457 CH0 DQ 1 Duty spec in!! Max-Min= 62%
2363 11:17:39.212583 [DutyScan_Calibration_Flow] ====Done====
2364 11:17:39.213173 ==
2365 11:17:39.215263 Dram Type= 6, Freq= 0, CH_1, rank 0
2366 11:17:39.218578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2367 11:17:39.219150 ==
2368 11:17:39.221831 [Duty_Offset_Calibration]
2369 11:17:39.222292 B0:0 B1:-1 CA:2
2370 11:17:39.222660
2371 11:17:39.225110 [DutyScan_Calibration_Flow] k_type=0
2372 11:17:39.235490
2373 11:17:39.236061 ==CLK 0==
2374 11:17:39.238817 Final CLK duty delay cell = 0
2375 11:17:39.242168 [0] MAX Duty = 5156%(X100), DQS PI = 16
2376 11:17:39.245501 [0] MIN Duty = 4938%(X100), DQS PI = 44
2377 11:17:39.245976 [0] AVG Duty = 5047%(X100)
2378 11:17:39.248729
2379 11:17:39.251800 CH1 CLK Duty spec in!! Max-Min= 218%
2380 11:17:39.255078 [DutyScan_Calibration_Flow] ====Done====
2381 11:17:39.255555
2382 11:17:39.258855 [DutyScan_Calibration_Flow] k_type=1
2383 11:17:39.275028
2384 11:17:39.275603 ==DQS 0 ==
2385 11:17:39.277928 Final DQS duty delay cell = 0
2386 11:17:39.280988 [0] MAX Duty = 5093%(X100), DQS PI = 24
2387 11:17:39.284651 [0] MIN Duty = 4969%(X100), DQS PI = 0
2388 11:17:39.287760 [0] AVG Duty = 5031%(X100)
2389 11:17:39.288301
2390 11:17:39.288682 ==DQS 1 ==
2391 11:17:39.291305 Final DQS duty delay cell = 0
2392 11:17:39.294633 [0] MAX Duty = 5156%(X100), DQS PI = 0
2393 11:17:39.297521 [0] MIN Duty = 4813%(X100), DQS PI = 36
2394 11:17:39.301315 [0] AVG Duty = 4984%(X100)
2395 11:17:39.301783
2396 11:17:39.304436 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2397 11:17:39.305026
2398 11:17:39.307752 CH1 DQS 1 Duty spec in!! Max-Min= 343%
2399 11:17:39.311098 [DutyScan_Calibration_Flow] ====Done====
2400 11:17:39.311570
2401 11:17:39.314342 [DutyScan_Calibration_Flow] k_type=3
2402 11:17:39.331231
2403 11:17:39.331849 ==DQM 0 ==
2404 11:17:39.334606 Final DQM duty delay cell = 4
2405 11:17:39.338210 [4] MAX Duty = 5093%(X100), DQS PI = 20
2406 11:17:39.341594 [4] MIN Duty = 4938%(X100), DQS PI = 44
2407 11:17:39.342228 [4] AVG Duty = 5015%(X100)
2408 11:17:39.344670
2409 11:17:39.345276 ==DQM 1 ==
2410 11:17:39.347608 Final DQM duty delay cell = -4
2411 11:17:39.351113 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2412 11:17:39.354762 [-4] MIN Duty = 4782%(X100), DQS PI = 22
2413 11:17:39.357850 [-4] AVG Duty = 4891%(X100)
2414 11:17:39.358327
2415 11:17:39.360882 CH1 DQM 0 Duty spec in!! Max-Min= 155%
2416 11:17:39.361357
2417 11:17:39.364448 CH1 DQM 1 Duty spec in!! Max-Min= 218%
2418 11:17:39.367509 [DutyScan_Calibration_Flow] ====Done====
2419 11:17:39.368068
2420 11:17:39.371108 [DutyScan_Calibration_Flow] k_type=2
2421 11:17:39.388514
2422 11:17:39.389176 ==DQ 0 ==
2423 11:17:39.391536 Final DQ duty delay cell = 0
2424 11:17:39.394652 [0] MAX Duty = 5062%(X100), DQS PI = 18
2425 11:17:39.398170 [0] MIN Duty = 4938%(X100), DQS PI = 46
2426 11:17:39.398633 [0] AVG Duty = 5000%(X100)
2427 11:17:39.401463
2428 11:17:39.402055 ==DQ 1 ==
2429 11:17:39.404530 Final DQ duty delay cell = 0
2430 11:17:39.408015 [0] MAX Duty = 5031%(X100), DQS PI = 2
2431 11:17:39.411468 [0] MIN Duty = 4813%(X100), DQS PI = 36
2432 11:17:39.412085 [0] AVG Duty = 4922%(X100)
2433 11:17:39.412498
2434 11:17:39.414685 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2435 11:17:39.417830
2436 11:17:39.421330 CH1 DQ 1 Duty spec in!! Max-Min= 218%
2437 11:17:39.424663 [DutyScan_Calibration_Flow] ====Done====
2438 11:17:39.428011 nWR fixed to 30
2439 11:17:39.428484 [ModeRegInit_LP4] CH0 RK0
2440 11:17:39.431139 [ModeRegInit_LP4] CH0 RK1
2441 11:17:39.434539 [ModeRegInit_LP4] CH1 RK0
2442 11:17:39.435009 [ModeRegInit_LP4] CH1 RK1
2443 11:17:39.437989 match AC timing 7
2444 11:17:39.441623 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2445 11:17:39.447977 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2446 11:17:39.451736 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2447 11:17:39.454532 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2448 11:17:39.461425 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2449 11:17:39.461898 ==
2450 11:17:39.464440 Dram Type= 6, Freq= 0, CH_0, rank 0
2451 11:17:39.468207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2452 11:17:39.468831 ==
2453 11:17:39.474894 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2454 11:17:39.481314 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2455 11:17:39.488077 [CA 0] Center 38 (7~69) winsize 63
2456 11:17:39.491498 [CA 1] Center 38 (7~69) winsize 63
2457 11:17:39.494557 [CA 2] Center 34 (4~65) winsize 62
2458 11:17:39.498033 [CA 3] Center 34 (4~65) winsize 62
2459 11:17:39.501364 [CA 4] Center 33 (3~64) winsize 62
2460 11:17:39.504583 [CA 5] Center 32 (2~63) winsize 62
2461 11:17:39.505195
2462 11:17:39.507766 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2463 11:17:39.508265
2464 11:17:39.511300 [CATrainingPosCal] consider 1 rank data
2465 11:17:39.514339 u2DelayCellTimex100 = 270/100 ps
2466 11:17:39.517794 CA0 delay=38 (7~69),Diff = 6 PI (28 cell)
2467 11:17:39.524515 CA1 delay=38 (7~69),Diff = 6 PI (28 cell)
2468 11:17:39.527627 CA2 delay=34 (4~65),Diff = 2 PI (9 cell)
2469 11:17:39.531141 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2470 11:17:39.534692 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2471 11:17:39.537644 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
2472 11:17:39.538205
2473 11:17:39.541402 CA PerBit enable=1, Macro0, CA PI delay=32
2474 11:17:39.541970
2475 11:17:39.544252 [CBTSetCACLKResult] CA Dly = 32
2476 11:17:39.544829 CS Dly: 6 (0~37)
2477 11:17:39.547357 ==
2478 11:17:39.551066 Dram Type= 6, Freq= 0, CH_0, rank 1
2479 11:17:39.554815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2480 11:17:39.555396 ==
2481 11:17:39.560406 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2482 11:17:39.564342 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2483 11:17:39.573823 [CA 0] Center 38 (7~69) winsize 63
2484 11:17:39.577324 [CA 1] Center 38 (7~69) winsize 63
2485 11:17:39.580234 [CA 2] Center 35 (5~66) winsize 62
2486 11:17:39.583464 [CA 3] Center 35 (5~66) winsize 62
2487 11:17:39.586986 [CA 4] Center 34 (3~65) winsize 63
2488 11:17:39.590549 [CA 5] Center 33 (3~64) winsize 62
2489 11:17:39.591117
2490 11:17:39.593606 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2491 11:17:39.594168
2492 11:17:39.596921 [CATrainingPosCal] consider 2 rank data
2493 11:17:39.600040 u2DelayCellTimex100 = 270/100 ps
2494 11:17:39.603215 CA0 delay=38 (7~69),Diff = 5 PI (24 cell)
2495 11:17:39.610113 CA1 delay=38 (7~69),Diff = 5 PI (24 cell)
2496 11:17:39.613216 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
2497 11:17:39.616903 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2498 11:17:39.619923 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2499 11:17:39.623982 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2500 11:17:39.624544
2501 11:17:39.626940 CA PerBit enable=1, Macro0, CA PI delay=33
2502 11:17:39.627603
2503 11:17:39.630326 [CBTSetCACLKResult] CA Dly = 33
2504 11:17:39.630788 CS Dly: 7 (0~39)
2505 11:17:39.631155
2506 11:17:39.637190 ----->DramcWriteLeveling(PI) begin...
2507 11:17:39.637761 ==
2508 11:17:39.640150 Dram Type= 6, Freq= 0, CH_0, rank 0
2509 11:17:39.643296 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2510 11:17:39.643765 ==
2511 11:17:39.646459 Write leveling (Byte 0): 35 => 35
2512 11:17:39.649668 Write leveling (Byte 1): 30 => 30
2513 11:17:39.653425 DramcWriteLeveling(PI) end<-----
2514 11:17:39.653991
2515 11:17:39.654357 ==
2516 11:17:39.656534 Dram Type= 6, Freq= 0, CH_0, rank 0
2517 11:17:39.659675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2518 11:17:39.660147 ==
2519 11:17:39.663467 [Gating] SW mode calibration
2520 11:17:39.669500 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2521 11:17:39.676262 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2522 11:17:39.679515 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2523 11:17:39.682701 0 15 4 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
2524 11:17:39.689795 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2525 11:17:39.693151 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2526 11:17:39.696377 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2527 11:17:39.703095 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2528 11:17:39.706014 0 15 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 0)
2529 11:17:39.709505 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
2530 11:17:39.716022 1 0 0 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (0 0)
2531 11:17:39.719878 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2532 11:17:39.722783 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2533 11:17:39.729619 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2534 11:17:39.732832 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2535 11:17:39.736108 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2536 11:17:39.739459 1 0 24 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
2537 11:17:39.745949 1 0 28 | B1->B0 | 2828 4646 | 0 0 | (1 1) (0 0)
2538 11:17:39.749491 1 1 0 | B1->B0 | 2e2e 4646 | 1 0 | (0 0) (0 0)
2539 11:17:39.753178 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2540 11:17:39.759460 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2541 11:17:39.762552 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2542 11:17:39.766144 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2543 11:17:39.772989 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2544 11:17:39.776017 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2545 11:17:39.779650 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2546 11:17:39.786004 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2547 11:17:39.789310 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 11:17:39.792722 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 11:17:39.799530 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 11:17:39.802669 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 11:17:39.806029 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 11:17:39.812669 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 11:17:39.816183 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 11:17:39.819333 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 11:17:39.825625 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 11:17:39.829353 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 11:17:39.832227 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 11:17:39.838938 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 11:17:39.843154 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2560 11:17:39.845822 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2561 11:17:39.852344 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2562 11:17:39.852953 Total UI for P1: 0, mck2ui 16
2563 11:17:39.858722 best dqsien dly found for B0: ( 1, 3, 26)
2564 11:17:39.862053 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2565 11:17:39.865392 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2566 11:17:39.869216 Total UI for P1: 0, mck2ui 16
2567 11:17:39.872397 best dqsien dly found for B1: ( 1, 3, 30)
2568 11:17:39.875750 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2569 11:17:39.878943 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2570 11:17:39.879515
2571 11:17:39.882615 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2572 11:17:39.888854 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2573 11:17:39.889421 [Gating] SW calibration Done
2574 11:17:39.889802 ==
2575 11:17:39.892700 Dram Type= 6, Freq= 0, CH_0, rank 0
2576 11:17:39.898939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2577 11:17:39.899518 ==
2578 11:17:39.899897 RX Vref Scan: 0
2579 11:17:39.900248
2580 11:17:39.901888 RX Vref 0 -> 0, step: 1
2581 11:17:39.902358
2582 11:17:39.905443 RX Delay -40 -> 252, step: 8
2583 11:17:39.909063 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
2584 11:17:39.912329 iDelay=208, Bit 1, Center 123 (56 ~ 191) 136
2585 11:17:39.915233 iDelay=208, Bit 2, Center 119 (48 ~ 191) 144
2586 11:17:39.922212 iDelay=208, Bit 3, Center 119 (48 ~ 191) 144
2587 11:17:39.925091 iDelay=208, Bit 4, Center 127 (56 ~ 199) 144
2588 11:17:39.928645 iDelay=208, Bit 5, Center 115 (48 ~ 183) 136
2589 11:17:39.932135 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
2590 11:17:39.935278 iDelay=208, Bit 7, Center 127 (56 ~ 199) 144
2591 11:17:39.941935 iDelay=208, Bit 8, Center 99 (32 ~ 167) 136
2592 11:17:39.945497 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
2593 11:17:39.948613 iDelay=208, Bit 10, Center 107 (40 ~ 175) 136
2594 11:17:39.951837 iDelay=208, Bit 11, Center 107 (40 ~ 175) 136
2595 11:17:39.955076 iDelay=208, Bit 12, Center 115 (48 ~ 183) 136
2596 11:17:39.961557 iDelay=208, Bit 13, Center 115 (48 ~ 183) 136
2597 11:17:39.965057 iDelay=208, Bit 14, Center 123 (56 ~ 191) 136
2598 11:17:39.968640 iDelay=208, Bit 15, Center 115 (48 ~ 183) 136
2599 11:17:39.969248 ==
2600 11:17:39.971902 Dram Type= 6, Freq= 0, CH_0, rank 0
2601 11:17:39.975005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2602 11:17:39.975495 ==
2603 11:17:39.978573 DQS Delay:
2604 11:17:39.979166 DQS0 = 0, DQS1 = 0
2605 11:17:39.981582 DQM Delay:
2606 11:17:39.982050 DQM0 = 123, DQM1 = 110
2607 11:17:39.982423 DQ Delay:
2608 11:17:39.988863 DQ0 =123, DQ1 =123, DQ2 =119, DQ3 =119
2609 11:17:39.991672 DQ4 =127, DQ5 =115, DQ6 =131, DQ7 =127
2610 11:17:39.995040 DQ8 =99, DQ9 =99, DQ10 =107, DQ11 =107
2611 11:17:39.998789 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2612 11:17:39.999362
2613 11:17:39.999738
2614 11:17:40.000085 ==
2615 11:17:40.002097 Dram Type= 6, Freq= 0, CH_0, rank 0
2616 11:17:40.004993 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2617 11:17:40.005570 ==
2618 11:17:40.005951
2619 11:17:40.006296
2620 11:17:40.008183 TX Vref Scan disable
2621 11:17:40.011271 == TX Byte 0 ==
2622 11:17:40.015026 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2623 11:17:40.018110 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2624 11:17:40.021666 == TX Byte 1 ==
2625 11:17:40.024812 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2626 11:17:40.028306 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2627 11:17:40.028915 ==
2628 11:17:40.031140 Dram Type= 6, Freq= 0, CH_0, rank 0
2629 11:17:40.034712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2630 11:17:40.038144 ==
2631 11:17:40.049147 TX Vref=22, minBit 7, minWin=22, winSum=402
2632 11:17:40.051882 TX Vref=24, minBit 0, minWin=24, winSum=406
2633 11:17:40.055257 TX Vref=26, minBit 5, minWin=24, winSum=414
2634 11:17:40.058089 TX Vref=28, minBit 0, minWin=25, winSum=418
2635 11:17:40.061663 TX Vref=30, minBit 1, minWin=25, winSum=419
2636 11:17:40.068445 TX Vref=32, minBit 2, minWin=24, winSum=411
2637 11:17:40.071508 [TxChooseVref] Worse bit 1, Min win 25, Win sum 419, Final Vref 30
2638 11:17:40.072088
2639 11:17:40.074639 Final TX Range 1 Vref 30
2640 11:17:40.075213
2641 11:17:40.075592 ==
2642 11:17:40.078065 Dram Type= 6, Freq= 0, CH_0, rank 0
2643 11:17:40.081142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2644 11:17:40.084717 ==
2645 11:17:40.085334
2646 11:17:40.085707
2647 11:17:40.086057 TX Vref Scan disable
2648 11:17:40.087934 == TX Byte 0 ==
2649 11:17:40.091476 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2650 11:17:40.098521 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2651 11:17:40.099097 == TX Byte 1 ==
2652 11:17:40.101609 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2653 11:17:40.107878 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2654 11:17:40.108441
2655 11:17:40.108843 [DATLAT]
2656 11:17:40.109195 Freq=1200, CH0 RK0
2657 11:17:40.109531
2658 11:17:40.111214 DATLAT Default: 0xd
2659 11:17:40.114435 0, 0xFFFF, sum = 0
2660 11:17:40.114912 1, 0xFFFF, sum = 0
2661 11:17:40.117993 2, 0xFFFF, sum = 0
2662 11:17:40.118575 3, 0xFFFF, sum = 0
2663 11:17:40.121312 4, 0xFFFF, sum = 0
2664 11:17:40.121787 5, 0xFFFF, sum = 0
2665 11:17:40.124349 6, 0xFFFF, sum = 0
2666 11:17:40.124862 7, 0xFFFF, sum = 0
2667 11:17:40.128136 8, 0xFFFF, sum = 0
2668 11:17:40.128719 9, 0xFFFF, sum = 0
2669 11:17:40.131347 10, 0xFFFF, sum = 0
2670 11:17:40.131925 11, 0xFFFF, sum = 0
2671 11:17:40.134250 12, 0x0, sum = 1
2672 11:17:40.134730 13, 0x0, sum = 2
2673 11:17:40.138325 14, 0x0, sum = 3
2674 11:17:40.138922 15, 0x0, sum = 4
2675 11:17:40.141122 best_step = 13
2676 11:17:40.141693
2677 11:17:40.142069 ==
2678 11:17:40.144604 Dram Type= 6, Freq= 0, CH_0, rank 0
2679 11:17:40.147875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2680 11:17:40.148460 ==
2681 11:17:40.148873 RX Vref Scan: 1
2682 11:17:40.149231
2683 11:17:40.150952 Set Vref Range= 32 -> 127
2684 11:17:40.151419
2685 11:17:40.154612 RX Vref 32 -> 127, step: 1
2686 11:17:40.155187
2687 11:17:40.157663 RX Delay -13 -> 252, step: 4
2688 11:17:40.158133
2689 11:17:40.160892 Set Vref, RX VrefLevel [Byte0]: 32
2690 11:17:40.164422 [Byte1]: 32
2691 11:17:40.164943
2692 11:17:40.167563 Set Vref, RX VrefLevel [Byte0]: 33
2693 11:17:40.170883 [Byte1]: 33
2694 11:17:40.174798
2695 11:17:40.177763 Set Vref, RX VrefLevel [Byte0]: 34
2696 11:17:40.181128 [Byte1]: 34
2697 11:17:40.181703
2698 11:17:40.184289 Set Vref, RX VrefLevel [Byte0]: 35
2699 11:17:40.187630 [Byte1]: 35
2700 11:17:40.188207
2701 11:17:40.191579 Set Vref, RX VrefLevel [Byte0]: 36
2702 11:17:40.194481 [Byte1]: 36
2703 11:17:40.198158
2704 11:17:40.198732 Set Vref, RX VrefLevel [Byte0]: 37
2705 11:17:40.201472 [Byte1]: 37
2706 11:17:40.206455
2707 11:17:40.207019 Set Vref, RX VrefLevel [Byte0]: 38
2708 11:17:40.209335 [Byte1]: 38
2709 11:17:40.213717
2710 11:17:40.214174 Set Vref, RX VrefLevel [Byte0]: 39
2711 11:17:40.216862 [Byte1]: 39
2712 11:17:40.221336
2713 11:17:40.221807 Set Vref, RX VrefLevel [Byte0]: 40
2714 11:17:40.225095 [Byte1]: 40
2715 11:17:40.229410
2716 11:17:40.229867 Set Vref, RX VrefLevel [Byte0]: 41
2717 11:17:40.232921 [Byte1]: 41
2718 11:17:40.237615
2719 11:17:40.238180 Set Vref, RX VrefLevel [Byte0]: 42
2720 11:17:40.240930 [Byte1]: 42
2721 11:17:40.245289
2722 11:17:40.245849 Set Vref, RX VrefLevel [Byte0]: 43
2723 11:17:40.248997 [Byte1]: 43
2724 11:17:40.253435
2725 11:17:40.253998 Set Vref, RX VrefLevel [Byte0]: 44
2726 11:17:40.256983 [Byte1]: 44
2727 11:17:40.260911
2728 11:17:40.261429 Set Vref, RX VrefLevel [Byte0]: 45
2729 11:17:40.264689 [Byte1]: 45
2730 11:17:40.269276
2731 11:17:40.269842 Set Vref, RX VrefLevel [Byte0]: 46
2732 11:17:40.272432 [Byte1]: 46
2733 11:17:40.277152
2734 11:17:40.277725 Set Vref, RX VrefLevel [Byte0]: 47
2735 11:17:40.280713 [Byte1]: 47
2736 11:17:40.285120
2737 11:17:40.285697 Set Vref, RX VrefLevel [Byte0]: 48
2738 11:17:40.288522 [Byte1]: 48
2739 11:17:40.292999
2740 11:17:40.293576 Set Vref, RX VrefLevel [Byte0]: 49
2741 11:17:40.296048 [Byte1]: 49
2742 11:17:40.300796
2743 11:17:40.301263 Set Vref, RX VrefLevel [Byte0]: 50
2744 11:17:40.303915 [Byte1]: 50
2745 11:17:40.308526
2746 11:17:40.309039 Set Vref, RX VrefLevel [Byte0]: 51
2747 11:17:40.311817 [Byte1]: 51
2748 11:17:40.316254
2749 11:17:40.316582 Set Vref, RX VrefLevel [Byte0]: 52
2750 11:17:40.319307 [Byte1]: 52
2751 11:17:40.323972
2752 11:17:40.324216 Set Vref, RX VrefLevel [Byte0]: 53
2753 11:17:40.327331 [Byte1]: 53
2754 11:17:40.331733
2755 11:17:40.331891 Set Vref, RX VrefLevel [Byte0]: 54
2756 11:17:40.335534 [Byte1]: 54
2757 11:17:40.340167
2758 11:17:40.340380 Set Vref, RX VrefLevel [Byte0]: 55
2759 11:17:40.343252 [Byte1]: 55
2760 11:17:40.347994
2761 11:17:40.348222 Set Vref, RX VrefLevel [Byte0]: 56
2762 11:17:40.351581 [Byte1]: 56
2763 11:17:40.355781
2764 11:17:40.356017 Set Vref, RX VrefLevel [Byte0]: 57
2765 11:17:40.359078 [Byte1]: 57
2766 11:17:40.363931
2767 11:17:40.364165 Set Vref, RX VrefLevel [Byte0]: 58
2768 11:17:40.366888 [Byte1]: 58
2769 11:17:40.371340
2770 11:17:40.374869 Set Vref, RX VrefLevel [Byte0]: 59
2771 11:17:40.375159 [Byte1]: 59
2772 11:17:40.379903
2773 11:17:40.380231 Set Vref, RX VrefLevel [Byte0]: 60
2774 11:17:40.382428 [Byte1]: 60
2775 11:17:40.387312
2776 11:17:40.387712 Set Vref, RX VrefLevel [Byte0]: 61
2777 11:17:40.390867 [Byte1]: 61
2778 11:17:40.395048
2779 11:17:40.395517 Set Vref, RX VrefLevel [Byte0]: 62
2780 11:17:40.398711 [Byte1]: 62
2781 11:17:40.403312
2782 11:17:40.403873 Set Vref, RX VrefLevel [Byte0]: 63
2783 11:17:40.406546 [Byte1]: 63
2784 11:17:40.411145
2785 11:17:40.411701 Set Vref, RX VrefLevel [Byte0]: 64
2786 11:17:40.414253 [Byte1]: 64
2787 11:17:40.419243
2788 11:17:40.419711 Set Vref, RX VrefLevel [Byte0]: 65
2789 11:17:40.422334 [Byte1]: 65
2790 11:17:40.427233
2791 11:17:40.427796 Set Vref, RX VrefLevel [Byte0]: 66
2792 11:17:40.430222 [Byte1]: 66
2793 11:17:40.434821
2794 11:17:40.435378 Set Vref, RX VrefLevel [Byte0]: 67
2795 11:17:40.441279 [Byte1]: 67
2796 11:17:40.441841
2797 11:17:40.444536 Set Vref, RX VrefLevel [Byte0]: 68
2798 11:17:40.448180 [Byte1]: 68
2799 11:17:40.448741
2800 11:17:40.451268 Set Vref, RX VrefLevel [Byte0]: 69
2801 11:17:40.454862 [Byte1]: 69
2802 11:17:40.458503
2803 11:17:40.458978 Final RX Vref Byte 0 = 57 to rank0
2804 11:17:40.462087 Final RX Vref Byte 1 = 49 to rank0
2805 11:17:40.465005 Final RX Vref Byte 0 = 57 to rank1
2806 11:17:40.468516 Final RX Vref Byte 1 = 49 to rank1==
2807 11:17:40.471870 Dram Type= 6, Freq= 0, CH_0, rank 0
2808 11:17:40.478490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2809 11:17:40.479049 ==
2810 11:17:40.479455 DQS Delay:
2811 11:17:40.479802 DQS0 = 0, DQS1 = 0
2812 11:17:40.481564 DQM Delay:
2813 11:17:40.482020 DQM0 = 122, DQM1 = 109
2814 11:17:40.485278 DQ Delay:
2815 11:17:40.488656 DQ0 =122, DQ1 =122, DQ2 =118, DQ3 =120
2816 11:17:40.492265 DQ4 =126, DQ5 =116, DQ6 =130, DQ7 =128
2817 11:17:40.495049 DQ8 =100, DQ9 =94, DQ10 =110, DQ11 =106
2818 11:17:40.498475 DQ12 =116, DQ13 =110, DQ14 =122, DQ15 =116
2819 11:17:40.498939
2820 11:17:40.499305
2821 11:17:40.505333 [DQSOSCAuto] RK0, (LSB)MR18= 0x905, (MSB)MR19= 0x404, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
2822 11:17:40.508675 CH0 RK0: MR19=404, MR18=905
2823 11:17:40.515283 CH0_RK0: MR19=0x404, MR18=0x905, DQSOSC=406, MR23=63, INC=39, DEC=26
2824 11:17:40.515847
2825 11:17:40.518347 ----->DramcWriteLeveling(PI) begin...
2826 11:17:40.518816 ==
2827 11:17:40.522142 Dram Type= 6, Freq= 0, CH_0, rank 1
2828 11:17:40.525089 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2829 11:17:40.525657 ==
2830 11:17:40.529140 Write leveling (Byte 0): 36 => 36
2831 11:17:40.531906 Write leveling (Byte 1): 30 => 30
2832 11:17:40.535045 DramcWriteLeveling(PI) end<-----
2833 11:17:40.535603
2834 11:17:40.535970 ==
2835 11:17:40.538516 Dram Type= 6, Freq= 0, CH_0, rank 1
2836 11:17:40.545381 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2837 11:17:40.545938 ==
2838 11:17:40.546312 [Gating] SW mode calibration
2839 11:17:40.554991 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2840 11:17:40.558276 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2841 11:17:40.561513 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
2842 11:17:40.568298 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2843 11:17:40.571693 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2844 11:17:40.575143 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2845 11:17:40.581333 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2846 11:17:40.584952 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2847 11:17:40.588285 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2848 11:17:40.594876 0 15 28 | B1->B0 | 2f2f 2d2d | 0 1 | (0 0) (1 0)
2849 11:17:40.598058 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2850 11:17:40.601228 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2851 11:17:40.608038 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2852 11:17:40.611124 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2853 11:17:40.615100 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2854 11:17:40.621391 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2855 11:17:40.624616 1 0 24 | B1->B0 | 2424 2b2b | 0 0 | (0 0) (0 0)
2856 11:17:40.628119 1 0 28 | B1->B0 | 3e3e 4343 | 1 0 | (0 0) (0 0)
2857 11:17:40.634748 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2858 11:17:40.637745 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2859 11:17:40.641407 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2860 11:17:40.647777 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2861 11:17:40.651101 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2862 11:17:40.654541 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2863 11:17:40.661299 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2864 11:17:40.664402 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2865 11:17:40.667596 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
2866 11:17:40.674436 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 11:17:40.677655 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 11:17:40.681382 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 11:17:40.687796 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 11:17:40.690661 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 11:17:40.694397 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 11:17:40.701067 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 11:17:40.704055 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 11:17:40.707528 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 11:17:40.714135 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2876 11:17:40.717234 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2877 11:17:40.720641 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 11:17:40.727110 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 11:17:40.730601 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 11:17:40.734259 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2881 11:17:40.737435 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
2882 11:17:40.741303 Total UI for P1: 0, mck2ui 16
2883 11:17:40.744360 best dqsien dly found for B1: ( 1, 3, 28)
2884 11:17:40.750849 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2885 11:17:40.751413 Total UI for P1: 0, mck2ui 16
2886 11:17:40.757633 best dqsien dly found for B0: ( 1, 3, 30)
2887 11:17:40.760697 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
2888 11:17:40.763781 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
2889 11:17:40.764245
2890 11:17:40.767173 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
2891 11:17:40.770548 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
2892 11:17:40.774160 [Gating] SW calibration Done
2893 11:17:40.774619 ==
2894 11:17:40.777313 Dram Type= 6, Freq= 0, CH_0, rank 1
2895 11:17:40.780788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2896 11:17:40.781361 ==
2897 11:17:40.784066 RX Vref Scan: 0
2898 11:17:40.784627
2899 11:17:40.785029 RX Vref 0 -> 0, step: 1
2900 11:17:40.785373
2901 11:17:40.787857 RX Delay -40 -> 252, step: 8
2902 11:17:40.790666 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2903 11:17:40.797652 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2904 11:17:40.801271 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2905 11:17:40.804555 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2906 11:17:40.807720 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2907 11:17:40.810713 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2908 11:17:40.817230 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2909 11:17:40.820655 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2910 11:17:40.824098 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2911 11:17:40.827354 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2912 11:17:40.830872 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2913 11:17:40.837948 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2914 11:17:40.840796 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2915 11:17:40.844026 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2916 11:17:40.847563 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2917 11:17:40.850803 iDelay=200, Bit 15, Center 111 (48 ~ 175) 128
2918 11:17:40.854034 ==
2919 11:17:40.857328 Dram Type= 6, Freq= 0, CH_0, rank 1
2920 11:17:40.860332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2921 11:17:40.860812 ==
2922 11:17:40.861187 DQS Delay:
2923 11:17:40.863966 DQS0 = 0, DQS1 = 0
2924 11:17:40.864425 DQM Delay:
2925 11:17:40.867003 DQM0 = 120, DQM1 = 108
2926 11:17:40.867463 DQ Delay:
2927 11:17:40.870533 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =115
2928 11:17:40.873916 DQ4 =119, DQ5 =115, DQ6 =127, DQ7 =127
2929 11:17:40.877457 DQ8 =99, DQ9 =95, DQ10 =107, DQ11 =107
2930 11:17:40.880536 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =111
2931 11:17:40.881139
2932 11:17:40.881518
2933 11:17:40.881858 ==
2934 11:17:40.883663 Dram Type= 6, Freq= 0, CH_0, rank 1
2935 11:17:40.890540 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2936 11:17:40.891121 ==
2937 11:17:40.891503
2938 11:17:40.891843
2939 11:17:40.892164 TX Vref Scan disable
2940 11:17:40.894006 == TX Byte 0 ==
2941 11:17:40.897335 Update DQ dly =855 (3 ,2, 23) DQ OEN =(2 ,7)
2942 11:17:40.904217 Update DQM dly =855 (3 ,2, 23) DQM OEN =(2 ,7)
2943 11:17:40.904851 == TX Byte 1 ==
2944 11:17:40.906981 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2945 11:17:40.913959 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2946 11:17:40.914512 ==
2947 11:17:40.917127 Dram Type= 6, Freq= 0, CH_0, rank 1
2948 11:17:40.920614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2949 11:17:40.921211 ==
2950 11:17:40.932280 TX Vref=22, minBit 2, minWin=25, winSum=416
2951 11:17:40.935598 TX Vref=24, minBit 0, minWin=25, winSum=413
2952 11:17:40.938810 TX Vref=26, minBit 1, minWin=25, winSum=421
2953 11:17:40.942048 TX Vref=28, minBit 1, minWin=24, winSum=421
2954 11:17:40.945227 TX Vref=30, minBit 0, minWin=26, winSum=426
2955 11:17:40.952227 TX Vref=32, minBit 2, minWin=25, winSum=425
2956 11:17:40.955505 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 30
2957 11:17:40.956072
2958 11:17:40.958773 Final TX Range 1 Vref 30
2959 11:17:40.959236
2960 11:17:40.959794 ==
2961 11:17:40.962492 Dram Type= 6, Freq= 0, CH_0, rank 1
2962 11:17:40.965835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2963 11:17:40.966298 ==
2964 11:17:40.968488
2965 11:17:40.968979
2966 11:17:40.969349 TX Vref Scan disable
2967 11:17:40.972056 == TX Byte 0 ==
2968 11:17:40.975444 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2969 11:17:40.982074 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2970 11:17:40.982635 == TX Byte 1 ==
2971 11:17:40.985184 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2972 11:17:40.992116 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2973 11:17:40.992670
2974 11:17:40.993122 [DATLAT]
2975 11:17:40.993471 Freq=1200, CH0 RK1
2976 11:17:40.993810
2977 11:17:40.995143 DATLAT Default: 0xd
2978 11:17:40.995606 0, 0xFFFF, sum = 0
2979 11:17:40.998877 1, 0xFFFF, sum = 0
2980 11:17:40.999449 2, 0xFFFF, sum = 0
2981 11:17:41.002029 3, 0xFFFF, sum = 0
2982 11:17:41.006019 4, 0xFFFF, sum = 0
2983 11:17:41.006593 5, 0xFFFF, sum = 0
2984 11:17:41.008602 6, 0xFFFF, sum = 0
2985 11:17:41.009102 7, 0xFFFF, sum = 0
2986 11:17:41.012175 8, 0xFFFF, sum = 0
2987 11:17:41.012642 9, 0xFFFF, sum = 0
2988 11:17:41.016086 10, 0xFFFF, sum = 0
2989 11:17:41.016667 11, 0xFFFF, sum = 0
2990 11:17:41.018427 12, 0x0, sum = 1
2991 11:17:41.018897 13, 0x0, sum = 2
2992 11:17:41.021785 14, 0x0, sum = 3
2993 11:17:41.022471 15, 0x0, sum = 4
2994 11:17:41.023065 best_step = 13
2995 11:17:41.024966
2996 11:17:41.025608 ==
2997 11:17:41.028259 Dram Type= 6, Freq= 0, CH_0, rank 1
2998 11:17:41.031562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2999 11:17:41.032117 ==
3000 11:17:41.032623 RX Vref Scan: 0
3001 11:17:41.033163
3002 11:17:41.034807 RX Vref 0 -> 0, step: 1
3003 11:17:41.035308
3004 11:17:41.038362 RX Delay -21 -> 252, step: 4
3005 11:17:41.041570 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3006 11:17:41.048388 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3007 11:17:41.051970 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3008 11:17:41.054921 iDelay=195, Bit 3, Center 116 (51 ~ 182) 132
3009 11:17:41.058654 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3010 11:17:41.061740 iDelay=195, Bit 5, Center 114 (51 ~ 178) 128
3011 11:17:41.068553 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3012 11:17:41.071763 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3013 11:17:41.075082 iDelay=195, Bit 8, Center 98 (35 ~ 162) 128
3014 11:17:41.078459 iDelay=195, Bit 9, Center 94 (31 ~ 158) 128
3015 11:17:41.081481 iDelay=195, Bit 10, Center 110 (47 ~ 174) 128
3016 11:17:41.087914 iDelay=195, Bit 11, Center 106 (43 ~ 170) 128
3017 11:17:41.091642 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3018 11:17:41.094897 iDelay=195, Bit 13, Center 110 (47 ~ 174) 128
3019 11:17:41.098110 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3020 11:17:41.101436 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3021 11:17:41.105161 ==
3022 11:17:41.107936 Dram Type= 6, Freq= 0, CH_0, rank 1
3023 11:17:41.111402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3024 11:17:41.111875 ==
3025 11:17:41.112264 DQS Delay:
3026 11:17:41.115077 DQS0 = 0, DQS1 = 0
3027 11:17:41.115542 DQM Delay:
3028 11:17:41.117996 DQM0 = 120, DQM1 = 107
3029 11:17:41.118419 DQ Delay:
3030 11:17:41.121501 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =116
3031 11:17:41.124555 DQ4 =122, DQ5 =114, DQ6 =126, DQ7 =126
3032 11:17:41.128022 DQ8 =98, DQ9 =94, DQ10 =110, DQ11 =106
3033 11:17:41.131367 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =114
3034 11:17:41.131900
3035 11:17:41.132278
3036 11:17:41.141365 [DQSOSCAuto] RK1, (LSB)MR18= 0xaf2, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 406 ps
3037 11:17:41.141898 CH0 RK1: MR19=403, MR18=AF2
3038 11:17:41.147877 CH0_RK1: MR19=0x403, MR18=0xAF2, DQSOSC=406, MR23=63, INC=39, DEC=26
3039 11:17:41.151179 [RxdqsGatingPostProcess] freq 1200
3040 11:17:41.157571 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3041 11:17:41.161049 best DQS0 dly(2T, 0.5T) = (0, 11)
3042 11:17:41.164248 best DQS1 dly(2T, 0.5T) = (0, 11)
3043 11:17:41.167663 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3044 11:17:41.171142 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3045 11:17:41.174428 best DQS0 dly(2T, 0.5T) = (0, 11)
3046 11:17:41.174855 best DQS1 dly(2T, 0.5T) = (0, 11)
3047 11:17:41.177744 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3048 11:17:41.181058 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3049 11:17:41.184513 Pre-setting of DQS Precalculation
3050 11:17:41.191207 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3051 11:17:41.191634 ==
3052 11:17:41.194630 Dram Type= 6, Freq= 0, CH_1, rank 0
3053 11:17:41.197500 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3054 11:17:41.197931 ==
3055 11:17:41.204227 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3056 11:17:41.210906 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3057 11:17:41.218246 [CA 0] Center 37 (7~67) winsize 61
3058 11:17:41.221429 [CA 1] Center 37 (7~68) winsize 62
3059 11:17:41.224496 [CA 2] Center 35 (5~65) winsize 61
3060 11:17:41.228343 [CA 3] Center 33 (3~64) winsize 62
3061 11:17:41.231605 [CA 4] Center 33 (3~64) winsize 62
3062 11:17:41.234861 [CA 5] Center 33 (3~63) winsize 61
3063 11:17:41.235279
3064 11:17:41.238455 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3065 11:17:41.238911
3066 11:17:41.241418 [CATrainingPosCal] consider 1 rank data
3067 11:17:41.244569 u2DelayCellTimex100 = 270/100 ps
3068 11:17:41.248457 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3069 11:17:41.251252 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3070 11:17:41.257938 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3071 11:17:41.261361 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3072 11:17:41.264461 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3073 11:17:41.267937 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3074 11:17:41.268354
3075 11:17:41.271276 CA PerBit enable=1, Macro0, CA PI delay=33
3076 11:17:41.271691
3077 11:17:41.274478 [CBTSetCACLKResult] CA Dly = 33
3078 11:17:41.274894 CS Dly: 5 (0~36)
3079 11:17:41.277724 ==
3080 11:17:41.278141 Dram Type= 6, Freq= 0, CH_1, rank 1
3081 11:17:41.284452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3082 11:17:41.284908 ==
3083 11:17:41.288041 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3084 11:17:41.294927 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3085 11:17:41.303598 [CA 0] Center 38 (8~68) winsize 61
3086 11:17:41.307122 [CA 1] Center 37 (7~68) winsize 62
3087 11:17:41.310408 [CA 2] Center 35 (5~66) winsize 62
3088 11:17:41.313647 [CA 3] Center 34 (4~65) winsize 62
3089 11:17:41.316994 [CA 4] Center 34 (4~64) winsize 61
3090 11:17:41.320279 [CA 5] Center 33 (3~64) winsize 62
3091 11:17:41.320737
3092 11:17:41.323778 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3093 11:17:41.324284
3094 11:17:41.326854 [CATrainingPosCal] consider 2 rank data
3095 11:17:41.330157 u2DelayCellTimex100 = 270/100 ps
3096 11:17:41.333993 CA0 delay=37 (8~67),Diff = 4 PI (19 cell)
3097 11:17:41.336940 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3098 11:17:41.343358 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3099 11:17:41.347009 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3100 11:17:41.350294 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3101 11:17:41.353444 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3102 11:17:41.354023
3103 11:17:41.357000 CA PerBit enable=1, Macro0, CA PI delay=33
3104 11:17:41.357568
3105 11:17:41.360090 [CBTSetCACLKResult] CA Dly = 33
3106 11:17:41.360559 CS Dly: 6 (0~38)
3107 11:17:41.360962
3108 11:17:41.367054 ----->DramcWriteLeveling(PI) begin...
3109 11:17:41.367768 ==
3110 11:17:41.369936 Dram Type= 6, Freq= 0, CH_1, rank 0
3111 11:17:41.373240 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3112 11:17:41.373665 ==
3113 11:17:41.376556 Write leveling (Byte 0): 23 => 23
3114 11:17:41.379919 Write leveling (Byte 1): 28 => 28
3115 11:17:41.383351 DramcWriteLeveling(PI) end<-----
3116 11:17:41.383769
3117 11:17:41.384101 ==
3118 11:17:41.386740 Dram Type= 6, Freq= 0, CH_1, rank 0
3119 11:17:41.389768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3120 11:17:41.390192 ==
3121 11:17:41.393001 [Gating] SW mode calibration
3122 11:17:41.400034 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3123 11:17:41.406691 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3124 11:17:41.409637 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3125 11:17:41.412790 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3126 11:17:41.419711 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3127 11:17:41.423199 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3128 11:17:41.426169 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3129 11:17:41.433004 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3130 11:17:41.436417 0 15 24 | B1->B0 | 2d2d 2727 | 0 0 | (0 1) (1 0)
3131 11:17:41.440249 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3132 11:17:41.446842 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3133 11:17:41.449898 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3134 11:17:41.453120 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3135 11:17:41.456120 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3136 11:17:41.463006 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3137 11:17:41.466456 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3138 11:17:41.469413 1 0 24 | B1->B0 | 3d3d 4444 | 0 0 | (0 0) (0 0)
3139 11:17:41.476236 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3140 11:17:41.479477 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3141 11:17:41.482751 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3142 11:17:41.489298 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3143 11:17:41.492801 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3144 11:17:41.496237 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3145 11:17:41.502870 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3146 11:17:41.506387 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3147 11:17:41.509275 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3148 11:17:41.516197 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 11:17:41.519706 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 11:17:41.522672 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 11:17:41.529411 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 11:17:41.532868 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 11:17:41.535852 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 11:17:41.542810 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 11:17:41.546477 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 11:17:41.549271 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 11:17:41.555945 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 11:17:41.559038 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 11:17:41.562588 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 11:17:41.569405 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 11:17:41.572232 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3162 11:17:41.575457 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3163 11:17:41.582579 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3164 11:17:41.583060 Total UI for P1: 0, mck2ui 16
3165 11:17:41.588996 best dqsien dly found for B0: ( 1, 3, 22)
3166 11:17:41.592020 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3167 11:17:41.595815 Total UI for P1: 0, mck2ui 16
3168 11:17:41.599129 best dqsien dly found for B1: ( 1, 3, 26)
3169 11:17:41.602186 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3170 11:17:41.605667 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3171 11:17:41.606224
3172 11:17:41.608658 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3173 11:17:41.611971 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3174 11:17:41.615838 [Gating] SW calibration Done
3175 11:17:41.616299 ==
3176 11:17:41.618836 Dram Type= 6, Freq= 0, CH_1, rank 0
3177 11:17:41.622258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3178 11:17:41.622682 ==
3179 11:17:41.625288 RX Vref Scan: 0
3180 11:17:41.625708
3181 11:17:41.628998 RX Vref 0 -> 0, step: 1
3182 11:17:41.629419
3183 11:17:41.629752 RX Delay -40 -> 252, step: 8
3184 11:17:41.635168 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3185 11:17:41.639190 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3186 11:17:41.642088 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3187 11:17:41.645851 iDelay=200, Bit 3, Center 123 (56 ~ 191) 136
3188 11:17:41.648937 iDelay=200, Bit 4, Center 115 (48 ~ 183) 136
3189 11:17:41.655218 iDelay=200, Bit 5, Center 127 (64 ~ 191) 128
3190 11:17:41.658815 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3191 11:17:41.661900 iDelay=200, Bit 7, Center 119 (56 ~ 183) 128
3192 11:17:41.665375 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3193 11:17:41.668661 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3194 11:17:41.675289 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3195 11:17:41.678360 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3196 11:17:41.681893 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3197 11:17:41.685373 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3198 11:17:41.688699 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3199 11:17:41.695084 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3200 11:17:41.695550 ==
3201 11:17:41.698601 Dram Type= 6, Freq= 0, CH_1, rank 0
3202 11:17:41.701840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3203 11:17:41.702256 ==
3204 11:17:41.702586 DQS Delay:
3205 11:17:41.705192 DQS0 = 0, DQS1 = 0
3206 11:17:41.705709 DQM Delay:
3207 11:17:41.708287 DQM0 = 120, DQM1 = 113
3208 11:17:41.708750 DQ Delay:
3209 11:17:41.711496 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =123
3210 11:17:41.715044 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =119
3211 11:17:41.717939 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3212 11:17:41.724432 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3213 11:17:41.724883
3214 11:17:41.725254
3215 11:17:41.725563 ==
3216 11:17:41.728330 Dram Type= 6, Freq= 0, CH_1, rank 0
3217 11:17:41.731173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3218 11:17:41.731590 ==
3219 11:17:41.731923
3220 11:17:41.732227
3221 11:17:41.734526 TX Vref Scan disable
3222 11:17:41.734984 == TX Byte 0 ==
3223 11:17:41.741339 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3224 11:17:41.744412 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3225 11:17:41.744889 == TX Byte 1 ==
3226 11:17:41.751246 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3227 11:17:41.754376 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3228 11:17:41.754793 ==
3229 11:17:41.757885 Dram Type= 6, Freq= 0, CH_1, rank 0
3230 11:17:41.761073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3231 11:17:41.761495 ==
3232 11:17:41.774133 TX Vref=22, minBit 11, minWin=23, winSum=396
3233 11:17:41.776925 TX Vref=24, minBit 10, minWin=24, winSum=408
3234 11:17:41.780812 TX Vref=26, minBit 11, minWin=24, winSum=410
3235 11:17:41.783749 TX Vref=28, minBit 9, minWin=25, winSum=415
3236 11:17:41.787181 TX Vref=30, minBit 10, minWin=24, winSum=417
3237 11:17:41.793920 TX Vref=32, minBit 10, minWin=25, winSum=419
3238 11:17:41.797032 [TxChooseVref] Worse bit 10, Min win 25, Win sum 419, Final Vref 32
3239 11:17:41.797455
3240 11:17:41.800600 Final TX Range 1 Vref 32
3241 11:17:41.801093
3242 11:17:41.801435 ==
3243 11:17:41.804116 Dram Type= 6, Freq= 0, CH_1, rank 0
3244 11:17:41.807661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3245 11:17:41.810311 ==
3246 11:17:41.810736
3247 11:17:41.811069
3248 11:17:41.811383 TX Vref Scan disable
3249 11:17:41.813952 == TX Byte 0 ==
3250 11:17:41.817237 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3251 11:17:41.824674 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3252 11:17:41.825351 == TX Byte 1 ==
3253 11:17:41.827329 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3254 11:17:41.834252 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3255 11:17:41.834683
3256 11:17:41.835020 [DATLAT]
3257 11:17:41.835335 Freq=1200, CH1 RK0
3258 11:17:41.835643
3259 11:17:41.837433 DATLAT Default: 0xd
3260 11:17:41.837922 0, 0xFFFF, sum = 0
3261 11:17:41.840667 1, 0xFFFF, sum = 0
3262 11:17:41.841181 2, 0xFFFF, sum = 0
3263 11:17:41.844252 3, 0xFFFF, sum = 0
3264 11:17:41.847299 4, 0xFFFF, sum = 0
3265 11:17:41.847732 5, 0xFFFF, sum = 0
3266 11:17:41.850629 6, 0xFFFF, sum = 0
3267 11:17:41.851060 7, 0xFFFF, sum = 0
3268 11:17:41.853917 8, 0xFFFF, sum = 0
3269 11:17:41.854348 9, 0xFFFF, sum = 0
3270 11:17:41.857175 10, 0xFFFF, sum = 0
3271 11:17:41.857685 11, 0xFFFF, sum = 0
3272 11:17:41.860502 12, 0x0, sum = 1
3273 11:17:41.861020 13, 0x0, sum = 2
3274 11:17:41.863544 14, 0x0, sum = 3
3275 11:17:41.863985 15, 0x0, sum = 4
3276 11:17:41.867120 best_step = 13
3277 11:17:41.867552
3278 11:17:41.867967 ==
3279 11:17:41.870603 Dram Type= 6, Freq= 0, CH_1, rank 0
3280 11:17:41.873797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3281 11:17:41.874217 ==
3282 11:17:41.874552 RX Vref Scan: 1
3283 11:17:41.877000
3284 11:17:41.877413 Set Vref Range= 32 -> 127
3285 11:17:41.877739
3286 11:17:41.880186 RX Vref 32 -> 127, step: 1
3287 11:17:41.880604
3288 11:17:41.883378 RX Delay -13 -> 252, step: 4
3289 11:17:41.883795
3290 11:17:41.887040 Set Vref, RX VrefLevel [Byte0]: 32
3291 11:17:41.890382 [Byte1]: 32
3292 11:17:41.890798
3293 11:17:41.893496 Set Vref, RX VrefLevel [Byte0]: 33
3294 11:17:41.896833 [Byte1]: 33
3295 11:17:41.900494
3296 11:17:41.900923 Set Vref, RX VrefLevel [Byte0]: 34
3297 11:17:41.903619 [Byte1]: 34
3298 11:17:41.908576
3299 11:17:41.909038 Set Vref, RX VrefLevel [Byte0]: 35
3300 11:17:41.911428 [Byte1]: 35
3301 11:17:41.916195
3302 11:17:41.916603 Set Vref, RX VrefLevel [Byte0]: 36
3303 11:17:41.919247 [Byte1]: 36
3304 11:17:41.924336
3305 11:17:41.924744 Set Vref, RX VrefLevel [Byte0]: 37
3306 11:17:41.927410 [Byte1]: 37
3307 11:17:41.932060
3308 11:17:41.932598 Set Vref, RX VrefLevel [Byte0]: 38
3309 11:17:41.935509 [Byte1]: 38
3310 11:17:41.940178
3311 11:17:41.940724 Set Vref, RX VrefLevel [Byte0]: 39
3312 11:17:41.943347 [Byte1]: 39
3313 11:17:41.948070
3314 11:17:41.948474 Set Vref, RX VrefLevel [Byte0]: 40
3315 11:17:41.951154 [Byte1]: 40
3316 11:17:41.955897
3317 11:17:41.956300 Set Vref, RX VrefLevel [Byte0]: 41
3318 11:17:41.958749 [Byte1]: 41
3319 11:17:41.963615
3320 11:17:41.964017 Set Vref, RX VrefLevel [Byte0]: 42
3321 11:17:41.966801 [Byte1]: 42
3322 11:17:41.971458
3323 11:17:41.971860 Set Vref, RX VrefLevel [Byte0]: 43
3324 11:17:41.974913 [Byte1]: 43
3325 11:17:41.979167
3326 11:17:41.979570 Set Vref, RX VrefLevel [Byte0]: 44
3327 11:17:41.982790 [Byte1]: 44
3328 11:17:41.987102
3329 11:17:41.987529 Set Vref, RX VrefLevel [Byte0]: 45
3330 11:17:41.990511 [Byte1]: 45
3331 11:17:41.995140
3332 11:17:41.995603 Set Vref, RX VrefLevel [Byte0]: 46
3333 11:17:41.998405 [Byte1]: 46
3334 11:17:42.002754
3335 11:17:42.003156 Set Vref, RX VrefLevel [Byte0]: 47
3336 11:17:42.006200 [Byte1]: 47
3337 11:17:42.010825
3338 11:17:42.011227 Set Vref, RX VrefLevel [Byte0]: 48
3339 11:17:42.014094 [Byte1]: 48
3340 11:17:42.018653
3341 11:17:42.019058 Set Vref, RX VrefLevel [Byte0]: 49
3342 11:17:42.022064 [Byte1]: 49
3343 11:17:42.026393
3344 11:17:42.026827 Set Vref, RX VrefLevel [Byte0]: 50
3345 11:17:42.030138 [Byte1]: 50
3346 11:17:42.035205
3347 11:17:42.035734 Set Vref, RX VrefLevel [Byte0]: 51
3348 11:17:42.038017 [Byte1]: 51
3349 11:17:42.042591
3350 11:17:42.043095 Set Vref, RX VrefLevel [Byte0]: 52
3351 11:17:42.045895 [Byte1]: 52
3352 11:17:42.050579
3353 11:17:42.051084 Set Vref, RX VrefLevel [Byte0]: 53
3354 11:17:42.053425 [Byte1]: 53
3355 11:17:42.058475
3356 11:17:42.061285 Set Vref, RX VrefLevel [Byte0]: 54
3357 11:17:42.064431 [Byte1]: 54
3358 11:17:42.064880
3359 11:17:42.067785 Set Vref, RX VrefLevel [Byte0]: 55
3360 11:17:42.071355 [Byte1]: 55
3361 11:17:42.071759
3362 11:17:42.074483 Set Vref, RX VrefLevel [Byte0]: 56
3363 11:17:42.077892 [Byte1]: 56
3364 11:17:42.081780
3365 11:17:42.082361 Set Vref, RX VrefLevel [Byte0]: 57
3366 11:17:42.085179 [Byte1]: 57
3367 11:17:42.089911
3368 11:17:42.090326 Set Vref, RX VrefLevel [Byte0]: 58
3369 11:17:42.092747 [Byte1]: 58
3370 11:17:42.097996
3371 11:17:42.098585 Set Vref, RX VrefLevel [Byte0]: 59
3372 11:17:42.101168 [Byte1]: 59
3373 11:17:42.105590
3374 11:17:42.106156 Set Vref, RX VrefLevel [Byte0]: 60
3375 11:17:42.108757 [Byte1]: 60
3376 11:17:42.113440
3377 11:17:42.113997 Set Vref, RX VrefLevel [Byte0]: 61
3378 11:17:42.116643 [Byte1]: 61
3379 11:17:42.121616
3380 11:17:42.122101 Set Vref, RX VrefLevel [Byte0]: 62
3381 11:17:42.124827 [Byte1]: 62
3382 11:17:42.129360
3383 11:17:42.129822 Set Vref, RX VrefLevel [Byte0]: 63
3384 11:17:42.132418 [Byte1]: 63
3385 11:17:42.137234
3386 11:17:42.137691 Set Vref, RX VrefLevel [Byte0]: 64
3387 11:17:42.140119 [Byte1]: 64
3388 11:17:42.145226
3389 11:17:42.145642 Set Vref, RX VrefLevel [Byte0]: 65
3390 11:17:42.148152 [Byte1]: 65
3391 11:17:42.153105
3392 11:17:42.153646 Set Vref, RX VrefLevel [Byte0]: 66
3393 11:17:42.156207 [Byte1]: 66
3394 11:17:42.160951
3395 11:17:42.161472 Set Vref, RX VrefLevel [Byte0]: 67
3396 11:17:42.163886 [Byte1]: 67
3397 11:17:42.168560
3398 11:17:42.169057 Final RX Vref Byte 0 = 51 to rank0
3399 11:17:42.171799 Final RX Vref Byte 1 = 52 to rank0
3400 11:17:42.175608 Final RX Vref Byte 0 = 51 to rank1
3401 11:17:42.178677 Final RX Vref Byte 1 = 52 to rank1==
3402 11:17:42.182069 Dram Type= 6, Freq= 0, CH_1, rank 0
3403 11:17:42.188583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3404 11:17:42.189057 ==
3405 11:17:42.189400 DQS Delay:
3406 11:17:42.189715 DQS0 = 0, DQS1 = 0
3407 11:17:42.191970 DQM Delay:
3408 11:17:42.192489 DQM0 = 119, DQM1 = 112
3409 11:17:42.195250 DQ Delay:
3410 11:17:42.198602 DQ0 =120, DQ1 =114, DQ2 =112, DQ3 =118
3411 11:17:42.201845 DQ4 =118, DQ5 =128, DQ6 =128, DQ7 =116
3412 11:17:42.205053 DQ8 =102, DQ9 =100, DQ10 =114, DQ11 =104
3413 11:17:42.208628 DQ12 =122, DQ13 =116, DQ14 =122, DQ15 =118
3414 11:17:42.209096
3415 11:17:42.209461
3416 11:17:42.218471 [DQSOSCAuto] RK0, (LSB)MR18= 0xff12, (MSB)MR19= 0x304, tDQSOscB0 = 403 ps tDQSOscB1 = 410 ps
3417 11:17:42.218904 CH1 RK0: MR19=304, MR18=FF12
3418 11:17:42.225354 CH1_RK0: MR19=0x304, MR18=0xFF12, DQSOSC=403, MR23=63, INC=40, DEC=26
3419 11:17:42.225783
3420 11:17:42.228457 ----->DramcWriteLeveling(PI) begin...
3421 11:17:42.228904 ==
3422 11:17:42.231702 Dram Type= 6, Freq= 0, CH_1, rank 1
3423 11:17:42.235219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3424 11:17:42.238632 ==
3425 11:17:42.239063 Write leveling (Byte 0): 26 => 26
3426 11:17:42.241850 Write leveling (Byte 1): 29 => 29
3427 11:17:42.245042 DramcWriteLeveling(PI) end<-----
3428 11:17:42.245515
3429 11:17:42.245947 ==
3430 11:17:42.248468 Dram Type= 6, Freq= 0, CH_1, rank 1
3431 11:17:42.255087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3432 11:17:42.255508 ==
3433 11:17:42.258563 [Gating] SW mode calibration
3434 11:17:42.265212 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3435 11:17:42.268875 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3436 11:17:42.274791 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3437 11:17:42.278230 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3438 11:17:42.281875 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3439 11:17:42.285029 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3440 11:17:42.291548 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3441 11:17:42.294803 0 15 20 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3442 11:17:42.298289 0 15 24 | B1->B0 | 2b2b 3434 | 0 0 | (1 0) (0 1)
3443 11:17:42.304714 0 15 28 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
3444 11:17:42.307982 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3445 11:17:42.311039 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3446 11:17:42.318201 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3447 11:17:42.321714 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3448 11:17:42.324541 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3449 11:17:42.331512 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3450 11:17:42.334769 1 0 24 | B1->B0 | 3737 2525 | 0 0 | (1 1) (0 0)
3451 11:17:42.338355 1 0 28 | B1->B0 | 4646 4040 | 0 0 | (0 0) (0 0)
3452 11:17:42.344901 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3453 11:17:42.348038 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3454 11:17:42.351532 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3455 11:17:42.357855 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3456 11:17:42.361215 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3457 11:17:42.364659 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3458 11:17:42.370963 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3459 11:17:42.374402 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3460 11:17:42.377563 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 11:17:42.384345 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 11:17:42.387558 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 11:17:42.390816 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 11:17:42.397365 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 11:17:42.400611 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 11:17:42.404045 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 11:17:42.411085 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 11:17:42.413850 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 11:17:42.417350 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 11:17:42.423945 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 11:17:42.427201 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 11:17:42.430632 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 11:17:42.437268 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3474 11:17:42.440234 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3475 11:17:42.443725 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3476 11:17:42.450026 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3477 11:17:42.450181 Total UI for P1: 0, mck2ui 16
3478 11:17:42.456959 best dqsien dly found for B0: ( 1, 3, 24)
3479 11:17:42.457115 Total UI for P1: 0, mck2ui 16
3480 11:17:42.463451 best dqsien dly found for B1: ( 1, 3, 26)
3481 11:17:42.466813 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3482 11:17:42.470418 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3483 11:17:42.470622
3484 11:17:42.473698 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3485 11:17:42.477023 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3486 11:17:42.480250 [Gating] SW calibration Done
3487 11:17:42.480552 ==
3488 11:17:42.484115 Dram Type= 6, Freq= 0, CH_1, rank 1
3489 11:17:42.487268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3490 11:17:42.487787 ==
3491 11:17:42.490602 RX Vref Scan: 0
3492 11:17:42.491119
3493 11:17:42.491459 RX Vref 0 -> 0, step: 1
3494 11:17:42.491778
3495 11:17:42.493659 RX Delay -40 -> 252, step: 8
3496 11:17:42.496991 iDelay=200, Bit 0, Center 123 (64 ~ 183) 120
3497 11:17:42.503550 iDelay=200, Bit 1, Center 111 (48 ~ 175) 128
3498 11:17:42.507647 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3499 11:17:42.510324 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3500 11:17:42.513661 iDelay=200, Bit 4, Center 123 (56 ~ 191) 136
3501 11:17:42.516751 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3502 11:17:42.523486 iDelay=200, Bit 6, Center 127 (64 ~ 191) 128
3503 11:17:42.526799 iDelay=200, Bit 7, Center 115 (48 ~ 183) 136
3504 11:17:42.530457 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3505 11:17:42.533651 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3506 11:17:42.536903 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3507 11:17:42.543179 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3508 11:17:42.546432 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3509 11:17:42.549824 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3510 11:17:42.553132 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3511 11:17:42.559436 iDelay=200, Bit 15, Center 123 (48 ~ 199) 152
3512 11:17:42.559922 ==
3513 11:17:42.563017 Dram Type= 6, Freq= 0, CH_1, rank 1
3514 11:17:42.566016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3515 11:17:42.566486 ==
3516 11:17:42.566857 DQS Delay:
3517 11:17:42.569867 DQS0 = 0, DQS1 = 0
3518 11:17:42.570479 DQM Delay:
3519 11:17:42.572722 DQM0 = 120, DQM1 = 112
3520 11:17:42.573338 DQ Delay:
3521 11:17:42.576073 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =119
3522 11:17:42.579294 DQ4 =123, DQ5 =131, DQ6 =127, DQ7 =115
3523 11:17:42.583008 DQ8 =99, DQ9 =99, DQ10 =115, DQ11 =107
3524 11:17:42.586215 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =123
3525 11:17:42.586780
3526 11:17:42.587157
3527 11:17:42.589299 ==
3528 11:17:42.592605 Dram Type= 6, Freq= 0, CH_1, rank 1
3529 11:17:42.596064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3530 11:17:42.596633 ==
3531 11:17:42.597062
3532 11:17:42.597417
3533 11:17:42.599282 TX Vref Scan disable
3534 11:17:42.599751 == TX Byte 0 ==
3535 11:17:42.602497 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3536 11:17:42.609215 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3537 11:17:42.609690 == TX Byte 1 ==
3538 11:17:42.615503 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3539 11:17:42.618892 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3540 11:17:42.619456 ==
3541 11:17:42.622339 Dram Type= 6, Freq= 0, CH_1, rank 1
3542 11:17:42.625910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3543 11:17:42.626474 ==
3544 11:17:42.637882 TX Vref=22, minBit 0, minWin=25, winSum=412
3545 11:17:42.641351 TX Vref=24, minBit 1, minWin=25, winSum=416
3546 11:17:42.644619 TX Vref=26, minBit 3, minWin=25, winSum=419
3547 11:17:42.647755 TX Vref=28, minBit 0, minWin=26, winSum=427
3548 11:17:42.650986 TX Vref=30, minBit 9, minWin=25, winSum=424
3549 11:17:42.657912 TX Vref=32, minBit 9, minWin=25, winSum=427
3550 11:17:42.660938 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 28
3551 11:17:42.661417
3552 11:17:42.664301 Final TX Range 1 Vref 28
3553 11:17:42.664896
3554 11:17:42.665277 ==
3555 11:17:42.667495 Dram Type= 6, Freq= 0, CH_1, rank 1
3556 11:17:42.670649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3557 11:17:42.673851 ==
3558 11:17:42.674317
3559 11:17:42.674686
3560 11:17:42.675030 TX Vref Scan disable
3561 11:17:42.677659 == TX Byte 0 ==
3562 11:17:42.681135 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3563 11:17:42.687477 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3564 11:17:42.688043 == TX Byte 1 ==
3565 11:17:42.690943 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3566 11:17:42.697218 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3567 11:17:42.697780
3568 11:17:42.698153 [DATLAT]
3569 11:17:42.698499 Freq=1200, CH1 RK1
3570 11:17:42.698838
3571 11:17:42.700577 DATLAT Default: 0xd
3572 11:17:42.703784 0, 0xFFFF, sum = 0
3573 11:17:42.704264 1, 0xFFFF, sum = 0
3574 11:17:42.707346 2, 0xFFFF, sum = 0
3575 11:17:42.707917 3, 0xFFFF, sum = 0
3576 11:17:42.710390 4, 0xFFFF, sum = 0
3577 11:17:42.710865 5, 0xFFFF, sum = 0
3578 11:17:42.713849 6, 0xFFFF, sum = 0
3579 11:17:42.714415 7, 0xFFFF, sum = 0
3580 11:17:42.717444 8, 0xFFFF, sum = 0
3581 11:17:42.717920 9, 0xFFFF, sum = 0
3582 11:17:42.720757 10, 0xFFFF, sum = 0
3583 11:17:42.721360 11, 0xFFFF, sum = 0
3584 11:17:42.723674 12, 0x0, sum = 1
3585 11:17:42.724246 13, 0x0, sum = 2
3586 11:17:42.726652 14, 0x0, sum = 3
3587 11:17:42.727126 15, 0x0, sum = 4
3588 11:17:42.730229 best_step = 13
3589 11:17:42.730793
3590 11:17:42.731166 ==
3591 11:17:42.733221 Dram Type= 6, Freq= 0, CH_1, rank 1
3592 11:17:42.736963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3593 11:17:42.737527 ==
3594 11:17:42.739776 RX Vref Scan: 0
3595 11:17:42.740266
3596 11:17:42.740635 RX Vref 0 -> 0, step: 1
3597 11:17:42.741028
3598 11:17:42.743360 RX Delay -13 -> 252, step: 4
3599 11:17:42.749755 iDelay=195, Bit 0, Center 122 (63 ~ 182) 120
3600 11:17:42.753664 iDelay=195, Bit 1, Center 114 (55 ~ 174) 120
3601 11:17:42.756867 iDelay=195, Bit 2, Center 108 (51 ~ 166) 116
3602 11:17:42.760010 iDelay=195, Bit 3, Center 116 (55 ~ 178) 124
3603 11:17:42.763260 iDelay=195, Bit 4, Center 120 (59 ~ 182) 124
3604 11:17:42.769421 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3605 11:17:42.773108 iDelay=195, Bit 6, Center 126 (67 ~ 186) 120
3606 11:17:42.776240 iDelay=195, Bit 7, Center 116 (55 ~ 178) 124
3607 11:17:42.779452 iDelay=195, Bit 8, Center 100 (39 ~ 162) 124
3608 11:17:42.782999 iDelay=195, Bit 9, Center 102 (39 ~ 166) 128
3609 11:17:42.789494 iDelay=195, Bit 10, Center 114 (51 ~ 178) 128
3610 11:17:42.793192 iDelay=195, Bit 11, Center 108 (43 ~ 174) 132
3611 11:17:42.796020 iDelay=195, Bit 12, Center 122 (59 ~ 186) 128
3612 11:17:42.799849 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3613 11:17:42.806207 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3614 11:17:42.809318 iDelay=195, Bit 15, Center 124 (59 ~ 190) 132
3615 11:17:42.809882 ==
3616 11:17:42.812564 Dram Type= 6, Freq= 0, CH_1, rank 1
3617 11:17:42.816095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3618 11:17:42.816660 ==
3619 11:17:42.819383 DQS Delay:
3620 11:17:42.819944 DQS0 = 0, DQS1 = 0
3621 11:17:42.820319 DQM Delay:
3622 11:17:42.822468 DQM0 = 119, DQM1 = 113
3623 11:17:42.823031 DQ Delay:
3624 11:17:42.825730 DQ0 =122, DQ1 =114, DQ2 =108, DQ3 =116
3625 11:17:42.828791 DQ4 =120, DQ5 =130, DQ6 =126, DQ7 =116
3626 11:17:42.836314 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =108
3627 11:17:42.838974 DQ12 =122, DQ13 =118, DQ14 =122, DQ15 =124
3628 11:17:42.839530
3629 11:17:42.839912
3630 11:17:42.845927 [DQSOSCAuto] RK1, (LSB)MR18= 0xaee, (MSB)MR19= 0x403, tDQSOscB0 = 417 ps tDQSOscB1 = 406 ps
3631 11:17:42.849104 CH1 RK1: MR19=403, MR18=AEE
3632 11:17:42.855477 CH1_RK1: MR19=0x403, MR18=0xAEE, DQSOSC=406, MR23=63, INC=39, DEC=26
3633 11:17:42.858729 [RxdqsGatingPostProcess] freq 1200
3634 11:17:42.861803 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3635 11:17:42.865172 best DQS0 dly(2T, 0.5T) = (0, 11)
3636 11:17:42.868933 best DQS1 dly(2T, 0.5T) = (0, 11)
3637 11:17:42.871737 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3638 11:17:42.875080 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3639 11:17:42.878220 best DQS0 dly(2T, 0.5T) = (0, 11)
3640 11:17:42.881706 best DQS1 dly(2T, 0.5T) = (0, 11)
3641 11:17:42.884889 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3642 11:17:42.888634 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3643 11:17:42.891716 Pre-setting of DQS Precalculation
3644 11:17:42.894872 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3645 11:17:42.904984 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3646 11:17:42.911791 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3647 11:17:42.912358
3648 11:17:42.912734
3649 11:17:42.914728 [Calibration Summary] 2400 Mbps
3650 11:17:42.915197 CH 0, Rank 0
3651 11:17:42.918416 SW Impedance : PASS
3652 11:17:42.921212 DUTY Scan : NO K
3653 11:17:42.921683 ZQ Calibration : PASS
3654 11:17:42.924344 Jitter Meter : NO K
3655 11:17:42.928260 CBT Training : PASS
3656 11:17:42.928886 Write leveling : PASS
3657 11:17:42.931340 RX DQS gating : PASS
3658 11:17:42.931898 RX DQ/DQS(RDDQC) : PASS
3659 11:17:42.934594 TX DQ/DQS : PASS
3660 11:17:42.938078 RX DATLAT : PASS
3661 11:17:42.938635 RX DQ/DQS(Engine): PASS
3662 11:17:42.941168 TX OE : NO K
3663 11:17:42.941636 All Pass.
3664 11:17:42.942004
3665 11:17:42.944126 CH 0, Rank 1
3666 11:17:42.944590 SW Impedance : PASS
3667 11:17:42.947476 DUTY Scan : NO K
3668 11:17:42.951179 ZQ Calibration : PASS
3669 11:17:42.951749 Jitter Meter : NO K
3670 11:17:42.954247 CBT Training : PASS
3671 11:17:42.957641 Write leveling : PASS
3672 11:17:42.958204 RX DQS gating : PASS
3673 11:17:42.960666 RX DQ/DQS(RDDQC) : PASS
3674 11:17:42.964045 TX DQ/DQS : PASS
3675 11:17:42.964614 RX DATLAT : PASS
3676 11:17:42.967607 RX DQ/DQS(Engine): PASS
3677 11:17:42.970501 TX OE : NO K
3678 11:17:42.970973 All Pass.
3679 11:17:42.971345
3680 11:17:42.971688 CH 1, Rank 0
3681 11:17:42.973845 SW Impedance : PASS
3682 11:17:42.977425 DUTY Scan : NO K
3683 11:17:42.977979 ZQ Calibration : PASS
3684 11:17:42.980356 Jitter Meter : NO K
3685 11:17:42.983773 CBT Training : PASS
3686 11:17:42.984331 Write leveling : PASS
3687 11:17:42.986969 RX DQS gating : PASS
3688 11:17:42.990311 RX DQ/DQS(RDDQC) : PASS
3689 11:17:42.990777 TX DQ/DQS : PASS
3690 11:17:42.993392 RX DATLAT : PASS
3691 11:17:42.996915 RX DQ/DQS(Engine): PASS
3692 11:17:42.997479 TX OE : NO K
3693 11:17:43.000123 All Pass.
3694 11:17:43.000680
3695 11:17:43.001089 CH 1, Rank 1
3696 11:17:43.003496 SW Impedance : PASS
3697 11:17:43.003982 DUTY Scan : NO K
3698 11:17:43.007150 ZQ Calibration : PASS
3699 11:17:43.010000 Jitter Meter : NO K
3700 11:17:43.010519 CBT Training : PASS
3701 11:17:43.013568 Write leveling : PASS
3702 11:17:43.016538 RX DQS gating : PASS
3703 11:17:43.017139 RX DQ/DQS(RDDQC) : PASS
3704 11:17:43.020302 TX DQ/DQS : PASS
3705 11:17:43.020895 RX DATLAT : PASS
3706 11:17:43.023339 RX DQ/DQS(Engine): PASS
3707 11:17:43.026700 TX OE : NO K
3708 11:17:43.027262 All Pass.
3709 11:17:43.027632
3710 11:17:43.030260 DramC Write-DBI off
3711 11:17:43.033376 PER_BANK_REFRESH: Hybrid Mode
3712 11:17:43.033933 TX_TRACKING: ON
3713 11:17:43.043184 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3714 11:17:43.046222 [FAST_K] Save calibration result to emmc
3715 11:17:43.049581 dramc_set_vcore_voltage set vcore to 650000
3716 11:17:43.053192 Read voltage for 600, 5
3717 11:17:43.053757 Vio18 = 0
3718 11:17:43.054133 Vcore = 650000
3719 11:17:43.056293 Vdram = 0
3720 11:17:43.056909 Vddq = 0
3721 11:17:43.057294 Vmddr = 0
3722 11:17:43.062928 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3723 11:17:43.066829 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3724 11:17:43.069780 MEM_TYPE=3, freq_sel=19
3725 11:17:43.073177 sv_algorithm_assistance_LP4_1600
3726 11:17:43.075980 ============ PULL DRAM RESETB DOWN ============
3727 11:17:43.079117 ========== PULL DRAM RESETB DOWN end =========
3728 11:17:43.086164 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3729 11:17:43.089547 ===================================
3730 11:17:43.090015 LPDDR4 DRAM CONFIGURATION
3731 11:17:43.092555 ===================================
3732 11:17:43.096086 EX_ROW_EN[0] = 0x0
3733 11:17:43.099496 EX_ROW_EN[1] = 0x0
3734 11:17:43.100068 LP4Y_EN = 0x0
3735 11:17:43.102487 WORK_FSP = 0x0
3736 11:17:43.103049 WL = 0x2
3737 11:17:43.105662 RL = 0x2
3738 11:17:43.106135 BL = 0x2
3739 11:17:43.108863 RPST = 0x0
3740 11:17:43.109328 RD_PRE = 0x0
3741 11:17:43.112233 WR_PRE = 0x1
3742 11:17:43.112695 WR_PST = 0x0
3743 11:17:43.115429 DBI_WR = 0x0
3744 11:17:43.115890 DBI_RD = 0x0
3745 11:17:43.119113 OTF = 0x1
3746 11:17:43.122048 ===================================
3747 11:17:43.125586 ===================================
3748 11:17:43.126118 ANA top config
3749 11:17:43.128956 ===================================
3750 11:17:43.132363 DLL_ASYNC_EN = 0
3751 11:17:43.135781 ALL_SLAVE_EN = 1
3752 11:17:43.138778 NEW_RANK_MODE = 1
3753 11:17:43.139342 DLL_IDLE_MODE = 1
3754 11:17:43.142026 LP45_APHY_COMB_EN = 1
3755 11:17:43.145488 TX_ODT_DIS = 1
3756 11:17:43.148700 NEW_8X_MODE = 1
3757 11:17:43.152577 ===================================
3758 11:17:43.155310 ===================================
3759 11:17:43.159199 data_rate = 1200
3760 11:17:43.159759 CKR = 1
3761 11:17:43.161855 DQ_P2S_RATIO = 8
3762 11:17:43.165656 ===================================
3763 11:17:43.168692 CA_P2S_RATIO = 8
3764 11:17:43.172012 DQ_CA_OPEN = 0
3765 11:17:43.175316 DQ_SEMI_OPEN = 0
3766 11:17:43.178753 CA_SEMI_OPEN = 0
3767 11:17:43.179217 CA_FULL_RATE = 0
3768 11:17:43.181743 DQ_CKDIV4_EN = 1
3769 11:17:43.184875 CA_CKDIV4_EN = 1
3770 11:17:43.188713 CA_PREDIV_EN = 0
3771 11:17:43.192109 PH8_DLY = 0
3772 11:17:43.195003 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3773 11:17:43.195469 DQ_AAMCK_DIV = 4
3774 11:17:43.198482 CA_AAMCK_DIV = 4
3775 11:17:43.201398 CA_ADMCK_DIV = 4
3776 11:17:43.205029 DQ_TRACK_CA_EN = 0
3777 11:17:43.208421 CA_PICK = 600
3778 11:17:43.211556 CA_MCKIO = 600
3779 11:17:43.215220 MCKIO_SEMI = 0
3780 11:17:43.215796 PLL_FREQ = 2288
3781 11:17:43.218208 DQ_UI_PI_RATIO = 32
3782 11:17:43.221750 CA_UI_PI_RATIO = 0
3783 11:17:43.224713 ===================================
3784 11:17:43.227967 ===================================
3785 11:17:43.231281 memory_type:LPDDR4
3786 11:17:43.234910 GP_NUM : 10
3787 11:17:43.235470 SRAM_EN : 1
3788 11:17:43.238581 MD32_EN : 0
3789 11:17:43.241388 ===================================
3790 11:17:43.241856 [ANA_INIT] >>>>>>>>>>>>>>
3791 11:17:43.244889 <<<<<< [CONFIGURE PHASE]: ANA_TX
3792 11:17:43.248178 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3793 11:17:43.252200 ===================================
3794 11:17:43.254812 data_rate = 1200,PCW = 0X5800
3795 11:17:43.258210 ===================================
3796 11:17:43.261542 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3797 11:17:43.268090 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3798 11:17:43.274239 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3799 11:17:43.277660 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3800 11:17:43.280943 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3801 11:17:43.284898 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3802 11:17:43.287987 [ANA_INIT] flow start
3803 11:17:43.288545 [ANA_INIT] PLL >>>>>>>>
3804 11:17:43.291388 [ANA_INIT] PLL <<<<<<<<
3805 11:17:43.294321 [ANA_INIT] MIDPI >>>>>>>>
3806 11:17:43.294883 [ANA_INIT] MIDPI <<<<<<<<
3807 11:17:43.298209 [ANA_INIT] DLL >>>>>>>>
3808 11:17:43.301038 [ANA_INIT] flow end
3809 11:17:43.304325 ============ LP4 DIFF to SE enter ============
3810 11:17:43.307649 ============ LP4 DIFF to SE exit ============
3811 11:17:43.311501 [ANA_INIT] <<<<<<<<<<<<<
3812 11:17:43.314109 [Flow] Enable top DCM control >>>>>
3813 11:17:43.317738 [Flow] Enable top DCM control <<<<<
3814 11:17:43.321145 Enable DLL master slave shuffle
3815 11:17:43.324076 ==============================================================
3816 11:17:43.327258 Gating Mode config
3817 11:17:43.334299 ==============================================================
3818 11:17:43.334851 Config description:
3819 11:17:43.344145 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3820 11:17:43.351048 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3821 11:17:43.357322 SELPH_MODE 0: By rank 1: By Phase
3822 11:17:43.360247 ==============================================================
3823 11:17:43.363904 GAT_TRACK_EN = 1
3824 11:17:43.367324 RX_GATING_MODE = 2
3825 11:17:43.370321 RX_GATING_TRACK_MODE = 2
3826 11:17:43.373605 SELPH_MODE = 1
3827 11:17:43.376892 PICG_EARLY_EN = 1
3828 11:17:43.380120 VALID_LAT_VALUE = 1
3829 11:17:43.383600 ==============================================================
3830 11:17:43.386726 Enter into Gating configuration >>>>
3831 11:17:43.390471 Exit from Gating configuration <<<<
3832 11:17:43.393110 Enter into DVFS_PRE_config >>>>>
3833 11:17:43.406392 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3834 11:17:43.410226 Exit from DVFS_PRE_config <<<<<
3835 11:17:43.412882 Enter into PICG configuration >>>>
3836 11:17:43.416597 Exit from PICG configuration <<<<
3837 11:17:43.417245 [RX_INPUT] configuration >>>>>
3838 11:17:43.419605 [RX_INPUT] configuration <<<<<
3839 11:17:43.426425 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3840 11:17:43.432809 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3841 11:17:43.436213 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3842 11:17:43.442316 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3843 11:17:43.449116 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3844 11:17:43.456436 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3845 11:17:43.459171 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3846 11:17:43.462476 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3847 11:17:43.469306 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3848 11:17:43.472169 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3849 11:17:43.475675 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3850 11:17:43.482523 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3851 11:17:43.486256 ===================================
3852 11:17:43.486839 LPDDR4 DRAM CONFIGURATION
3853 11:17:43.488874 ===================================
3854 11:17:43.492170 EX_ROW_EN[0] = 0x0
3855 11:17:43.492638 EX_ROW_EN[1] = 0x0
3856 11:17:43.495666 LP4Y_EN = 0x0
3857 11:17:43.498717 WORK_FSP = 0x0
3858 11:17:43.499190 WL = 0x2
3859 11:17:43.501982 RL = 0x2
3860 11:17:43.502451 BL = 0x2
3861 11:17:43.505423 RPST = 0x0
3862 11:17:43.505894 RD_PRE = 0x0
3863 11:17:43.508937 WR_PRE = 0x1
3864 11:17:43.509509 WR_PST = 0x0
3865 11:17:43.512325 DBI_WR = 0x0
3866 11:17:43.513072 DBI_RD = 0x0
3867 11:17:43.515376 OTF = 0x1
3868 11:17:43.518856 ===================================
3869 11:17:43.522422 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3870 11:17:43.525290 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3871 11:17:43.531853 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3872 11:17:43.535020 ===================================
3873 11:17:43.535496 LPDDR4 DRAM CONFIGURATION
3874 11:17:43.538705 ===================================
3875 11:17:43.541847 EX_ROW_EN[0] = 0x10
3876 11:17:43.542425 EX_ROW_EN[1] = 0x0
3877 11:17:43.545149 LP4Y_EN = 0x0
3878 11:17:43.548183 WORK_FSP = 0x0
3879 11:17:43.548663 WL = 0x2
3880 11:17:43.551752 RL = 0x2
3881 11:17:43.552314 BL = 0x2
3882 11:17:43.554820 RPST = 0x0
3883 11:17:43.555281 RD_PRE = 0x0
3884 11:17:43.558215 WR_PRE = 0x1
3885 11:17:43.558678 WR_PST = 0x0
3886 11:17:43.561479 DBI_WR = 0x0
3887 11:17:43.562042 DBI_RD = 0x0
3888 11:17:43.564704 OTF = 0x1
3889 11:17:43.568166 ===================================
3890 11:17:43.574449 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3891 11:17:43.578031 nWR fixed to 30
3892 11:17:43.578513 [ModeRegInit_LP4] CH0 RK0
3893 11:17:43.581141 [ModeRegInit_LP4] CH0 RK1
3894 11:17:43.585067 [ModeRegInit_LP4] CH1 RK0
3895 11:17:43.588088 [ModeRegInit_LP4] CH1 RK1
3896 11:17:43.588667 match AC timing 17
3897 11:17:43.591288 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3898 11:17:43.598144 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3899 11:17:43.601286 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3900 11:17:43.607931 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3901 11:17:43.611049 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3902 11:17:43.611612 ==
3903 11:17:43.614232 Dram Type= 6, Freq= 0, CH_0, rank 0
3904 11:17:43.617426 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3905 11:17:43.617895 ==
3906 11:17:43.624407 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3907 11:17:43.631094 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3908 11:17:43.633912 [CA 0] Center 36 (6~67) winsize 62
3909 11:17:43.637887 [CA 1] Center 36 (6~67) winsize 62
3910 11:17:43.641039 [CA 2] Center 34 (4~65) winsize 62
3911 11:17:43.644497 [CA 3] Center 34 (3~65) winsize 63
3912 11:17:43.647260 [CA 4] Center 34 (3~65) winsize 63
3913 11:17:43.650662 [CA 5] Center 33 (2~64) winsize 63
3914 11:17:43.651225
3915 11:17:43.653774 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3916 11:17:43.654239
3917 11:17:43.657311 [CATrainingPosCal] consider 1 rank data
3918 11:17:43.660589 u2DelayCellTimex100 = 270/100 ps
3919 11:17:43.663761 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3920 11:17:43.667175 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3921 11:17:43.670588 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3922 11:17:43.673955 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
3923 11:17:43.677091 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3924 11:17:43.683672 CA5 delay=33 (2~64),Diff = 0 PI (0 cell)
3925 11:17:43.684231
3926 11:17:43.686797 CA PerBit enable=1, Macro0, CA PI delay=33
3927 11:17:43.687262
3928 11:17:43.690332 [CBTSetCACLKResult] CA Dly = 33
3929 11:17:43.690794 CS Dly: 5 (0~36)
3930 11:17:43.691162 ==
3931 11:17:43.693539 Dram Type= 6, Freq= 0, CH_0, rank 1
3932 11:17:43.696794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3933 11:17:43.700360 ==
3934 11:17:43.703354 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3935 11:17:43.709991 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3936 11:17:43.713082 [CA 0] Center 36 (6~67) winsize 62
3937 11:17:43.716944 [CA 1] Center 36 (6~67) winsize 62
3938 11:17:43.720329 [CA 2] Center 35 (5~66) winsize 62
3939 11:17:43.723362 [CA 3] Center 34 (4~65) winsize 62
3940 11:17:43.726512 [CA 4] Center 34 (3~65) winsize 63
3941 11:17:43.729528 [CA 5] Center 33 (3~64) winsize 62
3942 11:17:43.729993
3943 11:17:43.732933 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3944 11:17:43.733488
3945 11:17:43.736225 [CATrainingPosCal] consider 2 rank data
3946 11:17:43.739862 u2DelayCellTimex100 = 270/100 ps
3947 11:17:43.742694 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3948 11:17:43.745981 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3949 11:17:43.753037 CA2 delay=35 (5~65),Diff = 2 PI (19 cell)
3950 11:17:43.756152 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3951 11:17:43.759540 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
3952 11:17:43.762961 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3953 11:17:43.763520
3954 11:17:43.766461 CA PerBit enable=1, Macro0, CA PI delay=33
3955 11:17:43.766925
3956 11:17:43.769140 [CBTSetCACLKResult] CA Dly = 33
3957 11:17:43.769605 CS Dly: 5 (0~37)
3958 11:17:43.769976
3959 11:17:43.772568 ----->DramcWriteLeveling(PI) begin...
3960 11:17:43.775691 ==
3961 11:17:43.779128 Dram Type= 6, Freq= 0, CH_0, rank 0
3962 11:17:43.782859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3963 11:17:43.783421 ==
3964 11:17:43.786155 Write leveling (Byte 0): 35 => 35
3965 11:17:43.789197 Write leveling (Byte 1): 30 => 30
3966 11:17:43.792696 DramcWriteLeveling(PI) end<-----
3967 11:17:43.793301
3968 11:17:43.793675 ==
3969 11:17:43.795987 Dram Type= 6, Freq= 0, CH_0, rank 0
3970 11:17:43.799245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3971 11:17:43.799814 ==
3972 11:17:43.802391 [Gating] SW mode calibration
3973 11:17:43.809029 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3974 11:17:43.815531 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3975 11:17:43.818639 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3976 11:17:43.822437 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3977 11:17:43.828873 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3978 11:17:43.832106 0 9 12 | B1->B0 | 3434 2c2c | 0 0 | (0 0) (0 0)
3979 11:17:43.834899 0 9 16 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
3980 11:17:43.841720 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3981 11:17:43.845294 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3982 11:17:43.848613 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 11:17:43.855272 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3984 11:17:43.858624 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3985 11:17:43.861630 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3986 11:17:43.868404 0 10 12 | B1->B0 | 2c2c 4040 | 0 0 | (0 0) (0 0)
3987 11:17:43.871453 0 10 16 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
3988 11:17:43.874774 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3989 11:17:43.881264 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3990 11:17:43.884855 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 11:17:43.888181 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 11:17:43.894900 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3993 11:17:43.898099 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3994 11:17:43.901668 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3995 11:17:43.908305 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3996 11:17:43.911344 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 11:17:43.914580 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 11:17:43.918032 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 11:17:43.924523 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 11:17:43.927999 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 11:17:43.931456 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 11:17:43.938167 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 11:17:43.941332 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 11:17:43.944486 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 11:17:43.951168 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 11:17:43.954593 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 11:17:43.957690 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 11:17:43.964082 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 11:17:43.967677 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 11:17:43.970983 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4011 11:17:43.977681 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4012 11:17:43.980929 Total UI for P1: 0, mck2ui 16
4013 11:17:43.984025 best dqsien dly found for B0: ( 0, 13, 12)
4014 11:17:43.987371 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4015 11:17:43.990454 Total UI for P1: 0, mck2ui 16
4016 11:17:43.993966 best dqsien dly found for B1: ( 0, 13, 16)
4017 11:17:43.997417 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4018 11:17:44.000573 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4019 11:17:44.001165
4020 11:17:44.004273 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4021 11:17:44.010497 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4022 11:17:44.011059 [Gating] SW calibration Done
4023 11:17:44.011432 ==
4024 11:17:44.013451 Dram Type= 6, Freq= 0, CH_0, rank 0
4025 11:17:44.020844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4026 11:17:44.021406 ==
4027 11:17:44.021779 RX Vref Scan: 0
4028 11:17:44.022120
4029 11:17:44.023903 RX Vref 0 -> 0, step: 1
4030 11:17:44.024473
4031 11:17:44.026944 RX Delay -230 -> 252, step: 16
4032 11:17:44.030419 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4033 11:17:44.033718 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4034 11:17:44.040655 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4035 11:17:44.043556 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4036 11:17:44.046770 iDelay=218, Bit 4, Center 57 (-102 ~ 217) 320
4037 11:17:44.050357 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4038 11:17:44.053657 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4039 11:17:44.060088 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4040 11:17:44.063373 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4041 11:17:44.067008 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4042 11:17:44.070192 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4043 11:17:44.076662 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4044 11:17:44.080029 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4045 11:17:44.083660 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4046 11:17:44.086841 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4047 11:17:44.093554 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4048 11:17:44.094126 ==
4049 11:17:44.096531 Dram Type= 6, Freq= 0, CH_0, rank 0
4050 11:17:44.099600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4051 11:17:44.100068 ==
4052 11:17:44.100434 DQS Delay:
4053 11:17:44.103173 DQS0 = 0, DQS1 = 0
4054 11:17:44.103731 DQM Delay:
4055 11:17:44.106499 DQM0 = 51, DQM1 = 39
4056 11:17:44.107127 DQ Delay:
4057 11:17:44.109435 DQ0 =49, DQ1 =57, DQ2 =49, DQ3 =41
4058 11:17:44.113120 DQ4 =57, DQ5 =41, DQ6 =57, DQ7 =57
4059 11:17:44.116249 DQ8 =33, DQ9 =25, DQ10 =41, DQ11 =33
4060 11:17:44.119245 DQ12 =41, DQ13 =41, DQ14 =57, DQ15 =41
4061 11:17:44.119769
4062 11:17:44.120138
4063 11:17:44.120479 ==
4064 11:17:44.122994 Dram Type= 6, Freq= 0, CH_0, rank 0
4065 11:17:44.125833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4066 11:17:44.129261 ==
4067 11:17:44.129722
4068 11:17:44.130086
4069 11:17:44.130425 TX Vref Scan disable
4070 11:17:44.132885 == TX Byte 0 ==
4071 11:17:44.136111 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4072 11:17:44.139367 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4073 11:17:44.142442 == TX Byte 1 ==
4074 11:17:44.145565 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4075 11:17:44.152736 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4076 11:17:44.153331 ==
4077 11:17:44.156124 Dram Type= 6, Freq= 0, CH_0, rank 0
4078 11:17:44.159585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4079 11:17:44.160150 ==
4080 11:17:44.160520
4081 11:17:44.160938
4082 11:17:44.162665 TX Vref Scan disable
4083 11:17:44.165556 == TX Byte 0 ==
4084 11:17:44.169013 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4085 11:17:44.172512 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4086 11:17:44.175356 == TX Byte 1 ==
4087 11:17:44.179084 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4088 11:17:44.182097 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4089 11:17:44.182765
4090 11:17:44.185256 [DATLAT]
4091 11:17:44.185717 Freq=600, CH0 RK0
4092 11:17:44.186085
4093 11:17:44.188842 DATLAT Default: 0x9
4094 11:17:44.189404 0, 0xFFFF, sum = 0
4095 11:17:44.191876 1, 0xFFFF, sum = 0
4096 11:17:44.192348 2, 0xFFFF, sum = 0
4097 11:17:44.195446 3, 0xFFFF, sum = 0
4098 11:17:44.196024 4, 0xFFFF, sum = 0
4099 11:17:44.198219 5, 0xFFFF, sum = 0
4100 11:17:44.198689 6, 0xFFFF, sum = 0
4101 11:17:44.201922 7, 0xFFFF, sum = 0
4102 11:17:44.202500 8, 0x0, sum = 1
4103 11:17:44.205062 9, 0x0, sum = 2
4104 11:17:44.205535 10, 0x0, sum = 3
4105 11:17:44.208427 11, 0x0, sum = 4
4106 11:17:44.209078 best_step = 9
4107 11:17:44.209458
4108 11:17:44.209797 ==
4109 11:17:44.211791 Dram Type= 6, Freq= 0, CH_0, rank 0
4110 11:17:44.215075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4111 11:17:44.215543 ==
4112 11:17:44.218415 RX Vref Scan: 1
4113 11:17:44.218879
4114 11:17:44.221628 RX Vref 0 -> 0, step: 1
4115 11:17:44.222202
4116 11:17:44.222572 RX Delay -179 -> 252, step: 8
4117 11:17:44.222918
4118 11:17:44.225132 Set Vref, RX VrefLevel [Byte0]: 57
4119 11:17:44.228089 [Byte1]: 49
4120 11:17:44.232974
4121 11:17:44.233544 Final RX Vref Byte 0 = 57 to rank0
4122 11:17:44.236330 Final RX Vref Byte 1 = 49 to rank0
4123 11:17:44.239625 Final RX Vref Byte 0 = 57 to rank1
4124 11:17:44.242742 Final RX Vref Byte 1 = 49 to rank1==
4125 11:17:44.246044 Dram Type= 6, Freq= 0, CH_0, rank 0
4126 11:17:44.252818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4127 11:17:44.253397 ==
4128 11:17:44.253769 DQS Delay:
4129 11:17:44.256241 DQS0 = 0, DQS1 = 0
4130 11:17:44.256834 DQM Delay:
4131 11:17:44.257212 DQM0 = 49, DQM1 = 39
4132 11:17:44.259418 DQ Delay:
4133 11:17:44.262549 DQ0 =44, DQ1 =52, DQ2 =44, DQ3 =44
4134 11:17:44.265843 DQ4 =52, DQ5 =40, DQ6 =60, DQ7 =56
4135 11:17:44.269424 DQ8 =36, DQ9 =24, DQ10 =36, DQ11 =36
4136 11:17:44.272729 DQ12 =44, DQ13 =40, DQ14 =52, DQ15 =48
4137 11:17:44.273332
4138 11:17:44.273702
4139 11:17:44.279081 [DQSOSCAuto] RK0, (LSB)MR18= 0x5650, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 393 ps
4140 11:17:44.282241 CH0 RK0: MR19=808, MR18=5650
4141 11:17:44.289667 CH0_RK0: MR19=0x808, MR18=0x5650, DQSOSC=393, MR23=63, INC=169, DEC=113
4142 11:17:44.290241
4143 11:17:44.292467 ----->DramcWriteLeveling(PI) begin...
4144 11:17:44.292963 ==
4145 11:17:44.296006 Dram Type= 6, Freq= 0, CH_0, rank 1
4146 11:17:44.298995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4147 11:17:44.299571 ==
4148 11:17:44.302241 Write leveling (Byte 0): 33 => 33
4149 11:17:44.305265 Write leveling (Byte 1): 32 => 32
4150 11:17:44.309003 DramcWriteLeveling(PI) end<-----
4151 11:17:44.309574
4152 11:17:44.309948 ==
4153 11:17:44.311969 Dram Type= 6, Freq= 0, CH_0, rank 1
4154 11:17:44.315322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4155 11:17:44.318754 ==
4156 11:17:44.319227 [Gating] SW mode calibration
4157 11:17:44.329257 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4158 11:17:44.331991 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4159 11:17:44.335152 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4160 11:17:44.342213 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4161 11:17:44.345388 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4162 11:17:44.348621 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 0)
4163 11:17:44.355327 0 9 16 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
4164 11:17:44.358589 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4165 11:17:44.361827 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4166 11:17:44.368824 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4167 11:17:44.371872 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4168 11:17:44.374687 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4169 11:17:44.381453 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4170 11:17:44.384984 0 10 12 | B1->B0 | 3232 3434 | 0 0 | (0 0) (0 0)
4171 11:17:44.388398 0 10 16 | B1->B0 | 4242 4646 | 1 0 | (0 0) (0 0)
4172 11:17:44.394935 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4173 11:17:44.398149 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4174 11:17:44.401482 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4175 11:17:44.408578 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4176 11:17:44.411764 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4177 11:17:44.414694 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4178 11:17:44.421200 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 11:17:44.424568 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4180 11:17:44.427927 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 11:17:44.434634 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 11:17:44.438063 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 11:17:44.441186 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 11:17:44.447886 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 11:17:44.451243 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 11:17:44.454453 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 11:17:44.461592 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 11:17:44.464429 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 11:17:44.467568 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 11:17:44.473968 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 11:17:44.477655 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 11:17:44.481001 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 11:17:44.487179 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 11:17:44.490554 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4195 11:17:44.493619 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4196 11:17:44.497125 Total UI for P1: 0, mck2ui 16
4197 11:17:44.500867 best dqsien dly found for B0: ( 0, 13, 12)
4198 11:17:44.507350 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4199 11:17:44.507923 Total UI for P1: 0, mck2ui 16
4200 11:17:44.514007 best dqsien dly found for B1: ( 0, 13, 14)
4201 11:17:44.516963 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4202 11:17:44.520225 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4203 11:17:44.520832
4204 11:17:44.523510 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4205 11:17:44.527115 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4206 11:17:44.530292 [Gating] SW calibration Done
4207 11:17:44.530790 ==
4208 11:17:44.533443 Dram Type= 6, Freq= 0, CH_0, rank 1
4209 11:17:44.536708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4210 11:17:44.537323 ==
4211 11:17:44.539949 RX Vref Scan: 0
4212 11:17:44.540509
4213 11:17:44.540918 RX Vref 0 -> 0, step: 1
4214 11:17:44.541326
4215 11:17:44.543492 RX Delay -230 -> 252, step: 16
4216 11:17:44.550046 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4217 11:17:44.553059 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4218 11:17:44.556630 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4219 11:17:44.559836 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4220 11:17:44.563283 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4221 11:17:44.569610 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4222 11:17:44.573127 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4223 11:17:44.576304 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4224 11:17:44.579844 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4225 11:17:44.586006 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4226 11:17:44.589284 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4227 11:17:44.592913 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4228 11:17:44.596289 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4229 11:17:44.602882 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4230 11:17:44.606486 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4231 11:17:44.609207 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4232 11:17:44.609675 ==
4233 11:17:44.612806 Dram Type= 6, Freq= 0, CH_0, rank 1
4234 11:17:44.615927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4235 11:17:44.619249 ==
4236 11:17:44.619726 DQS Delay:
4237 11:17:44.620100 DQS0 = 0, DQS1 = 0
4238 11:17:44.622729 DQM Delay:
4239 11:17:44.623289 DQM0 = 49, DQM1 = 41
4240 11:17:44.625688 DQ Delay:
4241 11:17:44.629247 DQ0 =49, DQ1 =49, DQ2 =49, DQ3 =41
4242 11:17:44.629820 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4243 11:17:44.632996 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =41
4244 11:17:44.639302 DQ12 =41, DQ13 =49, DQ14 =57, DQ15 =49
4245 11:17:44.639879
4246 11:17:44.640263
4247 11:17:44.640604 ==
4248 11:17:44.642475 Dram Type= 6, Freq= 0, CH_0, rank 1
4249 11:17:44.645468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4250 11:17:44.645937 ==
4251 11:17:44.646306
4252 11:17:44.646647
4253 11:17:44.649354 TX Vref Scan disable
4254 11:17:44.649819 == TX Byte 0 ==
4255 11:17:44.655772 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4256 11:17:44.658836 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4257 11:17:44.659409 == TX Byte 1 ==
4258 11:17:44.665606 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4259 11:17:44.668488 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4260 11:17:44.668981 ==
4261 11:17:44.671861 Dram Type= 6, Freq= 0, CH_0, rank 1
4262 11:17:44.675464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4263 11:17:44.675935 ==
4264 11:17:44.676307
4265 11:17:44.678545
4266 11:17:44.679011 TX Vref Scan disable
4267 11:17:44.682139 == TX Byte 0 ==
4268 11:17:44.685761 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4269 11:17:44.692227 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4270 11:17:44.692844 == TX Byte 1 ==
4271 11:17:44.695630 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4272 11:17:44.701943 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4273 11:17:44.702418
4274 11:17:44.702789 [DATLAT]
4275 11:17:44.703132 Freq=600, CH0 RK1
4276 11:17:44.703468
4277 11:17:44.704966 DATLAT Default: 0x9
4278 11:17:44.708443 0, 0xFFFF, sum = 0
4279 11:17:44.709085 1, 0xFFFF, sum = 0
4280 11:17:44.712165 2, 0xFFFF, sum = 0
4281 11:17:44.712742 3, 0xFFFF, sum = 0
4282 11:17:44.715655 4, 0xFFFF, sum = 0
4283 11:17:44.716235 5, 0xFFFF, sum = 0
4284 11:17:44.718364 6, 0xFFFF, sum = 0
4285 11:17:44.718942 7, 0xFFFF, sum = 0
4286 11:17:44.721819 8, 0x0, sum = 1
4287 11:17:44.722296 9, 0x0, sum = 2
4288 11:17:44.722675 10, 0x0, sum = 3
4289 11:17:44.724982 11, 0x0, sum = 4
4290 11:17:44.725563 best_step = 9
4291 11:17:44.726037
4292 11:17:44.728361 ==
4293 11:17:44.728860 Dram Type= 6, Freq= 0, CH_0, rank 1
4294 11:17:44.734994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4295 11:17:44.735456 ==
4296 11:17:44.735821 RX Vref Scan: 0
4297 11:17:44.736156
4298 11:17:44.738529 RX Vref 0 -> 0, step: 1
4299 11:17:44.738985
4300 11:17:44.741385 RX Delay -179 -> 252, step: 8
4301 11:17:44.748140 iDelay=205, Bit 0, Center 48 (-99 ~ 196) 296
4302 11:17:44.751265 iDelay=205, Bit 1, Center 48 (-99 ~ 196) 296
4303 11:17:44.754325 iDelay=205, Bit 2, Center 44 (-99 ~ 188) 288
4304 11:17:44.757647 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4305 11:17:44.761161 iDelay=205, Bit 4, Center 48 (-99 ~ 196) 296
4306 11:17:44.767488 iDelay=205, Bit 5, Center 40 (-107 ~ 188) 296
4307 11:17:44.771104 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4308 11:17:44.774246 iDelay=205, Bit 7, Center 56 (-91 ~ 204) 296
4309 11:17:44.777286 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4310 11:17:44.780972 iDelay=205, Bit 9, Center 28 (-115 ~ 172) 288
4311 11:17:44.787320 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4312 11:17:44.791585 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4313 11:17:44.794788 iDelay=205, Bit 12, Center 48 (-99 ~ 196) 296
4314 11:17:44.797058 iDelay=205, Bit 13, Center 44 (-99 ~ 188) 288
4315 11:17:44.803937 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4316 11:17:44.807466 iDelay=205, Bit 15, Center 48 (-91 ~ 188) 280
4317 11:17:44.808019 ==
4318 11:17:44.810605 Dram Type= 6, Freq= 0, CH_0, rank 1
4319 11:17:44.813930 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4320 11:17:44.814481 ==
4321 11:17:44.817500 DQS Delay:
4322 11:17:44.818044 DQS0 = 0, DQS1 = 0
4323 11:17:44.818406 DQM Delay:
4324 11:17:44.819987 DQM0 = 48, DQM1 = 40
4325 11:17:44.820497 DQ Delay:
4326 11:17:44.823902 DQ0 =48, DQ1 =48, DQ2 =44, DQ3 =44
4327 11:17:44.827064 DQ4 =48, DQ5 =40, DQ6 =60, DQ7 =56
4328 11:17:44.829981 DQ8 =32, DQ9 =28, DQ10 =40, DQ11 =32
4329 11:17:44.833482 DQ12 =48, DQ13 =44, DQ14 =48, DQ15 =48
4330 11:17:44.833940
4331 11:17:44.834297
4332 11:17:44.843386 [DQSOSCAuto] RK1, (LSB)MR18= 0x6533, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
4333 11:17:44.846471 CH0 RK1: MR19=808, MR18=6533
4334 11:17:44.853211 CH0_RK1: MR19=0x808, MR18=0x6533, DQSOSC=390, MR23=63, INC=172, DEC=114
4335 11:17:44.853672 [RxdqsGatingPostProcess] freq 600
4336 11:17:44.859859 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4337 11:17:44.863404 Pre-setting of DQS Precalculation
4338 11:17:44.866416 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4339 11:17:44.869696 ==
4340 11:17:44.873349 Dram Type= 6, Freq= 0, CH_1, rank 0
4341 11:17:44.876063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4342 11:17:44.876386 ==
4343 11:17:44.879673 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4344 11:17:44.885855 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4345 11:17:44.889694 [CA 0] Center 35 (5~66) winsize 62
4346 11:17:44.892887 [CA 1] Center 35 (5~66) winsize 62
4347 11:17:44.896748 [CA 2] Center 34 (4~65) winsize 62
4348 11:17:44.899530 [CA 3] Center 34 (3~65) winsize 63
4349 11:17:44.902899 [CA 4] Center 34 (3~65) winsize 63
4350 11:17:44.906233 [CA 5] Center 33 (3~64) winsize 62
4351 11:17:44.906340
4352 11:17:44.909330 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4353 11:17:44.909424
4354 11:17:44.912874 [CATrainingPosCal] consider 1 rank data
4355 11:17:44.916036 u2DelayCellTimex100 = 270/100 ps
4356 11:17:44.919430 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4357 11:17:44.925809 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4358 11:17:44.929262 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4359 11:17:44.932644 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4360 11:17:44.936023 CA4 delay=34 (3~65),Diff = 1 PI (9 cell)
4361 11:17:44.938906 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4362 11:17:44.938988
4363 11:17:44.942371 CA PerBit enable=1, Macro0, CA PI delay=33
4364 11:17:44.942453
4365 11:17:44.945533 [CBTSetCACLKResult] CA Dly = 33
4366 11:17:44.948734 CS Dly: 4 (0~35)
4367 11:17:44.948833 ==
4368 11:17:44.952561 Dram Type= 6, Freq= 0, CH_1, rank 1
4369 11:17:44.956187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4370 11:17:44.956270 ==
4371 11:17:44.962021 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4372 11:17:44.965417 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4373 11:17:44.969631 [CA 0] Center 35 (5~66) winsize 62
4374 11:17:44.973201 [CA 1] Center 35 (5~66) winsize 62
4375 11:17:44.976224 [CA 2] Center 34 (4~65) winsize 62
4376 11:17:44.979587 [CA 3] Center 34 (4~65) winsize 62
4377 11:17:44.982928 [CA 4] Center 34 (4~65) winsize 62
4378 11:17:44.986099 [CA 5] Center 34 (3~65) winsize 63
4379 11:17:44.986195
4380 11:17:44.989707 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4381 11:17:44.989801
4382 11:17:44.992826 [CATrainingPosCal] consider 2 rank data
4383 11:17:44.996180 u2DelayCellTimex100 = 270/100 ps
4384 11:17:44.999792 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4385 11:17:45.006032 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4386 11:17:45.009219 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4387 11:17:45.012699 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4388 11:17:45.016000 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4389 11:17:45.019354 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4390 11:17:45.019468
4391 11:17:45.022838 CA PerBit enable=1, Macro0, CA PI delay=33
4392 11:17:45.022930
4393 11:17:45.025711 [CBTSetCACLKResult] CA Dly = 33
4394 11:17:45.029186 CS Dly: 4 (0~36)
4395 11:17:45.029301
4396 11:17:45.032180 ----->DramcWriteLeveling(PI) begin...
4397 11:17:45.032280 ==
4398 11:17:45.035471 Dram Type= 6, Freq= 0, CH_1, rank 0
4399 11:17:45.038751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4400 11:17:45.038846 ==
4401 11:17:45.042249 Write leveling (Byte 0): 29 => 29
4402 11:17:45.045245 Write leveling (Byte 1): 31 => 31
4403 11:17:45.048661 DramcWriteLeveling(PI) end<-----
4404 11:17:45.048771
4405 11:17:45.048844 ==
4406 11:17:45.052114 Dram Type= 6, Freq= 0, CH_1, rank 0
4407 11:17:45.055544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4408 11:17:45.055660 ==
4409 11:17:45.058921 [Gating] SW mode calibration
4410 11:17:45.065363 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4411 11:17:45.071821 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4412 11:17:45.075286 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4413 11:17:45.078843 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4414 11:17:45.084998 0 9 8 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
4415 11:17:45.088322 0 9 12 | B1->B0 | 2d2d 2e2e | 0 1 | (1 1) (0 1)
4416 11:17:45.091583 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4417 11:17:45.098424 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 11:17:45.101678 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4419 11:17:45.104750 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4420 11:17:45.111299 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4421 11:17:45.114562 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4422 11:17:45.117997 0 10 8 | B1->B0 | 2424 2424 | 0 0 | (0 0) (0 0)
4423 11:17:45.124450 0 10 12 | B1->B0 | 3939 4343 | 1 0 | (0 0) (0 0)
4424 11:17:45.128023 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 11:17:45.131405 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 11:17:45.137881 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 11:17:45.140755 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 11:17:45.144094 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 11:17:45.150793 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 11:17:45.154158 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4431 11:17:45.157371 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4432 11:17:45.164597 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 11:17:45.167848 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 11:17:45.170844 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 11:17:45.177892 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 11:17:45.180848 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 11:17:45.184392 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 11:17:45.190878 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 11:17:45.194074 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 11:17:45.197740 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 11:17:45.204351 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 11:17:45.207984 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 11:17:45.211621 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 11:17:45.217696 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 11:17:45.221309 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 11:17:45.224473 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 11:17:45.230932 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4448 11:17:45.231491 Total UI for P1: 0, mck2ui 16
4449 11:17:45.237217 best dqsien dly found for B0: ( 0, 13, 10)
4450 11:17:45.237687 Total UI for P1: 0, mck2ui 16
4451 11:17:45.243913 best dqsien dly found for B1: ( 0, 13, 10)
4452 11:17:45.247659 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4453 11:17:45.250428 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4454 11:17:45.250987
4455 11:17:45.254055 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4456 11:17:45.257191 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4457 11:17:45.260639 [Gating] SW calibration Done
4458 11:17:45.261233 ==
4459 11:17:45.263700 Dram Type= 6, Freq= 0, CH_1, rank 0
4460 11:17:45.267478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4461 11:17:45.268039 ==
4462 11:17:45.270245 RX Vref Scan: 0
4463 11:17:45.270722
4464 11:17:45.273613 RX Vref 0 -> 0, step: 1
4465 11:17:45.274183
4466 11:17:45.274671 RX Delay -230 -> 252, step: 16
4467 11:17:45.280167 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4468 11:17:45.283299 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4469 11:17:45.286686 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4470 11:17:45.289991 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4471 11:17:45.296508 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4472 11:17:45.299993 iDelay=218, Bit 5, Center 57 (-86 ~ 201) 288
4473 11:17:45.303011 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4474 11:17:45.306730 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4475 11:17:45.312868 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4476 11:17:45.316318 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4477 11:17:45.319416 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4478 11:17:45.322938 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4479 11:17:45.329520 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4480 11:17:45.332991 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4481 11:17:45.336374 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4482 11:17:45.339035 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4483 11:17:45.339515 ==
4484 11:17:45.342513 Dram Type= 6, Freq= 0, CH_1, rank 0
4485 11:17:45.349641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4486 11:17:45.350143 ==
4487 11:17:45.350515 DQS Delay:
4488 11:17:45.352348 DQS0 = 0, DQS1 = 0
4489 11:17:45.352882 DQM Delay:
4490 11:17:45.353394 DQM0 = 51, DQM1 = 45
4491 11:17:45.355801 DQ Delay:
4492 11:17:45.359146 DQ0 =57, DQ1 =49, DQ2 =41, DQ3 =49
4493 11:17:45.362388 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4494 11:17:45.365447 DQ8 =25, DQ9 =33, DQ10 =49, DQ11 =41
4495 11:17:45.368865 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =49
4496 11:17:45.369283
4497 11:17:45.369632
4498 11:17:45.369940 ==
4499 11:17:45.372620 Dram Type= 6, Freq= 0, CH_1, rank 0
4500 11:17:45.375751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4501 11:17:45.376175 ==
4502 11:17:45.376505
4503 11:17:45.376866
4504 11:17:45.378642 TX Vref Scan disable
4505 11:17:45.381904 == TX Byte 0 ==
4506 11:17:45.385078 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4507 11:17:45.388798 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4508 11:17:45.391936 == TX Byte 1 ==
4509 11:17:45.395434 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4510 11:17:45.398838 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4511 11:17:45.399431 ==
4512 11:17:45.402144 Dram Type= 6, Freq= 0, CH_1, rank 0
4513 11:17:45.405207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4514 11:17:45.408566 ==
4515 11:17:45.409242
4516 11:17:45.409619
4517 11:17:45.409955 TX Vref Scan disable
4518 11:17:45.412187 == TX Byte 0 ==
4519 11:17:45.415602 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4520 11:17:45.422393 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4521 11:17:45.422856 == TX Byte 1 ==
4522 11:17:45.425462 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4523 11:17:45.432461 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4524 11:17:45.433079
4525 11:17:45.433449 [DATLAT]
4526 11:17:45.433845 Freq=600, CH1 RK0
4527 11:17:45.434182
4528 11:17:45.435497 DATLAT Default: 0x9
4529 11:17:45.436004 0, 0xFFFF, sum = 0
4530 11:17:45.438865 1, 0xFFFF, sum = 0
4531 11:17:45.442193 2, 0xFFFF, sum = 0
4532 11:17:45.442760 3, 0xFFFF, sum = 0
4533 11:17:45.445640 4, 0xFFFF, sum = 0
4534 11:17:45.446212 5, 0xFFFF, sum = 0
4535 11:17:45.448612 6, 0xFFFF, sum = 0
4536 11:17:45.449142 7, 0xFFFF, sum = 0
4537 11:17:45.452033 8, 0x0, sum = 1
4538 11:17:45.452498 9, 0x0, sum = 2
4539 11:17:45.452919 10, 0x0, sum = 3
4540 11:17:45.455731 11, 0x0, sum = 4
4541 11:17:45.456199 best_step = 9
4542 11:17:45.456564
4543 11:17:45.458730 ==
4544 11:17:45.459193 Dram Type= 6, Freq= 0, CH_1, rank 0
4545 11:17:45.465164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4546 11:17:45.465632 ==
4547 11:17:45.466004 RX Vref Scan: 1
4548 11:17:45.466354
4549 11:17:45.469400 RX Vref 0 -> 0, step: 1
4550 11:17:45.469968
4551 11:17:45.471977 RX Delay -179 -> 252, step: 8
4552 11:17:45.472543
4553 11:17:45.475394 Set Vref, RX VrefLevel [Byte0]: 51
4554 11:17:45.478590 [Byte1]: 52
4555 11:17:45.479155
4556 11:17:45.482267 Final RX Vref Byte 0 = 51 to rank0
4557 11:17:45.485325 Final RX Vref Byte 1 = 52 to rank0
4558 11:17:45.488434 Final RX Vref Byte 0 = 51 to rank1
4559 11:17:45.491669 Final RX Vref Byte 1 = 52 to rank1==
4560 11:17:45.495214 Dram Type= 6, Freq= 0, CH_1, rank 0
4561 11:17:45.498893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4562 11:17:45.499465 ==
4563 11:17:45.501822 DQS Delay:
4564 11:17:45.502286 DQS0 = 0, DQS1 = 0
4565 11:17:45.505159 DQM Delay:
4566 11:17:45.505622 DQM0 = 46, DQM1 = 37
4567 11:17:45.505988 DQ Delay:
4568 11:17:45.508807 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =40
4569 11:17:45.511959 DQ4 =48, DQ5 =56, DQ6 =56, DQ7 =40
4570 11:17:45.515156 DQ8 =24, DQ9 =24, DQ10 =44, DQ11 =32
4571 11:17:45.518216 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =44
4572 11:17:45.518706
4573 11:17:45.519113
4574 11:17:45.528058 [DQSOSCAuto] RK0, (LSB)MR18= 0x466c, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4575 11:17:45.531489 CH1 RK0: MR19=808, MR18=466C
4576 11:17:45.537997 CH1_RK0: MR19=0x808, MR18=0x466C, DQSOSC=389, MR23=63, INC=173, DEC=115
4577 11:17:45.538522
4578 11:17:45.541424 ----->DramcWriteLeveling(PI) begin...
4579 11:17:45.541985 ==
4580 11:17:45.545057 Dram Type= 6, Freq= 0, CH_1, rank 1
4581 11:17:45.548401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4582 11:17:45.548959 ==
4583 11:17:45.551487 Write leveling (Byte 0): 29 => 29
4584 11:17:45.554435 Write leveling (Byte 1): 29 => 29
4585 11:17:45.558059 DramcWriteLeveling(PI) end<-----
4586 11:17:45.558602
4587 11:17:45.558941 ==
4588 11:17:45.561188 Dram Type= 6, Freq= 0, CH_1, rank 1
4589 11:17:45.565345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4590 11:17:45.565871 ==
4591 11:17:45.568107 [Gating] SW mode calibration
4592 11:17:45.574642 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4593 11:17:45.581019 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4594 11:17:45.584882 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4595 11:17:45.587725 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4596 11:17:45.594345 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4597 11:17:45.597460 0 9 12 | B1->B0 | 2a2a 2f2f | 0 1 | (1 0) (1 0)
4598 11:17:45.600861 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4599 11:17:45.607644 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4600 11:17:45.610931 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4601 11:17:45.614627 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4602 11:17:45.621060 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4603 11:17:45.624449 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4604 11:17:45.627357 0 10 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4605 11:17:45.633818 0 10 12 | B1->B0 | 4343 3434 | 0 0 | (0 0) (0 0)
4606 11:17:45.637549 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4607 11:17:45.640510 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4608 11:17:45.646971 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4609 11:17:45.650508 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4610 11:17:45.653849 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4611 11:17:45.660166 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4612 11:17:45.663554 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4613 11:17:45.667031 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4614 11:17:45.674107 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 11:17:45.676838 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 11:17:45.680270 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 11:17:45.686722 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 11:17:45.689931 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 11:17:45.693335 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 11:17:45.700116 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 11:17:45.703390 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 11:17:45.706683 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 11:17:45.713136 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 11:17:45.716915 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 11:17:45.719882 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 11:17:45.726649 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 11:17:45.729381 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 11:17:45.732819 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 11:17:45.739396 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4630 11:17:45.743066 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4631 11:17:45.746448 Total UI for P1: 0, mck2ui 16
4632 11:17:45.749299 best dqsien dly found for B0: ( 0, 13, 12)
4633 11:17:45.752546 Total UI for P1: 0, mck2ui 16
4634 11:17:45.756234 best dqsien dly found for B1: ( 0, 13, 14)
4635 11:17:45.759449 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4636 11:17:45.762845 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4637 11:17:45.763554
4638 11:17:45.765905 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4639 11:17:45.769523 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4640 11:17:45.772700 [Gating] SW calibration Done
4641 11:17:45.773306 ==
4642 11:17:45.775691 Dram Type= 6, Freq= 0, CH_1, rank 1
4643 11:17:45.782591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4644 11:17:45.783156 ==
4645 11:17:45.783533 RX Vref Scan: 0
4646 11:17:45.783879
4647 11:17:45.785921 RX Vref 0 -> 0, step: 1
4648 11:17:45.786405
4649 11:17:45.788931 RX Delay -230 -> 252, step: 16
4650 11:17:45.792645 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4651 11:17:45.795900 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4652 11:17:45.798931 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4653 11:17:45.805654 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4654 11:17:45.809284 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4655 11:17:45.812388 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4656 11:17:45.815743 iDelay=218, Bit 6, Center 49 (-102 ~ 201) 304
4657 11:17:45.822091 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4658 11:17:45.825374 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4659 11:17:45.828923 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4660 11:17:45.832270 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4661 11:17:45.839176 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4662 11:17:45.842624 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4663 11:17:45.845426 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4664 11:17:45.848677 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4665 11:17:45.855555 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4666 11:17:45.856101 ==
4667 11:17:45.858375 Dram Type= 6, Freq= 0, CH_1, rank 1
4668 11:17:45.862086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4669 11:17:45.862666 ==
4670 11:17:45.863045 DQS Delay:
4671 11:17:45.864712 DQS0 = 0, DQS1 = 0
4672 11:17:45.865223 DQM Delay:
4673 11:17:45.868408 DQM0 = 46, DQM1 = 44
4674 11:17:45.868910 DQ Delay:
4675 11:17:45.871848 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4676 11:17:45.875322 DQ4 =49, DQ5 =57, DQ6 =49, DQ7 =49
4677 11:17:45.878090 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =41
4678 11:17:45.881576 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4679 11:17:45.882135
4680 11:17:45.882508
4681 11:17:45.882851 ==
4682 11:17:45.884897 Dram Type= 6, Freq= 0, CH_1, rank 1
4683 11:17:45.888058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4684 11:17:45.888527 ==
4685 11:17:45.888939
4686 11:17:45.891572
4687 11:17:45.892131 TX Vref Scan disable
4688 11:17:45.894637 == TX Byte 0 ==
4689 11:17:45.898075 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4690 11:17:45.901382 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4691 11:17:45.904720 == TX Byte 1 ==
4692 11:17:45.907972 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4693 11:17:45.911637 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4694 11:17:45.912207 ==
4695 11:17:45.914688 Dram Type= 6, Freq= 0, CH_1, rank 1
4696 11:17:45.921156 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4697 11:17:45.921728 ==
4698 11:17:45.922101
4699 11:17:45.922442
4700 11:17:45.922768 TX Vref Scan disable
4701 11:17:45.925885 == TX Byte 0 ==
4702 11:17:45.929350 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4703 11:17:45.935657 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4704 11:17:45.936205 == TX Byte 1 ==
4705 11:17:45.939235 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4706 11:17:45.945630 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4707 11:17:45.946183
4708 11:17:45.946553 [DATLAT]
4709 11:17:45.947090 Freq=600, CH1 RK1
4710 11:17:45.947530
4711 11:17:45.949101 DATLAT Default: 0x9
4712 11:17:45.949565 0, 0xFFFF, sum = 0
4713 11:17:45.952368 1, 0xFFFF, sum = 0
4714 11:17:45.955513 2, 0xFFFF, sum = 0
4715 11:17:45.956079 3, 0xFFFF, sum = 0
4716 11:17:45.958448 4, 0xFFFF, sum = 0
4717 11:17:45.958924 5, 0xFFFF, sum = 0
4718 11:17:45.961778 6, 0xFFFF, sum = 0
4719 11:17:45.962249 7, 0xFFFF, sum = 0
4720 11:17:45.965350 8, 0x0, sum = 1
4721 11:17:45.965918 9, 0x0, sum = 2
4722 11:17:45.969050 10, 0x0, sum = 3
4723 11:17:45.969620 11, 0x0, sum = 4
4724 11:17:45.970003 best_step = 9
4725 11:17:45.970348
4726 11:17:45.971699 ==
4727 11:17:45.975604 Dram Type= 6, Freq= 0, CH_1, rank 1
4728 11:17:45.978770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4729 11:17:45.979238 ==
4730 11:17:45.979611 RX Vref Scan: 0
4731 11:17:45.979956
4732 11:17:45.981838 RX Vref 0 -> 0, step: 1
4733 11:17:45.982301
4734 11:17:45.985196 RX Delay -179 -> 252, step: 8
4735 11:17:45.992024 iDelay=205, Bit 0, Center 52 (-91 ~ 196) 288
4736 11:17:45.994962 iDelay=205, Bit 1, Center 40 (-99 ~ 180) 280
4737 11:17:45.998497 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4738 11:17:46.001585 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4739 11:17:46.005057 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4740 11:17:46.011481 iDelay=205, Bit 5, Center 56 (-91 ~ 204) 296
4741 11:17:46.015176 iDelay=205, Bit 6, Center 52 (-91 ~ 196) 288
4742 11:17:46.018336 iDelay=205, Bit 7, Center 44 (-99 ~ 188) 288
4743 11:17:46.021581 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4744 11:17:46.024436 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4745 11:17:46.031369 iDelay=205, Bit 10, Center 40 (-107 ~ 188) 296
4746 11:17:46.034673 iDelay=205, Bit 11, Center 32 (-115 ~ 180) 296
4747 11:17:46.038000 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4748 11:17:46.044281 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4749 11:17:46.047527 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4750 11:17:46.050931 iDelay=205, Bit 15, Center 52 (-99 ~ 204) 304
4751 11:17:46.051562 ==
4752 11:17:46.054202 Dram Type= 6, Freq= 0, CH_1, rank 1
4753 11:17:46.057667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4754 11:17:46.058236 ==
4755 11:17:46.060375 DQS Delay:
4756 11:17:46.060869 DQS0 = 0, DQS1 = 0
4757 11:17:46.064119 DQM Delay:
4758 11:17:46.064677 DQM0 = 46, DQM1 = 39
4759 11:17:46.065083 DQ Delay:
4760 11:17:46.067245 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =44
4761 11:17:46.070348 DQ4 =44, DQ5 =56, DQ6 =52, DQ7 =44
4762 11:17:46.073879 DQ8 =28, DQ9 =32, DQ10 =40, DQ11 =32
4763 11:17:46.077377 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =52
4764 11:17:46.077946
4765 11:17:46.078317
4766 11:17:46.087219 [DQSOSCAuto] RK1, (LSB)MR18= 0x5a21, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 392 ps
4767 11:17:46.090133 CH1 RK1: MR19=808, MR18=5A21
4768 11:17:46.096681 CH1_RK1: MR19=0x808, MR18=0x5A21, DQSOSC=392, MR23=63, INC=170, DEC=113
4769 11:17:46.100355 [RxdqsGatingPostProcess] freq 600
4770 11:17:46.103627 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4771 11:17:46.106893 Pre-setting of DQS Precalculation
4772 11:17:46.113627 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4773 11:17:46.119795 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4774 11:17:46.126548 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4775 11:17:46.127107
4776 11:17:46.127475
4777 11:17:46.129648 [Calibration Summary] 1200 Mbps
4778 11:17:46.130111 CH 0, Rank 0
4779 11:17:46.133294 SW Impedance : PASS
4780 11:17:46.136146 DUTY Scan : NO K
4781 11:17:46.136614 ZQ Calibration : PASS
4782 11:17:46.139985 Jitter Meter : NO K
4783 11:17:46.142665 CBT Training : PASS
4784 11:17:46.143135 Write leveling : PASS
4785 11:17:46.146156 RX DQS gating : PASS
4786 11:17:46.149991 RX DQ/DQS(RDDQC) : PASS
4787 11:17:46.150550 TX DQ/DQS : PASS
4788 11:17:46.152818 RX DATLAT : PASS
4789 11:17:46.153376 RX DQ/DQS(Engine): PASS
4790 11:17:46.156218 TX OE : NO K
4791 11:17:46.156993 All Pass.
4792 11:17:46.157385
4793 11:17:46.159805 CH 0, Rank 1
4794 11:17:46.163041 SW Impedance : PASS
4795 11:17:46.163602 DUTY Scan : NO K
4796 11:17:46.166310 ZQ Calibration : PASS
4797 11:17:46.166879 Jitter Meter : NO K
4798 11:17:46.169503 CBT Training : PASS
4799 11:17:46.172725 Write leveling : PASS
4800 11:17:46.173319 RX DQS gating : PASS
4801 11:17:46.176043 RX DQ/DQS(RDDQC) : PASS
4802 11:17:46.179124 TX DQ/DQS : PASS
4803 11:17:46.179594 RX DATLAT : PASS
4804 11:17:46.182268 RX DQ/DQS(Engine): PASS
4805 11:17:46.185687 TX OE : NO K
4806 11:17:46.186150 All Pass.
4807 11:17:46.186515
4808 11:17:46.186857 CH 1, Rank 0
4809 11:17:46.188698 SW Impedance : PASS
4810 11:17:46.192260 DUTY Scan : NO K
4811 11:17:46.192957 ZQ Calibration : PASS
4812 11:17:46.195311 Jitter Meter : NO K
4813 11:17:46.198594 CBT Training : PASS
4814 11:17:46.199058 Write leveling : PASS
4815 11:17:46.202428 RX DQS gating : PASS
4816 11:17:46.205289 RX DQ/DQS(RDDQC) : PASS
4817 11:17:46.205752 TX DQ/DQS : PASS
4818 11:17:46.208646 RX DATLAT : PASS
4819 11:17:46.211997 RX DQ/DQS(Engine): PASS
4820 11:17:46.212415 TX OE : NO K
4821 11:17:46.215745 All Pass.
4822 11:17:46.216260
4823 11:17:46.216593 CH 1, Rank 1
4824 11:17:46.219063 SW Impedance : PASS
4825 11:17:46.219576 DUTY Scan : NO K
4826 11:17:46.222061 ZQ Calibration : PASS
4827 11:17:46.225411 Jitter Meter : NO K
4828 11:17:46.225829 CBT Training : PASS
4829 11:17:46.228848 Write leveling : PASS
4830 11:17:46.232257 RX DQS gating : PASS
4831 11:17:46.232799 RX DQ/DQS(RDDQC) : PASS
4832 11:17:46.235297 TX DQ/DQS : PASS
4833 11:17:46.235836 RX DATLAT : PASS
4834 11:17:46.238240 RX DQ/DQS(Engine): PASS
4835 11:17:46.241359 TX OE : NO K
4836 11:17:46.241441 All Pass.
4837 11:17:46.241505
4838 11:17:46.244369 DramC Write-DBI off
4839 11:17:46.247740 PER_BANK_REFRESH: Hybrid Mode
4840 11:17:46.247824 TX_TRACKING: ON
4841 11:17:46.257649 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4842 11:17:46.261124 [FAST_K] Save calibration result to emmc
4843 11:17:46.264210 dramc_set_vcore_voltage set vcore to 662500
4844 11:17:46.267623 Read voltage for 933, 3
4845 11:17:46.267706 Vio18 = 0
4846 11:17:46.267772 Vcore = 662500
4847 11:17:46.270908 Vdram = 0
4848 11:17:46.270990 Vddq = 0
4849 11:17:46.271054 Vmddr = 0
4850 11:17:46.277322 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4851 11:17:46.280567 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4852 11:17:46.283937 MEM_TYPE=3, freq_sel=17
4853 11:17:46.287377 sv_algorithm_assistance_LP4_1600
4854 11:17:46.290532 ============ PULL DRAM RESETB DOWN ============
4855 11:17:46.294082 ========== PULL DRAM RESETB DOWN end =========
4856 11:17:46.300622 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4857 11:17:46.303755 ===================================
4858 11:17:46.303840 LPDDR4 DRAM CONFIGURATION
4859 11:17:46.307267 ===================================
4860 11:17:46.310348 EX_ROW_EN[0] = 0x0
4861 11:17:46.313536 EX_ROW_EN[1] = 0x0
4862 11:17:46.313619 LP4Y_EN = 0x0
4863 11:17:46.317054 WORK_FSP = 0x0
4864 11:17:46.317136 WL = 0x3
4865 11:17:46.320231 RL = 0x3
4866 11:17:46.320314 BL = 0x2
4867 11:17:46.323789 RPST = 0x0
4868 11:17:46.323890 RD_PRE = 0x0
4869 11:17:46.326969 WR_PRE = 0x1
4870 11:17:46.327051 WR_PST = 0x0
4871 11:17:46.330524 DBI_WR = 0x0
4872 11:17:46.330607 DBI_RD = 0x0
4873 11:17:46.333968 OTF = 0x1
4874 11:17:46.336824 ===================================
4875 11:17:46.340311 ===================================
4876 11:17:46.340396 ANA top config
4877 11:17:46.343685 ===================================
4878 11:17:46.346864 DLL_ASYNC_EN = 0
4879 11:17:46.350109 ALL_SLAVE_EN = 1
4880 11:17:46.353505 NEW_RANK_MODE = 1
4881 11:17:46.353589 DLL_IDLE_MODE = 1
4882 11:17:46.356714 LP45_APHY_COMB_EN = 1
4883 11:17:46.360069 TX_ODT_DIS = 1
4884 11:17:46.363237 NEW_8X_MODE = 1
4885 11:17:46.366495 ===================================
4886 11:17:46.370011 ===================================
4887 11:17:46.373258 data_rate = 1866
4888 11:17:46.376358 CKR = 1
4889 11:17:46.376441 DQ_P2S_RATIO = 8
4890 11:17:46.379616 ===================================
4891 11:17:46.383135 CA_P2S_RATIO = 8
4892 11:17:46.386429 DQ_CA_OPEN = 0
4893 11:17:46.389556 DQ_SEMI_OPEN = 0
4894 11:17:46.393042 CA_SEMI_OPEN = 0
4895 11:17:46.396651 CA_FULL_RATE = 0
4896 11:17:46.396734 DQ_CKDIV4_EN = 1
4897 11:17:46.400275 CA_CKDIV4_EN = 1
4898 11:17:46.403168 CA_PREDIV_EN = 0
4899 11:17:46.406311 PH8_DLY = 0
4900 11:17:46.409899 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4901 11:17:46.409984 DQ_AAMCK_DIV = 4
4902 11:17:46.413464 CA_AAMCK_DIV = 4
4903 11:17:46.416177 CA_ADMCK_DIV = 4
4904 11:17:46.419637 DQ_TRACK_CA_EN = 0
4905 11:17:46.423102 CA_PICK = 933
4906 11:17:46.426405 CA_MCKIO = 933
4907 11:17:46.429526 MCKIO_SEMI = 0
4908 11:17:46.432874 PLL_FREQ = 3732
4909 11:17:46.432956 DQ_UI_PI_RATIO = 32
4910 11:17:46.436047 CA_UI_PI_RATIO = 0
4911 11:17:46.439312 ===================================
4912 11:17:46.442564 ===================================
4913 11:17:46.446266 memory_type:LPDDR4
4914 11:17:46.449348 GP_NUM : 10
4915 11:17:46.449430 SRAM_EN : 1
4916 11:17:46.453120 MD32_EN : 0
4917 11:17:46.456318 ===================================
4918 11:17:46.456401 [ANA_INIT] >>>>>>>>>>>>>>
4919 11:17:46.459312 <<<<<< [CONFIGURE PHASE]: ANA_TX
4920 11:17:46.462726 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4921 11:17:46.465810 ===================================
4922 11:17:46.469010 data_rate = 1866,PCW = 0X8f00
4923 11:17:46.472800 ===================================
4924 11:17:46.476008 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4925 11:17:46.482724 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4926 11:17:46.489473 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4927 11:17:46.492278 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4928 11:17:46.495908 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4929 11:17:46.499186 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4930 11:17:46.502262 [ANA_INIT] flow start
4931 11:17:46.502345 [ANA_INIT] PLL >>>>>>>>
4932 11:17:46.506034 [ANA_INIT] PLL <<<<<<<<
4933 11:17:46.509430 [ANA_INIT] MIDPI >>>>>>>>
4934 11:17:46.509512 [ANA_INIT] MIDPI <<<<<<<<
4935 11:17:46.512195 [ANA_INIT] DLL >>>>>>>>
4936 11:17:46.515503 [ANA_INIT] flow end
4937 11:17:46.518651 ============ LP4 DIFF to SE enter ============
4938 11:17:46.522233 ============ LP4 DIFF to SE exit ============
4939 11:17:46.525282 [ANA_INIT] <<<<<<<<<<<<<
4940 11:17:46.528451 [Flow] Enable top DCM control >>>>>
4941 11:17:46.532045 [Flow] Enable top DCM control <<<<<
4942 11:17:46.535260 Enable DLL master slave shuffle
4943 11:17:46.541826 ==============================================================
4944 11:17:46.541917 Gating Mode config
4945 11:17:46.548390 ==============================================================
4946 11:17:46.548475 Config description:
4947 11:17:46.558566 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4948 11:17:46.564907 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4949 11:17:46.571532 SELPH_MODE 0: By rank 1: By Phase
4950 11:17:46.574629 ==============================================================
4951 11:17:46.578275 GAT_TRACK_EN = 1
4952 11:17:46.581611 RX_GATING_MODE = 2
4953 11:17:46.584651 RX_GATING_TRACK_MODE = 2
4954 11:17:46.588007 SELPH_MODE = 1
4955 11:17:46.591313 PICG_EARLY_EN = 1
4956 11:17:46.594796 VALID_LAT_VALUE = 1
4957 11:17:46.601225 ==============================================================
4958 11:17:46.604367 Enter into Gating configuration >>>>
4959 11:17:46.608063 Exit from Gating configuration <<<<
4960 11:17:46.608145 Enter into DVFS_PRE_config >>>>>
4961 11:17:46.621093 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4962 11:17:46.624425 Exit from DVFS_PRE_config <<<<<
4963 11:17:46.628011 Enter into PICG configuration >>>>
4964 11:17:46.631206 Exit from PICG configuration <<<<
4965 11:17:46.631294 [RX_INPUT] configuration >>>>>
4966 11:17:46.634567 [RX_INPUT] configuration <<<<<
4967 11:17:46.641124 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4968 11:17:46.647697 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4969 11:17:46.650776 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4970 11:17:46.657561 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4971 11:17:46.663812 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4972 11:17:46.670801 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4973 11:17:46.673757 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4974 11:17:46.677195 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4975 11:17:46.683897 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4976 11:17:46.686954 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4977 11:17:46.690555 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4978 11:17:46.696790 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4979 11:17:46.700443 ===================================
4980 11:17:46.700532 LPDDR4 DRAM CONFIGURATION
4981 11:17:46.703754 ===================================
4982 11:17:46.706824 EX_ROW_EN[0] = 0x0
4983 11:17:46.706909 EX_ROW_EN[1] = 0x0
4984 11:17:46.710380 LP4Y_EN = 0x0
4985 11:17:46.713737 WORK_FSP = 0x0
4986 11:17:46.713821 WL = 0x3
4987 11:17:46.716966 RL = 0x3
4988 11:17:46.717049 BL = 0x2
4989 11:17:46.720466 RPST = 0x0
4990 11:17:46.720548 RD_PRE = 0x0
4991 11:17:46.723697 WR_PRE = 0x1
4992 11:17:46.723779 WR_PST = 0x0
4993 11:17:46.726668 DBI_WR = 0x0
4994 11:17:46.726750 DBI_RD = 0x0
4995 11:17:46.729857 OTF = 0x1
4996 11:17:46.733531 ===================================
4997 11:17:46.736745 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4998 11:17:46.740133 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4999 11:17:46.746892 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5000 11:17:46.749922 ===================================
5001 11:17:46.750008 LPDDR4 DRAM CONFIGURATION
5002 11:17:46.753157 ===================================
5003 11:17:46.756595 EX_ROW_EN[0] = 0x10
5004 11:17:46.759586 EX_ROW_EN[1] = 0x0
5005 11:17:46.759669 LP4Y_EN = 0x0
5006 11:17:46.762953 WORK_FSP = 0x0
5007 11:17:46.763036 WL = 0x3
5008 11:17:46.766414 RL = 0x3
5009 11:17:46.766496 BL = 0x2
5010 11:17:46.770064 RPST = 0x0
5011 11:17:46.770147 RD_PRE = 0x0
5012 11:17:46.772872 WR_PRE = 0x1
5013 11:17:46.772955 WR_PST = 0x0
5014 11:17:46.776877 DBI_WR = 0x0
5015 11:17:46.776960 DBI_RD = 0x0
5016 11:17:46.779771 OTF = 0x1
5017 11:17:46.782883 ===================================
5018 11:17:46.789535 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5019 11:17:46.792655 nWR fixed to 30
5020 11:17:46.792741 [ModeRegInit_LP4] CH0 RK0
5021 11:17:46.795919 [ModeRegInit_LP4] CH0 RK1
5022 11:17:46.799235 [ModeRegInit_LP4] CH1 RK0
5023 11:17:46.802645 [ModeRegInit_LP4] CH1 RK1
5024 11:17:46.802729 match AC timing 9
5025 11:17:46.809174 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5026 11:17:46.812300 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5027 11:17:46.815583 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5028 11:17:46.822340 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5029 11:17:46.825708 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5030 11:17:46.825792 ==
5031 11:17:46.828880 Dram Type= 6, Freq= 0, CH_0, rank 0
5032 11:17:46.832307 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5033 11:17:46.832391 ==
5034 11:17:46.838797 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5035 11:17:46.845877 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5036 11:17:46.848877 [CA 0] Center 37 (7~68) winsize 62
5037 11:17:46.852200 [CA 1] Center 38 (8~68) winsize 61
5038 11:17:46.855359 [CA 2] Center 35 (5~66) winsize 62
5039 11:17:46.858746 [CA 3] Center 34 (4~65) winsize 62
5040 11:17:46.861682 [CA 4] Center 34 (4~64) winsize 61
5041 11:17:46.864972 [CA 5] Center 33 (3~64) winsize 62
5042 11:17:46.865058
5043 11:17:46.868426 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5044 11:17:46.868542
5045 11:17:46.871877 [CATrainingPosCal] consider 1 rank data
5046 11:17:46.875229 u2DelayCellTimex100 = 270/100 ps
5047 11:17:46.878276 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5048 11:17:46.881521 CA1 delay=38 (8~68),Diff = 5 PI (31 cell)
5049 11:17:46.884757 CA2 delay=35 (5~66),Diff = 2 PI (12 cell)
5050 11:17:46.888247 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5051 11:17:46.891910 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5052 11:17:46.898073 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5053 11:17:46.898158
5054 11:17:46.901443 CA PerBit enable=1, Macro0, CA PI delay=33
5055 11:17:46.901529
5056 11:17:46.904482 [CBTSetCACLKResult] CA Dly = 33
5057 11:17:46.904566 CS Dly: 6 (0~37)
5058 11:17:46.904633 ==
5059 11:17:46.907777 Dram Type= 6, Freq= 0, CH_0, rank 1
5060 11:17:46.911211 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5061 11:17:46.914401 ==
5062 11:17:46.917778 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5063 11:17:46.924588 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5064 11:17:46.927661 [CA 0] Center 38 (7~69) winsize 63
5065 11:17:46.931124 [CA 1] Center 38 (8~69) winsize 62
5066 11:17:46.934653 [CA 2] Center 35 (6~65) winsize 60
5067 11:17:46.938049 [CA 3] Center 35 (5~66) winsize 62
5068 11:17:46.941075 [CA 4] Center 34 (4~65) winsize 62
5069 11:17:46.944227 [CA 5] Center 34 (4~64) winsize 61
5070 11:17:46.944309
5071 11:17:46.947741 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5072 11:17:46.947823
5073 11:17:46.950794 [CATrainingPosCal] consider 2 rank data
5074 11:17:46.954275 u2DelayCellTimex100 = 270/100 ps
5075 11:17:46.957550 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5076 11:17:46.960731 CA1 delay=38 (8~68),Diff = 4 PI (24 cell)
5077 11:17:46.964049 CA2 delay=35 (6~65),Diff = 1 PI (6 cell)
5078 11:17:46.971181 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5079 11:17:46.973928 CA4 delay=34 (4~64),Diff = 0 PI (0 cell)
5080 11:17:46.977401 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5081 11:17:46.977483
5082 11:17:46.980683 CA PerBit enable=1, Macro0, CA PI delay=34
5083 11:17:46.980771
5084 11:17:46.984027 [CBTSetCACLKResult] CA Dly = 34
5085 11:17:46.984109 CS Dly: 7 (0~39)
5086 11:17:46.984205
5087 11:17:46.987235 ----->DramcWriteLeveling(PI) begin...
5088 11:17:46.990803 ==
5089 11:17:46.990886 Dram Type= 6, Freq= 0, CH_0, rank 0
5090 11:17:46.997016 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5091 11:17:46.997103 ==
5092 11:17:47.000541 Write leveling (Byte 0): 34 => 34
5093 11:17:47.003828 Write leveling (Byte 1): 29 => 29
5094 11:17:47.007106 DramcWriteLeveling(PI) end<-----
5095 11:17:47.007189
5096 11:17:47.007255 ==
5097 11:17:47.010144 Dram Type= 6, Freq= 0, CH_0, rank 0
5098 11:17:47.013473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5099 11:17:47.013556 ==
5100 11:17:47.017099 [Gating] SW mode calibration
5101 11:17:47.023514 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5102 11:17:47.027031 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5103 11:17:47.033678 0 14 0 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
5104 11:17:47.037109 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5105 11:17:47.040246 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5106 11:17:47.046907 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5107 11:17:47.050067 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5108 11:17:47.053371 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5109 11:17:47.060212 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
5110 11:17:47.063349 0 14 28 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
5111 11:17:47.067029 0 15 0 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5112 11:17:47.073532 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5113 11:17:47.076757 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5114 11:17:47.079849 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5115 11:17:47.086188 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5116 11:17:47.089808 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5117 11:17:47.093295 0 15 24 | B1->B0 | 2323 3232 | 0 1 | (0 0) (0 0)
5118 11:17:47.099753 0 15 28 | B1->B0 | 2727 4545 | 0 0 | (0 0) (0 0)
5119 11:17:47.103062 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5120 11:17:47.106220 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5121 11:17:47.112761 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5122 11:17:47.116327 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5123 11:17:47.119480 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5124 11:17:47.126084 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5125 11:17:47.129298 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5126 11:17:47.132623 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5127 11:17:47.139293 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 11:17:47.142466 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 11:17:47.145964 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 11:17:47.152403 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 11:17:47.155690 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 11:17:47.159196 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 11:17:47.165661 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 11:17:47.168949 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 11:17:47.172418 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 11:17:47.178845 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 11:17:47.182363 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 11:17:47.185516 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 11:17:47.192393 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 11:17:47.195496 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 11:17:47.199296 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5142 11:17:47.205487 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5143 11:17:47.208723 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5144 11:17:47.212101 Total UI for P1: 0, mck2ui 16
5145 11:17:47.215249 best dqsien dly found for B0: ( 1, 2, 26)
5146 11:17:47.218506 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5147 11:17:47.221916 Total UI for P1: 0, mck2ui 16
5148 11:17:47.225202 best dqsien dly found for B1: ( 1, 2, 30)
5149 11:17:47.228798 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5150 11:17:47.231741 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5151 11:17:47.231823
5152 11:17:47.238403 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5153 11:17:47.241514 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5154 11:17:47.245011 [Gating] SW calibration Done
5155 11:17:47.245093 ==
5156 11:17:47.248322 Dram Type= 6, Freq= 0, CH_0, rank 0
5157 11:17:47.251454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5158 11:17:47.251537 ==
5159 11:17:47.251602 RX Vref Scan: 0
5160 11:17:47.251662
5161 11:17:47.254765 RX Vref 0 -> 0, step: 1
5162 11:17:47.254847
5163 11:17:47.258168 RX Delay -80 -> 252, step: 8
5164 11:17:47.261483 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5165 11:17:47.264730 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5166 11:17:47.271585 iDelay=208, Bit 2, Center 103 (16 ~ 191) 176
5167 11:17:47.274622 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5168 11:17:47.278117 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5169 11:17:47.281471 iDelay=208, Bit 5, Center 103 (16 ~ 191) 176
5170 11:17:47.284641 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5171 11:17:47.291337 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5172 11:17:47.294737 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5173 11:17:47.297972 iDelay=208, Bit 9, Center 79 (-8 ~ 167) 176
5174 11:17:47.301272 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5175 11:17:47.304357 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5176 11:17:47.308056 iDelay=208, Bit 12, Center 91 (0 ~ 183) 184
5177 11:17:47.314855 iDelay=208, Bit 13, Center 95 (8 ~ 183) 176
5178 11:17:47.317912 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5179 11:17:47.321274 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5180 11:17:47.321356 ==
5181 11:17:47.324138 Dram Type= 6, Freq= 0, CH_0, rank 0
5182 11:17:47.327270 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5183 11:17:47.330796 ==
5184 11:17:47.330878 DQS Delay:
5185 11:17:47.330942 DQS0 = 0, DQS1 = 0
5186 11:17:47.334149 DQM Delay:
5187 11:17:47.334231 DQM0 = 107, DQM1 = 91
5188 11:17:47.337300 DQ Delay:
5189 11:17:47.340566 DQ0 =107, DQ1 =107, DQ2 =103, DQ3 =103
5190 11:17:47.343732 DQ4 =107, DQ5 =103, DQ6 =115, DQ7 =115
5191 11:17:47.347230 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5192 11:17:47.350560 DQ12 =91, DQ13 =95, DQ14 =103, DQ15 =103
5193 11:17:47.350641
5194 11:17:47.350706
5195 11:17:47.350764 ==
5196 11:17:47.353791 Dram Type= 6, Freq= 0, CH_0, rank 0
5197 11:17:47.357194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5198 11:17:47.357280 ==
5199 11:17:47.357344
5200 11:17:47.357403
5201 11:17:47.360481 TX Vref Scan disable
5202 11:17:47.363813 == TX Byte 0 ==
5203 11:17:47.367409 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5204 11:17:47.370194 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5205 11:17:47.373828 == TX Byte 1 ==
5206 11:17:47.376887 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5207 11:17:47.380320 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5208 11:17:47.380402 ==
5209 11:17:47.383695 Dram Type= 6, Freq= 0, CH_0, rank 0
5210 11:17:47.390081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5211 11:17:47.390168 ==
5212 11:17:47.390235
5213 11:17:47.390295
5214 11:17:47.390354 TX Vref Scan disable
5215 11:17:47.393915 == TX Byte 0 ==
5216 11:17:47.397519 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5217 11:17:47.404465 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5218 11:17:47.404547 == TX Byte 1 ==
5219 11:17:47.407615 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5220 11:17:47.414587 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5221 11:17:47.414670
5222 11:17:47.414736 [DATLAT]
5223 11:17:47.414796 Freq=933, CH0 RK0
5224 11:17:47.414855
5225 11:17:47.417679 DATLAT Default: 0xd
5226 11:17:47.417761 0, 0xFFFF, sum = 0
5227 11:17:47.420704 1, 0xFFFF, sum = 0
5228 11:17:47.420826 2, 0xFFFF, sum = 0
5229 11:17:47.423865 3, 0xFFFF, sum = 0
5230 11:17:47.427480 4, 0xFFFF, sum = 0
5231 11:17:47.427564 5, 0xFFFF, sum = 0
5232 11:17:47.430548 6, 0xFFFF, sum = 0
5233 11:17:47.430637 7, 0xFFFF, sum = 0
5234 11:17:47.434156 8, 0xFFFF, sum = 0
5235 11:17:47.434239 9, 0xFFFF, sum = 0
5236 11:17:47.437520 10, 0x0, sum = 1
5237 11:17:47.437610 11, 0x0, sum = 2
5238 11:17:47.440489 12, 0x0, sum = 3
5239 11:17:47.440571 13, 0x0, sum = 4
5240 11:17:47.440637 best_step = 11
5241 11:17:47.443769
5242 11:17:47.443851 ==
5243 11:17:47.447068 Dram Type= 6, Freq= 0, CH_0, rank 0
5244 11:17:47.450300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5245 11:17:47.450383 ==
5246 11:17:47.450449 RX Vref Scan: 1
5247 11:17:47.450508
5248 11:17:47.453799 RX Vref 0 -> 0, step: 1
5249 11:17:47.453881
5250 11:17:47.457030 RX Delay -53 -> 252, step: 4
5251 11:17:47.457112
5252 11:17:47.460324 Set Vref, RX VrefLevel [Byte0]: 57
5253 11:17:47.463658 [Byte1]: 49
5254 11:17:47.463740
5255 11:17:47.466656 Final RX Vref Byte 0 = 57 to rank0
5256 11:17:47.470231 Final RX Vref Byte 1 = 49 to rank0
5257 11:17:47.473806 Final RX Vref Byte 0 = 57 to rank1
5258 11:17:47.476702 Final RX Vref Byte 1 = 49 to rank1==
5259 11:17:47.479841 Dram Type= 6, Freq= 0, CH_0, rank 0
5260 11:17:47.487062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5261 11:17:47.487142 ==
5262 11:17:47.487208 DQS Delay:
5263 11:17:47.487268 DQS0 = 0, DQS1 = 0
5264 11:17:47.490052 DQM Delay:
5265 11:17:47.490119 DQM0 = 108, DQM1 = 91
5266 11:17:47.493118 DQ Delay:
5267 11:17:47.496455 DQ0 =108, DQ1 =108, DQ2 =102, DQ3 =106
5268 11:17:47.499996 DQ4 =108, DQ5 =98, DQ6 =120, DQ7 =114
5269 11:17:47.503114 DQ8 =84, DQ9 =78, DQ10 =92, DQ11 =90
5270 11:17:47.506827 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =98
5271 11:17:47.506909
5272 11:17:47.506979
5273 11:17:47.513244 [DQSOSCAuto] RK0, (LSB)MR18= 0x231f, (MSB)MR19= 0x505, tDQSOscB0 = 412 ps tDQSOscB1 = 410 ps
5274 11:17:47.516399 CH0 RK0: MR19=505, MR18=231F
5275 11:17:47.522933 CH0_RK0: MR19=0x505, MR18=0x231F, DQSOSC=410, MR23=63, INC=64, DEC=42
5276 11:17:47.523042
5277 11:17:47.526361 ----->DramcWriteLeveling(PI) begin...
5278 11:17:47.526461 ==
5279 11:17:47.529744 Dram Type= 6, Freq= 0, CH_0, rank 1
5280 11:17:47.533002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5281 11:17:47.533114 ==
5282 11:17:47.536371 Write leveling (Byte 0): 32 => 32
5283 11:17:47.539713 Write leveling (Byte 1): 29 => 29
5284 11:17:47.542839 DramcWriteLeveling(PI) end<-----
5285 11:17:47.542928
5286 11:17:47.542994 ==
5287 11:17:47.546388 Dram Type= 6, Freq= 0, CH_0, rank 1
5288 11:17:47.552861 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5289 11:17:47.552945 ==
5290 11:17:47.553011 [Gating] SW mode calibration
5291 11:17:47.562936 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5292 11:17:47.566163 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5293 11:17:47.569512 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5294 11:17:47.575706 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5295 11:17:47.578968 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5296 11:17:47.582355 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5297 11:17:47.589198 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5298 11:17:47.592268 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5299 11:17:47.595914 0 14 24 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
5300 11:17:47.602150 0 14 28 | B1->B0 | 2c2c 2525 | 0 0 | (1 0) (0 0)
5301 11:17:47.605441 0 15 0 | B1->B0 | 2323 2323 | 1 0 | (1 0) (1 0)
5302 11:17:47.608700 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5303 11:17:47.615469 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5304 11:17:47.618556 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5305 11:17:47.622196 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5306 11:17:47.628612 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5307 11:17:47.631994 0 15 24 | B1->B0 | 2525 2d2d | 0 0 | (0 0) (0 0)
5308 11:17:47.635534 0 15 28 | B1->B0 | 3737 4040 | 0 0 | (0 0) (0 0)
5309 11:17:47.642025 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5310 11:17:47.645537 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5311 11:17:47.648545 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5312 11:17:47.655116 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5313 11:17:47.658512 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5314 11:17:47.661866 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5315 11:17:47.668701 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
5316 11:17:47.671762 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5317 11:17:47.675035 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5318 11:17:47.681530 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 11:17:47.684884 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 11:17:47.688061 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 11:17:47.694866 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 11:17:47.698017 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 11:17:47.701380 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 11:17:47.707922 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 11:17:47.711514 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 11:17:47.714787 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 11:17:47.721196 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 11:17:47.724506 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 11:17:47.727779 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 11:17:47.734598 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 11:17:47.737910 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 11:17:47.741328 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5333 11:17:47.744507 Total UI for P1: 0, mck2ui 16
5334 11:17:47.747978 best dqsien dly found for B0: ( 1, 2, 26)
5335 11:17:47.751101 Total UI for P1: 0, mck2ui 16
5336 11:17:47.754273 best dqsien dly found for B1: ( 1, 2, 26)
5337 11:17:47.757686 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5338 11:17:47.760890 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5339 11:17:47.760972
5340 11:17:47.767448 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5341 11:17:47.770773 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5342 11:17:47.774668 [Gating] SW calibration Done
5343 11:17:47.774749 ==
5344 11:17:47.777280 Dram Type= 6, Freq= 0, CH_0, rank 1
5345 11:17:47.780657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5346 11:17:47.780770 ==
5347 11:17:47.780839 RX Vref Scan: 0
5348 11:17:47.780900
5349 11:17:47.784152 RX Vref 0 -> 0, step: 1
5350 11:17:47.784233
5351 11:17:47.787452 RX Delay -80 -> 252, step: 8
5352 11:17:47.790537 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5353 11:17:47.793580 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5354 11:17:47.800550 iDelay=208, Bit 2, Center 103 (16 ~ 191) 176
5355 11:17:47.803729 iDelay=208, Bit 3, Center 103 (16 ~ 191) 176
5356 11:17:47.806977 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5357 11:17:47.810385 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5358 11:17:47.813811 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5359 11:17:47.820460 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5360 11:17:47.823835 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5361 11:17:47.827249 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5362 11:17:47.830274 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5363 11:17:47.833431 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5364 11:17:47.836953 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5365 11:17:47.843469 iDelay=208, Bit 13, Center 99 (16 ~ 183) 168
5366 11:17:47.847245 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5367 11:17:47.850391 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5368 11:17:47.850475 ==
5369 11:17:47.853479 Dram Type= 6, Freq= 0, CH_0, rank 1
5370 11:17:47.856694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5371 11:17:47.856801 ==
5372 11:17:47.860370 DQS Delay:
5373 11:17:47.860454 DQS0 = 0, DQS1 = 0
5374 11:17:47.863462 DQM Delay:
5375 11:17:47.863547 DQM0 = 105, DQM1 = 93
5376 11:17:47.866610 DQ Delay:
5377 11:17:47.869763 DQ0 =103, DQ1 =107, DQ2 =103, DQ3 =103
5378 11:17:47.873244 DQ4 =107, DQ5 =95, DQ6 =115, DQ7 =111
5379 11:17:47.876634 DQ8 =83, DQ9 =83, DQ10 =91, DQ11 =87
5380 11:17:47.879907 DQ12 =95, DQ13 =99, DQ14 =103, DQ15 =103
5381 11:17:47.879992
5382 11:17:47.880074
5383 11:17:47.880153 ==
5384 11:17:47.882862 Dram Type= 6, Freq= 0, CH_0, rank 1
5385 11:17:47.886804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5386 11:17:47.886890 ==
5387 11:17:47.886974
5388 11:17:47.887052
5389 11:17:47.890001 TX Vref Scan disable
5390 11:17:47.893128 == TX Byte 0 ==
5391 11:17:47.896214 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5392 11:17:47.899604 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5393 11:17:47.903096 == TX Byte 1 ==
5394 11:17:47.905986 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5395 11:17:47.909457 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5396 11:17:47.909541 ==
5397 11:17:47.912959 Dram Type= 6, Freq= 0, CH_0, rank 1
5398 11:17:47.915931 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5399 11:17:47.919498 ==
5400 11:17:47.919583
5401 11:17:47.919666
5402 11:17:47.919746 TX Vref Scan disable
5403 11:17:47.922968 == TX Byte 0 ==
5404 11:17:47.926275 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5405 11:17:47.932719 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5406 11:17:47.932843 == TX Byte 1 ==
5407 11:17:47.936251 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5408 11:17:47.942985 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5409 11:17:47.943069
5410 11:17:47.943134 [DATLAT]
5411 11:17:47.943194 Freq=933, CH0 RK1
5412 11:17:47.943253
5413 11:17:47.946204 DATLAT Default: 0xb
5414 11:17:47.946286 0, 0xFFFF, sum = 0
5415 11:17:47.949471 1, 0xFFFF, sum = 0
5416 11:17:47.952762 2, 0xFFFF, sum = 0
5417 11:17:47.952853 3, 0xFFFF, sum = 0
5418 11:17:47.956082 4, 0xFFFF, sum = 0
5419 11:17:47.956166 5, 0xFFFF, sum = 0
5420 11:17:47.959723 6, 0xFFFF, sum = 0
5421 11:17:47.959806 7, 0xFFFF, sum = 0
5422 11:17:47.962483 8, 0xFFFF, sum = 0
5423 11:17:47.962596 9, 0xFFFF, sum = 0
5424 11:17:47.965997 10, 0x0, sum = 1
5425 11:17:47.966081 11, 0x0, sum = 2
5426 11:17:47.969473 12, 0x0, sum = 3
5427 11:17:47.969556 13, 0x0, sum = 4
5428 11:17:47.969622 best_step = 11
5429 11:17:47.972487
5430 11:17:47.972594 ==
5431 11:17:47.975732 Dram Type= 6, Freq= 0, CH_0, rank 1
5432 11:17:47.979191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5433 11:17:47.979274 ==
5434 11:17:47.979340 RX Vref Scan: 0
5435 11:17:47.979401
5436 11:17:47.982312 RX Vref 0 -> 0, step: 1
5437 11:17:47.982394
5438 11:17:47.985633 RX Delay -53 -> 252, step: 4
5439 11:17:47.992285 iDelay=199, Bit 0, Center 104 (19 ~ 190) 172
5440 11:17:47.995676 iDelay=199, Bit 1, Center 106 (19 ~ 194) 176
5441 11:17:47.998977 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5442 11:17:48.002269 iDelay=199, Bit 3, Center 98 (15 ~ 182) 168
5443 11:17:48.005435 iDelay=199, Bit 4, Center 104 (19 ~ 190) 172
5444 11:17:48.012014 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5445 11:17:48.015268 iDelay=199, Bit 6, Center 110 (23 ~ 198) 176
5446 11:17:48.018625 iDelay=199, Bit 7, Center 110 (23 ~ 198) 176
5447 11:17:48.021811 iDelay=199, Bit 8, Center 86 (3 ~ 170) 168
5448 11:17:48.025669 iDelay=199, Bit 9, Center 80 (-1 ~ 162) 164
5449 11:17:48.028593 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5450 11:17:48.035336 iDelay=199, Bit 11, Center 92 (11 ~ 174) 164
5451 11:17:48.038551 iDelay=199, Bit 12, Center 96 (11 ~ 182) 172
5452 11:17:48.041732 iDelay=199, Bit 13, Center 94 (11 ~ 178) 168
5453 11:17:48.045063 iDelay=199, Bit 14, Center 100 (15 ~ 186) 172
5454 11:17:48.048690 iDelay=199, Bit 15, Center 98 (15 ~ 182) 168
5455 11:17:48.051716 ==
5456 11:17:48.055134 Dram Type= 6, Freq= 0, CH_0, rank 1
5457 11:17:48.058463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5458 11:17:48.058567 ==
5459 11:17:48.058697 DQS Delay:
5460 11:17:48.061880 DQS0 = 0, DQS1 = 0
5461 11:17:48.061965 DQM Delay:
5462 11:17:48.065204 DQM0 = 104, DQM1 = 92
5463 11:17:48.065288 DQ Delay:
5464 11:17:48.068311 DQ0 =104, DQ1 =106, DQ2 =102, DQ3 =98
5465 11:17:48.071545 DQ4 =104, DQ5 =98, DQ6 =110, DQ7 =110
5466 11:17:48.074695 DQ8 =86, DQ9 =80, DQ10 =94, DQ11 =92
5467 11:17:48.078246 DQ12 =96, DQ13 =94, DQ14 =100, DQ15 =98
5468 11:17:48.078331
5469 11:17:48.078397
5470 11:17:48.087824 [DQSOSCAuto] RK1, (LSB)MR18= 0x280a, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 409 ps
5471 11:17:48.087914 CH0 RK1: MR19=505, MR18=280A
5472 11:17:48.094579 CH0_RK1: MR19=0x505, MR18=0x280A, DQSOSC=409, MR23=63, INC=64, DEC=43
5473 11:17:48.097920 [RxdqsGatingPostProcess] freq 933
5474 11:17:48.104457 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5475 11:17:48.108023 best DQS0 dly(2T, 0.5T) = (0, 10)
5476 11:17:48.111374 best DQS1 dly(2T, 0.5T) = (0, 10)
5477 11:17:48.114655 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5478 11:17:48.117794 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5479 11:17:48.121778 best DQS0 dly(2T, 0.5T) = (0, 10)
5480 11:17:48.121862 best DQS1 dly(2T, 0.5T) = (0, 10)
5481 11:17:48.124406 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5482 11:17:48.127731 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5483 11:17:48.131057 Pre-setting of DQS Precalculation
5484 11:17:48.137679 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5485 11:17:48.137806 ==
5486 11:17:48.140926 Dram Type= 6, Freq= 0, CH_1, rank 0
5487 11:17:48.144476 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5488 11:17:48.144559 ==
5489 11:17:48.151117 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5490 11:17:48.157558 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5491 11:17:48.161006 [CA 0] Center 37 (7~68) winsize 62
5492 11:17:48.164140 [CA 1] Center 37 (7~68) winsize 62
5493 11:17:48.167291 [CA 2] Center 35 (5~65) winsize 61
5494 11:17:48.170557 [CA 3] Center 35 (5~65) winsize 61
5495 11:17:48.174125 [CA 4] Center 35 (5~66) winsize 62
5496 11:17:48.177448 [CA 5] Center 34 (4~65) winsize 62
5497 11:17:48.177530
5498 11:17:48.180527 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5499 11:17:48.180609
5500 11:17:48.184069 [CATrainingPosCal] consider 1 rank data
5501 11:17:48.187409 u2DelayCellTimex100 = 270/100 ps
5502 11:17:48.190715 CA0 delay=37 (7~68),Diff = 3 PI (18 cell)
5503 11:17:48.193868 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5504 11:17:48.197302 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5505 11:17:48.200308 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5506 11:17:48.203717 CA4 delay=35 (5~66),Diff = 1 PI (6 cell)
5507 11:17:48.207275 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5508 11:17:48.207358
5509 11:17:48.213962 CA PerBit enable=1, Macro0, CA PI delay=34
5510 11:17:48.214045
5511 11:17:48.216753 [CBTSetCACLKResult] CA Dly = 34
5512 11:17:48.216857 CS Dly: 6 (0~37)
5513 11:17:48.216923 ==
5514 11:17:48.220246 Dram Type= 6, Freq= 0, CH_1, rank 1
5515 11:17:48.223608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5516 11:17:48.223692 ==
5517 11:17:48.230100 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5518 11:17:48.236725 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5519 11:17:48.240134 [CA 0] Center 38 (8~68) winsize 61
5520 11:17:48.243375 [CA 1] Center 38 (7~69) winsize 63
5521 11:17:48.246817 [CA 2] Center 36 (6~66) winsize 61
5522 11:17:48.250033 [CA 3] Center 35 (6~65) winsize 60
5523 11:17:48.253555 [CA 4] Center 35 (5~65) winsize 61
5524 11:17:48.256949 [CA 5] Center 34 (4~65) winsize 62
5525 11:17:48.257035
5526 11:17:48.260098 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5527 11:17:48.260182
5528 11:17:48.263383 [CATrainingPosCal] consider 2 rank data
5529 11:17:48.266473 u2DelayCellTimex100 = 270/100 ps
5530 11:17:48.269780 CA0 delay=38 (8~68),Diff = 4 PI (24 cell)
5531 11:17:48.273162 CA1 delay=37 (7~68),Diff = 3 PI (18 cell)
5532 11:17:48.276646 CA2 delay=35 (6~65),Diff = 1 PI (6 cell)
5533 11:17:48.279841 CA3 delay=35 (6~65),Diff = 1 PI (6 cell)
5534 11:17:48.283078 CA4 delay=35 (5~65),Diff = 1 PI (6 cell)
5535 11:17:48.289921 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
5536 11:17:48.290006
5537 11:17:48.293225 CA PerBit enable=1, Macro0, CA PI delay=34
5538 11:17:48.293310
5539 11:17:48.296346 [CBTSetCACLKResult] CA Dly = 34
5540 11:17:48.296432 CS Dly: 7 (0~39)
5541 11:17:48.296531
5542 11:17:48.299940 ----->DramcWriteLeveling(PI) begin...
5543 11:17:48.300026 ==
5544 11:17:48.303134 Dram Type= 6, Freq= 0, CH_1, rank 0
5545 11:17:48.309470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5546 11:17:48.309554 ==
5547 11:17:48.313068 Write leveling (Byte 0): 27 => 27
5548 11:17:48.313151 Write leveling (Byte 1): 30 => 30
5549 11:17:48.316507 DramcWriteLeveling(PI) end<-----
5550 11:17:48.316590
5551 11:17:48.319667 ==
5552 11:17:48.322644 Dram Type= 6, Freq= 0, CH_1, rank 0
5553 11:17:48.326531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5554 11:17:48.326614 ==
5555 11:17:48.329937 [Gating] SW mode calibration
5556 11:17:48.336039 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5557 11:17:48.339249 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5558 11:17:48.346115 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5559 11:17:48.349368 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5560 11:17:48.352904 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5561 11:17:48.359187 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5562 11:17:48.362443 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5563 11:17:48.365794 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5564 11:17:48.372614 0 14 24 | B1->B0 | 3232 3030 | 1 1 | (0 0) (1 0)
5565 11:17:48.375660 0 14 28 | B1->B0 | 2929 2525 | 0 0 | (1 1) (0 0)
5566 11:17:48.379117 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5567 11:17:48.385464 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5568 11:17:48.388940 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5569 11:17:48.392292 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5570 11:17:48.398558 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5571 11:17:48.401904 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5572 11:17:48.405364 0 15 24 | B1->B0 | 2525 2e2e | 0 0 | (0 0) (1 1)
5573 11:17:48.412042 0 15 28 | B1->B0 | 3e3e 4242 | 1 0 | (0 0) (0 0)
5574 11:17:48.415356 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5575 11:17:48.418549 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5576 11:17:48.425491 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5577 11:17:48.428316 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5578 11:17:48.431895 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5579 11:17:48.438723 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5580 11:17:48.441873 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5581 11:17:48.444739 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5582 11:17:48.451517 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 11:17:48.454926 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 11:17:48.458350 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 11:17:48.464699 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 11:17:48.468145 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 11:17:48.471491 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 11:17:48.477997 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 11:17:48.481116 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 11:17:48.484745 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 11:17:48.491133 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 11:17:48.494773 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 11:17:48.497655 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 11:17:48.504233 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 11:17:48.507985 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 11:17:48.510937 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5597 11:17:48.517639 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5598 11:17:48.517727 Total UI for P1: 0, mck2ui 16
5599 11:17:48.524348 best dqsien dly found for B0: ( 1, 2, 24)
5600 11:17:48.527513 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5601 11:17:48.530490 Total UI for P1: 0, mck2ui 16
5602 11:17:48.534011 best dqsien dly found for B1: ( 1, 2, 26)
5603 11:17:48.537090 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5604 11:17:48.540655 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5605 11:17:48.540778
5606 11:17:48.544054 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5607 11:17:48.547225 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5608 11:17:48.550497 [Gating] SW calibration Done
5609 11:17:48.550582 ==
5610 11:17:48.553674 Dram Type= 6, Freq= 0, CH_1, rank 0
5611 11:17:48.560562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5612 11:17:48.560677 ==
5613 11:17:48.560794 RX Vref Scan: 0
5614 11:17:48.560875
5615 11:17:48.563568 RX Vref 0 -> 0, step: 1
5616 11:17:48.563652
5617 11:17:48.566897 RX Delay -80 -> 252, step: 8
5618 11:17:48.570220 iDelay=208, Bit 0, Center 103 (16 ~ 191) 176
5619 11:17:48.573663 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
5620 11:17:48.576947 iDelay=208, Bit 2, Center 95 (8 ~ 183) 176
5621 11:17:48.580106 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5622 11:17:48.583943 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5623 11:17:48.590409 iDelay=208, Bit 5, Center 111 (24 ~ 199) 176
5624 11:17:48.593517 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5625 11:17:48.596616 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5626 11:17:48.599966 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5627 11:17:48.603489 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5628 11:17:48.610053 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5629 11:17:48.613383 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5630 11:17:48.616804 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5631 11:17:48.619684 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5632 11:17:48.623200 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5633 11:17:48.626644 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5634 11:17:48.630012 ==
5635 11:17:48.632956 Dram Type= 6, Freq= 0, CH_1, rank 0
5636 11:17:48.636245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5637 11:17:48.636334 ==
5638 11:17:48.636400 DQS Delay:
5639 11:17:48.639656 DQS0 = 0, DQS1 = 0
5640 11:17:48.639740 DQM Delay:
5641 11:17:48.642926 DQM0 = 101, DQM1 = 95
5642 11:17:48.643010 DQ Delay:
5643 11:17:48.646125 DQ0 =103, DQ1 =95, DQ2 =95, DQ3 =99
5644 11:17:48.649663 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5645 11:17:48.653023 DQ8 =83, DQ9 =83, DQ10 =99, DQ11 =91
5646 11:17:48.656327 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =99
5647 11:17:48.656412
5648 11:17:48.656478
5649 11:17:48.656567 ==
5650 11:17:48.659388 Dram Type= 6, Freq= 0, CH_1, rank 0
5651 11:17:48.662990 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5652 11:17:48.666177 ==
5653 11:17:48.666261
5654 11:17:48.666327
5655 11:17:48.666386 TX Vref Scan disable
5656 11:17:48.669569 == TX Byte 0 ==
5657 11:17:48.672882 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5658 11:17:48.675948 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5659 11:17:48.679142 == TX Byte 1 ==
5660 11:17:48.682519 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5661 11:17:48.686301 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5662 11:17:48.686386 ==
5663 11:17:48.689462 Dram Type= 6, Freq= 0, CH_1, rank 0
5664 11:17:48.696173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5665 11:17:48.696267 ==
5666 11:17:48.696335
5667 11:17:48.696396
5668 11:17:48.699353 TX Vref Scan disable
5669 11:17:48.699458 == TX Byte 0 ==
5670 11:17:48.705660 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5671 11:17:48.709054 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5672 11:17:48.709139 == TX Byte 1 ==
5673 11:17:48.715852 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5674 11:17:48.719065 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5675 11:17:48.719149
5676 11:17:48.719215 [DATLAT]
5677 11:17:48.722086 Freq=933, CH1 RK0
5678 11:17:48.722170
5679 11:17:48.722236 DATLAT Default: 0xd
5680 11:17:48.725833 0, 0xFFFF, sum = 0
5681 11:17:48.725918 1, 0xFFFF, sum = 0
5682 11:17:48.729373 2, 0xFFFF, sum = 0
5683 11:17:48.729458 3, 0xFFFF, sum = 0
5684 11:17:48.732267 4, 0xFFFF, sum = 0
5685 11:17:48.732351 5, 0xFFFF, sum = 0
5686 11:17:48.735825 6, 0xFFFF, sum = 0
5687 11:17:48.735910 7, 0xFFFF, sum = 0
5688 11:17:48.738914 8, 0xFFFF, sum = 0
5689 11:17:48.741931 9, 0xFFFF, sum = 0
5690 11:17:48.742016 10, 0x0, sum = 1
5691 11:17:48.742084 11, 0x0, sum = 2
5692 11:17:48.745249 12, 0x0, sum = 3
5693 11:17:48.745334 13, 0x0, sum = 4
5694 11:17:48.748643 best_step = 11
5695 11:17:48.748726
5696 11:17:48.748796 ==
5697 11:17:48.751903 Dram Type= 6, Freq= 0, CH_1, rank 0
5698 11:17:48.755544 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5699 11:17:48.755629 ==
5700 11:17:48.758728 RX Vref Scan: 1
5701 11:17:48.758811
5702 11:17:48.758877 RX Vref 0 -> 0, step: 1
5703 11:17:48.758939
5704 11:17:48.762119 RX Delay -53 -> 252, step: 4
5705 11:17:48.762203
5706 11:17:48.765093 Set Vref, RX VrefLevel [Byte0]: 51
5707 11:17:48.768457 [Byte1]: 52
5708 11:17:48.773203
5709 11:17:48.773286 Final RX Vref Byte 0 = 51 to rank0
5710 11:17:48.776240 Final RX Vref Byte 1 = 52 to rank0
5711 11:17:48.779441 Final RX Vref Byte 0 = 51 to rank1
5712 11:17:48.783066 Final RX Vref Byte 1 = 52 to rank1==
5713 11:17:48.786351 Dram Type= 6, Freq= 0, CH_1, rank 0
5714 11:17:48.792947 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5715 11:17:48.793033 ==
5716 11:17:48.793100 DQS Delay:
5717 11:17:48.795960 DQS0 = 0, DQS1 = 0
5718 11:17:48.796047 DQM Delay:
5719 11:17:48.796114 DQM0 = 105, DQM1 = 97
5720 11:17:48.799214 DQ Delay:
5721 11:17:48.802749 DQ0 =108, DQ1 =98, DQ2 =96, DQ3 =104
5722 11:17:48.806052 DQ4 =104, DQ5 =114, DQ6 =116, DQ7 =102
5723 11:17:48.809162 DQ8 =88, DQ9 =84, DQ10 =100, DQ11 =94
5724 11:17:48.812234 DQ12 =106, DQ13 =100, DQ14 =102, DQ15 =102
5725 11:17:48.812315
5726 11:17:48.812415
5727 11:17:48.822133 [DQSOSCAuto] RK0, (LSB)MR18= 0x152d, (MSB)MR19= 0x505, tDQSOscB0 = 407 ps tDQSOscB1 = 415 ps
5728 11:17:48.822218 CH1 RK0: MR19=505, MR18=152D
5729 11:17:48.828669 CH1_RK0: MR19=0x505, MR18=0x152D, DQSOSC=407, MR23=63, INC=65, DEC=43
5730 11:17:48.828755
5731 11:17:48.831923 ----->DramcWriteLeveling(PI) begin...
5732 11:17:48.832010 ==
5733 11:17:48.835342 Dram Type= 6, Freq= 0, CH_1, rank 1
5734 11:17:48.841646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5735 11:17:48.841732 ==
5736 11:17:48.844814 Write leveling (Byte 0): 26 => 26
5737 11:17:48.848440 Write leveling (Byte 1): 28 => 28
5738 11:17:48.848526 DramcWriteLeveling(PI) end<-----
5739 11:17:48.851714
5740 11:17:48.851812 ==
5741 11:17:48.854920 Dram Type= 6, Freq= 0, CH_1, rank 1
5742 11:17:48.858741 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5743 11:17:48.858818 ==
5744 11:17:48.861709 [Gating] SW mode calibration
5745 11:17:48.868037 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5746 11:17:48.871376 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5747 11:17:48.877893 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5748 11:17:48.881073 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5749 11:17:48.884347 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5750 11:17:48.891236 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5751 11:17:48.894238 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5752 11:17:48.897835 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
5753 11:17:48.904255 0 14 24 | B1->B0 | 3030 3333 | 0 1 | (0 1) (1 0)
5754 11:17:48.907729 0 14 28 | B1->B0 | 2424 2929 | 0 1 | (0 0) (1 0)
5755 11:17:48.911211 0 15 0 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5756 11:17:48.917597 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5757 11:17:48.921060 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5758 11:17:48.924173 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5759 11:17:48.930717 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5760 11:17:48.934204 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5761 11:17:48.937413 0 15 24 | B1->B0 | 2a2a 2424 | 0 0 | (0 0) (0 0)
5762 11:17:48.944396 0 15 28 | B1->B0 | 4545 3f3f | 0 0 | (0 0) (0 0)
5763 11:17:48.947493 1 0 0 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
5764 11:17:48.950589 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5765 11:17:48.957192 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5766 11:17:48.960751 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5767 11:17:48.964138 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5768 11:17:48.970957 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5769 11:17:48.974494 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5770 11:17:48.977216 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5771 11:17:48.983965 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 11:17:48.987167 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 11:17:48.990465 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 11:17:48.996908 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 11:17:49.000351 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 11:17:49.003742 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 11:17:49.010381 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 11:17:49.013558 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 11:17:49.016671 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 11:17:49.023140 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 11:17:49.026830 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 11:17:49.029810 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 11:17:49.036457 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 11:17:49.039851 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 11:17:49.043037 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5786 11:17:49.049646 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5787 11:17:49.049769 Total UI for P1: 0, mck2ui 16
5788 11:17:49.056195 best dqsien dly found for B1: ( 1, 2, 24)
5789 11:17:49.059835 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5790 11:17:49.063040 Total UI for P1: 0, mck2ui 16
5791 11:17:49.066367 best dqsien dly found for B0: ( 1, 2, 26)
5792 11:17:49.070057 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5793 11:17:49.072833 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5794 11:17:49.072949
5795 11:17:49.076267 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5796 11:17:49.079452 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5797 11:17:49.083029 [Gating] SW calibration Done
5798 11:17:49.083141 ==
5799 11:17:49.086363 Dram Type= 6, Freq= 0, CH_1, rank 1
5800 11:17:49.089984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5801 11:17:49.092634 ==
5802 11:17:49.092743 RX Vref Scan: 0
5803 11:17:49.092878
5804 11:17:49.096409 RX Vref 0 -> 0, step: 1
5805 11:17:49.096521
5806 11:17:49.099430 RX Delay -80 -> 252, step: 8
5807 11:17:49.102642 iDelay=200, Bit 0, Center 107 (24 ~ 191) 168
5808 11:17:49.105784 iDelay=200, Bit 1, Center 99 (16 ~ 183) 168
5809 11:17:49.109465 iDelay=200, Bit 2, Center 87 (0 ~ 175) 176
5810 11:17:49.112787 iDelay=200, Bit 3, Center 103 (16 ~ 191) 176
5811 11:17:49.119401 iDelay=200, Bit 4, Center 103 (16 ~ 191) 176
5812 11:17:49.122552 iDelay=200, Bit 5, Center 111 (24 ~ 199) 176
5813 11:17:49.125914 iDelay=200, Bit 6, Center 111 (24 ~ 199) 176
5814 11:17:49.129541 iDelay=200, Bit 7, Center 103 (16 ~ 191) 176
5815 11:17:49.132716 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5816 11:17:49.135872 iDelay=200, Bit 9, Center 87 (0 ~ 175) 176
5817 11:17:49.142389 iDelay=200, Bit 10, Center 99 (8 ~ 191) 184
5818 11:17:49.145613 iDelay=200, Bit 11, Center 91 (0 ~ 183) 184
5819 11:17:49.148784 iDelay=200, Bit 12, Center 107 (16 ~ 199) 184
5820 11:17:49.152437 iDelay=200, Bit 13, Center 107 (16 ~ 199) 184
5821 11:17:49.155656 iDelay=200, Bit 14, Center 103 (8 ~ 199) 192
5822 11:17:49.162553 iDelay=200, Bit 15, Center 107 (16 ~ 199) 184
5823 11:17:49.162669 ==
5824 11:17:49.165382 Dram Type= 6, Freq= 0, CH_1, rank 1
5825 11:17:49.168752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5826 11:17:49.168886 ==
5827 11:17:49.168987 DQS Delay:
5828 11:17:49.172126 DQS0 = 0, DQS1 = 0
5829 11:17:49.172234 DQM Delay:
5830 11:17:49.175631 DQM0 = 103, DQM1 = 98
5831 11:17:49.175742 DQ Delay:
5832 11:17:49.178540 DQ0 =107, DQ1 =99, DQ2 =87, DQ3 =103
5833 11:17:49.181873 DQ4 =103, DQ5 =111, DQ6 =111, DQ7 =103
5834 11:17:49.185462 DQ8 =83, DQ9 =87, DQ10 =99, DQ11 =91
5835 11:17:49.188693 DQ12 =107, DQ13 =107, DQ14 =103, DQ15 =107
5836 11:17:49.188840
5837 11:17:49.188942
5838 11:17:49.191804 ==
5839 11:17:49.195080 Dram Type= 6, Freq= 0, CH_1, rank 1
5840 11:17:49.198577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5841 11:17:49.198693 ==
5842 11:17:49.198791
5843 11:17:49.198884
5844 11:17:49.202021 TX Vref Scan disable
5845 11:17:49.202136 == TX Byte 0 ==
5846 11:17:49.204991 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5847 11:17:49.211867 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5848 11:17:49.211983 == TX Byte 1 ==
5849 11:17:49.218494 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5850 11:17:49.221812 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5851 11:17:49.221924 ==
5852 11:17:49.224681 Dram Type= 6, Freq= 0, CH_1, rank 1
5853 11:17:49.228114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5854 11:17:49.228225 ==
5855 11:17:49.228323
5856 11:17:49.228421
5857 11:17:49.231172 TX Vref Scan disable
5858 11:17:49.234637 == TX Byte 0 ==
5859 11:17:49.237741 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5860 11:17:49.241126 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5861 11:17:49.244490 == TX Byte 1 ==
5862 11:17:49.247958 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5863 11:17:49.251368 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5864 11:17:49.251477
5865 11:17:49.254474 [DATLAT]
5866 11:17:49.254585 Freq=933, CH1 RK1
5867 11:17:49.254681
5868 11:17:49.257901 DATLAT Default: 0xb
5869 11:17:49.258009 0, 0xFFFF, sum = 0
5870 11:17:49.260991 1, 0xFFFF, sum = 0
5871 11:17:49.261101 2, 0xFFFF, sum = 0
5872 11:17:49.264273 3, 0xFFFF, sum = 0
5873 11:17:49.264383 4, 0xFFFF, sum = 0
5874 11:17:49.267549 5, 0xFFFF, sum = 0
5875 11:17:49.267665 6, 0xFFFF, sum = 0
5876 11:17:49.271667 7, 0xFFFF, sum = 0
5877 11:17:49.271776 8, 0xFFFF, sum = 0
5878 11:17:49.274160 9, 0xFFFF, sum = 0
5879 11:17:49.274270 10, 0x0, sum = 1
5880 11:17:49.277661 11, 0x0, sum = 2
5881 11:17:49.277770 12, 0x0, sum = 3
5882 11:17:49.280854 13, 0x0, sum = 4
5883 11:17:49.280965 best_step = 11
5884 11:17:49.281063
5885 11:17:49.281157 ==
5886 11:17:49.284387 Dram Type= 6, Freq= 0, CH_1, rank 1
5887 11:17:49.291056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5888 11:17:49.291173 ==
5889 11:17:49.291276 RX Vref Scan: 0
5890 11:17:49.291372
5891 11:17:49.293975 RX Vref 0 -> 0, step: 1
5892 11:17:49.294158
5893 11:17:49.297751 RX Delay -53 -> 252, step: 4
5894 11:17:49.300902 iDelay=199, Bit 0, Center 108 (31 ~ 186) 156
5895 11:17:49.304091 iDelay=199, Bit 1, Center 98 (19 ~ 178) 160
5896 11:17:49.310833 iDelay=199, Bit 2, Center 94 (15 ~ 174) 160
5897 11:17:49.313856 iDelay=199, Bit 3, Center 106 (27 ~ 186) 160
5898 11:17:49.317188 iDelay=199, Bit 4, Center 106 (27 ~ 186) 160
5899 11:17:49.320443 iDelay=199, Bit 5, Center 114 (31 ~ 198) 168
5900 11:17:49.323668 iDelay=199, Bit 6, Center 112 (31 ~ 194) 164
5901 11:17:49.330623 iDelay=199, Bit 7, Center 104 (27 ~ 182) 156
5902 11:17:49.333687 iDelay=199, Bit 8, Center 84 (-1 ~ 170) 172
5903 11:17:49.337271 iDelay=199, Bit 9, Center 88 (7 ~ 170) 164
5904 11:17:49.340178 iDelay=199, Bit 10, Center 98 (15 ~ 182) 168
5905 11:17:49.343669 iDelay=199, Bit 11, Center 92 (7 ~ 178) 172
5906 11:17:49.350477 iDelay=199, Bit 12, Center 106 (19 ~ 194) 176
5907 11:17:49.353353 iDelay=199, Bit 13, Center 104 (19 ~ 190) 172
5908 11:17:49.356745 iDelay=199, Bit 14, Center 106 (19 ~ 194) 176
5909 11:17:49.360194 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5910 11:17:49.360302 ==
5911 11:17:49.363480 Dram Type= 6, Freq= 0, CH_1, rank 1
5912 11:17:49.370416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5913 11:17:49.370527 ==
5914 11:17:49.370630 DQS Delay:
5915 11:17:49.373619 DQS0 = 0, DQS1 = 0
5916 11:17:49.373728 DQM Delay:
5917 11:17:49.373828 DQM0 = 105, DQM1 = 98
5918 11:17:49.376856 DQ Delay:
5919 11:17:49.380193 DQ0 =108, DQ1 =98, DQ2 =94, DQ3 =106
5920 11:17:49.383597 DQ4 =106, DQ5 =114, DQ6 =112, DQ7 =104
5921 11:17:49.386569 DQ8 =84, DQ9 =88, DQ10 =98, DQ11 =92
5922 11:17:49.390296 DQ12 =106, DQ13 =104, DQ14 =106, DQ15 =106
5923 11:17:49.390406
5924 11:17:49.390502
5925 11:17:49.396478 [DQSOSCAuto] RK1, (LSB)MR18= 0x21fe, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 411 ps
5926 11:17:49.399789 CH1 RK1: MR19=504, MR18=21FE
5927 11:17:49.406698 CH1_RK1: MR19=0x504, MR18=0x21FE, DQSOSC=411, MR23=63, INC=64, DEC=42
5928 11:17:49.409815 [RxdqsGatingPostProcess] freq 933
5929 11:17:49.416341 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5930 11:17:49.420039 best DQS0 dly(2T, 0.5T) = (0, 10)
5931 11:17:49.423095 best DQS1 dly(2T, 0.5T) = (0, 10)
5932 11:17:49.426459 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5933 11:17:49.429550 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5934 11:17:49.429663 best DQS0 dly(2T, 0.5T) = (0, 10)
5935 11:17:49.432761 best DQS1 dly(2T, 0.5T) = (0, 10)
5936 11:17:49.436222 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5937 11:17:49.439491 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5938 11:17:49.442934 Pre-setting of DQS Precalculation
5939 11:17:49.449411 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5940 11:17:49.455845 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5941 11:17:49.462499 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5942 11:17:49.462616
5943 11:17:49.462715
5944 11:17:49.465935 [Calibration Summary] 1866 Mbps
5945 11:17:49.466044 CH 0, Rank 0
5946 11:17:49.469130 SW Impedance : PASS
5947 11:17:49.472502 DUTY Scan : NO K
5948 11:17:49.472610 ZQ Calibration : PASS
5949 11:17:49.475711 Jitter Meter : NO K
5950 11:17:49.478782 CBT Training : PASS
5951 11:17:49.478892 Write leveling : PASS
5952 11:17:49.482360 RX DQS gating : PASS
5953 11:17:49.485453 RX DQ/DQS(RDDQC) : PASS
5954 11:17:49.485565 TX DQ/DQS : PASS
5955 11:17:49.488875 RX DATLAT : PASS
5956 11:17:49.491890 RX DQ/DQS(Engine): PASS
5957 11:17:49.491997 TX OE : NO K
5958 11:17:49.495567 All Pass.
5959 11:17:49.495675
5960 11:17:49.495771 CH 0, Rank 1
5961 11:17:49.498833 SW Impedance : PASS
5962 11:17:49.498944 DUTY Scan : NO K
5963 11:17:49.501692 ZQ Calibration : PASS
5964 11:17:49.505031 Jitter Meter : NO K
5965 11:17:49.505142 CBT Training : PASS
5966 11:17:49.508457 Write leveling : PASS
5967 11:17:49.511790 RX DQS gating : PASS
5968 11:17:49.511899 RX DQ/DQS(RDDQC) : PASS
5969 11:17:49.515141 TX DQ/DQS : PASS
5970 11:17:49.518298 RX DATLAT : PASS
5971 11:17:49.518409 RX DQ/DQS(Engine): PASS
5972 11:17:49.521538 TX OE : NO K
5973 11:17:49.521647 All Pass.
5974 11:17:49.521745
5975 11:17:49.524937 CH 1, Rank 0
5976 11:17:49.525045 SW Impedance : PASS
5977 11:17:49.528596 DUTY Scan : NO K
5978 11:17:49.531730 ZQ Calibration : PASS
5979 11:17:49.531837 Jitter Meter : NO K
5980 11:17:49.534711 CBT Training : PASS
5981 11:17:49.538632 Write leveling : PASS
5982 11:17:49.538738 RX DQS gating : PASS
5983 11:17:49.541565 RX DQ/DQS(RDDQC) : PASS
5984 11:17:49.541674 TX DQ/DQS : PASS
5985 11:17:49.544864 RX DATLAT : PASS
5986 11:17:49.548503 RX DQ/DQS(Engine): PASS
5987 11:17:49.548611 TX OE : NO K
5988 11:17:49.551799 All Pass.
5989 11:17:49.551910
5990 11:17:49.552007 CH 1, Rank 1
5991 11:17:49.555210 SW Impedance : PASS
5992 11:17:49.555320 DUTY Scan : NO K
5993 11:17:49.558172 ZQ Calibration : PASS
5994 11:17:49.561906 Jitter Meter : NO K
5995 11:17:49.562017 CBT Training : PASS
5996 11:17:49.565053 Write leveling : PASS
5997 11:17:49.567940 RX DQS gating : PASS
5998 11:17:49.568048 RX DQ/DQS(RDDQC) : PASS
5999 11:17:49.571575 TX DQ/DQS : PASS
6000 11:17:49.574808 RX DATLAT : PASS
6001 11:17:49.574915 RX DQ/DQS(Engine): PASS
6002 11:17:49.578049 TX OE : NO K
6003 11:17:49.578159 All Pass.
6004 11:17:49.578257
6005 11:17:49.581392 DramC Write-DBI off
6006 11:17:49.584459 PER_BANK_REFRESH: Hybrid Mode
6007 11:17:49.584571 TX_TRACKING: ON
6008 11:17:49.594381 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6009 11:17:49.598126 [FAST_K] Save calibration result to emmc
6010 11:17:49.601241 dramc_set_vcore_voltage set vcore to 650000
6011 11:17:49.604341 Read voltage for 400, 6
6012 11:17:49.604450 Vio18 = 0
6013 11:17:49.604549 Vcore = 650000
6014 11:17:49.607516 Vdram = 0
6015 11:17:49.607629 Vddq = 0
6016 11:17:49.607728 Vmddr = 0
6017 11:17:49.614139 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6018 11:17:49.618059 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6019 11:17:49.620875 MEM_TYPE=3, freq_sel=20
6020 11:17:49.624086 sv_algorithm_assistance_LP4_800
6021 11:17:49.627471 ============ PULL DRAM RESETB DOWN ============
6022 11:17:49.631179 ========== PULL DRAM RESETB DOWN end =========
6023 11:17:49.637586 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6024 11:17:49.641129 ===================================
6025 11:17:49.644159 LPDDR4 DRAM CONFIGURATION
6026 11:17:49.647342 ===================================
6027 11:17:49.647450 EX_ROW_EN[0] = 0x0
6028 11:17:49.650503 EX_ROW_EN[1] = 0x0
6029 11:17:49.650611 LP4Y_EN = 0x0
6030 11:17:49.654216 WORK_FSP = 0x0
6031 11:17:49.654325 WL = 0x2
6032 11:17:49.657056 RL = 0x2
6033 11:17:49.657163 BL = 0x2
6034 11:17:49.660737 RPST = 0x0
6035 11:17:49.660865 RD_PRE = 0x0
6036 11:17:49.664250 WR_PRE = 0x1
6037 11:17:49.664359 WR_PST = 0x0
6038 11:17:49.667228 DBI_WR = 0x0
6039 11:17:49.667337 DBI_RD = 0x0
6040 11:17:49.670441 OTF = 0x1
6041 11:17:49.673820 ===================================
6042 11:17:49.677202 ===================================
6043 11:17:49.677312 ANA top config
6044 11:17:49.680428 ===================================
6045 11:17:49.683562 DLL_ASYNC_EN = 0
6046 11:17:49.686869 ALL_SLAVE_EN = 1
6047 11:17:49.690261 NEW_RANK_MODE = 1
6048 11:17:49.693861 DLL_IDLE_MODE = 1
6049 11:17:49.693973 LP45_APHY_COMB_EN = 1
6050 11:17:49.696612 TX_ODT_DIS = 1
6051 11:17:49.700041 NEW_8X_MODE = 1
6052 11:17:49.703313 ===================================
6053 11:17:49.706897 ===================================
6054 11:17:49.710439 data_rate = 800
6055 11:17:49.713649 CKR = 1
6056 11:17:49.713762 DQ_P2S_RATIO = 4
6057 11:17:49.716701 ===================================
6058 11:17:49.719958 CA_P2S_RATIO = 4
6059 11:17:49.723365 DQ_CA_OPEN = 0
6060 11:17:49.727344 DQ_SEMI_OPEN = 1
6061 11:17:49.730793 CA_SEMI_OPEN = 1
6062 11:17:49.733467 CA_FULL_RATE = 0
6063 11:17:49.733578 DQ_CKDIV4_EN = 0
6064 11:17:49.736585 CA_CKDIV4_EN = 1
6065 11:17:49.740065 CA_PREDIV_EN = 0
6066 11:17:49.743552 PH8_DLY = 0
6067 11:17:49.746532 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6068 11:17:49.749762 DQ_AAMCK_DIV = 0
6069 11:17:49.749873 CA_AAMCK_DIV = 0
6070 11:17:49.753369 CA_ADMCK_DIV = 4
6071 11:17:49.756380 DQ_TRACK_CA_EN = 0
6072 11:17:49.759938 CA_PICK = 800
6073 11:17:49.763009 CA_MCKIO = 400
6074 11:17:49.766621 MCKIO_SEMI = 400
6075 11:17:49.769477 PLL_FREQ = 3016
6076 11:17:49.772901 DQ_UI_PI_RATIO = 32
6077 11:17:49.773014 CA_UI_PI_RATIO = 32
6078 11:17:49.776041 ===================================
6079 11:17:49.779447 ===================================
6080 11:17:49.782787 memory_type:LPDDR4
6081 11:17:49.786132 GP_NUM : 10
6082 11:17:49.786242 SRAM_EN : 1
6083 11:17:49.789390 MD32_EN : 0
6084 11:17:49.792888 ===================================
6085 11:17:49.795856 [ANA_INIT] >>>>>>>>>>>>>>
6086 11:17:49.799418 <<<<<< [CONFIGURE PHASE]: ANA_TX
6087 11:17:49.802614 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6088 11:17:49.806127 ===================================
6089 11:17:49.806239 data_rate = 800,PCW = 0X7400
6090 11:17:49.809535 ===================================
6091 11:17:49.812509 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6092 11:17:49.819318 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6093 11:17:49.832391 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6094 11:17:49.835532 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6095 11:17:49.839037 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6096 11:17:49.841955 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6097 11:17:49.845234 [ANA_INIT] flow start
6098 11:17:49.845344 [ANA_INIT] PLL >>>>>>>>
6099 11:17:49.848757 [ANA_INIT] PLL <<<<<<<<
6100 11:17:49.852054 [ANA_INIT] MIDPI >>>>>>>>
6101 11:17:49.855391 [ANA_INIT] MIDPI <<<<<<<<
6102 11:17:49.855501 [ANA_INIT] DLL >>>>>>>>
6103 11:17:49.858511 [ANA_INIT] flow end
6104 11:17:49.861784 ============ LP4 DIFF to SE enter ============
6105 11:17:49.865034 ============ LP4 DIFF to SE exit ============
6106 11:17:49.868448 [ANA_INIT] <<<<<<<<<<<<<
6107 11:17:49.871799 [Flow] Enable top DCM control >>>>>
6108 11:17:49.874982 [Flow] Enable top DCM control <<<<<
6109 11:17:49.878234 Enable DLL master slave shuffle
6110 11:17:49.884952 ==============================================================
6111 11:17:49.885067 Gating Mode config
6112 11:17:49.891555 ==============================================================
6113 11:17:49.891669 Config description:
6114 11:17:49.901222 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6115 11:17:49.907980 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6116 11:17:49.914720 SELPH_MODE 0: By rank 1: By Phase
6117 11:17:49.918033 ==============================================================
6118 11:17:49.921061 GAT_TRACK_EN = 0
6119 11:17:49.924543 RX_GATING_MODE = 2
6120 11:17:49.927579 RX_GATING_TRACK_MODE = 2
6121 11:17:49.930784 SELPH_MODE = 1
6122 11:17:49.934642 PICG_EARLY_EN = 1
6123 11:17:49.937413 VALID_LAT_VALUE = 1
6124 11:17:49.943990 ==============================================================
6125 11:17:49.947930 Enter into Gating configuration >>>>
6126 11:17:49.950930 Exit from Gating configuration <<<<
6127 11:17:49.954130 Enter into DVFS_PRE_config >>>>>
6128 11:17:49.964124 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6129 11:17:49.967329 Exit from DVFS_PRE_config <<<<<
6130 11:17:49.970853 Enter into PICG configuration >>>>
6131 11:17:49.973771 Exit from PICG configuration <<<<
6132 11:17:49.977466 [RX_INPUT] configuration >>>>>
6133 11:17:49.977579 [RX_INPUT] configuration <<<<<
6134 11:17:49.984219 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6135 11:17:49.990412 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6136 11:17:49.993686 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6137 11:17:50.000254 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6138 11:17:50.007171 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6139 11:17:50.013739 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6140 11:17:50.016900 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6141 11:17:50.020082 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6142 11:17:50.026882 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6143 11:17:50.030091 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6144 11:17:50.033269 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6145 11:17:50.040380 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6146 11:17:50.043539 ===================================
6147 11:17:50.043650 LPDDR4 DRAM CONFIGURATION
6148 11:17:50.046849 ===================================
6149 11:17:50.050295 EX_ROW_EN[0] = 0x0
6150 11:17:50.053180 EX_ROW_EN[1] = 0x0
6151 11:17:50.053288 LP4Y_EN = 0x0
6152 11:17:50.056893 WORK_FSP = 0x0
6153 11:17:50.057006 WL = 0x2
6154 11:17:50.059794 RL = 0x2
6155 11:17:50.059904 BL = 0x2
6156 11:17:50.062985 RPST = 0x0
6157 11:17:50.063092 RD_PRE = 0x0
6158 11:17:50.066438 WR_PRE = 0x1
6159 11:17:50.066548 WR_PST = 0x0
6160 11:17:50.069982 DBI_WR = 0x0
6161 11:17:50.070091 DBI_RD = 0x0
6162 11:17:50.073090 OTF = 0x1
6163 11:17:50.076264 ===================================
6164 11:17:50.079673 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6165 11:17:50.083197 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6166 11:17:50.089629 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6167 11:17:50.092618 ===================================
6168 11:17:50.092729 LPDDR4 DRAM CONFIGURATION
6169 11:17:50.096004 ===================================
6170 11:17:50.099567 EX_ROW_EN[0] = 0x10
6171 11:17:50.102772 EX_ROW_EN[1] = 0x0
6172 11:17:50.102880 LP4Y_EN = 0x0
6173 11:17:50.106006 WORK_FSP = 0x0
6174 11:17:50.106117 WL = 0x2
6175 11:17:50.109228 RL = 0x2
6176 11:17:50.109336 BL = 0x2
6177 11:17:50.113042 RPST = 0x0
6178 11:17:50.113150 RD_PRE = 0x0
6179 11:17:50.115865 WR_PRE = 0x1
6180 11:17:50.115974 WR_PST = 0x0
6181 11:17:50.119476 DBI_WR = 0x0
6182 11:17:50.119583 DBI_RD = 0x0
6183 11:17:50.122836 OTF = 0x1
6184 11:17:50.125904 ===================================
6185 11:17:50.132566 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6186 11:17:50.136179 nWR fixed to 30
6187 11:17:50.136290 [ModeRegInit_LP4] CH0 RK0
6188 11:17:50.139102 [ModeRegInit_LP4] CH0 RK1
6189 11:17:50.142332 [ModeRegInit_LP4] CH1 RK0
6190 11:17:50.145722 [ModeRegInit_LP4] CH1 RK1
6191 11:17:50.145832 match AC timing 19
6192 11:17:50.149163 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6193 11:17:50.155883 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6194 11:17:50.159032 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6195 11:17:50.162371 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6196 11:17:50.169144 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6197 11:17:50.169265 ==
6198 11:17:50.172272 Dram Type= 6, Freq= 0, CH_0, rank 0
6199 11:17:50.175919 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6200 11:17:50.176031 ==
6201 11:17:50.182438 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6202 11:17:50.189119 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6203 11:17:50.192377 [CA 0] Center 36 (8~64) winsize 57
6204 11:17:50.192488 [CA 1] Center 36 (8~64) winsize 57
6205 11:17:50.195660 [CA 2] Center 36 (8~64) winsize 57
6206 11:17:50.198691 [CA 3] Center 36 (8~64) winsize 57
6207 11:17:50.202191 [CA 4] Center 36 (8~64) winsize 57
6208 11:17:50.205577 [CA 5] Center 36 (8~64) winsize 57
6209 11:17:50.205687
6210 11:17:50.208478 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6211 11:17:50.208587
6212 11:17:50.215199 [CATrainingPosCal] consider 1 rank data
6213 11:17:50.215312 u2DelayCellTimex100 = 270/100 ps
6214 11:17:50.218723 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6215 11:17:50.225016 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6216 11:17:50.228462 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6217 11:17:50.231899 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6218 11:17:50.235221 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6219 11:17:50.238373 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6220 11:17:50.238484
6221 11:17:50.242079 CA PerBit enable=1, Macro0, CA PI delay=36
6222 11:17:50.242187
6223 11:17:50.245162 [CBTSetCACLKResult] CA Dly = 36
6224 11:17:50.248442 CS Dly: 1 (0~32)
6225 11:17:50.248552 ==
6226 11:17:50.251708 Dram Type= 6, Freq= 0, CH_0, rank 1
6227 11:17:50.254926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6228 11:17:50.255039 ==
6229 11:17:50.262160 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6230 11:17:50.264751 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6231 11:17:50.268518 [CA 0] Center 36 (8~64) winsize 57
6232 11:17:50.271381 [CA 1] Center 36 (8~64) winsize 57
6233 11:17:50.274698 [CA 2] Center 36 (8~64) winsize 57
6234 11:17:50.278302 [CA 3] Center 36 (8~64) winsize 57
6235 11:17:50.281245 [CA 4] Center 36 (8~64) winsize 57
6236 11:17:50.284751 [CA 5] Center 36 (8~64) winsize 57
6237 11:17:50.284893
6238 11:17:50.288068 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6239 11:17:50.288179
6240 11:17:50.291210 [CATrainingPosCal] consider 2 rank data
6241 11:17:50.294432 u2DelayCellTimex100 = 270/100 ps
6242 11:17:50.298298 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 11:17:50.301422 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 11:17:50.307796 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 11:17:50.311085 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 11:17:50.314297 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 11:17:50.317712 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6248 11:17:50.317824
6249 11:17:50.320951 CA PerBit enable=1, Macro0, CA PI delay=36
6250 11:17:50.321060
6251 11:17:50.324224 [CBTSetCACLKResult] CA Dly = 36
6252 11:17:50.324333 CS Dly: 1 (0~32)
6253 11:17:50.324433
6254 11:17:50.327790 ----->DramcWriteLeveling(PI) begin...
6255 11:17:50.330815 ==
6256 11:17:50.334249 Dram Type= 6, Freq= 0, CH_0, rank 0
6257 11:17:50.338306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6258 11:17:50.338419 ==
6259 11:17:50.340890 Write leveling (Byte 0): 40 => 8
6260 11:17:50.344268 Write leveling (Byte 1): 32 => 0
6261 11:17:50.347332 DramcWriteLeveling(PI) end<-----
6262 11:17:50.347443
6263 11:17:50.347540 ==
6264 11:17:50.351093 Dram Type= 6, Freq= 0, CH_0, rank 0
6265 11:17:50.354065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6266 11:17:50.354174 ==
6267 11:17:50.357194 [Gating] SW mode calibration
6268 11:17:50.363854 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6269 11:17:50.370721 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6270 11:17:50.373730 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6271 11:17:50.377285 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6272 11:17:50.383809 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6273 11:17:50.387128 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6274 11:17:50.390732 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6275 11:17:50.396710 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6276 11:17:50.400106 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6277 11:17:50.403491 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6278 11:17:50.410092 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6279 11:17:50.410211 Total UI for P1: 0, mck2ui 16
6280 11:17:50.413206 best dqsien dly found for B0: ( 0, 14, 24)
6281 11:17:50.416701 Total UI for P1: 0, mck2ui 16
6282 11:17:50.420010 best dqsien dly found for B1: ( 0, 14, 24)
6283 11:17:50.426879 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6284 11:17:50.429894 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6285 11:17:50.430004
6286 11:17:50.433479 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6287 11:17:50.436504 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6288 11:17:50.440058 [Gating] SW calibration Done
6289 11:17:50.440168 ==
6290 11:17:50.443255 Dram Type= 6, Freq= 0, CH_0, rank 0
6291 11:17:50.446422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6292 11:17:50.446534 ==
6293 11:17:50.449997 RX Vref Scan: 0
6294 11:17:50.450107
6295 11:17:50.450205 RX Vref 0 -> 0, step: 1
6296 11:17:50.450304
6297 11:17:50.453402 RX Delay -410 -> 252, step: 16
6298 11:17:50.459708 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6299 11:17:50.462986 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6300 11:17:50.466136 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6301 11:17:50.469623 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6302 11:17:50.476062 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6303 11:17:50.479100 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6304 11:17:50.482586 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6305 11:17:50.485601 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6306 11:17:50.492272 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6307 11:17:50.495836 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6308 11:17:50.499106 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6309 11:17:50.502190 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6310 11:17:50.508732 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6311 11:17:50.512019 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6312 11:17:50.515680 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6313 11:17:50.522233 iDelay=230, Bit 15, Center -27 (-266 ~ 213) 480
6314 11:17:50.522345 ==
6315 11:17:50.525559 Dram Type= 6, Freq= 0, CH_0, rank 0
6316 11:17:50.529009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6317 11:17:50.529118 ==
6318 11:17:50.529214 DQS Delay:
6319 11:17:50.532297 DQS0 = 27, DQS1 = 35
6320 11:17:50.532406 DQM Delay:
6321 11:17:50.535665 DQM0 = 11, DQM1 = 6
6322 11:17:50.535772 DQ Delay:
6323 11:17:50.538706 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =0
6324 11:17:50.541942 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6325 11:17:50.545489 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6326 11:17:50.548731 DQ12 =8, DQ13 =8, DQ14 =16, DQ15 =8
6327 11:17:50.548863
6328 11:17:50.548962
6329 11:17:50.549055 ==
6330 11:17:50.552032 Dram Type= 6, Freq= 0, CH_0, rank 0
6331 11:17:50.555034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6332 11:17:50.555145 ==
6333 11:17:50.555245
6334 11:17:50.555343
6335 11:17:50.558302 TX Vref Scan disable
6336 11:17:50.558408 == TX Byte 0 ==
6337 11:17:50.565044 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6338 11:17:50.568349 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6339 11:17:50.568469 == TX Byte 1 ==
6340 11:17:50.574750 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6341 11:17:50.578467 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6342 11:17:50.578583 ==
6343 11:17:50.581337 Dram Type= 6, Freq= 0, CH_0, rank 0
6344 11:17:50.585276 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6345 11:17:50.585391 ==
6346 11:17:50.585492
6347 11:17:50.585593
6348 11:17:50.587983 TX Vref Scan disable
6349 11:17:50.591550 == TX Byte 0 ==
6350 11:17:50.594613 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6351 11:17:50.598267 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6352 11:17:50.601246 == TX Byte 1 ==
6353 11:17:50.604555 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6354 11:17:50.607624 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6355 11:17:50.607737
6356 11:17:50.607834 [DATLAT]
6357 11:17:50.611024 Freq=400, CH0 RK0
6358 11:17:50.611134
6359 11:17:50.614230 DATLAT Default: 0xf
6360 11:17:50.614343 0, 0xFFFF, sum = 0
6361 11:17:50.617887 1, 0xFFFF, sum = 0
6362 11:17:50.618030 2, 0xFFFF, sum = 0
6363 11:17:50.621007 3, 0xFFFF, sum = 0
6364 11:17:50.621115 4, 0xFFFF, sum = 0
6365 11:17:50.624230 5, 0xFFFF, sum = 0
6366 11:17:50.624343 6, 0xFFFF, sum = 0
6367 11:17:50.627460 7, 0xFFFF, sum = 0
6368 11:17:50.627574 8, 0xFFFF, sum = 0
6369 11:17:50.631218 9, 0xFFFF, sum = 0
6370 11:17:50.631328 10, 0xFFFF, sum = 0
6371 11:17:50.634308 11, 0xFFFF, sum = 0
6372 11:17:50.634419 12, 0xFFFF, sum = 0
6373 11:17:50.637295 13, 0x0, sum = 1
6374 11:17:50.637405 14, 0x0, sum = 2
6375 11:17:50.640684 15, 0x0, sum = 3
6376 11:17:50.640833 16, 0x0, sum = 4
6377 11:17:50.644292 best_step = 14
6378 11:17:50.644401
6379 11:17:50.644499 ==
6380 11:17:50.647691 Dram Type= 6, Freq= 0, CH_0, rank 0
6381 11:17:50.650633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6382 11:17:50.650745 ==
6383 11:17:50.654012 RX Vref Scan: 1
6384 11:17:50.654120
6385 11:17:50.654221 RX Vref 0 -> 0, step: 1
6386 11:17:50.654317
6387 11:17:50.657230 RX Delay -311 -> 252, step: 8
6388 11:17:50.657341
6389 11:17:50.660769 Set Vref, RX VrefLevel [Byte0]: 57
6390 11:17:50.663957 [Byte1]: 49
6391 11:17:50.668369
6392 11:17:50.668481 Final RX Vref Byte 0 = 57 to rank0
6393 11:17:50.671796 Final RX Vref Byte 1 = 49 to rank0
6394 11:17:50.675196 Final RX Vref Byte 0 = 57 to rank1
6395 11:17:50.678393 Final RX Vref Byte 1 = 49 to rank1==
6396 11:17:50.681504 Dram Type= 6, Freq= 0, CH_0, rank 0
6397 11:17:50.688130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6398 11:17:50.688245 ==
6399 11:17:50.688343 DQS Delay:
6400 11:17:50.691519 DQS0 = 24, DQS1 = 48
6401 11:17:50.691628 DQM Delay:
6402 11:17:50.691727 DQM0 = 9, DQM1 = 15
6403 11:17:50.694701 DQ Delay:
6404 11:17:50.697907 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =4
6405 11:17:50.698020 DQ4 =8, DQ5 =0, DQ6 =20, DQ7 =16
6406 11:17:50.701448 DQ8 =8, DQ9 =0, DQ10 =12, DQ11 =12
6407 11:17:50.704944 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6408 11:17:50.707877
6409 11:17:50.707990
6410 11:17:50.714660 [DQSOSCAuto] RK0, (LSB)MR18= 0xa59d, (MSB)MR19= 0xc0c, tDQSOscB0 = 390 ps tDQSOscB1 = 389 ps
6411 11:17:50.718286 CH0 RK0: MR19=C0C, MR18=A59D
6412 11:17:50.724630 CH0_RK0: MR19=0xC0C, MR18=0xA59D, DQSOSC=389, MR23=63, INC=390, DEC=260
6413 11:17:50.724745 ==
6414 11:17:50.727660 Dram Type= 6, Freq= 0, CH_0, rank 1
6415 11:17:50.730998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6416 11:17:50.731111 ==
6417 11:17:50.734395 [Gating] SW mode calibration
6418 11:17:50.741237 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6419 11:17:50.747778 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6420 11:17:50.750644 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6421 11:17:50.754405 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6422 11:17:50.760969 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6423 11:17:50.764336 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6424 11:17:50.767284 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6425 11:17:50.773997 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6426 11:17:50.777125 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6427 11:17:50.780851 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6428 11:17:50.787328 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6429 11:17:50.787441 Total UI for P1: 0, mck2ui 16
6430 11:17:50.793744 best dqsien dly found for B0: ( 0, 14, 24)
6431 11:17:50.793858 Total UI for P1: 0, mck2ui 16
6432 11:17:50.800411 best dqsien dly found for B1: ( 0, 14, 24)
6433 11:17:50.803685 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6434 11:17:50.806817 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6435 11:17:50.806930
6436 11:17:50.810248 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6437 11:17:50.813802 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6438 11:17:50.816696 [Gating] SW calibration Done
6439 11:17:50.816800 ==
6440 11:17:50.820181 Dram Type= 6, Freq= 0, CH_0, rank 1
6441 11:17:50.823319 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6442 11:17:50.823402 ==
6443 11:17:50.826781 RX Vref Scan: 0
6444 11:17:50.826866
6445 11:17:50.826932 RX Vref 0 -> 0, step: 1
6446 11:17:50.830030
6447 11:17:50.830104 RX Delay -410 -> 252, step: 16
6448 11:17:50.836857 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6449 11:17:50.839994 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6450 11:17:50.843576 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6451 11:17:50.846444 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6452 11:17:50.853109 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6453 11:17:50.856665 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6454 11:17:50.859589 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6455 11:17:50.862964 iDelay=230, Bit 7, Center -11 (-250 ~ 229) 480
6456 11:17:50.869765 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6457 11:17:50.872747 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6458 11:17:50.876299 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6459 11:17:50.882886 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6460 11:17:50.885970 iDelay=230, Bit 12, Center -27 (-266 ~ 213) 480
6461 11:17:50.889286 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6462 11:17:50.893006 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6463 11:17:50.899336 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6464 11:17:50.899423 ==
6465 11:17:50.902594 Dram Type= 6, Freq= 0, CH_0, rank 1
6466 11:17:50.905984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6467 11:17:50.906068 ==
6468 11:17:50.906135 DQS Delay:
6469 11:17:50.909259 DQS0 = 27, DQS1 = 43
6470 11:17:50.909342 DQM Delay:
6471 11:17:50.912788 DQM0 = 10, DQM1 = 15
6472 11:17:50.912885 DQ Delay:
6473 11:17:50.915866 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6474 11:17:50.919259 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =16
6475 11:17:50.922738 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6476 11:17:50.925830 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6477 11:17:50.925913
6478 11:17:50.925978
6479 11:17:50.926037 ==
6480 11:17:50.929662 Dram Type= 6, Freq= 0, CH_0, rank 1
6481 11:17:50.932631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6482 11:17:50.932744 ==
6483 11:17:50.932853
6484 11:17:50.932915
6485 11:17:50.935729 TX Vref Scan disable
6486 11:17:50.935810 == TX Byte 0 ==
6487 11:17:50.942428 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6488 11:17:50.945402 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6489 11:17:50.945487 == TX Byte 1 ==
6490 11:17:50.952084 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6491 11:17:50.955816 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6492 11:17:50.955900 ==
6493 11:17:50.958991 Dram Type= 6, Freq= 0, CH_0, rank 1
6494 11:17:50.961995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6495 11:17:50.962079 ==
6496 11:17:50.962144
6497 11:17:50.962230
6498 11:17:50.965468 TX Vref Scan disable
6499 11:17:50.969024 == TX Byte 0 ==
6500 11:17:50.972327 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6501 11:17:50.975443 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6502 11:17:50.978711 == TX Byte 1 ==
6503 11:17:50.981885 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6504 11:17:50.985463 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6505 11:17:50.985546
6506 11:17:50.985610 [DATLAT]
6507 11:17:50.988681 Freq=400, CH0 RK1
6508 11:17:50.988822
6509 11:17:50.988889 DATLAT Default: 0xe
6510 11:17:50.992159 0, 0xFFFF, sum = 0
6511 11:17:50.992269 1, 0xFFFF, sum = 0
6512 11:17:50.995700 2, 0xFFFF, sum = 0
6513 11:17:50.995783 3, 0xFFFF, sum = 0
6514 11:17:50.998768 4, 0xFFFF, sum = 0
6515 11:17:51.001885 5, 0xFFFF, sum = 0
6516 11:17:51.001968 6, 0xFFFF, sum = 0
6517 11:17:51.005416 7, 0xFFFF, sum = 0
6518 11:17:51.005499 8, 0xFFFF, sum = 0
6519 11:17:51.008604 9, 0xFFFF, sum = 0
6520 11:17:51.008721 10, 0xFFFF, sum = 0
6521 11:17:51.012044 11, 0xFFFF, sum = 0
6522 11:17:51.012127 12, 0xFFFF, sum = 0
6523 11:17:51.015178 13, 0x0, sum = 1
6524 11:17:51.015261 14, 0x0, sum = 2
6525 11:17:51.018598 15, 0x0, sum = 3
6526 11:17:51.018681 16, 0x0, sum = 4
6527 11:17:51.021764 best_step = 14
6528 11:17:51.021847
6529 11:17:51.021912 ==
6530 11:17:51.025208 Dram Type= 6, Freq= 0, CH_0, rank 1
6531 11:17:51.029026 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6532 11:17:51.029109 ==
6533 11:17:51.029175 RX Vref Scan: 0
6534 11:17:51.031940
6535 11:17:51.032022 RX Vref 0 -> 0, step: 1
6536 11:17:51.032087
6537 11:17:51.034840 RX Delay -327 -> 252, step: 8
6538 11:17:51.042701 iDelay=217, Bit 0, Center -20 (-247 ~ 208) 456
6539 11:17:51.045472 iDelay=217, Bit 1, Center -16 (-239 ~ 208) 448
6540 11:17:51.048892 iDelay=217, Bit 2, Center -20 (-239 ~ 200) 440
6541 11:17:51.055235 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6542 11:17:51.058804 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6543 11:17:51.061940 iDelay=217, Bit 5, Center -28 (-255 ~ 200) 456
6544 11:17:51.065332 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
6545 11:17:51.068655 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6546 11:17:51.075130 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6547 11:17:51.078411 iDelay=217, Bit 9, Center -44 (-271 ~ 184) 456
6548 11:17:51.081884 iDelay=217, Bit 10, Center -28 (-255 ~ 200) 456
6549 11:17:51.088458 iDelay=217, Bit 11, Center -32 (-255 ~ 192) 448
6550 11:17:51.091592 iDelay=217, Bit 12, Center -24 (-247 ~ 200) 448
6551 11:17:51.094691 iDelay=217, Bit 13, Center -24 (-247 ~ 200) 448
6552 11:17:51.098262 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
6553 11:17:51.104757 iDelay=217, Bit 15, Center -20 (-239 ~ 200) 440
6554 11:17:51.104879 ==
6555 11:17:51.107937 Dram Type= 6, Freq= 0, CH_0, rank 1
6556 11:17:51.111357 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6557 11:17:51.111441 ==
6558 11:17:51.111506 DQS Delay:
6559 11:17:51.114980 DQS0 = 28, DQS1 = 44
6560 11:17:51.115063 DQM Delay:
6561 11:17:51.118319 DQM0 = 11, DQM1 = 16
6562 11:17:51.118401 DQ Delay:
6563 11:17:51.121751 DQ0 =8, DQ1 =12, DQ2 =8, DQ3 =8
6564 11:17:51.124638 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6565 11:17:51.127803 DQ8 =12, DQ9 =0, DQ10 =16, DQ11 =12
6566 11:17:51.131227 DQ12 =20, DQ13 =20, DQ14 =28, DQ15 =24
6567 11:17:51.131311
6568 11:17:51.131376
6569 11:17:51.141019 [DQSOSCAuto] RK1, (LSB)MR18= 0xba6f, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 386 ps
6570 11:17:51.141137 CH0 RK1: MR19=C0C, MR18=BA6F
6571 11:17:51.147942 CH0_RK1: MR19=0xC0C, MR18=0xBA6F, DQSOSC=386, MR23=63, INC=396, DEC=264
6572 11:17:51.150881 [RxdqsGatingPostProcess] freq 400
6573 11:17:51.157814 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6574 11:17:51.161152 best DQS0 dly(2T, 0.5T) = (0, 10)
6575 11:17:51.164427 best DQS1 dly(2T, 0.5T) = (0, 10)
6576 11:17:51.168021 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6577 11:17:51.171007 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6578 11:17:51.174444 best DQS0 dly(2T, 0.5T) = (0, 10)
6579 11:17:51.174526 best DQS1 dly(2T, 0.5T) = (0, 10)
6580 11:17:51.177677 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6581 11:17:51.180826 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6582 11:17:51.184228 Pre-setting of DQS Precalculation
6583 11:17:51.190807 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6584 11:17:51.190894 ==
6585 11:17:51.194117 Dram Type= 6, Freq= 0, CH_1, rank 0
6586 11:17:51.197272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6587 11:17:51.197355 ==
6588 11:17:51.203971 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6589 11:17:51.210868 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6590 11:17:51.213739 [CA 0] Center 36 (8~64) winsize 57
6591 11:17:51.217064 [CA 1] Center 36 (8~64) winsize 57
6592 11:17:51.220351 [CA 2] Center 36 (8~64) winsize 57
6593 11:17:51.220434 [CA 3] Center 36 (8~64) winsize 57
6594 11:17:51.223482 [CA 4] Center 36 (8~64) winsize 57
6595 11:17:51.227304 [CA 5] Center 36 (8~64) winsize 57
6596 11:17:51.227387
6597 11:17:51.233645 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6598 11:17:51.233731
6599 11:17:51.236971 [CATrainingPosCal] consider 1 rank data
6600 11:17:51.240150 u2DelayCellTimex100 = 270/100 ps
6601 11:17:51.243337 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6602 11:17:51.246550 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6603 11:17:51.250035 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6604 11:17:51.253559 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6605 11:17:51.256758 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6606 11:17:51.260094 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6607 11:17:51.260176
6608 11:17:51.263211 CA PerBit enable=1, Macro0, CA PI delay=36
6609 11:17:51.263327
6610 11:17:51.266582 [CBTSetCACLKResult] CA Dly = 36
6611 11:17:51.269920 CS Dly: 1 (0~32)
6612 11:17:51.270002 ==
6613 11:17:51.273389 Dram Type= 6, Freq= 0, CH_1, rank 1
6614 11:17:51.276298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6615 11:17:51.276380 ==
6616 11:17:51.282859 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6617 11:17:51.289801 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6618 11:17:51.292865 [CA 0] Center 36 (8~64) winsize 57
6619 11:17:51.292981 [CA 1] Center 36 (8~64) winsize 57
6620 11:17:51.296286 [CA 2] Center 36 (8~64) winsize 57
6621 11:17:51.299469 [CA 3] Center 36 (8~64) winsize 57
6622 11:17:51.302975 [CA 4] Center 36 (8~64) winsize 57
6623 11:17:51.306094 [CA 5] Center 36 (8~64) winsize 57
6624 11:17:51.306200
6625 11:17:51.309234 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6626 11:17:51.309322
6627 11:17:51.315951 [CATrainingPosCal] consider 2 rank data
6628 11:17:51.316032 u2DelayCellTimex100 = 270/100 ps
6629 11:17:51.322376 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 11:17:51.325753 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 11:17:51.328933 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 11:17:51.332772 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 11:17:51.335591 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 11:17:51.339050 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6635 11:17:51.339144
6636 11:17:51.342486 CA PerBit enable=1, Macro0, CA PI delay=36
6637 11:17:51.342563
6638 11:17:51.345860 [CBTSetCACLKResult] CA Dly = 36
6639 11:17:51.348880 CS Dly: 1 (0~32)
6640 11:17:51.349003
6641 11:17:51.352062 ----->DramcWriteLeveling(PI) begin...
6642 11:17:51.352138 ==
6643 11:17:51.355588 Dram Type= 6, Freq= 0, CH_1, rank 0
6644 11:17:51.358747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6645 11:17:51.358847 ==
6646 11:17:51.362424 Write leveling (Byte 0): 40 => 8
6647 11:17:51.365185 Write leveling (Byte 1): 32 => 0
6648 11:17:51.368503 DramcWriteLeveling(PI) end<-----
6649 11:17:51.368613
6650 11:17:51.368708 ==
6651 11:17:51.372127 Dram Type= 6, Freq= 0, CH_1, rank 0
6652 11:17:51.375834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6653 11:17:51.375922 ==
6654 11:17:51.378500 [Gating] SW mode calibration
6655 11:17:51.384979 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6656 11:17:51.391797 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6657 11:17:51.395265 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6658 11:17:51.398683 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6659 11:17:51.404953 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6660 11:17:51.408391 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6661 11:17:51.411834 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6662 11:17:51.418267 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6663 11:17:51.421810 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6664 11:17:51.424941 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6665 11:17:51.431613 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6666 11:17:51.434992 Total UI for P1: 0, mck2ui 16
6667 11:17:51.438010 best dqsien dly found for B0: ( 0, 14, 24)
6668 11:17:51.438094 Total UI for P1: 0, mck2ui 16
6669 11:17:51.444684 best dqsien dly found for B1: ( 0, 14, 24)
6670 11:17:51.448171 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6671 11:17:51.451382 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6672 11:17:51.451468
6673 11:17:51.454697 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6674 11:17:51.457866 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6675 11:17:51.461267 [Gating] SW calibration Done
6676 11:17:51.461353 ==
6677 11:17:51.464682 Dram Type= 6, Freq= 0, CH_1, rank 0
6678 11:17:51.468360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6679 11:17:51.468448 ==
6680 11:17:51.471351 RX Vref Scan: 0
6681 11:17:51.471463
6682 11:17:51.471534 RX Vref 0 -> 0, step: 1
6683 11:17:51.475133
6684 11:17:51.475219 RX Delay -410 -> 252, step: 16
6685 11:17:51.481274 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6686 11:17:51.484445 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6687 11:17:51.488118 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6688 11:17:51.491242 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6689 11:17:51.497495 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6690 11:17:51.501182 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6691 11:17:51.504348 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6692 11:17:51.507691 iDelay=230, Bit 7, Center -27 (-266 ~ 213) 480
6693 11:17:51.514154 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6694 11:17:51.517462 iDelay=230, Bit 9, Center -43 (-282 ~ 197) 480
6695 11:17:51.520665 iDelay=230, Bit 10, Center -27 (-266 ~ 213) 480
6696 11:17:51.527358 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6697 11:17:51.530553 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6698 11:17:51.533956 iDelay=230, Bit 13, Center -27 (-266 ~ 213) 480
6699 11:17:51.537131 iDelay=230, Bit 14, Center -27 (-266 ~ 213) 480
6700 11:17:51.543939 iDelay=230, Bit 15, Center -19 (-266 ~ 229) 496
6701 11:17:51.544020 ==
6702 11:17:51.547125 Dram Type= 6, Freq= 0, CH_1, rank 0
6703 11:17:51.550452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6704 11:17:51.550538 ==
6705 11:17:51.550605 DQS Delay:
6706 11:17:51.553809 DQS0 = 27, DQS1 = 43
6707 11:17:51.553893 DQM Delay:
6708 11:17:51.557241 DQM0 = 7, DQM1 = 15
6709 11:17:51.557325 DQ Delay:
6710 11:17:51.560282 DQ0 =8, DQ1 =0, DQ2 =0, DQ3 =8
6711 11:17:51.563510 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =0
6712 11:17:51.567130 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6713 11:17:51.570078 DQ12 =32, DQ13 =16, DQ14 =16, DQ15 =24
6714 11:17:51.570164
6715 11:17:51.570234
6716 11:17:51.570298 ==
6717 11:17:51.573497 Dram Type= 6, Freq= 0, CH_1, rank 0
6718 11:17:51.576745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6719 11:17:51.576855 ==
6720 11:17:51.576950
6721 11:17:51.577039
6722 11:17:51.580043 TX Vref Scan disable
6723 11:17:51.583613 == TX Byte 0 ==
6724 11:17:51.586903 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6725 11:17:51.589837 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6726 11:17:51.593042 == TX Byte 1 ==
6727 11:17:51.596400 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6728 11:17:51.600069 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6729 11:17:51.600156 ==
6730 11:17:51.603367 Dram Type= 6, Freq= 0, CH_1, rank 0
6731 11:17:51.606397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6732 11:17:51.609859 ==
6733 11:17:51.609937
6734 11:17:51.610001
6735 11:17:51.610060 TX Vref Scan disable
6736 11:17:51.613397 == TX Byte 0 ==
6737 11:17:51.616756 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6738 11:17:51.619957 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6739 11:17:51.622955 == TX Byte 1 ==
6740 11:17:51.626137 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6741 11:17:51.629509 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6742 11:17:51.629590
6743 11:17:51.632681 [DATLAT]
6744 11:17:51.632753 Freq=400, CH1 RK0
6745 11:17:51.632829
6746 11:17:51.635853 DATLAT Default: 0xf
6747 11:17:51.635954 0, 0xFFFF, sum = 0
6748 11:17:51.639506 1, 0xFFFF, sum = 0
6749 11:17:51.639583 2, 0xFFFF, sum = 0
6750 11:17:51.642442 3, 0xFFFF, sum = 0
6751 11:17:51.642529 4, 0xFFFF, sum = 0
6752 11:17:51.646209 5, 0xFFFF, sum = 0
6753 11:17:51.646295 6, 0xFFFF, sum = 0
6754 11:17:51.649316 7, 0xFFFF, sum = 0
6755 11:17:51.649402 8, 0xFFFF, sum = 0
6756 11:17:51.652681 9, 0xFFFF, sum = 0
6757 11:17:51.655856 10, 0xFFFF, sum = 0
6758 11:17:51.655943 11, 0xFFFF, sum = 0
6759 11:17:51.659393 12, 0xFFFF, sum = 0
6760 11:17:51.659479 13, 0x0, sum = 1
6761 11:17:51.662427 14, 0x0, sum = 2
6762 11:17:51.662512 15, 0x0, sum = 3
6763 11:17:51.665764 16, 0x0, sum = 4
6764 11:17:51.665854 best_step = 14
6765 11:17:51.665920
6766 11:17:51.665982 ==
6767 11:17:51.669487 Dram Type= 6, Freq= 0, CH_1, rank 0
6768 11:17:51.672246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6769 11:17:51.672332 ==
6770 11:17:51.675629 RX Vref Scan: 1
6771 11:17:51.675720
6772 11:17:51.678614 RX Vref 0 -> 0, step: 1
6773 11:17:51.678698
6774 11:17:51.678765 RX Delay -327 -> 252, step: 8
6775 11:17:51.682091
6776 11:17:51.682175 Set Vref, RX VrefLevel [Byte0]: 51
6777 11:17:51.685504 [Byte1]: 52
6778 11:17:51.691243
6779 11:17:51.691331 Final RX Vref Byte 0 = 51 to rank0
6780 11:17:51.694256 Final RX Vref Byte 1 = 52 to rank0
6781 11:17:51.697518 Final RX Vref Byte 0 = 51 to rank1
6782 11:17:51.701164 Final RX Vref Byte 1 = 52 to rank1==
6783 11:17:51.703979 Dram Type= 6, Freq= 0, CH_1, rank 0
6784 11:17:51.711031 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6785 11:17:51.711125 ==
6786 11:17:51.711194 DQS Delay:
6787 11:17:51.714089 DQS0 = 32, DQS1 = 40
6788 11:17:51.714173 DQM Delay:
6789 11:17:51.714239 DQM0 = 12, DQM1 = 11
6790 11:17:51.717565 DQ Delay:
6791 11:17:51.720923 DQ0 =20, DQ1 =8, DQ2 =0, DQ3 =8
6792 11:17:51.721009 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =8
6793 11:17:51.724002 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6794 11:17:51.727415 DQ12 =20, DQ13 =20, DQ14 =16, DQ15 =16
6795 11:17:51.730431
6796 11:17:51.730516
6797 11:17:51.737136 [DQSOSCAuto] RK0, (LSB)MR18= 0x96d1, (MSB)MR19= 0xc0c, tDQSOscB0 = 384 ps tDQSOscB1 = 391 ps
6798 11:17:51.740349 CH1 RK0: MR19=C0C, MR18=96D1
6799 11:17:51.747317 CH1_RK0: MR19=0xC0C, MR18=0x96D1, DQSOSC=384, MR23=63, INC=400, DEC=267
6800 11:17:51.747409 ==
6801 11:17:51.750503 Dram Type= 6, Freq= 0, CH_1, rank 1
6802 11:17:51.753662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6803 11:17:51.753765 ==
6804 11:17:51.757100 [Gating] SW mode calibration
6805 11:17:51.763883 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6806 11:17:51.770070 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6807 11:17:51.773482 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6808 11:17:51.777271 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6809 11:17:51.783873 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6810 11:17:51.786807 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6811 11:17:51.790200 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6812 11:17:51.796898 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6813 11:17:51.800406 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6814 11:17:51.803239 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6815 11:17:51.809742 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6816 11:17:51.809839 Total UI for P1: 0, mck2ui 16
6817 11:17:51.816593 best dqsien dly found for B0: ( 0, 14, 24)
6818 11:17:51.816700 Total UI for P1: 0, mck2ui 16
6819 11:17:51.819827 best dqsien dly found for B1: ( 0, 14, 24)
6820 11:17:51.826394 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6821 11:17:51.829891 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6822 11:17:51.829967
6823 11:17:51.833024 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6824 11:17:51.836737 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6825 11:17:51.839482 [Gating] SW calibration Done
6826 11:17:51.839586 ==
6827 11:17:51.842871 Dram Type= 6, Freq= 0, CH_1, rank 1
6828 11:17:51.846460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6829 11:17:51.846567 ==
6830 11:17:51.849410 RX Vref Scan: 0
6831 11:17:51.849484
6832 11:17:51.849546 RX Vref 0 -> 0, step: 1
6833 11:17:51.849605
6834 11:17:51.852860 RX Delay -410 -> 252, step: 16
6835 11:17:51.859432 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6836 11:17:51.862801 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6837 11:17:51.865929 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6838 11:17:51.869816 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6839 11:17:51.876163 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6840 11:17:51.879754 iDelay=230, Bit 5, Center -11 (-250 ~ 229) 480
6841 11:17:51.882771 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6842 11:17:51.885901 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6843 11:17:51.892426 iDelay=230, Bit 8, Center -43 (-282 ~ 197) 480
6844 11:17:51.895608 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6845 11:17:51.899104 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6846 11:17:51.902714 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6847 11:17:51.908695 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6848 11:17:51.912146 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6849 11:17:51.915698 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6850 11:17:51.922347 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6851 11:17:51.922454 ==
6852 11:17:51.925612 Dram Type= 6, Freq= 0, CH_1, rank 1
6853 11:17:51.928693 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6854 11:17:51.928815 ==
6855 11:17:51.928916 DQS Delay:
6856 11:17:51.932288 DQS0 = 35, DQS1 = 43
6857 11:17:51.932373 DQM Delay:
6858 11:17:51.935257 DQM0 = 16, DQM1 = 20
6859 11:17:51.935344 DQ Delay:
6860 11:17:51.938476 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6861 11:17:51.942176 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =16
6862 11:17:51.945142 DQ8 =0, DQ9 =8, DQ10 =24, DQ11 =16
6863 11:17:51.948713 DQ12 =32, DQ13 =24, DQ14 =24, DQ15 =32
6864 11:17:51.948828
6865 11:17:51.948921
6866 11:17:51.949010 ==
6867 11:17:51.951933 Dram Type= 6, Freq= 0, CH_1, rank 1
6868 11:17:51.955218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6869 11:17:51.955320 ==
6870 11:17:51.955411
6871 11:17:51.958416
6872 11:17:51.958546 TX Vref Scan disable
6873 11:17:51.961782 == TX Byte 0 ==
6874 11:17:51.964968 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6875 11:17:51.968508 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6876 11:17:51.971842 == TX Byte 1 ==
6877 11:17:51.975177 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6878 11:17:51.978373 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6879 11:17:51.978462 ==
6880 11:17:51.981777 Dram Type= 6, Freq= 0, CH_1, rank 1
6881 11:17:51.984940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6882 11:17:51.987947 ==
6883 11:17:51.988035
6884 11:17:51.988123
6885 11:17:51.988206 TX Vref Scan disable
6886 11:17:51.991551 == TX Byte 0 ==
6887 11:17:51.994738 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6888 11:17:51.997948 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6889 11:17:52.001513 == TX Byte 1 ==
6890 11:17:52.004454 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6891 11:17:52.008429 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6892 11:17:52.008512
6893 11:17:52.008579 [DATLAT]
6894 11:17:52.011447 Freq=400, CH1 RK1
6895 11:17:52.011533
6896 11:17:52.014591 DATLAT Default: 0xe
6897 11:17:52.014677 0, 0xFFFF, sum = 0
6898 11:17:52.017763 1, 0xFFFF, sum = 0
6899 11:17:52.017850 2, 0xFFFF, sum = 0
6900 11:17:52.021357 3, 0xFFFF, sum = 0
6901 11:17:52.021445 4, 0xFFFF, sum = 0
6902 11:17:52.024646 5, 0xFFFF, sum = 0
6903 11:17:52.024734 6, 0xFFFF, sum = 0
6904 11:17:52.027688 7, 0xFFFF, sum = 0
6905 11:17:52.027778 8, 0xFFFF, sum = 0
6906 11:17:52.031250 9, 0xFFFF, sum = 0
6907 11:17:52.031335 10, 0xFFFF, sum = 0
6908 11:17:52.034666 11, 0xFFFF, sum = 0
6909 11:17:52.034754 12, 0xFFFF, sum = 0
6910 11:17:52.037641 13, 0x0, sum = 1
6911 11:17:52.037754 14, 0x0, sum = 2
6912 11:17:52.040761 15, 0x0, sum = 3
6913 11:17:52.040853 16, 0x0, sum = 4
6914 11:17:52.044059 best_step = 14
6915 11:17:52.044143
6916 11:17:52.044209 ==
6917 11:17:52.047725 Dram Type= 6, Freq= 0, CH_1, rank 1
6918 11:17:52.050797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6919 11:17:52.050886 ==
6920 11:17:52.054082 RX Vref Scan: 0
6921 11:17:52.054194
6922 11:17:52.054285 RX Vref 0 -> 0, step: 1
6923 11:17:52.054360
6924 11:17:52.057448 RX Delay -327 -> 252, step: 8
6925 11:17:52.065293 iDelay=217, Bit 0, Center -16 (-231 ~ 200) 432
6926 11:17:52.068668 iDelay=217, Bit 1, Center -28 (-247 ~ 192) 440
6927 11:17:52.072099 iDelay=217, Bit 2, Center -32 (-255 ~ 192) 448
6928 11:17:52.078608 iDelay=217, Bit 3, Center -24 (-247 ~ 200) 448
6929 11:17:52.082015 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6930 11:17:52.085030 iDelay=217, Bit 5, Center -12 (-239 ~ 216) 456
6931 11:17:52.088277 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6932 11:17:52.095116 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
6933 11:17:52.098549 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
6934 11:17:52.101791 iDelay=217, Bit 9, Center -36 (-263 ~ 192) 456
6935 11:17:52.105022 iDelay=217, Bit 10, Center -24 (-247 ~ 200) 448
6936 11:17:52.111796 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
6937 11:17:52.115138 iDelay=217, Bit 12, Center -20 (-247 ~ 208) 456
6938 11:17:52.118182 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6939 11:17:52.121349 iDelay=217, Bit 14, Center -20 (-247 ~ 208) 456
6940 11:17:52.127998 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
6941 11:17:52.128102 ==
6942 11:17:52.131557 Dram Type= 6, Freq= 0, CH_1, rank 1
6943 11:17:52.134853 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6944 11:17:52.134953 ==
6945 11:17:52.135050 DQS Delay:
6946 11:17:52.137979 DQS0 = 32, DQS1 = 36
6947 11:17:52.138106 DQM Delay:
6948 11:17:52.141320 DQM0 = 12, DQM1 = 12
6949 11:17:52.141445 DQ Delay:
6950 11:17:52.144577 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =8
6951 11:17:52.147880 DQ4 =16, DQ5 =20, DQ6 =20, DQ7 =12
6952 11:17:52.151087 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =8
6953 11:17:52.154806 DQ12 =16, DQ13 =20, DQ14 =16, DQ15 =24
6954 11:17:52.154918
6955 11:17:52.155021
6956 11:17:52.161309 [DQSOSCAuto] RK1, (LSB)MR18= 0xa44c, (MSB)MR19= 0xc0c, tDQSOscB0 = 400 ps tDQSOscB1 = 389 ps
6957 11:17:52.164636 CH1 RK1: MR19=C0C, MR18=A44C
6958 11:17:52.171154 CH1_RK1: MR19=0xC0C, MR18=0xA44C, DQSOSC=389, MR23=63, INC=390, DEC=260
6959 11:17:52.174306 [RxdqsGatingPostProcess] freq 400
6960 11:17:52.181144 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6961 11:17:52.184587 best DQS0 dly(2T, 0.5T) = (0, 10)
6962 11:17:52.188303 best DQS1 dly(2T, 0.5T) = (0, 10)
6963 11:17:52.191053 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6964 11:17:52.194511 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6965 11:17:52.194616 best DQS0 dly(2T, 0.5T) = (0, 10)
6966 11:17:52.197956 best DQS1 dly(2T, 0.5T) = (0, 10)
6967 11:17:52.201049 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6968 11:17:52.204340 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6969 11:17:52.207632 Pre-setting of DQS Precalculation
6970 11:17:52.214468 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6971 11:17:52.221151 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6972 11:17:52.227725 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6973 11:17:52.227843
6974 11:17:52.227938
6975 11:17:52.231016 [Calibration Summary] 800 Mbps
6976 11:17:52.231097 CH 0, Rank 0
6977 11:17:52.233918 SW Impedance : PASS
6978 11:17:52.237486 DUTY Scan : NO K
6979 11:17:52.237572 ZQ Calibration : PASS
6980 11:17:52.240613 Jitter Meter : NO K
6981 11:17:52.243918 CBT Training : PASS
6982 11:17:52.244004 Write leveling : PASS
6983 11:17:52.247043 RX DQS gating : PASS
6984 11:17:52.250552 RX DQ/DQS(RDDQC) : PASS
6985 11:17:52.250639 TX DQ/DQS : PASS
6986 11:17:52.254163 RX DATLAT : PASS
6987 11:17:52.257032 RX DQ/DQS(Engine): PASS
6988 11:17:52.257118 TX OE : NO K
6989 11:17:52.260520 All Pass.
6990 11:17:52.260603
6991 11:17:52.260670 CH 0, Rank 1
6992 11:17:52.263706 SW Impedance : PASS
6993 11:17:52.263789 DUTY Scan : NO K
6994 11:17:52.266909 ZQ Calibration : PASS
6995 11:17:52.270199 Jitter Meter : NO K
6996 11:17:52.270310 CBT Training : PASS
6997 11:17:52.273497 Write leveling : NO K
6998 11:17:52.277188 RX DQS gating : PASS
6999 11:17:52.277273 RX DQ/DQS(RDDQC) : PASS
7000 11:17:52.280271 TX DQ/DQS : PASS
7001 11:17:52.283411 RX DATLAT : PASS
7002 11:17:52.283494 RX DQ/DQS(Engine): PASS
7003 11:17:52.286814 TX OE : NO K
7004 11:17:52.286897 All Pass.
7005 11:17:52.286963
7006 11:17:52.290189 CH 1, Rank 0
7007 11:17:52.290272 SW Impedance : PASS
7008 11:17:52.293290 DUTY Scan : NO K
7009 11:17:52.296492 ZQ Calibration : PASS
7010 11:17:52.296582 Jitter Meter : NO K
7011 11:17:52.299708 CBT Training : PASS
7012 11:17:52.299792 Write leveling : PASS
7013 11:17:52.303182 RX DQS gating : PASS
7014 11:17:52.306487 RX DQ/DQS(RDDQC) : PASS
7015 11:17:52.306573 TX DQ/DQS : PASS
7016 11:17:52.309918 RX DATLAT : PASS
7017 11:17:52.313129 RX DQ/DQS(Engine): PASS
7018 11:17:52.313213 TX OE : NO K
7019 11:17:52.316220 All Pass.
7020 11:17:52.316304
7021 11:17:52.316370 CH 1, Rank 1
7022 11:17:52.319502 SW Impedance : PASS
7023 11:17:52.319586 DUTY Scan : NO K
7024 11:17:52.323301 ZQ Calibration : PASS
7025 11:17:52.326683 Jitter Meter : NO K
7026 11:17:52.326768 CBT Training : PASS
7027 11:17:52.329524 Write leveling : NO K
7028 11:17:52.332926 RX DQS gating : PASS
7029 11:17:52.333010 RX DQ/DQS(RDDQC) : PASS
7030 11:17:52.336457 TX DQ/DQS : PASS
7031 11:17:52.339460 RX DATLAT : PASS
7032 11:17:52.339545 RX DQ/DQS(Engine): PASS
7033 11:17:52.343181 TX OE : NO K
7034 11:17:52.343266 All Pass.
7035 11:17:52.343332
7036 11:17:52.346287 DramC Write-DBI off
7037 11:17:52.349449 PER_BANK_REFRESH: Hybrid Mode
7038 11:17:52.349533 TX_TRACKING: ON
7039 11:17:52.359410 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7040 11:17:52.362647 [FAST_K] Save calibration result to emmc
7041 11:17:52.366060 dramc_set_vcore_voltage set vcore to 725000
7042 11:17:52.369219 Read voltage for 1600, 0
7043 11:17:52.369326 Vio18 = 0
7044 11:17:52.369421 Vcore = 725000
7045 11:17:52.372699 Vdram = 0
7046 11:17:52.372805 Vddq = 0
7047 11:17:52.372900 Vmddr = 0
7048 11:17:52.379081 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7049 11:17:52.382287 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7050 11:17:52.386034 MEM_TYPE=3, freq_sel=13
7051 11:17:52.388968 sv_algorithm_assistance_LP4_3733
7052 11:17:52.392465 ============ PULL DRAM RESETB DOWN ============
7053 11:17:52.395788 ========== PULL DRAM RESETB DOWN end =========
7054 11:17:52.402272 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7055 11:17:52.405608 ===================================
7056 11:17:52.409103 LPDDR4 DRAM CONFIGURATION
7057 11:17:52.412539 ===================================
7058 11:17:52.412624 EX_ROW_EN[0] = 0x0
7059 11:17:52.415534 EX_ROW_EN[1] = 0x0
7060 11:17:52.415618 LP4Y_EN = 0x0
7061 11:17:52.418897 WORK_FSP = 0x1
7062 11:17:52.418981 WL = 0x5
7063 11:17:52.422082 RL = 0x5
7064 11:17:52.422166 BL = 0x2
7065 11:17:52.425309 RPST = 0x0
7066 11:17:52.425392 RD_PRE = 0x0
7067 11:17:52.428907 WR_PRE = 0x1
7068 11:17:52.432098 WR_PST = 0x1
7069 11:17:52.432182 DBI_WR = 0x0
7070 11:17:52.435319 DBI_RD = 0x0
7071 11:17:52.435402 OTF = 0x1
7072 11:17:52.438404 ===================================
7073 11:17:52.441732 ===================================
7074 11:17:52.445044 ANA top config
7075 11:17:52.448207 ===================================
7076 11:17:52.448291 DLL_ASYNC_EN = 0
7077 11:17:52.451393 ALL_SLAVE_EN = 0
7078 11:17:52.455699 NEW_RANK_MODE = 1
7079 11:17:52.458010 DLL_IDLE_MODE = 1
7080 11:17:52.458093 LP45_APHY_COMB_EN = 1
7081 11:17:52.461651 TX_ODT_DIS = 0
7082 11:17:52.464664 NEW_8X_MODE = 1
7083 11:17:52.468214 ===================================
7084 11:17:52.471292 ===================================
7085 11:17:52.474639 data_rate = 3200
7086 11:17:52.477935 CKR = 1
7087 11:17:52.481570 DQ_P2S_RATIO = 8
7088 11:17:52.484692 ===================================
7089 11:17:52.484803 CA_P2S_RATIO = 8
7090 11:17:52.487986 DQ_CA_OPEN = 0
7091 11:17:52.491457 DQ_SEMI_OPEN = 0
7092 11:17:52.494524 CA_SEMI_OPEN = 0
7093 11:17:52.498087 CA_FULL_RATE = 0
7094 11:17:52.501339 DQ_CKDIV4_EN = 0
7095 11:17:52.501423 CA_CKDIV4_EN = 0
7096 11:17:52.504758 CA_PREDIV_EN = 0
7097 11:17:52.508081 PH8_DLY = 12
7098 11:17:52.511293 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7099 11:17:52.514270 DQ_AAMCK_DIV = 4
7100 11:17:52.517919 CA_AAMCK_DIV = 4
7101 11:17:52.518002 CA_ADMCK_DIV = 4
7102 11:17:52.521069 DQ_TRACK_CA_EN = 0
7103 11:17:52.524491 CA_PICK = 1600
7104 11:17:52.527518 CA_MCKIO = 1600
7105 11:17:52.531078 MCKIO_SEMI = 0
7106 11:17:52.534483 PLL_FREQ = 3068
7107 11:17:52.537889 DQ_UI_PI_RATIO = 32
7108 11:17:52.541026 CA_UI_PI_RATIO = 0
7109 11:17:52.541108 ===================================
7110 11:17:52.544063 ===================================
7111 11:17:52.547548 memory_type:LPDDR4
7112 11:17:52.550884 GP_NUM : 10
7113 11:17:52.550970 SRAM_EN : 1
7114 11:17:52.554151 MD32_EN : 0
7115 11:17:52.557435 ===================================
7116 11:17:52.560781 [ANA_INIT] >>>>>>>>>>>>>>
7117 11:17:52.564193 <<<<<< [CONFIGURE PHASE]: ANA_TX
7118 11:17:52.567224 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7119 11:17:52.570583 ===================================
7120 11:17:52.570670 data_rate = 3200,PCW = 0X7600
7121 11:17:52.573856 ===================================
7122 11:17:52.580671 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7123 11:17:52.583756 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7124 11:17:52.590509 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7125 11:17:52.593810 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7126 11:17:52.596886 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7127 11:17:52.600292 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7128 11:17:52.603724 [ANA_INIT] flow start
7129 11:17:52.606741 [ANA_INIT] PLL >>>>>>>>
7130 11:17:52.606828 [ANA_INIT] PLL <<<<<<<<
7131 11:17:52.610227 [ANA_INIT] MIDPI >>>>>>>>
7132 11:17:52.613687 [ANA_INIT] MIDPI <<<<<<<<
7133 11:17:52.616604 [ANA_INIT] DLL >>>>>>>>
7134 11:17:52.616715 [ANA_INIT] DLL <<<<<<<<
7135 11:17:52.620301 [ANA_INIT] flow end
7136 11:17:52.623486 ============ LP4 DIFF to SE enter ============
7137 11:17:52.626570 ============ LP4 DIFF to SE exit ============
7138 11:17:52.630001 [ANA_INIT] <<<<<<<<<<<<<
7139 11:17:52.633246 [Flow] Enable top DCM control >>>>>
7140 11:17:52.636490 [Flow] Enable top DCM control <<<<<
7141 11:17:52.639682 Enable DLL master slave shuffle
7142 11:17:52.646489 ==============================================================
7143 11:17:52.646600 Gating Mode config
7144 11:17:52.653107 ==============================================================
7145 11:17:52.653190 Config description:
7146 11:17:52.663150 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7147 11:17:52.669531 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7148 11:17:52.675855 SELPH_MODE 0: By rank 1: By Phase
7149 11:17:52.679302 ==============================================================
7150 11:17:52.682624 GAT_TRACK_EN = 1
7151 11:17:52.685779 RX_GATING_MODE = 2
7152 11:17:52.689276 RX_GATING_TRACK_MODE = 2
7153 11:17:52.692544 SELPH_MODE = 1
7154 11:17:52.695515 PICG_EARLY_EN = 1
7155 11:17:52.699081 VALID_LAT_VALUE = 1
7156 11:17:52.705643 ==============================================================
7157 11:17:52.708923 Enter into Gating configuration >>>>
7158 11:17:52.712339 Exit from Gating configuration <<<<
7159 11:17:52.715399 Enter into DVFS_PRE_config >>>>>
7160 11:17:52.725305 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7161 11:17:52.728662 Exit from DVFS_PRE_config <<<<<
7162 11:17:52.731967 Enter into PICG configuration >>>>
7163 11:17:52.735245 Exit from PICG configuration <<<<
7164 11:17:52.738645 [RX_INPUT] configuration >>>>>
7165 11:17:52.738727 [RX_INPUT] configuration <<<<<
7166 11:17:52.745366 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7167 11:17:52.751970 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7168 11:17:52.758534 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7169 11:17:52.761913 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7170 11:17:52.768562 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7171 11:17:52.775143 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7172 11:17:52.778356 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7173 11:17:52.781556 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7174 11:17:52.788281 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7175 11:17:52.791844 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7176 11:17:52.794957 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7177 11:17:52.801368 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7178 11:17:52.804770 ===================================
7179 11:17:52.804870 LPDDR4 DRAM CONFIGURATION
7180 11:17:52.808167 ===================================
7181 11:17:52.811169 EX_ROW_EN[0] = 0x0
7182 11:17:52.814464 EX_ROW_EN[1] = 0x0
7183 11:17:52.814548 LP4Y_EN = 0x0
7184 11:17:52.817981 WORK_FSP = 0x1
7185 11:17:52.818065 WL = 0x5
7186 11:17:52.821590 RL = 0x5
7187 11:17:52.821674 BL = 0x2
7188 11:17:52.824332 RPST = 0x0
7189 11:17:52.824415 RD_PRE = 0x0
7190 11:17:52.827742 WR_PRE = 0x1
7191 11:17:52.827826 WR_PST = 0x1
7192 11:17:52.831148 DBI_WR = 0x0
7193 11:17:52.831232 DBI_RD = 0x0
7194 11:17:52.834440 OTF = 0x1
7195 11:17:52.837963 ===================================
7196 11:17:52.841049 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7197 11:17:52.844577 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7198 11:17:52.851005 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7199 11:17:52.854420 ===================================
7200 11:17:52.854529 LPDDR4 DRAM CONFIGURATION
7201 11:17:52.857417 ===================================
7202 11:17:52.860788 EX_ROW_EN[0] = 0x10
7203 11:17:52.864252 EX_ROW_EN[1] = 0x0
7204 11:17:52.864358 LP4Y_EN = 0x0
7205 11:17:52.867628 WORK_FSP = 0x1
7206 11:17:52.867711 WL = 0x5
7207 11:17:52.870778 RL = 0x5
7208 11:17:52.870889 BL = 0x2
7209 11:17:52.874111 RPST = 0x0
7210 11:17:52.874193 RD_PRE = 0x0
7211 11:17:52.877372 WR_PRE = 0x1
7212 11:17:52.877454 WR_PST = 0x1
7213 11:17:52.880954 DBI_WR = 0x0
7214 11:17:52.881036 DBI_RD = 0x0
7215 11:17:52.884090 OTF = 0x1
7216 11:17:52.887202 ===================================
7217 11:17:52.894210 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7218 11:17:52.894294 ==
7219 11:17:52.897316 Dram Type= 6, Freq= 0, CH_0, rank 0
7220 11:17:52.900418 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7221 11:17:52.900502 ==
7222 11:17:52.903662 [Duty_Offset_Calibration]
7223 11:17:52.903744 B0:2 B1:0 CA:1
7224 11:17:52.903809
7225 11:17:52.907046 [DutyScan_Calibration_Flow] k_type=0
7226 11:17:52.917120
7227 11:17:52.917202 ==CLK 0==
7228 11:17:52.920534 Final CLK duty delay cell = -4
7229 11:17:52.923418 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7230 11:17:52.926769 [-4] MIN Duty = 4813%(X100), DQS PI = 62
7231 11:17:52.930062 [-4] AVG Duty = 4906%(X100)
7232 11:17:52.930170
7233 11:17:52.933556 CH0 CLK Duty spec in!! Max-Min= 187%
7234 11:17:52.936706 [DutyScan_Calibration_Flow] ====Done====
7235 11:17:52.936841
7236 11:17:52.940155 [DutyScan_Calibration_Flow] k_type=1
7237 11:17:52.956544
7238 11:17:52.956632 ==DQS 0 ==
7239 11:17:52.960024 Final DQS duty delay cell = 0
7240 11:17:52.963139 [0] MAX Duty = 5249%(X100), DQS PI = 32
7241 11:17:52.966140 [0] MIN Duty = 4969%(X100), DQS PI = 0
7242 11:17:52.969605 [0] AVG Duty = 5109%(X100)
7243 11:17:52.969687
7244 11:17:52.969786 ==DQS 1 ==
7245 11:17:52.972720 Final DQS duty delay cell = -4
7246 11:17:52.976471 [-4] MAX Duty = 5125%(X100), DQS PI = 28
7247 11:17:52.979152 [-4] MIN Duty = 4875%(X100), DQS PI = 4
7248 11:17:52.983079 [-4] AVG Duty = 5000%(X100)
7249 11:17:52.983160
7250 11:17:52.985907 CH0 DQS 0 Duty spec in!! Max-Min= 280%
7251 11:17:52.985989
7252 11:17:52.989737 CH0 DQS 1 Duty spec in!! Max-Min= 250%
7253 11:17:52.992488 [DutyScan_Calibration_Flow] ====Done====
7254 11:17:52.992570
7255 11:17:52.995535 [DutyScan_Calibration_Flow] k_type=3
7256 11:17:53.014045
7257 11:17:53.014141 ==DQM 0 ==
7258 11:17:53.017367 Final DQM duty delay cell = 0
7259 11:17:53.020239 [0] MAX Duty = 5093%(X100), DQS PI = 26
7260 11:17:53.023973 [0] MIN Duty = 4844%(X100), DQS PI = 2
7261 11:17:53.024054 [0] AVG Duty = 4968%(X100)
7262 11:17:53.027302
7263 11:17:53.027386 ==DQM 1 ==
7264 11:17:53.030624 Final DQM duty delay cell = 0
7265 11:17:53.033668 [0] MAX Duty = 5249%(X100), DQS PI = 44
7266 11:17:53.037290 [0] MIN Duty = 5031%(X100), DQS PI = 18
7267 11:17:53.040380 [0] AVG Duty = 5140%(X100)
7268 11:17:53.040462
7269 11:17:53.043547 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7270 11:17:53.043629
7271 11:17:53.046840 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7272 11:17:53.050349 [DutyScan_Calibration_Flow] ====Done====
7273 11:17:53.050431
7274 11:17:53.053902 [DutyScan_Calibration_Flow] k_type=2
7275 11:17:53.071063
7276 11:17:53.071150 ==DQ 0 ==
7277 11:17:53.074317 Final DQ duty delay cell = 0
7278 11:17:53.077992 [0] MAX Duty = 5124%(X100), DQS PI = 32
7279 11:17:53.081024 [0] MIN Duty = 5000%(X100), DQS PI = 0
7280 11:17:53.081107 [0] AVG Duty = 5062%(X100)
7281 11:17:53.084264
7282 11:17:53.084346 ==DQ 1 ==
7283 11:17:53.087840 Final DQ duty delay cell = 0
7284 11:17:53.090971 [0] MAX Duty = 4969%(X100), DQS PI = 42
7285 11:17:53.094095 [0] MIN Duty = 4875%(X100), DQS PI = 10
7286 11:17:53.094178 [0] AVG Duty = 4922%(X100)
7287 11:17:53.094243
7288 11:17:53.100687 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7289 11:17:53.100787
7290 11:17:53.104248 CH0 DQ 1 Duty spec in!! Max-Min= 94%
7291 11:17:53.107252 [DutyScan_Calibration_Flow] ====Done====
7292 11:17:53.107368 ==
7293 11:17:53.110676 Dram Type= 6, Freq= 0, CH_1, rank 0
7294 11:17:53.113923 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7295 11:17:53.114002 ==
7296 11:17:53.117389 [Duty_Offset_Calibration]
7297 11:17:53.117462 B0:0 B1:-1 CA:2
7298 11:17:53.117522
7299 11:17:53.120611 [DutyScan_Calibration_Flow] k_type=0
7300 11:17:53.131125
7301 11:17:53.131232 ==CLK 0==
7302 11:17:53.134350 Final CLK duty delay cell = 0
7303 11:17:53.137686 [0] MAX Duty = 5187%(X100), DQS PI = 14
7304 11:17:53.141116 [0] MIN Duty = 4906%(X100), DQS PI = 46
7305 11:17:53.144482 [0] AVG Duty = 5046%(X100)
7306 11:17:53.144562
7307 11:17:53.147780 CH1 CLK Duty spec in!! Max-Min= 281%
7308 11:17:53.151115 [DutyScan_Calibration_Flow] ====Done====
7309 11:17:53.151188
7310 11:17:53.154243 [DutyScan_Calibration_Flow] k_type=1
7311 11:17:53.171277
7312 11:17:53.171393 ==DQS 0 ==
7313 11:17:53.174377 Final DQS duty delay cell = 0
7314 11:17:53.177459 [0] MAX Duty = 5093%(X100), DQS PI = 24
7315 11:17:53.180655 [0] MIN Duty = 4969%(X100), DQS PI = 0
7316 11:17:53.183950 [0] AVG Duty = 5031%(X100)
7317 11:17:53.184048
7318 11:17:53.184147 ==DQS 1 ==
7319 11:17:53.187468 Final DQS duty delay cell = 0
7320 11:17:53.190613 [0] MAX Duty = 5187%(X100), DQS PI = 0
7321 11:17:53.194108 [0] MIN Duty = 4844%(X100), DQS PI = 32
7322 11:17:53.197317 [0] AVG Duty = 5015%(X100)
7323 11:17:53.197389
7324 11:17:53.200696 CH1 DQS 0 Duty spec in!! Max-Min= 124%
7325 11:17:53.200821
7326 11:17:53.204293 CH1 DQS 1 Duty spec in!! Max-Min= 343%
7327 11:17:53.207570 [DutyScan_Calibration_Flow] ====Done====
7328 11:17:53.207650
7329 11:17:53.210471 [DutyScan_Calibration_Flow] k_type=3
7330 11:17:53.228520
7331 11:17:53.228618 ==DQM 0 ==
7332 11:17:53.232056 Final DQM duty delay cell = 4
7333 11:17:53.234946 [4] MAX Duty = 5125%(X100), DQS PI = 6
7334 11:17:53.238467 [4] MIN Duty = 5000%(X100), DQS PI = 32
7335 11:17:53.241797 [4] AVG Duty = 5062%(X100)
7336 11:17:53.241880
7337 11:17:53.241943 ==DQM 1 ==
7338 11:17:53.245064 Final DQM duty delay cell = 0
7339 11:17:53.248267 [0] MAX Duty = 5281%(X100), DQS PI = 58
7340 11:17:53.251872 [0] MIN Duty = 4876%(X100), DQS PI = 34
7341 11:17:53.254872 [0] AVG Duty = 5078%(X100)
7342 11:17:53.254951
7343 11:17:53.258363 CH1 DQM 0 Duty spec in!! Max-Min= 125%
7344 11:17:53.258446
7345 11:17:53.261655 CH1 DQM 1 Duty spec in!! Max-Min= 405%
7346 11:17:53.265094 [DutyScan_Calibration_Flow] ====Done====
7347 11:17:53.265175
7348 11:17:53.268453 [DutyScan_Calibration_Flow] k_type=2
7349 11:17:53.285668
7350 11:17:53.285859 ==DQ 0 ==
7351 11:17:53.288939 Final DQ duty delay cell = 0
7352 11:17:53.292144 [0] MAX Duty = 5093%(X100), DQS PI = 22
7353 11:17:53.295381 [0] MIN Duty = 4969%(X100), DQS PI = 48
7354 11:17:53.295469 [0] AVG Duty = 5031%(X100)
7355 11:17:53.298617
7356 11:17:53.298700 ==DQ 1 ==
7357 11:17:53.301804 Final DQ duty delay cell = 0
7358 11:17:53.305011 [0] MAX Duty = 5062%(X100), DQS PI = 2
7359 11:17:53.308610 [0] MIN Duty = 4844%(X100), DQS PI = 32
7360 11:17:53.308694 [0] AVG Duty = 4953%(X100)
7361 11:17:53.308760
7362 11:17:53.311704 CH1 DQ 0 Duty spec in!! Max-Min= 124%
7363 11:17:53.315288
7364 11:17:53.318310 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7365 11:17:53.321686 [DutyScan_Calibration_Flow] ====Done====
7366 11:17:53.324795 nWR fixed to 30
7367 11:17:53.324879 [ModeRegInit_LP4] CH0 RK0
7368 11:17:53.328172 [ModeRegInit_LP4] CH0 RK1
7369 11:17:53.331495 [ModeRegInit_LP4] CH1 RK0
7370 11:17:53.335053 [ModeRegInit_LP4] CH1 RK1
7371 11:17:53.335136 match AC timing 5
7372 11:17:53.341319 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7373 11:17:53.344510 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7374 11:17:53.347991 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7375 11:17:53.354790 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7376 11:17:53.357983 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7377 11:17:53.358068 [MiockJmeterHQA]
7378 11:17:53.358134
7379 11:17:53.361280 [DramcMiockJmeter] u1RxGatingPI = 0
7380 11:17:53.364529 0 : 4253, 4027
7381 11:17:53.364613 4 : 4257, 4029
7382 11:17:53.368327 8 : 4363, 4138
7383 11:17:53.368412 12 : 4363, 4137
7384 11:17:53.371233 16 : 4363, 4138
7385 11:17:53.371317 20 : 4252, 4027
7386 11:17:53.371383 24 : 4252, 4027
7387 11:17:53.374301 28 : 4253, 4026
7388 11:17:53.374384 32 : 4252, 4027
7389 11:17:53.377558 36 : 4255, 4029
7390 11:17:53.377642 40 : 4363, 4137
7391 11:17:53.381027 44 : 4252, 4027
7392 11:17:53.381112 48 : 4253, 4027
7393 11:17:53.384583 52 : 4253, 4029
7394 11:17:53.384668 56 : 4255, 4029
7395 11:17:53.384735 60 : 4250, 4026
7396 11:17:53.387645 64 : 4361, 4138
7397 11:17:53.387731 68 : 4360, 4138
7398 11:17:53.391018 72 : 4250, 4027
7399 11:17:53.391104 76 : 4250, 4027
7400 11:17:53.394229 80 : 4250, 4027
7401 11:17:53.394313 84 : 4250, 4027
7402 11:17:53.394380 88 : 4252, 3601
7403 11:17:53.397790 92 : 4361, 0
7404 11:17:53.397875 96 : 4250, 0
7405 11:17:53.400901 100 : 4249, 0
7406 11:17:53.401019 104 : 4249, 0
7407 11:17:53.401175 108 : 4361, 0
7408 11:17:53.404044 112 : 4250, 0
7409 11:17:53.404159 116 : 4249, 0
7410 11:17:53.407337 120 : 4250, 0
7411 11:17:53.407423 124 : 4361, 0
7412 11:17:53.407489 128 : 4360, 0
7413 11:17:53.411161 132 : 4250, 0
7414 11:17:53.411273 136 : 4250, 0
7415 11:17:53.414379 140 : 4252, 0
7416 11:17:53.414465 144 : 4249, 0
7417 11:17:53.414533 148 : 4250, 0
7418 11:17:53.417639 152 : 4249, 0
7419 11:17:53.417725 156 : 4252, 0
7420 11:17:53.417792 160 : 4361, 0
7421 11:17:53.420983 164 : 4250, 0
7422 11:17:53.421068 168 : 4250, 0
7423 11:17:53.423987 172 : 4361, 0
7424 11:17:53.424073 176 : 4360, 0
7425 11:17:53.424139 180 : 4363, 0
7426 11:17:53.427185 184 : 4250, 0
7427 11:17:53.427271 188 : 4250, 0
7428 11:17:53.430402 192 : 4252, 0
7429 11:17:53.430487 196 : 4250, 0
7430 11:17:53.430554 200 : 4250, 19
7431 11:17:53.434052 204 : 4252, 2687
7432 11:17:53.434137 208 : 4360, 4137
7433 11:17:53.437127 212 : 4363, 4140
7434 11:17:53.437211 216 : 4250, 4027
7435 11:17:53.440952 220 : 4250, 4027
7436 11:17:53.441036 224 : 4363, 4140
7437 11:17:53.444258 228 : 4250, 4027
7438 11:17:53.444343 232 : 4250, 4027
7439 11:17:53.447291 236 : 4250, 4027
7440 11:17:53.447375 240 : 4249, 4027
7441 11:17:53.450837 244 : 4250, 4027
7442 11:17:53.450939 248 : 4250, 4027
7443 11:17:53.451007 252 : 4360, 4138
7444 11:17:53.453616 256 : 4250, 4027
7445 11:17:53.453702 260 : 4250, 4027
7446 11:17:53.457168 264 : 4361, 4137
7447 11:17:53.457253 268 : 4250, 4027
7448 11:17:53.460711 272 : 4249, 4027
7449 11:17:53.460835 276 : 4360, 4137
7450 11:17:53.463525 280 : 4250, 4027
7451 11:17:53.463610 284 : 4250, 4027
7452 11:17:53.466926 288 : 4249, 4027
7453 11:17:53.467012 292 : 4252, 4029
7454 11:17:53.470385 296 : 4250, 4027
7455 11:17:53.470473 300 : 4250, 4027
7456 11:17:53.473616 304 : 4361, 4138
7457 11:17:53.473703 308 : 4250, 4027
7458 11:17:53.477024 312 : 4249, 3865
7459 11:17:53.477110 316 : 4361, 1936
7460 11:17:53.477178
7461 11:17:53.480584 MIOCK jitter meter ch=0
7462 11:17:53.480670
7463 11:17:53.483518 1T = (316-92) = 224 dly cells
7464 11:17:53.487109 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7465 11:17:53.487204 ==
7466 11:17:53.490043 Dram Type= 6, Freq= 0, CH_0, rank 0
7467 11:17:53.496772 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7468 11:17:53.496892 ==
7469 11:17:53.499947 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7470 11:17:53.506805 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7471 11:17:53.510020 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7472 11:17:53.516484 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7473 11:17:53.527379 [CA 0] Center 42 (12~73) winsize 62
7474 11:17:53.527487 [CA 1] Center 42 (12~72) winsize 61
7475 11:17:53.530830 [CA 2] Center 37 (7~67) winsize 61
7476 11:17:53.534252 [CA 3] Center 37 (7~67) winsize 61
7477 11:17:53.537414 [CA 4] Center 36 (6~66) winsize 61
7478 11:17:53.540804 [CA 5] Center 35 (5~65) winsize 61
7479 11:17:53.540890
7480 11:17:53.544031 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7481 11:17:53.544115
7482 11:17:53.547587 [CATrainingPosCal] consider 1 rank data
7483 11:17:53.550932 u2DelayCellTimex100 = 290/100 ps
7484 11:17:53.557184 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7485 11:17:53.560818 CA1 delay=42 (12~72),Diff = 7 PI (23 cell)
7486 11:17:53.563808 CA2 delay=37 (7~67),Diff = 2 PI (6 cell)
7487 11:17:53.567613 CA3 delay=37 (7~67),Diff = 2 PI (6 cell)
7488 11:17:53.570249 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7489 11:17:53.573540 CA5 delay=35 (5~65),Diff = 0 PI (0 cell)
7490 11:17:53.573641
7491 11:17:53.576935 CA PerBit enable=1, Macro0, CA PI delay=35
7492 11:17:53.577017
7493 11:17:53.580251 [CBTSetCACLKResult] CA Dly = 35
7494 11:17:53.583705 CS Dly: 9 (0~40)
7495 11:17:53.586655 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7496 11:17:53.589835 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7497 11:17:53.589919 ==
7498 11:17:53.593158 Dram Type= 6, Freq= 0, CH_0, rank 1
7499 11:17:53.599572 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7500 11:17:53.599658 ==
7501 11:17:53.602830 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7502 11:17:53.609416 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7503 11:17:53.612903 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7504 11:17:53.619680 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7505 11:17:53.627594 [CA 0] Center 43 (13~74) winsize 62
7506 11:17:53.630720 [CA 1] Center 43 (13~73) winsize 61
7507 11:17:53.634266 [CA 2] Center 38 (9~68) winsize 60
7508 11:17:53.637469 [CA 3] Center 38 (9~68) winsize 60
7509 11:17:53.640642 [CA 4] Center 36 (7~66) winsize 60
7510 11:17:53.644456 [CA 5] Center 36 (6~66) winsize 61
7511 11:17:53.644542
7512 11:17:53.647612 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7513 11:17:53.647698
7514 11:17:53.650546 [CATrainingPosCal] consider 2 rank data
7515 11:17:53.654077 u2DelayCellTimex100 = 290/100 ps
7516 11:17:53.660378 CA0 delay=43 (13~73),Diff = 8 PI (26 cell)
7517 11:17:53.664022 CA1 delay=42 (13~72),Diff = 7 PI (23 cell)
7518 11:17:53.667080 CA2 delay=38 (9~67),Diff = 3 PI (10 cell)
7519 11:17:53.670179 CA3 delay=38 (9~67),Diff = 3 PI (10 cell)
7520 11:17:53.673924 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7521 11:17:53.677168 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7522 11:17:53.677255
7523 11:17:53.680479 CA PerBit enable=1, Macro0, CA PI delay=35
7524 11:17:53.680563
7525 11:17:53.683609 [CBTSetCACLKResult] CA Dly = 35
7526 11:17:53.687101 CS Dly: 10 (0~43)
7527 11:17:53.690056 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7528 11:17:53.693462 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7529 11:17:53.693547
7530 11:17:53.697034 ----->DramcWriteLeveling(PI) begin...
7531 11:17:53.697119 ==
7532 11:17:53.700241 Dram Type= 6, Freq= 0, CH_0, rank 0
7533 11:17:53.706812 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7534 11:17:53.706899 ==
7535 11:17:53.709991 Write leveling (Byte 0): 36 => 36
7536 11:17:53.713525 Write leveling (Byte 1): 30 => 30
7537 11:17:53.716562 DramcWriteLeveling(PI) end<-----
7538 11:17:53.716648
7539 11:17:53.716713 ==
7540 11:17:53.719862 Dram Type= 6, Freq= 0, CH_0, rank 0
7541 11:17:53.723136 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7542 11:17:53.723222 ==
7543 11:17:53.726755 [Gating] SW mode calibration
7544 11:17:53.733221 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7545 11:17:53.736521 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7546 11:17:53.742871 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7547 11:17:53.746378 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7548 11:17:53.749567 1 4 8 | B1->B0 | 2323 2e2d | 0 1 | (0 0) (1 1)
7549 11:17:53.756494 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7550 11:17:53.759698 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7551 11:17:53.762833 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7552 11:17:53.769529 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7553 11:17:53.772842 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7554 11:17:53.776250 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7555 11:17:53.782618 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7556 11:17:53.785890 1 5 8 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
7557 11:17:53.789305 1 5 12 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
7558 11:17:53.795784 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7559 11:17:53.799047 1 5 20 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
7560 11:17:53.803051 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7561 11:17:53.809068 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7562 11:17:53.812569 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7563 11:17:53.815597 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7564 11:17:53.822179 1 6 8 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
7565 11:17:53.825537 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7566 11:17:53.829357 1 6 16 | B1->B0 | 2727 4646 | 0 0 | (0 0) (0 0)
7567 11:17:53.835304 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7568 11:17:53.838776 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7569 11:17:53.842226 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7570 11:17:53.848408 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7571 11:17:53.852115 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7572 11:17:53.855119 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7573 11:17:53.862087 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7574 11:17:53.865488 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7575 11:17:53.868354 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7576 11:17:53.875362 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7577 11:17:53.878193 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7578 11:17:53.881768 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7579 11:17:53.888672 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7580 11:17:53.891483 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7581 11:17:53.894874 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7582 11:17:53.901383 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 11:17:53.904683 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 11:17:53.907922 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 11:17:53.914717 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 11:17:53.918090 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 11:17:53.921279 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 11:17:53.927806 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7589 11:17:53.931482 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7590 11:17:53.934381 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7591 11:17:53.937985 Total UI for P1: 0, mck2ui 16
7592 11:17:53.941181 best dqsien dly found for B0: ( 1, 9, 10)
7593 11:17:53.947471 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7594 11:17:53.950951 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7595 11:17:53.954280 Total UI for P1: 0, mck2ui 16
7596 11:17:53.957496 best dqsien dly found for B1: ( 1, 9, 20)
7597 11:17:53.960980 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7598 11:17:53.964203 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7599 11:17:53.964324
7600 11:17:53.967702 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7601 11:17:53.971390 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7602 11:17:53.974319 [Gating] SW calibration Done
7603 11:17:53.974436 ==
7604 11:17:53.977435 Dram Type= 6, Freq= 0, CH_0, rank 0
7605 11:17:53.983842 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7606 11:17:53.983973 ==
7607 11:17:53.984082 RX Vref Scan: 0
7608 11:17:53.984190
7609 11:17:53.987332 RX Vref 0 -> 0, step: 1
7610 11:17:53.987441
7611 11:17:53.990731 RX Delay 0 -> 252, step: 8
7612 11:17:53.994084 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7613 11:17:53.997092 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7614 11:17:54.000700 iDelay=200, Bit 2, Center 135 (88 ~ 183) 96
7615 11:17:54.003800 iDelay=200, Bit 3, Center 135 (88 ~ 183) 96
7616 11:17:54.010733 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7617 11:17:54.013794 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7618 11:17:54.017246 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
7619 11:17:54.020856 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7620 11:17:54.023588 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7621 11:17:54.030337 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7622 11:17:54.033718 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
7623 11:17:54.036800 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
7624 11:17:54.039974 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7625 11:17:54.043473 iDelay=200, Bit 13, Center 127 (80 ~ 175) 96
7626 11:17:54.049855 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7627 11:17:54.053166 iDelay=200, Bit 15, Center 135 (88 ~ 183) 96
7628 11:17:54.053279 ==
7629 11:17:54.056563 Dram Type= 6, Freq= 0, CH_0, rank 0
7630 11:17:54.059890 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7631 11:17:54.060003 ==
7632 11:17:54.063220 DQS Delay:
7633 11:17:54.063334 DQS0 = 0, DQS1 = 0
7634 11:17:54.066244 DQM Delay:
7635 11:17:54.066353 DQM0 = 137, DQM1 = 126
7636 11:17:54.066450 DQ Delay:
7637 11:17:54.073076 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
7638 11:17:54.076215 DQ4 =139, DQ5 =123, DQ6 =147, DQ7 =147
7639 11:17:54.079336 DQ8 =119, DQ9 =115, DQ10 =123, DQ11 =123
7640 11:17:54.082733 DQ12 =131, DQ13 =127, DQ14 =135, DQ15 =135
7641 11:17:54.082843
7642 11:17:54.082942
7643 11:17:54.083038 ==
7644 11:17:54.086110 Dram Type= 6, Freq= 0, CH_0, rank 0
7645 11:17:54.089375 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7646 11:17:54.089487 ==
7647 11:17:54.089586
7648 11:17:54.089684
7649 11:17:54.092994 TX Vref Scan disable
7650 11:17:54.095909 == TX Byte 0 ==
7651 11:17:54.099136 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7652 11:17:54.102388 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7653 11:17:54.105791 == TX Byte 1 ==
7654 11:17:54.109328 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
7655 11:17:54.112462 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7656 11:17:54.112578 ==
7657 11:17:54.116098 Dram Type= 6, Freq= 0, CH_0, rank 0
7658 11:17:54.122124 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7659 11:17:54.122239 ==
7660 11:17:54.133027
7661 11:17:54.136283 TX Vref early break, caculate TX vref
7662 11:17:54.139945 TX Vref=16, minBit 4, minWin=23, winSum=380
7663 11:17:54.143213 TX Vref=18, minBit 8, minWin=23, winSum=389
7664 11:17:54.146365 TX Vref=20, minBit 12, minWin=23, winSum=402
7665 11:17:54.149557 TX Vref=22, minBit 0, minWin=25, winSum=408
7666 11:17:54.153004 TX Vref=24, minBit 12, minWin=25, winSum=422
7667 11:17:54.159462 TX Vref=26, minBit 12, minWin=25, winSum=427
7668 11:17:54.163174 TX Vref=28, minBit 0, minWin=26, winSum=431
7669 11:17:54.166071 TX Vref=30, minBit 4, minWin=25, winSum=416
7670 11:17:54.169380 TX Vref=32, minBit 7, minWin=24, winSum=406
7671 11:17:54.176287 [TxChooseVref] Worse bit 0, Min win 26, Win sum 431, Final Vref 28
7672 11:17:54.176403
7673 11:17:54.179582 Final TX Range 0 Vref 28
7674 11:17:54.179683
7675 11:17:54.179773 ==
7676 11:17:54.182562 Dram Type= 6, Freq= 0, CH_0, rank 0
7677 11:17:54.185936 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7678 11:17:54.186022 ==
7679 11:17:54.186088
7680 11:17:54.186148
7681 11:17:54.189213 TX Vref Scan disable
7682 11:17:54.195719 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7683 11:17:54.195805 == TX Byte 0 ==
7684 11:17:54.199000 u2DelayCellOfst[0]=13 cells (4 PI)
7685 11:17:54.202555 u2DelayCellOfst[1]=16 cells (5 PI)
7686 11:17:54.205669 u2DelayCellOfst[2]=13 cells (4 PI)
7687 11:17:54.208922 u2DelayCellOfst[3]=10 cells (3 PI)
7688 11:17:54.212426 u2DelayCellOfst[4]=10 cells (3 PI)
7689 11:17:54.215698 u2DelayCellOfst[5]=0 cells (0 PI)
7690 11:17:54.218674 u2DelayCellOfst[6]=16 cells (5 PI)
7691 11:17:54.222336 u2DelayCellOfst[7]=13 cells (4 PI)
7692 11:17:54.225374 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7693 11:17:54.228746 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7694 11:17:54.232174 == TX Byte 1 ==
7695 11:17:54.235423 u2DelayCellOfst[8]=3 cells (1 PI)
7696 11:17:54.238634 u2DelayCellOfst[9]=0 cells (0 PI)
7697 11:17:54.238718 u2DelayCellOfst[10]=6 cells (2 PI)
7698 11:17:54.241911 u2DelayCellOfst[11]=3 cells (1 PI)
7699 11:17:54.245350 u2DelayCellOfst[12]=13 cells (4 PI)
7700 11:17:54.248418 u2DelayCellOfst[13]=10 cells (3 PI)
7701 11:17:54.251826 u2DelayCellOfst[14]=13 cells (4 PI)
7702 11:17:54.255311 u2DelayCellOfst[15]=10 cells (3 PI)
7703 11:17:54.261747 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
7704 11:17:54.264903 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
7705 11:17:54.265004 DramC Write-DBI on
7706 11:17:54.265100 ==
7707 11:17:54.268347 Dram Type= 6, Freq= 0, CH_0, rank 0
7708 11:17:54.275158 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7709 11:17:54.275262 ==
7710 11:17:54.275331
7711 11:17:54.275395
7712 11:17:54.275456 TX Vref Scan disable
7713 11:17:54.279102 == TX Byte 0 ==
7714 11:17:54.282281 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7715 11:17:54.285508 == TX Byte 1 ==
7716 11:17:54.289105 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
7717 11:17:54.292244 DramC Write-DBI off
7718 11:17:54.292321
7719 11:17:54.292386 [DATLAT]
7720 11:17:54.292477 Freq=1600, CH0 RK0
7721 11:17:54.292565
7722 11:17:54.295427 DATLAT Default: 0xf
7723 11:17:54.298910 0, 0xFFFF, sum = 0
7724 11:17:54.298986 1, 0xFFFF, sum = 0
7725 11:17:54.302426 2, 0xFFFF, sum = 0
7726 11:17:54.302528 3, 0xFFFF, sum = 0
7727 11:17:54.305688 4, 0xFFFF, sum = 0
7728 11:17:54.305765 5, 0xFFFF, sum = 0
7729 11:17:54.309025 6, 0xFFFF, sum = 0
7730 11:17:54.309113 7, 0xFFFF, sum = 0
7731 11:17:54.312123 8, 0xFFFF, sum = 0
7732 11:17:54.312201 9, 0xFFFF, sum = 0
7733 11:17:54.315454 10, 0xFFFF, sum = 0
7734 11:17:54.315532 11, 0xFFFF, sum = 0
7735 11:17:54.318724 12, 0xFFFF, sum = 0
7736 11:17:54.318800 13, 0xFFFF, sum = 0
7737 11:17:54.321904 14, 0x0, sum = 1
7738 11:17:54.321983 15, 0x0, sum = 2
7739 11:17:54.325614 16, 0x0, sum = 3
7740 11:17:54.325694 17, 0x0, sum = 4
7741 11:17:54.328985 best_step = 15
7742 11:17:54.329061
7743 11:17:54.329123 ==
7744 11:17:54.331948 Dram Type= 6, Freq= 0, CH_0, rank 0
7745 11:17:54.335438 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7746 11:17:54.335539 ==
7747 11:17:54.338892 RX Vref Scan: 1
7748 11:17:54.338970
7749 11:17:54.339033 Set Vref Range= 24 -> 127
7750 11:17:54.339093
7751 11:17:54.341717 RX Vref 24 -> 127, step: 1
7752 11:17:54.341790
7753 11:17:54.345023 RX Delay 19 -> 252, step: 4
7754 11:17:54.345115
7755 11:17:54.348593 Set Vref, RX VrefLevel [Byte0]: 24
7756 11:17:54.351761 [Byte1]: 24
7757 11:17:54.351847
7758 11:17:54.355184 Set Vref, RX VrefLevel [Byte0]: 25
7759 11:17:54.358244 [Byte1]: 25
7760 11:17:54.362220
7761 11:17:54.362297 Set Vref, RX VrefLevel [Byte0]: 26
7762 11:17:54.365209 [Byte1]: 26
7763 11:17:54.369206
7764 11:17:54.369363 Set Vref, RX VrefLevel [Byte0]: 27
7765 11:17:54.372458 [Byte1]: 27
7766 11:17:54.376821
7767 11:17:54.376920 Set Vref, RX VrefLevel [Byte0]: 28
7768 11:17:54.380417 [Byte1]: 28
7769 11:17:54.384439
7770 11:17:54.384540 Set Vref, RX VrefLevel [Byte0]: 29
7771 11:17:54.387697 [Byte1]: 29
7772 11:17:54.392018
7773 11:17:54.392120 Set Vref, RX VrefLevel [Byte0]: 30
7774 11:17:54.395455 [Byte1]: 30
7775 11:17:54.399650
7776 11:17:54.399733 Set Vref, RX VrefLevel [Byte0]: 31
7777 11:17:54.402781 [Byte1]: 31
7778 11:17:54.407391
7779 11:17:54.407474 Set Vref, RX VrefLevel [Byte0]: 32
7780 11:17:54.410768 [Byte1]: 32
7781 11:17:54.414592
7782 11:17:54.414675 Set Vref, RX VrefLevel [Byte0]: 33
7783 11:17:54.417992 [Byte1]: 33
7784 11:17:54.422462
7785 11:17:54.422546 Set Vref, RX VrefLevel [Byte0]: 34
7786 11:17:54.425745 [Byte1]: 34
7787 11:17:54.429920
7788 11:17:54.430002 Set Vref, RX VrefLevel [Byte0]: 35
7789 11:17:54.433504 [Byte1]: 35
7790 11:17:54.437615
7791 11:17:54.437697 Set Vref, RX VrefLevel [Byte0]: 36
7792 11:17:54.440690 [Byte1]: 36
7793 11:17:54.445381
7794 11:17:54.445463 Set Vref, RX VrefLevel [Byte0]: 37
7795 11:17:54.448480 [Byte1]: 37
7796 11:17:54.452724
7797 11:17:54.452825 Set Vref, RX VrefLevel [Byte0]: 38
7798 11:17:54.455803 [Byte1]: 38
7799 11:17:54.460145
7800 11:17:54.460227 Set Vref, RX VrefLevel [Byte0]: 39
7801 11:17:54.463639 [Byte1]: 39
7802 11:17:54.467817
7803 11:17:54.467899 Set Vref, RX VrefLevel [Byte0]: 40
7804 11:17:54.471070 [Byte1]: 40
7805 11:17:54.475417
7806 11:17:54.475500 Set Vref, RX VrefLevel [Byte0]: 41
7807 11:17:54.478578 [Byte1]: 41
7808 11:17:54.482924
7809 11:17:54.483013 Set Vref, RX VrefLevel [Byte0]: 42
7810 11:17:54.486228 [Byte1]: 42
7811 11:17:54.490610
7812 11:17:54.490697 Set Vref, RX VrefLevel [Byte0]: 43
7813 11:17:54.493894 [Byte1]: 43
7814 11:17:54.497839
7815 11:17:54.497924 Set Vref, RX VrefLevel [Byte0]: 44
7816 11:17:54.501555 [Byte1]: 44
7817 11:17:54.505462
7818 11:17:54.505546 Set Vref, RX VrefLevel [Byte0]: 45
7819 11:17:54.509452 [Byte1]: 45
7820 11:17:54.513239
7821 11:17:54.513322 Set Vref, RX VrefLevel [Byte0]: 46
7822 11:17:54.517031 [Byte1]: 46
7823 11:17:54.520894
7824 11:17:54.520988 Set Vref, RX VrefLevel [Byte0]: 47
7825 11:17:54.524143 [Byte1]: 47
7826 11:17:54.528811
7827 11:17:54.528900 Set Vref, RX VrefLevel [Byte0]: 48
7828 11:17:54.531915 [Byte1]: 48
7829 11:17:54.535925
7830 11:17:54.536008 Set Vref, RX VrefLevel [Byte0]: 49
7831 11:17:54.539557 [Byte1]: 49
7832 11:17:54.543452
7833 11:17:54.543535 Set Vref, RX VrefLevel [Byte0]: 50
7834 11:17:54.546919 [Byte1]: 50
7835 11:17:54.551374
7836 11:17:54.551460 Set Vref, RX VrefLevel [Byte0]: 51
7837 11:17:54.554216 [Byte1]: 51
7838 11:17:54.558889
7839 11:17:54.558972 Set Vref, RX VrefLevel [Byte0]: 52
7840 11:17:54.561804 [Byte1]: 52
7841 11:17:54.566104
7842 11:17:54.566186 Set Vref, RX VrefLevel [Byte0]: 53
7843 11:17:54.569594 [Byte1]: 53
7844 11:17:54.573781
7845 11:17:54.573865 Set Vref, RX VrefLevel [Byte0]: 54
7846 11:17:54.577045 [Byte1]: 54
7847 11:17:54.581142
7848 11:17:54.584326 Set Vref, RX VrefLevel [Byte0]: 55
7849 11:17:54.587869 [Byte1]: 55
7850 11:17:54.587953
7851 11:17:54.591246 Set Vref, RX VrefLevel [Byte0]: 56
7852 11:17:54.594499 [Byte1]: 56
7853 11:17:54.594583
7854 11:17:54.597860 Set Vref, RX VrefLevel [Byte0]: 57
7855 11:17:54.601040 [Byte1]: 57
7856 11:17:54.601124
7857 11:17:54.604168 Set Vref, RX VrefLevel [Byte0]: 58
7858 11:17:54.607465 [Byte1]: 58
7859 11:17:54.611734
7860 11:17:54.611818 Set Vref, RX VrefLevel [Byte0]: 59
7861 11:17:54.615237 [Byte1]: 59
7862 11:17:54.619066
7863 11:17:54.619150 Set Vref, RX VrefLevel [Byte0]: 60
7864 11:17:54.622504 [Byte1]: 60
7865 11:17:54.626661
7866 11:17:54.626744 Set Vref, RX VrefLevel [Byte0]: 61
7867 11:17:54.630192 [Byte1]: 61
7868 11:17:54.634279
7869 11:17:54.634363 Set Vref, RX VrefLevel [Byte0]: 62
7870 11:17:54.637664 [Byte1]: 62
7871 11:17:54.642145
7872 11:17:54.642228 Set Vref, RX VrefLevel [Byte0]: 63
7873 11:17:54.645202 [Byte1]: 63
7874 11:17:54.649591
7875 11:17:54.649675 Set Vref, RX VrefLevel [Byte0]: 64
7876 11:17:54.653122 [Byte1]: 64
7877 11:17:54.657160
7878 11:17:54.657243 Set Vref, RX VrefLevel [Byte0]: 65
7879 11:17:54.660379 [Byte1]: 65
7880 11:17:54.665056
7881 11:17:54.665138 Set Vref, RX VrefLevel [Byte0]: 66
7882 11:17:54.668176 [Byte1]: 66
7883 11:17:54.672170
7884 11:17:54.672253 Set Vref, RX VrefLevel [Byte0]: 67
7885 11:17:54.675810 [Byte1]: 67
7886 11:17:54.680190
7887 11:17:54.682900 Set Vref, RX VrefLevel [Byte0]: 68
7888 11:17:54.682987 [Byte1]: 68
7889 11:17:54.687342
7890 11:17:54.687425 Set Vref, RX VrefLevel [Byte0]: 69
7891 11:17:54.690631 [Byte1]: 69
7892 11:17:54.695039
7893 11:17:54.695122 Set Vref, RX VrefLevel [Byte0]: 70
7894 11:17:54.698690 [Byte1]: 70
7895 11:17:54.702735
7896 11:17:54.702819 Set Vref, RX VrefLevel [Byte0]: 71
7897 11:17:54.705788 [Byte1]: 71
7898 11:17:54.710069
7899 11:17:54.710150 Set Vref, RX VrefLevel [Byte0]: 72
7900 11:17:54.716681 [Byte1]: 72
7901 11:17:54.716814
7902 11:17:54.719722 Set Vref, RX VrefLevel [Byte0]: 73
7903 11:17:54.723157 [Byte1]: 73
7904 11:17:54.723240
7905 11:17:54.726775 Set Vref, RX VrefLevel [Byte0]: 74
7906 11:17:54.729607 [Byte1]: 74
7907 11:17:54.729690
7908 11:17:54.733197 Set Vref, RX VrefLevel [Byte0]: 75
7909 11:17:54.736449 [Byte1]: 75
7910 11:17:54.740495
7911 11:17:54.740578 Set Vref, RX VrefLevel [Byte0]: 76
7912 11:17:54.743573 [Byte1]: 76
7913 11:17:54.747908
7914 11:17:54.747990 Set Vref, RX VrefLevel [Byte0]: 77
7915 11:17:54.751101 [Byte1]: 77
7916 11:17:54.755684
7917 11:17:54.755766 Set Vref, RX VrefLevel [Byte0]: 78
7918 11:17:54.758766 [Byte1]: 78
7919 11:17:54.763269
7920 11:17:54.763351 Set Vref, RX VrefLevel [Byte0]: 79
7921 11:17:54.766298 [Byte1]: 79
7922 11:17:54.770600
7923 11:17:54.770681 Set Vref, RX VrefLevel [Byte0]: 80
7924 11:17:54.774050 [Byte1]: 80
7925 11:17:54.778139
7926 11:17:54.778221 Final RX Vref Byte 0 = 62 to rank0
7927 11:17:54.781654 Final RX Vref Byte 1 = 62 to rank0
7928 11:17:54.784897 Final RX Vref Byte 0 = 62 to rank1
7929 11:17:54.788402 Final RX Vref Byte 1 = 62 to rank1==
7930 11:17:54.791366 Dram Type= 6, Freq= 0, CH_0, rank 0
7931 11:17:54.798289 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7932 11:17:54.798373 ==
7933 11:17:54.798438 DQS Delay:
7934 11:17:54.801682 DQS0 = 0, DQS1 = 0
7935 11:17:54.801763 DQM Delay:
7936 11:17:54.801828 DQM0 = 135, DQM1 = 124
7937 11:17:54.804502 DQ Delay:
7938 11:17:54.807879 DQ0 =136, DQ1 =138, DQ2 =132, DQ3 =132
7939 11:17:54.811471 DQ4 =138, DQ5 =124, DQ6 =142, DQ7 =142
7940 11:17:54.814413 DQ8 =114, DQ9 =110, DQ10 =126, DQ11 =118
7941 11:17:54.817884 DQ12 =128, DQ13 =128, DQ14 =136, DQ15 =134
7942 11:17:54.817991
7943 11:17:54.818070
7944 11:17:54.818129
7945 11:17:54.821190 [DramC_TX_OE_Calibration] TA2
7946 11:17:54.824387 Original DQ_B0 (3 6) =30, OEN = 27
7947 11:17:54.827393 Original DQ_B1 (3 6) =30, OEN = 27
7948 11:17:54.830822 24, 0x0, End_B0=24 End_B1=24
7949 11:17:54.834485 25, 0x0, End_B0=25 End_B1=25
7950 11:17:54.834569 26, 0x0, End_B0=26 End_B1=26
7951 11:17:54.837378 27, 0x0, End_B0=27 End_B1=27
7952 11:17:54.840816 28, 0x0, End_B0=28 End_B1=28
7953 11:17:54.844109 29, 0x0, End_B0=29 End_B1=29
7954 11:17:54.844197 30, 0x0, End_B0=30 End_B1=30
7955 11:17:54.847605 31, 0x4141, End_B0=30 End_B1=30
7956 11:17:54.850966 Byte0 end_step=30 best_step=27
7957 11:17:54.854178 Byte1 end_step=30 best_step=27
7958 11:17:54.857213 Byte0 TX OE(2T, 0.5T) = (3, 3)
7959 11:17:54.860635 Byte1 TX OE(2T, 0.5T) = (3, 3)
7960 11:17:54.860718
7961 11:17:54.860819
7962 11:17:54.867395 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c1a, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
7963 11:17:54.870138 CH0 RK0: MR19=303, MR18=1C1A
7964 11:17:54.876812 CH0_RK0: MR19=0x303, MR18=0x1C1A, DQSOSC=395, MR23=63, INC=23, DEC=15
7965 11:17:54.876898
7966 11:17:54.880515 ----->DramcWriteLeveling(PI) begin...
7967 11:17:54.880598 ==
7968 11:17:54.883968 Dram Type= 6, Freq= 0, CH_0, rank 1
7969 11:17:54.887130 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7970 11:17:54.887213 ==
7971 11:17:54.890263 Write leveling (Byte 0): 38 => 38
7972 11:17:54.893468 Write leveling (Byte 1): 30 => 30
7973 11:17:54.897030 DramcWriteLeveling(PI) end<-----
7974 11:17:54.897124
7975 11:17:54.897190 ==
7976 11:17:54.900130 Dram Type= 6, Freq= 0, CH_0, rank 1
7977 11:17:54.903567 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7978 11:17:54.906890 ==
7979 11:17:54.906984 [Gating] SW mode calibration
7980 11:17:54.916692 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7981 11:17:54.919677 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7982 11:17:54.923464 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7983 11:17:54.929630 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7984 11:17:54.933200 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7985 11:17:54.936544 1 4 12 | B1->B0 | 2625 3131 | 1 1 | (0 0) (1 1)
7986 11:17:54.943192 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7987 11:17:54.946088 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7988 11:17:54.949670 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7989 11:17:54.956327 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7990 11:17:54.959509 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7991 11:17:54.962516 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7992 11:17:54.969371 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7993 11:17:54.972651 1 5 12 | B1->B0 | 3434 2b2b | 1 1 | (1 0) (1 0)
7994 11:17:54.975906 1 5 16 | B1->B0 | 2b2b 2323 | 1 0 | (1 0) (1 0)
7995 11:17:54.982517 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7996 11:17:54.986106 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7997 11:17:54.988979 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7998 11:17:54.995876 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7999 11:17:54.999171 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8000 11:17:55.002319 1 6 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
8001 11:17:55.009000 1 6 12 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
8002 11:17:55.012398 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8003 11:17:55.015725 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8004 11:17:55.022062 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8005 11:17:55.025433 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8006 11:17:55.029138 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8007 11:17:55.035558 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8008 11:17:55.038648 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8009 11:17:55.042155 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8010 11:17:55.048746 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8011 11:17:55.052189 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8012 11:17:55.055145 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8013 11:17:55.062337 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8014 11:17:55.065063 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8015 11:17:55.068460 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8016 11:17:55.074993 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8017 11:17:55.078301 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8018 11:17:55.081479 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8019 11:17:55.088192 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8020 11:17:55.091514 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 11:17:55.095007 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 11:17:55.101665 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 11:17:55.104721 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 11:17:55.108418 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8025 11:17:55.114828 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8026 11:17:55.117978 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8027 11:17:55.121182 Total UI for P1: 0, mck2ui 16
8028 11:17:55.124718 best dqsien dly found for B0: ( 1, 9, 10)
8029 11:17:55.127856 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8030 11:17:55.131128 Total UI for P1: 0, mck2ui 16
8031 11:17:55.134337 best dqsien dly found for B1: ( 1, 9, 14)
8032 11:17:55.137677 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8033 11:17:55.141405 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8034 11:17:55.141504
8035 11:17:55.147663 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8036 11:17:55.151513 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8037 11:17:55.154155 [Gating] SW calibration Done
8038 11:17:55.154237 ==
8039 11:17:55.157546 Dram Type= 6, Freq= 0, CH_0, rank 1
8040 11:17:55.161295 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8041 11:17:55.161378 ==
8042 11:17:55.161443 RX Vref Scan: 0
8043 11:17:55.164289
8044 11:17:55.164370 RX Vref 0 -> 0, step: 1
8045 11:17:55.164434
8046 11:17:55.167425 RX Delay 0 -> 252, step: 8
8047 11:17:55.171126 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8048 11:17:55.174290 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8049 11:17:55.180940 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8050 11:17:55.184281 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8051 11:17:55.187511 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8052 11:17:55.190898 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8053 11:17:55.194318 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8054 11:17:55.200544 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8055 11:17:55.203829 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8056 11:17:55.207135 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8057 11:17:55.210554 iDelay=200, Bit 10, Center 123 (72 ~ 175) 104
8058 11:17:55.213964 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8059 11:17:55.220376 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8060 11:17:55.223650 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
8061 11:17:55.226968 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8062 11:17:55.230399 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8063 11:17:55.230513 ==
8064 11:17:55.233723 Dram Type= 6, Freq= 0, CH_0, rank 1
8065 11:17:55.240222 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8066 11:17:55.240305 ==
8067 11:17:55.240370 DQS Delay:
8068 11:17:55.243933 DQS0 = 0, DQS1 = 0
8069 11:17:55.244015 DQM Delay:
8070 11:17:55.244080 DQM0 = 136, DQM1 = 125
8071 11:17:55.246987 DQ Delay:
8072 11:17:55.250032 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =131
8073 11:17:55.253600 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8074 11:17:55.256689 DQ8 =119, DQ9 =111, DQ10 =123, DQ11 =123
8075 11:17:55.259959 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =135
8076 11:17:55.260040
8077 11:17:55.260104
8078 11:17:55.260165 ==
8079 11:17:55.263442 Dram Type= 6, Freq= 0, CH_0, rank 1
8080 11:17:55.270139 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8081 11:17:55.270221 ==
8082 11:17:55.270288
8083 11:17:55.270347
8084 11:17:55.270404 TX Vref Scan disable
8085 11:17:55.273518 == TX Byte 0 ==
8086 11:17:55.276715 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8087 11:17:55.283361 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8088 11:17:55.283469 == TX Byte 1 ==
8089 11:17:55.286604 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8090 11:17:55.292754 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8091 11:17:55.292882 ==
8092 11:17:55.296481 Dram Type= 6, Freq= 0, CH_0, rank 1
8093 11:17:55.299384 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8094 11:17:55.299466 ==
8095 11:17:55.313084
8096 11:17:55.316505 TX Vref early break, caculate TX vref
8097 11:17:55.319562 TX Vref=16, minBit 8, minWin=23, winSum=393
8098 11:17:55.323206 TX Vref=18, minBit 0, minWin=23, winSum=399
8099 11:17:55.326232 TX Vref=20, minBit 0, minWin=25, winSum=409
8100 11:17:55.329829 TX Vref=22, minBit 0, minWin=25, winSum=418
8101 11:17:55.332938 TX Vref=24, minBit 0, minWin=25, winSum=427
8102 11:17:55.339523 TX Vref=26, minBit 8, minWin=25, winSum=432
8103 11:17:55.343680 TX Vref=28, minBit 0, minWin=26, winSum=430
8104 11:17:55.346132 TX Vref=30, minBit 2, minWin=26, winSum=426
8105 11:17:55.349212 TX Vref=32, minBit 1, minWin=25, winSum=414
8106 11:17:55.352717 TX Vref=34, minBit 2, minWin=24, winSum=405
8107 11:17:55.359391 [TxChooseVref] Worse bit 0, Min win 26, Win sum 430, Final Vref 28
8108 11:17:55.359474
8109 11:17:55.363034 Final TX Range 0 Vref 28
8110 11:17:55.363117
8111 11:17:55.363180 ==
8112 11:17:55.366005 Dram Type= 6, Freq= 0, CH_0, rank 1
8113 11:17:55.369246 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8114 11:17:55.369328 ==
8115 11:17:55.369393
8116 11:17:55.369451
8117 11:17:55.372495 TX Vref Scan disable
8118 11:17:55.379201 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8119 11:17:55.379286 == TX Byte 0 ==
8120 11:17:55.382256 u2DelayCellOfst[0]=16 cells (5 PI)
8121 11:17:55.385728 u2DelayCellOfst[1]=20 cells (6 PI)
8122 11:17:55.389226 u2DelayCellOfst[2]=13 cells (4 PI)
8123 11:17:55.392146 u2DelayCellOfst[3]=13 cells (4 PI)
8124 11:17:55.395790 u2DelayCellOfst[4]=10 cells (3 PI)
8125 11:17:55.398878 u2DelayCellOfst[5]=0 cells (0 PI)
8126 11:17:55.402255 u2DelayCellOfst[6]=20 cells (6 PI)
8127 11:17:55.405634 u2DelayCellOfst[7]=20 cells (6 PI)
8128 11:17:55.408819 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8129 11:17:55.412072 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8130 11:17:55.415404 == TX Byte 1 ==
8131 11:17:55.418972 u2DelayCellOfst[8]=3 cells (1 PI)
8132 11:17:55.421993 u2DelayCellOfst[9]=0 cells (0 PI)
8133 11:17:55.425248 u2DelayCellOfst[10]=6 cells (2 PI)
8134 11:17:55.425331 u2DelayCellOfst[11]=3 cells (1 PI)
8135 11:17:55.428705 u2DelayCellOfst[12]=13 cells (4 PI)
8136 11:17:55.431956 u2DelayCellOfst[13]=13 cells (4 PI)
8137 11:17:55.435055 u2DelayCellOfst[14]=13 cells (4 PI)
8138 11:17:55.438420 u2DelayCellOfst[15]=10 cells (3 PI)
8139 11:17:55.444993 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8140 11:17:55.448423 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8141 11:17:55.448506 DramC Write-DBI on
8142 11:17:55.451588 ==
8143 11:17:55.451671 Dram Type= 6, Freq= 0, CH_0, rank 1
8144 11:17:55.458873 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8145 11:17:55.458961 ==
8146 11:17:55.459059
8147 11:17:55.459121
8148 11:17:55.461677 TX Vref Scan disable
8149 11:17:55.461760 == TX Byte 0 ==
8150 11:17:55.468231 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8151 11:17:55.468317 == TX Byte 1 ==
8152 11:17:55.471659 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8153 11:17:55.474733 DramC Write-DBI off
8154 11:17:55.474815
8155 11:17:55.474880 [DATLAT]
8156 11:17:55.478150 Freq=1600, CH0 RK1
8157 11:17:55.478233
8158 11:17:55.478298 DATLAT Default: 0xf
8159 11:17:55.481474 0, 0xFFFF, sum = 0
8160 11:17:55.481559 1, 0xFFFF, sum = 0
8161 11:17:55.484882 2, 0xFFFF, sum = 0
8162 11:17:55.484965 3, 0xFFFF, sum = 0
8163 11:17:55.487896 4, 0xFFFF, sum = 0
8164 11:17:55.487980 5, 0xFFFF, sum = 0
8165 11:17:55.491523 6, 0xFFFF, sum = 0
8166 11:17:55.491615 7, 0xFFFF, sum = 0
8167 11:17:55.494598 8, 0xFFFF, sum = 0
8168 11:17:55.498111 9, 0xFFFF, sum = 0
8169 11:17:55.498195 10, 0xFFFF, sum = 0
8170 11:17:55.501211 11, 0xFFFF, sum = 0
8171 11:17:55.501299 12, 0xFFFF, sum = 0
8172 11:17:55.504531 13, 0xFFFF, sum = 0
8173 11:17:55.504615 14, 0x0, sum = 1
8174 11:17:55.507974 15, 0x0, sum = 2
8175 11:17:55.508058 16, 0x0, sum = 3
8176 11:17:55.511172 17, 0x0, sum = 4
8177 11:17:55.511256 best_step = 15
8178 11:17:55.511322
8179 11:17:55.511382 ==
8180 11:17:55.514600 Dram Type= 6, Freq= 0, CH_0, rank 1
8181 11:17:55.517867 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8182 11:17:55.517951 ==
8183 11:17:55.521248 RX Vref Scan: 0
8184 11:17:55.521330
8185 11:17:55.524326 RX Vref 0 -> 0, step: 1
8186 11:17:55.524408
8187 11:17:55.524473 RX Delay 11 -> 252, step: 4
8188 11:17:55.531717 iDelay=191, Bit 0, Center 132 (83 ~ 182) 100
8189 11:17:55.534928 iDelay=191, Bit 1, Center 136 (87 ~ 186) 100
8190 11:17:55.538187 iDelay=191, Bit 2, Center 132 (83 ~ 182) 100
8191 11:17:55.541477 iDelay=191, Bit 3, Center 130 (83 ~ 178) 96
8192 11:17:55.545083 iDelay=191, Bit 4, Center 134 (83 ~ 186) 104
8193 11:17:55.551360 iDelay=191, Bit 5, Center 124 (75 ~ 174) 100
8194 11:17:55.554925 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8195 11:17:55.557962 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8196 11:17:55.561156 iDelay=191, Bit 8, Center 116 (67 ~ 166) 100
8197 11:17:55.564900 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8198 11:17:55.571390 iDelay=191, Bit 10, Center 124 (75 ~ 174) 100
8199 11:17:55.574527 iDelay=191, Bit 11, Center 120 (71 ~ 170) 100
8200 11:17:55.578098 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8201 11:17:55.581291 iDelay=191, Bit 13, Center 128 (79 ~ 178) 100
8202 11:17:55.588007 iDelay=191, Bit 14, Center 132 (79 ~ 186) 108
8203 11:17:55.591024 iDelay=191, Bit 15, Center 128 (75 ~ 182) 108
8204 11:17:55.591107 ==
8205 11:17:55.594530 Dram Type= 6, Freq= 0, CH_0, rank 1
8206 11:17:55.598014 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8207 11:17:55.598098 ==
8208 11:17:55.600905 DQS Delay:
8209 11:17:55.600987 DQS0 = 0, DQS1 = 0
8210 11:17:55.601053 DQM Delay:
8211 11:17:55.604436 DQM0 = 133, DQM1 = 123
8212 11:17:55.604519 DQ Delay:
8213 11:17:55.607712 DQ0 =132, DQ1 =136, DQ2 =132, DQ3 =130
8214 11:17:55.611151 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
8215 11:17:55.617603 DQ8 =116, DQ9 =110, DQ10 =124, DQ11 =120
8216 11:17:55.620723 DQ12 =126, DQ13 =128, DQ14 =132, DQ15 =128
8217 11:17:55.620842
8218 11:17:55.620907
8219 11:17:55.620967
8220 11:17:55.624101 [DramC_TX_OE_Calibration] TA2
8221 11:17:55.627129 Original DQ_B0 (3 6) =30, OEN = 27
8222 11:17:55.630416 Original DQ_B1 (3 6) =30, OEN = 27
8223 11:17:55.630500 24, 0x0, End_B0=24 End_B1=24
8224 11:17:55.634098 25, 0x0, End_B0=25 End_B1=25
8225 11:17:55.637396 26, 0x0, End_B0=26 End_B1=26
8226 11:17:55.640651 27, 0x0, End_B0=27 End_B1=27
8227 11:17:55.640738 28, 0x0, End_B0=28 End_B1=28
8228 11:17:55.644150 29, 0x0, End_B0=29 End_B1=29
8229 11:17:55.647658 30, 0x0, End_B0=30 End_B1=30
8230 11:17:55.650510 31, 0x4141, End_B0=30 End_B1=30
8231 11:17:55.654038 Byte0 end_step=30 best_step=27
8232 11:17:55.657331 Byte1 end_step=30 best_step=27
8233 11:17:55.657415 Byte0 TX OE(2T, 0.5T) = (3, 3)
8234 11:17:55.660640 Byte1 TX OE(2T, 0.5T) = (3, 3)
8235 11:17:55.660723
8236 11:17:55.660827
8237 11:17:55.670497 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d0b, (MSB)MR19= 0x303, tDQSOscB0 = 404 ps tDQSOscB1 = 395 ps
8238 11:17:55.673515 CH0 RK1: MR19=303, MR18=1D0B
8239 11:17:55.677009 CH0_RK1: MR19=0x303, MR18=0x1D0B, DQSOSC=395, MR23=63, INC=23, DEC=15
8240 11:17:55.681096 [RxdqsGatingPostProcess] freq 1600
8241 11:17:55.687436 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8242 11:17:55.690347 best DQS0 dly(2T, 0.5T) = (1, 1)
8243 11:17:55.693378 best DQS1 dly(2T, 0.5T) = (1, 1)
8244 11:17:55.696943 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8245 11:17:55.700160 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8246 11:17:55.703406 best DQS0 dly(2T, 0.5T) = (1, 1)
8247 11:17:55.706616 best DQS1 dly(2T, 0.5T) = (1, 1)
8248 11:17:55.706699 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8249 11:17:55.710123 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8250 11:17:55.713193 Pre-setting of DQS Precalculation
8251 11:17:55.720148 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8252 11:17:55.720231 ==
8253 11:17:55.723123 Dram Type= 6, Freq= 0, CH_1, rank 0
8254 11:17:55.726324 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8255 11:17:55.726407 ==
8256 11:17:55.733161 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8257 11:17:55.736565 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8258 11:17:55.739977 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8259 11:17:55.746576 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8260 11:17:55.755767 [CA 0] Center 42 (13~72) winsize 60
8261 11:17:55.758924 [CA 1] Center 42 (12~72) winsize 61
8262 11:17:55.763185 [CA 2] Center 38 (9~68) winsize 60
8263 11:17:55.765511 [CA 3] Center 37 (8~67) winsize 60
8264 11:17:55.769135 [CA 4] Center 37 (8~67) winsize 60
8265 11:17:55.772174 [CA 5] Center 37 (7~67) winsize 61
8266 11:17:55.772255
8267 11:17:55.775498 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8268 11:17:55.775580
8269 11:17:55.782023 [CATrainingPosCal] consider 1 rank data
8270 11:17:55.782105 u2DelayCellTimex100 = 290/100 ps
8271 11:17:55.788552 CA0 delay=42 (13~72),Diff = 5 PI (16 cell)
8272 11:17:55.792263 CA1 delay=42 (12~72),Diff = 5 PI (16 cell)
8273 11:17:55.795303 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8274 11:17:55.798916 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8275 11:17:55.802014 CA4 delay=37 (8~67),Diff = 0 PI (0 cell)
8276 11:17:55.805095 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8277 11:17:55.805176
8278 11:17:55.808707 CA PerBit enable=1, Macro0, CA PI delay=37
8279 11:17:55.808843
8280 11:17:55.812117 [CBTSetCACLKResult] CA Dly = 37
8281 11:17:55.815126 CS Dly: 8 (0~39)
8282 11:17:55.818690 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8283 11:17:55.822144 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8284 11:17:55.822226 ==
8285 11:17:55.825068 Dram Type= 6, Freq= 0, CH_1, rank 1
8286 11:17:55.831516 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8287 11:17:55.831599 ==
8288 11:17:55.835074 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8289 11:17:55.841518 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8290 11:17:55.845010 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8291 11:17:55.851626 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8292 11:17:55.858741 [CA 0] Center 42 (12~72) winsize 61
8293 11:17:55.862300 [CA 1] Center 42 (12~72) winsize 61
8294 11:17:55.865422 [CA 2] Center 37 (8~67) winsize 60
8295 11:17:55.868904 [CA 3] Center 37 (8~66) winsize 59
8296 11:17:55.872889 [CA 4] Center 37 (8~67) winsize 60
8297 11:17:55.875344 [CA 5] Center 36 (7~66) winsize 60
8298 11:17:55.875423
8299 11:17:55.878720 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8300 11:17:55.878799
8301 11:17:55.885422 [CATrainingPosCal] consider 2 rank data
8302 11:17:55.885503 u2DelayCellTimex100 = 290/100 ps
8303 11:17:55.892024 CA0 delay=42 (13~72),Diff = 6 PI (20 cell)
8304 11:17:55.895175 CA1 delay=42 (12~72),Diff = 6 PI (20 cell)
8305 11:17:55.898670 CA2 delay=38 (9~67),Diff = 2 PI (6 cell)
8306 11:17:55.901648 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8307 11:17:55.905552 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8308 11:17:55.908404 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8309 11:17:55.908483
8310 11:17:55.912116 CA PerBit enable=1, Macro0, CA PI delay=36
8311 11:17:55.912195
8312 11:17:55.915204 [CBTSetCACLKResult] CA Dly = 36
8313 11:17:55.918390 CS Dly: 10 (0~43)
8314 11:17:55.921623 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8315 11:17:55.925486 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8316 11:17:55.925565
8317 11:17:55.928231 ----->DramcWriteLeveling(PI) begin...
8318 11:17:55.928312 ==
8319 11:17:55.931601 Dram Type= 6, Freq= 0, CH_1, rank 0
8320 11:17:55.938309 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8321 11:17:55.938390 ==
8322 11:17:55.941572 Write leveling (Byte 0): 26 => 26
8323 11:17:55.945359 Write leveling (Byte 1): 27 => 27
8324 11:17:55.945438 DramcWriteLeveling(PI) end<-----
8325 11:17:55.945501
8326 11:17:55.947981 ==
8327 11:17:55.951777 Dram Type= 6, Freq= 0, CH_1, rank 0
8328 11:17:55.954993 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8329 11:17:55.955073 ==
8330 11:17:55.958042 [Gating] SW mode calibration
8331 11:17:55.964427 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8332 11:17:55.967971 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8333 11:17:55.974771 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8334 11:17:55.977668 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8335 11:17:55.981157 1 4 8 | B1->B0 | 2d2d 3232 | 0 0 | (0 0) (0 0)
8336 11:17:55.987594 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8337 11:17:55.990832 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8338 11:17:55.994736 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8339 11:17:56.001067 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8340 11:17:56.004192 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8341 11:17:56.007704 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8342 11:17:56.014380 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8343 11:17:56.017838 1 5 8 | B1->B0 | 2a2a 2727 | 0 0 | (0 0) (1 0)
8344 11:17:56.021045 1 5 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8345 11:17:56.027493 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8346 11:17:56.030684 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8347 11:17:56.033821 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8348 11:17:56.040569 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8349 11:17:56.044081 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8350 11:17:56.047087 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8351 11:17:56.054132 1 6 8 | B1->B0 | 3b3b 4343 | 0 0 | (0 0) (0 0)
8352 11:17:56.057021 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8353 11:17:56.060471 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8354 11:17:56.066769 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8355 11:17:56.069970 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8356 11:17:56.073422 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8357 11:17:56.080134 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8358 11:17:56.083467 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8359 11:17:56.086724 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8360 11:17:56.093056 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8361 11:17:56.096389 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8362 11:17:56.099541 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8363 11:17:56.106492 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8364 11:17:56.109478 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8365 11:17:56.112721 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8366 11:17:56.119506 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8367 11:17:56.122639 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8368 11:17:56.126356 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8369 11:17:56.132640 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8370 11:17:56.136198 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8371 11:17:56.139553 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8372 11:17:56.145893 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 11:17:56.149131 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 11:17:56.152535 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8375 11:17:56.159130 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8376 11:17:56.162228 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8377 11:17:56.165699 Total UI for P1: 0, mck2ui 16
8378 11:17:56.169179 best dqsien dly found for B0: ( 1, 9, 6)
8379 11:17:56.172207 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8380 11:17:56.175399 Total UI for P1: 0, mck2ui 16
8381 11:17:56.178719 best dqsien dly found for B1: ( 1, 9, 10)
8382 11:17:56.182383 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8383 11:17:56.185829 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8384 11:17:56.185911
8385 11:17:56.192022 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8386 11:17:56.195788 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8387 11:17:56.198661 [Gating] SW calibration Done
8388 11:17:56.198742 ==
8389 11:17:56.201857 Dram Type= 6, Freq= 0, CH_1, rank 0
8390 11:17:56.205588 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8391 11:17:56.205670 ==
8392 11:17:56.205733 RX Vref Scan: 0
8393 11:17:56.205793
8394 11:17:56.208593 RX Vref 0 -> 0, step: 1
8395 11:17:56.208700
8396 11:17:56.211928 RX Delay 0 -> 252, step: 8
8397 11:17:56.215280 iDelay=200, Bit 0, Center 139 (96 ~ 183) 88
8398 11:17:56.218413 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
8399 11:17:56.225220 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8400 11:17:56.228282 iDelay=200, Bit 3, Center 139 (88 ~ 191) 104
8401 11:17:56.231584 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8402 11:17:56.234849 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8403 11:17:56.238656 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8404 11:17:56.244891 iDelay=200, Bit 7, Center 135 (88 ~ 183) 96
8405 11:17:56.248469 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8406 11:17:56.251554 iDelay=200, Bit 9, Center 119 (72 ~ 167) 96
8407 11:17:56.254957 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8408 11:17:56.258305 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8409 11:17:56.264762 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8410 11:17:56.267803 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8411 11:17:56.271318 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8412 11:17:56.274587 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8413 11:17:56.274669 ==
8414 11:17:56.277772 Dram Type= 6, Freq= 0, CH_1, rank 0
8415 11:17:56.284632 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8416 11:17:56.284740 ==
8417 11:17:56.284839 DQS Delay:
8418 11:17:56.284929 DQS0 = 0, DQS1 = 0
8419 11:17:56.287957 DQM Delay:
8420 11:17:56.288038 DQM0 = 137, DQM1 = 130
8421 11:17:56.291026 DQ Delay:
8422 11:17:56.294205 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =139
8423 11:17:56.297936 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8424 11:17:56.301055 DQ8 =119, DQ9 =119, DQ10 =131, DQ11 =123
8425 11:17:56.304446 DQ12 =139, DQ13 =135, DQ14 =139, DQ15 =139
8426 11:17:56.304528
8427 11:17:56.304592
8428 11:17:56.304651 ==
8429 11:17:56.307414 Dram Type= 6, Freq= 0, CH_1, rank 0
8430 11:17:56.314148 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8431 11:17:56.314235 ==
8432 11:17:56.314302
8433 11:17:56.314362
8434 11:17:56.314420 TX Vref Scan disable
8435 11:17:56.317581 == TX Byte 0 ==
8436 11:17:56.320920 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8437 11:17:56.324194 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8438 11:17:56.327412 == TX Byte 1 ==
8439 11:17:56.330575 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8440 11:17:56.337119 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8441 11:17:56.337206 ==
8442 11:17:56.340482 Dram Type= 6, Freq= 0, CH_1, rank 0
8443 11:17:56.343736 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8444 11:17:56.343819 ==
8445 11:17:56.355885
8446 11:17:56.359028 TX Vref early break, caculate TX vref
8447 11:17:56.362570 TX Vref=16, minBit 10, minWin=22, winSum=370
8448 11:17:56.365738 TX Vref=18, minBit 10, minWin=22, winSum=383
8449 11:17:56.368893 TX Vref=20, minBit 10, minWin=23, winSum=392
8450 11:17:56.372090 TX Vref=22, minBit 0, minWin=24, winSum=403
8451 11:17:56.378689 TX Vref=24, minBit 10, minWin=25, winSum=417
8452 11:17:56.382069 TX Vref=26, minBit 1, minWin=25, winSum=420
8453 11:17:56.385409 TX Vref=28, minBit 12, minWin=25, winSum=420
8454 11:17:56.388671 TX Vref=30, minBit 12, minWin=24, winSum=414
8455 11:17:56.392164 TX Vref=32, minBit 13, minWin=23, winSum=400
8456 11:17:56.398483 TX Vref=34, minBit 10, minWin=23, winSum=390
8457 11:17:56.401798 [TxChooseVref] Worse bit 1, Min win 25, Win sum 420, Final Vref 26
8458 11:17:56.401901
8459 11:17:56.405254 Final TX Range 0 Vref 26
8460 11:17:56.405336
8461 11:17:56.405401 ==
8462 11:17:56.408568 Dram Type= 6, Freq= 0, CH_1, rank 0
8463 11:17:56.411691 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8464 11:17:56.415200 ==
8465 11:17:56.415293
8466 11:17:56.415359
8467 11:17:56.415420 TX Vref Scan disable
8468 11:17:56.421752 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8469 11:17:56.421855 == TX Byte 0 ==
8470 11:17:56.425122 u2DelayCellOfst[0]=16 cells (5 PI)
8471 11:17:56.428586 u2DelayCellOfst[1]=6 cells (2 PI)
8472 11:17:56.431898 u2DelayCellOfst[2]=0 cells (0 PI)
8473 11:17:56.435394 u2DelayCellOfst[3]=3 cells (1 PI)
8474 11:17:56.438810 u2DelayCellOfst[4]=6 cells (2 PI)
8475 11:17:56.441359 u2DelayCellOfst[5]=16 cells (5 PI)
8476 11:17:56.445197 u2DelayCellOfst[6]=13 cells (4 PI)
8477 11:17:56.448037 u2DelayCellOfst[7]=6 cells (2 PI)
8478 11:17:56.451621 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8479 11:17:56.454624 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8480 11:17:56.458008 == TX Byte 1 ==
8481 11:17:56.461137 u2DelayCellOfst[8]=0 cells (0 PI)
8482 11:17:56.464706 u2DelayCellOfst[9]=3 cells (1 PI)
8483 11:17:56.468068 u2DelayCellOfst[10]=10 cells (3 PI)
8484 11:17:56.471235 u2DelayCellOfst[11]=0 cells (0 PI)
8485 11:17:56.474267 u2DelayCellOfst[12]=13 cells (4 PI)
8486 11:17:56.477918 u2DelayCellOfst[13]=16 cells (5 PI)
8487 11:17:56.478000 u2DelayCellOfst[14]=20 cells (6 PI)
8488 11:17:56.481054 u2DelayCellOfst[15]=16 cells (5 PI)
8489 11:17:56.487546 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8490 11:17:56.491119 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8491 11:17:56.494463 DramC Write-DBI on
8492 11:17:56.494576 ==
8493 11:17:56.497887 Dram Type= 6, Freq= 0, CH_1, rank 0
8494 11:17:56.501298 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8495 11:17:56.501380 ==
8496 11:17:56.501444
8497 11:17:56.501503
8498 11:17:56.504361 TX Vref Scan disable
8499 11:17:56.504443 == TX Byte 0 ==
8500 11:17:56.510814 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8501 11:17:56.510899 == TX Byte 1 ==
8502 11:17:56.514440 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8503 11:17:56.517508 DramC Write-DBI off
8504 11:17:56.517615
8505 11:17:56.517698 [DATLAT]
8506 11:17:56.520677 Freq=1600, CH1 RK0
8507 11:17:56.520817
8508 11:17:56.520885 DATLAT Default: 0xf
8509 11:17:56.524252 0, 0xFFFF, sum = 0
8510 11:17:56.524335 1, 0xFFFF, sum = 0
8511 11:17:56.527414 2, 0xFFFF, sum = 0
8512 11:17:56.527497 3, 0xFFFF, sum = 0
8513 11:17:56.530661 4, 0xFFFF, sum = 0
8514 11:17:56.534002 5, 0xFFFF, sum = 0
8515 11:17:56.534085 6, 0xFFFF, sum = 0
8516 11:17:56.537534 7, 0xFFFF, sum = 0
8517 11:17:56.537616 8, 0xFFFF, sum = 0
8518 11:17:56.540806 9, 0xFFFF, sum = 0
8519 11:17:56.540889 10, 0xFFFF, sum = 0
8520 11:17:56.544072 11, 0xFFFF, sum = 0
8521 11:17:56.544155 12, 0xFFFF, sum = 0
8522 11:17:56.547094 13, 0xFFFF, sum = 0
8523 11:17:56.547177 14, 0x0, sum = 1
8524 11:17:56.550542 15, 0x0, sum = 2
8525 11:17:56.550625 16, 0x0, sum = 3
8526 11:17:56.553943 17, 0x0, sum = 4
8527 11:17:56.554026 best_step = 15
8528 11:17:56.554090
8529 11:17:56.554149 ==
8530 11:17:56.557045 Dram Type= 6, Freq= 0, CH_1, rank 0
8531 11:17:56.560488 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8532 11:17:56.563724 ==
8533 11:17:56.563805 RX Vref Scan: 1
8534 11:17:56.563871
8535 11:17:56.567012 Set Vref Range= 24 -> 127
8536 11:17:56.567093
8537 11:17:56.570549 RX Vref 24 -> 127, step: 1
8538 11:17:56.570630
8539 11:17:56.570694 RX Delay 19 -> 252, step: 4
8540 11:17:56.570753
8541 11:17:56.573937 Set Vref, RX VrefLevel [Byte0]: 24
8542 11:17:56.577067 [Byte1]: 24
8543 11:17:56.581070
8544 11:17:56.581152 Set Vref, RX VrefLevel [Byte0]: 25
8545 11:17:56.584318 [Byte1]: 25
8546 11:17:56.588292
8547 11:17:56.588374 Set Vref, RX VrefLevel [Byte0]: 26
8548 11:17:56.591718 [Byte1]: 26
8549 11:17:56.595987
8550 11:17:56.596069 Set Vref, RX VrefLevel [Byte0]: 27
8551 11:17:56.599233 [Byte1]: 27
8552 11:17:56.603529
8553 11:17:56.603611 Set Vref, RX VrefLevel [Byte0]: 28
8554 11:17:56.606981 [Byte1]: 28
8555 11:17:56.611268
8556 11:17:56.611353 Set Vref, RX VrefLevel [Byte0]: 29
8557 11:17:56.614276 [Byte1]: 29
8558 11:17:56.618907
8559 11:17:56.618989 Set Vref, RX VrefLevel [Byte0]: 30
8560 11:17:56.622076 [Byte1]: 30
8561 11:17:56.626333
8562 11:17:56.626415 Set Vref, RX VrefLevel [Byte0]: 31
8563 11:17:56.629357 [Byte1]: 31
8564 11:17:56.633760
8565 11:17:56.633842 Set Vref, RX VrefLevel [Byte0]: 32
8566 11:17:56.637044 [Byte1]: 32
8567 11:17:56.641176
8568 11:17:56.641258 Set Vref, RX VrefLevel [Byte0]: 33
8569 11:17:56.645050 [Byte1]: 33
8570 11:17:56.648799
8571 11:17:56.648894 Set Vref, RX VrefLevel [Byte0]: 34
8572 11:17:56.652360 [Byte1]: 34
8573 11:17:56.656449
8574 11:17:56.656557 Set Vref, RX VrefLevel [Byte0]: 35
8575 11:17:56.659866 [Byte1]: 35
8576 11:17:56.664448
8577 11:17:56.664530 Set Vref, RX VrefLevel [Byte0]: 36
8578 11:17:56.667295 [Byte1]: 36
8579 11:17:56.671674
8580 11:17:56.671756 Set Vref, RX VrefLevel [Byte0]: 37
8581 11:17:56.674938 [Byte1]: 37
8582 11:17:56.679143
8583 11:17:56.679224 Set Vref, RX VrefLevel [Byte0]: 38
8584 11:17:56.682402 [Byte1]: 38
8585 11:17:56.686932
8586 11:17:56.687014 Set Vref, RX VrefLevel [Byte0]: 39
8587 11:17:56.690390 [Byte1]: 39
8588 11:17:56.694671
8589 11:17:56.694753 Set Vref, RX VrefLevel [Byte0]: 40
8590 11:17:56.697756 [Byte1]: 40
8591 11:17:56.702259
8592 11:17:56.702341 Set Vref, RX VrefLevel [Byte0]: 41
8593 11:17:56.705084 [Byte1]: 41
8594 11:17:56.709574
8595 11:17:56.709656 Set Vref, RX VrefLevel [Byte0]: 42
8596 11:17:56.713226 [Byte1]: 42
8597 11:17:56.717002
8598 11:17:56.717083 Set Vref, RX VrefLevel [Byte0]: 43
8599 11:17:56.720596 [Byte1]: 43
8600 11:17:56.724646
8601 11:17:56.724755 Set Vref, RX VrefLevel [Byte0]: 44
8602 11:17:56.727964 [Byte1]: 44
8603 11:17:56.732130
8604 11:17:56.732214 Set Vref, RX VrefLevel [Byte0]: 45
8605 11:17:56.735512 [Byte1]: 45
8606 11:17:56.739638
8607 11:17:56.739724 Set Vref, RX VrefLevel [Byte0]: 46
8608 11:17:56.743234 [Byte1]: 46
8609 11:17:56.747216
8610 11:17:56.747324 Set Vref, RX VrefLevel [Byte0]: 47
8611 11:17:56.750661 [Byte1]: 47
8612 11:17:56.754921
8613 11:17:56.755003 Set Vref, RX VrefLevel [Byte0]: 48
8614 11:17:56.758264 [Byte1]: 48
8615 11:17:56.762457
8616 11:17:56.765918 Set Vref, RX VrefLevel [Byte0]: 49
8617 11:17:56.768762 [Byte1]: 49
8618 11:17:56.768856
8619 11:17:56.772222 Set Vref, RX VrefLevel [Byte0]: 50
8620 11:17:56.775408 [Byte1]: 50
8621 11:17:56.775491
8622 11:17:56.778896 Set Vref, RX VrefLevel [Byte0]: 51
8623 11:17:56.782364 [Byte1]: 51
8624 11:17:56.782449
8625 11:17:56.785369 Set Vref, RX VrefLevel [Byte0]: 52
8626 11:17:56.788734 [Byte1]: 52
8627 11:17:56.792911
8628 11:17:56.793000 Set Vref, RX VrefLevel [Byte0]: 53
8629 11:17:56.796407 [Byte1]: 53
8630 11:17:56.800391
8631 11:17:56.800476 Set Vref, RX VrefLevel [Byte0]: 54
8632 11:17:56.804102 [Byte1]: 54
8633 11:17:56.807717
8634 11:17:56.807821 Set Vref, RX VrefLevel [Byte0]: 55
8635 11:17:56.811244 [Byte1]: 55
8636 11:17:56.815494
8637 11:17:56.815581 Set Vref, RX VrefLevel [Byte0]: 56
8638 11:17:56.819328 [Byte1]: 56
8639 11:17:56.823072
8640 11:17:56.823160 Set Vref, RX VrefLevel [Byte0]: 57
8641 11:17:56.826309 [Byte1]: 57
8642 11:17:56.830803
8643 11:17:56.830888 Set Vref, RX VrefLevel [Byte0]: 58
8644 11:17:56.833808 [Byte1]: 58
8645 11:17:56.838339
8646 11:17:56.838487 Set Vref, RX VrefLevel [Byte0]: 59
8647 11:17:56.841702 [Byte1]: 59
8648 11:17:56.846193
8649 11:17:56.846277 Set Vref, RX VrefLevel [Byte0]: 60
8650 11:17:56.848957 [Byte1]: 60
8651 11:17:56.853534
8652 11:17:56.853619 Set Vref, RX VrefLevel [Byte0]: 61
8653 11:17:56.856552 [Byte1]: 61
8654 11:17:56.861005
8655 11:17:56.861091 Set Vref, RX VrefLevel [Byte0]: 62
8656 11:17:56.864385 [Byte1]: 62
8657 11:17:56.868927
8658 11:17:56.869015 Set Vref, RX VrefLevel [Byte0]: 63
8659 11:17:56.871908 [Byte1]: 63
8660 11:17:56.876333
8661 11:17:56.876418 Set Vref, RX VrefLevel [Byte0]: 64
8662 11:17:56.879304 [Byte1]: 64
8663 11:17:56.883646
8664 11:17:56.883732 Set Vref, RX VrefLevel [Byte0]: 65
8665 11:17:56.887141 [Byte1]: 65
8666 11:17:56.891220
8667 11:17:56.891305 Set Vref, RX VrefLevel [Byte0]: 66
8668 11:17:56.894816 [Byte1]: 66
8669 11:17:56.898766
8670 11:17:56.898851 Set Vref, RX VrefLevel [Byte0]: 67
8671 11:17:56.902355 [Byte1]: 67
8672 11:17:56.906310
8673 11:17:56.906404 Set Vref, RX VrefLevel [Byte0]: 68
8674 11:17:56.909826 [Byte1]: 68
8675 11:17:56.913931
8676 11:17:56.914025 Set Vref, RX VrefLevel [Byte0]: 69
8677 11:17:56.917370 [Byte1]: 69
8678 11:17:56.921591
8679 11:17:56.921676 Set Vref, RX VrefLevel [Byte0]: 70
8680 11:17:56.924925 [Byte1]: 70
8681 11:17:56.929211
8682 11:17:56.929297 Set Vref, RX VrefLevel [Byte0]: 71
8683 11:17:56.932411 [Byte1]: 71
8684 11:17:56.936908
8685 11:17:56.936994 Set Vref, RX VrefLevel [Byte0]: 72
8686 11:17:56.940089 [Byte1]: 72
8687 11:17:56.944373
8688 11:17:56.944459 Set Vref, RX VrefLevel [Byte0]: 73
8689 11:17:56.947442 [Byte1]: 73
8690 11:17:56.951718
8691 11:17:56.951805 Set Vref, RX VrefLevel [Byte0]: 74
8692 11:17:56.955122 [Byte1]: 74
8693 11:17:56.959416
8694 11:17:56.959502 Final RX Vref Byte 0 = 58 to rank0
8695 11:17:56.962604 Final RX Vref Byte 1 = 62 to rank0
8696 11:17:56.965889 Final RX Vref Byte 0 = 58 to rank1
8697 11:17:56.969119 Final RX Vref Byte 1 = 62 to rank1==
8698 11:17:56.972721 Dram Type= 6, Freq= 0, CH_1, rank 0
8699 11:17:56.979530 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8700 11:17:56.979623 ==
8701 11:17:56.979709 DQS Delay:
8702 11:17:56.982652 DQS0 = 0, DQS1 = 0
8703 11:17:56.982738 DQM Delay:
8704 11:17:56.982824 DQM0 = 134, DQM1 = 129
8705 11:17:56.985743 DQ Delay:
8706 11:17:56.989063 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =132
8707 11:17:56.992467 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =132
8708 11:17:56.995796 DQ8 =116, DQ9 =120, DQ10 =132, DQ11 =122
8709 11:17:56.998780 DQ12 =140, DQ13 =134, DQ14 =136, DQ15 =138
8710 11:17:56.998864
8711 11:17:56.998929
8712 11:17:56.998989
8713 11:17:57.002105 [DramC_TX_OE_Calibration] TA2
8714 11:17:57.005511 Original DQ_B0 (3 6) =30, OEN = 27
8715 11:17:57.009284 Original DQ_B1 (3 6) =30, OEN = 27
8716 11:17:57.012219 24, 0x0, End_B0=24 End_B1=24
8717 11:17:57.012305 25, 0x0, End_B0=25 End_B1=25
8718 11:17:57.015821 26, 0x0, End_B0=26 End_B1=26
8719 11:17:57.019178 27, 0x0, End_B0=27 End_B1=27
8720 11:17:57.022360 28, 0x0, End_B0=28 End_B1=28
8721 11:17:57.025297 29, 0x0, End_B0=29 End_B1=29
8722 11:17:57.025383 30, 0x0, End_B0=30 End_B1=30
8723 11:17:57.028548 31, 0x4545, End_B0=30 End_B1=30
8724 11:17:57.031824 Byte0 end_step=30 best_step=27
8725 11:17:57.035340 Byte1 end_step=30 best_step=27
8726 11:17:57.038468 Byte0 TX OE(2T, 0.5T) = (3, 3)
8727 11:17:57.041905 Byte1 TX OE(2T, 0.5T) = (3, 3)
8728 11:17:57.041993
8729 11:17:57.042059
8730 11:17:57.048409 [DQSOSCAuto] RK0, (LSB)MR18= 0x1624, (MSB)MR19= 0x303, tDQSOscB0 = 391 ps tDQSOscB1 = 398 ps
8731 11:17:57.051811 CH1 RK0: MR19=303, MR18=1624
8732 11:17:57.058630 CH1_RK0: MR19=0x303, MR18=0x1624, DQSOSC=391, MR23=63, INC=24, DEC=16
8733 11:17:57.058738
8734 11:17:57.061849 ----->DramcWriteLeveling(PI) begin...
8735 11:17:57.061938 ==
8736 11:17:57.065225 Dram Type= 6, Freq= 0, CH_1, rank 1
8737 11:17:57.068135 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8738 11:17:57.068224 ==
8739 11:17:57.071452 Write leveling (Byte 0): 24 => 24
8740 11:17:57.074856 Write leveling (Byte 1): 27 => 27
8741 11:17:57.077971 DramcWriteLeveling(PI) end<-----
8742 11:17:57.078064
8743 11:17:57.078130 ==
8744 11:17:57.081415 Dram Type= 6, Freq= 0, CH_1, rank 1
8745 11:17:57.084741 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8746 11:17:57.088164 ==
8747 11:17:57.088253 [Gating] SW mode calibration
8748 11:17:57.097803 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8749 11:17:57.101566 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8750 11:17:57.104410 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8751 11:17:57.111170 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8752 11:17:57.114777 1 4 8 | B1->B0 | 3333 2323 | 1 0 | (1 1) (0 0)
8753 11:17:57.117919 1 4 12 | B1->B0 | 3434 2929 | 1 1 | (1 1) (0 0)
8754 11:17:57.124587 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8755 11:17:57.127811 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8756 11:17:57.131164 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8757 11:17:57.137424 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8758 11:17:57.140690 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8759 11:17:57.143934 1 5 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8760 11:17:57.151161 1 5 8 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 0)
8761 11:17:57.153991 1 5 12 | B1->B0 | 2323 3232 | 0 1 | (1 0) (1 0)
8762 11:17:57.157272 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8763 11:17:57.163921 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8764 11:17:57.167178 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8765 11:17:57.170473 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8766 11:17:57.177133 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8767 11:17:57.180475 1 6 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8768 11:17:57.183894 1 6 8 | B1->B0 | 4545 2424 | 0 0 | (0 0) (0 0)
8769 11:17:57.190439 1 6 12 | B1->B0 | 4646 4343 | 0 0 | (0 0) (1 1)
8770 11:17:57.193868 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8771 11:17:57.197008 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8772 11:17:57.203662 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8773 11:17:57.207089 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8774 11:17:57.210524 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8775 11:17:57.216821 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8776 11:17:57.220284 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8777 11:17:57.223485 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8778 11:17:57.230144 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8779 11:17:57.233477 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8780 11:17:57.236702 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8781 11:17:57.243141 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 11:17:57.246780 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 11:17:57.249849 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 11:17:57.256638 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 11:17:57.259518 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 11:17:57.263170 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 11:17:57.269804 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 11:17:57.272939 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 11:17:57.276465 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 11:17:57.282917 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 11:17:57.286112 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 11:17:57.289285 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8793 11:17:57.296139 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8794 11:17:57.296243 Total UI for P1: 0, mck2ui 16
8795 11:17:57.302505 best dqsien dly found for B0: ( 1, 9, 8)
8796 11:17:57.302600 Total UI for P1: 0, mck2ui 16
8797 11:17:57.309171 best dqsien dly found for B1: ( 1, 9, 8)
8798 11:17:57.312601 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8799 11:17:57.315867 best DQS1 dly(MCK, UI, PI) = (1, 9, 8)
8800 11:17:57.315951
8801 11:17:57.318893 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8802 11:17:57.322361 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 8)
8803 11:17:57.325632 [Gating] SW calibration Done
8804 11:17:57.325715 ==
8805 11:17:57.328986 Dram Type= 6, Freq= 0, CH_1, rank 1
8806 11:17:57.332872 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8807 11:17:57.332956 ==
8808 11:17:57.335658 RX Vref Scan: 0
8809 11:17:57.335741
8810 11:17:57.335807 RX Vref 0 -> 0, step: 1
8811 11:17:57.335868
8812 11:17:57.338726 RX Delay 0 -> 252, step: 8
8813 11:17:57.342111 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8814 11:17:57.348452 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8815 11:17:57.351875 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8816 11:17:57.355260 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8817 11:17:57.358659 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8818 11:17:57.361931 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8819 11:17:57.368268 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8820 11:17:57.371942 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8821 11:17:57.375194 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8822 11:17:57.378652 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8823 11:17:57.381647 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8824 11:17:57.388090 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8825 11:17:57.391353 iDelay=200, Bit 12, Center 143 (88 ~ 199) 112
8826 11:17:57.394823 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8827 11:17:57.398093 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8828 11:17:57.405783 iDelay=200, Bit 15, Center 143 (88 ~ 199) 112
8829 11:17:57.405912 ==
8830 11:17:57.407896 Dram Type= 6, Freq= 0, CH_1, rank 1
8831 11:17:57.411481 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8832 11:17:57.411584 ==
8833 11:17:57.411658 DQS Delay:
8834 11:17:57.414388 DQS0 = 0, DQS1 = 0
8835 11:17:57.414476 DQM Delay:
8836 11:17:57.417843 DQM0 = 136, DQM1 = 132
8837 11:17:57.417932 DQ Delay:
8838 11:17:57.420873 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8839 11:17:57.424220 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =135
8840 11:17:57.427517 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8841 11:17:57.430843 DQ12 =143, DQ13 =139, DQ14 =139, DQ15 =143
8842 11:17:57.434405
8843 11:17:57.434515
8844 11:17:57.434584 ==
8845 11:17:57.437515 Dram Type= 6, Freq= 0, CH_1, rank 1
8846 11:17:57.440934 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8847 11:17:57.441037 ==
8848 11:17:57.441106
8849 11:17:57.441167
8850 11:17:57.444117 TX Vref Scan disable
8851 11:17:57.444201 == TX Byte 0 ==
8852 11:17:57.450993 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8853 11:17:57.454241 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8854 11:17:57.454332 == TX Byte 1 ==
8855 11:17:57.461073 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8856 11:17:57.463850 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8857 11:17:57.463939 ==
8858 11:17:57.467369 Dram Type= 6, Freq= 0, CH_1, rank 1
8859 11:17:57.470587 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8860 11:17:57.470686 ==
8861 11:17:57.484447
8862 11:17:57.487660 TX Vref early break, caculate TX vref
8863 11:17:57.490912 TX Vref=16, minBit 9, minWin=23, winSum=388
8864 11:17:57.493847 TX Vref=18, minBit 5, minWin=24, winSum=396
8865 11:17:57.497613 TX Vref=20, minBit 9, minWin=24, winSum=407
8866 11:17:57.500665 TX Vref=22, minBit 13, minWin=24, winSum=413
8867 11:17:57.504054 TX Vref=24, minBit 9, minWin=25, winSum=417
8868 11:17:57.510460 TX Vref=26, minBit 0, minWin=26, winSum=428
8869 11:17:57.513851 TX Vref=28, minBit 12, minWin=25, winSum=424
8870 11:17:57.517493 TX Vref=30, minBit 10, minWin=24, winSum=416
8871 11:17:57.520727 TX Vref=32, minBit 10, minWin=24, winSum=409
8872 11:17:57.523784 TX Vref=34, minBit 0, minWin=24, winSum=401
8873 11:17:57.530727 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 26
8874 11:17:57.530827
8875 11:17:57.533825 Final TX Range 0 Vref 26
8876 11:17:57.533910
8877 11:17:57.533975 ==
8878 11:17:57.536979 Dram Type= 6, Freq= 0, CH_1, rank 1
8879 11:17:57.540529 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8880 11:17:57.540615 ==
8881 11:17:57.540680
8882 11:17:57.540740
8883 11:17:57.543831 TX Vref Scan disable
8884 11:17:57.550627 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8885 11:17:57.550726 == TX Byte 0 ==
8886 11:17:57.553950 u2DelayCellOfst[0]=13 cells (4 PI)
8887 11:17:57.556942 u2DelayCellOfst[1]=10 cells (3 PI)
8888 11:17:57.560340 u2DelayCellOfst[2]=0 cells (0 PI)
8889 11:17:57.563907 u2DelayCellOfst[3]=3 cells (1 PI)
8890 11:17:57.567022 u2DelayCellOfst[4]=6 cells (2 PI)
8891 11:17:57.570316 u2DelayCellOfst[5]=16 cells (5 PI)
8892 11:17:57.573682 u2DelayCellOfst[6]=16 cells (5 PI)
8893 11:17:57.576956 u2DelayCellOfst[7]=6 cells (2 PI)
8894 11:17:57.580361 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8895 11:17:57.583743 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8896 11:17:57.586996 == TX Byte 1 ==
8897 11:17:57.589939 u2DelayCellOfst[8]=0 cells (0 PI)
8898 11:17:57.590033 u2DelayCellOfst[9]=3 cells (1 PI)
8899 11:17:57.593491 u2DelayCellOfst[10]=10 cells (3 PI)
8900 11:17:57.596696 u2DelayCellOfst[11]=3 cells (1 PI)
8901 11:17:57.599827 u2DelayCellOfst[12]=13 cells (4 PI)
8902 11:17:57.603521 u2DelayCellOfst[13]=16 cells (5 PI)
8903 11:17:57.606330 u2DelayCellOfst[14]=20 cells (6 PI)
8904 11:17:57.609930 u2DelayCellOfst[15]=16 cells (5 PI)
8905 11:17:57.616274 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8906 11:17:57.619699 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8907 11:17:57.619818 DramC Write-DBI on
8908 11:17:57.619887 ==
8909 11:17:57.623252 Dram Type= 6, Freq= 0, CH_1, rank 1
8910 11:17:57.629606 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8911 11:17:57.629732 ==
8912 11:17:57.629800
8913 11:17:57.629860
8914 11:17:57.629916 TX Vref Scan disable
8915 11:17:57.633752 == TX Byte 0 ==
8916 11:17:57.637263 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8917 11:17:57.640196 == TX Byte 1 ==
8918 11:17:57.643575 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8919 11:17:57.646900 DramC Write-DBI off
8920 11:17:57.646996
8921 11:17:57.647062 [DATLAT]
8922 11:17:57.647123 Freq=1600, CH1 RK1
8923 11:17:57.647181
8924 11:17:57.650015 DATLAT Default: 0xf
8925 11:17:57.653558 0, 0xFFFF, sum = 0
8926 11:17:57.653665 1, 0xFFFF, sum = 0
8927 11:17:57.656681 2, 0xFFFF, sum = 0
8928 11:17:57.656847 3, 0xFFFF, sum = 0
8929 11:17:57.660089 4, 0xFFFF, sum = 0
8930 11:17:57.660200 5, 0xFFFF, sum = 0
8931 11:17:57.663546 6, 0xFFFF, sum = 0
8932 11:17:57.663651 7, 0xFFFF, sum = 0
8933 11:17:57.666550 8, 0xFFFF, sum = 0
8934 11:17:57.666654 9, 0xFFFF, sum = 0
8935 11:17:57.669794 10, 0xFFFF, sum = 0
8936 11:17:57.669904 11, 0xFFFF, sum = 0
8937 11:17:57.673410 12, 0xFFFF, sum = 0
8938 11:17:57.673519 13, 0xFFFF, sum = 0
8939 11:17:57.676632 14, 0x0, sum = 1
8940 11:17:57.676762 15, 0x0, sum = 2
8941 11:17:57.679776 16, 0x0, sum = 3
8942 11:17:57.679870 17, 0x0, sum = 4
8943 11:17:57.683154 best_step = 15
8944 11:17:57.683249
8945 11:17:57.683318 ==
8946 11:17:57.686246 Dram Type= 6, Freq= 0, CH_1, rank 1
8947 11:17:57.689748 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8948 11:17:57.689854 ==
8949 11:17:57.692775 RX Vref Scan: 0
8950 11:17:57.692882
8951 11:17:57.692950 RX Vref 0 -> 0, step: 1
8952 11:17:57.693012
8953 11:17:57.696077 RX Delay 19 -> 252, step: 4
8954 11:17:57.703086 iDelay=195, Bit 0, Center 136 (91 ~ 182) 92
8955 11:17:57.706265 iDelay=195, Bit 1, Center 130 (83 ~ 178) 96
8956 11:17:57.710001 iDelay=195, Bit 2, Center 120 (71 ~ 170) 100
8957 11:17:57.713134 iDelay=195, Bit 3, Center 132 (83 ~ 182) 100
8958 11:17:57.716215 iDelay=195, Bit 4, Center 134 (87 ~ 182) 96
8959 11:17:57.719329 iDelay=195, Bit 5, Center 144 (99 ~ 190) 92
8960 11:17:57.726171 iDelay=195, Bit 6, Center 142 (95 ~ 190) 96
8961 11:17:57.729356 iDelay=195, Bit 7, Center 132 (83 ~ 182) 100
8962 11:17:57.732693 iDelay=195, Bit 8, Center 112 (63 ~ 162) 100
8963 11:17:57.735958 iDelay=195, Bit 9, Center 120 (71 ~ 170) 100
8964 11:17:57.742586 iDelay=195, Bit 10, Center 130 (79 ~ 182) 104
8965 11:17:57.745944 iDelay=195, Bit 11, Center 126 (75 ~ 178) 104
8966 11:17:57.749071 iDelay=195, Bit 12, Center 138 (87 ~ 190) 104
8967 11:17:57.752465 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
8968 11:17:57.755743 iDelay=195, Bit 14, Center 138 (91 ~ 186) 96
8969 11:17:57.762120 iDelay=195, Bit 15, Center 140 (87 ~ 194) 108
8970 11:17:57.762211 ==
8971 11:17:57.765533 Dram Type= 6, Freq= 0, CH_1, rank 1
8972 11:17:57.768921 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8973 11:17:57.769006 ==
8974 11:17:57.769072 DQS Delay:
8975 11:17:57.772089 DQS0 = 0, DQS1 = 0
8976 11:17:57.772184 DQM Delay:
8977 11:17:57.775522 DQM0 = 133, DQM1 = 130
8978 11:17:57.775604 DQ Delay:
8979 11:17:57.778702 DQ0 =136, DQ1 =130, DQ2 =120, DQ3 =132
8980 11:17:57.781868 DQ4 =134, DQ5 =144, DQ6 =142, DQ7 =132
8981 11:17:57.785486 DQ8 =112, DQ9 =120, DQ10 =130, DQ11 =126
8982 11:17:57.788598 DQ12 =138, DQ13 =138, DQ14 =138, DQ15 =140
8983 11:17:57.791946
8984 11:17:57.792030
8985 11:17:57.792095
8986 11:17:57.792154 [DramC_TX_OE_Calibration] TA2
8987 11:17:57.795089 Original DQ_B0 (3 6) =30, OEN = 27
8988 11:17:57.798918 Original DQ_B1 (3 6) =30, OEN = 27
8989 11:17:57.802015 24, 0x0, End_B0=24 End_B1=24
8990 11:17:57.805211 25, 0x0, End_B0=25 End_B1=25
8991 11:17:57.808269 26, 0x0, End_B0=26 End_B1=26
8992 11:17:57.808356 27, 0x0, End_B0=27 End_B1=27
8993 11:17:57.811840 28, 0x0, End_B0=28 End_B1=28
8994 11:17:57.815059 29, 0x0, End_B0=29 End_B1=29
8995 11:17:57.818309 30, 0x0, End_B0=30 End_B1=30
8996 11:17:57.821543 31, 0x5151, End_B0=30 End_B1=30
8997 11:17:57.824611 Byte0 end_step=30 best_step=27
8998 11:17:57.824720 Byte1 end_step=30 best_step=27
8999 11:17:57.827800 Byte0 TX OE(2T, 0.5T) = (3, 3)
9000 11:17:57.831492 Byte1 TX OE(2T, 0.5T) = (3, 3)
9001 11:17:57.831599
9002 11:17:57.831669
9003 11:17:57.841268 [DQSOSCAuto] RK1, (LSB)MR18= 0x1b06, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 396 ps
9004 11:17:57.841408 CH1 RK1: MR19=303, MR18=1B06
9005 11:17:57.847619 CH1_RK1: MR19=0x303, MR18=0x1B06, DQSOSC=396, MR23=63, INC=23, DEC=15
9006 11:17:57.851129 [RxdqsGatingPostProcess] freq 1600
9007 11:17:57.857582 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9008 11:17:57.860678 best DQS0 dly(2T, 0.5T) = (1, 1)
9009 11:17:57.864068 best DQS1 dly(2T, 0.5T) = (1, 1)
9010 11:17:57.867481 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9011 11:17:57.871009 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9012 11:17:57.874181 best DQS0 dly(2T, 0.5T) = (1, 1)
9013 11:17:57.874300 best DQS1 dly(2T, 0.5T) = (1, 1)
9014 11:17:57.877224 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9015 11:17:57.880523 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9016 11:17:57.883651 Pre-setting of DQS Precalculation
9017 11:17:57.890456 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9018 11:17:57.897518 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9019 11:17:57.903664 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9020 11:17:57.903788
9021 11:17:57.903859
9022 11:17:57.906958 [Calibration Summary] 3200 Mbps
9023 11:17:57.910260 CH 0, Rank 0
9024 11:17:57.910355 SW Impedance : PASS
9025 11:17:57.913950 DUTY Scan : NO K
9026 11:17:57.914041 ZQ Calibration : PASS
9027 11:17:57.916939 Jitter Meter : NO K
9028 11:17:57.920534 CBT Training : PASS
9029 11:17:57.920657 Write leveling : PASS
9030 11:17:57.923659 RX DQS gating : PASS
9031 11:17:57.927126 RX DQ/DQS(RDDQC) : PASS
9032 11:17:57.927232 TX DQ/DQS : PASS
9033 11:17:57.930244 RX DATLAT : PASS
9034 11:17:57.933573 RX DQ/DQS(Engine): PASS
9035 11:17:57.933716 TX OE : PASS
9036 11:17:57.937050 All Pass.
9037 11:17:57.937174
9038 11:17:57.937247 CH 0, Rank 1
9039 11:17:57.940483 SW Impedance : PASS
9040 11:17:57.940595 DUTY Scan : NO K
9041 11:17:57.943406 ZQ Calibration : PASS
9042 11:17:57.946997 Jitter Meter : NO K
9043 11:17:57.947096 CBT Training : PASS
9044 11:17:57.949927 Write leveling : PASS
9045 11:17:57.953257 RX DQS gating : PASS
9046 11:17:57.953350 RX DQ/DQS(RDDQC) : PASS
9047 11:17:57.956719 TX DQ/DQS : PASS
9048 11:17:57.959989 RX DATLAT : PASS
9049 11:17:57.960074 RX DQ/DQS(Engine): PASS
9050 11:17:57.963307 TX OE : PASS
9051 11:17:57.963395 All Pass.
9052 11:17:57.963462
9053 11:17:57.966784 CH 1, Rank 0
9054 11:17:57.966871 SW Impedance : PASS
9055 11:17:57.969699 DUTY Scan : NO K
9056 11:17:57.973101 ZQ Calibration : PASS
9057 11:17:57.973207 Jitter Meter : NO K
9058 11:17:57.976622 CBT Training : PASS
9059 11:17:57.976721 Write leveling : PASS
9060 11:17:57.980214 RX DQS gating : PASS
9061 11:17:57.983073 RX DQ/DQS(RDDQC) : PASS
9062 11:17:57.983160 TX DQ/DQS : PASS
9063 11:17:57.986577 RX DATLAT : PASS
9064 11:17:57.989843 RX DQ/DQS(Engine): PASS
9065 11:17:57.989928 TX OE : PASS
9066 11:17:57.992871 All Pass.
9067 11:17:57.992957
9068 11:17:57.993024 CH 1, Rank 1
9069 11:17:57.996771 SW Impedance : PASS
9070 11:17:57.996873 DUTY Scan : NO K
9071 11:17:57.999661 ZQ Calibration : PASS
9072 11:17:58.002865 Jitter Meter : NO K
9073 11:17:58.002960 CBT Training : PASS
9074 11:17:58.006129 Write leveling : PASS
9075 11:17:58.009468 RX DQS gating : PASS
9076 11:17:58.009557 RX DQ/DQS(RDDQC) : PASS
9077 11:17:58.012660 TX DQ/DQS : PASS
9078 11:17:58.016571 RX DATLAT : PASS
9079 11:17:58.016669 RX DQ/DQS(Engine): PASS
9080 11:17:58.019533 TX OE : PASS
9081 11:17:58.019625 All Pass.
9082 11:17:58.019693
9083 11:17:58.022816 DramC Write-DBI on
9084 11:17:58.026094 PER_BANK_REFRESH: Hybrid Mode
9085 11:17:58.026178 TX_TRACKING: ON
9086 11:17:58.035944 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9087 11:17:58.042563 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9088 11:17:58.049083 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9089 11:17:58.052624 [FAST_K] Save calibration result to emmc
9090 11:17:58.055747 sync common calibartion params.
9091 11:17:58.059006 sync cbt_mode0:1, 1:1
9092 11:17:58.062789 dram_init: ddr_geometry: 2
9093 11:17:58.062874 dram_init: ddr_geometry: 2
9094 11:17:58.066070 dram_init: ddr_geometry: 2
9095 11:17:58.069105 0:dram_rank_size:100000000
9096 11:17:58.072611 1:dram_rank_size:100000000
9097 11:17:58.075614 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9098 11:17:58.079408 DFS_SHUFFLE_HW_MODE: ON
9099 11:17:58.082324 dramc_set_vcore_voltage set vcore to 725000
9100 11:17:58.085734 Read voltage for 1600, 0
9101 11:17:58.085821 Vio18 = 0
9102 11:17:58.085888 Vcore = 725000
9103 11:17:58.089242 Vdram = 0
9104 11:17:58.089326 Vddq = 0
9105 11:17:58.089392 Vmddr = 0
9106 11:17:58.092333 switch to 3200 Mbps bootup
9107 11:17:58.095767 [DramcRunTimeConfig]
9108 11:17:58.095853 PHYPLL
9109 11:17:58.095920 DPM_CONTROL_AFTERK: ON
9110 11:17:58.099029 PER_BANK_REFRESH: ON
9111 11:17:58.102228 REFRESH_OVERHEAD_REDUCTION: ON
9112 11:17:58.102315 CMD_PICG_NEW_MODE: OFF
9113 11:17:58.105625 XRTWTW_NEW_MODE: ON
9114 11:17:58.109081 XRTRTR_NEW_MODE: ON
9115 11:17:58.109169 TX_TRACKING: ON
9116 11:17:58.112333 RDSEL_TRACKING: OFF
9117 11:17:58.112420 DQS Precalculation for DVFS: ON
9118 11:17:58.115429 RX_TRACKING: OFF
9119 11:17:58.115529 HW_GATING DBG: ON
9120 11:17:58.118619 ZQCS_ENABLE_LP4: ON
9121 11:17:58.118703 RX_PICG_NEW_MODE: ON
9122 11:17:58.122556 TX_PICG_NEW_MODE: ON
9123 11:17:58.125260 ENABLE_RX_DCM_DPHY: ON
9124 11:17:58.128656 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9125 11:17:58.128759 DUMMY_READ_FOR_TRACKING: OFF
9126 11:17:58.131983 !!! SPM_CONTROL_AFTERK: OFF
9127 11:17:58.135521 !!! SPM could not control APHY
9128 11:17:58.138822 IMPEDANCE_TRACKING: ON
9129 11:17:58.138907 TEMP_SENSOR: ON
9130 11:17:58.141916 HW_SAVE_FOR_SR: OFF
9131 11:17:58.142001 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9132 11:17:58.148678 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9133 11:17:58.148794 Read ODT Tracking: ON
9134 11:17:58.151973 Refresh Rate DeBounce: ON
9135 11:17:58.155210 DFS_NO_QUEUE_FLUSH: ON
9136 11:17:58.158649 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9137 11:17:58.158745 ENABLE_DFS_RUNTIME_MRW: OFF
9138 11:17:58.161603 DDR_RESERVE_NEW_MODE: ON
9139 11:17:58.165331 MR_CBT_SWITCH_FREQ: ON
9140 11:17:58.165428 =========================
9141 11:17:58.184805 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9142 11:17:58.188047 dram_init: ddr_geometry: 2
9143 11:17:58.206231 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9144 11:17:58.209512 dram_init: dram init end (result: 0)
9145 11:17:58.216072 DRAM-K: Full calibration passed in 24487 msecs
9146 11:17:58.219565 MRC: failed to locate region type 0.
9147 11:17:58.219675 DRAM rank0 size:0x100000000,
9148 11:17:58.223109 DRAM rank1 size=0x100000000
9149 11:17:58.232916 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9150 11:17:58.239107 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9151 11:17:58.245740 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9152 11:17:58.255656 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9153 11:17:58.255745 DRAM rank0 size:0x100000000,
9154 11:17:58.259294 DRAM rank1 size=0x100000000
9155 11:17:58.259383 CBMEM:
9156 11:17:58.262613 IMD: root @ 0xfffff000 254 entries.
9157 11:17:58.265576 IMD: root @ 0xffffec00 62 entries.
9158 11:17:58.269358 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9159 11:17:58.275705 WARNING: RO_VPD is uninitialized or empty.
9160 11:17:58.278782 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9161 11:17:58.286311 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9162 11:17:58.299346 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9163 11:17:58.310403 BS: romstage times (exec / console): total (unknown) / 23993 ms
9164 11:17:58.310558
9165 11:17:58.310656
9166 11:17:58.320378 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9167 11:17:58.323740 ARM64: Exception handlers installed.
9168 11:17:58.326971 ARM64: Testing exception
9169 11:17:58.330096 ARM64: Done test exception
9170 11:17:58.330201 Enumerating buses...
9171 11:17:58.333680 Show all devs... Before device enumeration.
9172 11:17:58.336635 Root Device: enabled 1
9173 11:17:58.339920 CPU_CLUSTER: 0: enabled 1
9174 11:17:58.340036 CPU: 00: enabled 1
9175 11:17:58.343499 Compare with tree...
9176 11:17:58.343590 Root Device: enabled 1
9177 11:17:58.346811 CPU_CLUSTER: 0: enabled 1
9178 11:17:58.350095 CPU: 00: enabled 1
9179 11:17:58.350191 Root Device scanning...
9180 11:17:58.353684 scan_static_bus for Root Device
9181 11:17:58.356545 CPU_CLUSTER: 0 enabled
9182 11:17:58.360202 scan_static_bus for Root Device done
9183 11:17:58.363222 scan_bus: bus Root Device finished in 8 msecs
9184 11:17:58.363306 done
9185 11:17:58.369957 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9186 11:17:58.373258 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9187 11:17:58.379838 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9188 11:17:58.383078 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9189 11:17:58.386306 Allocating resources...
9190 11:17:58.389574 Reading resources...
9191 11:17:58.392889 Root Device read_resources bus 0 link: 0
9192 11:17:58.396178 DRAM rank0 size:0x100000000,
9193 11:17:58.396259 DRAM rank1 size=0x100000000
9194 11:17:58.399669 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9195 11:17:58.403419 CPU: 00 missing read_resources
9196 11:17:58.409782 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9197 11:17:58.413015 Root Device read_resources bus 0 link: 0 done
9198 11:17:58.413102 Done reading resources.
9199 11:17:58.419426 Show resources in subtree (Root Device)...After reading.
9200 11:17:58.422731 Root Device child on link 0 CPU_CLUSTER: 0
9201 11:17:58.426520 CPU_CLUSTER: 0 child on link 0 CPU: 00
9202 11:17:58.436130 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9203 11:17:58.436289 CPU: 00
9204 11:17:58.439376 Root Device assign_resources, bus 0 link: 0
9205 11:17:58.442706 CPU_CLUSTER: 0 missing set_resources
9206 11:17:58.449428 Root Device assign_resources, bus 0 link: 0 done
9207 11:17:58.449515 Done setting resources.
9208 11:17:58.455762 Show resources in subtree (Root Device)...After assigning values.
9209 11:17:58.459045 Root Device child on link 0 CPU_CLUSTER: 0
9210 11:17:58.462635 CPU_CLUSTER: 0 child on link 0 CPU: 00
9211 11:17:58.472599 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9212 11:17:58.472760 CPU: 00
9213 11:17:58.476103 Done allocating resources.
9214 11:17:58.482901 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9215 11:17:58.483062 Enabling resources...
9216 11:17:58.483134 done.
9217 11:17:58.488950 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9218 11:17:58.492259 Initializing devices...
9219 11:17:58.492428 Root Device init
9220 11:17:58.495674 init hardware done!
9221 11:17:58.495825 0x00000018: ctrlr->caps
9222 11:17:58.498928 52.000 MHz: ctrlr->f_max
9223 11:17:58.502391 0.400 MHz: ctrlr->f_min
9224 11:17:58.502525 0x40ff8080: ctrlr->voltages
9225 11:17:58.505621 sclk: 390625
9226 11:17:58.505806 Bus Width = 1
9227 11:17:58.505936 sclk: 390625
9228 11:17:58.509013 Bus Width = 1
9229 11:17:58.509134 Early init status = 3
9230 11:17:58.515226 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9231 11:17:58.519004 in-header: 03 fc 00 00 01 00 00 00
9232 11:17:58.522240 in-data: 00
9233 11:17:58.525091 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9234 11:17:58.529405 in-header: 03 fd 00 00 00 00 00 00
9235 11:17:58.532953 in-data:
9236 11:17:58.536591 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9237 11:17:58.540251 in-header: 03 fc 00 00 01 00 00 00
9238 11:17:58.544034 in-data: 00
9239 11:17:58.547124 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9240 11:17:58.552700 in-header: 03 fd 00 00 00 00 00 00
9241 11:17:58.556055 in-data:
9242 11:17:58.559252 [SSUSB] Setting up USB HOST controller...
9243 11:17:58.562593 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9244 11:17:58.565715 [SSUSB] phy power-on done.
9245 11:17:58.569602 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9246 11:17:58.576166 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9247 11:17:58.579275 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9248 11:17:58.585696 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9249 11:17:58.592434 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9250 11:17:58.599195 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9251 11:17:58.605444 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9252 11:17:58.612181 read SPI 0x705bc 0x1f6a: 923 us, 8712 KB/s, 69.696 Mbps
9253 11:17:58.615349 SPM: binary array size = 0x9dc
9254 11:17:58.618555 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9255 11:17:58.625391 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9256 11:17:58.632665 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9257 11:17:58.638422 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9258 11:17:58.641487 configure_display: Starting display init
9259 11:17:58.675863 anx7625_power_on_init: Init interface.
9260 11:17:58.679141 anx7625_disable_pd_protocol: Disabled PD feature.
9261 11:17:58.685411 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9262 11:17:58.710307 anx7625_start_dp_work: Secure OCM version=00
9263 11:17:58.713521 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9264 11:17:58.728418 sp_tx_get_edid_block: EDID Block = 1
9265 11:17:58.831119 Extracted contents:
9266 11:17:58.834167 header: 00 ff ff ff ff ff ff 00
9267 11:17:58.837780 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9268 11:17:58.841420 version: 01 04
9269 11:17:58.844404 basic params: 95 1f 11 78 0a
9270 11:17:58.847625 chroma info: 76 90 94 55 54 90 27 21 50 54
9271 11:17:58.851337 established: 00 00 00
9272 11:17:58.857617 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9273 11:17:58.864528 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9274 11:17:58.867586 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9275 11:17:58.874084 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9276 11:17:58.880477 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9277 11:17:58.883518 extensions: 00
9278 11:17:58.883953 checksum: fb
9279 11:17:58.884390
9280 11:17:58.890135 Manufacturer: IVO Model 57d Serial Number 0
9281 11:17:58.890623 Made week 0 of 2020
9282 11:17:58.893251 EDID version: 1.4
9283 11:17:58.893681 Digital display
9284 11:17:58.896939 6 bits per primary color channel
9285 11:17:58.897395 DisplayPort interface
9286 11:17:58.900413 Maximum image size: 31 cm x 17 cm
9287 11:17:58.903266 Gamma: 220%
9288 11:17:58.903698 Check DPMS levels
9289 11:17:58.910022 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9290 11:17:58.913346 First detailed timing is preferred timing
9291 11:17:58.913787 Established timings supported:
9292 11:17:58.917054 Standard timings supported:
9293 11:17:58.920022 Detailed timings
9294 11:17:58.923107 Hex of detail: 383680a07038204018303c0035ae10000019
9295 11:17:58.929942 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9296 11:17:58.933188 0780 0798 07c8 0820 hborder 0
9297 11:17:58.936418 0438 043b 0447 0458 vborder 0
9298 11:17:58.940043 -hsync -vsync
9299 11:17:58.940438 Did detailed timing
9300 11:17:58.946071 Hex of detail: 000000000000000000000000000000000000
9301 11:17:58.949762 Manufacturer-specified data, tag 0
9302 11:17:58.952881 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9303 11:17:58.956643 ASCII string: InfoVision
9304 11:17:58.959641 Hex of detail: 000000fe00523134304e574635205248200a
9305 11:17:58.962998 ASCII string: R140NWF5 RH
9306 11:17:58.963479 Checksum
9307 11:17:58.965956 Checksum: 0xfb (valid)
9308 11:17:58.969414 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9309 11:17:58.973430 DSI data_rate: 832800000 bps
9310 11:17:58.979392 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9311 11:17:58.982467 anx7625_parse_edid: pixelclock(138800).
9312 11:17:58.985884 hactive(1920), hsync(48), hfp(24), hbp(88)
9313 11:17:58.989065 vactive(1080), vsync(12), vfp(3), vbp(17)
9314 11:17:58.992457 anx7625_dsi_config: config dsi.
9315 11:17:58.998877 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9316 11:17:59.013143 anx7625_dsi_config: success to config DSI
9317 11:17:59.016177 anx7625_dp_start: MIPI phy setup OK.
9318 11:17:59.019370 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9319 11:17:59.023206 mtk_ddp_mode_set invalid vrefresh 60
9320 11:17:59.026381 main_disp_path_setup
9321 11:17:59.026848 ovl_layer_smi_id_en
9322 11:17:59.029366 ovl_layer_smi_id_en
9323 11:17:59.029741 ccorr_config
9324 11:17:59.030034 aal_config
9325 11:17:59.032701 gamma_config
9326 11:17:59.033104 postmask_config
9327 11:17:59.035967 dither_config
9328 11:17:59.039375 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9329 11:17:59.045933 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9330 11:17:59.049331 Root Device init finished in 553 msecs
9331 11:17:59.052658 CPU_CLUSTER: 0 init
9332 11:17:59.059702 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9333 11:17:59.065968 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9334 11:17:59.066472 APU_MBOX 0x190000b0 = 0x10001
9335 11:17:59.069312 APU_MBOX 0x190001b0 = 0x10001
9336 11:17:59.072537 APU_MBOX 0x190005b0 = 0x10001
9337 11:17:59.075898 APU_MBOX 0x190006b0 = 0x10001
9338 11:17:59.082386 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9339 11:17:59.091848 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9340 11:17:59.104459 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9341 11:17:59.111186 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9342 11:17:59.122839 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9343 11:17:59.131966 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9344 11:17:59.135593 CPU_CLUSTER: 0 init finished in 81 msecs
9345 11:17:59.138933 Devices initialized
9346 11:17:59.141614 Show all devs... After init.
9347 11:17:59.142035 Root Device: enabled 1
9348 11:17:59.145295 CPU_CLUSTER: 0: enabled 1
9349 11:17:59.148367 CPU: 00: enabled 1
9350 11:17:59.151728 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9351 11:17:59.155261 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9352 11:17:59.158182 ELOG: NV offset 0x57f000 size 0x1000
9353 11:17:59.164986 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9354 11:17:59.171454 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9355 11:17:59.174660 ELOG: Event(17) added with size 13 at 2023-06-05 11:17:56 UTC
9356 11:17:59.181542 out: cmd=0x121: 03 db 21 01 00 00 00 00
9357 11:17:59.184857 in-header: 03 3d 00 00 2c 00 00 00
9358 11:17:59.194579 in-data: 22 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9359 11:17:59.201203 ELOG: Event(A1) added with size 10 at 2023-06-05 11:17:56 UTC
9360 11:17:59.208417 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9361 11:17:59.214515 ELOG: Event(A0) added with size 9 at 2023-06-05 11:17:56 UTC
9362 11:17:59.217559 elog_add_boot_reason: Logged dev mode boot
9363 11:17:59.224702 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9364 11:17:59.225241 Finalize devices...
9365 11:17:59.227800 Devices finalized
9366 11:17:59.231074 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9367 11:17:59.234277 Writing coreboot table at 0xffe64000
9368 11:17:59.237633 0. 000000000010a000-0000000000113fff: RAMSTAGE
9369 11:17:59.244617 1. 0000000040000000-00000000400fffff: RAM
9370 11:17:59.247475 2. 0000000040100000-000000004032afff: RAMSTAGE
9371 11:17:59.250924 3. 000000004032b000-00000000545fffff: RAM
9372 11:17:59.254232 4. 0000000054600000-000000005465ffff: BL31
9373 11:17:59.257555 5. 0000000054660000-00000000ffe63fff: RAM
9374 11:17:59.264232 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9375 11:17:59.267755 7. 0000000100000000-000000023fffffff: RAM
9376 11:17:59.270627 Passing 5 GPIOs to payload:
9377 11:17:59.273816 NAME | PORT | POLARITY | VALUE
9378 11:17:59.280335 EC in RW | 0x000000aa | low | undefined
9379 11:17:59.283569 EC interrupt | 0x00000005 | low | undefined
9380 11:17:59.286877 TPM interrupt | 0x000000ab | high | undefined
9381 11:17:59.293671 SD card detect | 0x00000011 | high | undefined
9382 11:17:59.296805 speaker enable | 0x00000093 | high | undefined
9383 11:17:59.300518 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9384 11:17:59.303816 in-header: 03 f9 00 00 02 00 00 00
9385 11:17:59.307206 in-data: 02 00
9386 11:17:59.310014 ADC[4]: Raw value=901032 ID=7
9387 11:17:59.310442 ADC[3]: Raw value=213179 ID=1
9388 11:17:59.313503 RAM Code: 0x71
9389 11:17:59.316565 ADC[6]: Raw value=74502 ID=0
9390 11:17:59.317091 ADC[5]: Raw value=211703 ID=1
9391 11:17:59.320102 SKU Code: 0x1
9392 11:17:59.326744 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4ba3
9393 11:17:59.327270 coreboot table: 964 bytes.
9394 11:17:59.329880 IMD ROOT 0. 0xfffff000 0x00001000
9395 11:17:59.333064 IMD SMALL 1. 0xffffe000 0x00001000
9396 11:17:59.336275 RO MCACHE 2. 0xffffc000 0x00001104
9397 11:17:59.339771 CONSOLE 3. 0xfff7c000 0x00080000
9398 11:17:59.343602 FMAP 4. 0xfff7b000 0x00000452
9399 11:17:59.346225 TIME STAMP 5. 0xfff7a000 0x00000910
9400 11:17:59.349594 VBOOT WORK 6. 0xfff66000 0x00014000
9401 11:17:59.352870 RAMOOPS 7. 0xffe66000 0x00100000
9402 11:17:59.356275 COREBOOT 8. 0xffe64000 0x00002000
9403 11:17:59.359479 IMD small region:
9404 11:17:59.362641 IMD ROOT 0. 0xffffec00 0x00000400
9405 11:17:59.366219 VPD 1. 0xffffeba0 0x0000004c
9406 11:17:59.369211 MMC STATUS 2. 0xffffeb80 0x00000004
9407 11:17:59.375697 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9408 11:17:59.376126 Probing TPM: done!
9409 11:17:59.379455 Connected to device vid:did:rid of 1ae0:0028:00
9410 11:17:59.390893 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9411 11:17:59.394126 Initialized TPM device CR50 revision 0
9412 11:17:59.397489 Checking cr50 for pending updates
9413 11:17:59.401654 Reading cr50 TPM mode
9414 11:17:59.410333 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9415 11:17:59.416652 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9416 11:17:59.456872 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9417 11:17:59.460668 Checking segment from ROM address 0x40100000
9418 11:17:59.463520 Checking segment from ROM address 0x4010001c
9419 11:17:59.469955 Loading segment from ROM address 0x40100000
9420 11:17:59.470382 code (compression=0)
9421 11:17:59.479951 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9422 11:17:59.486729 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9423 11:17:59.487159 it's not compressed!
9424 11:17:59.493674 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9425 11:17:59.499900 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9426 11:17:59.517236 Loading segment from ROM address 0x4010001c
9427 11:17:59.517743 Entry Point 0x80000000
9428 11:17:59.520426 Loaded segments
9429 11:17:59.523794 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9430 11:17:59.530371 Jumping to boot code at 0x80000000(0xffe64000)
9431 11:17:59.537169 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9432 11:17:59.543789 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9433 11:17:59.551432 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9434 11:17:59.554984 Checking segment from ROM address 0x40100000
9435 11:17:59.558011 Checking segment from ROM address 0x4010001c
9436 11:17:59.565043 Loading segment from ROM address 0x40100000
9437 11:17:59.565470 code (compression=1)
9438 11:17:59.571379 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9439 11:17:59.581031 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9440 11:17:59.581460 using LZMA
9441 11:17:59.589729 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9442 11:17:59.596693 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9443 11:17:59.599705 Loading segment from ROM address 0x4010001c
9444 11:17:59.600310 Entry Point 0x54601000
9445 11:17:59.602835 Loaded segments
9446 11:17:59.606457 NOTICE: MT8192 bl31_setup
9447 11:17:59.613582 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9448 11:17:59.617025 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9449 11:17:59.620618 WARNING: region 0:
9450 11:17:59.624017 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9451 11:17:59.624538 WARNING: region 1:
9452 11:17:59.630359 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9453 11:17:59.633594 WARNING: region 2:
9454 11:17:59.636860 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9455 11:17:59.640508 WARNING: region 3:
9456 11:17:59.643123 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9457 11:17:59.646670 WARNING: region 4:
9458 11:17:59.653033 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9459 11:17:59.653604 WARNING: region 5:
9460 11:17:59.656492 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9461 11:17:59.660000 WARNING: region 6:
9462 11:17:59.663086 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9463 11:17:59.666357 WARNING: region 7:
9464 11:17:59.669909 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9465 11:17:59.676375 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9466 11:17:59.679869 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9467 11:17:59.682856 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9468 11:17:59.689567 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9469 11:17:59.692813 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9470 11:17:59.699600 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9471 11:17:59.702897 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9472 11:17:59.705920 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9473 11:17:59.712792 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9474 11:17:59.716451 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9475 11:17:59.719241 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9476 11:17:59.726110 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9477 11:17:59.729487 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9478 11:17:59.735885 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9479 11:17:59.739143 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9480 11:17:59.742592 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9481 11:17:59.749035 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9482 11:17:59.752558 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9483 11:17:59.755823 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9484 11:17:59.762303 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9485 11:17:59.765427 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9486 11:17:59.772232 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9487 11:17:59.775799 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9488 11:17:59.778811 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9489 11:17:59.785500 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9490 11:17:59.788793 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9491 11:17:59.795540 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9492 11:17:59.798918 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9493 11:17:59.805663 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9494 11:17:59.809247 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9495 11:17:59.812289 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9496 11:17:59.818983 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9497 11:17:59.822135 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9498 11:17:59.825443 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9499 11:17:59.829190 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9500 11:17:59.835758 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9501 11:17:59.839363 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9502 11:17:59.842333 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9503 11:17:59.846028 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9504 11:17:59.852737 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9505 11:17:59.855762 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9506 11:17:59.859012 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9507 11:17:59.862177 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9508 11:17:59.868616 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9509 11:17:59.872123 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9510 11:17:59.875306 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9511 11:17:59.878724 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9512 11:17:59.885594 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9513 11:17:59.888734 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9514 11:17:59.895410 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9515 11:17:59.899141 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9516 11:17:59.902200 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9517 11:17:59.908348 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9518 11:17:59.911970 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9519 11:17:59.918384 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9520 11:17:59.921947 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9521 11:17:59.928130 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9522 11:17:59.931672 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9523 11:17:59.938140 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9524 11:17:59.941435 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9525 11:17:59.945102 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9526 11:17:59.951445 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9527 11:17:59.954685 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9528 11:17:59.961511 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9529 11:17:59.964857 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9530 11:17:59.971420 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9531 11:17:59.974679 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9532 11:17:59.981254 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9533 11:17:59.984564 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9534 11:17:59.987775 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9535 11:17:59.994821 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9536 11:17:59.997856 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9537 11:18:00.004045 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9538 11:18:00.007777 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9539 11:18:00.014273 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9540 11:18:00.017390 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9541 11:18:00.024135 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9542 11:18:00.027369 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9543 11:18:00.030765 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9544 11:18:00.037630 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9545 11:18:00.040882 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9546 11:18:00.047170 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9547 11:18:00.050789 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9548 11:18:00.056990 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9549 11:18:00.060612 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9550 11:18:00.067512 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9551 11:18:00.070376 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9552 11:18:00.073512 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9553 11:18:00.080738 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9554 11:18:00.083965 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9555 11:18:00.090332 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9556 11:18:00.093465 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9557 11:18:00.100151 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9558 11:18:00.103191 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9559 11:18:00.109921 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9560 11:18:00.113375 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9561 11:18:00.117152 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9562 11:18:00.123341 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9563 11:18:00.126402 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9564 11:18:00.129640 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9565 11:18:00.132891 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9566 11:18:00.139952 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9567 11:18:00.143089 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9568 11:18:00.149946 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9569 11:18:00.153075 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9570 11:18:00.156656 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9571 11:18:00.163391 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9572 11:18:00.166187 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9573 11:18:00.173244 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9574 11:18:00.176426 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9575 11:18:00.179789 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9576 11:18:00.186242 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9577 11:18:00.189664 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9578 11:18:00.196127 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9579 11:18:00.199633 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9580 11:18:00.202737 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9581 11:18:00.209351 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9582 11:18:00.213062 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9583 11:18:00.216184 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9584 11:18:00.222691 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9585 11:18:00.225810 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9586 11:18:00.229520 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9587 11:18:00.232635 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9588 11:18:00.239395 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9589 11:18:00.242626 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9590 11:18:00.246148 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9591 11:18:00.252511 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9592 11:18:00.255839 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9593 11:18:00.262322 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9594 11:18:00.265804 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9595 11:18:00.268641 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9596 11:18:00.275548 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9597 11:18:00.278966 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9598 11:18:00.282370 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9599 11:18:00.288885 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9600 11:18:00.292109 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9601 11:18:00.299092 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9602 11:18:00.302278 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9603 11:18:00.305551 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9604 11:18:00.312172 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9605 11:18:00.315704 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9606 11:18:00.322134 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9607 11:18:00.325361 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9608 11:18:00.328599 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9609 11:18:00.335039 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9610 11:18:00.338798 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9611 11:18:00.345210 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9612 11:18:00.348683 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9613 11:18:00.351599 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9614 11:18:00.358116 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9615 11:18:00.361632 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9616 11:18:00.368168 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9617 11:18:00.371699 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9618 11:18:00.374933 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9619 11:18:00.381627 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9620 11:18:00.384966 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9621 11:18:00.391560 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9622 11:18:00.394907 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9623 11:18:00.397990 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9624 11:18:00.404551 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9625 11:18:00.407951 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9626 11:18:00.414752 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9627 11:18:00.417702 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9628 11:18:00.421093 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9629 11:18:00.428031 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9630 11:18:00.430975 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9631 11:18:00.437611 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9632 11:18:00.440678 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9633 11:18:00.444159 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9634 11:18:00.450911 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9635 11:18:00.453722 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9636 11:18:00.460645 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9637 11:18:00.463543 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9638 11:18:00.467666 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9639 11:18:00.473477 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9640 11:18:00.477384 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9641 11:18:00.483274 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9642 11:18:00.486954 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9643 11:18:00.490047 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9644 11:18:00.496678 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9645 11:18:00.500177 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9646 11:18:00.506530 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9647 11:18:00.510141 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9648 11:18:00.513546 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9649 11:18:00.520569 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9650 11:18:00.523203 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9651 11:18:00.530008 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9652 11:18:00.533575 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9653 11:18:00.536440 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9654 11:18:00.543354 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9655 11:18:00.546639 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9656 11:18:00.553381 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9657 11:18:00.556157 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9658 11:18:00.562979 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9659 11:18:00.565935 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9660 11:18:00.569354 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9661 11:18:00.575801 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9662 11:18:00.579286 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9663 11:18:00.586364 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9664 11:18:00.588924 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9665 11:18:00.595411 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9666 11:18:00.599064 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9667 11:18:00.602131 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9668 11:18:00.608841 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9669 11:18:00.611941 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9670 11:18:00.619027 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9671 11:18:00.622163 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9672 11:18:00.628524 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9673 11:18:00.632238 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9674 11:18:00.635055 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9675 11:18:00.642277 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9676 11:18:00.644885 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9677 11:18:00.651739 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9678 11:18:00.654841 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9679 11:18:00.661859 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9680 11:18:00.664674 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9681 11:18:00.668119 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9682 11:18:00.674868 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9683 11:18:00.678331 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9684 11:18:00.684672 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9685 11:18:00.687721 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9686 11:18:00.691301 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9687 11:18:00.697799 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9688 11:18:00.701235 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9689 11:18:00.707867 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9690 11:18:00.711024 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9691 11:18:00.717653 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9692 11:18:00.721026 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9693 11:18:00.724266 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9694 11:18:00.730924 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9695 11:18:00.734269 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9696 11:18:00.737545 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9697 11:18:00.740546 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9698 11:18:00.747078 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9699 11:18:00.750633 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9700 11:18:00.753910 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9701 11:18:00.760553 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9702 11:18:00.763853 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9703 11:18:00.767311 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9704 11:18:00.774193 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9705 11:18:00.777223 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9706 11:18:00.783632 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9707 11:18:00.786823 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9708 11:18:00.790146 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9709 11:18:00.797183 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9710 11:18:00.800444 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9711 11:18:00.807073 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9712 11:18:00.810799 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9713 11:18:00.813310 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9714 11:18:00.820290 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9715 11:18:00.823154 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9716 11:18:00.826357 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9717 11:18:00.832990 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9718 11:18:00.836557 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9719 11:18:00.839538 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9720 11:18:00.846557 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9721 11:18:00.849497 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9722 11:18:00.856018 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9723 11:18:00.859959 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9724 11:18:00.862810 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9725 11:18:00.869412 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9726 11:18:00.872985 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9727 11:18:00.879346 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9728 11:18:00.882275 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9729 11:18:00.885661 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9730 11:18:00.892785 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9731 11:18:00.895759 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9732 11:18:00.902212 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9733 11:18:00.905494 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9734 11:18:00.908924 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9735 11:18:00.912108 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9736 11:18:00.915282 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9737 11:18:00.922215 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9738 11:18:00.925758 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9739 11:18:00.928737 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9740 11:18:00.931956 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9741 11:18:00.938419 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9742 11:18:00.942026 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9743 11:18:00.945193 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9744 11:18:00.948669 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9745 11:18:00.955096 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9746 11:18:00.958284 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9747 11:18:00.961562 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9748 11:18:00.968069 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9749 11:18:00.971652 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9750 11:18:00.978212 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9751 11:18:00.981826 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9752 11:18:00.988252 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9753 11:18:00.991476 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9754 11:18:00.994542 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9755 11:18:01.001217 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9756 11:18:01.004760 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9757 11:18:01.010790 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9758 11:18:01.014327 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9759 11:18:01.020971 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9760 11:18:01.024105 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9761 11:18:01.027501 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9762 11:18:01.034305 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9763 11:18:01.037701 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9764 11:18:01.043992 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9765 11:18:01.047446 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9766 11:18:01.050471 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9767 11:18:01.057263 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9768 11:18:01.060674 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9769 11:18:01.067080 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9770 11:18:01.070774 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9771 11:18:01.073956 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9772 11:18:01.080406 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9773 11:18:01.083477 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9774 11:18:01.090092 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9775 11:18:01.093558 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9776 11:18:01.100028 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9777 11:18:01.103984 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9778 11:18:01.107234 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9779 11:18:01.113723 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9780 11:18:01.116600 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9781 11:18:01.123021 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9782 11:18:01.126883 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9783 11:18:01.133161 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9784 11:18:01.136584 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9785 11:18:01.139643 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9786 11:18:01.146596 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9787 11:18:01.149449 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9788 11:18:01.156479 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9789 11:18:01.159450 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9790 11:18:01.163107 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9791 11:18:01.169418 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9792 11:18:01.172630 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9793 11:18:01.179347 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9794 11:18:01.182826 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9795 11:18:01.185890 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9796 11:18:01.192488 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9797 11:18:01.195935 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9798 11:18:01.202420 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9799 11:18:01.205715 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9800 11:18:01.212192 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9801 11:18:01.215430 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9802 11:18:01.218806 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9803 11:18:01.225641 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9804 11:18:01.228580 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9805 11:18:01.235395 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9806 11:18:01.238623 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9807 11:18:01.245283 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9808 11:18:01.248474 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9809 11:18:01.251885 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9810 11:18:01.258345 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9811 11:18:01.261654 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9812 11:18:01.268405 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9813 11:18:01.271595 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9814 11:18:01.274837 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9815 11:18:01.281341 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9816 11:18:01.285190 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9817 11:18:01.291511 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9818 11:18:01.294940 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9819 11:18:01.298078 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9820 11:18:01.304739 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9821 11:18:01.308613 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9822 11:18:01.314487 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9823 11:18:01.317725 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9824 11:18:01.324228 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9825 11:18:01.327623 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9826 11:18:01.334370 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9827 11:18:01.337511 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9828 11:18:01.344328 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9829 11:18:01.347540 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9830 11:18:01.350581 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9831 11:18:01.357564 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9832 11:18:01.360933 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9833 11:18:01.367278 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9834 11:18:01.370462 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9835 11:18:01.377185 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9836 11:18:01.380681 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9837 11:18:01.387684 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9838 11:18:01.390404 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9839 11:18:01.393817 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9840 11:18:01.400212 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9841 11:18:01.403411 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9842 11:18:01.410204 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9843 11:18:01.413376 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9844 11:18:01.419954 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9845 11:18:01.423379 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9846 11:18:01.426752 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9847 11:18:01.433825 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9848 11:18:01.436579 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9849 11:18:01.443146 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9850 11:18:01.446828 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9851 11:18:01.453806 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9852 11:18:01.456683 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9853 11:18:01.463593 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9854 11:18:01.466241 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9855 11:18:01.469792 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9856 11:18:01.476399 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9857 11:18:01.479720 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9858 11:18:01.486048 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9859 11:18:01.489743 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9860 11:18:01.496297 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9861 11:18:01.499779 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9862 11:18:01.506204 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9863 11:18:01.509572 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9864 11:18:01.513067 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9865 11:18:01.519128 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9866 11:18:01.522692 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9867 11:18:01.529456 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9868 11:18:01.532706 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9869 11:18:01.535895 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9870 11:18:01.542540 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9871 11:18:01.545618 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9872 11:18:01.552846 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9873 11:18:01.555764 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9874 11:18:01.562423 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9875 11:18:01.565606 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9876 11:18:01.572049 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9877 11:18:01.575987 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9878 11:18:01.582250 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9879 11:18:01.585139 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9880 11:18:01.591763 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9881 11:18:01.594864 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9882 11:18:01.601384 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9883 11:18:01.605114 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9884 11:18:01.611707 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9885 11:18:01.615190 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9886 11:18:01.621927 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9887 11:18:01.624744 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9888 11:18:01.631523 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9889 11:18:01.634539 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9890 11:18:01.641415 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9891 11:18:01.644676 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9892 11:18:01.650998 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9893 11:18:01.654938 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9894 11:18:01.661082 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9895 11:18:01.664151 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9896 11:18:01.670941 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9897 11:18:01.674224 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9898 11:18:01.680661 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9899 11:18:01.684306 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9900 11:18:01.687821 INFO: [APUAPC] vio 0
9901 11:18:01.690984 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9902 11:18:01.697318 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9903 11:18:01.700664 INFO: [APUAPC] D0_APC_0: 0x400510
9904 11:18:01.703956 INFO: [APUAPC] D0_APC_1: 0x0
9905 11:18:01.707768 INFO: [APUAPC] D0_APC_2: 0x1540
9906 11:18:01.707856 INFO: [APUAPC] D0_APC_3: 0x0
9907 11:18:01.710645 INFO: [APUAPC] D1_APC_0: 0xffffffff
9908 11:18:01.717170 INFO: [APUAPC] D1_APC_1: 0xffffffff
9909 11:18:01.720441 INFO: [APUAPC] D1_APC_2: 0x3fffff
9910 11:18:01.720528 INFO: [APUAPC] D1_APC_3: 0x0
9911 11:18:01.723974 INFO: [APUAPC] D2_APC_0: 0xffffffff
9912 11:18:01.727289 INFO: [APUAPC] D2_APC_1: 0xffffffff
9913 11:18:01.730422 INFO: [APUAPC] D2_APC_2: 0x3fffff
9914 11:18:01.733812 INFO: [APUAPC] D2_APC_3: 0x0
9915 11:18:01.737154 INFO: [APUAPC] D3_APC_0: 0xffffffff
9916 11:18:01.740603 INFO: [APUAPC] D3_APC_1: 0xffffffff
9917 11:18:01.743576 INFO: [APUAPC] D3_APC_2: 0x3fffff
9918 11:18:01.747140 INFO: [APUAPC] D3_APC_3: 0x0
9919 11:18:01.750364 INFO: [APUAPC] D4_APC_0: 0xffffffff
9920 11:18:01.753489 INFO: [APUAPC] D4_APC_1: 0xffffffff
9921 11:18:01.756853 INFO: [APUAPC] D4_APC_2: 0x3fffff
9922 11:18:01.760318 INFO: [APUAPC] D4_APC_3: 0x0
9923 11:18:01.763466 INFO: [APUAPC] D5_APC_0: 0xffffffff
9924 11:18:01.766651 INFO: [APUAPC] D5_APC_1: 0xffffffff
9925 11:18:01.770175 INFO: [APUAPC] D5_APC_2: 0x3fffff
9926 11:18:01.773361 INFO: [APUAPC] D5_APC_3: 0x0
9927 11:18:01.776526 INFO: [APUAPC] D6_APC_0: 0xffffffff
9928 11:18:01.780198 INFO: [APUAPC] D6_APC_1: 0xffffffff
9929 11:18:01.783028 INFO: [APUAPC] D6_APC_2: 0x3fffff
9930 11:18:01.786638 INFO: [APUAPC] D6_APC_3: 0x0
9931 11:18:01.789912 INFO: [APUAPC] D7_APC_0: 0xffffffff
9932 11:18:01.793168 INFO: [APUAPC] D7_APC_1: 0xffffffff
9933 11:18:01.796534 INFO: [APUAPC] D7_APC_2: 0x3fffff
9934 11:18:01.799700 INFO: [APUAPC] D7_APC_3: 0x0
9935 11:18:01.803179 INFO: [APUAPC] D8_APC_0: 0xffffffff
9936 11:18:01.806610 INFO: [APUAPC] D8_APC_1: 0xffffffff
9937 11:18:01.809524 INFO: [APUAPC] D8_APC_2: 0x3fffff
9938 11:18:01.813043 INFO: [APUAPC] D8_APC_3: 0x0
9939 11:18:01.816032 INFO: [APUAPC] D9_APC_0: 0xffffffff
9940 11:18:01.819318 INFO: [APUAPC] D9_APC_1: 0xffffffff
9941 11:18:01.822791 INFO: [APUAPC] D9_APC_2: 0x3fffff
9942 11:18:01.826009 INFO: [APUAPC] D9_APC_3: 0x0
9943 11:18:01.829205 INFO: [APUAPC] D10_APC_0: 0xffffffff
9944 11:18:01.832605 INFO: [APUAPC] D10_APC_1: 0xffffffff
9945 11:18:01.835936 INFO: [APUAPC] D10_APC_2: 0x3fffff
9946 11:18:01.839025 INFO: [APUAPC] D10_APC_3: 0x0
9947 11:18:01.842592 INFO: [APUAPC] D11_APC_0: 0xffffffff
9948 11:18:01.845924 INFO: [APUAPC] D11_APC_1: 0xffffffff
9949 11:18:01.848911 INFO: [APUAPC] D11_APC_2: 0x3fffff
9950 11:18:01.852209 INFO: [APUAPC] D11_APC_3: 0x0
9951 11:18:01.855629 INFO: [APUAPC] D12_APC_0: 0xffffffff
9952 11:18:01.859105 INFO: [APUAPC] D12_APC_1: 0xffffffff
9953 11:18:01.862389 INFO: [APUAPC] D12_APC_2: 0x3fffff
9954 11:18:01.865892 INFO: [APUAPC] D12_APC_3: 0x0
9955 11:18:01.869039 INFO: [APUAPC] D13_APC_0: 0xffffffff
9956 11:18:01.872540 INFO: [APUAPC] D13_APC_1: 0xffffffff
9957 11:18:01.875620 INFO: [APUAPC] D13_APC_2: 0x3fffff
9958 11:18:01.878869 INFO: [APUAPC] D13_APC_3: 0x0
9959 11:18:01.882132 INFO: [APUAPC] D14_APC_0: 0xffffffff
9960 11:18:01.885631 INFO: [APUAPC] D14_APC_1: 0xffffffff
9961 11:18:01.889040 INFO: [APUAPC] D14_APC_2: 0x3fffff
9962 11:18:01.892082 INFO: [APUAPC] D14_APC_3: 0x0
9963 11:18:01.895409 INFO: [APUAPC] D15_APC_0: 0xffffffff
9964 11:18:01.898826 INFO: [APUAPC] D15_APC_1: 0xffffffff
9965 11:18:01.902119 INFO: [APUAPC] D15_APC_2: 0x3fffff
9966 11:18:01.905275 INFO: [APUAPC] D15_APC_3: 0x0
9967 11:18:01.908655 INFO: [APUAPC] APC_CON: 0x4
9968 11:18:01.912056 INFO: [NOCDAPC] D0_APC_0: 0x0
9969 11:18:01.915243 INFO: [NOCDAPC] D0_APC_1: 0x0
9970 11:18:01.918420 INFO: [NOCDAPC] D1_APC_0: 0x0
9971 11:18:01.921770 INFO: [NOCDAPC] D1_APC_1: 0xfff
9972 11:18:01.925085 INFO: [NOCDAPC] D2_APC_0: 0x0
9973 11:18:01.925242 INFO: [NOCDAPC] D2_APC_1: 0xfff
9974 11:18:01.928624 INFO: [NOCDAPC] D3_APC_0: 0x0
9975 11:18:01.931669 INFO: [NOCDAPC] D3_APC_1: 0xfff
9976 11:18:01.935123 INFO: [NOCDAPC] D4_APC_0: 0x0
9977 11:18:01.938540 INFO: [NOCDAPC] D4_APC_1: 0xfff
9978 11:18:01.941602 INFO: [NOCDAPC] D5_APC_0: 0x0
9979 11:18:01.945038 INFO: [NOCDAPC] D5_APC_1: 0xfff
9980 11:18:01.948023 INFO: [NOCDAPC] D6_APC_0: 0x0
9981 11:18:01.951783 INFO: [NOCDAPC] D6_APC_1: 0xfff
9982 11:18:01.954829 INFO: [NOCDAPC] D7_APC_0: 0x0
9983 11:18:01.958259 INFO: [NOCDAPC] D7_APC_1: 0xfff
9984 11:18:01.961496 INFO: [NOCDAPC] D8_APC_0: 0x0
9985 11:18:01.961669 INFO: [NOCDAPC] D8_APC_1: 0xfff
9986 11:18:01.964680 INFO: [NOCDAPC] D9_APC_0: 0x0
9987 11:18:01.967790 INFO: [NOCDAPC] D9_APC_1: 0xfff
9988 11:18:01.971276 INFO: [NOCDAPC] D10_APC_0: 0x0
9989 11:18:01.974461 INFO: [NOCDAPC] D10_APC_1: 0xfff
9990 11:18:01.977815 INFO: [NOCDAPC] D11_APC_0: 0x0
9991 11:18:01.981275 INFO: [NOCDAPC] D11_APC_1: 0xfff
9992 11:18:01.984328 INFO: [NOCDAPC] D12_APC_0: 0x0
9993 11:18:01.987685 INFO: [NOCDAPC] D12_APC_1: 0xfff
9994 11:18:01.991242 INFO: [NOCDAPC] D13_APC_0: 0x0
9995 11:18:01.994072 INFO: [NOCDAPC] D13_APC_1: 0xfff
9996 11:18:01.997317 INFO: [NOCDAPC] D14_APC_0: 0x0
9997 11:18:02.000863 INFO: [NOCDAPC] D14_APC_1: 0xfff
9998 11:18:02.004141 INFO: [NOCDAPC] D15_APC_0: 0x0
9999 11:18:02.007696 INFO: [NOCDAPC] D15_APC_1: 0xfff
10000 11:18:02.007837 INFO: [NOCDAPC] APC_CON: 0x4
10001 11:18:02.010837 INFO: [APUAPC] set_apusys_apc done
10002 11:18:02.014115 INFO: [DEVAPC] devapc_init done
10003 11:18:02.020883 INFO: GICv3 without legacy support detected.
10004 11:18:02.024053 INFO: ARM GICv3 driver initialized in EL3
10005 11:18:02.027165 INFO: Maximum SPI INTID supported: 639
10006 11:18:02.031236 INFO: BL31: Initializing runtime services
10007 11:18:02.037420 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10008 11:18:02.040495 INFO: SPM: enable CPC mode
10009 11:18:02.043616 INFO: mcdi ready for mcusys-off-idle and system suspend
10010 11:18:02.050535 INFO: BL31: Preparing for EL3 exit to normal world
10011 11:18:02.054045 INFO: Entry point address = 0x80000000
10012 11:18:02.054183 INFO: SPSR = 0x8
10013 11:18:02.061248
10014 11:18:02.061414
10015 11:18:02.061579
10016 11:18:02.064443 Starting depthcharge on Spherion...
10017 11:18:02.064607
10018 11:18:02.064718 Wipe memory regions:
10019 11:18:02.064837
10020 11:18:02.065923 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10021 11:18:02.066139 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10022 11:18:02.066279 Setting prompt string to ['asurada:']
10023 11:18:02.066412 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10024 11:18:02.067554 [0x00000040000000, 0x00000054600000)
10025 11:18:02.189871
10026 11:18:02.190200 [0x00000054660000, 0x00000080000000)
10027 11:18:02.450497
10028 11:18:02.450707 [0x000000821a7280, 0x000000ffe64000)
10029 11:18:03.195581
10030 11:18:03.196057 [0x00000100000000, 0x00000240000000)
10031 11:18:05.086288
10032 11:18:05.088642 Initializing XHCI USB controller at 0x11200000.
10033 11:18:06.127400
10034 11:18:06.130527 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10035 11:18:06.130642
10036 11:18:06.130737
10037 11:18:06.130828
10038 11:18:06.131149 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10040 11:18:06.231590 asurada: tftpboot 192.168.201.1 10591274/tftp-deploy-uqlzbi0t/kernel/image.itb 10591274/tftp-deploy-uqlzbi0t/kernel/cmdline
10041 11:18:06.231744 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10042 11:18:06.231864 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10043 11:18:06.236561 tftpboot 192.168.201.1 10591274/tftp-deploy-uqlzbi0t/kernel/image.itp-deploy-uqlzbi0t/kernel/cmdline
10044 11:18:06.236679
10045 11:18:06.236799 Waiting for link
10046 11:18:06.396382
10047 11:18:06.396545 R8152: Initializing
10048 11:18:06.396649
10049 11:18:06.399588 Version 9 (ocp_data = 6010)
10050 11:18:06.399697
10051 11:18:06.402947 R8152: Done initializing
10052 11:18:06.403056
10053 11:18:06.403152 Adding net device
10054 11:18:08.348721
10055 11:18:08.348936 done.
10056 11:18:08.349002
10057 11:18:08.349062 MAC: 00:e0:4c:72:2d:d6
10058 11:18:08.349121
10059 11:18:08.352464 Sending DHCP discover... done.
10060 11:18:08.352547
10061 11:18:08.355640 Waiting for reply... done.
10062 11:18:08.355722
10063 11:18:08.358573 Sending DHCP request... done.
10064 11:18:08.358655
10065 11:18:08.365320 Waiting for reply... done.
10066 11:18:08.365403
10067 11:18:08.365468 My ip is 192.168.201.21
10068 11:18:08.365528
10069 11:18:08.368800 The DHCP server ip is 192.168.201.1
10070 11:18:08.368895
10071 11:18:08.375575 TFTP server IP predefined by user: 192.168.201.1
10072 11:18:08.375657
10073 11:18:08.382078 Bootfile predefined by user: 10591274/tftp-deploy-uqlzbi0t/kernel/image.itb
10074 11:18:08.382160
10075 11:18:08.385235 Sending tftp read request... done.
10076 11:18:08.385317
10077 11:18:08.385381 Waiting for the transfer...
10078 11:18:08.388699
10079 11:18:08.657833 00000000 ################################################################
10080 11:18:08.657978
10081 11:18:08.935554 00080000 ################################################################
10082 11:18:08.935699
10083 11:18:09.216748 00100000 ################################################################
10084 11:18:09.216911
10085 11:18:09.480657 00180000 ################################################################
10086 11:18:09.480837
10087 11:18:09.764044 00200000 ################################################################
10088 11:18:09.764200
10089 11:18:10.042801 00280000 ################################################################
10090 11:18:10.042966
10091 11:18:10.296396 00300000 ################################################################
10092 11:18:10.296541
10093 11:18:10.546522 00380000 ################################################################
10094 11:18:10.546670
10095 11:18:10.820401 00400000 ################################################################
10096 11:18:10.820545
10097 11:18:11.087453 00480000 ################################################################
10098 11:18:11.087624
10099 11:18:11.366824 00500000 ################################################################
10100 11:18:11.366964
10101 11:18:11.654350 00580000 ################################################################
10102 11:18:11.654494
10103 11:18:11.904522 00600000 ################################################################
10104 11:18:11.904663
10105 11:18:12.178146 00680000 ################################################################
10106 11:18:12.178296
10107 11:18:12.460479 00700000 ################################################################
10108 11:18:12.460617
10109 11:18:12.736589 00780000 ################################################################
10110 11:18:12.736736
10111 11:18:13.033802 00800000 ################################################################
10112 11:18:13.033951
10113 11:18:13.326452 00880000 ################################################################
10114 11:18:13.326608
10115 11:18:13.622075 00900000 ################################################################
10116 11:18:13.622225
10117 11:18:13.918424 00980000 ################################################################
10118 11:18:13.918576
10119 11:18:14.218731 00a00000 ################################################################
10120 11:18:14.218875
10121 11:18:14.511780 00a80000 ################################################################
10122 11:18:14.511930
10123 11:18:14.800800 00b00000 ################################################################
10124 11:18:14.800944
10125 11:18:15.094629 00b80000 ################################################################
10126 11:18:15.094776
10127 11:18:15.388794 00c00000 ################################################################
10128 11:18:15.388947
10129 11:18:15.687157 00c80000 ################################################################
10130 11:18:15.687314
10131 11:18:15.937789 00d00000 ################################################################
10132 11:18:15.937946
10133 11:18:16.200184 00d80000 ################################################################
10134 11:18:16.200335
10135 11:18:16.456150 00e00000 ################################################################
10136 11:18:16.456305
10137 11:18:16.747521 00e80000 ################################################################
10138 11:18:16.747679
10139 11:18:17.042635 00f00000 ################################################################
10140 11:18:17.042819
10141 11:18:17.317063 00f80000 ################################################################
10142 11:18:17.317221
10143 11:18:17.596445 01000000 ################################################################
10144 11:18:17.596606
10145 11:18:17.855951 01080000 ################################################################
10146 11:18:17.856109
10147 11:18:18.134046 01100000 ################################################################
10148 11:18:18.134202
10149 11:18:18.410947 01180000 ################################################################
10150 11:18:18.411118
10151 11:18:18.655388 01200000 ################################################################
10152 11:18:18.655561
10153 11:18:18.890232 01280000 ################################################################
10154 11:18:18.890395
10155 11:18:19.124748 01300000 ################################################################
10156 11:18:19.124925
10157 11:18:19.383115 01380000 ################################################################
10158 11:18:19.383273
10159 11:18:19.676193 01400000 ################################################################
10160 11:18:19.676351
10161 11:18:19.974966 01480000 ################################################################
10162 11:18:19.975142
10163 11:18:20.274219 01500000 ################################################################
10164 11:18:20.274407
10165 11:18:20.549749 01580000 ################################################################
10166 11:18:20.549899
10167 11:18:20.826099 01600000 ################################################################
10168 11:18:20.826247
10169 11:18:21.112460 01680000 ################################################################
10170 11:18:21.112598
10171 11:18:21.388857 01700000 ################################################################
10172 11:18:21.388988
10173 11:18:21.677086 01780000 ################################################################
10174 11:18:21.677225
10175 11:18:21.955761 01800000 ################################################################
10176 11:18:21.955898
10177 11:18:22.246116 01880000 ################################################################
10178 11:18:22.246255
10179 11:18:22.501786 01900000 ################################################################
10180 11:18:22.501970
10181 11:18:22.762872 01980000 ################################################################
10182 11:18:22.763035
10183 11:18:23.056556 01a00000 ################################################################
10184 11:18:23.056691
10185 11:18:23.352939 01a80000 ################################################################
10186 11:18:23.353075
10187 11:18:23.637678 01b00000 ################################################################
10188 11:18:23.637816
10189 11:18:23.932569 01b80000 ################################################################
10190 11:18:23.932707
10191 11:18:24.211247 01c00000 ################################################################
10192 11:18:24.211383
10193 11:18:24.492313 01c80000 ################################################################
10194 11:18:24.492442
10195 11:18:24.774815 01d00000 ################################################################
10196 11:18:24.774946
10197 11:18:25.038153 01d80000 ################################################################
10198 11:18:25.038284
10199 11:18:25.294764 01e00000 ################################################################
10200 11:18:25.294902
10201 11:18:25.575969 01e80000 ################################################################
10202 11:18:25.576106
10203 11:18:25.851203 01f00000 ################################################################
10204 11:18:25.851335
10205 11:18:26.131487 01f80000 ################################################################
10206 11:18:26.131614
10207 11:18:26.410230 02000000 ################################################################
10208 11:18:26.410363
10209 11:18:26.704986 02080000 ################################################################
10210 11:18:26.705112
10211 11:18:26.991234 02100000 ################################################################
10212 11:18:26.991371
10213 11:18:27.280242 02180000 ################################################################
10214 11:18:27.280381
10215 11:18:27.550420 02200000 ################################################################
10216 11:18:27.550581
10217 11:18:27.820829 02280000 ################################################################
10218 11:18:27.820967
10219 11:18:28.066968 02300000 ################################################################
10220 11:18:28.067100
10221 11:18:28.325134 02380000 ################################################################
10222 11:18:28.325288
10223 11:18:28.581523 02400000 ################################################################
10224 11:18:28.581658
10225 11:18:28.851073 02480000 ################################################################
10226 11:18:28.851219
10227 11:18:29.126279 02500000 ################################################################
10228 11:18:29.126413
10229 11:18:29.392008 02580000 ################################################################
10230 11:18:29.392164
10231 11:18:29.643647 02600000 ################################################################
10232 11:18:29.643810
10233 11:18:29.886747 02680000 ################################################################
10234 11:18:29.886906
10235 11:18:30.133743 02700000 ################################################################
10236 11:18:30.133886
10237 11:18:30.377489 02780000 ################################################################
10238 11:18:30.377638
10239 11:18:30.611688 02800000 ################################################################
10240 11:18:30.611871
10241 11:18:30.856818 02880000 ################################################################
10242 11:18:30.856960
10243 11:18:31.107206 02900000 ################################################################
10244 11:18:31.107342
10245 11:18:31.357150 02980000 ################################################################
10246 11:18:31.357279
10247 11:18:31.606452 02a00000 ################################################################
10248 11:18:31.606599
10249 11:18:31.850979 02a80000 ################################################################
10250 11:18:31.851113
10251 11:18:32.104615 02b00000 ################################################################
10252 11:18:32.104773
10253 11:18:32.350717 02b80000 ################################################################
10254 11:18:32.350867
10255 11:18:32.598021 02c00000 ################################################################
10256 11:18:32.598151
10257 11:18:32.862021 02c80000 ################################################################
10258 11:18:32.862158
10259 11:18:33.100696 02d00000 ################################################################
10260 11:18:33.100883
10261 11:18:33.346592 02d80000 ################################################################
10262 11:18:33.346730
10263 11:18:33.592913 02e00000 ################################################################
10264 11:18:33.593051
10265 11:18:33.841088 02e80000 ################################################################
10266 11:18:33.841227
10267 11:18:34.086500 02f00000 ################################################################
10268 11:18:34.086630
10269 11:18:34.332911 02f80000 ################################################################
10270 11:18:34.333044
10271 11:18:34.579657 03000000 ################################################################
10272 11:18:34.579790
10273 11:18:34.828580 03080000 ################################################################
10274 11:18:34.828719
10275 11:18:35.083244 03100000 ################################################################
10276 11:18:35.083407
10277 11:18:35.328132 03180000 ################################################################
10278 11:18:35.328285
10279 11:18:35.576700 03200000 ################################################################
10280 11:18:35.576870
10281 11:18:35.824053 03280000 ################################################################
10282 11:18:35.824219
10283 11:18:36.075753 03300000 ################################################################
10284 11:18:36.075899
10285 11:18:36.318043 03380000 ################################################################
10286 11:18:36.318183
10287 11:18:36.571438 03400000 ################################################################
10288 11:18:36.571574
10289 11:18:36.827966 03480000 ################################################################
10290 11:18:36.828131
10291 11:18:37.073900 03500000 ################################################################
10292 11:18:37.074057
10293 11:18:37.327067 03580000 ################################################################
10294 11:18:37.327208
10295 11:18:37.582949 03600000 ################################################################
10296 11:18:37.583084
10297 11:18:37.826322 03680000 ################################################################
10298 11:18:37.826455
10299 11:18:38.075475 03700000 ################################################################
10300 11:18:38.075630
10301 11:18:38.325954 03780000 ################################################################
10302 11:18:38.326114
10303 11:18:38.581427 03800000 ################################################################
10304 11:18:38.581583
10305 11:18:38.830509 03880000 ################################################################
10306 11:18:38.830639
10307 11:18:39.084729 03900000 ################################################################
10308 11:18:39.084901
10309 11:18:39.342272 03980000 ################################################################
10310 11:18:39.342437
10311 11:18:39.589981 03a00000 ################################################################
10312 11:18:39.590119
10313 11:18:39.839789 03a80000 ################################################################
10314 11:18:39.839956
10315 11:18:40.097911 03b00000 ################################################################
10316 11:18:40.098052
10317 11:18:40.350972 03b80000 ################################################################
10318 11:18:40.351112
10319 11:18:40.600479 03c00000 ################################################################
10320 11:18:40.600616
10321 11:18:40.861624 03c80000 ################################################################
10322 11:18:40.861766
10323 11:18:41.118699 03d00000 ################################################################
10324 11:18:41.118842
10325 11:18:41.368614 03d80000 ################################################################
10326 11:18:41.368748
10327 11:18:41.619957 03e00000 ################################################################
10328 11:18:41.620114
10329 11:18:41.874899 03e80000 ################################################################
10330 11:18:41.875050
10331 11:18:42.104653 03f00000 ########################################################## done.
10332 11:18:42.104838
10333 11:18:42.107821 The bootfile was 66528830 bytes long.
10334 11:18:42.107929
10335 11:18:42.111471 Sending tftp read request... done.
10336 11:18:42.111553
10337 11:18:42.114799 Waiting for the transfer...
10338 11:18:42.114881
10339 11:18:42.114946 00000000 # done.
10340 11:18:42.115007
10341 11:18:42.124784 Command line loaded dynamically from TFTP file: 10591274/tftp-deploy-uqlzbi0t/kernel/cmdline
10342 11:18:42.124880
10343 11:18:42.134564 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10344 11:18:42.134648
10345 11:18:42.134713 Loading FIT.
10346 11:18:42.134773
10347 11:18:42.137745 Image ramdisk-1 has 56393850 bytes.
10348 11:18:42.137827
10349 11:18:42.141008 Image fdt-1 has 46924 bytes.
10350 11:18:42.141089
10351 11:18:42.144699 Image kernel-1 has 10086024 bytes.
10352 11:18:42.144843
10353 11:18:42.154554 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10354 11:18:42.154637
10355 11:18:42.170864 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10356 11:18:42.170950
10357 11:18:42.177542 Choosing best match conf-1 for compat google,spherion-rev2.
10358 11:18:42.177646
10359 11:18:42.184533 Connected to device vid:did:rid of 1ae0:0028:00
10360 11:18:42.191927
10361 11:18:42.195092 tpm_get_response: command 0x17b, return code 0x0
10362 11:18:42.195174
10363 11:18:42.198456 ec_init: CrosEC protocol v3 supported (256, 248)
10364 11:18:42.202844
10365 11:18:42.206101 tpm_cleanup: add release locality here.
10366 11:18:42.206177
10367 11:18:42.206244 Shutting down all USB controllers.
10368 11:18:42.209302
10369 11:18:42.209440 Removing current net device
10370 11:18:42.209522
10371 11:18:42.216076 Exiting depthcharge with code 4 at timestamp: 69438402
10372 11:18:42.216160
10373 11:18:42.219409 LZMA decompressing kernel-1 to 0x821a6718
10374 11:18:42.219495
10375 11:18:42.222669 LZMA decompressing kernel-1 to 0x40000000
10376 11:18:43.489223
10377 11:18:43.489366 jumping to kernel
10378 11:18:43.489815 end: 2.2.4 bootloader-commands (duration 00:00:41) [common]
10379 11:18:43.489931 start: 2.2.5 auto-login-action (timeout 00:03:44) [common]
10380 11:18:43.490010 Setting prompt string to ['Linux version [0-9]']
10381 11:18:43.490091 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10382 11:18:43.490161 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10383 11:18:43.570758
10384 11:18:43.574255 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10385 11:18:43.577797 start: 2.2.5.1 login-action (timeout 00:03:44) [common]
10386 11:18:43.577932 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10387 11:18:43.578056 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10388 11:18:43.578202 Using line separator: #'\n'#
10389 11:18:43.578302 No login prompt set.
10390 11:18:43.578410 Parsing kernel messages
10391 11:18:43.578499 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10392 11:18:43.578701 [login-action] Waiting for messages, (timeout 00:03:44)
10393 11:18:43.597131 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1609115-arm64-gcc-10-defconfig-arm64-chromebook-dplkv) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 10:57:14 UTC 2023
10394 11:18:43.600266 [ 0.000000] random: crng init done
10395 11:18:43.607044 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10396 11:18:43.607128 [ 0.000000] efi: UEFI not found.
10397 11:18:43.617103 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10398 11:18:43.623938 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10399 11:18:43.633844 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10400 11:18:43.643476 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10401 11:18:43.650069 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10402 11:18:43.656503 [ 0.000000] printk: bootconsole [mtk8250] enabled
10403 11:18:43.662812 [ 0.000000] NUMA: No NUMA configuration found
10404 11:18:43.669578 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10405 11:18:43.672660 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10406 11:18:43.676327 [ 0.000000] Zone ranges:
10407 11:18:43.682921 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10408 11:18:43.686055 [ 0.000000] DMA32 empty
10409 11:18:43.692658 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10410 11:18:43.696203 [ 0.000000] Movable zone start for each node
10411 11:18:43.699506 [ 0.000000] Early memory node ranges
10412 11:18:43.705966 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10413 11:18:43.712595 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10414 11:18:43.719271 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10415 11:18:43.725978 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10416 11:18:43.728907 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10417 11:18:43.738776 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10418 11:18:43.794926 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10419 11:18:43.801496 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10420 11:18:43.808170 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10421 11:18:43.811447 [ 0.000000] psci: probing for conduit method from DT.
10422 11:18:43.817834 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10423 11:18:43.821000 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10424 11:18:43.827568 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10425 11:18:43.831197 [ 0.000000] psci: SMC Calling Convention v1.2
10426 11:18:43.837533 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10427 11:18:43.840666 [ 0.000000] Detected VIPT I-cache on CPU0
10428 11:18:43.847340 [ 0.000000] CPU features: detected: GIC system register CPU interface
10429 11:18:43.853995 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10430 11:18:43.860657 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10431 11:18:43.867333 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10432 11:18:43.877107 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10433 11:18:43.883522 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10434 11:18:43.886697 [ 0.000000] alternatives: applying boot alternatives
10435 11:18:43.893352 [ 0.000000] Fallback order for Node 0: 0
10436 11:18:43.900413 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10437 11:18:43.903367 [ 0.000000] Policy zone: Normal
10438 11:18:43.916833 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10439 11:18:43.926470 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10440 11:18:43.936514 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10441 11:18:43.946275 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10442 11:18:43.953356 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10443 11:18:43.956418 <6>[ 0.000000] software IO TLB: area num 8.
10444 11:18:44.013294 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10445 11:18:44.162071 <6>[ 0.000000] Memory: 7917868K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 434900K reserved, 32768K cma-reserved)
10446 11:18:44.168734 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10447 11:18:44.175596 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10448 11:18:44.178930 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10449 11:18:44.185732 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10450 11:18:44.191970 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10451 11:18:44.195111 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10452 11:18:44.205437 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10453 11:18:44.211958 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10454 11:18:44.218404 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10455 11:18:44.225079 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10456 11:18:44.228385 <6>[ 0.000000] GICv3: 608 SPIs implemented
10457 11:18:44.231496 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10458 11:18:44.238186 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10459 11:18:44.241436 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10460 11:18:44.248284 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10461 11:18:44.261343 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10462 11:18:44.274249 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10463 11:18:44.281049 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10464 11:18:44.288681 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10465 11:18:44.302334 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10466 11:18:44.308999 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10467 11:18:44.315466 <6>[ 0.009172] Console: colour dummy device 80x25
10468 11:18:44.325101 <6>[ 0.013898] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10469 11:18:44.331707 <6>[ 0.024405] pid_max: default: 32768 minimum: 301
10470 11:18:44.335162 <6>[ 0.029278] LSM: Security Framework initializing
10471 11:18:44.341849 <6>[ 0.034247] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10472 11:18:44.351578 <6>[ 0.042061] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10473 11:18:44.361644 <6>[ 0.051549] cblist_init_generic: Setting adjustable number of callback queues.
10474 11:18:44.364756 <6>[ 0.059002] cblist_init_generic: Setting shift to 3 and lim to 1.
10475 11:18:44.371663 <6>[ 0.065341] cblist_init_generic: Setting shift to 3 and lim to 1.
10476 11:18:44.378032 <6>[ 0.071749] rcu: Hierarchical SRCU implementation.
10477 11:18:44.384483 <6>[ 0.076762] rcu: Max phase no-delay instances is 1000.
10478 11:18:44.390934 <6>[ 0.083775] EFI services will not be available.
10479 11:18:44.394134 <6>[ 0.088775] smp: Bringing up secondary CPUs ...
10480 11:18:44.402124 <6>[ 0.093829] Detected VIPT I-cache on CPU1
10481 11:18:44.408916 <6>[ 0.093900] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10482 11:18:44.415607 <6>[ 0.093931] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10483 11:18:44.418631 <6>[ 0.094259] Detected VIPT I-cache on CPU2
10484 11:18:44.425443 <6>[ 0.094311] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10485 11:18:44.435346 <6>[ 0.094327] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10486 11:18:44.438650 <6>[ 0.094584] Detected VIPT I-cache on CPU3
10487 11:18:44.445345 <6>[ 0.094630] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10488 11:18:44.451788 <6>[ 0.094644] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10489 11:18:44.455554 <6>[ 0.094949] CPU features: detected: Spectre-v4
10490 11:18:44.461640 <6>[ 0.094955] CPU features: detected: Spectre-BHB
10491 11:18:44.464900 <6>[ 0.094961] Detected PIPT I-cache on CPU4
10492 11:18:44.471929 <6>[ 0.095018] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10493 11:18:44.478213 <6>[ 0.095035] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10494 11:18:44.485028 <6>[ 0.095331] Detected PIPT I-cache on CPU5
10495 11:18:44.491607 <6>[ 0.095394] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10496 11:18:44.497893 <6>[ 0.095410] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10497 11:18:44.501547 <6>[ 0.095692] Detected PIPT I-cache on CPU6
10498 11:18:44.507794 <6>[ 0.095756] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10499 11:18:44.514563 <6>[ 0.095772] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10500 11:18:44.521230 <6>[ 0.096070] Detected PIPT I-cache on CPU7
10501 11:18:44.527760 <6>[ 0.096134] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10502 11:18:44.534633 <6>[ 0.096150] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10503 11:18:44.537671 <6>[ 0.096197] smp: Brought up 1 node, 8 CPUs
10504 11:18:44.543997 <6>[ 0.237387] SMP: Total of 8 processors activated.
10505 11:18:44.547825 <6>[ 0.242308] CPU features: detected: 32-bit EL0 Support
10506 11:18:44.557176 <6>[ 0.247671] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10507 11:18:44.563959 <6>[ 0.256471] CPU features: detected: Common not Private translations
10508 11:18:44.570604 <6>[ 0.262947] CPU features: detected: CRC32 instructions
10509 11:18:44.573726 <6>[ 0.268298] CPU features: detected: RCpc load-acquire (LDAPR)
10510 11:18:44.580147 <6>[ 0.274258] CPU features: detected: LSE atomic instructions
10511 11:18:44.587011 <6>[ 0.280039] CPU features: detected: Privileged Access Never
10512 11:18:44.593529 <6>[ 0.285819] CPU features: detected: RAS Extension Support
10513 11:18:44.600187 <6>[ 0.291427] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10514 11:18:44.603376 <6>[ 0.298692] CPU: All CPU(s) started at EL2
10515 11:18:44.609814 <6>[ 0.303008] alternatives: applying system-wide alternatives
10516 11:18:44.619727 <6>[ 0.313706] devtmpfs: initialized
10517 11:18:44.632097 <6>[ 0.322742] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10518 11:18:44.641981 <6>[ 0.332704] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10519 11:18:44.648486 <6>[ 0.340927] pinctrl core: initialized pinctrl subsystem
10520 11:18:44.651818 <6>[ 0.347589] DMI not present or invalid.
10521 11:18:44.658505 <6>[ 0.351993] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10522 11:18:44.668363 <6>[ 0.358875] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10523 11:18:44.675133 <6>[ 0.366451] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10524 11:18:44.684787 <6>[ 0.374676] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10525 11:18:44.687937 <6>[ 0.382915] audit: initializing netlink subsys (disabled)
10526 11:18:44.698200 <5>[ 0.388609] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10527 11:18:44.704658 <6>[ 0.389316] thermal_sys: Registered thermal governor 'step_wise'
10528 11:18:44.711331 <6>[ 0.396573] thermal_sys: Registered thermal governor 'power_allocator'
10529 11:18:44.714404 <6>[ 0.402826] cpuidle: using governor menu
10530 11:18:44.721133 <6>[ 0.413787] NET: Registered PF_QIPCRTR protocol family
10531 11:18:44.727799 <6>[ 0.419266] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10532 11:18:44.734141 <6>[ 0.426371] ASID allocator initialised with 32768 entries
10533 11:18:44.737579 <6>[ 0.432947] Serial: AMBA PL011 UART driver
10534 11:18:44.747803 <4>[ 0.441628] Trying to register duplicate clock ID: 134
10535 11:18:44.801616 <6>[ 0.498966] KASLR enabled
10536 11:18:44.815828 <6>[ 0.506661] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10537 11:18:44.822529 <6>[ 0.513677] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10538 11:18:44.829196 <6>[ 0.520166] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10539 11:18:44.835900 <6>[ 0.527167] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10540 11:18:44.842553 <6>[ 0.533655] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10541 11:18:44.848927 <6>[ 0.540661] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10542 11:18:44.855771 <6>[ 0.547146] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10543 11:18:44.862158 <6>[ 0.554149] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10544 11:18:44.865635 <6>[ 0.561614] ACPI: Interpreter disabled.
10545 11:18:44.874396 <6>[ 0.568049] iommu: Default domain type: Translated
10546 11:18:44.880645 <6>[ 0.573160] iommu: DMA domain TLB invalidation policy: strict mode
10547 11:18:44.883917 <5>[ 0.579815] SCSI subsystem initialized
10548 11:18:44.890678 <6>[ 0.584051] usbcore: registered new interface driver usbfs
10549 11:18:44.896931 <6>[ 0.589778] usbcore: registered new interface driver hub
10550 11:18:44.900704 <6>[ 0.595332] usbcore: registered new device driver usb
10551 11:18:44.907496 <6>[ 0.601427] pps_core: LinuxPPS API ver. 1 registered
10552 11:18:44.917428 <6>[ 0.606619] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10553 11:18:44.920585 <6>[ 0.615958] PTP clock support registered
10554 11:18:44.923817 <6>[ 0.620197] EDAC MC: Ver: 3.0.0
10555 11:18:44.931550 <6>[ 0.625379] FPGA manager framework
10556 11:18:44.938147 <6>[ 0.629056] Advanced Linux Sound Architecture Driver Initialized.
10557 11:18:44.941161 <6>[ 0.635819] vgaarb: loaded
10558 11:18:44.947923 <6>[ 0.638996] clocksource: Switched to clocksource arch_sys_counter
10559 11:18:44.951186 <5>[ 0.645443] VFS: Disk quotas dquot_6.6.0
10560 11:18:44.957624 <6>[ 0.649625] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10561 11:18:44.961187 <6>[ 0.656818] pnp: PnP ACPI: disabled
10562 11:18:44.969486 <6>[ 0.663504] NET: Registered PF_INET protocol family
10563 11:18:44.979433 <6>[ 0.669092] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10564 11:18:44.990896 <6>[ 0.681397] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10565 11:18:45.000591 <6>[ 0.690211] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10566 11:18:45.007215 <6>[ 0.698183] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10567 11:18:45.017077 <6>[ 0.706880] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10568 11:18:45.023803 <6>[ 0.716628] TCP: Hash tables configured (established 65536 bind 65536)
10569 11:18:45.029977 <6>[ 0.723487] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10570 11:18:45.040030 <6>[ 0.730688] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10571 11:18:45.046673 <6>[ 0.738388] NET: Registered PF_UNIX/PF_LOCAL protocol family
10572 11:18:45.053275 <6>[ 0.744553] RPC: Registered named UNIX socket transport module.
10573 11:18:45.056417 <6>[ 0.750708] RPC: Registered udp transport module.
10574 11:18:45.063068 <6>[ 0.755637] RPC: Registered tcp transport module.
10575 11:18:45.069596 <6>[ 0.760567] RPC: Registered tcp NFSv4.1 backchannel transport module.
10576 11:18:45.072651 <6>[ 0.767234] PCI: CLS 0 bytes, default 64
10577 11:18:45.076227 <6>[ 0.771625] Unpacking initramfs...
10578 11:18:45.085894 <6>[ 0.775429] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10579 11:18:45.093114 <6>[ 0.784081] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10580 11:18:45.099159 <6>[ 0.792918] kvm [1]: IPA Size Limit: 40 bits
10581 11:18:45.102561 <6>[ 0.797447] kvm [1]: GICv3: no GICV resource entry
10582 11:18:45.109144 <6>[ 0.802466] kvm [1]: disabling GICv2 emulation
10583 11:18:45.112412 <6>[ 0.807153] kvm [1]: GIC system register CPU interface enabled
10584 11:18:45.119256 <6>[ 0.813319] kvm [1]: vgic interrupt IRQ18
10585 11:18:45.122589 <6>[ 0.817675] kvm [1]: VHE mode initialized successfully
10586 11:18:45.130182 <5>[ 0.824141] Initialise system trusted keyrings
10587 11:18:45.136605 <6>[ 0.828927] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10588 11:18:45.144730 <6>[ 0.839004] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10589 11:18:45.151574 <5>[ 0.845387] NFS: Registering the id_resolver key type
10590 11:18:45.154640 <5>[ 0.850693] Key type id_resolver registered
10591 11:18:45.161570 <5>[ 0.855108] Key type id_legacy registered
10592 11:18:45.167911 <6>[ 0.859404] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10593 11:18:45.175017 <6>[ 0.866326] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10594 11:18:45.181161 <6>[ 0.874052] 9p: Installing v9fs 9p2000 file system support
10595 11:18:45.218343 <5>[ 0.912302] Key type asymmetric registered
10596 11:18:45.221594 <5>[ 0.916638] Asymmetric key parser 'x509' registered
10597 11:18:45.231660 <6>[ 0.921787] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10598 11:18:45.234629 <6>[ 0.929403] io scheduler mq-deadline registered
10599 11:18:45.238168 <6>[ 0.934163] io scheduler kyber registered
10600 11:18:45.256887 <6>[ 0.951244] EINJ: ACPI disabled.
10601 11:18:45.289310 <4>[ 0.976706] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10602 11:18:45.299096 <4>[ 0.987360] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10603 11:18:45.313910 <6>[ 1.008076] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10604 11:18:45.322139 <6>[ 1.016039] printk: console [ttyS0] disabled
10605 11:18:45.349902 <6>[ 1.040686] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10606 11:18:45.356374 <6>[ 1.050157] printk: console [ttyS0] enabled
10607 11:18:45.359996 <6>[ 1.050157] printk: console [ttyS0] enabled
10608 11:18:45.366486 <6>[ 1.059055] printk: bootconsole [mtk8250] disabled
10609 11:18:45.369984 <6>[ 1.059055] printk: bootconsole [mtk8250] disabled
10610 11:18:45.376173 <6>[ 1.070269] SuperH (H)SCI(F) driver initialized
10611 11:18:45.379581 <6>[ 1.075527] msm_serial: driver initialized
10612 11:18:45.393741 <6>[ 1.084401] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10613 11:18:45.403618 <6>[ 1.092945] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10614 11:18:45.410222 <6>[ 1.101486] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10615 11:18:45.420178 <6>[ 1.110114] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10616 11:18:45.429833 <6>[ 1.118820] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10617 11:18:45.436637 <6>[ 1.127542] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10618 11:18:45.446419 <6>[ 1.136083] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10619 11:18:45.453206 <6>[ 1.144895] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10620 11:18:45.463061 <6>[ 1.153439] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10621 11:18:45.474761 <6>[ 1.168911] loop: module loaded
10622 11:18:45.481466 <6>[ 1.174879] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10623 11:18:45.504283 <4>[ 1.198192] mtk-pmic-keys: Failed to locate of_node [id: -1]
10624 11:18:45.510760 <6>[ 1.204977] megasas: 07.719.03.00-rc1
10625 11:18:45.520564 <6>[ 1.214469] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10626 11:18:45.528227 <6>[ 1.222372] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10627 11:18:45.544998 <6>[ 1.239037] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10628 11:18:45.605816 <6>[ 1.292907] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10629 11:18:47.457234 <6>[ 3.150994] Freeing initrd memory: 55068K
10630 11:18:47.467542 <6>[ 3.161407] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10631 11:18:47.478306 <6>[ 3.172359] tun: Universal TUN/TAP device driver, 1.6
10632 11:18:47.481932 <6>[ 3.178416] thunder_xcv, ver 1.0
10633 11:18:47.484806 <6>[ 3.181919] thunder_bgx, ver 1.0
10634 11:18:47.488565 <6>[ 3.185414] nicpf, ver 1.0
10635 11:18:47.499217 <6>[ 3.189408] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10636 11:18:47.501822 <6>[ 3.196883] hns3: Copyright (c) 2017 Huawei Corporation.
10637 11:18:47.508696 <6>[ 3.202468] hclge is initializing
10638 11:18:47.512657 <6>[ 3.206055] e1000: Intel(R) PRO/1000 Network Driver
10639 11:18:47.518376 <6>[ 3.211185] e1000: Copyright (c) 1999-2006 Intel Corporation.
10640 11:18:47.521855 <6>[ 3.217197] e1000e: Intel(R) PRO/1000 Network Driver
10641 11:18:47.528237 <6>[ 3.222413] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10642 11:18:47.534653 <6>[ 3.228601] igb: Intel(R) Gigabit Ethernet Network Driver
10643 11:18:47.541350 <6>[ 3.234251] igb: Copyright (c) 2007-2014 Intel Corporation.
10644 11:18:47.548307 <6>[ 3.240087] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10645 11:18:47.554575 <6>[ 3.246605] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10646 11:18:47.558015 <6>[ 3.253060] sky2: driver version 1.30
10647 11:18:47.564407 <6>[ 3.258025] VFIO - User Level meta-driver version: 0.3
10648 11:18:47.572017 <6>[ 3.266173] usbcore: registered new interface driver usb-storage
10649 11:18:47.578962 <6>[ 3.272619] usbcore: registered new device driver onboard-usb-hub
10650 11:18:47.587394 <6>[ 3.281623] mt6397-rtc mt6359-rtc: registered as rtc0
10651 11:18:47.597534 <6>[ 3.287088] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-05T11:18:45 UTC (1685963925)
10652 11:18:47.600694 <6>[ 3.296645] i2c_dev: i2c /dev entries driver
10653 11:18:47.617490 <6>[ 3.308267] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10654 11:18:47.624030 <6>[ 3.318266] sdhci: Secure Digital Host Controller Interface driver
10655 11:18:47.631463 <6>[ 3.324705] sdhci: Copyright(c) Pierre Ossman
10656 11:18:47.637678 <6>[ 3.330099] Synopsys Designware Multimedia Card Interface Driver
10657 11:18:47.641028 <6>[ 3.336732] mmc0: CQHCI version 5.10
10658 11:18:47.648156 <6>[ 3.337254] sdhci-pltfm: SDHCI platform and OF driver helper
10659 11:18:47.654373 <6>[ 3.348610] ledtrig-cpu: registered to indicate activity on CPUs
10660 11:18:47.665303 <6>[ 3.355940] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10661 11:18:47.668842 <6>[ 3.363343] usbcore: registered new interface driver usbhid
10662 11:18:47.675231 <6>[ 3.369169] usbhid: USB HID core driver
10663 11:18:47.682045 <6>[ 3.373408] spi_master spi0: will run message pump with realtime priority
10664 11:18:47.731802 <6>[ 3.418967] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10665 11:18:47.750934 <6>[ 3.434489] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10666 11:18:47.754476 <6>[ 3.448065] mmc0: Command Queue Engine enabled
10667 11:18:47.761296 <6>[ 3.449775] cros-ec-spi spi0.0: Chrome EC device registered
10668 11:18:47.767961 <6>[ 3.452814] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10669 11:18:47.771213 <6>[ 3.465969] mmcblk0: mmc0:0001 DA4128 116 GiB
10670 11:18:47.782987 <6>[ 3.476107] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10671 11:18:47.792455 <6>[ 3.476306] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10672 11:18:47.798939 <6>[ 3.483200] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10673 11:18:47.801997 <6>[ 3.493417] NET: Registered PF_PACKET protocol family
10674 11:18:47.808859 <6>[ 3.497292] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10675 11:18:47.811979 <6>[ 3.501971] 9pnet: Installing 9P2000 support
10676 11:18:47.818530 <6>[ 3.507851] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10677 11:18:47.825326 <5>[ 3.511677] Key type dns_resolver registered
10678 11:18:47.828426 <6>[ 3.523290] registered taskstats version 1
10679 11:18:47.835135 <5>[ 3.527702] Loading compiled-in X.509 certificates
10680 11:18:47.871881 <4>[ 3.558409] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10681 11:18:47.880912 <4>[ 3.569093] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10682 11:18:47.891698 <3>[ 3.581856] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10683 11:18:47.903769 <6>[ 3.597343] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10684 11:18:47.910157 <6>[ 3.604113] xhci-mtk 11200000.usb: xHCI Host Controller
10685 11:18:47.917095 <6>[ 3.609623] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10686 11:18:47.927211 <6>[ 3.617481] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10687 11:18:47.933198 <6>[ 3.626935] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10688 11:18:47.940186 <6>[ 3.633143] xhci-mtk 11200000.usb: xHCI Host Controller
10689 11:18:47.947099 <6>[ 3.638645] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10690 11:18:47.953439 <6>[ 3.646306] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10691 11:18:47.960308 <6>[ 3.654192] hub 1-0:1.0: USB hub found
10692 11:18:47.963482 <6>[ 3.658229] hub 1-0:1.0: 1 port detected
10693 11:18:47.973151 <6>[ 3.662585] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10694 11:18:47.977007 <6>[ 3.671396] hub 2-0:1.0: USB hub found
10695 11:18:47.979679 <6>[ 3.675430] hub 2-0:1.0: 1 port detected
10696 11:18:47.988526 <6>[ 3.682747] mtk-msdc 11f70000.mmc: Got CD GPIO
10697 11:18:48.006142 <6>[ 3.696617] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10698 11:18:48.012435 <6>[ 3.704817] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10699 11:18:48.022581 <4>[ 3.712788] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10700 11:18:48.032221 <6>[ 3.722482] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10701 11:18:48.038730 <6>[ 3.730571] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10702 11:18:48.048827 <6>[ 3.738639] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10703 11:18:48.055466 <6>[ 3.746562] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10704 11:18:48.061914 <6>[ 3.754417] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10705 11:18:48.071934 <6>[ 3.762242] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10706 11:18:48.082132 <6>[ 3.772989] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10707 11:18:48.092399 <6>[ 3.781352] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10708 11:18:48.098745 <6>[ 3.789740] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10709 11:18:48.108883 <6>[ 3.798087] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10710 11:18:48.115404 <6>[ 3.806457] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10711 11:18:48.125318 <6>[ 3.814804] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10712 11:18:48.131623 <6>[ 3.823173] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10713 11:18:48.141730 <6>[ 3.831519] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10714 11:18:48.148188 <6>[ 3.839883] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10715 11:18:48.158439 <6>[ 3.848229] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10716 11:18:48.164839 <6>[ 3.856587] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10717 11:18:48.175102 <6>[ 3.864931] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10718 11:18:48.181428 <6>[ 3.873274] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10719 11:18:48.191141 <6>[ 3.881618] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10720 11:18:48.197367 <6>[ 3.889960] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10721 11:18:48.204356 <6>[ 3.898849] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10722 11:18:48.212214 <6>[ 3.906273] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10723 11:18:48.219160 <6>[ 3.913308] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10724 11:18:48.229450 <6>[ 3.920408] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10725 11:18:48.235701 <6>[ 3.927697] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10726 11:18:48.245806 <6>[ 3.934598] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10727 11:18:48.252369 <6>[ 3.943748] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10728 11:18:48.262800 <6>[ 3.952923] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10729 11:18:48.272610 <6>[ 3.962338] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10730 11:18:48.282706 <6>[ 3.971817] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10731 11:18:48.292903 <6>[ 3.981291] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10732 11:18:48.302511 <6>[ 3.990421] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10733 11:18:48.308837 <6>[ 3.999895] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10734 11:18:48.319041 <6>[ 4.009022] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10735 11:18:48.328982 <6>[ 4.018323] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10736 11:18:48.338692 <6>[ 4.028509] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10737 11:18:48.349369 <6>[ 4.040421] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10738 11:18:48.396614 <6>[ 4.087274] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10739 11:18:48.550693 <6>[ 4.244578] hub 1-1:1.0: USB hub found
10740 11:18:48.554089 <6>[ 4.249031] hub 1-1:1.0: 4 ports detected
10741 11:18:48.676397 <6>[ 4.367437] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10742 11:18:48.700478 <6>[ 4.394869] hub 2-1:1.0: USB hub found
10743 11:18:48.703622 <6>[ 4.399246] hub 2-1:1.0: 3 ports detected
10744 11:18:48.876310 <6>[ 4.567268] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10745 11:18:49.008702 <6>[ 4.703254] hub 1-1.4:1.0: USB hub found
10746 11:18:49.012017 <6>[ 4.707937] hub 1-1.4:1.0: 2 ports detected
10747 11:18:49.088819 <6>[ 4.779298] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10748 11:18:49.308249 <6>[ 4.999237] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10749 11:18:49.492695 <6>[ 5.183241] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10750 11:19:00.632921 <6>[ 16.331826] ALSA device list:
10751 11:19:00.639304 <6>[ 16.335082] No soundcards found.
10752 11:19:00.651569 <6>[ 16.347505] Freeing unused kernel memory: 8384K
10753 11:19:00.655181 <6>[ 16.352435] Run /init as init process
10754 11:19:00.684853 <6>[ 16.380636] NET: Registered PF_INET6 protocol family
10755 11:19:00.691584 <6>[ 16.387300] Segment Routing with IPv6
10756 11:19:00.695005 <6>[ 16.391259] In-situ OAM (IOAM) with IPv6
10757 11:19:00.729909 <30>[ 16.405701] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10758 11:19:00.732977 <30>[ 16.429559] systemd[1]: Detected architecture arm64.
10759 11:19:00.736741
10760 11:19:00.739669 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10761 11:19:00.739749
10762 11:19:00.755834 <30>[ 16.451444] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10763 11:19:00.898392 <30>[ 16.590739] systemd[1]: Queued start job for default target Graphical Interface.
10764 11:19:00.937272 <30>[ 16.632754] systemd[1]: Created slice system-getty.slice.
10765 11:19:00.943919 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10766 11:19:00.960359 <30>[ 16.655907] systemd[1]: Created slice system-modprobe.slice.
10767 11:19:00.967163 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10768 11:19:00.984871 <30>[ 16.680379] systemd[1]: Created slice system-serial\x2dgetty.slice.
10769 11:19:00.995246 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10770 11:19:01.008720 <30>[ 16.703797] systemd[1]: Created slice User and Session Slice.
10771 11:19:01.014949 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10772 11:19:01.035218 <30>[ 16.727835] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10773 11:19:01.045119 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10774 11:19:01.063016 <30>[ 16.755766] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10775 11:19:01.070089 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10776 11:19:01.091126 <30>[ 16.779391] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10777 11:19:01.096984 <30>[ 16.791438] systemd[1]: Reached target Local Encrypted Volumes.
10778 11:19:01.103573 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10779 11:19:01.120608 <30>[ 16.815626] systemd[1]: Reached target Paths.
10780 11:19:01.123900 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10781 11:19:01.140133 <30>[ 16.835324] systemd[1]: Reached target Remote File Systems.
10782 11:19:01.146620 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10783 11:19:01.164531 <30>[ 16.859534] systemd[1]: Reached target Slices.
10784 11:19:01.170919 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10785 11:19:01.184106 <30>[ 16.879337] systemd[1]: Reached target Swap.
10786 11:19:01.187174 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10787 11:19:01.207572 <30>[ 16.899622] systemd[1]: Listening on initctl Compatibility Named Pipe.
10788 11:19:01.214020 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10789 11:19:01.221045 <30>[ 16.914392] systemd[1]: Listening on Journal Audit Socket.
10790 11:19:01.227473 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10791 11:19:01.239940 <30>[ 16.935584] systemd[1]: Listening on Journal Socket (/dev/log).
10792 11:19:01.246956 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10793 11:19:01.264693 <30>[ 16.960050] systemd[1]: Listening on Journal Socket.
10794 11:19:01.271698 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10795 11:19:01.284367 <30>[ 16.979628] systemd[1]: Listening on udev Control Socket.
10796 11:19:01.290959 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10797 11:19:01.308621 <30>[ 17.003944] systemd[1]: Listening on udev Kernel Socket.
10798 11:19:01.315082 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10799 11:19:01.344691 <30>[ 17.039537] systemd[1]: Mounting Huge Pages File System...
10800 11:19:01.350888 Mounting [0;1;39mHuge Pages File System[0m...
10801 11:19:01.366301 <30>[ 17.061373] systemd[1]: Mounting POSIX Message Queue File System...
10802 11:19:01.372951 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10803 11:19:01.390406 <30>[ 17.085335] systemd[1]: Mounting Kernel Debug File System...
10804 11:19:01.396939 Mounting [0;1;39mKernel Debug File System[0m...
10805 11:19:01.415531 <30>[ 17.107591] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10806 11:19:01.447556 <30>[ 17.139769] systemd[1]: Starting Create list of static device nodes for the current kernel...
10807 11:19:01.457486 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10808 11:19:01.474524 <30>[ 17.169705] systemd[1]: Starting Load Kernel Module configfs...
10809 11:19:01.481042 Starting [0;1;39mLoad Kernel Module configfs[0m...
10810 11:19:01.498423 <30>[ 17.193627] systemd[1]: Starting Load Kernel Module drm...
10811 11:19:01.505007 Starting [0;1;39mLoad Kernel Module drm[0m...
10812 11:19:01.523318 <30>[ 17.215629] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10813 11:19:01.544064 <30>[ 17.239777] systemd[1]: Starting Journal Service...
10814 11:19:01.547926 Starting [0;1;39mJournal Service[0m...
10815 11:19:01.566709 <30>[ 17.262148] systemd[1]: Starting Load Kernel Modules...
10816 11:19:01.573094 Starting [0;1;39mLoad Kernel Modules[0m...
10817 11:19:01.594366 <30>[ 17.286418] systemd[1]: Starting Remount Root and Kernel File Systems...
10818 11:19:01.600994 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10819 11:19:01.618310 <30>[ 17.313837] systemd[1]: Starting Coldplug All udev Devices...
10820 11:19:01.625028 Starting [0;1;39mColdplug All udev Devices[0m...
10821 11:19:01.643054 <30>[ 17.338227] systemd[1]: Started Journal Service.
10822 11:19:01.649226 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10823 11:19:01.665971 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10824 11:19:01.680715 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10825 11:19:01.697395 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10826 11:19:01.716321 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10827 11:19:01.733730 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10828 11:19:01.750124 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10829 11:19:01.765425 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10830 11:19:01.784977 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10831 11:19:01.800280 See 'systemctl status systemd-remount-fs.service' for details.
10832 11:19:01.852403 Mounting [0;1;39mKernel Configuration File System[0m...
10833 11:19:01.870553 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10834 11:19:01.887931 <46>[ 17.580252] systemd-journald[179]: Received client request to flush runtime journal.
10835 11:19:01.933113 Starting [0;1;39mLoad/Save Random Seed[0m...
10836 11:19:01.950178 Starting [0;1;39mApply Kernel Variables[0m...
10837 11:19:01.966377 Starting [0;1;39mCreate System Users[0m...
10838 11:19:01.984982 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10839 11:19:02.004737 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10840 11:19:02.020830 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10841 11:19:02.041014 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10842 11:19:02.060839 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10843 11:19:02.080480 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10844 11:19:02.123992 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10845 11:19:02.146689 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10846 11:19:02.160649 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10847 11:19:02.175753 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10848 11:19:02.228354 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10849 11:19:02.255800 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10850 11:19:02.276505 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10851 11:19:02.296097 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10852 11:19:02.336856 Starting [0;1;39mNetwork Time Synchronization[0m...
10853 11:19:02.363328 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10854 11:19:02.396213 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10855 11:19:02.449157 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10856 11:19:02.482221 <6>[ 18.174146] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10857 11:19:02.493548 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10858 11:19:02.497160 <6>[ 18.193246] remoteproc remoteproc0: scp is available
10859 11:19:02.507768 <4>[ 18.198837] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10860 11:19:02.513506 <6>[ 18.209026] remoteproc remoteproc0: powering up scp
10861 11:19:02.520176 <6>[ 18.210418] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10862 11:19:02.529876 <4>[ 18.214236] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10863 11:19:02.539457 <6>[ 18.222136] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10864 11:19:02.546449 <3>[ 18.231614] remoteproc remoteproc0: request_firmware failed: -2
10865 11:19:02.552689 <6>[ 18.240326] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10866 11:19:02.570034 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.<3>[ 18.260976] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10867 11:19:02.570477
10868 11:19:02.576045 <3>[ 18.269501] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10869 11:19:02.586445 <3>[ 18.277618] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10870 11:19:02.596312 [[0;32m OK [0m] Reached targ<3>[ 18.288538] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10871 11:19:02.605907 et [0;1;39mSyst<3>[ 18.297539] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10872 11:19:02.616147 em Time Synchron<3>[ 18.307031] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10873 11:19:02.622678 <6>[ 18.307430] usbcore: registered new interface driver r8152
10874 11:19:02.623195 ized[0m.
10875 11:19:02.629471 <3>[ 18.316591] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10876 11:19:02.639113 <4>[ 18.323077] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10877 11:19:02.645581 <3>[ 18.331327] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10878 11:19:02.657402 <4>[ 18.349768] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10879 11:19:02.664271 <6>[ 18.359733] mc: Linux media interface: v0.10
10880 11:19:02.670359 <3>[ 18.363997] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10881 11:19:02.680208 <6>[ 18.372898] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10882 11:19:02.689988 <3>[ 18.382484] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10883 11:19:02.696565 <6>[ 18.386445] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10884 11:19:02.703563 <3>[ 18.390735] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10885 11:19:02.710245 <6>[ 18.397756] pci_bus 0000:00: root bus resource [bus 00-ff]
10886 11:19:02.719711 <3>[ 18.405827] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10887 11:19:02.723327 <6>[ 18.406894] videodev: Linux video capture interface: v2.00
10888 11:19:02.733164 <6>[ 18.411459] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10889 11:19:02.743467 <6>[ 18.411474] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10890 11:19:02.749534 <6>[ 18.419392] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10891 11:19:02.756517 <3>[ 18.419890] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10892 11:19:02.762898 <6>[ 18.425527] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10893 11:19:02.772809 <3>[ 18.432719] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10894 11:19:02.780120 <6>[ 18.442566] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10895 11:19:02.789649 <4>[ 18.443530] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10896 11:19:02.796067 <4>[ 18.443549] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10897 11:19:02.802590 <3>[ 18.449756] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10898 11:19:02.809326 <6>[ 18.457890] pci 0000:00:00.0: supports D1 D2
10899 11:19:02.815563 <3>[ 18.463244] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10900 11:19:02.822084 <3>[ 18.464095] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10901 11:19:02.828822 <6>[ 18.473397] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10902 11:19:02.838860 <3>[ 18.479649] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10903 11:19:02.848387 <6>[ 18.488024] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10904 11:19:02.858332 <6>[ 18.488393] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10905 11:19:02.865081 <6>[ 18.490615] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10906 11:19:02.871736 <3>[ 18.496835] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10907 11:19:02.878511 <6>[ 18.499228] r8152 2-1.3:1.0 eth0: v1.12.13
10908 11:19:02.885095 <6>[ 18.505009] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10909 11:19:02.891358 <3>[ 18.563345] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10910 11:19:02.898024 <6>[ 18.566340] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10911 11:19:02.908068 <4>[ 18.582786] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10912 11:19:02.911132 <4>[ 18.582786] Fallback method does not support PEC.
10913 11:19:02.917985 <6>[ 18.585132] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10914 11:19:02.927939 <6>[ 18.620088] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10915 11:19:02.931482 <6>[ 18.620242] pci 0000:01:00.0: supports D1 D2
10916 11:19:02.938065 <6>[ 18.632152] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10917 11:19:02.944252 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10918 11:19:02.963075 <6>[ 18.655180] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10919 11:19:02.969865 <6>[ 18.662149] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10920 11:19:02.976111 <6>[ 18.662157] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10921 11:19:02.986171 <6>[ 18.662170] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10922 11:19:02.992706 <6>[ 18.662186] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10923 11:19:03.002532 <6>[ 18.662202] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10924 11:19:03.008999 [[0;32m OK [<3>[ 18.671291] elants_i2c 4-0010: invalid 'hello' packet: ff ff ff ff
10925 11:19:03.015622 0m] Finished [0<6>[ 18.678302] pci 0000:00:00.0: PCI bridge to [bus 01]
10926 11:19:03.022637 <3>[ 18.686567] elants_i2c 4-0010: (read fw id) unexpected response: ff ff
10927 11:19:03.032299 ;1;39mLoad/Save <6>[ 18.694401] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10928 11:19:03.042125 <3>[ 18.697026] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10929 11:19:03.048618 <6>[ 18.702384] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10930 11:19:03.055456 <6>[ 18.710333] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10931 11:19:03.065344 Screen …s of l<6>[ 18.742045] usbcore: registered new interface driver cdc_ether
10932 11:19:03.068935 eds:white:kbd_ba<6>[ 18.753532] Bluetooth: Core ver 2.22
10933 11:19:03.069018 cklight[0m.
10934 11:19:03.075054 <6>[ 18.753607] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10935 11:19:03.081892 <6>[ 18.754111] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10936 11:19:03.088697 <6>[ 18.772934] usbcore: registered new interface driver r8153_ecm
10937 11:19:03.094975 <5>[ 18.774036] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10938 11:19:03.101701 <6>[ 18.777505] NET: Registered PF_BLUETOOTH protocol family
10939 11:19:03.108201 <6>[ 18.785525] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10940 11:19:03.115167 <6>[ 18.789386] Bluetooth: HCI device and connection manager initialized
10941 11:19:03.121417 <6>[ 18.789408] Bluetooth: HCI socket layer initialized
10942 11:19:03.128464 <6>[ 18.796952] r8152 2-1.3:1.0 enx00e04c722dd6: renamed from eth0
10943 11:19:03.132115 <5>[ 18.798679] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10944 11:19:03.145279 <6>[ 18.798808] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10945 11:19:03.152324 <6>[ 18.798967] usbcore: registered new interface driver uvcvideo
10946 11:19:03.155779 <6>[ 18.802960] Bluetooth: L2CAP socket layer initialized
10947 11:19:03.162517 <6>[ 18.802983] Bluetooth: SCO socket layer initialized
10948 11:19:03.168895 <6>[ 18.804279] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10949 11:19:03.175548 <6>[ 18.808709] remoteproc remoteproc0: powering up scp
10950 11:19:03.182762 <4>[ 18.808757] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10951 11:19:03.188907 <3>[ 18.808765] remoteproc remoteproc0: request_firmware failed: -2
10952 11:19:03.198808 <3>[ 18.808769] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10953 11:19:03.205268 <3>[ 18.866101] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10954 11:19:03.215308 <3>[ 18.885285] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10955 11:19:03.224977 <4>[ 18.900001] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10956 11:19:03.228415 <6>[ 18.909798] usbcore: registered new interface driver btusb
10957 11:19:03.241772 <4>[ 18.910468] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10958 11:19:03.248086 <3>[ 18.910480] Bluetooth: hci0: Failed to load firmware file (-2)
10959 11:19:03.251758 <3>[ 18.910484] Bluetooth: hci0: Failed to set up firmware (-2)
10960 11:19:03.261339 <4>[ 18.910490] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10961 11:19:03.267954 <6>[ 18.916422] cfg80211: failed to load regulatory.db
10962 11:19:03.275179 <6>[ 18.968452] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10963 11:19:03.282250 <6>[ 18.976432] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10964 11:19:03.296012 [[0;32m OK [0m] Found device [0;1;39m/dev/t<3>[ 18.986333] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10965 11:19:03.302949 <3>[ 18.987239] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10966 11:19:03.303066 tyS0[0m.
10967 11:19:03.309481 <6>[ 19.003149] mt7921e 0000:01:00.0: ASIC revision: 79610010
10968 11:19:03.319656 <3>[ 19.004114] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10969 11:19:03.333177 <3>[ 19.026224] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10970 11:19:03.364770 <3>[ 19.058025] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10971 11:19:03.395878 <3>[ 19.088539] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10972 11:19:03.426305 <4>[ 19.115313] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10973 11:19:03.433175 <3>[ 19.121027] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10974 11:19:03.474738 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10975 11:19:03.487231 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10976 11:19:03.504279 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10977 11:19:03.522913 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10978 11:19:03.546542 [[0;32m OK [0m] Reached targ<4>[ 19.234619] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10979 11:19:03.546630 et [0;1;39mTimers[0m.
10980 11:19:03.567945 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10981 11:19:03.579424 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10982 11:19:03.595098 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10983 11:19:03.614730 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10984 11:19:03.650024 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10985 11:19:03.665637 <4>[ 19.355280] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10986 11:19:03.677439 Starting [0;1;39mUser Login Management[0m...
10987 11:19:03.694214 Starting [0;1;39mPermit User Sessions[0m...
10988 11:19:03.712091 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10989 11:19:03.731416 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10990 11:19:03.744896 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10991 11:19:03.754326 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10992 11:19:03.776285 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10993 11:19:03.790455 <4>[ 19.480102] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10994 11:19:03.801771 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10995 11:19:03.820824 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10996 11:19:03.839689 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10997 11:19:03.858973 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10998 11:19:03.912053 <4>[ 19.601775] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10999 11:19:03.918639 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11000 11:19:03.948584 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11001 11:19:03.965976
11002 11:19:03.966170
11003 11:19:03.968918 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11004 11:19:03.969092
11005 11:19:03.971967 debian-bullseye-arm64 login: root (automatic login)
11006 11:19:03.972060
11007 11:19:03.972127
11008 11:19:03.989412 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Mon Jun 5 10:57:14 UTC 2023 aarch64
11009 11:19:03.989497
11010 11:19:03.995974 The programs included with the Debian GNU/Linux system are free software;
11011 11:19:04.002718 the exact distribution terms for each program are described in the
11012 11:19:04.005757 individual files in /usr/share/doc/*/copyright.
11013 11:19:04.005840
11014 11:19:04.012355 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11015 11:19:04.015336 permitted by applicable law.
11016 11:19:04.015679 Matched prompt #10: / #
11018 11:19:04.015891 Setting prompt string to ['/ #']
11019 11:19:04.015983 end: 2.2.5.1 login-action (duration 00:00:20) [common]
11021 11:19:04.016176 end: 2.2.5 auto-login-action (duration 00:00:21) [common]
11022 11:19:04.016263 start: 2.2.6 expect-shell-connection (timeout 00:03:23) [common]
11023 11:19:04.016333 Setting prompt string to ['/ #']
11024 11:19:04.016394 Forcing a shell prompt, looking for ['/ #']
11026 11:19:04.066614 / #
11027 11:19:04.066753 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11028 11:19:04.066844 Waiting using forced prompt support (timeout 00:02:30)
11029 11:19:04.066945 <4>[ 19.721836] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11030 11:19:04.071654
11031 11:19:04.071926 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11032 11:19:04.072017 start: 2.2.7 export-device-env (timeout 00:03:23) [common]
11033 11:19:04.072115 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11034 11:19:04.072200 end: 2.2 depthcharge-retry (duration 00:01:37) [common]
11035 11:19:04.072283 end: 2 depthcharge-action (duration 00:01:37) [common]
11036 11:19:04.072370 start: 3 lava-test-retry (timeout 00:08:02) [common]
11037 11:19:04.072458 start: 3.1 lava-test-shell (timeout 00:08:02) [common]
11038 11:19:04.072531 Using namespace: common
11040 11:19:04.172786 / # #
11041 11:19:04.172968 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11042 11:19:04.173084 #<4>[ 19.841087] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11043 11:19:04.178245
11044 11:19:04.178501 Using /lava-10591274
11046 11:19:04.278776 / # export SHELL=/bin/sh
11047 11:19:04.278955 export SHELL=/bin/sh<4>[ 19.961487] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11048 11:19:04.283777
11050 11:19:04.425323 / # . /lava-10591274/environment
11051 11:19:04.425466 . /lava-105912<4>[ 20.081195] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11052 11:19:04.430500 74/environment
11054 11:19:04.531046 / # /lava-10591274/bin/lava-test-runner /lava-10591274/0
11055 11:19:04.531752 Test shell timeout: 10s (minimum of the action and connection timeout)
11056 11:19:04.533695 /lava-10591274/bin/lava-test-runner /lava-10591274/0<4>[ 20.200959] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
11057 11:19:04.536595
11058 11:19:04.577150 + export TESTRUN_ID=0_igt-kms-me<8>[ 20.256596] <LAVA_SIGNAL_STARTRUN 0_igt-kms-mediatek 10591274_1.5.2.3.1>
11059 11:19:04.577759 diatek
11060 11:19:04.578256 + cd /lava-10591274/0/tests/0_igt-kms-mediatek
11061 11:19:04.578718 + cat uuid
11062 11:19:04.579136 + UUID=10591274_1.5.2.3.1
11063 11:19:04.579545 + set +x
11064 11:19:04.580208 Received signal: <STARTRUN> 0_igt-kms-mediatek 10591274_1.5.2.3.1
11065 11:19:04.580633 Starting test lava.0_igt-kms-mediatek (10591274_1.5.2.3.1)
11066 11:19:04.581240 Skipping test definition patterns.
11067 11:19:04.591709 + IGT_FORCE_DRIVER=mediatek /usr/bin/igt-parser.sh core_auth core_getclient core_getstats core_getversion core_setmaster_vs_auth drm_read kms_addfb_basic kms_atomic km<8>[ 20.287630] <LAVA_SIGNAL_TESTSET START core_auth>
11068 11:19:04.592409 Received signal: <TESTSET> START core_auth
11069 11:19:04.592827 Starting test_set core_auth
11070 11:19:04.598340 s_flip_event_leak kms_prop_blob kms_setmode kms_vblank
11071 11:19:04.624833 <3>[ 20.320620] mt7921e 0000:01:00.0: hardware init failed
11072 11:19:04.627998 <14>[ 20.326362] [IGT] core_auth: executing
11073 11:19:04.638077 IGT-Version: 1.2<14>[ 20.330800] [IGT] core_auth: starting subtest getclient-simple
11074 11:19:04.644468 7.1-g766edf9 (aa<14>[ 20.338565] [IGT] core_auth: exiting, ret=0
11075 11:19:04.645058 rch64) (Linux: 6.1.31 aarch64)
11076 11:19:04.647934 Starting subtest: getclient-simple
11077 11:19:04.657686 Opened devic<8>[ 20.350132] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-simple RESULT=pass>
11078 11:19:04.658209 e: /dev/dri/card0
11079 11:19:04.658867 Received signal: <TESTCASE> TEST_CASE_ID=getclient-simple RESULT=pass
11081 11:19:04.664353 [1mSubtest getclient-simple: SUCCESS (0.000s)[0m
11082 11:19:04.681095 <14>[ 20.376929] [IGT] core_auth: executing
11083 11:19:04.687616 IGT-Version: 1.2<14>[ 20.381436] [IGT] core_auth: starting subtest getclient-master-drop
11084 11:19:04.694302 7.1-g766edf9 (aa<14>[ 20.389683] [IGT] core_auth: exiting, ret=0
11085 11:19:04.697408 rch64) (Linux: 6.1.31 aarch64)
11086 11:19:04.700650 Starting subtest: getclient-master-drop
11087 11:19:04.707447 Received signal: <TESTCASE> TEST_CASE_ID=getclient-master-drop RESULT=pass
11089 11:19:04.710625 Opened <8>[ 20.400884] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=getclient-master-drop RESULT=pass>
11090 11:19:04.711055 device: /dev/dri/card0
11091 11:19:04.717350 [1mSubtest getclient-master-drop: SUCCESS (0.000s)[0m
11092 11:19:04.730650 <14>[ 20.426660] [IGT] core_auth: executing
11093 11:19:04.737590 IGT-Version: 1.2<14>[ 20.431263] [IGT] core_auth: starting subtest basic-auth
11094 11:19:04.743888 7.1-g766edf9 (aa<14>[ 20.438251] [IGT] core_auth: exiting, ret=0
11095 11:19:04.747235 rch64) (Linux: 6.1.31 aarch64)
11096 11:19:04.747677 Opened device: /dev/dri/card0
11097 11:19:04.757320 Starting subtest:<8>[ 20.449637] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-auth RESULT=pass>
11098 11:19:04.757745 basic-auth
11099 11:19:04.758327 Received signal: <TESTCASE> TEST_CASE_ID=basic-auth RESULT=pass
11101 11:19:04.760568 [1mSubtest basic-auth: SUCCESS (0.000s)[0m
11102 11:19:04.780039 <14>[ 20.475798] [IGT] core_auth: executing
11103 11:19:04.786445 IGT-Version: 1.2<14>[ 20.480442] [IGT] core_auth: starting subtest many-magics
11104 11:19:04.789735 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11105 11:19:04.793215 Opened device: /dev/dri/card0
11106 11:19:04.796508 Starting subtest: many-magics
11107 11:19:04.799789 Reopening device failed after 1020 opens
11108 11:19:04.802925 <14>[ 20.500348] [IGT] core_auth: exiting, ret=0
11109 11:19:04.809609 [1mSubtest many-magics: SUCCESS (0.013s)[0m
11110 11:19:04.816058 <8>[ 20.511679] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=many-magics RESULT=pass>
11111 11:19:04.816904 Received signal: <TESTCASE> TEST_CASE_ID=many-magics RESULT=pass
11113 11:19:04.824297 <8>[ 20.520216] <LAVA_SIGNAL_TESTSET STOP>
11114 11:19:04.825152 Received signal: <TESTSET> STOP
11115 11:19:04.825625 Closing test_set core_auth
11116 11:19:04.864425 <14>[ 20.560500] [IGT] core_getclient: executing
11117 11:19:04.871376 IGT-Version: 1.2<14>[ 20.565392] [IGT] core_getclient: exiting, ret=0
11118 11:19:04.874177 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11119 11:19:04.877704 Opened device: /dev/dri/card0
11120 11:19:04.884355 S<8>[ 20.577486] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getclient RESULT=pass>
11121 11:19:04.885156 Received signal: <TESTCASE> TEST_CASE_ID=core_getclient RESULT=pass
11123 11:19:04.887218 UCCESS (0.006s)
11124 11:19:04.925465 <14>[ 20.621531] [IGT] core_getstats: executing
11125 11:19:04.932340 IGT-Version: 1.2<14>[ 20.626364] [IGT] core_getstats: exiting, ret=0
11126 11:19:04.935352 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11127 11:19:04.939044 Opened device: /dev/dri/card0
11128 11:19:04.945476 S<8>[ 20.638536] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getstats RESULT=pass>
11129 11:19:04.945993 UCCESS (0.006s)
11130 11:19:04.946677 Received signal: <TESTCASE> TEST_CASE_ID=core_getstats RESULT=pass
11132 11:19:04.987638 <14>[ 20.683764] [IGT] core_getversion: executing
11133 11:19:04.994557 IGT-Version: 1.2<14>[ 20.688740] [IGT] core_getversion: exiting, ret=0
11134 11:19:04.997520 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11135 11:19:05.001141 Opened device: /dev/dri/card0
11136 11:19:05.007440 S<8>[ 20.700795] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_getversion RESULT=pass>
11137 11:19:05.008203 Received signal: <TESTCASE> TEST_CASE_ID=core_getversion RESULT=pass
11139 11:19:05.010527 UCCESS (0.006s)
11140 11:19:05.050075 <14>[ 20.746086] [IGT] core_setmaster_vs_auth: executing
11141 11:19:05.056581 IGT-Version: 1.2<14>[ 20.752214] [IGT] core_setmaster_vs_auth: exiting, ret=0
11142 11:19:05.063422 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11143 11:19:05.063931 Opened device: /dev/dri/card0
11144 11:19:05.073336 S<8>[ 20.764633] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass>
11145 11:19:05.073868 UCCESS (0.007s)
11146 11:19:05.074573 Received signal: <TESTCASE> TEST_CASE_ID=core_setmaster_vs_auth RESULT=pass
11148 11:19:05.097730 <8>[ 20.793788] <LAVA_SIGNAL_TESTSET START drm_read>
11149 11:19:05.098500 Received signal: <TESTSET> START drm_read
11150 11:19:05.098918 Starting test_set drm_read
11151 11:19:05.120818 <14>[ 20.816526] [IGT] drm_read: executing
11152 11:19:05.127182 IGT-Version: 1.2<14>[ 20.821186] [IGT] drm_read: exiting, ret=77
11153 11:19:05.130490 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11154 11:19:05.133922 Opened device: /dev/dri/card0
11155 11:19:05.140576 N<8>[ 20.832666] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-buffer RESULT=skip>
11156 11:19:05.141390 Received signal: <TESTCASE> TEST_CASE_ID=invalid-buffer RESULT=skip
11158 11:19:05.143661 o KMS driver or no outputs, pipes: 8, outputs: 0
11159 11:19:05.147124 [1mSubtest invalid-buffer: SKIP (0.000s)[0m
11160 11:19:05.161989 <14>[ 20.857912] [IGT] drm_read: executing
11161 11:19:05.168706 IGT-Version: 1.2<14>[ 20.862456] [IGT] drm_read: exiting, ret=77
11162 11:19:05.171982 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11163 11:19:05.175395 Opened device: /dev/dri/card0
11164 11:19:05.182096 N<8>[ 20.873518] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=fault-buffer RESULT=skip>
11165 11:19:05.182861 Received signal: <TESTCASE> TEST_CASE_ID=fault-buffer RESULT=skip
11167 11:19:05.184800 o KMS driver or no outputs, pipes: 8, outputs: 0
11168 11:19:05.188190 [1mSubtest fault-buffer: SKIP (0.000s)[0m
11169 11:19:05.203611 <14>[ 20.899693] [IGT] drm_read: executing
11170 11:19:05.210508 IGT-Version: 1.2<14>[ 20.904296] [IGT] drm_read: exiting, ret=77
11171 11:19:05.213928 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11172 11:19:05.217232 Opened device: /dev/dri/card0
11173 11:19:05.223528 N<8>[ 20.915560] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-block RESULT=skip>
11174 11:19:05.224314 Received signal: <TESTCASE> TEST_CASE_ID=empty-block RESULT=skip
11176 11:19:05.227172 o KMS driver or no outputs, pipes: 8, outputs: 0
11177 11:19:05.230103 [1mSubtest empty-block: SKIP (0.000s)[0m
11178 11:19:05.243986 <14>[ 20.940623] [IGT] drm_read: executing
11179 11:19:05.250561 IGT-Version: 1.2<14>[ 20.945175] [IGT] drm_read: exiting, ret=77
11180 11:19:05.254172 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11181 11:19:05.257680 Opened device: /dev/dri/card0
11182 11:19:05.264053 N<8>[ 20.956266] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=empty-nonblock RESULT=skip>
11183 11:19:05.264317 Received signal: <TESTCASE> TEST_CASE_ID=empty-nonblock RESULT=skip
11185 11:19:05.267615 o KMS driver or no outputs, pipes: 8, outputs: 0
11186 11:19:05.270694 [1mSubtest empty-nonblock: SKIP (0.000s)[0m
11187 11:19:05.286760 <14>[ 20.982796] [IGT] drm_read: executing
11188 11:19:05.293335 IGT-Version: 1.2<14>[ 20.987715] [IGT] drm_read: exiting, ret=77
11189 11:19:05.296644 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11190 11:19:05.299624 Opened device: /dev/dri/card0
11191 11:19:05.306318 N<8>[ 20.998584] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-block RESULT=skip>
11192 11:19:05.306592 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-block RESULT=skip
11194 11:19:05.309469 o KMS driver or no outputs, pipes: 8, outputs: 0
11195 11:19:05.316135 [1mSubtest short-buffer-block: SKIP (0.000s)[0m
11196 11:19:05.328438 <14>[ 21.024616] [IGT] drm_read: executing
11197 11:19:05.334913 IGT-Version: 1.2<14>[ 21.029279] [IGT] drm_read: exiting, ret=77
11198 11:19:05.337960 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11199 11:19:05.341624 Opened device: /dev/dri/card0
11200 11:19:05.348029 N<8>[ 21.040379] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-nonblock RESULT=skip>
11201 11:19:05.348286 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-nonblock RESULT=skip
11203 11:19:05.351369 o KMS driver or no outputs, pipes: 8, outputs: 0
11204 11:19:05.357889 [1mSubtest short-buffer-nonblock: SKIP (0.000s)[0m
11205 11:19:05.371211 <14>[ 21.067502] [IGT] drm_read: executing
11206 11:19:05.377962 IGT-Version: 1.2<14>[ 21.072178] [IGT] drm_read: exiting, ret=77
11207 11:19:05.380871 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11208 11:19:05.384521 Opened device: /dev/dri/card0
11209 11:19:05.390908 N<8>[ 21.083461] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=short-buffer-wakeup RESULT=skip>
11210 11:19:05.391188 Received signal: <TESTCASE> TEST_CASE_ID=short-buffer-wakeup RESULT=skip
11212 11:19:05.397700 o KMS driver or no outputs, pipe<8>[ 21.093744] <LAVA_SIGNAL_TESTSET STOP>
11213 11:19:05.397788 s: 8, outputs: 0
11214 11:19:05.398037 Received signal: <TESTSET> STOP
11215 11:19:05.398102 Closing test_set drm_read
11216 11:19:05.404285 [1mSubtest short-buffer-wakeup: SKIP (0.000s)[0m
11217 11:19:05.423907 <8>[ 21.120083] <LAVA_SIGNAL_TESTSET START kms_addfb_basic>
11218 11:19:05.424158 Received signal: <TESTSET> START kms_addfb_basic
11219 11:19:05.424226 Starting test_set kms_addfb_basic
11220 11:19:05.446152 <14>[ 21.142601] [IGT] kms_addfb_basic: executing
11221 11:19:05.452922 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11222 11:19:05.459358 <14>[ 21.152116] [IGT] kms_addfb_basic: starting subtest unused-handle
11223 11:19:05.459442 Opened device: /dev/dri/card0
11224 11:19:05.462472 Starting subtest: unused-handle
11225 11:19:05.469162 [1mSubtest unused-handle: SUCCESS (0.000s)[0m
11226 11:19:05.475681 Test requiremen<14>[ 21.169575] [IGT] kms_addfb_basic: exiting, ret=0
11227 11:19:05.479094 t not met in function igt_require_i915, file ../lib/drmtest.c:721:
11228 11:19:05.489004 Test require<8>[ 21.181534] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-handle RESULT=pass>
11229 11:19:05.489089 ment: is_i915_device(fd)
11230 11:19:05.489330 Received signal: <TESTCASE> TEST_CASE_ID=unused-handle RESULT=pass
11232 11:19:05.498772 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11233 11:19:05.502419 Test requirement: is_i915_device(fd)
11234 11:19:05.505686 No KMS driver or no outputs, pipes: 8, outputs: 0
11235 11:19:05.512095 <14>[ 21.207768] [IGT] kms_addfb_basic: executing
11236 11:19:05.515343 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11237 11:19:05.522200 <14>[ 21.217398] [IGT] kms_addfb_basic: starting subtest unused-pitches
11238 11:19:05.525373 Opened device: /dev/dri/card0
11239 11:19:05.528704 Starting subtest: unused-pitches
11240 11:19:05.532105 [1mSubtest unused-pitches: SUCCESS (0.000s)[0m
11241 11:19:05.538677 Test requirement<14>[ 21.234818] [IGT] kms_addfb_basic: exiting, ret=0
11242 11:19:05.545284 not met in function igt_require_i915, file ../lib/drmtest.c:721:
11243 11:19:05.555026 Test requirem<8>[ 21.247490] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-pitches RESULT=pass>
11244 11:19:05.555110 ent: is_i915_device(fd)
11245 11:19:05.555348 Received signal: <TESTCASE> TEST_CASE_ID=unused-pitches RESULT=pass
11247 11:19:05.561719 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11248 11:19:05.564957 Test requirement: is_i915_device(fd)
11249 11:19:05.571493 No KMS driver or no outputs, pipes: 8, outputs: 0
11250 11:19:05.578224 <14>[ 21.273635] [IGT] kms_addfb_basic: executing
11251 11:19:05.581223 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11252 11:19:05.588364 <14>[ 21.283389] [IGT] kms_addfb_basic: starting subtest unused-offsets
11253 11:19:05.591129 Opened device: /dev/dri/card0
11254 11:19:05.594544 Starting subtest: unused-offsets
11255 11:19:05.598097 [1mSubtest unused-offsets: SUCCESS (0.000s)[0m
11256 11:19:05.604497 Test requirement<14>[ 21.300905] [IGT] kms_addfb_basic: exiting, ret=0
11257 11:19:05.611174 not met in function igt_require_i915, file ../lib/drmtest.c:721:
11258 11:19:05.621184 Test requirem<8>[ 21.313145] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-offsets RESULT=pass>
11259 11:19:05.621268 ent: is_i915_device(fd)
11260 11:19:05.621507 Received signal: <TESTCASE> TEST_CASE_ID=unused-offsets RESULT=pass
11262 11:19:05.627814 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11263 11:19:05.631199 Test requirement: is_i915_device(fd)
11264 11:19:05.637584 No KMS driver or no outputs, pipes: 8, outputs: 0
11265 11:19:05.644032 <14>[ 21.339653] [IGT] kms_addfb_basic: executing
11266 11:19:05.647558 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11267 11:19:05.654279 <14>[ 21.349131] [IGT] kms_addfb_basic: starting subtest unused-modifier
11268 11:19:05.657446 Opened device: /dev/dri/card0
11269 11:19:05.660528 Starting subtest: unused-modifier
11270 11:19:05.663975 [1mSubtest unused-modifier: SUCCESS (0.000s)[0m
11271 11:19:05.670671 Test requir<14>[ 21.366662] [IGT] kms_addfb_basic: exiting, ret=0
11272 11:19:05.677125 ement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11273 11:19:05.686910 Test req<8>[ 21.378837] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=unused-modifier RESULT=pass>
11274 11:19:05.686992 uirement: is_i915_device(fd)
11275 11:19:05.687231 Received signal: <TESTCASE> TEST_CASE_ID=unused-modifier RESULT=pass
11277 11:19:05.697003 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11278 11:19:05.700195 Test requirement: is_i915_device(fd)
11279 11:19:05.703483 No KMS driver or no outputs, pipes: 8, outputs: 0
11280 11:19:05.709978 <14>[ 21.405238] [IGT] kms_addfb_basic: executing
11281 11:19:05.713065 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11282 11:19:05.719621 <14>[ 21.415193] [IGT] kms_addfb_basic: starting subtest clobberred-modifier
11283 11:19:05.723301 Opened device: /dev/dri/card0
11284 11:19:05.726346 Starting subtest: clobberred-modifier
11285 11:19:05.736438 Test requirement not met in function igt_require_i915, fil<14>[ 21.432912] [IGT] kms_addfb_basic: exiting, ret=77
11286 11:19:05.739871 e ../lib/drmtest.c:721:
11287 11:19:05.743357 Test requirement: is_i915_device(fd)
11288 11:19:05.752694 [1mSubtest clobb<8>[ 21.445341] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clobberred-modifier RESULT=skip>
11289 11:19:05.752956 Received signal: <TESTCASE> TEST_CASE_ID=clobberred-modifier RESULT=skip
11291 11:19:05.755962 erred-modifier: SKIP (0.000s)[0m
11292 11:19:05.762672 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11293 11:19:05.765823 Test requirement: is_i915_device(fd)
11294 11:19:05.775866 Test requirement not met in function igt_require_i91<14>[ 21.471559] [IGT] kms_addfb_basic: executing
11295 11:19:05.779232 5, file ../lib/drmtest.c:721:
11296 11:19:05.789048 Test requirement: is_i915_device(<14>[ 21.481382] [IGT] kms_addfb_basic: starting subtest invalid-smem-bo-on-discrete
11297 11:19:05.789182 fd)
11298 11:19:05.792435 No KMS driver or no outputs, pipes: 8, outputs: 0
11299 11:19:05.799032 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11300 11:19:05.805675 Opened d<14>[ 21.499825] [IGT] kms_addfb_basic: exiting, ret=77
11301 11:19:05.805787 evice: /dev/dri/card0
11302 11:19:05.809131 Starting subtest: invalid-smem-bo-on-discrete
11303 11:19:05.819073 Test requi<8>[ 21.512220] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip>
11304 11:19:05.819356 Received signal: <TESTCASE> TEST_CASE_ID=invalid-smem-bo-on-discrete RESULT=skip
11306 11:19:05.825573 rement not met in function igt_require_intel, file ../lib/drmtest.c:716:
11307 11:19:05.828590 Test requirement: is_intel_device(fd)
11308 11:19:05.835306 [1mSubtest invalid-smem-bo-on-discrete: SKIP (0.000s)[0m
11309 11:19:05.842095 Test requirement not met in functio<14>[ 21.539060] [IGT] kms_addfb_basic: executing
11310 11:19:05.845322 n igt_require_i915, file ../lib/drmtest.c:721:
11311 11:19:05.855114 Test requirement<14>[ 21.548928] [IGT] kms_addfb_basic: starting subtest legacy-format
11312 11:19:05.855222 : is_i915_device(fd)
11313 11:19:05.865121 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11314 11:19:05.868463 Test requirement: is_i915_device(fd)
11315 11:19:05.871464 No KMS driver or no outputs, pipes: 8, outputs: 0
11316 11:19:05.881516 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)<14>[ 21.578097] [IGT] kms_addfb_basic: exiting, ret=0
11317 11:19:05.881628
11318 11:19:05.884701 Opened device: /dev/dri/card0
11319 11:19:05.887841 Starting subtest: legacy-format
11320 11:19:05.894984 Successfully f<8>[ 21.589474] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=legacy-format RESULT=pass>
11321 11:19:05.895858 Received signal: <TESTCASE> TEST_CASE_ID=legacy-format RESULT=pass
11323 11:19:05.898373 uzzed 10000 {bpp, depth} variations
11324 11:19:05.905089 [1mSubtest legacy-format: SUCCESS (0.012s)[0m
11325 11:19:05.911453 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11326 11:19:05.914620 Test requirement: is_i915_device(fd)
11327 11:19:05.917835 T<14>[ 21.614978] [IGT] kms_addfb_basic: executing
11328 11:19:05.924617 est requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11329 11:19:05.934604 Test requireme<14>[ 21.627655] [IGT] kms_addfb_basic: starting subtest no-handle
11330 11:19:05.935333 nt: is_i915_device(fd)
11331 11:19:05.941022 No KMS driver or no outputs, pipes: 8, outputs: 0
11332 11:19:05.947767 IGT-Version: 1.27.1-g<14>[ 21.641780] [IGT] kms_addfb_basic: exiting, ret=0
11333 11:19:05.950689 766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11334 11:19:05.954128 Opened device: /dev/dri/card0
11335 11:19:05.960667 Starti<8>[ 21.653970] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=no-handle RESULT=pass>
11336 11:19:05.961267 ng subtest: no-handle
11337 11:19:05.962100 Received signal: <TESTCASE> TEST_CASE_ID=no-handle RESULT=pass
11339 11:19:05.967206 [1mSubtest no-handle: SUCCESS (0.000s)[0m
11340 11:19:05.973967 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11341 11:19:05.977364 Test requirement: is_i915_device(fd)
11342 11:19:05.983929 Test requirement no<14>[ 21.678496] [IGT] kms_addfb_basic: executing
11343 11:19:05.987296 t met in function igt_require_i915, file ../lib/drmtest.c:721:
11344 11:19:05.996878 Test requirement: is_i915_device<14>[ 21.691660] [IGT] kms_addfb_basic: starting subtest basic
11345 11:19:05.996996 (fd)
11346 11:19:06.003276 No KMS driver or no outputs, pipes: 8, outputs: 0
11347 11:19:06.009756 IGT-Version: 1.27.1-g766edf9 (aarch64) <14>[ 21.705602] [IGT] kms_addfb_basic: exiting, ret=0
11348 11:19:06.013505 (Linux: 6.1.31 aarch64)
11349 11:19:06.016415 Opened device: /dev/dri/card0
11350 11:19:06.016524 Starting subtest: basic
11351 11:19:06.022989 <8>[ 21.717877] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
11352 11:19:06.023103
11353 11:19:06.023380 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
11355 11:19:06.026040 [1mSubtest basic: SUCCESS (0.000s)[0m
11356 11:19:06.035788 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11357 11:19:06.039577 Test requirement: is_i915_device(fd)
11358 11:19:06.045903 Test requirement not met in function igt_requ<14>[ 21.742659] [IGT] kms_addfb_basic: executing
11359 11:19:06.049032 ire_i915, file ../lib/drmtest.c:721:
11360 11:19:06.052621 Test requirement: is_i915_device(fd)
11361 11:19:06.062338 No KMS driver or no <14>[ 21.755364] [IGT] kms_addfb_basic: starting subtest bad-pitch-0
11362 11:19:06.062418 outputs, pipes: 8, outputs: 0
11363 11:19:06.068892 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11364 11:19:06.075215 O<14>[ 21.769714] [IGT] kms_addfb_basic: exiting, ret=0
11365 11:19:06.075294 pened device: /dev/dri/card0
11366 11:19:06.078727 Starting subtest: bad-pitch-0
11367 11:19:06.088588 [1mSubtest bad-pit<8>[ 21.781751] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-0 RESULT=pass>
11368 11:19:06.088867 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-0 RESULT=pass
11370 11:19:06.091932 ch-0: SUCCESS (0.000s)[0m
11371 11:19:06.098297 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11372 11:19:06.101844 Test requirement: is_i915_device(fd)
11373 11:19:06.111785 Test requirement not met in function igt_require_i915, file ../lib/drmtest.<14>[ 21.807754] [IGT] kms_addfb_basic: executing
11374 11:19:06.111894 c:721:
11375 11:19:06.114785 Test requirement: is_i915_device(fd)
11376 11:19:06.121581 No KMS driver or no outputs, pipes: 8, outputs: 0
11377 11:19:06.128046 <14>[ 21.821337] [IGT] kms_addfb_basic: starting subtest bad-pitch-32
11378 11:19:06.128145
11379 11:19:06.131509 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11380 11:19:06.134590 Opened device: /dev/dri/card0
11381 11:19:06.141603 <14>[ 21.835812] [IGT] kms_addfb_basic: exiting, ret=0
11382 11:19:06.144426 Starting subtest: bad-pitch-32
11383 11:19:06.147929 [1mSubtest bad-pitch-32: SUCCESS (0.000s)[0m
11384 11:19:06.154376 <8>[ 21.847886] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-32 RESULT=pass>
11385 11:19:06.154653 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-32 RESULT=pass
11387 11:19:06.160745 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11388 11:19:06.164178 Test requirement: is_i915_device(fd)
11389 11:19:06.170651 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11390 11:19:06.177337 Test<14>[ 21.873458] [IGT] kms_addfb_basic: executing
11391 11:19:06.180580 requirement: is_i915_device(fd)
11392 11:19:06.183996 No KMS driver or no outputs, pipes: 8, outputs: 0
11393 11:19:06.190387 IGT-Version<14>[ 21.886006] [IGT] kms_addfb_basic: starting subtest bad-pitch-63
11394 11:19:06.197386 : 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11395 11:19:06.200321 Opened device: /dev/dri/card0
11396 11:19:06.203630 Starting sub<14>[ 21.900481] [IGT] kms_addfb_basic: exiting, ret=0
11397 11:19:06.206840 test: bad-pitch-63
11398 11:19:06.210628 [1mSubtest bad-pitch-63: SUCCESS (0.000s)[0m
11399 11:19:06.219936 Test require<8>[ 21.912618] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-63 RESULT=pass>
11400 11:19:06.220198 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-63 RESULT=pass
11402 11:19:06.226740 ment not met in function igt_require_i915, file ../lib/drmtest.c:721:
11403 11:19:06.230170 Test requirement: is_i915_device(fd)
11404 11:19:06.236720 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11405 11:19:06.243413 Test requirement<14>[ 21.938284] [IGT] kms_addfb_basic: executing
11406 11:19:06.243513 : is_i915_device(fd)
11407 11:19:06.246615 No KMS driver or no outputs, pipes: 8, outputs: 0
11408 11:19:06.256140 IGT-Version: 1.27.1-g76<14>[ 21.950754] [IGT] kms_addfb_basic: starting subtest bad-pitch-128
11409 11:19:06.259652 6edf9 (aarch64) (Linux: 6.1.31 aarch64)
11410 11:19:06.262923 Opened device: /dev/dri/card0
11411 11:19:06.269655 Starting subtest: bad-pi<14>[ 21.965460] [IGT] kms_addfb_basic: exiting, ret=0
11412 11:19:06.269732 tch-128
11413 11:19:06.276242 [1mSubtest bad-pitch-128: SUCCESS (0.000s)[0m
11414 11:19:06.282990 Test requirement not m<8>[ 21.977437] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-128 RESULT=pass>
11415 11:19:06.283287 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-128 RESULT=pass
11417 11:19:06.289770 et in function igt_require_i915, file ../lib/drmtest.c:721:
11418 11:19:06.292554 Test requirement: is_i915_device(fd)
11419 11:19:06.299139 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11420 11:19:06.302597 Test requirement: is_i915_device(fd)
11421 11:19:06.309231 No K<14>[ 22.003588] [IGT] kms_addfb_basic: executing
11422 11:19:06.312536 MS driver or no outputs, pipes: 8, outputs: 0
11423 11:19:06.322255 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.<14>[ 22.017131] [IGT] kms_addfb_basic: starting subtest bad-pitch-256
11424 11:19:06.325859 1.31 aarch64)
11425 11:19:06.326135 Opened device: /dev/dri/card0
11426 11:19:06.328967 Starting subtest: bad-pitch-256
11427 11:19:06.335472 [1mSubtest bad-p<14>[ 22.031713] [IGT] kms_addfb_basic: exiting, ret=0
11428 11:19:06.338904 itch-256: SUCCESS (0.000s)[0m
11429 11:19:06.348692 Test requirement not met in function igt_require<8>[ 22.043730] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-256 RESULT=pass>
11430 11:19:06.349434 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-256 RESULT=pass
11432 11:19:06.352347 _i915, file ../lib/drmtest.c:721:
11433 11:19:06.355510 Test requirement: is_i915_device(fd)
11434 11:19:06.365452 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11435 11:19:06.369134 Test requirement: is_i915_device(fd)
11436 11:19:06.375684 No KMS driver or no outputs, p<14>[ 22.069889] [IGT] kms_addfb_basic: executing
11437 11:19:06.376245 ipes: 8, outputs: 0
11438 11:19:06.382466 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11439 11:19:06.389220 Opened devi<14>[ 22.083551] [IGT] kms_addfb_basic: starting subtest bad-pitch-1024
11440 11:19:06.392596 ce: /dev/dri/card0
11441 11:19:06.396009 Starting subtest: bad-pitch-1024
11442 11:19:06.402240 [1mSubtest bad-pitch-1024: SUCCESS (0.000<14>[ 22.098154] [IGT] kms_addfb_basic: exiting, ret=0
11443 11:19:06.405563 s)[0m
11444 11:19:06.418998 Test requirement not met in function igt_require_i915, file ../lib/drmte<8>[ 22.110286] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-1024 RESULT=pass>
11445 11:19:06.419570 st.c:721:
11446 11:19:06.420218 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-1024 RESULT=pass
11448 11:19:06.421786 Test requirement: is_i915_device(fd)
11449 11:19:06.428883 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11450 11:19:06.431919 Test requirement: is_i915_device(fd)
11451 11:19:06.434945 No KMS driver or no outputs, pipes: 8, outputs: 0
11452 11:19:06.441713 <14>[ 22.136535] [IGT] kms_addfb_basic: executing
11453 11:19:06.448303 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11454 11:19:06.448914 Opened device: /dev/dri/card0
11455 11:19:06.455335 <14>[ 22.149700] [IGT] kms_addfb_basic: starting subtest bad-pitch-999
11456 11:19:06.457990 Starting subtest: bad-pitch-999
11457 11:19:06.465334 [1mSubtest bad-pitch-999: SUCCESS (0.000s)[0m
11458 11:19:06.468220 Test requireme<14>[ 22.164426] [IGT] kms_addfb_basic: exiting, ret=0
11459 11:19:06.475088 nt not met in function igt_require_i915, file ../lib/drmtest.c:721:
11460 11:19:06.484886 Test requir<8>[ 22.176737] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-999 RESULT=pass>
11461 11:19:06.485453 ement: is_i915_device(fd)
11462 11:19:06.486115 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-999 RESULT=pass
11464 11:19:06.494944 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11465 11:19:06.497797 Test requirement: is_i915_device(fd)
11466 11:19:06.501245 No KMS driver or no outputs, pipes: 8, outputs: 0
11467 11:19:06.507841 <14>[ 22.202627] [IGT] kms_addfb_basic: executing
11468 11:19:06.511226 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11469 11:19:06.514493 Opened device: /dev/dri/card0
11470 11:19:06.521012 <14>[ 22.214923] [IGT] kms_addfb_basic: starting subtest bad-pitch-65536
11471 11:19:06.524422 Starting subtest: bad-pitch-65536
11472 11:19:06.527446 [1mSubtest bad-pitch-65536: SUCCESS (0.000s)[0m
11473 11:19:06.533876 Test requi<14>[ 22.229791] [IGT] kms_addfb_basic: exiting, ret=0
11474 11:19:06.540380 rement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11475 11:19:06.550281 Test re<8>[ 22.242084] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bad-pitch-65536 RESULT=pass>
11476 11:19:06.550873 quirement: is_i915_device(fd)
11477 11:19:06.551571 Received signal: <TESTCASE> TEST_CASE_ID=bad-pitch-65536 RESULT=pass
11479 11:19:06.560638 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11480 11:19:06.563738 Test requirement: is_i915_device(fd)
11481 11:19:06.566939 No KMS driver or no outputs, pipes: 8, outputs: 0
11482 11:19:06.570476 <14>[ 22.267923] [IGT] kms_addfb_basic: executing
11483 11:19:06.576977 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11484 11:19:06.580443 Opened device: /dev/dri/card0
11485 11:19:06.586873 <14>[ 22.282391] [IGT] kms_addfb_basic: starting subtest invalid-get-prop-any
11486 11:19:06.593355 Starting subtest: invalid-get-prop-any
11487 11:19:06.600330 [1mSubtest invalid-get-<14>[ 22.294615] [IGT] kms_addfb_basic: exiting, ret=0
11488 11:19:06.603391 prop-any: SUCCESS (0.000s)[0m
11489 11:19:06.613422 Test requirement not met in function igt_require<8>[ 22.306400] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
11490 11:19:06.614164 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
11492 11:19:06.616856 _i915, file ../lib/drmtest.c:721:
11493 11:19:06.619861 Test requirement: is_i915_device(fd)
11494 11:19:06.626583 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11495 11:19:06.629678 Test requirement: is_i915_device(fd)
11496 11:19:06.636559 No KMS driver or no outputs, p<14>[ 22.332889] [IGT] kms_addfb_basic: executing
11497 11:19:06.639484 ipes: 8, outputs: 0
11498 11:19:06.646365 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11499 11:19:06.646790 Opened device: /dev/dri/card0
11500 11:19:06.652939 <14>[ 22.348913] [IGT] kms_addfb_basic: starting subtest invalid-get-prop
11501 11:19:06.656068 Starting subtest: invalid-get-prop
11502 11:19:06.666086 [1mSubtest invalid-get-prop<14>[ 22.361102] [IGT] kms_addfb_basic: exiting, ret=0
11503 11:19:06.666173 : SUCCESS (0.000s)[0m
11504 11:19:06.679655 Test requirement not met in function igt_require_i915, f<8>[ 22.372868] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
11505 11:19:06.679914 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
11507 11:19:06.682462 ile ../lib/drmtest.c:721:
11508 11:19:06.686189 Test requirement: is_i915_device(fd)
11509 11:19:06.692407 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11510 11:19:06.695448 Test requirement: is_i915_device(fd)
11511 11:19:06.702437 No KMS driver or no ou<14>[ 22.397943] [IGT] kms_addfb_basic: executing
11512 11:19:06.705436 tputs, pipes: 8, outputs: 0
11513 11:19:06.708933 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11514 11:19:06.712023 Opened device: /dev/dri/card0
11515 11:19:06.718736 <14>[ 22.413238] [IGT] kms_addfb_basic: starting subtest invalid-set-prop-any
11516 11:19:06.722206 Starting subtest: invalid-set-prop-any
11517 11:19:06.731804 [1mSubtest invalid-set-<14>[ 22.426479] [IGT] kms_addfb_basic: exiting, ret=0
11518 11:19:06.731887 prop-any: SUCCESS (0.000s)[0m
11519 11:19:06.745049 Test requirement not met in function igt_require<8>[ 22.438325] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
11520 11:19:06.745303 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
11522 11:19:06.748471 _i915, file ../lib/drmtest.c:721:
11523 11:19:06.751795 Test requirement: is_i915_device(fd)
11524 11:19:06.758485 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11525 11:19:06.761536 Test requirement: is_i915_device(fd)
11526 11:19:06.768192 No KMS driver <14>[ 22.463777] [IGT] kms_addfb_basic: executing
11527 11:19:06.771705 or no outputs, pipes: 8, outputs: 0
11528 11:19:06.777976 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11529 11:19:06.784654 Opened device: /dev/dri/car<14>[ 22.479105] [IGT] kms_addfb_basic: starting subtest invalid-set-prop
11530 11:19:06.784738 d0
11531 11:19:06.787788 Starting subtest: invalid-set-prop
11532 11:19:06.798009 [1mSubtest invalid-set-prop<14>[ 22.492377] [IGT] kms_addfb_basic: exiting, ret=0
11533 11:19:06.798093 : SUCCESS (0.000s)[0m
11534 11:19:06.811485 Test requirement not met in function igt_require_i915, f<8>[ 22.504197] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
11535 11:19:06.811743 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
11537 11:19:06.814645 ile ../lib/drmtest.c:721:
11538 11:19:06.817717 Test requirement: is_i915_device(fd)
11539 11:19:06.824617 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11540 11:19:06.827529 Test requirement: is_i915_device(fd)
11541 11:19:06.834123 No KMS driver or no ou<14>[ 22.529574] [IGT] kms_addfb_basic: executing
11542 11:19:06.837628 tputs, pipes: 8, outputs: 0
11543 11:19:06.841188 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11544 11:19:06.844088 Opened device: /dev/dri/card0
11545 11:19:06.850766 <14>[ 22.547190] [IGT] kms_addfb_basic: starting subtest master-rmfb
11546 11:19:06.853938 Starting subtest: master-rmfb
11547 11:19:06.860990 [1mSubtest maste<14>[ 22.556569] [IGT] kms_addfb_basic: exiting, ret=0
11548 11:19:06.863921 r-rmfb: SUCCESS (0.000s)[0m
11549 11:19:06.873998 Test requirement not met in function igt_require_i<8>[ 22.568701] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=master-rmfb RESULT=pass>
11550 11:19:06.874258 Received signal: <TESTCASE> TEST_CASE_ID=master-rmfb RESULT=pass
11552 11:19:06.877062 915, file ../lib/drmtest.c:721:
11553 11:19:06.880516 Test requirement: is_i915_device(fd)
11554 11:19:06.887505 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11555 11:19:06.890321 Test requirement: is_i915_device(fd)
11556 11:19:06.896804 No KMS driver or<14>[ 22.593739] [IGT] kms_addfb_basic: executing
11557 11:19:06.900366 no outputs, pipes: 8, outputs: 0
11558 11:19:06.907009 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11559 11:19:06.909998 Opened device: /dev/dri/card0
11560 11:19:06.920645 <14>[ 22.613639] [IGT] kms_addfb_basic: starting subtest addfb25-modifier-no-flag
11561 11:19:06.926906 Starting subtest<14>[ 22.621680] [IGT] kms_addfb_basic: exiting, ret=0
11562 11:19:06.930418 : addfb25-modifier-no-flag
11563 11:19:06.940277 [1mSubtest addfb25-modifier-no-flag: SUCCESS (0.000<8>[ 22.633750] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass>
11564 11:19:06.940534 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-modifier-no-flag RESULT=pass
11566 11:19:06.943199 s)[0m
11567 11:19:06.950196 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11568 11:19:06.953530 Test requirement: is_i915_device(fd)
11569 11:19:06.963278 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:72<14>[ 22.659812] [IGT] kms_addfb_basic: executing
11570 11:19:06.963363 1:
11571 11:19:06.966723 Test requirement: is_i915_device(fd)
11572 11:19:06.973148 No KMS driver or no outputs, pipes: 8, outputs: 0
11573 11:19:06.976333 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11574 11:19:06.986271 Opened device: /dev<14>[ 22.679791] [IGT] kms_addfb_basic: starting subtest addfb25-bad-modifier
11575 11:19:06.986357 /dri/card0
11576 11:19:06.989914 Starting subtest: addfb25-bad-modifier
11577 11:19:07.002914 (kms_addfb_basic:431) CRITICAL: Test assertion failure function addfb25_<14>[ 22.697531] [IGT] kms_addfb_basic: exiting, ret=98
11578 11:19:07.005931 tests, file ../tests/kms_addfb_basic.c:662:
11579 11:19:07.015745 (kms_addfb_basic:431) CRITICAL: Fai<8>[ 22.709762] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-bad-modifier RESULT=fail>
11580 11:19:07.016002 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-bad-modifier RESULT=fail
11582 11:19:07.032644 led assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11583 11:19:07.035581 (kms_addfb_basic:431) CRITICAL: error: 0 != -1
11584 11:19:07.042418 Stack<14>[ 22.736392] [IGT] kms_addfb_basic: executing
11585 11:19:07.042501 trace:
11586 11:19:07.045485 #0 ../lib/igt_core.c:1963 __igt_fail_assert()
11587 11:19:07.049154 #1 [<unknown>+0xd59147e0]
11588 11:19:07.052175 #2 [<unknown>+0xd5916278]
11589 11:19:07.052258 #3 [<unknown>+0xd591167c]
11590 11:19:07.055354 #4 [__libc_start_main+0xe8]
11591 11:19:07.062221 <14>[ 22.757339] [IGT] kms_addfb_basic: exiting, ret=77
11592 11:19:07.065518 #5 [<unknown>+0xd59116b4]
11593 11:19:07.065613 #6 [<unknown>+0xd59116b4]
11594 11:19:07.075363 Subtest addfb25-bad-mo<8>[ 22.768848] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip>
11595 11:19:07.075626 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-mismatch-legacy RESULT=skip
11597 11:19:07.078548 difier failed.
11598 11:19:07.078624 **** DEBUG ****
11599 11:19:07.088467 (kms_addfb_basic:431) ioctl_wrappers-DEBUG: Test requirement passed: igt_has_fb_modifiers(fd)
11600 11:19:07.098258 (kms_addfb_basic:431) CRITICAL: Test assertion failure function addfb25_tests, f<14>[ 22.796327] [IGT] kms_addfb_basic: executing
11601 11:19:07.101956 ile ../tests/kms_addfb_basic.c:662:
11602 11:19:07.121277 (kms_addfb_basic:431) CRITICAL: Failed assertion: igt_ioctl((fd), ((((2U|1U) << (((0+8)+8)+14)) | ((('d')) << (0+8)) | (((0xB8)) << 0) | ((<14>[ 22.816071] [IGT] kms_addfb_basic: exiting, ret=77
11603 11:19:07.124950 ((sizeof(struct drm_mode_fb_cmd2)))) << ((0+8)+8)))), (&f)) == -1
11604 11:19:07.134638 (kms_addfb_ba<8>[ 22.827485] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip>
11605 11:19:07.134901 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-x-tiled-legacy RESULT=skip
11607 11:19:07.138076 sic:431) CRITICAL: error: 0 != -1
11608 11:19:07.141139 (kms_addfb_basic:431) igt_core-INFO: Stack trace:
11609 11:19:07.151177 (kms_addfb_basic:431) igt_core-INFO: #0 ../lib/igt_core.c:1963 __igt_fail_assert()
11610 11:19:07.157912 (kms_addfb_basic:431) igt_core-INFO: #1 [<unknown><14>[ 22.854713] [IGT] kms_addfb_basic: executing
11611 11:19:07.161044 +0xd59147e0]
11612 11:19:07.164446 (kms_addfb_basic:431) igt_core-INFO: #2 [<unknown>+0xd5916278]
11613 11:19:07.171183 (kms_addfb_basic:431) igt_core-INFO: #3 [<unknown>+0xd591167c]
11614 11:19:07.180744 (kms_addfb_basic:431) igt_core<14>[ 22.875444] [IGT] kms_addfb_basic: exiting, ret=77
11615 11:19:07.183918 -INFO: #4 [__libc_start_main+0xe8]
11616 11:19:07.194006 (kms_addfb_basic:431) igt_core-INFO: #5 <8>[ 22.886939] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip>
11617 11:19:07.194273 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-framebuffer-vs-set-tiling RESULT=skip
11619 11:19:07.197220 [<unknown>+0xd59116b4]
11620 11:19:07.204082 (kms_addfb_basic:431) igt_core-INFO: #6 [<unknown>+0xd59116b4]
11621 11:19:07.204160 **** END ****
11622 11:19:07.210623 [1mSubtest addfb25-bad-modifier: FAIL (0.009s)[0m
11623 11:19:07.220367 Test requirement not met in function igt_require_i915, file ../l<14>[ 22.914851] [IGT] kms_addfb_basic: executing
11624 11:19:07.220447 ib/drmtest.c:721:
11625 11:19:07.223569 Test requirement: is_i915_device(fd)
11626 11:19:07.230597 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11627 11:19:07.240194 Test requirement: is_i915_device(fd)<14>[ 22.935703] [IGT] kms_addfb_basic: exiting, ret=77
11628 11:19:07.240274
11629 11:19:07.243606 No KMS driver or no outputs, pipes: 8, outputs: 0
11630 11:19:07.253386 IGT-Version: 1.27.1-g766edf<8>[ 22.947294] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip>
11631 11:19:07.253638 Received signal: <TESTCASE> TEST_CASE_ID=basic-x-tiled-legacy RESULT=skip
11633 11:19:07.256992 9 (aarch64) (Linux: 6.1.31 aarch64)
11634 11:19:07.260218 Opened device: /dev/dri/card0
11635 11:19:07.266755 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11636 11:19:07.269928 Test requirement: is_i915_device(fd)
11637 11:19:07.276916 [1mSubtest addfb25<14>[ 22.973601] [IGT] kms_addfb_basic: executing
11638 11:19:07.279913 -x-tiled-mismatch-legacy: SKIP (0.000s)[0m
11639 11:19:07.286562 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11640 11:19:07.289885 Test requirement: is_i915_device(fd)
11641 11:19:07.296639 No KMS dri<14>[ 22.993579] [IGT] kms_addfb_basic: exiting, ret=77
11642 11:19:07.299932 ver or no outputs, pipes: 8, outputs: 0
11643 11:19:07.312829 IGT-Version: 1.27.1-g766edf9 (aarch64) <8>[ 23.005212] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip>
11644 11:19:07.313083 Received signal: <TESTCASE> TEST_CASE_ID=framebuffer-vs-set-tiling RESULT=skip
11646 11:19:07.316291 (Linux: 6.1.31 aarch64)
11647 11:19:07.316368 Opened device: /dev/dri/card0
11648 11:19:07.326291 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11649 11:19:07.329412 Test requirement: is_i915_device(fd)
11650 11:19:07.335811 [1mSubtest addfb25-x-tiled-legacy: SKIP (0.000<14>[ 23.032193] [IGT] kms_addfb_basic: executing
11651 11:19:07.335891 s)[0m
11652 11:19:07.345811 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11653 11:19:07.349283 Test requirement: is_i915_device(fd)
11654 11:19:07.355867 No KMS driver or no outputs, pipes: 8, outputs:<14>[ 23.053018] [IGT] kms_addfb_basic: exiting, ret=77
11655 11:19:07.355946 0
11656 11:19:07.362327 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11657 11:19:07.372319 Opened devic<8>[ 23.064739] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tile-pitch-mismatch RESULT=skip>
11658 11:19:07.372401 e: /dev/dri/card0
11659 11:19:07.372675 Received signal: <TESTCASE> TEST_CASE_ID=tile-pitch-mismatch RESULT=skip
11661 11:19:07.379077 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11662 11:19:07.382533 Test requirement: is_i915_device(fd)
11663 11:19:07.388966 [1mSubtest addfb25-framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11664 11:19:07.395621 Te<14>[ 23.090238] [IGT] kms_addfb_basic: executing
11665 11:19:07.402125 st requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11666 11:19:07.405366 Test requirement: is_i915_device(fd)
11667 11:19:07.408720 No KMS driver or no outputs, pipes: 8, outputs: 0
11668 11:19:07.415717 IGT-Ve<14>[ 23.110532] [IGT] kms_addfb_basic: exiting, ret=77
11669 11:19:07.418686 rsion: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11670 11:19:07.428658 Opened device: /dev/dr<8>[ 23.122110] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip>
11671 11:19:07.428747 i/card0
11672 11:19:07.429037 Received signal: <TESTCASE> TEST_CASE_ID=basic-y-tiled-legacy RESULT=skip
11674 11:19:07.438584 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11675 11:19:07.441621 Test requirement: is_i915_device(fd)
11676 11:19:07.451687 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:7<14>[ 23.148805] [IGT] kms_addfb_basic: executing
11677 11:19:07.451776 21:
11678 11:19:07.454895 Test requirement: is_i915_device(fd)
11679 11:19:07.461486 [1mSubtest basic-x-tiled-legacy: SKIP (0.000s)[0m
11680 11:19:07.465065 No KMS driver or no outputs, pipes: 8, outputs: 0
11681 11:19:07.471776 IGT-Version: 1.27.1-g766edf9 <14>[ 23.168595] [IGT] kms_addfb_basic: exiting, ret=77
11682 11:19:07.474655 (aarch64) (Linux: 6.1.31 aarch64)
11683 11:19:07.478061 Opened device: /dev/dri/card0
11684 11:19:07.484795 Test requireme<8>[ 23.180253] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=size-max RESULT=skip>
11685 11:19:07.485063 Received signal: <TESTCASE> TEST_CASE_ID=size-max RESULT=skip
11687 11:19:07.491488 nt not met in function igt_require_i915, file ../lib/drmtest.c:721:
11688 11:19:07.494761 Test requirement: is_i915_device(fd)
11689 11:19:07.501276 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11690 11:19:07.511129 Test requirement: is_i915_device(f<14>[ 23.205905] [IGT] kms_addfb_basic: executing
11691 11:19:07.511211 d)
11692 11:19:07.514314 [1mSubtest framebuffer-vs-set-tiling: SKIP (0.000s)[0m
11693 11:19:07.520993 No KMS driver or no outputs, pipes: 8, outputs: 0
11694 11:19:07.524272 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11695 11:19:07.530943 <14>[ 23.226499] [IGT] kms_addfb_basic: exiting, ret=77
11696 11:19:07.531022
11697 11:19:07.534359 Opened device: /dev/dri/card0
11698 11:19:07.544170 Test requirement not met in function igt_require<8>[ 23.238123] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-wide RESULT=skip>
11699 11:19:07.544424 Received signal: <TESTCASE> TEST_CASE_ID=too-wide RESULT=skip
11701 11:19:07.547691 _i915, file ../lib/drmtest.c:721:
11702 11:19:07.550534 Test requirement: is_i915_device(fd)
11703 11:19:07.557567 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11704 11:19:07.561026 Test requirement: is_i915_device(fd)
11705 11:19:07.567115 [1mSubtest ti<14>[ 23.263060] [IGT] kms_addfb_basic: executing
11706 11:19:07.570609 le-pitch-mismatch: SKIP (0.000s)[0m
11707 11:19:07.574027 No KMS driver or no outputs, pipes: 8, outputs: 0
11708 11:19:07.580743 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11709 11:19:07.587151 Opened device: /dev/dri<14>[ 23.283024] [IGT] kms_addfb_basic: exiting, ret=77
11710 11:19:07.587242 /card0
11711 11:19:07.600506 Test requirement not met in function igt_require_i915, file ../lib/drmte<8>[ 23.294637] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=too-high RESULT=skip>
11712 11:19:07.600590 st.c:721:
11713 11:19:07.600789 Received signal: <TESTCASE> TEST_CASE_ID=too-high RESULT=skip
11715 11:19:07.603775 Test requirement: is_i915_device(fd)
11716 11:19:07.613560 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11717 11:19:07.616805 Test requirement: is_i915_device(fd)
11718 11:19:07.623470 [1mSubtest basic-y-tiled-legacy: SKIP<14>[ 23.319589] [IGT] kms_addfb_basic: executing
11719 11:19:07.623553 (0.000s)[0m
11720 11:19:07.630107 No KMS driver or no outputs, pipes: 8, outputs: 0
11721 11:19:07.633703 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11722 11:19:07.636569 Opened device: /dev/dri/card0
11723 11:19:07.643249 Test requiremen<14>[ 23.339947] [IGT] kms_addfb_basic: exiting, ret=77
11724 11:19:07.650121 t not met in function igt_require_i915, file ../lib/drmtest.c:721:
11725 11:19:07.656641 Test require<8>[ 23.351637] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small RESULT=skip>
11726 11:19:07.656895 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small RESULT=skip
11728 11:19:07.660235 ment: is_i915_device(fd)
11729 11:19:07.666604 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11730 11:19:07.669592 Test requirement: is_i915_device(fd)
11731 11:19:07.676649 No KMS driver or no outputs, pipes: 8, outputs: 0
11732 11:19:07.680109 [1mSubtes<14>[ 23.376795] [IGT] kms_addfb_basic: executing
11733 11:19:07.683254 t size-max: SKIP (0.000s)[0m
11734 11:19:07.689808 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11735 11:19:07.692882 Opened device: /dev/dri/card0
11736 11:19:07.699633 Test requirement not met in function igt_require_i<14>[ 23.397302] [IGT] kms_addfb_basic: exiting, ret=77
11737 11:19:07.702926 915, file ../lib/drmtest.c:721:
11738 11:19:07.706046 Test requirement: is_i915_device(fd)
11739 11:19:07.715896 Test requ<8>[ 23.409014] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=small-bo RESULT=skip>
11740 11:19:07.716148 Received signal: <TESTCASE> TEST_CASE_ID=small-bo RESULT=skip
11742 11:19:07.722604 irement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11743 11:19:07.725939 Test requirement: is_i915_device(fd)
11744 11:19:07.729011 No KMS driver or no outputs, pipes: 8, outputs: 0
11745 11:19:07.732213 [1mSubtest too-wide: SKIP (0.000s)[0m
11746 11:19:07.736059 IGT-<14>[ 23.433321] [IGT] kms_addfb_basic: executing
11747 11:19:07.742368 Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11748 11:19:07.745601 Opened device: /dev/dri/card0
11749 11:19:07.752548 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11750 11:19:07.758849 Te<14>[ 23.453857] [IGT] kms_addfb_basic: exiting, ret=77
11751 11:19:07.762214 st requirement: is_i915_device(fd)
11752 11:19:07.772325 Test requirement not met in function igt_req<8>[ 23.465567] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip>
11753 11:19:07.772642 Received signal: <TESTCASE> TEST_CASE_ID=bo-too-small-due-to-tiling RESULT=skip
11755 11:19:07.775457 uire_i915, file ../lib/drmtest.c:721:
11756 11:19:07.778661 Test requirement: is_i915_device(fd)
11757 11:19:07.785107 No KMS driver or no outputs, pipes: 8, outputs: 0
11758 11:19:07.788526 [1mSubtest too-high: SKIP (0.000s)[0m
11759 11:19:07.795247 IGT-Version: 1.27.1-g766edf9 (aarch64) <14>[ 23.491852] [IGT] kms_addfb_basic: executing
11760 11:19:07.798286 (Linux: 6.1.31 aarch64)
11761 11:19:07.801831 Opened device: /dev/dri/card0
11762 11:19:07.808221 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11763 11:19:07.811612 Test requirement: is_i915_device(fd)
11764 11:19:07.815075 <14>[ 23.512203] [IGT] kms_addfb_basic: exiting, ret=77
11765 11:19:07.815147
11766 11:19:07.831674 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:72<8>[ 23.523680] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip>
11767 11:19:07.831761 1:
11768 11:19:07.831999 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-legacy RESULT=skip
11770 11:19:07.834881 Test requirement: is_i915_device(fd)
11771 11:19:07.838163 No KMS driver or no outputs, pipes: 8, outputs: 0
11772 11:19:07.845024 [1mSubtest bo-too-small: SKIP (0.000s)[0m
11773 11:19:07.848049 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11774 11:19:07.854497 Opened device: /dev/dr<14>[ 23.550637] [IGT] kms_addfb_basic: executing
11775 11:19:07.854581 i/card0
11776 11:19:07.864220 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11777 11:19:07.867651 Test requirement: is_i915_device(fd)
11778 11:19:07.874606 Test requirement not met in function igt_requi<14>[ 23.571367] [IGT] kms_addfb_basic: exiting, ret=77
11779 11:19:07.877644 re_i915, file ../lib/drmtest.c:721:
11780 11:19:07.880852 Test requirement: is_i915_device(fd)
11781 11:19:07.890937 No KM<8>[ 23.583058] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip>
11782 11:19:07.891192 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-yf-tiled-legacy RESULT=skip
11784 11:19:07.893917 S driver or no outputs, pipes: 8, outputs: 0
11785 11:19:07.897176 [1mSubtest small-bo: SKIP (0.000s)[0m
11786 11:19:07.904278 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11787 11:19:07.907445 Opened device: /dev/dri/card0
11788 11:19:07.913785 Test requirement not met i<14>[ 23.609326] [IGT] kms_addfb_basic: executing
11789 11:19:07.917386 n function igt_require_i915, file ../lib/drmtest.c:721:
11790 11:19:07.920685 Test requirement: is_i915_device(fd)
11791 11:19:07.934048 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:<14>[ 23.629532] [IGT] kms_addfb_basic: exiting, ret=77
11792 11:19:07.934131
11793 11:19:07.937231 Test requirement: is_i915_device(fd)
11794 11:19:07.950337 No KMS driver or no outputs, pipes: 8, o<8>[ 23.641159] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip>
11795 11:19:07.950420 utputs: 0
11796 11:19:07.950655 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-y-tiled-small-legacy RESULT=skip
11798 11:19:07.953505 [1mSubtest bo-too-small-due-to-tiling: SKIP (0.000s)[0m
11799 11:19:07.960079 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11800 11:19:07.963422 Opened device: /dev/dri/card0
11801 11:19:07.970129 Test requirement not met in function igt_re<14>[ 23.667386] [IGT] kms_addfb_basic: executing
11802 11:19:07.976607 quire_i915, file ../lib/drmtest.c:721:
11803 11:19:07.979760 Test requirement: is_i915_device(fd)
11804 11:19:07.986574 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11805 11:19:07.993214 Test requiremen<14>[ 23.687763] [IGT] kms_addfb_basic: exiting, ret=77
11806 11:19:07.993295 t: is_i915_device(fd)
11807 11:19:07.999635 No KMS driver or no outputs, pipes: 8, outputs: 0
11808 11:19:08.005968 [1mSu<8>[ 23.699465] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=addfb25-4-tiled RESULT=skip>
11809 11:19:08.006225 Received signal: <TESTCASE> TEST_CASE_ID=addfb25-4-tiled RESULT=skip
11811 11:19:08.013177 btest addfb25-y-tiled-legacy: SK<8>[ 23.709503] <LAVA_SIGNAL_TESTSET STOP>
11812 11:19:08.013425 Received signal: <TESTSET> STOP
11813 11:19:08.013500 Closing test_set kms_addfb_basic
11814 11:19:08.015896 IP (0.000s)[0m
11815 11:19:08.019366 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11816 11:19:08.022815 Opened device: /dev/dri/card0
11817 11:19:08.029315 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11818 11:19:08.032686 Test requirement: is_i915_device(fd)
11819 11:19:08.039279 Test requirement not me<8>[ 23.735805] <LAVA_SIGNAL_TESTSET START kms_atomic>
11820 11:19:08.039520 Received signal: <TESTSET> START kms_atomic
11821 11:19:08.039592 Starting test_set kms_atomic
11822 11:19:08.045797 t in function igt_require_i915, file ../lib/drmtest.c:721:
11823 11:19:08.048924 Test requirement: is_i915_device(fd)
11824 11:19:08.052310 No KMS driver or no outputs, pipes: 8, outputs: 0
11825 11:19:08.058839 [1mSubtest addfb25-yf-tiled-legacy: SKIP (0.000s)[0m
11826 11:19:08.062115 IGT<14>[ 23.759909] [IGT] kms_atomic: executing
11827 11:19:08.068633 -Version: 1.27.1<14>[ 23.764756] [IGT] kms_atomic: exiting, ret=77
11828 11:19:08.072254 -g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11829 11:19:08.075296 Opened device: /dev/dri/card0
11830 11:19:08.081844 Test<8>[ 23.776277] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-overlay-legacy RESULT=skip>
11831 11:19:08.082088 Received signal: <TESTCASE> TEST_CASE_ID=plane-overlay-legacy RESULT=skip
11833 11:19:08.088360 requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11834 11:19:08.092115 Test requirement: is_i915_device(fd)
11835 11:19:08.102116 Test requirement not met in function igt_require_i915, file ../lib/drmtest.c:721:
11836 11:19:08.104858 Test req<14>[ 23.802005] [IGT] kms_atomic: executing
11837 11:19:08.111506 uirement: is_i91<14>[ 23.807732] [IGT] kms_atomic: exiting, ret=77
11838 11:19:08.111578 5_device(fd)
11839 11:19:08.118236 No KMS driver or no outputs, pipes: 8, outputs: 0
11840 11:19:08.124658 [1mSubtest add<8>[ 23.819037] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-legacy RESULT=skip>
11841 11:19:08.124900 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-legacy RESULT=skip
11843 11:19:08.131325 fb25-y-tiled-small-legacy: SKIP (0.000s)[0m
11844 11:19:08.134896 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11845 11:19:08.137973 Opened device: /dev/dri/card0
11846 11:19:08.148146 Test requirement not met in function igt_require_i915, file ../lib/<14>[ 23.845125] [IGT] kms_atomic: executing
11847 11:19:08.151158 drmtest.c:721:
11848 11:19:08.154436 <14>[ 23.850771] [IGT] kms_atomic: exiting, ret=77
11849 11:19:08.157648 Test requirement: is_i915_device(fd)
11850 11:19:08.167977 Test requirement not met i<8>[ 23.861816] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip>
11851 11:19:08.168235 Received signal: <TESTCASE> TEST_CASE_ID=plane-primary-overlay-mutable-zpos RESULT=skip
11853 11:19:08.174723 n function igt_require_i915, file ../lib/drmtest.c:721:
11854 11:19:08.177734 Test requirement: is_i915_device(fd)
11855 11:19:08.181042 No KMS driver or no outputs, pipes: 8, outputs: 0
11856 11:19:08.187816 [1mSubtest addfb25-4-tiled: SKIP (0.000s)[0m
11857 11:19:08.193978 IGT-Version: 1.27.1-g766edf9 (<14>[ 23.889510] [IGT] kms_atomic: executing
11858 11:19:08.197233 aarch64) (Linux:<14>[ 23.895341] [IGT] kms_atomic: exiting, ret=77
11859 11:19:08.200648 6.1.31 aarch64)
11860 11:19:08.204287 Opened device: /dev/dri/card0
11861 11:19:08.211009 No KMS driver o<8>[ 23.905987] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-immutable-zpos RESULT=skip>
11862 11:19:08.211262 Received signal: <TESTCASE> TEST_CASE_ID=plane-immutable-zpos RESULT=skip
11864 11:19:08.214172 r no outputs, pipes: 8, outputs: 0
11865 11:19:08.220977 [1mSubtest plane-overlay-legacy: SKIP (0.000s)[0m
11866 11:19:08.223931 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11867 11:19:08.227351 Opened device: /dev/dri/card0
11868 11:19:08.233964 No KMS driver or no outp<14>[ 23.931082] [IGT] kms_atomic: executing
11869 11:19:08.240481 uts, pipes: 8, o<14>[ 23.936647] [IGT] kms_atomic: exiting, ret=77
11870 11:19:08.240554 utputs: 0
11871 11:19:08.246878 [1mSubtest plane-primary-legacy: SKIP (0.000s)[0m
11872 11:19:08.253551 IGT-Version: 1.2<8>[ 23.948055] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=test-only RESULT=skip>
11873 11:19:08.253791 Received signal: <TESTCASE> TEST_CASE_ID=test-only RESULT=skip
11875 11:19:08.256882 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11876 11:19:08.260257 Opened device: /dev/dri/card0
11877 11:19:08.267226 No KMS driver or no outputs, pipes: 8, outputs: 0
11878 11:19:08.270157 [1mSubtest plane-primary-overlay-mutable-zpos: SKIP (0.000s)[0m
11879 11:19:08.277214 IGT-Version<14>[ 23.973573] [IGT] kms_atomic: executing
11880 11:19:08.283339 : 1.27.1-g766edf<14>[ 23.978689] [IGT] kms_atomic: exiting, ret=77
11881 11:19:08.286515 9 (aarch64) (Linux: 6.1.31 aarch64)
11882 11:19:08.290108 Opened device: /dev/dri/card0
11883 11:19:08.296408 No KMS drive<8>[ 23.990138] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-cursor-legacy RESULT=skip>
11884 11:19:08.296665 Received signal: <TESTCASE> TEST_CASE_ID=plane-cursor-legacy RESULT=skip
11886 11:19:08.299728 r or no outputs, pipes: 8, outputs: 0
11887 11:19:08.306797 [1mSubtest plane-immutable-zpos: SKIP (0.000s)[0m
11888 11:19:08.309854 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11889 11:19:08.313076 Opened device: /dev/dri/card0
11890 11:19:08.319823 No KMS driver or no o<14>[ 24.015836] [IGT] kms_atomic: executing
11891 11:19:08.326190 utputs, pipes: 8<14>[ 24.021620] [IGT] kms_atomic: exiting, ret=77
11892 11:19:08.326272 , outputs: 0
11893 11:19:08.329856 [1mSubtest test-only: SKIP (0.000s)[0m
11894 11:19:08.339248 IGT-Version: 1.27.1-g766<8>[ 24.032760] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params RESULT=skip>
11895 11:19:08.339501 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params RESULT=skip
11897 11:19:08.342818 edf9 (aarch64) (Linux: 6.1.31 aarch64)
11898 11:19:08.345928 Opened device: /dev/dri/card0
11899 11:19:08.349453 No KMS driver or no outputs, pipes: 8, outputs: 0
11900 11:19:08.356023 [1mSubtest plane-cursor-legacy: SKIP (0.000s)[0m
11901 11:19:08.362568 IGT-Version: 1.27.1-g766edf9 (aarc<14>[ 24.058687] [IGT] kms_atomic: executing
11902 11:19:08.368840 h64) (Linux: 6.1<14>[ 24.064544] [IGT] kms_atomic: exiting, ret=77
11903 11:19:08.368921 .31 aarch64)
11904 11:19:08.372382 Opened device: /dev/dri/card0
11905 11:19:08.382729 No KMS driver or no<8>[ 24.075658] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=plane-invalid-params-fence RESULT=skip>
11906 11:19:08.382983 Received signal: <TESTCASE> TEST_CASE_ID=plane-invalid-params-fence RESULT=skip
11908 11:19:08.385290 outputs, pipes: 8, outputs: 0
11909 11:19:08.388546 [1mSubtest plane-invalid-params: SKIP (0.000s)[0m
11910 11:19:08.395673 IGT-Version: 1.27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11911 11:19:08.398508 Opened device: /dev/dri/card0
11912 11:19:08.405332 No KMS driver or no outputs,<14>[ 24.100906] [IGT] kms_atomic: executing
11913 11:19:08.411790 pipes: 8, outpu<14>[ 24.106695] [IGT] kms_atomic: exiting, ret=77
11914 11:19:08.411869 ts: 0
11915 11:19:08.415092 [1mSubtest plane-invalid-params-fence: SKIP (0.000s)[0m
11916 11:19:08.425441 IGT-Version: 1<8>[ 24.117881] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params RESULT=skip>
11917 11:19:08.425684 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params RESULT=skip
11919 11:19:08.428129 .27.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11920 11:19:08.431659 Opened device: /dev/dri/card0
11921 11:19:08.438208 No KMS driver or no outputs, pipes: 8, outputs: 0
11922 11:19:08.441227 [1mSubtest crtc-invalid-params: SKIP (0.000s)[0m
11923 11:19:08.448170 <14>[ 24.144727] [IGT] kms_atomic: executing
11924 11:19:08.454408 IGT-Version: 1.2<14>[ 24.149533] [IGT] kms_atomic: exiting, ret=77
11925 11:19:08.457934 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11926 11:19:08.460918 Opened device: /dev/dri/card0
11927 11:19:08.467695 N<8>[ 24.161270] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip>
11928 11:19:08.467937 Received signal: <TESTCASE> TEST_CASE_ID=crtc-invalid-params-fence RESULT=skip
11930 11:19:08.474151 o KMS driver or no outputs, pipes: 8, outputs: 0
11931 11:19:08.477568 [1mSubtest crtc-invalid-params-fence: SKIP (0.000s)[0m
11932 11:19:08.490770 <14>[ 24.187478] [IGT] kms_atomic: executing
11933 11:19:08.497519 IGT-Version: 1.2<14>[ 24.192201] [IGT] kms_atomic: exiting, ret=77
11934 11:19:08.500536 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11935 11:19:08.503931 Opened device: /dev/dri/card0
11936 11:19:08.510877 N<8>[ 24.203522] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic-invalid-params RESULT=skip>
11937 11:19:08.511119 Received signal: <TESTCASE> TEST_CASE_ID=atomic-invalid-params RESULT=skip
11939 11:19:08.513852 o KMS driver or no outputs, pipes: 8, outputs: 0
11940 11:19:08.520539 [1mSubtest atomic-invalid-params: SKIP (0.000s)[0m
11941 11:19:08.532910 <14>[ 24.229661] [IGT] kms_atomic: executing
11942 11:19:08.539656 IGT-Version: 1.2<14>[ 24.234401] [IGT] kms_atomic: exiting, ret=77
11943 11:19:08.542753 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11944 11:19:08.546238 Opened device: /dev/dri/card0
11945 11:19:08.552898 N<8>[ 24.245786] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=atomic_plane_damage RESULT=skip>
11946 11:19:08.553148 Received signal: <TESTCASE> TEST_CASE_ID=atomic_plane_damage RESULT=skip
11948 11:19:08.559287 o KMS driver or no outputs, pipe<8>[ 24.256330] <LAVA_SIGNAL_TESTSET STOP>
11949 11:19:08.559530 Received signal: <TESTSET> STOP
11950 11:19:08.559597 Closing test_set kms_atomic
11951 11:19:08.562682 s: 8, outputs: 0
11952 11:19:08.565915 [1mSubtest atomic_plane_damage: SKIP (0.000s)[0m
11953 11:19:08.585640 <8>[ 24.282581] <LAVA_SIGNAL_TESTSET START kms_flip_event_leak>
11954 11:19:08.585889 Received signal: <TESTSET> START kms_flip_event_leak
11955 11:19:08.585965 Starting test_set kms_flip_event_leak
11956 11:19:08.609326 <14>[ 24.306076] [IGT] kms_flip_event_leak: executing
11957 11:19:08.616076 IGT-Version: 1.2<14>[ 24.311937] [IGT] kms_flip_event_leak: exiting, ret=77
11958 11:19:08.619170 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
11959 11:19:08.622548 Opened device: /dev/dri/card0
11960 11:19:08.629282 N<8>[ 24.324298] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
11961 11:19:08.629548 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
11963 11:19:08.635809 o KMS driver or no outputs, pipe<8>[ 24.333282] <LAVA_SIGNAL_TESTSET STOP>
11964 11:19:08.636076 Received signal: <TESTSET> STOP
11965 11:19:08.636151 Closing test_set kms_flip_event_leak
11966 11:19:08.639066 s: 8, outputs: 0
11967 11:19:08.642353 [1mSubtest basic: SKIP (0.000s)[0m
11968 11:19:08.661891 <8>[ 24.358746] <LAVA_SIGNAL_TESTSET START kms_prop_blob>
11969 11:19:08.662138 Received signal: <TESTSET> START kms_prop_blob
11970 11:19:08.662219 Starting test_set kms_prop_blob
11971 11:19:08.685088 <14>[ 24.382009] [IGT] kms_prop_blob: executing
11972 11:19:08.692130 IGT-Version: 1.2<14>[ 24.386857] [IGT] kms_prop_blob: starting subtest basic
11973 11:19:08.698541 7.1-g766edf9 (aa<14>[ 24.393963] [IGT] kms_prop_blob: exiting, ret=0
11974 11:19:08.701843 rch64) (Linux: 6.1.31 aarch64)
11975 11:19:08.705291 Opened device: /dev/dri/card0
11976 11:19:08.711710 Starting subtest:<8>[ 24.405598] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=pass>
11977 11:19:08.711793 basic
11978 11:19:08.712027 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=pass
11980 11:19:08.715037 [1mSubtest basic: SUCCESS (0.000s)[0m
11981 11:19:08.734227 <14>[ 24.430776] [IGT] kms_prop_blob: executing
11982 11:19:08.740693 IGT-Version: 1.2<14>[ 24.435717] [IGT] kms_prop_blob: starting subtest blob-prop-core
11983 11:19:08.747253 7.1-g766edf9 (aa<14>[ 24.443368] [IGT] kms_prop_blob: exiting, ret=0
11984 11:19:08.751028 rch64) (Linux: 6.1.31 aarch64)
11985 11:19:08.754012 Opened device: /dev/dri/card0
11986 11:19:08.760422 Starting subtest:<8>[ 24.455829] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-core RESULT=pass>
11987 11:19:08.760675 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-core RESULT=pass
11989 11:19:08.763866 blob-prop-core
11990 11:19:08.767271 [1mSubtest blob-prop-core: SUCCESS (0.000s)[0m
11991 11:19:08.784843 <14>[ 24.481219] [IGT] kms_prop_blob: executing
11992 11:19:08.790933 IGT-Version: 1.2<14>[ 24.486140] [IGT] kms_prop_blob: starting subtest blob-prop-validate
11993 11:19:08.797536 7.1-g766edf9 (aa<14>[ 24.494228] [IGT] kms_prop_blob: exiting, ret=0
11994 11:19:08.800947 rch64) (Linux: 6.1.31 aarch64)
11995 11:19:08.804288 Opened device: /dev/dri/card0
11996 11:19:08.814441 Starting subtest:<8>[ 24.506327] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-validate RESULT=pass>
11997 11:19:08.814523 blob-prop-validate
11998 11:19:08.814757 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-validate RESULT=pass
12000 11:19:08.820646 [1mSubtest blob-prop-validate: SUCCESS (0.000s)[0m
12001 11:19:08.835179 <14>[ 24.531935] [IGT] kms_prop_blob: executing
12002 11:19:08.841954 IGT-Version: 1.2<14>[ 24.536857] [IGT] kms_prop_blob: starting subtest blob-prop-lifetime
12003 11:19:08.848465 7.1-g766edf9 (aa<14>[ 24.544941] [IGT] kms_prop_blob: exiting, ret=0
12004 11:19:08.851580 rch64) (Linux: 6.1.31 aarch64)
12005 11:19:08.854668 Opened device: /dev/dri/card0
12006 11:19:08.864947 Starting subtest:<8>[ 24.556814] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-prop-lifetime RESULT=pass>
12007 11:19:08.865030 blob-prop-lifetime
12008 11:19:08.865264 Received signal: <TESTCASE> TEST_CASE_ID=blob-prop-lifetime RESULT=pass
12010 11:19:08.870997 [1mSubtest blob-prop-lifetime: SUCCESS (0.000s)[0m
12011 11:19:08.886012 <14>[ 24.582495] [IGT] kms_prop_blob: executing
12012 11:19:08.892467 IGT-Version: 1.2<14>[ 24.587510] [IGT] kms_prop_blob: starting subtest blob-multiple
12013 11:19:08.899168 7.1-g766edf9 (aa<14>[ 24.595160] [IGT] kms_prop_blob: exiting, ret=0
12014 11:19:08.902164 rch64) (Linux: 6.1.31 aarch64)
12015 11:19:08.905633 Opened device: /dev/dri/card0
12016 11:19:08.912061 Starting subtest:<8>[ 24.606837] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blob-multiple RESULT=pass>
12017 11:19:08.912317 Received signal: <TESTCASE> TEST_CASE_ID=blob-multiple RESULT=pass
12019 11:19:08.915713 blob-multiple
12020 11:19:08.918568 [1mSubtest blob-multiple: SUCCESS (0.000s)[0m
12021 11:19:08.935726 <14>[ 24.632337] [IGT] kms_prop_blob: executing
12022 11:19:08.942125 IGT-Version: 1.2<14>[ 24.637177] [IGT] kms_prop_blob: starting subtest invalid-get-prop-any
12023 11:19:08.949132 7.1-g766edf9 (aa<14>[ 24.645336] [IGT] kms_prop_blob: exiting, ret=0
12024 11:19:08.952057 rch64) (Linux: 6.1.31 aarch64)
12025 11:19:08.955728 Opened device: /dev/dri/card0
12026 11:19:08.965489 Starting subtest:<8>[ 24.657019] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop-any RESULT=pass>
12027 11:19:08.965574 invalid-get-prop-any
12028 11:19:08.965812 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop-any RESULT=pass
12030 11:19:08.971885 [1mSubtest invalid-get-prop-any: SUCCESS (0.000s)[0m
12031 11:19:08.986513 <14>[ 24.683270] [IGT] kms_prop_blob: executing
12032 11:19:08.993223 IGT-Version: 1.2<14>[ 24.688114] [IGT] kms_prop_blob: starting subtest invalid-get-prop
12033 11:19:08.999997 7.1-g766edf9 (aa<14>[ 24.695962] [IGT] kms_prop_blob: exiting, ret=0
12034 11:19:09.002885 rch64) (Linux: 6.1.31 aarch64)
12035 11:19:09.006372 Opened device: /dev/dri/card0
12036 11:19:09.012655 S<8>[ 24.707543] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-get-prop RESULT=pass>
12037 11:19:09.012943 Received signal: <TESTCASE> TEST_CASE_ID=invalid-get-prop RESULT=pass
12039 11:19:09.015947 tarting subtest: invalid-get-prop
12040 11:19:09.019557 [1mSubtest invalid-get-prop: SUCCESS (0.000s)[0m
12041 11:19:09.035687 <14>[ 24.732170] [IGT] kms_prop_blob: executing
12042 11:19:09.041770 IGT-Version: 1.2<14>[ 24.737004] [IGT] kms_prop_blob: starting subtest invalid-set-prop-any
12043 11:19:09.048654 7.1-g766edf9 (aa<14>[ 24.745176] [IGT] kms_prop_blob: exiting, ret=0
12044 11:19:09.051625 rch64) (Linux: 6.1.31 aarch64)
12045 11:19:09.055077 Opened device: /dev/dri/card0
12046 11:19:09.062038 S<8>[ 24.756793] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop-any RESULT=pass>
12047 11:19:09.062290 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop-any RESULT=pass
12049 11:19:09.065026 tarting subtest: invalid-set-prop-any
12050 11:19:09.071566 [1mSubtest invalid-set-prop-any: SUCCESS (0.000s)[0m
12051 11:19:09.085408 <14>[ 24.782385] [IGT] kms_prop_blob: executing
12052 11:19:09.092017 IGT-Version: 1.2<14>[ 24.787289] [IGT] kms_prop_blob: starting subtest invalid-set-prop
12053 11:19:09.098608 7.1-g766edf9 (aa<14>[ 24.795281] [IGT] kms_prop_blob: exiting, ret=0
12054 11:19:09.102129 rch64) (Linux: 6.1.31 aarch64)
12055 11:19:09.105211 Opened device: /dev/dri/card0
12056 11:19:09.112109 Received signal: <TESTCASE> TEST_CASE_ID=invalid-set-prop RESULT=pass
12058 11:19:09.115340 Starting subtest:<8>[ 24.806807] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-set-prop RESULT=pass>
12059 11:19:09.115418 invalid-set-prop
12060 11:19:09.121873 [1mSubtest i<8>[ 24.816886] <LAVA_SIGNAL_TESTSET STOP>
12061 11:19:09.122121 Received signal: <TESTSET> STOP
12062 11:19:09.122194 Closing test_set kms_prop_blob
12063 11:19:09.124929 nvalid-set-prop: SUCCESS (0.000s)[0m
12064 11:19:09.146297 <8>[ 24.843326] <LAVA_SIGNAL_TESTSET START kms_setmode>
12065 11:19:09.146547 Received signal: <TESTSET> START kms_setmode
12066 11:19:09.146630 Starting test_set kms_setmode
12067 11:19:09.169388 <14>[ 24.866308] [IGT] kms_setmode: executing
12068 11:19:09.176364 IGT-Version: 1.2<14>[ 24.871346] [IGT] kms_setmode: starting subtest basic
12069 11:19:09.182857 7.1-g766edf9 (aa<14>[ 24.877998] [IGT] kms_setmode: exiting, ret=77
12070 11:19:09.186085 rch64) (Linux: 6.1.31 aarch64)
12071 11:19:09.186172 Opened device: /dev/dri/card0
12072 11:19:09.196196 Starting subtest:<8>[ 24.889909] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic RESULT=skip>
12073 11:19:09.196287 basic
12074 11:19:09.196525 Received signal: <TESTCASE> TEST_CASE_ID=basic RESULT=skip
12076 11:19:09.199383 No dynamic tests executed.
12077 11:19:09.202674 [1mSubtest basic: SKIP (0.000s)[0m
12078 11:19:09.217826 <14>[ 24.914699] [IGT] kms_setmode: executing
12079 11:19:09.224728 IGT-Version: 1.2<14>[ 24.919622] [IGT] kms_setmode: starting subtest basic-clone-single-crtc
12080 11:19:09.231066 7.1-g766edf9 (aa<14>[ 24.927824] [IGT] kms_setmode: exiting, ret=77
12081 11:19:09.234119 rch64) (Linux: 6.1.31 aarch64)
12082 11:19:09.237865 Opened device: /dev/dri/card0
12083 11:19:09.247575 Starting subtest:<8>[ 24.939451] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=basic-clone-single-crtc RESULT=skip>
12084 11:19:09.247830 Received signal: <TESTCASE> TEST_CASE_ID=basic-clone-single-crtc RESULT=skip
12086 11:19:09.251160 basic-clone-single-crtc
12087 11:19:09.251242 No dynamic tests executed.
12088 11:19:09.257068 [1mSubtest basic-clone-single-crtc: SKIP (0.000s)[0m
12089 11:19:09.269479 <14>[ 24.966368] [IGT] kms_setmode: executing
12090 11:19:09.276153 IGT-Version: 1.2<14>[ 24.971304] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc
12091 11:19:09.282822 7.1-g766edf9 (aa<14>[ 24.979757] [IGT] kms_setmode: exiting, ret=77
12092 11:19:09.286141 rch64) (Linux: 6.1.31 aarch64)
12093 11:19:09.289540 Opened device: /dev/dri/card0
12094 11:19:09.298978 Starting subtest:<8>[ 24.991799] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip>
12095 11:19:09.299233 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc RESULT=skip
12097 11:19:09.302214 invalid-clone-single-crtc
12098 11:19:09.302294 No dynamic tests executed.
12099 11:19:09.309311 [1mSubtest invalid-clone-single-crtc: SKIP (0.000s)[0m
12100 11:19:09.321971 <14>[ 25.018696] [IGT] kms_setmode: executing
12101 11:19:09.328612 IGT-Version: 1.2<14>[ 25.023651] [IGT] kms_setmode: starting subtest invalid-clone-exclusive-crtc
12102 11:19:09.335387 7.1-g766edf9 (aa<14>[ 25.032066] [IGT] kms_setmode: exiting, ret=77
12103 11:19:09.338215 rch64) (Linux: 6.1.31 aarch64)
12104 11:19:09.341918 Opened device: /dev/dri/card0
12105 11:19:09.351369 Starting subtest:<8>[ 25.043959] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip>
12106 11:19:09.351622 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-exclusive-crtc RESULT=skip
12108 11:19:09.354739 invalid-clone-exclusive-crtc
12109 11:19:09.358502 No dynamic tests executed.
12110 11:19:09.361493 [1mSubtest invalid-clone-exclusive-crtc: SKIP (0.000s)[0m
12111 11:19:09.374023 <14>[ 25.070615] [IGT] kms_setmode: executing
12112 11:19:09.380364 IGT-Version: 1.2<14>[ 25.075581] [IGT] kms_setmode: starting subtest clone-exclusive-crtc
12113 11:19:09.387075 7.1-g766edf9 (aa<14>[ 25.083298] [IGT] kms_setmode: exiting, ret=77
12114 11:19:09.390191 rch64) (Linux: 6.1.31 aarch64)
12115 11:19:09.393675 Opened device: /dev/dri/card0
12116 11:19:09.403330 Starting subtest:<8>[ 25.095048] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=clone-exclusive-crtc RESULT=skip>
12117 11:19:09.403412 clone-exclusive-crtc
12118 11:19:09.403647 Received signal: <TESTCASE> TEST_CASE_ID=clone-exclusive-crtc RESULT=skip
12120 11:19:09.406863 No dynamic tests executed.
12121 11:19:09.409816 [1mSubtest clone-exclusive-crtc: SKIP (0.000s)[0m
12122 11:19:09.425112 <14>[ 25.121867] [IGT] kms_setmode: executing
12123 11:19:09.434845 IGT-Version: 1.2<14>[ 25.126779] [IGT] kms_setmode: starting subtest invalid-clone-single-crtc-stealing
12124 11:19:09.441447 7.1-g766edf9 (aa<14>[ 25.135869] [IGT] kms_setmode: exiting, ret=77
12125 11:19:09.441531 rch64) (Linux: 6.1.31 aarch64)
12126 11:19:09.445200 Opened device: /dev/dri/card0
12127 11:19:09.454876 Starting subtest:<8>[ 25.147850] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip>
12128 11:19:09.455151 Received signal: <TESTCASE> TEST_CASE_ID=invalid-clone-single-crtc-stealing RESULT=skip
12130 11:19:09.461490 invalid-clone-single-crtc-steal<8>[ 25.159459] <LAVA_SIGNAL_TESTSET STOP>
12131 11:19:09.461849 Received signal: <TESTSET> STOP
12132 11:19:09.461957 Closing test_set kms_setmode
12133 11:19:09.464748 ing
12134 11:19:09.464866 No dynamic tests executed.
12135 11:19:09.471567 [1mSubtest invalid-clone-single-crtc-stealing: SKIP (0.000s)[0m
12136 11:19:09.489098 <8>[ 25.186084] <LAVA_SIGNAL_TESTSET START kms_vblank>
12137 11:19:09.489462 Received signal: <TESTSET> START kms_vblank
12138 11:19:09.489606 Starting test_set kms_vblank
12139 11:19:09.512272 <14>[ 25.208974] [IGT] kms_vblank: executing
12140 11:19:09.519193 IGT-Version: 1.2<14>[ 25.214174] [IGT] kms_vblank: exiting, ret=77
12141 11:19:09.522451 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12142 11:19:09.525964 Opened device: /dev/dri/card0
12143 11:19:09.532199 N<8>[ 25.225795] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid RESULT=skip>
12144 11:19:09.532885 Received signal: <TESTCASE> TEST_CASE_ID=invalid RESULT=skip
12146 11:19:09.535347 o KMS driver or no outputs, pipes: 8, outputs: 0
12147 11:19:09.538715 [1mSubtest invalid: SKIP (0.000s)[0m
12148 11:19:09.553834 <14>[ 25.250257] [IGT] kms_vblank: executing
12149 11:19:09.560263 IGT-Version: 1.2<14>[ 25.255341] [IGT] kms_vblank: exiting, ret=77
12150 11:19:09.563760 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12151 11:19:09.570149 Opened device: /<8>[ 25.266285] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crtc-id RESULT=skip>
12152 11:19:09.570872 Received signal: <TESTCASE> TEST_CASE_ID=crtc-id RESULT=skip
12154 11:19:09.573595 dev/dri/card0
12155 11:19:09.576712 No KMS driver or no outputs, pipes: 8, outputs: 0
12156 11:19:09.580432 [1mSubtest crtc-id: SKIP (0.000s)[0m
12157 11:19:09.593507 <14>[ 25.289961] [IGT] kms_vblank: executing
12158 11:19:09.599879 IGT-Version: 1.2<14>[ 25.294922] [IGT] kms_vblank: exiting, ret=77
12159 11:19:09.603260 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12160 11:19:09.606515 Opened device: /dev/dri/card0
12161 11:19:09.613360 N<8>[ 25.306053] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-accuracy-idle RESULT=skip>
12162 11:19:09.614045 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-accuracy-idle RESULT=skip
12164 11:19:09.616651 o KMS driver or no outputs, pipes: 8, outputs: 0
12165 11:19:09.623219 [1mSubtest pipe-A-accuracy-idle: SKIP (0.000s)[0m
12166 11:19:09.635577 <14>[ 25.332078] [IGT] kms_vblank: executing
12167 11:19:09.642148 IGT-Version: 1.2<14>[ 25.337192] [IGT] kms_vblank: exiting, ret=77
12168 11:19:09.645677 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12169 11:19:09.648474 Opened device: /dev/dri/card0
12170 11:19:09.655088 N<8>[ 25.348271] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-idle RESULT=skip>
12171 11:19:09.655787 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-idle RESULT=skip
12173 11:19:09.658731 o KMS driver or no outputs, pipes: 8, outputs: 0
12174 11:19:09.665250 [1mSubtest pipe-A-query-idle: SKIP (0.000s)[0m
12175 11:19:09.678289 <14>[ 25.374729] [IGT] kms_vblank: executing
12176 11:19:09.684813 IGT-Version: 1.2<14>[ 25.379971] [IGT] kms_vblank: exiting, ret=77
12177 11:19:09.687893 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12178 11:19:09.691367 Opened device: /dev/dri/card0
12179 11:19:09.697585 N<8>[ 25.391846] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-idle-hang RESULT=skip>
12180 11:19:09.698269 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-idle-hang RESULT=skip
12182 11:19:09.704592 o KMS driver or no outputs, pipes: 8, outputs: 0
12183 11:19:09.707138 [1mSubtest pipe-A-query-idle-hang: SKIP (0.000s)[0m
12184 11:19:09.720597 <14>[ 25.417066] [IGT] kms_vblank: executing
12185 11:19:09.727196 IGT-Version: 1.2<14>[ 25.422157] [IGT] kms_vblank: exiting, ret=77
12186 11:19:09.730290 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12187 11:19:09.733922 Opened device: /dev/dri/card0
12188 11:19:09.740196 N<8>[ 25.433288] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked RESULT=skip>
12189 11:19:09.740885 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked RESULT=skip
12191 11:19:09.743882 o KMS driver or no outputs, pipes: 8, outputs: 0
12192 11:19:09.749801 [1mSubtest pipe-A-query-forked: SKIP (0.000s)[0m
12193 11:19:09.763438 <14>[ 25.459948] [IGT] kms_vblank: executing
12194 11:19:09.769942 IGT-Version: 1.2<14>[ 25.465179] [IGT] kms_vblank: exiting, ret=77
12195 11:19:09.773313 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12196 11:19:09.776603 Opened device: /dev/dri/card0
12197 11:19:09.783096 N<8>[ 25.476459] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-hang RESULT=skip>
12198 11:19:09.783786 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-hang RESULT=skip
12200 11:19:09.790024 o KMS driver or no outputs, pipes: 8, outputs: 0
12201 11:19:09.792864 [1mSubtest pipe-A-query-forked-hang: SKIP (0.000s)[0m
12202 11:19:09.806244 <14>[ 25.502851] [IGT] kms_vblank: executing
12203 11:19:09.813002 IGT-Version: 1.2<14>[ 25.508021] [IGT] kms_vblank: exiting, ret=77
12204 11:19:09.816173 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12205 11:19:09.826157 Opened device: /<8>[ 25.518846] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-busy RESULT=skip>
12206 11:19:09.826588 dev/dri/card0
12207 11:19:09.827176 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-busy RESULT=skip
12209 11:19:09.829589 No KMS driver or no outputs, pipes: 8, outputs: 0
12210 11:19:09.836063 [1mSubtest pipe-A-query-busy: SKIP (0.000s)[0m
12211 11:19:09.846932 <14>[ 25.543587] [IGT] kms_vblank: executing
12212 11:19:09.853574 IGT-Version: 1.2<14>[ 25.548711] [IGT] kms_vblank: exiting, ret=77
12213 11:19:09.857018 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12214 11:19:09.860125 Opened device: /dev/dri/card0
12215 11:19:09.866656 N<8>[ 25.559766] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-busy-hang RESULT=skip>
12216 11:19:09.867342 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-busy-hang RESULT=skip
12218 11:19:09.870155 o KMS driver or no outputs, pipes: 8, outputs: 0
12219 11:19:09.876962 [1mSubtest pipe-A-query-busy-hang: SKIP (0.000s)[0m
12220 11:19:09.889604 <14>[ 25.585971] [IGT] kms_vblank: executing
12221 11:19:09.896011 IGT-Version: 1.2<14>[ 25.590952] [IGT] kms_vblank: exiting, ret=77
12222 11:19:09.899274 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12223 11:19:09.902515 Opened device: /dev/dri/card0
12224 11:19:09.909149 N<8>[ 25.601946] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-busy RESULT=skip>
12225 11:19:09.909832 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-busy RESULT=skip
12227 11:19:09.916131 o KMS driver or no outputs, pipes: 8, outputs: 0
12228 11:19:09.919063 [1mSubtest pipe-A-query-forked-busy: SKIP (0.000s)[0m
12229 11:19:09.931758 <14>[ 25.628516] [IGT] kms_vblank: executing
12230 11:19:09.938433 IGT-Version: 1.2<14>[ 25.633501] [IGT] kms_vblank: exiting, ret=77
12231 11:19:09.941643 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12232 11:19:09.945008 Opened device: /dev/dri/card0
12233 11:19:09.951781 N<8>[ 25.644571] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-query-forked-busy-hang RESULT=skip>
12234 11:19:09.952463 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-query-forked-busy-hang RESULT=skip
12236 11:19:09.958144 o KMS driver or no outputs, pipes: 8, outputs: 0
12237 11:19:09.961669 [1mSubtest pipe-A-query-forked-busy-hang: SKIP (0.000s)[0m
12238 11:19:09.975279 <14>[ 25.672077] [IGT] kms_vblank: executing
12239 11:19:09.982493 IGT-Version: 1.2<14>[ 25.677467] [IGT] kms_vblank: exiting, ret=77
12240 11:19:09.985500 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12241 11:19:09.988518 Opened device: /dev/dri/card0
12242 11:19:09.995103 N<8>[ 25.688813] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-idle RESULT=skip>
12243 11:19:09.995913 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-idle RESULT=skip
12245 11:19:09.998777 o KMS driver or no outputs, pipes: 8, outputs: 0
12246 11:19:10.005074 [1mSubtest pipe-A-wait-idle: SKIP (0.000s)[0m
12247 11:19:10.017842 <14>[ 25.714193] [IGT] kms_vblank: executing
12248 11:19:10.024124 IGT-Version: 1.2<14>[ 25.719248] [IGT] kms_vblank: exiting, ret=77
12249 11:19:10.027412 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12250 11:19:10.030481 Opened device: /dev/dri/card0
12251 11:19:10.037248 N<8>[ 25.730330] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-idle-hang RESULT=skip>
12252 11:19:10.037925 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-idle-hang RESULT=skip
12254 11:19:10.043785 o KMS driver or no outputs, pipes: 8, outputs: 0
12255 11:19:10.046908 [1mSubtest pipe-A-wait-idle-hang: SKIP (0.000s)[0m
12256 11:19:10.060409 <14>[ 25.756604] [IGT] kms_vblank: executing
12257 11:19:10.066521 IGT-Version: 1.2<14>[ 25.761568] [IGT] kms_vblank: exiting, ret=77
12258 11:19:10.069924 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12259 11:19:10.073006 Opened device: /dev/dri/card0
12260 11:19:10.079567 N<8>[ 25.772733] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked RESULT=skip>
12261 11:19:10.080252 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked RESULT=skip
12263 11:19:10.082963 o KMS driver or no outputs, pipes: 8, outputs: 0
12264 11:19:10.089720 [1mSubtest pipe-A-wait-forked: SKIP (0.000s)[0m
12265 11:19:10.102067 <14>[ 25.798464] [IGT] kms_vblank: executing
12266 11:19:10.108405 IGT-Version: 1.2<14>[ 25.803606] [IGT] kms_vblank: exiting, ret=77
12267 11:19:10.111723 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12268 11:19:10.114724 Opened device: /dev/dri/card0
12269 11:19:10.121460 N<8>[ 25.814815] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-hang RESULT=skip>
12270 11:19:10.121714 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-hang RESULT=skip
12272 11:19:10.124971 o KMS driver or no outputs, pipes: 8, outputs: 0
12273 11:19:10.131244 [1mSubtest pipe-A-wait-forked-hang: SKIP (0.000s)[0m
12274 11:19:10.144079 <14>[ 25.840948] [IGT] kms_vblank: executing
12275 11:19:10.150597 IGT-Version: 1.2<14>[ 25.845923] [IGT] kms_vblank: exiting, ret=77
12276 11:19:10.153901 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12277 11:19:10.157231 Opened device: /dev/dri/card0
12278 11:19:10.163936 N<8>[ 25.857048] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-busy RESULT=skip>
12279 11:19:10.164190 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-busy RESULT=skip
12281 11:19:10.167010 o KMS driver or no outputs, pipes: 8, outputs: 0
12282 11:19:10.173711 [1mSubtest pipe-A-wait-busy: SKIP (0.000s)[0m
12283 11:19:10.185852 <14>[ 25.882860] [IGT] kms_vblank: executing
12284 11:19:10.192697 IGT-Version: 1.2<14>[ 25.887956] [IGT] kms_vblank: exiting, ret=77
12285 11:19:10.195893 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12286 11:19:10.199304 Opened device: /dev/dri/card0
12287 11:19:10.205955 N<8>[ 25.899049] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-busy-hang RESULT=skip>
12288 11:19:10.206209 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-busy-hang RESULT=skip
12290 11:19:10.209161 o KMS driver or no outputs, pipes: 8, outputs: 0
12291 11:19:10.215757 [1mSubtest pipe-A-wait-busy-hang: SKIP (0.000s)[0m
12292 11:19:10.228490 <14>[ 25.925124] [IGT] kms_vblank: executing
12293 11:19:10.234828 IGT-Version: 1.2<14>[ 25.930173] [IGT] kms_vblank: exiting, ret=77
12294 11:19:10.238091 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12295 11:19:10.241513 Opened device: /dev/dri/card0
12296 11:19:10.247830 N<8>[ 25.941198] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-busy RESULT=skip>
12297 11:19:10.248085 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-busy RESULT=skip
12299 11:19:10.251595 o KMS driver or no outputs, pipes: 8, outputs: 0
12300 11:19:10.258052 [1mSubtest pipe-A-wait-forked-busy: SKIP (0.000s)[0m
12301 11:19:10.270759 <14>[ 25.967598] [IGT] kms_vblank: executing
12302 11:19:10.277342 IGT-Version: 1.2<14>[ 25.972614] [IGT] kms_vblank: exiting, ret=77
12303 11:19:10.280389 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12304 11:19:10.284058 Opened device: /dev/dri/card0
12305 11:19:10.290486 N<8>[ 25.983662] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-wait-forked-busy-hang RESULT=skip>
12306 11:19:10.290743 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-wait-forked-busy-hang RESULT=skip
12308 11:19:10.297015 o KMS driver or no outputs, pipes: 8, outputs: 0
12309 11:19:10.300491 [1mSubtest pipe-A-wait-forked-busy-hang: SKIP (0.000s)[0m
12310 11:19:10.313734 <14>[ 26.010491] [IGT] kms_vblank: executing
12311 11:19:10.320281 IGT-Version: 1.2<14>[ 26.015672] [IGT] kms_vblank: exiting, ret=77
12312 11:19:10.323677 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12313 11:19:10.333551 Opened device: /<8>[ 26.026400] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-idle RESULT=skip>
12314 11:19:10.333636 dev/dri/card0
12315 11:19:10.333876 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-idle RESULT=skip
12317 11:19:10.340237 No KMS driver or no outputs, pipes: 8, outputs: 0
12318 11:19:10.343219 [1mSubtest pipe-A-ts-continuation-idle: SKIP (0.000s)[0m
12319 11:19:10.355717 <14>[ 26.052604] [IGT] kms_vblank: executing
12320 11:19:10.362080 IGT-Version: 1.2<14>[ 26.057717] [IGT] kms_vblank: exiting, ret=77
12321 11:19:10.365555 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12322 11:19:10.368907 Opened device: /dev/dri/card0
12323 11:19:10.375432 N<8>[ 26.069492] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-idle-hang RESULT=skip>
12324 11:19:10.375689 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-idle-hang RESULT=skip
12326 11:19:10.382147 o KMS driver or no outputs, pipes: 8, outputs: 0
12327 11:19:10.388250 [1mSubtest pipe-A-ts-continuation-idle-hang: SKIP (0.000s)[0m
12328 11:19:10.400027 <14>[ 26.096941] [IGT] kms_vblank: executing
12329 11:19:10.406617 IGT-Version: 1.2<14>[ 26.102173] [IGT] kms_vblank: exiting, ret=77
12330 11:19:10.410113 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12331 11:19:10.413167 Opened device: /dev/dri/card0
12332 11:19:10.419684 N<8>[ 26.113473] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-dpms-rpm RESULT=skip>
12333 11:19:10.419939 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-dpms-rpm RESULT=skip
12335 11:19:10.426041 o KMS driver or no outputs, pipes: 8, outputs: 0
12336 11:19:10.432620 [1mSubtest pipe-A-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12337 11:19:10.443214 <14>[ 26.140373] [IGT] kms_vblank: executing
12338 11:19:10.450166 IGT-Version: 1.2<14>[ 26.145378] [IGT] kms_vblank: exiting, ret=77
12339 11:19:10.453280 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12340 11:19:10.456612 Opened device: /dev/dri/card0
12341 11:19:10.463414 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-dpms-suspend RESULT=skip
12343 11:19:10.466629 N<8>[ 26.156758] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-dpms-suspend RESULT=skip>
12344 11:19:10.469707 o KMS driver or no outputs, pipes: 8, outputs: 0
12345 11:19:10.476147 [1mSubtest pipe-A-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12346 11:19:10.486906 <14>[ 26.184027] [IGT] kms_vblank: executing
12347 11:19:10.493569 IGT-Version: 1.2<14>[ 26.189076] [IGT] kms_vblank: exiting, ret=77
12348 11:19:10.497100 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12349 11:19:10.500037 Opened device: /dev/dri/card0
12350 11:19:10.506994 N<8>[ 26.200451] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-suspend RESULT=skip>
12351 11:19:10.507247 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-suspend RESULT=skip
12353 11:19:10.513619 o KMS driver or no outputs, pipes: 8, outputs: 0
12354 11:19:10.516672 [1mSubtest pipe-A-ts-continuation-suspend: SKIP (0.000s)[0m
12355 11:19:10.530163 <14>[ 26.227056] [IGT] kms_vblank: executing
12356 11:19:10.536669 IGT-Version: 1.2<14>[ 26.232090] [IGT] kms_vblank: exiting, ret=77
12357 11:19:10.540383 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12358 11:19:10.543234 Opened device: /dev/dri/card0
12359 11:19:10.550105 N<8>[ 26.243425] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset RESULT=skip>
12360 11:19:10.550358 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset RESULT=skip
12362 11:19:10.556364 o KMS driver or no outputs, pipes: 8, outputs: 0
12363 11:19:10.560201 [1mSubtest pipe-A-ts-continuation-modeset: SKIP (0.000s)[0m
12364 11:19:10.574556 <14>[ 26.271049] [IGT] kms_vblank: executing
12365 11:19:10.580587 IGT-Version: 1.2<14>[ 26.276113] [IGT] kms_vblank: exiting, ret=77
12366 11:19:10.583876 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12367 11:19:10.587216 Opened device: /dev/dri/card0
12368 11:19:10.594262 N<8>[ 26.287961] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset-hang RESULT=skip>
12369 11:19:10.594515 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset-hang RESULT=skip
12371 11:19:10.600584 o KMS driver or no outputs, pipes: 8, outputs: 0
12372 11:19:10.606904 [1mSubtest pipe-A-ts-continuation-modeset-hang: SKIP (0.000s)[0m
12373 11:19:10.617767 <14>[ 26.314624] [IGT] kms_vblank: executing
12374 11:19:10.624528 IGT-Version: 1.2<14>[ 26.319795] [IGT] kms_vblank: exiting, ret=77
12375 11:19:10.627466 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12376 11:19:10.630728 Opened device: /dev/dri/card0
12377 11:19:10.637434 N<8>[ 26.330717] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-A-ts-continuation-modeset-rpm RESULT=skip>
12378 11:19:10.637683 Received signal: <TESTCASE> TEST_CASE_ID=pipe-A-ts-continuation-modeset-rpm RESULT=skip
12380 11:19:10.643830 o KMS driver or no outputs, pipes: 8, outputs: 0
12381 11:19:10.650576 [1mSubtest pipe-A-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12382 11:19:10.662073 <14>[ 26.358860] [IGT] kms_vblank: executing
12383 11:19:10.668264 IGT-Version: 1.2<14>[ 26.363901] [IGT] kms_vblank: exiting, ret=77
12384 11:19:10.671833 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12385 11:19:10.674834 Opened device: /dev/dri/card0
12386 11:19:10.681746 N<8>[ 26.375864] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-accuracy-idle RESULT=skip>
12387 11:19:10.682010 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-accuracy-idle RESULT=skip
12389 11:19:10.685012 o KMS driver or no outputs, pipes: 8, outputs: 0
12390 11:19:10.691676 [1mSubtest pipe-B-accuracy-idle: SKIP (0.000s)[0m
12391 11:19:10.704531 <14>[ 26.401383] [IGT] kms_vblank: executing
12392 11:19:10.710898 IGT-Version: 1.2<14>[ 26.406427] [IGT] kms_vblank: exiting, ret=77
12393 11:19:10.714491 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12394 11:19:10.717378 Opened device: /dev/dri/card0
12395 11:19:10.724108 N<8>[ 26.417581] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-idle RESULT=skip>
12396 11:19:10.724357 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-idle RESULT=skip
12398 11:19:10.727289 o KMS driver or no outputs, pipes: 8, outputs: 0
12399 11:19:10.733953 [1mSubtest pipe-B-query-idle: SKIP (0.000s)[0m
12400 11:19:10.746701 <14>[ 26.443900] [IGT] kms_vblank: executing
12401 11:19:10.753350 IGT-Version: 1.2<14>[ 26.448993] [IGT] kms_vblank: exiting, ret=77
12402 11:19:10.756922 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12403 11:19:10.760001 Opened device: /dev/dri/card0
12404 11:19:10.766776 N<8>[ 26.460558] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-idle-hang RESULT=skip>
12405 11:19:10.767027 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-idle-hang RESULT=skip
12407 11:19:10.773351 o KMS driver or no outputs, pipes: 8, outputs: 0
12408 11:19:10.776700 [1mSubtest pipe-B-query-idle-hang: SKIP (0.000s)[0m
12409 11:19:10.789555 <14>[ 26.486278] [IGT] kms_vblank: executing
12410 11:19:10.795785 IGT-Version: 1.2<14>[ 26.491362] [IGT] kms_vblank: exiting, ret=77
12411 11:19:10.799512 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12412 11:19:10.809443 Opened device: /<8>[ 26.502138] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked RESULT=skip>
12413 11:19:10.809533 dev/dri/card0
12414 11:19:10.809789 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked RESULT=skip
12416 11:19:10.812506 No KMS driver or no outputs, pipes: 8, outputs: 0
12417 11:19:10.819091 [1mSubtest pipe-B-query-forked: SKIP (0.000s)[0m
12418 11:19:10.829989 <14>[ 26.526874] [IGT] kms_vblank: executing
12419 11:19:10.836573 IGT-Version: 1.2<14>[ 26.531911] [IGT] kms_vblank: exiting, ret=77
12420 11:19:10.839727 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12421 11:19:10.849485 Opened device: /<8>[ 26.542764] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-hang RESULT=skip>
12422 11:19:10.849567 dev/dri/card0
12423 11:19:10.849820 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-hang RESULT=skip
12425 11:19:10.855983 No KMS driver or no outputs, pipes: 8, outputs: 0
12426 11:19:10.859579 [1mSubtest pipe-B-query-forked-hang: SKIP (0.000s)[0m
12427 11:19:10.871079 <14>[ 26.567982] [IGT] kms_vblank: executing
12428 11:19:10.877493 IGT-Version: 1.2<14>[ 26.572942] [IGT] kms_vblank: exiting, ret=77
12429 11:19:10.881056 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12430 11:19:10.884369 Opened device: /dev/dri/card0
12431 11:19:10.890995 N<8>[ 26.583993] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-busy RESULT=skip>
12432 11:19:10.891247 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-busy RESULT=skip
12434 11:19:10.893891 o KMS driver or no outputs, pipes: 8, outputs: 0
12435 11:19:10.900351 [1mSubtest pipe-B-query-busy: SKIP (0.000s)[0m
12436 11:19:10.913516 <14>[ 26.610505] [IGT] kms_vblank: executing
12437 11:19:10.920086 IGT-Version: 1.2<14>[ 26.615748] [IGT] kms_vblank: exiting, ret=77
12438 11:19:10.923447 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12439 11:19:10.926932 Opened device: /dev/dri/card0
12440 11:19:10.933467 N<8>[ 26.627050] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-busy-hang RESULT=skip>
12441 11:19:10.933802 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-busy-hang RESULT=skip
12443 11:19:10.936746 o KMS driver or no outputs, pipes: 8, outputs: 0
12444 11:19:10.943305 [1mSubtest pipe-B-query-busy-hang: SKIP (0.000s)[0m
12445 11:19:10.957527 <14>[ 26.653977] [IGT] kms_vblank: executing
12446 11:19:10.964130 IGT-Version: 1.2<14>[ 26.659087] [IGT] kms_vblank: exiting, ret=77
12447 11:19:10.967283 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12448 11:19:10.970479 Opened device: /dev/dri/card0
12449 11:19:10.977594 N<8>[ 26.670332] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-busy RESULT=skip>
12450 11:19:10.978410 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-busy RESULT=skip
12452 11:19:10.983659 o KMS driver or no outputs, pipes: 8, outputs: 0
12453 11:19:10.987116 [1mSubtest pipe-B-query-forked-busy: SKIP (0.000s)[0m
12454 11:19:11.000399 <14>[ 26.696778] [IGT] kms_vblank: executing
12455 11:19:11.006875 IGT-Version: 1.2<14>[ 26.701804] [IGT] kms_vblank: exiting, ret=77
12456 11:19:11.009872 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12457 11:19:11.013435 Opened device: /dev/dri/card0
12458 11:19:11.019803 N<8>[ 26.712807] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-query-forked-busy-hang RESULT=skip>
12459 11:19:11.020532 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-query-forked-busy-hang RESULT=skip
12461 11:19:11.026447 o KMS driver or no outputs, pipes: 8, outputs: 0
12462 11:19:11.029609 [1mSubtest pipe-B-query-forked-busy-hang: SKIP (0.000s)[0m
12463 11:19:11.043529 <14>[ 26.740370] [IGT] kms_vblank: executing
12464 11:19:11.050637 IGT-Version: 1.2<14>[ 26.745990] [IGT] kms_vblank: exiting, ret=77
12465 11:19:11.053413 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12466 11:19:11.056243 Opened device: /dev/dri/card0
12467 11:19:11.063269 N<8>[ 26.757021] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-idle RESULT=skip>
12468 11:19:11.063524 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-idle RESULT=skip
12470 11:19:11.066274 o KMS driver or no outputs, pipes: 8, outputs: 0
12471 11:19:11.072949 [1mSubtest pipe-B-wait-idle: SKIP (0.000s)[0m
12472 11:19:11.086739 <14>[ 26.783859] [IGT] kms_vblank: executing
12473 11:19:11.093331 IGT-Version: 1.2<14>[ 26.788992] [IGT] kms_vblank: exiting, ret=77
12474 11:19:11.096391 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12475 11:19:11.099860 Opened device: /dev/dri/card0
12476 11:19:11.106724 N<8>[ 26.800259] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-idle-hang RESULT=skip>
12477 11:19:11.106979 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-idle-hang RESULT=skip
12479 11:19:11.113065 o KMS driver or no outputs, pipes: 8, outputs: 0
12480 11:19:11.116144 [1mSubtest pipe-B-wait-idle-hang: SKIP (0.000s)[0m
12481 11:19:11.129244 <14>[ 26.826233] [IGT] kms_vblank: executing
12482 11:19:11.135928 IGT-Version: 1.2<14>[ 26.831313] [IGT] kms_vblank: exiting, ret=77
12483 11:19:11.139438 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12484 11:19:11.142152 Opened device: /dev/dri/card0
12485 11:19:11.149133 N<8>[ 26.842345] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked RESULT=skip>
12486 11:19:11.149387 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked RESULT=skip
12488 11:19:11.152363 o KMS driver or no outputs, pipes: 8, outputs: 0
12489 11:19:11.158613 [1mSubtest pipe-B-wait-forked: SKIP (0.000s)[0m
12490 11:19:11.172080 <14>[ 26.869137] [IGT] kms_vblank: executing
12491 11:19:11.178747 IGT-Version: 1.2<14>[ 26.874239] [IGT] kms_vblank: exiting, ret=77
12492 11:19:11.181763 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12493 11:19:11.185243 Opened device: /dev/dri/card0
12494 11:19:11.191902 N<8>[ 26.885415] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-hang RESULT=skip>
12495 11:19:11.192154 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-hang RESULT=skip
12497 11:19:11.198479 o KMS driver or no outputs, pipes: 8, outputs: 0
12498 11:19:11.201470 [1mSubtest pipe-B-wait-forked-hang: SKIP (0.000s)[0m
12499 11:19:11.214725 <14>[ 26.911648] [IGT] kms_vblank: executing
12500 11:19:11.221077 IGT-Version: 1.2<14>[ 26.916786] [IGT] kms_vblank: exiting, ret=77
12501 11:19:11.224658 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12502 11:19:11.228103 Opened device: /dev/dri/card0
12503 11:19:11.234546 N<8>[ 26.927868] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-busy RESULT=skip>
12504 11:19:11.234797 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-busy RESULT=skip
12506 11:19:11.237684 o KMS driver or no outputs, pipes: 8, outputs: 0
12507 11:19:11.244387 [1mSubtest pipe-B-wait-busy: SKIP (0.000s)[0m
12508 11:19:11.257487 <14>[ 26.954335] [IGT] kms_vblank: executing
12509 11:19:11.264165 IGT-Version: 1.2<14>[ 26.959840] [IGT] kms_vblank: exiting, ret=77
12510 11:19:11.267054 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12511 11:19:11.270624 Opened device: /dev/dri/card0
12512 11:19:11.277067 N<8>[ 26.970772] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-busy-hang RESULT=skip>
12513 11:19:11.277318 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-busy-hang RESULT=skip
12515 11:19:11.280659 o KMS driver or no outputs, pipes: 8, outputs: 0
12516 11:19:11.287135 [1mSubtest pipe-B-wait-busy-hang: SKIP (0.000s)[0m
12517 11:19:11.300067 <14>[ 26.996847] [IGT] kms_vblank: executing
12518 11:19:11.306230 IGT-Version: 1.2<14>[ 27.001935] [IGT] kms_vblank: exiting, ret=77
12519 11:19:11.309614 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12520 11:19:11.319835 Opened device: /<8>[ 27.012841] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-busy RESULT=skip>
12521 11:19:11.319917 dev/dri/card0
12522 11:19:11.320152 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-busy RESULT=skip
12524 11:19:11.326291 No KMS driver or no outputs, pipes: 8, outputs: 0
12525 11:19:11.329748 [1mSubtest pipe-B-wait-forked-busy: SKIP (0.000s)[0m
12526 11:19:11.341531 <14>[ 27.038568] [IGT] kms_vblank: executing
12527 11:19:11.348271 IGT-Version: 1.2<14>[ 27.043758] [IGT] kms_vblank: exiting, ret=77
12528 11:19:11.352463 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12529 11:19:11.354553 Opened device: /dev/dri/card0
12530 11:19:11.361504 N<8>[ 27.054974] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-wait-forked-busy-hang RESULT=skip>
12531 11:19:11.361831 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-wait-forked-busy-hang RESULT=skip
12533 11:19:11.367877 o KMS driver or no outputs, pipes: 8, outputs: 0
12534 11:19:11.371086 [1mSubtest pipe-B-wait-forked-busy-hang: SKIP (0.000s)[0m
12535 11:19:11.384269 <14>[ 27.081522] [IGT] kms_vblank: executing
12536 11:19:11.391200 IGT-Version: 1.2<14>[ 27.086528] [IGT] kms_vblank: exiting, ret=77
12537 11:19:11.394115 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12538 11:19:11.404323 Opened device: /<8>[ 27.097320] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-idle RESULT=skip>
12539 11:19:11.404407 dev/dri/card0
12540 11:19:11.404642 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-idle RESULT=skip
12542 11:19:11.410646 No KMS driver or no outputs, pipes: 8, outputs: 0
12543 11:19:11.414083 [1mSubtest pipe-B-ts-continuation-idle: SKIP (0.000s)[0m
12544 11:19:11.426826 <14>[ 27.123889] [IGT] kms_vblank: executing
12545 11:19:11.433360 IGT-Version: 1.2<14>[ 27.129019] [IGT] kms_vblank: exiting, ret=77
12546 11:19:11.437092 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12547 11:19:11.440172 Opened device: /dev/dri/card0
12548 11:19:11.447078 N<8>[ 27.140243] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-idle-hang RESULT=skip>
12549 11:19:11.447331 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-idle-hang RESULT=skip
12551 11:19:11.452970 o KMS driver or no outputs, pipes: 8, outputs: 0
12552 11:19:11.456715 [1mSubtest pipe-B-ts-continuation-idle-hang: SKIP (0.000s)[0m
12553 11:19:11.471186 <14>[ 27.167948] [IGT] kms_vblank: executing
12554 11:19:11.477709 IGT-Version: 1.2<14>[ 27.173482] [IGT] kms_vblank: exiting, ret=77
12555 11:19:11.481031 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12556 11:19:11.484291 Opened device: /dev/dri/card0
12557 11:19:11.491109 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-dpms-rpm RESULT=skip
12559 11:19:11.493978 N<8>[ 27.184960] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-dpms-rpm RESULT=skip>
12560 11:19:11.497483 o KMS driver or no outputs, pipes: 8, outputs: 0
12561 11:19:11.504148 [1mSubtest pipe-B-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12562 11:19:11.514579 <14>[ 27.211627] [IGT] kms_vblank: executing
12563 11:19:11.521462 IGT-Version: 1.2<14>[ 27.216796] [IGT] kms_vblank: exiting, ret=77
12564 11:19:11.524555 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12565 11:19:11.528077 Opened device: /dev/dri/card0
12566 11:19:11.534570 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-dpms-suspend RESULT=skip
12568 11:19:11.537874 N<8>[ 27.227762] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-dpms-suspend RESULT=skip>
12569 11:19:11.541128 o KMS driver or no outputs, pipes: 8, outputs: 0
12570 11:19:11.547597 [1mSubtest pipe-B-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12571 11:19:11.558318 <14>[ 27.255172] [IGT] kms_vblank: executing
12572 11:19:11.564589 IGT-Version: 1.2<14>[ 27.260156] [IGT] kms_vblank: exiting, ret=77
12573 11:19:11.568262 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12574 11:19:11.578216 Opened device: /<8>[ 27.271042] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-suspend RESULT=skip>
12575 11:19:11.578300 dev/dri/card0
12576 11:19:11.578552 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-suspend RESULT=skip
12578 11:19:11.584385 No KMS driver or no outputs, pipes: 8, outputs: 0
12579 11:19:11.587853 [1mSubtest pipe-B-ts-continuation-suspend: SKIP (0.000s)[0m
12580 11:19:11.600485 <14>[ 27.297004] [IGT] kms_vblank: executing
12581 11:19:11.607041 IGT-Version: 1.2<14>[ 27.302041] [IGT] kms_vblank: exiting, ret=77
12582 11:19:11.610013 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12583 11:19:11.620020 Opened device: /<8>[ 27.312789] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset RESULT=skip>
12584 11:19:11.620284 dev/dri/card0
12585 11:19:11.620644 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset RESULT=skip
12587 11:19:11.626654 No KMS driver or no outputs, pipes: 8, outputs: 0
12588 11:19:11.629841 [1mSubtest pipe-B-ts-continuation-modeset: SKIP (0.000s)[0m
12589 11:19:11.642084 <14>[ 27.338680] [IGT] kms_vblank: executing
12590 11:19:11.648325 IGT-Version: 1.2<14>[ 27.343858] [IGT] kms_vblank: exiting, ret=77
12591 11:19:11.652013 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12592 11:19:11.655261 Opened device: /dev/dri/card0
12593 11:19:11.662134 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset-hang RESULT=skip
12595 11:19:11.664852 N<8>[ 27.354621] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset-hang RESULT=skip>
12596 11:19:11.668599 o KMS driver or no outputs, pipes: 8, outputs: 0
12597 11:19:11.675113 [1mSubtest pipe-B-ts-continuation-modeset-hang: SKIP (0.000s)[0m
12598 11:19:11.685284 <14>[ 27.382028] [IGT] kms_vblank: executing
12599 11:19:11.692314 IGT-Version: 1.2<14>[ 27.387085] [IGT] kms_vblank: exiting, ret=77
12600 11:19:11.695585 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12601 11:19:11.705140 Opened device: /<8>[ 27.397838] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-B-ts-continuation-modeset-rpm RESULT=skip>
12602 11:19:11.705707 dev/dri/card0
12603 11:19:11.706346 Received signal: <TESTCASE> TEST_CASE_ID=pipe-B-ts-continuation-modeset-rpm RESULT=skip
12605 11:19:11.711844 No KMS driver or no outputs, pipes: 8, outputs: 0
12606 11:19:11.718361 [1mSubtest pipe-B-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12607 11:19:11.727989 <14>[ 27.424901] [IGT] kms_vblank: executing
12608 11:19:11.734939 IGT-Version: 1.2<14>[ 27.429821] [IGT] kms_vblank: exiting, ret=77
12609 11:19:11.738312 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12610 11:19:11.741480 Opened device: /dev/dri/card0
12611 11:19:11.748251 N<8>[ 27.441174] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-accuracy-idle RESULT=skip>
12612 11:19:11.749130 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-accuracy-idle RESULT=skip
12614 11:19:11.750946 o KMS driver or no outputs, pipes: 8, outputs: 0
12615 11:19:11.757878 [1mSubtest pipe-C-accuracy-idle: SKIP (0.000s)[0m
12616 11:19:11.771331 <14>[ 27.467785] [IGT] kms_vblank: executing
12617 11:19:11.777607 IGT-Version: 1.2<14>[ 27.472928] [IGT] kms_vblank: exiting, ret=77
12618 11:19:11.780956 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12619 11:19:11.784478 Opened device: /dev/dri/card0
12620 11:19:11.790571 N<8>[ 27.484731] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-idle RESULT=skip>
12621 11:19:11.791462 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-idle RESULT=skip
12623 11:19:11.794098 o KMS driver or no outputs, pipes: 8, outputs: 0
12624 11:19:11.800578 [1mSubtest pipe-C-query-idle: SKIP (0.000s)[0m
12625 11:19:11.813383 <14>[ 27.509926] [IGT] kms_vblank: executing
12626 11:19:11.820238 IGT-Version: 1.2<14>[ 27.514941] [IGT] kms_vblank: exiting, ret=77
12627 11:19:11.823245 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12628 11:19:11.833542 Opened device: /<8>[ 27.525872] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-idle-hang RESULT=skip>
12629 11:19:11.834110 dev/dri/card0
12630 11:19:11.834759 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-idle-hang RESULT=skip
12632 11:19:11.836388 No KMS driver or no outputs, pipes: 8, outputs: 0
12633 11:19:11.843048 [1mSubtest pipe-C-query-idle-hang: SKIP (0.000s)[0m
12634 11:19:11.854358 <14>[ 27.550829] [IGT] kms_vblank: executing
12635 11:19:11.861112 IGT-Version: 1.2<14>[ 27.555978] [IGT] kms_vblank: exiting, ret=77
12636 11:19:11.864168 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12637 11:19:11.873999 Opened device: /<8>[ 27.566697] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked RESULT=skip>
12638 11:19:11.874700 dev/dri/card0
12639 11:19:11.875374 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked RESULT=skip
12641 11:19:11.877606 No KMS driver or no outputs, pipes: 8, outputs: 0
12642 11:19:11.883610 [1mSubtest pipe-C-query-forked: SKIP (0.000s)[0m
12643 11:19:11.894977 <14>[ 27.591573] [IGT] kms_vblank: executing
12644 11:19:11.901571 IGT-Version: 1.2<14>[ 27.596590] [IGT] kms_vblank: exiting, ret=77
12645 11:19:11.904873 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12646 11:19:11.914919 Opened device: /<8>[ 27.607515] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-hang RESULT=skip>
12647 11:19:11.915474 dev/dri/card0
12648 11:19:11.916133 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-hang RESULT=skip
12650 11:19:11.921262 No KMS driver or no outputs, pipes: 8, outputs: 0
12651 11:19:11.924801 [1mSubtest pipe-C-query-forked-hang: SKIP (0.000s)[0m
12652 11:19:11.936697 <14>[ 27.632848] [IGT] kms_vblank: executing
12653 11:19:11.942621 IGT-Version: 1.2<14>[ 27.637859] [IGT] kms_vblank: exiting, ret=77
12654 11:19:11.946371 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12655 11:19:11.955970 Opened device: /<8>[ 27.648700] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-busy RESULT=skip>
12656 11:19:11.956543 dev/dri/card0
12657 11:19:11.957225 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-busy RESULT=skip
12659 11:19:11.959109 No KMS driver or no outputs, pipes: 8, outputs: 0
12660 11:19:11.965427 [1mSubtest pipe-C-query-busy: SKIP (0.000s)[0m
12661 11:19:11.977199 <14>[ 27.673454] [IGT] kms_vblank: executing
12662 11:19:11.983251 IGT-Version: 1.2<14>[ 27.678493] [IGT] kms_vblank: exiting, ret=77
12663 11:19:11.986581 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12664 11:19:11.996325 Opened device: /<8>[ 27.689376] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-busy-hang RESULT=skip>
12665 11:19:11.996935 dev/dri/card0
12666 11:19:11.997573 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-busy-hang RESULT=skip
12668 11:19:11.999751 No KMS driver or no outputs, pipes: 8, outputs: 0
12669 11:19:12.006258 [1mSubtest pipe-C-query-busy-hang: SKIP (0.000s)[0m
12670 11:19:12.017669 <14>[ 27.714405] [IGT] kms_vblank: executing
12671 11:19:12.024623 IGT-Version: 1.2<14>[ 27.719536] [IGT] kms_vblank: exiting, ret=77
12672 11:19:12.027655 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12673 11:19:12.030973 Opened device: /dev/dri/card0
12674 11:19:12.037452 N<8>[ 27.730565] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-busy RESULT=skip>
12675 11:19:12.038294 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-busy RESULT=skip
12677 11:19:12.044032 o KMS driver or no outputs, pipes: 8, outputs: 0
12678 11:19:12.047804 [1mSubtest pipe-C-query-forked-busy: SKIP (0.000s)[0m
12679 11:19:12.060568 <14>[ 27.757042] [IGT] kms_vblank: executing
12680 11:19:12.066904 IGT-Version: 1.2<14>[ 27.762019] [IGT] kms_vblank: exiting, ret=77
12681 11:19:12.070450 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12682 11:19:12.080142 Opened device: /<8>[ 27.772976] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-query-forked-busy-hang RESULT=skip>
12683 11:19:12.080714 dev/dri/card0
12684 11:19:12.081480 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-query-forked-busy-hang RESULT=skip
12686 11:19:12.086925 No KMS driver or no outputs, pipes: 8, outputs: 0
12687 11:19:12.089943 [1mSubtest pipe-C-query-forked-busy-hang: SKIP (0.000s)[0m
12688 11:19:12.102786 <14>[ 27.799225] [IGT] kms_vblank: executing
12689 11:19:12.109375 IGT-Version: 1.2<14>[ 27.804312] [IGT] kms_vblank: exiting, ret=77
12690 11:19:12.113408 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12691 11:19:12.115835 Opened device: /dev/dri/card0
12692 11:19:12.122141 N<8>[ 27.815693] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-idle RESULT=skip>
12693 11:19:12.122975 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-idle RESULT=skip
12695 11:19:12.125459 o KMS driver or no outputs, pipes: 8, outputs: 0
12696 11:19:12.132077 [1mSubtest pipe-C-wait-idle: SKIP (0.000s)[0m
12697 11:19:12.144301 <14>[ 27.841154] [IGT] kms_vblank: executing
12698 11:19:12.151368 IGT-Version: 1.2<14>[ 27.846177] [IGT] kms_vblank: exiting, ret=77
12699 11:19:12.154453 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12700 11:19:12.164253 Opened device: /<8>[ 27.857133] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-idle-hang RESULT=skip>
12701 11:19:12.164850 dev/dri/card0
12702 11:19:12.165506 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-idle-hang RESULT=skip
12704 11:19:12.167132 No KMS driver or no outputs, pipes: 8, outputs: 0
12705 11:19:12.173770 [1mSubtest pipe-C-wait-idle-hang: SKIP (0.000s)[0m
12706 11:19:12.185769 <14>[ 27.882595] [IGT] kms_vblank: executing
12707 11:19:12.192587 IGT-Version: 1.2<14>[ 27.887975] [IGT] kms_vblank: exiting, ret=77
12708 11:19:12.195916 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12709 11:19:12.199161 Opened device: /dev/dri/card0
12710 11:19:12.206256 N<8>[ 27.899203] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked RESULT=skip>
12711 11:19:12.207134 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked RESULT=skip
12713 11:19:12.209027 o KMS driver or no outputs, pipes: 8, outputs: 0
12714 11:19:12.215728 [1mSubtest pipe-C-wait-forked: SKIP (0.000s)[0m
12715 11:19:12.228911 <14>[ 27.925321] [IGT] kms_vblank: executing
12716 11:19:12.235616 IGT-Version: 1.2<14>[ 27.930469] [IGT] kms_vblank: exiting, ret=77
12717 11:19:12.238832 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12718 11:19:12.241879 Opened device: /dev/dri/card0
12719 11:19:12.248725 N<8>[ 27.941827] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-hang RESULT=skip>
12720 11:19:12.249628 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-hang RESULT=skip
12722 11:19:12.255056 o KMS driver or no outputs, pipes: 8, outputs: 0
12723 11:19:12.258689 [1mSubtest pipe-C-wait-forked-hang: SKIP (0.000s)[0m
12724 11:19:12.272465 <14>[ 27.968611] [IGT] kms_vblank: executing
12725 11:19:12.278642 IGT-Version: 1.2<14>[ 27.973926] [IGT] kms_vblank: exiting, ret=77
12726 11:19:12.282043 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12727 11:19:12.285245 Opened device: /dev/dri/card0
12728 11:19:12.291869 N<8>[ 27.985434] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-busy RESULT=skip>
12729 11:19:12.292725 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-busy RESULT=skip
12731 11:19:12.295423 o KMS driver or no outputs, pipes: 8, outputs: 0
12732 11:19:12.301829 [1mSubtest pipe-C-wait-busy: SKIP (0.000s)[0m
12733 11:19:12.315550 <14>[ 28.011820] [IGT] kms_vblank: executing
12734 11:19:12.322138 IGT-Version: 1.2<14>[ 28.016813] [IGT] kms_vblank: exiting, ret=77
12735 11:19:12.325211 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12736 11:19:12.328309 Opened device: /dev/dri/card0
12737 11:19:12.335203 N<8>[ 28.028179] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-busy-hang RESULT=skip>
12738 11:19:12.336052 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-busy-hang RESULT=skip
12740 11:19:12.338423 o KMS driver or no outputs, pipes: 8, outputs: 0
12741 11:19:12.344649 [1mSubtest pipe-C-wait-busy-hang: SKIP (0.000s)[0m
12742 11:19:12.357744 <14>[ 28.054219] [IGT] kms_vblank: executing
12743 11:19:12.364479 IGT-Version: 1.2<14>[ 28.059255] [IGT] kms_vblank: exiting, ret=77
12744 11:19:12.367135 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12745 11:19:12.370688 Opened device: /dev/dri/card0
12746 11:19:12.377695 N<8>[ 28.070140] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-busy RESULT=skip>
12747 11:19:12.378537 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-busy RESULT=skip
12749 11:19:12.380404 o KMS driver or no outputs, pipes: 8, outputs: 0
12750 11:19:12.386985 [1mSubtest pipe-C-wait-forked-busy: SKIP (0.000s)[0m
12751 11:19:12.400473 <14>[ 28.097222] [IGT] kms_vblank: executing
12752 11:19:12.407051 IGT-Version: 1.2<14>[ 28.102510] [IGT] kms_vblank: exiting, ret=77
12753 11:19:12.410112 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12754 11:19:12.413693 Opened device: /dev/dri/card0
12755 11:19:12.420209 N<8>[ 28.113793] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-wait-forked-busy-hang RESULT=skip>
12756 11:19:12.420729 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-wait-forked-busy-hang RESULT=skip
12758 11:19:12.426812 o KMS driver or no outputs, pipes: 8, outputs: 0
12759 11:19:12.430149 [1mSubtest pipe-C-wait-forked-busy-hang: SKIP (0.000s)[0m
12760 11:19:12.443325 <14>[ 28.140374] [IGT] kms_vblank: executing
12761 11:19:12.450003 IGT-Version: 1.2<14>[ 28.145411] [IGT] kms_vblank: exiting, ret=77
12762 11:19:12.453566 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12763 11:19:12.456615 Opened device: /dev/dri/card0
12764 11:19:12.463671 N<8>[ 28.156749] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-idle RESULT=skip>
12765 11:19:12.464502 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-idle RESULT=skip
12767 11:19:12.469925 o KMS driver or no outputs, pipes: 8, outputs: 0
12768 11:19:12.473110 [1mSubtest pipe-C-ts-continuation-idle: SKIP (0.000s)[0m
12769 11:19:12.486693 <14>[ 28.183229] [IGT] kms_vblank: executing
12770 11:19:12.493155 IGT-Version: 1.2<14>[ 28.188238] [IGT] kms_vblank: exiting, ret=77
12771 11:19:12.496532 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12772 11:19:12.499545 Opened device: /dev/dri/card0
12773 11:19:12.506760 N<8>[ 28.199304] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-idle-hang RESULT=skip>
12774 11:19:12.507588 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-idle-hang RESULT=skip
12776 11:19:12.513441 o KMS driver or no outputs, pipes: 8, outputs: 0
12777 11:19:12.516530 [1mSubtest pipe-C-ts-continuation-idle-hang: SKIP (0.000s)[0m
12778 11:19:12.530015 <14>[ 28.226468] [IGT] kms_vblank: executing
12779 11:19:12.536490 IGT-Version: 1.2<14>[ 28.231656] [IGT] kms_vblank: exiting, ret=77
12780 11:19:12.539258 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12781 11:19:12.549680 Opened device: /<8>[ 28.242410] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-dpms-rpm RESULT=skip>
12782 11:19:12.550232 dev/dri/card0
12783 11:19:12.550864 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-dpms-rpm RESULT=skip
12785 11:19:12.556015 No KMS driver or no outputs, pipes: 8, outputs: 0
12786 11:19:12.559261 [1mSubtest pipe-C-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
12787 11:19:12.572636 <14>[ 28.269136] [IGT] kms_vblank: executing
12788 11:19:12.579424 IGT-Version: 1.2<14>[ 28.274416] [IGT] kms_vblank: exiting, ret=77
12789 11:19:12.582081 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12790 11:19:12.585432 Opened device: /dev/dri/card0
12791 11:19:12.595675 N<8>[ 28.285410] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-dpms-suspend RESULT=skip>
12792 11:19:12.596512 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-dpms-suspend RESULT=skip
12794 11:19:12.598896 o KMS driver or no outputs, pipes: 8, outputs: 0
12795 11:19:12.605606 [1mSubtest pipe-C-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
12796 11:19:12.617616 <14>[ 28.313878] [IGT] kms_vblank: executing
12797 11:19:12.623848 IGT-Version: 1.2<14>[ 28.319116] [IGT] kms_vblank: exiting, ret=77
12798 11:19:12.627387 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12799 11:19:12.637361 Opened device: /<8>[ 28.329911] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-suspend RESULT=skip>
12800 11:19:12.637934 dev/dri/card0
12801 11:19:12.638567 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-suspend RESULT=skip
12803 11:19:12.643665 No KMS driver or no outputs, pipes: 8, outputs: 0
12804 11:19:12.646991 [1mSubtest pipe-C-ts-continuation-suspend: SKIP (0.000s)[0m
12805 11:19:12.659527 <14>[ 28.356531] [IGT] kms_vblank: executing
12806 11:19:12.666524 IGT-Version: 1.2<14>[ 28.361749] [IGT] kms_vblank: exiting, ret=77
12807 11:19:12.669733 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12808 11:19:12.673187 Opened device: /dev/dri/card0
12809 11:19:12.679271 N<8>[ 28.372825] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset RESULT=skip>
12810 11:19:12.680116 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset RESULT=skip
12812 11:19:12.686205 o KMS driver or no outputs, pipes: 8, outputs: 0
12813 11:19:12.689281 [1mSubtest pipe-C-ts-continuation-modeset: SKIP (0.000s)[0m
12814 11:19:12.703948 <14>[ 28.400600] [IGT] kms_vblank: executing
12815 11:19:12.710861 IGT-Version: 1.2<14>[ 28.405756] [IGT] kms_vblank: exiting, ret=77
12816 11:19:12.713479 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12817 11:19:12.717408 Opened device: /dev/dri/card0
12818 11:19:12.724382 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset-hang RESULT=skip
12820 11:19:12.726790 N<8>[ 28.417366] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset-hang RESULT=skip>
12821 11:19:12.730667 o KMS driver or no outputs, pipes: 8, outputs: 0
12822 11:19:12.737170 [1mSubtest pipe-C-ts-continuation-modeset-hang: SKIP (0.000s)[0m
12823 11:19:12.748862 <14>[ 28.445406] [IGT] kms_vblank: executing
12824 11:19:12.755943 IGT-Version: 1.2<14>[ 28.450359] [IGT] kms_vblank: exiting, ret=77
12825 11:19:12.758840 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12826 11:19:12.769379 Opened device: /<8>[ 28.461387] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-C-ts-continuation-modeset-rpm RESULT=skip>
12827 11:19:12.769928 dev/dri/card0
12828 11:19:12.770563 Received signal: <TESTCASE> TEST_CASE_ID=pipe-C-ts-continuation-modeset-rpm RESULT=skip
12830 11:19:12.775429 No KMS driver or no outputs, pipes: 8, outputs: 0
12831 11:19:12.781657 [1mSubtest pipe-C-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
12832 11:19:12.791086 <14>[ 28.487384] [IGT] kms_vblank: executing
12833 11:19:12.797066 IGT-Version: 1.2<14>[ 28.492355] [IGT] kms_vblank: exiting, ret=77
12834 11:19:12.800461 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12835 11:19:12.810712 Opened device: /<8>[ 28.503252] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-accuracy-idle RESULT=skip>
12836 11:19:12.811264 dev/dri/card0
12837 11:19:12.811898 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-accuracy-idle RESULT=skip
12839 11:19:12.813703 No KMS driver or no outputs, pipes: 8, outputs: 0
12840 11:19:12.820203 [1mSubtest pipe-D-accuracy-idle: SKIP (0.000s)[0m
12841 11:19:12.832362 <14>[ 28.529000] [IGT] kms_vblank: executing
12842 11:19:12.838879 IGT-Version: 1.2<14>[ 28.534297] [IGT] kms_vblank: exiting, ret=77
12843 11:19:12.842014 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12844 11:19:12.845644 Opened device: /dev/dri/card0
12845 11:19:12.852689 N<8>[ 28.545372] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-idle RESULT=skip>
12846 11:19:12.853555 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-idle RESULT=skip
12848 11:19:12.855197 o KMS driver or no outputs, pipes: 8, outputs: 0
12849 11:19:12.861900 [1mSubtest pipe-D-query-idle: SKIP (0.000s)[0m
12850 11:19:12.874435 <14>[ 28.571228] [IGT] kms_vblank: executing
12851 11:19:12.881462 IGT-Version: 1.2<14>[ 28.576189] [IGT] kms_vblank: exiting, ret=77
12852 11:19:12.884443 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12853 11:19:12.894622 Opened device: /<8>[ 28.587096] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-idle-hang RESULT=skip>
12854 11:19:12.895195 dev/dri/card0
12855 11:19:12.895834 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-idle-hang RESULT=skip
12857 11:19:12.897617 No KMS driver or no outputs, pipes: 8, outputs: 0
12858 11:19:12.904295 [1mSubtest pipe-D-query-idle-hang: SKIP (0.000s)[0m
12859 11:19:12.915720 <14>[ 28.612276] [IGT] kms_vblank: executing
12860 11:19:12.922464 IGT-Version: 1.2<14>[ 28.617294] [IGT] kms_vblank: exiting, ret=77
12861 11:19:12.925601 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12862 11:19:12.928891 Opened device: /dev/dri/card0
12863 11:19:12.935852 N<8>[ 28.628440] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked RESULT=skip>
12864 11:19:12.936679 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked RESULT=skip
12866 11:19:12.938490 o KMS driver or no outputs, pipes: 8, outputs: 0
12867 11:19:12.945708 [1mSubtest pipe-D-query-forked: SKIP (0.000s)[0m
12868 11:19:12.958355 <14>[ 28.655048] [IGT] kms_vblank: executing
12869 11:19:12.964948 IGT-Version: 1.2<14>[ 28.660330] [IGT] kms_vblank: exiting, ret=77
12870 11:19:12.968151 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12871 11:19:12.971473 Opened device: /dev/dri/card0
12872 11:19:12.978323 N<8>[ 28.671699] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-hang RESULT=skip>
12873 11:19:12.978996 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-hang RESULT=skip
12875 11:19:12.984562 o KMS driver or no outputs, pipes: 8, outputs: 0
12876 11:19:12.988006 [1mSubtest pipe-D-query-forked-hang: SKIP (0.000s)[0m
12877 11:19:13.002028 <14>[ 28.698812] [IGT] kms_vblank: executing
12878 11:19:13.008559 IGT-Version: 1.2<14>[ 28.704019] [IGT] kms_vblank: exiting, ret=77
12879 11:19:13.011782 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12880 11:19:13.022199 Opened device: /<8>[ 28.714609] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-busy RESULT=skip>
12881 11:19:13.022766 dev/dri/card0
12882 11:19:13.023412 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-busy RESULT=skip
12884 11:19:13.025198 No KMS driver or no outputs, pipes: 8, outputs: 0
12885 11:19:13.031903 [1mSubtest pipe-D-query-busy: SKIP (0.000s)[0m
12886 11:19:13.042542 <14>[ 28.739431] [IGT] kms_vblank: executing
12887 11:19:13.049749 IGT-Version: 1.2<14>[ 28.744477] [IGT] kms_vblank: exiting, ret=77
12888 11:19:13.052725 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12889 11:19:13.062559 Opened device: /<8>[ 28.755464] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-busy-hang RESULT=skip>
12890 11:19:13.063134 dev/dri/card0
12891 11:19:13.063841 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-busy-hang RESULT=skip
12893 11:19:13.065472 No KMS driver or no outputs, pipes: 8, outputs: 0
12894 11:19:13.072624 [1mSubtest pipe-D-query-busy-hang: SKIP (0.000s)[0m
12895 11:19:13.084581 <14>[ 28.781057] [IGT] kms_vblank: executing
12896 11:19:13.090706 IGT-Version: 1.2<14>[ 28.786363] [IGT] kms_vblank: exiting, ret=77
12897 11:19:13.094531 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12898 11:19:13.097617 Opened device: /dev/dri/card0
12899 11:19:13.104256 N<8>[ 28.797414] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-busy RESULT=skip>
12900 11:19:13.105127 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-busy RESULT=skip
12902 11:19:13.111184 o KMS driver or no outputs, pipes: 8, outputs: 0
12903 11:19:13.113897 [1mSubtest pipe-D-query-forked-busy: SKIP (0.000s)[0m
12904 11:19:13.127756 <14>[ 28.824654] [IGT] kms_vblank: executing
12905 11:19:13.134732 IGT-Version: 1.2<14>[ 28.830255] [IGT] kms_vblank: exiting, ret=77
12906 11:19:13.137666 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12907 11:19:13.141396 Opened device: /dev/dri/card0
12908 11:19:13.148424 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-query-forked-busy-hang RESULT=skip
12910 11:19:13.150747 N<8>[ 28.841676] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-query-forked-busy-hang RESULT=skip>
12911 11:19:13.154857 o KMS driver or no outputs, pipes: 8, outputs: 0
12912 11:19:13.160974 [1mSubtest pipe-D-query-forked-busy-hang: SKIP (0.000s)[0m
12913 11:19:13.172823 <14>[ 28.869229] [IGT] kms_vblank: executing
12914 11:19:13.179135 IGT-Version: 1.2<14>[ 28.874209] [IGT] kms_vblank: exiting, ret=77
12915 11:19:13.182593 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12916 11:19:13.185486 Opened device: /dev/dri/card0
12917 11:19:13.192467 N<8>[ 28.885611] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-idle RESULT=skip>
12918 11:19:13.193302 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-idle RESULT=skip
12920 11:19:13.195826 o KMS driver or no outputs, pipes: 8, outputs: 0
12921 11:19:13.201964 [1mSubtest pipe-D-wait-idle: SKIP (0.000s)[0m
12922 11:19:13.214393 <14>[ 28.911028] [IGT] kms_vblank: executing
12923 11:19:13.220672 IGT-Version: 1.2<14>[ 28.916148] [IGT] kms_vblank: exiting, ret=77
12924 11:19:13.224158 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12925 11:19:13.227833 Opened device: /dev/dri/card0
12926 11:19:13.234367 N<8>[ 28.927599] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-idle-hang RESULT=skip>
12927 11:19:13.235183 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-idle-hang RESULT=skip
12929 11:19:13.237383 o KMS driver or no outputs, pipes: 8, outputs: 0
12930 11:19:13.244208 [1mSubtest pipe-D-wait-idle-hang: SKIP (0.000s)[0m
12931 11:19:13.257885 <14>[ 28.954312] [IGT] kms_vblank: executing
12932 11:19:13.264266 IGT-Version: 1.2<14>[ 28.959691] [IGT] kms_vblank: exiting, ret=77
12933 11:19:13.267775 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12934 11:19:13.271219 Opened device: /dev/dri/card0
12935 11:19:13.277690 N<8>[ 28.970483] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked RESULT=skip>
12936 11:19:13.278516 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked RESULT=skip
12938 11:19:13.280801 o KMS driver or no outputs, pipes: 8, outputs: 0
12939 11:19:13.287422 [1mSubtest pipe-D-wait-forked: SKIP (0.000s)[0m
12940 11:19:13.299990 <14>[ 28.996675] [IGT] kms_vblank: executing
12941 11:19:13.306507 IGT-Version: 1.2<14>[ 29.001650] [IGT] kms_vblank: exiting, ret=77
12942 11:19:13.309663 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12943 11:19:13.313144 Opened device: /dev/dri/card0
12944 11:19:13.319702 N<8>[ 29.013020] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-hang RESULT=skip>
12945 11:19:13.320540 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-hang RESULT=skip
12947 11:19:13.323387 o KMS driver or no outputs, pipes: 8, outputs: 0
12948 11:19:13.329501 [1mSubtest pipe-D-wait-forked-hang: SKIP (0.000s)[0m
12949 11:19:13.342634 <14>[ 29.039331] [IGT] kms_vblank: executing
12950 11:19:13.349386 IGT-Version: 1.2<14>[ 29.044339] [IGT] kms_vblank: exiting, ret=77
12951 11:19:13.352754 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12952 11:19:13.355856 Opened device: /dev/dri/card0
12953 11:19:13.362731 N<8>[ 29.055876] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-busy RESULT=skip>
12954 11:19:13.363505 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-busy RESULT=skip
12956 11:19:13.365505 o KMS driver or no outputs, pipes: 8, outputs: 0
12957 11:19:13.372284 [1mSubtest pipe-D-wait-busy: SKIP (0.000s)[0m
12958 11:19:13.384517 <14>[ 29.081116] [IGT] kms_vblank: executing
12959 11:19:13.391175 IGT-Version: 1.2<14>[ 29.086145] [IGT] kms_vblank: exiting, ret=77
12960 11:19:13.394650 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12961 11:19:13.397647 Opened device: /dev/dri/card0
12962 11:19:13.404273 N<8>[ 29.097296] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-busy-hang RESULT=skip>
12963 11:19:13.405163 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-busy-hang RESULT=skip
12965 11:19:13.407575 o KMS driver or no outputs, pipes: 8, outputs: 0
12966 11:19:13.414279 [1mSubtest pipe-D-wait-busy-hang: SKIP (0.000s)[0m
12967 11:19:13.427274 <14>[ 29.123477] [IGT] kms_vblank: executing
12968 11:19:13.433455 IGT-Version: 1.2<14>[ 29.128557] [IGT] kms_vblank: exiting, ret=77
12969 11:19:13.436901 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12970 11:19:13.440078 Opened device: /dev/dri/card0
12971 11:19:13.446509 N<8>[ 29.139775] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-busy RESULT=skip>
12972 11:19:13.447224 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-busy RESULT=skip
12974 11:19:13.450047 o KMS driver or no outputs, pipes: 8, outputs: 0
12975 11:19:13.456100 [1mSubtest pipe-D-wait-forked-busy: SKIP (0.000s)[0m
12976 11:19:13.469722 <14>[ 29.166565] [IGT] kms_vblank: executing
12977 11:19:13.476536 IGT-Version: 1.2<14>[ 29.171909] [IGT] kms_vblank: exiting, ret=77
12978 11:19:13.480095 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12979 11:19:13.483309 Opened device: /dev/dri/card0
12980 11:19:13.489458 N<8>[ 29.182642] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-wait-forked-busy-hang RESULT=skip>
12981 11:19:13.490342 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-wait-forked-busy-hang RESULT=skip
12983 11:19:13.495951 o KMS driver or no outputs, pipes: 8, outputs: 0
12984 11:19:13.499313 [1mSubtest pipe-D-wait-forked-busy-hang: SKIP (0.000s)[0m
12985 11:19:13.513392 <14>[ 29.210041] [IGT] kms_vblank: executing
12986 11:19:13.519448 IGT-Version: 1.2<14>[ 29.215142] [IGT] kms_vblank: exiting, ret=77
12987 11:19:13.523186 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12988 11:19:13.526649 Opened device: /dev/dri/card0
12989 11:19:13.533483 N<8>[ 29.226429] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-idle RESULT=skip>
12990 11:19:13.534326 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-idle RESULT=skip
12992 11:19:13.539922 o KMS driver or no outputs, pipes: 8, outputs: 0
12993 11:19:13.543208 [1mSubtest pipe-D-ts-continuation-idle: SKIP (0.000s)[0m
12994 11:19:13.556799 <14>[ 29.253030] [IGT] kms_vblank: executing
12995 11:19:13.562951 IGT-Version: 1.2<14>[ 29.258056] [IGT] kms_vblank: exiting, ret=77
12996 11:19:13.566384 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
12997 11:19:13.576101 Opened device: /<8>[ 29.268919] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-idle-hang RESULT=skip>
12998 11:19:13.576664 dev/dri/card0
12999 11:19:13.577360 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-idle-hang RESULT=skip
13001 11:19:13.582959 No KMS driver or no outputs, pipes: 8, outputs: 0
13002 11:19:13.586086 [1mSubtest pipe-D-ts-continuation-idle-hang: SKIP (0.000s)[0m
13003 11:19:13.597839 <14>[ 29.294689] [IGT] kms_vblank: executing
13004 11:19:13.604682 IGT-Version: 1.2<14>[ 29.299883] [IGT] kms_vblank: exiting, ret=77
13005 11:19:13.608191 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13006 11:19:13.617659 Opened device: /<8>[ 29.310559] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-dpms-rpm RESULT=skip>
13007 11:19:13.618185 dev/dri/card0
13008 11:19:13.618789 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-dpms-rpm RESULT=skip
13010 11:19:13.624649 No KMS driver or no outputs, pipes: 8, outputs: 0
13011 11:19:13.627615 [1mSubtest pipe-D-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13012 11:19:13.640072 <14>[ 29.336543] [IGT] kms_vblank: executing
13013 11:19:13.646494 IGT-Version: 1.2<14>[ 29.341684] [IGT] kms_vblank: exiting, ret=77
13014 11:19:13.650058 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13015 11:19:13.659728 Opened device: /<8>[ 29.352562] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-dpms-suspend RESULT=skip>
13016 11:19:13.660527 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-dpms-suspend RESULT=skip
13018 11:19:13.662957 dev/dri/card0
13019 11:19:13.666111 No KMS driver or no outputs, pipes: 8, outputs: 0
13020 11:19:13.672511 [1mSubtest pipe-D-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13021 11:19:13.683057 <14>[ 29.379481] [IGT] kms_vblank: executing
13022 11:19:13.689420 IGT-Version: 1.2<14>[ 29.384452] [IGT] kms_vblank: exiting, ret=77
13023 11:19:13.692391 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13024 11:19:13.695473 Opened device: /dev/dri/card0
13025 11:19:13.702953 N<8>[ 29.395910] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-suspend RESULT=skip>
13026 11:19:13.703747 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-suspend RESULT=skip
13028 11:19:13.709116 o KMS driver or no outputs, pipes: 8, outputs: 0
13029 11:19:13.711835 [1mSubtest pipe-D-ts-continuation-suspend: SKIP (0.000s)[0m
13030 11:19:13.725710 <14>[ 29.422571] [IGT] kms_vblank: executing
13031 11:19:13.732161 IGT-Version: 1.2<14>[ 29.427775] [IGT] kms_vblank: exiting, ret=77
13032 11:19:13.735856 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13033 11:19:13.745241 Opened device: /<8>[ 29.438354] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset RESULT=skip>
13034 11:19:13.745760 dev/dri/card0
13035 11:19:13.746361 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset RESULT=skip
13037 11:19:13.752208 No KMS driver or no outputs, pipes: 8, outputs: 0
13038 11:19:13.755797 [1mSubtest pipe-D-ts-continuation-modeset: SKIP (0.000s)[0m
13039 11:19:13.767606 <14>[ 29.464131] [IGT] kms_vblank: executing
13040 11:19:13.773708 IGT-Version: 1.2<14>[ 29.469115] [IGT] kms_vblank: exiting, ret=77
13041 11:19:13.777075 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13042 11:19:13.780696 Opened device: /dev/dri/card0
13043 11:19:13.786689 N<8>[ 29.480083] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset-hang RESULT=skip>
13044 11:19:13.787004 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset-hang RESULT=skip
13046 11:19:13.793333 o KMS driver or no outputs, pipes: 8, outputs: 0
13047 11:19:13.799839 [1mSubtest pipe-D-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13048 11:19:13.810980 <14>[ 29.508155] [IGT] kms_vblank: executing
13049 11:19:13.817857 IGT-Version: 1.2<14>[ 29.513213] [IGT] kms_vblank: exiting, ret=77
13050 11:19:13.820958 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13051 11:19:13.824166 Opened device: /dev/dri/card0
13052 11:19:13.831025 N<8>[ 29.524639] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-D-ts-continuation-modeset-rpm RESULT=skip>
13053 11:19:13.831697 Received signal: <TESTCASE> TEST_CASE_ID=pipe-D-ts-continuation-modeset-rpm RESULT=skip
13055 11:19:13.837620 o KMS driver or no outputs, pipes: 8, outputs: 0
13056 11:19:13.844060 [1mSubtest pipe-D-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13057 11:19:13.855909 <14>[ 29.552533] [IGT] kms_vblank: executing
13058 11:19:13.862388 IGT-Version: 1.2<14>[ 29.557822] [IGT] kms_vblank: exiting, ret=77
13059 11:19:13.865661 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13060 11:19:13.869126 Opened device: /dev/dri/card0
13061 11:19:13.875809 N<8>[ 29.568929] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-accuracy-idle RESULT=skip>
13062 11:19:13.876602 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-accuracy-idle RESULT=skip
13064 11:19:13.881864 o KMS driver or no outputs, pipes: 8, outputs: 0
13065 11:19:13.885239 [1mSubtest pipe-E-accuracy-idle: SKIP (0.000s)[0m
13066 11:19:13.899515 <14>[ 29.596047] [IGT] kms_vblank: executing
13067 11:19:13.905909 IGT-Version: 1.2<14>[ 29.601278] [IGT] kms_vblank: exiting, ret=77
13068 11:19:13.909054 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13069 11:19:13.912701 Opened device: /dev/dri/card0
13070 11:19:13.919077 N<8>[ 29.612255] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-idle RESULT=skip>
13071 11:19:13.919908 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-idle RESULT=skip
13073 11:19:13.922274 o KMS driver or no outputs, pipes: 8, outputs: 0
13074 11:19:13.929219 [1mSubtest pipe-E-query-idle: SKIP (0.000s)[0m
13075 11:19:13.941247 <14>[ 29.638227] [IGT] kms_vblank: executing
13076 11:19:13.948057 IGT-Version: 1.2<14>[ 29.643355] [IGT] kms_vblank: exiting, ret=77
13077 11:19:13.951581 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13078 11:19:13.961293 Opened device: /<8>[ 29.654136] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-idle-hang RESULT=skip>
13079 11:19:13.961836 dev/dri/card0
13080 11:19:13.962544 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-idle-hang RESULT=skip
13082 11:19:13.964124 No KMS driver or no outputs, pipes: 8, outputs: 0
13083 11:19:13.971117 [1mSubtest pipe-E-query-idle-hang: SKIP (0.000s)[0m
13084 11:19:13.982921 <14>[ 29.679140] [IGT] kms_vblank: executing
13085 11:19:13.988980 IGT-Version: 1.2<14>[ 29.684240] [IGT] kms_vblank: exiting, ret=77
13086 11:19:13.992069 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13087 11:19:14.001916 Opened device: /<8>[ 29.695192] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked RESULT=skip>
13088 11:19:14.002386 dev/dri/card0
13089 11:19:14.003075 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked RESULT=skip
13091 11:19:14.005469 No KMS driver or no outputs, pipes: 8, outputs: 0
13092 11:19:14.011885 [1mSubtest pipe-E-query-forked: SKIP (0.000s)[0m
13093 11:19:14.024361 <14>[ 29.720918] [IGT] kms_vblank: executing
13094 11:19:14.031132 IGT-Version: 1.2<14>[ 29.726425] [IGT] kms_vblank: exiting, ret=77
13095 11:19:14.034393 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13096 11:19:14.037621 Opened device: /dev/dri/card0
13097 11:19:14.044237 N<8>[ 29.737685] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-hang RESULT=skip>
13098 11:19:14.045088 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-hang RESULT=skip
13100 11:19:14.050605 o KMS driver or no outputs, pipes: 8, outputs: 0
13101 11:19:14.054078 [1mSubtest pipe-E-query-forked-hang: SKIP (0.000s)[0m
13102 11:19:14.067267 <14>[ 29.763997] [IGT] kms_vblank: executing
13103 11:19:14.073933 IGT-Version: 1.2<14>[ 29.769095] [IGT] kms_vblank: exiting, ret=77
13104 11:19:14.077187 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13105 11:19:14.080262 Opened device: /dev/dri/card0
13106 11:19:14.087228 N<8>[ 29.780165] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-busy RESULT=skip>
13107 11:19:14.088047 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-busy RESULT=skip
13109 11:19:14.090233 o KMS driver or no outputs, pipes: 8, outputs: 0
13110 11:19:14.096465 [1mSubtest pipe-E-query-busy: SKIP (0.000s)[0m
13111 11:19:14.108871 <14>[ 29.806051] [IGT] kms_vblank: executing
13112 11:19:14.115914 IGT-Version: 1.2<14>[ 29.811082] [IGT] kms_vblank: exiting, ret=77
13113 11:19:14.119358 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13114 11:19:14.128943 Opened device: /<8>[ 29.821854] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-busy-hang RESULT=skip>
13115 11:19:14.129475 dev/dri/card0
13116 11:19:14.130181 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-busy-hang RESULT=skip
13118 11:19:14.131991 No KMS driver or no outputs, pipes: 8, outputs: 0
13119 11:19:14.139201 [1mSubtest pipe-E-query-busy-hang: SKIP (0.000s)[0m
13120 11:19:14.149970 <14>[ 29.846848] [IGT] kms_vblank: executing
13121 11:19:14.156707 IGT-Version: 1.2<14>[ 29.852002] [IGT] kms_vblank: exiting, ret=77
13122 11:19:14.159730 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13123 11:19:14.163291 Opened device: /dev/dri/card0
13124 11:19:14.169826 N<8>[ 29.862857] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-busy RESULT=skip>
13125 11:19:14.170615 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-busy RESULT=skip
13127 11:19:14.176525 o KMS driver or no outputs, pipes: 8, outputs: 0
13128 11:19:14.179789 [1mSubtest pipe-E-query-forked-busy: SKIP (0.000s)[0m
13129 11:19:14.192559 <14>[ 29.889365] [IGT] kms_vblank: executing
13130 11:19:14.199255 IGT-Version: 1.2<14>[ 29.894355] [IGT] kms_vblank: exiting, ret=77
13131 11:19:14.202312 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13132 11:19:14.205687 Opened device: /dev/dri/card0
13133 11:19:14.212366 N<8>[ 29.905550] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-query-forked-busy-hang RESULT=skip>
13134 11:19:14.213192 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-query-forked-busy-hang RESULT=skip
13136 11:19:14.219020 o KMS driver or no outputs, pipes: 8, outputs: 0
13137 11:19:14.222186 [1mSubtest pipe-E-query-forked-busy-hang: SKIP (0.000s)[0m
13138 11:19:14.235311 <14>[ 29.932192] [IGT] kms_vblank: executing
13139 11:19:14.242075 IGT-Version: 1.2<14>[ 29.937177] [IGT] kms_vblank: exiting, ret=77
13140 11:19:14.245258 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13141 11:19:14.248463 Opened device: /dev/dri/card0
13142 11:19:14.255012 N<8>[ 29.948280] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-idle RESULT=skip>
13143 11:19:14.255814 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-idle RESULT=skip
13145 11:19:14.258284 o KMS driver or no outputs, pipes: 8, outputs: 0
13146 11:19:14.265192 [1mSubtest pipe-E-wait-idle: SKIP (0.000s)[0m
13147 11:19:14.277427 <14>[ 29.974380] [IGT] kms_vblank: executing
13148 11:19:14.284135 IGT-Version: 1.2<14>[ 29.979483] [IGT] kms_vblank: exiting, ret=77
13149 11:19:14.287199 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13150 11:19:14.297180 Opened device: /<8>[ 29.990267] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-idle-hang RESULT=skip>
13151 11:19:14.297613 dev/dri/card0
13152 11:19:14.298208 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-idle-hang RESULT=skip
13154 11:19:14.300624 No KMS driver or no outputs, pipes: 8, outputs: 0
13155 11:19:14.307056 [1mSubtest pipe-E-wait-idle-hang: SKIP (0.000s)[0m
13156 11:19:14.318185 <14>[ 30.015330] [IGT] kms_vblank: executing
13157 11:19:14.324981 IGT-Version: 1.2<14>[ 30.020417] [IGT] kms_vblank: exiting, ret=77
13158 11:19:14.328277 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13159 11:19:14.331659 Opened device: /dev/dri/card0
13160 11:19:14.338239 N<8>[ 30.031379] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked RESULT=skip>
13161 11:19:14.339042 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked RESULT=skip
13163 11:19:14.341235 o KMS driver or no outputs, pipes: 8, outputs: 0
13164 11:19:14.348156 [1mSubtest pipe-E-wait-forked: SKIP (0.000s)[0m
13165 11:19:14.360281 <14>[ 30.057250] [IGT] kms_vblank: executing
13166 11:19:14.366763 IGT-Version: 1.2<14>[ 30.062267] [IGT] kms_vblank: exiting, ret=77
13167 11:19:14.370502 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13168 11:19:14.373439 Opened device: /dev/dri/card0
13169 11:19:14.380368 N<8>[ 30.073294] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-hang RESULT=skip>
13170 11:19:14.381212 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-hang RESULT=skip
13172 11:19:14.386523 o KMS driver or no outputs, pipes: 8, outputs: 0
13173 11:19:14.389798 [1mSubtest pipe-E-wait-forked-hang: SKIP (0.000s)[0m
13174 11:19:14.403022 <14>[ 30.099745] [IGT] kms_vblank: executing
13175 11:19:14.409585 IGT-Version: 1.2<14>[ 30.104738] [IGT] kms_vblank: exiting, ret=77
13176 11:19:14.412902 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13177 11:19:14.416217 Opened device: /dev/dri/card0
13178 11:19:14.422542 N<8>[ 30.115807] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-busy RESULT=skip>
13179 11:19:14.423348 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-busy RESULT=skip
13181 11:19:14.426068 o KMS driver or no outputs, pipes: 8, outputs: 0
13182 11:19:14.432524 [1mSubtest pipe-E-wait-busy: SKIP (0.000s)[0m
13183 11:19:14.444951 <14>[ 30.141575] [IGT] kms_vblank: executing
13184 11:19:14.451512 IGT-Version: 1.2<14>[ 30.146596] [IGT] kms_vblank: exiting, ret=77
13185 11:19:14.454643 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13186 11:19:14.464911 Opened device: /<8>[ 30.157559] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-busy-hang RESULT=skip>
13187 11:19:14.465441 dev/dri/card0
13188 11:19:14.466047 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-busy-hang RESULT=skip
13190 11:19:14.467811 No KMS driver or no outputs, pipes: 8, outputs: 0
13191 11:19:14.474503 [1mSubtest pipe-E-wait-busy-hang: SKIP (0.000s)[0m
13192 11:19:14.486820 <14>[ 30.183329] [IGT] kms_vblank: executing
13193 11:19:14.493401 IGT-Version: 1.2<14>[ 30.188370] [IGT] kms_vblank: exiting, ret=77
13194 11:19:14.496923 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13195 11:19:14.499887 Opened device: /dev/dri/card0
13196 11:19:14.506306 N<8>[ 30.199654] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-busy RESULT=skip>
13197 11:19:14.507103 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-busy RESULT=skip
13199 11:19:14.509364 o KMS driver or no outputs, pipes: 8, outputs: 0
13200 11:19:14.515968 [1mSubtest pipe-E-wait-forked-busy: SKIP (0.000s)[0m
13201 11:19:14.529028 <14>[ 30.225698] [IGT] kms_vblank: executing
13202 11:19:14.535612 IGT-Version: 1.2<14>[ 30.230705] [IGT] kms_vblank: exiting, ret=77
13203 11:19:14.539135 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13204 11:19:14.541957 Opened device: /dev/dri/card0
13205 11:19:14.548718 N<8>[ 30.241676] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-wait-forked-busy-hang RESULT=skip>
13206 11:19:14.549545 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-wait-forked-busy-hang RESULT=skip
13208 11:19:14.555341 o KMS driver or no outputs, pipes: 8, outputs: 0
13209 11:19:14.558376 [1mSubtest pipe-E-wait-forked-busy-hang: SKIP (0.000s)[0m
13210 11:19:14.572405 <14>[ 30.269236] [IGT] kms_vblank: executing
13211 11:19:14.578899 IGT-Version: 1.2<14>[ 30.274516] [IGT] kms_vblank: exiting, ret=77
13212 11:19:14.582132 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13213 11:19:14.585507 Opened device: /dev/dri/card0
13214 11:19:14.592009 N<8>[ 30.285497] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-idle RESULT=skip>
13215 11:19:14.592837 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-idle RESULT=skip
13217 11:19:14.598414 o KMS driver or no outputs, pipes: 8, outputs: 0
13218 11:19:14.601909 [1mSubtest pipe-E-ts-continuation-idle: SKIP (0.000s)[0m
13219 11:19:14.616352 <14>[ 30.313235] [IGT] kms_vblank: executing
13220 11:19:14.622633 IGT-Version: 1.2<14>[ 30.318491] [IGT] kms_vblank: exiting, ret=77
13221 11:19:14.626492 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13222 11:19:14.629555 Opened device: /dev/dri/card0
13223 11:19:14.636458 N<8>[ 30.329475] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-idle-hang RESULT=skip>
13224 11:19:14.637333 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-idle-hang RESULT=skip
13226 11:19:14.642792 o KMS driver or no outputs, pipes: 8, outputs: 0
13227 11:19:14.645845 [1mSubtest pipe-E-ts-continuation-idle-hang: SKIP (0.000s)[0m
13228 11:19:14.659576 <14>[ 30.356760] [IGT] kms_vblank: executing
13229 11:19:14.666450 IGT-Version: 1.2<14>[ 30.361915] [IGT] kms_vblank: exiting, ret=77
13230 11:19:14.669801 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13231 11:19:14.672978 Opened device: /dev/dri/card0
13232 11:19:14.679852 N<8>[ 30.372828] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-dpms-rpm RESULT=skip>
13233 11:19:14.680642 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-dpms-rpm RESULT=skip
13235 11:19:14.686716 o KMS driver or no outputs, pipes: 8, outputs: 0
13236 11:19:14.689447 [1mSubtest pipe-E-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13237 11:19:14.704059 <14>[ 30.400994] [IGT] kms_vblank: executing
13238 11:19:14.710938 IGT-Version: 1.2<14>[ 30.406170] [IGT] kms_vblank: exiting, ret=77
13239 11:19:14.713683 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13240 11:19:14.717382 Opened device: /dev/dri/card0
13241 11:19:14.723989 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-dpms-suspend RESULT=skip
13243 11:19:14.727377 N<8>[ 30.417194] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-dpms-suspend RESULT=skip>
13244 11:19:14.730297 o KMS driver or no outputs, pipes: 8, outputs: 0
13245 11:19:14.737191 [1mSubtest pipe-E-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13246 11:19:14.749117 <14>[ 30.445764] [IGT] kms_vblank: executing
13247 11:19:14.755510 IGT-Version: 1.2<14>[ 30.451347] [IGT] kms_vblank: exiting, ret=77
13248 11:19:14.758871 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13249 11:19:14.761675 Opened device: /dev/dri/card0
13250 11:19:14.768503 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-suspend RESULT=skip
13252 11:19:14.771485 N<8>[ 30.462485] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-suspend RESULT=skip>
13253 11:19:14.775007 o KMS driver or no outputs, pipes: 8, outputs: 0
13254 11:19:14.781214 [1mSubtest pipe-E-ts-continuation-suspend: SKIP (0.000s)[0m
13255 11:19:14.792518 <14>[ 30.489404] [IGT] kms_vblank: executing
13256 11:19:14.799510 IGT-Version: 1.2<14>[ 30.494428] [IGT] kms_vblank: exiting, ret=77
13257 11:19:14.802288 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13258 11:19:14.806047 Opened device: /dev/dri/card0
13259 11:19:14.812416 N<8>[ 30.505553] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset RESULT=skip>
13260 11:19:14.813263 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset RESULT=skip
13262 11:19:14.819153 o KMS driver or no outputs, pipes: 8, outputs: 0
13263 11:19:14.822209 [1mSubtest pipe-E-ts-continuation-modeset: SKIP (0.000s)[0m
13264 11:19:14.836553 <14>[ 30.533439] [IGT] kms_vblank: executing
13265 11:19:14.843299 IGT-Version: 1.2<14>[ 30.538632] [IGT] kms_vblank: exiting, ret=77
13266 11:19:14.846478 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13267 11:19:14.849838 Opened device: /dev/dri/card0
13268 11:19:14.856949 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset-hang RESULT=skip
13270 11:19:14.859383 N<8>[ 30.549631] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset-hang RESULT=skip>
13271 11:19:14.862875 o KMS driver or no outputs, pipes: 8, outputs: 0
13272 11:19:14.869111 [1mSubtest pipe-E-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13273 11:19:14.881348 <14>[ 30.578114] [IGT] kms_vblank: executing
13274 11:19:14.887985 IGT-Version: 1.2<14>[ 30.583329] [IGT] kms_vblank: exiting, ret=77
13275 11:19:14.891293 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13276 11:19:14.900713 Opened device: /<8>[ 30.594094] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-E-ts-continuation-modeset-rpm RESULT=skip>
13277 11:19:14.901303 dev/dri/card0
13278 11:19:14.901920 Received signal: <TESTCASE> TEST_CASE_ID=pipe-E-ts-continuation-modeset-rpm RESULT=skip
13280 11:19:14.907502 No KMS driver or no outputs, pipes: 8, outputs: 0
13281 11:19:14.914273 [1mSubtest pipe-E-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13282 11:19:14.923756 <14>[ 30.620326] [IGT] kms_vblank: executing
13283 11:19:14.930238 IGT-Version: 1.2<14>[ 30.625409] [IGT] kms_vblank: exiting, ret=77
13284 11:19:14.933698 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13285 11:19:14.936828 Opened device: /dev/dri/card0
13286 11:19:14.943546 N<8>[ 30.636452] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-accuracy-idle RESULT=skip>
13287 11:19:14.944347 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-accuracy-idle RESULT=skip
13289 11:19:14.947110 o KMS driver or no outputs, pipes: 8, outputs: 0
13290 11:19:14.953230 [1mSubtest pipe-F-accuracy-idle: SKIP (0.000s)[0m
13291 11:19:14.965681 <14>[ 30.662550] [IGT] kms_vblank: executing
13292 11:19:14.972321 IGT-Version: 1.2<14>[ 30.667734] [IGT] kms_vblank: exiting, ret=77
13293 11:19:14.975791 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13294 11:19:14.985523 Opened device: /<8>[ 30.678489] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-idle RESULT=skip>
13295 11:19:14.986086 dev/dri/card0
13296 11:19:14.986701 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-idle RESULT=skip
13298 11:19:14.988593 No KMS driver or no outputs, pipes: 8, outputs: 0
13299 11:19:14.995233 [1mSubtest pipe-F-query-idle: SKIP (0.000s)[0m
13300 11:19:15.005876 <14>[ 30.702814] [IGT] kms_vblank: executing
13301 11:19:15.012856 IGT-Version: 1.2<14>[ 30.708115] [IGT] kms_vblank: exiting, ret=77
13302 11:19:15.015892 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13303 11:19:15.025640 Opened device: /<8>[ 30.718974] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-idle-hang RESULT=skip>
13304 11:19:15.026179 dev/dri/card0
13305 11:19:15.026784 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-idle-hang RESULT=skip
13307 11:19:15.032540 No KMS driver or no outputs, pipes: 8, outputs: 0
13308 11:19:15.035495 [1mSubtest pipe-F-query-idle-hang: SKIP (0.000s)[0m
13309 11:19:15.048342 <14>[ 30.745029] [IGT] kms_vblank: executing
13310 11:19:15.054699 IGT-Version: 1.2<14>[ 30.750226] [IGT] kms_vblank: exiting, ret=77
13311 11:19:15.057727 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13312 11:19:15.060890 Opened device: /dev/dri/card0
13313 11:19:15.067969 N<8>[ 30.761490] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked RESULT=skip>
13314 11:19:15.068815 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked RESULT=skip
13316 11:19:15.071077 o KMS driver or no outputs, pipes: 8, outputs: 0
13317 11:19:15.077685 [1mSubtest pipe-F-query-forked: SKIP (0.000s)[0m
13318 11:19:15.090309 <14>[ 30.787229] [IGT] kms_vblank: executing
13319 11:19:15.096833 IGT-Version: 1.2<14>[ 30.792328] [IGT] kms_vblank: exiting, ret=77
13320 11:19:15.100312 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13321 11:19:15.104030 Opened device: /dev/dri/card0
13322 11:19:15.110131 N<8>[ 30.803624] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-hang RESULT=skip>
13323 11:19:15.110991 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-hang RESULT=skip
13325 11:19:15.116685 o KMS driver or no outputs, pipes: 8, outputs: 0
13326 11:19:15.120342 [1mSubtest pipe-F-query-forked-hang: SKIP (0.000s)[0m
13327 11:19:15.133940 <14>[ 30.830716] [IGT] kms_vblank: executing
13328 11:19:15.140801 IGT-Version: 1.2<14>[ 30.836096] [IGT] kms_vblank: exiting, ret=77
13329 11:19:15.143951 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13330 11:19:15.147210 Opened device: /dev/dri/card0
13331 11:19:15.153713 N<8>[ 30.847059] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-busy RESULT=skip>
13332 11:19:15.154526 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-busy RESULT=skip
13334 11:19:15.157147 o KMS driver or no outputs, pipes: 8, outputs: 0
13335 11:19:15.163157 [1mSubtest pipe-F-query-busy: SKIP (0.000s)[0m
13336 11:19:15.176019 <14>[ 30.872913] [IGT] kms_vblank: executing
13337 11:19:15.182690 IGT-Version: 1.2<14>[ 30.878011] [IGT] kms_vblank: exiting, ret=77
13338 11:19:15.185645 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13339 11:19:15.195700 Opened device: /<8>[ 30.888883] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-busy-hang RESULT=skip>
13340 11:19:15.196230 dev/dri/card0
13341 11:19:15.196858 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-busy-hang RESULT=skip
13343 11:19:15.198911 No KMS driver or no outputs, pipes: 8, outputs: 0
13344 11:19:15.205474 [1mSubtest pipe-F-query-busy-hang: SKIP (0.000s)[0m
13345 11:19:15.218101 <14>[ 30.914845] [IGT] kms_vblank: executing
13346 11:19:15.224588 IGT-Version: 1.2<14>[ 30.920051] [IGT] kms_vblank: exiting, ret=77
13347 11:19:15.227585 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13348 11:19:15.231294 Opened device: /dev/dri/card0
13349 11:19:15.237687 N<8>[ 30.930953] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-busy RESULT=skip>
13350 11:19:15.238492 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-busy RESULT=skip
13352 11:19:15.244287 o KMS driver or no outputs, pipes: 8, outputs: 0
13353 11:19:15.247539 [1mSubtest pipe-F-query-forked-busy: SKIP (0.000s)[0m
13354 11:19:15.261795 <14>[ 30.958603] [IGT] kms_vblank: executing
13355 11:19:15.268329 IGT-Version: 1.2<14>[ 30.963975] [IGT] kms_vblank: exiting, ret=77
13356 11:19:15.271783 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13357 11:19:15.281665 Opened device: /<8>[ 30.974635] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-query-forked-busy-hang RESULT=skip>
13358 11:19:15.282207 dev/dri/card0
13359 11:19:15.282813 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-query-forked-busy-hang RESULT=skip
13361 11:19:15.288230 No KMS driver or no outputs, pipes: 8, outputs: 0
13362 11:19:15.291340 [1mSubtest pipe-F-query-forked-busy-hang: SKIP (0.000s)[0m
13363 11:19:15.304550 <14>[ 31.001510] [IGT] kms_vblank: executing
13364 11:19:15.310919 IGT-Version: 1.2<14>[ 31.006728] [IGT] kms_vblank: exiting, ret=77
13365 11:19:15.314672 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13366 11:19:15.317664 Opened device: /dev/dri/card0
13367 11:19:15.324401 N<8>[ 31.017945] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-idle RESULT=skip>
13368 11:19:15.325228 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-idle RESULT=skip
13370 11:19:15.327684 o KMS driver or no outputs, pipes: 8, outputs: 0
13371 11:19:15.334055 [1mSubtest pipe-F-wait-idle: SKIP (0.000s)[0m
13372 11:19:15.346510 <14>[ 31.043588] [IGT] kms_vblank: executing
13373 11:19:15.353194 IGT-Version: 1.2<14>[ 31.048633] [IGT] kms_vblank: exiting, ret=77
13374 11:19:15.356677 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13375 11:19:15.359644 Opened device: /dev/dri/card0
13376 11:19:15.366627 N<8>[ 31.059955] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-idle-hang RESULT=skip>
13377 11:19:15.367441 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-idle-hang RESULT=skip
13379 11:19:15.369623 o KMS driver or no outputs, pipes: 8, outputs: 0
13380 11:19:15.375830 [1mSubtest pipe-F-wait-idle-hang: SKIP (0.000s)[0m
13381 11:19:15.389582 <14>[ 31.086199] [IGT] kms_vblank: executing
13382 11:19:15.396051 IGT-Version: 1.2<14>[ 31.091270] [IGT] kms_vblank: exiting, ret=77
13383 11:19:15.398914 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13384 11:19:15.409030 Opened device: /<8>[ 31.102210] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked RESULT=skip>
13385 11:19:15.409561 dev/dri/card0
13386 11:19:15.410161 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked RESULT=skip
13388 11:19:15.412035 No KMS driver or no outputs, pipes: 8, outputs: 0
13389 11:19:15.419051 [1mSubtest pipe-F-wait-forked: SKIP (0.000s)[0m
13390 11:19:15.429695 <14>[ 31.126798] [IGT] kms_vblank: executing
13391 11:19:15.436604 IGT-Version: 1.2<14>[ 31.131968] [IGT] kms_vblank: exiting, ret=77
13392 11:19:15.439644 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13393 11:19:15.449642 Opened device: /<8>[ 31.142781] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-hang RESULT=skip>
13394 11:19:15.450167 dev/dri/card0
13395 11:19:15.450809 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-hang RESULT=skip
13397 11:19:15.456152 No KMS driver or no outputs, pipes: 8, outputs: 0
13398 11:19:15.459701 [1mSubtest pipe-F-wait-forked-hang: SKIP (0.000s)[0m
13399 11:19:15.472272 <14>[ 31.168861] [IGT] kms_vblank: executing
13400 11:19:15.478691 IGT-Version: 1.2<14>[ 31.173861] [IGT] kms_vblank: exiting, ret=77
13401 11:19:15.481812 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13402 11:19:15.485752 Opened device: /dev/dri/card0
13403 11:19:15.491904 N<8>[ 31.185347] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-busy RESULT=skip>
13404 11:19:15.492700 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-busy RESULT=skip
13406 11:19:15.494715 o KMS driver or no outputs, pipes: 8, outputs: 0
13407 11:19:15.501744 [1mSubtest pipe-F-wait-busy: SKIP (0.000s)[0m
13408 11:19:15.515094 <14>[ 31.211892] [IGT] kms_vblank: executing
13409 11:19:15.521561 IGT-Version: 1.2<14>[ 31.217063] [IGT] kms_vblank: exiting, ret=77
13410 11:19:15.524633 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13411 11:19:15.528471 Opened device: /dev/dri/card0
13412 11:19:15.535063 N<8>[ 31.228351] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-busy-hang RESULT=skip>
13413 11:19:15.535850 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-busy-hang RESULT=skip
13415 11:19:15.538138 o KMS driver or no outputs, pipes: 8, outputs: 0
13416 11:19:15.544913 [1mSubtest pipe-F-wait-busy-hang: SKIP (0.000s)[0m
13417 11:19:15.557544 <14>[ 31.254317] [IGT] kms_vblank: executing
13418 11:19:15.564176 IGT-Version: 1.2<14>[ 31.259349] [IGT] kms_vblank: exiting, ret=77
13419 11:19:15.567240 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13420 11:19:15.570041 Opened device: /dev/dri/card0
13421 11:19:15.577185 N<8>[ 31.270452] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-busy RESULT=skip>
13422 11:19:15.577975 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-busy RESULT=skip
13424 11:19:15.583706 o KMS driver or no outputs, pipes: 8, outputs: 0
13425 11:19:15.586710 [1mSubtest pipe-F-wait-forked-busy: SKIP (0.000s)[0m
13426 11:19:15.600564 <14>[ 31.297445] [IGT] kms_vblank: executing
13427 11:19:15.607184 IGT-Version: 1.2<14>[ 31.302361] [IGT] kms_vblank: exiting, ret=77
13428 11:19:15.610168 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13429 11:19:15.613371 Opened device: /dev/dri/card0
13430 11:19:15.620204 N<8>[ 31.314110] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-wait-forked-busy-hang RESULT=skip>
13431 11:19:15.621060 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-wait-forked-busy-hang RESULT=skip
13433 11:19:15.626681 o KMS driver or no outputs, pipes: 8, outputs: 0
13434 11:19:15.629744 [1mSubtest pipe-F-wait-forked-busy-hang: SKIP (0.000s)[0m
13435 11:19:15.643359 <14>[ 31.340265] [IGT] kms_vblank: executing
13436 11:19:15.649778 IGT-Version: 1.2<14>[ 31.345276] [IGT] kms_vblank: exiting, ret=77
13437 11:19:15.653025 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13438 11:19:15.656729 Opened device: /dev/dri/card0
13439 11:19:15.663221 N<8>[ 31.356362] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-idle RESULT=skip>
13440 11:19:15.664007 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-idle RESULT=skip
13442 11:19:15.669551 o KMS driver or no outputs, pipes: 8, outputs: 0
13443 11:19:15.672697 [1mSubtest pipe-F-ts-continuation-idle: SKIP (0.000s)[0m
13444 11:19:15.686543 <14>[ 31.383130] [IGT] kms_vblank: executing
13445 11:19:15.692635 IGT-Version: 1.2<14>[ 31.388132] [IGT] kms_vblank: exiting, ret=77
13446 11:19:15.696270 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13447 11:19:15.706120 Opened device: /<8>[ 31.399023] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-idle-hang RESULT=skip>
13448 11:19:15.706642 dev/dri/card0
13449 11:19:15.707241 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-idle-hang RESULT=skip
13451 11:19:15.712580 No KMS driver or no outputs, pipes: 8, outputs: 0
13452 11:19:15.715857 [1mSubtest pipe-F-ts-continuation-idle-hang: SKIP (0.000s)[0m
13453 11:19:15.728352 <14>[ 31.424965] [IGT] kms_vblank: executing
13454 11:19:15.734473 IGT-Version: 1.2<14>[ 31.429945] [IGT] kms_vblank: exiting, ret=77
13455 11:19:15.737807 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13456 11:19:15.741268 Opened device: /dev/dri/card0
13457 11:19:15.747915 N<8>[ 31.440959] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-dpms-rpm RESULT=skip>
13458 11:19:15.748696 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-dpms-rpm RESULT=skip
13460 11:19:15.754656 o KMS driver or no outputs, pipes: 8, outputs: 0
13461 11:19:15.757686 [1mSubtest pipe-F-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13462 11:19:15.771803 <14>[ 31.468744] [IGT] kms_vblank: executing
13463 11:19:15.778673 IGT-Version: 1.2<14>[ 31.473930] [IGT] kms_vblank: exiting, ret=77
13464 11:19:15.781421 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13465 11:19:15.785336 Opened device: /dev/dri/card0
13466 11:19:15.791950 N<8>[ 31.485308] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-dpms-suspend RESULT=skip>
13467 11:19:15.792757 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-dpms-suspend RESULT=skip
13469 11:19:15.798150 o KMS driver or no outputs, pipes: 8, outputs: 0
13470 11:19:15.804828 [1mSubtest pipe-F-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13471 11:19:15.815572 <14>[ 31.512470] [IGT] kms_vblank: executing
13472 11:19:15.821981 IGT-Version: 1.2<14>[ 31.517491] [IGT] kms_vblank: exiting, ret=77
13473 11:19:15.825245 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13474 11:19:15.828817 Opened device: /dev/dri/card0
13475 11:19:15.835091 N<8>[ 31.528471] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-suspend RESULT=skip>
13476 11:19:15.835907 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-suspend RESULT=skip
13478 11:19:15.841657 o KMS driver or no outputs, pipes: 8, outputs: 0
13479 11:19:15.844994 [1mSubtest pipe-F-ts-continuation-suspend: SKIP (0.000s)[0m
13480 11:19:15.859663 <14>[ 31.556446] [IGT] kms_vblank: executing
13481 11:19:15.865783 IGT-Version: 1.2<14>[ 31.561642] [IGT] kms_vblank: exiting, ret=77
13482 11:19:15.869443 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13483 11:19:15.873051 Opened device: /dev/dri/card0
13484 11:19:15.879156 N<8>[ 31.572767] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset RESULT=skip>
13485 11:19:15.879962 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset RESULT=skip
13487 11:19:15.885850 o KMS driver or no outputs, pipes: 8, outputs: 0
13488 11:19:15.889054 [1mSubtest pipe-F-ts-continuation-modeset: SKIP (0.000s)[0m
13489 11:19:15.903083 <14>[ 31.599771] [IGT] kms_vblank: executing
13490 11:19:15.909423 IGT-Version: 1.2<14>[ 31.604781] [IGT] kms_vblank: exiting, ret=77
13491 11:19:15.912597 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13492 11:19:15.916003 Opened device: /dev/dri/card0
13493 11:19:15.922304 N<8>[ 31.615732] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset-hang RESULT=skip>
13494 11:19:15.923091 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset-hang RESULT=skip
13496 11:19:15.928940 o KMS driver or no outputs, pipes: 8, outputs: 0
13497 11:19:15.935498 [1mSubtest pipe-F-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13498 11:19:15.946433 <14>[ 31.643384] [IGT] kms_vblank: executing
13499 11:19:15.953004 IGT-Version: 1.2<14>[ 31.648503] [IGT] kms_vblank: exiting, ret=77
13500 11:19:15.956030 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13501 11:19:15.966020 Opened device: /<8>[ 31.659333] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-F-ts-continuation-modeset-rpm RESULT=skip>
13502 11:19:15.966543 dev/dri/card0
13503 11:19:15.967137 Received signal: <TESTCASE> TEST_CASE_ID=pipe-F-ts-continuation-modeset-rpm RESULT=skip
13505 11:19:15.972399 No KMS driver or no outputs, pipes: 8, outputs: 0
13506 11:19:15.978996 [1mSubtest pipe-F-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13507 11:19:15.988515 <14>[ 31.685461] [IGT] kms_vblank: executing
13508 11:19:15.995039 IGT-Version: 1.2<14>[ 31.690439] [IGT] kms_vblank: exiting, ret=77
13509 11:19:15.998399 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13510 11:19:16.001352 Opened device: /dev/dri/card0
13511 11:19:16.008705 N<8>[ 31.701423] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-accuracy-idle RESULT=skip>
13512 11:19:16.009541 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-accuracy-idle RESULT=skip
13514 11:19:16.011504 o KMS driver or no outputs, pipes: 8, outputs: 0
13515 11:19:16.018278 [1mSubtest pipe-G-accuracy-idle: SKIP (0.000s)[0m
13516 11:19:16.030749 <14>[ 31.727498] [IGT] kms_vblank: executing
13517 11:19:16.037263 IGT-Version: 1.2<14>[ 31.732574] [IGT] kms_vblank: exiting, ret=77
13518 11:19:16.040259 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13519 11:19:16.050013 Opened device: /<8>[ 31.743499] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-idle RESULT=skip>
13520 11:19:16.050541 dev/dri/card0
13521 11:19:16.051149 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-idle RESULT=skip
13523 11:19:16.053068 No KMS driver or no outputs, pipes: 8, outputs: 0
13524 11:19:16.060031 [1mSubtest pipe-G-query-idle: SKIP (0.000s)[0m
13525 11:19:16.071048 <14>[ 31.768247] [IGT] kms_vblank: executing
13526 11:19:16.078024 IGT-Version: 1.2<14>[ 31.773242] [IGT] kms_vblank: exiting, ret=77
13527 11:19:16.081457 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13528 11:19:16.084478 Opened device: /dev/dri/card0
13529 11:19:16.091103 N<8>[ 31.784231] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-idle-hang RESULT=skip>
13530 11:19:16.091923 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-idle-hang RESULT=skip
13532 11:19:16.094343 o KMS driver or no outputs, pipes: 8, outputs: 0
13533 11:19:16.101156 [1mSubtest pipe-G-query-idle-hang: SKIP (0.000s)[0m
13534 11:19:16.113686 <14>[ 31.810495] [IGT] kms_vblank: executing
13535 11:19:16.120369 IGT-Version: 1.2<14>[ 31.815668] [IGT] kms_vblank: exiting, ret=77
13536 11:19:16.123317 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13537 11:19:16.133631 Opened device: /<8>[ 31.826459] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked RESULT=skip>
13538 11:19:16.134172 dev/dri/card0
13539 11:19:16.134783 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked RESULT=skip
13541 11:19:16.136387 No KMS driver or no outputs, pipes: 8, outputs: 0
13542 11:19:16.143046 [1mSubtest pipe-G-query-forked: SKIP (0.000s)[0m
13543 11:19:16.154985 <14>[ 31.852170] [IGT] kms_vblank: executing
13544 11:19:16.161407 IGT-Version: 1.2<14>[ 31.857137] [IGT] kms_vblank: exiting, ret=77
13545 11:19:16.164911 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13546 11:19:16.168030 Opened device: /dev/dri/card0
13547 11:19:16.174631 N<8>[ 31.868722] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-hang RESULT=skip>
13548 11:19:16.175328 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-hang RESULT=skip
13550 11:19:16.181710 o KMS driver or no outputs, pipes: 8, outputs: 0
13551 11:19:16.184918 [1mSubtest pipe-G-query-forked-hang: SKIP (0.000s)[0m
13552 11:19:16.198334 <14>[ 31.895500] [IGT] kms_vblank: executing
13553 11:19:16.205144 IGT-Version: 1.2<14>[ 31.900994] [IGT] kms_vblank: exiting, ret=77
13554 11:19:16.208042 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13555 11:19:16.211667 Opened device: /dev/dri/card0
13556 11:19:16.218273 N<8>[ 31.912475] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-busy RESULT=skip>
13557 11:19:16.219076 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-busy RESULT=skip
13559 11:19:16.221473 o KMS driver or no outputs, pipes: 8, outputs: 0
13560 11:19:16.228378 [1mSubtest pipe-G-query-busy: SKIP (0.000s)[0m
13561 11:19:16.242081 <14>[ 31.939192] [IGT] kms_vblank: executing
13562 11:19:16.248854 IGT-Version: 1.2<14>[ 31.944396] [IGT] kms_vblank: exiting, ret=77
13563 11:19:16.252577 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13564 11:19:16.255217 Opened device: /dev/dri/card0
13565 11:19:16.261651 N<8>[ 31.955755] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-busy-hang RESULT=skip>
13566 11:19:16.262357 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-busy-hang RESULT=skip
13568 11:19:16.268329 o KMS driver or no outputs, pipes: 8, outputs: 0
13569 11:19:16.271285 [1mSubtest pipe-G-query-busy-hang: SKIP (0.000s)[0m
13570 11:19:16.284688 <14>[ 31.981766] [IGT] kms_vblank: executing
13571 11:19:16.291413 IGT-Version: 1.2<14>[ 31.986759] [IGT] kms_vblank: exiting, ret=77
13572 11:19:16.294843 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13573 11:19:16.304498 Opened device: /<8>[ 31.997708] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-busy RESULT=skip>
13574 11:19:16.305097 dev/dri/card0
13575 11:19:16.305712 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-busy RESULT=skip
13577 11:19:16.310854 No KMS driver or no outputs, pipes: 8, outputs: 0
13578 11:19:16.314295 [1mSubtest pipe-G-query-forked-busy: SKIP (0.000s)[0m
13579 11:19:16.325762 <14>[ 32.022835] [IGT] kms_vblank: executing
13580 11:19:16.332570 IGT-Version: 1.2<14>[ 32.027940] [IGT] kms_vblank: exiting, ret=77
13581 11:19:16.335874 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13582 11:19:16.345882 Opened device: /<8>[ 32.038816] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-query-forked-busy-hang RESULT=skip>
13583 11:19:16.346413 dev/dri/card0
13584 11:19:16.347029 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-query-forked-busy-hang RESULT=skip
13586 11:19:16.352631 No KMS driver or no outputs, pipes: 8, outputs: 0
13587 11:19:16.355332 [1mSubtest pipe-G-query-forked-busy-hang: SKIP (0.000s)[0m
13588 11:19:16.367924 <14>[ 32.065138] [IGT] kms_vblank: executing
13589 11:19:16.374731 IGT-Version: 1.2<14>[ 32.070260] [IGT] kms_vblank: exiting, ret=77
13590 11:19:16.377910 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13591 11:19:16.381171 Opened device: /dev/dri/card0
13592 11:19:16.387990 N<8>[ 32.081513] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-idle RESULT=skip>
13593 11:19:16.388842 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-idle RESULT=skip
13595 11:19:16.390730 o KMS driver or no outputs, pipes: 8, outputs: 0
13596 11:19:16.397541 [1mSubtest pipe-G-wait-idle: SKIP (0.000s)[0m
13597 11:19:16.410243 <14>[ 32.107391] [IGT] kms_vblank: executing
13598 11:19:16.417264 IGT-Version: 1.2<14>[ 32.112472] [IGT] kms_vblank: exiting, ret=77
13599 11:19:16.420591 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13600 11:19:16.423711 Opened device: /dev/dri/card0
13601 11:19:16.430033 N<8>[ 32.123473] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-idle-hang RESULT=skip>
13602 11:19:16.430827 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-idle-hang RESULT=skip
13604 11:19:16.433304 o KMS driver or no outputs, pipes: 8, outputs: 0
13605 11:19:16.439918 [1mSubtest pipe-G-wait-idle-hang: SKIP (0.000s)[0m
13606 11:19:16.452913 <14>[ 32.149877] [IGT] kms_vblank: executing
13607 11:19:16.459228 IGT-Version: 1.2<14>[ 32.154889] [IGT] kms_vblank: exiting, ret=77
13608 11:19:16.462819 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13609 11:19:16.466764 Opened device: /dev/dri/card0
13610 11:19:16.472934 N<8>[ 32.165956] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked RESULT=skip>
13611 11:19:16.473741 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked RESULT=skip
13613 11:19:16.475437 o KMS driver or no outputs, pipes: 8, outputs: 0
13614 11:19:16.482232 [1mSubtest pipe-G-wait-forked: SKIP (0.000s)[0m
13615 11:19:16.495309 <14>[ 32.192680] [IGT] kms_vblank: executing
13616 11:19:16.501906 IGT-Version: 1.2<14>[ 32.197862] [IGT] kms_vblank: exiting, ret=77
13617 11:19:16.505522 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13618 11:19:16.508580 Opened device: /dev/dri/card0
13619 11:19:16.515651 N<8>[ 32.209373] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-hang RESULT=skip>
13620 11:19:16.516457 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-hang RESULT=skip
13622 11:19:16.522139 o KMS driver or no outputs, pipes: 8, outputs: 0
13623 11:19:16.525124 [1mSubtest pipe-G-wait-forked-hang: SKIP (0.000s)[0m
13624 11:19:16.539832 <14>[ 32.236465] [IGT] kms_vblank: executing
13625 11:19:16.546109 IGT-Version: 1.2<14>[ 32.241943] [IGT] kms_vblank: exiting, ret=77
13626 11:19:16.549442 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13627 11:19:16.552893 Opened device: /dev/dri/card0
13628 11:19:16.559475 N<8>[ 32.253245] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-busy RESULT=skip>
13629 11:19:16.560281 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-busy RESULT=skip
13631 11:19:16.562653 o KMS driver or no outputs, pipes: 8, outputs: 0
13632 11:19:16.569302 [1mSubtest pipe-G-wait-busy: SKIP (0.000s)[0m
13633 11:19:16.583500 <14>[ 32.280033] [IGT] kms_vblank: executing
13634 11:19:16.589690 IGT-Version: 1.2<14>[ 32.285242] [IGT] kms_vblank: exiting, ret=77
13635 11:19:16.593008 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13636 11:19:16.596089 Opened device: /dev/dri/card0
13637 11:19:16.602412 N<8>[ 32.296593] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-busy-hang RESULT=skip>
13638 11:19:16.603132 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-busy-hang RESULT=skip
13640 11:19:16.605875 o KMS driver or no outputs, pipes: 8, outputs: 0
13641 11:19:16.612644 [1mSubtest pipe-G-wait-busy-hang: SKIP (0.000s)[0m
13642 11:19:16.626401 <14>[ 32.323428] [IGT] kms_vblank: executing
13643 11:19:16.633225 IGT-Version: 1.2<14>[ 32.328625] [IGT] kms_vblank: exiting, ret=77
13644 11:19:16.635929 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13645 11:19:16.639452 Opened device: /dev/dri/card0
13646 11:19:16.646181 N<8>[ 32.340551] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-busy RESULT=skip>
13647 11:19:16.646972 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-busy RESULT=skip
13649 11:19:16.653108 o KMS driver or no outputs, pipes: 8, outputs: 0
13650 11:19:16.656313 [1mSubtest pipe-G-wait-forked-busy: SKIP (0.000s)[0m
13651 11:19:16.669509 <14>[ 32.366481] [IGT] kms_vblank: executing
13652 11:19:16.675861 IGT-Version: 1.2<14>[ 32.371732] [IGT] kms_vblank: exiting, ret=77
13653 11:19:16.679431 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13654 11:19:16.682455 Opened device: /dev/dri/card0
13655 11:19:16.689329 N<8>[ 32.383459] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-wait-forked-busy-hang RESULT=skip>
13656 11:19:16.690117 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-wait-forked-busy-hang RESULT=skip
13658 11:19:16.696024 o KMS driver or no outputs, pipes: 8, outputs: 0
13659 11:19:16.698828 [1mSubtest pipe-G-wait-forked-busy-hang: SKIP (0.000s)[0m
13660 11:19:16.713126 <14>[ 32.410341] [IGT] kms_vblank: executing
13661 11:19:16.719848 IGT-Version: 1.2<14>[ 32.415667] [IGT] kms_vblank: exiting, ret=77
13662 11:19:16.723364 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13663 11:19:16.726359 Opened device: /dev/dri/card0
13664 11:19:16.733272 N<8>[ 32.426831] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-idle RESULT=skip>
13665 11:19:16.734068 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-idle RESULT=skip
13667 11:19:16.739717 o KMS driver or no outputs, pipes: 8, outputs: 0
13668 11:19:16.743258 [1mSubtest pipe-G-ts-continuation-idle: SKIP (0.000s)[0m
13669 11:19:16.756428 <14>[ 32.453468] [IGT] kms_vblank: executing
13670 11:19:16.762876 IGT-Version: 1.2<14>[ 32.458538] [IGT] kms_vblank: exiting, ret=77
13671 11:19:16.766348 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13672 11:19:16.769187 Opened device: /dev/dri/card0
13673 11:19:16.776081 N<8>[ 32.469771] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-idle-hang RESULT=skip>
13674 11:19:16.776892 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-idle-hang RESULT=skip
13676 11:19:16.782676 o KMS driver or no outputs, pipes: 8, outputs: 0
13677 11:19:16.785971 [1mSubtest pipe-G-ts-continuation-idle-hang: SKIP (0.000s)[0m
13678 11:19:16.800499 <14>[ 32.497764] [IGT] kms_vblank: executing
13679 11:19:16.807198 IGT-Version: 1.2<14>[ 32.502890] [IGT] kms_vblank: exiting, ret=77
13680 11:19:16.810262 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13681 11:19:16.813693 Opened device: /dev/dri/card0
13682 11:19:16.820475 N<8>[ 32.514263] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-dpms-rpm RESULT=skip>
13683 11:19:16.821243 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-dpms-rpm RESULT=skip
13685 11:19:16.826764 o KMS driver or no outputs, pipes: 8, outputs: 0
13686 11:19:16.830200 [1mSubtest pipe-G-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13687 11:19:16.843841 <14>[ 32.541068] [IGT] kms_vblank: executing
13688 11:19:16.850667 IGT-Version: 1.2<14>[ 32.546204] [IGT] kms_vblank: exiting, ret=77
13689 11:19:16.853638 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13690 11:19:16.857456 Opened device: /dev/dri/card0
13691 11:19:16.864285 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-dpms-suspend RESULT=skip
13693 11:19:16.867231 N<8>[ 32.557284] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-dpms-suspend RESULT=skip>
13694 11:19:16.870224 o KMS driver or no outputs, pipes: 8, outputs: 0
13695 11:19:16.876641 [1mSubtest pipe-G-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13696 11:19:16.888328 <14>[ 32.585403] [IGT] kms_vblank: executing
13697 11:19:16.894632 IGT-Version: 1.2<14>[ 32.590684] [IGT] kms_vblank: exiting, ret=77
13698 11:19:16.898134 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13699 11:19:16.901427 Opened device: /dev/dri/card0
13700 11:19:16.908133 N<8>[ 32.601803] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-suspend RESULT=skip>
13701 11:19:16.908935 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-suspend RESULT=skip
13703 11:19:16.914845 o KMS driver or no outputs, pipes: 8, outputs: 0
13704 11:19:16.917931 [1mSubtest pipe-G-ts-continuation-suspend: SKIP (0.000s)[0m
13705 11:19:16.931153 <14>[ 32.628812] [IGT] kms_vblank: executing
13706 11:19:16.937823 IGT-Version: 1.2<14>[ 32.633818] [IGT] kms_vblank: exiting, ret=77
13707 11:19:16.941486 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13708 11:19:16.944627 Opened device: /dev/dri/card0
13709 11:19:16.951260 N<8>[ 32.644875] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset RESULT=skip>
13710 11:19:16.952062 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset RESULT=skip
13712 11:19:16.957906 o KMS driver or no outputs, pipes: 8, outputs: 0
13713 11:19:16.961262 [1mSubtest pipe-G-ts-continuation-modeset: SKIP (0.000s)[0m
13714 11:19:16.975804 <14>[ 32.672948] [IGT] kms_vblank: executing
13715 11:19:16.982530 IGT-Version: 1.2<14>[ 32.678155] [IGT] kms_vblank: exiting, ret=77
13716 11:19:16.985605 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13717 11:19:16.989260 Opened device: /dev/dri/card0
13718 11:19:16.995720 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset-hang RESULT=skip
13720 11:19:16.999157 N<8>[ 32.689239] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset-hang RESULT=skip>
13721 11:19:17.002462 o KMS driver or no outputs, pipes: 8, outputs: 0
13722 11:19:17.008439 [1mSubtest pipe-G-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13723 11:19:17.020212 <14>[ 32.717396] [IGT] kms_vblank: executing
13724 11:19:17.027096 IGT-Version: 1.2<14>[ 32.722683] [IGT] kms_vblank: exiting, ret=77
13725 11:19:17.029888 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13726 11:19:17.033425 Opened device: /dev/dri/card0
13727 11:19:17.040208 Received signal: <TESTCASE> TEST_CASE_ID=pipe-G-ts-continuation-modeset-rpm RESULT=skip
13729 11:19:17.043365 N<8>[ 32.734086] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-G-ts-continuation-modeset-rpm RESULT=skip>
13730 11:19:17.046889 o KMS driver or no outputs, pipes: 8, outputs: 0
13731 11:19:17.053107 [1mSubtest pipe-G-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13732 11:19:17.064075 <14>[ 32.761113] [IGT] kms_vblank: executing
13733 11:19:17.070469 IGT-Version: 1.2<14>[ 32.766200] [IGT] kms_vblank: exiting, ret=77
13734 11:19:17.073671 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13735 11:19:17.076865 Opened device: /dev/dri/card0
13736 11:19:17.084143 N<8>[ 32.777266] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-accuracy-idle RESULT=skip>
13737 11:19:17.084973 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-accuracy-idle RESULT=skip
13739 11:19:17.087390 o KMS driver or no outputs, pipes: 8, outputs: 0
13740 11:19:17.093619 [1mSubtest pipe-H-accuracy-idle: SKIP (0.000s)[0m
13741 11:19:17.105947 <14>[ 32.803343] [IGT] kms_vblank: executing
13742 11:19:17.112748 IGT-Version: 1.2<14>[ 32.808429] [IGT] kms_vblank: exiting, ret=77
13743 11:19:17.116165 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13744 11:19:17.119374 Opened device: /dev/dri/card0
13745 11:19:17.125689 N<8>[ 32.819542] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-idle RESULT=skip>
13746 11:19:17.126381 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-idle RESULT=skip
13748 11:19:17.128804 o KMS driver or no outputs, pipes: 8, outputs: 0
13749 11:19:17.135698 [1mSubtest pipe-H-query-idle: SKIP (0.000s)[0m
13750 11:19:17.148450 <14>[ 32.845472] [IGT] kms_vblank: executing
13751 11:19:17.154633 IGT-Version: 1.2<14>[ 32.850560] [IGT] kms_vblank: exiting, ret=77
13752 11:19:17.157934 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13753 11:19:17.161181 Opened device: /dev/dri/card0
13754 11:19:17.167647 N<8>[ 32.861590] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-idle-hang RESULT=skip>
13755 11:19:17.168448 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-idle-hang RESULT=skip
13757 11:19:17.171069 o KMS driver or no outputs, pipes: 8, outputs: 0
13758 11:19:17.177565 [1mSubtest pipe-H-query-idle-hang: SKIP (0.000s)[0m
13759 11:19:17.190737 <14>[ 32.887948] [IGT] kms_vblank: executing
13760 11:19:17.197408 IGT-Version: 1.2<14>[ 32.892956] [IGT] kms_vblank: exiting, ret=77
13761 11:19:17.200322 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13762 11:19:17.203798 Opened device: /dev/dri/card0
13763 11:19:17.210168 N<8>[ 32.904000] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked RESULT=skip>
13764 11:19:17.210834 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked RESULT=skip
13766 11:19:17.214306 o KMS driver or no outputs, pipes: 8, outputs: 0
13767 11:19:17.220696 [1mSubtest pipe-H-query-forked: SKIP (0.000s)[0m
13768 11:19:17.232696 <14>[ 32.930051] [IGT] kms_vblank: executing
13769 11:19:17.239569 IGT-Version: 1.2<14>[ 32.935133] [IGT] kms_vblank: exiting, ret=77
13770 11:19:17.242584 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13771 11:19:17.252616 Opened device: /<8>[ 32.945913] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-hang RESULT=skip>
13772 11:19:17.253186 dev/dri/card0
13773 11:19:17.253857 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-hang RESULT=skip
13775 11:19:17.259340 No KMS driver or no outputs, pipes: 8, outputs: 0
13776 11:19:17.262431 [1mSubtest pipe-H-query-forked-hang: SKIP (0.000s)[0m
13777 11:19:17.274579 <14>[ 32.971918] [IGT] kms_vblank: executing
13778 11:19:17.281211 IGT-Version: 1.2<14>[ 32.976992] [IGT] kms_vblank: exiting, ret=77
13779 11:19:17.284900 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13780 11:19:17.287926 Opened device: /dev/dri/card0
13781 11:19:17.294357 N<8>[ 32.988352] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-busy RESULT=skip>
13782 11:19:17.295169 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-busy RESULT=skip
13784 11:19:17.297821 o KMS driver or no outputs, pipes: 8, outputs: 0
13785 11:19:17.304586 [1mSubtest pipe-H-query-busy: SKIP (0.000s)[0m
13786 11:19:17.316839 <14>[ 33.013964] [IGT] kms_vblank: executing
13787 11:19:17.323549 IGT-Version: 1.2<14>[ 33.019043] [IGT] kms_vblank: exiting, ret=77
13788 11:19:17.326617 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13789 11:19:17.336831 Opened device: /<8>[ 33.029717] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-busy-hang RESULT=skip>
13790 11:19:17.337357 dev/dri/card0
13791 11:19:17.337948 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-busy-hang RESULT=skip
13793 11:19:17.339974 No KMS driver or no outputs, pipes: 8, outputs: 0
13794 11:19:17.346387 [1mSubtest pipe-H-query-busy-hang: SKIP (0.000s)[0m
13795 11:19:17.358293 <14>[ 33.055712] [IGT] kms_vblank: executing
13796 11:19:17.365099 IGT-Version: 1.2<14>[ 33.060933] [IGT] kms_vblank: exiting, ret=77
13797 11:19:17.368547 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13798 11:19:17.371780 Opened device: /dev/dri/card0
13799 11:19:17.378328 N<8>[ 33.072020] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-busy RESULT=skip>
13800 11:19:17.379122 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-busy RESULT=skip
13802 11:19:17.385121 o KMS driver or no outputs, pipes: 8, outputs: 0
13803 11:19:17.388519 [1mSubtest pipe-H-query-forked-busy: SKIP (0.000s)[0m
13804 11:19:17.401430 <14>[ 33.098434] [IGT] kms_vblank: executing
13805 11:19:17.407477 IGT-Version: 1.2<14>[ 33.103511] [IGT] kms_vblank: exiting, ret=77
13806 11:19:17.411182 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13807 11:19:17.421316 Opened device: /<8>[ 33.114128] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-query-forked-busy-hang RESULT=skip>
13808 11:19:17.421832 dev/dri/card0
13809 11:19:17.422421 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-query-forked-busy-hang RESULT=skip
13811 11:19:17.427671 No KMS driver or no outputs, pipes: 8, outputs: 0
13812 11:19:17.430793 [1mSubtest pipe-H-query-forked-busy-hang: SKIP (0.000s)[0m
13813 11:19:17.442582 <14>[ 33.140011] [IGT] kms_vblank: executing
13814 11:19:17.449638 IGT-Version: 1.2<14>[ 33.144981] [IGT] kms_vblank: exiting, ret=77
13815 11:19:17.452706 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13816 11:19:17.462290 Opened device: /<8>[ 33.155851] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-idle RESULT=skip>
13817 11:19:17.462713 dev/dri/card0
13818 11:19:17.463346 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-idle RESULT=skip
13820 11:19:17.465752 No KMS driver or no outputs, pipes: 8, outputs: 0
13821 11:19:17.472118 [1mSubtest pipe-H-wait-idle: SKIP (0.000s)[0m
13822 11:19:17.484147 <14>[ 33.181122] [IGT] kms_vblank: executing
13823 11:19:17.490928 IGT-Version: 1.2<14>[ 33.186048] [IGT] kms_vblank: exiting, ret=77
13824 11:19:17.493632 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13825 11:19:17.497384 Opened device: /dev/dri/card0
13826 11:19:17.504045 N<8>[ 33.197923] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-idle-hang RESULT=skip>
13827 11:19:17.504860 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-idle-hang RESULT=skip
13829 11:19:17.506862 o KMS driver or no outputs, pipes: 8, outputs: 0
13830 11:19:17.513527 [1mSubtest pipe-H-wait-idle-hang: SKIP (0.000s)[0m
13831 11:19:17.527089 <14>[ 33.224097] [IGT] kms_vblank: executing
13832 11:19:17.533627 IGT-Version: 1.2<14>[ 33.229145] [IGT] kms_vblank: exiting, ret=77
13833 11:19:17.536665 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13834 11:19:17.539888 Opened device: /dev/dri/card0
13835 11:19:17.546613 N<8>[ 33.241007] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked RESULT=skip>
13836 11:19:17.547400 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked RESULT=skip
13838 11:19:17.549411 o KMS driver or no outputs, pipes: 8, outputs: 0
13839 11:19:17.556476 [1mSubtest pipe-H-wait-forked: SKIP (0.000s)[0m
13840 11:19:17.568628 <14>[ 33.266047] [IGT] kms_vblank: executing
13841 11:19:17.575224 IGT-Version: 1.2<14>[ 33.271055] [IGT] kms_vblank: exiting, ret=77
13842 11:19:17.578293 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13843 11:19:17.581842 Opened device: /dev/dri/card0
13844 11:19:17.588384 N<8>[ 33.282079] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-hang RESULT=skip>
13845 11:19:17.589169 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-hang RESULT=skip
13847 11:19:17.591884 o KMS driver or no outputs, pipes: 8, outputs: 0
13848 11:19:17.598256 [1mSubtest pipe-H-wait-forked-hang: SKIP (0.000s)[0m
13849 11:19:17.612381 <14>[ 33.309327] [IGT] kms_vblank: executing
13850 11:19:17.618836 IGT-Version: 1.2<14>[ 33.314316] [IGT] kms_vblank: exiting, ret=77
13851 11:19:17.622071 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13852 11:19:17.625670 Opened device: /dev/dri/card0
13853 11:19:17.632194 N<8>[ 33.325869] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-busy RESULT=skip>
13854 11:19:17.632983 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-busy RESULT=skip
13856 11:19:17.635025 o KMS driver or no outputs, pipes: 8, outputs: 0
13857 11:19:17.641725 [1mSubtest pipe-H-wait-busy: SKIP (0.000s)[0m
13858 11:19:17.653927 <14>[ 33.351040] [IGT] kms_vblank: executing
13859 11:19:17.660314 IGT-Version: 1.2<14>[ 33.356161] [IGT] kms_vblank: exiting, ret=77
13860 11:19:17.663977 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13861 11:19:17.666836 Opened device: /dev/dri/card0
13862 11:19:17.673535 N<8>[ 33.367323] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-busy-hang RESULT=skip>
13863 11:19:17.674323 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-busy-hang RESULT=skip
13865 11:19:17.677172 o KMS driver or no outputs, pipes: 8, outputs: 0
13866 11:19:17.683086 [1mSubtest pipe-H-wait-busy-hang: SKIP (0.000s)[0m
13867 11:19:17.696475 <14>[ 33.393556] [IGT] kms_vblank: executing
13868 11:19:17.702735 IGT-Version: 1.2<14>[ 33.398534] [IGT] kms_vblank: exiting, ret=77
13869 11:19:17.706367 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13870 11:19:17.716199 Opened device: /<8>[ 33.409485] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-busy RESULT=skip>
13871 11:19:17.716739 dev/dri/card0
13872 11:19:17.717432 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-busy RESULT=skip
13874 11:19:17.719175 No KMS driver or no outputs, pipes: 8, outputs: 0
13875 11:19:17.725930 [1mSubtest pipe-H-wait-forked-busy: SKIP (0.000s)[0m
13876 11:19:17.737692 <14>[ 33.434537] [IGT] kms_vblank: executing
13877 11:19:17.744104 IGT-Version: 1.2<14>[ 33.439596] [IGT] kms_vblank: exiting, ret=77
13878 11:19:17.747337 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13879 11:19:17.750605 Opened device: /dev/dri/card0
13880 11:19:17.757118 N<8>[ 33.450615] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-wait-forked-busy-hang RESULT=skip>
13881 11:19:17.757900 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-wait-forked-busy-hang RESULT=skip
13883 11:19:17.763831 o KMS driver or no outputs, pipes: 8, outputs: 0
13884 11:19:17.766505 [1mSubtest pipe-H-wait-forked-busy-hang: SKIP (0.000s)[0m
13885 11:19:17.780197 <14>[ 33.477483] [IGT] kms_vblank: executing
13886 11:19:17.786505 IGT-Version: 1.2<14>[ 33.482505] [IGT] kms_vblank: exiting, ret=77
13887 11:19:17.789669 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13888 11:19:17.799842 Opened device: /<8>[ 33.493319] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-idle RESULT=skip>
13889 11:19:17.800375 dev/dri/card0
13890 11:19:17.800969 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-idle RESULT=skip
13892 11:19:17.806460 No KMS driver or no outputs, pipes: 8, outputs: 0
13893 11:19:17.809858 [1mSubtest pipe-H-ts-continuation-idle: SKIP (0.000s)[0m
13894 11:19:17.821552 <14>[ 33.519089] [IGT] kms_vblank: executing
13895 11:19:17.828410 IGT-Version: 1.2<14>[ 33.524076] [IGT] kms_vblank: exiting, ret=77
13896 11:19:17.832034 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13897 11:19:17.841662 Opened device: /<8>[ 33.534880] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-idle-hang RESULT=skip>
13898 11:19:17.842209 dev/dri/card0
13899 11:19:17.842812 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-idle-hang RESULT=skip
13901 11:19:17.848212 No KMS driver or no outputs, pipes: 8, outputs: 0
13902 11:19:17.851524 [1mSubtest pipe-H-ts-continuation-idle-hang: SKIP (0.000s)[0m
13903 11:19:17.863730 <14>[ 33.560921] [IGT] kms_vblank: executing
13904 11:19:17.870183 IGT-Version: 1.2<14>[ 33.565938] [IGT] kms_vblank: exiting, ret=77
13905 11:19:17.873632 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13906 11:19:17.883332 Opened device: /<8>[ 33.576818] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-dpms-rpm RESULT=skip>
13907 11:19:17.883860 dev/dri/card0
13908 11:19:17.884456 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-dpms-rpm RESULT=skip
13910 11:19:17.890025 No KMS driver or no outputs, pipes: 8, outputs: 0
13911 11:19:17.893272 [1mSubtest pipe-H-ts-continuation-dpms-rpm: SKIP (0.000s)[0m
13912 11:19:17.906218 <14>[ 33.603510] [IGT] kms_vblank: executing
13913 11:19:17.912623 IGT-Version: 1.2<14>[ 33.608447] [IGT] kms_vblank: exiting, ret=77
13914 11:19:17.915801 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13915 11:19:17.919506 Opened device: /dev/dri/card0
13916 11:19:17.926073 N<8>[ 33.620011] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-dpms-suspend RESULT=skip>
13917 11:19:17.926841 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-dpms-suspend RESULT=skip
13919 11:19:17.932630 o KMS driver or no outputs, pipes: 8, outputs: 0
13920 11:19:17.939304 [1mSubtest pipe-H-ts-continuation-dpms-suspend: SKIP (0.000s)[0m
13921 11:19:17.950990 <14>[ 33.648078] [IGT] kms_vblank: executing
13922 11:19:17.957597 IGT-Version: 1.2<14>[ 33.653269] [IGT] kms_vblank: exiting, ret=77
13923 11:19:17.960928 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13924 11:19:17.964032 Opened device: /dev/dri/card0
13925 11:19:17.970583 N<8>[ 33.664558] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-suspend RESULT=skip>
13926 11:19:17.971353 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-suspend RESULT=skip
13928 11:19:17.977382 o KMS driver or no outputs, pipes: 8, outputs: 0
13929 11:19:17.981050 [1mSubtest pipe-H-ts-continuation-suspend: SKIP (0.000s)[0m
13930 11:19:17.993790 <14>[ 33.691252] [IGT] kms_vblank: executing
13931 11:19:18.000920 IGT-Version: 1.2<14>[ 33.696251] [IGT] kms_vblank: exiting, ret=77
13932 11:19:18.003495 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13933 11:19:18.006864 Opened device: /dev/dri/card0
13934 11:19:18.013693 N<8>[ 33.707369] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset RESULT=skip>
13935 11:19:18.014384 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset RESULT=skip
13937 11:19:18.019951 o KMS driver or no outputs, pipes: 8, outputs: 0
13938 11:19:18.023677 [1mSubtest pipe-H-ts-continuation-modeset: SKIP (0.000s)[0m
13939 11:19:18.037036 <14>[ 33.734075] [IGT] kms_vblank: executing
13940 11:19:18.043770 IGT-Version: 1.2<14>[ 33.739086] [IGT] kms_vblank: exiting, ret=77
13941 11:19:18.046794 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13942 11:19:18.056423 Opened device: /<8>[ 33.749944] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset-hang RESULT=skip>
13943 11:19:18.056983 dev/dri/card0
13944 11:19:18.057585 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset-hang RESULT=skip
13946 11:19:18.063234 No KMS driver or no outputs, pipes: 8, outputs: 0
13947 11:19:18.070003 [1mSubtest pipe-H-ts-continuation-modeset-hang: SKIP (0.000s)[0m
13948 11:19:18.078949 <14>[ 33.776113] [IGT] kms_vblank: executing
13949 11:19:18.085646 IGT-Version: 1.2<14>[ 33.781110] [IGT] kms_vblank: exiting, ret=77
13950 11:19:18.088587 7.1-g766edf9 (aarch64) (Linux: 6.1.31 aarch64)
13951 11:19:18.092122 Opened device: /dev/dri/card0
13952 11:19:18.098638 N<8>[ 33.792142] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=pipe-H-ts-continuation-modeset-rpm RESULT=skip>
13953 11:19:18.099502 Received signal: <TESTCASE> TEST_CASE_ID=pipe-H-ts-continuation-modeset-rpm RESULT=skip
13955 11:19:18.105399 Received signal: <TESTSET> STOP
13956 11:19:18.105890 Closing test_set kms_vblank
13957 11:19:18.108058 o KMS driver or no outputs, pipe<8>[ 33.804071] <LAVA_SIGNAL_TESTSET STOP>
13958 11:19:18.115071 s: 8, outputs: 0<8>[ 33.810015] <LAVA_SIGNAL_ENDRUN 0_igt-kms-mediatek 10591274_1.5.2.3.1>
13959 11:19:18.115594
13960 11:19:18.116191 Received signal: <ENDRUN> 0_igt-kms-mediatek 10591274_1.5.2.3.1
13961 11:19:18.116573 Ending use of test pattern.
13962 11:19:18.116923 Ending test lava.0_igt-kms-mediatek (10591274_1.5.2.3.1), duration 13.54
13964 11:19:18.121523 [1mSubtest pipe-H-ts-continuation-modeset-rpm: SKIP (0.000s)[0m
13965 11:19:18.121943 + set +x
13966 11:19:18.124933 <LAVA_TEST_RUNNER EXIT>
13967 11:19:18.125599 ok: lava_test_shell seems to have completed
13968 11:19:18.145191 addfb25-4-tiled:
result: skip
set: kms_addfb_basic
addfb25-bad-modifier:
result: fail
set: kms_addfb_basic
addfb25-framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
addfb25-modifier-no-flag:
result: pass
set: kms_addfb_basic
addfb25-x-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-x-tiled-mismatch-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-legacy:
result: skip
set: kms_addfb_basic
addfb25-y-tiled-small-legacy:
result: skip
set: kms_addfb_basic
addfb25-yf-tiled-legacy:
result: skip
set: kms_addfb_basic
atomic-invalid-params:
result: skip
set: kms_atomic
atomic_plane_damage:
result: skip
set: kms_atomic
bad-pitch-0:
result: pass
set: kms_addfb_basic
bad-pitch-1024:
result: pass
set: kms_addfb_basic
bad-pitch-128:
result: pass
set: kms_addfb_basic
bad-pitch-256:
result: pass
set: kms_addfb_basic
bad-pitch-32:
result: pass
set: kms_addfb_basic
bad-pitch-63:
result: pass
set: kms_addfb_basic
bad-pitch-65536:
result: pass
set: kms_addfb_basic
bad-pitch-999:
result: pass
set: kms_addfb_basic
basic:
result: skip
set: kms_setmode
basic-auth:
result: pass
set: core_auth
basic-clone-single-crtc:
result: skip
set: kms_setmode
basic-x-tiled-legacy:
result: skip
set: kms_addfb_basic
basic-y-tiled-legacy:
result: skip
set: kms_addfb_basic
blob-multiple:
result: pass
set: kms_prop_blob
blob-prop-core:
result: pass
set: kms_prop_blob
blob-prop-lifetime:
result: pass
set: kms_prop_blob
blob-prop-validate:
result: pass
set: kms_prop_blob
bo-too-small:
result: skip
set: kms_addfb_basic
bo-too-small-due-to-tiling:
result: skip
set: kms_addfb_basic
clobberred-modifier:
result: skip
set: kms_addfb_basic
clone-exclusive-crtc:
result: skip
set: kms_setmode
core_getclient: pass
core_getstats: pass
core_getversion: pass
core_setmaster_vs_auth: pass
crtc-id:
result: skip
set: kms_vblank
crtc-invalid-params:
result: skip
set: kms_atomic
crtc-invalid-params-fence:
result: skip
set: kms_atomic
empty-block:
result: skip
set: drm_read
empty-nonblock:
result: skip
set: drm_read
fault-buffer:
result: skip
set: drm_read
framebuffer-vs-set-tiling:
result: skip
set: kms_addfb_basic
getclient-master-drop:
result: pass
set: core_auth
getclient-simple:
result: pass
set: core_auth
invalid:
result: skip
set: kms_vblank
invalid-buffer:
result: skip
set: drm_read
invalid-clone-exclusive-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc:
result: skip
set: kms_setmode
invalid-clone-single-crtc-stealing:
result: skip
set: kms_setmode
invalid-get-prop:
result: pass
set: kms_prop_blob
invalid-get-prop-any:
result: pass
set: kms_prop_blob
invalid-set-prop:
result: pass
set: kms_prop_blob
invalid-set-prop-any:
result: pass
set: kms_prop_blob
invalid-smem-bo-on-discrete:
result: skip
set: kms_addfb_basic
legacy-format:
result: pass
set: kms_addfb_basic
many-magics:
result: pass
set: core_auth
master-rmfb:
result: pass
set: kms_addfb_basic
no-handle:
result: pass
set: kms_addfb_basic
pipe-A-accuracy-idle:
result: skip
set: kms_vblank
pipe-A-query-busy:
result: skip
set: kms_vblank
pipe-A-query-busy-hang:
result: skip
set: kms_vblank
pipe-A-query-forked:
result: skip
set: kms_vblank
pipe-A-query-forked-busy:
result: skip
set: kms_vblank
pipe-A-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-A-query-forked-hang:
result: skip
set: kms_vblank
pipe-A-query-idle:
result: skip
set: kms_vblank
pipe-A-query-idle-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-A-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-A-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-A-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-A-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-A-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-A-wait-busy:
result: skip
set: kms_vblank
pipe-A-wait-busy-hang:
result: skip
set: kms_vblank
pipe-A-wait-forked:
result: skip
set: kms_vblank
pipe-A-wait-forked-busy:
result: skip
set: kms_vblank
pipe-A-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-A-wait-forked-hang:
result: skip
set: kms_vblank
pipe-A-wait-idle:
result: skip
set: kms_vblank
pipe-A-wait-idle-hang:
result: skip
set: kms_vblank
pipe-B-accuracy-idle:
result: skip
set: kms_vblank
pipe-B-query-busy:
result: skip
set: kms_vblank
pipe-B-query-busy-hang:
result: skip
set: kms_vblank
pipe-B-query-forked:
result: skip
set: kms_vblank
pipe-B-query-forked-busy:
result: skip
set: kms_vblank
pipe-B-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-B-query-forked-hang:
result: skip
set: kms_vblank
pipe-B-query-idle:
result: skip
set: kms_vblank
pipe-B-query-idle-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-B-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-B-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-B-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-B-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-B-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-B-wait-busy:
result: skip
set: kms_vblank
pipe-B-wait-busy-hang:
result: skip
set: kms_vblank
pipe-B-wait-forked:
result: skip
set: kms_vblank
pipe-B-wait-forked-busy:
result: skip
set: kms_vblank
pipe-B-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-B-wait-forked-hang:
result: skip
set: kms_vblank
pipe-B-wait-idle:
result: skip
set: kms_vblank
pipe-B-wait-idle-hang:
result: skip
set: kms_vblank
pipe-C-accuracy-idle:
result: skip
set: kms_vblank
pipe-C-query-busy:
result: skip
set: kms_vblank
pipe-C-query-busy-hang:
result: skip
set: kms_vblank
pipe-C-query-forked:
result: skip
set: kms_vblank
pipe-C-query-forked-busy:
result: skip
set: kms_vblank
pipe-C-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-C-query-forked-hang:
result: skip
set: kms_vblank
pipe-C-query-idle:
result: skip
set: kms_vblank
pipe-C-query-idle-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-C-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-C-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-C-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-C-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-C-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-C-wait-busy:
result: skip
set: kms_vblank
pipe-C-wait-busy-hang:
result: skip
set: kms_vblank
pipe-C-wait-forked:
result: skip
set: kms_vblank
pipe-C-wait-forked-busy:
result: skip
set: kms_vblank
pipe-C-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-C-wait-forked-hang:
result: skip
set: kms_vblank
pipe-C-wait-idle:
result: skip
set: kms_vblank
pipe-C-wait-idle-hang:
result: skip
set: kms_vblank
pipe-D-accuracy-idle:
result: skip
set: kms_vblank
pipe-D-query-busy:
result: skip
set: kms_vblank
pipe-D-query-busy-hang:
result: skip
set: kms_vblank
pipe-D-query-forked:
result: skip
set: kms_vblank
pipe-D-query-forked-busy:
result: skip
set: kms_vblank
pipe-D-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-D-query-forked-hang:
result: skip
set: kms_vblank
pipe-D-query-idle:
result: skip
set: kms_vblank
pipe-D-query-idle-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-D-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-D-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-D-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-D-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-D-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-D-wait-busy:
result: skip
set: kms_vblank
pipe-D-wait-busy-hang:
result: skip
set: kms_vblank
pipe-D-wait-forked:
result: skip
set: kms_vblank
pipe-D-wait-forked-busy:
result: skip
set: kms_vblank
pipe-D-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-D-wait-forked-hang:
result: skip
set: kms_vblank
pipe-D-wait-idle:
result: skip
set: kms_vblank
pipe-D-wait-idle-hang:
result: skip
set: kms_vblank
pipe-E-accuracy-idle:
result: skip
set: kms_vblank
pipe-E-query-busy:
result: skip
set: kms_vblank
pipe-E-query-busy-hang:
result: skip
set: kms_vblank
pipe-E-query-forked:
result: skip
set: kms_vblank
pipe-E-query-forked-busy:
result: skip
set: kms_vblank
pipe-E-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-E-query-forked-hang:
result: skip
set: kms_vblank
pipe-E-query-idle:
result: skip
set: kms_vblank
pipe-E-query-idle-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-E-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-E-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-E-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-E-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-E-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-E-wait-busy:
result: skip
set: kms_vblank
pipe-E-wait-busy-hang:
result: skip
set: kms_vblank
pipe-E-wait-forked:
result: skip
set: kms_vblank
pipe-E-wait-forked-busy:
result: skip
set: kms_vblank
pipe-E-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-E-wait-forked-hang:
result: skip
set: kms_vblank
pipe-E-wait-idle:
result: skip
set: kms_vblank
pipe-E-wait-idle-hang:
result: skip
set: kms_vblank
pipe-F-accuracy-idle:
result: skip
set: kms_vblank
pipe-F-query-busy:
result: skip
set: kms_vblank
pipe-F-query-busy-hang:
result: skip
set: kms_vblank
pipe-F-query-forked:
result: skip
set: kms_vblank
pipe-F-query-forked-busy:
result: skip
set: kms_vblank
pipe-F-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-F-query-forked-hang:
result: skip
set: kms_vblank
pipe-F-query-idle:
result: skip
set: kms_vblank
pipe-F-query-idle-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-F-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-F-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-F-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-F-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-F-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-F-wait-busy:
result: skip
set: kms_vblank
pipe-F-wait-busy-hang:
result: skip
set: kms_vblank
pipe-F-wait-forked:
result: skip
set: kms_vblank
pipe-F-wait-forked-busy:
result: skip
set: kms_vblank
pipe-F-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-F-wait-forked-hang:
result: skip
set: kms_vblank
pipe-F-wait-idle:
result: skip
set: kms_vblank
pipe-F-wait-idle-hang:
result: skip
set: kms_vblank
pipe-G-accuracy-idle:
result: skip
set: kms_vblank
pipe-G-query-busy:
result: skip
set: kms_vblank
pipe-G-query-busy-hang:
result: skip
set: kms_vblank
pipe-G-query-forked:
result: skip
set: kms_vblank
pipe-G-query-forked-busy:
result: skip
set: kms_vblank
pipe-G-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-G-query-forked-hang:
result: skip
set: kms_vblank
pipe-G-query-idle:
result: skip
set: kms_vblank
pipe-G-query-idle-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-G-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-G-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-G-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-G-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-G-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-G-wait-busy:
result: skip
set: kms_vblank
pipe-G-wait-busy-hang:
result: skip
set: kms_vblank
pipe-G-wait-forked:
result: skip
set: kms_vblank
pipe-G-wait-forked-busy:
result: skip
set: kms_vblank
pipe-G-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-G-wait-forked-hang:
result: skip
set: kms_vblank
pipe-G-wait-idle:
result: skip
set: kms_vblank
pipe-G-wait-idle-hang:
result: skip
set: kms_vblank
pipe-H-accuracy-idle:
result: skip
set: kms_vblank
pipe-H-query-busy:
result: skip
set: kms_vblank
pipe-H-query-busy-hang:
result: skip
set: kms_vblank
pipe-H-query-forked:
result: skip
set: kms_vblank
pipe-H-query-forked-busy:
result: skip
set: kms_vblank
pipe-H-query-forked-busy-hang:
result: skip
set: kms_vblank
pipe-H-query-forked-hang:
result: skip
set: kms_vblank
pipe-H-query-idle:
result: skip
set: kms_vblank
pipe-H-query-idle-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-dpms-rpm:
result: skip
set: kms_vblank
pipe-H-ts-continuation-dpms-suspend:
result: skip
set: kms_vblank
pipe-H-ts-continuation-idle:
result: skip
set: kms_vblank
pipe-H-ts-continuation-idle-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset-hang:
result: skip
set: kms_vblank
pipe-H-ts-continuation-modeset-rpm:
result: skip
set: kms_vblank
pipe-H-ts-continuation-suspend:
result: skip
set: kms_vblank
pipe-H-wait-busy:
result: skip
set: kms_vblank
pipe-H-wait-busy-hang:
result: skip
set: kms_vblank
pipe-H-wait-forked:
result: skip
set: kms_vblank
pipe-H-wait-forked-busy:
result: skip
set: kms_vblank
pipe-H-wait-forked-busy-hang:
result: skip
set: kms_vblank
pipe-H-wait-forked-hang:
result: skip
set: kms_vblank
pipe-H-wait-idle:
result: skip
set: kms_vblank
pipe-H-wait-idle-hang:
result: skip
set: kms_vblank
plane-cursor-legacy:
result: skip
set: kms_atomic
plane-immutable-zpos:
result: skip
set: kms_atomic
plane-invalid-params:
result: skip
set: kms_atomic
plane-invalid-params-fence:
result: skip
set: kms_atomic
plane-overlay-legacy:
result: skip
set: kms_atomic
plane-primary-legacy:
result: skip
set: kms_atomic
plane-primary-overlay-mutable-zpos:
result: skip
set: kms_atomic
short-buffer-block:
result: skip
set: drm_read
short-buffer-nonblock:
result: skip
set: drm_read
short-buffer-wakeup:
result: skip
set: drm_read
size-max:
result: skip
set: kms_addfb_basic
small-bo:
result: skip
set: kms_addfb_basic
test-only:
result: skip
set: kms_atomic
tile-pitch-mismatch:
result: skip
set: kms_addfb_basic
too-high:
result: skip
set: kms_addfb_basic
too-wide:
result: skip
set: kms_addfb_basic
unused-handle:
result: pass
set: kms_addfb_basic
unused-modifier:
result: pass
set: kms_addfb_basic
unused-offsets:
result: pass
set: kms_addfb_basic
unused-pitches:
result: pass
set: kms_addfb_basic
13969 11:19:18.146352 end: 3.1 lava-test-shell (duration 00:00:14) [common]
13970 11:19:18.146796 end: 3 lava-test-retry (duration 00:00:14) [common]
13971 11:19:18.147248 start: 4 finalize (timeout 00:07:48) [common]
13972 11:19:18.147675 start: 4.1 power-off (timeout 00:00:30) [common]
13973 11:19:18.148412 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-1' '--port=1' '--command=off'
13974 11:19:18.230420 >> Command sent successfully.
13975 11:19:18.234945 Returned 0 in 0 seconds
13976 11:19:18.335837 end: 4.1 power-off (duration 00:00:00) [common]
13978 11:19:18.337392 start: 4.2 read-feedback (timeout 00:07:48) [common]
13979 11:19:18.338657 Listened to connection for namespace 'common' for up to 1s
13980 11:19:19.339071 Finalising connection for namespace 'common'
13981 11:19:19.339286 Disconnecting from shell: Finalise
13982 11:19:19.339400 / #
13983 11:19:19.440013 end: 4.2 read-feedback (duration 00:00:01) [common]
13984 11:19:19.440653 end: 4 finalize (duration 00:00:01) [common]
13985 11:19:19.441240 Cleaning after the job
13986 11:19:19.441713 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591274/tftp-deploy-uqlzbi0t/ramdisk
13987 11:19:19.450204 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591274/tftp-deploy-uqlzbi0t/kernel
13988 11:19:19.455741 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591274/tftp-deploy-uqlzbi0t/dtb
13989 11:19:19.455891 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591274/tftp-deploy-uqlzbi0t/modules
13990 11:19:19.461012 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10591274
13991 11:19:19.557185 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10591274
13992 11:19:19.557366 Job finished correctly