Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 0
1 11:19:01.980672 lava-dispatcher, installed at version: 2023.05.1
2 11:19:01.980867 start: 0 validate
3 11:19:01.980996 Start time: 2023-06-05 11:19:01.980989+00:00 (UTC)
4 11:19:01.981116 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:19:01.981244 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
6 11:19:02.269210 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:19:02.269404 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:19:02.545219 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:19:02.545400 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:19:02.837276 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:19:02.837450 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbookworm-kselftest%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:19:03.124041 Using caching service: 'http://localhost/cache/?uri=%s'
13 11:19:03.124202 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 11:19:03.406802 validate duration: 1.43
16 11:19:03.407064 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:19:03.407171 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:19:03.407261 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:19:03.407386 Not decompressing ramdisk as can be used compressed.
20 11:19:03.407471 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20230527.0/arm64/initrd.cpio.gz
21 11:19:03.407537 saving as /var/lib/lava/dispatcher/tmp/10591284/tftp-deploy-n9bs2myb/ramdisk/initrd.cpio.gz
22 11:19:03.407615 total size: 5624321 (5MB)
23 11:19:03.408671 progress 0% (0MB)
24 11:19:03.410294 progress 5% (0MB)
25 11:19:03.411860 progress 10% (0MB)
26 11:19:03.413350 progress 15% (0MB)
27 11:19:03.414890 progress 20% (1MB)
28 11:19:03.416319 progress 25% (1MB)
29 11:19:03.417850 progress 30% (1MB)
30 11:19:03.419355 progress 35% (1MB)
31 11:19:03.420768 progress 40% (2MB)
32 11:19:03.422235 progress 45% (2MB)
33 11:19:03.423544 progress 50% (2MB)
34 11:19:03.425068 progress 55% (2MB)
35 11:19:03.426380 progress 60% (3MB)
36 11:19:03.427848 progress 65% (3MB)
37 11:19:03.429374 progress 70% (3MB)
38 11:19:03.430686 progress 75% (4MB)
39 11:19:03.432146 progress 80% (4MB)
40 11:19:03.433509 progress 85% (4MB)
41 11:19:03.434976 progress 90% (4MB)
42 11:19:03.436441 progress 95% (5MB)
43 11:19:03.437829 progress 100% (5MB)
44 11:19:03.438010 5MB downloaded in 0.03s (176.49MB/s)
45 11:19:03.438157 end: 1.1.1 http-download (duration 00:00:00) [common]
47 11:19:03.438391 end: 1.1 download-retry (duration 00:00:00) [common]
48 11:19:03.438475 start: 1.2 download-retry (timeout 00:10:00) [common]
49 11:19:03.438556 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 11:19:03.438676 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 11:19:03.438748 saving as /var/lib/lava/dispatcher/tmp/10591284/tftp-deploy-n9bs2myb/kernel/Image
52 11:19:03.438808 total size: 45746688 (43MB)
53 11:19:03.438867 No compression specified
54 11:19:03.439870 progress 0% (0MB)
55 11:19:03.451212 progress 5% (2MB)
56 11:19:03.462678 progress 10% (4MB)
57 11:19:03.474105 progress 15% (6MB)
58 11:19:03.485343 progress 20% (8MB)
59 11:19:03.496935 progress 25% (10MB)
60 11:19:03.508032 progress 30% (13MB)
61 11:19:03.519783 progress 35% (15MB)
62 11:19:03.531041 progress 40% (17MB)
63 11:19:03.542359 progress 45% (19MB)
64 11:19:03.553830 progress 50% (21MB)
65 11:19:03.565187 progress 55% (24MB)
66 11:19:03.576605 progress 60% (26MB)
67 11:19:03.587904 progress 65% (28MB)
68 11:19:03.599241 progress 70% (30MB)
69 11:19:03.610610 progress 75% (32MB)
70 11:19:03.621961 progress 80% (34MB)
71 11:19:03.633407 progress 85% (37MB)
72 11:19:03.644777 progress 90% (39MB)
73 11:19:03.655878 progress 95% (41MB)
74 11:19:03.667112 progress 100% (43MB)
75 11:19:03.667235 43MB downloaded in 0.23s (190.99MB/s)
76 11:19:03.667380 end: 1.2.1 http-download (duration 00:00:00) [common]
78 11:19:03.667614 end: 1.2 download-retry (duration 00:00:00) [common]
79 11:19:03.667704 start: 1.3 download-retry (timeout 00:10:00) [common]
80 11:19:03.667792 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 11:19:03.667928 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 11:19:03.667998 saving as /var/lib/lava/dispatcher/tmp/10591284/tftp-deploy-n9bs2myb/dtb/mt8192-asurada-spherion-r0.dtb
83 11:19:03.668059 total size: 46924 (0MB)
84 11:19:03.668119 No compression specified
85 11:19:03.669215 progress 69% (0MB)
86 11:19:03.669482 progress 100% (0MB)
87 11:19:03.669632 0MB downloaded in 0.00s (28.49MB/s)
88 11:19:03.669751 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:19:03.669977 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:19:03.670062 start: 1.4 download-retry (timeout 00:10:00) [common]
92 11:19:03.670145 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 11:19:03.670252 downloading http://storage.kernelci.org/images/rootfs/debian/bookworm-kselftest/20230527.0/arm64/full.rootfs.tar.xz
94 11:19:03.670320 saving as /var/lib/lava/dispatcher/tmp/10591284/tftp-deploy-n9bs2myb/nfsrootfs/full.rootfs.tar
95 11:19:03.670381 total size: 195125384 (186MB)
96 11:19:03.670441 Using unxz to decompress xz
97 11:19:03.673804 progress 0% (0MB)
98 11:19:04.211444 progress 5% (9MB)
99 11:19:04.699493 progress 10% (18MB)
100 11:19:05.265701 progress 15% (27MB)
101 11:19:05.536434 progress 20% (37MB)
102 11:19:05.976845 progress 25% (46MB)
103 11:19:06.530407 progress 30% (55MB)
104 11:19:07.071305 progress 35% (65MB)
105 11:19:07.611432 progress 40% (74MB)
106 11:19:08.167118 progress 45% (83MB)
107 11:19:08.757547 progress 50% (93MB)
108 11:19:09.345183 progress 55% (102MB)
109 11:19:09.974344 progress 60% (111MB)
110 11:19:10.358204 progress 65% (120MB)
111 11:19:10.435270 progress 70% (130MB)
112 11:19:10.581943 progress 75% (139MB)
113 11:19:10.652940 progress 80% (148MB)
114 11:19:10.697561 progress 85% (158MB)
115 11:19:10.784709 progress 90% (167MB)
116 11:19:11.148674 progress 95% (176MB)
117 11:19:11.709306 progress 100% (186MB)
118 11:19:11.715327 186MB downloaded in 8.04s (23.13MB/s)
119 11:19:11.715633 end: 1.4.1 http-download (duration 00:00:08) [common]
121 11:19:11.715897 end: 1.4 download-retry (duration 00:00:08) [common]
122 11:19:11.715987 start: 1.5 download-retry (timeout 00:09:52) [common]
123 11:19:11.716075 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 11:19:11.716224 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 11:19:11.716297 saving as /var/lib/lava/dispatcher/tmp/10591284/tftp-deploy-n9bs2myb/modules/modules.tar
126 11:19:11.716358 total size: 8547328 (8MB)
127 11:19:11.716420 Using unxz to decompress xz
128 11:19:11.719852 progress 0% (0MB)
129 11:19:11.741128 progress 5% (0MB)
130 11:19:11.765923 progress 10% (0MB)
131 11:19:11.791790 progress 15% (1MB)
132 11:19:11.816427 progress 20% (1MB)
133 11:19:11.842308 progress 25% (2MB)
134 11:19:11.867108 progress 30% (2MB)
135 11:19:11.892197 progress 35% (2MB)
136 11:19:11.916740 progress 40% (3MB)
137 11:19:11.942027 progress 45% (3MB)
138 11:19:11.965915 progress 50% (4MB)
139 11:19:11.988589 progress 55% (4MB)
140 11:19:12.013487 progress 60% (4MB)
141 11:19:12.039081 progress 65% (5MB)
142 11:19:12.064204 progress 70% (5MB)
143 11:19:12.090653 progress 75% (6MB)
144 11:19:12.119592 progress 80% (6MB)
145 11:19:12.142064 progress 85% (6MB)
146 11:19:12.167039 progress 90% (7MB)
147 11:19:12.190409 progress 95% (7MB)
148 11:19:12.213994 progress 100% (8MB)
149 11:19:12.219875 8MB downloaded in 0.50s (16.19MB/s)
150 11:19:12.220160 end: 1.5.1 http-download (duration 00:00:01) [common]
152 11:19:12.220424 end: 1.5 download-retry (duration 00:00:01) [common]
153 11:19:12.220519 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 11:19:12.220616 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 11:19:15.527269 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10591284/extract-nfsrootfs-85gyi42f
156 11:19:15.527487 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 11:19:15.527594 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 11:19:15.527768 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10591284/lava-overlay-ckmy6lk2
159 11:19:15.527900 makedir: /var/lib/lava/dispatcher/tmp/10591284/lava-overlay-ckmy6lk2/lava-10591284/bin
160 11:19:15.528005 makedir: /var/lib/lava/dispatcher/tmp/10591284/lava-overlay-ckmy6lk2/lava-10591284/tests
161 11:19:15.528103 makedir: /var/lib/lava/dispatcher/tmp/10591284/lava-overlay-ckmy6lk2/lava-10591284/results
162 11:19:15.528207 Creating /var/lib/lava/dispatcher/tmp/10591284/lava-overlay-ckmy6lk2/lava-10591284/bin/lava-add-keys
163 11:19:15.528350 Creating /var/lib/lava/dispatcher/tmp/10591284/lava-overlay-ckmy6lk2/lava-10591284/bin/lava-add-sources
164 11:19:15.528478 Creating /var/lib/lava/dispatcher/tmp/10591284/lava-overlay-ckmy6lk2/lava-10591284/bin/lava-background-process-start
165 11:19:15.528654 Creating /var/lib/lava/dispatcher/tmp/10591284/lava-overlay-ckmy6lk2/lava-10591284/bin/lava-background-process-stop
166 11:19:15.528781 Creating /var/lib/lava/dispatcher/tmp/10591284/lava-overlay-ckmy6lk2/lava-10591284/bin/lava-common-functions
167 11:19:15.528903 Creating /var/lib/lava/dispatcher/tmp/10591284/lava-overlay-ckmy6lk2/lava-10591284/bin/lava-echo-ipv4
168 11:19:15.529026 Creating /var/lib/lava/dispatcher/tmp/10591284/lava-overlay-ckmy6lk2/lava-10591284/bin/lava-install-packages
169 11:19:15.529147 Creating /var/lib/lava/dispatcher/tmp/10591284/lava-overlay-ckmy6lk2/lava-10591284/bin/lava-installed-packages
170 11:19:15.529266 Creating /var/lib/lava/dispatcher/tmp/10591284/lava-overlay-ckmy6lk2/lava-10591284/bin/lava-os-build
171 11:19:15.529392 Creating /var/lib/lava/dispatcher/tmp/10591284/lava-overlay-ckmy6lk2/lava-10591284/bin/lava-probe-channel
172 11:19:15.529512 Creating /var/lib/lava/dispatcher/tmp/10591284/lava-overlay-ckmy6lk2/lava-10591284/bin/lava-probe-ip
173 11:19:15.529633 Creating /var/lib/lava/dispatcher/tmp/10591284/lava-overlay-ckmy6lk2/lava-10591284/bin/lava-target-ip
174 11:19:15.529756 Creating /var/lib/lava/dispatcher/tmp/10591284/lava-overlay-ckmy6lk2/lava-10591284/bin/lava-target-mac
175 11:19:15.529876 Creating /var/lib/lava/dispatcher/tmp/10591284/lava-overlay-ckmy6lk2/lava-10591284/bin/lava-target-storage
176 11:19:15.530001 Creating /var/lib/lava/dispatcher/tmp/10591284/lava-overlay-ckmy6lk2/lava-10591284/bin/lava-test-case
177 11:19:15.530124 Creating /var/lib/lava/dispatcher/tmp/10591284/lava-overlay-ckmy6lk2/lava-10591284/bin/lava-test-event
178 11:19:15.530245 Creating /var/lib/lava/dispatcher/tmp/10591284/lava-overlay-ckmy6lk2/lava-10591284/bin/lava-test-feedback
179 11:19:15.530365 Creating /var/lib/lava/dispatcher/tmp/10591284/lava-overlay-ckmy6lk2/lava-10591284/bin/lava-test-raise
180 11:19:15.530486 Creating /var/lib/lava/dispatcher/tmp/10591284/lava-overlay-ckmy6lk2/lava-10591284/bin/lava-test-reference
181 11:19:15.530606 Creating /var/lib/lava/dispatcher/tmp/10591284/lava-overlay-ckmy6lk2/lava-10591284/bin/lava-test-runner
182 11:19:15.530726 Creating /var/lib/lava/dispatcher/tmp/10591284/lava-overlay-ckmy6lk2/lava-10591284/bin/lava-test-set
183 11:19:15.530846 Creating /var/lib/lava/dispatcher/tmp/10591284/lava-overlay-ckmy6lk2/lava-10591284/bin/lava-test-shell
184 11:19:15.530969 Updating /var/lib/lava/dispatcher/tmp/10591284/lava-overlay-ckmy6lk2/lava-10591284/bin/lava-add-keys (debian)
185 11:19:15.531123 Updating /var/lib/lava/dispatcher/tmp/10591284/lava-overlay-ckmy6lk2/lava-10591284/bin/lava-add-sources (debian)
186 11:19:15.531262 Updating /var/lib/lava/dispatcher/tmp/10591284/lava-overlay-ckmy6lk2/lava-10591284/bin/lava-install-packages (debian)
187 11:19:15.531409 Updating /var/lib/lava/dispatcher/tmp/10591284/lava-overlay-ckmy6lk2/lava-10591284/bin/lava-installed-packages (debian)
188 11:19:15.531547 Updating /var/lib/lava/dispatcher/tmp/10591284/lava-overlay-ckmy6lk2/lava-10591284/bin/lava-os-build (debian)
189 11:19:15.531666 Creating /var/lib/lava/dispatcher/tmp/10591284/lava-overlay-ckmy6lk2/lava-10591284/environment
190 11:19:15.531763 LAVA metadata
191 11:19:15.531834 - LAVA_JOB_ID=10591284
192 11:19:15.531898 - LAVA_DISPATCHER_IP=192.168.201.1
193 11:19:15.532001 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 11:19:15.532067 skipped lava-vland-overlay
195 11:19:15.532143 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 11:19:15.532222 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 11:19:15.532283 skipped lava-multinode-overlay
198 11:19:15.532355 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 11:19:15.532433 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 11:19:15.532505 Loading test definitions
201 11:19:15.532783 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 11:19:15.532859 Using /lava-10591284 at stage 0
203 11:19:15.533143 uuid=10591284_1.6.2.3.1 testdef=None
204 11:19:15.533247 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 11:19:15.533347 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 11:19:15.533785 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 11:19:15.534010 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 11:19:15.534552 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 11:19:15.534784 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 11:19:15.535309 runner path: /var/lib/lava/dispatcher/tmp/10591284/lava-overlay-ckmy6lk2/lava-10591284/0/tests/0_timesync-off test_uuid 10591284_1.6.2.3.1
213 11:19:15.535459 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 11:19:15.535686 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 11:19:15.535760 Using /lava-10591284 at stage 0
217 11:19:15.535857 Fetching tests from https://github.com/kernelci/test-definitions.git
218 11:19:15.535939 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/10591284/lava-overlay-ckmy6lk2/lava-10591284/0/tests/1_kselftest-alsa'
219 11:19:19.057162 Running '/usr/bin/git checkout kernelci.org
220 11:19:19.119035 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10591284/lava-overlay-ckmy6lk2/lava-10591284/0/tests/1_kselftest-alsa/automated/linux/kselftest/kselftest.yaml
221 11:19:19.119745 uuid=10591284_1.6.2.3.5 testdef=None
222 11:19:19.119908 end: 1.6.2.3.5 git-repo-action (duration 00:00:04) [common]
224 11:19:19.120152 start: 1.6.2.3.6 test-overlay (timeout 00:09:44) [common]
225 11:19:19.120944 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 11:19:19.121185 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:44) [common]
228 11:19:19.122135 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 11:19:19.122374 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:44) [common]
231 11:19:19.123292 runner path: /var/lib/lava/dispatcher/tmp/10591284/lava-overlay-ckmy6lk2/lava-10591284/0/tests/1_kselftest-alsa test_uuid 10591284_1.6.2.3.5
232 11:19:19.123386 BOARD='mt8192-asurada-spherion-r0'
233 11:19:19.123452 BRANCH='cip'
234 11:19:19.123515 SKIPFILE='/dev/null'
235 11:19:19.123575 SKIP_INSTALL='True'
236 11:19:19.123632 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 11:19:19.123691 TST_CASENAME=''
238 11:19:19.123749 TST_CMDFILES='alsa'
239 11:19:19.123895 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 11:19:19.124103 Creating lava-test-runner.conf files
242 11:19:19.124169 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10591284/lava-overlay-ckmy6lk2/lava-10591284/0 for stage 0
243 11:19:19.124263 - 0_timesync-off
244 11:19:19.124332 - 1_kselftest-alsa
245 11:19:19.124429 end: 1.6.2.3 test-definition (duration 00:00:04) [common]
246 11:19:19.124525 start: 1.6.2.4 compress-overlay (timeout 00:09:44) [common]
247 11:19:26.590070 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 11:19:26.590225 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:37) [common]
249 11:19:26.590357 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 11:19:26.590458 end: 1.6.2 lava-overlay (duration 00:00:11) [common]
251 11:19:26.590548 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:37) [common]
252 11:19:26.748434 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 11:19:26.748861 start: 1.6.4 extract-modules (timeout 00:09:37) [common]
254 11:19:26.748974 extracting modules file /var/lib/lava/dispatcher/tmp/10591284/tftp-deploy-n9bs2myb/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10591284/extract-nfsrootfs-85gyi42f
255 11:19:26.950104 extracting modules file /var/lib/lava/dispatcher/tmp/10591284/tftp-deploy-n9bs2myb/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10591284/extract-overlay-ramdisk-pmjw_b_o/ramdisk
256 11:19:27.153846 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 11:19:27.154024 start: 1.6.5 apply-overlay-tftp (timeout 00:09:36) [common]
258 11:19:27.154124 [common] Applying overlay to NFS
259 11:19:27.154224 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10591284/compress-overlay-nukstcc1/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10591284/extract-nfsrootfs-85gyi42f
260 11:19:28.038661 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 11:19:28.038826 start: 1.6.6 configure-preseed-file (timeout 00:09:35) [common]
262 11:19:28.038933 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 11:19:28.039027 start: 1.6.7 compress-ramdisk (timeout 00:09:35) [common]
264 11:19:28.039112 Building ramdisk /var/lib/lava/dispatcher/tmp/10591284/extract-overlay-ramdisk-pmjw_b_o/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10591284/extract-overlay-ramdisk-pmjw_b_o/ramdisk
265 11:19:28.367410 >> 128923 blocks
266 11:19:30.361406 rename /var/lib/lava/dispatcher/tmp/10591284/extract-overlay-ramdisk-pmjw_b_o/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10591284/tftp-deploy-n9bs2myb/ramdisk/ramdisk.cpio.gz
267 11:19:30.361820 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 11:19:30.361945 start: 1.6.8 prepare-kernel (timeout 00:09:33) [common]
269 11:19:30.362041 start: 1.6.8.1 prepare-fit (timeout 00:09:33) [common]
270 11:19:30.362149 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10591284/tftp-deploy-n9bs2myb/kernel/Image'
271 11:19:41.608060 Returned 0 in 11 seconds
272 11:19:41.709010 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10591284/tftp-deploy-n9bs2myb/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10591284/tftp-deploy-n9bs2myb/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10591284/tftp-deploy-n9bs2myb/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10591284/tftp-deploy-n9bs2myb/kernel/image.itb
273 11:19:42.075514 output: FIT description: Kernel Image image with one or more FDT blobs
274 11:19:42.075865 output: Created: Mon Jun 5 12:19:42 2023
275 11:19:42.075944 output: Image 0 (kernel-1)
276 11:19:42.076012 output: Description:
277 11:19:42.076076 output: Created: Mon Jun 5 12:19:42 2023
278 11:19:42.076139 output: Type: Kernel Image
279 11:19:42.076202 output: Compression: lzma compressed
280 11:19:42.076262 output: Data Size: 10086024 Bytes = 9849.63 KiB = 9.62 MiB
281 11:19:42.076322 output: Architecture: AArch64
282 11:19:42.076381 output: OS: Linux
283 11:19:42.076441 output: Load Address: 0x00000000
284 11:19:42.076498 output: Entry Point: 0x00000000
285 11:19:42.076599 output: Hash algo: crc32
286 11:19:42.076654 output: Hash value: eb1cf9b8
287 11:19:42.076708 output: Image 1 (fdt-1)
288 11:19:42.076762 output: Description: mt8192-asurada-spherion-r0
289 11:19:42.076815 output: Created: Mon Jun 5 12:19:42 2023
290 11:19:42.076870 output: Type: Flat Device Tree
291 11:19:42.076923 output: Compression: uncompressed
292 11:19:42.076977 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
293 11:19:42.077031 output: Architecture: AArch64
294 11:19:42.077084 output: Hash algo: crc32
295 11:19:42.077138 output: Hash value: 1df858fa
296 11:19:42.077191 output: Image 2 (ramdisk-1)
297 11:19:42.077244 output: Description: unavailable
298 11:19:42.077297 output: Created: Mon Jun 5 12:19:42 2023
299 11:19:42.077350 output: Type: RAMDisk Image
300 11:19:42.077404 output: Compression: Unknown Compression
301 11:19:42.077458 output: Data Size: 18603978 Bytes = 18167.95 KiB = 17.74 MiB
302 11:19:42.077511 output: Architecture: AArch64
303 11:19:42.077564 output: OS: Linux
304 11:19:42.077617 output: Load Address: unavailable
305 11:19:42.077670 output: Entry Point: unavailable
306 11:19:42.077723 output: Hash algo: crc32
307 11:19:42.077776 output: Hash value: ca977422
308 11:19:42.077828 output: Default Configuration: 'conf-1'
309 11:19:42.077881 output: Configuration 0 (conf-1)
310 11:19:42.077934 output: Description: mt8192-asurada-spherion-r0
311 11:19:42.077987 output: Kernel: kernel-1
312 11:19:42.078041 output: Init Ramdisk: ramdisk-1
313 11:19:42.078094 output: FDT: fdt-1
314 11:19:42.078147 output: Loadables: kernel-1
315 11:19:42.078200 output:
316 11:19:42.078389 end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
317 11:19:42.078484 end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
318 11:19:42.078585 end: 1.6 prepare-tftp-overlay (duration 00:00:30) [common]
319 11:19:42.078705 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:21) [common]
320 11:19:42.078819 No LXC device requested
321 11:19:42.078919 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 11:19:42.079008 start: 1.8 deploy-device-env (timeout 00:09:21) [common]
323 11:19:42.079089 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 11:19:42.079162 Checking files for TFTP limit of 4294967296 bytes.
325 11:19:42.079646 end: 1 tftp-deploy (duration 00:00:39) [common]
326 11:19:42.079758 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 11:19:42.079855 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 11:19:42.079983 substitutions:
329 11:19:42.080050 - {DTB}: 10591284/tftp-deploy-n9bs2myb/dtb/mt8192-asurada-spherion-r0.dtb
330 11:19:42.080114 - {INITRD}: 10591284/tftp-deploy-n9bs2myb/ramdisk/ramdisk.cpio.gz
331 11:19:42.080173 - {KERNEL}: 10591284/tftp-deploy-n9bs2myb/kernel/Image
332 11:19:42.080232 - {LAVA_MAC}: None
333 11:19:42.080289 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10591284/extract-nfsrootfs-85gyi42f
334 11:19:42.080346 - {NFS_SERVER_IP}: 192.168.201.1
335 11:19:42.080401 - {PRESEED_CONFIG}: None
336 11:19:42.080456 - {PRESEED_LOCAL}: None
337 11:19:42.080510 - {RAMDISK}: 10591284/tftp-deploy-n9bs2myb/ramdisk/ramdisk.cpio.gz
338 11:19:42.080613 - {ROOT_PART}: None
339 11:19:42.080668 - {ROOT}: None
340 11:19:42.080724 - {SERVER_IP}: 192.168.201.1
341 11:19:42.080779 - {TEE}: None
342 11:19:42.080834 Parsed boot commands:
343 11:19:42.080887 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 11:19:42.081058 Parsed boot commands: tftpboot 192.168.201.1 10591284/tftp-deploy-n9bs2myb/kernel/image.itb 10591284/tftp-deploy-n9bs2myb/kernel/cmdline
345 11:19:42.081149 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 11:19:42.081233 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 11:19:42.081325 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 11:19:42.081411 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 11:19:42.081482 Not connected, no need to disconnect.
350 11:19:42.081557 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 11:19:42.081639 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 11:19:42.081706 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-9'
353 11:19:42.085152 Setting prompt string to ['lava-test: # ']
354 11:19:42.085511 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 11:19:42.085622 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 11:19:42.085725 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 11:19:42.085817 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 11:19:42.086013 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
359 11:19:47.219799 >> Command sent successfully.
360 11:19:47.222132 Returned 0 in 5 seconds
361 11:19:47.322483 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 11:19:47.322798 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 11:19:47.322899 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 11:19:47.322987 Setting prompt string to 'Starting depthcharge on Spherion...'
366 11:19:47.323054 Changing prompt to 'Starting depthcharge on Spherion...'
367 11:19:47.323125 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 11:19:47.323386 [Enter `^Ec?' for help]
369 11:19:47.495405
370 11:19:47.495544
371 11:19:47.495614 F0: 102B 0000
372 11:19:47.495678
373 11:19:47.495738 F3: 1001 0000 [0200]
374 11:19:47.495797
375 11:19:47.499255 F3: 1001 0000
376 11:19:47.499340
377 11:19:47.499407 F7: 102D 0000
378 11:19:47.499469
379 11:19:47.502024 F1: 0000 0000
380 11:19:47.502110
381 11:19:47.502176 V0: 0000 0000 [0001]
382 11:19:47.502238
383 11:19:47.505842 00: 0007 8000
384 11:19:47.505930
385 11:19:47.505996 01: 0000 0000
386 11:19:47.506066
387 11:19:47.509426 BP: 0C00 0209 [0000]
388 11:19:47.509510
389 11:19:47.509576 G0: 1182 0000
390 11:19:47.509638
391 11:19:47.509696 EC: 0000 0021 [4000]
392 11:19:47.509754
393 11:19:47.512672 S7: 0000 0000 [0000]
394 11:19:47.512762
395 11:19:47.512834 CC: 0000 0000 [0001]
396 11:19:47.512897
397 11:19:47.516143 T0: 0000 0040 [010F]
398 11:19:47.516236
399 11:19:47.516302 Jump to BL
400 11:19:47.516364
401 11:19:47.542123
402 11:19:47.542209
403 11:19:47.542274
404 11:19:47.548752 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 11:19:47.552152 ARM64: Exception handlers installed.
406 11:19:47.555677 ARM64: Testing exception
407 11:19:47.559772 ARM64: Done test exception
408 11:19:47.566912 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 11:19:47.577250 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 11:19:47.584764 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 11:19:47.596077 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 11:19:47.599289 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 11:19:47.609946 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 11:19:47.619824 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 11:19:47.626223 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 11:19:47.645603 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 11:19:47.648032 WDT: Last reset was cold boot
418 11:19:47.651793 SPI1(PAD0) initialized at 2873684 Hz
419 11:19:47.655647 SPI5(PAD0) initialized at 992727 Hz
420 11:19:47.658385 VBOOT: Loading verstage.
421 11:19:47.665008 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 11:19:47.668065 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 11:19:47.671627 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 11:19:47.675005 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 11:19:47.682426 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 11:19:47.689135 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 11:19:47.700242 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 11:19:47.700329
429 11:19:47.700395
430 11:19:47.709945 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 11:19:47.713502 ARM64: Exception handlers installed.
432 11:19:47.716735 ARM64: Testing exception
433 11:19:47.716825 ARM64: Done test exception
434 11:19:47.723450 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 11:19:47.726618 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 11:19:47.741252 Probing TPM: . done!
437 11:19:47.741335 TPM ready after 0 ms
438 11:19:47.747628 Connected to device vid:did:rid of 1ae0:0028:00
439 11:19:47.754148 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
440 11:19:47.796213 Initialized TPM device CR50 revision 0
441 11:19:47.807977 tlcl_send_startup: Startup return code is 0
442 11:19:47.808063 TPM: setup succeeded
443 11:19:47.820662 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 11:19:47.828870 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 11:19:47.839582 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 11:19:47.848191 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 11:19:47.851356 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 11:19:47.854811 in-header: 03 07 00 00 08 00 00 00
449 11:19:47.858307 in-data: aa e4 47 04 13 02 00 00
450 11:19:47.861387 Chrome EC: UHEPI supported
451 11:19:47.867762 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 11:19:47.871398 in-header: 03 ad 00 00 08 00 00 00
453 11:19:47.874203 in-data: 00 20 20 08 00 00 00 00
454 11:19:47.874287 Phase 1
455 11:19:47.877591 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 11:19:47.884752 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 11:19:47.891239 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 11:19:47.894848 Recovery requested (1009000e)
459 11:19:47.898141 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 11:19:47.906856 tlcl_extend: response is 0
461 11:19:47.914863 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 11:19:47.920133 tlcl_extend: response is 0
463 11:19:47.926620 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 11:19:47.947356 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
465 11:19:47.954324 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 11:19:47.954408
467 11:19:47.954474
468 11:19:47.964960 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 11:19:47.968281 ARM64: Exception handlers installed.
470 11:19:47.971160 ARM64: Testing exception
471 11:19:47.971243 ARM64: Done test exception
472 11:19:47.993494 pmic_efuse_setting: Set efuses in 11 msecs
473 11:19:47.996792 pmwrap_interface_init: Select PMIF_VLD_RDY
474 11:19:48.004368 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 11:19:48.007052 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 11:19:48.010498 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 11:19:48.017406 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 11:19:48.020120 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 11:19:48.027402 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 11:19:48.030438 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 11:19:48.037225 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 11:19:48.040800 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 11:19:48.044098 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 11:19:48.050535 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 11:19:48.053644 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 11:19:48.057166 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 11:19:48.064335 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 11:19:48.071210 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 11:19:48.077815 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 11:19:48.080757 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 11:19:48.087493 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 11:19:48.093968 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 11:19:48.100821 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 11:19:48.104248 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 11:19:48.111717 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 11:19:48.115372 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 11:19:48.122426 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 11:19:48.125660 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 11:19:48.132158 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 11:19:48.135798 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 11:19:48.143101 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 11:19:48.146652 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 11:19:48.153156 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 11:19:48.156957 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 11:19:48.163456 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 11:19:48.166861 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 11:19:48.173519 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 11:19:48.176838 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 11:19:48.183352 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 11:19:48.186578 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 11:19:48.193389 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 11:19:48.197713 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 11:19:48.200985 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 11:19:48.204463 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 11:19:48.207831 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 11:19:48.214672 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 11:19:48.218068 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 11:19:48.221222 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 11:19:48.227947 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 11:19:48.231481 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 11:19:48.234518 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 11:19:48.241072 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 11:19:48.244749 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 11:19:48.248195 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 11:19:48.254409 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 11:19:48.264602 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 11:19:48.268414 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 11:19:48.278441 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 11:19:48.284072 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 11:19:48.290694 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 11:19:48.294095 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 11:19:48.297589 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 11:19:48.305452 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x2e
534 11:19:48.312213 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 11:19:48.315553 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
536 11:19:48.321855 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 11:19:48.330352 [RTC]rtc_get_frequency_meter,154: input=15, output=834
538 11:19:48.339565 [RTC]rtc_get_frequency_meter,154: input=7, output=709
539 11:19:48.349227 [RTC]rtc_get_frequency_meter,154: input=11, output=772
540 11:19:48.358792 [RTC]rtc_get_frequency_meter,154: input=13, output=803
541 11:19:48.368471 [RTC]rtc_get_frequency_meter,154: input=12, output=787
542 11:19:48.377466 [RTC]rtc_get_frequency_meter,154: input=12, output=787
543 11:19:48.386835 [RTC]rtc_get_frequency_meter,154: input=13, output=803
544 11:19:48.390376 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
545 11:19:48.397745 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
546 11:19:48.401214 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 11:19:48.404111 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 11:19:48.410597 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 11:19:48.414303 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 11:19:48.417537 ADC[4]: Raw value=905988 ID=7
551 11:19:48.417622 ADC[3]: Raw value=213282 ID=1
552 11:19:48.420721 RAM Code: 0x71
553 11:19:48.424379 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 11:19:48.430546 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 11:19:48.437355 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 11:19:48.443779 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 11:19:48.446976 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 11:19:48.450205 in-header: 03 07 00 00 08 00 00 00
559 11:19:48.453777 in-data: aa e4 47 04 13 02 00 00
560 11:19:48.456804 Chrome EC: UHEPI supported
561 11:19:48.463709 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 11:19:48.466951 in-header: 03 dd 00 00 08 00 00 00
563 11:19:48.470028 in-data: 90 20 60 08 00 00 00 00
564 11:19:48.473489 MRC: failed to locate region type 0.
565 11:19:48.479954 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 11:19:48.483499 DRAM-K: Running full calibration
567 11:19:48.489909 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 11:19:48.493187 header.status = 0x0
569 11:19:48.496375 header.version = 0x6 (expected: 0x6)
570 11:19:48.499705 header.size = 0xd00 (expected: 0xd00)
571 11:19:48.499807 header.flags = 0x0
572 11:19:48.506254 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 11:19:48.523523 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
574 11:19:48.530273 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 11:19:48.533746 dram_init: ddr_geometry: 2
576 11:19:48.537133 [EMI] MDL number = 2
577 11:19:48.537234 [EMI] Get MDL freq = 0
578 11:19:48.540661 dram_init: ddr_type: 0
579 11:19:48.540734 is_discrete_lpddr4: 1
580 11:19:48.543794 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 11:19:48.543899
582 11:19:48.543989
583 11:19:48.546981 [Bian_co] ETT version 0.0.0.1
584 11:19:48.554001 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 11:19:48.554078
586 11:19:48.557031 dramc_set_vcore_voltage set vcore to 650000
587 11:19:48.560309 Read voltage for 800, 4
588 11:19:48.560415 Vio18 = 0
589 11:19:48.560506 Vcore = 650000
590 11:19:48.563663 Vdram = 0
591 11:19:48.563761 Vddq = 0
592 11:19:48.563858 Vmddr = 0
593 11:19:48.566749 dram_init: config_dvfs: 1
594 11:19:48.570476 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 11:19:48.577348 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 11:19:48.580354 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
597 11:19:48.583750 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
598 11:19:48.587567 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
599 11:19:48.590598 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
600 11:19:48.593445 MEM_TYPE=3, freq_sel=18
601 11:19:48.596996 sv_algorithm_assistance_LP4_1600
602 11:19:48.600001 ============ PULL DRAM RESETB DOWN ============
603 11:19:48.607054 ========== PULL DRAM RESETB DOWN end =========
604 11:19:48.610014 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 11:19:48.613319 ===================================
606 11:19:48.616810 LPDDR4 DRAM CONFIGURATION
607 11:19:48.620405 ===================================
608 11:19:48.620505 EX_ROW_EN[0] = 0x0
609 11:19:48.623159 EX_ROW_EN[1] = 0x0
610 11:19:48.623246 LP4Y_EN = 0x0
611 11:19:48.626638 WORK_FSP = 0x0
612 11:19:48.626724 WL = 0x2
613 11:19:48.630110 RL = 0x2
614 11:19:48.630197 BL = 0x2
615 11:19:48.633690 RPST = 0x0
616 11:19:48.633776 RD_PRE = 0x0
617 11:19:48.636433 WR_PRE = 0x1
618 11:19:48.636541 WR_PST = 0x0
619 11:19:48.640632 DBI_WR = 0x0
620 11:19:48.643304 DBI_RD = 0x0
621 11:19:48.643389 OTF = 0x1
622 11:19:48.646562 ===================================
623 11:19:48.650136 ===================================
624 11:19:48.650222 ANA top config
625 11:19:48.653461 ===================================
626 11:19:48.657067 DLL_ASYNC_EN = 0
627 11:19:48.659546 ALL_SLAVE_EN = 1
628 11:19:48.663275 NEW_RANK_MODE = 1
629 11:19:48.666661 DLL_IDLE_MODE = 1
630 11:19:48.666747 LP45_APHY_COMB_EN = 1
631 11:19:48.669989 TX_ODT_DIS = 1
632 11:19:48.672744 NEW_8X_MODE = 1
633 11:19:48.676211 ===================================
634 11:19:48.679858 ===================================
635 11:19:48.683531 data_rate = 1600
636 11:19:48.686267 CKR = 1
637 11:19:48.686350 DQ_P2S_RATIO = 8
638 11:19:48.689967 ===================================
639 11:19:48.693118 CA_P2S_RATIO = 8
640 11:19:48.696578 DQ_CA_OPEN = 0
641 11:19:48.699750 DQ_SEMI_OPEN = 0
642 11:19:48.703547 CA_SEMI_OPEN = 0
643 11:19:48.706222 CA_FULL_RATE = 0
644 11:19:48.706305 DQ_CKDIV4_EN = 1
645 11:19:48.709769 CA_CKDIV4_EN = 1
646 11:19:48.713089 CA_PREDIV_EN = 0
647 11:19:48.716768 PH8_DLY = 0
648 11:19:48.719570 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 11:19:48.722958 DQ_AAMCK_DIV = 4
650 11:19:48.723041 CA_AAMCK_DIV = 4
651 11:19:48.726229 CA_ADMCK_DIV = 4
652 11:19:48.729512 DQ_TRACK_CA_EN = 0
653 11:19:48.732955 CA_PICK = 800
654 11:19:48.736361 CA_MCKIO = 800
655 11:19:48.739628 MCKIO_SEMI = 0
656 11:19:48.742718 PLL_FREQ = 3068
657 11:19:48.742802 DQ_UI_PI_RATIO = 32
658 11:19:48.746163 CA_UI_PI_RATIO = 0
659 11:19:48.749515 ===================================
660 11:19:48.752530 ===================================
661 11:19:48.756238 memory_type:LPDDR4
662 11:19:48.759092 GP_NUM : 10
663 11:19:48.759191 SRAM_EN : 1
664 11:19:48.762964 MD32_EN : 0
665 11:19:48.765989 ===================================
666 11:19:48.766071 [ANA_INIT] >>>>>>>>>>>>>>
667 11:19:48.769141 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 11:19:48.772671 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 11:19:48.776014 ===================================
670 11:19:48.779634 data_rate = 1600,PCW = 0X7600
671 11:19:48.782955 ===================================
672 11:19:48.785751 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 11:19:48.792832 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 11:19:48.799434 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 11:19:48.802468 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 11:19:48.805886 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 11:19:48.809445 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 11:19:48.812964 [ANA_INIT] flow start
679 11:19:48.813047 [ANA_INIT] PLL >>>>>>>>
680 11:19:48.815963 [ANA_INIT] PLL <<<<<<<<
681 11:19:48.820093 [ANA_INIT] MIDPI >>>>>>>>
682 11:19:48.820176 [ANA_INIT] MIDPI <<<<<<<<
683 11:19:48.823081 [ANA_INIT] DLL >>>>>>>>
684 11:19:48.826045 [ANA_INIT] flow end
685 11:19:48.829394 ============ LP4 DIFF to SE enter ============
686 11:19:48.832499 ============ LP4 DIFF to SE exit ============
687 11:19:48.836393 [ANA_INIT] <<<<<<<<<<<<<
688 11:19:48.839436 [Flow] Enable top DCM control >>>>>
689 11:19:48.842539 [Flow] Enable top DCM control <<<<<
690 11:19:48.845704 Enable DLL master slave shuffle
691 11:19:48.848997 ==============================================================
692 11:19:48.852442 Gating Mode config
693 11:19:48.859246 ==============================================================
694 11:19:48.859330 Config description:
695 11:19:48.869309 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 11:19:48.875745 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 11:19:48.878964 SELPH_MODE 0: By rank 1: By Phase
698 11:19:48.885357 ==============================================================
699 11:19:48.889490 GAT_TRACK_EN = 1
700 11:19:48.892013 RX_GATING_MODE = 2
701 11:19:48.895984 RX_GATING_TRACK_MODE = 2
702 11:19:48.899055 SELPH_MODE = 1
703 11:19:48.901980 PICG_EARLY_EN = 1
704 11:19:48.905498 VALID_LAT_VALUE = 1
705 11:19:48.908557 ==============================================================
706 11:19:48.911775 Enter into Gating configuration >>>>
707 11:19:48.915202 Exit from Gating configuration <<<<
708 11:19:48.918838 Enter into DVFS_PRE_config >>>>>
709 11:19:48.932504 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 11:19:48.932631 Exit from DVFS_PRE_config <<<<<
711 11:19:48.935337 Enter into PICG configuration >>>>
712 11:19:48.938582 Exit from PICG configuration <<<<
713 11:19:48.942463 [RX_INPUT] configuration >>>>>
714 11:19:48.945879 [RX_INPUT] configuration <<<<<
715 11:19:48.952759 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 11:19:48.955279 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 11:19:48.962918 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 11:19:48.969946 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 11:19:48.973479 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 11:19:48.981169 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 11:19:48.984242 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 11:19:48.987602 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 11:19:48.991695 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 11:19:48.998893 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 11:19:49.002507 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 11:19:49.006025 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 11:19:49.009628 ===================================
728 11:19:49.013251 LPDDR4 DRAM CONFIGURATION
729 11:19:49.013336 ===================================
730 11:19:49.016977 EX_ROW_EN[0] = 0x0
731 11:19:49.021114 EX_ROW_EN[1] = 0x0
732 11:19:49.021200 LP4Y_EN = 0x0
733 11:19:49.021286 WORK_FSP = 0x0
734 11:19:49.024358 WL = 0x2
735 11:19:49.024452 RL = 0x2
736 11:19:49.027981 BL = 0x2
737 11:19:49.028158 RPST = 0x0
738 11:19:49.031741 RD_PRE = 0x0
739 11:19:49.031867 WR_PRE = 0x1
740 11:19:49.035324 WR_PST = 0x0
741 11:19:49.035409 DBI_WR = 0x0
742 11:19:49.039695 DBI_RD = 0x0
743 11:19:49.039779 OTF = 0x1
744 11:19:49.043062 ===================================
745 11:19:49.046642 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 11:19:49.050006 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 11:19:49.056902 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 11:19:49.056987 ===================================
749 11:19:49.060509 LPDDR4 DRAM CONFIGURATION
750 11:19:49.064202 ===================================
751 11:19:49.067946 EX_ROW_EN[0] = 0x10
752 11:19:49.068031 EX_ROW_EN[1] = 0x0
753 11:19:49.071721 LP4Y_EN = 0x0
754 11:19:49.071804 WORK_FSP = 0x0
755 11:19:49.071871 WL = 0x2
756 11:19:49.075753 RL = 0x2
757 11:19:49.075837 BL = 0x2
758 11:19:49.079597 RPST = 0x0
759 11:19:49.079681 RD_PRE = 0x0
760 11:19:49.082891 WR_PRE = 0x1
761 11:19:49.082975 WR_PST = 0x0
762 11:19:49.086448 DBI_WR = 0x0
763 11:19:49.086531 DBI_RD = 0x0
764 11:19:49.090824 OTF = 0x1
765 11:19:49.094400 ===================================
766 11:19:49.097301 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 11:19:49.101961 nWR fixed to 40
768 11:19:49.105645 [ModeRegInit_LP4] CH0 RK0
769 11:19:49.105729 [ModeRegInit_LP4] CH0 RK1
770 11:19:49.109469 [ModeRegInit_LP4] CH1 RK0
771 11:19:49.112718 [ModeRegInit_LP4] CH1 RK1
772 11:19:49.112803 match AC timing 13
773 11:19:49.119555 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 11:19:49.122635 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 11:19:49.126035 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 11:19:49.130037 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 11:19:49.136317 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 11:19:49.136428 [EMI DOE] emi_dcm 0
779 11:19:49.139833 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 11:19:49.142672 ==
781 11:19:49.146646 Dram Type= 6, Freq= 0, CH_0, rank 0
782 11:19:49.149600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 11:19:49.149678 ==
784 11:19:49.156286 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 11:19:49.159688 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 11:19:49.169608 [CA 0] Center 37 (6~68) winsize 63
787 11:19:49.172960 [CA 1] Center 36 (6~67) winsize 62
788 11:19:49.176087 [CA 2] Center 34 (4~65) winsize 62
789 11:19:49.179760 [CA 3] Center 34 (4~65) winsize 62
790 11:19:49.183038 [CA 4] Center 33 (3~64) winsize 62
791 11:19:49.186514 [CA 5] Center 33 (3~64) winsize 62
792 11:19:49.186597
793 11:19:49.190132 [CmdBusTrainingLP45] Vref(ca) range 1: 32
794 11:19:49.190215
795 11:19:49.193229 [CATrainingPosCal] consider 1 rank data
796 11:19:49.196447 u2DelayCellTimex100 = 270/100 ps
797 11:19:49.200327 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
798 11:19:49.203006 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
799 11:19:49.206340 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
800 11:19:49.213293 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
801 11:19:49.216646 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
802 11:19:49.219712 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 11:19:49.219796
804 11:19:49.223368 CA PerBit enable=1, Macro0, CA PI delay=33
805 11:19:49.223452
806 11:19:49.226534 [CBTSetCACLKResult] CA Dly = 33
807 11:19:49.226618 CS Dly: 6 (0~37)
808 11:19:49.226685 ==
809 11:19:49.229731 Dram Type= 6, Freq= 0, CH_0, rank 1
810 11:19:49.236107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 11:19:49.236191 ==
812 11:19:49.239642 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 11:19:49.246099 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 11:19:49.255550 [CA 0] Center 37 (6~68) winsize 63
815 11:19:49.258873 [CA 1] Center 37 (7~68) winsize 62
816 11:19:49.262503 [CA 2] Center 34 (4~65) winsize 62
817 11:19:49.265664 [CA 3] Center 34 (4~65) winsize 62
818 11:19:49.269234 [CA 4] Center 33 (3~64) winsize 62
819 11:19:49.272220 [CA 5] Center 33 (2~64) winsize 63
820 11:19:49.272304
821 11:19:49.275735 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 11:19:49.275818
823 11:19:49.279210 [CATrainingPosCal] consider 2 rank data
824 11:19:49.282579 u2DelayCellTimex100 = 270/100 ps
825 11:19:49.285527 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
826 11:19:49.292213 CA1 delay=37 (7~67),Diff = 4 PI (28 cell)
827 11:19:49.295863 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
828 11:19:49.299786 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
829 11:19:49.303198 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
830 11:19:49.306674 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 11:19:49.306756
832 11:19:49.310229 CA PerBit enable=1, Macro0, CA PI delay=33
833 11:19:49.310311
834 11:19:49.310377 [CBTSetCACLKResult] CA Dly = 33
835 11:19:49.314825 CS Dly: 6 (0~38)
836 11:19:49.314908
837 11:19:49.318147 ----->DramcWriteLeveling(PI) begin...
838 11:19:49.318231 ==
839 11:19:49.322114 Dram Type= 6, Freq= 0, CH_0, rank 0
840 11:19:49.325246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 11:19:49.325330 ==
842 11:19:49.328748 Write leveling (Byte 0): 34 => 34
843 11:19:49.332124 Write leveling (Byte 1): 30 => 30
844 11:19:49.335424 DramcWriteLeveling(PI) end<-----
845 11:19:49.335507
846 11:19:49.335572 ==
847 11:19:49.338557 Dram Type= 6, Freq= 0, CH_0, rank 0
848 11:19:49.342608 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 11:19:49.342692 ==
850 11:19:49.345947 [Gating] SW mode calibration
851 11:19:49.352379 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 11:19:49.359422 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 11:19:49.362117 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 11:19:49.365653 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
855 11:19:49.368959 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
856 11:19:49.375348 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
857 11:19:49.379052 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 11:19:49.382047 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 11:19:49.388809 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 11:19:49.391751 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 11:19:49.395339 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 11:19:49.402027 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 11:19:49.405227 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 11:19:49.408644 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 11:19:49.415372 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 11:19:49.418322 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 11:19:49.421529 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 11:19:49.428437 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 11:19:49.432316 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 11:19:49.435021 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 11:19:49.441736 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
872 11:19:49.444949 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 11:19:49.448109 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 11:19:49.454980 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 11:19:49.458292 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 11:19:49.462065 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 11:19:49.468065 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 11:19:49.471472 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 11:19:49.475176 0 9 8 | B1->B0 | 2323 2a2a | 0 1 | (0 0) (1 1)
880 11:19:49.481984 0 9 12 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
881 11:19:49.484858 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 11:19:49.488149 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 11:19:49.494560 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 11:19:49.498653 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 11:19:49.501779 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 11:19:49.507940 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
887 11:19:49.511786 0 10 8 | B1->B0 | 3232 2525 | 1 0 | (1 1) (0 0)
888 11:19:49.515098 0 10 12 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
889 11:19:49.521138 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 11:19:49.524360 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 11:19:49.527949 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 11:19:49.534620 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 11:19:49.538037 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 11:19:49.540937 0 11 4 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
895 11:19:49.547979 0 11 8 | B1->B0 | 2525 3838 | 1 1 | (0 0) (0 0)
896 11:19:49.550950 0 11 12 | B1->B0 | 3c3c 4646 | 0 0 | (0 0) (0 0)
897 11:19:49.554646 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 11:19:49.557724 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 11:19:49.564021 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 11:19:49.567392 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 11:19:49.570920 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 11:19:49.577283 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
903 11:19:49.580674 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
904 11:19:49.583958 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 11:19:49.591083 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 11:19:49.594180 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 11:19:49.597273 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 11:19:49.604123 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 11:19:49.607393 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 11:19:49.610750 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 11:19:49.617244 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 11:19:49.620419 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 11:19:49.623754 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 11:19:49.630083 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 11:19:49.633454 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 11:19:49.636778 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 11:19:49.643804 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 11:19:49.646952 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
919 11:19:49.650142 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
920 11:19:49.657211 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
921 11:19:49.660103 Total UI for P1: 0, mck2ui 16
922 11:19:49.663348 best dqsien dly found for B0: ( 0, 14, 8)
923 11:19:49.666918 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
924 11:19:49.670353 Total UI for P1: 0, mck2ui 16
925 11:19:49.673447 best dqsien dly found for B1: ( 0, 14, 10)
926 11:19:49.676478 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
927 11:19:49.679898 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
928 11:19:49.679982
929 11:19:49.683749 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
930 11:19:49.687765 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
931 11:19:49.690832 [Gating] SW calibration Done
932 11:19:49.690916 ==
933 11:19:49.693740 Dram Type= 6, Freq= 0, CH_0, rank 0
934 11:19:49.697521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
935 11:19:49.697609 ==
936 11:19:49.700356 RX Vref Scan: 0
937 11:19:49.700465
938 11:19:49.703843 RX Vref 0 -> 0, step: 1
939 11:19:49.703926
940 11:19:49.703992 RX Delay -130 -> 252, step: 16
941 11:19:49.710314 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
942 11:19:49.713707 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
943 11:19:49.716777 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
944 11:19:49.720354 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
945 11:19:49.727226 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
946 11:19:49.730714 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
947 11:19:49.733335 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
948 11:19:49.737191 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
949 11:19:49.740155 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
950 11:19:49.746864 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
951 11:19:49.749830 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
952 11:19:49.753417 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
953 11:19:49.756418 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
954 11:19:49.759773 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
955 11:19:49.766958 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
956 11:19:49.769724 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
957 11:19:49.769808 ==
958 11:19:49.773398 Dram Type= 6, Freq= 0, CH_0, rank 0
959 11:19:49.776788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
960 11:19:49.776872 ==
961 11:19:49.779668 DQS Delay:
962 11:19:49.779751 DQS0 = 0, DQS1 = 0
963 11:19:49.779818 DQM Delay:
964 11:19:49.783178 DQM0 = 87, DQM1 = 76
965 11:19:49.783261 DQ Delay:
966 11:19:49.786418 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
967 11:19:49.789782 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =93
968 11:19:49.793449 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
969 11:19:49.796582 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
970 11:19:49.796665
971 11:19:49.796731
972 11:19:49.796791 ==
973 11:19:49.799550 Dram Type= 6, Freq= 0, CH_0, rank 0
974 11:19:49.806088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
975 11:19:49.806173 ==
976 11:19:49.806239
977 11:19:49.806298
978 11:19:49.806356 TX Vref Scan disable
979 11:19:49.809832 == TX Byte 0 ==
980 11:19:49.813185 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
981 11:19:49.820030 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
982 11:19:49.820117 == TX Byte 1 ==
983 11:19:49.823632 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
984 11:19:49.827271 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
985 11:19:49.827415 ==
986 11:19:49.830983 Dram Type= 6, Freq= 0, CH_0, rank 0
987 11:19:49.837469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
988 11:19:49.837553 ==
989 11:19:49.849240 TX Vref=22, minBit 3, minWin=27, winSum=440
990 11:19:49.853139 TX Vref=24, minBit 3, minWin=27, winSum=444
991 11:19:49.856686 TX Vref=26, minBit 3, minWin=27, winSum=444
992 11:19:49.860560 TX Vref=28, minBit 8, minWin=27, winSum=449
993 11:19:49.863616 TX Vref=30, minBit 0, minWin=27, winSum=448
994 11:19:49.867768 TX Vref=32, minBit 0, minWin=27, winSum=443
995 11:19:49.875406 [TxChooseVref] Worse bit 8, Min win 27, Win sum 449, Final Vref 28
996 11:19:49.875491
997 11:19:49.875557 Final TX Range 1 Vref 28
998 11:19:49.875619
999 11:19:49.875678 ==
1000 11:19:49.878733 Dram Type= 6, Freq= 0, CH_0, rank 0
1001 11:19:49.882632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1002 11:19:49.882716 ==
1003 11:19:49.882781
1004 11:19:49.886377
1005 11:19:49.886460 TX Vref Scan disable
1006 11:19:49.890080 == TX Byte 0 ==
1007 11:19:49.893124 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1008 11:19:49.897372 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1009 11:19:49.899913 == TX Byte 1 ==
1010 11:19:49.903087 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1011 11:19:49.906800 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1012 11:19:49.906884
1013 11:19:49.910213 [DATLAT]
1014 11:19:49.910296 Freq=800, CH0 RK0
1015 11:19:49.910362
1016 11:19:49.913711 DATLAT Default: 0xa
1017 11:19:49.913794 0, 0xFFFF, sum = 0
1018 11:19:49.917045 1, 0xFFFF, sum = 0
1019 11:19:49.917130 2, 0xFFFF, sum = 0
1020 11:19:49.919861 3, 0xFFFF, sum = 0
1021 11:19:49.919945 4, 0xFFFF, sum = 0
1022 11:19:49.923471 5, 0xFFFF, sum = 0
1023 11:19:49.923571 6, 0xFFFF, sum = 0
1024 11:19:49.926620 7, 0xFFFF, sum = 0
1025 11:19:49.926708 8, 0xFFFF, sum = 0
1026 11:19:49.930282 9, 0x0, sum = 1
1027 11:19:49.930364 10, 0x0, sum = 2
1028 11:19:49.933069 11, 0x0, sum = 3
1029 11:19:49.933152 12, 0x0, sum = 4
1030 11:19:49.937082 best_step = 10
1031 11:19:49.937164
1032 11:19:49.937228 ==
1033 11:19:49.940121 Dram Type= 6, Freq= 0, CH_0, rank 0
1034 11:19:49.943599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1035 11:19:49.943685 ==
1036 11:19:49.943751 RX Vref Scan: 1
1037 11:19:49.947141
1038 11:19:49.947223 Set Vref Range= 32 -> 127
1039 11:19:49.947288
1040 11:19:49.950557 RX Vref 32 -> 127, step: 1
1041 11:19:49.950639
1042 11:19:49.954022 RX Delay -111 -> 252, step: 8
1043 11:19:49.954105
1044 11:19:49.957885 Set Vref, RX VrefLevel [Byte0]: 32
1045 11:19:49.961577 [Byte1]: 32
1046 11:19:49.961659
1047 11:19:49.964863 Set Vref, RX VrefLevel [Byte0]: 33
1048 11:19:49.968321 [Byte1]: 33
1049 11:19:49.968403
1050 11:19:49.971440 Set Vref, RX VrefLevel [Byte0]: 34
1051 11:19:49.974582 [Byte1]: 34
1052 11:19:49.974665
1053 11:19:49.977913 Set Vref, RX VrefLevel [Byte0]: 35
1054 11:19:49.981101 [Byte1]: 35
1055 11:19:49.985751
1056 11:19:49.985832 Set Vref, RX VrefLevel [Byte0]: 36
1057 11:19:49.988946 [Byte1]: 36
1058 11:19:49.992711
1059 11:19:49.992795 Set Vref, RX VrefLevel [Byte0]: 37
1060 11:19:49.996336 [Byte1]: 37
1061 11:19:50.000499
1062 11:19:50.000599 Set Vref, RX VrefLevel [Byte0]: 38
1063 11:19:50.003606 [Byte1]: 38
1064 11:19:50.008212
1065 11:19:50.008287 Set Vref, RX VrefLevel [Byte0]: 39
1066 11:19:50.011243 [Byte1]: 39
1067 11:19:50.015583
1068 11:19:50.015661 Set Vref, RX VrefLevel [Byte0]: 40
1069 11:19:50.019094 [Byte1]: 40
1070 11:19:50.023743
1071 11:19:50.023815 Set Vref, RX VrefLevel [Byte0]: 41
1072 11:19:50.026869 [Byte1]: 41
1073 11:19:50.030992
1074 11:19:50.031070 Set Vref, RX VrefLevel [Byte0]: 42
1075 11:19:50.034125 [Byte1]: 42
1076 11:19:50.038682
1077 11:19:50.038758 Set Vref, RX VrefLevel [Byte0]: 43
1078 11:19:50.041916 [Byte1]: 43
1079 11:19:50.046505
1080 11:19:50.046584 Set Vref, RX VrefLevel [Byte0]: 44
1081 11:19:50.049708 [Byte1]: 44
1082 11:19:50.053946
1083 11:19:50.054023 Set Vref, RX VrefLevel [Byte0]: 45
1084 11:19:50.057142 [Byte1]: 45
1085 11:19:50.061666
1086 11:19:50.061739 Set Vref, RX VrefLevel [Byte0]: 46
1087 11:19:50.064811 [Byte1]: 46
1088 11:19:50.069408
1089 11:19:50.069487 Set Vref, RX VrefLevel [Byte0]: 47
1090 11:19:50.072798 [Byte1]: 47
1091 11:19:50.077273
1092 11:19:50.077362 Set Vref, RX VrefLevel [Byte0]: 48
1093 11:19:50.079935 [Byte1]: 48
1094 11:19:50.084347
1095 11:19:50.084418 Set Vref, RX VrefLevel [Byte0]: 49
1096 11:19:50.087619 [Byte1]: 49
1097 11:19:50.092193
1098 11:19:50.092276 Set Vref, RX VrefLevel [Byte0]: 50
1099 11:19:50.095337 [Byte1]: 50
1100 11:19:50.099754
1101 11:19:50.099836 Set Vref, RX VrefLevel [Byte0]: 51
1102 11:19:50.103199 [Byte1]: 51
1103 11:19:50.107366
1104 11:19:50.107447 Set Vref, RX VrefLevel [Byte0]: 52
1105 11:19:50.111096 [Byte1]: 52
1106 11:19:50.115084
1107 11:19:50.115165 Set Vref, RX VrefLevel [Byte0]: 53
1108 11:19:50.118424 [Byte1]: 53
1109 11:19:50.123108
1110 11:19:50.123190 Set Vref, RX VrefLevel [Byte0]: 54
1111 11:19:50.126073 [Byte1]: 54
1112 11:19:50.130253
1113 11:19:50.130339 Set Vref, RX VrefLevel [Byte0]: 55
1114 11:19:50.133474 [Byte1]: 55
1115 11:19:50.138003
1116 11:19:50.138084 Set Vref, RX VrefLevel [Byte0]: 56
1117 11:19:50.141566 [Byte1]: 56
1118 11:19:50.145754
1119 11:19:50.145835 Set Vref, RX VrefLevel [Byte0]: 57
1120 11:19:50.149487 [Byte1]: 57
1121 11:19:50.153754
1122 11:19:50.153835 Set Vref, RX VrefLevel [Byte0]: 58
1123 11:19:50.157306 [Byte1]: 58
1124 11:19:50.161207
1125 11:19:50.161288 Set Vref, RX VrefLevel [Byte0]: 59
1126 11:19:50.164627 [Byte1]: 59
1127 11:19:50.169106
1128 11:19:50.169186 Set Vref, RX VrefLevel [Byte0]: 60
1129 11:19:50.172160 [Byte1]: 60
1130 11:19:50.176674
1131 11:19:50.176773 Set Vref, RX VrefLevel [Byte0]: 61
1132 11:19:50.180191 [Byte1]: 61
1133 11:19:50.184643
1134 11:19:50.184735 Set Vref, RX VrefLevel [Byte0]: 62
1135 11:19:50.187305 [Byte1]: 62
1136 11:19:50.191738
1137 11:19:50.194981 Set Vref, RX VrefLevel [Byte0]: 63
1138 11:19:50.195064 [Byte1]: 63
1139 11:19:50.199596
1140 11:19:50.199679 Set Vref, RX VrefLevel [Byte0]: 64
1141 11:19:50.203148 [Byte1]: 64
1142 11:19:50.206969
1143 11:19:50.207051 Set Vref, RX VrefLevel [Byte0]: 65
1144 11:19:50.210720 [Byte1]: 65
1145 11:19:50.215010
1146 11:19:50.215092 Set Vref, RX VrefLevel [Byte0]: 66
1147 11:19:50.218525 [Byte1]: 66
1148 11:19:50.222564
1149 11:19:50.222647 Set Vref, RX VrefLevel [Byte0]: 67
1150 11:19:50.225751 [Byte1]: 67
1151 11:19:50.229917
1152 11:19:50.230031 Set Vref, RX VrefLevel [Byte0]: 68
1153 11:19:50.233446 [Byte1]: 68
1154 11:19:50.237665
1155 11:19:50.237816 Set Vref, RX VrefLevel [Byte0]: 69
1156 11:19:50.240929 [Byte1]: 69
1157 11:19:50.245507
1158 11:19:50.245585 Set Vref, RX VrefLevel [Byte0]: 70
1159 11:19:50.249198 [Byte1]: 70
1160 11:19:50.252357
1161 11:19:50.256304 Set Vref, RX VrefLevel [Byte0]: 71
1162 11:19:50.256388 [Byte1]: 71
1163 11:19:50.260866
1164 11:19:50.260950 Set Vref, RX VrefLevel [Byte0]: 72
1165 11:19:50.264212 [Byte1]: 72
1166 11:19:50.268878
1167 11:19:50.268954 Set Vref, RX VrefLevel [Byte0]: 73
1168 11:19:50.271781 [Byte1]: 73
1169 11:19:50.276126
1170 11:19:50.276225 Set Vref, RX VrefLevel [Byte0]: 74
1171 11:19:50.279750 [Byte1]: 74
1172 11:19:50.283508
1173 11:19:50.283615 Set Vref, RX VrefLevel [Byte0]: 75
1174 11:19:50.287261 [Byte1]: 75
1175 11:19:50.291179
1176 11:19:50.291253 Set Vref, RX VrefLevel [Byte0]: 76
1177 11:19:50.295297 [Byte1]: 76
1178 11:19:50.299420
1179 11:19:50.299523 Set Vref, RX VrefLevel [Byte0]: 77
1180 11:19:50.302383 [Byte1]: 77
1181 11:19:50.306145
1182 11:19:50.310003 Set Vref, RX VrefLevel [Byte0]: 78
1183 11:19:50.310088 [Byte1]: 78
1184 11:19:50.314103
1185 11:19:50.314187 Set Vref, RX VrefLevel [Byte0]: 79
1186 11:19:50.318001 [Byte1]: 79
1187 11:19:50.321992
1188 11:19:50.322075 Set Vref, RX VrefLevel [Byte0]: 80
1189 11:19:50.324777 [Byte1]: 80
1190 11:19:50.329860
1191 11:19:50.329952 Set Vref, RX VrefLevel [Byte0]: 81
1192 11:19:50.333215 [Byte1]: 81
1193 11:19:50.336820
1194 11:19:50.336903 Set Vref, RX VrefLevel [Byte0]: 82
1195 11:19:50.340325 [Byte1]: 82
1196 11:19:50.345031
1197 11:19:50.345114 Set Vref, RX VrefLevel [Byte0]: 83
1198 11:19:50.348261 [Byte1]: 83
1199 11:19:50.351937
1200 11:19:50.352021 Final RX Vref Byte 0 = 69 to rank0
1201 11:19:50.355487 Final RX Vref Byte 1 = 56 to rank0
1202 11:19:50.359535 Final RX Vref Byte 0 = 69 to rank1
1203 11:19:50.363017 Final RX Vref Byte 1 = 56 to rank1==
1204 11:19:50.366344 Dram Type= 6, Freq= 0, CH_0, rank 0
1205 11:19:50.369672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1206 11:19:50.369758 ==
1207 11:19:50.373132 DQS Delay:
1208 11:19:50.373214 DQS0 = 0, DQS1 = 0
1209 11:19:50.376365 DQM Delay:
1210 11:19:50.376464 DQM0 = 88, DQM1 = 75
1211 11:19:50.376553 DQ Delay:
1212 11:19:50.379856 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1213 11:19:50.383852 DQ4 =88, DQ5 =76, DQ6 =100, DQ7 =96
1214 11:19:50.387753 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1215 11:19:50.390906 DQ12 =80, DQ13 =76, DQ14 =88, DQ15 =84
1216 11:19:50.390989
1217 11:19:50.391054
1218 11:19:50.398591 [DQSOSCAuto] RK0, (LSB)MR18= 0x4728, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 392 ps
1219 11:19:50.402113 CH0 RK0: MR19=606, MR18=4728
1220 11:19:50.409248 CH0_RK0: MR19=0x606, MR18=0x4728, DQSOSC=392, MR23=63, INC=96, DEC=64
1221 11:19:50.409332
1222 11:19:50.413002 ----->DramcWriteLeveling(PI) begin...
1223 11:19:50.413085 ==
1224 11:19:50.416685 Dram Type= 6, Freq= 0, CH_0, rank 1
1225 11:19:50.460593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1226 11:19:50.460679 ==
1227 11:19:50.460745 Write leveling (Byte 0): 31 => 31
1228 11:19:50.460824 Write leveling (Byte 1): 31 => 31
1229 11:19:50.460886 DramcWriteLeveling(PI) end<-----
1230 11:19:50.460943
1231 11:19:50.460998 ==
1232 11:19:50.461239 Dram Type= 6, Freq= 0, CH_0, rank 1
1233 11:19:50.461627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1234 11:19:50.461732 ==
1235 11:19:50.461798 [Gating] SW mode calibration
1236 11:19:50.462224 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1237 11:19:50.462300 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1238 11:19:50.462390 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1239 11:19:50.462453 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1240 11:19:50.504725 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1241 11:19:50.505353 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 11:19:50.505438 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 11:19:50.506027 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 11:19:50.506306 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 11:19:50.506849 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 11:19:50.507281 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 11:19:50.507363 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 11:19:50.508112 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 11:19:50.508380 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 11:19:50.548788 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 11:19:50.549401 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 11:19:50.549484 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 11:19:50.549744 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 11:19:50.550033 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 11:19:50.550728 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1256 11:19:50.550996 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1257 11:19:50.551064 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 11:19:50.551564 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 11:19:50.551961 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 11:19:50.561610 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1261 11:19:50.562189 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1262 11:19:50.562273 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1263 11:19:50.565911 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1264 11:19:50.569607 0 9 8 | B1->B0 | 2323 3131 | 1 1 | (1 1) (1 1)
1265 11:19:50.573139 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1266 11:19:50.580438 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1267 11:19:50.584060 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1268 11:19:50.588046 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1269 11:19:50.592068 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1270 11:19:50.595629 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1271 11:19:50.599553 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
1272 11:19:50.606593 0 10 8 | B1->B0 | 3131 2525 | 0 0 | (0 0) (1 0)
1273 11:19:50.609932 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1274 11:19:50.613938 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1275 11:19:50.617755 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1276 11:19:50.621412 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1277 11:19:50.629009 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1278 11:19:50.632438 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1279 11:19:50.635720 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1280 11:19:50.639080 0 11 8 | B1->B0 | 2f2f 3f3f | 0 0 | (0 0) (0 0)
1281 11:19:50.645509 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1282 11:19:50.648738 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1283 11:19:50.652463 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1284 11:19:50.659120 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1285 11:19:50.662210 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1286 11:19:50.665712 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1287 11:19:50.672558 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1288 11:19:50.675653 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1289 11:19:50.679595 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1290 11:19:50.685762 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1291 11:19:50.689115 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1292 11:19:50.692181 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1293 11:19:50.695920 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1294 11:19:50.702081 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1295 11:19:50.705302 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1296 11:19:50.709140 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1297 11:19:50.715545 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1298 11:19:50.718688 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1299 11:19:50.721939 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1300 11:19:50.728456 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1301 11:19:50.732024 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1302 11:19:50.735099 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1303 11:19:50.742125 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1304 11:19:50.745410 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1305 11:19:50.748417 Total UI for P1: 0, mck2ui 16
1306 11:19:50.751928 best dqsien dly found for B0: ( 0, 14, 4)
1307 11:19:50.754976 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1308 11:19:50.758413 Total UI for P1: 0, mck2ui 16
1309 11:19:50.761778 best dqsien dly found for B1: ( 0, 14, 8)
1310 11:19:50.764945 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1311 11:19:50.768513 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1312 11:19:50.768601
1313 11:19:50.775104 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1314 11:19:50.778242 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1315 11:19:50.778324 [Gating] SW calibration Done
1316 11:19:50.781934 ==
1317 11:19:50.785027 Dram Type= 6, Freq= 0, CH_0, rank 1
1318 11:19:50.788407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1319 11:19:50.788491 ==
1320 11:19:50.788591 RX Vref Scan: 0
1321 11:19:50.788653
1322 11:19:50.792058 RX Vref 0 -> 0, step: 1
1323 11:19:50.792140
1324 11:19:50.794871 RX Delay -130 -> 252, step: 16
1325 11:19:50.798178 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1326 11:19:50.801533 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1327 11:19:50.808058 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1328 11:19:50.812144 iDelay=222, Bit 3, Center 77 (-34 ~ 189) 224
1329 11:19:50.814878 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1330 11:19:50.818300 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1331 11:19:50.821535 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1332 11:19:50.828014 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1333 11:19:50.831627 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1334 11:19:50.834588 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1335 11:19:50.838274 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1336 11:19:50.841564 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1337 11:19:50.848162 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1338 11:19:50.851358 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1339 11:19:50.854930 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1340 11:19:50.858067 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1341 11:19:50.858148 ==
1342 11:19:50.861388 Dram Type= 6, Freq= 0, CH_0, rank 1
1343 11:19:50.868135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1344 11:19:50.868217 ==
1345 11:19:50.868280 DQS Delay:
1346 11:19:50.871408 DQS0 = 0, DQS1 = 0
1347 11:19:50.871489 DQM Delay:
1348 11:19:50.871553 DQM0 = 85, DQM1 = 79
1349 11:19:50.874326 DQ Delay:
1350 11:19:50.877533 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =77
1351 11:19:50.881160 DQ4 =85, DQ5 =77, DQ6 =93, DQ7 =93
1352 11:19:50.884624 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1353 11:19:50.887611 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1354 11:19:50.887691
1355 11:19:50.887755
1356 11:19:50.887813 ==
1357 11:19:50.891046 Dram Type= 6, Freq= 0, CH_0, rank 1
1358 11:19:50.894659 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1359 11:19:50.894743 ==
1360 11:19:50.894807
1361 11:19:50.894866
1362 11:19:50.897536 TX Vref Scan disable
1363 11:19:50.897641 == TX Byte 0 ==
1364 11:19:50.904287 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1365 11:19:50.907663 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1366 11:19:50.907743 == TX Byte 1 ==
1367 11:19:50.914380 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1368 11:19:50.917651 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1369 11:19:50.917731 ==
1370 11:19:50.920705 Dram Type= 6, Freq= 0, CH_0, rank 1
1371 11:19:50.924352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1372 11:19:50.924458 ==
1373 11:19:50.938259 TX Vref=22, minBit 13, minWin=27, winSum=448
1374 11:19:50.941310 TX Vref=24, minBit 11, minWin=27, winSum=449
1375 11:19:50.944925 TX Vref=26, minBit 9, minWin=27, winSum=445
1376 11:19:50.948137 TX Vref=28, minBit 9, minWin=27, winSum=449
1377 11:19:50.952045 TX Vref=30, minBit 9, minWin=27, winSum=445
1378 11:19:50.958105 TX Vref=32, minBit 8, minWin=27, winSum=444
1379 11:19:50.961399 [TxChooseVref] Worse bit 11, Min win 27, Win sum 449, Final Vref 24
1380 11:19:50.961480
1381 11:19:50.964851 Final TX Range 1 Vref 24
1382 11:19:50.964930
1383 11:19:50.964992 ==
1384 11:19:50.968311 Dram Type= 6, Freq= 0, CH_0, rank 1
1385 11:19:50.971208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1386 11:19:50.974586 ==
1387 11:19:50.974666
1388 11:19:50.974729
1389 11:19:50.974786 TX Vref Scan disable
1390 11:19:50.978361 == TX Byte 0 ==
1391 11:19:50.981956 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1392 11:19:50.988360 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1393 11:19:50.988440 == TX Byte 1 ==
1394 11:19:50.991767 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1395 11:19:50.998572 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1396 11:19:50.998657
1397 11:19:50.998720 [DATLAT]
1398 11:19:50.998778 Freq=800, CH0 RK1
1399 11:19:50.998835
1400 11:19:51.001650 DATLAT Default: 0xa
1401 11:19:51.001729 0, 0xFFFF, sum = 0
1402 11:19:51.005036 1, 0xFFFF, sum = 0
1403 11:19:51.005116 2, 0xFFFF, sum = 0
1404 11:19:51.008521 3, 0xFFFF, sum = 0
1405 11:19:51.008616 4, 0xFFFF, sum = 0
1406 11:19:51.011529 5, 0xFFFF, sum = 0
1407 11:19:51.015291 6, 0xFFFF, sum = 0
1408 11:19:51.015371 7, 0xFFFF, sum = 0
1409 11:19:51.018049 8, 0xFFFF, sum = 0
1410 11:19:51.018130 9, 0x0, sum = 1
1411 11:19:51.018194 10, 0x0, sum = 2
1412 11:19:51.021552 11, 0x0, sum = 3
1413 11:19:51.021632 12, 0x0, sum = 4
1414 11:19:51.024919 best_step = 10
1415 11:19:51.024999
1416 11:19:51.025060 ==
1417 11:19:51.028406 Dram Type= 6, Freq= 0, CH_0, rank 1
1418 11:19:51.031585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1419 11:19:51.031665 ==
1420 11:19:51.034722 RX Vref Scan: 0
1421 11:19:51.034802
1422 11:19:51.034864 RX Vref 0 -> 0, step: 1
1423 11:19:51.038332
1424 11:19:51.038411 RX Delay -95 -> 252, step: 8
1425 11:19:51.045295 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1426 11:19:51.048045 iDelay=217, Bit 1, Center 88 (-23 ~ 200) 224
1427 11:19:51.051734 iDelay=217, Bit 2, Center 80 (-31 ~ 192) 224
1428 11:19:51.055198 iDelay=217, Bit 3, Center 80 (-39 ~ 200) 240
1429 11:19:51.058447 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1430 11:19:51.065059 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1431 11:19:51.068360 iDelay=217, Bit 6, Center 96 (-15 ~ 208) 224
1432 11:19:51.071612 iDelay=217, Bit 7, Center 100 (-15 ~ 216) 232
1433 11:19:51.074597 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
1434 11:19:51.077928 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1435 11:19:51.084621 iDelay=217, Bit 10, Center 80 (-39 ~ 200) 240
1436 11:19:51.088124 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1437 11:19:51.091820 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1438 11:19:51.095003 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1439 11:19:51.101335 iDelay=217, Bit 14, Center 88 (-23 ~ 200) 224
1440 11:19:51.104480 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1441 11:19:51.104597 ==
1442 11:19:51.108051 Dram Type= 6, Freq= 0, CH_0, rank 1
1443 11:19:51.111427 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1444 11:19:51.111507 ==
1445 11:19:51.111570 DQS Delay:
1446 11:19:51.114649 DQS0 = 0, DQS1 = 0
1447 11:19:51.114728 DQM Delay:
1448 11:19:51.118046 DQM0 = 86, DQM1 = 77
1449 11:19:51.118125 DQ Delay:
1450 11:19:51.121358 DQ0 =84, DQ1 =88, DQ2 =80, DQ3 =80
1451 11:19:51.124635 DQ4 =84, DQ5 =76, DQ6 =96, DQ7 =100
1452 11:19:51.128787 DQ8 =68, DQ9 =60, DQ10 =80, DQ11 =68
1453 11:19:51.131617 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1454 11:19:51.131696
1455 11:19:51.131758
1456 11:19:51.141258 [DQSOSCAuto] RK1, (LSB)MR18= 0x4208, (MSB)MR19= 0x606, tDQSOscB0 = 408 ps tDQSOscB1 = 393 ps
1457 11:19:51.141360 CH0 RK1: MR19=606, MR18=4208
1458 11:19:51.147789 CH0_RK1: MR19=0x606, MR18=0x4208, DQSOSC=393, MR23=63, INC=95, DEC=63
1459 11:19:51.151247 [RxdqsGatingPostProcess] freq 800
1460 11:19:51.157636 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1461 11:19:51.161273 Pre-setting of DQS Precalculation
1462 11:19:51.164416 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1463 11:19:51.164496 ==
1464 11:19:51.168216 Dram Type= 6, Freq= 0, CH_1, rank 0
1465 11:19:51.174191 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1466 11:19:51.174273 ==
1467 11:19:51.177437 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1468 11:19:51.183928 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1469 11:19:51.193724 [CA 0] Center 36 (6~67) winsize 62
1470 11:19:51.196549 [CA 1] Center 36 (6~67) winsize 62
1471 11:19:51.199975 [CA 2] Center 34 (4~65) winsize 62
1472 11:19:51.203536 [CA 3] Center 34 (3~65) winsize 63
1473 11:19:51.207478 [CA 4] Center 34 (4~65) winsize 62
1474 11:19:51.210011 [CA 5] Center 34 (3~65) winsize 63
1475 11:19:51.210091
1476 11:19:51.213427 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1477 11:19:51.213507
1478 11:19:51.216673 [CATrainingPosCal] consider 1 rank data
1479 11:19:51.219939 u2DelayCellTimex100 = 270/100 ps
1480 11:19:51.223231 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1481 11:19:51.230120 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1482 11:19:51.233556 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1483 11:19:51.236471 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1484 11:19:51.240057 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1485 11:19:51.243401 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1486 11:19:51.243508
1487 11:19:51.246754 CA PerBit enable=1, Macro0, CA PI delay=34
1488 11:19:51.246835
1489 11:19:51.249876 [CBTSetCACLKResult] CA Dly = 34
1490 11:19:51.249959 CS Dly: 5 (0~36)
1491 11:19:51.253330 ==
1492 11:19:51.256309 Dram Type= 6, Freq= 0, CH_1, rank 1
1493 11:19:51.259760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1494 11:19:51.259842 ==
1495 11:19:51.262997 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1496 11:19:51.269731 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1497 11:19:51.280453 [CA 0] Center 36 (6~67) winsize 62
1498 11:19:51.283510 [CA 1] Center 36 (6~67) winsize 62
1499 11:19:51.286537 [CA 2] Center 34 (4~65) winsize 62
1500 11:19:51.289451 [CA 3] Center 34 (3~65) winsize 63
1501 11:19:51.292957 [CA 4] Center 34 (4~65) winsize 62
1502 11:19:51.296406 [CA 5] Center 34 (3~65) winsize 63
1503 11:19:51.296487
1504 11:19:51.299558 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1505 11:19:51.299639
1506 11:19:51.302747 [CATrainingPosCal] consider 2 rank data
1507 11:19:51.306059 u2DelayCellTimex100 = 270/100 ps
1508 11:19:51.309371 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1509 11:19:51.316016 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1510 11:19:51.319378 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1511 11:19:51.322861 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1512 11:19:51.325948 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1513 11:19:51.329680 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1514 11:19:51.329766
1515 11:19:51.332725 CA PerBit enable=1, Macro0, CA PI delay=34
1516 11:19:51.332807
1517 11:19:51.336028 [CBTSetCACLKResult] CA Dly = 34
1518 11:19:51.336110 CS Dly: 6 (0~38)
1519 11:19:51.339124
1520 11:19:51.343014 ----->DramcWriteLeveling(PI) begin...
1521 11:19:51.343097 ==
1522 11:19:51.346055 Dram Type= 6, Freq= 0, CH_1, rank 0
1523 11:19:51.349260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1524 11:19:51.349342 ==
1525 11:19:51.352655 Write leveling (Byte 0): 28 => 28
1526 11:19:51.355584 Write leveling (Byte 1): 26 => 26
1527 11:19:51.358839 DramcWriteLeveling(PI) end<-----
1528 11:19:51.358920
1529 11:19:51.358985 ==
1530 11:19:51.362152 Dram Type= 6, Freq= 0, CH_1, rank 0
1531 11:19:51.365309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1532 11:19:51.365407 ==
1533 11:19:51.368730 [Gating] SW mode calibration
1534 11:19:51.375374 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1535 11:19:51.382055 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1536 11:19:51.384981 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1537 11:19:51.388385 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1538 11:19:51.395153 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 11:19:51.399086 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 11:19:51.401928 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 11:19:51.408415 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 11:19:51.411652 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 11:19:51.415402 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 11:19:51.422158 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 11:19:51.424908 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 11:19:51.428406 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 11:19:51.434985 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 11:19:51.438441 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1549 11:19:51.441567 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1550 11:19:51.448354 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 11:19:51.451625 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 11:19:51.454898 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1553 11:19:51.461462 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1554 11:19:51.465023 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1555 11:19:51.468173 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 11:19:51.475057 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 11:19:51.478360 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 11:19:51.481749 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 11:19:51.484895 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1560 11:19:51.491772 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1561 11:19:51.494761 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (1 1) (1 1)
1562 11:19:51.498746 0 9 8 | B1->B0 | 3030 2d2d | 1 1 | (0 0) (1 1)
1563 11:19:51.504719 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1564 11:19:51.508106 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1565 11:19:51.511499 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1566 11:19:51.518183 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1567 11:19:51.521366 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1568 11:19:51.525429 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1569 11:19:51.531781 0 10 4 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
1570 11:19:51.535115 0 10 8 | B1->B0 | 2b2b 2424 | 0 0 | (0 0) (1 1)
1571 11:19:51.538116 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1572 11:19:51.544941 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1573 11:19:51.548104 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1574 11:19:51.551193 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1575 11:19:51.558735 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1576 11:19:51.561355 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1577 11:19:51.564760 0 11 4 | B1->B0 | 2424 2d2d | 0 0 | (0 0) (0 0)
1578 11:19:51.571903 0 11 8 | B1->B0 | 3939 3c3c | 1 0 | (0 0) (0 0)
1579 11:19:51.574468 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1580 11:19:51.577858 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1581 11:19:51.584863 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1582 11:19:51.587930 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1583 11:19:51.591364 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1584 11:19:51.598119 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1585 11:19:51.600847 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1586 11:19:51.604895 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1587 11:19:51.611332 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1588 11:19:51.614766 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1589 11:19:51.618014 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1590 11:19:51.624404 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1591 11:19:51.627629 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1592 11:19:51.630864 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1593 11:19:51.634051 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1594 11:19:51.641404 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1595 11:19:51.644215 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1596 11:19:51.647581 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1597 11:19:51.654267 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1598 11:19:51.657454 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1599 11:19:51.660924 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1600 11:19:51.667647 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1601 11:19:51.670883 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1602 11:19:51.674154 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1603 11:19:51.677816 Total UI for P1: 0, mck2ui 16
1604 11:19:51.681192 best dqsien dly found for B0: ( 0, 14, 2)
1605 11:19:51.684413 Total UI for P1: 0, mck2ui 16
1606 11:19:51.687130 best dqsien dly found for B1: ( 0, 14, 6)
1607 11:19:51.690666 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1608 11:19:51.693970 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1609 11:19:51.694077
1610 11:19:51.701084 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1611 11:19:51.704043 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1612 11:19:51.704124 [Gating] SW calibration Done
1613 11:19:51.707341 ==
1614 11:19:51.710706 Dram Type= 6, Freq= 0, CH_1, rank 0
1615 11:19:51.714349 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1616 11:19:51.714431 ==
1617 11:19:51.714496 RX Vref Scan: 0
1618 11:19:51.714556
1619 11:19:51.717279 RX Vref 0 -> 0, step: 1
1620 11:19:51.717386
1621 11:19:51.720484 RX Delay -130 -> 252, step: 16
1622 11:19:51.724081 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1623 11:19:51.726944 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1624 11:19:51.734281 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1625 11:19:51.737020 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1626 11:19:51.740750 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1627 11:19:51.743799 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1628 11:19:51.746930 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1629 11:19:51.753737 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1630 11:19:51.757140 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1631 11:19:51.760739 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1632 11:19:51.763469 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1633 11:19:51.767554 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1634 11:19:51.773733 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1635 11:19:51.777095 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1636 11:19:51.780486 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1637 11:19:51.783509 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1638 11:19:51.783590 ==
1639 11:19:51.786703 Dram Type= 6, Freq= 0, CH_1, rank 0
1640 11:19:51.793252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1641 11:19:51.793333 ==
1642 11:19:51.793397 DQS Delay:
1643 11:19:51.796951 DQS0 = 0, DQS1 = 0
1644 11:19:51.797032 DQM Delay:
1645 11:19:51.797096 DQM0 = 88, DQM1 = 78
1646 11:19:51.800050 DQ Delay:
1647 11:19:51.803319 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1648 11:19:51.806848 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1649 11:19:51.810069 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1650 11:19:51.813374 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1651 11:19:51.813456
1652 11:19:51.813522
1653 11:19:51.813581 ==
1654 11:19:51.817052 Dram Type= 6, Freq= 0, CH_1, rank 0
1655 11:19:51.820261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1656 11:19:51.820343 ==
1657 11:19:51.820407
1658 11:19:51.820468
1659 11:19:51.823423 TX Vref Scan disable
1660 11:19:51.826826 == TX Byte 0 ==
1661 11:19:51.830146 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1662 11:19:51.833647 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1663 11:19:51.836487 == TX Byte 1 ==
1664 11:19:51.839894 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1665 11:19:51.843066 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1666 11:19:51.843148 ==
1667 11:19:51.846517 Dram Type= 6, Freq= 0, CH_1, rank 0
1668 11:19:51.849798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1669 11:19:51.849881 ==
1670 11:19:51.864684 TX Vref=22, minBit 2, minWin=27, winSum=445
1671 11:19:51.868242 TX Vref=24, minBit 9, minWin=27, winSum=451
1672 11:19:51.871016 TX Vref=26, minBit 11, minWin=27, winSum=451
1673 11:19:51.875088 TX Vref=28, minBit 15, minWin=27, winSum=453
1674 11:19:51.877869 TX Vref=30, minBit 15, minWin=27, winSum=453
1675 11:19:51.884465 TX Vref=32, minBit 10, minWin=27, winSum=448
1676 11:19:51.887961 [TxChooseVref] Worse bit 15, Min win 27, Win sum 453, Final Vref 28
1677 11:19:51.888046
1678 11:19:51.891208 Final TX Range 1 Vref 28
1679 11:19:51.891290
1680 11:19:51.891355 ==
1681 11:19:51.894616 Dram Type= 6, Freq= 0, CH_1, rank 0
1682 11:19:51.900787 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1683 11:19:51.900871 ==
1684 11:19:51.900936
1685 11:19:51.900995
1686 11:19:51.901053 TX Vref Scan disable
1687 11:19:51.905339 == TX Byte 0 ==
1688 11:19:51.908543 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1689 11:19:51.914861 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1690 11:19:51.914951 == TX Byte 1 ==
1691 11:19:51.917938 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1692 11:19:51.921277 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1693 11:19:51.924847
1694 11:19:51.924930 [DATLAT]
1695 11:19:51.924994 Freq=800, CH1 RK0
1696 11:19:51.925054
1697 11:19:51.928546 DATLAT Default: 0xa
1698 11:19:51.928643 0, 0xFFFF, sum = 0
1699 11:19:51.931515 1, 0xFFFF, sum = 0
1700 11:19:51.931599 2, 0xFFFF, sum = 0
1701 11:19:51.934737 3, 0xFFFF, sum = 0
1702 11:19:51.934822 4, 0xFFFF, sum = 0
1703 11:19:51.938886 5, 0xFFFF, sum = 0
1704 11:19:51.938970 6, 0xFFFF, sum = 0
1705 11:19:51.941913 7, 0xFFFF, sum = 0
1706 11:19:51.944714 8, 0xFFFF, sum = 0
1707 11:19:51.944799 9, 0x0, sum = 1
1708 11:19:51.944866 10, 0x0, sum = 2
1709 11:19:51.948171 11, 0x0, sum = 3
1710 11:19:51.948255 12, 0x0, sum = 4
1711 11:19:51.951388 best_step = 10
1712 11:19:51.951472
1713 11:19:51.951537 ==
1714 11:19:51.954958 Dram Type= 6, Freq= 0, CH_1, rank 0
1715 11:19:51.958020 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1716 11:19:51.958103 ==
1717 11:19:51.961914 RX Vref Scan: 1
1718 11:19:51.961997
1719 11:19:51.962063 Set Vref Range= 32 -> 127
1720 11:19:51.962123
1721 11:19:51.965259 RX Vref 32 -> 127, step: 1
1722 11:19:51.965372
1723 11:19:51.968174 RX Delay -95 -> 252, step: 8
1724 11:19:51.968257
1725 11:19:51.972057 Set Vref, RX VrefLevel [Byte0]: 32
1726 11:19:51.974942 [Byte1]: 32
1727 11:19:51.975024
1728 11:19:51.978175 Set Vref, RX VrefLevel [Byte0]: 33
1729 11:19:51.981378 [Byte1]: 33
1730 11:19:51.985312
1731 11:19:51.988452 Set Vref, RX VrefLevel [Byte0]: 34
1732 11:19:51.991697 [Byte1]: 34
1733 11:19:51.991780
1734 11:19:51.995023 Set Vref, RX VrefLevel [Byte0]: 35
1735 11:19:51.997933 [Byte1]: 35
1736 11:19:51.998016
1737 11:19:52.001432 Set Vref, RX VrefLevel [Byte0]: 36
1738 11:19:52.004626 [Byte1]: 36
1739 11:19:52.004709
1740 11:19:52.008234 Set Vref, RX VrefLevel [Byte0]: 37
1741 11:19:52.011716 [Byte1]: 37
1742 11:19:52.015765
1743 11:19:52.015847 Set Vref, RX VrefLevel [Byte0]: 38
1744 11:19:52.018862 [Byte1]: 38
1745 11:19:52.023171
1746 11:19:52.023253 Set Vref, RX VrefLevel [Byte0]: 39
1747 11:19:52.026389 [Byte1]: 39
1748 11:19:52.030665
1749 11:19:52.030748 Set Vref, RX VrefLevel [Byte0]: 40
1750 11:19:52.034355 [Byte1]: 40
1751 11:19:52.038103
1752 11:19:52.038186 Set Vref, RX VrefLevel [Byte0]: 41
1753 11:19:52.041803 [Byte1]: 41
1754 11:19:52.045850
1755 11:19:52.045932 Set Vref, RX VrefLevel [Byte0]: 42
1756 11:19:52.049300 [Byte1]: 42
1757 11:19:52.053509
1758 11:19:52.053602 Set Vref, RX VrefLevel [Byte0]: 43
1759 11:19:52.057143 [Byte1]: 43
1760 11:19:52.061116
1761 11:19:52.061201 Set Vref, RX VrefLevel [Byte0]: 44
1762 11:19:52.064270 [Byte1]: 44
1763 11:19:52.068468
1764 11:19:52.068556 Set Vref, RX VrefLevel [Byte0]: 45
1765 11:19:52.071977 [Byte1]: 45
1766 11:19:52.076444
1767 11:19:52.076561 Set Vref, RX VrefLevel [Byte0]: 46
1768 11:19:52.079610 [Byte1]: 46
1769 11:19:52.084074
1770 11:19:52.084157 Set Vref, RX VrefLevel [Byte0]: 47
1771 11:19:52.087049 [Byte1]: 47
1772 11:19:52.091479
1773 11:19:52.091563 Set Vref, RX VrefLevel [Byte0]: 48
1774 11:19:52.095020 [Byte1]: 48
1775 11:19:52.098897
1776 11:19:52.098981 Set Vref, RX VrefLevel [Byte0]: 49
1777 11:19:52.102835 [Byte1]: 49
1778 11:19:52.106653
1779 11:19:52.106737 Set Vref, RX VrefLevel [Byte0]: 50
1780 11:19:52.109893 [Byte1]: 50
1781 11:19:52.114388
1782 11:19:52.114471 Set Vref, RX VrefLevel [Byte0]: 51
1783 11:19:52.117891 [Byte1]: 51
1784 11:19:52.121725
1785 11:19:52.121809 Set Vref, RX VrefLevel [Byte0]: 52
1786 11:19:52.125139 [Byte1]: 52
1787 11:19:52.129260
1788 11:19:52.129344 Set Vref, RX VrefLevel [Byte0]: 53
1789 11:19:52.132807 [Byte1]: 53
1790 11:19:52.137317
1791 11:19:52.137400 Set Vref, RX VrefLevel [Byte0]: 54
1792 11:19:52.140296 [Byte1]: 54
1793 11:19:52.144959
1794 11:19:52.145044 Set Vref, RX VrefLevel [Byte0]: 55
1795 11:19:52.147979 [Byte1]: 55
1796 11:19:52.152150
1797 11:19:52.152232 Set Vref, RX VrefLevel [Byte0]: 56
1798 11:19:52.155797 [Byte1]: 56
1799 11:19:52.159803
1800 11:19:52.159883 Set Vref, RX VrefLevel [Byte0]: 57
1801 11:19:52.163159 [Byte1]: 57
1802 11:19:52.167497
1803 11:19:52.167580 Set Vref, RX VrefLevel [Byte0]: 58
1804 11:19:52.170643 [Byte1]: 58
1805 11:19:52.174838
1806 11:19:52.174915 Set Vref, RX VrefLevel [Byte0]: 59
1807 11:19:52.178196 [Byte1]: 59
1808 11:19:52.182666
1809 11:19:52.182742 Set Vref, RX VrefLevel [Byte0]: 60
1810 11:19:52.185670 [Byte1]: 60
1811 11:19:52.190303
1812 11:19:52.190386 Set Vref, RX VrefLevel [Byte0]: 61
1813 11:19:52.193184 [Byte1]: 61
1814 11:19:52.197661
1815 11:19:52.197736 Set Vref, RX VrefLevel [Byte0]: 62
1816 11:19:52.201353 [Byte1]: 62
1817 11:19:52.205969
1818 11:19:52.206059 Set Vref, RX VrefLevel [Byte0]: 63
1819 11:19:52.209244 [Byte1]: 63
1820 11:19:52.213130
1821 11:19:52.213213 Set Vref, RX VrefLevel [Byte0]: 64
1822 11:19:52.216384 [Byte1]: 64
1823 11:19:52.220485
1824 11:19:52.220612 Set Vref, RX VrefLevel [Byte0]: 65
1825 11:19:52.223868 [Byte1]: 65
1826 11:19:52.228501
1827 11:19:52.228622 Set Vref, RX VrefLevel [Byte0]: 66
1828 11:19:52.231363 [Byte1]: 66
1829 11:19:52.235573
1830 11:19:52.235657 Set Vref, RX VrefLevel [Byte0]: 67
1831 11:19:52.238941 [Byte1]: 67
1832 11:19:52.243523
1833 11:19:52.243605 Set Vref, RX VrefLevel [Byte0]: 68
1834 11:19:52.246524 [Byte1]: 68
1835 11:19:52.250945
1836 11:19:52.251027 Set Vref, RX VrefLevel [Byte0]: 69
1837 11:19:52.254924 [Byte1]: 69
1838 11:19:52.258568
1839 11:19:52.258650 Set Vref, RX VrefLevel [Byte0]: 70
1840 11:19:52.261911 [Byte1]: 70
1841 11:19:52.266349
1842 11:19:52.266432 Set Vref, RX VrefLevel [Byte0]: 71
1843 11:19:52.269499 [Byte1]: 71
1844 11:19:52.273912
1845 11:19:52.273994 Set Vref, RX VrefLevel [Byte0]: 72
1846 11:19:52.277212 [Byte1]: 72
1847 11:19:52.281932
1848 11:19:52.282014 Set Vref, RX VrefLevel [Byte0]: 73
1849 11:19:52.285052 [Byte1]: 73
1850 11:19:52.288839
1851 11:19:52.288921 Set Vref, RX VrefLevel [Byte0]: 74
1852 11:19:52.292713 [Byte1]: 74
1853 11:19:52.296389
1854 11:19:52.296471 Set Vref, RX VrefLevel [Byte0]: 75
1855 11:19:52.299918 [Byte1]: 75
1856 11:19:52.304455
1857 11:19:52.304571 Set Vref, RX VrefLevel [Byte0]: 76
1858 11:19:52.308015 [Byte1]: 76
1859 11:19:52.312120
1860 11:19:52.312203 Set Vref, RX VrefLevel [Byte0]: 77
1861 11:19:52.315291 [Byte1]: 77
1862 11:19:52.319589
1863 11:19:52.319671 Set Vref, RX VrefLevel [Byte0]: 78
1864 11:19:52.322897 [Byte1]: 78
1865 11:19:52.326942
1866 11:19:52.327024 Set Vref, RX VrefLevel [Byte0]: 79
1867 11:19:52.330335 [Byte1]: 79
1868 11:19:52.334448
1869 11:19:52.334531 Set Vref, RX VrefLevel [Byte0]: 80
1870 11:19:52.338098 [Byte1]: 80
1871 11:19:52.342113
1872 11:19:52.342196 Final RX Vref Byte 0 = 55 to rank0
1873 11:19:52.345401 Final RX Vref Byte 1 = 69 to rank0
1874 11:19:52.348459 Final RX Vref Byte 0 = 55 to rank1
1875 11:19:52.351994 Final RX Vref Byte 1 = 69 to rank1==
1876 11:19:52.355143 Dram Type= 6, Freq= 0, CH_1, rank 0
1877 11:19:52.361834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1878 11:19:52.361918 ==
1879 11:19:52.361984 DQS Delay:
1880 11:19:52.365058 DQS0 = 0, DQS1 = 0
1881 11:19:52.365141 DQM Delay:
1882 11:19:52.365206 DQM0 = 86, DQM1 = 78
1883 11:19:52.368750 DQ Delay:
1884 11:19:52.371997 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1885 11:19:52.375173 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =80
1886 11:19:52.378345 DQ8 =68, DQ9 =68, DQ10 =84, DQ11 =68
1887 11:19:52.381550 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1888 11:19:52.381631
1889 11:19:52.381702
1890 11:19:52.388458 [DQSOSCAuto] RK0, (LSB)MR18= 0x3420, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
1891 11:19:52.391424 CH1 RK0: MR19=606, MR18=3420
1892 11:19:52.398497 CH1_RK0: MR19=0x606, MR18=0x3420, DQSOSC=396, MR23=63, INC=94, DEC=62
1893 11:19:52.398578
1894 11:19:52.401254 ----->DramcWriteLeveling(PI) begin...
1895 11:19:52.401337 ==
1896 11:19:52.405005 Dram Type= 6, Freq= 0, CH_1, rank 1
1897 11:19:52.408348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1898 11:19:52.408430 ==
1899 11:19:52.411277 Write leveling (Byte 0): 27 => 27
1900 11:19:52.414604 Write leveling (Byte 1): 31 => 31
1901 11:19:52.418076 DramcWriteLeveling(PI) end<-----
1902 11:19:52.418157
1903 11:19:52.418221 ==
1904 11:19:52.421329 Dram Type= 6, Freq= 0, CH_1, rank 1
1905 11:19:52.424974 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1906 11:19:52.428081 ==
1907 11:19:52.428163 [Gating] SW mode calibration
1908 11:19:52.434706 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1909 11:19:52.441483 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1910 11:19:52.444487 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1911 11:19:52.451080 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1912 11:19:52.454421 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1913 11:19:52.457859 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 11:19:52.464464 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 11:19:52.467911 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1916 11:19:52.470859 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1917 11:19:52.477536 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1918 11:19:52.481134 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1919 11:19:52.484502 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1920 11:19:52.490835 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1921 11:19:52.493976 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1922 11:19:52.497816 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1923 11:19:52.504282 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1924 11:19:52.507322 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1925 11:19:52.511112 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1926 11:19:52.517629 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1927 11:19:52.520693 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1928 11:19:52.523818 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1929 11:19:52.530584 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1930 11:19:52.533797 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1931 11:19:52.537522 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1932 11:19:52.543554 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1933 11:19:52.546837 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1934 11:19:52.550498 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1935 11:19:52.556927 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1936 11:19:52.559943 0 9 8 | B1->B0 | 3130 2625 | 1 1 | (1 1) (1 1)
1937 11:19:52.563720 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1938 11:19:52.569964 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1939 11:19:52.573927 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1940 11:19:52.576862 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1941 11:19:52.583356 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1942 11:19:52.586792 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1943 11:19:52.590020 0 10 4 | B1->B0 | 3131 3434 | 1 1 | (1 0) (1 1)
1944 11:19:52.596683 0 10 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (1 1)
1945 11:19:52.599656 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1946 11:19:52.603288 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1947 11:19:52.606326 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1948 11:19:52.613197 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1949 11:19:52.616344 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1950 11:19:52.619819 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1951 11:19:52.626788 0 11 4 | B1->B0 | 2828 2424 | 0 0 | (0 0) (0 0)
1952 11:19:52.629644 0 11 8 | B1->B0 | 3f3f 3838 | 0 0 | (0 0) (0 0)
1953 11:19:52.633246 0 11 12 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
1954 11:19:52.640026 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1955 11:19:52.643387 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1956 11:19:52.646487 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1957 11:19:52.652536 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1958 11:19:52.656197 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1959 11:19:52.659386 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1960 11:19:52.666401 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1961 11:19:52.669320 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1962 11:19:52.672772 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1963 11:19:52.679536 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1964 11:19:52.682969 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1965 11:19:52.685949 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1966 11:19:52.692793 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1967 11:19:52.696134 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1968 11:19:52.699468 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1969 11:19:52.705834 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1970 11:19:52.709459 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1971 11:19:52.712498 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1972 11:19:52.719549 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1973 11:19:52.722714 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1974 11:19:52.726486 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1975 11:19:52.729563 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1976 11:19:52.733002 Total UI for P1: 0, mck2ui 16
1977 11:19:52.736288 best dqsien dly found for B1: ( 0, 14, 2)
1978 11:19:52.743037 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1979 11:19:52.746346 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1980 11:19:52.750050 Total UI for P1: 0, mck2ui 16
1981 11:19:52.752731 best dqsien dly found for B0: ( 0, 14, 6)
1982 11:19:52.756358 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1983 11:19:52.759748 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1984 11:19:52.759829
1985 11:19:52.762475 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1986 11:19:52.766277 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1987 11:19:52.769308 [Gating] SW calibration Done
1988 11:19:52.769389 ==
1989 11:19:52.772642 Dram Type= 6, Freq= 0, CH_1, rank 1
1990 11:19:52.779151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1991 11:19:52.779260 ==
1992 11:19:52.779350 RX Vref Scan: 0
1993 11:19:52.779413
1994 11:19:52.782851 RX Vref 0 -> 0, step: 1
1995 11:19:52.782952
1996 11:19:52.785750 RX Delay -130 -> 252, step: 16
1997 11:19:52.789178 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1998 11:19:52.792691 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1999 11:19:52.795977 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
2000 11:19:52.799388 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
2001 11:19:52.806247 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
2002 11:19:52.809367 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
2003 11:19:52.812450 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
2004 11:19:52.816042 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
2005 11:19:52.822368 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
2006 11:19:52.825668 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
2007 11:19:52.828978 iDelay=222, Bit 10, Center 77 (-34 ~ 189) 224
2008 11:19:52.832220 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
2009 11:19:52.835864 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
2010 11:19:52.842457 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
2011 11:19:52.845611 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
2012 11:19:52.848945 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
2013 11:19:52.849027 ==
2014 11:19:52.852271 Dram Type= 6, Freq= 0, CH_1, rank 1
2015 11:19:52.855615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2016 11:19:52.855696 ==
2017 11:19:52.858886 DQS Delay:
2018 11:19:52.858967 DQS0 = 0, DQS1 = 0
2019 11:19:52.862364 DQM Delay:
2020 11:19:52.862446 DQM0 = 87, DQM1 = 78
2021 11:19:52.862510 DQ Delay:
2022 11:19:52.865412 DQ0 =85, DQ1 =77, DQ2 =77, DQ3 =85
2023 11:19:52.868893 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
2024 11:19:52.872153 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
2025 11:19:52.875151 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
2026 11:19:52.875232
2027 11:19:52.878926
2028 11:19:52.879007 ==
2029 11:19:52.882862 Dram Type= 6, Freq= 0, CH_1, rank 1
2030 11:19:52.885645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2031 11:19:52.885726 ==
2032 11:19:52.885790
2033 11:19:52.885849
2034 11:19:52.889303 TX Vref Scan disable
2035 11:19:52.889384 == TX Byte 0 ==
2036 11:19:52.895357 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2037 11:19:52.898486 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2038 11:19:52.898567 == TX Byte 1 ==
2039 11:19:52.905318 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2040 11:19:52.908793 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2041 11:19:52.908874 ==
2042 11:19:52.911994 Dram Type= 6, Freq= 0, CH_1, rank 1
2043 11:19:52.915120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2044 11:19:52.915201 ==
2045 11:19:52.929098 TX Vref=22, minBit 9, minWin=26, winSum=443
2046 11:19:52.932432 TX Vref=24, minBit 8, minWin=27, winSum=449
2047 11:19:52.935898 TX Vref=26, minBit 8, minWin=27, winSum=451
2048 11:19:52.939141 TX Vref=28, minBit 8, minWin=27, winSum=449
2049 11:19:52.942817 TX Vref=30, minBit 8, minWin=27, winSum=452
2050 11:19:52.949009 TX Vref=32, minBit 8, minWin=27, winSum=450
2051 11:19:52.952394 [TxChooseVref] Worse bit 8, Min win 27, Win sum 452, Final Vref 30
2052 11:19:52.952476
2053 11:19:52.955825 Final TX Range 1 Vref 30
2054 11:19:52.955906
2055 11:19:52.955970 ==
2056 11:19:52.959228 Dram Type= 6, Freq= 0, CH_1, rank 1
2057 11:19:52.962047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2058 11:19:52.962129 ==
2059 11:19:52.965417
2060 11:19:52.965497
2061 11:19:52.965561 TX Vref Scan disable
2062 11:19:52.969231 == TX Byte 0 ==
2063 11:19:52.972854 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2064 11:19:52.978872 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2065 11:19:52.978960 == TX Byte 1 ==
2066 11:19:52.982339 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
2067 11:19:52.985524 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
2068 11:19:52.988870
2069 11:19:52.988950 [DATLAT]
2070 11:19:52.989014 Freq=800, CH1 RK1
2071 11:19:52.989076
2072 11:19:52.992434 DATLAT Default: 0xa
2073 11:19:52.992573 0, 0xFFFF, sum = 0
2074 11:19:52.995715 1, 0xFFFF, sum = 0
2075 11:19:52.995798 2, 0xFFFF, sum = 0
2076 11:19:52.998796 3, 0xFFFF, sum = 0
2077 11:19:52.998879 4, 0xFFFF, sum = 0
2078 11:19:53.002450 5, 0xFFFF, sum = 0
2079 11:19:53.005868 6, 0xFFFF, sum = 0
2080 11:19:53.005950 7, 0xFFFF, sum = 0
2081 11:19:53.009050 8, 0xFFFF, sum = 0
2082 11:19:53.009133 9, 0x0, sum = 1
2083 11:19:53.009199 10, 0x0, sum = 2
2084 11:19:53.012412 11, 0x0, sum = 3
2085 11:19:53.012526 12, 0x0, sum = 4
2086 11:19:53.015512 best_step = 10
2087 11:19:53.015593
2088 11:19:53.015689 ==
2089 11:19:53.018753 Dram Type= 6, Freq= 0, CH_1, rank 1
2090 11:19:53.022041 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2091 11:19:53.022123 ==
2092 11:19:53.025951 RX Vref Scan: 0
2093 11:19:53.026032
2094 11:19:53.026095 RX Vref 0 -> 0, step: 1
2095 11:19:53.026154
2096 11:19:53.029087 RX Delay -95 -> 252, step: 8
2097 11:19:53.035657 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2098 11:19:53.039010 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2099 11:19:53.042037 iDelay=217, Bit 2, Center 80 (-31 ~ 192) 224
2100 11:19:53.046044 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2101 11:19:53.052093 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2102 11:19:53.055496 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2103 11:19:53.058741 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2104 11:19:53.062013 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2105 11:19:53.065232 iDelay=217, Bit 8, Center 64 (-47 ~ 176) 224
2106 11:19:53.071916 iDelay=217, Bit 9, Center 72 (-39 ~ 184) 224
2107 11:19:53.075716 iDelay=217, Bit 10, Center 80 (-31 ~ 192) 224
2108 11:19:53.078303 iDelay=217, Bit 11, Center 72 (-39 ~ 184) 224
2109 11:19:53.081500 iDelay=217, Bit 12, Center 88 (-23 ~ 200) 224
2110 11:19:53.084954 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2111 11:19:53.092001 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2112 11:19:53.095045 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
2113 11:19:53.095128 ==
2114 11:19:53.098271 Dram Type= 6, Freq= 0, CH_1, rank 1
2115 11:19:53.101718 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2116 11:19:53.101802 ==
2117 11:19:53.105470 DQS Delay:
2118 11:19:53.105553 DQS0 = 0, DQS1 = 0
2119 11:19:53.105618 DQM Delay:
2120 11:19:53.108258 DQM0 = 87, DQM1 = 78
2121 11:19:53.108341 DQ Delay:
2122 11:19:53.112044 DQ0 =92, DQ1 =80, DQ2 =80, DQ3 =84
2123 11:19:53.115017 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2124 11:19:53.118312 DQ8 =64, DQ9 =72, DQ10 =80, DQ11 =72
2125 11:19:53.121695 DQ12 =88, DQ13 =84, DQ14 =84, DQ15 =84
2126 11:19:53.121777
2127 11:19:53.121842
2128 11:19:53.132385 [DQSOSCAuto] RK1, (LSB)MR18= 0x150d, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 404 ps
2129 11:19:53.134629 CH1 RK1: MR19=606, MR18=150D
2130 11:19:53.138052 CH1_RK1: MR19=0x606, MR18=0x150D, DQSOSC=404, MR23=63, INC=90, DEC=60
2131 11:19:53.141574 [RxdqsGatingPostProcess] freq 800
2132 11:19:53.148453 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2133 11:19:53.151787 Pre-setting of DQS Precalculation
2134 11:19:53.155114 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2135 11:19:53.164805 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2136 11:19:53.171273 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2137 11:19:53.171356
2138 11:19:53.171421
2139 11:19:53.174760 [Calibration Summary] 1600 Mbps
2140 11:19:53.174843 CH 0, Rank 0
2141 11:19:53.178075 SW Impedance : PASS
2142 11:19:53.178158 DUTY Scan : NO K
2143 11:19:53.181200 ZQ Calibration : PASS
2144 11:19:53.184713 Jitter Meter : NO K
2145 11:19:53.184795 CBT Training : PASS
2146 11:19:53.187862 Write leveling : PASS
2147 11:19:53.191540 RX DQS gating : PASS
2148 11:19:53.191622 RX DQ/DQS(RDDQC) : PASS
2149 11:19:53.194398 TX DQ/DQS : PASS
2150 11:19:53.197651 RX DATLAT : PASS
2151 11:19:53.197748 RX DQ/DQS(Engine): PASS
2152 11:19:53.200970 TX OE : NO K
2153 11:19:53.201052 All Pass.
2154 11:19:53.201117
2155 11:19:53.204498 CH 0, Rank 1
2156 11:19:53.204617 SW Impedance : PASS
2157 11:19:53.207519 DUTY Scan : NO K
2158 11:19:53.211269 ZQ Calibration : PASS
2159 11:19:53.211350 Jitter Meter : NO K
2160 11:19:53.214939 CBT Training : PASS
2161 11:19:53.215022 Write leveling : PASS
2162 11:19:53.217356 RX DQS gating : PASS
2163 11:19:53.220991 RX DQ/DQS(RDDQC) : PASS
2164 11:19:53.221072 TX DQ/DQS : PASS
2165 11:19:53.224559 RX DATLAT : PASS
2166 11:19:53.227823 RX DQ/DQS(Engine): PASS
2167 11:19:53.227904 TX OE : NO K
2168 11:19:53.231815 All Pass.
2169 11:19:53.231896
2170 11:19:53.231961 CH 1, Rank 0
2171 11:19:53.234280 SW Impedance : PASS
2172 11:19:53.234362 DUTY Scan : NO K
2173 11:19:53.237432 ZQ Calibration : PASS
2174 11:19:53.240738 Jitter Meter : NO K
2175 11:19:53.240820 CBT Training : PASS
2176 11:19:53.244355 Write leveling : PASS
2177 11:19:53.247868 RX DQS gating : PASS
2178 11:19:53.247950 RX DQ/DQS(RDDQC) : PASS
2179 11:19:53.250471 TX DQ/DQS : PASS
2180 11:19:53.253944 RX DATLAT : PASS
2181 11:19:53.254026 RX DQ/DQS(Engine): PASS
2182 11:19:53.257786 TX OE : NO K
2183 11:19:53.257869 All Pass.
2184 11:19:53.257934
2185 11:19:53.260545 CH 1, Rank 1
2186 11:19:53.260641 SW Impedance : PASS
2187 11:19:53.264099 DUTY Scan : NO K
2188 11:19:53.267318 ZQ Calibration : PASS
2189 11:19:53.267429 Jitter Meter : NO K
2190 11:19:53.270597 CBT Training : PASS
2191 11:19:53.274271 Write leveling : PASS
2192 11:19:53.274383 RX DQS gating : PASS
2193 11:19:53.277038 RX DQ/DQS(RDDQC) : PASS
2194 11:19:53.277136 TX DQ/DQS : PASS
2195 11:19:53.280377 RX DATLAT : PASS
2196 11:19:53.283954 RX DQ/DQS(Engine): PASS
2197 11:19:53.284054 TX OE : NO K
2198 11:19:53.287263 All Pass.
2199 11:19:53.287365
2200 11:19:53.287458 DramC Write-DBI off
2201 11:19:53.290437 PER_BANK_REFRESH: Hybrid Mode
2202 11:19:53.293988 TX_TRACKING: ON
2203 11:19:53.297056 [GetDramInforAfterCalByMRR] Vendor 6.
2204 11:19:53.300480 [GetDramInforAfterCalByMRR] Revision 606.
2205 11:19:53.303798 [GetDramInforAfterCalByMRR] Revision 2 0.
2206 11:19:53.303906 MR0 0x3b3b
2207 11:19:53.303998 MR8 0x5151
2208 11:19:53.310341 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2209 11:19:53.310416
2210 11:19:53.310488 MR0 0x3b3b
2211 11:19:53.310551 MR8 0x5151
2212 11:19:53.313391 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2213 11:19:53.313469
2214 11:19:53.323744 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2215 11:19:53.326942 [FAST_K] Save calibration result to emmc
2216 11:19:53.330200 [FAST_K] Save calibration result to emmc
2217 11:19:53.334194 dram_init: config_dvfs: 1
2218 11:19:53.336901 dramc_set_vcore_voltage set vcore to 662500
2219 11:19:53.340369 Read voltage for 1200, 2
2220 11:19:53.340472 Vio18 = 0
2221 11:19:53.343407 Vcore = 662500
2222 11:19:53.343505 Vdram = 0
2223 11:19:53.343567 Vddq = 0
2224 11:19:53.343625 Vmddr = 0
2225 11:19:53.350034 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2226 11:19:53.356670 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2227 11:19:53.356763 MEM_TYPE=3, freq_sel=15
2228 11:19:53.360217 sv_algorithm_assistance_LP4_1600
2229 11:19:53.363365 ============ PULL DRAM RESETB DOWN ============
2230 11:19:53.370501 ========== PULL DRAM RESETB DOWN end =========
2231 11:19:53.373376 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2232 11:19:53.376408 ===================================
2233 11:19:53.379915 LPDDR4 DRAM CONFIGURATION
2234 11:19:53.382986 ===================================
2235 11:19:53.383085 EX_ROW_EN[0] = 0x0
2236 11:19:53.386633 EX_ROW_EN[1] = 0x0
2237 11:19:53.386709 LP4Y_EN = 0x0
2238 11:19:53.389902 WORK_FSP = 0x0
2239 11:19:53.390006 WL = 0x4
2240 11:19:53.392945 RL = 0x4
2241 11:19:53.393025 BL = 0x2
2242 11:19:53.396503 RPST = 0x0
2243 11:19:53.396620 RD_PRE = 0x0
2244 11:19:53.399981 WR_PRE = 0x1
2245 11:19:53.402871 WR_PST = 0x0
2246 11:19:53.402978 DBI_WR = 0x0
2247 11:19:53.406794 DBI_RD = 0x0
2248 11:19:53.406892 OTF = 0x1
2249 11:19:53.409534 ===================================
2250 11:19:53.413145 ===================================
2251 11:19:53.413224 ANA top config
2252 11:19:53.416469 ===================================
2253 11:19:53.419671 DLL_ASYNC_EN = 0
2254 11:19:53.422741 ALL_SLAVE_EN = 0
2255 11:19:53.426175 NEW_RANK_MODE = 1
2256 11:19:53.429409 DLL_IDLE_MODE = 1
2257 11:19:53.429513 LP45_APHY_COMB_EN = 1
2258 11:19:53.432838 TX_ODT_DIS = 1
2259 11:19:53.436328 NEW_8X_MODE = 1
2260 11:19:53.439680 ===================================
2261 11:19:53.442527 ===================================
2262 11:19:53.446242 data_rate = 2400
2263 11:19:53.449544 CKR = 1
2264 11:19:53.449641 DQ_P2S_RATIO = 8
2265 11:19:53.452871 ===================================
2266 11:19:53.455836 CA_P2S_RATIO = 8
2267 11:19:53.459196 DQ_CA_OPEN = 0
2268 11:19:53.463370 DQ_SEMI_OPEN = 0
2269 11:19:53.466452 CA_SEMI_OPEN = 0
2270 11:19:53.469173 CA_FULL_RATE = 0
2271 11:19:53.472806 DQ_CKDIV4_EN = 0
2272 11:19:53.472904 CA_CKDIV4_EN = 0
2273 11:19:53.475722 CA_PREDIV_EN = 0
2274 11:19:53.479141 PH8_DLY = 17
2275 11:19:53.482241 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2276 11:19:53.485444 DQ_AAMCK_DIV = 4
2277 11:19:53.489299 CA_AAMCK_DIV = 4
2278 11:19:53.489396 CA_ADMCK_DIV = 4
2279 11:19:53.492735 DQ_TRACK_CA_EN = 0
2280 11:19:53.495645 CA_PICK = 1200
2281 11:19:53.498736 CA_MCKIO = 1200
2282 11:19:53.501981 MCKIO_SEMI = 0
2283 11:19:53.505954 PLL_FREQ = 2366
2284 11:19:53.508832 DQ_UI_PI_RATIO = 32
2285 11:19:53.508915 CA_UI_PI_RATIO = 0
2286 11:19:53.512409 ===================================
2287 11:19:53.515330 ===================================
2288 11:19:53.518593 memory_type:LPDDR4
2289 11:19:53.522676 GP_NUM : 10
2290 11:19:53.522759 SRAM_EN : 1
2291 11:19:53.525270 MD32_EN : 0
2292 11:19:53.528710 ===================================
2293 11:19:53.531842 [ANA_INIT] >>>>>>>>>>>>>>
2294 11:19:53.535375 <<<<<< [CONFIGURE PHASE]: ANA_TX
2295 11:19:53.538580 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2296 11:19:53.541729 ===================================
2297 11:19:53.541812 data_rate = 2400,PCW = 0X5b00
2298 11:19:53.544883 ===================================
2299 11:19:53.551490 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2300 11:19:53.555223 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2301 11:19:53.561949 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2302 11:19:53.564927 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2303 11:19:53.568327 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2304 11:19:53.571332 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2305 11:19:53.574725 [ANA_INIT] flow start
2306 11:19:53.578476 [ANA_INIT] PLL >>>>>>>>
2307 11:19:53.578559 [ANA_INIT] PLL <<<<<<<<
2308 11:19:53.581883 [ANA_INIT] MIDPI >>>>>>>>
2309 11:19:53.584829 [ANA_INIT] MIDPI <<<<<<<<
2310 11:19:53.584913 [ANA_INIT] DLL >>>>>>>>
2311 11:19:53.588108 [ANA_INIT] DLL <<<<<<<<
2312 11:19:53.591675 [ANA_INIT] flow end
2313 11:19:53.594600 ============ LP4 DIFF to SE enter ============
2314 11:19:53.598196 ============ LP4 DIFF to SE exit ============
2315 11:19:53.601385 [ANA_INIT] <<<<<<<<<<<<<
2316 11:19:53.604793 [Flow] Enable top DCM control >>>>>
2317 11:19:53.607806 [Flow] Enable top DCM control <<<<<
2318 11:19:53.611267 Enable DLL master slave shuffle
2319 11:19:53.614673 ==============================================================
2320 11:19:53.618178 Gating Mode config
2321 11:19:53.624326 ==============================================================
2322 11:19:53.624409 Config description:
2323 11:19:53.634683 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2324 11:19:53.640993 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2325 11:19:53.647906 SELPH_MODE 0: By rank 1: By Phase
2326 11:19:53.651391 ==============================================================
2327 11:19:53.654269 GAT_TRACK_EN = 1
2328 11:19:53.657621 RX_GATING_MODE = 2
2329 11:19:53.660819 RX_GATING_TRACK_MODE = 2
2330 11:19:53.664120 SELPH_MODE = 1
2331 11:19:53.667631 PICG_EARLY_EN = 1
2332 11:19:53.670910 VALID_LAT_VALUE = 1
2333 11:19:53.674159 ==============================================================
2334 11:19:53.677388 Enter into Gating configuration >>>>
2335 11:19:53.680661 Exit from Gating configuration <<<<
2336 11:19:53.684446 Enter into DVFS_PRE_config >>>>>
2337 11:19:53.697287 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2338 11:19:53.700609 Exit from DVFS_PRE_config <<<<<
2339 11:19:53.704228 Enter into PICG configuration >>>>
2340 11:19:53.704337 Exit from PICG configuration <<<<
2341 11:19:53.707061 [RX_INPUT] configuration >>>>>
2342 11:19:53.710577 [RX_INPUT] configuration <<<<<
2343 11:19:53.717154 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2344 11:19:53.720889 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2345 11:19:53.728039 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2346 11:19:53.733662 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2347 11:19:53.740538 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2348 11:19:53.747326 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2349 11:19:53.750112 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2350 11:19:53.753618 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2351 11:19:53.756845 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2352 11:19:53.763703 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2353 11:19:53.767087 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2354 11:19:53.769970 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2355 11:19:53.773908 ===================================
2356 11:19:53.776672 LPDDR4 DRAM CONFIGURATION
2357 11:19:53.780300 ===================================
2358 11:19:53.783658 EX_ROW_EN[0] = 0x0
2359 11:19:53.783741 EX_ROW_EN[1] = 0x0
2360 11:19:53.786754 LP4Y_EN = 0x0
2361 11:19:53.786836 WORK_FSP = 0x0
2362 11:19:53.790130 WL = 0x4
2363 11:19:53.790211 RL = 0x4
2364 11:19:53.793649 BL = 0x2
2365 11:19:53.793730 RPST = 0x0
2366 11:19:53.796519 RD_PRE = 0x0
2367 11:19:53.796601 WR_PRE = 0x1
2368 11:19:53.799922 WR_PST = 0x0
2369 11:19:53.800035 DBI_WR = 0x0
2370 11:19:53.803174 DBI_RD = 0x0
2371 11:19:53.806560 OTF = 0x1
2372 11:19:53.809835 ===================================
2373 11:19:53.813033 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2374 11:19:53.816787 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2375 11:19:53.819816 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2376 11:19:53.823695 ===================================
2377 11:19:53.826340 LPDDR4 DRAM CONFIGURATION
2378 11:19:53.829523 ===================================
2379 11:19:53.833019 EX_ROW_EN[0] = 0x10
2380 11:19:53.833101 EX_ROW_EN[1] = 0x0
2381 11:19:53.836660 LP4Y_EN = 0x0
2382 11:19:53.836766 WORK_FSP = 0x0
2383 11:19:53.839707 WL = 0x4
2384 11:19:53.839804 RL = 0x4
2385 11:19:53.843081 BL = 0x2
2386 11:19:53.843176 RPST = 0x0
2387 11:19:53.846249 RD_PRE = 0x0
2388 11:19:53.846330 WR_PRE = 0x1
2389 11:19:53.849702 WR_PST = 0x0
2390 11:19:53.849783 DBI_WR = 0x0
2391 11:19:53.853066 DBI_RD = 0x0
2392 11:19:53.853147 OTF = 0x1
2393 11:19:53.856434 ===================================
2394 11:19:53.862864 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2395 11:19:53.862945 ==
2396 11:19:53.866755 Dram Type= 6, Freq= 0, CH_0, rank 0
2397 11:19:53.873243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2398 11:19:53.873326 ==
2399 11:19:53.873389 [Duty_Offset_Calibration]
2400 11:19:53.876420 B0:1 B1:-1 CA:0
2401 11:19:53.876501
2402 11:19:53.879667 [DutyScan_Calibration_Flow] k_type=0
2403 11:19:53.888862
2404 11:19:53.888975 ==CLK 0==
2405 11:19:53.892484 Final CLK duty delay cell = 0
2406 11:19:53.894943 [0] MAX Duty = 5094%(X100), DQS PI = 16
2407 11:19:53.898323 [0] MIN Duty = 4907%(X100), DQS PI = 8
2408 11:19:53.898420 [0] AVG Duty = 5000%(X100)
2409 11:19:53.901795
2410 11:19:53.901895 CH0 CLK Duty spec in!! Max-Min= 187%
2411 11:19:53.908301 [DutyScan_Calibration_Flow] ====Done====
2412 11:19:53.908402
2413 11:19:53.911845 [DutyScan_Calibration_Flow] k_type=1
2414 11:19:53.926922
2415 11:19:53.927025 ==DQS 0 ==
2416 11:19:53.930242 Final DQS duty delay cell = -4
2417 11:19:53.933804 [-4] MAX Duty = 5062%(X100), DQS PI = 18
2418 11:19:53.937250 [-4] MIN Duty = 4875%(X100), DQS PI = 54
2419 11:19:53.940671 [-4] AVG Duty = 4968%(X100)
2420 11:19:53.940773
2421 11:19:53.940861 ==DQS 1 ==
2422 11:19:53.943559 Final DQS duty delay cell = 0
2423 11:19:53.946689 [0] MAX Duty = 5124%(X100), DQS PI = 4
2424 11:19:53.950141 [0] MIN Duty = 5000%(X100), DQS PI = 22
2425 11:19:53.953344 [0] AVG Duty = 5062%(X100)
2426 11:19:53.953425
2427 11:19:53.956914 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2428 11:19:53.956995
2429 11:19:53.959954 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2430 11:19:53.963659 [DutyScan_Calibration_Flow] ====Done====
2431 11:19:53.963740
2432 11:19:53.966757 [DutyScan_Calibration_Flow] k_type=3
2433 11:19:53.984744
2434 11:19:53.984849 ==DQM 0 ==
2435 11:19:53.987721 Final DQM duty delay cell = 0
2436 11:19:53.991210 [0] MAX Duty = 5031%(X100), DQS PI = 18
2437 11:19:53.994363 [0] MIN Duty = 4875%(X100), DQS PI = 8
2438 11:19:53.997628 [0] AVG Duty = 4953%(X100)
2439 11:19:53.997730
2440 11:19:53.997819 ==DQM 1 ==
2441 11:19:54.001320 Final DQM duty delay cell = 4
2442 11:19:54.004300 [4] MAX Duty = 5187%(X100), DQS PI = 14
2443 11:19:54.007641 [4] MIN Duty = 5000%(X100), DQS PI = 22
2444 11:19:54.011071 [4] AVG Duty = 5093%(X100)
2445 11:19:54.011153
2446 11:19:54.014612 CH0 DQM 0 Duty spec in!! Max-Min= 156%
2447 11:19:54.014718
2448 11:19:54.017538 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2449 11:19:54.021135 [DutyScan_Calibration_Flow] ====Done====
2450 11:19:54.021216
2451 11:19:54.024383 [DutyScan_Calibration_Flow] k_type=2
2452 11:19:54.040237
2453 11:19:54.040317 ==DQ 0 ==
2454 11:19:54.043642 Final DQ duty delay cell = -4
2455 11:19:54.046867 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2456 11:19:54.050574 [-4] MIN Duty = 4907%(X100), DQS PI = 46
2457 11:19:54.053611 [-4] AVG Duty = 4969%(X100)
2458 11:19:54.053695
2459 11:19:54.053759 ==DQ 1 ==
2460 11:19:54.057310 Final DQ duty delay cell = 0
2461 11:19:54.060603 [0] MAX Duty = 5093%(X100), DQS PI = 2
2462 11:19:54.063610 [0] MIN Duty = 4969%(X100), DQS PI = 40
2463 11:19:54.063693 [0] AVG Duty = 5031%(X100)
2464 11:19:54.067067
2465 11:19:54.070357 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2466 11:19:54.070440
2467 11:19:54.073720 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2468 11:19:54.076884 [DutyScan_Calibration_Flow] ====Done====
2469 11:19:54.076967 ==
2470 11:19:54.080860 Dram Type= 6, Freq= 0, CH_1, rank 0
2471 11:19:54.083356 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2472 11:19:54.083448 ==
2473 11:19:54.086964 [Duty_Offset_Calibration]
2474 11:19:54.087047 B0:-1 B1:1 CA:2
2475 11:19:54.087113
2476 11:19:54.090377 [DutyScan_Calibration_Flow] k_type=0
2477 11:19:54.100789
2478 11:19:54.100872 ==CLK 0==
2479 11:19:54.103522 Final CLK duty delay cell = 0
2480 11:19:54.106990 [0] MAX Duty = 5187%(X100), DQS PI = 36
2481 11:19:54.110216 [0] MIN Duty = 4969%(X100), DQS PI = 62
2482 11:19:54.113627 [0] AVG Duty = 5078%(X100)
2483 11:19:54.113710
2484 11:19:54.116925 CH1 CLK Duty spec in!! Max-Min= 218%
2485 11:19:54.120466 [DutyScan_Calibration_Flow] ====Done====
2486 11:19:54.120583
2487 11:19:54.123518 [DutyScan_Calibration_Flow] k_type=1
2488 11:19:54.139830
2489 11:19:54.139914 ==DQS 0 ==
2490 11:19:54.143580 Final DQS duty delay cell = 0
2491 11:19:54.146499 [0] MAX Duty = 5156%(X100), DQS PI = 48
2492 11:19:54.150106 [0] MIN Duty = 4907%(X100), DQS PI = 6
2493 11:19:54.153056 [0] AVG Duty = 5031%(X100)
2494 11:19:54.153166
2495 11:19:54.153260 ==DQS 1 ==
2496 11:19:54.156503 Final DQS duty delay cell = 0
2497 11:19:54.159718 [0] MAX Duty = 5062%(X100), DQS PI = 12
2498 11:19:54.162997 [0] MIN Duty = 4969%(X100), DQS PI = 56
2499 11:19:54.166421 [0] AVG Duty = 5015%(X100)
2500 11:19:54.166496
2501 11:19:54.169584 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2502 11:19:54.169661
2503 11:19:54.173022 CH1 DQS 1 Duty spec in!! Max-Min= 93%
2504 11:19:54.176275 [DutyScan_Calibration_Flow] ====Done====
2505 11:19:54.176386
2506 11:19:54.179412 [DutyScan_Calibration_Flow] k_type=3
2507 11:19:54.195595
2508 11:19:54.195676 ==DQM 0 ==
2509 11:19:54.199021 Final DQM duty delay cell = -4
2510 11:19:54.202366 [-4] MAX Duty = 5062%(X100), DQS PI = 36
2511 11:19:54.205717 [-4] MIN Duty = 4876%(X100), DQS PI = 6
2512 11:19:54.209248 [-4] AVG Duty = 4969%(X100)
2513 11:19:54.209329
2514 11:19:54.209394 ==DQM 1 ==
2515 11:19:54.212406 Final DQM duty delay cell = 0
2516 11:19:54.215751 [0] MAX Duty = 5156%(X100), DQS PI = 4
2517 11:19:54.219221 [0] MIN Duty = 4969%(X100), DQS PI = 28
2518 11:19:54.221987 [0] AVG Duty = 5062%(X100)
2519 11:19:54.222087
2520 11:19:54.225376 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2521 11:19:54.225466
2522 11:19:54.228755 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2523 11:19:54.232230 [DutyScan_Calibration_Flow] ====Done====
2524 11:19:54.232306
2525 11:19:54.235548 [DutyScan_Calibration_Flow] k_type=2
2526 11:19:54.252243
2527 11:19:54.252354 ==DQ 0 ==
2528 11:19:54.255402 Final DQ duty delay cell = 0
2529 11:19:54.259193 [0] MAX Duty = 5187%(X100), DQS PI = 30
2530 11:19:54.262327 [0] MIN Duty = 4907%(X100), DQS PI = 6
2531 11:19:54.262410 [0] AVG Duty = 5047%(X100)
2532 11:19:54.265333
2533 11:19:54.265437 ==DQ 1 ==
2534 11:19:54.269275 Final DQ duty delay cell = 0
2535 11:19:54.272243 [0] MAX Duty = 5124%(X100), DQS PI = 10
2536 11:19:54.275678 [0] MIN Duty = 4969%(X100), DQS PI = 58
2537 11:19:54.275761 [0] AVG Duty = 5046%(X100)
2538 11:19:54.275846
2539 11:19:54.278634 CH1 DQ 0 Duty spec in!! Max-Min= 280%
2540 11:19:54.282051
2541 11:19:54.285270 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2542 11:19:54.288638 [DutyScan_Calibration_Flow] ====Done====
2543 11:19:54.292261 nWR fixed to 30
2544 11:19:54.292370 [ModeRegInit_LP4] CH0 RK0
2545 11:19:54.295737 [ModeRegInit_LP4] CH0 RK1
2546 11:19:54.298809 [ModeRegInit_LP4] CH1 RK0
2547 11:19:54.301900 [ModeRegInit_LP4] CH1 RK1
2548 11:19:54.301988 match AC timing 7
2549 11:19:54.305100 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2550 11:19:54.311867 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2551 11:19:54.315151 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2552 11:19:54.322125 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2553 11:19:54.325625 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2554 11:19:54.325708 ==
2555 11:19:54.328889 Dram Type= 6, Freq= 0, CH_0, rank 0
2556 11:19:54.331719 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2557 11:19:54.331798 ==
2558 11:19:54.338273 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2559 11:19:54.344820 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2560 11:19:54.352447 [CA 0] Center 39 (9~70) winsize 62
2561 11:19:54.355686 [CA 1] Center 39 (9~70) winsize 62
2562 11:19:54.359000 [CA 2] Center 35 (5~66) winsize 62
2563 11:19:54.362161 [CA 3] Center 35 (5~65) winsize 61
2564 11:19:54.365340 [CA 4] Center 33 (3~64) winsize 62
2565 11:19:54.369000 [CA 5] Center 33 (3~63) winsize 61
2566 11:19:54.369084
2567 11:19:54.372157 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2568 11:19:54.372241
2569 11:19:54.375129 [CATrainingPosCal] consider 1 rank data
2570 11:19:54.378955 u2DelayCellTimex100 = 270/100 ps
2571 11:19:54.382257 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2572 11:19:54.388858 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2573 11:19:54.392071 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2574 11:19:54.395278 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2575 11:19:54.398264 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2576 11:19:54.402130 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2577 11:19:54.402214
2578 11:19:54.405078 CA PerBit enable=1, Macro0, CA PI delay=33
2579 11:19:54.405163
2580 11:19:54.408276 [CBTSetCACLKResult] CA Dly = 33
2581 11:19:54.411590 CS Dly: 8 (0~39)
2582 11:19:54.411675 ==
2583 11:19:54.414953 Dram Type= 6, Freq= 0, CH_0, rank 1
2584 11:19:54.418061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2585 11:19:54.418146 ==
2586 11:19:54.425073 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2587 11:19:54.428238 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2588 11:19:54.438316 [CA 0] Center 39 (9~70) winsize 62
2589 11:19:54.441500 [CA 1] Center 39 (9~70) winsize 62
2590 11:19:54.444437 [CA 2] Center 35 (5~66) winsize 62
2591 11:19:54.448049 [CA 3] Center 34 (4~65) winsize 62
2592 11:19:54.450802 [CA 4] Center 33 (3~64) winsize 62
2593 11:19:54.454905 [CA 5] Center 33 (3~63) winsize 61
2594 11:19:54.454989
2595 11:19:54.457967 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2596 11:19:54.458052
2597 11:19:54.460781 [CATrainingPosCal] consider 2 rank data
2598 11:19:54.463827 u2DelayCellTimex100 = 270/100 ps
2599 11:19:54.470831 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2600 11:19:54.474143 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2601 11:19:54.477107 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2602 11:19:54.480681 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2603 11:19:54.483927 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2604 11:19:54.487565 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2605 11:19:54.487649
2606 11:19:54.490467 CA PerBit enable=1, Macro0, CA PI delay=33
2607 11:19:54.490551
2608 11:19:54.493925 [CBTSetCACLKResult] CA Dly = 33
2609 11:19:54.497125 CS Dly: 8 (0~40)
2610 11:19:54.497210
2611 11:19:54.501163 ----->DramcWriteLeveling(PI) begin...
2612 11:19:54.501249 ==
2613 11:19:54.503935 Dram Type= 6, Freq= 0, CH_0, rank 0
2614 11:19:54.507154 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2615 11:19:54.507240 ==
2616 11:19:54.510658 Write leveling (Byte 0): 33 => 33
2617 11:19:54.513823 Write leveling (Byte 1): 28 => 28
2618 11:19:54.516877 DramcWriteLeveling(PI) end<-----
2619 11:19:54.516962
2620 11:19:54.517046 ==
2621 11:19:54.520750 Dram Type= 6, Freq= 0, CH_0, rank 0
2622 11:19:54.523679 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2623 11:19:54.523764 ==
2624 11:19:54.527042 [Gating] SW mode calibration
2625 11:19:54.534177 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2626 11:19:54.540236 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2627 11:19:54.544076 0 15 0 | B1->B0 | 2323 2d2d | 0 1 | (0 0) (0 0)
2628 11:19:54.547223 0 15 4 | B1->B0 | 2525 3434 | 1 1 | (0 0) (1 1)
2629 11:19:54.553661 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2630 11:19:54.556863 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2631 11:19:54.560204 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2632 11:19:54.566652 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2633 11:19:54.570361 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2634 11:19:54.573368 0 15 28 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
2635 11:19:54.580455 1 0 0 | B1->B0 | 3232 2323 | 0 0 | (0 1) (0 0)
2636 11:19:54.583343 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2637 11:19:54.586799 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2638 11:19:54.593274 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2639 11:19:54.596947 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2640 11:19:54.600623 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2641 11:19:54.606592 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2642 11:19:54.610290 1 0 28 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
2643 11:19:54.613224 1 1 0 | B1->B0 | 2525 4444 | 1 0 | (0 0) (0 0)
2644 11:19:54.620080 1 1 4 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
2645 11:19:54.623671 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2646 11:19:54.626593 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2647 11:19:54.633210 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2648 11:19:54.636555 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2649 11:19:54.639717 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2650 11:19:54.643257 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2651 11:19:54.649818 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2652 11:19:54.653179 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2653 11:19:54.656713 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2654 11:19:54.663055 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2655 11:19:54.666644 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2656 11:19:54.669790 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2657 11:19:54.676672 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2658 11:19:54.679398 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2659 11:19:54.682998 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2660 11:19:54.689543 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2661 11:19:54.693043 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2662 11:19:54.696181 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2663 11:19:54.703038 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2664 11:19:54.706432 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2665 11:19:54.709759 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2666 11:19:54.715999 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2667 11:19:54.719987 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2668 11:19:54.722525 Total UI for P1: 0, mck2ui 16
2669 11:19:54.726202 best dqsien dly found for B0: ( 1, 3, 26)
2670 11:19:54.729454 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2671 11:19:54.732426 Total UI for P1: 0, mck2ui 16
2672 11:19:54.736025 best dqsien dly found for B1: ( 1, 4, 0)
2673 11:19:54.739241 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2674 11:19:54.742758 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2675 11:19:54.742843
2676 11:19:54.749231 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2677 11:19:54.752196 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2678 11:19:54.756149 [Gating] SW calibration Done
2679 11:19:54.756234 ==
2680 11:19:54.758971 Dram Type= 6, Freq= 0, CH_0, rank 0
2681 11:19:54.762220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2682 11:19:54.762305 ==
2683 11:19:54.762390 RX Vref Scan: 0
2684 11:19:54.762470
2685 11:19:54.765868 RX Vref 0 -> 0, step: 1
2686 11:19:54.765953
2687 11:19:54.769530 RX Delay -40 -> 252, step: 8
2688 11:19:54.772402 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2689 11:19:54.775391 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2690 11:19:54.782142 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2691 11:19:54.785495 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2692 11:19:54.788550 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2693 11:19:54.792400 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2694 11:19:54.795549 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2695 11:19:54.802027 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2696 11:19:54.805242 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2697 11:19:54.808409 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2698 11:19:54.812040 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2699 11:19:54.815178 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2700 11:19:54.822251 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2701 11:19:54.825177 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2702 11:19:54.828401 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2703 11:19:54.831523 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2704 11:19:54.831606 ==
2705 11:19:54.835197 Dram Type= 6, Freq= 0, CH_0, rank 0
2706 11:19:54.841598 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2707 11:19:54.841681 ==
2708 11:19:54.841746 DQS Delay:
2709 11:19:54.844699 DQS0 = 0, DQS1 = 0
2710 11:19:54.844780 DQM Delay:
2711 11:19:54.844845 DQM0 = 119, DQM1 = 106
2712 11:19:54.848703 DQ Delay:
2713 11:19:54.851717 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2714 11:19:54.855066 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2715 11:19:54.858193 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2716 11:19:54.861409 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2717 11:19:54.861516
2718 11:19:54.861618
2719 11:19:54.861708 ==
2720 11:19:54.864927 Dram Type= 6, Freq= 0, CH_0, rank 0
2721 11:19:54.867995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2722 11:19:54.871533 ==
2723 11:19:54.871614
2724 11:19:54.871679
2725 11:19:54.871739 TX Vref Scan disable
2726 11:19:54.874753 == TX Byte 0 ==
2727 11:19:54.878090 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2728 11:19:54.881043 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2729 11:19:54.884497 == TX Byte 1 ==
2730 11:19:54.887896 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2731 11:19:54.891359 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2732 11:19:54.894738 ==
2733 11:19:54.897672 Dram Type= 6, Freq= 0, CH_0, rank 0
2734 11:19:54.901153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2735 11:19:54.901236 ==
2736 11:19:54.912466 TX Vref=22, minBit 5, minWin=25, winSum=416
2737 11:19:54.915792 TX Vref=24, minBit 4, minWin=26, winSum=426
2738 11:19:54.919386 TX Vref=26, minBit 1, minWin=26, winSum=432
2739 11:19:54.922630 TX Vref=28, minBit 5, minWin=26, winSum=433
2740 11:19:54.926005 TX Vref=30, minBit 10, minWin=26, winSum=435
2741 11:19:54.932667 TX Vref=32, minBit 4, minWin=26, winSum=431
2742 11:19:54.935472 [TxChooseVref] Worse bit 10, Min win 26, Win sum 435, Final Vref 30
2743 11:19:54.935554
2744 11:19:54.939251 Final TX Range 1 Vref 30
2745 11:19:54.939333
2746 11:19:54.939398 ==
2747 11:19:54.942117 Dram Type= 6, Freq= 0, CH_0, rank 0
2748 11:19:54.945777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2749 11:19:54.949027 ==
2750 11:19:54.949109
2751 11:19:54.949173
2752 11:19:54.949233 TX Vref Scan disable
2753 11:19:54.952812 == TX Byte 0 ==
2754 11:19:54.956422 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2755 11:19:54.959460 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2756 11:19:54.962471 == TX Byte 1 ==
2757 11:19:54.966014 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2758 11:19:54.968996 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2759 11:19:54.972447
2760 11:19:54.972585 [DATLAT]
2761 11:19:54.972651 Freq=1200, CH0 RK0
2762 11:19:54.972713
2763 11:19:54.975837 DATLAT Default: 0xd
2764 11:19:54.975919 0, 0xFFFF, sum = 0
2765 11:19:54.979523 1, 0xFFFF, sum = 0
2766 11:19:54.979606 2, 0xFFFF, sum = 0
2767 11:19:54.982670 3, 0xFFFF, sum = 0
2768 11:19:54.986042 4, 0xFFFF, sum = 0
2769 11:19:54.986126 5, 0xFFFF, sum = 0
2770 11:19:54.989149 6, 0xFFFF, sum = 0
2771 11:19:54.989259 7, 0xFFFF, sum = 0
2772 11:19:54.992619 8, 0xFFFF, sum = 0
2773 11:19:54.992702 9, 0xFFFF, sum = 0
2774 11:19:54.995848 10, 0xFFFF, sum = 0
2775 11:19:54.995932 11, 0xFFFF, sum = 0
2776 11:19:54.998811 12, 0x0, sum = 1
2777 11:19:54.998894 13, 0x0, sum = 2
2778 11:19:55.002105 14, 0x0, sum = 3
2779 11:19:55.002187 15, 0x0, sum = 4
2780 11:19:55.002254 best_step = 13
2781 11:19:55.005670
2782 11:19:55.005751 ==
2783 11:19:55.008968 Dram Type= 6, Freq= 0, CH_0, rank 0
2784 11:19:55.012772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2785 11:19:55.012854 ==
2786 11:19:55.012919 RX Vref Scan: 1
2787 11:19:55.012980
2788 11:19:55.015465 Set Vref Range= 32 -> 127
2789 11:19:55.015547
2790 11:19:55.018911 RX Vref 32 -> 127, step: 1
2791 11:19:55.018993
2792 11:19:55.022313 RX Delay -21 -> 252, step: 4
2793 11:19:55.022394
2794 11:19:55.025898 Set Vref, RX VrefLevel [Byte0]: 32
2795 11:19:55.029065 [Byte1]: 32
2796 11:19:55.029147
2797 11:19:55.032437 Set Vref, RX VrefLevel [Byte0]: 33
2798 11:19:55.035234 [Byte1]: 33
2799 11:19:55.038947
2800 11:19:55.039028 Set Vref, RX VrefLevel [Byte0]: 34
2801 11:19:55.042243 [Byte1]: 34
2802 11:19:55.046784
2803 11:19:55.046865 Set Vref, RX VrefLevel [Byte0]: 35
2804 11:19:55.049963 [Byte1]: 35
2805 11:19:55.054650
2806 11:19:55.054730 Set Vref, RX VrefLevel [Byte0]: 36
2807 11:19:55.058445 [Byte1]: 36
2808 11:19:55.063185
2809 11:19:55.063266 Set Vref, RX VrefLevel [Byte0]: 37
2810 11:19:55.065958 [Byte1]: 37
2811 11:19:55.070741
2812 11:19:55.070822 Set Vref, RX VrefLevel [Byte0]: 38
2813 11:19:55.074281 [Byte1]: 38
2814 11:19:55.078738
2815 11:19:55.078819 Set Vref, RX VrefLevel [Byte0]: 39
2816 11:19:55.082095 [Byte1]: 39
2817 11:19:55.086517
2818 11:19:55.086598 Set Vref, RX VrefLevel [Byte0]: 40
2819 11:19:55.090271 [Byte1]: 40
2820 11:19:55.094519
2821 11:19:55.094601 Set Vref, RX VrefLevel [Byte0]: 41
2822 11:19:55.098045 [Byte1]: 41
2823 11:19:55.102593
2824 11:19:55.102675 Set Vref, RX VrefLevel [Byte0]: 42
2825 11:19:55.105990 [Byte1]: 42
2826 11:19:55.110474
2827 11:19:55.110556 Set Vref, RX VrefLevel [Byte0]: 43
2828 11:19:55.113642 [Byte1]: 43
2829 11:19:55.118617
2830 11:19:55.118698 Set Vref, RX VrefLevel [Byte0]: 44
2831 11:19:55.121864 [Byte1]: 44
2832 11:19:55.125778
2833 11:19:55.129445 Set Vref, RX VrefLevel [Byte0]: 45
2834 11:19:55.132470 [Byte1]: 45
2835 11:19:55.132591
2836 11:19:55.135859 Set Vref, RX VrefLevel [Byte0]: 46
2837 11:19:55.139399 [Byte1]: 46
2838 11:19:55.139482
2839 11:19:55.142741 Set Vref, RX VrefLevel [Byte0]: 47
2840 11:19:55.146526 [Byte1]: 47
2841 11:19:55.149912
2842 11:19:55.149993 Set Vref, RX VrefLevel [Byte0]: 48
2843 11:19:55.153180 [Byte1]: 48
2844 11:19:55.158012
2845 11:19:55.158092 Set Vref, RX VrefLevel [Byte0]: 49
2846 11:19:55.161258 [Byte1]: 49
2847 11:19:55.166081
2848 11:19:55.166162 Set Vref, RX VrefLevel [Byte0]: 50
2849 11:19:55.168966 [Byte1]: 50
2850 11:19:55.173555
2851 11:19:55.173637 Set Vref, RX VrefLevel [Byte0]: 51
2852 11:19:55.177230 [Byte1]: 51
2853 11:19:55.182106
2854 11:19:55.182187 Set Vref, RX VrefLevel [Byte0]: 52
2855 11:19:55.185013 [Byte1]: 52
2856 11:19:55.189431
2857 11:19:55.189512 Set Vref, RX VrefLevel [Byte0]: 53
2858 11:19:55.193013 [Byte1]: 53
2859 11:19:55.197566
2860 11:19:55.197647 Set Vref, RX VrefLevel [Byte0]: 54
2861 11:19:55.201205 [Byte1]: 54
2862 11:19:55.205382
2863 11:19:55.205463 Set Vref, RX VrefLevel [Byte0]: 55
2864 11:19:55.208756 [Byte1]: 55
2865 11:19:55.213288
2866 11:19:55.213370 Set Vref, RX VrefLevel [Byte0]: 56
2867 11:19:55.216681 [Byte1]: 56
2868 11:19:55.221256
2869 11:19:55.221337 Set Vref, RX VrefLevel [Byte0]: 57
2870 11:19:55.224362 [Byte1]: 57
2871 11:19:55.228992
2872 11:19:55.229073 Set Vref, RX VrefLevel [Byte0]: 58
2873 11:19:55.232687 [Byte1]: 58
2874 11:19:55.237060
2875 11:19:55.237141 Set Vref, RX VrefLevel [Byte0]: 59
2876 11:19:55.240807 [Byte1]: 59
2877 11:19:55.245182
2878 11:19:55.245263 Set Vref, RX VrefLevel [Byte0]: 60
2879 11:19:55.248391 [Byte1]: 60
2880 11:19:55.253145
2881 11:19:55.253227 Set Vref, RX VrefLevel [Byte0]: 61
2882 11:19:55.256070 [Byte1]: 61
2883 11:19:55.261106
2884 11:19:55.261187 Set Vref, RX VrefLevel [Byte0]: 62
2885 11:19:55.264451 [Byte1]: 62
2886 11:19:55.268876
2887 11:19:55.268958 Set Vref, RX VrefLevel [Byte0]: 63
2888 11:19:55.272055 [Byte1]: 63
2889 11:19:55.276501
2890 11:19:55.276617 Set Vref, RX VrefLevel [Byte0]: 64
2891 11:19:55.280088 [Byte1]: 64
2892 11:19:55.284912
2893 11:19:55.284993 Set Vref, RX VrefLevel [Byte0]: 65
2894 11:19:55.287880 [Byte1]: 65
2895 11:19:55.292450
2896 11:19:55.292555 Set Vref, RX VrefLevel [Byte0]: 66
2897 11:19:55.295754 [Byte1]: 66
2898 11:19:55.300878
2899 11:19:55.300960 Set Vref, RX VrefLevel [Byte0]: 67
2900 11:19:55.303614 [Byte1]: 67
2901 11:19:55.308210
2902 11:19:55.308292 Set Vref, RX VrefLevel [Byte0]: 68
2903 11:19:55.311646 [Byte1]: 68
2904 11:19:55.316448
2905 11:19:55.316569 Set Vref, RX VrefLevel [Byte0]: 69
2906 11:19:55.320020 [Byte1]: 69
2907 11:19:55.324353
2908 11:19:55.327543 Set Vref, RX VrefLevel [Byte0]: 70
2909 11:19:55.331225 [Byte1]: 70
2910 11:19:55.331306
2911 11:19:55.333901 Set Vref, RX VrefLevel [Byte0]: 71
2912 11:19:55.337575 [Byte1]: 71
2913 11:19:55.337657
2914 11:19:55.340522 Set Vref, RX VrefLevel [Byte0]: 72
2915 11:19:55.343980 [Byte1]: 72
2916 11:19:55.348267
2917 11:19:55.348349 Set Vref, RX VrefLevel [Byte0]: 73
2918 11:19:55.351376 [Byte1]: 73
2919 11:19:55.355715
2920 11:19:55.355797 Set Vref, RX VrefLevel [Byte0]: 74
2921 11:19:55.359325 [Byte1]: 74
2922 11:19:55.364043
2923 11:19:55.364125 Set Vref, RX VrefLevel [Byte0]: 75
2924 11:19:55.367278 [Byte1]: 75
2925 11:19:55.371895
2926 11:19:55.371977 Set Vref, RX VrefLevel [Byte0]: 76
2927 11:19:55.374993 [Byte1]: 76
2928 11:19:55.379915
2929 11:19:55.379996 Set Vref, RX VrefLevel [Byte0]: 77
2930 11:19:55.382891 [Byte1]: 77
2931 11:19:55.387702
2932 11:19:55.387784 Set Vref, RX VrefLevel [Byte0]: 78
2933 11:19:55.390789 [Byte1]: 78
2934 11:19:55.395625
2935 11:19:55.395717 Final RX Vref Byte 0 = 60 to rank0
2936 11:19:55.398913 Final RX Vref Byte 1 = 49 to rank0
2937 11:19:55.402214 Final RX Vref Byte 0 = 60 to rank1
2938 11:19:55.406555 Final RX Vref Byte 1 = 49 to rank1==
2939 11:19:55.409192 Dram Type= 6, Freq= 0, CH_0, rank 0
2940 11:19:55.415493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2941 11:19:55.415616 ==
2942 11:19:55.415714 DQS Delay:
2943 11:19:55.415804 DQS0 = 0, DQS1 = 0
2944 11:19:55.419660 DQM Delay:
2945 11:19:55.419880 DQM0 = 119, DQM1 = 106
2946 11:19:55.423066 DQ Delay:
2947 11:19:55.426115 DQ0 =116, DQ1 =120, DQ2 =116, DQ3 =116
2948 11:19:55.428961 DQ4 =120, DQ5 =114, DQ6 =128, DQ7 =124
2949 11:19:55.432927 DQ8 =96, DQ9 =94, DQ10 =108, DQ11 =100
2950 11:19:55.435611 DQ12 =112, DQ13 =110, DQ14 =118, DQ15 =116
2951 11:19:55.435895
2952 11:19:55.436066
2953 11:19:55.442992 [DQSOSCAuto] RK0, (LSB)MR18= 0xdf9, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 405 ps
2954 11:19:55.445720 CH0 RK0: MR19=403, MR18=DF9
2955 11:19:55.452919 CH0_RK0: MR19=0x403, MR18=0xDF9, DQSOSC=405, MR23=63, INC=39, DEC=26
2956 11:19:55.453403
2957 11:19:55.455998 ----->DramcWriteLeveling(PI) begin...
2958 11:19:55.456470 ==
2959 11:19:55.459595 Dram Type= 6, Freq= 0, CH_0, rank 1
2960 11:19:55.462893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2961 11:19:55.463477 ==
2962 11:19:55.465915 Write leveling (Byte 0): 32 => 32
2963 11:19:55.468975 Write leveling (Byte 1): 29 => 29
2964 11:19:55.472432 DramcWriteLeveling(PI) end<-----
2965 11:19:55.472928
2966 11:19:55.473269 ==
2967 11:19:55.475865 Dram Type= 6, Freq= 0, CH_0, rank 1
2968 11:19:55.482733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2969 11:19:55.483295 ==
2970 11:19:55.483645 [Gating] SW mode calibration
2971 11:19:55.492260 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2972 11:19:55.495857 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2973 11:19:55.502614 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2974 11:19:55.505435 0 15 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
2975 11:19:55.508785 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2976 11:19:55.512410 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2977 11:19:55.518818 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2978 11:19:55.522040 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2979 11:19:55.525150 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2980 11:19:55.531991 0 15 28 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 1)
2981 11:19:55.535365 1 0 0 | B1->B0 | 2e2e 2323 | 0 0 | (1 0) (0 0)
2982 11:19:55.538630 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2983 11:19:55.545569 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2984 11:19:55.548967 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2985 11:19:55.552371 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2986 11:19:55.558444 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2987 11:19:55.562102 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2988 11:19:55.565443 1 0 28 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
2989 11:19:55.572131 1 1 0 | B1->B0 | 3534 4646 | 1 0 | (0 0) (0 0)
2990 11:19:55.575370 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2991 11:19:55.578709 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2992 11:19:55.585532 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2993 11:19:55.588344 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2994 11:19:55.591690 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2995 11:19:55.598618 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2996 11:19:55.601743 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2997 11:19:55.604799 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2998 11:19:55.611608 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2999 11:19:55.615449 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3000 11:19:55.618462 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3001 11:19:55.624489 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3002 11:19:55.628173 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3003 11:19:55.631770 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3004 11:19:55.638262 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3005 11:19:55.641434 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3006 11:19:55.644477 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3007 11:19:55.651808 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3008 11:19:55.654767 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3009 11:19:55.657778 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3010 11:19:55.665004 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3011 11:19:55.667885 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3012 11:19:55.671120 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3013 11:19:55.677749 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3014 11:19:55.681649 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3015 11:19:55.684455 Total UI for P1: 0, mck2ui 16
3016 11:19:55.687721 best dqsien dly found for B0: ( 1, 3, 30)
3017 11:19:55.690981 Total UI for P1: 0, mck2ui 16
3018 11:19:55.694345 best dqsien dly found for B1: ( 1, 4, 0)
3019 11:19:55.698108 best DQS0 dly(MCK, UI, PI) = (1, 3, 30)
3020 11:19:55.701222 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
3021 11:19:55.701688
3022 11:19:55.704405 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 30)
3023 11:19:55.707799 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
3024 11:19:55.711192 [Gating] SW calibration Done
3025 11:19:55.711792 ==
3026 11:19:55.714771 Dram Type= 6, Freq= 0, CH_0, rank 1
3027 11:19:55.717829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3028 11:19:55.718405 ==
3029 11:19:55.721194 RX Vref Scan: 0
3030 11:19:55.721658
3031 11:19:55.724245 RX Vref 0 -> 0, step: 1
3032 11:19:55.724738
3033 11:19:55.725108 RX Delay -40 -> 252, step: 8
3034 11:19:55.731549 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
3035 11:19:55.734070 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
3036 11:19:55.738063 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3037 11:19:55.740856 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3038 11:19:55.744409 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3039 11:19:55.751330 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
3040 11:19:55.754151 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3041 11:19:55.757490 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
3042 11:19:55.761049 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3043 11:19:55.764172 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3044 11:19:55.770770 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3045 11:19:55.774488 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3046 11:19:55.777255 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3047 11:19:55.780606 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3048 11:19:55.784121 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3049 11:19:55.790548 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3050 11:19:55.791107 ==
3051 11:19:55.793483 Dram Type= 6, Freq= 0, CH_0, rank 1
3052 11:19:55.797177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3053 11:19:55.797656 ==
3054 11:19:55.798037 DQS Delay:
3055 11:19:55.800692 DQS0 = 0, DQS1 = 0
3056 11:19:55.801155 DQM Delay:
3057 11:19:55.803725 DQM0 = 116, DQM1 = 108
3058 11:19:55.804189 DQ Delay:
3059 11:19:55.806883 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =115
3060 11:19:55.810956 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =123
3061 11:19:55.813950 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3062 11:19:55.817039 DQ12 =111, DQ13 =119, DQ14 =119, DQ15 =111
3063 11:19:55.817517
3064 11:19:55.820603
3065 11:19:55.821073 ==
3066 11:19:55.824118 Dram Type= 6, Freq= 0, CH_0, rank 1
3067 11:19:55.827621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3068 11:19:55.828203 ==
3069 11:19:55.828624
3070 11:19:55.828980
3071 11:19:55.830125 TX Vref Scan disable
3072 11:19:55.830598 == TX Byte 0 ==
3073 11:19:55.837319 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3074 11:19:55.839957 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3075 11:19:55.840449 == TX Byte 1 ==
3076 11:19:55.846932 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3077 11:19:55.850270 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3078 11:19:55.850852 ==
3079 11:19:55.853726 Dram Type= 6, Freq= 0, CH_0, rank 1
3080 11:19:55.856791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3081 11:19:55.857442 ==
3082 11:19:55.869233 TX Vref=22, minBit 5, minWin=25, winSum=420
3083 11:19:55.872730 TX Vref=24, minBit 13, minWin=25, winSum=426
3084 11:19:55.876144 TX Vref=26, minBit 1, minWin=26, winSum=432
3085 11:19:55.879602 TX Vref=28, minBit 10, minWin=26, winSum=432
3086 11:19:55.882774 TX Vref=30, minBit 13, minWin=26, winSum=434
3087 11:19:55.889255 TX Vref=32, minBit 10, minWin=26, winSum=429
3088 11:19:55.892472 [TxChooseVref] Worse bit 13, Min win 26, Win sum 434, Final Vref 30
3089 11:19:55.893078
3090 11:19:55.896045 Final TX Range 1 Vref 30
3091 11:19:55.896672
3092 11:19:55.897130 ==
3093 11:19:55.899901 Dram Type= 6, Freq= 0, CH_0, rank 1
3094 11:19:55.902650 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3095 11:19:55.906381 ==
3096 11:19:55.906860
3097 11:19:55.907259
3098 11:19:55.907613 TX Vref Scan disable
3099 11:19:55.909936 == TX Byte 0 ==
3100 11:19:55.912650 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
3101 11:19:55.916591 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
3102 11:19:55.919519 == TX Byte 1 ==
3103 11:19:55.922628 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3104 11:19:55.926376 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3105 11:19:55.929474
3106 11:19:55.930033 [DATLAT]
3107 11:19:55.930412 Freq=1200, CH0 RK1
3108 11:19:55.930767
3109 11:19:55.932563 DATLAT Default: 0xd
3110 11:19:55.933073 0, 0xFFFF, sum = 0
3111 11:19:55.935919 1, 0xFFFF, sum = 0
3112 11:19:55.936401 2, 0xFFFF, sum = 0
3113 11:19:55.939338 3, 0xFFFF, sum = 0
3114 11:19:55.943054 4, 0xFFFF, sum = 0
3115 11:19:55.943535 5, 0xFFFF, sum = 0
3116 11:19:55.945951 6, 0xFFFF, sum = 0
3117 11:19:55.946432 7, 0xFFFF, sum = 0
3118 11:19:55.949623 8, 0xFFFF, sum = 0
3119 11:19:55.950201 9, 0xFFFF, sum = 0
3120 11:19:55.952817 10, 0xFFFF, sum = 0
3121 11:19:55.953394 11, 0xFFFF, sum = 0
3122 11:19:55.956063 12, 0x0, sum = 1
3123 11:19:55.956674 13, 0x0, sum = 2
3124 11:19:55.959278 14, 0x0, sum = 3
3125 11:19:55.959755 15, 0x0, sum = 4
3126 11:19:55.962978 best_step = 13
3127 11:19:55.963547
3128 11:19:55.963923 ==
3129 11:19:55.965903 Dram Type= 6, Freq= 0, CH_0, rank 1
3130 11:19:55.969355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3131 11:19:55.969925 ==
3132 11:19:55.972160 RX Vref Scan: 0
3133 11:19:55.972650
3134 11:19:55.973023 RX Vref 0 -> 0, step: 1
3135 11:19:55.973374
3136 11:19:55.975339 RX Delay -21 -> 252, step: 4
3137 11:19:55.982285 iDelay=199, Bit 0, Center 114 (47 ~ 182) 136
3138 11:19:55.985297 iDelay=199, Bit 1, Center 118 (47 ~ 190) 144
3139 11:19:55.988661 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3140 11:19:55.991877 iDelay=199, Bit 3, Center 114 (43 ~ 186) 144
3141 11:19:55.995669 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3142 11:19:56.002038 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3143 11:19:56.005129 iDelay=199, Bit 6, Center 126 (55 ~ 198) 144
3144 11:19:56.008533 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3145 11:19:56.012285 iDelay=199, Bit 8, Center 96 (27 ~ 166) 140
3146 11:19:56.015689 iDelay=199, Bit 9, Center 94 (27 ~ 162) 136
3147 11:19:56.022275 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3148 11:19:56.025488 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3149 11:19:56.028110 iDelay=199, Bit 12, Center 114 (47 ~ 182) 136
3150 11:19:56.032115 iDelay=199, Bit 13, Center 114 (47 ~ 182) 136
3151 11:19:56.035547 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
3152 11:19:56.041637 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
3153 11:19:56.042203 ==
3154 11:19:56.045323 Dram Type= 6, Freq= 0, CH_0, rank 1
3155 11:19:56.048464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3156 11:19:56.049072 ==
3157 11:19:56.049451 DQS Delay:
3158 11:19:56.052303 DQS0 = 0, DQS1 = 0
3159 11:19:56.052912 DQM Delay:
3160 11:19:56.055145 DQM0 = 116, DQM1 = 107
3161 11:19:56.055716 DQ Delay:
3162 11:19:56.058535 DQ0 =114, DQ1 =118, DQ2 =110, DQ3 =114
3163 11:19:56.061624 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124
3164 11:19:56.065231 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =100
3165 11:19:56.068066 DQ12 =114, DQ13 =114, DQ14 =118, DQ15 =116
3166 11:19:56.068669
3167 11:19:56.069065
3168 11:19:56.078554 [DQSOSCAuto] RK1, (LSB)MR18= 0xde8, (MSB)MR19= 0x403, tDQSOscB0 = 420 ps tDQSOscB1 = 405 ps
3169 11:19:56.081605 CH0 RK1: MR19=403, MR18=DE8
3170 11:19:56.085990 CH0_RK1: MR19=0x403, MR18=0xDE8, DQSOSC=405, MR23=63, INC=39, DEC=26
3171 11:19:56.088665 [RxdqsGatingPostProcess] freq 1200
3172 11:19:56.094903 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3173 11:19:56.098113 best DQS0 dly(2T, 0.5T) = (0, 11)
3174 11:19:56.101584 best DQS1 dly(2T, 0.5T) = (0, 12)
3175 11:19:56.104488 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3176 11:19:56.108335 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3177 11:19:56.111188 best DQS0 dly(2T, 0.5T) = (0, 11)
3178 11:19:56.114704 best DQS1 dly(2T, 0.5T) = (0, 12)
3179 11:19:56.118058 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3180 11:19:56.121349 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3181 11:19:56.124606 Pre-setting of DQS Precalculation
3182 11:19:56.128160 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3183 11:19:56.128686 ==
3184 11:19:56.131628 Dram Type= 6, Freq= 0, CH_1, rank 0
3185 11:19:56.134852 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3186 11:19:56.135430 ==
3187 11:19:56.140939 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3188 11:19:56.148302 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3189 11:19:56.156019 [CA 0] Center 37 (7~68) winsize 62
3190 11:19:56.158912 [CA 1] Center 37 (7~68) winsize 62
3191 11:19:56.161941 [CA 2] Center 34 (4~64) winsize 61
3192 11:19:56.165827 [CA 3] Center 33 (3~64) winsize 62
3193 11:19:56.169080 [CA 4] Center 34 (4~64) winsize 61
3194 11:19:56.172400 [CA 5] Center 33 (3~64) winsize 62
3195 11:19:56.172919
3196 11:19:56.175674 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3197 11:19:56.176243
3198 11:19:56.179105 [CATrainingPosCal] consider 1 rank data
3199 11:19:56.182118 u2DelayCellTimex100 = 270/100 ps
3200 11:19:56.185588 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3201 11:19:56.191726 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3202 11:19:56.195227 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3203 11:19:56.198750 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3204 11:19:56.201779 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3205 11:19:56.205119 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3206 11:19:56.205697
3207 11:19:56.208731 CA PerBit enable=1, Macro0, CA PI delay=33
3208 11:19:56.209206
3209 11:19:56.211832 [CBTSetCACLKResult] CA Dly = 33
3210 11:19:56.212301 CS Dly: 6 (0~37)
3211 11:19:56.215333 ==
3212 11:19:56.218612 Dram Type= 6, Freq= 0, CH_1, rank 1
3213 11:19:56.221728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3214 11:19:56.222204 ==
3215 11:19:56.225313 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3216 11:19:56.231783 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3217 11:19:56.241320 [CA 0] Center 37 (7~68) winsize 62
3218 11:19:56.245077 [CA 1] Center 38 (8~68) winsize 61
3219 11:19:56.248196 [CA 2] Center 34 (4~65) winsize 62
3220 11:19:56.251312 [CA 3] Center 33 (3~64) winsize 62
3221 11:19:56.254646 [CA 4] Center 34 (4~65) winsize 62
3222 11:19:56.258208 [CA 5] Center 33 (3~64) winsize 62
3223 11:19:56.258678
3224 11:19:56.261514 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3225 11:19:56.262094
3226 11:19:56.264551 [CATrainingPosCal] consider 2 rank data
3227 11:19:56.268160 u2DelayCellTimex100 = 270/100 ps
3228 11:19:56.271389 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3229 11:19:56.274704 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3230 11:19:56.281231 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3231 11:19:56.284679 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3232 11:19:56.287797 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3233 11:19:56.291167 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3234 11:19:56.291762
3235 11:19:56.294265 CA PerBit enable=1, Macro0, CA PI delay=33
3236 11:19:56.294836
3237 11:19:56.297757 [CBTSetCACLKResult] CA Dly = 33
3238 11:19:56.298326 CS Dly: 7 (0~40)
3239 11:19:56.298700
3240 11:19:56.300715 ----->DramcWriteLeveling(PI) begin...
3241 11:19:56.304730 ==
3242 11:19:56.308217 Dram Type= 6, Freq= 0, CH_1, rank 0
3243 11:19:56.310824 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3244 11:19:56.311310 ==
3245 11:19:56.314595 Write leveling (Byte 0): 26 => 26
3246 11:19:56.317329 Write leveling (Byte 1): 26 => 26
3247 11:19:56.320949 DramcWriteLeveling(PI) end<-----
3248 11:19:56.321431
3249 11:19:56.321805 ==
3250 11:19:56.324283 Dram Type= 6, Freq= 0, CH_1, rank 0
3251 11:19:56.327224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3252 11:19:56.327727 ==
3253 11:19:56.331007 [Gating] SW mode calibration
3254 11:19:56.337910 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3255 11:19:56.344301 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3256 11:19:56.347766 0 15 0 | B1->B0 | 3232 3434 | 1 1 | (0 0) (1 1)
3257 11:19:56.350693 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3258 11:19:56.354288 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3259 11:19:56.361006 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3260 11:19:56.364575 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3261 11:19:56.367941 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3262 11:19:56.374550 0 15 24 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 1)
3263 11:19:56.377304 0 15 28 | B1->B0 | 2929 2323 | 0 0 | (0 0) (1 0)
3264 11:19:56.381080 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3265 11:19:56.387876 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3266 11:19:56.390855 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3267 11:19:56.394596 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3268 11:19:56.400474 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3269 11:19:56.403983 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3270 11:19:56.407599 1 0 24 | B1->B0 | 2727 3a3a | 0 1 | (0 0) (0 0)
3271 11:19:56.413904 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3272 11:19:56.417982 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3273 11:19:56.420506 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3274 11:19:56.427464 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3275 11:19:56.430515 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3276 11:19:56.433972 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3277 11:19:56.440431 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3278 11:19:56.443758 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3279 11:19:56.446981 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3280 11:19:56.454009 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3281 11:19:56.456723 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3282 11:19:56.460017 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3283 11:19:56.467292 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3284 11:19:56.470379 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3285 11:19:56.473613 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3286 11:19:56.480190 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3287 11:19:56.483694 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3288 11:19:56.486912 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3289 11:19:56.494085 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3290 11:19:56.497119 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3291 11:19:56.500282 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3292 11:19:56.506901 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3293 11:19:56.510482 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3294 11:19:56.513746 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3295 11:19:56.517035 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3296 11:19:56.520273 Total UI for P1: 0, mck2ui 16
3297 11:19:56.523618 best dqsien dly found for B0: ( 1, 3, 24)
3298 11:19:56.530302 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3299 11:19:56.533222 Total UI for P1: 0, mck2ui 16
3300 11:19:56.536752 best dqsien dly found for B1: ( 1, 3, 26)
3301 11:19:56.540183 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3302 11:19:56.543520 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3303 11:19:56.544084
3304 11:19:56.546252 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3305 11:19:56.549803 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3306 11:19:56.553388 [Gating] SW calibration Done
3307 11:19:56.553952 ==
3308 11:19:56.556423 Dram Type= 6, Freq= 0, CH_1, rank 0
3309 11:19:56.559678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3310 11:19:56.560150 ==
3311 11:19:56.563437 RX Vref Scan: 0
3312 11:19:56.564002
3313 11:19:56.566220 RX Vref 0 -> 0, step: 1
3314 11:19:56.566691
3315 11:19:56.567063 RX Delay -40 -> 252, step: 8
3316 11:19:56.572869 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3317 11:19:56.576325 iDelay=208, Bit 1, Center 115 (40 ~ 191) 152
3318 11:19:56.580126 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3319 11:19:56.582987 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3320 11:19:56.586292 iDelay=208, Bit 4, Center 111 (40 ~ 183) 144
3321 11:19:56.593040 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3322 11:19:56.596938 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3323 11:19:56.599466 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3324 11:19:56.603330 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3325 11:19:56.606126 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3326 11:19:56.612496 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3327 11:19:56.616572 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3328 11:19:56.619677 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3329 11:19:56.622490 iDelay=208, Bit 13, Center 115 (40 ~ 191) 152
3330 11:19:56.626389 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3331 11:19:56.632754 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3332 11:19:56.633238 ==
3333 11:19:56.635998 Dram Type= 6, Freq= 0, CH_1, rank 0
3334 11:19:56.639411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3335 11:19:56.640004 ==
3336 11:19:56.640493 DQS Delay:
3337 11:19:56.642890 DQS0 = 0, DQS1 = 0
3338 11:19:56.643427 DQM Delay:
3339 11:19:56.646064 DQM0 = 118, DQM1 = 108
3340 11:19:56.646539 DQ Delay:
3341 11:19:56.648945 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =115
3342 11:19:56.652377 DQ4 =111, DQ5 =131, DQ6 =123, DQ7 =115
3343 11:19:56.655939 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =95
3344 11:19:56.659058 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =119
3345 11:19:56.659527
3346 11:19:56.662406
3347 11:19:56.662870 ==
3348 11:19:56.665977 Dram Type= 6, Freq= 0, CH_1, rank 0
3349 11:19:56.669429 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3350 11:19:56.670001 ==
3351 11:19:56.670374
3352 11:19:56.670715
3353 11:19:56.672322 TX Vref Scan disable
3354 11:19:56.672861 == TX Byte 0 ==
3355 11:19:56.678925 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3356 11:19:56.682049 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3357 11:19:56.682540 == TX Byte 1 ==
3358 11:19:56.689110 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3359 11:19:56.692194 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3360 11:19:56.692736 ==
3361 11:19:56.695339 Dram Type= 6, Freq= 0, CH_1, rank 0
3362 11:19:56.698668 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3363 11:19:56.699133 ==
3364 11:19:56.710988 TX Vref=22, minBit 10, minWin=25, winSum=415
3365 11:19:56.713904 TX Vref=24, minBit 9, minWin=25, winSum=418
3366 11:19:56.717805 TX Vref=26, minBit 10, minWin=25, winSum=427
3367 11:19:56.721012 TX Vref=28, minBit 11, minWin=25, winSum=430
3368 11:19:56.724202 TX Vref=30, minBit 9, minWin=26, winSum=430
3369 11:19:56.730951 TX Vref=32, minBit 9, minWin=25, winSum=425
3370 11:19:56.734417 [TxChooseVref] Worse bit 9, Min win 26, Win sum 430, Final Vref 30
3371 11:19:56.734846
3372 11:19:56.737768 Final TX Range 1 Vref 30
3373 11:19:56.738297
3374 11:19:56.738632 ==
3375 11:19:56.740658 Dram Type= 6, Freq= 0, CH_1, rank 0
3376 11:19:56.744132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3377 11:19:56.747046 ==
3378 11:19:56.747508
3379 11:19:56.747876
3380 11:19:56.748213 TX Vref Scan disable
3381 11:19:56.751014 == TX Byte 0 ==
3382 11:19:56.754128 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3383 11:19:56.760968 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3384 11:19:56.761389 == TX Byte 1 ==
3385 11:19:56.763940 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3386 11:19:56.770845 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3387 11:19:56.771366
3388 11:19:56.771701 [DATLAT]
3389 11:19:56.772009 Freq=1200, CH1 RK0
3390 11:19:56.772307
3391 11:19:56.773991 DATLAT Default: 0xd
3392 11:19:56.777406 0, 0xFFFF, sum = 0
3393 11:19:56.777967 1, 0xFFFF, sum = 0
3394 11:19:56.780661 2, 0xFFFF, sum = 0
3395 11:19:56.781199 3, 0xFFFF, sum = 0
3396 11:19:56.784287 4, 0xFFFF, sum = 0
3397 11:19:56.784867 5, 0xFFFF, sum = 0
3398 11:19:56.787255 6, 0xFFFF, sum = 0
3399 11:19:56.787783 7, 0xFFFF, sum = 0
3400 11:19:56.790403 8, 0xFFFF, sum = 0
3401 11:19:56.790829 9, 0xFFFF, sum = 0
3402 11:19:56.793636 10, 0xFFFF, sum = 0
3403 11:19:56.794065 11, 0xFFFF, sum = 0
3404 11:19:56.797434 12, 0x0, sum = 1
3405 11:19:56.797903 13, 0x0, sum = 2
3406 11:19:56.800749 14, 0x0, sum = 3
3407 11:19:56.801325 15, 0x0, sum = 4
3408 11:19:56.803533 best_step = 13
3409 11:19:56.803993
3410 11:19:56.804353 ==
3411 11:19:56.807163 Dram Type= 6, Freq= 0, CH_1, rank 0
3412 11:19:56.810387 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3413 11:19:56.811053 ==
3414 11:19:56.811424 RX Vref Scan: 1
3415 11:19:56.813514
3416 11:19:56.813975 Set Vref Range= 32 -> 127
3417 11:19:56.814341
3418 11:19:56.817046 RX Vref 32 -> 127, step: 1
3419 11:19:56.817464
3420 11:19:56.820358 RX Delay -21 -> 252, step: 4
3421 11:19:56.820805
3422 11:19:56.824175 Set Vref, RX VrefLevel [Byte0]: 32
3423 11:19:56.827631 [Byte1]: 32
3424 11:19:56.828141
3425 11:19:56.830374 Set Vref, RX VrefLevel [Byte0]: 33
3426 11:19:56.834063 [Byte1]: 33
3427 11:19:56.837168
3428 11:19:56.837691 Set Vref, RX VrefLevel [Byte0]: 34
3429 11:19:56.841060 [Byte1]: 34
3430 11:19:56.845171
3431 11:19:56.845740 Set Vref, RX VrefLevel [Byte0]: 35
3432 11:19:56.848615 [Byte1]: 35
3433 11:19:56.853155
3434 11:19:56.853711 Set Vref, RX VrefLevel [Byte0]: 36
3435 11:19:56.857041 [Byte1]: 36
3436 11:19:56.861698
3437 11:19:56.862162 Set Vref, RX VrefLevel [Byte0]: 37
3438 11:19:56.864767 [Byte1]: 37
3439 11:19:56.869257
3440 11:19:56.869717 Set Vref, RX VrefLevel [Byte0]: 38
3441 11:19:56.872981 [Byte1]: 38
3442 11:19:56.877009
3443 11:19:56.877558 Set Vref, RX VrefLevel [Byte0]: 39
3444 11:19:56.880111 [Byte1]: 39
3445 11:19:56.884867
3446 11:19:56.885476 Set Vref, RX VrefLevel [Byte0]: 40
3447 11:19:56.888622 [Byte1]: 40
3448 11:19:56.892867
3449 11:19:56.893418 Set Vref, RX VrefLevel [Byte0]: 41
3450 11:19:56.896302 [Byte1]: 41
3451 11:19:56.900821
3452 11:19:56.901372 Set Vref, RX VrefLevel [Byte0]: 42
3453 11:19:56.904123 [Byte1]: 42
3454 11:19:56.908497
3455 11:19:56.909114 Set Vref, RX VrefLevel [Byte0]: 43
3456 11:19:56.911673 [Byte1]: 43
3457 11:19:56.916210
3458 11:19:56.916738 Set Vref, RX VrefLevel [Byte0]: 44
3459 11:19:56.919896 [Byte1]: 44
3460 11:19:56.924777
3461 11:19:56.925328 Set Vref, RX VrefLevel [Byte0]: 45
3462 11:19:56.927631 [Byte1]: 45
3463 11:19:56.932200
3464 11:19:56.932824 Set Vref, RX VrefLevel [Byte0]: 46
3465 11:19:56.935747 [Byte1]: 46
3466 11:19:56.940350
3467 11:19:56.940992 Set Vref, RX VrefLevel [Byte0]: 47
3468 11:19:56.944045 [Byte1]: 47
3469 11:19:56.947981
3470 11:19:56.948444 Set Vref, RX VrefLevel [Byte0]: 48
3471 11:19:56.951777 [Byte1]: 48
3472 11:19:56.956272
3473 11:19:56.956949 Set Vref, RX VrefLevel [Byte0]: 49
3474 11:19:56.959486 [Byte1]: 49
3475 11:19:56.964388
3476 11:19:56.964903 Set Vref, RX VrefLevel [Byte0]: 50
3477 11:19:56.967052 [Byte1]: 50
3478 11:19:56.972259
3479 11:19:56.972925 Set Vref, RX VrefLevel [Byte0]: 51
3480 11:19:56.975245 [Byte1]: 51
3481 11:19:56.980079
3482 11:19:56.980709 Set Vref, RX VrefLevel [Byte0]: 52
3483 11:19:56.983228 [Byte1]: 52
3484 11:19:56.987709
3485 11:19:56.988277 Set Vref, RX VrefLevel [Byte0]: 53
3486 11:19:56.991133 [Byte1]: 53
3487 11:19:56.995975
3488 11:19:56.996590 Set Vref, RX VrefLevel [Byte0]: 54
3489 11:19:56.998857 [Byte1]: 54
3490 11:19:57.003700
3491 11:19:57.004269 Set Vref, RX VrefLevel [Byte0]: 55
3492 11:19:57.007164 [Byte1]: 55
3493 11:19:57.012427
3494 11:19:57.013070 Set Vref, RX VrefLevel [Byte0]: 56
3495 11:19:57.014881 [Byte1]: 56
3496 11:19:57.019800
3497 11:19:57.020365 Set Vref, RX VrefLevel [Byte0]: 57
3498 11:19:57.023109 [Byte1]: 57
3499 11:19:57.027671
3500 11:19:57.028236 Set Vref, RX VrefLevel [Byte0]: 58
3501 11:19:57.030800 [Byte1]: 58
3502 11:19:57.035363
3503 11:19:57.035928 Set Vref, RX VrefLevel [Byte0]: 59
3504 11:19:57.039291 [Byte1]: 59
3505 11:19:57.043390
3506 11:19:57.043954 Set Vref, RX VrefLevel [Byte0]: 60
3507 11:19:57.046852 [Byte1]: 60
3508 11:19:57.051417
3509 11:19:57.051981 Set Vref, RX VrefLevel [Byte0]: 61
3510 11:19:57.054489 [Byte1]: 61
3511 11:19:57.059304
3512 11:19:57.059865 Set Vref, RX VrefLevel [Byte0]: 62
3513 11:19:57.062740 [Byte1]: 62
3514 11:19:57.066942
3515 11:19:57.067502 Set Vref, RX VrefLevel [Byte0]: 63
3516 11:19:57.070319 [Byte1]: 63
3517 11:19:57.075401
3518 11:19:57.075963 Set Vref, RX VrefLevel [Byte0]: 64
3519 11:19:57.078438 [Byte1]: 64
3520 11:19:57.083056
3521 11:19:57.083623 Set Vref, RX VrefLevel [Byte0]: 65
3522 11:19:57.085953 [Byte1]: 65
3523 11:19:57.091077
3524 11:19:57.091638 Set Vref, RX VrefLevel [Byte0]: 66
3525 11:19:57.093755 [Byte1]: 66
3526 11:19:57.098700
3527 11:19:57.099265 Final RX Vref Byte 0 = 48 to rank0
3528 11:19:57.101819 Final RX Vref Byte 1 = 53 to rank0
3529 11:19:57.105382 Final RX Vref Byte 0 = 48 to rank1
3530 11:19:57.108584 Final RX Vref Byte 1 = 53 to rank1==
3531 11:19:57.111656 Dram Type= 6, Freq= 0, CH_1, rank 0
3532 11:19:57.118761 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3533 11:19:57.119335 ==
3534 11:19:57.119714 DQS Delay:
3535 11:19:57.121356 DQS0 = 0, DQS1 = 0
3536 11:19:57.121831 DQM Delay:
3537 11:19:57.122209 DQM0 = 116, DQM1 = 110
3538 11:19:57.124745 DQ Delay:
3539 11:19:57.128659 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =112
3540 11:19:57.131781 DQ4 =114, DQ5 =126, DQ6 =126, DQ7 =114
3541 11:19:57.134876 DQ8 =96, DQ9 =102, DQ10 =112, DQ11 =100
3542 11:19:57.138414 DQ12 =118, DQ13 =118, DQ14 =120, DQ15 =118
3543 11:19:57.138979
3544 11:19:57.139357
3545 11:19:57.148463 [DQSOSCAuto] RK0, (LSB)MR18= 0x4f7, (MSB)MR19= 0x403, tDQSOscB0 = 413 ps tDQSOscB1 = 408 ps
3546 11:19:57.149087 CH1 RK0: MR19=403, MR18=4F7
3547 11:19:57.154889 CH1_RK0: MR19=0x403, MR18=0x4F7, DQSOSC=408, MR23=63, INC=39, DEC=26
3548 11:19:57.155458
3549 11:19:57.158143 ----->DramcWriteLeveling(PI) begin...
3550 11:19:57.158652 ==
3551 11:19:57.161045 Dram Type= 6, Freq= 0, CH_1, rank 1
3552 11:19:57.168232 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3553 11:19:57.168907 ==
3554 11:19:57.171133 Write leveling (Byte 0): 24 => 24
3555 11:19:57.174216 Write leveling (Byte 1): 28 => 28
3556 11:19:57.174691 DramcWriteLeveling(PI) end<-----
3557 11:19:57.175065
3558 11:19:57.177864 ==
3559 11:19:57.181108 Dram Type= 6, Freq= 0, CH_1, rank 1
3560 11:19:57.184509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3561 11:19:57.185122 ==
3562 11:19:57.187904 [Gating] SW mode calibration
3563 11:19:57.194517 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3564 11:19:57.197794 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3565 11:19:57.204303 0 15 0 | B1->B0 | 3434 3232 | 0 0 | (0 0) (1 1)
3566 11:19:57.207826 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3567 11:19:57.211014 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3568 11:19:57.217660 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3569 11:19:57.220477 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3570 11:19:57.224324 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3571 11:19:57.230884 0 15 24 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 0)
3572 11:19:57.233447 0 15 28 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (1 0)
3573 11:19:57.237304 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3574 11:19:57.243377 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3575 11:19:57.246469 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3576 11:19:57.249802 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3577 11:19:57.256657 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3578 11:19:57.259880 1 0 20 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
3579 11:19:57.266526 1 0 24 | B1->B0 | 4242 2c2c | 0 0 | (0 0) (0 0)
3580 11:19:57.269874 1 0 28 | B1->B0 | 4646 4444 | 0 0 | (0 0) (0 0)
3581 11:19:57.272768 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3582 11:19:57.279360 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3583 11:19:57.282571 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3584 11:19:57.286243 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3585 11:19:57.292695 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3586 11:19:57.296046 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3587 11:19:57.299539 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3588 11:19:57.305975 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3589 11:19:57.309014 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3590 11:19:57.312766 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3591 11:19:57.319073 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3592 11:19:57.322727 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3593 11:19:57.325333 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3594 11:19:57.332298 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3595 11:19:57.335800 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3596 11:19:57.339168 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3597 11:19:57.345502 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3598 11:19:57.349406 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3599 11:19:57.352160 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3600 11:19:57.358548 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3601 11:19:57.362513 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3602 11:19:57.365608 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3603 11:19:57.369247 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3604 11:19:57.374960 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3605 11:19:57.378854 Total UI for P1: 0, mck2ui 16
3606 11:19:57.382196 best dqsien dly found for B1: ( 1, 3, 24)
3607 11:19:57.385209 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3608 11:19:57.388887 Total UI for P1: 0, mck2ui 16
3609 11:19:57.392002 best dqsien dly found for B0: ( 1, 3, 28)
3610 11:19:57.395229 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3611 11:19:57.398267 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3612 11:19:57.398837
3613 11:19:57.401855 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3614 11:19:57.408424 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3615 11:19:57.409107 [Gating] SW calibration Done
3616 11:19:57.409495 ==
3617 11:19:57.411788 Dram Type= 6, Freq= 0, CH_1, rank 1
3618 11:19:57.417902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3619 11:19:57.418495 ==
3620 11:19:57.419092 RX Vref Scan: 0
3621 11:19:57.419679
3622 11:19:57.421532 RX Vref 0 -> 0, step: 1
3623 11:19:57.422115
3624 11:19:57.424723 RX Delay -40 -> 252, step: 8
3625 11:19:57.428450 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3626 11:19:57.431597 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3627 11:19:57.435319 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3628 11:19:57.441300 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3629 11:19:57.444268 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3630 11:19:57.447827 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3631 11:19:57.451174 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3632 11:19:57.454567 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3633 11:19:57.460692 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3634 11:19:57.463728 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3635 11:19:57.467766 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3636 11:19:57.470796 iDelay=200, Bit 11, Center 99 (24 ~ 175) 152
3637 11:19:57.477257 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3638 11:19:57.480507 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3639 11:19:57.484130 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
3640 11:19:57.486847 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3641 11:19:57.487354 ==
3642 11:19:57.490239 Dram Type= 6, Freq= 0, CH_1, rank 1
3643 11:19:57.496934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3644 11:19:57.497492 ==
3645 11:19:57.497867 DQS Delay:
3646 11:19:57.498214 DQS0 = 0, DQS1 = 0
3647 11:19:57.500491 DQM Delay:
3648 11:19:57.501002 DQM0 = 116, DQM1 = 110
3649 11:19:57.503820 DQ Delay:
3650 11:19:57.507180 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3651 11:19:57.510314 DQ4 =115, DQ5 =127, DQ6 =127, DQ7 =115
3652 11:19:57.513396 DQ8 =95, DQ9 =103, DQ10 =111, DQ11 =99
3653 11:19:57.517138 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3654 11:19:57.517613
3655 11:19:57.517983
3656 11:19:57.518323 ==
3657 11:19:57.519848 Dram Type= 6, Freq= 0, CH_1, rank 1
3658 11:19:57.523374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3659 11:19:57.526871 ==
3660 11:19:57.527433
3661 11:19:57.527810
3662 11:19:57.528156 TX Vref Scan disable
3663 11:19:57.530318 == TX Byte 0 ==
3664 11:19:57.533103 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3665 11:19:57.536732 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3666 11:19:57.540033 == TX Byte 1 ==
3667 11:19:57.543379 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3668 11:19:57.546274 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3669 11:19:57.550247 ==
3670 11:19:57.553198 Dram Type= 6, Freq= 0, CH_1, rank 1
3671 11:19:57.556378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3672 11:19:57.556886 ==
3673 11:19:57.567607 TX Vref=22, minBit 9, minWin=25, winSum=426
3674 11:19:57.570953 TX Vref=24, minBit 9, minWin=25, winSum=428
3675 11:19:57.574354 TX Vref=26, minBit 9, minWin=26, winSum=431
3676 11:19:57.577803 TX Vref=28, minBit 10, minWin=26, winSum=436
3677 11:19:57.580656 TX Vref=30, minBit 10, minWin=26, winSum=436
3678 11:19:57.587501 TX Vref=32, minBit 8, minWin=26, winSum=434
3679 11:19:57.590377 [TxChooseVref] Worse bit 10, Min win 26, Win sum 436, Final Vref 28
3680 11:19:57.594100
3681 11:19:57.594567 Final TX Range 1 Vref 28
3682 11:19:57.594936
3683 11:19:57.595274 ==
3684 11:19:57.596946 Dram Type= 6, Freq= 0, CH_1, rank 1
3685 11:19:57.603712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3686 11:19:57.604186 ==
3687 11:19:57.604592
3688 11:19:57.604937
3689 11:19:57.605267 TX Vref Scan disable
3690 11:19:57.607340 == TX Byte 0 ==
3691 11:19:57.610956 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3692 11:19:57.617300 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3693 11:19:57.617769 == TX Byte 1 ==
3694 11:19:57.621103 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3695 11:19:57.627429 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3696 11:19:57.627953
3697 11:19:57.628369 [DATLAT]
3698 11:19:57.628834 Freq=1200, CH1 RK1
3699 11:19:57.629178
3700 11:19:57.630692 DATLAT Default: 0xd
3701 11:19:57.633835 0, 0xFFFF, sum = 0
3702 11:19:57.634308 1, 0xFFFF, sum = 0
3703 11:19:57.637086 2, 0xFFFF, sum = 0
3704 11:19:57.637515 3, 0xFFFF, sum = 0
3705 11:19:57.640227 4, 0xFFFF, sum = 0
3706 11:19:57.640691 5, 0xFFFF, sum = 0
3707 11:19:57.643843 6, 0xFFFF, sum = 0
3708 11:19:57.644284 7, 0xFFFF, sum = 0
3709 11:19:57.647008 8, 0xFFFF, sum = 0
3710 11:19:57.647541 9, 0xFFFF, sum = 0
3711 11:19:57.650100 10, 0xFFFF, sum = 0
3712 11:19:57.650534 11, 0xFFFF, sum = 0
3713 11:19:57.653477 12, 0x0, sum = 1
3714 11:19:57.653908 13, 0x0, sum = 2
3715 11:19:57.656932 14, 0x0, sum = 3
3716 11:19:57.657483 15, 0x0, sum = 4
3717 11:19:57.660276 best_step = 13
3718 11:19:57.660803
3719 11:19:57.661175 ==
3720 11:19:57.663577 Dram Type= 6, Freq= 0, CH_1, rank 1
3721 11:19:57.666639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3722 11:19:57.667120 ==
3723 11:19:57.670494 RX Vref Scan: 0
3724 11:19:57.671067
3725 11:19:57.671445 RX Vref 0 -> 0, step: 1
3726 11:19:57.671795
3727 11:19:57.673562 RX Delay -21 -> 252, step: 4
3728 11:19:57.680269 iDelay=199, Bit 0, Center 120 (55 ~ 186) 132
3729 11:19:57.683266 iDelay=199, Bit 1, Center 112 (47 ~ 178) 132
3730 11:19:57.686505 iDelay=199, Bit 2, Center 106 (43 ~ 170) 128
3731 11:19:57.689728 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3732 11:19:57.693727 iDelay=199, Bit 4, Center 114 (47 ~ 182) 136
3733 11:19:57.700029 iDelay=199, Bit 5, Center 128 (63 ~ 194) 132
3734 11:19:57.703347 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3735 11:19:57.706261 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3736 11:19:57.709840 iDelay=199, Bit 8, Center 98 (31 ~ 166) 136
3737 11:19:57.713427 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3738 11:19:57.719435 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3739 11:19:57.722862 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3740 11:19:57.726577 iDelay=199, Bit 12, Center 118 (51 ~ 186) 136
3741 11:19:57.729301 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3742 11:19:57.736215 iDelay=199, Bit 14, Center 118 (51 ~ 186) 136
3743 11:19:57.739591 iDelay=199, Bit 15, Center 118 (51 ~ 186) 136
3744 11:19:57.740365 ==
3745 11:19:57.742455 Dram Type= 6, Freq= 0, CH_1, rank 1
3746 11:19:57.745952 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3747 11:19:57.746685 ==
3748 11:19:57.749320 DQS Delay:
3749 11:19:57.749931 DQS0 = 0, DQS1 = 0
3750 11:19:57.750489 DQM Delay:
3751 11:19:57.752703 DQM0 = 117, DQM1 = 110
3752 11:19:57.753249 DQ Delay:
3753 11:19:57.755833 DQ0 =120, DQ1 =112, DQ2 =106, DQ3 =112
3754 11:19:57.758913 DQ4 =114, DQ5 =128, DQ6 =130, DQ7 =116
3755 11:19:57.762322 DQ8 =98, DQ9 =100, DQ10 =110, DQ11 =100
3756 11:19:57.768853 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =118
3757 11:19:57.769391
3758 11:19:57.769760
3759 11:19:57.776035 [DQSOSCAuto] RK1, (LSB)MR18= 0xf3ef, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 415 ps
3760 11:19:57.778955 CH1 RK1: MR19=303, MR18=F3EF
3761 11:19:57.785333 CH1_RK1: MR19=0x303, MR18=0xF3EF, DQSOSC=415, MR23=63, INC=38, DEC=25
3762 11:19:57.789153 [RxdqsGatingPostProcess] freq 1200
3763 11:19:57.792056 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3764 11:19:57.795137 best DQS0 dly(2T, 0.5T) = (0, 11)
3765 11:19:57.799172 best DQS1 dly(2T, 0.5T) = (0, 11)
3766 11:19:57.802056 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3767 11:19:57.805057 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3768 11:19:57.808461 best DQS0 dly(2T, 0.5T) = (0, 11)
3769 11:19:57.812119 best DQS1 dly(2T, 0.5T) = (0, 11)
3770 11:19:57.814995 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3771 11:19:57.818109 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3772 11:19:57.821367 Pre-setting of DQS Precalculation
3773 11:19:57.828130 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3774 11:19:57.835279 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3775 11:19:57.841436 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3776 11:19:57.841909
3777 11:19:57.842278
3778 11:19:57.844742 [Calibration Summary] 2400 Mbps
3779 11:19:57.845236 CH 0, Rank 0
3780 11:19:57.848021 SW Impedance : PASS
3781 11:19:57.850916 DUTY Scan : NO K
3782 11:19:57.851391 ZQ Calibration : PASS
3783 11:19:57.854508 Jitter Meter : NO K
3784 11:19:57.857745 CBT Training : PASS
3785 11:19:57.858316 Write leveling : PASS
3786 11:19:57.860908 RX DQS gating : PASS
3787 11:19:57.864347 RX DQ/DQS(RDDQC) : PASS
3788 11:19:57.864896 TX DQ/DQS : PASS
3789 11:19:57.867524 RX DATLAT : PASS
3790 11:19:57.870580 RX DQ/DQS(Engine): PASS
3791 11:19:57.871079 TX OE : NO K
3792 11:19:57.871462 All Pass.
3793 11:19:57.874006
3794 11:19:57.874476 CH 0, Rank 1
3795 11:19:57.877399 SW Impedance : PASS
3796 11:19:57.877975 DUTY Scan : NO K
3797 11:19:57.880744 ZQ Calibration : PASS
3798 11:19:57.881216 Jitter Meter : NO K
3799 11:19:57.884383 CBT Training : PASS
3800 11:19:57.887471 Write leveling : PASS
3801 11:19:57.888049 RX DQS gating : PASS
3802 11:19:57.890601 RX DQ/DQS(RDDQC) : PASS
3803 11:19:57.893992 TX DQ/DQS : PASS
3804 11:19:57.894508 RX DATLAT : PASS
3805 11:19:57.897451 RX DQ/DQS(Engine): PASS
3806 11:19:57.900332 TX OE : NO K
3807 11:19:57.900914 All Pass.
3808 11:19:57.901399
3809 11:19:57.901767 CH 1, Rank 0
3810 11:19:57.903644 SW Impedance : PASS
3811 11:19:57.907071 DUTY Scan : NO K
3812 11:19:57.907540 ZQ Calibration : PASS
3813 11:19:57.910551 Jitter Meter : NO K
3814 11:19:57.913724 CBT Training : PASS
3815 11:19:57.914151 Write leveling : PASS
3816 11:19:57.916821 RX DQS gating : PASS
3817 11:19:57.920879 RX DQ/DQS(RDDQC) : PASS
3818 11:19:57.921335 TX DQ/DQS : PASS
3819 11:19:57.924295 RX DATLAT : PASS
3820 11:19:57.927081 RX DQ/DQS(Engine): PASS
3821 11:19:57.927531 TX OE : NO K
3822 11:19:57.930523 All Pass.
3823 11:19:57.931071
3824 11:19:57.931409 CH 1, Rank 1
3825 11:19:57.933435 SW Impedance : PASS
3826 11:19:57.933905 DUTY Scan : NO K
3827 11:19:57.936989 ZQ Calibration : PASS
3828 11:19:57.940007 Jitter Meter : NO K
3829 11:19:57.940476 CBT Training : PASS
3830 11:19:57.943236 Write leveling : PASS
3831 11:19:57.947172 RX DQS gating : PASS
3832 11:19:57.947698 RX DQ/DQS(RDDQC) : PASS
3833 11:19:57.950510 TX DQ/DQS : PASS
3834 11:19:57.950982 RX DATLAT : PASS
3835 11:19:57.953802 RX DQ/DQS(Engine): PASS
3836 11:19:57.956714 TX OE : NO K
3837 11:19:57.957172 All Pass.
3838 11:19:57.957510
3839 11:19:57.959980 DramC Write-DBI off
3840 11:19:57.960407 PER_BANK_REFRESH: Hybrid Mode
3841 11:19:57.963166 TX_TRACKING: ON
3842 11:19:57.973130 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3843 11:19:57.976420 [FAST_K] Save calibration result to emmc
3844 11:19:57.979618 dramc_set_vcore_voltage set vcore to 650000
3845 11:19:57.982798 Read voltage for 600, 5
3846 11:19:57.983270 Vio18 = 0
3847 11:19:57.983644 Vcore = 650000
3848 11:19:57.986319 Vdram = 0
3849 11:19:57.986785 Vddq = 0
3850 11:19:57.987155 Vmddr = 0
3851 11:19:57.992963 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3852 11:19:57.996408 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3853 11:19:57.999471 MEM_TYPE=3, freq_sel=19
3854 11:19:58.003236 sv_algorithm_assistance_LP4_1600
3855 11:19:58.006641 ============ PULL DRAM RESETB DOWN ============
3856 11:19:58.009515 ========== PULL DRAM RESETB DOWN end =========
3857 11:19:58.016078 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3858 11:19:58.018999 ===================================
3859 11:19:58.019491 LPDDR4 DRAM CONFIGURATION
3860 11:19:58.023124 ===================================
3861 11:19:58.025957 EX_ROW_EN[0] = 0x0
3862 11:19:58.029029 EX_ROW_EN[1] = 0x0
3863 11:19:58.029505 LP4Y_EN = 0x0
3864 11:19:58.032265 WORK_FSP = 0x0
3865 11:19:58.032881 WL = 0x2
3866 11:19:58.035575 RL = 0x2
3867 11:19:58.036061 BL = 0x2
3868 11:19:58.039131 RPST = 0x0
3869 11:19:58.039680 RD_PRE = 0x0
3870 11:19:58.042307 WR_PRE = 0x1
3871 11:19:58.042772 WR_PST = 0x0
3872 11:19:58.045940 DBI_WR = 0x0
3873 11:19:58.046515 DBI_RD = 0x0
3874 11:19:58.048942 OTF = 0x1
3875 11:19:58.052169 ===================================
3876 11:19:58.055604 ===================================
3877 11:19:58.056173 ANA top config
3878 11:19:58.059231 ===================================
3879 11:19:58.062028 DLL_ASYNC_EN = 0
3880 11:19:58.065317 ALL_SLAVE_EN = 1
3881 11:19:58.068609 NEW_RANK_MODE = 1
3882 11:19:58.069127 DLL_IDLE_MODE = 1
3883 11:19:58.072253 LP45_APHY_COMB_EN = 1
3884 11:19:58.075045 TX_ODT_DIS = 1
3885 11:19:58.078865 NEW_8X_MODE = 1
3886 11:19:58.081728 ===================================
3887 11:19:58.085160 ===================================
3888 11:19:58.088697 data_rate = 1200
3889 11:19:58.091938 CKR = 1
3890 11:19:58.092418 DQ_P2S_RATIO = 8
3891 11:19:58.095448 ===================================
3892 11:19:58.098135 CA_P2S_RATIO = 8
3893 11:19:58.101675 DQ_CA_OPEN = 0
3894 11:19:58.105066 DQ_SEMI_OPEN = 0
3895 11:19:58.108476 CA_SEMI_OPEN = 0
3896 11:19:58.111568 CA_FULL_RATE = 0
3897 11:19:58.112039 DQ_CKDIV4_EN = 1
3898 11:19:58.114616 CA_CKDIV4_EN = 1
3899 11:19:58.117953 CA_PREDIV_EN = 0
3900 11:19:58.121672 PH8_DLY = 0
3901 11:19:58.124594 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3902 11:19:58.127987 DQ_AAMCK_DIV = 4
3903 11:19:58.128660 CA_AAMCK_DIV = 4
3904 11:19:58.131458 CA_ADMCK_DIV = 4
3905 11:19:58.135034 DQ_TRACK_CA_EN = 0
3906 11:19:58.138321 CA_PICK = 600
3907 11:19:58.141288 CA_MCKIO = 600
3908 11:19:58.144848 MCKIO_SEMI = 0
3909 11:19:58.148155 PLL_FREQ = 2288
3910 11:19:58.151746 DQ_UI_PI_RATIO = 32
3911 11:19:58.152317 CA_UI_PI_RATIO = 0
3912 11:19:58.154684 ===================================
3913 11:19:58.157574 ===================================
3914 11:19:58.161321 memory_type:LPDDR4
3915 11:19:58.164500 GP_NUM : 10
3916 11:19:58.165017 SRAM_EN : 1
3917 11:19:58.167210 MD32_EN : 0
3918 11:19:58.170691 ===================================
3919 11:19:58.174441 [ANA_INIT] >>>>>>>>>>>>>>
3920 11:19:58.177190 <<<<<< [CONFIGURE PHASE]: ANA_TX
3921 11:19:58.180790 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3922 11:19:58.183911 ===================================
3923 11:19:58.184382 data_rate = 1200,PCW = 0X5800
3924 11:19:58.187797 ===================================
3925 11:19:58.190796 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3926 11:19:58.197106 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3927 11:19:58.203912 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3928 11:19:58.207530 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3929 11:19:58.210445 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3930 11:19:58.214060 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3931 11:19:58.216744 [ANA_INIT] flow start
3932 11:19:58.220483 [ANA_INIT] PLL >>>>>>>>
3933 11:19:58.220988 [ANA_INIT] PLL <<<<<<<<
3934 11:19:58.223501 [ANA_INIT] MIDPI >>>>>>>>
3935 11:19:58.227289 [ANA_INIT] MIDPI <<<<<<<<
3936 11:19:58.227837 [ANA_INIT] DLL >>>>>>>>
3937 11:19:58.230418 [ANA_INIT] flow end
3938 11:19:58.233169 ============ LP4 DIFF to SE enter ============
3939 11:19:58.236943 ============ LP4 DIFF to SE exit ============
3940 11:19:58.239750 [ANA_INIT] <<<<<<<<<<<<<
3941 11:19:58.243324 [Flow] Enable top DCM control >>>>>
3942 11:19:58.246706 [Flow] Enable top DCM control <<<<<
3943 11:19:58.249643 Enable DLL master slave shuffle
3944 11:19:58.256893 ==============================================================
3945 11:19:58.257474 Gating Mode config
3946 11:19:58.263446 ==============================================================
3947 11:19:58.266225 Config description:
3948 11:19:58.273383 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3949 11:19:58.279739 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3950 11:19:58.286377 SELPH_MODE 0: By rank 1: By Phase
3951 11:19:58.292857 ==============================================================
3952 11:19:58.295857 GAT_TRACK_EN = 1
3953 11:19:58.296331 RX_GATING_MODE = 2
3954 11:19:58.299419 RX_GATING_TRACK_MODE = 2
3955 11:19:58.302518 SELPH_MODE = 1
3956 11:19:58.306171 PICG_EARLY_EN = 1
3957 11:19:58.309211 VALID_LAT_VALUE = 1
3958 11:19:58.316024 ==============================================================
3959 11:19:58.319160 Enter into Gating configuration >>>>
3960 11:19:58.322395 Exit from Gating configuration <<<<
3961 11:19:58.326222 Enter into DVFS_PRE_config >>>>>
3962 11:19:58.335696 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3963 11:19:58.339253 Exit from DVFS_PRE_config <<<<<
3964 11:19:58.342275 Enter into PICG configuration >>>>
3965 11:19:58.346099 Exit from PICG configuration <<<<
3966 11:19:58.348952 [RX_INPUT] configuration >>>>>
3967 11:19:58.352104 [RX_INPUT] configuration <<<<<
3968 11:19:58.355834 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3969 11:19:58.362188 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3970 11:19:58.368476 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3971 11:19:58.375667 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3972 11:19:58.378295 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3973 11:19:58.385300 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3974 11:19:58.392050 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3975 11:19:58.395022 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3976 11:19:58.398486 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3977 11:19:58.401537 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3978 11:19:58.408419 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3979 11:19:58.411482 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3980 11:19:58.415055 ===================================
3981 11:19:58.418011 LPDDR4 DRAM CONFIGURATION
3982 11:19:58.421335 ===================================
3983 11:19:58.421876 EX_ROW_EN[0] = 0x0
3984 11:19:58.424419 EX_ROW_EN[1] = 0x0
3985 11:19:58.424985 LP4Y_EN = 0x0
3986 11:19:58.427961 WORK_FSP = 0x0
3987 11:19:58.428624 WL = 0x2
3988 11:19:58.431224 RL = 0x2
3989 11:19:58.431693 BL = 0x2
3990 11:19:58.434546 RPST = 0x0
3991 11:19:58.435180 RD_PRE = 0x0
3992 11:19:58.437696 WR_PRE = 0x1
3993 11:19:58.438181 WR_PST = 0x0
3994 11:19:58.441429 DBI_WR = 0x0
3995 11:19:58.444589 DBI_RD = 0x0
3996 11:19:58.445009 OTF = 0x1
3997 11:19:58.447940 ===================================
3998 11:19:58.451554 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3999 11:19:58.454012 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4000 11:19:58.461200 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
4001 11:19:58.464215 ===================================
4002 11:19:58.467466 LPDDR4 DRAM CONFIGURATION
4003 11:19:58.470579 ===================================
4004 11:19:58.471103 EX_ROW_EN[0] = 0x10
4005 11:19:58.474705 EX_ROW_EN[1] = 0x0
4006 11:19:58.475221 LP4Y_EN = 0x0
4007 11:19:58.477565 WORK_FSP = 0x0
4008 11:19:58.477989 WL = 0x2
4009 11:19:58.480347 RL = 0x2
4010 11:19:58.480860 BL = 0x2
4011 11:19:58.484604 RPST = 0x0
4012 11:19:58.485027 RD_PRE = 0x0
4013 11:19:58.486964 WR_PRE = 0x1
4014 11:19:58.491194 WR_PST = 0x0
4015 11:19:58.491653 DBI_WR = 0x0
4016 11:19:58.494172 DBI_RD = 0x0
4017 11:19:58.494709 OTF = 0x1
4018 11:19:58.497168 ===================================
4019 11:19:58.504042 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4020 11:19:58.507458 nWR fixed to 30
4021 11:19:58.511121 [ModeRegInit_LP4] CH0 RK0
4022 11:19:58.511578 [ModeRegInit_LP4] CH0 RK1
4023 11:19:58.514177 [ModeRegInit_LP4] CH1 RK0
4024 11:19:58.517299 [ModeRegInit_LP4] CH1 RK1
4025 11:19:58.517720 match AC timing 17
4026 11:19:58.523904 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
4027 11:19:58.527618 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4028 11:19:58.530632 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
4029 11:19:58.537174 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
4030 11:19:58.540662 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
4031 11:19:58.541095 ==
4032 11:19:58.544253 Dram Type= 6, Freq= 0, CH_0, rank 0
4033 11:19:58.547402 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4034 11:19:58.547834 ==
4035 11:19:58.553696 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4036 11:19:58.560354 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4037 11:19:58.563106 [CA 0] Center 36 (6~66) winsize 61
4038 11:19:58.566562 [CA 1] Center 36 (6~66) winsize 61
4039 11:19:58.569755 [CA 2] Center 34 (4~65) winsize 62
4040 11:19:58.573712 [CA 3] Center 34 (3~65) winsize 63
4041 11:19:58.576613 [CA 4] Center 33 (3~64) winsize 62
4042 11:19:58.580367 [CA 5] Center 33 (3~64) winsize 62
4043 11:19:58.580969
4044 11:19:58.583458 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4045 11:19:58.584061
4046 11:19:58.586682 [CATrainingPosCal] consider 1 rank data
4047 11:19:58.589844 u2DelayCellTimex100 = 270/100 ps
4048 11:19:58.593143 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4049 11:19:58.596581 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4050 11:19:58.600016 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4051 11:19:58.606109 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4052 11:19:58.609805 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4053 11:19:58.613185 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4054 11:19:58.613662
4055 11:19:58.616281 CA PerBit enable=1, Macro0, CA PI delay=33
4056 11:19:58.616800
4057 11:19:58.619206 [CBTSetCACLKResult] CA Dly = 33
4058 11:19:58.619678 CS Dly: 6 (0~37)
4059 11:19:58.620060 ==
4060 11:19:58.622816 Dram Type= 6, Freq= 0, CH_0, rank 1
4061 11:19:58.629233 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4062 11:19:58.629669 ==
4063 11:19:58.632508 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4064 11:19:58.639480 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4065 11:19:58.643261 [CA 0] Center 35 (5~66) winsize 62
4066 11:19:58.646031 [CA 1] Center 36 (6~66) winsize 61
4067 11:19:58.649641 [CA 2] Center 34 (3~65) winsize 63
4068 11:19:58.652474 [CA 3] Center 33 (3~64) winsize 62
4069 11:19:58.655839 [CA 4] Center 33 (3~64) winsize 62
4070 11:19:58.659099 [CA 5] Center 33 (2~64) winsize 63
4071 11:19:58.659600
4072 11:19:58.662609 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4073 11:19:58.663083
4074 11:19:58.666473 [CATrainingPosCal] consider 2 rank data
4075 11:19:58.669342 u2DelayCellTimex100 = 270/100 ps
4076 11:19:58.672688 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4077 11:19:58.679147 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4078 11:19:58.682726 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4079 11:19:58.686001 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4080 11:19:58.688772 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4081 11:19:58.692310 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4082 11:19:58.692918
4083 11:19:58.695352 CA PerBit enable=1, Macro0, CA PI delay=33
4084 11:19:58.695827
4085 11:19:58.699056 [CBTSetCACLKResult] CA Dly = 33
4086 11:19:58.702278 CS Dly: 6 (0~37)
4087 11:19:58.702750
4088 11:19:58.705880 ----->DramcWriteLeveling(PI) begin...
4089 11:19:58.706366 ==
4090 11:19:58.708975 Dram Type= 6, Freq= 0, CH_0, rank 0
4091 11:19:58.712439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4092 11:19:58.713041 ==
4093 11:19:58.715590 Write leveling (Byte 0): 32 => 32
4094 11:19:58.718484 Write leveling (Byte 1): 30 => 30
4095 11:19:58.722025 DramcWriteLeveling(PI) end<-----
4096 11:19:58.722540
4097 11:19:58.722915 ==
4098 11:19:58.725542 Dram Type= 6, Freq= 0, CH_0, rank 0
4099 11:19:58.728471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4100 11:19:58.728993 ==
4101 11:19:58.731865 [Gating] SW mode calibration
4102 11:19:58.738473 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4103 11:19:58.745122 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4104 11:19:58.748212 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4105 11:19:58.751500 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4106 11:19:58.758319 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4107 11:19:58.761566 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4108 11:19:58.764759 0 9 16 | B1->B0 | 3232 2626 | 1 0 | (1 0) (0 0)
4109 11:19:58.771438 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4110 11:19:58.774904 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4111 11:19:58.778124 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4112 11:19:58.784420 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4113 11:19:58.787962 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4114 11:19:58.791129 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4115 11:19:58.798479 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4116 11:19:58.801174 0 10 16 | B1->B0 | 3737 4545 | 0 0 | (0 0) (0 0)
4117 11:19:58.804407 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4118 11:19:58.811206 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4119 11:19:58.814412 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4120 11:19:58.818354 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4121 11:19:58.824637 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4122 11:19:58.827635 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4123 11:19:58.831869 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4124 11:19:58.837933 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4125 11:19:58.841098 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4126 11:19:58.844022 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4127 11:19:58.851133 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4128 11:19:58.854125 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4129 11:19:58.857909 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4130 11:19:58.863899 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4131 11:19:58.868022 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4132 11:19:58.870486 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4133 11:19:58.877092 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4134 11:19:58.881176 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4135 11:19:58.883925 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4136 11:19:58.890321 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4137 11:19:58.893648 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4138 11:19:58.896831 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4139 11:19:58.904026 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4140 11:19:58.907375 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4141 11:19:58.910658 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4142 11:19:58.913557 Total UI for P1: 0, mck2ui 16
4143 11:19:58.917150 best dqsien dly found for B0: ( 0, 13, 14)
4144 11:19:58.920204 Total UI for P1: 0, mck2ui 16
4145 11:19:58.923163 best dqsien dly found for B1: ( 0, 13, 16)
4146 11:19:58.926954 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4147 11:19:58.930555 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4148 11:19:58.931031
4149 11:19:58.936354 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4150 11:19:58.939935 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4151 11:19:58.943477 [Gating] SW calibration Done
4152 11:19:58.944024 ==
4153 11:19:58.946784 Dram Type= 6, Freq= 0, CH_0, rank 0
4154 11:19:58.950079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4155 11:19:58.950553 ==
4156 11:19:58.950930 RX Vref Scan: 0
4157 11:19:58.951278
4158 11:19:58.953583 RX Vref 0 -> 0, step: 1
4159 11:19:58.954054
4160 11:19:58.957018 RX Delay -230 -> 252, step: 16
4161 11:19:58.959692 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4162 11:19:58.963430 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4163 11:19:58.969681 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4164 11:19:58.973349 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4165 11:19:58.976620 iDelay=218, Bit 4, Center 49 (-118 ~ 217) 336
4166 11:19:58.979607 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4167 11:19:58.986102 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4168 11:19:58.989391 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4169 11:19:58.993115 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4170 11:19:58.995978 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4171 11:19:59.002743 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4172 11:19:59.006078 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4173 11:19:59.009458 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4174 11:19:59.012434 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4175 11:19:59.019368 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4176 11:19:59.022673 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4177 11:19:59.023153 ==
4178 11:19:59.026184 Dram Type= 6, Freq= 0, CH_0, rank 0
4179 11:19:59.029199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4180 11:19:59.029677 ==
4181 11:19:59.033564 DQS Delay:
4182 11:19:59.034034 DQS0 = 0, DQS1 = 0
4183 11:19:59.034405 DQM Delay:
4184 11:19:59.035452 DQM0 = 42, DQM1 = 30
4185 11:19:59.035922 DQ Delay:
4186 11:19:59.038856 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4187 11:19:59.042629 DQ4 =49, DQ5 =33, DQ6 =49, DQ7 =49
4188 11:19:59.046330 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4189 11:19:59.048951 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4190 11:19:59.049421
4191 11:19:59.049789
4192 11:19:59.050128 ==
4193 11:19:59.052431 Dram Type= 6, Freq= 0, CH_0, rank 0
4194 11:19:59.059174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4195 11:19:59.059650 ==
4196 11:19:59.060020
4197 11:19:59.060362
4198 11:19:59.060750 TX Vref Scan disable
4199 11:19:59.062498 == TX Byte 0 ==
4200 11:19:59.066228 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4201 11:19:59.072764 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4202 11:19:59.073334 == TX Byte 1 ==
4203 11:19:59.076292 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4204 11:19:59.082591 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4205 11:19:59.083148 ==
4206 11:19:59.085321 Dram Type= 6, Freq= 0, CH_0, rank 0
4207 11:19:59.088631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4208 11:19:59.089170 ==
4209 11:19:59.089542
4210 11:19:59.089885
4211 11:19:59.092018 TX Vref Scan disable
4212 11:19:59.095685 == TX Byte 0 ==
4213 11:19:59.098710 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4214 11:19:59.101831 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4215 11:19:59.104882 == TX Byte 1 ==
4216 11:19:59.108307 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4217 11:19:59.112270 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4218 11:19:59.112891
4219 11:19:59.115085 [DATLAT]
4220 11:19:59.115683 Freq=600, CH0 RK0
4221 11:19:59.116063
4222 11:19:59.118359 DATLAT Default: 0x9
4223 11:19:59.118822 0, 0xFFFF, sum = 0
4224 11:19:59.121566 1, 0xFFFF, sum = 0
4225 11:19:59.122073 2, 0xFFFF, sum = 0
4226 11:19:59.125511 3, 0xFFFF, sum = 0
4227 11:19:59.125997 4, 0xFFFF, sum = 0
4228 11:19:59.127959 5, 0xFFFF, sum = 0
4229 11:19:59.128453 6, 0xFFFF, sum = 0
4230 11:19:59.131504 7, 0xFFFF, sum = 0
4231 11:19:59.131990 8, 0x0, sum = 1
4232 11:19:59.135044 9, 0x0, sum = 2
4233 11:19:59.135582 10, 0x0, sum = 3
4234 11:19:59.138245 11, 0x0, sum = 4
4235 11:19:59.138779 best_step = 9
4236 11:19:59.139119
4237 11:19:59.139426 ==
4238 11:19:59.141464 Dram Type= 6, Freq= 0, CH_0, rank 0
4239 11:19:59.144223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4240 11:19:59.147972 ==
4241 11:19:59.148564 RX Vref Scan: 1
4242 11:19:59.148935
4243 11:19:59.151195 RX Vref 0 -> 0, step: 1
4244 11:19:59.151766
4245 11:19:59.154344 RX Delay -195 -> 252, step: 8
4246 11:19:59.154777
4247 11:19:59.157548 Set Vref, RX VrefLevel [Byte0]: 60
4248 11:19:59.161161 [Byte1]: 49
4249 11:19:59.161593
4250 11:19:59.164410 Final RX Vref Byte 0 = 60 to rank0
4251 11:19:59.168004 Final RX Vref Byte 1 = 49 to rank0
4252 11:19:59.170571 Final RX Vref Byte 0 = 60 to rank1
4253 11:19:59.174268 Final RX Vref Byte 1 = 49 to rank1==
4254 11:19:59.177128 Dram Type= 6, Freq= 0, CH_0, rank 0
4255 11:19:59.180887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4256 11:19:59.181360 ==
4257 11:19:59.184281 DQS Delay:
4258 11:19:59.184776 DQS0 = 0, DQS1 = 0
4259 11:19:59.185147 DQM Delay:
4260 11:19:59.187445 DQM0 = 43, DQM1 = 32
4261 11:19:59.187912 DQ Delay:
4262 11:19:59.190440 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4263 11:19:59.193854 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =52
4264 11:19:59.198164 DQ8 =24, DQ9 =20, DQ10 =32, DQ11 =24
4265 11:19:59.200833 DQ12 =36, DQ13 =36, DQ14 =44, DQ15 =40
4266 11:19:59.201376
4267 11:19:59.201722
4268 11:19:59.210331 [DQSOSCAuto] RK0, (LSB)MR18= 0x633a, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 391 ps
4269 11:19:59.213386 CH0 RK0: MR19=808, MR18=633A
4270 11:19:59.220252 CH0_RK0: MR19=0x808, MR18=0x633A, DQSOSC=391, MR23=63, INC=171, DEC=114
4271 11:19:59.220844
4272 11:19:59.223299 ----->DramcWriteLeveling(PI) begin...
4273 11:19:59.223807 ==
4274 11:19:59.226820 Dram Type= 6, Freq= 0, CH_0, rank 1
4275 11:19:59.229928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4276 11:19:59.230413 ==
4277 11:19:59.233421 Write leveling (Byte 0): 34 => 34
4278 11:19:59.236490 Write leveling (Byte 1): 33 => 33
4279 11:19:59.239740 DramcWriteLeveling(PI) end<-----
4280 11:19:59.240216
4281 11:19:59.240633 ==
4282 11:19:59.243596 Dram Type= 6, Freq= 0, CH_0, rank 1
4283 11:19:59.246863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4284 11:19:59.247478 ==
4285 11:19:59.249624 [Gating] SW mode calibration
4286 11:19:59.256149 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4287 11:19:59.263147 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4288 11:19:59.266416 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4289 11:19:59.269501 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4290 11:19:59.276406 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4291 11:19:59.279470 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4292 11:19:59.282539 0 9 16 | B1->B0 | 2a2a 2626 | 0 0 | (1 1) (1 1)
4293 11:19:59.289302 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4294 11:19:59.292642 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4295 11:19:59.295989 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4296 11:19:59.302779 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4297 11:19:59.305811 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4298 11:19:59.309419 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4299 11:19:59.315952 0 10 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (1 1)
4300 11:19:59.319421 0 10 16 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
4301 11:19:59.322212 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4302 11:19:59.329198 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4303 11:19:59.331900 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4304 11:19:59.335346 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4305 11:19:59.342208 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4306 11:19:59.345253 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4307 11:19:59.348932 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4308 11:19:59.355547 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4309 11:19:59.358814 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4310 11:19:59.362219 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4311 11:19:59.369502 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4312 11:19:59.371586 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4313 11:19:59.375072 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4314 11:19:59.381715 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4315 11:19:59.385184 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4316 11:19:59.388493 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4317 11:19:59.395208 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4318 11:19:59.398295 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4319 11:19:59.401511 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4320 11:19:59.407852 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4321 11:19:59.411611 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4322 11:19:59.415015 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4323 11:19:59.421625 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4324 11:19:59.424447 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4325 11:19:59.427812 Total UI for P1: 0, mck2ui 16
4326 11:19:59.431069 best dqsien dly found for B0: ( 0, 13, 12)
4327 11:19:59.434410 Total UI for P1: 0, mck2ui 16
4328 11:19:59.437509 best dqsien dly found for B1: ( 0, 13, 12)
4329 11:19:59.440951 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4330 11:19:59.444335 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4331 11:19:59.444883
4332 11:19:59.447500 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4333 11:19:59.450768 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4334 11:19:59.454132 [Gating] SW calibration Done
4335 11:19:59.454567 ==
4336 11:19:59.458007 Dram Type= 6, Freq= 0, CH_0, rank 1
4337 11:19:59.464120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4338 11:19:59.464739 ==
4339 11:19:59.465230 RX Vref Scan: 0
4340 11:19:59.465690
4341 11:19:59.467305 RX Vref 0 -> 0, step: 1
4342 11:19:59.467790
4343 11:19:59.471101 RX Delay -230 -> 252, step: 16
4344 11:19:59.473775 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4345 11:19:59.477795 iDelay=218, Bit 1, Center 49 (-118 ~ 217) 336
4346 11:19:59.480865 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4347 11:19:59.487077 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4348 11:19:59.490626 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4349 11:19:59.493984 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4350 11:19:59.497219 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4351 11:19:59.503792 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4352 11:19:59.507243 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4353 11:19:59.510637 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4354 11:19:59.513535 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4355 11:19:59.520416 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4356 11:19:59.523673 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4357 11:19:59.526542 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4358 11:19:59.530506 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4359 11:19:59.536387 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4360 11:19:59.536903 ==
4361 11:19:59.540381 Dram Type= 6, Freq= 0, CH_0, rank 1
4362 11:19:59.543030 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4363 11:19:59.543492 ==
4364 11:19:59.543856 DQS Delay:
4365 11:19:59.546641 DQS0 = 0, DQS1 = 0
4366 11:19:59.547097 DQM Delay:
4367 11:19:59.549799 DQM0 = 41, DQM1 = 34
4368 11:19:59.550215 DQ Delay:
4369 11:19:59.553214 DQ0 =41, DQ1 =49, DQ2 =33, DQ3 =33
4370 11:19:59.556179 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4371 11:19:59.560197 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4372 11:19:59.563018 DQ12 =33, DQ13 =49, DQ14 =49, DQ15 =33
4373 11:19:59.563410
4374 11:19:59.563650
4375 11:19:59.563866 ==
4376 11:19:59.566444 Dram Type= 6, Freq= 0, CH_0, rank 1
4377 11:19:59.569320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4378 11:19:59.569617 ==
4379 11:19:59.573970
4380 11:19:59.574355
4381 11:19:59.574628 TX Vref Scan disable
4382 11:19:59.576176 == TX Byte 0 ==
4383 11:19:59.579328 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4384 11:19:59.582633 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4385 11:19:59.585910 == TX Byte 1 ==
4386 11:19:59.590514 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4387 11:19:59.592716 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4388 11:19:59.596133 ==
4389 11:19:59.599250 Dram Type= 6, Freq= 0, CH_0, rank 1
4390 11:19:59.602382 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4391 11:19:59.602804 ==
4392 11:19:59.603135
4393 11:19:59.603438
4394 11:19:59.605665 TX Vref Scan disable
4395 11:19:59.606078 == TX Byte 0 ==
4396 11:19:59.612862 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4397 11:19:59.615846 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4398 11:19:59.619549 == TX Byte 1 ==
4399 11:19:59.622864 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4400 11:19:59.625839 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4401 11:19:59.626469
4402 11:19:59.627077 [DATLAT]
4403 11:19:59.629860 Freq=600, CH0 RK1
4404 11:19:59.630418
4405 11:19:59.630781 DATLAT Default: 0x9
4406 11:19:59.633021 0, 0xFFFF, sum = 0
4407 11:19:59.636169 1, 0xFFFF, sum = 0
4408 11:19:59.636771 2, 0xFFFF, sum = 0
4409 11:19:59.638890 3, 0xFFFF, sum = 0
4410 11:19:59.639378 4, 0xFFFF, sum = 0
4411 11:19:59.642034 5, 0xFFFF, sum = 0
4412 11:19:59.642503 6, 0xFFFF, sum = 0
4413 11:19:59.645547 7, 0xFFFF, sum = 0
4414 11:19:59.646014 8, 0x0, sum = 1
4415 11:19:59.648779 9, 0x0, sum = 2
4416 11:19:59.649269 10, 0x0, sum = 3
4417 11:19:59.649642 11, 0x0, sum = 4
4418 11:19:59.652093 best_step = 9
4419 11:19:59.652692
4420 11:19:59.653101 ==
4421 11:19:59.655749 Dram Type= 6, Freq= 0, CH_0, rank 1
4422 11:19:59.658808 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4423 11:19:59.659271 ==
4424 11:19:59.662261 RX Vref Scan: 0
4425 11:19:59.662675
4426 11:19:59.663003 RX Vref 0 -> 0, step: 1
4427 11:19:59.665576
4428 11:19:59.665989 RX Delay -179 -> 252, step: 8
4429 11:19:59.673356 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4430 11:19:59.676475 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4431 11:19:59.679720 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4432 11:19:59.683522 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4433 11:19:59.689770 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4434 11:19:59.693001 iDelay=205, Bit 5, Center 36 (-115 ~ 188) 304
4435 11:19:59.696274 iDelay=205, Bit 6, Center 52 (-99 ~ 204) 304
4436 11:19:59.699289 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4437 11:19:59.702729 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4438 11:19:59.709736 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4439 11:19:59.713399 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4440 11:19:59.716048 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4441 11:19:59.719610 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4442 11:19:59.726298 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4443 11:19:59.729468 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4444 11:19:59.732336 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4445 11:19:59.732835 ==
4446 11:19:59.736196 Dram Type= 6, Freq= 0, CH_0, rank 1
4447 11:19:59.739539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4448 11:19:59.742739 ==
4449 11:19:59.743292 DQS Delay:
4450 11:19:59.743653 DQS0 = 0, DQS1 = 0
4451 11:19:59.745950 DQM Delay:
4452 11:19:59.746491 DQM0 = 42, DQM1 = 37
4453 11:19:59.749386 DQ Delay:
4454 11:19:59.752512 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4455 11:19:59.753149 DQ4 =44, DQ5 =36, DQ6 =52, DQ7 =48
4456 11:19:59.755768 DQ8 =28, DQ9 =20, DQ10 =40, DQ11 =28
4457 11:19:59.759239 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =44
4458 11:19:59.762379
4459 11:19:59.762925
4460 11:19:59.769063 [DQSOSCAuto] RK1, (LSB)MR18= 0x5d11, (MSB)MR19= 0x808, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
4461 11:19:59.772856 CH0 RK1: MR19=808, MR18=5D11
4462 11:19:59.779359 CH0_RK1: MR19=0x808, MR18=0x5D11, DQSOSC=392, MR23=63, INC=170, DEC=113
4463 11:19:59.782458 [RxdqsGatingPostProcess] freq 600
4464 11:19:59.785980 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4465 11:19:59.788836 Pre-setting of DQS Precalculation
4466 11:19:59.795601 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4467 11:19:59.796118 ==
4468 11:19:59.798631 Dram Type= 6, Freq= 0, CH_1, rank 0
4469 11:19:59.802539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4470 11:19:59.802959 ==
4471 11:19:59.808383 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4472 11:19:59.812303 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4473 11:19:59.817536 [CA 0] Center 35 (5~66) winsize 62
4474 11:19:59.819956 [CA 1] Center 35 (5~66) winsize 62
4475 11:19:59.823064 [CA 2] Center 34 (4~65) winsize 62
4476 11:19:59.826287 [CA 3] Center 33 (3~64) winsize 62
4477 11:19:59.829737 [CA 4] Center 34 (4~65) winsize 62
4478 11:19:59.833073 [CA 5] Center 33 (3~64) winsize 62
4479 11:19:59.833534
4480 11:19:59.836273 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4481 11:19:59.836775
4482 11:19:59.839422 [CATrainingPosCal] consider 1 rank data
4483 11:19:59.842870 u2DelayCellTimex100 = 270/100 ps
4484 11:19:59.845806 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4485 11:19:59.852800 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4486 11:19:59.855990 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4487 11:19:59.859051 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4488 11:19:59.862340 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4489 11:19:59.866011 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4490 11:19:59.866592
4491 11:19:59.869200 CA PerBit enable=1, Macro0, CA PI delay=33
4492 11:19:59.869681
4493 11:19:59.872307 [CBTSetCACLKResult] CA Dly = 33
4494 11:19:59.876021 CS Dly: 4 (0~35)
4495 11:19:59.876637 ==
4496 11:19:59.879287 Dram Type= 6, Freq= 0, CH_1, rank 1
4497 11:19:59.882034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4498 11:19:59.882475 ==
4499 11:19:59.888739 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4500 11:19:59.895485 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4501 11:19:59.898329 [CA 0] Center 35 (5~66) winsize 62
4502 11:19:59.901628 [CA 1] Center 36 (6~66) winsize 61
4503 11:19:59.905007 [CA 2] Center 34 (4~65) winsize 62
4504 11:19:59.908171 [CA 3] Center 34 (3~65) winsize 63
4505 11:19:59.911600 [CA 4] Center 34 (4~65) winsize 62
4506 11:19:59.915381 [CA 5] Center 34 (3~65) winsize 63
4507 11:19:59.915956
4508 11:19:59.918062 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4509 11:19:59.918540
4510 11:19:59.921543 [CATrainingPosCal] consider 2 rank data
4511 11:19:59.924967 u2DelayCellTimex100 = 270/100 ps
4512 11:19:59.928134 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4513 11:19:59.932141 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4514 11:19:59.934730 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4515 11:19:59.937942 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4516 11:19:59.941734 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4517 11:19:59.944483 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4518 11:19:59.944939
4519 11:19:59.951246 CA PerBit enable=1, Macro0, CA PI delay=33
4520 11:19:59.951739
4521 11:19:59.952088 [CBTSetCACLKResult] CA Dly = 33
4522 11:19:59.954780 CS Dly: 5 (0~37)
4523 11:19:59.955208
4524 11:19:59.957548 ----->DramcWriteLeveling(PI) begin...
4525 11:19:59.957981 ==
4526 11:19:59.960945 Dram Type= 6, Freq= 0, CH_1, rank 0
4527 11:19:59.964616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4528 11:19:59.965137 ==
4529 11:19:59.967522 Write leveling (Byte 0): 29 => 29
4530 11:19:59.971375 Write leveling (Byte 1): 31 => 31
4531 11:19:59.974159 DramcWriteLeveling(PI) end<-----
4532 11:19:59.974586
4533 11:19:59.974922 ==
4534 11:19:59.977861 Dram Type= 6, Freq= 0, CH_1, rank 0
4535 11:19:59.984430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4536 11:19:59.985047 ==
4537 11:19:59.985429 [Gating] SW mode calibration
4538 11:19:59.995300 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4539 11:19:59.997639 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4540 11:20:00.000777 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4541 11:20:00.007124 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4542 11:20:00.010378 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
4543 11:20:00.014358 0 9 12 | B1->B0 | 3030 2d2d | 1 1 | (1 0) (1 0)
4544 11:20:00.020600 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4545 11:20:00.023715 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4546 11:20:00.026753 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4547 11:20:00.033473 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4548 11:20:00.037176 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4549 11:20:00.043940 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4550 11:20:00.046772 0 10 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4551 11:20:00.049739 0 10 12 | B1->B0 | 3030 3a3a | 0 0 | (0 0) (0 0)
4552 11:20:00.056819 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (1 1) (0 0)
4553 11:20:00.059821 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4554 11:20:00.063167 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4555 11:20:00.070151 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4556 11:20:00.073203 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4557 11:20:00.076483 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4558 11:20:00.083082 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4559 11:20:00.086500 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4560 11:20:00.089794 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4561 11:20:00.096235 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4562 11:20:00.099269 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4563 11:20:00.103065 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4564 11:20:00.109344 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4565 11:20:00.112719 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4566 11:20:00.116152 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4567 11:20:00.122209 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4568 11:20:00.125679 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4569 11:20:00.128838 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4570 11:20:00.135846 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4571 11:20:00.139021 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4572 11:20:00.142587 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4573 11:20:00.148554 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4574 11:20:00.152146 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4575 11:20:00.155140 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4576 11:20:00.158982 Total UI for P1: 0, mck2ui 16
4577 11:20:00.161883 best dqsien dly found for B0: ( 0, 13, 10)
4578 11:20:00.168381 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4579 11:20:00.168725 Total UI for P1: 0, mck2ui 16
4580 11:20:00.171519 best dqsien dly found for B1: ( 0, 13, 12)
4581 11:20:00.178857 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4582 11:20:00.181556 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4583 11:20:00.181994
4584 11:20:00.185482 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4585 11:20:00.188477 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4586 11:20:00.191355 [Gating] SW calibration Done
4587 11:20:00.191824 ==
4588 11:20:00.195075 Dram Type= 6, Freq= 0, CH_1, rank 0
4589 11:20:00.198185 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4590 11:20:00.198661 ==
4591 11:20:00.202691 RX Vref Scan: 0
4592 11:20:00.203257
4593 11:20:00.203665 RX Vref 0 -> 0, step: 1
4594 11:20:00.204102
4595 11:20:00.204902 RX Delay -230 -> 252, step: 16
4596 11:20:00.211566 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4597 11:20:00.214991 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4598 11:20:00.217834 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4599 11:20:00.221307 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4600 11:20:00.224908 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4601 11:20:00.230982 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4602 11:20:00.235262 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4603 11:20:00.238255 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4604 11:20:00.241204 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4605 11:20:00.247927 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4606 11:20:00.250803 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4607 11:20:00.254553 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4608 11:20:00.257988 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4609 11:20:00.264452 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4610 11:20:00.267589 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4611 11:20:00.271121 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4612 11:20:00.271597 ==
4613 11:20:00.274085 Dram Type= 6, Freq= 0, CH_1, rank 0
4614 11:20:00.278226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4615 11:20:00.281124 ==
4616 11:20:00.281593 DQS Delay:
4617 11:20:00.281965 DQS0 = 0, DQS1 = 0
4618 11:20:00.284780 DQM Delay:
4619 11:20:00.285340 DQM0 = 46, DQM1 = 40
4620 11:20:00.287390 DQ Delay:
4621 11:20:00.287857 DQ0 =49, DQ1 =41, DQ2 =41, DQ3 =41
4622 11:20:00.291226 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4623 11:20:00.294139 DQ8 =25, DQ9 =33, DQ10 =41, DQ11 =25
4624 11:20:00.297568 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4625 11:20:00.298139
4626 11:20:00.300793
4627 11:20:00.301262 ==
4628 11:20:00.303861 Dram Type= 6, Freq= 0, CH_1, rank 0
4629 11:20:00.307437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4630 11:20:00.308012 ==
4631 11:20:00.308392
4632 11:20:00.308804
4633 11:20:00.310757 TX Vref Scan disable
4634 11:20:00.311228 == TX Byte 0 ==
4635 11:20:00.317242 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4636 11:20:00.320315 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4637 11:20:00.320832 == TX Byte 1 ==
4638 11:20:00.326891 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4639 11:20:00.330162 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4640 11:20:00.330630 ==
4641 11:20:00.333572 Dram Type= 6, Freq= 0, CH_1, rank 0
4642 11:20:00.336826 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4643 11:20:00.337254 ==
4644 11:20:00.337597
4645 11:20:00.338022
4646 11:20:00.340035 TX Vref Scan disable
4647 11:20:00.343750 == TX Byte 0 ==
4648 11:20:00.346869 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4649 11:20:00.350294 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4650 11:20:00.353899 == TX Byte 1 ==
4651 11:20:00.356622 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4652 11:20:00.363211 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4653 11:20:00.363637
4654 11:20:00.363978 [DATLAT]
4655 11:20:00.364314 Freq=600, CH1 RK0
4656 11:20:00.364775
4657 11:20:00.366711 DATLAT Default: 0x9
4658 11:20:00.367136 0, 0xFFFF, sum = 0
4659 11:20:00.370604 1, 0xFFFF, sum = 0
4660 11:20:00.371093 2, 0xFFFF, sum = 0
4661 11:20:00.373584 3, 0xFFFF, sum = 0
4662 11:20:00.374018 4, 0xFFFF, sum = 0
4663 11:20:00.377170 5, 0xFFFF, sum = 0
4664 11:20:00.380106 6, 0xFFFF, sum = 0
4665 11:20:00.380565 7, 0xFFFF, sum = 0
4666 11:20:00.383531 8, 0x0, sum = 1
4667 11:20:00.383968 9, 0x0, sum = 2
4668 11:20:00.384343 10, 0x0, sum = 3
4669 11:20:00.386648 11, 0x0, sum = 4
4670 11:20:00.387079 best_step = 9
4671 11:20:00.387415
4672 11:20:00.387750 ==
4673 11:20:00.390369 Dram Type= 6, Freq= 0, CH_1, rank 0
4674 11:20:00.396942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4675 11:20:00.397479 ==
4676 11:20:00.397822 RX Vref Scan: 1
4677 11:20:00.398206
4678 11:20:00.399863 RX Vref 0 -> 0, step: 1
4679 11:20:00.400305
4680 11:20:00.403939 RX Delay -179 -> 252, step: 8
4681 11:20:00.404473
4682 11:20:00.407155 Set Vref, RX VrefLevel [Byte0]: 48
4683 11:20:00.410136 [Byte1]: 53
4684 11:20:00.410563
4685 11:20:00.413248 Final RX Vref Byte 0 = 48 to rank0
4686 11:20:00.416589 Final RX Vref Byte 1 = 53 to rank0
4687 11:20:00.419507 Final RX Vref Byte 0 = 48 to rank1
4688 11:20:00.423807 Final RX Vref Byte 1 = 53 to rank1==
4689 11:20:00.426962 Dram Type= 6, Freq= 0, CH_1, rank 0
4690 11:20:00.429686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4691 11:20:00.430125 ==
4692 11:20:00.433221 DQS Delay:
4693 11:20:00.433653 DQS0 = 0, DQS1 = 0
4694 11:20:00.436307 DQM Delay:
4695 11:20:00.436765 DQM0 = 47, DQM1 = 37
4696 11:20:00.437102 DQ Delay:
4697 11:20:00.439471 DQ0 =56, DQ1 =40, DQ2 =40, DQ3 =44
4698 11:20:00.443001 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =44
4699 11:20:00.446466 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4700 11:20:00.449153 DQ12 =44, DQ13 =40, DQ14 =48, DQ15 =48
4701 11:20:00.449584
4702 11:20:00.449976
4703 11:20:00.459302 [DQSOSCAuto] RK0, (LSB)MR18= 0x5034, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 394 ps
4704 11:20:00.462649 CH1 RK0: MR19=808, MR18=5034
4705 11:20:00.469461 CH1_RK0: MR19=0x808, MR18=0x5034, DQSOSC=394, MR23=63, INC=168, DEC=112
4706 11:20:00.470020
4707 11:20:00.472368 ----->DramcWriteLeveling(PI) begin...
4708 11:20:00.472879 ==
4709 11:20:00.475423 Dram Type= 6, Freq= 0, CH_1, rank 1
4710 11:20:00.478973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4711 11:20:00.479552 ==
4712 11:20:00.482048 Write leveling (Byte 0): 29 => 29
4713 11:20:00.485635 Write leveling (Byte 1): 29 => 29
4714 11:20:00.488606 DramcWriteLeveling(PI) end<-----
4715 11:20:00.489076
4716 11:20:00.489450 ==
4717 11:20:00.492177 Dram Type= 6, Freq= 0, CH_1, rank 1
4718 11:20:00.495652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4719 11:20:00.496233 ==
4720 11:20:00.499050 [Gating] SW mode calibration
4721 11:20:00.505481 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4722 11:20:00.512191 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4723 11:20:00.515803 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4724 11:20:00.518982 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4725 11:20:00.525427 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4726 11:20:00.528861 0 9 12 | B1->B0 | 2f2f 3333 | 1 1 | (1 1) (1 0)
4727 11:20:00.531761 0 9 16 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
4728 11:20:00.538534 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4729 11:20:00.542205 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4730 11:20:00.545174 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4731 11:20:00.551466 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4732 11:20:00.554920 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4733 11:20:00.558036 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4734 11:20:00.564791 0 10 12 | B1->B0 | 3838 2c2c | 1 0 | (0 0) (0 0)
4735 11:20:00.568684 0 10 16 | B1->B0 | 4545 4141 | 0 1 | (0 0) (0 0)
4736 11:20:00.571465 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4737 11:20:00.578159 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4738 11:20:00.581446 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4739 11:20:00.584616 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4740 11:20:00.591225 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4741 11:20:00.594614 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4742 11:20:00.598292 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4743 11:20:00.604670 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4744 11:20:00.608125 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4745 11:20:00.611405 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4746 11:20:00.617672 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4747 11:20:00.621068 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4748 11:20:00.625092 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4749 11:20:00.630497 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4750 11:20:00.634325 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4751 11:20:00.637546 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4752 11:20:00.644165 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4753 11:20:00.647297 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4754 11:20:00.650533 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4755 11:20:00.656793 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4756 11:20:00.660093 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4757 11:20:00.663496 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4758 11:20:00.670560 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4759 11:20:00.673306 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4760 11:20:00.677138 Total UI for P1: 0, mck2ui 16
4761 11:20:00.680327 best dqsien dly found for B0: ( 0, 13, 12)
4762 11:20:00.683872 Total UI for P1: 0, mck2ui 16
4763 11:20:00.686765 best dqsien dly found for B1: ( 0, 13, 10)
4764 11:20:00.690411 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4765 11:20:00.693243 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4766 11:20:00.693721
4767 11:20:00.696869 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4768 11:20:00.703421 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4769 11:20:00.704007 [Gating] SW calibration Done
4770 11:20:00.704392 ==
4771 11:20:00.706626 Dram Type= 6, Freq= 0, CH_1, rank 1
4772 11:20:00.713615 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4773 11:20:00.714198 ==
4774 11:20:00.714577 RX Vref Scan: 0
4775 11:20:00.714930
4776 11:20:00.716823 RX Vref 0 -> 0, step: 1
4777 11:20:00.717296
4778 11:20:00.720383 RX Delay -230 -> 252, step: 16
4779 11:20:00.723791 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4780 11:20:00.727167 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4781 11:20:00.733321 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4782 11:20:00.736624 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4783 11:20:00.740039 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4784 11:20:00.743512 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4785 11:20:00.746122 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4786 11:20:00.752932 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4787 11:20:00.756060 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4788 11:20:00.759667 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4789 11:20:00.762754 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4790 11:20:00.769432 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4791 11:20:00.772866 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4792 11:20:00.776052 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4793 11:20:00.779071 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4794 11:20:00.785771 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4795 11:20:00.786312 ==
4796 11:20:00.788969 Dram Type= 6, Freq= 0, CH_1, rank 1
4797 11:20:00.792434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4798 11:20:00.793023 ==
4799 11:20:00.793398 DQS Delay:
4800 11:20:00.795449 DQS0 = 0, DQS1 = 0
4801 11:20:00.795915 DQM Delay:
4802 11:20:00.799103 DQM0 = 43, DQM1 = 38
4803 11:20:00.799568 DQ Delay:
4804 11:20:00.802331 DQ0 =41, DQ1 =41, DQ2 =25, DQ3 =41
4805 11:20:00.805532 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4806 11:20:00.808974 DQ8 =17, DQ9 =33, DQ10 =33, DQ11 =25
4807 11:20:00.812144 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4808 11:20:00.812769
4809 11:20:00.813148
4810 11:20:00.813489 ==
4811 11:20:00.816159 Dram Type= 6, Freq= 0, CH_1, rank 1
4812 11:20:00.819074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4813 11:20:00.822042 ==
4814 11:20:00.822510
4815 11:20:00.822875
4816 11:20:00.823215 TX Vref Scan disable
4817 11:20:00.825329 == TX Byte 0 ==
4818 11:20:00.828636 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4819 11:20:00.834860 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4820 11:20:00.835445 == TX Byte 1 ==
4821 11:20:00.838419 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4822 11:20:00.845347 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4823 11:20:00.845873 ==
4824 11:20:00.848035 Dram Type= 6, Freq= 0, CH_1, rank 1
4825 11:20:00.851518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4826 11:20:00.852145 ==
4827 11:20:00.852504
4828 11:20:00.852897
4829 11:20:00.855403 TX Vref Scan disable
4830 11:20:00.858253 == TX Byte 0 ==
4831 11:20:00.861534 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4832 11:20:00.864645 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4833 11:20:00.868613 == TX Byte 1 ==
4834 11:20:00.871589 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4835 11:20:00.874879 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4836 11:20:00.875406
4837 11:20:00.875746 [DATLAT]
4838 11:20:00.878461 Freq=600, CH1 RK1
4839 11:20:00.878992
4840 11:20:00.881708 DATLAT Default: 0x9
4841 11:20:00.882239 0, 0xFFFF, sum = 0
4842 11:20:00.884978 1, 0xFFFF, sum = 0
4843 11:20:00.885687 2, 0xFFFF, sum = 0
4844 11:20:00.887966 3, 0xFFFF, sum = 0
4845 11:20:00.888551 4, 0xFFFF, sum = 0
4846 11:20:00.891000 5, 0xFFFF, sum = 0
4847 11:20:00.891612 6, 0xFFFF, sum = 0
4848 11:20:00.894438 7, 0xFFFF, sum = 0
4849 11:20:00.894910 8, 0x0, sum = 1
4850 11:20:00.897789 9, 0x0, sum = 2
4851 11:20:00.898262 10, 0x0, sum = 3
4852 11:20:00.900950 11, 0x0, sum = 4
4853 11:20:00.901425 best_step = 9
4854 11:20:00.901796
4855 11:20:00.902137 ==
4856 11:20:00.904822 Dram Type= 6, Freq= 0, CH_1, rank 1
4857 11:20:00.908044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4858 11:20:00.908694 ==
4859 11:20:00.910944 RX Vref Scan: 0
4860 11:20:00.911421
4861 11:20:00.914460 RX Vref 0 -> 0, step: 1
4862 11:20:00.915036
4863 11:20:00.915412 RX Delay -195 -> 252, step: 8
4864 11:20:00.922343 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4865 11:20:00.925683 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4866 11:20:00.929335 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4867 11:20:00.932666 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4868 11:20:00.939151 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4869 11:20:00.942128 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4870 11:20:00.945607 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4871 11:20:00.949081 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4872 11:20:00.952248 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4873 11:20:00.959136 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4874 11:20:00.962196 iDelay=213, Bit 10, Center 36 (-115 ~ 188) 304
4875 11:20:00.965563 iDelay=213, Bit 11, Center 28 (-123 ~ 180) 304
4876 11:20:00.968900 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4877 11:20:00.975742 iDelay=213, Bit 13, Center 44 (-107 ~ 196) 304
4878 11:20:00.978404 iDelay=213, Bit 14, Center 44 (-107 ~ 196) 304
4879 11:20:00.981966 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4880 11:20:00.982445 ==
4881 11:20:00.984987 Dram Type= 6, Freq= 0, CH_1, rank 1
4882 11:20:00.991665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4883 11:20:00.992250 ==
4884 11:20:00.992726 DQS Delay:
4885 11:20:00.993106 DQS0 = 0, DQS1 = 0
4886 11:20:00.994658 DQM Delay:
4887 11:20:00.995129 DQM0 = 45, DQM1 = 37
4888 11:20:00.998500 DQ Delay:
4889 11:20:01.001209 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4890 11:20:01.004710 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4891 11:20:01.007894 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4892 11:20:01.011436 DQ12 =48, DQ13 =44, DQ14 =44, DQ15 =48
4893 11:20:01.011920
4894 11:20:01.012402
4895 11:20:01.017967 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b20, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
4896 11:20:01.021197 CH1 RK1: MR19=808, MR18=2B20
4897 11:20:01.027855 CH1_RK1: MR19=0x808, MR18=0x2B20, DQSOSC=401, MR23=63, INC=163, DEC=108
4898 11:20:01.031345 [RxdqsGatingPostProcess] freq 600
4899 11:20:01.034061 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4900 11:20:01.038317 Pre-setting of DQS Precalculation
4901 11:20:01.044156 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4902 11:20:01.051284 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4903 11:20:01.058495 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4904 11:20:01.059059
4905 11:20:01.059430
4906 11:20:01.061392 [Calibration Summary] 1200 Mbps
4907 11:20:01.061858 CH 0, Rank 0
4908 11:20:01.064665 SW Impedance : PASS
4909 11:20:01.067759 DUTY Scan : NO K
4910 11:20:01.068318 ZQ Calibration : PASS
4911 11:20:01.070791 Jitter Meter : NO K
4912 11:20:01.074231 CBT Training : PASS
4913 11:20:01.074793 Write leveling : PASS
4914 11:20:01.077362 RX DQS gating : PASS
4915 11:20:01.081315 RX DQ/DQS(RDDQC) : PASS
4916 11:20:01.081891 TX DQ/DQS : PASS
4917 11:20:01.084318 RX DATLAT : PASS
4918 11:20:01.087741 RX DQ/DQS(Engine): PASS
4919 11:20:01.088305 TX OE : NO K
4920 11:20:01.090498 All Pass.
4921 11:20:01.090963
4922 11:20:01.091330 CH 0, Rank 1
4923 11:20:01.093957 SW Impedance : PASS
4924 11:20:01.094419 DUTY Scan : NO K
4925 11:20:01.097265 ZQ Calibration : PASS
4926 11:20:01.100284 Jitter Meter : NO K
4927 11:20:01.100783 CBT Training : PASS
4928 11:20:01.103744 Write leveling : PASS
4929 11:20:01.107730 RX DQS gating : PASS
4930 11:20:01.108318 RX DQ/DQS(RDDQC) : PASS
4931 11:20:01.110365 TX DQ/DQS : PASS
4932 11:20:01.113724 RX DATLAT : PASS
4933 11:20:01.114292 RX DQ/DQS(Engine): PASS
4934 11:20:01.117094 TX OE : NO K
4935 11:20:01.117561 All Pass.
4936 11:20:01.117932
4937 11:20:01.119906 CH 1, Rank 0
4938 11:20:01.120377 SW Impedance : PASS
4939 11:20:01.123776 DUTY Scan : NO K
4940 11:20:01.127131 ZQ Calibration : PASS
4941 11:20:01.127699 Jitter Meter : NO K
4942 11:20:01.130092 CBT Training : PASS
4943 11:20:01.130559 Write leveling : PASS
4944 11:20:01.133440 RX DQS gating : PASS
4945 11:20:01.137035 RX DQ/DQS(RDDQC) : PASS
4946 11:20:01.137505 TX DQ/DQS : PASS
4947 11:20:01.140438 RX DATLAT : PASS
4948 11:20:01.143098 RX DQ/DQS(Engine): PASS
4949 11:20:01.143570 TX OE : NO K
4950 11:20:01.146470 All Pass.
4951 11:20:01.147029
4952 11:20:01.147592 CH 1, Rank 1
4953 11:20:01.149614 SW Impedance : PASS
4954 11:20:01.150082 DUTY Scan : NO K
4955 11:20:01.153241 ZQ Calibration : PASS
4956 11:20:01.156353 Jitter Meter : NO K
4957 11:20:01.156892 CBT Training : PASS
4958 11:20:01.160414 Write leveling : PASS
4959 11:20:01.163438 RX DQS gating : PASS
4960 11:20:01.163974 RX DQ/DQS(RDDQC) : PASS
4961 11:20:01.166618 TX DQ/DQS : PASS
4962 11:20:01.169623 RX DATLAT : PASS
4963 11:20:01.170101 RX DQ/DQS(Engine): PASS
4964 11:20:01.172955 TX OE : NO K
4965 11:20:01.173432 All Pass.
4966 11:20:01.173811
4967 11:20:01.176691 DramC Write-DBI off
4968 11:20:01.179690 PER_BANK_REFRESH: Hybrid Mode
4969 11:20:01.180272 TX_TRACKING: ON
4970 11:20:01.189424 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4971 11:20:01.192835 [FAST_K] Save calibration result to emmc
4972 11:20:01.195949 dramc_set_vcore_voltage set vcore to 662500
4973 11:20:01.199772 Read voltage for 933, 3
4974 11:20:01.200248 Vio18 = 0
4975 11:20:01.200678 Vcore = 662500
4976 11:20:01.203475 Vdram = 0
4977 11:20:01.204052 Vddq = 0
4978 11:20:01.204435 Vmddr = 0
4979 11:20:01.209282 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4980 11:20:01.212725 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4981 11:20:01.216699 MEM_TYPE=3, freq_sel=17
4982 11:20:01.219887 sv_algorithm_assistance_LP4_1600
4983 11:20:01.222544 ============ PULL DRAM RESETB DOWN ============
4984 11:20:01.225650 ========== PULL DRAM RESETB DOWN end =========
4985 11:20:01.232302 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4986 11:20:01.235448 ===================================
4987 11:20:01.239188 LPDDR4 DRAM CONFIGURATION
4988 11:20:01.242085 ===================================
4989 11:20:01.242566 EX_ROW_EN[0] = 0x0
4990 11:20:01.246128 EX_ROW_EN[1] = 0x0
4991 11:20:01.246702 LP4Y_EN = 0x0
4992 11:20:01.249259 WORK_FSP = 0x0
4993 11:20:01.249734 WL = 0x3
4994 11:20:01.252574 RL = 0x3
4995 11:20:01.253199 BL = 0x2
4996 11:20:01.255786 RPST = 0x0
4997 11:20:01.256357 RD_PRE = 0x0
4998 11:20:01.258828 WR_PRE = 0x1
4999 11:20:01.259398 WR_PST = 0x0
5000 11:20:01.262195 DBI_WR = 0x0
5001 11:20:01.262668 DBI_RD = 0x0
5002 11:20:01.266115 OTF = 0x1
5003 11:20:01.269047 ===================================
5004 11:20:01.272397 ===================================
5005 11:20:01.272994 ANA top config
5006 11:20:01.275739 ===================================
5007 11:20:01.278953 DLL_ASYNC_EN = 0
5008 11:20:01.282133 ALL_SLAVE_EN = 1
5009 11:20:01.285403 NEW_RANK_MODE = 1
5010 11:20:01.285892 DLL_IDLE_MODE = 1
5011 11:20:01.289008 LP45_APHY_COMB_EN = 1
5012 11:20:01.291985 TX_ODT_DIS = 1
5013 11:20:01.295664 NEW_8X_MODE = 1
5014 11:20:01.299275 ===================================
5015 11:20:01.301801 ===================================
5016 11:20:01.305469 data_rate = 1866
5017 11:20:01.308371 CKR = 1
5018 11:20:01.308990 DQ_P2S_RATIO = 8
5019 11:20:01.312142 ===================================
5020 11:20:01.315310 CA_P2S_RATIO = 8
5021 11:20:01.318681 DQ_CA_OPEN = 0
5022 11:20:01.321503 DQ_SEMI_OPEN = 0
5023 11:20:01.324649 CA_SEMI_OPEN = 0
5024 11:20:01.328282 CA_FULL_RATE = 0
5025 11:20:01.328807 DQ_CKDIV4_EN = 1
5026 11:20:01.331315 CA_CKDIV4_EN = 1
5027 11:20:01.334830 CA_PREDIV_EN = 0
5028 11:20:01.338207 PH8_DLY = 0
5029 11:20:01.341411 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
5030 11:20:01.344581 DQ_AAMCK_DIV = 4
5031 11:20:01.345068 CA_AAMCK_DIV = 4
5032 11:20:01.348375 CA_ADMCK_DIV = 4
5033 11:20:01.351553 DQ_TRACK_CA_EN = 0
5034 11:20:01.354884 CA_PICK = 933
5035 11:20:01.358119 CA_MCKIO = 933
5036 11:20:01.361590 MCKIO_SEMI = 0
5037 11:20:01.365133 PLL_FREQ = 3732
5038 11:20:01.365716 DQ_UI_PI_RATIO = 32
5039 11:20:01.368098 CA_UI_PI_RATIO = 0
5040 11:20:01.370990 ===================================
5041 11:20:01.374557 ===================================
5042 11:20:01.377689 memory_type:LPDDR4
5043 11:20:01.381284 GP_NUM : 10
5044 11:20:01.381861 SRAM_EN : 1
5045 11:20:01.384311 MD32_EN : 0
5046 11:20:01.388161 ===================================
5047 11:20:01.391301 [ANA_INIT] >>>>>>>>>>>>>>
5048 11:20:01.391866 <<<<<< [CONFIGURE PHASE]: ANA_TX
5049 11:20:01.397790 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5050 11:20:01.400841 ===================================
5051 11:20:01.401313 data_rate = 1866,PCW = 0X8f00
5052 11:20:01.404239 ===================================
5053 11:20:01.407563 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5054 11:20:01.414113 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5055 11:20:01.420760 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5056 11:20:01.424015 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5057 11:20:01.427630 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5058 11:20:01.430691 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5059 11:20:01.433937 [ANA_INIT] flow start
5060 11:20:01.434412 [ANA_INIT] PLL >>>>>>>>
5061 11:20:01.437391 [ANA_INIT] PLL <<<<<<<<
5062 11:20:01.440733 [ANA_INIT] MIDPI >>>>>>>>
5063 11:20:01.444058 [ANA_INIT] MIDPI <<<<<<<<
5064 11:20:01.444565 [ANA_INIT] DLL >>>>>>>>
5065 11:20:01.447665 [ANA_INIT] flow end
5066 11:20:01.450715 ============ LP4 DIFF to SE enter ============
5067 11:20:01.453812 ============ LP4 DIFF to SE exit ============
5068 11:20:01.457192 [ANA_INIT] <<<<<<<<<<<<<
5069 11:20:01.460876 [Flow] Enable top DCM control >>>>>
5070 11:20:01.464367 [Flow] Enable top DCM control <<<<<
5071 11:20:01.466881 Enable DLL master slave shuffle
5072 11:20:01.473734 ==============================================================
5073 11:20:01.474303 Gating Mode config
5074 11:20:01.480006 ==============================================================
5075 11:20:01.480624 Config description:
5076 11:20:01.490072 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5077 11:20:01.496878 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5078 11:20:01.503458 SELPH_MODE 0: By rank 1: By Phase
5079 11:20:01.510270 ==============================================================
5080 11:20:01.510850 GAT_TRACK_EN = 1
5081 11:20:01.513180 RX_GATING_MODE = 2
5082 11:20:01.516249 RX_GATING_TRACK_MODE = 2
5083 11:20:01.520227 SELPH_MODE = 1
5084 11:20:01.523532 PICG_EARLY_EN = 1
5085 11:20:01.526753 VALID_LAT_VALUE = 1
5086 11:20:01.533706 ==============================================================
5087 11:20:01.536372 Enter into Gating configuration >>>>
5088 11:20:01.539978 Exit from Gating configuration <<<<
5089 11:20:01.543130 Enter into DVFS_PRE_config >>>>>
5090 11:20:01.552888 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5091 11:20:01.556259 Exit from DVFS_PRE_config <<<<<
5092 11:20:01.559611 Enter into PICG configuration >>>>
5093 11:20:01.562539 Exit from PICG configuration <<<<
5094 11:20:01.565892 [RX_INPUT] configuration >>>>>
5095 11:20:01.566362 [RX_INPUT] configuration <<<<<
5096 11:20:01.573396 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5097 11:20:01.579163 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5098 11:20:01.586216 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5099 11:20:01.589018 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5100 11:20:01.595699 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5101 11:20:01.602231 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5102 11:20:01.605334 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5103 11:20:01.608797 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5104 11:20:01.615666 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5105 11:20:01.618652 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5106 11:20:01.622262 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5107 11:20:01.629034 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5108 11:20:01.632002 ===================================
5109 11:20:01.632236 LPDDR4 DRAM CONFIGURATION
5110 11:20:01.635449 ===================================
5111 11:20:01.638774 EX_ROW_EN[0] = 0x0
5112 11:20:01.641680 EX_ROW_EN[1] = 0x0
5113 11:20:01.641836 LP4Y_EN = 0x0
5114 11:20:01.645561 WORK_FSP = 0x0
5115 11:20:01.645716 WL = 0x3
5116 11:20:01.648066 RL = 0x3
5117 11:20:01.648222 BL = 0x2
5118 11:20:01.651326 RPST = 0x0
5119 11:20:01.651487 RD_PRE = 0x0
5120 11:20:01.654990 WR_PRE = 0x1
5121 11:20:01.655153 WR_PST = 0x0
5122 11:20:01.658329 DBI_WR = 0x0
5123 11:20:01.658487 DBI_RD = 0x0
5124 11:20:01.661697 OTF = 0x1
5125 11:20:01.665458 ===================================
5126 11:20:01.668373 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5127 11:20:01.671654 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5128 11:20:01.678415 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5129 11:20:01.681317 ===================================
5130 11:20:01.681745 LPDDR4 DRAM CONFIGURATION
5131 11:20:01.685432 ===================================
5132 11:20:01.687824 EX_ROW_EN[0] = 0x10
5133 11:20:01.691740 EX_ROW_EN[1] = 0x0
5134 11:20:01.692179 LP4Y_EN = 0x0
5135 11:20:01.694512 WORK_FSP = 0x0
5136 11:20:01.694948 WL = 0x3
5137 11:20:01.698522 RL = 0x3
5138 11:20:01.698963 BL = 0x2
5139 11:20:01.701266 RPST = 0x0
5140 11:20:01.701706 RD_PRE = 0x0
5141 11:20:01.704945 WR_PRE = 0x1
5142 11:20:01.705261 WR_PST = 0x0
5143 11:20:01.707647 DBI_WR = 0x0
5144 11:20:01.707954 DBI_RD = 0x0
5145 11:20:01.710840 OTF = 0x1
5146 11:20:01.714865 ===================================
5147 11:20:01.720702 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5148 11:20:01.724032 nWR fixed to 30
5149 11:20:01.724216 [ModeRegInit_LP4] CH0 RK0
5150 11:20:01.727826 [ModeRegInit_LP4] CH0 RK1
5151 11:20:01.731071 [ModeRegInit_LP4] CH1 RK0
5152 11:20:01.733948 [ModeRegInit_LP4] CH1 RK1
5153 11:20:01.734081 match AC timing 9
5154 11:20:01.741114 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5155 11:20:01.744631 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5156 11:20:01.747404 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5157 11:20:01.753937 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5158 11:20:01.757162 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5159 11:20:01.757589 ==
5160 11:20:01.761038 Dram Type= 6, Freq= 0, CH_0, rank 0
5161 11:20:01.764291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5162 11:20:01.764797 ==
5163 11:20:01.770452 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5164 11:20:01.777197 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5165 11:20:01.781026 [CA 0] Center 37 (7~68) winsize 62
5166 11:20:01.783941 [CA 1] Center 37 (7~68) winsize 62
5167 11:20:01.787424 [CA 2] Center 34 (4~65) winsize 62
5168 11:20:01.790494 [CA 3] Center 35 (5~65) winsize 61
5169 11:20:01.794096 [CA 4] Center 33 (3~64) winsize 62
5170 11:20:01.797324 [CA 5] Center 33 (3~63) winsize 61
5171 11:20:01.797893
5172 11:20:01.800430 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5173 11:20:01.800952
5174 11:20:01.803453 [CATrainingPosCal] consider 1 rank data
5175 11:20:01.806923 u2DelayCellTimex100 = 270/100 ps
5176 11:20:01.810596 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5177 11:20:01.813854 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5178 11:20:01.816857 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5179 11:20:01.820049 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5180 11:20:01.823424 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5181 11:20:01.830207 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5182 11:20:01.830779
5183 11:20:01.833952 CA PerBit enable=1, Macro0, CA PI delay=33
5184 11:20:01.834519
5185 11:20:01.836680 [CBTSetCACLKResult] CA Dly = 33
5186 11:20:01.837159 CS Dly: 7 (0~38)
5187 11:20:01.837537 ==
5188 11:20:01.840209 Dram Type= 6, Freq= 0, CH_0, rank 1
5189 11:20:01.843173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5190 11:20:01.846478 ==
5191 11:20:01.850152 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5192 11:20:01.856780 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5193 11:20:01.859871 [CA 0] Center 37 (7~68) winsize 62
5194 11:20:01.863157 [CA 1] Center 37 (7~68) winsize 62
5195 11:20:01.866467 [CA 2] Center 34 (4~65) winsize 62
5196 11:20:01.869486 [CA 3] Center 34 (4~65) winsize 62
5197 11:20:01.872733 [CA 4] Center 33 (3~64) winsize 62
5198 11:20:01.876303 [CA 5] Center 33 (3~63) winsize 61
5199 11:20:01.876911
5200 11:20:01.880254 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5201 11:20:01.880862
5202 11:20:01.883384 [CATrainingPosCal] consider 2 rank data
5203 11:20:01.886050 u2DelayCellTimex100 = 270/100 ps
5204 11:20:01.889446 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5205 11:20:01.893406 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5206 11:20:01.896121 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5207 11:20:01.902790 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5208 11:20:01.906177 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5209 11:20:01.910349 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5210 11:20:01.910937
5211 11:20:01.912586 CA PerBit enable=1, Macro0, CA PI delay=33
5212 11:20:01.913077
5213 11:20:01.916226 [CBTSetCACLKResult] CA Dly = 33
5214 11:20:01.916753 CS Dly: 7 (0~39)
5215 11:20:01.917245
5216 11:20:01.919360 ----->DramcWriteLeveling(PI) begin...
5217 11:20:01.922816 ==
5218 11:20:01.926001 Dram Type= 6, Freq= 0, CH_0, rank 0
5219 11:20:01.929255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5220 11:20:01.929837 ==
5221 11:20:01.932684 Write leveling (Byte 0): 34 => 34
5222 11:20:01.936426 Write leveling (Byte 1): 31 => 31
5223 11:20:01.939351 DramcWriteLeveling(PI) end<-----
5224 11:20:01.939842
5225 11:20:01.940321 ==
5226 11:20:01.942643 Dram Type= 6, Freq= 0, CH_0, rank 0
5227 11:20:01.945596 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5228 11:20:01.946184 ==
5229 11:20:01.948834 [Gating] SW mode calibration
5230 11:20:01.955548 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5231 11:20:01.961967 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5232 11:20:01.965581 0 14 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
5233 11:20:01.968725 0 14 4 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
5234 11:20:01.975609 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5235 11:20:01.978571 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5236 11:20:01.981931 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5237 11:20:01.988577 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5238 11:20:01.991716 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5239 11:20:01.995070 0 14 28 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
5240 11:20:02.001965 0 15 0 | B1->B0 | 3030 2525 | 1 0 | (1 0) (0 0)
5241 11:20:02.005126 0 15 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5242 11:20:02.008286 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5243 11:20:02.014744 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5244 11:20:02.018414 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5245 11:20:02.021384 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5246 11:20:02.027897 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5247 11:20:02.031145 0 15 28 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
5248 11:20:02.034297 1 0 0 | B1->B0 | 3131 4545 | 0 0 | (1 1) (0 0)
5249 11:20:02.041096 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (1 1) (0 0)
5250 11:20:02.044547 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5251 11:20:02.048617 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5252 11:20:02.054458 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5253 11:20:02.057849 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5254 11:20:02.061080 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5255 11:20:02.067882 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5256 11:20:02.071509 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5257 11:20:02.074148 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5258 11:20:02.080776 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5259 11:20:02.084216 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5260 11:20:02.087371 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5261 11:20:02.094593 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5262 11:20:02.096859 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5263 11:20:02.100496 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5264 11:20:02.107391 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5265 11:20:02.110137 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5266 11:20:02.113418 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5267 11:20:02.120884 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5268 11:20:02.123780 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5269 11:20:02.127144 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5270 11:20:02.133236 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5271 11:20:02.137218 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5272 11:20:02.140016 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5273 11:20:02.143352 Total UI for P1: 0, mck2ui 16
5274 11:20:02.146922 best dqsien dly found for B0: ( 1, 2, 28)
5275 11:20:02.153662 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5276 11:20:02.154232 Total UI for P1: 0, mck2ui 16
5277 11:20:02.159717 best dqsien dly found for B1: ( 1, 3, 0)
5278 11:20:02.163238 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5279 11:20:02.166595 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5280 11:20:02.167067
5281 11:20:02.169573 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5282 11:20:02.173210 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5283 11:20:02.176190 [Gating] SW calibration Done
5284 11:20:02.176799 ==
5285 11:20:02.179872 Dram Type= 6, Freq= 0, CH_0, rank 0
5286 11:20:02.183075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5287 11:20:02.183653 ==
5288 11:20:02.186047 RX Vref Scan: 0
5289 11:20:02.186515
5290 11:20:02.186886 RX Vref 0 -> 0, step: 1
5291 11:20:02.187232
5292 11:20:02.189553 RX Delay -80 -> 252, step: 8
5293 11:20:02.192961 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5294 11:20:02.199731 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5295 11:20:02.203293 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5296 11:20:02.206534 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5297 11:20:02.209307 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5298 11:20:02.212689 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5299 11:20:02.216132 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5300 11:20:02.222309 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5301 11:20:02.226151 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5302 11:20:02.229295 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5303 11:20:02.232339 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5304 11:20:02.235884 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5305 11:20:02.242242 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5306 11:20:02.246293 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5307 11:20:02.248887 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5308 11:20:02.252378 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5309 11:20:02.252993 ==
5310 11:20:02.255492 Dram Type= 6, Freq= 0, CH_0, rank 0
5311 11:20:02.262503 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5312 11:20:02.263072 ==
5313 11:20:02.263445 DQS Delay:
5314 11:20:02.263784 DQS0 = 0, DQS1 = 0
5315 11:20:02.265284 DQM Delay:
5316 11:20:02.265749 DQM0 = 97, DQM1 = 86
5317 11:20:02.268996 DQ Delay:
5318 11:20:02.272233 DQ0 =99, DQ1 =99, DQ2 =91, DQ3 =91
5319 11:20:02.275232 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5320 11:20:02.278821 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5321 11:20:02.282032 DQ12 =91, DQ13 =91, DQ14 =91, DQ15 =91
5322 11:20:02.282601
5323 11:20:02.282967
5324 11:20:02.283304 ==
5325 11:20:02.285487 Dram Type= 6, Freq= 0, CH_0, rank 0
5326 11:20:02.288481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5327 11:20:02.288986 ==
5328 11:20:02.289360
5329 11:20:02.289701
5330 11:20:02.291853 TX Vref Scan disable
5331 11:20:02.292362 == TX Byte 0 ==
5332 11:20:02.298532 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5333 11:20:02.302292 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5334 11:20:02.305211 == TX Byte 1 ==
5335 11:20:02.308042 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5336 11:20:02.311711 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5337 11:20:02.312312 ==
5338 11:20:02.314792 Dram Type= 6, Freq= 0, CH_0, rank 0
5339 11:20:02.318789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5340 11:20:02.321680 ==
5341 11:20:02.322250
5342 11:20:02.322629
5343 11:20:02.322979 TX Vref Scan disable
5344 11:20:02.325004 == TX Byte 0 ==
5345 11:20:02.328573 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5346 11:20:02.335130 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5347 11:20:02.335704 == TX Byte 1 ==
5348 11:20:02.338382 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5349 11:20:02.345066 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5350 11:20:02.345636
5351 11:20:02.346013 [DATLAT]
5352 11:20:02.346364 Freq=933, CH0 RK0
5353 11:20:02.346704
5354 11:20:02.348196 DATLAT Default: 0xd
5355 11:20:02.348696 0, 0xFFFF, sum = 0
5356 11:20:02.351394 1, 0xFFFF, sum = 0
5357 11:20:02.354749 2, 0xFFFF, sum = 0
5358 11:20:02.355369 3, 0xFFFF, sum = 0
5359 11:20:02.358219 4, 0xFFFF, sum = 0
5360 11:20:02.358702 5, 0xFFFF, sum = 0
5361 11:20:02.361124 6, 0xFFFF, sum = 0
5362 11:20:02.361595 7, 0xFFFF, sum = 0
5363 11:20:02.364413 8, 0xFFFF, sum = 0
5364 11:20:02.364959 9, 0xFFFF, sum = 0
5365 11:20:02.367581 10, 0x0, sum = 1
5366 11:20:02.368052 11, 0x0, sum = 2
5367 11:20:02.371307 12, 0x0, sum = 3
5368 11:20:02.371777 13, 0x0, sum = 4
5369 11:20:02.372146 best_step = 11
5370 11:20:02.374342
5371 11:20:02.374777 ==
5372 11:20:02.377389 Dram Type= 6, Freq= 0, CH_0, rank 0
5373 11:20:02.381077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5374 11:20:02.381503 ==
5375 11:20:02.381839 RX Vref Scan: 1
5376 11:20:02.382147
5377 11:20:02.385080 RX Vref 0 -> 0, step: 1
5378 11:20:02.385594
5379 11:20:02.388326 RX Delay -61 -> 252, step: 4
5380 11:20:02.389211
5381 11:20:02.391238 Set Vref, RX VrefLevel [Byte0]: 60
5382 11:20:02.394637 [Byte1]: 49
5383 11:20:02.397631
5384 11:20:02.398378 Final RX Vref Byte 0 = 60 to rank0
5385 11:20:02.401062 Final RX Vref Byte 1 = 49 to rank0
5386 11:20:02.404119 Final RX Vref Byte 0 = 60 to rank1
5387 11:20:02.407192 Final RX Vref Byte 1 = 49 to rank1==
5388 11:20:02.410587 Dram Type= 6, Freq= 0, CH_0, rank 0
5389 11:20:02.417470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5390 11:20:02.418083 ==
5391 11:20:02.418450 DQS Delay:
5392 11:20:02.420564 DQS0 = 0, DQS1 = 0
5393 11:20:02.421029 DQM Delay:
5394 11:20:02.421393 DQM0 = 97, DQM1 = 85
5395 11:20:02.424003 DQ Delay:
5396 11:20:02.427279 DQ0 =94, DQ1 =98, DQ2 =92, DQ3 =92
5397 11:20:02.430438 DQ4 =98, DQ5 =88, DQ6 =108, DQ7 =106
5398 11:20:02.433796 DQ8 =78, DQ9 =74, DQ10 =84, DQ11 =80
5399 11:20:02.437489 DQ12 =92, DQ13 =88, DQ14 =98, DQ15 =92
5400 11:20:02.438066
5401 11:20:02.438439
5402 11:20:02.443802 [DQSOSCAuto] RK0, (LSB)MR18= 0x2d13, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 407 ps
5403 11:20:02.447030 CH0 RK0: MR19=505, MR18=2D13
5404 11:20:02.454036 CH0_RK0: MR19=0x505, MR18=0x2D13, DQSOSC=407, MR23=63, INC=65, DEC=43
5405 11:20:02.454584
5406 11:20:02.456978 ----->DramcWriteLeveling(PI) begin...
5407 11:20:02.457494 ==
5408 11:20:02.460117 Dram Type= 6, Freq= 0, CH_0, rank 1
5409 11:20:02.464079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5410 11:20:02.464680 ==
5411 11:20:02.467262 Write leveling (Byte 0): 31 => 31
5412 11:20:02.470367 Write leveling (Byte 1): 29 => 29
5413 11:20:02.473726 DramcWriteLeveling(PI) end<-----
5414 11:20:02.474269
5415 11:20:02.474631 ==
5416 11:20:02.477302 Dram Type= 6, Freq= 0, CH_0, rank 1
5417 11:20:02.480434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5418 11:20:02.484387 ==
5419 11:20:02.484986 [Gating] SW mode calibration
5420 11:20:02.493455 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5421 11:20:02.497443 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5422 11:20:02.499625 0 14 0 | B1->B0 | 2b2b 3333 | 1 0 | (0 0) (0 0)
5423 11:20:02.506673 0 14 4 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5424 11:20:02.510103 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5425 11:20:02.512651 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5426 11:20:02.519616 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5427 11:20:02.523153 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5428 11:20:02.525933 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5429 11:20:02.532597 0 14 28 | B1->B0 | 3232 2727 | 1 1 | (1 1) (1 1)
5430 11:20:02.536135 0 15 0 | B1->B0 | 2c2c 2323 | 1 0 | (1 0) (1 0)
5431 11:20:02.539746 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5432 11:20:02.546045 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5433 11:20:02.548998 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5434 11:20:02.553295 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5435 11:20:02.558987 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5436 11:20:02.562521 0 15 24 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
5437 11:20:02.565599 0 15 28 | B1->B0 | 2626 3737 | 0 0 | (0 0) (0 0)
5438 11:20:02.572451 1 0 0 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5439 11:20:02.575832 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5440 11:20:02.578881 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5441 11:20:02.585449 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5442 11:20:02.588935 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5443 11:20:02.592167 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5444 11:20:02.598553 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5445 11:20:02.602132 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5446 11:20:02.605157 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5447 11:20:02.612243 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5448 11:20:02.615257 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5449 11:20:02.618437 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5450 11:20:02.624918 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5451 11:20:02.628318 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5452 11:20:02.631687 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5453 11:20:02.638337 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5454 11:20:02.641755 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5455 11:20:02.644873 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5456 11:20:02.651457 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5457 11:20:02.655069 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5458 11:20:02.658069 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5459 11:20:02.664909 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5460 11:20:02.668414 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5461 11:20:02.671953 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5462 11:20:02.677921 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5463 11:20:02.678481 Total UI for P1: 0, mck2ui 16
5464 11:20:02.684706 best dqsien dly found for B0: ( 1, 2, 28)
5465 11:20:02.688176 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5466 11:20:02.691153 Total UI for P1: 0, mck2ui 16
5467 11:20:02.694317 best dqsien dly found for B1: ( 1, 2, 30)
5468 11:20:02.698277 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5469 11:20:02.701711 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5470 11:20:02.702181
5471 11:20:02.704256 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5472 11:20:02.708663 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5473 11:20:02.711258 [Gating] SW calibration Done
5474 11:20:02.711825 ==
5475 11:20:02.714481 Dram Type= 6, Freq= 0, CH_0, rank 1
5476 11:20:02.717631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5477 11:20:02.720936 ==
5478 11:20:02.721502 RX Vref Scan: 0
5479 11:20:02.721880
5480 11:20:02.724204 RX Vref 0 -> 0, step: 1
5481 11:20:02.724708
5482 11:20:02.727617 RX Delay -80 -> 252, step: 8
5483 11:20:02.730978 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5484 11:20:02.733851 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5485 11:20:02.737095 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5486 11:20:02.740652 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5487 11:20:02.743776 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5488 11:20:02.750365 iDelay=208, Bit 5, Center 87 (-16 ~ 191) 208
5489 11:20:02.754049 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5490 11:20:02.757469 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5491 11:20:02.761022 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5492 11:20:02.764098 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5493 11:20:02.770475 iDelay=208, Bit 10, Center 87 (-16 ~ 191) 208
5494 11:20:02.774049 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5495 11:20:02.777630 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5496 11:20:02.780640 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5497 11:20:02.784244 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5498 11:20:02.790385 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5499 11:20:02.790864 ==
5500 11:20:02.793694 Dram Type= 6, Freq= 0, CH_0, rank 1
5501 11:20:02.796795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5502 11:20:02.797380 ==
5503 11:20:02.797762 DQS Delay:
5504 11:20:02.800244 DQS0 = 0, DQS1 = 0
5505 11:20:02.800876 DQM Delay:
5506 11:20:02.803361 DQM0 = 97, DQM1 = 88
5507 11:20:02.803837 DQ Delay:
5508 11:20:02.807308 DQ0 =95, DQ1 =99, DQ2 =95, DQ3 =91
5509 11:20:02.810198 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5510 11:20:02.813924 DQ8 =79, DQ9 =79, DQ10 =87, DQ11 =79
5511 11:20:02.816692 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5512 11:20:02.817333
5513 11:20:02.817724
5514 11:20:02.818071 ==
5515 11:20:02.820209 Dram Type= 6, Freq= 0, CH_0, rank 1
5516 11:20:02.823388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5517 11:20:02.823976 ==
5518 11:20:02.826839
5519 11:20:02.827419
5520 11:20:02.827801 TX Vref Scan disable
5521 11:20:02.829515 == TX Byte 0 ==
5522 11:20:02.832909 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5523 11:20:02.836422 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5524 11:20:02.839830 == TX Byte 1 ==
5525 11:20:02.843151 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5526 11:20:02.846324 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5527 11:20:02.849770 ==
5528 11:20:02.850362 Dram Type= 6, Freq= 0, CH_0, rank 1
5529 11:20:02.856714 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5530 11:20:02.857297 ==
5531 11:20:02.857680
5532 11:20:02.858033
5533 11:20:02.859674 TX Vref Scan disable
5534 11:20:02.860148 == TX Byte 0 ==
5535 11:20:02.866077 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5536 11:20:02.869557 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5537 11:20:02.870035 == TX Byte 1 ==
5538 11:20:02.875826 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5539 11:20:02.879812 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5540 11:20:02.880390
5541 11:20:02.880827 [DATLAT]
5542 11:20:02.883738 Freq=933, CH0 RK1
5543 11:20:02.884318
5544 11:20:02.884750 DATLAT Default: 0xb
5545 11:20:02.885713 0, 0xFFFF, sum = 0
5546 11:20:02.886200 1, 0xFFFF, sum = 0
5547 11:20:02.889491 2, 0xFFFF, sum = 0
5548 11:20:02.890132 3, 0xFFFF, sum = 0
5549 11:20:02.892470 4, 0xFFFF, sum = 0
5550 11:20:02.892975 5, 0xFFFF, sum = 0
5551 11:20:02.896045 6, 0xFFFF, sum = 0
5552 11:20:02.896670 7, 0xFFFF, sum = 0
5553 11:20:02.899073 8, 0xFFFF, sum = 0
5554 11:20:02.902530 9, 0xFFFF, sum = 0
5555 11:20:02.903134 10, 0x0, sum = 1
5556 11:20:02.903531 11, 0x0, sum = 2
5557 11:20:02.905423 12, 0x0, sum = 3
5558 11:20:02.905907 13, 0x0, sum = 4
5559 11:20:02.908956 best_step = 11
5560 11:20:02.909429
5561 11:20:02.909802 ==
5562 11:20:02.912230 Dram Type= 6, Freq= 0, CH_0, rank 1
5563 11:20:02.916550 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5564 11:20:02.917141 ==
5565 11:20:02.919144 RX Vref Scan: 0
5566 11:20:02.919737
5567 11:20:02.922601 RX Vref 0 -> 0, step: 1
5568 11:20:02.923182
5569 11:20:02.923565 RX Delay -61 -> 252, step: 4
5570 11:20:02.930282 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5571 11:20:02.933164 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5572 11:20:02.936886 iDelay=203, Bit 2, Center 88 (-5 ~ 182) 188
5573 11:20:02.939624 iDelay=203, Bit 3, Center 92 (-5 ~ 190) 196
5574 11:20:02.943405 iDelay=203, Bit 4, Center 96 (3 ~ 190) 188
5575 11:20:02.949763 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5576 11:20:02.952578 iDelay=203, Bit 6, Center 104 (7 ~ 202) 196
5577 11:20:02.956063 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5578 11:20:02.959179 iDelay=203, Bit 8, Center 78 (-13 ~ 170) 184
5579 11:20:02.962829 iDelay=203, Bit 9, Center 74 (-17 ~ 166) 184
5580 11:20:02.969327 iDelay=203, Bit 10, Center 86 (-9 ~ 182) 192
5581 11:20:02.972943 iDelay=203, Bit 11, Center 76 (-17 ~ 170) 188
5582 11:20:02.975803 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5583 11:20:02.979132 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5584 11:20:02.982205 iDelay=203, Bit 14, Center 96 (7 ~ 186) 180
5585 11:20:02.988914 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5586 11:20:02.989492 ==
5587 11:20:02.992511 Dram Type= 6, Freq= 0, CH_0, rank 1
5588 11:20:02.995639 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5589 11:20:02.996220 ==
5590 11:20:02.996641 DQS Delay:
5591 11:20:02.998670 DQS0 = 0, DQS1 = 0
5592 11:20:02.999144 DQM Delay:
5593 11:20:03.002445 DQM0 = 94, DQM1 = 85
5594 11:20:03.003027 DQ Delay:
5595 11:20:03.005466 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =92
5596 11:20:03.008895 DQ4 =96, DQ5 =86, DQ6 =104, DQ7 =104
5597 11:20:03.012261 DQ8 =78, DQ9 =74, DQ10 =86, DQ11 =76
5598 11:20:03.015435 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
5599 11:20:03.016012
5600 11:20:03.016387
5601 11:20:03.025746 [DQSOSCAuto] RK1, (LSB)MR18= 0x29f9, (MSB)MR19= 0x504, tDQSOscB0 = 424 ps tDQSOscB1 = 408 ps
5602 11:20:03.026352 CH0 RK1: MR19=504, MR18=29F9
5603 11:20:03.031959 CH0_RK1: MR19=0x504, MR18=0x29F9, DQSOSC=408, MR23=63, INC=65, DEC=43
5604 11:20:03.035050 [RxdqsGatingPostProcess] freq 933
5605 11:20:03.041945 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5606 11:20:03.044921 best DQS0 dly(2T, 0.5T) = (0, 10)
5607 11:20:03.048204 best DQS1 dly(2T, 0.5T) = (0, 11)
5608 11:20:03.051821 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5609 11:20:03.055019 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5610 11:20:03.058327 best DQS0 dly(2T, 0.5T) = (0, 10)
5611 11:20:03.058877 best DQS1 dly(2T, 0.5T) = (0, 10)
5612 11:20:03.061647 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5613 11:20:03.065162 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5614 11:20:03.068051 Pre-setting of DQS Precalculation
5615 11:20:03.074415 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5616 11:20:03.074892 ==
5617 11:20:03.078121 Dram Type= 6, Freq= 0, CH_1, rank 0
5618 11:20:03.081169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5619 11:20:03.081647 ==
5620 11:20:03.087956 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5621 11:20:03.094731 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5622 11:20:03.098333 [CA 0] Center 36 (6~67) winsize 62
5623 11:20:03.101207 [CA 1] Center 36 (6~67) winsize 62
5624 11:20:03.104361 [CA 2] Center 34 (4~65) winsize 62
5625 11:20:03.107446 [CA 3] Center 33 (3~64) winsize 62
5626 11:20:03.110843 [CA 4] Center 34 (4~64) winsize 61
5627 11:20:03.114222 [CA 5] Center 33 (3~64) winsize 62
5628 11:20:03.114728
5629 11:20:03.117692 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5630 11:20:03.118260
5631 11:20:03.120533 [CATrainingPosCal] consider 1 rank data
5632 11:20:03.124558 u2DelayCellTimex100 = 270/100 ps
5633 11:20:03.127708 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5634 11:20:03.131277 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5635 11:20:03.133939 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5636 11:20:03.137578 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5637 11:20:03.140677 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5638 11:20:03.143917 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5639 11:20:03.144383
5640 11:20:03.150892 CA PerBit enable=1, Macro0, CA PI delay=33
5641 11:20:03.151460
5642 11:20:03.153977 [CBTSetCACLKResult] CA Dly = 33
5643 11:20:03.154449 CS Dly: 5 (0~36)
5644 11:20:03.154825 ==
5645 11:20:03.156900 Dram Type= 6, Freq= 0, CH_1, rank 1
5646 11:20:03.160092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5647 11:20:03.160589 ==
5648 11:20:03.167032 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5649 11:20:03.173564 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5650 11:20:03.177090 [CA 0] Center 36 (6~67) winsize 62
5651 11:20:03.180882 [CA 1] Center 37 (7~67) winsize 61
5652 11:20:03.183942 [CA 2] Center 34 (4~65) winsize 62
5653 11:20:03.186765 [CA 3] Center 33 (3~64) winsize 62
5654 11:20:03.190352 [CA 4] Center 34 (3~65) winsize 63
5655 11:20:03.193660 [CA 5] Center 33 (3~64) winsize 62
5656 11:20:03.194233
5657 11:20:03.197063 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5658 11:20:03.197643
5659 11:20:03.200129 [CATrainingPosCal] consider 2 rank data
5660 11:20:03.203018 u2DelayCellTimex100 = 270/100 ps
5661 11:20:03.207268 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5662 11:20:03.210631 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5663 11:20:03.213371 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5664 11:20:03.217169 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5665 11:20:03.223291 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5666 11:20:03.226669 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5667 11:20:03.227149
5668 11:20:03.230079 CA PerBit enable=1, Macro0, CA PI delay=33
5669 11:20:03.230651
5670 11:20:03.233703 [CBTSetCACLKResult] CA Dly = 33
5671 11:20:03.234287 CS Dly: 6 (0~39)
5672 11:20:03.234676
5673 11:20:03.236681 ----->DramcWriteLeveling(PI) begin...
5674 11:20:03.237251 ==
5675 11:20:03.239730 Dram Type= 6, Freq= 0, CH_1, rank 0
5676 11:20:03.246332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5677 11:20:03.246910 ==
5678 11:20:03.249473 Write leveling (Byte 0): 25 => 25
5679 11:20:03.252788 Write leveling (Byte 1): 27 => 27
5680 11:20:03.253271 DramcWriteLeveling(PI) end<-----
5681 11:20:03.253753
5682 11:20:03.256859 ==
5683 11:20:03.259506 Dram Type= 6, Freq= 0, CH_1, rank 0
5684 11:20:03.262651 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5685 11:20:03.263121 ==
5686 11:20:03.266432 [Gating] SW mode calibration
5687 11:20:03.272726 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5688 11:20:03.276402 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5689 11:20:03.283186 0 14 0 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
5690 11:20:03.285986 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5691 11:20:03.289398 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5692 11:20:03.295905 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5693 11:20:03.299804 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5694 11:20:03.303331 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5695 11:20:03.309314 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5696 11:20:03.312666 0 14 28 | B1->B0 | 2f2f 2929 | 1 0 | (1 0) (1 0)
5697 11:20:03.315756 0 15 0 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
5698 11:20:03.322329 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5699 11:20:03.325469 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5700 11:20:03.329251 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5701 11:20:03.336171 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5702 11:20:03.338779 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5703 11:20:03.342748 0 15 24 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5704 11:20:03.348826 0 15 28 | B1->B0 | 3a3a 3b3b | 1 0 | (1 1) (1 1)
5705 11:20:03.351977 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5706 11:20:03.355344 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5707 11:20:03.361833 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5708 11:20:03.365331 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5709 11:20:03.369123 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5710 11:20:03.375074 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5711 11:20:03.378702 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5712 11:20:03.381734 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5713 11:20:03.388175 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5714 11:20:03.391840 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5715 11:20:03.395146 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5716 11:20:03.401640 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5717 11:20:03.404737 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5718 11:20:03.408942 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5719 11:20:03.415183 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5720 11:20:03.418425 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5721 11:20:03.421334 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5722 11:20:03.428064 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5723 11:20:03.431024 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5724 11:20:03.434488 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5725 11:20:03.441151 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5726 11:20:03.444632 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5727 11:20:03.448163 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5728 11:20:03.454272 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5729 11:20:03.454828 Total UI for P1: 0, mck2ui 16
5730 11:20:03.461225 best dqsien dly found for B0: ( 1, 2, 22)
5731 11:20:03.464257 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5732 11:20:03.467449 Total UI for P1: 0, mck2ui 16
5733 11:20:03.470868 best dqsien dly found for B1: ( 1, 2, 26)
5734 11:20:03.474027 best DQS0 dly(MCK, UI, PI) = (1, 2, 22)
5735 11:20:03.477403 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5736 11:20:03.477888
5737 11:20:03.480888 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 22)
5738 11:20:03.483829 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5739 11:20:03.487633 [Gating] SW calibration Done
5740 11:20:03.488209 ==
5741 11:20:03.490372 Dram Type= 6, Freq= 0, CH_1, rank 0
5742 11:20:03.497222 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5743 11:20:03.497794 ==
5744 11:20:03.498175 RX Vref Scan: 0
5745 11:20:03.498568
5746 11:20:03.500490 RX Vref 0 -> 0, step: 1
5747 11:20:03.501030
5748 11:20:03.503813 RX Delay -80 -> 252, step: 8
5749 11:20:03.507029 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5750 11:20:03.510432 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5751 11:20:03.513730 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5752 11:20:03.516877 iDelay=208, Bit 3, Center 103 (8 ~ 199) 192
5753 11:20:03.520773 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5754 11:20:03.526866 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5755 11:20:03.530800 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5756 11:20:03.533625 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5757 11:20:03.536952 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5758 11:20:03.540669 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5759 11:20:03.546936 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5760 11:20:03.550118 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5761 11:20:03.553242 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5762 11:20:03.556780 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5763 11:20:03.560056 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5764 11:20:03.566597 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5765 11:20:03.567202 ==
5766 11:20:03.569843 Dram Type= 6, Freq= 0, CH_1, rank 0
5767 11:20:03.573371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5768 11:20:03.573843 ==
5769 11:20:03.574219 DQS Delay:
5770 11:20:03.576409 DQS0 = 0, DQS1 = 0
5771 11:20:03.577050 DQM Delay:
5772 11:20:03.580183 DQM0 = 102, DQM1 = 91
5773 11:20:03.580837 DQ Delay:
5774 11:20:03.582957 DQ0 =107, DQ1 =99, DQ2 =95, DQ3 =103
5775 11:20:03.586277 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =99
5776 11:20:03.589511 DQ8 =75, DQ9 =83, DQ10 =91, DQ11 =79
5777 11:20:03.592984 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =103
5778 11:20:03.593483
5779 11:20:03.593863
5780 11:20:03.594206 ==
5781 11:20:03.596409 Dram Type= 6, Freq= 0, CH_1, rank 0
5782 11:20:03.602818 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5783 11:20:03.603403 ==
5784 11:20:03.603778
5785 11:20:03.604116
5786 11:20:03.604438 TX Vref Scan disable
5787 11:20:03.606531 == TX Byte 0 ==
5788 11:20:03.609834 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5789 11:20:03.616160 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5790 11:20:03.616765 == TX Byte 1 ==
5791 11:20:03.619598 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5792 11:20:03.623262 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5793 11:20:03.625955 ==
5794 11:20:03.629700 Dram Type= 6, Freq= 0, CH_1, rank 0
5795 11:20:03.633247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5796 11:20:03.633815 ==
5797 11:20:03.634187
5798 11:20:03.634528
5799 11:20:03.636691 TX Vref Scan disable
5800 11:20:03.637156 == TX Byte 0 ==
5801 11:20:03.642730 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5802 11:20:03.645996 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5803 11:20:03.646469 == TX Byte 1 ==
5804 11:20:03.652434 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5805 11:20:03.656288 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5806 11:20:03.656909
5807 11:20:03.657289 [DATLAT]
5808 11:20:03.659035 Freq=933, CH1 RK0
5809 11:20:03.659502
5810 11:20:03.659877 DATLAT Default: 0xd
5811 11:20:03.662477 0, 0xFFFF, sum = 0
5812 11:20:03.663057 1, 0xFFFF, sum = 0
5813 11:20:03.665628 2, 0xFFFF, sum = 0
5814 11:20:03.669089 3, 0xFFFF, sum = 0
5815 11:20:03.669562 4, 0xFFFF, sum = 0
5816 11:20:03.672512 5, 0xFFFF, sum = 0
5817 11:20:03.673012 6, 0xFFFF, sum = 0
5818 11:20:03.675667 7, 0xFFFF, sum = 0
5819 11:20:03.676156 8, 0xFFFF, sum = 0
5820 11:20:03.679169 9, 0xFFFF, sum = 0
5821 11:20:03.679743 10, 0x0, sum = 1
5822 11:20:03.681935 11, 0x0, sum = 2
5823 11:20:03.682410 12, 0x0, sum = 3
5824 11:20:03.685334 13, 0x0, sum = 4
5825 11:20:03.685908 best_step = 11
5826 11:20:03.686288
5827 11:20:03.686636 ==
5828 11:20:03.689040 Dram Type= 6, Freq= 0, CH_1, rank 0
5829 11:20:03.692117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5830 11:20:03.692614 ==
5831 11:20:03.695612 RX Vref Scan: 1
5832 11:20:03.696186
5833 11:20:03.699118 RX Vref 0 -> 0, step: 1
5834 11:20:03.699693
5835 11:20:03.700070 RX Delay -69 -> 252, step: 4
5836 11:20:03.700425
5837 11:20:03.702550 Set Vref, RX VrefLevel [Byte0]: 48
5838 11:20:03.705501 [Byte1]: 53
5839 11:20:03.710317
5840 11:20:03.710881 Final RX Vref Byte 0 = 48 to rank0
5841 11:20:03.713446 Final RX Vref Byte 1 = 53 to rank0
5842 11:20:03.717038 Final RX Vref Byte 0 = 48 to rank1
5843 11:20:03.719958 Final RX Vref Byte 1 = 53 to rank1==
5844 11:20:03.723410 Dram Type= 6, Freq= 0, CH_1, rank 0
5845 11:20:03.729922 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5846 11:20:03.730501 ==
5847 11:20:03.730878 DQS Delay:
5848 11:20:03.733048 DQS0 = 0, DQS1 = 0
5849 11:20:03.733524 DQM Delay:
5850 11:20:03.733904 DQM0 = 101, DQM1 = 93
5851 11:20:03.736831 DQ Delay:
5852 11:20:03.740291 DQ0 =104, DQ1 =96, DQ2 =92, DQ3 =98
5853 11:20:03.743163 DQ4 =98, DQ5 =112, DQ6 =110, DQ7 =98
5854 11:20:03.746875 DQ8 =82, DQ9 =86, DQ10 =94, DQ11 =84
5855 11:20:03.750494 DQ12 =100, DQ13 =100, DQ14 =100, DQ15 =102
5856 11:20:03.750976
5857 11:20:03.751351
5858 11:20:03.756362 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a09, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 413 ps
5859 11:20:03.759306 CH1 RK0: MR19=505, MR18=1A09
5860 11:20:03.766095 CH1_RK0: MR19=0x505, MR18=0x1A09, DQSOSC=413, MR23=63, INC=63, DEC=42
5861 11:20:03.766570
5862 11:20:03.769288 ----->DramcWriteLeveling(PI) begin...
5863 11:20:03.769766 ==
5864 11:20:03.772870 Dram Type= 6, Freq= 0, CH_1, rank 1
5865 11:20:03.776164 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5866 11:20:03.779283 ==
5867 11:20:03.779881 Write leveling (Byte 0): 26 => 26
5868 11:20:03.783184 Write leveling (Byte 1): 28 => 28
5869 11:20:03.785877 DramcWriteLeveling(PI) end<-----
5870 11:20:03.786347
5871 11:20:03.786717 ==
5872 11:20:03.789443 Dram Type= 6, Freq= 0, CH_1, rank 1
5873 11:20:03.796437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5874 11:20:03.797044 ==
5875 11:20:03.799314 [Gating] SW mode calibration
5876 11:20:03.805617 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5877 11:20:03.808909 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5878 11:20:03.815415 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5879 11:20:03.819213 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5880 11:20:03.822696 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5881 11:20:03.829133 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5882 11:20:03.832356 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5883 11:20:03.835583 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5884 11:20:03.841942 0 14 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5885 11:20:03.845579 0 14 28 | B1->B0 | 2929 2f2f | 0 1 | (0 0) (1 0)
5886 11:20:03.848658 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5887 11:20:03.855137 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5888 11:20:03.859087 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5889 11:20:03.862450 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5890 11:20:03.868279 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5891 11:20:03.871641 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5892 11:20:03.874927 0 15 24 | B1->B0 | 2f2f 2626 | 0 1 | (0 0) (0 0)
5893 11:20:03.881924 0 15 28 | B1->B0 | 3939 3232 | 0 0 | (1 1) (1 1)
5894 11:20:03.884928 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5895 11:20:03.888333 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5896 11:20:03.894715 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5897 11:20:03.898043 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5898 11:20:03.901257 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5899 11:20:03.907924 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5900 11:20:03.911250 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5901 11:20:03.914144 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5902 11:20:03.921384 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5903 11:20:03.925395 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5904 11:20:03.927375 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5905 11:20:03.934418 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5906 11:20:03.937422 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5907 11:20:03.941306 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5908 11:20:03.947978 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5909 11:20:03.951115 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5910 11:20:03.953928 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5911 11:20:03.960774 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5912 11:20:03.964069 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5913 11:20:03.967997 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5914 11:20:03.974323 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5915 11:20:03.976855 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5916 11:20:03.980694 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5917 11:20:03.987007 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5918 11:20:03.990280 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5919 11:20:03.993714 Total UI for P1: 0, mck2ui 16
5920 11:20:03.997012 best dqsien dly found for B0: ( 1, 2, 28)
5921 11:20:04.000771 Total UI for P1: 0, mck2ui 16
5922 11:20:04.004112 best dqsien dly found for B1: ( 1, 2, 24)
5923 11:20:04.007343 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5924 11:20:04.010111 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5925 11:20:04.010583
5926 11:20:04.013650 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5927 11:20:04.016674 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5928 11:20:04.020425 [Gating] SW calibration Done
5929 11:20:04.021033 ==
5930 11:20:04.023771 Dram Type= 6, Freq= 0, CH_1, rank 1
5931 11:20:04.027215 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5932 11:20:04.027861 ==
5933 11:20:04.030187 RX Vref Scan: 0
5934 11:20:04.030657
5935 11:20:04.033730 RX Vref 0 -> 0, step: 1
5936 11:20:04.034334
5937 11:20:04.034715 RX Delay -80 -> 252, step: 8
5938 11:20:04.040636 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5939 11:20:04.043833 iDelay=208, Bit 1, Center 91 (0 ~ 183) 184
5940 11:20:04.046795 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5941 11:20:04.049932 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5942 11:20:04.053173 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5943 11:20:04.057017 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5944 11:20:04.063281 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5945 11:20:04.066820 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5946 11:20:04.069490 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5947 11:20:04.072759 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5948 11:20:04.076144 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5949 11:20:04.083430 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5950 11:20:04.087049 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5951 11:20:04.089276 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5952 11:20:04.092654 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5953 11:20:04.096083 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5954 11:20:04.096589 ==
5955 11:20:04.099352 Dram Type= 6, Freq= 0, CH_1, rank 1
5956 11:20:04.106147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5957 11:20:04.106746 ==
5958 11:20:04.107136 DQS Delay:
5959 11:20:04.109143 DQS0 = 0, DQS1 = 0
5960 11:20:04.109621 DQM Delay:
5961 11:20:04.113075 DQM0 = 99, DQM1 = 90
5962 11:20:04.113659 DQ Delay:
5963 11:20:04.115539 DQ0 =103, DQ1 =91, DQ2 =91, DQ3 =99
5964 11:20:04.119330 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5965 11:20:04.122203 DQ8 =79, DQ9 =79, DQ10 =91, DQ11 =79
5966 11:20:04.125771 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5967 11:20:04.126351
5968 11:20:04.126731
5969 11:20:04.127079 ==
5970 11:20:04.128947 Dram Type= 6, Freq= 0, CH_1, rank 1
5971 11:20:04.133092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5972 11:20:04.133678 ==
5973 11:20:04.134061
5974 11:20:04.135728
5975 11:20:04.136308 TX Vref Scan disable
5976 11:20:04.138764 == TX Byte 0 ==
5977 11:20:04.142087 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5978 11:20:04.146047 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5979 11:20:04.149866 == TX Byte 1 ==
5980 11:20:04.151920 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5981 11:20:04.155480 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5982 11:20:04.156058 ==
5983 11:20:04.158814 Dram Type= 6, Freq= 0, CH_1, rank 1
5984 11:20:04.165300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5985 11:20:04.165872 ==
5986 11:20:04.166249
5987 11:20:04.166593
5988 11:20:04.166925 TX Vref Scan disable
5989 11:20:04.169567 == TX Byte 0 ==
5990 11:20:04.172746 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5991 11:20:04.179444 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5992 11:20:04.180093 == TX Byte 1 ==
5993 11:20:04.182794 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5994 11:20:04.189280 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5995 11:20:04.189814
5996 11:20:04.190191 [DATLAT]
5997 11:20:04.190542 Freq=933, CH1 RK1
5998 11:20:04.190883
5999 11:20:04.192446 DATLAT Default: 0xb
6000 11:20:04.195709 0, 0xFFFF, sum = 0
6001 11:20:04.196190 1, 0xFFFF, sum = 0
6002 11:20:04.198825 2, 0xFFFF, sum = 0
6003 11:20:04.199399 3, 0xFFFF, sum = 0
6004 11:20:04.202016 4, 0xFFFF, sum = 0
6005 11:20:04.202496 5, 0xFFFF, sum = 0
6006 11:20:04.205300 6, 0xFFFF, sum = 0
6007 11:20:04.205878 7, 0xFFFF, sum = 0
6008 11:20:04.209131 8, 0xFFFF, sum = 0
6009 11:20:04.209712 9, 0xFFFF, sum = 0
6010 11:20:04.212104 10, 0x0, sum = 1
6011 11:20:04.212701 11, 0x0, sum = 2
6012 11:20:04.215394 12, 0x0, sum = 3
6013 11:20:04.215976 13, 0x0, sum = 4
6014 11:20:04.218755 best_step = 11
6015 11:20:04.219321
6016 11:20:04.219698 ==
6017 11:20:04.222630 Dram Type= 6, Freq= 0, CH_1, rank 1
6018 11:20:04.225246 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6019 11:20:04.225868 ==
6020 11:20:04.228544 RX Vref Scan: 0
6021 11:20:04.229016
6022 11:20:04.229388 RX Vref 0 -> 0, step: 1
6023 11:20:04.229742
6024 11:20:04.231928 RX Delay -61 -> 252, step: 4
6025 11:20:04.238738 iDelay=207, Bit 0, Center 104 (15 ~ 194) 180
6026 11:20:04.241753 iDelay=207, Bit 1, Center 94 (7 ~ 182) 176
6027 11:20:04.245278 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
6028 11:20:04.248722 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
6029 11:20:04.252065 iDelay=207, Bit 4, Center 98 (7 ~ 190) 184
6030 11:20:04.258332 iDelay=207, Bit 5, Center 112 (27 ~ 198) 172
6031 11:20:04.261523 iDelay=207, Bit 6, Center 116 (27 ~ 206) 180
6032 11:20:04.265255 iDelay=207, Bit 7, Center 98 (7 ~ 190) 184
6033 11:20:04.268005 iDelay=207, Bit 8, Center 80 (-9 ~ 170) 180
6034 11:20:04.271384 iDelay=207, Bit 9, Center 82 (-9 ~ 174) 184
6035 11:20:04.274730 iDelay=207, Bit 10, Center 94 (3 ~ 186) 184
6036 11:20:04.281814 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
6037 11:20:04.284677 iDelay=207, Bit 12, Center 102 (11 ~ 194) 184
6038 11:20:04.287529 iDelay=207, Bit 13, Center 102 (11 ~ 194) 184
6039 11:20:04.291757 iDelay=207, Bit 14, Center 100 (11 ~ 190) 180
6040 11:20:04.297588 iDelay=207, Bit 15, Center 102 (11 ~ 194) 184
6041 11:20:04.298061 ==
6042 11:20:04.301065 Dram Type= 6, Freq= 0, CH_1, rank 1
6043 11:20:04.304430 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6044 11:20:04.305035 ==
6045 11:20:04.305415 DQS Delay:
6046 11:20:04.307703 DQS0 = 0, DQS1 = 0
6047 11:20:04.308172 DQM Delay:
6048 11:20:04.310657 DQM0 = 101, DQM1 = 93
6049 11:20:04.311129 DQ Delay:
6050 11:20:04.314238 DQ0 =104, DQ1 =94, DQ2 =90, DQ3 =98
6051 11:20:04.317384 DQ4 =98, DQ5 =112, DQ6 =116, DQ7 =98
6052 11:20:04.320882 DQ8 =80, DQ9 =82, DQ10 =94, DQ11 =84
6053 11:20:04.324789 DQ12 =102, DQ13 =102, DQ14 =100, DQ15 =102
6054 11:20:04.325359
6055 11:20:04.325732
6056 11:20:04.335087 [DQSOSCAuto] RK1, (LSB)MR18= 0x701, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 419 ps
6057 11:20:04.335657 CH1 RK1: MR19=505, MR18=701
6058 11:20:04.340993 CH1_RK1: MR19=0x505, MR18=0x701, DQSOSC=419, MR23=63, INC=61, DEC=41
6059 11:20:04.344122 [RxdqsGatingPostProcess] freq 933
6060 11:20:04.350366 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6061 11:20:04.354037 best DQS0 dly(2T, 0.5T) = (0, 10)
6062 11:20:04.357332 best DQS1 dly(2T, 0.5T) = (0, 10)
6063 11:20:04.360636 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6064 11:20:04.363583 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6065 11:20:04.367032 best DQS0 dly(2T, 0.5T) = (0, 10)
6066 11:20:04.367514 best DQS1 dly(2T, 0.5T) = (0, 10)
6067 11:20:04.370333 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6068 11:20:04.373754 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6069 11:20:04.377054 Pre-setting of DQS Precalculation
6070 11:20:04.383399 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6071 11:20:04.389870 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6072 11:20:04.397169 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6073 11:20:04.397750
6074 11:20:04.398126
6075 11:20:04.399915 [Calibration Summary] 1866 Mbps
6076 11:20:04.403048 CH 0, Rank 0
6077 11:20:04.403519 SW Impedance : PASS
6078 11:20:04.406467 DUTY Scan : NO K
6079 11:20:04.409874 ZQ Calibration : PASS
6080 11:20:04.410345 Jitter Meter : NO K
6081 11:20:04.412912 CBT Training : PASS
6082 11:20:04.416315 Write leveling : PASS
6083 11:20:04.416930 RX DQS gating : PASS
6084 11:20:04.419871 RX DQ/DQS(RDDQC) : PASS
6085 11:20:04.420457 TX DQ/DQS : PASS
6086 11:20:04.423322 RX DATLAT : PASS
6087 11:20:04.426442 RX DQ/DQS(Engine): PASS
6088 11:20:04.427021 TX OE : NO K
6089 11:20:04.429592 All Pass.
6090 11:20:04.430063
6091 11:20:04.430436 CH 0, Rank 1
6092 11:20:04.433077 SW Impedance : PASS
6093 11:20:04.433651 DUTY Scan : NO K
6094 11:20:04.436267 ZQ Calibration : PASS
6095 11:20:04.439203 Jitter Meter : NO K
6096 11:20:04.439682 CBT Training : PASS
6097 11:20:04.442441 Write leveling : PASS
6098 11:20:04.446406 RX DQS gating : PASS
6099 11:20:04.446976 RX DQ/DQS(RDDQC) : PASS
6100 11:20:04.449222 TX DQ/DQS : PASS
6101 11:20:04.452466 RX DATLAT : PASS
6102 11:20:04.453208 RX DQ/DQS(Engine): PASS
6103 11:20:04.455710 TX OE : NO K
6104 11:20:04.456200 All Pass.
6105 11:20:04.456610
6106 11:20:04.458918 CH 1, Rank 0
6107 11:20:04.459393 SW Impedance : PASS
6108 11:20:04.462455 DUTY Scan : NO K
6109 11:20:04.466207 ZQ Calibration : PASS
6110 11:20:04.466780 Jitter Meter : NO K
6111 11:20:04.468655 CBT Training : PASS
6112 11:20:04.472481 Write leveling : PASS
6113 11:20:04.473095 RX DQS gating : PASS
6114 11:20:04.475379 RX DQ/DQS(RDDQC) : PASS
6115 11:20:04.478636 TX DQ/DQS : PASS
6116 11:20:04.479107 RX DATLAT : PASS
6117 11:20:04.481813 RX DQ/DQS(Engine): PASS
6118 11:20:04.485706 TX OE : NO K
6119 11:20:04.486278 All Pass.
6120 11:20:04.486655
6121 11:20:04.486998 CH 1, Rank 1
6122 11:20:04.488599 SW Impedance : PASS
6123 11:20:04.492234 DUTY Scan : NO K
6124 11:20:04.492852 ZQ Calibration : PASS
6125 11:20:04.495767 Jitter Meter : NO K
6126 11:20:04.498608 CBT Training : PASS
6127 11:20:04.499181 Write leveling : PASS
6128 11:20:04.501852 RX DQS gating : PASS
6129 11:20:04.505329 RX DQ/DQS(RDDQC) : PASS
6130 11:20:04.505909 TX DQ/DQS : PASS
6131 11:20:04.508204 RX DATLAT : PASS
6132 11:20:04.508695 RX DQ/DQS(Engine): PASS
6133 11:20:04.511895 TX OE : NO K
6134 11:20:04.512504 All Pass.
6135 11:20:04.512920
6136 11:20:04.515225 DramC Write-DBI off
6137 11:20:04.518035 PER_BANK_REFRESH: Hybrid Mode
6138 11:20:04.518511 TX_TRACKING: ON
6139 11:20:04.528261 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6140 11:20:04.531719 [FAST_K] Save calibration result to emmc
6141 11:20:04.534886 dramc_set_vcore_voltage set vcore to 650000
6142 11:20:04.538441 Read voltage for 400, 6
6143 11:20:04.539009 Vio18 = 0
6144 11:20:04.541726 Vcore = 650000
6145 11:20:04.542288 Vdram = 0
6146 11:20:04.542667 Vddq = 0
6147 11:20:04.543010 Vmddr = 0
6148 11:20:04.548458 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6149 11:20:04.554429 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6150 11:20:04.554999 MEM_TYPE=3, freq_sel=20
6151 11:20:04.557849 sv_algorithm_assistance_LP4_800
6152 11:20:04.561309 ============ PULL DRAM RESETB DOWN ============
6153 11:20:04.568105 ========== PULL DRAM RESETB DOWN end =========
6154 11:20:04.571103 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6155 11:20:04.574300 ===================================
6156 11:20:04.577688 LPDDR4 DRAM CONFIGURATION
6157 11:20:04.581031 ===================================
6158 11:20:04.581604 EX_ROW_EN[0] = 0x0
6159 11:20:04.584823 EX_ROW_EN[1] = 0x0
6160 11:20:04.587958 LP4Y_EN = 0x0
6161 11:20:04.588591 WORK_FSP = 0x0
6162 11:20:04.591308 WL = 0x2
6163 11:20:04.591774 RL = 0x2
6164 11:20:04.593854 BL = 0x2
6165 11:20:04.594387 RPST = 0x0
6166 11:20:04.597301 RD_PRE = 0x0
6167 11:20:04.597877 WR_PRE = 0x1
6168 11:20:04.601061 WR_PST = 0x0
6169 11:20:04.601631 DBI_WR = 0x0
6170 11:20:04.604049 DBI_RD = 0x0
6171 11:20:04.604647 OTF = 0x1
6172 11:20:04.607613 ===================================
6173 11:20:04.611054 ===================================
6174 11:20:04.614610 ANA top config
6175 11:20:04.618090 ===================================
6176 11:20:04.618745 DLL_ASYNC_EN = 0
6177 11:20:04.620718 ALL_SLAVE_EN = 1
6178 11:20:04.624013 NEW_RANK_MODE = 1
6179 11:20:04.627123 DLL_IDLE_MODE = 1
6180 11:20:04.630298 LP45_APHY_COMB_EN = 1
6181 11:20:04.630783 TX_ODT_DIS = 1
6182 11:20:04.634494 NEW_8X_MODE = 1
6183 11:20:04.637085 ===================================
6184 11:20:04.640603 ===================================
6185 11:20:04.643729 data_rate = 800
6186 11:20:04.647275 CKR = 1
6187 11:20:04.650488 DQ_P2S_RATIO = 4
6188 11:20:04.654101 ===================================
6189 11:20:04.657333 CA_P2S_RATIO = 4
6190 11:20:04.657903 DQ_CA_OPEN = 0
6191 11:20:04.660108 DQ_SEMI_OPEN = 1
6192 11:20:04.663418 CA_SEMI_OPEN = 1
6193 11:20:04.667078 CA_FULL_RATE = 0
6194 11:20:04.670184 DQ_CKDIV4_EN = 0
6195 11:20:04.673270 CA_CKDIV4_EN = 1
6196 11:20:04.673737 CA_PREDIV_EN = 0
6197 11:20:04.676850 PH8_DLY = 0
6198 11:20:04.680175 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6199 11:20:04.683384 DQ_AAMCK_DIV = 0
6200 11:20:04.686770 CA_AAMCK_DIV = 0
6201 11:20:04.689891 CA_ADMCK_DIV = 4
6202 11:20:04.690454 DQ_TRACK_CA_EN = 0
6203 11:20:04.693078 CA_PICK = 800
6204 11:20:04.696194 CA_MCKIO = 400
6205 11:20:04.699636 MCKIO_SEMI = 400
6206 11:20:04.702628 PLL_FREQ = 3016
6207 11:20:04.705894 DQ_UI_PI_RATIO = 32
6208 11:20:04.709184 CA_UI_PI_RATIO = 32
6209 11:20:04.712878 ===================================
6210 11:20:04.716358 ===================================
6211 11:20:04.719463 memory_type:LPDDR4
6212 11:20:04.720031 GP_NUM : 10
6213 11:20:04.722629 SRAM_EN : 1
6214 11:20:04.723205 MD32_EN : 0
6215 11:20:04.725930 ===================================
6216 11:20:04.728942 [ANA_INIT] >>>>>>>>>>>>>>
6217 11:20:04.732182 <<<<<< [CONFIGURE PHASE]: ANA_TX
6218 11:20:04.735647 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6219 11:20:04.739048 ===================================
6220 11:20:04.741996 data_rate = 800,PCW = 0X7400
6221 11:20:04.745532 ===================================
6222 11:20:04.748672 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6223 11:20:04.755227 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6224 11:20:04.765471 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6225 11:20:04.768571 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6226 11:20:04.771683 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6227 11:20:04.775071 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6228 11:20:04.778711 [ANA_INIT] flow start
6229 11:20:04.781878 [ANA_INIT] PLL >>>>>>>>
6230 11:20:04.782352 [ANA_INIT] PLL <<<<<<<<
6231 11:20:04.784909 [ANA_INIT] MIDPI >>>>>>>>
6232 11:20:04.788617 [ANA_INIT] MIDPI <<<<<<<<
6233 11:20:04.792120 [ANA_INIT] DLL >>>>>>>>
6234 11:20:04.792772 [ANA_INIT] flow end
6235 11:20:04.795047 ============ LP4 DIFF to SE enter ============
6236 11:20:04.801678 ============ LP4 DIFF to SE exit ============
6237 11:20:04.802252 [ANA_INIT] <<<<<<<<<<<<<
6238 11:20:04.804957 [Flow] Enable top DCM control >>>>>
6239 11:20:04.808023 [Flow] Enable top DCM control <<<<<
6240 11:20:04.811287 Enable DLL master slave shuffle
6241 11:20:04.817912 ==============================================================
6242 11:20:04.821451 Gating Mode config
6243 11:20:04.824683 ==============================================================
6244 11:20:04.827953 Config description:
6245 11:20:04.837611 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6246 11:20:04.844394 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6247 11:20:04.847680 SELPH_MODE 0: By rank 1: By Phase
6248 11:20:04.854487 ==============================================================
6249 11:20:04.857319 GAT_TRACK_EN = 0
6250 11:20:04.860951 RX_GATING_MODE = 2
6251 11:20:04.864044 RX_GATING_TRACK_MODE = 2
6252 11:20:04.867298 SELPH_MODE = 1
6253 11:20:04.867892 PICG_EARLY_EN = 1
6254 11:20:04.871122 VALID_LAT_VALUE = 1
6255 11:20:04.877724 ==============================================================
6256 11:20:04.881027 Enter into Gating configuration >>>>
6257 11:20:04.883708 Exit from Gating configuration <<<<
6258 11:20:04.887480 Enter into DVFS_PRE_config >>>>>
6259 11:20:04.896983 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6260 11:20:04.900451 Exit from DVFS_PRE_config <<<<<
6261 11:20:04.904005 Enter into PICG configuration >>>>
6262 11:20:04.906629 Exit from PICG configuration <<<<
6263 11:20:04.910625 [RX_INPUT] configuration >>>>>
6264 11:20:04.914043 [RX_INPUT] configuration <<<<<
6265 11:20:04.920009 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6266 11:20:04.923652 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6267 11:20:04.929984 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6268 11:20:04.936883 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6269 11:20:04.943813 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6270 11:20:04.949897 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6271 11:20:04.953089 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6272 11:20:04.956355 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6273 11:20:04.959768 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6274 11:20:04.966288 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6275 11:20:04.969757 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6276 11:20:04.972765 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6277 11:20:04.976570 ===================================
6278 11:20:04.979209 LPDDR4 DRAM CONFIGURATION
6279 11:20:04.982895 ===================================
6280 11:20:04.983371 EX_ROW_EN[0] = 0x0
6281 11:20:04.986284 EX_ROW_EN[1] = 0x0
6282 11:20:04.989093 LP4Y_EN = 0x0
6283 11:20:04.989573 WORK_FSP = 0x0
6284 11:20:04.992883 WL = 0x2
6285 11:20:04.993463 RL = 0x2
6286 11:20:04.995836 BL = 0x2
6287 11:20:04.996328 RPST = 0x0
6288 11:20:04.999575 RD_PRE = 0x0
6289 11:20:05.000157 WR_PRE = 0x1
6290 11:20:05.002434 WR_PST = 0x0
6291 11:20:05.002936 DBI_WR = 0x0
6292 11:20:05.005891 DBI_RD = 0x0
6293 11:20:05.006473 OTF = 0x1
6294 11:20:05.009056 ===================================
6295 11:20:05.012926 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6296 11:20:05.019124 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6297 11:20:05.023223 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6298 11:20:05.026403 ===================================
6299 11:20:05.029180 LPDDR4 DRAM CONFIGURATION
6300 11:20:05.033185 ===================================
6301 11:20:05.033770 EX_ROW_EN[0] = 0x10
6302 11:20:05.036443 EX_ROW_EN[1] = 0x0
6303 11:20:05.039528 LP4Y_EN = 0x0
6304 11:20:05.040258 WORK_FSP = 0x0
6305 11:20:05.042147 WL = 0x2
6306 11:20:05.042620 RL = 0x2
6307 11:20:05.045546 BL = 0x2
6308 11:20:05.046128 RPST = 0x0
6309 11:20:05.049549 RD_PRE = 0x0
6310 11:20:05.050131 WR_PRE = 0x1
6311 11:20:05.052151 WR_PST = 0x0
6312 11:20:05.052656 DBI_WR = 0x0
6313 11:20:05.055808 DBI_RD = 0x0
6314 11:20:05.056313 OTF = 0x1
6315 11:20:05.058591 ===================================
6316 11:20:05.065207 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6317 11:20:05.069746 nWR fixed to 30
6318 11:20:05.072957 [ModeRegInit_LP4] CH0 RK0
6319 11:20:05.073427 [ModeRegInit_LP4] CH0 RK1
6320 11:20:05.075960 [ModeRegInit_LP4] CH1 RK0
6321 11:20:05.079456 [ModeRegInit_LP4] CH1 RK1
6322 11:20:05.080041 match AC timing 19
6323 11:20:05.086869 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6324 11:20:05.089879 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6325 11:20:05.092744 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6326 11:20:05.099459 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6327 11:20:05.102907 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6328 11:20:05.103525 ==
6329 11:20:05.106073 Dram Type= 6, Freq= 0, CH_0, rank 0
6330 11:20:05.109038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6331 11:20:05.112475 ==
6332 11:20:05.115844 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6333 11:20:05.122594 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6334 11:20:05.126061 [CA 0] Center 36 (8~64) winsize 57
6335 11:20:05.128788 [CA 1] Center 36 (8~64) winsize 57
6336 11:20:05.131806 [CA 2] Center 36 (8~64) winsize 57
6337 11:20:05.135765 [CA 3] Center 36 (8~64) winsize 57
6338 11:20:05.139399 [CA 4] Center 36 (8~64) winsize 57
6339 11:20:05.141899 [CA 5] Center 36 (8~64) winsize 57
6340 11:20:05.142370
6341 11:20:05.145105 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6342 11:20:05.145575
6343 11:20:05.148700 [CATrainingPosCal] consider 1 rank data
6344 11:20:05.151786 u2DelayCellTimex100 = 270/100 ps
6345 11:20:05.154745 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6346 11:20:05.158223 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6347 11:20:05.162029 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6348 11:20:05.164886 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6349 11:20:05.168419 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6350 11:20:05.171415 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6351 11:20:05.171984
6352 11:20:05.178456 CA PerBit enable=1, Macro0, CA PI delay=36
6353 11:20:05.179142
6354 11:20:05.181400 [CBTSetCACLKResult] CA Dly = 36
6355 11:20:05.181868 CS Dly: 1 (0~32)
6356 11:20:05.182246 ==
6357 11:20:05.184559 Dram Type= 6, Freq= 0, CH_0, rank 1
6358 11:20:05.188220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6359 11:20:05.188918 ==
6360 11:20:05.194633 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6361 11:20:05.200886 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6362 11:20:05.204210 [CA 0] Center 36 (8~64) winsize 57
6363 11:20:05.207984 [CA 1] Center 36 (8~64) winsize 57
6364 11:20:05.211241 [CA 2] Center 36 (8~64) winsize 57
6365 11:20:05.213885 [CA 3] Center 36 (8~64) winsize 57
6366 11:20:05.217374 [CA 4] Center 36 (8~64) winsize 57
6367 11:20:05.220846 [CA 5] Center 36 (8~64) winsize 57
6368 11:20:05.221398
6369 11:20:05.224485 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6370 11:20:05.225118
6371 11:20:05.227460 [CATrainingPosCal] consider 2 rank data
6372 11:20:05.230431 u2DelayCellTimex100 = 270/100 ps
6373 11:20:05.234438 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6374 11:20:05.237123 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6375 11:20:05.240827 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6376 11:20:05.244140 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6377 11:20:05.247460 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6378 11:20:05.250683 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6379 11:20:05.251143
6380 11:20:05.256915 CA PerBit enable=1, Macro0, CA PI delay=36
6381 11:20:05.257374
6382 11:20:05.257976 [CBTSetCACLKResult] CA Dly = 36
6383 11:20:05.260444 CS Dly: 1 (0~32)
6384 11:20:05.261026
6385 11:20:05.263556 ----->DramcWriteLeveling(PI) begin...
6386 11:20:05.264020 ==
6387 11:20:05.267132 Dram Type= 6, Freq= 0, CH_0, rank 0
6388 11:20:05.270701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6389 11:20:05.271283 ==
6390 11:20:05.273659 Write leveling (Byte 0): 40 => 8
6391 11:20:05.276714 Write leveling (Byte 1): 32 => 0
6392 11:20:05.280383 DramcWriteLeveling(PI) end<-----
6393 11:20:05.280976
6394 11:20:05.281355 ==
6395 11:20:05.283809 Dram Type= 6, Freq= 0, CH_0, rank 0
6396 11:20:05.287037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6397 11:20:05.290115 ==
6398 11:20:05.290588 [Gating] SW mode calibration
6399 11:20:05.300300 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6400 11:20:05.303547 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6401 11:20:05.306972 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6402 11:20:05.313109 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6403 11:20:05.317018 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6404 11:20:05.320415 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6405 11:20:05.326547 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6406 11:20:05.329906 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6407 11:20:05.333317 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6408 11:20:05.340484 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6409 11:20:05.343673 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6410 11:20:05.346248 Total UI for P1: 0, mck2ui 16
6411 11:20:05.349458 best dqsien dly found for B0: ( 0, 14, 24)
6412 11:20:05.353362 Total UI for P1: 0, mck2ui 16
6413 11:20:05.356220 best dqsien dly found for B1: ( 0, 14, 24)
6414 11:20:05.359455 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6415 11:20:05.362533 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6416 11:20:05.363013
6417 11:20:05.366170 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6418 11:20:05.372425 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6419 11:20:05.372951 [Gating] SW calibration Done
6420 11:20:05.373426 ==
6421 11:20:05.375841 Dram Type= 6, Freq= 0, CH_0, rank 0
6422 11:20:05.382769 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6423 11:20:05.383363 ==
6424 11:20:05.383828 RX Vref Scan: 0
6425 11:20:05.384183
6426 11:20:05.385675 RX Vref 0 -> 0, step: 1
6427 11:20:05.386143
6428 11:20:05.389210 RX Delay -410 -> 252, step: 16
6429 11:20:05.392328 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6430 11:20:05.395407 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6431 11:20:05.402322 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6432 11:20:05.405873 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6433 11:20:05.409041 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6434 11:20:05.412707 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6435 11:20:05.418779 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6436 11:20:05.422052 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6437 11:20:05.425730 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6438 11:20:05.429113 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6439 11:20:05.435678 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6440 11:20:05.438635 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6441 11:20:05.442703 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6442 11:20:05.448548 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6443 11:20:05.451726 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6444 11:20:05.455254 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6445 11:20:05.455793 ==
6446 11:20:05.459126 Dram Type= 6, Freq= 0, CH_0, rank 0
6447 11:20:05.462295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6448 11:20:05.465128 ==
6449 11:20:05.465598 DQS Delay:
6450 11:20:05.465971 DQS0 = 43, DQS1 = 59
6451 11:20:05.468629 DQM Delay:
6452 11:20:05.469198 DQM0 = 9, DQM1 = 12
6453 11:20:05.471560 DQ Delay:
6454 11:20:05.472032 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =0
6455 11:20:05.475310 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6456 11:20:05.478188 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6457 11:20:05.482156 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6458 11:20:05.482789
6459 11:20:05.483191
6460 11:20:05.483543 ==
6461 11:20:05.484703 Dram Type= 6, Freq= 0, CH_0, rank 0
6462 11:20:05.491732 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6463 11:20:05.492452 ==
6464 11:20:05.492954
6465 11:20:05.493312
6466 11:20:05.493649 TX Vref Scan disable
6467 11:20:05.495006 == TX Byte 0 ==
6468 11:20:05.497909 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6469 11:20:05.501529 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6470 11:20:05.504932 == TX Byte 1 ==
6471 11:20:05.507741 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6472 11:20:05.515038 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6473 11:20:05.515507 ==
6474 11:20:05.517624 Dram Type= 6, Freq= 0, CH_0, rank 0
6475 11:20:05.521530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6476 11:20:05.522109 ==
6477 11:20:05.522488
6478 11:20:05.522834
6479 11:20:05.524607 TX Vref Scan disable
6480 11:20:05.525180 == TX Byte 0 ==
6481 11:20:05.527890 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6482 11:20:05.534512 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6483 11:20:05.535090 == TX Byte 1 ==
6484 11:20:05.537969 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6485 11:20:05.544690 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6486 11:20:05.545265
6487 11:20:05.545641 [DATLAT]
6488 11:20:05.545984 Freq=400, CH0 RK0
6489 11:20:05.548397
6490 11:20:05.549000 DATLAT Default: 0xf
6491 11:20:05.550962 0, 0xFFFF, sum = 0
6492 11:20:05.551506 1, 0xFFFF, sum = 0
6493 11:20:05.554430 2, 0xFFFF, sum = 0
6494 11:20:05.555011 3, 0xFFFF, sum = 0
6495 11:20:05.557340 4, 0xFFFF, sum = 0
6496 11:20:05.557818 5, 0xFFFF, sum = 0
6497 11:20:05.560668 6, 0xFFFF, sum = 0
6498 11:20:05.561146 7, 0xFFFF, sum = 0
6499 11:20:05.564665 8, 0xFFFF, sum = 0
6500 11:20:05.565271 9, 0xFFFF, sum = 0
6501 11:20:05.567913 10, 0xFFFF, sum = 0
6502 11:20:05.568510 11, 0xFFFF, sum = 0
6503 11:20:05.571233 12, 0xFFFF, sum = 0
6504 11:20:05.571814 13, 0x0, sum = 1
6505 11:20:05.574071 14, 0x0, sum = 2
6506 11:20:05.574657 15, 0x0, sum = 3
6507 11:20:05.577151 16, 0x0, sum = 4
6508 11:20:05.577832 best_step = 14
6509 11:20:05.578248
6510 11:20:05.578736 ==
6511 11:20:05.580588 Dram Type= 6, Freq= 0, CH_0, rank 0
6512 11:20:05.587628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6513 11:20:05.588196 ==
6514 11:20:05.588622 RX Vref Scan: 1
6515 11:20:05.589037
6516 11:20:05.590865 RX Vref 0 -> 0, step: 1
6517 11:20:05.591470
6518 11:20:05.593752 RX Delay -359 -> 252, step: 8
6519 11:20:05.594227
6520 11:20:05.597019 Set Vref, RX VrefLevel [Byte0]: 60
6521 11:20:05.600374 [Byte1]: 49
6522 11:20:05.600988
6523 11:20:05.603856 Final RX Vref Byte 0 = 60 to rank0
6524 11:20:05.607410 Final RX Vref Byte 1 = 49 to rank0
6525 11:20:05.610274 Final RX Vref Byte 0 = 60 to rank1
6526 11:20:05.613850 Final RX Vref Byte 1 = 49 to rank1==
6527 11:20:05.617102 Dram Type= 6, Freq= 0, CH_0, rank 0
6528 11:20:05.623577 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6529 11:20:05.624147 ==
6530 11:20:05.624555 DQS Delay:
6531 11:20:05.627005 DQS0 = 48, DQS1 = 60
6532 11:20:05.627577 DQM Delay:
6533 11:20:05.627956 DQM0 = 11, DQM1 = 12
6534 11:20:05.630060 DQ Delay:
6535 11:20:05.634176 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6536 11:20:05.637398 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6537 11:20:05.637970 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6538 11:20:05.640554 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6539 11:20:05.643308
6540 11:20:05.643875
6541 11:20:05.650285 [DQSOSCAuto] RK0, (LSB)MR18= 0xbb7d, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 386 ps
6542 11:20:05.653607 CH0 RK0: MR19=C0C, MR18=BB7D
6543 11:20:05.660185 CH0_RK0: MR19=0xC0C, MR18=0xBB7D, DQSOSC=386, MR23=63, INC=396, DEC=264
6544 11:20:05.660774 ==
6545 11:20:05.663585 Dram Type= 6, Freq= 0, CH_0, rank 1
6546 11:20:05.666602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6547 11:20:05.667174 ==
6548 11:20:05.670112 [Gating] SW mode calibration
6549 11:20:05.676736 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6550 11:20:05.683118 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6551 11:20:05.686181 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6552 11:20:05.689852 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6553 11:20:05.696205 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6554 11:20:05.699530 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6555 11:20:05.702745 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6556 11:20:05.709416 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6557 11:20:05.712640 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6558 11:20:05.716052 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6559 11:20:05.722571 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6560 11:20:05.723140 Total UI for P1: 0, mck2ui 16
6561 11:20:05.729384 best dqsien dly found for B0: ( 0, 14, 24)
6562 11:20:05.729856 Total UI for P1: 0, mck2ui 16
6563 11:20:05.732783 best dqsien dly found for B1: ( 0, 14, 24)
6564 11:20:05.739054 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6565 11:20:05.742492 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6566 11:20:05.743091
6567 11:20:05.745582 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6568 11:20:05.749701 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6569 11:20:05.752683 [Gating] SW calibration Done
6570 11:20:05.753155 ==
6571 11:20:05.755930 Dram Type= 6, Freq= 0, CH_0, rank 1
6572 11:20:05.759250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6573 11:20:05.759741 ==
6574 11:20:05.762196 RX Vref Scan: 0
6575 11:20:05.762663
6576 11:20:05.763031 RX Vref 0 -> 0, step: 1
6577 11:20:05.763380
6578 11:20:05.765671 RX Delay -410 -> 252, step: 16
6579 11:20:05.772249 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6580 11:20:05.775551 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6581 11:20:05.778919 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6582 11:20:05.782533 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6583 11:20:05.789727 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6584 11:20:05.791959 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6585 11:20:05.795417 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6586 11:20:05.799359 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6587 11:20:05.805391 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6588 11:20:05.808504 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6589 11:20:05.812098 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6590 11:20:05.815688 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6591 11:20:05.822353 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6592 11:20:05.825783 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6593 11:20:05.828865 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6594 11:20:05.835322 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6595 11:20:05.835888 ==
6596 11:20:05.838686 Dram Type= 6, Freq= 0, CH_0, rank 1
6597 11:20:05.841968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6598 11:20:05.842440 ==
6599 11:20:05.842806 DQS Delay:
6600 11:20:05.845029 DQS0 = 43, DQS1 = 59
6601 11:20:05.845597 DQM Delay:
6602 11:20:05.848679 DQM0 = 10, DQM1 = 16
6603 11:20:05.849148 DQ Delay:
6604 11:20:05.851491 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =0
6605 11:20:05.855292 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =16
6606 11:20:05.858142 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6607 11:20:05.861467 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6608 11:20:05.861948
6609 11:20:05.862317
6610 11:20:05.862658 ==
6611 11:20:05.865044 Dram Type= 6, Freq= 0, CH_0, rank 1
6612 11:20:05.868419 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6613 11:20:05.869046 ==
6614 11:20:05.869425
6615 11:20:05.869765
6616 11:20:05.871566 TX Vref Scan disable
6617 11:20:05.872029 == TX Byte 0 ==
6618 11:20:05.878016 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6619 11:20:05.881283 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6620 11:20:05.881756 == TX Byte 1 ==
6621 11:20:05.888276 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6622 11:20:05.891156 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6623 11:20:05.891735 ==
6624 11:20:05.894321 Dram Type= 6, Freq= 0, CH_0, rank 1
6625 11:20:05.897554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6626 11:20:05.898024 ==
6627 11:20:05.898392
6628 11:20:05.898762
6629 11:20:05.901421 TX Vref Scan disable
6630 11:20:05.904388 == TX Byte 0 ==
6631 11:20:05.907534 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6632 11:20:05.910977 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6633 11:20:05.914922 == TX Byte 1 ==
6634 11:20:05.917761 Update DQ dly =578 (4 ,2, 2) DQ OEN =(3 ,3)
6635 11:20:05.920696 Update DQM dly =578 (4 ,2, 2) DQM OEN =(3 ,3)
6636 11:20:05.921185
6637 11:20:05.921553 [DATLAT]
6638 11:20:05.924043 Freq=400, CH0 RK1
6639 11:20:05.924510
6640 11:20:05.924931 DATLAT Default: 0xe
6641 11:20:05.927806 0, 0xFFFF, sum = 0
6642 11:20:05.928380 1, 0xFFFF, sum = 0
6643 11:20:05.930639 2, 0xFFFF, sum = 0
6644 11:20:05.934051 3, 0xFFFF, sum = 0
6645 11:20:05.934524 4, 0xFFFF, sum = 0
6646 11:20:05.937513 5, 0xFFFF, sum = 0
6647 11:20:05.938089 6, 0xFFFF, sum = 0
6648 11:20:05.940755 7, 0xFFFF, sum = 0
6649 11:20:05.941339 8, 0xFFFF, sum = 0
6650 11:20:05.944091 9, 0xFFFF, sum = 0
6651 11:20:05.944590 10, 0xFFFF, sum = 0
6652 11:20:05.947169 11, 0xFFFF, sum = 0
6653 11:20:05.947640 12, 0xFFFF, sum = 0
6654 11:20:05.950811 13, 0x0, sum = 1
6655 11:20:05.951395 14, 0x0, sum = 2
6656 11:20:05.954137 15, 0x0, sum = 3
6657 11:20:05.954724 16, 0x0, sum = 4
6658 11:20:05.957085 best_step = 14
6659 11:20:05.957550
6660 11:20:05.957918 ==
6661 11:20:05.960648 Dram Type= 6, Freq= 0, CH_0, rank 1
6662 11:20:05.963973 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6663 11:20:05.964463 ==
6664 11:20:05.967334 RX Vref Scan: 0
6665 11:20:05.967905
6666 11:20:05.968278 RX Vref 0 -> 0, step: 1
6667 11:20:05.968685
6668 11:20:05.970282 RX Delay -359 -> 252, step: 8
6669 11:20:05.978174 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6670 11:20:05.981427 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6671 11:20:05.985052 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6672 11:20:05.991754 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6673 11:20:05.994480 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6674 11:20:05.997910 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6675 11:20:06.001090 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6676 11:20:06.007700 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6677 11:20:06.010551 iDelay=217, Bit 8, Center -56 (-303 ~ 192) 496
6678 11:20:06.013909 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6679 11:20:06.017348 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6680 11:20:06.023594 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6681 11:20:06.027606 iDelay=217, Bit 12, Center -36 (-279 ~ 208) 488
6682 11:20:06.030447 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6683 11:20:06.037007 iDelay=217, Bit 14, Center -32 (-271 ~ 208) 480
6684 11:20:06.040111 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6685 11:20:06.040621 ==
6686 11:20:06.043421 Dram Type= 6, Freq= 0, CH_0, rank 1
6687 11:20:06.047173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6688 11:20:06.047805 ==
6689 11:20:06.050164 DQS Delay:
6690 11:20:06.050813 DQS0 = 44, DQS1 = 60
6691 11:20:06.051348 DQM Delay:
6692 11:20:06.053210 DQM0 = 7, DQM1 = 16
6693 11:20:06.053678 DQ Delay:
6694 11:20:06.057134 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =4
6695 11:20:06.059533 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6696 11:20:06.062738 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =8
6697 11:20:06.066395 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =24
6698 11:20:06.066967
6699 11:20:06.067336
6700 11:20:06.076668 [DQSOSCAuto] RK1, (LSB)MR18= 0xb843, (MSB)MR19= 0xc0c, tDQSOscB0 = 401 ps tDQSOscB1 = 386 ps
6701 11:20:06.077242 CH0 RK1: MR19=C0C, MR18=B843
6702 11:20:06.082652 CH0_RK1: MR19=0xC0C, MR18=0xB843, DQSOSC=386, MR23=63, INC=396, DEC=264
6703 11:20:06.086036 [RxdqsGatingPostProcess] freq 400
6704 11:20:06.092892 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6705 11:20:06.096048 best DQS0 dly(2T, 0.5T) = (0, 10)
6706 11:20:06.099517 best DQS1 dly(2T, 0.5T) = (0, 10)
6707 11:20:06.102900 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6708 11:20:06.106319 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6709 11:20:06.109219 best DQS0 dly(2T, 0.5T) = (0, 10)
6710 11:20:06.112387 best DQS1 dly(2T, 0.5T) = (0, 10)
6711 11:20:06.115748 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6712 11:20:06.119584 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6713 11:20:06.120193 Pre-setting of DQS Precalculation
6714 11:20:06.126226 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6715 11:20:06.126789 ==
6716 11:20:06.129408 Dram Type= 6, Freq= 0, CH_1, rank 0
6717 11:20:06.132423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6718 11:20:06.132935 ==
6719 11:20:06.138737 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6720 11:20:06.145689 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6721 11:20:06.149117 [CA 0] Center 36 (8~64) winsize 57
6722 11:20:06.152197 [CA 1] Center 36 (8~64) winsize 57
6723 11:20:06.155691 [CA 2] Center 36 (8~64) winsize 57
6724 11:20:06.159418 [CA 3] Center 36 (8~64) winsize 57
6725 11:20:06.162169 [CA 4] Center 36 (8~64) winsize 57
6726 11:20:06.162699 [CA 5] Center 36 (8~64) winsize 57
6727 11:20:06.165610
6728 11:20:06.168505 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6729 11:20:06.169135
6730 11:20:06.172110 [CATrainingPosCal] consider 1 rank data
6731 11:20:06.174903 u2DelayCellTimex100 = 270/100 ps
6732 11:20:06.178328 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6733 11:20:06.181810 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6734 11:20:06.185559 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6735 11:20:06.188368 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6736 11:20:06.192329 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6737 11:20:06.195208 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6738 11:20:06.195679
6739 11:20:06.198312 CA PerBit enable=1, Macro0, CA PI delay=36
6740 11:20:06.202339
6741 11:20:06.202903 [CBTSetCACLKResult] CA Dly = 36
6742 11:20:06.204872 CS Dly: 1 (0~32)
6743 11:20:06.205441 ==
6744 11:20:06.208822 Dram Type= 6, Freq= 0, CH_1, rank 1
6745 11:20:06.211460 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6746 11:20:06.212023 ==
6747 11:20:06.218047 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6748 11:20:06.225052 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6749 11:20:06.228007 [CA 0] Center 36 (8~64) winsize 57
6750 11:20:06.231957 [CA 1] Center 36 (8~64) winsize 57
6751 11:20:06.235059 [CA 2] Center 36 (8~64) winsize 57
6752 11:20:06.235625 [CA 3] Center 36 (8~64) winsize 57
6753 11:20:06.237851 [CA 4] Center 36 (8~64) winsize 57
6754 11:20:06.241558 [CA 5] Center 36 (8~64) winsize 57
6755 11:20:06.242124
6756 11:20:06.248016 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6757 11:20:06.248615
6758 11:20:06.251111 [CATrainingPosCal] consider 2 rank data
6759 11:20:06.254298 u2DelayCellTimex100 = 270/100 ps
6760 11:20:06.258084 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6761 11:20:06.261648 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6762 11:20:06.264333 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6763 11:20:06.267501 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6764 11:20:06.271040 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6765 11:20:06.274206 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6766 11:20:06.274678
6767 11:20:06.277175 CA PerBit enable=1, Macro0, CA PI delay=36
6768 11:20:06.277643
6769 11:20:06.281169 [CBTSetCACLKResult] CA Dly = 36
6770 11:20:06.284537 CS Dly: 1 (0~32)
6771 11:20:06.285119
6772 11:20:06.288041 ----->DramcWriteLeveling(PI) begin...
6773 11:20:06.288668 ==
6774 11:20:06.291119 Dram Type= 6, Freq= 0, CH_1, rank 0
6775 11:20:06.293783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6776 11:20:06.294253 ==
6777 11:20:06.297459 Write leveling (Byte 0): 40 => 8
6778 11:20:06.301098 Write leveling (Byte 1): 40 => 8
6779 11:20:06.304038 DramcWriteLeveling(PI) end<-----
6780 11:20:06.304644
6781 11:20:06.305021 ==
6782 11:20:06.307505 Dram Type= 6, Freq= 0, CH_1, rank 0
6783 11:20:06.310439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6784 11:20:06.310913 ==
6785 11:20:06.313863 [Gating] SW mode calibration
6786 11:20:06.320046 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6787 11:20:06.327166 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6788 11:20:06.330205 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6789 11:20:06.337144 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6790 11:20:06.340130 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6791 11:20:06.343117 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6792 11:20:06.350179 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6793 11:20:06.353065 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6794 11:20:06.356609 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6795 11:20:06.363153 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6796 11:20:06.366823 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6797 11:20:06.369765 Total UI for P1: 0, mck2ui 16
6798 11:20:06.373143 best dqsien dly found for B0: ( 0, 14, 24)
6799 11:20:06.376699 Total UI for P1: 0, mck2ui 16
6800 11:20:06.380221 best dqsien dly found for B1: ( 0, 14, 24)
6801 11:20:06.382902 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6802 11:20:06.386041 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6803 11:20:06.386505
6804 11:20:06.390120 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6805 11:20:06.393421 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6806 11:20:06.396258 [Gating] SW calibration Done
6807 11:20:06.396769 ==
6808 11:20:06.399186 Dram Type= 6, Freq= 0, CH_1, rank 0
6809 11:20:06.402959 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6810 11:20:06.406624 ==
6811 11:20:06.407208 RX Vref Scan: 0
6812 11:20:06.407583
6813 11:20:06.409095 RX Vref 0 -> 0, step: 1
6814 11:20:06.409561
6815 11:20:06.412923 RX Delay -410 -> 252, step: 16
6816 11:20:06.415784 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6817 11:20:06.419057 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6818 11:20:06.422650 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6819 11:20:06.429221 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6820 11:20:06.432483 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6821 11:20:06.435890 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6822 11:20:06.438969 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6823 11:20:06.445561 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6824 11:20:06.448955 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6825 11:20:06.451913 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6826 11:20:06.458989 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6827 11:20:06.461649 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6828 11:20:06.464984 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6829 11:20:06.468922 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6830 11:20:06.475602 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6831 11:20:06.478244 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6832 11:20:06.478714 ==
6833 11:20:06.481650 Dram Type= 6, Freq= 0, CH_1, rank 0
6834 11:20:06.485127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6835 11:20:06.485700 ==
6836 11:20:06.488853 DQS Delay:
6837 11:20:06.489423 DQS0 = 43, DQS1 = 51
6838 11:20:06.491581 DQM Delay:
6839 11:20:06.492149 DQM0 = 12, DQM1 = 14
6840 11:20:06.492549 DQ Delay:
6841 11:20:06.495430 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6842 11:20:06.498735 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6843 11:20:06.501338 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6844 11:20:06.504789 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6845 11:20:06.505380
6846 11:20:06.505799
6847 11:20:06.506146 ==
6848 11:20:06.508283 Dram Type= 6, Freq= 0, CH_1, rank 0
6849 11:20:06.514983 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6850 11:20:06.515561 ==
6851 11:20:06.515939
6852 11:20:06.516283
6853 11:20:06.516647 TX Vref Scan disable
6854 11:20:06.518159 == TX Byte 0 ==
6855 11:20:06.521080 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6856 11:20:06.524393 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6857 11:20:06.528086 == TX Byte 1 ==
6858 11:20:06.531759 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6859 11:20:06.534441 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6860 11:20:06.534912 ==
6861 11:20:06.537914 Dram Type= 6, Freq= 0, CH_1, rank 0
6862 11:20:06.544181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6863 11:20:06.544789 ==
6864 11:20:06.545167
6865 11:20:06.545510
6866 11:20:06.547661 TX Vref Scan disable
6867 11:20:06.548245 == TX Byte 0 ==
6868 11:20:06.551103 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6869 11:20:06.557342 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6870 11:20:06.557916 == TX Byte 1 ==
6871 11:20:06.560869 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6872 11:20:06.564155 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6873 11:20:06.567624
6874 11:20:06.568189 [DATLAT]
6875 11:20:06.568602 Freq=400, CH1 RK0
6876 11:20:06.568957
6877 11:20:06.570834 DATLAT Default: 0xf
6878 11:20:06.571300 0, 0xFFFF, sum = 0
6879 11:20:06.574549 1, 0xFFFF, sum = 0
6880 11:20:06.575116 2, 0xFFFF, sum = 0
6881 11:20:06.577593 3, 0xFFFF, sum = 0
6882 11:20:06.580483 4, 0xFFFF, sum = 0
6883 11:20:06.581121 5, 0xFFFF, sum = 0
6884 11:20:06.583707 6, 0xFFFF, sum = 0
6885 11:20:06.584182 7, 0xFFFF, sum = 0
6886 11:20:06.587103 8, 0xFFFF, sum = 0
6887 11:20:06.587674 9, 0xFFFF, sum = 0
6888 11:20:06.590464 10, 0xFFFF, sum = 0
6889 11:20:06.591032 11, 0xFFFF, sum = 0
6890 11:20:06.593988 12, 0xFFFF, sum = 0
6891 11:20:06.594562 13, 0x0, sum = 1
6892 11:20:06.597197 14, 0x0, sum = 2
6893 11:20:06.597770 15, 0x0, sum = 3
6894 11:20:06.600121 16, 0x0, sum = 4
6895 11:20:06.600729 best_step = 14
6896 11:20:06.601105
6897 11:20:06.601446 ==
6898 11:20:06.603500 Dram Type= 6, Freq= 0, CH_1, rank 0
6899 11:20:06.607028 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6900 11:20:06.610265 ==
6901 11:20:06.610791 RX Vref Scan: 1
6902 11:20:06.611164
6903 11:20:06.613364 RX Vref 0 -> 0, step: 1
6904 11:20:06.613919
6905 11:20:06.616581 RX Delay -343 -> 252, step: 8
6906 11:20:06.617155
6907 11:20:06.620166 Set Vref, RX VrefLevel [Byte0]: 48
6908 11:20:06.623379 [Byte1]: 53
6909 11:20:06.623948
6910 11:20:06.627025 Final RX Vref Byte 0 = 48 to rank0
6911 11:20:06.629874 Final RX Vref Byte 1 = 53 to rank0
6912 11:20:06.633257 Final RX Vref Byte 0 = 48 to rank1
6913 11:20:06.636384 Final RX Vref Byte 1 = 53 to rank1==
6914 11:20:06.639713 Dram Type= 6, Freq= 0, CH_1, rank 0
6915 11:20:06.643120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6916 11:20:06.646314 ==
6917 11:20:06.646782 DQS Delay:
6918 11:20:06.647155 DQS0 = 44, DQS1 = 52
6919 11:20:06.649639 DQM Delay:
6920 11:20:06.650102 DQM0 = 7, DQM1 = 9
6921 11:20:06.653506 DQ Delay:
6922 11:20:06.653969 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6923 11:20:06.656460 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
6924 11:20:06.659388 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6925 11:20:06.662392 DQ12 =20, DQ13 =12, DQ14 =16, DQ15 =16
6926 11:20:06.662858
6927 11:20:06.663225
6928 11:20:06.672744 [DQSOSCAuto] RK0, (LSB)MR18= 0x996e, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 390 ps
6929 11:20:06.675640 CH1 RK0: MR19=C0C, MR18=996E
6930 11:20:06.682390 CH1_RK0: MR19=0xC0C, MR18=0x996E, DQSOSC=390, MR23=63, INC=388, DEC=258
6931 11:20:06.682973 ==
6932 11:20:06.685929 Dram Type= 6, Freq= 0, CH_1, rank 1
6933 11:20:06.689252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6934 11:20:06.689723 ==
6935 11:20:06.692441 [Gating] SW mode calibration
6936 11:20:06.699138 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6937 11:20:06.705414 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6938 11:20:06.708624 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6939 11:20:06.712011 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6940 11:20:06.718373 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6941 11:20:06.722033 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6942 11:20:06.725216 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6943 11:20:06.731847 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6944 11:20:06.734711 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6945 11:20:06.738681 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6946 11:20:06.745022 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6947 11:20:06.745496 Total UI for P1: 0, mck2ui 16
6948 11:20:06.752184 best dqsien dly found for B0: ( 0, 14, 24)
6949 11:20:06.752792 Total UI for P1: 0, mck2ui 16
6950 11:20:06.754933 best dqsien dly found for B1: ( 0, 14, 24)
6951 11:20:06.761054 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6952 11:20:06.764421 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6953 11:20:06.765122
6954 11:20:06.767979 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6955 11:20:06.771831 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6956 11:20:06.774617 [Gating] SW calibration Done
6957 11:20:06.775086 ==
6958 11:20:06.777769 Dram Type= 6, Freq= 0, CH_1, rank 1
6959 11:20:06.780928 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6960 11:20:06.781398 ==
6961 11:20:06.784299 RX Vref Scan: 0
6962 11:20:06.784806
6963 11:20:06.785312 RX Vref 0 -> 0, step: 1
6964 11:20:06.785796
6965 11:20:06.787656 RX Delay -410 -> 252, step: 16
6966 11:20:06.794663 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6967 11:20:06.797565 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6968 11:20:06.800901 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6969 11:20:06.804134 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6970 11:20:06.811062 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6971 11:20:06.814049 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6972 11:20:06.817569 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6973 11:20:06.820608 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6974 11:20:06.827552 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6975 11:20:06.830372 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6976 11:20:06.833546 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6977 11:20:06.837465 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6978 11:20:06.844140 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6979 11:20:06.847160 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6980 11:20:06.851142 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6981 11:20:06.857120 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6982 11:20:06.857700 ==
6983 11:20:06.860488 Dram Type= 6, Freq= 0, CH_1, rank 1
6984 11:20:06.863628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6985 11:20:06.864074 ==
6986 11:20:06.864706 DQS Delay:
6987 11:20:06.866739 DQS0 = 51, DQS1 = 51
6988 11:20:06.867210 DQM Delay:
6989 11:20:06.870593 DQM0 = 19, DQM1 = 15
6990 11:20:06.871161 DQ Delay:
6991 11:20:06.873606 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6992 11:20:06.877588 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6993 11:20:06.880288 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =8
6994 11:20:06.883488 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6995 11:20:06.883958
6996 11:20:06.884328
6997 11:20:06.884727 ==
6998 11:20:06.887142 Dram Type= 6, Freq= 0, CH_1, rank 1
6999 11:20:06.890272 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7000 11:20:06.890751 ==
7001 11:20:06.891129
7002 11:20:06.891476
7003 11:20:06.893628 TX Vref Scan disable
7004 11:20:06.896696 == TX Byte 0 ==
7005 11:20:06.900321 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
7006 11:20:06.903731 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
7007 11:20:06.907093 == TX Byte 1 ==
7008 11:20:06.910112 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
7009 11:20:06.913803 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
7010 11:20:06.914382 ==
7011 11:20:06.916692 Dram Type= 6, Freq= 0, CH_1, rank 1
7012 11:20:06.919917 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7013 11:20:06.920393 ==
7014 11:20:06.920798
7015 11:20:06.923050
7016 11:20:06.923624 TX Vref Scan disable
7017 11:20:06.926848 == TX Byte 0 ==
7018 11:20:06.929898 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
7019 11:20:06.933124 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
7020 11:20:06.936591 == TX Byte 1 ==
7021 11:20:06.939421 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
7022 11:20:06.942950 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
7023 11:20:06.943527
7024 11:20:06.943900 [DATLAT]
7025 11:20:06.946450 Freq=400, CH1 RK1
7026 11:20:06.946944
7027 11:20:06.949283 DATLAT Default: 0xe
7028 11:20:06.949753 0, 0xFFFF, sum = 0
7029 11:20:06.952997 1, 0xFFFF, sum = 0
7030 11:20:06.953510 2, 0xFFFF, sum = 0
7031 11:20:06.955876 3, 0xFFFF, sum = 0
7032 11:20:06.956353 4, 0xFFFF, sum = 0
7033 11:20:06.959591 5, 0xFFFF, sum = 0
7034 11:20:06.960070 6, 0xFFFF, sum = 0
7035 11:20:06.962557 7, 0xFFFF, sum = 0
7036 11:20:06.963035 8, 0xFFFF, sum = 0
7037 11:20:06.966115 9, 0xFFFF, sum = 0
7038 11:20:06.966714 10, 0xFFFF, sum = 0
7039 11:20:06.969541 11, 0xFFFF, sum = 0
7040 11:20:06.970021 12, 0xFFFF, sum = 0
7041 11:20:06.972821 13, 0x0, sum = 1
7042 11:20:06.973298 14, 0x0, sum = 2
7043 11:20:06.975941 15, 0x0, sum = 3
7044 11:20:06.976476 16, 0x0, sum = 4
7045 11:20:06.978966 best_step = 14
7046 11:20:06.979436
7047 11:20:06.979805 ==
7048 11:20:06.982765 Dram Type= 6, Freq= 0, CH_1, rank 1
7049 11:20:06.986133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7050 11:20:06.986710 ==
7051 11:20:06.989267 RX Vref Scan: 0
7052 11:20:06.989735
7053 11:20:06.990108 RX Vref 0 -> 0, step: 1
7054 11:20:06.990456
7055 11:20:06.992779 RX Delay -343 -> 252, step: 8
7056 11:20:07.000681 iDelay=225, Bit 0, Center -32 (-271 ~ 208) 480
7057 11:20:07.003816 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
7058 11:20:07.007085 iDelay=225, Bit 2, Center -48 (-287 ~ 192) 480
7059 11:20:07.013398 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
7060 11:20:07.016820 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
7061 11:20:07.020383 iDelay=225, Bit 5, Center -24 (-263 ~ 216) 480
7062 11:20:07.023774 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
7063 11:20:07.030331 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
7064 11:20:07.033389 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
7065 11:20:07.036804 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7066 11:20:07.039667 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
7067 11:20:07.046478 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
7068 11:20:07.050103 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
7069 11:20:07.053454 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
7070 11:20:07.056912 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
7071 11:20:07.063051 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
7072 11:20:07.063611 ==
7073 11:20:07.066206 Dram Type= 6, Freq= 0, CH_1, rank 1
7074 11:20:07.069777 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7075 11:20:07.070252 ==
7076 11:20:07.070624 DQS Delay:
7077 11:20:07.072772 DQS0 = 48, DQS1 = 56
7078 11:20:07.073241 DQM Delay:
7079 11:20:07.076026 DQM0 = 12, DQM1 = 11
7080 11:20:07.076541 DQ Delay:
7081 11:20:07.079648 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7082 11:20:07.083119 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
7083 11:20:07.086827 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7084 11:20:07.089586 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
7085 11:20:07.090161
7086 11:20:07.090538
7087 11:20:07.096171 [DQSOSCAuto] RK1, (LSB)MR18= 0x6d5d, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
7088 11:20:07.099245 CH1 RK1: MR19=C0C, MR18=6D5D
7089 11:20:07.106404 CH1_RK1: MR19=0xC0C, MR18=0x6D5D, DQSOSC=396, MR23=63, INC=376, DEC=251
7090 11:20:07.109407 [RxdqsGatingPostProcess] freq 400
7091 11:20:07.116337 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7092 11:20:07.119182 best DQS0 dly(2T, 0.5T) = (0, 10)
7093 11:20:07.122468 best DQS1 dly(2T, 0.5T) = (0, 10)
7094 11:20:07.125910 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7095 11:20:07.129347 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7096 11:20:07.129940 best DQS0 dly(2T, 0.5T) = (0, 10)
7097 11:20:07.132568 best DQS1 dly(2T, 0.5T) = (0, 10)
7098 11:20:07.135719 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7099 11:20:07.139223 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7100 11:20:07.142470 Pre-setting of DQS Precalculation
7101 11:20:07.149011 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7102 11:20:07.155613 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7103 11:20:07.162545 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7104 11:20:07.163125
7105 11:20:07.163496
7106 11:20:07.165413 [Calibration Summary] 800 Mbps
7107 11:20:07.166052 CH 0, Rank 0
7108 11:20:07.168772 SW Impedance : PASS
7109 11:20:07.172139 DUTY Scan : NO K
7110 11:20:07.172760 ZQ Calibration : PASS
7111 11:20:07.175374 Jitter Meter : NO K
7112 11:20:07.178836 CBT Training : PASS
7113 11:20:07.179306 Write leveling : PASS
7114 11:20:07.182186 RX DQS gating : PASS
7115 11:20:07.185019 RX DQ/DQS(RDDQC) : PASS
7116 11:20:07.185490 TX DQ/DQS : PASS
7117 11:20:07.188487 RX DATLAT : PASS
7118 11:20:07.191483 RX DQ/DQS(Engine): PASS
7119 11:20:07.191954 TX OE : NO K
7120 11:20:07.195201 All Pass.
7121 11:20:07.195669
7122 11:20:07.196038 CH 0, Rank 1
7123 11:20:07.198465 SW Impedance : PASS
7124 11:20:07.199014 DUTY Scan : NO K
7125 11:20:07.201272 ZQ Calibration : PASS
7126 11:20:07.204843 Jitter Meter : NO K
7127 11:20:07.205314 CBT Training : PASS
7128 11:20:07.208266 Write leveling : NO K
7129 11:20:07.211869 RX DQS gating : PASS
7130 11:20:07.212452 RX DQ/DQS(RDDQC) : PASS
7131 11:20:07.214444 TX DQ/DQS : PASS
7132 11:20:07.218399 RX DATLAT : PASS
7133 11:20:07.218977 RX DQ/DQS(Engine): PASS
7134 11:20:07.221241 TX OE : NO K
7135 11:20:07.221712 All Pass.
7136 11:20:07.222083
7137 11:20:07.224615 CH 1, Rank 0
7138 11:20:07.225086 SW Impedance : PASS
7139 11:20:07.228397 DUTY Scan : NO K
7140 11:20:07.231720 ZQ Calibration : PASS
7141 11:20:07.232299 Jitter Meter : NO K
7142 11:20:07.234155 CBT Training : PASS
7143 11:20:07.237652 Write leveling : PASS
7144 11:20:07.238230 RX DQS gating : PASS
7145 11:20:07.241173 RX DQ/DQS(RDDQC) : PASS
7146 11:20:07.244751 TX DQ/DQS : PASS
7147 11:20:07.245341 RX DATLAT : PASS
7148 11:20:07.247648 RX DQ/DQS(Engine): PASS
7149 11:20:07.248242 TX OE : NO K
7150 11:20:07.250825 All Pass.
7151 11:20:07.251401
7152 11:20:07.251775 CH 1, Rank 1
7153 11:20:07.254589 SW Impedance : PASS
7154 11:20:07.255060 DUTY Scan : NO K
7155 11:20:07.257400 ZQ Calibration : PASS
7156 11:20:07.260766 Jitter Meter : NO K
7157 11:20:07.261338 CBT Training : PASS
7158 11:20:07.264557 Write leveling : NO K
7159 11:20:07.268022 RX DQS gating : PASS
7160 11:20:07.268570 RX DQ/DQS(RDDQC) : PASS
7161 11:20:07.270918 TX DQ/DQS : PASS
7162 11:20:07.274010 RX DATLAT : PASS
7163 11:20:07.274585 RX DQ/DQS(Engine): PASS
7164 11:20:07.277045 TX OE : NO K
7165 11:20:07.277595 All Pass.
7166 11:20:07.277971
7167 11:20:07.280657 DramC Write-DBI off
7168 11:20:07.283745 PER_BANK_REFRESH: Hybrid Mode
7169 11:20:07.284333 TX_TRACKING: ON
7170 11:20:07.294392 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7171 11:20:07.296690 [FAST_K] Save calibration result to emmc
7172 11:20:07.300489 dramc_set_vcore_voltage set vcore to 725000
7173 11:20:07.303585 Read voltage for 1600, 0
7174 11:20:07.304101 Vio18 = 0
7175 11:20:07.306861 Vcore = 725000
7176 11:20:07.307435 Vdram = 0
7177 11:20:07.307915 Vddq = 0
7178 11:20:07.308267 Vmddr = 0
7179 11:20:07.313290 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7180 11:20:07.320467 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7181 11:20:07.321073 MEM_TYPE=3, freq_sel=13
7182 11:20:07.323868 sv_algorithm_assistance_LP4_3733
7183 11:20:07.326519 ============ PULL DRAM RESETB DOWN ============
7184 11:20:07.332757 ========== PULL DRAM RESETB DOWN end =========
7185 11:20:07.336397 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7186 11:20:07.339681 ===================================
7187 11:20:07.343042 LPDDR4 DRAM CONFIGURATION
7188 11:20:07.346010 ===================================
7189 11:20:07.346482 EX_ROW_EN[0] = 0x0
7190 11:20:07.349118 EX_ROW_EN[1] = 0x0
7191 11:20:07.353279 LP4Y_EN = 0x0
7192 11:20:07.353847 WORK_FSP = 0x1
7193 11:20:07.356184 WL = 0x5
7194 11:20:07.356684 RL = 0x5
7195 11:20:07.359428 BL = 0x2
7196 11:20:07.359991 RPST = 0x0
7197 11:20:07.362673 RD_PRE = 0x0
7198 11:20:07.363138 WR_PRE = 0x1
7199 11:20:07.365988 WR_PST = 0x1
7200 11:20:07.366455 DBI_WR = 0x0
7201 11:20:07.369311 DBI_RD = 0x0
7202 11:20:07.369783 OTF = 0x1
7203 11:20:07.372612 ===================================
7204 11:20:07.376187 ===================================
7205 11:20:07.379008 ANA top config
7206 11:20:07.382989 ===================================
7207 11:20:07.383575 DLL_ASYNC_EN = 0
7208 11:20:07.386366 ALL_SLAVE_EN = 0
7209 11:20:07.389308 NEW_RANK_MODE = 1
7210 11:20:07.392899 DLL_IDLE_MODE = 1
7211 11:20:07.395942 LP45_APHY_COMB_EN = 1
7212 11:20:07.396604 TX_ODT_DIS = 0
7213 11:20:07.399005 NEW_8X_MODE = 1
7214 11:20:07.402289 ===================================
7215 11:20:07.406038 ===================================
7216 11:20:07.408761 data_rate = 3200
7217 11:20:07.411998 CKR = 1
7218 11:20:07.415397 DQ_P2S_RATIO = 8
7219 11:20:07.418846 ===================================
7220 11:20:07.421904 CA_P2S_RATIO = 8
7221 11:20:07.422469 DQ_CA_OPEN = 0
7222 11:20:07.425518 DQ_SEMI_OPEN = 0
7223 11:20:07.428705 CA_SEMI_OPEN = 0
7224 11:20:07.432150 CA_FULL_RATE = 0
7225 11:20:07.435659 DQ_CKDIV4_EN = 0
7226 11:20:07.438881 CA_CKDIV4_EN = 0
7227 11:20:07.439496 CA_PREDIV_EN = 0
7228 11:20:07.442073 PH8_DLY = 12
7229 11:20:07.445235 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7230 11:20:07.448278 DQ_AAMCK_DIV = 4
7231 11:20:07.452127 CA_AAMCK_DIV = 4
7232 11:20:07.455354 CA_ADMCK_DIV = 4
7233 11:20:07.455926 DQ_TRACK_CA_EN = 0
7234 11:20:07.458348 CA_PICK = 1600
7235 11:20:07.461910 CA_MCKIO = 1600
7236 11:20:07.465388 MCKIO_SEMI = 0
7237 11:20:07.468154 PLL_FREQ = 3068
7238 11:20:07.471502 DQ_UI_PI_RATIO = 32
7239 11:20:07.474930 CA_UI_PI_RATIO = 0
7240 11:20:07.478095 ===================================
7241 11:20:07.481929 ===================================
7242 11:20:07.482500 memory_type:LPDDR4
7243 11:20:07.484759 GP_NUM : 10
7244 11:20:07.488500 SRAM_EN : 1
7245 11:20:07.489281 MD32_EN : 0
7246 11:20:07.491034 ===================================
7247 11:20:07.495010 [ANA_INIT] >>>>>>>>>>>>>>
7248 11:20:07.497843 <<<<<< [CONFIGURE PHASE]: ANA_TX
7249 11:20:07.501290 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7250 11:20:07.504300 ===================================
7251 11:20:07.507539 data_rate = 3200,PCW = 0X7600
7252 11:20:07.511474 ===================================
7253 11:20:07.514056 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7254 11:20:07.521170 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7255 11:20:07.524069 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7256 11:20:07.531101 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7257 11:20:07.534007 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7258 11:20:07.537230 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7259 11:20:07.537700 [ANA_INIT] flow start
7260 11:20:07.540655 [ANA_INIT] PLL >>>>>>>>
7261 11:20:07.544812 [ANA_INIT] PLL <<<<<<<<
7262 11:20:07.545378 [ANA_INIT] MIDPI >>>>>>>>
7263 11:20:07.547248 [ANA_INIT] MIDPI <<<<<<<<
7264 11:20:07.550573 [ANA_INIT] DLL >>>>>>>>
7265 11:20:07.551040 [ANA_INIT] DLL <<<<<<<<
7266 11:20:07.554608 [ANA_INIT] flow end
7267 11:20:07.557350 ============ LP4 DIFF to SE enter ============
7268 11:20:07.564468 ============ LP4 DIFF to SE exit ============
7269 11:20:07.565078 [ANA_INIT] <<<<<<<<<<<<<
7270 11:20:07.566982 [Flow] Enable top DCM control >>>>>
7271 11:20:07.570655 [Flow] Enable top DCM control <<<<<
7272 11:20:07.573974 Enable DLL master slave shuffle
7273 11:20:07.580278 ==============================================================
7274 11:20:07.580877 Gating Mode config
7275 11:20:07.587723 ==============================================================
7276 11:20:07.591044 Config description:
7277 11:20:07.596978 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7278 11:20:07.603352 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7279 11:20:07.610179 SELPH_MODE 0: By rank 1: By Phase
7280 11:20:07.617021 ==============================================================
7281 11:20:07.620216 GAT_TRACK_EN = 1
7282 11:20:07.620858 RX_GATING_MODE = 2
7283 11:20:07.623381 RX_GATING_TRACK_MODE = 2
7284 11:20:07.626909 SELPH_MODE = 1
7285 11:20:07.630233 PICG_EARLY_EN = 1
7286 11:20:07.633828 VALID_LAT_VALUE = 1
7287 11:20:07.640042 ==============================================================
7288 11:20:07.643204 Enter into Gating configuration >>>>
7289 11:20:07.645976 Exit from Gating configuration <<<<
7290 11:20:07.650152 Enter into DVFS_PRE_config >>>>>
7291 11:20:07.659844 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7292 11:20:07.663219 Exit from DVFS_PRE_config <<<<<
7293 11:20:07.666714 Enter into PICG configuration >>>>
7294 11:20:07.669503 Exit from PICG configuration <<<<
7295 11:20:07.672569 [RX_INPUT] configuration >>>>>
7296 11:20:07.675762 [RX_INPUT] configuration <<<<<
7297 11:20:07.679435 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7298 11:20:07.685909 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7299 11:20:07.692298 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7300 11:20:07.699132 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7301 11:20:07.705552 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7302 11:20:07.709482 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7303 11:20:07.716024 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7304 11:20:07.719128 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7305 11:20:07.722369 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7306 11:20:07.725598 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7307 11:20:07.729274 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7308 11:20:07.735575 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7309 11:20:07.738698 ===================================
7310 11:20:07.741741 LPDDR4 DRAM CONFIGURATION
7311 11:20:07.745229 ===================================
7312 11:20:07.745702 EX_ROW_EN[0] = 0x0
7313 11:20:07.749112 EX_ROW_EN[1] = 0x0
7314 11:20:07.749580 LP4Y_EN = 0x0
7315 11:20:07.752027 WORK_FSP = 0x1
7316 11:20:07.752494 WL = 0x5
7317 11:20:07.755595 RL = 0x5
7318 11:20:07.756064 BL = 0x2
7319 11:20:07.758645 RPST = 0x0
7320 11:20:07.759228 RD_PRE = 0x0
7321 11:20:07.761728 WR_PRE = 0x1
7322 11:20:07.762201 WR_PST = 0x1
7323 11:20:07.764988 DBI_WR = 0x0
7324 11:20:07.768193 DBI_RD = 0x0
7325 11:20:07.768700 OTF = 0x1
7326 11:20:07.771819 ===================================
7327 11:20:07.775495 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7328 11:20:07.778309 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7329 11:20:07.784696 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7330 11:20:07.788444 ===================================
7331 11:20:07.791472 LPDDR4 DRAM CONFIGURATION
7332 11:20:07.794952 ===================================
7333 11:20:07.795435 EX_ROW_EN[0] = 0x10
7334 11:20:07.798426 EX_ROW_EN[1] = 0x0
7335 11:20:07.798991 LP4Y_EN = 0x0
7336 11:20:07.801132 WORK_FSP = 0x1
7337 11:20:07.801599 WL = 0x5
7338 11:20:07.805136 RL = 0x5
7339 11:20:07.805696 BL = 0x2
7340 11:20:07.807945 RPST = 0x0
7341 11:20:07.808512 RD_PRE = 0x0
7342 11:20:07.811328 WR_PRE = 0x1
7343 11:20:07.814379 WR_PST = 0x1
7344 11:20:07.814946 DBI_WR = 0x0
7345 11:20:07.818015 DBI_RD = 0x0
7346 11:20:07.818583 OTF = 0x1
7347 11:20:07.820976 ===================================
7348 11:20:07.827694 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7349 11:20:07.828265 ==
7350 11:20:07.831257 Dram Type= 6, Freq= 0, CH_0, rank 0
7351 11:20:07.834108 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7352 11:20:07.834583 ==
7353 11:20:07.837440 [Duty_Offset_Calibration]
7354 11:20:07.840874 B0:1 B1:-1 CA:0
7355 11:20:07.841464
7356 11:20:07.844165 [DutyScan_Calibration_Flow] k_type=0
7357 11:20:07.852645
7358 11:20:07.853229 ==CLK 0==
7359 11:20:07.855642 Final CLK duty delay cell = 0
7360 11:20:07.859142 [0] MAX Duty = 5125%(X100), DQS PI = 20
7361 11:20:07.862464 [0] MIN Duty = 4907%(X100), DQS PI = 4
7362 11:20:07.862922 [0] AVG Duty = 5016%(X100)
7363 11:20:07.863281
7364 11:20:07.865650 CH0 CLK Duty spec in!! Max-Min= 218%
7365 11:20:07.872490 [DutyScan_Calibration_Flow] ====Done====
7366 11:20:07.872991
7367 11:20:07.875885 [DutyScan_Calibration_Flow] k_type=1
7368 11:20:07.891899
7369 11:20:07.892448 ==DQS 0 ==
7370 11:20:07.895019 Final DQS duty delay cell = -4
7371 11:20:07.898665 [-4] MAX Duty = 4969%(X100), DQS PI = 18
7372 11:20:07.901839 [-4] MIN Duty = 4844%(X100), DQS PI = 54
7373 11:20:07.905216 [-4] AVG Duty = 4906%(X100)
7374 11:20:07.905775
7375 11:20:07.906133 ==DQS 1 ==
7376 11:20:07.908165 Final DQS duty delay cell = 0
7377 11:20:07.911866 [0] MAX Duty = 5156%(X100), DQS PI = 2
7378 11:20:07.915378 [0] MIN Duty = 5031%(X100), DQS PI = 24
7379 11:20:07.918382 [0] AVG Duty = 5093%(X100)
7380 11:20:07.918937
7381 11:20:07.921658 CH0 DQS 0 Duty spec in!! Max-Min= 125%
7382 11:20:07.922214
7383 11:20:07.924916 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7384 11:20:07.928196 [DutyScan_Calibration_Flow] ====Done====
7385 11:20:07.928797
7386 11:20:07.931538 [DutyScan_Calibration_Flow] k_type=3
7387 11:20:07.949343
7388 11:20:07.949893 ==DQM 0 ==
7389 11:20:07.952628 Final DQM duty delay cell = 0
7390 11:20:07.955475 [0] MAX Duty = 5124%(X100), DQS PI = 22
7391 11:20:07.959339 [0] MIN Duty = 4907%(X100), DQS PI = 8
7392 11:20:07.959893 [0] AVG Duty = 5015%(X100)
7393 11:20:07.962379
7394 11:20:07.962933 ==DQM 1 ==
7395 11:20:07.965674 Final DQM duty delay cell = 0
7396 11:20:07.969235 [0] MAX Duty = 5000%(X100), DQS PI = 4
7397 11:20:07.972061 [0] MIN Duty = 4813%(X100), DQS PI = 18
7398 11:20:07.975356 [0] AVG Duty = 4906%(X100)
7399 11:20:07.975816
7400 11:20:07.978760 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7401 11:20:07.979233
7402 11:20:07.982721 CH0 DQM 1 Duty spec in!! Max-Min= 187%
7403 11:20:07.985845 [DutyScan_Calibration_Flow] ====Done====
7404 11:20:07.986414
7405 11:20:07.988480 [DutyScan_Calibration_Flow] k_type=2
7406 11:20:08.005996
7407 11:20:08.006573 ==DQ 0 ==
7408 11:20:08.009178 Final DQ duty delay cell = -4
7409 11:20:08.012152 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7410 11:20:08.015542 [-4] MIN Duty = 4876%(X100), DQS PI = 54
7411 11:20:08.018691 [-4] AVG Duty = 4953%(X100)
7412 11:20:08.019244
7413 11:20:08.019607 ==DQ 1 ==
7414 11:20:08.021851 Final DQ duty delay cell = 0
7415 11:20:08.025412 [0] MAX Duty = 5125%(X100), DQS PI = 48
7416 11:20:08.028474 [0] MIN Duty = 5000%(X100), DQS PI = 36
7417 11:20:08.032149 [0] AVG Duty = 5062%(X100)
7418 11:20:08.032746
7419 11:20:08.035089 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7420 11:20:08.035651
7421 11:20:08.038668 CH0 DQ 1 Duty spec in!! Max-Min= 125%
7422 11:20:08.042013 [DutyScan_Calibration_Flow] ====Done====
7423 11:20:08.042565 ==
7424 11:20:08.045078 Dram Type= 6, Freq= 0, CH_1, rank 0
7425 11:20:08.048233 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7426 11:20:08.048844 ==
7427 11:20:08.051530 [Duty_Offset_Calibration]
7428 11:20:08.052084 B0:-1 B1:1 CA:2
7429 11:20:08.054797
7430 11:20:08.058269 [DutyScan_Calibration_Flow] k_type=0
7431 11:20:08.065996
7432 11:20:08.066570 ==CLK 0==
7433 11:20:08.069753 Final CLK duty delay cell = 0
7434 11:20:08.073293 [0] MAX Duty = 5187%(X100), DQS PI = 24
7435 11:20:08.076187 [0] MIN Duty = 5000%(X100), DQS PI = 0
7436 11:20:08.076723 [0] AVG Duty = 5093%(X100)
7437 11:20:08.079020
7438 11:20:08.082692 CH1 CLK Duty spec in!! Max-Min= 187%
7439 11:20:08.085767 [DutyScan_Calibration_Flow] ====Done====
7440 11:20:08.086237
7441 11:20:08.089378 [DutyScan_Calibration_Flow] k_type=1
7442 11:20:08.105916
7443 11:20:08.106479 ==DQS 0 ==
7444 11:20:08.109074 Final DQS duty delay cell = 0
7445 11:20:08.112348 [0] MAX Duty = 5156%(X100), DQS PI = 20
7446 11:20:08.115750 [0] MIN Duty = 4907%(X100), DQS PI = 10
7447 11:20:08.119425 [0] AVG Duty = 5031%(X100)
7448 11:20:08.119993
7449 11:20:08.120363 ==DQS 1 ==
7450 11:20:08.122050 Final DQS duty delay cell = 0
7451 11:20:08.125208 [0] MAX Duty = 5093%(X100), DQS PI = 26
7452 11:20:08.128904 [0] MIN Duty = 4969%(X100), DQS PI = 56
7453 11:20:08.132057 [0] AVG Duty = 5031%(X100)
7454 11:20:08.132656
7455 11:20:08.135907 CH1 DQS 0 Duty spec in!! Max-Min= 249%
7456 11:20:08.136473
7457 11:20:08.138758 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7458 11:20:08.142133 [DutyScan_Calibration_Flow] ====Done====
7459 11:20:08.142604
7460 11:20:08.145067 [DutyScan_Calibration_Flow] k_type=3
7461 11:20:08.162393
7462 11:20:08.162963 ==DQM 0 ==
7463 11:20:08.165008 Final DQM duty delay cell = -4
7464 11:20:08.169044 [-4] MAX Duty = 5031%(X100), DQS PI = 32
7465 11:20:08.172172 [-4] MIN Duty = 4813%(X100), DQS PI = 8
7466 11:20:08.174976 [-4] AVG Duty = 4922%(X100)
7467 11:20:08.175465
7468 11:20:08.175837 ==DQM 1 ==
7469 11:20:08.178616 Final DQM duty delay cell = 0
7470 11:20:08.181556 [0] MAX Duty = 5156%(X100), DQS PI = 6
7471 11:20:08.185003 [0] MIN Duty = 4969%(X100), DQS PI = 34
7472 11:20:08.187974 [0] AVG Duty = 5062%(X100)
7473 11:20:08.188441
7474 11:20:08.191533 CH1 DQM 0 Duty spec in!! Max-Min= 218%
7475 11:20:08.192005
7476 11:20:08.195107 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7477 11:20:08.197860 [DutyScan_Calibration_Flow] ====Done====
7478 11:20:08.198330
7479 11:20:08.201093 [DutyScan_Calibration_Flow] k_type=2
7480 11:20:08.218888
7481 11:20:08.219459 ==DQ 0 ==
7482 11:20:08.222124 Final DQ duty delay cell = 0
7483 11:20:08.225660 [0] MAX Duty = 5187%(X100), DQS PI = 32
7484 11:20:08.229308 [0] MIN Duty = 4938%(X100), DQS PI = 8
7485 11:20:08.229883 [0] AVG Duty = 5062%(X100)
7486 11:20:08.232340
7487 11:20:08.232973 ==DQ 1 ==
7488 11:20:08.235589 Final DQ duty delay cell = 0
7489 11:20:08.239116 [0] MAX Duty = 5156%(X100), DQS PI = 8
7490 11:20:08.242290 [0] MIN Duty = 4969%(X100), DQS PI = 56
7491 11:20:08.242873 [0] AVG Duty = 5062%(X100)
7492 11:20:08.243253
7493 11:20:08.245453 CH1 DQ 0 Duty spec in!! Max-Min= 249%
7494 11:20:08.248810
7495 11:20:08.252427 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7496 11:20:08.255564 [DutyScan_Calibration_Flow] ====Done====
7497 11:20:08.258631 nWR fixed to 30
7498 11:20:08.259106 [ModeRegInit_LP4] CH0 RK0
7499 11:20:08.262150 [ModeRegInit_LP4] CH0 RK1
7500 11:20:08.265296 [ModeRegInit_LP4] CH1 RK0
7501 11:20:08.268708 [ModeRegInit_LP4] CH1 RK1
7502 11:20:08.269283 match AC timing 5
7503 11:20:08.275196 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7504 11:20:08.278112 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7505 11:20:08.281752 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7506 11:20:08.288598 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7507 11:20:08.291700 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7508 11:20:08.292177 [MiockJmeterHQA]
7509 11:20:08.292584
7510 11:20:08.295153 [DramcMiockJmeter] u1RxGatingPI = 0
7511 11:20:08.298680 0 : 4253, 4026
7512 11:20:08.299264 4 : 4255, 4029
7513 11:20:08.301219 8 : 4258, 4029
7514 11:20:08.301770 12 : 4365, 4140
7515 11:20:08.302304 16 : 4366, 4140
7516 11:20:08.304974 20 : 4363, 4137
7517 11:20:08.305448 24 : 4252, 4027
7518 11:20:08.308269 28 : 4250, 4026
7519 11:20:08.308779 32 : 4363, 4137
7520 11:20:08.311769 36 : 4250, 4027
7521 11:20:08.312371 40 : 4361, 4137
7522 11:20:08.314363 44 : 4250, 4027
7523 11:20:08.314837 48 : 4360, 4137
7524 11:20:08.315215 52 : 4252, 4029
7525 11:20:08.317809 56 : 4250, 4027
7526 11:20:08.318472 60 : 4254, 4029
7527 11:20:08.321142 64 : 4250, 4027
7528 11:20:08.321723 68 : 4363, 4140
7529 11:20:08.324866 72 : 4363, 4140
7530 11:20:08.325343 76 : 4252, 4030
7531 11:20:08.327996 80 : 4252, 4029
7532 11:20:08.328608 84 : 4361, 4137
7533 11:20:08.329006 88 : 4250, 4025
7534 11:20:08.331215 92 : 4363, 334
7535 11:20:08.331797 96 : 4253, 0
7536 11:20:08.334551 100 : 4250, 0
7537 11:20:08.335286 104 : 4363, 0
7538 11:20:08.335749 108 : 4363, 0
7539 11:20:08.337665 112 : 4250, 0
7540 11:20:08.338145 116 : 4250, 0
7541 11:20:08.340820 120 : 4250, 0
7542 11:20:08.341400 124 : 4253, 0
7543 11:20:08.341783 128 : 4250, 0
7544 11:20:08.345086 132 : 4250, 0
7545 11:20:08.345660 136 : 4253, 0
7546 11:20:08.348014 140 : 4360, 0
7547 11:20:08.348661 144 : 4361, 0
7548 11:20:08.349091 148 : 4363, 0
7549 11:20:08.350902 152 : 4250, 0
7550 11:20:08.351502 156 : 4363, 0
7551 11:20:08.354062 160 : 4250, 0
7552 11:20:08.354547 164 : 4250, 0
7553 11:20:08.354932 168 : 4250, 0
7554 11:20:08.357611 172 : 4250, 0
7555 11:20:08.358092 176 : 4253, 0
7556 11:20:08.361037 180 : 4250, 0
7557 11:20:08.361626 184 : 4250, 0
7558 11:20:08.362043 188 : 4253, 0
7559 11:20:08.364030 192 : 4361, 0
7560 11:20:08.364643 196 : 4360, 0
7561 11:20:08.365036 200 : 4363, 0
7562 11:20:08.367078 204 : 4250, 0
7563 11:20:08.367558 208 : 4360, 0
7564 11:20:08.370259 212 : 4250, 0
7565 11:20:08.370740 216 : 4250, 0
7566 11:20:08.373451 220 : 4250, 0
7567 11:20:08.374040 224 : 4250, 125
7568 11:20:08.374668 228 : 4250, 3225
7569 11:20:08.376971 232 : 4250, 4027
7570 11:20:08.377454 236 : 4363, 4140
7571 11:20:08.380155 240 : 4252, 4029
7572 11:20:08.380678 244 : 4250, 4027
7573 11:20:08.384082 248 : 4250, 4027
7574 11:20:08.384725 252 : 4252, 4029
7575 11:20:08.387203 256 : 4252, 4029
7576 11:20:08.387789 260 : 4363, 4140
7577 11:20:08.390794 264 : 4250, 4027
7578 11:20:08.391407 268 : 4252, 4029
7579 11:20:08.394534 272 : 4250, 4026
7580 11:20:08.395124 276 : 4363, 4140
7581 11:20:08.396694 280 : 4361, 4137
7582 11:20:08.397179 284 : 4250, 4027
7583 11:20:08.397563 288 : 4252, 4029
7584 11:20:08.400016 292 : 4252, 4029
7585 11:20:08.400499 296 : 4250, 4026
7586 11:20:08.403208 300 : 4250, 4027
7587 11:20:08.403687 304 : 4253, 4029
7588 11:20:08.406900 308 : 4252, 4029
7589 11:20:08.407487 312 : 4363, 4140
7590 11:20:08.410666 316 : 4250, 4027
7591 11:20:08.411149 320 : 4250, 4027
7592 11:20:08.413667 324 : 4250, 4026
7593 11:20:08.414194 328 : 4363, 4140
7594 11:20:08.416603 332 : 4361, 4137
7595 11:20:08.417083 336 : 4247, 3695
7596 11:20:08.419931 340 : 4363, 2064
7597 11:20:08.420410
7598 11:20:08.420844 MIOCK jitter meter ch=0
7599 11:20:08.421202
7600 11:20:08.422874 1T = (340-92) = 248 dly cells
7601 11:20:08.429864 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7602 11:20:08.430422 ==
7603 11:20:08.433621 Dram Type= 6, Freq= 0, CH_0, rank 0
7604 11:20:08.437143 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7605 11:20:08.437710 ==
7606 11:20:08.443603 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7607 11:20:08.446851 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7608 11:20:08.450272 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7609 11:20:08.456792 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7610 11:20:08.465966 [CA 0] Center 43 (12~74) winsize 63
7611 11:20:08.469402 [CA 1] Center 43 (13~73) winsize 61
7612 11:20:08.472420 [CA 2] Center 38 (9~68) winsize 60
7613 11:20:08.475665 [CA 3] Center 38 (9~68) winsize 60
7614 11:20:08.479555 [CA 4] Center 36 (7~66) winsize 60
7615 11:20:08.482840 [CA 5] Center 35 (6~65) winsize 60
7616 11:20:08.483413
7617 11:20:08.485528 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7618 11:20:08.486001
7619 11:20:08.491987 [CATrainingPosCal] consider 1 rank data
7620 11:20:08.492601 u2DelayCellTimex100 = 262/100 ps
7621 11:20:08.499257 CA0 delay=43 (12~74),Diff = 8 PI (29 cell)
7622 11:20:08.502196 CA1 delay=43 (13~73),Diff = 8 PI (29 cell)
7623 11:20:08.505453 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7624 11:20:08.508788 CA3 delay=38 (9~68),Diff = 3 PI (11 cell)
7625 11:20:08.512411 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7626 11:20:08.515057 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7627 11:20:08.515534
7628 11:20:08.519100 CA PerBit enable=1, Macro0, CA PI delay=35
7629 11:20:08.519691
7630 11:20:08.521731 [CBTSetCACLKResult] CA Dly = 35
7631 11:20:08.525103 CS Dly: 12 (0~43)
7632 11:20:08.528658 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7633 11:20:08.531921 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7634 11:20:08.532499 ==
7635 11:20:08.535131 Dram Type= 6, Freq= 0, CH_0, rank 1
7636 11:20:08.541640 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7637 11:20:08.542224 ==
7638 11:20:08.544981 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7639 11:20:08.551541 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7640 11:20:08.555368 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7641 11:20:08.561389 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7642 11:20:08.569891 [CA 0] Center 43 (13~74) winsize 62
7643 11:20:08.573308 [CA 1] Center 44 (14~74) winsize 61
7644 11:20:08.576124 [CA 2] Center 38 (9~68) winsize 60
7645 11:20:08.579812 [CA 3] Center 38 (9~68) winsize 60
7646 11:20:08.583497 [CA 4] Center 36 (7~66) winsize 60
7647 11:20:08.585751 [CA 5] Center 36 (7~66) winsize 60
7648 11:20:08.586227
7649 11:20:08.588990 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7650 11:20:08.589466
7651 11:20:08.593218 [CATrainingPosCal] consider 2 rank data
7652 11:20:08.596149 u2DelayCellTimex100 = 262/100 ps
7653 11:20:08.602324 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7654 11:20:08.606048 CA1 delay=43 (14~73),Diff = 7 PI (26 cell)
7655 11:20:08.609155 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7656 11:20:08.612426 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7657 11:20:08.615685 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7658 11:20:08.618873 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7659 11:20:08.619352
7660 11:20:08.622354 CA PerBit enable=1, Macro0, CA PI delay=36
7661 11:20:08.622830
7662 11:20:08.625260 [CBTSetCACLKResult] CA Dly = 36
7663 11:20:08.628888 CS Dly: 12 (0~44)
7664 11:20:08.632325 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7665 11:20:08.635223 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7666 11:20:08.635813
7667 11:20:08.638889 ----->DramcWriteLeveling(PI) begin...
7668 11:20:08.639365 ==
7669 11:20:08.642585 Dram Type= 6, Freq= 0, CH_0, rank 0
7670 11:20:08.648577 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7671 11:20:08.649149 ==
7672 11:20:08.652175 Write leveling (Byte 0): 36 => 36
7673 11:20:08.655138 Write leveling (Byte 1): 28 => 28
7674 11:20:08.655607 DramcWriteLeveling(PI) end<-----
7675 11:20:08.658745
7676 11:20:08.659312 ==
7677 11:20:08.662164 Dram Type= 6, Freq= 0, CH_0, rank 0
7678 11:20:08.665424 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7679 11:20:08.666000 ==
7680 11:20:08.668393 [Gating] SW mode calibration
7681 11:20:08.674894 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7682 11:20:08.678457 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7683 11:20:08.685412 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7684 11:20:08.688085 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7685 11:20:08.691772 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7686 11:20:08.697947 1 4 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7687 11:20:08.701560 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7688 11:20:08.705275 1 4 20 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
7689 11:20:08.711719 1 4 24 | B1->B0 | 2e2e 3434 | 1 1 | (1 1) (1 1)
7690 11:20:08.715249 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7691 11:20:08.717943 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7692 11:20:08.724805 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7693 11:20:08.728239 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7694 11:20:08.730972 1 5 12 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
7695 11:20:08.738021 1 5 16 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
7696 11:20:08.741482 1 5 20 | B1->B0 | 3232 2323 | 0 0 | (1 0) (0 0)
7697 11:20:08.744280 1 5 24 | B1->B0 | 2424 2323 | 1 0 | (1 0) (0 0)
7698 11:20:08.750940 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7699 11:20:08.754452 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7700 11:20:08.757852 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7701 11:20:08.764488 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7702 11:20:08.767890 1 6 12 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
7703 11:20:08.771196 1 6 16 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
7704 11:20:08.777128 1 6 20 | B1->B0 | 2c2b 4646 | 1 0 | (0 0) (0 0)
7705 11:20:08.780657 1 6 24 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
7706 11:20:08.783916 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7707 11:20:08.790729 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7708 11:20:08.793925 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7709 11:20:08.797228 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7710 11:20:08.803689 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7711 11:20:08.807199 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7712 11:20:08.810002 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7713 11:20:08.817036 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7714 11:20:08.820153 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7715 11:20:08.823887 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7716 11:20:08.830016 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7717 11:20:08.833488 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7718 11:20:08.837182 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7719 11:20:08.843557 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7720 11:20:08.846916 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7721 11:20:08.850209 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7722 11:20:08.856339 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7723 11:20:08.859284 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7724 11:20:08.862608 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7725 11:20:08.870035 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7726 11:20:08.873060 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7727 11:20:08.876169 Total UI for P1: 0, mck2ui 16
7728 11:20:08.879646 best dqsien dly found for B0: ( 1, 9, 8)
7729 11:20:08.882931 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7730 11:20:08.889536 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7731 11:20:08.892426 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7732 11:20:08.896798 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7733 11:20:08.899115 Total UI for P1: 0, mck2ui 16
7734 11:20:08.902192 best dqsien dly found for B1: ( 1, 9, 22)
7735 11:20:08.905851 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
7736 11:20:08.909466 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7737 11:20:08.912251
7738 11:20:08.916054 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
7739 11:20:08.918939 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7740 11:20:08.922654 [Gating] SW calibration Done
7741 11:20:08.923276 ==
7742 11:20:08.925696 Dram Type= 6, Freq= 0, CH_0, rank 0
7743 11:20:08.929333 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7744 11:20:08.929902 ==
7745 11:20:08.930275 RX Vref Scan: 0
7746 11:20:08.932800
7747 11:20:08.933381 RX Vref 0 -> 0, step: 1
7748 11:20:08.933764
7749 11:20:08.935795 RX Delay 0 -> 252, step: 8
7750 11:20:08.939131 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7751 11:20:08.942300 iDelay=200, Bit 1, Center 135 (88 ~ 183) 96
7752 11:20:08.949055 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7753 11:20:08.952507 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7754 11:20:08.955704 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7755 11:20:08.958970 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7756 11:20:08.962134 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7757 11:20:08.968431 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7758 11:20:08.971475 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7759 11:20:08.975047 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7760 11:20:08.978247 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7761 11:20:08.981724 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7762 11:20:08.988278 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7763 11:20:08.991815 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7764 11:20:08.995119 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7765 11:20:08.998510 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7766 11:20:08.999090 ==
7767 11:20:09.001337 Dram Type= 6, Freq= 0, CH_0, rank 0
7768 11:20:09.008458 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7769 11:20:09.009096 ==
7770 11:20:09.009579 DQS Delay:
7771 11:20:09.011126 DQS0 = 0, DQS1 = 0
7772 11:20:09.011634 DQM Delay:
7773 11:20:09.014507 DQM0 = 134, DQM1 = 126
7774 11:20:09.014984 DQ Delay:
7775 11:20:09.018130 DQ0 =135, DQ1 =135, DQ2 =131, DQ3 =131
7776 11:20:09.021260 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =147
7777 11:20:09.024899 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
7778 11:20:09.027977 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =131
7779 11:20:09.028574
7780 11:20:09.029063
7781 11:20:09.029508 ==
7782 11:20:09.030863 Dram Type= 6, Freq= 0, CH_0, rank 0
7783 11:20:09.037523 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7784 11:20:09.038083 ==
7785 11:20:09.038565
7786 11:20:09.039007
7787 11:20:09.039438 TX Vref Scan disable
7788 11:20:09.041703 == TX Byte 0 ==
7789 11:20:09.044843 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7790 11:20:09.051279 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7791 11:20:09.051854 == TX Byte 1 ==
7792 11:20:09.054252 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7793 11:20:09.061392 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7794 11:20:09.061964 ==
7795 11:20:09.064132 Dram Type= 6, Freq= 0, CH_0, rank 0
7796 11:20:09.067674 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7797 11:20:09.068275 ==
7798 11:20:09.080828
7799 11:20:09.084194 TX Vref early break, caculate TX vref
7800 11:20:09.087531 TX Vref=16, minBit 1, minWin=22, winSum=370
7801 11:20:09.090611 TX Vref=18, minBit 4, minWin=22, winSum=382
7802 11:20:09.093749 TX Vref=20, minBit 14, minWin=23, winSum=393
7803 11:20:09.097100 TX Vref=22, minBit 3, minWin=24, winSum=400
7804 11:20:09.100486 TX Vref=24, minBit 4, minWin=24, winSum=415
7805 11:20:09.107237 TX Vref=26, minBit 1, minWin=25, winSum=415
7806 11:20:09.110538 TX Vref=28, minBit 4, minWin=24, winSum=418
7807 11:20:09.113895 TX Vref=30, minBit 0, minWin=24, winSum=414
7808 11:20:09.117257 TX Vref=32, minBit 0, minWin=24, winSum=404
7809 11:20:09.120582 TX Vref=34, minBit 5, minWin=23, winSum=388
7810 11:20:09.127207 [TxChooseVref] Worse bit 1, Min win 25, Win sum 415, Final Vref 26
7811 11:20:09.127782
7812 11:20:09.130248 Final TX Range 0 Vref 26
7813 11:20:09.130824
7814 11:20:09.131302 ==
7815 11:20:09.133855 Dram Type= 6, Freq= 0, CH_0, rank 0
7816 11:20:09.137411 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7817 11:20:09.137923 ==
7818 11:20:09.138400
7819 11:20:09.138848
7820 11:20:09.140155 TX Vref Scan disable
7821 11:20:09.146672 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7822 11:20:09.147247 == TX Byte 0 ==
7823 11:20:09.150156 u2DelayCellOfst[0]=14 cells (4 PI)
7824 11:20:09.153473 u2DelayCellOfst[1]=18 cells (5 PI)
7825 11:20:09.156357 u2DelayCellOfst[2]=11 cells (3 PI)
7826 11:20:09.159945 u2DelayCellOfst[3]=18 cells (5 PI)
7827 11:20:09.163502 u2DelayCellOfst[4]=11 cells (3 PI)
7828 11:20:09.166855 u2DelayCellOfst[5]=0 cells (0 PI)
7829 11:20:09.169929 u2DelayCellOfst[6]=18 cells (5 PI)
7830 11:20:09.173563 u2DelayCellOfst[7]=18 cells (5 PI)
7831 11:20:09.176232 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7832 11:20:09.179700 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
7833 11:20:09.182831 == TX Byte 1 ==
7834 11:20:09.186105 u2DelayCellOfst[8]=0 cells (0 PI)
7835 11:20:09.189964 u2DelayCellOfst[9]=0 cells (0 PI)
7836 11:20:09.192765 u2DelayCellOfst[10]=7 cells (2 PI)
7837 11:20:09.193247 u2DelayCellOfst[11]=0 cells (0 PI)
7838 11:20:09.196454 u2DelayCellOfst[12]=11 cells (3 PI)
7839 11:20:09.200296 u2DelayCellOfst[13]=11 cells (3 PI)
7840 11:20:09.202890 u2DelayCellOfst[14]=14 cells (4 PI)
7841 11:20:09.206129 u2DelayCellOfst[15]=11 cells (3 PI)
7842 11:20:09.212758 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7843 11:20:09.216132 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7844 11:20:09.216652 DramC Write-DBI on
7845 11:20:09.219498 ==
7846 11:20:09.220072 Dram Type= 6, Freq= 0, CH_0, rank 0
7847 11:20:09.226372 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7848 11:20:09.226939 ==
7849 11:20:09.227319
7850 11:20:09.227666
7851 11:20:09.229218 TX Vref Scan disable
7852 11:20:09.229696 == TX Byte 0 ==
7853 11:20:09.235909 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7854 11:20:09.236503 == TX Byte 1 ==
7855 11:20:09.239210 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
7856 11:20:09.242172 DramC Write-DBI off
7857 11:20:09.242646
7858 11:20:09.243021 [DATLAT]
7859 11:20:09.246010 Freq=1600, CH0 RK0
7860 11:20:09.246590
7861 11:20:09.246969 DATLAT Default: 0xf
7862 11:20:09.249032 0, 0xFFFF, sum = 0
7863 11:20:09.249620 1, 0xFFFF, sum = 0
7864 11:20:09.252481 2, 0xFFFF, sum = 0
7865 11:20:09.253119 3, 0xFFFF, sum = 0
7866 11:20:09.255581 4, 0xFFFF, sum = 0
7867 11:20:09.256137 5, 0xFFFF, sum = 0
7868 11:20:09.259052 6, 0xFFFF, sum = 0
7869 11:20:09.262036 7, 0xFFFF, sum = 0
7870 11:20:09.262518 8, 0xFFFF, sum = 0
7871 11:20:09.265251 9, 0xFFFF, sum = 0
7872 11:20:09.265734 10, 0xFFFF, sum = 0
7873 11:20:09.268756 11, 0xFFFF, sum = 0
7874 11:20:09.269237 12, 0xFFFF, sum = 0
7875 11:20:09.271841 13, 0xFFFF, sum = 0
7876 11:20:09.272324 14, 0x0, sum = 1
7877 11:20:09.275253 15, 0x0, sum = 2
7878 11:20:09.275809 16, 0x0, sum = 3
7879 11:20:09.278483 17, 0x0, sum = 4
7880 11:20:09.278982 best_step = 15
7881 11:20:09.279364
7882 11:20:09.279715 ==
7883 11:20:09.281638 Dram Type= 6, Freq= 0, CH_0, rank 0
7884 11:20:09.285205 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7885 11:20:09.288492 ==
7886 11:20:09.289108 RX Vref Scan: 1
7887 11:20:09.289489
7888 11:20:09.292092 Set Vref Range= 24 -> 127
7889 11:20:09.292611
7890 11:20:09.295163 RX Vref 24 -> 127, step: 1
7891 11:20:09.295731
7892 11:20:09.296108 RX Delay 19 -> 252, step: 4
7893 11:20:09.296460
7894 11:20:09.298470 Set Vref, RX VrefLevel [Byte0]: 24
7895 11:20:09.301390 [Byte1]: 24
7896 11:20:09.305997
7897 11:20:09.306473 Set Vref, RX VrefLevel [Byte0]: 25
7898 11:20:09.309087 [Byte1]: 25
7899 11:20:09.313196
7900 11:20:09.313763 Set Vref, RX VrefLevel [Byte0]: 26
7901 11:20:09.316262 [Byte1]: 26
7902 11:20:09.320772
7903 11:20:09.321335 Set Vref, RX VrefLevel [Byte0]: 27
7904 11:20:09.327583 [Byte1]: 27
7905 11:20:09.328154
7906 11:20:09.330614 Set Vref, RX VrefLevel [Byte0]: 28
7907 11:20:09.334214 [Byte1]: 28
7908 11:20:09.334783
7909 11:20:09.336887 Set Vref, RX VrefLevel [Byte0]: 29
7910 11:20:09.340690 [Byte1]: 29
7911 11:20:09.341261
7912 11:20:09.344082 Set Vref, RX VrefLevel [Byte0]: 30
7913 11:20:09.347129 [Byte1]: 30
7914 11:20:09.351273
7915 11:20:09.351862 Set Vref, RX VrefLevel [Byte0]: 31
7916 11:20:09.354220 [Byte1]: 31
7917 11:20:09.358700
7918 11:20:09.359275 Set Vref, RX VrefLevel [Byte0]: 32
7919 11:20:09.361981 [Byte1]: 32
7920 11:20:09.366871
7921 11:20:09.367441 Set Vref, RX VrefLevel [Byte0]: 33
7922 11:20:09.369239 [Byte1]: 33
7923 11:20:09.373740
7924 11:20:09.374307 Set Vref, RX VrefLevel [Byte0]: 34
7925 11:20:09.377176 [Byte1]: 34
7926 11:20:09.381183
7927 11:20:09.381656 Set Vref, RX VrefLevel [Byte0]: 35
7928 11:20:09.384629 [Byte1]: 35
7929 11:20:09.389214
7930 11:20:09.389782 Set Vref, RX VrefLevel [Byte0]: 36
7931 11:20:09.392639 [Byte1]: 36
7932 11:20:09.396621
7933 11:20:09.397209 Set Vref, RX VrefLevel [Byte0]: 37
7934 11:20:09.399742 [Byte1]: 37
7935 11:20:09.404217
7936 11:20:09.404731 Set Vref, RX VrefLevel [Byte0]: 38
7937 11:20:09.407435 [Byte1]: 38
7938 11:20:09.411482
7939 11:20:09.412052 Set Vref, RX VrefLevel [Byte0]: 39
7940 11:20:09.415242 [Byte1]: 39
7941 11:20:09.419659
7942 11:20:09.420224 Set Vref, RX VrefLevel [Byte0]: 40
7943 11:20:09.422719 [Byte1]: 40
7944 11:20:09.426587
7945 11:20:09.427078 Set Vref, RX VrefLevel [Byte0]: 41
7946 11:20:09.430425 [Byte1]: 41
7947 11:20:09.435037
7948 11:20:09.435601 Set Vref, RX VrefLevel [Byte0]: 42
7949 11:20:09.437444 [Byte1]: 42
7950 11:20:09.442254
7951 11:20:09.442816 Set Vref, RX VrefLevel [Byte0]: 43
7952 11:20:09.445409 [Byte1]: 43
7953 11:20:09.449323
7954 11:20:09.449889 Set Vref, RX VrefLevel [Byte0]: 44
7955 11:20:09.452461 [Byte1]: 44
7956 11:20:09.457258
7957 11:20:09.457824 Set Vref, RX VrefLevel [Byte0]: 45
7958 11:20:09.460506 [Byte1]: 45
7959 11:20:09.464665
7960 11:20:09.465238 Set Vref, RX VrefLevel [Byte0]: 46
7961 11:20:09.468189 [Byte1]: 46
7962 11:20:09.472807
7963 11:20:09.473425 Set Vref, RX VrefLevel [Byte0]: 47
7964 11:20:09.475532 [Byte1]: 47
7965 11:20:09.479661
7966 11:20:09.480132 Set Vref, RX VrefLevel [Byte0]: 48
7967 11:20:09.483214 [Byte1]: 48
7968 11:20:09.487745
7969 11:20:09.488312 Set Vref, RX VrefLevel [Byte0]: 49
7970 11:20:09.490776 [Byte1]: 49
7971 11:20:09.495546
7972 11:20:09.496111 Set Vref, RX VrefLevel [Byte0]: 50
7973 11:20:09.498614 [Byte1]: 50
7974 11:20:09.502520
7975 11:20:09.503084 Set Vref, RX VrefLevel [Byte0]: 51
7976 11:20:09.505595 [Byte1]: 51
7977 11:20:09.510582
7978 11:20:09.511143 Set Vref, RX VrefLevel [Byte0]: 52
7979 11:20:09.513238 [Byte1]: 52
7980 11:20:09.517838
7981 11:20:09.518412 Set Vref, RX VrefLevel [Byte0]: 53
7982 11:20:09.520957 [Byte1]: 53
7983 11:20:09.525140
7984 11:20:09.525762 Set Vref, RX VrefLevel [Byte0]: 54
7985 11:20:09.528671 [Byte1]: 54
7986 11:20:09.532978
7987 11:20:09.533542 Set Vref, RX VrefLevel [Byte0]: 55
7988 11:20:09.536576 [Byte1]: 55
7989 11:20:09.540678
7990 11:20:09.541246 Set Vref, RX VrefLevel [Byte0]: 56
7991 11:20:09.543801 [Byte1]: 56
7992 11:20:09.548684
7993 11:20:09.549250 Set Vref, RX VrefLevel [Byte0]: 57
7994 11:20:09.551462 [Byte1]: 57
7995 11:20:09.555409
7996 11:20:09.558446 Set Vref, RX VrefLevel [Byte0]: 58
7997 11:20:09.562790 [Byte1]: 58
7998 11:20:09.563360
7999 11:20:09.565080 Set Vref, RX VrefLevel [Byte0]: 59
8000 11:20:09.568223 [Byte1]: 59
8001 11:20:09.568816
8002 11:20:09.571914 Set Vref, RX VrefLevel [Byte0]: 60
8003 11:20:09.575237 [Byte1]: 60
8004 11:20:09.575706
8005 11:20:09.578138 Set Vref, RX VrefLevel [Byte0]: 61
8006 11:20:09.581309 [Byte1]: 61
8007 11:20:09.585780
8008 11:20:09.586346 Set Vref, RX VrefLevel [Byte0]: 62
8009 11:20:09.588920 [Byte1]: 62
8010 11:20:09.593078
8011 11:20:09.593545 Set Vref, RX VrefLevel [Byte0]: 63
8012 11:20:09.596458 [Byte1]: 63
8013 11:20:09.601142
8014 11:20:09.601710 Set Vref, RX VrefLevel [Byte0]: 64
8015 11:20:09.604105 [Byte1]: 64
8016 11:20:09.609073
8017 11:20:09.609647 Set Vref, RX VrefLevel [Byte0]: 65
8018 11:20:09.611564 [Byte1]: 65
8019 11:20:09.616089
8020 11:20:09.616807 Set Vref, RX VrefLevel [Byte0]: 66
8021 11:20:09.619325 [Byte1]: 66
8022 11:20:09.623783
8023 11:20:09.624364 Set Vref, RX VrefLevel [Byte0]: 67
8024 11:20:09.626916 [Byte1]: 67
8025 11:20:09.631682
8026 11:20:09.632241 Set Vref, RX VrefLevel [Byte0]: 68
8027 11:20:09.635027 [Byte1]: 68
8028 11:20:09.638948
8029 11:20:09.639476 Set Vref, RX VrefLevel [Byte0]: 69
8030 11:20:09.641918 [Byte1]: 69
8031 11:20:09.646857
8032 11:20:09.647457 Set Vref, RX VrefLevel [Byte0]: 70
8033 11:20:09.649994 [Byte1]: 70
8034 11:20:09.653582
8035 11:20:09.654048 Set Vref, RX VrefLevel [Byte0]: 71
8036 11:20:09.657036 [Byte1]: 71
8037 11:20:09.661784
8038 11:20:09.662346 Set Vref, RX VrefLevel [Byte0]: 72
8039 11:20:09.665080 [Byte1]: 72
8040 11:20:09.668864
8041 11:20:09.669452 Set Vref, RX VrefLevel [Byte0]: 73
8042 11:20:09.672977 [Byte1]: 73
8043 11:20:09.676318
8044 11:20:09.676818 Set Vref, RX VrefLevel [Byte0]: 74
8045 11:20:09.679964 [Byte1]: 74
8046 11:20:09.684484
8047 11:20:09.685090 Set Vref, RX VrefLevel [Byte0]: 75
8048 11:20:09.690630 [Byte1]: 75
8049 11:20:09.691183
8050 11:20:09.694268 Set Vref, RX VrefLevel [Byte0]: 76
8051 11:20:09.697246 [Byte1]: 76
8052 11:20:09.697714
8053 11:20:09.700304 Set Vref, RX VrefLevel [Byte0]: 77
8054 11:20:09.703695 [Byte1]: 77
8055 11:20:09.704261
8056 11:20:09.707416 Set Vref, RX VrefLevel [Byte0]: 78
8057 11:20:09.710216 [Byte1]: 78
8058 11:20:09.714542
8059 11:20:09.715007 Set Vref, RX VrefLevel [Byte0]: 79
8060 11:20:09.717509 [Byte1]: 79
8061 11:20:09.722051
8062 11:20:09.722521 Final RX Vref Byte 0 = 68 to rank0
8063 11:20:09.725275 Final RX Vref Byte 1 = 59 to rank0
8064 11:20:09.728642 Final RX Vref Byte 0 = 68 to rank1
8065 11:20:09.731888 Final RX Vref Byte 1 = 59 to rank1==
8066 11:20:09.735154 Dram Type= 6, Freq= 0, CH_0, rank 0
8067 11:20:09.741808 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8068 11:20:09.742284 ==
8069 11:20:09.742654 DQS Delay:
8070 11:20:09.745881 DQS0 = 0, DQS1 = 0
8071 11:20:09.746639 DQM Delay:
8072 11:20:09.747045 DQM0 = 133, DQM1 = 123
8073 11:20:09.748593 DQ Delay:
8074 11:20:09.752651 DQ0 =132, DQ1 =136, DQ2 =132, DQ3 =132
8075 11:20:09.755102 DQ4 =132, DQ5 =122, DQ6 =142, DQ7 =140
8076 11:20:09.758207 DQ8 =116, DQ9 =112, DQ10 =124, DQ11 =120
8077 11:20:09.762200 DQ12 =128, DQ13 =128, DQ14 =134, DQ15 =128
8078 11:20:09.762771
8079 11:20:09.763142
8080 11:20:09.763482
8081 11:20:09.765135 [DramC_TX_OE_Calibration] TA2
8082 11:20:09.768673 Original DQ_B0 (3 6) =30, OEN = 27
8083 11:20:09.771720 Original DQ_B1 (3 6) =30, OEN = 27
8084 11:20:09.774638 24, 0x0, End_B0=24 End_B1=24
8085 11:20:09.775108 25, 0x0, End_B0=25 End_B1=25
8086 11:20:09.778274 26, 0x0, End_B0=26 End_B1=26
8087 11:20:09.781403 27, 0x0, End_B0=27 End_B1=27
8088 11:20:09.784906 28, 0x0, End_B0=28 End_B1=28
8089 11:20:09.788292 29, 0x0, End_B0=29 End_B1=29
8090 11:20:09.788909 30, 0x0, End_B0=30 End_B1=30
8091 11:20:09.791612 31, 0x4141, End_B0=30 End_B1=30
8092 11:20:09.794685 Byte0 end_step=30 best_step=27
8093 11:20:09.798011 Byte1 end_step=30 best_step=27
8094 11:20:09.801419 Byte0 TX OE(2T, 0.5T) = (3, 3)
8095 11:20:09.804670 Byte1 TX OE(2T, 0.5T) = (3, 3)
8096 11:20:09.805136
8097 11:20:09.805501
8098 11:20:09.811113 [DQSOSCAuto] RK0, (LSB)MR18= 0x2213, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 392 ps
8099 11:20:09.814362 CH0 RK0: MR19=303, MR18=2213
8100 11:20:09.821162 CH0_RK0: MR19=0x303, MR18=0x2213, DQSOSC=392, MR23=63, INC=24, DEC=16
8101 11:20:09.821633
8102 11:20:09.824473 ----->DramcWriteLeveling(PI) begin...
8103 11:20:09.825089 ==
8104 11:20:09.827630 Dram Type= 6, Freq= 0, CH_0, rank 1
8105 11:20:09.831470 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8106 11:20:09.832045 ==
8107 11:20:09.834639 Write leveling (Byte 0): 37 => 37
8108 11:20:09.838129 Write leveling (Byte 1): 26 => 26
8109 11:20:09.840960 DramcWriteLeveling(PI) end<-----
8110 11:20:09.841539
8111 11:20:09.841913 ==
8112 11:20:09.844609 Dram Type= 6, Freq= 0, CH_0, rank 1
8113 11:20:09.847642 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8114 11:20:09.848205 ==
8115 11:20:09.851363 [Gating] SW mode calibration
8116 11:20:09.857416 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8117 11:20:09.864558 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8118 11:20:09.867594 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8119 11:20:09.873954 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8120 11:20:09.877271 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8121 11:20:09.880992 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8122 11:20:09.887273 1 4 16 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
8123 11:20:09.890054 1 4 20 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
8124 11:20:09.894152 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8125 11:20:09.900244 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8126 11:20:09.903567 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8127 11:20:09.907303 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8128 11:20:09.913860 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8129 11:20:09.916582 1 5 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8130 11:20:09.920147 1 5 16 | B1->B0 | 3434 2929 | 1 0 | (1 0) (0 0)
8131 11:20:09.926887 1 5 20 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
8132 11:20:09.930126 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8133 11:20:09.933321 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8134 11:20:09.939901 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8135 11:20:09.943242 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8136 11:20:09.946536 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8137 11:20:09.953177 1 6 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
8138 11:20:09.956344 1 6 16 | B1->B0 | 2323 4242 | 0 0 | (0 0) (0 0)
8139 11:20:09.959928 1 6 20 | B1->B0 | 3131 4646 | 0 0 | (0 0) (0 0)
8140 11:20:09.966313 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8141 11:20:09.969508 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8142 11:20:09.972755 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8143 11:20:09.979861 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8144 11:20:09.983130 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8145 11:20:09.986128 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8146 11:20:09.993028 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8147 11:20:09.996112 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8148 11:20:09.999938 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8149 11:20:10.005894 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8150 11:20:10.009221 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8151 11:20:10.012871 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8152 11:20:10.019291 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8153 11:20:10.022435 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8154 11:20:10.025715 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8155 11:20:10.032314 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8156 11:20:10.036096 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8157 11:20:10.038996 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8158 11:20:10.045339 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8159 11:20:10.048863 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8160 11:20:10.052725 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8161 11:20:10.058319 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8162 11:20:10.061968 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8163 11:20:10.065330 Total UI for P1: 0, mck2ui 16
8164 11:20:10.069082 best dqsien dly found for B0: ( 1, 9, 10)
8165 11:20:10.072119 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8166 11:20:10.078480 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8167 11:20:10.079057 Total UI for P1: 0, mck2ui 16
8168 11:20:10.084767 best dqsien dly found for B1: ( 1, 9, 18)
8169 11:20:10.088698 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8170 11:20:10.091556 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8171 11:20:10.092137
8172 11:20:10.095389 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8173 11:20:10.098678 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8174 11:20:10.101252 [Gating] SW calibration Done
8175 11:20:10.101727 ==
8176 11:20:10.104973 Dram Type= 6, Freq= 0, CH_0, rank 1
8177 11:20:10.108427 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8178 11:20:10.109101 ==
8179 11:20:10.111357 RX Vref Scan: 0
8180 11:20:10.111841
8181 11:20:10.112213 RX Vref 0 -> 0, step: 1
8182 11:20:10.114475
8183 11:20:10.114948 RX Delay 0 -> 252, step: 8
8184 11:20:10.117954 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8185 11:20:10.125197 iDelay=200, Bit 1, Center 139 (80 ~ 199) 120
8186 11:20:10.128166 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8187 11:20:10.131825 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8188 11:20:10.134591 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8189 11:20:10.141359 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8190 11:20:10.144452 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8191 11:20:10.147768 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8192 11:20:10.151111 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8193 11:20:10.154538 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8194 11:20:10.161078 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8195 11:20:10.164311 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8196 11:20:10.167840 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8197 11:20:10.170530 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8198 11:20:10.174243 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8199 11:20:10.180722 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8200 11:20:10.181293 ==
8201 11:20:10.183835 Dram Type= 6, Freq= 0, CH_0, rank 1
8202 11:20:10.187355 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8203 11:20:10.187923 ==
8204 11:20:10.188301 DQS Delay:
8205 11:20:10.190788 DQS0 = 0, DQS1 = 0
8206 11:20:10.191420 DQM Delay:
8207 11:20:10.193583 DQM0 = 133, DQM1 = 127
8208 11:20:10.194051 DQ Delay:
8209 11:20:10.196921 DQ0 =135, DQ1 =139, DQ2 =127, DQ3 =127
8210 11:20:10.201065 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8211 11:20:10.203541 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8212 11:20:10.210216 DQ12 =131, DQ13 =135, DQ14 =135, DQ15 =135
8213 11:20:10.210687
8214 11:20:10.211055
8215 11:20:10.211399 ==
8216 11:20:10.213980 Dram Type= 6, Freq= 0, CH_0, rank 1
8217 11:20:10.216611 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8218 11:20:10.217083 ==
8219 11:20:10.217456
8220 11:20:10.217817
8221 11:20:10.220402 TX Vref Scan disable
8222 11:20:10.220912 == TX Byte 0 ==
8223 11:20:10.227128 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8224 11:20:10.230116 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8225 11:20:10.230649 == TX Byte 1 ==
8226 11:20:10.236718 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8227 11:20:10.239899 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8228 11:20:10.240462 ==
8229 11:20:10.243408 Dram Type= 6, Freq= 0, CH_0, rank 1
8230 11:20:10.246975 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8231 11:20:10.247545 ==
8232 11:20:10.261956
8233 11:20:10.265096 TX Vref early break, caculate TX vref
8234 11:20:10.268676 TX Vref=16, minBit 3, minWin=22, winSum=376
8235 11:20:10.271896 TX Vref=18, minBit 0, minWin=23, winSum=386
8236 11:20:10.275031 TX Vref=20, minBit 1, minWin=23, winSum=393
8237 11:20:10.278988 TX Vref=22, minBit 2, minWin=23, winSum=398
8238 11:20:10.281338 TX Vref=24, minBit 0, minWin=25, winSum=408
8239 11:20:10.288103 TX Vref=26, minBit 0, minWin=25, winSum=414
8240 11:20:10.291664 TX Vref=28, minBit 2, minWin=24, winSum=407
8241 11:20:10.295139 TX Vref=30, minBit 0, minWin=24, winSum=399
8242 11:20:10.298496 TX Vref=32, minBit 0, minWin=24, winSum=396
8243 11:20:10.301794 TX Vref=34, minBit 1, minWin=22, winSum=383
8244 11:20:10.308345 [TxChooseVref] Worse bit 0, Min win 25, Win sum 414, Final Vref 26
8245 11:20:10.308951
8246 11:20:10.311484 Final TX Range 0 Vref 26
8247 11:20:10.312049
8248 11:20:10.312423 ==
8249 11:20:10.314299 Dram Type= 6, Freq= 0, CH_0, rank 1
8250 11:20:10.318040 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8251 11:20:10.318618 ==
8252 11:20:10.318999
8253 11:20:10.319343
8254 11:20:10.321011 TX Vref Scan disable
8255 11:20:10.327506 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8256 11:20:10.328058 == TX Byte 0 ==
8257 11:20:10.331067 u2DelayCellOfst[0]=11 cells (3 PI)
8258 11:20:10.334541 u2DelayCellOfst[1]=14 cells (4 PI)
8259 11:20:10.337904 u2DelayCellOfst[2]=11 cells (3 PI)
8260 11:20:10.341104 u2DelayCellOfst[3]=14 cells (4 PI)
8261 11:20:10.344029 u2DelayCellOfst[4]=7 cells (2 PI)
8262 11:20:10.347950 u2DelayCellOfst[5]=0 cells (0 PI)
8263 11:20:10.351439 u2DelayCellOfst[6]=14 cells (4 PI)
8264 11:20:10.354302 u2DelayCellOfst[7]=14 cells (4 PI)
8265 11:20:10.357612 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8266 11:20:10.360565 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8267 11:20:10.364245 == TX Byte 1 ==
8268 11:20:10.367571 u2DelayCellOfst[8]=0 cells (0 PI)
8269 11:20:10.370282 u2DelayCellOfst[9]=0 cells (0 PI)
8270 11:20:10.370752 u2DelayCellOfst[10]=7 cells (2 PI)
8271 11:20:10.374035 u2DelayCellOfst[11]=3 cells (1 PI)
8272 11:20:10.377053 u2DelayCellOfst[12]=11 cells (3 PI)
8273 11:20:10.380634 u2DelayCellOfst[13]=11 cells (3 PI)
8274 11:20:10.383979 u2DelayCellOfst[14]=14 cells (4 PI)
8275 11:20:10.387383 u2DelayCellOfst[15]=11 cells (3 PI)
8276 11:20:10.393985 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8277 11:20:10.397734 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8278 11:20:10.398306 DramC Write-DBI on
8279 11:20:10.398675 ==
8280 11:20:10.400695 Dram Type= 6, Freq= 0, CH_0, rank 1
8281 11:20:10.407198 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8282 11:20:10.407757 ==
8283 11:20:10.408129
8284 11:20:10.408467
8285 11:20:10.408840 TX Vref Scan disable
8286 11:20:10.411785 == TX Byte 0 ==
8287 11:20:10.414441 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8288 11:20:10.417917 == TX Byte 1 ==
8289 11:20:10.421136 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8290 11:20:10.424405 DramC Write-DBI off
8291 11:20:10.424978
8292 11:20:10.425378 [DATLAT]
8293 11:20:10.425725 Freq=1600, CH0 RK1
8294 11:20:10.426128
8295 11:20:10.427604 DATLAT Default: 0xf
8296 11:20:10.431011 0, 0xFFFF, sum = 0
8297 11:20:10.431553 1, 0xFFFF, sum = 0
8298 11:20:10.434606 2, 0xFFFF, sum = 0
8299 11:20:10.435174 3, 0xFFFF, sum = 0
8300 11:20:10.437962 4, 0xFFFF, sum = 0
8301 11:20:10.438555 5, 0xFFFF, sum = 0
8302 11:20:10.440630 6, 0xFFFF, sum = 0
8303 11:20:10.441222 7, 0xFFFF, sum = 0
8304 11:20:10.444020 8, 0xFFFF, sum = 0
8305 11:20:10.444657 9, 0xFFFF, sum = 0
8306 11:20:10.447145 10, 0xFFFF, sum = 0
8307 11:20:10.447734 11, 0xFFFF, sum = 0
8308 11:20:10.450395 12, 0xFFFF, sum = 0
8309 11:20:10.450886 13, 0xFFFF, sum = 0
8310 11:20:10.453785 14, 0x0, sum = 1
8311 11:20:10.454347 15, 0x0, sum = 2
8312 11:20:10.457435 16, 0x0, sum = 3
8313 11:20:10.457876 17, 0x0, sum = 4
8314 11:20:10.460491 best_step = 15
8315 11:20:10.460958
8316 11:20:10.461295 ==
8317 11:20:10.464311 Dram Type= 6, Freq= 0, CH_0, rank 1
8318 11:20:10.467384 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8319 11:20:10.467819 ==
8320 11:20:10.470403 RX Vref Scan: 0
8321 11:20:10.470831
8322 11:20:10.471169 RX Vref 0 -> 0, step: 1
8323 11:20:10.471486
8324 11:20:10.473494 RX Delay 11 -> 252, step: 4
8325 11:20:10.480641 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8326 11:20:10.483408 iDelay=195, Bit 1, Center 132 (79 ~ 186) 108
8327 11:20:10.486937 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8328 11:20:10.490502 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8329 11:20:10.493407 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8330 11:20:10.500760 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8331 11:20:10.503713 iDelay=195, Bit 6, Center 138 (87 ~ 190) 104
8332 11:20:10.506751 iDelay=195, Bit 7, Center 140 (87 ~ 194) 108
8333 11:20:10.509815 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8334 11:20:10.516734 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8335 11:20:10.520011 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8336 11:20:10.523025 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8337 11:20:10.526838 iDelay=195, Bit 12, Center 130 (75 ~ 186) 112
8338 11:20:10.530133 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8339 11:20:10.537154 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8340 11:20:10.539445 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8341 11:20:10.539928 ==
8342 11:20:10.543113 Dram Type= 6, Freq= 0, CH_0, rank 1
8343 11:20:10.546063 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8344 11:20:10.546533 ==
8345 11:20:10.549414 DQS Delay:
8346 11:20:10.549979 DQS0 = 0, DQS1 = 0
8347 11:20:10.550354 DQM Delay:
8348 11:20:10.552637 DQM0 = 130, DQM1 = 125
8349 11:20:10.553107 DQ Delay:
8350 11:20:10.556299 DQ0 =128, DQ1 =132, DQ2 =124, DQ3 =128
8351 11:20:10.559777 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =140
8352 11:20:10.566009 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8353 11:20:10.569711 DQ12 =130, DQ13 =132, DQ14 =136, DQ15 =132
8354 11:20:10.570181
8355 11:20:10.570550
8356 11:20:10.570890
8357 11:20:10.572419 [DramC_TX_OE_Calibration] TA2
8358 11:20:10.576204 Original DQ_B0 (3 6) =30, OEN = 27
8359 11:20:10.579279 Original DQ_B1 (3 6) =30, OEN = 27
8360 11:20:10.579698 24, 0x0, End_B0=24 End_B1=24
8361 11:20:10.582202 25, 0x0, End_B0=25 End_B1=25
8362 11:20:10.585286 26, 0x0, End_B0=26 End_B1=26
8363 11:20:10.588640 27, 0x0, End_B0=27 End_B1=27
8364 11:20:10.589064 28, 0x0, End_B0=28 End_B1=28
8365 11:20:10.592554 29, 0x0, End_B0=29 End_B1=29
8366 11:20:10.595468 30, 0x0, End_B0=30 End_B1=30
8367 11:20:10.598713 31, 0x5151, End_B0=30 End_B1=30
8368 11:20:10.602657 Byte0 end_step=30 best_step=27
8369 11:20:10.605450 Byte1 end_step=30 best_step=27
8370 11:20:10.608803 Byte0 TX OE(2T, 0.5T) = (3, 3)
8371 11:20:10.609220 Byte1 TX OE(2T, 0.5T) = (3, 3)
8372 11:20:10.609550
8373 11:20:10.609854
8374 11:20:10.618453 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f02, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 394 ps
8375 11:20:10.621844 CH0 RK1: MR19=303, MR18=1F02
8376 11:20:10.628690 CH0_RK1: MR19=0x303, MR18=0x1F02, DQSOSC=394, MR23=63, INC=23, DEC=15
8377 11:20:10.631681 [RxdqsGatingPostProcess] freq 1600
8378 11:20:10.635076 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8379 11:20:10.638364 best DQS0 dly(2T, 0.5T) = (1, 1)
8380 11:20:10.642816 best DQS1 dly(2T, 0.5T) = (1, 1)
8381 11:20:10.644934 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8382 11:20:10.648348 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8383 11:20:10.651667 best DQS0 dly(2T, 0.5T) = (1, 1)
8384 11:20:10.654472 best DQS1 dly(2T, 0.5T) = (1, 1)
8385 11:20:10.658299 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8386 11:20:10.661073 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8387 11:20:10.664990 Pre-setting of DQS Precalculation
8388 11:20:10.667942 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8389 11:20:10.668404 ==
8390 11:20:10.671098 Dram Type= 6, Freq= 0, CH_1, rank 0
8391 11:20:10.674366 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8392 11:20:10.674831 ==
8393 11:20:10.681200 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8394 11:20:10.684198 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8395 11:20:10.691438 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8396 11:20:10.694083 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8397 11:20:10.704748 [CA 0] Center 42 (13~72) winsize 60
8398 11:20:10.707970 [CA 1] Center 42 (13~72) winsize 60
8399 11:20:10.710798 [CA 2] Center 38 (9~67) winsize 59
8400 11:20:10.714218 [CA 3] Center 36 (7~66) winsize 60
8401 11:20:10.717968 [CA 4] Center 37 (8~67) winsize 60
8402 11:20:10.721025 [CA 5] Center 37 (8~67) winsize 60
8403 11:20:10.721481
8404 11:20:10.723998 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8405 11:20:10.724455
8406 11:20:10.727499 [CATrainingPosCal] consider 1 rank data
8407 11:20:10.731085 u2DelayCellTimex100 = 262/100 ps
8408 11:20:10.737266 CA0 delay=42 (13~72),Diff = 6 PI (22 cell)
8409 11:20:10.741327 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8410 11:20:10.744473 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8411 11:20:10.747767 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8412 11:20:10.750493 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8413 11:20:10.754274 CA5 delay=37 (8~67),Diff = 1 PI (3 cell)
8414 11:20:10.754844
8415 11:20:10.757001 CA PerBit enable=1, Macro0, CA PI delay=36
8416 11:20:10.757467
8417 11:20:10.760392 [CBTSetCACLKResult] CA Dly = 36
8418 11:20:10.764127 CS Dly: 9 (0~40)
8419 11:20:10.767141 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8420 11:20:10.770751 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8421 11:20:10.771328 ==
8422 11:20:10.773732 Dram Type= 6, Freq= 0, CH_1, rank 1
8423 11:20:10.780440 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8424 11:20:10.781056 ==
8425 11:20:10.783495 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8426 11:20:10.790464 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8427 11:20:10.793288 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8428 11:20:10.799996 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8429 11:20:10.807763 [CA 0] Center 42 (12~72) winsize 61
8430 11:20:10.811392 [CA 1] Center 42 (13~72) winsize 60
8431 11:20:10.814350 [CA 2] Center 37 (8~67) winsize 60
8432 11:20:10.818134 [CA 3] Center 36 (7~66) winsize 60
8433 11:20:10.821319 [CA 4] Center 37 (8~67) winsize 60
8434 11:20:10.824068 [CA 5] Center 36 (7~66) winsize 60
8435 11:20:10.824555
8436 11:20:10.827677 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8437 11:20:10.828142
8438 11:20:10.831505 [CATrainingPosCal] consider 2 rank data
8439 11:20:10.834776 u2DelayCellTimex100 = 262/100 ps
8440 11:20:10.838042 CA0 delay=42 (13~72),Diff = 6 PI (22 cell)
8441 11:20:10.844272 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8442 11:20:10.848050 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8443 11:20:10.850417 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8444 11:20:10.854252 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8445 11:20:10.857313 CA5 delay=37 (8~66),Diff = 1 PI (3 cell)
8446 11:20:10.857784
8447 11:20:10.860741 CA PerBit enable=1, Macro0, CA PI delay=36
8448 11:20:10.861244
8449 11:20:10.864261 [CBTSetCACLKResult] CA Dly = 36
8450 11:20:10.867393 CS Dly: 10 (0~43)
8451 11:20:10.870578 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8452 11:20:10.874144 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8453 11:20:10.874706
8454 11:20:10.876870 ----->DramcWriteLeveling(PI) begin...
8455 11:20:10.877444 ==
8456 11:20:10.880345 Dram Type= 6, Freq= 0, CH_1, rank 0
8457 11:20:10.886807 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8458 11:20:10.887564 ==
8459 11:20:10.890303 Write leveling (Byte 0): 23 => 23
8460 11:20:10.893174 Write leveling (Byte 1): 27 => 27
8461 11:20:10.893645 DramcWriteLeveling(PI) end<-----
8462 11:20:10.894019
8463 11:20:10.897028 ==
8464 11:20:10.900355 Dram Type= 6, Freq= 0, CH_1, rank 0
8465 11:20:10.903525 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8466 11:20:10.904117 ==
8467 11:20:10.906578 [Gating] SW mode calibration
8468 11:20:10.913047 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8469 11:20:10.916507 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8470 11:20:10.923440 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8471 11:20:10.926344 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8472 11:20:10.929760 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8473 11:20:10.936425 1 4 12 | B1->B0 | 3232 3333 | 1 1 | (1 1) (1 1)
8474 11:20:10.939704 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8475 11:20:10.943181 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8476 11:20:10.949591 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8477 11:20:10.952902 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8478 11:20:10.956245 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8479 11:20:10.962647 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8480 11:20:10.966333 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8481 11:20:10.969210 1 5 12 | B1->B0 | 2525 2323 | 1 0 | (1 0) (0 0)
8482 11:20:10.976026 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8483 11:20:10.979175 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8484 11:20:10.982199 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8485 11:20:10.988747 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8486 11:20:10.992403 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8487 11:20:10.995428 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8488 11:20:11.002366 1 6 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8489 11:20:11.005361 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8490 11:20:11.008759 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8491 11:20:11.015215 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8492 11:20:11.018479 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8493 11:20:11.025038 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8494 11:20:11.028731 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8495 11:20:11.031797 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8496 11:20:11.035174 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8497 11:20:11.041320 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8498 11:20:11.044613 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8499 11:20:11.051451 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8500 11:20:11.054772 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8501 11:20:11.057840 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8502 11:20:11.065036 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8503 11:20:11.067458 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8504 11:20:11.070752 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8505 11:20:11.077815 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8506 11:20:11.081161 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8507 11:20:11.084189 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8508 11:20:11.090438 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8509 11:20:11.094068 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8510 11:20:11.097292 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8511 11:20:11.104182 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8512 11:20:11.107291 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8513 11:20:11.111123 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8514 11:20:11.116988 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8515 11:20:11.117565 Total UI for P1: 0, mck2ui 16
8516 11:20:11.123946 best dqsien dly found for B0: ( 1, 9, 10)
8517 11:20:11.124512 Total UI for P1: 0, mck2ui 16
8518 11:20:11.127400 best dqsien dly found for B1: ( 1, 9, 10)
8519 11:20:11.133414 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8520 11:20:11.137261 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8521 11:20:11.137830
8522 11:20:11.139998 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8523 11:20:11.143213 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8524 11:20:11.146867 [Gating] SW calibration Done
8525 11:20:11.147426 ==
8526 11:20:11.150546 Dram Type= 6, Freq= 0, CH_1, rank 0
8527 11:20:11.153539 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8528 11:20:11.154123 ==
8529 11:20:11.156679 RX Vref Scan: 0
8530 11:20:11.157254
8531 11:20:11.157738 RX Vref 0 -> 0, step: 1
8532 11:20:11.158188
8533 11:20:11.160439 RX Delay 0 -> 252, step: 8
8534 11:20:11.163351 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8535 11:20:11.170096 iDelay=208, Bit 1, Center 135 (88 ~ 183) 96
8536 11:20:11.173204 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8537 11:20:11.176887 iDelay=208, Bit 3, Center 139 (88 ~ 191) 104
8538 11:20:11.179745 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8539 11:20:11.183117 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8540 11:20:11.190380 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8541 11:20:11.193359 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8542 11:20:11.196600 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8543 11:20:11.199610 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8544 11:20:11.202901 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8545 11:20:11.209398 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8546 11:20:11.213027 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8547 11:20:11.215904 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8548 11:20:11.219413 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8549 11:20:11.225904 iDelay=208, Bit 15, Center 139 (88 ~ 191) 104
8550 11:20:11.226470 ==
8551 11:20:11.229934 Dram Type= 6, Freq= 0, CH_1, rank 0
8552 11:20:11.232922 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8553 11:20:11.233494 ==
8554 11:20:11.233869 DQS Delay:
8555 11:20:11.235988 DQS0 = 0, DQS1 = 0
8556 11:20:11.236584 DQM Delay:
8557 11:20:11.239356 DQM0 = 138, DQM1 = 129
8558 11:20:11.239825 DQ Delay:
8559 11:20:11.242441 DQ0 =143, DQ1 =135, DQ2 =127, DQ3 =139
8560 11:20:11.245896 DQ4 =135, DQ5 =151, DQ6 =143, DQ7 =135
8561 11:20:11.249110 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =123
8562 11:20:11.252230 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =139
8563 11:20:11.252840
8564 11:20:11.253213
8565 11:20:11.255646 ==
8566 11:20:11.259171 Dram Type= 6, Freq= 0, CH_1, rank 0
8567 11:20:11.262440 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8568 11:20:11.262914 ==
8569 11:20:11.263285
8570 11:20:11.263629
8571 11:20:11.265393 TX Vref Scan disable
8572 11:20:11.265922 == TX Byte 0 ==
8573 11:20:11.272438 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8574 11:20:11.275199 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8575 11:20:11.275669 == TX Byte 1 ==
8576 11:20:11.281705 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8577 11:20:11.285854 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8578 11:20:11.286414 ==
8579 11:20:11.288594 Dram Type= 6, Freq= 0, CH_1, rank 0
8580 11:20:11.291998 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8581 11:20:11.292607 ==
8582 11:20:11.305525
8583 11:20:11.308760 TX Vref early break, caculate TX vref
8584 11:20:11.312582 TX Vref=16, minBit 0, minWin=21, winSum=368
8585 11:20:11.315596 TX Vref=18, minBit 0, minWin=22, winSum=382
8586 11:20:11.318839 TX Vref=20, minBit 0, minWin=22, winSum=389
8587 11:20:11.322214 TX Vref=22, minBit 0, minWin=23, winSum=399
8588 11:20:11.325430 TX Vref=24, minBit 5, minWin=23, winSum=408
8589 11:20:11.331975 TX Vref=26, minBit 5, minWin=24, winSum=413
8590 11:20:11.335665 TX Vref=28, minBit 0, minWin=24, winSum=415
8591 11:20:11.338812 TX Vref=30, minBit 0, minWin=23, winSum=409
8592 11:20:11.341848 TX Vref=32, minBit 0, minWin=23, winSum=395
8593 11:20:11.345134 TX Vref=34, minBit 0, minWin=23, winSum=389
8594 11:20:11.352042 [TxChooseVref] Worse bit 0, Min win 24, Win sum 415, Final Vref 28
8595 11:20:11.352646
8596 11:20:11.354817 Final TX Range 0 Vref 28
8597 11:20:11.355305
8598 11:20:11.355725 ==
8599 11:20:11.358213 Dram Type= 6, Freq= 0, CH_1, rank 0
8600 11:20:11.361238 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8601 11:20:11.361706 ==
8602 11:20:11.362094
8603 11:20:11.362440
8604 11:20:11.364505 TX Vref Scan disable
8605 11:20:11.371427 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8606 11:20:11.371983 == TX Byte 0 ==
8607 11:20:11.374722 u2DelayCellOfst[0]=22 cells (6 PI)
8608 11:20:11.378031 u2DelayCellOfst[1]=14 cells (4 PI)
8609 11:20:11.381054 u2DelayCellOfst[2]=0 cells (0 PI)
8610 11:20:11.384385 u2DelayCellOfst[3]=7 cells (2 PI)
8611 11:20:11.387919 u2DelayCellOfst[4]=11 cells (3 PI)
8612 11:20:11.391076 u2DelayCellOfst[5]=26 cells (7 PI)
8613 11:20:11.394058 u2DelayCellOfst[6]=22 cells (6 PI)
8614 11:20:11.398037 u2DelayCellOfst[7]=7 cells (2 PI)
8615 11:20:11.400613 Update DQ dly =976 (3 ,6, 16) DQ OEN =(3 ,3)
8616 11:20:11.404033 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8617 11:20:11.407636 == TX Byte 1 ==
8618 11:20:11.410797 u2DelayCellOfst[8]=0 cells (0 PI)
8619 11:20:11.414321 u2DelayCellOfst[9]=3 cells (1 PI)
8620 11:20:11.417538 u2DelayCellOfst[10]=11 cells (3 PI)
8621 11:20:11.418119 u2DelayCellOfst[11]=3 cells (1 PI)
8622 11:20:11.420803 u2DelayCellOfst[12]=14 cells (4 PI)
8623 11:20:11.424400 u2DelayCellOfst[13]=18 cells (5 PI)
8624 11:20:11.427375 u2DelayCellOfst[14]=18 cells (5 PI)
8625 11:20:11.430327 u2DelayCellOfst[15]=18 cells (5 PI)
8626 11:20:11.437552 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8627 11:20:11.440711 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8628 11:20:11.441284 DramC Write-DBI on
8629 11:20:11.443983 ==
8630 11:20:11.444588 Dram Type= 6, Freq= 0, CH_1, rank 0
8631 11:20:11.450363 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8632 11:20:11.450940 ==
8633 11:20:11.451321
8634 11:20:11.451698
8635 11:20:11.453537 TX Vref Scan disable
8636 11:20:11.454048 == TX Byte 0 ==
8637 11:20:11.460568 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8638 11:20:11.461145 == TX Byte 1 ==
8639 11:20:11.463570 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8640 11:20:11.467401 DramC Write-DBI off
8641 11:20:11.467891
8642 11:20:11.468262 [DATLAT]
8643 11:20:11.470513 Freq=1600, CH1 RK0
8644 11:20:11.471086
8645 11:20:11.471456 DATLAT Default: 0xf
8646 11:20:11.473298 0, 0xFFFF, sum = 0
8647 11:20:11.473774 1, 0xFFFF, sum = 0
8648 11:20:11.476475 2, 0xFFFF, sum = 0
8649 11:20:11.476981 3, 0xFFFF, sum = 0
8650 11:20:11.479782 4, 0xFFFF, sum = 0
8651 11:20:11.480299 5, 0xFFFF, sum = 0
8652 11:20:11.483303 6, 0xFFFF, sum = 0
8653 11:20:11.483801 7, 0xFFFF, sum = 0
8654 11:20:11.486429 8, 0xFFFF, sum = 0
8655 11:20:11.490227 9, 0xFFFF, sum = 0
8656 11:20:11.490910 10, 0xFFFF, sum = 0
8657 11:20:11.493138 11, 0xFFFF, sum = 0
8658 11:20:11.493613 12, 0xFFFF, sum = 0
8659 11:20:11.496658 13, 0xFFFF, sum = 0
8660 11:20:11.497099 14, 0x0, sum = 1
8661 11:20:11.500398 15, 0x0, sum = 2
8662 11:20:11.501018 16, 0x0, sum = 3
8663 11:20:11.503039 17, 0x0, sum = 4
8664 11:20:11.503516 best_step = 15
8665 11:20:11.503884
8666 11:20:11.504227 ==
8667 11:20:11.507016 Dram Type= 6, Freq= 0, CH_1, rank 0
8668 11:20:11.509724 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8669 11:20:11.510201 ==
8670 11:20:11.513302 RX Vref Scan: 1
8671 11:20:11.513806
8672 11:20:11.516587 Set Vref Range= 24 -> 127
8673 11:20:11.517155
8674 11:20:11.517531 RX Vref 24 -> 127, step: 1
8675 11:20:11.519840
8676 11:20:11.520416 RX Delay 11 -> 252, step: 4
8677 11:20:11.520862
8678 11:20:11.523071 Set Vref, RX VrefLevel [Byte0]: 24
8679 11:20:11.526409 [Byte1]: 24
8680 11:20:11.529505
8681 11:20:11.529946 Set Vref, RX VrefLevel [Byte0]: 25
8682 11:20:11.533137 [Byte1]: 25
8683 11:20:11.537625
8684 11:20:11.538155 Set Vref, RX VrefLevel [Byte0]: 26
8685 11:20:11.540679 [Byte1]: 26
8686 11:20:11.545166
8687 11:20:11.545691 Set Vref, RX VrefLevel [Byte0]: 27
8688 11:20:11.548592 [Byte1]: 27
8689 11:20:11.552764
8690 11:20:11.553296 Set Vref, RX VrefLevel [Byte0]: 28
8691 11:20:11.555740 [Byte1]: 28
8692 11:20:11.560476
8693 11:20:11.561037 Set Vref, RX VrefLevel [Byte0]: 29
8694 11:20:11.563273 [Byte1]: 29
8695 11:20:11.568137
8696 11:20:11.568727 Set Vref, RX VrefLevel [Byte0]: 30
8697 11:20:11.571669 [Byte1]: 30
8698 11:20:11.575631
8699 11:20:11.576164 Set Vref, RX VrefLevel [Byte0]: 31
8700 11:20:11.578597 [Byte1]: 31
8701 11:20:11.583170
8702 11:20:11.583699 Set Vref, RX VrefLevel [Byte0]: 32
8703 11:20:11.586586 [Byte1]: 32
8704 11:20:11.591143
8705 11:20:11.591667 Set Vref, RX VrefLevel [Byte0]: 33
8706 11:20:11.594190 [Byte1]: 33
8707 11:20:11.598454
8708 11:20:11.598982 Set Vref, RX VrefLevel [Byte0]: 34
8709 11:20:11.601965 [Byte1]: 34
8710 11:20:11.605692
8711 11:20:11.606117 Set Vref, RX VrefLevel [Byte0]: 35
8712 11:20:11.609120 [Byte1]: 35
8713 11:20:11.613748
8714 11:20:11.614286 Set Vref, RX VrefLevel [Byte0]: 36
8715 11:20:11.616921 [Byte1]: 36
8716 11:20:11.621285
8717 11:20:11.621811 Set Vref, RX VrefLevel [Byte0]: 37
8718 11:20:11.624077 [Byte1]: 37
8719 11:20:11.629030
8720 11:20:11.629452 Set Vref, RX VrefLevel [Byte0]: 38
8721 11:20:11.631987 [Byte1]: 38
8722 11:20:11.636659
8723 11:20:11.637192 Set Vref, RX VrefLevel [Byte0]: 39
8724 11:20:11.640062 [Byte1]: 39
8725 11:20:11.643935
8726 11:20:11.644359 Set Vref, RX VrefLevel [Byte0]: 40
8727 11:20:11.647232 [Byte1]: 40
8728 11:20:11.651892
8729 11:20:11.652433 Set Vref, RX VrefLevel [Byte0]: 41
8730 11:20:11.654846 [Byte1]: 41
8731 11:20:11.659405
8732 11:20:11.659933 Set Vref, RX VrefLevel [Byte0]: 42
8733 11:20:11.662343 [Byte1]: 42
8734 11:20:11.666882
8735 11:20:11.667491 Set Vref, RX VrefLevel [Byte0]: 43
8736 11:20:11.669855 [Byte1]: 43
8737 11:20:11.674218
8738 11:20:11.674750 Set Vref, RX VrefLevel [Byte0]: 44
8739 11:20:11.677973 [Byte1]: 44
8740 11:20:11.682186
8741 11:20:11.682713 Set Vref, RX VrefLevel [Byte0]: 45
8742 11:20:11.685045 [Byte1]: 45
8743 11:20:11.689540
8744 11:20:11.690080 Set Vref, RX VrefLevel [Byte0]: 46
8745 11:20:11.692814 [Byte1]: 46
8746 11:20:11.697458
8747 11:20:11.697924 Set Vref, RX VrefLevel [Byte0]: 47
8748 11:20:11.700674 [Byte1]: 47
8749 11:20:11.705193
8750 11:20:11.705772 Set Vref, RX VrefLevel [Byte0]: 48
8751 11:20:11.708416 [Byte1]: 48
8752 11:20:11.712869
8753 11:20:11.713436 Set Vref, RX VrefLevel [Byte0]: 49
8754 11:20:11.715551 [Byte1]: 49
8755 11:20:11.720403
8756 11:20:11.721057 Set Vref, RX VrefLevel [Byte0]: 50
8757 11:20:11.723707 [Byte1]: 50
8758 11:20:11.727736
8759 11:20:11.728199 Set Vref, RX VrefLevel [Byte0]: 51
8760 11:20:11.731009 [Byte1]: 51
8761 11:20:11.735491
8762 11:20:11.736061 Set Vref, RX VrefLevel [Byte0]: 52
8763 11:20:11.738861 [Byte1]: 52
8764 11:20:11.742845
8765 11:20:11.743371 Set Vref, RX VrefLevel [Byte0]: 53
8766 11:20:11.746519 [Byte1]: 53
8767 11:20:11.751034
8768 11:20:11.751606 Set Vref, RX VrefLevel [Byte0]: 54
8769 11:20:11.753818 [Byte1]: 54
8770 11:20:11.758088
8771 11:20:11.758557 Set Vref, RX VrefLevel [Byte0]: 55
8772 11:20:11.761567 [Byte1]: 55
8773 11:20:11.765876
8774 11:20:11.766450 Set Vref, RX VrefLevel [Byte0]: 56
8775 11:20:11.769394 [Byte1]: 56
8776 11:20:11.773639
8777 11:20:11.774206 Set Vref, RX VrefLevel [Byte0]: 57
8778 11:20:11.776899 [Byte1]: 57
8779 11:20:11.781104
8780 11:20:11.781677 Set Vref, RX VrefLevel [Byte0]: 58
8781 11:20:11.784727 [Byte1]: 58
8782 11:20:11.788790
8783 11:20:11.789362 Set Vref, RX VrefLevel [Byte0]: 59
8784 11:20:11.791964 [Byte1]: 59
8785 11:20:11.796483
8786 11:20:11.797095 Set Vref, RX VrefLevel [Byte0]: 60
8787 11:20:11.799824 [Byte1]: 60
8788 11:20:11.804095
8789 11:20:11.804712 Set Vref, RX VrefLevel [Byte0]: 61
8790 11:20:11.807350 [Byte1]: 61
8791 11:20:11.812104
8792 11:20:11.812715 Set Vref, RX VrefLevel [Byte0]: 62
8793 11:20:11.815265 [Byte1]: 62
8794 11:20:11.819466
8795 11:20:11.820036 Set Vref, RX VrefLevel [Byte0]: 63
8796 11:20:11.822696 [Byte1]: 63
8797 11:20:11.826759
8798 11:20:11.827330 Set Vref, RX VrefLevel [Byte0]: 64
8799 11:20:11.829641 [Byte1]: 64
8800 11:20:11.834622
8801 11:20:11.835192 Set Vref, RX VrefLevel [Byte0]: 65
8802 11:20:11.837903 [Byte1]: 65
8803 11:20:11.842309
8804 11:20:11.842869 Set Vref, RX VrefLevel [Byte0]: 66
8805 11:20:11.845178 [Byte1]: 66
8806 11:20:11.849821
8807 11:20:11.850389 Set Vref, RX VrefLevel [Byte0]: 67
8808 11:20:11.852603 [Byte1]: 67
8809 11:20:11.857293
8810 11:20:11.857872 Set Vref, RX VrefLevel [Byte0]: 68
8811 11:20:11.860688 [Byte1]: 68
8812 11:20:11.865271
8813 11:20:11.865837 Set Vref, RX VrefLevel [Byte0]: 69
8814 11:20:11.868214 [Byte1]: 69
8815 11:20:11.872894
8816 11:20:11.873534 Set Vref, RX VrefLevel [Byte0]: 70
8817 11:20:11.875841 [Byte1]: 70
8818 11:20:11.880056
8819 11:20:11.880652 Set Vref, RX VrefLevel [Byte0]: 71
8820 11:20:11.883378 [Byte1]: 71
8821 11:20:11.887613
8822 11:20:11.888180 Set Vref, RX VrefLevel [Byte0]: 72
8823 11:20:11.890933 [Byte1]: 72
8824 11:20:11.895172
8825 11:20:11.895748 Final RX Vref Byte 0 = 54 to rank0
8826 11:20:11.898492 Final RX Vref Byte 1 = 56 to rank0
8827 11:20:11.901669 Final RX Vref Byte 0 = 54 to rank1
8828 11:20:11.905455 Final RX Vref Byte 1 = 56 to rank1==
8829 11:20:11.908575 Dram Type= 6, Freq= 0, CH_1, rank 0
8830 11:20:11.914803 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8831 11:20:11.915386 ==
8832 11:20:11.915771 DQS Delay:
8833 11:20:11.918329 DQS0 = 0, DQS1 = 0
8834 11:20:11.918797 DQM Delay:
8835 11:20:11.921399 DQM0 = 135, DQM1 = 128
8836 11:20:11.921866 DQ Delay:
8837 11:20:11.925398 DQ0 =142, DQ1 =128, DQ2 =124, DQ3 =132
8838 11:20:11.928167 DQ4 =132, DQ5 =148, DQ6 =144, DQ7 =130
8839 11:20:11.931344 DQ8 =116, DQ9 =116, DQ10 =130, DQ11 =118
8840 11:20:11.934962 DQ12 =136, DQ13 =138, DQ14 =138, DQ15 =138
8841 11:20:11.935532
8842 11:20:11.935906
8843 11:20:11.936250
8844 11:20:11.938271 [DramC_TX_OE_Calibration] TA2
8845 11:20:11.941642 Original DQ_B0 (3 6) =30, OEN = 27
8846 11:20:11.944459 Original DQ_B1 (3 6) =30, OEN = 27
8847 11:20:11.948075 24, 0x0, End_B0=24 End_B1=24
8848 11:20:11.951506 25, 0x0, End_B0=25 End_B1=25
8849 11:20:11.952076 26, 0x0, End_B0=26 End_B1=26
8850 11:20:11.954497 27, 0x0, End_B0=27 End_B1=27
8851 11:20:11.957825 28, 0x0, End_B0=28 End_B1=28
8852 11:20:11.961165 29, 0x0, End_B0=29 End_B1=29
8853 11:20:11.961742 30, 0x0, End_B0=30 End_B1=30
8854 11:20:11.964364 31, 0x4141, End_B0=30 End_B1=30
8855 11:20:11.967627 Byte0 end_step=30 best_step=27
8856 11:20:11.971018 Byte1 end_step=30 best_step=27
8857 11:20:11.974546 Byte0 TX OE(2T, 0.5T) = (3, 3)
8858 11:20:11.977221 Byte1 TX OE(2T, 0.5T) = (3, 3)
8859 11:20:11.977693
8860 11:20:11.978067
8861 11:20:11.983902 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a0f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 396 ps
8862 11:20:11.987463 CH1 RK0: MR19=303, MR18=1A0F
8863 11:20:11.993875 CH1_RK0: MR19=0x303, MR18=0x1A0F, DQSOSC=396, MR23=63, INC=23, DEC=15
8864 11:20:11.994353
8865 11:20:11.997561 ----->DramcWriteLeveling(PI) begin...
8866 11:20:11.998039 ==
8867 11:20:12.000717 Dram Type= 6, Freq= 0, CH_1, rank 1
8868 11:20:12.004032 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8869 11:20:12.004653 ==
8870 11:20:12.008047 Write leveling (Byte 0): 25 => 25
8871 11:20:12.010597 Write leveling (Byte 1): 28 => 28
8872 11:20:12.013616 DramcWriteLeveling(PI) end<-----
8873 11:20:12.014084
8874 11:20:12.014449 ==
8875 11:20:12.016847 Dram Type= 6, Freq= 0, CH_1, rank 1
8876 11:20:12.023922 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8877 11:20:12.024512 ==
8878 11:20:12.024955 [Gating] SW mode calibration
8879 11:20:12.033677 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8880 11:20:12.036884 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8881 11:20:12.040206 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8882 11:20:12.046885 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8883 11:20:12.050365 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8884 11:20:12.053363 1 4 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (1 1)
8885 11:20:12.059485 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8886 11:20:12.063088 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8887 11:20:12.069734 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8888 11:20:12.073397 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8889 11:20:12.076428 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8890 11:20:12.079868 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8891 11:20:12.086247 1 5 8 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
8892 11:20:12.089811 1 5 12 | B1->B0 | 2727 3434 | 0 1 | (1 0) (1 0)
8893 11:20:12.092704 1 5 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8894 11:20:12.099787 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8895 11:20:12.102664 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8896 11:20:12.106107 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8897 11:20:12.112980 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8898 11:20:12.116549 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8899 11:20:12.119022 1 6 8 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
8900 11:20:12.126192 1 6 12 | B1->B0 | 4646 2b2a | 0 1 | (0 0) (0 0)
8901 11:20:12.128873 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8902 11:20:12.132354 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8903 11:20:12.139441 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8904 11:20:12.142583 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8905 11:20:12.145447 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8906 11:20:12.153115 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8907 11:20:12.155579 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8908 11:20:12.158970 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8909 11:20:12.165460 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8910 11:20:12.168764 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8911 11:20:12.172692 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8912 11:20:12.178557 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8913 11:20:12.182113 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8914 11:20:12.185389 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8915 11:20:12.191967 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8916 11:20:12.194858 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8917 11:20:12.198228 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8918 11:20:12.204830 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8919 11:20:12.207870 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8920 11:20:12.214821 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8921 11:20:12.218149 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8922 11:20:12.221104 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8923 11:20:12.227627 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8924 11:20:12.230973 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8925 11:20:12.234449 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8926 11:20:12.237358 Total UI for P1: 0, mck2ui 16
8927 11:20:12.240917 best dqsien dly found for B0: ( 1, 9, 10)
8928 11:20:12.244196 Total UI for P1: 0, mck2ui 16
8929 11:20:12.248009 best dqsien dly found for B1: ( 1, 9, 10)
8930 11:20:12.250982 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8931 11:20:12.254364 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8932 11:20:12.254946
8933 11:20:12.258136 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8934 11:20:12.264350 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8935 11:20:12.264983 [Gating] SW calibration Done
8936 11:20:12.268141 ==
8937 11:20:12.268759 Dram Type= 6, Freq= 0, CH_1, rank 1
8938 11:20:12.274365 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8939 11:20:12.275005 ==
8940 11:20:12.275402 RX Vref Scan: 0
8941 11:20:12.275760
8942 11:20:12.277307 RX Vref 0 -> 0, step: 1
8943 11:20:12.277777
8944 11:20:12.280949 RX Delay 0 -> 252, step: 8
8945 11:20:12.284788 iDelay=208, Bit 0, Center 139 (80 ~ 199) 120
8946 11:20:12.287620 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8947 11:20:12.291180 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8948 11:20:12.297345 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8949 11:20:12.300890 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
8950 11:20:12.304472 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8951 11:20:12.307187 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8952 11:20:12.310661 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8953 11:20:12.317116 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8954 11:20:12.320799 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8955 11:20:12.324085 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8956 11:20:12.327307 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8957 11:20:12.330257 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8958 11:20:12.337195 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8959 11:20:12.340437 iDelay=208, Bit 14, Center 131 (72 ~ 191) 120
8960 11:20:12.343932 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8961 11:20:12.344502 ==
8962 11:20:12.347239 Dram Type= 6, Freq= 0, CH_1, rank 1
8963 11:20:12.350485 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8964 11:20:12.354199 ==
8965 11:20:12.354764 DQS Delay:
8966 11:20:12.355139 DQS0 = 0, DQS1 = 0
8967 11:20:12.356974 DQM Delay:
8968 11:20:12.357447 DQM0 = 136, DQM1 = 128
8969 11:20:12.360489 DQ Delay:
8970 11:20:12.363738 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8971 11:20:12.366771 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8972 11:20:12.370245 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
8973 11:20:12.373394 DQ12 =139, DQ13 =139, DQ14 =131, DQ15 =139
8974 11:20:12.373961
8975 11:20:12.374336
8976 11:20:12.374677 ==
8977 11:20:12.376907 Dram Type= 6, Freq= 0, CH_1, rank 1
8978 11:20:12.380323 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8979 11:20:12.380954 ==
8980 11:20:12.381334
8981 11:20:12.383147
8982 11:20:12.383617 TX Vref Scan disable
8983 11:20:12.386748 == TX Byte 0 ==
8984 11:20:12.390675 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8985 11:20:12.393552 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8986 11:20:12.397040 == TX Byte 1 ==
8987 11:20:12.399729 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8988 11:20:12.403688 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8989 11:20:12.404260 ==
8990 11:20:12.406765 Dram Type= 6, Freq= 0, CH_1, rank 1
8991 11:20:12.413488 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8992 11:20:12.413963 ==
8993 11:20:12.424958
8994 11:20:12.428049 TX Vref early break, caculate TX vref
8995 11:20:12.431692 TX Vref=16, minBit 1, minWin=23, winSum=387
8996 11:20:12.434754 TX Vref=18, minBit 15, minWin=23, winSum=397
8997 11:20:12.438401 TX Vref=20, minBit 0, minWin=24, winSum=404
8998 11:20:12.441611 TX Vref=22, minBit 0, minWin=25, winSum=413
8999 11:20:12.444690 TX Vref=24, minBit 9, minWin=25, winSum=420
9000 11:20:12.451561 TX Vref=26, minBit 0, minWin=25, winSum=421
9001 11:20:12.455003 TX Vref=28, minBit 0, minWin=26, winSum=424
9002 11:20:12.457595 TX Vref=30, minBit 0, minWin=25, winSum=419
9003 11:20:12.461242 TX Vref=32, minBit 0, minWin=24, winSum=408
9004 11:20:12.464426 TX Vref=34, minBit 0, minWin=23, winSum=399
9005 11:20:12.471277 [TxChooseVref] Worse bit 0, Min win 26, Win sum 424, Final Vref 28
9006 11:20:12.471844
9007 11:20:12.474126 Final TX Range 0 Vref 28
9008 11:20:12.474596
9009 11:20:12.474963 ==
9010 11:20:12.477796 Dram Type= 6, Freq= 0, CH_1, rank 1
9011 11:20:12.480701 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9012 11:20:12.481303 ==
9013 11:20:12.481679
9014 11:20:12.482022
9015 11:20:12.484080 TX Vref Scan disable
9016 11:20:12.490715 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
9017 11:20:12.491281 == TX Byte 0 ==
9018 11:20:12.493868 u2DelayCellOfst[0]=18 cells (5 PI)
9019 11:20:12.497177 u2DelayCellOfst[1]=14 cells (4 PI)
9020 11:20:12.500629 u2DelayCellOfst[2]=0 cells (0 PI)
9021 11:20:12.503980 u2DelayCellOfst[3]=7 cells (2 PI)
9022 11:20:12.507240 u2DelayCellOfst[4]=11 cells (3 PI)
9023 11:20:12.510646 u2DelayCellOfst[5]=22 cells (6 PI)
9024 11:20:12.513510 u2DelayCellOfst[6]=22 cells (6 PI)
9025 11:20:12.516898 u2DelayCellOfst[7]=7 cells (2 PI)
9026 11:20:12.520733 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
9027 11:20:12.523783 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
9028 11:20:12.527310 == TX Byte 1 ==
9029 11:20:12.530713 u2DelayCellOfst[8]=0 cells (0 PI)
9030 11:20:12.533677 u2DelayCellOfst[9]=7 cells (2 PI)
9031 11:20:12.536961 u2DelayCellOfst[10]=14 cells (4 PI)
9032 11:20:12.540392 u2DelayCellOfst[11]=7 cells (2 PI)
9033 11:20:12.543320 u2DelayCellOfst[12]=18 cells (5 PI)
9034 11:20:12.543878 u2DelayCellOfst[13]=18 cells (5 PI)
9035 11:20:12.546665 u2DelayCellOfst[14]=22 cells (6 PI)
9036 11:20:12.550143 u2DelayCellOfst[15]=18 cells (5 PI)
9037 11:20:12.556751 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
9038 11:20:12.559856 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
9039 11:20:12.563258 DramC Write-DBI on
9040 11:20:12.563743 ==
9041 11:20:12.566537 Dram Type= 6, Freq= 0, CH_1, rank 1
9042 11:20:12.569779 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9043 11:20:12.570353 ==
9044 11:20:12.570728
9045 11:20:12.571069
9046 11:20:12.572635 TX Vref Scan disable
9047 11:20:12.573102 == TX Byte 0 ==
9048 11:20:12.579801 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9049 11:20:12.580371 == TX Byte 1 ==
9050 11:20:12.582751 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9051 11:20:12.586408 DramC Write-DBI off
9052 11:20:12.586888
9053 11:20:12.587263 [DATLAT]
9054 11:20:12.589442 Freq=1600, CH1 RK1
9055 11:20:12.589918
9056 11:20:12.590289 DATLAT Default: 0xf
9057 11:20:12.592613 0, 0xFFFF, sum = 0
9058 11:20:12.595721 1, 0xFFFF, sum = 0
9059 11:20:12.596235 2, 0xFFFF, sum = 0
9060 11:20:12.599278 3, 0xFFFF, sum = 0
9061 11:20:12.599750 4, 0xFFFF, sum = 0
9062 11:20:12.602645 5, 0xFFFF, sum = 0
9063 11:20:12.603230 6, 0xFFFF, sum = 0
9064 11:20:12.605713 7, 0xFFFF, sum = 0
9065 11:20:12.606295 8, 0xFFFF, sum = 0
9066 11:20:12.608876 9, 0xFFFF, sum = 0
9067 11:20:12.609354 10, 0xFFFF, sum = 0
9068 11:20:12.612122 11, 0xFFFF, sum = 0
9069 11:20:12.612621 12, 0xFFFF, sum = 0
9070 11:20:12.615434 13, 0xFFFF, sum = 0
9071 11:20:12.615915 14, 0x0, sum = 1
9072 11:20:12.618543 15, 0x0, sum = 2
9073 11:20:12.619019 16, 0x0, sum = 3
9074 11:20:12.621836 17, 0x0, sum = 4
9075 11:20:12.622316 best_step = 15
9076 11:20:12.622688
9077 11:20:12.623032 ==
9078 11:20:12.625555 Dram Type= 6, Freq= 0, CH_1, rank 1
9079 11:20:12.632157 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9080 11:20:12.632773 ==
9081 11:20:12.633153 RX Vref Scan: 0
9082 11:20:12.633500
9083 11:20:12.635254 RX Vref 0 -> 0, step: 1
9084 11:20:12.635722
9085 11:20:12.638817 RX Delay 11 -> 252, step: 4
9086 11:20:12.642120 iDelay=203, Bit 0, Center 138 (87 ~ 190) 104
9087 11:20:12.645404 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9088 11:20:12.652306 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9089 11:20:12.655324 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9090 11:20:12.658706 iDelay=203, Bit 4, Center 134 (79 ~ 190) 112
9091 11:20:12.661761 iDelay=203, Bit 5, Center 146 (95 ~ 198) 104
9092 11:20:12.665199 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9093 11:20:12.671841 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9094 11:20:12.674976 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9095 11:20:12.678017 iDelay=203, Bit 9, Center 114 (59 ~ 170) 112
9096 11:20:12.681430 iDelay=203, Bit 10, Center 128 (75 ~ 182) 108
9097 11:20:12.684606 iDelay=203, Bit 11, Center 116 (63 ~ 170) 108
9098 11:20:12.691442 iDelay=203, Bit 12, Center 134 (79 ~ 190) 112
9099 11:20:12.695014 iDelay=203, Bit 13, Center 134 (79 ~ 190) 112
9100 11:20:12.697805 iDelay=203, Bit 14, Center 134 (79 ~ 190) 112
9101 11:20:12.701700 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9102 11:20:12.702266 ==
9103 11:20:12.704492 Dram Type= 6, Freq= 0, CH_1, rank 1
9104 11:20:12.711309 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9105 11:20:12.711866 ==
9106 11:20:12.712242 DQS Delay:
9107 11:20:12.714189 DQS0 = 0, DQS1 = 0
9108 11:20:12.714656 DQM Delay:
9109 11:20:12.718035 DQM0 = 134, DQM1 = 126
9110 11:20:12.718504 DQ Delay:
9111 11:20:12.721524 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9112 11:20:12.724417 DQ4 =134, DQ5 =146, DQ6 =146, DQ7 =130
9113 11:20:12.727690 DQ8 =112, DQ9 =114, DQ10 =128, DQ11 =116
9114 11:20:12.730644 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =138
9115 11:20:12.731115
9116 11:20:12.731484
9117 11:20:12.731826
9118 11:20:12.734406 [DramC_TX_OE_Calibration] TA2
9119 11:20:12.737979 Original DQ_B0 (3 6) =30, OEN = 27
9120 11:20:12.740838 Original DQ_B1 (3 6) =30, OEN = 27
9121 11:20:12.744424 24, 0x0, End_B0=24 End_B1=24
9122 11:20:12.747084 25, 0x0, End_B0=25 End_B1=25
9123 11:20:12.747562 26, 0x0, End_B0=26 End_B1=26
9124 11:20:12.750893 27, 0x0, End_B0=27 End_B1=27
9125 11:20:12.753950 28, 0x0, End_B0=28 End_B1=28
9126 11:20:12.757355 29, 0x0, End_B0=29 End_B1=29
9127 11:20:12.757934 30, 0x0, End_B0=30 End_B1=30
9128 11:20:12.760223 31, 0x4141, End_B0=30 End_B1=30
9129 11:20:12.763901 Byte0 end_step=30 best_step=27
9130 11:20:12.767444 Byte1 end_step=30 best_step=27
9131 11:20:12.770810 Byte0 TX OE(2T, 0.5T) = (3, 3)
9132 11:20:12.773682 Byte1 TX OE(2T, 0.5T) = (3, 3)
9133 11:20:12.774152
9134 11:20:12.774521
9135 11:20:12.780991 [DQSOSCAuto] RK1, (LSB)MR18= 0xd09, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
9136 11:20:12.783563 CH1 RK1: MR19=303, MR18=D09
9137 11:20:12.790397 CH1_RK1: MR19=0x303, MR18=0xD09, DQSOSC=403, MR23=63, INC=22, DEC=15
9138 11:20:12.793734 [RxdqsGatingPostProcess] freq 1600
9139 11:20:12.797478 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9140 11:20:12.800068 best DQS0 dly(2T, 0.5T) = (1, 1)
9141 11:20:12.803400 best DQS1 dly(2T, 0.5T) = (1, 1)
9142 11:20:12.806824 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9143 11:20:12.810258 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9144 11:20:12.813604 best DQS0 dly(2T, 0.5T) = (1, 1)
9145 11:20:12.817063 best DQS1 dly(2T, 0.5T) = (1, 1)
9146 11:20:12.820060 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9147 11:20:12.823510 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9148 11:20:12.826990 Pre-setting of DQS Precalculation
9149 11:20:12.829948 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9150 11:20:12.839932 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9151 11:20:12.846528 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9152 11:20:12.847082
9153 11:20:12.847448
9154 11:20:12.849952 [Calibration Summary] 3200 Mbps
9155 11:20:12.850520 CH 0, Rank 0
9156 11:20:12.853297 SW Impedance : PASS
9157 11:20:12.853764 DUTY Scan : NO K
9158 11:20:12.856458 ZQ Calibration : PASS
9159 11:20:12.859860 Jitter Meter : NO K
9160 11:20:12.860486 CBT Training : PASS
9161 11:20:12.863117 Write leveling : PASS
9162 11:20:12.866485 RX DQS gating : PASS
9163 11:20:12.867058 RX DQ/DQS(RDDQC) : PASS
9164 11:20:12.869567 TX DQ/DQS : PASS
9165 11:20:12.870048 RX DATLAT : PASS
9166 11:20:12.872716 RX DQ/DQS(Engine): PASS
9167 11:20:12.876023 TX OE : PASS
9168 11:20:12.876489 All Pass.
9169 11:20:12.876883
9170 11:20:12.879836 CH 0, Rank 1
9171 11:20:12.880324 SW Impedance : PASS
9172 11:20:12.882881 DUTY Scan : NO K
9173 11:20:12.883344 ZQ Calibration : PASS
9174 11:20:12.886606 Jitter Meter : NO K
9175 11:20:12.889566 CBT Training : PASS
9176 11:20:12.890029 Write leveling : PASS
9177 11:20:12.892707 RX DQS gating : PASS
9178 11:20:12.896162 RX DQ/DQS(RDDQC) : PASS
9179 11:20:12.896670 TX DQ/DQS : PASS
9180 11:20:12.899693 RX DATLAT : PASS
9181 11:20:12.902976 RX DQ/DQS(Engine): PASS
9182 11:20:12.903553 TX OE : PASS
9183 11:20:12.906221 All Pass.
9184 11:20:12.906801
9185 11:20:12.907175 CH 1, Rank 0
9186 11:20:12.909032 SW Impedance : PASS
9187 11:20:12.909501 DUTY Scan : NO K
9188 11:20:12.912746 ZQ Calibration : PASS
9189 11:20:12.916009 Jitter Meter : NO K
9190 11:20:12.916649 CBT Training : PASS
9191 11:20:12.919108 Write leveling : PASS
9192 11:20:12.922397 RX DQS gating : PASS
9193 11:20:12.922992 RX DQ/DQS(RDDQC) : PASS
9194 11:20:12.926063 TX DQ/DQS : PASS
9195 11:20:12.929069 RX DATLAT : PASS
9196 11:20:12.929557 RX DQ/DQS(Engine): PASS
9197 11:20:12.932907 TX OE : PASS
9198 11:20:12.933500 All Pass.
9199 11:20:12.934012
9200 11:20:12.935615 CH 1, Rank 1
9201 11:20:12.936164 SW Impedance : PASS
9202 11:20:12.939323 DUTY Scan : NO K
9203 11:20:12.942715 ZQ Calibration : PASS
9204 11:20:12.943313 Jitter Meter : NO K
9205 11:20:12.945551 CBT Training : PASS
9206 11:20:12.946038 Write leveling : PASS
9207 11:20:12.948730 RX DQS gating : PASS
9208 11:20:12.952299 RX DQ/DQS(RDDQC) : PASS
9209 11:20:12.952928 TX DQ/DQS : PASS
9210 11:20:12.955866 RX DATLAT : PASS
9211 11:20:12.959353 RX DQ/DQS(Engine): PASS
9212 11:20:12.959946 TX OE : PASS
9213 11:20:12.962321 All Pass.
9214 11:20:12.962915
9215 11:20:12.963410 DramC Write-DBI on
9216 11:20:12.965310 PER_BANK_REFRESH: Hybrid Mode
9217 11:20:12.968737 TX_TRACKING: ON
9218 11:20:12.975485 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9219 11:20:12.985033 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9220 11:20:12.991652 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9221 11:20:12.995150 [FAST_K] Save calibration result to emmc
9222 11:20:12.998044 sync common calibartion params.
9223 11:20:12.998534 sync cbt_mode0:1, 1:1
9224 11:20:13.001691 dram_init: ddr_geometry: 2
9225 11:20:13.004640 dram_init: ddr_geometry: 2
9226 11:20:13.008320 dram_init: ddr_geometry: 2
9227 11:20:13.009049 0:dram_rank_size:100000000
9228 11:20:13.011457 1:dram_rank_size:100000000
9229 11:20:13.018057 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9230 11:20:13.018644 DFS_SHUFFLE_HW_MODE: ON
9231 11:20:13.025034 dramc_set_vcore_voltage set vcore to 725000
9232 11:20:13.025612 Read voltage for 1600, 0
9233 11:20:13.028194 Vio18 = 0
9234 11:20:13.028717 Vcore = 725000
9235 11:20:13.029200 Vdram = 0
9236 11:20:13.031524 Vddq = 0
9237 11:20:13.032119 Vmddr = 0
9238 11:20:13.034892 switch to 3200 Mbps bootup
9239 11:20:13.035382 [DramcRunTimeConfig]
9240 11:20:13.035863 PHYPLL
9241 11:20:13.038125 DPM_CONTROL_AFTERK: ON
9242 11:20:13.041044 PER_BANK_REFRESH: ON
9243 11:20:13.041525 REFRESH_OVERHEAD_REDUCTION: ON
9244 11:20:13.045372 CMD_PICG_NEW_MODE: OFF
9245 11:20:13.047837 XRTWTW_NEW_MODE: ON
9246 11:20:13.048345 XRTRTR_NEW_MODE: ON
9247 11:20:13.051273 TX_TRACKING: ON
9248 11:20:13.051760 RDSEL_TRACKING: OFF
9249 11:20:13.054802 DQS Precalculation for DVFS: ON
9250 11:20:13.055291 RX_TRACKING: OFF
9251 11:20:13.057796 HW_GATING DBG: ON
9252 11:20:13.058388 ZQCS_ENABLE_LP4: ON
9253 11:20:13.061129 RX_PICG_NEW_MODE: ON
9254 11:20:13.064704 TX_PICG_NEW_MODE: ON
9255 11:20:13.065294 ENABLE_RX_DCM_DPHY: ON
9256 11:20:13.067785 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9257 11:20:13.071070 DUMMY_READ_FOR_TRACKING: OFF
9258 11:20:13.074263 !!! SPM_CONTROL_AFTERK: OFF
9259 11:20:13.077728 !!! SPM could not control APHY
9260 11:20:13.078321 IMPEDANCE_TRACKING: ON
9261 11:20:13.081016 TEMP_SENSOR: ON
9262 11:20:13.081502 HW_SAVE_FOR_SR: OFF
9263 11:20:13.084171 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9264 11:20:13.087459 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9265 11:20:13.090826 Read ODT Tracking: ON
9266 11:20:13.091421 Refresh Rate DeBounce: ON
9267 11:20:13.093888 DFS_NO_QUEUE_FLUSH: ON
9268 11:20:13.097441 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9269 11:20:13.100822 ENABLE_DFS_RUNTIME_MRW: OFF
9270 11:20:13.101309 DDR_RESERVE_NEW_MODE: ON
9271 11:20:13.103997 MR_CBT_SWITCH_FREQ: ON
9272 11:20:13.107746 =========================
9273 11:20:13.125639 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9274 11:20:13.128869 dram_init: ddr_geometry: 2
9275 11:20:13.147317 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9276 11:20:13.150593 dram_init: dram init end (result: 0)
9277 11:20:13.157174 DRAM-K: Full calibration passed in 24661 msecs
9278 11:20:13.160865 MRC: failed to locate region type 0.
9279 11:20:13.161465 DRAM rank0 size:0x100000000,
9280 11:20:13.163745 DRAM rank1 size=0x100000000
9281 11:20:13.173651 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9282 11:20:13.179830 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9283 11:20:13.186769 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9284 11:20:13.196684 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9285 11:20:13.197265 DRAM rank0 size:0x100000000,
9286 11:20:13.199882 DRAM rank1 size=0x100000000
9287 11:20:13.200321 CBMEM:
9288 11:20:13.203085 IMD: root @ 0xfffff000 254 entries.
9289 11:20:13.206436 IMD: root @ 0xffffec00 62 entries.
9290 11:20:13.209831 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9291 11:20:13.216183 WARNING: RO_VPD is uninitialized or empty.
9292 11:20:13.219626 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9293 11:20:13.226976 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9294 11:20:13.239929 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9295 11:20:13.251476 BS: romstage times (exec / console): total (unknown) / 24147 ms
9296 11:20:13.252037
9297 11:20:13.252405
9298 11:20:13.261202 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9299 11:20:13.264751 ARM64: Exception handlers installed.
9300 11:20:13.268479 ARM64: Testing exception
9301 11:20:13.271083 ARM64: Done test exception
9302 11:20:13.271662 Enumerating buses...
9303 11:20:13.274395 Show all devs... Before device enumeration.
9304 11:20:13.277398 Root Device: enabled 1
9305 11:20:13.281059 CPU_CLUSTER: 0: enabled 1
9306 11:20:13.281529 CPU: 00: enabled 1
9307 11:20:13.284604 Compare with tree...
9308 11:20:13.285095 Root Device: enabled 1
9309 11:20:13.287634 CPU_CLUSTER: 0: enabled 1
9310 11:20:13.291311 CPU: 00: enabled 1
9311 11:20:13.291896 Root Device scanning...
9312 11:20:13.293995 scan_static_bus for Root Device
9313 11:20:13.297820 CPU_CLUSTER: 0 enabled
9314 11:20:13.300952 scan_static_bus for Root Device done
9315 11:20:13.304445 scan_bus: bus Root Device finished in 8 msecs
9316 11:20:13.304959 done
9317 11:20:13.311146 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9318 11:20:13.313856 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9319 11:20:13.320908 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9320 11:20:13.324280 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9321 11:20:13.327291 Allocating resources...
9322 11:20:13.330487 Reading resources...
9323 11:20:13.333962 Root Device read_resources bus 0 link: 0
9324 11:20:13.337517 DRAM rank0 size:0x100000000,
9325 11:20:13.338085 DRAM rank1 size=0x100000000
9326 11:20:13.343561 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9327 11:20:13.344123 CPU: 00 missing read_resources
9328 11:20:13.350431 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9329 11:20:13.353712 Root Device read_resources bus 0 link: 0 done
9330 11:20:13.356879 Done reading resources.
9331 11:20:13.359930 Show resources in subtree (Root Device)...After reading.
9332 11:20:13.363566 Root Device child on link 0 CPU_CLUSTER: 0
9333 11:20:13.366680 CPU_CLUSTER: 0 child on link 0 CPU: 00
9334 11:20:13.376685 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9335 11:20:13.377256 CPU: 00
9336 11:20:13.383567 Root Device assign_resources, bus 0 link: 0
9337 11:20:13.386781 CPU_CLUSTER: 0 missing set_resources
9338 11:20:13.389823 Root Device assign_resources, bus 0 link: 0 done
9339 11:20:13.390292 Done setting resources.
9340 11:20:13.396326 Show resources in subtree (Root Device)...After assigning values.
9341 11:20:13.399802 Root Device child on link 0 CPU_CLUSTER: 0
9342 11:20:13.406626 CPU_CLUSTER: 0 child on link 0 CPU: 00
9343 11:20:13.412713 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9344 11:20:13.416809 CPU: 00
9345 11:20:13.417368 Done allocating resources.
9346 11:20:13.423119 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9347 11:20:13.423688 Enabling resources...
9348 11:20:13.426153 done.
9349 11:20:13.429546 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9350 11:20:13.432678 Initializing devices...
9351 11:20:13.433139 Root Device init
9352 11:20:13.435660 init hardware done!
9353 11:20:13.436126 0x00000018: ctrlr->caps
9354 11:20:13.439503 52.000 MHz: ctrlr->f_max
9355 11:20:13.442638 0.400 MHz: ctrlr->f_min
9356 11:20:13.443212 0x40ff8080: ctrlr->voltages
9357 11:20:13.446377 sclk: 390625
9358 11:20:13.446982 Bus Width = 1
9359 11:20:13.449498 sclk: 390625
9360 11:20:13.449953 Bus Width = 1
9361 11:20:13.452732 Early init status = 3
9362 11:20:13.455837 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9363 11:20:13.459429 in-header: 03 fc 00 00 01 00 00 00
9364 11:20:13.462966 in-data: 00
9365 11:20:13.465927 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9366 11:20:13.471965 in-header: 03 fd 00 00 00 00 00 00
9367 11:20:13.475159 in-data:
9368 11:20:13.478746 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9369 11:20:13.481634 in-header: 03 fc 00 00 01 00 00 00
9370 11:20:13.484824 in-data: 00
9371 11:20:13.488312 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9372 11:20:13.492825 in-header: 03 fd 00 00 00 00 00 00
9373 11:20:13.496322 in-data:
9374 11:20:13.499356 [SSUSB] Setting up USB HOST controller...
9375 11:20:13.503110 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9376 11:20:13.506050 [SSUSB] phy power-on done.
9377 11:20:13.509207 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9378 11:20:13.515921 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9379 11:20:13.519211 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9380 11:20:13.525808 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9381 11:20:13.532443 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9382 11:20:13.539050 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9383 11:20:13.545879 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9384 11:20:13.552118 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9385 11:20:13.555887 SPM: binary array size = 0x9dc
9386 11:20:13.558950 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9387 11:20:13.565756 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9388 11:20:13.572591 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9389 11:20:13.578676 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9390 11:20:13.582167 configure_display: Starting display init
9391 11:20:13.616071 anx7625_power_on_init: Init interface.
9392 11:20:13.619215 anx7625_disable_pd_protocol: Disabled PD feature.
9393 11:20:13.622645 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9394 11:20:13.650852 anx7625_start_dp_work: Secure OCM version=00
9395 11:20:13.654466 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9396 11:20:13.668870 sp_tx_get_edid_block: EDID Block = 1
9397 11:20:13.771079 Extracted contents:
9398 11:20:13.774787 header: 00 ff ff ff ff ff ff 00
9399 11:20:13.778178 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9400 11:20:13.780944 version: 01 04
9401 11:20:13.784266 basic params: 95 1f 11 78 0a
9402 11:20:13.787820 chroma info: 76 90 94 55 54 90 27 21 50 54
9403 11:20:13.791057 established: 00 00 00
9404 11:20:13.797491 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9405 11:20:13.804313 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9406 11:20:13.807751 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9407 11:20:13.813885 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9408 11:20:13.820404 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9409 11:20:13.824107 extensions: 00
9410 11:20:13.824657 checksum: fb
9411 11:20:13.825042
9412 11:20:13.830398 Manufacturer: IVO Model 57d Serial Number 0
9413 11:20:13.830872 Made week 0 of 2020
9414 11:20:13.833429 EDID version: 1.4
9415 11:20:13.833857 Digital display
9416 11:20:13.837194 6 bits per primary color channel
9417 11:20:13.840806 DisplayPort interface
9418 11:20:13.841326 Maximum image size: 31 cm x 17 cm
9419 11:20:13.843929 Gamma: 220%
9420 11:20:13.844487 Check DPMS levels
9421 11:20:13.850223 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9422 11:20:13.853799 First detailed timing is preferred timing
9423 11:20:13.856971 Established timings supported:
9424 11:20:13.857444 Standard timings supported:
9425 11:20:13.859943 Detailed timings
9426 11:20:13.863447 Hex of detail: 383680a07038204018303c0035ae10000019
9427 11:20:13.869932 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9428 11:20:13.872915 0780 0798 07c8 0820 hborder 0
9429 11:20:13.876362 0438 043b 0447 0458 vborder 0
9430 11:20:13.879898 -hsync -vsync
9431 11:20:13.880324 Did detailed timing
9432 11:20:13.886254 Hex of detail: 000000000000000000000000000000000000
9433 11:20:13.889504 Manufacturer-specified data, tag 0
9434 11:20:13.892949 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9435 11:20:13.895875 ASCII string: InfoVision
9436 11:20:13.899182 Hex of detail: 000000fe00523134304e574635205248200a
9437 11:20:13.902562 ASCII string: R140NWF5 RH
9438 11:20:13.902996 Checksum
9439 11:20:13.905921 Checksum: 0xfb (valid)
9440 11:20:13.909378 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9441 11:20:13.912688 DSI data_rate: 832800000 bps
9442 11:20:13.919100 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9443 11:20:13.921909 anx7625_parse_edid: pixelclock(138800).
9444 11:20:13.925834 hactive(1920), hsync(48), hfp(24), hbp(88)
9445 11:20:13.929713 vactive(1080), vsync(12), vfp(3), vbp(17)
9446 11:20:13.932072 anx7625_dsi_config: config dsi.
9447 11:20:13.939157 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9448 11:20:13.953611 anx7625_dsi_config: success to config DSI
9449 11:20:13.956709 anx7625_dp_start: MIPI phy setup OK.
9450 11:20:13.960111 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9451 11:20:13.963029 mtk_ddp_mode_set invalid vrefresh 60
9452 11:20:13.966282 main_disp_path_setup
9453 11:20:13.966741 ovl_layer_smi_id_en
9454 11:20:13.969736 ovl_layer_smi_id_en
9455 11:20:13.970198 ccorr_config
9456 11:20:13.970563 aal_config
9457 11:20:13.973133 gamma_config
9458 11:20:13.973552 postmask_config
9459 11:20:13.976869 dither_config
9460 11:20:13.979821 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9461 11:20:13.986224 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9462 11:20:13.989871 Root Device init finished in 553 msecs
9463 11:20:13.992835 CPU_CLUSTER: 0 init
9464 11:20:14.000338 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9465 11:20:14.002912 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9466 11:20:14.006526 APU_MBOX 0x190000b0 = 0x10001
9467 11:20:14.009795 APU_MBOX 0x190001b0 = 0x10001
9468 11:20:14.013311 APU_MBOX 0x190005b0 = 0x10001
9469 11:20:14.015774 APU_MBOX 0x190006b0 = 0x10001
9470 11:20:14.019705 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9471 11:20:14.032761 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9472 11:20:14.044838 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9473 11:20:14.051404 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9474 11:20:14.062757 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9475 11:20:14.072017 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9476 11:20:14.075174 CPU_CLUSTER: 0 init finished in 81 msecs
9477 11:20:14.078636 Devices initialized
9478 11:20:14.082095 Show all devs... After init.
9479 11:20:14.082672 Root Device: enabled 1
9480 11:20:14.085189 CPU_CLUSTER: 0: enabled 1
9481 11:20:14.088471 CPU: 00: enabled 1
9482 11:20:14.092326 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9483 11:20:14.095351 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9484 11:20:14.098766 ELOG: NV offset 0x57f000 size 0x1000
9485 11:20:14.105094 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9486 11:20:14.111982 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9487 11:20:14.115204 ELOG: Event(17) added with size 13 at 2023-06-05 11:20:14 UTC
9488 11:20:14.121526 out: cmd=0x121: 03 db 21 01 00 00 00 00
9489 11:20:14.124847 in-header: 03 98 00 00 2c 00 00 00
9490 11:20:14.138859 in-data: c7 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9491 11:20:14.144873 ELOG: Event(A1) added with size 10 at 2023-06-05 11:20:14 UTC
9492 11:20:14.151689 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9493 11:20:14.157765 ELOG: Event(A0) added with size 9 at 2023-06-05 11:20:14 UTC
9494 11:20:14.161408 elog_add_boot_reason: Logged dev mode boot
9495 11:20:14.164727 BS: BS_POST_DEVICE entry times (exec / console): 4 / 64 ms
9496 11:20:14.168114 Finalize devices...
9497 11:20:14.168725 Devices finalized
9498 11:20:14.174233 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9499 11:20:14.177331 Writing coreboot table at 0xffe64000
9500 11:20:14.181163 0. 000000000010a000-0000000000113fff: RAMSTAGE
9501 11:20:14.184388 1. 0000000040000000-00000000400fffff: RAM
9502 11:20:14.190851 2. 0000000040100000-000000004032afff: RAMSTAGE
9503 11:20:14.194000 3. 000000004032b000-00000000545fffff: RAM
9504 11:20:14.197267 4. 0000000054600000-000000005465ffff: BL31
9505 11:20:14.200933 5. 0000000054660000-00000000ffe63fff: RAM
9506 11:20:14.207498 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9507 11:20:14.210473 7. 0000000100000000-000000023fffffff: RAM
9508 11:20:14.213654 Passing 5 GPIOs to payload:
9509 11:20:14.217188 NAME | PORT | POLARITY | VALUE
9510 11:20:14.220471 EC in RW | 0x000000aa | low | undefined
9511 11:20:14.227595 EC interrupt | 0x00000005 | low | undefined
9512 11:20:14.230451 TPM interrupt | 0x000000ab | high | undefined
9513 11:20:14.237192 SD card detect | 0x00000011 | high | undefined
9514 11:20:14.240374 speaker enable | 0x00000093 | high | undefined
9515 11:20:14.243578 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9516 11:20:14.246765 in-header: 03 f9 00 00 02 00 00 00
9517 11:20:14.249975 in-data: 02 00
9518 11:20:14.250452 ADC[4]: Raw value=903031 ID=7
9519 11:20:14.253320 ADC[3]: Raw value=214021 ID=1
9520 11:20:14.257144 RAM Code: 0x71
9521 11:20:14.257725 ADC[6]: Raw value=75036 ID=0
9522 11:20:14.259882 ADC[5]: Raw value=213282 ID=1
9523 11:20:14.263899 SKU Code: 0x1
9524 11:20:14.266922 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a129
9525 11:20:14.270289 coreboot table: 964 bytes.
9526 11:20:14.273487 IMD ROOT 0. 0xfffff000 0x00001000
9527 11:20:14.276800 IMD SMALL 1. 0xffffe000 0x00001000
9528 11:20:14.279696 RO MCACHE 2. 0xffffc000 0x00001104
9529 11:20:14.283292 CONSOLE 3. 0xfff7c000 0x00080000
9530 11:20:14.286179 FMAP 4. 0xfff7b000 0x00000452
9531 11:20:14.289589 TIME STAMP 5. 0xfff7a000 0x00000910
9532 11:20:14.293171 VBOOT WORK 6. 0xfff66000 0x00014000
9533 11:20:14.296661 RAMOOPS 7. 0xffe66000 0x00100000
9534 11:20:14.299675 COREBOOT 8. 0xffe64000 0x00002000
9535 11:20:14.300243 IMD small region:
9536 11:20:14.306306 IMD ROOT 0. 0xffffec00 0x00000400
9537 11:20:14.309900 VPD 1. 0xffffeba0 0x0000004c
9538 11:20:14.312993 MMC STATUS 2. 0xffffeb80 0x00000004
9539 11:20:14.316219 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9540 11:20:14.320178 Probing TPM: done!
9541 11:20:14.323297 Connected to device vid:did:rid of 1ae0:0028:00
9542 11:20:14.333519 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9543 11:20:14.337077 Initialized TPM device CR50 revision 0
9544 11:20:14.340099 Checking cr50 for pending updates
9545 11:20:14.344108 Reading cr50 TPM mode
9546 11:20:14.352628 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9547 11:20:14.359186 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9548 11:20:14.399629 read SPI 0x3990ec 0x4f1b0: 34845 us, 9298 KB/s, 74.384 Mbps
9549 11:20:14.402222 Checking segment from ROM address 0x40100000
9550 11:20:14.405992 Checking segment from ROM address 0x4010001c
9551 11:20:14.412312 Loading segment from ROM address 0x40100000
9552 11:20:14.412935 code (compression=0)
9553 11:20:14.422005 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9554 11:20:14.428920 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9555 11:20:14.429389 it's not compressed!
9556 11:20:14.435752 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9557 11:20:14.442002 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9558 11:20:14.459508 Loading segment from ROM address 0x4010001c
9559 11:20:14.460108 Entry Point 0x80000000
9560 11:20:14.463032 Loaded segments
9561 11:20:14.466167 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9562 11:20:14.472929 Jumping to boot code at 0x80000000(0xffe64000)
9563 11:20:14.479259 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9564 11:20:14.486031 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9565 11:20:14.493994 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9566 11:20:14.497158 Checking segment from ROM address 0x40100000
9567 11:20:14.500696 Checking segment from ROM address 0x4010001c
9568 11:20:14.507526 Loading segment from ROM address 0x40100000
9569 11:20:14.508002 code (compression=1)
9570 11:20:14.513909 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9571 11:20:14.523854 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9572 11:20:14.524436 using LZMA
9573 11:20:14.532412 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9574 11:20:14.539362 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9575 11:20:14.542336 Loading segment from ROM address 0x4010001c
9576 11:20:14.542905 Entry Point 0x54601000
9577 11:20:14.546109 Loaded segments
9578 11:20:14.548901 NOTICE: MT8192 bl31_setup
9579 11:20:14.556043 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9580 11:20:14.559382 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9581 11:20:14.562973 WARNING: region 0:
9582 11:20:14.566189 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9583 11:20:14.566779 WARNING: region 1:
9584 11:20:14.572967 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9585 11:20:14.575938 WARNING: region 2:
9586 11:20:14.579443 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9587 11:20:14.582611 WARNING: region 3:
9588 11:20:14.585999 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9589 11:20:14.589125 WARNING: region 4:
9590 11:20:14.595639 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9591 11:20:14.596248 WARNING: region 5:
9592 11:20:14.598937 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9593 11:20:14.602239 WARNING: region 6:
9594 11:20:14.605525 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9595 11:20:14.609070 WARNING: region 7:
9596 11:20:14.612414 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9597 11:20:14.618716 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9598 11:20:14.621777 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9599 11:20:14.628982 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9600 11:20:14.632378 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9601 11:20:14.635323 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9602 11:20:14.642171 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9603 11:20:14.645724 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9604 11:20:14.648512 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9605 11:20:14.655325 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9606 11:20:14.658987 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9607 11:20:14.665598 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9608 11:20:14.668470 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9609 11:20:14.671710 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9610 11:20:14.678578 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9611 11:20:14.682257 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9612 11:20:14.685356 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9613 11:20:14.691988 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9614 11:20:14.695538 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9615 11:20:14.701763 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9616 11:20:14.704679 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9617 11:20:14.708416 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9618 11:20:14.715206 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9619 11:20:14.718223 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9620 11:20:14.721305 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9621 11:20:14.728257 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9622 11:20:14.731731 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9623 11:20:14.738136 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9624 11:20:14.741402 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9625 11:20:14.747914 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9626 11:20:14.751188 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9627 11:20:14.754569 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9628 11:20:14.761496 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9629 11:20:14.764700 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9630 11:20:14.768210 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9631 11:20:14.770948 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9632 11:20:14.777820 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9633 11:20:14.781464 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9634 11:20:14.784659 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9635 11:20:14.787557 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9636 11:20:14.794716 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9637 11:20:14.797496 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9638 11:20:14.801217 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9639 11:20:14.807307 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9640 11:20:14.811120 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9641 11:20:14.813990 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9642 11:20:14.817597 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9643 11:20:14.824640 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9644 11:20:14.827275 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9645 11:20:14.830745 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9646 11:20:14.837369 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9647 11:20:14.840995 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9648 11:20:14.847534 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9649 11:20:14.850823 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9650 11:20:14.853825 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9651 11:20:14.860716 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9652 11:20:14.863852 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9653 11:20:14.870598 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9654 11:20:14.873744 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9655 11:20:14.880594 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9656 11:20:14.883490 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9657 11:20:14.890305 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9658 11:20:14.893799 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9659 11:20:14.896925 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9660 11:20:14.903636 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9661 11:20:14.906821 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9662 11:20:14.913667 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9663 11:20:14.916623 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9664 11:20:14.923372 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9665 11:20:14.926620 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9666 11:20:14.933434 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9667 11:20:14.936994 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9668 11:20:14.940119 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9669 11:20:14.947621 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9670 11:20:14.950150 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9671 11:20:14.956910 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9672 11:20:14.959862 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9673 11:20:14.966844 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9674 11:20:14.969778 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9675 11:20:14.976196 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9676 11:20:14.979486 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9677 11:20:14.983070 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9678 11:20:14.989901 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9679 11:20:14.993779 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9680 11:20:15.000240 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9681 11:20:15.002726 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9682 11:20:15.009444 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9683 11:20:15.012902 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9684 11:20:15.016298 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9685 11:20:15.023020 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9686 11:20:15.025952 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9687 11:20:15.032651 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9688 11:20:15.036213 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9689 11:20:15.042479 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9690 11:20:15.045851 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9691 11:20:15.053230 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9692 11:20:15.055880 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9693 11:20:15.059231 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9694 11:20:15.066363 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9695 11:20:15.069609 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9696 11:20:15.072756 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9697 11:20:15.075934 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9698 11:20:15.082591 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9699 11:20:15.085650 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9700 11:20:15.092011 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9701 11:20:15.096761 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9702 11:20:15.099120 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9703 11:20:15.105405 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9704 11:20:15.108906 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9705 11:20:15.115726 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9706 11:20:15.119386 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9707 11:20:15.122197 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9708 11:20:15.129079 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9709 11:20:15.132505 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9710 11:20:15.138554 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9711 11:20:15.142135 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9712 11:20:15.145685 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9713 11:20:15.152821 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9714 11:20:15.155561 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9715 11:20:15.158875 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9716 11:20:15.165740 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9717 11:20:15.168442 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9718 11:20:15.171781 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9719 11:20:15.175650 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9720 11:20:15.178951 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9721 11:20:15.186363 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9722 11:20:15.188700 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9723 11:20:15.195554 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9724 11:20:15.198300 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9725 11:20:15.205258 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9726 11:20:15.208291 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9727 11:20:15.211532 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9728 11:20:15.218506 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9729 11:20:15.221517 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9730 11:20:15.228602 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9731 11:20:15.231078 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9732 11:20:15.234937 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9733 11:20:15.241277 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9734 11:20:15.244916 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9735 11:20:15.247799 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9736 11:20:15.254886 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9737 11:20:15.257994 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9738 11:20:15.264740 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9739 11:20:15.267785 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9740 11:20:15.274378 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9741 11:20:15.277592 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9742 11:20:15.280909 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9743 11:20:15.287750 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9744 11:20:15.291102 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9745 11:20:15.294359 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9746 11:20:15.300664 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9747 11:20:15.303944 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9748 11:20:15.310750 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9749 11:20:15.313738 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9750 11:20:15.317210 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9751 11:20:15.324026 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9752 11:20:15.327257 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9753 11:20:15.333806 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9754 11:20:15.337168 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9755 11:20:15.340669 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9756 11:20:15.347045 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9757 11:20:15.350633 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9758 11:20:15.356977 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9759 11:20:15.360161 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9760 11:20:15.363388 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9761 11:20:15.369891 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9762 11:20:15.373287 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9763 11:20:15.380053 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9764 11:20:15.383489 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9765 11:20:15.386499 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9766 11:20:15.393195 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9767 11:20:15.396270 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9768 11:20:15.403023 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9769 11:20:15.406262 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9770 11:20:15.409375 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9771 11:20:15.416593 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9772 11:20:15.419591 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9773 11:20:15.425793 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9774 11:20:15.429965 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9775 11:20:15.436013 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9776 11:20:15.439415 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9777 11:20:15.442815 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9778 11:20:15.449673 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9779 11:20:15.452698 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9780 11:20:15.455915 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9781 11:20:15.462704 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9782 11:20:15.465727 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9783 11:20:15.472420 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9784 11:20:15.475904 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9785 11:20:15.478788 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9786 11:20:15.485920 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9787 11:20:15.488896 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9788 11:20:15.495652 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9789 11:20:15.498515 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9790 11:20:15.505463 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9791 11:20:15.508550 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9792 11:20:15.511458 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9793 11:20:15.518305 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9794 11:20:15.522023 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9795 11:20:15.528503 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9796 11:20:15.531636 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9797 11:20:15.538614 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9798 11:20:15.541751 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9799 11:20:15.545203 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9800 11:20:15.551165 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9801 11:20:15.554676 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9802 11:20:15.561447 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9803 11:20:15.564849 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9804 11:20:15.571780 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9805 11:20:15.575241 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9806 11:20:15.578322 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9807 11:20:15.585163 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9808 11:20:15.587986 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9809 11:20:15.594591 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9810 11:20:15.597866 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9811 11:20:15.600923 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9812 11:20:15.608103 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9813 11:20:15.610922 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9814 11:20:15.618327 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9815 11:20:15.621357 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9816 11:20:15.628235 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9817 11:20:15.630903 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9818 11:20:15.634844 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9819 11:20:15.641173 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9820 11:20:15.644322 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9821 11:20:15.650459 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9822 11:20:15.653665 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9823 11:20:15.660637 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9824 11:20:15.663726 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9825 11:20:15.667499 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9826 11:20:15.674210 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9827 11:20:15.677098 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9828 11:20:15.680477 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9829 11:20:15.683668 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9830 11:20:15.690213 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9831 11:20:15.693531 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9832 11:20:15.697186 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9833 11:20:15.703873 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9834 11:20:15.706702 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9835 11:20:15.709984 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9836 11:20:15.716560 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9837 11:20:15.719893 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9838 11:20:15.726502 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9839 11:20:15.729526 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9840 11:20:15.733155 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9841 11:20:15.739886 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9842 11:20:15.743227 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9843 11:20:15.746167 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9844 11:20:15.752848 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9845 11:20:15.756153 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9846 11:20:15.762775 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9847 11:20:15.766222 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9848 11:20:15.769414 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9849 11:20:15.776474 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9850 11:20:15.779633 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9851 11:20:15.782944 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9852 11:20:15.789831 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9853 11:20:15.792682 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9854 11:20:15.800098 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9855 11:20:15.802992 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9856 11:20:15.806165 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9857 11:20:15.812615 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9858 11:20:15.815654 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9859 11:20:15.822272 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9860 11:20:15.825759 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9861 11:20:15.828695 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9862 11:20:15.835794 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9863 11:20:15.839299 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9864 11:20:15.842010 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9865 11:20:15.848829 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9866 11:20:15.851928 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9867 11:20:15.855342 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9868 11:20:15.858220 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9869 11:20:15.865173 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9870 11:20:15.868256 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9871 11:20:15.871568 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9872 11:20:15.875246 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9873 11:20:15.881433 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9874 11:20:15.884893 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9875 11:20:15.888360 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9876 11:20:15.891959 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9877 11:20:15.897992 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9878 11:20:15.901502 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9879 11:20:15.904674 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9880 11:20:15.911511 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9881 11:20:15.914625 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9882 11:20:15.921932 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9883 11:20:15.924795 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9884 11:20:15.931194 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9885 11:20:15.934222 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9886 11:20:15.937616 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9887 11:20:15.944600 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9888 11:20:15.947820 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9889 11:20:15.953891 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9890 11:20:15.957652 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9891 11:20:15.960819 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9892 11:20:15.966952 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9893 11:20:15.970660 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9894 11:20:15.977369 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9895 11:20:15.980660 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9896 11:20:15.983848 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9897 11:20:15.990308 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9898 11:20:15.993855 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9899 11:20:16.000479 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9900 11:20:16.004078 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9901 11:20:16.010430 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9902 11:20:16.013438 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9903 11:20:16.017069 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9904 11:20:16.023737 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9905 11:20:16.027309 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9906 11:20:16.033597 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9907 11:20:16.036730 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9908 11:20:16.040105 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9909 11:20:16.047188 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9910 11:20:16.050133 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9911 11:20:16.057317 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9912 11:20:16.060105 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9913 11:20:16.063566 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9914 11:20:16.070603 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9915 11:20:16.073096 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9916 11:20:16.080043 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9917 11:20:16.083335 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9918 11:20:16.090093 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9919 11:20:16.093268 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9920 11:20:16.096436 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9921 11:20:16.103232 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9922 11:20:16.106194 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9923 11:20:16.112799 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9924 11:20:16.116114 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9925 11:20:16.123371 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9926 11:20:16.126222 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9927 11:20:16.129642 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9928 11:20:16.136404 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9929 11:20:16.139425 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9930 11:20:16.146273 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9931 11:20:16.149426 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9932 11:20:16.152842 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9933 11:20:16.159470 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9934 11:20:16.162788 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9935 11:20:16.169405 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9936 11:20:16.172636 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9937 11:20:16.175826 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9938 11:20:16.182585 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9939 11:20:16.185733 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9940 11:20:16.192306 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9941 11:20:16.195617 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9942 11:20:16.199012 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9943 11:20:16.205375 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9944 11:20:16.208784 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9945 11:20:16.215559 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9946 11:20:16.218805 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9947 11:20:16.225201 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9948 11:20:16.228643 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9949 11:20:16.235535 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9950 11:20:16.238478 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9951 11:20:16.241930 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9952 11:20:16.248571 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9953 11:20:16.252034 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9954 11:20:16.258186 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9955 11:20:16.261646 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9956 11:20:16.268235 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9957 11:20:16.271350 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9958 11:20:16.274713 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9959 11:20:16.281792 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9960 11:20:16.284638 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9961 11:20:16.291348 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9962 11:20:16.295346 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9963 11:20:16.301450 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9964 11:20:16.304817 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9965 11:20:16.307786 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9966 11:20:16.314930 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9967 11:20:16.318041 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9968 11:20:16.324406 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9969 11:20:16.327797 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9970 11:20:16.334688 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9971 11:20:16.338337 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9972 11:20:16.344647 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9973 11:20:16.348009 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9974 11:20:16.351129 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9975 11:20:16.357523 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9976 11:20:16.361416 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9977 11:20:16.367518 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9978 11:20:16.370799 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9979 11:20:16.377405 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9980 11:20:16.380889 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9981 11:20:16.387492 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9982 11:20:16.390277 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9983 11:20:16.394009 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9984 11:20:16.400582 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9985 11:20:16.403475 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9986 11:20:16.410448 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9987 11:20:16.413705 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9988 11:20:16.420558 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9989 11:20:16.423508 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9990 11:20:16.426581 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9991 11:20:16.433455 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9992 11:20:16.436486 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9993 11:20:16.443297 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9994 11:20:16.446376 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9995 11:20:16.453203 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9996 11:20:16.456237 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9997 11:20:16.462804 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9998 11:20:16.466449 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9999 11:20:16.469634 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
10000 11:20:16.476377 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
10001 11:20:16.479463 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
10002 11:20:16.485876 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
10003 11:20:16.489197 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
10004 11:20:16.496115 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
10005 11:20:16.499165 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
10006 11:20:16.506044 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
10007 11:20:16.509413 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
10008 11:20:16.515657 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
10009 11:20:16.518727 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
10010 11:20:16.525344 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
10011 11:20:16.529270 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
10012 11:20:16.536263 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
10013 11:20:16.538829 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
10014 11:20:16.545402 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
10015 11:20:16.548603 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
10016 11:20:16.555512 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
10017 11:20:16.558567 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
10018 11:20:16.565353 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
10019 11:20:16.568780 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
10020 11:20:16.575517 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
10021 11:20:16.578420 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
10022 11:20:16.584779 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
10023 11:20:16.588313 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
10024 11:20:16.594669 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
10025 11:20:16.597833 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
10026 11:20:16.604820 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
10027 11:20:16.608071 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
10028 11:20:16.614526 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
10029 11:20:16.617658 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
10030 11:20:16.624116 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10031 11:20:16.627653 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10032 11:20:16.631445 INFO: [APUAPC] vio 0
10033 11:20:16.634075 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10034 11:20:16.641118 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10035 11:20:16.644089 INFO: [APUAPC] D0_APC_0: 0x400510
10036 11:20:16.644706 INFO: [APUAPC] D0_APC_1: 0x0
10037 11:20:16.647522 INFO: [APUAPC] D0_APC_2: 0x1540
10038 11:20:16.651154 INFO: [APUAPC] D0_APC_3: 0x0
10039 11:20:16.653996 INFO: [APUAPC] D1_APC_0: 0xffffffff
10040 11:20:16.657249 INFO: [APUAPC] D1_APC_1: 0xffffffff
10041 11:20:16.660483 INFO: [APUAPC] D1_APC_2: 0x3fffff
10042 11:20:16.663947 INFO: [APUAPC] D1_APC_3: 0x0
10043 11:20:16.667648 INFO: [APUAPC] D2_APC_0: 0xffffffff
10044 11:20:16.670659 INFO: [APUAPC] D2_APC_1: 0xffffffff
10045 11:20:16.673557 INFO: [APUAPC] D2_APC_2: 0x3fffff
10046 11:20:16.677401 INFO: [APUAPC] D2_APC_3: 0x0
10047 11:20:16.680992 INFO: [APUAPC] D3_APC_0: 0xffffffff
10048 11:20:16.683635 INFO: [APUAPC] D3_APC_1: 0xffffffff
10049 11:20:16.686822 INFO: [APUAPC] D3_APC_2: 0x3fffff
10050 11:20:16.689980 INFO: [APUAPC] D3_APC_3: 0x0
10051 11:20:16.693654 INFO: [APUAPC] D4_APC_0: 0xffffffff
10052 11:20:16.697304 INFO: [APUAPC] D4_APC_1: 0xffffffff
10053 11:20:16.700241 INFO: [APUAPC] D4_APC_2: 0x3fffff
10054 11:20:16.703518 INFO: [APUAPC] D4_APC_3: 0x0
10055 11:20:16.706746 INFO: [APUAPC] D5_APC_0: 0xffffffff
10056 11:20:16.709814 INFO: [APUAPC] D5_APC_1: 0xffffffff
10057 11:20:16.713699 INFO: [APUAPC] D5_APC_2: 0x3fffff
10058 11:20:16.716681 INFO: [APUAPC] D5_APC_3: 0x0
10059 11:20:16.720019 INFO: [APUAPC] D6_APC_0: 0xffffffff
10060 11:20:16.723245 INFO: [APUAPC] D6_APC_1: 0xffffffff
10061 11:20:16.726690 INFO: [APUAPC] D6_APC_2: 0x3fffff
10062 11:20:16.730064 INFO: [APUAPC] D6_APC_3: 0x0
10063 11:20:16.733167 INFO: [APUAPC] D7_APC_0: 0xffffffff
10064 11:20:16.736721 INFO: [APUAPC] D7_APC_1: 0xffffffff
10065 11:20:16.739661 INFO: [APUAPC] D7_APC_2: 0x3fffff
10066 11:20:16.743661 INFO: [APUAPC] D7_APC_3: 0x0
10067 11:20:16.746782 INFO: [APUAPC] D8_APC_0: 0xffffffff
10068 11:20:16.750138 INFO: [APUAPC] D8_APC_1: 0xffffffff
10069 11:20:16.753062 INFO: [APUAPC] D8_APC_2: 0x3fffff
10070 11:20:16.756833 INFO: [APUAPC] D8_APC_3: 0x0
10071 11:20:16.759916 INFO: [APUAPC] D9_APC_0: 0xffffffff
10072 11:20:16.763176 INFO: [APUAPC] D9_APC_1: 0xffffffff
10073 11:20:16.766768 INFO: [APUAPC] D9_APC_2: 0x3fffff
10074 11:20:16.769922 INFO: [APUAPC] D9_APC_3: 0x0
10075 11:20:16.772791 INFO: [APUAPC] D10_APC_0: 0xffffffff
10076 11:20:16.776268 INFO: [APUAPC] D10_APC_1: 0xffffffff
10077 11:20:16.779355 INFO: [APUAPC] D10_APC_2: 0x3fffff
10078 11:20:16.782582 INFO: [APUAPC] D10_APC_3: 0x0
10079 11:20:16.786191 INFO: [APUAPC] D11_APC_0: 0xffffffff
10080 11:20:16.789655 INFO: [APUAPC] D11_APC_1: 0xffffffff
10081 11:20:16.792564 INFO: [APUAPC] D11_APC_2: 0x3fffff
10082 11:20:16.796090 INFO: [APUAPC] D11_APC_3: 0x0
10083 11:20:16.799051 INFO: [APUAPC] D12_APC_0: 0xffffffff
10084 11:20:16.802321 INFO: [APUAPC] D12_APC_1: 0xffffffff
10085 11:20:16.805936 INFO: [APUAPC] D12_APC_2: 0x3fffff
10086 11:20:16.809052 INFO: [APUAPC] D12_APC_3: 0x0
10087 11:20:16.812328 INFO: [APUAPC] D13_APC_0: 0xffffffff
10088 11:20:16.815634 INFO: [APUAPC] D13_APC_1: 0xffffffff
10089 11:20:16.818963 INFO: [APUAPC] D13_APC_2: 0x3fffff
10090 11:20:16.822518 INFO: [APUAPC] D13_APC_3: 0x0
10091 11:20:16.825852 INFO: [APUAPC] D14_APC_0: 0xffffffff
10092 11:20:16.828444 INFO: [APUAPC] D14_APC_1: 0xffffffff
10093 11:20:16.832653 INFO: [APUAPC] D14_APC_2: 0x3fffff
10094 11:20:16.835326 INFO: [APUAPC] D14_APC_3: 0x0
10095 11:20:16.838568 INFO: [APUAPC] D15_APC_0: 0xffffffff
10096 11:20:16.841700 INFO: [APUAPC] D15_APC_1: 0xffffffff
10097 11:20:16.845346 INFO: [APUAPC] D15_APC_2: 0x3fffff
10098 11:20:16.848669 INFO: [APUAPC] D15_APC_3: 0x0
10099 11:20:16.852252 INFO: [APUAPC] APC_CON: 0x4
10100 11:20:16.855634 INFO: [NOCDAPC] D0_APC_0: 0x0
10101 11:20:16.858864 INFO: [NOCDAPC] D0_APC_1: 0x0
10102 11:20:16.861642 INFO: [NOCDAPC] D1_APC_0: 0x0
10103 11:20:16.865119 INFO: [NOCDAPC] D1_APC_1: 0xfff
10104 11:20:16.865689 INFO: [NOCDAPC] D2_APC_0: 0x0
10105 11:20:16.868422 INFO: [NOCDAPC] D2_APC_1: 0xfff
10106 11:20:16.872257 INFO: [NOCDAPC] D3_APC_0: 0x0
10107 11:20:16.874968 INFO: [NOCDAPC] D3_APC_1: 0xfff
10108 11:20:16.878715 INFO: [NOCDAPC] D4_APC_0: 0x0
10109 11:20:16.881426 INFO: [NOCDAPC] D4_APC_1: 0xfff
10110 11:20:16.884927 INFO: [NOCDAPC] D5_APC_0: 0x0
10111 11:20:16.888460 INFO: [NOCDAPC] D5_APC_1: 0xfff
10112 11:20:16.891507 INFO: [NOCDAPC] D6_APC_0: 0x0
10113 11:20:16.894891 INFO: [NOCDAPC] D6_APC_1: 0xfff
10114 11:20:16.897822 INFO: [NOCDAPC] D7_APC_0: 0x0
10115 11:20:16.901176 INFO: [NOCDAPC] D7_APC_1: 0xfff
10116 11:20:16.901644 INFO: [NOCDAPC] D8_APC_0: 0x0
10117 11:20:16.904830 INFO: [NOCDAPC] D8_APC_1: 0xfff
10118 11:20:16.908053 INFO: [NOCDAPC] D9_APC_0: 0x0
10119 11:20:16.911298 INFO: [NOCDAPC] D9_APC_1: 0xfff
10120 11:20:16.914933 INFO: [NOCDAPC] D10_APC_0: 0x0
10121 11:20:16.917473 INFO: [NOCDAPC] D10_APC_1: 0xfff
10122 11:20:16.921134 INFO: [NOCDAPC] D11_APC_0: 0x0
10123 11:20:16.924144 INFO: [NOCDAPC] D11_APC_1: 0xfff
10124 11:20:16.927990 INFO: [NOCDAPC] D12_APC_0: 0x0
10125 11:20:16.931318 INFO: [NOCDAPC] D12_APC_1: 0xfff
10126 11:20:16.934716 INFO: [NOCDAPC] D13_APC_0: 0x0
10127 11:20:16.937415 INFO: [NOCDAPC] D13_APC_1: 0xfff
10128 11:20:16.941276 INFO: [NOCDAPC] D14_APC_0: 0x0
10129 11:20:16.944374 INFO: [NOCDAPC] D14_APC_1: 0xfff
10130 11:20:16.947626 INFO: [NOCDAPC] D15_APC_0: 0x0
10131 11:20:16.950770 INFO: [NOCDAPC] D15_APC_1: 0xfff
10132 11:20:16.951352 INFO: [NOCDAPC] APC_CON: 0x4
10133 11:20:16.954117 INFO: [APUAPC] set_apusys_apc done
10134 11:20:16.957698 INFO: [DEVAPC] devapc_init done
10135 11:20:16.964192 INFO: GICv3 without legacy support detected.
10136 11:20:16.967005 INFO: ARM GICv3 driver initialized in EL3
10137 11:20:16.970543 INFO: Maximum SPI INTID supported: 639
10138 11:20:16.973892 INFO: BL31: Initializing runtime services
10139 11:20:16.980613 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10140 11:20:16.984059 INFO: SPM: enable CPC mode
10141 11:20:16.986804 INFO: mcdi ready for mcusys-off-idle and system suspend
10142 11:20:16.994526 INFO: BL31: Preparing for EL3 exit to normal world
10143 11:20:16.996769 INFO: Entry point address = 0x80000000
10144 11:20:16.997355 INFO: SPSR = 0x8
10145 11:20:17.004141
10146 11:20:17.004750
10147 11:20:17.005236
10148 11:20:17.007826 Starting depthcharge on Spherion...
10149 11:20:17.008405
10150 11:20:17.008935 Wipe memory regions:
10151 11:20:17.009393
10152 11:20:17.011948 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10153 11:20:17.012631 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10154 11:20:17.013139 Setting prompt string to ['asurada:']
10155 11:20:17.013679 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10156 11:20:17.014519 [0x00000040000000, 0x00000054600000)
10157 11:20:17.132793
10158 11:20:17.133366 [0x00000054660000, 0x00000080000000)
10159 11:20:17.393278
10160 11:20:17.393849 [0x000000821a7280, 0x000000ffe64000)
10161 11:20:18.138065
10162 11:20:18.138642 [0x00000100000000, 0x00000240000000)
10163 11:20:20.027412
10164 11:20:20.030684 Initializing XHCI USB controller at 0x11200000.
10165 11:20:21.012068
10166 11:20:21.012603 R8152: Initializing
10167 11:20:21.012948
10168 11:20:21.015804 Version 9 (ocp_data = 6010)
10169 11:20:21.016229
10170 11:20:21.018665 R8152: Done initializing
10171 11:20:21.019089
10172 11:20:21.019427 Adding net device
10173 11:20:21.542032
10174 11:20:21.544330 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10175 11:20:21.544913
10176 11:20:21.545289
10177 11:20:21.545657
10178 11:20:21.546453 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10180 11:20:21.647633 asurada: tftpboot 192.168.201.1 10591284/tftp-deploy-n9bs2myb/kernel/image.itb 10591284/tftp-deploy-n9bs2myb/kernel/cmdline
10181 11:20:21.648174 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10182 11:20:21.648628 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:20)
10183 11:20:21.653031 tftpboot 192.168.201.1 10591284/tftp-deploy-n9bs2myb/kernel/image.itp-deploy-n9bs2myb/kernel/cmdline
10184 11:20:21.653470
10185 11:20:21.653808 Waiting for link
10186 11:20:21.855165
10187 11:20:21.855658 done.
10188 11:20:21.856003
10189 11:20:21.856445 MAC: f4:f5:e8:50:de:0a
10190 11:20:21.857180
10191 11:20:21.859069 Sending DHCP discover... done.
10192 11:20:21.859499
10193 11:20:21.862142 Waiting for reply... done.
10194 11:20:21.862574
10195 11:20:21.865378 Sending DHCP request... done.
10196 11:20:21.865805
10197 11:20:21.870541 Waiting for reply... done.
10198 11:20:21.870970
10199 11:20:21.871310 My ip is 192.168.201.14
10200 11:20:21.871626
10201 11:20:21.874427 The DHCP server ip is 192.168.201.1
10202 11:20:21.874857
10203 11:20:21.880765 TFTP server IP predefined by user: 192.168.201.1
10204 11:20:21.881326
10205 11:20:21.886870 Bootfile predefined by user: 10591284/tftp-deploy-n9bs2myb/kernel/image.itb
10206 11:20:21.887468
10207 11:20:21.890571 Sending tftp read request... done.
10208 11:20:21.891003
10209 11:20:21.896031 Waiting for the transfer...
10210 11:20:21.896640
10211 11:20:22.236816 00000000 ################################################################
10212 11:20:22.237479
10213 11:20:22.511273 00080000 ################################################################
10214 11:20:22.511438
10215 11:20:22.820398 00100000 ################################################################
10216 11:20:22.820584
10217 11:20:23.177789 00180000 ################################################################
10218 11:20:23.177941
10219 11:20:23.522768 00200000 ################################################################
10220 11:20:23.522920
10221 11:20:23.841457 00280000 ################################################################
10222 11:20:23.841596
10223 11:20:24.133792 00300000 ################################################################
10224 11:20:24.133930
10225 11:20:24.379184 00380000 ################################################################
10226 11:20:24.379316
10227 11:20:24.632560 00400000 ################################################################
10228 11:20:24.632703
10229 11:20:24.895695 00480000 ################################################################
10230 11:20:24.895831
10231 11:20:25.152837 00500000 ################################################################
10232 11:20:25.152977
10233 11:20:25.493495 00580000 ################################################################
10234 11:20:25.493673
10235 11:20:25.842455 00600000 ################################################################
10236 11:20:25.842635
10237 11:20:26.188412 00680000 ################################################################
10238 11:20:26.188598
10239 11:20:26.466439 00700000 ################################################################
10240 11:20:26.466578
10241 11:20:26.735517 00780000 ################################################################
10242 11:20:26.735665
10243 11:20:26.994997 00800000 ################################################################
10244 11:20:26.995134
10245 11:20:27.241677 00880000 ################################################################
10246 11:20:27.241818
10247 11:20:27.478505 00900000 ################################################################
10248 11:20:27.478655
10249 11:20:27.734989 00980000 ################################################################
10250 11:20:27.735146
10251 11:20:27.988453 00a00000 ################################################################
10252 11:20:27.988627
10253 11:20:28.235989 00a80000 ################################################################
10254 11:20:28.236132
10255 11:20:28.487999 00b00000 ################################################################
10256 11:20:28.488143
10257 11:20:28.725106 00b80000 ################################################################
10258 11:20:28.725250
10259 11:20:28.964336 00c00000 ################################################################
10260 11:20:28.964503
10261 11:20:29.196645 00c80000 ################################################################
10262 11:20:29.196777
10263 11:20:29.438957 00d00000 ################################################################
10264 11:20:29.439090
10265 11:20:29.698383 00d80000 ################################################################
10266 11:20:29.698555
10267 11:20:29.927543 00e00000 ################################################################
10268 11:20:29.927702
10269 11:20:30.179411 00e80000 ################################################################
10270 11:20:30.179570
10271 11:20:30.409991 00f00000 ################################################################
10272 11:20:30.410124
10273 11:20:30.661373 00f80000 ################################################################
10274 11:20:30.661539
10275 11:20:30.913911 01000000 ################################################################
10276 11:20:30.914073
10277 11:20:31.140160 01080000 ################################################################
10278 11:20:31.140319
10279 11:20:31.364456 01100000 ################################################################
10280 11:20:31.364642
10281 11:20:31.588000 01180000 ################################################################
10282 11:20:31.588162
10283 11:20:31.817496 01200000 ################################################################
10284 11:20:31.817649
10285 11:20:32.131351 01280000 ################################################################
10286 11:20:32.131522
10287 11:20:32.376613 01300000 ################################################################
10288 11:20:32.376789
10289 11:20:32.651055 01380000 ################################################################
10290 11:20:32.651208
10291 11:20:32.916865 01400000 ################################################################
10292 11:20:32.917015
10293 11:20:33.156762 01480000 ################################################################
10294 11:20:33.156912
10295 11:20:33.401435 01500000 ################################################################
10296 11:20:33.401588
10297 11:20:33.658616 01580000 ################################################################
10298 11:20:33.658766
10299 11:20:33.929189 01600000 ################################################################
10300 11:20:33.929334
10301 11:20:34.202179 01680000 ################################################################
10302 11:20:34.202354
10303 11:20:34.508444 01700000 ################################################################
10304 11:20:34.508627
10305 11:20:34.838344 01780000 ################################################################
10306 11:20:34.838494
10307 11:20:35.142869 01800000 ################################################################
10308 11:20:35.143021
10309 11:20:35.433622 01880000 ################################################################
10310 11:20:35.433777
10311 11:20:35.718875 01900000 ################################################################
10312 11:20:35.719035
10313 11:20:36.016617 01980000 ################################################################
10314 11:20:36.016784
10315 11:20:36.279578 01a00000 ################################################################
10316 11:20:36.279728
10317 11:20:36.552908 01a80000 ################################################################
10318 11:20:36.553061
10319 11:20:36.761092 01b00000 ##################################################### done.
10320 11:20:36.761242
10321 11:20:36.765333 The bootfile was 28738958 bytes long.
10322 11:20:36.765426
10323 11:20:36.767947 Sending tftp read request... done.
10324 11:20:36.768031
10325 11:20:36.770953 Waiting for the transfer...
10326 11:20:36.771041
10327 11:20:36.771107 00000000 # done.
10328 11:20:36.771172
10329 11:20:36.781121 Command line loaded dynamically from TFTP file: 10591284/tftp-deploy-n9bs2myb/kernel/cmdline
10330 11:20:36.781206
10331 11:20:36.797505 The command line is: console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10591284/extract-nfsrootfs-85gyi42f,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10332 11:20:36.797594
10333 11:20:36.797659 Loading FIT.
10334 11:20:36.797720
10335 11:20:36.800545 Image ramdisk-1 has 18603978 bytes.
10336 11:20:36.800642
10337 11:20:36.804367 Image fdt-1 has 46924 bytes.
10338 11:20:36.804450
10339 11:20:36.807813 Image kernel-1 has 10086024 bytes.
10340 11:20:36.807895
10341 11:20:36.814432 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10342 11:20:36.814516
10343 11:20:36.833793 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10344 11:20:36.833882
10345 11:20:36.837687 Choosing best match conf-1 for compat google,spherion-rev2.
10346 11:20:36.842479
10347 11:20:36.847342 Connected to device vid:did:rid of 1ae0:0028:00
10348 11:20:36.854514
10349 11:20:36.857513 tpm_get_response: command 0x17b, return code 0x0
10350 11:20:36.858061
10351 11:20:36.864867 ec_init: CrosEC protocol v3 supported (256, 248)
10352 11:20:36.865355
10353 11:20:36.867479 tpm_cleanup: add release locality here.
10354 11:20:36.867970
10355 11:20:36.870361 Shutting down all USB controllers.
10356 11:20:36.870833
10357 11:20:36.874117 Removing current net device
10358 11:20:36.874591
10359 11:20:36.877046 Exiting depthcharge with code 4 at timestamp: 49332339
10360 11:20:36.877476
10361 11:20:36.880380 LZMA decompressing kernel-1 to 0x821a6718
10362 11:20:36.880838
10363 11:20:36.883612 LZMA decompressing kernel-1 to 0x40000000
10364 11:20:38.151988
10365 11:20:38.152146 jumping to kernel
10366 11:20:38.152556 end: 2.2.4 bootloader-commands (duration 00:00:21) [common]
10367 11:20:38.152663 start: 2.2.5 auto-login-action (timeout 00:04:04) [common]
10368 11:20:38.152739 Setting prompt string to ['Linux version [0-9]']
10369 11:20:38.152809 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10370 11:20:38.152879 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10371 11:20:38.702176
10372 11:20:38.705135 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10373 11:20:38.709034 start: 2.2.5.1 login-action (timeout 00:04:03) [common]
10374 11:20:38.709128 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10375 11:20:38.709212 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10376 11:20:38.709290 Using line separator: #'\n'#
10377 11:20:38.709351 No login prompt set.
10378 11:20:38.709412 Parsing kernel messages
10379 11:20:38.709468 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10380 11:20:38.709570 [login-action] Waiting for messages, (timeout 00:04:03)
10381 11:20:38.728443 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1609115-arm64-gcc-10-defconfig-arm64-chromebook-dplkv) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 10:57:14 UTC 2023
10382 11:20:38.731386 [ 0.000000] random: crng init done
10383 11:20:38.738654 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10384 11:20:38.741494 [ 0.000000] efi: UEFI not found.
10385 11:20:38.748288 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10386 11:20:38.754932 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10387 11:20:38.764924 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10388 11:20:38.774472 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10389 11:20:38.777728 [ 0.000000] NUMA: No NUMA configuration found
10390 11:20:38.787664 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10391 11:20:38.791253 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10392 11:20:38.794333 [ 0.000000] Zone ranges:
10393 11:20:38.801220 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10394 11:20:38.804750 [ 0.000000] DMA32 empty
10395 11:20:38.810883 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10396 11:20:38.814278 [ 0.000000] Movable zone start for each node
10397 11:20:38.817363 [ 0.000000] Early memory node ranges
10398 11:20:38.824016 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10399 11:20:38.830787 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10400 11:20:38.837100 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10401 11:20:38.844586 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10402 11:20:38.847933 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10403 11:20:38.857281 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10404 11:20:38.860428 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10405 11:20:38.867643 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10406 11:20:38.874236 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10407 11:20:38.876998 [ 0.000000] psci: probing for conduit method from DT.
10408 11:20:38.883842 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10409 11:20:38.886939 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10410 11:20:38.894077 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10411 11:20:38.897108 [ 0.000000] psci: SMC Calling Convention v1.2
10412 11:20:38.903708 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10413 11:20:38.907023 [ 0.000000] Detected VIPT I-cache on CPU0
10414 11:20:38.913259 [ 0.000000] CPU features: detected: GIC system register CPU interface
10415 11:20:38.919938 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10416 11:20:38.927256 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10417 11:20:38.933570 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10418 11:20:38.943957 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10419 11:20:38.950283 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10420 11:20:38.953022 [ 0.000000] alternatives: applying boot alternatives
10421 11:20:38.956382 [ 0.000000] Fallback order for Node 0: 0
10422 11:20:38.963075 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10423 11:20:38.966894 [ 0.000000] Policy zone: Normal
10424 11:20:38.986440 [ 0.000000] Kernel command line: console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10591284/extract-nfsrootfs-85gyi42f,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10425 11:20:38.996327 [ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10426 11:20:39.002964 [ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10427 11:20:39.013325 [ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10428 11:20:39.019184 [ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10429 11:20:39.022688 [ 0.000000] software IO TLB: area num 8.
10430 11:20:39.029444 [ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10431 11:20:39.042600 [ 0.000000] Memory: 7954772K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397996K reserved, 32768K cma-reserved)
10432 11:20:39.048816 [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10433 11:20:39.055695 [ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10434 11:20:39.058916 [ 0.000000] rcu: RCU event tracing is enabled.
10435 11:20:39.065864 [ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10436 11:20:39.071793 [ 0.000000] Trampoline variant of Tasks RCU enabled.
10437 11:20:39.075597 [ 0.000000] Tracing variant of Tasks RCU enabled.
10438 11:20:39.085502 [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10439 11:20:39.091814 [ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10440 11:20:39.095187 [ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10441 11:20:39.102422 [ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10442 11:20:39.105457 [ 0.000000] GICv3: 608 SPIs implemented
10443 11:20:39.111514 [ 0.000000] GICv3: 0 Extended SPIs implemented
10444 11:20:39.115073 [ 0.000000] Root IRQ handler: gic_handle_irq
10445 11:20:39.118298 [ 0.000000] GICv3: GICv3 features: 16 PPIs
10446 11:20:39.124774 [ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10447 11:20:39.138309 [ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10448 11:20:39.148379 [ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10449 11:20:39.154738 [ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10450 11:20:39.161162 [ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10451 11:20:39.174921 [ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10452 11:20:39.181135 [ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10453 11:20:39.184610 [ 0.000949] Console: colour dummy device 80x25
10454 11:20:39.194746 [ 0.001015] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10455 11:20:39.201395 [ 0.001022] pid_max: default: 32768 minimum: 301
10456 11:20:39.204281 [ 0.001065] LSM: Security Framework initializing
10457 11:20:39.211423 [ 0.001173] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10458 11:20:39.220637 [ 0.001224] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10459 11:20:39.227161 [ 0.002462] cblist_init_generic: Setting adjustable number of callback queues.
10460 11:20:39.234094 [ 0.002473] cblist_init_generic: Setting shift to 3 and lim to 1.
10461 11:20:39.240496 [ 0.002515] cblist_init_generic: Setting shift to 3 and lim to 1.
10462 11:20:39.243878 [ 0.002621] rcu: Hierarchical SRCU implementation.
10463 11:20:39.250355 [ 0.002624] rcu: Max phase no-delay instances is 1000.
10464 11:20:39.253922 [ 0.004250] EFI services will not be available.
10465 11:20:39.260227 [ 0.004472] smp: Bringing up secondary CPUs ...
10466 11:20:39.263646 [ 0.004767] Detected VIPT I-cache on CPU1
10467 11:20:39.270185 [ 0.004840] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10468 11:20:39.277169 [ 0.004872] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10469 11:20:39.280271 [ 0.005216] Detected VIPT I-cache on CPU2
10470 11:20:39.286641 [ 0.005265] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10471 11:20:39.293171 [ 0.005282] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10472 11:20:39.296685 [ 0.005541] Detected VIPT I-cache on CPU3
10473 11:20:39.303468 [ 0.005588] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10474 11:20:39.310245 [ 0.005602] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10475 11:20:39.316651 [ 0.005908] CPU features: detected: Spectre-v4
10476 11:20:39.319899 [ 0.005914] CPU features: detected: Spectre-BHB
10477 11:20:39.323607 [ 0.005920] Detected PIPT I-cache on CPU4
10478 11:20:39.333162 [ 0.005978] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10479 11:20:39.337354 [ 0.005994] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10480 11:20:39.343060 [ 0.006291] Detected PIPT I-cache on CPU5
10481 11:20:39.349799 [ 0.006354] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10482 11:20:39.356353 [ 0.006371] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10483 11:20:39.360101 [ 0.006655] Detected PIPT I-cache on CPU6
10484 11:20:39.365991 [ 0.006719] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10485 11:20:39.372648 [ 0.006735] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10486 11:20:39.375849 [ 0.007031] Detected PIPT I-cache on CPU7
10487 11:20:39.382538 [ 0.007097] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10488 11:20:39.389455 [ 0.007114] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10489 11:20:39.395804 [ 0.007161] smp: Brought up 1 node, 8 CPUs
10490 11:20:39.398777 [ 0.007167] SMP: Total of 8 processors activated.
10491 11:20:39.405492 [ 0.007170] CPU features: detected: 32-bit EL0 Support
10492 11:20:39.412163 [ 0.007173] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10493 11:20:39.419356 [ 0.007175] CPU features: detected: Common not Private translations
10494 11:20:39.425882 [ 0.007177] CPU features: detected: CRC32 instructions
10495 11:20:39.428876 [ 0.007180] CPU features: detected: RCpc load-acquire (LDAPR)
10496 11:20:39.435805 [ 0.007182] CPU features: detected: LSE atomic instructions
10497 11:20:39.442226 [ 0.007184] CPU features: detected: Privileged Access Never
10498 11:20:39.445950 [ 0.007185] CPU features: detected: RAS Extension Support
10499 11:20:39.455204 [ 0.007189] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10500 11:20:39.458605 [ 0.007262] CPU: All CPU(s) started at EL2
10501 11:20:39.461637 [ 0.007264] alternatives: applying system-wide alternatives
10502 11:20:39.464790 [ 0.012229] devtmpfs: initialized
10503 11:20:39.474928 [ 0.017800] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10504 11:20:39.485256 [ 0.017815] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10505 11:20:39.489262 [ 0.018827] pinctrl core: initialized pinctrl subsystem
10506 11:20:39.491878 [ 0.020056] DMI not present or invalid.
10507 11:20:39.498363 [ 0.020395] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10508 11:20:39.504840 [ 0.021130] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10509 11:20:39.514694 [ 0.021355] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10510 11:20:39.521429 [ 0.021535] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10511 11:20:39.527671 [ 0.021559] audit: initializing netlink subsys (disabled)
10512 11:20:39.534312 [ 0.021632] audit: type=2000 audit(0.016:1): state=initialized audit_enabled=0 res=1
10513 11:20:39.540883 [ 0.022340] thermal_sys: Registered thermal governor 'step_wise'
10514 11:20:39.547749 [ 0.022344] thermal_sys: Registered thermal governor 'power_allocator'
10515 11:20:39.550705 [ 0.022373] cpuidle: using governor menu
10516 11:20:39.554387 [ 0.022439] NET: Registered PF_QIPCRTR protocol family
10517 11:20:39.564204 [ 0.022554] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10518 11:20:39.567234 [ 0.022645] ASID allocator initialised with 32768 entries
10519 11:20:39.570727 [ 0.023607] Serial: AMBA PL011 UART driver
10520 11:20:39.577395 [ 0.027994] Trying to register duplicate clock ID: 134
10521 11:20:39.580817 [ 0.082256] KASLR enabled
10522 11:20:39.587184 [ 0.087142] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10523 11:20:39.593564 [ 0.087146] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10524 11:20:39.601027 [ 0.087151] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10525 11:20:39.606976 [ 0.087153] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10526 11:20:39.614156 [ 0.087156] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10527 11:20:39.620308 [ 0.087158] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10528 11:20:39.626994 [ 0.087161] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10529 11:20:39.633574 [ 0.087163] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10530 11:20:39.636984 [ 0.088154] ACPI: Interpreter disabled.
10531 11:20:39.639808 [ 0.090480] iommu: Default domain type: Translated
10532 11:20:39.646589 [ 0.090483] iommu: DMA domain TLB invalidation policy: strict mode
10533 11:20:39.649879 [ 0.090661] SCSI subsystem initialized
10534 11:20:39.656410 [ 0.090852] usbcore: registered new interface driver usbfs
10535 11:20:39.659550 [ 0.090869] usbcore: registered new interface driver hub
10536 11:20:39.666052 [ 0.090883] usbcore: registered new device driver usb
10537 11:20:39.669522 [ 0.091699] pps_core: LinuxPPS API ver. 1 registered
10538 11:20:39.679241 [ 0.091702] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10539 11:20:39.683660 [ 0.091708] PTP clock support registered
10540 11:20:39.686301 [ 0.091792] EDAC MC: Ver: 3.0.0
10541 11:20:39.690072 [ 0.093560] FPGA manager framework
10542 11:20:39.695956 [ 0.093601] Advanced Linux Sound Architecture Driver Initialized.
10543 11:20:39.699978 [ 0.094045] vgaarb: loaded
10544 11:20:39.706333 [ 0.094259] clocksource: Switched to clocksource arch_sys_counter
10545 11:20:39.709732 [ 0.094387] VFS: Disk quotas dquot_6.6.0
10546 11:20:39.716407 [ 0.094415] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10547 11:20:39.719563 [ 0.094536] pnp: PnP ACPI: disabled
10548 11:20:39.726234 [ 0.097309] NET: Registered PF_INET protocol family
10549 11:20:39.732601 [ 0.097776] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10550 11:20:39.742555 [ 0.102385] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10551 11:20:39.749101 [ 0.102461] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10552 11:20:39.755474 [ 0.102476] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10553 11:20:39.765339 [ 0.103047] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10554 11:20:39.771932 [ 0.105181] TCP: Hash tables configured (established 65536 bind 65536)
10555 11:20:39.778601 [ 0.105289] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10556 11:20:39.785711 [ 0.105482] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10557 11:20:39.788737 [ 0.105744] NET: Registered PF_UNIX/PF_LOCAL protocol family
10558 11:20:39.795128 [ 0.105951] RPC: Registered named UNIX socket transport module.
10559 11:20:39.801817 [ 0.105954] RPC: Registered udp transport module.
10560 11:20:39.805292 [ 0.105956] RPC: Registered tcp transport module.
10561 11:20:39.811893 [ 0.105958] RPC: Registered tcp NFSv4.1 backchannel transport module.
10562 11:20:39.815078 [ 0.105969] PCI: CLS 0 bytes, default 64
10563 11:20:39.818299 [ 0.106206] Unpacking initramfs...
10564 11:20:39.828128 [ 0.114914] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10565 11:20:39.834640 [ 0.115148] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10566 11:20:39.838241 [ 0.115595] kvm [1]: IPA Size Limit: 40 bits
10567 11:20:39.844687 [ 0.115619] kvm [1]: GICv3: no GICV resource entry
10568 11:20:39.848416 [ 0.115624] kvm [1]: disabling GICv2 emulation
10569 11:20:39.854660 [ 0.115638] kvm [1]: GIC system register CPU interface enabled
10570 11:20:39.858351 [ 0.115731] kvm [1]: vgic interrupt IRQ18
10571 11:20:39.864603 [ 0.115835] kvm [1]: VHE mode initialized successfully
10572 11:20:39.867988 [ 0.116697] Initialise system trusted keyrings
10573 11:20:39.874570 [ 0.116796] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10574 11:20:39.881169 [ 0.120154] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10575 11:20:39.884364 [ 0.120469] NFS: Registering the id_resolver key type
10576 11:20:39.891050 [ 0.120488] Key type id_resolver registered
10577 11:20:39.894007 [ 0.120490] Key type id_legacy registered
10578 11:20:39.900817 [ 0.120527] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10579 11:20:39.907423 [ 0.120531] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10580 11:20:39.913923 [ 0.120613] 9p: Installing v9fs 9p2000 file system support
10581 11:20:39.917936 [ 0.153732] Key type asymmetric registered
10582 11:20:39.920344 [ 0.153738] Asymmetric key parser 'x509' registered
10583 11:20:39.930193 [ 0.153778] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10584 11:20:39.933469 [ 0.153782] io scheduler mq-deadline registered
10585 11:20:39.936836 [ 0.153787] io scheduler kyber registered
10586 11:20:39.940080 [ 0.166511] EINJ: ACPI disabled.
10587 11:20:39.950285 [ 0.188476] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10588 11:20:39.960053 [ 0.188615] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10589 11:20:39.966940 [ 0.198761] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10590 11:20:39.973552 [ 0.200107] printk: console [ttyS0] disabled
10591 11:20:39.980012 [ 0.220242] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10592 11:20:39.987375 [ 0.908502] Freeing initrd memory: 18164K
10593 11:20:39.989898 [ 0.910405] printk: console [ttyS0] enabled
10594 11:20:39.996936 [ 1.510786] SuperH (H)SCI(F) driver initialized
10595 11:20:40.000043 [ 1.515787] msm_serial: driver initialized
10596 11:20:40.012993 [ 1.524410] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10597 11:20:40.019732 [ 1.532697] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10598 11:20:40.030125 [ 1.540978] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10599 11:20:40.039454 [ 1.549346] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10600 11:20:40.046377 [ 1.557796] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10601 11:20:40.056109 [ 1.566253] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10602 11:20:40.062921 [ 1.574532] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10603 11:20:40.072838 [ 1.583070] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10604 11:20:40.079060 [ 1.591351] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10605 11:20:40.088366 [ 1.606229] loop: module loaded
10606 11:20:40.097213 [ 1.611882] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10607 11:20:40.119613 [ 1.634472] mtk-pmic-keys: Failed to locate of_node [id: -1]
10608 11:20:40.126078 [ 1.640765] megasas: 07.719.03.00-rc1
10609 11:20:40.135858 [ 1.649913] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10610 11:20:40.144196 [ 1.657642] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10611 11:20:40.150336 [ 1.662072] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10612 11:20:40.159682 [ 1.674618] tun: Universal TUN/TAP device driver, 1.6
10613 11:20:40.167400 [ 1.675340] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10614 11:20:40.171085 [ 1.680435] thunder_xcv, ver 1.0
10615 11:20:40.171516 [ 1.689082] thunder_bgx, ver 1.0
10616 11:20:40.174715 [ 1.692320] nicpf, ver 1.0
10617 11:20:40.183925 [ 1.696068] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10618 11:20:40.200956 [ 1.703284] hns3: Copyright (c) 2017 Huawei Corporation.
10619 11:20:40.201832 [ 1.708611] hclge is initializing
10620 11:20:40.202256 [ 1.711931] e1000: Intel(R) PRO/1000 Network Driver
10621 11:20:40.206396 [ 1.716800] e1000: Copyright (c) 1999-2006 Intel Corporation.
10622 11:20:40.206829 [ 1.722553] e1000e: Intel(R) PRO/1000 Network Driver
10623 11:20:40.217080 [ 1.727508] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10624 11:20:40.222300 [ 1.733433] igb: Intel(R) Gigabit Ethernet Network Driver
10625 11:20:40.225288 [ 1.738822] igb: Copyright (c) 2007-2014 Intel Corporation.
10626 11:20:40.231967 [ 1.744400] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10627 11:20:40.242609 [ 1.746200] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10628 11:20:40.248288 [ 1.750657] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10629 11:20:40.251709 [ 1.750954] sky2: driver version 1.30
10630 11:20:40.258319 [ 1.772061] VFIO - User Level meta-driver version: 0.3
10631 11:20:40.264984 [ 1.779948] usbcore: registered new interface driver usb-storage
10632 11:20:40.271813 [ 1.786132] usbcore: registered new device driver onboard-usb-hub
10633 11:20:40.280104 [ 1.794897] mt6397-rtc mt6359-rtc: registered as rtc0
10634 11:20:40.289694 [ 1.800101] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-05T11:20:40 UTC (1685964040)
10635 11:20:40.292699 [ 1.809398] i2c_dev: i2c /dev entries driver
10636 11:20:40.308525 [ 1.820801] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10637 11:20:40.315473 [ 1.830728] sdhci: Secure Digital Host Controller Interface driver
10638 11:20:40.321890 [ 1.836906] sdhci: Copyright(c) Pierre Ossman
10639 11:20:40.328944 [ 1.842074] Synopsys Designware Multimedia Card Interface Driver
10640 11:20:40.332175 [ 1.848535] mmc0: CQHCI version 5.10
10641 11:20:40.338739 [ 1.848971] sdhci-pltfm: SDHCI platform and OF driver helper
10642 11:20:40.345153 [ 1.859882] ledtrig-cpu: registered to indicate activity on CPUs
10643 11:20:40.351907 [ 1.866971] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10644 11:20:40.358640 [ 1.874098] usbcore: registered new interface driver usbhid
10645 11:20:40.362523 [ 1.879666] usbhid: USB HID core driver
10646 11:20:40.368664 [ 1.883657] spi_master spi0: will run message pump with realtime priority
10647 11:20:40.416985 [ 1.925401] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10648 11:20:40.432639 [ 1.941143] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10649 11:20:40.439588 [ 1.954546] mmc0: Command Queue Engine enabled
10650 11:20:40.446234 [ 1.957432] cros-ec-spi spi0.0: Chrome EC device registered
10651 11:20:40.449971 [ 1.959020] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10652 11:20:40.456647 [ 1.971772] mmcblk0: mmc0:0001 DA4128 116 GiB
10653 11:20:40.469182 [ 1.981150] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10654 11:20:40.476201 [ 1.985253] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10655 11:20:40.479301 [ 1.992342] NET: Registered PF_PACKET protocol family
10656 11:20:40.485826 [ 1.998003] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10657 11:20:40.489169 [ 2.001048] 9pnet: Installing 9P2000 support
10658 11:20:40.495533 [ 2.006870] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10659 11:20:40.498975 [ 2.010180] Key type dns_resolver registered
10660 11:20:40.506058 [ 2.015882] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10661 11:20:40.509158 [ 2.019989] registered taskstats version 1
10662 11:20:40.515417 [ 2.029760] Loading compiled-in X.509 certificates
10663 11:20:40.548224 [ 2.056827] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10664 11:20:40.558154 [ 2.067245] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10665 11:20:40.568173 [ 2.079593] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10666 11:20:40.579492 [ 2.093974] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10667 11:20:40.585531 [ 2.100424] xhci-mtk 11200000.usb: xHCI Host Controller
10668 11:20:40.592103 [ 2.105658] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10669 11:20:40.602775 [ 2.113246] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10670 11:20:40.608814 [ 2.122419] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10671 11:20:40.612188 [ 2.128238] xhci-mtk 11200000.usb: xHCI Host Controller
10672 11:20:40.622307 [ 2.133459] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10673 11:20:40.628500 [ 2.140849] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10674 11:20:40.631801 [ 2.148296] hub 1-0:1.0: USB hub found
10675 11:20:40.635068 [ 2.152057] hub 1-0:1.0: 1 port detected
10676 11:20:40.645286 [ 2.156133] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10677 11:20:40.648620 [ 2.164493] hub 2-0:1.0: USB hub found
10678 11:20:40.651820 [ 2.168249] hub 2-0:1.0: 1 port detected
10679 11:20:40.660227 [ 2.175357] mtk-msdc 11f70000.mmc: Got CD GPIO
10680 11:20:40.677443 [ 2.189241] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10681 11:20:40.684296 [ 2.197020] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10682 11:20:40.694150 [ 2.204758] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10683 11:20:40.700916 [ 2.214167] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10684 11:20:40.711063 [ 2.221987] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10685 11:20:40.717375 [ 2.229748] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10686 11:20:40.724080 [ 2.237405] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10687 11:20:40.733792 [ 2.244966] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10688 11:20:40.740916 [ 2.252526] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10689 11:20:40.751345 [ 2.262919] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10690 11:20:40.758185 [ 2.271026] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10691 11:20:40.768372 [ 2.279109] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10692 11:20:40.774688 [ 2.287191] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10693 11:20:40.785116 [ 2.295273] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10694 11:20:40.791118 [ 2.303357] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10695 11:20:40.801779 [ 2.311444] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10696 11:20:40.807892 [ 2.319527] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10697 11:20:40.814734 [ 2.327609] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10698 11:20:40.824382 [ 2.335691] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10699 11:20:40.831033 [ 2.343773] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10700 11:20:40.841772 [ 2.351854] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10701 11:20:40.847398 [ 2.359936] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10702 11:20:40.857474 [ 2.368019] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10703 11:20:40.864122 [ 2.376106] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10704 11:20:40.870649 [ 2.384813] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10705 11:20:40.877340 [ 2.391999] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10706 11:20:40.883718 [ 2.398789] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10707 11:20:40.890348 [ 2.405641] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10708 11:20:40.897813 [ 2.412672] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10709 11:20:40.907820 [ 2.419315] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10710 11:20:40.917511 [ 2.428195] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10711 11:20:40.927798 [ 2.437061] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10712 11:20:40.934323 [ 2.446103] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10713 11:20:40.944234 [ 2.455316] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10714 11:20:40.953617 [ 2.464531] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10715 11:20:40.963839 [ 2.473396] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10716 11:20:40.970025 [ 2.482609] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10717 11:20:40.980337 [ 2.491475] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10718 11:20:40.990488 [ 2.500516] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10719 11:20:41.000147 [ 2.510420] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10720 11:20:41.009857 [ 2.521562] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10721 11:20:41.016450 [ 2.531115] Trying to probe devices needed for running init ...
10722 11:20:41.039880 [ 2.554714] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10723 11:20:41.069742 [ 2.584883] hub 2-1:1.0: USB hub found
10724 11:20:41.073023 [ 2.589034] hub 2-1:1.0: 3 ports detected
10725 11:20:41.191134 [ 2.706504] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10726 11:20:41.347281 [ 2.862458] hub 1-1:1.0: USB hub found
10727 11:20:41.350195 [ 2.866543] hub 1-1:1.0: 4 ports detected
10728 11:20:41.670581 [ 3.182385] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
10729 11:20:41.801180 [ 3.316404] hub 1-1.1:1.0: USB hub found
10730 11:20:41.804438 [ 3.320425] hub 1-1.1:1.0: 4 ports detected
10731 11:20:41.918453 [ 3.430298] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk
10732 11:20:42.051694 [ 3.566640] hub 1-1.4:1.0: USB hub found
10733 11:20:42.054892 [ 3.571027] hub 1-1.4:1.0: 2 ports detected
10734 11:20:42.130815 [ 3.642524] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
10735 11:20:42.314306 [ 3.826522] usb 1-1.1.4: new full-speed USB device number 6 using xhci-mtk
10736 11:20:42.399417 [ 3.914735] usb 1-1.1.4: device descriptor read/64, error -32
10737 11:20:42.591501 [ 4.106732] usb 1-1.1.4: device descriptor read/64, error -32
10738 11:20:42.786311 [ 4.298524] usb 1-1.4.1: new high-speed USB device number 7 using xhci-mtk
10739 11:20:42.974039 [ 4.486524] usb 1-1.1.4: new full-speed USB device number 8 using xhci-mtk
10740 11:20:43.059237 [ 4.574624] usb 1-1.1.4: device descriptor read/64, error -32
10741 11:20:43.251766 [ 4.766748] usb 1-1.1.4: device descriptor read/64, error -32
10742 11:20:43.363994 [ 4.879095] usb 1-1.1-port4: attempt power cycle
10743 11:20:43.451130 [ 4.962523] usb 1-1.4.2: new high-speed USB device number 9 using xhci-mtk
10744 11:20:43.974878 [ 5.486524] usb 1-1.1.4: new full-speed USB device number 10 using xhci-mtk
10745 11:20:43.977934 [ 5.493713] usb 1-1.1.4: Device not responding to setup address.
10746 11:20:44.191461 [ 5.706789] usb 1-1.1.4: Device not responding to setup address.
10747 11:20:44.403153 [ 5.918541] usb 1-1.1.4: device not accepting address 10, error -71
10748 11:20:44.490368 [ 6.002523] usb 1-1.1.4: new full-speed USB device number 11 using xhci-mtk
10749 11:20:44.493356 [ 6.009711] usb 1-1.1.4: Device not responding to setup address.
10750 11:20:44.707284 [ 6.222783] usb 1-1.1.4: Device not responding to setup address.
10751 11:20:44.918867 [ 6.434413] usb 1-1.1.4: device not accepting address 11, error -71
10752 11:20:44.925939 [ 6.441222] usb 1-1.1-port4: unable to enumerate USB device
10753 11:20:53.303775 [ 14.823073] ALSA device list:
10754 11:20:53.307083 [ 14.826048] No soundcards found.
10755 11:20:53.321908 [ 14.838216] Freeing unused kernel memory: 8384K
10756 11:20:53.325383 [ 14.842888] Run /init as init process
10757 11:20:53.336375 Loading, please wait...
10758 11:20:53.364967 Starting systemd-udevd version 252.6-1
10759 11:20:53.797911 [ 15.310451] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10760 11:20:53.804126 [ 15.317853] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10761 11:20:53.813997 [ 15.326366] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10762 11:20:53.825299 [ 15.337903] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10763 11:20:53.831671 [ 15.339398] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10764 11:20:53.838242 [ 15.341314] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10765 11:20:53.848403 [ 15.341331] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10766 11:20:53.854423 [ 15.341340] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10767 11:20:53.861180 [ 15.341412] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10768 11:20:53.871065 [ 15.341422] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10769 11:20:53.877838 [ 15.341429] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10770 11:20:53.888332 [ 15.341439] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10771 11:20:53.894934 [ 15.341449] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10772 11:20:53.900995 [ 15.341487] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10773 11:20:53.911368 [ 15.341522] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10774 11:20:53.917342 [ 15.341531] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10775 11:20:53.924037 [ 15.341538] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10776 11:20:53.933699 [ 15.341615] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10777 11:20:53.941159 [ 15.341624] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10778 11:20:53.950748 [ 15.341633] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10779 11:20:53.957093 [ 15.341647] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10780 11:20:53.963995 [ 15.341659] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10781 11:20:53.974314 [ 15.341749] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10782 11:20:53.980498 [ 15.346006] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10783 11:20:53.983790 [ 15.348214] remoteproc remoteproc0: scp is available
10784 11:20:53.994783 [ 15.348743] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10785 11:20:53.997599 [ 15.348752] remoteproc remoteproc0: powering up scp
10786 11:20:54.007872 [ 15.348778] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10787 11:20:54.014523 [ 15.348782] remoteproc remoteproc0: request_firmware failed: -2
10788 11:20:54.017880 [ 15.365021] mc: Linux media interface: v0.10
10789 11:20:54.027291 [ 15.368369] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10790 11:20:54.030948 [ 15.408801] usbcore: registered new interface driver r8152
10791 11:20:54.040788 [ 15.433411] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10792 11:20:54.044389 [ 15.433411] Fallback method does not support PEC.
10793 11:20:54.050389 [ 15.437292] videodev: Linux video capture interface: v2.00
10794 11:20:54.056974 [ 15.463874] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10795 11:20:54.064111 [ 15.485596] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10796 11:20:54.070407 [ 15.485992] pci_bus 0000:00: root bus resource [bus 00-ff]
10797 11:20:54.077499 [ 15.514538] usb 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
10798 11:20:54.083847 [ 15.515344] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10799 11:20:54.093514 [ 15.521082] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10800 11:20:54.103609 [ 15.530258] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10801 11:20:54.110054 [ 15.534807] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10802 11:20:54.119780 [ 15.555076] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10803 11:20:54.126208 [ 15.566077] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10804 11:20:54.136507 [ 15.571763] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10805 11:20:54.142976 [ 15.577720] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10806 11:20:54.149662 [ 15.614739] usbcore: registered new interface driver cdc_ether
10807 11:20:54.152717 [ 15.623924] pci 0000:00:00.0: supports D1 D2
10808 11:20:54.156410 [ 15.624666] Bluetooth: Core ver 2.22
10809 11:20:54.163151 [ 15.624759] NET: Registered PF_BLUETOOTH protocol family
10810 11:20:54.169371 [ 15.624764] Bluetooth: HCI device and connection manager initialized
10811 11:20:54.173077 [ 15.624798] Bluetooth: HCI socket layer initialized
10812 11:20:54.179034 [ 15.624809] Bluetooth: L2CAP socket layer initialized
10813 11:20:54.182399 [ 15.624851] Bluetooth: SCO socket layer initialized
10814 11:20:54.192162 [ 15.629452] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10815 11:20:54.199148 [ 15.629461] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10816 11:20:54.205986 [ 15.643267] usbcore: registered new interface driver r8153_ecm
10817 11:20:54.212906 [ 15.648716] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10818 11:20:54.218933 [ 15.649717] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10819 11:20:54.232235 [ 15.650894] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10820 11:20:54.238755 [ 15.651027] usbcore: registered new interface driver uvcvideo
10821 11:20:54.245581 [ 15.671981] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10822 11:20:54.248788 [ 15.675533] usbcore: registered new interface driver btusb
10823 11:20:54.258631 [ 15.676535] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10824 11:20:54.265248 [ 15.676546] Bluetooth: hci0: Failed to load firmware file (-2)
10825 11:20:54.271753 [ 15.676550] Bluetooth: hci0: Failed to set up firmware (-2)
10826 11:20:54.281893 [ 15.676554] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10827 11:20:54.288593 [ 15.680062] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10828 11:20:54.294979 [ 15.698456] r8152 1-1.1.1:1.0 eth0: v1.12.13
10829 11:20:54.298090 [ 15.700085] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10830 11:20:54.305045 [ 15.714375] r8152 1-1.1.1:1.0 enxf4f5e850de0a: renamed from eth0
10831 11:20:54.311755 [ 15.721793] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10832 11:20:54.321658 [ 15.833949] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10833 11:20:54.328337 [ 15.841328] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10834 11:20:54.331464 [ 15.848691] pci 0000:01:00.0: supports D1 D2
10835 11:20:54.337761 [ 15.852969] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10836 11:20:54.358340 [ 15.874569] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10837 11:20:54.368402 [ 15.881234] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10838 11:20:54.374490 [ 15.889062] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10839 11:20:54.384801 [ 15.896807] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10840 11:20:54.391101 [ 15.904553] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10841 11:20:54.397641 [ 15.912306] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10842 11:20:54.404430 [ 15.920052] pci 0000:00:00.0: PCI bridge to [bus 01]
10843 11:20:54.411091 [ 15.925012] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10844 11:20:54.417443 [ 15.932917] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10845 11:20:54.423928 [ 15.939894] pcieport 0000:00:00.0: PME: Signaling with IRQ 283
10846 11:20:54.430898 [ 15.946151] pcieport 0000:00:00.0: AER: enabled with IRQ 283
10847 11:20:54.447364 [ 15.960500] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10848 11:20:54.465408 [ 15.981636] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10849 11:20:54.475553 [ 15.988313] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10850 11:20:54.481831 [ 15.996934] cfg80211: failed to load regulatory.db
10851 11:20:54.526346 [ 16.039489] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10852 11:20:54.530170 [ 16.046740] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10853 11:20:54.556744 [ 16.073167] mt7921e 0000:01:00.0: ASIC revision: 79610010
10854 11:20:54.664968 [ 16.174593] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10855 11:20:54.677123 Begin: Loading essential drivers ... done.
10856 11:20:54.679837 Begin: Running /scripts/init-premount ... done.
10857 11:20:54.686828 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10858 11:20:54.697038 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10859 11:20:54.699696 Device /sys/class/net/enxf4f5e850de0a found
10860 11:20:54.700164 done.
10861 11:20:54.725735 Begin: Waiting up to 180 secs for any network device to become available ... done.
10862 11:20:54.783253 [ 16.292814] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10863 11:20:54.789395 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
10864 11:20:54.902557 [ 16.412130] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10865 11:20:55.018139 [ 16.527951] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10866 11:20:55.134244 [ 16.643860] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10867 11:20:55.249898 [ 16.759839] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10868 11:20:55.365967 [ 16.875744] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10869 11:20:55.482125 [ 16.991699] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10870 11:20:55.597474 [ 17.107658] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10871 11:20:55.713682 [ 17.223698] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10872 11:20:55.821435 [ 17.337620] mt7921e 0000:01:00.0: hardware init failed
10873 11:20:55.853091 [ 17.369426] r8152 1-1.1.1:1.0 enxf4f5e850de0a: carrier on
10874 11:20:56.783601 IP-Config: no response after 2 secs - giving up
10875 11:20:56.821167 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
10876 11:20:56.824779 IP-Config: enxf4f5e850de0a complete (dhcp from 192.168.201.1):
10877 11:20:56.834626 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10878 11:20:56.840895 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10879 11:20:56.847374 host : mt8192-asurada-spherion-r0-cbg-9
10880 11:20:56.853336 domain : lava-rack
10881 11:20:56.856764 rootserver: 192.168.201.1 rootpath:
10882 11:20:56.856846 filename :
10883 11:20:56.889427 done.
10884 11:20:56.897642 Begin: Running /scripts/nfs-bottom ... done.
10885 11:20:56.918270 Begin: Running /scripts/init-bottom ... done.
10886 11:20:58.175731 [ 19.692346] NET: Registered PF_INET6 protocol family
10887 11:20:58.182772 [ 19.699025] Segment Routing with IPv6
10888 11:20:58.185220 [ 19.702757] In-situ OAM (IOAM) with IPv6
10889 11:20:58.360011 [ 19.850445] systemd[1]: systemd 252.6-1 running in system mode (+PAM +AUDIT +SELINUX +APPARMOR +IMA +SMACK +SECCOMP +GCRYPT -GNUTLS +OPENSSL +ACL +BLKID +CURL +ELFUTILS +FIDO2 +IDN2 -IDN +IPTC +KMOD +LIBCRYPTSETUP +LIBFDISK +PCRE2 -PWQUALITY +P11KIT +QRENCODE +TPM2 +BZIP2 +LZ4 +XZ +ZLIB +ZSTD -BPF_FRAMEWORK -XKBCOMMON +UTMP +SYSVINIT default-hierarchy=unified)
10890 11:20:58.366204 [ 19.882504] systemd[1]: Detected architecture arm64.
10891 11:20:58.374003
10892 11:20:58.377143 Welcome to [1mDebian GNU/Linux 12 (bookworm)[0m!
10893 11:20:58.377610
10894 11:20:58.402967 [ 19.919823] systemd[1]: Hostname set to <debian-bookworm-arm64>.
10895 11:20:59.089678 [ 20.603464] systemd[1]: Queued start job for default target graphical.target.
10896 11:20:59.114889 [ 20.628468] systemd[1]: Created slice system-getty.slice - Slice /system/getty.
10897 11:20:59.121350 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m - Slice /system/getty.
10898 11:20:59.142031 [ 20.655476] systemd[1]: Created slice system-modprobe.slice - Slice /system/modprobe.
10899 11:20:59.148306 [[0;32m OK [0m] Created slice [0;1;39msystem-modpr…lice[0m - Slice /system/modprobe.
10900 11:20:59.169723 [ 20.683318] systemd[1]: Created slice system-serial\x2dgetty.slice - Slice /system/serial-getty.
10901 11:20:59.179538 [[0;32m OK [0m] Created slice [0;1;39msystem-seria…[0m - Slice /system/serial-getty.
10902 11:20:59.197993 [ 20.711698] systemd[1]: Created slice user.slice - User and Session Slice.
10903 11:20:59.204535 [[0;32m OK [0m] Created slice [0;1;39muser.slice[0m - User and Session Slice.
10904 11:20:59.224336 [ 20.734778] systemd[1]: Started systemd-ask-password-console.path - Dispatch Password Requests to Console Directory Watch.
10905 11:20:59.231146 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo…quests to Console Directory Watch.
10906 11:20:59.252683 [ 20.763021] systemd[1]: Started systemd-ask-password-wall.path - Forward Password Requests to Wall Directory Watch.
10907 11:20:59.259672 [[0;32m OK [0m] Started [0;1;39msystemd-ask-passwo… Requests to Wall Directory Watch.
10908 11:20:59.287539 [ 20.790990] systemd[1]: proc-sys-fs-binfmt_misc.automount - Arbitrary Executable File Formats File System Automount Point was skipped because of an unmet condition check (ConditionPathExists=/proc/sys/fs/binfmt_misc).
10909 11:20:59.297281 [ 20.810492] systemd[1]: Reached target cryptsetup.target - Local Encrypted Volumes.
10910 11:20:59.304261 [[0;32m OK [0m] Reached target [0;1;39mcryptsetup.…get[0m - Local Encrypted Volumes.
10911 11:20:59.320871 [ 20.834561] systemd[1]: Reached target integritysetup.target - Local Integrity Protected Volumes.
10912 11:20:59.330757 [[0;32m OK [0m] Reached target [0;1;39mintegrityse…Local Integrity Protected Volumes.
10913 11:20:59.345685 [ 20.862637] systemd[1]: Reached target paths.target - Path Units.
10914 11:20:59.352737 [[0;32m OK [0m] Reached target [0;1;39mpaths.target[0m - Path Units.
10915 11:20:59.373046 [ 20.886611] systemd[1]: Reached target remote-fs.target - Remote File Systems.
10916 11:20:59.380158 [[0;32m OK [0m] Reached target [0;1;39mremote-fs.target[0m - Remote File Systems.
10917 11:20:59.393755 [ 20.910614] systemd[1]: Reached target slices.target - Slice Units.
10918 11:20:59.403699 [[0;32m OK [0m] Reached target [0;1;39mslices.target[0m - Slice Units.
10919 11:20:59.417769 [ 20.934878] systemd[1]: Reached target swap.target - Swaps.
10920 11:20:59.424467 [[0;32m OK [0m] Reached target [0;1;39mswap.target[0m - Swaps.
10921 11:20:59.445099 [ 20.958898] systemd[1]: Reached target veritysetup.target - Local Verity Protected Volumes.
10922 11:20:59.455031 [[0;32m OK [0m] Reached target [0;1;39mveritysetup… - Local Verity Protected Volumes.
10923 11:20:59.473281 [ 20.987112] systemd[1]: Listening on systemd-initctl.socket - initctl Compatibility Named Pipe.
10924 11:20:59.483136 [[0;32m OK [0m] Listening on [0;1;39msystemd-initc… initctl Compatibility Named Pipe.
10925 11:20:59.503076 [ 21.016270] systemd[1]: Listening on systemd-journald-audit.socket - Journal Audit Socket.
10926 11:20:59.512813 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…socket[0m - Journal Audit Socket.
10927 11:20:59.530837 [ 21.044537] systemd[1]: Listening on systemd-journald-dev-log.socket - Journal Socket (/dev/log).
10928 11:20:59.540749 [[0;32m OK [0m] Listening on [0;1;39msystemd-journ…t[0m - Journal Socket (/dev/log).
10929 11:20:59.558141 [ 21.071394] systemd[1]: Listening on systemd-journald.socket - Journal Socket.
10930 11:20:59.564156 [[0;32m OK [0m] Listening on [0;1;39msystemd-journald.socket[0m - Journal Socket.
10931 11:20:59.583042 [ 21.096051] systemd[1]: Listening on systemd-networkd.socket - Network Service Netlink Socket.
10932 11:20:59.592682 [[0;32m OK [0m] Listening on [0;1;39msystemd-netwo… - Network Service Netlink Socket.
10933 11:20:59.612438 [ 21.125765] systemd[1]: Listening on systemd-udevd-control.socket - udev Control Socket.
10934 11:20:59.618555 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd….socket[0m - udev Control Socket.
10935 11:20:59.637650 [ 21.151280] systemd[1]: Listening on systemd-udevd-kernel.socket - udev Kernel Socket.
10936 11:20:59.644687 [[0;32m OK [0m] Listening on [0;1;39msystemd-udevd…l.socket[0m - udev Kernel Socket.
10937 11:20:59.677435 [ 21.190956] systemd[1]: Mounting dev-hugepages.mount - Huge Pages File System...
10938 11:20:59.684046 Mounting [0;1;39mdev-hugepages.mount[0m - Huge Pages File System...
10939 11:20:59.703407 [ 21.217241] systemd[1]: Mounting dev-mqueue.mount - POSIX Message Queue File System...
10940 11:20:59.709990 Mounting [0;1;39mdev-mqueue.mount…POSIX Message Queue File System...
10941 11:20:59.732045 [ 21.245208] systemd[1]: Mounting sys-kernel-debug.mount - Kernel Debug File System...
10942 11:20:59.738122 Mounting [0;1;39msys-kernel-debug.…[0m - Kernel Debug File System...
10943 11:20:59.763680 [ 21.270768] systemd[1]: sys-kernel-tracing.mount - Kernel Trace File System was skipped because of an unmet condition check (ConditionPathExists=/sys/kernel/tracing).
10944 11:20:59.775297 [ 21.289109] systemd[1]: Starting kmod-static-nodes.service - Create List of Static Device Nodes...
10945 11:20:59.782268 Starting [0;1;39mkmod-static-nodes…ate List of Static Device Nodes...
10946 11:20:59.804225 [ 21.317547] systemd[1]: Starting modprobe@configfs.service - Load Kernel Module configfs...
10947 11:20:59.810319 Starting [0;1;39mmodprobe@configfs…m - Load Kernel Module configfs...
10948 11:20:59.831898 [ 21.345539] systemd[1]: Starting modprobe@dm_mod.service - Load Kernel Module dm_mod...
10949 11:20:59.838408 Starting [0;1;39mmodprobe@dm_mod.s…[0m - Load Kernel Module dm_mod...
10950 11:20:59.859969 [ 21.373881] systemd[1]: Starting modprobe@drm.service - Load Kernel Module drm...
10951 11:20:59.866409 Starting [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm...
10952 11:20:59.877333 [ 21.391171] device-mapper: ioctl: 4.47.0-ioctl (2022-07-28) initialised: dm-devel@redhat.com
10953 11:20:59.889867 [ 21.403234] systemd[1]: Starting modprobe@efi_pstore.service - Load Kernel Module efi_pstore...
10954 11:20:59.895693 Starting [0;1;39mmodprobe@efi_psto…- Load Kernel Module efi_pstore...
10955 11:20:59.919793 [ 21.433586] systemd[1]: Starting modprobe@fuse.service - Load Kernel Module fuse...
10956 11:20:59.926708 Starting [0;1;39mmodprobe@fuse.ser…e[0m - Load Kernel Module fuse...
10957 11:20:59.948167 [ 21.461881] systemd[1]: Starting modprobe@loop.service - Load Kernel Module loop...
10958 11:20:59.957756 Starting [0;1;39mmodprobe@loop.ser…e[0m - Load Kernel Module loop..[ 21.476001] fuse: init (API version 7.37)
10959 11:20:59.958199 .
10960 11:20:59.981934 [ 21.495638] systemd[1]: Starting systemd-journald.service - Journal Service...
10961 11:20:59.988982 Starting [0;1;39msystemd-journald.service[0m - Journal Service...
10962 11:21:00.012615 [ 21.526712] systemd[1]: Starting systemd-modules-load.service - Load Kernel Modules...
10963 11:21:00.019774 Starting [0;1;39msystemd-modules-l…rvice[0m - Load Kernel Modules...
10964 11:21:00.042849 [ 21.553657] systemd[1]: Starting systemd-network-generator.service - Generate network units from Kernel command line...
10965 11:21:00.049810 Starting [0;1;39msystemd-network-g… units from Kernel command line...
10966 11:21:00.072082 [ 21.585927] systemd[1]: Starting systemd-remount-fs.service - Remount Root and Kernel File Systems...
10967 11:21:00.082224 Starting [0;1;39msystemd-remount-f…nt Root and Kernel File Systems...
10968 11:21:00.105157 [ 21.618190] systemd[1]: Starting systemd-udev-trigger.service - Coldplug All udev Devices...
10969 11:21:00.111217 Starting [0;1;39msystemd-udev-trig…[0m - Coldplug All udev Devices...
10970 11:21:00.133835 [ 21.647242] systemd[1]: Mounted dev-hugepages.mount - Huge Pages File System.
10971 11:21:00.140059 [ 21.651294] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10972 11:21:00.150374 [[0;32m OK [0m] Mounted [0;1;39mdev-hugepages.mount[0m - Huge Pages File System.
10973 11:21:00.166350 [ 21.679288] systemd[1]: Mounted dev-mqueue.mount - POSIX Message Queue File System.
10974 11:21:00.172940 [ 21.686600] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10975 11:21:00.182572 [[0;32m OK [0m] Mounted [0;1;39mdev-mqueue.mount[…- POSIX Message Queue File System.
10976 11:21:00.201407 [ 21.715272] systemd[1]: Mounted sys-kernel-debug.mount - Kernel Debug File System.
10977 11:21:00.207883 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-debug.m…nt[0m - Kernel Debug File System.
10978 11:21:00.220278 [ 21.734289] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10979 11:21:00.230553 [ 21.743803] systemd[1]: Finished kmod-static-nodes.service - Create List of Static Device Nodes.
10980 11:21:00.237289 [[0;32m OK [0m] Finished [0;1;39mkmod-static-nodes…reate List of Static Device Nodes.
10981 11:21:00.251252 [ 21.765343] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10982 11:21:00.261369 [ 21.775171] systemd[1]: modprobe@configfs.service: Deactivated successfully.
10983 11:21:00.268354 [ 21.782753] systemd[1]: Finished modprobe@configfs.service - Load Kernel Module configfs.
10984 11:21:00.281681 [[0;32m OK [0m] Finished [0;1;39mmodprobe@c[ 21.794106] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10985 11:21:00.285058 onfigfs…[0m - Load Kernel Module configfs.
10986 11:21:00.306854 [ 21.819625] systemd[1]: modprobe@dm_mod.service: Deactivated successfully.
10987 11:21:00.313007 [ 21.827014] systemd[1]: Finished modprobe@dm_mod.service - Load Kernel Module dm_mod.
10988 11:21:00.320127 [ 21.829749] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10989 11:21:00.329975 [[0;32m OK [0m] Finished [0;1;39mmodprobe@dm_mod.s…e[0m - Load Kernel Module dm_mod.
10990 11:21:00.347418 [ 21.863861] systemd[1]: modprobe@drm.service: Deactivated successfully.
10991 11:21:00.357293 [ 21.869070] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10992 11:21:00.364064 [ 21.870894] systemd[1]: Finished modprobe@drm.service - Load Kernel Module drm.
10993 11:21:00.373701 [[0;32m OK [0m] Finished [0;1;39mmodprobe@drm.service[0m - Load Kernel Module drm.
10994 11:21:00.390228 [ 21.903954] systemd[1]: modprobe@efi_pstore.service: Deactivated successfully.
10995 11:21:00.396840 [ 21.904587] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10996 11:21:00.407029 [ 21.911606] systemd[1]: Finished modprobe@efi_pstore.service - Load Kernel Module efi_pstore.
10997 11:21:00.413314 [[0;32m OK [0m] Finished [0;1;39mmodprobe@efi_psto…m - Load Kernel Module efi_pstore.
10998 11:21:00.431738 [ 21.945164] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10999 11:21:00.441217 [ 21.955105] systemd[1]: modprobe@fuse.service: Deactivated successfully.
11000 11:21:00.448402 [ 21.962215] systemd[1]: Finished modprobe@fuse.service - Load Kernel Module fuse.
11001 11:21:00.454961 [[0;32m OK [0m] Finished [0;1;39mmodprobe@fuse.service[0m - Load Kernel Module fuse.
11002 11:21:00.466093 [ 21.979496] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
11003 11:21:00.472330 [ 21.989145] systemd[1]: modprobe@loop.service: Deactivated successfully.
11004 11:21:00.482303 [ 21.996231] systemd[1]: Finished modprobe@loop.service - Load Kernel Module loop.
11005 11:21:00.489185 [[0;32m OK [0m] Finished [0;1;39mmodprobe@loop.service[0m - Load Kernel Module loop.
11006 11:21:00.510424 [ 22.023829] systemd[1]: Finished systemd-modules-load.service - Load Kernel Modules.
11007 11:21:00.518042 [[0;32m OK [0m] Finished [0;1;39msystemd-modules-l…service[0m - Load Kernel Modules.
11008 11:21:00.537925 [ 22.051223] systemd[1]: Started systemd-journald.service - Journal Service.
11009 11:21:00.544148 [[0;32m OK [0m] Started [0;1;39msystemd-journald.service[0m - Journal Service.
11010 11:21:00.563467 [[0;32m OK [0m] Finished [0;1;39msystemd-network-g…rk units from Kernel command line.
11011 11:21:00.586316 [[0;32m OK [0m] Finished [0;1;39msystemd-remount-f…ount Root and Kernel File Systems.
11012 11:21:00.606600 [[0;32m OK [0m] Reached target [0;1;39mnetwork-pre…get[0m - Preparation for Network.
11013 11:21:00.646061 Mounting [0;1;39msys-fs-fuse-conne…[0m - FUSE Control File System...
11014 11:21:00.668087 Mounting [0;1;39msys-kernel-config…ernel Configuration File System...
11015 11:21:00.687706 Starting [0;1;39msystemd-journal-f…h Journal to Persistent Storage...
11016 11:21:00.711703 [ 22.219016] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
11017 11:21:00.718369 [ 22.234455] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
11018 11:21:00.728352 Starting [0;1;39msystemd-random-se…ice[0m - Load/Save Random Seed...
11019 11:21:00.758820 [ 22.272428] systemd-journald[299]: Received client request to flush runtime journal.
11020 11:21:00.772967 Starting [0;1;39msystemd-sysctl.se…ce[0m - Apply Kernel Variables...
11021 11:21:00.798323 Starting [0;1;39msystemd-sysusers.…rvice[0m - Create System Users...
11022 11:21:01.066455 [[0;32m OK [0m] Finished [0;1;39msystemd-udev-trig…e[0m - Coldplug All udev Devices.
11023 11:21:01.084785 [[0;32m OK [0m] Mounted [0;1;39msys-fs-fuse-connec…nt[0m - FUSE Control File System.
11024 11:21:01.104524 [[0;32m OK [0m] Mounted [0;1;39msys-kernel-config.… Kernel Configuration File System.
11025 11:21:01.120708 [[0;32m OK [0m] Finished [0;1;39msystemd-random-se…rvice[0m - Load/Save Random Seed.
11026 11:21:01.847814 [[0;32m OK [0m] Finished [0;1;39msystemd-sysctl.service[0m - Apply Kernel Variables.
11027 11:21:02.140487 [[0;32m OK [0m] Finished [0;1;39msystemd-journal-f…ush Journal to Persistent Storage.
11028 11:21:02.158392 [[0;32m OK [0m] Finished [0;1;39msystemd-sysusers.service[0m - Create System Users.
11029 11:21:02.205085 Starting [0;1;39msystemd-tmpfiles-…ate Static Device Nodes in /dev...
11030 11:21:02.297735 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…reate Static Device Nodes in /dev.
11031 11:21:02.317143 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs-pr…reparation for Local File Systems.
11032 11:21:02.333059 [[0;32m OK [0m] Reached target [0;1;39mlocal-fs.target[0m - Local File Systems.
11033 11:21:02.381303 Starting [0;1;39msystemd-binfmt.se…et Up Additional Binary Formats...
11034 11:21:02.405142 Starting [0;1;39msystemd-tmpfiles-… Volatile Files and Directories...
11035 11:21:02.424333 Starting [0;1;39msystemd-udevd.ser…ger for Device Events and Files...
11036 11:21:02.448932 [[0;1;31mFAILED[0m] Failed to start [0;1;39msystemd-bi… Set Up Additional Binary Formats.
11037 11:21:02.461209 See 'systemctl status systemd-binfmt.service' for details.
11038 11:21:02.660949 [[0;32m OK [0m] Started [0;1;39msystemd-udevd.serv…nager for Device Events and Files.
11039 11:21:02.714164 Starting [0;1;39msystemd-networkd.…ice[0m - Network Configuration...
11040 11:21:02.775740 [[0;32m OK [0m] Finished [0;1;39msystemd-tmpfiles-…te Volatile Files and Directories.
11041 11:21:02.812293 [[0;32m OK [0m] Found device [0;1;39mdev-ttyS0.device[0m - /dev/ttyS0.
11042 11:21:02.909755 Starting [0;1;39msystemd-timesyncd… - Network Time Synchronization...
11043 11:21:02.939036 Starting [0;1;39msystemd-update-ut…rd System Boot/Shutdown in UTMP...
11044 11:21:03.126570 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut…cord System Boot/Shutdown in UTMP.
11045 11:21:03.176392 [[0;32m OK [0m] Created slice [0;1;39msystem-syste…- Slice /system/systemd-backlight.
11046 11:21:03.192215 [[0;32m OK [0m] Reached target [0;1;39mbluetooth.target[0m - Bluetooth Support.
11047 11:21:03.242487 Starting [0;1;39msystemd-backlight…ess of leds:white:kbd_backlight...
11048 11:21:03.256055 [ 24.773436] remoteproc remoteproc0: powering up scp
11049 11:21:03.274898 [ 24.788902] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
11050 11:21:03.282184 [ 24.800014] remoteproc remoteproc0: request_firmware failed: -2
11051 11:21:03.294500 [ 24.809121] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
11052 11:21:03.301100 [[0;32m OK [0m] Listening on [0;1;39msystemd-rfkil…l Switch Status /dev/rfkill Watch.
11053 11:21:03.321944 [[0;32m OK [0m] Started [0;1;39msystemd-networkd.service[0m - Network Configuration.
11054 11:21:03.341990 [[0;32m OK [0m] Started [0;1;39msystemd-timesyncd.…0m - Network Time Synchronization.
11055 11:21:03.361834 [[0;32m OK [0m] Finished [0;1;39msystemd-backlight…tness of leds:white:kbd_backlight.
11056 11:21:03.382543 [[0;32m OK [0m] Reached target [0;1;39mnetwork.target[0m - Network.
11057 11:21:03.400366 [[0;32m OK [0m] Reached target [0;1;39msysinit.target[0m - System Initialization.
11058 11:21:03.417038 [[0;32m OK [0m] Started [0;1;39msystemd-tmpfiles-c… Cleanup of Temporary Directories.
11059 11:21:03.432481 [[0;32m OK [0m] Reached target [0;1;39mtime-set.target[0m - System Time Set.
11060 11:21:03.458408 [[0;32m OK [0m] Started [0;1;39mapt-daily.timer[0m - Daily apt download activities.
11061 11:21:03.484496 [[0;32m OK [0m] Started [0;1;39mapt-daily-upgrade.… apt upgrade and clean activities.
11062 11:21:03.504625 [[0;32m OK [0m] Started [0;1;39mdpkg-db-backup.tim… Daily dpkg database backup timer.
11063 11:21:03.527918 [[0;32m OK [0m] Started [0;1;39me2scrub_all.timer…etadata Check for All Filesystems.
11064 11:21:03.552665 [[0;32m OK [0m] Started [0;1;39mfstrim.timer[0m - Discard unused blocks once a week.
11065 11:21:03.568727 [[0;32m OK [0m] Reached target [0;1;39mtimers.target[0m - Timer Units.
11066 11:21:03.587707 [[0;32m OK [0m] Listening on [0;1;39mdbus.socket[…- D-Bus System Message Bus Socket.
11067 11:21:03.604593 [[0;32m OK [0m] Reached target [0;1;39msockets.target[0m - Socket Units.
11068 11:21:03.620939 [[0;32m OK [0m] Reached target [0;1;39mbasic.target[0m - Basic System.
11069 11:21:03.658452 Starting [0;1;39mdbus.service[0m - D-Bus System Message Bus...
11070 11:21:03.690742 Starting [0;1;39me2scrub_reap.serv…e ext4 Metadata Check Snapshots...
11071 11:21:03.781297 Starting [0;1;39msystemd-logind.se…ice[0m - User Login Management...
11072 11:21:03.804439 Starting [0;1;39msystemd-rfkill.se…Load/Save RF Kill Switch Status...
11073 11:21:03.824910 Starting [0;1;39msystemd-user-sess…vice[0m - Permit User Sessions...
11074 11:21:03.988201 [[0;32m OK [0m] Finished [0;1;39msystemd-user-sess…ervice[0m - Permit User Sessions.
11075 11:21:04.032330 [[0;32m OK [0m] Started [0;1;39mgetty@tty1.service[0m - Getty on tty1.
11076 11:21:04.057556 [[0;32m OK [0m] Started [0;1;39mserial-getty@ttyS0…rvice[0m - Serial Getty on ttyS0.
11077 11:21:04.080532 [[0;32m OK [0m] Reached target [0;1;39mgetty.target[0m - Login Prompts.
11078 11:21:04.101400 [[0;32m OK [0m] Started [0;1;39msystemd-rfkill.ser…- Load/Save RF Kill Switch Status.
11079 11:21:04.121418 [[0;32m OK [0m] Started [0;1;39mdbus.service[0m - D-Bus System Message Bus.
11080 11:21:04.148561 [[0;32m OK [0m] Finished [0;1;39me2scrub_reap.serv…ine ext4 Metadata Check Snapshots.
11081 11:21:04.173787 [[0;32m OK [0m] Started [0;1;39msystemd-logind.service[0m - User Login Management.
11082 11:21:04.204875 [[0;32m OK [0m] Reached target [0;1;39mmulti-user.target[0m - Multi-User System.
11083 11:21:04.228622 [[0;32m OK [0m] Reached target [0;1;39mgraphical.target[0m - Graphical Interface.
11084 11:21:04.278886 Starting [0;1;39msystemd-hostnamed.service[0m - Hostname Service...
11085 11:21:04.298062 Starting [0;1;39msystemd-update-ut… Record Runlevel Change in UTMP...
11086 11:21:04.363597 [[0;32m OK [0m] Finished [0;1;39msystemd-update-ut… - Record Runlevel Change in UTMP.
11087 11:21:04.422289 [[0;32m OK [0m] Started [0;1;39msystemd-hostnamed.service[0m - Hostname Service.
11088 11:21:04.492641
11089 11:21:04.493160
11090 11:21:04.496184 Debian GNU/Linux 12 debian-bookworm-arm64 ttyS0
11091 11:21:04.496649
11092 11:21:04.499199 debian-bookworm-arm64 login: root (automatic login)
11093 11:21:04.499725
11094 11:21:04.500141
11095 11:21:04.747995 Linux debian-bookworm-arm64 6.1.31 #1 SMP PREEMPT Mon Jun 5 10:57:14 UTC 2023 aarch64
11096 11:21:04.748747
11097 11:21:04.753875 The programs included with the Debian GNU/Linux system are free software;
11098 11:21:04.760779 the exact distribution terms for each program are described in the
11099 11:21:04.763926 individual files in /usr/share/doc/*/copyright.
11100 11:21:04.764505
11101 11:21:04.770845 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11102 11:21:04.773655 permitted by applicable law.
11103 11:21:05.727251 Matched prompt #10: / #
11105 11:21:05.727535 Setting prompt string to ['/ #']
11106 11:21:05.727628 end: 2.2.5.1 login-action (duration 00:00:27) [common]
11108 11:21:05.727815 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
11109 11:21:05.727917 start: 2.2.6 expect-shell-connection (timeout 00:03:36) [common]
11110 11:21:05.727989 Setting prompt string to ['/ #']
11111 11:21:05.728051 Forcing a shell prompt, looking for ['/ #']
11113 11:21:05.778453 / #
11114 11:21:05.778896 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11115 11:21:05.779185 Waiting using forced prompt support (timeout 00:02:30)
11116 11:21:05.784371
11117 11:21:05.785191 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11118 11:21:05.785606 start: 2.2.7 export-device-env (timeout 00:03:36) [common]
11120 11:21:05.886786 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10591284/extract-nfsrootfs-85gyi42f'
11121 11:21:05.892254 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10591284/extract-nfsrootfs-85gyi42f'
11123 11:21:05.993167 / # export NFS_SERVER_IP='192.168.201.1'
11124 11:21:05.999723 export NFS_SERVER_IP='192.168.201.1'
11125 11:21:06.000775 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11126 11:21:06.001330 end: 2.2 depthcharge-retry (duration 00:01:24) [common]
11127 11:21:06.001839 end: 2 depthcharge-action (duration 00:01:24) [common]
11128 11:21:06.002344 start: 3 lava-test-retry (timeout 00:07:57) [common]
11129 11:21:06.002828 start: 3.1 lava-test-shell (timeout 00:07:57) [common]
11130 11:21:06.003244 Using namespace: common
11132 11:21:06.104624 / # #
11133 11:21:06.105447 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11134 11:21:06.111468 #
11135 11:21:06.112358 Using /lava-10591284
11137 11:21:06.213665 / # export SHELL=/bin/bash
11138 11:21:06.220174 export SHELL=/bin/bash
11140 11:21:06.321975 / # . /lava-10591284/environment
11141 11:21:06.328667 . /lava-10591284/environment
11143 11:21:06.435541 / # /lava-10591284/bin/lava-test-runner /lava-10591284/0
11144 11:21:06.436277 Test shell timeout: 10s (minimum of the action and connection timeout)
11145 11:21:06.441938 /lava-10591284/bin/lava-test-runner /lava-10591284/0
11146 11:21:06.665993 + export TESTRUN_ID=0_timesync-off
11147 11:21:06.668806 + TESTRUN_ID=0_timesync-off
11148 11:21:06.672162 + cd /lava-10591284/0/tests/0_timesync-off
11149 11:21:06.675452 ++ cat uuid
11150 11:21:06.679690 + UUID=10591284_1.6.2.3.1
11151 11:21:06.679774 + set +x
11152 11:21:06.685710 <LAVA_SIGNAL_STARTRUN 0_timesync-off 10591284_1.6.2.3.1>
11153 11:21:06.685971 Received signal: <STARTRUN> 0_timesync-off 10591284_1.6.2.3.1
11154 11:21:06.686046 Starting test lava.0_timesync-off (10591284_1.6.2.3.1)
11155 11:21:06.686132 Skipping test definition patterns.
11156 11:21:06.688690 + systemctl stop systemd-timesyncd
11157 11:21:06.729060 + set +x
11158 11:21:06.732384 <LAVA_SIGNAL_ENDRUN 0_timesync-off 10591284_1.6.2.3.1>
11159 11:21:06.733109 Received signal: <ENDRUN> 0_timesync-off 10591284_1.6.2.3.1
11160 11:21:06.733536 Ending use of test pattern.
11161 11:21:06.733864 Ending test lava.0_timesync-off (10591284_1.6.2.3.1), duration 0.05
11163 11:21:06.801092 + export TESTRUN_ID=1_kselftest-alsa
11164 11:21:06.804473 + TESTRUN_ID=1_kselftest-alsa
11165 11:21:06.811008 + cd /lava-10591284/0/tests/1_kselftest-alsa
11166 11:21:06.811443 ++ cat uuid
11167 11:21:06.818222 + UUID=10591284_1.6.2.3.5
11168 11:21:06.818654 + set +x
11169 11:21:06.824649 <LAVA_SIGNAL_STARTRUN 1_kselftest-alsa 10591284_1.6.2.3.5>
11170 11:21:06.825333 Received signal: <STARTRUN> 1_kselftest-alsa 10591284_1.6.2.3.5
11171 11:21:06.825704 Starting test lava.1_kselftest-alsa (10591284_1.6.2.3.5)
11172 11:21:06.826095 Skipping test definition patterns.
11173 11:21:06.827769 + cd ./automated/linux/kselftest/
11174 11:21:06.853959 + ./kselftest.sh -c alsa -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11175 11:21:06.895788 INFO: install_deps skipped
11176 11:21:07.374204 --2023-06-05 11:21:07-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11177 11:21:07.381900 Resolving storage.kernelci.org (storage.kernelci.org)... 52.250.1.28
11178 11:21:07.529757 Connecting to storage.kernelci.org (storage.kernelci.org)|52.250.1.28|:80... connected.
11179 11:21:07.675833 HTTP request sent, awaiting response... 200 OK
11180 11:21:07.679281 Length: 2714204 (2.6M) [application/octet-stream]
11181 11:21:07.682332 Saving to: 'kselftest.tar.xz'
11182 11:21:07.682801
11183 11:21:07.683172
11184 11:21:07.970198 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11185 11:21:08.264074 kselftest.tar.xz 1%[ ] 47.81K 166KB/s
11186 11:21:08.742626 kselftest.tar.xz 8%[> ] 216.08K 375KB/s
11187 11:21:09.001447 kselftest.tar.xz 26%[====> ] 693.55K 662KB/s
11188 11:21:09.150904 kselftest.tar.xz 85%[================> ] 2.22M 1.71MB/s
11189 11:21:09.157276 kselftest.tar.xz 100%[===================>] 2.59M 1.79MB/s in 1.5s
11190 11:21:09.157886
11191 11:21:09.390722 2023-06-05 11:21:09 (1.79 MB/s) - 'kselftest.tar.xz' saved [2714204/2714204]
11192 11:21:09.390875
11193 11:21:14.178404 skiplist:
11194 11:21:14.182086 ========================================
11195 11:21:14.185382 ========================================
11196 11:21:14.226911 alsa:mixer-test
11197 11:21:14.246154 ============== Tests to run ===============
11198 11:21:14.246590 alsa:mixer-test
11199 11:21:14.249592 ===========End Tests to run ===============
11200 11:21:14.346890 [ 35.865484] kselftest: Running tests in alsa
11201 11:21:14.355398 TAP version 13
11202 11:21:14.370826 1..1
11203 11:21:14.385911 # selftests: alsa: mixer-test
11204 11:21:14.829557 # TAP version 13
11205 11:21:14.830281 # 1..0
11206 11:21:14.836278 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:0 error:0
11207 11:21:14.839443 ok 1 selftests: alsa: mixer-test
11208 11:21:15.487969 alsa_mixer-test pass
11209 11:21:15.520494 + ../../utils/send-to-lava.sh ./output/result.txt
11210 11:21:15.587411 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alsa_mixer-test RESULT=pass>
11211 11:21:15.587863 + set +x
11212 11:21:15.588469 Received signal: <TESTCASE> TEST_CASE_ID=alsa_mixer-test RESULT=pass
11214 11:21:15.594310 <LAVA_SIGNAL_ENDRUN 1_kselftest-alsa 10591284_1.6.2.3.5>
11215 11:21:15.594977 Received signal: <ENDRUN> 1_kselftest-alsa 10591284_1.6.2.3.5
11216 11:21:15.595348 Ending use of test pattern.
11217 11:21:15.595668 Ending test lava.1_kselftest-alsa (10591284_1.6.2.3.5), duration 8.77
11219 11:21:15.597236 <LAVA_TEST_RUNNER EXIT>
11220 11:21:15.597904 ok: lava_test_shell seems to have completed
11221 11:21:15.598394 alsa_mixer-test: pass
11222 11:21:15.598816 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11223 11:21:15.599359 end: 3 lava-test-retry (duration 00:00:10) [common]
11224 11:21:15.599868 start: 4 finalize (timeout 00:07:48) [common]
11225 11:21:15.600320 start: 4.1 power-off (timeout 00:00:30) [common]
11226 11:21:15.601108 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11227 11:21:15.684690 >> Command sent successfully.
11228 11:21:15.688946 Returned 0 in 0 seconds
11229 11:21:15.789858 end: 4.1 power-off (duration 00:00:00) [common]
11231 11:21:15.791399 start: 4.2 read-feedback (timeout 00:07:48) [common]
11232 11:21:15.792702 Listened to connection for namespace 'common' for up to 1s
11233 11:21:16.792838 Finalising connection for namespace 'common'
11234 11:21:16.793540 Disconnecting from shell: Finalise
11235 11:21:16.794043 / #
11236 11:21:16.895035 end: 4.2 read-feedback (duration 00:00:01) [common]
11237 11:21:16.895742 end: 4 finalize (duration 00:00:01) [common]
11238 11:21:16.896381 Cleaning after the job
11239 11:21:16.896936 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591284/tftp-deploy-n9bs2myb/ramdisk
11240 11:21:16.908132 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591284/tftp-deploy-n9bs2myb/kernel
11241 11:21:16.932024 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591284/tftp-deploy-n9bs2myb/dtb
11242 11:21:16.932477 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591284/tftp-deploy-n9bs2myb/nfsrootfs
11243 11:21:17.014844 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591284/tftp-deploy-n9bs2myb/modules
11244 11:21:17.020157 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10591284
11245 11:21:17.538405 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10591284
11246 11:21:17.538587 Job finished correctly