Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 0
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 0
1 11:15:38.970085 lava-dispatcher, installed at version: 2023.05.1
2 11:15:38.970303 start: 0 validate
3 11:15:38.970428 Start time: 2023-06-05 11:15:38.970421+00:00 (UTC)
4 11:15:38.970545 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:15:38.970667 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
6 11:15:39.265012 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:15:39.265819 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:15:39.561412 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:15:39.562139 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:15:39.860863 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:15:39.861750 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:15:40.155928 Using caching service: 'http://localhost/cache/?uri=%s'
13 11:15:40.156652 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 11:15:40.453669 validate duration: 1.48
16 11:15:40.454826 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:15:40.455309 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:15:40.455759 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:15:40.456343 Not decompressing ramdisk as can be used compressed.
20 11:15:40.456894 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/initrd.cpio.gz
21 11:15:40.457223 saving as /var/lib/lava/dispatcher/tmp/10591250/tftp-deploy-3xwj17rv/ramdisk/initrd.cpio.gz
22 11:15:40.457535 total size: 4665601 (4MB)
23 11:15:40.462326 progress 0% (0MB)
24 11:15:40.469972 progress 5% (0MB)
25 11:15:40.475680 progress 10% (0MB)
26 11:15:40.480030 progress 15% (0MB)
27 11:15:40.483456 progress 20% (0MB)
28 11:15:40.486206 progress 25% (1MB)
29 11:15:40.488911 progress 30% (1MB)
30 11:15:40.491108 progress 35% (1MB)
31 11:15:40.493325 progress 40% (1MB)
32 11:15:40.495537 progress 45% (2MB)
33 11:15:40.497444 progress 50% (2MB)
34 11:15:40.499290 progress 55% (2MB)
35 11:15:40.501012 progress 60% (2MB)
36 11:15:40.502688 progress 65% (2MB)
37 11:15:40.504333 progress 70% (3MB)
38 11:15:40.505816 progress 75% (3MB)
39 11:15:40.507288 progress 80% (3MB)
40 11:15:40.508961 progress 85% (3MB)
41 11:15:40.510283 progress 90% (4MB)
42 11:15:40.511615 progress 95% (4MB)
43 11:15:40.512962 progress 100% (4MB)
44 11:15:40.513126 4MB downloaded in 0.06s (80.03MB/s)
45 11:15:40.513284 end: 1.1.1 http-download (duration 00:00:00) [common]
47 11:15:40.513542 end: 1.1 download-retry (duration 00:00:00) [common]
48 11:15:40.513637 start: 1.2 download-retry (timeout 00:10:00) [common]
49 11:15:40.513743 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 11:15:40.513894 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 11:15:40.513966 saving as /var/lib/lava/dispatcher/tmp/10591250/tftp-deploy-3xwj17rv/kernel/Image
52 11:15:40.514026 total size: 45746688 (43MB)
53 11:15:40.514085 No compression specified
54 11:15:40.515156 progress 0% (0MB)
55 11:15:40.526372 progress 5% (2MB)
56 11:15:40.537961 progress 10% (4MB)
57 11:15:40.549406 progress 15% (6MB)
58 11:15:40.560678 progress 20% (8MB)
59 11:15:40.571885 progress 25% (10MB)
60 11:15:40.582916 progress 30% (13MB)
61 11:15:40.594162 progress 35% (15MB)
62 11:15:40.605476 progress 40% (17MB)
63 11:15:40.616695 progress 45% (19MB)
64 11:15:40.627823 progress 50% (21MB)
65 11:15:40.639113 progress 55% (24MB)
66 11:15:40.650492 progress 60% (26MB)
67 11:15:40.661769 progress 65% (28MB)
68 11:15:40.672973 progress 70% (30MB)
69 11:15:40.684672 progress 75% (32MB)
70 11:15:40.697289 progress 80% (34MB)
71 11:15:40.709690 progress 85% (37MB)
72 11:15:40.721004 progress 90% (39MB)
73 11:15:40.732133 progress 95% (41MB)
74 11:15:40.743689 progress 100% (43MB)
75 11:15:40.743824 43MB downloaded in 0.23s (189.86MB/s)
76 11:15:40.743976 end: 1.2.1 http-download (duration 00:00:00) [common]
78 11:15:40.744208 end: 1.2 download-retry (duration 00:00:00) [common]
79 11:15:40.744305 start: 1.3 download-retry (timeout 00:10:00) [common]
80 11:15:40.744393 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 11:15:40.744562 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 11:15:40.744647 saving as /var/lib/lava/dispatcher/tmp/10591250/tftp-deploy-3xwj17rv/dtb/mt8192-asurada-spherion-r0.dtb
83 11:15:40.744715 total size: 46924 (0MB)
84 11:15:40.744773 No compression specified
85 11:15:40.745915 progress 69% (0MB)
86 11:15:40.746201 progress 100% (0MB)
87 11:15:40.746358 0MB downloaded in 0.00s (27.27MB/s)
88 11:15:40.746476 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:15:40.746710 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:15:40.746793 start: 1.4 download-retry (timeout 00:10:00) [common]
92 11:15:40.746883 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 11:15:40.746997 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/full.rootfs.tar.xz
94 11:15:40.747064 saving as /var/lib/lava/dispatcher/tmp/10591250/tftp-deploy-3xwj17rv/nfsrootfs/full.rootfs.tar
95 11:15:40.747128 total size: 200770336 (191MB)
96 11:15:40.747188 Using unxz to decompress xz
97 11:15:40.750827 progress 0% (0MB)
98 11:15:41.274406 progress 5% (9MB)
99 11:15:41.778937 progress 10% (19MB)
100 11:15:42.350711 progress 15% (28MB)
101 11:15:42.713552 progress 20% (38MB)
102 11:15:43.034237 progress 25% (47MB)
103 11:15:43.618825 progress 30% (57MB)
104 11:15:44.165130 progress 35% (67MB)
105 11:15:44.742948 progress 40% (76MB)
106 11:15:45.291242 progress 45% (86MB)
107 11:15:45.859898 progress 50% (95MB)
108 11:15:46.473930 progress 55% (105MB)
109 11:15:47.118757 progress 60% (114MB)
110 11:15:47.236596 progress 65% (124MB)
111 11:15:47.375884 progress 70% (134MB)
112 11:15:47.470497 progress 75% (143MB)
113 11:15:47.542489 progress 80% (153MB)
114 11:15:47.609377 progress 85% (162MB)
115 11:15:47.705248 progress 90% (172MB)
116 11:15:47.972410 progress 95% (181MB)
117 11:15:48.526765 progress 100% (191MB)
118 11:15:48.531333 191MB downloaded in 7.78s (24.60MB/s)
119 11:15:48.531613 end: 1.4.1 http-download (duration 00:00:08) [common]
121 11:15:48.532036 end: 1.4 download-retry (duration 00:00:08) [common]
122 11:15:48.532154 start: 1.5 download-retry (timeout 00:09:52) [common]
123 11:15:48.532261 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 11:15:48.532428 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 11:15:48.532498 saving as /var/lib/lava/dispatcher/tmp/10591250/tftp-deploy-3xwj17rv/modules/modules.tar
126 11:15:48.532609 total size: 8547328 (8MB)
127 11:15:48.532671 Using unxz to decompress xz
128 11:15:48.536161 progress 0% (0MB)
129 11:15:48.557375 progress 5% (0MB)
130 11:15:48.581484 progress 10% (0MB)
131 11:15:48.606547 progress 15% (1MB)
132 11:15:48.629945 progress 20% (1MB)
133 11:15:48.654720 progress 25% (2MB)
134 11:15:48.678871 progress 30% (2MB)
135 11:15:48.703017 progress 35% (2MB)
136 11:15:48.726513 progress 40% (3MB)
137 11:15:48.750885 progress 45% (3MB)
138 11:15:48.774242 progress 50% (4MB)
139 11:15:48.796374 progress 55% (4MB)
140 11:15:48.820415 progress 60% (4MB)
141 11:15:48.844385 progress 65% (5MB)
142 11:15:48.869131 progress 70% (5MB)
143 11:15:48.894818 progress 75% (6MB)
144 11:15:48.922958 progress 80% (6MB)
145 11:15:48.944554 progress 85% (6MB)
146 11:15:48.973565 progress 90% (7MB)
147 11:15:48.996022 progress 95% (7MB)
148 11:15:49.018756 progress 100% (8MB)
149 11:15:49.024601 8MB downloaded in 0.49s (16.57MB/s)
150 11:15:49.024862 end: 1.5.1 http-download (duration 00:00:00) [common]
152 11:15:49.025122 end: 1.5 download-retry (duration 00:00:00) [common]
153 11:15:49.025214 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 11:15:49.025306 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 11:15:52.225699 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10591250/extract-nfsrootfs-r0k0govq
156 11:15:52.225918 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 11:15:52.226054 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 11:15:52.226267 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10591250/lava-overlay-qk1y24dn
159 11:15:52.226442 makedir: /var/lib/lava/dispatcher/tmp/10591250/lava-overlay-qk1y24dn/lava-10591250/bin
160 11:15:52.226580 makedir: /var/lib/lava/dispatcher/tmp/10591250/lava-overlay-qk1y24dn/lava-10591250/tests
161 11:15:52.226710 makedir: /var/lib/lava/dispatcher/tmp/10591250/lava-overlay-qk1y24dn/lava-10591250/results
162 11:15:52.226852 Creating /var/lib/lava/dispatcher/tmp/10591250/lava-overlay-qk1y24dn/lava-10591250/bin/lava-add-keys
163 11:15:52.227045 Creating /var/lib/lava/dispatcher/tmp/10591250/lava-overlay-qk1y24dn/lava-10591250/bin/lava-add-sources
164 11:15:52.227223 Creating /var/lib/lava/dispatcher/tmp/10591250/lava-overlay-qk1y24dn/lava-10591250/bin/lava-background-process-start
165 11:15:52.227395 Creating /var/lib/lava/dispatcher/tmp/10591250/lava-overlay-qk1y24dn/lava-10591250/bin/lava-background-process-stop
166 11:15:52.227518 Creating /var/lib/lava/dispatcher/tmp/10591250/lava-overlay-qk1y24dn/lava-10591250/bin/lava-common-functions
167 11:15:52.227634 Creating /var/lib/lava/dispatcher/tmp/10591250/lava-overlay-qk1y24dn/lava-10591250/bin/lava-echo-ipv4
168 11:15:52.227750 Creating /var/lib/lava/dispatcher/tmp/10591250/lava-overlay-qk1y24dn/lava-10591250/bin/lava-install-packages
169 11:15:52.227863 Creating /var/lib/lava/dispatcher/tmp/10591250/lava-overlay-qk1y24dn/lava-10591250/bin/lava-installed-packages
170 11:15:52.227974 Creating /var/lib/lava/dispatcher/tmp/10591250/lava-overlay-qk1y24dn/lava-10591250/bin/lava-os-build
171 11:15:52.228087 Creating /var/lib/lava/dispatcher/tmp/10591250/lava-overlay-qk1y24dn/lava-10591250/bin/lava-probe-channel
172 11:15:52.228246 Creating /var/lib/lava/dispatcher/tmp/10591250/lava-overlay-qk1y24dn/lava-10591250/bin/lava-probe-ip
173 11:15:52.228373 Creating /var/lib/lava/dispatcher/tmp/10591250/lava-overlay-qk1y24dn/lava-10591250/bin/lava-target-ip
174 11:15:52.228485 Creating /var/lib/lava/dispatcher/tmp/10591250/lava-overlay-qk1y24dn/lava-10591250/bin/lava-target-mac
175 11:15:52.229037 Creating /var/lib/lava/dispatcher/tmp/10591250/lava-overlay-qk1y24dn/lava-10591250/bin/lava-target-storage
176 11:15:52.229158 Creating /var/lib/lava/dispatcher/tmp/10591250/lava-overlay-qk1y24dn/lava-10591250/bin/lava-test-case
177 11:15:52.229273 Creating /var/lib/lava/dispatcher/tmp/10591250/lava-overlay-qk1y24dn/lava-10591250/bin/lava-test-event
178 11:15:52.229387 Creating /var/lib/lava/dispatcher/tmp/10591250/lava-overlay-qk1y24dn/lava-10591250/bin/lava-test-feedback
179 11:15:52.229500 Creating /var/lib/lava/dispatcher/tmp/10591250/lava-overlay-qk1y24dn/lava-10591250/bin/lava-test-raise
180 11:15:52.229617 Creating /var/lib/lava/dispatcher/tmp/10591250/lava-overlay-qk1y24dn/lava-10591250/bin/lava-test-reference
181 11:15:52.229732 Creating /var/lib/lava/dispatcher/tmp/10591250/lava-overlay-qk1y24dn/lava-10591250/bin/lava-test-runner
182 11:15:52.229845 Creating /var/lib/lava/dispatcher/tmp/10591250/lava-overlay-qk1y24dn/lava-10591250/bin/lava-test-set
183 11:15:52.229957 Creating /var/lib/lava/dispatcher/tmp/10591250/lava-overlay-qk1y24dn/lava-10591250/bin/lava-test-shell
184 11:15:52.230072 Updating /var/lib/lava/dispatcher/tmp/10591250/lava-overlay-qk1y24dn/lava-10591250/bin/lava-add-keys (debian)
185 11:15:52.230207 Updating /var/lib/lava/dispatcher/tmp/10591250/lava-overlay-qk1y24dn/lava-10591250/bin/lava-add-sources (debian)
186 11:15:52.230348 Updating /var/lib/lava/dispatcher/tmp/10591250/lava-overlay-qk1y24dn/lava-10591250/bin/lava-install-packages (debian)
187 11:15:52.230480 Updating /var/lib/lava/dispatcher/tmp/10591250/lava-overlay-qk1y24dn/lava-10591250/bin/lava-installed-packages (debian)
188 11:15:52.230615 Updating /var/lib/lava/dispatcher/tmp/10591250/lava-overlay-qk1y24dn/lava-10591250/bin/lava-os-build (debian)
189 11:15:52.230734 Creating /var/lib/lava/dispatcher/tmp/10591250/lava-overlay-qk1y24dn/lava-10591250/environment
190 11:15:52.230833 LAVA metadata
191 11:15:52.230899 - LAVA_JOB_ID=10591250
192 11:15:52.230958 - LAVA_DISPATCHER_IP=192.168.201.1
193 11:15:52.231053 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 11:15:52.231114 skipped lava-vland-overlay
195 11:15:52.231184 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 11:15:52.231261 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 11:15:52.231320 skipped lava-multinode-overlay
198 11:15:52.231388 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 11:15:52.231462 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 11:15:52.231531 Loading test definitions
201 11:15:52.231616 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 11:15:52.231682 Using /lava-10591250 at stage 0
203 11:15:52.231940 uuid=10591250_1.6.2.3.1 testdef=None
204 11:15:52.232023 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 11:15:52.232109 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 11:15:52.232572 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 11:15:52.232785 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 11:15:52.233315 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 11:15:52.233538 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 11:15:52.234092 runner path: /var/lib/lava/dispatcher/tmp/10591250/lava-overlay-qk1y24dn/lava-10591250/0/tests/0_timesync-off test_uuid 10591250_1.6.2.3.1
213 11:15:52.234267 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 11:15:52.234481 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 11:15:52.234549 Using /lava-10591250 at stage 0
217 11:15:52.234639 Fetching tests from https://github.com/kernelci/test-definitions.git
218 11:15:52.234711 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/10591250/lava-overlay-qk1y24dn/lava-10591250/0/tests/1_kselftest-arm64'
219 11:15:59.055946 Running '/usr/bin/git checkout kernelci.org
220 11:15:59.122058 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10591250/lava-overlay-qk1y24dn/lava-10591250/0/tests/1_kselftest-arm64/automated/linux/kselftest/kselftest.yaml
221 11:15:59.122803 uuid=10591250_1.6.2.3.5 testdef=None
222 11:15:59.122974 end: 1.6.2.3.5 git-repo-action (duration 00:00:07) [common]
224 11:15:59.123309 start: 1.6.2.3.6 test-overlay (timeout 00:09:41) [common]
225 11:15:59.124048 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 11:15:59.124299 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:41) [common]
228 11:15:59.125384 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 11:15:59.125638 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:41) [common]
231 11:15:59.126540 runner path: /var/lib/lava/dispatcher/tmp/10591250/lava-overlay-qk1y24dn/lava-10591250/0/tests/1_kselftest-arm64 test_uuid 10591250_1.6.2.3.5
232 11:15:59.126636 BOARD='mt8192-asurada-spherion-r0'
233 11:15:59.126710 BRANCH='cip'
234 11:15:59.126787 SKIPFILE='/dev/null'
235 11:15:59.126861 SKIP_INSTALL='True'
236 11:15:59.126933 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 11:15:59.127027 TST_CASENAME=''
238 11:15:59.127120 TST_CMDFILES='arm64'
239 11:15:59.127310 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 11:15:59.127657 Creating lava-test-runner.conf files
242 11:15:59.127754 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10591250/lava-overlay-qk1y24dn/lava-10591250/0 for stage 0
243 11:15:59.127887 - 0_timesync-off
244 11:15:59.127985 - 1_kselftest-arm64
245 11:15:59.128122 end: 1.6.2.3 test-definition (duration 00:00:07) [common]
246 11:15:59.128251 start: 1.6.2.4 compress-overlay (timeout 00:09:41) [common]
247 11:16:06.514369 end: 1.6.2.4 compress-overlay (duration 00:00:07) [common]
248 11:16:06.514521 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:34) [common]
249 11:16:06.514610 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 11:16:06.514704 end: 1.6.2 lava-overlay (duration 00:00:14) [common]
251 11:16:06.514793 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:34) [common]
252 11:16:06.626415 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 11:16:06.626836 start: 1.6.4 extract-modules (timeout 00:09:34) [common]
254 11:16:06.626957 extracting modules file /var/lib/lava/dispatcher/tmp/10591250/tftp-deploy-3xwj17rv/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10591250/extract-nfsrootfs-r0k0govq
255 11:16:06.824802 extracting modules file /var/lib/lava/dispatcher/tmp/10591250/tftp-deploy-3xwj17rv/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10591250/extract-overlay-ramdisk-cx8dkfhn/ramdisk
256 11:16:07.028619 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 11:16:07.028795 start: 1.6.5 apply-overlay-tftp (timeout 00:09:33) [common]
258 11:16:07.028894 [common] Applying overlay to NFS
259 11:16:07.028965 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10591250/compress-overlay-7bfx1q39/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10591250/extract-nfsrootfs-r0k0govq
260 11:16:07.903907 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 11:16:07.904085 start: 1.6.6 configure-preseed-file (timeout 00:09:33) [common]
262 11:16:07.904178 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 11:16:07.904271 start: 1.6.7 compress-ramdisk (timeout 00:09:33) [common]
264 11:16:07.904355 Building ramdisk /var/lib/lava/dispatcher/tmp/10591250/extract-overlay-ramdisk-cx8dkfhn/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10591250/extract-overlay-ramdisk-cx8dkfhn/ramdisk
265 11:16:08.209363 >> 117801 blocks
266 11:16:10.073003 rename /var/lib/lava/dispatcher/tmp/10591250/extract-overlay-ramdisk-cx8dkfhn/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10591250/tftp-deploy-3xwj17rv/ramdisk/ramdisk.cpio.gz
267 11:16:10.073432 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 11:16:10.073552 start: 1.6.8 prepare-kernel (timeout 00:09:30) [common]
269 11:16:10.073651 start: 1.6.8.1 prepare-fit (timeout 00:09:30) [common]
270 11:16:10.073753 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10591250/tftp-deploy-3xwj17rv/kernel/Image'
271 11:16:21.335453 Returned 0 in 11 seconds
272 11:16:21.436083 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10591250/tftp-deploy-3xwj17rv/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10591250/tftp-deploy-3xwj17rv/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10591250/tftp-deploy-3xwj17rv/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10591250/tftp-deploy-3xwj17rv/kernel/image.itb
273 11:16:21.757723 output: FIT description: Kernel Image image with one or more FDT blobs
274 11:16:21.758082 output: Created: Mon Jun 5 12:16:21 2023
275 11:16:21.758159 output: Image 0 (kernel-1)
276 11:16:21.758223 output: Description:
277 11:16:21.758287 output: Created: Mon Jun 5 12:16:21 2023
278 11:16:21.758347 output: Type: Kernel Image
279 11:16:21.758405 output: Compression: lzma compressed
280 11:16:21.758465 output: Data Size: 10086024 Bytes = 9849.63 KiB = 9.62 MiB
281 11:16:21.758521 output: Architecture: AArch64
282 11:16:21.758576 output: OS: Linux
283 11:16:21.758632 output: Load Address: 0x00000000
284 11:16:21.758688 output: Entry Point: 0x00000000
285 11:16:21.758744 output: Hash algo: crc32
286 11:16:21.758797 output: Hash value: eb1cf9b8
287 11:16:21.758848 output: Image 1 (fdt-1)
288 11:16:21.758899 output: Description: mt8192-asurada-spherion-r0
289 11:16:21.758951 output: Created: Mon Jun 5 12:16:21 2023
290 11:16:21.759003 output: Type: Flat Device Tree
291 11:16:21.759055 output: Compression: uncompressed
292 11:16:21.759106 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
293 11:16:21.759158 output: Architecture: AArch64
294 11:16:21.759210 output: Hash algo: crc32
295 11:16:21.759262 output: Hash value: 1df858fa
296 11:16:21.759314 output: Image 2 (ramdisk-1)
297 11:16:21.759366 output: Description: unavailable
298 11:16:21.759417 output: Created: Mon Jun 5 12:16:21 2023
299 11:16:21.759469 output: Type: RAMDisk Image
300 11:16:21.759521 output: Compression: Unknown Compression
301 11:16:21.759573 output: Data Size: 17646578 Bytes = 17232.99 KiB = 16.83 MiB
302 11:16:21.759625 output: Architecture: AArch64
303 11:16:21.759676 output: OS: Linux
304 11:16:21.759727 output: Load Address: unavailable
305 11:16:21.759779 output: Entry Point: unavailable
306 11:16:21.759830 output: Hash algo: crc32
307 11:16:21.759881 output: Hash value: 228e6ef1
308 11:16:21.759932 output: Default Configuration: 'conf-1'
309 11:16:21.759984 output: Configuration 0 (conf-1)
310 11:16:21.760035 output: Description: mt8192-asurada-spherion-r0
311 11:16:21.760087 output: Kernel: kernel-1
312 11:16:21.760138 output: Init Ramdisk: ramdisk-1
313 11:16:21.760189 output: FDT: fdt-1
314 11:16:21.760240 output: Loadables: kernel-1
315 11:16:21.760292 output:
316 11:16:21.760488 end: 1.6.8.1 prepare-fit (duration 00:00:12) [common]
317 11:16:21.760635 end: 1.6.8 prepare-kernel (duration 00:00:12) [common]
318 11:16:21.760740 end: 1.6 prepare-tftp-overlay (duration 00:00:33) [common]
319 11:16:21.760834 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:19) [common]
320 11:16:21.760916 No LXC device requested
321 11:16:21.760993 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 11:16:21.761077 start: 1.8 deploy-device-env (timeout 00:09:19) [common]
323 11:16:21.761152 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 11:16:21.761217 Checking files for TFTP limit of 4294967296 bytes.
325 11:16:21.761714 end: 1 tftp-deploy (duration 00:00:41) [common]
326 11:16:21.761824 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 11:16:21.761918 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 11:16:21.762042 substitutions:
329 11:16:21.762109 - {DTB}: 10591250/tftp-deploy-3xwj17rv/dtb/mt8192-asurada-spherion-r0.dtb
330 11:16:21.762174 - {INITRD}: 10591250/tftp-deploy-3xwj17rv/ramdisk/ramdisk.cpio.gz
331 11:16:21.762232 - {KERNEL}: 10591250/tftp-deploy-3xwj17rv/kernel/Image
332 11:16:21.762288 - {LAVA_MAC}: None
333 11:16:21.762344 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10591250/extract-nfsrootfs-r0k0govq
334 11:16:21.762400 - {NFS_SERVER_IP}: 192.168.201.1
335 11:16:21.762455 - {PRESEED_CONFIG}: None
336 11:16:21.762509 - {PRESEED_LOCAL}: None
337 11:16:21.762563 - {RAMDISK}: 10591250/tftp-deploy-3xwj17rv/ramdisk/ramdisk.cpio.gz
338 11:16:21.762617 - {ROOT_PART}: None
339 11:16:21.762670 - {ROOT}: None
340 11:16:21.762728 - {SERVER_IP}: 192.168.201.1
341 11:16:21.762797 - {TEE}: None
342 11:16:21.762852 Parsed boot commands:
343 11:16:21.762903 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 11:16:21.763077 Parsed boot commands: tftpboot 192.168.201.1 10591250/tftp-deploy-3xwj17rv/kernel/image.itb 10591250/tftp-deploy-3xwj17rv/kernel/cmdline
345 11:16:21.763170 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 11:16:21.763252 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 11:16:21.763338 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 11:16:21.763422 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 11:16:21.763491 Not connected, no need to disconnect.
350 11:16:21.763565 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 11:16:21.763647 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 11:16:21.763710 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-9'
353 11:16:21.767110 Setting prompt string to ['lava-test: # ']
354 11:16:21.767450 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 11:16:21.767557 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 11:16:21.767658 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 11:16:21.767746 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 11:16:21.767945 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
359 11:16:26.903364 >> Command sent successfully.
360 11:16:26.905744 Returned 0 in 5 seconds
361 11:16:27.006139 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 11:16:27.006454 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 11:16:27.006553 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 11:16:27.006669 Setting prompt string to 'Starting depthcharge on Spherion...'
366 11:16:27.006738 Changing prompt to 'Starting depthcharge on Spherion...'
367 11:16:27.006809 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 11:16:27.007078 [Enter `^Ec?' for help]
369 11:16:27.178532
370 11:16:27.178671
371 11:16:27.178738 F0: 102B 0000
372 11:16:27.178800
373 11:16:27.182532 F3: 1001 0000 [0200]
374 11:16:27.182615
375 11:16:27.182680 F3: 1001 0000
376 11:16:27.182742
377 11:16:27.182799 F7: 102D 0000
378 11:16:27.182855
379 11:16:27.185972 F1: 0000 0000
380 11:16:27.186056
381 11:16:27.186120 V0: 0000 0000 [0001]
382 11:16:27.186181
383 11:16:27.186240 00: 0007 8000
384 11:16:27.186302
385 11:16:27.190189 01: 0000 0000
386 11:16:27.190272
387 11:16:27.190336 BP: 0C00 0209 [0000]
388 11:16:27.190397
389 11:16:27.193181 G0: 1182 0000
390 11:16:27.193262
391 11:16:27.193326 EC: 0000 0021 [4000]
392 11:16:27.193385
393 11:16:27.196775 S7: 0000 0000 [0000]
394 11:16:27.196856
395 11:16:27.196920 CC: 0000 0000 [0001]
396 11:16:27.196978
397 11:16:27.199970 T0: 0000 0040 [010F]
398 11:16:27.200052
399 11:16:27.200117 Jump to BL
400 11:16:27.200212
401 11:16:27.226718
402 11:16:27.226800
403 11:16:27.226863
404 11:16:27.233410 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 11:16:27.236960 ARM64: Exception handlers installed.
406 11:16:27.239987 ARM64: Testing exception
407 11:16:27.243864 ARM64: Done test exception
408 11:16:27.250907 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 11:16:27.262228 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 11:16:27.265779 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 11:16:27.277679 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 11:16:27.284190 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 11:16:27.290912 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 11:16:27.302526 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 11:16:27.308763 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 11:16:27.328939 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 11:16:27.331951 WDT: Last reset was cold boot
418 11:16:27.335494 SPI1(PAD0) initialized at 2873684 Hz
419 11:16:27.338510 SPI5(PAD0) initialized at 992727 Hz
420 11:16:27.341980 VBOOT: Loading verstage.
421 11:16:27.348956 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 11:16:27.352496 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 11:16:27.355118 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 11:16:27.358941 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 11:16:27.365950 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 11:16:27.372901 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 11:16:27.383662 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 11:16:27.383746
429 11:16:27.383809
430 11:16:27.393535 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 11:16:27.397126 ARM64: Exception handlers installed.
432 11:16:27.400336 ARM64: Testing exception
433 11:16:27.400418 ARM64: Done test exception
434 11:16:27.406972 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 11:16:27.410087 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 11:16:27.424550 Probing TPM: . done!
437 11:16:27.424631 TPM ready after 0 ms
438 11:16:27.431214 Connected to device vid:did:rid of 1ae0:0028:00
439 11:16:27.440962 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
440 11:16:27.479641 Initialized TPM device CR50 revision 0
441 11:16:27.492414 tlcl_send_startup: Startup return code is 0
442 11:16:27.492499 TPM: setup succeeded
443 11:16:27.504257 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 11:16:27.512534 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 11:16:27.523075 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 11:16:27.532914 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 11:16:27.536049 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 11:16:27.539663 in-header: 03 07 00 00 08 00 00 00
449 11:16:27.542688 in-data: aa e4 47 04 13 02 00 00
450 11:16:27.545996 Chrome EC: UHEPI supported
451 11:16:27.552509 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 11:16:27.555911 in-header: 03 ad 00 00 08 00 00 00
453 11:16:27.559737 in-data: 00 20 20 08 00 00 00 00
454 11:16:27.559819 Phase 1
455 11:16:27.562633 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 11:16:27.569447 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 11:16:27.575872 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 11:16:27.579463 Recovery requested (1009000e)
459 11:16:27.583186 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 11:16:27.591804 tlcl_extend: response is 0
461 11:16:27.600567 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 11:16:27.605113 tlcl_extend: response is 0
463 11:16:27.611578 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 11:16:27.632458 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
465 11:16:27.639107 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 11:16:27.639192
467 11:16:27.639259
468 11:16:27.649890 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 11:16:27.653726 ARM64: Exception handlers installed.
470 11:16:27.653814 ARM64: Testing exception
471 11:16:27.656561 ARM64: Done test exception
472 11:16:27.679088 pmic_efuse_setting: Set efuses in 11 msecs
473 11:16:27.682042 pmwrap_interface_init: Select PMIF_VLD_RDY
474 11:16:27.685511 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 11:16:27.692960 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 11:16:27.695544 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 11:16:27.702425 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 11:16:27.705623 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 11:16:27.712966 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 11:16:27.715676 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 11:16:27.719404 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 11:16:27.725655 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 11:16:27.729109 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 11:16:27.735952 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 11:16:27.739206 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 11:16:27.742521 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 11:16:27.749491 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 11:16:27.756285 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 11:16:27.762553 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 11:16:27.765917 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 11:16:27.773067 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 11:16:27.778996 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 11:16:27.786458 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 11:16:27.789287 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 11:16:27.796448 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 11:16:27.799832 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 11:16:27.806600 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 11:16:27.810351 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 11:16:27.816638 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 11:16:27.820404 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 11:16:27.827219 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 11:16:27.830738 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 11:16:27.837664 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 11:16:27.841522 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 11:16:27.846265 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 11:16:27.852230 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 11:16:27.855963 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 11:16:27.862241 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 11:16:27.865479 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 11:16:27.872192 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 11:16:27.875717 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 11:16:27.882363 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 11:16:27.886317 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 11:16:27.889984 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 11:16:27.894250 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 11:16:27.900273 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 11:16:27.903684 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 11:16:27.906769 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 11:16:27.913812 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 11:16:27.916740 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 11:16:27.920065 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 11:16:27.923381 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 11:16:27.930064 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 11:16:27.933681 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 11:16:27.940782 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 11:16:27.950119 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 11:16:27.953266 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 11:16:27.963146 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 11:16:27.969865 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 11:16:27.976114 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 11:16:27.979916 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 11:16:27.983111 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 11:16:27.990913 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x2e
534 11:16:27.997213 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 11:16:28.001152 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
536 11:16:28.003845 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 11:16:28.014805 [RTC]rtc_get_frequency_meter,154: input=15, output=834
538 11:16:28.024444 [RTC]rtc_get_frequency_meter,154: input=7, output=708
539 11:16:28.034140 [RTC]rtc_get_frequency_meter,154: input=11, output=772
540 11:16:28.043418 [RTC]rtc_get_frequency_meter,154: input=13, output=803
541 11:16:28.053271 [RTC]rtc_get_frequency_meter,154: input=12, output=788
542 11:16:28.062884 [RTC]rtc_get_frequency_meter,154: input=12, output=787
543 11:16:28.072067 [RTC]rtc_get_frequency_meter,154: input=13, output=804
544 11:16:28.074995 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
545 11:16:28.082366 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
546 11:16:28.085828 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 11:16:28.088994 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 11:16:28.095858 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 11:16:28.099357 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 11:16:28.102461 ADC[4]: Raw value=904139 ID=7
551 11:16:28.102551 ADC[3]: Raw value=213282 ID=1
552 11:16:28.106111 RAM Code: 0x71
553 11:16:28.109143 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 11:16:28.115581 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 11:16:28.122628 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 11:16:28.128737 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 11:16:28.132241 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 11:16:28.135357 in-header: 03 07 00 00 08 00 00 00
559 11:16:28.138621 in-data: aa e4 47 04 13 02 00 00
560 11:16:28.142197 Chrome EC: UHEPI supported
561 11:16:28.148753 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 11:16:28.152069 in-header: 03 dd 00 00 08 00 00 00
563 11:16:28.155355 in-data: 90 20 60 08 00 00 00 00
564 11:16:28.158980 MRC: failed to locate region type 0.
565 11:16:28.165773 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 11:16:28.168775 DRAM-K: Running full calibration
567 11:16:28.175156 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 11:16:28.175248 header.status = 0x0
569 11:16:28.178847 header.version = 0x6 (expected: 0x6)
570 11:16:28.182433 header.size = 0xd00 (expected: 0xd00)
571 11:16:28.185739 header.flags = 0x0
572 11:16:28.192475 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 11:16:28.208990 read SPI 0x72590 0x1c583: 12497 us, 9290 KB/s, 74.320 Mbps
574 11:16:28.215611 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 11:16:28.220324 dram_init: ddr_geometry: 2
576 11:16:28.222269 [EMI] MDL number = 2
577 11:16:28.222358 [EMI] Get MDL freq = 0
578 11:16:28.225706 dram_init: ddr_type: 0
579 11:16:28.225793 is_discrete_lpddr4: 1
580 11:16:28.229370 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 11:16:28.229456
582 11:16:28.229569
583 11:16:28.232166 [Bian_co] ETT version 0.0.0.1
584 11:16:28.238781 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 11:16:28.238874
586 11:16:28.242611 dramc_set_vcore_voltage set vcore to 650000
587 11:16:28.242696 Read voltage for 800, 4
588 11:16:28.246138 Vio18 = 0
589 11:16:28.246223 Vcore = 650000
590 11:16:28.246289 Vdram = 0
591 11:16:28.248743 Vddq = 0
592 11:16:28.248826 Vmddr = 0
593 11:16:28.252707 dram_init: config_dvfs: 1
594 11:16:28.256092 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 11:16:28.262103 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 11:16:28.265556 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
597 11:16:28.269476 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
598 11:16:28.272119 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
599 11:16:28.275479 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
600 11:16:28.279134 MEM_TYPE=3, freq_sel=18
601 11:16:28.282441 sv_algorithm_assistance_LP4_1600
602 11:16:28.285781 ============ PULL DRAM RESETB DOWN ============
603 11:16:28.289061 ========== PULL DRAM RESETB DOWN end =========
604 11:16:28.295894 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 11:16:28.299095 ===================================
606 11:16:28.301865 LPDDR4 DRAM CONFIGURATION
607 11:16:28.305622 ===================================
608 11:16:28.305705 EX_ROW_EN[0] = 0x0
609 11:16:28.308868 EX_ROW_EN[1] = 0x0
610 11:16:28.308949 LP4Y_EN = 0x0
611 11:16:28.312305 WORK_FSP = 0x0
612 11:16:28.312387 WL = 0x2
613 11:16:28.315160 RL = 0x2
614 11:16:28.315242 BL = 0x2
615 11:16:28.318775 RPST = 0x0
616 11:16:28.318857 RD_PRE = 0x0
617 11:16:28.322189 WR_PRE = 0x1
618 11:16:28.322271 WR_PST = 0x0
619 11:16:28.325216 DBI_WR = 0x0
620 11:16:28.325298 DBI_RD = 0x0
621 11:16:28.328436 OTF = 0x1
622 11:16:28.331738 ===================================
623 11:16:28.335414 ===================================
624 11:16:28.335506 ANA top config
625 11:16:28.338521 ===================================
626 11:16:28.341863 DLL_ASYNC_EN = 0
627 11:16:28.345383 ALL_SLAVE_EN = 1
628 11:16:28.348495 NEW_RANK_MODE = 1
629 11:16:28.348633 DLL_IDLE_MODE = 1
630 11:16:28.351671 LP45_APHY_COMB_EN = 1
631 11:16:28.355059 TX_ODT_DIS = 1
632 11:16:28.358638 NEW_8X_MODE = 1
633 11:16:28.361642 ===================================
634 11:16:28.365056 ===================================
635 11:16:28.368845 data_rate = 1600
636 11:16:28.371579 CKR = 1
637 11:16:28.371661 DQ_P2S_RATIO = 8
638 11:16:28.374844 ===================================
639 11:16:28.378311 CA_P2S_RATIO = 8
640 11:16:28.381909 DQ_CA_OPEN = 0
641 11:16:28.385176 DQ_SEMI_OPEN = 0
642 11:16:28.388427 CA_SEMI_OPEN = 0
643 11:16:28.388521 CA_FULL_RATE = 0
644 11:16:28.392231 DQ_CKDIV4_EN = 1
645 11:16:28.395390 CA_CKDIV4_EN = 1
646 11:16:28.398346 CA_PREDIV_EN = 0
647 11:16:28.401525 PH8_DLY = 0
648 11:16:28.405217 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 11:16:28.405302 DQ_AAMCK_DIV = 4
650 11:16:28.408348 CA_AAMCK_DIV = 4
651 11:16:28.411657 CA_ADMCK_DIV = 4
652 11:16:28.414770 DQ_TRACK_CA_EN = 0
653 11:16:28.418465 CA_PICK = 800
654 11:16:28.421820 CA_MCKIO = 800
655 11:16:28.424782 MCKIO_SEMI = 0
656 11:16:28.424866 PLL_FREQ = 3068
657 11:16:28.428057 DQ_UI_PI_RATIO = 32
658 11:16:28.431477 CA_UI_PI_RATIO = 0
659 11:16:28.434734 ===================================
660 11:16:28.438176 ===================================
661 11:16:28.441262 memory_type:LPDDR4
662 11:16:28.444893 GP_NUM : 10
663 11:16:28.444978 SRAM_EN : 1
664 11:16:28.448308 MD32_EN : 0
665 11:16:28.451380 ===================================
666 11:16:28.451462 [ANA_INIT] >>>>>>>>>>>>>>
667 11:16:28.454360 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 11:16:28.457728 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 11:16:28.461041 ===================================
670 11:16:28.464835 data_rate = 1600,PCW = 0X7600
671 11:16:28.468027 ===================================
672 11:16:28.470970 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 11:16:28.478051 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 11:16:28.484717 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 11:16:28.487715 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 11:16:28.491275 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 11:16:28.494460 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 11:16:28.497548 [ANA_INIT] flow start
679 11:16:28.497633 [ANA_INIT] PLL >>>>>>>>
680 11:16:28.501437 [ANA_INIT] PLL <<<<<<<<
681 11:16:28.504241 [ANA_INIT] MIDPI >>>>>>>>
682 11:16:28.504324 [ANA_INIT] MIDPI <<<<<<<<
683 11:16:28.507803 [ANA_INIT] DLL >>>>>>>>
684 11:16:28.511139 [ANA_INIT] flow end
685 11:16:28.513997 ============ LP4 DIFF to SE enter ============
686 11:16:28.517643 ============ LP4 DIFF to SE exit ============
687 11:16:28.520532 [ANA_INIT] <<<<<<<<<<<<<
688 11:16:28.524259 [Flow] Enable top DCM control >>>>>
689 11:16:28.527339 [Flow] Enable top DCM control <<<<<
690 11:16:28.530777 Enable DLL master slave shuffle
691 11:16:28.534318 ==============================================================
692 11:16:28.537558 Gating Mode config
693 11:16:28.544218 ==============================================================
694 11:16:28.544338 Config description:
695 11:16:28.554187 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 11:16:28.560658 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 11:16:28.564678 SELPH_MODE 0: By rank 1: By Phase
698 11:16:28.570722 ==============================================================
699 11:16:28.573979 GAT_TRACK_EN = 1
700 11:16:28.577300 RX_GATING_MODE = 2
701 11:16:28.580412 RX_GATING_TRACK_MODE = 2
702 11:16:28.583768 SELPH_MODE = 1
703 11:16:28.587472 PICG_EARLY_EN = 1
704 11:16:28.590443 VALID_LAT_VALUE = 1
705 11:16:28.593989 ==============================================================
706 11:16:28.597488 Enter into Gating configuration >>>>
707 11:16:28.600575 Exit from Gating configuration <<<<
708 11:16:28.604089 Enter into DVFS_PRE_config >>>>>
709 11:16:28.617138 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 11:16:28.617273 Exit from DVFS_PRE_config <<<<<
711 11:16:28.620375 Enter into PICG configuration >>>>
712 11:16:28.623915 Exit from PICG configuration <<<<
713 11:16:28.627186 [RX_INPUT] configuration >>>>>
714 11:16:28.630695 [RX_INPUT] configuration <<<<<
715 11:16:28.637184 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 11:16:28.640785 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 11:16:28.648073 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 11:16:28.655559 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 11:16:28.659397 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 11:16:28.666281 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 11:16:28.670932 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 11:16:28.673651 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 11:16:28.677230 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 11:16:28.681020 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 11:16:28.684637 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 11:16:28.692072 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 11:16:28.695760 ===================================
728 11:16:28.695862 LPDDR4 DRAM CONFIGURATION
729 11:16:28.699175 ===================================
730 11:16:28.702930 EX_ROW_EN[0] = 0x0
731 11:16:28.703024 EX_ROW_EN[1] = 0x0
732 11:16:28.707319 LP4Y_EN = 0x0
733 11:16:28.707407 WORK_FSP = 0x0
734 11:16:28.710476 WL = 0x2
735 11:16:28.710562 RL = 0x2
736 11:16:28.714159 BL = 0x2
737 11:16:28.714247 RPST = 0x0
738 11:16:28.718122 RD_PRE = 0x0
739 11:16:28.718231 WR_PRE = 0x1
740 11:16:28.718298 WR_PST = 0x0
741 11:16:28.721372 DBI_WR = 0x0
742 11:16:28.721457 DBI_RD = 0x0
743 11:16:28.724819 OTF = 0x1
744 11:16:28.728630 ===================================
745 11:16:28.732071 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 11:16:28.736148 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 11:16:28.740033 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 11:16:28.743186 ===================================
749 11:16:28.747230 LPDDR4 DRAM CONFIGURATION
750 11:16:28.750818 ===================================
751 11:16:28.750913 EX_ROW_EN[0] = 0x10
752 11:16:28.754334 EX_ROW_EN[1] = 0x0
753 11:16:28.754421 LP4Y_EN = 0x0
754 11:16:28.758359 WORK_FSP = 0x0
755 11:16:28.758448 WL = 0x2
756 11:16:28.761914 RL = 0x2
757 11:16:28.762002 BL = 0x2
758 11:16:28.762071 RPST = 0x0
759 11:16:28.766011 RD_PRE = 0x0
760 11:16:28.766099 WR_PRE = 0x1
761 11:16:28.769294 WR_PST = 0x0
762 11:16:28.769381 DBI_WR = 0x0
763 11:16:28.772773 DBI_RD = 0x0
764 11:16:28.772861 OTF = 0x1
765 11:16:28.776777 ===================================
766 11:16:28.783673 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 11:16:28.787278 nWR fixed to 40
768 11:16:28.791007 [ModeRegInit_LP4] CH0 RK0
769 11:16:28.791106 [ModeRegInit_LP4] CH0 RK1
770 11:16:28.794836 [ModeRegInit_LP4] CH1 RK0
771 11:16:28.798175 [ModeRegInit_LP4] CH1 RK1
772 11:16:28.798267 match AC timing 13
773 11:16:28.801764 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 11:16:28.805242 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 11:16:28.812019 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 11:16:28.814899 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 11:16:28.821606 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 11:16:28.821716 [EMI DOE] emi_dcm 0
779 11:16:28.825219 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 11:16:28.828222 ==
781 11:16:28.828312 Dram Type= 6, Freq= 0, CH_0, rank 0
782 11:16:28.835489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 11:16:28.835613 ==
784 11:16:28.838642 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 11:16:28.845304 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 11:16:28.855061 [CA 0] Center 37 (7~68) winsize 62
787 11:16:28.857860 [CA 1] Center 37 (6~68) winsize 63
788 11:16:28.861516 [CA 2] Center 34 (4~65) winsize 62
789 11:16:28.864631 [CA 3] Center 34 (4~65) winsize 62
790 11:16:28.868139 [CA 4] Center 33 (3~64) winsize 62
791 11:16:28.871658 [CA 5] Center 33 (3~64) winsize 62
792 11:16:28.871747
793 11:16:28.874455 [CmdBusTrainingLP45] Vref(ca) range 1: 34
794 11:16:28.874541
795 11:16:28.877782 [CATrainingPosCal] consider 1 rank data
796 11:16:28.881112 u2DelayCellTimex100 = 270/100 ps
797 11:16:28.884273 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
798 11:16:28.891007 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
799 11:16:28.894596 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
800 11:16:28.897798 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
801 11:16:28.901255 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
802 11:16:28.903947 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
803 11:16:28.904035
804 11:16:28.907226 CA PerBit enable=1, Macro0, CA PI delay=33
805 11:16:28.907311
806 11:16:28.910565 [CBTSetCACLKResult] CA Dly = 33
807 11:16:28.914097 CS Dly: 7 (0~38)
808 11:16:28.914185 ==
809 11:16:28.917435 Dram Type= 6, Freq= 0, CH_0, rank 1
810 11:16:28.920645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 11:16:28.920733 ==
812 11:16:28.927410 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 11:16:28.931112 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 11:16:28.940979 [CA 0] Center 37 (6~68) winsize 63
815 11:16:28.944121 [CA 1] Center 37 (7~68) winsize 62
816 11:16:28.947243 [CA 2] Center 34 (4~65) winsize 62
817 11:16:28.950959 [CA 3] Center 34 (4~65) winsize 62
818 11:16:28.954275 [CA 4] Center 33 (3~64) winsize 62
819 11:16:28.957425 [CA 5] Center 33 (3~64) winsize 62
820 11:16:28.957513
821 11:16:28.961193 [CmdBusTrainingLP45] Vref(ca) range 1: 32
822 11:16:28.961279
823 11:16:28.963994 [CATrainingPosCal] consider 2 rank data
824 11:16:28.967379 u2DelayCellTimex100 = 270/100 ps
825 11:16:28.970688 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
826 11:16:28.977254 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
827 11:16:28.981037 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
828 11:16:28.984949 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
829 11:16:28.988161 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
830 11:16:28.992166 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
831 11:16:28.992276
832 11:16:28.996313 CA PerBit enable=1, Macro0, CA PI delay=33
833 11:16:28.996403
834 11:16:28.996469 [CBTSetCACLKResult] CA Dly = 33
835 11:16:28.999064 CS Dly: 7 (0~38)
836 11:16:28.999169
837 11:16:29.002429 ----->DramcWriteLeveling(PI) begin...
838 11:16:29.002547 ==
839 11:16:29.006075 Dram Type= 6, Freq= 0, CH_0, rank 0
840 11:16:29.009459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 11:16:29.009565 ==
842 11:16:29.013249 Write leveling (Byte 0): 34 => 34
843 11:16:29.016331 Write leveling (Byte 1): 31 => 31
844 11:16:29.019436 DramcWriteLeveling(PI) end<-----
845 11:16:29.019523
846 11:16:29.019587 ==
847 11:16:29.023076 Dram Type= 6, Freq= 0, CH_0, rank 0
848 11:16:29.026148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 11:16:29.026236 ==
850 11:16:29.030084 [Gating] SW mode calibration
851 11:16:29.036257 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 11:16:29.043376 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 11:16:29.046706 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 11:16:29.049958 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
855 11:16:29.056081 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
856 11:16:29.059868 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
857 11:16:29.062617 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 11:16:29.069103 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 11:16:29.072447 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 11:16:29.075806 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 11:16:29.082924 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 11:16:29.086447 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 11:16:29.089557 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 11:16:29.095732 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 11:16:29.099335 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 11:16:29.102441 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 11:16:29.109295 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 11:16:29.112643 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 11:16:29.116046 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
870 11:16:29.122509 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
871 11:16:29.125734 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
872 11:16:29.129101 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
873 11:16:29.135935 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 11:16:29.138975 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 11:16:29.142122 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 11:16:29.149500 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 11:16:29.152462 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 11:16:29.155842 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
879 11:16:29.162613 0 9 8 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (1 1)
880 11:16:29.165683 0 9 12 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
881 11:16:29.168636 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 11:16:29.175516 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 11:16:29.178435 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 11:16:29.182131 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 11:16:29.188275 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 11:16:29.192124 0 10 4 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
887 11:16:29.195140 0 10 8 | B1->B0 | 3333 2727 | 0 0 | (1 0) (1 0)
888 11:16:29.202393 0 10 12 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
889 11:16:29.205245 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 11:16:29.208258 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 11:16:29.215753 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 11:16:29.218398 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 11:16:29.221912 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 11:16:29.225177 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
895 11:16:29.231886 0 11 8 | B1->B0 | 2424 3939 | 0 0 | (0 0) (1 1)
896 11:16:29.235168 0 11 12 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
897 11:16:29.241415 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 11:16:29.244940 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 11:16:29.247850 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 11:16:29.255136 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 11:16:29.257935 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 11:16:29.261479 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
903 11:16:29.264493 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
904 11:16:29.271333 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 11:16:29.274527 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 11:16:29.278069 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 11:16:29.284804 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 11:16:29.287756 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 11:16:29.291243 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 11:16:29.298093 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 11:16:29.300737 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 11:16:29.304349 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 11:16:29.310735 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 11:16:29.314519 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 11:16:29.317676 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 11:16:29.324329 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 11:16:29.327554 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 11:16:29.331256 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
919 11:16:29.337425 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
920 11:16:29.340492 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
921 11:16:29.343880 Total UI for P1: 0, mck2ui 16
922 11:16:29.347340 best dqsien dly found for B0: ( 0, 14, 8)
923 11:16:29.350695 Total UI for P1: 0, mck2ui 16
924 11:16:29.353880 best dqsien dly found for B1: ( 0, 14, 10)
925 11:16:29.356877 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
926 11:16:29.360935 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
927 11:16:29.361028
928 11:16:29.364144 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
929 11:16:29.367503 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
930 11:16:29.370623 [Gating] SW calibration Done
931 11:16:29.370714 ==
932 11:16:29.374489 Dram Type= 6, Freq= 0, CH_0, rank 0
933 11:16:29.378004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 11:16:29.381082 ==
935 11:16:29.381177 RX Vref Scan: 0
936 11:16:29.381256
937 11:16:29.384382 RX Vref 0 -> 0, step: 1
938 11:16:29.384466
939 11:16:29.387899 RX Delay -130 -> 252, step: 16
940 11:16:29.391314 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
941 11:16:29.394428 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
942 11:16:29.397529 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 11:16:29.400739 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 11:16:29.407888 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
945 11:16:29.410877 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
946 11:16:29.414369 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
947 11:16:29.418200 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
948 11:16:29.420753 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
949 11:16:29.428071 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
950 11:16:29.431141 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
951 11:16:29.433926 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
952 11:16:29.437564 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
953 11:16:29.440817 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
954 11:16:29.447162 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
955 11:16:29.450971 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
956 11:16:29.451070 ==
957 11:16:29.454397 Dram Type= 6, Freq= 0, CH_0, rank 0
958 11:16:29.457462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 11:16:29.457555 ==
960 11:16:29.461363 DQS Delay:
961 11:16:29.461454 DQS0 = 0, DQS1 = 0
962 11:16:29.461521 DQM Delay:
963 11:16:29.464736 DQM0 = 87, DQM1 = 73
964 11:16:29.464824 DQ Delay:
965 11:16:29.468118 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
966 11:16:29.471538 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =101
967 11:16:29.475160 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
968 11:16:29.479062 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =77
969 11:16:29.479163
970 11:16:29.479232
971 11:16:29.479293 ==
972 11:16:29.482242 Dram Type= 6, Freq= 0, CH_0, rank 0
973 11:16:29.486120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 11:16:29.486213 ==
975 11:16:29.486279
976 11:16:29.486339
977 11:16:29.489748 TX Vref Scan disable
978 11:16:29.489837 == TX Byte 0 ==
979 11:16:29.493940 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
980 11:16:29.501086 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
981 11:16:29.501199 == TX Byte 1 ==
982 11:16:29.504910 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
983 11:16:29.508388 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
984 11:16:29.508487 ==
985 11:16:29.511788 Dram Type= 6, Freq= 0, CH_0, rank 0
986 11:16:29.518206 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 11:16:29.518310 ==
988 11:16:29.530146 TX Vref=22, minBit 2, minWin=27, winSum=438
989 11:16:29.533828 TX Vref=24, minBit 3, minWin=27, winSum=443
990 11:16:29.536848 TX Vref=26, minBit 8, minWin=27, winSum=446
991 11:16:29.540200 TX Vref=28, minBit 10, minWin=27, winSum=448
992 11:16:29.543641 TX Vref=30, minBit 10, minWin=27, winSum=449
993 11:16:29.547958 TX Vref=32, minBit 3, minWin=27, winSum=444
994 11:16:29.553831 [TxChooseVref] Worse bit 10, Min win 27, Win sum 449, Final Vref 30
995 11:16:29.553938
996 11:16:29.557017 Final TX Range 1 Vref 30
997 11:16:29.557104
998 11:16:29.557174 ==
999 11:16:29.560313 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 11:16:29.563557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 11:16:29.563655 ==
1002 11:16:29.566547
1003 11:16:29.566631
1004 11:16:29.566696 TX Vref Scan disable
1005 11:16:29.571122 == TX Byte 0 ==
1006 11:16:29.574584 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1007 11:16:29.578490 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1008 11:16:29.581937 == TX Byte 1 ==
1009 11:16:29.585996 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1010 11:16:29.589132 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1011 11:16:29.589227
1012 11:16:29.589299 [DATLAT]
1013 11:16:29.592766 Freq=800, CH0 RK0
1014 11:16:29.592857
1015 11:16:29.592923 DATLAT Default: 0xa
1016 11:16:29.596867 0, 0xFFFF, sum = 0
1017 11:16:29.596958 1, 0xFFFF, sum = 0
1018 11:16:29.600637 2, 0xFFFF, sum = 0
1019 11:16:29.600736 3, 0xFFFF, sum = 0
1020 11:16:29.604188 4, 0xFFFF, sum = 0
1021 11:16:29.604277 5, 0xFFFF, sum = 0
1022 11:16:29.606900 6, 0xFFFF, sum = 0
1023 11:16:29.606985 7, 0xFFFF, sum = 0
1024 11:16:29.609757 8, 0xFFFF, sum = 0
1025 11:16:29.609852 9, 0x0, sum = 1
1026 11:16:29.613301 10, 0x0, sum = 2
1027 11:16:29.613389 11, 0x0, sum = 3
1028 11:16:29.616501 12, 0x0, sum = 4
1029 11:16:29.616595 best_step = 10
1030 11:16:29.616661
1031 11:16:29.616721 ==
1032 11:16:29.619605 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 11:16:29.622848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 11:16:29.622938 ==
1035 11:16:29.626478 RX Vref Scan: 1
1036 11:16:29.626565
1037 11:16:29.629819 Set Vref Range= 32 -> 127
1038 11:16:29.629903
1039 11:16:29.629968 RX Vref 32 -> 127, step: 1
1040 11:16:29.630027
1041 11:16:29.633449 RX Delay -111 -> 252, step: 8
1042 11:16:29.633534
1043 11:16:29.636191 Set Vref, RX VrefLevel [Byte0]: 32
1044 11:16:29.639799 [Byte1]: 32
1045 11:16:29.643111
1046 11:16:29.643205 Set Vref, RX VrefLevel [Byte0]: 33
1047 11:16:29.646671 [Byte1]: 33
1048 11:16:29.650654
1049 11:16:29.650745 Set Vref, RX VrefLevel [Byte0]: 34
1050 11:16:29.654465 [Byte1]: 34
1051 11:16:29.658523
1052 11:16:29.658615 Set Vref, RX VrefLevel [Byte0]: 35
1053 11:16:29.661790 [Byte1]: 35
1054 11:16:29.665960
1055 11:16:29.666063 Set Vref, RX VrefLevel [Byte0]: 36
1056 11:16:29.670008 [Byte1]: 36
1057 11:16:29.673854
1058 11:16:29.673962 Set Vref, RX VrefLevel [Byte0]: 37
1059 11:16:29.676968 [Byte1]: 37
1060 11:16:29.681528
1061 11:16:29.681620 Set Vref, RX VrefLevel [Byte0]: 38
1062 11:16:29.684470 [Byte1]: 38
1063 11:16:29.688789
1064 11:16:29.688880 Set Vref, RX VrefLevel [Byte0]: 39
1065 11:16:29.693032 [Byte1]: 39
1066 11:16:29.696727
1067 11:16:29.696813 Set Vref, RX VrefLevel [Byte0]: 40
1068 11:16:29.700252 [Byte1]: 40
1069 11:16:29.704071
1070 11:16:29.704157 Set Vref, RX VrefLevel [Byte0]: 41
1071 11:16:29.707502 [Byte1]: 41
1072 11:16:29.711874
1073 11:16:29.711960 Set Vref, RX VrefLevel [Byte0]: 42
1074 11:16:29.715474 [Byte1]: 42
1075 11:16:29.719807
1076 11:16:29.719899 Set Vref, RX VrefLevel [Byte0]: 43
1077 11:16:29.722965 [Byte1]: 43
1078 11:16:29.727165
1079 11:16:29.727261 Set Vref, RX VrefLevel [Byte0]: 44
1080 11:16:29.730815 [Byte1]: 44
1081 11:16:29.734901
1082 11:16:29.734996 Set Vref, RX VrefLevel [Byte0]: 45
1083 11:16:29.737993 [Byte1]: 45
1084 11:16:29.742809
1085 11:16:29.742908 Set Vref, RX VrefLevel [Byte0]: 46
1086 11:16:29.745988 [Byte1]: 46
1087 11:16:29.750150
1088 11:16:29.750246 Set Vref, RX VrefLevel [Byte0]: 47
1089 11:16:29.753249 [Byte1]: 47
1090 11:16:29.758062
1091 11:16:29.758167 Set Vref, RX VrefLevel [Byte0]: 48
1092 11:16:29.761101 [Byte1]: 48
1093 11:16:29.765256
1094 11:16:29.765344 Set Vref, RX VrefLevel [Byte0]: 49
1095 11:16:29.768971 [Byte1]: 49
1096 11:16:29.772910
1097 11:16:29.772999 Set Vref, RX VrefLevel [Byte0]: 50
1098 11:16:29.776402 [Byte1]: 50
1099 11:16:29.780651
1100 11:16:29.780743 Set Vref, RX VrefLevel [Byte0]: 51
1101 11:16:29.784373 [Byte1]: 51
1102 11:16:29.788292
1103 11:16:29.788396 Set Vref, RX VrefLevel [Byte0]: 52
1104 11:16:29.791803 [Byte1]: 52
1105 11:16:29.796437
1106 11:16:29.796545 Set Vref, RX VrefLevel [Byte0]: 53
1107 11:16:29.799520 [Byte1]: 53
1108 11:16:29.803871
1109 11:16:29.803960 Set Vref, RX VrefLevel [Byte0]: 54
1110 11:16:29.806896 [Byte1]: 54
1111 11:16:29.811159
1112 11:16:29.811248 Set Vref, RX VrefLevel [Byte0]: 55
1113 11:16:29.815530 [Byte1]: 55
1114 11:16:29.819011
1115 11:16:29.819101 Set Vref, RX VrefLevel [Byte0]: 56
1116 11:16:29.822235 [Byte1]: 56
1117 11:16:29.826711
1118 11:16:29.826851 Set Vref, RX VrefLevel [Byte0]: 57
1119 11:16:29.829940 [Byte1]: 57
1120 11:16:29.834451
1121 11:16:29.834591 Set Vref, RX VrefLevel [Byte0]: 58
1122 11:16:29.837601 [Byte1]: 58
1123 11:16:29.842235
1124 11:16:29.842329 Set Vref, RX VrefLevel [Byte0]: 59
1125 11:16:29.845595 [Byte1]: 59
1126 11:16:29.849881
1127 11:16:29.849975 Set Vref, RX VrefLevel [Byte0]: 60
1128 11:16:29.853421 [Byte1]: 60
1129 11:16:29.857430
1130 11:16:29.857523 Set Vref, RX VrefLevel [Byte0]: 61
1131 11:16:29.861305 [Byte1]: 61
1132 11:16:29.864869
1133 11:16:29.868176 Set Vref, RX VrefLevel [Byte0]: 62
1134 11:16:29.868267 [Byte1]: 62
1135 11:16:29.872909
1136 11:16:29.873002 Set Vref, RX VrefLevel [Byte0]: 63
1137 11:16:29.876656 [Byte1]: 63
1138 11:16:29.880641
1139 11:16:29.880733 Set Vref, RX VrefLevel [Byte0]: 64
1140 11:16:29.884334 [Byte1]: 64
1141 11:16:29.888008
1142 11:16:29.888100 Set Vref, RX VrefLevel [Byte0]: 65
1143 11:16:29.891757 [Byte1]: 65
1144 11:16:29.895901
1145 11:16:29.895995 Set Vref, RX VrefLevel [Byte0]: 66
1146 11:16:29.899044 [Byte1]: 66
1147 11:16:29.903370
1148 11:16:29.903469 Set Vref, RX VrefLevel [Byte0]: 67
1149 11:16:29.906702 [Byte1]: 67
1150 11:16:29.910968
1151 11:16:29.911061 Set Vref, RX VrefLevel [Byte0]: 68
1152 11:16:29.914146 [Byte1]: 68
1153 11:16:29.918622
1154 11:16:29.918716 Set Vref, RX VrefLevel [Byte0]: 69
1155 11:16:29.921811 [Byte1]: 69
1156 11:16:29.926692
1157 11:16:29.926797 Set Vref, RX VrefLevel [Byte0]: 70
1158 11:16:29.929589 [Byte1]: 70
1159 11:16:29.934128
1160 11:16:29.934221 Set Vref, RX VrefLevel [Byte0]: 71
1161 11:16:29.937734 [Byte1]: 71
1162 11:16:29.941706
1163 11:16:29.941806 Set Vref, RX VrefLevel [Byte0]: 72
1164 11:16:29.945174 [Byte1]: 72
1165 11:16:29.949362
1166 11:16:29.949458 Set Vref, RX VrefLevel [Byte0]: 73
1167 11:16:29.952827 [Byte1]: 73
1168 11:16:29.956973
1169 11:16:29.957073 Set Vref, RX VrefLevel [Byte0]: 74
1170 11:16:29.961086 [Byte1]: 74
1171 11:16:29.964876
1172 11:16:29.964972 Set Vref, RX VrefLevel [Byte0]: 75
1173 11:16:29.967845 [Byte1]: 75
1174 11:16:29.972177
1175 11:16:29.972271 Set Vref, RX VrefLevel [Byte0]: 76
1176 11:16:29.975985 [Byte1]: 76
1177 11:16:29.979498
1178 11:16:29.979592 Set Vref, RX VrefLevel [Byte0]: 77
1179 11:16:29.983384 [Byte1]: 77
1180 11:16:29.987475
1181 11:16:29.987573 Set Vref, RX VrefLevel [Byte0]: 78
1182 11:16:29.990586 [Byte1]: 78
1183 11:16:29.994984
1184 11:16:29.995080 Set Vref, RX VrefLevel [Byte0]: 79
1185 11:16:29.998260 [Byte1]: 79
1186 11:16:30.002888
1187 11:16:30.002983 Set Vref, RX VrefLevel [Byte0]: 80
1188 11:16:30.006569 [Byte1]: 80
1189 11:16:30.010515
1190 11:16:30.010612 Set Vref, RX VrefLevel [Byte0]: 81
1191 11:16:30.014027 [Byte1]: 81
1192 11:16:30.017972
1193 11:16:30.018066 Set Vref, RX VrefLevel [Byte0]: 82
1194 11:16:30.021497 [Byte1]: 82
1195 11:16:30.026022
1196 11:16:30.026135 Final RX Vref Byte 0 = 67 to rank0
1197 11:16:30.029364 Final RX Vref Byte 1 = 50 to rank0
1198 11:16:30.033147 Final RX Vref Byte 0 = 67 to rank1
1199 11:16:30.036881 Final RX Vref Byte 1 = 50 to rank1==
1200 11:16:30.040240 Dram Type= 6, Freq= 0, CH_0, rank 0
1201 11:16:30.044444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1202 11:16:30.044589 ==
1203 11:16:30.044661 DQS Delay:
1204 11:16:30.047831 DQS0 = 0, DQS1 = 0
1205 11:16:30.047918 DQM Delay:
1206 11:16:30.051569 DQM0 = 87, DQM1 = 76
1207 11:16:30.051655 DQ Delay:
1208 11:16:30.054944 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1209 11:16:30.058790 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1210 11:16:30.058914 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1211 11:16:30.062324 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1212 11:16:30.062412
1213 11:16:30.065535
1214 11:16:30.072847 [DQSOSCAuto] RK0, (LSB)MR18= 0x4729, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 392 ps
1215 11:16:30.076627 CH0 RK0: MR19=606, MR18=4729
1216 11:16:30.080624 CH0_RK0: MR19=0x606, MR18=0x4729, DQSOSC=392, MR23=63, INC=96, DEC=64
1217 11:16:30.080725
1218 11:16:30.083951 ----->DramcWriteLeveling(PI) begin...
1219 11:16:30.084041 ==
1220 11:16:30.087717 Dram Type= 6, Freq= 0, CH_0, rank 1
1221 11:16:30.091397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1222 11:16:30.091501 ==
1223 11:16:30.094788 Write leveling (Byte 0): 31 => 31
1224 11:16:30.097938 Write leveling (Byte 1): 30 => 30
1225 11:16:30.101279 DramcWriteLeveling(PI) end<-----
1226 11:16:30.101374
1227 11:16:30.101441 ==
1228 11:16:30.145719 Dram Type= 6, Freq= 0, CH_0, rank 1
1229 11:16:30.146121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1230 11:16:30.146259 ==
1231 11:16:30.146320 [Gating] SW mode calibration
1232 11:16:30.146405 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1233 11:16:30.146489 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1234 11:16:30.146937 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1235 11:16:30.147448 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1236 11:16:30.147716 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1237 11:16:30.147789 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1238 11:16:30.147869 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 11:16:30.189351 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 11:16:30.189733 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 11:16:30.190106 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 11:16:30.190274 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 11:16:30.190437 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 11:16:30.190531 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 11:16:30.191211 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 11:16:30.191573 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 11:16:30.191665 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 11:16:30.191741 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 11:16:30.234042 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 11:16:30.234465 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 11:16:30.234564 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 11:16:30.234842 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1253 11:16:30.234931 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 11:16:30.235644 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 11:16:30.235921 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 11:16:30.236203 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 11:16:30.236316 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 11:16:30.236426 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 11:16:30.245418 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 11:16:30.245717 0 9 8 | B1->B0 | 2323 3333 | 0 0 | (0 0) (1 1)
1261 11:16:30.248925 0 9 12 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
1262 11:16:30.252643 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1263 11:16:30.256649 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1264 11:16:30.260007 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1265 11:16:30.264202 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1266 11:16:30.271445 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1267 11:16:30.275184 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1268 11:16:30.278503 0 10 8 | B1->B0 | 3030 2d2d | 0 0 | (1 0) (1 1)
1269 11:16:30.282187 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1270 11:16:30.286099 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1271 11:16:30.293284 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1272 11:16:30.296737 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1273 11:16:30.300760 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1274 11:16:30.304863 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1275 11:16:30.308448 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1276 11:16:30.311742 0 11 8 | B1->B0 | 2c2c 3f3f | 0 0 | (0 0) (0 0)
1277 11:16:30.318928 0 11 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1278 11:16:30.322841 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1279 11:16:30.326359 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1280 11:16:30.330419 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1281 11:16:30.334466 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1282 11:16:30.340394 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1283 11:16:30.343593 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1284 11:16:30.349876 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1285 11:16:30.354028 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1286 11:16:30.356885 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1287 11:16:30.360089 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1288 11:16:30.366835 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1289 11:16:30.370180 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1290 11:16:30.373487 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1291 11:16:30.379808 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1292 11:16:30.383384 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1293 11:16:30.386884 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1294 11:16:30.393316 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1295 11:16:30.396495 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1296 11:16:30.400362 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1297 11:16:30.406504 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1298 11:16:30.409938 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1299 11:16:30.413450 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1300 11:16:30.419870 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1301 11:16:30.423109 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1302 11:16:30.426578 Total UI for P1: 0, mck2ui 16
1303 11:16:30.429672 best dqsien dly found for B0: ( 0, 14, 6)
1304 11:16:30.433371 Total UI for P1: 0, mck2ui 16
1305 11:16:30.436606 best dqsien dly found for B1: ( 0, 14, 10)
1306 11:16:30.439982 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1307 11:16:30.443339 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1308 11:16:30.443434
1309 11:16:30.446584 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1310 11:16:30.449686 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1311 11:16:30.453667 [Gating] SW calibration Done
1312 11:16:30.453759 ==
1313 11:16:30.456667 Dram Type= 6, Freq= 0, CH_0, rank 1
1314 11:16:30.460056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1315 11:16:30.460158 ==
1316 11:16:30.463082 RX Vref Scan: 0
1317 11:16:30.463167
1318 11:16:30.466359 RX Vref 0 -> 0, step: 1
1319 11:16:30.466443
1320 11:16:30.470292 RX Delay -130 -> 252, step: 16
1321 11:16:30.473196 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1322 11:16:30.476223 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1323 11:16:30.479844 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
1324 11:16:30.483052 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1325 11:16:30.489979 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1326 11:16:30.493384 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
1327 11:16:30.496658 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1328 11:16:30.499792 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
1329 11:16:30.502780 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1330 11:16:30.509444 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1331 11:16:30.512952 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1332 11:16:30.516140 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1333 11:16:30.519727 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1334 11:16:30.523252 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1335 11:16:30.529538 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1336 11:16:30.532753 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1337 11:16:30.532848 ==
1338 11:16:30.535875 Dram Type= 6, Freq= 0, CH_0, rank 1
1339 11:16:30.539445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1340 11:16:30.539543 ==
1341 11:16:30.542559 DQS Delay:
1342 11:16:30.542649 DQS0 = 0, DQS1 = 0
1343 11:16:30.542715 DQM Delay:
1344 11:16:30.545844 DQM0 = 88, DQM1 = 79
1345 11:16:30.545930 DQ Delay:
1346 11:16:30.548959 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
1347 11:16:30.553088 DQ4 =85, DQ5 =77, DQ6 =101, DQ7 =101
1348 11:16:30.555579 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1349 11:16:30.559035 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1350 11:16:30.559126
1351 11:16:30.559192
1352 11:16:30.562556 ==
1353 11:16:30.562643 Dram Type= 6, Freq= 0, CH_0, rank 1
1354 11:16:30.569324 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1355 11:16:30.569434 ==
1356 11:16:30.569504
1357 11:16:30.569565
1358 11:16:30.572481 TX Vref Scan disable
1359 11:16:30.572581 == TX Byte 0 ==
1360 11:16:30.575412 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
1361 11:16:30.582365 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
1362 11:16:30.582478 == TX Byte 1 ==
1363 11:16:30.585617 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1364 11:16:30.592352 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1365 11:16:30.592463 ==
1366 11:16:30.595962 Dram Type= 6, Freq= 0, CH_0, rank 1
1367 11:16:30.598797 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1368 11:16:30.598884 ==
1369 11:16:30.612115 TX Vref=22, minBit 11, minWin=27, winSum=445
1370 11:16:30.615537 TX Vref=24, minBit 9, minWin=27, winSum=447
1371 11:16:30.618643 TX Vref=26, minBit 9, minWin=27, winSum=447
1372 11:16:30.622027 TX Vref=28, minBit 9, minWin=27, winSum=446
1373 11:16:30.625444 TX Vref=30, minBit 9, minWin=27, winSum=448
1374 11:16:30.631925 TX Vref=32, minBit 9, minWin=27, winSum=447
1375 11:16:30.635568 [TxChooseVref] Worse bit 9, Min win 27, Win sum 448, Final Vref 30
1376 11:16:30.635670
1377 11:16:30.638625 Final TX Range 1 Vref 30
1378 11:16:30.638715
1379 11:16:30.638778 ==
1380 11:16:30.642200 Dram Type= 6, Freq= 0, CH_0, rank 1
1381 11:16:30.645242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1382 11:16:30.648460 ==
1383 11:16:30.648635
1384 11:16:30.648723
1385 11:16:30.648810 TX Vref Scan disable
1386 11:16:30.652121 == TX Byte 0 ==
1387 11:16:30.655328 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1388 11:16:30.661969 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1389 11:16:30.662070 == TX Byte 1 ==
1390 11:16:30.665191 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1391 11:16:30.672630 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1392 11:16:30.672735
1393 11:16:30.672799 [DATLAT]
1394 11:16:30.672857 Freq=800, CH0 RK1
1395 11:16:30.672912
1396 11:16:30.675379 DATLAT Default: 0xa
1397 11:16:30.675457 0, 0xFFFF, sum = 0
1398 11:16:30.678389 1, 0xFFFF, sum = 0
1399 11:16:30.678470 2, 0xFFFF, sum = 0
1400 11:16:30.681924 3, 0xFFFF, sum = 0
1401 11:16:30.685101 4, 0xFFFF, sum = 0
1402 11:16:30.685187 5, 0xFFFF, sum = 0
1403 11:16:30.689090 6, 0xFFFF, sum = 0
1404 11:16:30.689177 7, 0xFFFF, sum = 0
1405 11:16:30.692028 8, 0xFFFF, sum = 0
1406 11:16:30.692110 9, 0x0, sum = 1
1407 11:16:30.692203 10, 0x0, sum = 2
1408 11:16:30.695297 11, 0x0, sum = 3
1409 11:16:30.695378 12, 0x0, sum = 4
1410 11:16:30.698830 best_step = 10
1411 11:16:30.698911
1412 11:16:30.698973 ==
1413 11:16:30.702107 Dram Type= 6, Freq= 0, CH_0, rank 1
1414 11:16:30.705538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1415 11:16:30.705622 ==
1416 11:16:30.708396 RX Vref Scan: 0
1417 11:16:30.708500
1418 11:16:30.708607 RX Vref 0 -> 0, step: 1
1419 11:16:30.711983
1420 11:16:30.712062 RX Delay -95 -> 252, step: 8
1421 11:16:30.718674 iDelay=217, Bit 0, Center 84 (-31 ~ 200) 232
1422 11:16:30.722044 iDelay=217, Bit 1, Center 92 (-23 ~ 208) 232
1423 11:16:30.725689 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
1424 11:16:30.728849 iDelay=217, Bit 3, Center 84 (-31 ~ 200) 232
1425 11:16:30.731942 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
1426 11:16:30.738412 iDelay=217, Bit 5, Center 76 (-39 ~ 192) 232
1427 11:16:30.741890 iDelay=217, Bit 6, Center 92 (-23 ~ 208) 232
1428 11:16:30.745011 iDelay=217, Bit 7, Center 96 (-23 ~ 216) 240
1429 11:16:30.748197 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
1430 11:16:30.751774 iDelay=217, Bit 9, Center 60 (-55 ~ 176) 232
1431 11:16:30.758516 iDelay=217, Bit 10, Center 76 (-39 ~ 192) 232
1432 11:16:30.762052 iDelay=217, Bit 11, Center 68 (-47 ~ 184) 232
1433 11:16:30.765492 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
1434 11:16:30.768326 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
1435 11:16:30.774918 iDelay=217, Bit 14, Center 88 (-23 ~ 200) 224
1436 11:16:30.778013 iDelay=217, Bit 15, Center 84 (-31 ~ 200) 232
1437 11:16:30.778106 ==
1438 11:16:30.781708 Dram Type= 6, Freq= 0, CH_0, rank 1
1439 11:16:30.784949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1440 11:16:30.785037 ==
1441 11:16:30.788548 DQS Delay:
1442 11:16:30.788635 DQS0 = 0, DQS1 = 0
1443 11:16:30.788700 DQM Delay:
1444 11:16:30.791686 DQM0 = 85, DQM1 = 76
1445 11:16:30.791768 DQ Delay:
1446 11:16:30.795415 DQ0 =84, DQ1 =92, DQ2 =76, DQ3 =84
1447 11:16:30.798715 DQ4 =84, DQ5 =76, DQ6 =92, DQ7 =96
1448 11:16:30.801669 DQ8 =68, DQ9 =60, DQ10 =76, DQ11 =68
1449 11:16:30.805019 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1450 11:16:30.805106
1451 11:16:30.805172
1452 11:16:30.814511 [DQSOSCAuto] RK1, (LSB)MR18= 0x3d03, (MSB)MR19= 0x606, tDQSOscB0 = 409 ps tDQSOscB1 = 394 ps
1453 11:16:30.814621 CH0 RK1: MR19=606, MR18=3D03
1454 11:16:30.821617 CH0_RK1: MR19=0x606, MR18=0x3D03, DQSOSC=394, MR23=63, INC=95, DEC=63
1455 11:16:30.824644 [RxdqsGatingPostProcess] freq 800
1456 11:16:30.831610 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1457 11:16:30.834766 Pre-setting of DQS Precalculation
1458 11:16:30.838002 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1459 11:16:30.838124 ==
1460 11:16:30.841252 Dram Type= 6, Freq= 0, CH_1, rank 0
1461 11:16:30.847998 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1462 11:16:30.848114 ==
1463 11:16:30.851209 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1464 11:16:30.857842 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1465 11:16:30.867205 [CA 0] Center 36 (6~67) winsize 62
1466 11:16:30.870185 [CA 1] Center 36 (6~67) winsize 62
1467 11:16:30.874007 [CA 2] Center 34 (4~65) winsize 62
1468 11:16:30.876995 [CA 3] Center 34 (3~65) winsize 63
1469 11:16:30.880510 [CA 4] Center 34 (4~65) winsize 62
1470 11:16:30.883712 [CA 5] Center 34 (3~65) winsize 63
1471 11:16:30.883805
1472 11:16:30.887069 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1473 11:16:30.887156
1474 11:16:30.890319 [CATrainingPosCal] consider 1 rank data
1475 11:16:30.894401 u2DelayCellTimex100 = 270/100 ps
1476 11:16:30.897126 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1477 11:16:30.903811 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1478 11:16:30.906813 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1479 11:16:30.910192 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1480 11:16:30.913262 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1481 11:16:30.917190 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
1482 11:16:30.917285
1483 11:16:30.919789 CA PerBit enable=1, Macro0, CA PI delay=34
1484 11:16:30.919876
1485 11:16:30.923466 [CBTSetCACLKResult] CA Dly = 34
1486 11:16:30.923555 CS Dly: 5 (0~36)
1487 11:16:30.926543 ==
1488 11:16:30.930264 Dram Type= 6, Freq= 0, CH_1, rank 1
1489 11:16:30.933061 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1490 11:16:30.933154 ==
1491 11:16:30.936465 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1492 11:16:30.943010 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1493 11:16:30.953288 [CA 0] Center 36 (6~67) winsize 62
1494 11:16:30.956775 [CA 1] Center 37 (6~68) winsize 63
1495 11:16:30.959928 [CA 2] Center 34 (4~65) winsize 62
1496 11:16:30.963326 [CA 3] Center 34 (3~65) winsize 63
1497 11:16:30.966555 [CA 4] Center 34 (4~65) winsize 62
1498 11:16:30.969992 [CA 5] Center 33 (3~64) winsize 62
1499 11:16:30.970082
1500 11:16:30.973308 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1501 11:16:30.973392
1502 11:16:30.976728 [CATrainingPosCal] consider 2 rank data
1503 11:16:30.979637 u2DelayCellTimex100 = 270/100 ps
1504 11:16:30.983052 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1505 11:16:30.989533 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1506 11:16:30.993153 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1507 11:16:30.996862 CA3 delay=34 (3~65),Diff = 1 PI (7 cell)
1508 11:16:30.999537 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1509 11:16:31.003234 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1510 11:16:31.003325
1511 11:16:31.006714 CA PerBit enable=1, Macro0, CA PI delay=33
1512 11:16:31.006800
1513 11:16:31.010047 [CBTSetCACLKResult] CA Dly = 33
1514 11:16:31.010131 CS Dly: 6 (0~38)
1515 11:16:31.010196
1516 11:16:31.013192 ----->DramcWriteLeveling(PI) begin...
1517 11:16:31.016481 ==
1518 11:16:31.019536 Dram Type= 6, Freq= 0, CH_1, rank 0
1519 11:16:31.023166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1520 11:16:31.023256 ==
1521 11:16:31.026150 Write leveling (Byte 0): 28 => 28
1522 11:16:31.029837 Write leveling (Byte 1): 28 => 28
1523 11:16:31.033128 DramcWriteLeveling(PI) end<-----
1524 11:16:31.033215
1525 11:16:31.033281 ==
1526 11:16:31.036342 Dram Type= 6, Freq= 0, CH_1, rank 0
1527 11:16:31.039462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1528 11:16:31.039554 ==
1529 11:16:31.042790 [Gating] SW mode calibration
1530 11:16:31.049148 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1531 11:16:31.056321 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1532 11:16:31.059401 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1533 11:16:31.062819 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1534 11:16:31.069476 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1535 11:16:31.072818 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1536 11:16:31.076252 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 11:16:31.079294 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 11:16:31.085795 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 11:16:31.089524 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 11:16:31.092709 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 11:16:31.099126 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 11:16:31.102798 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 11:16:31.106192 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1544 11:16:31.112412 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1545 11:16:31.115598 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1546 11:16:31.119039 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1547 11:16:31.125892 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1548 11:16:31.129119 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1549 11:16:31.132621 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1550 11:16:31.139358 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 11:16:31.142581 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 11:16:31.145538 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 11:16:31.152081 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 11:16:31.155612 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 11:16:31.159189 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 11:16:31.165679 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 11:16:31.169394 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 11:16:31.172339 0 9 8 | B1->B0 | 2e2d 2f2f | 1 1 | (0 0) (1 1)
1559 11:16:31.179194 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1560 11:16:31.181987 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1561 11:16:31.185301 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1562 11:16:31.192444 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1563 11:16:31.195178 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1564 11:16:31.198809 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1565 11:16:31.205788 0 10 4 | B1->B0 | 3232 3131 | 1 1 | (1 0) (1 0)
1566 11:16:31.208684 0 10 8 | B1->B0 | 2828 2424 | 1 0 | (1 0) (0 0)
1567 11:16:31.211828 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1568 11:16:31.218363 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1569 11:16:31.221610 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1570 11:16:31.225451 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1571 11:16:31.231947 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1572 11:16:31.235331 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1573 11:16:31.238300 0 11 4 | B1->B0 | 2727 2929 | 0 0 | (0 0) (0 0)
1574 11:16:31.245145 0 11 8 | B1->B0 | 3a3a 4343 | 1 1 | (0 0) (0 0)
1575 11:16:31.248586 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1576 11:16:31.251940 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1577 11:16:31.258191 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1578 11:16:31.262172 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1579 11:16:31.264644 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1580 11:16:31.271372 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1581 11:16:31.274680 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1582 11:16:31.278126 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1583 11:16:31.281485 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1584 11:16:31.288067 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1585 11:16:31.291225 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1586 11:16:31.295012 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1587 11:16:31.301196 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1588 11:16:31.304474 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1589 11:16:31.307752 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1590 11:16:31.314498 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1591 11:16:31.318456 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1592 11:16:31.321324 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1593 11:16:31.327516 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1594 11:16:31.330844 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1595 11:16:31.334259 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1596 11:16:31.340830 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1597 11:16:31.344806 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1598 11:16:31.348254 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1599 11:16:31.351387 Total UI for P1: 0, mck2ui 16
1600 11:16:31.354252 best dqsien dly found for B0: ( 0, 14, 4)
1601 11:16:31.360824 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1602 11:16:31.360952 Total UI for P1: 0, mck2ui 16
1603 11:16:31.367986 best dqsien dly found for B1: ( 0, 14, 6)
1604 11:16:31.370879 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1605 11:16:31.374282 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1606 11:16:31.374375
1607 11:16:31.377307 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1608 11:16:31.380727 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1609 11:16:31.384008 [Gating] SW calibration Done
1610 11:16:31.384094 ==
1611 11:16:31.387599 Dram Type= 6, Freq= 0, CH_1, rank 0
1612 11:16:31.391123 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1613 11:16:31.391212 ==
1614 11:16:31.393877 RX Vref Scan: 0
1615 11:16:31.393960
1616 11:16:31.394026 RX Vref 0 -> 0, step: 1
1617 11:16:31.394085
1618 11:16:31.397509 RX Delay -130 -> 252, step: 16
1619 11:16:31.400498 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1620 11:16:31.407881 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1621 11:16:31.410797 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1622 11:16:31.414188 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1623 11:16:31.417018 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1624 11:16:31.420435 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1625 11:16:31.427272 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1626 11:16:31.430769 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1627 11:16:31.434052 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1628 11:16:31.437011 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1629 11:16:31.444003 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1630 11:16:31.447083 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1631 11:16:31.450250 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1632 11:16:31.454104 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1633 11:16:31.456937 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1634 11:16:31.463379 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1635 11:16:31.463492 ==
1636 11:16:31.466898 Dram Type= 6, Freq= 0, CH_1, rank 0
1637 11:16:31.470249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1638 11:16:31.470339 ==
1639 11:16:31.470407 DQS Delay:
1640 11:16:31.473392 DQS0 = 0, DQS1 = 0
1641 11:16:31.473477 DQM Delay:
1642 11:16:31.476909 DQM0 = 89, DQM1 = 79
1643 11:16:31.476996 DQ Delay:
1644 11:16:31.480859 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1645 11:16:31.483347 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1646 11:16:31.486794 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1647 11:16:31.490167 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1648 11:16:31.490256
1649 11:16:31.490321
1650 11:16:31.490380 ==
1651 11:16:31.493425 Dram Type= 6, Freq= 0, CH_1, rank 0
1652 11:16:31.496735 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1653 11:16:31.499811 ==
1654 11:16:31.499897
1655 11:16:31.499962
1656 11:16:31.500022 TX Vref Scan disable
1657 11:16:31.503665 == TX Byte 0 ==
1658 11:16:31.506429 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1659 11:16:31.510231 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1660 11:16:31.513389 == TX Byte 1 ==
1661 11:16:31.516730 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1662 11:16:31.520445 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1663 11:16:31.523914 ==
1664 11:16:31.526703 Dram Type= 6, Freq= 0, CH_1, rank 0
1665 11:16:31.529969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1666 11:16:31.530059 ==
1667 11:16:31.542032 TX Vref=22, minBit 8, minWin=26, winSum=443
1668 11:16:31.546158 TX Vref=24, minBit 9, minWin=27, winSum=448
1669 11:16:31.549236 TX Vref=26, minBit 9, minWin=27, winSum=450
1670 11:16:31.551979 TX Vref=28, minBit 10, minWin=27, winSum=452
1671 11:16:31.555591 TX Vref=30, minBit 8, minWin=27, winSum=451
1672 11:16:31.562027 TX Vref=32, minBit 0, minWin=27, winSum=446
1673 11:16:31.565952 [TxChooseVref] Worse bit 10, Min win 27, Win sum 452, Final Vref 28
1674 11:16:31.566057
1675 11:16:31.568968 Final TX Range 1 Vref 28
1676 11:16:31.569054
1677 11:16:31.569120 ==
1678 11:16:31.571791 Dram Type= 6, Freq= 0, CH_1, rank 0
1679 11:16:31.575204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1680 11:16:31.578539 ==
1681 11:16:31.578630
1682 11:16:31.578696
1683 11:16:31.578756 TX Vref Scan disable
1684 11:16:31.582293 == TX Byte 0 ==
1685 11:16:31.585513 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1686 11:16:31.592374 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1687 11:16:31.592477 == TX Byte 1 ==
1688 11:16:31.595579 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1689 11:16:31.602273 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1690 11:16:31.602384
1691 11:16:31.602455 [DATLAT]
1692 11:16:31.602517 Freq=800, CH1 RK0
1693 11:16:31.602577
1694 11:16:31.605405 DATLAT Default: 0xa
1695 11:16:31.605489 0, 0xFFFF, sum = 0
1696 11:16:31.608641 1, 0xFFFF, sum = 0
1697 11:16:31.611893 2, 0xFFFF, sum = 0
1698 11:16:31.611981 3, 0xFFFF, sum = 0
1699 11:16:31.615079 4, 0xFFFF, sum = 0
1700 11:16:31.615165 5, 0xFFFF, sum = 0
1701 11:16:31.618954 6, 0xFFFF, sum = 0
1702 11:16:31.619042 7, 0xFFFF, sum = 0
1703 11:16:31.621835 8, 0xFFFF, sum = 0
1704 11:16:31.621922 9, 0x0, sum = 1
1705 11:16:31.625610 10, 0x0, sum = 2
1706 11:16:31.625700 11, 0x0, sum = 3
1707 11:16:31.625768 12, 0x0, sum = 4
1708 11:16:31.628719 best_step = 10
1709 11:16:31.628806
1710 11:16:31.628872 ==
1711 11:16:31.631972 Dram Type= 6, Freq= 0, CH_1, rank 0
1712 11:16:31.635666 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1713 11:16:31.635755 ==
1714 11:16:31.638265 RX Vref Scan: 1
1715 11:16:31.638355
1716 11:16:31.641650 Set Vref Range= 32 -> 127
1717 11:16:31.641738
1718 11:16:31.641804 RX Vref 32 -> 127, step: 1
1719 11:16:31.641864
1720 11:16:31.645395 RX Delay -95 -> 252, step: 8
1721 11:16:31.645494
1722 11:16:31.648722 Set Vref, RX VrefLevel [Byte0]: 32
1723 11:16:31.651896 [Byte1]: 32
1724 11:16:31.651983
1725 11:16:31.655039 Set Vref, RX VrefLevel [Byte0]: 33
1726 11:16:31.658386 [Byte1]: 33
1727 11:16:31.662715
1728 11:16:31.662808 Set Vref, RX VrefLevel [Byte0]: 34
1729 11:16:31.665730 [Byte1]: 34
1730 11:16:31.669916
1731 11:16:31.670012 Set Vref, RX VrefLevel [Byte0]: 35
1732 11:16:31.673576 [Byte1]: 35
1733 11:16:31.678720
1734 11:16:31.678831 Set Vref, RX VrefLevel [Byte0]: 36
1735 11:16:31.681298 [Byte1]: 36
1736 11:16:31.685444
1737 11:16:31.685534 Set Vref, RX VrefLevel [Byte0]: 37
1738 11:16:31.688714 [Byte1]: 37
1739 11:16:31.692795
1740 11:16:31.692884 Set Vref, RX VrefLevel [Byte0]: 38
1741 11:16:31.696198 [Byte1]: 38
1742 11:16:31.700579
1743 11:16:31.700664 Set Vref, RX VrefLevel [Byte0]: 39
1744 11:16:31.704044 [Byte1]: 39
1745 11:16:31.708248
1746 11:16:31.708342 Set Vref, RX VrefLevel [Byte0]: 40
1747 11:16:31.711576 [Byte1]: 40
1748 11:16:31.715875
1749 11:16:31.715992 Set Vref, RX VrefLevel [Byte0]: 41
1750 11:16:31.719275 [Byte1]: 41
1751 11:16:31.723946
1752 11:16:31.724036 Set Vref, RX VrefLevel [Byte0]: 42
1753 11:16:31.726640 [Byte1]: 42
1754 11:16:31.731281
1755 11:16:31.731372 Set Vref, RX VrefLevel [Byte0]: 43
1756 11:16:31.734816 [Byte1]: 43
1757 11:16:31.738331
1758 11:16:31.738443 Set Vref, RX VrefLevel [Byte0]: 44
1759 11:16:31.742015 [Byte1]: 44
1760 11:16:31.746340
1761 11:16:31.746431 Set Vref, RX VrefLevel [Byte0]: 45
1762 11:16:31.749332 [Byte1]: 45
1763 11:16:31.753609
1764 11:16:31.753752 Set Vref, RX VrefLevel [Byte0]: 46
1765 11:16:31.757978 [Byte1]: 46
1766 11:16:31.761224
1767 11:16:31.761310 Set Vref, RX VrefLevel [Byte0]: 47
1768 11:16:31.764789 [Byte1]: 47
1769 11:16:31.768758
1770 11:16:31.768846 Set Vref, RX VrefLevel [Byte0]: 48
1771 11:16:31.772297 [Byte1]: 48
1772 11:16:31.776491
1773 11:16:31.776618 Set Vref, RX VrefLevel [Byte0]: 49
1774 11:16:31.780144 [Byte1]: 49
1775 11:16:31.783907
1776 11:16:31.783996 Set Vref, RX VrefLevel [Byte0]: 50
1777 11:16:31.788939 [Byte1]: 50
1778 11:16:31.791640
1779 11:16:31.791746 Set Vref, RX VrefLevel [Byte0]: 51
1780 11:16:31.794748 [Byte1]: 51
1781 11:16:31.799489
1782 11:16:31.799577 Set Vref, RX VrefLevel [Byte0]: 52
1783 11:16:31.802467 [Byte1]: 52
1784 11:16:31.806775
1785 11:16:31.806862 Set Vref, RX VrefLevel [Byte0]: 53
1786 11:16:31.810507 [Byte1]: 53
1787 11:16:31.814708
1788 11:16:31.814796 Set Vref, RX VrefLevel [Byte0]: 54
1789 11:16:31.817767 [Byte1]: 54
1790 11:16:31.822166
1791 11:16:31.822323 Set Vref, RX VrefLevel [Byte0]: 55
1792 11:16:31.825440 [Byte1]: 55
1793 11:16:31.829429
1794 11:16:31.829515 Set Vref, RX VrefLevel [Byte0]: 56
1795 11:16:31.832805 [Byte1]: 56
1796 11:16:31.837085
1797 11:16:31.837174 Set Vref, RX VrefLevel [Byte0]: 57
1798 11:16:31.840459 [Byte1]: 57
1799 11:16:31.845079
1800 11:16:31.845174 Set Vref, RX VrefLevel [Byte0]: 58
1801 11:16:31.848433 [Byte1]: 58
1802 11:16:31.852190
1803 11:16:31.852278 Set Vref, RX VrefLevel [Byte0]: 59
1804 11:16:31.855548 [Byte1]: 59
1805 11:16:31.860254
1806 11:16:31.860347 Set Vref, RX VrefLevel [Byte0]: 60
1807 11:16:31.863315 [Byte1]: 60
1808 11:16:31.867841
1809 11:16:31.867930 Set Vref, RX VrefLevel [Byte0]: 61
1810 11:16:31.870914 [Byte1]: 61
1811 11:16:31.875304
1812 11:16:31.875396 Set Vref, RX VrefLevel [Byte0]: 62
1813 11:16:31.878427 [Byte1]: 62
1814 11:16:31.883150
1815 11:16:31.883240 Set Vref, RX VrefLevel [Byte0]: 63
1816 11:16:31.886196 [Byte1]: 63
1817 11:16:31.890471
1818 11:16:31.890563 Set Vref, RX VrefLevel [Byte0]: 64
1819 11:16:31.893905 [Byte1]: 64
1820 11:16:31.898136
1821 11:16:31.898231 Set Vref, RX VrefLevel [Byte0]: 65
1822 11:16:31.901051 [Byte1]: 65
1823 11:16:31.905486
1824 11:16:31.905575 Set Vref, RX VrefLevel [Byte0]: 66
1825 11:16:31.908939 [Byte1]: 66
1826 11:16:31.913160
1827 11:16:31.913249 Set Vref, RX VrefLevel [Byte0]: 67
1828 11:16:31.916373 [Byte1]: 67
1829 11:16:31.921180
1830 11:16:31.921272 Set Vref, RX VrefLevel [Byte0]: 68
1831 11:16:31.924357 [Byte1]: 68
1832 11:16:31.928540
1833 11:16:31.928657 Set Vref, RX VrefLevel [Byte0]: 69
1834 11:16:31.931988 [Byte1]: 69
1835 11:16:31.936242
1836 11:16:31.936336 Set Vref, RX VrefLevel [Byte0]: 70
1837 11:16:31.939261 [Byte1]: 70
1838 11:16:31.943470
1839 11:16:31.943569 Set Vref, RX VrefLevel [Byte0]: 71
1840 11:16:31.947024 [Byte1]: 71
1841 11:16:31.951183
1842 11:16:31.951276 Set Vref, RX VrefLevel [Byte0]: 72
1843 11:16:31.954591 [Byte1]: 72
1844 11:16:31.958586
1845 11:16:31.958676 Set Vref, RX VrefLevel [Byte0]: 73
1846 11:16:31.962299 [Byte1]: 73
1847 11:16:31.966202
1848 11:16:31.969550 Set Vref, RX VrefLevel [Byte0]: 74
1849 11:16:31.972746 [Byte1]: 74
1850 11:16:31.972837
1851 11:16:31.976162 Final RX Vref Byte 0 = 55 to rank0
1852 11:16:31.979442 Final RX Vref Byte 1 = 63 to rank0
1853 11:16:31.984000 Final RX Vref Byte 0 = 55 to rank1
1854 11:16:31.986199 Final RX Vref Byte 1 = 63 to rank1==
1855 11:16:31.989337 Dram Type= 6, Freq= 0, CH_1, rank 0
1856 11:16:31.993295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1857 11:16:31.993392 ==
1858 11:16:31.993478 DQS Delay:
1859 11:16:31.996377 DQS0 = 0, DQS1 = 0
1860 11:16:31.996461 DQM Delay:
1861 11:16:31.999321 DQM0 = 86, DQM1 = 79
1862 11:16:31.999405 DQ Delay:
1863 11:16:32.002747 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1864 11:16:32.005623 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =80
1865 11:16:32.009382 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1866 11:16:32.012708 DQ12 =88, DQ13 =84, DQ14 =88, DQ15 =88
1867 11:16:32.012797
1868 11:16:32.012879
1869 11:16:32.019057 [DQSOSCAuto] RK0, (LSB)MR18= 0x3521, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 396 ps
1870 11:16:32.022540 CH1 RK0: MR19=606, MR18=3521
1871 11:16:32.029523 CH1_RK0: MR19=0x606, MR18=0x3521, DQSOSC=396, MR23=63, INC=94, DEC=62
1872 11:16:32.029633
1873 11:16:32.032136 ----->DramcWriteLeveling(PI) begin...
1874 11:16:32.032222 ==
1875 11:16:32.035646 Dram Type= 6, Freq= 0, CH_1, rank 1
1876 11:16:32.042736 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1877 11:16:32.042880 ==
1878 11:16:32.046360 Write leveling (Byte 0): 27 => 27
1879 11:16:32.046451 Write leveling (Byte 1): 33 => 33
1880 11:16:32.049035 DramcWriteLeveling(PI) end<-----
1881 11:16:32.049120
1882 11:16:32.049203 ==
1883 11:16:32.052239 Dram Type= 6, Freq= 0, CH_1, rank 1
1884 11:16:32.058715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1885 11:16:32.058814 ==
1886 11:16:32.062255 [Gating] SW mode calibration
1887 11:16:32.068741 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1888 11:16:32.072017 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1889 11:16:32.078617 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1890 11:16:32.081866 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1891 11:16:32.085439 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1892 11:16:32.092135 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1893 11:16:32.095079 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1894 11:16:32.098356 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1895 11:16:32.105290 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1896 11:16:32.108740 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1897 11:16:32.111739 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1898 11:16:32.118314 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1899 11:16:32.121448 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 11:16:32.125197 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 11:16:32.131866 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 11:16:32.135159 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 11:16:32.138099 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 11:16:32.145361 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 11:16:32.148304 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1906 11:16:32.151957 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1907 11:16:32.155290 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
1908 11:16:32.161990 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1909 11:16:32.165469 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1910 11:16:32.168407 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1911 11:16:32.175509 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1912 11:16:32.178270 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1913 11:16:32.181427 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1914 11:16:32.187993 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1915 11:16:32.191430 0 9 8 | B1->B0 | 3030 2726 | 1 1 | (1 1) (0 0)
1916 11:16:32.194449 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1917 11:16:32.201293 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1918 11:16:32.204500 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1919 11:16:32.207923 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1920 11:16:32.214693 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1921 11:16:32.218380 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1922 11:16:32.221231 0 10 4 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 1)
1923 11:16:32.227711 0 10 8 | B1->B0 | 2424 2e2e | 0 0 | (1 0) (0 0)
1924 11:16:32.231271 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1925 11:16:32.234364 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1926 11:16:32.241202 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1927 11:16:32.244219 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1928 11:16:32.247654 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1929 11:16:32.254408 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1930 11:16:32.257531 0 11 4 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
1931 11:16:32.260892 0 11 8 | B1->B0 | 4242 3737 | 0 0 | (0 0) (0 0)
1932 11:16:32.267515 0 11 12 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
1933 11:16:32.271079 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1934 11:16:32.274493 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1935 11:16:32.280932 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1936 11:16:32.284430 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1937 11:16:32.287660 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1938 11:16:32.294049 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1939 11:16:32.297462 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1940 11:16:32.301287 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1941 11:16:32.307655 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1942 11:16:32.311299 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1943 11:16:32.314181 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1944 11:16:32.317292 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1945 11:16:32.324272 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1946 11:16:32.327882 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1947 11:16:32.330699 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1948 11:16:32.337571 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1949 11:16:32.340666 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1950 11:16:32.344040 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1951 11:16:32.351344 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1952 11:16:32.354267 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1953 11:16:32.357428 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1954 11:16:32.364087 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1955 11:16:32.367450 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1956 11:16:32.370868 Total UI for P1: 0, mck2ui 16
1957 11:16:32.374339 best dqsien dly found for B0: ( 0, 14, 4)
1958 11:16:32.377203 Total UI for P1: 0, mck2ui 16
1959 11:16:32.380431 best dqsien dly found for B1: ( 0, 14, 4)
1960 11:16:32.384061 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1961 11:16:32.387172 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1962 11:16:32.387264
1963 11:16:32.390286 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1964 11:16:32.393838 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1965 11:16:32.397411 [Gating] SW calibration Done
1966 11:16:32.397504 ==
1967 11:16:32.400660 Dram Type= 6, Freq= 0, CH_1, rank 1
1968 11:16:32.403881 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1969 11:16:32.407061 ==
1970 11:16:32.407163 RX Vref Scan: 0
1971 11:16:32.407227
1972 11:16:32.410492 RX Vref 0 -> 0, step: 1
1973 11:16:32.410578
1974 11:16:32.414101 RX Delay -130 -> 252, step: 16
1975 11:16:32.416995 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1976 11:16:32.420211 iDelay=222, Bit 1, Center 77 (-34 ~ 189) 224
1977 11:16:32.423768 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1978 11:16:32.427023 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1979 11:16:32.433397 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1980 11:16:32.437020 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1981 11:16:32.440073 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1982 11:16:32.443648 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1983 11:16:32.446797 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1984 11:16:32.453392 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1985 11:16:32.456557 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1986 11:16:32.460199 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1987 11:16:32.463316 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1988 11:16:32.470218 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1989 11:16:32.473590 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1990 11:16:32.477170 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1991 11:16:32.477258 ==
1992 11:16:32.480093 Dram Type= 6, Freq= 0, CH_1, rank 1
1993 11:16:32.483294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1994 11:16:32.483381 ==
1995 11:16:32.487256 DQS Delay:
1996 11:16:32.487344 DQS0 = 0, DQS1 = 0
1997 11:16:32.487410 DQM Delay:
1998 11:16:32.490202 DQM0 = 86, DQM1 = 78
1999 11:16:32.490285 DQ Delay:
2000 11:16:32.494354 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =85
2001 11:16:32.496710 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
2002 11:16:32.499906 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
2003 11:16:32.503734 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
2004 11:16:32.503824
2005 11:16:32.503889
2006 11:16:32.506822 ==
2007 11:16:32.506906 Dram Type= 6, Freq= 0, CH_1, rank 1
2008 11:16:32.513416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2009 11:16:32.513572 ==
2010 11:16:32.513651
2011 11:16:32.513711
2012 11:16:32.516422 TX Vref Scan disable
2013 11:16:32.516505 == TX Byte 0 ==
2014 11:16:32.519622 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2015 11:16:32.526577 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2016 11:16:32.526695 == TX Byte 1 ==
2017 11:16:32.529608 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
2018 11:16:32.536391 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
2019 11:16:32.536510 ==
2020 11:16:32.539871 Dram Type= 6, Freq= 0, CH_1, rank 1
2021 11:16:32.542638 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2022 11:16:32.542744 ==
2023 11:16:32.556641 TX Vref=22, minBit 8, minWin=26, winSum=443
2024 11:16:32.560630 TX Vref=24, minBit 8, minWin=26, winSum=448
2025 11:16:32.563719 TX Vref=26, minBit 0, minWin=28, winSum=452
2026 11:16:32.566504 TX Vref=28, minBit 10, minWin=27, winSum=453
2027 11:16:32.570175 TX Vref=30, minBit 13, minWin=27, winSum=450
2028 11:16:32.576736 TX Vref=32, minBit 8, minWin=27, winSum=448
2029 11:16:32.580046 [TxChooseVref] Worse bit 0, Min win 28, Win sum 452, Final Vref 26
2030 11:16:32.580158
2031 11:16:32.583630 Final TX Range 1 Vref 26
2032 11:16:32.583716
2033 11:16:32.583780 ==
2034 11:16:32.587540 Dram Type= 6, Freq= 0, CH_1, rank 1
2035 11:16:32.590063 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2036 11:16:32.590148 ==
2037 11:16:32.590213
2038 11:16:32.593201
2039 11:16:32.593285 TX Vref Scan disable
2040 11:16:32.596866 == TX Byte 0 ==
2041 11:16:32.600531 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
2042 11:16:32.603355 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
2043 11:16:32.606670 == TX Byte 1 ==
2044 11:16:32.610368 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
2045 11:16:32.616890 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
2046 11:16:32.616998
2047 11:16:32.617067 [DATLAT]
2048 11:16:32.617126 Freq=800, CH1 RK1
2049 11:16:32.617185
2050 11:16:32.620040 DATLAT Default: 0xa
2051 11:16:32.620140 0, 0xFFFF, sum = 0
2052 11:16:32.623622 1, 0xFFFF, sum = 0
2053 11:16:32.623710 2, 0xFFFF, sum = 0
2054 11:16:32.626687 3, 0xFFFF, sum = 0
2055 11:16:32.630440 4, 0xFFFF, sum = 0
2056 11:16:32.630529 5, 0xFFFF, sum = 0
2057 11:16:32.633710 6, 0xFFFF, sum = 0
2058 11:16:32.633795 7, 0xFFFF, sum = 0
2059 11:16:32.636675 8, 0xFFFF, sum = 0
2060 11:16:32.636759 9, 0x0, sum = 1
2061 11:16:32.636824 10, 0x0, sum = 2
2062 11:16:32.640376 11, 0x0, sum = 3
2063 11:16:32.640461 12, 0x0, sum = 4
2064 11:16:32.643142 best_step = 10
2065 11:16:32.643225
2066 11:16:32.643289 ==
2067 11:16:32.646465 Dram Type= 6, Freq= 0, CH_1, rank 1
2068 11:16:32.649743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2069 11:16:32.649830 ==
2070 11:16:32.653151 RX Vref Scan: 0
2071 11:16:32.653238
2072 11:16:32.653302 RX Vref 0 -> 0, step: 1
2073 11:16:32.656471
2074 11:16:32.656604 RX Delay -95 -> 252, step: 8
2075 11:16:32.663381 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2076 11:16:32.667001 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2077 11:16:32.670401 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2078 11:16:32.673279 iDelay=217, Bit 3, Center 84 (-23 ~ 192) 216
2079 11:16:32.676689 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2080 11:16:32.683332 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2081 11:16:32.686812 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2082 11:16:32.690025 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2083 11:16:32.693280 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2084 11:16:32.696707 iDelay=217, Bit 9, Center 72 (-39 ~ 184) 224
2085 11:16:32.703626 iDelay=217, Bit 10, Center 84 (-31 ~ 200) 232
2086 11:16:32.706586 iDelay=217, Bit 11, Center 72 (-39 ~ 184) 224
2087 11:16:32.709961 iDelay=217, Bit 12, Center 84 (-31 ~ 200) 232
2088 11:16:32.714138 iDelay=217, Bit 13, Center 84 (-31 ~ 200) 232
2089 11:16:32.719847 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2090 11:16:32.723574 iDelay=217, Bit 15, Center 88 (-31 ~ 208) 240
2091 11:16:32.723709 ==
2092 11:16:32.727111 Dram Type= 6, Freq= 0, CH_1, rank 1
2093 11:16:32.730291 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2094 11:16:32.730381 ==
2095 11:16:32.730447 DQS Delay:
2096 11:16:32.733137 DQS0 = 0, DQS1 = 0
2097 11:16:32.733219 DQM Delay:
2098 11:16:32.736810 DQM0 = 87, DQM1 = 79
2099 11:16:32.736895 DQ Delay:
2100 11:16:32.740383 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
2101 11:16:32.743080 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2102 11:16:32.746379 DQ8 =68, DQ9 =72, DQ10 =84, DQ11 =72
2103 11:16:32.749926 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
2104 11:16:32.750016
2105 11:16:32.750109
2106 11:16:32.759686 [DQSOSCAuto] RK1, (LSB)MR18= 0x160e, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 404 ps
2107 11:16:32.759809 CH1 RK1: MR19=606, MR18=160E
2108 11:16:32.766547 CH1_RK1: MR19=0x606, MR18=0x160E, DQSOSC=404, MR23=63, INC=90, DEC=60
2109 11:16:32.769981 [RxdqsGatingPostProcess] freq 800
2110 11:16:32.776437 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2111 11:16:32.779603 Pre-setting of DQS Precalculation
2112 11:16:32.782900 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2113 11:16:32.789368 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2114 11:16:32.800410 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2115 11:16:32.800575
2116 11:16:32.800681
2117 11:16:32.803093 [Calibration Summary] 1600 Mbps
2118 11:16:32.803179 CH 0, Rank 0
2119 11:16:32.805911 SW Impedance : PASS
2120 11:16:32.805999 DUTY Scan : NO K
2121 11:16:32.809897 ZQ Calibration : PASS
2122 11:16:32.812968 Jitter Meter : NO K
2123 11:16:32.813093 CBT Training : PASS
2124 11:16:32.815880 Write leveling : PASS
2125 11:16:32.819250 RX DQS gating : PASS
2126 11:16:32.819344 RX DQ/DQS(RDDQC) : PASS
2127 11:16:32.822528 TX DQ/DQS : PASS
2128 11:16:32.822616 RX DATLAT : PASS
2129 11:16:32.826123 RX DQ/DQS(Engine): PASS
2130 11:16:32.829297 TX OE : NO K
2131 11:16:32.829387 All Pass.
2132 11:16:32.829472
2133 11:16:32.829549 CH 0, Rank 1
2134 11:16:32.832742 SW Impedance : PASS
2135 11:16:32.835987 DUTY Scan : NO K
2136 11:16:32.836077 ZQ Calibration : PASS
2137 11:16:32.839942 Jitter Meter : NO K
2138 11:16:32.843521 CBT Training : PASS
2139 11:16:32.843618 Write leveling : PASS
2140 11:16:32.846018 RX DQS gating : PASS
2141 11:16:32.850102 RX DQ/DQS(RDDQC) : PASS
2142 11:16:32.850197 TX DQ/DQS : PASS
2143 11:16:32.852740 RX DATLAT : PASS
2144 11:16:32.855670 RX DQ/DQS(Engine): PASS
2145 11:16:32.855759 TX OE : NO K
2146 11:16:32.858993 All Pass.
2147 11:16:32.859081
2148 11:16:32.859166 CH 1, Rank 0
2149 11:16:32.862584 SW Impedance : PASS
2150 11:16:32.862672 DUTY Scan : NO K
2151 11:16:32.865847 ZQ Calibration : PASS
2152 11:16:32.869102 Jitter Meter : NO K
2153 11:16:32.869191 CBT Training : PASS
2154 11:16:32.872114 Write leveling : PASS
2155 11:16:32.876015 RX DQS gating : PASS
2156 11:16:32.876110 RX DQ/DQS(RDDQC) : PASS
2157 11:16:32.878816 TX DQ/DQS : PASS
2158 11:16:32.878902 RX DATLAT : PASS
2159 11:16:32.881967 RX DQ/DQS(Engine): PASS
2160 11:16:32.885795 TX OE : NO K
2161 11:16:32.885887 All Pass.
2162 11:16:32.885954
2163 11:16:32.886016 CH 1, Rank 1
2164 11:16:32.888853 SW Impedance : PASS
2165 11:16:32.892113 DUTY Scan : NO K
2166 11:16:32.892201 ZQ Calibration : PASS
2167 11:16:32.895346 Jitter Meter : NO K
2168 11:16:32.899162 CBT Training : PASS
2169 11:16:32.899253 Write leveling : PASS
2170 11:16:32.902008 RX DQS gating : PASS
2171 11:16:32.905340 RX DQ/DQS(RDDQC) : PASS
2172 11:16:32.905431 TX DQ/DQS : PASS
2173 11:16:32.908504 RX DATLAT : PASS
2174 11:16:32.912306 RX DQ/DQS(Engine): PASS
2175 11:16:32.912398 TX OE : NO K
2176 11:16:32.915325 All Pass.
2177 11:16:32.915411
2178 11:16:32.915476 DramC Write-DBI off
2179 11:16:32.918770 PER_BANK_REFRESH: Hybrid Mode
2180 11:16:32.918858 TX_TRACKING: ON
2181 11:16:32.921988 [GetDramInforAfterCalByMRR] Vendor 6.
2182 11:16:32.928563 [GetDramInforAfterCalByMRR] Revision 606.
2183 11:16:32.932086 [GetDramInforAfterCalByMRR] Revision 2 0.
2184 11:16:32.932182 MR0 0x3b3b
2185 11:16:32.932249 MR8 0x5151
2186 11:16:32.934962 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2187 11:16:32.938481
2188 11:16:32.938572 MR0 0x3b3b
2189 11:16:32.938637 MR8 0x5151
2190 11:16:32.941704 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2191 11:16:32.941824
2192 11:16:32.951974 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2193 11:16:32.954763 [FAST_K] Save calibration result to emmc
2194 11:16:32.958369 [FAST_K] Save calibration result to emmc
2195 11:16:32.961987 dram_init: config_dvfs: 1
2196 11:16:32.964900 dramc_set_vcore_voltage set vcore to 662500
2197 11:16:32.968052 Read voltage for 1200, 2
2198 11:16:32.968162 Vio18 = 0
2199 11:16:32.968240 Vcore = 662500
2200 11:16:32.971511 Vdram = 0
2201 11:16:32.971594 Vddq = 0
2202 11:16:32.971658 Vmddr = 0
2203 11:16:32.978049 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2204 11:16:32.981466 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2205 11:16:32.985092 MEM_TYPE=3, freq_sel=15
2206 11:16:32.988496 sv_algorithm_assistance_LP4_1600
2207 11:16:32.991351 ============ PULL DRAM RESETB DOWN ============
2208 11:16:32.994924 ========== PULL DRAM RESETB DOWN end =========
2209 11:16:33.001991 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2210 11:16:33.004480 ===================================
2211 11:16:33.008103 LPDDR4 DRAM CONFIGURATION
2212 11:16:33.011106 ===================================
2213 11:16:33.011196 EX_ROW_EN[0] = 0x0
2214 11:16:33.014863 EX_ROW_EN[1] = 0x0
2215 11:16:33.014952 LP4Y_EN = 0x0
2216 11:16:33.018111 WORK_FSP = 0x0
2217 11:16:33.018195 WL = 0x4
2218 11:16:33.021587 RL = 0x4
2219 11:16:33.021672 BL = 0x2
2220 11:16:33.024667 RPST = 0x0
2221 11:16:33.024752 RD_PRE = 0x0
2222 11:16:33.027762 WR_PRE = 0x1
2223 11:16:33.027844 WR_PST = 0x0
2224 11:16:33.031307 DBI_WR = 0x0
2225 11:16:33.031393 DBI_RD = 0x0
2226 11:16:33.034733 OTF = 0x1
2227 11:16:33.038288 ===================================
2228 11:16:33.041196 ===================================
2229 11:16:33.041285 ANA top config
2230 11:16:33.044540 ===================================
2231 11:16:33.047840 DLL_ASYNC_EN = 0
2232 11:16:33.051201 ALL_SLAVE_EN = 0
2233 11:16:33.054945 NEW_RANK_MODE = 1
2234 11:16:33.055037 DLL_IDLE_MODE = 1
2235 11:16:33.057768 LP45_APHY_COMB_EN = 1
2236 11:16:33.061563 TX_ODT_DIS = 1
2237 11:16:33.064581 NEW_8X_MODE = 1
2238 11:16:33.068184 ===================================
2239 11:16:33.071036 ===================================
2240 11:16:33.074242 data_rate = 2400
2241 11:16:33.077565 CKR = 1
2242 11:16:33.077654 DQ_P2S_RATIO = 8
2243 11:16:33.081105 ===================================
2244 11:16:33.084350 CA_P2S_RATIO = 8
2245 11:16:33.087828 DQ_CA_OPEN = 0
2246 11:16:33.090785 DQ_SEMI_OPEN = 0
2247 11:16:33.094223 CA_SEMI_OPEN = 0
2248 11:16:33.097366 CA_FULL_RATE = 0
2249 11:16:33.097455 DQ_CKDIV4_EN = 0
2250 11:16:33.100641 CA_CKDIV4_EN = 0
2251 11:16:33.104453 CA_PREDIV_EN = 0
2252 11:16:33.107658 PH8_DLY = 17
2253 11:16:33.110921 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2254 11:16:33.113908 DQ_AAMCK_DIV = 4
2255 11:16:33.113996 CA_AAMCK_DIV = 4
2256 11:16:33.117412 CA_ADMCK_DIV = 4
2257 11:16:33.120878 DQ_TRACK_CA_EN = 0
2258 11:16:33.123929 CA_PICK = 1200
2259 11:16:33.127758 CA_MCKIO = 1200
2260 11:16:33.131039 MCKIO_SEMI = 0
2261 11:16:33.134144 PLL_FREQ = 2366
2262 11:16:33.134270 DQ_UI_PI_RATIO = 32
2263 11:16:33.137288 CA_UI_PI_RATIO = 0
2264 11:16:33.140556 ===================================
2265 11:16:33.144189 ===================================
2266 11:16:33.147748 memory_type:LPDDR4
2267 11:16:33.150724 GP_NUM : 10
2268 11:16:33.150810 SRAM_EN : 1
2269 11:16:33.153891 MD32_EN : 0
2270 11:16:33.157082 ===================================
2271 11:16:33.160794 [ANA_INIT] >>>>>>>>>>>>>>
2272 11:16:33.160883 <<<<<< [CONFIGURE PHASE]: ANA_TX
2273 11:16:33.163853 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2274 11:16:33.167237 ===================================
2275 11:16:33.170518 data_rate = 2400,PCW = 0X5b00
2276 11:16:33.173791 ===================================
2277 11:16:33.176916 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2278 11:16:33.183915 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2279 11:16:33.190322 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2280 11:16:33.193442 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2281 11:16:33.197248 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2282 11:16:33.200848 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2283 11:16:33.203384 [ANA_INIT] flow start
2284 11:16:33.203470 [ANA_INIT] PLL >>>>>>>>
2285 11:16:33.207318 [ANA_INIT] PLL <<<<<<<<
2286 11:16:33.210349 [ANA_INIT] MIDPI >>>>>>>>
2287 11:16:33.213630 [ANA_INIT] MIDPI <<<<<<<<
2288 11:16:33.213716 [ANA_INIT] DLL >>>>>>>>
2289 11:16:33.217062 [ANA_INIT] DLL <<<<<<<<
2290 11:16:33.217146 [ANA_INIT] flow end
2291 11:16:33.223392 ============ LP4 DIFF to SE enter ============
2292 11:16:33.226883 ============ LP4 DIFF to SE exit ============
2293 11:16:33.230585 [ANA_INIT] <<<<<<<<<<<<<
2294 11:16:33.233413 [Flow] Enable top DCM control >>>>>
2295 11:16:33.236663 [Flow] Enable top DCM control <<<<<
2296 11:16:33.236750 Enable DLL master slave shuffle
2297 11:16:33.243509 ==============================================================
2298 11:16:33.246664 Gating Mode config
2299 11:16:33.250205 ==============================================================
2300 11:16:33.253356 Config description:
2301 11:16:33.263467 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2302 11:16:33.269931 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2303 11:16:33.273900 SELPH_MODE 0: By rank 1: By Phase
2304 11:16:33.279926 ==============================================================
2305 11:16:33.283172 GAT_TRACK_EN = 1
2306 11:16:33.286996 RX_GATING_MODE = 2
2307 11:16:33.290392 RX_GATING_TRACK_MODE = 2
2308 11:16:33.293174 SELPH_MODE = 1
2309 11:16:33.293262 PICG_EARLY_EN = 1
2310 11:16:33.296401 VALID_LAT_VALUE = 1
2311 11:16:33.302893 ==============================================================
2312 11:16:33.306694 Enter into Gating configuration >>>>
2313 11:16:33.310001 Exit from Gating configuration <<<<
2314 11:16:33.313088 Enter into DVFS_PRE_config >>>>>
2315 11:16:33.322823 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2316 11:16:33.326907 Exit from DVFS_PRE_config <<<<<
2317 11:16:33.329738 Enter into PICG configuration >>>>
2318 11:16:33.334371 Exit from PICG configuration <<<<
2319 11:16:33.336262 [RX_INPUT] configuration >>>>>
2320 11:16:33.339659 [RX_INPUT] configuration <<<<<
2321 11:16:33.342984 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2322 11:16:33.349245 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2323 11:16:33.356013 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2324 11:16:33.362894 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2325 11:16:33.369126 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2326 11:16:33.375626 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2327 11:16:33.378937 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2328 11:16:33.382149 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2329 11:16:33.385889 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2330 11:16:33.392722 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2331 11:16:33.395528 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2332 11:16:33.399027 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2333 11:16:33.402446 ===================================
2334 11:16:33.406024 LPDDR4 DRAM CONFIGURATION
2335 11:16:33.408724 ===================================
2336 11:16:33.408841 EX_ROW_EN[0] = 0x0
2337 11:16:33.411852 EX_ROW_EN[1] = 0x0
2338 11:16:33.415881 LP4Y_EN = 0x0
2339 11:16:33.415972 WORK_FSP = 0x0
2340 11:16:33.418900 WL = 0x4
2341 11:16:33.418986 RL = 0x4
2342 11:16:33.421838 BL = 0x2
2343 11:16:33.421920 RPST = 0x0
2344 11:16:33.425353 RD_PRE = 0x0
2345 11:16:33.425436 WR_PRE = 0x1
2346 11:16:33.428899 WR_PST = 0x0
2347 11:16:33.428985 DBI_WR = 0x0
2348 11:16:33.432232 DBI_RD = 0x0
2349 11:16:33.432316 OTF = 0x1
2350 11:16:33.435832 ===================================
2351 11:16:33.438513 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2352 11:16:33.445505 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2353 11:16:33.448606 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2354 11:16:33.451745 ===================================
2355 11:16:33.455308 LPDDR4 DRAM CONFIGURATION
2356 11:16:33.458570 ===================================
2357 11:16:33.458660 EX_ROW_EN[0] = 0x10
2358 11:16:33.461961 EX_ROW_EN[1] = 0x0
2359 11:16:33.462045 LP4Y_EN = 0x0
2360 11:16:33.464896 WORK_FSP = 0x0
2361 11:16:33.468378 WL = 0x4
2362 11:16:33.468470 RL = 0x4
2363 11:16:33.471654 BL = 0x2
2364 11:16:33.471738 RPST = 0x0
2365 11:16:33.474933 RD_PRE = 0x0
2366 11:16:33.475014 WR_PRE = 0x1
2367 11:16:33.478320 WR_PST = 0x0
2368 11:16:33.478400 DBI_WR = 0x0
2369 11:16:33.482174 DBI_RD = 0x0
2370 11:16:33.482257 OTF = 0x1
2371 11:16:33.485293 ===================================
2372 11:16:33.491910 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2373 11:16:33.492008 ==
2374 11:16:33.495319 Dram Type= 6, Freq= 0, CH_0, rank 0
2375 11:16:33.498479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2376 11:16:33.498564 ==
2377 11:16:33.501980 [Duty_Offset_Calibration]
2378 11:16:33.505335 B0:1 B1:-1 CA:0
2379 11:16:33.505422
2380 11:16:33.508356 [DutyScan_Calibration_Flow] k_type=0
2381 11:16:33.516472
2382 11:16:33.516620 ==CLK 0==
2383 11:16:33.519585 Final CLK duty delay cell = 0
2384 11:16:33.523239 [0] MAX Duty = 5125%(X100), DQS PI = 24
2385 11:16:33.526223 [0] MIN Duty = 4907%(X100), DQS PI = 8
2386 11:16:33.526307 [0] AVG Duty = 5016%(X100)
2387 11:16:33.529708
2388 11:16:33.532989 CH0 CLK Duty spec in!! Max-Min= 218%
2389 11:16:33.536124 [DutyScan_Calibration_Flow] ====Done====
2390 11:16:33.536208
2391 11:16:33.539231 [DutyScan_Calibration_Flow] k_type=1
2392 11:16:33.554936
2393 11:16:33.555077 ==DQS 0 ==
2394 11:16:33.558457 Final DQS duty delay cell = -4
2395 11:16:33.561736 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2396 11:16:33.565026 [-4] MIN Duty = 4875%(X100), DQS PI = 8
2397 11:16:33.568196 [-4] AVG Duty = 4968%(X100)
2398 11:16:33.568282
2399 11:16:33.568344 ==DQS 1 ==
2400 11:16:33.571697 Final DQS duty delay cell = 0
2401 11:16:33.574780 [0] MAX Duty = 5124%(X100), DQS PI = 4
2402 11:16:33.578135 [0] MIN Duty = 5031%(X100), DQS PI = 20
2403 11:16:33.581684 [0] AVG Duty = 5077%(X100)
2404 11:16:33.581770
2405 11:16:33.584932 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2406 11:16:33.585013
2407 11:16:33.588082 CH0 DQS 1 Duty spec in!! Max-Min= 93%
2408 11:16:33.591437 [DutyScan_Calibration_Flow] ====Done====
2409 11:16:33.591521
2410 11:16:33.594794 [DutyScan_Calibration_Flow] k_type=3
2411 11:16:33.612600
2412 11:16:33.612740 ==DQM 0 ==
2413 11:16:33.615543 Final DQM duty delay cell = 0
2414 11:16:33.618817 [0] MAX Duty = 5031%(X100), DQS PI = 18
2415 11:16:33.622047 [0] MIN Duty = 4875%(X100), DQS PI = 6
2416 11:16:33.625655 [0] AVG Duty = 4953%(X100)
2417 11:16:33.625747
2418 11:16:33.625810 ==DQM 1 ==
2419 11:16:33.628956 Final DQM duty delay cell = 4
2420 11:16:33.632114 [4] MAX Duty = 5187%(X100), DQS PI = 14
2421 11:16:33.635281 [4] MIN Duty = 5000%(X100), DQS PI = 24
2422 11:16:33.638796 [4] AVG Duty = 5093%(X100)
2423 11:16:33.638910
2424 11:16:33.642077 CH0 DQM 0 Duty spec in!! Max-Min= 156%
2425 11:16:33.642162
2426 11:16:33.645852 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2427 11:16:33.648452 [DutyScan_Calibration_Flow] ====Done====
2428 11:16:33.648859
2429 11:16:33.652356 [DutyScan_Calibration_Flow] k_type=2
2430 11:16:33.667908
2431 11:16:33.668042 ==DQ 0 ==
2432 11:16:33.671467 Final DQ duty delay cell = -4
2433 11:16:33.674516 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2434 11:16:33.677902 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2435 11:16:33.681549 [-4] AVG Duty = 4969%(X100)
2436 11:16:33.681662
2437 11:16:33.681744 ==DQ 1 ==
2438 11:16:33.685072 Final DQ duty delay cell = 0
2439 11:16:33.687866 [0] MAX Duty = 5093%(X100), DQS PI = 4
2440 11:16:33.691412 [0] MIN Duty = 4969%(X100), DQS PI = 40
2441 11:16:33.694416 [0] AVG Duty = 5031%(X100)
2442 11:16:33.694508
2443 11:16:33.697613 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2444 11:16:33.697715
2445 11:16:33.700934 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2446 11:16:33.704217 [DutyScan_Calibration_Flow] ====Done====
2447 11:16:33.704324 ==
2448 11:16:33.708297 Dram Type= 6, Freq= 0, CH_1, rank 0
2449 11:16:33.711105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2450 11:16:33.711211 ==
2451 11:16:33.714386 [Duty_Offset_Calibration]
2452 11:16:33.714492 B0:-1 B1:1 CA:2
2453 11:16:33.714573
2454 11:16:33.718007 [DutyScan_Calibration_Flow] k_type=0
2455 11:16:33.728320
2456 11:16:33.728456 ==CLK 0==
2457 11:16:33.731580 Final CLK duty delay cell = 0
2458 11:16:33.734968 [0] MAX Duty = 5156%(X100), DQS PI = 22
2459 11:16:33.738121 [0] MIN Duty = 4969%(X100), DQS PI = 60
2460 11:16:33.738218 [0] AVG Duty = 5062%(X100)
2461 11:16:33.741760
2462 11:16:33.745043 CH1 CLK Duty spec in!! Max-Min= 187%
2463 11:16:33.748137 [DutyScan_Calibration_Flow] ====Done====
2464 11:16:33.748233
2465 11:16:33.751469 [DutyScan_Calibration_Flow] k_type=1
2466 11:16:33.767692
2467 11:16:33.767837 ==DQS 0 ==
2468 11:16:33.771042 Final DQS duty delay cell = 0
2469 11:16:33.774061 [0] MAX Duty = 5125%(X100), DQS PI = 16
2470 11:16:33.777789 [0] MIN Duty = 4938%(X100), DQS PI = 6
2471 11:16:33.781128 [0] AVG Duty = 5031%(X100)
2472 11:16:33.781221
2473 11:16:33.781284 ==DQS 1 ==
2474 11:16:33.784164 Final DQS duty delay cell = 0
2475 11:16:33.787435 [0] MAX Duty = 5094%(X100), DQS PI = 12
2476 11:16:33.790648 [0] MIN Duty = 4969%(X100), DQS PI = 56
2477 11:16:33.794026 [0] AVG Duty = 5031%(X100)
2478 11:16:33.794116
2479 11:16:33.797496 CH1 DQS 0 Duty spec in!! Max-Min= 187%
2480 11:16:33.797583
2481 11:16:33.800670 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2482 11:16:33.804029 [DutyScan_Calibration_Flow] ====Done====
2483 11:16:33.804117
2484 11:16:33.807611 [DutyScan_Calibration_Flow] k_type=3
2485 11:16:33.823296
2486 11:16:33.823436 ==DQM 0 ==
2487 11:16:33.826703 Final DQM duty delay cell = -4
2488 11:16:33.830008 [-4] MAX Duty = 5062%(X100), DQS PI = 36
2489 11:16:33.833151 [-4] MIN Duty = 4876%(X100), DQS PI = 6
2490 11:16:33.836697 [-4] AVG Duty = 4969%(X100)
2491 11:16:33.836791
2492 11:16:33.836859 ==DQM 1 ==
2493 11:16:33.840029 Final DQM duty delay cell = 0
2494 11:16:33.843290 [0] MAX Duty = 5187%(X100), DQS PI = 6
2495 11:16:33.846885 [0] MIN Duty = 5000%(X100), DQS PI = 28
2496 11:16:33.849671 [0] AVG Duty = 5093%(X100)
2497 11:16:33.849762
2498 11:16:33.853725 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2499 11:16:33.853816
2500 11:16:33.856647 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2501 11:16:33.860297 [DutyScan_Calibration_Flow] ====Done====
2502 11:16:33.860387
2503 11:16:33.863100 [DutyScan_Calibration_Flow] k_type=2
2504 11:16:33.879982
2505 11:16:33.880117 ==DQ 0 ==
2506 11:16:33.883291 Final DQ duty delay cell = 0
2507 11:16:33.886872 [0] MAX Duty = 5187%(X100), DQS PI = 30
2508 11:16:33.890041 [0] MIN Duty = 4907%(X100), DQS PI = 8
2509 11:16:33.890132 [0] AVG Duty = 5047%(X100)
2510 11:16:33.890199
2511 11:16:33.892988 ==DQ 1 ==
2512 11:16:33.896430 Final DQ duty delay cell = 0
2513 11:16:33.900080 [0] MAX Duty = 5124%(X100), DQS PI = 10
2514 11:16:33.903291 [0] MIN Duty = 4969%(X100), DQS PI = 0
2515 11:16:33.903382 [0] AVG Duty = 5046%(X100)
2516 11:16:33.903449
2517 11:16:33.906464 CH1 DQ 0 Duty spec in!! Max-Min= 280%
2518 11:16:33.906550
2519 11:16:33.909753 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2520 11:16:33.916956 [DutyScan_Calibration_Flow] ====Done====
2521 11:16:33.920168 nWR fixed to 30
2522 11:16:33.920265 [ModeRegInit_LP4] CH0 RK0
2523 11:16:33.924199 [ModeRegInit_LP4] CH0 RK1
2524 11:16:33.926613 [ModeRegInit_LP4] CH1 RK0
2525 11:16:33.926703 [ModeRegInit_LP4] CH1 RK1
2526 11:16:33.929957 match AC timing 7
2527 11:16:33.933213 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2528 11:16:33.936428 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2529 11:16:33.943682 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2530 11:16:33.946472 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2531 11:16:33.953252 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2532 11:16:33.953370 ==
2533 11:16:33.956729 Dram Type= 6, Freq= 0, CH_0, rank 0
2534 11:16:33.959748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2535 11:16:33.959838 ==
2536 11:16:33.966331 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2537 11:16:33.972507 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2538 11:16:33.980428 [CA 0] Center 39 (9~70) winsize 62
2539 11:16:33.983033 [CA 1] Center 39 (9~69) winsize 61
2540 11:16:33.986411 [CA 2] Center 35 (5~66) winsize 62
2541 11:16:33.990149 [CA 3] Center 35 (5~66) winsize 62
2542 11:16:33.993022 [CA 4] Center 33 (4~63) winsize 60
2543 11:16:33.996100 [CA 5] Center 33 (3~63) winsize 61
2544 11:16:33.996188
2545 11:16:34.000033 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2546 11:16:34.000119
2547 11:16:34.003111 [CATrainingPosCal] consider 1 rank data
2548 11:16:34.006677 u2DelayCellTimex100 = 270/100 ps
2549 11:16:34.010031 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2550 11:16:34.016261 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2551 11:16:34.019574 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2552 11:16:34.022835 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2553 11:16:34.026409 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2554 11:16:34.029412 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2555 11:16:34.029503
2556 11:16:34.033236 CA PerBit enable=1, Macro0, CA PI delay=33
2557 11:16:34.033326
2558 11:16:34.036218 [CBTSetCACLKResult] CA Dly = 33
2559 11:16:34.036299 CS Dly: 8 (0~39)
2560 11:16:34.039093 ==
2561 11:16:34.042752 Dram Type= 6, Freq= 0, CH_0, rank 1
2562 11:16:34.046105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2563 11:16:34.046201 ==
2564 11:16:34.049148 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2565 11:16:34.056173 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2566 11:16:34.065693 [CA 0] Center 39 (8~70) winsize 63
2567 11:16:34.068712 [CA 1] Center 39 (9~70) winsize 62
2568 11:16:34.071966 [CA 2] Center 35 (5~66) winsize 62
2569 11:16:34.075642 [CA 3] Center 34 (4~65) winsize 62
2570 11:16:34.079336 [CA 4] Center 33 (3~64) winsize 62
2571 11:16:34.082505 [CA 5] Center 33 (3~63) winsize 61
2572 11:16:34.082601
2573 11:16:34.085479 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2574 11:16:34.085565
2575 11:16:34.088508 [CATrainingPosCal] consider 2 rank data
2576 11:16:34.091835 u2DelayCellTimex100 = 270/100 ps
2577 11:16:34.095666 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2578 11:16:34.102168 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2579 11:16:34.105494 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2580 11:16:34.109053 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2581 11:16:34.112244 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2582 11:16:34.115402 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2583 11:16:34.115494
2584 11:16:34.118890 CA PerBit enable=1, Macro0, CA PI delay=33
2585 11:16:34.118977
2586 11:16:34.121876 [CBTSetCACLKResult] CA Dly = 33
2587 11:16:34.121960 CS Dly: 8 (0~40)
2588 11:16:34.125051
2589 11:16:34.128684 ----->DramcWriteLeveling(PI) begin...
2590 11:16:34.128776 ==
2591 11:16:34.131781 Dram Type= 6, Freq= 0, CH_0, rank 0
2592 11:16:34.134999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2593 11:16:34.135090 ==
2594 11:16:34.138685 Write leveling (Byte 0): 35 => 35
2595 11:16:34.141661 Write leveling (Byte 1): 29 => 29
2596 11:16:34.144967 DramcWriteLeveling(PI) end<-----
2597 11:16:34.145060
2598 11:16:34.145123 ==
2599 11:16:34.148370 Dram Type= 6, Freq= 0, CH_0, rank 0
2600 11:16:34.152140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2601 11:16:34.152236 ==
2602 11:16:34.155206 [Gating] SW mode calibration
2603 11:16:34.161761 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2604 11:16:34.168706 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2605 11:16:34.171658 0 15 0 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
2606 11:16:34.175216 0 15 4 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
2607 11:16:34.181857 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2608 11:16:34.185123 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2609 11:16:34.188139 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2610 11:16:34.194594 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2611 11:16:34.198078 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2612 11:16:34.201579 0 15 28 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 0)
2613 11:16:34.207761 1 0 0 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
2614 11:16:34.211103 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2615 11:16:34.214550 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2616 11:16:34.221120 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2617 11:16:34.224442 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2618 11:16:34.228233 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2619 11:16:34.234279 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2620 11:16:34.237675 1 0 28 | B1->B0 | 2323 3c3c | 0 0 | (0 0) (0 0)
2621 11:16:34.240727 1 1 0 | B1->B0 | 2424 4646 | 0 0 | (0 0) (0 0)
2622 11:16:34.247905 1 1 4 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
2623 11:16:34.250872 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2624 11:16:34.254379 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2625 11:16:34.260767 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2626 11:16:34.264240 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2627 11:16:34.267656 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2628 11:16:34.274051 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2629 11:16:34.277203 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2630 11:16:34.282136 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2631 11:16:34.284259 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2632 11:16:34.290495 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2633 11:16:34.294427 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2634 11:16:34.297310 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2635 11:16:34.304002 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2636 11:16:34.307304 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2637 11:16:34.310348 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2638 11:16:34.317720 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2639 11:16:34.320736 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2640 11:16:34.323583 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2641 11:16:34.330259 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2642 11:16:34.333526 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2643 11:16:34.336883 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2644 11:16:34.343641 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2645 11:16:34.346891 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2646 11:16:34.350311 Total UI for P1: 0, mck2ui 16
2647 11:16:34.353536 best dqsien dly found for B0: ( 1, 3, 26)
2648 11:16:34.356903 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2649 11:16:34.363751 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2650 11:16:34.363861 Total UI for P1: 0, mck2ui 16
2651 11:16:34.370478 best dqsien dly found for B1: ( 1, 4, 2)
2652 11:16:34.373848 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2653 11:16:34.377253 best DQS1 dly(MCK, UI, PI) = (1, 4, 2)
2654 11:16:34.377348
2655 11:16:34.380084 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2656 11:16:34.383329 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 2)
2657 11:16:34.386990 [Gating] SW calibration Done
2658 11:16:34.387081 ==
2659 11:16:34.389851 Dram Type= 6, Freq= 0, CH_0, rank 0
2660 11:16:34.393407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2661 11:16:34.393496 ==
2662 11:16:34.396382 RX Vref Scan: 0
2663 11:16:34.396465
2664 11:16:34.396558 RX Vref 0 -> 0, step: 1
2665 11:16:34.396650
2666 11:16:34.400136 RX Delay -40 -> 252, step: 8
2667 11:16:34.403379 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2668 11:16:34.409778 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2669 11:16:34.413050 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2670 11:16:34.416461 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2671 11:16:34.419878 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2672 11:16:34.423322 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2673 11:16:34.429650 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2674 11:16:34.432972 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2675 11:16:34.436197 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2676 11:16:34.440448 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2677 11:16:34.443083 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2678 11:16:34.449381 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2679 11:16:34.453108 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2680 11:16:34.455873 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2681 11:16:34.459799 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2682 11:16:34.465911 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2683 11:16:34.466015 ==
2684 11:16:34.469918 Dram Type= 6, Freq= 0, CH_0, rank 0
2685 11:16:34.472661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2686 11:16:34.472749 ==
2687 11:16:34.472813 DQS Delay:
2688 11:16:34.475878 DQS0 = 0, DQS1 = 0
2689 11:16:34.475971 DQM Delay:
2690 11:16:34.479344 DQM0 = 119, DQM1 = 107
2691 11:16:34.479427 DQ Delay:
2692 11:16:34.482730 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2693 11:16:34.486034 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =123
2694 11:16:34.489579 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2695 11:16:34.493044 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2696 11:16:34.493154
2697 11:16:34.493234
2698 11:16:34.493322 ==
2699 11:16:34.495939 Dram Type= 6, Freq= 0, CH_0, rank 0
2700 11:16:34.502706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2701 11:16:34.502804 ==
2702 11:16:34.502870
2703 11:16:34.502929
2704 11:16:34.502986 TX Vref Scan disable
2705 11:16:34.506456 == TX Byte 0 ==
2706 11:16:34.509733 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2707 11:16:34.516490 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2708 11:16:34.516596 == TX Byte 1 ==
2709 11:16:34.519343 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2710 11:16:34.525967 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2711 11:16:34.526066 ==
2712 11:16:34.529417 Dram Type= 6, Freq= 0, CH_0, rank 0
2713 11:16:34.532703 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2714 11:16:34.532790 ==
2715 11:16:34.544760 TX Vref=22, minBit 7, minWin=25, winSum=418
2716 11:16:34.547732 TX Vref=24, minBit 7, minWin=25, winSum=424
2717 11:16:34.551599 TX Vref=26, minBit 13, minWin=26, winSum=433
2718 11:16:34.554623 TX Vref=28, minBit 0, minWin=27, winSum=439
2719 11:16:34.557847 TX Vref=30, minBit 0, minWin=27, winSum=436
2720 11:16:34.564313 TX Vref=32, minBit 4, minWin=26, winSum=431
2721 11:16:34.567882 [TxChooseVref] Worse bit 0, Min win 27, Win sum 439, Final Vref 28
2722 11:16:34.567978
2723 11:16:34.570895 Final TX Range 1 Vref 28
2724 11:16:34.570982
2725 11:16:34.571047 ==
2726 11:16:34.574208 Dram Type= 6, Freq= 0, CH_0, rank 0
2727 11:16:34.577570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2728 11:16:34.577662 ==
2729 11:16:34.581124
2730 11:16:34.581208
2731 11:16:34.581271 TX Vref Scan disable
2732 11:16:34.584300 == TX Byte 0 ==
2733 11:16:34.587759 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2734 11:16:34.591903 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2735 11:16:34.594504 == TX Byte 1 ==
2736 11:16:34.597779 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2737 11:16:34.604621 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2738 11:16:34.604729
2739 11:16:34.604794 [DATLAT]
2740 11:16:34.604853 Freq=1200, CH0 RK0
2741 11:16:34.604908
2742 11:16:34.607924 DATLAT Default: 0xd
2743 11:16:34.608007 0, 0xFFFF, sum = 0
2744 11:16:34.611084 1, 0xFFFF, sum = 0
2745 11:16:34.611169 2, 0xFFFF, sum = 0
2746 11:16:34.614413 3, 0xFFFF, sum = 0
2747 11:16:34.617632 4, 0xFFFF, sum = 0
2748 11:16:34.617719 5, 0xFFFF, sum = 0
2749 11:16:34.621006 6, 0xFFFF, sum = 0
2750 11:16:34.621090 7, 0xFFFF, sum = 0
2751 11:16:34.624935 8, 0xFFFF, sum = 0
2752 11:16:34.625021 9, 0xFFFF, sum = 0
2753 11:16:34.627542 10, 0xFFFF, sum = 0
2754 11:16:34.627626 11, 0xFFFF, sum = 0
2755 11:16:34.631463 12, 0x0, sum = 1
2756 11:16:34.631549 13, 0x0, sum = 2
2757 11:16:34.634238 14, 0x0, sum = 3
2758 11:16:34.634322 15, 0x0, sum = 4
2759 11:16:34.634387 best_step = 13
2760 11:16:34.637524
2761 11:16:34.637628 ==
2762 11:16:34.641475 Dram Type= 6, Freq= 0, CH_0, rank 0
2763 11:16:34.644455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2764 11:16:34.644600 ==
2765 11:16:34.644666 RX Vref Scan: 1
2766 11:16:34.644726
2767 11:16:34.647308 Set Vref Range= 32 -> 127
2768 11:16:34.647391
2769 11:16:34.650665 RX Vref 32 -> 127, step: 1
2770 11:16:34.650750
2771 11:16:34.654198 RX Delay -21 -> 252, step: 4
2772 11:16:34.654282
2773 11:16:34.657493 Set Vref, RX VrefLevel [Byte0]: 32
2774 11:16:34.661388 [Byte1]: 32
2775 11:16:34.661478
2776 11:16:34.664372 Set Vref, RX VrefLevel [Byte0]: 33
2777 11:16:34.668088 [Byte1]: 33
2778 11:16:34.671523
2779 11:16:34.671610 Set Vref, RX VrefLevel [Byte0]: 34
2780 11:16:34.674117 [Byte1]: 34
2781 11:16:34.678821
2782 11:16:34.678912 Set Vref, RX VrefLevel [Byte0]: 35
2783 11:16:34.682412 [Byte1]: 35
2784 11:16:34.686634
2785 11:16:34.686724 Set Vref, RX VrefLevel [Byte0]: 36
2786 11:16:34.690229 [Byte1]: 36
2787 11:16:34.694705
2788 11:16:34.694823 Set Vref, RX VrefLevel [Byte0]: 37
2789 11:16:34.697865 [Byte1]: 37
2790 11:16:34.702931
2791 11:16:34.703011 Set Vref, RX VrefLevel [Byte0]: 38
2792 11:16:34.705794 [Byte1]: 38
2793 11:16:34.710701
2794 11:16:34.710796 Set Vref, RX VrefLevel [Byte0]: 39
2795 11:16:34.713794 [Byte1]: 39
2796 11:16:34.718904
2797 11:16:34.719000 Set Vref, RX VrefLevel [Byte0]: 40
2798 11:16:34.721754 [Byte1]: 40
2799 11:16:34.726810
2800 11:16:34.726891 Set Vref, RX VrefLevel [Byte0]: 41
2801 11:16:34.729823 [Byte1]: 41
2802 11:16:34.734739
2803 11:16:34.734820 Set Vref, RX VrefLevel [Byte0]: 42
2804 11:16:34.737613 [Byte1]: 42
2805 11:16:34.742278
2806 11:16:34.742361 Set Vref, RX VrefLevel [Byte0]: 43
2807 11:16:34.745594 [Byte1]: 43
2808 11:16:34.750956
2809 11:16:34.751039 Set Vref, RX VrefLevel [Byte0]: 44
2810 11:16:34.753933 [Byte1]: 44
2811 11:16:34.758014
2812 11:16:34.758096 Set Vref, RX VrefLevel [Byte0]: 45
2813 11:16:34.761252 [Byte1]: 45
2814 11:16:34.765953
2815 11:16:34.766034 Set Vref, RX VrefLevel [Byte0]: 46
2816 11:16:34.769345 [Byte1]: 46
2817 11:16:34.774353
2818 11:16:34.774434 Set Vref, RX VrefLevel [Byte0]: 47
2819 11:16:34.777175 [Byte1]: 47
2820 11:16:34.782912
2821 11:16:34.783005 Set Vref, RX VrefLevel [Byte0]: 48
2822 11:16:34.785275 [Byte1]: 48
2823 11:16:34.789860
2824 11:16:34.789941 Set Vref, RX VrefLevel [Byte0]: 49
2825 11:16:34.793006 [Byte1]: 49
2826 11:16:34.798174
2827 11:16:34.798255 Set Vref, RX VrefLevel [Byte0]: 50
2828 11:16:34.801410 [Byte1]: 50
2829 11:16:34.806148
2830 11:16:34.806229 Set Vref, RX VrefLevel [Byte0]: 51
2831 11:16:34.809139 [Byte1]: 51
2832 11:16:34.814152
2833 11:16:34.814233 Set Vref, RX VrefLevel [Byte0]: 52
2834 11:16:34.817167 [Byte1]: 52
2835 11:16:34.821621
2836 11:16:34.821702 Set Vref, RX VrefLevel [Byte0]: 53
2837 11:16:34.824871 [Byte1]: 53
2838 11:16:34.829351
2839 11:16:34.829432 Set Vref, RX VrefLevel [Byte0]: 54
2840 11:16:34.833225 [Byte1]: 54
2841 11:16:34.837186
2842 11:16:34.837267 Set Vref, RX VrefLevel [Byte0]: 55
2843 11:16:34.840742 [Byte1]: 55
2844 11:16:34.845554
2845 11:16:34.845637 Set Vref, RX VrefLevel [Byte0]: 56
2846 11:16:34.848807 [Byte1]: 56
2847 11:16:34.853099
2848 11:16:34.853180 Set Vref, RX VrefLevel [Byte0]: 57
2849 11:16:34.856400 [Byte1]: 57
2850 11:16:34.861182
2851 11:16:34.861263 Set Vref, RX VrefLevel [Byte0]: 58
2852 11:16:34.864391 [Byte1]: 58
2853 11:16:34.869179
2854 11:16:34.869260 Set Vref, RX VrefLevel [Byte0]: 59
2855 11:16:34.872262 [Byte1]: 59
2856 11:16:34.877312
2857 11:16:34.877393 Set Vref, RX VrefLevel [Byte0]: 60
2858 11:16:34.880474 [Byte1]: 60
2859 11:16:34.884860
2860 11:16:34.884941 Set Vref, RX VrefLevel [Byte0]: 61
2861 11:16:34.888550 [Byte1]: 61
2862 11:16:34.892719
2863 11:16:34.892800 Set Vref, RX VrefLevel [Byte0]: 62
2864 11:16:34.896264 [Byte1]: 62
2865 11:16:34.900668
2866 11:16:34.900749 Set Vref, RX VrefLevel [Byte0]: 63
2867 11:16:34.904380 [Byte1]: 63
2868 11:16:34.908735
2869 11:16:34.908816 Set Vref, RX VrefLevel [Byte0]: 64
2870 11:16:34.912345 [Byte1]: 64
2871 11:16:34.916533
2872 11:16:34.916612 Set Vref, RX VrefLevel [Byte0]: 65
2873 11:16:34.920252 [Byte1]: 65
2874 11:16:34.924953
2875 11:16:34.925033 Set Vref, RX VrefLevel [Byte0]: 66
2876 11:16:34.928058 [Byte1]: 66
2877 11:16:34.932632
2878 11:16:34.932713 Set Vref, RX VrefLevel [Byte0]: 67
2879 11:16:34.935822 [Byte1]: 67
2880 11:16:34.940409
2881 11:16:34.940522 Set Vref, RX VrefLevel [Byte0]: 68
2882 11:16:34.943628 [Byte1]: 68
2883 11:16:34.948275
2884 11:16:34.948384 Set Vref, RX VrefLevel [Byte0]: 69
2885 11:16:34.951598 [Byte1]: 69
2886 11:16:34.956511
2887 11:16:34.956629 Set Vref, RX VrefLevel [Byte0]: 70
2888 11:16:34.959407 [Byte1]: 70
2889 11:16:34.964083
2890 11:16:34.964193 Set Vref, RX VrefLevel [Byte0]: 71
2891 11:16:34.967299 [Byte1]: 71
2892 11:16:34.972134
2893 11:16:34.972215 Set Vref, RX VrefLevel [Byte0]: 72
2894 11:16:34.975388 [Byte1]: 72
2895 11:16:34.980397
2896 11:16:34.980503 Set Vref, RX VrefLevel [Byte0]: 73
2897 11:16:34.983213 [Byte1]: 73
2898 11:16:34.988461
2899 11:16:34.988564 Set Vref, RX VrefLevel [Byte0]: 74
2900 11:16:34.991080 [Byte1]: 74
2901 11:16:34.995848
2902 11:16:34.995928 Set Vref, RX VrefLevel [Byte0]: 75
2903 11:16:34.999342 [Byte1]: 75
2904 11:16:35.004053
2905 11:16:35.004133 Set Vref, RX VrefLevel [Byte0]: 76
2906 11:16:35.007073 [Byte1]: 76
2907 11:16:35.012159
2908 11:16:35.012240 Set Vref, RX VrefLevel [Byte0]: 77
2909 11:16:35.015438 [Byte1]: 77
2910 11:16:35.019940
2911 11:16:35.020021 Set Vref, RX VrefLevel [Byte0]: 78
2912 11:16:35.023313 [Byte1]: 78
2913 11:16:35.027648
2914 11:16:35.027728 Final RX Vref Byte 0 = 57 to rank0
2915 11:16:35.031238 Final RX Vref Byte 1 = 57 to rank0
2916 11:16:35.034448 Final RX Vref Byte 0 = 57 to rank1
2917 11:16:35.037908 Final RX Vref Byte 1 = 57 to rank1==
2918 11:16:35.041148 Dram Type= 6, Freq= 0, CH_0, rank 0
2919 11:16:35.047622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2920 11:16:35.047706 ==
2921 11:16:35.047772 DQS Delay:
2922 11:16:35.047830 DQS0 = 0, DQS1 = 0
2923 11:16:35.051391 DQM Delay:
2924 11:16:35.051472 DQM0 = 118, DQM1 = 107
2925 11:16:35.054497 DQ Delay:
2926 11:16:35.057562 DQ0 =118, DQ1 =120, DQ2 =116, DQ3 =114
2927 11:16:35.061165 DQ4 =120, DQ5 =110, DQ6 =126, DQ7 =126
2928 11:16:35.064234 DQ8 =96, DQ9 =94, DQ10 =110, DQ11 =102
2929 11:16:35.067619 DQ12 =112, DQ13 =112, DQ14 =122, DQ15 =114
2930 11:16:35.067698
2931 11:16:35.067759
2932 11:16:35.074059 [DQSOSCAuto] RK0, (LSB)MR18= 0xefa, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 404 ps
2933 11:16:35.077692 CH0 RK0: MR19=403, MR18=EFA
2934 11:16:35.084389 CH0_RK0: MR19=0x403, MR18=0xEFA, DQSOSC=404, MR23=63, INC=40, DEC=26
2935 11:16:35.084470
2936 11:16:35.087282 ----->DramcWriteLeveling(PI) begin...
2937 11:16:35.087362 ==
2938 11:16:35.091035 Dram Type= 6, Freq= 0, CH_0, rank 1
2939 11:16:35.093901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2940 11:16:35.097907 ==
2941 11:16:35.097986 Write leveling (Byte 0): 33 => 33
2942 11:16:35.100907 Write leveling (Byte 1): 30 => 30
2943 11:16:35.104218 DramcWriteLeveling(PI) end<-----
2944 11:16:35.104297
2945 11:16:35.104359 ==
2946 11:16:35.107452 Dram Type= 6, Freq= 0, CH_0, rank 1
2947 11:16:35.113965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2948 11:16:35.114047 ==
2949 11:16:35.114110 [Gating] SW mode calibration
2950 11:16:35.124016 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2951 11:16:35.127277 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2952 11:16:35.130502 0 15 0 | B1->B0 | 2727 3434 | 0 0 | (0 0) (0 0)
2953 11:16:35.137324 0 15 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
2954 11:16:35.140655 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2955 11:16:35.143919 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2956 11:16:35.150665 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2957 11:16:35.154059 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2958 11:16:35.157369 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2959 11:16:35.164170 0 15 28 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 1)
2960 11:16:35.167299 1 0 0 | B1->B0 | 2c2c 2323 | 0 0 | (1 0) (0 0)
2961 11:16:35.170401 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2962 11:16:35.176956 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2963 11:16:35.180443 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2964 11:16:35.184139 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2965 11:16:35.190253 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2966 11:16:35.193546 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2967 11:16:35.197441 1 0 28 | B1->B0 | 2323 3130 | 0 1 | (0 0) (1 1)
2968 11:16:35.203845 1 1 0 | B1->B0 | 3838 4646 | 0 0 | (1 1) (0 0)
2969 11:16:35.206785 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2970 11:16:35.210533 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2971 11:16:35.217027 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2972 11:16:35.220279 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2973 11:16:35.223998 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2974 11:16:35.230310 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2975 11:16:35.233514 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2976 11:16:35.236825 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2977 11:16:35.243412 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2978 11:16:35.246808 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2979 11:16:35.250053 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2980 11:16:35.256745 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2981 11:16:35.259725 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2982 11:16:35.263291 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2983 11:16:35.269762 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2984 11:16:35.273243 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2985 11:16:35.276402 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2986 11:16:35.283045 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2987 11:16:35.286379 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2988 11:16:35.289521 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2989 11:16:35.296480 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2990 11:16:35.299364 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2991 11:16:35.302749 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2992 11:16:35.310253 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2993 11:16:35.310337 Total UI for P1: 0, mck2ui 16
2994 11:16:35.316197 best dqsien dly found for B0: ( 1, 3, 26)
2995 11:16:35.319376 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2996 11:16:35.322900 Total UI for P1: 0, mck2ui 16
2997 11:16:35.326263 best dqsien dly found for B1: ( 1, 4, 0)
2998 11:16:35.329121 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2999 11:16:35.332504 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
3000 11:16:35.332641
3001 11:16:35.336248 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3002 11:16:35.339332 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
3003 11:16:35.342559 [Gating] SW calibration Done
3004 11:16:35.342641 ==
3005 11:16:35.345701 Dram Type= 6, Freq= 0, CH_0, rank 1
3006 11:16:35.348730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3007 11:16:35.348816 ==
3008 11:16:35.352395 RX Vref Scan: 0
3009 11:16:35.352502
3010 11:16:35.355843 RX Vref 0 -> 0, step: 1
3011 11:16:35.355924
3012 11:16:35.355989 RX Delay -40 -> 252, step: 8
3013 11:16:35.362260 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
3014 11:16:35.365921 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
3015 11:16:35.368814 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3016 11:16:35.372560 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3017 11:16:35.375583 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3018 11:16:35.382115 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
3019 11:16:35.385576 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3020 11:16:35.388798 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
3021 11:16:35.392136 iDelay=200, Bit 8, Center 99 (24 ~ 175) 152
3022 11:16:35.395416 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3023 11:16:35.402240 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3024 11:16:35.405021 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3025 11:16:35.408420 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3026 11:16:35.411729 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
3027 11:16:35.418298 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3028 11:16:35.421828 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3029 11:16:35.421911 ==
3030 11:16:35.425180 Dram Type= 6, Freq= 0, CH_0, rank 1
3031 11:16:35.428907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3032 11:16:35.428989 ==
3033 11:16:35.429054 DQS Delay:
3034 11:16:35.431987 DQS0 = 0, DQS1 = 0
3035 11:16:35.432068 DQM Delay:
3036 11:16:35.435071 DQM0 = 116, DQM1 = 109
3037 11:16:35.435153 DQ Delay:
3038 11:16:35.438468 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =115
3039 11:16:35.441646 DQ4 =115, DQ5 =111, DQ6 =123, DQ7 =123
3040 11:16:35.444821 DQ8 =99, DQ9 =95, DQ10 =111, DQ11 =103
3041 11:16:35.448420 DQ12 =111, DQ13 =115, DQ14 =119, DQ15 =119
3042 11:16:35.451742
3043 11:16:35.451838
3044 11:16:35.451916 ==
3045 11:16:35.454852 Dram Type= 6, Freq= 0, CH_0, rank 1
3046 11:16:35.458471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3047 11:16:35.458594 ==
3048 11:16:35.458659
3049 11:16:35.458717
3050 11:16:35.461504 TX Vref Scan disable
3051 11:16:35.461584 == TX Byte 0 ==
3052 11:16:35.468371 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3053 11:16:35.472641 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3054 11:16:35.472721 == TX Byte 1 ==
3055 11:16:35.478318 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3056 11:16:35.481507 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3057 11:16:35.481588 ==
3058 11:16:35.485118 Dram Type= 6, Freq= 0, CH_0, rank 1
3059 11:16:35.488902 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3060 11:16:35.488983 ==
3061 11:16:35.500695 TX Vref=22, minBit 0, minWin=26, winSum=429
3062 11:16:35.504331 TX Vref=24, minBit 2, minWin=26, winSum=432
3063 11:16:35.507633 TX Vref=26, minBit 5, minWin=25, winSum=431
3064 11:16:35.510994 TX Vref=28, minBit 1, minWin=26, winSum=433
3065 11:16:35.514141 TX Vref=30, minBit 13, minWin=26, winSum=435
3066 11:16:35.520693 TX Vref=32, minBit 10, minWin=26, winSum=432
3067 11:16:35.523930 [TxChooseVref] Worse bit 13, Min win 26, Win sum 435, Final Vref 30
3068 11:16:35.524012
3069 11:16:35.527457 Final TX Range 1 Vref 30
3070 11:16:35.527539
3071 11:16:35.527602 ==
3072 11:16:35.530470 Dram Type= 6, Freq= 0, CH_0, rank 1
3073 11:16:35.534176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3074 11:16:35.537997 ==
3075 11:16:35.538077
3076 11:16:35.538140
3077 11:16:35.538198 TX Vref Scan disable
3078 11:16:35.540658 == TX Byte 0 ==
3079 11:16:35.544176 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3080 11:16:35.550979 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3081 11:16:35.551065 == TX Byte 1 ==
3082 11:16:35.554153 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3083 11:16:35.560970 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3084 11:16:35.561059
3085 11:16:35.561125 [DATLAT]
3086 11:16:35.561184 Freq=1200, CH0 RK1
3087 11:16:35.561243
3088 11:16:35.563891 DATLAT Default: 0xd
3089 11:16:35.567137 0, 0xFFFF, sum = 0
3090 11:16:35.567220 1, 0xFFFF, sum = 0
3091 11:16:35.570735 2, 0xFFFF, sum = 0
3092 11:16:35.570819 3, 0xFFFF, sum = 0
3093 11:16:35.573987 4, 0xFFFF, sum = 0
3094 11:16:35.574071 5, 0xFFFF, sum = 0
3095 11:16:35.577493 6, 0xFFFF, sum = 0
3096 11:16:35.577577 7, 0xFFFF, sum = 0
3097 11:16:35.580678 8, 0xFFFF, sum = 0
3098 11:16:35.580761 9, 0xFFFF, sum = 0
3099 11:16:35.583747 10, 0xFFFF, sum = 0
3100 11:16:35.583830 11, 0xFFFF, sum = 0
3101 11:16:35.587176 12, 0x0, sum = 1
3102 11:16:35.587260 13, 0x0, sum = 2
3103 11:16:35.590695 14, 0x0, sum = 3
3104 11:16:35.590778 15, 0x0, sum = 4
3105 11:16:35.593571 best_step = 13
3106 11:16:35.593654
3107 11:16:35.593718 ==
3108 11:16:35.597260 Dram Type= 6, Freq= 0, CH_0, rank 1
3109 11:16:35.600715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3110 11:16:35.600798 ==
3111 11:16:35.600863 RX Vref Scan: 0
3112 11:16:35.603901
3113 11:16:35.603982 RX Vref 0 -> 0, step: 1
3114 11:16:35.604048
3115 11:16:35.607000 RX Delay -21 -> 252, step: 4
3116 11:16:35.613614 iDelay=199, Bit 0, Center 112 (47 ~ 178) 132
3117 11:16:35.616746 iDelay=199, Bit 1, Center 118 (47 ~ 190) 144
3118 11:16:35.620162 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3119 11:16:35.623823 iDelay=199, Bit 3, Center 114 (43 ~ 186) 144
3120 11:16:35.626955 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3121 11:16:35.633438 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3122 11:16:35.637114 iDelay=199, Bit 6, Center 126 (55 ~ 198) 144
3123 11:16:35.640196 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3124 11:16:35.643586 iDelay=199, Bit 8, Center 98 (31 ~ 166) 136
3125 11:16:35.646750 iDelay=199, Bit 9, Center 96 (31 ~ 162) 132
3126 11:16:35.650518 iDelay=199, Bit 10, Center 112 (43 ~ 182) 140
3127 11:16:35.657433 iDelay=199, Bit 11, Center 102 (35 ~ 170) 136
3128 11:16:35.660111 iDelay=199, Bit 12, Center 116 (51 ~ 182) 132
3129 11:16:35.663374 iDelay=199, Bit 13, Center 114 (51 ~ 178) 128
3130 11:16:35.667241 iDelay=199, Bit 14, Center 120 (55 ~ 186) 132
3131 11:16:35.673859 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
3132 11:16:35.673946 ==
3133 11:16:35.676837 Dram Type= 6, Freq= 0, CH_0, rank 1
3134 11:16:35.679855 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3135 11:16:35.679938 ==
3136 11:16:35.680003 DQS Delay:
3137 11:16:35.683354 DQS0 = 0, DQS1 = 0
3138 11:16:35.683437 DQM Delay:
3139 11:16:35.686458 DQM0 = 116, DQM1 = 109
3140 11:16:35.686540 DQ Delay:
3141 11:16:35.689870 DQ0 =112, DQ1 =118, DQ2 =110, DQ3 =114
3142 11:16:35.693121 DQ4 =116, DQ5 =110, DQ6 =126, DQ7 =124
3143 11:16:35.696495 DQ8 =98, DQ9 =96, DQ10 =112, DQ11 =102
3144 11:16:35.700062 DQ12 =116, DQ13 =114, DQ14 =120, DQ15 =116
3145 11:16:35.700145
3146 11:16:35.700210
3147 11:16:35.709870 [DQSOSCAuto] RK1, (LSB)MR18= 0xce6, (MSB)MR19= 0x403, tDQSOscB0 = 420 ps tDQSOscB1 = 405 ps
3148 11:16:35.713233 CH0 RK1: MR19=403, MR18=CE6
3149 11:16:35.716331 CH0_RK1: MR19=0x403, MR18=0xCE6, DQSOSC=405, MR23=63, INC=39, DEC=26
3150 11:16:35.719980 [RxdqsGatingPostProcess] freq 1200
3151 11:16:35.726596 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3152 11:16:35.729691 best DQS0 dly(2T, 0.5T) = (0, 11)
3153 11:16:35.732857 best DQS1 dly(2T, 0.5T) = (0, 12)
3154 11:16:35.736128 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3155 11:16:35.739769 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3156 11:16:35.743318 best DQS0 dly(2T, 0.5T) = (0, 11)
3157 11:16:35.746366 best DQS1 dly(2T, 0.5T) = (0, 12)
3158 11:16:35.750515 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3159 11:16:35.753336 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3160 11:16:35.753419 Pre-setting of DQS Precalculation
3161 11:16:35.759402 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3162 11:16:35.759485 ==
3163 11:16:35.763064 Dram Type= 6, Freq= 0, CH_1, rank 0
3164 11:16:35.766546 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3165 11:16:35.766674 ==
3166 11:16:35.772550 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3167 11:16:35.779403 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3168 11:16:35.787202 [CA 0] Center 37 (7~67) winsize 61
3169 11:16:35.790324 [CA 1] Center 37 (7~68) winsize 62
3170 11:16:35.793603 [CA 2] Center 34 (4~64) winsize 61
3171 11:16:35.796950 [CA 3] Center 33 (3~64) winsize 62
3172 11:16:35.800154 [CA 4] Center 34 (4~64) winsize 61
3173 11:16:35.803320 [CA 5] Center 33 (3~64) winsize 62
3174 11:16:35.803466
3175 11:16:35.807109 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3176 11:16:35.807191
3177 11:16:35.810580 [CATrainingPosCal] consider 1 rank data
3178 11:16:35.813572 u2DelayCellTimex100 = 270/100 ps
3179 11:16:35.816715 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3180 11:16:35.823436 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3181 11:16:35.826711 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3182 11:16:35.830179 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3183 11:16:35.833430 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3184 11:16:35.836765 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3185 11:16:35.836847
3186 11:16:35.839919 CA PerBit enable=1, Macro0, CA PI delay=33
3187 11:16:35.840030
3188 11:16:35.843646 [CBTSetCACLKResult] CA Dly = 33
3189 11:16:35.843728 CS Dly: 6 (0~37)
3190 11:16:35.846357 ==
3191 11:16:35.850280 Dram Type= 6, Freq= 0, CH_1, rank 1
3192 11:16:35.853209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3193 11:16:35.853295 ==
3194 11:16:35.856297 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3195 11:16:35.862888 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3196 11:16:35.872771 [CA 0] Center 37 (7~67) winsize 61
3197 11:16:35.876089 [CA 1] Center 37 (7~68) winsize 62
3198 11:16:35.879350 [CA 2] Center 34 (4~65) winsize 62
3199 11:16:35.882421 [CA 3] Center 33 (3~64) winsize 62
3200 11:16:35.886024 [CA 4] Center 34 (4~64) winsize 61
3201 11:16:35.889050 [CA 5] Center 33 (3~64) winsize 62
3202 11:16:35.889134
3203 11:16:35.892508 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3204 11:16:35.892628
3205 11:16:35.895803 [CATrainingPosCal] consider 2 rank data
3206 11:16:35.898970 u2DelayCellTimex100 = 270/100 ps
3207 11:16:35.902142 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3208 11:16:35.909173 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3209 11:16:35.912110 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3210 11:16:35.915652 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3211 11:16:35.919483 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3212 11:16:35.921997 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3213 11:16:35.922080
3214 11:16:35.925446 CA PerBit enable=1, Macro0, CA PI delay=33
3215 11:16:35.925529
3216 11:16:35.929298 [CBTSetCACLKResult] CA Dly = 33
3217 11:16:35.929380 CS Dly: 7 (0~40)
3218 11:16:35.932113
3219 11:16:35.935962 ----->DramcWriteLeveling(PI) begin...
3220 11:16:35.936046 ==
3221 11:16:35.938693 Dram Type= 6, Freq= 0, CH_1, rank 0
3222 11:16:35.942078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3223 11:16:35.942160 ==
3224 11:16:35.945455 Write leveling (Byte 0): 25 => 25
3225 11:16:35.948854 Write leveling (Byte 1): 28 => 28
3226 11:16:35.952090 DramcWriteLeveling(PI) end<-----
3227 11:16:35.952172
3228 11:16:35.952234 ==
3229 11:16:35.955290 Dram Type= 6, Freq= 0, CH_1, rank 0
3230 11:16:35.958589 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3231 11:16:35.958672 ==
3232 11:16:35.962664 [Gating] SW mode calibration
3233 11:16:35.968449 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3234 11:16:35.975617 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3235 11:16:35.978718 0 15 0 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
3236 11:16:35.982140 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3237 11:16:35.988416 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3238 11:16:35.992274 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3239 11:16:35.995397 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3240 11:16:36.001872 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3241 11:16:36.005174 0 15 24 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (0 1)
3242 11:16:36.008378 0 15 28 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
3243 11:16:36.015751 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3244 11:16:36.018529 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3245 11:16:36.022260 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3246 11:16:36.028135 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3247 11:16:36.031582 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3248 11:16:36.034919 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3249 11:16:36.041590 1 0 24 | B1->B0 | 2626 3838 | 0 0 | (0 0) (1 1)
3250 11:16:36.044817 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3251 11:16:36.048378 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3252 11:16:36.051329 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3253 11:16:36.058186 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3254 11:16:36.061445 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3255 11:16:36.064883 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3256 11:16:36.071284 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3257 11:16:36.074931 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3258 11:16:36.078147 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3259 11:16:36.084656 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3260 11:16:36.088010 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3261 11:16:36.091316 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3262 11:16:36.098148 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3263 11:16:36.101262 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3264 11:16:36.105173 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3265 11:16:36.111514 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3266 11:16:36.114451 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3267 11:16:36.118051 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3268 11:16:36.124392 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3269 11:16:36.127574 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3270 11:16:36.130893 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3271 11:16:36.137543 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3272 11:16:36.140761 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3273 11:16:36.144877 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3274 11:16:36.150856 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3275 11:16:36.150958 Total UI for P1: 0, mck2ui 16
3276 11:16:36.157357 best dqsien dly found for B0: ( 1, 3, 24)
3277 11:16:36.157448 Total UI for P1: 0, mck2ui 16
3278 11:16:36.164284 best dqsien dly found for B1: ( 1, 3, 26)
3279 11:16:36.167419 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3280 11:16:36.170810 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3281 11:16:36.170891
3282 11:16:36.174141 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3283 11:16:36.177144 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3284 11:16:36.180760 [Gating] SW calibration Done
3285 11:16:36.180841 ==
3286 11:16:36.183778 Dram Type= 6, Freq= 0, CH_1, rank 0
3287 11:16:36.187098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3288 11:16:36.187182 ==
3289 11:16:36.190877 RX Vref Scan: 0
3290 11:16:36.190958
3291 11:16:36.191022 RX Vref 0 -> 0, step: 1
3292 11:16:36.191080
3293 11:16:36.194157 RX Delay -40 -> 252, step: 8
3294 11:16:36.197358 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3295 11:16:36.203771 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3296 11:16:36.207521 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3297 11:16:36.210617 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3298 11:16:36.214209 iDelay=208, Bit 4, Center 111 (40 ~ 183) 144
3299 11:16:36.217027 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3300 11:16:36.223679 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3301 11:16:36.226641 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3302 11:16:36.230650 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3303 11:16:36.233550 iDelay=208, Bit 9, Center 103 (32 ~ 175) 144
3304 11:16:36.240134 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3305 11:16:36.243654 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3306 11:16:36.247202 iDelay=208, Bit 12, Center 115 (40 ~ 191) 152
3307 11:16:36.249889 iDelay=208, Bit 13, Center 115 (40 ~ 191) 152
3308 11:16:36.253094 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3309 11:16:36.260406 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3310 11:16:36.260503 ==
3311 11:16:36.263606 Dram Type= 6, Freq= 0, CH_1, rank 0
3312 11:16:36.266795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3313 11:16:36.266877 ==
3314 11:16:36.266942 DQS Delay:
3315 11:16:36.270014 DQS0 = 0, DQS1 = 0
3316 11:16:36.270095 DQM Delay:
3317 11:16:36.272949 DQM0 = 117, DQM1 = 108
3318 11:16:36.273029 DQ Delay:
3319 11:16:36.276432 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3320 11:16:36.280113 DQ4 =111, DQ5 =131, DQ6 =123, DQ7 =115
3321 11:16:36.283023 DQ8 =95, DQ9 =103, DQ10 =111, DQ11 =95
3322 11:16:36.286622 DQ12 =115, DQ13 =115, DQ14 =115, DQ15 =119
3323 11:16:36.286719
3324 11:16:36.286811
3325 11:16:36.289804 ==
3326 11:16:36.292852 Dram Type= 6, Freq= 0, CH_1, rank 0
3327 11:16:36.297078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3328 11:16:36.297163 ==
3329 11:16:36.297228
3330 11:16:36.297286
3331 11:16:36.299706 TX Vref Scan disable
3332 11:16:36.299788 == TX Byte 0 ==
3333 11:16:36.302978 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3334 11:16:36.309765 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3335 11:16:36.309851 == TX Byte 1 ==
3336 11:16:36.312892 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3337 11:16:36.319512 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3338 11:16:36.319597 ==
3339 11:16:36.323230 Dram Type= 6, Freq= 0, CH_1, rank 0
3340 11:16:36.326260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3341 11:16:36.326354 ==
3342 11:16:36.338073 TX Vref=22, minBit 10, minWin=24, winSum=415
3343 11:16:36.341434 TX Vref=24, minBit 9, minWin=25, winSum=421
3344 11:16:36.344715 TX Vref=26, minBit 8, minWin=25, winSum=425
3345 11:16:36.348338 TX Vref=28, minBit 9, minWin=25, winSum=428
3346 11:16:36.351517 TX Vref=30, minBit 9, minWin=25, winSum=428
3347 11:16:36.358207 TX Vref=32, minBit 9, minWin=25, winSum=424
3348 11:16:36.361650 [TxChooseVref] Worse bit 9, Min win 25, Win sum 428, Final Vref 28
3349 11:16:36.361738
3350 11:16:36.364730 Final TX Range 1 Vref 28
3351 11:16:36.364814
3352 11:16:36.364880 ==
3353 11:16:36.368938 Dram Type= 6, Freq= 0, CH_1, rank 0
3354 11:16:36.371978 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3355 11:16:36.372065 ==
3356 11:16:36.375004
3357 11:16:36.375087
3358 11:16:36.375153 TX Vref Scan disable
3359 11:16:36.378136 == TX Byte 0 ==
3360 11:16:36.381198 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3361 11:16:36.387880 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3362 11:16:36.387974 == TX Byte 1 ==
3363 11:16:36.391231 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3364 11:16:36.397992 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3365 11:16:36.398084
3366 11:16:36.398148 [DATLAT]
3367 11:16:36.398207 Freq=1200, CH1 RK0
3368 11:16:36.398264
3369 11:16:36.401868 DATLAT Default: 0xd
3370 11:16:36.401951 0, 0xFFFF, sum = 0
3371 11:16:36.404428 1, 0xFFFF, sum = 0
3372 11:16:36.407707 2, 0xFFFF, sum = 0
3373 11:16:36.407790 3, 0xFFFF, sum = 0
3374 11:16:36.411240 4, 0xFFFF, sum = 0
3375 11:16:36.411324 5, 0xFFFF, sum = 0
3376 11:16:36.414257 6, 0xFFFF, sum = 0
3377 11:16:36.414340 7, 0xFFFF, sum = 0
3378 11:16:36.417791 8, 0xFFFF, sum = 0
3379 11:16:36.417875 9, 0xFFFF, sum = 0
3380 11:16:36.421165 10, 0xFFFF, sum = 0
3381 11:16:36.421247 11, 0xFFFF, sum = 0
3382 11:16:36.424237 12, 0x0, sum = 1
3383 11:16:36.424319 13, 0x0, sum = 2
3384 11:16:36.428090 14, 0x0, sum = 3
3385 11:16:36.428171 15, 0x0, sum = 4
3386 11:16:36.430793 best_step = 13
3387 11:16:36.430873
3388 11:16:36.430936 ==
3389 11:16:36.434072 Dram Type= 6, Freq= 0, CH_1, rank 0
3390 11:16:36.438241 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3391 11:16:36.438324 ==
3392 11:16:36.438387 RX Vref Scan: 1
3393 11:16:36.441140
3394 11:16:36.441220 Set Vref Range= 32 -> 127
3395 11:16:36.441282
3396 11:16:36.443999 RX Vref 32 -> 127, step: 1
3397 11:16:36.444086
3398 11:16:36.447708 RX Delay -21 -> 252, step: 4
3399 11:16:36.447792
3400 11:16:36.451304 Set Vref, RX VrefLevel [Byte0]: 32
3401 11:16:36.454504 [Byte1]: 32
3402 11:16:36.454590
3403 11:16:36.457314 Set Vref, RX VrefLevel [Byte0]: 33
3404 11:16:36.460680 [Byte1]: 33
3405 11:16:36.464686
3406 11:16:36.464772 Set Vref, RX VrefLevel [Byte0]: 34
3407 11:16:36.467813 [Byte1]: 34
3408 11:16:36.472487
3409 11:16:36.472604 Set Vref, RX VrefLevel [Byte0]: 35
3410 11:16:36.475717 [Byte1]: 35
3411 11:16:36.480341
3412 11:16:36.480428 Set Vref, RX VrefLevel [Byte0]: 36
3413 11:16:36.483772 [Byte1]: 36
3414 11:16:36.488156
3415 11:16:36.488253 Set Vref, RX VrefLevel [Byte0]: 37
3416 11:16:36.494537 [Byte1]: 37
3417 11:16:36.494631
3418 11:16:36.498200 Set Vref, RX VrefLevel [Byte0]: 38
3419 11:16:36.501758 [Byte1]: 38
3420 11:16:36.501845
3421 11:16:36.504439 Set Vref, RX VrefLevel [Byte0]: 39
3422 11:16:36.507990 [Byte1]: 39
3423 11:16:36.511977
3424 11:16:36.512064 Set Vref, RX VrefLevel [Byte0]: 40
3425 11:16:36.515217 [Byte1]: 40
3426 11:16:36.520135
3427 11:16:36.520223 Set Vref, RX VrefLevel [Byte0]: 41
3428 11:16:36.523305 [Byte1]: 41
3429 11:16:36.528034
3430 11:16:36.528119 Set Vref, RX VrefLevel [Byte0]: 42
3431 11:16:36.531118 [Byte1]: 42
3432 11:16:36.535978
3433 11:16:36.536065 Set Vref, RX VrefLevel [Byte0]: 43
3434 11:16:36.539635 [Byte1]: 43
3435 11:16:36.543728
3436 11:16:36.543837 Set Vref, RX VrefLevel [Byte0]: 44
3437 11:16:36.547290 [Byte1]: 44
3438 11:16:36.551650
3439 11:16:36.551739 Set Vref, RX VrefLevel [Byte0]: 45
3440 11:16:36.555101 [Byte1]: 45
3441 11:16:36.559435
3442 11:16:36.559518 Set Vref, RX VrefLevel [Byte0]: 46
3443 11:16:36.562782 [Byte1]: 46
3444 11:16:36.567440
3445 11:16:36.567523 Set Vref, RX VrefLevel [Byte0]: 47
3446 11:16:36.570660 [Byte1]: 47
3447 11:16:36.575642
3448 11:16:36.575731 Set Vref, RX VrefLevel [Byte0]: 48
3449 11:16:36.578600 [Byte1]: 48
3450 11:16:36.583641
3451 11:16:36.583729 Set Vref, RX VrefLevel [Byte0]: 49
3452 11:16:36.586664 [Byte1]: 49
3453 11:16:36.591186
3454 11:16:36.591269 Set Vref, RX VrefLevel [Byte0]: 50
3455 11:16:36.594604 [Byte1]: 50
3456 11:16:36.599259
3457 11:16:36.599341 Set Vref, RX VrefLevel [Byte0]: 51
3458 11:16:36.602772 [Byte1]: 51
3459 11:16:36.607038
3460 11:16:36.607119 Set Vref, RX VrefLevel [Byte0]: 52
3461 11:16:36.610328 [Byte1]: 52
3462 11:16:36.615247
3463 11:16:36.615329 Set Vref, RX VrefLevel [Byte0]: 53
3464 11:16:36.618469 [Byte1]: 53
3465 11:16:36.623121
3466 11:16:36.623202 Set Vref, RX VrefLevel [Byte0]: 54
3467 11:16:36.626518 [Byte1]: 54
3468 11:16:36.630855
3469 11:16:36.630936 Set Vref, RX VrefLevel [Byte0]: 55
3470 11:16:36.634270 [Byte1]: 55
3471 11:16:36.638644
3472 11:16:36.638728 Set Vref, RX VrefLevel [Byte0]: 56
3473 11:16:36.642090 [Byte1]: 56
3474 11:16:36.646801
3475 11:16:36.646884 Set Vref, RX VrefLevel [Byte0]: 57
3476 11:16:36.649867 [Byte1]: 57
3477 11:16:36.654721
3478 11:16:36.654807 Set Vref, RX VrefLevel [Byte0]: 58
3479 11:16:36.657628 [Byte1]: 58
3480 11:16:36.662553
3481 11:16:36.662635 Set Vref, RX VrefLevel [Byte0]: 59
3482 11:16:36.666425 [Byte1]: 59
3483 11:16:36.670514
3484 11:16:36.670596 Set Vref, RX VrefLevel [Byte0]: 60
3485 11:16:36.673572 [Byte1]: 60
3486 11:16:36.678398
3487 11:16:36.678480 Set Vref, RX VrefLevel [Byte0]: 61
3488 11:16:36.681827 [Byte1]: 61
3489 11:16:36.686458
3490 11:16:36.686544 Set Vref, RX VrefLevel [Byte0]: 62
3491 11:16:36.690129 [Byte1]: 62
3492 11:16:36.693945
3493 11:16:36.694027 Set Vref, RX VrefLevel [Byte0]: 63
3494 11:16:36.697435 [Byte1]: 63
3495 11:16:36.701967
3496 11:16:36.702047 Set Vref, RX VrefLevel [Byte0]: 64
3497 11:16:36.705195 [Byte1]: 64
3498 11:16:36.709888
3499 11:16:36.709969 Set Vref, RX VrefLevel [Byte0]: 65
3500 11:16:36.713310 [Byte1]: 65
3501 11:16:36.718059
3502 11:16:36.718140 Set Vref, RX VrefLevel [Byte0]: 66
3503 11:16:36.721045 [Byte1]: 66
3504 11:16:36.725863
3505 11:16:36.725943 Set Vref, RX VrefLevel [Byte0]: 67
3506 11:16:36.729057 [Byte1]: 67
3507 11:16:36.733758
3508 11:16:36.733838 Set Vref, RX VrefLevel [Byte0]: 68
3509 11:16:36.737240 [Byte1]: 68
3510 11:16:36.741839
3511 11:16:36.741937 Final RX Vref Byte 0 = 47 to rank0
3512 11:16:36.744869 Final RX Vref Byte 1 = 53 to rank0
3513 11:16:36.748722 Final RX Vref Byte 0 = 47 to rank1
3514 11:16:36.752473 Final RX Vref Byte 1 = 53 to rank1==
3515 11:16:36.755215 Dram Type= 6, Freq= 0, CH_1, rank 0
3516 11:16:36.761632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3517 11:16:36.761716 ==
3518 11:16:36.761780 DQS Delay:
3519 11:16:36.761837 DQS0 = 0, DQS1 = 0
3520 11:16:36.764753 DQM Delay:
3521 11:16:36.764833 DQM0 = 116, DQM1 = 110
3522 11:16:36.768158 DQ Delay:
3523 11:16:36.771805 DQ0 =118, DQ1 =112, DQ2 =108, DQ3 =112
3524 11:16:36.775238 DQ4 =114, DQ5 =126, DQ6 =126, DQ7 =114
3525 11:16:36.778224 DQ8 =96, DQ9 =102, DQ10 =112, DQ11 =100
3526 11:16:36.781798 DQ12 =118, DQ13 =118, DQ14 =120, DQ15 =118
3527 11:16:36.781880
3528 11:16:36.781942
3529 11:16:36.787978 [DQSOSCAuto] RK0, (LSB)MR18= 0xf4, (MSB)MR19= 0x403, tDQSOscB0 = 415 ps tDQSOscB1 = 410 ps
3530 11:16:36.791293 CH1 RK0: MR19=403, MR18=F4
3531 11:16:36.797905 CH1_RK0: MR19=0x403, MR18=0xF4, DQSOSC=410, MR23=63, INC=39, DEC=26
3532 11:16:36.798015
3533 11:16:36.801880 ----->DramcWriteLeveling(PI) begin...
3534 11:16:36.801967 ==
3535 11:16:36.804400 Dram Type= 6, Freq= 0, CH_1, rank 1
3536 11:16:36.808231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3537 11:16:36.811120 ==
3538 11:16:36.811201 Write leveling (Byte 0): 24 => 24
3539 11:16:36.814757 Write leveling (Byte 1): 28 => 28
3540 11:16:36.817868 DramcWriteLeveling(PI) end<-----
3541 11:16:36.817949
3542 11:16:36.818012 ==
3543 11:16:36.821122 Dram Type= 6, Freq= 0, CH_1, rank 1
3544 11:16:36.827571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3545 11:16:36.827653 ==
3546 11:16:36.831230 [Gating] SW mode calibration
3547 11:16:36.837611 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3548 11:16:36.840822 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3549 11:16:36.846896 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3550 11:16:36.850686 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3551 11:16:36.854160 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3552 11:16:36.860483 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3553 11:16:36.863963 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3554 11:16:36.867109 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3555 11:16:36.873450 0 15 24 | B1->B0 | 2d2d 3434 | 0 0 | (0 0) (0 0)
3556 11:16:36.876882 0 15 28 | B1->B0 | 2323 2323 | 0 1 | (1 0) (1 0)
3557 11:16:36.880495 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3558 11:16:36.886454 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3559 11:16:36.890173 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3560 11:16:36.893657 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3561 11:16:36.899953 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3562 11:16:36.903352 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3563 11:16:36.906265 1 0 24 | B1->B0 | 3a3a 2b2b | 0 1 | (1 1) (0 0)
3564 11:16:36.913012 1 0 28 | B1->B0 | 4646 4343 | 0 0 | (0 0) (0 0)
3565 11:16:36.916233 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3566 11:16:36.920486 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3567 11:16:36.926883 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3568 11:16:36.929836 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3569 11:16:36.932861 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3570 11:16:36.939668 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3571 11:16:36.942674 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3572 11:16:36.945913 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3573 11:16:36.953140 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3574 11:16:36.956326 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3575 11:16:36.959100 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3576 11:16:36.965620 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3577 11:16:36.969144 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3578 11:16:36.972480 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3579 11:16:36.979146 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3580 11:16:36.982182 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3581 11:16:36.985851 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3582 11:16:36.992424 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3583 11:16:36.995763 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3584 11:16:36.999092 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3585 11:16:37.005758 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3586 11:16:37.008568 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3587 11:16:37.011905 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3588 11:16:37.018841 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3589 11:16:37.022308 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3590 11:16:37.025319 Total UI for P1: 0, mck2ui 16
3591 11:16:37.028550 best dqsien dly found for B0: ( 1, 3, 26)
3592 11:16:37.032143 Total UI for P1: 0, mck2ui 16
3593 11:16:37.035522 best dqsien dly found for B1: ( 1, 3, 26)
3594 11:16:37.038666 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3595 11:16:37.041943 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3596 11:16:37.042025
3597 11:16:37.044867 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3598 11:16:37.048236 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3599 11:16:37.052234 [Gating] SW calibration Done
3600 11:16:37.052316 ==
3601 11:16:37.055142 Dram Type= 6, Freq= 0, CH_1, rank 1
3602 11:16:37.058730 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3603 11:16:37.061354 ==
3604 11:16:37.061437 RX Vref Scan: 0
3605 11:16:37.061519
3606 11:16:37.064663 RX Vref 0 -> 0, step: 1
3607 11:16:37.064746
3608 11:16:37.068300 RX Delay -40 -> 252, step: 8
3609 11:16:37.072184 iDelay=208, Bit 0, Center 119 (48 ~ 191) 144
3610 11:16:37.074814 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3611 11:16:37.078022 iDelay=208, Bit 2, Center 103 (32 ~ 175) 144
3612 11:16:37.081152 iDelay=208, Bit 3, Center 111 (40 ~ 183) 144
3613 11:16:37.087705 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3614 11:16:37.091227 iDelay=208, Bit 5, Center 123 (48 ~ 199) 152
3615 11:16:37.094706 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
3616 11:16:37.097739 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3617 11:16:37.101024 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3618 11:16:37.107814 iDelay=208, Bit 9, Center 103 (32 ~ 175) 144
3619 11:16:37.111347 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3620 11:16:37.114171 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3621 11:16:37.117535 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3622 11:16:37.124212 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3623 11:16:37.127456 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3624 11:16:37.130764 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3625 11:16:37.130846 ==
3626 11:16:37.134157 Dram Type= 6, Freq= 0, CH_1, rank 1
3627 11:16:37.137234 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3628 11:16:37.137318 ==
3629 11:16:37.140968 DQS Delay:
3630 11:16:37.141048 DQS0 = 0, DQS1 = 0
3631 11:16:37.143868 DQM Delay:
3632 11:16:37.143948 DQM0 = 116, DQM1 = 110
3633 11:16:37.144013 DQ Delay:
3634 11:16:37.150387 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =111
3635 11:16:37.153700 DQ4 =115, DQ5 =123, DQ6 =131, DQ7 =115
3636 11:16:37.156944 DQ8 =95, DQ9 =103, DQ10 =111, DQ11 =103
3637 11:16:37.160078 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3638 11:16:37.160161
3639 11:16:37.160225
3640 11:16:37.160285 ==
3641 11:16:37.163803 Dram Type= 6, Freq= 0, CH_1, rank 1
3642 11:16:37.166835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3643 11:16:37.166917 ==
3644 11:16:37.166981
3645 11:16:37.167040
3646 11:16:37.170007 TX Vref Scan disable
3647 11:16:37.173940 == TX Byte 0 ==
3648 11:16:37.177263 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3649 11:16:37.180300 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3650 11:16:37.183492 == TX Byte 1 ==
3651 11:16:37.186735 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3652 11:16:37.190385 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3653 11:16:37.190468 ==
3654 11:16:37.193300 Dram Type= 6, Freq= 0, CH_1, rank 1
3655 11:16:37.199792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3656 11:16:37.199877 ==
3657 11:16:37.210378 TX Vref=22, minBit 9, minWin=25, winSum=425
3658 11:16:37.213651 TX Vref=24, minBit 0, minWin=26, winSum=431
3659 11:16:37.217563 TX Vref=26, minBit 8, minWin=26, winSum=433
3660 11:16:37.220624 TX Vref=28, minBit 9, minWin=26, winSum=439
3661 11:16:37.223598 TX Vref=30, minBit 9, minWin=26, winSum=437
3662 11:16:37.230155 TX Vref=32, minBit 9, minWin=26, winSum=434
3663 11:16:37.233459 [TxChooseVref] Worse bit 9, Min win 26, Win sum 439, Final Vref 28
3664 11:16:37.233541
3665 11:16:37.237016 Final TX Range 1 Vref 28
3666 11:16:37.237106
3667 11:16:37.237171 ==
3668 11:16:37.240452 Dram Type= 6, Freq= 0, CH_1, rank 1
3669 11:16:37.243346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3670 11:16:37.247096 ==
3671 11:16:37.247176
3672 11:16:37.247238
3673 11:16:37.247295 TX Vref Scan disable
3674 11:16:37.250369 == TX Byte 0 ==
3675 11:16:37.253630 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3676 11:16:37.260409 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3677 11:16:37.260496 == TX Byte 1 ==
3678 11:16:37.263296 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3679 11:16:37.269787 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3680 11:16:37.269868
3681 11:16:37.269932 [DATLAT]
3682 11:16:37.269992 Freq=1200, CH1 RK1
3683 11:16:37.270050
3684 11:16:37.273361 DATLAT Default: 0xd
3685 11:16:37.276921 0, 0xFFFF, sum = 0
3686 11:16:37.277003 1, 0xFFFF, sum = 0
3687 11:16:37.279787 2, 0xFFFF, sum = 0
3688 11:16:37.279868 3, 0xFFFF, sum = 0
3689 11:16:37.283600 4, 0xFFFF, sum = 0
3690 11:16:37.283680 5, 0xFFFF, sum = 0
3691 11:16:37.286502 6, 0xFFFF, sum = 0
3692 11:16:37.286584 7, 0xFFFF, sum = 0
3693 11:16:37.289577 8, 0xFFFF, sum = 0
3694 11:16:37.289659 9, 0xFFFF, sum = 0
3695 11:16:37.293179 10, 0xFFFF, sum = 0
3696 11:16:37.293259 11, 0xFFFF, sum = 0
3697 11:16:37.296375 12, 0x0, sum = 1
3698 11:16:37.296455 13, 0x0, sum = 2
3699 11:16:37.299875 14, 0x0, sum = 3
3700 11:16:37.300001 15, 0x0, sum = 4
3701 11:16:37.302896 best_step = 13
3702 11:16:37.302976
3703 11:16:37.303039 ==
3704 11:16:37.306708 Dram Type= 6, Freq= 0, CH_1, rank 1
3705 11:16:37.309871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3706 11:16:37.309951 ==
3707 11:16:37.312865 RX Vref Scan: 0
3708 11:16:37.312944
3709 11:16:37.313007 RX Vref 0 -> 0, step: 1
3710 11:16:37.313067
3711 11:16:37.316619 RX Delay -21 -> 252, step: 4
3712 11:16:37.322654 iDelay=199, Bit 0, Center 120 (51 ~ 190) 140
3713 11:16:37.326168 iDelay=199, Bit 1, Center 110 (43 ~ 178) 136
3714 11:16:37.329667 iDelay=199, Bit 2, Center 108 (43 ~ 174) 132
3715 11:16:37.332745 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3716 11:16:37.336643 iDelay=199, Bit 4, Center 116 (47 ~ 186) 140
3717 11:16:37.342505 iDelay=199, Bit 5, Center 126 (59 ~ 194) 136
3718 11:16:37.345974 iDelay=199, Bit 6, Center 128 (59 ~ 198) 140
3719 11:16:37.349606 iDelay=199, Bit 7, Center 114 (47 ~ 182) 136
3720 11:16:37.352666 iDelay=199, Bit 8, Center 98 (31 ~ 166) 136
3721 11:16:37.355638 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3722 11:16:37.362264 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3723 11:16:37.365734 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3724 11:16:37.368732 iDelay=199, Bit 12, Center 118 (51 ~ 186) 136
3725 11:16:37.372228 iDelay=199, Bit 13, Center 118 (51 ~ 186) 136
3726 11:16:37.379024 iDelay=199, Bit 14, Center 118 (51 ~ 186) 136
3727 11:16:37.382352 iDelay=199, Bit 15, Center 120 (51 ~ 190) 140
3728 11:16:37.382435 ==
3729 11:16:37.385640 Dram Type= 6, Freq= 0, CH_1, rank 1
3730 11:16:37.388752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3731 11:16:37.388835 ==
3732 11:16:37.392395 DQS Delay:
3733 11:16:37.392476 DQS0 = 0, DQS1 = 0
3734 11:16:37.392618 DQM Delay:
3735 11:16:37.395457 DQM0 = 116, DQM1 = 110
3736 11:16:37.395539 DQ Delay:
3737 11:16:37.398673 DQ0 =120, DQ1 =110, DQ2 =108, DQ3 =112
3738 11:16:37.401898 DQ4 =116, DQ5 =126, DQ6 =128, DQ7 =114
3739 11:16:37.405599 DQ8 =98, DQ9 =100, DQ10 =110, DQ11 =100
3740 11:16:37.412148 DQ12 =118, DQ13 =118, DQ14 =118, DQ15 =120
3741 11:16:37.412256
3742 11:16:37.412338
3743 11:16:37.418936 [DQSOSCAuto] RK1, (LSB)MR18= 0xf2ed, (MSB)MR19= 0x303, tDQSOscB0 = 417 ps tDQSOscB1 = 415 ps
3744 11:16:37.421900 CH1 RK1: MR19=303, MR18=F2ED
3745 11:16:37.428181 CH1_RK1: MR19=0x303, MR18=0xF2ED, DQSOSC=415, MR23=63, INC=38, DEC=25
3746 11:16:37.431383 [RxdqsGatingPostProcess] freq 1200
3747 11:16:37.434737 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3748 11:16:37.438175 best DQS0 dly(2T, 0.5T) = (0, 11)
3749 11:16:37.441593 best DQS1 dly(2T, 0.5T) = (0, 11)
3750 11:16:37.444721 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3751 11:16:37.449027 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3752 11:16:37.451363 best DQS0 dly(2T, 0.5T) = (0, 11)
3753 11:16:37.455461 best DQS1 dly(2T, 0.5T) = (0, 11)
3754 11:16:37.458365 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3755 11:16:37.461198 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3756 11:16:37.464635 Pre-setting of DQS Precalculation
3757 11:16:37.468242 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3758 11:16:37.477648 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3759 11:16:37.484249 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3760 11:16:37.484334
3761 11:16:37.484418
3762 11:16:37.487684 [Calibration Summary] 2400 Mbps
3763 11:16:37.487768 CH 0, Rank 0
3764 11:16:37.491358 SW Impedance : PASS
3765 11:16:37.491442 DUTY Scan : NO K
3766 11:16:37.494047 ZQ Calibration : PASS
3767 11:16:37.497804 Jitter Meter : NO K
3768 11:16:37.497887 CBT Training : PASS
3769 11:16:37.500704 Write leveling : PASS
3770 11:16:37.504126 RX DQS gating : PASS
3771 11:16:37.504209 RX DQ/DQS(RDDQC) : PASS
3772 11:16:37.507765 TX DQ/DQS : PASS
3773 11:16:37.511053 RX DATLAT : PASS
3774 11:16:37.511136 RX DQ/DQS(Engine): PASS
3775 11:16:37.514165 TX OE : NO K
3776 11:16:37.514248 All Pass.
3777 11:16:37.514331
3778 11:16:37.517169 CH 0, Rank 1
3779 11:16:37.517266 SW Impedance : PASS
3780 11:16:37.520486 DUTY Scan : NO K
3781 11:16:37.524136 ZQ Calibration : PASS
3782 11:16:37.524220 Jitter Meter : NO K
3783 11:16:37.527404 CBT Training : PASS
3784 11:16:37.530972 Write leveling : PASS
3785 11:16:37.531055 RX DQS gating : PASS
3786 11:16:37.534139 RX DQ/DQS(RDDQC) : PASS
3787 11:16:37.537387 TX DQ/DQS : PASS
3788 11:16:37.537471 RX DATLAT : PASS
3789 11:16:37.540552 RX DQ/DQS(Engine): PASS
3790 11:16:37.543826 TX OE : NO K
3791 11:16:37.543909 All Pass.
3792 11:16:37.544004
3793 11:16:37.544096 CH 1, Rank 0
3794 11:16:37.547020 SW Impedance : PASS
3795 11:16:37.550447 DUTY Scan : NO K
3796 11:16:37.550528 ZQ Calibration : PASS
3797 11:16:37.553810 Jitter Meter : NO K
3798 11:16:37.556795 CBT Training : PASS
3799 11:16:37.556876 Write leveling : PASS
3800 11:16:37.560687 RX DQS gating : PASS
3801 11:16:37.560767 RX DQ/DQS(RDDQC) : PASS
3802 11:16:37.563456 TX DQ/DQS : PASS
3803 11:16:37.567295 RX DATLAT : PASS
3804 11:16:37.567376 RX DQ/DQS(Engine): PASS
3805 11:16:37.570193 TX OE : NO K
3806 11:16:37.570275 All Pass.
3807 11:16:37.570339
3808 11:16:37.573728 CH 1, Rank 1
3809 11:16:37.573809 SW Impedance : PASS
3810 11:16:37.576927 DUTY Scan : NO K
3811 11:16:37.579713 ZQ Calibration : PASS
3812 11:16:37.579793 Jitter Meter : NO K
3813 11:16:37.583079 CBT Training : PASS
3814 11:16:37.586797 Write leveling : PASS
3815 11:16:37.586884 RX DQS gating : PASS
3816 11:16:37.589978 RX DQ/DQS(RDDQC) : PASS
3817 11:16:37.593646 TX DQ/DQS : PASS
3818 11:16:37.593729 RX DATLAT : PASS
3819 11:16:37.596791 RX DQ/DQS(Engine): PASS
3820 11:16:37.600037 TX OE : NO K
3821 11:16:37.600119 All Pass.
3822 11:16:37.600184
3823 11:16:37.602827 DramC Write-DBI off
3824 11:16:37.602908 PER_BANK_REFRESH: Hybrid Mode
3825 11:16:37.606348 TX_TRACKING: ON
3826 11:16:37.613041 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3827 11:16:37.619471 [FAST_K] Save calibration result to emmc
3828 11:16:37.622960 dramc_set_vcore_voltage set vcore to 650000
3829 11:16:37.623044 Read voltage for 600, 5
3830 11:16:37.626471 Vio18 = 0
3831 11:16:37.626554 Vcore = 650000
3832 11:16:37.626618 Vdram = 0
3833 11:16:37.629727 Vddq = 0
3834 11:16:37.629809 Vmddr = 0
3835 11:16:37.632718 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3836 11:16:37.639126 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3837 11:16:37.642705 MEM_TYPE=3, freq_sel=19
3838 11:16:37.645905 sv_algorithm_assistance_LP4_1600
3839 11:16:37.649126 ============ PULL DRAM RESETB DOWN ============
3840 11:16:37.652284 ========== PULL DRAM RESETB DOWN end =========
3841 11:16:37.659450 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3842 11:16:37.662338 ===================================
3843 11:16:37.662420 LPDDR4 DRAM CONFIGURATION
3844 11:16:37.665985 ===================================
3845 11:16:37.668810 EX_ROW_EN[0] = 0x0
3846 11:16:37.672499 EX_ROW_EN[1] = 0x0
3847 11:16:37.672636 LP4Y_EN = 0x0
3848 11:16:37.675711 WORK_FSP = 0x0
3849 11:16:37.675797 WL = 0x2
3850 11:16:37.678703 RL = 0x2
3851 11:16:37.678784 BL = 0x2
3852 11:16:37.682381 RPST = 0x0
3853 11:16:37.682461 RD_PRE = 0x0
3854 11:16:37.685551 WR_PRE = 0x1
3855 11:16:37.685632 WR_PST = 0x0
3856 11:16:37.688505 DBI_WR = 0x0
3857 11:16:37.688623 DBI_RD = 0x0
3858 11:16:37.692184 OTF = 0x1
3859 11:16:37.695627 ===================================
3860 11:16:37.698869 ===================================
3861 11:16:37.698966 ANA top config
3862 11:16:37.701835 ===================================
3863 11:16:37.705902 DLL_ASYNC_EN = 0
3864 11:16:37.708414 ALL_SLAVE_EN = 1
3865 11:16:37.712356 NEW_RANK_MODE = 1
3866 11:16:37.712438 DLL_IDLE_MODE = 1
3867 11:16:37.715350 LP45_APHY_COMB_EN = 1
3868 11:16:37.718372 TX_ODT_DIS = 1
3869 11:16:37.721768 NEW_8X_MODE = 1
3870 11:16:37.725328 ===================================
3871 11:16:37.728127 ===================================
3872 11:16:37.731641 data_rate = 1200
3873 11:16:37.731722 CKR = 1
3874 11:16:37.735227 DQ_P2S_RATIO = 8
3875 11:16:37.737998 ===================================
3876 11:16:37.741784 CA_P2S_RATIO = 8
3877 11:16:37.744881 DQ_CA_OPEN = 0
3878 11:16:37.748135 DQ_SEMI_OPEN = 0
3879 11:16:37.751310 CA_SEMI_OPEN = 0
3880 11:16:37.751418 CA_FULL_RATE = 0
3881 11:16:37.755286 DQ_CKDIV4_EN = 1
3882 11:16:37.757955 CA_CKDIV4_EN = 1
3883 11:16:37.761426 CA_PREDIV_EN = 0
3884 11:16:37.764690 PH8_DLY = 0
3885 11:16:37.767905 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3886 11:16:37.767993 DQ_AAMCK_DIV = 4
3887 11:16:37.771399 CA_AAMCK_DIV = 4
3888 11:16:37.774632 CA_ADMCK_DIV = 4
3889 11:16:37.777582 DQ_TRACK_CA_EN = 0
3890 11:16:37.780925 CA_PICK = 600
3891 11:16:37.784368 CA_MCKIO = 600
3892 11:16:37.787812 MCKIO_SEMI = 0
3893 11:16:37.787913 PLL_FREQ = 2288
3894 11:16:37.791148 DQ_UI_PI_RATIO = 32
3895 11:16:37.794167 CA_UI_PI_RATIO = 0
3896 11:16:37.797533 ===================================
3897 11:16:37.800857 ===================================
3898 11:16:37.804257 memory_type:LPDDR4
3899 11:16:37.807416 GP_NUM : 10
3900 11:16:37.807498 SRAM_EN : 1
3901 11:16:37.811258 MD32_EN : 0
3902 11:16:37.814409 ===================================
3903 11:16:37.814491 [ANA_INIT] >>>>>>>>>>>>>>
3904 11:16:37.817300 <<<<<< [CONFIGURE PHASE]: ANA_TX
3905 11:16:37.820819 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3906 11:16:37.823987 ===================================
3907 11:16:37.827407 data_rate = 1200,PCW = 0X5800
3908 11:16:37.830937 ===================================
3909 11:16:37.833724 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3910 11:16:37.840894 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3911 11:16:37.847257 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3912 11:16:37.850138 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3913 11:16:37.853654 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3914 11:16:37.856773 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3915 11:16:37.860012 [ANA_INIT] flow start
3916 11:16:37.860094 [ANA_INIT] PLL >>>>>>>>
3917 11:16:37.863607 [ANA_INIT] PLL <<<<<<<<
3918 11:16:37.866831 [ANA_INIT] MIDPI >>>>>>>>
3919 11:16:37.870216 [ANA_INIT] MIDPI <<<<<<<<
3920 11:16:37.870297 [ANA_INIT] DLL >>>>>>>>
3921 11:16:37.873152 [ANA_INIT] flow end
3922 11:16:37.876887 ============ LP4 DIFF to SE enter ============
3923 11:16:37.880315 ============ LP4 DIFF to SE exit ============
3924 11:16:37.883181 [ANA_INIT] <<<<<<<<<<<<<
3925 11:16:37.887006 [Flow] Enable top DCM control >>>>>
3926 11:16:37.889974 [Flow] Enable top DCM control <<<<<
3927 11:16:37.893147 Enable DLL master slave shuffle
3928 11:16:37.899944 ==============================================================
3929 11:16:37.900029 Gating Mode config
3930 11:16:37.906235 ==============================================================
3931 11:16:37.906317 Config description:
3932 11:16:37.916403 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3933 11:16:37.922679 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3934 11:16:37.929484 SELPH_MODE 0: By rank 1: By Phase
3935 11:16:37.932710 ==============================================================
3936 11:16:37.935999 GAT_TRACK_EN = 1
3937 11:16:37.939545 RX_GATING_MODE = 2
3938 11:16:37.943073 RX_GATING_TRACK_MODE = 2
3939 11:16:37.946285 SELPH_MODE = 1
3940 11:16:37.949169 PICG_EARLY_EN = 1
3941 11:16:37.952721 VALID_LAT_VALUE = 1
3942 11:16:37.959161 ==============================================================
3943 11:16:37.962420 Enter into Gating configuration >>>>
3944 11:16:37.966160 Exit from Gating configuration <<<<
3945 11:16:37.969187 Enter into DVFS_PRE_config >>>>>
3946 11:16:37.978787 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3947 11:16:37.982174 Exit from DVFS_PRE_config <<<<<
3948 11:16:37.985807 Enter into PICG configuration >>>>
3949 11:16:37.989112 Exit from PICG configuration <<<<
3950 11:16:37.991880 [RX_INPUT] configuration >>>>>
3951 11:16:37.991962 [RX_INPUT] configuration <<<<<
3952 11:16:37.998697 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3953 11:16:38.005208 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3954 11:16:38.012031 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3955 11:16:38.015004 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3956 11:16:38.021981 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3957 11:16:38.028423 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3958 11:16:38.031641 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3959 11:16:38.035169 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3960 11:16:38.041944 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3961 11:16:38.045286 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3962 11:16:38.048510 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3963 11:16:38.055154 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3964 11:16:38.058107 ===================================
3965 11:16:38.058193 LPDDR4 DRAM CONFIGURATION
3966 11:16:38.061866 ===================================
3967 11:16:38.064978 EX_ROW_EN[0] = 0x0
3968 11:16:38.068084 EX_ROW_EN[1] = 0x0
3969 11:16:38.068192 LP4Y_EN = 0x0
3970 11:16:38.071632 WORK_FSP = 0x0
3971 11:16:38.071713 WL = 0x2
3972 11:16:38.075002 RL = 0x2
3973 11:16:38.075085 BL = 0x2
3974 11:16:38.078290 RPST = 0x0
3975 11:16:38.078373 RD_PRE = 0x0
3976 11:16:38.081075 WR_PRE = 0x1
3977 11:16:38.081157 WR_PST = 0x0
3978 11:16:38.084654 DBI_WR = 0x0
3979 11:16:38.084736 DBI_RD = 0x0
3980 11:16:38.088093 OTF = 0x1
3981 11:16:38.091190 ===================================
3982 11:16:38.094685 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3983 11:16:38.097924 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3984 11:16:38.104289 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3985 11:16:38.107884 ===================================
3986 11:16:38.107967 LPDDR4 DRAM CONFIGURATION
3987 11:16:38.111189 ===================================
3988 11:16:38.114640 EX_ROW_EN[0] = 0x10
3989 11:16:38.117512 EX_ROW_EN[1] = 0x0
3990 11:16:38.117594 LP4Y_EN = 0x0
3991 11:16:38.120866 WORK_FSP = 0x0
3992 11:16:38.120948 WL = 0x2
3993 11:16:38.124195 RL = 0x2
3994 11:16:38.124276 BL = 0x2
3995 11:16:38.127380 RPST = 0x0
3996 11:16:38.127462 RD_PRE = 0x0
3997 11:16:38.130725 WR_PRE = 0x1
3998 11:16:38.130806 WR_PST = 0x0
3999 11:16:38.134107 DBI_WR = 0x0
4000 11:16:38.134190 DBI_RD = 0x0
4001 11:16:38.137425 OTF = 0x1
4002 11:16:38.140747 ===================================
4003 11:16:38.146990 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4004 11:16:38.150516 nWR fixed to 30
4005 11:16:38.154479 [ModeRegInit_LP4] CH0 RK0
4006 11:16:38.154565 [ModeRegInit_LP4] CH0 RK1
4007 11:16:38.156935 [ModeRegInit_LP4] CH1 RK0
4008 11:16:38.160334 [ModeRegInit_LP4] CH1 RK1
4009 11:16:38.160417 match AC timing 17
4010 11:16:38.167339 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
4011 11:16:38.170536 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4012 11:16:38.173521 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
4013 11:16:38.180350 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
4014 11:16:38.183530 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
4015 11:16:38.183615 ==
4016 11:16:38.186639 Dram Type= 6, Freq= 0, CH_0, rank 0
4017 11:16:38.190565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4018 11:16:38.190650 ==
4019 11:16:38.197084 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4020 11:16:38.203150 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4021 11:16:38.206829 [CA 0] Center 36 (6~66) winsize 61
4022 11:16:38.209580 [CA 1] Center 36 (6~66) winsize 61
4023 11:16:38.212964 [CA 2] Center 34 (4~65) winsize 62
4024 11:16:38.216148 [CA 3] Center 34 (3~65) winsize 63
4025 11:16:38.220122 [CA 4] Center 33 (3~64) winsize 62
4026 11:16:38.223207 [CA 5] Center 33 (3~64) winsize 62
4027 11:16:38.223290
4028 11:16:38.226829 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4029 11:16:38.226913
4030 11:16:38.230563 [CATrainingPosCal] consider 1 rank data
4031 11:16:38.233208 u2DelayCellTimex100 = 270/100 ps
4032 11:16:38.236526 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4033 11:16:38.239713 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4034 11:16:38.242943 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4035 11:16:38.246287 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4036 11:16:38.249712 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4037 11:16:38.256025 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4038 11:16:38.256128
4039 11:16:38.259681 CA PerBit enable=1, Macro0, CA PI delay=33
4040 11:16:38.259763
4041 11:16:38.262979 [CBTSetCACLKResult] CA Dly = 33
4042 11:16:38.263061 CS Dly: 6 (0~37)
4043 11:16:38.263124 ==
4044 11:16:38.266083 Dram Type= 6, Freq= 0, CH_0, rank 1
4045 11:16:38.269366 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4046 11:16:38.272764 ==
4047 11:16:38.275970 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4048 11:16:38.282452 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4049 11:16:38.285667 [CA 0] Center 36 (6~66) winsize 61
4050 11:16:38.289271 [CA 1] Center 36 (6~66) winsize 61
4051 11:16:38.292407 [CA 2] Center 33 (3~64) winsize 62
4052 11:16:38.296089 [CA 3] Center 33 (3~64) winsize 62
4053 11:16:38.299149 [CA 4] Center 33 (2~64) winsize 63
4054 11:16:38.302229 [CA 5] Center 33 (2~64) winsize 63
4055 11:16:38.302309
4056 11:16:38.305833 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4057 11:16:38.305943
4058 11:16:38.308812 [CATrainingPosCal] consider 2 rank data
4059 11:16:38.312511 u2DelayCellTimex100 = 270/100 ps
4060 11:16:38.315850 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4061 11:16:38.318824 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4062 11:16:38.325564 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4063 11:16:38.328443 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4064 11:16:38.331717 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4065 11:16:38.335301 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4066 11:16:38.335382
4067 11:16:38.338467 CA PerBit enable=1, Macro0, CA PI delay=33
4068 11:16:38.338548
4069 11:16:38.341633 [CBTSetCACLKResult] CA Dly = 33
4070 11:16:38.341715 CS Dly: 5 (0~36)
4071 11:16:38.345529
4072 11:16:38.348413 ----->DramcWriteLeveling(PI) begin...
4073 11:16:38.348497 ==
4074 11:16:38.351691 Dram Type= 6, Freq= 0, CH_0, rank 0
4075 11:16:38.355228 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4076 11:16:38.355315 ==
4077 11:16:38.358616 Write leveling (Byte 0): 34 => 34
4078 11:16:38.362855 Write leveling (Byte 1): 31 => 31
4079 11:16:38.365706 DramcWriteLeveling(PI) end<-----
4080 11:16:38.365791
4081 11:16:38.365854 ==
4082 11:16:38.368711 Dram Type= 6, Freq= 0, CH_0, rank 0
4083 11:16:38.371566 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4084 11:16:38.371650 ==
4085 11:16:38.375028 [Gating] SW mode calibration
4086 11:16:38.381768 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4087 11:16:38.388083 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4088 11:16:38.391800 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4089 11:16:38.395123 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4090 11:16:38.401472 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4091 11:16:38.404976 0 9 12 | B1->B0 | 3434 3333 | 1 0 | (1 0) (0 1)
4092 11:16:38.408056 0 9 16 | B1->B0 | 2f2f 2626 | 0 0 | (0 0) (0 0)
4093 11:16:38.415062 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4094 11:16:38.418202 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4095 11:16:38.421492 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4096 11:16:38.427855 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4097 11:16:38.430989 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4098 11:16:38.434709 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4099 11:16:38.441232 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4100 11:16:38.444372 0 10 16 | B1->B0 | 3636 3c3c | 0 0 | (0 0) (0 0)
4101 11:16:38.447620 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4102 11:16:38.454912 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4103 11:16:38.457807 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4104 11:16:38.460551 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4105 11:16:38.468141 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4106 11:16:38.470894 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4107 11:16:38.473961 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4108 11:16:38.480765 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4109 11:16:38.484251 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4110 11:16:38.487219 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4111 11:16:38.493821 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4112 11:16:38.497180 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4113 11:16:38.500675 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4114 11:16:38.506951 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4115 11:16:38.510217 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4116 11:16:38.513524 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4117 11:16:38.519979 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4118 11:16:38.523903 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4119 11:16:38.527190 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4120 11:16:38.533315 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4121 11:16:38.536926 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4122 11:16:38.540509 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4123 11:16:38.546436 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4124 11:16:38.549870 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4125 11:16:38.553125 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4126 11:16:38.556852 Total UI for P1: 0, mck2ui 16
4127 11:16:38.560480 best dqsien dly found for B0: ( 0, 13, 16)
4128 11:16:38.562773 Total UI for P1: 0, mck2ui 16
4129 11:16:38.566313 best dqsien dly found for B1: ( 0, 13, 16)
4130 11:16:38.569593 best DQS0 dly(MCK, UI, PI) = (0, 13, 16)
4131 11:16:38.572685 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4132 11:16:38.572766
4133 11:16:38.579833 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 16)
4134 11:16:38.582933 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4135 11:16:38.585912 [Gating] SW calibration Done
4136 11:16:38.585992 ==
4137 11:16:38.589543 Dram Type= 6, Freq= 0, CH_0, rank 0
4138 11:16:38.592701 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4139 11:16:38.592781 ==
4140 11:16:38.592845 RX Vref Scan: 0
4141 11:16:38.592903
4142 11:16:38.595785 RX Vref 0 -> 0, step: 1
4143 11:16:38.595865
4144 11:16:38.599575 RX Delay -230 -> 252, step: 16
4145 11:16:38.602461 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4146 11:16:38.606330 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4147 11:16:38.612411 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4148 11:16:38.615642 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4149 11:16:38.619355 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4150 11:16:38.622342 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4151 11:16:38.628947 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4152 11:16:38.632473 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4153 11:16:38.635690 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4154 11:16:38.638859 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4155 11:16:38.645380 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4156 11:16:38.648728 iDelay=218, Bit 11, Center 17 (-150 ~ 185) 336
4157 11:16:38.652139 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4158 11:16:38.655341 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4159 11:16:38.661705 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4160 11:16:38.665362 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4161 11:16:38.665443 ==
4162 11:16:38.668487 Dram Type= 6, Freq= 0, CH_0, rank 0
4163 11:16:38.671955 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4164 11:16:38.672036 ==
4165 11:16:38.675155 DQS Delay:
4166 11:16:38.675235 DQS0 = 0, DQS1 = 0
4167 11:16:38.675298 DQM Delay:
4168 11:16:38.678190 DQM0 = 43, DQM1 = 29
4169 11:16:38.678270 DQ Delay:
4170 11:16:38.681476 DQ0 =41, DQ1 =49, DQ2 =33, DQ3 =33
4171 11:16:38.684829 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =57
4172 11:16:38.688047 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =17
4173 11:16:38.691440 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4174 11:16:38.691520
4175 11:16:38.691582
4176 11:16:38.691639 ==
4177 11:16:38.694603 Dram Type= 6, Freq= 0, CH_0, rank 0
4178 11:16:38.701734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4179 11:16:38.701815 ==
4180 11:16:38.701879
4181 11:16:38.701935
4182 11:16:38.701991 TX Vref Scan disable
4183 11:16:38.705402 == TX Byte 0 ==
4184 11:16:38.708629 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4185 11:16:38.714984 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4186 11:16:38.715064 == TX Byte 1 ==
4187 11:16:38.718737 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4188 11:16:38.724926 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4189 11:16:38.725006 ==
4190 11:16:38.728772 Dram Type= 6, Freq= 0, CH_0, rank 0
4191 11:16:38.731444 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4192 11:16:38.731525 ==
4193 11:16:38.731588
4194 11:16:38.731645
4195 11:16:38.734961 TX Vref Scan disable
4196 11:16:38.738222 == TX Byte 0 ==
4197 11:16:38.741674 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4198 11:16:38.744645 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4199 11:16:38.747627 == TX Byte 1 ==
4200 11:16:38.750964 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4201 11:16:38.754664 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4202 11:16:38.754747
4203 11:16:38.757603 [DATLAT]
4204 11:16:38.757707 Freq=600, CH0 RK0
4205 11:16:38.757797
4206 11:16:38.760968 DATLAT Default: 0x9
4207 11:16:38.761049 0, 0xFFFF, sum = 0
4208 11:16:38.764757 1, 0xFFFF, sum = 0
4209 11:16:38.764838 2, 0xFFFF, sum = 0
4210 11:16:38.767899 3, 0xFFFF, sum = 0
4211 11:16:38.767980 4, 0xFFFF, sum = 0
4212 11:16:38.771261 5, 0xFFFF, sum = 0
4213 11:16:38.771343 6, 0xFFFF, sum = 0
4214 11:16:38.774687 7, 0xFFFF, sum = 0
4215 11:16:38.774769 8, 0x0, sum = 1
4216 11:16:38.778192 9, 0x0, sum = 2
4217 11:16:38.778274 10, 0x0, sum = 3
4218 11:16:38.781218 11, 0x0, sum = 4
4219 11:16:38.781299 best_step = 9
4220 11:16:38.781362
4221 11:16:38.781435 ==
4222 11:16:38.783973 Dram Type= 6, Freq= 0, CH_0, rank 0
4223 11:16:38.787644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4224 11:16:38.787750 ==
4225 11:16:38.790832 RX Vref Scan: 1
4226 11:16:38.790912
4227 11:16:38.794069 RX Vref 0 -> 0, step: 1
4228 11:16:38.794149
4229 11:16:38.794213 RX Delay -195 -> 252, step: 8
4230 11:16:38.797396
4231 11:16:38.797476 Set Vref, RX VrefLevel [Byte0]: 57
4232 11:16:38.800695 [Byte1]: 57
4233 11:16:38.805560
4234 11:16:38.805680 Final RX Vref Byte 0 = 57 to rank0
4235 11:16:38.809006 Final RX Vref Byte 1 = 57 to rank0
4236 11:16:38.812337 Final RX Vref Byte 0 = 57 to rank1
4237 11:16:38.815698 Final RX Vref Byte 1 = 57 to rank1==
4238 11:16:38.818729 Dram Type= 6, Freq= 0, CH_0, rank 0
4239 11:16:38.825625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4240 11:16:38.825715 ==
4241 11:16:38.825805 DQS Delay:
4242 11:16:38.828828 DQS0 = 0, DQS1 = 0
4243 11:16:38.828925 DQM Delay:
4244 11:16:38.829022 DQM0 = 43, DQM1 = 32
4245 11:16:38.831939 DQ Delay:
4246 11:16:38.835599 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =40
4247 11:16:38.838803 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =52
4248 11:16:38.842036 DQ8 =20, DQ9 =20, DQ10 =32, DQ11 =24
4249 11:16:38.845994 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4250 11:16:38.846079
4251 11:16:38.846144
4252 11:16:38.852157 [DQSOSCAuto] RK0, (LSB)MR18= 0x6840, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 390 ps
4253 11:16:38.855326 CH0 RK0: MR19=808, MR18=6840
4254 11:16:38.861771 CH0_RK0: MR19=0x808, MR18=0x6840, DQSOSC=390, MR23=63, INC=172, DEC=114
4255 11:16:38.861872
4256 11:16:38.865072 ----->DramcWriteLeveling(PI) begin...
4257 11:16:38.865159 ==
4258 11:16:38.868187 Dram Type= 6, Freq= 0, CH_0, rank 1
4259 11:16:38.871439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4260 11:16:38.871524 ==
4261 11:16:38.874626 Write leveling (Byte 0): 34 => 34
4262 11:16:38.877721 Write leveling (Byte 1): 33 => 33
4263 11:16:38.881413 DramcWriteLeveling(PI) end<-----
4264 11:16:38.881497
4265 11:16:38.881561 ==
4266 11:16:38.884346 Dram Type= 6, Freq= 0, CH_0, rank 1
4267 11:16:38.891219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4268 11:16:38.891312 ==
4269 11:16:38.891379 [Gating] SW mode calibration
4270 11:16:38.901047 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4271 11:16:38.904379 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4272 11:16:38.907610 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4273 11:16:38.914387 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4274 11:16:38.917501 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4275 11:16:38.920710 0 9 12 | B1->B0 | 3333 3333 | 0 1 | (0 1) (1 1)
4276 11:16:38.927286 0 9 16 | B1->B0 | 2f2f 2c2c | 0 0 | (0 0) (0 0)
4277 11:16:38.930973 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4278 11:16:38.937717 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4279 11:16:38.940378 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4280 11:16:38.943627 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4281 11:16:38.947139 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4282 11:16:38.953631 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4283 11:16:38.957482 0 10 12 | B1->B0 | 2424 2727 | 0 0 | (0 0) (0 0)
4284 11:16:38.960243 0 10 16 | B1->B0 | 3b3b 4242 | 0 0 | (0 0) (0 0)
4285 11:16:38.967383 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4286 11:16:38.970405 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4287 11:16:38.973699 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4288 11:16:38.980201 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4289 11:16:38.983514 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4290 11:16:38.986998 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4291 11:16:38.993184 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4292 11:16:38.996851 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4293 11:16:39.000113 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4294 11:16:39.006574 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4295 11:16:39.009940 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4296 11:16:39.013461 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4297 11:16:39.019688 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4298 11:16:39.023142 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4299 11:16:39.026584 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4300 11:16:39.032722 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4301 11:16:39.035832 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4302 11:16:39.042659 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4303 11:16:39.045980 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4304 11:16:39.049122 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4305 11:16:39.052688 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4306 11:16:39.058983 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4307 11:16:39.062286 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4308 11:16:39.069573 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4309 11:16:39.069664 Total UI for P1: 0, mck2ui 16
4310 11:16:39.072449 best dqsien dly found for B0: ( 0, 13, 12)
4311 11:16:39.078981 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4312 11:16:39.082231 Total UI for P1: 0, mck2ui 16
4313 11:16:39.086559 best dqsien dly found for B1: ( 0, 13, 16)
4314 11:16:39.088754 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4315 11:16:39.092205 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4316 11:16:39.092288
4317 11:16:39.095782 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4318 11:16:39.099305 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4319 11:16:39.102241 [Gating] SW calibration Done
4320 11:16:39.102323 ==
4321 11:16:39.105279 Dram Type= 6, Freq= 0, CH_0, rank 1
4322 11:16:39.108571 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4323 11:16:39.108654 ==
4324 11:16:39.112259 RX Vref Scan: 0
4325 11:16:39.112339
4326 11:16:39.115297 RX Vref 0 -> 0, step: 1
4327 11:16:39.115379
4328 11:16:39.115443 RX Delay -230 -> 252, step: 16
4329 11:16:39.122166 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4330 11:16:39.125714 iDelay=218, Bit 1, Center 41 (-134 ~ 217) 352
4331 11:16:39.128651 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4332 11:16:39.132672 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4333 11:16:39.138941 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4334 11:16:39.141884 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4335 11:16:39.145325 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4336 11:16:39.148842 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4337 11:16:39.154965 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4338 11:16:39.159118 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4339 11:16:39.161795 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4340 11:16:39.165170 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4341 11:16:39.171603 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4342 11:16:39.175056 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4343 11:16:39.178090 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4344 11:16:39.181479 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4345 11:16:39.181560 ==
4346 11:16:39.185499 Dram Type= 6, Freq= 0, CH_0, rank 1
4347 11:16:39.191151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4348 11:16:39.191232 ==
4349 11:16:39.191296 DQS Delay:
4350 11:16:39.194693 DQS0 = 0, DQS1 = 0
4351 11:16:39.194773 DQM Delay:
4352 11:16:39.194837 DQM0 = 40, DQM1 = 33
4353 11:16:39.197860 DQ Delay:
4354 11:16:39.201495 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4355 11:16:39.204475 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4356 11:16:39.208139 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33
4357 11:16:39.211352 DQ12 =33, DQ13 =41, DQ14 =49, DQ15 =33
4358 11:16:39.211433
4359 11:16:39.211497
4360 11:16:39.211554 ==
4361 11:16:39.214481 Dram Type= 6, Freq= 0, CH_0, rank 1
4362 11:16:39.217879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4363 11:16:39.217959 ==
4364 11:16:39.218020
4365 11:16:39.218077
4366 11:16:39.221035 TX Vref Scan disable
4367 11:16:39.224451 == TX Byte 0 ==
4368 11:16:39.227678 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4369 11:16:39.230870 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4370 11:16:39.234899 == TX Byte 1 ==
4371 11:16:39.237429 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4372 11:16:39.240719 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4373 11:16:39.240797 ==
4374 11:16:39.243915 Dram Type= 6, Freq= 0, CH_0, rank 1
4375 11:16:39.247488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4376 11:16:39.250792 ==
4377 11:16:39.250869
4378 11:16:39.250929
4379 11:16:39.250985 TX Vref Scan disable
4380 11:16:39.254607 == TX Byte 0 ==
4381 11:16:39.258097 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4382 11:16:39.264972 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4383 11:16:39.265050 == TX Byte 1 ==
4384 11:16:39.268013 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4385 11:16:39.274264 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4386 11:16:39.274341
4387 11:16:39.274402 [DATLAT]
4388 11:16:39.274458 Freq=600, CH0 RK1
4389 11:16:39.274513
4390 11:16:39.277582 DATLAT Default: 0x9
4391 11:16:39.280805 0, 0xFFFF, sum = 0
4392 11:16:39.280913 1, 0xFFFF, sum = 0
4393 11:16:39.284071 2, 0xFFFF, sum = 0
4394 11:16:39.284149 3, 0xFFFF, sum = 0
4395 11:16:39.287397 4, 0xFFFF, sum = 0
4396 11:16:39.287475 5, 0xFFFF, sum = 0
4397 11:16:39.290656 6, 0xFFFF, sum = 0
4398 11:16:39.290734 7, 0xFFFF, sum = 0
4399 11:16:39.294342 8, 0x0, sum = 1
4400 11:16:39.294420 9, 0x0, sum = 2
4401 11:16:39.297358 10, 0x0, sum = 3
4402 11:16:39.297437 11, 0x0, sum = 4
4403 11:16:39.297514 best_step = 9
4404 11:16:39.297586
4405 11:16:39.301318 ==
4406 11:16:39.304433 Dram Type= 6, Freq= 0, CH_0, rank 1
4407 11:16:39.307982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4408 11:16:39.308060 ==
4409 11:16:39.308120 RX Vref Scan: 0
4410 11:16:39.308175
4411 11:16:39.310797 RX Vref 0 -> 0, step: 1
4412 11:16:39.310874
4413 11:16:39.314083 RX Delay -195 -> 252, step: 8
4414 11:16:39.320751 iDelay=205, Bit 0, Center 36 (-115 ~ 188) 304
4415 11:16:39.323891 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4416 11:16:39.327657 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4417 11:16:39.330619 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4418 11:16:39.337195 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4419 11:16:39.340470 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4420 11:16:39.343807 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4421 11:16:39.346953 iDelay=205, Bit 7, Center 48 (-107 ~ 204) 312
4422 11:16:39.350331 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4423 11:16:39.357308 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4424 11:16:39.360246 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4425 11:16:39.363498 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4426 11:16:39.366384 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4427 11:16:39.373079 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4428 11:16:39.376211 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4429 11:16:39.380261 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4430 11:16:39.380341 ==
4431 11:16:39.383031 Dram Type= 6, Freq= 0, CH_0, rank 1
4432 11:16:39.390037 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4433 11:16:39.390118 ==
4434 11:16:39.390182 DQS Delay:
4435 11:16:39.392986 DQS0 = 0, DQS1 = 0
4436 11:16:39.393066 DQM Delay:
4437 11:16:39.393130 DQM0 = 41, DQM1 = 36
4438 11:16:39.395925 DQ Delay:
4439 11:16:39.399469 DQ0 =36, DQ1 =44, DQ2 =36, DQ3 =40
4440 11:16:39.402711 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4441 11:16:39.406408 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4442 11:16:39.410176 DQ12 =44, DQ13 =44, DQ14 =44, DQ15 =44
4443 11:16:39.410256
4444 11:16:39.410319
4445 11:16:39.416190 [DQSOSCAuto] RK1, (LSB)MR18= 0x6417, (MSB)MR19= 0x808, tDQSOscB0 = 405 ps tDQSOscB1 = 391 ps
4446 11:16:39.419054 CH0 RK1: MR19=808, MR18=6417
4447 11:16:39.425907 CH0_RK1: MR19=0x808, MR18=0x6417, DQSOSC=391, MR23=63, INC=171, DEC=114
4448 11:16:39.429050 [RxdqsGatingPostProcess] freq 600
4449 11:16:39.432739 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4450 11:16:39.436016 Pre-setting of DQS Precalculation
4451 11:16:39.442159 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4452 11:16:39.442241 ==
4453 11:16:39.445796 Dram Type= 6, Freq= 0, CH_1, rank 0
4454 11:16:39.448915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4455 11:16:39.448996 ==
4456 11:16:39.455746 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4457 11:16:39.462378 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4458 11:16:39.465320 [CA 0] Center 35 (5~66) winsize 62
4459 11:16:39.468902 [CA 1] Center 35 (5~66) winsize 62
4460 11:16:39.471865 [CA 2] Center 34 (4~65) winsize 62
4461 11:16:39.475518 [CA 3] Center 33 (3~64) winsize 62
4462 11:16:39.478918 [CA 4] Center 34 (4~64) winsize 61
4463 11:16:39.482817 [CA 5] Center 33 (3~64) winsize 62
4464 11:16:39.482898
4465 11:16:39.485182 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4466 11:16:39.485263
4467 11:16:39.488476 [CATrainingPosCal] consider 1 rank data
4468 11:16:39.492056 u2DelayCellTimex100 = 270/100 ps
4469 11:16:39.495220 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4470 11:16:39.498497 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4471 11:16:39.501637 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4472 11:16:39.505639 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4473 11:16:39.508149 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4474 11:16:39.512418 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4475 11:16:39.512561
4476 11:16:39.518113 CA PerBit enable=1, Macro0, CA PI delay=33
4477 11:16:39.518195
4478 11:16:39.521333 [CBTSetCACLKResult] CA Dly = 33
4479 11:16:39.521413 CS Dly: 6 (0~37)
4480 11:16:39.521477 ==
4481 11:16:39.524996 Dram Type= 6, Freq= 0, CH_1, rank 1
4482 11:16:39.528621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4483 11:16:39.528703 ==
4484 11:16:39.534517 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4485 11:16:39.541034 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4486 11:16:39.544629 [CA 0] Center 35 (5~66) winsize 62
4487 11:16:39.547904 [CA 1] Center 36 (6~66) winsize 61
4488 11:16:39.551421 [CA 2] Center 34 (4~65) winsize 62
4489 11:16:39.554430 [CA 3] Center 34 (4~65) winsize 62
4490 11:16:39.557546 [CA 4] Center 34 (3~65) winsize 63
4491 11:16:39.560942 [CA 5] Center 34 (3~65) winsize 63
4492 11:16:39.561077
4493 11:16:39.564409 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4494 11:16:39.564643
4495 11:16:39.567752 [CATrainingPosCal] consider 2 rank data
4496 11:16:39.571094 u2DelayCellTimex100 = 270/100 ps
4497 11:16:39.574285 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4498 11:16:39.577488 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4499 11:16:39.581584 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4500 11:16:39.588150 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4501 11:16:39.591732 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4502 11:16:39.594058 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4503 11:16:39.594222
4504 11:16:39.597737 CA PerBit enable=1, Macro0, CA PI delay=33
4505 11:16:39.597885
4506 11:16:39.600906 [CBTSetCACLKResult] CA Dly = 33
4507 11:16:39.601090 CS Dly: 6 (0~37)
4508 11:16:39.601183
4509 11:16:39.604186 ----->DramcWriteLeveling(PI) begin...
4510 11:16:39.607189 ==
4511 11:16:39.610419 Dram Type= 6, Freq= 0, CH_1, rank 0
4512 11:16:39.613886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4513 11:16:39.614019 ==
4514 11:16:39.617122 Write leveling (Byte 0): 29 => 29
4515 11:16:39.620867 Write leveling (Byte 1): 31 => 31
4516 11:16:39.623783 DramcWriteLeveling(PI) end<-----
4517 11:16:39.624028
4518 11:16:39.624166 ==
4519 11:16:39.627130 Dram Type= 6, Freq= 0, CH_1, rank 0
4520 11:16:39.631009 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4521 11:16:39.631321 ==
4522 11:16:39.633841 [Gating] SW mode calibration
4523 11:16:39.640478 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4524 11:16:39.647392 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4525 11:16:39.650062 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4526 11:16:39.653300 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4527 11:16:39.659911 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4528 11:16:39.663532 0 9 12 | B1->B0 | 3131 2f2f | 0 0 | (0 0) (1 0)
4529 11:16:39.666706 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4530 11:16:39.673052 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4531 11:16:39.676254 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4532 11:16:39.679842 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4533 11:16:39.686366 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4534 11:16:39.689790 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4535 11:16:39.692833 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (1 1)
4536 11:16:39.699292 0 10 12 | B1->B0 | 3131 3a3a | 0 0 | (0 0) (0 0)
4537 11:16:39.702588 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4538 11:16:39.705914 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4539 11:16:39.712672 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4540 11:16:39.715871 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4541 11:16:39.719525 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4542 11:16:39.726031 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4543 11:16:39.729135 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4544 11:16:39.732455 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4545 11:16:39.739209 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4546 11:16:39.742433 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4547 11:16:39.745917 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4548 11:16:39.752443 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4549 11:16:39.755569 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4550 11:16:39.758869 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4551 11:16:39.762231 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4552 11:16:39.768735 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4553 11:16:39.771878 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4554 11:16:39.775333 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4555 11:16:39.782380 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4556 11:16:39.785253 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4557 11:16:39.788771 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4558 11:16:39.795440 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4559 11:16:39.798548 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4560 11:16:39.802094 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4561 11:16:39.808688 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4562 11:16:39.811754 Total UI for P1: 0, mck2ui 16
4563 11:16:39.815300 best dqsien dly found for B0: ( 0, 13, 10)
4564 11:16:39.818730 Total UI for P1: 0, mck2ui 16
4565 11:16:39.821859 best dqsien dly found for B1: ( 0, 13, 14)
4566 11:16:39.824956 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4567 11:16:39.828228 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4568 11:16:39.828310
4569 11:16:39.831296 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4570 11:16:39.834938 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4571 11:16:39.837963 [Gating] SW calibration Done
4572 11:16:39.838052 ==
4573 11:16:39.841349 Dram Type= 6, Freq= 0, CH_1, rank 0
4574 11:16:39.844913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4575 11:16:39.847937 ==
4576 11:16:39.848019 RX Vref Scan: 0
4577 11:16:39.848083
4578 11:16:39.851082 RX Vref 0 -> 0, step: 1
4579 11:16:39.851164
4580 11:16:39.854587 RX Delay -230 -> 252, step: 16
4581 11:16:39.857885 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4582 11:16:39.861293 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4583 11:16:39.864995 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4584 11:16:39.870625 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4585 11:16:39.874590 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4586 11:16:39.877633 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4587 11:16:39.880506 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4588 11:16:39.884273 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4589 11:16:39.890750 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4590 11:16:39.894057 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4591 11:16:39.898150 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4592 11:16:39.900696 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4593 11:16:39.907311 iDelay=218, Bit 12, Center 41 (-134 ~ 217) 352
4594 11:16:39.910674 iDelay=218, Bit 13, Center 41 (-134 ~ 217) 352
4595 11:16:39.914258 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4596 11:16:39.917148 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4597 11:16:39.920285 ==
4598 11:16:39.920367 Dram Type= 6, Freq= 0, CH_1, rank 0
4599 11:16:39.927111 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4600 11:16:39.927193 ==
4601 11:16:39.927258 DQS Delay:
4602 11:16:39.930931 DQS0 = 0, DQS1 = 0
4603 11:16:39.931012 DQM Delay:
4604 11:16:39.934414 DQM0 = 46, DQM1 = 35
4605 11:16:39.934495 DQ Delay:
4606 11:16:39.937431 DQ0 =57, DQ1 =41, DQ2 =33, DQ3 =41
4607 11:16:39.940339 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4608 11:16:39.943603 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4609 11:16:39.947100 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =49
4610 11:16:39.947181
4611 11:16:39.947242
4612 11:16:39.947299 ==
4613 11:16:39.950101 Dram Type= 6, Freq= 0, CH_1, rank 0
4614 11:16:39.953793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4615 11:16:39.953874 ==
4616 11:16:39.953936
4617 11:16:39.953993
4618 11:16:39.956777 TX Vref Scan disable
4619 11:16:39.960156 == TX Byte 0 ==
4620 11:16:39.963431 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4621 11:16:39.966862 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4622 11:16:39.969982 == TX Byte 1 ==
4623 11:16:39.974012 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4624 11:16:39.976898 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4625 11:16:39.976978 ==
4626 11:16:39.980635 Dram Type= 6, Freq= 0, CH_1, rank 0
4627 11:16:39.986464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4628 11:16:39.986549 ==
4629 11:16:39.986612
4630 11:16:39.986669
4631 11:16:39.986726 TX Vref Scan disable
4632 11:16:39.990930 == TX Byte 0 ==
4633 11:16:39.994064 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4634 11:16:40.001274 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4635 11:16:40.001355 == TX Byte 1 ==
4636 11:16:40.003871 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4637 11:16:40.010731 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4638 11:16:40.010813
4639 11:16:40.010876 [DATLAT]
4640 11:16:40.010933 Freq=600, CH1 RK0
4641 11:16:40.010990
4642 11:16:40.013830 DATLAT Default: 0x9
4643 11:16:40.013910 0, 0xFFFF, sum = 0
4644 11:16:40.017432 1, 0xFFFF, sum = 0
4645 11:16:40.020698 2, 0xFFFF, sum = 0
4646 11:16:40.020780 3, 0xFFFF, sum = 0
4647 11:16:40.023579 4, 0xFFFF, sum = 0
4648 11:16:40.023659 5, 0xFFFF, sum = 0
4649 11:16:40.026935 6, 0xFFFF, sum = 0
4650 11:16:40.027019 7, 0xFFFF, sum = 0
4651 11:16:40.031046 8, 0x0, sum = 1
4652 11:16:40.031127 9, 0x0, sum = 2
4653 11:16:40.031193 10, 0x0, sum = 3
4654 11:16:40.033543 11, 0x0, sum = 4
4655 11:16:40.033624 best_step = 9
4656 11:16:40.033687
4657 11:16:40.037288 ==
4658 11:16:40.037368 Dram Type= 6, Freq= 0, CH_1, rank 0
4659 11:16:40.043458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4660 11:16:40.043540 ==
4661 11:16:40.043603 RX Vref Scan: 1
4662 11:16:40.043661
4663 11:16:40.046831 RX Vref 0 -> 0, step: 1
4664 11:16:40.046911
4665 11:16:40.050341 RX Delay -195 -> 252, step: 8
4666 11:16:40.050496
4667 11:16:40.053611 Set Vref, RX VrefLevel [Byte0]: 47
4668 11:16:40.056918 [Byte1]: 53
4669 11:16:40.056999
4670 11:16:40.060294 Final RX Vref Byte 0 = 47 to rank0
4671 11:16:40.063808 Final RX Vref Byte 1 = 53 to rank0
4672 11:16:40.066799 Final RX Vref Byte 0 = 47 to rank1
4673 11:16:40.070034 Final RX Vref Byte 1 = 53 to rank1==
4674 11:16:40.073529 Dram Type= 6, Freq= 0, CH_1, rank 0
4675 11:16:40.076399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4676 11:16:40.079770 ==
4677 11:16:40.079851 DQS Delay:
4678 11:16:40.079915 DQS0 = 0, DQS1 = 0
4679 11:16:40.083229 DQM Delay:
4680 11:16:40.083309 DQM0 = 44, DQM1 = 35
4681 11:16:40.086407 DQ Delay:
4682 11:16:40.086487 DQ0 =48, DQ1 =40, DQ2 =36, DQ3 =40
4683 11:16:40.089836 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =36
4684 11:16:40.093298 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =24
4685 11:16:40.096349 DQ12 =44, DQ13 =40, DQ14 =48, DQ15 =44
4686 11:16:40.096430
4687 11:16:40.099895
4688 11:16:40.106660 [DQSOSCAuto] RK0, (LSB)MR18= 0x4a2f, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 395 ps
4689 11:16:40.109892 CH1 RK0: MR19=808, MR18=4A2F
4690 11:16:40.116495 CH1_RK0: MR19=0x808, MR18=0x4A2F, DQSOSC=395, MR23=63, INC=168, DEC=112
4691 11:16:40.116608
4692 11:16:40.119632 ----->DramcWriteLeveling(PI) begin...
4693 11:16:40.119713 ==
4694 11:16:40.122998 Dram Type= 6, Freq= 0, CH_1, rank 1
4695 11:16:40.126236 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4696 11:16:40.126318 ==
4697 11:16:40.129535 Write leveling (Byte 0): 30 => 30
4698 11:16:40.132512 Write leveling (Byte 1): 30 => 30
4699 11:16:40.135933 DramcWriteLeveling(PI) end<-----
4700 11:16:40.136013
4701 11:16:40.136076 ==
4702 11:16:40.139764 Dram Type= 6, Freq= 0, CH_1, rank 1
4703 11:16:40.142773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4704 11:16:40.142855 ==
4705 11:16:40.146426 [Gating] SW mode calibration
4706 11:16:40.152282 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4707 11:16:40.159178 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4708 11:16:40.162180 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4709 11:16:40.169095 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4710 11:16:40.172149 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4711 11:16:40.175826 0 9 12 | B1->B0 | 3131 3333 | 1 1 | (0 1) (1 0)
4712 11:16:40.182459 0 9 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
4713 11:16:40.185554 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4714 11:16:40.188707 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4715 11:16:40.195013 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4716 11:16:40.198283 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4717 11:16:40.201881 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4718 11:16:40.208309 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4719 11:16:40.211721 0 10 12 | B1->B0 | 3232 2e2e | 0 1 | (0 0) (0 0)
4720 11:16:40.214811 0 10 16 | B1->B0 | 4545 4343 | 0 0 | (0 0) (0 0)
4721 11:16:40.221751 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4722 11:16:40.224921 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4723 11:16:40.228147 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4724 11:16:40.234567 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4725 11:16:40.238124 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4726 11:16:40.241537 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4727 11:16:40.247895 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4728 11:16:40.251449 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4729 11:16:40.254529 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4730 11:16:40.260959 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4731 11:16:40.264802 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4732 11:16:40.267765 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4733 11:16:40.274841 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4734 11:16:40.277441 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4735 11:16:40.281067 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4736 11:16:40.287671 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4737 11:16:40.290773 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4738 11:16:40.294214 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4739 11:16:40.300906 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4740 11:16:40.304106 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4741 11:16:40.307170 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4742 11:16:40.313958 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4743 11:16:40.317198 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4744 11:16:40.320766 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4745 11:16:40.323824 Total UI for P1: 0, mck2ui 16
4746 11:16:40.327146 best dqsien dly found for B0: ( 0, 13, 12)
4747 11:16:40.330248 Total UI for P1: 0, mck2ui 16
4748 11:16:40.333910 best dqsien dly found for B1: ( 0, 13, 12)
4749 11:16:40.336971 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4750 11:16:40.340456 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4751 11:16:40.340607
4752 11:16:40.346863 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4753 11:16:40.350070 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4754 11:16:40.350157 [Gating] SW calibration Done
4755 11:16:40.353963 ==
4756 11:16:40.356877 Dram Type= 6, Freq= 0, CH_1, rank 1
4757 11:16:40.360254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4758 11:16:40.360363 ==
4759 11:16:40.360454 RX Vref Scan: 0
4760 11:16:40.360564
4761 11:16:40.363578 RX Vref 0 -> 0, step: 1
4762 11:16:40.363658
4763 11:16:40.367422 RX Delay -230 -> 252, step: 16
4764 11:16:40.370186 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4765 11:16:40.373171 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4766 11:16:40.379884 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4767 11:16:40.383585 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4768 11:16:40.387191 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4769 11:16:40.389802 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4770 11:16:40.396788 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4771 11:16:40.400162 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4772 11:16:40.403114 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4773 11:16:40.406643 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4774 11:16:40.409998 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4775 11:16:40.416976 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4776 11:16:40.420243 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4777 11:16:40.424166 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4778 11:16:40.427073 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4779 11:16:40.433780 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4780 11:16:40.434311 ==
4781 11:16:40.436888 Dram Type= 6, Freq= 0, CH_1, rank 1
4782 11:16:40.440096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4783 11:16:40.440656 ==
4784 11:16:40.440994 DQS Delay:
4785 11:16:40.443126 DQS0 = 0, DQS1 = 0
4786 11:16:40.443540 DQM Delay:
4787 11:16:40.446632 DQM0 = 42, DQM1 = 38
4788 11:16:40.447148 DQ Delay:
4789 11:16:40.449820 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =41
4790 11:16:40.453266 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4791 11:16:40.456957 DQ8 =17, DQ9 =25, DQ10 =41, DQ11 =25
4792 11:16:40.459658 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4793 11:16:40.460073
4794 11:16:40.460397
4795 11:16:40.460853 ==
4796 11:16:40.462890 Dram Type= 6, Freq= 0, CH_1, rank 1
4797 11:16:40.466459 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4798 11:16:40.469448 ==
4799 11:16:40.469914
4800 11:16:40.470242
4801 11:16:40.470545 TX Vref Scan disable
4802 11:16:40.472792 == TX Byte 0 ==
4803 11:16:40.476136 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4804 11:16:40.483236 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4805 11:16:40.483743 == TX Byte 1 ==
4806 11:16:40.486009 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4807 11:16:40.492461 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4808 11:16:40.493027 ==
4809 11:16:40.495947 Dram Type= 6, Freq= 0, CH_1, rank 1
4810 11:16:40.499405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4811 11:16:40.499914 ==
4812 11:16:40.500249
4813 11:16:40.500584
4814 11:16:40.502776 TX Vref Scan disable
4815 11:16:40.506395 == TX Byte 0 ==
4816 11:16:40.509737 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4817 11:16:40.512448 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4818 11:16:40.516160 == TX Byte 1 ==
4819 11:16:40.519742 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4820 11:16:40.522780 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4821 11:16:40.523290
4822 11:16:40.523617 [DATLAT]
4823 11:16:40.526065 Freq=600, CH1 RK1
4824 11:16:40.526572
4825 11:16:40.529136 DATLAT Default: 0x9
4826 11:16:40.529643 0, 0xFFFF, sum = 0
4827 11:16:40.532879 1, 0xFFFF, sum = 0
4828 11:16:40.533387 2, 0xFFFF, sum = 0
4829 11:16:40.536012 3, 0xFFFF, sum = 0
4830 11:16:40.536569 4, 0xFFFF, sum = 0
4831 11:16:40.539034 5, 0xFFFF, sum = 0
4832 11:16:40.539452 6, 0xFFFF, sum = 0
4833 11:16:40.542366 7, 0xFFFF, sum = 0
4834 11:16:40.542788 8, 0x0, sum = 1
4835 11:16:40.545567 9, 0x0, sum = 2
4836 11:16:40.545985 10, 0x0, sum = 3
4837 11:16:40.548828 11, 0x0, sum = 4
4838 11:16:40.549247 best_step = 9
4839 11:16:40.549572
4840 11:16:40.549871 ==
4841 11:16:40.552572 Dram Type= 6, Freq= 0, CH_1, rank 1
4842 11:16:40.555585 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4843 11:16:40.556096 ==
4844 11:16:40.558851 RX Vref Scan: 0
4845 11:16:40.559261
4846 11:16:40.561975 RX Vref 0 -> 0, step: 1
4847 11:16:40.562388
4848 11:16:40.562717 RX Delay -195 -> 252, step: 8
4849 11:16:40.570181 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4850 11:16:40.573264 iDelay=213, Bit 1, Center 36 (-115 ~ 188) 304
4851 11:16:40.576424 iDelay=213, Bit 2, Center 28 (-123 ~ 180) 304
4852 11:16:40.580095 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4853 11:16:40.586531 iDelay=213, Bit 4, Center 40 (-115 ~ 196) 312
4854 11:16:40.590037 iDelay=213, Bit 5, Center 52 (-99 ~ 204) 304
4855 11:16:40.593722 iDelay=213, Bit 6, Center 56 (-99 ~ 212) 312
4856 11:16:40.597017 iDelay=213, Bit 7, Center 40 (-115 ~ 196) 312
4857 11:16:40.600291 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4858 11:16:40.606404 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4859 11:16:40.609473 iDelay=213, Bit 10, Center 32 (-123 ~ 188) 312
4860 11:16:40.613330 iDelay=213, Bit 11, Center 24 (-131 ~ 180) 312
4861 11:16:40.616451 iDelay=213, Bit 12, Center 44 (-115 ~ 204) 320
4862 11:16:40.623255 iDelay=213, Bit 13, Center 40 (-115 ~ 196) 312
4863 11:16:40.626556 iDelay=213, Bit 14, Center 40 (-115 ~ 196) 312
4864 11:16:40.629536 iDelay=213, Bit 15, Center 44 (-115 ~ 204) 320
4865 11:16:40.630044 ==
4866 11:16:40.632993 Dram Type= 6, Freq= 0, CH_1, rank 1
4867 11:16:40.639582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4868 11:16:40.640093 ==
4869 11:16:40.640423 DQS Delay:
4870 11:16:40.640823 DQS0 = 0, DQS1 = 0
4871 11:16:40.642970 DQM Delay:
4872 11:16:40.643487 DQM0 = 42, DQM1 = 34
4873 11:16:40.645959 DQ Delay:
4874 11:16:40.649107 DQ0 =48, DQ1 =36, DQ2 =28, DQ3 =40
4875 11:16:40.652839 DQ4 =40, DQ5 =52, DQ6 =56, DQ7 =40
4876 11:16:40.656019 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =24
4877 11:16:40.659296 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =44
4878 11:16:40.659709
4879 11:16:40.660035
4880 11:16:40.665529 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b20, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
4881 11:16:40.669426 CH1 RK1: MR19=808, MR18=2B20
4882 11:16:40.675865 CH1_RK1: MR19=0x808, MR18=0x2B20, DQSOSC=401, MR23=63, INC=163, DEC=108
4883 11:16:40.679057 [RxdqsGatingPostProcess] freq 600
4884 11:16:40.682270 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4885 11:16:40.685367 Pre-setting of DQS Precalculation
4886 11:16:40.692062 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4887 11:16:40.699067 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4888 11:16:40.705649 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4889 11:16:40.706169
4890 11:16:40.706498
4891 11:16:40.709044 [Calibration Summary] 1200 Mbps
4892 11:16:40.709560 CH 0, Rank 0
4893 11:16:40.712466 SW Impedance : PASS
4894 11:16:40.715293 DUTY Scan : NO K
4895 11:16:40.715707 ZQ Calibration : PASS
4896 11:16:40.719142 Jitter Meter : NO K
4897 11:16:40.721641 CBT Training : PASS
4898 11:16:40.722059 Write leveling : PASS
4899 11:16:40.725342 RX DQS gating : PASS
4900 11:16:40.728341 RX DQ/DQS(RDDQC) : PASS
4901 11:16:40.728900 TX DQ/DQS : PASS
4902 11:16:40.731801 RX DATLAT : PASS
4903 11:16:40.735010 RX DQ/DQS(Engine): PASS
4904 11:16:40.735516 TX OE : NO K
4905 11:16:40.738400 All Pass.
4906 11:16:40.738909
4907 11:16:40.739238 CH 0, Rank 1
4908 11:16:40.741273 SW Impedance : PASS
4909 11:16:40.741688 DUTY Scan : NO K
4910 11:16:40.745124 ZQ Calibration : PASS
4911 11:16:40.748408 Jitter Meter : NO K
4912 11:16:40.749004 CBT Training : PASS
4913 11:16:40.751363 Write leveling : PASS
4914 11:16:40.755447 RX DQS gating : PASS
4915 11:16:40.755954 RX DQ/DQS(RDDQC) : PASS
4916 11:16:40.758220 TX DQ/DQS : PASS
4917 11:16:40.761426 RX DATLAT : PASS
4918 11:16:40.761882 RX DQ/DQS(Engine): PASS
4919 11:16:40.764629 TX OE : NO K
4920 11:16:40.765050 All Pass.
4921 11:16:40.765385
4922 11:16:40.767976 CH 1, Rank 0
4923 11:16:40.768394 SW Impedance : PASS
4924 11:16:40.771497 DUTY Scan : NO K
4925 11:16:40.772029 ZQ Calibration : PASS
4926 11:16:40.774616 Jitter Meter : NO K
4927 11:16:40.777580 CBT Training : PASS
4928 11:16:40.778011 Write leveling : PASS
4929 11:16:40.781083 RX DQS gating : PASS
4930 11:16:40.784047 RX DQ/DQS(RDDQC) : PASS
4931 11:16:40.784461 TX DQ/DQS : PASS
4932 11:16:40.787823 RX DATLAT : PASS
4933 11:16:40.791234 RX DQ/DQS(Engine): PASS
4934 11:16:40.791746 TX OE : NO K
4935 11:16:40.794521 All Pass.
4936 11:16:40.794939
4937 11:16:40.795270 CH 1, Rank 1
4938 11:16:40.797664 SW Impedance : PASS
4939 11:16:40.798170 DUTY Scan : NO K
4940 11:16:40.801085 ZQ Calibration : PASS
4941 11:16:40.804209 Jitter Meter : NO K
4942 11:16:40.804673 CBT Training : PASS
4943 11:16:40.807444 Write leveling : PASS
4944 11:16:40.810456 RX DQS gating : PASS
4945 11:16:40.810874 RX DQ/DQS(RDDQC) : PASS
4946 11:16:40.813963 TX DQ/DQS : PASS
4947 11:16:40.817059 RX DATLAT : PASS
4948 11:16:40.817477 RX DQ/DQS(Engine): PASS
4949 11:16:40.821058 TX OE : NO K
4950 11:16:40.821621 All Pass.
4951 11:16:40.821955
4952 11:16:40.824093 DramC Write-DBI off
4953 11:16:40.827232 PER_BANK_REFRESH: Hybrid Mode
4954 11:16:40.827746 TX_TRACKING: ON
4955 11:16:40.837120 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4956 11:16:40.840328 [FAST_K] Save calibration result to emmc
4957 11:16:40.844031 dramc_set_vcore_voltage set vcore to 662500
4958 11:16:40.846910 Read voltage for 933, 3
4959 11:16:40.847427 Vio18 = 0
4960 11:16:40.847756 Vcore = 662500
4961 11:16:40.850434 Vdram = 0
4962 11:16:40.850853 Vddq = 0
4963 11:16:40.851187 Vmddr = 0
4964 11:16:40.856901 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4965 11:16:40.859715 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4966 11:16:40.863727 MEM_TYPE=3, freq_sel=17
4967 11:16:40.866526 sv_algorithm_assistance_LP4_1600
4968 11:16:40.869694 ============ PULL DRAM RESETB DOWN ============
4969 11:16:40.876673 ========== PULL DRAM RESETB DOWN end =========
4970 11:16:40.879802 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4971 11:16:40.883375 ===================================
4972 11:16:40.886158 LPDDR4 DRAM CONFIGURATION
4973 11:16:40.889738 ===================================
4974 11:16:40.890251 EX_ROW_EN[0] = 0x0
4975 11:16:40.892879 EX_ROW_EN[1] = 0x0
4976 11:16:40.893393 LP4Y_EN = 0x0
4977 11:16:40.896115 WORK_FSP = 0x0
4978 11:16:40.896665 WL = 0x3
4979 11:16:40.899278 RL = 0x3
4980 11:16:40.899695 BL = 0x2
4981 11:16:40.903185 RPST = 0x0
4982 11:16:40.906035 RD_PRE = 0x0
4983 11:16:40.906561 WR_PRE = 0x1
4984 11:16:40.909515 WR_PST = 0x0
4985 11:16:40.910029 DBI_WR = 0x0
4986 11:16:40.912674 DBI_RD = 0x0
4987 11:16:40.913190 OTF = 0x1
4988 11:16:40.915708 ===================================
4989 11:16:40.919511 ===================================
4990 11:16:40.922653 ANA top config
4991 11:16:40.926169 ===================================
4992 11:16:40.926593 DLL_ASYNC_EN = 0
4993 11:16:40.929572 ALL_SLAVE_EN = 1
4994 11:16:40.932575 NEW_RANK_MODE = 1
4995 11:16:40.935860 DLL_IDLE_MODE = 1
4996 11:16:40.936378 LP45_APHY_COMB_EN = 1
4997 11:16:40.939577 TX_ODT_DIS = 1
4998 11:16:40.942813 NEW_8X_MODE = 1
4999 11:16:40.946131 ===================================
5000 11:16:40.949617 ===================================
5001 11:16:40.952324 data_rate = 1866
5002 11:16:40.956022 CKR = 1
5003 11:16:40.959759 DQ_P2S_RATIO = 8
5004 11:16:40.961992 ===================================
5005 11:16:40.962413 CA_P2S_RATIO = 8
5006 11:16:40.965554 DQ_CA_OPEN = 0
5007 11:16:40.968957 DQ_SEMI_OPEN = 0
5008 11:16:40.972101 CA_SEMI_OPEN = 0
5009 11:16:40.975861 CA_FULL_RATE = 0
5010 11:16:40.979656 DQ_CKDIV4_EN = 1
5011 11:16:40.980182 CA_CKDIV4_EN = 1
5012 11:16:40.982821 CA_PREDIV_EN = 0
5013 11:16:40.985548 PH8_DLY = 0
5014 11:16:40.989110 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
5015 11:16:40.992199 DQ_AAMCK_DIV = 4
5016 11:16:40.995654 CA_AAMCK_DIV = 4
5017 11:16:40.996189 CA_ADMCK_DIV = 4
5018 11:16:40.998349 DQ_TRACK_CA_EN = 0
5019 11:16:41.002126 CA_PICK = 933
5020 11:16:41.004983 CA_MCKIO = 933
5021 11:16:41.008702 MCKIO_SEMI = 0
5022 11:16:41.011838 PLL_FREQ = 3732
5023 11:16:41.015371 DQ_UI_PI_RATIO = 32
5024 11:16:41.015895 CA_UI_PI_RATIO = 0
5025 11:16:41.019022 ===================================
5026 11:16:41.021660 ===================================
5027 11:16:41.025630 memory_type:LPDDR4
5028 11:16:41.028178 GP_NUM : 10
5029 11:16:41.028632 SRAM_EN : 1
5030 11:16:41.031915 MD32_EN : 0
5031 11:16:41.035015 ===================================
5032 11:16:41.038419 [ANA_INIT] >>>>>>>>>>>>>>
5033 11:16:41.041984 <<<<<< [CONFIGURE PHASE]: ANA_TX
5034 11:16:41.044917 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5035 11:16:41.048067 ===================================
5036 11:16:41.048625 data_rate = 1866,PCW = 0X8f00
5037 11:16:41.051390 ===================================
5038 11:16:41.057935 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5039 11:16:41.061416 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5040 11:16:41.067565 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5041 11:16:41.070964 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5042 11:16:41.074731 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5043 11:16:41.077806 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5044 11:16:41.080973 [ANA_INIT] flow start
5045 11:16:41.084605 [ANA_INIT] PLL >>>>>>>>
5046 11:16:41.085133 [ANA_INIT] PLL <<<<<<<<
5047 11:16:41.087719 [ANA_INIT] MIDPI >>>>>>>>
5048 11:16:41.091161 [ANA_INIT] MIDPI <<<<<<<<
5049 11:16:41.091682 [ANA_INIT] DLL >>>>>>>>
5050 11:16:41.094610 [ANA_INIT] flow end
5051 11:16:41.097649 ============ LP4 DIFF to SE enter ============
5052 11:16:41.104478 ============ LP4 DIFF to SE exit ============
5053 11:16:41.105062 [ANA_INIT] <<<<<<<<<<<<<
5054 11:16:41.107960 [Flow] Enable top DCM control >>>>>
5055 11:16:41.110942 [Flow] Enable top DCM control <<<<<
5056 11:16:41.114327 Enable DLL master slave shuffle
5057 11:16:41.120866 ==============================================================
5058 11:16:41.121379 Gating Mode config
5059 11:16:41.127243 ==============================================================
5060 11:16:41.130874 Config description:
5061 11:16:41.137281 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5062 11:16:41.144337 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5063 11:16:41.150500 SELPH_MODE 0: By rank 1: By Phase
5064 11:16:41.157335 ==============================================================
5065 11:16:41.160818 GAT_TRACK_EN = 1
5066 11:16:41.161237 RX_GATING_MODE = 2
5067 11:16:41.164027 RX_GATING_TRACK_MODE = 2
5068 11:16:41.167489 SELPH_MODE = 1
5069 11:16:41.170842 PICG_EARLY_EN = 1
5070 11:16:41.173340 VALID_LAT_VALUE = 1
5071 11:16:41.180254 ==============================================================
5072 11:16:41.183559 Enter into Gating configuration >>>>
5073 11:16:41.187019 Exit from Gating configuration <<<<
5074 11:16:41.190448 Enter into DVFS_PRE_config >>>>>
5075 11:16:41.200029 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5076 11:16:41.203205 Exit from DVFS_PRE_config <<<<<
5077 11:16:41.206486 Enter into PICG configuration >>>>
5078 11:16:41.209836 Exit from PICG configuration <<<<
5079 11:16:41.213162 [RX_INPUT] configuration >>>>>
5080 11:16:41.216182 [RX_INPUT] configuration <<<<<
5081 11:16:41.219871 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5082 11:16:41.226397 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5083 11:16:41.233023 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5084 11:16:41.239702 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5085 11:16:41.242608 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5086 11:16:41.249528 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5087 11:16:41.256265 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5088 11:16:41.259991 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5089 11:16:41.262867 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5090 11:16:41.266441 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5091 11:16:41.269594 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5092 11:16:41.276450 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5093 11:16:41.278825 ===================================
5094 11:16:41.282365 LPDDR4 DRAM CONFIGURATION
5095 11:16:41.285948 ===================================
5096 11:16:41.286368 EX_ROW_EN[0] = 0x0
5097 11:16:41.289070 EX_ROW_EN[1] = 0x0
5098 11:16:41.289481 LP4Y_EN = 0x0
5099 11:16:41.292468 WORK_FSP = 0x0
5100 11:16:41.293067 WL = 0x3
5101 11:16:41.295447 RL = 0x3
5102 11:16:41.295875 BL = 0x2
5103 11:16:41.299965 RPST = 0x0
5104 11:16:41.300481 RD_PRE = 0x0
5105 11:16:41.302145 WR_PRE = 0x1
5106 11:16:41.302640 WR_PST = 0x0
5107 11:16:41.305449 DBI_WR = 0x0
5108 11:16:41.309090 DBI_RD = 0x0
5109 11:16:41.309618 OTF = 0x1
5110 11:16:41.311918 ===================================
5111 11:16:41.315469 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5112 11:16:41.318666 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5113 11:16:41.325522 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5114 11:16:41.328886 ===================================
5115 11:16:41.331981 LPDDR4 DRAM CONFIGURATION
5116 11:16:41.335508 ===================================
5117 11:16:41.336027 EX_ROW_EN[0] = 0x10
5118 11:16:41.338658 EX_ROW_EN[1] = 0x0
5119 11:16:41.339174 LP4Y_EN = 0x0
5120 11:16:41.341925 WORK_FSP = 0x0
5121 11:16:41.342341 WL = 0x3
5122 11:16:41.344956 RL = 0x3
5123 11:16:41.345373 BL = 0x2
5124 11:16:41.348720 RPST = 0x0
5125 11:16:41.349240 RD_PRE = 0x0
5126 11:16:41.351869 WR_PRE = 0x1
5127 11:16:41.355634 WR_PST = 0x0
5128 11:16:41.356148 DBI_WR = 0x0
5129 11:16:41.359006 DBI_RD = 0x0
5130 11:16:41.359420 OTF = 0x1
5131 11:16:41.361800 ===================================
5132 11:16:41.368792 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5133 11:16:41.372141 nWR fixed to 30
5134 11:16:41.375189 [ModeRegInit_LP4] CH0 RK0
5135 11:16:41.375715 [ModeRegInit_LP4] CH0 RK1
5136 11:16:41.378471 [ModeRegInit_LP4] CH1 RK0
5137 11:16:41.382196 [ModeRegInit_LP4] CH1 RK1
5138 11:16:41.382744 match AC timing 9
5139 11:16:41.388856 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5140 11:16:41.391702 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5141 11:16:41.395100 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5142 11:16:41.401901 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5143 11:16:41.404910 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5144 11:16:41.405435 ==
5145 11:16:41.408226 Dram Type= 6, Freq= 0, CH_0, rank 0
5146 11:16:41.411523 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5147 11:16:41.412055 ==
5148 11:16:41.418283 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5149 11:16:41.425053 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5150 11:16:41.428018 [CA 0] Center 37 (7~68) winsize 62
5151 11:16:41.431818 [CA 1] Center 37 (7~68) winsize 62
5152 11:16:41.435541 [CA 2] Center 34 (4~65) winsize 62
5153 11:16:41.438226 [CA 3] Center 34 (4~65) winsize 62
5154 11:16:41.441455 [CA 4] Center 33 (3~64) winsize 62
5155 11:16:41.444788 [CA 5] Center 33 (3~64) winsize 62
5156 11:16:41.445314
5157 11:16:41.447542 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5158 11:16:41.447964
5159 11:16:41.450844 [CATrainingPosCal] consider 1 rank data
5160 11:16:41.454070 u2DelayCellTimex100 = 270/100 ps
5161 11:16:41.457815 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5162 11:16:41.460650 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5163 11:16:41.463980 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5164 11:16:41.467741 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5165 11:16:41.474164 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5166 11:16:41.477349 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5167 11:16:41.477857
5168 11:16:41.480547 CA PerBit enable=1, Macro0, CA PI delay=33
5169 11:16:41.481070
5170 11:16:41.483823 [CBTSetCACLKResult] CA Dly = 33
5171 11:16:41.484241 CS Dly: 7 (0~38)
5172 11:16:41.484615 ==
5173 11:16:41.487257 Dram Type= 6, Freq= 0, CH_0, rank 1
5174 11:16:41.493835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5175 11:16:41.494349 ==
5176 11:16:41.497090 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5177 11:16:41.503707 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5178 11:16:41.507065 [CA 0] Center 37 (7~68) winsize 62
5179 11:16:41.510606 [CA 1] Center 37 (7~68) winsize 62
5180 11:16:41.513479 [CA 2] Center 34 (4~65) winsize 62
5181 11:16:41.517165 [CA 3] Center 34 (4~65) winsize 62
5182 11:16:41.520051 [CA 4] Center 33 (3~64) winsize 62
5183 11:16:41.523840 [CA 5] Center 33 (3~63) winsize 61
5184 11:16:41.524355
5185 11:16:41.526697 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5186 11:16:41.527215
5187 11:16:41.530331 [CATrainingPosCal] consider 2 rank data
5188 11:16:41.533099 u2DelayCellTimex100 = 270/100 ps
5189 11:16:41.536815 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5190 11:16:41.543188 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5191 11:16:41.546169 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5192 11:16:41.550067 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5193 11:16:41.552916 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5194 11:16:41.556169 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5195 11:16:41.556744
5196 11:16:41.560027 CA PerBit enable=1, Macro0, CA PI delay=33
5197 11:16:41.560626
5198 11:16:41.562960 [CBTSetCACLKResult] CA Dly = 33
5199 11:16:41.566172 CS Dly: 7 (0~39)
5200 11:16:41.566596
5201 11:16:41.569252 ----->DramcWriteLeveling(PI) begin...
5202 11:16:41.569681 ==
5203 11:16:41.572754 Dram Type= 6, Freq= 0, CH_0, rank 0
5204 11:16:41.576755 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5205 11:16:41.577285 ==
5206 11:16:41.579696 Write leveling (Byte 0): 33 => 33
5207 11:16:41.582671 Write leveling (Byte 1): 31 => 31
5208 11:16:41.586576 DramcWriteLeveling(PI) end<-----
5209 11:16:41.587109
5210 11:16:41.587445 ==
5211 11:16:41.589419 Dram Type= 6, Freq= 0, CH_0, rank 0
5212 11:16:41.592909 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5213 11:16:41.593447 ==
5214 11:16:41.596174 [Gating] SW mode calibration
5215 11:16:41.602499 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5216 11:16:41.609086 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5217 11:16:41.613131 0 14 0 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
5218 11:16:41.616135 0 14 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5219 11:16:41.622163 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5220 11:16:41.625672 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5221 11:16:41.628754 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5222 11:16:41.636041 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5223 11:16:41.638561 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5224 11:16:41.642410 0 14 28 | B1->B0 | 3434 2828 | 1 0 | (1 1) (1 0)
5225 11:16:41.648876 0 15 0 | B1->B0 | 2f2f 2626 | 1 0 | (1 0) (0 0)
5226 11:16:41.652237 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5227 11:16:41.655438 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5228 11:16:41.661746 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5229 11:16:41.664877 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5230 11:16:41.668400 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5231 11:16:41.675104 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5232 11:16:41.679253 0 15 28 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
5233 11:16:41.681619 1 0 0 | B1->B0 | 3636 4646 | 0 0 | (0 0) (0 0)
5234 11:16:41.688864 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5235 11:16:41.692367 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5236 11:16:41.695415 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5237 11:16:41.701306 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5238 11:16:41.704932 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5239 11:16:41.708222 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5240 11:16:41.714985 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5241 11:16:41.717815 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5242 11:16:41.721148 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5243 11:16:41.728570 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5244 11:16:41.731216 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5245 11:16:41.734671 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5246 11:16:41.741300 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5247 11:16:41.744841 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5248 11:16:41.747922 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5249 11:16:41.754522 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5250 11:16:41.757943 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5251 11:16:41.761344 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5252 11:16:41.767650 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5253 11:16:41.770493 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5254 11:16:41.774116 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5255 11:16:41.780625 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5256 11:16:41.784464 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5257 11:16:41.787349 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
5258 11:16:41.790892 Total UI for P1: 0, mck2ui 16
5259 11:16:41.793921 best dqsien dly found for B0: ( 1, 2, 26)
5260 11:16:41.800892 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5261 11:16:41.801453 Total UI for P1: 0, mck2ui 16
5262 11:16:41.806853 best dqsien dly found for B1: ( 1, 3, 2)
5263 11:16:41.810485 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5264 11:16:41.813598 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5265 11:16:41.814110
5266 11:16:41.816922 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5267 11:16:41.820118 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5268 11:16:41.823646 [Gating] SW calibration Done
5269 11:16:41.824157 ==
5270 11:16:41.826915 Dram Type= 6, Freq= 0, CH_0, rank 0
5271 11:16:41.830652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5272 11:16:41.831173 ==
5273 11:16:41.833562 RX Vref Scan: 0
5274 11:16:41.833971
5275 11:16:41.834295 RX Vref 0 -> 0, step: 1
5276 11:16:41.834652
5277 11:16:41.836987 RX Delay -80 -> 252, step: 8
5278 11:16:41.839921 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5279 11:16:41.846711 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5280 11:16:41.850246 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5281 11:16:41.853754 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5282 11:16:41.856760 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5283 11:16:41.860367 iDelay=208, Bit 5, Center 83 (-16 ~ 183) 200
5284 11:16:41.863597 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5285 11:16:41.870263 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5286 11:16:41.873260 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5287 11:16:41.876747 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5288 11:16:41.880120 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5289 11:16:41.883081 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5290 11:16:41.890269 iDelay=208, Bit 12, Center 87 (-8 ~ 183) 192
5291 11:16:41.892833 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5292 11:16:41.896873 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5293 11:16:41.899836 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5294 11:16:41.900357 ==
5295 11:16:41.903115 Dram Type= 6, Freq= 0, CH_0, rank 0
5296 11:16:41.909498 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5297 11:16:41.910061 ==
5298 11:16:41.910401 DQS Delay:
5299 11:16:41.912830 DQS0 = 0, DQS1 = 0
5300 11:16:41.913336 DQM Delay:
5301 11:16:41.913665 DQM0 = 98, DQM1 = 85
5302 11:16:41.916756 DQ Delay:
5303 11:16:41.919712 DQ0 =103, DQ1 =99, DQ2 =95, DQ3 =91
5304 11:16:41.922699 DQ4 =99, DQ5 =83, DQ6 =107, DQ7 =107
5305 11:16:41.926055 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =79
5306 11:16:41.929613 DQ12 =87, DQ13 =91, DQ14 =95, DQ15 =91
5307 11:16:41.930159
5308 11:16:41.930489
5309 11:16:41.930794 ==
5310 11:16:41.932827 Dram Type= 6, Freq= 0, CH_0, rank 0
5311 11:16:41.935749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5312 11:16:41.936168 ==
5313 11:16:41.936497
5314 11:16:41.936853
5315 11:16:41.939331 TX Vref Scan disable
5316 11:16:41.942614 == TX Byte 0 ==
5317 11:16:41.946004 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5318 11:16:41.949110 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5319 11:16:41.952551 == TX Byte 1 ==
5320 11:16:41.955710 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5321 11:16:41.958990 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5322 11:16:41.959408 ==
5323 11:16:41.961937 Dram Type= 6, Freq= 0, CH_0, rank 0
5324 11:16:41.966133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5325 11:16:41.968457 ==
5326 11:16:41.968918
5327 11:16:41.969250
5328 11:16:41.969555 TX Vref Scan disable
5329 11:16:41.972361 == TX Byte 0 ==
5330 11:16:41.976220 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5331 11:16:41.982170 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5332 11:16:41.982674 == TX Byte 1 ==
5333 11:16:41.986177 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5334 11:16:41.992498 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5335 11:16:41.993054
5336 11:16:41.993386 [DATLAT]
5337 11:16:41.993721 Freq=933, CH0 RK0
5338 11:16:41.994029
5339 11:16:41.995350 DATLAT Default: 0xd
5340 11:16:41.998661 0, 0xFFFF, sum = 0
5341 11:16:41.999182 1, 0xFFFF, sum = 0
5342 11:16:42.002255 2, 0xFFFF, sum = 0
5343 11:16:42.002778 3, 0xFFFF, sum = 0
5344 11:16:42.005575 4, 0xFFFF, sum = 0
5345 11:16:42.006014 5, 0xFFFF, sum = 0
5346 11:16:42.008923 6, 0xFFFF, sum = 0
5347 11:16:42.009484 7, 0xFFFF, sum = 0
5348 11:16:42.012146 8, 0xFFFF, sum = 0
5349 11:16:42.012722 9, 0xFFFF, sum = 0
5350 11:16:42.015383 10, 0x0, sum = 1
5351 11:16:42.015919 11, 0x0, sum = 2
5352 11:16:42.018488 12, 0x0, sum = 3
5353 11:16:42.018914 13, 0x0, sum = 4
5354 11:16:42.021864 best_step = 11
5355 11:16:42.022382
5356 11:16:42.022713 ==
5357 11:16:42.025655 Dram Type= 6, Freq= 0, CH_0, rank 0
5358 11:16:42.028667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5359 11:16:42.029192 ==
5360 11:16:42.029518 RX Vref Scan: 1
5361 11:16:42.029818
5362 11:16:42.031932 RX Vref 0 -> 0, step: 1
5363 11:16:42.032338
5364 11:16:42.035102 RX Delay -69 -> 252, step: 4
5365 11:16:42.035509
5366 11:16:42.038103 Set Vref, RX VrefLevel [Byte0]: 57
5367 11:16:42.041574 [Byte1]: 57
5368 11:16:42.044837
5369 11:16:42.045243 Final RX Vref Byte 0 = 57 to rank0
5370 11:16:42.048163 Final RX Vref Byte 1 = 57 to rank0
5371 11:16:42.051401 Final RX Vref Byte 0 = 57 to rank1
5372 11:16:42.054707 Final RX Vref Byte 1 = 57 to rank1==
5373 11:16:42.058388 Dram Type= 6, Freq= 0, CH_0, rank 0
5374 11:16:42.064988 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5375 11:16:42.065511 ==
5376 11:16:42.065861 DQS Delay:
5377 11:16:42.068396 DQS0 = 0, DQS1 = 0
5378 11:16:42.068854 DQM Delay:
5379 11:16:42.069184 DQM0 = 97, DQM1 = 86
5380 11:16:42.071398 DQ Delay:
5381 11:16:42.074635 DQ0 =96, DQ1 =98, DQ2 =94, DQ3 =94
5382 11:16:42.078097 DQ4 =98, DQ5 =88, DQ6 =104, DQ7 =106
5383 11:16:42.081238 DQ8 =80, DQ9 =78, DQ10 =88, DQ11 =82
5384 11:16:42.084237 DQ12 =90, DQ13 =90, DQ14 =94, DQ15 =92
5385 11:16:42.084679
5386 11:16:42.085003
5387 11:16:42.091491 [DQSOSCAuto] RK0, (LSB)MR18= 0x2b11, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 408 ps
5388 11:16:42.094784 CH0 RK0: MR19=505, MR18=2B11
5389 11:16:42.101497 CH0_RK0: MR19=0x505, MR18=0x2B11, DQSOSC=408, MR23=63, INC=65, DEC=43
5390 11:16:42.102000
5391 11:16:42.104736 ----->DramcWriteLeveling(PI) begin...
5392 11:16:42.105240 ==
5393 11:16:42.107931 Dram Type= 6, Freq= 0, CH_0, rank 1
5394 11:16:42.111004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5395 11:16:42.111423 ==
5396 11:16:42.114170 Write leveling (Byte 0): 32 => 32
5397 11:16:42.117551 Write leveling (Byte 1): 31 => 31
5398 11:16:42.120743 DramcWriteLeveling(PI) end<-----
5399 11:16:42.121233
5400 11:16:42.121555 ==
5401 11:16:42.124026 Dram Type= 6, Freq= 0, CH_0, rank 1
5402 11:16:42.127518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5403 11:16:42.130640 ==
5404 11:16:42.131148 [Gating] SW mode calibration
5405 11:16:42.140402 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5406 11:16:42.143973 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5407 11:16:42.147393 0 14 0 | B1->B0 | 2d2d 3232 | 0 0 | (0 0) (0 0)
5408 11:16:42.154102 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5409 11:16:42.157615 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5410 11:16:42.161189 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5411 11:16:42.167462 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5412 11:16:42.170508 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5413 11:16:42.173849 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
5414 11:16:42.180785 0 14 28 | B1->B0 | 3434 3030 | 1 0 | (1 0) (1 0)
5415 11:16:42.184383 0 15 0 | B1->B0 | 2f2f 2e2e | 0 0 | (0 0) (1 1)
5416 11:16:42.187107 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5417 11:16:42.193740 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5418 11:16:42.197244 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5419 11:16:42.200345 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5420 11:16:42.207281 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5421 11:16:42.210186 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5422 11:16:42.213417 0 15 28 | B1->B0 | 2626 3232 | 0 0 | (0 0) (0 0)
5423 11:16:42.220374 1 0 0 | B1->B0 | 3939 4545 | 1 0 | (0 0) (0 0)
5424 11:16:42.223424 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5425 11:16:42.226777 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5426 11:16:42.233119 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5427 11:16:42.236943 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5428 11:16:42.240574 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5429 11:16:42.247067 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5430 11:16:42.249547 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5431 11:16:42.252799 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5432 11:16:42.259800 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5433 11:16:42.263186 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5434 11:16:42.266398 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5435 11:16:42.273673 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5436 11:16:42.276189 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5437 11:16:42.279850 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5438 11:16:42.286274 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5439 11:16:42.289811 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5440 11:16:42.292796 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5441 11:16:42.299298 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5442 11:16:42.302741 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5443 11:16:42.306202 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5444 11:16:42.312595 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5445 11:16:42.315907 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5446 11:16:42.319264 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5447 11:16:42.325821 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5448 11:16:42.326358 Total UI for P1: 0, mck2ui 16
5449 11:16:42.332573 best dqsien dly found for B0: ( 1, 2, 30)
5450 11:16:42.335663 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5451 11:16:42.338994 Total UI for P1: 0, mck2ui 16
5452 11:16:42.341992 best dqsien dly found for B1: ( 1, 3, 0)
5453 11:16:42.345543 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5454 11:16:42.349111 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5455 11:16:42.349681
5456 11:16:42.351915 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5457 11:16:42.355198 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5458 11:16:42.358206 [Gating] SW calibration Done
5459 11:16:42.358620 ==
5460 11:16:42.361631 Dram Type= 6, Freq= 0, CH_0, rank 1
5461 11:16:42.368289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5462 11:16:42.368760 ==
5463 11:16:42.369094 RX Vref Scan: 0
5464 11:16:42.369403
5465 11:16:42.371436 RX Vref 0 -> 0, step: 1
5466 11:16:42.371957
5467 11:16:42.374941 RX Delay -80 -> 252, step: 8
5468 11:16:42.378399 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5469 11:16:42.381294 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5470 11:16:42.384693 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5471 11:16:42.388050 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5472 11:16:42.394683 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5473 11:16:42.398387 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5474 11:16:42.401520 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5475 11:16:42.404972 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5476 11:16:42.408165 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5477 11:16:42.411237 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5478 11:16:42.417811 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5479 11:16:42.421059 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5480 11:16:42.424178 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5481 11:16:42.428334 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5482 11:16:42.430771 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5483 11:16:42.437449 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5484 11:16:42.438014 ==
5485 11:16:42.440679 Dram Type= 6, Freq= 0, CH_0, rank 1
5486 11:16:42.443893 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5487 11:16:42.444364 ==
5488 11:16:42.444769 DQS Delay:
5489 11:16:42.447352 DQS0 = 0, DQS1 = 0
5490 11:16:42.447910 DQM Delay:
5491 11:16:42.450339 DQM0 = 97, DQM1 = 90
5492 11:16:42.450803 DQ Delay:
5493 11:16:42.453783 DQ0 =95, DQ1 =99, DQ2 =87, DQ3 =91
5494 11:16:42.457462 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =107
5495 11:16:42.460305 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5496 11:16:42.463887 DQ12 =91, DQ13 =95, DQ14 =99, DQ15 =95
5497 11:16:42.464328
5498 11:16:42.464723
5499 11:16:42.465044 ==
5500 11:16:42.466694 Dram Type= 6, Freq= 0, CH_0, rank 1
5501 11:16:42.470096 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5502 11:16:42.473501 ==
5503 11:16:42.473926
5504 11:16:42.474258
5505 11:16:42.474567 TX Vref Scan disable
5506 11:16:42.476781 == TX Byte 0 ==
5507 11:16:42.480409 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5508 11:16:42.483843 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5509 11:16:42.487013 == TX Byte 1 ==
5510 11:16:42.490151 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5511 11:16:42.493446 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5512 11:16:42.497095 ==
5513 11:16:42.500860 Dram Type= 6, Freq= 0, CH_0, rank 1
5514 11:16:42.503436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5515 11:16:42.503992 ==
5516 11:16:42.504361
5517 11:16:42.504760
5518 11:16:42.506627 TX Vref Scan disable
5519 11:16:42.507127 == TX Byte 0 ==
5520 11:16:42.513630 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5521 11:16:42.516781 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5522 11:16:42.517295 == TX Byte 1 ==
5523 11:16:42.523014 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5524 11:16:42.526694 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5525 11:16:42.527209
5526 11:16:42.527540 [DATLAT]
5527 11:16:42.530075 Freq=933, CH0 RK1
5528 11:16:42.530593
5529 11:16:42.530925 DATLAT Default: 0xb
5530 11:16:42.533075 0, 0xFFFF, sum = 0
5531 11:16:42.533599 1, 0xFFFF, sum = 0
5532 11:16:42.536242 2, 0xFFFF, sum = 0
5533 11:16:42.539908 3, 0xFFFF, sum = 0
5534 11:16:42.540431 4, 0xFFFF, sum = 0
5535 11:16:42.543086 5, 0xFFFF, sum = 0
5536 11:16:42.543604 6, 0xFFFF, sum = 0
5537 11:16:42.546033 7, 0xFFFF, sum = 0
5538 11:16:42.546553 8, 0xFFFF, sum = 0
5539 11:16:42.549629 9, 0xFFFF, sum = 0
5540 11:16:42.550154 10, 0x0, sum = 1
5541 11:16:42.552842 11, 0x0, sum = 2
5542 11:16:42.553365 12, 0x0, sum = 3
5543 11:16:42.556183 13, 0x0, sum = 4
5544 11:16:42.556647 best_step = 11
5545 11:16:42.556985
5546 11:16:42.557293 ==
5547 11:16:42.561062 Dram Type= 6, Freq= 0, CH_0, rank 1
5548 11:16:42.562665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5549 11:16:42.563092 ==
5550 11:16:42.565748 RX Vref Scan: 0
5551 11:16:42.566188
5552 11:16:42.569171 RX Vref 0 -> 0, step: 1
5553 11:16:42.569589
5554 11:16:42.569917 RX Delay -61 -> 252, step: 4
5555 11:16:42.576990 iDelay=203, Bit 0, Center 94 (3 ~ 186) 184
5556 11:16:42.580336 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5557 11:16:42.583949 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5558 11:16:42.587568 iDelay=203, Bit 3, Center 94 (-1 ~ 190) 192
5559 11:16:42.590808 iDelay=203, Bit 4, Center 94 (3 ~ 186) 184
5560 11:16:42.594021 iDelay=203, Bit 5, Center 86 (-9 ~ 182) 192
5561 11:16:42.600400 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5562 11:16:42.603742 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5563 11:16:42.607059 iDelay=203, Bit 8, Center 80 (-13 ~ 174) 188
5564 11:16:42.610310 iDelay=203, Bit 9, Center 78 (-13 ~ 170) 184
5565 11:16:42.613926 iDelay=203, Bit 10, Center 90 (-5 ~ 186) 192
5566 11:16:42.620237 iDelay=203, Bit 11, Center 80 (-13 ~ 174) 188
5567 11:16:42.623609 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5568 11:16:42.626348 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5569 11:16:42.629834 iDelay=203, Bit 14, Center 94 (-1 ~ 190) 192
5570 11:16:42.636509 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5571 11:16:42.637057 ==
5572 11:16:42.639787 Dram Type= 6, Freq= 0, CH_0, rank 1
5573 11:16:42.643115 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5574 11:16:42.643640 ==
5575 11:16:42.643981 DQS Delay:
5576 11:16:42.646072 DQS0 = 0, DQS1 = 0
5577 11:16:42.646591 DQM Delay:
5578 11:16:42.649436 DQM0 = 95, DQM1 = 87
5579 11:16:42.649961 DQ Delay:
5580 11:16:42.653202 DQ0 =94, DQ1 =96, DQ2 =90, DQ3 =94
5581 11:16:42.655992 DQ4 =94, DQ5 =86, DQ6 =106, DQ7 =104
5582 11:16:42.659266 DQ8 =80, DQ9 =78, DQ10 =90, DQ11 =80
5583 11:16:42.662559 DQ12 =92, DQ13 =92, DQ14 =94, DQ15 =92
5584 11:16:42.662979
5585 11:16:42.663340
5586 11:16:42.672272 [DQSOSCAuto] RK1, (LSB)MR18= 0x28f8, (MSB)MR19= 0x504, tDQSOscB0 = 424 ps tDQSOscB1 = 409 ps
5587 11:16:42.672749 CH0 RK1: MR19=504, MR18=28F8
5588 11:16:42.678990 CH0_RK1: MR19=0x504, MR18=0x28F8, DQSOSC=409, MR23=63, INC=64, DEC=43
5589 11:16:42.682113 [RxdqsGatingPostProcess] freq 933
5590 11:16:42.688664 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5591 11:16:42.692012 best DQS0 dly(2T, 0.5T) = (0, 10)
5592 11:16:42.695453 best DQS1 dly(2T, 0.5T) = (0, 11)
5593 11:16:42.698678 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5594 11:16:42.702271 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5595 11:16:42.705829 best DQS0 dly(2T, 0.5T) = (0, 10)
5596 11:16:42.708478 best DQS1 dly(2T, 0.5T) = (0, 11)
5597 11:16:42.711771 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5598 11:16:42.715477 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5599 11:16:42.715996 Pre-setting of DQS Precalculation
5600 11:16:42.722122 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5601 11:16:42.722640 ==
5602 11:16:42.725351 Dram Type= 6, Freq= 0, CH_1, rank 0
5603 11:16:42.728630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5604 11:16:42.729244 ==
5605 11:16:42.735090 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5606 11:16:42.741775 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5607 11:16:42.745302 [CA 0] Center 36 (6~67) winsize 62
5608 11:16:42.748635 [CA 1] Center 37 (6~68) winsize 63
5609 11:16:42.751313 [CA 2] Center 34 (4~65) winsize 62
5610 11:16:42.754768 [CA 3] Center 33 (3~64) winsize 62
5611 11:16:42.758715 [CA 4] Center 34 (4~64) winsize 61
5612 11:16:42.761071 [CA 5] Center 33 (3~64) winsize 62
5613 11:16:42.761512
5614 11:16:42.764334 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5615 11:16:42.764846
5616 11:16:42.768027 [CATrainingPosCal] consider 1 rank data
5617 11:16:42.771191 u2DelayCellTimex100 = 270/100 ps
5618 11:16:42.774589 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5619 11:16:42.777528 CA1 delay=37 (6~68),Diff = 4 PI (24 cell)
5620 11:16:42.781475 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5621 11:16:42.784328 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5622 11:16:42.788248 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5623 11:16:42.794002 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5624 11:16:42.794423
5625 11:16:42.797211 CA PerBit enable=1, Macro0, CA PI delay=33
5626 11:16:42.797629
5627 11:16:42.801114 [CBTSetCACLKResult] CA Dly = 33
5628 11:16:42.801630 CS Dly: 6 (0~37)
5629 11:16:42.801961 ==
5630 11:16:42.804086 Dram Type= 6, Freq= 0, CH_1, rank 1
5631 11:16:42.810812 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5632 11:16:42.811377 ==
5633 11:16:42.813936 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5634 11:16:42.821159 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5635 11:16:42.824325 [CA 0] Center 36 (6~67) winsize 62
5636 11:16:42.827362 [CA 1] Center 36 (6~67) winsize 62
5637 11:16:42.830794 [CA 2] Center 34 (4~65) winsize 62
5638 11:16:42.834136 [CA 3] Center 34 (3~65) winsize 63
5639 11:16:42.837489 [CA 4] Center 34 (4~65) winsize 62
5640 11:16:42.841008 [CA 5] Center 33 (3~64) winsize 62
5641 11:16:42.841567
5642 11:16:42.844157 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5643 11:16:42.844714
5644 11:16:42.847207 [CATrainingPosCal] consider 2 rank data
5645 11:16:42.850684 u2DelayCellTimex100 = 270/100 ps
5646 11:16:42.853874 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5647 11:16:42.856631 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5648 11:16:42.863317 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5649 11:16:42.866706 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
5650 11:16:42.870045 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5651 11:16:42.873525 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5652 11:16:42.873986
5653 11:16:42.876878 CA PerBit enable=1, Macro0, CA PI delay=33
5654 11:16:42.877291
5655 11:16:42.880059 [CBTSetCACLKResult] CA Dly = 33
5656 11:16:42.880619 CS Dly: 7 (0~39)
5657 11:16:42.880962
5658 11:16:42.883342 ----->DramcWriteLeveling(PI) begin...
5659 11:16:42.886861 ==
5660 11:16:42.890185 Dram Type= 6, Freq= 0, CH_1, rank 0
5661 11:16:42.893057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5662 11:16:42.893479 ==
5663 11:16:42.896542 Write leveling (Byte 0): 23 => 23
5664 11:16:42.900150 Write leveling (Byte 1): 25 => 25
5665 11:16:42.902827 DramcWriteLeveling(PI) end<-----
5666 11:16:42.903336
5667 11:16:42.903666 ==
5668 11:16:42.906492 Dram Type= 6, Freq= 0, CH_1, rank 0
5669 11:16:42.909633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5670 11:16:42.910160 ==
5671 11:16:42.913240 [Gating] SW mode calibration
5672 11:16:42.919432 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5673 11:16:42.926154 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5674 11:16:42.929596 0 14 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5675 11:16:42.932693 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5676 11:16:42.939836 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5677 11:16:42.943097 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5678 11:16:42.946136 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5679 11:16:42.952407 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5680 11:16:42.956288 0 14 24 | B1->B0 | 3434 3232 | 1 0 | (1 0) (0 1)
5681 11:16:42.959358 0 14 28 | B1->B0 | 2f2f 2e2e | 0 0 | (1 1) (1 1)
5682 11:16:42.965801 0 15 0 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
5683 11:16:42.969302 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5684 11:16:42.972331 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5685 11:16:42.978806 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5686 11:16:42.982195 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5687 11:16:42.985748 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5688 11:16:42.992227 0 15 24 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 1)
5689 11:16:42.995409 0 15 28 | B1->B0 | 3535 3d3c | 1 1 | (0 0) (0 0)
5690 11:16:42.998942 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5691 11:16:43.005135 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5692 11:16:43.008426 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5693 11:16:43.011882 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5694 11:16:43.018400 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5695 11:16:43.021747 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5696 11:16:43.024897 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5697 11:16:43.032083 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5698 11:16:43.035203 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5699 11:16:43.038556 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5700 11:16:43.044880 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5701 11:16:43.048360 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5702 11:16:43.051644 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5703 11:16:43.059010 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5704 11:16:43.061023 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5705 11:16:43.065204 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5706 11:16:43.071213 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5707 11:16:43.074280 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5708 11:16:43.078156 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5709 11:16:43.084620 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5710 11:16:43.087515 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5711 11:16:43.091163 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5712 11:16:43.097420 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5713 11:16:43.100873 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5714 11:16:43.104077 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5715 11:16:43.107574 Total UI for P1: 0, mck2ui 16
5716 11:16:43.110952 best dqsien dly found for B0: ( 1, 2, 26)
5717 11:16:43.114612 Total UI for P1: 0, mck2ui 16
5718 11:16:43.117611 best dqsien dly found for B1: ( 1, 2, 26)
5719 11:16:43.120848 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5720 11:16:43.124864 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5721 11:16:43.125429
5722 11:16:43.131179 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5723 11:16:43.133849 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5724 11:16:43.134411 [Gating] SW calibration Done
5725 11:16:43.137553 ==
5726 11:16:43.138014 Dram Type= 6, Freq= 0, CH_1, rank 0
5727 11:16:43.143966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5728 11:16:43.144566 ==
5729 11:16:43.144945 RX Vref Scan: 0
5730 11:16:43.145285
5731 11:16:43.147892 RX Vref 0 -> 0, step: 1
5732 11:16:43.148452
5733 11:16:43.150554 RX Delay -80 -> 252, step: 8
5734 11:16:43.153784 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5735 11:16:43.157019 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5736 11:16:43.161114 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5737 11:16:43.167077 iDelay=208, Bit 3, Center 103 (8 ~ 199) 192
5738 11:16:43.170608 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5739 11:16:43.173944 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5740 11:16:43.177586 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5741 11:16:43.180256 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5742 11:16:43.183493 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5743 11:16:43.190164 iDelay=208, Bit 9, Center 83 (-16 ~ 183) 200
5744 11:16:43.193320 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5745 11:16:43.196933 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5746 11:16:43.200355 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5747 11:16:43.203943 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5748 11:16:43.209766 iDelay=208, Bit 14, Center 95 (-8 ~ 199) 208
5749 11:16:43.213454 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
5750 11:16:43.213874 ==
5751 11:16:43.216363 Dram Type= 6, Freq= 0, CH_1, rank 0
5752 11:16:43.220258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5753 11:16:43.220822 ==
5754 11:16:43.223450 DQS Delay:
5755 11:16:43.223862 DQS0 = 0, DQS1 = 0
5756 11:16:43.224189 DQM Delay:
5757 11:16:43.226646 DQM0 = 100, DQM1 = 90
5758 11:16:43.227161 DQ Delay:
5759 11:16:43.230452 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =103
5760 11:16:43.233027 DQ4 =95, DQ5 =111, DQ6 =111, DQ7 =95
5761 11:16:43.236913 DQ8 =79, DQ9 =83, DQ10 =91, DQ11 =79
5762 11:16:43.240034 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =99
5763 11:16:43.240588
5764 11:16:43.240930
5765 11:16:43.241232 ==
5766 11:16:43.243595 Dram Type= 6, Freq= 0, CH_1, rank 0
5767 11:16:43.249865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5768 11:16:43.250386 ==
5769 11:16:43.250721
5770 11:16:43.251026
5771 11:16:43.253286 TX Vref Scan disable
5772 11:16:43.253702 == TX Byte 0 ==
5773 11:16:43.256341 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5774 11:16:43.263254 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5775 11:16:43.263775 == TX Byte 1 ==
5776 11:16:43.265857 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5777 11:16:43.272495 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5778 11:16:43.273013 ==
5779 11:16:43.276235 Dram Type= 6, Freq= 0, CH_1, rank 0
5780 11:16:43.279513 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5781 11:16:43.280076 ==
5782 11:16:43.280494
5783 11:16:43.280848
5784 11:16:43.282765 TX Vref Scan disable
5785 11:16:43.286350 == TX Byte 0 ==
5786 11:16:43.289218 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5787 11:16:43.292557 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5788 11:16:43.295778 == TX Byte 1 ==
5789 11:16:43.299153 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5790 11:16:43.302787 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5791 11:16:43.303317
5792 11:16:43.305977 [DATLAT]
5793 11:16:43.306488 Freq=933, CH1 RK0
5794 11:16:43.306820
5795 11:16:43.309022 DATLAT Default: 0xd
5796 11:16:43.309433 0, 0xFFFF, sum = 0
5797 11:16:43.312841 1, 0xFFFF, sum = 0
5798 11:16:43.313262 2, 0xFFFF, sum = 0
5799 11:16:43.315973 3, 0xFFFF, sum = 0
5800 11:16:43.316493 4, 0xFFFF, sum = 0
5801 11:16:43.319150 5, 0xFFFF, sum = 0
5802 11:16:43.319669 6, 0xFFFF, sum = 0
5803 11:16:43.322818 7, 0xFFFF, sum = 0
5804 11:16:43.323235 8, 0xFFFF, sum = 0
5805 11:16:43.325423 9, 0xFFFF, sum = 0
5806 11:16:43.325845 10, 0x0, sum = 1
5807 11:16:43.328812 11, 0x0, sum = 2
5808 11:16:43.329341 12, 0x0, sum = 3
5809 11:16:43.332506 13, 0x0, sum = 4
5810 11:16:43.333054 best_step = 11
5811 11:16:43.333384
5812 11:16:43.333686 ==
5813 11:16:43.336025 Dram Type= 6, Freq= 0, CH_1, rank 0
5814 11:16:43.342153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5815 11:16:43.342687 ==
5816 11:16:43.343027 RX Vref Scan: 1
5817 11:16:43.343333
5818 11:16:43.345316 RX Vref 0 -> 0, step: 1
5819 11:16:43.345728
5820 11:16:43.349351 RX Delay -61 -> 252, step: 4
5821 11:16:43.349873
5822 11:16:43.352109 Set Vref, RX VrefLevel [Byte0]: 47
5823 11:16:43.355767 [Byte1]: 53
5824 11:16:43.356285
5825 11:16:43.358334 Final RX Vref Byte 0 = 47 to rank0
5826 11:16:43.361789 Final RX Vref Byte 1 = 53 to rank0
5827 11:16:43.365498 Final RX Vref Byte 0 = 47 to rank1
5828 11:16:43.368823 Final RX Vref Byte 1 = 53 to rank1==
5829 11:16:43.371361 Dram Type= 6, Freq= 0, CH_1, rank 0
5830 11:16:43.374856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5831 11:16:43.375410 ==
5832 11:16:43.378242 DQS Delay:
5833 11:16:43.378655 DQS0 = 0, DQS1 = 0
5834 11:16:43.381168 DQM Delay:
5835 11:16:43.381579 DQM0 = 101, DQM1 = 94
5836 11:16:43.381907 DQ Delay:
5837 11:16:43.385131 DQ0 =106, DQ1 =96, DQ2 =92, DQ3 =98
5838 11:16:43.388215 DQ4 =100, DQ5 =112, DQ6 =108, DQ7 =98
5839 11:16:43.391569 DQ8 =80, DQ9 =88, DQ10 =96, DQ11 =84
5840 11:16:43.398091 DQ12 =102, DQ13 =100, DQ14 =102, DQ15 =104
5841 11:16:43.398625
5842 11:16:43.398965
5843 11:16:43.404952 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c0b, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 412 ps
5844 11:16:43.408387 CH1 RK0: MR19=505, MR18=1C0B
5845 11:16:43.414276 CH1_RK0: MR19=0x505, MR18=0x1C0B, DQSOSC=412, MR23=63, INC=63, DEC=42
5846 11:16:43.414699
5847 11:16:43.417938 ----->DramcWriteLeveling(PI) begin...
5848 11:16:43.418467 ==
5849 11:16:43.421310 Dram Type= 6, Freq= 0, CH_1, rank 1
5850 11:16:43.424223 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5851 11:16:43.424810 ==
5852 11:16:43.428158 Write leveling (Byte 0): 25 => 25
5853 11:16:43.431265 Write leveling (Byte 1): 27 => 27
5854 11:16:43.434391 DramcWriteLeveling(PI) end<-----
5855 11:16:43.434849
5856 11:16:43.435207 ==
5857 11:16:43.437730 Dram Type= 6, Freq= 0, CH_1, rank 1
5858 11:16:43.440877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5859 11:16:43.441437 ==
5860 11:16:43.444339 [Gating] SW mode calibration
5861 11:16:43.450971 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5862 11:16:43.457348 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5863 11:16:43.460877 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5864 11:16:43.467901 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5865 11:16:43.471728 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5866 11:16:43.474449 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5867 11:16:43.480965 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5868 11:16:43.483803 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5869 11:16:43.487163 0 14 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5870 11:16:43.493546 0 14 28 | B1->B0 | 2c2c 2f2f | 1 1 | (1 1) (1 1)
5871 11:16:43.496933 0 15 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (1 0)
5872 11:16:43.500622 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5873 11:16:43.507360 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5874 11:16:43.510366 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5875 11:16:43.513888 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5876 11:16:43.520546 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5877 11:16:43.523320 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5878 11:16:43.527201 0 15 28 | B1->B0 | 3a3a 2f2f | 1 0 | (0 0) (0 0)
5879 11:16:43.533356 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5880 11:16:43.537034 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5881 11:16:43.539948 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5882 11:16:43.546946 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5883 11:16:43.549818 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5884 11:16:43.553084 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5885 11:16:43.559557 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5886 11:16:43.563173 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5887 11:16:43.566582 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5888 11:16:43.573063 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5889 11:16:43.576439 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5890 11:16:43.579905 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5891 11:16:43.586571 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5892 11:16:43.589354 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5893 11:16:43.592600 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5894 11:16:43.600340 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5895 11:16:43.602720 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5896 11:16:43.606599 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5897 11:16:43.612782 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5898 11:16:43.616356 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5899 11:16:43.619216 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5900 11:16:43.626085 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5901 11:16:43.629274 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5902 11:16:43.632424 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5903 11:16:43.636001 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5904 11:16:43.639003 Total UI for P1: 0, mck2ui 16
5905 11:16:43.642275 best dqsien dly found for B0: ( 1, 2, 28)
5906 11:16:43.646041 Total UI for P1: 0, mck2ui 16
5907 11:16:43.648962 best dqsien dly found for B1: ( 1, 2, 26)
5908 11:16:43.655170 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5909 11:16:43.658471 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5910 11:16:43.658929
5911 11:16:43.662055 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5912 11:16:43.665243 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5913 11:16:43.668535 [Gating] SW calibration Done
5914 11:16:43.668999 ==
5915 11:16:43.671809 Dram Type= 6, Freq= 0, CH_1, rank 1
5916 11:16:43.675724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5917 11:16:43.676187 ==
5918 11:16:43.678385 RX Vref Scan: 0
5919 11:16:43.678841
5920 11:16:43.679199 RX Vref 0 -> 0, step: 1
5921 11:16:43.679533
5922 11:16:43.681968 RX Delay -80 -> 252, step: 8
5923 11:16:43.685349 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5924 11:16:43.692077 iDelay=208, Bit 1, Center 91 (0 ~ 183) 184
5925 11:16:43.694699 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5926 11:16:43.698306 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5927 11:16:43.701656 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5928 11:16:43.704934 iDelay=208, Bit 5, Center 107 (16 ~ 199) 184
5929 11:16:43.708691 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5930 11:16:43.715280 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5931 11:16:43.718265 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5932 11:16:43.721336 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5933 11:16:43.724778 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5934 11:16:43.728236 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5935 11:16:43.731537 iDelay=208, Bit 12, Center 99 (0 ~ 199) 200
5936 11:16:43.738100 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
5937 11:16:43.741154 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5938 11:16:43.744435 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5939 11:16:43.744886 ==
5940 11:16:43.748258 Dram Type= 6, Freq= 0, CH_1, rank 1
5941 11:16:43.751259 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5942 11:16:43.751779 ==
5943 11:16:43.754866 DQS Delay:
5944 11:16:43.755375 DQS0 = 0, DQS1 = 0
5945 11:16:43.757894 DQM Delay:
5946 11:16:43.758307 DQM0 = 99, DQM1 = 92
5947 11:16:43.758631 DQ Delay:
5948 11:16:43.760783 DQ0 =103, DQ1 =91, DQ2 =91, DQ3 =99
5949 11:16:43.764185 DQ4 =95, DQ5 =107, DQ6 =111, DQ7 =95
5950 11:16:43.767376 DQ8 =79, DQ9 =83, DQ10 =95, DQ11 =87
5951 11:16:43.770783 DQ12 =99, DQ13 =99, DQ14 =95, DQ15 =103
5952 11:16:43.771199
5953 11:16:43.774029
5954 11:16:43.774442 ==
5955 11:16:43.777816 Dram Type= 6, Freq= 0, CH_1, rank 1
5956 11:16:43.780767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5957 11:16:43.781184 ==
5958 11:16:43.781509
5959 11:16:43.781809
5960 11:16:43.784099 TX Vref Scan disable
5961 11:16:43.784510 == TX Byte 0 ==
5962 11:16:43.790693 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5963 11:16:43.794494 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5964 11:16:43.795001 == TX Byte 1 ==
5965 11:16:43.800994 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5966 11:16:43.804251 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5967 11:16:43.804691 ==
5968 11:16:43.807218 Dram Type= 6, Freq= 0, CH_1, rank 1
5969 11:16:43.810378 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5970 11:16:43.810795 ==
5971 11:16:43.811118
5972 11:16:43.811421
5973 11:16:43.813954 TX Vref Scan disable
5974 11:16:43.817525 == TX Byte 0 ==
5975 11:16:43.820663 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5976 11:16:43.824193 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5977 11:16:43.827428 == TX Byte 1 ==
5978 11:16:43.831120 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5979 11:16:43.834063 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5980 11:16:43.834572
5981 11:16:43.837571 [DATLAT]
5982 11:16:43.838094 Freq=933, CH1 RK1
5983 11:16:43.838437
5984 11:16:43.840555 DATLAT Default: 0xb
5985 11:16:43.840967 0, 0xFFFF, sum = 0
5986 11:16:43.843504 1, 0xFFFF, sum = 0
5987 11:16:43.843923 2, 0xFFFF, sum = 0
5988 11:16:43.847766 3, 0xFFFF, sum = 0
5989 11:16:43.848282 4, 0xFFFF, sum = 0
5990 11:16:43.850395 5, 0xFFFF, sum = 0
5991 11:16:43.850915 6, 0xFFFF, sum = 0
5992 11:16:43.853873 7, 0xFFFF, sum = 0
5993 11:16:43.854296 8, 0xFFFF, sum = 0
5994 11:16:43.857167 9, 0xFFFF, sum = 0
5995 11:16:43.857686 10, 0x0, sum = 1
5996 11:16:43.860862 11, 0x0, sum = 2
5997 11:16:43.861385 12, 0x0, sum = 3
5998 11:16:43.863770 13, 0x0, sum = 4
5999 11:16:43.864292 best_step = 11
6000 11:16:43.864668
6001 11:16:43.864983 ==
6002 11:16:43.866703 Dram Type= 6, Freq= 0, CH_1, rank 1
6003 11:16:43.873706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6004 11:16:43.874357 ==
6005 11:16:43.874702 RX Vref Scan: 0
6006 11:16:43.875009
6007 11:16:43.876842 RX Vref 0 -> 0, step: 1
6008 11:16:43.877257
6009 11:16:43.880114 RX Delay -61 -> 252, step: 4
6010 11:16:43.883442 iDelay=207, Bit 0, Center 106 (19 ~ 194) 176
6011 11:16:43.889892 iDelay=207, Bit 1, Center 94 (7 ~ 182) 176
6012 11:16:43.893430 iDelay=207, Bit 2, Center 90 (3 ~ 178) 176
6013 11:16:43.896670 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
6014 11:16:43.899938 iDelay=207, Bit 4, Center 98 (7 ~ 190) 184
6015 11:16:43.903267 iDelay=207, Bit 5, Center 110 (23 ~ 198) 176
6016 11:16:43.906546 iDelay=207, Bit 6, Center 114 (23 ~ 206) 184
6017 11:16:43.913028 iDelay=207, Bit 7, Center 96 (3 ~ 190) 188
6018 11:16:43.916336 iDelay=207, Bit 8, Center 82 (-9 ~ 174) 184
6019 11:16:43.919785 iDelay=207, Bit 9, Center 86 (-1 ~ 174) 176
6020 11:16:43.923451 iDelay=207, Bit 10, Center 94 (3 ~ 186) 184
6021 11:16:43.926456 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
6022 11:16:43.933046 iDelay=207, Bit 12, Center 102 (11 ~ 194) 184
6023 11:16:43.936434 iDelay=207, Bit 13, Center 100 (11 ~ 190) 180
6024 11:16:43.939593 iDelay=207, Bit 14, Center 98 (7 ~ 190) 184
6025 11:16:43.942511 iDelay=207, Bit 15, Center 100 (7 ~ 194) 188
6026 11:16:43.942930 ==
6027 11:16:43.946180 Dram Type= 6, Freq= 0, CH_1, rank 1
6028 11:16:43.949146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6029 11:16:43.953058 ==
6030 11:16:43.953633 DQS Delay:
6031 11:16:43.953975 DQS0 = 0, DQS1 = 0
6032 11:16:43.956175 DQM Delay:
6033 11:16:43.956615 DQM0 = 100, DQM1 = 93
6034 11:16:43.959207 DQ Delay:
6035 11:16:43.962487 DQ0 =106, DQ1 =94, DQ2 =90, DQ3 =98
6036 11:16:43.965911 DQ4 =98, DQ5 =110, DQ6 =114, DQ7 =96
6037 11:16:43.969220 DQ8 =82, DQ9 =86, DQ10 =94, DQ11 =84
6038 11:16:43.972923 DQ12 =102, DQ13 =100, DQ14 =98, DQ15 =100
6039 11:16:43.973441
6040 11:16:43.973770
6041 11:16:43.978859 [DQSOSCAuto] RK1, (LSB)MR18= 0x902, (MSB)MR19= 0x505, tDQSOscB0 = 421 ps tDQSOscB1 = 419 ps
6042 11:16:43.982542 CH1 RK1: MR19=505, MR18=902
6043 11:16:43.989021 CH1_RK1: MR19=0x505, MR18=0x902, DQSOSC=419, MR23=63, INC=61, DEC=41
6044 11:16:43.992749 [RxdqsGatingPostProcess] freq 933
6045 11:16:43.995645 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6046 11:16:43.998896 best DQS0 dly(2T, 0.5T) = (0, 10)
6047 11:16:44.002266 best DQS1 dly(2T, 0.5T) = (0, 10)
6048 11:16:44.005442 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6049 11:16:44.008902 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6050 11:16:44.012312 best DQS0 dly(2T, 0.5T) = (0, 10)
6051 11:16:44.015387 best DQS1 dly(2T, 0.5T) = (0, 10)
6052 11:16:44.018419 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6053 11:16:44.021987 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6054 11:16:44.025022 Pre-setting of DQS Precalculation
6055 11:16:44.028015 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6056 11:16:44.038280 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6057 11:16:44.045226 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6058 11:16:44.045787
6059 11:16:44.046160
6060 11:16:44.048606 [Calibration Summary] 1866 Mbps
6061 11:16:44.049071 CH 0, Rank 0
6062 11:16:44.051886 SW Impedance : PASS
6063 11:16:44.055020 DUTY Scan : NO K
6064 11:16:44.055482 ZQ Calibration : PASS
6065 11:16:44.057859 Jitter Meter : NO K
6066 11:16:44.058326 CBT Training : PASS
6067 11:16:44.061686 Write leveling : PASS
6068 11:16:44.065186 RX DQS gating : PASS
6069 11:16:44.065758 RX DQ/DQS(RDDQC) : PASS
6070 11:16:44.068160 TX DQ/DQS : PASS
6071 11:16:44.071227 RX DATLAT : PASS
6072 11:16:44.071797 RX DQ/DQS(Engine): PASS
6073 11:16:44.074739 TX OE : NO K
6074 11:16:44.075360 All Pass.
6075 11:16:44.075737
6076 11:16:44.077799 CH 0, Rank 1
6077 11:16:44.078265 SW Impedance : PASS
6078 11:16:44.080959 DUTY Scan : NO K
6079 11:16:44.085098 ZQ Calibration : PASS
6080 11:16:44.085672 Jitter Meter : NO K
6081 11:16:44.087855 CBT Training : PASS
6082 11:16:44.091189 Write leveling : PASS
6083 11:16:44.091758 RX DQS gating : PASS
6084 11:16:44.094743 RX DQ/DQS(RDDQC) : PASS
6085 11:16:44.097883 TX DQ/DQS : PASS
6086 11:16:44.098455 RX DATLAT : PASS
6087 11:16:44.100790 RX DQ/DQS(Engine): PASS
6088 11:16:44.104670 TX OE : NO K
6089 11:16:44.105227 All Pass.
6090 11:16:44.105597
6091 11:16:44.106019 CH 1, Rank 0
6092 11:16:44.108174 SW Impedance : PASS
6093 11:16:44.110948 DUTY Scan : NO K
6094 11:16:44.111430 ZQ Calibration : PASS
6095 11:16:44.114415 Jitter Meter : NO K
6096 11:16:44.118148 CBT Training : PASS
6097 11:16:44.118732 Write leveling : PASS
6098 11:16:44.120627 RX DQS gating : PASS
6099 11:16:44.124187 RX DQ/DQS(RDDQC) : PASS
6100 11:16:44.124817 TX DQ/DQS : PASS
6101 11:16:44.127746 RX DATLAT : PASS
6102 11:16:44.128320 RX DQ/DQS(Engine): PASS
6103 11:16:44.131340 TX OE : NO K
6104 11:16:44.131904 All Pass.
6105 11:16:44.132277
6106 11:16:44.133786 CH 1, Rank 1
6107 11:16:44.134261 SW Impedance : PASS
6108 11:16:44.137706 DUTY Scan : NO K
6109 11:16:44.140510 ZQ Calibration : PASS
6110 11:16:44.141019 Jitter Meter : NO K
6111 11:16:44.144474 CBT Training : PASS
6112 11:16:44.147227 Write leveling : PASS
6113 11:16:44.147820 RX DQS gating : PASS
6114 11:16:44.151152 RX DQ/DQS(RDDQC) : PASS
6115 11:16:44.153982 TX DQ/DQS : PASS
6116 11:16:44.154486 RX DATLAT : PASS
6117 11:16:44.156967 RX DQ/DQS(Engine): PASS
6118 11:16:44.160235 TX OE : NO K
6119 11:16:44.160859 All Pass.
6120 11:16:44.161237
6121 11:16:44.164659 DramC Write-DBI off
6122 11:16:44.165225 PER_BANK_REFRESH: Hybrid Mode
6123 11:16:44.166823 TX_TRACKING: ON
6124 11:16:44.173899 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6125 11:16:44.180543 [FAST_K] Save calibration result to emmc
6126 11:16:44.183422 dramc_set_vcore_voltage set vcore to 650000
6127 11:16:44.183996 Read voltage for 400, 6
6128 11:16:44.186648 Vio18 = 0
6129 11:16:44.187112 Vcore = 650000
6130 11:16:44.187576 Vdram = 0
6131 11:16:44.190667 Vddq = 0
6132 11:16:44.191232 Vmddr = 0
6133 11:16:44.193168 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6134 11:16:44.199977 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6135 11:16:44.203556 MEM_TYPE=3, freq_sel=20
6136 11:16:44.206949 sv_algorithm_assistance_LP4_800
6137 11:16:44.209585 ============ PULL DRAM RESETB DOWN ============
6138 11:16:44.213187 ========== PULL DRAM RESETB DOWN end =========
6139 11:16:44.220126 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6140 11:16:44.223907 ===================================
6141 11:16:44.224470 LPDDR4 DRAM CONFIGURATION
6142 11:16:44.226193 ===================================
6143 11:16:44.229892 EX_ROW_EN[0] = 0x0
6144 11:16:44.230358 EX_ROW_EN[1] = 0x0
6145 11:16:44.232991 LP4Y_EN = 0x0
6146 11:16:44.236209 WORK_FSP = 0x0
6147 11:16:44.236814 WL = 0x2
6148 11:16:44.239569 RL = 0x2
6149 11:16:44.240142 BL = 0x2
6150 11:16:44.242966 RPST = 0x0
6151 11:16:44.243522 RD_PRE = 0x0
6152 11:16:44.247019 WR_PRE = 0x1
6153 11:16:44.247575 WR_PST = 0x0
6154 11:16:44.249623 DBI_WR = 0x0
6155 11:16:44.250107 DBI_RD = 0x0
6156 11:16:44.252958 OTF = 0x1
6157 11:16:44.256132 ===================================
6158 11:16:44.259146 ===================================
6159 11:16:44.259615 ANA top config
6160 11:16:44.262635 ===================================
6161 11:16:44.266256 DLL_ASYNC_EN = 0
6162 11:16:44.268879 ALL_SLAVE_EN = 1
6163 11:16:44.272980 NEW_RANK_MODE = 1
6164 11:16:44.273543 DLL_IDLE_MODE = 1
6165 11:16:44.275740 LP45_APHY_COMB_EN = 1
6166 11:16:44.279683 TX_ODT_DIS = 1
6167 11:16:44.282404 NEW_8X_MODE = 1
6168 11:16:44.285768 ===================================
6169 11:16:44.289094 ===================================
6170 11:16:44.292446 data_rate = 800
6171 11:16:44.293062 CKR = 1
6172 11:16:44.296166 DQ_P2S_RATIO = 4
6173 11:16:44.299201 ===================================
6174 11:16:44.302521 CA_P2S_RATIO = 4
6175 11:16:44.306163 DQ_CA_OPEN = 0
6176 11:16:44.309184 DQ_SEMI_OPEN = 1
6177 11:16:44.312585 CA_SEMI_OPEN = 1
6178 11:16:44.313144 CA_FULL_RATE = 0
6179 11:16:44.315322 DQ_CKDIV4_EN = 0
6180 11:16:44.319052 CA_CKDIV4_EN = 1
6181 11:16:44.322142 CA_PREDIV_EN = 0
6182 11:16:44.325363 PH8_DLY = 0
6183 11:16:44.328352 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6184 11:16:44.328852 DQ_AAMCK_DIV = 0
6185 11:16:44.332321 CA_AAMCK_DIV = 0
6186 11:16:44.335519 CA_ADMCK_DIV = 4
6187 11:16:44.338623 DQ_TRACK_CA_EN = 0
6188 11:16:44.341840 CA_PICK = 800
6189 11:16:44.344827 CA_MCKIO = 400
6190 11:16:44.348763 MCKIO_SEMI = 400
6191 11:16:44.352715 PLL_FREQ = 3016
6192 11:16:44.353268 DQ_UI_PI_RATIO = 32
6193 11:16:44.354825 CA_UI_PI_RATIO = 32
6194 11:16:44.358552 ===================================
6195 11:16:44.361855 ===================================
6196 11:16:44.364995 memory_type:LPDDR4
6197 11:16:44.368265 GP_NUM : 10
6198 11:16:44.368750 SRAM_EN : 1
6199 11:16:44.371625 MD32_EN : 0
6200 11:16:44.374480 ===================================
6201 11:16:44.378435 [ANA_INIT] >>>>>>>>>>>>>>
6202 11:16:44.378893 <<<<<< [CONFIGURE PHASE]: ANA_TX
6203 11:16:44.381166 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6204 11:16:44.384686 ===================================
6205 11:16:44.388344 data_rate = 800,PCW = 0X7400
6206 11:16:44.391586 ===================================
6207 11:16:44.394800 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6208 11:16:44.401258 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6209 11:16:44.413948 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6210 11:16:44.417059 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6211 11:16:44.420572 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6212 11:16:44.423797 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6213 11:16:44.427746 [ANA_INIT] flow start
6214 11:16:44.428309 [ANA_INIT] PLL >>>>>>>>
6215 11:16:44.430536 [ANA_INIT] PLL <<<<<<<<
6216 11:16:44.433923 [ANA_INIT] MIDPI >>>>>>>>
6217 11:16:44.434486 [ANA_INIT] MIDPI <<<<<<<<
6218 11:16:44.436843 [ANA_INIT] DLL >>>>>>>>
6219 11:16:44.440209 [ANA_INIT] flow end
6220 11:16:44.443928 ============ LP4 DIFF to SE enter ============
6221 11:16:44.446938 ============ LP4 DIFF to SE exit ============
6222 11:16:44.450273 [ANA_INIT] <<<<<<<<<<<<<
6223 11:16:44.453462 [Flow] Enable top DCM control >>>>>
6224 11:16:44.456891 [Flow] Enable top DCM control <<<<<
6225 11:16:44.459895 Enable DLL master slave shuffle
6226 11:16:44.466614 ==============================================================
6227 11:16:44.467164 Gating Mode config
6228 11:16:44.473071 ==============================================================
6229 11:16:44.473532 Config description:
6230 11:16:44.483222 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6231 11:16:44.489672 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6232 11:16:44.496177 SELPH_MODE 0: By rank 1: By Phase
6233 11:16:44.499941 ==============================================================
6234 11:16:44.502571 GAT_TRACK_EN = 0
6235 11:16:44.506517 RX_GATING_MODE = 2
6236 11:16:44.509436 RX_GATING_TRACK_MODE = 2
6237 11:16:44.512591 SELPH_MODE = 1
6238 11:16:44.515858 PICG_EARLY_EN = 1
6239 11:16:44.519485 VALID_LAT_VALUE = 1
6240 11:16:44.525571 ==============================================================
6241 11:16:44.529051 Enter into Gating configuration >>>>
6242 11:16:44.532816 Exit from Gating configuration <<<<
6243 11:16:44.535502 Enter into DVFS_PRE_config >>>>>
6244 11:16:44.545553 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6245 11:16:44.549029 Exit from DVFS_PRE_config <<<<<
6246 11:16:44.551875 Enter into PICG configuration >>>>
6247 11:16:44.555538 Exit from PICG configuration <<<<
6248 11:16:44.558801 [RX_INPUT] configuration >>>>>
6249 11:16:44.559214 [RX_INPUT] configuration <<<<<
6250 11:16:44.565417 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6251 11:16:44.571991 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6252 11:16:44.575137 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6253 11:16:44.582019 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6254 11:16:44.588210 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6255 11:16:44.595195 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6256 11:16:44.598706 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6257 11:16:44.602055 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6258 11:16:44.608159 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6259 11:16:44.611153 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6260 11:16:44.614752 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6261 11:16:44.621022 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6262 11:16:44.624286 ===================================
6263 11:16:44.624740 LPDDR4 DRAM CONFIGURATION
6264 11:16:44.628156 ===================================
6265 11:16:44.631080 EX_ROW_EN[0] = 0x0
6266 11:16:44.634080 EX_ROW_EN[1] = 0x0
6267 11:16:44.634495 LP4Y_EN = 0x0
6268 11:16:44.638071 WORK_FSP = 0x0
6269 11:16:44.638486 WL = 0x2
6270 11:16:44.640426 RL = 0x2
6271 11:16:44.640846 BL = 0x2
6272 11:16:44.644071 RPST = 0x0
6273 11:16:44.644485 RD_PRE = 0x0
6274 11:16:44.647188 WR_PRE = 0x1
6275 11:16:44.647601 WR_PST = 0x0
6276 11:16:44.650268 DBI_WR = 0x0
6277 11:16:44.653644 DBI_RD = 0x0
6278 11:16:44.654058 OTF = 0x1
6279 11:16:44.657266 ===================================
6280 11:16:44.660826 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6281 11:16:44.663779 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6282 11:16:44.670686 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6283 11:16:44.673566 ===================================
6284 11:16:44.677138 LPDDR4 DRAM CONFIGURATION
6285 11:16:44.680356 ===================================
6286 11:16:44.680805 EX_ROW_EN[0] = 0x10
6287 11:16:44.683892 EX_ROW_EN[1] = 0x0
6288 11:16:44.684305 LP4Y_EN = 0x0
6289 11:16:44.687105 WORK_FSP = 0x0
6290 11:16:44.687523 WL = 0x2
6291 11:16:44.690604 RL = 0x2
6292 11:16:44.691087 BL = 0x2
6293 11:16:44.693591 RPST = 0x0
6294 11:16:44.694007 RD_PRE = 0x0
6295 11:16:44.696756 WR_PRE = 0x1
6296 11:16:44.697174 WR_PST = 0x0
6297 11:16:44.700254 DBI_WR = 0x0
6298 11:16:44.700688 DBI_RD = 0x0
6299 11:16:44.703445 OTF = 0x1
6300 11:16:44.706837 ===================================
6301 11:16:44.713370 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6302 11:16:44.716583 nWR fixed to 30
6303 11:16:44.720165 [ModeRegInit_LP4] CH0 RK0
6304 11:16:44.720610 [ModeRegInit_LP4] CH0 RK1
6305 11:16:44.723393 [ModeRegInit_LP4] CH1 RK0
6306 11:16:44.726609 [ModeRegInit_LP4] CH1 RK1
6307 11:16:44.727030 match AC timing 19
6308 11:16:44.733055 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6309 11:16:44.736382 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6310 11:16:44.739959 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6311 11:16:44.746071 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6312 11:16:44.749705 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6313 11:16:44.750130 ==
6314 11:16:44.752777 Dram Type= 6, Freq= 0, CH_0, rank 0
6315 11:16:44.755888 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6316 11:16:44.756315 ==
6317 11:16:44.762868 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6318 11:16:44.769314 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6319 11:16:44.772302 [CA 0] Center 36 (8~64) winsize 57
6320 11:16:44.775873 [CA 1] Center 36 (8~64) winsize 57
6321 11:16:44.779219 [CA 2] Center 36 (8~64) winsize 57
6322 11:16:44.782691 [CA 3] Center 36 (8~64) winsize 57
6323 11:16:44.785541 [CA 4] Center 36 (8~64) winsize 57
6324 11:16:44.789041 [CA 5] Center 36 (8~64) winsize 57
6325 11:16:44.789466
6326 11:16:44.792207 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6327 11:16:44.792669
6328 11:16:44.795493 [CATrainingPosCal] consider 1 rank data
6329 11:16:44.798952 u2DelayCellTimex100 = 270/100 ps
6330 11:16:44.802100 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6331 11:16:44.805670 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6332 11:16:44.809133 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6333 11:16:44.812299 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6334 11:16:44.816038 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6335 11:16:44.818275 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6336 11:16:44.818706
6337 11:16:44.825194 CA PerBit enable=1, Macro0, CA PI delay=36
6338 11:16:44.825620
6339 11:16:44.828700 [CBTSetCACLKResult] CA Dly = 36
6340 11:16:44.829143 CS Dly: 1 (0~32)
6341 11:16:44.829478 ==
6342 11:16:44.832182 Dram Type= 6, Freq= 0, CH_0, rank 1
6343 11:16:44.835053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6344 11:16:44.835571 ==
6345 11:16:44.841487 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6346 11:16:44.848048 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6347 11:16:44.851687 [CA 0] Center 36 (8~64) winsize 57
6348 11:16:44.854532 [CA 1] Center 36 (8~64) winsize 57
6349 11:16:44.857769 [CA 2] Center 36 (8~64) winsize 57
6350 11:16:44.861174 [CA 3] Center 36 (8~64) winsize 57
6351 11:16:44.864554 [CA 4] Center 36 (8~64) winsize 57
6352 11:16:44.868096 [CA 5] Center 36 (8~64) winsize 57
6353 11:16:44.868591
6354 11:16:44.871043 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6355 11:16:44.871467
6356 11:16:44.874297 [CATrainingPosCal] consider 2 rank data
6357 11:16:44.877841 u2DelayCellTimex100 = 270/100 ps
6358 11:16:44.881649 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6359 11:16:44.884143 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6360 11:16:44.887682 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6361 11:16:44.891343 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6362 11:16:44.894381 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6363 11:16:44.897681 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6364 11:16:44.898102
6365 11:16:44.900858 CA PerBit enable=1, Macro0, CA PI delay=36
6366 11:16:44.904307
6367 11:16:44.904626 [CBTSetCACLKResult] CA Dly = 36
6368 11:16:44.907463 CS Dly: 1 (0~32)
6369 11:16:44.907756
6370 11:16:44.910745 ----->DramcWriteLeveling(PI) begin...
6371 11:16:44.911042 ==
6372 11:16:44.914228 Dram Type= 6, Freq= 0, CH_0, rank 0
6373 11:16:44.917144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6374 11:16:44.917439 ==
6375 11:16:44.920343 Write leveling (Byte 0): 40 => 8
6376 11:16:44.924051 Write leveling (Byte 1): 32 => 0
6377 11:16:44.927682 DramcWriteLeveling(PI) end<-----
6378 11:16:44.927974
6379 11:16:44.928203 ==
6380 11:16:44.930681 Dram Type= 6, Freq= 0, CH_0, rank 0
6381 11:16:44.933782 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6382 11:16:44.937051 ==
6383 11:16:44.937430 [Gating] SW mode calibration
6384 11:16:44.943865 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6385 11:16:44.950422 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6386 11:16:44.954644 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6387 11:16:44.960579 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6388 11:16:44.964367 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6389 11:16:44.967531 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6390 11:16:44.974055 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6391 11:16:44.977353 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6392 11:16:44.980214 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6393 11:16:44.986626 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6394 11:16:44.990124 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6395 11:16:44.993383 Total UI for P1: 0, mck2ui 16
6396 11:16:44.996816 best dqsien dly found for B0: ( 0, 14, 24)
6397 11:16:45.000567 Total UI for P1: 0, mck2ui 16
6398 11:16:45.003231 best dqsien dly found for B1: ( 0, 14, 24)
6399 11:16:45.006588 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6400 11:16:45.010015 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6401 11:16:45.010521
6402 11:16:45.013543 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6403 11:16:45.016373 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6404 11:16:45.020097 [Gating] SW calibration Done
6405 11:16:45.020639 ==
6406 11:16:45.023360 Dram Type= 6, Freq= 0, CH_0, rank 0
6407 11:16:45.029984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6408 11:16:45.030529 ==
6409 11:16:45.030928 RX Vref Scan: 0
6410 11:16:45.031381
6411 11:16:45.033021 RX Vref 0 -> 0, step: 1
6412 11:16:45.033468
6413 11:16:45.037208 RX Delay -410 -> 252, step: 16
6414 11:16:45.039887 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6415 11:16:45.043100 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6416 11:16:45.050830 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6417 11:16:45.052989 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6418 11:16:45.056934 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6419 11:16:45.059566 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6420 11:16:45.066264 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6421 11:16:45.069456 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6422 11:16:45.073042 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6423 11:16:45.075749 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6424 11:16:45.082281 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6425 11:16:45.085948 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6426 11:16:45.088986 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6427 11:16:45.092362 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6428 11:16:45.099164 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6429 11:16:45.102568 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6430 11:16:45.103243 ==
6431 11:16:45.105811 Dram Type= 6, Freq= 0, CH_0, rank 0
6432 11:16:45.109182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6433 11:16:45.109734 ==
6434 11:16:45.112161 DQS Delay:
6435 11:16:45.112750 DQS0 = 43, DQS1 = 59
6436 11:16:45.115571 DQM Delay:
6437 11:16:45.116132 DQM0 = 10, DQM1 = 13
6438 11:16:45.118885 DQ Delay:
6439 11:16:45.119449 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6440 11:16:45.122891 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =16
6441 11:16:45.125982 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6442 11:16:45.128835 DQ12 =16, DQ13 =24, DQ14 =24, DQ15 =24
6443 11:16:45.129407
6444 11:16:45.129804
6445 11:16:45.130143 ==
6446 11:16:45.132218 Dram Type= 6, Freq= 0, CH_0, rank 0
6447 11:16:45.138806 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6448 11:16:45.139358 ==
6449 11:16:45.139724
6450 11:16:45.140055
6451 11:16:45.140374 TX Vref Scan disable
6452 11:16:45.142260 == TX Byte 0 ==
6453 11:16:45.145433 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6454 11:16:45.150028 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6455 11:16:45.151650 == TX Byte 1 ==
6456 11:16:45.155356 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6457 11:16:45.158627 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6458 11:16:45.162043 ==
6459 11:16:45.165310 Dram Type= 6, Freq= 0, CH_0, rank 0
6460 11:16:45.169070 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6461 11:16:45.169633 ==
6462 11:16:45.170007
6463 11:16:45.170433
6464 11:16:45.171597 TX Vref Scan disable
6465 11:16:45.172054 == TX Byte 0 ==
6466 11:16:45.175336 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6467 11:16:45.181073 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6468 11:16:45.181802 == TX Byte 1 ==
6469 11:16:45.184839 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6470 11:16:45.191772 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6471 11:16:45.192362
6472 11:16:45.192800 [DATLAT]
6473 11:16:45.194502 Freq=400, CH0 RK0
6474 11:16:45.194968
6475 11:16:45.195333 DATLAT Default: 0xf
6476 11:16:45.198101 0, 0xFFFF, sum = 0
6477 11:16:45.198574 1, 0xFFFF, sum = 0
6478 11:16:45.200966 2, 0xFFFF, sum = 0
6479 11:16:45.201438 3, 0xFFFF, sum = 0
6480 11:16:45.204497 4, 0xFFFF, sum = 0
6481 11:16:45.205015 5, 0xFFFF, sum = 0
6482 11:16:45.208027 6, 0xFFFF, sum = 0
6483 11:16:45.208495 7, 0xFFFF, sum = 0
6484 11:16:45.211096 8, 0xFFFF, sum = 0
6485 11:16:45.211669 9, 0xFFFF, sum = 0
6486 11:16:45.214170 10, 0xFFFF, sum = 0
6487 11:16:45.214661 11, 0xFFFF, sum = 0
6488 11:16:45.217741 12, 0xFFFF, sum = 0
6489 11:16:45.218171 13, 0x0, sum = 1
6490 11:16:45.220979 14, 0x0, sum = 2
6491 11:16:45.221410 15, 0x0, sum = 3
6492 11:16:45.224648 16, 0x0, sum = 4
6493 11:16:45.225183 best_step = 14
6494 11:16:45.225520
6495 11:16:45.225845 ==
6496 11:16:45.227684 Dram Type= 6, Freq= 0, CH_0, rank 0
6497 11:16:45.234289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6498 11:16:45.234823 ==
6499 11:16:45.235164 RX Vref Scan: 1
6500 11:16:45.235475
6501 11:16:45.237173 RX Vref 0 -> 0, step: 1
6502 11:16:45.237597
6503 11:16:45.241149 RX Delay -359 -> 252, step: 8
6504 11:16:45.241676
6505 11:16:45.244129 Set Vref, RX VrefLevel [Byte0]: 57
6506 11:16:45.247329 [Byte1]: 57
6507 11:16:45.250654
6508 11:16:45.251171 Final RX Vref Byte 0 = 57 to rank0
6509 11:16:45.254200 Final RX Vref Byte 1 = 57 to rank0
6510 11:16:45.257664 Final RX Vref Byte 0 = 57 to rank1
6511 11:16:45.260510 Final RX Vref Byte 1 = 57 to rank1==
6512 11:16:45.264256 Dram Type= 6, Freq= 0, CH_0, rank 0
6513 11:16:45.270424 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6514 11:16:45.270945 ==
6515 11:16:45.271284 DQS Delay:
6516 11:16:45.273801 DQS0 = 48, DQS1 = 56
6517 11:16:45.274321 DQM Delay:
6518 11:16:45.274657 DQM0 = 12, DQM1 = 8
6519 11:16:45.276903 DQ Delay:
6520 11:16:45.280628 DQ0 =12, DQ1 =16, DQ2 =8, DQ3 =8
6521 11:16:45.283399 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6522 11:16:45.283827 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6523 11:16:45.287335 DQ12 =12, DQ13 =12, DQ14 =20, DQ15 =16
6524 11:16:45.290406
6525 11:16:45.291103
6526 11:16:45.296776 [DQSOSCAuto] RK0, (LSB)MR18= 0xbd7f, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 386 ps
6527 11:16:45.300367 CH0 RK0: MR19=C0C, MR18=BD7F
6528 11:16:45.307237 CH0_RK0: MR19=0xC0C, MR18=0xBD7F, DQSOSC=386, MR23=63, INC=396, DEC=264
6529 11:16:45.307788 ==
6530 11:16:45.310120 Dram Type= 6, Freq= 0, CH_0, rank 1
6531 11:16:45.313260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6532 11:16:45.313774 ==
6533 11:16:45.316607 [Gating] SW mode calibration
6534 11:16:45.323265 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6535 11:16:45.329545 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6536 11:16:45.332968 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6537 11:16:45.336132 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6538 11:16:45.343224 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6539 11:16:45.346238 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6540 11:16:45.349651 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6541 11:16:45.356101 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6542 11:16:45.359511 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6543 11:16:45.362816 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6544 11:16:45.369061 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6545 11:16:45.372339 Total UI for P1: 0, mck2ui 16
6546 11:16:45.376079 best dqsien dly found for B0: ( 0, 14, 24)
6547 11:16:45.376682 Total UI for P1: 0, mck2ui 16
6548 11:16:45.382285 best dqsien dly found for B1: ( 0, 14, 24)
6549 11:16:45.385995 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6550 11:16:45.389297 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6551 11:16:45.389756
6552 11:16:45.392312 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6553 11:16:45.395682 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6554 11:16:45.398732 [Gating] SW calibration Done
6555 11:16:45.399189 ==
6556 11:16:45.402582 Dram Type= 6, Freq= 0, CH_0, rank 1
6557 11:16:45.405340 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6558 11:16:45.405757 ==
6559 11:16:45.408876 RX Vref Scan: 0
6560 11:16:45.409331
6561 11:16:45.412125 RX Vref 0 -> 0, step: 1
6562 11:16:45.412570
6563 11:16:45.412941 RX Delay -410 -> 252, step: 16
6564 11:16:45.418593 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6565 11:16:45.421826 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6566 11:16:45.425319 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6567 11:16:45.431923 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6568 11:16:45.435431 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6569 11:16:45.438530 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6570 11:16:45.442007 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6571 11:16:45.448202 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6572 11:16:45.452096 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6573 11:16:45.455220 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6574 11:16:45.458194 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6575 11:16:45.465034 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6576 11:16:45.468236 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6577 11:16:45.471724 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6578 11:16:45.474763 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6579 11:16:45.481058 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6580 11:16:45.481500 ==
6581 11:16:45.484752 Dram Type= 6, Freq= 0, CH_0, rank 1
6582 11:16:45.487825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6583 11:16:45.488257 ==
6584 11:16:45.491211 DQS Delay:
6585 11:16:45.491626 DQS0 = 43, DQS1 = 59
6586 11:16:45.491952 DQM Delay:
6587 11:16:45.494451 DQM0 = 9, DQM1 = 16
6588 11:16:45.494971 DQ Delay:
6589 11:16:45.498100 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6590 11:16:45.500834 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6591 11:16:45.504074 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6592 11:16:45.507686 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6593 11:16:45.508103
6594 11:16:45.508425
6595 11:16:45.508777 ==
6596 11:16:45.510548 Dram Type= 6, Freq= 0, CH_0, rank 1
6597 11:16:45.514294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6598 11:16:45.514713 ==
6599 11:16:45.517522
6600 11:16:45.517931
6601 11:16:45.518254 TX Vref Scan disable
6602 11:16:45.521286 == TX Byte 0 ==
6603 11:16:45.524313 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6604 11:16:45.527191 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6605 11:16:45.530246 == TX Byte 1 ==
6606 11:16:45.533976 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6607 11:16:45.537202 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6608 11:16:45.537618 ==
6609 11:16:45.540324 Dram Type= 6, Freq= 0, CH_0, rank 1
6610 11:16:45.544475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6611 11:16:45.547251 ==
6612 11:16:45.547763
6613 11:16:45.548095
6614 11:16:45.548395 TX Vref Scan disable
6615 11:16:45.550566 == TX Byte 0 ==
6616 11:16:45.553402 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6617 11:16:45.556816 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6618 11:16:45.560367 == TX Byte 1 ==
6619 11:16:45.563358 Update DQ dly =577 (4 ,2, 1) DQ OEN =(3 ,3)
6620 11:16:45.567161 Update DQM dly =577 (4 ,2, 1) DQM OEN =(3 ,3)
6621 11:16:45.567680
6622 11:16:45.570335 [DATLAT]
6623 11:16:45.570843 Freq=400, CH0 RK1
6624 11:16:45.571184
6625 11:16:45.574001 DATLAT Default: 0xe
6626 11:16:45.574532 0, 0xFFFF, sum = 0
6627 11:16:45.576868 1, 0xFFFF, sum = 0
6628 11:16:45.577578 2, 0xFFFF, sum = 0
6629 11:16:45.580324 3, 0xFFFF, sum = 0
6630 11:16:45.580788 4, 0xFFFF, sum = 0
6631 11:16:45.583555 5, 0xFFFF, sum = 0
6632 11:16:45.583976 6, 0xFFFF, sum = 0
6633 11:16:45.586753 7, 0xFFFF, sum = 0
6634 11:16:45.587187 8, 0xFFFF, sum = 0
6635 11:16:45.590225 9, 0xFFFF, sum = 0
6636 11:16:45.590646 10, 0xFFFF, sum = 0
6637 11:16:45.593151 11, 0xFFFF, sum = 0
6638 11:16:45.596902 12, 0xFFFF, sum = 0
6639 11:16:45.597324 13, 0x0, sum = 1
6640 11:16:45.597654 14, 0x0, sum = 2
6641 11:16:45.600069 15, 0x0, sum = 3
6642 11:16:45.600485 16, 0x0, sum = 4
6643 11:16:45.603272 best_step = 14
6644 11:16:45.603825
6645 11:16:45.604277 ==
6646 11:16:45.606769 Dram Type= 6, Freq= 0, CH_0, rank 1
6647 11:16:45.610355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6648 11:16:45.610771 ==
6649 11:16:45.612879 RX Vref Scan: 0
6650 11:16:45.613290
6651 11:16:45.613612 RX Vref 0 -> 0, step: 1
6652 11:16:45.613953
6653 11:16:45.616183 RX Delay -359 -> 252, step: 8
6654 11:16:45.625913 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6655 11:16:45.628320 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6656 11:16:45.631006 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6657 11:16:45.637955 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6658 11:16:45.641202 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6659 11:16:45.644763 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6660 11:16:45.647694 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6661 11:16:45.654761 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6662 11:16:45.657580 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6663 11:16:45.660864 iDelay=217, Bit 9, Center -56 (-303 ~ 192) 496
6664 11:16:45.664319 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6665 11:16:45.671320 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6666 11:16:45.674340 iDelay=217, Bit 12, Center -40 (-287 ~ 208) 496
6667 11:16:45.678183 iDelay=217, Bit 13, Center -40 (-287 ~ 208) 496
6668 11:16:45.681259 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6669 11:16:45.688196 iDelay=217, Bit 15, Center -40 (-287 ~ 208) 496
6670 11:16:45.688794 ==
6671 11:16:45.691268 Dram Type= 6, Freq= 0, CH_0, rank 1
6672 11:16:45.694249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6673 11:16:45.694741 ==
6674 11:16:45.695105 DQS Delay:
6675 11:16:45.697587 DQS0 = 44, DQS1 = 56
6676 11:16:45.698198 DQM Delay:
6677 11:16:45.700772 DQM0 = 8, DQM1 = 11
6678 11:16:45.701229 DQ Delay:
6679 11:16:45.704171 DQ0 =4, DQ1 =12, DQ2 =4, DQ3 =8
6680 11:16:45.707834 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6681 11:16:45.710946 DQ8 =4, DQ9 =0, DQ10 =16, DQ11 =4
6682 11:16:45.714809 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =16
6683 11:16:45.715341
6684 11:16:45.715677
6685 11:16:45.721131 [DQSOSCAuto] RK1, (LSB)MR18= 0xb13e, (MSB)MR19= 0xc0c, tDQSOscB0 = 402 ps tDQSOscB1 = 387 ps
6686 11:16:45.724302 CH0 RK1: MR19=C0C, MR18=B13E
6687 11:16:45.730660 CH0_RK1: MR19=0xC0C, MR18=0xB13E, DQSOSC=387, MR23=63, INC=394, DEC=262
6688 11:16:45.734021 [RxdqsGatingPostProcess] freq 400
6689 11:16:45.740724 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6690 11:16:45.744217 best DQS0 dly(2T, 0.5T) = (0, 10)
6691 11:16:45.744905 best DQS1 dly(2T, 0.5T) = (0, 10)
6692 11:16:45.747154 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6693 11:16:45.750025 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6694 11:16:45.753278 best DQS0 dly(2T, 0.5T) = (0, 10)
6695 11:16:45.757412 best DQS1 dly(2T, 0.5T) = (0, 10)
6696 11:16:45.760091 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6697 11:16:45.763638 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6698 11:16:45.766975 Pre-setting of DQS Precalculation
6699 11:16:45.773219 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6700 11:16:45.773680 ==
6701 11:16:45.776922 Dram Type= 6, Freq= 0, CH_1, rank 0
6702 11:16:45.780380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6703 11:16:45.780838 ==
6704 11:16:45.786692 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6705 11:16:45.793442 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6706 11:16:45.796673 [CA 0] Center 36 (8~64) winsize 57
6707 11:16:45.797087 [CA 1] Center 36 (8~64) winsize 57
6708 11:16:45.799785 [CA 2] Center 36 (8~64) winsize 57
6709 11:16:45.803167 [CA 3] Center 36 (8~64) winsize 57
6710 11:16:45.806679 [CA 4] Center 36 (8~64) winsize 57
6711 11:16:45.810150 [CA 5] Center 36 (8~64) winsize 57
6712 11:16:45.810661
6713 11:16:45.813488 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6714 11:16:45.814001
6715 11:16:45.819698 [CATrainingPosCal] consider 1 rank data
6716 11:16:45.820218 u2DelayCellTimex100 = 270/100 ps
6717 11:16:45.826218 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6718 11:16:45.829644 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6719 11:16:45.832720 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6720 11:16:45.836242 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6721 11:16:45.839038 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6722 11:16:45.842788 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6723 11:16:45.843264
6724 11:16:45.845524 CA PerBit enable=1, Macro0, CA PI delay=36
6725 11:16:45.845938
6726 11:16:45.849303 [CBTSetCACLKResult] CA Dly = 36
6727 11:16:45.852977 CS Dly: 1 (0~32)
6728 11:16:45.853497 ==
6729 11:16:45.855543 Dram Type= 6, Freq= 0, CH_1, rank 1
6730 11:16:45.859168 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6731 11:16:45.859583 ==
6732 11:16:45.865752 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6733 11:16:45.869121 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6734 11:16:45.872291 [CA 0] Center 36 (8~64) winsize 57
6735 11:16:45.875223 [CA 1] Center 36 (8~64) winsize 57
6736 11:16:45.878571 [CA 2] Center 36 (8~64) winsize 57
6737 11:16:45.882676 [CA 3] Center 36 (8~64) winsize 57
6738 11:16:45.885092 [CA 4] Center 36 (8~64) winsize 57
6739 11:16:45.888792 [CA 5] Center 36 (8~64) winsize 57
6740 11:16:45.889204
6741 11:16:45.892228 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6742 11:16:45.892784
6743 11:16:45.895449 [CATrainingPosCal] consider 2 rank data
6744 11:16:45.898470 u2DelayCellTimex100 = 270/100 ps
6745 11:16:45.902178 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6746 11:16:45.908897 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6747 11:16:45.912028 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6748 11:16:45.915179 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6749 11:16:45.918350 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6750 11:16:45.921635 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6751 11:16:45.922153
6752 11:16:45.925073 CA PerBit enable=1, Macro0, CA PI delay=36
6753 11:16:45.925592
6754 11:16:45.927988 [CBTSetCACLKResult] CA Dly = 36
6755 11:16:45.932003 CS Dly: 1 (0~32)
6756 11:16:45.932654
6757 11:16:45.934854 ----->DramcWriteLeveling(PI) begin...
6758 11:16:45.935373 ==
6759 11:16:45.937820 Dram Type= 6, Freq= 0, CH_1, rank 0
6760 11:16:45.941602 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6761 11:16:45.942156 ==
6762 11:16:45.945299 Write leveling (Byte 0): 40 => 8
6763 11:16:45.948048 Write leveling (Byte 1): 40 => 8
6764 11:16:45.951509 DramcWriteLeveling(PI) end<-----
6765 11:16:45.952072
6766 11:16:45.952405 ==
6767 11:16:45.954971 Dram Type= 6, Freq= 0, CH_1, rank 0
6768 11:16:45.958184 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6769 11:16:45.958688 ==
6770 11:16:45.960931 [Gating] SW mode calibration
6771 11:16:45.967723 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6772 11:16:45.974000 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6773 11:16:45.977712 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6774 11:16:45.980817 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6775 11:16:45.987360 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6776 11:16:45.990620 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6777 11:16:45.994425 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6778 11:16:46.000485 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6779 11:16:46.003999 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6780 11:16:46.007233 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6781 11:16:46.013452 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6782 11:16:46.017057 Total UI for P1: 0, mck2ui 16
6783 11:16:46.020674 best dqsien dly found for B0: ( 0, 14, 24)
6784 11:16:46.023729 Total UI for P1: 0, mck2ui 16
6785 11:16:46.026691 best dqsien dly found for B1: ( 0, 14, 24)
6786 11:16:46.030679 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6787 11:16:46.033235 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6788 11:16:46.033713
6789 11:16:46.036421 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6790 11:16:46.040194 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6791 11:16:46.043528 [Gating] SW calibration Done
6792 11:16:46.044104 ==
6793 11:16:46.046761 Dram Type= 6, Freq= 0, CH_1, rank 0
6794 11:16:46.049872 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6795 11:16:46.050356 ==
6796 11:16:46.052888 RX Vref Scan: 0
6797 11:16:46.053368
6798 11:16:46.056269 RX Vref 0 -> 0, step: 1
6799 11:16:46.056957
6800 11:16:46.059476 RX Delay -410 -> 252, step: 16
6801 11:16:46.063909 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6802 11:16:46.066330 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6803 11:16:46.069762 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6804 11:16:46.076627 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6805 11:16:46.079364 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6806 11:16:46.082568 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6807 11:16:46.086332 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6808 11:16:46.092861 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6809 11:16:46.096495 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6810 11:16:46.099488 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6811 11:16:46.102808 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6812 11:16:46.109239 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6813 11:16:46.112713 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6814 11:16:46.115873 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6815 11:16:46.122282 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6816 11:16:46.126105 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6817 11:16:46.126670 ==
6818 11:16:46.128912 Dram Type= 6, Freq= 0, CH_1, rank 0
6819 11:16:46.132316 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6820 11:16:46.132906 ==
6821 11:16:46.135732 DQS Delay:
6822 11:16:46.136294 DQS0 = 43, DQS1 = 51
6823 11:16:46.136702 DQM Delay:
6824 11:16:46.139419 DQM0 = 12, DQM1 = 14
6825 11:16:46.139985 DQ Delay:
6826 11:16:46.142884 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6827 11:16:46.146042 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6828 11:16:46.148863 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6829 11:16:46.151853 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6830 11:16:46.152411
6831 11:16:46.152812
6832 11:16:46.153228 ==
6833 11:16:46.155127 Dram Type= 6, Freq= 0, CH_1, rank 0
6834 11:16:46.158404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6835 11:16:46.161766 ==
6836 11:16:46.162225
6837 11:16:46.162584
6838 11:16:46.162919 TX Vref Scan disable
6839 11:16:46.165194 == TX Byte 0 ==
6840 11:16:46.168807 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6841 11:16:46.171908 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6842 11:16:46.175288 == TX Byte 1 ==
6843 11:16:46.178459 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6844 11:16:46.181468 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6845 11:16:46.181893 ==
6846 11:16:46.184896 Dram Type= 6, Freq= 0, CH_1, rank 0
6847 11:16:46.188473 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6848 11:16:46.192102 ==
6849 11:16:46.192623
6850 11:16:46.192959
6851 11:16:46.193263 TX Vref Scan disable
6852 11:16:46.195216 == TX Byte 0 ==
6853 11:16:46.198295 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6854 11:16:46.201706 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6855 11:16:46.205360 == TX Byte 1 ==
6856 11:16:46.208289 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6857 11:16:46.211771 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6858 11:16:46.212257
6859 11:16:46.215001 [DATLAT]
6860 11:16:46.215498 Freq=400, CH1 RK0
6861 11:16:46.215836
6862 11:16:46.218073 DATLAT Default: 0xf
6863 11:16:46.218489 0, 0xFFFF, sum = 0
6864 11:16:46.221433 1, 0xFFFF, sum = 0
6865 11:16:46.221936 2, 0xFFFF, sum = 0
6866 11:16:46.224909 3, 0xFFFF, sum = 0
6867 11:16:46.225424 4, 0xFFFF, sum = 0
6868 11:16:46.228107 5, 0xFFFF, sum = 0
6869 11:16:46.228559 6, 0xFFFF, sum = 0
6870 11:16:46.231105 7, 0xFFFF, sum = 0
6871 11:16:46.231541 8, 0xFFFF, sum = 0
6872 11:16:46.234402 9, 0xFFFF, sum = 0
6873 11:16:46.234897 10, 0xFFFF, sum = 0
6874 11:16:46.237885 11, 0xFFFF, sum = 0
6875 11:16:46.241183 12, 0xFFFF, sum = 0
6876 11:16:46.241705 13, 0x0, sum = 1
6877 11:16:46.244599 14, 0x0, sum = 2
6878 11:16:46.245114 15, 0x0, sum = 3
6879 11:16:46.245454 16, 0x0, sum = 4
6880 11:16:46.248180 best_step = 14
6881 11:16:46.248758
6882 11:16:46.249107 ==
6883 11:16:46.251050 Dram Type= 6, Freq= 0, CH_1, rank 0
6884 11:16:46.254506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6885 11:16:46.255027 ==
6886 11:16:46.257651 RX Vref Scan: 1
6887 11:16:46.258065
6888 11:16:46.260827 RX Vref 0 -> 0, step: 1
6889 11:16:46.261239
6890 11:16:46.261584 RX Delay -343 -> 252, step: 8
6891 11:16:46.261894
6892 11:16:46.264184 Set Vref, RX VrefLevel [Byte0]: 47
6893 11:16:46.267685 [Byte1]: 53
6894 11:16:46.272676
6895 11:16:46.273088 Final RX Vref Byte 0 = 47 to rank0
6896 11:16:46.276154 Final RX Vref Byte 1 = 53 to rank0
6897 11:16:46.279385 Final RX Vref Byte 0 = 47 to rank1
6898 11:16:46.282640 Final RX Vref Byte 1 = 53 to rank1==
6899 11:16:46.285921 Dram Type= 6, Freq= 0, CH_1, rank 0
6900 11:16:46.292958 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6901 11:16:46.293388 ==
6902 11:16:46.293755 DQS Delay:
6903 11:16:46.296032 DQS0 = 44, DQS1 = 56
6904 11:16:46.296454 DQM Delay:
6905 11:16:46.296874 DQM0 = 8, DQM1 = 11
6906 11:16:46.299309 DQ Delay:
6907 11:16:46.302306 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
6908 11:16:46.305924 DQ4 =4, DQ5 =20, DQ6 =16, DQ7 =4
6909 11:16:46.306395 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6910 11:16:46.312346 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =20
6911 11:16:46.312925
6912 11:16:46.313261
6913 11:16:46.319294 [DQSOSCAuto] RK0, (LSB)MR18= 0x976d, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 390 ps
6914 11:16:46.322148 CH1 RK0: MR19=C0C, MR18=976D
6915 11:16:46.328874 CH1_RK0: MR19=0xC0C, MR18=0x976D, DQSOSC=390, MR23=63, INC=388, DEC=258
6916 11:16:46.329394 ==
6917 11:16:46.332105 Dram Type= 6, Freq= 0, CH_1, rank 1
6918 11:16:46.335370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6919 11:16:46.335893 ==
6920 11:16:46.338477 [Gating] SW mode calibration
6921 11:16:46.345089 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6922 11:16:46.351788 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6923 11:16:46.355275 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6924 11:16:46.358396 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6925 11:16:46.364791 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6926 11:16:46.368146 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6927 11:16:46.371344 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6928 11:16:46.378246 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6929 11:16:46.382186 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6930 11:16:46.385246 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6931 11:16:46.391166 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6932 11:16:46.391720 Total UI for P1: 0, mck2ui 16
6933 11:16:46.398005 best dqsien dly found for B0: ( 0, 14, 24)
6934 11:16:46.398490 Total UI for P1: 0, mck2ui 16
6935 11:16:46.404362 best dqsien dly found for B1: ( 0, 14, 24)
6936 11:16:46.408085 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6937 11:16:46.410881 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6938 11:16:46.411309
6939 11:16:46.415029 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6940 11:16:46.417558 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6941 11:16:46.421260 [Gating] SW calibration Done
6942 11:16:46.421766 ==
6943 11:16:46.424700 Dram Type= 6, Freq= 0, CH_1, rank 1
6944 11:16:46.427875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6945 11:16:46.428395 ==
6946 11:16:46.431548 RX Vref Scan: 0
6947 11:16:46.432064
6948 11:16:46.434221 RX Vref 0 -> 0, step: 1
6949 11:16:46.434731
6950 11:16:46.435068 RX Delay -410 -> 252, step: 16
6951 11:16:46.441619 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6952 11:16:46.444510 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6953 11:16:46.447755 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
6954 11:16:46.454419 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6955 11:16:46.457196 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6956 11:16:46.460613 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6957 11:16:46.463967 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6958 11:16:46.470647 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6959 11:16:46.473554 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6960 11:16:46.477333 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6961 11:16:46.480300 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6962 11:16:46.487274 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6963 11:16:46.489748 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6964 11:16:46.493514 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6965 11:16:46.499877 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6966 11:16:46.503137 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6967 11:16:46.503561 ==
6968 11:16:46.506397 Dram Type= 6, Freq= 0, CH_1, rank 1
6969 11:16:46.509967 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6970 11:16:46.510494 ==
6971 11:16:46.512825 DQS Delay:
6972 11:16:46.513245 DQS0 = 51, DQS1 = 51
6973 11:16:46.513582 DQM Delay:
6974 11:16:46.516731 DQM0 = 18, DQM1 = 14
6975 11:16:46.517153 DQ Delay:
6976 11:16:46.519407 DQ0 =16, DQ1 =16, DQ2 =0, DQ3 =16
6977 11:16:46.523306 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6978 11:16:46.526302 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6979 11:16:46.529332 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6980 11:16:46.529849
6981 11:16:46.530180
6982 11:16:46.530488 ==
6983 11:16:46.532713 Dram Type= 6, Freq= 0, CH_1, rank 1
6984 11:16:46.539708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6985 11:16:46.540226 ==
6986 11:16:46.540598
6987 11:16:46.540912
6988 11:16:46.541208 TX Vref Scan disable
6989 11:16:46.542674 == TX Byte 0 ==
6990 11:16:46.546194 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6991 11:16:46.549662 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6992 11:16:46.552668 == TX Byte 1 ==
6993 11:16:46.555472 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6994 11:16:46.559157 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6995 11:16:46.559690 ==
6996 11:16:46.562150 Dram Type= 6, Freq= 0, CH_1, rank 1
6997 11:16:46.568936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6998 11:16:46.569423 ==
6999 11:16:46.569754
7000 11:16:46.570061
7001 11:16:46.571802 TX Vref Scan disable
7002 11:16:46.572221 == TX Byte 0 ==
7003 11:16:46.575166 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
7004 11:16:46.581903 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
7005 11:16:46.582367 == TX Byte 1 ==
7006 11:16:46.585344 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
7007 11:16:46.591780 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
7008 11:16:46.592242
7009 11:16:46.592655 [DATLAT]
7010 11:16:46.593003 Freq=400, CH1 RK1
7011 11:16:46.593334
7012 11:16:46.594794 DATLAT Default: 0xe
7013 11:16:46.595212 0, 0xFFFF, sum = 0
7014 11:16:46.598113 1, 0xFFFF, sum = 0
7015 11:16:46.601347 2, 0xFFFF, sum = 0
7016 11:16:46.601805 3, 0xFFFF, sum = 0
7017 11:16:46.604966 4, 0xFFFF, sum = 0
7018 11:16:46.605390 5, 0xFFFF, sum = 0
7019 11:16:46.607820 6, 0xFFFF, sum = 0
7020 11:16:46.608245 7, 0xFFFF, sum = 0
7021 11:16:46.611371 8, 0xFFFF, sum = 0
7022 11:16:46.611794 9, 0xFFFF, sum = 0
7023 11:16:46.614807 10, 0xFFFF, sum = 0
7024 11:16:46.615229 11, 0xFFFF, sum = 0
7025 11:16:46.617712 12, 0xFFFF, sum = 0
7026 11:16:46.618138 13, 0x0, sum = 1
7027 11:16:46.621189 14, 0x0, sum = 2
7028 11:16:46.621613 15, 0x0, sum = 3
7029 11:16:46.625136 16, 0x0, sum = 4
7030 11:16:46.625657 best_step = 14
7031 11:16:46.625987
7032 11:16:46.626294 ==
7033 11:16:46.628005 Dram Type= 6, Freq= 0, CH_1, rank 1
7034 11:16:46.634739 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7035 11:16:46.635260 ==
7036 11:16:46.635593 RX Vref Scan: 0
7037 11:16:46.635899
7038 11:16:46.638061 RX Vref 0 -> 0, step: 1
7039 11:16:46.638588
7040 11:16:46.641547 RX Delay -343 -> 252, step: 8
7041 11:16:46.647934 iDelay=225, Bit 0, Center -32 (-271 ~ 208) 480
7042 11:16:46.651206 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
7043 11:16:46.654793 iDelay=225, Bit 2, Center -48 (-287 ~ 192) 480
7044 11:16:46.657522 iDelay=225, Bit 3, Center -36 (-271 ~ 200) 472
7045 11:16:46.664432 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
7046 11:16:46.667260 iDelay=225, Bit 5, Center -24 (-263 ~ 216) 480
7047 11:16:46.670947 iDelay=225, Bit 6, Center -20 (-263 ~ 224) 488
7048 11:16:46.674057 iDelay=225, Bit 7, Center -36 (-279 ~ 208) 488
7049 11:16:46.680933 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
7050 11:16:46.684108 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7051 11:16:46.686959 iDelay=225, Bit 10, Center -40 (-287 ~ 208) 496
7052 11:16:46.690571 iDelay=225, Bit 11, Center -52 (-295 ~ 192) 488
7053 11:16:46.697318 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
7054 11:16:46.700270 iDelay=225, Bit 13, Center -40 (-287 ~ 208) 496
7055 11:16:46.703458 iDelay=225, Bit 14, Center -40 (-287 ~ 208) 496
7056 11:16:46.710339 iDelay=225, Bit 15, Center -32 (-279 ~ 216) 496
7057 11:16:46.710890 ==
7058 11:16:46.713264 Dram Type= 6, Freq= 0, CH_1, rank 1
7059 11:16:46.717098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7060 11:16:46.717521 ==
7061 11:16:46.717887 DQS Delay:
7062 11:16:46.720083 DQS0 = 48, DQS1 = 56
7063 11:16:46.720500 DQM Delay:
7064 11:16:46.723401 DQM0 = 14, DQM1 = 12
7065 11:16:46.723932 DQ Delay:
7066 11:16:46.727074 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
7067 11:16:46.729818 DQ4 =12, DQ5 =24, DQ6 =28, DQ7 =12
7068 11:16:46.733674 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
7069 11:16:46.736668 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =24
7070 11:16:46.737151
7071 11:16:46.737484
7072 11:16:46.743139 [DQSOSCAuto] RK1, (LSB)MR18= 0x6757, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
7073 11:16:46.746736 CH1 RK1: MR19=C0C, MR18=6757
7074 11:16:46.753274 CH1_RK1: MR19=0xC0C, MR18=0x6757, DQSOSC=396, MR23=63, INC=376, DEC=251
7075 11:16:46.756597 [RxdqsGatingPostProcess] freq 400
7076 11:16:46.762988 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7077 11:16:46.766091 best DQS0 dly(2T, 0.5T) = (0, 10)
7078 11:16:46.769945 best DQS1 dly(2T, 0.5T) = (0, 10)
7079 11:16:46.773238 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7080 11:16:46.776125 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7081 11:16:46.776561 best DQS0 dly(2T, 0.5T) = (0, 10)
7082 11:16:46.779654 best DQS1 dly(2T, 0.5T) = (0, 10)
7083 11:16:46.782807 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7084 11:16:46.786474 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7085 11:16:46.789055 Pre-setting of DQS Precalculation
7086 11:16:46.795811 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7087 11:16:46.802571 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7088 11:16:46.809193 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7089 11:16:46.809607
7090 11:16:46.809931
7091 11:16:46.812437 [Calibration Summary] 800 Mbps
7092 11:16:46.812876 CH 0, Rank 0
7093 11:16:46.816002 SW Impedance : PASS
7094 11:16:46.819361 DUTY Scan : NO K
7095 11:16:46.819859 ZQ Calibration : PASS
7096 11:16:46.822874 Jitter Meter : NO K
7097 11:16:46.825964 CBT Training : PASS
7098 11:16:46.826654 Write leveling : PASS
7099 11:16:46.829350 RX DQS gating : PASS
7100 11:16:46.832189 RX DQ/DQS(RDDQC) : PASS
7101 11:16:46.832646 TX DQ/DQS : PASS
7102 11:16:46.836257 RX DATLAT : PASS
7103 11:16:46.839574 RX DQ/DQS(Engine): PASS
7104 11:16:46.840260 TX OE : NO K
7105 11:16:46.842634 All Pass.
7106 11:16:46.843241
7107 11:16:46.843732 CH 0, Rank 1
7108 11:16:46.845409 SW Impedance : PASS
7109 11:16:46.845822 DUTY Scan : NO K
7110 11:16:46.849046 ZQ Calibration : PASS
7111 11:16:46.852239 Jitter Meter : NO K
7112 11:16:46.852948 CBT Training : PASS
7113 11:16:46.855593 Write leveling : NO K
7114 11:16:46.858719 RX DQS gating : PASS
7115 11:16:46.859151 RX DQ/DQS(RDDQC) : PASS
7116 11:16:46.862639 TX DQ/DQS : PASS
7117 11:16:46.863236 RX DATLAT : PASS
7118 11:16:46.865415 RX DQ/DQS(Engine): PASS
7119 11:16:46.869172 TX OE : NO K
7120 11:16:46.869789 All Pass.
7121 11:16:46.870174
7122 11:16:46.870518 CH 1, Rank 0
7123 11:16:46.872386 SW Impedance : PASS
7124 11:16:46.875195 DUTY Scan : NO K
7125 11:16:46.875656 ZQ Calibration : PASS
7126 11:16:46.878461 Jitter Meter : NO K
7127 11:16:46.881641 CBT Training : PASS
7128 11:16:46.882100 Write leveling : PASS
7129 11:16:46.885187 RX DQS gating : PASS
7130 11:16:46.888499 RX DQ/DQS(RDDQC) : PASS
7131 11:16:46.888951 TX DQ/DQS : PASS
7132 11:16:46.891857 RX DATLAT : PASS
7133 11:16:46.895268 RX DQ/DQS(Engine): PASS
7134 11:16:46.895761 TX OE : NO K
7135 11:16:46.898623 All Pass.
7136 11:16:46.899146
7137 11:16:46.899478 CH 1, Rank 1
7138 11:16:46.901806 SW Impedance : PASS
7139 11:16:46.902223 DUTY Scan : NO K
7140 11:16:46.904927 ZQ Calibration : PASS
7141 11:16:46.908704 Jitter Meter : NO K
7142 11:16:46.909125 CBT Training : PASS
7143 11:16:46.912171 Write leveling : NO K
7144 11:16:46.915007 RX DQS gating : PASS
7145 11:16:46.915444 RX DQ/DQS(RDDQC) : PASS
7146 11:16:46.918402 TX DQ/DQS : PASS
7147 11:16:46.921810 RX DATLAT : PASS
7148 11:16:46.922229 RX DQ/DQS(Engine): PASS
7149 11:16:46.924835 TX OE : NO K
7150 11:16:46.925254 All Pass.
7151 11:16:46.925582
7152 11:16:46.928388 DramC Write-DBI off
7153 11:16:46.931265 PER_BANK_REFRESH: Hybrid Mode
7154 11:16:46.931682 TX_TRACKING: ON
7155 11:16:46.941379 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7156 11:16:46.944625 [FAST_K] Save calibration result to emmc
7157 11:16:46.947772 dramc_set_vcore_voltage set vcore to 725000
7158 11:16:46.951015 Read voltage for 1600, 0
7159 11:16:46.951432 Vio18 = 0
7160 11:16:46.951758 Vcore = 725000
7161 11:16:46.954722 Vdram = 0
7162 11:16:46.955261 Vddq = 0
7163 11:16:46.955600 Vmddr = 0
7164 11:16:46.960940 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7165 11:16:46.964440 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7166 11:16:46.967628 MEM_TYPE=3, freq_sel=13
7167 11:16:46.970933 sv_algorithm_assistance_LP4_3733
7168 11:16:46.974357 ============ PULL DRAM RESETB DOWN ============
7169 11:16:46.977703 ========== PULL DRAM RESETB DOWN end =========
7170 11:16:46.984392 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7171 11:16:46.987686 ===================================
7172 11:16:46.990878 LPDDR4 DRAM CONFIGURATION
7173 11:16:46.994174 ===================================
7174 11:16:46.994593 EX_ROW_EN[0] = 0x0
7175 11:16:46.997849 EX_ROW_EN[1] = 0x0
7176 11:16:46.998269 LP4Y_EN = 0x0
7177 11:16:47.000597 WORK_FSP = 0x1
7178 11:16:47.001014 WL = 0x5
7179 11:16:47.004211 RL = 0x5
7180 11:16:47.004662 BL = 0x2
7181 11:16:47.007208 RPST = 0x0
7182 11:16:47.007628 RD_PRE = 0x0
7183 11:16:47.010788 WR_PRE = 0x1
7184 11:16:47.011205 WR_PST = 0x1
7185 11:16:47.014022 DBI_WR = 0x0
7186 11:16:47.014446 DBI_RD = 0x0
7187 11:16:47.016966 OTF = 0x1
7188 11:16:47.020456 ===================================
7189 11:16:47.024471 ===================================
7190 11:16:47.024932 ANA top config
7191 11:16:47.027078 ===================================
7192 11:16:47.030435 DLL_ASYNC_EN = 0
7193 11:16:47.033835 ALL_SLAVE_EN = 0
7194 11:16:47.036997 NEW_RANK_MODE = 1
7195 11:16:47.040509 DLL_IDLE_MODE = 1
7196 11:16:47.041066 LP45_APHY_COMB_EN = 1
7197 11:16:47.043704 TX_ODT_DIS = 0
7198 11:16:47.047284 NEW_8X_MODE = 1
7199 11:16:47.050579 ===================================
7200 11:16:47.053658 ===================================
7201 11:16:47.057324 data_rate = 3200
7202 11:16:47.060226 CKR = 1
7203 11:16:47.060778 DQ_P2S_RATIO = 8
7204 11:16:47.063664 ===================================
7205 11:16:47.066638 CA_P2S_RATIO = 8
7206 11:16:47.070087 DQ_CA_OPEN = 0
7207 11:16:47.073397 DQ_SEMI_OPEN = 0
7208 11:16:47.076847 CA_SEMI_OPEN = 0
7209 11:16:47.079860 CA_FULL_RATE = 0
7210 11:16:47.080280 DQ_CKDIV4_EN = 0
7211 11:16:47.083077 CA_CKDIV4_EN = 0
7212 11:16:47.086425 CA_PREDIV_EN = 0
7213 11:16:47.089704 PH8_DLY = 12
7214 11:16:47.093212 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7215 11:16:47.096635 DQ_AAMCK_DIV = 4
7216 11:16:47.097047 CA_AAMCK_DIV = 4
7217 11:16:47.099833 CA_ADMCK_DIV = 4
7218 11:16:47.103436 DQ_TRACK_CA_EN = 0
7219 11:16:47.106747 CA_PICK = 1600
7220 11:16:47.109594 CA_MCKIO = 1600
7221 11:16:47.113015 MCKIO_SEMI = 0
7222 11:16:47.116375 PLL_FREQ = 3068
7223 11:16:47.119845 DQ_UI_PI_RATIO = 32
7224 11:16:47.120336 CA_UI_PI_RATIO = 0
7225 11:16:47.123014 ===================================
7226 11:16:47.126025 ===================================
7227 11:16:47.129395 memory_type:LPDDR4
7228 11:16:47.132794 GP_NUM : 10
7229 11:16:47.133253 SRAM_EN : 1
7230 11:16:47.136048 MD32_EN : 0
7231 11:16:47.139633 ===================================
7232 11:16:47.143071 [ANA_INIT] >>>>>>>>>>>>>>
7233 11:16:47.145890 <<<<<< [CONFIGURE PHASE]: ANA_TX
7234 11:16:47.149182 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7235 11:16:47.152809 ===================================
7236 11:16:47.153357 data_rate = 3200,PCW = 0X7600
7237 11:16:47.156111 ===================================
7238 11:16:47.159244 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7239 11:16:47.166362 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7240 11:16:47.172657 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7241 11:16:47.175797 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7242 11:16:47.178945 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7243 11:16:47.182004 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7244 11:16:47.185368 [ANA_INIT] flow start
7245 11:16:47.188956 [ANA_INIT] PLL >>>>>>>>
7246 11:16:47.189431 [ANA_INIT] PLL <<<<<<<<
7247 11:16:47.192375 [ANA_INIT] MIDPI >>>>>>>>
7248 11:16:47.195730 [ANA_INIT] MIDPI <<<<<<<<
7249 11:16:47.196187 [ANA_INIT] DLL >>>>>>>>
7250 11:16:47.199389 [ANA_INIT] DLL <<<<<<<<
7251 11:16:47.202758 [ANA_INIT] flow end
7252 11:16:47.205708 ============ LP4 DIFF to SE enter ============
7253 11:16:47.208673 ============ LP4 DIFF to SE exit ============
7254 11:16:47.212172 [ANA_INIT] <<<<<<<<<<<<<
7255 11:16:47.215947 [Flow] Enable top DCM control >>>>>
7256 11:16:47.218785 [Flow] Enable top DCM control <<<<<
7257 11:16:47.222274 Enable DLL master slave shuffle
7258 11:16:47.225477 ==============================================================
7259 11:16:47.229153 Gating Mode config
7260 11:16:47.235449 ==============================================================
7261 11:16:47.236036 Config description:
7262 11:16:47.245611 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7263 11:16:47.252150 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7264 11:16:47.258265 SELPH_MODE 0: By rank 1: By Phase
7265 11:16:47.262115 ==============================================================
7266 11:16:47.265439 GAT_TRACK_EN = 1
7267 11:16:47.268623 RX_GATING_MODE = 2
7268 11:16:47.272024 RX_GATING_TRACK_MODE = 2
7269 11:16:47.275169 SELPH_MODE = 1
7270 11:16:47.278475 PICG_EARLY_EN = 1
7271 11:16:47.281712 VALID_LAT_VALUE = 1
7272 11:16:47.285177 ==============================================================
7273 11:16:47.288071 Enter into Gating configuration >>>>
7274 11:16:47.291360 Exit from Gating configuration <<<<
7275 11:16:47.294786 Enter into DVFS_PRE_config >>>>>
7276 11:16:47.308199 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7277 11:16:47.311898 Exit from DVFS_PRE_config <<<<<
7278 11:16:47.314690 Enter into PICG configuration >>>>
7279 11:16:47.318350 Exit from PICG configuration <<<<
7280 11:16:47.318762 [RX_INPUT] configuration >>>>>
7281 11:16:47.321018 [RX_INPUT] configuration <<<<<
7282 11:16:47.327696 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7283 11:16:47.331198 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7284 11:16:47.337424 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7285 11:16:47.343953 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7286 11:16:47.350695 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7287 11:16:47.357318 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7288 11:16:47.360360 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7289 11:16:47.363662 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7290 11:16:47.370663 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7291 11:16:47.373975 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7292 11:16:47.377011 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7293 11:16:47.383331 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7294 11:16:47.386860 ===================================
7295 11:16:47.387288 LPDDR4 DRAM CONFIGURATION
7296 11:16:47.389936 ===================================
7297 11:16:47.393260 EX_ROW_EN[0] = 0x0
7298 11:16:47.393677 EX_ROW_EN[1] = 0x0
7299 11:16:47.396961 LP4Y_EN = 0x0
7300 11:16:47.397375 WORK_FSP = 0x1
7301 11:16:47.400109 WL = 0x5
7302 11:16:47.403702 RL = 0x5
7303 11:16:47.404119 BL = 0x2
7304 11:16:47.406733 RPST = 0x0
7305 11:16:47.407146 RD_PRE = 0x0
7306 11:16:47.410535 WR_PRE = 0x1
7307 11:16:47.411037 WR_PST = 0x1
7308 11:16:47.413240 DBI_WR = 0x0
7309 11:16:47.413651 DBI_RD = 0x0
7310 11:16:47.416654 OTF = 0x1
7311 11:16:47.419736 ===================================
7312 11:16:47.422887 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7313 11:16:47.426619 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7314 11:16:47.432989 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7315 11:16:47.436158 ===================================
7316 11:16:47.436741 LPDDR4 DRAM CONFIGURATION
7317 11:16:47.439866 ===================================
7318 11:16:47.442805 EX_ROW_EN[0] = 0x10
7319 11:16:47.443224 EX_ROW_EN[1] = 0x0
7320 11:16:47.446289 LP4Y_EN = 0x0
7321 11:16:47.449410 WORK_FSP = 0x1
7322 11:16:47.449826 WL = 0x5
7323 11:16:47.452829 RL = 0x5
7324 11:16:47.453244 BL = 0x2
7325 11:16:47.456132 RPST = 0x0
7326 11:16:47.456650 RD_PRE = 0x0
7327 11:16:47.459374 WR_PRE = 0x1
7328 11:16:47.459841 WR_PST = 0x1
7329 11:16:47.462599 DBI_WR = 0x0
7330 11:16:47.463010 DBI_RD = 0x0
7331 11:16:47.465943 OTF = 0x1
7332 11:16:47.469256 ===================================
7333 11:16:47.476136 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7334 11:16:47.476687 ==
7335 11:16:47.479464 Dram Type= 6, Freq= 0, CH_0, rank 0
7336 11:16:47.482381 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7337 11:16:47.482911 ==
7338 11:16:47.485673 [Duty_Offset_Calibration]
7339 11:16:47.486086 B0:1 B1:-1 CA:0
7340 11:16:47.486411
7341 11:16:47.488846 [DutyScan_Calibration_Flow] k_type=0
7342 11:16:47.499831
7343 11:16:47.500317 ==CLK 0==
7344 11:16:47.502782 Final CLK duty delay cell = 0
7345 11:16:47.506415 [0] MAX Duty = 5124%(X100), DQS PI = 22
7346 11:16:47.509569 [0] MIN Duty = 4907%(X100), DQS PI = 6
7347 11:16:47.509993 [0] AVG Duty = 5015%(X100)
7348 11:16:47.512675
7349 11:16:47.516353 CH0 CLK Duty spec in!! Max-Min= 217%
7350 11:16:47.519635 [DutyScan_Calibration_Flow] ====Done====
7351 11:16:47.520097
7352 11:16:47.522812 [DutyScan_Calibration_Flow] k_type=1
7353 11:16:47.538711
7354 11:16:47.539241 ==DQS 0 ==
7355 11:16:47.541985 Final DQS duty delay cell = -4
7356 11:16:47.545596 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7357 11:16:47.548861 [-4] MIN Duty = 4844%(X100), DQS PI = 48
7358 11:16:47.552179 [-4] AVG Duty = 4922%(X100)
7359 11:16:47.552631
7360 11:16:47.552963 ==DQS 1 ==
7361 11:16:47.555381 Final DQS duty delay cell = 0
7362 11:16:47.558286 [0] MAX Duty = 5156%(X100), DQS PI = 0
7363 11:16:47.561596 [0] MIN Duty = 5031%(X100), DQS PI = 18
7364 11:16:47.564755 [0] AVG Duty = 5093%(X100)
7365 11:16:47.565161
7366 11:16:47.568480 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7367 11:16:47.568926
7368 11:16:47.571949 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7369 11:16:47.575210 [DutyScan_Calibration_Flow] ====Done====
7370 11:16:47.575616
7371 11:16:47.578079 [DutyScan_Calibration_Flow] k_type=3
7372 11:16:47.596267
7373 11:16:47.596783 ==DQM 0 ==
7374 11:16:47.599555 Final DQM duty delay cell = 0
7375 11:16:47.602841 [0] MAX Duty = 5124%(X100), DQS PI = 22
7376 11:16:47.606293 [0] MIN Duty = 4876%(X100), DQS PI = 8
7377 11:16:47.609846 [0] AVG Duty = 5000%(X100)
7378 11:16:47.610455
7379 11:16:47.610821 ==DQM 1 ==
7380 11:16:47.612683 Final DQM duty delay cell = 0
7381 11:16:47.616048 [0] MAX Duty = 5031%(X100), DQS PI = 54
7382 11:16:47.619399 [0] MIN Duty = 4813%(X100), DQS PI = 20
7383 11:16:47.622591 [0] AVG Duty = 4922%(X100)
7384 11:16:47.622995
7385 11:16:47.626055 CH0 DQM 0 Duty spec in!! Max-Min= 248%
7386 11:16:47.626464
7387 11:16:47.629065 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7388 11:16:47.632511 [DutyScan_Calibration_Flow] ====Done====
7389 11:16:47.633165
7390 11:16:47.635666 [DutyScan_Calibration_Flow] k_type=2
7391 11:16:47.652648
7392 11:16:47.653143 ==DQ 0 ==
7393 11:16:47.655637 Final DQ duty delay cell = -4
7394 11:16:47.658980 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7395 11:16:47.662454 [-4] MIN Duty = 4876%(X100), DQS PI = 52
7396 11:16:47.665886 [-4] AVG Duty = 4953%(X100)
7397 11:16:47.666341
7398 11:16:47.666697 ==DQ 1 ==
7399 11:16:47.668844 Final DQ duty delay cell = 0
7400 11:16:47.672621 [0] MAX Duty = 5125%(X100), DQS PI = 48
7401 11:16:47.675675 [0] MIN Duty = 4969%(X100), DQS PI = 38
7402 11:16:47.678831 [0] AVG Duty = 5047%(X100)
7403 11:16:47.679330
7404 11:16:47.682304 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7405 11:16:47.682719
7406 11:16:47.685408 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7407 11:16:47.688737 [DutyScan_Calibration_Flow] ====Done====
7408 11:16:47.689235 ==
7409 11:16:47.692505 Dram Type= 6, Freq= 0, CH_1, rank 0
7410 11:16:47.695472 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7411 11:16:47.695930 ==
7412 11:16:47.698565 [Duty_Offset_Calibration]
7413 11:16:47.699084 B0:-1 B1:1 CA:2
7414 11:16:47.702289
7415 11:16:47.705106 [DutyScan_Calibration_Flow] k_type=0
7416 11:16:47.713384
7417 11:16:47.713884 ==CLK 0==
7418 11:16:47.716390 Final CLK duty delay cell = 0
7419 11:16:47.720042 [0] MAX Duty = 5187%(X100), DQS PI = 22
7420 11:16:47.722895 [0] MIN Duty = 5000%(X100), DQS PI = 0
7421 11:16:47.726707 [0] AVG Duty = 5093%(X100)
7422 11:16:47.727291
7423 11:16:47.729728 CH1 CLK Duty spec in!! Max-Min= 187%
7424 11:16:47.732970 [DutyScan_Calibration_Flow] ====Done====
7425 11:16:47.733440
7426 11:16:47.736196 [DutyScan_Calibration_Flow] k_type=1
7427 11:16:47.752853
7428 11:16:47.753524 ==DQS 0 ==
7429 11:16:47.756364 Final DQS duty delay cell = 0
7430 11:16:47.759810 [0] MAX Duty = 5156%(X100), DQS PI = 20
7431 11:16:47.762824 [0] MIN Duty = 4938%(X100), DQS PI = 10
7432 11:16:47.766250 [0] AVG Duty = 5047%(X100)
7433 11:16:47.766705
7434 11:16:47.767059 ==DQS 1 ==
7435 11:16:47.769671 Final DQS duty delay cell = 0
7436 11:16:47.772485 [0] MAX Duty = 5093%(X100), DQS PI = 26
7437 11:16:47.776454 [0] MIN Duty = 4969%(X100), DQS PI = 54
7438 11:16:47.779618 [0] AVG Duty = 5031%(X100)
7439 11:16:47.780074
7440 11:16:47.783027 CH1 DQS 0 Duty spec in!! Max-Min= 218%
7441 11:16:47.783481
7442 11:16:47.785792 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7443 11:16:47.789662 [DutyScan_Calibration_Flow] ====Done====
7444 11:16:47.790216
7445 11:16:47.792737 [DutyScan_Calibration_Flow] k_type=3
7446 11:16:47.809991
7447 11:16:47.810542 ==DQM 0 ==
7448 11:16:47.813123 Final DQM duty delay cell = 0
7449 11:16:47.816340 [0] MAX Duty = 5218%(X100), DQS PI = 38
7450 11:16:47.819883 [0] MIN Duty = 5031%(X100), DQS PI = 8
7451 11:16:47.822627 [0] AVG Duty = 5124%(X100)
7452 11:16:47.823113
7453 11:16:47.823472 ==DQM 1 ==
7454 11:16:47.826052 Final DQM duty delay cell = 0
7455 11:16:47.829497 [0] MAX Duty = 5156%(X100), DQS PI = 6
7456 11:16:47.833270 [0] MIN Duty = 4969%(X100), DQS PI = 32
7457 11:16:47.836256 [0] AVG Duty = 5062%(X100)
7458 11:16:47.836860
7459 11:16:47.839633 CH1 DQM 0 Duty spec in!! Max-Min= 187%
7460 11:16:47.840198
7461 11:16:47.842856 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7462 11:16:47.846433 [DutyScan_Calibration_Flow] ====Done====
7463 11:16:47.846900
7464 11:16:47.849340 [DutyScan_Calibration_Flow] k_type=2
7465 11:16:47.866730
7466 11:16:47.867321 ==DQ 0 ==
7467 11:16:47.869872 Final DQ duty delay cell = 0
7468 11:16:47.873382 [0] MAX Duty = 5156%(X100), DQS PI = 28
7469 11:16:47.876299 [0] MIN Duty = 4906%(X100), DQS PI = 8
7470 11:16:47.876855 [0] AVG Duty = 5031%(X100)
7471 11:16:47.880128
7472 11:16:47.880739 ==DQ 1 ==
7473 11:16:47.883364 Final DQ duty delay cell = 0
7474 11:16:47.886149 [0] MAX Duty = 5156%(X100), DQS PI = 8
7475 11:16:47.889638 [0] MIN Duty = 4969%(X100), DQS PI = 56
7476 11:16:47.890205 [0] AVG Duty = 5062%(X100)
7477 11:16:47.893586
7478 11:16:47.896215 CH1 DQ 0 Duty spec in!! Max-Min= 250%
7479 11:16:47.896711
7480 11:16:47.899969 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7481 11:16:47.902922 [DutyScan_Calibration_Flow] ====Done====
7482 11:16:47.906361 nWR fixed to 30
7483 11:16:47.906921 [ModeRegInit_LP4] CH0 RK0
7484 11:16:47.909044 [ModeRegInit_LP4] CH0 RK1
7485 11:16:47.912598 [ModeRegInit_LP4] CH1 RK0
7486 11:16:47.916928 [ModeRegInit_LP4] CH1 RK1
7487 11:16:47.917489 match AC timing 5
7488 11:16:47.922589 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7489 11:16:47.925714 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7490 11:16:47.929080 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7491 11:16:47.935886 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7492 11:16:47.939366 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7493 11:16:47.939864 [MiockJmeterHQA]
7494 11:16:47.940232
7495 11:16:47.942921 [DramcMiockJmeter] u1RxGatingPI = 0
7496 11:16:47.945892 0 : 4363, 4138
7497 11:16:47.946362 4 : 4252, 4027
7498 11:16:47.949344 8 : 4363, 4137
7499 11:16:47.949807 12 : 4252, 4027
7500 11:16:47.950303 16 : 4252, 4026
7501 11:16:47.952482 20 : 4363, 4137
7502 11:16:47.953106 24 : 4363, 4137
7503 11:16:47.956109 28 : 4252, 4027
7504 11:16:47.956736 32 : 4252, 4027
7505 11:16:47.959170 36 : 4250, 4026
7506 11:16:47.959635 40 : 4363, 4138
7507 11:16:47.962261 44 : 4250, 4027
7508 11:16:47.962766 48 : 4361, 4137
7509 11:16:47.963134 52 : 4253, 4027
7510 11:16:47.966694 56 : 4250, 4027
7511 11:16:47.967419 60 : 4250, 4027
7512 11:16:47.969178 64 : 4252, 4029
7513 11:16:47.969644 68 : 4360, 4138
7514 11:16:47.971991 72 : 4250, 4027
7515 11:16:47.972597 76 : 4361, 4137
7516 11:16:47.975531 80 : 4250, 4027
7517 11:16:47.975994 84 : 4250, 4026
7518 11:16:47.976361 88 : 4250, 4026
7519 11:16:47.979089 92 : 4360, 372
7520 11:16:47.979720 96 : 4252, 0
7521 11:16:47.981852 100 : 4252, 0
7522 11:16:47.982319 104 : 4361, 0
7523 11:16:47.982689 108 : 4360, 0
7524 11:16:47.985208 112 : 4363, 0
7525 11:16:47.985677 116 : 4250, 0
7526 11:16:47.989068 120 : 4361, 0
7527 11:16:47.989597 124 : 4250, 0
7528 11:16:47.989937 128 : 4249, 0
7529 11:16:47.991977 132 : 4253, 0
7530 11:16:47.992397 136 : 4250, 0
7531 11:16:47.994881 140 : 4252, 0
7532 11:16:47.995513 144 : 4363, 0
7533 11:16:47.995867 148 : 4250, 0
7534 11:16:47.998455 152 : 4250, 0
7535 11:16:47.998976 156 : 4253, 0
7536 11:16:48.002274 160 : 4360, 0
7537 11:16:48.002803 164 : 4250, 0
7538 11:16:48.003142 168 : 4253, 0
7539 11:16:48.005424 172 : 4250, 0
7540 11:16:48.005842 176 : 4250, 0
7541 11:16:48.008165 180 : 4252, 0
7542 11:16:48.008641 184 : 4252, 0
7543 11:16:48.008998 188 : 4250, 0
7544 11:16:48.011364 192 : 4252, 0
7545 11:16:48.011784 196 : 4363, 0
7546 11:16:48.012119 200 : 4250, 0
7547 11:16:48.014851 204 : 4250, 0
7548 11:16:48.015375 208 : 4249, 0
7549 11:16:48.018092 212 : 4360, 0
7550 11:16:48.018533 216 : 4361, 0
7551 11:16:48.021518 220 : 4250, 0
7552 11:16:48.022040 224 : 4250, 378
7553 11:16:48.022381 228 : 4252, 3473
7554 11:16:48.024993 232 : 4360, 4137
7555 11:16:48.025414 236 : 4252, 4029
7556 11:16:48.028284 240 : 4250, 4027
7557 11:16:48.028856 244 : 4250, 4027
7558 11:16:48.031088 248 : 4253, 4030
7559 11:16:48.031609 252 : 4250, 4027
7560 11:16:48.035399 256 : 4253, 4029
7561 11:16:48.035905 260 : 4249, 4027
7562 11:16:48.038563 264 : 4252, 4029
7563 11:16:48.039015 268 : 4250, 4027
7564 11:16:48.040928 272 : 4360, 4138
7565 11:16:48.041348 276 : 4360, 4138
7566 11:16:48.044664 280 : 4250, 4027
7567 11:16:48.045199 284 : 4363, 4139
7568 11:16:48.045539 288 : 4360, 4138
7569 11:16:48.047967 292 : 4250, 4027
7570 11:16:48.048490 296 : 4249, 4027
7571 11:16:48.051212 300 : 4252, 4029
7572 11:16:48.051734 304 : 4250, 4027
7573 11:16:48.054519 308 : 4253, 4029
7574 11:16:48.055112 312 : 4250, 4027
7575 11:16:48.057301 316 : 4253, 4029
7576 11:16:48.057723 320 : 4250, 4027
7577 11:16:48.061317 324 : 4360, 4138
7578 11:16:48.061846 328 : 4360, 4138
7579 11:16:48.064089 332 : 4250, 4026
7580 11:16:48.064510 336 : 4363, 3720
7581 11:16:48.067460 340 : 4360, 1840
7582 11:16:48.067975
7583 11:16:48.068381 MIOCK jitter meter ch=0
7584 11:16:48.068753
7585 11:16:48.070719 1T = (340-92) = 248 dly cells
7586 11:16:48.077345 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7587 11:16:48.077764 ==
7588 11:16:48.081149 Dram Type= 6, Freq= 0, CH_0, rank 0
7589 11:16:48.083813 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7590 11:16:48.084280 ==
7591 11:16:48.090484 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7592 11:16:48.093770 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7593 11:16:48.096819 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7594 11:16:48.103556 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7595 11:16:48.116899 [CA 0] Center 43 (12~74) winsize 63
7596 11:16:48.117456 [CA 1] Center 42 (12~73) winsize 62
7597 11:16:48.120238 [CA 2] Center 38 (9~68) winsize 60
7598 11:16:48.123051 [CA 3] Center 38 (8~68) winsize 61
7599 11:16:48.126470 [CA 4] Center 36 (7~66) winsize 60
7600 11:16:48.129865 [CA 5] Center 35 (6~65) winsize 60
7601 11:16:48.130321
7602 11:16:48.132950 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7603 11:16:48.133432
7604 11:16:48.139752 [CATrainingPosCal] consider 1 rank data
7605 11:16:48.140234 u2DelayCellTimex100 = 262/100 ps
7606 11:16:48.146332 CA0 delay=43 (12~74),Diff = 8 PI (29 cell)
7607 11:16:48.149725 CA1 delay=42 (12~73),Diff = 7 PI (26 cell)
7608 11:16:48.152785 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7609 11:16:48.156351 CA3 delay=38 (8~68),Diff = 3 PI (11 cell)
7610 11:16:48.159225 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7611 11:16:48.162867 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7612 11:16:48.163621
7613 11:16:48.166083 CA PerBit enable=1, Macro0, CA PI delay=35
7614 11:16:48.166671
7615 11:16:48.169440 [CBTSetCACLKResult] CA Dly = 35
7616 11:16:48.172481 CS Dly: 12 (0~43)
7617 11:16:48.175862 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7618 11:16:48.178893 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7619 11:16:48.182376 ==
7620 11:16:48.182831 Dram Type= 6, Freq= 0, CH_0, rank 1
7621 11:16:48.189197 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7622 11:16:48.189661 ==
7623 11:16:48.192578 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7624 11:16:48.198772 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7625 11:16:48.202690 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7626 11:16:48.209144 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7627 11:16:48.217078 [CA 0] Center 43 (13~74) winsize 62
7628 11:16:48.220590 [CA 1] Center 44 (14~74) winsize 61
7629 11:16:48.223656 [CA 2] Center 38 (9~68) winsize 60
7630 11:16:48.226855 [CA 3] Center 38 (9~68) winsize 60
7631 11:16:48.230010 [CA 4] Center 36 (7~66) winsize 60
7632 11:16:48.233964 [CA 5] Center 36 (7~66) winsize 60
7633 11:16:48.234482
7634 11:16:48.237113 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7635 11:16:48.237531
7636 11:16:48.240608 [CATrainingPosCal] consider 2 rank data
7637 11:16:48.243319 u2DelayCellTimex100 = 262/100 ps
7638 11:16:48.250313 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7639 11:16:48.253316 CA1 delay=43 (14~73),Diff = 7 PI (26 cell)
7640 11:16:48.256729 CA2 delay=38 (9~68),Diff = 2 PI (7 cell)
7641 11:16:48.260371 CA3 delay=38 (9~68),Diff = 2 PI (7 cell)
7642 11:16:48.263254 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7643 11:16:48.266662 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
7644 11:16:48.267184
7645 11:16:48.269795 CA PerBit enable=1, Macro0, CA PI delay=36
7646 11:16:48.270216
7647 11:16:48.272878 [CBTSetCACLKResult] CA Dly = 36
7648 11:16:48.277138 CS Dly: 12 (0~44)
7649 11:16:48.279830 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7650 11:16:48.283165 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7651 11:16:48.283585
7652 11:16:48.286591 ----->DramcWriteLeveling(PI) begin...
7653 11:16:48.287014 ==
7654 11:16:48.290203 Dram Type= 6, Freq= 0, CH_0, rank 0
7655 11:16:48.296634 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7656 11:16:48.297279 ==
7657 11:16:48.299841 Write leveling (Byte 0): 36 => 36
7658 11:16:48.303114 Write leveling (Byte 1): 26 => 26
7659 11:16:48.303626 DramcWriteLeveling(PI) end<-----
7660 11:16:48.303959
7661 11:16:48.306496 ==
7662 11:16:48.309543 Dram Type= 6, Freq= 0, CH_0, rank 0
7663 11:16:48.312423 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7664 11:16:48.312882 ==
7665 11:16:48.316044 [Gating] SW mode calibration
7666 11:16:48.322888 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7667 11:16:48.325988 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7668 11:16:48.332453 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7669 11:16:48.335917 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7670 11:16:48.339709 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7671 11:16:48.346126 1 4 12 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
7672 11:16:48.349843 1 4 16 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
7673 11:16:48.353064 1 4 20 | B1->B0 | 2525 3434 | 0 1 | (0 0) (1 1)
7674 11:16:48.359136 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7675 11:16:48.362406 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7676 11:16:48.365890 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7677 11:16:48.373014 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7678 11:16:48.375937 1 5 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
7679 11:16:48.378905 1 5 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (1 0)
7680 11:16:48.385372 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7681 11:16:48.388770 1 5 20 | B1->B0 | 3333 2323 | 0 0 | (0 1) (0 0)
7682 11:16:48.392018 1 5 24 | B1->B0 | 2a2a 2323 | 0 0 | (0 0) (0 0)
7683 11:16:48.398381 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7684 11:16:48.402034 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7685 11:16:48.405260 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7686 11:16:48.411496 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7687 11:16:48.415029 1 6 12 | B1->B0 | 2323 3f3f | 0 0 | (0 0) (0 0)
7688 11:16:48.418507 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7689 11:16:48.425392 1 6 20 | B1->B0 | 2828 4646 | 1 0 | (0 0) (0 0)
7690 11:16:48.428208 1 6 24 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
7691 11:16:48.431498 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7692 11:16:48.438314 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7693 11:16:48.441478 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7694 11:16:48.444973 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7695 11:16:48.451422 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7696 11:16:48.454962 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7697 11:16:48.457998 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7698 11:16:48.464963 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7699 11:16:48.467800 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7700 11:16:48.471726 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7701 11:16:48.477557 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7702 11:16:48.481361 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7703 11:16:48.484501 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7704 11:16:48.491032 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7705 11:16:48.494146 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7706 11:16:48.497404 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7707 11:16:48.504285 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7708 11:16:48.508289 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7709 11:16:48.511014 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7710 11:16:48.517435 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7711 11:16:48.520623 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7712 11:16:48.524316 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7713 11:16:48.527900 Total UI for P1: 0, mck2ui 16
7714 11:16:48.530491 best dqsien dly found for B0: ( 1, 9, 10)
7715 11:16:48.537087 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7716 11:16:48.540421 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7717 11:16:48.543797 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7718 11:16:48.547108 Total UI for P1: 0, mck2ui 16
7719 11:16:48.550952 best dqsien dly found for B1: ( 1, 9, 22)
7720 11:16:48.554011 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7721 11:16:48.557262 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7722 11:16:48.557739
7723 11:16:48.563355 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7724 11:16:48.567118 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7725 11:16:48.570362 [Gating] SW calibration Done
7726 11:16:48.570833 ==
7727 11:16:48.573668 Dram Type= 6, Freq= 0, CH_0, rank 0
7728 11:16:48.576615 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7729 11:16:48.577079 ==
7730 11:16:48.577441 RX Vref Scan: 0
7731 11:16:48.579799
7732 11:16:48.580291 RX Vref 0 -> 0, step: 1
7733 11:16:48.580729
7734 11:16:48.583368 RX Delay 0 -> 252, step: 8
7735 11:16:48.586863 iDelay=200, Bit 0, Center 135 (88 ~ 183) 96
7736 11:16:48.590217 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7737 11:16:48.596648 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7738 11:16:48.599622 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7739 11:16:48.603137 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7740 11:16:48.606340 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
7741 11:16:48.609663 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7742 11:16:48.616688 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7743 11:16:48.619431 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
7744 11:16:48.623571 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7745 11:16:48.626559 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7746 11:16:48.629465 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7747 11:16:48.636407 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7748 11:16:48.639608 iDelay=200, Bit 13, Center 131 (80 ~ 183) 104
7749 11:16:48.642775 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
7750 11:16:48.646170 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7751 11:16:48.646740 ==
7752 11:16:48.649519 Dram Type= 6, Freq= 0, CH_0, rank 0
7753 11:16:48.656367 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7754 11:16:48.656970 ==
7755 11:16:48.657344 DQS Delay:
7756 11:16:48.659289 DQS0 = 0, DQS1 = 0
7757 11:16:48.659756 DQM Delay:
7758 11:16:48.663088 DQM0 = 136, DQM1 = 125
7759 11:16:48.663551 DQ Delay:
7760 11:16:48.665824 DQ0 =135, DQ1 =139, DQ2 =131, DQ3 =131
7761 11:16:48.669180 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =147
7762 11:16:48.672633 DQ8 =115, DQ9 =115, DQ10 =127, DQ11 =119
7763 11:16:48.675691 DQ12 =131, DQ13 =131, DQ14 =135, DQ15 =131
7764 11:16:48.676115
7765 11:16:48.676447
7766 11:16:48.676809 ==
7767 11:16:48.679041 Dram Type= 6, Freq= 0, CH_0, rank 0
7768 11:16:48.685914 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7769 11:16:48.686408 ==
7770 11:16:48.686747
7771 11:16:48.687056
7772 11:16:48.687390 TX Vref Scan disable
7773 11:16:48.689156 == TX Byte 0 ==
7774 11:16:48.692575 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7775 11:16:48.699116 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7776 11:16:48.699543 == TX Byte 1 ==
7777 11:16:48.703067 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7778 11:16:48.709074 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7779 11:16:48.709506 ==
7780 11:16:48.712618 Dram Type= 6, Freq= 0, CH_0, rank 0
7781 11:16:48.715612 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7782 11:16:48.716131 ==
7783 11:16:48.729208
7784 11:16:48.732150 TX Vref early break, caculate TX vref
7785 11:16:48.735818 TX Vref=16, minBit 1, minWin=22, winSum=370
7786 11:16:48.738902 TX Vref=18, minBit 0, minWin=23, winSum=380
7787 11:16:48.742174 TX Vref=20, minBit 4, minWin=23, winSum=390
7788 11:16:48.745708 TX Vref=22, minBit 1, minWin=24, winSum=399
7789 11:16:48.749062 TX Vref=24, minBit 0, minWin=25, winSum=408
7790 11:16:48.755284 TX Vref=26, minBit 1, minWin=25, winSum=414
7791 11:16:48.758682 TX Vref=28, minBit 4, minWin=24, winSum=418
7792 11:16:48.761948 TX Vref=30, minBit 0, minWin=24, winSum=407
7793 11:16:48.765694 TX Vref=32, minBit 0, minWin=24, winSum=399
7794 11:16:48.768658 TX Vref=34, minBit 4, minWin=23, winSum=387
7795 11:16:48.775333 [TxChooseVref] Worse bit 1, Min win 25, Win sum 414, Final Vref 26
7796 11:16:48.775840
7797 11:16:48.778301 Final TX Range 0 Vref 26
7798 11:16:48.778727
7799 11:16:48.779061 ==
7800 11:16:48.781908 Dram Type= 6, Freq= 0, CH_0, rank 0
7801 11:16:48.785435 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7802 11:16:48.786120 ==
7803 11:16:48.786671
7804 11:16:48.787037
7805 11:16:48.788686 TX Vref Scan disable
7806 11:16:48.795130 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7807 11:16:48.795625 == TX Byte 0 ==
7808 11:16:48.798181 u2DelayCellOfst[0]=14 cells (4 PI)
7809 11:16:48.801313 u2DelayCellOfst[1]=18 cells (5 PI)
7810 11:16:48.804743 u2DelayCellOfst[2]=14 cells (4 PI)
7811 11:16:48.808603 u2DelayCellOfst[3]=14 cells (4 PI)
7812 11:16:48.811556 u2DelayCellOfst[4]=11 cells (3 PI)
7813 11:16:48.814903 u2DelayCellOfst[5]=0 cells (0 PI)
7814 11:16:48.817984 u2DelayCellOfst[6]=18 cells (5 PI)
7815 11:16:48.821067 u2DelayCellOfst[7]=22 cells (6 PI)
7816 11:16:48.824848 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7817 11:16:48.827986 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7818 11:16:48.830914 == TX Byte 1 ==
7819 11:16:48.834671 u2DelayCellOfst[8]=0 cells (0 PI)
7820 11:16:48.837677 u2DelayCellOfst[9]=3 cells (1 PI)
7821 11:16:48.841065 u2DelayCellOfst[10]=7 cells (2 PI)
7822 11:16:48.844342 u2DelayCellOfst[11]=3 cells (1 PI)
7823 11:16:48.844967 u2DelayCellOfst[12]=14 cells (4 PI)
7824 11:16:48.847919 u2DelayCellOfst[13]=14 cells (4 PI)
7825 11:16:48.850722 u2DelayCellOfst[14]=14 cells (4 PI)
7826 11:16:48.853849 u2DelayCellOfst[15]=11 cells (3 PI)
7827 11:16:48.860859 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
7828 11:16:48.864122 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
7829 11:16:48.864712 DramC Write-DBI on
7830 11:16:48.867899 ==
7831 11:16:48.870668 Dram Type= 6, Freq= 0, CH_0, rank 0
7832 11:16:48.874118 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7833 11:16:48.874584 ==
7834 11:16:48.874947
7835 11:16:48.875282
7836 11:16:48.876843 TX Vref Scan disable
7837 11:16:48.877312 == TX Byte 0 ==
7838 11:16:48.884419 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7839 11:16:48.885029 == TX Byte 1 ==
7840 11:16:48.887222 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
7841 11:16:48.890408 DramC Write-DBI off
7842 11:16:48.890977
7843 11:16:48.891349 [DATLAT]
7844 11:16:48.893386 Freq=1600, CH0 RK0
7845 11:16:48.893870
7846 11:16:48.894240 DATLAT Default: 0xf
7847 11:16:48.897024 0, 0xFFFF, sum = 0
7848 11:16:48.897591 1, 0xFFFF, sum = 0
7849 11:16:48.900359 2, 0xFFFF, sum = 0
7850 11:16:48.903419 3, 0xFFFF, sum = 0
7851 11:16:48.903887 4, 0xFFFF, sum = 0
7852 11:16:48.906584 5, 0xFFFF, sum = 0
7853 11:16:48.907054 6, 0xFFFF, sum = 0
7854 11:16:48.910953 7, 0xFFFF, sum = 0
7855 11:16:48.911394 8, 0xFFFF, sum = 0
7856 11:16:48.913479 9, 0xFFFF, sum = 0
7857 11:16:48.913903 10, 0xFFFF, sum = 0
7858 11:16:48.916351 11, 0xFFFF, sum = 0
7859 11:16:48.916805 12, 0xFFFF, sum = 0
7860 11:16:48.919821 13, 0xFFFF, sum = 0
7861 11:16:48.920245 14, 0x0, sum = 1
7862 11:16:48.923551 15, 0x0, sum = 2
7863 11:16:48.923975 16, 0x0, sum = 3
7864 11:16:48.926048 17, 0x0, sum = 4
7865 11:16:48.926469 best_step = 15
7866 11:16:48.926799
7867 11:16:48.927102 ==
7868 11:16:48.929802 Dram Type= 6, Freq= 0, CH_0, rank 0
7869 11:16:48.936762 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7870 11:16:48.937177 ==
7871 11:16:48.937501 RX Vref Scan: 1
7872 11:16:48.937802
7873 11:16:48.939944 Set Vref Range= 24 -> 127
7874 11:16:48.940388
7875 11:16:48.942725 RX Vref 24 -> 127, step: 1
7876 11:16:48.943138
7877 11:16:48.943466 RX Delay 11 -> 252, step: 4
7878 11:16:48.943788
7879 11:16:48.946454 Set Vref, RX VrefLevel [Byte0]: 24
7880 11:16:48.950957 [Byte1]: 24
7881 11:16:48.954140
7882 11:16:48.954656 Set Vref, RX VrefLevel [Byte0]: 25
7883 11:16:48.957085 [Byte1]: 25
7884 11:16:48.961455
7885 11:16:48.961960 Set Vref, RX VrefLevel [Byte0]: 26
7886 11:16:48.964685 [Byte1]: 26
7887 11:16:48.969234
7888 11:16:48.969665 Set Vref, RX VrefLevel [Byte0]: 27
7889 11:16:48.975667 [Byte1]: 27
7890 11:16:48.976183
7891 11:16:48.978531 Set Vref, RX VrefLevel [Byte0]: 28
7892 11:16:48.981844 [Byte1]: 28
7893 11:16:48.982390
7894 11:16:48.985276 Set Vref, RX VrefLevel [Byte0]: 29
7895 11:16:48.988703 [Byte1]: 29
7896 11:16:48.989117
7897 11:16:48.991834 Set Vref, RX VrefLevel [Byte0]: 30
7898 11:16:48.995018 [Byte1]: 30
7899 11:16:48.999144
7900 11:16:48.999558 Set Vref, RX VrefLevel [Byte0]: 31
7901 11:16:49.002501 [Byte1]: 31
7902 11:16:49.007166
7903 11:16:49.007690 Set Vref, RX VrefLevel [Byte0]: 32
7904 11:16:49.010164 [Byte1]: 32
7905 11:16:49.014226
7906 11:16:49.014774 Set Vref, RX VrefLevel [Byte0]: 33
7907 11:16:49.018151 [Byte1]: 33
7908 11:16:49.022294
7909 11:16:49.022730 Set Vref, RX VrefLevel [Byte0]: 34
7910 11:16:49.025372 [Byte1]: 34
7911 11:16:49.030037
7912 11:16:49.030534 Set Vref, RX VrefLevel [Byte0]: 35
7913 11:16:49.032764 [Byte1]: 35
7914 11:16:49.037576
7915 11:16:49.038049 Set Vref, RX VrefLevel [Byte0]: 36
7916 11:16:49.041173 [Byte1]: 36
7917 11:16:49.045535
7918 11:16:49.046050 Set Vref, RX VrefLevel [Byte0]: 37
7919 11:16:49.049321 [Byte1]: 37
7920 11:16:49.052850
7921 11:16:49.053349 Set Vref, RX VrefLevel [Byte0]: 38
7922 11:16:49.056154 [Byte1]: 38
7923 11:16:49.060584
7924 11:16:49.061059 Set Vref, RX VrefLevel [Byte0]: 39
7925 11:16:49.063244 [Byte1]: 39
7926 11:16:49.067810
7927 11:16:49.068220 Set Vref, RX VrefLevel [Byte0]: 40
7928 11:16:49.074822 [Byte1]: 40
7929 11:16:49.075338
7930 11:16:49.077782 Set Vref, RX VrefLevel [Byte0]: 41
7931 11:16:49.081148 [Byte1]: 41
7932 11:16:49.081662
7933 11:16:49.084897 Set Vref, RX VrefLevel [Byte0]: 42
7934 11:16:49.087673 [Byte1]: 42
7935 11:16:49.091456
7936 11:16:49.091976 Set Vref, RX VrefLevel [Byte0]: 43
7937 11:16:49.094483 [Byte1]: 43
7938 11:16:49.098234
7939 11:16:49.098745 Set Vref, RX VrefLevel [Byte0]: 44
7940 11:16:49.101681 [Byte1]: 44
7941 11:16:49.105992
7942 11:16:49.106506 Set Vref, RX VrefLevel [Byte0]: 45
7943 11:16:49.109518 [Byte1]: 45
7944 11:16:49.114276
7945 11:16:49.114830 Set Vref, RX VrefLevel [Byte0]: 46
7946 11:16:49.116804 [Byte1]: 46
7947 11:16:49.121124
7948 11:16:49.121729 Set Vref, RX VrefLevel [Byte0]: 47
7949 11:16:49.124798 [Byte1]: 47
7950 11:16:49.128664
7951 11:16:49.129129 Set Vref, RX VrefLevel [Byte0]: 48
7952 11:16:49.131848 [Byte1]: 48
7953 11:16:49.136371
7954 11:16:49.137018 Set Vref, RX VrefLevel [Byte0]: 49
7955 11:16:49.140058 [Byte1]: 49
7956 11:16:49.144301
7957 11:16:49.144897 Set Vref, RX VrefLevel [Byte0]: 50
7958 11:16:49.147423 [Byte1]: 50
7959 11:16:49.151408
7960 11:16:49.151872 Set Vref, RX VrefLevel [Byte0]: 51
7961 11:16:49.155292 [Byte1]: 51
7962 11:16:49.159559
7963 11:16:49.160114 Set Vref, RX VrefLevel [Byte0]: 52
7964 11:16:49.162710 [Byte1]: 52
7965 11:16:49.166845
7966 11:16:49.167430 Set Vref, RX VrefLevel [Byte0]: 53
7967 11:16:49.173183 [Byte1]: 53
7968 11:16:49.173713
7969 11:16:49.176774 Set Vref, RX VrefLevel [Byte0]: 54
7970 11:16:49.180274 [Byte1]: 54
7971 11:16:49.180783
7972 11:16:49.183105 Set Vref, RX VrefLevel [Byte0]: 55
7973 11:16:49.186577 [Byte1]: 55
7974 11:16:49.190098
7975 11:16:49.190562 Set Vref, RX VrefLevel [Byte0]: 56
7976 11:16:49.193377 [Byte1]: 56
7977 11:16:49.197260
7978 11:16:49.197812 Set Vref, RX VrefLevel [Byte0]: 57
7979 11:16:49.200696 [Byte1]: 57
7980 11:16:49.205314
7981 11:16:49.205862 Set Vref, RX VrefLevel [Byte0]: 58
7982 11:16:49.208389 [Byte1]: 58
7983 11:16:49.212804
7984 11:16:49.213360 Set Vref, RX VrefLevel [Byte0]: 59
7985 11:16:49.216660 [Byte1]: 59
7986 11:16:49.220596
7987 11:16:49.221149 Set Vref, RX VrefLevel [Byte0]: 60
7988 11:16:49.224274 [Byte1]: 60
7989 11:16:49.227912
7990 11:16:49.228566 Set Vref, RX VrefLevel [Byte0]: 61
7991 11:16:49.230814 [Byte1]: 61
7992 11:16:49.235625
7993 11:16:49.236090 Set Vref, RX VrefLevel [Byte0]: 62
7994 11:16:49.238915 [Byte1]: 62
7995 11:16:49.242616
7996 11:16:49.243104 Set Vref, RX VrefLevel [Byte0]: 63
7997 11:16:49.246479 [Byte1]: 63
7998 11:16:49.250429
7999 11:16:49.250890 Set Vref, RX VrefLevel [Byte0]: 64
8000 11:16:49.254033 [Byte1]: 64
8001 11:16:49.258108
8002 11:16:49.258621 Set Vref, RX VrefLevel [Byte0]: 65
8003 11:16:49.261985 [Byte1]: 65
8004 11:16:49.266102
8005 11:16:49.266614 Set Vref, RX VrefLevel [Byte0]: 66
8006 11:16:49.272406 [Byte1]: 66
8007 11:16:49.272959
8008 11:16:49.275924 Set Vref, RX VrefLevel [Byte0]: 67
8009 11:16:49.278755 [Byte1]: 67
8010 11:16:49.279180
8011 11:16:49.282121 Set Vref, RX VrefLevel [Byte0]: 68
8012 11:16:49.285821 [Byte1]: 68
8013 11:16:49.286339
8014 11:16:49.289111 Set Vref, RX VrefLevel [Byte0]: 69
8015 11:16:49.292344 [Byte1]: 69
8016 11:16:49.296672
8017 11:16:49.297097 Set Vref, RX VrefLevel [Byte0]: 70
8018 11:16:49.299579 [Byte1]: 70
8019 11:16:49.304199
8020 11:16:49.304657 Set Vref, RX VrefLevel [Byte0]: 71
8021 11:16:49.307346 [Byte1]: 71
8022 11:16:49.311644
8023 11:16:49.312199 Set Vref, RX VrefLevel [Byte0]: 72
8024 11:16:49.315386 [Byte1]: 72
8025 11:16:49.319752
8026 11:16:49.320340 Set Vref, RX VrefLevel [Byte0]: 73
8027 11:16:49.322590 [Byte1]: 73
8028 11:16:49.326738
8029 11:16:49.327350 Set Vref, RX VrefLevel [Byte0]: 74
8030 11:16:49.330020 [Byte1]: 74
8031 11:16:49.334200
8032 11:16:49.334662 Set Vref, RX VrefLevel [Byte0]: 75
8033 11:16:49.339041 [Byte1]: 75
8034 11:16:49.342218
8035 11:16:49.342676 Set Vref, RX VrefLevel [Byte0]: 76
8036 11:16:49.345459 [Byte1]: 76
8037 11:16:49.349350
8038 11:16:49.349805 Set Vref, RX VrefLevel [Byte0]: 77
8039 11:16:49.353251 [Byte1]: 77
8040 11:16:49.357775
8041 11:16:49.358331 Set Vref, RX VrefLevel [Byte0]: 78
8042 11:16:49.360451 [Byte1]: 78
8043 11:16:49.365149
8044 11:16:49.365705 Final RX Vref Byte 0 = 65 to rank0
8045 11:16:49.368040 Final RX Vref Byte 1 = 58 to rank0
8046 11:16:49.371283 Final RX Vref Byte 0 = 65 to rank1
8047 11:16:49.374670 Final RX Vref Byte 1 = 58 to rank1==
8048 11:16:49.377735 Dram Type= 6, Freq= 0, CH_0, rank 0
8049 11:16:49.384637 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8050 11:16:49.385113 ==
8051 11:16:49.385478 DQS Delay:
8052 11:16:49.388218 DQS0 = 0, DQS1 = 0
8053 11:16:49.388716 DQM Delay:
8054 11:16:49.389080 DQM0 = 133, DQM1 = 123
8055 11:16:49.391332 DQ Delay:
8056 11:16:49.394641 DQ0 =130, DQ1 =136, DQ2 =132, DQ3 =132
8057 11:16:49.398176 DQ4 =134, DQ5 =122, DQ6 =140, DQ7 =142
8058 11:16:49.401491 DQ8 =114, DQ9 =112, DQ10 =122, DQ11 =118
8059 11:16:49.404395 DQ12 =128, DQ13 =126, DQ14 =134, DQ15 =130
8060 11:16:49.404913
8061 11:16:49.405281
8062 11:16:49.405617
8063 11:16:49.407537 [DramC_TX_OE_Calibration] TA2
8064 11:16:49.411113 Original DQ_B0 (3 6) =30, OEN = 27
8065 11:16:49.414816 Original DQ_B1 (3 6) =30, OEN = 27
8066 11:16:49.418203 24, 0x0, End_B0=24 End_B1=24
8067 11:16:49.420831 25, 0x0, End_B0=25 End_B1=25
8068 11:16:49.421300 26, 0x0, End_B0=26 End_B1=26
8069 11:16:49.424136 27, 0x0, End_B0=27 End_B1=27
8070 11:16:49.427435 28, 0x0, End_B0=28 End_B1=28
8071 11:16:49.430823 29, 0x0, End_B0=29 End_B1=29
8072 11:16:49.431398 30, 0x0, End_B0=30 End_B1=30
8073 11:16:49.434474 31, 0x4141, End_B0=30 End_B1=30
8074 11:16:49.437403 Byte0 end_step=30 best_step=27
8075 11:16:49.440556 Byte1 end_step=30 best_step=27
8076 11:16:49.444397 Byte0 TX OE(2T, 0.5T) = (3, 3)
8077 11:16:49.447225 Byte1 TX OE(2T, 0.5T) = (3, 3)
8078 11:16:49.447808
8079 11:16:49.448176
8080 11:16:49.454075 [DQSOSCAuto] RK0, (LSB)MR18= 0x2011, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 393 ps
8081 11:16:49.457335 CH0 RK0: MR19=303, MR18=2011
8082 11:16:49.463898 CH0_RK0: MR19=0x303, MR18=0x2011, DQSOSC=393, MR23=63, INC=23, DEC=15
8083 11:16:49.464476
8084 11:16:49.467329 ----->DramcWriteLeveling(PI) begin...
8085 11:16:49.467822 ==
8086 11:16:49.470103 Dram Type= 6, Freq= 0, CH_0, rank 1
8087 11:16:49.473777 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8088 11:16:49.474199 ==
8089 11:16:49.476467 Write leveling (Byte 0): 37 => 37
8090 11:16:49.479932 Write leveling (Byte 1): 28 => 28
8091 11:16:49.483069 DramcWriteLeveling(PI) end<-----
8092 11:16:49.483488
8093 11:16:49.483819 ==
8094 11:16:49.486828 Dram Type= 6, Freq= 0, CH_0, rank 1
8095 11:16:49.492975 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8096 11:16:49.493411 ==
8097 11:16:49.493772 [Gating] SW mode calibration
8098 11:16:49.502790 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8099 11:16:49.506345 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8100 11:16:49.512958 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8101 11:16:49.515868 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8102 11:16:49.519662 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8103 11:16:49.525972 1 4 12 | B1->B0 | 2323 2625 | 0 1 | (0 0) (1 1)
8104 11:16:49.529391 1 4 16 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
8105 11:16:49.532503 1 4 20 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
8106 11:16:49.539582 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8107 11:16:49.542573 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8108 11:16:49.545590 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8109 11:16:49.552956 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8110 11:16:49.556086 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8111 11:16:49.559203 1 5 12 | B1->B0 | 3434 3333 | 1 0 | (1 0) (1 1)
8112 11:16:49.565733 1 5 16 | B1->B0 | 3434 2828 | 1 0 | (1 0) (0 0)
8113 11:16:49.568989 1 5 20 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (0 0)
8114 11:16:49.571975 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8115 11:16:49.578884 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8116 11:16:49.581753 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8117 11:16:49.585519 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8118 11:16:49.592241 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8119 11:16:49.595292 1 6 12 | B1->B0 | 2323 2e2e | 0 1 | (0 0) (0 0)
8120 11:16:49.598752 1 6 16 | B1->B0 | 2929 4242 | 0 0 | (0 0) (0 0)
8121 11:16:49.605346 1 6 20 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
8122 11:16:49.608701 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8123 11:16:49.612163 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8124 11:16:49.618699 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8125 11:16:49.621477 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8126 11:16:49.625313 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8127 11:16:49.631501 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8128 11:16:49.635178 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8129 11:16:49.638171 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8130 11:16:49.644488 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8131 11:16:49.648378 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8132 11:16:49.651417 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8133 11:16:49.658152 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8134 11:16:49.661153 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8135 11:16:49.664895 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8136 11:16:49.671733 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8137 11:16:49.674482 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8138 11:16:49.678119 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8139 11:16:49.683832 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8140 11:16:49.687615 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8141 11:16:49.691276 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8142 11:16:49.697229 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8143 11:16:49.700502 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8144 11:16:49.704005 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8145 11:16:49.707727 Total UI for P1: 0, mck2ui 16
8146 11:16:49.710557 best dqsien dly found for B0: ( 1, 9, 10)
8147 11:16:49.714131 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8148 11:16:49.720858 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8149 11:16:49.723570 Total UI for P1: 0, mck2ui 16
8150 11:16:49.726863 best dqsien dly found for B1: ( 1, 9, 18)
8151 11:16:49.730215 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8152 11:16:49.734026 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8153 11:16:49.734454
8154 11:16:49.736826 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8155 11:16:49.740448 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8156 11:16:49.744104 [Gating] SW calibration Done
8157 11:16:49.744663 ==
8158 11:16:49.747320 Dram Type= 6, Freq= 0, CH_0, rank 1
8159 11:16:49.750315 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8160 11:16:49.754019 ==
8161 11:16:49.754589 RX Vref Scan: 0
8162 11:16:49.754963
8163 11:16:49.757124 RX Vref 0 -> 0, step: 1
8164 11:16:49.757679
8165 11:16:49.758046 RX Delay 0 -> 252, step: 8
8166 11:16:49.763588 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8167 11:16:49.767025 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8168 11:16:49.769688 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8169 11:16:49.773485 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8170 11:16:49.779690 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8171 11:16:49.783200 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8172 11:16:49.786509 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8173 11:16:49.789502 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8174 11:16:49.793258 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8175 11:16:49.800413 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8176 11:16:49.802816 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8177 11:16:49.806386 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8178 11:16:49.809730 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8179 11:16:49.813157 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8180 11:16:49.819587 iDelay=200, Bit 14, Center 143 (88 ~ 199) 112
8181 11:16:49.823040 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8182 11:16:49.823512 ==
8183 11:16:49.826463 Dram Type= 6, Freq= 0, CH_0, rank 1
8184 11:16:49.829357 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8185 11:16:49.829829 ==
8186 11:16:49.833482 DQS Delay:
8187 11:16:49.834056 DQS0 = 0, DQS1 = 0
8188 11:16:49.834425 DQM Delay:
8189 11:16:49.836438 DQM0 = 133, DQM1 = 130
8190 11:16:49.836936 DQ Delay:
8191 11:16:49.839578 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =127
8192 11:16:49.842886 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8193 11:16:49.846012 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =127
8194 11:16:49.852837 DQ12 =135, DQ13 =135, DQ14 =143, DQ15 =135
8195 11:16:49.853396
8196 11:16:49.853766
8197 11:16:49.854108 ==
8198 11:16:49.856093 Dram Type= 6, Freq= 0, CH_0, rank 1
8199 11:16:49.859421 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8200 11:16:49.859983 ==
8201 11:16:49.860355
8202 11:16:49.860762
8203 11:16:49.862529 TX Vref Scan disable
8204 11:16:49.862994 == TX Byte 0 ==
8205 11:16:49.869920 Update DQ dly =993 (3 ,6, 33) DQ OEN =(3 ,3)
8206 11:16:49.872380 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8207 11:16:49.876022 == TX Byte 1 ==
8208 11:16:49.879132 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8209 11:16:49.882076 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8210 11:16:49.882544 ==
8211 11:16:49.886034 Dram Type= 6, Freq= 0, CH_0, rank 1
8212 11:16:49.889107 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8213 11:16:49.891806 ==
8214 11:16:49.904040
8215 11:16:49.907757 TX Vref early break, caculate TX vref
8216 11:16:49.911002 TX Vref=16, minBit 1, minWin=22, winSum=380
8217 11:16:49.913808 TX Vref=18, minBit 0, minWin=23, winSum=386
8218 11:16:49.917619 TX Vref=20, minBit 0, minWin=23, winSum=391
8219 11:16:49.920842 TX Vref=22, minBit 1, minWin=24, winSum=403
8220 11:16:49.924017 TX Vref=24, minBit 1, minWin=24, winSum=408
8221 11:16:49.930574 TX Vref=26, minBit 0, minWin=25, winSum=414
8222 11:16:49.933863 TX Vref=28, minBit 1, minWin=24, winSum=415
8223 11:16:49.936885 TX Vref=30, minBit 0, minWin=24, winSum=403
8224 11:16:49.940237 TX Vref=32, minBit 0, minWin=24, winSum=397
8225 11:16:49.944181 TX Vref=34, minBit 2, minWin=23, winSum=392
8226 11:16:49.950684 [TxChooseVref] Worse bit 0, Min win 25, Win sum 414, Final Vref 26
8227 11:16:49.951243
8228 11:16:49.953819 Final TX Range 0 Vref 26
8229 11:16:49.954370
8230 11:16:49.954741 ==
8231 11:16:49.957177 Dram Type= 6, Freq= 0, CH_0, rank 1
8232 11:16:49.961115 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8233 11:16:49.961673 ==
8234 11:16:49.962088
8235 11:16:49.962437
8236 11:16:49.963164 TX Vref Scan disable
8237 11:16:49.970403 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8238 11:16:49.970964 == TX Byte 0 ==
8239 11:16:49.973029 u2DelayCellOfst[0]=11 cells (3 PI)
8240 11:16:49.977050 u2DelayCellOfst[1]=14 cells (4 PI)
8241 11:16:49.980274 u2DelayCellOfst[2]=11 cells (3 PI)
8242 11:16:49.982870 u2DelayCellOfst[3]=11 cells (3 PI)
8243 11:16:49.986528 u2DelayCellOfst[4]=7 cells (2 PI)
8244 11:16:49.989960 u2DelayCellOfst[5]=0 cells (0 PI)
8245 11:16:49.993543 u2DelayCellOfst[6]=14 cells (4 PI)
8246 11:16:49.996028 u2DelayCellOfst[7]=14 cells (4 PI)
8247 11:16:49.999533 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8248 11:16:50.002876 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8249 11:16:50.006145 == TX Byte 1 ==
8250 11:16:50.009682 u2DelayCellOfst[8]=0 cells (0 PI)
8251 11:16:50.012826 u2DelayCellOfst[9]=3 cells (1 PI)
8252 11:16:50.016280 u2DelayCellOfst[10]=7 cells (2 PI)
8253 11:16:50.019481 u2DelayCellOfst[11]=3 cells (1 PI)
8254 11:16:50.020040 u2DelayCellOfst[12]=11 cells (3 PI)
8255 11:16:50.022863 u2DelayCellOfst[13]=11 cells (3 PI)
8256 11:16:50.025939 u2DelayCellOfst[14]=18 cells (5 PI)
8257 11:16:50.029446 u2DelayCellOfst[15]=11 cells (3 PI)
8258 11:16:50.036322 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8259 11:16:50.039216 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8260 11:16:50.039776 DramC Write-DBI on
8261 11:16:50.042932 ==
8262 11:16:50.045672 Dram Type= 6, Freq= 0, CH_0, rank 1
8263 11:16:50.049295 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8264 11:16:50.049853 ==
8265 11:16:50.050224
8266 11:16:50.050564
8267 11:16:50.052722 TX Vref Scan disable
8268 11:16:50.053294 == TX Byte 0 ==
8269 11:16:50.059334 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8270 11:16:50.059892 == TX Byte 1 ==
8271 11:16:50.062325 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8272 11:16:50.065290 DramC Write-DBI off
8273 11:16:50.065756
8274 11:16:50.066121 [DATLAT]
8275 11:16:50.069230 Freq=1600, CH0 RK1
8276 11:16:50.069794
8277 11:16:50.070160 DATLAT Default: 0xf
8278 11:16:50.071961 0, 0xFFFF, sum = 0
8279 11:16:50.072434 1, 0xFFFF, sum = 0
8280 11:16:50.075253 2, 0xFFFF, sum = 0
8281 11:16:50.078427 3, 0xFFFF, sum = 0
8282 11:16:50.078929 4, 0xFFFF, sum = 0
8283 11:16:50.082212 5, 0xFFFF, sum = 0
8284 11:16:50.082686 6, 0xFFFF, sum = 0
8285 11:16:50.085210 7, 0xFFFF, sum = 0
8286 11:16:50.085733 8, 0xFFFF, sum = 0
8287 11:16:50.088958 9, 0xFFFF, sum = 0
8288 11:16:50.089524 10, 0xFFFF, sum = 0
8289 11:16:50.091973 11, 0xFFFF, sum = 0
8290 11:16:50.092564 12, 0xFFFF, sum = 0
8291 11:16:50.094833 13, 0xFFFF, sum = 0
8292 11:16:50.095307 14, 0x0, sum = 1
8293 11:16:50.098261 15, 0x0, sum = 2
8294 11:16:50.098736 16, 0x0, sum = 3
8295 11:16:50.101738 17, 0x0, sum = 4
8296 11:16:50.102213 best_step = 15
8297 11:16:50.102595
8298 11:16:50.102988 ==
8299 11:16:50.105007 Dram Type= 6, Freq= 0, CH_0, rank 1
8300 11:16:50.112215 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8301 11:16:50.112678 ==
8302 11:16:50.113020 RX Vref Scan: 0
8303 11:16:50.113333
8304 11:16:50.115226 RX Vref 0 -> 0, step: 1
8305 11:16:50.115744
8306 11:16:50.118589 RX Delay 11 -> 252, step: 4
8307 11:16:50.121278 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8308 11:16:50.124636 iDelay=195, Bit 1, Center 136 (83 ~ 190) 108
8309 11:16:50.131158 iDelay=195, Bit 2, Center 126 (75 ~ 178) 104
8310 11:16:50.134304 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8311 11:16:50.137987 iDelay=195, Bit 4, Center 130 (79 ~ 182) 104
8312 11:16:50.140689 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8313 11:16:50.144807 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
8314 11:16:50.151505 iDelay=195, Bit 7, Center 138 (87 ~ 190) 104
8315 11:16:50.154293 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
8316 11:16:50.158435 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8317 11:16:50.160692 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8318 11:16:50.164198 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8319 11:16:50.170930 iDelay=195, Bit 12, Center 130 (79 ~ 182) 104
8320 11:16:50.174026 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8321 11:16:50.177243 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8322 11:16:50.180990 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8323 11:16:50.181454 ==
8324 11:16:50.183685 Dram Type= 6, Freq= 0, CH_0, rank 1
8325 11:16:50.190395 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8326 11:16:50.190947 ==
8327 11:16:50.191319 DQS Delay:
8328 11:16:50.193973 DQS0 = 0, DQS1 = 0
8329 11:16:50.194434 DQM Delay:
8330 11:16:50.196680 DQM0 = 130, DQM1 = 125
8331 11:16:50.197112 DQ Delay:
8332 11:16:50.200086 DQ0 =128, DQ1 =136, DQ2 =126, DQ3 =128
8333 11:16:50.203810 DQ4 =130, DQ5 =120, DQ6 =140, DQ7 =138
8334 11:16:50.206943 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8335 11:16:50.210259 DQ12 =130, DQ13 =132, DQ14 =136, DQ15 =132
8336 11:16:50.210677
8337 11:16:50.211007
8338 11:16:50.211313
8339 11:16:50.213158 [DramC_TX_OE_Calibration] TA2
8340 11:16:50.216876 Original DQ_B0 (3 6) =30, OEN = 27
8341 11:16:50.220065 Original DQ_B1 (3 6) =30, OEN = 27
8342 11:16:50.223290 24, 0x0, End_B0=24 End_B1=24
8343 11:16:50.227161 25, 0x0, End_B0=25 End_B1=25
8344 11:16:50.227682 26, 0x0, End_B0=26 End_B1=26
8345 11:16:50.229727 27, 0x0, End_B0=27 End_B1=27
8346 11:16:50.233164 28, 0x0, End_B0=28 End_B1=28
8347 11:16:50.236506 29, 0x0, End_B0=29 End_B1=29
8348 11:16:50.239905 30, 0x0, End_B0=30 End_B1=30
8349 11:16:50.240443 31, 0x4545, End_B0=30 End_B1=30
8350 11:16:50.243142 Byte0 end_step=30 best_step=27
8351 11:16:50.245991 Byte1 end_step=30 best_step=27
8352 11:16:50.249679 Byte0 TX OE(2T, 0.5T) = (3, 3)
8353 11:16:50.252958 Byte1 TX OE(2T, 0.5T) = (3, 3)
8354 11:16:50.253512
8355 11:16:50.253878
8356 11:16:50.259376 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f02, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 394 ps
8357 11:16:50.262882 CH0 RK1: MR19=303, MR18=1F02
8358 11:16:50.269240 CH0_RK1: MR19=0x303, MR18=0x1F02, DQSOSC=394, MR23=63, INC=23, DEC=15
8359 11:16:50.272504 [RxdqsGatingPostProcess] freq 1600
8360 11:16:50.279406 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8361 11:16:50.282102 best DQS0 dly(2T, 0.5T) = (1, 1)
8362 11:16:50.282515 best DQS1 dly(2T, 0.5T) = (1, 1)
8363 11:16:50.285855 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8364 11:16:50.288883 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8365 11:16:50.291998 best DQS0 dly(2T, 0.5T) = (1, 1)
8366 11:16:50.295463 best DQS1 dly(2T, 0.5T) = (1, 1)
8367 11:16:50.298854 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8368 11:16:50.302334 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8369 11:16:50.305627 Pre-setting of DQS Precalculation
8370 11:16:50.308803 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8371 11:16:50.312378 ==
8372 11:16:50.315502 Dram Type= 6, Freq= 0, CH_1, rank 0
8373 11:16:50.318906 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8374 11:16:50.319415 ==
8375 11:16:50.325337 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8376 11:16:50.328650 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8377 11:16:50.331981 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8378 11:16:50.338433 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8379 11:16:50.347536 [CA 0] Center 41 (12~71) winsize 60
8380 11:16:50.350164 [CA 1] Center 41 (12~71) winsize 60
8381 11:16:50.354009 [CA 2] Center 37 (8~66) winsize 59
8382 11:16:50.357173 [CA 3] Center 36 (7~65) winsize 59
8383 11:16:50.360330 [CA 4] Center 37 (7~67) winsize 61
8384 11:16:50.363314 [CA 5] Center 36 (7~65) winsize 59
8385 11:16:50.363858
8386 11:16:50.366586 [CmdBusTrainingLP45] Vref(ca) range 0: 30
8387 11:16:50.367045
8388 11:16:50.370607 [CATrainingPosCal] consider 1 rank data
8389 11:16:50.374010 u2DelayCellTimex100 = 262/100 ps
8390 11:16:50.380006 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8391 11:16:50.383264 CA1 delay=41 (12~71),Diff = 5 PI (18 cell)
8392 11:16:50.386320 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8393 11:16:50.390010 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8394 11:16:50.393080 CA4 delay=37 (7~67),Diff = 1 PI (3 cell)
8395 11:16:50.396457 CA5 delay=36 (7~65),Diff = 0 PI (0 cell)
8396 11:16:50.397056
8397 11:16:50.399570 CA PerBit enable=1, Macro0, CA PI delay=36
8398 11:16:50.400033
8399 11:16:50.403142 [CBTSetCACLKResult] CA Dly = 36
8400 11:16:50.406150 CS Dly: 8 (0~39)
8401 11:16:50.409380 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8402 11:16:50.413259 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8403 11:16:50.413802 ==
8404 11:16:50.416641 Dram Type= 6, Freq= 0, CH_1, rank 1
8405 11:16:50.419780 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8406 11:16:50.422852 ==
8407 11:16:50.426516 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8408 11:16:50.429966 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8409 11:16:50.436668 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8410 11:16:50.443040 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8411 11:16:50.450349 [CA 0] Center 42 (13~71) winsize 59
8412 11:16:50.453108 [CA 1] Center 42 (12~72) winsize 61
8413 11:16:50.456676 [CA 2] Center 37 (8~67) winsize 60
8414 11:16:50.460152 [CA 3] Center 37 (7~67) winsize 61
8415 11:16:50.463552 [CA 4] Center 38 (9~67) winsize 59
8416 11:16:50.466483 [CA 5] Center 37 (8~67) winsize 60
8417 11:16:50.467040
8418 11:16:50.469845 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8419 11:16:50.470306
8420 11:16:50.473477 [CATrainingPosCal] consider 2 rank data
8421 11:16:50.476844 u2DelayCellTimex100 = 262/100 ps
8422 11:16:50.483145 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8423 11:16:50.486074 CA1 delay=41 (12~71),Diff = 5 PI (18 cell)
8424 11:16:50.489411 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8425 11:16:50.493038 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8426 11:16:50.496155 CA4 delay=38 (9~67),Diff = 2 PI (7 cell)
8427 11:16:50.499342 CA5 delay=36 (8~65),Diff = 0 PI (0 cell)
8428 11:16:50.499806
8429 11:16:50.502975 CA PerBit enable=1, Macro0, CA PI delay=36
8430 11:16:50.503564
8431 11:16:50.506028 [CBTSetCACLKResult] CA Dly = 36
8432 11:16:50.509062 CS Dly: 10 (0~43)
8433 11:16:50.512434 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8434 11:16:50.516429 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8435 11:16:50.517023
8436 11:16:50.519309 ----->DramcWriteLeveling(PI) begin...
8437 11:16:50.519876 ==
8438 11:16:50.522648 Dram Type= 6, Freq= 0, CH_1, rank 0
8439 11:16:50.529216 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8440 11:16:50.529860 ==
8441 11:16:50.532932 Write leveling (Byte 0): 23 => 23
8442 11:16:50.535748 Write leveling (Byte 1): 26 => 26
8443 11:16:50.536207 DramcWriteLeveling(PI) end<-----
8444 11:16:50.536600
8445 11:16:50.538803 ==
8446 11:16:50.542098 Dram Type= 6, Freq= 0, CH_1, rank 0
8447 11:16:50.545721 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8448 11:16:50.546142 ==
8449 11:16:50.549355 [Gating] SW mode calibration
8450 11:16:50.555693 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8451 11:16:50.559009 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8452 11:16:50.565699 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8453 11:16:50.568832 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8454 11:16:50.572178 1 4 8 | B1->B0 | 2322 2626 | 1 0 | (0 0) (0 0)
8455 11:16:50.578876 1 4 12 | B1->B0 | 3333 3434 | 0 0 | (0 0) (0 0)
8456 11:16:50.582356 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8457 11:16:50.585246 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8458 11:16:50.592233 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8459 11:16:50.595440 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8460 11:16:50.598486 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8461 11:16:50.605379 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8462 11:16:50.608116 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8463 11:16:50.612030 1 5 12 | B1->B0 | 2d2d 2525 | 0 0 | (1 0) (1 0)
8464 11:16:50.618800 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8465 11:16:50.622198 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8466 11:16:50.625191 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8467 11:16:50.631811 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8468 11:16:50.634978 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8469 11:16:50.638000 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8470 11:16:50.644684 1 6 8 | B1->B0 | 2424 2828 | 0 0 | (0 0) (0 0)
8471 11:16:50.648009 1 6 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8472 11:16:50.651740 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8473 11:16:50.658701 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8474 11:16:50.661031 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8475 11:16:50.664846 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8476 11:16:50.670905 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8477 11:16:50.674274 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8478 11:16:50.678004 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8479 11:16:50.684413 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8480 11:16:50.687871 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8481 11:16:50.691053 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8482 11:16:50.697553 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8483 11:16:50.701254 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8484 11:16:50.704385 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8485 11:16:50.710713 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8486 11:16:50.713993 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8487 11:16:50.718008 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8488 11:16:50.723948 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8489 11:16:50.727517 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8490 11:16:50.730944 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8491 11:16:50.737495 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8492 11:16:50.741089 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8493 11:16:50.743942 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8494 11:16:50.751152 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8495 11:16:50.753882 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8496 11:16:50.757155 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8497 11:16:50.760583 Total UI for P1: 0, mck2ui 16
8498 11:16:50.763908 best dqsien dly found for B0: ( 1, 9, 10)
8499 11:16:50.766818 Total UI for P1: 0, mck2ui 16
8500 11:16:50.770456 best dqsien dly found for B1: ( 1, 9, 12)
8501 11:16:50.773977 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8502 11:16:50.776985 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8503 11:16:50.777533
8504 11:16:50.783767 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8505 11:16:50.786700 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8506 11:16:50.789836 [Gating] SW calibration Done
8507 11:16:50.790296 ==
8508 11:16:50.793213 Dram Type= 6, Freq= 0, CH_1, rank 0
8509 11:16:50.797066 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8510 11:16:50.797634 ==
8511 11:16:50.798002 RX Vref Scan: 0
8512 11:16:50.798344
8513 11:16:50.799879 RX Vref 0 -> 0, step: 1
8514 11:16:50.800431
8515 11:16:50.803512 RX Delay 0 -> 252, step: 8
8516 11:16:50.807072 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8517 11:16:50.810280 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8518 11:16:50.813459 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8519 11:16:50.820141 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8520 11:16:50.823235 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8521 11:16:50.826366 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8522 11:16:50.829766 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8523 11:16:50.836306 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8524 11:16:50.839575 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8525 11:16:50.843343 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8526 11:16:50.846967 iDelay=208, Bit 10, Center 127 (72 ~ 183) 112
8527 11:16:50.849810 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8528 11:16:50.856548 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8529 11:16:50.860096 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8530 11:16:50.863224 iDelay=208, Bit 14, Center 135 (80 ~ 191) 112
8531 11:16:50.866029 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8532 11:16:50.866518 ==
8533 11:16:50.869673 Dram Type= 6, Freq= 0, CH_1, rank 0
8534 11:16:50.875909 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8535 11:16:50.876468 ==
8536 11:16:50.876897 DQS Delay:
8537 11:16:50.879857 DQS0 = 0, DQS1 = 0
8538 11:16:50.880417 DQM Delay:
8539 11:16:50.880844 DQM0 = 138, DQM1 = 128
8540 11:16:50.882972 DQ Delay:
8541 11:16:50.886469 DQ0 =143, DQ1 =131, DQ2 =127, DQ3 =135
8542 11:16:50.889767 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8543 11:16:50.892624 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =123
8544 11:16:50.896068 DQ12 =135, DQ13 =139, DQ14 =135, DQ15 =135
8545 11:16:50.896565
8546 11:16:50.896938
8547 11:16:50.897294 ==
8548 11:16:50.899218 Dram Type= 6, Freq= 0, CH_1, rank 0
8549 11:16:50.905572 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8550 11:16:50.906145 ==
8551 11:16:50.906518
8552 11:16:50.906857
8553 11:16:50.907184 TX Vref Scan disable
8554 11:16:50.908876 == TX Byte 0 ==
8555 11:16:50.912069 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8556 11:16:50.915827 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8557 11:16:50.918719 == TX Byte 1 ==
8558 11:16:50.922058 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8559 11:16:50.929038 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8560 11:16:50.929602 ==
8561 11:16:50.932801 Dram Type= 6, Freq= 0, CH_1, rank 0
8562 11:16:50.935629 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8563 11:16:50.936096 ==
8564 11:16:50.947900
8565 11:16:50.951200 TX Vref early break, caculate TX vref
8566 11:16:50.954729 TX Vref=16, minBit 0, minWin=21, winSum=372
8567 11:16:50.957905 TX Vref=18, minBit 0, minWin=22, winSum=382
8568 11:16:50.961240 TX Vref=20, minBit 0, minWin=22, winSum=391
8569 11:16:50.964432 TX Vref=22, minBit 5, minWin=23, winSum=402
8570 11:16:50.967713 TX Vref=24, minBit 6, minWin=24, winSum=414
8571 11:16:50.973928 TX Vref=26, minBit 0, minWin=24, winSum=421
8572 11:16:50.977199 TX Vref=28, minBit 0, minWin=24, winSum=419
8573 11:16:50.980476 TX Vref=30, minBit 0, minWin=23, winSum=410
8574 11:16:50.983735 TX Vref=32, minBit 0, minWin=23, winSum=403
8575 11:16:50.987709 TX Vref=34, minBit 0, minWin=23, winSum=394
8576 11:16:50.993825 [TxChooseVref] Worse bit 0, Min win 24, Win sum 421, Final Vref 26
8577 11:16:50.994392
8578 11:16:50.997167 Final TX Range 0 Vref 26
8579 11:16:50.997792
8580 11:16:50.998194 ==
8581 11:16:51.000148 Dram Type= 6, Freq= 0, CH_1, rank 0
8582 11:16:51.003674 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8583 11:16:51.004413 ==
8584 11:16:51.004858
8585 11:16:51.006784
8586 11:16:51.007347 TX Vref Scan disable
8587 11:16:51.013691 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8588 11:16:51.014256 == TX Byte 0 ==
8589 11:16:51.016997 u2DelayCellOfst[0]=14 cells (4 PI)
8590 11:16:51.019894 u2DelayCellOfst[1]=11 cells (3 PI)
8591 11:16:51.023220 u2DelayCellOfst[2]=0 cells (0 PI)
8592 11:16:51.026717 u2DelayCellOfst[3]=3 cells (1 PI)
8593 11:16:51.030372 u2DelayCellOfst[4]=7 cells (2 PI)
8594 11:16:51.033214 u2DelayCellOfst[5]=18 cells (5 PI)
8595 11:16:51.037304 u2DelayCellOfst[6]=18 cells (5 PI)
8596 11:16:51.039558 u2DelayCellOfst[7]=3 cells (1 PI)
8597 11:16:51.043168 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8598 11:16:51.046162 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8599 11:16:51.050030 == TX Byte 1 ==
8600 11:16:51.052945 u2DelayCellOfst[8]=0 cells (0 PI)
8601 11:16:51.056800 u2DelayCellOfst[9]=0 cells (0 PI)
8602 11:16:51.059961 u2DelayCellOfst[10]=7 cells (2 PI)
8603 11:16:51.060558 u2DelayCellOfst[11]=3 cells (1 PI)
8604 11:16:51.062815 u2DelayCellOfst[12]=11 cells (3 PI)
8605 11:16:51.066196 u2DelayCellOfst[13]=11 cells (3 PI)
8606 11:16:51.069324 u2DelayCellOfst[14]=14 cells (4 PI)
8607 11:16:51.072633 u2DelayCellOfst[15]=11 cells (3 PI)
8608 11:16:51.079197 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8609 11:16:51.082845 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8610 11:16:51.083410 DramC Write-DBI on
8611 11:16:51.085761 ==
8612 11:16:51.089122 Dram Type= 6, Freq= 0, CH_1, rank 0
8613 11:16:51.092677 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8614 11:16:51.093147 ==
8615 11:16:51.093516
8616 11:16:51.093855
8617 11:16:51.095800 TX Vref Scan disable
8618 11:16:51.096356 == TX Byte 0 ==
8619 11:16:51.101965 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8620 11:16:51.102449 == TX Byte 1 ==
8621 11:16:51.105431 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8622 11:16:51.109312 DramC Write-DBI off
8623 11:16:51.110102
8624 11:16:51.110497 [DATLAT]
8625 11:16:51.112189 Freq=1600, CH1 RK0
8626 11:16:51.112907
8627 11:16:51.113334 DATLAT Default: 0xf
8628 11:16:51.115623 0, 0xFFFF, sum = 0
8629 11:16:51.116095 1, 0xFFFF, sum = 0
8630 11:16:51.119318 2, 0xFFFF, sum = 0
8631 11:16:51.119885 3, 0xFFFF, sum = 0
8632 11:16:51.122600 4, 0xFFFF, sum = 0
8633 11:16:51.123165 5, 0xFFFF, sum = 0
8634 11:16:51.125187 6, 0xFFFF, sum = 0
8635 11:16:51.128741 7, 0xFFFF, sum = 0
8636 11:16:51.129306 8, 0xFFFF, sum = 0
8637 11:16:51.132353 9, 0xFFFF, sum = 0
8638 11:16:51.132959 10, 0xFFFF, sum = 0
8639 11:16:51.135540 11, 0xFFFF, sum = 0
8640 11:16:51.136105 12, 0xFFFF, sum = 0
8641 11:16:51.138795 13, 0xFFFF, sum = 0
8642 11:16:51.139272 14, 0x0, sum = 1
8643 11:16:51.142169 15, 0x0, sum = 2
8644 11:16:51.142642 16, 0x0, sum = 3
8645 11:16:51.145202 17, 0x0, sum = 4
8646 11:16:51.145676 best_step = 15
8647 11:16:51.146043
8648 11:16:51.146380 ==
8649 11:16:51.148406 Dram Type= 6, Freq= 0, CH_1, rank 0
8650 11:16:51.151692 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8651 11:16:51.155226 ==
8652 11:16:51.155695 RX Vref Scan: 1
8653 11:16:51.156064
8654 11:16:51.158906 Set Vref Range= 24 -> 127
8655 11:16:51.159466
8656 11:16:51.161865 RX Vref 24 -> 127, step: 1
8657 11:16:51.162422
8658 11:16:51.162787 RX Delay 11 -> 252, step: 4
8659 11:16:51.163130
8660 11:16:51.165129 Set Vref, RX VrefLevel [Byte0]: 24
8661 11:16:51.168625 [Byte1]: 24
8662 11:16:51.172830
8663 11:16:51.173299 Set Vref, RX VrefLevel [Byte0]: 25
8664 11:16:51.176204 [Byte1]: 25
8665 11:16:51.179653
8666 11:16:51.180209 Set Vref, RX VrefLevel [Byte0]: 26
8667 11:16:51.183588 [Byte1]: 26
8668 11:16:51.187011
8669 11:16:51.187477 Set Vref, RX VrefLevel [Byte0]: 27
8670 11:16:51.190714 [Byte1]: 27
8671 11:16:51.195045
8672 11:16:51.195605 Set Vref, RX VrefLevel [Byte0]: 28
8673 11:16:51.198585 [Byte1]: 28
8674 11:16:51.202675
8675 11:16:51.203250 Set Vref, RX VrefLevel [Byte0]: 29
8676 11:16:51.206302 [Byte1]: 29
8677 11:16:51.210203
8678 11:16:51.210903 Set Vref, RX VrefLevel [Byte0]: 30
8679 11:16:51.213726 [Byte1]: 30
8680 11:16:51.217941
8681 11:16:51.218405 Set Vref, RX VrefLevel [Byte0]: 31
8682 11:16:51.221320 [Byte1]: 31
8683 11:16:51.225334
8684 11:16:51.225803 Set Vref, RX VrefLevel [Byte0]: 32
8685 11:16:51.228992 [Byte1]: 32
8686 11:16:51.233069
8687 11:16:51.233628 Set Vref, RX VrefLevel [Byte0]: 33
8688 11:16:51.236567 [Byte1]: 33
8689 11:16:51.240675
8690 11:16:51.241222 Set Vref, RX VrefLevel [Byte0]: 34
8691 11:16:51.243940 [Byte1]: 34
8692 11:16:51.248441
8693 11:16:51.249025 Set Vref, RX VrefLevel [Byte0]: 35
8694 11:16:51.251645 [Byte1]: 35
8695 11:16:51.255676
8696 11:16:51.256241 Set Vref, RX VrefLevel [Byte0]: 36
8697 11:16:51.259298 [Byte1]: 36
8698 11:16:51.263635
8699 11:16:51.264103 Set Vref, RX VrefLevel [Byte0]: 37
8700 11:16:51.266854 [Byte1]: 37
8701 11:16:51.270777
8702 11:16:51.271245 Set Vref, RX VrefLevel [Byte0]: 38
8703 11:16:51.275185 [Byte1]: 38
8704 11:16:51.278930
8705 11:16:51.279486 Set Vref, RX VrefLevel [Byte0]: 39
8706 11:16:51.281845 [Byte1]: 39
8707 11:16:51.286304
8708 11:16:51.286860 Set Vref, RX VrefLevel [Byte0]: 40
8709 11:16:51.289655 [Byte1]: 40
8710 11:16:51.294091
8711 11:16:51.294662 Set Vref, RX VrefLevel [Byte0]: 41
8712 11:16:51.297069 [Byte1]: 41
8713 11:16:51.301889
8714 11:16:51.302455 Set Vref, RX VrefLevel [Byte0]: 42
8715 11:16:51.304625 [Byte1]: 42
8716 11:16:51.309107
8717 11:16:51.309681 Set Vref, RX VrefLevel [Byte0]: 43
8718 11:16:51.312132 [Byte1]: 43
8719 11:16:51.317178
8720 11:16:51.317783 Set Vref, RX VrefLevel [Byte0]: 44
8721 11:16:51.320097 [Byte1]: 44
8722 11:16:51.324782
8723 11:16:51.325332 Set Vref, RX VrefLevel [Byte0]: 45
8724 11:16:51.327728 [Byte1]: 45
8725 11:16:51.332113
8726 11:16:51.332705 Set Vref, RX VrefLevel [Byte0]: 46
8727 11:16:51.335271 [Byte1]: 46
8728 11:16:51.339446
8729 11:16:51.339905 Set Vref, RX VrefLevel [Byte0]: 47
8730 11:16:51.343029 [Byte1]: 47
8731 11:16:51.348077
8732 11:16:51.348677 Set Vref, RX VrefLevel [Byte0]: 48
8733 11:16:51.350766 [Byte1]: 48
8734 11:16:51.355418
8735 11:16:51.355882 Set Vref, RX VrefLevel [Byte0]: 49
8736 11:16:51.357949 [Byte1]: 49
8737 11:16:51.362442
8738 11:16:51.362998 Set Vref, RX VrefLevel [Byte0]: 50
8739 11:16:51.365394 [Byte1]: 50
8740 11:16:51.370011
8741 11:16:51.370471 Set Vref, RX VrefLevel [Byte0]: 51
8742 11:16:51.373209 [Byte1]: 51
8743 11:16:51.378001
8744 11:16:51.378557 Set Vref, RX VrefLevel [Byte0]: 52
8745 11:16:51.380809 [Byte1]: 52
8746 11:16:51.385551
8747 11:16:51.386105 Set Vref, RX VrefLevel [Byte0]: 53
8748 11:16:51.388572 [Byte1]: 53
8749 11:16:51.392643
8750 11:16:51.393106 Set Vref, RX VrefLevel [Byte0]: 54
8751 11:16:51.396148 [Byte1]: 54
8752 11:16:51.400575
8753 11:16:51.401041 Set Vref, RX VrefLevel [Byte0]: 55
8754 11:16:51.404156 [Byte1]: 55
8755 11:16:51.408349
8756 11:16:51.408981 Set Vref, RX VrefLevel [Byte0]: 56
8757 11:16:51.411113 [Byte1]: 56
8758 11:16:51.415293
8759 11:16:51.418745 Set Vref, RX VrefLevel [Byte0]: 57
8760 11:16:51.422351 [Byte1]: 57
8761 11:16:51.422923
8762 11:16:51.425894 Set Vref, RX VrefLevel [Byte0]: 58
8763 11:16:51.428570 [Byte1]: 58
8764 11:16:51.429034
8765 11:16:51.431818 Set Vref, RX VrefLevel [Byte0]: 59
8766 11:16:51.435532 [Byte1]: 59
8767 11:16:51.436101
8768 11:16:51.438909 Set Vref, RX VrefLevel [Byte0]: 60
8769 11:16:51.442228 [Byte1]: 60
8770 11:16:51.446043
8771 11:16:51.446532 Set Vref, RX VrefLevel [Byte0]: 61
8772 11:16:51.449735 [Byte1]: 61
8773 11:16:51.454095
8774 11:16:51.454650 Set Vref, RX VrefLevel [Byte0]: 62
8775 11:16:51.457003 [Byte1]: 62
8776 11:16:51.461879
8777 11:16:51.462433 Set Vref, RX VrefLevel [Byte0]: 63
8778 11:16:51.464656 [Byte1]: 63
8779 11:16:51.469376
8780 11:16:51.469927 Set Vref, RX VrefLevel [Byte0]: 64
8781 11:16:51.471964 [Byte1]: 64
8782 11:16:51.476828
8783 11:16:51.477476 Set Vref, RX VrefLevel [Byte0]: 65
8784 11:16:51.479944 [Byte1]: 65
8785 11:16:51.484620
8786 11:16:51.485174 Set Vref, RX VrefLevel [Byte0]: 66
8787 11:16:51.487670 [Byte1]: 66
8788 11:16:51.491854
8789 11:16:51.492412 Set Vref, RX VrefLevel [Byte0]: 67
8790 11:16:51.495161 [Byte1]: 67
8791 11:16:51.499796
8792 11:16:51.500350 Set Vref, RX VrefLevel [Byte0]: 68
8793 11:16:51.502988 [Byte1]: 68
8794 11:16:51.507471
8795 11:16:51.508023 Set Vref, RX VrefLevel [Byte0]: 69
8796 11:16:51.510927 [Byte1]: 69
8797 11:16:51.514795
8798 11:16:51.517903 Set Vref, RX VrefLevel [Byte0]: 70
8799 11:16:51.521232 [Byte1]: 70
8800 11:16:51.521697
8801 11:16:51.524336 Set Vref, RX VrefLevel [Byte0]: 71
8802 11:16:51.527787 [Byte1]: 71
8803 11:16:51.528337
8804 11:16:51.530654 Set Vref, RX VrefLevel [Byte0]: 72
8805 11:16:51.534400 [Byte1]: 72
8806 11:16:51.537499
8807 11:16:51.538037 Set Vref, RX VrefLevel [Byte0]: 73
8808 11:16:51.540666 [Byte1]: 73
8809 11:16:51.545126
8810 11:16:51.545678 Final RX Vref Byte 0 = 54 to rank0
8811 11:16:51.548568 Final RX Vref Byte 1 = 59 to rank0
8812 11:16:51.551703 Final RX Vref Byte 0 = 54 to rank1
8813 11:16:51.554930 Final RX Vref Byte 1 = 59 to rank1==
8814 11:16:51.558181 Dram Type= 6, Freq= 0, CH_1, rank 0
8815 11:16:51.564807 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8816 11:16:51.565357 ==
8817 11:16:51.565726 DQS Delay:
8818 11:16:51.568274 DQS0 = 0, DQS1 = 0
8819 11:16:51.568764 DQM Delay:
8820 11:16:51.569125 DQM0 = 133, DQM1 = 127
8821 11:16:51.571424 DQ Delay:
8822 11:16:51.574818 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
8823 11:16:51.577803 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =128
8824 11:16:51.581590 DQ8 =114, DQ9 =116, DQ10 =130, DQ11 =118
8825 11:16:51.584552 DQ12 =134, DQ13 =136, DQ14 =136, DQ15 =138
8826 11:16:51.585019
8827 11:16:51.585384
8828 11:16:51.585717
8829 11:16:51.588003 [DramC_TX_OE_Calibration] TA2
8830 11:16:51.591309 Original DQ_B0 (3 6) =30, OEN = 27
8831 11:16:51.594795 Original DQ_B1 (3 6) =30, OEN = 27
8832 11:16:51.598122 24, 0x0, End_B0=24 End_B1=24
8833 11:16:51.598593 25, 0x0, End_B0=25 End_B1=25
8834 11:16:51.600791 26, 0x0, End_B0=26 End_B1=26
8835 11:16:51.604476 27, 0x0, End_B0=27 End_B1=27
8836 11:16:51.607997 28, 0x0, End_B0=28 End_B1=28
8837 11:16:51.611036 29, 0x0, End_B0=29 End_B1=29
8838 11:16:51.611470 30, 0x0, End_B0=30 End_B1=30
8839 11:16:51.614661 31, 0x4141, End_B0=30 End_B1=30
8840 11:16:51.617361 Byte0 end_step=30 best_step=27
8841 11:16:51.621211 Byte1 end_step=30 best_step=27
8842 11:16:51.624503 Byte0 TX OE(2T, 0.5T) = (3, 3)
8843 11:16:51.627495 Byte1 TX OE(2T, 0.5T) = (3, 3)
8844 11:16:51.628048
8845 11:16:51.628400
8846 11:16:51.633928 [DQSOSCAuto] RK0, (LSB)MR18= 0x160c, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 398 ps
8847 11:16:51.636998 CH1 RK0: MR19=303, MR18=160C
8848 11:16:51.644151 CH1_RK0: MR19=0x303, MR18=0x160C, DQSOSC=398, MR23=63, INC=23, DEC=15
8849 11:16:51.644755
8850 11:16:51.647142 ----->DramcWriteLeveling(PI) begin...
8851 11:16:51.647703 ==
8852 11:16:51.650979 Dram Type= 6, Freq= 0, CH_1, rank 1
8853 11:16:51.653696 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8854 11:16:51.654159 ==
8855 11:16:51.657172 Write leveling (Byte 0): 24 => 24
8856 11:16:51.660294 Write leveling (Byte 1): 26 => 26
8857 11:16:51.663692 DramcWriteLeveling(PI) end<-----
8858 11:16:51.664236
8859 11:16:51.664840 ==
8860 11:16:51.667348 Dram Type= 6, Freq= 0, CH_1, rank 1
8861 11:16:51.673351 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8862 11:16:51.673821 ==
8863 11:16:51.674187 [Gating] SW mode calibration
8864 11:16:51.683589 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8865 11:16:51.686976 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8866 11:16:51.690135 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8867 11:16:51.697134 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8868 11:16:51.700467 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8869 11:16:51.703649 1 4 12 | B1->B0 | 3434 2424 | 0 0 | (0 0) (1 1)
8870 11:16:51.709887 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8871 11:16:51.713894 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8872 11:16:51.716363 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8873 11:16:51.723035 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8874 11:16:51.726350 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8875 11:16:51.729522 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8876 11:16:51.736409 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8877 11:16:51.739943 1 5 12 | B1->B0 | 2424 3434 | 0 1 | (1 0) (1 0)
8878 11:16:51.743340 1 5 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 1)
8879 11:16:51.749604 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8880 11:16:51.753414 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8881 11:16:51.756612 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8882 11:16:51.762942 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8883 11:16:51.766480 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8884 11:16:51.769827 1 6 8 | B1->B0 | 2f2e 2323 | 1 0 | (0 0) (0 0)
8885 11:16:51.775873 1 6 12 | B1->B0 | 4444 2626 | 0 0 | (0 0) (1 1)
8886 11:16:51.779524 1 6 16 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
8887 11:16:51.782606 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8888 11:16:51.789649 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8889 11:16:51.792920 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8890 11:16:51.795856 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8891 11:16:51.802312 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8892 11:16:51.805988 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8893 11:16:51.809196 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8894 11:16:51.815334 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8895 11:16:51.818537 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8896 11:16:51.822141 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8897 11:16:51.828908 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8898 11:16:51.832353 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8899 11:16:51.835185 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8900 11:16:51.841999 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8901 11:16:51.845586 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8902 11:16:51.848806 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8903 11:16:51.855355 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8904 11:16:51.858760 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8905 11:16:51.862334 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8906 11:16:51.869084 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8907 11:16:51.872196 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8908 11:16:51.875486 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8909 11:16:51.881617 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8910 11:16:51.885417 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8911 11:16:51.888371 Total UI for P1: 0, mck2ui 16
8912 11:16:51.891592 best dqsien dly found for B0: ( 1, 9, 10)
8913 11:16:51.895281 Total UI for P1: 0, mck2ui 16
8914 11:16:51.898520 best dqsien dly found for B1: ( 1, 9, 10)
8915 11:16:51.901518 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8916 11:16:51.905169 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8917 11:16:51.905718
8918 11:16:51.908826 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8919 11:16:51.911662 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8920 11:16:51.915068 [Gating] SW calibration Done
8921 11:16:51.915548 ==
8922 11:16:51.918133 Dram Type= 6, Freq= 0, CH_1, rank 1
8923 11:16:51.921698 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8924 11:16:51.924728 ==
8925 11:16:51.925192 RX Vref Scan: 0
8926 11:16:51.925556
8927 11:16:51.928094 RX Vref 0 -> 0, step: 1
8928 11:16:51.928573
8929 11:16:51.931644 RX Delay 0 -> 252, step: 8
8930 11:16:51.934679 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8931 11:16:51.937965 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
8932 11:16:51.940992 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
8933 11:16:51.944768 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
8934 11:16:51.950994 iDelay=208, Bit 4, Center 135 (72 ~ 199) 128
8935 11:16:51.954342 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8936 11:16:51.957512 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
8937 11:16:51.961312 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8938 11:16:51.964245 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
8939 11:16:51.970828 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8940 11:16:51.974315 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
8941 11:16:51.977181 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8942 11:16:51.980735 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
8943 11:16:51.987422 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8944 11:16:51.990837 iDelay=208, Bit 14, Center 139 (80 ~ 199) 120
8945 11:16:51.993852 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
8946 11:16:51.994316 ==
8947 11:16:51.997050 Dram Type= 6, Freq= 0, CH_1, rank 1
8948 11:16:52.000289 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8949 11:16:52.000980 ==
8950 11:16:52.003712 DQS Delay:
8951 11:16:52.004272 DQS0 = 0, DQS1 = 0
8952 11:16:52.007519 DQM Delay:
8953 11:16:52.008082 DQM0 = 137, DQM1 = 130
8954 11:16:52.010167 DQ Delay:
8955 11:16:52.013202 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8956 11:16:52.016815 DQ4 =135, DQ5 =147, DQ6 =147, DQ7 =135
8957 11:16:52.020043 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =119
8958 11:16:52.023419 DQ12 =139, DQ13 =139, DQ14 =139, DQ15 =139
8959 11:16:52.023982
8960 11:16:52.024349
8961 11:16:52.024749 ==
8962 11:16:52.026902 Dram Type= 6, Freq= 0, CH_1, rank 1
8963 11:16:52.030351 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8964 11:16:52.030918 ==
8965 11:16:52.031285
8966 11:16:52.033077
8967 11:16:52.033534 TX Vref Scan disable
8968 11:16:52.036697 == TX Byte 0 ==
8969 11:16:52.040346 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8970 11:16:52.043367 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8971 11:16:52.046492 == TX Byte 1 ==
8972 11:16:52.049734 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8973 11:16:52.053234 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8974 11:16:52.053897 ==
8975 11:16:52.056969 Dram Type= 6, Freq= 0, CH_1, rank 1
8976 11:16:52.063006 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8977 11:16:52.063603 ==
8978 11:16:52.074816
8979 11:16:52.077959 TX Vref early break, caculate TX vref
8980 11:16:52.081074 TX Vref=16, minBit 1, minWin=22, winSum=384
8981 11:16:52.084897 TX Vref=18, minBit 0, minWin=24, winSum=398
8982 11:16:52.088374 TX Vref=20, minBit 0, minWin=24, winSum=404
8983 11:16:52.091234 TX Vref=22, minBit 1, minWin=24, winSum=408
8984 11:16:52.094563 TX Vref=24, minBit 5, minWin=24, winSum=416
8985 11:16:52.101012 TX Vref=26, minBit 0, minWin=25, winSum=426
8986 11:16:52.104413 TX Vref=28, minBit 1, minWin=25, winSum=422
8987 11:16:52.107540 TX Vref=30, minBit 0, minWin=24, winSum=417
8988 11:16:52.111236 TX Vref=32, minBit 0, minWin=24, winSum=407
8989 11:16:52.114027 TX Vref=34, minBit 0, minWin=22, winSum=396
8990 11:16:52.121047 [TxChooseVref] Worse bit 0, Min win 25, Win sum 426, Final Vref 26
8991 11:16:52.121511
8992 11:16:52.124057 Final TX Range 0 Vref 26
8993 11:16:52.124540
8994 11:16:52.124922 ==
8995 11:16:52.127424 Dram Type= 6, Freq= 0, CH_1, rank 1
8996 11:16:52.131464 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8997 11:16:52.132025 ==
8998 11:16:52.132392
8999 11:16:52.132772
9000 11:16:52.133841 TX Vref Scan disable
9001 11:16:52.140655 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
9002 11:16:52.141213 == TX Byte 0 ==
9003 11:16:52.144128 u2DelayCellOfst[0]=18 cells (5 PI)
9004 11:16:52.146968 u2DelayCellOfst[1]=11 cells (3 PI)
9005 11:16:52.150679 u2DelayCellOfst[2]=0 cells (0 PI)
9006 11:16:52.153625 u2DelayCellOfst[3]=7 cells (2 PI)
9007 11:16:52.157299 u2DelayCellOfst[4]=7 cells (2 PI)
9008 11:16:52.160680 u2DelayCellOfst[5]=22 cells (6 PI)
9009 11:16:52.164013 u2DelayCellOfst[6]=18 cells (5 PI)
9010 11:16:52.167526 u2DelayCellOfst[7]=3 cells (1 PI)
9011 11:16:52.170300 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
9012 11:16:52.173694 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
9013 11:16:52.176872 == TX Byte 1 ==
9014 11:16:52.179945 u2DelayCellOfst[8]=0 cells (0 PI)
9015 11:16:52.183089 u2DelayCellOfst[9]=7 cells (2 PI)
9016 11:16:52.183558 u2DelayCellOfst[10]=14 cells (4 PI)
9017 11:16:52.186747 u2DelayCellOfst[11]=3 cells (1 PI)
9018 11:16:52.189971 u2DelayCellOfst[12]=14 cells (4 PI)
9019 11:16:52.193522 u2DelayCellOfst[13]=18 cells (5 PI)
9020 11:16:52.196681 u2DelayCellOfst[14]=18 cells (5 PI)
9021 11:16:52.199620 u2DelayCellOfst[15]=18 cells (5 PI)
9022 11:16:52.206869 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
9023 11:16:52.209832 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
9024 11:16:52.210409 DramC Write-DBI on
9025 11:16:52.210776 ==
9026 11:16:52.213387 Dram Type= 6, Freq= 0, CH_1, rank 1
9027 11:16:52.219542 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9028 11:16:52.220018 ==
9029 11:16:52.220385
9030 11:16:52.220762
9031 11:16:52.222892 TX Vref Scan disable
9032 11:16:52.223457 == TX Byte 0 ==
9033 11:16:52.229225 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9034 11:16:52.229838 == TX Byte 1 ==
9035 11:16:52.233057 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
9036 11:16:52.236763 DramC Write-DBI off
9037 11:16:52.237324
9038 11:16:52.237772 [DATLAT]
9039 11:16:52.239422 Freq=1600, CH1 RK1
9040 11:16:52.240185
9041 11:16:52.240630 DATLAT Default: 0xf
9042 11:16:52.243006 0, 0xFFFF, sum = 0
9043 11:16:52.243580 1, 0xFFFF, sum = 0
9044 11:16:52.246059 2, 0xFFFF, sum = 0
9045 11:16:52.246532 3, 0xFFFF, sum = 0
9046 11:16:52.249460 4, 0xFFFF, sum = 0
9047 11:16:52.249932 5, 0xFFFF, sum = 0
9048 11:16:52.252723 6, 0xFFFF, sum = 0
9049 11:16:52.253291 7, 0xFFFF, sum = 0
9050 11:16:52.256440 8, 0xFFFF, sum = 0
9051 11:16:52.257055 9, 0xFFFF, sum = 0
9052 11:16:52.259517 10, 0xFFFF, sum = 0
9053 11:16:52.262856 11, 0xFFFF, sum = 0
9054 11:16:52.263430 12, 0xFFFF, sum = 0
9055 11:16:52.266052 13, 0xFFFF, sum = 0
9056 11:16:52.266626 14, 0x0, sum = 1
9057 11:16:52.269420 15, 0x0, sum = 2
9058 11:16:52.269891 16, 0x0, sum = 3
9059 11:16:52.272496 17, 0x0, sum = 4
9060 11:16:52.273091 best_step = 15
9061 11:16:52.273590
9062 11:16:52.273950 ==
9063 11:16:52.275942 Dram Type= 6, Freq= 0, CH_1, rank 1
9064 11:16:52.279481 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9065 11:16:52.280059 ==
9066 11:16:52.282531 RX Vref Scan: 0
9067 11:16:52.283100
9068 11:16:52.285601 RX Vref 0 -> 0, step: 1
9069 11:16:52.286064
9070 11:16:52.286429 RX Delay 11 -> 252, step: 4
9071 11:16:52.292711 iDelay=203, Bit 0, Center 140 (87 ~ 194) 108
9072 11:16:52.296405 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9073 11:16:52.299510 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9074 11:16:52.302685 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9075 11:16:52.309413 iDelay=203, Bit 4, Center 132 (75 ~ 190) 116
9076 11:16:52.313119 iDelay=203, Bit 5, Center 144 (91 ~ 198) 108
9077 11:16:52.315787 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9078 11:16:52.318890 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9079 11:16:52.322911 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9080 11:16:52.328865 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9081 11:16:52.332634 iDelay=203, Bit 10, Center 126 (71 ~ 182) 112
9082 11:16:52.335874 iDelay=203, Bit 11, Center 116 (63 ~ 170) 108
9083 11:16:52.339256 iDelay=203, Bit 12, Center 136 (83 ~ 190) 108
9084 11:16:52.342469 iDelay=203, Bit 13, Center 136 (83 ~ 190) 108
9085 11:16:52.348608 iDelay=203, Bit 14, Center 132 (75 ~ 190) 116
9086 11:16:52.351943 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9087 11:16:52.352407 ==
9088 11:16:52.355522 Dram Type= 6, Freq= 0, CH_1, rank 1
9089 11:16:52.359250 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9090 11:16:52.359811 ==
9091 11:16:52.361789 DQS Delay:
9092 11:16:52.362252 DQS0 = 0, DQS1 = 0
9093 11:16:52.362619 DQM Delay:
9094 11:16:52.365382 DQM0 = 134, DQM1 = 126
9095 11:16:52.365936 DQ Delay:
9096 11:16:52.368779 DQ0 =140, DQ1 =128, DQ2 =122, DQ3 =130
9097 11:16:52.375236 DQ4 =132, DQ5 =144, DQ6 =146, DQ7 =130
9098 11:16:52.378807 DQ8 =112, DQ9 =116, DQ10 =126, DQ11 =116
9099 11:16:52.381873 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =138
9100 11:16:52.382339
9101 11:16:52.382704
9102 11:16:52.383042
9103 11:16:52.385286 [DramC_TX_OE_Calibration] TA2
9104 11:16:52.388330 Original DQ_B0 (3 6) =30, OEN = 27
9105 11:16:52.391588 Original DQ_B1 (3 6) =30, OEN = 27
9106 11:16:52.392217 24, 0x0, End_B0=24 End_B1=24
9107 11:16:52.394881 25, 0x0, End_B0=25 End_B1=25
9108 11:16:52.398463 26, 0x0, End_B0=26 End_B1=26
9109 11:16:52.401447 27, 0x0, End_B0=27 End_B1=27
9110 11:16:52.405108 28, 0x0, End_B0=28 End_B1=28
9111 11:16:52.405674 29, 0x0, End_B0=29 End_B1=29
9112 11:16:52.408109 30, 0x0, End_B0=30 End_B1=30
9113 11:16:52.411434 31, 0x4141, End_B0=30 End_B1=30
9114 11:16:52.414838 Byte0 end_step=30 best_step=27
9115 11:16:52.418016 Byte1 end_step=30 best_step=27
9116 11:16:52.421087 Byte0 TX OE(2T, 0.5T) = (3, 3)
9117 11:16:52.421553 Byte1 TX OE(2T, 0.5T) = (3, 3)
9118 11:16:52.421919
9119 11:16:52.422252
9120 11:16:52.431410 [DQSOSCAuto] RK1, (LSB)MR18= 0xa07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 404 ps
9121 11:16:52.434262 CH1 RK1: MR19=303, MR18=A07
9122 11:16:52.437862 CH1_RK1: MR19=0x303, MR18=0xA07, DQSOSC=404, MR23=63, INC=22, DEC=15
9123 11:16:52.441459 [RxdqsGatingPostProcess] freq 1600
9124 11:16:52.447726 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9125 11:16:52.450857 best DQS0 dly(2T, 0.5T) = (1, 1)
9126 11:16:52.454205 best DQS1 dly(2T, 0.5T) = (1, 1)
9127 11:16:52.457510 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9128 11:16:52.461378 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9129 11:16:52.464351 best DQS0 dly(2T, 0.5T) = (1, 1)
9130 11:16:52.467696 best DQS1 dly(2T, 0.5T) = (1, 1)
9131 11:16:52.470870 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9132 11:16:52.474638 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9133 11:16:52.475205 Pre-setting of DQS Precalculation
9134 11:16:52.480486 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9135 11:16:52.487122 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9136 11:16:52.493645 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9137 11:16:52.494130
9138 11:16:52.494493
9139 11:16:52.496706 [Calibration Summary] 3200 Mbps
9140 11:16:52.500800 CH 0, Rank 0
9141 11:16:52.501362 SW Impedance : PASS
9142 11:16:52.503401 DUTY Scan : NO K
9143 11:16:52.507239 ZQ Calibration : PASS
9144 11:16:52.507811 Jitter Meter : NO K
9145 11:16:52.510633 CBT Training : PASS
9146 11:16:52.513182 Write leveling : PASS
9147 11:16:52.513646 RX DQS gating : PASS
9148 11:16:52.516614 RX DQ/DQS(RDDQC) : PASS
9149 11:16:52.520150 TX DQ/DQS : PASS
9150 11:16:52.520674 RX DATLAT : PASS
9151 11:16:52.523210 RX DQ/DQS(Engine): PASS
9152 11:16:52.527085 TX OE : PASS
9153 11:16:52.527643 All Pass.
9154 11:16:52.528009
9155 11:16:52.528346 CH 0, Rank 1
9156 11:16:52.529994 SW Impedance : PASS
9157 11:16:52.533710 DUTY Scan : NO K
9158 11:16:52.534270 ZQ Calibration : PASS
9159 11:16:52.536699 Jitter Meter : NO K
9160 11:16:52.539744 CBT Training : PASS
9161 11:16:52.540300 Write leveling : PASS
9162 11:16:52.543354 RX DQS gating : PASS
9163 11:16:52.543910 RX DQ/DQS(RDDQC) : PASS
9164 11:16:52.546290 TX DQ/DQS : PASS
9165 11:16:52.549880 RX DATLAT : PASS
9166 11:16:52.550434 RX DQ/DQS(Engine): PASS
9167 11:16:52.553186 TX OE : PASS
9168 11:16:52.553745 All Pass.
9169 11:16:52.554114
9170 11:16:52.556439 CH 1, Rank 0
9171 11:16:52.557026 SW Impedance : PASS
9172 11:16:52.559498 DUTY Scan : NO K
9173 11:16:52.563519 ZQ Calibration : PASS
9174 11:16:52.564091 Jitter Meter : NO K
9175 11:16:52.566576 CBT Training : PASS
9176 11:16:52.569498 Write leveling : PASS
9177 11:16:52.569963 RX DQS gating : PASS
9178 11:16:52.572965 RX DQ/DQS(RDDQC) : PASS
9179 11:16:52.576182 TX DQ/DQS : PASS
9180 11:16:52.576760 RX DATLAT : PASS
9181 11:16:52.579591 RX DQ/DQS(Engine): PASS
9182 11:16:52.582647 TX OE : PASS
9183 11:16:52.583114 All Pass.
9184 11:16:52.583481
9185 11:16:52.583821 CH 1, Rank 1
9186 11:16:52.586000 SW Impedance : PASS
9187 11:16:52.590189 DUTY Scan : NO K
9188 11:16:52.590757 ZQ Calibration : PASS
9189 11:16:52.592951 Jitter Meter : NO K
9190 11:16:52.595575 CBT Training : PASS
9191 11:16:52.596032 Write leveling : PASS
9192 11:16:52.599127 RX DQS gating : PASS
9193 11:16:52.602412 RX DQ/DQS(RDDQC) : PASS
9194 11:16:52.602871 TX DQ/DQS : PASS
9195 11:16:52.606172 RX DATLAT : PASS
9196 11:16:52.609187 RX DQ/DQS(Engine): PASS
9197 11:16:52.609645 TX OE : PASS
9198 11:16:52.612264 All Pass.
9199 11:16:52.612846
9200 11:16:52.613210 DramC Write-DBI on
9201 11:16:52.615801 PER_BANK_REFRESH: Hybrid Mode
9202 11:16:52.616511 TX_TRACKING: ON
9203 11:16:52.625402 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9204 11:16:52.632643 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9205 11:16:52.641874 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9206 11:16:52.645166 [FAST_K] Save calibration result to emmc
9207 11:16:52.648755 sync common calibartion params.
9208 11:16:52.649306 sync cbt_mode0:1, 1:1
9209 11:16:52.651697 dram_init: ddr_geometry: 2
9210 11:16:52.655341 dram_init: ddr_geometry: 2
9211 11:16:52.655926 dram_init: ddr_geometry: 2
9212 11:16:52.658387 0:dram_rank_size:100000000
9213 11:16:52.661888 1:dram_rank_size:100000000
9214 11:16:52.668680 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9215 11:16:52.669266 DFS_SHUFFLE_HW_MODE: ON
9216 11:16:52.671599 dramc_set_vcore_voltage set vcore to 725000
9217 11:16:52.674673 Read voltage for 1600, 0
9218 11:16:52.675143 Vio18 = 0
9219 11:16:52.678578 Vcore = 725000
9220 11:16:52.679147 Vdram = 0
9221 11:16:52.679626 Vddq = 0
9222 11:16:52.681421 Vmddr = 0
9223 11:16:52.681890 switch to 3200 Mbps bootup
9224 11:16:52.684839 [DramcRunTimeConfig]
9225 11:16:52.685312 PHYPLL
9226 11:16:52.688128 DPM_CONTROL_AFTERK: ON
9227 11:16:52.688621 PER_BANK_REFRESH: ON
9228 11:16:52.691762 REFRESH_OVERHEAD_REDUCTION: ON
9229 11:16:52.694939 CMD_PICG_NEW_MODE: OFF
9230 11:16:52.695414 XRTWTW_NEW_MODE: ON
9231 11:16:52.697840 XRTRTR_NEW_MODE: ON
9232 11:16:52.698311 TX_TRACKING: ON
9233 11:16:52.701148 RDSEL_TRACKING: OFF
9234 11:16:52.704691 DQS Precalculation for DVFS: ON
9235 11:16:52.705258 RX_TRACKING: OFF
9236 11:16:52.708110 HW_GATING DBG: ON
9237 11:16:52.708720 ZQCS_ENABLE_LP4: ON
9238 11:16:52.711312 RX_PICG_NEW_MODE: ON
9239 11:16:52.712115 TX_PICG_NEW_MODE: ON
9240 11:16:52.714351 ENABLE_RX_DCM_DPHY: ON
9241 11:16:52.717727 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9242 11:16:52.721022 DUMMY_READ_FOR_TRACKING: OFF
9243 11:16:52.724121 !!! SPM_CONTROL_AFTERK: OFF
9244 11:16:52.724676 !!! SPM could not control APHY
9245 11:16:52.727841 IMPEDANCE_TRACKING: ON
9246 11:16:52.728310 TEMP_SENSOR: ON
9247 11:16:52.731117 HW_SAVE_FOR_SR: OFF
9248 11:16:52.733999 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9249 11:16:52.737233 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9250 11:16:52.741150 Read ODT Tracking: ON
9251 11:16:52.741739 Refresh Rate DeBounce: ON
9252 11:16:52.744508 DFS_NO_QUEUE_FLUSH: ON
9253 11:16:52.747915 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9254 11:16:52.750633 ENABLE_DFS_RUNTIME_MRW: OFF
9255 11:16:52.751193 DDR_RESERVE_NEW_MODE: ON
9256 11:16:52.754464 MR_CBT_SWITCH_FREQ: ON
9257 11:16:52.757060 =========================
9258 11:16:52.775183 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9259 11:16:52.778679 dram_init: ddr_geometry: 2
9260 11:16:52.796859 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9261 11:16:52.799986 dram_init: dram init end (result: 0)
9262 11:16:52.806698 DRAM-K: Full calibration passed in 24625 msecs
9263 11:16:52.809991 MRC: failed to locate region type 0.
9264 11:16:52.810542 DRAM rank0 size:0x100000000,
9265 11:16:52.813086 DRAM rank1 size=0x100000000
9266 11:16:52.823004 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9267 11:16:52.830014 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9268 11:16:52.836187 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9269 11:16:52.846169 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9270 11:16:52.846741 DRAM rank0 size:0x100000000,
9271 11:16:52.849531 DRAM rank1 size=0x100000000
9272 11:16:52.850105 CBMEM:
9273 11:16:52.853030 IMD: root @ 0xfffff000 254 entries.
9274 11:16:52.856510 IMD: root @ 0xffffec00 62 entries.
9275 11:16:52.859792 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9276 11:16:52.865719 WARNING: RO_VPD is uninitialized or empty.
9277 11:16:52.869418 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9278 11:16:52.876593 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9279 11:16:52.889657 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9280 11:16:52.900955 BS: romstage times (exec / console): total (unknown) / 24114 ms
9281 11:16:52.901527
9282 11:16:52.902003
9283 11:16:52.910968 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9284 11:16:52.914274 ARM64: Exception handlers installed.
9285 11:16:52.917410 ARM64: Testing exception
9286 11:16:52.920469 ARM64: Done test exception
9287 11:16:52.921000 Enumerating buses...
9288 11:16:52.924169 Show all devs... Before device enumeration.
9289 11:16:52.927243 Root Device: enabled 1
9290 11:16:52.931317 CPU_CLUSTER: 0: enabled 1
9291 11:16:52.931789 CPU: 00: enabled 1
9292 11:16:52.933899 Compare with tree...
9293 11:16:52.934458 Root Device: enabled 1
9294 11:16:52.936986 CPU_CLUSTER: 0: enabled 1
9295 11:16:52.940341 CPU: 00: enabled 1
9296 11:16:52.940962 Root Device scanning...
9297 11:16:52.943764 scan_static_bus for Root Device
9298 11:16:52.947169 CPU_CLUSTER: 0 enabled
9299 11:16:52.950404 scan_static_bus for Root Device done
9300 11:16:52.954250 scan_bus: bus Root Device finished in 8 msecs
9301 11:16:52.954814 done
9302 11:16:52.960369 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9303 11:16:52.963618 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9304 11:16:52.970904 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9305 11:16:52.973426 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9306 11:16:52.976655 Allocating resources...
9307 11:16:52.980152 Reading resources...
9308 11:16:52.983879 Root Device read_resources bus 0 link: 0
9309 11:16:52.986541 DRAM rank0 size:0x100000000,
9310 11:16:52.987013 DRAM rank1 size=0x100000000
9311 11:16:52.992990 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9312 11:16:52.993484 CPU: 00 missing read_resources
9313 11:16:53.000047 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9314 11:16:53.003413 Root Device read_resources bus 0 link: 0 done
9315 11:16:53.007389 Done reading resources.
9316 11:16:53.009696 Show resources in subtree (Root Device)...After reading.
9317 11:16:53.013419 Root Device child on link 0 CPU_CLUSTER: 0
9318 11:16:53.016297 CPU_CLUSTER: 0 child on link 0 CPU: 00
9319 11:16:53.026368 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9320 11:16:53.026843 CPU: 00
9321 11:16:53.029377 Root Device assign_resources, bus 0 link: 0
9322 11:16:53.032666 CPU_CLUSTER: 0 missing set_resources
9323 11:16:53.039546 Root Device assign_resources, bus 0 link: 0 done
9324 11:16:53.040103 Done setting resources.
9325 11:16:53.046259 Show resources in subtree (Root Device)...After assigning values.
9326 11:16:53.049147 Root Device child on link 0 CPU_CLUSTER: 0
9327 11:16:53.052688 CPU_CLUSTER: 0 child on link 0 CPU: 00
9328 11:16:53.062816 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9329 11:16:53.063379 CPU: 00
9330 11:16:53.066046 Done allocating resources.
9331 11:16:53.072683 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9332 11:16:53.073248 Enabling resources...
9333 11:16:53.075706 done.
9334 11:16:53.079102 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9335 11:16:53.082217 Initializing devices...
9336 11:16:53.082683 Root Device init
9337 11:16:53.085420 init hardware done!
9338 11:16:53.085901 0x00000018: ctrlr->caps
9339 11:16:53.089417 52.000 MHz: ctrlr->f_max
9340 11:16:53.092395 0.400 MHz: ctrlr->f_min
9341 11:16:53.093004 0x40ff8080: ctrlr->voltages
9342 11:16:53.095488 sclk: 390625
9343 11:16:53.095953 Bus Width = 1
9344 11:16:53.099048 sclk: 390625
9345 11:16:53.099604 Bus Width = 1
9346 11:16:53.102209 Early init status = 3
9347 11:16:53.105359 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9348 11:16:53.109048 in-header: 03 fc 00 00 01 00 00 00
9349 11:16:53.112277 in-data: 00
9350 11:16:53.114898 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9351 11:16:53.122751 in-header: 03 fd 00 00 00 00 00 00
9352 11:16:53.125934 in-data:
9353 11:16:53.129137 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9354 11:16:53.133198 in-header: 03 fc 00 00 01 00 00 00
9355 11:16:53.136217 in-data: 00
9356 11:16:53.139685 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9357 11:16:53.144704 in-header: 03 fd 00 00 00 00 00 00
9358 11:16:53.147633 in-data:
9359 11:16:53.150839 [SSUSB] Setting up USB HOST controller...
9360 11:16:53.154173 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9361 11:16:53.157759 [SSUSB] phy power-on done.
9362 11:16:53.160776 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9363 11:16:53.167636 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9364 11:16:53.170968 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9365 11:16:53.177859 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9366 11:16:53.183847 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9367 11:16:53.190796 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9368 11:16:53.196881 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9369 11:16:53.203528 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9370 11:16:53.206708 SPM: binary array size = 0x9dc
9371 11:16:53.210426 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9372 11:16:53.217108 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9373 11:16:53.223708 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9374 11:16:53.229878 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9375 11:16:53.233270 configure_display: Starting display init
9376 11:16:53.267726 anx7625_power_on_init: Init interface.
9377 11:16:53.271506 anx7625_disable_pd_protocol: Disabled PD feature.
9378 11:16:53.274460 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9379 11:16:53.302367 anx7625_start_dp_work: Secure OCM version=00
9380 11:16:53.305410 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9381 11:16:53.320100 sp_tx_get_edid_block: EDID Block = 1
9382 11:16:53.423005 Extracted contents:
9383 11:16:53.426428 header: 00 ff ff ff ff ff ff 00
9384 11:16:53.429138 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9385 11:16:53.432436 version: 01 04
9386 11:16:53.436201 basic params: 95 1f 11 78 0a
9387 11:16:53.439192 chroma info: 76 90 94 55 54 90 27 21 50 54
9388 11:16:53.442790 established: 00 00 00
9389 11:16:53.448898 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9390 11:16:53.452373 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9391 11:16:53.459878 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9392 11:16:53.465760 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9393 11:16:53.471917 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9394 11:16:53.475296 extensions: 00
9395 11:16:53.475891 checksum: fb
9396 11:16:53.476268
9397 11:16:53.479241 Manufacturer: IVO Model 57d Serial Number 0
9398 11:16:53.481884 Made week 0 of 2020
9399 11:16:53.485242 EDID version: 1.4
9400 11:16:53.485707 Digital display
9401 11:16:53.488615 6 bits per primary color channel
9402 11:16:53.489182 DisplayPort interface
9403 11:16:53.492076 Maximum image size: 31 cm x 17 cm
9404 11:16:53.495100 Gamma: 220%
9405 11:16:53.495568 Check DPMS levels
9406 11:16:53.498529 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9407 11:16:53.505292 First detailed timing is preferred timing
9408 11:16:53.505850 Established timings supported:
9409 11:16:53.508870 Standard timings supported:
9410 11:16:53.511974 Detailed timings
9411 11:16:53.514889 Hex of detail: 383680a07038204018303c0035ae10000019
9412 11:16:53.521743 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9413 11:16:53.525101 0780 0798 07c8 0820 hborder 0
9414 11:16:53.528429 0438 043b 0447 0458 vborder 0
9415 11:16:53.532011 -hsync -vsync
9416 11:16:53.532611 Did detailed timing
9417 11:16:53.538425 Hex of detail: 000000000000000000000000000000000000
9418 11:16:53.541197 Manufacturer-specified data, tag 0
9419 11:16:53.544878 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9420 11:16:53.547971 ASCII string: InfoVision
9421 11:16:53.551834 Hex of detail: 000000fe00523134304e574635205248200a
9422 11:16:53.554723 ASCII string: R140NWF5 RH
9423 11:16:53.555283 Checksum
9424 11:16:53.558030 Checksum: 0xfb (valid)
9425 11:16:53.561774 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9426 11:16:53.565156 DSI data_rate: 832800000 bps
9427 11:16:53.571026 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9428 11:16:53.574343 anx7625_parse_edid: pixelclock(138800).
9429 11:16:53.577505 hactive(1920), hsync(48), hfp(24), hbp(88)
9430 11:16:53.580965 vactive(1080), vsync(12), vfp(3), vbp(17)
9431 11:16:53.584394 anx7625_dsi_config: config dsi.
9432 11:16:53.591196 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9433 11:16:53.604629 anx7625_dsi_config: success to config DSI
9434 11:16:53.608288 anx7625_dp_start: MIPI phy setup OK.
9435 11:16:53.611149 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9436 11:16:53.614595 mtk_ddp_mode_set invalid vrefresh 60
9437 11:16:53.618516 main_disp_path_setup
9438 11:16:53.619095 ovl_layer_smi_id_en
9439 11:16:53.621019 ovl_layer_smi_id_en
9440 11:16:53.621476 ccorr_config
9441 11:16:53.621833 aal_config
9442 11:16:53.624484 gamma_config
9443 11:16:53.625342 postmask_config
9444 11:16:53.627998 dither_config
9445 11:16:53.631350 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9446 11:16:53.637617 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9447 11:16:53.641558 Root Device init finished in 555 msecs
9448 11:16:53.644123 CPU_CLUSTER: 0 init
9449 11:16:53.651369 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9450 11:16:53.657717 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9451 11:16:53.658286 APU_MBOX 0x190000b0 = 0x10001
9452 11:16:53.660994 APU_MBOX 0x190001b0 = 0x10001
9453 11:16:53.663795 APU_MBOX 0x190005b0 = 0x10001
9454 11:16:53.667636 APU_MBOX 0x190006b0 = 0x10001
9455 11:16:53.673955 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9456 11:16:53.683860 read SPI 0x539f4 0xe237: 6246 us, 9271 KB/s, 74.168 Mbps
9457 11:16:53.697086 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9458 11:16:53.702570 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9459 11:16:53.714230 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9460 11:16:53.723565 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9461 11:16:53.727031 CPU_CLUSTER: 0 init finished in 81 msecs
9462 11:16:53.730321 Devices initialized
9463 11:16:53.733131 Show all devs... After init.
9464 11:16:53.733599 Root Device: enabled 1
9465 11:16:53.737200 CPU_CLUSTER: 0: enabled 1
9466 11:16:53.740327 CPU: 00: enabled 1
9467 11:16:53.743626 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9468 11:16:53.747051 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9469 11:16:53.750304 ELOG: NV offset 0x57f000 size 0x1000
9470 11:16:53.757064 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9471 11:16:53.763060 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9472 11:16:53.766846 ELOG: Event(17) added with size 13 at 2023-06-05 11:16:54 UTC
9473 11:16:53.773065 out: cmd=0x121: 03 db 21 01 00 00 00 00
9474 11:16:53.777154 in-header: 03 bc 00 00 2c 00 00 00
9475 11:16:53.786475 in-data: a3 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9476 11:16:53.793160 ELOG: Event(A1) added with size 10 at 2023-06-05 11:16:54 UTC
9477 11:16:53.799372 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9478 11:16:53.806457 ELOG: Event(A0) added with size 9 at 2023-06-05 11:16:54 UTC
9479 11:16:53.809721 elog_add_boot_reason: Logged dev mode boot
9480 11:16:53.815770 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9481 11:16:53.816335 Finalize devices...
9482 11:16:53.819651 Devices finalized
9483 11:16:53.822456 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9484 11:16:53.826143 Writing coreboot table at 0xffe64000
9485 11:16:53.829026 0. 000000000010a000-0000000000113fff: RAMSTAGE
9486 11:16:53.835954 1. 0000000040000000-00000000400fffff: RAM
9487 11:16:53.839368 2. 0000000040100000-000000004032afff: RAMSTAGE
9488 11:16:53.842491 3. 000000004032b000-00000000545fffff: RAM
9489 11:16:53.845853 4. 0000000054600000-000000005465ffff: BL31
9490 11:16:53.849330 5. 0000000054660000-00000000ffe63fff: RAM
9491 11:16:53.855576 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9492 11:16:53.859078 7. 0000000100000000-000000023fffffff: RAM
9493 11:16:53.862568 Passing 5 GPIOs to payload:
9494 11:16:53.865796 NAME | PORT | POLARITY | VALUE
9495 11:16:53.871972 EC in RW | 0x000000aa | low | undefined
9496 11:16:53.875206 EC interrupt | 0x00000005 | low | undefined
9497 11:16:53.881892 TPM interrupt | 0x000000ab | high | undefined
9498 11:16:53.885062 SD card detect | 0x00000011 | high | undefined
9499 11:16:53.888556 speaker enable | 0x00000093 | high | undefined
9500 11:16:53.891752 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9501 11:16:53.894801 in-header: 03 f9 00 00 02 00 00 00
9502 11:16:53.898280 in-data: 02 00
9503 11:16:53.901790 ADC[4]: Raw value=901922 ID=7
9504 11:16:53.904611 ADC[3]: Raw value=213282 ID=1
9505 11:16:53.905078 RAM Code: 0x71
9506 11:16:53.908740 ADC[6]: Raw value=75036 ID=0
9507 11:16:53.911947 ADC[5]: Raw value=213282 ID=1
9508 11:16:53.912508 SKU Code: 0x1
9509 11:16:53.918245 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a129
9510 11:16:53.918810 coreboot table: 964 bytes.
9511 11:16:53.921626 IMD ROOT 0. 0xfffff000 0x00001000
9512 11:16:53.924671 IMD SMALL 1. 0xffffe000 0x00001000
9513 11:16:53.927847 RO MCACHE 2. 0xffffc000 0x00001104
9514 11:16:53.931615 CONSOLE 3. 0xfff7c000 0x00080000
9515 11:16:53.934468 FMAP 4. 0xfff7b000 0x00000452
9516 11:16:53.937864 TIME STAMP 5. 0xfff7a000 0x00000910
9517 11:16:53.941158 VBOOT WORK 6. 0xfff66000 0x00014000
9518 11:16:53.945016 RAMOOPS 7. 0xffe66000 0x00100000
9519 11:16:53.947737 COREBOOT 8. 0xffe64000 0x00002000
9520 11:16:53.951140 IMD small region:
9521 11:16:53.954596 IMD ROOT 0. 0xffffec00 0x00000400
9522 11:16:53.957478 VPD 1. 0xffffeba0 0x0000004c
9523 11:16:53.961294 MMC STATUS 2. 0xffffeb80 0x00000004
9524 11:16:53.967662 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9525 11:16:53.968231 Probing TPM: done!
9526 11:16:53.974208 Connected to device vid:did:rid of 1ae0:0028:00
9527 11:16:53.980638 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9528 11:16:53.984176 Initialized TPM device CR50 revision 0
9529 11:16:53.987782 Checking cr50 for pending updates
9530 11:16:53.992830 Reading cr50 TPM mode
9531 11:16:54.001650 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9532 11:16:54.008643 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9533 11:16:54.049197 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9534 11:16:54.051954 Checking segment from ROM address 0x40100000
9535 11:16:54.055504 Checking segment from ROM address 0x4010001c
9536 11:16:54.061747 Loading segment from ROM address 0x40100000
9537 11:16:54.062311 code (compression=0)
9538 11:16:54.072071 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9539 11:16:54.078320 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9540 11:16:54.078874 it's not compressed!
9541 11:16:54.084888 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9542 11:16:54.091292 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9543 11:16:54.109087 Loading segment from ROM address 0x4010001c
9544 11:16:54.109656 Entry Point 0x80000000
9545 11:16:54.112498 Loaded segments
9546 11:16:54.115423 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9547 11:16:54.122478 Jumping to boot code at 0x80000000(0xffe64000)
9548 11:16:54.128786 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9549 11:16:54.135687 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9550 11:16:54.143218 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9551 11:16:54.146974 Checking segment from ROM address 0x40100000
9552 11:16:54.149950 Checking segment from ROM address 0x4010001c
9553 11:16:54.156624 Loading segment from ROM address 0x40100000
9554 11:16:54.157181 code (compression=1)
9555 11:16:54.163439 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9556 11:16:54.173242 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9557 11:16:54.173812 using LZMA
9558 11:16:54.182237 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9559 11:16:54.188413 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9560 11:16:54.191192 Loading segment from ROM address 0x4010001c
9561 11:16:54.191653 Entry Point 0x54601000
9562 11:16:54.195794 Loaded segments
9563 11:16:54.198141 NOTICE: MT8192 bl31_setup
9564 11:16:54.205339 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9565 11:16:54.208462 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9566 11:16:54.212061 WARNING: region 0:
9567 11:16:54.215448 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9568 11:16:54.215913 WARNING: region 1:
9569 11:16:54.221919 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9570 11:16:54.225833 WARNING: region 2:
9571 11:16:54.228917 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9572 11:16:54.232073 WARNING: region 3:
9573 11:16:54.235429 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9574 11:16:54.238756 WARNING: region 4:
9575 11:16:54.244935 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9576 11:16:54.245424 WARNING: region 5:
9577 11:16:54.248322 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9578 11:16:54.251991 WARNING: region 6:
9579 11:16:54.255215 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9580 11:16:54.258763 WARNING: region 7:
9581 11:16:54.262083 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9582 11:16:54.268440 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9583 11:16:54.271518 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9584 11:16:54.274962 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9585 11:16:54.281198 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9586 11:16:54.285289 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9587 11:16:54.291415 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9588 11:16:54.294531 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9589 11:16:54.298101 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9590 11:16:54.304851 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9591 11:16:54.307979 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9592 11:16:54.311768 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9593 11:16:54.317917 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9594 11:16:54.321068 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9595 11:16:54.327531 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9596 11:16:54.330891 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9597 11:16:54.334709 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9598 11:16:54.341098 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9599 11:16:54.344461 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9600 11:16:54.351413 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9601 11:16:54.354628 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9602 11:16:54.357466 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9603 11:16:54.364256 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9604 11:16:54.367487 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9605 11:16:54.373982 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9606 11:16:54.377532 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9607 11:16:54.380803 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9608 11:16:54.387324 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9609 11:16:54.390974 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9610 11:16:54.397055 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9611 11:16:54.400429 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9612 11:16:54.404638 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9613 11:16:54.410218 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9614 11:16:54.413676 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9615 11:16:54.417404 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9616 11:16:54.420599 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9617 11:16:54.426794 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9618 11:16:54.430253 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9619 11:16:54.433646 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9620 11:16:54.436842 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9621 11:16:54.443676 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9622 11:16:54.447062 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9623 11:16:54.450057 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9624 11:16:54.453329 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9625 11:16:54.459970 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9626 11:16:54.463115 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9627 11:16:54.466631 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9628 11:16:54.473561 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9629 11:16:54.476852 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9630 11:16:54.479910 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9631 11:16:54.486348 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9632 11:16:54.489640 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9633 11:16:54.496610 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9634 11:16:54.500215 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9635 11:16:54.503535 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9636 11:16:54.510075 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9637 11:16:54.513051 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9638 11:16:54.519643 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9639 11:16:54.522958 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9640 11:16:54.529466 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9641 11:16:54.532835 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9642 11:16:54.536034 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9643 11:16:54.542647 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9644 11:16:54.546337 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9645 11:16:54.552874 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9646 11:16:54.556405 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9647 11:16:54.562729 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9648 11:16:54.565770 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9649 11:16:54.573257 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9650 11:16:54.576471 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9651 11:16:54.579538 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9652 11:16:54.585749 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9653 11:16:54.589191 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9654 11:16:54.595922 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9655 11:16:54.599329 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9656 11:16:54.605496 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9657 11:16:54.609003 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9658 11:16:54.615700 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9659 11:16:54.619424 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9660 11:16:54.622194 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9661 11:16:54.629079 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9662 11:16:54.632080 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9663 11:16:54.639208 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9664 11:16:54.642230 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9665 11:16:54.648758 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9666 11:16:54.652244 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9667 11:16:54.659264 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9668 11:16:54.662396 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9669 11:16:54.665477 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9670 11:16:54.672691 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9671 11:16:54.675962 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9672 11:16:54.682349 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9673 11:16:54.685406 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9674 11:16:54.692277 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9675 11:16:54.695654 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9676 11:16:54.698866 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9677 11:16:54.705486 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9678 11:16:54.708857 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9679 11:16:54.712267 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9680 11:16:54.718655 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9681 11:16:54.722498 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9682 11:16:54.725729 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9683 11:16:54.731852 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9684 11:16:54.735625 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9685 11:16:54.738851 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9686 11:16:54.745384 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9687 11:16:54.749094 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9688 11:16:54.755340 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9689 11:16:54.758866 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9690 11:16:54.762212 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9691 11:16:54.768689 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9692 11:16:54.772204 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9693 11:16:54.778578 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9694 11:16:54.782283 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9695 11:16:54.788157 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9696 11:16:54.791516 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9697 11:16:54.795150 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9698 11:16:54.798393 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9699 11:16:54.804788 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9700 11:16:54.808685 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9701 11:16:54.811542 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9702 11:16:54.818208 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9703 11:16:54.821369 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9704 11:16:54.824733 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9705 11:16:54.828584 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9706 11:16:54.834655 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9707 11:16:54.838123 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9708 11:16:54.844425 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9709 11:16:54.847723 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9710 11:16:54.851338 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9711 11:16:54.857979 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9712 11:16:54.861294 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9713 11:16:54.867931 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9714 11:16:54.871537 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9715 11:16:54.874629 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9716 11:16:54.881368 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9717 11:16:54.884450 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9718 11:16:54.891544 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9719 11:16:54.894607 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9720 11:16:54.897580 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9721 11:16:54.904736 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9722 11:16:54.908003 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9723 11:16:54.914244 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9724 11:16:54.917756 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9725 11:16:54.920648 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9726 11:16:54.927664 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9727 11:16:54.930955 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9728 11:16:54.933905 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9729 11:16:54.941065 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9730 11:16:54.944229 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9731 11:16:54.950612 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9732 11:16:54.954021 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9733 11:16:54.957533 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9734 11:16:54.964154 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9735 11:16:54.967714 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9736 11:16:54.974437 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9737 11:16:54.977449 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9738 11:16:54.980735 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9739 11:16:54.987359 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9740 11:16:54.990626 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9741 11:16:54.997225 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9742 11:16:55.000493 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9743 11:16:55.004095 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9744 11:16:55.011052 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9745 11:16:55.013703 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9746 11:16:55.020196 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9747 11:16:55.023335 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9748 11:16:55.026821 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9749 11:16:55.033443 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9750 11:16:55.036498 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9751 11:16:55.043438 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9752 11:16:55.046655 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9753 11:16:55.050112 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9754 11:16:55.056556 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9755 11:16:55.059960 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9756 11:16:55.065893 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9757 11:16:55.069644 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9758 11:16:55.073033 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9759 11:16:55.079542 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9760 11:16:55.082934 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9761 11:16:55.089274 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9762 11:16:55.092668 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9763 11:16:55.096222 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9764 11:16:55.102691 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9765 11:16:55.106048 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9766 11:16:55.112757 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9767 11:16:55.115710 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9768 11:16:55.118927 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9769 11:16:55.125648 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9770 11:16:55.129307 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9771 11:16:55.135577 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9772 11:16:55.138541 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9773 11:16:55.145148 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9774 11:16:55.149007 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9775 11:16:55.152090 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9776 11:16:55.158537 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9777 11:16:55.161755 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9778 11:16:55.168478 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9779 11:16:55.171808 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9780 11:16:55.178738 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9781 11:16:55.181965 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9782 11:16:55.185411 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9783 11:16:55.191539 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9784 11:16:55.194915 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9785 11:16:55.201705 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9786 11:16:55.204581 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9787 11:16:55.211888 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9788 11:16:55.214469 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9789 11:16:55.218207 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9790 11:16:55.224958 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9791 11:16:55.228227 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9792 11:16:55.234343 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9793 11:16:55.237602 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9794 11:16:55.241313 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9795 11:16:55.248042 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9796 11:16:55.251458 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9797 11:16:55.258316 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9798 11:16:55.261073 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9799 11:16:55.267229 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9800 11:16:55.270791 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9801 11:16:55.274678 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9802 11:16:55.280618 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9803 11:16:55.284023 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9804 11:16:55.290733 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9805 11:16:55.293824 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9806 11:16:55.301097 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9807 11:16:55.303724 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9808 11:16:55.307439 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9809 11:16:55.314006 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9810 11:16:55.316967 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9811 11:16:55.320289 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9812 11:16:55.326710 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9813 11:16:55.329974 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9814 11:16:55.333232 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9815 11:16:55.337102 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9816 11:16:55.343413 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9817 11:16:55.346923 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9818 11:16:55.353057 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9819 11:16:55.356635 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9820 11:16:55.360040 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9821 11:16:55.366504 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9822 11:16:55.370086 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9823 11:16:55.373166 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9824 11:16:55.379376 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9825 11:16:55.382974 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9826 11:16:55.389866 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9827 11:16:55.393178 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9828 11:16:55.396207 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9829 11:16:55.403134 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9830 11:16:55.405766 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9831 11:16:55.409171 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9832 11:16:55.415758 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9833 11:16:55.419415 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9834 11:16:55.425832 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9835 11:16:55.429012 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9836 11:16:55.432562 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9837 11:16:55.439024 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9838 11:16:55.443008 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9839 11:16:55.445444 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9840 11:16:55.452331 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9841 11:16:55.455243 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9842 11:16:55.461807 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9843 11:16:55.465514 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9844 11:16:55.469069 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9845 11:16:55.475316 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9846 11:16:55.478614 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9847 11:16:55.482082 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9848 11:16:55.488415 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9849 11:16:55.491620 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9850 11:16:55.494997 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9851 11:16:55.501739 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9852 11:16:55.504889 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9853 11:16:55.508167 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9854 11:16:55.511358 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9855 11:16:55.518939 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9856 11:16:55.521171 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9857 11:16:55.525316 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9858 11:16:55.528467 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9859 11:16:55.534394 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9860 11:16:55.538152 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9861 11:16:55.540987 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9862 11:16:55.547496 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9863 11:16:55.551026 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9864 11:16:55.554295 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9865 11:16:55.560877 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9866 11:16:55.564332 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9867 11:16:55.570637 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9868 11:16:55.573896 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9869 11:16:55.577271 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9870 11:16:55.583877 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9871 11:16:55.587108 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9872 11:16:55.594181 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9873 11:16:55.597103 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9874 11:16:55.600878 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9875 11:16:55.607139 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9876 11:16:55.610569 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9877 11:16:55.616976 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9878 11:16:55.620267 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9879 11:16:55.623910 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9880 11:16:55.630303 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9881 11:16:55.634021 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9882 11:16:55.640069 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9883 11:16:55.643874 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9884 11:16:55.650089 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9885 11:16:55.653212 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9886 11:16:55.659702 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9887 11:16:55.663842 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9888 11:16:55.666223 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9889 11:16:55.672807 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9890 11:16:55.676149 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9891 11:16:55.682843 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9892 11:16:55.686607 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9893 11:16:55.689087 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9894 11:16:55.695871 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9895 11:16:55.699503 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9896 11:16:55.706177 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9897 11:16:55.709038 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9898 11:16:55.715845 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9899 11:16:55.719380 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9900 11:16:55.722596 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9901 11:16:55.729504 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9902 11:16:55.732490 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9903 11:16:55.738538 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9904 11:16:55.742141 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9905 11:16:55.745209 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9906 11:16:55.752292 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9907 11:16:55.755463 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9908 11:16:55.762253 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9909 11:16:55.765346 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9910 11:16:55.772325 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9911 11:16:55.775237 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9912 11:16:55.778395 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9913 11:16:55.785768 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9914 11:16:55.788473 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9915 11:16:55.795344 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9916 11:16:55.798071 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9917 11:16:55.804978 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9918 11:16:55.807955 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9919 11:16:55.811862 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9920 11:16:55.818441 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9921 11:16:55.821317 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9922 11:16:55.824804 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9923 11:16:55.832029 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9924 11:16:55.834692 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9925 11:16:55.841468 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9926 11:16:55.844424 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9927 11:16:55.851468 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9928 11:16:55.854715 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9929 11:16:55.857405 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9930 11:16:55.864681 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9931 11:16:55.867477 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9932 11:16:55.874240 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9933 11:16:55.877791 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9934 11:16:55.883968 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9935 11:16:55.887134 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9936 11:16:55.890516 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9937 11:16:55.897227 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9938 11:16:55.900493 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9939 11:16:55.907184 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9940 11:16:55.910539 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9941 11:16:55.917424 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9942 11:16:55.920130 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9943 11:16:55.923833 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9944 11:16:55.930497 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9945 11:16:55.933346 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9946 11:16:55.940604 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9947 11:16:55.943620 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9948 11:16:55.950734 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9949 11:16:55.953453 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9950 11:16:55.960347 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9951 11:16:55.963245 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9952 11:16:55.966919 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9953 11:16:55.973052 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9954 11:16:55.976737 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9955 11:16:55.983196 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9956 11:16:55.986127 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9957 11:16:55.993311 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9958 11:16:55.996505 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9959 11:16:55.999760 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9960 11:16:56.006727 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9961 11:16:56.009685 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9962 11:16:56.016238 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9963 11:16:56.019705 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9964 11:16:56.026029 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9965 11:16:56.029343 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9966 11:16:56.035426 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9967 11:16:56.039248 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9968 11:16:56.045556 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9969 11:16:56.048992 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9970 11:16:56.055600 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9971 11:16:56.058778 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9972 11:16:56.062508 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9973 11:16:56.068633 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9974 11:16:56.072299 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9975 11:16:56.079134 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9976 11:16:56.081313 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9977 11:16:56.088542 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9978 11:16:56.091590 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9979 11:16:56.098216 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9980 11:16:56.101524 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9981 11:16:56.105120 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9982 11:16:56.111551 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9983 11:16:56.114658 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9984 11:16:56.121642 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9985 11:16:56.124634 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9986 11:16:56.128074 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9987 11:16:56.134447 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9988 11:16:56.138111 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9989 11:16:56.144455 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9990 11:16:56.148131 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9991 11:16:56.154179 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9992 11:16:56.157837 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9993 11:16:56.164694 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9994 11:16:56.168039 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9995 11:16:56.174319 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9996 11:16:56.177587 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9997 11:16:56.184990 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9998 11:16:56.187728 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9999 11:16:56.193824 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
10000 11:16:56.197237 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
10001 11:16:56.203751 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
10002 11:16:56.206930 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
10003 11:16:56.213664 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
10004 11:16:56.217397 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
10005 11:16:56.224044 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
10006 11:16:56.227302 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
10007 11:16:56.234111 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
10008 11:16:56.237147 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
10009 11:16:56.243721 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
10010 11:16:56.247574 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
10011 11:16:56.253194 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
10012 11:16:56.256904 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
10013 11:16:56.263331 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
10014 11:16:56.266713 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
10015 11:16:56.273416 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10016 11:16:56.276640 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10017 11:16:56.279764 INFO: [APUAPC] vio 0
10018 11:16:56.283168 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10019 11:16:56.290615 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10020 11:16:56.293124 INFO: [APUAPC] D0_APC_0: 0x400510
10021 11:16:56.296834 INFO: [APUAPC] D0_APC_1: 0x0
10022 11:16:56.299797 INFO: [APUAPC] D0_APC_2: 0x1540
10023 11:16:56.300354 INFO: [APUAPC] D0_APC_3: 0x0
10024 11:16:56.303172 INFO: [APUAPC] D1_APC_0: 0xffffffff
10025 11:16:56.309657 INFO: [APUAPC] D1_APC_1: 0xffffffff
10026 11:16:56.310124 INFO: [APUAPC] D1_APC_2: 0x3fffff
10027 11:16:56.312585 INFO: [APUAPC] D1_APC_3: 0x0
10028 11:16:56.315964 INFO: [APUAPC] D2_APC_0: 0xffffffff
10029 11:16:56.319470 INFO: [APUAPC] D2_APC_1: 0xffffffff
10030 11:16:56.323136 INFO: [APUAPC] D2_APC_2: 0x3fffff
10031 11:16:56.325930 INFO: [APUAPC] D2_APC_3: 0x0
10032 11:16:56.329791 INFO: [APUAPC] D3_APC_0: 0xffffffff
10033 11:16:56.332737 INFO: [APUAPC] D3_APC_1: 0xffffffff
10034 11:16:56.336261 INFO: [APUAPC] D3_APC_2: 0x3fffff
10035 11:16:56.339003 INFO: [APUAPC] D3_APC_3: 0x0
10036 11:16:56.342647 INFO: [APUAPC] D4_APC_0: 0xffffffff
10037 11:16:56.346193 INFO: [APUAPC] D4_APC_1: 0xffffffff
10038 11:16:56.348836 INFO: [APUAPC] D4_APC_2: 0x3fffff
10039 11:16:56.352554 INFO: [APUAPC] D4_APC_3: 0x0
10040 11:16:56.355711 INFO: [APUAPC] D5_APC_0: 0xffffffff
10041 11:16:56.358958 INFO: [APUAPC] D5_APC_1: 0xffffffff
10042 11:16:56.362298 INFO: [APUAPC] D5_APC_2: 0x3fffff
10043 11:16:56.365567 INFO: [APUAPC] D5_APC_3: 0x0
10044 11:16:56.369335 INFO: [APUAPC] D6_APC_0: 0xffffffff
10045 11:16:56.372203 INFO: [APUAPC] D6_APC_1: 0xffffffff
10046 11:16:56.375471 INFO: [APUAPC] D6_APC_2: 0x3fffff
10047 11:16:56.379095 INFO: [APUAPC] D6_APC_3: 0x0
10048 11:16:56.382168 INFO: [APUAPC] D7_APC_0: 0xffffffff
10049 11:16:56.385425 INFO: [APUAPC] D7_APC_1: 0xffffffff
10050 11:16:56.388933 INFO: [APUAPC] D7_APC_2: 0x3fffff
10051 11:16:56.392050 INFO: [APUAPC] D7_APC_3: 0x0
10052 11:16:56.395477 INFO: [APUAPC] D8_APC_0: 0xffffffff
10053 11:16:56.398654 INFO: [APUAPC] D8_APC_1: 0xffffffff
10054 11:16:56.402223 INFO: [APUAPC] D8_APC_2: 0x3fffff
10055 11:16:56.405125 INFO: [APUAPC] D8_APC_3: 0x0
10056 11:16:56.409135 INFO: [APUAPC] D9_APC_0: 0xffffffff
10057 11:16:56.412486 INFO: [APUAPC] D9_APC_1: 0xffffffff
10058 11:16:56.415273 INFO: [APUAPC] D9_APC_2: 0x3fffff
10059 11:16:56.418483 INFO: [APUAPC] D9_APC_3: 0x0
10060 11:16:56.422502 INFO: [APUAPC] D10_APC_0: 0xffffffff
10061 11:16:56.425418 INFO: [APUAPC] D10_APC_1: 0xffffffff
10062 11:16:56.428354 INFO: [APUAPC] D10_APC_2: 0x3fffff
10063 11:16:56.431751 INFO: [APUAPC] D10_APC_3: 0x0
10064 11:16:56.435400 INFO: [APUAPC] D11_APC_0: 0xffffffff
10065 11:16:56.438862 INFO: [APUAPC] D11_APC_1: 0xffffffff
10066 11:16:56.441783 INFO: [APUAPC] D11_APC_2: 0x3fffff
10067 11:16:56.445009 INFO: [APUAPC] D11_APC_3: 0x0
10068 11:16:56.448702 INFO: [APUAPC] D12_APC_0: 0xffffffff
10069 11:16:56.451771 INFO: [APUAPC] D12_APC_1: 0xffffffff
10070 11:16:56.455155 INFO: [APUAPC] D12_APC_2: 0x3fffff
10071 11:16:56.458296 INFO: [APUAPC] D12_APC_3: 0x0
10072 11:16:56.461511 INFO: [APUAPC] D13_APC_0: 0xffffffff
10073 11:16:56.464918 INFO: [APUAPC] D13_APC_1: 0xffffffff
10074 11:16:56.468475 INFO: [APUAPC] D13_APC_2: 0x3fffff
10075 11:16:56.471765 INFO: [APUAPC] D13_APC_3: 0x0
10076 11:16:56.475126 INFO: [APUAPC] D14_APC_0: 0xffffffff
10077 11:16:56.478120 INFO: [APUAPC] D14_APC_1: 0xffffffff
10078 11:16:56.481647 INFO: [APUAPC] D14_APC_2: 0x3fffff
10079 11:16:56.485191 INFO: [APUAPC] D14_APC_3: 0x0
10080 11:16:56.488211 INFO: [APUAPC] D15_APC_0: 0xffffffff
10081 11:16:56.491116 INFO: [APUAPC] D15_APC_1: 0xffffffff
10082 11:16:56.494528 INFO: [APUAPC] D15_APC_2: 0x3fffff
10083 11:16:56.498592 INFO: [APUAPC] D15_APC_3: 0x0
10084 11:16:56.502013 INFO: [APUAPC] APC_CON: 0x4
10085 11:16:56.504684 INFO: [NOCDAPC] D0_APC_0: 0x0
10086 11:16:56.508281 INFO: [NOCDAPC] D0_APC_1: 0x0
10087 11:16:56.511213 INFO: [NOCDAPC] D1_APC_0: 0x0
10088 11:16:56.511677 INFO: [NOCDAPC] D1_APC_1: 0xfff
10089 11:16:56.514864 INFO: [NOCDAPC] D2_APC_0: 0x0
10090 11:16:56.517964 INFO: [NOCDAPC] D2_APC_1: 0xfff
10091 11:16:56.521252 INFO: [NOCDAPC] D3_APC_0: 0x0
10092 11:16:56.525191 INFO: [NOCDAPC] D3_APC_1: 0xfff
10093 11:16:56.527811 INFO: [NOCDAPC] D4_APC_0: 0x0
10094 11:16:56.531639 INFO: [NOCDAPC] D4_APC_1: 0xfff
10095 11:16:56.534654 INFO: [NOCDAPC] D5_APC_0: 0x0
10096 11:16:56.538174 INFO: [NOCDAPC] D5_APC_1: 0xfff
10097 11:16:56.541282 INFO: [NOCDAPC] D6_APC_0: 0x0
10098 11:16:56.544903 INFO: [NOCDAPC] D6_APC_1: 0xfff
10099 11:16:56.545471 INFO: [NOCDAPC] D7_APC_0: 0x0
10100 11:16:56.547910 INFO: [NOCDAPC] D7_APC_1: 0xfff
10101 11:16:56.551440 INFO: [NOCDAPC] D8_APC_0: 0x0
10102 11:16:56.554055 INFO: [NOCDAPC] D8_APC_1: 0xfff
10103 11:16:56.557410 INFO: [NOCDAPC] D9_APC_0: 0x0
10104 11:16:56.561077 INFO: [NOCDAPC] D9_APC_1: 0xfff
10105 11:16:56.564170 INFO: [NOCDAPC] D10_APC_0: 0x0
10106 11:16:56.567757 INFO: [NOCDAPC] D10_APC_1: 0xfff
10107 11:16:56.571060 INFO: [NOCDAPC] D11_APC_0: 0x0
10108 11:16:56.574567 INFO: [NOCDAPC] D11_APC_1: 0xfff
10109 11:16:56.577253 INFO: [NOCDAPC] D12_APC_0: 0x0
10110 11:16:56.580551 INFO: [NOCDAPC] D12_APC_1: 0xfff
10111 11:16:56.583789 INFO: [NOCDAPC] D13_APC_0: 0x0
10112 11:16:56.587726 INFO: [NOCDAPC] D13_APC_1: 0xfff
10113 11:16:56.588289 INFO: [NOCDAPC] D14_APC_0: 0x0
10114 11:16:56.590935 INFO: [NOCDAPC] D14_APC_1: 0xfff
10115 11:16:56.593709 INFO: [NOCDAPC] D15_APC_0: 0x0
10116 11:16:56.597179 INFO: [NOCDAPC] D15_APC_1: 0xfff
10117 11:16:56.601900 INFO: [NOCDAPC] APC_CON: 0x4
10118 11:16:56.603687 INFO: [APUAPC] set_apusys_apc done
10119 11:16:56.606745 INFO: [DEVAPC] devapc_init done
10120 11:16:56.610249 INFO: GICv3 without legacy support detected.
10121 11:16:56.617155 INFO: ARM GICv3 driver initialized in EL3
10122 11:16:56.619973 INFO: Maximum SPI INTID supported: 639
10123 11:16:56.623419 INFO: BL31: Initializing runtime services
10124 11:16:56.630117 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10125 11:16:56.633606 INFO: SPM: enable CPC mode
10126 11:16:56.636561 INFO: mcdi ready for mcusys-off-idle and system suspend
10127 11:16:56.642953 INFO: BL31: Preparing for EL3 exit to normal world
10128 11:16:56.646902 INFO: Entry point address = 0x80000000
10129 11:16:56.647489 INFO: SPSR = 0x8
10130 11:16:56.653296
10131 11:16:56.653862
10132 11:16:56.654230
10133 11:16:56.656449 Starting depthcharge on Spherion...
10134 11:16:56.656950
10135 11:16:56.657316 Wipe memory regions:
10136 11:16:56.657658
10137 11:16:56.660102 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10138 11:16:56.660692 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10139 11:16:56.661175 Setting prompt string to ['asurada:']
10140 11:16:56.661618 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10141 11:16:56.662335 [0x00000040000000, 0x00000054600000)
10142 11:16:56.781841
10143 11:16:56.782411 [0x00000054660000, 0x00000080000000)
10144 11:16:57.042714
10145 11:16:57.043278 [0x000000821a7280, 0x000000ffe64000)
10146 11:16:57.787795
10147 11:16:57.788389 [0x00000100000000, 0x00000240000000)
10148 11:16:59.677477
10149 11:16:59.680335 Initializing XHCI USB controller at 0x11200000.
10150 11:17:00.661416
10151 11:17:00.661567 R8152: Initializing
10152 11:17:00.661635
10153 11:17:00.665036 Version 9 (ocp_data = 6010)
10154 11:17:00.665106
10155 11:17:00.668345 R8152: Done initializing
10156 11:17:00.668410
10157 11:17:00.668476 Adding net device
10158 11:17:01.189896
10159 11:17:01.193062 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10160 11:17:01.193145
10161 11:17:01.193219
10162 11:17:01.193304
10163 11:17:01.193619 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10165 11:17:01.293931 asurada: tftpboot 192.168.201.1 10591250/tftp-deploy-3xwj17rv/kernel/image.itb 10591250/tftp-deploy-3xwj17rv/kernel/cmdline
10166 11:17:01.294064 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10167 11:17:01.294146 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:20)
10168 11:17:01.298684 tftpboot 192.168.201.1 10591250/tftp-deploy-3xwj17rv/kernel/image.ittp-deploy-3xwj17rv/kernel/cmdline
10169 11:17:01.298769
10170 11:17:01.298836 Waiting for link
10171 11:17:01.500803
10172 11:17:01.500923 done.
10173 11:17:01.500990
10174 11:17:01.501056 MAC: f4:f5:e8:50:de:0a
10175 11:17:01.501116
10176 11:17:01.504134 Sending DHCP discover... done.
10177 11:17:01.504211
10178 11:17:01.507257 Waiting for reply... done.
10179 11:17:01.507338
10180 11:17:01.510658 Sending DHCP request... done.
10181 11:17:01.510758
10182 11:17:01.514823 Waiting for reply... done.
10183 11:17:01.514903
10184 11:17:01.514965 My ip is 192.168.201.14
10185 11:17:01.515022
10186 11:17:01.518539 The DHCP server ip is 192.168.201.1
10187 11:17:01.518621
10188 11:17:01.524724 TFTP server IP predefined by user: 192.168.201.1
10189 11:17:01.524804
10190 11:17:01.531333 Bootfile predefined by user: 10591250/tftp-deploy-3xwj17rv/kernel/image.itb
10191 11:17:01.531410
10192 11:17:01.535162 Sending tftp read request... done.
10193 11:17:01.535236
10194 11:17:01.538245 Waiting for the transfer...
10195 11:17:01.538323
10196 11:17:01.768775 00000000 ################################################################
10197 11:17:01.768926
10198 11:17:01.987328 00080000 ################################################################
10199 11:17:01.987485
10200 11:17:02.208141 00100000 ################################################################
10201 11:17:02.208302
10202 11:17:02.425301 00180000 ################################################################
10203 11:17:02.425458
10204 11:17:02.642749 00200000 ################################################################
10205 11:17:02.642909
10206 11:17:02.860076 00280000 ################################################################
10207 11:17:02.860248
10208 11:17:03.091463 00300000 ################################################################
10209 11:17:03.091625
10210 11:17:03.311816 00380000 ################################################################
10211 11:17:03.311981
10212 11:17:03.529396 00400000 ################################################################
10213 11:17:03.529559
10214 11:17:03.747090 00480000 ################################################################
10215 11:17:03.747261
10216 11:17:03.964918 00500000 ################################################################
10217 11:17:03.965088
10218 11:17:04.193656 00580000 ################################################################
10219 11:17:04.193827
10220 11:17:04.415088 00600000 ################################################################
10221 11:17:04.415250
10222 11:17:04.633721 00680000 ################################################################
10223 11:17:04.633879
10224 11:17:04.851559 00700000 ################################################################
10225 11:17:04.851691
10226 11:17:05.069299 00780000 ################################################################
10227 11:17:05.069434
10228 11:17:05.286533 00800000 ################################################################
10229 11:17:05.286657
10230 11:17:05.504510 00880000 ################################################################
10231 11:17:05.504719
10232 11:17:05.724042 00900000 ################################################################
10233 11:17:05.724217
10234 11:17:05.941365 00980000 ################################################################
10235 11:17:05.941512
10236 11:17:06.159076 00a00000 ################################################################
10237 11:17:06.159223
10238 11:17:06.377351 00a80000 ################################################################
10239 11:17:06.377491
10240 11:17:06.594874 00b00000 ################################################################
10241 11:17:06.595011
10242 11:17:06.812357 00b80000 ################################################################
10243 11:17:06.812503
10244 11:17:07.029922 00c00000 ################################################################
10245 11:17:07.030061
10246 11:17:07.247126 00c80000 ################################################################
10247 11:17:07.247263
10248 11:17:07.466325 00d00000 ################################################################
10249 11:17:07.466459
10250 11:17:07.685897 00d80000 ################################################################
10251 11:17:07.686033
10252 11:17:07.904671 00e00000 ################################################################
10253 11:17:07.904808
10254 11:17:08.121959 00e80000 ################################################################
10255 11:17:08.122097
10256 11:17:08.339276 00f00000 ################################################################
10257 11:17:08.339407
10258 11:17:08.557104 00f80000 ################################################################
10259 11:17:08.557246
10260 11:17:08.788351 01000000 ################################################################
10261 11:17:08.788484
10262 11:17:09.008173 01080000 ################################################################
10263 11:17:09.008303
10264 11:17:09.226517 01100000 ################################################################
10265 11:17:09.226666
10266 11:17:09.456824 01180000 ################################################################
10267 11:17:09.456961
10268 11:17:09.689186 01200000 ################################################################
10269 11:17:09.689329
10270 11:17:09.908809 01280000 ################################################################
10271 11:17:09.908950
10272 11:17:10.124437 01300000 ################################################################
10273 11:17:10.124622
10274 11:17:10.343030 01380000 ################################################################
10275 11:17:10.343195
10276 11:17:10.563134 01400000 ################################################################
10277 11:17:10.563294
10278 11:17:10.781108 01480000 ################################################################
10279 11:17:10.781280
10280 11:17:11.010600 01500000 ################################################################
10281 11:17:11.010763
10282 11:17:11.254086 01580000 ################################################################
10283 11:17:11.254249
10284 11:17:11.481971 01600000 ################################################################
10285 11:17:11.482130
10286 11:17:11.701453 01680000 ################################################################
10287 11:17:11.701587
10288 11:17:11.919661 01700000 ################################################################
10289 11:17:11.919814
10290 11:17:12.142717 01780000 ################################################################
10291 11:17:12.142842
10292 11:17:12.386798 01800000 ################################################################
10293 11:17:12.386954
10294 11:17:12.621035 01880000 ################################################################
10295 11:17:12.621170
10296 11:17:12.841517 01900000 ################################################################
10297 11:17:12.841660
10298 11:17:13.060686 01980000 ################################################################
10299 11:17:13.060836
10300 11:17:13.276737 01a00000 ################################################################ done.
10301 11:17:13.276907
10302 11:17:13.280035 The bootfile was 27781558 bytes long.
10303 11:17:13.280159
10304 11:17:13.283289 Sending tftp read request... done.
10305 11:17:13.283373
10306 11:17:13.286229 Waiting for the transfer...
10307 11:17:13.286312
10308 11:17:13.286395 00000000 # done.
10309 11:17:13.286475
10310 11:17:13.295956 Command line loaded dynamically from TFTP file: 10591250/tftp-deploy-3xwj17rv/kernel/cmdline
10311 11:17:13.296040
10312 11:17:13.312413 The command line is: console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10591250/extract-nfsrootfs-r0k0govq,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10313 11:17:13.312503
10314 11:17:13.312625 Loading FIT.
10315 11:17:13.312703
10316 11:17:13.315671 Image ramdisk-1 has 17646578 bytes.
10317 11:17:13.315753
10318 11:17:13.319175 Image fdt-1 has 46924 bytes.
10319 11:17:13.319258
10320 11:17:13.322422 Image kernel-1 has 10086024 bytes.
10321 11:17:13.322506
10322 11:17:13.329156 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10323 11:17:13.332664
10324 11:17:13.348899 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10325 11:17:13.348991
10326 11:17:13.352219 Choosing best match conf-1 for compat google,spherion-rev2.
10327 11:17:13.357772
10328 11:17:13.361893 Connected to device vid:did:rid of 1ae0:0028:00
10329 11:17:13.369227
10330 11:17:13.372733 tpm_get_response: command 0x17b, return code 0x0
10331 11:17:13.372816
10332 11:17:13.375794 ec_init: CrosEC protocol v3 supported (256, 248)
10333 11:17:13.380186
10334 11:17:13.383081 tpm_cleanup: add release locality here.
10335 11:17:13.383164
10336 11:17:13.383246 Shutting down all USB controllers.
10337 11:17:13.386389
10338 11:17:13.386472 Removing current net device
10339 11:17:13.386554
10340 11:17:13.393123 Exiting depthcharge with code 4 at timestamp: 46163801
10341 11:17:13.393206
10342 11:17:13.396800 LZMA decompressing kernel-1 to 0x821a6718
10343 11:17:13.396883
10344 11:17:13.399854 LZMA decompressing kernel-1 to 0x40000000
10345 11:17:14.666801
10346 11:17:14.666940 jumping to kernel
10347 11:17:14.667366 end: 2.2.4 bootloader-commands (duration 00:00:18) [common]
10348 11:17:14.667477 start: 2.2.5 auto-login-action (timeout 00:04:07) [common]
10349 11:17:14.667561 Setting prompt string to ['Linux version [0-9]']
10350 11:17:14.667643 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10351 11:17:14.667727 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10352 11:17:15.215421
10353 11:17:15.219197 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10354 11:17:15.222441 start: 2.2.5.1 login-action (timeout 00:04:07) [common]
10355 11:17:15.222528 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10356 11:17:15.222614 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10357 11:17:15.222689 Using line separator: #'\n'#
10358 11:17:15.222747 No login prompt set.
10359 11:17:15.222808 Parsing kernel messages
10360 11:17:15.222861 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10361 11:17:15.222962 [login-action] Waiting for messages, (timeout 00:04:07)
10362 11:17:15.241686 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1609115-arm64-gcc-10-defconfig-arm64-chromebook-dplkv) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 10:57:14 UTC 2023
10363 11:17:15.245359 [ 0.000000] random: crng init done
10364 11:17:15.252399 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10365 11:17:15.255031 [ 0.000000] efi: UEFI not found.
10366 11:17:15.261841 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10367 11:17:15.268191 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10368 11:17:15.278547 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10369 11:17:15.288145 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10370 11:17:15.291227 [ 0.000000] NUMA: No NUMA configuration found
10371 11:17:15.302187 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10372 11:17:15.304524 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10373 11:17:15.308276 [ 0.000000] Zone ranges:
10374 11:17:15.314482 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10375 11:17:15.317799 [ 0.000000] DMA32 empty
10376 11:17:15.324728 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10377 11:17:15.327692 [ 0.000000] Movable zone start for each node
10378 11:17:15.331255 [ 0.000000] Early memory node ranges
10379 11:17:15.337891 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10380 11:17:15.344080 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10381 11:17:15.350998 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10382 11:17:15.357444 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10383 11:17:15.360669 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10384 11:17:15.370712 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10385 11:17:15.373809 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10386 11:17:15.380414 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10387 11:17:15.387652 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10388 11:17:15.390704 [ 0.000000] psci: probing for conduit method from DT.
10389 11:17:15.397159 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10390 11:17:15.400271 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10391 11:17:15.406971 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10392 11:17:15.410318 [ 0.000000] psci: SMC Calling Convention v1.2
10393 11:17:15.417024 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10394 11:17:15.420820 [ 0.000000] Detected VIPT I-cache on CPU0
10395 11:17:15.427166 [ 0.000000] CPU features: detected: GIC system register CPU interface
10396 11:17:15.433815 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10397 11:17:15.440203 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10398 11:17:15.447016 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10399 11:17:15.453241 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10400 11:17:15.463645 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10401 11:17:15.466750 [ 0.000000] alternatives: applying boot alternatives
10402 11:17:15.469941 [ 0.000000] Fallback order for Node 0: 0
10403 11:17:15.476466 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10404 11:17:15.480057 [ 0.000000] Policy zone: Normal
10405 11:17:15.499504 [ 0.000000] Kernel command line: console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10591250/extract-nfsrootfs-r0k0govq,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10406 11:17:15.509953 [ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10407 11:17:15.516280 [ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10408 11:17:15.525901 [ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10409 11:17:15.532448 [ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10410 11:17:15.536499 [ 0.000000] software IO TLB: area num 8.
10411 11:17:15.542957 [ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10412 11:17:15.555835 [ 0.000000] Memory: 7955708K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397060K reserved, 32768K cma-reserved)
10413 11:17:15.562625 [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10414 11:17:15.569221 [ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10415 11:17:15.572027 [ 0.000000] rcu: RCU event tracing is enabled.
10416 11:17:15.578980 [ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10417 11:17:15.585346 [ 0.000000] Trampoline variant of Tasks RCU enabled.
10418 11:17:15.588477 [ 0.000000] Tracing variant of Tasks RCU enabled.
10419 11:17:15.598765 [ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10420 11:17:15.604879 [ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10421 11:17:15.608475 [ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10422 11:17:15.614963 [ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10423 11:17:15.618299 [ 0.000000] GICv3: 608 SPIs implemented
10424 11:17:15.625177 [ 0.000000] GICv3: 0 Extended SPIs implemented
10425 11:17:15.628220 [ 0.000000] Root IRQ handler: gic_handle_irq
10426 11:17:15.632029 [ 0.000000] GICv3: GICv3 features: 16 PPIs
10427 11:17:15.638558 [ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10428 11:17:15.651575 [ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10429 11:17:15.661507 [ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10430 11:17:15.668188 [ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10431 11:17:15.674424 [ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10432 11:17:15.687920 [ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10433 11:17:15.694094 [ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10434 11:17:15.697691 [ 0.000953] Console: colour dummy device 80x25
10435 11:17:15.707427 [ 0.001019] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10436 11:17:15.714190 [ 0.001027] pid_max: default: 32768 minimum: 301
10437 11:17:15.717829 [ 0.001069] LSM: Security Framework initializing
10438 11:17:15.727237 [ 0.001175] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10439 11:17:15.734260 [ 0.001226] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10440 11:17:15.740365 [ 0.002378] cblist_init_generic: Setting adjustable number of callback queues.
10441 11:17:15.746951 [ 0.002388] cblist_init_generic: Setting shift to 3 and lim to 1.
10442 11:17:15.753593 [ 0.002431] cblist_init_generic: Setting shift to 3 and lim to 1.
10443 11:17:15.757008 [ 0.002536] rcu: Hierarchical SRCU implementation.
10444 11:17:15.763632 [ 0.002538] rcu: Max phase no-delay instances is 1000.
10445 11:17:15.766926 [ 0.004163] EFI services will not be available.
10446 11:17:15.773807 [ 0.004385] smp: Bringing up secondary CPUs ...
10447 11:17:15.776724 [ 0.004681] Detected VIPT I-cache on CPU1
10448 11:17:15.783658 [ 0.004752] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10449 11:17:15.789969 [ 0.004784] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10450 11:17:15.793374 [ 0.005124] Detected VIPT I-cache on CPU2
10451 11:17:15.800268 [ 0.005176] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10452 11:17:15.806697 [ 0.005192] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10453 11:17:15.810051 [ 0.005453] Detected VIPT I-cache on CPU3
10454 11:17:15.819764 [ 0.005501] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10455 11:17:15.826502 [ 0.005515] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10456 11:17:15.829509 [ 0.005823] CPU features: detected: Spectre-v4
10457 11:17:15.832924 [ 0.005829] CPU features: detected: Spectre-BHB
10458 11:17:15.836418 [ 0.005835] Detected PIPT I-cache on CPU4
10459 11:17:15.846153 [ 0.005893] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10460 11:17:15.853003 [ 0.005910] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10461 11:17:15.856529 [ 0.006204] Detected PIPT I-cache on CPU5
10462 11:17:15.862867 [ 0.006267] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10463 11:17:15.869157 [ 0.006284] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10464 11:17:15.872755 [ 0.006567] Detected PIPT I-cache on CPU6
10465 11:17:15.879543 [ 0.006633] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10466 11:17:15.885622 [ 0.006649] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10467 11:17:15.889271 [ 0.006948] Detected PIPT I-cache on CPU7
10468 11:17:15.899413 [ 0.007012] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10469 11:17:15.902288 [ 0.007028] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10470 11:17:15.908718 [ 0.007076] smp: Brought up 1 node, 8 CPUs
10471 11:17:15.912195 [ 0.007082] SMP: Total of 8 processors activated.
10472 11:17:15.919012 [ 0.007085] CPU features: detected: 32-bit EL0 Support
10473 11:17:15.925775 [ 0.007088] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10474 11:17:15.932487 [ 0.007090] CPU features: detected: Common not Private translations
10475 11:17:15.939156 [ 0.007093] CPU features: detected: CRC32 instructions
10476 11:17:15.941911 [ 0.007095] CPU features: detected: RCpc load-acquire (LDAPR)
10477 11:17:15.948488 [ 0.007097] CPU features: detected: LSE atomic instructions
10478 11:17:15.955357 [ 0.007099] CPU features: detected: Privileged Access Never
10479 11:17:15.958479 [ 0.007101] CPU features: detected: RAS Extension Support
10480 11:17:15.968548 [ 0.007104] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10481 11:17:15.971428 [ 0.007175] CPU: All CPU(s) started at EL2
10482 11:17:15.978117 [ 0.007177] alternatives: applying system-wide alternatives
10483 11:17:15.981636 [ 0.012142] devtmpfs: initialized
10484 11:17:15.988469 [ 0.017705] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10485 11:17:15.997978 [ 0.017720] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10486 11:17:16.001180 [ 0.018633] pinctrl core: initialized pinctrl subsystem
10487 11:17:16.004467 [ 0.019828] DMI not present or invalid.
10488 11:17:16.011181 [ 0.020166] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10489 11:17:16.017678 [ 0.020899] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10490 11:17:16.027992 [ 0.021128] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10491 11:17:16.034632 [ 0.021306] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10492 11:17:16.041380 [ 0.021332] audit: initializing netlink subsys (disabled)
10493 11:17:16.047715 [ 0.021408] audit: type=2000 audit(0.016:1): state=initialized audit_enabled=0 res=1
10494 11:17:16.054456 [ 0.022122] thermal_sys: Registered thermal governor 'step_wise'
10495 11:17:16.060620 [ 0.022125] thermal_sys: Registered thermal governor 'power_allocator'
10496 11:17:16.063873 [ 0.022166] cpuidle: using governor menu
10497 11:17:16.070734 [ 0.022231] NET: Registered PF_QIPCRTR protocol family
10498 11:17:16.077144 [ 0.022354] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10499 11:17:16.080633 [ 0.022445] ASID allocator initialised with 32768 entries
10500 11:17:16.083671 [ 0.023421] Serial: AMBA PL011 UART driver
10501 11:17:16.090585 [ 0.027808] Trying to register duplicate clock ID: 134
10502 11:17:16.094076 [ 0.081908] KASLR enabled
10503 11:17:16.100475 [ 0.086876] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10504 11:17:16.107388 [ 0.086880] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10505 11:17:16.113874 [ 0.086884] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10506 11:17:16.120400 [ 0.086887] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10507 11:17:16.127035 [ 0.086890] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10508 11:17:16.133510 [ 0.086892] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10509 11:17:16.139937 [ 0.086895] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10510 11:17:16.147225 [ 0.086897] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10511 11:17:16.149982 [ 0.088064] ACPI: Interpreter disabled.
10512 11:17:16.153816 [ 0.090383] iommu: Default domain type: Translated
10513 11:17:16.160010 [ 0.090387] iommu: DMA domain TLB invalidation policy: strict mode
10514 11:17:16.163160 [ 0.090558] SCSI subsystem initialized
10515 11:17:16.170126 [ 0.090734] usbcore: registered new interface driver usbfs
10516 11:17:16.173139 [ 0.090754] usbcore: registered new interface driver hub
10517 11:17:16.179977 [ 0.090767] usbcore: registered new device driver usb
10518 11:17:16.183558 [ 0.091578] pps_core: LinuxPPS API ver. 1 registered
10519 11:17:16.192864 [ 0.091581] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10520 11:17:16.196834 [ 0.091587] PTP clock support registered
10521 11:17:16.199946 [ 0.091670] EDAC MC: Ver: 3.0.0
10522 11:17:16.202924 [ 0.093431] FPGA manager framework
10523 11:17:16.209725 [ 0.093475] Advanced Linux Sound Architecture Driver Initialized.
10524 11:17:16.213352 [ 0.093928] vgaarb: loaded
10525 11:17:16.220131 [ 0.094155] clocksource: Switched to clocksource arch_sys_counter
10526 11:17:16.223078 [ 0.094284] VFS: Disk quotas dquot_6.6.0
10527 11:17:16.229231 [ 0.094311] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10528 11:17:16.232905 [ 0.094406] pnp: PnP ACPI: disabled
10529 11:17:16.239430 [ 0.097293] NET: Registered PF_INET protocol family
10530 11:17:16.245990 [ 0.097764] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10531 11:17:16.255620 [ 0.102317] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10532 11:17:16.262485 [ 0.102388] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10533 11:17:16.269181 [ 0.102396] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10534 11:17:16.279124 [ 0.102965] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10535 11:17:16.285883 [ 0.105099] TCP: Hash tables configured (established 65536 bind 65536)
10536 11:17:16.292003 [ 0.105212] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10537 11:17:16.298546 [ 0.105403] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10538 11:17:16.302269 [ 0.105670] NET: Registered PF_UNIX/PF_LOCAL protocol family
10539 11:17:16.308501 [ 0.105899] RPC: Registered named UNIX socket transport module.
10540 11:17:16.315448 [ 0.105903] RPC: Registered udp transport module.
10541 11:17:16.318473 [ 0.105905] RPC: Registered tcp transport module.
10542 11:17:16.324831 [ 0.105907] RPC: Registered tcp NFSv4.1 backchannel transport module.
10543 11:17:16.328694 [ 0.105914] PCI: CLS 0 bytes, default 64
10544 11:17:16.331421 [ 0.106209] Unpacking initramfs...
10545 11:17:16.341547 [ 0.114663] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10546 11:17:16.348216 [ 0.114905] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10547 11:17:16.352289 [ 0.115342] kvm [1]: IPA Size Limit: 40 bits
10548 11:17:16.358461 [ 0.115368] kvm [1]: GICv3: no GICV resource entry
10549 11:17:16.361428 [ 0.115373] kvm [1]: disabling GICv2 emulation
10550 11:17:16.367967 [ 0.115387] kvm [1]: GIC system register CPU interface enabled
10551 11:17:16.371639 [ 0.115485] kvm [1]: vgic interrupt IRQ18
10552 11:17:16.377761 [ 0.115589] kvm [1]: VHE mode initialized successfully
10553 11:17:16.381054 [ 0.116489] Initialise system trusted keyrings
10554 11:17:16.387895 [ 0.116566] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10555 11:17:16.394912 [ 0.119825] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10556 11:17:16.398033 [ 0.120121] NFS: Registering the id_resolver key type
10557 11:17:16.404422 [ 0.120139] Key type id_resolver registered
10558 11:17:16.407438 [ 0.120141] Key type id_legacy registered
10559 11:17:16.414164 [ 0.120180] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10560 11:17:16.420865 [ 0.120184] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10561 11:17:16.427461 [ 0.120272] 9p: Installing v9fs 9p2000 file system support
10562 11:17:16.430632 [ 0.152019] Key type asymmetric registered
10563 11:17:16.434265 [ 0.152024] Asymmetric key parser 'x509' registered
10564 11:17:16.444385 [ 0.152068] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10565 11:17:16.447102 [ 0.152073] io scheduler mq-deadline registered
10566 11:17:16.450607 [ 0.152075] io scheduler kyber registered
10567 11:17:16.453579 [ 0.164538] EINJ: ACPI disabled.
10568 11:17:16.463789 [ 0.186761] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10569 11:17:16.473922 [ 0.186903] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10570 11:17:16.480403 [ 0.197074] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10571 11:17:16.487062 [ 0.198587] printk: console [ttyS0] disabled
10572 11:17:16.493696 [ 0.218751] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10573 11:17:16.500779 [ 0.832528] Freeing initrd memory: 17228K
10574 11:17:16.503364 [ 0.834275] printk: console [ttyS0] enabled
10575 11:17:16.509819 [ 1.509518] SuperH (H)SCI(F) driver initialized
10576 11:17:16.513114 [ 1.514525] msm_serial: driver initialized
10577 11:17:16.526536 [ 1.523113] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10578 11:17:16.536046 [ 1.531399] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10579 11:17:16.542636 [ 1.539680] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10580 11:17:16.552585 [ 1.548049] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10581 11:17:16.559211 [ 1.556494] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10582 11:17:16.568969 [ 1.564945] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10583 11:17:16.575394 [ 1.573224] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10584 11:17:16.585956 [ 1.581761] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10585 11:17:16.592066 [ 1.590043] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10586 11:17:16.601494 [ 1.604865] loop: module loaded
10587 11:17:16.610692 [ 1.610518] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10588 11:17:16.633118 [ 1.633078] mtk-pmic-keys: Failed to locate of_node [id: -1]
10589 11:17:16.636413 [ 1.639362] megasas: 07.719.03.00-rc1
10590 11:17:16.648447 [ 1.648587] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10591 11:17:16.658046 [ 1.657595] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10592 11:17:16.665148 [ 1.659495] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10593 11:17:16.674417 [ 1.674517] tun: Universal TUN/TAP device driver, 1.6
10594 11:17:16.681941 [ 1.675384] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10595 11:17:16.685972 [ 1.680305] thunder_xcv, ver 1.0
10596 11:17:16.686078 [ 1.688980] thunder_bgx, ver 1.0
10597 11:17:16.690108 [ 1.692214] nicpf, ver 1.0
10598 11:17:16.699736 [ 1.695950] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10599 11:17:16.715033 [ 1.703165] hns3: Copyright (c) 2017 Huawei Corporation.
10600 11:17:16.715731 [ 1.708495] hclge is initializing
10601 11:17:16.715803 [ 1.711814] e1000: Intel(R) PRO/1000 Network Driver
10602 11:17:16.718876 [ 1.716683] e1000: Copyright (c) 1999-2006 Intel Corporation.
10603 11:17:16.723809 [ 1.722435] e1000e: Intel(R) PRO/1000 Network Driver
10604 11:17:16.731713 [ 1.727390] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10605 11:17:16.736446 [ 1.733314] igb: Intel(R) Gigabit Ethernet Network Driver
10606 11:17:16.740168 [ 1.738703] igb: Copyright (c) 2007-2014 Intel Corporation.
10607 11:17:16.746100 [ 1.744285] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10608 11:17:16.756049 [ 1.746164] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10609 11:17:16.763073 [ 1.750543] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10610 11:17:16.766419 [ 1.750839] sky2: driver version 1.30
10611 11:17:16.772710 [ 1.771933] VFIO - User Level meta-driver version: 0.3
10612 11:17:16.780068 [ 1.779771] usbcore: registered new interface driver usb-storage
10613 11:17:16.786061 [ 1.785954] usbcore: registered new device driver onboard-usb-hub
10614 11:17:16.794735 [ 1.794700] mt6397-rtc mt6359-rtc: registered as rtc0
10615 11:17:16.804205 [ 1.799905] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-05T11:17:17 UTC (1685963837)
10616 11:17:16.807508 [ 1.809204] i2c_dev: i2c /dev entries driver
10617 11:17:16.823390 [ 1.820563] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10618 11:17:16.830824 [ 1.830472] sdhci: Secure Digital Host Controller Interface driver
10619 11:17:16.837022 [ 1.836647] sdhci: Copyright(c) Pierre Ossman
10620 11:17:16.843463 [ 1.841820] Synopsys Designware Multimedia Card Interface Driver
10621 11:17:16.846925 [ 1.848276] mmc0: CQHCI version 5.10
10622 11:17:16.853666 [ 1.848712] sdhci-pltfm: SDHCI platform and OF driver helper
10623 11:17:16.860145 [ 1.859596] ledtrig-cpu: registered to indicate activity on CPUs
10624 11:17:16.866639 [ 1.866641] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10625 11:17:16.873803 [ 1.873774] usbcore: registered new interface driver usbhid
10626 11:17:16.876936 [ 1.879341] usbhid: USB HID core driver
10627 11:17:16.883905 [ 1.883349] spi_master spi0: will run message pump with realtime priority
10628 11:17:16.930825 [ 1.924203] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10629 11:17:16.945943 [ 1.939576] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10630 11:17:16.953013 [ 1.952976] mmc0: Command Queue Engine enabled
10631 11:17:16.956508 [ 1.954141] cros-ec-spi spi0.0: Chrome EC device registered
10632 11:17:16.963561 [ 1.957447] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10633 11:17:16.970257 [ 1.970071] mmcblk0: mmc0:0001 DA4128 116 GiB
10634 11:17:16.983666 [ 1.979928] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10635 11:17:16.989604 [ 1.985343] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10636 11:17:16.993024 [ 1.991110] NET: Registered PF_PACKET protocol family
10637 11:17:16.999736 [ 1.996715] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10638 11:17:17.002847 [ 1.999824] 9pnet: Installing 9P2000 support
10639 11:17:17.009596 [ 2.005626] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10640 11:17:17.012521 [ 2.008980] Key type dns_resolver registered
10641 11:17:17.019628 [ 2.014705] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10642 11:17:17.022785 [ 2.018633] registered taskstats version 1
10643 11:17:17.029290 [ 2.028541] Loading compiled-in X.509 certificates
10644 11:17:17.061315 [ 2.054646] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10645 11:17:17.071360 [ 2.065049] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10646 11:17:17.080698 [ 2.077257] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10647 11:17:17.091826 [ 2.091906] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10648 11:17:17.098116 [ 2.098471] xhci-mtk 11200000.usb: xHCI Host Controller
10649 11:17:17.104864 [ 2.103709] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10650 11:17:17.115169 [ 2.111299] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10651 11:17:17.121642 [ 2.120470] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10652 11:17:17.124879 [ 2.126301] xhci-mtk 11200000.usb: xHCI Host Controller
10653 11:17:17.134887 [ 2.131523] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10654 11:17:17.141408 [ 2.138916] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10655 11:17:17.144528 [ 2.146475] hub 1-0:1.0: USB hub found
10656 11:17:17.147908 [ 2.150253] hub 1-0:1.0: 1 port detected
10657 11:17:17.158344 [ 2.154350] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10658 11:17:17.161350 [ 2.162867] hub 2-0:1.0: USB hub found
10659 11:17:17.164483 [ 2.166648] hub 2-0:1.0: 1 port detected
10660 11:17:17.173243 [ 2.173597] mtk-msdc 11f70000.mmc: Got CD GPIO
10661 11:17:17.190474 [ 2.187077] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10662 11:17:17.196714 [ 2.194841] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10663 11:17:17.207168 [ 2.202554] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10664 11:17:17.213293 [ 2.211953] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10665 11:17:17.223617 [ 2.219774] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10666 11:17:17.230244 [ 2.227546] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10667 11:17:17.236733 [ 2.235206] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10668 11:17:17.246395 [ 2.242766] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10669 11:17:17.253524 [ 2.250326] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10670 11:17:17.263730 [ 2.260833] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10671 11:17:17.270541 [ 2.268940] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10672 11:17:17.280372 [ 2.277035] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10673 11:17:17.287384 [ 2.285118] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10674 11:17:17.297600 [ 2.293204] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10675 11:17:17.303652 [ 2.301288] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10676 11:17:17.313711 [ 2.309370] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10677 11:17:17.320974 [ 2.317452] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10678 11:17:17.327324 [ 2.325534] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10679 11:17:17.336953 [ 2.333617] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10680 11:17:17.343924 [ 2.341700] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10681 11:17:17.353829 [ 2.349782] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10682 11:17:17.359901 [ 2.357864] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10683 11:17:17.370457 [ 2.365946] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10684 11:17:17.376645 [ 2.374029] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10685 11:17:17.383524 [ 2.382708] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10686 11:17:17.389711 [ 2.389888] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10687 11:17:17.396647 [ 2.396720] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10688 11:17:17.403392 [ 2.403582] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10689 11:17:17.410473 [ 2.410649] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10690 11:17:17.420331 [ 2.417310] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10691 11:17:17.430252 [ 2.426190] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10692 11:17:17.440287 [ 2.435058] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10693 11:17:17.446977 [ 2.444099] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10694 11:17:17.457226 [ 2.453313] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10695 11:17:17.466766 [ 2.462528] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10696 11:17:17.477106 [ 2.471394] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10697 11:17:17.483364 [ 2.480606] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10698 11:17:17.493801 [ 2.489476] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10699 11:17:17.503218 [ 2.498521] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10700 11:17:17.513554 [ 2.508427] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10701 11:17:17.523358 [ 2.519569] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10702 11:17:17.529756 [ 2.529227] Trying to probe devices needed for running init ...
10703 11:17:17.578023 [ 2.578401] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10704 11:17:17.733936 [ 2.734380] hub 1-1:1.0: USB hub found
10705 11:17:17.737300 [ 2.738475] hub 1-1:1.0: 4 ports detected
10706 11:17:17.858029 [ 2.858503] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10707 11:17:17.887697 [ 2.888163] hub 2-1:1.0: USB hub found
10708 11:17:17.891982 [ 2.892398] hub 2-1:1.0: 3 ports detected
10709 11:17:18.057324 [ 3.054427] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
10710 11:17:18.188064 [ 3.188191] hub 1-1.1:1.0: USB hub found
10711 11:17:18.190986 [ 3.192213] hub 1-1.1:1.0: 4 ports detected
10712 11:17:18.305020 [ 3.302287] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk
10713 11:17:18.438286 [ 3.438339] hub 1-1.4:1.0: USB hub found
10714 11:17:18.441145 [ 3.442735] hub 1-1.4:1.0: 2 ports detected
10715 11:17:18.521275 [ 3.518431] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
10716 11:17:18.705491 [ 3.702429] usb 1-1.1.4: new full-speed USB device number 6 using xhci-mtk
10717 11:17:18.790123 [ 3.790634] usb 1-1.1.4: device descriptor read/64, error -32
10718 11:17:18.982673 [ 3.982641] usb 1-1.1.4: device descriptor read/64, error -32
10719 11:17:19.177073 [ 4.174430] usb 1-1.4.1: new high-speed USB device number 7 using xhci-mtk
10720 11:17:19.365031 [ 4.362429] usb 1-1.1.4: new full-speed USB device number 8 using xhci-mtk
10721 11:17:19.445962 [ 4.446517] usb 1-1.1.4: device descriptor read/64, error -32
10722 11:17:19.638224 [ 4.638642] usb 1-1.1.4: device descriptor read/64, error -32
10723 11:17:19.750686 [ 4.750874] usb 1-1.1-port4: attempt power cycle
10724 11:17:19.837353 [ 4.834428] usb 1-1.4.2: new high-speed USB device number 9 using xhci-mtk
10725 11:17:20.361093 [ 5.358437] usb 1-1.1.4: new full-speed USB device number 10 using xhci-mtk
10726 11:17:20.364827 [ 5.365620] usb 1-1.1.4: Device not responding to setup address.
10727 11:17:20.578102 [ 5.578699] usb 1-1.1.4: Device not responding to setup address.
10728 11:17:20.790300 [ 5.790447] usb 1-1.1.4: device not accepting address 10, error -71
10729 11:17:20.877016 [ 5.874429] usb 1-1.1.4: new full-speed USB device number 11 using xhci-mtk
10730 11:17:20.880479 [ 5.881618] usb 1-1.1.4: Device not responding to setup address.
10731 11:17:21.093908 [ 6.094692] usb 1-1.1.4: Device not responding to setup address.
10732 11:17:21.305982 [ 6.306419] usb 1-1.1.4: device not accepting address 11, error -71
10733 11:17:21.312590 [ 6.313245] usb 1-1.1-port4: unable to enumerate USB device
10734 11:17:29.814424 [ 14.819026] ALSA device list:
10735 11:17:29.818225 [ 14.822005] No soundcards found.
10736 11:17:29.827950 [ 14.829070] Freeing unused kernel memory: 8384K
10737 11:17:29.831225 [ 14.833788] Run /init as init process
10738 11:17:29.839510 Loading, please wait...
10739 11:17:29.856976 Starting version 247.3-7+deb11u2
10740 11:17:30.186257 [ 15.183889] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10741 11:17:30.194735 [ 15.195646] remoteproc remoteproc0: scp is available
10742 11:17:30.204124 [ 15.201879] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10743 11:17:30.214748 [ 15.208182] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10744 11:17:30.217268 [ 15.211504] remoteproc remoteproc0: powering up scp
10745 11:17:30.227493 [ 15.219371] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10746 11:17:30.233819 [ 15.222915] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10747 11:17:30.240666 [ 15.222939] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10748 11:17:30.250381 [ 15.222949] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10749 11:17:30.260318 [ 15.224305] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10750 11:17:30.266643 [ 15.232020] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10751 11:17:30.273703 [ 15.239322] remoteproc remoteproc0: request_firmware failed: -2
10752 11:17:30.279941 [ 15.264284] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10753 11:17:30.290249 [ 15.268523] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10754 11:17:30.293840 [ 15.280595] mc: Linux media interface: v0.10
10755 11:17:30.299977 [ 15.286923] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10756 11:17:30.307011 [ 15.296543] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10757 11:17:30.316317 [ 15.299096] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10758 11:17:30.322982 [ 15.311710] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10759 11:17:30.329846 [ 15.313965] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10760 11:17:30.336761 [ 15.325603] usbcore: registered new interface driver r8152
10761 11:17:30.342745 [ 15.328825] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10762 11:17:30.353087 [ 15.330363] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10763 11:17:30.356265 [ 15.331025] videodev: Linux video capture interface: v2.00
10764 11:17:30.367278 [ 15.337811] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10765 11:17:30.369899 [ 15.337811] Fallback method does not support PEC.
10766 11:17:30.377156 [ 15.339835] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10767 11:17:30.383296 [ 15.339843] pci_bus 0000:00: root bus resource [bus 00-ff]
10768 11:17:30.390031 [ 15.339849] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10769 11:17:30.400133 [ 15.339854] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10770 11:17:30.406701 [ 15.339885] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10771 11:17:30.412702 [ 15.339905] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10772 11:17:30.415887 [ 15.339983] pci 0000:00:00.0: supports D1 D2
10773 11:17:30.422693 [ 15.339987] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10774 11:17:30.429754 [ 15.341574] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10775 11:17:30.436475 [ 15.341699] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10776 11:17:30.443262 [ 15.341730] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10777 11:17:30.453143 [ 15.341750] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10778 11:17:30.459748 [ 15.341769] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10779 11:17:30.463355 [ 15.341883] pci 0000:01:00.0: supports D1 D2
10780 11:17:30.469508 [ 15.341886] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10781 11:17:30.476346 [ 15.344064] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10782 11:17:30.482993 [ 15.360673] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10783 11:17:30.493114 [ 15.363525] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10784 11:17:30.499553 [ 15.366578] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10785 11:17:30.509663 [ 15.377003] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10786 11:17:30.516622 [ 15.383220] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10787 11:17:30.522515 [ 15.383374] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10788 11:17:30.532403 [ 15.388742] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10789 11:17:30.538945 [ 15.395573] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10790 11:17:30.545457 [ 15.405244] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10791 11:17:30.555472 [ 15.411209] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10792 11:17:30.562577 [ 15.418453] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10793 11:17:30.572087 [ 15.419225] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10794 11:17:30.581789 [ 15.419614] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10795 11:17:30.588824 [ 15.422687] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10796 11:17:30.598667 [ 15.422693] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10797 11:17:30.605201 [ 15.422729] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10798 11:17:30.612372 [ 15.426581] usb 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
10799 11:17:30.618283 [ 15.429379] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10800 11:17:30.628870 [ 15.430271] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10801 11:17:30.638881 [ 15.450573] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10802 11:17:30.641647 [ 15.458157] usbcore: registered new interface driver cdc_ether
10803 11:17:30.648389 [ 15.458200] pci 0000:00:00.0: PCI bridge to [bus 01]
10804 11:17:30.654661 [ 15.458214] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10805 11:17:30.661861 [ 15.459373] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10806 11:17:30.668499 [ 15.460644] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10807 11:17:30.675052 [ 15.460828] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10808 11:17:30.678199 [ 15.485628] Bluetooth: Core ver 2.22
10809 11:17:30.684366 [ 15.486202] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10810 11:17:30.691002 [ 15.487188] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10811 11:17:30.704646 [ 15.488046] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10812 11:17:30.711608 [ 15.488209] usbcore: registered new interface driver uvcvideo
10813 11:17:30.717282 [ 15.498521] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10814 11:17:30.720748 [ 15.498624] usbcore: registered new interface driver r8153_ecm
10815 11:17:30.727547 [ 15.506910] NET: Registered PF_BLUETOOTH protocol family
10816 11:17:30.734694 [ 15.514863] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10817 11:17:30.740469 [ 15.515400] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10818 11:17:30.747402 [ 15.522417] Bluetooth: HCI device and connection manager initialized
10819 11:17:30.754172 [ 15.522439] Bluetooth: HCI socket layer initialized
10820 11:17:30.757219 [ 15.530275] cfg80211: failed to load regulatory.db
10821 11:17:30.764247 [ 15.537988] Bluetooth: L2CAP socket layer initialized
10822 11:17:30.770493 [ 15.558214] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10823 11:17:30.777205 [ 15.561388] Bluetooth: SCO socket layer initialized
10824 11:17:30.784138 [ 15.569114] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10825 11:17:30.793675 [ 15.623376] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10826 11:17:30.797438 [ 15.635758] usbcore: registered new interface driver btusb
10827 11:17:30.807202 [ 15.636352] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10828 11:17:30.813663 [ 15.636362] Bluetooth: hci0: Failed to load firmware file (-2)
10829 11:17:30.819819 [ 15.636367] Bluetooth: hci0: Failed to set up firmware (-2)
10830 11:17:30.829766 [ 15.636370] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10831 11:17:30.836651 [ 15.643645] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10832 11:17:30.840189 [ 15.690497] r8152 1-1.1.1:1.0 eth0: v1.12.13
10833 11:17:30.846832 [ 15.718190] mt7921e 0000:01:00.0: ASIC revision: 79610010
10834 11:17:30.849964 [ 15.730739] r8152 1-1.1.1:1.0 enxf4f5e850de0a: renamed from eth0
10835 11:17:30.862729 [ 15.825643] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10836 11:17:30.914238 Begin: Loading essential drivers ... done.
10837 11:17:30.917663 Begin: Running /scripts/init-premount ... done.
10838 11:17:30.924779 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10839 11:17:30.934586 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10840 11:17:30.937638 Device /sys/class/net/enxf4f5e850de0a found
10841 11:17:30.938200 done.
10842 11:17:30.982712 [ 15.977210] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10843 11:17:31.005047 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
10844 11:17:31.101648 [ 16.096116] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10845 11:17:31.217309 [ 16.211940] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10846 11:17:31.333334 [ 16.327977] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10847 11:17:31.449395 [ 16.443834] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10848 11:17:31.565164 [ 16.559755] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10849 11:17:31.681142 [ 16.675745] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10850 11:17:31.796978 [ 16.791664] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10851 11:17:31.912961 [ 16.907613] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10852 11:17:32.020093 [ 17.021545] mt7921e 0000:01:00.0: hardware init failed
10853 11:17:32.298585 IP-Config: no response after 2 secs - giving up
10854 11:17:32.352173 IP-Config: enxf4[ 17.350802] r8152 1-1.1.1:1.0 enxf4f5e850de0a: carrier on
10855 11:17:32.355540 f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
10856 11:17:33.457289 IP-Config: enxf4f5e850de0a complete (dhcp from 192.168.201.1):
10857 11:17:33.463871 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
10858 11:17:33.470559 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10859 11:17:33.477035 host : mt8192-asurada-spherion-r0-cbg-9
10860 11:17:33.483746 domain : lava-rack
10861 11:17:33.489792 rootserver: 192.168.201.1 rootpath:
10862 11:17:33.490661 filename :
10863 11:17:33.530700 done.
10864 11:17:33.534424 Begin: Running /scripts/nfs-bottom ... done.
10865 11:17:33.554820 Begin: Running /scripts/init-bottom ... done.
10866 11:17:34.644854 [ 19.647009] NET: Registered PF_INET6 protocol family
10867 11:17:34.652243 [ 19.653853] Segment Routing with IPv6
10868 11:17:34.655040 [ 19.657573] In-situ OAM (IOAM) with IPv6
10869 11:17:34.761752 [ 19.746970] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10870 11:17:34.768330 [ 19.770396] systemd[1]: Detected architecture arm64.
10871 11:17:34.786617
10872 11:17:34.789637 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10873 11:17:34.790062
10874 11:17:34.806348 [ 19.808296] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10875 11:17:35.340576 [ 20.339343] systemd[1]: Queued start job for default target Graphical Interface.
10876 11:17:35.365866 [ 20.367447] systemd[1]: Created slice system-getty.slice.
10877 11:17:35.372411 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10878 11:17:35.389073 [ 20.391086] systemd[1]: Created slice system-modprobe.slice.
10879 11:17:35.395618 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10880 11:17:35.413784 [ 20.415030] systemd[1]: Created slice system-serial\x2dgetty.slice.
10881 11:17:35.419803 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10882 11:17:35.437980 [ 20.439471] systemd[1]: Created slice User and Session Slice.
10883 11:17:35.444974 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10884 11:17:35.464821 [ 20.463006] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10885 11:17:35.471356 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10886 11:17:35.488033 [ 20.486531] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10887 11:17:35.494661 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10888 11:17:35.515807 [ 20.510561] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10889 11:17:35.521725 [ 20.522256] systemd[1]: Reached target Local Encrypted Volumes.
10890 11:17:35.528582 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10891 11:17:35.540877 [ 20.542778] systemd[1]: Reached target Paths.
10892 11:17:35.544560 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10893 11:17:35.560974 [ 20.562473] systemd[1]: Reached target Remote File Systems.
10894 11:17:35.567197 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10895 11:17:35.580437 [ 20.582430] systemd[1]: Reached target Slices.
10896 11:17:35.583826 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10897 11:17:35.601318 [ 20.602472] systemd[1]: Reached target Swap.
10898 11:17:35.604184 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10899 11:17:35.621120 [ 20.622776] systemd[1]: Listening on initctl Compatibility Named Pipe.
10900 11:17:35.630667 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10901 11:17:35.637385 [ 20.638011] systemd[1]: Listening on Journal Audit Socket.
10902 11:17:35.643950 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10903 11:17:35.658317 [ 20.659491] systemd[1]: Listening on Journal Socket (/dev/log).
10904 11:17:35.664485 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10905 11:17:35.681200 [ 20.682687] systemd[1]: Listening on Journal Socket.
10906 11:17:35.687703 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10907 11:17:35.701937 [ 20.703560] systemd[1]: Listening on Network Service Netlink Socket.
10908 11:17:35.711504 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10909 11:17:35.728288 [ 20.729421] systemd[1]: Listening on udev Control Socket.
10910 11:17:35.734018 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10911 11:17:35.748759 [ 20.750718] systemd[1]: Listening on udev Kernel Socket.
10912 11:17:35.755179 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10913 11:17:35.805004 [ 20.806583] systemd[1]: Mounting Huge Pages File System...
10914 11:17:35.811259 Mounting [0;1;39mHuge Pages File System[0m...
10915 11:17:35.827516 [ 20.828726] systemd[1]: Mounting POSIX Message Queue File System...
10916 11:17:35.833241 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10917 11:17:35.850712 [ 20.852809] systemd[1]: Mounting Kernel Debug File System...
10918 11:17:35.857343 Mounting [0;1;39mKernel Debug File System[0m...
10919 11:17:35.876193 [ 20.874638] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10920 11:17:35.889975 [ 20.888787] systemd[1]: Starting Create list of static device nodes for the current kernel...
10921 11:17:35.896643 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10922 11:17:35.915650 [ 20.917169] systemd[1]: Starting Load Kernel Module configfs...
10923 11:17:35.922067 Starting [0;1;39mLoad Kernel Module configfs[0m...
10924 11:17:35.938825 [ 20.940868] systemd[1]: Starting Load Kernel Module drm...
10925 11:17:35.945529 Starting [0;1;39mLoad Kernel Module drm[0m...
10926 11:17:35.962659 [ 20.964798] systemd[1]: Starting Load Kernel Module fuse...
10927 11:17:35.969385 Starting [0;1;39mLoad Kernel Module fuse[0m...
10928 11:17:36.002407 [ 21.004110] fuse: init (API version 7.37)
10929 11:17:36.012154 [ 21.009011] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10930 11:17:36.049324 [ 21.051040] systemd[1]: Starting Journal Service...
10931 11:17:36.052809 Starting [0;1;39mJournal Service[0m...
10932 11:17:36.076744 [ 21.078561] systemd[1]: Starting Load Kernel Modules...
10933 11:17:36.083221 Starting [0;1;39mLoad Kernel Modules[0m...
10934 11:17:36.102157 [ 21.101069] systemd[1]: Starting Remount Root and Kernel File Systems...
10935 11:17:36.108615 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10936 11:17:36.124030 [ 21.125792] systemd[1]: Starting Coldplug All udev Devices...
10937 11:17:36.130165 Starting [0;1;39mColdplug All udev Devices[0m...
10938 11:17:36.147800 [ 21.149794] systemd[1]: Mounted Huge Pages File System.
10939 11:17:36.154538 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10940 11:17:36.168963 [ 21.170760] systemd[1]: Mounted POSIX Message Queue File System.
10941 11:17:36.175340 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10942 11:17:36.193024 [ 21.194868] systemd[1]: Mounted Kernel Debug File System.
10943 11:17:36.199738 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10944 11:17:36.213120 [ 21.211329] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10945 11:17:36.222470 [ 21.221059] systemd[1]: Finished Create list of static device nodes for the current kernel.
10946 11:17:36.229394 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10947 11:17:36.248150 [ 21.246671] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10948 11:17:36.254976 [ 21.247435] systemd[1]: modprobe@configfs.service: Succeeded.
10949 11:17:36.261517 [ 21.261515] systemd[1]: Finished Load Kernel Module configfs.
10950 11:17:36.267715 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10951 11:17:36.282091 [ 21.283515] systemd[1]: modprobe@drm.service: Succeeded.
10952 11:17:36.288950 [ 21.289664] systemd[1]: Finished Load Kernel Module drm.
10953 11:17:36.295435 [ 21.290690] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10954 11:17:36.301948 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10955 11:17:36.318232 [ 21.319580] systemd[1]: modprobe@fuse.service: Succeeded.
10956 11:17:36.325470 [ 21.325601] systemd[1]: Finished Load Kernel Module fuse.
10957 11:17:36.331388 [ 21.327367] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10958 11:17:36.338815 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10959 11:17:36.354063 [ 21.355463] systemd[1]: Finished Load Kernel Modules.
10960 11:17:36.367267 [[0;32m OK [0m] Finished [0;1;39mLoad Kerne[ 21.364437] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10961 11:17:36.367821 l Modules[0m.
10962 11:17:36.382249 [ 21.383716] systemd[1]: Finished Remount Root and Kernel File Systems.
10963 11:17:36.392333 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10964 11:17:36.398389 [ 21.397604] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10965 11:17:36.420979 [ 21.423013] systemd[1]: Mounting FUSE Control File System...
10966 11:17:36.434255 Mounting [0;1;39mFUSE Control File Sys[ 21.432567] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10967 11:17:36.434724 tem[0m...
10968 11:17:36.451068 [ 21.452964] systemd[1]: Mounting Kernel Configuration File System...
10969 11:17:36.464780 Mounting [0;1;39mKerne[ 21.461905] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10970 11:17:36.468075 l Configuration File System[0m...
10971 11:17:36.489940 [ 21.487999] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10972 11:17:36.496623 [ 21.493055] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10973 11:17:36.506688 [ 21.496685] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10974 11:17:36.529071 [ 21.527685] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10975 11:17:36.535680 [ 21.531157] systemd[1]: Starting Load/Save Random Seed...
10976 11:17:36.539044 Starting [0;1;39mLoad/Save Random Seed[0m...
10977 11:17:36.559872 [ 21.561906] systemd[1]: Starting Apply Kernel Variables...
10978 11:17:36.566535 Starting [0;1;39mApply Kernel Variables[0m...
10979 11:17:36.584637 [ 21.586840] systemd[1]: Starting Create System Users...
10980 11:17:36.588354 Starting [0;1;39mCreate System Users[0m...
10981 11:17:36.606073 [ 21.608129] systemd[1]: Started Journal Service.
10982 11:17:36.613075 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10983 11:17:36.626764 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10984 11:17:36.657857 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File S[ 21.648308] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10985 11:17:36.658386 ystem[0m.
10986 11:17:36.664283 [ 21.664190] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10987 11:17:36.671733 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10988 11:17:36.697947 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10989 11:17:36.712486 See 'systemctl status systemd-udev-trigger.service' for details.
10990 11:17:36.729728 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10991 11:17:36.749162 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10992 11:17:36.793147 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10993 11:17:36.815031 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10994 11:17:36.847604 [ 21.846919] systemd-journald[293]: Received client request to flush runtime journal.
10995 11:17:36.881006 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10996 11:17:36.897099 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10997 11:17:36.912102 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10998 11:17:36.960548 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10999 11:17:38.228195 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
11000 11:17:38.264538 Starting [0;1;39mCreate Volatile Files and Directories[0m...
11001 11:17:38.292315 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
11002 11:17:38.389106 Starting [0;1;39mNetwork Service[0m...
11003 11:17:38.476678 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
11004 11:17:38.537173 Starting [0;1;39mNetwork Time Synchronization[0m...
11005 11:17:38.555700 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
11006 11:17:38.601425 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
11007 11:17:38.644768 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
11008 11:17:38.668469 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
11009 11:17:38.848307 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
11010 11:17:38.876340 [ 23.878480] remoteproc remoteproc0: powering up scp
11011 11:17:38.899558 [ 23.898548] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
11012 11:17:38.906203 [ 23.908358] remoteproc remoteproc0: request_firmware failed: -2
11013 11:17:38.915873 [ 23.914717] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
11014 11:17:39.085112 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11015 11:17:39.111010 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
11016 11:17:39.124432 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
11017 11:17:39.169640 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11018 11:17:39.184128 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11019 11:17:39.203574 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11020 11:17:39.210386 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11021 11:17:39.224398 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11022 11:17:39.911653 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
11023 11:17:40.248188 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
11024 11:17:40.269887 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
11025 11:17:40.290080 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11026 11:17:40.304305 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11027 11:17:40.325289 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11028 11:17:40.340766 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11029 11:17:40.356467 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11030 11:17:40.376111 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11031 11:17:40.420595 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11032 11:17:40.452828 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
11033 11:17:40.537443 Starting [0;1;39mUser Login Management[0m...
11034 11:17:40.664286 Starting [0;1;39mNetwork Name Resolution[0m...
11035 11:17:40.683271 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11036 11:17:40.767357 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
11037 11:17:40.781629 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11038 11:17:40.803678 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11039 11:17:41.327126 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
11040 11:17:41.348875 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
11041 11:17:41.367216 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
11042 11:17:41.396578 Starting [0;1;39mPermit User Sessions[0m...
11043 11:17:41.427316 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11044 11:17:41.473478 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11045 11:17:41.491407 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11046 11:17:41.512952 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11047 11:17:41.528917 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11048 11:17:41.544397 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11049 11:17:41.592054 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11050 11:17:41.627279 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11051 11:17:41.689173
11052 11:17:41.689722
11053 11:17:41.692627 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11054 11:17:41.693087
11055 11:17:41.696098 debian-bullseye-arm64 login: root (automatic login)
11056 11:17:41.696586
11057 11:17:41.696952
11058 11:17:41.987348 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Mon Jun 5 10:57:14 UTC 2023 aarch64
11059 11:17:41.987509
11060 11:17:41.993664 The programs included with the Debian GNU/Linux system are free software;
11061 11:17:42.000569 the exact distribution terms for each program are described in the
11062 11:17:42.003959 individual files in /usr/share/doc/*/copyright.
11063 11:17:42.004038
11064 11:17:42.011096 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11065 11:17:42.014258 permitted by applicable law.
11066 11:17:42.853922 Matched prompt #10: / #
11068 11:17:42.855032 Setting prompt string to ['/ #']
11069 11:17:42.855460 end: 2.2.5.1 login-action (duration 00:00:28) [common]
11071 11:17:42.856420 end: 2.2.5 auto-login-action (duration 00:00:28) [common]
11072 11:17:42.856897 start: 2.2.6 expect-shell-connection (timeout 00:03:39) [common]
11073 11:17:42.857253 Setting prompt string to ['/ #']
11074 11:17:42.857553 Forcing a shell prompt, looking for ['/ #']
11076 11:17:42.908311 / #
11077 11:17:42.908847 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11078 11:17:42.909236 Waiting using forced prompt support (timeout 00:02:30)
11079 11:17:42.914714
11080 11:17:42.915588 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11081 11:17:42.916073 start: 2.2.7 export-device-env (timeout 00:03:39) [common]
11083 11:17:43.017367 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10591250/extract-nfsrootfs-r0k0govq'
11084 11:17:43.023860 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10591250/extract-nfsrootfs-r0k0govq'
11086 11:17:43.125454 / # export NFS_SERVER_IP='192.168.201.1'
11087 11:17:43.131751 export NFS_SERVER_IP='192.168.201.1'
11088 11:17:43.132722 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11089 11:17:43.133283 end: 2.2 depthcharge-retry (duration 00:01:21) [common]
11090 11:17:43.133796 end: 2 depthcharge-action (duration 00:01:21) [common]
11091 11:17:43.134313 start: 3 lava-test-retry (timeout 00:07:57) [common]
11092 11:17:43.134806 start: 3.1 lava-test-shell (timeout 00:07:57) [common]
11093 11:17:43.135245 Using namespace: common
11095 11:17:43.236434 / # #
11096 11:17:43.237135 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11097 11:17:43.243044 #
11098 11:17:43.243932 Using /lava-10591250
11100 11:17:43.345332 / # export SHELL=/bin/bash
11101 11:17:43.351838 export SHELL=/bin/bash
11103 11:17:43.453552 / # . /lava-10591250/environment
11104 11:17:43.459954 . /lava-10591250/environment
11106 11:17:43.567136 / # /lava-10591250/bin/lava-test-runner /lava-10591250/0
11107 11:17:43.567781 Test shell timeout: 10s (minimum of the action and connection timeout)
11108 11:17:43.572946 /lava-10591250/bin/lava-test-runner /lava-10591250/0
11109 11:17:43.799032 + export TESTRUN_ID=0_timesync-off
11110 11:17:43.802160 + TESTRUN_ID=0_timesync-off
11111 11:17:43.805525 + cd /lava-10591250/0/tests/0_timesync-off
11112 11:17:43.809073 ++ cat uuid
11113 11:17:43.812561 + UUID=10591250_1.6.2.3.1
11114 11:17:43.812656 + set +x
11115 11:17:43.815330 <LAVA_SIGNAL_STARTRUN 0_timesync-off 10591250_1.6.2.3.1>
11116 11:17:43.815618 Received signal: <STARTRUN> 0_timesync-off 10591250_1.6.2.3.1
11117 11:17:43.815693 Starting test lava.0_timesync-off (10591250_1.6.2.3.1)
11118 11:17:43.815791 Skipping test definition patterns.
11119 11:17:43.818914 + systemctl stop systemd-timesyncd
11120 11:17:43.854145 + set +x
11121 11:17:43.857921 <LAVA_SIGNAL_ENDRUN 0_timesync-off 10591250_1.6.2.3.1>
11122 11:17:43.858249 Received signal: <ENDRUN> 0_timesync-off 10591250_1.6.2.3.1
11123 11:17:43.858397 Ending use of test pattern.
11124 11:17:43.858509 Ending test lava.0_timesync-off (10591250_1.6.2.3.1), duration 0.04
11126 11:17:43.914209 + export TESTRUN_ID=1_kselftest-arm64
11127 11:17:43.914653 + TESTRUN_ID=1_kselftest-arm64
11128 11:17:43.920595 + cd /lava-10591250/0/tests/1_kselftest-arm64
11129 11:17:43.921020 ++ cat uuid
11130 11:17:43.925567 + UUID=10591250_1.6.2.3.5
11131 11:17:43.925990 + set +x
11132 11:17:43.932157 <LAVA_SIGNAL_STARTRUN 1_kselftest-arm64 10591250_1.6.2.3.5>
11133 11:17:43.932867 Received signal: <STARTRUN> 1_kselftest-arm64 10591250_1.6.2.3.5
11134 11:17:43.933219 Starting test lava.1_kselftest-arm64 (10591250_1.6.2.3.5)
11135 11:17:43.933602 Skipping test definition patterns.
11136 11:17:43.935237 + cd ./automated/linux/kselftest/
11137 11:17:43.961582 + ./kselftest.sh -c arm64 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11138 11:17:43.995064 INFO: install_deps skipped
11139 11:17:44.109008 --2023-06-05 11:17:44-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11140 11:17:44.115553 Resolving storage.kernelci.org (storage.kernelci.org)... 52.250.1.28
11141 11:17:44.257459 Connecting to storage.kernelci.org (storage.kernelci.org)|52.250.1.28|:80... connected.
11142 11:17:44.403883 HTTP request sent, awaiting response... 200 OK
11143 11:17:44.407213 Length: 2714204 (2.6M) [application/octet-stream]
11144 11:17:44.410686 Saving to: 'kselftest.tar.xz'
11145 11:17:44.410926
11146 11:17:44.411062
11147 11:17:44.699668 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11148 11:17:44.994527 kselftest.tar.xz 1%[ ] 46.39K 158KB/s
11149 11:17:45.337696 kselftest.tar.xz 8%[> ] 216.08K 367KB/s
11150 11:17:45.640037 kselftest.tar.xz 31%[=====> ] 826.96K 887KB/s
11151 11:17:45.744445 kselftest.tar.xz 74%[=============> ] 1.94M 1.57MB/s
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11153 11:17:45.751332
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11155 11:17:45.985670
11156 11:17:50.731247 skiplist:
11157 11:17:50.734499 ========================================
11158 11:17:50.738380 ========================================
11159 11:17:50.771828 arm64:tags_test
11160 11:17:50.775255 arm64:run_tags_test.sh
11161 11:17:50.775335 arm64:fake_sigreturn_bad_magic
11162 11:17:50.778834 arm64:fake_sigreturn_bad_size
11163 11:17:50.781693 arm64:fake_sigreturn_bad_size_for_magic0
11164 11:17:50.784940 arm64:fake_sigreturn_duplicated_fpsimd
11165 11:17:50.788260 arm64:fake_sigreturn_misaligned_sp
11166 11:17:50.791462 arm64:fake_sigreturn_missing_fpsimd
11167 11:17:50.795201 arm64:fake_sigreturn_sme_change_vl
11168 11:17:50.798500 arm64:fake_sigreturn_sve_change_vl
11169 11:17:50.801478 arm64:mangle_pstate_invalid_compat_toggle
11170 11:17:50.804797 arm64:mangle_pstate_invalid_daif_bits
11171 11:17:50.808298 arm64:mangle_pstate_invalid_mode_el1h
11172 11:17:50.811551 arm64:mangle_pstate_invalid_mode_el1t
11173 11:17:50.814610 arm64:mangle_pstate_invalid_mode_el2h
11174 11:17:50.817998 arm64:mangle_pstate_invalid_mode_el2t
11175 11:17:50.821358 arm64:mangle_pstate_invalid_mode_el3h
11176 11:17:50.828204 arm64:mangle_pstate_invalid_mode_el3t
11177 11:17:50.828308 arm64:sme_trap_no_sm
11178 11:17:50.831404 arm64:sme_trap_non_streaming
11179 11:17:50.831486 arm64:sme_trap_za
11180 11:17:50.834598 arm64:sme_vl
11181 11:17:50.834685 arm64:ssve_regs
11182 11:17:50.838242 arm64:sve_regs
11183 11:17:50.838663 arm64:sve_vl
11184 11:17:50.838995 arm64:za_no_regs
11185 11:17:50.841333 arm64:za_regs
11186 11:17:50.841845 arm64:pac
11187 11:17:50.844812 arm64:fp-stress
11188 11:17:50.845235 arm64:sve-ptrace
11189 11:17:50.848024 arm64:sve-probe-vls
11190 11:17:50.848561 arm64:vec-syscfg
11191 11:17:50.848930 arm64:za-fork
11192 11:17:50.851413 arm64:za-ptrace
11193 11:17:50.855415 arm64:check_buffer_fill
11194 11:17:50.855960 arm64:check_child_memory
11195 11:17:50.857831 arm64:check_gcr_el1_cswitch
11196 11:17:50.861349 arm64:check_ksm_options
11197 11:17:50.861771 arm64:check_mmap_options
11198 11:17:50.864578 arm64:check_prctl
11199 11:17:50.867706 arm64:check_tags_inclusion
11200 11:17:50.868132 arm64:check_user_mem
11201 11:17:50.871387 arm64:btitest
11202 11:17:50.871888 arm64:nobtitest
11203 11:17:50.872361 arm64:hwcap
11204 11:17:50.874373 arm64:ptrace
11205 11:17:50.874794 arm64:syscall-abi
11206 11:17:50.877464 arm64:tpidr2
11207 11:17:50.881097 ============== Tests to run ===============
11208 11:17:50.881184 arm64:tags_test
11209 11:17:50.883825 arm64:run_tags_test.sh
11210 11:17:50.887404 arm64:fake_sigreturn_bad_magic
11211 11:17:50.890264 arm64:fake_sigreturn_bad_size
11212 11:17:50.893959 arm64:fake_sigreturn_bad_size_for_magic0
11213 11:17:50.897115 arm64:fake_sigreturn_duplicated_fpsimd
11214 11:17:50.900648 arm64:fake_sigreturn_misaligned_sp
11215 11:17:50.903646 arm64:fake_sigreturn_missing_fpsimd
11216 11:17:50.907631 arm64:fake_sigreturn_sme_change_vl
11217 11:17:50.910282 arm64:fake_sigreturn_sve_change_vl
11218 11:17:50.913829 arm64:mangle_pstate_invalid_compat_toggle
11219 11:17:50.916833 arm64:mangle_pstate_invalid_daif_bits
11220 11:17:50.920288 arm64:mangle_pstate_invalid_mode_el1h
11221 11:17:50.923498 arm64:mangle_pstate_invalid_mode_el1t
11222 11:17:50.926706 arm64:mangle_pstate_invalid_mode_el2h
11223 11:17:50.930187 arm64:mangle_pstate_invalid_mode_el2t
11224 11:17:50.933429 arm64:mangle_pstate_invalid_mode_el3h
11225 11:17:50.936887 arm64:mangle_pstate_invalid_mode_el3t
11226 11:17:50.936967 arm64:sme_trap_no_sm
11227 11:17:50.939881 arm64:sme_trap_non_streaming
11228 11:17:50.943850 arm64:sme_trap_za
11229 11:17:50.943930 arm64:sme_vl
11230 11:17:50.943994 arm64:ssve_regs
11231 11:17:50.946853 arm64:sve_regs
11232 11:17:50.946934 arm64:sve_vl
11233 11:17:50.950313 arm64:za_no_regs
11234 11:17:50.950438 arm64:za_regs
11235 11:17:50.950543 arm64:pac
11236 11:17:50.953422 arm64:fp-stress
11237 11:17:50.953504 arm64:sve-ptrace
11238 11:17:50.956501 arm64:sve-probe-vls
11239 11:17:50.956629 arm64:vec-syscfg
11240 11:17:50.959948 arm64:za-fork
11241 11:17:50.960034 arm64:za-ptrace
11242 11:17:50.962960 arm64:check_buffer_fill
11243 11:17:50.966809 arm64:check_child_memory
11244 11:17:50.966916 arm64:check_gcr_el1_cswitch
11245 11:17:50.970453 arm64:check_ksm_options
11246 11:17:50.973656 arm64:check_mmap_options
11247 11:17:50.974069 arm64:check_prctl
11248 11:17:50.976623 arm64:check_tags_inclusion
11249 11:17:50.977037 arm64:check_user_mem
11250 11:17:50.980016 arm64:btitest
11251 11:17:50.980428 arm64:nobtitest
11252 11:17:50.983459 arm64:hwcap
11253 11:17:50.983873 arm64:ptrace
11254 11:17:50.987025 arm64:syscall-abi
11255 11:17:50.987561 arm64:tpidr2
11256 11:17:50.989913 ===========End Tests to run ===============
11257 11:17:51.177378 [ 36.181168] kselftest: Running tests in arm64
11258 11:17:51.186195 TAP version 13
11259 11:17:51.198732 1..48
11260 11:17:51.216078 # selftests: arm64: tags_test
11261 11:17:51.578617 ok 1 selftests: arm64: tags_test
11262 11:17:51.592071 # selftests: arm64: run_tags_test.sh
11263 11:17:51.646812 # --------------------
11264 11:17:51.649693 # running tags test
11265 11:17:51.650155 # --------------------
11266 11:17:51.653085 # [PASS]
11267 11:17:51.656457 ok 2 selftests: arm64: run_tags_test.sh
11268 11:17:51.668109 # selftests: arm64: fake_sigreturn_bad_magic
11269 11:17:51.718563 # Registered handlers for all signals.
11270 11:17:51.719157 # Detected MINSTKSIGSZ:4720
11271 11:17:51.721893 # Testcase initialized.
11272 11:17:51.724889 # uc context validated.
11273 11:17:51.728249 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11274 11:17:51.731523 # Handled SIG_COPYCTX
11275 11:17:51.731976 # Available space:3568
11276 11:17:51.738004 # Using badly built context - ERR: BAD MAGIC !
11277 11:17:51.744873 # SIG_OK -- SP:0xFFFFD4892790 si_addr@:0xffffd4892790 si_code:2 token@:0xffffd4891530 offset:-4704
11278 11:17:51.748592 # ==>> completed. PASS(1)
11279 11:17:51.754782 # # FAKE_SIGRETURN_BAD_MAGIC :: Trigger a sigreturn with a sigframe with a bad magic
11280 11:17:51.761594 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD4891530
11281 11:17:51.768035 ok 3 selftests: arm64: fake_sigreturn_bad_magic
11282 11:17:51.771216 # selftests: arm64: fake_sigreturn_bad_size
11283 11:17:51.784803 # Registered handlers for all signals.
11284 11:17:51.785404 # Detected MINSTKSIGSZ:4720
11285 11:17:51.788000 # Testcase initialized.
11286 11:17:51.791461 # uc context validated.
11287 11:17:51.794583 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11288 11:17:51.798062 # Handled SIG_COPYCTX
11289 11:17:51.798776 # Available space:3568
11290 11:17:51.800905 # uc context validated.
11291 11:17:51.807690 # Using badly built context - ERR: Bad size for esr_context
11292 11:17:51.814345 # SIG_OK -- SP:0xFFFFEFFFDED0 si_addr@:0xffffefffded0 si_code:2 token@:0xffffefffcc70 offset:-4704
11293 11:17:51.818057 # ==>> completed. PASS(1)
11294 11:17:51.824297 # # FAKE_SIGRETURN_BAD_SIZE :: Triggers a sigreturn with a overrun __reserved area
11295 11:17:51.831104 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFEFFFCC70
11296 11:17:51.834819 ok 4 selftests: arm64: fake_sigreturn_bad_size
11297 11:17:51.840679 # selftests: arm64: fake_sigreturn_bad_size_for_magic0
11298 11:17:51.856475 # Registered handlers for all signals.
11299 11:17:51.857084 # Detected MINSTKSIGSZ:4720
11300 11:17:51.859250 # Testcase initialized.
11301 11:17:51.862621 # uc context validated.
11302 11:17:51.866036 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11303 11:17:51.869172 # Handled SIG_COPYCTX
11304 11:17:51.869628 # Available space:3568
11305 11:17:51.875769 # Using badly built context - ERR: Bad size for terminator
11306 11:17:51.886020 # SIG_OK -- SP:0xFFFFD60A6220 si_addr@:0xffffd60a6220 si_code:2 token@:0xffffd60a4fc0 offset:-4704
11307 11:17:51.886480 # ==>> completed. PASS(1)
11308 11:17:51.895637 # # FAKE_SIGRETURN_BAD_SIZE_FOR_TERMINATOR :: Trigger a sigreturn using non-zero size terminator
11309 11:17:51.902318 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFD60A4FC0
11310 11:17:51.905252 ok 5 selftests: arm64: fake_sigreturn_bad_size_for_magic0
11311 11:17:51.912085 # selftests: arm64: fake_sigreturn_duplicated_fpsimd
11312 11:17:51.923834 # Registered handlers for all signals.
11313 11:17:51.924438 # Detected MINSTKSIGSZ:4720
11314 11:17:51.926995 # Testcase initialized.
11315 11:17:51.930453 # uc context validated.
11316 11:17:51.934089 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11317 11:17:51.937247 # Handled SIG_COPYCTX
11318 11:17:51.937708 # Available space:3568
11319 11:17:51.943546 # Using badly built context - ERR: Multiple FPSIMD_MAGIC
11320 11:17:51.953480 # SIG_OK -- SP:0xFFFFEBC79410 si_addr@:0xffffebc79410 si_code:2 token@:0xffffebc781b0 offset:-4704
11321 11:17:51.953945 # ==>> completed. PASS(1)
11322 11:17:51.963394 # # FAKE_SIGRETURN_DUPLICATED_FPSIMD :: Triggers a sigreturn including two fpsimd_context
11323 11:17:51.970628 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFEBC781B0
11324 11:17:51.973328 ok 6 selftests: arm64: fake_sigreturn_duplicated_fpsimd
11325 11:17:51.977036 # selftests: arm64: fake_sigreturn_misaligned_sp
11326 11:17:51.995987 # Registered handlers for all signals.
11327 11:17:51.996621 # Detected MINSTKSIGSZ:4720
11328 11:17:51.999014 # Testcase initialized.
11329 11:17:52.002476 # uc context validated.
11330 11:17:52.005959 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11331 11:17:52.009277 # Handled SIG_COPYCTX
11332 11:17:52.015759 # SIG_OK -- SP:0xFFFFEBEB29B3 si_addr@:0xffffebeb29b3 si_code:2 token@:0xffffebeb29b3 offset:0
11333 11:17:52.019154 # ==>> completed. PASS(1)
11334 11:17:52.025646 # # FAKE_SIGRETURN_MISALIGNED_SP :: Triggers a sigreturn with a misaligned sigframe
11335 11:17:52.031975 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFEBEB29B3
11336 11:17:52.038861 ok 7 selftests: arm64: fake_sigreturn_misaligned_sp
11337 11:17:52.041983 # selftests: arm64: fake_sigreturn_missing_fpsimd
11338 11:17:52.069317 # Registered handlers for all signals.
11339 11:17:52.069948 # Detected MINSTKSIGSZ:4720
11340 11:17:52.073064 # Testcase initialized.
11341 11:17:52.075776 # uc context validated.
11342 11:17:52.079204 # 4560 byte GOOD CONTEXT grabbed from sig_copyctx handler
11343 11:17:52.082818 # Handled SIG_COPYCTX
11344 11:17:52.086113 # Mangling template header. Spare space:4096
11345 11:17:52.089201 # Using badly built context - ERR: Missing FPSIMD
11346 11:17:52.098883 # SIG_OK -- SP:0xFFFFC7418D50 si_addr@:0xffffc7418d50 si_code:2 token@:0xffffc7417af0 offset:-4704
11347 11:17:52.102011 # ==>> completed. PASS(1)
11348 11:17:52.108897 # # FAKE_SIGRETURN_MISSING_FPSIMD :: Triggers a sigreturn with a missing fpsimd_context
11349 11:17:52.115351 # Calling sigreturn with fake sigframe sized:4688 at SP @FFFFC7417AF0
11350 11:17:52.119085 ok 8 selftests: arm64: fake_sigreturn_missing_fpsimd
11351 11:17:52.125189 # selftests: arm64: fake_sigreturn_sme_change_vl
11352 11:17:52.137235 # Registered handlers for all signals.
11353 11:17:52.137787 # Detected MINSTKSIGSZ:4720
11354 11:17:52.140412 # ==>> completed. SKIP.
11355 11:17:52.148014 # # FAKE_SIGRETURN_SSVE_CHANGE :: Attempt to change Streaming SVE VL
11356 11:17:52.150454 ok 9 selftests: arm64: fake_sigreturn_sme_change_vl # SKIP
11357 11:17:52.156974 # selftests: arm64: fake_sigreturn_sve_change_vl
11358 11:17:52.202328 # Registered handlers for all signals.
11359 11:17:52.202521 # Detected MINSTKSIGSZ:4720
11360 11:17:52.205339 # ==>> completed. SKIP.
11361 11:17:52.211971 # # FAKE_SIGRETURN_SVE_CHANGE :: Attempt to change SVE VL
11362 11:17:52.215009 ok 10 selftests: arm64: fake_sigreturn_sve_change_vl # SKIP
11363 11:17:52.221755 # selftests: arm64: mangle_pstate_invalid_compat_toggle
11364 11:17:52.264368 # Registered handlers for all signals.
11365 11:17:52.264513 # Detected MINSTKSIGSZ:4720
11366 11:17:52.267800 # Testcase initialized.
11367 11:17:52.271131 # uc context validated.
11368 11:17:52.271214 # Handled SIG_TRIG
11369 11:17:52.280876 # SIG_OK -- SP:0xFFFFF348AF10 si_addr@:0xfffff348af10 si_code:2 token@:(nil) offset:-281474763370256
11370 11:17:52.283836 # ==>> completed. PASS(1)
11371 11:17:52.291147 # # MANGLE_PSTATE_INVALID_STATE_TOGGLE :: Mangling uc_mcontext with INVALID STATE_TOGGLE
11372 11:17:52.297114 ok 11 selftests: arm64: mangle_pstate_invalid_compat_toggle
11373 11:17:52.300721 # selftests: arm64: mangle_pstate_invalid_daif_bits
11374 11:17:52.328347 # Registered handlers for all signals.
11375 11:17:52.328512 # Detected MINSTKSIGSZ:4720
11376 11:17:52.332023 # Testcase initialized.
11377 11:17:52.334963 # uc context validated.
11378 11:17:52.335070 # Handled SIG_TRIG
11379 11:17:52.345199 # SIG_OK -- SP:0xFFFFC32CB8F0 si_addr@:0xffffc32cb8f0 si_code:2 token@:(nil) offset:-281473956231408
11380 11:17:52.348398 # ==>> completed. PASS(1)
11381 11:17:52.355246 # # MANGLE_PSTATE_INVALID_DAIF_BITS :: Mangling uc_mcontext with INVALID DAIF_BITS
11382 11:17:52.358295 ok 12 selftests: arm64: mangle_pstate_invalid_daif_bits
11383 11:17:52.364399 # selftests: arm64: mangle_pstate_invalid_mode_el1h
11384 11:17:52.400116 # Registered handlers for all signals.
11385 11:17:52.400447 # Detected MINSTKSIGSZ:4720
11386 11:17:52.403013 # Testcase initialized.
11387 11:17:52.406143 # uc context validated.
11388 11:17:52.406416 # Handled SIG_TRIG
11389 11:17:52.416264 # SIG_OK -- SP:0xFFFFD0E563C0 si_addr@:0xffffd0e563c0 si_code:2 token@:(nil) offset:-281474186437568
11390 11:17:52.419374 # ==>> completed. PASS(1)
11391 11:17:52.426194 # # MANGLE_PSTATE_INVALID_MODE_EL1h :: Mangling uc_mcontext INVALID MODE EL1h
11392 11:17:52.429822 ok 13 selftests: arm64: mangle_pstate_invalid_mode_el1h
11393 11:17:52.436064 # selftests: arm64: mangle_pstate_invalid_mode_el1t
11394 11:17:52.464869 # Registered handlers for all signals.
11395 11:17:52.465414 # Detected MINSTKSIGSZ:4720
11396 11:17:52.468250 # Testcase initialized.
11397 11:17:52.471737 # uc context validated.
11398 11:17:52.472455 # Handled SIG_TRIG
11399 11:17:52.481803 # SIG_OK -- SP:0xFFFFE7E9D5A0 si_addr@:0xffffe7e9d5a0 si_code:2 token@:(nil) offset:-281474572604832
11400 11:17:52.484253 # ==>> completed. PASS(1)
11401 11:17:52.491900 # # MANGLE_PSTATE_INVALID_MODE_EL1t :: Mangling uc_mcontext INVALID MODE EL1t
11402 11:17:52.495111 ok 14 selftests: arm64: mangle_pstate_invalid_mode_el1t
11403 11:17:52.501134 # selftests: arm64: mangle_pstate_invalid_mode_el2h
11404 11:17:52.531677 # Registered handlers for all signals.
11405 11:17:52.532253 # Detected MINSTKSIGSZ:4720
11406 11:17:52.535141 # Testcase initialized.
11407 11:17:52.538503 # uc context validated.
11408 11:17:52.538987 # Handled SIG_TRIG
11409 11:17:52.548422 # SIG_OK -- SP:0xFFFFFE45BB00 si_addr@:0xfffffe45bb00 si_code:2 token@:(nil) offset:-281474947726080
11410 11:17:52.551175 # ==>> completed. PASS(1)
11411 11:17:52.558118 # # MANGLE_PSTATE_INVALID_MODE_EL2h :: Mangling uc_mcontext INVALID MODE EL2h
11412 11:17:52.561533 ok 15 selftests: arm64: mangle_pstate_invalid_mode_el2h
11413 11:17:52.568286 # selftests: arm64: mangle_pstate_invalid_mode_el2t
11414 11:17:52.600047 # Registered handlers for all signals.
11415 11:17:52.600629 # Detected MINSTKSIGSZ:4720
11416 11:17:52.603778 # Testcase initialized.
11417 11:17:52.606840 # uc context validated.
11418 11:17:52.607304 # Handled SIG_TRIG
11419 11:17:52.616840 # SIG_OK -- SP:0xFFFFCBF22240 si_addr@:0xffffcbf22240 si_code:2 token@:(nil) offset:-281474103386688
11420 11:17:52.620573 # ==>> completed. PASS(1)
11421 11:17:52.626815 # # MANGLE_PSTATE_INVALID_MODE_EL2t :: Mangling uc_mcontext INVALID MODE EL2t
11422 11:17:52.630226 ok 16 selftests: arm64: mangle_pstate_invalid_mode_el2t
11423 11:17:52.636573 # selftests: arm64: mangle_pstate_invalid_mode_el3h
11424 11:17:52.668840 # Registered handlers for all signals.
11425 11:17:52.669396 # Detected MINSTKSIGSZ:4720
11426 11:17:52.672376 # Testcase initialized.
11427 11:17:52.675362 # uc context validated.
11428 11:17:52.676051 # Handled SIG_TRIG
11429 11:17:52.685214 # SIG_OK -- SP:0xFFFFEE025EA0 si_addr@:0xffffee025ea0 si_code:2 token@:(nil) offset:-281474674876064
11430 11:17:52.688827 # ==>> completed. PASS(1)
11431 11:17:52.695081 # # MANGLE_PSTATE_INVALID_MODE_EL3h :: Mangling uc_mcontext INVALID MODE EL3h
11432 11:17:52.698760 ok 17 selftests: arm64: mangle_pstate_invalid_mode_el3h
11433 11:17:52.705947 # selftests: arm64: mangle_pstate_invalid_mode_el3t
11434 11:17:52.735690 # Registered handlers for all signals.
11435 11:17:52.736246 # Detected MINSTKSIGSZ:4720
11436 11:17:52.738980 # Testcase initialized.
11437 11:17:52.742243 # uc context validated.
11438 11:17:52.742853 # Handled SIG_TRIG
11439 11:17:52.752009 # SIG_OK -- SP:0xFFFFD77DD4C0 si_addr@:0xffffd77dd4c0 si_code:2 token@:(nil) offset:-281474297091264
11440 11:17:52.755999 # ==>> completed. PASS(1)
11441 11:17:52.762091 # # MANGLE_PSTATE_INVALID_MODE_EL3t :: Mangling uc_mcontext INVALID MODE EL3t
11442 11:17:52.765983 ok 18 selftests: arm64: mangle_pstate_invalid_mode_el3t
11443 11:17:52.768868 # selftests: arm64: sme_trap_no_sm
11444 11:17:52.804681 # Registered handlers for all signals.
11445 11:17:52.805224 # Detected MINSTKSIGSZ:4720
11446 11:17:52.807615 # ==>> completed. SKIP.
11447 11:17:52.817836 # # SME trap without SM :: Check that we get a SIGILL if we use streaming mode without enabling it
11448 11:17:52.820947 ok 19 selftests: arm64: sme_trap_no_sm # SKIP
11449 11:17:52.824117 # selftests: arm64: sme_trap_non_streaming
11450 11:17:52.872479 # Registered handlers for all signals.
11451 11:17:52.873079 # Detected MINSTKSIGSZ:4720
11452 11:17:52.875965 # ==>> completed. SKIP.
11453 11:17:52.885609 # # SME SM trap unsupported instruction :: Check that we get a SIGILL if we use an unsupported instruction in streaming mode
11454 11:17:52.892634 ok 20 selftests: arm64: sme_trap_non_streaming # SKIP
11455 11:17:52.895394 # selftests: arm64: sme_trap_za
11456 11:17:52.940825 # Registered handlers for all signals.
11457 11:17:52.941369 # Detected MINSTKSIGSZ:4720
11458 11:17:52.944194 # Testcase initialized.
11459 11:17:52.954033 # SIG_OK -- SP:0xFFFFC0840530 si_addr@:0xaaaad6b42510 si_code:1 token@:(nil) offset:-187650723292432
11460 11:17:52.954509 # ==>> completed. PASS(1)
11461 11:17:52.963950 # # SME ZA trap :: Check that we get a SIGILL if we access ZA without enabling
11462 11:17:52.967085 ok 21 selftests: arm64: sme_trap_za
11463 11:17:52.967554 # selftests: arm64: sme_vl
11464 11:17:53.008014 # Registered handlers for all signals.
11465 11:17:53.008673 # Detected MINSTKSIGSZ:4720
11466 11:17:53.010921 # ==>> completed. SKIP.
11467 11:17:53.017579 # # SME VL :: Check that we get the right SME VL reported
11468 11:17:53.020999 ok 22 selftests: arm64: sme_vl # SKIP
11469 11:17:53.024005 # selftests: arm64: ssve_regs
11470 11:17:53.076957 # Registered handlers for all signals.
11471 11:17:53.077576 # Detected MINSTKSIGSZ:4720
11472 11:17:53.079089 # ==>> completed. SKIP.
11473 11:17:53.086743 # # Streaming SVE registers :: Check that we get the right Streaming SVE registers reported
11474 11:17:53.092571 ok 23 selftests: arm64: ssve_regs # SKIP
11475 11:17:53.093043 # selftests: arm64: sve_regs
11476 11:17:53.145555 # Registered handlers for all signals.
11477 11:17:53.146109 # Detected MINSTKSIGSZ:4720
11478 11:17:53.148855 # ==>> completed. SKIP.
11479 11:17:53.155026 # # SVE registers :: Check that we get the right SVE registers reported
11480 11:17:53.158504 ok 24 selftests: arm64: sve_regs # SKIP
11481 11:17:53.161848 # selftests: arm64: sve_vl
11482 11:17:53.214460 # Registered handlers for all signals.
11483 11:17:53.214994 # Detected MINSTKSIGSZ:4720
11484 11:17:53.217497 # ==>> completed. SKIP.
11485 11:17:53.224178 # # SVE VL :: Check that we get the right SVE VL reported
11486 11:17:53.227559 ok 25 selftests: arm64: sve_vl # SKIP
11487 11:17:53.230769 # selftests: arm64: za_no_regs
11488 11:17:53.282381 # Registered handlers for all signals.
11489 11:17:53.282935 # Detected MINSTKSIGSZ:4720
11490 11:17:53.285030 # ==>> completed. SKIP.
11491 11:17:53.291329 # # ZA registers - ZA disabled :: Check ZA context with ZA disabled
11492 11:17:53.294648 ok 26 selftests: arm64: za_no_regs # SKIP
11493 11:17:53.297822 # selftests: arm64: za_regs
11494 11:17:53.349201 # Registered handlers for all signals.
11495 11:17:53.349749 # Detected MINSTKSIGSZ:4720
11496 11:17:53.352591 # ==>> completed. SKIP.
11497 11:17:53.359464 # # ZA register :: Check that we get the right ZA registers reported
11498 11:17:53.362639 ok 27 selftests: arm64: za_regs # SKIP
11499 11:17:53.365722 # selftests: arm64: pac
11500 11:17:53.413894 # TAP version 13
11501 11:17:53.414449 # 1..7
11502 11:17:53.417123 # # Starting 7 tests from 1 test cases.
11503 11:17:53.420580 # # RUN global.corrupt_pac ...
11504 11:17:53.423438 # # SKIP PAUTH not enabled
11505 11:17:53.427232 # # OK global.corrupt_pac
11506 11:17:53.430606 # ok 1 # SKIP PAUTH not enabled
11507 11:17:53.436987 # # RUN global.pac_instructions_not_nop ...
11508 11:17:53.440237 # # SKIP PAUTH not enabled
11509 11:17:53.443758 # # OK global.pac_instructions_not_nop
11510 11:17:53.447009 # ok 2 # SKIP PAUTH not enabled
11511 11:17:53.453539 # # RUN global.pac_instructions_not_nop_generic ...
11512 11:17:53.456808 # # SKIP Generic PAUTH not enabled
11513 11:17:53.460122 # # OK global.pac_instructions_not_nop_generic
11514 11:17:53.466669 # ok 3 # SKIP Generic PAUTH not enabled
11515 11:17:53.469977 # # RUN global.single_thread_different_keys ...
11516 11:17:53.472946 # # SKIP PAUTH not enabled
11517 11:17:53.480083 # # OK global.single_thread_different_keys
11518 11:17:53.480689 # ok 4 # SKIP PAUTH not enabled
11519 11:17:53.486262 # # RUN global.exec_changed_keys ...
11520 11:17:53.489762 # # SKIP PAUTH not enabled
11521 11:17:53.493199 # # OK global.exec_changed_keys
11522 11:17:53.496654 # ok 5 # SKIP PAUTH not enabled
11523 11:17:53.499666 # # RUN global.context_switch_keep_keys ...
11524 11:17:53.502921 # # SKIP PAUTH not enabled
11525 11:17:53.509642 # # OK global.context_switch_keep_keys
11526 11:17:53.512701 # ok 6 # SKIP PAUTH not enabled
11527 11:17:53.516683 # # RUN global.context_switch_keep_keys_generic ...
11528 11:17:53.519568 # # SKIP Generic PAUTH not enabled
11529 11:17:53.526071 # # OK global.context_switch_keep_keys_generic
11530 11:17:53.529365 # ok 7 # SKIP Generic PAUTH not enabled
11531 11:17:53.532740 # # PASSED: 7 / 7 tests passed.
11532 11:17:53.536082 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:7 error:0
11533 11:17:53.539964 ok 28 selftests: arm64: pac
11534 11:17:53.542337 # selftests: arm64: fp-stress
11535 11:18:01.042594 [ 46.050234] vpu: disabling
11536 11:18:01.045183 [ 46.053024] vproc2: disabling
11537 11:18:01.048694 [ 46.056034] vproc1: disabling
11538 11:18:01.052733 [ 46.059184] vaud18: disabling
11539 11:18:01.056008 [ 46.062345] vsram_others: disabling
11540 11:18:01.058965 [ 46.065959] va09: disabling
11541 11:18:01.062234 [ 46.068810] vsram_md: disabling
11542 11:18:01.065208 [ 46.072063] Vgpu: disabling
11543 11:18:03.500554 # TAP version 13
11544 11:18:03.501112 # 1..16
11545 11:18:03.504376 # # 8 CPUs, 0 SVE VLs, 0 SME VLs
11546 11:18:03.507015 # # Will run for 10s
11547 11:18:03.507569 # # Started FPSIMD-0-0
11548 11:18:03.510106 # # Started FPSIMD-0-1
11549 11:18:03.513168 # # Started FPSIMD-1-0
11550 11:18:03.513707 # # Started FPSIMD-1-1
11551 11:18:03.517090 # # Started FPSIMD-2-0
11552 11:18:03.517811 # # Started FPSIMD-2-1
11553 11:18:03.519776 # # Started FPSIMD-3-0
11554 11:18:03.523069 # # Started FPSIMD-3-1
11555 11:18:03.523759 # # Started FPSIMD-4-0
11556 11:18:03.526413 # # Started FPSIMD-4-1
11557 11:18:03.530748 # # Started FPSIMD-5-0
11558 11:18:03.531340 # # Started FPSIMD-5-1
11559 11:18:03.533281 # # Started FPSIMD-6-0
11560 11:18:03.536743 # # Started FPSIMD-6-1
11561 11:18:03.537201 # # Started FPSIMD-7-0
11562 11:18:03.539689 # # Started FPSIMD-7-1
11563 11:18:03.543241 # # FPSIMD-1-0: Vector length: 128 bits
11564 11:18:03.546201 # # FPSIMD-1-0: PID: 1135
11565 11:18:03.550196 # # FPSIMD-0-1: Vector length: 128 bits
11566 11:18:03.550626 # # FPSIMD-0-1: PID: 1134
11567 11:18:03.552836 # # FPSIMD-0-0: Vector length: 128 bits
11568 11:18:03.557127 # # FPSIMD-0-0: PID: 1133
11569 11:18:03.559643 # # FPSIMD-3-0: Vector length: 128 bits
11570 11:18:03.563007 # # FPSIMD-3-0: PID: 1139
11571 11:18:03.566625 # # FPSIMD-1-1: Vector length: 128 bits
11572 11:18:03.569391 # # FPSIMD-1-1: PID: 1136
11573 11:18:03.572909 # # FPSIMD-4-0: Vector length: 128 bits
11574 11:18:03.576686 # # FPSIMD-4-0: PID: 1141
11575 11:18:03.579508 # # FPSIMD-2-1: Vector length: 128 bits
11576 11:18:03.579933 # # FPSIMD-2-1: PID: 1138
11577 11:18:03.582646 # # FPSIMD-4-1: Vector length: 128 bits
11578 11:18:03.585745 # # FPSIMD-4-1: PID: 1142
11579 11:18:03.589421 # # FPSIMD-5-1: Vector length: 128 bits
11580 11:18:03.592382 # # FPSIMD-5-1: PID: 1144
11581 11:18:03.595801 # # FPSIMD-2-0: Vector length: 128 bits
11582 11:18:03.599111 # # FPSIMD-2-0: PID: 1137
11583 11:18:03.602499 # # FPSIMD-6-1: Vector length: 128 bits
11584 11:18:03.602918 # # FPSIMD-6-1: PID: 1146
11585 11:18:03.608982 # # FPSIMD-7-0: Vector length: 128 bits
11586 11:18:03.609399 # # FPSIMD-7-0: PID: 1147
11587 11:18:03.612318 # # FPSIMD-5-0: Vector length: 128 bits
11588 11:18:03.615752 # # FPSIMD-5-0: PID: 1143
11589 11:18:03.619364 # # FPSIMD-3-1: Vector length: 128 bits
11590 11:18:03.622623 # # FPSIMD-3-1: PID: 1140
11591 11:18:03.625640 # # FPSIMD-6-0: Vector length: 128 bits
11592 11:18:03.628905 # # FPSIMD-6-0: PID: 1145
11593 11:18:03.632196 # # FPSIMD-7-1: Vector length: 128 bits
11594 11:18:03.632795 # # FPSIMD-7-1: PID: 1148
11595 11:18:03.635758 # # Finishing up...
11596 11:18:03.642452 # # FPSIMD-0-0: Terminated by signal 15, no error, iterations=865058, signals=10
11597 11:18:03.649011 # # FPSIMD-0-1: Terminated by signal 15, no error, iterations=924824, signals=10
11598 11:18:03.655132 # # FPSIMD-2-0: Terminated by signal 15, no error, iterations=966425, signals=10
11599 11:18:03.665127 # # FPSIMD-3-0: Terminated by signal 15, no error, iterations=1139781, signals=10
11600 11:18:03.671530 # # FPSIMD-3-1: Terminated by signal 15, no error, iterations=912658, signals=10
11601 11:18:03.678397 # # FPSIMD-2-1: Terminated by signal 15, no error, iterations=1126327, signals=10
11602 11:18:03.684844 # # FPSIMD-5-1: Terminated by signal 15, no error, iterations=885729, signals=10
11603 11:18:03.688457 # ok 1 FPSIMD-0-0
11604 11:18:03.689020 # ok 2 FPSIMD-0-1
11605 11:18:03.691988 # ok 3 FPSIMD-1-0
11606 11:18:03.692509 # ok 4 FPSIMD-1-1
11607 11:18:03.695619 # ok 5 FPSIMD-2-0
11608 11:18:03.696130 # ok 6 FPSIMD-2-1
11609 11:18:03.698426 # ok 7 FPSIMD-3-0
11610 11:18:03.698977 # ok 8 FPSIMD-3-1
11611 11:18:03.701377 # ok 9 FPSIMD-4-0
11612 11:18:03.701839 # ok 10 FPSIMD-4-1
11613 11:18:03.704980 # ok 11 FPSIMD-5-0
11614 11:18:03.705398 # ok 12 FPSIMD-5-1
11615 11:18:03.707924 # ok 13 FPSIMD-6-0
11616 11:18:03.708340 # ok 14 FPSIMD-6-1
11617 11:18:03.711550 # ok 15 FPSIMD-7-0
11618 11:18:03.712092 # ok 16 FPSIMD-7-1
11619 11:18:03.717694 # # FPSIMD-6-0: Terminated by signal 15, no error, iterations=585501, signals=9
11620 11:18:03.728205 # # FPSIMD-5-0: Terminated by signal 15, no error, iterations=929301, signals=10
11621 11:18:03.734483 # # FPSIMD-4-1: Terminated by signal 15, no error, iterations=1382965, signals=10
11622 11:18:03.740774 # # FPSIMD-1-1: Terminated by signal 15, no error, iterations=363707, signals=10
11623 11:18:03.747378 # # FPSIMD-6-1: Terminated by signal 15, no error, iterations=1085225, signals=9
11624 11:18:03.754361 # # FPSIMD-4-0: Terminated by signal 15, no error, iterations=362158, signals=9
11625 11:18:03.761016 # # FPSIMD-7-1: Terminated by signal 15, no error, iterations=439345, signals=10
11626 11:18:03.770531 # # FPSIMD-1-0: Terminated by signal 15, no error, iterations=511335, signals=10
11627 11:18:03.777249 # # FPSIMD-7-0: Terminated by signal 15, no error, iterations=350328, signals=9
11628 11:18:03.780650 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:0 error:0
11629 11:18:03.783838 ok 29 selftests: arm64: fp-stress
11630 11:18:03.787511 # selftests: arm64: sve-ptrace
11631 11:18:03.787931 # TAP version 13
11632 11:18:03.790600 # 1..4104
11633 11:18:03.793836 # ok 2 # SKIP SVE not available
11634 11:18:03.797303 # # Planned tests != run tests (4104 != 1)
11635 11:18:03.800193 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11636 11:18:03.803711 ok 30 selftests: arm64: sve-ptrace # SKIP
11637 11:18:03.806889 # selftests: arm64: sve-probe-vls
11638 11:18:03.810126 # TAP version 13
11639 11:18:03.810564 # 1..2
11640 11:18:03.813664 # ok 2 # SKIP SVE not available
11641 11:18:03.816652 # # Planned tests != run tests (2 != 1)
11642 11:18:03.823716 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11643 11:18:03.826921 ok 31 selftests: arm64: sve-probe-vls # SKIP
11644 11:18:03.830161 # selftests: arm64: vec-syscfg
11645 11:18:03.830681 # TAP version 13
11646 11:18:03.831035 # 1..20
11647 11:18:03.833350 # ok 1 # SKIP SVE not supported
11648 11:18:03.836855 # ok 2 # SKIP SVE not supported
11649 11:18:03.839853 # ok 3 # SKIP SVE not supported
11650 11:18:03.843684 # ok 4 # SKIP SVE not supported
11651 11:18:03.846664 # ok 5 # SKIP SVE not supported
11652 11:18:03.847097 # ok 6 # SKIP SVE not supported
11653 11:18:03.850294 # ok 7 # SKIP SVE not supported
11654 11:18:03.853739 # ok 8 # SKIP SVE not supported
11655 11:18:03.856207 # ok 9 # SKIP SVE not supported
11656 11:18:03.860011 # ok 10 # SKIP SVE not supported
11657 11:18:03.863025 # ok 11 # SKIP SME not supported
11658 11:18:03.866235 # ok 12 # SKIP SME not supported
11659 11:18:03.869535 # ok 13 # SKIP SME not supported
11660 11:18:03.872989 # ok 14 # SKIP SME not supported
11661 11:18:03.876120 # ok 15 # SKIP SME not supported
11662 11:18:03.876563 # ok 16 # SKIP SME not supported
11663 11:18:03.879286 # ok 17 # SKIP SME not supported
11664 11:18:03.882403 # ok 18 # SKIP SME not supported
11665 11:18:03.886178 # ok 19 # SKIP SME not supported
11666 11:18:03.889363 # ok 20 # SKIP SME not supported
11667 11:18:03.895654 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:20 error:0
11668 11:18:03.898939 ok 32 selftests: arm64: vec-syscfg
11669 11:18:03.899448 # selftests: arm64: za-fork
11670 11:18:03.902017 # TAP version 13
11671 11:18:03.902429 # 1..1
11672 11:18:03.902753 # # PID: 1219
11673 11:18:03.905849 # # SME support not present
11674 11:18:03.908783 # ok 0 skipped
11675 11:18:03.911986 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11676 11:18:03.915553 ok 33 selftests: arm64: za-fork
11677 11:18:03.918550 # selftests: arm64: za-ptrace
11678 11:18:03.918967 # TAP version 13
11679 11:18:03.919381 # 1..1
11680 11:18:03.922451 # ok 2 # SKIP SME not available
11681 11:18:03.928246 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:1 error:0
11682 11:18:03.932000 ok 34 selftests: arm64: za-ptrace # SKIP
11683 11:18:03.935048 # selftests: arm64: check_buffer_fill
11684 11:18:03.938419 # # SKIP: MTE features unavailable
11685 11:18:03.941383 ok 35 selftests: arm64: check_buffer_fill # SKIP
11686 11:18:03.945077 # selftests: arm64: check_child_memory
11687 11:18:03.985092 # # SKIP: MTE features unavailable
11688 11:18:03.991820 ok 36 selftests: arm64: check_child_memory # SKIP
11689 11:18:04.007137 # selftests: arm64: check_gcr_el1_cswitch
11690 11:18:04.054268 # # SKIP: MTE features unavailable
11691 11:18:04.061124 ok 37 selftests: arm64: check_gcr_el1_cswitch # SKIP
11692 11:18:04.074842 # selftests: arm64: check_ksm_options
11693 11:18:04.121374 # # SKIP: MTE features unavailable
11694 11:18:04.128513 ok 38 selftests: arm64: check_ksm_options # SKIP
11695 11:18:04.142944 # selftests: arm64: check_mmap_options
11696 11:18:04.190726 # # SKIP: MTE features unavailable
11697 11:18:04.197464 ok 39 selftests: arm64: check_mmap_options # SKIP
11698 11:18:04.208451 # selftests: arm64: check_prctl
11699 11:18:04.259506 # TAP version 13
11700 11:18:04.260025 # 1..5
11701 11:18:04.263028 # ok 1 check_basic_read
11702 11:18:04.263444 # ok 2 NONE
11703 11:18:04.266041 # ok 3 # SKIP SYNC
11704 11:18:04.266457 # ok 4 # SKIP ASYNC
11705 11:18:04.269104 # ok 5 # SKIP SYNC+ASYNC
11706 11:18:04.272648 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:3 error:0
11707 11:18:04.275718 ok 40 selftests: arm64: check_prctl
11708 11:18:04.282261 # selftests: arm64: check_tags_inclusion
11709 11:18:04.325995 # # SKIP: MTE features unavailable
11710 11:18:04.333004 ok 41 selftests: arm64: check_tags_inclusion # SKIP
11711 11:18:04.344312 # selftests: arm64: check_user_mem
11712 11:18:04.392664 # # SKIP: MTE features unavailable
11713 11:18:04.399496 ok 42 selftests: arm64: check_user_mem # SKIP
11714 11:18:04.410774 # selftests: arm64: btitest
11715 11:18:04.459252 # TAP version 13
11716 11:18:04.459488 # 1..18
11717 11:18:04.462149 # # HWCAP_PACA not present
11718 11:18:04.465555 # # HWCAP2_BTI not present
11719 11:18:04.465810 # # Test binary built for BTI
11720 11:18:04.471898 # ok 1 nohint_func/call_using_br_x0 # SKIP
11721 11:18:04.475000 # ok 1 nohint_func/call_using_br_x16 # SKIP
11722 11:18:04.478424 # ok 1 nohint_func/call_using_blr # SKIP
11723 11:18:04.482777 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11724 11:18:04.485256 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11725 11:18:04.491998 # ok 1 bti_none_func/call_using_blr # SKIP
11726 11:18:04.495037 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11727 11:18:04.498820 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11728 11:18:04.501846 # ok 1 bti_c_func/call_using_blr # SKIP
11729 11:18:04.504963 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11730 11:18:04.508420 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11731 11:18:04.511997 # ok 1 bti_j_func/call_using_blr # SKIP
11732 11:18:04.515343 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11733 11:18:04.521690 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11734 11:18:04.525157 # ok 1 bti_jc_func/call_using_blr # SKIP
11735 11:18:04.528270 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11736 11:18:04.531591 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11737 11:18:04.534581 # ok 1 paciasp_func/call_using_blr # SKIP
11738 11:18:04.541264 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11739 11:18:04.544837 # # WARNING - EXPECTED TEST COUNT WRONG
11740 11:18:04.548359 ok 43 selftests: arm64: btitest
11741 11:18:04.551414 # selftests: arm64: nobtitest
11742 11:18:04.551954 # TAP version 13
11743 11:18:04.552369 # 1..18
11744 11:18:04.554712 # # HWCAP_PACA not present
11745 11:18:04.557633 # # HWCAP2_BTI not present
11746 11:18:04.560913 # # Test binary not built for BTI
11747 11:18:04.564449 # ok 1 nohint_func/call_using_br_x0 # SKIP
11748 11:18:04.568003 # ok 1 nohint_func/call_using_br_x16 # SKIP
11749 11:18:04.571168 # ok 1 nohint_func/call_using_blr # SKIP
11750 11:18:04.574201 # ok 1 bti_none_func/call_using_br_x0 # SKIP
11751 11:18:04.581112 # ok 1 bti_none_func/call_using_br_x16 # SKIP
11752 11:18:04.584074 # ok 1 bti_none_func/call_using_blr # SKIP
11753 11:18:04.587561 # ok 1 bti_c_func/call_using_br_x0 # SKIP
11754 11:18:04.591097 # ok 1 bti_c_func/call_using_br_x16 # SKIP
11755 11:18:04.594163 # ok 1 bti_c_func/call_using_blr # SKIP
11756 11:18:04.597740 # ok 1 bti_j_func/call_using_br_x0 # SKIP
11757 11:18:04.601336 # ok 1 bti_j_func/call_using_br_x16 # SKIP
11758 11:18:04.604198 # ok 1 bti_j_func/call_using_blr # SKIP
11759 11:18:04.611007 # ok 1 bti_jc_func/call_using_br_x0 # SKIP
11760 11:18:04.613838 # ok 1 bti_jc_func/call_using_br_x16 # SKIP
11761 11:18:04.617438 # ok 1 bti_jc_func/call_using_blr # SKIP
11762 11:18:04.620869 # ok 1 paciasp_func/call_using_br_x0 # SKIP
11763 11:18:04.623657 # ok 1 paciasp_func/call_using_br_x16 # SKIP
11764 11:18:04.627463 # ok 1 paciasp_func/call_using_blr # SKIP
11765 11:18:04.633682 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:18 error:0
11766 11:18:04.637426 # # WARNING - EXPECTED TEST COUNT WRONG
11767 11:18:04.640221 ok 44 selftests: arm64: nobtitest
11768 11:18:04.643738 # selftests: arm64: hwcap
11769 11:18:04.644254 # TAP version 13
11770 11:18:04.644634 # 1..28
11771 11:18:04.646945 # ok 1 cpuinfo_match_RNG
11772 11:18:04.650915 # # SIGILL reported for RNG
11773 11:18:04.653722 # ok 2 # SKIP sigill_RNG
11774 11:18:04.654139 # ok 3 cpuinfo_match_SME
11775 11:18:04.657205 # ok 4 sigill_SME
11776 11:18:04.657619 # ok 5 cpuinfo_match_SVE
11777 11:18:04.660271 # ok 6 sigill_SVE
11778 11:18:04.664261 # ok 7 cpuinfo_match_SVE 2
11779 11:18:04.664830 # # SIGILL reported for SVE 2
11780 11:18:04.666740 # ok 8 # SKIP sigill_SVE 2
11781 11:18:04.670492 # ok 9 cpuinfo_match_SVE AES
11782 11:18:04.673564 # # SIGILL reported for SVE AES
11783 11:18:04.676498 # ok 10 # SKIP sigill_SVE AES
11784 11:18:04.680298 # ok 11 cpuinfo_match_SVE2 PMULL
11785 11:18:04.683153 # # SIGILL reported for SVE2 PMULL
11786 11:18:04.683569 # ok 12 # SKIP sigill_SVE2 PMULL
11787 11:18:04.686580 # ok 13 cpuinfo_match_SVE2 BITPERM
11788 11:18:04.689575 # # SIGILL reported for SVE2 BITPERM
11789 11:18:04.692841 # ok 14 # SKIP sigill_SVE2 BITPERM
11790 11:18:04.696246 # ok 15 cpuinfo_match_SVE2 SHA3
11791 11:18:04.699874 # # SIGILL reported for SVE2 SHA3
11792 11:18:04.702678 # ok 16 # SKIP sigill_SVE2 SHA3
11793 11:18:04.706450 # ok 17 cpuinfo_match_SVE2 SM4
11794 11:18:04.709238 # # SIGILL reported for SVE2 SM4
11795 11:18:04.712863 # ok 18 # SKIP sigill_SVE2 SM4
11796 11:18:04.713383 # ok 19 cpuinfo_match_SVE2 I8MM
11797 11:18:04.716404 # # SIGILL reported for SVE2 I8MM
11798 11:18:04.719718 # ok 20 # SKIP sigill_SVE2 I8MM
11799 11:18:04.722849 # ok 21 cpuinfo_match_SVE2 F32MM
11800 11:18:04.725734 # # SIGILL reported for SVE2 F32MM
11801 11:18:04.728964 # ok 22 # SKIP sigill_SVE2 F32MM
11802 11:18:04.733044 # ok 23 cpuinfo_match_SVE2 F64MM
11803 11:18:04.736138 # # SIGILL reported for SVE2 F64MM
11804 11:18:04.739183 # ok 24 # SKIP sigill_SVE2 F64MM
11805 11:18:04.742346 # ok 25 cpuinfo_match_SVE2 BF16
11806 11:18:04.745964 # # SIGILL reported for SVE2 BF16
11807 11:18:04.746378 # ok 26 # SKIP sigill_SVE2 BF16
11808 11:18:04.749049 # ok 27 cpuinfo_match_SVE2 EBF16
11809 11:18:04.752330 # ok 28 # SKIP sigill_SVE2 EBF16
11810 11:18:04.759101 # # Totals: pass:16 fail:0 xfail:0 xpass:0 skip:12 error:0
11811 11:18:04.762077 ok 45 selftests: arm64: hwcap
11812 11:18:04.762497 # selftests: arm64: ptrace
11813 11:18:04.765620 # TAP version 13
11814 11:18:04.766032 # 1..7
11815 11:18:04.768813 # # Parent is 1448, child is 1449
11816 11:18:04.773377 # ok 1 read_tpidr_one
11817 11:18:04.773791 # ok 2 write_tpidr_one
11818 11:18:04.775401 # ok 3 verify_tpidr_one
11819 11:18:04.775818 # ok 4 count_tpidrs
11820 11:18:04.778692 # ok 5 tpidr2_write
11821 11:18:04.779231 # ok 6 tpidr2_read
11822 11:18:04.782088 # ok 7 write_tpidr_only
11823 11:18:04.788910 # # Totals: pass:7 fail:0 xfail:0 xpass:0 skip:0 error:0
11824 11:18:04.789428 ok 46 selftests: arm64: ptrace
11825 11:18:04.792132 # selftests: arm64: syscall-abi
11826 11:18:04.795110 # TAP version 13
11827 11:18:04.795524 # 1..2
11828 11:18:04.798657 # ok 1 getpid() FPSIMD
11829 11:18:04.799080 # ok 2 sched_yield() FPSIMD
11830 11:18:04.805367 # # Totals: pass:2 fail:0 xfail:0 xpass:0 skip:0 error:0
11831 11:18:04.808780 ok 47 selftests: arm64: syscall-abi
11832 11:18:04.811487 # selftests: arm64: tpidr2
11833 11:18:04.811904 # TAP version 13
11834 11:18:04.812235 # 1..5
11835 11:18:04.815245 # # PID: 1483
11836 11:18:04.815659 # # SME support not present
11837 11:18:04.821572 # ok 0 skipped, TPIDR2 not supported
11838 11:18:04.824659 # ok 1 skipped, TPIDR2 not supported
11839 11:18:04.828309 # ok 2 skipped, TPIDR2 not supported
11840 11:18:04.831485 # ok 3 skipped, TPIDR2 not supported
11841 11:18:04.834664 # ok 4 skipped, TPIDR2 not supported
11842 11:18:04.837849 # # Totals: pass:0 fail:0 xfail:0 xpass:0 skip:5 error:0
11843 11:18:04.841396 ok 48 selftests: arm64: tpidr2
11844 11:18:05.328793 arm64_tags_test pass
11845 11:18:05.332246 arm64_run_tags_test_sh pass
11846 11:18:05.336013 arm64_fake_sigreturn_bad_magic pass
11847 11:18:05.338592 arm64_fake_sigreturn_bad_size pass
11848 11:18:05.342483 arm64_fake_sigreturn_bad_size_for_magic0 pass
11849 11:18:05.345376 arm64_fake_sigreturn_duplicated_fpsimd pass
11850 11:18:05.348386 arm64_fake_sigreturn_misaligned_sp pass
11851 11:18:05.352270 arm64_fake_sigreturn_missing_fpsimd pass
11852 11:18:05.355382 arm64_fake_sigreturn_sme_change_vl skip
11853 11:18:05.361990 arm64_fake_sigreturn_sve_change_vl skip
11854 11:18:05.365688 arm64_mangle_pstate_invalid_compat_toggle pass
11855 11:18:05.368663 arm64_mangle_pstate_invalid_daif_bits pass
11856 11:18:05.371662 arm64_mangle_pstate_invalid_mode_el1h pass
11857 11:18:05.374895 arm64_mangle_pstate_invalid_mode_el1t pass
11858 11:18:05.378842 arm64_mangle_pstate_invalid_mode_el2h pass
11859 11:18:05.384891 arm64_mangle_pstate_invalid_mode_el2t pass
11860 11:18:05.388688 arm64_mangle_pstate_invalid_mode_el3h pass
11861 11:18:05.391533 arm64_mangle_pstate_invalid_mode_el3t pass
11862 11:18:05.394580 arm64_sme_trap_no_sm skip
11863 11:18:05.398301 arm64_sme_trap_non_streaming skip
11864 11:18:05.398793 arm64_sme_trap_za pass
11865 11:18:05.401267 arm64_sme_vl skip
11866 11:18:05.401689 arm64_ssve_regs skip
11867 11:18:05.404701 arm64_sve_regs skip
11868 11:18:05.405267 arm64_sve_vl skip
11869 11:18:05.407955 arm64_za_no_regs skip
11870 11:18:05.408560 arm64_za_regs skip
11871 11:18:05.411642 arm64_pac_PAUTH_not_enabled skip
11872 11:18:05.414822 arm64_pac_PAUTH_not_enabled skip
11873 11:18:05.417760 arm64_pac_Generic_PAUTH_not_enabled skip
11874 11:18:05.421413 arm64_pac_PAUTH_not_enabled skip
11875 11:18:05.424276 arm64_pac_PAUTH_not_enabled skip
11876 11:18:05.427811 arm64_pac_PAUTH_not_enabled skip
11877 11:18:05.431230 arm64_pac_Generic_PAUTH_not_enabled skip
11878 11:18:05.435137 arm64_pac pass
11879 11:18:05.435705 arm64_fp-stress_FPSIMD-0-0 pass
11880 11:18:05.437404 arm64_fp-stress_FPSIMD-0-1 pass
11881 11:18:05.441416 arm64_fp-stress_FPSIMD-1-0 pass
11882 11:18:05.444506 arm64_fp-stress_FPSIMD-1-1 pass
11883 11:18:05.448316 arm64_fp-stress_FPSIMD-2-0 pass
11884 11:18:05.450923 arm64_fp-stress_FPSIMD-2-1 pass
11885 11:18:05.454457 arm64_fp-stress_FPSIMD-3-0 pass
11886 11:18:05.455022 arm64_fp-stress_FPSIMD-3-1 pass
11887 11:18:05.457542 arm64_fp-stress_FPSIMD-4-0 pass
11888 11:18:05.460860 arm64_fp-stress_FPSIMD-4-1 pass
11889 11:18:05.464330 arm64_fp-stress_FPSIMD-5-0 pass
11890 11:18:05.467505 arm64_fp-stress_FPSIMD-5-1 pass
11891 11:18:05.470477 arm64_fp-stress_FPSIMD-6-0 pass
11892 11:18:05.473805 arm64_fp-stress_FPSIMD-6-1 pass
11893 11:18:05.476883 arm64_fp-stress_FPSIMD-7-0 pass
11894 11:18:05.477350 arm64_fp-stress_FPSIMD-7-1 pass
11895 11:18:05.480863 arm64_fp-stress pass
11896 11:18:05.484054 arm64_sve-ptrace_SVE_not_available skip
11897 11:18:05.487004 arm64_sve-ptrace skip
11898 11:18:05.490586 arm64_sve-probe-vls_SVE_not_available skip
11899 11:18:05.493485 arm64_sve-probe-vls skip
11900 11:18:05.496989 arm64_vec-syscfg_SVE_not_supported skip
11901 11:18:05.500157 arm64_vec-syscfg_SVE_not_supported skip
11902 11:18:05.503795 arm64_vec-syscfg_SVE_not_supported skip
11903 11:18:05.507043 arm64_vec-syscfg_SVE_not_supported skip
11904 11:18:05.510252 arm64_vec-syscfg_SVE_not_supported skip
11905 11:18:05.513866 arm64_vec-syscfg_SVE_not_supported skip
11906 11:18:05.517080 arm64_vec-syscfg_SVE_not_supported skip
11907 11:18:05.520277 arm64_vec-syscfg_SVE_not_supported skip
11908 11:18:05.523466 arm64_vec-syscfg_SVE_not_supported skip
11909 11:18:05.526775 arm64_vec-syscfg_SVE_not_supported skip
11910 11:18:05.530090 arm64_vec-syscfg_SME_not_supported skip
11911 11:18:05.534107 arm64_vec-syscfg_SME_not_supported skip
11912 11:18:05.539737 arm64_vec-syscfg_SME_not_supported skip
11913 11:18:05.543486 arm64_vec-syscfg_SME_not_supported skip
11914 11:18:05.546769 arm64_vec-syscfg_SME_not_supported skip
11915 11:18:05.549727 arm64_vec-syscfg_SME_not_supported skip
11916 11:18:05.553069 arm64_vec-syscfg_SME_not_supported skip
11917 11:18:05.556684 arm64_vec-syscfg_SME_not_supported skip
11918 11:18:05.559864 arm64_vec-syscfg_SME_not_supported skip
11919 11:18:05.563547 arm64_vec-syscfg_SME_not_supported skip
11920 11:18:05.566268 arm64_vec-syscfg pass
11921 11:18:05.566830 arm64_za-fork_skipped pass
11922 11:18:05.569755 arm64_za-fork pass
11923 11:18:05.573063 arm64_za-ptrace_SME_not_available skip
11924 11:18:05.576043 arm64_za-ptrace skip
11925 11:18:05.576596 arm64_check_buffer_fill skip
11926 11:18:05.580709 arm64_check_child_memory skip
11927 11:18:05.582651 arm64_check_gcr_el1_cswitch skip
11928 11:18:05.586036 arm64_check_ksm_options skip
11929 11:18:05.589419 arm64_check_mmap_options skip
11930 11:18:05.592370 arm64_check_prctl_check_basic_read pass
11931 11:18:05.596457 arm64_check_prctl_NONE pass
11932 11:18:05.597083 arm64_check_prctl_SYNC skip
11933 11:18:05.599883 arm64_check_prctl_ASYNC skip
11934 11:18:05.602419 arm64_check_prctl_SYNC_ASYNC skip
11935 11:18:05.606104 arm64_check_prctl pass
11936 11:18:05.609143 arm64_check_tags_inclusion skip
11937 11:18:05.609601 arm64_check_user_mem skip
11938 11:18:05.616682 arm64_btitest_nohint_func_call_using_br_x0 skip
11939 11:18:05.619366 arm64_btitest_nohint_func_call_using_br_x16 skip
11940 11:18:05.622591 arm64_btitest_nohint_func_call_using_blr skip
11941 11:18:05.625670 arm64_btitest_bti_none_func_call_using_br_x0 skip
11942 11:18:05.632441 arm64_btitest_bti_none_func_call_using_br_x16 skip
11943 11:18:05.636154 arm64_btitest_bti_none_func_call_using_blr skip
11944 11:18:05.638994 arm64_btitest_bti_c_func_call_using_br_x0 skip
11945 11:18:05.645433 arm64_btitest_bti_c_func_call_using_br_x16 skip
11946 11:18:05.649204 arm64_btitest_bti_c_func_call_using_blr skip
11947 11:18:05.651927 arm64_btitest_bti_j_func_call_using_br_x0 skip
11948 11:18:05.655460 arm64_btitest_bti_j_func_call_using_br_x16 skip
11949 11:18:05.662197 arm64_btitest_bti_j_func_call_using_blr skip
11950 11:18:05.665097 arm64_btitest_bti_jc_func_call_using_br_x0 skip
11951 11:18:05.669040 arm64_btitest_bti_jc_func_call_using_br_x16 skip
11952 11:18:05.671872 arm64_btitest_bti_jc_func_call_using_blr skip
11953 11:18:05.678602 arm64_btitest_paciasp_func_call_using_br_x0 skip
11954 11:18:05.682048 arm64_btitest_paciasp_func_call_using_br_x16 skip
11955 11:18:05.685207 arm64_btitest_paciasp_func_call_using_blr skip
11956 11:18:05.688582 arm64_btitest pass
11957 11:18:05.691627 arm64_nobtitest_nohint_func_call_using_br_x0 skip
11958 11:18:05.698565 arm64_nobtitest_nohint_func_call_using_br_x16 skip
11959 11:18:05.701973 arm64_nobtitest_nohint_func_call_using_blr skip
11960 11:18:05.704985 arm64_nobtitest_bti_none_func_call_using_br_x0 skip
11961 11:18:05.711341 arm64_nobtitest_bti_none_func_call_using_br_x16 skip
11962 11:18:05.714572 arm64_nobtitest_bti_none_func_call_using_blr skip
11963 11:18:05.718607 arm64_nobtitest_bti_c_func_call_using_br_x0 skip
11964 11:18:05.724385 arm64_nobtitest_bti_c_func_call_using_br_x16 skip
11965 11:18:05.727986 arm64_nobtitest_bti_c_func_call_using_blr skip
11966 11:18:05.731291 arm64_nobtitest_bti_j_func_call_using_br_x0 skip
11967 11:18:05.737993 arm64_nobtitest_bti_j_func_call_using_br_x16 skip
11968 11:18:05.741076 arm64_nobtitest_bti_j_func_call_using_blr skip
11969 11:18:05.745008 arm64_nobtitest_bti_jc_func_call_using_br_x0 skip
11970 11:18:05.750917 arm64_nobtitest_bti_jc_func_call_using_br_x16 skip
11971 11:18:05.754188 arm64_nobtitest_bti_jc_func_call_using_blr skip
11972 11:18:05.757705 arm64_nobtitest_paciasp_func_call_using_br_x0 skip
11973 11:18:05.764007 arm64_nobtitest_paciasp_func_call_using_br_x16 skip
11974 11:18:05.767141 arm64_nobtitest_paciasp_func_call_using_blr skip
11975 11:18:05.770485 arm64_nobtitest pass
11976 11:18:05.770902 arm64_hwcap_cpuinfo_match_RNG pass
11977 11:18:05.774072 arm64_hwcap_sigill_RNG skip
11978 11:18:05.777606 arm64_hwcap_cpuinfo_match_SME pass
11979 11:18:05.781050 arm64_hwcap_sigill_SME pass
11980 11:18:05.784180 arm64_hwcap_cpuinfo_match_SVE pass
11981 11:18:05.787344 arm64_hwcap_sigill_SVE pass
11982 11:18:05.790920 arm64_hwcap_cpuinfo_match_SVE_2 pass
11983 11:18:05.791335 arm64_hwcap_sigill_SVE_2 skip
11984 11:18:05.794424 arm64_hwcap_cpuinfo_match_SVE_AES pass
11985 11:18:05.797513 arm64_hwcap_sigill_SVE_AES skip
11986 11:18:05.801141 arm64_hwcap_cpuinfo_match_SVE2_PMULL pass
11987 11:18:05.804138 arm64_hwcap_sigill_SVE2_PMULL skip
11988 11:18:05.810396 arm64_hwcap_cpuinfo_match_SVE2_BITPERM pass
11989 11:18:05.813572 arm64_hwcap_sigill_SVE2_BITPERM skip
11990 11:18:05.817097 arm64_hwcap_cpuinfo_match_SVE2_SHA3 pass
11991 11:18:05.820447 arm64_hwcap_sigill_SVE2_SHA3 skip
11992 11:18:05.823471 arm64_hwcap_cpuinfo_match_SVE2_SM4 pass
11993 11:18:05.826817 arm64_hwcap_sigill_SVE2_SM4 skip
11994 11:18:05.830092 arm64_hwcap_cpuinfo_match_SVE2_I8MM pass
11995 11:18:05.833805 arm64_hwcap_sigill_SVE2_I8MM skip
11996 11:18:05.837091 arm64_hwcap_cpuinfo_match_SVE2_F32MM pass
11997 11:18:05.840003 arm64_hwcap_sigill_SVE2_F32MM skip
11998 11:18:05.843874 arm64_hwcap_cpuinfo_match_SVE2_F64MM pass
11999 11:18:05.846744 arm64_hwcap_sigill_SVE2_F64MM skip
12000 11:18:05.850104 arm64_hwcap_cpuinfo_match_SVE2_BF16 pass
12001 11:18:05.853328 arm64_hwcap_sigill_SVE2_BF16 skip
12002 11:18:05.856665 arm64_hwcap_cpuinfo_match_SVE2_EBF16 pass
12003 11:18:05.860007 arm64_hwcap_sigill_SVE2_EBF16 skip
12004 11:18:05.860433 arm64_hwcap pass
12005 11:18:05.863215 arm64_ptrace_read_tpidr_one pass
12006 11:18:05.866322 arm64_ptrace_write_tpidr_one pass
12007 11:18:05.870157 arm64_ptrace_verify_tpidr_one pass
12008 11:18:05.872830 arm64_ptrace_count_tpidrs pass
12009 11:18:05.876065 arm64_ptrace_tpidr2_write pass
12010 11:18:05.879334 arm64_ptrace_tpidr2_read pass
12011 11:18:05.882788 arm64_ptrace_write_tpidr_only pass
12012 11:18:05.883219 arm64_ptrace pass
12013 11:18:05.886419 arm64_syscall-abi_getpid_FPSIMD pass
12014 11:18:05.889591 arm64_syscall-abi_sched_yield_FPSIMD pass
12015 11:18:05.892905 arm64_syscall-abi pass
12016 11:18:05.895803 arm64_tpidr2_skipped_TPIDR2_not_supported pass
12017 11:18:05.899095 arm64_tpidr2_skipped_TPIDR2_not_supported pass
12018 11:18:05.906235 arm64_tpidr2_skipped_TPIDR2_not_supported pass
12019 11:18:05.910076 arm64_tpidr2_skipped_TPIDR2_not_supported pass
12020 11:18:05.912689 arm64_tpidr2_skipped_TPIDR2_not_supported pass
12021 11:18:05.915980 arm64_tpidr2 pass
12022 11:18:05.919006 + ../../utils/send-to-lava.sh ./output/result.txt
12023 11:18:05.926197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tags_test RESULT=pass>
12024 11:18:05.926947 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tags_test RESULT=pass
12026 11:18:05.932612 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass>
12027 11:18:05.933297 Received signal: <TESTCASE> TEST_CASE_ID=arm64_run_tags_test_sh RESULT=pass
12029 11:18:05.938934 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass>
12030 11:18:05.939614 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_magic RESULT=pass
12032 11:18:05.945399 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass>
12033 11:18:05.946081 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size RESULT=pass
12035 11:18:05.952197 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass>
12036 11:18:05.952915 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_bad_size_for_magic0 RESULT=pass
12038 11:18:05.962076 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass>
12039 11:18:05.962751 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_duplicated_fpsimd RESULT=pass
12041 11:18:06.007505 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass>
12042 11:18:06.008192 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_misaligned_sp RESULT=pass
12044 11:18:06.050741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass>
12045 11:18:06.051427 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_missing_fpsimd RESULT=pass
12047 11:18:06.100707 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip>
12048 11:18:06.101397 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sme_change_vl RESULT=skip
12050 11:18:06.138127 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip>
12051 11:18:06.138918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fake_sigreturn_sve_change_vl RESULT=skip
12053 11:18:06.181246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass>
12054 11:18:06.181918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_compat_toggle RESULT=pass
12056 11:18:06.225074 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass>
12057 11:18:06.225739 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_daif_bits RESULT=pass
12059 11:18:06.267175 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass>
12060 11:18:06.267842 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1h RESULT=pass
12062 11:18:06.310243 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass>
12063 11:18:06.310499 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el1t RESULT=pass
12065 11:18:06.345733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass>
12066 11:18:06.345989 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2h RESULT=pass
12068 11:18:06.383620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass>
12069 11:18:06.383897 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el2t RESULT=pass
12071 11:18:06.419531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass>
12072 11:18:06.420189 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3h RESULT=pass
12074 11:18:06.462269 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass>
12075 11:18:06.462932 Received signal: <TESTCASE> TEST_CASE_ID=arm64_mangle_pstate_invalid_mode_el3t RESULT=pass
12077 11:18:06.499901 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip>
12078 11:18:06.500601 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_no_sm RESULT=skip
12080 11:18:06.545125 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip
12082 11:18:06.547710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_non_streaming RESULT=skip>
12083 11:18:06.582874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_trap_za RESULT=pass>
12084 11:18:06.583143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_trap_za RESULT=pass
12086 11:18:06.618424 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sme_vl RESULT=skip>
12087 11:18:06.618677 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sme_vl RESULT=skip
12089 11:18:06.651213 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ssve_regs RESULT=skip>
12090 11:18:06.651464 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ssve_regs RESULT=skip
12092 11:18:06.684837 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_regs RESULT=skip>
12093 11:18:06.685096 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_regs RESULT=skip
12095 11:18:06.715873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve_vl RESULT=skip>
12096 11:18:06.716130 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve_vl RESULT=skip
12098 11:18:06.752915 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_no_regs RESULT=skip>
12099 11:18:06.753640 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_no_regs RESULT=skip
12101 11:18:06.792584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za_regs RESULT=skip>
12102 11:18:06.793255 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za_regs RESULT=skip
12104 11:18:06.836360 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12106 11:18:06.839938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12107 11:18:06.876771 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12109 11:18:06.879191 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12110 11:18:06.923925 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip>
12111 11:18:06.924622 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip
12113 11:18:06.970805 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12115 11:18:06.973952 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12116 11:18:07.023505 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12118 11:18:07.026850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12119 11:18:07.075424 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip
12121 11:18:07.078593 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_PAUTH_not_enabled RESULT=skip>
12122 11:18:07.116301 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip>
12123 11:18:07.117019 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac_Generic_PAUTH_not_enabled RESULT=skip
12125 11:18:07.161485 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_pac RESULT=pass>
12126 11:18:07.161763 Received signal: <TESTCASE> TEST_CASE_ID=arm64_pac RESULT=pass
12128 11:18:07.200104 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass>
12129 11:18:07.200903 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-0 RESULT=pass
12131 11:18:07.246741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass>
12132 11:18:07.247434 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-0-1 RESULT=pass
12134 11:18:07.293636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass>
12135 11:18:07.294318 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-0 RESULT=pass
12137 11:18:07.347855 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass>
12138 11:18:07.348119 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-1-1 RESULT=pass
12140 11:18:07.381529 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass>
12141 11:18:07.381812 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-0 RESULT=pass
12143 11:18:07.419976 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass>
12144 11:18:07.420229 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-2-1 RESULT=pass
12146 11:18:07.452934 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass
12148 11:18:07.456412 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-0 RESULT=pass>
12149 11:18:07.497517 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass>
12150 11:18:07.498244 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-3-1 RESULT=pass
12152 11:18:07.545078 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass>
12153 11:18:07.545766 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-0 RESULT=pass
12155 11:18:07.584968 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass>
12156 11:18:07.585641 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-4-1 RESULT=pass
12158 11:18:07.627778 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass>
12159 11:18:07.628466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-0 RESULT=pass
12161 11:18:07.678330 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass>
12162 11:18:07.678995 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-5-1 RESULT=pass
12164 11:18:07.724337 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass>
12165 11:18:07.724591 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-0 RESULT=pass
12167 11:18:07.762453 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass>
12168 11:18:07.762708 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-6-1 RESULT=pass
12170 11:18:07.804392 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass>
12171 11:18:07.804653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-0 RESULT=pass
12173 11:18:07.846756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass>
12174 11:18:07.847021 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress_FPSIMD-7-1 RESULT=pass
12176 11:18:07.892423 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_fp-stress RESULT=pass>
12177 11:18:07.892964 Received signal: <TESTCASE> TEST_CASE_ID=arm64_fp-stress RESULT=pass
12179 11:18:07.938220 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip>
12180 11:18:07.938886 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace_SVE_not_available RESULT=skip
12182 11:18:07.977474 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-ptrace RESULT=skip>
12183 11:18:07.977727 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-ptrace RESULT=skip
12185 11:18:08.022397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip>
12186 11:18:08.022651 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls_SVE_not_available RESULT=skip
12188 11:18:08.058584 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip>
12189 11:18:08.058838 Received signal: <TESTCASE> TEST_CASE_ID=arm64_sve-probe-vls RESULT=skip
12191 11:18:08.099871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12192 11:18:08.100144 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12194 11:18:08.139610 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12195 11:18:08.139866 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12197 11:18:08.181402 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12198 11:18:08.181662 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12200 11:18:08.218365 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12201 11:18:08.218618 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12203 11:18:08.254459 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12204 11:18:08.254711 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12206 11:18:08.292508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12207 11:18:08.292835 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12209 11:18:08.330950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12210 11:18:08.331203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12212 11:18:08.372477 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12213 11:18:08.372767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12215 11:18:08.417027 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12216 11:18:08.417729 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12218 11:18:08.466295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip>
12219 11:18:08.466969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SVE_not_supported RESULT=skip
12221 11:18:08.516938 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12222 11:18:08.517610 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12224 11:18:08.570450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12225 11:18:08.571128 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12227 11:18:08.612766 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12228 11:18:08.613453 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12230 11:18:08.660826 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12231 11:18:08.661496 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12233 11:18:08.709531 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12234 11:18:08.709791 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12236 11:18:08.755611 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12237 11:18:08.755879 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12239 11:18:08.797589 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12240 11:18:08.797850 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12242 11:18:08.840957 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12243 11:18:08.841211 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12245 11:18:08.875421 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12246 11:18:08.875673 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12248 11:18:08.915193 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip>
12249 11:18:08.915452 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg_SME_not_supported RESULT=skip
12251 11:18:08.951744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_vec-syscfg RESULT=pass>
12252 11:18:08.951999 Received signal: <TESTCASE> TEST_CASE_ID=arm64_vec-syscfg RESULT=pass
12254 11:18:08.990690 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass>
12255 11:18:08.990955 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork_skipped RESULT=pass
12257 11:18:09.030945 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-fork RESULT=pass>
12258 11:18:09.031198 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-fork RESULT=pass
12260 11:18:09.075620 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip>
12261 11:18:09.075873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace_SME_not_available RESULT=skip
12263 11:18:09.108440 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_za-ptrace RESULT=skip>
12264 11:18:09.108713 Received signal: <TESTCASE> TEST_CASE_ID=arm64_za-ptrace RESULT=skip
12266 11:18:09.146513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip>
12267 11:18:09.146783 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_buffer_fill RESULT=skip
12269 11:18:09.184665 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_child_memory RESULT=skip>
12270 11:18:09.184918 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_child_memory RESULT=skip
12272 11:18:09.223321 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip
12274 11:18:09.226258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_gcr_el1_cswitch RESULT=skip>
12275 11:18:09.262536 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_ksm_options RESULT=skip>
12276 11:18:09.262852 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_ksm_options RESULT=skip
12278 11:18:09.303134 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_mmap_options RESULT=skip>
12279 11:18:09.303391 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_mmap_options RESULT=skip
12281 11:18:09.350470 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass>
12282 11:18:09.350728 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_check_basic_read RESULT=pass
12284 11:18:09.385787 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass>
12285 11:18:09.386042 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_NONE RESULT=pass
12287 11:18:09.427550 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip>
12288 11:18:09.427806 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC RESULT=skip
12290 11:18:09.472768 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip>
12291 11:18:09.473022 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_ASYNC RESULT=skip
12293 11:18:09.521407 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip
12295 11:18:09.525058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl_SYNC_ASYNC RESULT=skip>
12296 11:18:09.559154 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_prctl RESULT=pass>
12297 11:18:09.559408 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_prctl RESULT=pass
12299 11:18:09.599230 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip>
12300 11:18:09.599493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_tags_inclusion RESULT=skip
12302 11:18:09.638713 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_check_user_mem RESULT=skip>
12303 11:18:09.638969 Received signal: <TESTCASE> TEST_CASE_ID=arm64_check_user_mem RESULT=skip
12305 11:18:09.690874 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip>
12306 11:18:09.691136 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x0 RESULT=skip
12308 11:18:09.725344 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip>
12309 11:18:09.725595 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_br_x16 RESULT=skip
12311 11:18:09.767410 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip>
12312 11:18:09.767666 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_nohint_func_call_using_blr RESULT=skip
12314 11:18:09.807113 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip>
12315 11:18:09.807382 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x0 RESULT=skip
12317 11:18:09.850973 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip>
12318 11:18:09.851653 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_br_x16 RESULT=skip
12320 11:18:09.900502 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip>
12321 11:18:09.901215 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_none_func_call_using_blr RESULT=skip
12323 11:18:09.948574 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip>
12324 11:18:09.949249 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x0 RESULT=skip
12326 11:18:09.996338 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip>
12327 11:18:09.997075 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_br_x16 RESULT=skip
12329 11:18:10.041216 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip>
12330 11:18:10.041474 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_c_func_call_using_blr RESULT=skip
12332 11:18:10.080674 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip>
12333 11:18:10.080930 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x0 RESULT=skip
12335 11:18:10.120983 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip>
12336 11:18:10.121242 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_br_x16 RESULT=skip
12338 11:18:10.161370 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip>
12339 11:18:10.161628 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_j_func_call_using_blr RESULT=skip
12341 11:18:10.200491 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12342 11:18:10.200775 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x0 RESULT=skip
12344 11:18:10.244701 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12345 11:18:10.245223 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_br_x16 RESULT=skip
12347 11:18:10.290231 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip>
12348 11:18:10.290493 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_bti_jc_func_call_using_blr RESULT=skip
12350 11:18:10.330883 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip>
12351 11:18:10.331139 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x0 RESULT=skip
12353 11:18:10.365178 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip>
12354 11:18:10.365466 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_br_x16 RESULT=skip
12356 11:18:10.412246 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip>
12357 11:18:10.413070 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest_paciasp_func_call_using_blr RESULT=skip
12359 11:18:10.449597 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_btitest RESULT=pass>
12360 11:18:10.450387 Received signal: <TESTCASE> TEST_CASE_ID=arm64_btitest RESULT=pass
12362 11:18:10.501206 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip>
12363 11:18:10.501942 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x0 RESULT=skip
12365 11:18:10.548094 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip>
12366 11:18:10.548352 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_br_x16 RESULT=skip
12368 11:18:10.596436 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip>
12369 11:18:10.596746 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_nohint_func_call_using_blr RESULT=skip
12371 11:18:10.639839 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip>
12372 11:18:10.640585 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x0 RESULT=skip
12374 11:18:10.685873 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip>
12375 11:18:10.686538 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_br_x16 RESULT=skip
12377 11:18:10.730749 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip>
12378 11:18:10.731418 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_none_func_call_using_blr RESULT=skip
12380 11:18:10.775508 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip>
12381 11:18:10.775762 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x0 RESULT=skip
12383 11:18:10.816914 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip>
12384 11:18:10.817171 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_br_x16 RESULT=skip
12386 11:18:10.859303 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip>
12387 11:18:10.859575 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_c_func_call_using_blr RESULT=skip
12389 11:18:10.910296 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip>
12390 11:18:10.910558 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x0 RESULT=skip
12392 11:18:10.948677 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip>
12393 11:18:10.948929 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_br_x16 RESULT=skip
12395 11:18:10.988378 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip>
12396 11:18:10.988678 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_j_func_call_using_blr RESULT=skip
12398 11:18:11.031190 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip>
12399 11:18:11.031444 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x0 RESULT=skip
12401 11:18:11.073950 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip>
12402 11:18:11.074203 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_br_x16 RESULT=skip
12404 11:18:11.115480 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip>
12405 11:18:11.115753 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_bti_jc_func_call_using_blr RESULT=skip
12407 11:18:11.156283 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip>
12408 11:18:11.157000 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x0 RESULT=skip
12410 11:18:11.204084 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip>
12411 11:18:11.204810 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_br_x16 RESULT=skip
12413 11:18:11.246501 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip>
12414 11:18:11.246755 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest_paciasp_func_call_using_blr RESULT=skip
12416 11:18:11.275830 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_nobtitest RESULT=pass>
12417 11:18:11.276083 Received signal: <TESTCASE> TEST_CASE_ID=arm64_nobtitest RESULT=pass
12419 11:18:11.315431 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass>
12420 11:18:11.315772 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_RNG RESULT=pass
12422 11:18:11.353422 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip>
12423 11:18:11.353873 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_RNG RESULT=skip
12425 11:18:11.400306 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass>
12426 11:18:11.401033 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SME RESULT=pass
12428 11:18:11.438869 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass>
12429 11:18:11.439123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SME RESULT=pass
12431 11:18:11.483054 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass>
12432 11:18:11.483305 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE RESULT=pass
12434 11:18:11.519458 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass>
12435 11:18:11.519719 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE RESULT=pass
12437 11:18:11.559861 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass>
12438 11:18:11.560129 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_2 RESULT=pass
12440 11:18:11.596099 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip>
12441 11:18:11.596620 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_2 RESULT=skip
12443 11:18:11.638842 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass>
12444 11:18:11.639103 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE_AES RESULT=pass
12446 11:18:11.678730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip>
12447 11:18:11.678992 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE_AES RESULT=skip
12449 11:18:11.721997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass>
12450 11:18:11.722286 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_PMULL RESULT=pass
12452 11:18:11.759380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip>
12453 11:18:11.759645 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_PMULL RESULT=skip
12455 11:18:11.802295 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass>
12456 11:18:11.802562 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BITPERM RESULT=pass
12458 11:18:11.840496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip>
12459 11:18:11.840814 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BITPERM RESULT=skip
12461 11:18:11.879640 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass>
12462 11:18:11.879891 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SHA3 RESULT=pass
12464 11:18:11.919240 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip
12466 11:18:11.922097 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SHA3 RESULT=skip>
12467 11:18:11.959856 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass>
12468 11:18:11.960123 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_SM4 RESULT=pass
12470 11:18:11.999937 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip
12472 11:18:12.002660 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_SM4 RESULT=skip>
12473 11:18:12.042762 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass>
12474 11:18:12.043025 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_I8MM RESULT=pass
12476 11:18:12.078410 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip
12478 11:18:12.081650 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_I8MM RESULT=skip>
12479 11:18:12.120803 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass>
12480 11:18:12.121059 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F32MM RESULT=pass
12482 11:18:12.163334 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip>
12483 11:18:12.163586 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F32MM RESULT=skip
12485 11:18:12.199954 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass>
12486 11:18:12.200206 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_F64MM RESULT=pass
12488 11:18:12.244733 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip>
12489 11:18:12.244985 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_F64MM RESULT=skip
12491 11:18:12.287646 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass>
12492 11:18:12.287920 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_BF16 RESULT=pass
12494 11:18:12.323135 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip
12496 11:18:12.326413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_BF16 RESULT=skip>
12497 11:18:12.364507 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass>
12498 11:18:12.364796 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_cpuinfo_match_SVE2_EBF16 RESULT=pass
12500 11:18:12.402183 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip>
12501 11:18:12.402436 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap_sigill_SVE2_EBF16 RESULT=skip
12503 11:18:12.440060 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_hwcap RESULT=pass>
12504 11:18:12.440333 Received signal: <TESTCASE> TEST_CASE_ID=arm64_hwcap RESULT=pass
12506 11:18:12.485760 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass
12508 11:18:12.488710 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_read_tpidr_one RESULT=pass>
12509 11:18:12.523902 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass
12511 11:18:12.527240 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_one RESULT=pass>
12512 11:18:12.566905 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass>
12513 11:18:12.567162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_verify_tpidr_one RESULT=pass
12515 11:18:12.602891 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass>
12516 11:18:12.603162 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_count_tpidrs RESULT=pass
12518 11:18:12.637214 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass>
12519 11:18:12.637467 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_write RESULT=pass
12521 11:18:12.674245 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass>
12522 11:18:12.674510 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_tpidr2_read RESULT=pass
12524 11:18:12.711571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass>
12525 11:18:12.711854 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace_write_tpidr_only RESULT=pass
12527 11:18:12.743009 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_ptrace RESULT=pass>
12528 11:18:12.743295 Received signal: <TESTCASE> TEST_CASE_ID=arm64_ptrace RESULT=pass
12530 11:18:12.777729 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass>
12531 11:18:12.777978 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_getpid_FPSIMD RESULT=pass
12533 11:18:12.813469 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass>
12534 11:18:12.813737 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi_sched_yield_FPSIMD RESULT=pass
12536 11:18:12.851383 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_syscall-abi RESULT=pass>
12537 11:18:12.852151 Received signal: <TESTCASE> TEST_CASE_ID=arm64_syscall-abi RESULT=pass
12539 11:18:12.902299 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12540 11:18:12.902560 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12542 11:18:12.935489 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12543 11:18:12.935761 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12545 11:18:12.979877 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12546 11:18:12.980592 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12548 11:18:13.030186 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12549 11:18:13.030445 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12551 11:18:13.070513 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass>
12552 11:18:13.070767 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2_skipped_TPIDR2_not_supported RESULT=pass
12554 11:18:13.108817 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=arm64_tpidr2 RESULT=pass>
12555 11:18:13.108905 + set +x
12556 11:18:13.109143 Received signal: <TESTCASE> TEST_CASE_ID=arm64_tpidr2 RESULT=pass
12558 11:18:13.115260 <LAVA_SIGNAL_ENDRUN 1_kselftest-arm64 10591250_1.6.2.3.5>
12559 11:18:13.115512 Received signal: <ENDRUN> 1_kselftest-arm64 10591250_1.6.2.3.5
12560 11:18:13.115585 Ending use of test pattern.
12561 11:18:13.115649 Ending test lava.1_kselftest-arm64 (10591250_1.6.2.3.5), duration 29.18
12563 11:18:13.118618 <LAVA_TEST_RUNNER EXIT>
12564 11:18:13.118969 ok: lava_test_shell seems to have completed
12565 11:18:13.120002 arm64_btitest: pass
arm64_btitest_bti_c_func_call_using_blr: skip
arm64_btitest_bti_c_func_call_using_br_x0: skip
arm64_btitest_bti_c_func_call_using_br_x16: skip
arm64_btitest_bti_j_func_call_using_blr: skip
arm64_btitest_bti_j_func_call_using_br_x0: skip
arm64_btitest_bti_j_func_call_using_br_x16: skip
arm64_btitest_bti_jc_func_call_using_blr: skip
arm64_btitest_bti_jc_func_call_using_br_x0: skip
arm64_btitest_bti_jc_func_call_using_br_x16: skip
arm64_btitest_bti_none_func_call_using_blr: skip
arm64_btitest_bti_none_func_call_using_br_x0: skip
arm64_btitest_bti_none_func_call_using_br_x16: skip
arm64_btitest_nohint_func_call_using_blr: skip
arm64_btitest_nohint_func_call_using_br_x0: skip
arm64_btitest_nohint_func_call_using_br_x16: skip
arm64_btitest_paciasp_func_call_using_blr: skip
arm64_btitest_paciasp_func_call_using_br_x0: skip
arm64_btitest_paciasp_func_call_using_br_x16: skip
arm64_check_buffer_fill: skip
arm64_check_child_memory: skip
arm64_check_gcr_el1_cswitch: skip
arm64_check_ksm_options: skip
arm64_check_mmap_options: skip
arm64_check_prctl: pass
arm64_check_prctl_ASYNC: skip
arm64_check_prctl_NONE: pass
arm64_check_prctl_SYNC: skip
arm64_check_prctl_SYNC_ASYNC: skip
arm64_check_prctl_check_basic_read: pass
arm64_check_tags_inclusion: skip
arm64_check_user_mem: skip
arm64_fake_sigreturn_bad_magic: pass
arm64_fake_sigreturn_bad_size: pass
arm64_fake_sigreturn_bad_size_for_magic0: pass
arm64_fake_sigreturn_duplicated_fpsimd: pass
arm64_fake_sigreturn_misaligned_sp: pass
arm64_fake_sigreturn_missing_fpsimd: pass
arm64_fake_sigreturn_sme_change_vl: skip
arm64_fake_sigreturn_sve_change_vl: skip
arm64_fp-stress: pass
arm64_fp-stress_FPSIMD-0-0: pass
arm64_fp-stress_FPSIMD-0-1: pass
arm64_fp-stress_FPSIMD-1-0: pass
arm64_fp-stress_FPSIMD-1-1: pass
arm64_fp-stress_FPSIMD-2-0: pass
arm64_fp-stress_FPSIMD-2-1: pass
arm64_fp-stress_FPSIMD-3-0: pass
arm64_fp-stress_FPSIMD-3-1: pass
arm64_fp-stress_FPSIMD-4-0: pass
arm64_fp-stress_FPSIMD-4-1: pass
arm64_fp-stress_FPSIMD-5-0: pass
arm64_fp-stress_FPSIMD-5-1: pass
arm64_fp-stress_FPSIMD-6-0: pass
arm64_fp-stress_FPSIMD-6-1: pass
arm64_fp-stress_FPSIMD-7-0: pass
arm64_fp-stress_FPSIMD-7-1: pass
arm64_hwcap: pass
arm64_hwcap_cpuinfo_match_RNG: pass
arm64_hwcap_cpuinfo_match_SME: pass
arm64_hwcap_cpuinfo_match_SVE: pass
arm64_hwcap_cpuinfo_match_SVE2_BF16: pass
arm64_hwcap_cpuinfo_match_SVE2_BITPERM: pass
arm64_hwcap_cpuinfo_match_SVE2_EBF16: pass
arm64_hwcap_cpuinfo_match_SVE2_F32MM: pass
arm64_hwcap_cpuinfo_match_SVE2_F64MM: pass
arm64_hwcap_cpuinfo_match_SVE2_I8MM: pass
arm64_hwcap_cpuinfo_match_SVE2_PMULL: pass
arm64_hwcap_cpuinfo_match_SVE2_SHA3: pass
arm64_hwcap_cpuinfo_match_SVE2_SM4: pass
arm64_hwcap_cpuinfo_match_SVE_2: pass
arm64_hwcap_cpuinfo_match_SVE_AES: pass
arm64_hwcap_sigill_RNG: skip
arm64_hwcap_sigill_SME: pass
arm64_hwcap_sigill_SVE: pass
arm64_hwcap_sigill_SVE2_BF16: skip
arm64_hwcap_sigill_SVE2_BITPERM: skip
arm64_hwcap_sigill_SVE2_EBF16: skip
arm64_hwcap_sigill_SVE2_F32MM: skip
arm64_hwcap_sigill_SVE2_F64MM: skip
arm64_hwcap_sigill_SVE2_I8MM: skip
arm64_hwcap_sigill_SVE2_PMULL: skip
arm64_hwcap_sigill_SVE2_SHA3: skip
arm64_hwcap_sigill_SVE2_SM4: skip
arm64_hwcap_sigill_SVE_2: skip
arm64_hwcap_sigill_SVE_AES: skip
arm64_mangle_pstate_invalid_compat_toggle: pass
arm64_mangle_pstate_invalid_daif_bits: pass
arm64_mangle_pstate_invalid_mode_el1h: pass
arm64_mangle_pstate_invalid_mode_el1t: pass
arm64_mangle_pstate_invalid_mode_el2h: pass
arm64_mangle_pstate_invalid_mode_el2t: pass
arm64_mangle_pstate_invalid_mode_el3h: pass
arm64_mangle_pstate_invalid_mode_el3t: pass
arm64_nobtitest: pass
arm64_nobtitest_bti_c_func_call_using_blr: skip
arm64_nobtitest_bti_c_func_call_using_br_x0: skip
arm64_nobtitest_bti_c_func_call_using_br_x16: skip
arm64_nobtitest_bti_j_func_call_using_blr: skip
arm64_nobtitest_bti_j_func_call_using_br_x0: skip
arm64_nobtitest_bti_j_func_call_using_br_x16: skip
arm64_nobtitest_bti_jc_func_call_using_blr: skip
arm64_nobtitest_bti_jc_func_call_using_br_x0: skip
arm64_nobtitest_bti_jc_func_call_using_br_x16: skip
arm64_nobtitest_bti_none_func_call_using_blr: skip
arm64_nobtitest_bti_none_func_call_using_br_x0: skip
arm64_nobtitest_bti_none_func_call_using_br_x16: skip
arm64_nobtitest_nohint_func_call_using_blr: skip
arm64_nobtitest_nohint_func_call_using_br_x0: skip
arm64_nobtitest_nohint_func_call_using_br_x16: skip
arm64_nobtitest_paciasp_func_call_using_blr: skip
arm64_nobtitest_paciasp_func_call_using_br_x0: skip
arm64_nobtitest_paciasp_func_call_using_br_x16: skip
arm64_pac: pass
arm64_pac_Generic_PAUTH_not_enabled: skip
arm64_pac_PAUTH_not_enabled: skip
arm64_ptrace: pass
arm64_ptrace_count_tpidrs: pass
arm64_ptrace_read_tpidr_one: pass
arm64_ptrace_tpidr2_read: pass
arm64_ptrace_tpidr2_write: pass
arm64_ptrace_verify_tpidr_one: pass
arm64_ptrace_write_tpidr_one: pass
arm64_ptrace_write_tpidr_only: pass
arm64_run_tags_test_sh: pass
arm64_sme_trap_no_sm: skip
arm64_sme_trap_non_streaming: skip
arm64_sme_trap_za: pass
arm64_sme_vl: skip
arm64_ssve_regs: skip
arm64_sve-probe-vls: skip
arm64_sve-probe-vls_SVE_not_available: skip
arm64_sve-ptrace: skip
arm64_sve-ptrace_SVE_not_available: skip
arm64_sve_regs: skip
arm64_sve_vl: skip
arm64_syscall-abi: pass
arm64_syscall-abi_getpid_FPSIMD: pass
arm64_syscall-abi_sched_yield_FPSIMD: pass
arm64_tags_test: pass
arm64_tpidr2: pass
arm64_tpidr2_skipped_TPIDR2_not_supported: pass
arm64_vec-syscfg: pass
arm64_vec-syscfg_SME_not_supported: skip
arm64_vec-syscfg_SVE_not_supported: skip
arm64_za-fork: pass
arm64_za-fork_skipped: pass
arm64_za-ptrace: skip
arm64_za-ptrace_SME_not_available: skip
arm64_za_no_regs: skip
arm64_za_regs: skip
12566 11:18:13.120169 end: 3.1 lava-test-shell (duration 00:00:30) [common]
12567 11:18:13.120265 end: 3 lava-test-retry (duration 00:00:30) [common]
12568 11:18:13.120357 start: 4 finalize (timeout 00:07:27) [common]
12569 11:18:13.120459 start: 4.1 power-off (timeout 00:00:30) [common]
12570 11:18:13.120640 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
12571 11:18:13.199278 >> Command sent successfully.
12572 11:18:13.204281 Returned 0 in 0 seconds
12573 11:18:13.305220 end: 4.1 power-off (duration 00:00:00) [common]
12575 11:18:13.306765 start: 4.2 read-feedback (timeout 00:07:27) [common]
12576 11:18:13.308072 Listened to connection for namespace 'common' for up to 1s
12577 11:18:14.308762 Finalising connection for namespace 'common'
12578 11:18:14.309461 Disconnecting from shell: Finalise
12579 11:18:14.309901 / #
12580 11:18:14.411033 end: 4.2 read-feedback (duration 00:00:01) [common]
12581 11:18:14.411774 end: 4 finalize (duration 00:00:01) [common]
12582 11:18:14.412379 Cleaning after the job
12583 11:18:14.412935 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591250/tftp-deploy-3xwj17rv/ramdisk
12584 11:18:14.422722 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591250/tftp-deploy-3xwj17rv/kernel
12585 11:18:14.454346 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591250/tftp-deploy-3xwj17rv/dtb
12586 11:18:14.454709 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591250/tftp-deploy-3xwj17rv/nfsrootfs
12587 11:18:14.527921 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591250/tftp-deploy-3xwj17rv/modules
12588 11:18:14.533268 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10591250
12589 11:18:15.058167 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10591250
12590 11:18:15.058349 Job finished correctly