Boot log: mt8192-asurada-spherion-r0
- Errors: 0
- Kernel Errors: 42
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 30
1 11:16:42.155317 lava-dispatcher, installed at version: 2023.05.1
2 11:16:42.155558 start: 0 validate
3 11:16:42.155688 Start time: 2023-06-05 11:16:42.155681+00:00 (UTC)
4 11:16:42.155806 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:16:42.155932 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Finitrd.cpio.gz exists
6 11:16:42.444455 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:16:42.445200 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:16:42.737410 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:16:42.738197 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:16:43.027874 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:16:43.028630 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-kselftest%2F20230527.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 11:16:43.318537 Using caching service: 'http://localhost/cache/?uri=%s'
13 11:16:43.319197 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 11:16:43.604167 validate duration: 1.45
16 11:16:43.604422 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 11:16:43.604520 start: 1.1 download-retry (timeout 00:10:00) [common]
18 11:16:43.604609 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 11:16:43.604739 Not decompressing ramdisk as can be used compressed.
20 11:16:43.604832 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/initrd.cpio.gz
21 11:16:43.604897 saving as /var/lib/lava/dispatcher/tmp/10591269/tftp-deploy-al9f63sa/ramdisk/initrd.cpio.gz
22 11:16:43.604961 total size: 4665601 (4MB)
23 11:16:43.606082 progress 0% (0MB)
24 11:16:43.607677 progress 5% (0MB)
25 11:16:43.608912 progress 10% (0MB)
26 11:16:43.610164 progress 15% (0MB)
27 11:16:43.611432 progress 20% (0MB)
28 11:16:43.612675 progress 25% (1MB)
29 11:16:43.613963 progress 30% (1MB)
30 11:16:43.615189 progress 35% (1MB)
31 11:16:43.616473 progress 40% (1MB)
32 11:16:43.617857 progress 45% (2MB)
33 11:16:43.619109 progress 50% (2MB)
34 11:16:43.620439 progress 55% (2MB)
35 11:16:43.621709 progress 60% (2MB)
36 11:16:43.622969 progress 65% (2MB)
37 11:16:43.624253 progress 70% (3MB)
38 11:16:43.625514 progress 75% (3MB)
39 11:16:43.626801 progress 80% (3MB)
40 11:16:43.628277 progress 85% (3MB)
41 11:16:43.629509 progress 90% (4MB)
42 11:16:43.630780 progress 95% (4MB)
43 11:16:43.632073 progress 100% (4MB)
44 11:16:43.632233 4MB downloaded in 0.03s (163.19MB/s)
45 11:16:43.632379 end: 1.1.1 http-download (duration 00:00:00) [common]
47 11:16:43.632624 end: 1.1 download-retry (duration 00:00:00) [common]
48 11:16:43.632714 start: 1.2 download-retry (timeout 00:10:00) [common]
49 11:16:43.632802 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 11:16:43.632935 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 11:16:43.633008 saving as /var/lib/lava/dispatcher/tmp/10591269/tftp-deploy-al9f63sa/kernel/Image
52 11:16:43.633070 total size: 45746688 (43MB)
53 11:16:43.633129 No compression specified
54 11:16:43.634255 progress 0% (0MB)
55 11:16:43.646139 progress 5% (2MB)
56 11:16:43.658221 progress 10% (4MB)
57 11:16:43.670192 progress 15% (6MB)
58 11:16:43.682200 progress 20% (8MB)
59 11:16:43.694164 progress 25% (10MB)
60 11:16:43.705661 progress 30% (13MB)
61 11:16:43.717419 progress 35% (15MB)
62 11:16:43.729148 progress 40% (17MB)
63 11:16:43.741155 progress 45% (19MB)
64 11:16:43.753196 progress 50% (21MB)
65 11:16:43.764970 progress 55% (24MB)
66 11:16:43.776957 progress 60% (26MB)
67 11:16:43.788920 progress 65% (28MB)
68 11:16:43.800685 progress 70% (30MB)
69 11:16:43.812267 progress 75% (32MB)
70 11:16:43.823847 progress 80% (34MB)
71 11:16:43.835525 progress 85% (37MB)
72 11:16:43.847374 progress 90% (39MB)
73 11:16:43.859183 progress 95% (41MB)
74 11:16:43.870799 progress 100% (43MB)
75 11:16:43.870945 43MB downloaded in 0.24s (183.41MB/s)
76 11:16:43.871135 end: 1.2.1 http-download (duration 00:00:00) [common]
78 11:16:43.871505 end: 1.2 download-retry (duration 00:00:00) [common]
79 11:16:43.871595 start: 1.3 download-retry (timeout 00:10:00) [common]
80 11:16:43.871685 start: 1.3.1 http-download (timeout 00:10:00) [common]
81 11:16:43.871820 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 11:16:43.871889 saving as /var/lib/lava/dispatcher/tmp/10591269/tftp-deploy-al9f63sa/dtb/mt8192-asurada-spherion-r0.dtb
83 11:16:43.871957 total size: 46924 (0MB)
84 11:16:43.872016 No compression specified
85 11:16:43.873141 progress 69% (0MB)
86 11:16:43.873409 progress 100% (0MB)
87 11:16:43.873588 0MB downloaded in 0.00s (27.51MB/s)
88 11:16:43.873753 end: 1.3.1 http-download (duration 00:00:00) [common]
90 11:16:43.874001 end: 1.3 download-retry (duration 00:00:00) [common]
91 11:16:43.874087 start: 1.4 download-retry (timeout 00:10:00) [common]
92 11:16:43.874169 start: 1.4.1 http-download (timeout 00:10:00) [common]
93 11:16:43.874356 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-kselftest/20230527.0/arm64/full.rootfs.tar.xz
94 11:16:43.874423 saving as /var/lib/lava/dispatcher/tmp/10591269/tftp-deploy-al9f63sa/nfsrootfs/full.rootfs.tar
95 11:16:43.874482 total size: 200770336 (191MB)
96 11:16:43.874541 Using unxz to decompress xz
97 11:16:43.878508 progress 0% (0MB)
98 11:16:44.399581 progress 5% (9MB)
99 11:16:44.905728 progress 10% (19MB)
100 11:16:45.478509 progress 15% (28MB)
101 11:16:45.839389 progress 20% (38MB)
102 11:16:46.158656 progress 25% (47MB)
103 11:16:46.739985 progress 30% (57MB)
104 11:16:47.278825 progress 35% (67MB)
105 11:16:47.856628 progress 40% (76MB)
106 11:16:48.403696 progress 45% (86MB)
107 11:16:48.976397 progress 50% (95MB)
108 11:16:49.594933 progress 55% (105MB)
109 11:16:50.239359 progress 60% (114MB)
110 11:16:50.357194 progress 65% (124MB)
111 11:16:50.496883 progress 70% (134MB)
112 11:16:50.592677 progress 75% (143MB)
113 11:16:50.667958 progress 80% (153MB)
114 11:16:50.738869 progress 85% (162MB)
115 11:16:50.836947 progress 90% (172MB)
116 11:16:51.122785 progress 95% (181MB)
117 11:16:51.720428 progress 100% (191MB)
118 11:16:51.725053 191MB downloaded in 7.85s (24.39MB/s)
119 11:16:51.725395 end: 1.4.1 http-download (duration 00:00:08) [common]
121 11:16:51.725659 end: 1.4 download-retry (duration 00:00:08) [common]
122 11:16:51.725749 start: 1.5 download-retry (timeout 00:09:52) [common]
123 11:16:51.725835 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 11:16:51.725981 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 11:16:51.726052 saving as /var/lib/lava/dispatcher/tmp/10591269/tftp-deploy-al9f63sa/modules/modules.tar
126 11:16:51.726113 total size: 8547328 (8MB)
127 11:16:51.726175 Using unxz to decompress xz
128 11:16:51.729699 progress 0% (0MB)
129 11:16:51.750826 progress 5% (0MB)
130 11:16:51.775466 progress 10% (0MB)
131 11:16:51.801042 progress 15% (1MB)
132 11:16:51.825654 progress 20% (1MB)
133 11:16:51.851023 progress 25% (2MB)
134 11:16:51.875276 progress 30% (2MB)
135 11:16:51.899843 progress 35% (2MB)
136 11:16:51.924111 progress 40% (3MB)
137 11:16:51.948983 progress 45% (3MB)
138 11:16:51.972342 progress 50% (4MB)
139 11:16:51.994965 progress 55% (4MB)
140 11:16:52.019674 progress 60% (4MB)
141 11:16:52.044451 progress 65% (5MB)
142 11:16:52.069539 progress 70% (5MB)
143 11:16:52.095804 progress 75% (6MB)
144 11:16:52.124689 progress 80% (6MB)
145 11:16:52.147036 progress 85% (6MB)
146 11:16:52.171622 progress 90% (7MB)
147 11:16:52.194664 progress 95% (7MB)
148 11:16:52.217909 progress 100% (8MB)
149 11:16:52.223799 8MB downloaded in 0.50s (16.38MB/s)
150 11:16:52.224068 end: 1.5.1 http-download (duration 00:00:00) [common]
152 11:16:52.224342 end: 1.5 download-retry (duration 00:00:00) [common]
153 11:16:52.224435 start: 1.6 prepare-tftp-overlay (timeout 00:09:51) [common]
154 11:16:52.224528 start: 1.6.1 extract-nfsrootfs (timeout 00:09:51) [common]
155 11:16:55.509995 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/10591269/extract-nfsrootfs-e40z_w25
156 11:16:55.510189 end: 1.6.1 extract-nfsrootfs (duration 00:00:03) [common]
157 11:16:55.510290 start: 1.6.2 lava-overlay (timeout 00:09:48) [common]
158 11:16:55.510490 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10591269/lava-overlay-xzzfx22o
159 11:16:55.510657 makedir: /var/lib/lava/dispatcher/tmp/10591269/lava-overlay-xzzfx22o/lava-10591269/bin
160 11:16:55.510766 makedir: /var/lib/lava/dispatcher/tmp/10591269/lava-overlay-xzzfx22o/lava-10591269/tests
161 11:16:55.510901 makedir: /var/lib/lava/dispatcher/tmp/10591269/lava-overlay-xzzfx22o/lava-10591269/results
162 11:16:55.511002 Creating /var/lib/lava/dispatcher/tmp/10591269/lava-overlay-xzzfx22o/lava-10591269/bin/lava-add-keys
163 11:16:55.511179 Creating /var/lib/lava/dispatcher/tmp/10591269/lava-overlay-xzzfx22o/lava-10591269/bin/lava-add-sources
164 11:16:55.511303 Creating /var/lib/lava/dispatcher/tmp/10591269/lava-overlay-xzzfx22o/lava-10591269/bin/lava-background-process-start
165 11:16:55.511470 Creating /var/lib/lava/dispatcher/tmp/10591269/lava-overlay-xzzfx22o/lava-10591269/bin/lava-background-process-stop
166 11:16:55.511592 Creating /var/lib/lava/dispatcher/tmp/10591269/lava-overlay-xzzfx22o/lava-10591269/bin/lava-common-functions
167 11:16:55.511710 Creating /var/lib/lava/dispatcher/tmp/10591269/lava-overlay-xzzfx22o/lava-10591269/bin/lava-echo-ipv4
168 11:16:55.511829 Creating /var/lib/lava/dispatcher/tmp/10591269/lava-overlay-xzzfx22o/lava-10591269/bin/lava-install-packages
169 11:16:55.511945 Creating /var/lib/lava/dispatcher/tmp/10591269/lava-overlay-xzzfx22o/lava-10591269/bin/lava-installed-packages
170 11:16:55.512107 Creating /var/lib/lava/dispatcher/tmp/10591269/lava-overlay-xzzfx22o/lava-10591269/bin/lava-os-build
171 11:16:55.512225 Creating /var/lib/lava/dispatcher/tmp/10591269/lava-overlay-xzzfx22o/lava-10591269/bin/lava-probe-channel
172 11:16:55.512382 Creating /var/lib/lava/dispatcher/tmp/10591269/lava-overlay-xzzfx22o/lava-10591269/bin/lava-probe-ip
173 11:16:55.512500 Creating /var/lib/lava/dispatcher/tmp/10591269/lava-overlay-xzzfx22o/lava-10591269/bin/lava-target-ip
174 11:16:55.512620 Creating /var/lib/lava/dispatcher/tmp/10591269/lava-overlay-xzzfx22o/lava-10591269/bin/lava-target-mac
175 11:16:55.512738 Creating /var/lib/lava/dispatcher/tmp/10591269/lava-overlay-xzzfx22o/lava-10591269/bin/lava-target-storage
176 11:16:55.512905 Creating /var/lib/lava/dispatcher/tmp/10591269/lava-overlay-xzzfx22o/lava-10591269/bin/lava-test-case
177 11:16:55.513027 Creating /var/lib/lava/dispatcher/tmp/10591269/lava-overlay-xzzfx22o/lava-10591269/bin/lava-test-event
178 11:16:55.513146 Creating /var/lib/lava/dispatcher/tmp/10591269/lava-overlay-xzzfx22o/lava-10591269/bin/lava-test-feedback
179 11:16:55.513264 Creating /var/lib/lava/dispatcher/tmp/10591269/lava-overlay-xzzfx22o/lava-10591269/bin/lava-test-raise
180 11:16:55.513422 Creating /var/lib/lava/dispatcher/tmp/10591269/lava-overlay-xzzfx22o/lava-10591269/bin/lava-test-reference
181 11:16:55.513541 Creating /var/lib/lava/dispatcher/tmp/10591269/lava-overlay-xzzfx22o/lava-10591269/bin/lava-test-runner
182 11:16:55.513702 Creating /var/lib/lava/dispatcher/tmp/10591269/lava-overlay-xzzfx22o/lava-10591269/bin/lava-test-set
183 11:16:55.513819 Creating /var/lib/lava/dispatcher/tmp/10591269/lava-overlay-xzzfx22o/lava-10591269/bin/lava-test-shell
184 11:16:55.513982 Updating /var/lib/lava/dispatcher/tmp/10591269/lava-overlay-xzzfx22o/lava-10591269/bin/lava-add-keys (debian)
185 11:16:55.514120 Updating /var/lib/lava/dispatcher/tmp/10591269/lava-overlay-xzzfx22o/lava-10591269/bin/lava-add-sources (debian)
186 11:16:55.514259 Updating /var/lib/lava/dispatcher/tmp/10591269/lava-overlay-xzzfx22o/lava-10591269/bin/lava-install-packages (debian)
187 11:16:55.514396 Updating /var/lib/lava/dispatcher/tmp/10591269/lava-overlay-xzzfx22o/lava-10591269/bin/lava-installed-packages (debian)
188 11:16:55.514539 Updating /var/lib/lava/dispatcher/tmp/10591269/lava-overlay-xzzfx22o/lava-10591269/bin/lava-os-build (debian)
189 11:16:55.514690 Creating /var/lib/lava/dispatcher/tmp/10591269/lava-overlay-xzzfx22o/lava-10591269/environment
190 11:16:55.514786 LAVA metadata
191 11:16:55.514855 - LAVA_JOB_ID=10591269
192 11:16:55.514917 - LAVA_DISPATCHER_IP=192.168.201.1
193 11:16:55.515015 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:48) [common]
194 11:16:55.515082 skipped lava-vland-overlay
195 11:16:55.515156 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
196 11:16:55.515235 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:48) [common]
197 11:16:55.515311 skipped lava-multinode-overlay
198 11:16:55.515408 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
199 11:16:55.515487 start: 1.6.2.3 test-definition (timeout 00:09:48) [common]
200 11:16:55.515559 Loading test definitions
201 11:16:55.515675 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:48) [common]
202 11:16:55.515763 Using /lava-10591269 at stage 0
203 11:16:55.516029 uuid=10591269_1.6.2.3.1 testdef=None
204 11:16:55.516116 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
205 11:16:55.516241 start: 1.6.2.3.2 test-overlay (timeout 00:09:48) [common]
206 11:16:55.516689 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
208 11:16:55.516983 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:48) [common]
209 11:16:55.517541 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
211 11:16:55.517777 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:48) [common]
212 11:16:55.518324 runner path: /var/lib/lava/dispatcher/tmp/10591269/lava-overlay-xzzfx22o/lava-10591269/0/tests/0_timesync-off test_uuid 10591269_1.6.2.3.1
213 11:16:55.518500 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
215 11:16:55.518778 start: 1.6.2.3.5 git-repo-action (timeout 00:09:48) [common]
216 11:16:55.518888 Using /lava-10591269 at stage 0
217 11:16:55.518982 Fetching tests from https://github.com/kernelci/test-definitions.git
218 11:16:55.519059 Running '/usr/bin/git clone https://github.com/kernelci/test-definitions.git /var/lib/lava/dispatcher/tmp/10591269/lava-overlay-xzzfx22o/lava-10591269/0/tests/1_kselftest-tpm2'
219 11:17:01.293684 Running '/usr/bin/git checkout kernelci.org
220 11:17:01.437362 Tests stored (tmp) in /var/lib/lava/dispatcher/tmp/10591269/lava-overlay-xzzfx22o/lava-10591269/0/tests/1_kselftest-tpm2/automated/linux/kselftest/kselftest.yaml
221 11:17:01.438093 uuid=10591269_1.6.2.3.5 testdef=None
222 11:17:01.438286 end: 1.6.2.3.5 git-repo-action (duration 00:00:06) [common]
224 11:17:01.438619 start: 1.6.2.3.6 test-overlay (timeout 00:09:42) [common]
225 11:17:01.439408 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
227 11:17:01.439648 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:42) [common]
228 11:17:01.440855 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
230 11:17:01.441232 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:42) [common]
231 11:17:01.442849 runner path: /var/lib/lava/dispatcher/tmp/10591269/lava-overlay-xzzfx22o/lava-10591269/0/tests/1_kselftest-tpm2 test_uuid 10591269_1.6.2.3.5
232 11:17:01.442970 BOARD='mt8192-asurada-spherion-r0'
233 11:17:01.443068 BRANCH='cip'
234 11:17:01.443156 SKIPFILE='/dev/null'
235 11:17:01.443248 SKIP_INSTALL='True'
236 11:17:01.443356 TESTPROG_URL='http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz'
237 11:17:01.443493 TST_CASENAME=''
238 11:17:01.443578 TST_CMDFILES='tpm2'
239 11:17:01.443766 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
241 11:17:01.444113 Creating lava-test-runner.conf files
242 11:17:01.444206 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10591269/lava-overlay-xzzfx22o/lava-10591269/0 for stage 0
243 11:17:01.444332 - 0_timesync-off
244 11:17:01.444431 - 1_kselftest-tpm2
245 11:17:01.444563 end: 1.6.2.3 test-definition (duration 00:00:06) [common]
246 11:17:01.444681 start: 1.6.2.4 compress-overlay (timeout 00:09:42) [common]
247 11:17:09.221846 end: 1.6.2.4 compress-overlay (duration 00:00:08) [common]
248 11:17:09.222027 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:34) [common]
249 11:17:09.222156 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
250 11:17:09.222285 end: 1.6.2 lava-overlay (duration 00:00:14) [common]
251 11:17:09.222424 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:34) [common]
252 11:17:09.339626 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
253 11:17:09.340009 start: 1.6.4 extract-modules (timeout 00:09:34) [common]
254 11:17:09.340160 extracting modules file /var/lib/lava/dispatcher/tmp/10591269/tftp-deploy-al9f63sa/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10591269/extract-nfsrootfs-e40z_w25
255 11:17:09.620624 extracting modules file /var/lib/lava/dispatcher/tmp/10591269/tftp-deploy-al9f63sa/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10591269/extract-overlay-ramdisk-4gx1zhmg/ramdisk
256 11:17:09.829783 end: 1.6.4 extract-modules (duration 00:00:00) [common]
257 11:17:09.829953 start: 1.6.5 apply-overlay-tftp (timeout 00:09:34) [common]
258 11:17:09.830051 [common] Applying overlay to NFS
259 11:17:09.830123 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10591269/compress-overlay-dqnb7o9m/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10591269/extract-nfsrootfs-e40z_w25
260 11:17:10.729544 end: 1.6.5 apply-overlay-tftp (duration 00:00:01) [common]
261 11:17:10.729705 start: 1.6.6 configure-preseed-file (timeout 00:09:33) [common]
262 11:17:10.729803 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
263 11:17:10.729915 start: 1.6.7 compress-ramdisk (timeout 00:09:33) [common]
264 11:17:10.730013 Building ramdisk /var/lib/lava/dispatcher/tmp/10591269/extract-overlay-ramdisk-4gx1zhmg/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10591269/extract-overlay-ramdisk-4gx1zhmg/ramdisk
265 11:17:11.030934 >> 117801 blocks
266 11:17:13.113117 rename /var/lib/lava/dispatcher/tmp/10591269/extract-overlay-ramdisk-4gx1zhmg/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10591269/tftp-deploy-al9f63sa/ramdisk/ramdisk.cpio.gz
267 11:17:13.113534 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
268 11:17:13.113660 start: 1.6.8 prepare-kernel (timeout 00:09:30) [common]
269 11:17:13.113761 start: 1.6.8.1 prepare-fit (timeout 00:09:30) [common]
270 11:17:13.113871 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10591269/tftp-deploy-al9f63sa/kernel/Image'
271 11:17:25.268796 Returned 0 in 12 seconds
272 11:17:25.369400 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10591269/tftp-deploy-al9f63sa/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10591269/tftp-deploy-al9f63sa/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10591269/tftp-deploy-al9f63sa/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10591269/tftp-deploy-al9f63sa/kernel/image.itb
273 11:17:25.702421 output: FIT description: Kernel Image image with one or more FDT blobs
274 11:17:25.702768 output: Created: Mon Jun 5 12:17:25 2023
275 11:17:25.702846 output: Image 0 (kernel-1)
276 11:17:25.702913 output: Description:
277 11:17:25.702985 output: Created: Mon Jun 5 12:17:25 2023
278 11:17:25.703058 output: Type: Kernel Image
279 11:17:25.703121 output: Compression: lzma compressed
280 11:17:25.703182 output: Data Size: 10086024 Bytes = 9849.63 KiB = 9.62 MiB
281 11:17:25.703242 output: Architecture: AArch64
282 11:17:25.703302 output: OS: Linux
283 11:17:25.703372 output: Load Address: 0x00000000
284 11:17:25.703432 output: Entry Point: 0x00000000
285 11:17:25.703491 output: Hash algo: crc32
286 11:17:25.703546 output: Hash value: eb1cf9b8
287 11:17:25.703601 output: Image 1 (fdt-1)
288 11:17:25.703656 output: Description: mt8192-asurada-spherion-r0
289 11:17:25.703710 output: Created: Mon Jun 5 12:17:25 2023
290 11:17:25.703764 output: Type: Flat Device Tree
291 11:17:25.703819 output: Compression: uncompressed
292 11:17:25.703874 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
293 11:17:25.703928 output: Architecture: AArch64
294 11:17:25.703982 output: Hash algo: crc32
295 11:17:25.704035 output: Hash value: 1df858fa
296 11:17:25.704089 output: Image 2 (ramdisk-1)
297 11:17:25.704143 output: Description: unavailable
298 11:17:25.704196 output: Created: Mon Jun 5 12:17:25 2023
299 11:17:25.704250 output: Type: RAMDisk Image
300 11:17:25.704303 output: Compression: Unknown Compression
301 11:17:25.704356 output: Data Size: 17640170 Bytes = 17226.73 KiB = 16.82 MiB
302 11:17:25.704410 output: Architecture: AArch64
303 11:17:25.704464 output: OS: Linux
304 11:17:25.704517 output: Load Address: unavailable
305 11:17:25.704570 output: Entry Point: unavailable
306 11:17:25.704623 output: Hash algo: crc32
307 11:17:25.704676 output: Hash value: 808d37fa
308 11:17:25.704730 output: Default Configuration: 'conf-1'
309 11:17:25.704784 output: Configuration 0 (conf-1)
310 11:17:25.704838 output: Description: mt8192-asurada-spherion-r0
311 11:17:25.704892 output: Kernel: kernel-1
312 11:17:25.704945 output: Init Ramdisk: ramdisk-1
313 11:17:25.704998 output: FDT: fdt-1
314 11:17:25.705051 output: Loadables: kernel-1
315 11:17:25.705105 output:
316 11:17:25.705309 end: 1.6.8.1 prepare-fit (duration 00:00:13) [common]
317 11:17:25.705410 end: 1.6.8 prepare-kernel (duration 00:00:13) [common]
318 11:17:25.705514 end: 1.6 prepare-tftp-overlay (duration 00:00:33) [common]
319 11:17:25.705615 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:18) [common]
320 11:17:25.705692 No LXC device requested
321 11:17:25.705771 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
322 11:17:25.705856 start: 1.8 deploy-device-env (timeout 00:09:18) [common]
323 11:17:25.705934 end: 1.8 deploy-device-env (duration 00:00:00) [common]
324 11:17:25.706003 Checking files for TFTP limit of 4294967296 bytes.
325 11:17:25.706500 end: 1 tftp-deploy (duration 00:00:42) [common]
326 11:17:25.706619 start: 2 depthcharge-action (timeout 00:05:00) [common]
327 11:17:25.706714 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
328 11:17:25.706840 substitutions:
329 11:17:25.706909 - {DTB}: 10591269/tftp-deploy-al9f63sa/dtb/mt8192-asurada-spherion-r0.dtb
330 11:17:25.706977 - {INITRD}: 10591269/tftp-deploy-al9f63sa/ramdisk/ramdisk.cpio.gz
331 11:17:25.707038 - {KERNEL}: 10591269/tftp-deploy-al9f63sa/kernel/Image
332 11:17:25.707096 - {LAVA_MAC}: None
333 11:17:25.707154 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/10591269/extract-nfsrootfs-e40z_w25
334 11:17:25.707212 - {NFS_SERVER_IP}: 192.168.201.1
335 11:17:25.707268 - {PRESEED_CONFIG}: None
336 11:17:25.707331 - {PRESEED_LOCAL}: None
337 11:17:25.707390 - {RAMDISK}: 10591269/tftp-deploy-al9f63sa/ramdisk/ramdisk.cpio.gz
338 11:17:25.707446 - {ROOT_PART}: None
339 11:17:25.707501 - {ROOT}: None
340 11:17:25.707556 - {SERVER_IP}: 192.168.201.1
341 11:17:25.707611 - {TEE}: None
342 11:17:25.707665 Parsed boot commands:
343 11:17:25.707718 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
344 11:17:25.707907 Parsed boot commands: tftpboot 192.168.201.1 10591269/tftp-deploy-al9f63sa/kernel/image.itb 10591269/tftp-deploy-al9f63sa/kernel/cmdline
345 11:17:25.708001 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
346 11:17:25.708087 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
347 11:17:25.708182 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
348 11:17:25.708271 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
349 11:17:25.708347 Not connected, no need to disconnect.
350 11:17:25.708424 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
351 11:17:25.708507 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
352 11:17:25.708575 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-0'
353 11:17:25.712066 Setting prompt string to ['lava-test: # ']
354 11:17:25.712432 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
355 11:17:25.712542 end: 2.2.1 reset-connection (duration 00:00:00) [common]
356 11:17:25.712647 start: 2.2.2 reset-device (timeout 00:05:00) [common]
357 11:17:25.712735 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
358 11:17:25.712942 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=reboot'
359 11:17:30.851125 >> Command sent successfully.
360 11:17:30.853886 Returned 0 in 5 seconds
361 11:17:30.954372 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
363 11:17:30.954720 end: 2.2.2 reset-device (duration 00:00:05) [common]
364 11:17:30.954835 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
365 11:17:30.954923 Setting prompt string to 'Starting depthcharge on Spherion...'
366 11:17:30.954989 Changing prompt to 'Starting depthcharge on Spherion...'
367 11:17:30.955065 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
368 11:17:30.955413 [Enter `^Ec?' for help]
369 11:17:31.127708
370 11:17:31.127886
371 11:17:31.127992 F0: 102B 0000
372 11:17:31.128098
373 11:17:31.128187 F3: 1001 0000 [0200]
374 11:17:31.128284
375 11:17:31.131431 F3: 1001 0000
376 11:17:31.131522
377 11:17:31.131587 F7: 102D 0000
378 11:17:31.131652
379 11:17:31.131712 F1: 0000 0000
380 11:17:31.131778
381 11:17:31.135196 V0: 0000 0000 [0001]
382 11:17:31.135279
383 11:17:31.135382 00: 0007 8000
384 11:17:31.135449
385 11:17:31.138816 01: 0000 0000
386 11:17:31.138900
387 11:17:31.138966 BP: 0C00 0209 [0000]
388 11:17:31.139027
389 11:17:31.141921 G0: 1182 0000
390 11:17:31.142004
391 11:17:31.142070 EC: 0000 0021 [4000]
392 11:17:31.142131
393 11:17:31.145857 S7: 0000 0000 [0000]
394 11:17:31.145939
395 11:17:31.146005 CC: 0000 0000 [0001]
396 11:17:31.146082
397 11:17:31.148844 T0: 0000 0040 [010F]
398 11:17:31.148932
399 11:17:31.148997 Jump to BL
400 11:17:31.149058
401 11:17:31.175024
402 11:17:31.175149
403 11:17:31.175219
404 11:17:31.182100 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
405 11:17:31.185791 ARM64: Exception handlers installed.
406 11:17:31.189473 ARM64: Testing exception
407 11:17:31.193348 ARM64: Done test exception
408 11:17:31.200733 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
409 11:17:31.207940 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
410 11:17:31.214288 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
411 11:17:31.225394 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
412 11:17:31.231663 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
413 11:17:31.242313 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
414 11:17:31.252480 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
415 11:17:31.259037 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
416 11:17:31.277642 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
417 11:17:31.280857 WDT: Last reset was cold boot
418 11:17:31.283948 SPI1(PAD0) initialized at 2873684 Hz
419 11:17:31.287506 SPI5(PAD0) initialized at 992727 Hz
420 11:17:31.290941 VBOOT: Loading verstage.
421 11:17:31.297622 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
422 11:17:31.301146 FMAP: Found "FLASH" version 1.1 at 0x20000.
423 11:17:31.304629 FMAP: base = 0x0 size = 0x800000 #areas = 25
424 11:17:31.307740 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
425 11:17:31.314979 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
426 11:17:31.321644 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
427 11:17:31.333082 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
428 11:17:31.333222
429 11:17:31.333334
430 11:17:31.343031 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
431 11:17:31.346752 ARM64: Exception handlers installed.
432 11:17:31.346868 ARM64: Testing exception
433 11:17:31.349807 ARM64: Done test exception
434 11:17:31.352955 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
435 11:17:31.360332 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
436 11:17:31.373649 Probing TPM: . done!
437 11:17:31.373776 TPM ready after 0 ms
438 11:17:31.381314 Connected to device vid:did:rid of 1ae0:0028:00
439 11:17:31.387890 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9b9523
440 11:17:31.447273 Initialized TPM device CR50 revision 0
441 11:17:31.458854 tlcl_send_startup: Startup return code is 0
442 11:17:31.458975 TPM: setup succeeded
443 11:17:31.470033 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
444 11:17:31.479154 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
445 11:17:31.493298 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
446 11:17:31.500885 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
447 11:17:31.504421 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
448 11:17:31.508396 in-header: 03 07 00 00 08 00 00 00
449 11:17:31.512019 in-data: aa e4 47 04 13 02 00 00
450 11:17:31.512108 Chrome EC: UHEPI supported
451 11:17:31.519294 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
452 11:17:31.523683 in-header: 03 95 00 00 08 00 00 00
453 11:17:31.526862 in-data: 18 20 20 08 00 00 00 00
454 11:17:31.526948 Phase 1
455 11:17:31.533926 FMAP: area GBB found @ 3f5000 (12032 bytes)
456 11:17:31.537739 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
457 11:17:31.545336 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
458 11:17:31.549233 Recovery requested (1009000e)
459 11:17:31.559071 TPM: Extending digest for VBOOT: boot mode into PCR 0
460 11:17:31.562667 tlcl_extend: response is 0
461 11:17:31.571109 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
462 11:17:31.576736 tlcl_extend: response is 0
463 11:17:31.583965 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
464 11:17:31.603589 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
465 11:17:31.610111 BS: bootblock times (exec / console): total (unknown) / 148 ms
466 11:17:31.610216
467 11:17:31.610286
468 11:17:31.620408 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
469 11:17:31.623489 ARM64: Exception handlers installed.
470 11:17:31.627208 ARM64: Testing exception
471 11:17:31.627296 ARM64: Done test exception
472 11:17:31.649089 pmic_efuse_setting: Set efuses in 11 msecs
473 11:17:31.652352 pmwrap_interface_init: Select PMIF_VLD_RDY
474 11:17:31.659110 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
475 11:17:31.662830 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
476 11:17:31.670040 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
477 11:17:31.673909 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
478 11:17:31.677504 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
479 11:17:31.681216 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
480 11:17:31.688546 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
481 11:17:31.692457 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
482 11:17:31.695719 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
483 11:17:31.703056 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
484 11:17:31.706928 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
485 11:17:31.710351 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
486 11:17:31.713299 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
487 11:17:31.722252 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
488 11:17:31.728813 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
489 11:17:31.733098 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
490 11:17:31.740194 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
491 11:17:31.743879 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
492 11:17:31.751295 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
493 11:17:31.755025 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
494 11:17:31.762463 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
495 11:17:31.766138 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
496 11:17:31.774052 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
497 11:17:31.777653 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
498 11:17:31.781518 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
499 11:17:31.788908 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
500 11:17:31.792687 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
501 11:17:31.799460 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
502 11:17:31.803600 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
503 11:17:31.807516 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
504 11:17:31.814221 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
505 11:17:31.817726 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
506 11:17:31.822079 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
507 11:17:31.828812 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
508 11:17:31.832377 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
509 11:17:31.840202 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
510 11:17:31.843899 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
511 11:17:31.848067 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
512 11:17:31.851645 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
513 11:17:31.855415 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
514 11:17:31.862845 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
515 11:17:31.866721 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
516 11:17:31.869959 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
517 11:17:31.873589 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
518 11:17:31.877452 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
519 11:17:31.884526 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
520 11:17:31.888299 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
521 11:17:31.891971 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
522 11:17:31.895570 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
523 11:17:31.898742 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
524 11:17:31.903108 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
525 11:17:31.910397 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
526 11:17:31.921480 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
527 11:17:31.924808 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
528 11:17:31.932232 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
529 11:17:31.943122 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
530 11:17:31.946709 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
531 11:17:31.950784 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
532 11:17:31.954318 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
533 11:17:31.962357 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde70, sec=0x0
534 11:17:31.966037 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
535 11:17:31.974403 [RTC]rtc_osc_init,62: osc32con val = 0xde70
536 11:17:31.977604 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
537 11:17:31.986267 [RTC]rtc_get_frequency_meter,154: input=15, output=759
538 11:17:31.996751 [RTC]rtc_get_frequency_meter,154: input=23, output=942
539 11:17:32.005769 [RTC]rtc_get_frequency_meter,154: input=19, output=848
540 11:17:32.015593 [RTC]rtc_get_frequency_meter,154: input=17, output=804
541 11:17:32.024838 [RTC]rtc_get_frequency_meter,154: input=16, output=783
542 11:17:32.034590 [RTC]rtc_get_frequency_meter,154: input=16, output=781
543 11:17:32.044429 [RTC]rtc_get_frequency_meter,154: input=17, output=803
544 11:17:32.047599 [RTC]rtc_eosc_cali,47: left: 16, middle: 16, right: 17
545 11:17:32.051598 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde71
546 11:17:32.055192 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
547 11:17:32.062351 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
548 11:17:32.065847 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
549 11:17:32.070291 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
550 11:17:32.074123 ADC[4]: Raw value=905465 ID=7
551 11:17:32.074208 ADC[3]: Raw value=213810 ID=1
552 11:17:32.077255 RAM Code: 0x71
553 11:17:32.081535 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
554 11:17:32.084672 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
555 11:17:32.096931 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
556 11:17:32.100387 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
557 11:17:32.104113 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
558 11:17:32.107739 in-header: 03 07 00 00 08 00 00 00
559 11:17:32.112001 in-data: aa e4 47 04 13 02 00 00
560 11:17:32.115749 Chrome EC: UHEPI supported
561 11:17:32.119432 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
562 11:17:32.123952 in-header: 03 95 00 00 08 00 00 00
563 11:17:32.127614 in-data: 18 20 20 08 00 00 00 00
564 11:17:32.131604 MRC: failed to locate region type 0.
565 11:17:32.138573 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
566 11:17:32.142795 DRAM-K: Running full calibration
567 11:17:32.146311 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
568 11:17:32.150110 header.status = 0x0
569 11:17:32.154180 header.version = 0x6 (expected: 0x6)
570 11:17:32.157726 header.size = 0xd00 (expected: 0xd00)
571 11:17:32.157836 header.flags = 0x0
572 11:17:32.164886 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
573 11:17:32.181781 read SPI 0x72590 0x1c583: 12495 us, 9291 KB/s, 74.328 Mbps
574 11:17:32.189942 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
575 11:17:32.193795 dram_init: ddr_geometry: 2
576 11:17:32.193915 [EMI] MDL number = 2
577 11:17:32.196760 [EMI] Get MDL freq = 0
578 11:17:32.196869 dram_init: ddr_type: 0
579 11:17:32.200506 is_discrete_lpddr4: 1
580 11:17:32.204140 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
581 11:17:32.204247
582 11:17:32.204343
583 11:17:32.204437 [Bian_co] ETT version 0.0.0.1
584 11:17:32.212097 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
585 11:17:32.212205
586 11:17:32.215882 dramc_set_vcore_voltage set vcore to 650000
587 11:17:32.215996 Read voltage for 800, 4
588 11:17:32.216074 Vio18 = 0
589 11:17:32.219575 Vcore = 650000
590 11:17:32.219685 Vdram = 0
591 11:17:32.219781 Vddq = 0
592 11:17:32.223220 Vmddr = 0
593 11:17:32.223374 dram_init: config_dvfs: 1
594 11:17:32.231174 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
595 11:17:32.234478 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
596 11:17:32.238015 [SwImpedanceCal] DRVP=10, DRVN=16, ODTN=9
597 11:17:32.242008 freq_region=0, Reg: DRVP=10, DRVN=16, ODTN=9
598 11:17:32.244823 [SwImpedanceCal] DRVP=16, DRVN=24, ODTN=9
599 11:17:32.248356 freq_region=1, Reg: DRVP=16, DRVN=24, ODTN=9
600 11:17:32.251857 MEM_TYPE=3, freq_sel=18
601 11:17:32.255232 sv_algorithm_assistance_LP4_1600
602 11:17:32.258204 ============ PULL DRAM RESETB DOWN ============
603 11:17:32.262213 ========== PULL DRAM RESETB DOWN end =========
604 11:17:32.269699 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
605 11:17:32.269815 ===================================
606 11:17:32.273677 LPDDR4 DRAM CONFIGURATION
607 11:17:32.276814 ===================================
608 11:17:32.281182 EX_ROW_EN[0] = 0x0
609 11:17:32.281266 EX_ROW_EN[1] = 0x0
610 11:17:32.281332 LP4Y_EN = 0x0
611 11:17:32.284444 WORK_FSP = 0x0
612 11:17:32.284562 WL = 0x2
613 11:17:32.287355 RL = 0x2
614 11:17:32.290978 BL = 0x2
615 11:17:32.291082 RPST = 0x0
616 11:17:32.294293 RD_PRE = 0x0
617 11:17:32.294372 WR_PRE = 0x1
618 11:17:32.297339 WR_PST = 0x0
619 11:17:32.297443 DBI_WR = 0x0
620 11:17:32.301165 DBI_RD = 0x0
621 11:17:32.301273 OTF = 0x1
622 11:17:32.304415 ===================================
623 11:17:32.307872 ===================================
624 11:17:32.307947 ANA top config
625 11:17:32.311596 ===================================
626 11:17:32.314854 DLL_ASYNC_EN = 0
627 11:17:32.318371 ALL_SLAVE_EN = 1
628 11:17:32.321899 NEW_RANK_MODE = 1
629 11:17:32.321985 DLL_IDLE_MODE = 1
630 11:17:32.325452 LP45_APHY_COMB_EN = 1
631 11:17:32.328383 TX_ODT_DIS = 1
632 11:17:32.332640 NEW_8X_MODE = 1
633 11:17:32.332724 ===================================
634 11:17:32.335665 ===================================
635 11:17:32.339392 data_rate = 1600
636 11:17:32.342393 CKR = 1
637 11:17:32.345766 DQ_P2S_RATIO = 8
638 11:17:32.349205 ===================================
639 11:17:32.352496 CA_P2S_RATIO = 8
640 11:17:32.356049 DQ_CA_OPEN = 0
641 11:17:32.356132 DQ_SEMI_OPEN = 0
642 11:17:32.359547 CA_SEMI_OPEN = 0
643 11:17:32.362959 CA_FULL_RATE = 0
644 11:17:32.365811 DQ_CKDIV4_EN = 1
645 11:17:32.369095 CA_CKDIV4_EN = 1
646 11:17:32.372530 CA_PREDIV_EN = 0
647 11:17:32.372604 PH8_DLY = 0
648 11:17:32.376009 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
649 11:17:32.379317 DQ_AAMCK_DIV = 4
650 11:17:32.382655 CA_AAMCK_DIV = 4
651 11:17:32.385851 CA_ADMCK_DIV = 4
652 11:17:32.389256 DQ_TRACK_CA_EN = 0
653 11:17:32.389362 CA_PICK = 800
654 11:17:32.392743 CA_MCKIO = 800
655 11:17:32.396654 MCKIO_SEMI = 0
656 11:17:32.400210 PLL_FREQ = 3068
657 11:17:32.403959 DQ_UI_PI_RATIO = 32
658 11:17:32.404044 CA_UI_PI_RATIO = 0
659 11:17:32.407757 ===================================
660 11:17:32.411336 ===================================
661 11:17:32.415080 memory_type:LPDDR4
662 11:17:32.415170 GP_NUM : 10
663 11:17:32.418626 SRAM_EN : 1
664 11:17:32.418709 MD32_EN : 0
665 11:17:32.422626 ===================================
666 11:17:32.426076 [ANA_INIT] >>>>>>>>>>>>>>
667 11:17:32.429803 <<<<<< [CONFIGURE PHASE]: ANA_TX
668 11:17:32.433285 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
669 11:17:32.436548 ===================================
670 11:17:32.436631 data_rate = 1600,PCW = 0X7600
671 11:17:32.440674 ===================================
672 11:17:32.443622 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
673 11:17:32.450616 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
674 11:17:32.457378 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
675 11:17:32.460421 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
676 11:17:32.463521 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
677 11:17:32.466725 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
678 11:17:32.470105 [ANA_INIT] flow start
679 11:17:32.470192 [ANA_INIT] PLL >>>>>>>>
680 11:17:32.473608 [ANA_INIT] PLL <<<<<<<<
681 11:17:32.476535 [ANA_INIT] MIDPI >>>>>>>>
682 11:17:32.476611 [ANA_INIT] MIDPI <<<<<<<<
683 11:17:32.479969 [ANA_INIT] DLL >>>>>>>>
684 11:17:32.483518 [ANA_INIT] flow end
685 11:17:32.486759 ============ LP4 DIFF to SE enter ============
686 11:17:32.490243 ============ LP4 DIFF to SE exit ============
687 11:17:32.493486 [ANA_INIT] <<<<<<<<<<<<<
688 11:17:32.496710 [Flow] Enable top DCM control >>>>>
689 11:17:32.500338 [Flow] Enable top DCM control <<<<<
690 11:17:32.503631 Enable DLL master slave shuffle
691 11:17:32.507156 ==============================================================
692 11:17:32.510496 Gating Mode config
693 11:17:32.516716 ==============================================================
694 11:17:32.516802 Config description:
695 11:17:32.526705 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
696 11:17:32.533405 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
697 11:17:32.536905 SELPH_MODE 0: By rank 1: By Phase
698 11:17:32.543600 ==============================================================
699 11:17:32.547141 GAT_TRACK_EN = 1
700 11:17:32.550275 RX_GATING_MODE = 2
701 11:17:32.553756 RX_GATING_TRACK_MODE = 2
702 11:17:32.556872 SELPH_MODE = 1
703 11:17:32.560526 PICG_EARLY_EN = 1
704 11:17:32.563617 VALID_LAT_VALUE = 1
705 11:17:32.566609 ==============================================================
706 11:17:32.570206 Enter into Gating configuration >>>>
707 11:17:32.573726 Exit from Gating configuration <<<<
708 11:17:32.577357 Enter into DVFS_PRE_config >>>>>
709 11:17:32.586964 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
710 11:17:32.590302 Exit from DVFS_PRE_config <<<<<
711 11:17:32.593641 Enter into PICG configuration >>>>
712 11:17:32.596985 Exit from PICG configuration <<<<
713 11:17:32.600449 [RX_INPUT] configuration >>>>>
714 11:17:32.603586 [RX_INPUT] configuration <<<<<
715 11:17:32.610609 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
716 11:17:32.613759 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
717 11:17:32.620495 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
718 11:17:32.626731 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
719 11:17:32.633595 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
720 11:17:32.640121 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
721 11:17:32.643427 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
722 11:17:32.646880 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
723 11:17:32.650538 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
724 11:17:32.653475 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
725 11:17:32.660438 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
726 11:17:32.663912 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
727 11:17:32.667058 ===================================
728 11:17:32.670794 LPDDR4 DRAM CONFIGURATION
729 11:17:32.673846 ===================================
730 11:17:32.673929 EX_ROW_EN[0] = 0x0
731 11:17:32.676943 EX_ROW_EN[1] = 0x0
732 11:17:32.677025 LP4Y_EN = 0x0
733 11:17:32.680460 WORK_FSP = 0x0
734 11:17:32.680576 WL = 0x2
735 11:17:32.683787 RL = 0x2
736 11:17:32.683875 BL = 0x2
737 11:17:32.687201 RPST = 0x0
738 11:17:32.687284 RD_PRE = 0x0
739 11:17:32.690614 WR_PRE = 0x1
740 11:17:32.690697 WR_PST = 0x0
741 11:17:32.693625 DBI_WR = 0x0
742 11:17:32.697173 DBI_RD = 0x0
743 11:17:32.697256 OTF = 0x1
744 11:17:32.700741 ===================================
745 11:17:32.703987 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
746 11:17:32.707435 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
747 11:17:32.714194 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
748 11:17:32.717299 ===================================
749 11:17:32.717382 LPDDR4 DRAM CONFIGURATION
750 11:17:32.721133 ===================================
751 11:17:32.724091 EX_ROW_EN[0] = 0x10
752 11:17:32.727903 EX_ROW_EN[1] = 0x0
753 11:17:32.727986 LP4Y_EN = 0x0
754 11:17:32.730695 WORK_FSP = 0x0
755 11:17:32.730813 WL = 0x2
756 11:17:32.734144 RL = 0x2
757 11:17:32.734285 BL = 0x2
758 11:17:32.737189 RPST = 0x0
759 11:17:32.737295 RD_PRE = 0x0
760 11:17:32.740724 WR_PRE = 0x1
761 11:17:32.740810 WR_PST = 0x0
762 11:17:32.744363 DBI_WR = 0x0
763 11:17:32.744447 DBI_RD = 0x0
764 11:17:32.747409 OTF = 0x1
765 11:17:32.751129 ===================================
766 11:17:32.757678 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
767 11:17:32.760816 nWR fixed to 40
768 11:17:32.760902 [ModeRegInit_LP4] CH0 RK0
769 11:17:32.764307 [ModeRegInit_LP4] CH0 RK1
770 11:17:32.767391 [ModeRegInit_LP4] CH1 RK0
771 11:17:32.771056 [ModeRegInit_LP4] CH1 RK1
772 11:17:32.771140 match AC timing 13
773 11:17:32.774136 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
774 11:17:32.780570 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
775 11:17:32.784190 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
776 11:17:32.787700 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
777 11:17:32.794189 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
778 11:17:32.794276 [EMI DOE] emi_dcm 0
779 11:17:32.800686 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
780 11:17:32.800771 ==
781 11:17:32.803953 Dram Type= 6, Freq= 0, CH_0, rank 0
782 11:17:32.807482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
783 11:17:32.807580 ==
784 11:17:32.814436 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
785 11:17:32.817436 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
786 11:17:32.827299 [CA 0] Center 36 (6~67) winsize 62
787 11:17:32.831071 [CA 1] Center 36 (6~67) winsize 62
788 11:17:32.834083 [CA 2] Center 34 (4~65) winsize 62
789 11:17:32.837981 [CA 3] Center 34 (4~64) winsize 61
790 11:17:32.841028 [CA 4] Center 33 (3~63) winsize 61
791 11:17:32.844073 [CA 5] Center 32 (2~62) winsize 61
792 11:17:32.844156
793 11:17:32.847701 [CmdBusTrainingLP45] Vref(ca) range 1: 32
794 11:17:32.847785
795 11:17:32.850692 [CATrainingPosCal] consider 1 rank data
796 11:17:32.854513 u2DelayCellTimex100 = 270/100 ps
797 11:17:32.857654 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
798 11:17:32.860699 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
799 11:17:32.867635 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
800 11:17:32.871177 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
801 11:17:32.873975 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
802 11:17:32.877927 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
803 11:17:32.878027
804 11:17:32.880869 CA PerBit enable=1, Macro0, CA PI delay=32
805 11:17:32.880984
806 11:17:32.884047 [CBTSetCACLKResult] CA Dly = 32
807 11:17:32.884148 CS Dly: 4 (0~35)
808 11:17:32.884246 ==
809 11:17:32.887830 Dram Type= 6, Freq= 0, CH_0, rank 1
810 11:17:32.894627 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
811 11:17:32.894726 ==
812 11:17:32.897626 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
813 11:17:32.904807 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
814 11:17:32.913458 [CA 0] Center 36 (6~67) winsize 62
815 11:17:32.917272 [CA 1] Center 36 (6~67) winsize 62
816 11:17:32.920173 [CA 2] Center 34 (3~65) winsize 63
817 11:17:32.923469 [CA 3] Center 33 (3~64) winsize 62
818 11:17:32.927281 [CA 4] Center 33 (3~63) winsize 61
819 11:17:32.930384 [CA 5] Center 32 (2~63) winsize 62
820 11:17:32.930468
821 11:17:32.933558 [CmdBusTrainingLP45] Vref(ca) range 1: 34
822 11:17:32.933642
823 11:17:32.937116 [CATrainingPosCal] consider 2 rank data
824 11:17:32.940356 u2DelayCellTimex100 = 270/100 ps
825 11:17:32.944008 CA0 delay=36 (6~67),Diff = 4 PI (28 cell)
826 11:17:32.947151 CA1 delay=36 (6~67),Diff = 4 PI (28 cell)
827 11:17:32.953784 CA2 delay=34 (4~65),Diff = 2 PI (14 cell)
828 11:17:32.957025 CA3 delay=34 (4~64),Diff = 2 PI (14 cell)
829 11:17:32.960595 CA4 delay=33 (3~63),Diff = 1 PI (7 cell)
830 11:17:32.963879 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
831 11:17:32.963978
832 11:17:32.967288 CA PerBit enable=1, Macro0, CA PI delay=32
833 11:17:32.967413
834 11:17:32.970360 [CBTSetCACLKResult] CA Dly = 32
835 11:17:32.970444 CS Dly: 4 (0~36)
836 11:17:32.970533
837 11:17:32.974306 ----->DramcWriteLeveling(PI) begin...
838 11:17:32.974392 ==
839 11:17:32.977932 Dram Type= 6, Freq= 0, CH_0, rank 0
840 11:17:32.981894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
841 11:17:32.985615 ==
842 11:17:32.985698 Write leveling (Byte 0): 32 => 32
843 11:17:32.989457 Write leveling (Byte 1): 29 => 29
844 11:17:32.992543 DramcWriteLeveling(PI) end<-----
845 11:17:32.992627
846 11:17:32.992693 ==
847 11:17:32.996206 Dram Type= 6, Freq= 0, CH_0, rank 0
848 11:17:32.999359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
849 11:17:32.999458 ==
850 11:17:33.002773 [Gating] SW mode calibration
851 11:17:33.010254 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
852 11:17:33.016687 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
853 11:17:33.020175 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
854 11:17:33.023448 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
855 11:17:33.030163 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
856 11:17:33.033190 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 11:17:33.036659 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 11:17:33.040380 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 11:17:33.047186 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 11:17:33.050312 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 11:17:33.053324 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 11:17:33.060059 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 11:17:33.063796 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 11:17:33.066972 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 11:17:33.073706 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 11:17:33.077363 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 11:17:33.080229 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
868 11:17:33.086999 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
869 11:17:33.090692 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 11:17:33.093670 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
871 11:17:33.097363 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
872 11:17:33.103529 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 11:17:33.106906 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 11:17:33.113888 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 11:17:33.116797 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 11:17:33.120329 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
877 11:17:33.123838 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
878 11:17:33.130894 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 1)
879 11:17:33.133891 0 9 8 | B1->B0 | 2323 3332 | 0 1 | (0 0) (1 1)
880 11:17:33.137026 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
881 11:17:33.143528 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 11:17:33.147162 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 11:17:33.150265 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
884 11:17:33.157161 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
885 11:17:33.160180 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
886 11:17:33.163990 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
887 11:17:33.170305 0 10 8 | B1->B0 | 2e2e 2626 | 1 0 | (1 0) (0 0)
888 11:17:33.174078 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
889 11:17:33.177080 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 11:17:33.183841 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 11:17:33.186846 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 11:17:33.190280 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 11:17:33.197026 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
894 11:17:33.200936 0 11 4 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
895 11:17:33.203679 0 11 8 | B1->B0 | 2d2d 3e3e | 1 0 | (0 0) (0 0)
896 11:17:33.207215 0 11 12 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
897 11:17:33.213872 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 11:17:33.217409 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 11:17:33.220401 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 11:17:33.227165 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 11:17:33.230596 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
902 11:17:33.233594 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
903 11:17:33.240665 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
904 11:17:33.244062 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 11:17:33.246986 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 11:17:33.254407 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 11:17:33.257388 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 11:17:33.260608 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 11:17:33.264123 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 11:17:33.271099 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 11:17:33.274088 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 11:17:33.277268 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 11:17:33.284026 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
914 11:17:33.287572 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 11:17:33.290651 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 11:17:33.297344 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 11:17:33.301076 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 11:17:33.304141 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 11:17:33.310850 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
920 11:17:33.310937 Total UI for P1: 0, mck2ui 16
921 11:17:33.317749 best dqsien dly found for B0: ( 0, 14, 4)
922 11:17:33.321410 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
923 11:17:33.324612 Total UI for P1: 0, mck2ui 16
924 11:17:33.327789 best dqsien dly found for B1: ( 0, 14, 8)
925 11:17:33.331805 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
926 11:17:33.334916 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
927 11:17:33.335001
928 11:17:33.338538 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
929 11:17:33.341379 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
930 11:17:33.344926 [Gating] SW calibration Done
931 11:17:33.345011 ==
932 11:17:33.348044 Dram Type= 6, Freq= 0, CH_0, rank 0
933 11:17:33.351458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 11:17:33.351545 ==
935 11:17:33.354968 RX Vref Scan: 0
936 11:17:33.355054
937 11:17:33.355121 RX Vref 0 -> 0, step: 1
938 11:17:33.355184
939 11:17:33.358416 RX Delay -130 -> 252, step: 16
940 11:17:33.362061 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
941 11:17:33.368125 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
942 11:17:33.371890 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
943 11:17:33.375087 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
944 11:17:33.378216 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
945 11:17:33.381873 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
946 11:17:33.388127 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
947 11:17:33.391669 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
948 11:17:33.394974 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
949 11:17:33.398509 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
950 11:17:33.402111 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
951 11:17:33.408257 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
952 11:17:33.411916 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
953 11:17:33.414779 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
954 11:17:33.418633 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
955 11:17:33.421777 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
956 11:17:33.425374 ==
957 11:17:33.425461 Dram Type= 6, Freq= 0, CH_0, rank 0
958 11:17:33.432050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 11:17:33.432139 ==
960 11:17:33.432209 DQS Delay:
961 11:17:33.435142 DQS0 = 0, DQS1 = 0
962 11:17:33.435228 DQM Delay:
963 11:17:33.438754 DQM0 = 93, DQM1 = 86
964 11:17:33.438842 DQ Delay:
965 11:17:33.441682 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
966 11:17:33.445230 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
967 11:17:33.448153 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =77
968 11:17:33.451545 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
969 11:17:33.451630
970 11:17:33.451696
971 11:17:33.451758 ==
972 11:17:33.455020 Dram Type= 6, Freq= 0, CH_0, rank 0
973 11:17:33.458620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 11:17:33.458705 ==
975 11:17:33.458771
976 11:17:33.458833
977 11:17:33.462233 TX Vref Scan disable
978 11:17:33.465397 == TX Byte 0 ==
979 11:17:33.468463 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
980 11:17:33.472150 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
981 11:17:33.472235 == TX Byte 1 ==
982 11:17:33.479064 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
983 11:17:33.482105 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
984 11:17:33.482189 ==
985 11:17:33.485137 Dram Type= 6, Freq= 0, CH_0, rank 0
986 11:17:33.488462 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
987 11:17:33.488551 ==
988 11:17:33.503093 TX Vref=22, minBit 8, minWin=27, winSum=448
989 11:17:33.506722 TX Vref=24, minBit 0, minWin=28, winSum=452
990 11:17:33.509701 TX Vref=26, minBit 8, minWin=27, winSum=453
991 11:17:33.513417 TX Vref=28, minBit 8, minWin=28, winSum=456
992 11:17:33.516780 TX Vref=30, minBit 5, minWin=28, winSum=456
993 11:17:33.519640 TX Vref=32, minBit 2, minWin=28, winSum=452
994 11:17:33.526411 [TxChooseVref] Worse bit 8, Min win 28, Win sum 456, Final Vref 28
995 11:17:33.526546
996 11:17:33.530253 Final TX Range 1 Vref 28
997 11:17:33.530363
998 11:17:33.530437 ==
999 11:17:33.533260 Dram Type= 6, Freq= 0, CH_0, rank 0
1000 11:17:33.536388 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1001 11:17:33.536476 ==
1002 11:17:33.536572
1003 11:17:33.536638
1004 11:17:33.539862 TX Vref Scan disable
1005 11:17:33.543290 == TX Byte 0 ==
1006 11:17:33.546455 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1007 11:17:33.549969 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1008 11:17:33.553638 == TX Byte 1 ==
1009 11:17:33.556437 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1010 11:17:33.560171 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1011 11:17:33.560256
1012 11:17:33.563301 [DATLAT]
1013 11:17:33.563409 Freq=800, CH0 RK0
1014 11:17:33.563476
1015 11:17:33.566678 DATLAT Default: 0xa
1016 11:17:33.566761 0, 0xFFFF, sum = 0
1017 11:17:33.570426 1, 0xFFFF, sum = 0
1018 11:17:33.570515 2, 0xFFFF, sum = 0
1019 11:17:33.573355 3, 0xFFFF, sum = 0
1020 11:17:33.573438 4, 0xFFFF, sum = 0
1021 11:17:33.576509 5, 0xFFFF, sum = 0
1022 11:17:33.576606 6, 0xFFFF, sum = 0
1023 11:17:33.580219 7, 0xFFFF, sum = 0
1024 11:17:33.580304 8, 0xFFFF, sum = 0
1025 11:17:33.583286 9, 0x0, sum = 1
1026 11:17:33.583377 10, 0x0, sum = 2
1027 11:17:33.586608 11, 0x0, sum = 3
1028 11:17:33.586692 12, 0x0, sum = 4
1029 11:17:33.590422 best_step = 10
1030 11:17:33.590505
1031 11:17:33.590571 ==
1032 11:17:33.593476 Dram Type= 6, Freq= 0, CH_0, rank 0
1033 11:17:33.596601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1034 11:17:33.596687 ==
1035 11:17:33.600487 RX Vref Scan: 1
1036 11:17:33.600571
1037 11:17:33.600636 Set Vref Range= 32 -> 127
1038 11:17:33.600697
1039 11:17:33.603517 RX Vref 32 -> 127, step: 1
1040 11:17:33.603613
1041 11:17:33.607153 RX Delay -79 -> 252, step: 8
1042 11:17:33.607238
1043 11:17:33.610018 Set Vref, RX VrefLevel [Byte0]: 32
1044 11:17:33.613516 [Byte1]: 32
1045 11:17:33.613657
1046 11:17:33.616789 Set Vref, RX VrefLevel [Byte0]: 33
1047 11:17:33.620316 [Byte1]: 33
1048 11:17:33.620399
1049 11:17:33.623457 Set Vref, RX VrefLevel [Byte0]: 34
1050 11:17:33.626700 [Byte1]: 34
1051 11:17:33.630683
1052 11:17:33.630765 Set Vref, RX VrefLevel [Byte0]: 35
1053 11:17:33.634284 [Byte1]: 35
1054 11:17:33.638676
1055 11:17:33.638751 Set Vref, RX VrefLevel [Byte0]: 36
1056 11:17:33.642336 [Byte1]: 36
1057 11:17:33.646399
1058 11:17:33.646518 Set Vref, RX VrefLevel [Byte0]: 37
1059 11:17:33.649552 [Byte1]: 37
1060 11:17:33.653851
1061 11:17:33.653955 Set Vref, RX VrefLevel [Byte0]: 38
1062 11:17:33.656944 [Byte1]: 38
1063 11:17:33.660956
1064 11:17:33.661048 Set Vref, RX VrefLevel [Byte0]: 39
1065 11:17:33.664676 [Byte1]: 39
1066 11:17:33.668713
1067 11:17:33.668796 Set Vref, RX VrefLevel [Byte0]: 40
1068 11:17:33.671953 [Byte1]: 40
1069 11:17:33.676047
1070 11:17:33.676130 Set Vref, RX VrefLevel [Byte0]: 41
1071 11:17:33.679425 [Byte1]: 41
1072 11:17:33.683748
1073 11:17:33.683831 Set Vref, RX VrefLevel [Byte0]: 42
1074 11:17:33.686978 [Byte1]: 42
1075 11:17:33.691455
1076 11:17:33.691539 Set Vref, RX VrefLevel [Byte0]: 43
1077 11:17:33.694522 [Byte1]: 43
1078 11:17:33.698851
1079 11:17:33.698962 Set Vref, RX VrefLevel [Byte0]: 44
1080 11:17:33.701980 [Byte1]: 44
1081 11:17:33.706315
1082 11:17:33.706420 Set Vref, RX VrefLevel [Byte0]: 45
1083 11:17:33.709581 [Byte1]: 45
1084 11:17:33.713478
1085 11:17:33.713585 Set Vref, RX VrefLevel [Byte0]: 46
1086 11:17:33.717253 [Byte1]: 46
1087 11:17:33.721396
1088 11:17:33.721510 Set Vref, RX VrefLevel [Byte0]: 47
1089 11:17:33.724503 [Byte1]: 47
1090 11:17:33.729111
1091 11:17:33.729194 Set Vref, RX VrefLevel [Byte0]: 48
1092 11:17:33.732441 [Byte1]: 48
1093 11:17:33.736419
1094 11:17:33.736545 Set Vref, RX VrefLevel [Byte0]: 49
1095 11:17:33.739577 [Byte1]: 49
1096 11:17:33.743695
1097 11:17:33.743777 Set Vref, RX VrefLevel [Byte0]: 50
1098 11:17:33.747302 [Byte1]: 50
1099 11:17:33.751534
1100 11:17:33.751642 Set Vref, RX VrefLevel [Byte0]: 51
1101 11:17:33.754567 [Byte1]: 51
1102 11:17:33.758839
1103 11:17:33.758921 Set Vref, RX VrefLevel [Byte0]: 52
1104 11:17:33.762578 [Byte1]: 52
1105 11:17:33.766629
1106 11:17:33.766711 Set Vref, RX VrefLevel [Byte0]: 53
1107 11:17:33.769672 [Byte1]: 53
1108 11:17:33.773946
1109 11:17:33.774079 Set Vref, RX VrefLevel [Byte0]: 54
1110 11:17:33.777642 [Byte1]: 54
1111 11:17:33.781498
1112 11:17:33.781580 Set Vref, RX VrefLevel [Byte0]: 55
1113 11:17:33.785139 [Byte1]: 55
1114 11:17:33.789242
1115 11:17:33.789327 Set Vref, RX VrefLevel [Byte0]: 56
1116 11:17:33.792825 [Byte1]: 56
1117 11:17:33.796859
1118 11:17:33.796941 Set Vref, RX VrefLevel [Byte0]: 57
1119 11:17:33.800315 [Byte1]: 57
1120 11:17:33.804660
1121 11:17:33.804742 Set Vref, RX VrefLevel [Byte0]: 58
1122 11:17:33.807765 [Byte1]: 58
1123 11:17:33.811673
1124 11:17:33.811755 Set Vref, RX VrefLevel [Byte0]: 59
1125 11:17:33.815089 [Byte1]: 59
1126 11:17:33.819363
1127 11:17:33.819438 Set Vref, RX VrefLevel [Byte0]: 60
1128 11:17:33.822729 [Byte1]: 60
1129 11:17:33.826965
1130 11:17:33.827043 Set Vref, RX VrefLevel [Byte0]: 61
1131 11:17:33.830210 [Byte1]: 61
1132 11:17:33.834494
1133 11:17:33.834571 Set Vref, RX VrefLevel [Byte0]: 62
1134 11:17:33.837521 [Byte1]: 62
1135 11:17:33.841768
1136 11:17:33.841846 Set Vref, RX VrefLevel [Byte0]: 63
1137 11:17:33.845077 [Byte1]: 63
1138 11:17:33.849823
1139 11:17:33.849941 Set Vref, RX VrefLevel [Byte0]: 64
1140 11:17:33.852850 [Byte1]: 64
1141 11:17:33.857202
1142 11:17:33.857292 Set Vref, RX VrefLevel [Byte0]: 65
1143 11:17:33.860657 [Byte1]: 65
1144 11:17:33.864807
1145 11:17:33.864912 Set Vref, RX VrefLevel [Byte0]: 66
1146 11:17:33.868281 [Byte1]: 66
1147 11:17:33.871976
1148 11:17:33.872057 Set Vref, RX VrefLevel [Byte0]: 67
1149 11:17:33.875527 [Byte1]: 67
1150 11:17:33.880188
1151 11:17:33.880273 Set Vref, RX VrefLevel [Byte0]: 68
1152 11:17:33.883050 [Byte1]: 68
1153 11:17:33.887815
1154 11:17:33.887899 Set Vref, RX VrefLevel [Byte0]: 69
1155 11:17:33.890610 [Byte1]: 69
1156 11:17:33.895038
1157 11:17:33.898189 Set Vref, RX VrefLevel [Byte0]: 70
1158 11:17:33.898294 [Byte1]: 70
1159 11:17:33.902457
1160 11:17:33.902544 Set Vref, RX VrefLevel [Byte0]: 71
1161 11:17:33.905666 [Byte1]: 71
1162 11:17:33.910031
1163 11:17:33.910141 Set Vref, RX VrefLevel [Byte0]: 72
1164 11:17:33.913280 [Byte1]: 72
1165 11:17:33.917459
1166 11:17:33.917564 Set Vref, RX VrefLevel [Byte0]: 73
1167 11:17:33.920552 [Byte1]: 73
1168 11:17:33.924913
1169 11:17:33.925021 Set Vref, RX VrefLevel [Byte0]: 74
1170 11:17:33.928426 [Byte1]: 74
1171 11:17:33.932345
1172 11:17:33.932456 Set Vref, RX VrefLevel [Byte0]: 75
1173 11:17:33.936058 [Byte1]: 75
1174 11:17:33.940482
1175 11:17:33.940600 Set Vref, RX VrefLevel [Byte0]: 76
1176 11:17:33.943544 [Byte1]: 76
1177 11:17:33.947825
1178 11:17:33.947958 Set Vref, RX VrefLevel [Byte0]: 77
1179 11:17:33.951544 [Byte1]: 77
1180 11:17:33.955617
1181 11:17:33.955722 Final RX Vref Byte 0 = 51 to rank0
1182 11:17:33.958337 Final RX Vref Byte 1 = 59 to rank0
1183 11:17:33.961668 Final RX Vref Byte 0 = 51 to rank1
1184 11:17:33.965366 Final RX Vref Byte 1 = 59 to rank1==
1185 11:17:33.968907 Dram Type= 6, Freq= 0, CH_0, rank 0
1186 11:17:33.975256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1187 11:17:33.975403 ==
1188 11:17:33.975474 DQS Delay:
1189 11:17:33.975536 DQS0 = 0, DQS1 = 0
1190 11:17:33.978673 DQM Delay:
1191 11:17:33.978778 DQM0 = 91, DQM1 = 85
1192 11:17:33.981758 DQ Delay:
1193 11:17:33.985048 DQ0 =88, DQ1 =96, DQ2 =88, DQ3 =88
1194 11:17:33.988510 DQ4 =92, DQ5 =80, DQ6 =100, DQ7 =100
1195 11:17:33.992224 DQ8 =76, DQ9 =76, DQ10 =84, DQ11 =76
1196 11:17:33.995242 DQ12 =92, DQ13 =92, DQ14 =92, DQ15 =92
1197 11:17:33.995410
1198 11:17:33.995503
1199 11:17:34.002401 [DQSOSCAuto] RK0, (LSB)MR18= 0x4b41, (MSB)MR19= 0x606, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
1200 11:17:34.005589 CH0 RK0: MR19=606, MR18=4B41
1201 11:17:34.011721 CH0_RK0: MR19=0x606, MR18=0x4B41, DQSOSC=391, MR23=63, INC=96, DEC=64
1202 11:17:34.011872
1203 11:17:34.015403 ----->DramcWriteLeveling(PI) begin...
1204 11:17:34.015512 ==
1205 11:17:34.018799 Dram Type= 6, Freq= 0, CH_0, rank 1
1206 11:17:34.021706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1207 11:17:34.021814 ==
1208 11:17:34.025128 Write leveling (Byte 0): 32 => 32
1209 11:17:34.028579 Write leveling (Byte 1): 27 => 27
1210 11:17:34.031722 DramcWriteLeveling(PI) end<-----
1211 11:17:34.031805
1212 11:17:34.031868 ==
1213 11:17:34.035401 Dram Type= 6, Freq= 0, CH_0, rank 1
1214 11:17:34.039039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1215 11:17:34.039133 ==
1216 11:17:34.042265 [Gating] SW mode calibration
1217 11:17:34.049023 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1218 11:17:34.093009 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1219 11:17:34.093364 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1220 11:17:34.093517 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1221 11:17:34.093588 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1222 11:17:34.093654 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1223 11:17:34.093736 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1224 11:17:34.093798 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1225 11:17:34.093859 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1226 11:17:34.093985 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1227 11:17:34.094060 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1228 11:17:34.136931 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1229 11:17:34.137563 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1230 11:17:34.137887 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1231 11:17:34.137959 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1232 11:17:34.138026 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1233 11:17:34.138110 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1234 11:17:34.138204 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1235 11:17:34.138317 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1236 11:17:34.138381 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1237 11:17:34.138439 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1238 11:17:34.181118 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1239 11:17:34.181774 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1240 11:17:34.182046 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1241 11:17:34.182149 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1242 11:17:34.182257 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1243 11:17:34.182392 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1244 11:17:34.182477 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1245 11:17:34.182546 0 9 8 | B1->B0 | 3131 2828 | 0 0 | (0 0) (0 0)
1246 11:17:34.182643 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1247 11:17:34.182701 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1248 11:17:34.185874 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1249 11:17:34.189435 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1250 11:17:34.195995 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1251 11:17:34.199157 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1252 11:17:34.203007 0 10 4 | B1->B0 | 3333 3232 | 0 1 | (0 0) (1 1)
1253 11:17:34.209383 0 10 8 | B1->B0 | 2828 2727 | 0 0 | (0 0) (0 0)
1254 11:17:34.212969 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 11:17:34.216086 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 11:17:34.219830 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 11:17:34.227313 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 11:17:34.231231 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1259 11:17:34.234817 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1260 11:17:34.238204 0 11 4 | B1->B0 | 2828 2424 | 0 0 | (0 0) (0 0)
1261 11:17:34.244898 0 11 8 | B1->B0 | 3f3f 4141 | 0 0 | (0 0) (0 0)
1262 11:17:34.248661 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1263 11:17:34.251737 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1264 11:17:34.255303 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1265 11:17:34.261631 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1266 11:17:34.265231 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1267 11:17:34.268735 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1268 11:17:34.275306 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1269 11:17:34.278405 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1270 11:17:34.281909 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1271 11:17:34.288476 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1272 11:17:34.291736 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1273 11:17:34.295227 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1274 11:17:34.302163 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1275 11:17:34.304989 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1276 11:17:34.308633 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1277 11:17:34.315433 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1278 11:17:34.318495 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1279 11:17:34.321837 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1280 11:17:34.328637 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1281 11:17:34.331807 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1282 11:17:34.335031 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1283 11:17:34.338893 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1284 11:17:34.345094 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1285 11:17:34.348623 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1286 11:17:34.351687 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1287 11:17:34.355450 Total UI for P1: 0, mck2ui 16
1288 11:17:34.359015 best dqsien dly found for B0: ( 0, 14, 8)
1289 11:17:34.365090 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1290 11:17:34.365182 Total UI for P1: 0, mck2ui 16
1291 11:17:34.371625 best dqsien dly found for B1: ( 0, 14, 12)
1292 11:17:34.375445 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1293 11:17:34.378304 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
1294 11:17:34.378388
1295 11:17:34.381733 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1296 11:17:34.385264 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
1297 11:17:34.388295 [Gating] SW calibration Done
1298 11:17:34.388376 ==
1299 11:17:34.392039 Dram Type= 6, Freq= 0, CH_0, rank 1
1300 11:17:34.395507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1301 11:17:34.395598 ==
1302 11:17:34.398428 RX Vref Scan: 0
1303 11:17:34.398547
1304 11:17:34.398642 RX Vref 0 -> 0, step: 1
1305 11:17:34.398741
1306 11:17:34.401795 RX Delay -130 -> 252, step: 16
1307 11:17:34.405220 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1308 11:17:34.412242 iDelay=206, Bit 1, Center 93 (-18 ~ 205) 224
1309 11:17:34.415414 iDelay=206, Bit 2, Center 93 (-18 ~ 205) 224
1310 11:17:34.418921 iDelay=206, Bit 3, Center 93 (-18 ~ 205) 224
1311 11:17:34.422636 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1312 11:17:34.425429 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1313 11:17:34.431901 iDelay=206, Bit 6, Center 101 (-2 ~ 205) 208
1314 11:17:34.435787 iDelay=206, Bit 7, Center 101 (-2 ~ 205) 208
1315 11:17:34.438634 iDelay=206, Bit 8, Center 77 (-34 ~ 189) 224
1316 11:17:34.442615 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1317 11:17:34.445463 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1318 11:17:34.451849 iDelay=206, Bit 11, Center 77 (-34 ~ 189) 224
1319 11:17:34.455619 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1320 11:17:34.459397 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1321 11:17:34.462241 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1322 11:17:34.465562 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1323 11:17:34.465682 ==
1324 11:17:34.469299 Dram Type= 6, Freq= 0, CH_0, rank 1
1325 11:17:34.475790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1326 11:17:34.475876 ==
1327 11:17:34.475942 DQS Delay:
1328 11:17:34.479248 DQS0 = 0, DQS1 = 0
1329 11:17:34.479414 DQM Delay:
1330 11:17:34.479519 DQM0 = 93, DQM1 = 84
1331 11:17:34.482241 DQ Delay:
1332 11:17:34.485469 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
1333 11:17:34.489063 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =101
1334 11:17:34.492156 DQ8 =77, DQ9 =69, DQ10 =77, DQ11 =77
1335 11:17:34.495453 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1336 11:17:34.495546
1337 11:17:34.495664
1338 11:17:34.495784 ==
1339 11:17:34.498673 Dram Type= 6, Freq= 0, CH_0, rank 1
1340 11:17:34.502490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1341 11:17:34.502568 ==
1342 11:17:34.502631
1343 11:17:34.502688
1344 11:17:34.505762 TX Vref Scan disable
1345 11:17:34.508708 == TX Byte 0 ==
1346 11:17:34.512108 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1347 11:17:34.515513 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1348 11:17:34.519179 == TX Byte 1 ==
1349 11:17:34.522077 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1350 11:17:34.525683 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1351 11:17:34.525791 ==
1352 11:17:34.529048 Dram Type= 6, Freq= 0, CH_0, rank 1
1353 11:17:34.532092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1354 11:17:34.532195 ==
1355 11:17:34.547150 TX Vref=22, minBit 8, minWin=27, winSum=447
1356 11:17:34.550481 TX Vref=24, minBit 12, minWin=27, winSum=451
1357 11:17:34.554383 TX Vref=26, minBit 4, minWin=28, winSum=457
1358 11:17:34.557248 TX Vref=28, minBit 9, minWin=28, winSum=461
1359 11:17:34.560300 TX Vref=30, minBit 4, minWin=28, winSum=458
1360 11:17:34.563845 TX Vref=32, minBit 7, minWin=28, winSum=460
1361 11:17:34.570740 [TxChooseVref] Worse bit 9, Min win 28, Win sum 461, Final Vref 28
1362 11:17:34.570879
1363 11:17:34.573677 Final TX Range 1 Vref 28
1364 11:17:34.573767
1365 11:17:34.573868 ==
1366 11:17:34.576894 Dram Type= 6, Freq= 0, CH_0, rank 1
1367 11:17:34.580328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1368 11:17:34.580448 ==
1369 11:17:34.580540
1370 11:17:34.584106
1371 11:17:34.584220 TX Vref Scan disable
1372 11:17:34.587152 == TX Byte 0 ==
1373 11:17:34.590792 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
1374 11:17:34.593956 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
1375 11:17:34.597541 == TX Byte 1 ==
1376 11:17:34.600667 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1377 11:17:34.603725 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1378 11:17:34.607166
1379 11:17:34.607249 [DATLAT]
1380 11:17:34.607315 Freq=800, CH0 RK1
1381 11:17:34.607397
1382 11:17:34.610713 DATLAT Default: 0xa
1383 11:17:34.610795 0, 0xFFFF, sum = 0
1384 11:17:34.614175 1, 0xFFFF, sum = 0
1385 11:17:34.614262 2, 0xFFFF, sum = 0
1386 11:17:34.617213 3, 0xFFFF, sum = 0
1387 11:17:34.617333 4, 0xFFFF, sum = 0
1388 11:17:34.620795 5, 0xFFFF, sum = 0
1389 11:17:34.620882 6, 0xFFFF, sum = 0
1390 11:17:34.623972 7, 0xFFFF, sum = 0
1391 11:17:34.624055 8, 0xFFFF, sum = 0
1392 11:17:34.627252 9, 0x0, sum = 1
1393 11:17:34.627376 10, 0x0, sum = 2
1394 11:17:34.630765 11, 0x0, sum = 3
1395 11:17:34.630878 12, 0x0, sum = 4
1396 11:17:34.634414 best_step = 10
1397 11:17:34.634511
1398 11:17:34.634597 ==
1399 11:17:34.637341 Dram Type= 6, Freq= 0, CH_0, rank 1
1400 11:17:34.640562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1401 11:17:34.640673 ==
1402 11:17:34.644225 RX Vref Scan: 0
1403 11:17:34.644304
1404 11:17:34.644380 RX Vref 0 -> 0, step: 1
1405 11:17:34.644439
1406 11:17:34.647411 RX Delay -95 -> 252, step: 8
1407 11:17:34.654490 iDelay=209, Bit 0, Center 92 (-15 ~ 200) 216
1408 11:17:34.657379 iDelay=209, Bit 1, Center 96 (-7 ~ 200) 208
1409 11:17:34.660644 iDelay=209, Bit 2, Center 88 (-23 ~ 200) 224
1410 11:17:34.664246 iDelay=209, Bit 3, Center 92 (-15 ~ 200) 216
1411 11:17:34.667823 iDelay=209, Bit 4, Center 96 (-15 ~ 208) 224
1412 11:17:34.670883 iDelay=209, Bit 5, Center 84 (-23 ~ 192) 216
1413 11:17:34.677444 iDelay=209, Bit 6, Center 96 (-7 ~ 200) 208
1414 11:17:34.681084 iDelay=209, Bit 7, Center 100 (-7 ~ 208) 216
1415 11:17:34.684266 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
1416 11:17:34.687543 iDelay=209, Bit 9, Center 72 (-31 ~ 176) 208
1417 11:17:34.690975 iDelay=209, Bit 10, Center 84 (-23 ~ 192) 216
1418 11:17:34.697683 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
1419 11:17:34.701010 iDelay=209, Bit 12, Center 88 (-15 ~ 192) 208
1420 11:17:34.704613 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
1421 11:17:34.707880 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
1422 11:17:34.713971 iDelay=209, Bit 15, Center 92 (-15 ~ 200) 216
1423 11:17:34.714077 ==
1424 11:17:34.717521 Dram Type= 6, Freq= 0, CH_0, rank 1
1425 11:17:34.720799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1426 11:17:34.720875 ==
1427 11:17:34.720951 DQS Delay:
1428 11:17:34.724380 DQS0 = 0, DQS1 = 0
1429 11:17:34.724468 DQM Delay:
1430 11:17:34.727300 DQM0 = 93, DQM1 = 84
1431 11:17:34.727420 DQ Delay:
1432 11:17:34.730766 DQ0 =92, DQ1 =96, DQ2 =88, DQ3 =92
1433 11:17:34.734220 DQ4 =96, DQ5 =84, DQ6 =96, DQ7 =100
1434 11:17:34.737494 DQ8 =76, DQ9 =72, DQ10 =84, DQ11 =76
1435 11:17:34.741078 DQ12 =88, DQ13 =92, DQ14 =92, DQ15 =92
1436 11:17:34.741177
1437 11:17:34.741264
1438 11:17:34.747465 [DQSOSCAuto] RK1, (LSB)MR18= 0x4011, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 393 ps
1439 11:17:34.751406 CH0 RK1: MR19=606, MR18=4011
1440 11:17:34.758057 CH0_RK1: MR19=0x606, MR18=0x4011, DQSOSC=393, MR23=63, INC=95, DEC=63
1441 11:17:34.761293 [RxdqsGatingPostProcess] freq 800
1442 11:17:34.764423 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1443 11:17:34.767459 Pre-setting of DQS Precalculation
1444 11:17:34.774229 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1445 11:17:34.774354 ==
1446 11:17:34.778050 Dram Type= 6, Freq= 0, CH_1, rank 0
1447 11:17:34.780966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1448 11:17:34.781048 ==
1449 11:17:34.787785 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1450 11:17:34.794730 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1451 11:17:34.801981 [CA 0] Center 36 (6~67) winsize 62
1452 11:17:34.805485 [CA 1] Center 36 (6~67) winsize 62
1453 11:17:34.808994 [CA 2] Center 35 (5~66) winsize 62
1454 11:17:34.812434 [CA 3] Center 34 (4~65) winsize 62
1455 11:17:34.815462 [CA 4] Center 34 (4~65) winsize 62
1456 11:17:34.818437 [CA 5] Center 34 (4~64) winsize 61
1457 11:17:34.818529
1458 11:17:34.822204 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1459 11:17:34.822320
1460 11:17:34.825324 [CATrainingPosCal] consider 1 rank data
1461 11:17:34.828851 u2DelayCellTimex100 = 270/100 ps
1462 11:17:34.832251 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1463 11:17:34.835363 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1464 11:17:34.842199 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1465 11:17:34.845175 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1466 11:17:34.848595 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1467 11:17:34.851909 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1468 11:17:34.852035
1469 11:17:34.855542 CA PerBit enable=1, Macro0, CA PI delay=34
1470 11:17:34.855633
1471 11:17:34.858601 [CBTSetCACLKResult] CA Dly = 34
1472 11:17:34.858680 CS Dly: 6 (0~37)
1473 11:17:34.858741 ==
1474 11:17:34.862305 Dram Type= 6, Freq= 0, CH_1, rank 1
1475 11:17:34.869197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1476 11:17:34.869306 ==
1477 11:17:34.872196 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1478 11:17:34.878758 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1479 11:17:34.888755 [CA 0] Center 36 (6~67) winsize 62
1480 11:17:34.892539 [CA 1] Center 36 (6~67) winsize 62
1481 11:17:34.896164 [CA 2] Center 35 (5~66) winsize 62
1482 11:17:34.899989 [CA 3] Center 34 (4~65) winsize 62
1483 11:17:34.903450 [CA 4] Center 34 (4~65) winsize 62
1484 11:17:34.906718 [CA 5] Center 34 (4~65) winsize 62
1485 11:17:34.906800
1486 11:17:34.910694 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1487 11:17:34.910773
1488 11:17:34.914096 [CATrainingPosCal] consider 2 rank data
1489 11:17:34.914206 u2DelayCellTimex100 = 270/100 ps
1490 11:17:34.917907 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1491 11:17:34.924393 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1492 11:17:34.928114 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
1493 11:17:34.931203 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
1494 11:17:34.934821 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1495 11:17:34.938218 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1496 11:17:34.938329
1497 11:17:34.941055 CA PerBit enable=1, Macro0, CA PI delay=34
1498 11:17:34.941132
1499 11:17:34.944680 [CBTSetCACLKResult] CA Dly = 34
1500 11:17:34.944791 CS Dly: 7 (0~39)
1501 11:17:34.944881
1502 11:17:34.948186 ----->DramcWriteLeveling(PI) begin...
1503 11:17:34.951548 ==
1504 11:17:34.954696 Dram Type= 6, Freq= 0, CH_1, rank 0
1505 11:17:34.957867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1506 11:17:34.957958 ==
1507 11:17:34.961217 Write leveling (Byte 0): 27 => 27
1508 11:17:34.964881 Write leveling (Byte 1): 27 => 27
1509 11:17:34.968070 DramcWriteLeveling(PI) end<-----
1510 11:17:34.968145
1511 11:17:34.968226 ==
1512 11:17:34.971090 Dram Type= 6, Freq= 0, CH_1, rank 0
1513 11:17:34.974882 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1514 11:17:34.974973 ==
1515 11:17:34.977986 [Gating] SW mode calibration
1516 11:17:34.984592 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1517 11:17:34.988370 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1518 11:17:34.994873 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1519 11:17:34.998059 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1520 11:17:35.001716 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1521 11:17:35.008193 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1522 11:17:35.011494 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1523 11:17:35.015026 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1524 11:17:35.021538 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1525 11:17:35.024822 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1526 11:17:35.028384 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1527 11:17:35.035073 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1528 11:17:35.038362 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1529 11:17:35.041363 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1530 11:17:35.048377 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1531 11:17:35.051740 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1532 11:17:35.054886 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1533 11:17:35.058335 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1534 11:17:35.064980 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1535 11:17:35.068508 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1536 11:17:35.071657 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1537 11:17:35.078432 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1538 11:17:35.082134 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1539 11:17:35.085157 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1540 11:17:35.091509 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1541 11:17:35.095138 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1542 11:17:35.098735 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1543 11:17:35.105078 0 9 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
1544 11:17:35.108701 0 9 8 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1545 11:17:35.111751 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1546 11:17:35.118328 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1547 11:17:35.121893 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1548 11:17:35.125507 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1549 11:17:35.128391 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1550 11:17:35.135240 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1551 11:17:35.138758 0 10 4 | B1->B0 | 3333 2d2d | 0 0 | (0 0) (0 0)
1552 11:17:35.142201 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1553 11:17:35.148754 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 11:17:35.151965 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 11:17:35.155126 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 11:17:35.162081 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 11:17:35.165683 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 11:17:35.168623 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 11:17:35.175205 0 11 4 | B1->B0 | 2a2a 3333 | 0 0 | (1 1) (1 1)
1560 11:17:35.178856 0 11 8 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
1561 11:17:35.181962 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1562 11:17:35.188591 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1563 11:17:35.192046 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1564 11:17:35.195731 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1565 11:17:35.199462 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1566 11:17:35.205551 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1567 11:17:35.209415 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
1568 11:17:35.212385 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1569 11:17:35.219489 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1570 11:17:35.222561 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1571 11:17:35.225645 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1572 11:17:35.232237 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1573 11:17:35.235521 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1574 11:17:35.239117 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1575 11:17:35.245558 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1576 11:17:35.249080 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1577 11:17:35.252157 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1578 11:17:35.258838 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1579 11:17:35.262665 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1580 11:17:35.265589 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1581 11:17:35.272443 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1582 11:17:35.275940 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
1583 11:17:35.278797 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1584 11:17:35.282217 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1585 11:17:35.285650 Total UI for P1: 0, mck2ui 16
1586 11:17:35.289685 best dqsien dly found for B1: ( 0, 14, 2)
1587 11:17:35.295764 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1588 11:17:35.295892 Total UI for P1: 0, mck2ui 16
1589 11:17:35.302293 best dqsien dly found for B0: ( 0, 14, 6)
1590 11:17:35.305897 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1591 11:17:35.309099 best DQS1 dly(MCK, UI, PI) = (0, 14, 2)
1592 11:17:35.309186
1593 11:17:35.312337 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1594 11:17:35.316080 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 2)
1595 11:17:35.319153 [Gating] SW calibration Done
1596 11:17:35.319236 ==
1597 11:17:35.322865 Dram Type= 6, Freq= 0, CH_1, rank 0
1598 11:17:35.326057 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1599 11:17:35.326134 ==
1600 11:17:35.328961 RX Vref Scan: 0
1601 11:17:35.329062
1602 11:17:35.329132 RX Vref 0 -> 0, step: 1
1603 11:17:35.329194
1604 11:17:35.332761 RX Delay -130 -> 252, step: 16
1605 11:17:35.335684 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1606 11:17:35.342785 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1607 11:17:35.345760 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1608 11:17:35.349616 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
1609 11:17:35.352583 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
1610 11:17:35.355861 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1611 11:17:35.362425 iDelay=222, Bit 6, Center 109 (-2 ~ 221) 224
1612 11:17:35.365653 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1613 11:17:35.369377 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1614 11:17:35.372361 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1615 11:17:35.375957 iDelay=222, Bit 10, Center 85 (-18 ~ 189) 208
1616 11:17:35.382624 iDelay=222, Bit 11, Center 85 (-18 ~ 189) 208
1617 11:17:35.385753 iDelay=222, Bit 12, Center 101 (-2 ~ 205) 208
1618 11:17:35.388975 iDelay=222, Bit 13, Center 101 (-2 ~ 205) 208
1619 11:17:35.392538 iDelay=222, Bit 14, Center 101 (-2 ~ 205) 208
1620 11:17:35.395966 iDelay=222, Bit 15, Center 101 (-2 ~ 205) 208
1621 11:17:35.399079 ==
1622 11:17:35.399160 Dram Type= 6, Freq= 0, CH_1, rank 0
1623 11:17:35.405737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1624 11:17:35.405821 ==
1625 11:17:35.405885 DQS Delay:
1626 11:17:35.409347 DQS0 = 0, DQS1 = 0
1627 11:17:35.409425 DQM Delay:
1628 11:17:35.412381 DQM0 = 95, DQM1 = 91
1629 11:17:35.412458 DQ Delay:
1630 11:17:35.416218 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =93
1631 11:17:35.419457 DQ4 =93, DQ5 =109, DQ6 =109, DQ7 =93
1632 11:17:35.422318 DQ8 =77, DQ9 =77, DQ10 =85, DQ11 =85
1633 11:17:35.426279 DQ12 =101, DQ13 =101, DQ14 =101, DQ15 =101
1634 11:17:35.426357
1635 11:17:35.426419
1636 11:17:35.426476 ==
1637 11:17:35.429274 Dram Type= 6, Freq= 0, CH_1, rank 0
1638 11:17:35.432522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1639 11:17:35.432614 ==
1640 11:17:35.432684
1641 11:17:35.432745
1642 11:17:35.435976 TX Vref Scan disable
1643 11:17:35.439064 == TX Byte 0 ==
1644 11:17:35.442663 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1645 11:17:35.445687 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1646 11:17:35.449280 == TX Byte 1 ==
1647 11:17:35.452688 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1648 11:17:35.455889 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1649 11:17:35.455968 ==
1650 11:17:35.459198 Dram Type= 6, Freq= 0, CH_1, rank 0
1651 11:17:35.462758 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1652 11:17:35.466238 ==
1653 11:17:35.477485 TX Vref=22, minBit 0, minWin=26, winSum=432
1654 11:17:35.480678 TX Vref=24, minBit 3, minWin=26, winSum=440
1655 11:17:35.484433 TX Vref=26, minBit 2, minWin=27, winSum=445
1656 11:17:35.487272 TX Vref=28, minBit 1, minWin=27, winSum=447
1657 11:17:35.490676 TX Vref=30, minBit 1, minWin=27, winSum=446
1658 11:17:35.494342 TX Vref=32, minBit 2, minWin=26, winSum=445
1659 11:17:35.500688 [TxChooseVref] Worse bit 1, Min win 27, Win sum 447, Final Vref 28
1660 11:17:35.500776
1661 11:17:35.504290 Final TX Range 1 Vref 28
1662 11:17:35.504386
1663 11:17:35.504452 ==
1664 11:17:35.507224 Dram Type= 6, Freq= 0, CH_1, rank 0
1665 11:17:35.510833 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1666 11:17:35.510915 ==
1667 11:17:35.510982
1668 11:17:35.513990
1669 11:17:35.514098 TX Vref Scan disable
1670 11:17:35.517264 == TX Byte 0 ==
1671 11:17:35.520735 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1672 11:17:35.524015 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1673 11:17:35.527117 == TX Byte 1 ==
1674 11:17:35.530936 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1675 11:17:35.534068 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1676 11:17:35.537264
1677 11:17:35.537362 [DATLAT]
1678 11:17:35.537430 Freq=800, CH1 RK0
1679 11:17:35.537492
1680 11:17:35.540404 DATLAT Default: 0xa
1681 11:17:35.540479 0, 0xFFFF, sum = 0
1682 11:17:35.544235 1, 0xFFFF, sum = 0
1683 11:17:35.544321 2, 0xFFFF, sum = 0
1684 11:17:35.547317 3, 0xFFFF, sum = 0
1685 11:17:35.547467 4, 0xFFFF, sum = 0
1686 11:17:35.550300 5, 0xFFFF, sum = 0
1687 11:17:35.550409 6, 0xFFFF, sum = 0
1688 11:17:35.554147 7, 0xFFFF, sum = 0
1689 11:17:35.554262 8, 0x0, sum = 1
1690 11:17:35.557129 9, 0x0, sum = 2
1691 11:17:35.557222 10, 0x0, sum = 3
1692 11:17:35.560566 11, 0x0, sum = 4
1693 11:17:35.560648 best_step = 9
1694 11:17:35.560732
1695 11:17:35.560801 ==
1696 11:17:35.563822 Dram Type= 6, Freq= 0, CH_1, rank 0
1697 11:17:35.570493 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1698 11:17:35.570611 ==
1699 11:17:35.570716 RX Vref Scan: 1
1700 11:17:35.570808
1701 11:17:35.574165 Set Vref Range= 32 -> 127
1702 11:17:35.574252
1703 11:17:35.577355 RX Vref 32 -> 127, step: 1
1704 11:17:35.577439
1705 11:17:35.577503 RX Delay -79 -> 252, step: 8
1706 11:17:35.577563
1707 11:17:35.580441 Set Vref, RX VrefLevel [Byte0]: 32
1708 11:17:35.584188 [Byte1]: 32
1709 11:17:35.588231
1710 11:17:35.588312 Set Vref, RX VrefLevel [Byte0]: 33
1711 11:17:35.591116 [Byte1]: 33
1712 11:17:35.595892
1713 11:17:35.596016 Set Vref, RX VrefLevel [Byte0]: 34
1714 11:17:35.599195 [Byte1]: 34
1715 11:17:35.603393
1716 11:17:35.603502 Set Vref, RX VrefLevel [Byte0]: 35
1717 11:17:35.606089 [Byte1]: 35
1718 11:17:35.610577
1719 11:17:35.610653 Set Vref, RX VrefLevel [Byte0]: 36
1720 11:17:35.614162 [Byte1]: 36
1721 11:17:35.618080
1722 11:17:35.618155 Set Vref, RX VrefLevel [Byte0]: 37
1723 11:17:35.621321 [Byte1]: 37
1724 11:17:35.625742
1725 11:17:35.625816 Set Vref, RX VrefLevel [Byte0]: 38
1726 11:17:35.629248 [Byte1]: 38
1727 11:17:35.633031
1728 11:17:35.633128 Set Vref, RX VrefLevel [Byte0]: 39
1729 11:17:35.636842 [Byte1]: 39
1730 11:17:35.640588
1731 11:17:35.640660 Set Vref, RX VrefLevel [Byte0]: 40
1732 11:17:35.644308 [Byte1]: 40
1733 11:17:35.647983
1734 11:17:35.648059 Set Vref, RX VrefLevel [Byte0]: 41
1735 11:17:35.651729 [Byte1]: 41
1736 11:17:35.656124
1737 11:17:35.656199 Set Vref, RX VrefLevel [Byte0]: 42
1738 11:17:35.658828 [Byte1]: 42
1739 11:17:35.663128
1740 11:17:35.663202 Set Vref, RX VrefLevel [Byte0]: 43
1741 11:17:35.666475 [Byte1]: 43
1742 11:17:35.670970
1743 11:17:35.671050 Set Vref, RX VrefLevel [Byte0]: 44
1744 11:17:35.673983 [Byte1]: 44
1745 11:17:35.678638
1746 11:17:35.678747 Set Vref, RX VrefLevel [Byte0]: 45
1747 11:17:35.681985 [Byte1]: 45
1748 11:17:35.686117
1749 11:17:35.686222 Set Vref, RX VrefLevel [Byte0]: 46
1750 11:17:35.689261 [Byte1]: 46
1751 11:17:35.693585
1752 11:17:35.693688 Set Vref, RX VrefLevel [Byte0]: 47
1753 11:17:35.696560 [Byte1]: 47
1754 11:17:35.701484
1755 11:17:35.701592 Set Vref, RX VrefLevel [Byte0]: 48
1756 11:17:35.704264 [Byte1]: 48
1757 11:17:35.708619
1758 11:17:35.708783 Set Vref, RX VrefLevel [Byte0]: 49
1759 11:17:35.711965 [Byte1]: 49
1760 11:17:35.716131
1761 11:17:35.716216 Set Vref, RX VrefLevel [Byte0]: 50
1762 11:17:35.719625 [Byte1]: 50
1763 11:17:35.723668
1764 11:17:35.723768 Set Vref, RX VrefLevel [Byte0]: 51
1765 11:17:35.727224 [Byte1]: 51
1766 11:17:35.731084
1767 11:17:35.731184 Set Vref, RX VrefLevel [Byte0]: 52
1768 11:17:35.734316 [Byte1]: 52
1769 11:17:35.738713
1770 11:17:35.738822 Set Vref, RX VrefLevel [Byte0]: 53
1771 11:17:35.742431 [Byte1]: 53
1772 11:17:35.746095
1773 11:17:35.746201 Set Vref, RX VrefLevel [Byte0]: 54
1774 11:17:35.749964 [Byte1]: 54
1775 11:17:35.754343
1776 11:17:35.754426 Set Vref, RX VrefLevel [Byte0]: 55
1777 11:17:35.756972 [Byte1]: 55
1778 11:17:35.761209
1779 11:17:35.761322 Set Vref, RX VrefLevel [Byte0]: 56
1780 11:17:35.764896 [Byte1]: 56
1781 11:17:35.769070
1782 11:17:35.769189 Set Vref, RX VrefLevel [Byte0]: 57
1783 11:17:35.772432 [Byte1]: 57
1784 11:17:35.776925
1785 11:17:35.777076 Set Vref, RX VrefLevel [Byte0]: 58
1786 11:17:35.779667 [Byte1]: 58
1787 11:17:35.784339
1788 11:17:35.784445 Set Vref, RX VrefLevel [Byte0]: 59
1789 11:17:35.787538 [Byte1]: 59
1790 11:17:35.791833
1791 11:17:35.791951 Set Vref, RX VrefLevel [Byte0]: 60
1792 11:17:35.795264 [Byte1]: 60
1793 11:17:35.799521
1794 11:17:35.799651 Set Vref, RX VrefLevel [Byte0]: 61
1795 11:17:35.802552 [Byte1]: 61
1796 11:17:35.807077
1797 11:17:35.807160 Set Vref, RX VrefLevel [Byte0]: 62
1798 11:17:35.810335 [Byte1]: 62
1799 11:17:35.814447
1800 11:17:35.814529 Set Vref, RX VrefLevel [Byte0]: 63
1801 11:17:35.817414 [Byte1]: 63
1802 11:17:35.821589
1803 11:17:35.821670 Set Vref, RX VrefLevel [Byte0]: 64
1804 11:17:35.825058 [Byte1]: 64
1805 11:17:35.829203
1806 11:17:35.829367 Set Vref, RX VrefLevel [Byte0]: 65
1807 11:17:35.832805 [Byte1]: 65
1808 11:17:35.836903
1809 11:17:35.836985 Set Vref, RX VrefLevel [Byte0]: 66
1810 11:17:35.840289 [Byte1]: 66
1811 11:17:35.844383
1812 11:17:35.844465 Set Vref, RX VrefLevel [Byte0]: 67
1813 11:17:35.848423 [Byte1]: 67
1814 11:17:35.851835
1815 11:17:35.851911 Set Vref, RX VrefLevel [Byte0]: 68
1816 11:17:35.855897 [Byte1]: 68
1817 11:17:35.859316
1818 11:17:35.859414 Set Vref, RX VrefLevel [Byte0]: 69
1819 11:17:35.862946 [Byte1]: 69
1820 11:17:35.867213
1821 11:17:35.867302 Set Vref, RX VrefLevel [Byte0]: 70
1822 11:17:35.870163 [Byte1]: 70
1823 11:17:35.874998
1824 11:17:35.875079 Set Vref, RX VrefLevel [Byte0]: 71
1825 11:17:35.877903 [Byte1]: 71
1826 11:17:35.882104
1827 11:17:35.882222 Final RX Vref Byte 0 = 56 to rank0
1828 11:17:35.885608 Final RX Vref Byte 1 = 55 to rank0
1829 11:17:35.889327 Final RX Vref Byte 0 = 56 to rank1
1830 11:17:35.892269 Final RX Vref Byte 1 = 55 to rank1==
1831 11:17:35.895510 Dram Type= 6, Freq= 0, CH_1, rank 0
1832 11:17:35.899242 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1833 11:17:35.902269 ==
1834 11:17:35.902366 DQS Delay:
1835 11:17:35.902459 DQS0 = 0, DQS1 = 0
1836 11:17:35.906070 DQM Delay:
1837 11:17:35.906151 DQM0 = 95, DQM1 = 90
1838 11:17:35.909090 DQ Delay:
1839 11:17:35.909172 DQ0 =96, DQ1 =88, DQ2 =84, DQ3 =92
1840 11:17:35.912259 DQ4 =96, DQ5 =108, DQ6 =104, DQ7 =92
1841 11:17:35.915617 DQ8 =80, DQ9 =80, DQ10 =88, DQ11 =84
1842 11:17:35.922519 DQ12 =96, DQ13 =96, DQ14 =96, DQ15 =100
1843 11:17:35.922646
1844 11:17:35.922740
1845 11:17:35.928858 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f4c, (MSB)MR19= 0x606, tDQSOscB0 = 390 ps tDQSOscB1 = 397 ps
1846 11:17:35.932615 CH1 RK0: MR19=606, MR18=2F4C
1847 11:17:35.939043 CH1_RK0: MR19=0x606, MR18=0x2F4C, DQSOSC=390, MR23=63, INC=97, DEC=64
1848 11:17:35.939157
1849 11:17:35.942674 ----->DramcWriteLeveling(PI) begin...
1850 11:17:35.942789 ==
1851 11:17:35.946005 Dram Type= 6, Freq= 0, CH_1, rank 1
1852 11:17:35.949088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1853 11:17:35.949172 ==
1854 11:17:35.952472 Write leveling (Byte 0): 26 => 26
1855 11:17:35.955308 Write leveling (Byte 1): 30 => 30
1856 11:17:35.959035 DramcWriteLeveling(PI) end<-----
1857 11:17:35.959116
1858 11:17:35.959184 ==
1859 11:17:35.962290 Dram Type= 6, Freq= 0, CH_1, rank 1
1860 11:17:35.965770 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1861 11:17:35.965882 ==
1862 11:17:35.969330 [Gating] SW mode calibration
1863 11:17:35.975518 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1864 11:17:35.982669 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1865 11:17:35.985834 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1866 11:17:35.989103 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1867 11:17:35.995966 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1868 11:17:35.999051 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1869 11:17:36.002743 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1870 11:17:36.009053 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1871 11:17:36.012751 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1872 11:17:36.015677 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 11:17:36.022614 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 11:17:36.025672 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 11:17:36.029701 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 11:17:36.032490 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 11:17:36.039016 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 11:17:36.042543 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1879 11:17:36.046352 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1880 11:17:36.052636 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1881 11:17:36.055759 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1882 11:17:36.059382 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1883 11:17:36.066226 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1884 11:17:36.069485 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1885 11:17:36.072310 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1886 11:17:36.079375 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1887 11:17:36.082831 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1888 11:17:36.086222 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1889 11:17:36.092917 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1890 11:17:36.096416 0 9 4 | B1->B0 | 2929 2323 | 1 1 | (1 1) (1 1)
1891 11:17:36.099134 0 9 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 1)
1892 11:17:36.106055 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1893 11:17:36.109305 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1894 11:17:36.113000 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1895 11:17:36.116104 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1896 11:17:36.123107 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1897 11:17:36.125983 0 10 0 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 1)
1898 11:17:36.129499 0 10 4 | B1->B0 | 2828 3232 | 0 0 | (0 0) (0 1)
1899 11:17:36.136488 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1900 11:17:36.140108 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1901 11:17:36.142827 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1902 11:17:36.149966 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1903 11:17:36.152989 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1904 11:17:36.156261 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1905 11:17:36.163070 0 11 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
1906 11:17:36.166090 0 11 4 | B1->B0 | 3737 2c2c | 0 0 | (0 0) (0 0)
1907 11:17:36.169867 0 11 8 | B1->B0 | 4646 4545 | 0 0 | (0 0) (0 0)
1908 11:17:36.176533 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1909 11:17:36.179614 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1910 11:17:36.182799 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1911 11:17:36.186570 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1912 11:17:36.193559 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1913 11:17:36.196731 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1914 11:17:36.199934 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
1915 11:17:36.206486 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1916 11:17:36.209981 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1917 11:17:36.213119 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1918 11:17:36.219706 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1919 11:17:36.223318 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1920 11:17:36.226858 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1921 11:17:36.233287 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1922 11:17:36.236122 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1923 11:17:36.239546 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1924 11:17:36.246107 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1925 11:17:36.249791 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1926 11:17:36.253132 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1927 11:17:36.260300 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1928 11:17:36.263357 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1929 11:17:36.266610 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1930 11:17:36.270461 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1931 11:17:36.276659 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1932 11:17:36.279686 Total UI for P1: 0, mck2ui 16
1933 11:17:36.283218 best dqsien dly found for B0: ( 0, 14, 4)
1934 11:17:36.283303 Total UI for P1: 0, mck2ui 16
1935 11:17:36.289817 best dqsien dly found for B1: ( 0, 14, 4)
1936 11:17:36.293715 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1937 11:17:36.296811 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1938 11:17:36.296895
1939 11:17:36.300343 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1940 11:17:36.303282 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1941 11:17:36.306971 [Gating] SW calibration Done
1942 11:17:36.307055 ==
1943 11:17:36.309815 Dram Type= 6, Freq= 0, CH_1, rank 1
1944 11:17:36.313207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1945 11:17:36.313289 ==
1946 11:17:36.316568 RX Vref Scan: 0
1947 11:17:36.316656
1948 11:17:36.316742 RX Vref 0 -> 0, step: 1
1949 11:17:36.316832
1950 11:17:36.320262 RX Delay -130 -> 252, step: 16
1951 11:17:36.323523 iDelay=222, Bit 0, Center 101 (-2 ~ 205) 208
1952 11:17:36.329832 iDelay=222, Bit 1, Center 85 (-18 ~ 189) 208
1953 11:17:36.333446 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1954 11:17:36.336621 iDelay=222, Bit 3, Center 85 (-18 ~ 189) 208
1955 11:17:36.340021 iDelay=222, Bit 4, Center 85 (-18 ~ 189) 208
1956 11:17:36.343674 iDelay=222, Bit 5, Center 109 (-2 ~ 221) 224
1957 11:17:36.349804 iDelay=222, Bit 6, Center 101 (-2 ~ 205) 208
1958 11:17:36.353406 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
1959 11:17:36.356752 iDelay=222, Bit 8, Center 77 (-34 ~ 189) 224
1960 11:17:36.360142 iDelay=222, Bit 9, Center 77 (-34 ~ 189) 224
1961 11:17:36.363092 iDelay=222, Bit 10, Center 93 (-18 ~ 205) 224
1962 11:17:36.370112 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1963 11:17:36.373320 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1964 11:17:36.376592 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1965 11:17:36.380215 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1966 11:17:36.383542 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1967 11:17:36.383641 ==
1968 11:17:36.386717 Dram Type= 6, Freq= 0, CH_1, rank 1
1969 11:17:36.393260 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1970 11:17:36.393374 ==
1971 11:17:36.393489 DQS Delay:
1972 11:17:36.397222 DQS0 = 0, DQS1 = 0
1973 11:17:36.397301 DQM Delay:
1974 11:17:36.400085 DQM0 = 92, DQM1 = 87
1975 11:17:36.400168 DQ Delay:
1976 11:17:36.403227 DQ0 =101, DQ1 =85, DQ2 =77, DQ3 =85
1977 11:17:36.406354 DQ4 =85, DQ5 =109, DQ6 =101, DQ7 =93
1978 11:17:36.410132 DQ8 =77, DQ9 =77, DQ10 =93, DQ11 =77
1979 11:17:36.413662 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1980 11:17:36.413761
1981 11:17:36.413842
1982 11:17:36.413930 ==
1983 11:17:36.416657 Dram Type= 6, Freq= 0, CH_1, rank 1
1984 11:17:36.420086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1985 11:17:36.420184 ==
1986 11:17:36.420273
1987 11:17:36.420360
1988 11:17:36.423171 TX Vref Scan disable
1989 11:17:36.426878 == TX Byte 0 ==
1990 11:17:36.430398 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1991 11:17:36.433479 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1992 11:17:36.436497 == TX Byte 1 ==
1993 11:17:36.439896 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1994 11:17:36.443517 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1995 11:17:36.443629 ==
1996 11:17:36.446571 Dram Type= 6, Freq= 0, CH_1, rank 1
1997 11:17:36.450129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1998 11:17:36.450218 ==
1999 11:17:36.464997 TX Vref=22, minBit 1, minWin=26, winSum=438
2000 11:17:36.468429 TX Vref=24, minBit 0, minWin=27, winSum=444
2001 11:17:36.471771 TX Vref=26, minBit 1, minWin=27, winSum=446
2002 11:17:36.474560 TX Vref=28, minBit 2, minWin=27, winSum=451
2003 11:17:36.478462 TX Vref=30, minBit 0, minWin=27, winSum=450
2004 11:17:36.481675 TX Vref=32, minBit 0, minWin=27, winSum=448
2005 11:17:36.488438 [TxChooseVref] Worse bit 2, Min win 27, Win sum 451, Final Vref 28
2006 11:17:36.488531
2007 11:17:36.491473 Final TX Range 1 Vref 28
2008 11:17:36.491553
2009 11:17:36.491657 ==
2010 11:17:36.495226 Dram Type= 6, Freq= 0, CH_1, rank 1
2011 11:17:36.498244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2012 11:17:36.498333 ==
2013 11:17:36.498420
2014 11:17:36.498506
2015 11:17:36.502029 TX Vref Scan disable
2016 11:17:36.505133 == TX Byte 0 ==
2017 11:17:36.508188 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
2018 11:17:36.512037 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
2019 11:17:36.515105 == TX Byte 1 ==
2020 11:17:36.518382 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2021 11:17:36.521493 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2022 11:17:36.521572
2023 11:17:36.525224 [DATLAT]
2024 11:17:36.525307 Freq=800, CH1 RK1
2025 11:17:36.525372
2026 11:17:36.528419 DATLAT Default: 0x9
2027 11:17:36.528504 0, 0xFFFF, sum = 0
2028 11:17:36.531789 1, 0xFFFF, sum = 0
2029 11:17:36.531905 2, 0xFFFF, sum = 0
2030 11:17:36.535304 3, 0xFFFF, sum = 0
2031 11:17:36.535426 4, 0xFFFF, sum = 0
2032 11:17:36.538387 5, 0xFFFF, sum = 0
2033 11:17:36.538471 6, 0xFFFF, sum = 0
2034 11:17:36.542283 7, 0xFFFF, sum = 0
2035 11:17:36.542367 8, 0xFFFF, sum = 0
2036 11:17:36.545355 9, 0x0, sum = 1
2037 11:17:36.545456 10, 0x0, sum = 2
2038 11:17:36.548354 11, 0x0, sum = 3
2039 11:17:36.548455 12, 0x0, sum = 4
2040 11:17:36.552009 best_step = 10
2041 11:17:36.552109
2042 11:17:36.552227 ==
2043 11:17:36.555048 Dram Type= 6, Freq= 0, CH_1, rank 1
2044 11:17:36.558647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2045 11:17:36.558730 ==
2046 11:17:36.558795 RX Vref Scan: 0
2047 11:17:36.562202
2048 11:17:36.562286 RX Vref 0 -> 0, step: 1
2049 11:17:36.562369
2050 11:17:36.565112 RX Delay -79 -> 252, step: 8
2051 11:17:36.568692 iDelay=209, Bit 0, Center 104 (9 ~ 200) 192
2052 11:17:36.575105 iDelay=209, Bit 1, Center 92 (-7 ~ 192) 200
2053 11:17:36.578455 iDelay=209, Bit 2, Center 84 (-15 ~ 184) 200
2054 11:17:36.582147 iDelay=209, Bit 3, Center 92 (-7 ~ 192) 200
2055 11:17:36.585431 iDelay=209, Bit 4, Center 92 (-7 ~ 192) 200
2056 11:17:36.588785 iDelay=209, Bit 5, Center 112 (17 ~ 208) 192
2057 11:17:36.592083 iDelay=209, Bit 6, Center 108 (9 ~ 208) 200
2058 11:17:36.599011 iDelay=209, Bit 7, Center 96 (-7 ~ 200) 208
2059 11:17:36.601999 iDelay=209, Bit 8, Center 80 (-23 ~ 184) 208
2060 11:17:36.605094 iDelay=209, Bit 9, Center 80 (-23 ~ 184) 208
2061 11:17:36.608553 iDelay=209, Bit 10, Center 92 (-15 ~ 200) 216
2062 11:17:36.612187 iDelay=209, Bit 11, Center 84 (-23 ~ 192) 216
2063 11:17:36.619036 iDelay=209, Bit 12, Center 100 (-7 ~ 208) 216
2064 11:17:36.622090 iDelay=209, Bit 13, Center 96 (-7 ~ 200) 208
2065 11:17:36.625081 iDelay=209, Bit 14, Center 96 (-7 ~ 200) 208
2066 11:17:36.628712 iDelay=209, Bit 15, Center 96 (-7 ~ 200) 208
2067 11:17:36.628791 ==
2068 11:17:36.631799 Dram Type= 6, Freq= 0, CH_1, rank 1
2069 11:17:36.638856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2070 11:17:36.638935 ==
2071 11:17:36.638999 DQS Delay:
2072 11:17:36.639059 DQS0 = 0, DQS1 = 0
2073 11:17:36.642261 DQM Delay:
2074 11:17:36.642343 DQM0 = 97, DQM1 = 90
2075 11:17:36.645189 DQ Delay:
2076 11:17:36.648825 DQ0 =104, DQ1 =92, DQ2 =84, DQ3 =92
2077 11:17:36.652178 DQ4 =92, DQ5 =112, DQ6 =108, DQ7 =96
2078 11:17:36.655789 DQ8 =80, DQ9 =80, DQ10 =92, DQ11 =84
2079 11:17:36.658790 DQ12 =100, DQ13 =96, DQ14 =96, DQ15 =96
2080 11:17:36.658885
2081 11:17:36.658972
2082 11:17:36.665635 [DQSOSCAuto] RK1, (LSB)MR18= 0x440d, (MSB)MR19= 0x606, tDQSOscB0 = 406 ps tDQSOscB1 = 392 ps
2083 11:17:36.669034 CH1 RK1: MR19=606, MR18=440D
2084 11:17:36.675288 CH1_RK1: MR19=0x606, MR18=0x440D, DQSOSC=392, MR23=63, INC=96, DEC=64
2085 11:17:36.678902 [RxdqsGatingPostProcess] freq 800
2086 11:17:36.682370 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2087 11:17:36.686096 Pre-setting of DQS Precalculation
2088 11:17:36.692104 [DualRankRxdatlatCal] RK0: 9, RK1: 10, Final_Datlat 10
2089 11:17:36.699102 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2090 11:17:36.705352 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2091 11:17:36.705436
2092 11:17:36.705501
2093 11:17:36.709203 [Calibration Summary] 1600 Mbps
2094 11:17:36.709286 CH 0, Rank 0
2095 11:17:36.712032 SW Impedance : PASS
2096 11:17:36.715446 DUTY Scan : NO K
2097 11:17:36.715523 ZQ Calibration : PASS
2098 11:17:36.719128 Jitter Meter : NO K
2099 11:17:36.719235 CBT Training : PASS
2100 11:17:36.722387 Write leveling : PASS
2101 11:17:36.725585 RX DQS gating : PASS
2102 11:17:36.725657 RX DQ/DQS(RDDQC) : PASS
2103 11:17:36.729155 TX DQ/DQS : PASS
2104 11:17:36.732476 RX DATLAT : PASS
2105 11:17:36.732549 RX DQ/DQS(Engine): PASS
2106 11:17:36.735533 TX OE : NO K
2107 11:17:36.735616 All Pass.
2108 11:17:36.735678
2109 11:17:36.739090 CH 0, Rank 1
2110 11:17:36.739158 SW Impedance : PASS
2111 11:17:36.742235 DUTY Scan : NO K
2112 11:17:36.745777 ZQ Calibration : PASS
2113 11:17:36.745855 Jitter Meter : NO K
2114 11:17:36.749111 CBT Training : PASS
2115 11:17:36.752187 Write leveling : PASS
2116 11:17:36.752262 RX DQS gating : PASS
2117 11:17:36.755478 RX DQ/DQS(RDDQC) : PASS
2118 11:17:36.755561 TX DQ/DQS : PASS
2119 11:17:36.759193 RX DATLAT : PASS
2120 11:17:36.762310 RX DQ/DQS(Engine): PASS
2121 11:17:36.762398 TX OE : NO K
2122 11:17:36.765519 All Pass.
2123 11:17:36.765603
2124 11:17:36.765668 CH 1, Rank 0
2125 11:17:36.769127 SW Impedance : PASS
2126 11:17:36.769211 DUTY Scan : NO K
2127 11:17:36.772653 ZQ Calibration : PASS
2128 11:17:36.776029 Jitter Meter : NO K
2129 11:17:36.776112 CBT Training : PASS
2130 11:17:36.778988 Write leveling : PASS
2131 11:17:36.782621 RX DQS gating : PASS
2132 11:17:36.782704 RX DQ/DQS(RDDQC) : PASS
2133 11:17:36.785840 TX DQ/DQS : PASS
2134 11:17:36.789358 RX DATLAT : PASS
2135 11:17:36.789464 RX DQ/DQS(Engine): PASS
2136 11:17:36.792366 TX OE : NO K
2137 11:17:36.792450 All Pass.
2138 11:17:36.792516
2139 11:17:36.796031 CH 1, Rank 1
2140 11:17:36.796114 SW Impedance : PASS
2141 11:17:36.799021 DUTY Scan : NO K
2142 11:17:36.799114 ZQ Calibration : PASS
2143 11:17:36.802189 Jitter Meter : NO K
2144 11:17:36.805975 CBT Training : PASS
2145 11:17:36.806059 Write leveling : PASS
2146 11:17:36.809055 RX DQS gating : PASS
2147 11:17:36.812851 RX DQ/DQS(RDDQC) : PASS
2148 11:17:36.812935 TX DQ/DQS : PASS
2149 11:17:36.815970 RX DATLAT : PASS
2150 11:17:36.818982 RX DQ/DQS(Engine): PASS
2151 11:17:36.819065 TX OE : NO K
2152 11:17:36.822473 All Pass.
2153 11:17:36.822556
2154 11:17:36.822622 DramC Write-DBI off
2155 11:17:36.826097 PER_BANK_REFRESH: Hybrid Mode
2156 11:17:36.826180 TX_TRACKING: ON
2157 11:17:36.829071 [GetDramInforAfterCalByMRR] Vendor 6.
2158 11:17:36.836131 [GetDramInforAfterCalByMRR] Revision 606.
2159 11:17:36.839207 [GetDramInforAfterCalByMRR] Revision 2 0.
2160 11:17:36.839291 MR0 0x3b3b
2161 11:17:36.839363 MR8 0x5151
2162 11:17:36.842372 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2163 11:17:36.842468
2164 11:17:36.846202 MR0 0x3b3b
2165 11:17:36.846285 MR8 0x5151
2166 11:17:36.848971 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2167 11:17:36.849081
2168 11:17:36.859292 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2169 11:17:36.862992 [FAST_K] Save calibration result to emmc
2170 11:17:36.866123 [FAST_K] Save calibration result to emmc
2171 11:17:36.869350 dram_init: config_dvfs: 1
2172 11:17:36.872488 dramc_set_vcore_voltage set vcore to 662500
2173 11:17:36.872571 Read voltage for 1200, 2
2174 11:17:36.876331 Vio18 = 0
2175 11:17:36.876409 Vcore = 662500
2176 11:17:36.876474 Vdram = 0
2177 11:17:36.879357 Vddq = 0
2178 11:17:36.879442 Vmddr = 0
2179 11:17:36.885804 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2180 11:17:36.889291 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2181 11:17:36.892932 MEM_TYPE=3, freq_sel=15
2182 11:17:36.896474 sv_algorithm_assistance_LP4_1600
2183 11:17:36.899196 ============ PULL DRAM RESETB DOWN ============
2184 11:17:36.902812 ========== PULL DRAM RESETB DOWN end =========
2185 11:17:36.909146 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2186 11:17:36.912914 ===================================
2187 11:17:36.913043 LPDDR4 DRAM CONFIGURATION
2188 11:17:36.916454 ===================================
2189 11:17:36.919476 EX_ROW_EN[0] = 0x0
2190 11:17:36.919559 EX_ROW_EN[1] = 0x0
2191 11:17:36.922632 LP4Y_EN = 0x0
2192 11:17:36.922749 WORK_FSP = 0x0
2193 11:17:36.926434 WL = 0x4
2194 11:17:36.926508 RL = 0x4
2195 11:17:36.929244 BL = 0x2
2196 11:17:36.932730 RPST = 0x0
2197 11:17:36.932805 RD_PRE = 0x0
2198 11:17:36.936038 WR_PRE = 0x1
2199 11:17:36.936134 WR_PST = 0x0
2200 11:17:36.939666 DBI_WR = 0x0
2201 11:17:36.939781 DBI_RD = 0x0
2202 11:17:36.942684 OTF = 0x1
2203 11:17:36.946525 ===================================
2204 11:17:36.949600 ===================================
2205 11:17:36.949699 ANA top config
2206 11:17:36.952868 ===================================
2207 11:17:36.956477 DLL_ASYNC_EN = 0
2208 11:17:36.960018 ALL_SLAVE_EN = 0
2209 11:17:36.960092 NEW_RANK_MODE = 1
2210 11:17:36.962899 DLL_IDLE_MODE = 1
2211 11:17:36.966094 LP45_APHY_COMB_EN = 1
2212 11:17:36.969731 TX_ODT_DIS = 1
2213 11:17:36.969830 NEW_8X_MODE = 1
2214 11:17:36.972990 ===================================
2215 11:17:36.976057 ===================================
2216 11:17:36.979726 data_rate = 2400
2217 11:17:36.983012 CKR = 1
2218 11:17:36.986531 DQ_P2S_RATIO = 8
2219 11:17:36.989679 ===================================
2220 11:17:36.992760 CA_P2S_RATIO = 8
2221 11:17:36.996497 DQ_CA_OPEN = 0
2222 11:17:36.996612 DQ_SEMI_OPEN = 0
2223 11:17:36.999635 CA_SEMI_OPEN = 0
2224 11:17:37.003090 CA_FULL_RATE = 0
2225 11:17:37.006523 DQ_CKDIV4_EN = 0
2226 11:17:37.009790 CA_CKDIV4_EN = 0
2227 11:17:37.009866 CA_PREDIV_EN = 0
2228 11:17:37.013304 PH8_DLY = 17
2229 11:17:37.016671 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2230 11:17:37.020272 DQ_AAMCK_DIV = 4
2231 11:17:37.023456 CA_AAMCK_DIV = 4
2232 11:17:37.026398 CA_ADMCK_DIV = 4
2233 11:17:37.026474 DQ_TRACK_CA_EN = 0
2234 11:17:37.029800 CA_PICK = 1200
2235 11:17:37.033364 CA_MCKIO = 1200
2236 11:17:37.036151 MCKIO_SEMI = 0
2237 11:17:37.039866 PLL_FREQ = 2366
2238 11:17:37.043623 DQ_UI_PI_RATIO = 32
2239 11:17:37.046413 CA_UI_PI_RATIO = 0
2240 11:17:37.050146 ===================================
2241 11:17:37.053325 ===================================
2242 11:17:37.053402 memory_type:LPDDR4
2243 11:17:37.056520 GP_NUM : 10
2244 11:17:37.060222 SRAM_EN : 1
2245 11:17:37.060299 MD32_EN : 0
2246 11:17:37.063188 ===================================
2247 11:17:37.066419 [ANA_INIT] >>>>>>>>>>>>>>
2248 11:17:37.069880 <<<<<< [CONFIGURE PHASE]: ANA_TX
2249 11:17:37.073013 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2250 11:17:37.076737 ===================================
2251 11:17:37.080120 data_rate = 2400,PCW = 0X5b00
2252 11:17:37.083723 ===================================
2253 11:17:37.086787 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2254 11:17:37.090408 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2255 11:17:37.096628 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2256 11:17:37.099846 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2257 11:17:37.103295 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2258 11:17:37.106732 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2259 11:17:37.110307 [ANA_INIT] flow start
2260 11:17:37.113338 [ANA_INIT] PLL >>>>>>>>
2261 11:17:37.113414 [ANA_INIT] PLL <<<<<<<<
2262 11:17:37.116501 [ANA_INIT] MIDPI >>>>>>>>
2263 11:17:37.119961 [ANA_INIT] MIDPI <<<<<<<<
2264 11:17:37.120038 [ANA_INIT] DLL >>>>>>>>
2265 11:17:37.123111 [ANA_INIT] DLL <<<<<<<<
2266 11:17:37.126511 [ANA_INIT] flow end
2267 11:17:37.130117 ============ LP4 DIFF to SE enter ============
2268 11:17:37.133310 ============ LP4 DIFF to SE exit ============
2269 11:17:37.136491 [ANA_INIT] <<<<<<<<<<<<<
2270 11:17:37.140240 [Flow] Enable top DCM control >>>>>
2271 11:17:37.143341 [Flow] Enable top DCM control <<<<<
2272 11:17:37.146511 Enable DLL master slave shuffle
2273 11:17:37.150014 ==============================================================
2274 11:17:37.153778 Gating Mode config
2275 11:17:37.156871 ==============================================================
2276 11:17:37.160165 Config description:
2277 11:17:37.170341 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2278 11:17:37.176591 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2279 11:17:37.180090 SELPH_MODE 0: By rank 1: By Phase
2280 11:17:37.187064 ==============================================================
2281 11:17:37.190134 GAT_TRACK_EN = 1
2282 11:17:37.193225 RX_GATING_MODE = 2
2283 11:17:37.196661 RX_GATING_TRACK_MODE = 2
2284 11:17:37.199998 SELPH_MODE = 1
2285 11:17:37.203557 PICG_EARLY_EN = 1
2286 11:17:37.203660 VALID_LAT_VALUE = 1
2287 11:17:37.209954 ==============================================================
2288 11:17:37.213462 Enter into Gating configuration >>>>
2289 11:17:37.216863 Exit from Gating configuration <<<<
2290 11:17:37.220180 Enter into DVFS_PRE_config >>>>>
2291 11:17:37.230157 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2292 11:17:37.233738 Exit from DVFS_PRE_config <<<<<
2293 11:17:37.237036 Enter into PICG configuration >>>>
2294 11:17:37.240440 Exit from PICG configuration <<<<
2295 11:17:37.244134 [RX_INPUT] configuration >>>>>
2296 11:17:37.246982 [RX_INPUT] configuration <<<<<
2297 11:17:37.249974 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2298 11:17:37.256585 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2299 11:17:37.263317 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2300 11:17:37.269942 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2301 11:17:37.277204 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2302 11:17:37.280244 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2303 11:17:37.286872 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2304 11:17:37.290101 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2305 11:17:37.293757 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2306 11:17:37.297086 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2307 11:17:37.300113 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2308 11:17:37.306767 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2309 11:17:37.310226 ===================================
2310 11:17:37.313479 LPDDR4 DRAM CONFIGURATION
2311 11:17:37.316908 ===================================
2312 11:17:37.316992 EX_ROW_EN[0] = 0x0
2313 11:17:37.320413 EX_ROW_EN[1] = 0x0
2314 11:17:37.320517 LP4Y_EN = 0x0
2315 11:17:37.323812 WORK_FSP = 0x0
2316 11:17:37.323895 WL = 0x4
2317 11:17:37.326732 RL = 0x4
2318 11:17:37.326814 BL = 0x2
2319 11:17:37.330175 RPST = 0x0
2320 11:17:37.330275 RD_PRE = 0x0
2321 11:17:37.333430 WR_PRE = 0x1
2322 11:17:37.333512 WR_PST = 0x0
2323 11:17:37.336687 DBI_WR = 0x0
2324 11:17:37.336774 DBI_RD = 0x0
2325 11:17:37.340233 OTF = 0x1
2326 11:17:37.343315 ===================================
2327 11:17:37.346698 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2328 11:17:37.350287 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2329 11:17:37.356663 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2330 11:17:37.360249 ===================================
2331 11:17:37.360334 LPDDR4 DRAM CONFIGURATION
2332 11:17:37.363777 ===================================
2333 11:17:37.366838 EX_ROW_EN[0] = 0x10
2334 11:17:37.370132 EX_ROW_EN[1] = 0x0
2335 11:17:37.370216 LP4Y_EN = 0x0
2336 11:17:37.373724 WORK_FSP = 0x0
2337 11:17:37.373834 WL = 0x4
2338 11:17:37.376815 RL = 0x4
2339 11:17:37.376899 BL = 0x2
2340 11:17:37.380265 RPST = 0x0
2341 11:17:37.380349 RD_PRE = 0x0
2342 11:17:37.383261 WR_PRE = 0x1
2343 11:17:37.383375 WR_PST = 0x0
2344 11:17:37.386583 DBI_WR = 0x0
2345 11:17:37.386668 DBI_RD = 0x0
2346 11:17:37.389947 OTF = 0x1
2347 11:17:37.393154 ===================================
2348 11:17:37.400236 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2349 11:17:37.400321 ==
2350 11:17:37.403278 Dram Type= 6, Freq= 0, CH_0, rank 0
2351 11:17:37.406865 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2352 11:17:37.406950 ==
2353 11:17:37.409978 [Duty_Offset_Calibration]
2354 11:17:37.410062 B0:2 B1:1 CA:1
2355 11:17:37.410128
2356 11:17:37.413646 [DutyScan_Calibration_Flow] k_type=0
2357 11:17:37.423355
2358 11:17:37.423441 ==CLK 0==
2359 11:17:37.427016 Final CLK duty delay cell = 0
2360 11:17:37.429947 [0] MAX Duty = 5187%(X100), DQS PI = 24
2361 11:17:37.433435 [0] MIN Duty = 4844%(X100), DQS PI = 48
2362 11:17:37.436759 [0] AVG Duty = 5015%(X100)
2363 11:17:37.436834
2364 11:17:37.440130 CH0 CLK Duty spec in!! Max-Min= 343%
2365 11:17:37.443613 [DutyScan_Calibration_Flow] ====Done====
2366 11:17:37.443694
2367 11:17:37.446710 [DutyScan_Calibration_Flow] k_type=1
2368 11:17:37.462337
2369 11:17:37.462416 ==DQS 0 ==
2370 11:17:37.465671 Final DQS duty delay cell = -4
2371 11:17:37.468627 [-4] MAX Duty = 5124%(X100), DQS PI = 24
2372 11:17:37.472292 [-4] MIN Duty = 4782%(X100), DQS PI = 0
2373 11:17:37.475300 [-4] AVG Duty = 4953%(X100)
2374 11:17:37.475420
2375 11:17:37.475488 ==DQS 1 ==
2376 11:17:37.478539 Final DQS duty delay cell = 0
2377 11:17:37.482192 [0] MAX Duty = 5156%(X100), DQS PI = 0
2378 11:17:37.485969 [0] MIN Duty = 5000%(X100), DQS PI = 34
2379 11:17:37.486078 [0] AVG Duty = 5078%(X100)
2380 11:17:37.488822
2381 11:17:37.492322 CH0 DQS 0 Duty spec in!! Max-Min= 342%
2382 11:17:37.492413
2383 11:17:37.496027 CH0 DQS 1 Duty spec in!! Max-Min= 156%
2384 11:17:37.499190 [DutyScan_Calibration_Flow] ====Done====
2385 11:17:37.499267
2386 11:17:37.502257 [DutyScan_Calibration_Flow] k_type=3
2387 11:17:37.518739
2388 11:17:37.518832 ==DQM 0 ==
2389 11:17:37.522233 Final DQM duty delay cell = 0
2390 11:17:37.525620 [0] MAX Duty = 5156%(X100), DQS PI = 30
2391 11:17:37.529007 [0] MIN Duty = 4906%(X100), DQS PI = 50
2392 11:17:37.532242 [0] AVG Duty = 5031%(X100)
2393 11:17:37.532345
2394 11:17:37.532437 ==DQM 1 ==
2395 11:17:37.535901 Final DQM duty delay cell = 0
2396 11:17:37.538822 [0] MAX Duty = 5125%(X100), DQS PI = 60
2397 11:17:37.542230 [0] MIN Duty = 5031%(X100), DQS PI = 14
2398 11:17:37.545591 [0] AVG Duty = 5078%(X100)
2399 11:17:37.545696
2400 11:17:37.549006 CH0 DQM 0 Duty spec in!! Max-Min= 250%
2401 11:17:37.549112
2402 11:17:37.551979 CH0 DQM 1 Duty spec in!! Max-Min= 94%
2403 11:17:37.555835 [DutyScan_Calibration_Flow] ====Done====
2404 11:17:37.555950
2405 11:17:37.558894 [DutyScan_Calibration_Flow] k_type=2
2406 11:17:37.575134
2407 11:17:37.575282 ==DQ 0 ==
2408 11:17:37.578692 Final DQ duty delay cell = 0
2409 11:17:37.581741 [0] MAX Duty = 5062%(X100), DQS PI = 32
2410 11:17:37.585634 [0] MIN Duty = 4875%(X100), DQS PI = 62
2411 11:17:37.585742 [0] AVG Duty = 4968%(X100)
2412 11:17:37.588511
2413 11:17:37.588618 ==DQ 1 ==
2414 11:17:37.592197 Final DQ duty delay cell = 0
2415 11:17:37.595281 [0] MAX Duty = 5093%(X100), DQS PI = 10
2416 11:17:37.598752 [0] MIN Duty = 4969%(X100), DQS PI = 2
2417 11:17:37.598863 [0] AVG Duty = 5031%(X100)
2418 11:17:37.598958
2419 11:17:37.602229 CH0 DQ 0 Duty spec in!! Max-Min= 187%
2420 11:17:37.602369
2421 11:17:37.605466 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2422 11:17:37.612058 [DutyScan_Calibration_Flow] ====Done====
2423 11:17:37.612167 ==
2424 11:17:37.615201 Dram Type= 6, Freq= 0, CH_1, rank 0
2425 11:17:37.618673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2426 11:17:37.618795 ==
2427 11:17:37.622256 [Duty_Offset_Calibration]
2428 11:17:37.622382 B0:1 B1:0 CA:1
2429 11:17:37.622501
2430 11:17:37.625585 [DutyScan_Calibration_Flow] k_type=0
2431 11:17:37.634790
2432 11:17:37.634902 ==CLK 0==
2433 11:17:37.638118 Final CLK duty delay cell = -4
2434 11:17:37.641038 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2435 11:17:37.644760 [-4] MIN Duty = 4907%(X100), DQS PI = 12
2436 11:17:37.648218 [-4] AVG Duty = 4969%(X100)
2437 11:17:37.648338
2438 11:17:37.650820 CH1 CLK Duty spec in!! Max-Min= 124%
2439 11:17:37.654286 [DutyScan_Calibration_Flow] ====Done====
2440 11:17:37.654371
2441 11:17:37.657658 [DutyScan_Calibration_Flow] k_type=1
2442 11:17:37.674319
2443 11:17:37.674440 ==DQS 0 ==
2444 11:17:37.678024 Final DQS duty delay cell = 0
2445 11:17:37.680947 [0] MAX Duty = 5094%(X100), DQS PI = 28
2446 11:17:37.684744 [0] MIN Duty = 4875%(X100), DQS PI = 0
2447 11:17:37.684866 [0] AVG Duty = 4984%(X100)
2448 11:17:37.684963
2449 11:17:37.687730 ==DQS 1 ==
2450 11:17:37.691274 Final DQS duty delay cell = 0
2451 11:17:37.694419 [0] MAX Duty = 5187%(X100), DQS PI = 20
2452 11:17:37.698165 [0] MIN Duty = 4969%(X100), DQS PI = 8
2453 11:17:37.698278 [0] AVG Duty = 5078%(X100)
2454 11:17:37.698375
2455 11:17:37.701054 CH1 DQS 0 Duty spec in!! Max-Min= 219%
2456 11:17:37.704719
2457 11:17:37.707872 CH1 DQS 1 Duty spec in!! Max-Min= 218%
2458 11:17:37.711574 [DutyScan_Calibration_Flow] ====Done====
2459 11:17:37.711685
2460 11:17:37.714763 [DutyScan_Calibration_Flow] k_type=3
2461 11:17:37.731445
2462 11:17:37.731558 ==DQM 0 ==
2463 11:17:37.734361 Final DQM duty delay cell = 0
2464 11:17:37.737597 [0] MAX Duty = 5156%(X100), DQS PI = 6
2465 11:17:37.741307 [0] MIN Duty = 5031%(X100), DQS PI = 0
2466 11:17:37.741412 [0] AVG Duty = 5093%(X100)
2467 11:17:37.741511
2468 11:17:37.744464 ==DQM 1 ==
2469 11:17:37.747704 Final DQM duty delay cell = 0
2470 11:17:37.750677 [0] MAX Duty = 5031%(X100), DQS PI = 16
2471 11:17:37.754173 [0] MIN Duty = 4907%(X100), DQS PI = 36
2472 11:17:37.754282 [0] AVG Duty = 4969%(X100)
2473 11:17:37.754377
2474 11:17:37.757765 CH1 DQM 0 Duty spec in!! Max-Min= 125%
2475 11:17:37.761116
2476 11:17:37.764167 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2477 11:17:37.767526 [DutyScan_Calibration_Flow] ====Done====
2478 11:17:37.767638
2479 11:17:37.771096 [DutyScan_Calibration_Flow] k_type=2
2480 11:17:37.786895
2481 11:17:37.786995 ==DQ 0 ==
2482 11:17:37.789905 Final DQ duty delay cell = -4
2483 11:17:37.793559 [-4] MAX Duty = 5062%(X100), DQS PI = 8
2484 11:17:37.796789 [-4] MIN Duty = 4938%(X100), DQS PI = 0
2485 11:17:37.796902 [-4] AVG Duty = 5000%(X100)
2486 11:17:37.800047
2487 11:17:37.800160 ==DQ 1 ==
2488 11:17:37.803089 Final DQ duty delay cell = 0
2489 11:17:37.806683 [0] MAX Duty = 5125%(X100), DQS PI = 20
2490 11:17:37.810794 [0] MIN Duty = 4969%(X100), DQS PI = 12
2491 11:17:37.810909 [0] AVG Duty = 5047%(X100)
2492 11:17:37.811010
2493 11:17:37.813177 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2494 11:17:37.816579
2495 11:17:37.820174 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2496 11:17:37.823078 [DutyScan_Calibration_Flow] ====Done====
2497 11:17:37.827092 nWR fixed to 30
2498 11:17:37.827203 [ModeRegInit_LP4] CH0 RK0
2499 11:17:37.830004 [ModeRegInit_LP4] CH0 RK1
2500 11:17:37.833642 [ModeRegInit_LP4] CH1 RK0
2501 11:17:37.833754 [ModeRegInit_LP4] CH1 RK1
2502 11:17:37.836508 match AC timing 7
2503 11:17:37.840167 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2504 11:17:37.843398 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2505 11:17:37.850114 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2506 11:17:37.853076 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2507 11:17:37.859986 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2508 11:17:37.860114 ==
2509 11:17:37.863453 Dram Type= 6, Freq= 0, CH_0, rank 0
2510 11:17:37.866926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2511 11:17:37.867039 ==
2512 11:17:37.873280 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2513 11:17:37.876814 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2514 11:17:37.886801 [CA 0] Center 39 (8~70) winsize 63
2515 11:17:37.889973 [CA 1] Center 39 (8~70) winsize 63
2516 11:17:37.893592 [CA 2] Center 35 (5~66) winsize 62
2517 11:17:37.896494 [CA 3] Center 34 (4~65) winsize 62
2518 11:17:37.900209 [CA 4] Center 33 (3~64) winsize 62
2519 11:17:37.903278 [CA 5] Center 32 (3~62) winsize 60
2520 11:17:37.903391
2521 11:17:37.907273 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2522 11:17:37.907416
2523 11:17:37.910273 [CATrainingPosCal] consider 1 rank data
2524 11:17:37.913587 u2DelayCellTimex100 = 270/100 ps
2525 11:17:37.917185 CA0 delay=39 (8~70),Diff = 7 PI (33 cell)
2526 11:17:37.920038 CA1 delay=39 (8~70),Diff = 7 PI (33 cell)
2527 11:17:37.927024 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2528 11:17:37.929967 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2529 11:17:37.933846 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2530 11:17:37.936692 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2531 11:17:37.936801
2532 11:17:37.940394 CA PerBit enable=1, Macro0, CA PI delay=32
2533 11:17:37.940476
2534 11:17:37.943623 [CBTSetCACLKResult] CA Dly = 32
2535 11:17:37.943707 CS Dly: 6 (0~37)
2536 11:17:37.943773 ==
2537 11:17:37.946786 Dram Type= 6, Freq= 0, CH_0, rank 1
2538 11:17:37.953522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2539 11:17:37.953606 ==
2540 11:17:37.956592 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2541 11:17:37.963501 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2542 11:17:37.972147 [CA 0] Center 38 (8~69) winsize 62
2543 11:17:37.975691 [CA 1] Center 38 (8~69) winsize 62
2544 11:17:37.979098 [CA 2] Center 35 (4~66) winsize 63
2545 11:17:37.982526 [CA 3] Center 34 (4~65) winsize 62
2546 11:17:37.985867 [CA 4] Center 33 (3~64) winsize 62
2547 11:17:37.988961 [CA 5] Center 32 (3~62) winsize 60
2548 11:17:37.989045
2549 11:17:37.992713 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2550 11:17:37.992798
2551 11:17:37.995702 [CATrainingPosCal] consider 2 rank data
2552 11:17:37.999335 u2DelayCellTimex100 = 270/100 ps
2553 11:17:38.002208 CA0 delay=38 (8~69),Diff = 6 PI (28 cell)
2554 11:17:38.006098 CA1 delay=38 (8~69),Diff = 6 PI (28 cell)
2555 11:17:38.012420 CA2 delay=35 (5~66),Diff = 3 PI (14 cell)
2556 11:17:38.016146 CA3 delay=34 (4~65),Diff = 2 PI (9 cell)
2557 11:17:38.019312 CA4 delay=33 (3~64),Diff = 1 PI (4 cell)
2558 11:17:38.022752 CA5 delay=32 (3~62),Diff = 0 PI (0 cell)
2559 11:17:38.022836
2560 11:17:38.025730 CA PerBit enable=1, Macro0, CA PI delay=32
2561 11:17:38.025814
2562 11:17:38.029066 [CBTSetCACLKResult] CA Dly = 32
2563 11:17:38.029167 CS Dly: 6 (0~38)
2564 11:17:38.029263
2565 11:17:38.032708 ----->DramcWriteLeveling(PI) begin...
2566 11:17:38.032792 ==
2567 11:17:38.036200 Dram Type= 6, Freq= 0, CH_0, rank 0
2568 11:17:38.042834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2569 11:17:38.042932 ==
2570 11:17:38.045916 Write leveling (Byte 0): 33 => 33
2571 11:17:38.049101 Write leveling (Byte 1): 28 => 28
2572 11:17:38.049199 DramcWriteLeveling(PI) end<-----
2573 11:17:38.049294
2574 11:17:38.052931 ==
2575 11:17:38.055989 Dram Type= 6, Freq= 0, CH_0, rank 0
2576 11:17:38.059174 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2577 11:17:38.059271 ==
2578 11:17:38.062814 [Gating] SW mode calibration
2579 11:17:38.069301 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2580 11:17:38.072731 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2581 11:17:38.079610 0 15 0 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
2582 11:17:38.083064 0 15 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
2583 11:17:38.086461 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2584 11:17:38.092597 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2585 11:17:38.096145 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2586 11:17:38.099834 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2587 11:17:38.106201 0 15 24 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 0)
2588 11:17:38.109751 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
2589 11:17:38.112964 1 0 0 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
2590 11:17:38.116193 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2591 11:17:38.122950 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2592 11:17:38.126173 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2593 11:17:38.129742 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2594 11:17:38.136176 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2595 11:17:38.139723 1 0 24 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
2596 11:17:38.143182 1 0 28 | B1->B0 | 2929 4545 | 1 0 | (0 0) (1 1)
2597 11:17:38.149959 1 1 0 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
2598 11:17:38.152953 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2599 11:17:38.156626 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2600 11:17:38.162945 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2601 11:17:38.166878 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2602 11:17:38.169907 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2603 11:17:38.176159 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2604 11:17:38.180020 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2605 11:17:38.183530 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2606 11:17:38.189767 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2607 11:17:38.193018 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2608 11:17:38.196474 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2609 11:17:38.199981 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2610 11:17:38.206470 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2611 11:17:38.210277 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2612 11:17:38.213307 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2613 11:17:38.220094 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2614 11:17:38.223250 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2615 11:17:38.227207 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2616 11:17:38.233210 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2617 11:17:38.236951 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2618 11:17:38.239756 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2619 11:17:38.246808 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2620 11:17:38.250202 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2621 11:17:38.253620 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2622 11:17:38.257430 Total UI for P1: 0, mck2ui 16
2623 11:17:38.260375 best dqsien dly found for B0: ( 1, 3, 26)
2624 11:17:38.263486 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2625 11:17:38.267220 Total UI for P1: 0, mck2ui 16
2626 11:17:38.270591 best dqsien dly found for B1: ( 1, 4, 0)
2627 11:17:38.273515 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2628 11:17:38.277241 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2629 11:17:38.277323
2630 11:17:38.283720 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2631 11:17:38.287029 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2632 11:17:38.287111 [Gating] SW calibration Done
2633 11:17:38.290278 ==
2634 11:17:38.294037 Dram Type= 6, Freq= 0, CH_0, rank 0
2635 11:17:38.296999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2636 11:17:38.297102 ==
2637 11:17:38.297201 RX Vref Scan: 0
2638 11:17:38.297291
2639 11:17:38.300484 RX Vref 0 -> 0, step: 1
2640 11:17:38.300582
2641 11:17:38.303779 RX Delay -40 -> 252, step: 8
2642 11:17:38.306749 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2643 11:17:38.310626 iDelay=200, Bit 1, Center 123 (48 ~ 199) 152
2644 11:17:38.313497 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2645 11:17:38.320371 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2646 11:17:38.323766 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2647 11:17:38.327075 iDelay=200, Bit 5, Center 115 (48 ~ 183) 136
2648 11:17:38.330744 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2649 11:17:38.333935 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2650 11:17:38.340641 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2651 11:17:38.343833 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
2652 11:17:38.347129 iDelay=200, Bit 10, Center 111 (48 ~ 175) 128
2653 11:17:38.350148 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2654 11:17:38.353715 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2655 11:17:38.360428 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2656 11:17:38.363816 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2657 11:17:38.367012 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
2658 11:17:38.367138 ==
2659 11:17:38.370687 Dram Type= 6, Freq= 0, CH_0, rank 0
2660 11:17:38.374012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2661 11:17:38.374083 ==
2662 11:17:38.376890 DQS Delay:
2663 11:17:38.376958 DQS0 = 0, DQS1 = 0
2664 11:17:38.380713 DQM Delay:
2665 11:17:38.380794 DQM0 = 122, DQM1 = 113
2666 11:17:38.380854 DQ Delay:
2667 11:17:38.386822 DQ0 =119, DQ1 =123, DQ2 =119, DQ3 =119
2668 11:17:38.390417 DQ4 =127, DQ5 =115, DQ6 =127, DQ7 =127
2669 11:17:38.394106 DQ8 =99, DQ9 =107, DQ10 =111, DQ11 =107
2670 11:17:38.397054 DQ12 =119, DQ13 =123, DQ14 =123, DQ15 =119
2671 11:17:38.397128
2672 11:17:38.397191
2673 11:17:38.397259 ==
2674 11:17:38.400240 Dram Type= 6, Freq= 0, CH_0, rank 0
2675 11:17:38.403400 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2676 11:17:38.403486 ==
2677 11:17:38.403554
2678 11:17:38.403612
2679 11:17:38.406855 TX Vref Scan disable
2680 11:17:38.410423 == TX Byte 0 ==
2681 11:17:38.413767 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2682 11:17:38.416709 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2683 11:17:38.420148 == TX Byte 1 ==
2684 11:17:38.423658 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
2685 11:17:38.427209 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
2686 11:17:38.427331 ==
2687 11:17:38.430474 Dram Type= 6, Freq= 0, CH_0, rank 0
2688 11:17:38.433980 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2689 11:17:38.437144 ==
2690 11:17:38.447224 TX Vref=22, minBit 0, minWin=25, winSum=408
2691 11:17:38.450902 TX Vref=24, minBit 0, minWin=25, winSum=417
2692 11:17:38.453691 TX Vref=26, minBit 4, minWin=25, winSum=420
2693 11:17:38.457164 TX Vref=28, minBit 0, minWin=26, winSum=426
2694 11:17:38.460688 TX Vref=30, minBit 0, minWin=26, winSum=425
2695 11:17:38.464253 TX Vref=32, minBit 0, minWin=26, winSum=426
2696 11:17:38.470936 [TxChooseVref] Worse bit 0, Min win 26, Win sum 426, Final Vref 28
2697 11:17:38.471042
2698 11:17:38.474001 Final TX Range 1 Vref 28
2699 11:17:38.474108
2700 11:17:38.474200 ==
2701 11:17:38.477132 Dram Type= 6, Freq= 0, CH_0, rank 0
2702 11:17:38.480800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2703 11:17:38.480906 ==
2704 11:17:38.480979
2705 11:17:38.483859
2706 11:17:38.483950 TX Vref Scan disable
2707 11:17:38.487732 == TX Byte 0 ==
2708 11:17:38.490795 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2709 11:17:38.494008 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2710 11:17:38.497373 == TX Byte 1 ==
2711 11:17:38.500521 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2712 11:17:38.504429 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2713 11:17:38.504512
2714 11:17:38.507421 [DATLAT]
2715 11:17:38.507505 Freq=1200, CH0 RK0
2716 11:17:38.507571
2717 11:17:38.511192 DATLAT Default: 0xd
2718 11:17:38.511276 0, 0xFFFF, sum = 0
2719 11:17:38.513947 1, 0xFFFF, sum = 0
2720 11:17:38.514032 2, 0xFFFF, sum = 0
2721 11:17:38.517711 3, 0xFFFF, sum = 0
2722 11:17:38.517796 4, 0xFFFF, sum = 0
2723 11:17:38.520486 5, 0xFFFF, sum = 0
2724 11:17:38.520571 6, 0xFFFF, sum = 0
2725 11:17:38.524089 7, 0xFFFF, sum = 0
2726 11:17:38.524174 8, 0xFFFF, sum = 0
2727 11:17:38.527562 9, 0xFFFF, sum = 0
2728 11:17:38.530943 10, 0xFFFF, sum = 0
2729 11:17:38.531027 11, 0xFFFF, sum = 0
2730 11:17:38.534330 12, 0x0, sum = 1
2731 11:17:38.534426 13, 0x0, sum = 2
2732 11:17:38.534495 14, 0x0, sum = 3
2733 11:17:38.537903 15, 0x0, sum = 4
2734 11:17:38.537987 best_step = 13
2735 11:17:38.538053
2736 11:17:38.538115 ==
2737 11:17:38.540765 Dram Type= 6, Freq= 0, CH_0, rank 0
2738 11:17:38.547595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2739 11:17:38.547684 ==
2740 11:17:38.547750 RX Vref Scan: 1
2741 11:17:38.547818
2742 11:17:38.551123 Set Vref Range= 32 -> 127
2743 11:17:38.551206
2744 11:17:38.554390 RX Vref 32 -> 127, step: 1
2745 11:17:38.554473
2746 11:17:38.557361 RX Delay -13 -> 252, step: 4
2747 11:17:38.557443
2748 11:17:38.560778 Set Vref, RX VrefLevel [Byte0]: 32
2749 11:17:38.564268 [Byte1]: 32
2750 11:17:38.564361
2751 11:17:38.567299 Set Vref, RX VrefLevel [Byte0]: 33
2752 11:17:38.570734 [Byte1]: 33
2753 11:17:38.570821
2754 11:17:38.574345 Set Vref, RX VrefLevel [Byte0]: 34
2755 11:17:38.577275 [Byte1]: 34
2756 11:17:38.581680
2757 11:17:38.581770 Set Vref, RX VrefLevel [Byte0]: 35
2758 11:17:38.584795 [Byte1]: 35
2759 11:17:38.589042
2760 11:17:38.589129 Set Vref, RX VrefLevel [Byte0]: 36
2761 11:17:38.592416 [Byte1]: 36
2762 11:17:38.596774
2763 11:17:38.596853 Set Vref, RX VrefLevel [Byte0]: 37
2764 11:17:38.600199 [Byte1]: 37
2765 11:17:38.605242
2766 11:17:38.605339 Set Vref, RX VrefLevel [Byte0]: 38
2767 11:17:38.608465 [Byte1]: 38
2768 11:17:38.612753
2769 11:17:38.612839 Set Vref, RX VrefLevel [Byte0]: 39
2770 11:17:38.616264 [Byte1]: 39
2771 11:17:38.620626
2772 11:17:38.620719 Set Vref, RX VrefLevel [Byte0]: 40
2773 11:17:38.624194 [Byte1]: 40
2774 11:17:38.628855
2775 11:17:38.628950 Set Vref, RX VrefLevel [Byte0]: 41
2776 11:17:38.631941 [Byte1]: 41
2777 11:17:38.636532
2778 11:17:38.636627 Set Vref, RX VrefLevel [Byte0]: 42
2779 11:17:38.639815 [Byte1]: 42
2780 11:17:38.644513
2781 11:17:38.644598 Set Vref, RX VrefLevel [Byte0]: 43
2782 11:17:38.647681 [Byte1]: 43
2783 11:17:38.652030
2784 11:17:38.652118 Set Vref, RX VrefLevel [Byte0]: 44
2785 11:17:38.655591 [Byte1]: 44
2786 11:17:38.660397
2787 11:17:38.660491 Set Vref, RX VrefLevel [Byte0]: 45
2788 11:17:38.663594 [Byte1]: 45
2789 11:17:38.668150
2790 11:17:38.668237 Set Vref, RX VrefLevel [Byte0]: 46
2791 11:17:38.671417 [Byte1]: 46
2792 11:17:38.676232
2793 11:17:38.676323 Set Vref, RX VrefLevel [Byte0]: 47
2794 11:17:38.679000 [Byte1]: 47
2795 11:17:38.684310
2796 11:17:38.684398 Set Vref, RX VrefLevel [Byte0]: 48
2797 11:17:38.687441 [Byte1]: 48
2798 11:17:38.691766
2799 11:17:38.691850 Set Vref, RX VrefLevel [Byte0]: 49
2800 11:17:38.694963 [Byte1]: 49
2801 11:17:38.699792
2802 11:17:38.699876 Set Vref, RX VrefLevel [Byte0]: 50
2803 11:17:38.703196 [Byte1]: 50
2804 11:17:38.707321
2805 11:17:38.707420 Set Vref, RX VrefLevel [Byte0]: 51
2806 11:17:38.711135 [Byte1]: 51
2807 11:17:38.715568
2808 11:17:38.715652 Set Vref, RX VrefLevel [Byte0]: 52
2809 11:17:38.718970 [Byte1]: 52
2810 11:17:38.723044
2811 11:17:38.723128 Set Vref, RX VrefLevel [Byte0]: 53
2812 11:17:38.726873 [Byte1]: 53
2813 11:17:38.731136
2814 11:17:38.731243 Set Vref, RX VrefLevel [Byte0]: 54
2815 11:17:38.734381 [Byte1]: 54
2816 11:17:38.739133
2817 11:17:38.739242 Set Vref, RX VrefLevel [Byte0]: 55
2818 11:17:38.742169 [Byte1]: 55
2819 11:17:38.747116
2820 11:17:38.747198 Set Vref, RX VrefLevel [Byte0]: 56
2821 11:17:38.750036 [Byte1]: 56
2822 11:17:38.754669
2823 11:17:38.754752 Set Vref, RX VrefLevel [Byte0]: 57
2824 11:17:38.758355 [Byte1]: 57
2825 11:17:38.762629
2826 11:17:38.762701 Set Vref, RX VrefLevel [Byte0]: 58
2827 11:17:38.766200 [Byte1]: 58
2828 11:17:38.770898
2829 11:17:38.770981 Set Vref, RX VrefLevel [Byte0]: 59
2830 11:17:38.773992 [Byte1]: 59
2831 11:17:38.778664
2832 11:17:38.778757 Set Vref, RX VrefLevel [Byte0]: 60
2833 11:17:38.781927 [Byte1]: 60
2834 11:17:38.786653
2835 11:17:38.786731 Set Vref, RX VrefLevel [Byte0]: 61
2836 11:17:38.789510 [Byte1]: 61
2837 11:17:38.794521
2838 11:17:38.794599 Set Vref, RX VrefLevel [Byte0]: 62
2839 11:17:38.797647 [Byte1]: 62
2840 11:17:38.802572
2841 11:17:38.802658 Set Vref, RX VrefLevel [Byte0]: 63
2842 11:17:38.805667 [Byte1]: 63
2843 11:17:38.810520
2844 11:17:38.810635 Set Vref, RX VrefLevel [Byte0]: 64
2845 11:17:38.813195 [Byte1]: 64
2846 11:17:38.818024
2847 11:17:38.818127 Set Vref, RX VrefLevel [Byte0]: 65
2848 11:17:38.821199 [Byte1]: 65
2849 11:17:38.826193
2850 11:17:38.826307 Set Vref, RX VrefLevel [Byte0]: 66
2851 11:17:38.829342 [Byte1]: 66
2852 11:17:38.833522
2853 11:17:38.833631 Set Vref, RX VrefLevel [Byte0]: 67
2854 11:17:38.836937 [Byte1]: 67
2855 11:17:38.841512
2856 11:17:38.841626 Set Vref, RX VrefLevel [Byte0]: 68
2857 11:17:38.844951 [Byte1]: 68
2858 11:17:38.849697
2859 11:17:38.849805 Set Vref, RX VrefLevel [Byte0]: 69
2860 11:17:38.853074 [Byte1]: 69
2861 11:17:38.857533
2862 11:17:38.857647 Final RX Vref Byte 0 = 54 to rank0
2863 11:17:38.860639 Final RX Vref Byte 1 = 55 to rank0
2864 11:17:38.864334 Final RX Vref Byte 0 = 54 to rank1
2865 11:17:38.867621 Final RX Vref Byte 1 = 55 to rank1==
2866 11:17:38.870430 Dram Type= 6, Freq= 0, CH_0, rank 0
2867 11:17:38.877068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2868 11:17:38.877179 ==
2869 11:17:38.877281 DQS Delay:
2870 11:17:38.880606 DQS0 = 0, DQS1 = 0
2871 11:17:38.880694 DQM Delay:
2872 11:17:38.880767 DQM0 = 120, DQM1 = 113
2873 11:17:38.884194 DQ Delay:
2874 11:17:38.886993 DQ0 =120, DQ1 =120, DQ2 =118, DQ3 =118
2875 11:17:38.890469 DQ4 =122, DQ5 =112, DQ6 =126, DQ7 =128
2876 11:17:38.893978 DQ8 =100, DQ9 =102, DQ10 =116, DQ11 =106
2877 11:17:38.897176 DQ12 =120, DQ13 =118, DQ14 =126, DQ15 =122
2878 11:17:38.897279
2879 11:17:38.897381
2880 11:17:38.907598 [DQSOSCAuto] RK0, (LSB)MR18= 0x160f, (MSB)MR19= 0x404, tDQSOscB0 = 404 ps tDQSOscB1 = 401 ps
2881 11:17:38.907710 CH0 RK0: MR19=404, MR18=160F
2882 11:17:38.914170 CH0_RK0: MR19=0x404, MR18=0x160F, DQSOSC=401, MR23=63, INC=40, DEC=27
2883 11:17:38.914255
2884 11:17:38.917319 ----->DramcWriteLeveling(PI) begin...
2885 11:17:38.917405 ==
2886 11:17:38.920518 Dram Type= 6, Freq= 0, CH_0, rank 1
2887 11:17:38.924208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2888 11:17:38.927113 ==
2889 11:17:38.930751 Write leveling (Byte 0): 33 => 33
2890 11:17:38.930866 Write leveling (Byte 1): 30 => 30
2891 11:17:38.933979 DramcWriteLeveling(PI) end<-----
2892 11:17:38.934062
2893 11:17:38.934129 ==
2894 11:17:38.937091 Dram Type= 6, Freq= 0, CH_0, rank 1
2895 11:17:38.943785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2896 11:17:38.943868 ==
2897 11:17:38.943934 [Gating] SW mode calibration
2898 11:17:38.953929 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2899 11:17:38.957222 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2900 11:17:38.960760 0 15 0 | B1->B0 | 3434 3030 | 0 0 | (0 0) (0 0)
2901 11:17:38.967388 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2902 11:17:38.970598 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2903 11:17:38.974185 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2904 11:17:38.980820 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2905 11:17:38.984089 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2906 11:17:38.987251 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2907 11:17:38.994145 0 15 28 | B1->B0 | 3434 2e2e | 0 0 | (0 1) (0 0)
2908 11:17:38.997722 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
2909 11:17:39.000778 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2910 11:17:39.007441 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2911 11:17:39.011046 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2912 11:17:39.014451 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2913 11:17:39.021044 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2914 11:17:39.024328 1 0 24 | B1->B0 | 2626 2525 | 0 0 | (0 0) (0 0)
2915 11:17:39.027913 1 0 28 | B1->B0 | 3636 3434 | 0 0 | (0 0) (0 0)
2916 11:17:39.034198 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2917 11:17:39.037926 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2918 11:17:39.040876 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2919 11:17:39.044095 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2920 11:17:39.050848 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2921 11:17:39.054689 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2922 11:17:39.057585 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2923 11:17:39.064459 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2924 11:17:39.067862 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2925 11:17:39.070952 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2926 11:17:39.077593 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2927 11:17:39.080945 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2928 11:17:39.084586 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2929 11:17:39.090848 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2930 11:17:39.094342 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2931 11:17:39.097985 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2932 11:17:39.104282 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2933 11:17:39.107298 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2934 11:17:39.110779 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2935 11:17:39.117873 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2936 11:17:39.121557 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2937 11:17:39.124652 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2938 11:17:39.127665 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2939 11:17:39.134543 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2940 11:17:39.137514 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2941 11:17:39.141405 Total UI for P1: 0, mck2ui 16
2942 11:17:39.144419 best dqsien dly found for B0: ( 1, 3, 28)
2943 11:17:39.148141 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2944 11:17:39.151152 Total UI for P1: 0, mck2ui 16
2945 11:17:39.154156 best dqsien dly found for B1: ( 1, 3, 30)
2946 11:17:39.157838 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2947 11:17:39.161134 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2948 11:17:39.161247
2949 11:17:39.167816 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2950 11:17:39.171493 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2951 11:17:39.171575 [Gating] SW calibration Done
2952 11:17:39.174639 ==
2953 11:17:39.178007 Dram Type= 6, Freq= 0, CH_0, rank 1
2954 11:17:39.181533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2955 11:17:39.181630 ==
2956 11:17:39.181694 RX Vref Scan: 0
2957 11:17:39.181754
2958 11:17:39.184595 RX Vref 0 -> 0, step: 1
2959 11:17:39.184676
2960 11:17:39.188083 RX Delay -40 -> 252, step: 8
2961 11:17:39.191117 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2962 11:17:39.194661 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2963 11:17:39.197837 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2964 11:17:39.204687 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
2965 11:17:39.207873 iDelay=200, Bit 4, Center 127 (56 ~ 199) 144
2966 11:17:39.211213 iDelay=200, Bit 5, Center 119 (48 ~ 191) 144
2967 11:17:39.214715 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2968 11:17:39.218212 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2969 11:17:39.224421 iDelay=200, Bit 8, Center 107 (40 ~ 175) 136
2970 11:17:39.228163 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
2971 11:17:39.231219 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
2972 11:17:39.234921 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
2973 11:17:39.238146 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2974 11:17:39.244787 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
2975 11:17:39.248133 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2976 11:17:39.251452 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
2977 11:17:39.251534 ==
2978 11:17:39.254859 Dram Type= 6, Freq= 0, CH_0, rank 1
2979 11:17:39.257923 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2980 11:17:39.258038 ==
2981 11:17:39.261649 DQS Delay:
2982 11:17:39.261731 DQS0 = 0, DQS1 = 0
2983 11:17:39.264893 DQM Delay:
2984 11:17:39.264974 DQM0 = 122, DQM1 = 114
2985 11:17:39.265039 DQ Delay:
2986 11:17:39.268692 DQ0 =119, DQ1 =119, DQ2 =119, DQ3 =119
2987 11:17:39.271627 DQ4 =127, DQ5 =119, DQ6 =127, DQ7 =127
2988 11:17:39.278411 DQ8 =107, DQ9 =103, DQ10 =115, DQ11 =107
2989 11:17:39.281791 DQ12 =115, DQ13 =123, DQ14 =123, DQ15 =123
2990 11:17:39.281872
2991 11:17:39.281937
2992 11:17:39.281997 ==
2993 11:17:39.285362 Dram Type= 6, Freq= 0, CH_0, rank 1
2994 11:17:39.288358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2995 11:17:39.288465 ==
2996 11:17:39.288567
2997 11:17:39.288667
2998 11:17:39.291815 TX Vref Scan disable
2999 11:17:39.291927 == TX Byte 0 ==
3000 11:17:39.298202 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3001 11:17:39.302054 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3002 11:17:39.302139 == TX Byte 1 ==
3003 11:17:39.308505 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3004 11:17:39.311962 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3005 11:17:39.312059 ==
3006 11:17:39.315017 Dram Type= 6, Freq= 0, CH_0, rank 1
3007 11:17:39.318289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3008 11:17:39.318380 ==
3009 11:17:39.331817 TX Vref=22, minBit 1, minWin=25, winSum=416
3010 11:17:39.335551 TX Vref=24, minBit 1, minWin=25, winSum=418
3011 11:17:39.338524 TX Vref=26, minBit 4, minWin=25, winSum=422
3012 11:17:39.341831 TX Vref=28, minBit 1, minWin=26, winSum=427
3013 11:17:39.345248 TX Vref=30, minBit 1, minWin=26, winSum=428
3014 11:17:39.348431 TX Vref=32, minBit 0, minWin=26, winSum=428
3015 11:17:39.355237 [TxChooseVref] Worse bit 1, Min win 26, Win sum 428, Final Vref 30
3016 11:17:39.355376
3017 11:17:39.358402 Final TX Range 1 Vref 30
3018 11:17:39.358512
3019 11:17:39.358612 ==
3020 11:17:39.362096 Dram Type= 6, Freq= 0, CH_0, rank 1
3021 11:17:39.365077 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3022 11:17:39.365160 ==
3023 11:17:39.365225
3024 11:17:39.365286
3025 11:17:39.368312 TX Vref Scan disable
3026 11:17:39.372035 == TX Byte 0 ==
3027 11:17:39.375289 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3028 11:17:39.378301 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3029 11:17:39.381845 == TX Byte 1 ==
3030 11:17:39.385302 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3031 11:17:39.388597 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3032 11:17:39.388680
3033 11:17:39.392086 [DATLAT]
3034 11:17:39.392209 Freq=1200, CH0 RK1
3035 11:17:39.392302
3036 11:17:39.395183 DATLAT Default: 0xd
3037 11:17:39.395266 0, 0xFFFF, sum = 0
3038 11:17:39.398327 1, 0xFFFF, sum = 0
3039 11:17:39.398411 2, 0xFFFF, sum = 0
3040 11:17:39.401820 3, 0xFFFF, sum = 0
3041 11:17:39.401934 4, 0xFFFF, sum = 0
3042 11:17:39.405555 5, 0xFFFF, sum = 0
3043 11:17:39.405717 6, 0xFFFF, sum = 0
3044 11:17:39.409119 7, 0xFFFF, sum = 0
3045 11:17:39.409236 8, 0xFFFF, sum = 0
3046 11:17:39.412010 9, 0xFFFF, sum = 0
3047 11:17:39.412096 10, 0xFFFF, sum = 0
3048 11:17:39.415322 11, 0xFFFF, sum = 0
3049 11:17:39.415458 12, 0x0, sum = 1
3050 11:17:39.419007 13, 0x0, sum = 2
3051 11:17:39.419122 14, 0x0, sum = 3
3052 11:17:39.421822 15, 0x0, sum = 4
3053 11:17:39.421902 best_step = 13
3054 11:17:39.421964
3055 11:17:39.422023 ==
3056 11:17:39.425080 Dram Type= 6, Freq= 0, CH_0, rank 1
3057 11:17:39.432081 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3058 11:17:39.432166 ==
3059 11:17:39.432233 RX Vref Scan: 0
3060 11:17:39.432294
3061 11:17:39.435566 RX Vref 0 -> 0, step: 1
3062 11:17:39.435648
3063 11:17:39.438554 RX Delay -13 -> 252, step: 4
3064 11:17:39.442380 iDelay=195, Bit 0, Center 118 (51 ~ 186) 136
3065 11:17:39.445607 iDelay=195, Bit 1, Center 122 (55 ~ 190) 136
3066 11:17:39.452080 iDelay=195, Bit 2, Center 118 (51 ~ 186) 136
3067 11:17:39.455265 iDelay=195, Bit 3, Center 118 (51 ~ 186) 136
3068 11:17:39.459045 iDelay=195, Bit 4, Center 122 (55 ~ 190) 136
3069 11:17:39.462169 iDelay=195, Bit 5, Center 116 (51 ~ 182) 132
3070 11:17:39.465275 iDelay=195, Bit 6, Center 128 (63 ~ 194) 132
3071 11:17:39.468896 iDelay=195, Bit 7, Center 126 (59 ~ 194) 136
3072 11:17:39.475786 iDelay=195, Bit 8, Center 102 (35 ~ 170) 136
3073 11:17:39.478534 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3074 11:17:39.482055 iDelay=195, Bit 10, Center 112 (47 ~ 178) 132
3075 11:17:39.485400 iDelay=195, Bit 11, Center 104 (39 ~ 170) 132
3076 11:17:39.488929 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3077 11:17:39.495395 iDelay=195, Bit 13, Center 118 (55 ~ 182) 128
3078 11:17:39.498819 iDelay=195, Bit 14, Center 122 (59 ~ 186) 128
3079 11:17:39.502491 iDelay=195, Bit 15, Center 120 (59 ~ 182) 124
3080 11:17:39.502703 ==
3081 11:17:39.505320 Dram Type= 6, Freq= 0, CH_0, rank 1
3082 11:17:39.508889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3083 11:17:39.512222 ==
3084 11:17:39.512351 DQS Delay:
3085 11:17:39.512454 DQS0 = 0, DQS1 = 0
3086 11:17:39.515283 DQM Delay:
3087 11:17:39.515401 DQM0 = 121, DQM1 = 112
3088 11:17:39.518882 DQ Delay:
3089 11:17:39.521808 DQ0 =118, DQ1 =122, DQ2 =118, DQ3 =118
3090 11:17:39.525159 DQ4 =122, DQ5 =116, DQ6 =128, DQ7 =126
3091 11:17:39.528511 DQ8 =102, DQ9 =100, DQ10 =112, DQ11 =104
3092 11:17:39.532118 DQ12 =118, DQ13 =118, DQ14 =122, DQ15 =120
3093 11:17:39.532239
3094 11:17:39.532331
3095 11:17:39.539026 [DQSOSCAuto] RK1, (LSB)MR18= 0x10f1, (MSB)MR19= 0x403, tDQSOscB0 = 416 ps tDQSOscB1 = 403 ps
3096 11:17:39.542111 CH0 RK1: MR19=403, MR18=10F1
3097 11:17:39.548869 CH0_RK1: MR19=0x403, MR18=0x10F1, DQSOSC=403, MR23=63, INC=40, DEC=26
3098 11:17:39.552040 [RxdqsGatingPostProcess] freq 1200
3099 11:17:39.559074 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3100 11:17:39.562202 best DQS0 dly(2T, 0.5T) = (0, 11)
3101 11:17:39.562288 best DQS1 dly(2T, 0.5T) = (0, 12)
3102 11:17:39.565133 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3103 11:17:39.568977 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3104 11:17:39.572097 best DQS0 dly(2T, 0.5T) = (0, 11)
3105 11:17:39.575229 best DQS1 dly(2T, 0.5T) = (0, 11)
3106 11:17:39.579280 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3107 11:17:39.582431 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3108 11:17:39.585554 Pre-setting of DQS Precalculation
3109 11:17:39.592087 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3110 11:17:39.592181 ==
3111 11:17:39.595600 Dram Type= 6, Freq= 0, CH_1, rank 0
3112 11:17:39.598712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3113 11:17:39.598820 ==
3114 11:17:39.602478 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3115 11:17:39.608529 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3116 11:17:39.617879 [CA 0] Center 37 (7~68) winsize 62
3117 11:17:39.621618 [CA 1] Center 37 (7~68) winsize 62
3118 11:17:39.624714 [CA 2] Center 35 (5~65) winsize 61
3119 11:17:39.627736 [CA 3] Center 34 (4~64) winsize 61
3120 11:17:39.631212 [CA 4] Center 34 (4~64) winsize 61
3121 11:17:39.634988 [CA 5] Center 33 (3~63) winsize 61
3122 11:17:39.635078
3123 11:17:39.638074 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3124 11:17:39.638160
3125 11:17:39.641655 [CATrainingPosCal] consider 1 rank data
3126 11:17:39.644703 u2DelayCellTimex100 = 270/100 ps
3127 11:17:39.647961 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3128 11:17:39.651318 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3129 11:17:39.658051 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3130 11:17:39.661315 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3131 11:17:39.665186 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3132 11:17:39.668369 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3133 11:17:39.668457
3134 11:17:39.671343 CA PerBit enable=1, Macro0, CA PI delay=33
3135 11:17:39.671428
3136 11:17:39.674983 [CBTSetCACLKResult] CA Dly = 33
3137 11:17:39.675070 CS Dly: 7 (0~38)
3138 11:17:39.675138 ==
3139 11:17:39.678062 Dram Type= 6, Freq= 0, CH_1, rank 1
3140 11:17:39.685083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3141 11:17:39.685170 ==
3142 11:17:39.688583 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3143 11:17:39.695003 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3144 11:17:39.703665 [CA 0] Center 37 (7~68) winsize 62
3145 11:17:39.706722 [CA 1] Center 37 (7~68) winsize 62
3146 11:17:39.710355 [CA 2] Center 35 (5~65) winsize 61
3147 11:17:39.713735 [CA 3] Center 34 (4~65) winsize 62
3148 11:17:39.717242 [CA 4] Center 35 (5~65) winsize 61
3149 11:17:39.720319 [CA 5] Center 34 (4~64) winsize 61
3150 11:17:39.720407
3151 11:17:39.723755 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3152 11:17:39.723844
3153 11:17:39.727364 [CATrainingPosCal] consider 2 rank data
3154 11:17:39.730183 u2DelayCellTimex100 = 270/100 ps
3155 11:17:39.733727 CA0 delay=37 (7~68),Diff = 4 PI (19 cell)
3156 11:17:39.737093 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3157 11:17:39.743992 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3158 11:17:39.747185 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3159 11:17:39.750136 CA4 delay=34 (5~64),Diff = 1 PI (4 cell)
3160 11:17:39.753515 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3161 11:17:39.753605
3162 11:17:39.756970 CA PerBit enable=1, Macro0, CA PI delay=33
3163 11:17:39.757056
3164 11:17:39.760613 [CBTSetCACLKResult] CA Dly = 33
3165 11:17:39.760696 CS Dly: 8 (0~41)
3166 11:17:39.760810
3167 11:17:39.763523 ----->DramcWriteLeveling(PI) begin...
3168 11:17:39.767314 ==
3169 11:17:39.767438 Dram Type= 6, Freq= 0, CH_1, rank 0
3170 11:17:39.774375 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3171 11:17:39.774468 ==
3172 11:17:39.777221 Write leveling (Byte 0): 26 => 26
3173 11:17:39.780291 Write leveling (Byte 1): 27 => 27
3174 11:17:39.780378 DramcWriteLeveling(PI) end<-----
3175 11:17:39.783985
3176 11:17:39.784072 ==
3177 11:17:39.787132 Dram Type= 6, Freq= 0, CH_1, rank 0
3178 11:17:39.790830 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3179 11:17:39.790926 ==
3180 11:17:39.793820 [Gating] SW mode calibration
3181 11:17:39.800462 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3182 11:17:39.804099 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3183 11:17:39.810652 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3184 11:17:39.814071 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3185 11:17:39.817090 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3186 11:17:39.823632 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3187 11:17:39.827113 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3188 11:17:39.830298 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3189 11:17:39.837450 0 15 24 | B1->B0 | 3232 2d2d | 0 1 | (0 0) (1 0)
3190 11:17:39.840510 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
3191 11:17:39.843705 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3192 11:17:39.850886 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3193 11:17:39.853765 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3194 11:17:39.857383 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3195 11:17:39.864078 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3196 11:17:39.867090 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3197 11:17:39.870769 1 0 24 | B1->B0 | 3030 3737 | 0 0 | (1 1) (1 1)
3198 11:17:39.877516 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3199 11:17:39.880780 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3200 11:17:39.883728 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3201 11:17:39.887625 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3202 11:17:39.894097 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3203 11:17:39.897677 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3204 11:17:39.900755 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3205 11:17:39.907368 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3206 11:17:39.910504 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3207 11:17:39.914187 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 11:17:39.921172 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3209 11:17:39.924220 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 11:17:39.927360 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 11:17:39.934205 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 11:17:39.937298 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3213 11:17:39.940928 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 11:17:39.947170 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 11:17:39.950874 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 11:17:39.953959 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 11:17:39.957547 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 11:17:39.964392 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3219 11:17:39.967827 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3220 11:17:39.970691 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3221 11:17:39.977450 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3222 11:17:39.980786 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3223 11:17:39.984500 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3224 11:17:39.987308 Total UI for P1: 0, mck2ui 16
3225 11:17:39.991147 best dqsien dly found for B0: ( 1, 3, 24)
3226 11:17:39.994159 Total UI for P1: 0, mck2ui 16
3227 11:17:39.997847 best dqsien dly found for B1: ( 1, 3, 26)
3228 11:17:40.001154 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3229 11:17:40.004201 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3230 11:17:40.004282
3231 11:17:40.007873 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3232 11:17:40.014133 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3233 11:17:40.014214 [Gating] SW calibration Done
3234 11:17:40.017586 ==
3235 11:17:40.017667 Dram Type= 6, Freq= 0, CH_1, rank 0
3236 11:17:40.024148 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3237 11:17:40.024230 ==
3238 11:17:40.024294 RX Vref Scan: 0
3239 11:17:40.024353
3240 11:17:40.027277 RX Vref 0 -> 0, step: 1
3241 11:17:40.027363
3242 11:17:40.030718 RX Delay -40 -> 252, step: 8
3243 11:17:40.034235 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3244 11:17:40.037981 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3245 11:17:40.040967 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3246 11:17:40.047550 iDelay=200, Bit 3, Center 119 (48 ~ 191) 144
3247 11:17:40.051240 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3248 11:17:40.054522 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3249 11:17:40.057728 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3250 11:17:40.061308 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3251 11:17:40.064548 iDelay=200, Bit 8, Center 107 (48 ~ 167) 120
3252 11:17:40.071358 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3253 11:17:40.074388 iDelay=200, Bit 10, Center 115 (48 ~ 183) 136
3254 11:17:40.078216 iDelay=200, Bit 11, Center 111 (48 ~ 175) 128
3255 11:17:40.081214 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3256 11:17:40.084555 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3257 11:17:40.091219 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3258 11:17:40.094872 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3259 11:17:40.094946 ==
3260 11:17:40.097914 Dram Type= 6, Freq= 0, CH_1, rank 0
3261 11:17:40.101664 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3262 11:17:40.101747 ==
3263 11:17:40.104883 DQS Delay:
3264 11:17:40.104967 DQS0 = 0, DQS1 = 0
3265 11:17:40.105035 DQM Delay:
3266 11:17:40.108298 DQM0 = 119, DQM1 = 117
3267 11:17:40.108404 DQ Delay:
3268 11:17:40.111430 DQ0 =123, DQ1 =115, DQ2 =107, DQ3 =119
3269 11:17:40.114649 DQ4 =119, DQ5 =127, DQ6 =127, DQ7 =119
3270 11:17:40.118191 DQ8 =107, DQ9 =107, DQ10 =115, DQ11 =111
3271 11:17:40.124842 DQ12 =123, DQ13 =127, DQ14 =123, DQ15 =123
3272 11:17:40.124923
3273 11:17:40.124988
3274 11:17:40.125047 ==
3275 11:17:40.127961 Dram Type= 6, Freq= 0, CH_1, rank 0
3276 11:17:40.131655 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3277 11:17:40.131737 ==
3278 11:17:40.131802
3279 11:17:40.131861
3280 11:17:40.134898 TX Vref Scan disable
3281 11:17:40.135007 == TX Byte 0 ==
3282 11:17:40.141549 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3283 11:17:40.145232 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3284 11:17:40.145314 == TX Byte 1 ==
3285 11:17:40.151818 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3286 11:17:40.154964 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3287 11:17:40.155046 ==
3288 11:17:40.158424 Dram Type= 6, Freq= 0, CH_1, rank 0
3289 11:17:40.161877 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3290 11:17:40.161959 ==
3291 11:17:40.174191 TX Vref=22, minBit 10, minWin=24, winSum=407
3292 11:17:40.177055 TX Vref=24, minBit 1, minWin=25, winSum=418
3293 11:17:40.180901 TX Vref=26, minBit 9, minWin=25, winSum=423
3294 11:17:40.183857 TX Vref=28, minBit 9, minWin=25, winSum=423
3295 11:17:40.187233 TX Vref=30, minBit 9, minWin=25, winSum=429
3296 11:17:40.190886 TX Vref=32, minBit 9, minWin=25, winSum=427
3297 11:17:40.197164 [TxChooseVref] Worse bit 9, Min win 25, Win sum 429, Final Vref 30
3298 11:17:40.197246
3299 11:17:40.200676 Final TX Range 1 Vref 30
3300 11:17:40.200797
3301 11:17:40.200861 ==
3302 11:17:40.203886 Dram Type= 6, Freq= 0, CH_1, rank 0
3303 11:17:40.207625 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3304 11:17:40.207707 ==
3305 11:17:40.207772
3306 11:17:40.210592
3307 11:17:40.210673 TX Vref Scan disable
3308 11:17:40.213723 == TX Byte 0 ==
3309 11:17:40.217446 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3310 11:17:40.220457 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3311 11:17:40.224100 == TX Byte 1 ==
3312 11:17:40.227089 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3313 11:17:40.230901 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3314 11:17:40.230983
3315 11:17:40.233848 [DATLAT]
3316 11:17:40.233929 Freq=1200, CH1 RK0
3317 11:17:40.233993
3318 11:17:40.237099 DATLAT Default: 0xd
3319 11:17:40.237181 0, 0xFFFF, sum = 0
3320 11:17:40.240277 1, 0xFFFF, sum = 0
3321 11:17:40.240360 2, 0xFFFF, sum = 0
3322 11:17:40.243917 3, 0xFFFF, sum = 0
3323 11:17:40.244000 4, 0xFFFF, sum = 0
3324 11:17:40.247055 5, 0xFFFF, sum = 0
3325 11:17:40.247137 6, 0xFFFF, sum = 0
3326 11:17:40.250453 7, 0xFFFF, sum = 0
3327 11:17:40.250535 8, 0xFFFF, sum = 0
3328 11:17:40.253695 9, 0xFFFF, sum = 0
3329 11:17:40.257327 10, 0xFFFF, sum = 0
3330 11:17:40.257409 11, 0xFFFF, sum = 0
3331 11:17:40.260247 12, 0x0, sum = 1
3332 11:17:40.260330 13, 0x0, sum = 2
3333 11:17:40.260396 14, 0x0, sum = 3
3334 11:17:40.264005 15, 0x0, sum = 4
3335 11:17:40.264087 best_step = 13
3336 11:17:40.264152
3337 11:17:40.267129 ==
3338 11:17:40.267211 Dram Type= 6, Freq= 0, CH_1, rank 0
3339 11:17:40.274314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3340 11:17:40.274396 ==
3341 11:17:40.274460 RX Vref Scan: 1
3342 11:17:40.274520
3343 11:17:40.277557 Set Vref Range= 32 -> 127
3344 11:17:40.277638
3345 11:17:40.280641 RX Vref 32 -> 127, step: 1
3346 11:17:40.280722
3347 11:17:40.284030 RX Delay -5 -> 252, step: 4
3348 11:17:40.284112
3349 11:17:40.287364 Set Vref, RX VrefLevel [Byte0]: 32
3350 11:17:40.291009 [Byte1]: 32
3351 11:17:40.291090
3352 11:17:40.294365 Set Vref, RX VrefLevel [Byte0]: 33
3353 11:17:40.297221 [Byte1]: 33
3354 11:17:40.297302
3355 11:17:40.300683 Set Vref, RX VrefLevel [Byte0]: 34
3356 11:17:40.304116 [Byte1]: 34
3357 11:17:40.307568
3358 11:17:40.307662 Set Vref, RX VrefLevel [Byte0]: 35
3359 11:17:40.311185 [Byte1]: 35
3360 11:17:40.315513
3361 11:17:40.315592 Set Vref, RX VrefLevel [Byte0]: 36
3362 11:17:40.318729 [Byte1]: 36
3363 11:17:40.323315
3364 11:17:40.323432 Set Vref, RX VrefLevel [Byte0]: 37
3365 11:17:40.327091 [Byte1]: 37
3366 11:17:40.331149
3367 11:17:40.331228 Set Vref, RX VrefLevel [Byte0]: 38
3368 11:17:40.334743 [Byte1]: 38
3369 11:17:40.339128
3370 11:17:40.339207 Set Vref, RX VrefLevel [Byte0]: 39
3371 11:17:40.342870 [Byte1]: 39
3372 11:17:40.346670
3373 11:17:40.346756 Set Vref, RX VrefLevel [Byte0]: 40
3374 11:17:40.350200 [Byte1]: 40
3375 11:17:40.355213
3376 11:17:40.355294 Set Vref, RX VrefLevel [Byte0]: 41
3377 11:17:40.357904 [Byte1]: 41
3378 11:17:40.362417
3379 11:17:40.362495 Set Vref, RX VrefLevel [Byte0]: 42
3380 11:17:40.366220 [Byte1]: 42
3381 11:17:40.370396
3382 11:17:40.370474 Set Vref, RX VrefLevel [Byte0]: 43
3383 11:17:40.374091 [Byte1]: 43
3384 11:17:40.378274
3385 11:17:40.378367 Set Vref, RX VrefLevel [Byte0]: 44
3386 11:17:40.381967 [Byte1]: 44
3387 11:17:40.386270
3388 11:17:40.386348 Set Vref, RX VrefLevel [Byte0]: 45
3389 11:17:40.389863 [Byte1]: 45
3390 11:17:40.394237
3391 11:17:40.394315 Set Vref, RX VrefLevel [Byte0]: 46
3392 11:17:40.397460 [Byte1]: 46
3393 11:17:40.402149
3394 11:17:40.402227 Set Vref, RX VrefLevel [Byte0]: 47
3395 11:17:40.405007 [Byte1]: 47
3396 11:17:40.409748
3397 11:17:40.409826 Set Vref, RX VrefLevel [Byte0]: 48
3398 11:17:40.412929 [Byte1]: 48
3399 11:17:40.417901
3400 11:17:40.417980 Set Vref, RX VrefLevel [Byte0]: 49
3401 11:17:40.420838 [Byte1]: 49
3402 11:17:40.425551
3403 11:17:40.425630 Set Vref, RX VrefLevel [Byte0]: 50
3404 11:17:40.428684 [Byte1]: 50
3405 11:17:40.433176
3406 11:17:40.433254 Set Vref, RX VrefLevel [Byte0]: 51
3407 11:17:40.436879 [Byte1]: 51
3408 11:17:40.441202
3409 11:17:40.441281 Set Vref, RX VrefLevel [Byte0]: 52
3410 11:17:40.444387 [Byte1]: 52
3411 11:17:40.449273
3412 11:17:40.449361 Set Vref, RX VrefLevel [Byte0]: 53
3413 11:17:40.452223 [Byte1]: 53
3414 11:17:40.457150
3415 11:17:40.457237 Set Vref, RX VrefLevel [Byte0]: 54
3416 11:17:40.460187 [Byte1]: 54
3417 11:17:40.464787
3418 11:17:40.464885 Set Vref, RX VrefLevel [Byte0]: 55
3419 11:17:40.468281 [Byte1]: 55
3420 11:17:40.472896
3421 11:17:40.472975 Set Vref, RX VrefLevel [Byte0]: 56
3422 11:17:40.475826 [Byte1]: 56
3423 11:17:40.480859
3424 11:17:40.480939 Set Vref, RX VrefLevel [Byte0]: 57
3425 11:17:40.484005 [Byte1]: 57
3426 11:17:40.488211
3427 11:17:40.488291 Set Vref, RX VrefLevel [Byte0]: 58
3428 11:17:40.491455 [Byte1]: 58
3429 11:17:40.495927
3430 11:17:40.496008 Set Vref, RX VrefLevel [Byte0]: 59
3431 11:17:40.499234 [Byte1]: 59
3432 11:17:40.503985
3433 11:17:40.504066 Set Vref, RX VrefLevel [Byte0]: 60
3434 11:17:40.507666 [Byte1]: 60
3435 11:17:40.512042
3436 11:17:40.512122 Set Vref, RX VrefLevel [Byte0]: 61
3437 11:17:40.515220 [Byte1]: 61
3438 11:17:40.519613
3439 11:17:40.519693 Set Vref, RX VrefLevel [Byte0]: 62
3440 11:17:40.522924 [Byte1]: 62
3441 11:17:40.527287
3442 11:17:40.527384 Set Vref, RX VrefLevel [Byte0]: 63
3443 11:17:40.530878 [Byte1]: 63
3444 11:17:40.535363
3445 11:17:40.535458 Set Vref, RX VrefLevel [Byte0]: 64
3446 11:17:40.538611 [Byte1]: 64
3447 11:17:40.543301
3448 11:17:40.543392 Set Vref, RX VrefLevel [Byte0]: 65
3449 11:17:40.546685 [Byte1]: 65
3450 11:17:40.551535
3451 11:17:40.551616 Set Vref, RX VrefLevel [Byte0]: 66
3452 11:17:40.554523 [Byte1]: 66
3453 11:17:40.558900
3454 11:17:40.558981 Set Vref, RX VrefLevel [Byte0]: 67
3455 11:17:40.562676 [Byte1]: 67
3456 11:17:40.567056
3457 11:17:40.567136 Set Vref, RX VrefLevel [Byte0]: 68
3458 11:17:40.570016 [Byte1]: 68
3459 11:17:40.574987
3460 11:17:40.575068 Set Vref, RX VrefLevel [Byte0]: 69
3461 11:17:40.577870 [Byte1]: 69
3462 11:17:40.582600
3463 11:17:40.582682 Set Vref, RX VrefLevel [Byte0]: 70
3464 11:17:40.585825 [Byte1]: 70
3465 11:17:40.590425
3466 11:17:40.590507 Set Vref, RX VrefLevel [Byte0]: 71
3467 11:17:40.593486 [Byte1]: 71
3468 11:17:40.598479
3469 11:17:40.598560 Final RX Vref Byte 0 = 51 to rank0
3470 11:17:40.601383 Final RX Vref Byte 1 = 53 to rank0
3471 11:17:40.605536 Final RX Vref Byte 0 = 51 to rank1
3472 11:17:40.608288 Final RX Vref Byte 1 = 53 to rank1==
3473 11:17:40.611774 Dram Type= 6, Freq= 0, CH_1, rank 0
3474 11:17:40.618355 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3475 11:17:40.618438 ==
3476 11:17:40.618503 DQS Delay:
3477 11:17:40.618563 DQS0 = 0, DQS1 = 0
3478 11:17:40.621276 DQM Delay:
3479 11:17:40.621358 DQM0 = 119, DQM1 = 117
3480 11:17:40.624527 DQ Delay:
3481 11:17:40.628103 DQ0 =122, DQ1 =114, DQ2 =110, DQ3 =114
3482 11:17:40.631847 DQ4 =118, DQ5 =130, DQ6 =130, DQ7 =120
3483 11:17:40.634844 DQ8 =104, DQ9 =106, DQ10 =118, DQ11 =112
3484 11:17:40.638393 DQ12 =124, DQ13 =124, DQ14 =124, DQ15 =126
3485 11:17:40.638474
3486 11:17:40.638538
3487 11:17:40.644789 [DQSOSCAuto] RK0, (LSB)MR18= 0x113, (MSB)MR19= 0x404, tDQSOscB0 = 402 ps tDQSOscB1 = 409 ps
3488 11:17:40.648513 CH1 RK0: MR19=404, MR18=113
3489 11:17:40.654743 CH1_RK0: MR19=0x404, MR18=0x113, DQSOSC=402, MR23=63, INC=40, DEC=27
3490 11:17:40.654824
3491 11:17:40.658476 ----->DramcWriteLeveling(PI) begin...
3492 11:17:40.658577 ==
3493 11:17:40.661563 Dram Type= 6, Freq= 0, CH_1, rank 1
3494 11:17:40.664675 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3495 11:17:40.664756 ==
3496 11:17:40.668244 Write leveling (Byte 0): 26 => 26
3497 11:17:40.671297 Write leveling (Byte 1): 29 => 29
3498 11:17:40.674633 DramcWriteLeveling(PI) end<-----
3499 11:17:40.674714
3500 11:17:40.674777 ==
3501 11:17:40.678126 Dram Type= 6, Freq= 0, CH_1, rank 1
3502 11:17:40.684683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3503 11:17:40.684764 ==
3504 11:17:40.684828 [Gating] SW mode calibration
3505 11:17:40.695320 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3506 11:17:40.698076 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3507 11:17:40.701865 0 15 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
3508 11:17:40.708469 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3509 11:17:40.711842 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3510 11:17:40.715376 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3511 11:17:40.721906 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3512 11:17:40.724710 0 15 20 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 1)
3513 11:17:40.728648 0 15 24 | B1->B0 | 2929 3333 | 0 1 | (1 0) (1 0)
3514 11:17:40.734926 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3515 11:17:40.738490 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3516 11:17:40.741575 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3517 11:17:40.748530 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3518 11:17:40.751681 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3519 11:17:40.754860 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3520 11:17:40.761681 1 0 20 | B1->B0 | 2929 2323 | 0 0 | (0 0) (0 0)
3521 11:17:40.764670 1 0 24 | B1->B0 | 3e3e 2727 | 0 0 | (0 0) (0 0)
3522 11:17:40.768421 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3523 11:17:40.771492 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3524 11:17:40.777940 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3525 11:17:40.781733 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3526 11:17:40.784785 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3527 11:17:40.791565 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3528 11:17:40.794448 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3529 11:17:40.798146 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
3530 11:17:40.804802 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3531 11:17:40.808294 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3532 11:17:40.811004 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3533 11:17:40.818162 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3534 11:17:40.821365 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3535 11:17:40.824799 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3536 11:17:40.831174 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3537 11:17:40.834766 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3538 11:17:40.837777 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3539 11:17:40.844652 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3540 11:17:40.848143 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3541 11:17:40.851152 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3542 11:17:40.857973 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3543 11:17:40.861097 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3544 11:17:40.864234 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
3545 11:17:40.871206 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3546 11:17:40.874925 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
3547 11:17:40.878000 Total UI for P1: 0, mck2ui 16
3548 11:17:40.881192 best dqsien dly found for B1: ( 1, 3, 22)
3549 11:17:40.884374 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3550 11:17:40.888246 Total UI for P1: 0, mck2ui 16
3551 11:17:40.891288 best dqsien dly found for B0: ( 1, 3, 26)
3552 11:17:40.894272 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3553 11:17:40.898017 best DQS1 dly(MCK, UI, PI) = (1, 3, 22)
3554 11:17:40.898111
3555 11:17:40.901102 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3556 11:17:40.907636 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 22)
3557 11:17:40.907718 [Gating] SW calibration Done
3558 11:17:40.911213 ==
3559 11:17:40.911308 Dram Type= 6, Freq= 0, CH_1, rank 1
3560 11:17:40.917433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3561 11:17:40.917516 ==
3562 11:17:40.917583 RX Vref Scan: 0
3563 11:17:40.917642
3564 11:17:40.921237 RX Vref 0 -> 0, step: 1
3565 11:17:40.921306
3566 11:17:40.924525 RX Delay -40 -> 252, step: 8
3567 11:17:40.927998 iDelay=200, Bit 0, Center 123 (56 ~ 191) 136
3568 11:17:40.931072 iDelay=200, Bit 1, Center 115 (48 ~ 183) 136
3569 11:17:40.933931 iDelay=200, Bit 2, Center 111 (48 ~ 175) 128
3570 11:17:40.940437 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3571 11:17:40.944195 iDelay=200, Bit 4, Center 119 (56 ~ 183) 128
3572 11:17:40.947226 iDelay=200, Bit 5, Center 131 (64 ~ 199) 136
3573 11:17:40.950764 iDelay=200, Bit 6, Center 131 (64 ~ 199) 136
3574 11:17:40.954218 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3575 11:17:40.960566 iDelay=200, Bit 8, Center 103 (40 ~ 167) 128
3576 11:17:40.963835 iDelay=200, Bit 9, Center 107 (40 ~ 175) 136
3577 11:17:40.967597 iDelay=200, Bit 10, Center 119 (48 ~ 191) 144
3578 11:17:40.970540 iDelay=200, Bit 11, Center 115 (48 ~ 183) 136
3579 11:17:40.976926 iDelay=200, Bit 12, Center 127 (56 ~ 199) 144
3580 11:17:40.980093 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
3581 11:17:40.983613 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
3582 11:17:40.986747 iDelay=200, Bit 15, Center 123 (56 ~ 191) 136
3583 11:17:40.986821 ==
3584 11:17:40.990534 Dram Type= 6, Freq= 0, CH_1, rank 1
3585 11:17:40.996632 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3586 11:17:40.996709 ==
3587 11:17:40.996773 DQS Delay:
3588 11:17:40.996831 DQS0 = 0, DQS1 = 0
3589 11:17:41.000218 DQM Delay:
3590 11:17:41.000292 DQM0 = 120, DQM1 = 118
3591 11:17:41.003259 DQ Delay:
3592 11:17:41.007200 DQ0 =123, DQ1 =115, DQ2 =111, DQ3 =115
3593 11:17:41.010029 DQ4 =119, DQ5 =131, DQ6 =131, DQ7 =119
3594 11:17:41.013867 DQ8 =103, DQ9 =107, DQ10 =119, DQ11 =115
3595 11:17:41.016879 DQ12 =127, DQ13 =127, DQ14 =123, DQ15 =123
3596 11:17:41.016953
3597 11:17:41.017060
3598 11:17:41.017148 ==
3599 11:17:41.020004 Dram Type= 6, Freq= 0, CH_1, rank 1
3600 11:17:41.023475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3601 11:17:41.026682 ==
3602 11:17:41.026795
3603 11:17:41.026893
3604 11:17:41.026998 TX Vref Scan disable
3605 11:17:41.029810 == TX Byte 0 ==
3606 11:17:41.033401 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3607 11:17:41.036845 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3608 11:17:41.039738 == TX Byte 1 ==
3609 11:17:41.043272 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3610 11:17:41.046395 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3611 11:17:41.046494 ==
3612 11:17:41.049797 Dram Type= 6, Freq= 0, CH_1, rank 1
3613 11:17:41.056793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3614 11:17:41.056897 ==
3615 11:17:41.067639 TX Vref=22, minBit 9, minWin=25, winSum=420
3616 11:17:41.070602 TX Vref=24, minBit 9, minWin=25, winSum=423
3617 11:17:41.073685 TX Vref=26, minBit 9, minWin=26, winSum=430
3618 11:17:41.077408 TX Vref=28, minBit 9, minWin=26, winSum=433
3619 11:17:41.080198 TX Vref=30, minBit 9, minWin=26, winSum=434
3620 11:17:41.087219 TX Vref=32, minBit 9, minWin=26, winSum=436
3621 11:17:41.090318 [TxChooseVref] Worse bit 9, Min win 26, Win sum 436, Final Vref 32
3622 11:17:41.090394
3623 11:17:41.093513 Final TX Range 1 Vref 32
3624 11:17:41.093596
3625 11:17:41.093661 ==
3626 11:17:41.097115 Dram Type= 6, Freq= 0, CH_1, rank 1
3627 11:17:41.100278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3628 11:17:41.103800 ==
3629 11:17:41.103878
3630 11:17:41.103943
3631 11:17:41.104003 TX Vref Scan disable
3632 11:17:41.106957 == TX Byte 0 ==
3633 11:17:41.110082 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3634 11:17:41.116761 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3635 11:17:41.116843 == TX Byte 1 ==
3636 11:17:41.119983 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3637 11:17:41.127259 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3638 11:17:41.127366
3639 11:17:41.127480 [DATLAT]
3640 11:17:41.127543 Freq=1200, CH1 RK1
3641 11:17:41.127609
3642 11:17:41.130413 DATLAT Default: 0xd
3643 11:17:41.130483 0, 0xFFFF, sum = 0
3644 11:17:41.133453 1, 0xFFFF, sum = 0
3645 11:17:41.136893 2, 0xFFFF, sum = 0
3646 11:17:41.136964 3, 0xFFFF, sum = 0
3647 11:17:41.140085 4, 0xFFFF, sum = 0
3648 11:17:41.140166 5, 0xFFFF, sum = 0
3649 11:17:41.143472 6, 0xFFFF, sum = 0
3650 11:17:41.143546 7, 0xFFFF, sum = 0
3651 11:17:41.147182 8, 0xFFFF, sum = 0
3652 11:17:41.147286 9, 0xFFFF, sum = 0
3653 11:17:41.150456 10, 0xFFFF, sum = 0
3654 11:17:41.150554 11, 0xFFFF, sum = 0
3655 11:17:41.153263 12, 0x0, sum = 1
3656 11:17:41.153335 13, 0x0, sum = 2
3657 11:17:41.156774 14, 0x0, sum = 3
3658 11:17:41.156850 15, 0x0, sum = 4
3659 11:17:41.160201 best_step = 13
3660 11:17:41.160284
3661 11:17:41.160345 ==
3662 11:17:41.163211 Dram Type= 6, Freq= 0, CH_1, rank 1
3663 11:17:41.166604 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3664 11:17:41.166683 ==
3665 11:17:41.166745 RX Vref Scan: 0
3666 11:17:41.166803
3667 11:17:41.170133 RX Vref 0 -> 0, step: 1
3668 11:17:41.170204
3669 11:17:41.173590 RX Delay -5 -> 252, step: 4
3670 11:17:41.176356 iDelay=195, Bit 0, Center 122 (59 ~ 186) 128
3671 11:17:41.183178 iDelay=195, Bit 1, Center 116 (55 ~ 178) 124
3672 11:17:41.186751 iDelay=195, Bit 2, Center 110 (51 ~ 170) 120
3673 11:17:41.190105 iDelay=195, Bit 3, Center 116 (55 ~ 178) 124
3674 11:17:41.193235 iDelay=195, Bit 4, Center 116 (55 ~ 178) 124
3675 11:17:41.196881 iDelay=195, Bit 5, Center 130 (67 ~ 194) 128
3676 11:17:41.203174 iDelay=195, Bit 6, Center 130 (67 ~ 194) 128
3677 11:17:41.206304 iDelay=195, Bit 7, Center 118 (59 ~ 178) 120
3678 11:17:41.209824 iDelay=195, Bit 8, Center 106 (47 ~ 166) 120
3679 11:17:41.213037 iDelay=195, Bit 9, Center 108 (47 ~ 170) 124
3680 11:17:41.216773 iDelay=195, Bit 10, Center 116 (55 ~ 178) 124
3681 11:17:41.223476 iDelay=195, Bit 11, Center 112 (51 ~ 174) 124
3682 11:17:41.226390 iDelay=195, Bit 12, Center 126 (63 ~ 190) 128
3683 11:17:41.229775 iDelay=195, Bit 13, Center 124 (67 ~ 182) 116
3684 11:17:41.233409 iDelay=195, Bit 14, Center 124 (67 ~ 182) 116
3685 11:17:41.239576 iDelay=195, Bit 15, Center 128 (67 ~ 190) 124
3686 11:17:41.239657 ==
3687 11:17:41.242754 Dram Type= 6, Freq= 0, CH_1, rank 1
3688 11:17:41.246059 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3689 11:17:41.246131 ==
3690 11:17:41.246199 DQS Delay:
3691 11:17:41.249406 DQS0 = 0, DQS1 = 0
3692 11:17:41.249482 DQM Delay:
3693 11:17:41.252814 DQM0 = 119, DQM1 = 118
3694 11:17:41.252889 DQ Delay:
3695 11:17:41.256374 DQ0 =122, DQ1 =116, DQ2 =110, DQ3 =116
3696 11:17:41.259260 DQ4 =116, DQ5 =130, DQ6 =130, DQ7 =118
3697 11:17:41.262584 DQ8 =106, DQ9 =108, DQ10 =116, DQ11 =112
3698 11:17:41.266026 DQ12 =126, DQ13 =124, DQ14 =124, DQ15 =128
3699 11:17:41.266103
3700 11:17:41.266166
3701 11:17:41.276342 [DQSOSCAuto] RK1, (LSB)MR18= 0xfec, (MSB)MR19= 0x403, tDQSOscB0 = 418 ps tDQSOscB1 = 404 ps
3702 11:17:41.279219 CH1 RK1: MR19=403, MR18=FEC
3703 11:17:41.282627 CH1_RK1: MR19=0x403, MR18=0xFEC, DQSOSC=404, MR23=63, INC=40, DEC=26
3704 11:17:41.286073 [RxdqsGatingPostProcess] freq 1200
3705 11:17:41.292514 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3706 11:17:41.296227 best DQS0 dly(2T, 0.5T) = (0, 11)
3707 11:17:41.299230 best DQS1 dly(2T, 0.5T) = (0, 11)
3708 11:17:41.302310 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3709 11:17:41.306231 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3710 11:17:41.309452 best DQS0 dly(2T, 0.5T) = (0, 11)
3711 11:17:41.312987 best DQS1 dly(2T, 0.5T) = (0, 11)
3712 11:17:41.316084 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3713 11:17:41.318976 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3714 11:17:41.322344 Pre-setting of DQS Precalculation
3715 11:17:41.326001 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3716 11:17:41.332530 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3717 11:17:41.339619 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3718 11:17:41.339699
3719 11:17:41.339762
3720 11:17:41.342432 [Calibration Summary] 2400 Mbps
3721 11:17:41.346401 CH 0, Rank 0
3722 11:17:41.346479 SW Impedance : PASS
3723 11:17:41.349472 DUTY Scan : NO K
3724 11:17:41.352521 ZQ Calibration : PASS
3725 11:17:41.352593 Jitter Meter : NO K
3726 11:17:41.356278 CBT Training : PASS
3727 11:17:41.359192 Write leveling : PASS
3728 11:17:41.359292 RX DQS gating : PASS
3729 11:17:41.362616 RX DQ/DQS(RDDQC) : PASS
3730 11:17:41.365645 TX DQ/DQS : PASS
3731 11:17:41.365725 RX DATLAT : PASS
3732 11:17:41.368938 RX DQ/DQS(Engine): PASS
3733 11:17:41.372170 TX OE : NO K
3734 11:17:41.372252 All Pass.
3735 11:17:41.372318
3736 11:17:41.372377 CH 0, Rank 1
3737 11:17:41.375534 SW Impedance : PASS
3738 11:17:41.378716 DUTY Scan : NO K
3739 11:17:41.378799 ZQ Calibration : PASS
3740 11:17:41.382260 Jitter Meter : NO K
3741 11:17:41.382339 CBT Training : PASS
3742 11:17:41.385749 Write leveling : PASS
3743 11:17:41.389010 RX DQS gating : PASS
3744 11:17:41.389090 RX DQ/DQS(RDDQC) : PASS
3745 11:17:41.392385 TX DQ/DQS : PASS
3746 11:17:41.395797 RX DATLAT : PASS
3747 11:17:41.395877 RX DQ/DQS(Engine): PASS
3748 11:17:41.398825 TX OE : NO K
3749 11:17:41.398896 All Pass.
3750 11:17:41.398956
3751 11:17:41.401896 CH 1, Rank 0
3752 11:17:41.401969 SW Impedance : PASS
3753 11:17:41.405615 DUTY Scan : NO K
3754 11:17:41.408757 ZQ Calibration : PASS
3755 11:17:41.408834 Jitter Meter : NO K
3756 11:17:41.412490 CBT Training : PASS
3757 11:17:41.415524 Write leveling : PASS
3758 11:17:41.415603 RX DQS gating : PASS
3759 11:17:41.418627 RX DQ/DQS(RDDQC) : PASS
3760 11:17:41.422196 TX DQ/DQS : PASS
3761 11:17:41.422268 RX DATLAT : PASS
3762 11:17:41.425314 RX DQ/DQS(Engine): PASS
3763 11:17:41.425385 TX OE : NO K
3764 11:17:41.429009 All Pass.
3765 11:17:41.429079
3766 11:17:41.429139 CH 1, Rank 1
3767 11:17:41.432210 SW Impedance : PASS
3768 11:17:41.432280 DUTY Scan : NO K
3769 11:17:41.435754 ZQ Calibration : PASS
3770 11:17:41.438942 Jitter Meter : NO K
3771 11:17:41.439016 CBT Training : PASS
3772 11:17:41.441895 Write leveling : PASS
3773 11:17:41.445251 RX DQS gating : PASS
3774 11:17:41.445323 RX DQ/DQS(RDDQC) : PASS
3775 11:17:41.448780 TX DQ/DQS : PASS
3776 11:17:41.452067 RX DATLAT : PASS
3777 11:17:41.452139 RX DQ/DQS(Engine): PASS
3778 11:17:41.455625 TX OE : NO K
3779 11:17:41.455704 All Pass.
3780 11:17:41.455767
3781 11:17:41.458722 DramC Write-DBI off
3782 11:17:41.461963 PER_BANK_REFRESH: Hybrid Mode
3783 11:17:41.462037 TX_TRACKING: ON
3784 11:17:41.471828 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3785 11:17:41.475306 [FAST_K] Save calibration result to emmc
3786 11:17:41.478811 dramc_set_vcore_voltage set vcore to 650000
3787 11:17:41.481881 Read voltage for 600, 5
3788 11:17:41.481992 Vio18 = 0
3789 11:17:41.482086 Vcore = 650000
3790 11:17:41.485351 Vdram = 0
3791 11:17:41.485457 Vddq = 0
3792 11:17:41.485551 Vmddr = 0
3793 11:17:41.491946 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3794 11:17:41.494928 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3795 11:17:41.498296 MEM_TYPE=3, freq_sel=19
3796 11:17:41.501810 sv_algorithm_assistance_LP4_1600
3797 11:17:41.505189 ============ PULL DRAM RESETB DOWN ============
3798 11:17:41.508016 ========== PULL DRAM RESETB DOWN end =========
3799 11:17:41.515069 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3800 11:17:41.518331 ===================================
3801 11:17:41.521922 LPDDR4 DRAM CONFIGURATION
3802 11:17:41.524968 ===================================
3803 11:17:41.525045 EX_ROW_EN[0] = 0x0
3804 11:17:41.528197 EX_ROW_EN[1] = 0x0
3805 11:17:41.528282 LP4Y_EN = 0x0
3806 11:17:41.531467 WORK_FSP = 0x0
3807 11:17:41.531548 WL = 0x2
3808 11:17:41.534587 RL = 0x2
3809 11:17:41.534657 BL = 0x2
3810 11:17:41.538398 RPST = 0x0
3811 11:17:41.538497 RD_PRE = 0x0
3812 11:17:41.541391 WR_PRE = 0x1
3813 11:17:41.541473 WR_PST = 0x0
3814 11:17:41.544765 DBI_WR = 0x0
3815 11:17:41.544846 DBI_RD = 0x0
3816 11:17:41.548387 OTF = 0x1
3817 11:17:41.551540 ===================================
3818 11:17:41.554587 ===================================
3819 11:17:41.554684 ANA top config
3820 11:17:41.558286 ===================================
3821 11:17:41.561560 DLL_ASYNC_EN = 0
3822 11:17:41.564939 ALL_SLAVE_EN = 1
3823 11:17:41.567929 NEW_RANK_MODE = 1
3824 11:17:41.568005 DLL_IDLE_MODE = 1
3825 11:17:41.571271 LP45_APHY_COMB_EN = 1
3826 11:17:41.575040 TX_ODT_DIS = 1
3827 11:17:41.577943 NEW_8X_MODE = 1
3828 11:17:41.580973 ===================================
3829 11:17:41.584486 ===================================
3830 11:17:41.587996 data_rate = 1200
3831 11:17:41.591585 CKR = 1
3832 11:17:41.591688 DQ_P2S_RATIO = 8
3833 11:17:41.594468 ===================================
3834 11:17:41.597927 CA_P2S_RATIO = 8
3835 11:17:41.601095 DQ_CA_OPEN = 0
3836 11:17:41.604320 DQ_SEMI_OPEN = 0
3837 11:17:41.607764 CA_SEMI_OPEN = 0
3838 11:17:41.607849 CA_FULL_RATE = 0
3839 11:17:41.610838 DQ_CKDIV4_EN = 1
3840 11:17:41.614145 CA_CKDIV4_EN = 1
3841 11:17:41.617490 CA_PREDIV_EN = 0
3842 11:17:41.621336 PH8_DLY = 0
3843 11:17:41.624353 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3844 11:17:41.624465 DQ_AAMCK_DIV = 4
3845 11:17:41.627408 CA_AAMCK_DIV = 4
3846 11:17:41.631467 CA_ADMCK_DIV = 4
3847 11:17:41.633985 DQ_TRACK_CA_EN = 0
3848 11:17:41.637748 CA_PICK = 600
3849 11:17:41.640748 CA_MCKIO = 600
3850 11:17:41.644409 MCKIO_SEMI = 0
3851 11:17:41.647567 PLL_FREQ = 2288
3852 11:17:41.647643 DQ_UI_PI_RATIO = 32
3853 11:17:41.651223 CA_UI_PI_RATIO = 0
3854 11:17:41.654156 ===================================
3855 11:17:41.657499 ===================================
3856 11:17:41.660396 memory_type:LPDDR4
3857 11:17:41.664276 GP_NUM : 10
3858 11:17:41.664378 SRAM_EN : 1
3859 11:17:41.667307 MD32_EN : 0
3860 11:17:41.670457 ===================================
3861 11:17:41.670560 [ANA_INIT] >>>>>>>>>>>>>>
3862 11:17:41.673819 <<<<<< [CONFIGURE PHASE]: ANA_TX
3863 11:17:41.677512 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3864 11:17:41.680648 ===================================
3865 11:17:41.683758 data_rate = 1200,PCW = 0X5800
3866 11:17:41.687508 ===================================
3867 11:17:41.690455 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3868 11:17:41.697622 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3869 11:17:41.700409 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3870 11:17:41.707484 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3871 11:17:41.710521 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3872 11:17:41.714130 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3873 11:17:41.717149 [ANA_INIT] flow start
3874 11:17:41.717260 [ANA_INIT] PLL >>>>>>>>
3875 11:17:41.721015 [ANA_INIT] PLL <<<<<<<<
3876 11:17:41.724134 [ANA_INIT] MIDPI >>>>>>>>
3877 11:17:41.724213 [ANA_INIT] MIDPI <<<<<<<<
3878 11:17:41.727305 [ANA_INIT] DLL >>>>>>>>
3879 11:17:41.731011 [ANA_INIT] flow end
3880 11:17:41.734313 ============ LP4 DIFF to SE enter ============
3881 11:17:41.737527 ============ LP4 DIFF to SE exit ============
3882 11:17:41.740705 [ANA_INIT] <<<<<<<<<<<<<
3883 11:17:41.743914 [Flow] Enable top DCM control >>>>>
3884 11:17:41.747089 [Flow] Enable top DCM control <<<<<
3885 11:17:41.750787 Enable DLL master slave shuffle
3886 11:17:41.753938 ==============================================================
3887 11:17:41.757149 Gating Mode config
3888 11:17:41.764134 ==============================================================
3889 11:17:41.764233 Config description:
3890 11:17:41.773782 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3891 11:17:41.780303 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3892 11:17:41.784093 SELPH_MODE 0: By rank 1: By Phase
3893 11:17:41.790212 ==============================================================
3894 11:17:41.793720 GAT_TRACK_EN = 1
3895 11:17:41.796845 RX_GATING_MODE = 2
3896 11:17:41.800318 RX_GATING_TRACK_MODE = 2
3897 11:17:41.803262 SELPH_MODE = 1
3898 11:17:41.807132 PICG_EARLY_EN = 1
3899 11:17:41.810231 VALID_LAT_VALUE = 1
3900 11:17:41.813523 ==============================================================
3901 11:17:41.817135 Enter into Gating configuration >>>>
3902 11:17:41.820247 Exit from Gating configuration <<<<
3903 11:17:41.823766 Enter into DVFS_PRE_config >>>>>
3904 11:17:41.833622 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3905 11:17:41.836942 Exit from DVFS_PRE_config <<<<<
3906 11:17:41.840205 Enter into PICG configuration >>>>
3907 11:17:41.843345 Exit from PICG configuration <<<<
3908 11:17:41.847180 [RX_INPUT] configuration >>>>>
3909 11:17:41.849985 [RX_INPUT] configuration <<<<<
3910 11:17:41.857139 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3911 11:17:41.860413 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3912 11:17:41.867171 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3913 11:17:41.873568 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3914 11:17:41.880254 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3915 11:17:41.886664 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3916 11:17:41.890700 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3917 11:17:41.893916 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3918 11:17:41.896945 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3919 11:17:41.903724 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3920 11:17:41.906355 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3921 11:17:41.910215 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3922 11:17:41.913611 ===================================
3923 11:17:41.916602 LPDDR4 DRAM CONFIGURATION
3924 11:17:41.920186 ===================================
3925 11:17:41.920302 EX_ROW_EN[0] = 0x0
3926 11:17:41.923184 EX_ROW_EN[1] = 0x0
3927 11:17:41.923266 LP4Y_EN = 0x0
3928 11:17:41.926773 WORK_FSP = 0x0
3929 11:17:41.929536 WL = 0x2
3930 11:17:41.929619 RL = 0x2
3931 11:17:41.932916 BL = 0x2
3932 11:17:41.933000 RPST = 0x0
3933 11:17:41.936474 RD_PRE = 0x0
3934 11:17:41.936590 WR_PRE = 0x1
3935 11:17:41.939674 WR_PST = 0x0
3936 11:17:41.939758 DBI_WR = 0x0
3937 11:17:41.943374 DBI_RD = 0x0
3938 11:17:41.943458 OTF = 0x1
3939 11:17:41.946740 ===================================
3940 11:17:41.949465 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3941 11:17:41.956343 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3942 11:17:41.959590 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3943 11:17:41.962826 ===================================
3944 11:17:41.966501 LPDDR4 DRAM CONFIGURATION
3945 11:17:41.969422 ===================================
3946 11:17:41.969506 EX_ROW_EN[0] = 0x10
3947 11:17:41.973225 EX_ROW_EN[1] = 0x0
3948 11:17:41.973323 LP4Y_EN = 0x0
3949 11:17:41.976261 WORK_FSP = 0x0
3950 11:17:41.976371 WL = 0x2
3951 11:17:41.979492 RL = 0x2
3952 11:17:41.982730 BL = 0x2
3953 11:17:41.982812 RPST = 0x0
3954 11:17:41.986119 RD_PRE = 0x0
3955 11:17:41.986208 WR_PRE = 0x1
3956 11:17:41.989152 WR_PST = 0x0
3957 11:17:41.989235 DBI_WR = 0x0
3958 11:17:41.993029 DBI_RD = 0x0
3959 11:17:41.993112 OTF = 0x1
3960 11:17:41.996096 ===================================
3961 11:17:42.003003 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3962 11:17:42.006917 nWR fixed to 30
3963 11:17:42.010102 [ModeRegInit_LP4] CH0 RK0
3964 11:17:42.010185 [ModeRegInit_LP4] CH0 RK1
3965 11:17:42.013224 [ModeRegInit_LP4] CH1 RK0
3966 11:17:42.017140 [ModeRegInit_LP4] CH1 RK1
3967 11:17:42.017223 match AC timing 17
3968 11:17:42.023505 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3969 11:17:42.026357 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3970 11:17:42.029995 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3971 11:17:42.036678 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3972 11:17:42.040077 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3973 11:17:42.040160 ==
3974 11:17:42.043042 Dram Type= 6, Freq= 0, CH_0, rank 0
3975 11:17:42.047073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3976 11:17:42.047178 ==
3977 11:17:42.053153 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3978 11:17:42.059927 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3979 11:17:42.063197 [CA 0] Center 35 (5~66) winsize 62
3980 11:17:42.066327 [CA 1] Center 35 (5~66) winsize 62
3981 11:17:42.070056 [CA 2] Center 33 (3~64) winsize 62
3982 11:17:42.073311 [CA 3] Center 33 (2~64) winsize 63
3983 11:17:42.076674 [CA 4] Center 33 (2~64) winsize 63
3984 11:17:42.079805 [CA 5] Center 32 (2~63) winsize 62
3985 11:17:42.079888
3986 11:17:42.083214 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3987 11:17:42.083321
3988 11:17:42.086999 [CATrainingPosCal] consider 1 rank data
3989 11:17:42.089544 u2DelayCellTimex100 = 270/100 ps
3990 11:17:42.093367 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
3991 11:17:42.096270 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
3992 11:17:42.100019 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
3993 11:17:42.103135 CA3 delay=33 (2~64),Diff = 1 PI (9 cell)
3994 11:17:42.106329 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
3995 11:17:42.109859 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
3996 11:17:42.113042
3997 11:17:42.116447 CA PerBit enable=1, Macro0, CA PI delay=32
3998 11:17:42.116556
3999 11:17:42.120223 [CBTSetCACLKResult] CA Dly = 32
4000 11:17:42.120307 CS Dly: 4 (0~35)
4001 11:17:42.120374 ==
4002 11:17:42.123020 Dram Type= 6, Freq= 0, CH_0, rank 1
4003 11:17:42.126420 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4004 11:17:42.126506 ==
4005 11:17:42.133051 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4006 11:17:42.139726 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4007 11:17:42.142770 [CA 0] Center 35 (5~66) winsize 62
4008 11:17:42.146448 [CA 1] Center 35 (5~66) winsize 62
4009 11:17:42.149555 [CA 2] Center 34 (3~65) winsize 63
4010 11:17:42.152759 [CA 3] Center 34 (3~65) winsize 63
4011 11:17:42.156651 [CA 4] Center 33 (2~64) winsize 63
4012 11:17:42.159832 [CA 5] Center 32 (2~63) winsize 62
4013 11:17:42.159914
4014 11:17:42.163506 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4015 11:17:42.163588
4016 11:17:42.166492 [CATrainingPosCal] consider 2 rank data
4017 11:17:42.169720 u2DelayCellTimex100 = 270/100 ps
4018 11:17:42.172964 CA0 delay=35 (5~66),Diff = 3 PI (28 cell)
4019 11:17:42.176124 CA1 delay=35 (5~66),Diff = 3 PI (28 cell)
4020 11:17:42.179739 CA2 delay=33 (3~64),Diff = 1 PI (9 cell)
4021 11:17:42.183044 CA3 delay=33 (3~64),Diff = 1 PI (9 cell)
4022 11:17:42.186647 CA4 delay=33 (2~64),Diff = 1 PI (9 cell)
4023 11:17:42.193202 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
4024 11:17:42.193307
4025 11:17:42.196301 CA PerBit enable=1, Macro0, CA PI delay=32
4026 11:17:42.196384
4027 11:17:42.199299 [CBTSetCACLKResult] CA Dly = 32
4028 11:17:42.199397 CS Dly: 4 (0~36)
4029 11:17:42.199464
4030 11:17:42.203170 ----->DramcWriteLeveling(PI) begin...
4031 11:17:42.203244 ==
4032 11:17:42.206335 Dram Type= 6, Freq= 0, CH_0, rank 0
4033 11:17:42.212751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4034 11:17:42.212848 ==
4035 11:17:42.215866 Write leveling (Byte 0): 34 => 34
4036 11:17:42.215941 Write leveling (Byte 1): 34 => 34
4037 11:17:42.219668 DramcWriteLeveling(PI) end<-----
4038 11:17:42.219750
4039 11:17:42.219835 ==
4040 11:17:42.223148 Dram Type= 6, Freq= 0, CH_0, rank 0
4041 11:17:42.229686 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4042 11:17:42.229803 ==
4043 11:17:42.229902 [Gating] SW mode calibration
4044 11:17:42.239582 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4045 11:17:42.243205 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4046 11:17:42.249693 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4047 11:17:42.252989 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4048 11:17:42.256197 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4049 11:17:42.262669 0 9 12 | B1->B0 | 3434 2b2b | 1 0 | (1 1) (0 0)
4050 11:17:42.265711 0 9 16 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
4051 11:17:42.268970 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4052 11:17:42.276006 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4053 11:17:42.279182 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4054 11:17:42.282242 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4055 11:17:42.285846 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4056 11:17:42.292132 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4057 11:17:42.295949 0 10 12 | B1->B0 | 2323 3838 | 0 0 | (0 0) (0 0)
4058 11:17:42.299124 0 10 16 | B1->B0 | 3232 4646 | 0 0 | (1 1) (0 0)
4059 11:17:42.305608 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4060 11:17:42.309433 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4061 11:17:42.312577 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4062 11:17:42.318902 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4063 11:17:42.321956 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4064 11:17:42.325642 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4065 11:17:42.332083 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4066 11:17:42.335819 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4067 11:17:42.338758 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 11:17:42.345308 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 11:17:42.348388 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 11:17:42.351938 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 11:17:42.358508 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 11:17:42.361812 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 11:17:42.364945 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 11:17:42.372156 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 11:17:42.375393 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 11:17:42.378544 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 11:17:42.385079 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4078 11:17:42.388669 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4079 11:17:42.391866 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4080 11:17:42.398600 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4081 11:17:42.401653 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4082 11:17:42.405479 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4083 11:17:42.408454 Total UI for P1: 0, mck2ui 16
4084 11:17:42.411570 best dqsien dly found for B0: ( 0, 13, 12)
4085 11:17:42.415202 Total UI for P1: 0, mck2ui 16
4086 11:17:42.418444 best dqsien dly found for B1: ( 0, 13, 14)
4087 11:17:42.421871 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4088 11:17:42.425177 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4089 11:17:42.425291
4090 11:17:42.431644 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4091 11:17:42.435330 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4092 11:17:42.435443 [Gating] SW calibration Done
4093 11:17:42.438222 ==
4094 11:17:42.442023 Dram Type= 6, Freq= 0, CH_0, rank 0
4095 11:17:42.445158 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4096 11:17:42.445241 ==
4097 11:17:42.445307 RX Vref Scan: 0
4098 11:17:42.445376
4099 11:17:42.448081 RX Vref 0 -> 0, step: 1
4100 11:17:42.448163
4101 11:17:42.451538 RX Delay -230 -> 252, step: 16
4102 11:17:42.455091 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4103 11:17:42.458305 iDelay=218, Bit 1, Center 65 (-86 ~ 217) 304
4104 11:17:42.464931 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4105 11:17:42.468307 iDelay=218, Bit 3, Center 57 (-86 ~ 201) 288
4106 11:17:42.471299 iDelay=218, Bit 4, Center 65 (-86 ~ 217) 304
4107 11:17:42.474644 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4108 11:17:42.478696 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4109 11:17:42.484394 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4110 11:17:42.488109 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4111 11:17:42.491350 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4112 11:17:42.494387 iDelay=218, Bit 10, Center 57 (-86 ~ 201) 288
4113 11:17:42.498312 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4114 11:17:42.504509 iDelay=218, Bit 12, Center 57 (-86 ~ 201) 288
4115 11:17:42.508450 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4116 11:17:42.511483 iDelay=218, Bit 14, Center 65 (-86 ~ 217) 304
4117 11:17:42.515195 iDelay=218, Bit 15, Center 65 (-86 ~ 217) 304
4118 11:17:42.515306 ==
4119 11:17:42.518011 Dram Type= 6, Freq= 0, CH_0, rank 0
4120 11:17:42.524470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4121 11:17:42.524574 ==
4122 11:17:42.524670 DQS Delay:
4123 11:17:42.528266 DQS0 = 0, DQS1 = 0
4124 11:17:42.528375 DQM Delay:
4125 11:17:42.528473 DQM0 = 58, DQM1 = 51
4126 11:17:42.531263 DQ Delay:
4127 11:17:42.534513 DQ0 =57, DQ1 =65, DQ2 =49, DQ3 =57
4128 11:17:42.537986 DQ4 =65, DQ5 =41, DQ6 =65, DQ7 =65
4129 11:17:42.540940 DQ8 =33, DQ9 =33, DQ10 =57, DQ11 =41
4130 11:17:42.544444 DQ12 =57, DQ13 =57, DQ14 =65, DQ15 =65
4131 11:17:42.544527
4132 11:17:42.544592
4133 11:17:42.544654 ==
4134 11:17:42.548103 Dram Type= 6, Freq= 0, CH_0, rank 0
4135 11:17:42.551102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4136 11:17:42.551199 ==
4137 11:17:42.551293
4138 11:17:42.551375
4139 11:17:42.554582 TX Vref Scan disable
4140 11:17:42.557576 == TX Byte 0 ==
4141 11:17:42.561289 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4142 11:17:42.564372 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4143 11:17:42.567909 == TX Byte 1 ==
4144 11:17:42.570948 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4145 11:17:42.574211 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4146 11:17:42.574295 ==
4147 11:17:42.577452 Dram Type= 6, Freq= 0, CH_0, rank 0
4148 11:17:42.580717 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4149 11:17:42.584407 ==
4150 11:17:42.584492
4151 11:17:42.584565
4152 11:17:42.584624 TX Vref Scan disable
4153 11:17:42.587693 == TX Byte 0 ==
4154 11:17:42.591446 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4155 11:17:42.597567 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4156 11:17:42.597669 == TX Byte 1 ==
4157 11:17:42.601234 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4158 11:17:42.608216 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4159 11:17:42.608300
4160 11:17:42.608365 [DATLAT]
4161 11:17:42.608424 Freq=600, CH0 RK0
4162 11:17:42.608484
4163 11:17:42.611277 DATLAT Default: 0x9
4164 11:17:42.611370 0, 0xFFFF, sum = 0
4165 11:17:42.614351 1, 0xFFFF, sum = 0
4166 11:17:42.614435 2, 0xFFFF, sum = 0
4167 11:17:42.618058 3, 0xFFFF, sum = 0
4168 11:17:42.621109 4, 0xFFFF, sum = 0
4169 11:17:42.621193 5, 0xFFFF, sum = 0
4170 11:17:42.624730 6, 0xFFFF, sum = 0
4171 11:17:42.624814 7, 0xFFFF, sum = 0
4172 11:17:42.627808 8, 0x0, sum = 1
4173 11:17:42.627893 9, 0x0, sum = 2
4174 11:17:42.627959 10, 0x0, sum = 3
4175 11:17:42.631490 11, 0x0, sum = 4
4176 11:17:42.631574 best_step = 9
4177 11:17:42.631638
4178 11:17:42.631697 ==
4179 11:17:42.634496 Dram Type= 6, Freq= 0, CH_0, rank 0
4180 11:17:42.641347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4181 11:17:42.641446 ==
4182 11:17:42.641514 RX Vref Scan: 1
4183 11:17:42.641575
4184 11:17:42.644668 RX Vref 0 -> 0, step: 1
4185 11:17:42.644750
4186 11:17:42.647635 RX Delay -163 -> 252, step: 8
4187 11:17:42.647717
4188 11:17:42.651234 Set Vref, RX VrefLevel [Byte0]: 54
4189 11:17:42.654534 [Byte1]: 55
4190 11:17:42.654617
4191 11:17:42.657770 Final RX Vref Byte 0 = 54 to rank0
4192 11:17:42.661336 Final RX Vref Byte 1 = 55 to rank0
4193 11:17:42.664336 Final RX Vref Byte 0 = 54 to rank1
4194 11:17:42.667806 Final RX Vref Byte 1 = 55 to rank1==
4195 11:17:42.670960 Dram Type= 6, Freq= 0, CH_0, rank 0
4196 11:17:42.674284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4197 11:17:42.674396 ==
4198 11:17:42.677478 DQS Delay:
4199 11:17:42.677560 DQS0 = 0, DQS1 = 0
4200 11:17:42.677623 DQM Delay:
4201 11:17:42.681392 DQM0 = 52, DQM1 = 48
4202 11:17:42.681467 DQ Delay:
4203 11:17:42.683982 DQ0 =52, DQ1 =56, DQ2 =48, DQ3 =48
4204 11:17:42.687304 DQ4 =56, DQ5 =44, DQ6 =60, DQ7 =56
4205 11:17:42.691081 DQ8 =40, DQ9 =36, DQ10 =48, DQ11 =44
4206 11:17:42.694295 DQ12 =56, DQ13 =56, DQ14 =56, DQ15 =52
4207 11:17:42.694369
4208 11:17:42.694431
4209 11:17:42.704328 [DQSOSCAuto] RK0, (LSB)MR18= 0x7265, (MSB)MR19= 0x808, tDQSOscB0 = 390 ps tDQSOscB1 = 388 ps
4210 11:17:42.707305 CH0 RK0: MR19=808, MR18=7265
4211 11:17:42.710599 CH0_RK0: MR19=0x808, MR18=0x7265, DQSOSC=388, MR23=63, INC=174, DEC=116
4212 11:17:42.710711
4213 11:17:42.714313 ----->DramcWriteLeveling(PI) begin...
4214 11:17:42.717378 ==
4215 11:17:42.720622 Dram Type= 6, Freq= 0, CH_0, rank 1
4216 11:17:42.724117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4217 11:17:42.724196 ==
4218 11:17:42.727216 Write leveling (Byte 0): 35 => 35
4219 11:17:42.730879 Write leveling (Byte 1): 31 => 31
4220 11:17:42.734122 DramcWriteLeveling(PI) end<-----
4221 11:17:42.734231
4222 11:17:42.734324 ==
4223 11:17:42.737331 Dram Type= 6, Freq= 0, CH_0, rank 1
4224 11:17:42.741066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4225 11:17:42.741189 ==
4226 11:17:42.744436 [Gating] SW mode calibration
4227 11:17:42.750506 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4228 11:17:42.757451 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4229 11:17:42.760207 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4230 11:17:42.763831 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4231 11:17:42.770599 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4232 11:17:42.774028 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
4233 11:17:42.777120 0 9 16 | B1->B0 | 2626 2f2f | 1 0 | (1 0) (1 1)
4234 11:17:42.780669 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4235 11:17:42.787465 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4236 11:17:42.790177 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4237 11:17:42.794012 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4238 11:17:42.800496 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4239 11:17:42.804003 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4240 11:17:42.807237 0 10 12 | B1->B0 | 2828 2828 | 0 0 | (0 0) (1 1)
4241 11:17:42.813939 0 10 16 | B1->B0 | 3e3e 4444 | 0 0 | (0 0) (0 0)
4242 11:17:42.817131 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4243 11:17:42.820400 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4244 11:17:42.827215 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4245 11:17:42.830516 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4246 11:17:42.834219 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4247 11:17:42.840352 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4248 11:17:42.843540 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4249 11:17:42.847191 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4250 11:17:42.853554 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 11:17:42.857162 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 11:17:42.860118 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 11:17:42.866922 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 11:17:42.870327 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 11:17:42.873458 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 11:17:42.879913 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 11:17:42.883110 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 11:17:42.886614 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 11:17:42.893391 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 11:17:42.896530 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 11:17:42.900513 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 11:17:42.906834 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 11:17:42.909866 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 11:17:42.913080 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4265 11:17:42.916717 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4266 11:17:42.919811 Total UI for P1: 0, mck2ui 16
4267 11:17:42.923100 best dqsien dly found for B0: ( 0, 13, 12)
4268 11:17:42.926998 Total UI for P1: 0, mck2ui 16
4269 11:17:42.930030 best dqsien dly found for B1: ( 0, 13, 14)
4270 11:17:42.933273 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4271 11:17:42.939908 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4272 11:17:42.939993
4273 11:17:42.943432 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4274 11:17:42.946870 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4275 11:17:42.950099 [Gating] SW calibration Done
4276 11:17:42.950177 ==
4277 11:17:42.953057 Dram Type= 6, Freq= 0, CH_0, rank 1
4278 11:17:42.956135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4279 11:17:42.956212 ==
4280 11:17:42.959848 RX Vref Scan: 0
4281 11:17:42.959950
4282 11:17:42.960031 RX Vref 0 -> 0, step: 1
4283 11:17:42.960108
4284 11:17:42.962989 RX Delay -230 -> 252, step: 16
4285 11:17:42.966202 iDelay=218, Bit 0, Center 57 (-86 ~ 201) 288
4286 11:17:42.973013 iDelay=218, Bit 1, Center 57 (-86 ~ 201) 288
4287 11:17:42.976562 iDelay=218, Bit 2, Center 57 (-86 ~ 201) 288
4288 11:17:42.979536 iDelay=218, Bit 3, Center 57 (-86 ~ 201) 288
4289 11:17:42.983183 iDelay=218, Bit 4, Center 65 (-86 ~ 217) 304
4290 11:17:42.986221 iDelay=218, Bit 5, Center 49 (-102 ~ 201) 304
4291 11:17:42.992830 iDelay=218, Bit 6, Center 65 (-86 ~ 217) 304
4292 11:17:42.995891 iDelay=218, Bit 7, Center 65 (-86 ~ 217) 304
4293 11:17:42.999929 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4294 11:17:43.002814 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4295 11:17:43.006128 iDelay=218, Bit 10, Center 57 (-86 ~ 201) 288
4296 11:17:43.012587 iDelay=218, Bit 11, Center 33 (-118 ~ 185) 304
4297 11:17:43.016613 iDelay=218, Bit 12, Center 57 (-86 ~ 201) 288
4298 11:17:43.019386 iDelay=218, Bit 13, Center 57 (-86 ~ 201) 288
4299 11:17:43.022992 iDelay=218, Bit 14, Center 57 (-86 ~ 201) 288
4300 11:17:43.029950 iDelay=218, Bit 15, Center 57 (-86 ~ 201) 288
4301 11:17:43.030051 ==
4302 11:17:43.032968 Dram Type= 6, Freq= 0, CH_0, rank 1
4303 11:17:43.036354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4304 11:17:43.036456 ==
4305 11:17:43.036548 DQS Delay:
4306 11:17:43.039231 DQS0 = 0, DQS1 = 0
4307 11:17:43.039333 DQM Delay:
4308 11:17:43.043069 DQM0 = 59, DQM1 = 48
4309 11:17:43.043169 DQ Delay:
4310 11:17:43.045834 DQ0 =57, DQ1 =57, DQ2 =57, DQ3 =57
4311 11:17:43.049574 DQ4 =65, DQ5 =49, DQ6 =65, DQ7 =65
4312 11:17:43.053009 DQ8 =33, DQ9 =33, DQ10 =57, DQ11 =33
4313 11:17:43.056061 DQ12 =57, DQ13 =57, DQ14 =57, DQ15 =57
4314 11:17:43.056139
4315 11:17:43.056206
4316 11:17:43.056264 ==
4317 11:17:43.059396 Dram Type= 6, Freq= 0, CH_0, rank 1
4318 11:17:43.063127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4319 11:17:43.063235 ==
4320 11:17:43.063333
4321 11:17:43.063401
4322 11:17:43.066147 TX Vref Scan disable
4323 11:17:43.069381 == TX Byte 0 ==
4324 11:17:43.073030 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4325 11:17:43.076307 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4326 11:17:43.079810 == TX Byte 1 ==
4327 11:17:43.082840 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4328 11:17:43.086454 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4329 11:17:43.086531 ==
4330 11:17:43.089762 Dram Type= 6, Freq= 0, CH_0, rank 1
4331 11:17:43.095972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4332 11:17:43.096053 ==
4333 11:17:43.096150
4334 11:17:43.096240
4335 11:17:43.096327 TX Vref Scan disable
4336 11:17:43.100530 == TX Byte 0 ==
4337 11:17:43.103657 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4338 11:17:43.110347 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4339 11:17:43.110456 == TX Byte 1 ==
4340 11:17:43.113904 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4341 11:17:43.120289 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4342 11:17:43.120384
4343 11:17:43.120481 [DATLAT]
4344 11:17:43.120572 Freq=600, CH0 RK1
4345 11:17:43.120655
4346 11:17:43.123958 DATLAT Default: 0x9
4347 11:17:43.124034 0, 0xFFFF, sum = 0
4348 11:17:43.126899 1, 0xFFFF, sum = 0
4349 11:17:43.127002 2, 0xFFFF, sum = 0
4350 11:17:43.130707 3, 0xFFFF, sum = 0
4351 11:17:43.130809 4, 0xFFFF, sum = 0
4352 11:17:43.133708 5, 0xFFFF, sum = 0
4353 11:17:43.137029 6, 0xFFFF, sum = 0
4354 11:17:43.137107 7, 0xFFFF, sum = 0
4355 11:17:43.137182 8, 0x0, sum = 1
4356 11:17:43.140117 9, 0x0, sum = 2
4357 11:17:43.140215 10, 0x0, sum = 3
4358 11:17:43.143770 11, 0x0, sum = 4
4359 11:17:43.143868 best_step = 9
4360 11:17:43.143958
4361 11:17:43.144020 ==
4362 11:17:43.146742 Dram Type= 6, Freq= 0, CH_0, rank 1
4363 11:17:43.153578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4364 11:17:43.153683 ==
4365 11:17:43.153773 RX Vref Scan: 0
4366 11:17:43.153864
4367 11:17:43.157125 RX Vref 0 -> 0, step: 1
4368 11:17:43.157193
4369 11:17:43.160097 RX Delay -163 -> 252, step: 8
4370 11:17:43.163840 iDelay=197, Bit 0, Center 52 (-91 ~ 196) 288
4371 11:17:43.170110 iDelay=197, Bit 1, Center 52 (-91 ~ 196) 288
4372 11:17:43.173961 iDelay=197, Bit 2, Center 48 (-99 ~ 196) 296
4373 11:17:43.177056 iDelay=197, Bit 3, Center 52 (-91 ~ 196) 288
4374 11:17:43.179885 iDelay=197, Bit 4, Center 52 (-91 ~ 196) 288
4375 11:17:43.183132 iDelay=197, Bit 5, Center 44 (-99 ~ 188) 288
4376 11:17:43.186487 iDelay=197, Bit 6, Center 56 (-83 ~ 196) 280
4377 11:17:43.193396 iDelay=197, Bit 7, Center 56 (-83 ~ 196) 280
4378 11:17:43.196852 iDelay=197, Bit 8, Center 36 (-107 ~ 180) 288
4379 11:17:43.199925 iDelay=197, Bit 9, Center 36 (-107 ~ 180) 288
4380 11:17:43.203302 iDelay=197, Bit 10, Center 48 (-91 ~ 188) 280
4381 11:17:43.209813 iDelay=197, Bit 11, Center 36 (-107 ~ 180) 288
4382 11:17:43.213374 iDelay=197, Bit 12, Center 52 (-91 ~ 196) 288
4383 11:17:43.216863 iDelay=197, Bit 13, Center 52 (-91 ~ 196) 288
4384 11:17:43.220619 iDelay=197, Bit 14, Center 52 (-91 ~ 196) 288
4385 11:17:43.223287 iDelay=197, Bit 15, Center 52 (-91 ~ 196) 288
4386 11:17:43.227003 ==
4387 11:17:43.227109 Dram Type= 6, Freq= 0, CH_0, rank 1
4388 11:17:43.233306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4389 11:17:43.233387 ==
4390 11:17:43.233450 DQS Delay:
4391 11:17:43.236803 DQS0 = 0, DQS1 = 0
4392 11:17:43.236883 DQM Delay:
4393 11:17:43.240071 DQM0 = 51, DQM1 = 45
4394 11:17:43.240150 DQ Delay:
4395 11:17:43.243219 DQ0 =52, DQ1 =52, DQ2 =48, DQ3 =52
4396 11:17:43.246817 DQ4 =52, DQ5 =44, DQ6 =56, DQ7 =56
4397 11:17:43.249972 DQ8 =36, DQ9 =36, DQ10 =48, DQ11 =36
4398 11:17:43.253001 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =52
4399 11:17:43.253082
4400 11:17:43.253146
4401 11:17:43.260226 [DQSOSCAuto] RK1, (LSB)MR18= 0x6020, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 391 ps
4402 11:17:43.263250 CH0 RK1: MR19=808, MR18=6020
4403 11:17:43.269940 CH0_RK1: MR19=0x808, MR18=0x6020, DQSOSC=391, MR23=63, INC=171, DEC=114
4404 11:17:43.273064 [RxdqsGatingPostProcess] freq 600
4405 11:17:43.280085 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4406 11:17:43.280165 Pre-setting of DQS Precalculation
4407 11:17:43.286239 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4408 11:17:43.286319 ==
4409 11:17:43.289744 Dram Type= 6, Freq= 0, CH_1, rank 0
4410 11:17:43.293514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4411 11:17:43.293594 ==
4412 11:17:43.299925 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4413 11:17:43.306300 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4414 11:17:43.309689 [CA 0] Center 36 (5~67) winsize 63
4415 11:17:43.312621 [CA 1] Center 36 (5~67) winsize 63
4416 11:17:43.316074 [CA 2] Center 34 (4~65) winsize 62
4417 11:17:43.319754 [CA 3] Center 34 (4~65) winsize 62
4418 11:17:43.323115 [CA 4] Center 34 (4~65) winsize 62
4419 11:17:43.326099 [CA 5] Center 33 (3~64) winsize 62
4420 11:17:43.326182
4421 11:17:43.329514 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4422 11:17:43.329596
4423 11:17:43.332465 [CATrainingPosCal] consider 1 rank data
4424 11:17:43.335923 u2DelayCellTimex100 = 270/100 ps
4425 11:17:43.339204 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
4426 11:17:43.342835 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4427 11:17:43.346269 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4428 11:17:43.349427 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4429 11:17:43.352987 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4430 11:17:43.356050 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4431 11:17:43.359100
4432 11:17:43.362850 CA PerBit enable=1, Macro0, CA PI delay=33
4433 11:17:43.362932
4434 11:17:43.365949 [CBTSetCACLKResult] CA Dly = 33
4435 11:17:43.366031 CS Dly: 5 (0~36)
4436 11:17:43.366096 ==
4437 11:17:43.369469 Dram Type= 6, Freq= 0, CH_1, rank 1
4438 11:17:43.372336 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4439 11:17:43.372419 ==
4440 11:17:43.379512 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4441 11:17:43.385644 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4442 11:17:43.389581 [CA 0] Center 36 (5~67) winsize 63
4443 11:17:43.392704 [CA 1] Center 36 (5~67) winsize 63
4444 11:17:43.396242 [CA 2] Center 34 (4~65) winsize 62
4445 11:17:43.399125 [CA 3] Center 34 (4~65) winsize 62
4446 11:17:43.402622 [CA 4] Center 34 (4~65) winsize 62
4447 11:17:43.406236 [CA 5] Center 34 (3~65) winsize 63
4448 11:17:43.406344
4449 11:17:43.409755 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4450 11:17:43.409837
4451 11:17:43.413241 [CATrainingPosCal] consider 2 rank data
4452 11:17:43.416103 u2DelayCellTimex100 = 270/100 ps
4453 11:17:43.419165 CA0 delay=36 (5~67),Diff = 3 PI (28 cell)
4454 11:17:43.422629 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
4455 11:17:43.426027 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4456 11:17:43.429576 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4457 11:17:43.432715 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4458 11:17:43.436045 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4459 11:17:43.439078
4460 11:17:43.442377 CA PerBit enable=1, Macro0, CA PI delay=33
4461 11:17:43.442458
4462 11:17:43.445623 [CBTSetCACLKResult] CA Dly = 33
4463 11:17:43.445705 CS Dly: 5 (0~37)
4464 11:17:43.445769
4465 11:17:43.449311 ----->DramcWriteLeveling(PI) begin...
4466 11:17:43.449394 ==
4467 11:17:43.452378 Dram Type= 6, Freq= 0, CH_1, rank 0
4468 11:17:43.456067 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4469 11:17:43.459233 ==
4470 11:17:43.459315 Write leveling (Byte 0): 32 => 32
4471 11:17:43.462253 Write leveling (Byte 1): 30 => 30
4472 11:17:43.465589 DramcWriteLeveling(PI) end<-----
4473 11:17:43.465671
4474 11:17:43.465735 ==
4475 11:17:43.469048 Dram Type= 6, Freq= 0, CH_1, rank 0
4476 11:17:43.475578 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4477 11:17:43.475660 ==
4478 11:17:43.475725 [Gating] SW mode calibration
4479 11:17:43.485592 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4480 11:17:43.489331 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4481 11:17:43.495439 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4482 11:17:43.499251 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4483 11:17:43.502273 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4484 11:17:43.508722 0 9 12 | B1->B0 | 2e2e 2e2e | 1 1 | (1 0) (1 0)
4485 11:17:43.512331 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4486 11:17:43.515125 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4487 11:17:43.521902 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4488 11:17:43.525372 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4489 11:17:43.528432 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4490 11:17:43.535140 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4491 11:17:43.538382 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4492 11:17:43.541624 0 10 12 | B1->B0 | 3838 3c3c | 0 0 | (0 0) (1 1)
4493 11:17:43.544954 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4494 11:17:43.551995 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4495 11:17:43.554895 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4496 11:17:43.558907 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4497 11:17:43.565077 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4498 11:17:43.568249 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4499 11:17:43.572038 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4500 11:17:43.578606 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4501 11:17:43.581791 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4502 11:17:43.585428 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4503 11:17:43.591750 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4504 11:17:43.595514 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4505 11:17:43.598401 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 11:17:43.605372 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 11:17:43.608401 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 11:17:43.611965 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 11:17:43.618235 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 11:17:43.621761 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 11:17:43.625274 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 11:17:43.631482 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 11:17:43.634848 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 11:17:43.638340 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 11:17:43.645424 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 11:17:43.648355 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4517 11:17:43.651736 Total UI for P1: 0, mck2ui 16
4518 11:17:43.654617 best dqsien dly found for B0: ( 0, 13, 10)
4519 11:17:43.657994 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4520 11:17:43.661516 Total UI for P1: 0, mck2ui 16
4521 11:17:43.664744 best dqsien dly found for B1: ( 0, 13, 12)
4522 11:17:43.668583 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4523 11:17:43.671619 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4524 11:17:43.671700
4525 11:17:43.674643 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4526 11:17:43.681441 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4527 11:17:43.681522 [Gating] SW calibration Done
4528 11:17:43.684401 ==
4529 11:17:43.684482 Dram Type= 6, Freq= 0, CH_1, rank 0
4530 11:17:43.691116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4531 11:17:43.691197 ==
4532 11:17:43.691260 RX Vref Scan: 0
4533 11:17:43.691320
4534 11:17:43.694927 RX Vref 0 -> 0, step: 1
4535 11:17:43.695007
4536 11:17:43.698271 RX Delay -230 -> 252, step: 16
4537 11:17:43.701228 iDelay=218, Bit 0, Center 57 (-102 ~ 217) 320
4538 11:17:43.705048 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4539 11:17:43.711153 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4540 11:17:43.714524 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4541 11:17:43.718088 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4542 11:17:43.721116 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4543 11:17:43.724340 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4544 11:17:43.731232 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4545 11:17:43.734688 iDelay=218, Bit 8, Center 33 (-118 ~ 185) 304
4546 11:17:43.738162 iDelay=218, Bit 9, Center 33 (-118 ~ 185) 304
4547 11:17:43.741136 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4548 11:17:43.747819 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4549 11:17:43.751123 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4550 11:17:43.754655 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4551 11:17:43.757666 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4552 11:17:43.764768 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4553 11:17:43.764851 ==
4554 11:17:43.768198 Dram Type= 6, Freq= 0, CH_1, rank 0
4555 11:17:43.771182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4556 11:17:43.771264 ==
4557 11:17:43.771336 DQS Delay:
4558 11:17:43.774347 DQS0 = 0, DQS1 = 0
4559 11:17:43.774428 DQM Delay:
4560 11:17:43.778120 DQM0 = 50, DQM1 = 46
4561 11:17:43.778201 DQ Delay:
4562 11:17:43.781041 DQ0 =57, DQ1 =41, DQ2 =41, DQ3 =49
4563 11:17:43.784360 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4564 11:17:43.788092 DQ8 =33, DQ9 =33, DQ10 =49, DQ11 =41
4565 11:17:43.791072 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =57
4566 11:17:43.791153
4567 11:17:43.791216
4568 11:17:43.791275 ==
4569 11:17:43.794220 Dram Type= 6, Freq= 0, CH_1, rank 0
4570 11:17:43.797661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4571 11:17:43.797742 ==
4572 11:17:43.797806
4573 11:17:43.797863
4574 11:17:43.801495 TX Vref Scan disable
4575 11:17:43.804781 == TX Byte 0 ==
4576 11:17:43.807622 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4577 11:17:43.811512 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4578 11:17:43.814624 == TX Byte 1 ==
4579 11:17:43.817788 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4580 11:17:43.821343 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4581 11:17:43.821424 ==
4582 11:17:43.824523 Dram Type= 6, Freq= 0, CH_1, rank 0
4583 11:17:43.831452 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4584 11:17:43.831533 ==
4585 11:17:43.831597
4586 11:17:43.831655
4587 11:17:43.831712 TX Vref Scan disable
4588 11:17:43.835203 == TX Byte 0 ==
4589 11:17:43.838518 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4590 11:17:43.844965 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4591 11:17:43.845050 == TX Byte 1 ==
4592 11:17:43.848427 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4593 11:17:43.851992 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4594 11:17:43.855443
4595 11:17:43.855523 [DATLAT]
4596 11:17:43.855587 Freq=600, CH1 RK0
4597 11:17:43.855645
4598 11:17:43.858333 DATLAT Default: 0x9
4599 11:17:43.858413 0, 0xFFFF, sum = 0
4600 11:17:43.861848 1, 0xFFFF, sum = 0
4601 11:17:43.861930 2, 0xFFFF, sum = 0
4602 11:17:43.865255 3, 0xFFFF, sum = 0
4603 11:17:43.865337 4, 0xFFFF, sum = 0
4604 11:17:43.868456 5, 0xFFFF, sum = 0
4605 11:17:43.871836 6, 0xFFFF, sum = 0
4606 11:17:43.871918 7, 0xFFFF, sum = 0
4607 11:17:43.871983 8, 0x0, sum = 1
4608 11:17:43.875197 9, 0x0, sum = 2
4609 11:17:43.875279 10, 0x0, sum = 3
4610 11:17:43.878551 11, 0x0, sum = 4
4611 11:17:43.878633 best_step = 9
4612 11:17:43.878697
4613 11:17:43.878756 ==
4614 11:17:43.881988 Dram Type= 6, Freq= 0, CH_1, rank 0
4615 11:17:43.888189 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4616 11:17:43.888270 ==
4617 11:17:43.888333 RX Vref Scan: 1
4618 11:17:43.888393
4619 11:17:43.891898 RX Vref 0 -> 0, step: 1
4620 11:17:43.891978
4621 11:17:43.895062 RX Delay -163 -> 252, step: 8
4622 11:17:43.895144
4623 11:17:43.898645 Set Vref, RX VrefLevel [Byte0]: 51
4624 11:17:43.902195 [Byte1]: 53
4625 11:17:43.902276
4626 11:17:43.905338 Final RX Vref Byte 0 = 51 to rank0
4627 11:17:43.908386 Final RX Vref Byte 1 = 53 to rank0
4628 11:17:43.912090 Final RX Vref Byte 0 = 51 to rank1
4629 11:17:43.915362 Final RX Vref Byte 1 = 53 to rank1==
4630 11:17:43.918395 Dram Type= 6, Freq= 0, CH_1, rank 0
4631 11:17:43.922039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4632 11:17:43.922121 ==
4633 11:17:43.925208 DQS Delay:
4634 11:17:43.925291 DQS0 = 0, DQS1 = 0
4635 11:17:43.925356 DQM Delay:
4636 11:17:43.928434 DQM0 = 48, DQM1 = 45
4637 11:17:43.928516 DQ Delay:
4638 11:17:43.932107 DQ0 =52, DQ1 =40, DQ2 =36, DQ3 =44
4639 11:17:43.935049 DQ4 =48, DQ5 =60, DQ6 =56, DQ7 =48
4640 11:17:43.938312 DQ8 =32, DQ9 =36, DQ10 =44, DQ11 =36
4641 11:17:43.941850 DQ12 =52, DQ13 =52, DQ14 =52, DQ15 =56
4642 11:17:43.941933
4643 11:17:43.941998
4644 11:17:43.951529 [DQSOSCAuto] RK0, (LSB)MR18= 0x476c, (MSB)MR19= 0x808, tDQSOscB0 = 389 ps tDQSOscB1 = 396 ps
4645 11:17:43.951613 CH1 RK0: MR19=808, MR18=476C
4646 11:17:43.958457 CH1_RK0: MR19=0x808, MR18=0x476C, DQSOSC=389, MR23=63, INC=173, DEC=115
4647 11:17:43.958540
4648 11:17:43.961828 ----->DramcWriteLeveling(PI) begin...
4649 11:17:43.964827 ==
4650 11:17:43.964912 Dram Type= 6, Freq= 0, CH_1, rank 1
4651 11:17:43.972022 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4652 11:17:43.972105 ==
4653 11:17:43.974858 Write leveling (Byte 0): 30 => 30
4654 11:17:43.978553 Write leveling (Byte 1): 30 => 30
4655 11:17:43.981639 DramcWriteLeveling(PI) end<-----
4656 11:17:43.981722
4657 11:17:43.981786 ==
4658 11:17:43.984677 Dram Type= 6, Freq= 0, CH_1, rank 1
4659 11:17:43.988379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4660 11:17:43.988462 ==
4661 11:17:43.991442 [Gating] SW mode calibration
4662 11:17:43.998227 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4663 11:17:44.001647 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4664 11:17:44.008281 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4665 11:17:44.011631 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4666 11:17:44.015221 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4667 11:17:44.021283 0 9 12 | B1->B0 | 2e2e 2f2f | 0 0 | (1 1) (0 0)
4668 11:17:44.024922 0 9 16 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4669 11:17:44.027914 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4670 11:17:44.034631 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4671 11:17:44.038385 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4672 11:17:44.041557 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4673 11:17:44.048591 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4674 11:17:44.051504 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4675 11:17:44.054947 0 10 12 | B1->B0 | 3838 3636 | 0 0 | (0 0) (0 0)
4676 11:17:44.061199 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4677 11:17:44.064651 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4678 11:17:44.068174 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4679 11:17:44.074625 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4680 11:17:44.078284 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4681 11:17:44.081213 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4682 11:17:44.087740 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4683 11:17:44.091342 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4684 11:17:44.094655 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4685 11:17:44.101093 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4686 11:17:44.104572 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4687 11:17:44.108188 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4688 11:17:44.111199 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4689 11:17:44.117825 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4690 11:17:44.121454 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4691 11:17:44.124529 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 11:17:44.130926 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 11:17:44.134461 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 11:17:44.137689 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 11:17:44.144475 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 11:17:44.148211 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 11:17:44.151344 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 11:17:44.158019 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 11:17:44.161312 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4700 11:17:44.164320 Total UI for P1: 0, mck2ui 16
4701 11:17:44.167614 best dqsien dly found for B1: ( 0, 13, 10)
4702 11:17:44.171262 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4703 11:17:44.174056 Total UI for P1: 0, mck2ui 16
4704 11:17:44.177632 best dqsien dly found for B0: ( 0, 13, 12)
4705 11:17:44.180744 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4706 11:17:44.184056 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4707 11:17:44.187507
4708 11:17:44.190944 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4709 11:17:44.194358 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4710 11:17:44.197318 [Gating] SW calibration Done
4711 11:17:44.197400 ==
4712 11:17:44.201103 Dram Type= 6, Freq= 0, CH_1, rank 1
4713 11:17:44.204140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4714 11:17:44.204223 ==
4715 11:17:44.204287 RX Vref Scan: 0
4716 11:17:44.204348
4717 11:17:44.207445 RX Vref 0 -> 0, step: 1
4718 11:17:44.207526
4719 11:17:44.211057 RX Delay -230 -> 252, step: 16
4720 11:17:44.214002 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4721 11:17:44.220519 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4722 11:17:44.224383 iDelay=218, Bit 2, Center 33 (-118 ~ 185) 304
4723 11:17:44.227364 iDelay=218, Bit 3, Center 49 (-102 ~ 201) 304
4724 11:17:44.230623 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4725 11:17:44.233859 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4726 11:17:44.240449 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4727 11:17:44.244380 iDelay=218, Bit 7, Center 49 (-102 ~ 201) 304
4728 11:17:44.247297 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4729 11:17:44.250568 iDelay=218, Bit 9, Center 41 (-118 ~ 201) 320
4730 11:17:44.257644 iDelay=218, Bit 10, Center 49 (-102 ~ 201) 304
4731 11:17:44.260841 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4732 11:17:44.263738 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4733 11:17:44.267055 iDelay=218, Bit 13, Center 57 (-102 ~ 217) 320
4734 11:17:44.270359 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4735 11:17:44.277344 iDelay=218, Bit 15, Center 57 (-102 ~ 217) 320
4736 11:17:44.277453 ==
4737 11:17:44.280380 Dram Type= 6, Freq= 0, CH_1, rank 1
4738 11:17:44.283713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4739 11:17:44.283795 ==
4740 11:17:44.283859 DQS Delay:
4741 11:17:44.287211 DQS0 = 0, DQS1 = 0
4742 11:17:44.287293 DQM Delay:
4743 11:17:44.290407 DQM0 = 48, DQM1 = 47
4744 11:17:44.290487 DQ Delay:
4745 11:17:44.293708 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =49
4746 11:17:44.297388 DQ4 =49, DQ5 =57, DQ6 =57, DQ7 =49
4747 11:17:44.300273 DQ8 =25, DQ9 =41, DQ10 =49, DQ11 =41
4748 11:17:44.304003 DQ12 =57, DQ13 =57, DQ14 =49, DQ15 =57
4749 11:17:44.304084
4750 11:17:44.304148
4751 11:17:44.304206 ==
4752 11:17:44.306913 Dram Type= 6, Freq= 0, CH_1, rank 1
4753 11:17:44.310927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4754 11:17:44.313984 ==
4755 11:17:44.314085
4756 11:17:44.314173
4757 11:17:44.314262 TX Vref Scan disable
4758 11:17:44.316904 == TX Byte 0 ==
4759 11:17:44.320489 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4760 11:17:44.324248 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4761 11:17:44.327104 == TX Byte 1 ==
4762 11:17:44.330796 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4763 11:17:44.333926 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4764 11:17:44.334007 ==
4765 11:17:44.337135 Dram Type= 6, Freq= 0, CH_1, rank 1
4766 11:17:44.343734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4767 11:17:44.343816 ==
4768 11:17:44.343880
4769 11:17:44.343938
4770 11:17:44.347489 TX Vref Scan disable
4771 11:17:44.347569 == TX Byte 0 ==
4772 11:17:44.353571 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4773 11:17:44.356874 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4774 11:17:44.356955 == TX Byte 1 ==
4775 11:17:44.363586 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4776 11:17:44.366919 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4777 11:17:44.367000
4778 11:17:44.367063 [DATLAT]
4779 11:17:44.370480 Freq=600, CH1 RK1
4780 11:17:44.370561
4781 11:17:44.370625 DATLAT Default: 0x9
4782 11:17:44.374011 0, 0xFFFF, sum = 0
4783 11:17:44.374093 1, 0xFFFF, sum = 0
4784 11:17:44.377229 2, 0xFFFF, sum = 0
4785 11:17:44.377310 3, 0xFFFF, sum = 0
4786 11:17:44.380262 4, 0xFFFF, sum = 0
4787 11:17:44.380344 5, 0xFFFF, sum = 0
4788 11:17:44.383517 6, 0xFFFF, sum = 0
4789 11:17:44.383599 7, 0xFFFF, sum = 0
4790 11:17:44.387137 8, 0x0, sum = 1
4791 11:17:44.387219 9, 0x0, sum = 2
4792 11:17:44.390535 10, 0x0, sum = 3
4793 11:17:44.390618 11, 0x0, sum = 4
4794 11:17:44.393724 best_step = 9
4795 11:17:44.393806
4796 11:17:44.393870 ==
4797 11:17:44.396691 Dram Type= 6, Freq= 0, CH_1, rank 1
4798 11:17:44.400151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4799 11:17:44.400232 ==
4800 11:17:44.403768 RX Vref Scan: 0
4801 11:17:44.403849
4802 11:17:44.403914 RX Vref 0 -> 0, step: 1
4803 11:17:44.403976
4804 11:17:44.406653 RX Delay -179 -> 252, step: 8
4805 11:17:44.413951 iDelay=205, Bit 0, Center 56 (-83 ~ 196) 280
4806 11:17:44.417170 iDelay=205, Bit 1, Center 44 (-99 ~ 188) 288
4807 11:17:44.420579 iDelay=205, Bit 2, Center 36 (-107 ~ 180) 288
4808 11:17:44.424195 iDelay=205, Bit 3, Center 44 (-99 ~ 188) 288
4809 11:17:44.427209 iDelay=205, Bit 4, Center 44 (-99 ~ 188) 288
4810 11:17:44.433894 iDelay=205, Bit 5, Center 60 (-83 ~ 204) 288
4811 11:17:44.437631 iDelay=205, Bit 6, Center 60 (-83 ~ 204) 288
4812 11:17:44.440547 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4813 11:17:44.444282 iDelay=205, Bit 8, Center 32 (-115 ~ 180) 296
4814 11:17:44.447279 iDelay=205, Bit 9, Center 32 (-115 ~ 180) 296
4815 11:17:44.453906 iDelay=205, Bit 10, Center 48 (-99 ~ 196) 296
4816 11:17:44.457049 iDelay=205, Bit 11, Center 40 (-107 ~ 188) 296
4817 11:17:44.460854 iDelay=205, Bit 12, Center 52 (-99 ~ 204) 304
4818 11:17:44.463817 iDelay=205, Bit 13, Center 52 (-91 ~ 196) 288
4819 11:17:44.470684 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4820 11:17:44.473620 iDelay=205, Bit 15, Center 56 (-91 ~ 204) 296
4821 11:17:44.473702 ==
4822 11:17:44.477435 Dram Type= 6, Freq= 0, CH_1, rank 1
4823 11:17:44.480502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4824 11:17:44.480583 ==
4825 11:17:44.483332 DQS Delay:
4826 11:17:44.483415 DQS0 = 0, DQS1 = 0
4827 11:17:44.483479 DQM Delay:
4828 11:17:44.487147 DQM0 = 49, DQM1 = 45
4829 11:17:44.487229 DQ Delay:
4830 11:17:44.490652 DQ0 =56, DQ1 =44, DQ2 =36, DQ3 =44
4831 11:17:44.493681 DQ4 =44, DQ5 =60, DQ6 =60, DQ7 =48
4832 11:17:44.496675 DQ8 =32, DQ9 =32, DQ10 =48, DQ11 =40
4833 11:17:44.500152 DQ12 =52, DQ13 =52, DQ14 =48, DQ15 =56
4834 11:17:44.500233
4835 11:17:44.500298
4836 11:17:44.510164 [DQSOSCAuto] RK1, (LSB)MR18= 0x6c24, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 389 ps
4837 11:17:44.510247 CH1 RK1: MR19=808, MR18=6C24
4838 11:17:44.516817 CH1_RK1: MR19=0x808, MR18=0x6C24, DQSOSC=389, MR23=63, INC=173, DEC=115
4839 11:17:44.520056 [RxdqsGatingPostProcess] freq 600
4840 11:17:44.526908 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4841 11:17:44.529859 Pre-setting of DQS Precalculation
4842 11:17:44.533498 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4843 11:17:44.539750 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4844 11:17:44.549709 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4845 11:17:44.549815
4846 11:17:44.549931
4847 11:17:44.553177 [Calibration Summary] 1200 Mbps
4848 11:17:44.553257 CH 0, Rank 0
4849 11:17:44.556258 SW Impedance : PASS
4850 11:17:44.556338 DUTY Scan : NO K
4851 11:17:44.559987 ZQ Calibration : PASS
4852 11:17:44.563294 Jitter Meter : NO K
4853 11:17:44.563426 CBT Training : PASS
4854 11:17:44.566474 Write leveling : PASS
4855 11:17:44.570011 RX DQS gating : PASS
4856 11:17:44.570106 RX DQ/DQS(RDDQC) : PASS
4857 11:17:44.573328 TX DQ/DQS : PASS
4858 11:17:44.573408 RX DATLAT : PASS
4859 11:17:44.576294 RX DQ/DQS(Engine): PASS
4860 11:17:44.580003 TX OE : NO K
4861 11:17:44.580104 All Pass.
4862 11:17:44.580175
4863 11:17:44.580263 CH 0, Rank 1
4864 11:17:44.582984 SW Impedance : PASS
4865 11:17:44.586724 DUTY Scan : NO K
4866 11:17:44.586804 ZQ Calibration : PASS
4867 11:17:44.589736 Jitter Meter : NO K
4868 11:17:44.592745 CBT Training : PASS
4869 11:17:44.592825 Write leveling : PASS
4870 11:17:44.596332 RX DQS gating : PASS
4871 11:17:44.599269 RX DQ/DQS(RDDQC) : PASS
4872 11:17:44.599390 TX DQ/DQS : PASS
4873 11:17:44.603113 RX DATLAT : PASS
4874 11:17:44.605989 RX DQ/DQS(Engine): PASS
4875 11:17:44.606114 TX OE : NO K
4876 11:17:44.609399 All Pass.
4877 11:17:44.609478
4878 11:17:44.609560 CH 1, Rank 0
4879 11:17:44.612853 SW Impedance : PASS
4880 11:17:44.612933 DUTY Scan : NO K
4881 11:17:44.615815 ZQ Calibration : PASS
4882 11:17:44.619618 Jitter Meter : NO K
4883 11:17:44.619698 CBT Training : PASS
4884 11:17:44.623154 Write leveling : PASS
4885 11:17:44.626527 RX DQS gating : PASS
4886 11:17:44.626607 RX DQ/DQS(RDDQC) : PASS
4887 11:17:44.629180 TX DQ/DQS : PASS
4888 11:17:44.629260 RX DATLAT : PASS
4889 11:17:44.632825 RX DQ/DQS(Engine): PASS
4890 11:17:44.635882 TX OE : NO K
4891 11:17:44.635962 All Pass.
4892 11:17:44.636025
4893 11:17:44.636082 CH 1, Rank 1
4894 11:17:44.639611 SW Impedance : PASS
4895 11:17:44.642519 DUTY Scan : NO K
4896 11:17:44.642600 ZQ Calibration : PASS
4897 11:17:44.646242 Jitter Meter : NO K
4898 11:17:44.649333 CBT Training : PASS
4899 11:17:44.649415 Write leveling : PASS
4900 11:17:44.652816 RX DQS gating : PASS
4901 11:17:44.655831 RX DQ/DQS(RDDQC) : PASS
4902 11:17:44.655913 TX DQ/DQS : PASS
4903 11:17:44.659314 RX DATLAT : PASS
4904 11:17:44.662402 RX DQ/DQS(Engine): PASS
4905 11:17:44.662483 TX OE : NO K
4906 11:17:44.666187 All Pass.
4907 11:17:44.666268
4908 11:17:44.666331 DramC Write-DBI off
4909 11:17:44.669233 PER_BANK_REFRESH: Hybrid Mode
4910 11:17:44.669315 TX_TRACKING: ON
4911 11:17:44.679117 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4912 11:17:44.682645 [FAST_K] Save calibration result to emmc
4913 11:17:44.685962 dramc_set_vcore_voltage set vcore to 662500
4914 11:17:44.688971 Read voltage for 933, 3
4915 11:17:44.689052 Vio18 = 0
4916 11:17:44.692144 Vcore = 662500
4917 11:17:44.692225 Vdram = 0
4918 11:17:44.692288 Vddq = 0
4919 11:17:44.695729 Vmddr = 0
4920 11:17:44.698936 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4921 11:17:44.705837 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4922 11:17:44.705918 MEM_TYPE=3, freq_sel=17
4923 11:17:44.708763 sv_algorithm_assistance_LP4_1600
4924 11:17:44.712281 ============ PULL DRAM RESETB DOWN ============
4925 11:17:44.719256 ========== PULL DRAM RESETB DOWN end =========
4926 11:17:44.722649 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4927 11:17:44.725637 ===================================
4928 11:17:44.729088 LPDDR4 DRAM CONFIGURATION
4929 11:17:44.732785 ===================================
4930 11:17:44.732867 EX_ROW_EN[0] = 0x0
4931 11:17:44.735776 EX_ROW_EN[1] = 0x0
4932 11:17:44.735857 LP4Y_EN = 0x0
4933 11:17:44.738880 WORK_FSP = 0x0
4934 11:17:44.738962 WL = 0x3
4935 11:17:44.742360 RL = 0x3
4936 11:17:44.745961 BL = 0x2
4937 11:17:44.746042 RPST = 0x0
4938 11:17:44.749072 RD_PRE = 0x0
4939 11:17:44.749153 WR_PRE = 0x1
4940 11:17:44.752582 WR_PST = 0x0
4941 11:17:44.752663 DBI_WR = 0x0
4942 11:17:44.755685 DBI_RD = 0x0
4943 11:17:44.755767 OTF = 0x1
4944 11:17:44.758798 ===================================
4945 11:17:44.762352 ===================================
4946 11:17:44.765811 ANA top config
4947 11:17:44.768867 ===================================
4948 11:17:44.768948 DLL_ASYNC_EN = 0
4949 11:17:44.772655 ALL_SLAVE_EN = 1
4950 11:17:44.775650 NEW_RANK_MODE = 1
4951 11:17:44.778953 DLL_IDLE_MODE = 1
4952 11:17:44.779035 LP45_APHY_COMB_EN = 1
4953 11:17:44.782690 TX_ODT_DIS = 1
4954 11:17:44.785545 NEW_8X_MODE = 1
4955 11:17:44.789138 ===================================
4956 11:17:44.792320 ===================================
4957 11:17:44.795255 data_rate = 1866
4958 11:17:44.798977 CKR = 1
4959 11:17:44.802094 DQ_P2S_RATIO = 8
4960 11:17:44.802179 ===================================
4961 11:17:44.805867 CA_P2S_RATIO = 8
4962 11:17:44.808931 DQ_CA_OPEN = 0
4963 11:17:44.811951 DQ_SEMI_OPEN = 0
4964 11:17:44.815449 CA_SEMI_OPEN = 0
4965 11:17:44.818958 CA_FULL_RATE = 0
4966 11:17:44.819040 DQ_CKDIV4_EN = 1
4967 11:17:44.822353 CA_CKDIV4_EN = 1
4968 11:17:44.825234 CA_PREDIV_EN = 0
4969 11:17:44.828731 PH8_DLY = 0
4970 11:17:44.832276 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4971 11:17:44.835127 DQ_AAMCK_DIV = 4
4972 11:17:44.835208 CA_AAMCK_DIV = 4
4973 11:17:44.838673 CA_ADMCK_DIV = 4
4974 11:17:44.841804 DQ_TRACK_CA_EN = 0
4975 11:17:44.845515 CA_PICK = 933
4976 11:17:44.848538 CA_MCKIO = 933
4977 11:17:44.851971 MCKIO_SEMI = 0
4978 11:17:44.855202 PLL_FREQ = 3732
4979 11:17:44.858676 DQ_UI_PI_RATIO = 32
4980 11:17:44.858758 CA_UI_PI_RATIO = 0
4981 11:17:44.861799 ===================================
4982 11:17:44.864896 ===================================
4983 11:17:44.868500 memory_type:LPDDR4
4984 11:17:44.871886 GP_NUM : 10
4985 11:17:44.871966 SRAM_EN : 1
4986 11:17:44.874832 MD32_EN : 0
4987 11:17:44.878496 ===================================
4988 11:17:44.881569 [ANA_INIT] >>>>>>>>>>>>>>
4989 11:17:44.881651 <<<<<< [CONFIGURE PHASE]: ANA_TX
4990 11:17:44.888074 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4991 11:17:44.892300 ===================================
4992 11:17:44.892392 data_rate = 1866,PCW = 0X8f00
4993 11:17:44.895311 ===================================
4994 11:17:44.898401 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4995 11:17:44.905226 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4996 11:17:44.911918 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4997 11:17:44.915055 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4998 11:17:44.918823 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4999 11:17:44.921842 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5000 11:17:44.925311 [ANA_INIT] flow start
5001 11:17:44.925393 [ANA_INIT] PLL >>>>>>>>
5002 11:17:44.928323 [ANA_INIT] PLL <<<<<<<<
5003 11:17:44.931676 [ANA_INIT] MIDPI >>>>>>>>
5004 11:17:44.931759 [ANA_INIT] MIDPI <<<<<<<<
5005 11:17:44.934712 [ANA_INIT] DLL >>>>>>>>
5006 11:17:44.938470 [ANA_INIT] flow end
5007 11:17:44.941937 ============ LP4 DIFF to SE enter ============
5008 11:17:44.944993 ============ LP4 DIFF to SE exit ============
5009 11:17:44.948349 [ANA_INIT] <<<<<<<<<<<<<
5010 11:17:44.951894 [Flow] Enable top DCM control >>>>>
5011 11:17:44.954844 [Flow] Enable top DCM control <<<<<
5012 11:17:44.958307 Enable DLL master slave shuffle
5013 11:17:44.964428 ==============================================================
5014 11:17:44.964510 Gating Mode config
5015 11:17:44.971239 ==============================================================
5016 11:17:44.971322 Config description:
5017 11:17:44.981270 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5018 11:17:44.987825 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5019 11:17:44.994246 SELPH_MODE 0: By rank 1: By Phase
5020 11:17:44.997819 ==============================================================
5021 11:17:45.001388 GAT_TRACK_EN = 1
5022 11:17:45.004517 RX_GATING_MODE = 2
5023 11:17:45.007604 RX_GATING_TRACK_MODE = 2
5024 11:17:45.011171 SELPH_MODE = 1
5025 11:17:45.014469 PICG_EARLY_EN = 1
5026 11:17:45.017461 VALID_LAT_VALUE = 1
5027 11:17:45.020638 ==============================================================
5028 11:17:45.024387 Enter into Gating configuration >>>>
5029 11:17:45.027287 Exit from Gating configuration <<<<
5030 11:17:45.030739 Enter into DVFS_PRE_config >>>>>
5031 11:17:45.043930 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5032 11:17:45.047446 Exit from DVFS_PRE_config <<<<<
5033 11:17:45.050919 Enter into PICG configuration >>>>
5034 11:17:45.054112 Exit from PICG configuration <<<<
5035 11:17:45.054195 [RX_INPUT] configuration >>>>>
5036 11:17:45.057840 [RX_INPUT] configuration <<<<<
5037 11:17:45.064193 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5038 11:17:45.067659 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5039 11:17:45.074302 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5040 11:17:45.080653 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5041 11:17:45.087351 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5042 11:17:45.094063 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5043 11:17:45.097647 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5044 11:17:45.100632 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5045 11:17:45.104465 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5046 11:17:45.110549 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5047 11:17:45.114286 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5048 11:17:45.117169 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5049 11:17:45.120959 ===================================
5050 11:17:45.124273 LPDDR4 DRAM CONFIGURATION
5051 11:17:45.127221 ===================================
5052 11:17:45.130830 EX_ROW_EN[0] = 0x0
5053 11:17:45.130913 EX_ROW_EN[1] = 0x0
5054 11:17:45.134327 LP4Y_EN = 0x0
5055 11:17:45.134408 WORK_FSP = 0x0
5056 11:17:45.137162 WL = 0x3
5057 11:17:45.137244 RL = 0x3
5058 11:17:45.140753 BL = 0x2
5059 11:17:45.140835 RPST = 0x0
5060 11:17:45.144374 RD_PRE = 0x0
5061 11:17:45.144457 WR_PRE = 0x1
5062 11:17:45.147371 WR_PST = 0x0
5063 11:17:45.147453 DBI_WR = 0x0
5064 11:17:45.150977 DBI_RD = 0x0
5065 11:17:45.151058 OTF = 0x1
5066 11:17:45.153847 ===================================
5067 11:17:45.160462 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5068 11:17:45.164306 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5069 11:17:45.167224 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5070 11:17:45.170912 ===================================
5071 11:17:45.173951 LPDDR4 DRAM CONFIGURATION
5072 11:17:45.176861 ===================================
5073 11:17:45.180574 EX_ROW_EN[0] = 0x10
5074 11:17:45.180657 EX_ROW_EN[1] = 0x0
5075 11:17:45.183635 LP4Y_EN = 0x0
5076 11:17:45.183717 WORK_FSP = 0x0
5077 11:17:45.187289 WL = 0x3
5078 11:17:45.187377 RL = 0x3
5079 11:17:45.190304 BL = 0x2
5080 11:17:45.190386 RPST = 0x0
5081 11:17:45.193891 RD_PRE = 0x0
5082 11:17:45.193973 WR_PRE = 0x1
5083 11:17:45.196964 WR_PST = 0x0
5084 11:17:45.197047 DBI_WR = 0x0
5085 11:17:45.200102 DBI_RD = 0x0
5086 11:17:45.200184 OTF = 0x1
5087 11:17:45.203886 ===================================
5088 11:17:45.209971 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5089 11:17:45.214899 nWR fixed to 30
5090 11:17:45.218102 [ModeRegInit_LP4] CH0 RK0
5091 11:17:45.218184 [ModeRegInit_LP4] CH0 RK1
5092 11:17:45.221296 [ModeRegInit_LP4] CH1 RK0
5093 11:17:45.224829 [ModeRegInit_LP4] CH1 RK1
5094 11:17:45.224911 match AC timing 9
5095 11:17:45.231928 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5096 11:17:45.234837 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5097 11:17:45.238314 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5098 11:17:45.244770 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5099 11:17:45.247837 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5100 11:17:45.247919 ==
5101 11:17:45.251303 Dram Type= 6, Freq= 0, CH_0, rank 0
5102 11:17:45.254926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5103 11:17:45.255025 ==
5104 11:17:45.261512 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5105 11:17:45.268152 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5106 11:17:45.271900 [CA 0] Center 37 (6~68) winsize 63
5107 11:17:45.274805 [CA 1] Center 37 (6~68) winsize 63
5108 11:17:45.278240 [CA 2] Center 34 (4~65) winsize 62
5109 11:17:45.281301 [CA 3] Center 34 (3~65) winsize 63
5110 11:17:45.284982 [CA 4] Center 33 (3~64) winsize 62
5111 11:17:45.287953 [CA 5] Center 32 (2~62) winsize 61
5112 11:17:45.288035
5113 11:17:45.291815 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5114 11:17:45.291897
5115 11:17:45.294804 [CATrainingPosCal] consider 1 rank data
5116 11:17:45.298532 u2DelayCellTimex100 = 270/100 ps
5117 11:17:45.301667 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5118 11:17:45.305243 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5119 11:17:45.308244 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5120 11:17:45.311298 CA3 delay=34 (3~65),Diff = 2 PI (12 cell)
5121 11:17:45.314524 CA4 delay=33 (3~64),Diff = 1 PI (6 cell)
5122 11:17:45.317897 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5123 11:17:45.317979
5124 11:17:45.324712 CA PerBit enable=1, Macro0, CA PI delay=32
5125 11:17:45.324793
5126 11:17:45.327788 [CBTSetCACLKResult] CA Dly = 32
5127 11:17:45.327869 CS Dly: 5 (0~36)
5128 11:17:45.327934 ==
5129 11:17:45.331029 Dram Type= 6, Freq= 0, CH_0, rank 1
5130 11:17:45.334645 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5131 11:17:45.334727 ==
5132 11:17:45.341039 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5133 11:17:45.348084 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5134 11:17:45.350878 [CA 0] Center 37 (6~68) winsize 63
5135 11:17:45.354371 [CA 1] Center 37 (6~68) winsize 63
5136 11:17:45.357405 [CA 2] Center 34 (4~65) winsize 62
5137 11:17:45.361253 [CA 3] Center 34 (4~65) winsize 62
5138 11:17:45.364609 [CA 4] Center 33 (3~63) winsize 61
5139 11:17:45.367607 [CA 5] Center 32 (2~62) winsize 61
5140 11:17:45.367715
5141 11:17:45.371263 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5142 11:17:45.371401
5143 11:17:45.374395 [CATrainingPosCal] consider 2 rank data
5144 11:17:45.378045 u2DelayCellTimex100 = 270/100 ps
5145 11:17:45.381354 CA0 delay=37 (6~68),Diff = 5 PI (31 cell)
5146 11:17:45.384414 CA1 delay=37 (6~68),Diff = 5 PI (31 cell)
5147 11:17:45.387695 CA2 delay=34 (4~65),Diff = 2 PI (12 cell)
5148 11:17:45.391089 CA3 delay=34 (4~65),Diff = 2 PI (12 cell)
5149 11:17:45.394235 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5150 11:17:45.401113 CA5 delay=32 (2~62),Diff = 0 PI (0 cell)
5151 11:17:45.401214
5152 11:17:45.404235 CA PerBit enable=1, Macro0, CA PI delay=32
5153 11:17:45.404324
5154 11:17:45.407875 [CBTSetCACLKResult] CA Dly = 32
5155 11:17:45.407974 CS Dly: 5 (0~37)
5156 11:17:45.408041
5157 11:17:45.410700 ----->DramcWriteLeveling(PI) begin...
5158 11:17:45.410782 ==
5159 11:17:45.414433 Dram Type= 6, Freq= 0, CH_0, rank 0
5160 11:17:45.421157 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5161 11:17:45.421271 ==
5162 11:17:45.424162 Write leveling (Byte 0): 32 => 32
5163 11:17:45.424243 Write leveling (Byte 1): 30 => 30
5164 11:17:45.427593 DramcWriteLeveling(PI) end<-----
5165 11:17:45.427674
5166 11:17:45.427738 ==
5167 11:17:45.430784 Dram Type= 6, Freq= 0, CH_0, rank 0
5168 11:17:45.437423 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5169 11:17:45.437523 ==
5170 11:17:45.441206 [Gating] SW mode calibration
5171 11:17:45.447779 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5172 11:17:45.450989 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5173 11:17:45.457594 0 14 0 | B1->B0 | 2828 3434 | 0 1 | (0 0) (1 1)
5174 11:17:45.460675 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5175 11:17:45.464350 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5176 11:17:45.470827 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5177 11:17:45.473677 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5178 11:17:45.477350 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5179 11:17:45.483905 0 14 24 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
5180 11:17:45.487563 0 14 28 | B1->B0 | 3333 2727 | 1 0 | (1 0) (0 0)
5181 11:17:45.490580 0 15 0 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (1 0)
5182 11:17:45.497042 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5183 11:17:45.500701 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5184 11:17:45.504292 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5185 11:17:45.507254 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5186 11:17:45.514133 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5187 11:17:45.517325 0 15 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
5188 11:17:45.520727 0 15 28 | B1->B0 | 2525 3d3d | 0 0 | (0 0) (0 0)
5189 11:17:45.527291 1 0 0 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
5190 11:17:45.530364 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5191 11:17:45.533728 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5192 11:17:45.540379 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5193 11:17:45.543556 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5194 11:17:45.546851 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5195 11:17:45.553610 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5196 11:17:45.556709 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5197 11:17:45.560307 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5198 11:17:45.567007 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5199 11:17:45.570136 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5200 11:17:45.573677 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5201 11:17:45.580599 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5202 11:17:45.583566 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5203 11:17:45.587287 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5204 11:17:45.593349 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5205 11:17:45.597072 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5206 11:17:45.600152 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5207 11:17:45.606816 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5208 11:17:45.610387 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5209 11:17:45.613557 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5210 11:17:45.620279 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5211 11:17:45.623696 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5212 11:17:45.626654 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5213 11:17:45.630437 Total UI for P1: 0, mck2ui 16
5214 11:17:45.633488 best dqsien dly found for B0: ( 1, 2, 24)
5215 11:17:45.636694 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5216 11:17:45.640614 Total UI for P1: 0, mck2ui 16
5217 11:17:45.643618 best dqsien dly found for B1: ( 1, 2, 28)
5218 11:17:45.647254 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5219 11:17:45.653491 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5220 11:17:45.653572
5221 11:17:45.656659 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5222 11:17:45.660260 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5223 11:17:45.663252 [Gating] SW calibration Done
5224 11:17:45.663359 ==
5225 11:17:45.666626 Dram Type= 6, Freq= 0, CH_0, rank 0
5226 11:17:45.670162 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5227 11:17:45.670243 ==
5228 11:17:45.670308 RX Vref Scan: 0
5229 11:17:45.673233
5230 11:17:45.673314 RX Vref 0 -> 0, step: 1
5231 11:17:45.673377
5232 11:17:45.676689 RX Delay -80 -> 252, step: 8
5233 11:17:45.680272 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5234 11:17:45.683436 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5235 11:17:45.689876 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5236 11:17:45.693293 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5237 11:17:45.696582 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5238 11:17:45.700225 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5239 11:17:45.703471 iDelay=208, Bit 6, Center 115 (24 ~ 207) 184
5240 11:17:45.707140 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5241 11:17:45.713118 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5242 11:17:45.716503 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5243 11:17:45.719948 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5244 11:17:45.723611 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5245 11:17:45.726533 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5246 11:17:45.729881 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5247 11:17:45.736513 iDelay=208, Bit 14, Center 107 (16 ~ 199) 184
5248 11:17:45.740412 iDelay=208, Bit 15, Center 99 (8 ~ 191) 184
5249 11:17:45.740493 ==
5250 11:17:45.743439 Dram Type= 6, Freq= 0, CH_0, rank 0
5251 11:17:45.746631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5252 11:17:45.746712 ==
5253 11:17:45.749682 DQS Delay:
5254 11:17:45.749762 DQS0 = 0, DQS1 = 0
5255 11:17:45.749825 DQM Delay:
5256 11:17:45.753483 DQM0 = 104, DQM1 = 96
5257 11:17:45.753563 DQ Delay:
5258 11:17:45.756780 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5259 11:17:45.760076 DQ4 =107, DQ5 =91, DQ6 =115, DQ7 =115
5260 11:17:45.762863 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =91
5261 11:17:45.766501 DQ12 =99, DQ13 =103, DQ14 =107, DQ15 =99
5262 11:17:45.766581
5263 11:17:45.766645
5264 11:17:45.770053 ==
5265 11:17:45.770134 Dram Type= 6, Freq= 0, CH_0, rank 0
5266 11:17:45.776497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5267 11:17:45.776578 ==
5268 11:17:45.776642
5269 11:17:45.776699
5270 11:17:45.779543 TX Vref Scan disable
5271 11:17:45.779623 == TX Byte 0 ==
5272 11:17:45.782971 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5273 11:17:45.789544 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5274 11:17:45.789625 == TX Byte 1 ==
5275 11:17:45.793134 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5276 11:17:45.800076 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5277 11:17:45.800161 ==
5278 11:17:45.803273 Dram Type= 6, Freq= 0, CH_0, rank 0
5279 11:17:45.806310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5280 11:17:45.806391 ==
5281 11:17:45.806454
5282 11:17:45.806511
5283 11:17:45.809438 TX Vref Scan disable
5284 11:17:45.812696 == TX Byte 0 ==
5285 11:17:45.816233 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5286 11:17:45.819462 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5287 11:17:45.822716 == TX Byte 1 ==
5288 11:17:45.825915 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5289 11:17:45.829212 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5290 11:17:45.829293
5291 11:17:45.832911 [DATLAT]
5292 11:17:45.832995 Freq=933, CH0 RK0
5293 11:17:45.833059
5294 11:17:45.836211 DATLAT Default: 0xd
5295 11:17:45.836291 0, 0xFFFF, sum = 0
5296 11:17:45.839522 1, 0xFFFF, sum = 0
5297 11:17:45.839605 2, 0xFFFF, sum = 0
5298 11:17:45.843003 3, 0xFFFF, sum = 0
5299 11:17:45.843085 4, 0xFFFF, sum = 0
5300 11:17:45.846474 5, 0xFFFF, sum = 0
5301 11:17:45.846556 6, 0xFFFF, sum = 0
5302 11:17:45.849577 7, 0xFFFF, sum = 0
5303 11:17:45.849659 8, 0xFFFF, sum = 0
5304 11:17:45.852727 9, 0xFFFF, sum = 0
5305 11:17:45.852809 10, 0x0, sum = 1
5306 11:17:45.855785 11, 0x0, sum = 2
5307 11:17:45.855866 12, 0x0, sum = 3
5308 11:17:45.859568 13, 0x0, sum = 4
5309 11:17:45.859650 best_step = 11
5310 11:17:45.859714
5311 11:17:45.859771 ==
5312 11:17:45.862756 Dram Type= 6, Freq= 0, CH_0, rank 0
5313 11:17:45.865907 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5314 11:17:45.869088 ==
5315 11:17:45.869168 RX Vref Scan: 1
5316 11:17:45.869232
5317 11:17:45.872708 RX Vref 0 -> 0, step: 1
5318 11:17:45.872789
5319 11:17:45.872852 RX Delay -45 -> 252, step: 4
5320 11:17:45.876324
5321 11:17:45.876404 Set Vref, RX VrefLevel [Byte0]: 54
5322 11:17:45.879275 [Byte1]: 55
5323 11:17:45.884192
5324 11:17:45.884272 Final RX Vref Byte 0 = 54 to rank0
5325 11:17:45.887709 Final RX Vref Byte 1 = 55 to rank0
5326 11:17:45.890866 Final RX Vref Byte 0 = 54 to rank1
5327 11:17:45.894358 Final RX Vref Byte 1 = 55 to rank1==
5328 11:17:45.897444 Dram Type= 6, Freq= 0, CH_0, rank 0
5329 11:17:45.904256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5330 11:17:45.904338 ==
5331 11:17:45.904403 DQS Delay:
5332 11:17:45.904462 DQS0 = 0, DQS1 = 0
5333 11:17:45.907322 DQM Delay:
5334 11:17:45.907444 DQM0 = 104, DQM1 = 97
5335 11:17:45.911065 DQ Delay:
5336 11:17:45.914393 DQ0 =104, DQ1 =104, DQ2 =102, DQ3 =102
5337 11:17:45.917378 DQ4 =104, DQ5 =96, DQ6 =112, DQ7 =110
5338 11:17:45.921094 DQ8 =86, DQ9 =88, DQ10 =96, DQ11 =90
5339 11:17:45.924186 DQ12 =102, DQ13 =102, DQ14 =108, DQ15 =104
5340 11:17:45.924268
5341 11:17:45.924331
5342 11:17:45.930768 [DQSOSCAuto] RK0, (LSB)MR18= 0x322a, (MSB)MR19= 0x505, tDQSOscB0 = 408 ps tDQSOscB1 = 406 ps
5343 11:17:45.934302 CH0 RK0: MR19=505, MR18=322A
5344 11:17:45.940961 CH0_RK0: MR19=0x505, MR18=0x322A, DQSOSC=406, MR23=63, INC=65, DEC=43
5345 11:17:45.941044
5346 11:17:45.944525 ----->DramcWriteLeveling(PI) begin...
5347 11:17:45.944608 ==
5348 11:17:45.947299 Dram Type= 6, Freq= 0, CH_0, rank 1
5349 11:17:45.951107 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5350 11:17:45.951189 ==
5351 11:17:45.954071 Write leveling (Byte 0): 34 => 34
5352 11:17:45.957294 Write leveling (Byte 1): 29 => 29
5353 11:17:45.961286 DramcWriteLeveling(PI) end<-----
5354 11:17:45.961367
5355 11:17:45.961432 ==
5356 11:17:45.964205 Dram Type= 6, Freq= 0, CH_0, rank 1
5357 11:17:45.967218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5358 11:17:45.970984 ==
5359 11:17:45.971066 [Gating] SW mode calibration
5360 11:17:45.981130 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5361 11:17:45.983893 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5362 11:17:45.987313 0 14 0 | B1->B0 | 3434 3131 | 0 0 | (0 0) (0 0)
5363 11:17:45.993862 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5364 11:17:45.997629 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5365 11:17:46.000480 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5366 11:17:46.007012 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5367 11:17:46.010596 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5368 11:17:46.013821 0 14 24 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
5369 11:17:46.020600 0 14 28 | B1->B0 | 2d2d 2d2d | 0 0 | (0 0) (0 1)
5370 11:17:46.023570 0 15 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (1 0)
5371 11:17:46.027403 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5372 11:17:46.033683 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5373 11:17:46.037268 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5374 11:17:46.040180 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5375 11:17:46.047124 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5376 11:17:46.050251 0 15 24 | B1->B0 | 2424 2423 | 0 1 | (0 0) (0 0)
5377 11:17:46.053571 0 15 28 | B1->B0 | 3939 3938 | 1 1 | (0 0) (0 0)
5378 11:17:46.060239 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5379 11:17:46.064031 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5380 11:17:46.066920 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5381 11:17:46.073742 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5382 11:17:46.076912 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5383 11:17:46.080024 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5384 11:17:46.086818 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5385 11:17:46.090378 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5386 11:17:46.093385 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5387 11:17:46.099952 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5388 11:17:46.103465 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5389 11:17:46.107019 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5390 11:17:46.110162 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5391 11:17:46.117136 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5392 11:17:46.120237 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5393 11:17:46.123497 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5394 11:17:46.130485 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5395 11:17:46.133661 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5396 11:17:46.136798 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5397 11:17:46.143214 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5398 11:17:46.146794 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5399 11:17:46.149682 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5400 11:17:46.156704 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5401 11:17:46.160430 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5402 11:17:46.163316 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5403 11:17:46.166585 Total UI for P1: 0, mck2ui 16
5404 11:17:46.169851 best dqsien dly found for B0: ( 1, 2, 28)
5405 11:17:46.173376 Total UI for P1: 0, mck2ui 16
5406 11:17:46.176559 best dqsien dly found for B1: ( 1, 2, 30)
5407 11:17:46.179678 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5408 11:17:46.183637 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5409 11:17:46.183721
5410 11:17:46.189556 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5411 11:17:46.193024 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5412 11:17:46.196546 [Gating] SW calibration Done
5413 11:17:46.196665 ==
5414 11:17:46.199491 Dram Type= 6, Freq= 0, CH_0, rank 1
5415 11:17:46.203143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5416 11:17:46.203265 ==
5417 11:17:46.203372 RX Vref Scan: 0
5418 11:17:46.203434
5419 11:17:46.206285 RX Vref 0 -> 0, step: 1
5420 11:17:46.206373
5421 11:17:46.209924 RX Delay -80 -> 252, step: 8
5422 11:17:46.213589 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5423 11:17:46.216614 iDelay=208, Bit 1, Center 107 (16 ~ 199) 184
5424 11:17:46.220097 iDelay=208, Bit 2, Center 99 (8 ~ 191) 184
5425 11:17:46.226194 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5426 11:17:46.229463 iDelay=208, Bit 4, Center 107 (16 ~ 199) 184
5427 11:17:46.233142 iDelay=208, Bit 5, Center 95 (0 ~ 191) 192
5428 11:17:46.236652 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5429 11:17:46.239793 iDelay=208, Bit 7, Center 115 (24 ~ 207) 184
5430 11:17:46.242924 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5431 11:17:46.249758 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5432 11:17:46.252908 iDelay=208, Bit 10, Center 95 (8 ~ 183) 176
5433 11:17:46.256168 iDelay=208, Bit 11, Center 87 (0 ~ 175) 176
5434 11:17:46.259626 iDelay=208, Bit 12, Center 99 (8 ~ 191) 184
5435 11:17:46.262676 iDelay=208, Bit 13, Center 99 (8 ~ 191) 184
5436 11:17:46.266179 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5437 11:17:46.272851 iDelay=208, Bit 15, Center 103 (16 ~ 191) 176
5438 11:17:46.272934 ==
5439 11:17:46.276635 Dram Type= 6, Freq= 0, CH_0, rank 1
5440 11:17:46.279535 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5441 11:17:46.279619 ==
5442 11:17:46.279685 DQS Delay:
5443 11:17:46.282874 DQS0 = 0, DQS1 = 0
5444 11:17:46.282956 DQM Delay:
5445 11:17:46.286313 DQM0 = 104, DQM1 = 94
5446 11:17:46.286421 DQ Delay:
5447 11:17:46.289490 DQ0 =103, DQ1 =107, DQ2 =99, DQ3 =99
5448 11:17:46.292726 DQ4 =107, DQ5 =95, DQ6 =111, DQ7 =115
5449 11:17:46.295891 DQ8 =87, DQ9 =87, DQ10 =95, DQ11 =87
5450 11:17:46.299578 DQ12 =99, DQ13 =99, DQ14 =99, DQ15 =103
5451 11:17:46.299671
5452 11:17:46.299736
5453 11:17:46.299795 ==
5454 11:17:46.302616 Dram Type= 6, Freq= 0, CH_0, rank 1
5455 11:17:46.309471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5456 11:17:46.309553 ==
5457 11:17:46.309618
5458 11:17:46.309677
5459 11:17:46.309735 TX Vref Scan disable
5460 11:17:46.313113 == TX Byte 0 ==
5461 11:17:46.316289 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5462 11:17:46.319278 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5463 11:17:46.322571 == TX Byte 1 ==
5464 11:17:46.326142 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5465 11:17:46.329447 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5466 11:17:46.332759 ==
5467 11:17:46.336472 Dram Type= 6, Freq= 0, CH_0, rank 1
5468 11:17:46.339775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5469 11:17:46.339882 ==
5470 11:17:46.339969
5471 11:17:46.340030
5472 11:17:46.343092 TX Vref Scan disable
5473 11:17:46.343181 == TX Byte 0 ==
5474 11:17:46.349481 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5475 11:17:46.352666 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5476 11:17:46.352756 == TX Byte 1 ==
5477 11:17:46.359716 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5478 11:17:46.363015 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5479 11:17:46.363157
5480 11:17:46.363250 [DATLAT]
5481 11:17:46.366520 Freq=933, CH0 RK1
5482 11:17:46.366615
5483 11:17:46.366681 DATLAT Default: 0xb
5484 11:17:46.369381 0, 0xFFFF, sum = 0
5485 11:17:46.369464 1, 0xFFFF, sum = 0
5486 11:17:46.372957 2, 0xFFFF, sum = 0
5487 11:17:46.373039 3, 0xFFFF, sum = 0
5488 11:17:46.376452 4, 0xFFFF, sum = 0
5489 11:17:46.376536 5, 0xFFFF, sum = 0
5490 11:17:46.379296 6, 0xFFFF, sum = 0
5491 11:17:46.379419 7, 0xFFFF, sum = 0
5492 11:17:46.383266 8, 0xFFFF, sum = 0
5493 11:17:46.383371 9, 0xFFFF, sum = 0
5494 11:17:46.386337 10, 0x0, sum = 1
5495 11:17:46.386420 11, 0x0, sum = 2
5496 11:17:46.389468 12, 0x0, sum = 3
5497 11:17:46.389551 13, 0x0, sum = 4
5498 11:17:46.392737 best_step = 11
5499 11:17:46.392818
5500 11:17:46.392919 ==
5501 11:17:46.395976 Dram Type= 6, Freq= 0, CH_0, rank 1
5502 11:17:46.399226 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5503 11:17:46.399308 ==
5504 11:17:46.402957 RX Vref Scan: 0
5505 11:17:46.403037
5506 11:17:46.403102 RX Vref 0 -> 0, step: 1
5507 11:17:46.403160
5508 11:17:46.406173 RX Delay -45 -> 252, step: 4
5509 11:17:46.413108 iDelay=199, Bit 0, Center 102 (15 ~ 190) 176
5510 11:17:46.416607 iDelay=199, Bit 1, Center 108 (23 ~ 194) 172
5511 11:17:46.419700 iDelay=199, Bit 2, Center 102 (15 ~ 190) 176
5512 11:17:46.423104 iDelay=199, Bit 3, Center 102 (15 ~ 190) 176
5513 11:17:46.426702 iDelay=199, Bit 4, Center 106 (19 ~ 194) 176
5514 11:17:46.433045 iDelay=199, Bit 5, Center 98 (11 ~ 186) 176
5515 11:17:46.436676 iDelay=199, Bit 6, Center 110 (27 ~ 194) 168
5516 11:17:46.439610 iDelay=199, Bit 7, Center 112 (27 ~ 198) 172
5517 11:17:46.442900 iDelay=199, Bit 8, Center 88 (7 ~ 170) 164
5518 11:17:46.446545 iDelay=199, Bit 9, Center 86 (3 ~ 170) 168
5519 11:17:46.449981 iDelay=199, Bit 10, Center 94 (11 ~ 178) 168
5520 11:17:46.456215 iDelay=199, Bit 11, Center 92 (11 ~ 174) 164
5521 11:17:46.459554 iDelay=199, Bit 12, Center 100 (19 ~ 182) 164
5522 11:17:46.463274 iDelay=199, Bit 13, Center 100 (15 ~ 186) 172
5523 11:17:46.466531 iDelay=199, Bit 14, Center 106 (23 ~ 190) 168
5524 11:17:46.473187 iDelay=199, Bit 15, Center 104 (23 ~ 186) 164
5525 11:17:46.473277 ==
5526 11:17:46.476017 Dram Type= 6, Freq= 0, CH_0, rank 1
5527 11:17:46.479711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5528 11:17:46.479795 ==
5529 11:17:46.479915 DQS Delay:
5530 11:17:46.483079 DQS0 = 0, DQS1 = 0
5531 11:17:46.483163 DQM Delay:
5532 11:17:46.486641 DQM0 = 105, DQM1 = 96
5533 11:17:46.486724 DQ Delay:
5534 11:17:46.489626 DQ0 =102, DQ1 =108, DQ2 =102, DQ3 =102
5535 11:17:46.492665 DQ4 =106, DQ5 =98, DQ6 =110, DQ7 =112
5536 11:17:46.496686 DQ8 =88, DQ9 =86, DQ10 =94, DQ11 =92
5537 11:17:46.499705 DQ12 =100, DQ13 =100, DQ14 =106, DQ15 =104
5538 11:17:46.499789
5539 11:17:46.499893
5540 11:17:46.509551 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c04, (MSB)MR19= 0x505, tDQSOscB0 = 420 ps tDQSOscB1 = 408 ps
5541 11:17:46.509637 CH0 RK1: MR19=505, MR18=2C04
5542 11:17:46.516574 CH0_RK1: MR19=0x505, MR18=0x2C04, DQSOSC=408, MR23=63, INC=65, DEC=43
5543 11:17:46.519491 [RxdqsGatingPostProcess] freq 933
5544 11:17:46.526521 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5545 11:17:46.529400 best DQS0 dly(2T, 0.5T) = (0, 10)
5546 11:17:46.533195 best DQS1 dly(2T, 0.5T) = (0, 10)
5547 11:17:46.536197 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5548 11:17:46.539760 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5549 11:17:46.542696 best DQS0 dly(2T, 0.5T) = (0, 10)
5550 11:17:46.545994 best DQS1 dly(2T, 0.5T) = (0, 10)
5551 11:17:46.549227 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5552 11:17:46.552516 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5553 11:17:46.552626 Pre-setting of DQS Precalculation
5554 11:17:46.559281 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5555 11:17:46.559416 ==
5556 11:17:46.562880 Dram Type= 6, Freq= 0, CH_1, rank 0
5557 11:17:46.565941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5558 11:17:46.566074 ==
5559 11:17:46.572659 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5560 11:17:46.578862 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5561 11:17:46.582419 [CA 0] Center 36 (6~67) winsize 62
5562 11:17:46.585903 [CA 1] Center 36 (6~67) winsize 62
5563 11:17:46.589301 [CA 2] Center 34 (4~65) winsize 62
5564 11:17:46.592408 [CA 3] Center 34 (4~65) winsize 62
5565 11:17:46.596060 [CA 4] Center 34 (4~65) winsize 62
5566 11:17:46.599028 [CA 5] Center 33 (3~64) winsize 62
5567 11:17:46.599106
5568 11:17:46.602186 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5569 11:17:46.602263
5570 11:17:46.605588 [CATrainingPosCal] consider 1 rank data
5571 11:17:46.608806 u2DelayCellTimex100 = 270/100 ps
5572 11:17:46.612622 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5573 11:17:46.615706 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5574 11:17:46.618914 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5575 11:17:46.621951 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5576 11:17:46.625231 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5577 11:17:46.628830 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5578 11:17:46.628913
5579 11:17:46.635313 CA PerBit enable=1, Macro0, CA PI delay=33
5580 11:17:46.635451
5581 11:17:46.638934 [CBTSetCACLKResult] CA Dly = 33
5582 11:17:46.639017 CS Dly: 6 (0~37)
5583 11:17:46.639082 ==
5584 11:17:46.641923 Dram Type= 6, Freq= 0, CH_1, rank 1
5585 11:17:46.645573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5586 11:17:46.645657 ==
5587 11:17:46.652320 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5588 11:17:46.658862 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5589 11:17:46.662000 [CA 0] Center 36 (6~67) winsize 62
5590 11:17:46.665422 [CA 1] Center 37 (7~68) winsize 62
5591 11:17:46.668572 [CA 2] Center 35 (5~66) winsize 62
5592 11:17:46.672509 [CA 3] Center 34 (4~65) winsize 62
5593 11:17:46.675744 [CA 4] Center 34 (4~65) winsize 62
5594 11:17:46.678796 [CA 5] Center 34 (4~64) winsize 61
5595 11:17:46.678878
5596 11:17:46.681887 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5597 11:17:46.681970
5598 11:17:46.685100 [CATrainingPosCal] consider 2 rank data
5599 11:17:46.688895 u2DelayCellTimex100 = 270/100 ps
5600 11:17:46.691892 CA0 delay=36 (6~67),Diff = 2 PI (12 cell)
5601 11:17:46.695473 CA1 delay=37 (7~67),Diff = 3 PI (18 cell)
5602 11:17:46.698384 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5603 11:17:46.701918 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
5604 11:17:46.705259 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5605 11:17:46.708673 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5606 11:17:46.711833
5607 11:17:46.715449 CA PerBit enable=1, Macro0, CA PI delay=34
5608 11:17:46.715531
5609 11:17:46.718712 [CBTSetCACLKResult] CA Dly = 34
5610 11:17:46.718794 CS Dly: 7 (0~40)
5611 11:17:46.718859
5612 11:17:46.721824 ----->DramcWriteLeveling(PI) begin...
5613 11:17:46.721907 ==
5614 11:17:46.724841 Dram Type= 6, Freq= 0, CH_1, rank 0
5615 11:17:46.728653 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5616 11:17:46.731694 ==
5617 11:17:46.731775 Write leveling (Byte 0): 27 => 27
5618 11:17:46.735207 Write leveling (Byte 1): 28 => 28
5619 11:17:46.738323 DramcWriteLeveling(PI) end<-----
5620 11:17:46.738404
5621 11:17:46.738467 ==
5622 11:17:46.742004 Dram Type= 6, Freq= 0, CH_1, rank 0
5623 11:17:46.748051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5624 11:17:46.748160 ==
5625 11:17:46.751471 [Gating] SW mode calibration
5626 11:17:46.758121 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5627 11:17:46.762143 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5628 11:17:46.768371 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5629 11:17:46.771301 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5630 11:17:46.774754 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5631 11:17:46.781269 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5632 11:17:46.785273 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5633 11:17:46.788325 0 14 20 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5634 11:17:46.791681 0 14 24 | B1->B0 | 3434 2b2b | 0 0 | (0 1) (0 0)
5635 11:17:46.797874 0 14 28 | B1->B0 | 2a2a 2323 | 0 0 | (1 1) (0 0)
5636 11:17:46.801539 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5637 11:17:46.805302 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5638 11:17:46.811513 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5639 11:17:46.814631 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5640 11:17:46.818189 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5641 11:17:46.824559 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5642 11:17:46.827854 0 15 24 | B1->B0 | 2323 3232 | 1 1 | (0 0) (0 0)
5643 11:17:46.831224 0 15 28 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
5644 11:17:46.838046 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5645 11:17:46.841097 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5646 11:17:46.844364 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5647 11:17:46.850934 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5648 11:17:46.854465 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5649 11:17:46.857804 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5650 11:17:46.864179 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5651 11:17:46.868177 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5652 11:17:46.871244 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5653 11:17:46.877421 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5654 11:17:46.881126 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5655 11:17:46.884151 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5656 11:17:46.890486 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5657 11:17:46.894245 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5658 11:17:46.897300 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5659 11:17:46.904152 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5660 11:17:46.907614 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5661 11:17:46.910721 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5662 11:17:46.917529 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5663 11:17:46.920601 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5664 11:17:46.924306 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5665 11:17:46.930438 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5666 11:17:46.933658 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5667 11:17:46.936928 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5668 11:17:46.940434 Total UI for P1: 0, mck2ui 16
5669 11:17:46.943821 best dqsien dly found for B1: ( 1, 2, 24)
5670 11:17:46.950246 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5671 11:17:46.950328 Total UI for P1: 0, mck2ui 16
5672 11:17:46.954049 best dqsien dly found for B0: ( 1, 2, 28)
5673 11:17:46.960643 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5674 11:17:46.964099 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
5675 11:17:46.964193
5676 11:17:46.967021 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5677 11:17:46.970493 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
5678 11:17:46.974245 [Gating] SW calibration Done
5679 11:17:46.974328 ==
5680 11:17:46.977255 Dram Type= 6, Freq= 0, CH_1, rank 0
5681 11:17:46.980350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5682 11:17:46.980433 ==
5683 11:17:46.984114 RX Vref Scan: 0
5684 11:17:46.984195
5685 11:17:46.984259 RX Vref 0 -> 0, step: 1
5686 11:17:46.984319
5687 11:17:46.987227 RX Delay -80 -> 252, step: 8
5688 11:17:46.990406 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5689 11:17:46.993688 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5690 11:17:47.000559 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5691 11:17:47.004518 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5692 11:17:47.007155 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5693 11:17:47.010795 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5694 11:17:47.013953 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5695 11:17:47.017876 iDelay=208, Bit 7, Center 103 (8 ~ 199) 192
5696 11:17:47.020466 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5697 11:17:47.027752 iDelay=208, Bit 9, Center 87 (0 ~ 175) 176
5698 11:17:47.030551 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5699 11:17:47.034104 iDelay=208, Bit 11, Center 95 (8 ~ 183) 176
5700 11:17:47.037401 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5701 11:17:47.040594 iDelay=208, Bit 13, Center 103 (16 ~ 191) 176
5702 11:17:47.047261 iDelay=208, Bit 14, Center 103 (16 ~ 191) 176
5703 11:17:47.050634 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5704 11:17:47.050716 ==
5705 11:17:47.054163 Dram Type= 6, Freq= 0, CH_1, rank 0
5706 11:17:47.057019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5707 11:17:47.057127 ==
5708 11:17:47.060670 DQS Delay:
5709 11:17:47.060751 DQS0 = 0, DQS1 = 0
5710 11:17:47.060815 DQM Delay:
5711 11:17:47.064140 DQM0 = 102, DQM1 = 98
5712 11:17:47.064222 DQ Delay:
5713 11:17:47.067246 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5714 11:17:47.070705 DQ4 =99, DQ5 =115, DQ6 =111, DQ7 =103
5715 11:17:47.073803 DQ8 =87, DQ9 =87, DQ10 =99, DQ11 =95
5716 11:17:47.077329 DQ12 =107, DQ13 =103, DQ14 =103, DQ15 =107
5717 11:17:47.077411
5718 11:17:47.077485
5719 11:17:47.080342 ==
5720 11:17:47.084133 Dram Type= 6, Freq= 0, CH_1, rank 0
5721 11:17:47.087133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5722 11:17:47.087241 ==
5723 11:17:47.087341
5724 11:17:47.087441
5725 11:17:47.090397 TX Vref Scan disable
5726 11:17:47.090480 == TX Byte 0 ==
5727 11:17:47.094026 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5728 11:17:47.100187 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5729 11:17:47.100270 == TX Byte 1 ==
5730 11:17:47.106937 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5731 11:17:47.110168 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5732 11:17:47.110250 ==
5733 11:17:47.113365 Dram Type= 6, Freq= 0, CH_1, rank 0
5734 11:17:47.117006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5735 11:17:47.117089 ==
5736 11:17:47.117154
5737 11:17:47.117215
5738 11:17:47.120139 TX Vref Scan disable
5739 11:17:47.123799 == TX Byte 0 ==
5740 11:17:47.126843 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5741 11:17:47.130303 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5742 11:17:47.133618 == TX Byte 1 ==
5743 11:17:47.136758 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5744 11:17:47.139801 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5745 11:17:47.139879
5746 11:17:47.143453 [DATLAT]
5747 11:17:47.143536 Freq=933, CH1 RK0
5748 11:17:47.143601
5749 11:17:47.147096 DATLAT Default: 0xd
5750 11:17:47.147203 0, 0xFFFF, sum = 0
5751 11:17:47.150210 1, 0xFFFF, sum = 0
5752 11:17:47.150293 2, 0xFFFF, sum = 0
5753 11:17:47.153285 3, 0xFFFF, sum = 0
5754 11:17:47.153369 4, 0xFFFF, sum = 0
5755 11:17:47.156969 5, 0xFFFF, sum = 0
5756 11:17:47.157078 6, 0xFFFF, sum = 0
5757 11:17:47.159822 7, 0xFFFF, sum = 0
5758 11:17:47.159925 8, 0xFFFF, sum = 0
5759 11:17:47.163583 9, 0xFFFF, sum = 0
5760 11:17:47.163672 10, 0x0, sum = 1
5761 11:17:47.166612 11, 0x0, sum = 2
5762 11:17:47.166695 12, 0x0, sum = 3
5763 11:17:47.170406 13, 0x0, sum = 4
5764 11:17:47.170491 best_step = 11
5765 11:17:47.170555
5766 11:17:47.170615 ==
5767 11:17:47.173458 Dram Type= 6, Freq= 0, CH_1, rank 0
5768 11:17:47.176789 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5769 11:17:47.179827 ==
5770 11:17:47.179902 RX Vref Scan: 1
5771 11:17:47.179963
5772 11:17:47.183301 RX Vref 0 -> 0, step: 1
5773 11:17:47.183400
5774 11:17:47.186432 RX Delay -45 -> 252, step: 4
5775 11:17:47.186507
5776 11:17:47.190335 Set Vref, RX VrefLevel [Byte0]: 51
5777 11:17:47.193379 [Byte1]: 53
5778 11:17:47.193454
5779 11:17:47.196914 Final RX Vref Byte 0 = 51 to rank0
5780 11:17:47.199920 Final RX Vref Byte 1 = 53 to rank0
5781 11:17:47.203266 Final RX Vref Byte 0 = 51 to rank1
5782 11:17:47.206331 Final RX Vref Byte 1 = 53 to rank1==
5783 11:17:47.210291 Dram Type= 6, Freq= 0, CH_1, rank 0
5784 11:17:47.213560 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5785 11:17:47.213667 ==
5786 11:17:47.213760 DQS Delay:
5787 11:17:47.216709 DQS0 = 0, DQS1 = 0
5788 11:17:47.216790 DQM Delay:
5789 11:17:47.219769 DQM0 = 102, DQM1 = 99
5790 11:17:47.219850 DQ Delay:
5791 11:17:47.223113 DQ0 =106, DQ1 =96, DQ2 =92, DQ3 =98
5792 11:17:47.226290 DQ4 =104, DQ5 =112, DQ6 =112, DQ7 =102
5793 11:17:47.230309 DQ8 =88, DQ9 =90, DQ10 =100, DQ11 =92
5794 11:17:47.233516 DQ12 =106, DQ13 =106, DQ14 =106, DQ15 =106
5795 11:17:47.233598
5796 11:17:47.233662
5797 11:17:47.243098 [DQSOSCAuto] RK0, (LSB)MR18= 0x1a32, (MSB)MR19= 0x505, tDQSOscB0 = 406 ps tDQSOscB1 = 413 ps
5798 11:17:47.246083 CH1 RK0: MR19=505, MR18=1A32
5799 11:17:47.253371 CH1_RK0: MR19=0x505, MR18=0x1A32, DQSOSC=406, MR23=63, INC=65, DEC=43
5800 11:17:47.253453
5801 11:17:47.256237 ----->DramcWriteLeveling(PI) begin...
5802 11:17:47.256320 ==
5803 11:17:47.259427 Dram Type= 6, Freq= 0, CH_1, rank 1
5804 11:17:47.263052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5805 11:17:47.263135 ==
5806 11:17:47.266065 Write leveling (Byte 0): 26 => 26
5807 11:17:47.269563 Write leveling (Byte 1): 28 => 28
5808 11:17:47.272666 DramcWriteLeveling(PI) end<-----
5809 11:17:47.272749
5810 11:17:47.272812 ==
5811 11:17:47.276316 Dram Type= 6, Freq= 0, CH_1, rank 1
5812 11:17:47.279628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5813 11:17:47.279711 ==
5814 11:17:47.283093 [Gating] SW mode calibration
5815 11:17:47.289601 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5816 11:17:47.296363 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5817 11:17:47.299288 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5818 11:17:47.302653 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5819 11:17:47.309538 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5820 11:17:47.313054 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5821 11:17:47.316424 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5822 11:17:47.322499 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5823 11:17:47.326027 0 14 24 | B1->B0 | 2828 3434 | 0 0 | (0 0) (0 0)
5824 11:17:47.329282 0 14 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5825 11:17:47.336160 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5826 11:17:47.339310 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5827 11:17:47.342860 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5828 11:17:47.349471 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5829 11:17:47.353024 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5830 11:17:47.356112 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5831 11:17:47.359739 0 15 24 | B1->B0 | 3535 2e2e | 0 0 | (0 0) (0 0)
5832 11:17:47.365687 0 15 28 | B1->B0 | 4646 4040 | 0 0 | (0 0) (0 0)
5833 11:17:47.369420 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5834 11:17:47.372757 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5835 11:17:47.379217 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5836 11:17:47.382409 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5837 11:17:47.386183 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5838 11:17:47.393088 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5839 11:17:47.396147 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5840 11:17:47.399276 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5841 11:17:47.406339 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
5842 11:17:47.409565 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5843 11:17:47.412696 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5844 11:17:47.419160 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5845 11:17:47.422608 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5846 11:17:47.426214 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5847 11:17:47.432528 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5848 11:17:47.435783 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5849 11:17:47.439138 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5850 11:17:47.445796 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5851 11:17:47.449375 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5852 11:17:47.452726 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5853 11:17:47.459062 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5854 11:17:47.462468 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5855 11:17:47.465751 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
5856 11:17:47.472226 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5857 11:17:47.472310 Total UI for P1: 0, mck2ui 16
5858 11:17:47.478597 best dqsien dly found for B0: ( 1, 2, 26)
5859 11:17:47.482168 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5860 11:17:47.485572 Total UI for P1: 0, mck2ui 16
5861 11:17:47.488671 best dqsien dly found for B1: ( 1, 2, 26)
5862 11:17:47.492158 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5863 11:17:47.495203 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5864 11:17:47.495318
5865 11:17:47.498651 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5866 11:17:47.501777 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5867 11:17:47.505038 [Gating] SW calibration Done
5868 11:17:47.505149 ==
5869 11:17:47.508648 Dram Type= 6, Freq= 0, CH_1, rank 1
5870 11:17:47.512056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5871 11:17:47.512166 ==
5872 11:17:47.515215 RX Vref Scan: 0
5873 11:17:47.515321
5874 11:17:47.518449 RX Vref 0 -> 0, step: 1
5875 11:17:47.518534
5876 11:17:47.518607 RX Delay -80 -> 252, step: 8
5877 11:17:47.525205 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
5878 11:17:47.528600 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5879 11:17:47.532273 iDelay=208, Bit 2, Center 87 (0 ~ 175) 176
5880 11:17:47.535111 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5881 11:17:47.538795 iDelay=208, Bit 4, Center 95 (8 ~ 183) 176
5882 11:17:47.542030 iDelay=208, Bit 5, Center 115 (24 ~ 207) 184
5883 11:17:47.548559 iDelay=208, Bit 6, Center 111 (24 ~ 199) 176
5884 11:17:47.552224 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5885 11:17:47.555372 iDelay=208, Bit 8, Center 87 (0 ~ 175) 176
5886 11:17:47.558546 iDelay=208, Bit 9, Center 91 (0 ~ 183) 184
5887 11:17:47.561779 iDelay=208, Bit 10, Center 99 (8 ~ 191) 184
5888 11:17:47.565609 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5889 11:17:47.571617 iDelay=208, Bit 12, Center 107 (16 ~ 199) 184
5890 11:17:47.575292 iDelay=208, Bit 13, Center 107 (16 ~ 199) 184
5891 11:17:47.578213 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5892 11:17:47.582003 iDelay=208, Bit 15, Center 107 (16 ~ 199) 184
5893 11:17:47.582120 ==
5894 11:17:47.585339 Dram Type= 6, Freq= 0, CH_1, rank 1
5895 11:17:47.591982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5896 11:17:47.592113 ==
5897 11:17:47.592250 DQS Delay:
5898 11:17:47.592330 DQS0 = 0, DQS1 = 0
5899 11:17:47.594773 DQM Delay:
5900 11:17:47.594857 DQM0 = 101, DQM1 = 98
5901 11:17:47.598248 DQ Delay:
5902 11:17:47.601839 DQ0 =107, DQ1 =99, DQ2 =87, DQ3 =99
5903 11:17:47.604779 DQ4 =95, DQ5 =115, DQ6 =111, DQ7 =99
5904 11:17:47.608484 DQ8 =87, DQ9 =91, DQ10 =99, DQ11 =91
5905 11:17:47.611439 DQ12 =107, DQ13 =107, DQ14 =99, DQ15 =107
5906 11:17:47.611588
5907 11:17:47.611709
5908 11:17:47.611789 ==
5909 11:17:47.614791 Dram Type= 6, Freq= 0, CH_1, rank 1
5910 11:17:47.618064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5911 11:17:47.618177 ==
5912 11:17:47.618279
5913 11:17:47.618377
5914 11:17:47.621661 TX Vref Scan disable
5915 11:17:47.625040 == TX Byte 0 ==
5916 11:17:47.628026 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5917 11:17:47.631466 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5918 11:17:47.634683 == TX Byte 1 ==
5919 11:17:47.638268 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5920 11:17:47.641313 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5921 11:17:47.641387 ==
5922 11:17:47.644665 Dram Type= 6, Freq= 0, CH_1, rank 1
5923 11:17:47.648547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5924 11:17:47.648621 ==
5925 11:17:47.651282
5926 11:17:47.651383
5927 11:17:47.651448 TX Vref Scan disable
5928 11:17:47.655039 == TX Byte 0 ==
5929 11:17:47.658042 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5930 11:17:47.661984 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5931 11:17:47.665176 == TX Byte 1 ==
5932 11:17:47.668277 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5933 11:17:47.671523 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5934 11:17:47.675107
5935 11:17:47.675208 [DATLAT]
5936 11:17:47.675316 Freq=933, CH1 RK1
5937 11:17:47.675438
5938 11:17:47.678106 DATLAT Default: 0xb
5939 11:17:47.678207 0, 0xFFFF, sum = 0
5940 11:17:47.681302 1, 0xFFFF, sum = 0
5941 11:17:47.681433 2, 0xFFFF, sum = 0
5942 11:17:47.684914 3, 0xFFFF, sum = 0
5943 11:17:47.685018 4, 0xFFFF, sum = 0
5944 11:17:47.688305 5, 0xFFFF, sum = 0
5945 11:17:47.691815 6, 0xFFFF, sum = 0
5946 11:17:47.691921 7, 0xFFFF, sum = 0
5947 11:17:47.694506 8, 0xFFFF, sum = 0
5948 11:17:47.694591 9, 0xFFFF, sum = 0
5949 11:17:47.698225 10, 0x0, sum = 1
5950 11:17:47.698340 11, 0x0, sum = 2
5951 11:17:47.698449 12, 0x0, sum = 3
5952 11:17:47.701604 13, 0x0, sum = 4
5953 11:17:47.701691 best_step = 11
5954 11:17:47.701786
5955 11:17:47.704548 ==
5956 11:17:47.704658 Dram Type= 6, Freq= 0, CH_1, rank 1
5957 11:17:47.711660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5958 11:17:47.711770 ==
5959 11:17:47.711868 RX Vref Scan: 0
5960 11:17:47.711965
5961 11:17:47.714474 RX Vref 0 -> 0, step: 1
5962 11:17:47.714583
5963 11:17:47.718176 RX Delay -45 -> 252, step: 4
5964 11:17:47.721283 iDelay=199, Bit 0, Center 108 (27 ~ 190) 164
5965 11:17:47.728086 iDelay=199, Bit 1, Center 100 (19 ~ 182) 164
5966 11:17:47.731118 iDelay=199, Bit 2, Center 94 (11 ~ 178) 168
5967 11:17:47.734968 iDelay=199, Bit 3, Center 100 (19 ~ 182) 164
5968 11:17:47.738200 iDelay=199, Bit 4, Center 100 (19 ~ 182) 164
5969 11:17:47.741309 iDelay=199, Bit 5, Center 116 (35 ~ 198) 164
5970 11:17:47.748227 iDelay=199, Bit 6, Center 114 (31 ~ 198) 168
5971 11:17:47.751328 iDelay=199, Bit 7, Center 102 (19 ~ 186) 168
5972 11:17:47.755244 iDelay=199, Bit 8, Center 92 (11 ~ 174) 164
5973 11:17:47.758356 iDelay=199, Bit 9, Center 88 (-1 ~ 178) 180
5974 11:17:47.761416 iDelay=199, Bit 10, Center 102 (19 ~ 186) 168
5975 11:17:47.764616 iDelay=199, Bit 11, Center 94 (11 ~ 178) 168
5976 11:17:47.771714 iDelay=199, Bit 12, Center 108 (19 ~ 198) 180
5977 11:17:47.774901 iDelay=199, Bit 13, Center 104 (19 ~ 190) 172
5978 11:17:47.777865 iDelay=199, Bit 14, Center 104 (19 ~ 190) 172
5979 11:17:47.781224 iDelay=199, Bit 15, Center 106 (19 ~ 194) 176
5980 11:17:47.781331 ==
5981 11:17:47.784962 Dram Type= 6, Freq= 0, CH_1, rank 1
5982 11:17:47.791187 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5983 11:17:47.791268 ==
5984 11:17:47.791356 DQS Delay:
5985 11:17:47.795067 DQS0 = 0, DQS1 = 0
5986 11:17:47.795176 DQM Delay:
5987 11:17:47.795272 DQM0 = 104, DQM1 = 99
5988 11:17:47.798179 DQ Delay:
5989 11:17:47.801744 DQ0 =108, DQ1 =100, DQ2 =94, DQ3 =100
5990 11:17:47.804673 DQ4 =100, DQ5 =116, DQ6 =114, DQ7 =102
5991 11:17:47.808207 DQ8 =92, DQ9 =88, DQ10 =102, DQ11 =94
5992 11:17:47.811259 DQ12 =108, DQ13 =104, DQ14 =104, DQ15 =106
5993 11:17:47.811411
5994 11:17:47.811552
5995 11:17:47.818285 [DQSOSCAuto] RK1, (LSB)MR18= 0x29fd, (MSB)MR19= 0x504, tDQSOscB0 = 423 ps tDQSOscB1 = 408 ps
5996 11:17:47.821170 CH1 RK1: MR19=504, MR18=29FD
5997 11:17:47.827919 CH1_RK1: MR19=0x504, MR18=0x29FD, DQSOSC=408, MR23=63, INC=65, DEC=43
5998 11:17:47.830994 [RxdqsGatingPostProcess] freq 933
5999 11:17:47.837918 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6000 11:17:47.841188 best DQS0 dly(2T, 0.5T) = (0, 10)
6001 11:17:47.844519 best DQS1 dly(2T, 0.5T) = (0, 10)
6002 11:17:47.848071 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6003 11:17:47.848176 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6004 11:17:47.851228 best DQS0 dly(2T, 0.5T) = (0, 10)
6005 11:17:47.854683 best DQS1 dly(2T, 0.5T) = (0, 10)
6006 11:17:47.857935 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6007 11:17:47.860875 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6008 11:17:47.864220 Pre-setting of DQS Precalculation
6009 11:17:47.871380 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6010 11:17:47.877830 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6011 11:17:47.884176 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6012 11:17:47.884259
6013 11:17:47.884324
6014 11:17:47.887895 [Calibration Summary] 1866 Mbps
6015 11:17:47.887977 CH 0, Rank 0
6016 11:17:47.890952 SW Impedance : PASS
6017 11:17:47.894138 DUTY Scan : NO K
6018 11:17:47.894245 ZQ Calibration : PASS
6019 11:17:47.898143 Jitter Meter : NO K
6020 11:17:47.901151 CBT Training : PASS
6021 11:17:47.901233 Write leveling : PASS
6022 11:17:47.904229 RX DQS gating : PASS
6023 11:17:47.907725 RX DQ/DQS(RDDQC) : PASS
6024 11:17:47.907807 TX DQ/DQS : PASS
6025 11:17:47.910851 RX DATLAT : PASS
6026 11:17:47.910933 RX DQ/DQS(Engine): PASS
6027 11:17:47.914431 TX OE : NO K
6028 11:17:47.914514 All Pass.
6029 11:17:47.914578
6030 11:17:47.917433 CH 0, Rank 1
6031 11:17:47.917517 SW Impedance : PASS
6032 11:17:47.920928 DUTY Scan : NO K
6033 11:17:47.924368 ZQ Calibration : PASS
6034 11:17:47.924449 Jitter Meter : NO K
6035 11:17:47.927371 CBT Training : PASS
6036 11:17:47.930824 Write leveling : PASS
6037 11:17:47.930906 RX DQS gating : PASS
6038 11:17:47.934362 RX DQ/DQS(RDDQC) : PASS
6039 11:17:47.937367 TX DQ/DQS : PASS
6040 11:17:47.937450 RX DATLAT : PASS
6041 11:17:47.940692 RX DQ/DQS(Engine): PASS
6042 11:17:47.943962 TX OE : NO K
6043 11:17:47.944047 All Pass.
6044 11:17:47.944130
6045 11:17:47.944208 CH 1, Rank 0
6046 11:17:47.947581 SW Impedance : PASS
6047 11:17:47.950533 DUTY Scan : NO K
6048 11:17:47.950635 ZQ Calibration : PASS
6049 11:17:47.954397 Jitter Meter : NO K
6050 11:17:47.957532 CBT Training : PASS
6051 11:17:47.957614 Write leveling : PASS
6052 11:17:47.960625 RX DQS gating : PASS
6053 11:17:47.964278 RX DQ/DQS(RDDQC) : PASS
6054 11:17:47.964361 TX DQ/DQS : PASS
6055 11:17:47.967191 RX DATLAT : PASS
6056 11:17:47.967273 RX DQ/DQS(Engine): PASS
6057 11:17:47.970687 TX OE : NO K
6058 11:17:47.970790 All Pass.
6059 11:17:47.970873
6060 11:17:47.973991 CH 1, Rank 1
6061 11:17:47.974079 SW Impedance : PASS
6062 11:17:47.977588 DUTY Scan : NO K
6063 11:17:47.980817 ZQ Calibration : PASS
6064 11:17:47.980925 Jitter Meter : NO K
6065 11:17:47.984123 CBT Training : PASS
6066 11:17:47.987671 Write leveling : PASS
6067 11:17:47.987754 RX DQS gating : PASS
6068 11:17:47.990614 RX DQ/DQS(RDDQC) : PASS
6069 11:17:47.994305 TX DQ/DQS : PASS
6070 11:17:47.994388 RX DATLAT : PASS
6071 11:17:47.997861 RX DQ/DQS(Engine): PASS
6072 11:17:48.000759 TX OE : NO K
6073 11:17:48.000867 All Pass.
6074 11:17:48.000949
6075 11:17:48.001025 DramC Write-DBI off
6076 11:17:48.004399 PER_BANK_REFRESH: Hybrid Mode
6077 11:17:48.007603 TX_TRACKING: ON
6078 11:17:48.014265 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6079 11:17:48.017226 [FAST_K] Save calibration result to emmc
6080 11:17:48.023659 dramc_set_vcore_voltage set vcore to 650000
6081 11:17:48.023752 Read voltage for 400, 6
6082 11:17:48.027182 Vio18 = 0
6083 11:17:48.027288 Vcore = 650000
6084 11:17:48.027408 Vdram = 0
6085 11:17:48.027469 Vddq = 0
6086 11:17:48.030734 Vmddr = 0
6087 11:17:48.034203 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6088 11:17:48.040588 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6089 11:17:48.044099 MEM_TYPE=3, freq_sel=20
6090 11:17:48.044179 sv_algorithm_assistance_LP4_800
6091 11:17:48.050847 ============ PULL DRAM RESETB DOWN ============
6092 11:17:48.053863 ========== PULL DRAM RESETB DOWN end =========
6093 11:17:48.056934 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6094 11:17:48.060698 ===================================
6095 11:17:48.063877 LPDDR4 DRAM CONFIGURATION
6096 11:17:48.067037 ===================================
6097 11:17:48.070635 EX_ROW_EN[0] = 0x0
6098 11:17:48.070716 EX_ROW_EN[1] = 0x0
6099 11:17:48.073731 LP4Y_EN = 0x0
6100 11:17:48.073838 WORK_FSP = 0x0
6101 11:17:48.076890 WL = 0x2
6102 11:17:48.076971 RL = 0x2
6103 11:17:48.080152 BL = 0x2
6104 11:17:48.080234 RPST = 0x0
6105 11:17:48.084066 RD_PRE = 0x0
6106 11:17:48.084146 WR_PRE = 0x1
6107 11:17:48.087049 WR_PST = 0x0
6108 11:17:48.087131 DBI_WR = 0x0
6109 11:17:48.090740 DBI_RD = 0x0
6110 11:17:48.090821 OTF = 0x1
6111 11:17:48.093912 ===================================
6112 11:17:48.097134 ===================================
6113 11:17:48.100305 ANA top config
6114 11:17:48.103894 ===================================
6115 11:17:48.106870 DLL_ASYNC_EN = 0
6116 11:17:48.106950 ALL_SLAVE_EN = 1
6117 11:17:48.110067 NEW_RANK_MODE = 1
6118 11:17:48.113720 DLL_IDLE_MODE = 1
6119 11:17:48.116823 LP45_APHY_COMB_EN = 1
6120 11:17:48.119960 TX_ODT_DIS = 1
6121 11:17:48.120043 NEW_8X_MODE = 1
6122 11:17:48.123514 ===================================
6123 11:17:48.126627 ===================================
6124 11:17:48.130301 data_rate = 800
6125 11:17:48.133300 CKR = 1
6126 11:17:48.136727 DQ_P2S_RATIO = 4
6127 11:17:48.140231 ===================================
6128 11:17:48.143477 CA_P2S_RATIO = 4
6129 11:17:48.143560 DQ_CA_OPEN = 0
6130 11:17:48.146828 DQ_SEMI_OPEN = 1
6131 11:17:48.150256 CA_SEMI_OPEN = 1
6132 11:17:48.153150 CA_FULL_RATE = 0
6133 11:17:48.156790 DQ_CKDIV4_EN = 0
6134 11:17:48.159922 CA_CKDIV4_EN = 1
6135 11:17:48.160006 CA_PREDIV_EN = 0
6136 11:17:48.163062 PH8_DLY = 0
6137 11:17:48.166891 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6138 11:17:48.169975 DQ_AAMCK_DIV = 0
6139 11:17:48.173050 CA_AAMCK_DIV = 0
6140 11:17:48.176597 CA_ADMCK_DIV = 4
6141 11:17:48.176691 DQ_TRACK_CA_EN = 0
6142 11:17:48.180091 CA_PICK = 800
6143 11:17:48.183718 CA_MCKIO = 400
6144 11:17:48.186825 MCKIO_SEMI = 400
6145 11:17:48.190118 PLL_FREQ = 3016
6146 11:17:48.193163 DQ_UI_PI_RATIO = 32
6147 11:17:48.196750 CA_UI_PI_RATIO = 32
6148 11:17:48.200620 ===================================
6149 11:17:48.203597 ===================================
6150 11:17:48.203680 memory_type:LPDDR4
6151 11:17:48.206904 GP_NUM : 10
6152 11:17:48.209966 SRAM_EN : 1
6153 11:17:48.210050 MD32_EN : 0
6154 11:17:48.213343 ===================================
6155 11:17:48.216802 [ANA_INIT] >>>>>>>>>>>>>>
6156 11:17:48.220034 <<<<<< [CONFIGURE PHASE]: ANA_TX
6157 11:17:48.223372 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6158 11:17:48.226947 ===================================
6159 11:17:48.230419 data_rate = 800,PCW = 0X7400
6160 11:17:48.233505 ===================================
6161 11:17:48.236655 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6162 11:17:48.240013 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6163 11:17:48.253142 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6164 11:17:48.256617 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6165 11:17:48.260121 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6166 11:17:48.263256 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6167 11:17:48.266478 [ANA_INIT] flow start
6168 11:17:48.266561 [ANA_INIT] PLL >>>>>>>>
6169 11:17:48.269585 [ANA_INIT] PLL <<<<<<<<
6170 11:17:48.273195 [ANA_INIT] MIDPI >>>>>>>>
6171 11:17:48.276466 [ANA_INIT] MIDPI <<<<<<<<
6172 11:17:48.276550 [ANA_INIT] DLL >>>>>>>>
6173 11:17:48.280000 [ANA_INIT] flow end
6174 11:17:48.282841 ============ LP4 DIFF to SE enter ============
6175 11:17:48.286656 ============ LP4 DIFF to SE exit ============
6176 11:17:48.289783 [ANA_INIT] <<<<<<<<<<<<<
6177 11:17:48.292801 [Flow] Enable top DCM control >>>>>
6178 11:17:48.296145 [Flow] Enable top DCM control <<<<<
6179 11:17:48.299647 Enable DLL master slave shuffle
6180 11:17:48.307035 ==============================================================
6181 11:17:48.307119 Gating Mode config
6182 11:17:48.313007 ==============================================================
6183 11:17:48.313091 Config description:
6184 11:17:48.323091 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6185 11:17:48.329788 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6186 11:17:48.336232 SELPH_MODE 0: By rank 1: By Phase
6187 11:17:48.339211 ==============================================================
6188 11:17:48.342707 GAT_TRACK_EN = 0
6189 11:17:48.346189 RX_GATING_MODE = 2
6190 11:17:48.349160 RX_GATING_TRACK_MODE = 2
6191 11:17:48.352700 SELPH_MODE = 1
6192 11:17:48.356445 PICG_EARLY_EN = 1
6193 11:17:48.359282 VALID_LAT_VALUE = 1
6194 11:17:48.366356 ==============================================================
6195 11:17:48.369340 Enter into Gating configuration >>>>
6196 11:17:48.372427 Exit from Gating configuration <<<<
6197 11:17:48.372509 Enter into DVFS_PRE_config >>>>>
6198 11:17:48.385976 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6199 11:17:48.389052 Exit from DVFS_PRE_config <<<<<
6200 11:17:48.392592 Enter into PICG configuration >>>>
6201 11:17:48.395895 Exit from PICG configuration <<<<
6202 11:17:48.395976 [RX_INPUT] configuration >>>>>
6203 11:17:48.399059 [RX_INPUT] configuration <<<<<
6204 11:17:48.405572 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6205 11:17:48.409284 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6206 11:17:48.415600 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6207 11:17:48.422784 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6208 11:17:48.429362 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6209 11:17:48.435624 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6210 11:17:48.438706 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6211 11:17:48.442120 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6212 11:17:48.448619 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6213 11:17:48.452291 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6214 11:17:48.455608 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6215 11:17:48.458596 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6216 11:17:48.462450 ===================================
6217 11:17:48.465229 LPDDR4 DRAM CONFIGURATION
6218 11:17:48.468699 ===================================
6219 11:17:48.472315 EX_ROW_EN[0] = 0x0
6220 11:17:48.472398 EX_ROW_EN[1] = 0x0
6221 11:17:48.475191 LP4Y_EN = 0x0
6222 11:17:48.475273 WORK_FSP = 0x0
6223 11:17:48.479041 WL = 0x2
6224 11:17:48.479124 RL = 0x2
6225 11:17:48.482004 BL = 0x2
6226 11:17:48.482086 RPST = 0x0
6227 11:17:48.485175 RD_PRE = 0x0
6228 11:17:48.485257 WR_PRE = 0x1
6229 11:17:48.488754 WR_PST = 0x0
6230 11:17:48.491793 DBI_WR = 0x0
6231 11:17:48.491875 DBI_RD = 0x0
6232 11:17:48.495030 OTF = 0x1
6233 11:17:48.498550 ===================================
6234 11:17:48.501709 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6235 11:17:48.505525 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6236 11:17:48.508707 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6237 11:17:48.512198 ===================================
6238 11:17:48.514961 LPDDR4 DRAM CONFIGURATION
6239 11:17:48.518568 ===================================
6240 11:17:48.521661 EX_ROW_EN[0] = 0x10
6241 11:17:48.521777 EX_ROW_EN[1] = 0x0
6242 11:17:48.524882 LP4Y_EN = 0x0
6243 11:17:48.524965 WORK_FSP = 0x0
6244 11:17:48.528517 WL = 0x2
6245 11:17:48.528600 RL = 0x2
6246 11:17:48.531633 BL = 0x2
6247 11:17:48.531716 RPST = 0x0
6248 11:17:48.534867 RD_PRE = 0x0
6249 11:17:48.534949 WR_PRE = 0x1
6250 11:17:48.538754 WR_PST = 0x0
6251 11:17:48.538837 DBI_WR = 0x0
6252 11:17:48.541634 DBI_RD = 0x0
6253 11:17:48.545138 OTF = 0x1
6254 11:17:48.548182 ===================================
6255 11:17:48.551526 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6256 11:17:48.556742 nWR fixed to 30
6257 11:17:48.560191 [ModeRegInit_LP4] CH0 RK0
6258 11:17:48.560274 [ModeRegInit_LP4] CH0 RK1
6259 11:17:48.563061 [ModeRegInit_LP4] CH1 RK0
6260 11:17:48.566601 [ModeRegInit_LP4] CH1 RK1
6261 11:17:48.566684 match AC timing 19
6262 11:17:48.573033 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6263 11:17:48.576690 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6264 11:17:48.580369 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6265 11:17:48.586850 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6266 11:17:48.589972 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6267 11:17:48.590056 ==
6268 11:17:48.593164 Dram Type= 6, Freq= 0, CH_0, rank 0
6269 11:17:48.596813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6270 11:17:48.596897 ==
6271 11:17:48.603072 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6272 11:17:48.610012 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6273 11:17:48.613031 [CA 0] Center 36 (8~64) winsize 57
6274 11:17:48.616927 [CA 1] Center 36 (8~64) winsize 57
6275 11:17:48.619959 [CA 2] Center 36 (8~64) winsize 57
6276 11:17:48.623038 [CA 3] Center 36 (8~64) winsize 57
6277 11:17:48.623121 [CA 4] Center 36 (8~64) winsize 57
6278 11:17:48.626745 [CA 5] Center 36 (8~64) winsize 57
6279 11:17:48.626828
6280 11:17:48.633107 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6281 11:17:48.633190
6282 11:17:48.636658 [CATrainingPosCal] consider 1 rank data
6283 11:17:48.639333 u2DelayCellTimex100 = 270/100 ps
6284 11:17:48.643087 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6285 11:17:48.646669 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6286 11:17:48.650161 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6287 11:17:48.652967 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6288 11:17:48.656569 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6289 11:17:48.659413 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6290 11:17:48.659496
6291 11:17:48.663064 CA PerBit enable=1, Macro0, CA PI delay=36
6292 11:17:48.663148
6293 11:17:48.666301 [CBTSetCACLKResult] CA Dly = 36
6294 11:17:48.669738 CS Dly: 1 (0~32)
6295 11:17:48.669821 ==
6296 11:17:48.673151 Dram Type= 6, Freq= 0, CH_0, rank 1
6297 11:17:48.676690 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6298 11:17:48.676774 ==
6299 11:17:48.682698 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6300 11:17:48.686170 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6301 11:17:48.689677 [CA 0] Center 36 (8~64) winsize 57
6302 11:17:48.692994 [CA 1] Center 36 (8~64) winsize 57
6303 11:17:48.696069 [CA 2] Center 36 (8~64) winsize 57
6304 11:17:48.699381 [CA 3] Center 36 (8~64) winsize 57
6305 11:17:48.702757 [CA 4] Center 36 (8~64) winsize 57
6306 11:17:48.705952 [CA 5] Center 36 (8~64) winsize 57
6307 11:17:48.706035
6308 11:17:48.709623 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6309 11:17:48.709706
6310 11:17:48.712933 [CATrainingPosCal] consider 2 rank data
6311 11:17:48.716310 u2DelayCellTimex100 = 270/100 ps
6312 11:17:48.719516 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6313 11:17:48.722581 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6314 11:17:48.729473 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6315 11:17:48.732453 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6316 11:17:48.736429 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6317 11:17:48.739494 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6318 11:17:48.739577
6319 11:17:48.742891 CA PerBit enable=1, Macro0, CA PI delay=36
6320 11:17:48.742974
6321 11:17:48.745995 [CBTSetCACLKResult] CA Dly = 36
6322 11:17:48.746078 CS Dly: 1 (0~32)
6323 11:17:48.746144
6324 11:17:48.749129 ----->DramcWriteLeveling(PI) begin...
6325 11:17:48.752852 ==
6326 11:17:48.752935 Dram Type= 6, Freq= 0, CH_0, rank 0
6327 11:17:48.759537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6328 11:17:48.759620 ==
6329 11:17:48.762913 Write leveling (Byte 0): 40 => 8
6330 11:17:48.766035 Write leveling (Byte 1): 40 => 8
6331 11:17:48.766117 DramcWriteLeveling(PI) end<-----
6332 11:17:48.769540
6333 11:17:48.769622 ==
6334 11:17:48.772582 Dram Type= 6, Freq= 0, CH_0, rank 0
6335 11:17:48.776177 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6336 11:17:48.776259 ==
6337 11:17:48.779527 [Gating] SW mode calibration
6338 11:17:48.786062 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6339 11:17:48.789095 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6340 11:17:48.796173 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6341 11:17:48.799622 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6342 11:17:48.802557 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6343 11:17:48.809163 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6344 11:17:48.812160 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6345 11:17:48.815618 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6346 11:17:48.822590 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6347 11:17:48.825728 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6348 11:17:48.828877 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6349 11:17:48.832710 Total UI for P1: 0, mck2ui 16
6350 11:17:48.835819 best dqsien dly found for B0: ( 0, 14, 24)
6351 11:17:48.838905 Total UI for P1: 0, mck2ui 16
6352 11:17:48.842160 best dqsien dly found for B1: ( 0, 14, 24)
6353 11:17:48.845785 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6354 11:17:48.848874 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6355 11:17:48.848956
6356 11:17:48.855911 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6357 11:17:48.859017 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6358 11:17:48.862301 [Gating] SW calibration Done
6359 11:17:48.862384 ==
6360 11:17:48.865356 Dram Type= 6, Freq= 0, CH_0, rank 0
6361 11:17:48.868683 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6362 11:17:48.868764 ==
6363 11:17:48.868828 RX Vref Scan: 0
6364 11:17:48.868887
6365 11:17:48.871907 RX Vref 0 -> 0, step: 1
6366 11:17:48.871987
6367 11:17:48.875338 RX Delay -410 -> 252, step: 16
6368 11:17:48.878772 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6369 11:17:48.885382 iDelay=230, Bit 1, Center -11 (-250 ~ 229) 480
6370 11:17:48.888741 iDelay=230, Bit 2, Center -27 (-266 ~ 213) 480
6371 11:17:48.892353 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6372 11:17:48.895425 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6373 11:17:48.901767 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6374 11:17:48.905629 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6375 11:17:48.908443 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6376 11:17:48.912061 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6377 11:17:48.915221 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6378 11:17:48.922269 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6379 11:17:48.925260 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6380 11:17:48.928394 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6381 11:17:48.935719 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6382 11:17:48.938735 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6383 11:17:48.941997 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6384 11:17:48.942078 ==
6385 11:17:48.945151 Dram Type= 6, Freq= 0, CH_0, rank 0
6386 11:17:48.948743 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6387 11:17:48.951936 ==
6388 11:17:48.952016 DQS Delay:
6389 11:17:48.952080 DQS0 = 27, DQS1 = 35
6390 11:17:48.955016 DQM Delay:
6391 11:17:48.955096 DQM0 = 11, DQM1 = 11
6392 11:17:48.958490 DQ Delay:
6393 11:17:48.958570 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =8
6394 11:17:48.961550 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6395 11:17:48.965302 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6396 11:17:48.968321 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6397 11:17:48.968401
6398 11:17:48.968464
6399 11:17:48.971628 ==
6400 11:17:48.971709 Dram Type= 6, Freq= 0, CH_0, rank 0
6401 11:17:48.978464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6402 11:17:48.978545 ==
6403 11:17:48.978626
6404 11:17:48.978720
6405 11:17:48.981803 TX Vref Scan disable
6406 11:17:48.981883 == TX Byte 0 ==
6407 11:17:48.984682 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6408 11:17:48.991713 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6409 11:17:48.991794 == TX Byte 1 ==
6410 11:17:48.994889 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6411 11:17:48.998383 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6412 11:17:49.001948 ==
6413 11:17:49.004890 Dram Type= 6, Freq= 0, CH_0, rank 0
6414 11:17:49.008173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6415 11:17:49.008256 ==
6416 11:17:49.008321
6417 11:17:49.008380
6418 11:17:49.011532 TX Vref Scan disable
6419 11:17:49.011614 == TX Byte 0 ==
6420 11:17:49.014839 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6421 11:17:49.021312 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6422 11:17:49.021397 == TX Byte 1 ==
6423 11:17:49.025254 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6424 11:17:49.031926 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6425 11:17:49.032009
6426 11:17:49.032073 [DATLAT]
6427 11:17:49.032134 Freq=400, CH0 RK0
6428 11:17:49.032193
6429 11:17:49.035158 DATLAT Default: 0xf
6430 11:17:49.035240 0, 0xFFFF, sum = 0
6431 11:17:49.038078 1, 0xFFFF, sum = 0
6432 11:17:49.038161 2, 0xFFFF, sum = 0
6433 11:17:49.041736 3, 0xFFFF, sum = 0
6434 11:17:49.044958 4, 0xFFFF, sum = 0
6435 11:17:49.045042 5, 0xFFFF, sum = 0
6436 11:17:49.047917 6, 0xFFFF, sum = 0
6437 11:17:49.048000 7, 0xFFFF, sum = 0
6438 11:17:49.051233 8, 0xFFFF, sum = 0
6439 11:17:49.051317 9, 0xFFFF, sum = 0
6440 11:17:49.054463 10, 0xFFFF, sum = 0
6441 11:17:49.054546 11, 0xFFFF, sum = 0
6442 11:17:49.057974 12, 0xFFFF, sum = 0
6443 11:17:49.058057 13, 0x0, sum = 1
6444 11:17:49.061075 14, 0x0, sum = 2
6445 11:17:49.061159 15, 0x0, sum = 3
6446 11:17:49.064948 16, 0x0, sum = 4
6447 11:17:49.065031 best_step = 14
6448 11:17:49.065096
6449 11:17:49.065155 ==
6450 11:17:49.068066 Dram Type= 6, Freq= 0, CH_0, rank 0
6451 11:17:49.070972 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6452 11:17:49.074172 ==
6453 11:17:49.074254 RX Vref Scan: 1
6454 11:17:49.074318
6455 11:17:49.077588 RX Vref 0 -> 0, step: 1
6456 11:17:49.077669
6457 11:17:49.081036 RX Delay -311 -> 252, step: 8
6458 11:17:49.081118
6459 11:17:49.084443 Set Vref, RX VrefLevel [Byte0]: 54
6460 11:17:49.087545 [Byte1]: 55
6461 11:17:49.087652
6462 11:17:49.091243 Final RX Vref Byte 0 = 54 to rank0
6463 11:17:49.094110 Final RX Vref Byte 1 = 55 to rank0
6464 11:17:49.097495 Final RX Vref Byte 0 = 54 to rank1
6465 11:17:49.101027 Final RX Vref Byte 1 = 55 to rank1==
6466 11:17:49.104453 Dram Type= 6, Freq= 0, CH_0, rank 0
6467 11:17:49.107313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6468 11:17:49.107438 ==
6469 11:17:49.110928 DQS Delay:
6470 11:17:49.111010 DQS0 = 28, DQS1 = 36
6471 11:17:49.114458 DQM Delay:
6472 11:17:49.114540 DQM0 = 11, DQM1 = 13
6473 11:17:49.114605 DQ Delay:
6474 11:17:49.117467 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6475 11:17:49.120860 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =16
6476 11:17:49.124380 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =4
6477 11:17:49.127252 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =20
6478 11:17:49.127355
6479 11:17:49.127435
6480 11:17:49.137472 [DQSOSCAuto] RK0, (LSB)MR18= 0xc8b5, (MSB)MR19= 0xc0c, tDQSOscB0 = 387 ps tDQSOscB1 = 385 ps
6481 11:17:49.137556 CH0 RK0: MR19=C0C, MR18=C8B5
6482 11:17:49.144322 CH0_RK0: MR19=0xC0C, MR18=0xC8B5, DQSOSC=385, MR23=63, INC=398, DEC=265
6483 11:17:49.144405 ==
6484 11:17:49.147280 Dram Type= 6, Freq= 0, CH_0, rank 1
6485 11:17:49.154294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6486 11:17:49.154377 ==
6487 11:17:49.157090 [Gating] SW mode calibration
6488 11:17:49.163799 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6489 11:17:49.167430 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6490 11:17:49.173806 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6491 11:17:49.177170 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6492 11:17:49.180675 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6493 11:17:49.187238 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6494 11:17:49.190380 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6495 11:17:49.193875 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6496 11:17:49.200526 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6497 11:17:49.203496 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6498 11:17:49.206896 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6499 11:17:49.210505 Total UI for P1: 0, mck2ui 16
6500 11:17:49.213419 best dqsien dly found for B0: ( 0, 14, 24)
6501 11:17:49.217044 Total UI for P1: 0, mck2ui 16
6502 11:17:49.220455 best dqsien dly found for B1: ( 0, 14, 24)
6503 11:17:49.223869 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6504 11:17:49.227282 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6505 11:17:49.227391
6506 11:17:49.230663 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6507 11:17:49.237116 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6508 11:17:49.237199 [Gating] SW calibration Done
6509 11:17:49.237265 ==
6510 11:17:49.240462 Dram Type= 6, Freq= 0, CH_0, rank 1
6511 11:17:49.247136 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6512 11:17:49.247219 ==
6513 11:17:49.247285 RX Vref Scan: 0
6514 11:17:49.247360
6515 11:17:49.250274 RX Vref 0 -> 0, step: 1
6516 11:17:49.250356
6517 11:17:49.254100 RX Delay -410 -> 252, step: 16
6518 11:17:49.257402 iDelay=230, Bit 0, Center -19 (-250 ~ 213) 464
6519 11:17:49.260513 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6520 11:17:49.266731 iDelay=230, Bit 2, Center -19 (-250 ~ 213) 464
6521 11:17:49.270399 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6522 11:17:49.273408 iDelay=230, Bit 4, Center -11 (-250 ~ 229) 480
6523 11:17:49.277077 iDelay=230, Bit 5, Center -27 (-266 ~ 213) 480
6524 11:17:49.283288 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6525 11:17:49.287021 iDelay=230, Bit 7, Center -3 (-234 ~ 229) 464
6526 11:17:49.290481 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6527 11:17:49.293534 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6528 11:17:49.300060 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6529 11:17:49.303705 iDelay=230, Bit 11, Center -35 (-266 ~ 197) 464
6530 11:17:49.306604 iDelay=230, Bit 12, Center -19 (-250 ~ 213) 464
6531 11:17:49.310161 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6532 11:17:49.316602 iDelay=230, Bit 14, Center -11 (-234 ~ 213) 448
6533 11:17:49.319922 iDelay=230, Bit 15, Center -19 (-250 ~ 213) 464
6534 11:17:49.320005 ==
6535 11:17:49.323166 Dram Type= 6, Freq= 0, CH_0, rank 1
6536 11:17:49.326749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6537 11:17:49.326834 ==
6538 11:17:49.330083 DQS Delay:
6539 11:17:49.330163 DQS0 = 27, DQS1 = 35
6540 11:17:49.333719 DQM Delay:
6541 11:17:49.333800 DQM0 = 11, DQM1 = 11
6542 11:17:49.333863 DQ Delay:
6543 11:17:49.336410 DQ0 =8, DQ1 =8, DQ2 =8, DQ3 =8
6544 11:17:49.339822 DQ4 =16, DQ5 =0, DQ6 =16, DQ7 =24
6545 11:17:49.343430 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6546 11:17:49.346927 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6547 11:17:49.347008
6548 11:17:49.347071
6549 11:17:49.347130 ==
6550 11:17:49.349644 Dram Type= 6, Freq= 0, CH_0, rank 1
6551 11:17:49.356671 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6552 11:17:49.356752 ==
6553 11:17:49.356816
6554 11:17:49.356873
6555 11:17:49.356930 TX Vref Scan disable
6556 11:17:49.359795 == TX Byte 0 ==
6557 11:17:49.363518 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6558 11:17:49.366545 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6559 11:17:49.369834 == TX Byte 1 ==
6560 11:17:49.372903 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6561 11:17:49.376508 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6562 11:17:49.376589 ==
6563 11:17:49.379823 Dram Type= 6, Freq= 0, CH_0, rank 1
6564 11:17:49.386748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6565 11:17:49.386829 ==
6566 11:17:49.386892
6567 11:17:49.386950
6568 11:17:49.387006 TX Vref Scan disable
6569 11:17:49.389766 == TX Byte 0 ==
6570 11:17:49.393224 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6571 11:17:49.396499 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6572 11:17:49.400056 == TX Byte 1 ==
6573 11:17:49.402880 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6574 11:17:49.406786 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6575 11:17:49.406867
6576 11:17:49.409878 [DATLAT]
6577 11:17:49.409958 Freq=400, CH0 RK1
6578 11:17:49.410022
6579 11:17:49.413619 DATLAT Default: 0xe
6580 11:17:49.413700 0, 0xFFFF, sum = 0
6581 11:17:49.416945 1, 0xFFFF, sum = 0
6582 11:17:49.417026 2, 0xFFFF, sum = 0
6583 11:17:49.419857 3, 0xFFFF, sum = 0
6584 11:17:49.419938 4, 0xFFFF, sum = 0
6585 11:17:49.423503 5, 0xFFFF, sum = 0
6586 11:17:49.423618 6, 0xFFFF, sum = 0
6587 11:17:49.426384 7, 0xFFFF, sum = 0
6588 11:17:49.426465 8, 0xFFFF, sum = 0
6589 11:17:49.430149 9, 0xFFFF, sum = 0
6590 11:17:49.430230 10, 0xFFFF, sum = 0
6591 11:17:49.433039 11, 0xFFFF, sum = 0
6592 11:17:49.433120 12, 0xFFFF, sum = 0
6593 11:17:49.436473 13, 0x0, sum = 1
6594 11:17:49.436555 14, 0x0, sum = 2
6595 11:17:49.439412 15, 0x0, sum = 3
6596 11:17:49.439524 16, 0x0, sum = 4
6597 11:17:49.442748 best_step = 14
6598 11:17:49.442829
6599 11:17:49.442893 ==
6600 11:17:49.446142 Dram Type= 6, Freq= 0, CH_0, rank 1
6601 11:17:49.449456 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6602 11:17:49.449562 ==
6603 11:17:49.452792 RX Vref Scan: 0
6604 11:17:49.452872
6605 11:17:49.452936 RX Vref 0 -> 0, step: 1
6606 11:17:49.452994
6607 11:17:49.456353 RX Delay -311 -> 252, step: 8
6608 11:17:49.463880 iDelay=217, Bit 0, Center -16 (-239 ~ 208) 448
6609 11:17:49.467569 iDelay=217, Bit 1, Center -12 (-231 ~ 208) 440
6610 11:17:49.470675 iDelay=217, Bit 2, Center -20 (-247 ~ 208) 456
6611 11:17:49.474404 iDelay=217, Bit 3, Center -16 (-239 ~ 208) 448
6612 11:17:49.480731 iDelay=217, Bit 4, Center -16 (-239 ~ 208) 448
6613 11:17:49.483887 iDelay=217, Bit 5, Center -24 (-247 ~ 200) 448
6614 11:17:49.487533 iDelay=217, Bit 6, Center -12 (-231 ~ 208) 440
6615 11:17:49.490678 iDelay=217, Bit 7, Center -8 (-231 ~ 216) 448
6616 11:17:49.497358 iDelay=217, Bit 8, Center -32 (-255 ~ 192) 448
6617 11:17:49.501008 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
6618 11:17:49.504247 iDelay=217, Bit 10, Center -20 (-239 ~ 200) 440
6619 11:17:49.507679 iDelay=217, Bit 11, Center -28 (-247 ~ 192) 440
6620 11:17:49.513873 iDelay=217, Bit 12, Center -16 (-239 ~ 208) 448
6621 11:17:49.517211 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
6622 11:17:49.521129 iDelay=217, Bit 14, Center -12 (-231 ~ 208) 440
6623 11:17:49.524200 iDelay=217, Bit 15, Center -16 (-239 ~ 208) 448
6624 11:17:49.527481 ==
6625 11:17:49.530781 Dram Type= 6, Freq= 0, CH_0, rank 1
6626 11:17:49.534379 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6627 11:17:49.534460 ==
6628 11:17:49.534524 DQS Delay:
6629 11:17:49.537192 DQS0 = 24, DQS1 = 32
6630 11:17:49.537272 DQM Delay:
6631 11:17:49.540698 DQM0 = 8, DQM1 = 10
6632 11:17:49.540778 DQ Delay:
6633 11:17:49.544059 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6634 11:17:49.547517 DQ4 =8, DQ5 =0, DQ6 =12, DQ7 =16
6635 11:17:49.550873 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6636 11:17:49.553876 DQ12 =16, DQ13 =16, DQ14 =20, DQ15 =16
6637 11:17:49.553956
6638 11:17:49.554020
6639 11:17:49.560907 [DQSOSCAuto] RK1, (LSB)MR18= 0xb959, (MSB)MR19= 0xc0c, tDQSOscB0 = 398 ps tDQSOscB1 = 386 ps
6640 11:17:49.563894 CH0 RK1: MR19=C0C, MR18=B959
6641 11:17:49.570915 CH0_RK1: MR19=0xC0C, MR18=0xB959, DQSOSC=386, MR23=63, INC=396, DEC=264
6642 11:17:49.573798 [RxdqsGatingPostProcess] freq 400
6643 11:17:49.577760 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6644 11:17:49.580897 best DQS0 dly(2T, 0.5T) = (0, 10)
6645 11:17:49.583883 best DQS1 dly(2T, 0.5T) = (0, 10)
6646 11:17:49.587550 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6647 11:17:49.590717 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6648 11:17:49.594509 best DQS0 dly(2T, 0.5T) = (0, 10)
6649 11:17:49.597379 best DQS1 dly(2T, 0.5T) = (0, 10)
6650 11:17:49.600487 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6651 11:17:49.604180 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6652 11:17:49.607285 Pre-setting of DQS Precalculation
6653 11:17:49.610955 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6654 11:17:49.611039 ==
6655 11:17:49.614281 Dram Type= 6, Freq= 0, CH_1, rank 0
6656 11:17:49.620529 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6657 11:17:49.620611 ==
6658 11:17:49.624371 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6659 11:17:49.630686 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6660 11:17:49.634265 [CA 0] Center 36 (8~64) winsize 57
6661 11:17:49.637039 [CA 1] Center 36 (8~64) winsize 57
6662 11:17:49.640278 [CA 2] Center 36 (8~64) winsize 57
6663 11:17:49.643819 [CA 3] Center 36 (8~64) winsize 57
6664 11:17:49.647359 [CA 4] Center 36 (8~64) winsize 57
6665 11:17:49.650289 [CA 5] Center 36 (8~64) winsize 57
6666 11:17:49.650370
6667 11:17:49.653677 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6668 11:17:49.653758
6669 11:17:49.657215 [CATrainingPosCal] consider 1 rank data
6670 11:17:49.660673 u2DelayCellTimex100 = 270/100 ps
6671 11:17:49.664012 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6672 11:17:49.667078 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6673 11:17:49.670366 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6674 11:17:49.674243 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6675 11:17:49.677246 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6676 11:17:49.680993 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6677 11:17:49.681074
6678 11:17:49.687118 CA PerBit enable=1, Macro0, CA PI delay=36
6679 11:17:49.687200
6680 11:17:49.690201 [CBTSetCACLKResult] CA Dly = 36
6681 11:17:49.690282 CS Dly: 1 (0~32)
6682 11:17:49.690346 ==
6683 11:17:49.693916 Dram Type= 6, Freq= 0, CH_1, rank 1
6684 11:17:49.696976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6685 11:17:49.697058 ==
6686 11:17:49.703285 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6687 11:17:49.710018 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6688 11:17:49.713814 [CA 0] Center 36 (8~64) winsize 57
6689 11:17:49.716944 [CA 1] Center 36 (8~64) winsize 57
6690 11:17:49.720232 [CA 2] Center 36 (8~64) winsize 57
6691 11:17:49.723730 [CA 3] Center 36 (8~64) winsize 57
6692 11:17:49.726673 [CA 4] Center 36 (8~64) winsize 57
6693 11:17:49.726754 [CA 5] Center 36 (8~64) winsize 57
6694 11:17:49.730271
6695 11:17:49.733517 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6696 11:17:49.733598
6697 11:17:49.736517 [CATrainingPosCal] consider 2 rank data
6698 11:17:49.740123 u2DelayCellTimex100 = 270/100 ps
6699 11:17:49.743142 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6700 11:17:49.746505 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6701 11:17:49.750324 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6702 11:17:49.753198 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6703 11:17:49.756796 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6704 11:17:49.760365 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6705 11:17:49.760446
6706 11:17:49.763125 CA PerBit enable=1, Macro0, CA PI delay=36
6707 11:17:49.763206
6708 11:17:49.766614 [CBTSetCACLKResult] CA Dly = 36
6709 11:17:49.769904 CS Dly: 1 (0~32)
6710 11:17:49.769984
6711 11:17:49.773420 ----->DramcWriteLeveling(PI) begin...
6712 11:17:49.773502 ==
6713 11:17:49.776326 Dram Type= 6, Freq= 0, CH_1, rank 0
6714 11:17:49.779940 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6715 11:17:49.780026 ==
6716 11:17:49.782934 Write leveling (Byte 0): 40 => 8
6717 11:17:49.786136 Write leveling (Byte 1): 40 => 8
6718 11:17:49.789932 DramcWriteLeveling(PI) end<-----
6719 11:17:49.790030
6720 11:17:49.790096 ==
6721 11:17:49.793061 Dram Type= 6, Freq= 0, CH_1, rank 0
6722 11:17:49.796090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6723 11:17:49.796171 ==
6724 11:17:49.799830 [Gating] SW mode calibration
6725 11:17:49.806175 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6726 11:17:49.813329 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6727 11:17:49.816364 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6728 11:17:49.823193 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6729 11:17:49.826317 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6730 11:17:49.829808 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6731 11:17:49.836686 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6732 11:17:49.839559 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6733 11:17:49.842665 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6734 11:17:49.846482 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6735 11:17:49.853060 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6736 11:17:49.855985 Total UI for P1: 0, mck2ui 16
6737 11:17:49.859809 best dqsien dly found for B0: ( 0, 14, 24)
6738 11:17:49.862767 Total UI for P1: 0, mck2ui 16
6739 11:17:49.866366 best dqsien dly found for B1: ( 0, 14, 24)
6740 11:17:49.869398 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6741 11:17:49.872926 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6742 11:17:49.873006
6743 11:17:49.876233 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6744 11:17:49.879592 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6745 11:17:49.882944 [Gating] SW calibration Done
6746 11:17:49.883038 ==
6747 11:17:49.885878 Dram Type= 6, Freq= 0, CH_1, rank 0
6748 11:17:49.889524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6749 11:17:49.889609 ==
6750 11:17:49.892809 RX Vref Scan: 0
6751 11:17:49.892888
6752 11:17:49.895758 RX Vref 0 -> 0, step: 1
6753 11:17:49.895840
6754 11:17:49.895904 RX Delay -410 -> 252, step: 16
6755 11:17:49.902756 iDelay=230, Bit 0, Center -11 (-250 ~ 229) 480
6756 11:17:49.906273 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6757 11:17:49.909453 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6758 11:17:49.912479 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6759 11:17:49.919061 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6760 11:17:49.922953 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6761 11:17:49.926065 iDelay=230, Bit 6, Center -11 (-250 ~ 229) 480
6762 11:17:49.929350 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6763 11:17:49.935553 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6764 11:17:49.939145 iDelay=230, Bit 9, Center -35 (-266 ~ 197) 464
6765 11:17:49.942281 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6766 11:17:49.946079 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6767 11:17:49.952593 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6768 11:17:49.956283 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6769 11:17:49.959333 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6770 11:17:49.965955 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6771 11:17:49.966121 ==
6772 11:17:49.969020 Dram Type= 6, Freq= 0, CH_1, rank 0
6773 11:17:49.972557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6774 11:17:49.972698 ==
6775 11:17:49.972779 DQS Delay:
6776 11:17:49.975418 DQS0 = 35, DQS1 = 35
6777 11:17:49.975529 DQM Delay:
6778 11:17:49.979161 DQM0 = 18, DQM1 = 13
6779 11:17:49.979407 DQ Delay:
6780 11:17:49.982633 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6781 11:17:49.985580 DQ4 =16, DQ5 =32, DQ6 =24, DQ7 =16
6782 11:17:49.989153 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6783 11:17:49.992107 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6784 11:17:49.992258
6785 11:17:49.992377
6786 11:17:49.992533 ==
6787 11:17:49.995652 Dram Type= 6, Freq= 0, CH_1, rank 0
6788 11:17:49.999300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6789 11:17:49.999528 ==
6790 11:17:49.999667
6791 11:17:49.999794
6792 11:17:50.002630 TX Vref Scan disable
6793 11:17:50.002837 == TX Byte 0 ==
6794 11:17:50.009271 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6795 11:17:50.012584 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6796 11:17:50.012998 == TX Byte 1 ==
6797 11:17:50.019501 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6798 11:17:50.022367 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6799 11:17:50.022726 ==
6800 11:17:50.026516 Dram Type= 6, Freq= 0, CH_1, rank 0
6801 11:17:50.029575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6802 11:17:50.029953 ==
6803 11:17:50.030243
6804 11:17:50.030505
6805 11:17:50.032969 TX Vref Scan disable
6806 11:17:50.036091 == TX Byte 0 ==
6807 11:17:50.039482 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6808 11:17:50.042426 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6809 11:17:50.042818 == TX Byte 1 ==
6810 11:17:50.049529 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6811 11:17:50.052685 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6812 11:17:50.053179
6813 11:17:50.053489 [DATLAT]
6814 11:17:50.056239 Freq=400, CH1 RK0
6815 11:17:50.056725
6816 11:17:50.057028 DATLAT Default: 0xf
6817 11:17:50.059707 0, 0xFFFF, sum = 0
6818 11:17:50.060211 1, 0xFFFF, sum = 0
6819 11:17:50.062946 2, 0xFFFF, sum = 0
6820 11:17:50.063465 3, 0xFFFF, sum = 0
6821 11:17:50.066159 4, 0xFFFF, sum = 0
6822 11:17:50.066658 5, 0xFFFF, sum = 0
6823 11:17:50.069439 6, 0xFFFF, sum = 0
6824 11:17:50.069830 7, 0xFFFF, sum = 0
6825 11:17:50.072565 8, 0xFFFF, sum = 0
6826 11:17:50.076088 9, 0xFFFF, sum = 0
6827 11:17:50.076582 10, 0xFFFF, sum = 0
6828 11:17:50.079476 11, 0xFFFF, sum = 0
6829 11:17:50.079869 12, 0xFFFF, sum = 0
6830 11:17:50.082652 13, 0x0, sum = 1
6831 11:17:50.083040 14, 0x0, sum = 2
6832 11:17:50.086333 15, 0x0, sum = 3
6833 11:17:50.086840 16, 0x0, sum = 4
6834 11:17:50.087158 best_step = 14
6835 11:17:50.087491
6836 11:17:50.089242 ==
6837 11:17:50.092751 Dram Type= 6, Freq= 0, CH_1, rank 0
6838 11:17:50.095745 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6839 11:17:50.096134 ==
6840 11:17:50.096439 RX Vref Scan: 1
6841 11:17:50.096741
6842 11:17:50.099208 RX Vref 0 -> 0, step: 1
6843 11:17:50.099616
6844 11:17:50.102973 RX Delay -311 -> 252, step: 8
6845 11:17:50.103615
6846 11:17:50.105774 Set Vref, RX VrefLevel [Byte0]: 51
6847 11:17:50.109186 [Byte1]: 53
6848 11:17:50.113134
6849 11:17:50.113670 Final RX Vref Byte 0 = 51 to rank0
6850 11:17:50.116440 Final RX Vref Byte 1 = 53 to rank0
6851 11:17:50.119400 Final RX Vref Byte 0 = 51 to rank1
6852 11:17:50.122503 Final RX Vref Byte 1 = 53 to rank1==
6853 11:17:50.126150 Dram Type= 6, Freq= 0, CH_1, rank 0
6854 11:17:50.132891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6855 11:17:50.133364 ==
6856 11:17:50.133658 DQS Delay:
6857 11:17:50.135818 DQS0 = 32, DQS1 = 32
6858 11:17:50.136182 DQM Delay:
6859 11:17:50.139147 DQM0 = 14, DQM1 = 10
6860 11:17:50.139700 DQ Delay:
6861 11:17:50.142157 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6862 11:17:50.145476 DQ4 =16, DQ5 =24, DQ6 =24, DQ7 =12
6863 11:17:50.149391 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6864 11:17:50.152246 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =24
6865 11:17:50.152755
6866 11:17:50.153069
6867 11:17:50.159452 [DQSOSCAuto] RK0, (LSB)MR18= 0x8cc4, (MSB)MR19= 0xc0c, tDQSOscB0 = 385 ps tDQSOscB1 = 392 ps
6868 11:17:50.162641 CH1 RK0: MR19=C0C, MR18=8CC4
6869 11:17:50.168785 CH1_RK0: MR19=0xC0C, MR18=0x8CC4, DQSOSC=385, MR23=63, INC=398, DEC=265
6870 11:17:50.169178 ==
6871 11:17:50.172275 Dram Type= 6, Freq= 0, CH_1, rank 1
6872 11:17:50.175515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6873 11:17:50.176018 ==
6874 11:17:50.178760 [Gating] SW mode calibration
6875 11:17:50.185545 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6876 11:17:50.191837 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6877 11:17:50.195455 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6878 11:17:50.198574 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6879 11:17:50.205795 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6880 11:17:50.208716 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6881 11:17:50.211928 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6882 11:17:50.218582 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6883 11:17:50.221404 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6884 11:17:50.225171 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6885 11:17:50.231900 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6886 11:17:50.232351 Total UI for P1: 0, mck2ui 16
6887 11:17:50.238141 best dqsien dly found for B0: ( 0, 14, 24)
6888 11:17:50.238636 Total UI for P1: 0, mck2ui 16
6889 11:17:50.245340 best dqsien dly found for B1: ( 0, 14, 24)
6890 11:17:50.248344 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6891 11:17:50.251809 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6892 11:17:50.252343
6893 11:17:50.255036 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6894 11:17:50.258570 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6895 11:17:50.261459 [Gating] SW calibration Done
6896 11:17:50.262119 ==
6897 11:17:50.265452 Dram Type= 6, Freq= 0, CH_1, rank 1
6898 11:17:50.268294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6899 11:17:50.268736 ==
6900 11:17:50.271759 RX Vref Scan: 0
6901 11:17:50.272300
6902 11:17:50.272752 RX Vref 0 -> 0, step: 1
6903 11:17:50.273174
6904 11:17:50.274878 RX Delay -410 -> 252, step: 16
6905 11:17:50.281191 iDelay=230, Bit 0, Center -11 (-234 ~ 213) 448
6906 11:17:50.284399 iDelay=230, Bit 1, Center -19 (-250 ~ 213) 464
6907 11:17:50.288188 iDelay=230, Bit 2, Center -35 (-266 ~ 197) 464
6908 11:17:50.291616 iDelay=230, Bit 3, Center -19 (-250 ~ 213) 464
6909 11:17:50.298649 iDelay=230, Bit 4, Center -19 (-250 ~ 213) 464
6910 11:17:50.301260 iDelay=230, Bit 5, Center -3 (-234 ~ 229) 464
6911 11:17:50.304760 iDelay=230, Bit 6, Center -3 (-234 ~ 229) 464
6912 11:17:50.308107 iDelay=230, Bit 7, Center -19 (-250 ~ 213) 464
6913 11:17:50.314764 iDelay=230, Bit 8, Center -35 (-266 ~ 197) 464
6914 11:17:50.317743 iDelay=230, Bit 9, Center -27 (-266 ~ 213) 480
6915 11:17:50.321081 iDelay=230, Bit 10, Center -19 (-250 ~ 213) 464
6916 11:17:50.324107 iDelay=230, Bit 11, Center -27 (-266 ~ 213) 480
6917 11:17:50.331002 iDelay=230, Bit 12, Center -11 (-250 ~ 229) 480
6918 11:17:50.334222 iDelay=230, Bit 13, Center -19 (-250 ~ 213) 464
6919 11:17:50.338205 iDelay=230, Bit 14, Center -19 (-250 ~ 213) 464
6920 11:17:50.341237 iDelay=230, Bit 15, Center -11 (-250 ~ 229) 480
6921 11:17:50.341644 ==
6922 11:17:50.344401 Dram Type= 6, Freq= 0, CH_1, rank 1
6923 11:17:50.350944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6924 11:17:50.351474 ==
6925 11:17:50.351894 DQS Delay:
6926 11:17:50.354812 DQS0 = 35, DQS1 = 35
6927 11:17:50.355304 DQM Delay:
6928 11:17:50.357922 DQM0 = 19, DQM1 = 14
6929 11:17:50.358422 DQ Delay:
6930 11:17:50.360943 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6931 11:17:50.364792 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6932 11:17:50.367798 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6933 11:17:50.371314 DQ12 =24, DQ13 =16, DQ14 =16, DQ15 =24
6934 11:17:50.371968
6935 11:17:50.372388
6936 11:17:50.372688 ==
6937 11:17:50.374186 Dram Type= 6, Freq= 0, CH_1, rank 1
6938 11:17:50.377581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6939 11:17:50.378073 ==
6940 11:17:50.378388
6941 11:17:50.378672
6942 11:17:50.381364 TX Vref Scan disable
6943 11:17:50.381851 == TX Byte 0 ==
6944 11:17:50.387751 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6945 11:17:50.391204 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6946 11:17:50.391624 == TX Byte 1 ==
6947 11:17:50.397404 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6948 11:17:50.401318 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6949 11:17:50.401806 ==
6950 11:17:50.404286 Dram Type= 6, Freq= 0, CH_1, rank 1
6951 11:17:50.407801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6952 11:17:50.408298 ==
6953 11:17:50.408611
6954 11:17:50.408897
6955 11:17:50.410625 TX Vref Scan disable
6956 11:17:50.411060 == TX Byte 0 ==
6957 11:17:50.417551 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6958 11:17:50.420540 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6959 11:17:50.420960 == TX Byte 1 ==
6960 11:17:50.427555 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6961 11:17:50.430500 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6962 11:17:50.430885
6963 11:17:50.431189 [DATLAT]
6964 11:17:50.434118 Freq=400, CH1 RK1
6965 11:17:50.434504
6966 11:17:50.434806 DATLAT Default: 0xe
6967 11:17:50.437655 0, 0xFFFF, sum = 0
6968 11:17:50.438144 1, 0xFFFF, sum = 0
6969 11:17:50.441151 2, 0xFFFF, sum = 0
6970 11:17:50.441657 3, 0xFFFF, sum = 0
6971 11:17:50.443763 4, 0xFFFF, sum = 0
6972 11:17:50.444155 5, 0xFFFF, sum = 0
6973 11:17:50.447671 6, 0xFFFF, sum = 0
6974 11:17:50.448167 7, 0xFFFF, sum = 0
6975 11:17:50.450890 8, 0xFFFF, sum = 0
6976 11:17:50.451412 9, 0xFFFF, sum = 0
6977 11:17:50.454113 10, 0xFFFF, sum = 0
6978 11:17:50.457243 11, 0xFFFF, sum = 0
6979 11:17:50.457734 12, 0xFFFF, sum = 0
6980 11:17:50.460341 13, 0x0, sum = 1
6981 11:17:50.460835 14, 0x0, sum = 2
6982 11:17:50.461154 15, 0x0, sum = 3
6983 11:17:50.464254 16, 0x0, sum = 4
6984 11:17:50.464747 best_step = 14
6985 11:17:50.465054
6986 11:17:50.467360 ==
6987 11:17:50.470614 Dram Type= 6, Freq= 0, CH_1, rank 1
6988 11:17:50.474019 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6989 11:17:50.474511 ==
6990 11:17:50.474821 RX Vref Scan: 0
6991 11:17:50.475104
6992 11:17:50.476864 RX Vref 0 -> 0, step: 1
6993 11:17:50.477251
6994 11:17:50.480529 RX Delay -311 -> 252, step: 8
6995 11:17:50.487172 iDelay=217, Bit 0, Center -12 (-231 ~ 208) 440
6996 11:17:50.490690 iDelay=217, Bit 1, Center -20 (-239 ~ 200) 440
6997 11:17:50.493492 iDelay=217, Bit 2, Center -28 (-247 ~ 192) 440
6998 11:17:50.497051 iDelay=217, Bit 3, Center -20 (-239 ~ 200) 440
6999 11:17:50.503619 iDelay=217, Bit 4, Center -20 (-239 ~ 200) 440
7000 11:17:50.507407 iDelay=217, Bit 5, Center -4 (-223 ~ 216) 440
7001 11:17:50.510334 iDelay=217, Bit 6, Center -8 (-231 ~ 216) 448
7002 11:17:50.513660 iDelay=217, Bit 7, Center -20 (-239 ~ 200) 440
7003 11:17:50.520516 iDelay=217, Bit 8, Center -36 (-263 ~ 192) 456
7004 11:17:50.523415 iDelay=217, Bit 9, Center -32 (-255 ~ 192) 448
7005 11:17:50.527019 iDelay=217, Bit 10, Center -16 (-239 ~ 208) 448
7006 11:17:50.530470 iDelay=217, Bit 11, Center -28 (-255 ~ 200) 456
7007 11:17:50.537568 iDelay=217, Bit 12, Center -12 (-239 ~ 216) 456
7008 11:17:50.540431 iDelay=217, Bit 13, Center -16 (-239 ~ 208) 448
7009 11:17:50.543913 iDelay=217, Bit 14, Center -16 (-239 ~ 208) 448
7010 11:17:50.547025 iDelay=217, Bit 15, Center -12 (-239 ~ 216) 456
7011 11:17:50.550651 ==
7012 11:17:50.551141 Dram Type= 6, Freq= 0, CH_1, rank 1
7013 11:17:50.557433 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7014 11:17:50.557920 ==
7015 11:17:50.558229 DQS Delay:
7016 11:17:50.560418 DQS0 = 28, DQS1 = 36
7017 11:17:50.560799 DQM Delay:
7018 11:17:50.563956 DQM0 = 11, DQM1 = 15
7019 11:17:50.564338 DQ Delay:
7020 11:17:50.567436 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7021 11:17:50.570986 DQ4 =8, DQ5 =24, DQ6 =20, DQ7 =8
7022 11:17:50.571513 DQ8 =0, DQ9 =4, DQ10 =20, DQ11 =8
7023 11:17:50.577372 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =24
7024 11:17:50.577857
7025 11:17:50.578160
7026 11:17:50.584065 [DQSOSCAuto] RK1, (LSB)MR18= 0xc253, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 385 ps
7027 11:17:50.587234 CH1 RK1: MR19=C0C, MR18=C253
7028 11:17:50.594001 CH1_RK1: MR19=0xC0C, MR18=0xC253, DQSOSC=385, MR23=63, INC=398, DEC=265
7029 11:17:50.597225 [RxdqsGatingPostProcess] freq 400
7030 11:17:50.601282 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7031 11:17:50.604213 best DQS0 dly(2T, 0.5T) = (0, 10)
7032 11:17:50.607271 best DQS1 dly(2T, 0.5T) = (0, 10)
7033 11:17:50.610455 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7034 11:17:50.613934 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7035 11:17:50.616877 best DQS0 dly(2T, 0.5T) = (0, 10)
7036 11:17:50.620742 best DQS1 dly(2T, 0.5T) = (0, 10)
7037 11:17:50.623815 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7038 11:17:50.627183 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7039 11:17:50.630496 Pre-setting of DQS Precalculation
7040 11:17:50.634129 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7041 11:17:50.640397 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7042 11:17:50.650614 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7043 11:17:50.651127
7044 11:17:50.651502
7045 11:17:50.653743 [Calibration Summary] 800 Mbps
7046 11:17:50.654255 CH 0, Rank 0
7047 11:17:50.657327 SW Impedance : PASS
7048 11:17:50.657860 DUTY Scan : NO K
7049 11:17:50.660237 ZQ Calibration : PASS
7050 11:17:50.660651 Jitter Meter : NO K
7051 11:17:50.663662 CBT Training : PASS
7052 11:17:50.667319 Write leveling : PASS
7053 11:17:50.667764 RX DQS gating : PASS
7054 11:17:50.670658 RX DQ/DQS(RDDQC) : PASS
7055 11:17:50.674000 TX DQ/DQS : PASS
7056 11:17:50.674490 RX DATLAT : PASS
7057 11:17:50.677200 RX DQ/DQS(Engine): PASS
7058 11:17:50.680133 TX OE : NO K
7059 11:17:50.680530 All Pass.
7060 11:17:50.680838
7061 11:17:50.681123 CH 0, Rank 1
7062 11:17:50.683801 SW Impedance : PASS
7063 11:17:50.686719 DUTY Scan : NO K
7064 11:17:50.687113 ZQ Calibration : PASS
7065 11:17:50.689906 Jitter Meter : NO K
7066 11:17:50.693616 CBT Training : PASS
7067 11:17:50.694018 Write leveling : NO K
7068 11:17:50.696514 RX DQS gating : PASS
7069 11:17:50.700497 RX DQ/DQS(RDDQC) : PASS
7070 11:17:50.700979 TX DQ/DQS : PASS
7071 11:17:50.703677 RX DATLAT : PASS
7072 11:17:50.706700 RX DQ/DQS(Engine): PASS
7073 11:17:50.707139 TX OE : NO K
7074 11:17:50.707504 All Pass.
7075 11:17:50.707816
7076 11:17:50.710361 CH 1, Rank 0
7077 11:17:50.710744 SW Impedance : PASS
7078 11:17:50.713855 DUTY Scan : NO K
7079 11:17:50.716867 ZQ Calibration : PASS
7080 11:17:50.717289 Jitter Meter : NO K
7081 11:17:50.720046 CBT Training : PASS
7082 11:17:50.723999 Write leveling : PASS
7083 11:17:50.724435 RX DQS gating : PASS
7084 11:17:50.727152 RX DQ/DQS(RDDQC) : PASS
7085 11:17:50.730136 TX DQ/DQS : PASS
7086 11:17:50.730550 RX DATLAT : PASS
7087 11:17:50.734097 RX DQ/DQS(Engine): PASS
7088 11:17:50.736940 TX OE : NO K
7089 11:17:50.737362 All Pass.
7090 11:17:50.737695
7091 11:17:50.737998 CH 1, Rank 1
7092 11:17:50.740615 SW Impedance : PASS
7093 11:17:50.743666 DUTY Scan : NO K
7094 11:17:50.744051 ZQ Calibration : PASS
7095 11:17:50.747002 Jitter Meter : NO K
7096 11:17:50.749943 CBT Training : PASS
7097 11:17:50.750322 Write leveling : NO K
7098 11:17:50.753779 RX DQS gating : PASS
7099 11:17:50.754267 RX DQ/DQS(RDDQC) : PASS
7100 11:17:50.757478 TX DQ/DQS : PASS
7101 11:17:50.760673 RX DATLAT : PASS
7102 11:17:50.761108 RX DQ/DQS(Engine): PASS
7103 11:17:50.763779 TX OE : NO K
7104 11:17:50.764197 All Pass.
7105 11:17:50.764524
7106 11:17:50.766743 DramC Write-DBI off
7107 11:17:50.770475 PER_BANK_REFRESH: Hybrid Mode
7108 11:17:50.770859 TX_TRACKING: ON
7109 11:17:50.780216 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7110 11:17:50.783674 [FAST_K] Save calibration result to emmc
7111 11:17:50.786867 dramc_set_vcore_voltage set vcore to 725000
7112 11:17:50.790455 Read voltage for 1600, 0
7113 11:17:50.790974 Vio18 = 0
7114 11:17:50.793603 Vcore = 725000
7115 11:17:50.794016 Vdram = 0
7116 11:17:50.794344 Vddq = 0
7117 11:17:50.794649 Vmddr = 0
7118 11:17:50.799972 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7119 11:17:50.803721 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7120 11:17:50.806899 MEM_TYPE=3, freq_sel=13
7121 11:17:50.810059 sv_algorithm_assistance_LP4_3733
7122 11:17:50.814021 ============ PULL DRAM RESETB DOWN ============
7123 11:17:50.819955 ========== PULL DRAM RESETB DOWN end =========
7124 11:17:50.823218 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7125 11:17:50.826407 ===================================
7126 11:17:50.829972 LPDDR4 DRAM CONFIGURATION
7127 11:17:50.834026 ===================================
7128 11:17:50.834603 EX_ROW_EN[0] = 0x0
7129 11:17:50.837226 EX_ROW_EN[1] = 0x0
7130 11:17:50.837753 LP4Y_EN = 0x0
7131 11:17:50.840039 WORK_FSP = 0x1
7132 11:17:50.840464 WL = 0x5
7133 11:17:50.843175 RL = 0x5
7134 11:17:50.843635 BL = 0x2
7135 11:17:50.846663 RPST = 0x0
7136 11:17:50.847247 RD_PRE = 0x0
7137 11:17:50.850095 WR_PRE = 0x1
7138 11:17:50.850532 WR_PST = 0x1
7139 11:17:50.853127 DBI_WR = 0x0
7140 11:17:50.856674 DBI_RD = 0x0
7141 11:17:50.857087 OTF = 0x1
7142 11:17:50.860436 ===================================
7143 11:17:50.863323 ===================================
7144 11:17:50.863779 ANA top config
7145 11:17:50.866816 ===================================
7146 11:17:50.870141 DLL_ASYNC_EN = 0
7147 11:17:50.873030 ALL_SLAVE_EN = 0
7148 11:17:50.876467 NEW_RANK_MODE = 1
7149 11:17:50.876851 DLL_IDLE_MODE = 1
7150 11:17:50.879803 LP45_APHY_COMB_EN = 1
7151 11:17:50.883396 TX_ODT_DIS = 0
7152 11:17:50.886604 NEW_8X_MODE = 1
7153 11:17:50.890114 ===================================
7154 11:17:50.893056 ===================================
7155 11:17:50.896113 data_rate = 3200
7156 11:17:50.899950 CKR = 1
7157 11:17:50.900371 DQ_P2S_RATIO = 8
7158 11:17:50.903076 ===================================
7159 11:17:50.907072 CA_P2S_RATIO = 8
7160 11:17:50.909834 DQ_CA_OPEN = 0
7161 11:17:50.913074 DQ_SEMI_OPEN = 0
7162 11:17:50.916276 CA_SEMI_OPEN = 0
7163 11:17:50.919995 CA_FULL_RATE = 0
7164 11:17:50.920376 DQ_CKDIV4_EN = 0
7165 11:17:50.923231 CA_CKDIV4_EN = 0
7166 11:17:50.926608 CA_PREDIV_EN = 0
7167 11:17:50.930087 PH8_DLY = 12
7168 11:17:50.932867 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7169 11:17:50.936079 DQ_AAMCK_DIV = 4
7170 11:17:50.936464 CA_AAMCK_DIV = 4
7171 11:17:50.939297 CA_ADMCK_DIV = 4
7172 11:17:50.942923 DQ_TRACK_CA_EN = 0
7173 11:17:50.946198 CA_PICK = 1600
7174 11:17:50.949150 CA_MCKIO = 1600
7175 11:17:50.952641 MCKIO_SEMI = 0
7176 11:17:50.956245 PLL_FREQ = 3068
7177 11:17:50.956655 DQ_UI_PI_RATIO = 32
7178 11:17:50.959369 CA_UI_PI_RATIO = 0
7179 11:17:50.963034 ===================================
7180 11:17:50.966089 ===================================
7181 11:17:50.969085 memory_type:LPDDR4
7182 11:17:50.972437 GP_NUM : 10
7183 11:17:50.972947 SRAM_EN : 1
7184 11:17:50.975783 MD32_EN : 0
7185 11:17:50.979481 ===================================
7186 11:17:50.982647 [ANA_INIT] >>>>>>>>>>>>>>
7187 11:17:50.983035 <<<<<< [CONFIGURE PHASE]: ANA_TX
7188 11:17:50.985771 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7189 11:17:50.989425 ===================================
7190 11:17:50.992655 data_rate = 3200,PCW = 0X7600
7191 11:17:50.995955 ===================================
7192 11:17:50.999168 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7193 11:17:51.005640 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7194 11:17:51.012348 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7195 11:17:51.015778 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7196 11:17:51.018840 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7197 11:17:51.022431 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7198 11:17:51.025782 [ANA_INIT] flow start
7199 11:17:51.026283 [ANA_INIT] PLL >>>>>>>>
7200 11:17:51.029619 [ANA_INIT] PLL <<<<<<<<
7201 11:17:51.033143 [ANA_INIT] MIDPI >>>>>>>>
7202 11:17:51.033629 [ANA_INIT] MIDPI <<<<<<<<
7203 11:17:51.035920 [ANA_INIT] DLL >>>>>>>>
7204 11:17:51.039419 [ANA_INIT] DLL <<<<<<<<
7205 11:17:51.039808 [ANA_INIT] flow end
7206 11:17:51.046063 ============ LP4 DIFF to SE enter ============
7207 11:17:51.049206 ============ LP4 DIFF to SE exit ============
7208 11:17:51.052429 [ANA_INIT] <<<<<<<<<<<<<
7209 11:17:51.056205 [Flow] Enable top DCM control >>>>>
7210 11:17:51.059589 [Flow] Enable top DCM control <<<<<
7211 11:17:51.060114 Enable DLL master slave shuffle
7212 11:17:51.066033 ==============================================================
7213 11:17:51.069567 Gating Mode config
7214 11:17:51.072349 ==============================================================
7215 11:17:51.076133 Config description:
7216 11:17:51.085616 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7217 11:17:51.092722 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7218 11:17:51.095794 SELPH_MODE 0: By rank 1: By Phase
7219 11:17:51.102922 ==============================================================
7220 11:17:51.105841 GAT_TRACK_EN = 1
7221 11:17:51.108896 RX_GATING_MODE = 2
7222 11:17:51.113038 RX_GATING_TRACK_MODE = 2
7223 11:17:51.113536 SELPH_MODE = 1
7224 11:17:51.115934 PICG_EARLY_EN = 1
7225 11:17:51.119196 VALID_LAT_VALUE = 1
7226 11:17:51.126057 ==============================================================
7227 11:17:51.128949 Enter into Gating configuration >>>>
7228 11:17:51.132707 Exit from Gating configuration <<<<
7229 11:17:51.136092 Enter into DVFS_PRE_config >>>>>
7230 11:17:51.145720 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7231 11:17:51.149720 Exit from DVFS_PRE_config <<<<<
7232 11:17:51.152756 Enter into PICG configuration >>>>
7233 11:17:51.156204 Exit from PICG configuration <<<<
7234 11:17:51.159228 [RX_INPUT] configuration >>>>>
7235 11:17:51.162131 [RX_INPUT] configuration <<<<<
7236 11:17:51.166338 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7237 11:17:51.172652 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7238 11:17:51.179078 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7239 11:17:51.185515 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7240 11:17:51.189680 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7241 11:17:51.196113 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7242 11:17:51.199231 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7243 11:17:51.205808 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7244 11:17:51.209198 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7245 11:17:51.212230 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7246 11:17:51.215967 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7247 11:17:51.222088 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7248 11:17:51.225926 ===================================
7249 11:17:51.226445 LPDDR4 DRAM CONFIGURATION
7250 11:17:51.228986 ===================================
7251 11:17:51.232161 EX_ROW_EN[0] = 0x0
7252 11:17:51.235767 EX_ROW_EN[1] = 0x0
7253 11:17:51.236197 LP4Y_EN = 0x0
7254 11:17:51.238692 WORK_FSP = 0x1
7255 11:17:51.239119 WL = 0x5
7256 11:17:51.242175 RL = 0x5
7257 11:17:51.242598 BL = 0x2
7258 11:17:51.245654 RPST = 0x0
7259 11:17:51.246186 RD_PRE = 0x0
7260 11:17:51.248538 WR_PRE = 0x1
7261 11:17:51.248963 WR_PST = 0x1
7262 11:17:51.252526 DBI_WR = 0x0
7263 11:17:51.252954 DBI_RD = 0x0
7264 11:17:51.255674 OTF = 0x1
7265 11:17:51.258907 ===================================
7266 11:17:51.261981 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7267 11:17:51.265738 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7268 11:17:51.272301 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7269 11:17:51.275645 ===================================
7270 11:17:51.276188 LPDDR4 DRAM CONFIGURATION
7271 11:17:51.278679 ===================================
7272 11:17:51.282107 EX_ROW_EN[0] = 0x10
7273 11:17:51.285488 EX_ROW_EN[1] = 0x0
7274 11:17:51.285917 LP4Y_EN = 0x0
7275 11:17:51.288569 WORK_FSP = 0x1
7276 11:17:51.288993 WL = 0x5
7277 11:17:51.292072 RL = 0x5
7278 11:17:51.292618 BL = 0x2
7279 11:17:51.295429 RPST = 0x0
7280 11:17:51.295855 RD_PRE = 0x0
7281 11:17:51.298456 WR_PRE = 0x1
7282 11:17:51.298878 WR_PST = 0x1
7283 11:17:51.301890 DBI_WR = 0x0
7284 11:17:51.302315 DBI_RD = 0x0
7285 11:17:51.305706 OTF = 0x1
7286 11:17:51.308479 ===================================
7287 11:17:51.315051 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7288 11:17:51.315506 ==
7289 11:17:51.318871 Dram Type= 6, Freq= 0, CH_0, rank 0
7290 11:17:51.322373 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7291 11:17:51.322840 ==
7292 11:17:51.325246 [Duty_Offset_Calibration]
7293 11:17:51.325679 B0:2 B1:1 CA:1
7294 11:17:51.326117
7295 11:17:51.328494 [DutyScan_Calibration_Flow] k_type=0
7296 11:17:51.338712
7297 11:17:51.339213 ==CLK 0==
7298 11:17:51.342347 Final CLK duty delay cell = 0
7299 11:17:51.346109 [0] MAX Duty = 5156%(X100), DQS PI = 22
7300 11:17:51.348805 [0] MIN Duty = 4907%(X100), DQS PI = 0
7301 11:17:51.349330 [0] AVG Duty = 5031%(X100)
7302 11:17:51.352263
7303 11:17:51.355754 CH0 CLK Duty spec in!! Max-Min= 249%
7304 11:17:51.359444 [DutyScan_Calibration_Flow] ====Done====
7305 11:17:51.359970
7306 11:17:51.362743 [DutyScan_Calibration_Flow] k_type=1
7307 11:17:51.378537
7308 11:17:51.379050 ==DQS 0 ==
7309 11:17:51.381770 Final DQS duty delay cell = -4
7310 11:17:51.385008 [-4] MAX Duty = 5156%(X100), DQS PI = 26
7311 11:17:51.387798 [-4] MIN Duty = 4688%(X100), DQS PI = 0
7312 11:17:51.391857 [-4] AVG Duty = 4922%(X100)
7313 11:17:51.392346
7314 11:17:51.392700 ==DQS 1 ==
7315 11:17:51.394950 Final DQS duty delay cell = 0
7316 11:17:51.398164 [0] MAX Duty = 5187%(X100), DQS PI = 20
7317 11:17:51.401448 [0] MIN Duty = 5062%(X100), DQS PI = 34
7318 11:17:51.405001 [0] AVG Duty = 5124%(X100)
7319 11:17:51.405537
7320 11:17:51.407785 CH0 DQS 0 Duty spec in!! Max-Min= 468%
7321 11:17:51.408206
7322 11:17:51.411438 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7323 11:17:51.414602 [DutyScan_Calibration_Flow] ====Done====
7324 11:17:51.415123
7325 11:17:51.417852 [DutyScan_Calibration_Flow] k_type=3
7326 11:17:51.435454
7327 11:17:51.435942 ==DQM 0 ==
7328 11:17:51.439536 Final DQM duty delay cell = 0
7329 11:17:51.442614 [0] MAX Duty = 5218%(X100), DQS PI = 34
7330 11:17:51.445565 [0] MIN Duty = 4875%(X100), DQS PI = 60
7331 11:17:51.448622 [0] AVG Duty = 5046%(X100)
7332 11:17:51.449043
7333 11:17:51.449373 ==DQM 1 ==
7334 11:17:51.452337 Final DQM duty delay cell = 0
7335 11:17:51.455424 [0] MAX Duty = 5187%(X100), DQS PI = 2
7336 11:17:51.459295 [0] MIN Duty = 5062%(X100), DQS PI = 48
7337 11:17:51.462444 [0] AVG Duty = 5124%(X100)
7338 11:17:51.462964
7339 11:17:51.465441 CH0 DQM 0 Duty spec in!! Max-Min= 343%
7340 11:17:51.465862
7341 11:17:51.468884 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7342 11:17:51.471955 [DutyScan_Calibration_Flow] ====Done====
7343 11:17:51.472376
7344 11:17:51.475733 [DutyScan_Calibration_Flow] k_type=2
7345 11:17:51.492634
7346 11:17:51.493122 ==DQ 0 ==
7347 11:17:51.495817 Final DQ duty delay cell = 0
7348 11:17:51.499192 [0] MAX Duty = 5062%(X100), DQS PI = 24
7349 11:17:51.503132 [0] MIN Duty = 4907%(X100), DQS PI = 0
7350 11:17:51.503691 [0] AVG Duty = 4984%(X100)
7351 11:17:51.504033
7352 11:17:51.506145 ==DQ 1 ==
7353 11:17:51.509649 Final DQ duty delay cell = 0
7354 11:17:51.512497 [0] MAX Duty = 5125%(X100), DQS PI = 6
7355 11:17:51.516090 [0] MIN Duty = 4907%(X100), DQS PI = 34
7356 11:17:51.516522 [0] AVG Duty = 5016%(X100)
7357 11:17:51.516859
7358 11:17:51.519784 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7359 11:17:51.520207
7360 11:17:51.522623 CH0 DQ 1 Duty spec in!! Max-Min= 218%
7361 11:17:51.528989 [DutyScan_Calibration_Flow] ====Done====
7362 11:17:51.529399 ==
7363 11:17:51.532334 Dram Type= 6, Freq= 0, CH_1, rank 0
7364 11:17:51.535970 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7365 11:17:51.536377 ==
7366 11:17:51.539156 [Duty_Offset_Calibration]
7367 11:17:51.539623 B0:1 B1:0 CA:0
7368 11:17:51.539948
7369 11:17:51.542564 [DutyScan_Calibration_Flow] k_type=0
7370 11:17:51.552096
7371 11:17:51.552467 ==CLK 0==
7372 11:17:51.554946 Final CLK duty delay cell = -4
7373 11:17:51.558414 [-4] MAX Duty = 5000%(X100), DQS PI = 22
7374 11:17:51.561948 [-4] MIN Duty = 4844%(X100), DQS PI = 52
7375 11:17:51.564904 [-4] AVG Duty = 4922%(X100)
7376 11:17:51.565380
7377 11:17:51.568274 CH1 CLK Duty spec in!! Max-Min= 156%
7378 11:17:51.571952 [DutyScan_Calibration_Flow] ====Done====
7379 11:17:51.572324
7380 11:17:51.575167 [DutyScan_Calibration_Flow] k_type=1
7381 11:17:51.591737
7382 11:17:51.592128 ==DQS 0 ==
7383 11:17:51.595597 Final DQS duty delay cell = 0
7384 11:17:51.598762 [0] MAX Duty = 5094%(X100), DQS PI = 28
7385 11:17:51.601870 [0] MIN Duty = 4844%(X100), DQS PI = 0
7386 11:17:51.602244 [0] AVG Duty = 4969%(X100)
7387 11:17:51.605208
7388 11:17:51.605578 ==DQS 1 ==
7389 11:17:51.608645 Final DQS duty delay cell = 0
7390 11:17:51.611837 [0] MAX Duty = 5249%(X100), DQS PI = 16
7391 11:17:51.615787 [0] MIN Duty = 4938%(X100), DQS PI = 8
7392 11:17:51.616265 [0] AVG Duty = 5093%(X100)
7393 11:17:51.618363
7394 11:17:51.621948 CH1 DQS 0 Duty spec in!! Max-Min= 250%
7395 11:17:51.622321
7396 11:17:51.625473 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7397 11:17:51.628295 [DutyScan_Calibration_Flow] ====Done====
7398 11:17:51.628693
7399 11:17:51.631511 [DutyScan_Calibration_Flow] k_type=3
7400 11:17:51.648978
7401 11:17:51.649490 ==DQM 0 ==
7402 11:17:51.651922 Final DQM duty delay cell = 0
7403 11:17:51.655091 [0] MAX Duty = 5218%(X100), DQS PI = 18
7404 11:17:51.658963 [0] MIN Duty = 4969%(X100), DQS PI = 48
7405 11:17:51.661821 [0] AVG Duty = 5093%(X100)
7406 11:17:51.662243
7407 11:17:51.662567 ==DQM 1 ==
7408 11:17:51.665748 Final DQM duty delay cell = 0
7409 11:17:51.669021 [0] MAX Duty = 5093%(X100), DQS PI = 16
7410 11:17:51.671910 [0] MIN Duty = 4938%(X100), DQS PI = 8
7411 11:17:51.675405 [0] AVG Duty = 5015%(X100)
7412 11:17:51.675917
7413 11:17:51.679250 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7414 11:17:51.679817
7415 11:17:51.682151 CH1 DQM 1 Duty spec in!! Max-Min= 155%
7416 11:17:51.685144 [DutyScan_Calibration_Flow] ====Done====
7417 11:17:51.685554
7418 11:17:51.688587 [DutyScan_Calibration_Flow] k_type=2
7419 11:17:51.705412
7420 11:17:51.705923 ==DQ 0 ==
7421 11:17:51.708535 Final DQ duty delay cell = -4
7422 11:17:51.711929 [-4] MAX Duty = 5062%(X100), DQS PI = 12
7423 11:17:51.715109 [-4] MIN Duty = 4875%(X100), DQS PI = 46
7424 11:17:51.718225 [-4] AVG Duty = 4968%(X100)
7425 11:17:51.718737
7426 11:17:51.719062 ==DQ 1 ==
7427 11:17:51.721720 Final DQ duty delay cell = 0
7428 11:17:51.724859 [0] MAX Duty = 5124%(X100), DQS PI = 16
7429 11:17:51.728374 [0] MIN Duty = 4938%(X100), DQS PI = 10
7430 11:17:51.731402 [0] AVG Duty = 5031%(X100)
7431 11:17:51.731816
7432 11:17:51.735138 CH1 DQ 0 Duty spec in!! Max-Min= 187%
7433 11:17:51.735705
7434 11:17:51.738255 CH1 DQ 1 Duty spec in!! Max-Min= 186%
7435 11:17:51.741711 [DutyScan_Calibration_Flow] ====Done====
7436 11:17:51.745192 nWR fixed to 30
7437 11:17:51.745607 [ModeRegInit_LP4] CH0 RK0
7438 11:17:51.747991 [ModeRegInit_LP4] CH0 RK1
7439 11:17:51.751686 [ModeRegInit_LP4] CH1 RK0
7440 11:17:51.754644 [ModeRegInit_LP4] CH1 RK1
7441 11:17:51.755052 match AC timing 5
7442 11:17:51.761874 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7443 11:17:51.765042 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7444 11:17:51.768159 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7445 11:17:51.774915 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7446 11:17:51.778152 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7447 11:17:51.778565 [MiockJmeterHQA]
7448 11:17:51.778892
7449 11:17:51.781343 [DramcMiockJmeter] u1RxGatingPI = 0
7450 11:17:51.784625 0 : 4252, 4027
7451 11:17:51.785053 4 : 4363, 4138
7452 11:17:51.787861 8 : 4255, 4029
7453 11:17:51.788284 12 : 4252, 4027
7454 11:17:51.788619 16 : 4253, 4027
7455 11:17:51.791012 20 : 4252, 4027
7456 11:17:51.791567 24 : 4252, 4027
7457 11:17:51.794739 28 : 4363, 4137
7458 11:17:51.795156 32 : 4253, 4027
7459 11:17:51.797983 36 : 4363, 4137
7460 11:17:51.798397 40 : 4252, 4027
7461 11:17:51.801242 44 : 4255, 4030
7462 11:17:51.801655 48 : 4252, 4026
7463 11:17:51.801984 52 : 4363, 4138
7464 11:17:51.804622 56 : 4252, 4027
7465 11:17:51.805134 60 : 4361, 4138
7466 11:17:51.807596 64 : 4250, 4027
7467 11:17:51.808104 68 : 4250, 4027
7468 11:17:51.811419 72 : 4250, 4027
7469 11:17:51.811916 76 : 4250, 4027
7470 11:17:51.814475 80 : 4361, 4137
7471 11:17:51.814889 84 : 4250, 4027
7472 11:17:51.815217 88 : 4360, 286
7473 11:17:51.818014 92 : 4361, 0
7474 11:17:51.818538 96 : 4250, 0
7475 11:17:51.820824 100 : 4250, 0
7476 11:17:51.821249 104 : 4252, 0
7477 11:17:51.821586 108 : 4361, 0
7478 11:17:51.824036 112 : 4360, 0
7479 11:17:51.824463 116 : 4363, 0
7480 11:17:51.824799 120 : 4250, 0
7481 11:17:51.827685 124 : 4250, 0
7482 11:17:51.828112 128 : 4250, 0
7483 11:17:51.830794 132 : 4250, 0
7484 11:17:51.831225 136 : 4250, 0
7485 11:17:51.831647 140 : 4250, 0
7486 11:17:51.834107 144 : 4252, 0
7487 11:17:51.834530 148 : 4250, 0
7488 11:17:51.837745 152 : 4250, 0
7489 11:17:51.838173 156 : 4249, 0
7490 11:17:51.838510 160 : 4363, 0
7491 11:17:51.841118 164 : 4361, 0
7492 11:17:51.841543 168 : 4363, 0
7493 11:17:51.844832 172 : 4250, 0
7494 11:17:51.845255 176 : 4250, 0
7495 11:17:51.845591 180 : 4250, 0
7496 11:17:51.847713 184 : 4250, 0
7497 11:17:51.848138 188 : 4249, 0
7498 11:17:51.848475 192 : 4250, 0
7499 11:17:51.851238 196 : 4253, 0
7500 11:17:51.851748 200 : 4253, 0
7501 11:17:51.854295 204 : 4250, 1243
7502 11:17:51.854819 208 : 4252, 4011
7503 11:17:51.857731 212 : 4250, 4027
7504 11:17:51.858160 216 : 4252, 4029
7505 11:17:51.861266 220 : 4249, 4027
7506 11:17:51.861693 224 : 4250, 4027
7507 11:17:51.864325 228 : 4250, 4026
7508 11:17:51.864753 232 : 4249, 4027
7509 11:17:51.865093 236 : 4250, 4026
7510 11:17:51.867598 240 : 4361, 4137
7511 11:17:51.868117 244 : 4361, 4137
7512 11:17:51.871582 248 : 4250, 4027
7513 11:17:51.872101 252 : 4361, 4137
7514 11:17:51.874222 256 : 4361, 4137
7515 11:17:51.874652 260 : 4250, 4027
7516 11:17:51.877810 264 : 4250, 4027
7517 11:17:51.878236 268 : 4249, 4027
7518 11:17:51.881324 272 : 4250, 4026
7519 11:17:51.881848 276 : 4250, 4027
7520 11:17:51.884122 280 : 4252, 4029
7521 11:17:51.884549 284 : 4250, 4027
7522 11:17:51.887449 288 : 4250, 4026
7523 11:17:51.887879 292 : 4363, 4140
7524 11:17:51.888215 296 : 4360, 4138
7525 11:17:51.890513 300 : 4248, 4024
7526 11:17:51.890941 304 : 4360, 4137
7527 11:17:51.893725 308 : 4361, 4085
7528 11:17:51.894153 312 : 4250, 2121
7529 11:17:51.894492
7530 11:17:51.897327 MIOCK jitter meter ch=0
7531 11:17:51.897745
7532 11:17:51.900536 1T = (312-88) = 224 dly cells
7533 11:17:51.907180 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 290/100 ps
7534 11:17:51.907779 ==
7535 11:17:51.910940 Dram Type= 6, Freq= 0, CH_0, rank 0
7536 11:17:51.914095 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7537 11:17:51.914615 ==
7538 11:17:51.920580 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7539 11:17:51.924097 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7540 11:17:51.927500 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7541 11:17:51.933990 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7542 11:17:51.943441 [CA 0] Center 42 (12~73) winsize 62
7543 11:17:51.945673 [CA 1] Center 42 (12~73) winsize 62
7544 11:17:51.949681 [CA 2] Center 38 (8~68) winsize 61
7545 11:17:51.952754 [CA 3] Center 37 (8~67) winsize 60
7546 11:17:51.955745 [CA 4] Center 36 (6~66) winsize 61
7547 11:17:51.959443 [CA 5] Center 35 (6~64) winsize 59
7548 11:17:51.959972
7549 11:17:51.962438 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7550 11:17:51.962957
7551 11:17:51.965796 [CATrainingPosCal] consider 1 rank data
7552 11:17:51.969156 u2DelayCellTimex100 = 290/100 ps
7553 11:17:51.972498 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7554 11:17:51.979483 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7555 11:17:51.982574 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7556 11:17:51.986317 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7557 11:17:51.989395 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7558 11:17:51.992737 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7559 11:17:51.993161
7560 11:17:51.995967 CA PerBit enable=1, Macro0, CA PI delay=35
7561 11:17:51.996387
7562 11:17:51.999295 [CBTSetCACLKResult] CA Dly = 35
7563 11:17:52.002293 CS Dly: 9 (0~40)
7564 11:17:52.006329 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7565 11:17:52.009527 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7566 11:17:52.010043 ==
7567 11:17:52.012720 Dram Type= 6, Freq= 0, CH_0, rank 1
7568 11:17:52.016186 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7569 11:17:52.016706 ==
7570 11:17:52.022871 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7571 11:17:52.026215 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7572 11:17:52.032164 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7573 11:17:52.035783 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7574 11:17:52.045907 [CA 0] Center 42 (12~73) winsize 62
7575 11:17:52.049477 [CA 1] Center 42 (12~73) winsize 62
7576 11:17:52.052433 [CA 2] Center 38 (8~68) winsize 61
7577 11:17:52.055802 [CA 3] Center 37 (8~67) winsize 60
7578 11:17:52.059404 [CA 4] Center 36 (6~66) winsize 61
7579 11:17:52.062766 [CA 5] Center 35 (5~65) winsize 61
7580 11:17:52.063285
7581 11:17:52.066160 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7582 11:17:52.066583
7583 11:17:52.069189 [CATrainingPosCal] consider 2 rank data
7584 11:17:52.072952 u2DelayCellTimex100 = 290/100 ps
7585 11:17:52.075975 CA0 delay=42 (12~73),Diff = 7 PI (23 cell)
7586 11:17:52.082937 CA1 delay=42 (12~73),Diff = 7 PI (23 cell)
7587 11:17:52.085670 CA2 delay=38 (8~68),Diff = 3 PI (10 cell)
7588 11:17:52.088785 CA3 delay=37 (8~67),Diff = 2 PI (6 cell)
7589 11:17:52.092620 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7590 11:17:52.095626 CA5 delay=35 (6~64),Diff = 0 PI (0 cell)
7591 11:17:52.096049
7592 11:17:52.098852 CA PerBit enable=1, Macro0, CA PI delay=35
7593 11:17:52.099414
7594 11:17:52.102423 [CBTSetCACLKResult] CA Dly = 35
7595 11:17:52.105850 CS Dly: 10 (0~42)
7596 11:17:52.109026 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7597 11:17:52.112036 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7598 11:17:52.112458
7599 11:17:52.116191 ----->DramcWriteLeveling(PI) begin...
7600 11:17:52.116713 ==
7601 11:17:52.119318 Dram Type= 6, Freq= 0, CH_0, rank 0
7602 11:17:52.125524 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7603 11:17:52.126061 ==
7604 11:17:52.128593 Write leveling (Byte 0): 35 => 35
7605 11:17:52.129013 Write leveling (Byte 1): 28 => 28
7606 11:17:52.131901 DramcWriteLeveling(PI) end<-----
7607 11:17:52.132320
7608 11:17:52.132650 ==
7609 11:17:52.135868 Dram Type= 6, Freq= 0, CH_0, rank 0
7610 11:17:52.142619 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7611 11:17:52.143143 ==
7612 11:17:52.145581 [Gating] SW mode calibration
7613 11:17:52.151884 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7614 11:17:52.155470 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7615 11:17:52.162126 1 4 0 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
7616 11:17:52.165708 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7617 11:17:52.168705 1 4 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 1)
7618 11:17:52.175168 1 4 12 | B1->B0 | 2323 3534 | 0 1 | (0 0) (1 1)
7619 11:17:52.178670 1 4 16 | B1->B0 | 2323 3535 | 0 0 | (0 0) (0 0)
7620 11:17:52.182217 1 4 20 | B1->B0 | 3333 3535 | 0 0 | (0 0) (0 0)
7621 11:17:52.185305 1 4 24 | B1->B0 | 3434 3736 | 1 1 | (1 1) (1 1)
7622 11:17:52.191812 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7623 11:17:52.195532 1 5 0 | B1->B0 | 3434 3838 | 1 0 | (1 1) (0 0)
7624 11:17:52.198446 1 5 4 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
7625 11:17:52.205440 1 5 8 | B1->B0 | 3434 3232 | 1 0 | (1 1) (0 1)
7626 11:17:52.209116 1 5 12 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
7627 11:17:52.212101 1 5 16 | B1->B0 | 3434 2727 | 1 0 | (1 0) (0 0)
7628 11:17:52.219272 1 5 20 | B1->B0 | 2626 2727 | 0 0 | (0 0) (0 0)
7629 11:17:52.222429 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7630 11:17:52.225252 1 5 28 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7631 11:17:52.231639 1 6 0 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
7632 11:17:52.235146 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7633 11:17:52.238917 1 6 8 | B1->B0 | 2323 3535 | 0 1 | (0 0) (0 0)
7634 11:17:52.245026 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7635 11:17:52.248419 1 6 16 | B1->B0 | 2828 4645 | 0 1 | (0 0) (0 0)
7636 11:17:52.252253 1 6 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7637 11:17:52.258357 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7638 11:17:52.261752 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7639 11:17:52.265276 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7640 11:17:52.272031 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7641 11:17:52.275701 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7642 11:17:52.278487 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7643 11:17:52.285680 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7644 11:17:52.288561 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7645 11:17:52.291938 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7646 11:17:52.298637 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7647 11:17:52.301618 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7648 11:17:52.305133 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7649 11:17:52.311788 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7650 11:17:52.315356 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7651 11:17:52.318206 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7652 11:17:52.324965 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7653 11:17:52.328142 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7654 11:17:52.331806 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7655 11:17:52.334949 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7656 11:17:52.341638 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7657 11:17:52.344706 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7658 11:17:52.347911 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7659 11:17:52.355205 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7660 11:17:52.358212 Total UI for P1: 0, mck2ui 16
7661 11:17:52.361788 best dqsien dly found for B0: ( 1, 9, 10)
7662 11:17:52.364893 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7663 11:17:52.367783 Total UI for P1: 0, mck2ui 16
7664 11:17:52.371895 best dqsien dly found for B1: ( 1, 9, 16)
7665 11:17:52.375136 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7666 11:17:52.377992 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
7667 11:17:52.378416
7668 11:17:52.381421 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7669 11:17:52.388285 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
7670 11:17:52.388799 [Gating] SW calibration Done
7671 11:17:52.389249 ==
7672 11:17:52.391089 Dram Type= 6, Freq= 0, CH_0, rank 0
7673 11:17:52.398083 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7674 11:17:52.398508 ==
7675 11:17:52.398843 RX Vref Scan: 0
7676 11:17:52.399155
7677 11:17:52.401251 RX Vref 0 -> 0, step: 1
7678 11:17:52.401668
7679 11:17:52.404928 RX Delay 0 -> 252, step: 8
7680 11:17:52.407701 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
7681 11:17:52.411162 iDelay=200, Bit 1, Center 143 (88 ~ 199) 112
7682 11:17:52.414898 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7683 11:17:52.418016 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7684 11:17:52.424836 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
7685 11:17:52.427692 iDelay=200, Bit 5, Center 123 (72 ~ 175) 104
7686 11:17:52.431260 iDelay=200, Bit 6, Center 143 (96 ~ 191) 96
7687 11:17:52.434294 iDelay=200, Bit 7, Center 143 (96 ~ 191) 96
7688 11:17:52.438418 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
7689 11:17:52.441299 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
7690 11:17:52.447503 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
7691 11:17:52.451031 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
7692 11:17:52.455019 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
7693 11:17:52.458324 iDelay=200, Bit 13, Center 139 (88 ~ 191) 104
7694 11:17:52.464324 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7695 11:17:52.467682 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
7696 11:17:52.468231 ==
7697 11:17:52.471384 Dram Type= 6, Freq= 0, CH_0, rank 0
7698 11:17:52.474250 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7699 11:17:52.474690 ==
7700 11:17:52.477683 DQS Delay:
7701 11:17:52.478215 DQS0 = 0, DQS1 = 0
7702 11:17:52.478555 DQM Delay:
7703 11:17:52.480964 DQM0 = 136, DQM1 = 130
7704 11:17:52.481575 DQ Delay:
7705 11:17:52.484580 DQ0 =135, DQ1 =143, DQ2 =131, DQ3 =131
7706 11:17:52.487598 DQ4 =139, DQ5 =123, DQ6 =143, DQ7 =143
7707 11:17:52.490622 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =123
7708 11:17:52.497199 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =135
7709 11:17:52.497631
7710 11:17:52.497967
7711 11:17:52.498280 ==
7712 11:17:52.500940 Dram Type= 6, Freq= 0, CH_0, rank 0
7713 11:17:52.503804 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7714 11:17:52.504234 ==
7715 11:17:52.504571
7716 11:17:52.504879
7717 11:17:52.507853 TX Vref Scan disable
7718 11:17:52.508385 == TX Byte 0 ==
7719 11:17:52.514241 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7720 11:17:52.517853 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7721 11:17:52.518393 == TX Byte 1 ==
7722 11:17:52.524325 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7723 11:17:52.527588 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7724 11:17:52.528018 ==
7725 11:17:52.530761 Dram Type= 6, Freq= 0, CH_0, rank 0
7726 11:17:52.533737 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7727 11:17:52.534168 ==
7728 11:17:52.548761
7729 11:17:52.552144 TX Vref early break, caculate TX vref
7730 11:17:52.555432 TX Vref=16, minBit 7, minWin=22, winSum=379
7731 11:17:52.559381 TX Vref=18, minBit 7, minWin=23, winSum=384
7732 11:17:52.562332 TX Vref=20, minBit 7, minWin=23, winSum=399
7733 11:17:52.565451 TX Vref=22, minBit 1, minWin=24, winSum=407
7734 11:17:52.568677 TX Vref=24, minBit 1, minWin=25, winSum=418
7735 11:17:52.575590 TX Vref=26, minBit 2, minWin=25, winSum=423
7736 11:17:52.578794 TX Vref=28, minBit 1, minWin=25, winSum=425
7737 11:17:52.582179 TX Vref=30, minBit 1, minWin=25, winSum=413
7738 11:17:52.585963 TX Vref=32, minBit 1, minWin=24, winSum=406
7739 11:17:52.588866 TX Vref=34, minBit 1, minWin=23, winSum=395
7740 11:17:52.595570 [TxChooseVref] Worse bit 1, Min win 25, Win sum 425, Final Vref 28
7741 11:17:52.596114
7742 11:17:52.598851 Final TX Range 0 Vref 28
7743 11:17:52.599415
7744 11:17:52.599772 ==
7745 11:17:52.602629 Dram Type= 6, Freq= 0, CH_0, rank 0
7746 11:17:52.605091 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7747 11:17:52.605524 ==
7748 11:17:52.605858
7749 11:17:52.606167
7750 11:17:52.608809 TX Vref Scan disable
7751 11:17:52.615436 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
7752 11:17:52.615959 == TX Byte 0 ==
7753 11:17:52.618668 u2DelayCellOfst[0]=10 cells (3 PI)
7754 11:17:52.622142 u2DelayCellOfst[1]=13 cells (4 PI)
7755 11:17:52.624946 u2DelayCellOfst[2]=10 cells (3 PI)
7756 11:17:52.628802 u2DelayCellOfst[3]=10 cells (3 PI)
7757 11:17:52.631780 u2DelayCellOfst[4]=6 cells (2 PI)
7758 11:17:52.635639 u2DelayCellOfst[5]=0 cells (0 PI)
7759 11:17:52.636065 u2DelayCellOfst[6]=16 cells (5 PI)
7760 11:17:52.638776 u2DelayCellOfst[7]=16 cells (5 PI)
7761 11:17:52.645904 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7762 11:17:52.648706 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7763 11:17:52.649189 == TX Byte 1 ==
7764 11:17:52.652228 u2DelayCellOfst[8]=0 cells (0 PI)
7765 11:17:52.655556 u2DelayCellOfst[9]=0 cells (0 PI)
7766 11:17:52.658609 u2DelayCellOfst[10]=6 cells (2 PI)
7767 11:17:52.661753 u2DelayCellOfst[11]=0 cells (0 PI)
7768 11:17:52.665521 u2DelayCellOfst[12]=6 cells (2 PI)
7769 11:17:52.668612 u2DelayCellOfst[13]=10 cells (3 PI)
7770 11:17:52.672206 u2DelayCellOfst[14]=13 cells (4 PI)
7771 11:17:52.675225 u2DelayCellOfst[15]=10 cells (3 PI)
7772 11:17:52.678597 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
7773 11:17:52.682123 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
7774 11:17:52.685354 DramC Write-DBI on
7775 11:17:52.685871 ==
7776 11:17:52.688536 Dram Type= 6, Freq= 0, CH_0, rank 0
7777 11:17:52.691847 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7778 11:17:52.692366 ==
7779 11:17:52.692708
7780 11:17:52.693056
7781 11:17:52.695371 TX Vref Scan disable
7782 11:17:52.698592 == TX Byte 0 ==
7783 11:17:52.701785 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7784 11:17:52.705204 == TX Byte 1 ==
7785 11:17:52.708793 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7786 11:17:52.709318 DramC Write-DBI off
7787 11:17:52.709662
7788 11:17:52.712097 [DATLAT]
7789 11:17:52.712521 Freq=1600, CH0 RK0
7790 11:17:52.712857
7791 11:17:52.715077 DATLAT Default: 0xf
7792 11:17:52.715536 0, 0xFFFF, sum = 0
7793 11:17:52.718696 1, 0xFFFF, sum = 0
7794 11:17:52.719219 2, 0xFFFF, sum = 0
7795 11:17:52.721474 3, 0xFFFF, sum = 0
7796 11:17:52.721902 4, 0xFFFF, sum = 0
7797 11:17:52.725020 5, 0xFFFF, sum = 0
7798 11:17:52.725451 6, 0xFFFF, sum = 0
7799 11:17:52.728458 7, 0xFFFF, sum = 0
7800 11:17:52.728888 8, 0xFFFF, sum = 0
7801 11:17:52.731614 9, 0xFFFF, sum = 0
7802 11:17:52.734850 10, 0xFFFF, sum = 0
7803 11:17:52.735282 11, 0xFFFF, sum = 0
7804 11:17:52.738400 12, 0xFFFF, sum = 0
7805 11:17:52.738831 13, 0xFFFF, sum = 0
7806 11:17:52.741750 14, 0x0, sum = 1
7807 11:17:52.742301 15, 0x0, sum = 2
7808 11:17:52.745044 16, 0x0, sum = 3
7809 11:17:52.745573 17, 0x0, sum = 4
7810 11:17:52.745917 best_step = 15
7811 11:17:52.746229
7812 11:17:52.748696 ==
7813 11:17:52.751829 Dram Type= 6, Freq= 0, CH_0, rank 0
7814 11:17:52.755395 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7815 11:17:52.755836 ==
7816 11:17:52.756178 RX Vref Scan: 1
7817 11:17:52.756499
7818 11:17:52.758333 Set Vref Range= 24 -> 127
7819 11:17:52.758758
7820 11:17:52.761902 RX Vref 24 -> 127, step: 1
7821 11:17:52.762326
7822 11:17:52.765278 RX Delay 27 -> 252, step: 4
7823 11:17:52.765800
7824 11:17:52.768291 Set Vref, RX VrefLevel [Byte0]: 24
7825 11:17:52.772084 [Byte1]: 24
7826 11:17:52.772604
7827 11:17:52.774612 Set Vref, RX VrefLevel [Byte0]: 25
7828 11:17:52.778637 [Byte1]: 25
7829 11:17:52.779161
7830 11:17:52.781568 Set Vref, RX VrefLevel [Byte0]: 26
7831 11:17:52.784905 [Byte1]: 26
7832 11:17:52.788697
7833 11:17:52.789213 Set Vref, RX VrefLevel [Byte0]: 27
7834 11:17:52.791723 [Byte1]: 27
7835 11:17:52.795781
7836 11:17:52.796297 Set Vref, RX VrefLevel [Byte0]: 28
7837 11:17:52.798737 [Byte1]: 28
7838 11:17:52.803106
7839 11:17:52.803578 Set Vref, RX VrefLevel [Byte0]: 29
7840 11:17:52.806479 [Byte1]: 29
7841 11:17:52.810748
7842 11:17:52.811461 Set Vref, RX VrefLevel [Byte0]: 30
7843 11:17:52.814195 [Byte1]: 30
7844 11:17:52.818643
7845 11:17:52.819176 Set Vref, RX VrefLevel [Byte0]: 31
7846 11:17:52.821251 [Byte1]: 31
7847 11:17:52.825855
7848 11:17:52.826277 Set Vref, RX VrefLevel [Byte0]: 32
7849 11:17:52.829356 [Byte1]: 32
7850 11:17:52.833359
7851 11:17:52.833957 Set Vref, RX VrefLevel [Byte0]: 33
7852 11:17:52.836353 [Byte1]: 33
7853 11:17:52.840977
7854 11:17:52.841494 Set Vref, RX VrefLevel [Byte0]: 34
7855 11:17:52.844368 [Byte1]: 34
7856 11:17:52.848887
7857 11:17:52.849403 Set Vref, RX VrefLevel [Byte0]: 35
7858 11:17:52.851982 [Byte1]: 35
7859 11:17:52.855780
7860 11:17:52.856202 Set Vref, RX VrefLevel [Byte0]: 36
7861 11:17:52.859505 [Byte1]: 36
7862 11:17:52.863309
7863 11:17:52.863897 Set Vref, RX VrefLevel [Byte0]: 37
7864 11:17:52.870023 [Byte1]: 37
7865 11:17:52.870545
7866 11:17:52.873725 Set Vref, RX VrefLevel [Byte0]: 38
7867 11:17:52.877036 [Byte1]: 38
7868 11:17:52.877552
7869 11:17:52.880178 Set Vref, RX VrefLevel [Byte0]: 39
7870 11:17:52.883546 [Byte1]: 39
7871 11:17:52.884064
7872 11:17:52.886611 Set Vref, RX VrefLevel [Byte0]: 40
7873 11:17:52.889761 [Byte1]: 40
7874 11:17:52.893468
7875 11:17:52.893984 Set Vref, RX VrefLevel [Byte0]: 41
7876 11:17:52.897070 [Byte1]: 41
7877 11:17:52.901623
7878 11:17:52.902142 Set Vref, RX VrefLevel [Byte0]: 42
7879 11:17:52.904659 [Byte1]: 42
7880 11:17:52.908763
7881 11:17:52.909273 Set Vref, RX VrefLevel [Byte0]: 43
7882 11:17:52.912018 [Byte1]: 43
7883 11:17:52.916496
7884 11:17:52.917014 Set Vref, RX VrefLevel [Byte0]: 44
7885 11:17:52.919208 [Byte1]: 44
7886 11:17:52.923827
7887 11:17:52.924244 Set Vref, RX VrefLevel [Byte0]: 45
7888 11:17:52.927048 [Byte1]: 45
7889 11:17:52.931411
7890 11:17:52.931832 Set Vref, RX VrefLevel [Byte0]: 46
7891 11:17:52.934753 [Byte1]: 46
7892 11:17:52.939022
7893 11:17:52.939587 Set Vref, RX VrefLevel [Byte0]: 47
7894 11:17:52.941932 [Byte1]: 47
7895 11:17:52.946661
7896 11:17:52.947220 Set Vref, RX VrefLevel [Byte0]: 48
7897 11:17:52.949721 [Byte1]: 48
7898 11:17:52.953639
7899 11:17:52.954276 Set Vref, RX VrefLevel [Byte0]: 49
7900 11:17:52.957609 [Byte1]: 49
7901 11:17:52.961612
7902 11:17:52.962026 Set Vref, RX VrefLevel [Byte0]: 50
7903 11:17:52.964940 [Byte1]: 50
7904 11:17:52.969364
7905 11:17:52.969893 Set Vref, RX VrefLevel [Byte0]: 51
7906 11:17:52.972609 [Byte1]: 51
7907 11:17:52.976701
7908 11:17:52.977230 Set Vref, RX VrefLevel [Byte0]: 52
7909 11:17:52.979550 [Byte1]: 52
7910 11:17:52.984236
7911 11:17:52.984762 Set Vref, RX VrefLevel [Byte0]: 53
7912 11:17:52.987501 [Byte1]: 53
7913 11:17:52.991941
7914 11:17:52.992478 Set Vref, RX VrefLevel [Byte0]: 54
7915 11:17:52.994810 [Byte1]: 54
7916 11:17:52.999270
7917 11:17:52.999714 Set Vref, RX VrefLevel [Byte0]: 55
7918 11:17:53.002845 [Byte1]: 55
7919 11:17:53.006609
7920 11:17:53.007140 Set Vref, RX VrefLevel [Byte0]: 56
7921 11:17:53.010209 [Byte1]: 56
7922 11:17:53.013992
7923 11:17:53.014418 Set Vref, RX VrefLevel [Byte0]: 57
7924 11:17:53.018120 [Byte1]: 57
7925 11:17:53.021622
7926 11:17:53.022048 Set Vref, RX VrefLevel [Byte0]: 58
7927 11:17:53.025126 [Byte1]: 58
7928 11:17:53.029318
7929 11:17:53.029755 Set Vref, RX VrefLevel [Byte0]: 59
7930 11:17:53.032307 [Byte1]: 59
7931 11:17:53.036499
7932 11:17:53.036921 Set Vref, RX VrefLevel [Byte0]: 60
7933 11:17:53.040332 [Byte1]: 60
7934 11:17:53.044408
7935 11:17:53.044929 Set Vref, RX VrefLevel [Byte0]: 61
7936 11:17:53.047227 [Byte1]: 61
7937 11:17:53.052261
7938 11:17:53.052784 Set Vref, RX VrefLevel [Byte0]: 62
7939 11:17:53.055551 [Byte1]: 62
7940 11:17:53.059197
7941 11:17:53.059769 Set Vref, RX VrefLevel [Byte0]: 63
7942 11:17:53.063065 [Byte1]: 63
7943 11:17:53.067138
7944 11:17:53.067718 Set Vref, RX VrefLevel [Byte0]: 64
7945 11:17:53.070506 [Byte1]: 64
7946 11:17:53.074790
7947 11:17:53.075322 Set Vref, RX VrefLevel [Byte0]: 65
7948 11:17:53.078082 [Byte1]: 65
7949 11:17:53.082447
7950 11:17:53.082966 Set Vref, RX VrefLevel [Byte0]: 66
7951 11:17:53.085192 [Byte1]: 66
7952 11:17:53.089698
7953 11:17:53.090216 Set Vref, RX VrefLevel [Byte0]: 67
7954 11:17:53.092731 [Byte1]: 67
7955 11:17:53.097162
7956 11:17:53.097682 Set Vref, RX VrefLevel [Byte0]: 68
7957 11:17:53.100292 [Byte1]: 68
7958 11:17:53.104776
7959 11:17:53.105305 Set Vref, RX VrefLevel [Byte0]: 69
7960 11:17:53.108121 [Byte1]: 69
7961 11:17:53.112672
7962 11:17:53.113192 Set Vref, RX VrefLevel [Byte0]: 70
7963 11:17:53.115515 [Byte1]: 70
7964 11:17:53.119667
7965 11:17:53.120184 Set Vref, RX VrefLevel [Byte0]: 71
7966 11:17:53.122913 [Byte1]: 71
7967 11:17:53.127095
7968 11:17:53.127596 Set Vref, RX VrefLevel [Byte0]: 72
7969 11:17:53.130079 [Byte1]: 72
7970 11:17:53.134949
7971 11:17:53.135402 Set Vref, RX VrefLevel [Byte0]: 73
7972 11:17:53.137767 [Byte1]: 73
7973 11:17:53.142442
7974 11:17:53.143007 Set Vref, RX VrefLevel [Byte0]: 74
7975 11:17:53.145403 [Byte1]: 74
7976 11:17:53.149548
7977 11:17:53.150071 Final RX Vref Byte 0 = 59 to rank0
7978 11:17:53.153081 Final RX Vref Byte 1 = 64 to rank0
7979 11:17:53.155887 Final RX Vref Byte 0 = 59 to rank1
7980 11:17:53.159782 Final RX Vref Byte 1 = 64 to rank1==
7981 11:17:53.163242 Dram Type= 6, Freq= 0, CH_0, rank 0
7982 11:17:53.169226 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7983 11:17:53.169753 ==
7984 11:17:53.170107 DQS Delay:
7985 11:17:53.170417 DQS0 = 0, DQS1 = 0
7986 11:17:53.173137 DQM Delay:
7987 11:17:53.173654 DQM0 = 134, DQM1 = 128
7988 11:17:53.175844 DQ Delay:
7989 11:17:53.179437 DQ0 =134, DQ1 =138, DQ2 =134, DQ3 =132
7990 11:17:53.183302 DQ4 =134, DQ5 =124, DQ6 =140, DQ7 =140
7991 11:17:53.186177 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =122
7992 11:17:53.189488 DQ12 =132, DQ13 =132, DQ14 =138, DQ15 =136
7993 11:17:53.190007
7994 11:17:53.190345
7995 11:17:53.190669
7996 11:17:53.192933 [DramC_TX_OE_Calibration] TA2
7997 11:17:53.196063 Original DQ_B0 (3 6) =30, OEN = 27
7998 11:17:53.199300 Original DQ_B1 (3 6) =30, OEN = 27
7999 11:17:53.202476 24, 0x0, End_B0=24 End_B1=24
8000 11:17:53.202901 25, 0x0, End_B0=25 End_B1=25
8001 11:17:53.206412 26, 0x0, End_B0=26 End_B1=26
8002 11:17:53.209502 27, 0x0, End_B0=27 End_B1=27
8003 11:17:53.212513 28, 0x0, End_B0=28 End_B1=28
8004 11:17:53.215828 29, 0x0, End_B0=29 End_B1=29
8005 11:17:53.216372 30, 0x0, End_B0=30 End_B1=30
8006 11:17:53.219515 31, 0x4141, End_B0=30 End_B1=30
8007 11:17:53.222882 Byte0 end_step=30 best_step=27
8008 11:17:53.226096 Byte1 end_step=30 best_step=27
8009 11:17:53.229220 Byte0 TX OE(2T, 0.5T) = (3, 3)
8010 11:17:53.232426 Byte1 TX OE(2T, 0.5T) = (3, 3)
8011 11:17:53.232906
8012 11:17:53.233235
8013 11:17:53.239318 [DQSOSCAuto] RK0, (LSB)MR18= 0x2520, (MSB)MR19= 0x303, tDQSOscB0 = 393 ps tDQSOscB1 = 391 ps
8014 11:17:53.242697 CH0 RK0: MR19=303, MR18=2520
8015 11:17:53.249621 CH0_RK0: MR19=0x303, MR18=0x2520, DQSOSC=391, MR23=63, INC=24, DEC=16
8016 11:17:53.250148
8017 11:17:53.252212 ----->DramcWriteLeveling(PI) begin...
8018 11:17:53.252639 ==
8019 11:17:53.255716 Dram Type= 6, Freq= 0, CH_0, rank 1
8020 11:17:53.259210 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8021 11:17:53.259669 ==
8022 11:17:53.262454 Write leveling (Byte 0): 37 => 37
8023 11:17:53.265997 Write leveling (Byte 1): 27 => 27
8024 11:17:53.268979 DramcWriteLeveling(PI) end<-----
8025 11:17:53.269402
8026 11:17:53.269732 ==
8027 11:17:53.273040 Dram Type= 6, Freq= 0, CH_0, rank 1
8028 11:17:53.275829 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8029 11:17:53.276256 ==
8030 11:17:53.279187 [Gating] SW mode calibration
8031 11:17:53.286189 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8032 11:17:53.292688 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8033 11:17:53.295844 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8034 11:17:53.302439 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8035 11:17:53.305478 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8036 11:17:53.308849 1 4 12 | B1->B0 | 2323 2525 | 0 1 | (0 0) (1 1)
8037 11:17:53.312472 1 4 16 | B1->B0 | 2e2e 3535 | 0 1 | (1 1) (0 0)
8038 11:17:53.319078 1 4 20 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
8039 11:17:53.322254 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8040 11:17:53.325463 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8041 11:17:53.332118 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8042 11:17:53.335424 1 5 4 | B1->B0 | 3434 3535 | 1 1 | (1 1) (1 1)
8043 11:17:53.338408 1 5 8 | B1->B0 | 3434 3535 | 1 0 | (1 1) (0 0)
8044 11:17:53.345326 1 5 12 | B1->B0 | 3434 3030 | 1 1 | (1 0) (1 0)
8045 11:17:53.348425 1 5 16 | B1->B0 | 2d2d 2525 | 1 0 | (1 0) (0 0)
8046 11:17:53.351948 1 5 20 | B1->B0 | 2323 2928 | 0 1 | (0 0) (1 1)
8047 11:17:53.358987 1 5 24 | B1->B0 | 2323 2827 | 0 1 | (0 0) (0 0)
8048 11:17:53.361876 1 5 28 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (1 1)
8049 11:17:53.365509 1 6 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8050 11:17:53.371679 1 6 4 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
8051 11:17:53.375196 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8052 11:17:53.378507 1 6 12 | B1->B0 | 2828 3b3b | 0 0 | (0 0) (0 0)
8053 11:17:53.384663 1 6 16 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
8054 11:17:53.388463 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8055 11:17:53.391478 1 6 24 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
8056 11:17:53.398142 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8057 11:17:53.401832 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8058 11:17:53.404897 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8059 11:17:53.411960 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8060 11:17:53.415012 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8061 11:17:53.418031 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8062 11:17:53.425318 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8063 11:17:53.428328 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8064 11:17:53.431491 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8065 11:17:53.438610 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8066 11:17:53.442338 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8067 11:17:53.445211 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8068 11:17:53.451672 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8069 11:17:53.455177 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8070 11:17:53.458283 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8071 11:17:53.461618 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8072 11:17:53.467884 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8073 11:17:53.471525 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8074 11:17:53.475062 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8075 11:17:53.481961 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8076 11:17:53.484979 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8077 11:17:53.488007 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8078 11:17:53.495262 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8079 11:17:53.498141 Total UI for P1: 0, mck2ui 16
8080 11:17:53.501210 best dqsien dly found for B0: ( 1, 9, 12)
8081 11:17:53.504762 Total UI for P1: 0, mck2ui 16
8082 11:17:53.507824 best dqsien dly found for B1: ( 1, 9, 14)
8083 11:17:53.511086 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8084 11:17:53.514742 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8085 11:17:53.515268
8086 11:17:53.517657 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8087 11:17:53.521605 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8088 11:17:53.524847 [Gating] SW calibration Done
8089 11:17:53.525384 ==
8090 11:17:53.527840 Dram Type= 6, Freq= 0, CH_0, rank 1
8091 11:17:53.530887 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8092 11:17:53.531345 ==
8093 11:17:53.534570 RX Vref Scan: 0
8094 11:17:53.535101
8095 11:17:53.537488 RX Vref 0 -> 0, step: 1
8096 11:17:53.537941
8097 11:17:53.538377 RX Delay 0 -> 252, step: 8
8098 11:17:53.544876 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8099 11:17:53.547890 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
8100 11:17:53.551305 iDelay=200, Bit 2, Center 135 (80 ~ 191) 112
8101 11:17:53.554585 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8102 11:17:53.558145 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8103 11:17:53.561490 iDelay=200, Bit 5, Center 127 (72 ~ 183) 112
8104 11:17:53.567807 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8105 11:17:53.570936 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8106 11:17:53.574677 iDelay=200, Bit 8, Center 123 (72 ~ 175) 104
8107 11:17:53.577801 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8108 11:17:53.584278 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8109 11:17:53.587795 iDelay=200, Bit 11, Center 123 (72 ~ 175) 104
8110 11:17:53.591080 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8111 11:17:53.593919 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8112 11:17:53.597500 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8113 11:17:53.604119 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8114 11:17:53.604656 ==
8115 11:17:53.607673 Dram Type= 6, Freq= 0, CH_0, rank 1
8116 11:17:53.610727 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8117 11:17:53.611262 ==
8118 11:17:53.611743 DQS Delay:
8119 11:17:53.614020 DQS0 = 0, DQS1 = 0
8120 11:17:53.614459 DQM Delay:
8121 11:17:53.617268 DQM0 = 137, DQM1 = 130
8122 11:17:53.617705 DQ Delay:
8123 11:17:53.621206 DQ0 =135, DQ1 =139, DQ2 =135, DQ3 =135
8124 11:17:53.624139 DQ4 =139, DQ5 =127, DQ6 =143, DQ7 =143
8125 11:17:53.626977 DQ8 =123, DQ9 =119, DQ10 =131, DQ11 =123
8126 11:17:53.630858 DQ12 =135, DQ13 =135, DQ14 =139, DQ15 =139
8127 11:17:53.634323
8128 11:17:53.634849
8129 11:17:53.635395 ==
8130 11:17:53.637182 Dram Type= 6, Freq= 0, CH_0, rank 1
8131 11:17:53.640415 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8132 11:17:53.640854 ==
8133 11:17:53.641289
8134 11:17:53.641693
8135 11:17:53.643783 TX Vref Scan disable
8136 11:17:53.644217 == TX Byte 0 ==
8137 11:17:53.650425 Update DQ dly =994 (3 ,6, 34) DQ OEN =(3 ,3)
8138 11:17:53.653798 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8139 11:17:53.654336 == TX Byte 1 ==
8140 11:17:53.660853 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8141 11:17:53.663625 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8142 11:17:53.664165 ==
8143 11:17:53.667241 Dram Type= 6, Freq= 0, CH_0, rank 1
8144 11:17:53.670171 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8145 11:17:53.670614 ==
8146 11:17:53.686493
8147 11:17:53.689999 TX Vref early break, caculate TX vref
8148 11:17:53.692762 TX Vref=16, minBit 1, minWin=23, winSum=387
8149 11:17:53.696055 TX Vref=18, minBit 1, minWin=23, winSum=392
8150 11:17:53.699742 TX Vref=20, minBit 4, minWin=23, winSum=403
8151 11:17:53.702563 TX Vref=22, minBit 3, minWin=24, winSum=408
8152 11:17:53.706229 TX Vref=24, minBit 1, minWin=25, winSum=418
8153 11:17:53.713243 TX Vref=26, minBit 4, minWin=24, winSum=425
8154 11:17:53.716337 TX Vref=28, minBit 2, minWin=25, winSum=424
8155 11:17:53.719651 TX Vref=30, minBit 0, minWin=25, winSum=416
8156 11:17:53.722975 TX Vref=32, minBit 3, minWin=24, winSum=408
8157 11:17:53.725973 TX Vref=34, minBit 0, minWin=24, winSum=403
8158 11:17:53.729105 TX Vref=36, minBit 0, minWin=24, winSum=391
8159 11:17:53.735727 [TxChooseVref] Worse bit 2, Min win 25, Win sum 424, Final Vref 28
8160 11:17:53.736239
8161 11:17:53.739589 Final TX Range 0 Vref 28
8162 11:17:53.740028
8163 11:17:53.740462 ==
8164 11:17:53.742635 Dram Type= 6, Freq= 0, CH_0, rank 1
8165 11:17:53.746025 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8166 11:17:53.746556 ==
8167 11:17:53.747000
8168 11:17:53.747526
8169 11:17:53.749077 TX Vref Scan disable
8170 11:17:53.755596 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8171 11:17:53.756129 == TX Byte 0 ==
8172 11:17:53.759515 u2DelayCellOfst[0]=13 cells (4 PI)
8173 11:17:53.762684 u2DelayCellOfst[1]=16 cells (5 PI)
8174 11:17:53.765870 u2DelayCellOfst[2]=13 cells (4 PI)
8175 11:17:53.769094 u2DelayCellOfst[3]=13 cells (4 PI)
8176 11:17:53.772842 u2DelayCellOfst[4]=10 cells (3 PI)
8177 11:17:53.775707 u2DelayCellOfst[5]=0 cells (0 PI)
8178 11:17:53.779380 u2DelayCellOfst[6]=20 cells (6 PI)
8179 11:17:53.782449 u2DelayCellOfst[7]=16 cells (5 PI)
8180 11:17:53.785980 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8181 11:17:53.789156 Update DQM dly =994 (3 ,6, 34) DQM OEN =(3 ,3)
8182 11:17:53.792556 == TX Byte 1 ==
8183 11:17:53.795466 u2DelayCellOfst[8]=3 cells (1 PI)
8184 11:17:53.798508 u2DelayCellOfst[9]=0 cells (0 PI)
8185 11:17:53.802089 u2DelayCellOfst[10]=6 cells (2 PI)
8186 11:17:53.802618 u2DelayCellOfst[11]=3 cells (1 PI)
8187 11:17:53.805780 u2DelayCellOfst[12]=13 cells (4 PI)
8188 11:17:53.809214 u2DelayCellOfst[13]=10 cells (3 PI)
8189 11:17:53.812085 u2DelayCellOfst[14]=13 cells (4 PI)
8190 11:17:53.815932 u2DelayCellOfst[15]=10 cells (3 PI)
8191 11:17:53.822384 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8192 11:17:53.825361 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8193 11:17:53.825888 DramC Write-DBI on
8194 11:17:53.826336 ==
8195 11:17:53.828311 Dram Type= 6, Freq= 0, CH_0, rank 1
8196 11:17:53.835306 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8197 11:17:53.835872 ==
8198 11:17:53.836315
8199 11:17:53.836727
8200 11:17:53.838685 TX Vref Scan disable
8201 11:17:53.839120 == TX Byte 0 ==
8202 11:17:53.845833 Update DQM dly =737 (2 ,6, 33) DQM OEN =(3 ,3)
8203 11:17:53.846368 == TX Byte 1 ==
8204 11:17:53.848916 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8205 11:17:53.852011 DramC Write-DBI off
8206 11:17:53.852444
8207 11:17:53.852878 [DATLAT]
8208 11:17:53.855236 Freq=1600, CH0 RK1
8209 11:17:53.855713
8210 11:17:53.856149 DATLAT Default: 0xf
8211 11:17:53.858464 0, 0xFFFF, sum = 0
8212 11:17:53.858903 1, 0xFFFF, sum = 0
8213 11:17:53.861697 2, 0xFFFF, sum = 0
8214 11:17:53.862141 3, 0xFFFF, sum = 0
8215 11:17:53.865131 4, 0xFFFF, sum = 0
8216 11:17:53.865670 5, 0xFFFF, sum = 0
8217 11:17:53.869116 6, 0xFFFF, sum = 0
8218 11:17:53.869653 7, 0xFFFF, sum = 0
8219 11:17:53.872064 8, 0xFFFF, sum = 0
8220 11:17:53.872509 9, 0xFFFF, sum = 0
8221 11:17:53.875564 10, 0xFFFF, sum = 0
8222 11:17:53.878624 11, 0xFFFF, sum = 0
8223 11:17:53.879160 12, 0xFFFF, sum = 0
8224 11:17:53.881681 13, 0xFFFF, sum = 0
8225 11:17:53.882124 14, 0x0, sum = 1
8226 11:17:53.885331 15, 0x0, sum = 2
8227 11:17:53.885868 16, 0x0, sum = 3
8228 11:17:53.888246 17, 0x0, sum = 4
8229 11:17:53.888693 best_step = 15
8230 11:17:53.889135
8231 11:17:53.889547 ==
8232 11:17:53.891917 Dram Type= 6, Freq= 0, CH_0, rank 1
8233 11:17:53.895109 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8234 11:17:53.895728 ==
8235 11:17:53.898538 RX Vref Scan: 0
8236 11:17:53.898973
8237 11:17:53.901501 RX Vref 0 -> 0, step: 1
8238 11:17:53.901939
8239 11:17:53.902375 RX Delay 19 -> 252, step: 4
8240 11:17:53.908911 iDelay=191, Bit 0, Center 134 (83 ~ 186) 104
8241 11:17:53.911760 iDelay=191, Bit 1, Center 138 (91 ~ 186) 96
8242 11:17:53.915742 iDelay=191, Bit 2, Center 130 (79 ~ 182) 104
8243 11:17:53.918828 iDelay=191, Bit 3, Center 134 (83 ~ 186) 104
8244 11:17:53.921596 iDelay=191, Bit 4, Center 136 (87 ~ 186) 100
8245 11:17:53.928507 iDelay=191, Bit 5, Center 126 (75 ~ 178) 104
8246 11:17:53.931777 iDelay=191, Bit 6, Center 140 (91 ~ 190) 100
8247 11:17:53.934914 iDelay=191, Bit 7, Center 140 (91 ~ 190) 100
8248 11:17:53.938720 iDelay=191, Bit 8, Center 120 (71 ~ 170) 100
8249 11:17:53.941657 iDelay=191, Bit 9, Center 116 (67 ~ 166) 100
8250 11:17:53.948018 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8251 11:17:53.951237 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8252 11:17:53.955449 iDelay=191, Bit 12, Center 134 (83 ~ 186) 104
8253 11:17:53.958386 iDelay=191, Bit 13, Center 134 (83 ~ 186) 104
8254 11:17:53.965058 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8255 11:17:53.968020 iDelay=191, Bit 15, Center 134 (87 ~ 182) 96
8256 11:17:53.968437 ==
8257 11:17:53.971837 Dram Type= 6, Freq= 0, CH_0, rank 1
8258 11:17:53.975409 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8259 11:17:53.975934 ==
8260 11:17:53.976272 DQS Delay:
8261 11:17:53.978513 DQS0 = 0, DQS1 = 0
8262 11:17:53.979027 DQM Delay:
8263 11:17:53.981543 DQM0 = 134, DQM1 = 127
8264 11:17:53.982010 DQ Delay:
8265 11:17:53.985055 DQ0 =134, DQ1 =138, DQ2 =130, DQ3 =134
8266 11:17:53.987925 DQ4 =136, DQ5 =126, DQ6 =140, DQ7 =140
8267 11:17:53.991556 DQ8 =120, DQ9 =116, DQ10 =128, DQ11 =118
8268 11:17:53.998240 DQ12 =134, DQ13 =134, DQ14 =134, DQ15 =134
8269 11:17:53.998658
8270 11:17:53.998983
8271 11:17:53.999486
8272 11:17:54.001160 [DramC_TX_OE_Calibration] TA2
8273 11:17:54.001573 Original DQ_B0 (3 6) =30, OEN = 27
8274 11:17:54.004867 Original DQ_B1 (3 6) =30, OEN = 27
8275 11:17:54.007627 24, 0x0, End_B0=24 End_B1=24
8276 11:17:54.011305 25, 0x0, End_B0=25 End_B1=25
8277 11:17:54.014768 26, 0x0, End_B0=26 End_B1=26
8278 11:17:54.015193 27, 0x0, End_B0=27 End_B1=27
8279 11:17:54.017676 28, 0x0, End_B0=28 End_B1=28
8280 11:17:54.021750 29, 0x0, End_B0=29 End_B1=29
8281 11:17:54.024452 30, 0x0, End_B0=30 End_B1=30
8282 11:17:54.027956 31, 0x4141, End_B0=30 End_B1=30
8283 11:17:54.031185 Byte0 end_step=30 best_step=27
8284 11:17:54.031746 Byte1 end_step=30 best_step=27
8285 11:17:54.034434 Byte0 TX OE(2T, 0.5T) = (3, 3)
8286 11:17:54.037915 Byte1 TX OE(2T, 0.5T) = (3, 3)
8287 11:17:54.038443
8288 11:17:54.038778
8289 11:17:54.047659 [DQSOSCAuto] RK1, (LSB)MR18= 0x1f07, (MSB)MR19= 0x303, tDQSOscB0 = 406 ps tDQSOscB1 = 394 ps
8290 11:17:54.048109 CH0 RK1: MR19=303, MR18=1F07
8291 11:17:54.054497 CH0_RK1: MR19=0x303, MR18=0x1F07, DQSOSC=394, MR23=63, INC=23, DEC=15
8292 11:17:54.058175 [RxdqsGatingPostProcess] freq 1600
8293 11:17:54.064535 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8294 11:17:54.067759 best DQS0 dly(2T, 0.5T) = (1, 1)
8295 11:17:54.070968 best DQS1 dly(2T, 0.5T) = (1, 1)
8296 11:17:54.075007 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8297 11:17:54.075568 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8298 11:17:54.078205 best DQS0 dly(2T, 0.5T) = (1, 1)
8299 11:17:54.081417 best DQS1 dly(2T, 0.5T) = (1, 1)
8300 11:17:54.084653 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8301 11:17:54.087777 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8302 11:17:54.091298 Pre-setting of DQS Precalculation
8303 11:17:54.097804 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8304 11:17:54.098324 ==
8305 11:17:54.100833 Dram Type= 6, Freq= 0, CH_1, rank 0
8306 11:17:54.104734 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8307 11:17:54.105257 ==
8308 11:17:54.110984 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8309 11:17:54.114329 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8310 11:17:54.117637 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8311 11:17:54.124079 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8312 11:17:54.132476 [CA 0] Center 41 (12~71) winsize 60
8313 11:17:54.135845 [CA 1] Center 41 (12~71) winsize 60
8314 11:17:54.138985 [CA 2] Center 38 (9~68) winsize 60
8315 11:17:54.142200 [CA 3] Center 37 (8~66) winsize 59
8316 11:17:54.146171 [CA 4] Center 37 (8~67) winsize 60
8317 11:17:54.149340 [CA 5] Center 36 (7~66) winsize 60
8318 11:17:54.149832
8319 11:17:54.152599 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8320 11:17:54.153120
8321 11:17:54.155752 [CATrainingPosCal] consider 1 rank data
8322 11:17:54.159407 u2DelayCellTimex100 = 290/100 ps
8323 11:17:54.162636 CA0 delay=41 (12~71),Diff = 5 PI (16 cell)
8324 11:17:54.169516 CA1 delay=41 (12~71),Diff = 5 PI (16 cell)
8325 11:17:54.172817 CA2 delay=38 (9~68),Diff = 2 PI (6 cell)
8326 11:17:54.176166 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8327 11:17:54.179356 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8328 11:17:54.182627 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8329 11:17:54.183148
8330 11:17:54.186479 CA PerBit enable=1, Macro0, CA PI delay=36
8331 11:17:54.186997
8332 11:17:54.189887 [CBTSetCACLKResult] CA Dly = 36
8333 11:17:54.192846 CS Dly: 11 (0~42)
8334 11:17:54.195987 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8335 11:17:54.199305 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8336 11:17:54.199876 ==
8337 11:17:54.202375 Dram Type= 6, Freq= 0, CH_1, rank 1
8338 11:17:54.205428 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8339 11:17:54.208884 ==
8340 11:17:54.212461 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8341 11:17:54.215967 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8342 11:17:54.222621 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8343 11:17:54.225351 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8344 11:17:54.236050 [CA 0] Center 42 (12~72) winsize 61
8345 11:17:54.238932 [CA 1] Center 42 (13~72) winsize 60
8346 11:17:54.242361 [CA 2] Center 39 (10~68) winsize 59
8347 11:17:54.245999 [CA 3] Center 38 (9~68) winsize 60
8348 11:17:54.249120 [CA 4] Center 38 (9~68) winsize 60
8349 11:17:54.252733 [CA 5] Center 37 (8~67) winsize 60
8350 11:17:54.253271
8351 11:17:54.255580 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8352 11:17:54.256022
8353 11:17:54.259290 [CATrainingPosCal] consider 2 rank data
8354 11:17:54.262450 u2DelayCellTimex100 = 290/100 ps
8355 11:17:54.265621 CA0 delay=41 (12~71),Diff = 4 PI (13 cell)
8356 11:17:54.272349 CA1 delay=42 (13~71),Diff = 5 PI (16 cell)
8357 11:17:54.275453 CA2 delay=39 (10~68),Diff = 2 PI (6 cell)
8358 11:17:54.279001 CA3 delay=37 (9~66),Diff = 0 PI (0 cell)
8359 11:17:54.281931 CA4 delay=38 (9~67),Diff = 1 PI (3 cell)
8360 11:17:54.285796 CA5 delay=37 (8~66),Diff = 0 PI (0 cell)
8361 11:17:54.286208
8362 11:17:54.289025 CA PerBit enable=1, Macro0, CA PI delay=37
8363 11:17:54.289438
8364 11:17:54.292315 [CBTSetCACLKResult] CA Dly = 37
8365 11:17:54.295442 CS Dly: 12 (0~45)
8366 11:17:54.298614 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8367 11:17:54.302587 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8368 11:17:54.302883
8369 11:17:54.305672 ----->DramcWriteLeveling(PI) begin...
8370 11:17:54.305971 ==
8371 11:17:54.309147 Dram Type= 6, Freq= 0, CH_1, rank 0
8372 11:17:54.311885 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8373 11:17:54.315647 ==
8374 11:17:54.315943 Write leveling (Byte 0): 25 => 25
8375 11:17:54.318540 Write leveling (Byte 1): 26 => 26
8376 11:17:54.322381 DramcWriteLeveling(PI) end<-----
8377 11:17:54.322770
8378 11:17:54.323010 ==
8379 11:17:54.325398 Dram Type= 6, Freq= 0, CH_1, rank 0
8380 11:17:54.332644 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8381 11:17:54.332953 ==
8382 11:17:54.333188 [Gating] SW mode calibration
8383 11:17:54.342243 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8384 11:17:54.345838 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8385 11:17:54.352169 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8386 11:17:54.356088 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8387 11:17:54.359284 1 4 8 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
8388 11:17:54.362854 1 4 12 | B1->B0 | 3030 3434 | 1 1 | (0 0) (1 1)
8389 11:17:54.368808 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8390 11:17:54.372541 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8391 11:17:54.376176 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8392 11:17:54.382030 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8393 11:17:54.385753 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8394 11:17:54.389261 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8395 11:17:54.395887 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8396 11:17:54.399104 1 5 12 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (1 0)
8397 11:17:54.402031 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8398 11:17:54.409508 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8399 11:17:54.412569 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8400 11:17:54.415654 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8401 11:17:54.422555 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8402 11:17:54.425875 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8403 11:17:54.428826 1 6 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8404 11:17:54.434994 1 6 12 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
8405 11:17:54.438964 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8406 11:17:54.441861 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8407 11:17:54.448811 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8408 11:17:54.451829 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8409 11:17:54.454991 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8410 11:17:54.461744 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8411 11:17:54.465624 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8412 11:17:54.468759 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8413 11:17:54.475397 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8414 11:17:54.478538 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8415 11:17:54.481558 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8416 11:17:54.488353 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8417 11:17:54.491384 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8418 11:17:54.494609 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8419 11:17:54.501368 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8420 11:17:54.504518 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8421 11:17:54.508393 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8422 11:17:54.511469 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8423 11:17:54.517914 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8424 11:17:54.521981 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8425 11:17:54.525088 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8426 11:17:54.531599 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8427 11:17:54.534604 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8428 11:17:54.537981 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8429 11:17:54.544916 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8430 11:17:54.547820 Total UI for P1: 0, mck2ui 16
8431 11:17:54.551434 best dqsien dly found for B0: ( 1, 9, 10)
8432 11:17:54.551546 Total UI for P1: 0, mck2ui 16
8433 11:17:54.557892 best dqsien dly found for B1: ( 1, 9, 10)
8434 11:17:54.561552 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8435 11:17:54.564635 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8436 11:17:54.564872
8437 11:17:54.567738 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8438 11:17:54.571080 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8439 11:17:54.574389 [Gating] SW calibration Done
8440 11:17:54.574605 ==
8441 11:17:54.578179 Dram Type= 6, Freq= 0, CH_1, rank 0
8442 11:17:54.581710 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8443 11:17:54.581958 ==
8444 11:17:54.584917 RX Vref Scan: 0
8445 11:17:54.585220
8446 11:17:54.585457 RX Vref 0 -> 0, step: 1
8447 11:17:54.588348
8448 11:17:54.588735 RX Delay 0 -> 252, step: 8
8449 11:17:54.591561 iDelay=200, Bit 0, Center 143 (96 ~ 191) 96
8450 11:17:54.598135 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8451 11:17:54.601192 iDelay=200, Bit 2, Center 123 (72 ~ 175) 104
8452 11:17:54.604587 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8453 11:17:54.607686 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8454 11:17:54.611668 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8455 11:17:54.617996 iDelay=200, Bit 6, Center 147 (96 ~ 199) 104
8456 11:17:54.621557 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8457 11:17:54.624712 iDelay=200, Bit 8, Center 119 (72 ~ 167) 96
8458 11:17:54.627963 iDelay=200, Bit 9, Center 123 (72 ~ 175) 104
8459 11:17:54.631579 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8460 11:17:54.638039 iDelay=200, Bit 11, Center 127 (80 ~ 175) 96
8461 11:17:54.641038 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8462 11:17:54.644610 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8463 11:17:54.647741 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8464 11:17:54.651428 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8465 11:17:54.654173 ==
8466 11:17:54.658157 Dram Type= 6, Freq= 0, CH_1, rank 0
8467 11:17:54.661386 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8468 11:17:54.661865 ==
8469 11:17:54.662229 DQS Delay:
8470 11:17:54.664296 DQS0 = 0, DQS1 = 0
8471 11:17:54.664991 DQM Delay:
8472 11:17:54.667460 DQM0 = 136, DQM1 = 132
8473 11:17:54.668158 DQ Delay:
8474 11:17:54.671110 DQ0 =143, DQ1 =131, DQ2 =123, DQ3 =135
8475 11:17:54.674275 DQ4 =131, DQ5 =147, DQ6 =147, DQ7 =135
8476 11:17:54.677495 DQ8 =119, DQ9 =123, DQ10 =131, DQ11 =127
8477 11:17:54.681193 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8478 11:17:54.681763
8479 11:17:54.682152
8480 11:17:54.682734 ==
8481 11:17:54.684362 Dram Type= 6, Freq= 0, CH_1, rank 0
8482 11:17:54.690812 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8483 11:17:54.691439 ==
8484 11:17:54.692078
8485 11:17:54.692684
8486 11:17:54.693293 TX Vref Scan disable
8487 11:17:54.694298 == TX Byte 0 ==
8488 11:17:54.698008 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8489 11:17:54.704833 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8490 11:17:54.705296 == TX Byte 1 ==
8491 11:17:54.708030 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8492 11:17:54.714487 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8493 11:17:54.714994 ==
8494 11:17:54.717654 Dram Type= 6, Freq= 0, CH_1, rank 0
8495 11:17:54.720895 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8496 11:17:54.721321 ==
8497 11:17:54.733065
8498 11:17:54.736629 TX Vref early break, caculate TX vref
8499 11:17:54.739731 TX Vref=16, minBit 0, minWin=23, winSum=382
8500 11:17:54.743201 TX Vref=18, minBit 2, minWin=23, winSum=388
8501 11:17:54.746736 TX Vref=20, minBit 9, minWin=23, winSum=398
8502 11:17:54.749686 TX Vref=22, minBit 1, minWin=25, winSum=411
8503 11:17:54.753316 TX Vref=24, minBit 0, minWin=25, winSum=419
8504 11:17:54.759940 TX Vref=26, minBit 0, minWin=25, winSum=424
8505 11:17:54.763069 TX Vref=28, minBit 1, minWin=25, winSum=429
8506 11:17:54.766193 TX Vref=30, minBit 0, minWin=25, winSum=422
8507 11:17:54.769781 TX Vref=32, minBit 2, minWin=24, winSum=417
8508 11:17:54.772868 TX Vref=34, minBit 0, minWin=24, winSum=406
8509 11:17:54.779908 [TxChooseVref] Worse bit 1, Min win 25, Win sum 429, Final Vref 28
8510 11:17:54.780333
8511 11:17:54.783071 Final TX Range 0 Vref 28
8512 11:17:54.783524
8513 11:17:54.783858 ==
8514 11:17:54.786248 Dram Type= 6, Freq= 0, CH_1, rank 0
8515 11:17:54.789482 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8516 11:17:54.789903 ==
8517 11:17:54.790238
8518 11:17:54.790546
8519 11:17:54.793017 TX Vref Scan disable
8520 11:17:54.799643 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8521 11:17:54.799944 == TX Byte 0 ==
8522 11:17:54.802627 u2DelayCellOfst[0]=16 cells (5 PI)
8523 11:17:54.805673 u2DelayCellOfst[1]=10 cells (3 PI)
8524 11:17:54.809383 u2DelayCellOfst[2]=0 cells (0 PI)
8525 11:17:54.812830 u2DelayCellOfst[3]=6 cells (2 PI)
8526 11:17:54.816037 u2DelayCellOfst[4]=10 cells (3 PI)
8527 11:17:54.819003 u2DelayCellOfst[5]=16 cells (5 PI)
8528 11:17:54.822257 u2DelayCellOfst[6]=20 cells (6 PI)
8529 11:17:54.825990 u2DelayCellOfst[7]=6 cells (2 PI)
8530 11:17:54.829206 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8531 11:17:54.832397 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8532 11:17:54.835761 == TX Byte 1 ==
8533 11:17:54.836162 u2DelayCellOfst[8]=0 cells (0 PI)
8534 11:17:54.838807 u2DelayCellOfst[9]=3 cells (1 PI)
8535 11:17:54.842571 u2DelayCellOfst[10]=13 cells (4 PI)
8536 11:17:54.845572 u2DelayCellOfst[11]=3 cells (1 PI)
8537 11:17:54.849311 u2DelayCellOfst[12]=16 cells (5 PI)
8538 11:17:54.852356 u2DelayCellOfst[13]=16 cells (5 PI)
8539 11:17:54.855745 u2DelayCellOfst[14]=16 cells (5 PI)
8540 11:17:54.858819 u2DelayCellOfst[15]=16 cells (5 PI)
8541 11:17:54.862424 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8542 11:17:54.868867 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8543 11:17:54.869173 DramC Write-DBI on
8544 11:17:54.869420 ==
8545 11:17:54.872326 Dram Type= 6, Freq= 0, CH_1, rank 0
8546 11:17:54.875461 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8547 11:17:54.878980 ==
8548 11:17:54.879275
8549 11:17:54.879548
8550 11:17:54.879771 TX Vref Scan disable
8551 11:17:54.882206 == TX Byte 0 ==
8552 11:17:54.885748 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8553 11:17:54.889032 == TX Byte 1 ==
8554 11:17:54.892286 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8555 11:17:54.895306 DramC Write-DBI off
8556 11:17:54.895634
8557 11:17:54.895871 [DATLAT]
8558 11:17:54.896093 Freq=1600, CH1 RK0
8559 11:17:54.896306
8560 11:17:54.898991 DATLAT Default: 0xf
8561 11:17:54.899313 0, 0xFFFF, sum = 0
8562 11:17:54.902063 1, 0xFFFF, sum = 0
8563 11:17:54.902366 2, 0xFFFF, sum = 0
8564 11:17:54.905768 3, 0xFFFF, sum = 0
8565 11:17:54.908705 4, 0xFFFF, sum = 0
8566 11:17:54.909009 5, 0xFFFF, sum = 0
8567 11:17:54.912354 6, 0xFFFF, sum = 0
8568 11:17:54.912657 7, 0xFFFF, sum = 0
8569 11:17:54.915354 8, 0xFFFF, sum = 0
8570 11:17:54.915671 9, 0xFFFF, sum = 0
8571 11:17:54.919255 10, 0xFFFF, sum = 0
8572 11:17:54.919584 11, 0xFFFF, sum = 0
8573 11:17:54.922433 12, 0xFFFF, sum = 0
8574 11:17:54.922738 13, 0xFFFF, sum = 0
8575 11:17:54.925751 14, 0x0, sum = 1
8576 11:17:54.926153 15, 0x0, sum = 2
8577 11:17:54.928703 16, 0x0, sum = 3
8578 11:17:54.929029 17, 0x0, sum = 4
8579 11:17:54.931956 best_step = 15
8580 11:17:54.932253
8581 11:17:54.932488 ==
8582 11:17:54.935062 Dram Type= 6, Freq= 0, CH_1, rank 0
8583 11:17:54.938956 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8584 11:17:54.939258 ==
8585 11:17:54.942256 RX Vref Scan: 1
8586 11:17:54.942559
8587 11:17:54.942964 Set Vref Range= 24 -> 127
8588 11:17:54.943209
8589 11:17:54.945285 RX Vref 24 -> 127, step: 1
8590 11:17:54.945618
8591 11:17:54.948504 RX Delay 27 -> 252, step: 4
8592 11:17:54.948800
8593 11:17:54.951727 Set Vref, RX VrefLevel [Byte0]: 24
8594 11:17:54.955398 [Byte1]: 24
8595 11:17:54.955748
8596 11:17:54.958406 Set Vref, RX VrefLevel [Byte0]: 25
8597 11:17:54.961679 [Byte1]: 25
8598 11:17:54.961979
8599 11:17:54.965141 Set Vref, RX VrefLevel [Byte0]: 26
8600 11:17:54.968590 [Byte1]: 26
8601 11:17:54.972323
8602 11:17:54.972619 Set Vref, RX VrefLevel [Byte0]: 27
8603 11:17:54.975840 [Byte1]: 27
8604 11:17:54.979878
8605 11:17:54.980178 Set Vref, RX VrefLevel [Byte0]: 28
8606 11:17:54.982960 [Byte1]: 28
8607 11:17:54.987734
8608 11:17:54.987959 Set Vref, RX VrefLevel [Byte0]: 29
8609 11:17:54.990743 [Byte1]: 29
8610 11:17:54.995082
8611 11:17:54.995309 Set Vref, RX VrefLevel [Byte0]: 30
8612 11:17:54.998300 [Byte1]: 30
8613 11:17:55.002773
8614 11:17:55.003000 Set Vref, RX VrefLevel [Byte0]: 31
8615 11:17:55.005785 [Byte1]: 31
8616 11:17:55.010331
8617 11:17:55.010558 Set Vref, RX VrefLevel [Byte0]: 32
8618 11:17:55.013295 [Byte1]: 32
8619 11:17:55.017531
8620 11:17:55.017756 Set Vref, RX VrefLevel [Byte0]: 33
8621 11:17:55.020605 [Byte1]: 33
8622 11:17:55.025039
8623 11:17:55.025264 Set Vref, RX VrefLevel [Byte0]: 34
8624 11:17:55.028282 [Byte1]: 34
8625 11:17:55.032923
8626 11:17:55.033147 Set Vref, RX VrefLevel [Byte0]: 35
8627 11:17:55.036074 [Byte1]: 35
8628 11:17:55.039976
8629 11:17:55.040201 Set Vref, RX VrefLevel [Byte0]: 36
8630 11:17:55.043641 [Byte1]: 36
8631 11:17:55.047386
8632 11:17:55.047609 Set Vref, RX VrefLevel [Byte0]: 37
8633 11:17:55.051145 [Byte1]: 37
8634 11:17:55.055059
8635 11:17:55.055280 Set Vref, RX VrefLevel [Byte0]: 38
8636 11:17:55.058215 [Byte1]: 38
8637 11:17:55.062838
8638 11:17:55.063092 Set Vref, RX VrefLevel [Byte0]: 39
8639 11:17:55.066227 [Byte1]: 39
8640 11:17:55.070073
8641 11:17:55.070320 Set Vref, RX VrefLevel [Byte0]: 40
8642 11:17:55.073583 [Byte1]: 40
8643 11:17:55.078120
8644 11:17:55.078532 Set Vref, RX VrefLevel [Byte0]: 41
8645 11:17:55.081143 [Byte1]: 41
8646 11:17:55.085431
8647 11:17:55.085846 Set Vref, RX VrefLevel [Byte0]: 42
8648 11:17:55.088456 [Byte1]: 42
8649 11:17:55.092681
8650 11:17:55.092972 Set Vref, RX VrefLevel [Byte0]: 43
8651 11:17:55.096215 [Byte1]: 43
8652 11:17:55.100500
8653 11:17:55.100680 Set Vref, RX VrefLevel [Byte0]: 44
8654 11:17:55.103548 [Byte1]: 44
8655 11:17:55.107982
8656 11:17:55.108160 Set Vref, RX VrefLevel [Byte0]: 45
8657 11:17:55.111095 [Byte1]: 45
8658 11:17:55.115629
8659 11:17:55.115881 Set Vref, RX VrefLevel [Byte0]: 46
8660 11:17:55.118706 [Byte1]: 46
8661 11:17:55.122912
8662 11:17:55.123148 Set Vref, RX VrefLevel [Byte0]: 47
8663 11:17:55.126178 [Byte1]: 47
8664 11:17:55.130629
8665 11:17:55.130881 Set Vref, RX VrefLevel [Byte0]: 48
8666 11:17:55.134009 [Byte1]: 48
8667 11:17:55.137842
8668 11:17:55.138180 Set Vref, RX VrefLevel [Byte0]: 49
8669 11:17:55.141647 [Byte1]: 49
8670 11:17:55.145863
8671 11:17:55.146186 Set Vref, RX VrefLevel [Byte0]: 50
8672 11:17:55.149271 [Byte1]: 50
8673 11:17:55.153483
8674 11:17:55.154037 Set Vref, RX VrefLevel [Byte0]: 51
8675 11:17:55.156419 [Byte1]: 51
8676 11:17:55.160797
8677 11:17:55.161235 Set Vref, RX VrefLevel [Byte0]: 52
8678 11:17:55.164051 [Byte1]: 52
8679 11:17:55.168400
8680 11:17:55.168808 Set Vref, RX VrefLevel [Byte0]: 53
8681 11:17:55.171703 [Byte1]: 53
8682 11:17:55.175809
8683 11:17:55.176128 Set Vref, RX VrefLevel [Byte0]: 54
8684 11:17:55.179501 [Byte1]: 54
8685 11:17:55.183729
8686 11:17:55.184163 Set Vref, RX VrefLevel [Byte0]: 55
8687 11:17:55.186716 [Byte1]: 55
8688 11:17:55.190847
8689 11:17:55.191438 Set Vref, RX VrefLevel [Byte0]: 56
8690 11:17:55.194409 [Byte1]: 56
8691 11:17:55.198740
8692 11:17:55.199059 Set Vref, RX VrefLevel [Byte0]: 57
8693 11:17:55.202040 [Byte1]: 57
8694 11:17:55.206574
8695 11:17:55.207134 Set Vref, RX VrefLevel [Byte0]: 58
8696 11:17:55.209534 [Byte1]: 58
8697 11:17:55.214116
8698 11:17:55.214706 Set Vref, RX VrefLevel [Byte0]: 59
8699 11:17:55.217360 [Byte1]: 59
8700 11:17:55.220984
8701 11:17:55.221308 Set Vref, RX VrefLevel [Byte0]: 60
8702 11:17:55.224236 [Byte1]: 60
8703 11:17:55.228823
8704 11:17:55.229153 Set Vref, RX VrefLevel [Byte0]: 61
8705 11:17:55.231852 [Byte1]: 61
8706 11:17:55.236218
8707 11:17:55.236640 Set Vref, RX VrefLevel [Byte0]: 62
8708 11:17:55.239463 [Byte1]: 62
8709 11:17:55.243894
8710 11:17:55.244235 Set Vref, RX VrefLevel [Byte0]: 63
8711 11:17:55.246928 [Byte1]: 63
8712 11:17:55.250881
8713 11:17:55.251226 Set Vref, RX VrefLevel [Byte0]: 64
8714 11:17:55.254824 [Byte1]: 64
8715 11:17:55.258899
8716 11:17:55.259365 Set Vref, RX VrefLevel [Byte0]: 65
8717 11:17:55.261765 [Byte1]: 65
8718 11:17:55.266205
8719 11:17:55.266534 Set Vref, RX VrefLevel [Byte0]: 66
8720 11:17:55.269692 [Byte1]: 66
8721 11:17:55.273594
8722 11:17:55.274181 Set Vref, RX VrefLevel [Byte0]: 67
8723 11:17:55.277619 [Byte1]: 67
8724 11:17:55.281550
8725 11:17:55.281975 Set Vref, RX VrefLevel [Byte0]: 68
8726 11:17:55.284555 [Byte1]: 68
8727 11:17:55.288970
8728 11:17:55.289392 Set Vref, RX VrefLevel [Byte0]: 69
8729 11:17:55.292804 [Byte1]: 69
8730 11:17:55.296552
8731 11:17:55.297182 Set Vref, RX VrefLevel [Byte0]: 70
8732 11:17:55.299412 [Byte1]: 70
8733 11:17:55.304111
8734 11:17:55.304552 Set Vref, RX VrefLevel [Byte0]: 71
8735 11:17:55.307720 [Byte1]: 71
8736 11:17:55.311473
8737 11:17:55.311981 Set Vref, RX VrefLevel [Byte0]: 72
8738 11:17:55.315033 [Byte1]: 72
8739 11:17:55.319802
8740 11:17:55.320458 Set Vref, RX VrefLevel [Byte0]: 73
8741 11:17:55.322697 [Byte1]: 73
8742 11:17:55.326910
8743 11:17:55.327461 Set Vref, RX VrefLevel [Byte0]: 74
8744 11:17:55.330118 [Byte1]: 74
8745 11:17:55.333862
8746 11:17:55.334285 Set Vref, RX VrefLevel [Byte0]: 75
8747 11:17:55.337814 [Byte1]: 75
8748 11:17:55.341523
8749 11:17:55.342037 Set Vref, RX VrefLevel [Byte0]: 76
8750 11:17:55.345262 [Byte1]: 76
8751 11:17:55.349026
8752 11:17:55.349448 Final RX Vref Byte 0 = 56 to rank0
8753 11:17:55.352215 Final RX Vref Byte 1 = 56 to rank0
8754 11:17:55.355502 Final RX Vref Byte 0 = 56 to rank1
8755 11:17:55.359716 Final RX Vref Byte 1 = 56 to rank1==
8756 11:17:55.363010 Dram Type= 6, Freq= 0, CH_1, rank 0
8757 11:17:55.369343 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8758 11:17:55.369868 ==
8759 11:17:55.370210 DQS Delay:
8760 11:17:55.370523 DQS0 = 0, DQS1 = 0
8761 11:17:55.372254 DQM Delay:
8762 11:17:55.372680 DQM0 = 134, DQM1 = 131
8763 11:17:55.375951 DQ Delay:
8764 11:17:55.379496 DQ0 =140, DQ1 =128, DQ2 =124, DQ3 =130
8765 11:17:55.382438 DQ4 =132, DQ5 =144, DQ6 =142, DQ7 =132
8766 11:17:55.385630 DQ8 =116, DQ9 =122, DQ10 =132, DQ11 =124
8767 11:17:55.389037 DQ12 =138, DQ13 =140, DQ14 =140, DQ15 =140
8768 11:17:55.389492
8769 11:17:55.390008
8770 11:17:55.390349
8771 11:17:55.392428 [DramC_TX_OE_Calibration] TA2
8772 11:17:55.395652 Original DQ_B0 (3 6) =30, OEN = 27
8773 11:17:55.399107 Original DQ_B1 (3 6) =30, OEN = 27
8774 11:17:55.402102 24, 0x0, End_B0=24 End_B1=24
8775 11:17:55.402552 25, 0x0, End_B0=25 End_B1=25
8776 11:17:55.406021 26, 0x0, End_B0=26 End_B1=26
8777 11:17:55.409507 27, 0x0, End_B0=27 End_B1=27
8778 11:17:55.412232 28, 0x0, End_B0=28 End_B1=28
8779 11:17:55.415875 29, 0x0, End_B0=29 End_B1=29
8780 11:17:55.416327 30, 0x0, End_B0=30 End_B1=30
8781 11:17:55.418794 31, 0x4141, End_B0=30 End_B1=30
8782 11:17:55.422296 Byte0 end_step=30 best_step=27
8783 11:17:55.425448 Byte1 end_step=30 best_step=27
8784 11:17:55.429161 Byte0 TX OE(2T, 0.5T) = (3, 3)
8785 11:17:55.432366 Byte1 TX OE(2T, 0.5T) = (3, 3)
8786 11:17:55.432783
8787 11:17:55.433109
8788 11:17:55.438950 [DQSOSCAuto] RK0, (LSB)MR18= 0x1523, (MSB)MR19= 0x303, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
8789 11:17:55.442542 CH1 RK0: MR19=303, MR18=1523
8790 11:17:55.448826 CH1_RK0: MR19=0x303, MR18=0x1523, DQSOSC=392, MR23=63, INC=24, DEC=16
8791 11:17:55.449279
8792 11:17:55.452457 ----->DramcWriteLeveling(PI) begin...
8793 11:17:55.452883 ==
8794 11:17:55.455773 Dram Type= 6, Freq= 0, CH_1, rank 1
8795 11:17:55.458807 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8796 11:17:55.459224 ==
8797 11:17:55.461943 Write leveling (Byte 0): 27 => 27
8798 11:17:55.465611 Write leveling (Byte 1): 27 => 27
8799 11:17:55.468825 DramcWriteLeveling(PI) end<-----
8800 11:17:55.469344
8801 11:17:55.469676 ==
8802 11:17:55.471828 Dram Type= 6, Freq= 0, CH_1, rank 1
8803 11:17:55.475716 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8804 11:17:55.476135 ==
8805 11:17:55.478859 [Gating] SW mode calibration
8806 11:17:55.485520 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8807 11:17:55.492093 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8808 11:17:55.495831 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8809 11:17:55.498813 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8810 11:17:55.505432 1 4 8 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8811 11:17:55.508417 1 4 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8812 11:17:55.512035 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8813 11:17:55.518680 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8814 11:17:55.522147 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8815 11:17:55.525065 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8816 11:17:55.532069 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8817 11:17:55.535085 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
8818 11:17:55.538378 1 5 8 | B1->B0 | 3333 3434 | 0 1 | (0 1) (1 0)
8819 11:17:55.545516 1 5 12 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 1)
8820 11:17:55.548489 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8821 11:17:55.552139 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8822 11:17:55.558461 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8823 11:17:55.562201 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8824 11:17:55.565554 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8825 11:17:55.571840 1 6 4 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
8826 11:17:55.575291 1 6 8 | B1->B0 | 2f2f 2323 | 1 0 | (0 0) (0 0)
8827 11:17:55.578430 1 6 12 | B1->B0 | 4646 4242 | 0 1 | (0 0) (0 0)
8828 11:17:55.585192 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8829 11:17:55.588942 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8830 11:17:55.591953 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8831 11:17:55.594968 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8832 11:17:55.601981 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8833 11:17:55.605012 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8834 11:17:55.608107 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
8835 11:17:55.615279 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8836 11:17:55.618198 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
8837 11:17:55.621560 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8838 11:17:55.628259 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8839 11:17:55.631909 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8840 11:17:55.635060 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8841 11:17:55.641668 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8842 11:17:55.644884 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8843 11:17:55.648030 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8844 11:17:55.655052 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8845 11:17:55.658331 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8846 11:17:55.661604 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8847 11:17:55.668708 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8848 11:17:55.672181 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8849 11:17:55.675260 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8850 11:17:55.681401 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
8851 11:17:55.688312 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
8852 11:17:55.689157 Total UI for P1: 0, mck2ui 16
8853 11:17:55.691877 best dqsien dly found for B1: ( 1, 9, 6)
8854 11:17:55.695375 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8855 11:17:55.698056 Total UI for P1: 0, mck2ui 16
8856 11:17:55.702132 best dqsien dly found for B0: ( 1, 9, 12)
8857 11:17:55.705040 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8858 11:17:55.708125 best DQS1 dly(MCK, UI, PI) = (1, 9, 6)
8859 11:17:55.708552
8860 11:17:55.711894 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8861 11:17:55.718680 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 6)
8862 11:17:55.719197 [Gating] SW calibration Done
8863 11:17:55.719577 ==
8864 11:17:55.721628 Dram Type= 6, Freq= 0, CH_1, rank 1
8865 11:17:55.728163 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8866 11:17:55.728592 ==
8867 11:17:55.728929 RX Vref Scan: 0
8868 11:17:55.729244
8869 11:17:55.731617 RX Vref 0 -> 0, step: 1
8870 11:17:55.732041
8871 11:17:55.734590 RX Delay 0 -> 252, step: 8
8872 11:17:55.738143 iDelay=208, Bit 0, Center 139 (88 ~ 191) 104
8873 11:17:55.741092 iDelay=208, Bit 1, Center 135 (80 ~ 191) 112
8874 11:17:55.744609 iDelay=208, Bit 2, Center 123 (72 ~ 175) 104
8875 11:17:55.751454 iDelay=208, Bit 3, Center 131 (80 ~ 183) 104
8876 11:17:55.754885 iDelay=208, Bit 4, Center 131 (80 ~ 183) 104
8877 11:17:55.757827 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8878 11:17:55.761387 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8879 11:17:55.764403 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8880 11:17:55.768151 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8881 11:17:55.774802 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8882 11:17:55.778116 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8883 11:17:55.781126 iDelay=208, Bit 11, Center 127 (72 ~ 183) 112
8884 11:17:55.784819 iDelay=208, Bit 12, Center 143 (88 ~ 199) 112
8885 11:17:55.791259 iDelay=208, Bit 13, Center 143 (88 ~ 199) 112
8886 11:17:55.794381 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8887 11:17:55.798213 iDelay=208, Bit 15, Center 143 (88 ~ 199) 112
8888 11:17:55.798633 ==
8889 11:17:55.801311 Dram Type= 6, Freq= 0, CH_1, rank 1
8890 11:17:55.804367 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8891 11:17:55.804791 ==
8892 11:17:55.807798 DQS Delay:
8893 11:17:55.808219 DQS0 = 0, DQS1 = 0
8894 11:17:55.808554 DQM Delay:
8895 11:17:55.811061 DQM0 = 136, DQM1 = 133
8896 11:17:55.811472 DQ Delay:
8897 11:17:55.814157 DQ0 =139, DQ1 =135, DQ2 =123, DQ3 =131
8898 11:17:55.817613 DQ4 =131, DQ5 =151, DQ6 =143, DQ7 =135
8899 11:17:55.824064 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =127
8900 11:17:55.827523 DQ12 =143, DQ13 =143, DQ14 =139, DQ15 =143
8901 11:17:55.827676
8902 11:17:55.827795
8903 11:17:55.827905 ==
8904 11:17:55.830876 Dram Type= 6, Freq= 0, CH_1, rank 1
8905 11:17:55.834262 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8906 11:17:55.834394 ==
8907 11:17:55.834498
8908 11:17:55.834594
8909 11:17:55.837691 TX Vref Scan disable
8910 11:17:55.840716 == TX Byte 0 ==
8911 11:17:55.844219 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8912 11:17:55.847204 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8913 11:17:55.850687 == TX Byte 1 ==
8914 11:17:55.853700 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8915 11:17:55.857433 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8916 11:17:55.857516 ==
8917 11:17:55.860693 Dram Type= 6, Freq= 0, CH_1, rank 1
8918 11:17:55.863737 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8919 11:17:55.867321 ==
8920 11:17:55.878833
8921 11:17:55.882488 TX Vref early break, caculate TX vref
8922 11:17:55.885686 TX Vref=16, minBit 0, minWin=23, winSum=384
8923 11:17:55.888786 TX Vref=18, minBit 0, minWin=24, winSum=397
8924 11:17:55.892032 TX Vref=20, minBit 0, minWin=24, winSum=405
8925 11:17:55.895907 TX Vref=22, minBit 1, minWin=24, winSum=408
8926 11:17:55.899023 TX Vref=24, minBit 6, minWin=25, winSum=422
8927 11:17:55.905262 TX Vref=26, minBit 0, minWin=25, winSum=426
8928 11:17:55.909077 TX Vref=28, minBit 0, minWin=26, winSum=428
8929 11:17:55.911876 TX Vref=30, minBit 1, minWin=25, winSum=422
8930 11:17:55.915148 TX Vref=32, minBit 1, minWin=24, winSum=412
8931 11:17:55.919095 TX Vref=34, minBit 0, minWin=24, winSum=408
8932 11:17:55.922110 TX Vref=36, minBit 0, minWin=24, winSum=399
8933 11:17:55.928928 [TxChooseVref] Worse bit 0, Min win 26, Win sum 428, Final Vref 28
8934 11:17:55.929076
8935 11:17:55.931874 Final TX Range 0 Vref 28
8936 11:17:55.932027
8937 11:17:55.932110 ==
8938 11:17:55.935352 Dram Type= 6, Freq= 0, CH_1, rank 1
8939 11:17:55.938637 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8940 11:17:55.938773 ==
8941 11:17:55.938848
8942 11:17:55.942011
8943 11:17:55.942113 TX Vref Scan disable
8944 11:17:55.948811 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =290/100 ps
8945 11:17:55.948927 == TX Byte 0 ==
8946 11:17:55.952299 u2DelayCellOfst[0]=16 cells (5 PI)
8947 11:17:55.955264 u2DelayCellOfst[1]=10 cells (3 PI)
8948 11:17:55.958873 u2DelayCellOfst[2]=0 cells (0 PI)
8949 11:17:55.961917 u2DelayCellOfst[3]=6 cells (2 PI)
8950 11:17:55.965830 u2DelayCellOfst[4]=6 cells (2 PI)
8951 11:17:55.968613 u2DelayCellOfst[5]=16 cells (5 PI)
8952 11:17:55.972278 u2DelayCellOfst[6]=16 cells (5 PI)
8953 11:17:55.975292 u2DelayCellOfst[7]=6 cells (2 PI)
8954 11:17:55.978955 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8955 11:17:55.982172 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8956 11:17:55.985239 == TX Byte 1 ==
8957 11:17:55.988852 u2DelayCellOfst[8]=0 cells (0 PI)
8958 11:17:55.992271 u2DelayCellOfst[9]=3 cells (1 PI)
8959 11:17:55.992791 u2DelayCellOfst[10]=10 cells (3 PI)
8960 11:17:55.995571 u2DelayCellOfst[11]=3 cells (1 PI)
8961 11:17:55.999231 u2DelayCellOfst[12]=13 cells (4 PI)
8962 11:17:56.002193 u2DelayCellOfst[13]=16 cells (5 PI)
8963 11:17:56.005395 u2DelayCellOfst[14]=16 cells (5 PI)
8964 11:17:56.008555 u2DelayCellOfst[15]=16 cells (5 PI)
8965 11:17:56.011886 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8966 11:17:56.018429 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8967 11:17:56.018853 DramC Write-DBI on
8968 11:17:56.019190 ==
8969 11:17:56.022286 Dram Type= 6, Freq= 0, CH_1, rank 1
8970 11:17:56.028572 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8971 11:17:56.029020 ==
8972 11:17:56.029357
8973 11:17:56.029665
8974 11:17:56.029959 TX Vref Scan disable
8975 11:17:56.032371 == TX Byte 0 ==
8976 11:17:56.035856 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8977 11:17:56.039468 == TX Byte 1 ==
8978 11:17:56.042202 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8979 11:17:56.045788 DramC Write-DBI off
8980 11:17:56.046114
8981 11:17:56.046362 [DATLAT]
8982 11:17:56.046528 Freq=1600, CH1 RK1
8983 11:17:56.046691
8984 11:17:56.049254 DATLAT Default: 0xf
8985 11:17:56.049499 0, 0xFFFF, sum = 0
8986 11:17:56.052100 1, 0xFFFF, sum = 0
8987 11:17:56.052305 2, 0xFFFF, sum = 0
8988 11:17:56.055669 3, 0xFFFF, sum = 0
8989 11:17:56.059070 4, 0xFFFF, sum = 0
8990 11:17:56.059243 5, 0xFFFF, sum = 0
8991 11:17:56.062088 6, 0xFFFF, sum = 0
8992 11:17:56.062230 7, 0xFFFF, sum = 0
8993 11:17:56.065631 8, 0xFFFF, sum = 0
8994 11:17:56.065787 9, 0xFFFF, sum = 0
8995 11:17:56.069113 10, 0xFFFF, sum = 0
8996 11:17:56.069243 11, 0xFFFF, sum = 0
8997 11:17:56.072032 12, 0xFFFF, sum = 0
8998 11:17:56.072142 13, 0xFFFF, sum = 0
8999 11:17:56.075773 14, 0x0, sum = 1
9000 11:17:56.075879 15, 0x0, sum = 2
9001 11:17:56.079073 16, 0x0, sum = 3
9002 11:17:56.079244 17, 0x0, sum = 4
9003 11:17:56.082268 best_step = 15
9004 11:17:56.082427
9005 11:17:56.082503 ==
9006 11:17:56.085677 Dram Type= 6, Freq= 0, CH_1, rank 1
9007 11:17:56.088683 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9008 11:17:56.088834 ==
9009 11:17:56.088910 RX Vref Scan: 0
9010 11:17:56.091942
9011 11:17:56.092100 RX Vref 0 -> 0, step: 1
9012 11:17:56.092176
9013 11:17:56.095545 RX Delay 19 -> 252, step: 4
9014 11:17:56.098463 iDelay=195, Bit 0, Center 138 (91 ~ 186) 96
9015 11:17:56.105602 iDelay=195, Bit 1, Center 128 (79 ~ 178) 100
9016 11:17:56.108809 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
9017 11:17:56.112504 iDelay=195, Bit 3, Center 130 (83 ~ 178) 96
9018 11:17:56.115829 iDelay=195, Bit 4, Center 130 (83 ~ 178) 96
9019 11:17:56.118945 iDelay=195, Bit 5, Center 146 (99 ~ 194) 96
9020 11:17:56.121941 iDelay=195, Bit 6, Center 144 (95 ~ 194) 100
9021 11:17:56.128910 iDelay=195, Bit 7, Center 134 (83 ~ 186) 104
9022 11:17:56.132079 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
9023 11:17:56.135152 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9024 11:17:56.138760 iDelay=195, Bit 10, Center 132 (83 ~ 182) 100
9025 11:17:56.142219 iDelay=195, Bit 11, Center 124 (71 ~ 178) 108
9026 11:17:56.148666 iDelay=195, Bit 12, Center 140 (87 ~ 194) 108
9027 11:17:56.151738 iDelay=195, Bit 13, Center 138 (87 ~ 190) 104
9028 11:17:56.155251 iDelay=195, Bit 14, Center 136 (87 ~ 186) 100
9029 11:17:56.158866 iDelay=195, Bit 15, Center 140 (91 ~ 190) 100
9030 11:17:56.161851 ==
9031 11:17:56.162379 Dram Type= 6, Freq= 0, CH_1, rank 1
9032 11:17:56.168805 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9033 11:17:56.169311 ==
9034 11:17:56.169647 DQS Delay:
9035 11:17:56.172285 DQS0 = 0, DQS1 = 0
9036 11:17:56.172707 DQM Delay:
9037 11:17:56.175131 DQM0 = 134, DQM1 = 130
9038 11:17:56.175584 DQ Delay:
9039 11:17:56.178730 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9040 11:17:56.182075 DQ4 =130, DQ5 =146, DQ6 =144, DQ7 =134
9041 11:17:56.185433 DQ8 =116, DQ9 =118, DQ10 =132, DQ11 =124
9042 11:17:56.188371 DQ12 =140, DQ13 =138, DQ14 =136, DQ15 =140
9043 11:17:56.188819
9044 11:17:56.189154
9045 11:17:56.189460
9046 11:17:56.192149 [DramC_TX_OE_Calibration] TA2
9047 11:17:56.195267 Original DQ_B0 (3 6) =30, OEN = 27
9048 11:17:56.198273 Original DQ_B1 (3 6) =30, OEN = 27
9049 11:17:56.202155 24, 0x0, End_B0=24 End_B1=24
9050 11:17:56.204938 25, 0x0, End_B0=25 End_B1=25
9051 11:17:56.205382 26, 0x0, End_B0=26 End_B1=26
9052 11:17:56.208736 27, 0x0, End_B0=27 End_B1=27
9053 11:17:56.212164 28, 0x0, End_B0=28 End_B1=28
9054 11:17:56.215238 29, 0x0, End_B0=29 End_B1=29
9055 11:17:56.215805 30, 0x0, End_B0=30 End_B1=30
9056 11:17:56.218241 31, 0x4545, End_B0=30 End_B1=30
9057 11:17:56.221377 Byte0 end_step=30 best_step=27
9058 11:17:56.225293 Byte1 end_step=30 best_step=27
9059 11:17:56.228120 Byte0 TX OE(2T, 0.5T) = (3, 3)
9060 11:17:56.231943 Byte1 TX OE(2T, 0.5T) = (3, 3)
9061 11:17:56.232370
9062 11:17:56.232707
9063 11:17:56.238373 [DQSOSCAuto] RK1, (LSB)MR18= 0x2208, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 392 ps
9064 11:17:56.241573 CH1 RK1: MR19=303, MR18=2208
9065 11:17:56.248074 CH1_RK1: MR19=0x303, MR18=0x2208, DQSOSC=392, MR23=63, INC=24, DEC=16
9066 11:17:56.251295 [RxdqsGatingPostProcess] freq 1600
9067 11:17:56.257932 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9068 11:17:56.258364 best DQS0 dly(2T, 0.5T) = (1, 1)
9069 11:17:56.261593 best DQS1 dly(2T, 0.5T) = (1, 1)
9070 11:17:56.264602 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9071 11:17:56.267914 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9072 11:17:56.271647 best DQS0 dly(2T, 0.5T) = (1, 1)
9073 11:17:56.274792 best DQS1 dly(2T, 0.5T) = (1, 1)
9074 11:17:56.278158 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9075 11:17:56.281302 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9076 11:17:56.284705 Pre-setting of DQS Precalculation
9077 11:17:56.287995 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9078 11:17:56.298122 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9079 11:17:56.304540 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9080 11:17:56.305058
9081 11:17:56.305497
9082 11:17:56.308074 [Calibration Summary] 3200 Mbps
9083 11:17:56.308511 CH 0, Rank 0
9084 11:17:56.311001 SW Impedance : PASS
9085 11:17:56.311473 DUTY Scan : NO K
9086 11:17:56.315091 ZQ Calibration : PASS
9087 11:17:56.317999 Jitter Meter : NO K
9088 11:17:56.318434 CBT Training : PASS
9089 11:17:56.320995 Write leveling : PASS
9090 11:17:56.324526 RX DQS gating : PASS
9091 11:17:56.325081 RX DQ/DQS(RDDQC) : PASS
9092 11:17:56.328060 TX DQ/DQS : PASS
9093 11:17:56.328486 RX DATLAT : PASS
9094 11:17:56.331110 RX DQ/DQS(Engine): PASS
9095 11:17:56.334735 TX OE : PASS
9096 11:17:56.335175 All Pass.
9097 11:17:56.335566
9098 11:17:56.335883 CH 0, Rank 1
9099 11:17:56.337906 SW Impedance : PASS
9100 11:17:56.341108 DUTY Scan : NO K
9101 11:17:56.341529 ZQ Calibration : PASS
9102 11:17:56.344186 Jitter Meter : NO K
9103 11:17:56.347493 CBT Training : PASS
9104 11:17:56.347911 Write leveling : PASS
9105 11:17:56.350746 RX DQS gating : PASS
9106 11:17:56.354365 RX DQ/DQS(RDDQC) : PASS
9107 11:17:56.354779 TX DQ/DQS : PASS
9108 11:17:56.357386 RX DATLAT : PASS
9109 11:17:56.360685 RX DQ/DQS(Engine): PASS
9110 11:17:56.361103 TX OE : PASS
9111 11:17:56.364073 All Pass.
9112 11:17:56.364496
9113 11:17:56.364826 CH 1, Rank 0
9114 11:17:56.367243 SW Impedance : PASS
9115 11:17:56.367711 DUTY Scan : NO K
9116 11:17:56.370741 ZQ Calibration : PASS
9117 11:17:56.374375 Jitter Meter : NO K
9118 11:17:56.374889 CBT Training : PASS
9119 11:17:56.377614 Write leveling : PASS
9120 11:17:56.380521 RX DQS gating : PASS
9121 11:17:56.380940 RX DQ/DQS(RDDQC) : PASS
9122 11:17:56.384073 TX DQ/DQS : PASS
9123 11:17:56.387374 RX DATLAT : PASS
9124 11:17:56.387795 RX DQ/DQS(Engine): PASS
9125 11:17:56.391110 TX OE : PASS
9126 11:17:56.391663 All Pass.
9127 11:17:56.392007
9128 11:17:56.392318 CH 1, Rank 1
9129 11:17:56.394554 SW Impedance : PASS
9130 11:17:56.397740 DUTY Scan : NO K
9131 11:17:56.398165 ZQ Calibration : PASS
9132 11:17:56.400762 Jitter Meter : NO K
9133 11:17:56.403940 CBT Training : PASS
9134 11:17:56.404360 Write leveling : PASS
9135 11:17:56.407614 RX DQS gating : PASS
9136 11:17:56.411142 RX DQ/DQS(RDDQC) : PASS
9137 11:17:56.411695 TX DQ/DQS : PASS
9138 11:17:56.414093 RX DATLAT : PASS
9139 11:17:56.417490 RX DQ/DQS(Engine): PASS
9140 11:17:56.418009 TX OE : PASS
9141 11:17:56.421079 All Pass.
9142 11:17:56.421498
9143 11:17:56.421830 DramC Write-DBI on
9144 11:17:56.423911 PER_BANK_REFRESH: Hybrid Mode
9145 11:17:56.424427 TX_TRACKING: ON
9146 11:17:56.433755 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9147 11:17:56.440598 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9148 11:17:56.450803 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9149 11:17:56.454009 [FAST_K] Save calibration result to emmc
9150 11:17:56.457461 sync common calibartion params.
9151 11:17:56.457980 sync cbt_mode0:1, 1:1
9152 11:17:56.460503 dram_init: ddr_geometry: 2
9153 11:17:56.463475 dram_init: ddr_geometry: 2
9154 11:17:56.463997 dram_init: ddr_geometry: 2
9155 11:17:56.467012 0:dram_rank_size:100000000
9156 11:17:56.470954 1:dram_rank_size:100000000
9157 11:17:56.477235 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9158 11:17:56.477764 DFS_SHUFFLE_HW_MODE: ON
9159 11:17:56.480073 dramc_set_vcore_voltage set vcore to 725000
9160 11:17:56.483471 Read voltage for 1600, 0
9161 11:17:56.483895 Vio18 = 0
9162 11:17:56.486851 Vcore = 725000
9163 11:17:56.487277 Vdram = 0
9164 11:17:56.487646 Vddq = 0
9165 11:17:56.489835 Vmddr = 0
9166 11:17:56.490258 switch to 3200 Mbps bootup
9167 11:17:56.493210 [DramcRunTimeConfig]
9168 11:17:56.493632 PHYPLL
9169 11:17:56.496706 DPM_CONTROL_AFTERK: ON
9170 11:17:56.497223 PER_BANK_REFRESH: ON
9171 11:17:56.500533 REFRESH_OVERHEAD_REDUCTION: ON
9172 11:17:56.503292 CMD_PICG_NEW_MODE: OFF
9173 11:17:56.503851 XRTWTW_NEW_MODE: ON
9174 11:17:56.506883 XRTRTR_NEW_MODE: ON
9175 11:17:56.507465 TX_TRACKING: ON
9176 11:17:56.509664 RDSEL_TRACKING: OFF
9177 11:17:56.512924 DQS Precalculation for DVFS: ON
9178 11:17:56.513350 RX_TRACKING: OFF
9179 11:17:56.516887 HW_GATING DBG: ON
9180 11:17:56.517404 ZQCS_ENABLE_LP4: ON
9181 11:17:56.519822 RX_PICG_NEW_MODE: ON
9182 11:17:56.520246 TX_PICG_NEW_MODE: ON
9183 11:17:56.523046 ENABLE_RX_DCM_DPHY: ON
9184 11:17:56.526648 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9185 11:17:56.529929 DUMMY_READ_FOR_TRACKING: OFF
9186 11:17:56.530456 !!! SPM_CONTROL_AFTERK: OFF
9187 11:17:56.532921 !!! SPM could not control APHY
9188 11:17:56.536651 IMPEDANCE_TRACKING: ON
9189 11:17:56.537076 TEMP_SENSOR: ON
9190 11:17:56.540095 HW_SAVE_FOR_SR: OFF
9191 11:17:56.543184 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9192 11:17:56.546445 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9193 11:17:56.549815 Read ODT Tracking: ON
9194 11:17:56.550235 Refresh Rate DeBounce: ON
9195 11:17:56.552987 DFS_NO_QUEUE_FLUSH: ON
9196 11:17:56.556376 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9197 11:17:56.559707 ENABLE_DFS_RUNTIME_MRW: OFF
9198 11:17:56.560224 DDR_RESERVE_NEW_MODE: ON
9199 11:17:56.562641 MR_CBT_SWITCH_FREQ: ON
9200 11:17:56.566597 =========================
9201 11:17:56.584100 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9202 11:17:56.586849 dram_init: ddr_geometry: 2
9203 11:17:56.605535 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9204 11:17:56.608501 dram_init: dram init end (result: 0)
9205 11:17:56.615659 DRAM-K: Full calibration passed in 24461 msecs
9206 11:17:56.619020 MRC: failed to locate region type 0.
9207 11:17:56.619583 DRAM rank0 size:0x100000000,
9208 11:17:56.621854 DRAM rank1 size=0x100000000
9209 11:17:56.631893 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9210 11:17:56.638690 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9211 11:17:56.645120 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9212 11:17:56.651498 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9213 11:17:56.654708 DRAM rank0 size:0x100000000,
9214 11:17:56.658854 DRAM rank1 size=0x100000000
9215 11:17:56.659415 CBMEM:
9216 11:17:56.662077 IMD: root @ 0xfffff000 254 entries.
9217 11:17:56.665030 IMD: root @ 0xffffec00 62 entries.
9218 11:17:56.668270 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9219 11:17:56.671457 WARNING: RO_VPD is uninitialized or empty.
9220 11:17:56.678233 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9221 11:17:56.685581 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9222 11:17:56.697984 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9223 11:17:56.709554 BS: romstage times (exec / console): total (unknown) / 23992 ms
9224 11:17:56.709990
9225 11:17:56.710328
9226 11:17:56.719140 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9227 11:17:56.722534 ARM64: Exception handlers installed.
9228 11:17:56.725934 ARM64: Testing exception
9229 11:17:56.729552 ARM64: Done test exception
9230 11:17:56.729998 Enumerating buses...
9231 11:17:56.732506 Show all devs... Before device enumeration.
9232 11:17:56.735785 Root Device: enabled 1
9233 11:17:56.739380 CPU_CLUSTER: 0: enabled 1
9234 11:17:56.739893 CPU: 00: enabled 1
9235 11:17:56.742480 Compare with tree...
9236 11:17:56.742918 Root Device: enabled 1
9237 11:17:56.746447 CPU_CLUSTER: 0: enabled 1
9238 11:17:56.749284 CPU: 00: enabled 1
9239 11:17:56.749714 Root Device scanning...
9240 11:17:56.752411 scan_static_bus for Root Device
9241 11:17:56.755933 CPU_CLUSTER: 0 enabled
9242 11:17:56.759241 scan_static_bus for Root Device done
9243 11:17:56.762689 scan_bus: bus Root Device finished in 8 msecs
9244 11:17:56.763215 done
9245 11:17:56.769580 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9246 11:17:56.772791 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9247 11:17:56.779287 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9248 11:17:56.782761 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9249 11:17:56.785933 Allocating resources...
9250 11:17:56.789487 Reading resources...
9251 11:17:56.792590 Root Device read_resources bus 0 link: 0
9252 11:17:56.793013 DRAM rank0 size:0x100000000,
9253 11:17:56.795543 DRAM rank1 size=0x100000000
9254 11:17:56.799141 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9255 11:17:56.802316 CPU: 00 missing read_resources
9256 11:17:56.805864 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9257 11:17:56.812364 Root Device read_resources bus 0 link: 0 done
9258 11:17:56.812785 Done reading resources.
9259 11:17:56.818931 Show resources in subtree (Root Device)...After reading.
9260 11:17:56.822324 Root Device child on link 0 CPU_CLUSTER: 0
9261 11:17:56.825901 CPU_CLUSTER: 0 child on link 0 CPU: 00
9262 11:17:56.835420 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9263 11:17:56.835852 CPU: 00
9264 11:17:56.839315 Root Device assign_resources, bus 0 link: 0
9265 11:17:56.842520 CPU_CLUSTER: 0 missing set_resources
9266 11:17:56.845612 Root Device assign_resources, bus 0 link: 0 done
9267 11:17:56.849205 Done setting resources.
9268 11:17:56.855619 Show resources in subtree (Root Device)...After assigning values.
9269 11:17:56.858746 Root Device child on link 0 CPU_CLUSTER: 0
9270 11:17:56.862827 CPU_CLUSTER: 0 child on link 0 CPU: 00
9271 11:17:56.872181 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9272 11:17:56.872724 CPU: 00
9273 11:17:56.875737 Done allocating resources.
9274 11:17:56.878797 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9275 11:17:56.882020 Enabling resources...
9276 11:17:56.882536 done.
9277 11:17:56.889047 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9278 11:17:56.889567 Initializing devices...
9279 11:17:56.892102 Root Device init
9280 11:17:56.892517 init hardware done!
9281 11:17:56.895481 0x00000018: ctrlr->caps
9282 11:17:56.898848 52.000 MHz: ctrlr->f_max
9283 11:17:56.899285 0.400 MHz: ctrlr->f_min
9284 11:17:56.901813 0x40ff8080: ctrlr->voltages
9285 11:17:56.902301 sclk: 390625
9286 11:17:56.905572 Bus Width = 1
9287 11:17:56.905989 sclk: 390625
9288 11:17:56.908648 Bus Width = 1
9289 11:17:56.909067 Early init status = 3
9290 11:17:56.915397 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9291 11:17:56.918607 in-header: 03 fc 00 00 01 00 00 00
9292 11:17:56.919040 in-data: 00
9293 11:17:56.925249 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9294 11:17:56.928837 in-header: 03 fd 00 00 00 00 00 00
9295 11:17:56.931711 in-data:
9296 11:17:56.935317 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9297 11:17:56.939268 in-header: 03 fc 00 00 01 00 00 00
9298 11:17:56.942770 in-data: 00
9299 11:17:56.945746 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9300 11:17:56.950992 in-header: 03 fd 00 00 00 00 00 00
9301 11:17:56.954402 in-data:
9302 11:17:56.957656 [SSUSB] Setting up USB HOST controller...
9303 11:17:56.961016 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9304 11:17:56.964307 [SSUSB] phy power-on done.
9305 11:17:56.967634 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9306 11:17:56.974672 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9307 11:17:56.977594 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9308 11:17:56.984379 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9309 11:17:56.991272 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9310 11:17:56.997854 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9311 11:17:57.004635 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9312 11:17:57.011476 read SPI 0x705bc 0x1f6a: 925 us, 8694 KB/s, 69.552 Mbps
9313 11:17:57.014369 SPM: binary array size = 0x9dc
9314 11:17:57.017683 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9315 11:17:57.024198 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9316 11:17:57.030826 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9317 11:17:57.034306 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9318 11:17:57.040756 configure_display: Starting display init
9319 11:17:57.074567 anx7625_power_on_init: Init interface.
9320 11:17:57.077667 anx7625_disable_pd_protocol: Disabled PD feature.
9321 11:17:57.080826 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9322 11:17:57.108700 anx7625_start_dp_work: Secure OCM version=00
9323 11:17:57.112512 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9324 11:17:57.126597 sp_tx_get_edid_block: EDID Block = 1
9325 11:17:57.229619 Extracted contents:
9326 11:17:57.233025 header: 00 ff ff ff ff ff ff 00
9327 11:17:57.236170 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9328 11:17:57.239570 version: 01 04
9329 11:17:57.242988 basic params: 95 1f 11 78 0a
9330 11:17:57.246319 chroma info: 76 90 94 55 54 90 27 21 50 54
9331 11:17:57.249140 established: 00 00 00
9332 11:17:57.255854 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9333 11:17:57.259562 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9334 11:17:57.265557 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9335 11:17:57.272350 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9336 11:17:57.279422 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9337 11:17:57.282466 extensions: 00
9338 11:17:57.282880 checksum: fb
9339 11:17:57.283276
9340 11:17:57.285814 Manufacturer: IVO Model 57d Serial Number 0
9341 11:17:57.289448 Made week 0 of 2020
9342 11:17:57.289978 EDID version: 1.4
9343 11:17:57.292307 Digital display
9344 11:17:57.295618 6 bits per primary color channel
9345 11:17:57.296046 DisplayPort interface
9346 11:17:57.298847 Maximum image size: 31 cm x 17 cm
9347 11:17:57.302752 Gamma: 220%
9348 11:17:57.303257 Check DPMS levels
9349 11:17:57.305631 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9350 11:17:57.312133 First detailed timing is preferred timing
9351 11:17:57.312674 Established timings supported:
9352 11:17:57.315809 Standard timings supported:
9353 11:17:57.318957 Detailed timings
9354 11:17:57.322137 Hex of detail: 383680a07038204018303c0035ae10000019
9355 11:17:57.325900 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9356 11:17:57.332238 0780 0798 07c8 0820 hborder 0
9357 11:17:57.335790 0438 043b 0447 0458 vborder 0
9358 11:17:57.338889 -hsync -vsync
9359 11:17:57.339316 Did detailed timing
9360 11:17:57.345713 Hex of detail: 000000000000000000000000000000000000
9361 11:17:57.348476 Manufacturer-specified data, tag 0
9362 11:17:57.352088 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9363 11:17:57.355042 ASCII string: InfoVision
9364 11:17:57.358658 Hex of detail: 000000fe00523134304e574635205248200a
9365 11:17:57.362092 ASCII string: R140NWF5 RH
9366 11:17:57.362454 Checksum
9367 11:17:57.365115 Checksum: 0xfb (valid)
9368 11:17:57.368629 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9369 11:17:57.371804 DSI data_rate: 832800000 bps
9370 11:17:57.378761 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9371 11:17:57.381865 anx7625_parse_edid: pixelclock(138800).
9372 11:17:57.385274 hactive(1920), hsync(48), hfp(24), hbp(88)
9373 11:17:57.388649 vactive(1080), vsync(12), vfp(3), vbp(17)
9374 11:17:57.392071 anx7625_dsi_config: config dsi.
9375 11:17:57.398570 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9376 11:17:57.411417 anx7625_dsi_config: success to config DSI
9377 11:17:57.415414 anx7625_dp_start: MIPI phy setup OK.
9378 11:17:57.418501 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9379 11:17:57.421728 mtk_ddp_mode_set invalid vrefresh 60
9380 11:17:57.425311 main_disp_path_setup
9381 11:17:57.425829 ovl_layer_smi_id_en
9382 11:17:57.428134 ovl_layer_smi_id_en
9383 11:17:57.428547 ccorr_config
9384 11:17:57.428969 aal_config
9385 11:17:57.431534 gamma_config
9386 11:17:57.432043 postmask_config
9387 11:17:57.435314 dither_config
9388 11:17:57.438533 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9389 11:17:57.444607 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9390 11:17:57.448128 Root Device init finished in 553 msecs
9391 11:17:57.451776 CPU_CLUSTER: 0 init
9392 11:17:57.457966 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9393 11:17:57.461501 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9394 11:17:57.464471 APU_MBOX 0x190000b0 = 0x10001
9395 11:17:57.468096 APU_MBOX 0x190001b0 = 0x10001
9396 11:17:57.471007 APU_MBOX 0x190005b0 = 0x10001
9397 11:17:57.474603 APU_MBOX 0x190006b0 = 0x10001
9398 11:17:57.477604 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9399 11:17:57.490431 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9400 11:17:57.502765 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9401 11:17:57.509730 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9402 11:17:57.521373 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9403 11:17:57.530076 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9404 11:17:57.533880 CPU_CLUSTER: 0 init finished in 81 msecs
9405 11:17:57.537293 Devices initialized
9406 11:17:57.540781 Show all devs... After init.
9407 11:17:57.541320 Root Device: enabled 1
9408 11:17:57.543817 CPU_CLUSTER: 0: enabled 1
9409 11:17:57.547010 CPU: 00: enabled 1
9410 11:17:57.550764 BS: BS_DEV_INIT run times (exec / console): 211 / 447 ms
9411 11:17:57.553489 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9412 11:17:57.557075 ELOG: NV offset 0x57f000 size 0x1000
9413 11:17:57.563507 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9414 11:17:57.570699 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9415 11:17:57.573878 ELOG: Event(17) added with size 13 at 2023-06-05 11:17:45 UTC
9416 11:17:57.577235 out: cmd=0x121: 03 db 21 01 00 00 00 00
9417 11:17:57.580652 in-header: 03 d2 00 00 2c 00 00 00
9418 11:17:57.594375 in-data: 8d 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9419 11:17:57.600971 ELOG: Event(A1) added with size 10 at 2023-06-05 11:17:45 UTC
9420 11:17:57.607182 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9421 11:17:57.613923 ELOG: Event(A0) added with size 9 at 2023-06-05 11:17:45 UTC
9422 11:17:57.617096 elog_add_boot_reason: Logged dev mode boot
9423 11:17:57.620637 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9424 11:17:57.624050 Finalize devices...
9425 11:17:57.624544 Devices finalized
9426 11:17:57.630527 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9427 11:17:57.633485 Writing coreboot table at 0xffe64000
9428 11:17:57.636987 0. 000000000010a000-0000000000113fff: RAMSTAGE
9429 11:17:57.640202 1. 0000000040000000-00000000400fffff: RAM
9430 11:17:57.643857 2. 0000000040100000-000000004032afff: RAMSTAGE
9431 11:17:57.650158 3. 000000004032b000-00000000545fffff: RAM
9432 11:17:57.653922 4. 0000000054600000-000000005465ffff: BL31
9433 11:17:57.657167 5. 0000000054660000-00000000ffe63fff: RAM
9434 11:17:57.663412 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9435 11:17:57.667063 7. 0000000100000000-000000023fffffff: RAM
9436 11:17:57.667699 Passing 5 GPIOs to payload:
9437 11:17:57.673471 NAME | PORT | POLARITY | VALUE
9438 11:17:57.676928 EC in RW | 0x000000aa | low | undefined
9439 11:17:57.683387 EC interrupt | 0x00000005 | low | undefined
9440 11:17:57.687245 TPM interrupt | 0x000000ab | high | undefined
9441 11:17:57.690135 SD card detect | 0x00000011 | high | undefined
9442 11:17:57.697127 speaker enable | 0x00000093 | high | undefined
9443 11:17:57.700339 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9444 11:17:57.703770 in-header: 03 f9 00 00 02 00 00 00
9445 11:17:57.704194 in-data: 02 00
9446 11:17:57.707124 ADC[4]: Raw value=904726 ID=7
9447 11:17:57.710097 ADC[3]: Raw value=213441 ID=1
9448 11:17:57.710527 RAM Code: 0x71
9449 11:17:57.713868 ADC[6]: Raw value=75332 ID=0
9450 11:17:57.716789 ADC[5]: Raw value=213072 ID=1
9451 11:17:57.717213 SKU Code: 0x1
9452 11:17:57.723733 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 4e98
9453 11:17:57.726688 coreboot table: 964 bytes.
9454 11:17:57.730123 IMD ROOT 0. 0xfffff000 0x00001000
9455 11:17:57.733777 IMD SMALL 1. 0xffffe000 0x00001000
9456 11:17:57.736764 RO MCACHE 2. 0xffffc000 0x00001104
9457 11:17:57.739844 CONSOLE 3. 0xfff7c000 0x00080000
9458 11:17:57.743588 FMAP 4. 0xfff7b000 0x00000452
9459 11:17:57.746741 TIME STAMP 5. 0xfff7a000 0x00000910
9460 11:17:57.749948 VBOOT WORK 6. 0xfff66000 0x00014000
9461 11:17:57.753722 RAMOOPS 7. 0xffe66000 0x00100000
9462 11:17:57.756811 COREBOOT 8. 0xffe64000 0x00002000
9463 11:17:57.757238 IMD small region:
9464 11:17:57.760074 IMD ROOT 0. 0xffffec00 0x00000400
9465 11:17:57.763176 VPD 1. 0xffffeba0 0x0000004c
9466 11:17:57.766527 MMC STATUS 2. 0xffffeb80 0x00000004
9467 11:17:57.773916 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9468 11:17:57.774399 Probing TPM: done!
9469 11:17:57.780155 Connected to device vid:did:rid of 1ae0:0028:00
9470 11:17:57.787353 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9b9523
9471 11:17:57.790312 Initialized TPM device CR50 revision 0
9472 11:17:57.794443 Checking cr50 for pending updates
9473 11:17:57.799861 Reading cr50 TPM mode
9474 11:17:57.808603 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9475 11:17:57.815522 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9476 11:17:57.855631 read SPI 0x3990ec 0x4f1b0: 34848 us, 9297 KB/s, 74.376 Mbps
9477 11:17:57.858601 Checking segment from ROM address 0x40100000
9478 11:17:57.862232 Checking segment from ROM address 0x4010001c
9479 11:17:57.869108 Loading segment from ROM address 0x40100000
9480 11:17:57.869626 code (compression=0)
9481 11:17:57.878883 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9482 11:17:57.885897 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9483 11:17:57.886407 it's not compressed!
9484 11:17:57.892073 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9485 11:17:57.895208 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9486 11:17:57.916020 Loading segment from ROM address 0x4010001c
9487 11:17:57.916537 Entry Point 0x80000000
9488 11:17:57.919131 Loaded segments
9489 11:17:57.922477 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9490 11:17:57.929130 Jumping to boot code at 0x80000000(0xffe64000)
9491 11:17:57.935827 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9492 11:17:57.942204 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9493 11:17:57.950454 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9494 11:17:57.953664 Checking segment from ROM address 0x40100000
9495 11:17:57.957479 Checking segment from ROM address 0x4010001c
9496 11:17:57.963952 Loading segment from ROM address 0x40100000
9497 11:17:57.964404 code (compression=1)
9498 11:17:57.970497 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9499 11:17:57.980491 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9500 11:17:57.980986 using LZMA
9501 11:17:57.988770 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9502 11:17:57.995450 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9503 11:17:57.998432 Loading segment from ROM address 0x4010001c
9504 11:17:57.999060 Entry Point 0x54601000
9505 11:17:58.001734 Loaded segments
9506 11:17:58.005275 NOTICE: MT8192 bl31_setup
9507 11:17:58.011943 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9508 11:17:58.015439 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9509 11:17:58.019122 WARNING: region 0:
9510 11:17:58.022290 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9511 11:17:58.022798 WARNING: region 1:
9512 11:17:58.028963 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9513 11:17:58.032162 WARNING: region 2:
9514 11:17:58.035471 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9515 11:17:58.038890 WARNING: region 3:
9516 11:17:58.042631 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9517 11:17:58.045754 WARNING: region 4:
9518 11:17:58.048877 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9519 11:17:58.052959 WARNING: region 5:
9520 11:17:58.055670 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9521 11:17:58.059426 WARNING: region 6:
9522 11:17:58.062688 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9523 11:17:58.063104 WARNING: region 7:
9524 11:17:58.069792 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9525 11:17:58.076041 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9526 11:17:58.079353 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9527 11:17:58.082524 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9528 11:17:58.085746 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9529 11:17:58.092497 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9530 11:17:58.096011 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9531 11:17:58.102682 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9532 11:17:58.106162 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9533 11:17:58.109161 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9534 11:17:58.116037 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9535 11:17:58.119517 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9536 11:17:58.123036 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9537 11:17:58.129976 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9538 11:17:58.132772 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9539 11:17:58.139224 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9540 11:17:58.143026 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9541 11:17:58.145946 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9542 11:17:58.152507 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9543 11:17:58.156276 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9544 11:17:58.159446 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9545 11:17:58.166443 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9546 11:17:58.169690 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9547 11:17:58.176446 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9548 11:17:58.179502 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9549 11:17:58.183489 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9550 11:17:58.189724 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9551 11:17:58.192809 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9552 11:17:58.199693 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9553 11:17:58.202529 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9554 11:17:58.206306 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9555 11:17:58.212589 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9556 11:17:58.215962 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9557 11:17:58.219496 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9558 11:17:58.226029 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9559 11:17:58.229460 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9560 11:17:58.233155 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9561 11:17:58.236163 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9562 11:17:58.242814 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9563 11:17:58.246025 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9564 11:17:58.249674 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9565 11:17:58.253017 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9566 11:17:58.256117 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9567 11:17:58.262795 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9568 11:17:58.266386 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9569 11:17:58.269829 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9570 11:17:58.276622 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9571 11:17:58.279810 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9572 11:17:58.283099 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9573 11:17:58.286354 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9574 11:17:58.293349 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9575 11:17:58.296445 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9576 11:17:58.303091 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9577 11:17:58.306903 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9578 11:17:58.313723 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9579 11:17:58.316558 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9580 11:17:58.320005 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9581 11:17:58.326494 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9582 11:17:58.330067 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9583 11:17:58.336979 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9584 11:17:58.339933 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9585 11:17:58.346530 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9586 11:17:58.350122 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9587 11:17:58.353173 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9588 11:17:58.359846 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9589 11:17:58.363165 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9590 11:17:58.369970 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9591 11:17:58.373548 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9592 11:17:58.379903 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9593 11:17:58.383285 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9594 11:17:58.386901 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9595 11:17:58.393108 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9596 11:17:58.396674 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9597 11:17:58.403203 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9598 11:17:58.406827 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9599 11:17:58.413178 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9600 11:17:58.416899 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9601 11:17:58.419943 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9602 11:17:58.426536 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9603 11:17:58.430497 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9604 11:17:58.437203 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9605 11:17:58.439930 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9606 11:17:58.446498 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9607 11:17:58.450019 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9608 11:17:58.453016 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9609 11:17:58.460504 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9610 11:17:58.463665 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9611 11:17:58.470191 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9612 11:17:58.473839 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9613 11:17:58.480275 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9614 11:17:58.483446 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9615 11:17:58.486567 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9616 11:17:58.493664 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9617 11:17:58.497144 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9618 11:17:58.503427 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9619 11:17:58.506503 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9620 11:17:58.514240 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9621 11:17:58.517384 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9622 11:17:58.520706 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9623 11:17:58.523545 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9624 11:17:58.530480 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9625 11:17:58.534019 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9626 11:17:58.537462 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9627 11:17:58.543463 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9628 11:17:58.547032 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9629 11:17:58.550665 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9630 11:17:58.557082 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9631 11:17:58.560042 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9632 11:17:58.566819 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9633 11:17:58.570648 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9634 11:17:58.573835 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9635 11:17:58.580936 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9636 11:17:58.583899 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9637 11:17:58.590334 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9638 11:17:58.593461 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9639 11:17:58.597170 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9640 11:17:58.603948 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9641 11:17:58.607004 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9642 11:17:58.610641 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9643 11:17:58.617269 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9644 11:17:58.620446 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9645 11:17:58.624190 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9646 11:17:58.627468 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9647 11:17:58.630571 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9648 11:17:58.637470 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9649 11:17:58.640375 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9650 11:17:58.647536 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9651 11:17:58.650619 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9652 11:17:58.654021 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9653 11:17:58.660508 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9654 11:17:58.664051 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9655 11:17:58.667705 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9656 11:17:58.674442 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9657 11:17:58.677733 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9658 11:17:58.684293 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9659 11:17:58.687505 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9660 11:17:58.690548 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9661 11:17:58.697419 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9662 11:17:58.700405 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9663 11:17:58.707463 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9664 11:17:58.710620 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9665 11:17:58.713805 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9666 11:17:58.720654 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9667 11:17:58.724235 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9668 11:17:58.727439 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9669 11:17:58.733936 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9670 11:17:58.737626 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9671 11:17:58.743927 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9672 11:17:58.747060 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9673 11:17:58.750692 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9674 11:17:58.757050 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9675 11:17:58.760621 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9676 11:17:58.767159 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9677 11:17:58.770737 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9678 11:17:58.773659 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9679 11:17:58.780425 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9680 11:17:58.784173 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9681 11:17:58.787087 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9682 11:17:58.794197 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9683 11:17:58.797268 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9684 11:17:58.803728 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9685 11:17:58.807316 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9686 11:17:58.810355 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9687 11:17:58.817687 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9688 11:17:58.820767 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9689 11:17:58.827304 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9690 11:17:58.830767 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9691 11:17:58.833979 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9692 11:17:58.840936 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9693 11:17:58.843798 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9694 11:17:58.850511 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9695 11:17:58.853935 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9696 11:17:58.856978 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9697 11:17:58.863658 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9698 11:17:58.866848 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9699 11:17:58.870438 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9700 11:17:58.876860 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9701 11:17:58.880521 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9702 11:17:58.887013 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9703 11:17:58.890115 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9704 11:17:58.894022 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9705 11:17:58.900166 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9706 11:17:58.903399 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9707 11:17:58.910132 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9708 11:17:58.913626 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9709 11:17:58.916793 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9710 11:17:58.923688 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9711 11:17:58.927016 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9712 11:17:58.933819 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9713 11:17:58.936861 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9714 11:17:58.939989 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9715 11:17:58.946747 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9716 11:17:58.949922 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9717 11:17:58.956773 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9718 11:17:58.960135 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9719 11:17:58.963117 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9720 11:17:58.970029 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9721 11:17:58.973347 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9722 11:17:58.980015 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9723 11:17:58.983516 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9724 11:17:58.989922 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9725 11:17:58.993869 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9726 11:17:58.996487 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9727 11:17:59.003622 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9728 11:17:59.007071 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9729 11:17:59.013426 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9730 11:17:59.017214 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9731 11:17:59.020121 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9732 11:17:59.026801 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9733 11:17:59.030234 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9734 11:17:59.036721 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9735 11:17:59.039824 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9736 11:17:59.043794 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9737 11:17:59.049970 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9738 11:17:59.053220 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9739 11:17:59.060082 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9740 11:17:59.063273 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9741 11:17:59.070188 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9742 11:17:59.072734 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9743 11:17:59.076408 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9744 11:17:59.083384 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9745 11:17:59.086353 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9746 11:17:59.093159 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9747 11:17:59.096719 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9748 11:17:59.099906 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9749 11:17:59.106457 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9750 11:17:59.110009 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9751 11:17:59.116385 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9752 11:17:59.119433 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9753 11:17:59.126250 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9754 11:17:59.129975 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9755 11:17:59.133396 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9756 11:17:59.136526 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9757 11:17:59.139538 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9758 11:17:59.146584 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9759 11:17:59.149936 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9760 11:17:59.153430 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9761 11:17:59.159851 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9762 11:17:59.162923 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9763 11:17:59.166636 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9764 11:17:59.172998 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9765 11:17:59.176078 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9766 11:17:59.182723 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9767 11:17:59.186177 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9768 11:17:59.189696 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9769 11:17:59.196402 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9770 11:17:59.199352 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9771 11:17:59.202823 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9772 11:17:59.209721 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9773 11:17:59.212827 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9774 11:17:59.216351 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9775 11:17:59.222539 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9776 11:17:59.226048 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9777 11:17:59.232363 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9778 11:17:59.236030 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9779 11:17:59.239151 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9780 11:17:59.245797 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9781 11:17:59.248961 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9782 11:17:59.255993 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9783 11:17:59.259119 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9784 11:17:59.262350 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9785 11:17:59.269009 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9786 11:17:59.272765 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9787 11:17:59.275421 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9788 11:17:59.282282 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9789 11:17:59.285505 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9790 11:17:59.288540 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9791 11:17:59.295567 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9792 11:17:59.298686 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9793 11:17:59.302201 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9794 11:17:59.308691 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9795 11:17:59.312032 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9796 11:17:59.315061 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9797 11:17:59.319083 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9798 11:17:59.322199 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9799 11:17:59.328343 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9800 11:17:59.332010 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9801 11:17:59.335046 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9802 11:17:59.341903 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9803 11:17:59.344814 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9804 11:17:59.348476 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9805 11:17:59.354707 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9806 11:17:59.358433 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9807 11:17:59.361551 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9808 11:17:59.367949 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9809 11:17:59.371192 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9810 11:17:59.374955 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9811 11:17:59.381669 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9812 11:17:59.384769 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9813 11:17:59.391666 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9814 11:17:59.394563 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9815 11:17:59.398150 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9816 11:17:59.404716 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9817 11:17:59.408263 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9818 11:17:59.414861 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9819 11:17:59.418315 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9820 11:17:59.424880 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9821 11:17:59.427992 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9822 11:17:59.431546 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9823 11:17:59.438185 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9824 11:17:59.441785 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9825 11:17:59.444948 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9826 11:17:59.451489 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9827 11:17:59.454415 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9828 11:17:59.461452 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9829 11:17:59.464542 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9830 11:17:59.467831 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9831 11:17:59.474844 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9832 11:17:59.477884 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9833 11:17:59.484721 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9834 11:17:59.487775 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9835 11:17:59.494886 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9836 11:17:59.498071 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9837 11:17:59.501149 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9838 11:17:59.507566 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9839 11:17:59.511593 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9840 11:17:59.517607 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9841 11:17:59.521240 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9842 11:17:59.524076 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9843 11:17:59.530882 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9844 11:17:59.534471 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9845 11:17:59.540575 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9846 11:17:59.544060 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9847 11:17:59.547626 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9848 11:17:59.554189 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9849 11:17:59.557083 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9850 11:17:59.563947 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9851 11:17:59.567147 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9852 11:17:59.574205 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9853 11:17:59.577370 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9854 11:17:59.580528 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9855 11:17:59.586870 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9856 11:17:59.589993 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9857 11:17:59.596912 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9858 11:17:59.600139 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9859 11:17:59.606932 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9860 11:17:59.609840 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9861 11:17:59.613429 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9862 11:17:59.620110 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9863 11:17:59.623212 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9864 11:17:59.630026 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9865 11:17:59.633651 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9866 11:17:59.636665 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9867 11:17:59.643647 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9868 11:17:59.646635 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9869 11:17:59.653440 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9870 11:17:59.656432 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9871 11:17:59.659821 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9872 11:17:59.666226 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9873 11:17:59.669622 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9874 11:17:59.676183 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9875 11:17:59.679761 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9876 11:17:59.686443 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9877 11:17:59.689616 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9878 11:17:59.693190 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9879 11:17:59.699518 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9880 11:17:59.703253 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9881 11:17:59.709718 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9882 11:17:59.712725 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9883 11:17:59.719958 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9884 11:17:59.722831 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9885 11:17:59.726379 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9886 11:17:59.732991 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9887 11:17:59.736471 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9888 11:17:59.742854 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9889 11:17:59.746433 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9890 11:17:59.753032 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9891 11:17:59.756411 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9892 11:17:59.759306 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9893 11:17:59.765919 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9894 11:17:59.769393 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9895 11:17:59.775490 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9896 11:17:59.778916 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9897 11:17:59.785825 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9898 11:17:59.788924 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9899 11:17:59.792850 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9900 11:17:59.798973 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9901 11:17:59.802786 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9902 11:17:59.808874 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9903 11:17:59.812524 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9904 11:17:59.818945 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9905 11:17:59.822388 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9906 11:17:59.828796 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9907 11:17:59.832289 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9908 11:17:59.835452 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9909 11:17:59.842209 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9910 11:17:59.845634 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9911 11:17:59.852024 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9912 11:17:59.855798 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9913 11:17:59.862345 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9914 11:17:59.865485 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9915 11:17:59.869176 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9916 11:17:59.875439 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9917 11:17:59.878602 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9918 11:17:59.885383 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9919 11:17:59.888367 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9920 11:17:59.895090 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9921 11:17:59.898236 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9922 11:17:59.905218 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9923 11:17:59.908819 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9924 11:17:59.912157 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9925 11:17:59.918975 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9926 11:17:59.921906 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9927 11:17:59.928138 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9928 11:17:59.931661 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9929 11:17:59.935008 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9930 11:17:59.941678 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9931 11:17:59.944623 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9932 11:17:59.951718 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9933 11:17:59.955054 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9934 11:17:59.961810 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9935 11:17:59.965044 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9936 11:17:59.971320 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9937 11:17:59.974992 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9938 11:17:59.981189 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9939 11:17:59.984775 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9940 11:17:59.991412 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9941 11:17:59.994427 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9942 11:18:00.001338 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9943 11:18:00.004538 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9944 11:18:00.011440 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9945 11:18:00.014764 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9946 11:18:00.021026 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9947 11:18:00.024948 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9948 11:18:00.031628 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9949 11:18:00.034539 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9950 11:18:00.041028 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9951 11:18:00.044445 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9952 11:18:00.051112 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9953 11:18:00.054703 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9954 11:18:00.061544 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9955 11:18:00.064352 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9956 11:18:00.071180 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9957 11:18:00.074397 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9958 11:18:00.081215 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9959 11:18:00.084456 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9960 11:18:00.084772 INFO: [APUAPC] vio 0
9961 11:18:00.092077 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9962 11:18:00.095386 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9963 11:18:00.098483 INFO: [APUAPC] D0_APC_0: 0x400510
9964 11:18:00.102197 INFO: [APUAPC] D0_APC_1: 0x0
9965 11:18:00.105421 INFO: [APUAPC] D0_APC_2: 0x1540
9966 11:18:00.108995 INFO: [APUAPC] D0_APC_3: 0x0
9967 11:18:00.112280 INFO: [APUAPC] D1_APC_0: 0xffffffff
9968 11:18:00.115652 INFO: [APUAPC] D1_APC_1: 0xffffffff
9969 11:18:00.118987 INFO: [APUAPC] D1_APC_2: 0x3fffff
9970 11:18:00.122106 INFO: [APUAPC] D1_APC_3: 0x0
9971 11:18:00.125915 INFO: [APUAPC] D2_APC_0: 0xffffffff
9972 11:18:00.128667 INFO: [APUAPC] D2_APC_1: 0xffffffff
9973 11:18:00.132186 INFO: [APUAPC] D2_APC_2: 0x3fffff
9974 11:18:00.135252 INFO: [APUAPC] D2_APC_3: 0x0
9975 11:18:00.139050 INFO: [APUAPC] D3_APC_0: 0xffffffff
9976 11:18:00.142099 INFO: [APUAPC] D3_APC_1: 0xffffffff
9977 11:18:00.145488 INFO: [APUAPC] D3_APC_2: 0x3fffff
9978 11:18:00.146055 INFO: [APUAPC] D3_APC_3: 0x0
9979 11:18:00.152254 INFO: [APUAPC] D4_APC_0: 0xffffffff
9980 11:18:00.155318 INFO: [APUAPC] D4_APC_1: 0xffffffff
9981 11:18:00.158304 INFO: [APUAPC] D4_APC_2: 0x3fffff
9982 11:18:00.158754 INFO: [APUAPC] D4_APC_3: 0x0
9983 11:18:00.162114 INFO: [APUAPC] D5_APC_0: 0xffffffff
9984 11:18:00.165333 INFO: [APUAPC] D5_APC_1: 0xffffffff
9985 11:18:00.168471 INFO: [APUAPC] D5_APC_2: 0x3fffff
9986 11:18:00.172033 INFO: [APUAPC] D5_APC_3: 0x0
9987 11:18:00.174967 INFO: [APUAPC] D6_APC_0: 0xffffffff
9988 11:18:00.178692 INFO: [APUAPC] D6_APC_1: 0xffffffff
9989 11:18:00.181637 INFO: [APUAPC] D6_APC_2: 0x3fffff
9990 11:18:00.184956 INFO: [APUAPC] D6_APC_3: 0x0
9991 11:18:00.188192 INFO: [APUAPC] D7_APC_0: 0xffffffff
9992 11:18:00.192062 INFO: [APUAPC] D7_APC_1: 0xffffffff
9993 11:18:00.195054 INFO: [APUAPC] D7_APC_2: 0x3fffff
9994 11:18:00.198559 INFO: [APUAPC] D7_APC_3: 0x0
9995 11:18:00.201701 INFO: [APUAPC] D8_APC_0: 0xffffffff
9996 11:18:00.205160 INFO: [APUAPC] D8_APC_1: 0xffffffff
9997 11:18:00.208243 INFO: [APUAPC] D8_APC_2: 0x3fffff
9998 11:18:00.211797 INFO: [APUAPC] D8_APC_3: 0x0
9999 11:18:00.214847 INFO: [APUAPC] D9_APC_0: 0xffffffff
10000 11:18:00.218434 INFO: [APUAPC] D9_APC_1: 0xffffffff
10001 11:18:00.221504 INFO: [APUAPC] D9_APC_2: 0x3fffff
10002 11:18:00.224774 INFO: [APUAPC] D9_APC_3: 0x0
10003 11:18:00.228579 INFO: [APUAPC] D10_APC_0: 0xffffffff
10004 11:18:00.231603 INFO: [APUAPC] D10_APC_1: 0xffffffff
10005 11:18:00.234902 INFO: [APUAPC] D10_APC_2: 0x3fffff
10006 11:18:00.237995 INFO: [APUAPC] D10_APC_3: 0x0
10007 11:18:00.241896 INFO: [APUAPC] D11_APC_0: 0xffffffff
10008 11:18:00.245126 INFO: [APUAPC] D11_APC_1: 0xffffffff
10009 11:18:00.248398 INFO: [APUAPC] D11_APC_2: 0x3fffff
10010 11:18:00.251452 INFO: [APUAPC] D11_APC_3: 0x0
10011 11:18:00.255033 INFO: [APUAPC] D12_APC_0: 0xffffffff
10012 11:18:00.257997 INFO: [APUAPC] D12_APC_1: 0xffffffff
10013 11:18:00.261594 INFO: [APUAPC] D12_APC_2: 0x3fffff
10014 11:18:00.264553 INFO: [APUAPC] D12_APC_3: 0x0
10015 11:18:00.268684 INFO: [APUAPC] D13_APC_0: 0xffffffff
10016 11:18:00.271230 INFO: [APUAPC] D13_APC_1: 0xffffffff
10017 11:18:00.274829 INFO: [APUAPC] D13_APC_2: 0x3fffff
10018 11:18:00.278367 INFO: [APUAPC] D13_APC_3: 0x0
10019 11:18:00.281332 INFO: [APUAPC] D14_APC_0: 0xffffffff
10020 11:18:00.284621 INFO: [APUAPC] D14_APC_1: 0xffffffff
10021 11:18:00.287959 INFO: [APUAPC] D14_APC_2: 0x3fffff
10022 11:18:00.291687 INFO: [APUAPC] D14_APC_3: 0x0
10023 11:18:00.294832 INFO: [APUAPC] D15_APC_0: 0xffffffff
10024 11:18:00.297922 INFO: [APUAPC] D15_APC_1: 0xffffffff
10025 11:18:00.301160 INFO: [APUAPC] D15_APC_2: 0x3fffff
10026 11:18:00.304756 INFO: [APUAPC] D15_APC_3: 0x0
10027 11:18:00.308322 INFO: [APUAPC] APC_CON: 0x4
10028 11:18:00.311435 INFO: [NOCDAPC] D0_APC_0: 0x0
10029 11:18:00.314397 INFO: [NOCDAPC] D0_APC_1: 0x0
10030 11:18:00.318023 INFO: [NOCDAPC] D1_APC_0: 0x0
10031 11:18:00.321541 INFO: [NOCDAPC] D1_APC_1: 0xfff
10032 11:18:00.321968 INFO: [NOCDAPC] D2_APC_0: 0x0
10033 11:18:00.324720 INFO: [NOCDAPC] D2_APC_1: 0xfff
10034 11:18:00.327806 INFO: [NOCDAPC] D3_APC_0: 0x0
10035 11:18:00.331485 INFO: [NOCDAPC] D3_APC_1: 0xfff
10036 11:18:00.334740 INFO: [NOCDAPC] D4_APC_0: 0x0
10037 11:18:00.337809 INFO: [NOCDAPC] D4_APC_1: 0xfff
10038 11:18:00.341512 INFO: [NOCDAPC] D5_APC_0: 0x0
10039 11:18:00.344884 INFO: [NOCDAPC] D5_APC_1: 0xfff
10040 11:18:00.348054 INFO: [NOCDAPC] D6_APC_0: 0x0
10041 11:18:00.351810 INFO: [NOCDAPC] D6_APC_1: 0xfff
10042 11:18:00.352341 INFO: [NOCDAPC] D7_APC_0: 0x0
10043 11:18:00.355028 INFO: [NOCDAPC] D7_APC_1: 0xfff
10044 11:18:00.358200 INFO: [NOCDAPC] D8_APC_0: 0x0
10045 11:18:00.361456 INFO: [NOCDAPC] D8_APC_1: 0xfff
10046 11:18:00.364435 INFO: [NOCDAPC] D9_APC_0: 0x0
10047 11:18:00.368060 INFO: [NOCDAPC] D9_APC_1: 0xfff
10048 11:18:00.371468 INFO: [NOCDAPC] D10_APC_0: 0x0
10049 11:18:00.374581 INFO: [NOCDAPC] D10_APC_1: 0xfff
10050 11:18:00.378190 INFO: [NOCDAPC] D11_APC_0: 0x0
10051 11:18:00.381080 INFO: [NOCDAPC] D11_APC_1: 0xfff
10052 11:18:00.384420 INFO: [NOCDAPC] D12_APC_0: 0x0
10053 11:18:00.387548 INFO: [NOCDAPC] D12_APC_1: 0xfff
10054 11:18:00.391089 INFO: [NOCDAPC] D13_APC_0: 0x0
10055 11:18:00.391555 INFO: [NOCDAPC] D13_APC_1: 0xfff
10056 11:18:00.394617 INFO: [NOCDAPC] D14_APC_0: 0x0
10057 11:18:00.397652 INFO: [NOCDAPC] D14_APC_1: 0xfff
10058 11:18:00.401383 INFO: [NOCDAPC] D15_APC_0: 0x0
10059 11:18:00.404620 INFO: [NOCDAPC] D15_APC_1: 0xfff
10060 11:18:00.408086 INFO: [NOCDAPC] APC_CON: 0x4
10061 11:18:00.411075 INFO: [APUAPC] set_apusys_apc done
10062 11:18:00.414348 INFO: [DEVAPC] devapc_init done
10063 11:18:00.418334 INFO: GICv3 without legacy support detected.
10064 11:18:00.421036 INFO: ARM GICv3 driver initialized in EL3
10065 11:18:00.427648 INFO: Maximum SPI INTID supported: 639
10066 11:18:00.431248 INFO: BL31: Initializing runtime services
10067 11:18:00.438033 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10068 11:18:00.438465 INFO: SPM: enable CPC mode
10069 11:18:00.444404 INFO: mcdi ready for mcusys-off-idle and system suspend
10070 11:18:00.447486 INFO: BL31: Preparing for EL3 exit to normal world
10071 11:18:00.450928 INFO: Entry point address = 0x80000000
10072 11:18:00.454498 INFO: SPSR = 0x8
10073 11:18:00.460358
10074 11:18:00.460878
10075 11:18:00.461253
10076 11:18:00.463549 Starting depthcharge on Spherion...
10077 11:18:00.464043
10078 11:18:00.464404 Wipe memory regions:
10079 11:18:00.464805
10080 11:18:00.467474 end: 2.2.3 depthcharge-start (duration 00:00:30) [common]
10081 11:18:00.468080 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10082 11:18:00.468568 Setting prompt string to ['asurada:']
10083 11:18:00.469197 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10084 11:18:00.469949 [0x00000040000000, 0x00000054600000)
10085 11:18:00.589300
10086 11:18:00.589794 [0x00000054660000, 0x00000080000000)
10087 11:18:00.849649
10088 11:18:00.850187 [0x000000821a7280, 0x000000ffe64000)
10089 11:18:01.594086
10090 11:18:01.594671 [0x00000100000000, 0x00000240000000)
10091 11:18:03.483810
10092 11:18:03.486950 Initializing XHCI USB controller at 0x11200000.
10093 11:18:04.525883
10094 11:18:04.529431 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10095 11:18:04.529520
10096 11:18:04.529586
10097 11:18:04.529645
10098 11:18:04.529926 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10100 11:18:04.630273 asurada: tftpboot 192.168.201.1 10591269/tftp-deploy-al9f63sa/kernel/image.itb 10591269/tftp-deploy-al9f63sa/kernel/cmdline
10101 11:18:04.630408 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10102 11:18:04.630490 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10103 11:18:04.634666 tftpboot 192.168.201.1 10591269/tftp-deploy-al9f63sa/kernel/image.ittp-deploy-al9f63sa/kernel/cmdline
10104 11:18:04.634787
10105 11:18:04.634852 Waiting for link
10106 11:18:04.795154
10107 11:18:04.795288 R8152: Initializing
10108 11:18:04.795397
10109 11:18:04.798334 Version 9 (ocp_data = 6010)
10110 11:18:04.798417
10111 11:18:04.801398 R8152: Done initializing
10112 11:18:04.801483
10113 11:18:04.801572 Adding net device
10114 11:18:06.747469
10115 11:18:06.747616 done.
10116 11:18:06.747685
10117 11:18:06.747747 MAC: 00:e0:4c:78:7a:aa
10118 11:18:06.747808
10119 11:18:06.751146 Sending DHCP discover... done.
10120 11:18:06.751216
10121 11:18:06.754513 Waiting for reply... done.
10122 11:18:06.754588
10123 11:18:06.757636 Sending DHCP request... done.
10124 11:18:06.757719
10125 11:18:06.763335 Waiting for reply... done.
10126 11:18:06.763451
10127 11:18:06.763516 My ip is 192.168.201.12
10128 11:18:06.763576
10129 11:18:06.766385 The DHCP server ip is 192.168.201.1
10130 11:18:06.766467
10131 11:18:06.773078 TFTP server IP predefined by user: 192.168.201.1
10132 11:18:06.773161
10133 11:18:06.779452 Bootfile predefined by user: 10591269/tftp-deploy-al9f63sa/kernel/image.itb
10134 11:18:06.779536
10135 11:18:06.783265 Sending tftp read request... done.
10136 11:18:06.783397
10137 11:18:06.786370 Waiting for the transfer...
10138 11:18:06.786452
10139 11:18:07.043867 00000000 ################################################################
10140 11:18:07.044001
10141 11:18:07.319594 00080000 ################################################################
10142 11:18:07.319736
10143 11:18:07.597971 00100000 ################################################################
10144 11:18:07.598112
10145 11:18:07.862632 00180000 ################################################################
10146 11:18:07.862769
10147 11:18:08.130401 00200000 ################################################################
10148 11:18:08.130535
10149 11:18:08.384481 00280000 ################################################################
10150 11:18:08.384614
10151 11:18:08.639303 00300000 ################################################################
10152 11:18:08.639458
10153 11:18:08.895157 00380000 ################################################################
10154 11:18:08.895295
10155 11:18:09.148707 00400000 ################################################################
10156 11:18:09.148841
10157 11:18:09.401628 00480000 ################################################################
10158 11:18:09.401764
10159 11:18:09.652821 00500000 ################################################################
10160 11:18:09.652951
10161 11:18:09.905961 00580000 ################################################################
10162 11:18:09.906126
10163 11:18:10.161755 00600000 ################################################################
10164 11:18:10.161889
10165 11:18:10.423989 00680000 ################################################################
10166 11:18:10.424165
10167 11:18:10.675081 00700000 ################################################################
10168 11:18:10.675228
10169 11:18:10.928113 00780000 ################################################################
10170 11:18:10.928285
10171 11:18:11.191654 00800000 ################################################################
10172 11:18:11.191805
10173 11:18:11.448387 00880000 ################################################################
10174 11:18:11.448522
10175 11:18:11.700713 00900000 ################################################################
10176 11:18:11.700863
10177 11:18:11.952696 00980000 ################################################################
10178 11:18:11.952844
10179 11:18:12.209896 00a00000 ################################################################
10180 11:18:12.210064
10181 11:18:12.475820 00a80000 ################################################################
10182 11:18:12.475995
10183 11:18:12.726725 00b00000 ################################################################
10184 11:18:12.726871
10185 11:18:12.978749 00b80000 ################################################################
10186 11:18:12.978888
10187 11:18:13.233611 00c00000 ################################################################
10188 11:18:13.233748
10189 11:18:13.489995 00c80000 ################################################################
10190 11:18:13.490140
10191 11:18:13.745144 00d00000 ################################################################
10192 11:18:13.745293
10193 11:18:13.999362 00d80000 ################################################################
10194 11:18:13.999502
10195 11:18:14.258038 00e00000 ################################################################
10196 11:18:14.258179
10197 11:18:14.517518 00e80000 ################################################################
10198 11:18:14.517654
10199 11:18:14.780460 00f00000 ################################################################
10200 11:18:14.780598
10201 11:18:15.035233 00f80000 ################################################################
10202 11:18:15.035397
10203 11:18:15.289219 01000000 ################################################################
10204 11:18:15.289362
10205 11:18:15.534577 01080000 ################################################################
10206 11:18:15.534713
10207 11:18:15.795203 01100000 ################################################################
10208 11:18:15.795398
10209 11:18:16.053788 01180000 ################################################################
10210 11:18:16.053949
10211 11:18:16.319278 01200000 ################################################################
10212 11:18:16.319422
10213 11:18:16.589935 01280000 ################################################################
10214 11:18:16.590107
10215 11:18:16.844025 01300000 ################################################################
10216 11:18:16.844201
10217 11:18:17.125705 01380000 ################################################################
10218 11:18:17.125851
10219 11:18:17.419860 01400000 ################################################################
10220 11:18:17.420005
10221 11:18:17.712056 01480000 ################################################################
10222 11:18:17.712203
10223 11:18:17.983954 01500000 ################################################################
10224 11:18:17.984082
10225 11:18:18.268931 01580000 ################################################################
10226 11:18:18.269064
10227 11:18:18.531595 01600000 ################################################################
10228 11:18:18.531730
10229 11:18:18.793931 01680000 ################################################################
10230 11:18:18.794061
10231 11:18:19.059588 01700000 ################################################################
10232 11:18:19.059721
10233 11:18:19.341376 01780000 ################################################################
10234 11:18:19.341509
10235 11:18:19.617271 01800000 ################################################################
10236 11:18:19.617401
10237 11:18:19.908466 01880000 ################################################################
10238 11:18:19.908599
10239 11:18:20.199170 01900000 ################################################################
10240 11:18:20.199304
10241 11:18:20.489218 01980000 ################################################################
10242 11:18:20.489354
10243 11:18:20.738828 01a00000 ############################################################### done.
10244 11:18:20.738984
10245 11:18:20.742027 The bootfile was 27775150 bytes long.
10246 11:18:20.742111
10247 11:18:20.745748 Sending tftp read request... done.
10248 11:18:20.745838
10249 11:18:20.748996 Waiting for the transfer...
10250 11:18:20.749090
10251 11:18:20.749165 00000000 # done.
10252 11:18:20.749241
10253 11:18:20.758954 Command line loaded dynamically from TFTP file: 10591269/tftp-deploy-al9f63sa/kernel/cmdline
10254 11:18:20.759598
10255 11:18:20.778771 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10591269/extract-nfsrootfs-e40z_w25,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10256 11:18:20.779295
10257 11:18:20.779874 Loading FIT.
10258 11:18:20.780222
10259 11:18:20.782599 Image ramdisk-1 has 17640170 bytes.
10260 11:18:20.783026
10261 11:18:20.785510 Image fdt-1 has 46924 bytes.
10262 11:18:20.785977
10263 11:18:20.789366 Image kernel-1 has 10086024 bytes.
10264 11:18:20.789791
10265 11:18:20.799072 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10266 11:18:20.799545
10267 11:18:20.815653 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10268 11:18:20.816181
10269 11:18:20.819010 Choosing best match conf-1 for compat google,spherion-rev2.
10270 11:18:20.824619
10271 11:18:20.829707 Connected to device vid:did:rid of 1ae0:0028:00
10272 11:18:20.837504
10273 11:18:20.840697 tpm_get_response: command 0x17b, return code 0x0
10274 11:18:20.841124
10275 11:18:20.844104 ec_init: CrosEC protocol v3 supported (256, 248)
10276 11:18:20.848452
10277 11:18:20.852343 tpm_cleanup: add release locality here.
10278 11:18:20.852905
10279 11:18:20.853276 Shutting down all USB controllers.
10280 11:18:20.855784
10281 11:18:20.856320 Removing current net device
10282 11:18:20.856697
10283 11:18:20.861870 Exiting depthcharge with code 4 at timestamp: 49683312
10284 11:18:20.862409
10285 11:18:20.865246 LZMA decompressing kernel-1 to 0x821a6718
10286 11:18:20.865716
10287 11:18:20.868747 LZMA decompressing kernel-1 to 0x40000000
10288 11:18:22.135048
10289 11:18:22.135189 jumping to kernel
10290 11:18:22.135596 end: 2.2.4 bootloader-commands (duration 00:00:22) [common]
10291 11:18:22.135700 start: 2.2.5 auto-login-action (timeout 00:04:04) [common]
10292 11:18:22.135778 Setting prompt string to ['Linux version [0-9]']
10293 11:18:22.135848 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10294 11:18:22.135917 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10295 11:18:22.216713
10296 11:18:22.219775 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10297 11:18:22.223143 start: 2.2.5.1 login-action (timeout 00:04:03) [common]
10298 11:18:22.223236 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10299 11:18:22.223322 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10300 11:18:22.223457 Using line separator: #'\n'#
10301 11:18:22.223519 No login prompt set.
10302 11:18:22.223579 Parsing kernel messages
10303 11:18:22.223634 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10304 11:18:22.223758 [login-action] Waiting for messages, (timeout 00:04:03)
10305 11:18:22.242726 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1609115-arm64-gcc-10-defconfig-arm64-chromebook-dplkv) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 10:57:14 UTC 2023
10306 11:18:22.245987 [ 0.000000] random: crng init done
10307 11:18:22.249097 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10308 11:18:22.252904 [ 0.000000] efi: UEFI not found.
10309 11:18:22.262995 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10310 11:18:22.269242 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10311 11:18:22.279209 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10312 11:18:22.289482 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10313 11:18:22.296076 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10314 11:18:22.299695 [ 0.000000] printk: bootconsole [mtk8250] enabled
10315 11:18:22.308201 [ 0.000000] NUMA: No NUMA configuration found
10316 11:18:22.314947 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10317 11:18:22.321781 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10318 11:18:22.322349 [ 0.000000] Zone ranges:
10319 11:18:22.327939 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10320 11:18:22.331776 [ 0.000000] DMA32 empty
10321 11:18:22.337896 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10322 11:18:22.342038 [ 0.000000] Movable zone start for each node
10323 11:18:22.344999 [ 0.000000] Early memory node ranges
10324 11:18:22.351968 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10325 11:18:22.358234 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10326 11:18:22.365035 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10327 11:18:22.371392 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10328 11:18:22.377977 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10329 11:18:22.384692 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10330 11:18:22.440683 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10331 11:18:22.447656 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10332 11:18:22.454267 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10333 11:18:22.457421 [ 0.000000] psci: probing for conduit method from DT.
10334 11:18:22.464082 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10335 11:18:22.467966 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10336 11:18:22.474194 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10337 11:18:22.477649 [ 0.000000] psci: SMC Calling Convention v1.2
10338 11:18:22.484669 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10339 11:18:22.487717 [ 0.000000] Detected VIPT I-cache on CPU0
10340 11:18:22.494572 [ 0.000000] CPU features: detected: GIC system register CPU interface
10341 11:18:22.500758 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10342 11:18:22.507672 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10343 11:18:22.513827 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10344 11:18:22.520489 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10345 11:18:22.527262 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10346 11:18:22.533918 [ 0.000000] alternatives: applying boot alternatives
10347 11:18:22.537449 [ 0.000000] Fallback order for Node 0: 0
10348 11:18:22.544059 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10349 11:18:22.547305 [ 0.000000] Policy zone: Normal
10350 11:18:22.570251 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/10591269/extract-nfsrootfs-e40z_w25,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10351 11:18:22.580603 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10352 11:18:22.591545 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10353 11:18:22.601607 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10354 11:18:22.604875 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10355 11:18:22.611266 <6>[ 0.000000] software IO TLB: area num 8.
10356 11:18:22.667012 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10357 11:18:22.816050 <6>[ 0.000000] Memory: 7955720K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 397048K reserved, 32768K cma-reserved)
10358 11:18:22.822861 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10359 11:18:22.829701 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10360 11:18:22.832921 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10361 11:18:22.839787 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10362 11:18:22.846037 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10363 11:18:22.849848 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10364 11:18:22.859444 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10365 11:18:22.865688 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10366 11:18:22.869680 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10367 11:18:22.877690 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10368 11:18:22.880867 <6>[ 0.000000] GICv3: 608 SPIs implemented
10369 11:18:22.887626 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10370 11:18:22.890710 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10371 11:18:22.893579 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10372 11:18:22.903562 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10373 11:18:22.913930 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10374 11:18:22.927037 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10375 11:18:22.933447 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10376 11:18:22.942757 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10377 11:18:22.955488 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10378 11:18:22.962302 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10379 11:18:22.969089 <6>[ 0.009220] Console: colour dummy device 80x25
10380 11:18:22.979221 <6>[ 0.013976] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10381 11:18:22.985730 <6>[ 0.024483] pid_max: default: 32768 minimum: 301
10382 11:18:22.988687 <6>[ 0.029386] LSM: Security Framework initializing
10383 11:18:22.995723 <6>[ 0.034325] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10384 11:18:23.005556 <6>[ 0.042139] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10385 11:18:23.015415 <6>[ 0.051564] cblist_init_generic: Setting adjustable number of callback queues.
10386 11:18:23.018902 <6>[ 0.059062] cblist_init_generic: Setting shift to 3 and lim to 1.
10387 11:18:23.025350 <6>[ 0.065401] cblist_init_generic: Setting shift to 3 and lim to 1.
10388 11:18:23.032147 <6>[ 0.071809] rcu: Hierarchical SRCU implementation.
10389 11:18:23.038544 <6>[ 0.076855] rcu: Max phase no-delay instances is 1000.
10390 11:18:23.042213 <6>[ 0.083912] EFI services will not be available.
10391 11:18:23.048628 <6>[ 0.088870] smp: Bringing up secondary CPUs ...
10392 11:18:23.055978 <6>[ 0.093923] Detected VIPT I-cache on CPU1
10393 11:18:23.062452 <6>[ 0.093998] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10394 11:18:23.069141 <6>[ 0.094029] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10395 11:18:23.072938 <6>[ 0.094368] Detected VIPT I-cache on CPU2
10396 11:18:23.082662 <6>[ 0.094420] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10397 11:18:23.088934 <6>[ 0.094436] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10398 11:18:23.092696 <6>[ 0.094695] Detected VIPT I-cache on CPU3
10399 11:18:23.099095 <6>[ 0.094741] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10400 11:18:23.106020 <6>[ 0.094755] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10401 11:18:23.108897 <6>[ 0.095062] CPU features: detected: Spectre-v4
10402 11:18:23.115607 <6>[ 0.095068] CPU features: detected: Spectre-BHB
10403 11:18:23.118764 <6>[ 0.095074] Detected PIPT I-cache on CPU4
10404 11:18:23.125587 <6>[ 0.095132] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10405 11:18:23.132722 <6>[ 0.095149] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10406 11:18:23.139616 <6>[ 0.095446] Detected PIPT I-cache on CPU5
10407 11:18:23.145736 <6>[ 0.095510] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10408 11:18:23.152565 <6>[ 0.095526] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10409 11:18:23.155553 <6>[ 0.095811] Detected PIPT I-cache on CPU6
10410 11:18:23.162116 <6>[ 0.095877] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10411 11:18:23.168775 <6>[ 0.095894] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10412 11:18:23.175588 <6>[ 0.096189] Detected PIPT I-cache on CPU7
10413 11:18:23.182198 <6>[ 0.096255] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10414 11:18:23.188810 <6>[ 0.096272] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10415 11:18:23.191860 <6>[ 0.096320] smp: Brought up 1 node, 8 CPUs
10416 11:18:23.198758 <6>[ 0.237598] SMP: Total of 8 processors activated.
10417 11:18:23.201843 <6>[ 0.242540] CPU features: detected: 32-bit EL0 Support
10418 11:18:23.211630 <6>[ 0.247903] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10419 11:18:23.218477 <6>[ 0.256703] CPU features: detected: Common not Private translations
10420 11:18:23.221536 <6>[ 0.263178] CPU features: detected: CRC32 instructions
10421 11:18:23.228447 <6>[ 0.268530] CPU features: detected: RCpc load-acquire (LDAPR)
10422 11:18:23.235507 <6>[ 0.274489] CPU features: detected: LSE atomic instructions
10423 11:18:23.241472 <6>[ 0.280306] CPU features: detected: Privileged Access Never
10424 11:18:23.245278 <6>[ 0.286086] CPU features: detected: RAS Extension Support
10425 11:18:23.255293 <6>[ 0.291729] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10426 11:18:23.258498 <6>[ 0.298982] CPU: All CPU(s) started at EL2
10427 11:18:23.264740 <6>[ 0.303325] alternatives: applying system-wide alternatives
10428 11:18:23.274146 <6>[ 0.314028] devtmpfs: initialized
10429 11:18:23.289181 <6>[ 0.322837] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10430 11:18:23.296012 <6>[ 0.332797] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10431 11:18:23.299292 <6>[ 0.340487] pinctrl core: initialized pinctrl subsystem
10432 11:18:23.307304 <6>[ 0.347152] DMI not present or invalid.
10433 11:18:23.313392 <6>[ 0.351554] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10434 11:18:23.320576 <6>[ 0.358446] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10435 11:18:23.330379 <6>[ 0.366026] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10436 11:18:23.336954 <6>[ 0.374240] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10437 11:18:23.343966 <6>[ 0.382480] audit: initializing netlink subsys (disabled)
10438 11:18:23.350234 <5>[ 0.388173] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10439 11:18:23.356791 <6>[ 0.388875] thermal_sys: Registered thermal governor 'step_wise'
10440 11:18:23.363891 <6>[ 0.396136] thermal_sys: Registered thermal governor 'power_allocator'
10441 11:18:23.367198 <6>[ 0.402388] cpuidle: using governor menu
10442 11:18:23.373798 <6>[ 0.413342] NET: Registered PF_QIPCRTR protocol family
10443 11:18:23.380278 <6>[ 0.418829] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10444 11:18:23.387238 <6>[ 0.425929] ASID allocator initialised with 32768 entries
10445 11:18:23.390261 <6>[ 0.432495] Serial: AMBA PL011 UART driver
10446 11:18:23.400810 <4>[ 0.441186] Trying to register duplicate clock ID: 134
10447 11:18:23.454648 <6>[ 0.498489] KASLR enabled
10448 11:18:23.469053 <6>[ 0.506234] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10449 11:18:23.475347 <6>[ 0.513246] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10450 11:18:23.482148 <6>[ 0.519737] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10451 11:18:23.488620 <6>[ 0.526743] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10452 11:18:23.495482 <6>[ 0.533231] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10453 11:18:23.502081 <6>[ 0.540238] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10454 11:18:23.508900 <6>[ 0.546725] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10455 11:18:23.515286 <6>[ 0.553731] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10456 11:18:23.518348 <6>[ 0.561225] ACPI: Interpreter disabled.
10457 11:18:23.526708 <6>[ 0.567593] iommu: Default domain type: Translated
10458 11:18:23.533674 <6>[ 0.572701] iommu: DMA domain TLB invalidation policy: strict mode
10459 11:18:23.536983 <5>[ 0.579350] SCSI subsystem initialized
10460 11:18:23.543750 <6>[ 0.583513] usbcore: registered new interface driver usbfs
10461 11:18:23.550148 <6>[ 0.589247] usbcore: registered new interface driver hub
10462 11:18:23.553258 <6>[ 0.594799] usbcore: registered new device driver usb
10463 11:18:23.560097 <6>[ 0.600873] pps_core: LinuxPPS API ver. 1 registered
10464 11:18:23.570086 <6>[ 0.606067] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10465 11:18:23.573920 <6>[ 0.615410] PTP clock support registered
10466 11:18:23.577085 <6>[ 0.619649] EDAC MC: Ver: 3.0.0
10467 11:18:23.584755 <6>[ 0.624780] FPGA manager framework
10468 11:18:23.587314 <6>[ 0.628460] Advanced Linux Sound Architecture Driver Initialized.
10469 11:18:23.591109 <6>[ 0.635224] vgaarb: loaded
10470 11:18:23.597893 <6>[ 0.638404] clocksource: Switched to clocksource arch_sys_counter
10471 11:18:23.604678 <5>[ 0.644838] VFS: Disk quotas dquot_6.6.0
10472 11:18:23.611363 <6>[ 0.649021] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10473 11:18:23.614286 <6>[ 0.656205] pnp: PnP ACPI: disabled
10474 11:18:23.622443 <6>[ 0.662933] NET: Registered PF_INET protocol family
10475 11:18:23.632122 <6>[ 0.668526] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10476 11:18:23.643767 <6>[ 0.680839] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10477 11:18:23.653634 <6>[ 0.689655] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10478 11:18:23.660395 <6>[ 0.697622] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10479 11:18:23.666557 <6>[ 0.706318] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10480 11:18:23.679018 <6>[ 0.716068] TCP: Hash tables configured (established 65536 bind 65536)
10481 11:18:23.685194 <6>[ 0.722928] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10482 11:18:23.691896 <6>[ 0.730126] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10483 11:18:23.698691 <6>[ 0.737823] NET: Registered PF_UNIX/PF_LOCAL protocol family
10484 11:18:23.705383 <6>[ 0.743974] RPC: Registered named UNIX socket transport module.
10485 11:18:23.708352 <6>[ 0.750128] RPC: Registered udp transport module.
10486 11:18:23.715349 <6>[ 0.755063] RPC: Registered tcp transport module.
10487 11:18:23.721833 <6>[ 0.759995] RPC: Registered tcp NFSv4.1 backchannel transport module.
10488 11:18:23.725439 <6>[ 0.766662] PCI: CLS 0 bytes, default 64
10489 11:18:23.728364 <6>[ 0.770974] Unpacking initramfs...
10490 11:18:23.738262 <6>[ 0.775028] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10491 11:18:23.744847 <6>[ 0.783668] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10492 11:18:23.751667 <6>[ 0.792486] kvm [1]: IPA Size Limit: 40 bits
10493 11:18:23.754899 <6>[ 0.797010] kvm [1]: GICv3: no GICV resource entry
10494 11:18:23.761655 <6>[ 0.802031] kvm [1]: disabling GICv2 emulation
10495 11:18:23.768662 <6>[ 0.806718] kvm [1]: GIC system register CPU interface enabled
10496 11:18:23.771681 <6>[ 0.812876] kvm [1]: vgic interrupt IRQ18
10497 11:18:23.778605 <6>[ 0.817232] kvm [1]: VHE mode initialized successfully
10498 11:18:23.781739 <5>[ 0.823600] Initialise system trusted keyrings
10499 11:18:23.788035 <6>[ 0.828402] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10500 11:18:23.797810 <6>[ 0.838365] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10501 11:18:23.804099 <5>[ 0.844730] NFS: Registering the id_resolver key type
10502 11:18:23.807831 <5>[ 0.850026] Key type id_resolver registered
10503 11:18:23.814013 <5>[ 0.854441] Key type id_legacy registered
10504 11:18:23.820756 <6>[ 0.858726] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10505 11:18:23.827596 <6>[ 0.865650] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10506 11:18:23.834234 <6>[ 0.873354] 9p: Installing v9fs 9p2000 file system support
10507 11:18:23.871238 <5>[ 0.911703] Key type asymmetric registered
10508 11:18:23.874423 <5>[ 0.916035] Asymmetric key parser 'x509' registered
10509 11:18:23.884496 <6>[ 0.921180] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10510 11:18:23.887548 <6>[ 0.928793] io scheduler mq-deadline registered
10511 11:18:23.890679 <6>[ 0.933554] io scheduler kyber registered
10512 11:18:23.909708 <6>[ 0.950459] EINJ: ACPI disabled.
10513 11:18:23.942072 <4>[ 0.976016] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10514 11:18:23.951675 <4>[ 0.986673] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10515 11:18:23.966741 <6>[ 1.007536] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10516 11:18:23.974561 <6>[ 1.015503] printk: console [ttyS0] disabled
10517 11:18:24.002658 <6>[ 1.040145] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10518 11:18:24.009656 <6>[ 1.049620] printk: console [ttyS0] enabled
10519 11:18:24.012881 <6>[ 1.049620] printk: console [ttyS0] enabled
10520 11:18:24.019443 <6>[ 1.058517] printk: bootconsole [mtk8250] disabled
10521 11:18:24.022864 <6>[ 1.058517] printk: bootconsole [mtk8250] disabled
10522 11:18:24.029486 <6>[ 1.069728] SuperH (H)SCI(F) driver initialized
10523 11:18:24.032723 <6>[ 1.074985] msm_serial: driver initialized
10524 11:18:24.046394 <6>[ 1.083891] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10525 11:18:24.056415 <6>[ 1.092438] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10526 11:18:24.063066 <6>[ 1.100979] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10527 11:18:24.072971 <6>[ 1.109607] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10528 11:18:24.079650 <6>[ 1.118313] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10529 11:18:24.089598 <6>[ 1.127035] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10530 11:18:24.099233 <6>[ 1.135577] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10531 11:18:24.106079 <6>[ 1.144378] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10532 11:18:24.116350 <6>[ 1.152920] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10533 11:18:24.127928 <6>[ 1.168482] loop: module loaded
10534 11:18:24.134375 <6>[ 1.174548] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10535 11:18:24.157533 <4>[ 1.198067] mtk-pmic-keys: Failed to locate of_node [id: -1]
10536 11:18:24.164567 <6>[ 1.205083] megasas: 07.719.03.00-rc1
10537 11:18:24.173757 <6>[ 1.214789] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10538 11:18:24.181413 <6>[ 1.221815] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10539 11:18:24.198063 <6>[ 1.238702] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10540 11:18:24.255229 <6>[ 1.289250] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.153/cr50_v3.94_pp.113-620c9
10541 11:18:24.505533 <6>[ 1.546316] Freeing initrd memory: 17220K
10542 11:18:24.516428 <6>[ 1.556683] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10543 11:18:24.526769 <6>[ 1.567616] tun: Universal TUN/TAP device driver, 1.6
10544 11:18:24.530564 <6>[ 1.573668] thunder_xcv, ver 1.0
10545 11:18:24.533747 <6>[ 1.577172] thunder_bgx, ver 1.0
10546 11:18:24.536945 <6>[ 1.580666] nicpf, ver 1.0
10547 11:18:24.547153 <6>[ 1.584658] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10548 11:18:24.550658 <6>[ 1.592132] hns3: Copyright (c) 2017 Huawei Corporation.
10549 11:18:24.557460 <6>[ 1.597718] hclge is initializing
10550 11:18:24.560505 <6>[ 1.601301] e1000: Intel(R) PRO/1000 Network Driver
10551 11:18:24.567530 <6>[ 1.606430] e1000: Copyright (c) 1999-2006 Intel Corporation.
10552 11:18:24.570359 <6>[ 1.612443] e1000e: Intel(R) PRO/1000 Network Driver
10553 11:18:24.577197 <6>[ 1.617658] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10554 11:18:24.583787 <6>[ 1.623847] igb: Intel(R) Gigabit Ethernet Network Driver
10555 11:18:24.590212 <6>[ 1.629496] igb: Copyright (c) 2007-2014 Intel Corporation.
10556 11:18:24.597509 <6>[ 1.635332] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10557 11:18:24.603565 <6>[ 1.641850] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10558 11:18:24.607273 <6>[ 1.648306] sky2: driver version 1.30
10559 11:18:24.613539 <6>[ 1.653288] VFIO - User Level meta-driver version: 0.3
10560 11:18:24.620581 <6>[ 1.661426] usbcore: registered new interface driver usb-storage
10561 11:18:24.627540 <6>[ 1.667871] usbcore: registered new device driver onboard-usb-hub
10562 11:18:24.636196 <6>[ 1.676906] mt6397-rtc mt6359-rtc: registered as rtc0
10563 11:18:24.646263 <6>[ 1.682371] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-05T11:18:12 UTC (1685963892)
10564 11:18:24.649400 <6>[ 1.691923] i2c_dev: i2c /dev entries driver
10565 11:18:24.665786 <6>[ 1.703495] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10566 11:18:24.672773 <6>[ 1.713685] sdhci: Secure Digital Host Controller Interface driver
10567 11:18:24.679558 <6>[ 1.720124] sdhci: Copyright(c) Pierre Ossman
10568 11:18:24.686466 <6>[ 1.725514] Synopsys Designware Multimedia Card Interface Driver
10569 11:18:24.689551 <6>[ 1.732157] mmc0: CQHCI version 5.10
10570 11:18:24.696403 <6>[ 1.732658] sdhci-pltfm: SDHCI platform and OF driver helper
10571 11:18:24.703110 <6>[ 1.744088] ledtrig-cpu: registered to indicate activity on CPUs
10572 11:18:24.713651 <6>[ 1.751408] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10573 11:18:24.717291 <6>[ 1.758799] usbcore: registered new interface driver usbhid
10574 11:18:24.724351 <6>[ 1.764625] usbhid: USB HID core driver
10575 11:18:24.730480 <6>[ 1.768869] spi_master spi0: will run message pump with realtime priority
10576 11:18:24.779289 <6>[ 1.813484] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10577 11:18:24.797966 <6>[ 1.828483] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10578 11:18:24.801473 <6>[ 1.842097] mmc0: Command Queue Engine enabled
10579 11:18:24.808712 <6>[ 1.843342] cros-ec-spi spi0.0: Chrome EC device registered
10580 11:18:24.811710 <6>[ 1.846850] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10581 11:18:24.819436 <6>[ 1.859997] mmcblk0: mmc0:0001 DA4128 116 GiB
10582 11:18:24.831441 <6>[ 1.869121] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10583 11:18:24.838210 <6>[ 1.869394] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10584 11:18:24.845395 <6>[ 1.880535] NET: Registered PF_PACKET protocol family
10585 11:18:24.848518 <6>[ 1.885213] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10586 11:18:24.855511 <6>[ 1.889782] 9pnet: Installing 9P2000 support
10587 11:18:24.858750 <6>[ 1.895507] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10588 11:18:24.861649 <5>[ 1.899466] Key type dns_resolver registered
10589 11:18:24.868459 <6>[ 1.905165] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10590 11:18:24.874692 <6>[ 1.909714] registered taskstats version 1
10591 11:18:24.878482 <5>[ 1.920086] Loading compiled-in X.509 certificates
10592 11:18:24.912974 <4>[ 1.947177] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10593 11:18:24.922621 <4>[ 1.957878] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10594 11:18:24.933346 <3>[ 1.970790] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10595 11:18:24.945296 <6>[ 1.986170] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10596 11:18:24.952121 <6>[ 1.992923] xhci-mtk 11200000.usb: xHCI Host Controller
10597 11:18:24.958573 <6>[ 1.998421] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10598 11:18:24.969010 <6>[ 2.006273] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10599 11:18:24.975248 <6>[ 2.015700] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10600 11:18:24.982132 <6>[ 2.021877] xhci-mtk 11200000.usb: xHCI Host Controller
10601 11:18:24.988439 <6>[ 2.027375] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10602 11:18:24.995464 <6>[ 2.035033] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10603 11:18:25.002312 <6>[ 2.042967] hub 1-0:1.0: USB hub found
10604 11:18:25.005877 <6>[ 2.047000] hub 1-0:1.0: 1 port detected
10605 11:18:25.012453 <6>[ 2.051345] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10606 11:18:25.019458 <6>[ 2.060138] hub 2-0:1.0: USB hub found
10607 11:18:25.022393 <6>[ 2.064176] hub 2-0:1.0: 1 port detected
10608 11:18:25.030389 <6>[ 2.071323] mtk-msdc 11f70000.mmc: Got CD GPIO
10609 11:18:25.047520 <6>[ 2.084591] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10610 11:18:25.053692 <6>[ 2.092637] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10611 11:18:25.064031 <4>[ 2.100700] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10612 11:18:25.073665 <6>[ 2.110366] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10613 11:18:25.080403 <6>[ 2.118495] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10614 11:18:25.087282 <6>[ 2.126524] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10615 11:18:25.097382 <6>[ 2.134486] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10616 11:18:25.103674 <6>[ 2.142311] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10617 11:18:25.113665 <6>[ 2.150134] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10618 11:18:25.123791 <6>[ 2.160883] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10619 11:18:25.130528 <6>[ 2.169246] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10620 11:18:25.139978 <6>[ 2.177633] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10621 11:18:25.150263 <6>[ 2.185980] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10622 11:18:25.156662 <6>[ 2.194350] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10623 11:18:25.167048 <6>[ 2.202695] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10624 11:18:25.173508 <6>[ 2.211064] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10625 11:18:25.183261 <6>[ 2.219410] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10626 11:18:25.190078 <6>[ 2.227773] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10627 11:18:25.200282 <6>[ 2.236117] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10628 11:18:25.206630 <6>[ 2.244461] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10629 11:18:25.217164 <6>[ 2.252808] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10630 11:18:25.223319 <6>[ 2.261152] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10631 11:18:25.233349 <6>[ 2.269496] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10632 11:18:25.240072 <6>[ 2.277838] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10633 11:18:25.247076 <6>[ 2.286770] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10634 11:18:25.253436 <6>[ 2.294212] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10635 11:18:25.260631 <6>[ 2.301221] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10636 11:18:25.270784 <6>[ 2.308321] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10637 11:18:25.277523 <6>[ 2.315587] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10638 11:18:25.287126 <6>[ 2.322526] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10639 11:18:25.293840 <6>[ 2.331672] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10640 11:18:25.303847 <6>[ 2.340830] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10641 11:18:25.314171 <6>[ 2.350145] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10642 11:18:25.323388 <6>[ 2.359622] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10643 11:18:25.333420 <6>[ 2.369096] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10644 11:18:25.339946 <6>[ 2.378223] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10645 11:18:25.350215 <6>[ 2.387697] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10646 11:18:25.359970 <6>[ 2.396824] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10647 11:18:25.370297 <6>[ 2.406126] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10648 11:18:25.380050 <6>[ 2.416292] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10649 11:18:25.389989 <6>[ 2.427715] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10650 11:18:25.396878 <6>[ 2.437666] Trying to probe devices needed for running init ...
10651 11:18:25.412953 <6>[ 2.450671] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10652 11:18:25.440018 <6>[ 2.481159] hub 2-1:1.0: USB hub found
10653 11:18:25.443812 <6>[ 2.485566] hub 2-1:1.0: 3 ports detected
10654 11:18:25.565084 <6>[ 2.602622] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10655 11:18:25.719798 <6>[ 2.760426] hub 1-1:1.0: USB hub found
10656 11:18:25.722900 <6>[ 2.764853] hub 1-1:1.0: 4 ports detected
10657 11:18:25.801012 <6>[ 2.838935] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10658 11:18:26.045372 <6>[ 3.082720] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10659 11:18:26.178156 <6>[ 3.218944] hub 1-1.4:1.0: USB hub found
10660 11:18:26.181312 <6>[ 3.223632] hub 1-1.4:1.0: 2 ports detected
10661 11:18:26.477110 <6>[ 3.514692] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10662 11:18:26.668821 <6>[ 3.706684] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10663 11:18:37.685489 <6>[ 14.731232] ALSA device list:
10664 11:18:37.691842 <6>[ 14.734488] No soundcards found.
10665 11:18:37.704788 <6>[ 14.746865] Freeing unused kernel memory: 8384K
10666 11:18:37.708192 <6>[ 14.751795] Run /init as init process
10667 11:18:37.719086 Loading, please wait...
10668 11:18:37.738736 Starting version 247.3-7+deb11u2
10669 11:18:38.054050 <6>[ 15.093181] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10670 11:18:38.069327 <6>[ 15.111546] remoteproc remoteproc0: scp is available
10671 11:18:38.079287 <4>[ 15.117133] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10672 11:18:38.085220 <6>[ 15.126992] remoteproc remoteproc0: powering up scp
10673 11:18:38.095479 <4>[ 15.132183] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10674 11:18:38.102526 <6>[ 15.133500] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10675 11:18:38.108584 <3>[ 15.145159] remoteproc remoteproc0: request_firmware failed: -2
10676 11:18:38.115805 <6>[ 15.149676] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10677 11:18:38.121958 <6>[ 15.159069] usbcore: registered new interface driver r8152
10678 11:18:38.132290 <6>[ 15.164669] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10679 11:18:38.153892 <4>[ 15.192591] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10680 11:18:38.166888 <4>[ 15.205247] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10681 11:18:38.173171 <3>[ 15.207420] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10682 11:18:38.183169 <3>[ 15.220836] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10683 11:18:38.186957 <6>[ 15.225496] mc: Linux media interface: v0.10
10684 11:18:38.192944 <3>[ 15.228975] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10685 11:18:38.203056 <6>[ 15.234890] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10686 11:18:38.209958 <3>[ 15.242040] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10687 11:18:38.219525 <3>[ 15.257649] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10688 11:18:38.226240 <4>[ 15.264684] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10689 11:18:38.232983 <4>[ 15.264684] Fallback method does not support PEC.
10690 11:18:38.239634 <3>[ 15.265794] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10691 11:18:38.247655 <6>[ 15.278684] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10692 11:18:38.254476 <3>[ 15.294617] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10693 11:18:38.264088 <3>[ 15.295199] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10694 11:18:38.273871 <4>[ 15.301379] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
10695 11:18:38.280966 <4>[ 15.301389] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
10696 11:18:38.288429 <3>[ 15.302880] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10697 11:18:38.295247 <6>[ 15.303176] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10698 11:18:38.301754 <6>[ 15.303184] pci_bus 0000:00: root bus resource [bus 00-ff]
10699 11:18:38.308452 <6>[ 15.303192] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10700 11:18:38.317855 <6>[ 15.303198] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10701 11:18:38.324474 <6>[ 15.303229] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10702 11:18:38.334664 <6>[ 15.303248] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10703 11:18:38.338266 <6>[ 15.303322] pci 0000:00:00.0: supports D1 D2
10704 11:18:38.344478 <6>[ 15.303326] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10705 11:18:38.351638 <6>[ 15.305086] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10706 11:18:38.358193 <6>[ 15.305186] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10707 11:18:38.367942 <6>[ 15.305214] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10708 11:18:38.374747 <6>[ 15.305233] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10709 11:18:38.381608 <6>[ 15.305250] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10710 11:18:38.384608 <6>[ 15.305360] pci 0000:01:00.0: supports D1 D2
10711 11:18:38.394575 <6>[ 15.305363] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10712 11:18:38.404706 <6>[ 15.306996] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10713 11:18:38.410888 <6>[ 15.307210] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10714 11:18:38.417800 <6>[ 15.314654] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10715 11:18:38.427639 <3>[ 15.320811] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10716 11:18:38.437360 <6>[ 15.321352] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10717 11:18:38.443824 <6>[ 15.328907] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10718 11:18:38.450821 <6>[ 15.329514] usbcore: registered new interface driver cdc_ether
10719 11:18:38.460720 <3>[ 15.335800] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10720 11:18:38.467529 <3>[ 15.337172] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10721 11:18:38.473666 <6>[ 15.338557] videodev: Linux video capture interface: v2.00
10722 11:18:38.480497 <6>[ 15.343894] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10723 11:18:38.487142 <6>[ 15.344138] usbcore: registered new interface driver r8153_ecm
10724 11:18:38.494141 <3>[ 15.349654] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10725 11:18:38.500140 <6>[ 15.350569] Bluetooth: Core ver 2.22
10726 11:18:38.503315 <6>[ 15.350652] NET: Registered PF_BLUETOOTH protocol family
10727 11:18:38.510331 <6>[ 15.350658] Bluetooth: HCI device and connection manager initialized
10728 11:18:38.517137 <6>[ 15.350682] Bluetooth: HCI socket layer initialized
10729 11:18:38.520307 <6>[ 15.350692] Bluetooth: L2CAP socket layer initialized
10730 11:18:38.526807 <6>[ 15.350709] Bluetooth: SCO socket layer initialized
10731 11:18:38.533357 <6>[ 15.356783] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10732 11:18:38.543548 <3>[ 15.366693] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10733 11:18:38.549947 <6>[ 15.372958] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10734 11:18:38.559957 <3>[ 15.380656] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10735 11:18:38.566610 <6>[ 15.384962] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10736 11:18:38.573181 <6>[ 15.384981] pci 0000:00:00.0: PCI bridge to [bus 01]
10737 11:18:38.580405 <6>[ 15.384994] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10738 11:18:38.586502 <6>[ 15.385241] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10739 11:18:38.593437 <3>[ 15.391883] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10740 11:18:38.599977 <6>[ 15.394717] r8152 2-1.3:1.0 eth0: v1.12.13
10741 11:18:38.606351 <6>[ 15.402313] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10742 11:18:38.613266 <6>[ 15.403706] r8152 2-1.3:1.0 enx00e04c787aaa: renamed from eth0
10743 11:18:38.616376 <6>[ 15.404294] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10744 11:18:38.623004 <6>[ 15.404588] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10745 11:18:38.633242 <3>[ 15.406410] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10746 11:18:38.639302 <3>[ 15.406442] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10747 11:18:38.649175 <3>[ 15.406452] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10748 11:18:38.652809 <6>[ 15.407666] usbcore: registered new interface driver btusb
10749 11:18:38.662994 <4>[ 15.408256] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10750 11:18:38.669404 <3>[ 15.408271] Bluetooth: hci0: Failed to load firmware file (-2)
10751 11:18:38.675664 <3>[ 15.408277] Bluetooth: hci0: Failed to set up firmware (-2)
10752 11:18:38.685854 <4>[ 15.408283] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10753 11:18:38.699014 <6>[ 15.415370] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10754 11:18:38.705348 <3>[ 15.421478] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10755 11:18:38.712475 <6>[ 15.423282] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10756 11:18:38.718980 <6>[ 15.429090] usbcore: registered new interface driver uvcvideo
10757 11:18:38.737106 <5>[ 15.776477] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10758 11:18:38.755959 <5>[ 15.794949] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10759 11:18:38.762517 <4>[ 15.801876] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10760 11:18:38.769162 <6>[ 15.810760] cfg80211: failed to load regulatory.db
10761 11:18:38.814963 <6>[ 15.853778] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10762 11:18:38.821449 <6>[ 15.861291] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10763 11:18:38.845340 <6>[ 15.887974] mt7921e 0000:01:00.0: ASIC revision: 79610010
10764 11:18:38.950749 <4>[ 15.986221] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10765 11:18:38.953994 Begin: Loading essential drivers ... done.
10766 11:18:38.960119 Begin: Running /scripts/init-premount ... done.
10767 11:18:38.966791 Begin: Mounting root file system ... Begin: Running /scripts/nfs-top ... done.
10768 11:18:38.973710 Begin: Running /scripts/nfs-premount ... Waiting up to 60 secs for any ethernet to become available
10769 11:18:38.977201 Device /sys/class/net/enx00e04c787aaa found
10770 11:18:38.980304 done.
10771 11:18:39.027304 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10772 11:18:39.068653 <4>[ 16.104827] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10773 11:18:39.188763 <4>[ 16.224331] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10774 11:18:39.304074 <4>[ 16.340151] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10775 11:18:39.419997 <4>[ 16.456043] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10776 11:18:39.536328 <4>[ 16.571962] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10777 11:18:39.652200 <4>[ 16.687886] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10778 11:18:39.768127 <4>[ 16.803892] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10779 11:18:39.883664 <4>[ 16.919825] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10780 11:18:39.948688 <6>[ 16.991048] r8152 2-1.3:1.0 enx00e04c787aaa: carrier on
10781 11:18:40.000125 <4>[ 17.035767] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10782 11:18:40.107227 <3>[ 17.149736] mt7921e 0000:01:00.0: hardware init failed
10783 11:18:40.140132 IP-Config: no response after 2 secs - giving up
10784 11:18:40.175550 IP-Config: enx00e04c787aaa hardware address 00:e0:4c:78:7a:aa mtu 1500 DHCP
10785 11:18:40.178422 IP-Config: enx00e04c787aaa complete (dhcp from 192.168.201.1):
10786 11:18:40.185125 address: 192.168.201.12 broadcast: 192.168.201.255 netmask: 255.255.255.0
10787 11:18:40.195105 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
10788 11:18:40.201896 host : mt8192-asurada-spherion-r0-cbg-0
10789 11:18:40.205129 domain : lava-rack
10790 11:18:40.208336 rootserver: 192.168.201.1 rootpath:
10791 11:18:40.211272 filename :
10792 11:18:40.241145 done.
10793 11:18:40.247537 Begin: Running /scripts/nfs-bottom ... done.
10794 11:18:40.264096 Begin: Running /scripts/init-bottom ... done.
10795 11:18:41.349738 <6>[ 18.392277] NET: Registered PF_INET6 protocol family
10796 11:18:41.356067 <6>[ 18.398906] Segment Routing with IPv6
10797 11:18:41.359672 <6>[ 18.402890] In-situ OAM (IOAM) with IPv6
10798 11:18:41.463205 <30>[ 18.486229] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10799 11:18:41.466277 <30>[ 18.510017] systemd[1]: Detected architecture arm64.
10800 11:18:41.484643
10801 11:18:41.488306 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10802 11:18:41.488387
10803 11:18:41.506009 <30>[ 18.548712] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10804 11:18:41.928638 <30>[ 18.968335] systemd[1]: Queued start job for default target Graphical Interface.
10805 11:18:41.960782 <30>[ 19.003749] systemd[1]: Created slice system-getty.slice.
10806 11:18:41.967485 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10807 11:18:41.984337 <30>[ 19.027260] systemd[1]: Created slice system-modprobe.slice.
10808 11:18:41.990853 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10809 11:18:42.008685 <30>[ 19.051847] systemd[1]: Created slice system-serial\x2dgetty.slice.
10810 11:18:42.019269 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10811 11:18:42.032187 <30>[ 19.075190] systemd[1]: Created slice User and Session Slice.
10812 11:18:42.038993 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10813 11:18:42.059489 <30>[ 19.098837] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10814 11:18:42.066286 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10815 11:18:42.083148 <30>[ 19.122835] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10816 11:18:42.090034 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10817 11:18:42.110477 <30>[ 19.146777] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10818 11:18:42.117268 <30>[ 19.158799] systemd[1]: Reached target Local Encrypted Volumes.
10819 11:18:42.123573 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10820 11:18:42.139974 <30>[ 19.182815] systemd[1]: Reached target Paths.
10821 11:18:42.143230 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10822 11:18:42.159696 <30>[ 19.202714] systemd[1]: Reached target Remote File Systems.
10823 11:18:42.166164 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10824 11:18:42.179702 <30>[ 19.222700] systemd[1]: Reached target Slices.
10825 11:18:42.183359 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10826 11:18:42.200266 <30>[ 19.242713] systemd[1]: Reached target Swap.
10827 11:18:42.203344 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10828 11:18:42.223025 <30>[ 19.262878] systemd[1]: Listening on initctl Compatibility Named Pipe.
10829 11:18:42.230238 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10830 11:18:42.236806 <30>[ 19.278044] systemd[1]: Listening on Journal Audit Socket.
10831 11:18:42.243031 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10832 11:18:42.256814 <30>[ 19.299579] systemd[1]: Listening on Journal Socket (/dev/log).
10833 11:18:42.263281 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10834 11:18:42.280740 <30>[ 19.323504] systemd[1]: Listening on Journal Socket.
10835 11:18:42.287384 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10836 11:18:42.304511 <30>[ 19.343838] systemd[1]: Listening on Network Service Netlink Socket.
10837 11:18:42.310767 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10838 11:18:42.325558 <30>[ 19.368671] systemd[1]: Listening on udev Control Socket.
10839 11:18:42.332210 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10840 11:18:42.347835 <30>[ 19.390910] systemd[1]: Listening on udev Kernel Socket.
10841 11:18:42.354695 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10842 11:18:42.388277 <30>[ 19.431001] systemd[1]: Mounting Huge Pages File System...
10843 11:18:42.394713 Mounting [0;1;39mHuge Pages File System[0m...
10844 11:18:42.409931 <30>[ 19.453080] systemd[1]: Mounting POSIX Message Queue File System...
10845 11:18:42.416766 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10846 11:18:42.434199 <30>[ 19.476957] systemd[1]: Mounting Kernel Debug File System...
10847 11:18:42.440856 Mounting [0;1;39mKernel Debug File System[0m...
10848 11:18:42.459816 <30>[ 19.498987] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10849 11:18:42.507483 <30>[ 19.547156] systemd[1]: Starting Create list of static device nodes for the current kernel...
10850 11:18:42.514436 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10851 11:18:42.534655 <30>[ 19.577369] systemd[1]: Starting Load Kernel Module configfs...
10852 11:18:42.541223 Starting [0;1;39mLoad Kernel Module configfs[0m...
10853 11:18:42.558637 <30>[ 19.601417] systemd[1]: Starting Load Kernel Module drm...
10854 11:18:42.565037 Starting [0;1;39mLoad Kernel Module drm[0m...
10855 11:18:42.582437 <30>[ 19.625275] systemd[1]: Starting Load Kernel Module fuse...
10856 11:18:42.588931 Starting [0;1;39mLoad Kernel Module fuse[0m...
10857 11:18:42.618531 <6>[ 19.661309] fuse: init (API version 7.37)
10858 11:18:42.628459 <30>[ 19.661565] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10859 11:18:42.636799 <30>[ 19.679534] systemd[1]: Starting Journal Service...
10860 11:18:42.639892 Starting [0;1;39mJournal Service[0m...
10861 11:18:42.662748 <30>[ 19.705209] systemd[1]: Starting Load Kernel Modules...
10862 11:18:42.669133 Starting [0;1;39mLoad Kernel Modules[0m...
10863 11:18:42.691013 <30>[ 19.730306] systemd[1]: Starting Remount Root and Kernel File Systems...
10864 11:18:42.697177 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10865 11:18:42.714613 <30>[ 19.757416] systemd[1]: Starting Coldplug All udev Devices...
10866 11:18:42.720871 Starting [0;1;39mColdplug All udev Devices[0m...
10867 11:18:42.738840 <30>[ 19.781705] systemd[1]: Mounted Huge Pages File System.
10868 11:18:42.745256 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10869 11:18:42.760314 <30>[ 19.803218] systemd[1]: Mounted POSIX Message Queue File System.
10870 11:18:42.766816 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10871 11:18:42.784364 <30>[ 19.826990] systemd[1]: Mounted Kernel Debug File System.
10872 11:18:42.797945 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0<3>[ 19.837382] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10873 11:18:42.798034 m.
10874 11:18:42.820282 <30>[ 19.859560] systemd[1]: Finished Create list of static device nodes for the current kernel.
10875 11:18:42.837468 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current<3>[ 19.875070] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10876 11:18:42.837560 kernel[0m.
10877 11:18:42.852677 <30>[ 19.895707] systemd[1]: modprobe@configfs.service: Succeeded.
10878 11:18:42.859303 <30>[ 19.902388] systemd[1]: Finished Load Kernel Module configfs.
10879 11:18:42.866525 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10880 11:18:42.878226 <3>[ 19.917809] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10881 11:18:42.885140 <30>[ 19.927827] systemd[1]: modprobe@drm.service: Succeeded.
10882 11:18:42.891717 <30>[ 19.934278] systemd[1]: Finished Load Kernel Module drm.
10883 11:18:42.898666 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10884 11:18:42.908785 <3>[ 19.948148] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10885 11:18:42.915512 <30>[ 19.958041] systemd[1]: modprobe@fuse.service: Succeeded.
10886 11:18:42.922386 <30>[ 19.964535] systemd[1]: Finished Load Kernel Module fuse.
10887 11:18:42.929121 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
10888 11:18:42.939252 <3>[ 19.978033] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10889 11:18:42.946162 <30>[ 19.988145] systemd[1]: Finished Load Kernel Modules.
10890 11:18:42.952424 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10891 11:18:42.969781 <3>[ 20.009600] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10892 11:18:42.980516 <30>[ 20.020051] systemd[1]: Finished Remount Root and Kernel File Systems.
10893 11:18:42.986831 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
10894 11:18:43.002253 <3>[ 20.041582] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10895 11:18:43.035651 <3>[ 20.075181] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10896 11:18:43.045125 <30>[ 20.088111] systemd[1]: Mounting FUSE Control File System...
10897 11:18:43.051910 Mounting [0;1;39mFUSE Control File System[0m...
10898 11:18:43.070107 <30>[ 20.109471] systemd[1]: Mounting Kernel Configuration File System...
10899 11:18:43.073219 Mounting [0;1;39mKernel Configuration File System[0m...
10900 11:18:43.094837 <30>[ 20.134339] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
10901 11:18:43.104697 <30>[ 20.143319] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
10902 11:18:43.136592 <30>[ 20.179260] systemd[1]: Starting Load/Save Random Seed...
10903 11:18:43.143105 Starting [0;1;39mLoad/Save Random Seed[0m...
10904 11:18:43.162850 <30>[ 20.205690] systemd[1]: Starting Apply Kernel Variables...
10905 11:18:43.169948 Starting [0;1;39mApply Kernel Variables[0m...
10906 11:18:43.187763 <30>[ 20.230342] systemd[1]: Starting Create System Users...
10907 11:18:43.194528 Starting [0;1;39mCreate System Users[0m...
10908 11:18:43.210203 <30>[ 20.252748] systemd[1]: Started Journal Service.
10909 11:18:43.216308 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10910 11:18:43.229657 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
10911 11:18:43.249803 <4>[ 20.282911] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-5/5-000b/power_supply/sbs-5-000b: failed to send uevent
10912 11:18:43.259876 <3>[ 20.298737] power_supply sbs-5-000b: uevent: failed to send synthetic uevent: -5
10913 11:18:43.266245 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10914 11:18:43.284912 [[0;32m OK [0m] Finished [0<4>[ 20.326313] power_supply_show_property: 4 callbacks suppressed
10915 11:18:43.295473 ;1;39mLoad/Save <3>[ 20.326328] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10916 11:18:43.298429 Random Seed[0m.
10917 11:18:43.313659 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
10918 11:18:43.324328 <3>[ 20.364201] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10919 11:18:43.331292 See 'systemctl status systemd-udev-trigger.service' for details.
10920 11:18:43.353874 <3>[ 20.393589] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10921 11:18:43.360976 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10922 11:18:43.383812 <3>[ 20.423344] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10923 11:18:43.390360 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10924 11:18:43.412842 <3>[ 20.452704] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10925 11:18:43.424195 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10926 11:18:43.442450 <3>[ 20.482046] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10927 11:18:43.451181 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10928 11:18:43.472459 <3>[ 20.512234] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10929 11:18:43.503136 <3>[ 20.542622] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10930 11:18:43.509722 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10931 11:18:43.534886 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (<3>[ 20.572063] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10932 11:18:43.534972 Pre)[0m.
10933 11:18:43.548134 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10934 11:18:43.563175 <3>[ 20.602827] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10935 11:18:43.596172 Startin<46>[ 20.636071] systemd-journald[294]: Received client request to flush runtime journal.
10936 11:18:43.602298 g [0;1;39mRule-based Manage…for Device Events and Files[0m...
10937 11:18:44.965577 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10938 11:18:45.021554 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10939 11:18:45.040020 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10940 11:18:45.077206 Starting [0;1;39mNetwork Service[0m...
10941 11:18:45.373822 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10942 11:18:45.392123 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10943 11:18:45.448141 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10944 11:18:45.594992 <6>[ 22.638080] remoteproc remoteproc0: powering up scp
10945 11:18:45.631819 <4>[ 22.671998] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10946 11:18:45.638509 <3>[ 22.681944] remoteproc remoteproc0: request_firmware failed: -2
10947 11:18:45.648532 <3>[ 22.688131] fops_vcodec_open(),166: [MTK_V4L2][ERROR] vpu_load_firmware failed!
10948 11:18:45.777387 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10949 11:18:45.795577 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10950 11:18:45.808262 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10951 11:18:45.827510 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10952 11:18:45.848019 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10953 11:18:45.904330 Starting [0;1;39mNetwork Name Resolution[0m...
10954 11:18:45.922403 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10955 11:18:45.946529 Starting [0;1;39mNetwork Time Synchronization[0m...
10956 11:18:45.963075 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10957 11:18:45.980838 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10958 11:18:46.008839 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10959 11:18:46.366006 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10960 11:18:46.383990 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10961 11:18:46.406661 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10962 11:18:46.419712 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10963 11:18:46.435239 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10964 11:18:46.465975 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
10965 11:18:46.488850 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
10966 11:18:46.508693 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
10967 11:18:46.529651 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10968 11:18:46.547433 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10969 11:18:46.567781 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10970 11:18:46.579437 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10971 11:18:46.595563 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10972 11:18:46.628001 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10973 11:18:46.706967 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
10974 11:18:46.820137 Starting [0;1;39mUser Login Management[0m...
10975 11:18:46.836520 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
10976 11:18:46.855997 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10977 11:18:46.875270 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10978 11:18:46.920287 Starting [0;1;39mPermit User Sessions[0m...
10979 11:18:47.010878 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
10980 11:18:47.036247 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10981 11:18:47.092408 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10982 11:18:47.110545 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10983 11:18:47.117328 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10984 11:18:47.132337 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10985 11:18:47.139508 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10986 11:18:47.155230 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10987 11:18:47.194274 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10988 11:18:47.261353 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10989 11:18:47.320498
10990 11:18:47.320722
10991 11:18:47.323355 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10992 11:18:47.323502
10993 11:18:47.326431 debian-bullseye-arm64 login: root (automatic login)
10994 11:18:47.326558
10995 11:18:47.326680
10996 11:18:47.599659 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Mon Jun 5 10:57:14 UTC 2023 aarch64
10997 11:18:47.599822
10998 11:18:47.606343 The programs included with the Debian GNU/Linux system are free software;
10999 11:18:47.612786 the exact distribution terms for each program are described in the
11000 11:18:47.616329 individual files in /usr/share/doc/*/copyright.
11001 11:18:47.616412
11002 11:18:47.622586 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11003 11:18:47.622669 permitted by applicable law.
11004 11:18:48.364129 Matched prompt #10: / #
11006 11:18:48.365589 Setting prompt string to ['/ #']
11007 11:18:48.366111 end: 2.2.5.1 login-action (duration 00:00:26) [common]
11009 11:18:48.367598 end: 2.2.5 auto-login-action (duration 00:00:26) [common]
11010 11:18:48.367992 start: 2.2.6 expect-shell-connection (timeout 00:03:37) [common]
11011 11:18:48.368303 Setting prompt string to ['/ #']
11012 11:18:48.368567 Forcing a shell prompt, looking for ['/ #']
11014 11:18:48.419382 / #
11015 11:18:48.419931 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11016 11:18:48.420289 Waiting using forced prompt support (timeout 00:02:30)
11017 11:18:48.424771
11018 11:18:48.425609 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11019 11:18:48.426148 start: 2.2.7 export-device-env (timeout 00:03:37) [common]
11021 11:18:48.527239 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10591269/extract-nfsrootfs-e40z_w25'
11022 11:18:48.533253 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/10591269/extract-nfsrootfs-e40z_w25'
11024 11:18:48.634671 / # export NFS_SERVER_IP='192.168.201.1'
11025 11:18:48.640170 export NFS_SERVER_IP='192.168.201.1'
11026 11:18:48.640860 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11027 11:18:48.641296 end: 2.2 depthcharge-retry (duration 00:01:23) [common]
11028 11:18:48.641738 end: 2 depthcharge-action (duration 00:01:23) [common]
11029 11:18:48.642150 start: 3 lava-test-retry (timeout 00:07:55) [common]
11030 11:18:48.642528 start: 3.1 lava-test-shell (timeout 00:07:55) [common]
11031 11:18:48.642859 Using namespace: common
11033 11:18:48.744057 / # #
11034 11:18:48.744620 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
11035 11:18:48.750402 #
11036 11:18:48.751252 Using /lava-10591269
11038 11:18:48.852416 / # export SHELL=/bin/bash
11039 11:18:48.858391 export SHELL=/bin/bash
11041 11:18:48.959861 / # . /lava-10591269/environment
11042 11:18:48.965997 . /lava-10591269/environment
11044 11:18:49.072300 / # /lava-10591269/bin/lava-test-runner /lava-10591269/0
11045 11:18:49.072841 Test shell timeout: 10s (minimum of the action and connection timeout)
11046 11:18:49.078192 /lava-10591269/bin/lava-test-runner /lava-10591269/0
11047 11:18:49.318060 + export TESTRUN_ID=0_timesync-off
11048 11:18:49.321522 + TESTRUN_ID=0_timesync-off
11049 11:18:49.324449 + cd /lava-10591269/0/tests/0_timesync-off
11050 11:18:49.327942 ++ cat uuid
11051 11:18:49.328047 + UUID=10591269_1.6.2.3.1
11052 11:18:49.331056 + set +x
11053 11:18:49.334729 <LAVA_SIGNAL_STARTRUN 0_timesync-off 10591269_1.6.2.3.1>
11054 11:18:49.335013 Received signal: <STARTRUN> 0_timesync-off 10591269_1.6.2.3.1
11055 11:18:49.335115 Starting test lava.0_timesync-off (10591269_1.6.2.3.1)
11056 11:18:49.335236 Skipping test definition patterns.
11057 11:18:49.337730 + systemctl stop systemd-timesyncd
11058 11:18:49.362942 + set +x
11059 11:18:49.366036 <LAVA_SIGNAL_ENDRUN 0_timesync-off 10591269_1.6.2.3.1>
11060 11:18:49.366310 Received signal: <ENDRUN> 0_timesync-off 10591269_1.6.2.3.1
11061 11:18:49.366417 Ending use of test pattern.
11062 11:18:49.366510 Ending test lava.0_timesync-off (10591269_1.6.2.3.1), duration 0.03
11064 11:18:49.413798 + export TESTRUN_ID=1_kselftest-tpm2
11065 11:18:49.417003 + TESTRUN_ID=1_kselftest-tpm2
11066 11:18:49.420176 + cd /lava-10591269/0/tests/1_kselftest-tpm2
11067 11:18:49.423750 ++ cat uuid
11068 11:18:49.426815 + UUID=10591269_1.6.2.3.5
11069 11:18:49.426916 + set +x
11070 11:18:49.430327 <LAVA_SIGNAL_STARTRUN 1_kselftest-tpm2 10591269_1.6.2.3.5>
11071 11:18:49.430602 Received signal: <STARTRUN> 1_kselftest-tpm2 10591269_1.6.2.3.5
11072 11:18:49.430699 Starting test lava.1_kselftest-tpm2 (10591269_1.6.2.3.5)
11073 11:18:49.430810 Skipping test definition patterns.
11074 11:18:49.433204 + cd ./automated/linux/kselftest/
11075 11:18:49.459964 + ./kselftest.sh -c tpm2 -T '' -t kselftest_armhf.tar.gz -s True -u http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz -L '' -S /dev/null -b mt8192-asurada-spherion-r0 -g cip -e '' -p /opt/kselftests/mainline/ -n 1 -i 1
11076 11:18:49.480840 INFO: install_deps skipped
11077 11:18:49.581392 --2023-06-05 11:18:37-- http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kselftest.tar.xz
11078 11:18:49.588841 Resolving storage.kernelci.org (storage.kernelci.org)... 52.250.1.28
11079 11:18:49.732296 Connecting to storage.kernelci.org (storage.kernelci.org)|52.250.1.28|:80... connected.
11080 11:18:49.874933 HTTP request sent, awaiting response... 200 OK
11081 11:18:49.878482 Length: 2714204 (2.6M) [application/octet-stream]
11082 11:18:49.881811 Saving to: 'kselftest.tar.xz'
11083 11:18:49.882325
11084 11:18:49.882666
11085 11:18:50.160208 kselftest.tar.xz 0%[ ] 0 --.-KB/s
11086 11:18:50.445930 kselftest.tar.xz 1%[ ] 47.81K 164KB/s
11087 11:18:50.922222 kselftest.tar.xz 8%[> ] 217.50K 373KB/s
11088 11:18:51.159868 kselftest.tar.xz 30%[=====> ] 814.23K 760KB/s
11089 11:18:51.187994 kselftest.tar.xz 91%[=================> ] 2.36M 1.80MB/s
11090 11:18:51.195080 kselftest.tar.xz 100%[===================>] 2.59M 1.93MB/s in 1.3s
11091 11:18:51.195185
11092 11:18:51.437140 2023-06-05 11:18:39 (1.93 MB/s) - 'kselftest.tar.xz' saved [2714204/2714204]
11093 11:18:51.437275
11094 11:18:56.085076 skiplist:
11095 11:18:56.088784 ========================================
11096 11:18:56.091816 ========================================
11097 11:18:56.126147 tpm2:test_smoke.sh
11098 11:18:56.129033 tpm2:test_space.sh
11099 11:18:56.142696 ============== Tests to run ===============
11100 11:18:56.143118 tpm2:test_smoke.sh
11101 11:18:56.146022 tpm2:test_space.sh
11102 11:18:56.148698 ===========End Tests to run ===============
11103 11:18:56.231862 <12>[ 33.276218] kselftest: Running tests in tpm2
11104 11:18:56.240219 TAP version 13
11105 11:18:56.250697 1..2
11106 11:18:56.274290 # selftests: tpm2: test_smoke.sh
11107 11:18:57.419309 # test_read_partial_overwrite (tpm2_tests.SmokeTest) ... ERROR
11108 11:18:57.422787 # test_read_partial_resp (tpm2_tests.SmokeTest) ... ERROR
11109 11:18:57.429889 # Exception ignored in: <function Client.__del__ at 0xffff8dd1cd30>
11110 11:18:57.433113 # Traceback (most recent call last):
11111 11:18:57.442858 # File "/lava-10591269/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11112 11:18:57.443289 # if self.tpm:
11113 11:18:57.449398 # AttributeError: 'Client' object has no attribute 'tpm'
11114 11:18:57.452723 # test_seal_with_auth (tpm2_tests.SmokeTest) ... ERROR
11115 11:18:57.459781 # Exception ignored in: <function Client.__del__ at 0xffff8dd1cd30>
11116 11:18:57.462984 # Traceback (most recent call last):
11117 11:18:57.472618 # File "/lava-10591269/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11118 11:18:57.475787 # if self.tpm:
11119 11:18:57.479224 # AttributeError: 'Client' object has no attribute 'tpm'
11120 11:18:57.485964 # test_seal_with_policy (tpm2_tests.SmokeTest) ... ERROR
11121 11:18:57.492593 # Exception ignored in: <function Client.__del__ at 0xffff8dd1cd30>
11122 11:18:57.496237 # Traceback (most recent call last):
11123 11:18:57.506083 # File "/lava-10591269/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11124 11:18:57.506531 # if self.tpm:
11125 11:18:57.512958 # AttributeError: 'Client' object has no attribute 'tpm'
11126 11:18:57.515972 # test_seal_with_too_long_auth (tpm2_tests.SmokeTest) ... ERROR
11127 11:18:57.522998 # Exception ignored in: <function Client.__del__ at 0xffff8dd1cd30>
11128 11:18:57.526007 # Traceback (most recent call last):
11129 11:18:57.535857 # File "/lava-10591269/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11130 11:18:57.539014 # if self.tpm:
11131 11:18:57.542241 # AttributeError: 'Client' object has no attribute 'tpm'
11132 11:18:57.549304 # test_send_two_cmds (tpm2_tests.SmokeTest) ... ERROR
11133 11:18:57.552655 # Exception ignored in: <function Client.__del__ at 0xffff8dd1cd30>
11134 11:18:57.555892 # Traceback (most recent call last):
11135 11:18:57.566077 # File "/lava-10591269/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11136 11:18:57.569267 # if self.tpm:
11137 11:18:57.572354 # AttributeError: 'Client' object has no attribute 'tpm'
11138 11:18:57.579125 # test_too_short_cmd (tpm2_tests.SmokeTest) ... ERROR
11139 11:18:57.585944 # Exception ignored in: <function Client.__del__ at 0xffff8dd1cd30>
11140 11:18:57.586400 # Traceback (most recent call last):
11141 11:18:57.596011 # File "/lava-10591269/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11142 11:18:57.599400 # if self.tpm:
11143 11:18:57.602402 # AttributeError: 'Client' object has no attribute 'tpm'
11144 11:18:57.609587 # test_unseal_with_wrong_auth (tpm2_tests.SmokeTest) ... ERROR
11145 11:18:57.616385 # Exception ignored in: <function Client.__del__ at 0xffff8dd1cd30>
11146 11:18:57.619283 # Traceback (most recent call last):
11147 11:18:57.628946 # File "/lava-10591269/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11148 11:18:57.629416 # if self.tpm:
11149 11:18:57.635746 # AttributeError: 'Client' object has no attribute 'tpm'
11150 11:18:57.642473 # test_unseal_with_wrong_policy (tpm2_tests.SmokeTest) ... ERROR
11151 11:18:57.645683 # Exception ignored in: <function Client.__del__ at 0xffff8dd1cd30>
11152 11:18:57.648904 # Traceback (most recent call last):
11153 11:18:57.659236 # File "/lava-10591269/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 375, in __del__
11154 11:18:57.663077 # if self.tpm:
11155 11:18:57.666189 # AttributeError: 'Client' object has no attribute 'tpm'
11156 11:18:57.666613 #
11157 11:18:57.672574 # ======================================================================
11158 11:18:57.679657 # ERROR: test_read_partial_overwrite (tpm2_tests.SmokeTest)
11159 11:18:57.689065 # ----------------------------------------------------------------------
11160 11:18:57.689532 # Traceback (most recent call last):
11161 11:18:57.699841 # File "/lava-10591269/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 16, in setUp
11162 11:18:57.703006 # self.root_key = self.client.create_root_key()
11163 11:18:57.713319 # File "/lava-10591269/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11164 11:18:57.719551 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11165 11:18:57.729852 # File "/lava-10591269/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11166 11:18:57.732961 # raise ProtocolError(cc, rc)
11167 11:18:57.739640 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11168 11:18:57.740063 #
11169 11:18:57.746040 # ======================================================================
11170 11:18:57.749421 # ERROR: test_read_partial_resp (tpm2_tests.SmokeTest)
11171 11:18:57.756312 # ----------------------------------------------------------------------
11172 11:18:57.759597 # Traceback (most recent call last):
11173 11:18:57.769911 # File "/lava-10591269/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11174 11:18:57.773173 # self.client = tpm2.Client()
11175 11:18:57.783059 # File "/lava-10591269/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11176 11:18:57.786354 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11177 11:18:57.792570 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11178 11:18:57.793035 #
11179 11:18:57.799675 # ======================================================================
11180 11:18:57.802832 # ERROR: test_seal_with_auth (tpm2_tests.SmokeTest)
11181 11:18:57.809773 # ----------------------------------------------------------------------
11182 11:18:57.813069 # Traceback (most recent call last):
11183 11:18:57.822980 # File "/lava-10591269/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11184 11:18:57.826561 # self.client = tpm2.Client()
11185 11:18:57.836112 # File "/lava-10591269/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11186 11:18:57.842780 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11187 11:18:57.846130 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11188 11:18:57.846580 #
11189 11:18:57.853157 # ======================================================================
11190 11:18:57.859748 # ERROR: test_seal_with_policy (tpm2_tests.SmokeTest)
11191 11:18:57.866260 # ----------------------------------------------------------------------
11192 11:18:57.869513 # Traceback (most recent call last):
11193 11:18:57.879762 # File "/lava-10591269/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11194 11:18:57.882905 # self.client = tpm2.Client()
11195 11:18:57.892974 # File "/lava-10591269/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11196 11:18:57.896260 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11197 11:18:57.902887 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11198 11:18:57.903308 #
11199 11:18:57.909875 # ======================================================================
11200 11:18:57.912688 # ERROR: test_seal_with_too_long_auth (tpm2_tests.SmokeTest)
11201 11:18:57.919933 # ----------------------------------------------------------------------
11202 11:18:57.922984 # Traceback (most recent call last):
11203 11:18:57.932632 # File "/lava-10591269/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11204 11:18:57.936018 # self.client = tpm2.Client()
11205 11:18:57.946347 # File "/lava-10591269/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11206 11:18:57.952828 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11207 11:18:57.956229 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11208 11:18:57.956661 #
11209 11:18:57.962703 # ======================================================================
11210 11:18:57.969239 # ERROR: test_send_two_cmds (tpm2_tests.SmokeTest)
11211 11:18:57.973119 # ----------------------------------------------------------------------
11212 11:18:57.976385 # Traceback (most recent call last):
11213 11:18:57.985934 # File "/lava-10591269/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11214 11:18:57.989908 # self.client = tpm2.Client()
11215 11:18:57.999521 # File "/lava-10591269/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11216 11:18:58.008327 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11217 11:18:58.011641 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11218 11:18:58.012072 #
11219 11:18:58.018955 # ======================================================================
11220 11:18:58.022081 # ERROR: test_too_short_cmd (tpm2_tests.SmokeTest)
11221 11:18:58.027294 # ----------------------------------------------------------------------
11222 11:18:58.030849 # Traceback (most recent call last):
11223 11:18:58.040749 # File "/lava-10591269/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11224 11:18:58.044569 # self.client = tpm2.Client()
11225 11:18:58.055742 # File "/lava-10591269/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11226 11:18:58.060984 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11227 11:18:58.064053 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11228 11:18:58.064483 #
11229 11:18:58.070746 # ======================================================================
11230 11:18:58.077465 # ERROR: test_unseal_with_wrong_auth (tpm2_tests.SmokeTest)
11231 11:18:58.084386 # ----------------------------------------------------------------------
11232 11:18:58.087599 # Traceback (most recent call last):
11233 11:18:58.097870 # File "/lava-10591269/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11234 11:18:58.101381 # self.client = tpm2.Client()
11235 11:18:58.110711 # File "/lava-10591269/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11236 11:18:58.114652 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11237 11:18:58.121056 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11238 11:18:58.121626 #
11239 11:18:58.127797 # ======================================================================
11240 11:18:58.130788 # ERROR: test_unseal_with_wrong_policy (tpm2_tests.SmokeTest)
11241 11:18:58.137965 # ----------------------------------------------------------------------
11242 11:18:58.140959 # Traceback (most recent call last):
11243 11:18:58.151212 # File "/lava-10591269/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 15, in setUp
11244 11:18:58.154531 # self.client = tpm2.Client()
11245 11:18:58.164424 # File "/lava-10591269/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 364, in __init__
11246 11:18:58.168094 # self.tpm = open('/dev/tpm0', 'r+b', buffering=0)
11247 11:18:58.174511 # OSError: [Errno 16] Device or resource busy: '/dev/tpm0'
11248 11:18:58.175053 #
11249 11:18:58.181366 # ----------------------------------------------------------------------
11250 11:18:58.184628 # Ran 9 tests in 0.029s
11251 11:18:58.185166 #
11252 11:18:58.185540 # FAILED (errors=9)
11253 11:18:58.191265 # test_async (tpm2_tests.AsyncTest) ... ok
11254 11:18:58.194636 # test_flush_invalid_context (tpm2_tests.AsyncTest) ... ok
11255 11:18:58.195183 #
11256 11:18:58.201459 # ----------------------------------------------------------------------
11257 11:18:58.204556 # Ran 2 tests in 0.032s
11258 11:18:58.205021 #
11259 11:18:58.205411 # OK
11260 11:18:58.207700 ok 1 selftests: tpm2: test_smoke.sh
11261 11:18:58.211703 # selftests: tpm2: test_space.sh
11262 11:18:58.214617 # test_flush_context (tpm2_tests.SpaceTest) ... ERROR
11263 11:18:58.221145 # test_get_handles (tpm2_tests.SpaceTest) ... ERROR
11264 11:18:58.224638 # test_invalid_cc (tpm2_tests.SpaceTest) ... ERROR
11265 11:18:58.231705 # test_make_two_spaces (tpm2_tests.SpaceTest) ... ERROR
11266 11:18:58.232243 #
11267 11:18:58.237890 # ======================================================================
11268 11:18:58.241060 # ERROR: test_flush_context (tpm2_tests.SpaceTest)
11269 11:18:58.247911 # ----------------------------------------------------------------------
11270 11:18:58.251098 # Traceback (most recent call last):
11271 11:18:58.260958 # File "/lava-10591269/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 261, in test_flush_context
11272 11:18:58.264702 # root1 = space1.create_root_key()
11273 11:18:58.274298 # File "/lava-10591269/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11274 11:18:58.281103 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11275 11:18:58.291366 # File "/lava-10591269/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11276 11:18:58.294234 # raise ProtocolError(cc, rc)
11277 11:18:58.300919 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11278 11:18:58.301350 #
11279 11:18:58.307786 # ======================================================================
11280 11:18:58.311050 # ERROR: test_get_handles (tpm2_tests.SpaceTest)
11281 11:18:58.317592 # ----------------------------------------------------------------------
11282 11:18:58.320713 # Traceback (most recent call last):
11283 11:18:58.331212 # File "/lava-10591269/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 271, in test_get_handles
11284 11:18:58.334246 # space1.create_root_key()
11285 11:18:58.344404 # File "/lava-10591269/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11286 11:18:58.350870 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11287 11:18:58.361194 # File "/lava-10591269/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11288 11:18:58.364095 # raise ProtocolError(cc, rc)
11289 11:18:58.370878 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11290 11:18:58.371401 #
11291 11:18:58.377356 # ======================================================================
11292 11:18:58.381310 # ERROR: test_invalid_cc (tpm2_tests.SpaceTest)
11293 11:18:58.387109 # ----------------------------------------------------------------------
11294 11:18:58.391115 # Traceback (most recent call last):
11295 11:18:58.400911 # File "/lava-10591269/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 290, in test_invalid_cc
11296 11:18:58.403705 # root1 = space1.create_root_key()
11297 11:18:58.414065 # File "/lava-10591269/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11298 11:18:58.421164 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11299 11:18:58.430690 # File "/lava-10591269/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11300 11:18:58.434177 # raise ProtocolError(cc, rc)
11301 11:18:58.440870 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11302 11:18:58.441436 #
11303 11:18:58.447607 # ======================================================================
11304 11:18:58.450637 # ERROR: test_make_two_spaces (tpm2_tests.SpaceTest)
11305 11:18:58.457503 # ----------------------------------------------------------------------
11306 11:18:58.460695 # Traceback (most recent call last):
11307 11:18:58.473941 # File "/lava-10591269/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2_tests.py", line 247, in test_make_two_spaces
11308 11:18:58.477023 # root1 = space1.create_root_key()
11309 11:18:58.487232 # File "/lava-10591269/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 587, in create_root_key
11310 11:18:58.493840 # return struct.unpack('>I', self.send_cmd(cmd)[10:14])[0]
11311 11:18:58.503865 # File "/lava-10591269/0/tests/1_kselftest-tpm2/automated/linux/kselftest/tpm2/tpm2.py", line 402, in send_cmd
11312 11:18:58.504292 # raise ProtocolError(cc, rc)
11313 11:18:58.510239 # tpm2.ProtocolError: TPM_RC_BAD_AUTH: cc=0x00000131, rc=0x000009a2
11314 11:18:58.510656 #
11315 11:18:58.517119 # ----------------------------------------------------------------------
11316 11:18:58.520343 # Ran 4 tests in 0.076s
11317 11:18:58.520759 #
11318 11:18:58.523557 # FAILED (errors=4)
11319 11:18:58.526748 not ok 2 selftests: tpm2: test_space.sh # exit=1
11320 11:18:58.533284 tpm2_test_smoke_sh pass
11321 11:18:58.536303 tpm2_test_space_sh fail
11322 11:18:58.552003 + ../../utils/send-to-lava.sh ./output/result.txt
11323 11:18:58.615305 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass>
11324 11:18:58.616174 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_smoke_sh RESULT=pass
11326 11:18:58.665703 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm2_test_space_sh RESULT=fail>
11327 11:18:58.666389 Received signal: <TESTCASE> TEST_CASE_ID=tpm2_test_space_sh RESULT=fail
11329 11:18:58.668914 + set +x
11330 11:18:58.672056 <LAVA_SIGNAL_ENDRUN 1_kselftest-tpm2 10591269_1.6.2.3.5>
11331 11:18:58.672751 Received signal: <ENDRUN> 1_kselftest-tpm2 10591269_1.6.2.3.5
11332 11:18:58.673138 Ending use of test pattern.
11333 11:18:58.673462 Ending test lava.1_kselftest-tpm2 (10591269_1.6.2.3.5), duration 9.24
11335 11:18:58.675308 <LAVA_TEST_RUNNER EXIT>
11336 11:18:58.676016 ok: lava_test_shell seems to have completed
11337 11:18:58.676582 tpm2_test_smoke_sh: pass
tpm2_test_space_sh: fail
11338 11:18:58.677154 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11339 11:18:58.677630 end: 3 lava-test-retry (duration 00:00:10) [common]
11340 11:18:58.678108 start: 4 finalize (timeout 00:07:45) [common]
11341 11:18:58.678572 start: 4.1 power-off (timeout 00:00:30) [common]
11342 11:18:58.679311 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-0' '--port=1' '--command=off'
11343 11:18:58.799060 >> Command sent successfully.
11344 11:18:58.802610 Returned 0 in 0 seconds
11345 11:18:58.903552 end: 4.1 power-off (duration 00:00:00) [common]
11347 11:18:58.905050 start: 4.2 read-feedback (timeout 00:07:45) [common]
11348 11:18:58.906476 Listened to connection for namespace 'common' for up to 1s
11349 11:18:59.907018 Finalising connection for namespace 'common'
11350 11:18:59.907620 Disconnecting from shell: Finalise
11351 11:18:59.908010 / #
11352 11:19:00.008952 end: 4.2 read-feedback (duration 00:00:01) [common]
11353 11:19:00.009559 end: 4 finalize (duration 00:00:01) [common]
11354 11:19:00.010181 Cleaning after the job
11355 11:19:00.010759 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591269/tftp-deploy-al9f63sa/ramdisk
11356 11:19:00.020948 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591269/tftp-deploy-al9f63sa/kernel
11357 11:19:00.049956 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591269/tftp-deploy-al9f63sa/dtb
11358 11:19:00.050314 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591269/tftp-deploy-al9f63sa/nfsrootfs
11359 11:19:00.122115 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591269/tftp-deploy-al9f63sa/modules
11360 11:19:00.127489 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10591269
11361 11:19:00.656151 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10591269
11362 11:19:00.656330 Job finished correctly