Boot log: mt8192-asurada-spherion-r0
- Errors: 1
- Kernel Errors: 25
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 62
1 11:18:41.773608 lava-dispatcher, installed at version: 2023.05.1
2 11:18:41.773831 start: 0 validate
3 11:18:41.773966 Start time: 2023-06-05 11:18:41.773959+00:00 (UTC)
4 11:18:41.774090 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:18:41.774226 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 11:18:42.059469 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:18:42.059659 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:18:42.350083 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:18:42.350315 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:18:42.639384 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:18:42.639564 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 11:18:42.929815 validate duration: 1.16
14 11:18:42.930163 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 11:18:42.930299 start: 1.1 download-retry (timeout 00:10:00) [common]
16 11:18:42.930417 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 11:18:42.930580 Not decompressing ramdisk as can be used compressed.
18 11:18:42.930697 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230527.0/arm64/rootfs.cpio.gz
19 11:18:42.930795 saving as /var/lib/lava/dispatcher/tmp/10591280/tftp-deploy-_r2evtbo/ramdisk/rootfs.cpio.gz
20 11:18:42.930935 total size: 27151647 (25MB)
21 11:18:42.932174 progress 0% (0MB)
22 11:18:42.939758 progress 5% (1MB)
23 11:18:42.946651 progress 10% (2MB)
24 11:18:42.953722 progress 15% (3MB)
25 11:18:42.960764 progress 20% (5MB)
26 11:18:42.967873 progress 25% (6MB)
27 11:18:42.974792 progress 30% (7MB)
28 11:18:42.981891 progress 35% (9MB)
29 11:18:42.988879 progress 40% (10MB)
30 11:18:42.995743 progress 45% (11MB)
31 11:18:43.002722 progress 50% (12MB)
32 11:18:43.009637 progress 55% (14MB)
33 11:18:43.016982 progress 60% (15MB)
34 11:18:43.024244 progress 65% (16MB)
35 11:18:43.031366 progress 70% (18MB)
36 11:18:43.038288 progress 75% (19MB)
37 11:18:43.045198 progress 80% (20MB)
38 11:18:43.052260 progress 85% (22MB)
39 11:18:43.058980 progress 90% (23MB)
40 11:18:43.066043 progress 95% (24MB)
41 11:18:43.073055 progress 100% (25MB)
42 11:18:43.073275 25MB downloaded in 0.14s (181.92MB/s)
43 11:18:43.073461 end: 1.1.1 http-download (duration 00:00:00) [common]
45 11:18:43.073840 end: 1.1 download-retry (duration 00:00:00) [common]
46 11:18:43.073963 start: 1.2 download-retry (timeout 00:10:00) [common]
47 11:18:43.074081 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 11:18:43.074246 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 11:18:43.074347 saving as /var/lib/lava/dispatcher/tmp/10591280/tftp-deploy-_r2evtbo/kernel/Image
50 11:18:43.074439 total size: 45746688 (43MB)
51 11:18:43.074531 No compression specified
52 11:18:43.075951 progress 0% (0MB)
53 11:18:43.087931 progress 5% (2MB)
54 11:18:43.099863 progress 10% (4MB)
55 11:18:43.111803 progress 15% (6MB)
56 11:18:43.123888 progress 20% (8MB)
57 11:18:43.135847 progress 25% (10MB)
58 11:18:43.147489 progress 30% (13MB)
59 11:18:43.159283 progress 35% (15MB)
60 11:18:43.171289 progress 40% (17MB)
61 11:18:43.183413 progress 45% (19MB)
62 11:18:43.195232 progress 50% (21MB)
63 11:18:43.206541 progress 55% (24MB)
64 11:18:43.218155 progress 60% (26MB)
65 11:18:43.229854 progress 65% (28MB)
66 11:18:43.241642 progress 70% (30MB)
67 11:18:43.253577 progress 75% (32MB)
68 11:18:43.265472 progress 80% (34MB)
69 11:18:43.277019 progress 85% (37MB)
70 11:18:43.288940 progress 90% (39MB)
71 11:18:43.300591 progress 95% (41MB)
72 11:18:43.312110 progress 100% (43MB)
73 11:18:43.312237 43MB downloaded in 0.24s (183.47MB/s)
74 11:18:43.312385 end: 1.2.1 http-download (duration 00:00:00) [common]
76 11:18:43.312622 end: 1.2 download-retry (duration 00:00:00) [common]
77 11:18:43.312744 start: 1.3 download-retry (timeout 00:10:00) [common]
78 11:18:43.312862 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 11:18:43.313031 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 11:18:43.313132 saving as /var/lib/lava/dispatcher/tmp/10591280/tftp-deploy-_r2evtbo/dtb/mt8192-asurada-spherion-r0.dtb
81 11:18:43.313198 total size: 46924 (0MB)
82 11:18:43.313260 No compression specified
83 11:18:43.314324 progress 69% (0MB)
84 11:18:43.314592 progress 100% (0MB)
85 11:18:43.314744 0MB downloaded in 0.00s (29.00MB/s)
86 11:18:43.314872 end: 1.3.1 http-download (duration 00:00:00) [common]
88 11:18:43.315101 end: 1.3 download-retry (duration 00:00:00) [common]
89 11:18:43.315193 start: 1.4 download-retry (timeout 00:10:00) [common]
90 11:18:43.315278 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 11:18:43.315388 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 11:18:43.315458 saving as /var/lib/lava/dispatcher/tmp/10591280/tftp-deploy-_r2evtbo/modules/modules.tar
93 11:18:43.315520 total size: 8547328 (8MB)
94 11:18:43.315581 Using unxz to decompress xz
95 11:18:43.319479 progress 0% (0MB)
96 11:18:43.340802 progress 5% (0MB)
97 11:18:43.365322 progress 10% (0MB)
98 11:18:43.392731 progress 15% (1MB)
99 11:18:43.416746 progress 20% (1MB)
100 11:18:43.441756 progress 25% (2MB)
101 11:18:43.467280 progress 30% (2MB)
102 11:18:43.492237 progress 35% (2MB)
103 11:18:43.516293 progress 40% (3MB)
104 11:18:43.540696 progress 45% (3MB)
105 11:18:43.563997 progress 50% (4MB)
106 11:18:43.586601 progress 55% (4MB)
107 11:18:43.611334 progress 60% (4MB)
108 11:18:43.635888 progress 65% (5MB)
109 11:18:43.660541 progress 70% (5MB)
110 11:18:43.686811 progress 75% (6MB)
111 11:18:43.715775 progress 80% (6MB)
112 11:18:43.737854 progress 85% (6MB)
113 11:18:43.762328 progress 90% (7MB)
114 11:18:43.785437 progress 95% (7MB)
115 11:18:43.808623 progress 100% (8MB)
116 11:18:43.814455 8MB downloaded in 0.50s (16.34MB/s)
117 11:18:43.814735 end: 1.4.1 http-download (duration 00:00:00) [common]
119 11:18:43.815070 end: 1.4 download-retry (duration 00:00:00) [common]
120 11:18:43.815179 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 11:18:43.815290 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 11:18:43.815390 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 11:18:43.815491 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 11:18:43.815736 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10591280/lava-overlay-e8qt1y2h
125 11:18:43.815910 makedir: /var/lib/lava/dispatcher/tmp/10591280/lava-overlay-e8qt1y2h/lava-10591280/bin
126 11:18:43.816055 makedir: /var/lib/lava/dispatcher/tmp/10591280/lava-overlay-e8qt1y2h/lava-10591280/tests
127 11:18:43.816195 makedir: /var/lib/lava/dispatcher/tmp/10591280/lava-overlay-e8qt1y2h/lava-10591280/results
128 11:18:43.816322 Creating /var/lib/lava/dispatcher/tmp/10591280/lava-overlay-e8qt1y2h/lava-10591280/bin/lava-add-keys
129 11:18:43.816483 Creating /var/lib/lava/dispatcher/tmp/10591280/lava-overlay-e8qt1y2h/lava-10591280/bin/lava-add-sources
130 11:18:43.816627 Creating /var/lib/lava/dispatcher/tmp/10591280/lava-overlay-e8qt1y2h/lava-10591280/bin/lava-background-process-start
131 11:18:43.816775 Creating /var/lib/lava/dispatcher/tmp/10591280/lava-overlay-e8qt1y2h/lava-10591280/bin/lava-background-process-stop
132 11:18:43.816920 Creating /var/lib/lava/dispatcher/tmp/10591280/lava-overlay-e8qt1y2h/lava-10591280/bin/lava-common-functions
133 11:18:43.817088 Creating /var/lib/lava/dispatcher/tmp/10591280/lava-overlay-e8qt1y2h/lava-10591280/bin/lava-echo-ipv4
134 11:18:43.817257 Creating /var/lib/lava/dispatcher/tmp/10591280/lava-overlay-e8qt1y2h/lava-10591280/bin/lava-install-packages
135 11:18:43.817420 Creating /var/lib/lava/dispatcher/tmp/10591280/lava-overlay-e8qt1y2h/lava-10591280/bin/lava-installed-packages
136 11:18:43.817559 Creating /var/lib/lava/dispatcher/tmp/10591280/lava-overlay-e8qt1y2h/lava-10591280/bin/lava-os-build
137 11:18:43.817698 Creating /var/lib/lava/dispatcher/tmp/10591280/lava-overlay-e8qt1y2h/lava-10591280/bin/lava-probe-channel
138 11:18:43.817837 Creating /var/lib/lava/dispatcher/tmp/10591280/lava-overlay-e8qt1y2h/lava-10591280/bin/lava-probe-ip
139 11:18:43.817976 Creating /var/lib/lava/dispatcher/tmp/10591280/lava-overlay-e8qt1y2h/lava-10591280/bin/lava-target-ip
140 11:18:43.818115 Creating /var/lib/lava/dispatcher/tmp/10591280/lava-overlay-e8qt1y2h/lava-10591280/bin/lava-target-mac
141 11:18:43.818256 Creating /var/lib/lava/dispatcher/tmp/10591280/lava-overlay-e8qt1y2h/lava-10591280/bin/lava-target-storage
142 11:18:43.818426 Creating /var/lib/lava/dispatcher/tmp/10591280/lava-overlay-e8qt1y2h/lava-10591280/bin/lava-test-case
143 11:18:43.818595 Creating /var/lib/lava/dispatcher/tmp/10591280/lava-overlay-e8qt1y2h/lava-10591280/bin/lava-test-event
144 11:18:43.818761 Creating /var/lib/lava/dispatcher/tmp/10591280/lava-overlay-e8qt1y2h/lava-10591280/bin/lava-test-feedback
145 11:18:43.818968 Creating /var/lib/lava/dispatcher/tmp/10591280/lava-overlay-e8qt1y2h/lava-10591280/bin/lava-test-raise
146 11:18:43.819139 Creating /var/lib/lava/dispatcher/tmp/10591280/lava-overlay-e8qt1y2h/lava-10591280/bin/lava-test-reference
147 11:18:43.819307 Creating /var/lib/lava/dispatcher/tmp/10591280/lava-overlay-e8qt1y2h/lava-10591280/bin/lava-test-runner
148 11:18:43.819476 Creating /var/lib/lava/dispatcher/tmp/10591280/lava-overlay-e8qt1y2h/lava-10591280/bin/lava-test-set
149 11:18:43.819646 Creating /var/lib/lava/dispatcher/tmp/10591280/lava-overlay-e8qt1y2h/lava-10591280/bin/lava-test-shell
150 11:18:43.819819 Updating /var/lib/lava/dispatcher/tmp/10591280/lava-overlay-e8qt1y2h/lava-10591280/bin/lava-install-packages (oe)
151 11:18:43.820015 Updating /var/lib/lava/dispatcher/tmp/10591280/lava-overlay-e8qt1y2h/lava-10591280/bin/lava-installed-packages (oe)
152 11:18:43.820175 Creating /var/lib/lava/dispatcher/tmp/10591280/lava-overlay-e8qt1y2h/lava-10591280/environment
153 11:18:43.820350 LAVA metadata
154 11:18:43.820458 - LAVA_JOB_ID=10591280
155 11:18:43.820563 - LAVA_DISPATCHER_IP=192.168.201.1
156 11:18:43.820713 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 11:18:43.820813 skipped lava-vland-overlay
158 11:18:43.820934 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 11:18:43.821059 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 11:18:43.821156 skipped lava-multinode-overlay
161 11:18:43.821277 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 11:18:43.821403 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 11:18:43.821517 Loading test definitions
164 11:18:43.821652 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 11:18:43.821767 Using /lava-10591280 at stage 0
166 11:18:43.822179 uuid=10591280_1.5.2.3.1 testdef=None
167 11:18:43.822302 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 11:18:43.822430 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 11:18:43.822984 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 11:18:43.823232 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 11:18:43.823850 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 11:18:43.824110 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 11:18:43.824721 runner path: /var/lib/lava/dispatcher/tmp/10591280/lava-overlay-e8qt1y2h/lava-10591280/0/tests/0_v4l2-compliance-mtk-vcodec-enc test_uuid 10591280_1.5.2.3.1
176 11:18:43.824885 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 11:18:43.825214 Creating lava-test-runner.conf files
179 11:18:43.825299 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10591280/lava-overlay-e8qt1y2h/lava-10591280/0 for stage 0
180 11:18:43.825412 - 0_v4l2-compliance-mtk-vcodec-enc
181 11:18:43.825549 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 11:18:43.825650 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 11:18:43.832212 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 11:18:43.832325 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 11:18:43.832458 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 11:18:43.832560 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 11:18:43.832667 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 11:18:44.530545 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 11:18:44.530926 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 11:18:44.531059 extracting modules file /var/lib/lava/dispatcher/tmp/10591280/tftp-deploy-_r2evtbo/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10591280/extract-overlay-ramdisk-a7_emoev/ramdisk
191 11:18:44.737262 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 11:18:44.737431 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 11:18:44.737531 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10591280/compress-overlay-en6z69j0/overlay-1.5.2.4.tar.gz to ramdisk
194 11:18:44.737605 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10591280/compress-overlay-en6z69j0/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10591280/extract-overlay-ramdisk-a7_emoev/ramdisk
195 11:18:44.743883 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 11:18:44.743998 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 11:18:44.744090 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 11:18:44.744179 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 11:18:44.744257 Building ramdisk /var/lib/lava/dispatcher/tmp/10591280/extract-overlay-ramdisk-a7_emoev/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10591280/extract-overlay-ramdisk-a7_emoev/ramdisk
200 11:18:45.327671 >> 230336 blocks
201 11:18:49.308266 rename /var/lib/lava/dispatcher/tmp/10591280/extract-overlay-ramdisk-a7_emoev/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10591280/tftp-deploy-_r2evtbo/ramdisk/ramdisk.cpio.gz
202 11:18:49.308688 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 11:18:49.308805 start: 1.5.8 prepare-kernel (timeout 00:09:54) [common]
204 11:18:49.308907 start: 1.5.8.1 prepare-fit (timeout 00:09:54) [common]
205 11:18:49.309022 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10591280/tftp-deploy-_r2evtbo/kernel/Image'
206 11:19:01.143629 Returned 0 in 11 seconds
207 11:19:01.244209 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10591280/tftp-deploy-_r2evtbo/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10591280/tftp-deploy-_r2evtbo/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10591280/tftp-deploy-_r2evtbo/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10591280/tftp-deploy-_r2evtbo/kernel/image.itb
208 11:19:01.803619 output: FIT description: Kernel Image image with one or more FDT blobs
209 11:19:01.803979 output: Created: Mon Jun 5 12:19:01 2023
210 11:19:01.804069 output: Image 0 (kernel-1)
211 11:19:01.804138 output: Description:
212 11:19:01.804203 output: Created: Mon Jun 5 12:19:01 2023
213 11:19:01.804269 output: Type: Kernel Image
214 11:19:01.804330 output: Compression: lzma compressed
215 11:19:01.804392 output: Data Size: 10086024 Bytes = 9849.63 KiB = 9.62 MiB
216 11:19:01.804451 output: Architecture: AArch64
217 11:19:01.804509 output: OS: Linux
218 11:19:01.804568 output: Load Address: 0x00000000
219 11:19:01.804627 output: Entry Point: 0x00000000
220 11:19:01.804683 output: Hash algo: crc32
221 11:19:01.804738 output: Hash value: eb1cf9b8
222 11:19:01.804792 output: Image 1 (fdt-1)
223 11:19:01.804845 output: Description: mt8192-asurada-spherion-r0
224 11:19:01.804899 output: Created: Mon Jun 5 12:19:01 2023
225 11:19:01.804954 output: Type: Flat Device Tree
226 11:19:01.805007 output: Compression: uncompressed
227 11:19:01.805060 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
228 11:19:01.805114 output: Architecture: AArch64
229 11:19:01.805167 output: Hash algo: crc32
230 11:19:01.805220 output: Hash value: 1df858fa
231 11:19:01.805273 output: Image 2 (ramdisk-1)
232 11:19:01.805325 output: Description: unavailable
233 11:19:01.805382 output: Created: Mon Jun 5 12:19:01 2023
234 11:19:01.805436 output: Type: RAMDisk Image
235 11:19:01.805489 output: Compression: Unknown Compression
236 11:19:01.805542 output: Data Size: 40125206 Bytes = 39184.77 KiB = 38.27 MiB
237 11:19:01.805595 output: Architecture: AArch64
238 11:19:01.805647 output: OS: Linux
239 11:19:01.805700 output: Load Address: unavailable
240 11:19:01.805753 output: Entry Point: unavailable
241 11:19:01.805806 output: Hash algo: crc32
242 11:19:01.805859 output: Hash value: d53c805e
243 11:19:01.805911 output: Default Configuration: 'conf-1'
244 11:19:01.805964 output: Configuration 0 (conf-1)
245 11:19:01.806017 output: Description: mt8192-asurada-spherion-r0
246 11:19:01.806070 output: Kernel: kernel-1
247 11:19:01.806123 output: Init Ramdisk: ramdisk-1
248 11:19:01.806175 output: FDT: fdt-1
249 11:19:01.806227 output: Loadables: kernel-1
250 11:19:01.806280 output:
251 11:19:01.806468 end: 1.5.8.1 prepare-fit (duration 00:00:12) [common]
252 11:19:01.806570 end: 1.5.8 prepare-kernel (duration 00:00:12) [common]
253 11:19:01.806676 end: 1.5 prepare-tftp-overlay (duration 00:00:18) [common]
254 11:19:01.806771 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:41) [common]
255 11:19:01.806888 No LXC device requested
256 11:19:01.806969 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 11:19:01.807061 start: 1.7 deploy-device-env (timeout 00:09:41) [common]
258 11:19:01.807140 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 11:19:01.807212 Checking files for TFTP limit of 4294967296 bytes.
260 11:19:01.807707 end: 1 tftp-deploy (duration 00:00:19) [common]
261 11:19:01.807808 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 11:19:01.807898 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 11:19:01.808016 substitutions:
264 11:19:01.808083 - {DTB}: 10591280/tftp-deploy-_r2evtbo/dtb/mt8192-asurada-spherion-r0.dtb
265 11:19:01.808150 - {INITRD}: 10591280/tftp-deploy-_r2evtbo/ramdisk/ramdisk.cpio.gz
266 11:19:01.808210 - {KERNEL}: 10591280/tftp-deploy-_r2evtbo/kernel/Image
267 11:19:01.808268 - {LAVA_MAC}: None
268 11:19:01.808325 - {PRESEED_CONFIG}: None
269 11:19:01.808381 - {PRESEED_LOCAL}: None
270 11:19:01.808436 - {RAMDISK}: 10591280/tftp-deploy-_r2evtbo/ramdisk/ramdisk.cpio.gz
271 11:19:01.808491 - {ROOT_PART}: None
272 11:19:01.808555 - {ROOT}: None
273 11:19:01.808619 - {SERVER_IP}: 192.168.201.1
274 11:19:01.808674 - {TEE}: None
275 11:19:01.808729 Parsed boot commands:
276 11:19:01.808783 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 11:19:01.808951 Parsed boot commands: tftpboot 192.168.201.1 10591280/tftp-deploy-_r2evtbo/kernel/image.itb 10591280/tftp-deploy-_r2evtbo/kernel/cmdline
278 11:19:01.809041 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 11:19:01.809124 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 11:19:01.809216 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 11:19:01.809301 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 11:19:01.809371 Not connected, no need to disconnect.
283 11:19:01.809445 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 11:19:01.809526 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 11:19:01.809596 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-8'
286 11:19:01.812788 Setting prompt string to ['lava-test: # ']
287 11:19:01.813121 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 11:19:01.813242 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 11:19:01.813376 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 11:19:01.813470 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 11:19:01.813665 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=reboot'
292 11:19:06.953033 >> Command sent successfully.
293 11:19:06.967094 Returned 0 in 5 seconds
294 11:19:07.068454 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 11:19:07.071235 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 11:19:07.071924 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 11:19:07.072611 Setting prompt string to 'Starting depthcharge on Spherion...'
299 11:19:07.073092 Changing prompt to 'Starting depthcharge on Spherion...'
300 11:19:07.073504 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 11:19:07.074768 [Enter `^Ec?' for help]
302 11:19:07.228726
303 11:19:07.228871
304 11:19:07.228944 F0: 102B 0000
305 11:19:07.229011
306 11:19:07.229077 F3: 1001 0000 [0200]
307 11:19:07.231942
308 11:19:07.232019 F3: 1001 0000
309 11:19:07.232091
310 11:19:07.232152 F7: 102D 0000
311 11:19:07.232210
312 11:19:07.235858 F1: 0000 0000
313 11:19:07.235937
314 11:19:07.236002 V0: 0000 0000 [0001]
315 11:19:07.236070
316 11:19:07.238697 00: 0007 8000
317 11:19:07.238803
318 11:19:07.238917 01: 0000 0000
319 11:19:07.238987
320 11:19:07.242286 BP: 0C00 0209 [0000]
321 11:19:07.242361
322 11:19:07.242422 G0: 1182 0000
323 11:19:07.242487
324 11:19:07.245832 EC: 0000 0021 [4000]
325 11:19:07.245908
326 11:19:07.245970 S7: 0000 0000 [0000]
327 11:19:07.246029
328 11:19:07.249647 CC: 0000 0000 [0001]
329 11:19:07.249722
330 11:19:07.249785 T0: 0000 0040 [010F]
331 11:19:07.249852
332 11:19:07.249911 Jump to BL
333 11:19:07.249967
334 11:19:07.275981
335 11:19:07.276070
336 11:19:07.276136
337 11:19:07.283651 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 11:19:07.287509 ARM64: Exception handlers installed.
339 11:19:07.290432 ARM64: Testing exception
340 11:19:07.294129 ARM64: Done test exception
341 11:19:07.300699 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 11:19:07.310651 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 11:19:07.317428 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 11:19:07.327273 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 11:19:07.333968 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 11:19:07.340872 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 11:19:07.352563 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 11:19:07.359369 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 11:19:07.378577 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 11:19:07.381968 WDT: Last reset was cold boot
351 11:19:07.385423 SPI1(PAD0) initialized at 2873684 Hz
352 11:19:07.388435 SPI5(PAD0) initialized at 992727 Hz
353 11:19:07.392041 VBOOT: Loading verstage.
354 11:19:07.398716 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 11:19:07.401732 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 11:19:07.405275 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 11:19:07.408320 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 11:19:07.416380 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 11:19:07.422741 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 11:19:07.433847 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 11:19:07.433939
362 11:19:07.434005
363 11:19:07.443589 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 11:19:07.447000 ARM64: Exception handlers installed.
365 11:19:07.450355 ARM64: Testing exception
366 11:19:07.453370 ARM64: Done test exception
367 11:19:07.458200 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 11:19:07.461502 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 11:19:07.474522 Probing TPM: . done!
370 11:19:07.474603 TPM ready after 0 ms
371 11:19:07.481424 Connected to device vid:did:rid of 1ae0:0028:00
372 11:19:07.491359 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
373 11:19:07.530565 Initialized TPM device CR50 revision 0
374 11:19:07.542591 tlcl_send_startup: Startup return code is 0
375 11:19:07.542683 TPM: setup succeeded
376 11:19:07.553487 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 11:19:07.562656 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 11:19:07.573762 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 11:19:07.583615 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 11:19:07.586557 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 11:19:07.590262 in-header: 03 07 00 00 08 00 00 00
382 11:19:07.593715 in-data: aa e4 47 04 13 02 00 00
383 11:19:07.597890 Chrome EC: UHEPI supported
384 11:19:07.601462 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 11:19:07.605902 in-header: 03 9d 00 00 08 00 00 00
386 11:19:07.609351 in-data: 10 20 20 08 00 00 00 00
387 11:19:07.609441 Phase 1
388 11:19:07.616701 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 11:19:07.620086 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 11:19:07.627143 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 11:19:07.627227 Recovery requested (1009000e)
392 11:19:07.636574 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 11:19:07.641708 tlcl_extend: response is 0
394 11:19:07.650351 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 11:19:07.655243 tlcl_extend: response is 0
396 11:19:07.661939 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 11:19:07.683020 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
398 11:19:07.690129 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 11:19:07.690213
400 11:19:07.690279
401 11:19:07.701328 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 11:19:07.701414 ARM64: Exception handlers installed.
403 11:19:07.704862 ARM64: Testing exception
404 11:19:07.707936 ARM64: Done test exception
405 11:19:07.728651 pmic_efuse_setting: Set efuses in 11 msecs
406 11:19:07.732265 pmwrap_interface_init: Select PMIF_VLD_RDY
407 11:19:07.738315 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 11:19:07.742313 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 11:19:07.745768 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 11:19:07.752695 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 11:19:07.756251 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 11:19:07.760057 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 11:19:07.767353 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 11:19:07.770612 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 11:19:07.774177 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 11:19:07.780840 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 11:19:07.784175 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 11:19:07.791004 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 11:19:07.794089 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 11:19:07.800296 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 11:19:07.807442 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 11:19:07.810274 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 11:19:07.816714 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 11:19:07.823343 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 11:19:07.826900 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 11:19:07.834066 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 11:19:07.840962 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 11:19:07.844979 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 11:19:07.851509 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 11:19:07.855054 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 11:19:07.861757 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 11:19:07.868631 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 11:19:07.871347 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 11:19:07.878822 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 11:19:07.882655 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 11:19:07.885447 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 11:19:07.892510 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 11:19:07.896107 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 11:19:07.903597 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 11:19:07.907039 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 11:19:07.910918 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 11:19:07.918325 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 11:19:07.922016 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 11:19:07.928597 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 11:19:07.931623 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 11:19:07.935110 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 11:19:07.941800 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 11:19:07.944760 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 11:19:07.948401 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 11:19:07.954940 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 11:19:07.957956 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 11:19:07.961543 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 11:19:07.964908 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 11:19:07.971649 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 11:19:07.975097 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 11:19:07.978097 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 11:19:07.981549 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 11:19:07.991184 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 11:19:07.997824 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 11:19:08.004497 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 11:19:08.011484 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 11:19:08.021185 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 11:19:08.024571 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 11:19:08.031144 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 11:19:08.034646 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 11:19:08.041127 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6f, sec=0x0
467 11:19:08.047626 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 11:19:08.050586 [RTC]rtc_osc_init,62: osc32con val = 0xde6f
469 11:19:08.054046 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 11:19:08.064967 [RTC]rtc_get_frequency_meter,154: input=15, output=793
471 11:19:08.068624 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6f
472 11:19:08.075070 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
473 11:19:08.078343 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
474 11:19:08.081803 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
475 11:19:08.085035 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
476 11:19:08.088546 ADC[4]: Raw value=896300 ID=7
477 11:19:08.091725 ADC[3]: Raw value=213810 ID=1
478 11:19:08.095116 RAM Code: 0x71
479 11:19:08.098404 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
480 11:19:08.101892 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
481 11:19:08.112018 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
482 11:19:08.118793 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
483 11:19:08.122476 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
484 11:19:08.126039 in-header: 03 07 00 00 08 00 00 00
485 11:19:08.128895 in-data: aa e4 47 04 13 02 00 00
486 11:19:08.132648 Chrome EC: UHEPI supported
487 11:19:08.138969 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
488 11:19:08.143138 in-header: 03 d5 00 00 08 00 00 00
489 11:19:08.143224 in-data: 98 20 60 08 00 00 00 00
490 11:19:08.146314 MRC: failed to locate region type 0.
491 11:19:08.153485 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
492 11:19:08.157282 DRAM-K: Running full calibration
493 11:19:08.164134 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
494 11:19:08.164220 header.status = 0x0
495 11:19:08.167349 header.version = 0x6 (expected: 0x6)
496 11:19:08.170771 header.size = 0xd00 (expected: 0xd00)
497 11:19:08.173728 header.flags = 0x0
498 11:19:08.180842 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
499 11:19:08.197127 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
500 11:19:08.204028 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
501 11:19:08.207456 dram_init: ddr_geometry: 2
502 11:19:08.210425 [EMI] MDL number = 2
503 11:19:08.210513 [EMI] Get MDL freq = 0
504 11:19:08.214236 dram_init: ddr_type: 0
505 11:19:08.214321 is_discrete_lpddr4: 1
506 11:19:08.217213 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
507 11:19:08.217300
508 11:19:08.217367
509 11:19:08.220530 [Bian_co] ETT version 0.0.0.1
510 11:19:08.227561 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
511 11:19:08.227647
512 11:19:08.230635 dramc_set_vcore_voltage set vcore to 650000
513 11:19:08.233983 Read voltage for 800, 4
514 11:19:08.234068 Vio18 = 0
515 11:19:08.234138 Vcore = 650000
516 11:19:08.236940 Vdram = 0
517 11:19:08.237025 Vddq = 0
518 11:19:08.237093 Vmddr = 0
519 11:19:08.240704 dram_init: config_dvfs: 1
520 11:19:08.243653 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
521 11:19:08.250507 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
522 11:19:08.253525 [SwImpedanceCal] DRVP=7, DRVN=17, ODTN=9
523 11:19:08.257079 freq_region=0, Reg: DRVP=7, DRVN=17, ODTN=9
524 11:19:08.260124 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
525 11:19:08.267231 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
526 11:19:08.267319 MEM_TYPE=3, freq_sel=18
527 11:19:08.270038 sv_algorithm_assistance_LP4_1600
528 11:19:08.273632 ============ PULL DRAM RESETB DOWN ============
529 11:19:08.280205 ========== PULL DRAM RESETB DOWN end =========
530 11:19:08.283169 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
531 11:19:08.286908 ===================================
532 11:19:08.290207 LPDDR4 DRAM CONFIGURATION
533 11:19:08.293342 ===================================
534 11:19:08.293427 EX_ROW_EN[0] = 0x0
535 11:19:08.296796 EX_ROW_EN[1] = 0x0
536 11:19:08.296882 LP4Y_EN = 0x0
537 11:19:08.300384 WORK_FSP = 0x0
538 11:19:08.300469 WL = 0x2
539 11:19:08.303827 RL = 0x2
540 11:19:08.303950 BL = 0x2
541 11:19:08.306968 RPST = 0x0
542 11:19:08.307053 RD_PRE = 0x0
543 11:19:08.310307 WR_PRE = 0x1
544 11:19:08.310392 WR_PST = 0x0
545 11:19:08.313592 DBI_WR = 0x0
546 11:19:08.313677 DBI_RD = 0x0
547 11:19:08.317112 OTF = 0x1
548 11:19:08.320180 ===================================
549 11:19:08.324069 ===================================
550 11:19:08.324154 ANA top config
551 11:19:08.327624 ===================================
552 11:19:08.331110 DLL_ASYNC_EN = 0
553 11:19:08.334755 ALL_SLAVE_EN = 1
554 11:19:08.334900 NEW_RANK_MODE = 1
555 11:19:08.338285 DLL_IDLE_MODE = 1
556 11:19:08.342249 LP45_APHY_COMB_EN = 1
557 11:19:08.342334 TX_ODT_DIS = 1
558 11:19:08.345953 NEW_8X_MODE = 1
559 11:19:08.349220 ===================================
560 11:19:08.353295 ===================================
561 11:19:08.357042 data_rate = 1600
562 11:19:08.359989 CKR = 1
563 11:19:08.360074 DQ_P2S_RATIO = 8
564 11:19:08.364021 ===================================
565 11:19:08.368035 CA_P2S_RATIO = 8
566 11:19:08.371556 DQ_CA_OPEN = 0
567 11:19:08.371642 DQ_SEMI_OPEN = 0
568 11:19:08.375248 CA_SEMI_OPEN = 0
569 11:19:08.378982 CA_FULL_RATE = 0
570 11:19:08.382620 DQ_CKDIV4_EN = 1
571 11:19:08.382706 CA_CKDIV4_EN = 1
572 11:19:08.386188 CA_PREDIV_EN = 0
573 11:19:08.389824 PH8_DLY = 0
574 11:19:08.393931 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
575 11:19:08.394083 DQ_AAMCK_DIV = 4
576 11:19:08.397521 CA_AAMCK_DIV = 4
577 11:19:08.400787 CA_ADMCK_DIV = 4
578 11:19:08.404605 DQ_TRACK_CA_EN = 0
579 11:19:08.404703 CA_PICK = 800
580 11:19:08.408389 CA_MCKIO = 800
581 11:19:08.412464 MCKIO_SEMI = 0
582 11:19:08.415680 PLL_FREQ = 3068
583 11:19:08.418977 DQ_UI_PI_RATIO = 32
584 11:19:08.419063 CA_UI_PI_RATIO = 0
585 11:19:08.422246 ===================================
586 11:19:08.425193 ===================================
587 11:19:08.428851 memory_type:LPDDR4
588 11:19:08.432200 GP_NUM : 10
589 11:19:08.432289 SRAM_EN : 1
590 11:19:08.435549 MD32_EN : 0
591 11:19:08.438267 ===================================
592 11:19:08.442074 [ANA_INIT] >>>>>>>>>>>>>>
593 11:19:08.444933 <<<<<< [CONFIGURE PHASE]: ANA_TX
594 11:19:08.448333 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
595 11:19:08.451820 ===================================
596 11:19:08.455206 data_rate = 1600,PCW = 0X7600
597 11:19:08.458296 ===================================
598 11:19:08.461232 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
599 11:19:08.464838 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
600 11:19:08.471430 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
601 11:19:08.474763 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
602 11:19:08.478341 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
603 11:19:08.481415 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
604 11:19:08.484940 [ANA_INIT] flow start
605 11:19:08.488594 [ANA_INIT] PLL >>>>>>>>
606 11:19:08.488679 [ANA_INIT] PLL <<<<<<<<
607 11:19:08.492683 [ANA_INIT] MIDPI >>>>>>>>
608 11:19:08.492768 [ANA_INIT] MIDPI <<<<<<<<
609 11:19:08.495719 [ANA_INIT] DLL >>>>>>>>
610 11:19:08.499402 [ANA_INIT] flow end
611 11:19:08.503005 ============ LP4 DIFF to SE enter ============
612 11:19:08.507175 ============ LP4 DIFF to SE exit ============
613 11:19:08.510522 [ANA_INIT] <<<<<<<<<<<<<
614 11:19:08.514119 [Flow] Enable top DCM control >>>>>
615 11:19:08.514204 [Flow] Enable top DCM control <<<<<
616 11:19:08.517725 Enable DLL master slave shuffle
617 11:19:08.524958 ==============================================================
618 11:19:08.525049 Gating Mode config
619 11:19:08.531602 ==============================================================
620 11:19:08.531688 Config description:
621 11:19:08.541511 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
622 11:19:08.548471 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
623 11:19:08.555009 SELPH_MODE 0: By rank 1: By Phase
624 11:19:08.557797 ==============================================================
625 11:19:08.561046 GAT_TRACK_EN = 1
626 11:19:08.564649 RX_GATING_MODE = 2
627 11:19:08.567612 RX_GATING_TRACK_MODE = 2
628 11:19:08.571295 SELPH_MODE = 1
629 11:19:08.574250 PICG_EARLY_EN = 1
630 11:19:08.577773 VALID_LAT_VALUE = 1
631 11:19:08.584500 ==============================================================
632 11:19:08.587498 Enter into Gating configuration >>>>
633 11:19:08.591241 Exit from Gating configuration <<<<
634 11:19:08.594157 Enter into DVFS_PRE_config >>>>>
635 11:19:08.604224 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
636 11:19:08.607813 Exit from DVFS_PRE_config <<<<<
637 11:19:08.610818 Enter into PICG configuration >>>>
638 11:19:08.614248 Exit from PICG configuration <<<<
639 11:19:08.617511 [RX_INPUT] configuration >>>>>
640 11:19:08.617598 [RX_INPUT] configuration <<<<<
641 11:19:08.624041 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
642 11:19:08.630752 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
643 11:19:08.634203 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
644 11:19:08.640521 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
645 11:19:08.647505 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
646 11:19:08.654259 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
647 11:19:08.657088 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
648 11:19:08.660429 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
649 11:19:08.667363 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
650 11:19:08.670336 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
651 11:19:08.673819 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
652 11:19:08.680364 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
653 11:19:08.683942 ===================================
654 11:19:08.684022 LPDDR4 DRAM CONFIGURATION
655 11:19:08.686861 ===================================
656 11:19:08.690535 EX_ROW_EN[0] = 0x0
657 11:19:08.693510 EX_ROW_EN[1] = 0x0
658 11:19:08.693592 LP4Y_EN = 0x0
659 11:19:08.697165 WORK_FSP = 0x0
660 11:19:08.697244 WL = 0x2
661 11:19:08.700639 RL = 0x2
662 11:19:08.700720 BL = 0x2
663 11:19:08.703870 RPST = 0x0
664 11:19:08.703952 RD_PRE = 0x0
665 11:19:08.707283 WR_PRE = 0x1
666 11:19:08.707364 WR_PST = 0x0
667 11:19:08.710239 DBI_WR = 0x0
668 11:19:08.710319 DBI_RD = 0x0
669 11:19:08.713931 OTF = 0x1
670 11:19:08.716905 ===================================
671 11:19:08.720338 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
672 11:19:08.724145 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
673 11:19:08.730274 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
674 11:19:08.733409 ===================================
675 11:19:08.733485 LPDDR4 DRAM CONFIGURATION
676 11:19:08.737000 ===================================
677 11:19:08.740136 EX_ROW_EN[0] = 0x10
678 11:19:08.740211 EX_ROW_EN[1] = 0x0
679 11:19:08.743522 LP4Y_EN = 0x0
680 11:19:08.743594 WORK_FSP = 0x0
681 11:19:08.746915 WL = 0x2
682 11:19:08.750216 RL = 0x2
683 11:19:08.750288 BL = 0x2
684 11:19:08.753672 RPST = 0x0
685 11:19:08.753743 RD_PRE = 0x0
686 11:19:08.756450 WR_PRE = 0x1
687 11:19:08.756525 WR_PST = 0x0
688 11:19:08.760044 DBI_WR = 0x0
689 11:19:08.760117 DBI_RD = 0x0
690 11:19:08.763299 OTF = 0x1
691 11:19:08.766790 ===================================
692 11:19:08.772941 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
693 11:19:08.776423 nWR fixed to 40
694 11:19:08.776501 [ModeRegInit_LP4] CH0 RK0
695 11:19:08.780079 [ModeRegInit_LP4] CH0 RK1
696 11:19:08.783051 [ModeRegInit_LP4] CH1 RK0
697 11:19:08.783124 [ModeRegInit_LP4] CH1 RK1
698 11:19:08.786661 match AC timing 13
699 11:19:08.789704 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
700 11:19:08.793258 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
701 11:19:08.800576 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
702 11:19:08.804627 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
703 11:19:08.808203 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
704 11:19:08.811761 [EMI DOE] emi_dcm 0
705 11:19:08.815321 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
706 11:19:08.815402 ==
707 11:19:08.818925 Dram Type= 6, Freq= 0, CH_0, rank 0
708 11:19:08.822522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
709 11:19:08.822600 ==
710 11:19:08.830247 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
711 11:19:08.833655 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
712 11:19:08.843241 [CA 0] Center 38 (7~69) winsize 63
713 11:19:08.847126 [CA 1] Center 37 (7~68) winsize 62
714 11:19:08.850614 [CA 2] Center 35 (5~66) winsize 62
715 11:19:08.854041 [CA 3] Center 35 (5~66) winsize 62
716 11:19:08.857949 [CA 4] Center 34 (4~65) winsize 62
717 11:19:08.861421 [CA 5] Center 34 (4~65) winsize 62
718 11:19:08.861502
719 11:19:08.865470 [CmdBusTrainingLP45] Vref(ca) range 1: 32
720 11:19:08.865547
721 11:19:08.869349 [CATrainingPosCal] consider 1 rank data
722 11:19:08.869427 u2DelayCellTimex100 = 270/100 ps
723 11:19:08.872910 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
724 11:19:08.876395 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
725 11:19:08.880437 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
726 11:19:08.883592 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
727 11:19:08.887770 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
728 11:19:08.891342 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
729 11:19:08.891421
730 11:19:08.894994 CA PerBit enable=1, Macro0, CA PI delay=34
731 11:19:08.898620
732 11:19:08.898705 [CBTSetCACLKResult] CA Dly = 34
733 11:19:08.902455 CS Dly: 6 (0~37)
734 11:19:08.902539 ==
735 11:19:08.905831 Dram Type= 6, Freq= 0, CH_0, rank 1
736 11:19:08.909442 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
737 11:19:08.909527 ==
738 11:19:08.913158 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
739 11:19:08.920401 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
740 11:19:08.929976 [CA 0] Center 38 (7~69) winsize 63
741 11:19:08.933634 [CA 1] Center 38 (7~69) winsize 63
742 11:19:08.937282 [CA 2] Center 35 (5~66) winsize 62
743 11:19:08.940807 [CA 3] Center 35 (5~66) winsize 62
744 11:19:08.944638 [CA 4] Center 34 (4~65) winsize 62
745 11:19:08.948408 [CA 5] Center 34 (4~65) winsize 62
746 11:19:08.948493
747 11:19:08.951632 [CmdBusTrainingLP45] Vref(ca) range 1: 34
748 11:19:08.951726
749 11:19:08.956008 [CATrainingPosCal] consider 2 rank data
750 11:19:08.956093 u2DelayCellTimex100 = 270/100 ps
751 11:19:08.959384 CA0 delay=38 (7~69),Diff = 4 PI (28 cell)
752 11:19:08.966540 CA1 delay=37 (7~68),Diff = 3 PI (21 cell)
753 11:19:08.966626 CA2 delay=35 (5~66),Diff = 1 PI (7 cell)
754 11:19:08.970017 CA3 delay=35 (5~66),Diff = 1 PI (7 cell)
755 11:19:08.974035 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
756 11:19:08.977583 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
757 11:19:08.977668
758 11:19:08.984496 CA PerBit enable=1, Macro0, CA PI delay=34
759 11:19:08.984602
760 11:19:08.984697 [CBTSetCACLKResult] CA Dly = 34
761 11:19:08.988900 CS Dly: 6 (0~38)
762 11:19:08.988977
763 11:19:08.992279 ----->DramcWriteLeveling(PI) begin...
764 11:19:08.992387 ==
765 11:19:08.995767 Dram Type= 6, Freq= 0, CH_0, rank 0
766 11:19:08.999532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
767 11:19:08.999647 ==
768 11:19:09.003332 Write leveling (Byte 0): 34 => 34
769 11:19:09.006808 Write leveling (Byte 1): 29 => 29
770 11:19:09.006937 DramcWriteLeveling(PI) end<-----
771 11:19:09.007053
772 11:19:09.007151 ==
773 11:19:09.010485 Dram Type= 6, Freq= 0, CH_0, rank 0
774 11:19:09.014482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
775 11:19:09.017855 ==
776 11:19:09.017940 [Gating] SW mode calibration
777 11:19:09.025148 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
778 11:19:09.032269 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
779 11:19:09.035947 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
780 11:19:09.039673 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
781 11:19:09.043205 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
782 11:19:09.046716 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
783 11:19:09.054257 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
784 11:19:09.058086 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
785 11:19:09.061849 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
786 11:19:09.065870 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
787 11:19:09.069558 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
788 11:19:09.076978 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
789 11:19:09.080574 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 11:19:09.084138 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 11:19:09.088026 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 11:19:09.091322 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 11:19:09.095429 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 11:19:09.102620 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 11:19:09.106272 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 11:19:09.109991 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
797 11:19:09.113442 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
798 11:19:09.120167 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
799 11:19:09.123776 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 11:19:09.126985 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 11:19:09.133357 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 11:19:09.136956 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
803 11:19:09.139912 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 11:19:09.146577 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 11:19:09.150219 0 9 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 11:19:09.153220 0 9 12 | B1->B0 | 2424 2e2e | 0 0 | (0 0) (0 0)
807 11:19:09.160102 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
808 11:19:09.163259 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
809 11:19:09.166408 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
810 11:19:09.173149 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
811 11:19:09.176658 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
812 11:19:09.179518 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
813 11:19:09.182845 0 10 8 | B1->B0 | 3434 2f2f | 1 0 | (1 0) (1 0)
814 11:19:09.189683 0 10 12 | B1->B0 | 3030 2828 | 1 1 | (1 0) (1 0)
815 11:19:09.193064 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 11:19:09.199607 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
817 11:19:09.202872 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
818 11:19:09.206419 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
819 11:19:09.209606 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 11:19:09.216200 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 11:19:09.219104 0 11 8 | B1->B0 | 2424 2e2e | 0 0 | (0 0) (0 0)
822 11:19:09.222577 0 11 12 | B1->B0 | 3333 4242 | 0 0 | (0 0) (0 0)
823 11:19:09.229105 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
824 11:19:09.232929 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
825 11:19:09.235714 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
826 11:19:09.242274 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
827 11:19:09.245879 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
828 11:19:09.249503 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
829 11:19:09.256141 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
830 11:19:09.259171 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
831 11:19:09.262516 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
832 11:19:09.269109 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
833 11:19:09.272640 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
834 11:19:09.275783 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
835 11:19:09.282527 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
836 11:19:09.286003 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
837 11:19:09.288851 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
838 11:19:09.295743 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 11:19:09.298935 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 11:19:09.302153 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 11:19:09.309282 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 11:19:09.312145 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 11:19:09.315493 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 11:19:09.322400 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 11:19:09.325441 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 11:19:09.329014 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
847 11:19:09.332131 Total UI for P1: 0, mck2ui 16
848 11:19:09.335572 best dqsien dly found for B0: ( 0, 14, 10)
849 11:19:09.338621 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
850 11:19:09.342265 Total UI for P1: 0, mck2ui 16
851 11:19:09.345979 best dqsien dly found for B1: ( 0, 14, 12)
852 11:19:09.352390 best DQS0 dly(MCK, UI, PI) = (0, 14, 10)
853 11:19:09.355367 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
854 11:19:09.355464
855 11:19:09.359036 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 10)
856 11:19:09.362108 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
857 11:19:09.365722 [Gating] SW calibration Done
858 11:19:09.365818 ==
859 11:19:09.368762 Dram Type= 6, Freq= 0, CH_0, rank 0
860 11:19:09.371977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
861 11:19:09.372073 ==
862 11:19:09.375364 RX Vref Scan: 0
863 11:19:09.375432
864 11:19:09.375493 RX Vref 0 -> 0, step: 1
865 11:19:09.375552
866 11:19:09.378631 RX Delay -130 -> 252, step: 16
867 11:19:09.381965 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
868 11:19:09.388461 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
869 11:19:09.391813 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
870 11:19:09.395183 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
871 11:19:09.398460 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
872 11:19:09.401929 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
873 11:19:09.408863 iDelay=222, Bit 6, Center 85 (-34 ~ 205) 240
874 11:19:09.411783 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
875 11:19:09.415312 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
876 11:19:09.418711 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
877 11:19:09.422338 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
878 11:19:09.428516 iDelay=222, Bit 11, Center 61 (-66 ~ 189) 256
879 11:19:09.432187 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
880 11:19:09.435291 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
881 11:19:09.438315 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
882 11:19:09.441998 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
883 11:19:09.445047 ==
884 11:19:09.445145 Dram Type= 6, Freq= 0, CH_0, rank 0
885 11:19:09.452216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
886 11:19:09.452316 ==
887 11:19:09.452409 DQS Delay:
888 11:19:09.455498 DQS0 = 0, DQS1 = 0
889 11:19:09.455594 DQM Delay:
890 11:19:09.458334 DQM0 = 81, DQM1 = 69
891 11:19:09.458408 DQ Delay:
892 11:19:09.461916 DQ0 =77, DQ1 =85, DQ2 =77, DQ3 =77
893 11:19:09.464942 DQ4 =85, DQ5 =69, DQ6 =85, DQ7 =93
894 11:19:09.468710 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =61
895 11:19:09.472156 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
896 11:19:09.472226
897 11:19:09.472287
898 11:19:09.472346 ==
899 11:19:09.475366 Dram Type= 6, Freq= 0, CH_0, rank 0
900 11:19:09.479114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
901 11:19:09.479183 ==
902 11:19:09.479289
903 11:19:09.479389
904 11:19:09.481972 TX Vref Scan disable
905 11:19:09.482041 == TX Byte 0 ==
906 11:19:09.488570 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
907 11:19:09.492056 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
908 11:19:09.492157 == TX Byte 1 ==
909 11:19:09.498522 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
910 11:19:09.502125 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
911 11:19:09.502224 ==
912 11:19:09.505382 Dram Type= 6, Freq= 0, CH_0, rank 0
913 11:19:09.508757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
914 11:19:09.508857 ==
915 11:19:09.523364 TX Vref=22, minBit 1, minWin=26, winSum=432
916 11:19:09.526339 TX Vref=24, minBit 1, minWin=27, winSum=439
917 11:19:09.529856 TX Vref=26, minBit 5, minWin=27, winSum=444
918 11:19:09.532935 TX Vref=28, minBit 4, minWin=27, winSum=443
919 11:19:09.536463 TX Vref=30, minBit 5, minWin=27, winSum=442
920 11:19:09.543235 TX Vref=32, minBit 10, minWin=26, winSum=440
921 11:19:09.546178 [TxChooseVref] Worse bit 5, Min win 27, Win sum 444, Final Vref 26
922 11:19:09.546275
923 11:19:09.550010 Final TX Range 1 Vref 26
924 11:19:09.550084
925 11:19:09.550148 ==
926 11:19:09.552943 Dram Type= 6, Freq= 0, CH_0, rank 0
927 11:19:09.556619 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
928 11:19:09.559691 ==
929 11:19:09.559793
930 11:19:09.559885
931 11:19:09.559974 TX Vref Scan disable
932 11:19:09.563308 == TX Byte 0 ==
933 11:19:09.566870 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
934 11:19:09.573797 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
935 11:19:09.573899 == TX Byte 1 ==
936 11:19:09.576713 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
937 11:19:09.583128 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
938 11:19:09.583205
939 11:19:09.583272 [DATLAT]
940 11:19:09.583339 Freq=800, CH0 RK0
941 11:19:09.583440
942 11:19:09.586568 DATLAT Default: 0xa
943 11:19:09.586668 0, 0xFFFF, sum = 0
944 11:19:09.590165 1, 0xFFFF, sum = 0
945 11:19:09.590254 2, 0xFFFF, sum = 0
946 11:19:09.593535 3, 0xFFFF, sum = 0
947 11:19:09.596678 4, 0xFFFF, sum = 0
948 11:19:09.596782 5, 0xFFFF, sum = 0
949 11:19:09.600094 6, 0xFFFF, sum = 0
950 11:19:09.600167 7, 0xFFFF, sum = 0
951 11:19:09.603325 8, 0xFFFF, sum = 0
952 11:19:09.603396 9, 0x0, sum = 1
953 11:19:09.606587 10, 0x0, sum = 2
954 11:19:09.606688 11, 0x0, sum = 3
955 11:19:09.606782 12, 0x0, sum = 4
956 11:19:09.610008 best_step = 10
957 11:19:09.610083
958 11:19:09.610147 ==
959 11:19:09.613325 Dram Type= 6, Freq= 0, CH_0, rank 0
960 11:19:09.616614 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
961 11:19:09.616690 ==
962 11:19:09.619958 RX Vref Scan: 1
963 11:19:09.620054
964 11:19:09.620144 Set Vref Range= 32 -> 127
965 11:19:09.623559
966 11:19:09.623628 RX Vref 32 -> 127, step: 1
967 11:19:09.623689
968 11:19:09.626761 RX Delay -111 -> 252, step: 8
969 11:19:09.626885
970 11:19:09.629810 Set Vref, RX VrefLevel [Byte0]: 32
971 11:19:09.633265 [Byte1]: 32
972 11:19:09.633365
973 11:19:09.636539 Set Vref, RX VrefLevel [Byte0]: 33
974 11:19:09.640064 [Byte1]: 33
975 11:19:09.644340
976 11:19:09.644411 Set Vref, RX VrefLevel [Byte0]: 34
977 11:19:09.647376 [Byte1]: 34
978 11:19:09.651542
979 11:19:09.651612 Set Vref, RX VrefLevel [Byte0]: 35
980 11:19:09.655102 [Byte1]: 35
981 11:19:09.659303
982 11:19:09.659375 Set Vref, RX VrefLevel [Byte0]: 36
983 11:19:09.662368 [Byte1]: 36
984 11:19:09.667070
985 11:19:09.667141 Set Vref, RX VrefLevel [Byte0]: 37
986 11:19:09.670118 [Byte1]: 37
987 11:19:09.674440
988 11:19:09.674537 Set Vref, RX VrefLevel [Byte0]: 38
989 11:19:09.678053 [Byte1]: 38
990 11:19:09.682283
991 11:19:09.682354 Set Vref, RX VrefLevel [Byte0]: 39
992 11:19:09.685813 [Byte1]: 39
993 11:19:09.689790
994 11:19:09.689886 Set Vref, RX VrefLevel [Byte0]: 40
995 11:19:09.693381 [Byte1]: 40
996 11:19:09.697359
997 11:19:09.697459 Set Vref, RX VrefLevel [Byte0]: 41
998 11:19:09.700825 [Byte1]: 41
999 11:19:09.705313
1000 11:19:09.705416 Set Vref, RX VrefLevel [Byte0]: 42
1001 11:19:09.708177 [Byte1]: 42
1002 11:19:09.712503
1003 11:19:09.712610 Set Vref, RX VrefLevel [Byte0]: 43
1004 11:19:09.715891 [Byte1]: 43
1005 11:19:09.720370
1006 11:19:09.720470 Set Vref, RX VrefLevel [Byte0]: 44
1007 11:19:09.723715 [Byte1]: 44
1008 11:19:09.727972
1009 11:19:09.728071 Set Vref, RX VrefLevel [Byte0]: 45
1010 11:19:09.731556 [Byte1]: 45
1011 11:19:09.736272
1012 11:19:09.736370 Set Vref, RX VrefLevel [Byte0]: 46
1013 11:19:09.739558 [Byte1]: 46
1014 11:19:09.743823
1015 11:19:09.743893 Set Vref, RX VrefLevel [Byte0]: 47
1016 11:19:09.747144 [Byte1]: 47
1017 11:19:09.751379
1018 11:19:09.751450 Set Vref, RX VrefLevel [Byte0]: 48
1019 11:19:09.755141 [Byte1]: 48
1020 11:19:09.759213
1021 11:19:09.759283 Set Vref, RX VrefLevel [Byte0]: 49
1022 11:19:09.762798 [Byte1]: 49
1023 11:19:09.766468
1024 11:19:09.766535 Set Vref, RX VrefLevel [Byte0]: 50
1025 11:19:09.769502 [Byte1]: 50
1026 11:19:09.773667
1027 11:19:09.773763 Set Vref, RX VrefLevel [Byte0]: 51
1028 11:19:09.777311 [Byte1]: 51
1029 11:19:09.781519
1030 11:19:09.781591 Set Vref, RX VrefLevel [Byte0]: 52
1031 11:19:09.784573 [Byte1]: 52
1032 11:19:09.789328
1033 11:19:09.789421 Set Vref, RX VrefLevel [Byte0]: 53
1034 11:19:09.792329 [Byte1]: 53
1035 11:19:09.796947
1036 11:19:09.797043 Set Vref, RX VrefLevel [Byte0]: 54
1037 11:19:09.800073 [Byte1]: 54
1038 11:19:09.804545
1039 11:19:09.804621 Set Vref, RX VrefLevel [Byte0]: 55
1040 11:19:09.807991 [Byte1]: 55
1041 11:19:09.811994
1042 11:19:09.812072 Set Vref, RX VrefLevel [Byte0]: 56
1043 11:19:09.815677 [Byte1]: 56
1044 11:19:09.819517
1045 11:19:09.819589 Set Vref, RX VrefLevel [Byte0]: 57
1046 11:19:09.822902 [Byte1]: 57
1047 11:19:09.827492
1048 11:19:09.827560 Set Vref, RX VrefLevel [Byte0]: 58
1049 11:19:09.830626 [Byte1]: 58
1050 11:19:09.834814
1051 11:19:09.834924 Set Vref, RX VrefLevel [Byte0]: 59
1052 11:19:09.838260 [Byte1]: 59
1053 11:19:09.842517
1054 11:19:09.842612 Set Vref, RX VrefLevel [Byte0]: 60
1055 11:19:09.845726 [Byte1]: 60
1056 11:19:09.850215
1057 11:19:09.850312 Set Vref, RX VrefLevel [Byte0]: 61
1058 11:19:09.853580 [Byte1]: 61
1059 11:19:09.857982
1060 11:19:09.858055 Set Vref, RX VrefLevel [Byte0]: 62
1061 11:19:09.861093 [Byte1]: 62
1062 11:19:09.865902
1063 11:19:09.865971 Set Vref, RX VrefLevel [Byte0]: 63
1064 11:19:09.868971 [Byte1]: 63
1065 11:19:09.873103
1066 11:19:09.873168 Set Vref, RX VrefLevel [Byte0]: 64
1067 11:19:09.876894 [Byte1]: 64
1068 11:19:09.880962
1069 11:19:09.881029 Set Vref, RX VrefLevel [Byte0]: 65
1070 11:19:09.883966 [Byte1]: 65
1071 11:19:09.888851
1072 11:19:09.888963 Set Vref, RX VrefLevel [Byte0]: 66
1073 11:19:09.892151 [Byte1]: 66
1074 11:19:09.895983
1075 11:19:09.896137 Set Vref, RX VrefLevel [Byte0]: 67
1076 11:19:09.899587 [Byte1]: 67
1077 11:19:09.903986
1078 11:19:09.904094 Set Vref, RX VrefLevel [Byte0]: 68
1079 11:19:09.907491 [Byte1]: 68
1080 11:19:09.911349
1081 11:19:09.911470 Set Vref, RX VrefLevel [Byte0]: 69
1082 11:19:09.914774 [Byte1]: 69
1083 11:19:09.918949
1084 11:19:09.919063 Set Vref, RX VrefLevel [Byte0]: 70
1085 11:19:09.922367 [Byte1]: 70
1086 11:19:09.926906
1087 11:19:09.927062 Set Vref, RX VrefLevel [Byte0]: 71
1088 11:19:09.930311 [Byte1]: 71
1089 11:19:09.934766
1090 11:19:09.934884 Set Vref, RX VrefLevel [Byte0]: 72
1091 11:19:09.937581 [Byte1]: 72
1092 11:19:09.941944
1093 11:19:09.942045 Set Vref, RX VrefLevel [Byte0]: 73
1094 11:19:09.945376 [Byte1]: 73
1095 11:19:09.950115
1096 11:19:09.950193 Set Vref, RX VrefLevel [Byte0]: 74
1097 11:19:09.952878 [Byte1]: 74
1098 11:19:09.957482
1099 11:19:09.957553 Set Vref, RX VrefLevel [Byte0]: 75
1100 11:19:09.961029 [Byte1]: 75
1101 11:19:09.965193
1102 11:19:09.965275 Set Vref, RX VrefLevel [Byte0]: 76
1103 11:19:09.968219 [Byte1]: 76
1104 11:19:09.973003
1105 11:19:09.973085 Set Vref, RX VrefLevel [Byte0]: 77
1106 11:19:09.976045 [Byte1]: 77
1107 11:19:09.980181
1108 11:19:09.980288 Set Vref, RX VrefLevel [Byte0]: 78
1109 11:19:09.983884 [Byte1]: 78
1110 11:19:09.988004
1111 11:19:09.988086 Final RX Vref Byte 0 = 59 to rank0
1112 11:19:09.991044 Final RX Vref Byte 1 = 61 to rank0
1113 11:19:09.994632 Final RX Vref Byte 0 = 59 to rank1
1114 11:19:09.997640 Final RX Vref Byte 1 = 61 to rank1==
1115 11:19:10.001205 Dram Type= 6, Freq= 0, CH_0, rank 0
1116 11:19:10.007886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1117 11:19:10.007969 ==
1118 11:19:10.008062 DQS Delay:
1119 11:19:10.011566 DQS0 = 0, DQS1 = 0
1120 11:19:10.011651 DQM Delay:
1121 11:19:10.011718 DQM0 = 81, DQM1 = 68
1122 11:19:10.014403 DQ Delay:
1123 11:19:10.017893 DQ0 =80, DQ1 =84, DQ2 =80, DQ3 =80
1124 11:19:10.021608 DQ4 =80, DQ5 =68, DQ6 =88, DQ7 =92
1125 11:19:10.024206 DQ8 =60, DQ9 =56, DQ10 =68, DQ11 =60
1126 11:19:10.027676 DQ12 =76, DQ13 =72, DQ14 =76, DQ15 =76
1127 11:19:10.027759
1128 11:19:10.027824
1129 11:19:10.033967 [DQSOSCAuto] RK0, (LSB)MR18= 0x2525, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 400 ps
1130 11:19:10.037800 CH0 RK0: MR19=606, MR18=2525
1131 11:19:10.044376 CH0_RK0: MR19=0x606, MR18=0x2525, DQSOSC=400, MR23=63, INC=92, DEC=61
1132 11:19:10.044487
1133 11:19:10.047767 ----->DramcWriteLeveling(PI) begin...
1134 11:19:10.047853 ==
1135 11:19:10.050976 Dram Type= 6, Freq= 0, CH_0, rank 1
1136 11:19:10.054696 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1137 11:19:10.054781 ==
1138 11:19:10.057493 Write leveling (Byte 0): 34 => 34
1139 11:19:10.061021 Write leveling (Byte 1): 30 => 30
1140 11:19:10.064003 DramcWriteLeveling(PI) end<-----
1141 11:19:10.064086
1142 11:19:10.064152 ==
1143 11:19:10.067521 Dram Type= 6, Freq= 0, CH_0, rank 1
1144 11:19:10.070510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1145 11:19:10.070595 ==
1146 11:19:10.073796 [Gating] SW mode calibration
1147 11:19:10.080947 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1148 11:19:10.087483 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1149 11:19:10.090499 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1150 11:19:10.097163 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1151 11:19:10.100817 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1152 11:19:10.103635 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 11:19:10.110297 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 11:19:10.113704 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 11:19:10.117096 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 11:19:10.123779 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 11:19:10.126755 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1158 11:19:10.130265 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1159 11:19:10.133783 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 11:19:10.140118 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 11:19:10.143461 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 11:19:10.146777 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 11:19:10.194507 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 11:19:10.194598 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 11:19:10.194868 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 11:19:10.194950 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1167 11:19:10.195012 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1168 11:19:10.195750 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 11:19:10.195817 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 11:19:10.196055 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 11:19:10.196131 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 11:19:10.196369 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 11:19:10.238205 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 11:19:10.238291 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 11:19:10.238983 0 9 8 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
1176 11:19:10.239243 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1177 11:19:10.239324 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1178 11:19:10.239604 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1179 11:19:10.239670 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1180 11:19:10.239730 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1181 11:19:10.239788 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1182 11:19:10.240022 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (0 1)
1183 11:19:10.243271 0 10 8 | B1->B0 | 3333 2b2b | 0 0 | (0 1) (1 0)
1184 11:19:10.246403 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1185 11:19:10.249643 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 11:19:10.253089 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 11:19:10.259794 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 11:19:10.263065 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1189 11:19:10.266458 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1190 11:19:10.273568 0 11 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
1191 11:19:10.276234 0 11 8 | B1->B0 | 3030 4242 | 0 0 | (0 0) (0 0)
1192 11:19:10.279823 0 11 12 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
1193 11:19:10.286275 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1194 11:19:10.289759 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1195 11:19:10.292734 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1196 11:19:10.296334 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1197 11:19:10.302889 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1198 11:19:10.306442 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1199 11:19:10.310562 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1200 11:19:10.314073 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 11:19:10.320732 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 11:19:10.324365 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 11:19:10.327871 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 11:19:10.334417 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 11:19:10.337833 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1206 11:19:10.340892 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1207 11:19:10.347403 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1208 11:19:10.350806 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1209 11:19:10.353863 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1210 11:19:10.360963 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1211 11:19:10.364371 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1212 11:19:10.367064 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1213 11:19:10.374112 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 11:19:10.376843 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1215 11:19:10.380787 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1216 11:19:10.387621 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1217 11:19:10.387704 Total UI for P1: 0, mck2ui 16
1218 11:19:10.390548 best dqsien dly found for B0: ( 0, 14, 6)
1219 11:19:10.393762 Total UI for P1: 0, mck2ui 16
1220 11:19:10.397359 best dqsien dly found for B1: ( 0, 14, 10)
1221 11:19:10.404214 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1222 11:19:10.407059 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1223 11:19:10.407141
1224 11:19:10.410072 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1225 11:19:10.413754 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1226 11:19:10.417156 [Gating] SW calibration Done
1227 11:19:10.417240 ==
1228 11:19:10.420162 Dram Type= 6, Freq= 0, CH_0, rank 1
1229 11:19:10.423737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1230 11:19:10.423813 ==
1231 11:19:10.426696 RX Vref Scan: 0
1232 11:19:10.426811
1233 11:19:10.426936 RX Vref 0 -> 0, step: 1
1234 11:19:10.427016
1235 11:19:10.430136 RX Delay -130 -> 252, step: 16
1236 11:19:10.433763 iDelay=222, Bit 0, Center 77 (-50 ~ 205) 256
1237 11:19:10.440433 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1238 11:19:10.443241 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1239 11:19:10.446910 iDelay=222, Bit 3, Center 69 (-50 ~ 189) 240
1240 11:19:10.450154 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1241 11:19:10.453605 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1242 11:19:10.460121 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1243 11:19:10.463545 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1244 11:19:10.466939 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1245 11:19:10.470327 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
1246 11:19:10.473763 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1247 11:19:10.480480 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1248 11:19:10.483537 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1249 11:19:10.487018 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1250 11:19:10.489913 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1251 11:19:10.493787 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1252 11:19:10.496635 ==
1253 11:19:10.496717 Dram Type= 6, Freq= 0, CH_0, rank 1
1254 11:19:10.503574 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1255 11:19:10.503658 ==
1256 11:19:10.503724 DQS Delay:
1257 11:19:10.506708 DQS0 = 0, DQS1 = 0
1258 11:19:10.506790 DQM Delay:
1259 11:19:10.510174 DQM0 = 78, DQM1 = 71
1260 11:19:10.510256 DQ Delay:
1261 11:19:10.513186 DQ0 =77, DQ1 =77, DQ2 =69, DQ3 =69
1262 11:19:10.516977 DQ4 =77, DQ5 =69, DQ6 =93, DQ7 =93
1263 11:19:10.519724 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
1264 11:19:10.523188 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1265 11:19:10.523271
1266 11:19:10.523336
1267 11:19:10.523396 ==
1268 11:19:10.526228 Dram Type= 6, Freq= 0, CH_0, rank 1
1269 11:19:10.529748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1270 11:19:10.529832 ==
1271 11:19:10.529897
1272 11:19:10.529958
1273 11:19:10.533233 TX Vref Scan disable
1274 11:19:10.536327 == TX Byte 0 ==
1275 11:19:10.540036 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1276 11:19:10.543150 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1277 11:19:10.546517 == TX Byte 1 ==
1278 11:19:10.549487 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1279 11:19:10.552954 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1280 11:19:10.553038 ==
1281 11:19:10.556608 Dram Type= 6, Freq= 0, CH_0, rank 1
1282 11:19:10.559534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1283 11:19:10.563085 ==
1284 11:19:10.574587 TX Vref=22, minBit 0, minWin=27, winSum=433
1285 11:19:10.577873 TX Vref=24, minBit 1, minWin=27, winSum=439
1286 11:19:10.581342 TX Vref=26, minBit 1, minWin=27, winSum=442
1287 11:19:10.584900 TX Vref=28, minBit 1, minWin=27, winSum=443
1288 11:19:10.587900 TX Vref=30, minBit 2, minWin=27, winSum=444
1289 11:19:10.594445 TX Vref=32, minBit 9, minWin=27, winSum=443
1290 11:19:10.597869 [TxChooseVref] Worse bit 2, Min win 27, Win sum 444, Final Vref 30
1291 11:19:10.597953
1292 11:19:10.601162 Final TX Range 1 Vref 30
1293 11:19:10.601244
1294 11:19:10.601308 ==
1295 11:19:10.604783 Dram Type= 6, Freq= 0, CH_0, rank 1
1296 11:19:10.607725 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1297 11:19:10.607807 ==
1298 11:19:10.611231
1299 11:19:10.611312
1300 11:19:10.611376 TX Vref Scan disable
1301 11:19:10.614767 == TX Byte 0 ==
1302 11:19:10.617820 Update DQ dly =584 (2 ,1, 40) DQ OEN =(1 ,6)
1303 11:19:10.624779 Update DQM dly =584 (2 ,1, 40) DQM OEN =(1 ,6)
1304 11:19:10.624860 == TX Byte 1 ==
1305 11:19:10.628000 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1306 11:19:10.631498 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1307 11:19:10.634396
1308 11:19:10.634473 [DATLAT]
1309 11:19:10.634549 Freq=800, CH0 RK1
1310 11:19:10.634612
1311 11:19:10.637827 DATLAT Default: 0xa
1312 11:19:10.637923 0, 0xFFFF, sum = 0
1313 11:19:10.641385 1, 0xFFFF, sum = 0
1314 11:19:10.641481 2, 0xFFFF, sum = 0
1315 11:19:10.644340 3, 0xFFFF, sum = 0
1316 11:19:10.644434 4, 0xFFFF, sum = 0
1317 11:19:10.647994 5, 0xFFFF, sum = 0
1318 11:19:10.651414 6, 0xFFFF, sum = 0
1319 11:19:10.651496 7, 0xFFFF, sum = 0
1320 11:19:10.654885 8, 0xFFFF, sum = 0
1321 11:19:10.654967 9, 0x0, sum = 1
1322 11:19:10.655033 10, 0x0, sum = 2
1323 11:19:10.657816 11, 0x0, sum = 3
1324 11:19:10.657924 12, 0x0, sum = 4
1325 11:19:10.661307 best_step = 10
1326 11:19:10.661387
1327 11:19:10.661450 ==
1328 11:19:10.665013 Dram Type= 6, Freq= 0, CH_0, rank 1
1329 11:19:10.667878 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1330 11:19:10.667959 ==
1331 11:19:10.671463 RX Vref Scan: 0
1332 11:19:10.671543
1333 11:19:10.671607 RX Vref 0 -> 0, step: 1
1334 11:19:10.671666
1335 11:19:10.674549 RX Delay -111 -> 252, step: 8
1336 11:19:10.681518 iDelay=209, Bit 0, Center 80 (-39 ~ 200) 240
1337 11:19:10.684690 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1338 11:19:10.687925 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1339 11:19:10.691193 iDelay=209, Bit 3, Center 72 (-47 ~ 192) 240
1340 11:19:10.694617 iDelay=209, Bit 4, Center 80 (-39 ~ 200) 240
1341 11:19:10.701199 iDelay=209, Bit 5, Center 64 (-55 ~ 184) 240
1342 11:19:10.704587 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1343 11:19:10.708079 iDelay=209, Bit 7, Center 88 (-31 ~ 208) 240
1344 11:19:10.711233 iDelay=209, Bit 8, Center 64 (-55 ~ 184) 240
1345 11:19:10.714856 iDelay=209, Bit 9, Center 56 (-63 ~ 176) 240
1346 11:19:10.720886 iDelay=209, Bit 10, Center 72 (-47 ~ 192) 240
1347 11:19:10.724561 iDelay=209, Bit 11, Center 64 (-55 ~ 184) 240
1348 11:19:10.727657 iDelay=209, Bit 12, Center 72 (-47 ~ 192) 240
1349 11:19:10.730864 iDelay=209, Bit 13, Center 76 (-39 ~ 192) 232
1350 11:19:10.737407 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
1351 11:19:10.741042 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
1352 11:19:10.741123 ==
1353 11:19:10.744501 Dram Type= 6, Freq= 0, CH_0, rank 1
1354 11:19:10.747496 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1355 11:19:10.747578 ==
1356 11:19:10.751244 DQS Delay:
1357 11:19:10.751324 DQS0 = 0, DQS1 = 0
1358 11:19:10.751387 DQM Delay:
1359 11:19:10.754152 DQM0 = 79, DQM1 = 70
1360 11:19:10.754233 DQ Delay:
1361 11:19:10.757829 DQ0 =80, DQ1 =84, DQ2 =76, DQ3 =72
1362 11:19:10.760976 DQ4 =80, DQ5 =64, DQ6 =88, DQ7 =88
1363 11:19:10.763940 DQ8 =64, DQ9 =56, DQ10 =72, DQ11 =64
1364 11:19:10.767507 DQ12 =72, DQ13 =76, DQ14 =80, DQ15 =80
1365 11:19:10.767588
1366 11:19:10.767651
1367 11:19:10.776983 [DQSOSCAuto] RK1, (LSB)MR18= 0x4520, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 392 ps
1368 11:19:10.780531 CH0 RK1: MR19=606, MR18=4520
1369 11:19:10.784142 CH0_RK1: MR19=0x606, MR18=0x4520, DQSOSC=392, MR23=63, INC=96, DEC=64
1370 11:19:10.787268 [RxdqsGatingPostProcess] freq 800
1371 11:19:10.793845 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1372 11:19:10.797200 Pre-setting of DQS Precalculation
1373 11:19:10.800565 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1374 11:19:10.800646 ==
1375 11:19:10.804011 Dram Type= 6, Freq= 0, CH_1, rank 0
1376 11:19:10.810715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1377 11:19:10.810800 ==
1378 11:19:10.814110 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1379 11:19:10.820150 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1380 11:19:10.830007 [CA 0] Center 36 (6~67) winsize 62
1381 11:19:10.832977 [CA 1] Center 36 (6~67) winsize 62
1382 11:19:10.836609 [CA 2] Center 34 (4~64) winsize 61
1383 11:19:10.839609 [CA 3] Center 34 (4~64) winsize 61
1384 11:19:10.843213 [CA 4] Center 34 (4~64) winsize 61
1385 11:19:10.846684 [CA 5] Center 33 (3~64) winsize 62
1386 11:19:10.846767
1387 11:19:10.849685 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1388 11:19:10.849768
1389 11:19:10.853285 [CATrainingPosCal] consider 1 rank data
1390 11:19:10.856250 u2DelayCellTimex100 = 270/100 ps
1391 11:19:10.859811 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1392 11:19:10.866164 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1393 11:19:10.869591 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1394 11:19:10.873057 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1395 11:19:10.876047 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
1396 11:19:10.879816 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1397 11:19:10.879900
1398 11:19:10.882762 CA PerBit enable=1, Macro0, CA PI delay=33
1399 11:19:10.882880
1400 11:19:10.885856 [CBTSetCACLKResult] CA Dly = 33
1401 11:19:10.885939 CS Dly: 5 (0~36)
1402 11:19:10.889435 ==
1403 11:19:10.893035 Dram Type= 6, Freq= 0, CH_1, rank 1
1404 11:19:10.895999 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1405 11:19:10.896082 ==
1406 11:19:10.899238 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1407 11:19:10.905936 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1408 11:19:10.915921 [CA 0] Center 37 (7~67) winsize 61
1409 11:19:10.919380 [CA 1] Center 36 (6~67) winsize 62
1410 11:19:10.922222 [CA 2] Center 34 (4~65) winsize 62
1411 11:19:10.925771 [CA 3] Center 34 (4~64) winsize 61
1412 11:19:10.928945 [CA 4] Center 34 (4~65) winsize 62
1413 11:19:10.932207 [CA 5] Center 33 (3~64) winsize 62
1414 11:19:10.932290
1415 11:19:10.935846 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1416 11:19:10.935929
1417 11:19:10.939081 [CATrainingPosCal] consider 2 rank data
1418 11:19:10.942126 u2DelayCellTimex100 = 270/100 ps
1419 11:19:10.945808 CA0 delay=37 (7~67),Diff = 4 PI (28 cell)
1420 11:19:10.952163 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1421 11:19:10.955781 CA2 delay=34 (4~64),Diff = 1 PI (7 cell)
1422 11:19:10.958860 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1423 11:19:10.962338 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
1424 11:19:10.965772 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1425 11:19:10.965856
1426 11:19:10.969240 CA PerBit enable=1, Macro0, CA PI delay=33
1427 11:19:10.969323
1428 11:19:10.973044 [CBTSetCACLKResult] CA Dly = 33
1429 11:19:10.973128 CS Dly: 6 (0~38)
1430 11:19:10.973194
1431 11:19:10.976373 ----->DramcWriteLeveling(PI) begin...
1432 11:19:10.976457 ==
1433 11:19:10.980025 Dram Type= 6, Freq= 0, CH_1, rank 0
1434 11:19:10.984285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1435 11:19:10.984368 ==
1436 11:19:10.988208 Write leveling (Byte 0): 28 => 28
1437 11:19:10.991460 Write leveling (Byte 1): 28 => 28
1438 11:19:10.995094 DramcWriteLeveling(PI) end<-----
1439 11:19:10.995194
1440 11:19:10.995273 ==
1441 11:19:10.998767 Dram Type= 6, Freq= 0, CH_1, rank 0
1442 11:19:11.002330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1443 11:19:11.002413 ==
1444 11:19:11.005890 [Gating] SW mode calibration
1445 11:19:11.012522 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1446 11:19:11.016041 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1447 11:19:11.022454 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1448 11:19:11.025779 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1449 11:19:11.029079 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 11:19:11.035233 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 11:19:11.039411 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 11:19:11.042208 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 11:19:11.048559 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 11:19:11.052075 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1455 11:19:11.055776 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1456 11:19:11.061648 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 11:19:11.065190 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 11:19:11.068711 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 11:19:11.075407 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 11:19:11.078763 0 7 20 | B1->B0 | 2323 2323 | 0 1 | (0 0) (0 0)
1461 11:19:11.081916 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 11:19:11.088365 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 11:19:11.091956 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 11:19:11.094961 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1465 11:19:11.101504 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 1)
1466 11:19:11.105340 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1467 11:19:11.109000 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1468 11:19:11.115043 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1469 11:19:11.118421 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1470 11:19:11.121688 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1471 11:19:11.128309 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1472 11:19:11.131679 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1473 11:19:11.134989 0 9 8 | B1->B0 | 2929 2a2a | 1 0 | (0 0) (0 0)
1474 11:19:11.141143 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1475 11:19:11.144635 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1476 11:19:11.147949 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1477 11:19:11.154474 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1478 11:19:11.157908 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1479 11:19:11.161641 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1480 11:19:11.168114 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
1481 11:19:11.171464 0 10 8 | B1->B0 | 2b2b 2e2e | 0 0 | (0 0) (1 0)
1482 11:19:11.174281 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1483 11:19:11.181137 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 11:19:11.184616 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 11:19:11.187615 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 11:19:11.194628 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 11:19:11.197624 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1488 11:19:11.201200 0 11 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1489 11:19:11.207782 0 11 8 | B1->B0 | 3939 3232 | 0 1 | (0 0) (0 0)
1490 11:19:11.210784 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1491 11:19:11.214582 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1492 11:19:11.220825 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1493 11:19:11.224590 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1494 11:19:11.227524 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1495 11:19:11.234255 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1496 11:19:11.237461 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1497 11:19:11.240630 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1498 11:19:11.247326 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 11:19:11.250669 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 11:19:11.254013 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 11:19:11.260456 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 11:19:11.263916 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 11:19:11.267416 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1504 11:19:11.273967 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1505 11:19:11.277238 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1506 11:19:11.280222 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1507 11:19:11.283842 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1508 11:19:11.290398 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1509 11:19:11.293819 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1510 11:19:11.297430 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1511 11:19:11.303504 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1512 11:19:11.307019 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1513 11:19:11.310058 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1514 11:19:11.316647 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1515 11:19:11.320150 Total UI for P1: 0, mck2ui 16
1516 11:19:11.323756 best dqsien dly found for B0: ( 0, 14, 8)
1517 11:19:11.327190 Total UI for P1: 0, mck2ui 16
1518 11:19:11.330150 best dqsien dly found for B1: ( 0, 14, 8)
1519 11:19:11.333410 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
1520 11:19:11.336722 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1521 11:19:11.336805
1522 11:19:11.339986 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
1523 11:19:11.343352 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1524 11:19:11.346588 [Gating] SW calibration Done
1525 11:19:11.346671 ==
1526 11:19:11.349860 Dram Type= 6, Freq= 0, CH_1, rank 0
1527 11:19:11.353261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1528 11:19:11.353345 ==
1529 11:19:11.356541 RX Vref Scan: 0
1530 11:19:11.356623
1531 11:19:11.356689 RX Vref 0 -> 0, step: 1
1532 11:19:11.356749
1533 11:19:11.359945 RX Delay -130 -> 252, step: 16
1534 11:19:11.366850 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1535 11:19:11.370148 iDelay=222, Bit 1, Center 77 (-50 ~ 205) 256
1536 11:19:11.373417 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1537 11:19:11.376469 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1538 11:19:11.380018 iDelay=222, Bit 4, Center 77 (-50 ~ 205) 256
1539 11:19:11.386381 iDelay=222, Bit 5, Center 93 (-34 ~ 221) 256
1540 11:19:11.389999 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1541 11:19:11.393062 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1542 11:19:11.396454 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1543 11:19:11.399426 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1544 11:19:11.406253 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
1545 11:19:11.409834 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1546 11:19:11.412926 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1547 11:19:11.416507 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1548 11:19:11.419511 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1549 11:19:11.426197 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1550 11:19:11.426280 ==
1551 11:19:11.429205 Dram Type= 6, Freq= 0, CH_1, rank 0
1552 11:19:11.432786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1553 11:19:11.432871 ==
1554 11:19:11.432937 DQS Delay:
1555 11:19:11.436356 DQS0 = 0, DQS1 = 0
1556 11:19:11.436439 DQM Delay:
1557 11:19:11.439702 DQM0 = 81, DQM1 = 71
1558 11:19:11.439785 DQ Delay:
1559 11:19:11.443008 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1560 11:19:11.446147 DQ4 =77, DQ5 =93, DQ6 =93, DQ7 =77
1561 11:19:11.449484 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
1562 11:19:11.452895 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1563 11:19:11.452978
1564 11:19:11.453044
1565 11:19:11.453104 ==
1566 11:19:11.456251 Dram Type= 6, Freq= 0, CH_1, rank 0
1567 11:19:11.459558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1568 11:19:11.459666 ==
1569 11:19:11.462533
1570 11:19:11.462615
1571 11:19:11.462681 TX Vref Scan disable
1572 11:19:11.466179 == TX Byte 0 ==
1573 11:19:11.469219 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1574 11:19:11.472397 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1575 11:19:11.475952 == TX Byte 1 ==
1576 11:19:11.479255 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1577 11:19:11.482811 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1578 11:19:11.486254 ==
1579 11:19:11.486336 Dram Type= 6, Freq= 0, CH_1, rank 0
1580 11:19:11.492354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1581 11:19:11.492437 ==
1582 11:19:11.504384 TX Vref=22, minBit 1, minWin=27, winSum=439
1583 11:19:11.508088 TX Vref=24, minBit 1, minWin=26, winSum=440
1584 11:19:11.510820 TX Vref=26, minBit 4, minWin=27, winSum=445
1585 11:19:11.514466 TX Vref=28, minBit 4, minWin=27, winSum=447
1586 11:19:11.517439 TX Vref=30, minBit 4, minWin=27, winSum=445
1587 11:19:11.524004 TX Vref=32, minBit 5, minWin=27, winSum=444
1588 11:19:11.527626 [TxChooseVref] Worse bit 4, Min win 27, Win sum 447, Final Vref 28
1589 11:19:11.527710
1590 11:19:11.531299 Final TX Range 1 Vref 28
1591 11:19:11.531383
1592 11:19:11.531449 ==
1593 11:19:11.534406 Dram Type= 6, Freq= 0, CH_1, rank 0
1594 11:19:11.537567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1595 11:19:11.537651 ==
1596 11:19:11.540955
1597 11:19:11.541037
1598 11:19:11.541102 TX Vref Scan disable
1599 11:19:11.544406 == TX Byte 0 ==
1600 11:19:11.548154 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1601 11:19:11.551335 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1602 11:19:11.554836 == TX Byte 1 ==
1603 11:19:11.558136 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1604 11:19:11.561587 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1605 11:19:11.561671
1606 11:19:11.564814 [DATLAT]
1607 11:19:11.564896 Freq=800, CH1 RK0
1608 11:19:11.564962
1609 11:19:11.568274 DATLAT Default: 0xa
1610 11:19:11.568357 0, 0xFFFF, sum = 0
1611 11:19:11.571082 1, 0xFFFF, sum = 0
1612 11:19:11.571193 2, 0xFFFF, sum = 0
1613 11:19:11.574633 3, 0xFFFF, sum = 0
1614 11:19:11.574723 4, 0xFFFF, sum = 0
1615 11:19:11.578017 5, 0xFFFF, sum = 0
1616 11:19:11.578101 6, 0xFFFF, sum = 0
1617 11:19:11.581445 7, 0xFFFF, sum = 0
1618 11:19:11.581529 8, 0xFFFF, sum = 0
1619 11:19:11.584555 9, 0x0, sum = 1
1620 11:19:11.584639 10, 0x0, sum = 2
1621 11:19:11.587824 11, 0x0, sum = 3
1622 11:19:11.587909 12, 0x0, sum = 4
1623 11:19:11.591059 best_step = 10
1624 11:19:11.591141
1625 11:19:11.591207 ==
1626 11:19:11.594559 Dram Type= 6, Freq= 0, CH_1, rank 0
1627 11:19:11.597383 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1628 11:19:11.597467 ==
1629 11:19:11.600818 RX Vref Scan: 1
1630 11:19:11.600900
1631 11:19:11.600966 Set Vref Range= 32 -> 127
1632 11:19:11.601027
1633 11:19:11.604463 RX Vref 32 -> 127, step: 1
1634 11:19:11.604546
1635 11:19:11.607482 RX Delay -111 -> 252, step: 8
1636 11:19:11.607564
1637 11:19:11.611126 Set Vref, RX VrefLevel [Byte0]: 32
1638 11:19:11.614217 [Byte1]: 32
1639 11:19:11.614311
1640 11:19:11.617832 Set Vref, RX VrefLevel [Byte0]: 33
1641 11:19:11.620899 [Byte1]: 33
1642 11:19:11.625075
1643 11:19:11.625158 Set Vref, RX VrefLevel [Byte0]: 34
1644 11:19:11.628053 [Byte1]: 34
1645 11:19:11.632291
1646 11:19:11.632374 Set Vref, RX VrefLevel [Byte0]: 35
1647 11:19:11.635919 [Byte1]: 35
1648 11:19:11.640177
1649 11:19:11.640259 Set Vref, RX VrefLevel [Byte0]: 36
1650 11:19:11.643180 [Byte1]: 36
1651 11:19:11.647943
1652 11:19:11.648025 Set Vref, RX VrefLevel [Byte0]: 37
1653 11:19:11.651305 [Byte1]: 37
1654 11:19:11.655118
1655 11:19:11.655200 Set Vref, RX VrefLevel [Byte0]: 38
1656 11:19:11.658551 [Byte1]: 38
1657 11:19:11.662876
1658 11:19:11.662958 Set Vref, RX VrefLevel [Byte0]: 39
1659 11:19:11.666386 [Byte1]: 39
1660 11:19:11.670782
1661 11:19:11.670889 Set Vref, RX VrefLevel [Byte0]: 40
1662 11:19:11.674132 [Byte1]: 40
1663 11:19:11.678284
1664 11:19:11.678370 Set Vref, RX VrefLevel [Byte0]: 41
1665 11:19:11.681383 [Byte1]: 41
1666 11:19:11.686157
1667 11:19:11.686240 Set Vref, RX VrefLevel [Byte0]: 42
1668 11:19:11.689171 [Byte1]: 42
1669 11:19:11.693418
1670 11:19:11.693500 Set Vref, RX VrefLevel [Byte0]: 43
1671 11:19:11.696897 [Byte1]: 43
1672 11:19:11.701434
1673 11:19:11.701516 Set Vref, RX VrefLevel [Byte0]: 44
1674 11:19:11.704492 [Byte1]: 44
1675 11:19:11.708789
1676 11:19:11.708871 Set Vref, RX VrefLevel [Byte0]: 45
1677 11:19:11.712276 [Byte1]: 45
1678 11:19:11.716464
1679 11:19:11.716547 Set Vref, RX VrefLevel [Byte0]: 46
1680 11:19:11.720189 [Byte1]: 46
1681 11:19:11.724144
1682 11:19:11.724227 Set Vref, RX VrefLevel [Byte0]: 47
1683 11:19:11.727712 [Byte1]: 47
1684 11:19:11.731936
1685 11:19:11.732019 Set Vref, RX VrefLevel [Byte0]: 48
1686 11:19:11.735020 [Byte1]: 48
1687 11:19:11.739914
1688 11:19:11.739996 Set Vref, RX VrefLevel [Byte0]: 49
1689 11:19:11.742835 [Byte1]: 49
1690 11:19:11.747178
1691 11:19:11.747261 Set Vref, RX VrefLevel [Byte0]: 50
1692 11:19:11.750760 [Byte1]: 50
1693 11:19:11.754975
1694 11:19:11.755057 Set Vref, RX VrefLevel [Byte0]: 51
1695 11:19:11.758299 [Byte1]: 51
1696 11:19:11.762502
1697 11:19:11.762584 Set Vref, RX VrefLevel [Byte0]: 52
1698 11:19:11.766071 [Byte1]: 52
1699 11:19:11.770463
1700 11:19:11.770545 Set Vref, RX VrefLevel [Byte0]: 53
1701 11:19:11.773192 [Byte1]: 53
1702 11:19:11.777642
1703 11:19:11.777725 Set Vref, RX VrefLevel [Byte0]: 54
1704 11:19:11.780992 [Byte1]: 54
1705 11:19:11.785160
1706 11:19:11.785243 Set Vref, RX VrefLevel [Byte0]: 55
1707 11:19:11.788730 [Byte1]: 55
1708 11:19:11.792882
1709 11:19:11.792965 Set Vref, RX VrefLevel [Byte0]: 56
1710 11:19:11.796132 [Byte1]: 56
1711 11:19:11.800901
1712 11:19:11.800990 Set Vref, RX VrefLevel [Byte0]: 57
1713 11:19:11.803956 [Byte1]: 57
1714 11:19:11.808482
1715 11:19:11.808564 Set Vref, RX VrefLevel [Byte0]: 58
1716 11:19:11.811675 [Byte1]: 58
1717 11:19:11.815906
1718 11:19:11.815989 Set Vref, RX VrefLevel [Byte0]: 59
1719 11:19:11.819292 [Byte1]: 59
1720 11:19:11.823677
1721 11:19:11.823766 Set Vref, RX VrefLevel [Byte0]: 60
1722 11:19:11.827061 [Byte1]: 60
1723 11:19:11.831253
1724 11:19:11.831335 Set Vref, RX VrefLevel [Byte0]: 61
1725 11:19:11.834261 [Byte1]: 61
1726 11:19:11.839080
1727 11:19:11.839162 Set Vref, RX VrefLevel [Byte0]: 62
1728 11:19:11.842134 [Byte1]: 62
1729 11:19:11.846356
1730 11:19:11.846440 Set Vref, RX VrefLevel [Byte0]: 63
1731 11:19:11.849942 [Byte1]: 63
1732 11:19:11.854162
1733 11:19:11.854245 Set Vref, RX VrefLevel [Byte0]: 64
1734 11:19:11.857863 [Byte1]: 64
1735 11:19:11.861958
1736 11:19:11.862041 Set Vref, RX VrefLevel [Byte0]: 65
1737 11:19:11.865095 [Byte1]: 65
1738 11:19:11.869778
1739 11:19:11.869861 Set Vref, RX VrefLevel [Byte0]: 66
1740 11:19:11.872573 [Byte1]: 66
1741 11:19:11.877089
1742 11:19:11.877172 Set Vref, RX VrefLevel [Byte0]: 67
1743 11:19:11.880449 [Byte1]: 67
1744 11:19:11.884849
1745 11:19:11.884932 Set Vref, RX VrefLevel [Byte0]: 68
1746 11:19:11.888541 [Byte1]: 68
1747 11:19:11.892208
1748 11:19:11.892290 Set Vref, RX VrefLevel [Byte0]: 69
1749 11:19:11.899058 [Byte1]: 69
1750 11:19:11.899141
1751 11:19:11.902595 Set Vref, RX VrefLevel [Byte0]: 70
1752 11:19:11.905336 [Byte1]: 70
1753 11:19:11.905419
1754 11:19:11.908728 Set Vref, RX VrefLevel [Byte0]: 71
1755 11:19:11.912128 [Byte1]: 71
1756 11:19:11.915584
1757 11:19:11.915670 Set Vref, RX VrefLevel [Byte0]: 72
1758 11:19:11.918372 [Byte1]: 72
1759 11:19:11.922847
1760 11:19:11.922943 Set Vref, RX VrefLevel [Byte0]: 73
1761 11:19:11.926330 [Byte1]: 73
1762 11:19:11.930473
1763 11:19:11.930557 Final RX Vref Byte 0 = 61 to rank0
1764 11:19:11.934123 Final RX Vref Byte 1 = 53 to rank0
1765 11:19:11.937208 Final RX Vref Byte 0 = 61 to rank1
1766 11:19:11.940781 Final RX Vref Byte 1 = 53 to rank1==
1767 11:19:11.943765 Dram Type= 6, Freq= 0, CH_1, rank 0
1768 11:19:11.950370 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1769 11:19:11.950460 ==
1770 11:19:11.950528 DQS Delay:
1771 11:19:11.953963 DQS0 = 0, DQS1 = 0
1772 11:19:11.954046 DQM Delay:
1773 11:19:11.954112 DQM0 = 80, DQM1 = 71
1774 11:19:11.957019 DQ Delay:
1775 11:19:11.960615 DQ0 =84, DQ1 =76, DQ2 =68, DQ3 =76
1776 11:19:11.963532 DQ4 =80, DQ5 =92, DQ6 =92, DQ7 =76
1777 11:19:11.967154 DQ8 =60, DQ9 =64, DQ10 =72, DQ11 =64
1778 11:19:11.970675 DQ12 =80, DQ13 =76, DQ14 =76, DQ15 =76
1779 11:19:11.970758
1780 11:19:11.970823
1781 11:19:11.977160 [DQSOSCAuto] RK0, (LSB)MR18= 0xb16, (MSB)MR19= 0x606, tDQSOscB0 = 404 ps tDQSOscB1 = 407 ps
1782 11:19:11.980503 CH1 RK0: MR19=606, MR18=B16
1783 11:19:11.986657 CH1_RK0: MR19=0x606, MR18=0xB16, DQSOSC=404, MR23=63, INC=90, DEC=60
1784 11:19:11.986741
1785 11:19:11.989953 ----->DramcWriteLeveling(PI) begin...
1786 11:19:11.990037 ==
1787 11:19:11.993496 Dram Type= 6, Freq= 0, CH_1, rank 1
1788 11:19:11.996874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1789 11:19:11.996958 ==
1790 11:19:11.999991 Write leveling (Byte 0): 25 => 25
1791 11:19:12.003612 Write leveling (Byte 1): 29 => 29
1792 11:19:12.006556 DramcWriteLeveling(PI) end<-----
1793 11:19:12.006639
1794 11:19:12.006704 ==
1795 11:19:12.010231 Dram Type= 6, Freq= 0, CH_1, rank 1
1796 11:19:12.013526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1797 11:19:12.013610 ==
1798 11:19:12.016773 [Gating] SW mode calibration
1799 11:19:12.022991 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1800 11:19:12.030026 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1801 11:19:12.032981 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1802 11:19:12.039619 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1803 11:19:12.042849 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1804 11:19:12.046397 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1805 11:19:12.053055 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1806 11:19:12.056055 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1807 11:19:12.059742 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 11:19:12.066368 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 11:19:12.069414 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 11:19:12.072946 0 7 4 | B1->B0 | 2323 2322 | 0 1 | (0 0) (0 0)
1811 11:19:12.075908 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 11:19:12.082774 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 11:19:12.086217 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 11:19:12.089429 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 11:19:12.096072 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 11:19:12.099181 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 11:19:12.102360 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 11:19:12.109258 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1819 11:19:12.112486 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 11:19:12.115987 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1821 11:19:12.122754 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1822 11:19:12.125925 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 11:19:12.129071 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 11:19:12.136025 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 11:19:12.138942 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 11:19:12.142560 0 9 4 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
1827 11:19:12.149214 0 9 8 | B1->B0 | 2e2e 3434 | 1 1 | (0 0) (1 1)
1828 11:19:12.152441 0 9 12 | B1->B0 | 3434 3534 | 1 1 | (1 1) (0 0)
1829 11:19:12.155918 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1830 11:19:12.162513 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1831 11:19:12.165296 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1832 11:19:12.168870 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1833 11:19:12.175472 0 10 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
1834 11:19:12.178431 0 10 4 | B1->B0 | 3333 2e2e | 0 1 | (0 0) (1 1)
1835 11:19:12.182021 0 10 8 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
1836 11:19:12.188450 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1837 11:19:12.191732 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1838 11:19:12.195053 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1839 11:19:12.201740 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 11:19:12.205268 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 11:19:12.208678 0 11 0 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1842 11:19:12.214941 0 11 4 | B1->B0 | 2b2b 3838 | 0 0 | (0 0) (0 0)
1843 11:19:12.218457 0 11 8 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
1844 11:19:12.221865 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1845 11:19:12.228443 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1846 11:19:12.231997 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1847 11:19:12.235026 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1848 11:19:12.241515 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1849 11:19:12.244997 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1850 11:19:12.248124 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1851 11:19:12.254819 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1852 11:19:12.258034 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1853 11:19:12.261482 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1854 11:19:12.268026 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 11:19:12.271015 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 11:19:12.274801 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 11:19:12.281255 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 11:19:12.284283 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 11:19:12.287814 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 11:19:12.294211 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 11:19:12.297847 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 11:19:12.301016 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 11:19:12.307605 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 11:19:12.311039 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 11:19:12.313966 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 11:19:12.320838 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1867 11:19:12.324074 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1868 11:19:12.327530 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1869 11:19:12.331117 Total UI for P1: 0, mck2ui 16
1870 11:19:12.334107 best dqsien dly found for B0: ( 0, 14, 6)
1871 11:19:12.337635 Total UI for P1: 0, mck2ui 16
1872 11:19:12.340814 best dqsien dly found for B1: ( 0, 14, 8)
1873 11:19:12.343889 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1874 11:19:12.347652 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1875 11:19:12.347770
1876 11:19:12.350534 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1877 11:19:12.356995 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1878 11:19:12.357071 [Gating] SW calibration Done
1879 11:19:12.357170 ==
1880 11:19:12.360670 Dram Type= 6, Freq= 0, CH_1, rank 1
1881 11:19:12.367404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1882 11:19:12.367487 ==
1883 11:19:12.367563 RX Vref Scan: 0
1884 11:19:12.367623
1885 11:19:12.370393 RX Vref 0 -> 0, step: 1
1886 11:19:12.370489
1887 11:19:12.374004 RX Delay -130 -> 252, step: 16
1888 11:19:12.376996 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1889 11:19:12.380508 iDelay=222, Bit 1, Center 69 (-50 ~ 189) 240
1890 11:19:12.383606 iDelay=222, Bit 2, Center 61 (-66 ~ 189) 256
1891 11:19:12.391006 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1892 11:19:12.393780 iDelay=222, Bit 4, Center 69 (-50 ~ 189) 240
1893 11:19:12.397296 iDelay=222, Bit 5, Center 85 (-34 ~ 205) 240
1894 11:19:12.400280 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1895 11:19:12.403753 iDelay=222, Bit 7, Center 77 (-50 ~ 205) 256
1896 11:19:12.410535 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
1897 11:19:12.413899 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
1898 11:19:12.416794 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1899 11:19:12.420745 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1900 11:19:12.423418 iDelay=222, Bit 12, Center 77 (-50 ~ 205) 256
1901 11:19:12.430057 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
1902 11:19:12.433521 iDelay=222, Bit 14, Center 77 (-50 ~ 205) 256
1903 11:19:12.437210 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
1904 11:19:12.437293 ==
1905 11:19:12.439976 Dram Type= 6, Freq= 0, CH_1, rank 1
1906 11:19:12.443810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1907 11:19:12.443893 ==
1908 11:19:12.446615 DQS Delay:
1909 11:19:12.446708 DQS0 = 0, DQS1 = 0
1910 11:19:12.449999 DQM Delay:
1911 11:19:12.450081 DQM0 = 77, DQM1 = 72
1912 11:19:12.453375 DQ Delay:
1913 11:19:12.453483 DQ0 =85, DQ1 =69, DQ2 =61, DQ3 =77
1914 11:19:12.456720 DQ4 =69, DQ5 =85, DQ6 =93, DQ7 =77
1915 11:19:12.460149 DQ8 =61, DQ9 =61, DQ10 =77, DQ11 =69
1916 11:19:12.463212 DQ12 =77, DQ13 =77, DQ14 =77, DQ15 =77
1917 11:19:12.463286
1918 11:19:12.466684
1919 11:19:12.466754 ==
1920 11:19:12.469773 Dram Type= 6, Freq= 0, CH_1, rank 1
1921 11:19:12.473364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1922 11:19:12.473460 ==
1923 11:19:12.473523
1924 11:19:12.473582
1925 11:19:12.476500 TX Vref Scan disable
1926 11:19:12.476582 == TX Byte 0 ==
1927 11:19:12.483201 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1928 11:19:12.486579 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1929 11:19:12.486684 == TX Byte 1 ==
1930 11:19:12.493449 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1931 11:19:12.496927 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1932 11:19:12.497025 ==
1933 11:19:12.499824 Dram Type= 6, Freq= 0, CH_1, rank 1
1934 11:19:12.503208 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1935 11:19:12.503285 ==
1936 11:19:12.516842 TX Vref=22, minBit 9, minWin=27, winSum=452
1937 11:19:12.520493 TX Vref=24, minBit 9, minWin=28, winSum=460
1938 11:19:12.523663 TX Vref=26, minBit 3, minWin=28, winSum=458
1939 11:19:12.526775 TX Vref=28, minBit 5, minWin=28, winSum=464
1940 11:19:12.530230 TX Vref=30, minBit 5, minWin=28, winSum=465
1941 11:19:12.537012 TX Vref=32, minBit 5, minWin=28, winSum=464
1942 11:19:12.539950 [TxChooseVref] Worse bit 5, Min win 28, Win sum 465, Final Vref 30
1943 11:19:12.540053
1944 11:19:12.543419 Final TX Range 1 Vref 30
1945 11:19:12.543493
1946 11:19:12.543564 ==
1947 11:19:12.546938 Dram Type= 6, Freq= 0, CH_1, rank 1
1948 11:19:12.549920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1949 11:19:12.550017 ==
1950 11:19:12.553578
1951 11:19:12.553674
1952 11:19:12.553769 TX Vref Scan disable
1953 11:19:12.557061 == TX Byte 0 ==
1954 11:19:12.560082 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1955 11:19:12.566769 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1956 11:19:12.566851 == TX Byte 1 ==
1957 11:19:12.570320 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1958 11:19:12.577124 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1959 11:19:12.577197
1960 11:19:12.577271 [DATLAT]
1961 11:19:12.577359 Freq=800, CH1 RK1
1962 11:19:12.577444
1963 11:19:12.580209 DATLAT Default: 0xa
1964 11:19:12.580310 0, 0xFFFF, sum = 0
1965 11:19:12.583641 1, 0xFFFF, sum = 0
1966 11:19:12.583738 2, 0xFFFF, sum = 0
1967 11:19:12.586784 3, 0xFFFF, sum = 0
1968 11:19:12.589667 4, 0xFFFF, sum = 0
1969 11:19:12.589770 5, 0xFFFF, sum = 0
1970 11:19:12.593306 6, 0xFFFF, sum = 0
1971 11:19:12.593377 7, 0xFFFF, sum = 0
1972 11:19:12.596871 8, 0xFFFF, sum = 0
1973 11:19:12.596942 9, 0x0, sum = 1
1974 11:19:12.599835 10, 0x0, sum = 2
1975 11:19:12.599907 11, 0x0, sum = 3
1976 11:19:12.599966 12, 0x0, sum = 4
1977 11:19:12.603407 best_step = 10
1978 11:19:12.603483
1979 11:19:12.603546 ==
1980 11:19:12.606363 Dram Type= 6, Freq= 0, CH_1, rank 1
1981 11:19:12.609720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1982 11:19:12.609817 ==
1983 11:19:12.613293 RX Vref Scan: 0
1984 11:19:12.613380
1985 11:19:12.613443 RX Vref 0 -> 0, step: 1
1986 11:19:12.616832
1987 11:19:12.616931 RX Delay -111 -> 252, step: 8
1988 11:19:12.623399 iDelay=209, Bit 0, Center 84 (-39 ~ 208) 248
1989 11:19:12.626993 iDelay=209, Bit 1, Center 72 (-47 ~ 192) 240
1990 11:19:12.630421 iDelay=209, Bit 2, Center 68 (-55 ~ 192) 248
1991 11:19:12.633500 iDelay=209, Bit 3, Center 76 (-47 ~ 200) 248
1992 11:19:12.636782 iDelay=209, Bit 4, Center 76 (-47 ~ 200) 248
1993 11:19:12.643457 iDelay=209, Bit 5, Center 88 (-31 ~ 208) 240
1994 11:19:12.646748 iDelay=209, Bit 6, Center 88 (-31 ~ 208) 240
1995 11:19:12.650197 iDelay=209, Bit 7, Center 76 (-47 ~ 200) 248
1996 11:19:12.653303 iDelay=209, Bit 8, Center 60 (-63 ~ 184) 248
1997 11:19:12.656861 iDelay=209, Bit 9, Center 64 (-55 ~ 184) 240
1998 11:19:12.663528 iDelay=209, Bit 10, Center 80 (-39 ~ 200) 240
1999 11:19:12.666998 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
2000 11:19:12.670448 iDelay=209, Bit 12, Center 80 (-39 ~ 200) 240
2001 11:19:12.673776 iDelay=209, Bit 13, Center 80 (-39 ~ 200) 240
2002 11:19:12.680562 iDelay=209, Bit 14, Center 80 (-39 ~ 200) 240
2003 11:19:12.683496 iDelay=209, Bit 15, Center 80 (-39 ~ 200) 240
2004 11:19:12.683579 ==
2005 11:19:12.686952 Dram Type= 6, Freq= 0, CH_1, rank 1
2006 11:19:12.690033 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2007 11:19:12.690116 ==
2008 11:19:12.690181 DQS Delay:
2009 11:19:12.693616 DQS0 = 0, DQS1 = 0
2010 11:19:12.693699 DQM Delay:
2011 11:19:12.696581 DQM0 = 78, DQM1 = 74
2012 11:19:12.696664 DQ Delay:
2013 11:19:12.700204 DQ0 =84, DQ1 =72, DQ2 =68, DQ3 =76
2014 11:19:12.703193 DQ4 =76, DQ5 =88, DQ6 =88, DQ7 =76
2015 11:19:12.706813 DQ8 =60, DQ9 =64, DQ10 =80, DQ11 =68
2016 11:19:12.710741 DQ12 =80, DQ13 =80, DQ14 =80, DQ15 =80
2017 11:19:12.710824
2018 11:19:12.710925
2019 11:19:12.719765 [DQSOSCAuto] RK1, (LSB)MR18= 0x1c34, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 402 ps
2020 11:19:12.719861 CH1 RK1: MR19=606, MR18=1C34
2021 11:19:12.726521 CH1_RK1: MR19=0x606, MR18=0x1C34, DQSOSC=396, MR23=63, INC=94, DEC=62
2022 11:19:12.729988 [RxdqsGatingPostProcess] freq 800
2023 11:19:12.736688 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2024 11:19:12.739525 Pre-setting of DQS Precalculation
2025 11:19:12.743024 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2026 11:19:12.749478 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2027 11:19:12.759415 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2028 11:19:12.759498
2029 11:19:12.759564
2030 11:19:12.762891 [Calibration Summary] 1600 Mbps
2031 11:19:12.762974 CH 0, Rank 0
2032 11:19:12.766343 SW Impedance : PASS
2033 11:19:12.766426 DUTY Scan : NO K
2034 11:19:12.770117 ZQ Calibration : PASS
2035 11:19:12.770200 Jitter Meter : NO K
2036 11:19:12.772708 CBT Training : PASS
2037 11:19:12.775967 Write leveling : PASS
2038 11:19:12.776050 RX DQS gating : PASS
2039 11:19:12.779372 RX DQ/DQS(RDDQC) : PASS
2040 11:19:12.783116 TX DQ/DQS : PASS
2041 11:19:12.783200 RX DATLAT : PASS
2042 11:19:12.786013 RX DQ/DQS(Engine): PASS
2043 11:19:12.789634 TX OE : NO K
2044 11:19:12.789717 All Pass.
2045 11:19:12.789783
2046 11:19:12.789844 CH 0, Rank 1
2047 11:19:12.792586 SW Impedance : PASS
2048 11:19:12.796274 DUTY Scan : NO K
2049 11:19:12.796357 ZQ Calibration : PASS
2050 11:19:12.799298 Jitter Meter : NO K
2051 11:19:12.802894 CBT Training : PASS
2052 11:19:12.802976 Write leveling : PASS
2053 11:19:12.806142 RX DQS gating : PASS
2054 11:19:12.809566 RX DQ/DQS(RDDQC) : PASS
2055 11:19:12.809649 TX DQ/DQS : PASS
2056 11:19:12.812698 RX DATLAT : PASS
2057 11:19:12.816197 RX DQ/DQS(Engine): PASS
2058 11:19:12.816281 TX OE : NO K
2059 11:19:12.816347 All Pass.
2060 11:19:12.819096
2061 11:19:12.819178 CH 1, Rank 0
2062 11:19:12.822505 SW Impedance : PASS
2063 11:19:12.822587 DUTY Scan : NO K
2064 11:19:12.825877 ZQ Calibration : PASS
2065 11:19:12.825966 Jitter Meter : NO K
2066 11:19:12.829273 CBT Training : PASS
2067 11:19:12.832598 Write leveling : PASS
2068 11:19:12.832681 RX DQS gating : PASS
2069 11:19:12.835988 RX DQ/DQS(RDDQC) : PASS
2070 11:19:12.839304 TX DQ/DQS : PASS
2071 11:19:12.839387 RX DATLAT : PASS
2072 11:19:12.842906 RX DQ/DQS(Engine): PASS
2073 11:19:12.845965 TX OE : NO K
2074 11:19:12.846049 All Pass.
2075 11:19:12.846115
2076 11:19:12.846175 CH 1, Rank 1
2077 11:19:12.849104 SW Impedance : PASS
2078 11:19:12.852450 DUTY Scan : NO K
2079 11:19:12.852533 ZQ Calibration : PASS
2080 11:19:12.855747 Jitter Meter : NO K
2081 11:19:12.859105 CBT Training : PASS
2082 11:19:12.859187 Write leveling : PASS
2083 11:19:12.862651 RX DQS gating : PASS
2084 11:19:12.865646 RX DQ/DQS(RDDQC) : PASS
2085 11:19:12.865729 TX DQ/DQS : PASS
2086 11:19:12.869224 RX DATLAT : PASS
2087 11:19:12.872480 RX DQ/DQS(Engine): PASS
2088 11:19:12.872563 TX OE : NO K
2089 11:19:12.872629 All Pass.
2090 11:19:12.875336
2091 11:19:12.875418 DramC Write-DBI off
2092 11:19:12.878952 PER_BANK_REFRESH: Hybrid Mode
2093 11:19:12.879035 TX_TRACKING: ON
2094 11:19:12.882136 [GetDramInforAfterCalByMRR] Vendor 6.
2095 11:19:12.889119 [GetDramInforAfterCalByMRR] Revision 606.
2096 11:19:12.892083 [GetDramInforAfterCalByMRR] Revision 2 0.
2097 11:19:12.892166 MR0 0x3b3b
2098 11:19:12.892231 MR8 0x5151
2099 11:19:12.895219 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2100 11:19:12.895304
2101 11:19:12.898804 MR0 0x3b3b
2102 11:19:12.898898 MR8 0x5151
2103 11:19:12.901915 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2104 11:19:12.901998
2105 11:19:12.912252 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2106 11:19:12.915370 [FAST_K] Save calibration result to emmc
2107 11:19:12.918362 [FAST_K] Save calibration result to emmc
2108 11:19:12.921919 dram_init: config_dvfs: 1
2109 11:19:12.925771 dramc_set_vcore_voltage set vcore to 662500
2110 11:19:12.928307 Read voltage for 1200, 2
2111 11:19:12.928390 Vio18 = 0
2112 11:19:12.928456 Vcore = 662500
2113 11:19:12.931626 Vdram = 0
2114 11:19:12.931709 Vddq = 0
2115 11:19:12.931774 Vmddr = 0
2116 11:19:12.938375 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2117 11:19:12.941668 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2118 11:19:12.944908 MEM_TYPE=3, freq_sel=15
2119 11:19:12.948047 sv_algorithm_assistance_LP4_1600
2120 11:19:12.951543 ============ PULL DRAM RESETB DOWN ============
2121 11:19:12.954624 ========== PULL DRAM RESETB DOWN end =========
2122 11:19:12.961448 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2123 11:19:12.964787 ===================================
2124 11:19:12.968060 LPDDR4 DRAM CONFIGURATION
2125 11:19:12.971591 ===================================
2126 11:19:12.971674 EX_ROW_EN[0] = 0x0
2127 11:19:12.974417 EX_ROW_EN[1] = 0x0
2128 11:19:12.974500 LP4Y_EN = 0x0
2129 11:19:12.978003 WORK_FSP = 0x0
2130 11:19:12.978086 WL = 0x4
2131 11:19:12.981036 RL = 0x4
2132 11:19:12.981119 BL = 0x2
2133 11:19:12.984521 RPST = 0x0
2134 11:19:12.984603 RD_PRE = 0x0
2135 11:19:12.988070 WR_PRE = 0x1
2136 11:19:12.988153 WR_PST = 0x0
2137 11:19:12.990780 DBI_WR = 0x0
2138 11:19:12.994354 DBI_RD = 0x0
2139 11:19:12.994437 OTF = 0x1
2140 11:19:12.997775 ===================================
2141 11:19:13.000881 ===================================
2142 11:19:13.000964 ANA top config
2143 11:19:13.004414 ===================================
2144 11:19:13.007497 DLL_ASYNC_EN = 0
2145 11:19:13.010525 ALL_SLAVE_EN = 0
2146 11:19:13.014099 NEW_RANK_MODE = 1
2147 11:19:13.017124 DLL_IDLE_MODE = 1
2148 11:19:13.017234 LP45_APHY_COMB_EN = 1
2149 11:19:13.020805 TX_ODT_DIS = 1
2150 11:19:13.023888 NEW_8X_MODE = 1
2151 11:19:13.027525 ===================================
2152 11:19:13.030484 ===================================
2153 11:19:13.034181 data_rate = 2400
2154 11:19:13.036949 CKR = 1
2155 11:19:13.040461 DQ_P2S_RATIO = 8
2156 11:19:13.040545 ===================================
2157 11:19:13.043924 CA_P2S_RATIO = 8
2158 11:19:13.047210 DQ_CA_OPEN = 0
2159 11:19:13.050477 DQ_SEMI_OPEN = 0
2160 11:19:13.053809 CA_SEMI_OPEN = 0
2161 11:19:13.057207 CA_FULL_RATE = 0
2162 11:19:13.057316 DQ_CKDIV4_EN = 0
2163 11:19:13.060890 CA_CKDIV4_EN = 0
2164 11:19:13.063974 CA_PREDIV_EN = 0
2165 11:19:13.066807 PH8_DLY = 17
2166 11:19:13.070293 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2167 11:19:13.073350 DQ_AAMCK_DIV = 4
2168 11:19:13.077120 CA_AAMCK_DIV = 4
2169 11:19:13.077209 CA_ADMCK_DIV = 4
2170 11:19:13.080307 DQ_TRACK_CA_EN = 0
2171 11:19:13.083983 CA_PICK = 1200
2172 11:19:13.086764 CA_MCKIO = 1200
2173 11:19:13.090250 MCKIO_SEMI = 0
2174 11:19:13.093632 PLL_FREQ = 2366
2175 11:19:13.096948 DQ_UI_PI_RATIO = 32
2176 11:19:13.097031 CA_UI_PI_RATIO = 0
2177 11:19:13.100445 ===================================
2178 11:19:13.103405 ===================================
2179 11:19:13.107017 memory_type:LPDDR4
2180 11:19:13.110082 GP_NUM : 10
2181 11:19:13.110165 SRAM_EN : 1
2182 11:19:13.113632 MD32_EN : 0
2183 11:19:13.116687 ===================================
2184 11:19:13.119752 [ANA_INIT] >>>>>>>>>>>>>>
2185 11:19:13.123285 <<<<<< [CONFIGURE PHASE]: ANA_TX
2186 11:19:13.126346 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2187 11:19:13.129996 ===================================
2188 11:19:13.130079 data_rate = 2400,PCW = 0X5b00
2189 11:19:13.132939 ===================================
2190 11:19:13.136521 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2191 11:19:13.143200 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2192 11:19:13.149687 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2193 11:19:13.153032 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2194 11:19:13.156270 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2195 11:19:13.159796 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2196 11:19:13.162903 [ANA_INIT] flow start
2197 11:19:13.166199 [ANA_INIT] PLL >>>>>>>>
2198 11:19:13.166282 [ANA_INIT] PLL <<<<<<<<
2199 11:19:13.169558 [ANA_INIT] MIDPI >>>>>>>>
2200 11:19:13.172975 [ANA_INIT] MIDPI <<<<<<<<
2201 11:19:13.173058 [ANA_INIT] DLL >>>>>>>>
2202 11:19:13.175843 [ANA_INIT] DLL <<<<<<<<
2203 11:19:13.179344 [ANA_INIT] flow end
2204 11:19:13.182824 ============ LP4 DIFF to SE enter ============
2205 11:19:13.185893 ============ LP4 DIFF to SE exit ============
2206 11:19:13.189429 [ANA_INIT] <<<<<<<<<<<<<
2207 11:19:13.192719 [Flow] Enable top DCM control >>>>>
2208 11:19:13.196215 [Flow] Enable top DCM control <<<<<
2209 11:19:13.199219 Enable DLL master slave shuffle
2210 11:19:13.202499 ==============================================================
2211 11:19:13.205879 Gating Mode config
2212 11:19:13.212623 ==============================================================
2213 11:19:13.212706 Config description:
2214 11:19:13.222124 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2215 11:19:13.229375 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2216 11:19:13.235872 SELPH_MODE 0: By rank 1: By Phase
2217 11:19:13.238992 ==============================================================
2218 11:19:13.242573 GAT_TRACK_EN = 1
2219 11:19:13.245480 RX_GATING_MODE = 2
2220 11:19:13.248857 RX_GATING_TRACK_MODE = 2
2221 11:19:13.252397 SELPH_MODE = 1
2222 11:19:13.255218 PICG_EARLY_EN = 1
2223 11:19:13.258675 VALID_LAT_VALUE = 1
2224 11:19:13.261958 ==============================================================
2225 11:19:13.265207 Enter into Gating configuration >>>>
2226 11:19:13.268482 Exit from Gating configuration <<<<
2227 11:19:13.272249 Enter into DVFS_PRE_config >>>>>
2228 11:19:13.285459 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2229 11:19:13.288859 Exit from DVFS_PRE_config <<<<<
2230 11:19:13.292085 Enter into PICG configuration >>>>
2231 11:19:13.292169 Exit from PICG configuration <<<<
2232 11:19:13.295059 [RX_INPUT] configuration >>>>>
2233 11:19:13.298619 [RX_INPUT] configuration <<<<<
2234 11:19:13.305254 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2235 11:19:13.308609 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2236 11:19:13.314921 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2237 11:19:13.321486 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2238 11:19:13.328275 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2239 11:19:13.334977 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2240 11:19:13.337930 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2241 11:19:13.341656 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2242 11:19:13.344592 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2243 11:19:13.351407 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2244 11:19:13.355073 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2245 11:19:13.357954 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2246 11:19:13.361576 ===================================
2247 11:19:13.364819 LPDDR4 DRAM CONFIGURATION
2248 11:19:13.368154 ===================================
2249 11:19:13.371519 EX_ROW_EN[0] = 0x0
2250 11:19:13.371596 EX_ROW_EN[1] = 0x0
2251 11:19:13.374886 LP4Y_EN = 0x0
2252 11:19:13.374959 WORK_FSP = 0x0
2253 11:19:13.377710 WL = 0x4
2254 11:19:13.377793 RL = 0x4
2255 11:19:13.381068 BL = 0x2
2256 11:19:13.381152 RPST = 0x0
2257 11:19:13.384468 RD_PRE = 0x0
2258 11:19:13.384544 WR_PRE = 0x1
2259 11:19:13.387804 WR_PST = 0x0
2260 11:19:13.387880 DBI_WR = 0x0
2261 11:19:13.391080 DBI_RD = 0x0
2262 11:19:13.391156 OTF = 0x1
2263 11:19:13.394617 ===================================
2264 11:19:13.401319 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2265 11:19:13.404436 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2266 11:19:13.407955 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2267 11:19:13.410884 ===================================
2268 11:19:13.414115 LPDDR4 DRAM CONFIGURATION
2269 11:19:13.417849 ===================================
2270 11:19:13.421143 EX_ROW_EN[0] = 0x10
2271 11:19:13.421230 EX_ROW_EN[1] = 0x0
2272 11:19:13.424250 LP4Y_EN = 0x0
2273 11:19:13.424333 WORK_FSP = 0x0
2274 11:19:13.427823 WL = 0x4
2275 11:19:13.427906 RL = 0x4
2276 11:19:13.430888 BL = 0x2
2277 11:19:13.430971 RPST = 0x0
2278 11:19:13.434523 RD_PRE = 0x0
2279 11:19:13.434606 WR_PRE = 0x1
2280 11:19:13.437622 WR_PST = 0x0
2281 11:19:13.437705 DBI_WR = 0x0
2282 11:19:13.441141 DBI_RD = 0x0
2283 11:19:13.441224 OTF = 0x1
2284 11:19:13.444292 ===================================
2285 11:19:13.450758 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2286 11:19:13.450877 ==
2287 11:19:13.454361 Dram Type= 6, Freq= 0, CH_0, rank 0
2288 11:19:13.460748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2289 11:19:13.460832 ==
2290 11:19:13.460898 [Duty_Offset_Calibration]
2291 11:19:13.464619 B0:2 B1:0 CA:3
2292 11:19:13.464701
2293 11:19:13.467308 [DutyScan_Calibration_Flow] k_type=0
2294 11:19:13.476255
2295 11:19:13.476337 ==CLK 0==
2296 11:19:13.479608 Final CLK duty delay cell = 0
2297 11:19:13.483159 [0] MAX Duty = 5062%(X100), DQS PI = 20
2298 11:19:13.486422 [0] MIN Duty = 4875%(X100), DQS PI = 58
2299 11:19:13.486504 [0] AVG Duty = 4968%(X100)
2300 11:19:13.489741
2301 11:19:13.493159 CH0 CLK Duty spec in!! Max-Min= 187%
2302 11:19:13.496345 [DutyScan_Calibration_Flow] ====Done====
2303 11:19:13.496426
2304 11:19:13.499947 [DutyScan_Calibration_Flow] k_type=1
2305 11:19:13.514674
2306 11:19:13.514775 ==DQS 0 ==
2307 11:19:13.517933 Final DQS duty delay cell = 0
2308 11:19:13.521295 [0] MAX Duty = 5062%(X100), DQS PI = 12
2309 11:19:13.524676 [0] MIN Duty = 4907%(X100), DQS PI = 46
2310 11:19:13.528340 [0] AVG Duty = 4984%(X100)
2311 11:19:13.528421
2312 11:19:13.528484 ==DQS 1 ==
2313 11:19:13.531420 Final DQS duty delay cell = -4
2314 11:19:13.534526 [-4] MAX Duty = 4969%(X100), DQS PI = 22
2315 11:19:13.537973 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2316 11:19:13.541014 [-4] AVG Duty = 4938%(X100)
2317 11:19:13.541094
2318 11:19:13.544682 CH0 DQS 0 Duty spec in!! Max-Min= 155%
2319 11:19:13.544763
2320 11:19:13.548246 CH0 DQS 1 Duty spec in!! Max-Min= 62%
2321 11:19:13.551287 [DutyScan_Calibration_Flow] ====Done====
2322 11:19:13.551368
2323 11:19:13.554969 [DutyScan_Calibration_Flow] k_type=3
2324 11:19:13.571427
2325 11:19:13.571508 ==DQM 0 ==
2326 11:19:13.574893 Final DQM duty delay cell = 0
2327 11:19:13.578437 [0] MAX Duty = 5124%(X100), DQS PI = 28
2328 11:19:13.581565 [0] MIN Duty = 4876%(X100), DQS PI = 0
2329 11:19:13.584817 [0] AVG Duty = 5000%(X100)
2330 11:19:13.584893
2331 11:19:13.584964 ==DQM 1 ==
2332 11:19:13.588181 Final DQM duty delay cell = 0
2333 11:19:13.591133 [0] MAX Duty = 4969%(X100), DQS PI = 50
2334 11:19:13.594742 [0] MIN Duty = 4844%(X100), DQS PI = 16
2335 11:19:13.597981 [0] AVG Duty = 4906%(X100)
2336 11:19:13.598064
2337 11:19:13.601159 CH0 DQM 0 Duty spec in!! Max-Min= 248%
2338 11:19:13.601260
2339 11:19:13.604522 CH0 DQM 1 Duty spec in!! Max-Min= 125%
2340 11:19:13.608154 [DutyScan_Calibration_Flow] ====Done====
2341 11:19:13.608235
2342 11:19:13.611258 [DutyScan_Calibration_Flow] k_type=2
2343 11:19:13.626495
2344 11:19:13.626583 ==DQ 0 ==
2345 11:19:13.629988 Final DQ duty delay cell = -4
2346 11:19:13.632985 [-4] MAX Duty = 5031%(X100), DQS PI = 20
2347 11:19:13.636437 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2348 11:19:13.639439 [-4] AVG Duty = 4969%(X100)
2349 11:19:13.639514
2350 11:19:13.639575 ==DQ 1 ==
2351 11:19:13.643074 Final DQ duty delay cell = -4
2352 11:19:13.646636 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2353 11:19:13.649569 [-4] MIN Duty = 4876%(X100), DQS PI = 18
2354 11:19:13.653247 [-4] AVG Duty = 4938%(X100)
2355 11:19:13.653330
2356 11:19:13.656343 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2357 11:19:13.656433
2358 11:19:13.659853 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2359 11:19:13.662810 [DutyScan_Calibration_Flow] ====Done====
2360 11:19:13.662908 ==
2361 11:19:13.666346 Dram Type= 6, Freq= 0, CH_1, rank 0
2362 11:19:13.669345 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2363 11:19:13.669429 ==
2364 11:19:13.673118 [Duty_Offset_Calibration]
2365 11:19:13.673236 B0:1 B1:-2 CA:0
2366 11:19:13.673299
2367 11:19:13.676090 [DutyScan_Calibration_Flow] k_type=0
2368 11:19:13.686790
2369 11:19:13.686913 ==CLK 0==
2370 11:19:13.690050 Final CLK duty delay cell = 0
2371 11:19:13.693468 [0] MAX Duty = 5031%(X100), DQS PI = 16
2372 11:19:13.696904 [0] MIN Duty = 4844%(X100), DQS PI = 2
2373 11:19:13.697009 [0] AVG Duty = 4937%(X100)
2374 11:19:13.700240
2375 11:19:13.703644 CH1 CLK Duty spec in!! Max-Min= 187%
2376 11:19:13.706837 [DutyScan_Calibration_Flow] ====Done====
2377 11:19:13.706960
2378 11:19:13.710079 [DutyScan_Calibration_Flow] k_type=1
2379 11:19:13.725574
2380 11:19:13.725711 ==DQS 0 ==
2381 11:19:13.728711 Final DQS duty delay cell = -4
2382 11:19:13.731953 [-4] MAX Duty = 5031%(X100), DQS PI = 24
2383 11:19:13.735570 [-4] MIN Duty = 4907%(X100), DQS PI = 2
2384 11:19:13.738493 [-4] AVG Duty = 4969%(X100)
2385 11:19:13.738670
2386 11:19:13.738807 ==DQS 1 ==
2387 11:19:13.742265 Final DQS duty delay cell = 0
2388 11:19:13.745270 [0] MAX Duty = 5062%(X100), DQS PI = 0
2389 11:19:13.748966 [0] MIN Duty = 4875%(X100), DQS PI = 26
2390 11:19:13.752078 [0] AVG Duty = 4968%(X100)
2391 11:19:13.752384
2392 11:19:13.755779 CH1 DQS 0 Duty spec in!! Max-Min= 124%
2393 11:19:13.756174
2394 11:19:13.758955 CH1 DQS 1 Duty spec in!! Max-Min= 187%
2395 11:19:13.762329 [DutyScan_Calibration_Flow] ====Done====
2396 11:19:13.762921
2397 11:19:13.765431 [DutyScan_Calibration_Flow] k_type=3
2398 11:19:13.782256
2399 11:19:13.782688 ==DQM 0 ==
2400 11:19:13.785761 Final DQM duty delay cell = 0
2401 11:19:13.788834 [0] MAX Duty = 5000%(X100), DQS PI = 22
2402 11:19:13.792362 [0] MIN Duty = 4844%(X100), DQS PI = 54
2403 11:19:13.795211 [0] AVG Duty = 4922%(X100)
2404 11:19:13.795323
2405 11:19:13.795392 ==DQM 1 ==
2406 11:19:13.798481 Final DQM duty delay cell = 0
2407 11:19:13.801846 [0] MAX Duty = 5031%(X100), DQS PI = 36
2408 11:19:13.805602 [0] MIN Duty = 4907%(X100), DQS PI = 0
2409 11:19:13.808774 [0] AVG Duty = 4969%(X100)
2410 11:19:13.808855
2411 11:19:13.811591 CH1 DQM 0 Duty spec in!! Max-Min= 156%
2412 11:19:13.811673
2413 11:19:13.814885 CH1 DQM 1 Duty spec in!! Max-Min= 124%
2414 11:19:13.818671 [DutyScan_Calibration_Flow] ====Done====
2415 11:19:13.818779
2416 11:19:13.821527 [DutyScan_Calibration_Flow] k_type=2
2417 11:19:13.838183
2418 11:19:13.838264 ==DQ 0 ==
2419 11:19:13.841609 Final DQ duty delay cell = 0
2420 11:19:13.845122 [0] MAX Duty = 5062%(X100), DQS PI = 18
2421 11:19:13.848151 [0] MIN Duty = 4938%(X100), DQS PI = 56
2422 11:19:13.851787 [0] AVG Duty = 5000%(X100)
2423 11:19:13.851869
2424 11:19:13.851933 ==DQ 1 ==
2425 11:19:13.854988 Final DQ duty delay cell = 0
2426 11:19:13.858458 [0] MAX Duty = 5125%(X100), DQS PI = 36
2427 11:19:13.861629 [0] MIN Duty = 4969%(X100), DQS PI = 26
2428 11:19:13.865043 [0] AVG Duty = 5047%(X100)
2429 11:19:13.865125
2430 11:19:13.868038 CH1 DQ 0 Duty spec in!! Max-Min= 124%
2431 11:19:13.868145
2432 11:19:13.871566 CH1 DQ 1 Duty spec in!! Max-Min= 156%
2433 11:19:13.874589 [DutyScan_Calibration_Flow] ====Done====
2434 11:19:13.878364 nWR fixed to 30
2435 11:19:13.881369 [ModeRegInit_LP4] CH0 RK0
2436 11:19:13.881451 [ModeRegInit_LP4] CH0 RK1
2437 11:19:13.884932 [ModeRegInit_LP4] CH1 RK0
2438 11:19:13.887880 [ModeRegInit_LP4] CH1 RK1
2439 11:19:13.887962 match AC timing 7
2440 11:19:13.894692 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2441 11:19:13.897998 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2442 11:19:13.901368 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2443 11:19:13.907595 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2444 11:19:13.911087 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2445 11:19:13.911170 ==
2446 11:19:13.914496 Dram Type= 6, Freq= 0, CH_0, rank 0
2447 11:19:13.918160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2448 11:19:13.918254 ==
2449 11:19:13.924531 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2450 11:19:13.930695 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2451 11:19:13.938388 [CA 0] Center 40 (10~71) winsize 62
2452 11:19:13.941847 [CA 1] Center 39 (9~70) winsize 62
2453 11:19:13.944647 [CA 2] Center 36 (6~66) winsize 61
2454 11:19:13.948232 [CA 3] Center 35 (5~66) winsize 62
2455 11:19:13.951570 [CA 4] Center 34 (4~65) winsize 62
2456 11:19:13.954652 [CA 5] Center 33 (3~63) winsize 61
2457 11:19:13.954765
2458 11:19:13.958231 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2459 11:19:13.958341
2460 11:19:13.964364 [CATrainingPosCal] consider 1 rank data
2461 11:19:13.964478 u2DelayCellTimex100 = 270/100 ps
2462 11:19:13.970984 CA0 delay=40 (10~71),Diff = 7 PI (33 cell)
2463 11:19:13.974629 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2464 11:19:13.977598 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2465 11:19:13.981192 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2466 11:19:13.984225 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2467 11:19:13.987305 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2468 11:19:13.987387
2469 11:19:13.990983 CA PerBit enable=1, Macro0, CA PI delay=33
2470 11:19:13.991065
2471 11:19:13.994451 [CBTSetCACLKResult] CA Dly = 33
2472 11:19:13.997435 CS Dly: 7 (0~38)
2473 11:19:13.997517 ==
2474 11:19:14.000853 Dram Type= 6, Freq= 0, CH_0, rank 1
2475 11:19:14.004261 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2476 11:19:14.004344 ==
2477 11:19:14.010958 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2478 11:19:14.017176 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2479 11:19:14.024884 [CA 0] Center 40 (10~70) winsize 61
2480 11:19:14.028106 [CA 1] Center 40 (10~70) winsize 61
2481 11:19:14.031266 [CA 2] Center 35 (5~66) winsize 62
2482 11:19:14.034750 [CA 3] Center 35 (5~66) winsize 62
2483 11:19:14.037932 [CA 4] Center 34 (3~65) winsize 63
2484 11:19:14.040957 [CA 5] Center 33 (3~64) winsize 62
2485 11:19:14.041044
2486 11:19:14.044635 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2487 11:19:14.044719
2488 11:19:14.047553 [CATrainingPosCal] consider 2 rank data
2489 11:19:14.050882 u2DelayCellTimex100 = 270/100 ps
2490 11:19:14.054330 CA0 delay=40 (10~70),Diff = 7 PI (33 cell)
2491 11:19:14.060874 CA1 delay=40 (10~70),Diff = 7 PI (33 cell)
2492 11:19:14.064861 CA2 delay=36 (6~66),Diff = 3 PI (14 cell)
2493 11:19:14.067552 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2494 11:19:14.071236 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
2495 11:19:14.074120 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2496 11:19:14.074204
2497 11:19:14.077664 CA PerBit enable=1, Macro0, CA PI delay=33
2498 11:19:14.077748
2499 11:19:14.080638 [CBTSetCACLKResult] CA Dly = 33
2500 11:19:14.084230 CS Dly: 8 (0~40)
2501 11:19:14.084314
2502 11:19:14.087311 ----->DramcWriteLeveling(PI) begin...
2503 11:19:14.087396 ==
2504 11:19:14.090799 Dram Type= 6, Freq= 0, CH_0, rank 0
2505 11:19:14.094527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2506 11:19:14.094611 ==
2507 11:19:14.097550 Write leveling (Byte 0): 31 => 31
2508 11:19:14.101178 Write leveling (Byte 1): 29 => 29
2509 11:19:14.103943 DramcWriteLeveling(PI) end<-----
2510 11:19:14.104027
2511 11:19:14.104094 ==
2512 11:19:14.107388 Dram Type= 6, Freq= 0, CH_0, rank 0
2513 11:19:14.110849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2514 11:19:14.110950 ==
2515 11:19:14.114205 [Gating] SW mode calibration
2516 11:19:14.120934 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2517 11:19:14.127133 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2518 11:19:14.130583 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2519 11:19:14.133919 0 15 4 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
2520 11:19:14.140576 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2521 11:19:14.143959 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2522 11:19:14.147535 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2523 11:19:14.154081 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2524 11:19:14.157602 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2525 11:19:14.160608 0 15 28 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
2526 11:19:14.167013 1 0 0 | B1->B0 | 3333 2a2a | 1 0 | (1 1) (1 0)
2527 11:19:14.170595 1 0 4 | B1->B0 | 2424 2323 | 1 0 | (1 0) (0 0)
2528 11:19:14.173619 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2529 11:19:14.180236 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2530 11:19:14.183811 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2531 11:19:14.187367 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2532 11:19:14.193972 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2533 11:19:14.197043 1 0 28 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
2534 11:19:14.200684 1 1 0 | B1->B0 | 2525 2e2e | 0 0 | (1 1) (0 0)
2535 11:19:14.207465 1 1 4 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
2536 11:19:14.210549 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2537 11:19:14.213925 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2538 11:19:14.217226 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2539 11:19:14.223481 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2540 11:19:14.226862 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2541 11:19:14.230046 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2542 11:19:14.236817 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
2543 11:19:14.240228 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2544 11:19:14.243581 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2545 11:19:14.250299 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2546 11:19:14.253534 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2547 11:19:14.256853 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 11:19:14.263755 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 11:19:14.266918 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 11:19:14.270053 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 11:19:14.276600 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 11:19:14.280225 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 11:19:14.283267 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 11:19:14.289839 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 11:19:14.293493 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 11:19:14.296449 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2557 11:19:14.303733 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2558 11:19:14.306686 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2559 11:19:14.310292 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2560 11:19:14.313294 Total UI for P1: 0, mck2ui 16
2561 11:19:14.316826 best dqsien dly found for B0: ( 1, 3, 28)
2562 11:19:14.320256 Total UI for P1: 0, mck2ui 16
2563 11:19:14.323439 best dqsien dly found for B1: ( 1, 4, 0)
2564 11:19:14.326338 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2565 11:19:14.329801 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2566 11:19:14.329883
2567 11:19:14.333447 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2568 11:19:14.340164 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2569 11:19:14.340247 [Gating] SW calibration Done
2570 11:19:14.340314 ==
2571 11:19:14.343472 Dram Type= 6, Freq= 0, CH_0, rank 0
2572 11:19:14.350146 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2573 11:19:14.350230 ==
2574 11:19:14.350296 RX Vref Scan: 0
2575 11:19:14.350384
2576 11:19:14.353357 RX Vref 0 -> 0, step: 1
2577 11:19:14.353428
2578 11:19:14.356737 RX Delay -40 -> 252, step: 8
2579 11:19:14.359655 iDelay=200, Bit 0, Center 111 (32 ~ 191) 160
2580 11:19:14.363151 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
2581 11:19:14.366613 iDelay=200, Bit 2, Center 111 (32 ~ 191) 160
2582 11:19:14.372751 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2583 11:19:14.376064 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2584 11:19:14.379728 iDelay=200, Bit 5, Center 99 (24 ~ 175) 152
2585 11:19:14.382728 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
2586 11:19:14.385931 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2587 11:19:14.392448 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2588 11:19:14.395880 iDelay=200, Bit 9, Center 87 (8 ~ 167) 160
2589 11:19:14.399517 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2590 11:19:14.402563 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2591 11:19:14.405507 iDelay=200, Bit 12, Center 107 (40 ~ 175) 136
2592 11:19:14.412866 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2593 11:19:14.415623 iDelay=200, Bit 14, Center 115 (40 ~ 191) 152
2594 11:19:14.419184 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2595 11:19:14.419271 ==
2596 11:19:14.422113 Dram Type= 6, Freq= 0, CH_0, rank 0
2597 11:19:14.425788 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2598 11:19:14.428853 ==
2599 11:19:14.428936 DQS Delay:
2600 11:19:14.429020 DQS0 = 0, DQS1 = 0
2601 11:19:14.432450 DQM Delay:
2602 11:19:14.432533 DQM0 = 112, DQM1 = 102
2603 11:19:14.435937 DQ Delay:
2604 11:19:14.439107 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2605 11:19:14.442173 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2606 11:19:14.445548 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =95
2607 11:19:14.449054 DQ12 =107, DQ13 =111, DQ14 =115, DQ15 =111
2608 11:19:14.449137
2609 11:19:14.449203
2610 11:19:14.449264 ==
2611 11:19:14.452351 Dram Type= 6, Freq= 0, CH_0, rank 0
2612 11:19:14.455231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2613 11:19:14.455315 ==
2614 11:19:14.455380
2615 11:19:14.455441
2616 11:19:14.458541 TX Vref Scan disable
2617 11:19:14.462303 == TX Byte 0 ==
2618 11:19:14.465585 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2619 11:19:14.469406 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2620 11:19:14.472022 == TX Byte 1 ==
2621 11:19:14.475527 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2622 11:19:14.478763 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2623 11:19:14.478902 ==
2624 11:19:14.482499 Dram Type= 6, Freq= 0, CH_0, rank 0
2625 11:19:14.485323 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2626 11:19:14.489029 ==
2627 11:19:14.499543 TX Vref=22, minBit 11, minWin=25, winSum=419
2628 11:19:14.502311 TX Vref=24, minBit 3, minWin=26, winSum=424
2629 11:19:14.505346 TX Vref=26, minBit 4, minWin=26, winSum=432
2630 11:19:14.509107 TX Vref=28, minBit 8, minWin=26, winSum=436
2631 11:19:14.512534 TX Vref=30, minBit 13, minWin=26, winSum=436
2632 11:19:14.519208 TX Vref=32, minBit 8, minWin=26, winSum=428
2633 11:19:14.522042 [TxChooseVref] Worse bit 8, Min win 26, Win sum 436, Final Vref 28
2634 11:19:14.522125
2635 11:19:14.525595 Final TX Range 1 Vref 28
2636 11:19:14.525678
2637 11:19:14.525743 ==
2638 11:19:14.528582 Dram Type= 6, Freq= 0, CH_0, rank 0
2639 11:19:14.532039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2640 11:19:14.535540 ==
2641 11:19:14.535622
2642 11:19:14.535688
2643 11:19:14.535749 TX Vref Scan disable
2644 11:19:14.538853 == TX Byte 0 ==
2645 11:19:14.542170 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2646 11:19:14.548776 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2647 11:19:14.548859 == TX Byte 1 ==
2648 11:19:14.552050 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
2649 11:19:14.558654 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
2650 11:19:14.558737
2651 11:19:14.558803 [DATLAT]
2652 11:19:14.558906 Freq=1200, CH0 RK0
2653 11:19:14.558967
2654 11:19:14.561973 DATLAT Default: 0xd
2655 11:19:14.562055 0, 0xFFFF, sum = 0
2656 11:19:14.565578 1, 0xFFFF, sum = 0
2657 11:19:14.568600 2, 0xFFFF, sum = 0
2658 11:19:14.568684 3, 0xFFFF, sum = 0
2659 11:19:14.571821 4, 0xFFFF, sum = 0
2660 11:19:14.571905 5, 0xFFFF, sum = 0
2661 11:19:14.575217 6, 0xFFFF, sum = 0
2662 11:19:14.575301 7, 0xFFFF, sum = 0
2663 11:19:14.578776 8, 0xFFFF, sum = 0
2664 11:19:14.578897 9, 0xFFFF, sum = 0
2665 11:19:14.582015 10, 0xFFFF, sum = 0
2666 11:19:14.582127 11, 0xFFFF, sum = 0
2667 11:19:14.585443 12, 0x0, sum = 1
2668 11:19:14.585547 13, 0x0, sum = 2
2669 11:19:14.588810 14, 0x0, sum = 3
2670 11:19:14.588891 15, 0x0, sum = 4
2671 11:19:14.592021 best_step = 13
2672 11:19:14.592118
2673 11:19:14.592212 ==
2674 11:19:14.595449 Dram Type= 6, Freq= 0, CH_0, rank 0
2675 11:19:14.598464 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2676 11:19:14.598567 ==
2677 11:19:14.598661 RX Vref Scan: 1
2678 11:19:14.602008
2679 11:19:14.602109 Set Vref Range= 32 -> 127
2680 11:19:14.602202
2681 11:19:14.604989 RX Vref 32 -> 127, step: 1
2682 11:19:14.605085
2683 11:19:14.608504 RX Delay -37 -> 252, step: 4
2684 11:19:14.608608
2685 11:19:14.611519 Set Vref, RX VrefLevel [Byte0]: 32
2686 11:19:14.615198 [Byte1]: 32
2687 11:19:14.615277
2688 11:19:14.618240 Set Vref, RX VrefLevel [Byte0]: 33
2689 11:19:14.621839 [Byte1]: 33
2690 11:19:14.625458
2691 11:19:14.625561 Set Vref, RX VrefLevel [Byte0]: 34
2692 11:19:14.629010 [Byte1]: 34
2693 11:19:14.633542
2694 11:19:14.633647 Set Vref, RX VrefLevel [Byte0]: 35
2695 11:19:14.636904 [Byte1]: 35
2696 11:19:14.641635
2697 11:19:14.641737 Set Vref, RX VrefLevel [Byte0]: 36
2698 11:19:14.644665 [Byte1]: 36
2699 11:19:14.649659
2700 11:19:14.649760 Set Vref, RX VrefLevel [Byte0]: 37
2701 11:19:14.652667 [Byte1]: 37
2702 11:19:14.657356
2703 11:19:14.657460 Set Vref, RX VrefLevel [Byte0]: 38
2704 11:19:14.661228 [Byte1]: 38
2705 11:19:14.665463
2706 11:19:14.665562 Set Vref, RX VrefLevel [Byte0]: 39
2707 11:19:14.668795 [Byte1]: 39
2708 11:19:14.673298
2709 11:19:14.673399 Set Vref, RX VrefLevel [Byte0]: 40
2710 11:19:14.676571 [Byte1]: 40
2711 11:19:14.681574
2712 11:19:14.681676 Set Vref, RX VrefLevel [Byte0]: 41
2713 11:19:14.684915 [Byte1]: 41
2714 11:19:14.689425
2715 11:19:14.689526 Set Vref, RX VrefLevel [Byte0]: 42
2716 11:19:14.692935 [Byte1]: 42
2717 11:19:14.697715
2718 11:19:14.697797 Set Vref, RX VrefLevel [Byte0]: 43
2719 11:19:14.700720 [Byte1]: 43
2720 11:19:14.705491
2721 11:19:14.705573 Set Vref, RX VrefLevel [Byte0]: 44
2722 11:19:14.709056 [Byte1]: 44
2723 11:19:14.713285
2724 11:19:14.713366 Set Vref, RX VrefLevel [Byte0]: 45
2725 11:19:14.716868 [Byte1]: 45
2726 11:19:14.721759
2727 11:19:14.721869 Set Vref, RX VrefLevel [Byte0]: 46
2728 11:19:14.724792 [Byte1]: 46
2729 11:19:14.729543
2730 11:19:14.729620 Set Vref, RX VrefLevel [Byte0]: 47
2731 11:19:14.732601 [Byte1]: 47
2732 11:19:14.737468
2733 11:19:14.737549 Set Vref, RX VrefLevel [Byte0]: 48
2734 11:19:14.740944 [Byte1]: 48
2735 11:19:14.745546
2736 11:19:14.745656 Set Vref, RX VrefLevel [Byte0]: 49
2737 11:19:14.748866 [Byte1]: 49
2738 11:19:14.753406
2739 11:19:14.753488 Set Vref, RX VrefLevel [Byte0]: 50
2740 11:19:14.757239 [Byte1]: 50
2741 11:19:14.761347
2742 11:19:14.761429 Set Vref, RX VrefLevel [Byte0]: 51
2743 11:19:14.764665 [Byte1]: 51
2744 11:19:14.769566
2745 11:19:14.769648 Set Vref, RX VrefLevel [Byte0]: 52
2746 11:19:14.772947 [Byte1]: 52
2747 11:19:14.777435
2748 11:19:14.777518 Set Vref, RX VrefLevel [Byte0]: 53
2749 11:19:14.780622 [Byte1]: 53
2750 11:19:14.785619
2751 11:19:14.785706 Set Vref, RX VrefLevel [Byte0]: 54
2752 11:19:14.789048 [Byte1]: 54
2753 11:19:14.793363
2754 11:19:14.793445 Set Vref, RX VrefLevel [Byte0]: 55
2755 11:19:14.796999 [Byte1]: 55
2756 11:19:14.801329
2757 11:19:14.801411 Set Vref, RX VrefLevel [Byte0]: 56
2758 11:19:14.804892 [Byte1]: 56
2759 11:19:14.809775
2760 11:19:14.809857 Set Vref, RX VrefLevel [Byte0]: 57
2761 11:19:14.813116 [Byte1]: 57
2762 11:19:14.817255
2763 11:19:14.817366 Set Vref, RX VrefLevel [Byte0]: 58
2764 11:19:14.820784 [Byte1]: 58
2765 11:19:14.825559
2766 11:19:14.825660 Set Vref, RX VrefLevel [Byte0]: 59
2767 11:19:14.828610 [Byte1]: 59
2768 11:19:14.833390
2769 11:19:14.833489 Set Vref, RX VrefLevel [Byte0]: 60
2770 11:19:14.837234 [Byte1]: 60
2771 11:19:14.841271
2772 11:19:14.841346 Set Vref, RX VrefLevel [Byte0]: 61
2773 11:19:14.844829 [Byte1]: 61
2774 11:19:14.849412
2775 11:19:14.849483 Set Vref, RX VrefLevel [Byte0]: 62
2776 11:19:14.853029 [Byte1]: 62
2777 11:19:14.857309
2778 11:19:14.857381 Set Vref, RX VrefLevel [Byte0]: 63
2779 11:19:14.860805 [Byte1]: 63
2780 11:19:14.865484
2781 11:19:14.865583 Set Vref, RX VrefLevel [Byte0]: 64
2782 11:19:14.868532 [Byte1]: 64
2783 11:19:14.873485
2784 11:19:14.873558 Set Vref, RX VrefLevel [Byte0]: 65
2785 11:19:14.876813 [Byte1]: 65
2786 11:19:14.881453
2787 11:19:14.881555 Set Vref, RX VrefLevel [Byte0]: 66
2788 11:19:14.884835 [Byte1]: 66
2789 11:19:14.889840
2790 11:19:14.889921 Set Vref, RX VrefLevel [Byte0]: 67
2791 11:19:14.892716 [Byte1]: 67
2792 11:19:14.897618
2793 11:19:14.897700 Set Vref, RX VrefLevel [Byte0]: 68
2794 11:19:14.901222 [Byte1]: 68
2795 11:19:14.905487
2796 11:19:14.905569 Set Vref, RX VrefLevel [Byte0]: 69
2797 11:19:14.909029 [Byte1]: 69
2798 11:19:14.913477
2799 11:19:14.913560 Set Vref, RX VrefLevel [Byte0]: 70
2800 11:19:14.917048 [Byte1]: 70
2801 11:19:14.924683
2802 11:19:14.924766 Set Vref, RX VrefLevel [Byte0]: 71
2803 11:19:14.925015 [Byte1]: 71
2804 11:19:14.929551
2805 11:19:14.929634 Set Vref, RX VrefLevel [Byte0]: 72
2806 11:19:14.932728 [Byte1]: 72
2807 11:19:14.937247
2808 11:19:14.937362 Set Vref, RX VrefLevel [Byte0]: 73
2809 11:19:14.940830 [Byte1]: 73
2810 11:19:14.945709
2811 11:19:14.945792 Set Vref, RX VrefLevel [Byte0]: 74
2812 11:19:14.948542 [Byte1]: 74
2813 11:19:14.953301
2814 11:19:14.953387 Final RX Vref Byte 0 = 61 to rank0
2815 11:19:14.956861 Final RX Vref Byte 1 = 57 to rank0
2816 11:19:14.959906 Final RX Vref Byte 0 = 61 to rank1
2817 11:19:14.963495 Final RX Vref Byte 1 = 57 to rank1==
2818 11:19:14.967034 Dram Type= 6, Freq= 0, CH_0, rank 0
2819 11:19:14.973271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2820 11:19:14.973354 ==
2821 11:19:14.973420 DQS Delay:
2822 11:19:14.976467 DQS0 = 0, DQS1 = 0
2823 11:19:14.976550 DQM Delay:
2824 11:19:14.976616 DQM0 = 111, DQM1 = 102
2825 11:19:14.980022 DQ Delay:
2826 11:19:14.983378 DQ0 =110, DQ1 =110, DQ2 =112, DQ3 =108
2827 11:19:14.986964 DQ4 =112, DQ5 =104, DQ6 =118, DQ7 =120
2828 11:19:14.989879 DQ8 =94, DQ9 =86, DQ10 =104, DQ11 =94
2829 11:19:14.993256 DQ12 =108, DQ13 =108, DQ14 =116, DQ15 =108
2830 11:19:14.993339
2831 11:19:14.993436
2832 11:19:15.003116 [DQSOSCAuto] RK0, (LSB)MR18= 0xf9f8, (MSB)MR19= 0x303, tDQSOscB0 = 413 ps tDQSOscB1 = 412 ps
2833 11:19:15.003201 CH0 RK0: MR19=303, MR18=F9F8
2834 11:19:15.009617 CH0_RK0: MR19=0x303, MR18=0xF9F8, DQSOSC=412, MR23=63, INC=38, DEC=25
2835 11:19:15.009701
2836 11:19:15.013071 ----->DramcWriteLeveling(PI) begin...
2837 11:19:15.013156 ==
2838 11:19:15.016137 Dram Type= 6, Freq= 0, CH_0, rank 1
2839 11:19:15.022708 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2840 11:19:15.022820 ==
2841 11:19:15.026365 Write leveling (Byte 0): 35 => 35
2842 11:19:15.029284 Write leveling (Byte 1): 29 => 29
2843 11:19:15.029368 DramcWriteLeveling(PI) end<-----
2844 11:19:15.029433
2845 11:19:15.033021 ==
2846 11:19:15.036027 Dram Type= 6, Freq= 0, CH_0, rank 1
2847 11:19:15.039539 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2848 11:19:15.039623 ==
2849 11:19:15.042573 [Gating] SW mode calibration
2850 11:19:15.049199 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2851 11:19:15.052764 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2852 11:19:15.059416 0 15 0 | B1->B0 | 2323 3434 | 1 0 | (1 1) (0 0)
2853 11:19:15.062750 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2854 11:19:15.065788 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2855 11:19:15.072460 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2856 11:19:15.076018 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2857 11:19:15.078876 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2858 11:19:15.086164 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 0)
2859 11:19:15.089244 0 15 28 | B1->B0 | 3434 2424 | 1 1 | (1 1) (1 0)
2860 11:19:15.092815 1 0 0 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
2861 11:19:15.099365 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2862 11:19:15.102536 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2863 11:19:15.106074 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2864 11:19:15.112273 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2865 11:19:15.115750 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2866 11:19:15.118999 1 0 24 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
2867 11:19:15.125347 1 0 28 | B1->B0 | 2828 4646 | 0 0 | (1 1) (0 0)
2868 11:19:15.128801 1 1 0 | B1->B0 | 3f3f 4646 | 1 0 | (0 0) (0 0)
2869 11:19:15.131973 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2870 11:19:15.138586 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2871 11:19:15.142196 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2872 11:19:15.145170 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2873 11:19:15.151859 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2874 11:19:15.155349 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2875 11:19:15.158526 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2876 11:19:15.165332 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2877 11:19:15.168364 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2878 11:19:15.171903 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2879 11:19:15.178538 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2880 11:19:15.181478 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2881 11:19:15.184966 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2882 11:19:15.188511 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2883 11:19:15.195259 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2884 11:19:15.198406 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2885 11:19:15.201891 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2886 11:19:15.208291 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2887 11:19:15.211723 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2888 11:19:15.214973 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2889 11:19:15.221614 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2890 11:19:15.224917 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2891 11:19:15.228290 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2892 11:19:15.231535 Total UI for P1: 0, mck2ui 16
2893 11:19:15.235160 best dqsien dly found for B0: ( 1, 3, 26)
2894 11:19:15.241543 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2895 11:19:15.244582 Total UI for P1: 0, mck2ui 16
2896 11:19:15.248376 best dqsien dly found for B1: ( 1, 3, 30)
2897 11:19:15.251142 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2898 11:19:15.254847 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2899 11:19:15.254946
2900 11:19:15.257720 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2901 11:19:15.261256 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2902 11:19:15.264688 [Gating] SW calibration Done
2903 11:19:15.264790 ==
2904 11:19:15.267940 Dram Type= 6, Freq= 0, CH_0, rank 1
2905 11:19:15.271025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2906 11:19:15.271126 ==
2907 11:19:15.274496 RX Vref Scan: 0
2908 11:19:15.274590
2909 11:19:15.277551 RX Vref 0 -> 0, step: 1
2910 11:19:15.277649
2911 11:19:15.277742 RX Delay -40 -> 252, step: 8
2912 11:19:15.284083 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2913 11:19:15.287817 iDelay=200, Bit 1, Center 111 (32 ~ 191) 160
2914 11:19:15.291014 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2915 11:19:15.293968 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
2916 11:19:15.297592 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
2917 11:19:15.304307 iDelay=200, Bit 5, Center 99 (32 ~ 167) 136
2918 11:19:15.307958 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
2919 11:19:15.310535 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2920 11:19:15.314101 iDelay=200, Bit 8, Center 91 (16 ~ 167) 152
2921 11:19:15.317454 iDelay=200, Bit 9, Center 87 (16 ~ 159) 144
2922 11:19:15.323983 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
2923 11:19:15.327312 iDelay=200, Bit 11, Center 95 (24 ~ 167) 144
2924 11:19:15.330627 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2925 11:19:15.334069 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2926 11:19:15.337412 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
2927 11:19:15.344025 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2928 11:19:15.344126 ==
2929 11:19:15.347533 Dram Type= 6, Freq= 0, CH_0, rank 1
2930 11:19:15.350484 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2931 11:19:15.350586 ==
2932 11:19:15.350677 DQS Delay:
2933 11:19:15.354097 DQS0 = 0, DQS1 = 0
2934 11:19:15.354172 DQM Delay:
2935 11:19:15.357045 DQM0 = 112, DQM1 = 102
2936 11:19:15.357115 DQ Delay:
2937 11:19:15.360836 DQ0 =111, DQ1 =111, DQ2 =111, DQ3 =107
2938 11:19:15.363622 DQ4 =115, DQ5 =99, DQ6 =119, DQ7 =123
2939 11:19:15.367260 DQ8 =91, DQ9 =87, DQ10 =103, DQ11 =95
2940 11:19:15.370189 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
2941 11:19:15.370295
2942 11:19:15.370384
2943 11:19:15.373860 ==
2944 11:19:15.373963 Dram Type= 6, Freq= 0, CH_0, rank 1
2945 11:19:15.380528 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2946 11:19:15.380633 ==
2947 11:19:15.380723
2948 11:19:15.380809
2949 11:19:15.383549 TX Vref Scan disable
2950 11:19:15.383618 == TX Byte 0 ==
2951 11:19:15.387211 Update DQ dly =854 (3 ,2, 22) DQ OEN =(2 ,7)
2952 11:19:15.393691 Update DQM dly =854 (3 ,2, 22) DQM OEN =(2 ,7)
2953 11:19:15.393765 == TX Byte 1 ==
2954 11:19:15.396655 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2955 11:19:15.403194 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2956 11:19:15.403293 ==
2957 11:19:15.406572 Dram Type= 6, Freq= 0, CH_0, rank 1
2958 11:19:15.409891 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2959 11:19:15.409997 ==
2960 11:19:15.422383 TX Vref=22, minBit 1, minWin=25, winSum=425
2961 11:19:15.425797 TX Vref=24, minBit 1, minWin=26, winSum=431
2962 11:19:15.429381 TX Vref=26, minBit 7, minWin=26, winSum=435
2963 11:19:15.432736 TX Vref=28, minBit 1, minWin=26, winSum=435
2964 11:19:15.436116 TX Vref=30, minBit 1, minWin=27, winSum=440
2965 11:19:15.443042 TX Vref=32, minBit 1, minWin=26, winSum=438
2966 11:19:15.445680 [TxChooseVref] Worse bit 1, Min win 27, Win sum 440, Final Vref 30
2967 11:19:15.445786
2968 11:19:15.448929 Final TX Range 1 Vref 30
2969 11:19:15.449025
2970 11:19:15.449121 ==
2971 11:19:15.452393 Dram Type= 6, Freq= 0, CH_0, rank 1
2972 11:19:15.455497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2973 11:19:15.459245 ==
2974 11:19:15.459345
2975 11:19:15.459440
2976 11:19:15.459502 TX Vref Scan disable
2977 11:19:15.462272 == TX Byte 0 ==
2978 11:19:15.465840 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2979 11:19:15.472347 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2980 11:19:15.472422 == TX Byte 1 ==
2981 11:19:15.475501 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2982 11:19:15.481957 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2983 11:19:15.482053
2984 11:19:15.482150 [DATLAT]
2985 11:19:15.482237 Freq=1200, CH0 RK1
2986 11:19:15.482323
2987 11:19:15.485605 DATLAT Default: 0xd
2988 11:19:15.488511 0, 0xFFFF, sum = 0
2989 11:19:15.488580 1, 0xFFFF, sum = 0
2990 11:19:15.492031 2, 0xFFFF, sum = 0
2991 11:19:15.492099 3, 0xFFFF, sum = 0
2992 11:19:15.495000 4, 0xFFFF, sum = 0
2993 11:19:15.495078 5, 0xFFFF, sum = 0
2994 11:19:15.498417 6, 0xFFFF, sum = 0
2995 11:19:15.498512 7, 0xFFFF, sum = 0
2996 11:19:15.501386 8, 0xFFFF, sum = 0
2997 11:19:15.501487 9, 0xFFFF, sum = 0
2998 11:19:15.504977 10, 0xFFFF, sum = 0
2999 11:19:15.505049 11, 0xFFFF, sum = 0
3000 11:19:15.507947 12, 0x0, sum = 1
3001 11:19:15.508059 13, 0x0, sum = 2
3002 11:19:15.511391 14, 0x0, sum = 3
3003 11:19:15.511468 15, 0x0, sum = 4
3004 11:19:15.515000 best_step = 13
3005 11:19:15.515099
3006 11:19:15.515187 ==
3007 11:19:15.518675 Dram Type= 6, Freq= 0, CH_0, rank 1
3008 11:19:15.521472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3009 11:19:15.521560 ==
3010 11:19:15.525187 RX Vref Scan: 0
3011 11:19:15.525270
3012 11:19:15.525336 RX Vref 0 -> 0, step: 1
3013 11:19:15.525398
3014 11:19:15.528049 RX Delay -29 -> 252, step: 4
3015 11:19:15.534784 iDelay=195, Bit 0, Center 108 (39 ~ 178) 140
3016 11:19:15.538263 iDelay=195, Bit 1, Center 112 (43 ~ 182) 140
3017 11:19:15.541041 iDelay=195, Bit 2, Center 108 (39 ~ 178) 140
3018 11:19:15.544578 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3019 11:19:15.548109 iDelay=195, Bit 4, Center 112 (43 ~ 182) 140
3020 11:19:15.554369 iDelay=195, Bit 5, Center 100 (35 ~ 166) 132
3021 11:19:15.557958 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3022 11:19:15.561524 iDelay=195, Bit 7, Center 120 (47 ~ 194) 148
3023 11:19:15.564424 iDelay=195, Bit 8, Center 90 (19 ~ 162) 144
3024 11:19:15.567940 iDelay=195, Bit 9, Center 84 (15 ~ 154) 140
3025 11:19:15.574589 iDelay=195, Bit 10, Center 102 (35 ~ 170) 136
3026 11:19:15.577479 iDelay=195, Bit 11, Center 94 (27 ~ 162) 136
3027 11:19:15.580984 iDelay=195, Bit 12, Center 110 (43 ~ 178) 136
3028 11:19:15.584020 iDelay=195, Bit 13, Center 108 (39 ~ 178) 140
3029 11:19:15.590611 iDelay=195, Bit 14, Center 116 (51 ~ 182) 132
3030 11:19:15.594233 iDelay=195, Bit 15, Center 110 (43 ~ 178) 136
3031 11:19:15.594320 ==
3032 11:19:15.597250 Dram Type= 6, Freq= 0, CH_0, rank 1
3033 11:19:15.600884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3034 11:19:15.600971 ==
3035 11:19:15.603858 DQS Delay:
3036 11:19:15.603944 DQS0 = 0, DQS1 = 0
3037 11:19:15.604029 DQM Delay:
3038 11:19:15.607390 DQM0 = 111, DQM1 = 101
3039 11:19:15.607476 DQ Delay:
3040 11:19:15.610468 DQ0 =108, DQ1 =112, DQ2 =108, DQ3 =108
3041 11:19:15.613918 DQ4 =112, DQ5 =100, DQ6 =120, DQ7 =120
3042 11:19:15.617339 DQ8 =90, DQ9 =84, DQ10 =102, DQ11 =94
3043 11:19:15.620361 DQ12 =110, DQ13 =108, DQ14 =116, DQ15 =110
3044 11:19:15.623948
3045 11:19:15.624034
3046 11:19:15.630641 [DQSOSCAuto] RK1, (LSB)MR18= 0x15fd, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 401 ps
3047 11:19:15.633966 CH0 RK1: MR19=403, MR18=15FD
3048 11:19:15.640110 CH0_RK1: MR19=0x403, MR18=0x15FD, DQSOSC=401, MR23=63, INC=40, DEC=27
3049 11:19:15.643888 [RxdqsGatingPostProcess] freq 1200
3050 11:19:15.647185 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3051 11:19:15.650450 best DQS0 dly(2T, 0.5T) = (0, 11)
3052 11:19:15.653892 best DQS1 dly(2T, 0.5T) = (0, 12)
3053 11:19:15.656888 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3054 11:19:15.660797 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3055 11:19:15.663440 best DQS0 dly(2T, 0.5T) = (0, 11)
3056 11:19:15.666816 best DQS1 dly(2T, 0.5T) = (0, 11)
3057 11:19:15.670077 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3058 11:19:15.673324 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3059 11:19:15.676891 Pre-setting of DQS Precalculation
3060 11:19:15.680201 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3061 11:19:15.680288 ==
3062 11:19:15.683371 Dram Type= 6, Freq= 0, CH_1, rank 0
3063 11:19:15.689795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3064 11:19:15.689891 ==
3065 11:19:15.693325 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3066 11:19:15.699591 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3067 11:19:15.708600 [CA 0] Center 37 (7~67) winsize 61
3068 11:19:15.712139 [CA 1] Center 37 (7~68) winsize 62
3069 11:19:15.715210 [CA 2] Center 34 (5~64) winsize 60
3070 11:19:15.718704 [CA 3] Center 33 (3~64) winsize 62
3071 11:19:15.722135 [CA 4] Center 34 (4~64) winsize 61
3072 11:19:15.725251 [CA 5] Center 33 (3~63) winsize 61
3073 11:19:15.725389
3074 11:19:15.728680 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3075 11:19:15.728763
3076 11:19:15.731601 [CATrainingPosCal] consider 1 rank data
3077 11:19:15.735069 u2DelayCellTimex100 = 270/100 ps
3078 11:19:15.738562 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3079 11:19:15.745115 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3080 11:19:15.748500 CA2 delay=34 (5~64),Diff = 1 PI (4 cell)
3081 11:19:15.751849 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3082 11:19:15.754587 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3083 11:19:15.758376 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3084 11:19:15.758472
3085 11:19:15.761686 CA PerBit enable=1, Macro0, CA PI delay=33
3086 11:19:15.761789
3087 11:19:15.765081 [CBTSetCACLKResult] CA Dly = 33
3088 11:19:15.767949 CS Dly: 6 (0~37)
3089 11:19:15.768062 ==
3090 11:19:15.771354 Dram Type= 6, Freq= 0, CH_1, rank 1
3091 11:19:15.774785 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3092 11:19:15.774922 ==
3093 11:19:15.781341 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3094 11:19:15.784637 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3095 11:19:15.794873 [CA 0] Center 37 (7~67) winsize 61
3096 11:19:15.797912 [CA 1] Center 37 (7~68) winsize 62
3097 11:19:15.801550 [CA 2] Center 34 (4~65) winsize 62
3098 11:19:15.804392 [CA 3] Center 33 (3~64) winsize 62
3099 11:19:15.808038 [CA 4] Center 34 (4~64) winsize 61
3100 11:19:15.811452 [CA 5] Center 32 (2~63) winsize 62
3101 11:19:15.811927
3102 11:19:15.814437 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3103 11:19:15.814929
3104 11:19:15.818055 [CATrainingPosCal] consider 2 rank data
3105 11:19:15.821180 u2DelayCellTimex100 = 270/100 ps
3106 11:19:15.824730 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3107 11:19:15.827968 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3108 11:19:15.834617 CA2 delay=34 (5~64),Diff = 1 PI (4 cell)
3109 11:19:15.837642 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3110 11:19:15.840969 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3111 11:19:15.844189 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3112 11:19:15.844272
3113 11:19:15.847273 CA PerBit enable=1, Macro0, CA PI delay=33
3114 11:19:15.847356
3115 11:19:15.850440 [CBTSetCACLKResult] CA Dly = 33
3116 11:19:15.850544 CS Dly: 7 (0~39)
3117 11:19:15.854224
3118 11:19:15.857155 ----->DramcWriteLeveling(PI) begin...
3119 11:19:15.857230 ==
3120 11:19:15.860716 Dram Type= 6, Freq= 0, CH_1, rank 0
3121 11:19:15.864086 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3122 11:19:15.864171 ==
3123 11:19:15.867536 Write leveling (Byte 0): 25 => 25
3124 11:19:15.870374 Write leveling (Byte 1): 28 => 28
3125 11:19:15.874058 DramcWriteLeveling(PI) end<-----
3126 11:19:15.874142
3127 11:19:15.874226 ==
3128 11:19:15.876748 Dram Type= 6, Freq= 0, CH_1, rank 0
3129 11:19:15.880097 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3130 11:19:15.880182 ==
3131 11:19:15.883388 [Gating] SW mode calibration
3132 11:19:15.890255 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3133 11:19:15.896853 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3134 11:19:15.900530 0 15 0 | B1->B0 | 2e2e 2726 | 1 1 | (1 1) (0 0)
3135 11:19:15.903621 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3136 11:19:15.910646 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3137 11:19:15.913640 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3138 11:19:15.917047 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3139 11:19:15.923625 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3140 11:19:15.927441 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3141 11:19:15.930561 0 15 28 | B1->B0 | 2b2b 3030 | 1 1 | (1 0) (1 0)
3142 11:19:15.937452 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
3143 11:19:15.940401 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3144 11:19:15.943818 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3145 11:19:15.950293 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3146 11:19:15.953703 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3147 11:19:15.957284 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3148 11:19:15.963203 1 0 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3149 11:19:15.967251 1 0 28 | B1->B0 | 4242 3f3f | 0 0 | (0 0) (0 0)
3150 11:19:15.970294 1 1 0 | B1->B0 | 4545 4444 | 0 0 | (0 0) (0 0)
3151 11:19:15.976688 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3152 11:19:15.979993 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3153 11:19:15.983249 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3154 11:19:15.989780 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3155 11:19:15.993165 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3156 11:19:15.996685 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3157 11:19:16.003300 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3158 11:19:16.006137 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3159 11:19:16.009829 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3160 11:19:16.016355 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3161 11:19:16.019858 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3162 11:19:16.023296 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3163 11:19:16.026337 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3164 11:19:16.033257 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3165 11:19:16.036738 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3166 11:19:16.039494 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3167 11:19:16.046479 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3168 11:19:16.049760 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3169 11:19:16.053327 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3170 11:19:16.060125 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3171 11:19:16.062993 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3172 11:19:16.065922 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3173 11:19:16.072816 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3174 11:19:16.076151 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3175 11:19:16.078961 Total UI for P1: 0, mck2ui 16
3176 11:19:16.082419 best dqsien dly found for B0: ( 1, 3, 28)
3177 11:19:16.085514 Total UI for P1: 0, mck2ui 16
3178 11:19:16.088791 best dqsien dly found for B1: ( 1, 3, 30)
3179 11:19:16.092022 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3180 11:19:16.095526 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
3181 11:19:16.095609
3182 11:19:16.098994 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3183 11:19:16.102370 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
3184 11:19:16.105773 [Gating] SW calibration Done
3185 11:19:16.105845 ==
3186 11:19:16.108735 Dram Type= 6, Freq= 0, CH_1, rank 0
3187 11:19:16.115230 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3188 11:19:16.115321 ==
3189 11:19:16.115391 RX Vref Scan: 0
3190 11:19:16.115456
3191 11:19:16.118833 RX Vref 0 -> 0, step: 1
3192 11:19:16.118957
3193 11:19:16.121872 RX Delay -40 -> 252, step: 8
3194 11:19:16.125029 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3195 11:19:16.128823 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3196 11:19:16.132413 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3197 11:19:16.138965 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3198 11:19:16.141994 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3199 11:19:16.145533 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3200 11:19:16.148417 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3201 11:19:16.152332 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3202 11:19:16.154952 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3203 11:19:16.161673 iDelay=200, Bit 9, Center 99 (32 ~ 167) 136
3204 11:19:16.165634 iDelay=200, Bit 10, Center 103 (32 ~ 175) 144
3205 11:19:16.169145 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3206 11:19:16.172094 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3207 11:19:16.175115 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
3208 11:19:16.181823 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3209 11:19:16.185471 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3210 11:19:16.185902 ==
3211 11:19:16.189151 Dram Type= 6, Freq= 0, CH_1, rank 0
3212 11:19:16.192501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3213 11:19:16.192923 ==
3214 11:19:16.195576 DQS Delay:
3215 11:19:16.196119 DQS0 = 0, DQS1 = 0
3216 11:19:16.196499 DQM Delay:
3217 11:19:16.199122 DQM0 = 114, DQM1 = 105
3218 11:19:16.199600 DQ Delay:
3219 11:19:16.202299 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3220 11:19:16.205800 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3221 11:19:16.208965 DQ8 =95, DQ9 =99, DQ10 =103, DQ11 =99
3222 11:19:16.215650 DQ12 =111, DQ13 =111, DQ14 =111, DQ15 =111
3223 11:19:16.216122
3224 11:19:16.216489
3225 11:19:16.216832 ==
3226 11:19:16.218655 Dram Type= 6, Freq= 0, CH_1, rank 0
3227 11:19:16.222438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3228 11:19:16.222996 ==
3229 11:19:16.223403
3230 11:19:16.223752
3231 11:19:16.225329 TX Vref Scan disable
3232 11:19:16.225806 == TX Byte 0 ==
3233 11:19:16.232127 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3234 11:19:16.235692 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3235 11:19:16.236147 == TX Byte 1 ==
3236 11:19:16.242245 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3237 11:19:16.245233 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3238 11:19:16.245787 ==
3239 11:19:16.248846 Dram Type= 6, Freq= 0, CH_1, rank 0
3240 11:19:16.251817 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3241 11:19:16.252425 ==
3242 11:19:16.264370 TX Vref=22, minBit 11, minWin=23, winSum=404
3243 11:19:16.267888 TX Vref=24, minBit 8, minWin=25, winSum=413
3244 11:19:16.271074 TX Vref=26, minBit 8, minWin=25, winSum=418
3245 11:19:16.274543 TX Vref=28, minBit 9, minWin=25, winSum=425
3246 11:19:16.277528 TX Vref=30, minBit 9, minWin=25, winSum=423
3247 11:19:16.284091 TX Vref=32, minBit 9, minWin=25, winSum=418
3248 11:19:16.287492 [TxChooseVref] Worse bit 9, Min win 25, Win sum 425, Final Vref 28
3249 11:19:16.287967
3250 11:19:16.290801 Final TX Range 1 Vref 28
3251 11:19:16.291318
3252 11:19:16.291692 ==
3253 11:19:16.294552 Dram Type= 6, Freq= 0, CH_1, rank 0
3254 11:19:16.297397 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3255 11:19:16.301241 ==
3256 11:19:16.301666
3257 11:19:16.302001
3258 11:19:16.302314 TX Vref Scan disable
3259 11:19:16.304541 == TX Byte 0 ==
3260 11:19:16.307659 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3261 11:19:16.314446 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3262 11:19:16.314947 == TX Byte 1 ==
3263 11:19:16.317684 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3264 11:19:16.324339 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3265 11:19:16.324817
3266 11:19:16.325344 [DATLAT]
3267 11:19:16.325850 Freq=1200, CH1 RK0
3268 11:19:16.326210
3269 11:19:16.327206 DATLAT Default: 0xd
3270 11:19:16.327675 0, 0xFFFF, sum = 0
3271 11:19:16.330771 1, 0xFFFF, sum = 0
3272 11:19:16.334303 2, 0xFFFF, sum = 0
3273 11:19:16.334778 3, 0xFFFF, sum = 0
3274 11:19:16.337706 4, 0xFFFF, sum = 0
3275 11:19:16.338183 5, 0xFFFF, sum = 0
3276 11:19:16.340669 6, 0xFFFF, sum = 0
3277 11:19:16.341242 7, 0xFFFF, sum = 0
3278 11:19:16.344230 8, 0xFFFF, sum = 0
3279 11:19:16.344712 9, 0xFFFF, sum = 0
3280 11:19:16.347281 10, 0xFFFF, sum = 0
3281 11:19:16.347764 11, 0xFFFF, sum = 0
3282 11:19:16.350892 12, 0x0, sum = 1
3283 11:19:16.351371 13, 0x0, sum = 2
3284 11:19:16.353830 14, 0x0, sum = 3
3285 11:19:16.354308 15, 0x0, sum = 4
3286 11:19:16.357554 best_step = 13
3287 11:19:16.358124
3288 11:19:16.358499 ==
3289 11:19:16.360421 Dram Type= 6, Freq= 0, CH_1, rank 0
3290 11:19:16.363747 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3291 11:19:16.364252 ==
3292 11:19:16.366963 RX Vref Scan: 1
3293 11:19:16.367044
3294 11:19:16.367108 Set Vref Range= 32 -> 127
3295 11:19:16.367169
3296 11:19:16.369990 RX Vref 32 -> 127, step: 1
3297 11:19:16.370071
3298 11:19:16.373686 RX Delay -21 -> 252, step: 4
3299 11:19:16.373768
3300 11:19:16.376539 Set Vref, RX VrefLevel [Byte0]: 32
3301 11:19:16.380203 [Byte1]: 32
3302 11:19:16.380284
3303 11:19:16.383235 Set Vref, RX VrefLevel [Byte0]: 33
3304 11:19:16.386852 [Byte1]: 33
3305 11:19:16.390446
3306 11:19:16.390542 Set Vref, RX VrefLevel [Byte0]: 34
3307 11:19:16.393749 [Byte1]: 34
3308 11:19:16.398300
3309 11:19:16.398395 Set Vref, RX VrefLevel [Byte0]: 35
3310 11:19:16.401429 [Byte1]: 35
3311 11:19:16.406387
3312 11:19:16.406487 Set Vref, RX VrefLevel [Byte0]: 36
3313 11:19:16.409678 [Byte1]: 36
3314 11:19:16.414229
3315 11:19:16.414305 Set Vref, RX VrefLevel [Byte0]: 37
3316 11:19:16.417561 [Byte1]: 37
3317 11:19:16.422122
3318 11:19:16.422203 Set Vref, RX VrefLevel [Byte0]: 38
3319 11:19:16.425374 [Byte1]: 38
3320 11:19:16.430213
3321 11:19:16.430288 Set Vref, RX VrefLevel [Byte0]: 39
3322 11:19:16.433314 [Byte1]: 39
3323 11:19:16.438014
3324 11:19:16.438111 Set Vref, RX VrefLevel [Byte0]: 40
3325 11:19:16.441105 [Byte1]: 40
3326 11:19:16.445933
3327 11:19:16.446026 Set Vref, RX VrefLevel [Byte0]: 41
3328 11:19:16.448916 [Byte1]: 41
3329 11:19:16.453655
3330 11:19:16.453788 Set Vref, RX VrefLevel [Byte0]: 42
3331 11:19:16.460353 [Byte1]: 42
3332 11:19:16.460549
3333 11:19:16.463627 Set Vref, RX VrefLevel [Byte0]: 43
3334 11:19:16.467121 [Byte1]: 43
3335 11:19:16.467335
3336 11:19:16.470644 Set Vref, RX VrefLevel [Byte0]: 44
3337 11:19:16.473753 [Byte1]: 44
3338 11:19:16.478090
3339 11:19:16.478346 Set Vref, RX VrefLevel [Byte0]: 45
3340 11:19:16.481022 [Byte1]: 45
3341 11:19:16.485848
3342 11:19:16.486178 Set Vref, RX VrefLevel [Byte0]: 46
3343 11:19:16.489047 [Byte1]: 46
3344 11:19:16.493960
3345 11:19:16.494355 Set Vref, RX VrefLevel [Byte0]: 47
3346 11:19:16.497088 [Byte1]: 47
3347 11:19:16.501783
3348 11:19:16.502244 Set Vref, RX VrefLevel [Byte0]: 48
3349 11:19:16.505413 [Byte1]: 48
3350 11:19:16.509719
3351 11:19:16.510296 Set Vref, RX VrefLevel [Byte0]: 49
3352 11:19:16.512676 [Byte1]: 49
3353 11:19:16.517725
3354 11:19:16.518190 Set Vref, RX VrefLevel [Byte0]: 50
3355 11:19:16.521123 [Byte1]: 50
3356 11:19:16.525378
3357 11:19:16.525878 Set Vref, RX VrefLevel [Byte0]: 51
3358 11:19:16.528548 [Byte1]: 51
3359 11:19:16.533189
3360 11:19:16.533664 Set Vref, RX VrefLevel [Byte0]: 52
3361 11:19:16.536676 [Byte1]: 52
3362 11:19:16.541858
3363 11:19:16.542436 Set Vref, RX VrefLevel [Byte0]: 53
3364 11:19:16.544854 [Byte1]: 53
3365 11:19:16.549510
3366 11:19:16.549984 Set Vref, RX VrefLevel [Byte0]: 54
3367 11:19:16.552577 [Byte1]: 54
3368 11:19:16.557250
3369 11:19:16.557724 Set Vref, RX VrefLevel [Byte0]: 55
3370 11:19:16.560806 [Byte1]: 55
3371 11:19:16.565093
3372 11:19:16.565565 Set Vref, RX VrefLevel [Byte0]: 56
3373 11:19:16.568303 [Byte1]: 56
3374 11:19:16.573254
3375 11:19:16.573721 Set Vref, RX VrefLevel [Byte0]: 57
3376 11:19:16.576162 [Byte1]: 57
3377 11:19:16.580838
3378 11:19:16.581127 Set Vref, RX VrefLevel [Byte0]: 58
3379 11:19:16.584383 [Byte1]: 58
3380 11:19:16.588299
3381 11:19:16.588381 Set Vref, RX VrefLevel [Byte0]: 59
3382 11:19:16.591920 [Byte1]: 59
3383 11:19:16.596062
3384 11:19:16.596143 Set Vref, RX VrefLevel [Byte0]: 60
3385 11:19:16.599712 [Byte1]: 60
3386 11:19:16.604247
3387 11:19:16.604329 Set Vref, RX VrefLevel [Byte0]: 61
3388 11:19:16.607959 [Byte1]: 61
3389 11:19:16.612282
3390 11:19:16.612382 Set Vref, RX VrefLevel [Byte0]: 62
3391 11:19:16.615301 [Byte1]: 62
3392 11:19:16.620044
3393 11:19:16.620138 Set Vref, RX VrefLevel [Byte0]: 63
3394 11:19:16.623236 [Byte1]: 63
3395 11:19:16.627963
3396 11:19:16.628045 Set Vref, RX VrefLevel [Byte0]: 64
3397 11:19:16.631730 [Byte1]: 64
3398 11:19:16.636143
3399 11:19:16.636312 Set Vref, RX VrefLevel [Byte0]: 65
3400 11:19:16.639373 [Byte1]: 65
3401 11:19:16.644065
3402 11:19:16.644256 Final RX Vref Byte 0 = 57 to rank0
3403 11:19:16.647372 Final RX Vref Byte 1 = 49 to rank0
3404 11:19:16.650579 Final RX Vref Byte 0 = 57 to rank1
3405 11:19:16.654074 Final RX Vref Byte 1 = 49 to rank1==
3406 11:19:16.657078 Dram Type= 6, Freq= 0, CH_1, rank 0
3407 11:19:16.664078 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3408 11:19:16.664303 ==
3409 11:19:16.664442 DQS Delay:
3410 11:19:16.667337 DQS0 = 0, DQS1 = 0
3411 11:19:16.667552 DQM Delay:
3412 11:19:16.667701 DQM0 = 114, DQM1 = 105
3413 11:19:16.670775 DQ Delay:
3414 11:19:16.674061 DQ0 =116, DQ1 =110, DQ2 =106, DQ3 =112
3415 11:19:16.677470 DQ4 =112, DQ5 =124, DQ6 =124, DQ7 =112
3416 11:19:16.680212 DQ8 =92, DQ9 =96, DQ10 =104, DQ11 =100
3417 11:19:16.683866 DQ12 =112, DQ13 =112, DQ14 =114, DQ15 =112
3418 11:19:16.684186
3419 11:19:16.684433
3420 11:19:16.693724 [DQSOSCAuto] RK0, (LSB)MR18= 0xecf3, (MSB)MR19= 0x303, tDQSOscB0 = 415 ps tDQSOscB1 = 418 ps
3421 11:19:16.694483 CH1 RK0: MR19=303, MR18=ECF3
3422 11:19:16.700376 CH1_RK0: MR19=0x303, MR18=0xECF3, DQSOSC=415, MR23=63, INC=38, DEC=25
3423 11:19:16.700857
3424 11:19:16.703856 ----->DramcWriteLeveling(PI) begin...
3425 11:19:16.704342 ==
3426 11:19:16.707263 Dram Type= 6, Freq= 0, CH_1, rank 1
3427 11:19:16.713859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3428 11:19:16.714636 ==
3429 11:19:16.716750 Write leveling (Byte 0): 25 => 25
3430 11:19:16.720238 Write leveling (Byte 1): 28 => 28
3431 11:19:16.720673 DramcWriteLeveling(PI) end<-----
3432 11:19:16.721115
3433 11:19:16.723637 ==
3434 11:19:16.727192 Dram Type= 6, Freq= 0, CH_1, rank 1
3435 11:19:16.730326 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3436 11:19:16.730929 ==
3437 11:19:16.733587 [Gating] SW mode calibration
3438 11:19:16.740324 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3439 11:19:16.743248 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3440 11:19:16.749932 0 15 0 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
3441 11:19:16.753470 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3442 11:19:16.756345 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3443 11:19:16.763066 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3444 11:19:16.766385 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3445 11:19:16.769909 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3446 11:19:16.776626 0 15 24 | B1->B0 | 3333 2525 | 1 0 | (1 1) (0 0)
3447 11:19:16.780147 0 15 28 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
3448 11:19:16.782893 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3449 11:19:16.789707 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3450 11:19:16.793192 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3451 11:19:16.796252 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3452 11:19:16.803347 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3453 11:19:16.806349 1 0 20 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
3454 11:19:16.809440 1 0 24 | B1->B0 | 2e2e 4646 | 1 0 | (0 0) (0 0)
3455 11:19:16.816518 1 0 28 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
3456 11:19:16.819406 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3457 11:19:16.823020 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3458 11:19:16.829696 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3459 11:19:16.833050 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3460 11:19:16.836384 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3461 11:19:16.843118 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3462 11:19:16.846636 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3463 11:19:16.849602 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3464 11:19:16.856101 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 11:19:16.859387 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 11:19:16.862942 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 11:19:16.869291 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 11:19:16.872421 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 11:19:16.876036 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 11:19:16.882329 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 11:19:16.885861 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3472 11:19:16.889193 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3473 11:19:16.895857 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3474 11:19:16.899118 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3475 11:19:16.902047 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3476 11:19:16.908565 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3477 11:19:16.911527 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3478 11:19:16.915220 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3479 11:19:16.921402 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3480 11:19:16.921891 Total UI for P1: 0, mck2ui 16
3481 11:19:16.928185 best dqsien dly found for B0: ( 1, 3, 24)
3482 11:19:16.928683 Total UI for P1: 0, mck2ui 16
3483 11:19:16.935250 best dqsien dly found for B1: ( 1, 3, 24)
3484 11:19:16.938674 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3485 11:19:16.941351 best DQS1 dly(MCK, UI, PI) = (1, 3, 24)
3486 11:19:16.941820
3487 11:19:16.944826 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3488 11:19:16.948127 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 24)
3489 11:19:16.951478 [Gating] SW calibration Done
3490 11:19:16.951958 ==
3491 11:19:16.954634 Dram Type= 6, Freq= 0, CH_1, rank 1
3492 11:19:16.958333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3493 11:19:16.958759 ==
3494 11:19:16.961273 RX Vref Scan: 0
3495 11:19:16.961718
3496 11:19:16.962057 RX Vref 0 -> 0, step: 1
3497 11:19:16.962496
3498 11:19:16.964682 RX Delay -40 -> 252, step: 8
3499 11:19:16.968198 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
3500 11:19:16.974771 iDelay=200, Bit 1, Center 103 (32 ~ 175) 144
3501 11:19:16.978110 iDelay=200, Bit 2, Center 99 (24 ~ 175) 152
3502 11:19:16.981369 iDelay=200, Bit 3, Center 107 (32 ~ 183) 152
3503 11:19:16.984503 iDelay=200, Bit 4, Center 107 (32 ~ 183) 152
3504 11:19:16.987340 iDelay=200, Bit 5, Center 119 (40 ~ 199) 160
3505 11:19:16.994486 iDelay=200, Bit 6, Center 119 (40 ~ 199) 160
3506 11:19:16.997414 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3507 11:19:17.001171 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3508 11:19:17.003940 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3509 11:19:17.007523 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3510 11:19:17.014291 iDelay=200, Bit 11, Center 99 (32 ~ 167) 136
3511 11:19:17.017331 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3512 11:19:17.020773 iDelay=200, Bit 13, Center 115 (40 ~ 191) 152
3513 11:19:17.024081 iDelay=200, Bit 14, Center 111 (40 ~ 183) 144
3514 11:19:17.030923 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3515 11:19:17.031363 ==
3516 11:19:17.033926 Dram Type= 6, Freq= 0, CH_1, rank 1
3517 11:19:17.037401 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3518 11:19:17.037838 ==
3519 11:19:17.038185 DQS Delay:
3520 11:19:17.040344 DQS0 = 0, DQS1 = 0
3521 11:19:17.040777 DQM Delay:
3522 11:19:17.043744 DQM0 = 110, DQM1 = 106
3523 11:19:17.044175 DQ Delay:
3524 11:19:17.047173 DQ0 =115, DQ1 =103, DQ2 =99, DQ3 =107
3525 11:19:17.050259 DQ4 =107, DQ5 =119, DQ6 =119, DQ7 =111
3526 11:19:17.053744 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =99
3527 11:19:17.057071 DQ12 =111, DQ13 =115, DQ14 =111, DQ15 =111
3528 11:19:17.057505
3529 11:19:17.057848
3530 11:19:17.058165 ==
3531 11:19:17.060543 Dram Type= 6, Freq= 0, CH_1, rank 1
3532 11:19:17.066933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3533 11:19:17.067497 ==
3534 11:19:17.067981
3535 11:19:17.068441
3536 11:19:17.070248 TX Vref Scan disable
3537 11:19:17.070680 == TX Byte 0 ==
3538 11:19:17.073349 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3539 11:19:17.079622 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3540 11:19:17.080054 == TX Byte 1 ==
3541 11:19:17.083083 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3542 11:19:17.090104 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3543 11:19:17.090629 ==
3544 11:19:17.092984 Dram Type= 6, Freq= 0, CH_1, rank 1
3545 11:19:17.096254 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3546 11:19:17.096586 ==
3547 11:19:17.108113 TX Vref=22, minBit 7, minWin=25, winSum=424
3548 11:19:17.111804 TX Vref=24, minBit 8, minWin=25, winSum=426
3549 11:19:17.114607 TX Vref=26, minBit 8, minWin=26, winSum=430
3550 11:19:17.118553 TX Vref=28, minBit 3, minWin=26, winSum=433
3551 11:19:17.121352 TX Vref=30, minBit 9, minWin=26, winSum=435
3552 11:19:17.128136 TX Vref=32, minBit 8, minWin=25, winSum=432
3553 11:19:17.131105 [TxChooseVref] Worse bit 9, Min win 26, Win sum 435, Final Vref 30
3554 11:19:17.131193
3555 11:19:17.134771 Final TX Range 1 Vref 30
3556 11:19:17.134908
3557 11:19:17.134976 ==
3558 11:19:17.137607 Dram Type= 6, Freq= 0, CH_1, rank 1
3559 11:19:17.144288 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3560 11:19:17.144377 ==
3561 11:19:17.144444
3562 11:19:17.144505
3563 11:19:17.144564 TX Vref Scan disable
3564 11:19:17.147913 == TX Byte 0 ==
3565 11:19:17.151171 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3566 11:19:17.158030 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3567 11:19:17.158116 == TX Byte 1 ==
3568 11:19:17.161158 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3569 11:19:17.168099 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3570 11:19:17.168190
3571 11:19:17.168258 [DATLAT]
3572 11:19:17.168319 Freq=1200, CH1 RK1
3573 11:19:17.168378
3574 11:19:17.171225 DATLAT Default: 0xd
3575 11:19:17.171309 0, 0xFFFF, sum = 0
3576 11:19:17.174636 1, 0xFFFF, sum = 0
3577 11:19:17.177810 2, 0xFFFF, sum = 0
3578 11:19:17.177895 3, 0xFFFF, sum = 0
3579 11:19:17.181321 4, 0xFFFF, sum = 0
3580 11:19:17.181448 5, 0xFFFF, sum = 0
3581 11:19:17.184396 6, 0xFFFF, sum = 0
3582 11:19:17.184481 7, 0xFFFF, sum = 0
3583 11:19:17.187501 8, 0xFFFF, sum = 0
3584 11:19:17.187586 9, 0xFFFF, sum = 0
3585 11:19:17.190893 10, 0xFFFF, sum = 0
3586 11:19:17.190977 11, 0xFFFF, sum = 0
3587 11:19:17.194363 12, 0x0, sum = 1
3588 11:19:17.194447 13, 0x0, sum = 2
3589 11:19:17.197679 14, 0x0, sum = 3
3590 11:19:17.197762 15, 0x0, sum = 4
3591 11:19:17.200947 best_step = 13
3592 11:19:17.201030
3593 11:19:17.201095 ==
3594 11:19:17.204040 Dram Type= 6, Freq= 0, CH_1, rank 1
3595 11:19:17.207479 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3596 11:19:17.207590 ==
3597 11:19:17.210530 RX Vref Scan: 0
3598 11:19:17.210638
3599 11:19:17.210737 RX Vref 0 -> 0, step: 1
3600 11:19:17.210850
3601 11:19:17.214088 RX Delay -21 -> 252, step: 4
3602 11:19:17.220368 iDelay=195, Bit 0, Center 114 (43 ~ 186) 144
3603 11:19:17.224005 iDelay=195, Bit 1, Center 110 (43 ~ 178) 136
3604 11:19:17.227185 iDelay=195, Bit 2, Center 100 (31 ~ 170) 140
3605 11:19:17.230602 iDelay=195, Bit 3, Center 108 (39 ~ 178) 140
3606 11:19:17.233506 iDelay=195, Bit 4, Center 108 (39 ~ 178) 140
3607 11:19:17.240245 iDelay=195, Bit 5, Center 120 (47 ~ 194) 148
3608 11:19:17.243792 iDelay=195, Bit 6, Center 120 (47 ~ 194) 148
3609 11:19:17.246801 iDelay=195, Bit 7, Center 110 (43 ~ 178) 136
3610 11:19:17.250024 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3611 11:19:17.253399 iDelay=195, Bit 9, Center 100 (35 ~ 166) 132
3612 11:19:17.259834 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3613 11:19:17.263178 iDelay=195, Bit 11, Center 102 (35 ~ 170) 136
3614 11:19:17.266655 iDelay=195, Bit 12, Center 118 (55 ~ 182) 128
3615 11:19:17.269926 iDelay=195, Bit 13, Center 116 (51 ~ 182) 132
3616 11:19:17.276312 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3617 11:19:17.279851 iDelay=195, Bit 15, Center 118 (55 ~ 182) 128
3618 11:19:17.279939 ==
3619 11:19:17.283080 Dram Type= 6, Freq= 0, CH_1, rank 1
3620 11:19:17.285916 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3621 11:19:17.286003 ==
3622 11:19:17.289677 DQS Delay:
3623 11:19:17.289760 DQS0 = 0, DQS1 = 0
3624 11:19:17.289826 DQM Delay:
3625 11:19:17.292616 DQM0 = 111, DQM1 = 109
3626 11:19:17.292699 DQ Delay:
3627 11:19:17.296013 DQ0 =114, DQ1 =110, DQ2 =100, DQ3 =108
3628 11:19:17.299395 DQ4 =108, DQ5 =120, DQ6 =120, DQ7 =110
3629 11:19:17.306182 DQ8 =96, DQ9 =100, DQ10 =110, DQ11 =102
3630 11:19:17.309186 DQ12 =118, DQ13 =116, DQ14 =118, DQ15 =118
3631 11:19:17.309301
3632 11:19:17.309400
3633 11:19:17.316058 [DQSOSCAuto] RK1, (LSB)MR18= 0xf405, (MSB)MR19= 0x304, tDQSOscB0 = 408 ps tDQSOscB1 = 415 ps
3634 11:19:17.319254 CH1 RK1: MR19=304, MR18=F405
3635 11:19:17.325812 CH1_RK1: MR19=0x304, MR18=0xF405, DQSOSC=408, MR23=63, INC=39, DEC=26
3636 11:19:17.328867 [RxdqsGatingPostProcess] freq 1200
3637 11:19:17.336033 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3638 11:19:17.336209 best DQS0 dly(2T, 0.5T) = (0, 11)
3639 11:19:17.338790 best DQS1 dly(2T, 0.5T) = (0, 11)
3640 11:19:17.342444 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3641 11:19:17.345465 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3642 11:19:17.348612 best DQS0 dly(2T, 0.5T) = (0, 11)
3643 11:19:17.352111 best DQS1 dly(2T, 0.5T) = (0, 11)
3644 11:19:17.355167 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3645 11:19:17.358729 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3646 11:19:17.361927 Pre-setting of DQS Precalculation
3647 11:19:17.368609 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3648 11:19:17.375064 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3649 11:19:17.381605 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3650 11:19:17.382038
3651 11:19:17.382383
3652 11:19:17.385069 [Calibration Summary] 2400 Mbps
3653 11:19:17.385501 CH 0, Rank 0
3654 11:19:17.388488 SW Impedance : PASS
3655 11:19:17.391763 DUTY Scan : NO K
3656 11:19:17.392193 ZQ Calibration : PASS
3657 11:19:17.395268 Jitter Meter : NO K
3658 11:19:17.397969 CBT Training : PASS
3659 11:19:17.398459 Write leveling : PASS
3660 11:19:17.401504 RX DQS gating : PASS
3661 11:19:17.405053 RX DQ/DQS(RDDQC) : PASS
3662 11:19:17.405528 TX DQ/DQS : PASS
3663 11:19:17.408054 RX DATLAT : PASS
3664 11:19:17.411437 RX DQ/DQS(Engine): PASS
3665 11:19:17.412015 TX OE : NO K
3666 11:19:17.414669 All Pass.
3667 11:19:17.415135
3668 11:19:17.415474 CH 0, Rank 1
3669 11:19:17.418081 SW Impedance : PASS
3670 11:19:17.418505 DUTY Scan : NO K
3671 11:19:17.421502 ZQ Calibration : PASS
3672 11:19:17.424521 Jitter Meter : NO K
3673 11:19:17.424971 CBT Training : PASS
3674 11:19:17.428004 Write leveling : PASS
3675 11:19:17.431295 RX DQS gating : PASS
3676 11:19:17.431679 RX DQ/DQS(RDDQC) : PASS
3677 11:19:17.434598 TX DQ/DQS : PASS
3678 11:19:17.435010 RX DATLAT : PASS
3679 11:19:17.437898 RX DQ/DQS(Engine): PASS
3680 11:19:17.441117 TX OE : NO K
3681 11:19:17.441560 All Pass.
3682 11:19:17.441904
3683 11:19:17.442221 CH 1, Rank 0
3684 11:19:17.444662 SW Impedance : PASS
3685 11:19:17.447406 DUTY Scan : NO K
3686 11:19:17.447490 ZQ Calibration : PASS
3687 11:19:17.450557 Jitter Meter : NO K
3688 11:19:17.454070 CBT Training : PASS
3689 11:19:17.454153 Write leveling : PASS
3690 11:19:17.457578 RX DQS gating : PASS
3691 11:19:17.460752 RX DQ/DQS(RDDQC) : PASS
3692 11:19:17.460836 TX DQ/DQS : PASS
3693 11:19:17.463875 RX DATLAT : PASS
3694 11:19:17.467227 RX DQ/DQS(Engine): PASS
3695 11:19:17.467310 TX OE : NO K
3696 11:19:17.470645 All Pass.
3697 11:19:17.470728
3698 11:19:17.470793 CH 1, Rank 1
3699 11:19:17.473982 SW Impedance : PASS
3700 11:19:17.474065 DUTY Scan : NO K
3701 11:19:17.477402 ZQ Calibration : PASS
3702 11:19:17.480602 Jitter Meter : NO K
3703 11:19:17.480686 CBT Training : PASS
3704 11:19:17.483605 Write leveling : PASS
3705 11:19:17.486850 RX DQS gating : PASS
3706 11:19:17.486939 RX DQ/DQS(RDDQC) : PASS
3707 11:19:17.490306 TX DQ/DQS : PASS
3708 11:19:17.493799 RX DATLAT : PASS
3709 11:19:17.493908 RX DQ/DQS(Engine): PASS
3710 11:19:17.496778 TX OE : NO K
3711 11:19:17.496888 All Pass.
3712 11:19:17.496986
3713 11:19:17.500365 DramC Write-DBI off
3714 11:19:17.503632 PER_BANK_REFRESH: Hybrid Mode
3715 11:19:17.503716 TX_TRACKING: ON
3716 11:19:17.513480 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3717 11:19:17.516464 [FAST_K] Save calibration result to emmc
3718 11:19:17.519636 dramc_set_vcore_voltage set vcore to 650000
3719 11:19:17.523165 Read voltage for 600, 5
3720 11:19:17.523248 Vio18 = 0
3721 11:19:17.523314 Vcore = 650000
3722 11:19:17.526569 Vdram = 0
3723 11:19:17.526652 Vddq = 0
3724 11:19:17.526717 Vmddr = 0
3725 11:19:17.533295 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3726 11:19:17.536356 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3727 11:19:17.539907 MEM_TYPE=3, freq_sel=19
3728 11:19:17.542806 sv_algorithm_assistance_LP4_1600
3729 11:19:17.546304 ============ PULL DRAM RESETB DOWN ============
3730 11:19:17.549390 ========== PULL DRAM RESETB DOWN end =========
3731 11:19:17.556298 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3732 11:19:17.559691 ===================================
3733 11:19:17.562666 LPDDR4 DRAM CONFIGURATION
3734 11:19:17.566339 ===================================
3735 11:19:17.566423 EX_ROW_EN[0] = 0x0
3736 11:19:17.569467 EX_ROW_EN[1] = 0x0
3737 11:19:17.569550 LP4Y_EN = 0x0
3738 11:19:17.572893 WORK_FSP = 0x0
3739 11:19:17.572976 WL = 0x2
3740 11:19:17.575999 RL = 0x2
3741 11:19:17.576082 BL = 0x2
3742 11:19:17.579548 RPST = 0x0
3743 11:19:17.579630 RD_PRE = 0x0
3744 11:19:17.582387 WR_PRE = 0x1
3745 11:19:17.582469 WR_PST = 0x0
3746 11:19:17.586263 DBI_WR = 0x0
3747 11:19:17.586345 DBI_RD = 0x0
3748 11:19:17.589307 OTF = 0x1
3749 11:19:17.592800 ===================================
3750 11:19:17.595651 ===================================
3751 11:19:17.595732 ANA top config
3752 11:19:17.598990 ===================================
3753 11:19:17.602518 DLL_ASYNC_EN = 0
3754 11:19:17.605877 ALL_SLAVE_EN = 1
3755 11:19:17.609079 NEW_RANK_MODE = 1
3756 11:19:17.612265 DLL_IDLE_MODE = 1
3757 11:19:17.612374 LP45_APHY_COMB_EN = 1
3758 11:19:17.615661 TX_ODT_DIS = 1
3759 11:19:17.618748 NEW_8X_MODE = 1
3760 11:19:17.622233 ===================================
3761 11:19:17.625142 ===================================
3762 11:19:17.628918 data_rate = 1200
3763 11:19:17.632548 CKR = 1
3764 11:19:17.632655 DQ_P2S_RATIO = 8
3765 11:19:17.635391 ===================================
3766 11:19:17.638264 CA_P2S_RATIO = 8
3767 11:19:17.641965 DQ_CA_OPEN = 0
3768 11:19:17.644927 DQ_SEMI_OPEN = 0
3769 11:19:17.648354 CA_SEMI_OPEN = 0
3770 11:19:17.651763 CA_FULL_RATE = 0
3771 11:19:17.654898 DQ_CKDIV4_EN = 1
3772 11:19:17.654990 CA_CKDIV4_EN = 1
3773 11:19:17.658671 CA_PREDIV_EN = 0
3774 11:19:17.661514 PH8_DLY = 0
3775 11:19:17.664531 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3776 11:19:17.668266 DQ_AAMCK_DIV = 4
3777 11:19:17.671742 CA_AAMCK_DIV = 4
3778 11:19:17.671838 CA_ADMCK_DIV = 4
3779 11:19:17.674712 DQ_TRACK_CA_EN = 0
3780 11:19:17.677595 CA_PICK = 600
3781 11:19:17.681343 CA_MCKIO = 600
3782 11:19:17.684235 MCKIO_SEMI = 0
3783 11:19:17.687772 PLL_FREQ = 2288
3784 11:19:17.691227 DQ_UI_PI_RATIO = 32
3785 11:19:17.691343 CA_UI_PI_RATIO = 0
3786 11:19:17.694452 ===================================
3787 11:19:17.697794 ===================================
3788 11:19:17.701129 memory_type:LPDDR4
3789 11:19:17.703953 GP_NUM : 10
3790 11:19:17.704041 SRAM_EN : 1
3791 11:19:17.707415 MD32_EN : 0
3792 11:19:17.710944 ===================================
3793 11:19:17.713789 [ANA_INIT] >>>>>>>>>>>>>>
3794 11:19:17.717112 <<<<<< [CONFIGURE PHASE]: ANA_TX
3795 11:19:17.720455 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3796 11:19:17.723964 ===================================
3797 11:19:17.727373 data_rate = 1200,PCW = 0X5800
3798 11:19:17.730325 ===================================
3799 11:19:17.734101 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3800 11:19:17.737043 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3801 11:19:17.744429 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3802 11:19:17.747937 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3803 11:19:17.750793 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3804 11:19:17.754221 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3805 11:19:17.757150 [ANA_INIT] flow start
3806 11:19:17.760880 [ANA_INIT] PLL >>>>>>>>
3807 11:19:17.761337 [ANA_INIT] PLL <<<<<<<<
3808 11:19:17.763855 [ANA_INIT] MIDPI >>>>>>>>
3809 11:19:17.767570 [ANA_INIT] MIDPI <<<<<<<<
3810 11:19:17.770497 [ANA_INIT] DLL >>>>>>>>
3811 11:19:17.770983 [ANA_INIT] flow end
3812 11:19:17.774362 ============ LP4 DIFF to SE enter ============
3813 11:19:17.780572 ============ LP4 DIFF to SE exit ============
3814 11:19:17.781008 [ANA_INIT] <<<<<<<<<<<<<
3815 11:19:17.783632 [Flow] Enable top DCM control >>>>>
3816 11:19:17.787257 [Flow] Enable top DCM control <<<<<
3817 11:19:17.790189 Enable DLL master slave shuffle
3818 11:19:17.796754 ==============================================================
3819 11:19:17.797179 Gating Mode config
3820 11:19:17.803571 ==============================================================
3821 11:19:17.806365 Config description:
3822 11:19:17.816563 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3823 11:19:17.822900 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3824 11:19:17.826161 SELPH_MODE 0: By rank 1: By Phase
3825 11:19:17.833036 ==============================================================
3826 11:19:17.836157 GAT_TRACK_EN = 1
3827 11:19:17.839410 RX_GATING_MODE = 2
3828 11:19:17.839984 RX_GATING_TRACK_MODE = 2
3829 11:19:17.843283 SELPH_MODE = 1
3830 11:19:17.845984 PICG_EARLY_EN = 1
3831 11:19:17.849483 VALID_LAT_VALUE = 1
3832 11:19:17.856649 ==============================================================
3833 11:19:17.859081 Enter into Gating configuration >>>>
3834 11:19:17.862622 Exit from Gating configuration <<<<
3835 11:19:17.866172 Enter into DVFS_PRE_config >>>>>
3836 11:19:17.875820 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3837 11:19:17.878990 Exit from DVFS_PRE_config <<<<<
3838 11:19:17.882351 Enter into PICG configuration >>>>
3839 11:19:17.885385 Exit from PICG configuration <<<<
3840 11:19:17.889283 [RX_INPUT] configuration >>>>>
3841 11:19:17.892209 [RX_INPUT] configuration <<<<<
3842 11:19:17.895646 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3843 11:19:17.901919 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3844 11:19:17.908932 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3845 11:19:17.915272 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3846 11:19:17.922121 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3847 11:19:17.928257 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3848 11:19:17.931945 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3849 11:19:17.934884 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3850 11:19:17.938248 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3851 11:19:17.945306 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3852 11:19:17.948283 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3853 11:19:17.951217 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3854 11:19:17.954566 ===================================
3855 11:19:17.957681 LPDDR4 DRAM CONFIGURATION
3856 11:19:17.961145 ===================================
3857 11:19:17.961229 EX_ROW_EN[0] = 0x0
3858 11:19:17.964496 EX_ROW_EN[1] = 0x0
3859 11:19:17.967699 LP4Y_EN = 0x0
3860 11:19:17.967781 WORK_FSP = 0x0
3861 11:19:17.971245 WL = 0x2
3862 11:19:17.971328 RL = 0x2
3863 11:19:17.974035 BL = 0x2
3864 11:19:17.974131 RPST = 0x0
3865 11:19:17.977643 RD_PRE = 0x0
3866 11:19:17.977726 WR_PRE = 0x1
3867 11:19:17.980835 WR_PST = 0x0
3868 11:19:17.980918 DBI_WR = 0x0
3869 11:19:17.984393 DBI_RD = 0x0
3870 11:19:17.984475 OTF = 0x1
3871 11:19:17.987338 ===================================
3872 11:19:17.990737 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3873 11:19:17.997425 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3874 11:19:18.000373 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3875 11:19:18.004052 ===================================
3876 11:19:18.007102 LPDDR4 DRAM CONFIGURATION
3877 11:19:18.010589 ===================================
3878 11:19:18.010678 EX_ROW_EN[0] = 0x10
3879 11:19:18.013994 EX_ROW_EN[1] = 0x0
3880 11:19:18.016976 LP4Y_EN = 0x0
3881 11:19:18.017072 WORK_FSP = 0x0
3882 11:19:18.020467 WL = 0x2
3883 11:19:18.020570 RL = 0x2
3884 11:19:18.023445 BL = 0x2
3885 11:19:18.023548 RPST = 0x0
3886 11:19:18.027173 RD_PRE = 0x0
3887 11:19:18.027287 WR_PRE = 0x1
3888 11:19:18.030620 WR_PST = 0x0
3889 11:19:18.030745 DBI_WR = 0x0
3890 11:19:18.033843 DBI_RD = 0x0
3891 11:19:18.033967 OTF = 0x1
3892 11:19:18.036824 ===================================
3893 11:19:18.043410 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3894 11:19:18.048091 nWR fixed to 30
3895 11:19:18.051254 [ModeRegInit_LP4] CH0 RK0
3896 11:19:18.051458 [ModeRegInit_LP4] CH0 RK1
3897 11:19:18.054481 [ModeRegInit_LP4] CH1 RK0
3898 11:19:18.058050 [ModeRegInit_LP4] CH1 RK1
3899 11:19:18.058294 match AC timing 17
3900 11:19:18.064617 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3901 11:19:18.068233 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3902 11:19:18.071202 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3903 11:19:18.078407 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3904 11:19:18.081587 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3905 11:19:18.082018 ==
3906 11:19:18.084760 Dram Type= 6, Freq= 0, CH_0, rank 0
3907 11:19:18.087775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3908 11:19:18.088237 ==
3909 11:19:18.094553 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3910 11:19:18.101179 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
3911 11:19:18.104464 [CA 0] Center 37 (7~67) winsize 61
3912 11:19:18.107666 [CA 1] Center 37 (7~67) winsize 61
3913 11:19:18.110916 [CA 2] Center 35 (5~65) winsize 61
3914 11:19:18.114101 [CA 3] Center 35 (5~65) winsize 61
3915 11:19:18.117376 [CA 4] Center 34 (4~65) winsize 62
3916 11:19:18.120487 [CA 5] Center 34 (4~64) winsize 61
3917 11:19:18.120967
3918 11:19:18.124506 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3919 11:19:18.125134
3920 11:19:18.127523 [CATrainingPosCal] consider 1 rank data
3921 11:19:18.130559 u2DelayCellTimex100 = 270/100 ps
3922 11:19:18.133816 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3923 11:19:18.137196 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3924 11:19:18.140623 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3925 11:19:18.146961 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3926 11:19:18.150779 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3927 11:19:18.153648 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3928 11:19:18.154180
3929 11:19:18.156935 CA PerBit enable=1, Macro0, CA PI delay=34
3930 11:19:18.157365
3931 11:19:18.160279 [CBTSetCACLKResult] CA Dly = 34
3932 11:19:18.160732 CS Dly: 6 (0~37)
3933 11:19:18.161126 ==
3934 11:19:18.164057 Dram Type= 6, Freq= 0, CH_0, rank 1
3935 11:19:18.170076 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3936 11:19:18.170681 ==
3937 11:19:18.173526 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3938 11:19:18.179892 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3939 11:19:18.183638 [CA 0] Center 37 (7~67) winsize 61
3940 11:19:18.187404 [CA 1] Center 37 (7~67) winsize 61
3941 11:19:18.190269 [CA 2] Center 35 (5~65) winsize 61
3942 11:19:18.193123 [CA 3] Center 35 (5~65) winsize 61
3943 11:19:18.196352 [CA 4] Center 34 (4~65) winsize 62
3944 11:19:18.200064 [CA 5] Center 33 (3~64) winsize 62
3945 11:19:18.200138
3946 11:19:18.202949 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3947 11:19:18.203023
3948 11:19:18.206429 [CATrainingPosCal] consider 2 rank data
3949 11:19:18.209473 u2DelayCellTimex100 = 270/100 ps
3950 11:19:18.212642 CA0 delay=37 (7~67),Diff = 3 PI (28 cell)
3951 11:19:18.219097 CA1 delay=37 (7~67),Diff = 3 PI (28 cell)
3952 11:19:18.222721 CA2 delay=35 (5~65),Diff = 1 PI (9 cell)
3953 11:19:18.225709 CA3 delay=35 (5~65),Diff = 1 PI (9 cell)
3954 11:19:18.229374 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3955 11:19:18.232438 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3956 11:19:18.232546
3957 11:19:18.235544 CA PerBit enable=1, Macro0, CA PI delay=34
3958 11:19:18.235638
3959 11:19:18.239050 [CBTSetCACLKResult] CA Dly = 34
3960 11:19:18.242311 CS Dly: 5 (0~36)
3961 11:19:18.242414
3962 11:19:18.245692 ----->DramcWriteLeveling(PI) begin...
3963 11:19:18.245770 ==
3964 11:19:18.249046 Dram Type= 6, Freq= 0, CH_0, rank 0
3965 11:19:18.252386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3966 11:19:18.252471 ==
3967 11:19:18.255836 Write leveling (Byte 0): 31 => 31
3968 11:19:18.259096 Write leveling (Byte 1): 30 => 30
3969 11:19:18.262251 DramcWriteLeveling(PI) end<-----
3970 11:19:18.262325
3971 11:19:18.262387 ==
3972 11:19:18.265662 Dram Type= 6, Freq= 0, CH_0, rank 0
3973 11:19:18.268706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3974 11:19:18.268785 ==
3975 11:19:18.272230 [Gating] SW mode calibration
3976 11:19:18.278938 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3977 11:19:18.285636 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3978 11:19:18.288809 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3979 11:19:18.291625 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3980 11:19:18.298465 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3981 11:19:18.301973 0 9 12 | B1->B0 | 3333 3030 | 1 1 | (1 1) (1 1)
3982 11:19:18.304884 0 9 16 | B1->B0 | 3434 2c2c | 0 0 | (0 1) (0 0)
3983 11:19:18.311457 0 9 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
3984 11:19:18.315152 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3985 11:19:18.318101 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3986 11:19:18.324785 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3987 11:19:18.328544 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3988 11:19:18.331595 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3989 11:19:18.338079 0 10 12 | B1->B0 | 2323 2c2c | 0 0 | (0 0) (0 0)
3990 11:19:18.341559 0 10 16 | B1->B0 | 3030 4141 | 0 0 | (1 1) (0 0)
3991 11:19:18.344890 0 10 20 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
3992 11:19:18.351253 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3993 11:19:18.354601 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3994 11:19:18.358416 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3995 11:19:18.364941 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3996 11:19:18.367851 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3997 11:19:18.371070 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3998 11:19:18.377715 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3999 11:19:18.380813 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 11:19:18.387634 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 11:19:18.391112 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 11:19:18.394757 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 11:19:18.397505 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 11:19:18.404495 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 11:19:18.407428 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 11:19:18.410407 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 11:19:18.417258 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 11:19:18.420863 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4009 11:19:18.423936 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4010 11:19:18.430311 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4011 11:19:18.433986 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4012 11:19:18.440768 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4013 11:19:18.443914 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
4014 11:19:18.446725 Total UI for P1: 0, mck2ui 16
4015 11:19:18.450118 best dqsien dly found for B0: ( 0, 13, 10)
4016 11:19:18.453428 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4017 11:19:18.457109 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4018 11:19:18.460055 Total UI for P1: 0, mck2ui 16
4019 11:19:18.463409 best dqsien dly found for B1: ( 0, 13, 16)
4020 11:19:18.469836 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4021 11:19:18.473115 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4022 11:19:18.473774
4023 11:19:18.476515 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4024 11:19:18.480098 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4025 11:19:18.483420 [Gating] SW calibration Done
4026 11:19:18.483844 ==
4027 11:19:18.486397 Dram Type= 6, Freq= 0, CH_0, rank 0
4028 11:19:18.489989 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4029 11:19:18.490588 ==
4030 11:19:18.493289 RX Vref Scan: 0
4031 11:19:18.493814
4032 11:19:18.494158 RX Vref 0 -> 0, step: 1
4033 11:19:18.494472
4034 11:19:18.496182 RX Delay -230 -> 252, step: 16
4035 11:19:18.503135 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4036 11:19:18.505905 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4037 11:19:18.509574 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4038 11:19:18.512774 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4039 11:19:18.516158 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4040 11:19:18.522680 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4041 11:19:18.525862 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4042 11:19:18.528856 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4043 11:19:18.532268 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4044 11:19:18.539043 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4045 11:19:18.542908 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4046 11:19:18.545650 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4047 11:19:18.549580 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4048 11:19:18.555288 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4049 11:19:18.558861 iDelay=218, Bit 14, Center 41 (-134 ~ 217) 352
4050 11:19:18.562182 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4051 11:19:18.562717 ==
4052 11:19:18.565773 Dram Type= 6, Freq= 0, CH_0, rank 0
4053 11:19:18.571628 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4054 11:19:18.572152 ==
4055 11:19:18.572498 DQS Delay:
4056 11:19:18.573028 DQS0 = 0, DQS1 = 0
4057 11:19:18.575130 DQM Delay:
4058 11:19:18.575566 DQM0 = 37, DQM1 = 29
4059 11:19:18.578246 DQ Delay:
4060 11:19:18.581561 DQ0 =33, DQ1 =41, DQ2 =33, DQ3 =33
4061 11:19:18.584995 DQ4 =33, DQ5 =25, DQ6 =49, DQ7 =49
4062 11:19:18.588558 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4063 11:19:18.591497 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4064 11:19:18.591956
4065 11:19:18.592292
4066 11:19:18.592615 ==
4067 11:19:18.595001 Dram Type= 6, Freq= 0, CH_0, rank 0
4068 11:19:18.598127 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4069 11:19:18.598708 ==
4070 11:19:18.599204
4071 11:19:18.599737
4072 11:19:18.601772 TX Vref Scan disable
4073 11:19:18.602313 == TX Byte 0 ==
4074 11:19:18.608257 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4075 11:19:18.611270 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4076 11:19:18.614811 == TX Byte 1 ==
4077 11:19:18.617835 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4078 11:19:18.620882 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4079 11:19:18.621496 ==
4080 11:19:18.624233 Dram Type= 6, Freq= 0, CH_0, rank 0
4081 11:19:18.627772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4082 11:19:18.630806 ==
4083 11:19:18.631353
4084 11:19:18.631755
4085 11:19:18.632092 TX Vref Scan disable
4086 11:19:18.634980 == TX Byte 0 ==
4087 11:19:18.638340 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4088 11:19:18.645063 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4089 11:19:18.645494 == TX Byte 1 ==
4090 11:19:18.648258 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4091 11:19:18.654993 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4092 11:19:18.655487
4093 11:19:18.655864 [DATLAT]
4094 11:19:18.656269 Freq=600, CH0 RK0
4095 11:19:18.656633
4096 11:19:18.658318 DATLAT Default: 0x9
4097 11:19:18.658874 0, 0xFFFF, sum = 0
4098 11:19:18.661353 1, 0xFFFF, sum = 0
4099 11:19:18.664911 2, 0xFFFF, sum = 0
4100 11:19:18.665345 3, 0xFFFF, sum = 0
4101 11:19:18.667976 4, 0xFFFF, sum = 0
4102 11:19:18.668440 5, 0xFFFF, sum = 0
4103 11:19:18.671538 6, 0xFFFF, sum = 0
4104 11:19:18.672009 7, 0xFFFF, sum = 0
4105 11:19:18.674866 8, 0x0, sum = 1
4106 11:19:18.675302 9, 0x0, sum = 2
4107 11:19:18.677650 10, 0x0, sum = 3
4108 11:19:18.678080 11, 0x0, sum = 4
4109 11:19:18.678556 best_step = 9
4110 11:19:18.678920
4111 11:19:18.681104 ==
4112 11:19:18.681532 Dram Type= 6, Freq= 0, CH_0, rank 0
4113 11:19:18.687807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4114 11:19:18.688267 ==
4115 11:19:18.688607 RX Vref Scan: 1
4116 11:19:18.688920
4117 11:19:18.691085 RX Vref 0 -> 0, step: 1
4118 11:19:18.691510
4119 11:19:18.694551 RX Delay -195 -> 252, step: 8
4120 11:19:18.695010
4121 11:19:18.697808 Set Vref, RX VrefLevel [Byte0]: 61
4122 11:19:18.700899 [Byte1]: 57
4123 11:19:18.701419
4124 11:19:18.703951 Final RX Vref Byte 0 = 61 to rank0
4125 11:19:18.707427 Final RX Vref Byte 1 = 57 to rank0
4126 11:19:18.711060 Final RX Vref Byte 0 = 61 to rank1
4127 11:19:18.714199 Final RX Vref Byte 1 = 57 to rank1==
4128 11:19:18.717704 Dram Type= 6, Freq= 0, CH_0, rank 0
4129 11:19:18.720694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4130 11:19:18.723804 ==
4131 11:19:18.724375 DQS Delay:
4132 11:19:18.724952 DQS0 = 0, DQS1 = 0
4133 11:19:18.727453 DQM Delay:
4134 11:19:18.728129 DQM0 = 35, DQM1 = 29
4135 11:19:18.730880 DQ Delay:
4136 11:19:18.731339 DQ0 =36, DQ1 =36, DQ2 =36, DQ3 =32
4137 11:19:18.733884 DQ4 =32, DQ5 =24, DQ6 =40, DQ7 =44
4138 11:19:18.736977 DQ8 =20, DQ9 =16, DQ10 =28, DQ11 =20
4139 11:19:18.740607 DQ12 =36, DQ13 =36, DQ14 =40, DQ15 =36
4140 11:19:18.744052
4141 11:19:18.744553
4142 11:19:18.750608 [DQSOSCAuto] RK0, (LSB)MR18= 0x3838, (MSB)MR19= 0x808, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
4143 11:19:18.753684 CH0 RK0: MR19=808, MR18=3838
4144 11:19:18.760174 CH0_RK0: MR19=0x808, MR18=0x3838, DQSOSC=399, MR23=63, INC=164, DEC=109
4145 11:19:18.760634
4146 11:19:18.763971 ----->DramcWriteLeveling(PI) begin...
4147 11:19:18.764482 ==
4148 11:19:18.767514 Dram Type= 6, Freq= 0, CH_0, rank 1
4149 11:19:18.770328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4150 11:19:18.770757 ==
4151 11:19:18.774101 Write leveling (Byte 0): 32 => 32
4152 11:19:18.776700 Write leveling (Byte 1): 31 => 31
4153 11:19:18.780179 DramcWriteLeveling(PI) end<-----
4154 11:19:18.780608
4155 11:19:18.780945 ==
4156 11:19:18.783821 Dram Type= 6, Freq= 0, CH_0, rank 1
4157 11:19:18.786672 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4158 11:19:18.787130 ==
4159 11:19:18.790026 [Gating] SW mode calibration
4160 11:19:18.796361 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4161 11:19:18.803160 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4162 11:19:18.806762 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4163 11:19:18.813234 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4164 11:19:18.816261 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4165 11:19:18.819491 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
4166 11:19:18.826200 0 9 16 | B1->B0 | 2f2f 2424 | 0 0 | (0 0) (0 0)
4167 11:19:18.829666 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4168 11:19:18.833175 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4169 11:19:18.839847 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4170 11:19:18.842783 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4171 11:19:18.846246 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4172 11:19:18.852817 0 10 8 | B1->B0 | 2323 2424 | 0 1 | (0 0) (0 0)
4173 11:19:18.856018 0 10 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
4174 11:19:18.859196 0 10 16 | B1->B0 | 3838 4646 | 1 0 | (1 1) (0 0)
4175 11:19:18.865895 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4176 11:19:18.869364 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4177 11:19:18.872570 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4178 11:19:18.878891 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4179 11:19:18.882729 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4180 11:19:18.885582 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4181 11:19:18.892654 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4182 11:19:18.895932 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4183 11:19:18.898620 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 11:19:18.905653 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 11:19:18.908752 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 11:19:18.912166 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 11:19:18.918563 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 11:19:18.921563 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 11:19:18.924987 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 11:19:18.931351 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 11:19:18.934887 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 11:19:18.937865 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4193 11:19:18.944443 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4194 11:19:18.948030 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4195 11:19:18.950957 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4196 11:19:18.957544 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4197 11:19:18.961186 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4198 11:19:18.964292 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4199 11:19:18.967374 Total UI for P1: 0, mck2ui 16
4200 11:19:18.970817 best dqsien dly found for B0: ( 0, 13, 12)
4201 11:19:18.977656 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4202 11:19:18.977739 Total UI for P1: 0, mck2ui 16
4203 11:19:18.981175 best dqsien dly found for B1: ( 0, 13, 16)
4204 11:19:18.987724 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4205 11:19:18.990759 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4206 11:19:18.990870
4207 11:19:18.994315 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4208 11:19:18.997458 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4209 11:19:19.000592 [Gating] SW calibration Done
4210 11:19:19.000759 ==
4211 11:19:19.003972 Dram Type= 6, Freq= 0, CH_0, rank 1
4212 11:19:19.007244 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4213 11:19:19.007321 ==
4214 11:19:19.010658 RX Vref Scan: 0
4215 11:19:19.010756
4216 11:19:19.010868 RX Vref 0 -> 0, step: 1
4217 11:19:19.010958
4218 11:19:19.013559 RX Delay -230 -> 252, step: 16
4219 11:19:19.020259 iDelay=218, Bit 0, Center 33 (-134 ~ 201) 336
4220 11:19:19.023625 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4221 11:19:19.026707 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4222 11:19:19.030093 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4223 11:19:19.036405 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4224 11:19:19.039812 iDelay=218, Bit 5, Center 25 (-134 ~ 185) 320
4225 11:19:19.043223 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4226 11:19:19.046131 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4227 11:19:19.052710 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4228 11:19:19.056420 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4229 11:19:19.059405 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4230 11:19:19.062993 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4231 11:19:19.069271 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4232 11:19:19.072875 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4233 11:19:19.075650 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4234 11:19:19.079325 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4235 11:19:19.079400 ==
4236 11:19:19.082566 Dram Type= 6, Freq= 0, CH_0, rank 1
4237 11:19:19.089404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4238 11:19:19.089482 ==
4239 11:19:19.089547 DQS Delay:
4240 11:19:19.092282 DQS0 = 0, DQS1 = 0
4241 11:19:19.092353 DQM Delay:
4242 11:19:19.092413 DQM0 = 36, DQM1 = 29
4243 11:19:19.095863 DQ Delay:
4244 11:19:19.098790 DQ0 =33, DQ1 =33, DQ2 =33, DQ3 =33
4245 11:19:19.102581 DQ4 =33, DQ5 =25, DQ6 =49, DQ7 =49
4246 11:19:19.105791 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4247 11:19:19.108636 DQ12 =33, DQ13 =33, DQ14 =41, DQ15 =33
4248 11:19:19.108718
4249 11:19:19.108782
4250 11:19:19.108842 ==
4251 11:19:19.111891 Dram Type= 6, Freq= 0, CH_0, rank 1
4252 11:19:19.115726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4253 11:19:19.115809 ==
4254 11:19:19.115873
4255 11:19:19.115933
4256 11:19:19.118953 TX Vref Scan disable
4257 11:19:19.121848 == TX Byte 0 ==
4258 11:19:19.125287 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4259 11:19:19.128817 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4260 11:19:19.131802 == TX Byte 1 ==
4261 11:19:19.135288 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4262 11:19:19.138842 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4263 11:19:19.138955 ==
4264 11:19:19.141670 Dram Type= 6, Freq= 0, CH_0, rank 1
4265 11:19:19.148494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4266 11:19:19.148576 ==
4267 11:19:19.148641
4268 11:19:19.148699
4269 11:19:19.148757 TX Vref Scan disable
4270 11:19:19.152558 == TX Byte 0 ==
4271 11:19:19.155555 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4272 11:19:19.162675 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4273 11:19:19.162784 == TX Byte 1 ==
4274 11:19:19.165819 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4275 11:19:19.171969 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4276 11:19:19.172057
4277 11:19:19.172126 [DATLAT]
4278 11:19:19.172189 Freq=600, CH0 RK1
4279 11:19:19.172252
4280 11:19:19.175838 DATLAT Default: 0x9
4281 11:19:19.178885 0, 0xFFFF, sum = 0
4282 11:19:19.178996 1, 0xFFFF, sum = 0
4283 11:19:19.182151 2, 0xFFFF, sum = 0
4284 11:19:19.182254 3, 0xFFFF, sum = 0
4285 11:19:19.185699 4, 0xFFFF, sum = 0
4286 11:19:19.185819 5, 0xFFFF, sum = 0
4287 11:19:19.188821 6, 0xFFFF, sum = 0
4288 11:19:19.188933 7, 0xFFFF, sum = 0
4289 11:19:19.191925 8, 0x0, sum = 1
4290 11:19:19.192050 9, 0x0, sum = 2
4291 11:19:19.195326 10, 0x0, sum = 3
4292 11:19:19.195463 11, 0x0, sum = 4
4293 11:19:19.195570 best_step = 9
4294 11:19:19.195667
4295 11:19:19.198416 ==
4296 11:19:19.202156 Dram Type= 6, Freq= 0, CH_0, rank 1
4297 11:19:19.205035 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4298 11:19:19.205184 ==
4299 11:19:19.205303 RX Vref Scan: 0
4300 11:19:19.205412
4301 11:19:19.208823 RX Vref 0 -> 0, step: 1
4302 11:19:19.208971
4303 11:19:19.211639 RX Delay -195 -> 252, step: 8
4304 11:19:19.218407 iDelay=205, Bit 0, Center 32 (-123 ~ 188) 312
4305 11:19:19.221629 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4306 11:19:19.224671 iDelay=205, Bit 2, Center 32 (-123 ~ 188) 312
4307 11:19:19.228037 iDelay=205, Bit 3, Center 28 (-131 ~ 188) 320
4308 11:19:19.234721 iDelay=205, Bit 4, Center 32 (-123 ~ 188) 312
4309 11:19:19.238212 iDelay=205, Bit 5, Center 24 (-131 ~ 180) 312
4310 11:19:19.241199 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4311 11:19:19.244622 iDelay=205, Bit 7, Center 44 (-115 ~ 204) 320
4312 11:19:19.248066 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4313 11:19:19.254352 iDelay=205, Bit 9, Center 12 (-147 ~ 172) 320
4314 11:19:19.257884 iDelay=205, Bit 10, Center 28 (-131 ~ 188) 320
4315 11:19:19.261384 iDelay=205, Bit 11, Center 20 (-139 ~ 180) 320
4316 11:19:19.264510 iDelay=205, Bit 12, Center 32 (-131 ~ 196) 328
4317 11:19:19.271490 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4318 11:19:19.274413 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4319 11:19:19.277548 iDelay=205, Bit 15, Center 32 (-131 ~ 196) 328
4320 11:19:19.277648 ==
4321 11:19:19.281083 Dram Type= 6, Freq= 0, CH_0, rank 1
4322 11:19:19.287665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4323 11:19:19.287784 ==
4324 11:19:19.287878 DQS Delay:
4325 11:19:19.287965 DQS0 = 0, DQS1 = 0
4326 11:19:19.290769 DQM Delay:
4327 11:19:19.290916 DQM0 = 34, DQM1 = 27
4328 11:19:19.294196 DQ Delay:
4329 11:19:19.297664 DQ0 =32, DQ1 =36, DQ2 =32, DQ3 =28
4330 11:19:19.300809 DQ4 =32, DQ5 =24, DQ6 =44, DQ7 =44
4331 11:19:19.300980 DQ8 =20, DQ9 =12, DQ10 =28, DQ11 =20
4332 11:19:19.307579 DQ12 =32, DQ13 =36, DQ14 =36, DQ15 =32
4333 11:19:19.307780
4334 11:19:19.307934
4335 11:19:19.314085 [DQSOSCAuto] RK1, (LSB)MR18= 0x6634, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 390 ps
4336 11:19:19.317406 CH0 RK1: MR19=808, MR18=6634
4337 11:19:19.323872 CH0_RK1: MR19=0x808, MR18=0x6634, DQSOSC=390, MR23=63, INC=172, DEC=114
4338 11:19:19.326902 [RxdqsGatingPostProcess] freq 600
4339 11:19:19.330394 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4340 11:19:19.333648 Pre-setting of DQS Precalculation
4341 11:19:19.340553 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4342 11:19:19.340635 ==
4343 11:19:19.343571 Dram Type= 6, Freq= 0, CH_1, rank 0
4344 11:19:19.346547 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4345 11:19:19.346628 ==
4346 11:19:19.353484 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4347 11:19:19.359996 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4348 11:19:19.363362 [CA 0] Center 35 (5~66) winsize 62
4349 11:19:19.366848 [CA 1] Center 35 (5~66) winsize 62
4350 11:19:19.370275 [CA 2] Center 34 (4~65) winsize 62
4351 11:19:19.373129 [CA 3] Center 34 (4~65) winsize 62
4352 11:19:19.376508 [CA 4] Center 34 (4~65) winsize 62
4353 11:19:19.379966 [CA 5] Center 34 (4~64) winsize 61
4354 11:19:19.380055
4355 11:19:19.382891 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4356 11:19:19.382980
4357 11:19:19.386885 [CATrainingPosCal] consider 1 rank data
4358 11:19:19.389885 u2DelayCellTimex100 = 270/100 ps
4359 11:19:19.393370 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4360 11:19:19.396941 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4361 11:19:19.399897 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4362 11:19:19.403177 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4363 11:19:19.406598 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4364 11:19:19.409628 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4365 11:19:19.410054
4366 11:19:19.416349 CA PerBit enable=1, Macro0, CA PI delay=34
4367 11:19:19.416776
4368 11:19:19.420281 [CBTSetCACLKResult] CA Dly = 34
4369 11:19:19.420710 CS Dly: 5 (0~36)
4370 11:19:19.421047 ==
4371 11:19:19.423285 Dram Type= 6, Freq= 0, CH_1, rank 1
4372 11:19:19.426268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4373 11:19:19.426699 ==
4374 11:19:19.432864 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4375 11:19:19.439079 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4376 11:19:19.442883 [CA 0] Center 35 (5~66) winsize 62
4377 11:19:19.446288 [CA 1] Center 36 (5~67) winsize 63
4378 11:19:19.449189 [CA 2] Center 34 (4~65) winsize 62
4379 11:19:19.452383 [CA 3] Center 34 (3~65) winsize 63
4380 11:19:19.455793 [CA 4] Center 34 (4~65) winsize 62
4381 11:19:19.458973 [CA 5] Center 34 (3~65) winsize 63
4382 11:19:19.459492
4383 11:19:19.462530 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4384 11:19:19.463092
4385 11:19:19.465353 [CATrainingPosCal] consider 2 rank data
4386 11:19:19.468912 u2DelayCellTimex100 = 270/100 ps
4387 11:19:19.472216 CA0 delay=35 (5~66),Diff = 1 PI (9 cell)
4388 11:19:19.475474 CA1 delay=35 (5~66),Diff = 1 PI (9 cell)
4389 11:19:19.478800 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4390 11:19:19.485388 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4391 11:19:19.488542 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4392 11:19:19.491974 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
4393 11:19:19.492498
4394 11:19:19.494908 CA PerBit enable=1, Macro0, CA PI delay=34
4395 11:19:19.495598
4396 11:19:19.498485 [CBTSetCACLKResult] CA Dly = 34
4397 11:19:19.499119 CS Dly: 5 (0~37)
4398 11:19:19.499642
4399 11:19:19.501651 ----->DramcWriteLeveling(PI) begin...
4400 11:19:19.504865 ==
4401 11:19:19.505344 Dram Type= 6, Freq= 0, CH_1, rank 0
4402 11:19:19.511559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4403 11:19:19.512015 ==
4404 11:19:19.515262 Write leveling (Byte 0): 28 => 28
4405 11:19:19.518332 Write leveling (Byte 1): 30 => 30
4406 11:19:19.521186 DramcWriteLeveling(PI) end<-----
4407 11:19:19.521694
4408 11:19:19.522125 ==
4409 11:19:19.524654 Dram Type= 6, Freq= 0, CH_1, rank 0
4410 11:19:19.527599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4411 11:19:19.528071 ==
4412 11:19:19.531421 [Gating] SW mode calibration
4413 11:19:19.538022 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4414 11:19:19.544449 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4415 11:19:19.547925 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4416 11:19:19.550869 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4417 11:19:19.557990 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4418 11:19:19.561058 0 9 12 | B1->B0 | 3030 3030 | 1 1 | (1 1) (1 1)
4419 11:19:19.564051 0 9 16 | B1->B0 | 2929 2626 | 0 0 | (0 0) (0 0)
4420 11:19:19.570808 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4421 11:19:19.573863 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4422 11:19:19.577279 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4423 11:19:19.584034 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4424 11:19:19.587250 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4425 11:19:19.590762 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4426 11:19:19.597292 0 10 12 | B1->B0 | 2f2f 3030 | 1 0 | (1 1) (0 0)
4427 11:19:19.600109 0 10 16 | B1->B0 | 4040 3a3a | 1 1 | (0 0) (0 0)
4428 11:19:19.603760 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 11:19:19.610364 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4430 11:19:19.613292 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4431 11:19:19.616872 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4432 11:19:19.623649 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4433 11:19:19.626790 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4434 11:19:19.630217 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4435 11:19:19.636770 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 11:19:19.640178 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 11:19:19.642913 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 11:19:19.649986 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 11:19:19.653275 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 11:19:19.656183 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 11:19:19.662692 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 11:19:19.666251 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 11:19:19.669785 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 11:19:19.676129 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4445 11:19:19.679122 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4446 11:19:19.682591 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4447 11:19:19.689181 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4448 11:19:19.692445 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4449 11:19:19.695505 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4450 11:19:19.702386 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
4451 11:19:19.705947 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4452 11:19:19.708932 Total UI for P1: 0, mck2ui 16
4453 11:19:19.712578 best dqsien dly found for B0: ( 0, 13, 14)
4454 11:19:19.715670 Total UI for P1: 0, mck2ui 16
4455 11:19:19.718927 best dqsien dly found for B1: ( 0, 13, 12)
4456 11:19:19.721976 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4457 11:19:19.725951 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4458 11:19:19.726492
4459 11:19:19.728596 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4460 11:19:19.732257 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4461 11:19:19.735371 [Gating] SW calibration Done
4462 11:19:19.735800 ==
4463 11:19:19.738880 Dram Type= 6, Freq= 0, CH_1, rank 0
4464 11:19:19.745361 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4465 11:19:19.745837 ==
4466 11:19:19.746207 RX Vref Scan: 0
4467 11:19:19.746552
4468 11:19:19.748783 RX Vref 0 -> 0, step: 1
4469 11:19:19.749254
4470 11:19:19.751996 RX Delay -230 -> 252, step: 16
4471 11:19:19.754858 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4472 11:19:19.758289 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4473 11:19:19.761828 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4474 11:19:19.768038 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4475 11:19:19.771694 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4476 11:19:19.775151 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4477 11:19:19.778221 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4478 11:19:19.784721 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4479 11:19:19.788146 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4480 11:19:19.791401 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4481 11:19:19.794880 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4482 11:19:19.801467 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4483 11:19:19.804481 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4484 11:19:19.808032 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4485 11:19:19.811205 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4486 11:19:19.817696 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4487 11:19:19.818123 ==
4488 11:19:19.821324 Dram Type= 6, Freq= 0, CH_1, rank 0
4489 11:19:19.824436 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4490 11:19:19.824859 ==
4491 11:19:19.825194 DQS Delay:
4492 11:19:19.827959 DQS0 = 0, DQS1 = 0
4493 11:19:19.828434 DQM Delay:
4494 11:19:19.830745 DQM0 = 39, DQM1 = 28
4495 11:19:19.831246 DQ Delay:
4496 11:19:19.834384 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4497 11:19:19.837559 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4498 11:19:19.841238 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4499 11:19:19.844354 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4500 11:19:19.844782
4501 11:19:19.845117
4502 11:19:19.845429 ==
4503 11:19:19.847305 Dram Type= 6, Freq= 0, CH_1, rank 0
4504 11:19:19.850935 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4505 11:19:19.851369 ==
4506 11:19:19.854198
4507 11:19:19.854623
4508 11:19:19.855002 TX Vref Scan disable
4509 11:19:19.857326 == TX Byte 0 ==
4510 11:19:19.860662 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4511 11:19:19.864169 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4512 11:19:19.866875 == TX Byte 1 ==
4513 11:19:19.870387 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4514 11:19:19.873687 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4515 11:19:19.877289 ==
4516 11:19:19.880325 Dram Type= 6, Freq= 0, CH_1, rank 0
4517 11:19:19.883910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4518 11:19:19.884343 ==
4519 11:19:19.884685
4520 11:19:19.885000
4521 11:19:19.886564 TX Vref Scan disable
4522 11:19:19.890177 == TX Byte 0 ==
4523 11:19:19.893127 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4524 11:19:19.896718 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4525 11:19:19.899610 == TX Byte 1 ==
4526 11:19:19.902772 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4527 11:19:19.906394 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4528 11:19:19.906477
4529 11:19:19.906541 [DATLAT]
4530 11:19:19.909779 Freq=600, CH1 RK0
4531 11:19:19.909863
4532 11:19:19.913149 DATLAT Default: 0x9
4533 11:19:19.913232 0, 0xFFFF, sum = 0
4534 11:19:19.915932 1, 0xFFFF, sum = 0
4535 11:19:19.916035 2, 0xFFFF, sum = 0
4536 11:19:19.919144 3, 0xFFFF, sum = 0
4537 11:19:19.919229 4, 0xFFFF, sum = 0
4538 11:19:19.922670 5, 0xFFFF, sum = 0
4539 11:19:19.922755 6, 0xFFFF, sum = 0
4540 11:19:19.925524 7, 0xFFFF, sum = 0
4541 11:19:19.925608 8, 0x0, sum = 1
4542 11:19:19.929275 9, 0x0, sum = 2
4543 11:19:19.929360 10, 0x0, sum = 3
4544 11:19:19.932494 11, 0x0, sum = 4
4545 11:19:19.932579 best_step = 9
4546 11:19:19.932646
4547 11:19:19.932745 ==
4548 11:19:19.935583 Dram Type= 6, Freq= 0, CH_1, rank 0
4549 11:19:19.939025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4550 11:19:19.939109 ==
4551 11:19:19.942182 RX Vref Scan: 1
4552 11:19:19.942265
4553 11:19:19.945332 RX Vref 0 -> 0, step: 1
4554 11:19:19.945427
4555 11:19:19.945492 RX Delay -195 -> 252, step: 8
4556 11:19:19.948963
4557 11:19:19.949050 Set Vref, RX VrefLevel [Byte0]: 57
4558 11:19:19.952208 [Byte1]: 49
4559 11:19:19.956910
4560 11:19:19.956992 Final RX Vref Byte 0 = 57 to rank0
4561 11:19:19.960462 Final RX Vref Byte 1 = 49 to rank0
4562 11:19:19.963502 Final RX Vref Byte 0 = 57 to rank1
4563 11:19:19.966762 Final RX Vref Byte 1 = 49 to rank1==
4564 11:19:19.970280 Dram Type= 6, Freq= 0, CH_1, rank 0
4565 11:19:19.977006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4566 11:19:19.977112 ==
4567 11:19:19.977179 DQS Delay:
4568 11:19:19.980179 DQS0 = 0, DQS1 = 0
4569 11:19:19.980264 DQM Delay:
4570 11:19:19.980326 DQM0 = 39, DQM1 = 29
4571 11:19:19.983158 DQ Delay:
4572 11:19:19.987098 DQ0 =44, DQ1 =36, DQ2 =28, DQ3 =36
4573 11:19:19.989660 DQ4 =36, DQ5 =52, DQ6 =48, DQ7 =36
4574 11:19:19.993105 DQ8 =12, DQ9 =20, DQ10 =28, DQ11 =24
4575 11:19:19.996811 DQ12 =40, DQ13 =36, DQ14 =36, DQ15 =36
4576 11:19:19.996893
4577 11:19:19.996988
4578 11:19:20.002837 [DQSOSCAuto] RK0, (LSB)MR18= 0x2330, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 403 ps
4579 11:19:20.006514 CH1 RK0: MR19=808, MR18=2330
4580 11:19:20.012786 CH1_RK0: MR19=0x808, MR18=0x2330, DQSOSC=400, MR23=63, INC=163, DEC=109
4581 11:19:20.012870
4582 11:19:20.016513 ----->DramcWriteLeveling(PI) begin...
4583 11:19:20.016596 ==
4584 11:19:20.019911 Dram Type= 6, Freq= 0, CH_1, rank 1
4585 11:19:20.022767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4586 11:19:20.022888 ==
4587 11:19:20.026218 Write leveling (Byte 0): 28 => 28
4588 11:19:20.029585 Write leveling (Byte 1): 31 => 31
4589 11:19:20.032715 DramcWriteLeveling(PI) end<-----
4590 11:19:20.032804
4591 11:19:20.032873 ==
4592 11:19:20.035853 Dram Type= 6, Freq= 0, CH_1, rank 1
4593 11:19:20.039601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4594 11:19:20.042508 ==
4595 11:19:20.042583 [Gating] SW mode calibration
4596 11:19:20.052849 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4597 11:19:20.055854 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4598 11:19:20.058819 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4599 11:19:20.065862 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4600 11:19:20.068787 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4601 11:19:20.072110 0 9 12 | B1->B0 | 3131 3030 | 1 0 | (1 1) (1 1)
4602 11:19:20.078978 0 9 16 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
4603 11:19:20.082385 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4604 11:19:20.085255 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4605 11:19:20.092253 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4606 11:19:20.095306 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4607 11:19:20.098561 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4608 11:19:20.105221 0 10 8 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
4609 11:19:20.108932 0 10 12 | B1->B0 | 3131 4444 | 0 0 | (0 0) (0 0)
4610 11:19:20.111601 0 10 16 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
4611 11:19:20.118221 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4612 11:19:20.121868 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4613 11:19:20.124973 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4614 11:19:20.131695 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4615 11:19:20.134822 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4616 11:19:20.138167 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4617 11:19:20.144986 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4618 11:19:20.148129 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 11:19:20.151474 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 11:19:20.158211 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 11:19:20.161244 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 11:19:20.164356 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 11:19:20.171368 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 11:19:20.174470 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 11:19:20.180758 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 11:19:20.184116 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 11:19:20.187718 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4628 11:19:20.194145 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4629 11:19:20.197775 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4630 11:19:20.200822 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4631 11:19:20.204487 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4632 11:19:20.211185 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4633 11:19:20.214209 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4634 11:19:20.217548 Total UI for P1: 0, mck2ui 16
4635 11:19:20.220875 best dqsien dly found for B0: ( 0, 13, 10)
4636 11:19:20.223849 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4637 11:19:20.227576 Total UI for P1: 0, mck2ui 16
4638 11:19:20.230647 best dqsien dly found for B1: ( 0, 13, 12)
4639 11:19:20.237137 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4640 11:19:20.240463 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4641 11:19:20.240942
4642 11:19:20.244055 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4643 11:19:20.247418 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4644 11:19:20.250112 [Gating] SW calibration Done
4645 11:19:20.250589 ==
4646 11:19:20.253730 Dram Type= 6, Freq= 0, CH_1, rank 1
4647 11:19:20.256869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4648 11:19:20.257574 ==
4649 11:19:20.260235 RX Vref Scan: 0
4650 11:19:20.260732
4651 11:19:20.261145 RX Vref 0 -> 0, step: 1
4652 11:19:20.261557
4653 11:19:20.263312 RX Delay -230 -> 252, step: 16
4654 11:19:20.270103 iDelay=218, Bit 0, Center 41 (-134 ~ 217) 352
4655 11:19:20.273431 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4656 11:19:20.276548 iDelay=218, Bit 2, Center 17 (-150 ~ 185) 336
4657 11:19:20.279757 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4658 11:19:20.283293 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4659 11:19:20.289578 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4660 11:19:20.292988 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4661 11:19:20.296376 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4662 11:19:20.300048 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4663 11:19:20.306801 iDelay=218, Bit 9, Center 25 (-150 ~ 201) 352
4664 11:19:20.309587 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4665 11:19:20.313166 iDelay=218, Bit 11, Center 25 (-150 ~ 201) 352
4666 11:19:20.316336 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4667 11:19:20.322778 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4668 11:19:20.325952 iDelay=218, Bit 14, Center 33 (-134 ~ 201) 336
4669 11:19:20.329306 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4670 11:19:20.329825 ==
4671 11:19:20.332969 Dram Type= 6, Freq= 0, CH_1, rank 1
4672 11:19:20.335936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4673 11:19:20.338959 ==
4674 11:19:20.339451 DQS Delay:
4675 11:19:20.339903 DQS0 = 0, DQS1 = 0
4676 11:19:20.342570 DQM Delay:
4677 11:19:20.343216 DQM0 = 36, DQM1 = 29
4678 11:19:20.345736 DQ Delay:
4679 11:19:20.349341 DQ0 =41, DQ1 =33, DQ2 =17, DQ3 =33
4680 11:19:20.349910 DQ4 =33, DQ5 =49, DQ6 =49, DQ7 =33
4681 11:19:20.352803 DQ8 =17, DQ9 =25, DQ10 =33, DQ11 =25
4682 11:19:20.358796 DQ12 =33, DQ13 =33, DQ14 =33, DQ15 =33
4683 11:19:20.359280
4684 11:19:20.359624
4685 11:19:20.359974 ==
4686 11:19:20.361944 Dram Type= 6, Freq= 0, CH_1, rank 1
4687 11:19:20.365527 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4688 11:19:20.366072 ==
4689 11:19:20.366442
4690 11:19:20.366940
4691 11:19:20.368701 TX Vref Scan disable
4692 11:19:20.369136 == TX Byte 0 ==
4693 11:19:20.375177 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4694 11:19:20.378885 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4695 11:19:20.379411 == TX Byte 1 ==
4696 11:19:20.385123 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4697 11:19:20.388814 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4698 11:19:20.389412 ==
4699 11:19:20.391844 Dram Type= 6, Freq= 0, CH_1, rank 1
4700 11:19:20.395334 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4701 11:19:20.395769 ==
4702 11:19:20.398186
4703 11:19:20.398641
4704 11:19:20.399094 TX Vref Scan disable
4705 11:19:20.401817 == TX Byte 0 ==
4706 11:19:20.405205 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4707 11:19:20.411960 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4708 11:19:20.412394 == TX Byte 1 ==
4709 11:19:20.415502 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4710 11:19:20.422058 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4711 11:19:20.422142
4712 11:19:20.422241 [DATLAT]
4713 11:19:20.422301 Freq=600, CH1 RK1
4714 11:19:20.422360
4715 11:19:20.425483 DATLAT Default: 0x9
4716 11:19:20.425566 0, 0xFFFF, sum = 0
4717 11:19:20.427993 1, 0xFFFF, sum = 0
4718 11:19:20.431380 2, 0xFFFF, sum = 0
4719 11:19:20.431491 3, 0xFFFF, sum = 0
4720 11:19:20.434674 4, 0xFFFF, sum = 0
4721 11:19:20.434785 5, 0xFFFF, sum = 0
4722 11:19:20.438136 6, 0xFFFF, sum = 0
4723 11:19:20.438221 7, 0xFFFF, sum = 0
4724 11:19:20.441621 8, 0x0, sum = 1
4725 11:19:20.441713 9, 0x0, sum = 2
4726 11:19:20.441785 10, 0x0, sum = 3
4727 11:19:20.444811 11, 0x0, sum = 4
4728 11:19:20.444910 best_step = 9
4729 11:19:20.444986
4730 11:19:20.447902 ==
4731 11:19:20.447999 Dram Type= 6, Freq= 0, CH_1, rank 1
4732 11:19:20.454425 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4733 11:19:20.454541 ==
4734 11:19:20.454631 RX Vref Scan: 0
4735 11:19:20.454763
4736 11:19:20.457672 RX Vref 0 -> 0, step: 1
4737 11:19:20.457785
4738 11:19:20.461145 RX Delay -195 -> 252, step: 8
4739 11:19:20.467814 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4740 11:19:20.471213 iDelay=205, Bit 1, Center 32 (-123 ~ 188) 312
4741 11:19:20.474671 iDelay=205, Bit 2, Center 24 (-131 ~ 180) 312
4742 11:19:20.477508 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4743 11:19:20.484263 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4744 11:19:20.487337 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4745 11:19:20.491057 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4746 11:19:20.494525 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4747 11:19:20.500570 iDelay=205, Bit 8, Center 16 (-147 ~ 180) 328
4748 11:19:20.504304 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4749 11:19:20.507372 iDelay=205, Bit 10, Center 32 (-131 ~ 196) 328
4750 11:19:20.510801 iDelay=205, Bit 11, Center 24 (-131 ~ 180) 312
4751 11:19:20.517257 iDelay=205, Bit 12, Center 36 (-123 ~ 196) 320
4752 11:19:20.520219 iDelay=205, Bit 13, Center 36 (-123 ~ 196) 320
4753 11:19:20.523824 iDelay=205, Bit 14, Center 36 (-123 ~ 196) 320
4754 11:19:20.526809 iDelay=205, Bit 15, Center 36 (-123 ~ 196) 320
4755 11:19:20.527369 ==
4756 11:19:20.530147 Dram Type= 6, Freq= 0, CH_1, rank 1
4757 11:19:20.536649 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4758 11:19:20.537129 ==
4759 11:19:20.537507 DQS Delay:
4760 11:19:20.540126 DQS0 = 0, DQS1 = 0
4761 11:19:20.540604 DQM Delay:
4762 11:19:20.540980 DQM0 = 36, DQM1 = 29
4763 11:19:20.543624 DQ Delay:
4764 11:19:20.546873 DQ0 =40, DQ1 =32, DQ2 =24, DQ3 =32
4765 11:19:20.550373 DQ4 =36, DQ5 =48, DQ6 =48, DQ7 =32
4766 11:19:20.553250 DQ8 =16, DQ9 =20, DQ10 =32, DQ11 =24
4767 11:19:20.556814 DQ12 =36, DQ13 =36, DQ14 =36, DQ15 =36
4768 11:19:20.557289
4769 11:19:20.557664
4770 11:19:20.563347 [DQSOSCAuto] RK1, (LSB)MR18= 0x3353, (MSB)MR19= 0x808, tDQSOscB0 = 394 ps tDQSOscB1 = 400 ps
4771 11:19:20.566414 CH1 RK1: MR19=808, MR18=3353
4772 11:19:20.573568 CH1_RK1: MR19=0x808, MR18=0x3353, DQSOSC=394, MR23=63, INC=168, DEC=112
4773 11:19:20.576311 [RxdqsGatingPostProcess] freq 600
4774 11:19:20.579961 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4775 11:19:20.583188 Pre-setting of DQS Precalculation
4776 11:19:20.589748 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4777 11:19:20.596133 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4778 11:19:20.602974 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4779 11:19:20.603541
4780 11:19:20.603911
4781 11:19:20.606211 [Calibration Summary] 1200 Mbps
4782 11:19:20.609780 CH 0, Rank 0
4783 11:19:20.610388 SW Impedance : PASS
4784 11:19:20.612958 DUTY Scan : NO K
4785 11:19:20.613427 ZQ Calibration : PASS
4786 11:19:20.616165 Jitter Meter : NO K
4787 11:19:20.619827 CBT Training : PASS
4788 11:19:20.620449 Write leveling : PASS
4789 11:19:20.622585 RX DQS gating : PASS
4790 11:19:20.626647 RX DQ/DQS(RDDQC) : PASS
4791 11:19:20.627317 TX DQ/DQS : PASS
4792 11:19:20.629242 RX DATLAT : PASS
4793 11:19:20.632762 RX DQ/DQS(Engine): PASS
4794 11:19:20.633275 TX OE : NO K
4795 11:19:20.636032 All Pass.
4796 11:19:20.636736
4797 11:19:20.637137 CH 0, Rank 1
4798 11:19:20.639032 SW Impedance : PASS
4799 11:19:20.639504 DUTY Scan : NO K
4800 11:19:20.642684 ZQ Calibration : PASS
4801 11:19:20.645609 Jitter Meter : NO K
4802 11:19:20.646075 CBT Training : PASS
4803 11:19:20.649287 Write leveling : PASS
4804 11:19:20.652524 RX DQS gating : PASS
4805 11:19:20.653045 RX DQ/DQS(RDDQC) : PASS
4806 11:19:20.655645 TX DQ/DQS : PASS
4807 11:19:20.658952 RX DATLAT : PASS
4808 11:19:20.659618 RX DQ/DQS(Engine): PASS
4809 11:19:20.662745 TX OE : NO K
4810 11:19:20.663364 All Pass.
4811 11:19:20.663787
4812 11:19:20.665520 CH 1, Rank 0
4813 11:19:20.666008 SW Impedance : PASS
4814 11:19:20.669005 DUTY Scan : NO K
4815 11:19:20.671951 ZQ Calibration : PASS
4816 11:19:20.672416 Jitter Meter : NO K
4817 11:19:20.675787 CBT Training : PASS
4818 11:19:20.678717 Write leveling : PASS
4819 11:19:20.679271 RX DQS gating : PASS
4820 11:19:20.681715 RX DQ/DQS(RDDQC) : PASS
4821 11:19:20.682181 TX DQ/DQS : PASS
4822 11:19:20.685372 RX DATLAT : PASS
4823 11:19:20.688389 RX DQ/DQS(Engine): PASS
4824 11:19:20.688835 TX OE : NO K
4825 11:19:20.691933 All Pass.
4826 11:19:20.692351
4827 11:19:20.692682 CH 1, Rank 1
4828 11:19:20.694981 SW Impedance : PASS
4829 11:19:20.695401 DUTY Scan : NO K
4830 11:19:20.698506 ZQ Calibration : PASS
4831 11:19:20.702610 Jitter Meter : NO K
4832 11:19:20.703109 CBT Training : PASS
4833 11:19:20.705230 Write leveling : PASS
4834 11:19:20.708566 RX DQS gating : PASS
4835 11:19:20.708994 RX DQ/DQS(RDDQC) : PASS
4836 11:19:20.711989 TX DQ/DQS : PASS
4837 11:19:20.714631 RX DATLAT : PASS
4838 11:19:20.715117 RX DQ/DQS(Engine): PASS
4839 11:19:20.718082 TX OE : NO K
4840 11:19:20.718503 All Pass.
4841 11:19:20.718872
4842 11:19:20.721250 DramC Write-DBI off
4843 11:19:20.724664 PER_BANK_REFRESH: Hybrid Mode
4844 11:19:20.725085 TX_TRACKING: ON
4845 11:19:20.734552 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4846 11:19:20.738144 [FAST_K] Save calibration result to emmc
4847 11:19:20.740942 dramc_set_vcore_voltage set vcore to 662500
4848 11:19:20.744597 Read voltage for 933, 3
4849 11:19:20.745020 Vio18 = 0
4850 11:19:20.745355 Vcore = 662500
4851 11:19:20.747765 Vdram = 0
4852 11:19:20.748203 Vddq = 0
4853 11:19:20.748537 Vmddr = 0
4854 11:19:20.754223 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4855 11:19:20.757686 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4856 11:19:20.761219 MEM_TYPE=3, freq_sel=17
4857 11:19:20.764377 sv_algorithm_assistance_LP4_1600
4858 11:19:20.767538 ============ PULL DRAM RESETB DOWN ============
4859 11:19:20.773860 ========== PULL DRAM RESETB DOWN end =========
4860 11:19:20.777290 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4861 11:19:20.780799 ===================================
4862 11:19:20.783791 LPDDR4 DRAM CONFIGURATION
4863 11:19:20.787058 ===================================
4864 11:19:20.787657 EX_ROW_EN[0] = 0x0
4865 11:19:20.790779 EX_ROW_EN[1] = 0x0
4866 11:19:20.791377 LP4Y_EN = 0x0
4867 11:19:20.793643 WORK_FSP = 0x0
4868 11:19:20.794248 WL = 0x3
4869 11:19:20.797513 RL = 0x3
4870 11:19:20.798128 BL = 0x2
4871 11:19:20.800498 RPST = 0x0
4872 11:19:20.804188 RD_PRE = 0x0
4873 11:19:20.804732 WR_PRE = 0x1
4874 11:19:20.806879 WR_PST = 0x0
4875 11:19:20.807302 DBI_WR = 0x0
4876 11:19:20.810291 DBI_RD = 0x0
4877 11:19:20.810987 OTF = 0x1
4878 11:19:20.813613 ===================================
4879 11:19:20.816975 ===================================
4880 11:19:20.820349 ANA top config
4881 11:19:20.823142 ===================================
4882 11:19:20.823664 DLL_ASYNC_EN = 0
4883 11:19:20.826488 ALL_SLAVE_EN = 1
4884 11:19:20.830127 NEW_RANK_MODE = 1
4885 11:19:20.833460 DLL_IDLE_MODE = 1
4886 11:19:20.833893 LP45_APHY_COMB_EN = 1
4887 11:19:20.836760 TX_ODT_DIS = 1
4888 11:19:20.840261 NEW_8X_MODE = 1
4889 11:19:20.843230 ===================================
4890 11:19:20.846775 ===================================
4891 11:19:20.849748 data_rate = 1866
4892 11:19:20.853327 CKR = 1
4893 11:19:20.856178 DQ_P2S_RATIO = 8
4894 11:19:20.859756 ===================================
4895 11:19:20.860191 CA_P2S_RATIO = 8
4896 11:19:20.863241 DQ_CA_OPEN = 0
4897 11:19:20.866655 DQ_SEMI_OPEN = 0
4898 11:19:20.869478 CA_SEMI_OPEN = 0
4899 11:19:20.872926 CA_FULL_RATE = 0
4900 11:19:20.876083 DQ_CKDIV4_EN = 1
4901 11:19:20.876684 CA_CKDIV4_EN = 1
4902 11:19:20.879516 CA_PREDIV_EN = 0
4903 11:19:20.882959 PH8_DLY = 0
4904 11:19:20.885952 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4905 11:19:20.889773 DQ_AAMCK_DIV = 4
4906 11:19:20.892484 CA_AAMCK_DIV = 4
4907 11:19:20.896049 CA_ADMCK_DIV = 4
4908 11:19:20.896511 DQ_TRACK_CA_EN = 0
4909 11:19:20.898818 CA_PICK = 933
4910 11:19:20.902440 CA_MCKIO = 933
4911 11:19:20.905461 MCKIO_SEMI = 0
4912 11:19:20.908578 PLL_FREQ = 3732
4913 11:19:20.912311 DQ_UI_PI_RATIO = 32
4914 11:19:20.915251 CA_UI_PI_RATIO = 0
4915 11:19:20.918887 ===================================
4916 11:19:20.922235 ===================================
4917 11:19:20.922893 memory_type:LPDDR4
4918 11:19:20.925356 GP_NUM : 10
4919 11:19:20.928697 SRAM_EN : 1
4920 11:19:20.929334 MD32_EN : 0
4921 11:19:20.932124 ===================================
4922 11:19:20.935593 [ANA_INIT] >>>>>>>>>>>>>>
4923 11:19:20.939099 <<<<<< [CONFIGURE PHASE]: ANA_TX
4924 11:19:20.941929 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4925 11:19:20.945123 ===================================
4926 11:19:20.948665 data_rate = 1866,PCW = 0X8f00
4927 11:19:20.952180 ===================================
4928 11:19:20.955199 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4929 11:19:20.958765 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4930 11:19:20.965246 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4931 11:19:20.968113 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4932 11:19:20.971741 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4933 11:19:20.974891 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4934 11:19:20.978410 [ANA_INIT] flow start
4935 11:19:20.981840 [ANA_INIT] PLL >>>>>>>>
4936 11:19:20.982272 [ANA_INIT] PLL <<<<<<<<
4937 11:19:20.984972 [ANA_INIT] MIDPI >>>>>>>>
4938 11:19:20.988268 [ANA_INIT] MIDPI <<<<<<<<
4939 11:19:20.991507 [ANA_INIT] DLL >>>>>>>>
4940 11:19:20.991932 [ANA_INIT] flow end
4941 11:19:20.995260 ============ LP4 DIFF to SE enter ============
4942 11:19:21.001617 ============ LP4 DIFF to SE exit ============
4943 11:19:21.002052 [ANA_INIT] <<<<<<<<<<<<<
4944 11:19:21.004824 [Flow] Enable top DCM control >>>>>
4945 11:19:21.008301 [Flow] Enable top DCM control <<<<<
4946 11:19:21.011294 Enable DLL master slave shuffle
4947 11:19:21.018007 ==============================================================
4948 11:19:21.020983 Gating Mode config
4949 11:19:21.024478 ==============================================================
4950 11:19:21.027943 Config description:
4951 11:19:21.037571 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4952 11:19:21.044658 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4953 11:19:21.047541 SELPH_MODE 0: By rank 1: By Phase
4954 11:19:21.054478 ==============================================================
4955 11:19:21.057548 GAT_TRACK_EN = 1
4956 11:19:21.060504 RX_GATING_MODE = 2
4957 11:19:21.064068 RX_GATING_TRACK_MODE = 2
4958 11:19:21.064639 SELPH_MODE = 1
4959 11:19:21.067026 PICG_EARLY_EN = 1
4960 11:19:21.070421 VALID_LAT_VALUE = 1
4961 11:19:21.076866 ==============================================================
4962 11:19:21.080487 Enter into Gating configuration >>>>
4963 11:19:21.083327 Exit from Gating configuration <<<<
4964 11:19:21.086986 Enter into DVFS_PRE_config >>>>>
4965 11:19:21.096538 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4966 11:19:21.100445 Exit from DVFS_PRE_config <<<<<
4967 11:19:21.103387 Enter into PICG configuration >>>>
4968 11:19:21.106336 Exit from PICG configuration <<<<
4969 11:19:21.109986 [RX_INPUT] configuration >>>>>
4970 11:19:21.112976 [RX_INPUT] configuration <<<<<
4971 11:19:21.116838 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4972 11:19:21.122914 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4973 11:19:21.129319 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4974 11:19:21.136303 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4975 11:19:21.142983 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4976 11:19:21.149173 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4977 11:19:21.152718 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4978 11:19:21.156228 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4979 11:19:21.159040 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4980 11:19:21.165894 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4981 11:19:21.169244 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4982 11:19:21.172888 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4983 11:19:21.175970 ===================================
4984 11:19:21.179213 LPDDR4 DRAM CONFIGURATION
4985 11:19:21.182689 ===================================
4986 11:19:21.182792 EX_ROW_EN[0] = 0x0
4987 11:19:21.185866 EX_ROW_EN[1] = 0x0
4988 11:19:21.188896 LP4Y_EN = 0x0
4989 11:19:21.189027 WORK_FSP = 0x0
4990 11:19:21.192476 WL = 0x3
4991 11:19:21.192599 RL = 0x3
4992 11:19:21.195426 BL = 0x2
4993 11:19:21.195562 RPST = 0x0
4994 11:19:21.198801 RD_PRE = 0x0
4995 11:19:21.198966 WR_PRE = 0x1
4996 11:19:21.201963 WR_PST = 0x0
4997 11:19:21.202114 DBI_WR = 0x0
4998 11:19:21.206046 DBI_RD = 0x0
4999 11:19:21.206470 OTF = 0x1
5000 11:19:21.208978 ===================================
5001 11:19:21.212324 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5002 11:19:21.219135 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5003 11:19:21.222042 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5004 11:19:21.225766 ===================================
5005 11:19:21.228706 LPDDR4 DRAM CONFIGURATION
5006 11:19:21.232402 ===================================
5007 11:19:21.232824 EX_ROW_EN[0] = 0x10
5008 11:19:21.235765 EX_ROW_EN[1] = 0x0
5009 11:19:21.238776 LP4Y_EN = 0x0
5010 11:19:21.239467 WORK_FSP = 0x0
5011 11:19:21.242417 WL = 0x3
5012 11:19:21.242878 RL = 0x3
5013 11:19:21.245245 BL = 0x2
5014 11:19:21.245667 RPST = 0x0
5015 11:19:21.249093 RD_PRE = 0x0
5016 11:19:21.249513 WR_PRE = 0x1
5017 11:19:21.251882 WR_PST = 0x0
5018 11:19:21.252305 DBI_WR = 0x0
5019 11:19:21.255660 DBI_RD = 0x0
5020 11:19:21.256082 OTF = 0x1
5021 11:19:21.259139 ===================================
5022 11:19:21.265217 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5023 11:19:21.269773 nWR fixed to 30
5024 11:19:21.272925 [ModeRegInit_LP4] CH0 RK0
5025 11:19:21.273366 [ModeRegInit_LP4] CH0 RK1
5026 11:19:21.276312 [ModeRegInit_LP4] CH1 RK0
5027 11:19:21.279677 [ModeRegInit_LP4] CH1 RK1
5028 11:19:21.280112 match AC timing 9
5029 11:19:21.286159 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5030 11:19:21.289289 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5031 11:19:21.292519 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5032 11:19:21.299114 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5033 11:19:21.302809 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5034 11:19:21.303278 ==
5035 11:19:21.306158 Dram Type= 6, Freq= 0, CH_0, rank 0
5036 11:19:21.309199 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5037 11:19:21.309671 ==
5038 11:19:21.316135 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5039 11:19:21.322224 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5040 11:19:21.325677 [CA 0] Center 38 (8~69) winsize 62
5041 11:19:21.328680 [CA 1] Center 38 (8~69) winsize 62
5042 11:19:21.332508 [CA 2] Center 35 (5~65) winsize 61
5043 11:19:21.335688 [CA 3] Center 35 (5~65) winsize 61
5044 11:19:21.338616 [CA 4] Center 34 (4~65) winsize 62
5045 11:19:21.342112 [CA 5] Center 33 (3~64) winsize 62
5046 11:19:21.342534
5047 11:19:21.345388 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5048 11:19:21.345808
5049 11:19:21.348604 [CATrainingPosCal] consider 1 rank data
5050 11:19:21.351699 u2DelayCellTimex100 = 270/100 ps
5051 11:19:21.355473 CA0 delay=38 (8~69),Diff = 5 PI (31 cell)
5052 11:19:21.358535 CA1 delay=38 (8~69),Diff = 5 PI (31 cell)
5053 11:19:21.361445 CA2 delay=35 (5~65),Diff = 2 PI (12 cell)
5054 11:19:21.368240 CA3 delay=35 (5~65),Diff = 2 PI (12 cell)
5055 11:19:21.371644 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5056 11:19:21.374577 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5057 11:19:21.374787
5058 11:19:21.378148 CA PerBit enable=1, Macro0, CA PI delay=33
5059 11:19:21.378299
5060 11:19:21.381895 [CBTSetCACLKResult] CA Dly = 33
5061 11:19:21.382075 CS Dly: 6 (0~37)
5062 11:19:21.382226 ==
5063 11:19:21.384400 Dram Type= 6, Freq= 0, CH_0, rank 1
5064 11:19:21.391405 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5065 11:19:21.391492 ==
5066 11:19:21.394373 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5067 11:19:21.400959 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5068 11:19:21.404477 [CA 0] Center 38 (8~69) winsize 62
5069 11:19:21.407986 [CA 1] Center 38 (8~69) winsize 62
5070 11:19:21.410749 [CA 2] Center 35 (5~65) winsize 61
5071 11:19:21.414115 [CA 3] Center 35 (5~66) winsize 62
5072 11:19:21.417528 [CA 4] Center 34 (4~65) winsize 62
5073 11:19:21.421528 [CA 5] Center 34 (4~64) winsize 61
5074 11:19:21.421614
5075 11:19:21.424310 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5076 11:19:21.424387
5077 11:19:21.427790 [CATrainingPosCal] consider 2 rank data
5078 11:19:21.430813 u2DelayCellTimex100 = 270/100 ps
5079 11:19:21.433907 CA0 delay=38 (8~69),Diff = 4 PI (24 cell)
5080 11:19:21.440455 CA1 delay=38 (8~69),Diff = 4 PI (24 cell)
5081 11:19:21.443995 CA2 delay=35 (5~65),Diff = 1 PI (6 cell)
5082 11:19:21.447164 CA3 delay=35 (5~65),Diff = 1 PI (6 cell)
5083 11:19:21.450535 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
5084 11:19:21.453813 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
5085 11:19:21.453918
5086 11:19:21.457158 CA PerBit enable=1, Macro0, CA PI delay=34
5087 11:19:21.457247
5088 11:19:21.460387 [CBTSetCACLKResult] CA Dly = 34
5089 11:19:21.464104 CS Dly: 7 (0~39)
5090 11:19:21.464210
5091 11:19:21.467188 ----->DramcWriteLeveling(PI) begin...
5092 11:19:21.467318 ==
5093 11:19:21.470354 Dram Type= 6, Freq= 0, CH_0, rank 0
5094 11:19:21.473715 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5095 11:19:21.473807 ==
5096 11:19:21.477681 Write leveling (Byte 0): 30 => 30
5097 11:19:21.480777 Write leveling (Byte 1): 30 => 30
5098 11:19:21.483806 DramcWriteLeveling(PI) end<-----
5099 11:19:21.483890
5100 11:19:21.483957 ==
5101 11:19:21.487098 Dram Type= 6, Freq= 0, CH_0, rank 0
5102 11:19:21.490416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5103 11:19:21.490521 ==
5104 11:19:21.494167 [Gating] SW mode calibration
5105 11:19:21.500414 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5106 11:19:21.506805 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5107 11:19:21.510325 0 14 0 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
5108 11:19:21.513152 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5109 11:19:21.519971 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5110 11:19:21.523296 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5111 11:19:21.526614 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5112 11:19:21.533556 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5113 11:19:21.536347 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5114 11:19:21.540017 0 14 28 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
5115 11:19:21.546324 0 15 0 | B1->B0 | 3434 2d2d | 1 0 | (1 1) (0 0)
5116 11:19:21.550149 0 15 4 | B1->B0 | 2b2b 2323 | 0 0 | (1 0) (0 0)
5117 11:19:21.552772 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5118 11:19:21.559472 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5119 11:19:21.563077 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5120 11:19:21.566379 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5121 11:19:21.572797 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5122 11:19:21.575935 0 15 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5123 11:19:21.579233 1 0 0 | B1->B0 | 2a2a 3e3e | 1 0 | (0 0) (0 0)
5124 11:19:21.586056 1 0 4 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5125 11:19:21.588999 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5126 11:19:21.592343 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5127 11:19:21.599320 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5128 11:19:21.602199 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5129 11:19:21.605475 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5130 11:19:21.612028 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5131 11:19:21.615524 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5132 11:19:21.618454 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5133 11:19:21.625365 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5134 11:19:21.629128 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 11:19:21.631942 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 11:19:21.638599 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 11:19:21.641529 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 11:19:21.645210 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 11:19:21.651677 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 11:19:21.655340 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5141 11:19:21.658120 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5142 11:19:21.664802 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5143 11:19:21.668615 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5144 11:19:21.671348 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5145 11:19:21.678193 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5146 11:19:21.681398 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5147 11:19:21.684479 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5148 11:19:21.687801 Total UI for P1: 0, mck2ui 16
5149 11:19:21.690768 best dqsien dly found for B0: ( 1, 2, 28)
5150 11:19:21.697921 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5151 11:19:21.701225 Total UI for P1: 0, mck2ui 16
5152 11:19:21.704011 best dqsien dly found for B1: ( 1, 3, 0)
5153 11:19:21.707303 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5154 11:19:21.710730 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5155 11:19:21.710834
5156 11:19:21.714279 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5157 11:19:21.717258 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5158 11:19:21.720730 [Gating] SW calibration Done
5159 11:19:21.720835 ==
5160 11:19:21.724062 Dram Type= 6, Freq= 0, CH_0, rank 0
5161 11:19:21.727524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5162 11:19:21.727618 ==
5163 11:19:21.730618 RX Vref Scan: 0
5164 11:19:21.730705
5165 11:19:21.733958 RX Vref 0 -> 0, step: 1
5166 11:19:21.734050
5167 11:19:21.734116 RX Delay -80 -> 252, step: 8
5168 11:19:21.740543 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5169 11:19:21.743548 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5170 11:19:21.747163 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5171 11:19:21.750349 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5172 11:19:21.753992 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5173 11:19:21.760421 iDelay=208, Bit 5, Center 79 (-16 ~ 175) 192
5174 11:19:21.763318 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5175 11:19:21.766478 iDelay=208, Bit 7, Center 111 (16 ~ 207) 192
5176 11:19:21.770055 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5177 11:19:21.773443 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5178 11:19:21.779938 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5179 11:19:21.782778 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5180 11:19:21.786133 iDelay=208, Bit 12, Center 83 (-16 ~ 183) 200
5181 11:19:21.789497 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5182 11:19:21.796185 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5183 11:19:21.799185 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5184 11:19:21.799302 ==
5185 11:19:21.802448 Dram Type= 6, Freq= 0, CH_0, rank 0
5186 11:19:21.805847 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5187 11:19:21.805964 ==
5188 11:19:21.806065 DQS Delay:
5189 11:19:21.809019 DQS0 = 0, DQS1 = 0
5190 11:19:21.809137 DQM Delay:
5191 11:19:21.812188 DQM0 = 95, DQM1 = 83
5192 11:19:21.812314 DQ Delay:
5193 11:19:21.815876 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =91
5194 11:19:21.819248 DQ4 =99, DQ5 =79, DQ6 =103, DQ7 =111
5195 11:19:21.822260 DQ8 =79, DQ9 =71, DQ10 =83, DQ11 =75
5196 11:19:21.825963 DQ12 =83, DQ13 =91, DQ14 =91, DQ15 =91
5197 11:19:21.826069
5198 11:19:21.826163
5199 11:19:21.826255 ==
5200 11:19:21.829151 Dram Type= 6, Freq= 0, CH_0, rank 0
5201 11:19:21.835691 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5202 11:19:21.835809 ==
5203 11:19:21.835908
5204 11:19:21.836002
5205 11:19:21.836095 TX Vref Scan disable
5206 11:19:21.839163 == TX Byte 0 ==
5207 11:19:21.841973 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5208 11:19:21.848714 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5209 11:19:21.848803 == TX Byte 1 ==
5210 11:19:21.851976 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5211 11:19:21.858538 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5212 11:19:21.858626 ==
5213 11:19:21.862117 Dram Type= 6, Freq= 0, CH_0, rank 0
5214 11:19:21.865047 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5215 11:19:21.865135 ==
5216 11:19:21.865204
5217 11:19:21.865268
5218 11:19:21.868429 TX Vref Scan disable
5219 11:19:21.871820 == TX Byte 0 ==
5220 11:19:21.874694 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5221 11:19:21.878161 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5222 11:19:21.881718 == TX Byte 1 ==
5223 11:19:21.884795 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5224 11:19:21.888191 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5225 11:19:21.888277
5226 11:19:21.888343 [DATLAT]
5227 11:19:21.891882 Freq=933, CH0 RK0
5228 11:19:21.891968
5229 11:19:21.895584 DATLAT Default: 0xd
5230 11:19:21.896011 0, 0xFFFF, sum = 0
5231 11:19:21.898568 1, 0xFFFF, sum = 0
5232 11:19:21.899023 2, 0xFFFF, sum = 0
5233 11:19:21.901724 3, 0xFFFF, sum = 0
5234 11:19:21.902158 4, 0xFFFF, sum = 0
5235 11:19:21.905390 5, 0xFFFF, sum = 0
5236 11:19:21.905825 6, 0xFFFF, sum = 0
5237 11:19:21.908525 7, 0xFFFF, sum = 0
5238 11:19:21.908959 8, 0xFFFF, sum = 0
5239 11:19:21.911457 9, 0xFFFF, sum = 0
5240 11:19:21.911896 10, 0x0, sum = 1
5241 11:19:21.914754 11, 0x0, sum = 2
5242 11:19:21.915227 12, 0x0, sum = 3
5243 11:19:21.918145 13, 0x0, sum = 4
5244 11:19:21.918580 best_step = 11
5245 11:19:21.918961
5246 11:19:21.919285 ==
5247 11:19:21.921601 Dram Type= 6, Freq= 0, CH_0, rank 0
5248 11:19:21.924760 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5249 11:19:21.927803 ==
5250 11:19:21.928230 RX Vref Scan: 1
5251 11:19:21.928574
5252 11:19:21.931305 RX Vref 0 -> 0, step: 1
5253 11:19:21.931738
5254 11:19:21.934675 RX Delay -69 -> 252, step: 4
5255 11:19:21.935149
5256 11:19:21.938146 Set Vref, RX VrefLevel [Byte0]: 61
5257 11:19:21.941181 [Byte1]: 57
5258 11:19:21.941628
5259 11:19:21.944632 Final RX Vref Byte 0 = 61 to rank0
5260 11:19:21.948144 Final RX Vref Byte 1 = 57 to rank0
5261 11:19:21.950997 Final RX Vref Byte 0 = 61 to rank1
5262 11:19:21.954120 Final RX Vref Byte 1 = 57 to rank1==
5263 11:19:21.957540 Dram Type= 6, Freq= 0, CH_0, rank 0
5264 11:19:21.960792 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5265 11:19:21.961260 ==
5266 11:19:21.964566 DQS Delay:
5267 11:19:21.965001 DQS0 = 0, DQS1 = 0
5268 11:19:21.965349 DQM Delay:
5269 11:19:21.967300 DQM0 = 95, DQM1 = 84
5270 11:19:21.967737 DQ Delay:
5271 11:19:21.970613 DQ0 =94, DQ1 =96, DQ2 =92, DQ3 =92
5272 11:19:21.974375 DQ4 =96, DQ5 =84, DQ6 =104, DQ7 =108
5273 11:19:21.977755 DQ8 =78, DQ9 =72, DQ10 =82, DQ11 =80
5274 11:19:21.980604 DQ12 =90, DQ13 =90, DQ14 =96, DQ15 =90
5275 11:19:21.980724
5276 11:19:21.980791
5277 11:19:21.990546 [DQSOSCAuto] RK0, (LSB)MR18= 0x1515, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 415 ps
5278 11:19:21.993409 CH0 RK0: MR19=505, MR18=1515
5279 11:19:22.000322 CH0_RK0: MR19=0x505, MR18=0x1515, DQSOSC=415, MR23=63, INC=62, DEC=41
5280 11:19:22.000409
5281 11:19:22.003296 ----->DramcWriteLeveling(PI) begin...
5282 11:19:22.003382 ==
5283 11:19:22.006558 Dram Type= 6, Freq= 0, CH_0, rank 1
5284 11:19:22.009941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5285 11:19:22.010026 ==
5286 11:19:22.013175 Write leveling (Byte 0): 32 => 32
5287 11:19:22.016730 Write leveling (Byte 1): 31 => 31
5288 11:19:22.020036 DramcWriteLeveling(PI) end<-----
5289 11:19:22.020145
5290 11:19:22.020226 ==
5291 11:19:22.023008 Dram Type= 6, Freq= 0, CH_0, rank 1
5292 11:19:22.026315 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5293 11:19:22.026398 ==
5294 11:19:22.029586 [Gating] SW mode calibration
5295 11:19:22.036624 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5296 11:19:22.042745 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5297 11:19:22.046311 0 14 0 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
5298 11:19:22.049285 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5299 11:19:22.056244 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5300 11:19:22.059604 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5301 11:19:22.062461 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5302 11:19:22.069539 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5303 11:19:22.072595 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (0 0)
5304 11:19:22.076355 0 14 28 | B1->B0 | 3434 2f2f | 0 1 | (0 0) (1 0)
5305 11:19:22.082533 0 15 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
5306 11:19:22.086257 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5307 11:19:22.089172 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5308 11:19:22.096135 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5309 11:19:22.099733 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5310 11:19:22.102145 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5311 11:19:22.109174 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5312 11:19:22.112746 0 15 28 | B1->B0 | 2423 3333 | 1 1 | (0 0) (0 0)
5313 11:19:22.115407 1 0 0 | B1->B0 | 3e3e 4646 | 1 0 | (0 0) (0 0)
5314 11:19:22.122071 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5315 11:19:22.125298 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5316 11:19:22.128689 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5317 11:19:22.135579 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5318 11:19:22.138725 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5319 11:19:22.141894 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5320 11:19:22.148805 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5321 11:19:22.151924 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5322 11:19:22.155211 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 11:19:22.162097 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 11:19:22.165465 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 11:19:22.168795 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 11:19:22.174996 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 11:19:22.178500 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 11:19:22.181517 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 11:19:22.188739 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5330 11:19:22.191613 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5331 11:19:22.195317 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5332 11:19:22.201528 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5333 11:19:22.204841 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5334 11:19:22.207778 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5335 11:19:22.214906 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5336 11:19:22.217695 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5337 11:19:22.220909 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5338 11:19:22.224560 Total UI for P1: 0, mck2ui 16
5339 11:19:22.227884 best dqsien dly found for B0: ( 1, 2, 28)
5340 11:19:22.234270 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5341 11:19:22.237624 Total UI for P1: 0, mck2ui 16
5342 11:19:22.240956 best dqsien dly found for B1: ( 1, 2, 30)
5343 11:19:22.244037 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5344 11:19:22.247703 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5345 11:19:22.248234
5346 11:19:22.250431 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5347 11:19:22.254047 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5348 11:19:22.257118 [Gating] SW calibration Done
5349 11:19:22.257692 ==
5350 11:19:22.260527 Dram Type= 6, Freq= 0, CH_0, rank 1
5351 11:19:22.264132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5352 11:19:22.264726 ==
5353 11:19:22.266791 RX Vref Scan: 0
5354 11:19:22.267398
5355 11:19:22.270275 RX Vref 0 -> 0, step: 1
5356 11:19:22.270805
5357 11:19:22.271337 RX Delay -80 -> 252, step: 8
5358 11:19:22.276921 iDelay=208, Bit 0, Center 91 (-8 ~ 191) 200
5359 11:19:22.280229 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5360 11:19:22.283942 iDelay=208, Bit 2, Center 91 (-8 ~ 191) 200
5361 11:19:22.286742 iDelay=208, Bit 3, Center 87 (-16 ~ 191) 208
5362 11:19:22.290156 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5363 11:19:22.296897 iDelay=208, Bit 5, Center 75 (-24 ~ 175) 200
5364 11:19:22.300050 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5365 11:19:22.303593 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5366 11:19:22.306965 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5367 11:19:22.309986 iDelay=208, Bit 9, Center 67 (-32 ~ 167) 200
5368 11:19:22.317080 iDelay=208, Bit 10, Center 83 (-16 ~ 183) 200
5369 11:19:22.320022 iDelay=208, Bit 11, Center 75 (-24 ~ 175) 200
5370 11:19:22.323514 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5371 11:19:22.326886 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5372 11:19:22.329540 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5373 11:19:22.336091 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5374 11:19:22.336552 ==
5375 11:19:22.339386 Dram Type= 6, Freq= 0, CH_0, rank 1
5376 11:19:22.343149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5377 11:19:22.343609 ==
5378 11:19:22.343956 DQS Delay:
5379 11:19:22.345932 DQS0 = 0, DQS1 = 0
5380 11:19:22.346357 DQM Delay:
5381 11:19:22.349315 DQM0 = 92, DQM1 = 83
5382 11:19:22.349742 DQ Delay:
5383 11:19:22.352466 DQ0 =91, DQ1 =95, DQ2 =91, DQ3 =87
5384 11:19:22.356284 DQ4 =91, DQ5 =75, DQ6 =103, DQ7 =107
5385 11:19:22.359080 DQ8 =75, DQ9 =67, DQ10 =83, DQ11 =75
5386 11:19:22.362898 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5387 11:19:22.363325
5388 11:19:22.363660
5389 11:19:22.363973 ==
5390 11:19:22.365676 Dram Type= 6, Freq= 0, CH_0, rank 1
5391 11:19:22.372502 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5392 11:19:22.372932 ==
5393 11:19:22.373271
5394 11:19:22.373582
5395 11:19:22.373887 TX Vref Scan disable
5396 11:19:22.375809 == TX Byte 0 ==
5397 11:19:22.378808 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5398 11:19:22.385800 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5399 11:19:22.386227 == TX Byte 1 ==
5400 11:19:22.389177 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5401 11:19:22.395388 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5402 11:19:22.395890 ==
5403 11:19:22.398876 Dram Type= 6, Freq= 0, CH_0, rank 1
5404 11:19:22.401889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5405 11:19:22.402319 ==
5406 11:19:22.402655
5407 11:19:22.403013
5408 11:19:22.405488 TX Vref Scan disable
5409 11:19:22.405916 == TX Byte 0 ==
5410 11:19:22.411683 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5411 11:19:22.415021 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5412 11:19:22.418429 == TX Byte 1 ==
5413 11:19:22.422223 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5414 11:19:22.424918 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5415 11:19:22.425347
5416 11:19:22.425684 [DATLAT]
5417 11:19:22.428439 Freq=933, CH0 RK1
5418 11:19:22.428867
5419 11:19:22.431697 DATLAT Default: 0xb
5420 11:19:22.432121 0, 0xFFFF, sum = 0
5421 11:19:22.435137 1, 0xFFFF, sum = 0
5422 11:19:22.435569 2, 0xFFFF, sum = 0
5423 11:19:22.437924 3, 0xFFFF, sum = 0
5424 11:19:22.438355 4, 0xFFFF, sum = 0
5425 11:19:22.441256 5, 0xFFFF, sum = 0
5426 11:19:22.441690 6, 0xFFFF, sum = 0
5427 11:19:22.444477 7, 0xFFFF, sum = 0
5428 11:19:22.444910 8, 0xFFFF, sum = 0
5429 11:19:22.448179 9, 0xFFFF, sum = 0
5430 11:19:22.448608 10, 0x0, sum = 1
5431 11:19:22.451611 11, 0x0, sum = 2
5432 11:19:22.452043 12, 0x0, sum = 3
5433 11:19:22.454888 13, 0x0, sum = 4
5434 11:19:22.455320 best_step = 11
5435 11:19:22.455658
5436 11:19:22.455971 ==
5437 11:19:22.458082 Dram Type= 6, Freq= 0, CH_0, rank 1
5438 11:19:22.461269 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5439 11:19:22.464603 ==
5440 11:19:22.465050 RX Vref Scan: 0
5441 11:19:22.465405
5442 11:19:22.467502 RX Vref 0 -> 0, step: 1
5443 11:19:22.467930
5444 11:19:22.471049 RX Delay -77 -> 252, step: 4
5445 11:19:22.474707 iDelay=199, Bit 0, Center 90 (-5 ~ 186) 192
5446 11:19:22.477375 iDelay=199, Bit 1, Center 94 (3 ~ 186) 184
5447 11:19:22.484202 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
5448 11:19:22.487841 iDelay=199, Bit 3, Center 88 (-9 ~ 186) 196
5449 11:19:22.491015 iDelay=199, Bit 4, Center 92 (-1 ~ 186) 188
5450 11:19:22.493894 iDelay=199, Bit 5, Center 80 (-13 ~ 174) 188
5451 11:19:22.497424 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5452 11:19:22.500879 iDelay=199, Bit 7, Center 102 (11 ~ 194) 184
5453 11:19:22.507210 iDelay=199, Bit 8, Center 78 (-13 ~ 170) 184
5454 11:19:22.510672 iDelay=199, Bit 9, Center 72 (-17 ~ 162) 180
5455 11:19:22.513563 iDelay=199, Bit 10, Center 86 (-5 ~ 178) 184
5456 11:19:22.517034 iDelay=199, Bit 11, Center 78 (-13 ~ 170) 184
5457 11:19:22.523914 iDelay=199, Bit 12, Center 90 (-1 ~ 182) 184
5458 11:19:22.526699 iDelay=199, Bit 13, Center 90 (-1 ~ 182) 184
5459 11:19:22.530264 iDelay=199, Bit 14, Center 96 (7 ~ 186) 180
5460 11:19:22.533455 iDelay=199, Bit 15, Center 92 (-1 ~ 186) 188
5461 11:19:22.533546 ==
5462 11:19:22.536364 Dram Type= 6, Freq= 0, CH_0, rank 1
5463 11:19:22.540163 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5464 11:19:22.542952 ==
5465 11:19:22.543036 DQS Delay:
5466 11:19:22.543102 DQS0 = 0, DQS1 = 0
5467 11:19:22.546793 DQM Delay:
5468 11:19:22.546897 DQM0 = 92, DQM1 = 85
5469 11:19:22.549761 DQ Delay:
5470 11:19:22.549859 DQ0 =90, DQ1 =94, DQ2 =88, DQ3 =88
5471 11:19:22.553203 DQ4 =92, DQ5 =80, DQ6 =104, DQ7 =102
5472 11:19:22.556614 DQ8 =78, DQ9 =72, DQ10 =86, DQ11 =78
5473 11:19:22.563654 DQ12 =90, DQ13 =90, DQ14 =96, DQ15 =92
5474 11:19:22.563811
5475 11:19:22.563937
5476 11:19:22.569843 [DQSOSCAuto] RK1, (LSB)MR18= 0x2c0e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 408 ps
5477 11:19:22.572838 CH0 RK1: MR19=505, MR18=2C0E
5478 11:19:22.579331 CH0_RK1: MR19=0x505, MR18=0x2C0E, DQSOSC=408, MR23=63, INC=65, DEC=43
5479 11:19:22.582782 [RxdqsGatingPostProcess] freq 933
5480 11:19:22.586382 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5481 11:19:22.589864 best DQS0 dly(2T, 0.5T) = (0, 10)
5482 11:19:22.593173 best DQS1 dly(2T, 0.5T) = (0, 11)
5483 11:19:22.596280 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5484 11:19:22.599854 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5485 11:19:22.603259 best DQS0 dly(2T, 0.5T) = (0, 10)
5486 11:19:22.605856 best DQS1 dly(2T, 0.5T) = (0, 10)
5487 11:19:22.609447 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5488 11:19:22.612467 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5489 11:19:22.615732 Pre-setting of DQS Precalculation
5490 11:19:22.618720 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5491 11:19:22.618853 ==
5492 11:19:22.622629 Dram Type= 6, Freq= 0, CH_1, rank 0
5493 11:19:22.629091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5494 11:19:22.629177 ==
5495 11:19:22.632028 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5496 11:19:22.639079 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5497 11:19:22.642476 [CA 0] Center 37 (7~67) winsize 61
5498 11:19:22.645675 [CA 1] Center 37 (7~68) winsize 62
5499 11:19:22.649054 [CA 2] Center 34 (5~64) winsize 60
5500 11:19:22.652073 [CA 3] Center 34 (4~64) winsize 61
5501 11:19:22.655838 [CA 4] Center 34 (5~64) winsize 60
5502 11:19:22.658994 [CA 5] Center 33 (4~63) winsize 60
5503 11:19:22.659078
5504 11:19:22.662499 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5505 11:19:22.662583
5506 11:19:22.665694 [CATrainingPosCal] consider 1 rank data
5507 11:19:22.668900 u2DelayCellTimex100 = 270/100 ps
5508 11:19:22.672393 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5509 11:19:22.678602 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5510 11:19:22.682112 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5511 11:19:22.685155 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5512 11:19:22.688539 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5513 11:19:22.691512 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5514 11:19:22.691598
5515 11:19:22.695042 CA PerBit enable=1, Macro0, CA PI delay=33
5516 11:19:22.695151
5517 11:19:22.698137 [CBTSetCACLKResult] CA Dly = 33
5518 11:19:22.701485 CS Dly: 6 (0~37)
5519 11:19:22.701596 ==
5520 11:19:22.704882 Dram Type= 6, Freq= 0, CH_1, rank 1
5521 11:19:22.708065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5522 11:19:22.708166 ==
5523 11:19:22.714757 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5524 11:19:22.718257 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5525 11:19:22.722364 [CA 0] Center 38 (8~68) winsize 61
5526 11:19:22.725157 [CA 1] Center 37 (7~68) winsize 62
5527 11:19:22.728518 [CA 2] Center 35 (5~65) winsize 61
5528 11:19:22.732355 [CA 3] Center 34 (4~64) winsize 61
5529 11:19:22.735274 [CA 4] Center 35 (5~65) winsize 61
5530 11:19:22.738644 [CA 5] Center 34 (4~64) winsize 61
5531 11:19:22.738773
5532 11:19:22.741689 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5533 11:19:22.741792
5534 11:19:22.745132 [CATrainingPosCal] consider 2 rank data
5535 11:19:22.748572 u2DelayCellTimex100 = 270/100 ps
5536 11:19:22.751799 CA0 delay=37 (8~67),Diff = 4 PI (24 cell)
5537 11:19:22.758730 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5538 11:19:22.761850 CA2 delay=34 (5~64),Diff = 1 PI (6 cell)
5539 11:19:22.765234 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5540 11:19:22.768456 CA4 delay=34 (5~64),Diff = 1 PI (6 cell)
5541 11:19:22.771880 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
5542 11:19:22.771980
5543 11:19:22.775116 CA PerBit enable=1, Macro0, CA PI delay=33
5544 11:19:22.775204
5545 11:19:22.778530 [CBTSetCACLKResult] CA Dly = 33
5546 11:19:22.781564 CS Dly: 6 (0~38)
5547 11:19:22.781651
5548 11:19:22.784658 ----->DramcWriteLeveling(PI) begin...
5549 11:19:22.784747 ==
5550 11:19:22.788117 Dram Type= 6, Freq= 0, CH_1, rank 0
5551 11:19:22.791533 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5552 11:19:22.791616 ==
5553 11:19:22.795197 Write leveling (Byte 0): 25 => 25
5554 11:19:22.798156 Write leveling (Byte 1): 27 => 27
5555 11:19:22.801374 DramcWriteLeveling(PI) end<-----
5556 11:19:22.801452
5557 11:19:22.801517 ==
5558 11:19:22.804333 Dram Type= 6, Freq= 0, CH_1, rank 0
5559 11:19:22.807843 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5560 11:19:22.807934 ==
5561 11:19:22.810893 [Gating] SW mode calibration
5562 11:19:22.817482 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5563 11:19:22.824130 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5564 11:19:22.827581 0 14 0 | B1->B0 | 3030 3434 | 1 0 | (1 1) (0 0)
5565 11:19:22.833861 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5566 11:19:22.837366 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5567 11:19:22.840828 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5568 11:19:22.847411 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5569 11:19:22.850404 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5570 11:19:22.854048 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5571 11:19:22.860254 0 14 28 | B1->B0 | 2f2f 2f2f | 0 0 | (0 1) (1 0)
5572 11:19:22.863657 0 15 0 | B1->B0 | 2626 2727 | 0 0 | (1 1) (1 1)
5573 11:19:22.867030 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5574 11:19:22.870244 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5575 11:19:22.876952 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5576 11:19:22.880247 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5577 11:19:22.886884 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5578 11:19:22.890410 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5579 11:19:22.893378 0 15 28 | B1->B0 | 3434 3333 | 1 0 | (0 0) (1 1)
5580 11:19:22.899912 1 0 0 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
5581 11:19:22.903353 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5582 11:19:22.906765 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5583 11:19:22.913125 1 0 12 | B1->B0 | 4646 4645 | 0 1 | (0 0) (0 0)
5584 11:19:22.916449 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5585 11:19:22.919885 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5586 11:19:22.926659 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5587 11:19:22.929634 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5588 11:19:22.933195 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5589 11:19:22.939557 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 11:19:22.942432 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 11:19:22.946046 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 11:19:22.952602 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 11:19:22.956024 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 11:19:22.958881 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 11:19:22.965753 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 11:19:22.968881 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 11:19:22.972660 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5598 11:19:22.978700 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5599 11:19:22.982258 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5600 11:19:22.985452 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5601 11:19:22.991998 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5602 11:19:22.995414 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5603 11:19:22.998774 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
5604 11:19:23.002436 Total UI for P1: 0, mck2ui 16
5605 11:19:23.005180 best dqsien dly found for B1: ( 1, 2, 26)
5606 11:19:23.012088 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5607 11:19:23.012178 Total UI for P1: 0, mck2ui 16
5608 11:19:23.015036 best dqsien dly found for B0: ( 1, 2, 28)
5609 11:19:23.021816 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5610 11:19:23.025395 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5611 11:19:23.025501
5612 11:19:23.028509 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5613 11:19:23.031414 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5614 11:19:23.034832 [Gating] SW calibration Done
5615 11:19:23.034948 ==
5616 11:19:23.038185 Dram Type= 6, Freq= 0, CH_1, rank 0
5617 11:19:23.041530 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5618 11:19:23.041664 ==
5619 11:19:23.044432 RX Vref Scan: 0
5620 11:19:23.044526
5621 11:19:23.044594 RX Vref 0 -> 0, step: 1
5622 11:19:23.044658
5623 11:19:23.048014 RX Delay -80 -> 252, step: 8
5624 11:19:23.051017 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5625 11:19:23.058145 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5626 11:19:23.060923 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5627 11:19:23.064533 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5628 11:19:23.067492 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5629 11:19:23.070937 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5630 11:19:23.077465 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5631 11:19:23.080927 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5632 11:19:23.083938 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5633 11:19:23.087220 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5634 11:19:23.090519 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5635 11:19:23.097466 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5636 11:19:23.100824 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5637 11:19:23.104025 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5638 11:19:23.106987 iDelay=208, Bit 14, Center 91 (-8 ~ 191) 200
5639 11:19:23.110333 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5640 11:19:23.110422 ==
5641 11:19:23.113871 Dram Type= 6, Freq= 0, CH_1, rank 0
5642 11:19:23.120247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5643 11:19:23.120368 ==
5644 11:19:23.120457 DQS Delay:
5645 11:19:23.123859 DQS0 = 0, DQS1 = 0
5646 11:19:23.123948 DQM Delay:
5647 11:19:23.126806 DQM0 = 94, DQM1 = 86
5648 11:19:23.126918 DQ Delay:
5649 11:19:23.130203 DQ0 =99, DQ1 =91, DQ2 =87, DQ3 =91
5650 11:19:23.133603 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5651 11:19:23.136515 DQ8 =75, DQ9 =79, DQ10 =87, DQ11 =83
5652 11:19:23.139916 DQ12 =95, DQ13 =91, DQ14 =91, DQ15 =91
5653 11:19:23.140008
5654 11:19:23.140098
5655 11:19:23.140180 ==
5656 11:19:23.143329 Dram Type= 6, Freq= 0, CH_1, rank 0
5657 11:19:23.146489 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5658 11:19:23.146580 ==
5659 11:19:23.146667
5660 11:19:23.146767
5661 11:19:23.149950 TX Vref Scan disable
5662 11:19:23.153026 == TX Byte 0 ==
5663 11:19:23.156578 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5664 11:19:23.159555 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5665 11:19:23.163186 == TX Byte 1 ==
5666 11:19:23.166501 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5667 11:19:23.169575 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5668 11:19:23.169667 ==
5669 11:19:23.172923 Dram Type= 6, Freq= 0, CH_1, rank 0
5670 11:19:23.179677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5671 11:19:23.179766 ==
5672 11:19:23.179855
5673 11:19:23.179937
5674 11:19:23.180018 TX Vref Scan disable
5675 11:19:23.183581 == TX Byte 0 ==
5676 11:19:23.187058 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5677 11:19:23.193680 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5678 11:19:23.193777 == TX Byte 1 ==
5679 11:19:23.196529 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5680 11:19:23.203755 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5681 11:19:23.203890
5682 11:19:23.203984 [DATLAT]
5683 11:19:23.204067 Freq=933, CH1 RK0
5684 11:19:23.204148
5685 11:19:23.206299 DATLAT Default: 0xd
5686 11:19:23.209782 0, 0xFFFF, sum = 0
5687 11:19:23.209886 1, 0xFFFF, sum = 0
5688 11:19:23.213684 2, 0xFFFF, sum = 0
5689 11:19:23.213797 3, 0xFFFF, sum = 0
5690 11:19:23.216581 4, 0xFFFF, sum = 0
5691 11:19:23.216670 5, 0xFFFF, sum = 0
5692 11:19:23.220204 6, 0xFFFF, sum = 0
5693 11:19:23.220291 7, 0xFFFF, sum = 0
5694 11:19:23.223138 8, 0xFFFF, sum = 0
5695 11:19:23.223229 9, 0xFFFF, sum = 0
5696 11:19:23.226584 10, 0x0, sum = 1
5697 11:19:23.226672 11, 0x0, sum = 2
5698 11:19:23.229486 12, 0x0, sum = 3
5699 11:19:23.229575 13, 0x0, sum = 4
5700 11:19:23.233084 best_step = 11
5701 11:19:23.233174
5702 11:19:23.233261 ==
5703 11:19:23.236003 Dram Type= 6, Freq= 0, CH_1, rank 0
5704 11:19:23.239541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5705 11:19:23.239629 ==
5706 11:19:23.239717 RX Vref Scan: 1
5707 11:19:23.242891
5708 11:19:23.242978 RX Vref 0 -> 0, step: 1
5709 11:19:23.243064
5710 11:19:23.245852 RX Delay -69 -> 252, step: 4
5711 11:19:23.245956
5712 11:19:23.249221 Set Vref, RX VrefLevel [Byte0]: 57
5713 11:19:23.252637 [Byte1]: 49
5714 11:19:23.256435
5715 11:19:23.256522 Final RX Vref Byte 0 = 57 to rank0
5716 11:19:23.259326 Final RX Vref Byte 1 = 49 to rank0
5717 11:19:23.262771 Final RX Vref Byte 0 = 57 to rank1
5718 11:19:23.266338 Final RX Vref Byte 1 = 49 to rank1==
5719 11:19:23.269262 Dram Type= 6, Freq= 0, CH_1, rank 0
5720 11:19:23.276292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5721 11:19:23.276380 ==
5722 11:19:23.276468 DQS Delay:
5723 11:19:23.279139 DQS0 = 0, DQS1 = 0
5724 11:19:23.279225 DQM Delay:
5725 11:19:23.279312 DQM0 = 96, DQM1 = 88
5726 11:19:23.282497 DQ Delay:
5727 11:19:23.286027 DQ0 =102, DQ1 =90, DQ2 =84, DQ3 =92
5728 11:19:23.288941 DQ4 =94, DQ5 =104, DQ6 =110, DQ7 =94
5729 11:19:23.292433 DQ8 =78, DQ9 =80, DQ10 =86, DQ11 =80
5730 11:19:23.295332 DQ12 =98, DQ13 =96, DQ14 =96, DQ15 =96
5731 11:19:23.295419
5732 11:19:23.295505
5733 11:19:23.302397 [DQSOSCAuto] RK0, (LSB)MR18= 0x40c, (MSB)MR19= 0x505, tDQSOscB0 = 418 ps tDQSOscB1 = 420 ps
5734 11:19:23.305582 CH1 RK0: MR19=505, MR18=40C
5735 11:19:23.312023 CH1_RK0: MR19=0x505, MR18=0x40C, DQSOSC=418, MR23=63, INC=62, DEC=41
5736 11:19:23.312167
5737 11:19:23.315492 ----->DramcWriteLeveling(PI) begin...
5738 11:19:23.315578 ==
5739 11:19:23.318729 Dram Type= 6, Freq= 0, CH_1, rank 1
5740 11:19:23.321871 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5741 11:19:23.321971 ==
5742 11:19:23.325304 Write leveling (Byte 0): 25 => 25
5743 11:19:23.328297 Write leveling (Byte 1): 25 => 25
5744 11:19:23.331841 DramcWriteLeveling(PI) end<-----
5745 11:19:23.331930
5746 11:19:23.331993 ==
5747 11:19:23.335514 Dram Type= 6, Freq= 0, CH_1, rank 1
5748 11:19:23.338557 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5749 11:19:23.341663 ==
5750 11:19:23.341763 [Gating] SW mode calibration
5751 11:19:23.351527 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5752 11:19:23.354730 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5753 11:19:23.358072 0 14 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
5754 11:19:23.364625 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5755 11:19:23.368244 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5756 11:19:23.371200 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5757 11:19:23.377636 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5758 11:19:23.381145 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5759 11:19:23.388143 0 14 24 | B1->B0 | 3232 2f2f | 0 0 | (0 0) (0 1)
5760 11:19:23.391015 0 14 28 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
5761 11:19:23.394661 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5762 11:19:23.397419 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5763 11:19:23.404241 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5764 11:19:23.407785 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5765 11:19:23.410639 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5766 11:19:23.418052 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5767 11:19:23.421007 0 15 24 | B1->B0 | 2525 3232 | 0 0 | (0 0) (1 1)
5768 11:19:23.424435 0 15 28 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5769 11:19:23.430455 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5770 11:19:23.433923 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5771 11:19:23.437384 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5772 11:19:23.443693 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5773 11:19:23.446933 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5774 11:19:23.450217 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5775 11:19:23.456902 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5776 11:19:23.460321 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 11:19:23.463998 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 11:19:23.470299 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 11:19:23.473259 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 11:19:23.477002 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 11:19:23.483320 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 11:19:23.486275 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 11:19:23.493125 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 11:19:23.496127 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 11:19:23.499819 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5786 11:19:23.506103 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5787 11:19:23.509587 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5788 11:19:23.513170 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5789 11:19:23.519465 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5790 11:19:23.522733 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5791 11:19:23.525959 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5792 11:19:23.532458 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5793 11:19:23.535805 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5794 11:19:23.538988 Total UI for P1: 0, mck2ui 16
5795 11:19:23.542263 best dqsien dly found for B0: ( 1, 2, 26)
5796 11:19:23.545766 Total UI for P1: 0, mck2ui 16
5797 11:19:23.548967 best dqsien dly found for B1: ( 1, 2, 28)
5798 11:19:23.552380 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5799 11:19:23.555569 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5800 11:19:23.555654
5801 11:19:23.558820 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5802 11:19:23.562059 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5803 11:19:23.565671 [Gating] SW calibration Done
5804 11:19:23.565749 ==
5805 11:19:23.568473 Dram Type= 6, Freq= 0, CH_1, rank 1
5806 11:19:23.571961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5807 11:19:23.575328 ==
5808 11:19:23.575403 RX Vref Scan: 0
5809 11:19:23.575466
5810 11:19:23.578758 RX Vref 0 -> 0, step: 1
5811 11:19:23.578852
5812 11:19:23.581785 RX Delay -80 -> 252, step: 8
5813 11:19:23.585370 iDelay=208, Bit 0, Center 95 (-8 ~ 199) 208
5814 11:19:23.588148 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5815 11:19:23.591555 iDelay=208, Bit 2, Center 83 (-16 ~ 183) 200
5816 11:19:23.594686 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5817 11:19:23.601770 iDelay=208, Bit 4, Center 91 (-8 ~ 191) 200
5818 11:19:23.604644 iDelay=208, Bit 5, Center 103 (0 ~ 207) 208
5819 11:19:23.608221 iDelay=208, Bit 6, Center 103 (0 ~ 207) 208
5820 11:19:23.611146 iDelay=208, Bit 7, Center 91 (-8 ~ 191) 200
5821 11:19:23.614688 iDelay=208, Bit 8, Center 75 (-24 ~ 175) 200
5822 11:19:23.618169 iDelay=208, Bit 9, Center 79 (-16 ~ 175) 192
5823 11:19:23.624800 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5824 11:19:23.628247 iDelay=208, Bit 11, Center 83 (-16 ~ 183) 200
5825 11:19:23.631382 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5826 11:19:23.634548 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5827 11:19:23.637706 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5828 11:19:23.644407 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5829 11:19:23.644523 ==
5830 11:19:23.647410 Dram Type= 6, Freq= 0, CH_1, rank 1
5831 11:19:23.651166 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5832 11:19:23.651243 ==
5833 11:19:23.651331 DQS Delay:
5834 11:19:23.654032 DQS0 = 0, DQS1 = 0
5835 11:19:23.654102 DQM Delay:
5836 11:19:23.657457 DQM0 = 93, DQM1 = 88
5837 11:19:23.657556 DQ Delay:
5838 11:19:23.661045 DQ0 =95, DQ1 =91, DQ2 =83, DQ3 =91
5839 11:19:23.663818 DQ4 =91, DQ5 =103, DQ6 =103, DQ7 =91
5840 11:19:23.667705 DQ8 =75, DQ9 =79, DQ10 =91, DQ11 =83
5841 11:19:23.671364 DQ12 =95, DQ13 =91, DQ14 =95, DQ15 =95
5842 11:19:23.671448
5843 11:19:23.671515
5844 11:19:23.671575 ==
5845 11:19:23.673945 Dram Type= 6, Freq= 0, CH_1, rank 1
5846 11:19:23.681001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5847 11:19:23.681085 ==
5848 11:19:23.681151
5849 11:19:23.681234
5850 11:19:23.681322 TX Vref Scan disable
5851 11:19:23.683730 == TX Byte 0 ==
5852 11:19:23.687309 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5853 11:19:23.693652 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5854 11:19:23.693736 == TX Byte 1 ==
5855 11:19:23.696961 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5856 11:19:23.703854 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5857 11:19:23.703938 ==
5858 11:19:23.706761 Dram Type= 6, Freq= 0, CH_1, rank 1
5859 11:19:23.710251 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5860 11:19:23.710334 ==
5861 11:19:23.710400
5862 11:19:23.710460
5863 11:19:23.713333 TX Vref Scan disable
5864 11:19:23.713417 == TX Byte 0 ==
5865 11:19:23.720240 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5866 11:19:23.723105 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5867 11:19:23.726580 == TX Byte 1 ==
5868 11:19:23.729784 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5869 11:19:23.732968 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5870 11:19:23.733044
5871 11:19:23.733107 [DATLAT]
5872 11:19:23.736264 Freq=933, CH1 RK1
5873 11:19:23.736343
5874 11:19:23.739533 DATLAT Default: 0xb
5875 11:19:23.739613 0, 0xFFFF, sum = 0
5876 11:19:23.742790 1, 0xFFFF, sum = 0
5877 11:19:23.742891 2, 0xFFFF, sum = 0
5878 11:19:23.746492 3, 0xFFFF, sum = 0
5879 11:19:23.746582 4, 0xFFFF, sum = 0
5880 11:19:23.749750 5, 0xFFFF, sum = 0
5881 11:19:23.749857 6, 0xFFFF, sum = 0
5882 11:19:23.753164 7, 0xFFFF, sum = 0
5883 11:19:23.753271 8, 0xFFFF, sum = 0
5884 11:19:23.756318 9, 0xFFFF, sum = 0
5885 11:19:23.756394 10, 0x0, sum = 1
5886 11:19:23.759651 11, 0x0, sum = 2
5887 11:19:23.759725 12, 0x0, sum = 3
5888 11:19:23.762420 13, 0x0, sum = 4
5889 11:19:23.762603 best_step = 11
5890 11:19:23.762697
5891 11:19:23.762789 ==
5892 11:19:23.765956 Dram Type= 6, Freq= 0, CH_1, rank 1
5893 11:19:23.769542 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5894 11:19:23.772818 ==
5895 11:19:23.772895 RX Vref Scan: 0
5896 11:19:23.772958
5897 11:19:23.775966 RX Vref 0 -> 0, step: 1
5898 11:19:23.776081
5899 11:19:23.779203 RX Delay -69 -> 252, step: 4
5900 11:19:23.782680 iDelay=203, Bit 0, Center 96 (-1 ~ 194) 196
5901 11:19:23.785474 iDelay=203, Bit 1, Center 86 (-9 ~ 182) 192
5902 11:19:23.792425 iDelay=203, Bit 2, Center 82 (-13 ~ 178) 192
5903 11:19:23.795378 iDelay=203, Bit 3, Center 88 (-9 ~ 186) 196
5904 11:19:23.798798 iDelay=203, Bit 4, Center 88 (-9 ~ 186) 196
5905 11:19:23.802075 iDelay=203, Bit 5, Center 102 (7 ~ 198) 192
5906 11:19:23.805675 iDelay=203, Bit 6, Center 102 (3 ~ 202) 200
5907 11:19:23.808607 iDelay=203, Bit 7, Center 88 (-9 ~ 186) 196
5908 11:19:23.815064 iDelay=203, Bit 8, Center 76 (-17 ~ 170) 188
5909 11:19:23.818831 iDelay=203, Bit 9, Center 82 (-13 ~ 178) 192
5910 11:19:23.822132 iDelay=203, Bit 10, Center 92 (-1 ~ 186) 188
5911 11:19:23.824950 iDelay=203, Bit 11, Center 84 (-9 ~ 178) 188
5912 11:19:23.828511 iDelay=203, Bit 12, Center 96 (3 ~ 190) 188
5913 11:19:23.834979 iDelay=203, Bit 13, Center 98 (7 ~ 190) 184
5914 11:19:23.838239 iDelay=203, Bit 14, Center 98 (7 ~ 190) 184
5915 11:19:23.841586 iDelay=203, Bit 15, Center 96 (3 ~ 190) 188
5916 11:19:23.841684 ==
5917 11:19:23.845074 Dram Type= 6, Freq= 0, CH_1, rank 1
5918 11:19:23.848265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5919 11:19:23.848354 ==
5920 11:19:23.851504 DQS Delay:
5921 11:19:23.851588 DQS0 = 0, DQS1 = 0
5922 11:19:23.855027 DQM Delay:
5923 11:19:23.855111 DQM0 = 91, DQM1 = 90
5924 11:19:23.855177 DQ Delay:
5925 11:19:23.858072 DQ0 =96, DQ1 =86, DQ2 =82, DQ3 =88
5926 11:19:23.861370 DQ4 =88, DQ5 =102, DQ6 =102, DQ7 =88
5927 11:19:23.864828 DQ8 =76, DQ9 =82, DQ10 =92, DQ11 =84
5928 11:19:23.868157 DQ12 =96, DQ13 =98, DQ14 =98, DQ15 =96
5929 11:19:23.868241
5930 11:19:23.871022
5931 11:19:23.878114 [DQSOSCAuto] RK1, (LSB)MR18= 0xe21, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 417 ps
5932 11:19:23.881158 CH1 RK1: MR19=505, MR18=E21
5933 11:19:23.887779 CH1_RK1: MR19=0x505, MR18=0xE21, DQSOSC=411, MR23=63, INC=64, DEC=42
5934 11:19:23.887868 [RxdqsGatingPostProcess] freq 933
5935 11:19:23.894726 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5936 11:19:23.897656 best DQS0 dly(2T, 0.5T) = (0, 10)
5937 11:19:23.901106 best DQS1 dly(2T, 0.5T) = (0, 10)
5938 11:19:23.904517 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5939 11:19:23.907839 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5940 11:19:23.911235 best DQS0 dly(2T, 0.5T) = (0, 10)
5941 11:19:23.914403 best DQS1 dly(2T, 0.5T) = (0, 10)
5942 11:19:23.917735 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5943 11:19:23.920648 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5944 11:19:23.924184 Pre-setting of DQS Precalculation
5945 11:19:23.927820 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5946 11:19:23.934124 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5947 11:19:23.943796 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5948 11:19:23.943888
5949 11:19:23.943954
5950 11:19:23.947162 [Calibration Summary] 1866 Mbps
5951 11:19:23.947248 CH 0, Rank 0
5952 11:19:23.950411 SW Impedance : PASS
5953 11:19:23.950496 DUTY Scan : NO K
5954 11:19:23.954211 ZQ Calibration : PASS
5955 11:19:23.957260 Jitter Meter : NO K
5956 11:19:23.957345 CBT Training : PASS
5957 11:19:23.960443 Write leveling : PASS
5958 11:19:23.960544 RX DQS gating : PASS
5959 11:19:23.963862 RX DQ/DQS(RDDQC) : PASS
5960 11:19:23.967150 TX DQ/DQS : PASS
5961 11:19:23.967241 RX DATLAT : PASS
5962 11:19:23.970426 RX DQ/DQS(Engine): PASS
5963 11:19:23.973662 TX OE : NO K
5964 11:19:23.973746 All Pass.
5965 11:19:23.973814
5966 11:19:23.973876 CH 0, Rank 1
5967 11:19:23.976721 SW Impedance : PASS
5968 11:19:23.980082 DUTY Scan : NO K
5969 11:19:23.980167 ZQ Calibration : PASS
5970 11:19:23.983577 Jitter Meter : NO K
5971 11:19:23.986943 CBT Training : PASS
5972 11:19:23.987026 Write leveling : PASS
5973 11:19:23.990232 RX DQS gating : PASS
5974 11:19:23.993278 RX DQ/DQS(RDDQC) : PASS
5975 11:19:23.993363 TX DQ/DQS : PASS
5976 11:19:23.996807 RX DATLAT : PASS
5977 11:19:24.000149 RX DQ/DQS(Engine): PASS
5978 11:19:24.000234 TX OE : NO K
5979 11:19:24.003076 All Pass.
5980 11:19:24.003160
5981 11:19:24.003226 CH 1, Rank 0
5982 11:19:24.006535 SW Impedance : PASS
5983 11:19:24.006627 DUTY Scan : NO K
5984 11:19:24.009765 ZQ Calibration : PASS
5985 11:19:24.013384 Jitter Meter : NO K
5986 11:19:24.013468 CBT Training : PASS
5987 11:19:24.016408 Write leveling : PASS
5988 11:19:24.019766 RX DQS gating : PASS
5989 11:19:24.019850 RX DQ/DQS(RDDQC) : PASS
5990 11:19:24.022839 TX DQ/DQS : PASS
5991 11:19:24.026218 RX DATLAT : PASS
5992 11:19:24.026317 RX DQ/DQS(Engine): PASS
5993 11:19:24.029235 TX OE : NO K
5994 11:19:24.029319 All Pass.
5995 11:19:24.029386
5996 11:19:24.032916 CH 1, Rank 1
5997 11:19:24.033000 SW Impedance : PASS
5998 11:19:24.036112 DUTY Scan : NO K
5999 11:19:24.039137 ZQ Calibration : PASS
6000 11:19:24.039221 Jitter Meter : NO K
6001 11:19:24.042686 CBT Training : PASS
6002 11:19:24.046072 Write leveling : PASS
6003 11:19:24.046183 RX DQS gating : PASS
6004 11:19:24.048942 RX DQ/DQS(RDDQC) : PASS
6005 11:19:24.049026 TX DQ/DQS : PASS
6006 11:19:24.052298 RX DATLAT : PASS
6007 11:19:24.055592 RX DQ/DQS(Engine): PASS
6008 11:19:24.055676 TX OE : NO K
6009 11:19:24.058996 All Pass.
6010 11:19:24.059080
6011 11:19:24.059146 DramC Write-DBI off
6012 11:19:24.062024 PER_BANK_REFRESH: Hybrid Mode
6013 11:19:24.065336 TX_TRACKING: ON
6014 11:19:24.071921 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6015 11:19:24.075265 [FAST_K] Save calibration result to emmc
6016 11:19:24.082030 dramc_set_vcore_voltage set vcore to 650000
6017 11:19:24.082115 Read voltage for 400, 6
6018 11:19:24.085474 Vio18 = 0
6019 11:19:24.085559 Vcore = 650000
6020 11:19:24.085626 Vdram = 0
6021 11:19:24.088454 Vddq = 0
6022 11:19:24.088538 Vmddr = 0
6023 11:19:24.092062 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6024 11:19:24.098516 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6025 11:19:24.101554 MEM_TYPE=3, freq_sel=20
6026 11:19:24.105184 sv_algorithm_assistance_LP4_800
6027 11:19:24.108165 ============ PULL DRAM RESETB DOWN ============
6028 11:19:24.111416 ========== PULL DRAM RESETB DOWN end =========
6029 11:19:24.114855 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6030 11:19:24.117863 ===================================
6031 11:19:24.121413 LPDDR4 DRAM CONFIGURATION
6032 11:19:24.124897 ===================================
6033 11:19:24.127864 EX_ROW_EN[0] = 0x0
6034 11:19:24.127967 EX_ROW_EN[1] = 0x0
6035 11:19:24.131270 LP4Y_EN = 0x0
6036 11:19:24.131349 WORK_FSP = 0x0
6037 11:19:24.134752 WL = 0x2
6038 11:19:24.134825 RL = 0x2
6039 11:19:24.138216 BL = 0x2
6040 11:19:24.138295 RPST = 0x0
6041 11:19:24.141138 RD_PRE = 0x0
6042 11:19:24.144590 WR_PRE = 0x1
6043 11:19:24.144665 WR_PST = 0x0
6044 11:19:24.148113 DBI_WR = 0x0
6045 11:19:24.148198 DBI_RD = 0x0
6046 11:19:24.151001 OTF = 0x1
6047 11:19:24.154436 ===================================
6048 11:19:24.157885 ===================================
6049 11:19:24.157969 ANA top config
6050 11:19:24.161311 ===================================
6051 11:19:24.164554 DLL_ASYNC_EN = 0
6052 11:19:24.167840 ALL_SLAVE_EN = 1
6053 11:19:24.167925 NEW_RANK_MODE = 1
6054 11:19:24.171258 DLL_IDLE_MODE = 1
6055 11:19:24.174037 LP45_APHY_COMB_EN = 1
6056 11:19:24.177952 TX_ODT_DIS = 1
6057 11:19:24.181162 NEW_8X_MODE = 1
6058 11:19:24.184355 ===================================
6059 11:19:24.187196 ===================================
6060 11:19:24.187280 data_rate = 800
6061 11:19:24.190810 CKR = 1
6062 11:19:24.193963 DQ_P2S_RATIO = 4
6063 11:19:24.197390 ===================================
6064 11:19:24.200841 CA_P2S_RATIO = 4
6065 11:19:24.203934 DQ_CA_OPEN = 0
6066 11:19:24.206995 DQ_SEMI_OPEN = 1
6067 11:19:24.207117 CA_SEMI_OPEN = 1
6068 11:19:24.210449 CA_FULL_RATE = 0
6069 11:19:24.213796 DQ_CKDIV4_EN = 0
6070 11:19:24.217086 CA_CKDIV4_EN = 1
6071 11:19:24.220475 CA_PREDIV_EN = 0
6072 11:19:24.223989 PH8_DLY = 0
6073 11:19:24.224073 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6074 11:19:24.227029 DQ_AAMCK_DIV = 0
6075 11:19:24.230410 CA_AAMCK_DIV = 0
6076 11:19:24.233895 CA_ADMCK_DIV = 4
6077 11:19:24.236939 DQ_TRACK_CA_EN = 0
6078 11:19:24.240271 CA_PICK = 800
6079 11:19:24.243851 CA_MCKIO = 400
6080 11:19:24.243936 MCKIO_SEMI = 400
6081 11:19:24.247148 PLL_FREQ = 3016
6082 11:19:24.250279 DQ_UI_PI_RATIO = 32
6083 11:19:24.253629 CA_UI_PI_RATIO = 32
6084 11:19:24.256774 ===================================
6085 11:19:24.260110 ===================================
6086 11:19:24.263288 memory_type:LPDDR4
6087 11:19:24.263372 GP_NUM : 10
6088 11:19:24.266591 SRAM_EN : 1
6089 11:19:24.270105 MD32_EN : 0
6090 11:19:24.273188 ===================================
6091 11:19:24.273272 [ANA_INIT] >>>>>>>>>>>>>>
6092 11:19:24.276445 <<<<<< [CONFIGURE PHASE]: ANA_TX
6093 11:19:24.279838 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6094 11:19:24.283035 ===================================
6095 11:19:24.286468 data_rate = 800,PCW = 0X7400
6096 11:19:24.289766 ===================================
6097 11:19:24.293094 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6098 11:19:24.299800 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6099 11:19:24.309497 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6100 11:19:24.315871 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6101 11:19:24.319028 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6102 11:19:24.322589 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6103 11:19:24.322675 [ANA_INIT] flow start
6104 11:19:24.325969 [ANA_INIT] PLL >>>>>>>>
6105 11:19:24.329123 [ANA_INIT] PLL <<<<<<<<
6106 11:19:24.332373 [ANA_INIT] MIDPI >>>>>>>>
6107 11:19:24.332460 [ANA_INIT] MIDPI <<<<<<<<
6108 11:19:24.335943 [ANA_INIT] DLL >>>>>>>>
6109 11:19:24.339039 [ANA_INIT] flow end
6110 11:19:24.342554 ============ LP4 DIFF to SE enter ============
6111 11:19:24.345355 ============ LP4 DIFF to SE exit ============
6112 11:19:24.348849 [ANA_INIT] <<<<<<<<<<<<<
6113 11:19:24.352286 [Flow] Enable top DCM control >>>>>
6114 11:19:24.355090 [Flow] Enable top DCM control <<<<<
6115 11:19:24.358704 Enable DLL master slave shuffle
6116 11:19:24.362201 ==============================================================
6117 11:19:24.365231 Gating Mode config
6118 11:19:24.371972 ==============================================================
6119 11:19:24.372059 Config description:
6120 11:19:24.381928 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6121 11:19:24.388440 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6122 11:19:24.391947 SELPH_MODE 0: By rank 1: By Phase
6123 11:19:24.398609 ==============================================================
6124 11:19:24.401349 GAT_TRACK_EN = 0
6125 11:19:24.404800 RX_GATING_MODE = 2
6126 11:19:24.408081 RX_GATING_TRACK_MODE = 2
6127 11:19:24.411632 SELPH_MODE = 1
6128 11:19:24.414751 PICG_EARLY_EN = 1
6129 11:19:24.418059 VALID_LAT_VALUE = 1
6130 11:19:24.421342 ==============================================================
6131 11:19:24.424435 Enter into Gating configuration >>>>
6132 11:19:24.427918 Exit from Gating configuration <<<<
6133 11:19:24.431269 Enter into DVFS_PRE_config >>>>>
6134 11:19:24.444322 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6135 11:19:24.447634 Exit from DVFS_PRE_config <<<<<
6136 11:19:24.451075 Enter into PICG configuration >>>>
6137 11:19:24.451159 Exit from PICG configuration <<<<
6138 11:19:24.454595 [RX_INPUT] configuration >>>>>
6139 11:19:24.457348 [RX_INPUT] configuration <<<<<
6140 11:19:24.464387 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6141 11:19:24.467754 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6142 11:19:24.474077 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6143 11:19:24.480740 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6144 11:19:24.487288 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6145 11:19:24.493824 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6146 11:19:24.497061 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6147 11:19:24.500309 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6148 11:19:24.507050 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6149 11:19:24.510464 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6150 11:19:24.513736 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6151 11:19:24.516674 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6152 11:19:24.520647 ===================================
6153 11:19:24.523755 LPDDR4 DRAM CONFIGURATION
6154 11:19:24.527090 ===================================
6155 11:19:24.530388 EX_ROW_EN[0] = 0x0
6156 11:19:24.530482 EX_ROW_EN[1] = 0x0
6157 11:19:24.533685 LP4Y_EN = 0x0
6158 11:19:24.533794 WORK_FSP = 0x0
6159 11:19:24.537062 WL = 0x2
6160 11:19:24.537145 RL = 0x2
6161 11:19:24.539982 BL = 0x2
6162 11:19:24.540081 RPST = 0x0
6163 11:19:24.543516 RD_PRE = 0x0
6164 11:19:24.543599 WR_PRE = 0x1
6165 11:19:24.547088 WR_PST = 0x0
6166 11:19:24.549844 DBI_WR = 0x0
6167 11:19:24.549941 DBI_RD = 0x0
6168 11:19:24.553467 OTF = 0x1
6169 11:19:24.556898 ===================================
6170 11:19:24.559797 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6171 11:19:24.563343 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6172 11:19:24.566249 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6173 11:19:24.569777 ===================================
6174 11:19:24.573238 LPDDR4 DRAM CONFIGURATION
6175 11:19:24.576387 ===================================
6176 11:19:24.579674 EX_ROW_EN[0] = 0x10
6177 11:19:24.579768 EX_ROW_EN[1] = 0x0
6178 11:19:24.583127 LP4Y_EN = 0x0
6179 11:19:24.583211 WORK_FSP = 0x0
6180 11:19:24.586434 WL = 0x2
6181 11:19:24.586542 RL = 0x2
6182 11:19:24.589944 BL = 0x2
6183 11:19:24.590046 RPST = 0x0
6184 11:19:24.592998 RD_PRE = 0x0
6185 11:19:24.595844 WR_PRE = 0x1
6186 11:19:24.595919 WR_PST = 0x0
6187 11:19:24.599201 DBI_WR = 0x0
6188 11:19:24.599284 DBI_RD = 0x0
6189 11:19:24.602727 OTF = 0x1
6190 11:19:24.606088 ===================================
6191 11:19:24.612709 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6192 11:19:24.615500 nWR fixed to 30
6193 11:19:24.615615 [ModeRegInit_LP4] CH0 RK0
6194 11:19:24.618959 [ModeRegInit_LP4] CH0 RK1
6195 11:19:24.622537 [ModeRegInit_LP4] CH1 RK0
6196 11:19:24.622620 [ModeRegInit_LP4] CH1 RK1
6197 11:19:24.625507 match AC timing 19
6198 11:19:24.629152 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6199 11:19:24.635185 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6200 11:19:24.638558 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6201 11:19:24.641870 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6202 11:19:24.648360 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6203 11:19:24.648482 ==
6204 11:19:24.651827 Dram Type= 6, Freq= 0, CH_0, rank 0
6205 11:19:24.655376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6206 11:19:24.655459 ==
6207 11:19:24.662106 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6208 11:19:24.668329 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6209 11:19:24.671678 [CA 0] Center 36 (8~64) winsize 57
6210 11:19:24.674640 [CA 1] Center 36 (8~64) winsize 57
6211 11:19:24.674759 [CA 2] Center 36 (8~64) winsize 57
6212 11:19:24.678428 [CA 3] Center 36 (8~64) winsize 57
6213 11:19:24.681202 [CA 4] Center 36 (8~64) winsize 57
6214 11:19:24.684844 [CA 5] Center 36 (8~64) winsize 57
6215 11:19:24.684944
6216 11:19:24.687747 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6217 11:19:24.691518
6218 11:19:24.694867 [CATrainingPosCal] consider 1 rank data
6219 11:19:24.694952 u2DelayCellTimex100 = 270/100 ps
6220 11:19:24.700954 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6221 11:19:24.704281 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6222 11:19:24.707843 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6223 11:19:24.710980 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6224 11:19:24.714436 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6225 11:19:24.717542 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6226 11:19:24.717627
6227 11:19:24.720897 CA PerBit enable=1, Macro0, CA PI delay=36
6228 11:19:24.720983
6229 11:19:24.724613 [CBTSetCACLKResult] CA Dly = 36
6230 11:19:24.727390 CS Dly: 1 (0~32)
6231 11:19:24.727489 ==
6232 11:19:24.730797 Dram Type= 6, Freq= 0, CH_0, rank 1
6233 11:19:24.734248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6234 11:19:24.734328 ==
6235 11:19:24.741099 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6236 11:19:24.747117 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6237 11:19:24.750530 [CA 0] Center 36 (8~64) winsize 57
6238 11:19:24.750618 [CA 1] Center 36 (8~64) winsize 57
6239 11:19:24.753545 [CA 2] Center 36 (8~64) winsize 57
6240 11:19:24.757076 [CA 3] Center 36 (8~64) winsize 57
6241 11:19:24.760446 [CA 4] Center 36 (8~64) winsize 57
6242 11:19:24.763508 [CA 5] Center 36 (8~64) winsize 57
6243 11:19:24.763593
6244 11:19:24.767216 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6245 11:19:24.767301
6246 11:19:24.773748 [CATrainingPosCal] consider 2 rank data
6247 11:19:24.773865 u2DelayCellTimex100 = 270/100 ps
6248 11:19:24.780101 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6249 11:19:24.783428 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6250 11:19:24.786948 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6251 11:19:24.789904 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6252 11:19:24.793376 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6253 11:19:24.796237 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6254 11:19:24.796321
6255 11:19:24.799616 CA PerBit enable=1, Macro0, CA PI delay=36
6256 11:19:24.799700
6257 11:19:24.802932 [CBTSetCACLKResult] CA Dly = 36
6258 11:19:24.806091 CS Dly: 1 (0~32)
6259 11:19:24.806179
6260 11:19:24.809444 ----->DramcWriteLeveling(PI) begin...
6261 11:19:24.809529 ==
6262 11:19:24.813088 Dram Type= 6, Freq= 0, CH_0, rank 0
6263 11:19:24.815997 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6264 11:19:24.816082 ==
6265 11:19:24.819414 Write leveling (Byte 0): 40 => 8
6266 11:19:24.822602 Write leveling (Byte 1): 40 => 8
6267 11:19:24.826499 DramcWriteLeveling(PI) end<-----
6268 11:19:24.826583
6269 11:19:24.826650 ==
6270 11:19:24.829201 Dram Type= 6, Freq= 0, CH_0, rank 0
6271 11:19:24.832790 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6272 11:19:24.832875 ==
6273 11:19:24.835765 [Gating] SW mode calibration
6274 11:19:24.842604 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6275 11:19:24.849356 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6276 11:19:24.852486 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6277 11:19:24.859383 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6278 11:19:24.862148 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6279 11:19:24.865666 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6280 11:19:24.872006 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6281 11:19:24.875763 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6282 11:19:24.878782 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6283 11:19:24.885366 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6284 11:19:24.888178 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6285 11:19:24.891834 Total UI for P1: 0, mck2ui 16
6286 11:19:24.895300 best dqsien dly found for B0: ( 0, 14, 24)
6287 11:19:24.898188 Total UI for P1: 0, mck2ui 16
6288 11:19:24.901552 best dqsien dly found for B1: ( 0, 14, 24)
6289 11:19:24.905017 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6290 11:19:24.908336 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6291 11:19:24.908420
6292 11:19:24.911483 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6293 11:19:24.914772 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6294 11:19:24.918055 [Gating] SW calibration Done
6295 11:19:24.918130 ==
6296 11:19:24.921311 Dram Type= 6, Freq= 0, CH_0, rank 0
6297 11:19:24.927744 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6298 11:19:24.927836 ==
6299 11:19:24.927901 RX Vref Scan: 0
6300 11:19:24.927961
6301 11:19:24.931036 RX Vref 0 -> 0, step: 1
6302 11:19:24.931148
6303 11:19:24.934376 RX Delay -410 -> 252, step: 16
6304 11:19:24.937905 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6305 11:19:24.940896 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6306 11:19:24.947182 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6307 11:19:24.950546 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6308 11:19:24.954011 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6309 11:19:24.957342 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6310 11:19:24.963952 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6311 11:19:24.967305 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6312 11:19:24.970706 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6313 11:19:24.974059 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6314 11:19:24.980388 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6315 11:19:24.983974 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6316 11:19:24.986757 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6317 11:19:24.990385 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6318 11:19:24.996819 iDelay=230, Bit 14, Center -35 (-298 ~ 229) 528
6319 11:19:25.000497 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6320 11:19:25.000581 ==
6321 11:19:25.003731 Dram Type= 6, Freq= 0, CH_0, rank 0
6322 11:19:25.006876 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6323 11:19:25.006958 ==
6324 11:19:25.010423 DQS Delay:
6325 11:19:25.010505 DQS0 = 59, DQS1 = 59
6326 11:19:25.013467 DQM Delay:
6327 11:19:25.013549 DQM0 = 18, DQM1 = 10
6328 11:19:25.016963 DQ Delay:
6329 11:19:25.017045 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6330 11:19:25.020011 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6331 11:19:25.023244 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6332 11:19:25.026610 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6333 11:19:25.026691
6334 11:19:25.026755
6335 11:19:25.029998 ==
6336 11:19:25.030079 Dram Type= 6, Freq= 0, CH_0, rank 0
6337 11:19:25.036299 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6338 11:19:25.036384 ==
6339 11:19:25.036448
6340 11:19:25.036533
6341 11:19:25.039393 TX Vref Scan disable
6342 11:19:25.039475 == TX Byte 0 ==
6343 11:19:25.043030 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6344 11:19:25.049563 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6345 11:19:25.049650 == TX Byte 1 ==
6346 11:19:25.053189 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6347 11:19:25.059316 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6348 11:19:25.059400 ==
6349 11:19:25.062961 Dram Type= 6, Freq= 0, CH_0, rank 0
6350 11:19:25.066173 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6351 11:19:25.066286 ==
6352 11:19:25.066351
6353 11:19:25.066412
6354 11:19:25.069533 TX Vref Scan disable
6355 11:19:25.069615 == TX Byte 0 ==
6356 11:19:25.072835 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6357 11:19:25.079506 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6358 11:19:25.079591 == TX Byte 1 ==
6359 11:19:25.082807 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6360 11:19:25.089156 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6361 11:19:25.089240
6362 11:19:25.089347 [DATLAT]
6363 11:19:25.089434 Freq=400, CH0 RK0
6364 11:19:25.092651
6365 11:19:25.092746 DATLAT Default: 0xf
6366 11:19:25.095738 0, 0xFFFF, sum = 0
6367 11:19:25.095834 1, 0xFFFF, sum = 0
6368 11:19:25.099228 2, 0xFFFF, sum = 0
6369 11:19:25.099311 3, 0xFFFF, sum = 0
6370 11:19:25.102832 4, 0xFFFF, sum = 0
6371 11:19:25.102961 5, 0xFFFF, sum = 0
6372 11:19:25.105638 6, 0xFFFF, sum = 0
6373 11:19:25.105720 7, 0xFFFF, sum = 0
6374 11:19:25.109485 8, 0xFFFF, sum = 0
6375 11:19:25.109568 9, 0xFFFF, sum = 0
6376 11:19:25.112291 10, 0xFFFF, sum = 0
6377 11:19:25.112374 11, 0xFFFF, sum = 0
6378 11:19:25.115525 12, 0xFFFF, sum = 0
6379 11:19:25.115608 13, 0x0, sum = 1
6380 11:19:25.118810 14, 0x0, sum = 2
6381 11:19:25.118917 15, 0x0, sum = 3
6382 11:19:25.122106 16, 0x0, sum = 4
6383 11:19:25.122189 best_step = 14
6384 11:19:25.122254
6385 11:19:25.122313 ==
6386 11:19:25.125801 Dram Type= 6, Freq= 0, CH_0, rank 0
6387 11:19:25.132328 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6388 11:19:25.132412 ==
6389 11:19:25.132507 RX Vref Scan: 1
6390 11:19:25.132626
6391 11:19:25.135576 RX Vref 0 -> 0, step: 1
6392 11:19:25.135657
6393 11:19:25.139185 RX Delay -359 -> 252, step: 8
6394 11:19:25.139267
6395 11:19:25.142096 Set Vref, RX VrefLevel [Byte0]: 61
6396 11:19:25.145498 [Byte1]: 57
6397 11:19:25.148394
6398 11:19:25.148476 Final RX Vref Byte 0 = 61 to rank0
6399 11:19:25.151916 Final RX Vref Byte 1 = 57 to rank0
6400 11:19:25.154945 Final RX Vref Byte 0 = 61 to rank1
6401 11:19:25.158395 Final RX Vref Byte 1 = 57 to rank1==
6402 11:19:25.161873 Dram Type= 6, Freq= 0, CH_0, rank 0
6403 11:19:25.168048 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6404 11:19:25.168132 ==
6405 11:19:25.168196 DQS Delay:
6406 11:19:25.171455 DQS0 = 60, DQS1 = 68
6407 11:19:25.171562 DQM Delay:
6408 11:19:25.171654 DQM0 = 14, DQM1 = 14
6409 11:19:25.175190 DQ Delay:
6410 11:19:25.178453 DQ0 =12, DQ1 =16, DQ2 =12, DQ3 =8
6411 11:19:25.181359 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =24
6412 11:19:25.181441 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6413 11:19:25.188425 DQ12 =16, DQ13 =20, DQ14 =24, DQ15 =20
6414 11:19:25.188507
6415 11:19:25.188572
6416 11:19:25.194586 [DQSOSCAuto] RK0, (LSB)MR18= 0x8281, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 393 ps
6417 11:19:25.198102 CH0 RK0: MR19=C0C, MR18=8281
6418 11:19:25.204586 CH0_RK0: MR19=0xC0C, MR18=0x8281, DQSOSC=393, MR23=63, INC=382, DEC=254
6419 11:19:25.204673 ==
6420 11:19:25.207532 Dram Type= 6, Freq= 0, CH_0, rank 1
6421 11:19:25.210984 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6422 11:19:25.211071 ==
6423 11:19:25.214476 [Gating] SW mode calibration
6424 11:19:25.220930 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6425 11:19:25.227365 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6426 11:19:25.230665 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6427 11:19:25.234350 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6428 11:19:25.240768 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6429 11:19:25.243870 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6430 11:19:25.247071 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6431 11:19:25.253898 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6432 11:19:25.257524 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6433 11:19:25.260964 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6434 11:19:25.267636 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6435 11:19:25.270706 Total UI for P1: 0, mck2ui 16
6436 11:19:25.273822 best dqsien dly found for B0: ( 0, 14, 24)
6437 11:19:25.277115 Total UI for P1: 0, mck2ui 16
6438 11:19:25.280843 best dqsien dly found for B1: ( 0, 14, 24)
6439 11:19:25.283617 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6440 11:19:25.286747 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6441 11:19:25.286897
6442 11:19:25.290045 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6443 11:19:25.293841 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6444 11:19:25.296796 [Gating] SW calibration Done
6445 11:19:25.296887 ==
6446 11:19:25.300440 Dram Type= 6, Freq= 0, CH_0, rank 1
6447 11:19:25.303376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6448 11:19:25.303460 ==
6449 11:19:25.307252 RX Vref Scan: 0
6450 11:19:25.307335
6451 11:19:25.309847 RX Vref 0 -> 0, step: 1
6452 11:19:25.309930
6453 11:19:25.309996 RX Delay -410 -> 252, step: 16
6454 11:19:25.316894 iDelay=230, Bit 0, Center -43 (-298 ~ 213) 512
6455 11:19:25.320346 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6456 11:19:25.323239 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6457 11:19:25.330067 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6458 11:19:25.333125 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6459 11:19:25.336319 iDelay=230, Bit 5, Center -59 (-314 ~ 197) 512
6460 11:19:25.340055 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6461 11:19:25.346697 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6462 11:19:25.350048 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6463 11:19:25.353248 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6464 11:19:25.356522 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6465 11:19:25.363036 iDelay=230, Bit 11, Center -59 (-314 ~ 197) 512
6466 11:19:25.366357 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6467 11:19:25.370067 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6468 11:19:25.372726 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6469 11:19:25.379350 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6470 11:19:25.379437 ==
6471 11:19:25.382755 Dram Type= 6, Freq= 0, CH_0, rank 1
6472 11:19:25.386309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6473 11:19:25.386394 ==
6474 11:19:25.386460 DQS Delay:
6475 11:19:25.389150 DQS0 = 59, DQS1 = 59
6476 11:19:25.389234 DQM Delay:
6477 11:19:25.392610 DQM0 = 18, DQM1 = 10
6478 11:19:25.392696 DQ Delay:
6479 11:19:25.395851 DQ0 =16, DQ1 =16, DQ2 =16, DQ3 =16
6480 11:19:25.399103 DQ4 =16, DQ5 =0, DQ6 =32, DQ7 =32
6481 11:19:25.402432 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6482 11:19:25.405983 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6483 11:19:25.406066
6484 11:19:25.406132
6485 11:19:25.406192 ==
6486 11:19:25.408923 Dram Type= 6, Freq= 0, CH_0, rank 1
6487 11:19:25.412454 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6488 11:19:25.415900 ==
6489 11:19:25.415984
6490 11:19:25.416049
6491 11:19:25.416111 TX Vref Scan disable
6492 11:19:25.418766 == TX Byte 0 ==
6493 11:19:25.422344 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6494 11:19:25.425380 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6495 11:19:25.428960 == TX Byte 1 ==
6496 11:19:25.431909 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6497 11:19:25.435315 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6498 11:19:25.435403 ==
6499 11:19:25.438453 Dram Type= 6, Freq= 0, CH_0, rank 1
6500 11:19:25.445321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6501 11:19:25.445441 ==
6502 11:19:25.445578
6503 11:19:25.445714
6504 11:19:25.445850 TX Vref Scan disable
6505 11:19:25.448546 == TX Byte 0 ==
6506 11:19:25.451654 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6507 11:19:25.454979 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6508 11:19:25.458463 == TX Byte 1 ==
6509 11:19:25.461603 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6510 11:19:25.464870 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6511 11:19:25.464957
6512 11:19:25.468304 [DATLAT]
6513 11:19:25.468409 Freq=400, CH0 RK1
6514 11:19:25.468504
6515 11:19:25.471794 DATLAT Default: 0xe
6516 11:19:25.471894 0, 0xFFFF, sum = 0
6517 11:19:25.474817 1, 0xFFFF, sum = 0
6518 11:19:25.474931 2, 0xFFFF, sum = 0
6519 11:19:25.478357 3, 0xFFFF, sum = 0
6520 11:19:25.478430 4, 0xFFFF, sum = 0
6521 11:19:25.481443 5, 0xFFFF, sum = 0
6522 11:19:25.481556 6, 0xFFFF, sum = 0
6523 11:19:25.484610 7, 0xFFFF, sum = 0
6524 11:19:25.484696 8, 0xFFFF, sum = 0
6525 11:19:25.488398 9, 0xFFFF, sum = 0
6526 11:19:25.491781 10, 0xFFFF, sum = 0
6527 11:19:25.491890 11, 0xFFFF, sum = 0
6528 11:19:25.494861 12, 0xFFFF, sum = 0
6529 11:19:25.494980 13, 0x0, sum = 1
6530 11:19:25.498202 14, 0x0, sum = 2
6531 11:19:25.498314 15, 0x0, sum = 3
6532 11:19:25.501131 16, 0x0, sum = 4
6533 11:19:25.501217 best_step = 14
6534 11:19:25.501284
6535 11:19:25.501345 ==
6536 11:19:25.504903 Dram Type= 6, Freq= 0, CH_0, rank 1
6537 11:19:25.507858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6538 11:19:25.507961 ==
6539 11:19:25.511293 RX Vref Scan: 0
6540 11:19:25.511370
6541 11:19:25.514196 RX Vref 0 -> 0, step: 1
6542 11:19:25.514271
6543 11:19:25.514337 RX Delay -359 -> 252, step: 8
6544 11:19:25.523136 iDelay=217, Bit 0, Center -52 (-303 ~ 200) 504
6545 11:19:25.526679 iDelay=217, Bit 1, Center -44 (-295 ~ 208) 504
6546 11:19:25.530297 iDelay=217, Bit 2, Center -52 (-303 ~ 200) 504
6547 11:19:25.536849 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6548 11:19:25.539734 iDelay=217, Bit 4, Center -52 (-303 ~ 200) 504
6549 11:19:25.543038 iDelay=217, Bit 5, Center -60 (-311 ~ 192) 504
6550 11:19:25.546356 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6551 11:19:25.552820 iDelay=217, Bit 7, Center -36 (-287 ~ 216) 504
6552 11:19:25.556004 iDelay=217, Bit 8, Center -60 (-311 ~ 192) 504
6553 11:19:25.559363 iDelay=217, Bit 9, Center -68 (-319 ~ 184) 504
6554 11:19:25.562525 iDelay=217, Bit 10, Center -52 (-303 ~ 200) 504
6555 11:19:25.569656 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6556 11:19:25.572525 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6557 11:19:25.575707 iDelay=217, Bit 13, Center -52 (-303 ~ 200) 504
6558 11:19:25.582133 iDelay=217, Bit 14, Center -44 (-295 ~ 208) 504
6559 11:19:25.585690 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6560 11:19:25.585794 ==
6561 11:19:25.588525 Dram Type= 6, Freq= 0, CH_0, rank 1
6562 11:19:25.591892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6563 11:19:25.591979 ==
6564 11:19:25.595611 DQS Delay:
6565 11:19:25.595696 DQS0 = 60, DQS1 = 68
6566 11:19:25.598566 DQM Delay:
6567 11:19:25.598649 DQM0 = 12, DQM1 = 14
6568 11:19:25.598716 DQ Delay:
6569 11:19:25.601859 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6570 11:19:25.605526 DQ4 =8, DQ5 =0, DQ6 =24, DQ7 =24
6571 11:19:25.608512 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6572 11:19:25.611631 DQ12 =20, DQ13 =16, DQ14 =24, DQ15 =20
6573 11:19:25.611718
6574 11:19:25.611804
6575 11:19:25.621765 [DQSOSCAuto] RK1, (LSB)MR18= 0xc67b, (MSB)MR19= 0xc0c, tDQSOscB0 = 394 ps tDQSOscB1 = 385 ps
6576 11:19:25.621863 CH0 RK1: MR19=C0C, MR18=C67B
6577 11:19:25.628281 CH0_RK1: MR19=0xC0C, MR18=0xC67B, DQSOSC=385, MR23=63, INC=398, DEC=265
6578 11:19:25.631204 [RxdqsGatingPostProcess] freq 400
6579 11:19:25.638217 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6580 11:19:25.641110 best DQS0 dly(2T, 0.5T) = (0, 10)
6581 11:19:25.644639 best DQS1 dly(2T, 0.5T) = (0, 10)
6582 11:19:25.648020 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6583 11:19:25.650947 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6584 11:19:25.654458 best DQS0 dly(2T, 0.5T) = (0, 10)
6585 11:19:25.657684 best DQS1 dly(2T, 0.5T) = (0, 10)
6586 11:19:25.661124 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6587 11:19:25.664483 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6588 11:19:25.667883 Pre-setting of DQS Precalculation
6589 11:19:25.670978 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6590 11:19:25.671067 ==
6591 11:19:25.674413 Dram Type= 6, Freq= 0, CH_1, rank 0
6592 11:19:25.677900 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6593 11:19:25.677991 ==
6594 11:19:25.684080 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6595 11:19:25.690999 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6596 11:19:25.694428 [CA 0] Center 36 (8~64) winsize 57
6597 11:19:25.697481 [CA 1] Center 36 (8~64) winsize 57
6598 11:19:25.700963 [CA 2] Center 36 (8~64) winsize 57
6599 11:19:25.704444 [CA 3] Center 36 (8~64) winsize 57
6600 11:19:25.708089 [CA 4] Center 36 (8~64) winsize 57
6601 11:19:25.708185 [CA 5] Center 36 (8~64) winsize 57
6602 11:19:25.711120
6603 11:19:25.713951 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6604 11:19:25.714034
6605 11:19:25.717734 [CATrainingPosCal] consider 1 rank data
6606 11:19:25.720933 u2DelayCellTimex100 = 270/100 ps
6607 11:19:25.723766 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6608 11:19:25.727392 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6609 11:19:25.730734 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6610 11:19:25.733540 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6611 11:19:25.737255 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6612 11:19:25.740667 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6613 11:19:25.740751
6614 11:19:25.743680 CA PerBit enable=1, Macro0, CA PI delay=36
6615 11:19:25.747204
6616 11:19:25.747288 [CBTSetCACLKResult] CA Dly = 36
6617 11:19:25.750160 CS Dly: 1 (0~32)
6618 11:19:25.750244 ==
6619 11:19:25.753523 Dram Type= 6, Freq= 0, CH_1, rank 1
6620 11:19:25.756994 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6621 11:19:25.757081 ==
6622 11:19:25.763352 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6623 11:19:25.770222 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6624 11:19:25.773460 [CA 0] Center 36 (8~64) winsize 57
6625 11:19:25.776597 [CA 1] Center 36 (8~64) winsize 57
6626 11:19:25.779938 [CA 2] Center 36 (8~64) winsize 57
6627 11:19:25.780023 [CA 3] Center 36 (8~64) winsize 57
6628 11:19:25.783203 [CA 4] Center 36 (8~64) winsize 57
6629 11:19:25.786455 [CA 5] Center 36 (8~64) winsize 57
6630 11:19:25.786541
6631 11:19:25.793244 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6632 11:19:25.793335
6633 11:19:25.796662 [CATrainingPosCal] consider 2 rank data
6634 11:19:25.799587 u2DelayCellTimex100 = 270/100 ps
6635 11:19:25.803065 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6636 11:19:25.806424 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6637 11:19:25.809767 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6638 11:19:25.813006 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6639 11:19:25.816213 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6640 11:19:25.819758 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6641 11:19:25.819844
6642 11:19:25.822597 CA PerBit enable=1, Macro0, CA PI delay=36
6643 11:19:25.822682
6644 11:19:25.826248 [CBTSetCACLKResult] CA Dly = 36
6645 11:19:25.829384 CS Dly: 1 (0~32)
6646 11:19:25.829470
6647 11:19:25.832885 ----->DramcWriteLeveling(PI) begin...
6648 11:19:25.832962 ==
6649 11:19:25.836382 Dram Type= 6, Freq= 0, CH_1, rank 0
6650 11:19:25.839392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6651 11:19:25.839478 ==
6652 11:19:25.843041 Write leveling (Byte 0): 40 => 8
6653 11:19:25.845807 Write leveling (Byte 1): 40 => 8
6654 11:19:25.849351 DramcWriteLeveling(PI) end<-----
6655 11:19:25.849436
6656 11:19:25.849503 ==
6657 11:19:25.852881 Dram Type= 6, Freq= 0, CH_1, rank 0
6658 11:19:25.855815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6659 11:19:25.855901 ==
6660 11:19:25.859185 [Gating] SW mode calibration
6661 11:19:25.865611 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6662 11:19:25.872455 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6663 11:19:25.875988 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6664 11:19:25.882349 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6665 11:19:25.885626 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6666 11:19:25.890522 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6667 11:19:25.895506 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6668 11:19:25.898803 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6669 11:19:25.901866 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6670 11:19:25.908125 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6671 11:19:25.911925 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6672 11:19:25.914785 Total UI for P1: 0, mck2ui 16
6673 11:19:25.918195 best dqsien dly found for B0: ( 0, 14, 24)
6674 11:19:25.921265 Total UI for P1: 0, mck2ui 16
6675 11:19:25.924622 best dqsien dly found for B1: ( 0, 14, 24)
6676 11:19:25.928212 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6677 11:19:25.931796 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6678 11:19:25.931881
6679 11:19:25.935079 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6680 11:19:25.937993 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6681 11:19:25.941406 [Gating] SW calibration Done
6682 11:19:25.941491 ==
6683 11:19:25.944896 Dram Type= 6, Freq= 0, CH_1, rank 0
6684 11:19:25.951376 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6685 11:19:25.951482 ==
6686 11:19:25.951550 RX Vref Scan: 0
6687 11:19:25.951612
6688 11:19:25.954471 RX Vref 0 -> 0, step: 1
6689 11:19:25.954555
6690 11:19:25.957905 RX Delay -410 -> 252, step: 16
6691 11:19:25.961276 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6692 11:19:25.964856 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6693 11:19:25.970940 iDelay=230, Bit 2, Center -51 (-314 ~ 213) 528
6694 11:19:25.974471 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6695 11:19:25.977586 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6696 11:19:25.980842 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6697 11:19:25.987517 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6698 11:19:25.991288 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6699 11:19:25.993985 iDelay=230, Bit 8, Center -67 (-330 ~ 197) 528
6700 11:19:25.997457 iDelay=230, Bit 9, Center -67 (-330 ~ 197) 528
6701 11:19:26.003786 iDelay=230, Bit 10, Center -51 (-314 ~ 213) 528
6702 11:19:26.007020 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6703 11:19:26.010340 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6704 11:19:26.013642 iDelay=230, Bit 13, Center -35 (-298 ~ 229) 528
6705 11:19:26.020506 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6706 11:19:26.023905 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6707 11:19:26.024021 ==
6708 11:19:26.026999 Dram Type= 6, Freq= 0, CH_1, rank 0
6709 11:19:26.030364 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6710 11:19:26.030451 ==
6711 11:19:26.033772 DQS Delay:
6712 11:19:26.033852 DQS0 = 51, DQS1 = 67
6713 11:19:26.037176 DQM Delay:
6714 11:19:26.037260 DQM0 = 13, DQM1 = 17
6715 11:19:26.040169 DQ Delay:
6716 11:19:26.040253 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6717 11:19:26.043193 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6718 11:19:26.046777 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6719 11:19:26.049980 DQ12 =24, DQ13 =32, DQ14 =24, DQ15 =24
6720 11:19:26.050130
6721 11:19:26.050268
6722 11:19:26.050358 ==
6723 11:19:26.053264 Dram Type= 6, Freq= 0, CH_1, rank 0
6724 11:19:26.059804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6725 11:19:26.059974 ==
6726 11:19:26.060100
6727 11:19:26.060205
6728 11:19:26.063173 TX Vref Scan disable
6729 11:19:26.063284 == TX Byte 0 ==
6730 11:19:26.066789 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6731 11:19:26.072966 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6732 11:19:26.073054 == TX Byte 1 ==
6733 11:19:26.076328 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6734 11:19:26.082804 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6735 11:19:26.082919 ==
6736 11:19:26.086344 Dram Type= 6, Freq= 0, CH_1, rank 0
6737 11:19:26.089122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6738 11:19:26.089208 ==
6739 11:19:26.089303
6740 11:19:26.089365
6741 11:19:26.092480 TX Vref Scan disable
6742 11:19:26.092593 == TX Byte 0 ==
6743 11:19:26.095682 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6744 11:19:26.102302 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6745 11:19:26.102393 == TX Byte 1 ==
6746 11:19:26.105663 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6747 11:19:26.112156 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6748 11:19:26.112246
6749 11:19:26.112314 [DATLAT]
6750 11:19:26.115455 Freq=400, CH1 RK0
6751 11:19:26.115539
6752 11:19:26.115606 DATLAT Default: 0xf
6753 11:19:26.118961 0, 0xFFFF, sum = 0
6754 11:19:26.119046 1, 0xFFFF, sum = 0
6755 11:19:26.122411 2, 0xFFFF, sum = 0
6756 11:19:26.122524 3, 0xFFFF, sum = 0
6757 11:19:26.125370 4, 0xFFFF, sum = 0
6758 11:19:26.125456 5, 0xFFFF, sum = 0
6759 11:19:26.128947 6, 0xFFFF, sum = 0
6760 11:19:26.129033 7, 0xFFFF, sum = 0
6761 11:19:26.132345 8, 0xFFFF, sum = 0
6762 11:19:26.132431 9, 0xFFFF, sum = 0
6763 11:19:26.135403 10, 0xFFFF, sum = 0
6764 11:19:26.135502 11, 0xFFFF, sum = 0
6765 11:19:26.138558 12, 0xFFFF, sum = 0
6766 11:19:26.138673 13, 0x0, sum = 1
6767 11:19:26.141740 14, 0x0, sum = 2
6768 11:19:26.141845 15, 0x0, sum = 3
6769 11:19:26.145226 16, 0x0, sum = 4
6770 11:19:26.145312 best_step = 14
6771 11:19:26.145379
6772 11:19:26.145442 ==
6773 11:19:26.148522 Dram Type= 6, Freq= 0, CH_1, rank 0
6774 11:19:26.155079 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6775 11:19:26.155193 ==
6776 11:19:26.155262 RX Vref Scan: 1
6777 11:19:26.155325
6778 11:19:26.158569 RX Vref 0 -> 0, step: 1
6779 11:19:26.158654
6780 11:19:26.161518 RX Delay -375 -> 252, step: 8
6781 11:19:26.161602
6782 11:19:26.164976 Set Vref, RX VrefLevel [Byte0]: 57
6783 11:19:26.167828 [Byte1]: 49
6784 11:19:26.171812
6785 11:19:26.171897 Final RX Vref Byte 0 = 57 to rank0
6786 11:19:26.175351 Final RX Vref Byte 1 = 49 to rank0
6787 11:19:26.178441 Final RX Vref Byte 0 = 57 to rank1
6788 11:19:26.181720 Final RX Vref Byte 1 = 49 to rank1==
6789 11:19:26.185370 Dram Type= 6, Freq= 0, CH_1, rank 0
6790 11:19:26.191601 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6791 11:19:26.191689 ==
6792 11:19:26.191757 DQS Delay:
6793 11:19:26.194836 DQS0 = 52, DQS1 = 68
6794 11:19:26.194935 DQM Delay:
6795 11:19:26.195003 DQM0 = 9, DQM1 = 14
6796 11:19:26.198194 DQ Delay:
6797 11:19:26.201623 DQ0 =16, DQ1 =4, DQ2 =0, DQ3 =4
6798 11:19:26.204511 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =4
6799 11:19:26.204596 DQ8 =0, DQ9 =4, DQ10 =16, DQ11 =8
6800 11:19:26.211000 DQ12 =24, DQ13 =20, DQ14 =20, DQ15 =20
6801 11:19:26.211111
6802 11:19:26.211182
6803 11:19:26.217975 [DQSOSCAuto] RK0, (LSB)MR18= 0x5b6e, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 398 ps
6804 11:19:26.221362 CH1 RK0: MR19=C0C, MR18=5B6E
6805 11:19:26.227512 CH1_RK0: MR19=0xC0C, MR18=0x5B6E, DQSOSC=395, MR23=63, INC=378, DEC=252
6806 11:19:26.227623 ==
6807 11:19:26.231053 Dram Type= 6, Freq= 0, CH_1, rank 1
6808 11:19:26.233960 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6809 11:19:26.234041 ==
6810 11:19:26.237489 [Gating] SW mode calibration
6811 11:19:26.244070 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6812 11:19:26.250711 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6813 11:19:26.254132 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6814 11:19:26.257526 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6815 11:19:26.264039 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6816 11:19:26.267053 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6817 11:19:26.270538 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6818 11:19:26.277297 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6819 11:19:26.280236 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6820 11:19:26.283726 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6821 11:19:26.289987 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6822 11:19:26.293639 Total UI for P1: 0, mck2ui 16
6823 11:19:26.297125 best dqsien dly found for B0: ( 0, 14, 24)
6824 11:19:26.297210 Total UI for P1: 0, mck2ui 16
6825 11:19:26.303712 best dqsien dly found for B1: ( 0, 14, 24)
6826 11:19:26.306760 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6827 11:19:26.310010 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6828 11:19:26.310095
6829 11:19:26.313404 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6830 11:19:26.316599 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6831 11:19:26.319819 [Gating] SW calibration Done
6832 11:19:26.319903 ==
6833 11:19:26.323104 Dram Type= 6, Freq= 0, CH_1, rank 1
6834 11:19:26.326351 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6835 11:19:26.326437 ==
6836 11:19:26.329528 RX Vref Scan: 0
6837 11:19:26.329710
6838 11:19:26.333102 RX Vref 0 -> 0, step: 1
6839 11:19:26.333211
6840 11:19:26.333306 RX Delay -410 -> 252, step: 16
6841 11:19:26.340160 iDelay=230, Bit 0, Center -35 (-298 ~ 229) 528
6842 11:19:26.343026 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6843 11:19:26.346597 iDelay=230, Bit 2, Center -59 (-314 ~ 197) 512
6844 11:19:26.349727 iDelay=230, Bit 3, Center -43 (-298 ~ 213) 512
6845 11:19:26.356765 iDelay=230, Bit 4, Center -43 (-298 ~ 213) 512
6846 11:19:26.359859 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6847 11:19:26.363100 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6848 11:19:26.369569 iDelay=230, Bit 7, Center -43 (-298 ~ 213) 512
6849 11:19:26.373259 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6850 11:19:26.376058 iDelay=230, Bit 9, Center -51 (-314 ~ 213) 528
6851 11:19:26.379584 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6852 11:19:26.385956 iDelay=230, Bit 11, Center -51 (-314 ~ 213) 528
6853 11:19:26.389316 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6854 11:19:26.392955 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6855 11:19:26.395802 iDelay=230, Bit 14, Center -43 (-298 ~ 213) 512
6856 11:19:26.402406 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6857 11:19:26.402482 ==
6858 11:19:26.405977 Dram Type= 6, Freq= 0, CH_1, rank 1
6859 11:19:26.409207 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6860 11:19:26.409292 ==
6861 11:19:26.409361 DQS Delay:
6862 11:19:26.412576 DQS0 = 59, DQS1 = 59
6863 11:19:26.412661 DQM Delay:
6864 11:19:26.416199 DQM0 = 19, DQM1 = 12
6865 11:19:26.416283 DQ Delay:
6866 11:19:26.418946 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
6867 11:19:26.422265 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
6868 11:19:26.425405 DQ8 =0, DQ9 =8, DQ10 =16, DQ11 =8
6869 11:19:26.428971 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6870 11:19:26.429056
6871 11:19:26.429123
6872 11:19:26.429186 ==
6873 11:19:26.432298 Dram Type= 6, Freq= 0, CH_1, rank 1
6874 11:19:26.435753 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6875 11:19:26.438562 ==
6876 11:19:26.438671
6877 11:19:26.438765
6878 11:19:26.438873 TX Vref Scan disable
6879 11:19:26.442134 == TX Byte 0 ==
6880 11:19:26.445695 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6881 11:19:26.448723 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6882 11:19:26.452111 == TX Byte 1 ==
6883 11:19:26.455182 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6884 11:19:26.458564 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6885 11:19:26.458668 ==
6886 11:19:26.461819 Dram Type= 6, Freq= 0, CH_1, rank 1
6887 11:19:26.468559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6888 11:19:26.468686 ==
6889 11:19:26.468789
6890 11:19:26.468892
6891 11:19:26.468989 TX Vref Scan disable
6892 11:19:26.472012 == TX Byte 0 ==
6893 11:19:26.475029 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6894 11:19:26.478448 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6895 11:19:26.481898 == TX Byte 1 ==
6896 11:19:26.484688 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6897 11:19:26.488470 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6898 11:19:26.488572
6899 11:19:26.491521 [DATLAT]
6900 11:19:26.491607 Freq=400, CH1 RK1
6901 11:19:26.491694
6902 11:19:26.495063 DATLAT Default: 0xe
6903 11:19:26.495150 0, 0xFFFF, sum = 0
6904 11:19:26.498697 1, 0xFFFF, sum = 0
6905 11:19:26.498784 2, 0xFFFF, sum = 0
6906 11:19:26.501617 3, 0xFFFF, sum = 0
6907 11:19:26.501703 4, 0xFFFF, sum = 0
6908 11:19:26.504476 5, 0xFFFF, sum = 0
6909 11:19:26.504579 6, 0xFFFF, sum = 0
6910 11:19:26.508087 7, 0xFFFF, sum = 0
6911 11:19:26.508173 8, 0xFFFF, sum = 0
6912 11:19:26.511644 9, 0xFFFF, sum = 0
6913 11:19:26.511730 10, 0xFFFF, sum = 0
6914 11:19:26.514554 11, 0xFFFF, sum = 0
6915 11:19:26.518002 12, 0xFFFF, sum = 0
6916 11:19:26.518088 13, 0x0, sum = 1
6917 11:19:26.521050 14, 0x0, sum = 2
6918 11:19:26.521136 15, 0x0, sum = 3
6919 11:19:26.521221 16, 0x0, sum = 4
6920 11:19:26.524596 best_step = 14
6921 11:19:26.524681
6922 11:19:26.524765 ==
6923 11:19:26.527984 Dram Type= 6, Freq= 0, CH_1, rank 1
6924 11:19:26.531545 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6925 11:19:26.531631 ==
6926 11:19:26.534258 RX Vref Scan: 0
6927 11:19:26.534343
6928 11:19:26.537534 RX Vref 0 -> 0, step: 1
6929 11:19:26.537619
6930 11:19:26.537704 RX Delay -359 -> 252, step: 8
6931 11:19:26.546358 iDelay=217, Bit 0, Center -44 (-295 ~ 208) 504
6932 11:19:26.549404 iDelay=217, Bit 1, Center -52 (-303 ~ 200) 504
6933 11:19:26.552895 iDelay=217, Bit 2, Center -60 (-311 ~ 192) 504
6934 11:19:26.556381 iDelay=217, Bit 3, Center -52 (-303 ~ 200) 504
6935 11:19:26.563146 iDelay=217, Bit 4, Center -48 (-303 ~ 208) 512
6936 11:19:26.565874 iDelay=217, Bit 5, Center -36 (-287 ~ 216) 504
6937 11:19:26.569350 iDelay=217, Bit 6, Center -36 (-287 ~ 216) 504
6938 11:19:26.576164 iDelay=217, Bit 7, Center -52 (-303 ~ 200) 504
6939 11:19:26.578822 iDelay=217, Bit 8, Center -64 (-319 ~ 192) 512
6940 11:19:26.582362 iDelay=217, Bit 9, Center -64 (-319 ~ 192) 512
6941 11:19:26.585842 iDelay=217, Bit 10, Center -48 (-303 ~ 208) 512
6942 11:19:26.592113 iDelay=217, Bit 11, Center -60 (-311 ~ 192) 504
6943 11:19:26.595480 iDelay=217, Bit 12, Center -48 (-303 ~ 208) 512
6944 11:19:26.598867 iDelay=217, Bit 13, Center -48 (-303 ~ 208) 512
6945 11:19:26.605531 iDelay=217, Bit 14, Center -48 (-303 ~ 208) 512
6946 11:19:26.608482 iDelay=217, Bit 15, Center -48 (-303 ~ 208) 512
6947 11:19:26.608575 ==
6948 11:19:26.611872 Dram Type= 6, Freq= 0, CH_1, rank 1
6949 11:19:26.615440 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6950 11:19:26.615559 ==
6951 11:19:26.618382 DQS Delay:
6952 11:19:26.618467 DQS0 = 60, DQS1 = 64
6953 11:19:26.618534 DQM Delay:
6954 11:19:26.621876 DQM0 = 12, DQM1 = 10
6955 11:19:26.621970 DQ Delay:
6956 11:19:26.625340 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6957 11:19:26.628735 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
6958 11:19:26.631655 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =4
6959 11:19:26.634881 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6960 11:19:26.634966
6961 11:19:26.635034
6962 11:19:26.644732 [DQSOSCAuto] RK1, (LSB)MR18= 0x70a0, (MSB)MR19= 0xc0c, tDQSOscB0 = 389 ps tDQSOscB1 = 395 ps
6963 11:19:26.644820 CH1 RK1: MR19=C0C, MR18=70A0
6964 11:19:26.651227 CH1_RK1: MR19=0xC0C, MR18=0x70A0, DQSOSC=389, MR23=63, INC=390, DEC=260
6965 11:19:26.654711 [RxdqsGatingPostProcess] freq 400
6966 11:19:26.661120 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6967 11:19:26.664454 best DQS0 dly(2T, 0.5T) = (0, 10)
6968 11:19:26.667725 best DQS1 dly(2T, 0.5T) = (0, 10)
6969 11:19:26.671422 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6970 11:19:26.674481 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6971 11:19:26.677885 best DQS0 dly(2T, 0.5T) = (0, 10)
6972 11:19:26.681112 best DQS1 dly(2T, 0.5T) = (0, 10)
6973 11:19:26.684713 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6974 11:19:26.687594 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6975 11:19:26.687681 Pre-setting of DQS Precalculation
6976 11:19:26.694442 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6977 11:19:26.700596 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6978 11:19:26.707474 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6979 11:19:26.707565
6980 11:19:26.707633
6981 11:19:26.710421 [Calibration Summary] 800 Mbps
6982 11:19:26.713939 CH 0, Rank 0
6983 11:19:26.714040 SW Impedance : PASS
6984 11:19:26.717353 DUTY Scan : NO K
6985 11:19:26.720741 ZQ Calibration : PASS
6986 11:19:26.720830 Jitter Meter : NO K
6987 11:19:26.723855 CBT Training : PASS
6988 11:19:26.727083 Write leveling : PASS
6989 11:19:26.727209 RX DQS gating : PASS
6990 11:19:26.730516 RX DQ/DQS(RDDQC) : PASS
6991 11:19:26.733455 TX DQ/DQS : PASS
6992 11:19:26.733549 RX DATLAT : PASS
6993 11:19:26.736695 RX DQ/DQS(Engine): PASS
6994 11:19:26.739904 TX OE : NO K
6995 11:19:26.740002 All Pass.
6996 11:19:26.740070
6997 11:19:26.740132 CH 0, Rank 1
6998 11:19:26.743365 SW Impedance : PASS
6999 11:19:26.746977 DUTY Scan : NO K
7000 11:19:26.747092 ZQ Calibration : PASS
7001 11:19:26.749942 Jitter Meter : NO K
7002 11:19:26.753281 CBT Training : PASS
7003 11:19:26.753395 Write leveling : NO K
7004 11:19:26.756608 RX DQS gating : PASS
7005 11:19:26.759870 RX DQ/DQS(RDDQC) : PASS
7006 11:19:26.759978 TX DQ/DQS : PASS
7007 11:19:26.763448 RX DATLAT : PASS
7008 11:19:26.763626 RX DQ/DQS(Engine): PASS
7009 11:19:26.766429 TX OE : NO K
7010 11:19:26.766553 All Pass.
7011 11:19:26.766667
7012 11:19:26.769858 CH 1, Rank 0
7013 11:19:26.769933 SW Impedance : PASS
7014 11:19:26.773232 DUTY Scan : NO K
7015 11:19:26.776596 ZQ Calibration : PASS
7016 11:19:26.776734 Jitter Meter : NO K
7017 11:19:26.780162 CBT Training : PASS
7018 11:19:26.782912 Write leveling : PASS
7019 11:19:26.782994 RX DQS gating : PASS
7020 11:19:26.786109 RX DQ/DQS(RDDQC) : PASS
7021 11:19:26.789549 TX DQ/DQS : PASS
7022 11:19:26.789670 RX DATLAT : PASS
7023 11:19:26.793174 RX DQ/DQS(Engine): PASS
7024 11:19:26.796475 TX OE : NO K
7025 11:19:26.796560 All Pass.
7026 11:19:26.796627
7027 11:19:26.796689 CH 1, Rank 1
7028 11:19:26.799591 SW Impedance : PASS
7029 11:19:26.803024 DUTY Scan : NO K
7030 11:19:26.803114 ZQ Calibration : PASS
7031 11:19:26.805836 Jitter Meter : NO K
7032 11:19:26.809318 CBT Training : PASS
7033 11:19:26.809435 Write leveling : NO K
7034 11:19:26.812891 RX DQS gating : PASS
7035 11:19:26.816091 RX DQ/DQS(RDDQC) : PASS
7036 11:19:26.816175 TX DQ/DQS : PASS
7037 11:19:26.819678 RX DATLAT : PASS
7038 11:19:26.822959 RX DQ/DQS(Engine): PASS
7039 11:19:26.823044 TX OE : NO K
7040 11:19:26.823112 All Pass.
7041 11:19:26.825882
7042 11:19:26.825966 DramC Write-DBI off
7043 11:19:26.829410 PER_BANK_REFRESH: Hybrid Mode
7044 11:19:26.829494 TX_TRACKING: ON
7045 11:19:26.839151 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7046 11:19:26.842669 [FAST_K] Save calibration result to emmc
7047 11:19:26.845438 dramc_set_vcore_voltage set vcore to 725000
7048 11:19:26.848873 Read voltage for 1600, 0
7049 11:19:26.848960 Vio18 = 0
7050 11:19:26.852338 Vcore = 725000
7051 11:19:26.852439 Vdram = 0
7052 11:19:26.852536 Vddq = 0
7053 11:19:26.855327 Vmddr = 0
7054 11:19:26.858730 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7055 11:19:26.865196 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7056 11:19:26.865283 MEM_TYPE=3, freq_sel=13
7057 11:19:26.868762 sv_algorithm_assistance_LP4_3733
7058 11:19:26.875252 ============ PULL DRAM RESETB DOWN ============
7059 11:19:26.878578 ========== PULL DRAM RESETB DOWN end =========
7060 11:19:26.881921 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7061 11:19:26.885216 ===================================
7062 11:19:26.888531 LPDDR4 DRAM CONFIGURATION
7063 11:19:26.891940 ===================================
7064 11:19:26.895338 EX_ROW_EN[0] = 0x0
7065 11:19:26.895422 EX_ROW_EN[1] = 0x0
7066 11:19:26.898155 LP4Y_EN = 0x0
7067 11:19:26.898237 WORK_FSP = 0x1
7068 11:19:26.901539 WL = 0x5
7069 11:19:26.901622 RL = 0x5
7070 11:19:26.905071 BL = 0x2
7071 11:19:26.905154 RPST = 0x0
7072 11:19:26.908445 RD_PRE = 0x0
7073 11:19:26.908528 WR_PRE = 0x1
7074 11:19:26.911347 WR_PST = 0x1
7075 11:19:26.911430 DBI_WR = 0x0
7076 11:19:26.914755 DBI_RD = 0x0
7077 11:19:26.914861 OTF = 0x1
7078 11:19:26.918222 ===================================
7079 11:19:26.921142 ===================================
7080 11:19:26.924690 ANA top config
7081 11:19:26.928218 ===================================
7082 11:19:26.930994 DLL_ASYNC_EN = 0
7083 11:19:26.931077 ALL_SLAVE_EN = 0
7084 11:19:26.934556 NEW_RANK_MODE = 1
7085 11:19:26.937963 DLL_IDLE_MODE = 1
7086 11:19:26.941404 LP45_APHY_COMB_EN = 1
7087 11:19:26.944274 TX_ODT_DIS = 0
7088 11:19:26.944357 NEW_8X_MODE = 1
7089 11:19:26.947728 ===================================
7090 11:19:26.951104 ===================================
7091 11:19:26.954086 data_rate = 3200
7092 11:19:26.957245 CKR = 1
7093 11:19:26.961112 DQ_P2S_RATIO = 8
7094 11:19:26.964464 ===================================
7095 11:19:26.967449 CA_P2S_RATIO = 8
7096 11:19:26.971099 DQ_CA_OPEN = 0
7097 11:19:26.971183 DQ_SEMI_OPEN = 0
7098 11:19:26.974045 CA_SEMI_OPEN = 0
7099 11:19:26.977528 CA_FULL_RATE = 0
7100 11:19:26.980438 DQ_CKDIV4_EN = 0
7101 11:19:26.983930 CA_CKDIV4_EN = 0
7102 11:19:26.987125 CA_PREDIV_EN = 0
7103 11:19:26.987208 PH8_DLY = 12
7104 11:19:26.990506 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7105 11:19:26.993868 DQ_AAMCK_DIV = 4
7106 11:19:26.997297 CA_AAMCK_DIV = 4
7107 11:19:27.000559 CA_ADMCK_DIV = 4
7108 11:19:27.003905 DQ_TRACK_CA_EN = 0
7109 11:19:27.006768 CA_PICK = 1600
7110 11:19:27.006893 CA_MCKIO = 1600
7111 11:19:27.010301 MCKIO_SEMI = 0
7112 11:19:27.013894 PLL_FREQ = 3068
7113 11:19:27.016576 DQ_UI_PI_RATIO = 32
7114 11:19:27.020122 CA_UI_PI_RATIO = 0
7115 11:19:27.023838 ===================================
7116 11:19:27.027355 ===================================
7117 11:19:27.030102 memory_type:LPDDR4
7118 11:19:27.030185 GP_NUM : 10
7119 11:19:27.033598 SRAM_EN : 1
7120 11:19:27.033680 MD32_EN : 0
7121 11:19:27.036591 ===================================
7122 11:19:27.040029 [ANA_INIT] >>>>>>>>>>>>>>
7123 11:19:27.043330 <<<<<< [CONFIGURE PHASE]: ANA_TX
7124 11:19:27.046754 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7125 11:19:27.049747 ===================================
7126 11:19:27.053381 data_rate = 3200,PCW = 0X7600
7127 11:19:27.056644 ===================================
7128 11:19:27.059534 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7129 11:19:27.066073 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7130 11:19:27.069224 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7131 11:19:27.076131 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7132 11:19:27.079729 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7133 11:19:27.082615 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7134 11:19:27.082737 [ANA_INIT] flow start
7135 11:19:27.086111 [ANA_INIT] PLL >>>>>>>>
7136 11:19:27.089132 [ANA_INIT] PLL <<<<<<<<
7137 11:19:27.092247 [ANA_INIT] MIDPI >>>>>>>>
7138 11:19:27.092360 [ANA_INIT] MIDPI <<<<<<<<
7139 11:19:27.095622 [ANA_INIT] DLL >>>>>>>>
7140 11:19:27.098904 [ANA_INIT] DLL <<<<<<<<
7141 11:19:27.098987 [ANA_INIT] flow end
7142 11:19:27.102249 ============ LP4 DIFF to SE enter ============
7143 11:19:27.108912 ============ LP4 DIFF to SE exit ============
7144 11:19:27.109000 [ANA_INIT] <<<<<<<<<<<<<
7145 11:19:27.112531 [Flow] Enable top DCM control >>>>>
7146 11:19:27.115322 [Flow] Enable top DCM control <<<<<
7147 11:19:27.118757 Enable DLL master slave shuffle
7148 11:19:27.125218 ==============================================================
7149 11:19:27.128471 Gating Mode config
7150 11:19:27.132159 ==============================================================
7151 11:19:27.135143 Config description:
7152 11:19:27.145047 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7153 11:19:27.151925 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7154 11:19:27.154844 SELPH_MODE 0: By rank 1: By Phase
7155 11:19:27.161816 ==============================================================
7156 11:19:27.164694 GAT_TRACK_EN = 1
7157 11:19:27.168077 RX_GATING_MODE = 2
7158 11:19:27.171657 RX_GATING_TRACK_MODE = 2
7159 11:19:27.174776 SELPH_MODE = 1
7160 11:19:27.178027 PICG_EARLY_EN = 1
7161 11:19:27.178113 VALID_LAT_VALUE = 1
7162 11:19:27.184968 ==============================================================
7163 11:19:27.188289 Enter into Gating configuration >>>>
7164 11:19:27.191145 Exit from Gating configuration <<<<
7165 11:19:27.194584 Enter into DVFS_PRE_config >>>>>
7166 11:19:27.204551 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7167 11:19:27.207732 Exit from DVFS_PRE_config <<<<<
7168 11:19:27.211148 Enter into PICG configuration >>>>
7169 11:19:27.214306 Exit from PICG configuration <<<<
7170 11:19:27.217683 [RX_INPUT] configuration >>>>>
7171 11:19:27.221001 [RX_INPUT] configuration <<<<<
7172 11:19:27.228140 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7173 11:19:27.230820 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7174 11:19:27.237862 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7175 11:19:27.244298 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7176 11:19:27.250602 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7177 11:19:27.257435 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7178 11:19:27.260425 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7179 11:19:27.263962 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7180 11:19:27.266941 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7181 11:19:27.273841 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7182 11:19:27.276746 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7183 11:19:27.280061 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7184 11:19:27.283330 ===================================
7185 11:19:27.286787 LPDDR4 DRAM CONFIGURATION
7186 11:19:27.290029 ===================================
7187 11:19:27.293233 EX_ROW_EN[0] = 0x0
7188 11:19:27.293308 EX_ROW_EN[1] = 0x0
7189 11:19:27.296826 LP4Y_EN = 0x0
7190 11:19:27.296905 WORK_FSP = 0x1
7191 11:19:27.300253 WL = 0x5
7192 11:19:27.300360 RL = 0x5
7193 11:19:27.303525 BL = 0x2
7194 11:19:27.303637 RPST = 0x0
7195 11:19:27.306271 RD_PRE = 0x0
7196 11:19:27.306368 WR_PRE = 0x1
7197 11:19:27.309626 WR_PST = 0x1
7198 11:19:27.309704 DBI_WR = 0x0
7199 11:19:27.312925 DBI_RD = 0x0
7200 11:19:27.312996 OTF = 0x1
7201 11:19:27.316989 ===================================
7202 11:19:27.323207 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7203 11:19:27.326440 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7204 11:19:27.329832 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7205 11:19:27.332628 ===================================
7206 11:19:27.336107 LPDDR4 DRAM CONFIGURATION
7207 11:19:27.339506 ===================================
7208 11:19:27.343021 EX_ROW_EN[0] = 0x10
7209 11:19:27.343095 EX_ROW_EN[1] = 0x0
7210 11:19:27.345924 LP4Y_EN = 0x0
7211 11:19:27.345996 WORK_FSP = 0x1
7212 11:19:27.349486 WL = 0x5
7213 11:19:27.349564 RL = 0x5
7214 11:19:27.352432 BL = 0x2
7215 11:19:27.352513 RPST = 0x0
7216 11:19:27.355783 RD_PRE = 0x0
7217 11:19:27.355859 WR_PRE = 0x1
7218 11:19:27.359242 WR_PST = 0x1
7219 11:19:27.359336 DBI_WR = 0x0
7220 11:19:27.362676 DBI_RD = 0x0
7221 11:19:27.362804 OTF = 0x1
7222 11:19:27.365854 ===================================
7223 11:19:27.372200 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7224 11:19:27.372285 ==
7225 11:19:27.375961 Dram Type= 6, Freq= 0, CH_0, rank 0
7226 11:19:27.382035 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7227 11:19:27.382118 ==
7228 11:19:27.385354 [Duty_Offset_Calibration]
7229 11:19:27.385436 B0:2 B1:0 CA:3
7230 11:19:27.385533
7231 11:19:27.388741 [DutyScan_Calibration_Flow] k_type=0
7232 11:19:27.398729
7233 11:19:27.398863 ==CLK 0==
7234 11:19:27.402068 Final CLK duty delay cell = 0
7235 11:19:27.404944 [0] MAX Duty = 5031%(X100), DQS PI = 12
7236 11:19:27.408421 [0] MIN Duty = 4907%(X100), DQS PI = 6
7237 11:19:27.411577 [0] AVG Duty = 4969%(X100)
7238 11:19:27.411684
7239 11:19:27.415058 CH0 CLK Duty spec in!! Max-Min= 124%
7240 11:19:27.418280 [DutyScan_Calibration_Flow] ====Done====
7241 11:19:27.418394
7242 11:19:27.421147 [DutyScan_Calibration_Flow] k_type=1
7243 11:19:27.438284
7244 11:19:27.438377 ==DQS 0 ==
7245 11:19:27.441601 Final DQS duty delay cell = 0
7246 11:19:27.445037 [0] MAX Duty = 5094%(X100), DQS PI = 14
7247 11:19:27.448672 [0] MIN Duty = 4906%(X100), DQS PI = 46
7248 11:19:27.451647 [0] AVG Duty = 5000%(X100)
7249 11:19:27.451731
7250 11:19:27.451796 ==DQS 1 ==
7251 11:19:27.455069 Final DQS duty delay cell = 0
7252 11:19:27.457939 [0] MAX Duty = 5156%(X100), DQS PI = 32
7253 11:19:27.461402 [0] MIN Duty = 5031%(X100), DQS PI = 12
7254 11:19:27.464790 [0] AVG Duty = 5093%(X100)
7255 11:19:27.464874
7256 11:19:27.467593 CH0 DQS 0 Duty spec in!! Max-Min= 188%
7257 11:19:27.467693
7258 11:19:27.471294 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7259 11:19:27.474678 [DutyScan_Calibration_Flow] ====Done====
7260 11:19:27.474804
7261 11:19:27.477616 [DutyScan_Calibration_Flow] k_type=3
7262 11:19:27.496568
7263 11:19:27.496669 ==DQM 0 ==
7264 11:19:27.499932 Final DQM duty delay cell = 0
7265 11:19:27.503382 [0] MAX Duty = 5156%(X100), DQS PI = 30
7266 11:19:27.506356 [0] MIN Duty = 4844%(X100), DQS PI = 52
7267 11:19:27.509284 [0] AVG Duty = 5000%(X100)
7268 11:19:27.509382
7269 11:19:27.509477 ==DQM 1 ==
7270 11:19:27.512944 Final DQM duty delay cell = 4
7271 11:19:27.515987 [4] MAX Duty = 5187%(X100), DQS PI = 60
7272 11:19:27.519384 [4] MIN Duty = 5031%(X100), DQS PI = 14
7273 11:19:27.522738 [4] AVG Duty = 5109%(X100)
7274 11:19:27.522862
7275 11:19:27.526096 CH0 DQM 0 Duty spec in!! Max-Min= 312%
7276 11:19:27.526172
7277 11:19:27.529429 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7278 11:19:27.532468 [DutyScan_Calibration_Flow] ====Done====
7279 11:19:27.532541
7280 11:19:27.535845 [DutyScan_Calibration_Flow] k_type=2
7281 11:19:27.553121
7282 11:19:27.553228 ==DQ 0 ==
7283 11:19:27.556219 Final DQ duty delay cell = -4
7284 11:19:27.559528 [-4] MAX Duty = 5000%(X100), DQS PI = 14
7285 11:19:27.563326 [-4] MIN Duty = 4876%(X100), DQS PI = 0
7286 11:19:27.566419 [-4] AVG Duty = 4938%(X100)
7287 11:19:27.566539
7288 11:19:27.566638 ==DQ 1 ==
7289 11:19:27.569113 Final DQ duty delay cell = 0
7290 11:19:27.572647 [0] MAX Duty = 5156%(X100), DQS PI = 58
7291 11:19:27.576003 [0] MIN Duty = 5000%(X100), DQS PI = 16
7292 11:19:27.578959 [0] AVG Duty = 5078%(X100)
7293 11:19:27.579042
7294 11:19:27.582567 CH0 DQ 0 Duty spec in!! Max-Min= 124%
7295 11:19:27.582655
7296 11:19:27.585969 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7297 11:19:27.588945 [DutyScan_Calibration_Flow] ====Done====
7298 11:19:27.589028 ==
7299 11:19:27.592349 Dram Type= 6, Freq= 0, CH_1, rank 0
7300 11:19:27.595762 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7301 11:19:27.595845 ==
7302 11:19:27.599112 [Duty_Offset_Calibration]
7303 11:19:27.599195 B0:1 B1:-2 CA:1
7304 11:19:27.599259
7305 11:19:27.602456 [DutyScan_Calibration_Flow] k_type=0
7306 11:19:27.613402
7307 11:19:27.613486 ==CLK 0==
7308 11:19:27.616897 Final CLK duty delay cell = 0
7309 11:19:27.620317 [0] MAX Duty = 5031%(X100), DQS PI = 50
7310 11:19:27.623437 [0] MIN Duty = 4875%(X100), DQS PI = 26
7311 11:19:27.626236 [0] AVG Duty = 4953%(X100)
7312 11:19:27.626318
7313 11:19:27.629720 CH1 CLK Duty spec in!! Max-Min= 156%
7314 11:19:27.633015 [DutyScan_Calibration_Flow] ====Done====
7315 11:19:27.633098
7316 11:19:27.636290 [DutyScan_Calibration_Flow] k_type=1
7317 11:19:27.652361
7318 11:19:27.652484 ==DQS 0 ==
7319 11:19:27.655480 Final DQS duty delay cell = -4
7320 11:19:27.659047 [-4] MAX Duty = 4938%(X100), DQS PI = 4
7321 11:19:27.662036 [-4] MIN Duty = 4844%(X100), DQS PI = 14
7322 11:19:27.665768 [-4] AVG Duty = 4891%(X100)
7323 11:19:27.665876
7324 11:19:27.665969 ==DQS 1 ==
7325 11:19:27.668822 Final DQS duty delay cell = 0
7326 11:19:27.672067 [0] MAX Duty = 5124%(X100), DQS PI = 30
7327 11:19:27.675547 [0] MIN Duty = 4813%(X100), DQS PI = 58
7328 11:19:27.678495 [0] AVG Duty = 4968%(X100)
7329 11:19:27.678577
7330 11:19:27.682042 CH1 DQS 0 Duty spec in!! Max-Min= 94%
7331 11:19:27.682152
7332 11:19:27.685521 CH1 DQS 1 Duty spec in!! Max-Min= 311%
7333 11:19:27.688351 [DutyScan_Calibration_Flow] ====Done====
7334 11:19:27.688433
7335 11:19:27.691801 [DutyScan_Calibration_Flow] k_type=3
7336 11:19:27.709689
7337 11:19:27.709781 ==DQM 0 ==
7338 11:19:27.712913 Final DQM duty delay cell = 0
7339 11:19:27.716065 [0] MAX Duty = 5000%(X100), DQS PI = 0
7340 11:19:27.719451 [0] MIN Duty = 4844%(X100), DQS PI = 22
7341 11:19:27.722860 [0] AVG Duty = 4922%(X100)
7342 11:19:27.722974
7343 11:19:27.723065 ==DQM 1 ==
7344 11:19:27.725998 Final DQM duty delay cell = 0
7345 11:19:27.729597 [0] MAX Duty = 5062%(X100), DQS PI = 4
7346 11:19:27.732710 [0] MIN Duty = 4875%(X100), DQS PI = 38
7347 11:19:27.736141 [0] AVG Duty = 4968%(X100)
7348 11:19:27.736253
7349 11:19:27.739422 CH1 DQM 0 Duty spec in!! Max-Min= 156%
7350 11:19:27.739504
7351 11:19:27.742683 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7352 11:19:27.745724 [DutyScan_Calibration_Flow] ====Done====
7353 11:19:27.745806
7354 11:19:27.749110 [DutyScan_Calibration_Flow] k_type=2
7355 11:19:27.766420
7356 11:19:27.766551 ==DQ 0 ==
7357 11:19:27.769931 Final DQ duty delay cell = 0
7358 11:19:27.772799 [0] MAX Duty = 5093%(X100), DQS PI = 54
7359 11:19:27.776174 [0] MIN Duty = 4938%(X100), DQS PI = 14
7360 11:19:27.776257 [0] AVG Duty = 5015%(X100)
7361 11:19:27.779726
7362 11:19:27.779808 ==DQ 1 ==
7363 11:19:27.783258 Final DQ duty delay cell = 0
7364 11:19:27.786148 [0] MAX Duty = 5156%(X100), DQS PI = 26
7365 11:19:27.789760 [0] MIN Duty = 4938%(X100), DQS PI = 56
7366 11:19:27.789843 [0] AVG Duty = 5047%(X100)
7367 11:19:27.792665
7368 11:19:27.796199 CH1 DQ 0 Duty spec in!! Max-Min= 155%
7369 11:19:27.796282
7370 11:19:27.799448 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7371 11:19:27.802917 [DutyScan_Calibration_Flow] ====Done====
7372 11:19:27.805798 nWR fixed to 30
7373 11:19:27.805881 [ModeRegInit_LP4] CH0 RK0
7374 11:19:27.809275 [ModeRegInit_LP4] CH0 RK1
7375 11:19:27.812796 [ModeRegInit_LP4] CH1 RK0
7376 11:19:27.815850 [ModeRegInit_LP4] CH1 RK1
7377 11:19:27.815933 match AC timing 5
7378 11:19:27.822437 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7379 11:19:27.825684 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7380 11:19:27.829087 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7381 11:19:27.835457 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7382 11:19:27.838629 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7383 11:19:27.838711 [MiockJmeterHQA]
7384 11:19:27.838776
7385 11:19:27.842020 [DramcMiockJmeter] u1RxGatingPI = 0
7386 11:19:27.845379 0 : 4252, 4027
7387 11:19:27.845463 4 : 4253, 4026
7388 11:19:27.848873 8 : 4253, 4027
7389 11:19:27.848958 12 : 4253, 4027
7390 11:19:27.852338 16 : 4252, 4026
7391 11:19:27.852450 20 : 4252, 4027
7392 11:19:27.852546 24 : 4253, 4026
7393 11:19:27.855682 28 : 4363, 4137
7394 11:19:27.855766 32 : 4253, 4027
7395 11:19:27.858383 36 : 4252, 4027
7396 11:19:27.858466 40 : 4253, 4026
7397 11:19:27.862644 44 : 4250, 4026
7398 11:19:27.862729 48 : 4250, 4027
7399 11:19:27.865420 52 : 4363, 4137
7400 11:19:27.865505 56 : 4361, 4137
7401 11:19:27.865572 60 : 4250, 4027
7402 11:19:27.868775 64 : 4250, 4027
7403 11:19:27.868860 68 : 4250, 4027
7404 11:19:27.871720 72 : 4250, 4026
7405 11:19:27.871806 76 : 4254, 4032
7406 11:19:27.875244 80 : 4360, 4138
7407 11:19:27.875330 84 : 4250, 4027
7408 11:19:27.878559 88 : 4250, 4027
7409 11:19:27.878660 92 : 4250, 4026
7410 11:19:27.878731 96 : 4250, 4026
7411 11:19:27.881662 100 : 4250, 4027
7412 11:19:27.881749 104 : 4250, 3612
7413 11:19:27.885090 108 : 4250, 2
7414 11:19:27.885176 112 : 4250, 0
7415 11:19:27.888518 116 : 4363, 0
7416 11:19:27.888618 120 : 4250, 0
7417 11:19:27.888701 124 : 4250, 0
7418 11:19:27.891554 128 : 4253, 0
7419 11:19:27.891640 132 : 4250, 0
7420 11:19:27.895132 136 : 4250, 0
7421 11:19:27.895217 140 : 4250, 0
7422 11:19:27.895284 144 : 4250, 0
7423 11:19:27.897987 148 : 4361, 0
7424 11:19:27.898071 152 : 4249, 0
7425 11:19:27.898138 156 : 4250, 0
7426 11:19:27.901683 160 : 4250, 0
7427 11:19:27.901768 164 : 4361, 0
7428 11:19:27.904897 168 : 4250, 0
7429 11:19:27.904989 172 : 4250, 0
7430 11:19:27.905058 176 : 4250, 0
7431 11:19:27.907848 180 : 4250, 0
7432 11:19:27.907932 184 : 4252, 0
7433 11:19:27.911430 188 : 4250, 0
7434 11:19:27.911514 192 : 4250, 0
7435 11:19:27.911615 196 : 4252, 0
7436 11:19:27.914347 200 : 4361, 0
7437 11:19:27.914431 204 : 4250, 0
7438 11:19:27.917885 208 : 4361, 0
7439 11:19:27.917970 212 : 4250, 0
7440 11:19:27.918037 216 : 4361, 0
7441 11:19:27.921439 220 : 4360, 0
7442 11:19:27.921523 224 : 4250, 0
7443 11:19:27.924156 228 : 4250, 0
7444 11:19:27.924240 232 : 4250, 2
7445 11:19:27.924307 236 : 4252, 1460
7446 11:19:27.927653 240 : 4250, 4027
7447 11:19:27.927737 244 : 4360, 4138
7448 11:19:27.931000 248 : 4250, 4027
7449 11:19:27.931099 252 : 4250, 4027
7450 11:19:27.934263 256 : 4361, 4137
7451 11:19:27.934347 260 : 4250, 4027
7452 11:19:27.937547 264 : 4250, 4027
7453 11:19:27.937632 268 : 4250, 4027
7454 11:19:27.940927 272 : 4250, 4026
7455 11:19:27.941011 276 : 4250, 4027
7456 11:19:27.943860 280 : 4250, 4026
7457 11:19:27.943945 284 : 4361, 4137
7458 11:19:27.947530 288 : 4250, 4026
7459 11:19:27.947615 292 : 4250, 4027
7460 11:19:27.950640 296 : 4360, 4138
7461 11:19:27.950725 300 : 4250, 4027
7462 11:19:27.950792 304 : 4250, 4027
7463 11:19:27.953875 308 : 4361, 4137
7464 11:19:27.953960 312 : 4250, 4027
7465 11:19:27.957068 316 : 4250, 4026
7466 11:19:27.957179 320 : 4250, 4027
7467 11:19:27.960731 324 : 4252, 4029
7468 11:19:27.960867 328 : 4250, 4027
7469 11:19:27.963864 332 : 4250, 4027
7470 11:19:27.963948 336 : 4361, 4137
7471 11:19:27.967469 340 : 4250, 4026
7472 11:19:27.967554 344 : 4250, 4027
7473 11:19:27.970945 348 : 4360, 4138
7474 11:19:27.971031 352 : 4250, 4018
7475 11:19:27.973903 356 : 4250, 2785
7476 11:19:27.973996 360 : 4361, 0
7477 11:19:27.974064
7478 11:19:27.977463 MIOCK jitter meter ch=0
7479 11:19:27.977564
7480 11:19:27.980000 1T = (360-108) = 252 dly cells
7481 11:19:27.983316 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 258/100 ps
7482 11:19:27.983411 ==
7483 11:19:27.986821 Dram Type= 6, Freq= 0, CH_0, rank 0
7484 11:19:27.993405 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7485 11:19:27.993496 ==
7486 11:19:27.996907 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7487 11:19:28.003223 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7488 11:19:28.006732 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7489 11:19:28.012929 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7490 11:19:28.021042 [CA 0] Center 43 (13~74) winsize 62
7491 11:19:28.024685 [CA 1] Center 43 (13~74) winsize 62
7492 11:19:28.028123 [CA 2] Center 39 (10~68) winsize 59
7493 11:19:28.031099 [CA 3] Center 39 (10~68) winsize 59
7494 11:19:28.034674 [CA 4] Center 36 (7~66) winsize 60
7495 11:19:28.037603 [CA 5] Center 36 (7~66) winsize 60
7496 11:19:28.037686
7497 11:19:28.040828 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7498 11:19:28.040912
7499 11:19:28.047448 [CATrainingPosCal] consider 1 rank data
7500 11:19:28.047545 u2DelayCellTimex100 = 258/100 ps
7501 11:19:28.054401 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7502 11:19:28.057693 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7503 11:19:28.061047 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7504 11:19:28.063872 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7505 11:19:28.067287 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7506 11:19:28.070504 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7507 11:19:28.070612
7508 11:19:28.073730 CA PerBit enable=1, Macro0, CA PI delay=36
7509 11:19:28.076888
7510 11:19:28.076978 [CBTSetCACLKResult] CA Dly = 36
7511 11:19:28.080752 CS Dly: 11 (0~42)
7512 11:19:28.084064 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7513 11:19:28.086841 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7514 11:19:28.090386 ==
7515 11:19:28.094006 Dram Type= 6, Freq= 0, CH_0, rank 1
7516 11:19:28.096852 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7517 11:19:28.096939 ==
7518 11:19:28.100394 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7519 11:19:28.106806 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7520 11:19:28.110221 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7521 11:19:28.116659 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7522 11:19:28.125504 [CA 0] Center 43 (13~74) winsize 62
7523 11:19:28.128410 [CA 1] Center 43 (13~74) winsize 62
7524 11:19:28.131760 [CA 2] Center 39 (10~68) winsize 59
7525 11:19:28.135313 [CA 3] Center 39 (10~68) winsize 59
7526 11:19:28.138299 [CA 4] Center 36 (6~66) winsize 61
7527 11:19:28.141881 [CA 5] Center 36 (6~66) winsize 61
7528 11:19:28.141956
7529 11:19:28.144821 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7530 11:19:28.144920
7531 11:19:28.151691 [CATrainingPosCal] consider 2 rank data
7532 11:19:28.151777 u2DelayCellTimex100 = 258/100 ps
7533 11:19:28.157852 CA0 delay=43 (13~74),Diff = 7 PI (26 cell)
7534 11:19:28.161250 CA1 delay=43 (13~74),Diff = 7 PI (26 cell)
7535 11:19:28.164512 CA2 delay=39 (10~68),Diff = 3 PI (11 cell)
7536 11:19:28.168049 CA3 delay=39 (10~68),Diff = 3 PI (11 cell)
7537 11:19:28.171316 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
7538 11:19:28.174623 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7539 11:19:28.174734
7540 11:19:28.177888 CA PerBit enable=1, Macro0, CA PI delay=36
7541 11:19:28.181176
7542 11:19:28.181288 [CBTSetCACLKResult] CA Dly = 36
7543 11:19:28.184340 CS Dly: 11 (0~43)
7544 11:19:28.187668 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7545 11:19:28.190871 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7546 11:19:28.194345
7547 11:19:28.197278 ----->DramcWriteLeveling(PI) begin...
7548 11:19:28.197364 ==
7549 11:19:28.200998 Dram Type= 6, Freq= 0, CH_0, rank 0
7550 11:19:28.204207 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7551 11:19:28.204294 ==
7552 11:19:28.207182 Write leveling (Byte 0): 35 => 35
7553 11:19:28.210630 Write leveling (Byte 1): 25 => 25
7554 11:19:28.214098 DramcWriteLeveling(PI) end<-----
7555 11:19:28.214189
7556 11:19:28.214261 ==
7557 11:19:28.217347 Dram Type= 6, Freq= 0, CH_0, rank 0
7558 11:19:28.220163 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7559 11:19:28.220273 ==
7560 11:19:28.223688 [Gating] SW mode calibration
7561 11:19:28.230043 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7562 11:19:28.237065 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7563 11:19:28.240698 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7564 11:19:28.243382 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7565 11:19:28.250544 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7566 11:19:28.253380 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7567 11:19:28.256829 1 4 16 | B1->B0 | 2323 2525 | 0 1 | (0 0) (1 1)
7568 11:19:28.263623 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7569 11:19:28.267192 1 4 24 | B1->B0 | 3030 3434 | 1 1 | (1 1) (1 1)
7570 11:19:28.270287 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7571 11:19:28.277174 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7572 11:19:28.279900 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7573 11:19:28.283205 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7574 11:19:28.289767 1 5 12 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7575 11:19:28.293028 1 5 16 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 1)
7576 11:19:28.296261 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7577 11:19:28.302745 1 5 24 | B1->B0 | 2c2c 2323 | 0 0 | (0 0) (0 0)
7578 11:19:28.306342 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
7579 11:19:28.309873 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7580 11:19:28.316202 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7581 11:19:28.319135 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7582 11:19:28.322482 1 6 12 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7583 11:19:28.329556 1 6 16 | B1->B0 | 2323 3e3e | 0 0 | (0 0) (0 0)
7584 11:19:28.332468 1 6 20 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
7585 11:19:28.336103 1 6 24 | B1->B0 | 4040 4646 | 0 0 | (0 0) (0 0)
7586 11:19:28.342416 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7587 11:19:28.345727 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7588 11:19:28.348657 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7589 11:19:28.355848 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7590 11:19:28.359249 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7591 11:19:28.362097 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7592 11:19:28.368831 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7593 11:19:28.372025 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7594 11:19:28.375360 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7595 11:19:28.382036 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7596 11:19:28.385187 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7597 11:19:28.388640 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7598 11:19:28.395069 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7599 11:19:28.398292 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7600 11:19:28.401614 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7601 11:19:28.408196 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7602 11:19:28.411431 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7603 11:19:28.414750 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7604 11:19:28.421559 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7605 11:19:28.425084 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7606 11:19:28.427791 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7607 11:19:28.434598 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7608 11:19:28.437868 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7609 11:19:28.441424 Total UI for P1: 0, mck2ui 16
7610 11:19:28.444312 best dqsien dly found for B0: ( 1, 9, 14)
7611 11:19:28.447949 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7612 11:19:28.454252 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7613 11:19:28.457735 Total UI for P1: 0, mck2ui 16
7614 11:19:28.460624 best dqsien dly found for B1: ( 1, 9, 22)
7615 11:19:28.464102 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
7616 11:19:28.467518 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7617 11:19:28.467601
7618 11:19:28.470445 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
7619 11:19:28.473952 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7620 11:19:28.477618 [Gating] SW calibration Done
7621 11:19:28.477762 ==
7622 11:19:28.480694 Dram Type= 6, Freq= 0, CH_0, rank 0
7623 11:19:28.484295 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7624 11:19:28.484457 ==
7625 11:19:28.487257 RX Vref Scan: 0
7626 11:19:28.487372
7627 11:19:28.490551 RX Vref 0 -> 0, step: 1
7628 11:19:28.490723
7629 11:19:28.490821 RX Delay 0 -> 252, step: 8
7630 11:19:28.496837 iDelay=192, Bit 0, Center 127 (72 ~ 183) 112
7631 11:19:28.500470 iDelay=192, Bit 1, Center 131 (80 ~ 183) 104
7632 11:19:28.503826 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7633 11:19:28.507202 iDelay=192, Bit 3, Center 123 (72 ~ 175) 104
7634 11:19:28.510483 iDelay=192, Bit 4, Center 127 (72 ~ 183) 112
7635 11:19:28.516904 iDelay=192, Bit 5, Center 111 (56 ~ 167) 112
7636 11:19:28.520259 iDelay=192, Bit 6, Center 135 (80 ~ 191) 112
7637 11:19:28.523690 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7638 11:19:28.526621 iDelay=192, Bit 8, Center 115 (56 ~ 175) 120
7639 11:19:28.533500 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7640 11:19:28.536550 iDelay=192, Bit 10, Center 123 (64 ~ 183) 120
7641 11:19:28.539912 iDelay=192, Bit 11, Center 115 (56 ~ 175) 120
7642 11:19:28.543420 iDelay=192, Bit 12, Center 127 (72 ~ 183) 112
7643 11:19:28.546307 iDelay=192, Bit 13, Center 131 (72 ~ 191) 120
7644 11:19:28.553269 iDelay=192, Bit 14, Center 131 (72 ~ 191) 120
7645 11:19:28.556356 iDelay=192, Bit 15, Center 127 (72 ~ 183) 112
7646 11:19:28.556438 ==
7647 11:19:28.559778 Dram Type= 6, Freq= 0, CH_0, rank 0
7648 11:19:28.563227 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7649 11:19:28.563317 ==
7650 11:19:28.566344 DQS Delay:
7651 11:19:28.566420 DQS0 = 0, DQS1 = 0
7652 11:19:28.566483 DQM Delay:
7653 11:19:28.569757 DQM0 = 127, DQM1 = 122
7654 11:19:28.569869 DQ Delay:
7655 11:19:28.572900 DQ0 =127, DQ1 =131, DQ2 =127, DQ3 =123
7656 11:19:28.576293 DQ4 =127, DQ5 =111, DQ6 =135, DQ7 =139
7657 11:19:28.582474 DQ8 =115, DQ9 =111, DQ10 =123, DQ11 =115
7658 11:19:28.586267 DQ12 =127, DQ13 =131, DQ14 =131, DQ15 =127
7659 11:19:28.586345
7660 11:19:28.586410
7661 11:19:28.586473 ==
7662 11:19:28.589384 Dram Type= 6, Freq= 0, CH_0, rank 0
7663 11:19:28.592883 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7664 11:19:28.592957 ==
7665 11:19:28.593020
7666 11:19:28.593080
7667 11:19:28.596008 TX Vref Scan disable
7668 11:19:28.599399 == TX Byte 0 ==
7669 11:19:28.603116 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7670 11:19:28.605984 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7671 11:19:28.609280 == TX Byte 1 ==
7672 11:19:28.612254 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7673 11:19:28.615498 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7674 11:19:28.615587 ==
7675 11:19:28.618781 Dram Type= 6, Freq= 0, CH_0, rank 0
7676 11:19:28.625225 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7677 11:19:28.625337 ==
7678 11:19:28.637794
7679 11:19:28.641360 TX Vref early break, caculate TX vref
7680 11:19:28.644741 TX Vref=16, minBit 4, minWin=21, winSum=360
7681 11:19:28.647572 TX Vref=18, minBit 8, minWin=22, winSum=370
7682 11:19:28.650980 TX Vref=20, minBit 11, minWin=22, winSum=381
7683 11:19:28.654462 TX Vref=22, minBit 0, minWin=24, winSum=393
7684 11:19:28.657544 TX Vref=24, minBit 4, minWin=24, winSum=399
7685 11:19:28.664058 TX Vref=26, minBit 8, minWin=24, winSum=407
7686 11:19:28.667710 TX Vref=28, minBit 10, minWin=24, winSum=410
7687 11:19:28.670628 TX Vref=30, minBit 4, minWin=24, winSum=401
7688 11:19:28.674388 TX Vref=32, minBit 9, minWin=23, winSum=392
7689 11:19:28.677553 TX Vref=34, minBit 8, minWin=22, winSum=381
7690 11:19:28.684184 [TxChooseVref] Worse bit 10, Min win 24, Win sum 410, Final Vref 28
7691 11:19:28.684269
7692 11:19:28.687729 Final TX Range 0 Vref 28
7693 11:19:28.687813
7694 11:19:28.687878 ==
7695 11:19:28.690464 Dram Type= 6, Freq= 0, CH_0, rank 0
7696 11:19:28.693889 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7697 11:19:28.693973 ==
7698 11:19:28.694065
7699 11:19:28.697183
7700 11:19:28.697268 TX Vref Scan disable
7701 11:19:28.704260 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
7702 11:19:28.704349 == TX Byte 0 ==
7703 11:19:28.707578 u2DelayCellOfst[0]=11 cells (3 PI)
7704 11:19:28.710311 u2DelayCellOfst[1]=15 cells (4 PI)
7705 11:19:28.713685 u2DelayCellOfst[2]=7 cells (2 PI)
7706 11:19:28.716808 u2DelayCellOfst[3]=11 cells (3 PI)
7707 11:19:28.720480 u2DelayCellOfst[4]=7 cells (2 PI)
7708 11:19:28.723616 u2DelayCellOfst[5]=0 cells (0 PI)
7709 11:19:28.727084 u2DelayCellOfst[6]=18 cells (5 PI)
7710 11:19:28.730295 u2DelayCellOfst[7]=15 cells (4 PI)
7711 11:19:28.733502 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
7712 11:19:28.736844 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7713 11:19:28.740140 == TX Byte 1 ==
7714 11:19:28.743509 u2DelayCellOfst[8]=0 cells (0 PI)
7715 11:19:28.746985 u2DelayCellOfst[9]=3 cells (1 PI)
7716 11:19:28.749931 u2DelayCellOfst[10]=11 cells (3 PI)
7717 11:19:28.753496 u2DelayCellOfst[11]=7 cells (2 PI)
7718 11:19:28.756318 u2DelayCellOfst[12]=15 cells (4 PI)
7719 11:19:28.759854 u2DelayCellOfst[13]=15 cells (4 PI)
7720 11:19:28.759967 u2DelayCellOfst[14]=18 cells (5 PI)
7721 11:19:28.763461 u2DelayCellOfst[15]=15 cells (4 PI)
7722 11:19:28.769884 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7723 11:19:28.773353 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7724 11:19:28.776309 DramC Write-DBI on
7725 11:19:28.776411 ==
7726 11:19:28.779823 Dram Type= 6, Freq= 0, CH_0, rank 0
7727 11:19:28.782716 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7728 11:19:28.782820 ==
7729 11:19:28.782911
7730 11:19:28.782983
7731 11:19:28.786519 TX Vref Scan disable
7732 11:19:28.786590 == TX Byte 0 ==
7733 11:19:28.792894 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
7734 11:19:28.792973 == TX Byte 1 ==
7735 11:19:28.799278 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
7736 11:19:28.799385 DramC Write-DBI off
7737 11:19:28.799482
7738 11:19:28.799570 [DATLAT]
7739 11:19:28.802472 Freq=1600, CH0 RK0
7740 11:19:28.802575
7741 11:19:28.806022 DATLAT Default: 0xf
7742 11:19:28.806121 0, 0xFFFF, sum = 0
7743 11:19:28.809434 1, 0xFFFF, sum = 0
7744 11:19:28.809518 2, 0xFFFF, sum = 0
7745 11:19:28.812624 3, 0xFFFF, sum = 0
7746 11:19:28.812723 4, 0xFFFF, sum = 0
7747 11:19:28.815726 5, 0xFFFF, sum = 0
7748 11:19:28.815810 6, 0xFFFF, sum = 0
7749 11:19:28.818950 7, 0xFFFF, sum = 0
7750 11:19:28.819048 8, 0xFFFF, sum = 0
7751 11:19:28.822594 9, 0xFFFF, sum = 0
7752 11:19:28.822689 10, 0xFFFF, sum = 0
7753 11:19:28.825858 11, 0xFFFF, sum = 0
7754 11:19:28.825941 12, 0xFFFF, sum = 0
7755 11:19:28.829217 13, 0xEFFF, sum = 0
7756 11:19:28.829300 14, 0x0, sum = 1
7757 11:19:28.832626 15, 0x0, sum = 2
7758 11:19:28.832724 16, 0x0, sum = 3
7759 11:19:28.835905 17, 0x0, sum = 4
7760 11:19:28.835980 best_step = 15
7761 11:19:28.836043
7762 11:19:28.836102 ==
7763 11:19:28.838815 Dram Type= 6, Freq= 0, CH_0, rank 0
7764 11:19:28.845517 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7765 11:19:28.845638 ==
7766 11:19:28.845703 RX Vref Scan: 1
7767 11:19:28.845765
7768 11:19:28.848541 Set Vref Range= 24 -> 127
7769 11:19:28.848624
7770 11:19:28.851848 RX Vref 24 -> 127, step: 1
7771 11:19:28.851934
7772 11:19:28.855415 RX Delay 11 -> 252, step: 4
7773 11:19:28.855500
7774 11:19:28.858355 Set Vref, RX VrefLevel [Byte0]: 24
7775 11:19:28.861789 [Byte1]: 24
7776 11:19:28.861873
7777 11:19:28.865341 Set Vref, RX VrefLevel [Byte0]: 25
7778 11:19:28.868312 [Byte1]: 25
7779 11:19:28.868397
7780 11:19:28.871751 Set Vref, RX VrefLevel [Byte0]: 26
7781 11:19:28.874852 [Byte1]: 26
7782 11:19:28.878504
7783 11:19:28.878589 Set Vref, RX VrefLevel [Byte0]: 27
7784 11:19:28.882090 [Byte1]: 27
7785 11:19:28.885965
7786 11:19:28.886049 Set Vref, RX VrefLevel [Byte0]: 28
7787 11:19:28.889489 [Byte1]: 28
7788 11:19:28.893524
7789 11:19:28.893611 Set Vref, RX VrefLevel [Byte0]: 29
7790 11:19:28.897028 [Byte1]: 29
7791 11:19:28.901047
7792 11:19:28.901133 Set Vref, RX VrefLevel [Byte0]: 30
7793 11:19:28.904510 [Byte1]: 30
7794 11:19:28.908572
7795 11:19:28.908677 Set Vref, RX VrefLevel [Byte0]: 31
7796 11:19:28.911847 [Byte1]: 31
7797 11:19:28.916229
7798 11:19:28.916310 Set Vref, RX VrefLevel [Byte0]: 32
7799 11:19:28.919884 [Byte1]: 32
7800 11:19:28.923882
7801 11:19:28.924003 Set Vref, RX VrefLevel [Byte0]: 33
7802 11:19:28.927214 [Byte1]: 33
7803 11:19:28.931606
7804 11:19:28.931696 Set Vref, RX VrefLevel [Byte0]: 34
7805 11:19:28.935144 [Byte1]: 34
7806 11:19:28.939172
7807 11:19:28.939250 Set Vref, RX VrefLevel [Byte0]: 35
7808 11:19:28.942897 [Byte1]: 35
7809 11:19:28.947097
7810 11:19:28.947219 Set Vref, RX VrefLevel [Byte0]: 36
7811 11:19:28.950222 [Byte1]: 36
7812 11:19:28.954481
7813 11:19:28.954601 Set Vref, RX VrefLevel [Byte0]: 37
7814 11:19:28.957724 [Byte1]: 37
7815 11:19:28.961718
7816 11:19:28.961829 Set Vref, RX VrefLevel [Byte0]: 38
7817 11:19:28.965025 [Byte1]: 38
7818 11:19:28.969871
7819 11:19:28.969955 Set Vref, RX VrefLevel [Byte0]: 39
7820 11:19:28.972627 [Byte1]: 39
7821 11:19:28.977377
7822 11:19:28.977463 Set Vref, RX VrefLevel [Byte0]: 40
7823 11:19:28.980304 [Byte1]: 40
7824 11:19:28.984980
7825 11:19:28.985083 Set Vref, RX VrefLevel [Byte0]: 41
7826 11:19:28.987962 [Byte1]: 41
7827 11:19:28.992761
7828 11:19:28.992845 Set Vref, RX VrefLevel [Byte0]: 42
7829 11:19:28.995643 [Byte1]: 42
7830 11:19:29.000199
7831 11:19:29.000282 Set Vref, RX VrefLevel [Byte0]: 43
7832 11:19:29.003092 [Byte1]: 43
7833 11:19:29.007876
7834 11:19:29.007986 Set Vref, RX VrefLevel [Byte0]: 44
7835 11:19:29.010793 [Byte1]: 44
7836 11:19:29.015433
7837 11:19:29.015536 Set Vref, RX VrefLevel [Byte0]: 45
7838 11:19:29.018331 [Byte1]: 45
7839 11:19:29.022871
7840 11:19:29.022960 Set Vref, RX VrefLevel [Byte0]: 46
7841 11:19:29.026439 [Byte1]: 46
7842 11:19:29.030631
7843 11:19:29.030745 Set Vref, RX VrefLevel [Byte0]: 47
7844 11:19:29.033503 [Byte1]: 47
7845 11:19:29.038267
7846 11:19:29.038352 Set Vref, RX VrefLevel [Byte0]: 48
7847 11:19:29.041669 [Byte1]: 48
7848 11:19:29.046069
7849 11:19:29.046154 Set Vref, RX VrefLevel [Byte0]: 49
7850 11:19:29.049224 [Byte1]: 49
7851 11:19:29.054001
7852 11:19:29.054113 Set Vref, RX VrefLevel [Byte0]: 50
7853 11:19:29.056462 [Byte1]: 50
7854 11:19:29.061013
7855 11:19:29.061094 Set Vref, RX VrefLevel [Byte0]: 51
7856 11:19:29.064161 [Byte1]: 51
7857 11:19:29.068642
7858 11:19:29.068726 Set Vref, RX VrefLevel [Byte0]: 52
7859 11:19:29.072558 [Byte1]: 52
7860 11:19:29.076291
7861 11:19:29.076376 Set Vref, RX VrefLevel [Byte0]: 53
7862 11:19:29.079848 [Byte1]: 53
7863 11:19:29.083870
7864 11:19:29.083954 Set Vref, RX VrefLevel [Byte0]: 54
7865 11:19:29.087594 [Byte1]: 54
7866 11:19:29.091461
7867 11:19:29.091546 Set Vref, RX VrefLevel [Byte0]: 55
7868 11:19:29.094643 [Byte1]: 55
7869 11:19:29.099273
7870 11:19:29.099357 Set Vref, RX VrefLevel [Byte0]: 56
7871 11:19:29.102241 [Byte1]: 56
7872 11:19:29.106704
7873 11:19:29.106788 Set Vref, RX VrefLevel [Byte0]: 57
7874 11:19:29.110312 [Byte1]: 57
7875 11:19:29.114387
7876 11:19:29.114471 Set Vref, RX VrefLevel [Byte0]: 58
7877 11:19:29.117365 [Byte1]: 58
7878 11:19:29.122137
7879 11:19:29.122222 Set Vref, RX VrefLevel [Byte0]: 59
7880 11:19:29.125260 [Byte1]: 59
7881 11:19:29.129560
7882 11:19:29.129645 Set Vref, RX VrefLevel [Byte0]: 60
7883 11:19:29.132914 [Byte1]: 60
7884 11:19:29.136789
7885 11:19:29.136911 Set Vref, RX VrefLevel [Byte0]: 61
7886 11:19:29.140129 [Byte1]: 61
7887 11:19:29.144902
7888 11:19:29.145014 Set Vref, RX VrefLevel [Byte0]: 62
7889 11:19:29.147877 [Byte1]: 62
7890 11:19:29.152306
7891 11:19:29.152417 Set Vref, RX VrefLevel [Byte0]: 63
7892 11:19:29.155276 [Byte1]: 63
7893 11:19:29.159685
7894 11:19:29.159792 Set Vref, RX VrefLevel [Byte0]: 64
7895 11:19:29.162938 [Byte1]: 64
7896 11:19:29.167632
7897 11:19:29.167738 Set Vref, RX VrefLevel [Byte0]: 65
7898 11:19:29.171017 [Byte1]: 65
7899 11:19:29.174808
7900 11:19:29.174942 Set Vref, RX VrefLevel [Byte0]: 66
7901 11:19:29.178771 [Byte1]: 66
7902 11:19:29.182601
7903 11:19:29.182710 Set Vref, RX VrefLevel [Byte0]: 67
7904 11:19:29.186151 [Byte1]: 67
7905 11:19:29.190196
7906 11:19:29.190272 Set Vref, RX VrefLevel [Byte0]: 68
7907 11:19:29.193842 [Byte1]: 68
7908 11:19:29.197978
7909 11:19:29.198060 Set Vref, RX VrefLevel [Byte0]: 69
7910 11:19:29.201401 [Byte1]: 69
7911 11:19:29.205587
7912 11:19:29.205664 Set Vref, RX VrefLevel [Byte0]: 70
7913 11:19:29.209150 [Byte1]: 70
7914 11:19:29.212955
7915 11:19:29.213058 Set Vref, RX VrefLevel [Byte0]: 71
7916 11:19:29.216492 [Byte1]: 71
7917 11:19:29.220841
7918 11:19:29.220969 Set Vref, RX VrefLevel [Byte0]: 72
7919 11:19:29.224284 [Byte1]: 72
7920 11:19:29.228690
7921 11:19:29.228784 Set Vref, RX VrefLevel [Byte0]: 73
7922 11:19:29.231715 [Byte1]: 73
7923 11:19:29.236046
7924 11:19:29.236123 Set Vref, RX VrefLevel [Byte0]: 74
7925 11:19:29.239349 [Byte1]: 74
7926 11:19:29.243592
7927 11:19:29.243671 Set Vref, RX VrefLevel [Byte0]: 75
7928 11:19:29.246817 [Byte1]: 75
7929 11:19:29.251283
7930 11:19:29.251364 Set Vref, RX VrefLevel [Byte0]: 76
7931 11:19:29.254586 [Byte1]: 76
7932 11:19:29.258892
7933 11:19:29.259021 Final RX Vref Byte 0 = 64 to rank0
7934 11:19:29.262283 Final RX Vref Byte 1 = 60 to rank0
7935 11:19:29.265496 Final RX Vref Byte 0 = 64 to rank1
7936 11:19:29.268711 Final RX Vref Byte 1 = 60 to rank1==
7937 11:19:29.271917 Dram Type= 6, Freq= 0, CH_0, rank 0
7938 11:19:29.278532 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7939 11:19:29.278620 ==
7940 11:19:29.278688 DQS Delay:
7941 11:19:29.282019 DQS0 = 0, DQS1 = 0
7942 11:19:29.282105 DQM Delay:
7943 11:19:29.282173 DQM0 = 126, DQM1 = 119
7944 11:19:29.285216 DQ Delay:
7945 11:19:29.288647 DQ0 =126, DQ1 =126, DQ2 =126, DQ3 =122
7946 11:19:29.291519 DQ4 =126, DQ5 =114, DQ6 =134, DQ7 =138
7947 11:19:29.295125 DQ8 =112, DQ9 =106, DQ10 =120, DQ11 =114
7948 11:19:29.298707 DQ12 =124, DQ13 =124, DQ14 =130, DQ15 =128
7949 11:19:29.298793
7950 11:19:29.298870
7951 11:19:29.298934
7952 11:19:29.301669 [DramC_TX_OE_Calibration] TA2
7953 11:19:29.305156 Original DQ_B0 (3 6) =30, OEN = 27
7954 11:19:29.308211 Original DQ_B1 (3 6) =30, OEN = 27
7955 11:19:29.311473 24, 0x0, End_B0=24 End_B1=24
7956 11:19:29.314748 25, 0x0, End_B0=25 End_B1=25
7957 11:19:29.314871 26, 0x0, End_B0=26 End_B1=26
7958 11:19:29.318388 27, 0x0, End_B0=27 End_B1=27
7959 11:19:29.321306 28, 0x0, End_B0=28 End_B1=28
7960 11:19:29.324864 29, 0x0, End_B0=29 End_B1=29
7961 11:19:29.324951 30, 0x0, End_B0=30 End_B1=30
7962 11:19:29.328294 31, 0x4141, End_B0=30 End_B1=30
7963 11:19:29.331673 Byte0 end_step=30 best_step=27
7964 11:19:29.334768 Byte1 end_step=30 best_step=27
7965 11:19:29.338118 Byte0 TX OE(2T, 0.5T) = (3, 3)
7966 11:19:29.341107 Byte1 TX OE(2T, 0.5T) = (3, 3)
7967 11:19:29.341197
7968 11:19:29.341264
7969 11:19:29.347762 [DQSOSCAuto] RK0, (LSB)MR18= 0x1414, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 399 ps
7970 11:19:29.351163 CH0 RK0: MR19=303, MR18=1414
7971 11:19:29.357850 CH0_RK0: MR19=0x303, MR18=0x1414, DQSOSC=399, MR23=63, INC=23, DEC=15
7972 11:19:29.357962
7973 11:19:29.361353 ----->DramcWriteLeveling(PI) begin...
7974 11:19:29.361437 ==
7975 11:19:29.364494 Dram Type= 6, Freq= 0, CH_0, rank 1
7976 11:19:29.367571 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7977 11:19:29.367655 ==
7978 11:19:29.370897 Write leveling (Byte 0): 34 => 34
7979 11:19:29.374245 Write leveling (Byte 1): 27 => 27
7980 11:19:29.377612 DramcWriteLeveling(PI) end<-----
7981 11:19:29.377722
7982 11:19:29.377818 ==
7983 11:19:29.381159 Dram Type= 6, Freq= 0, CH_0, rank 1
7984 11:19:29.384178 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7985 11:19:29.387487 ==
7986 11:19:29.387593 [Gating] SW mode calibration
7987 11:19:29.397142 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7988 11:19:29.400699 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7989 11:19:29.404264 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7990 11:19:29.410791 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7991 11:19:29.413665 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7992 11:19:29.416875 1 4 12 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
7993 11:19:29.423997 1 4 16 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
7994 11:19:29.426818 1 4 20 | B1->B0 | 3131 3434 | 0 1 | (0 0) (1 1)
7995 11:19:29.430273 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7996 11:19:29.437186 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7997 11:19:29.440125 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7998 11:19:29.443581 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7999 11:19:29.449970 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8000 11:19:29.453476 1 5 12 | B1->B0 | 3434 2828 | 1 0 | (1 1) (0 0)
8001 11:19:29.456347 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8002 11:19:29.463510 1 5 20 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
8003 11:19:29.466734 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8004 11:19:29.470221 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8005 11:19:29.476418 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8006 11:19:29.479753 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8007 11:19:29.482983 1 6 8 | B1->B0 | 2323 2929 | 0 1 | (0 0) (0 0)
8008 11:19:29.489437 1 6 12 | B1->B0 | 2323 4242 | 0 1 | (0 0) (0 0)
8009 11:19:29.492556 1 6 16 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
8010 11:19:29.496626 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
8011 11:19:29.503000 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8012 11:19:29.506362 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8013 11:19:29.509136 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8014 11:19:29.515802 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8015 11:19:29.519057 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8016 11:19:29.522599 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8017 11:19:29.529536 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8018 11:19:29.532199 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8019 11:19:29.535914 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8020 11:19:29.542059 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8021 11:19:29.545772 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8022 11:19:29.549076 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8023 11:19:29.555470 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8024 11:19:29.558515 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8025 11:19:29.561903 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8026 11:19:29.568821 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8027 11:19:29.571633 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8028 11:19:29.574999 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8029 11:19:29.581886 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8030 11:19:29.585213 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8031 11:19:29.588689 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8032 11:19:29.594970 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8033 11:19:29.598559 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8034 11:19:29.601450 Total UI for P1: 0, mck2ui 16
8035 11:19:29.604788 best dqsien dly found for B0: ( 1, 9, 10)
8036 11:19:29.608062 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8037 11:19:29.614794 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8038 11:19:29.617782 Total UI for P1: 0, mck2ui 16
8039 11:19:29.621286 best dqsien dly found for B1: ( 1, 9, 18)
8040 11:19:29.624718 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8041 11:19:29.628129 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8042 11:19:29.628207
8043 11:19:29.631299 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8044 11:19:29.634754 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8045 11:19:29.637500 [Gating] SW calibration Done
8046 11:19:29.637576 ==
8047 11:19:29.640997 Dram Type= 6, Freq= 0, CH_0, rank 1
8048 11:19:29.644283 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8049 11:19:29.647459 ==
8050 11:19:29.647542 RX Vref Scan: 0
8051 11:19:29.647621
8052 11:19:29.650777 RX Vref 0 -> 0, step: 1
8053 11:19:29.650901
8054 11:19:29.651035 RX Delay 0 -> 252, step: 8
8055 11:19:29.657230 iDelay=200, Bit 0, Center 127 (72 ~ 183) 112
8056 11:19:29.660806 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8057 11:19:29.664310 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8058 11:19:29.667695 iDelay=200, Bit 3, Center 123 (64 ~ 183) 120
8059 11:19:29.670860 iDelay=200, Bit 4, Center 127 (72 ~ 183) 112
8060 11:19:29.677443 iDelay=200, Bit 5, Center 115 (56 ~ 175) 120
8061 11:19:29.680680 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8062 11:19:29.683997 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8063 11:19:29.687333 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8064 11:19:29.693522 iDelay=200, Bit 9, Center 107 (48 ~ 167) 120
8065 11:19:29.696821 iDelay=200, Bit 10, Center 123 (64 ~ 183) 120
8066 11:19:29.700255 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8067 11:19:29.703553 iDelay=200, Bit 12, Center 127 (64 ~ 191) 128
8068 11:19:29.707267 iDelay=200, Bit 13, Center 127 (64 ~ 191) 128
8069 11:19:29.713681 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8070 11:19:29.716852 iDelay=200, Bit 15, Center 127 (64 ~ 191) 128
8071 11:19:29.716935 ==
8072 11:19:29.720294 Dram Type= 6, Freq= 0, CH_0, rank 1
8073 11:19:29.723664 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8074 11:19:29.723747 ==
8075 11:19:29.726510 DQS Delay:
8076 11:19:29.726629 DQS0 = 0, DQS1 = 0
8077 11:19:29.726695 DQM Delay:
8078 11:19:29.729942 DQM0 = 128, DQM1 = 121
8079 11:19:29.730025 DQ Delay:
8080 11:19:29.733491 DQ0 =127, DQ1 =127, DQ2 =127, DQ3 =123
8081 11:19:29.736337 DQ4 =127, DQ5 =115, DQ6 =139, DQ7 =139
8082 11:19:29.743155 DQ8 =111, DQ9 =107, DQ10 =123, DQ11 =115
8083 11:19:29.746771 DQ12 =127, DQ13 =127, DQ14 =131, DQ15 =127
8084 11:19:29.746914
8085 11:19:29.746980
8086 11:19:29.747053 ==
8087 11:19:29.749480 Dram Type= 6, Freq= 0, CH_0, rank 1
8088 11:19:29.753087 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8089 11:19:29.753172 ==
8090 11:19:29.753254
8091 11:19:29.753318
8092 11:19:29.756687 TX Vref Scan disable
8093 11:19:29.759673 == TX Byte 0 ==
8094 11:19:29.763176 Update DQ dly =990 (3 ,6, 30) DQ OEN =(3 ,3)
8095 11:19:29.766004 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8096 11:19:29.769382 == TX Byte 1 ==
8097 11:19:29.772810 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8098 11:19:29.776253 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8099 11:19:29.776342 ==
8100 11:19:29.779283 Dram Type= 6, Freq= 0, CH_0, rank 1
8101 11:19:29.782650 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8102 11:19:29.785907 ==
8103 11:19:29.799110
8104 11:19:29.802581 TX Vref early break, caculate TX vref
8105 11:19:29.806046 TX Vref=16, minBit 10, minWin=21, winSum=364
8106 11:19:29.808978 TX Vref=18, minBit 0, minWin=22, winSum=373
8107 11:19:29.812807 TX Vref=20, minBit 8, minWin=22, winSum=381
8108 11:19:29.815424 TX Vref=22, minBit 8, minWin=22, winSum=389
8109 11:19:29.818704 TX Vref=24, minBit 0, minWin=24, winSum=399
8110 11:19:29.825489 TX Vref=26, minBit 8, minWin=24, winSum=402
8111 11:19:29.828850 TX Vref=28, minBit 8, minWin=24, winSum=406
8112 11:19:29.832569 TX Vref=30, minBit 8, minWin=24, winSum=408
8113 11:19:29.835673 TX Vref=32, minBit 8, minWin=23, winSum=394
8114 11:19:29.838648 TX Vref=34, minBit 8, minWin=22, winSum=388
8115 11:19:29.845083 TX Vref=36, minBit 8, minWin=22, winSum=380
8116 11:19:29.848516 [TxChooseVref] Worse bit 8, Min win 24, Win sum 408, Final Vref 30
8117 11:19:29.848595
8118 11:19:29.851872 Final TX Range 0 Vref 30
8119 11:19:29.851982
8120 11:19:29.852082 ==
8121 11:19:29.855318 Dram Type= 6, Freq= 0, CH_0, rank 1
8122 11:19:29.858295 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8123 11:19:29.861999 ==
8124 11:19:29.862097
8125 11:19:29.862201
8126 11:19:29.862309 TX Vref Scan disable
8127 11:19:29.868886 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8128 11:19:29.868979 == TX Byte 0 ==
8129 11:19:29.871770 u2DelayCellOfst[0]=15 cells (4 PI)
8130 11:19:29.875109 u2DelayCellOfst[1]=18 cells (5 PI)
8131 11:19:29.878531 u2DelayCellOfst[2]=11 cells (3 PI)
8132 11:19:29.881450 u2DelayCellOfst[3]=11 cells (3 PI)
8133 11:19:29.884962 u2DelayCellOfst[4]=7 cells (2 PI)
8134 11:19:29.888644 u2DelayCellOfst[5]=0 cells (0 PI)
8135 11:19:29.891344 u2DelayCellOfst[6]=18 cells (5 PI)
8136 11:19:29.894777 u2DelayCellOfst[7]=18 cells (5 PI)
8137 11:19:29.898159 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8138 11:19:29.901309 Update DQM dly =990 (3 ,6, 30) DQM OEN =(3 ,3)
8139 11:19:29.904873 == TX Byte 1 ==
8140 11:19:29.908195 u2DelayCellOfst[8]=0 cells (0 PI)
8141 11:19:29.911233 u2DelayCellOfst[9]=3 cells (1 PI)
8142 11:19:29.914757 u2DelayCellOfst[10]=11 cells (3 PI)
8143 11:19:29.917615 u2DelayCellOfst[11]=7 cells (2 PI)
8144 11:19:29.920963 u2DelayCellOfst[12]=15 cells (4 PI)
8145 11:19:29.925102 u2DelayCellOfst[13]=11 cells (3 PI)
8146 11:19:29.927777 u2DelayCellOfst[14]=15 cells (4 PI)
8147 11:19:29.930859 u2DelayCellOfst[15]=15 cells (4 PI)
8148 11:19:29.934698 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8149 11:19:29.937661 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8150 11:19:29.941097 DramC Write-DBI on
8151 11:19:29.941182 ==
8152 11:19:29.944360 Dram Type= 6, Freq= 0, CH_0, rank 1
8153 11:19:29.947836 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8154 11:19:29.947949 ==
8155 11:19:29.948033
8156 11:19:29.948096
8157 11:19:29.950686 TX Vref Scan disable
8158 11:19:29.954209 == TX Byte 0 ==
8159 11:19:29.957629 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8160 11:19:29.957713 == TX Byte 1 ==
8161 11:19:29.964202 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8162 11:19:29.964286 DramC Write-DBI off
8163 11:19:29.964351
8164 11:19:29.964411 [DATLAT]
8165 11:19:29.967299 Freq=1600, CH0 RK1
8166 11:19:29.967381
8167 11:19:29.970676 DATLAT Default: 0xf
8168 11:19:29.970785 0, 0xFFFF, sum = 0
8169 11:19:29.973538 1, 0xFFFF, sum = 0
8170 11:19:29.973661 2, 0xFFFF, sum = 0
8171 11:19:29.977021 3, 0xFFFF, sum = 0
8172 11:19:29.977105 4, 0xFFFF, sum = 0
8173 11:19:29.980355 5, 0xFFFF, sum = 0
8174 11:19:29.980477 6, 0xFFFF, sum = 0
8175 11:19:29.984003 7, 0xFFFF, sum = 0
8176 11:19:29.984086 8, 0xFFFF, sum = 0
8177 11:19:29.986784 9, 0xFFFF, sum = 0
8178 11:19:29.986916 10, 0xFFFF, sum = 0
8179 11:19:29.990344 11, 0xFFFF, sum = 0
8180 11:19:29.990461 12, 0xFFFF, sum = 0
8181 11:19:29.994001 13, 0xCFFF, sum = 0
8182 11:19:29.994085 14, 0x0, sum = 1
8183 11:19:29.996621 15, 0x0, sum = 2
8184 11:19:29.996735 16, 0x0, sum = 3
8185 11:19:30.000117 17, 0x0, sum = 4
8186 11:19:30.000201 best_step = 15
8187 11:19:30.000265
8188 11:19:30.000326 ==
8189 11:19:30.003504 Dram Type= 6, Freq= 0, CH_0, rank 1
8190 11:19:30.010206 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8191 11:19:30.010291 ==
8192 11:19:30.010356 RX Vref Scan: 0
8193 11:19:30.010417
8194 11:19:30.013425 RX Vref 0 -> 0, step: 1
8195 11:19:30.013555
8196 11:19:30.016505 RX Delay 3 -> 252, step: 4
8197 11:19:30.020012 iDelay=191, Bit 0, Center 124 (71 ~ 178) 108
8198 11:19:30.023401 iDelay=191, Bit 1, Center 124 (71 ~ 178) 108
8199 11:19:30.030079 iDelay=191, Bit 2, Center 122 (71 ~ 174) 104
8200 11:19:30.033362 iDelay=191, Bit 3, Center 122 (67 ~ 178) 112
8201 11:19:30.036552 iDelay=191, Bit 4, Center 124 (71 ~ 178) 108
8202 11:19:30.039473 iDelay=191, Bit 5, Center 112 (59 ~ 166) 108
8203 11:19:30.042864 iDelay=191, Bit 6, Center 134 (79 ~ 190) 112
8204 11:19:30.049475 iDelay=191, Bit 7, Center 134 (79 ~ 190) 112
8205 11:19:30.052932 iDelay=191, Bit 8, Center 110 (51 ~ 170) 120
8206 11:19:30.055918 iDelay=191, Bit 9, Center 104 (47 ~ 162) 116
8207 11:19:30.059374 iDelay=191, Bit 10, Center 120 (63 ~ 178) 116
8208 11:19:30.062738 iDelay=191, Bit 11, Center 112 (55 ~ 170) 116
8209 11:19:30.069239 iDelay=191, Bit 12, Center 124 (67 ~ 182) 116
8210 11:19:30.072786 iDelay=191, Bit 13, Center 122 (67 ~ 178) 112
8211 11:19:30.075647 iDelay=191, Bit 14, Center 126 (67 ~ 186) 120
8212 11:19:30.079233 iDelay=191, Bit 15, Center 124 (67 ~ 182) 116
8213 11:19:30.082675 ==
8214 11:19:30.085435 Dram Type= 6, Freq= 0, CH_0, rank 1
8215 11:19:30.088877 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8216 11:19:30.089010 ==
8217 11:19:30.089106 DQS Delay:
8218 11:19:30.092500 DQS0 = 0, DQS1 = 0
8219 11:19:30.092619 DQM Delay:
8220 11:19:30.095386 DQM0 = 124, DQM1 = 117
8221 11:19:30.095507 DQ Delay:
8222 11:19:30.098825 DQ0 =124, DQ1 =124, DQ2 =122, DQ3 =122
8223 11:19:30.102300 DQ4 =124, DQ5 =112, DQ6 =134, DQ7 =134
8224 11:19:30.105866 DQ8 =110, DQ9 =104, DQ10 =120, DQ11 =112
8225 11:19:30.108983 DQ12 =124, DQ13 =122, DQ14 =126, DQ15 =124
8226 11:19:30.109065
8227 11:19:30.109131
8228 11:19:30.109190
8229 11:19:30.111856 [DramC_TX_OE_Calibration] TA2
8230 11:19:30.115376 Original DQ_B0 (3 6) =30, OEN = 27
8231 11:19:30.118668 Original DQ_B1 (3 6) =30, OEN = 27
8232 11:19:30.121826 24, 0x0, End_B0=24 End_B1=24
8233 11:19:30.125410 25, 0x0, End_B0=25 End_B1=25
8234 11:19:30.125495 26, 0x0, End_B0=26 End_B1=26
8235 11:19:30.128420 27, 0x0, End_B0=27 End_B1=27
8236 11:19:30.131750 28, 0x0, End_B0=28 End_B1=28
8237 11:19:30.134915 29, 0x0, End_B0=29 End_B1=29
8238 11:19:30.138377 30, 0x0, End_B0=30 End_B1=30
8239 11:19:30.138463 31, 0x4141, End_B0=30 End_B1=30
8240 11:19:30.141772 Byte0 end_step=30 best_step=27
8241 11:19:30.145076 Byte1 end_step=30 best_step=27
8242 11:19:30.148515 Byte0 TX OE(2T, 0.5T) = (3, 3)
8243 11:19:30.151860 Byte1 TX OE(2T, 0.5T) = (3, 3)
8244 11:19:30.151944
8245 11:19:30.152009
8246 11:19:30.158053 [DQSOSCAuto] RK1, (LSB)MR18= 0x210d, (MSB)MR19= 0x303, tDQSOscB0 = 403 ps tDQSOscB1 = 393 ps
8247 11:19:30.161325 CH0 RK1: MR19=303, MR18=210D
8248 11:19:30.168286 CH0_RK1: MR19=0x303, MR18=0x210D, DQSOSC=393, MR23=63, INC=23, DEC=15
8249 11:19:30.171165 [RxdqsGatingPostProcess] freq 1600
8250 11:19:30.178206 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8251 11:19:30.181354 best DQS0 dly(2T, 0.5T) = (1, 1)
8252 11:19:30.184551 best DQS1 dly(2T, 0.5T) = (1, 1)
8253 11:19:30.184652 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8254 11:19:30.187818 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8255 11:19:30.191222 best DQS0 dly(2T, 0.5T) = (1, 1)
8256 11:19:30.194408 best DQS1 dly(2T, 0.5T) = (1, 1)
8257 11:19:30.197807 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8258 11:19:30.201175 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8259 11:19:30.204510 Pre-setting of DQS Precalculation
8260 11:19:30.210959 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8261 11:19:30.211060 ==
8262 11:19:30.213903 Dram Type= 6, Freq= 0, CH_1, rank 0
8263 11:19:30.217855 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8264 11:19:30.217956 ==
8265 11:19:30.224038 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8266 11:19:30.227497 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8267 11:19:30.230655 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8268 11:19:30.237332 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8269 11:19:30.245843 [CA 0] Center 42 (13~71) winsize 59
8270 11:19:30.249366 [CA 1] Center 42 (13~72) winsize 60
8271 11:19:30.252508 [CA 2] Center 37 (9~66) winsize 58
8272 11:19:30.255693 [CA 3] Center 36 (7~66) winsize 60
8273 11:19:30.259043 [CA 4] Center 37 (8~67) winsize 60
8274 11:19:30.262334 [CA 5] Center 36 (7~66) winsize 60
8275 11:19:30.262473
8276 11:19:30.265568 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8277 11:19:30.265652
8278 11:19:30.269260 [CATrainingPosCal] consider 1 rank data
8279 11:19:30.272617 u2DelayCellTimex100 = 258/100 ps
8280 11:19:30.275508 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8281 11:19:30.282096 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8282 11:19:30.285530 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8283 11:19:30.289155 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8284 11:19:30.292415 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8285 11:19:30.295323 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8286 11:19:30.295407
8287 11:19:30.299073 CA PerBit enable=1, Macro0, CA PI delay=36
8288 11:19:30.299157
8289 11:19:30.301883 [CBTSetCACLKResult] CA Dly = 36
8290 11:19:30.305414 CS Dly: 10 (0~41)
8291 11:19:30.308820 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8292 11:19:30.311788 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8293 11:19:30.311871 ==
8294 11:19:30.315241 Dram Type= 6, Freq= 0, CH_1, rank 1
8295 11:19:30.321756 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8296 11:19:30.321842 ==
8297 11:19:30.325129 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8298 11:19:30.331653 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8299 11:19:30.335124 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8300 11:19:30.341135 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8301 11:19:30.348984 [CA 0] Center 41 (12~71) winsize 60
8302 11:19:30.352679 [CA 1] Center 42 (12~72) winsize 61
8303 11:19:30.355414 [CA 2] Center 37 (8~67) winsize 60
8304 11:19:30.358783 [CA 3] Center 36 (7~66) winsize 60
8305 11:19:30.362391 [CA 4] Center 37 (7~67) winsize 61
8306 11:19:30.365850 [CA 5] Center 36 (6~66) winsize 61
8307 11:19:30.365976
8308 11:19:30.368522 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8309 11:19:30.368604
8310 11:19:30.375564 [CATrainingPosCal] consider 2 rank data
8311 11:19:30.375648 u2DelayCellTimex100 = 258/100 ps
8312 11:19:30.382077 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8313 11:19:30.385370 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8314 11:19:30.388775 CA2 delay=37 (9~66),Diff = 1 PI (3 cell)
8315 11:19:30.391738 CA3 delay=36 (7~66),Diff = 0 PI (0 cell)
8316 11:19:30.395205 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8317 11:19:30.398459 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8318 11:19:30.398542
8319 11:19:30.401968 CA PerBit enable=1, Macro0, CA PI delay=36
8320 11:19:30.402050
8321 11:19:30.405018 [CBTSetCACLKResult] CA Dly = 36
8322 11:19:30.408555 CS Dly: 11 (0~43)
8323 11:19:30.411323 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8324 11:19:30.414803 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8325 11:19:30.414933
8326 11:19:30.418374 ----->DramcWriteLeveling(PI) begin...
8327 11:19:30.418458 ==
8328 11:19:30.421451 Dram Type= 6, Freq= 0, CH_1, rank 0
8329 11:19:30.428305 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8330 11:19:30.428404 ==
8331 11:19:30.431372 Write leveling (Byte 0): 24 => 24
8332 11:19:30.435038 Write leveling (Byte 1): 28 => 28
8333 11:19:30.435134 DramcWriteLeveling(PI) end<-----
8334 11:19:30.438087
8335 11:19:30.438170 ==
8336 11:19:30.441424 Dram Type= 6, Freq= 0, CH_1, rank 0
8337 11:19:30.444684 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8338 11:19:30.444800 ==
8339 11:19:30.447861 [Gating] SW mode calibration
8340 11:19:30.454596 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8341 11:19:30.458019 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8342 11:19:30.464388 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8343 11:19:30.467864 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8344 11:19:30.474089 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8345 11:19:30.477299 1 4 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8346 11:19:30.480994 1 4 16 | B1->B0 | 3333 3333 | 1 0 | (1 1) (1 1)
8347 11:19:30.487710 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8348 11:19:30.490532 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8349 11:19:30.494071 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8350 11:19:30.500327 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8351 11:19:30.503825 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8352 11:19:30.507319 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8353 11:19:30.513664 1 5 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8354 11:19:30.516956 1 5 16 | B1->B0 | 2c2c 2626 | 1 0 | (1 1) (0 1)
8355 11:19:30.520444 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8356 11:19:30.526981 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8357 11:19:30.530019 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8358 11:19:30.533482 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8359 11:19:30.539564 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8360 11:19:30.542987 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8361 11:19:30.546706 1 6 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8362 11:19:30.552926 1 6 16 | B1->B0 | 4343 4444 | 0 0 | (0 0) (0 0)
8363 11:19:30.556570 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8364 11:19:30.559667 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8365 11:19:30.566410 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8366 11:19:30.569210 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8367 11:19:30.572749 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8368 11:19:30.579550 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8369 11:19:30.582797 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8370 11:19:30.586107 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8371 11:19:30.592610 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8372 11:19:30.595802 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8373 11:19:30.599269 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8374 11:19:30.605678 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8375 11:19:30.609068 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8376 11:19:30.611954 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8377 11:19:30.618998 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8378 11:19:30.622424 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8379 11:19:30.625366 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8380 11:19:30.631814 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8381 11:19:30.635274 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8382 11:19:30.638776 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8383 11:19:30.645070 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8384 11:19:30.648548 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8385 11:19:30.651724 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8386 11:19:30.658343 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8387 11:19:30.661454 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8388 11:19:30.665319 Total UI for P1: 0, mck2ui 16
8389 11:19:30.668218 best dqsien dly found for B0: ( 1, 9, 14)
8390 11:19:30.671342 Total UI for P1: 0, mck2ui 16
8391 11:19:30.674660 best dqsien dly found for B1: ( 1, 9, 16)
8392 11:19:30.678031 best DQS0 dly(MCK, UI, PI) = (1, 9, 14)
8393 11:19:30.681502 best DQS1 dly(MCK, UI, PI) = (1, 9, 16)
8394 11:19:30.681611
8395 11:19:30.684371 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 14)
8396 11:19:30.687724 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 16)
8397 11:19:30.690849 [Gating] SW calibration Done
8398 11:19:30.690961 ==
8399 11:19:30.694159 Dram Type= 6, Freq= 0, CH_1, rank 0
8400 11:19:30.700950 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8401 11:19:30.701065 ==
8402 11:19:30.701164 RX Vref Scan: 0
8403 11:19:30.701260
8404 11:19:30.704399 RX Vref 0 -> 0, step: 1
8405 11:19:30.704509
8406 11:19:30.707767 RX Delay 0 -> 252, step: 8
8407 11:19:30.710579 iDelay=208, Bit 0, Center 135 (80 ~ 191) 112
8408 11:19:30.714103 iDelay=208, Bit 1, Center 123 (64 ~ 183) 120
8409 11:19:30.717742 iDelay=208, Bit 2, Center 119 (64 ~ 175) 112
8410 11:19:30.720697 iDelay=208, Bit 3, Center 131 (72 ~ 191) 120
8411 11:19:30.727722 iDelay=208, Bit 4, Center 127 (72 ~ 183) 112
8412 11:19:30.730680 iDelay=208, Bit 5, Center 147 (88 ~ 207) 120
8413 11:19:30.734146 iDelay=208, Bit 6, Center 143 (88 ~ 199) 112
8414 11:19:30.737208 iDelay=208, Bit 7, Center 127 (72 ~ 183) 112
8415 11:19:30.740740 iDelay=208, Bit 8, Center 111 (56 ~ 167) 112
8416 11:19:30.747210 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
8417 11:19:30.750638 iDelay=208, Bit 10, Center 123 (72 ~ 175) 104
8418 11:19:30.753775 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
8419 11:19:30.757125 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8420 11:19:30.763790 iDelay=208, Bit 13, Center 131 (72 ~ 191) 120
8421 11:19:30.766760 iDelay=208, Bit 14, Center 131 (80 ~ 183) 104
8422 11:19:30.770119 iDelay=208, Bit 15, Center 135 (80 ~ 191) 112
8423 11:19:30.770231 ==
8424 11:19:30.773524 Dram Type= 6, Freq= 0, CH_1, rank 0
8425 11:19:30.777027 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8426 11:19:30.780134 ==
8427 11:19:30.780241 DQS Delay:
8428 11:19:30.780337 DQS0 = 0, DQS1 = 0
8429 11:19:30.783372 DQM Delay:
8430 11:19:30.783484 DQM0 = 131, DQM1 = 125
8431 11:19:30.786722 DQ Delay:
8432 11:19:30.789633 DQ0 =135, DQ1 =123, DQ2 =119, DQ3 =131
8433 11:19:30.793049 DQ4 =127, DQ5 =147, DQ6 =143, DQ7 =127
8434 11:19:30.796403 DQ8 =111, DQ9 =115, DQ10 =123, DQ11 =119
8435 11:19:30.799334 DQ12 =135, DQ13 =131, DQ14 =131, DQ15 =135
8436 11:19:30.799444
8437 11:19:30.799538
8438 11:19:30.799631 ==
8439 11:19:30.802701 Dram Type= 6, Freq= 0, CH_1, rank 0
8440 11:19:30.805930 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8441 11:19:30.809100 ==
8442 11:19:30.809209
8443 11:19:30.809305
8444 11:19:30.809397 TX Vref Scan disable
8445 11:19:30.812845 == TX Byte 0 ==
8446 11:19:30.816156 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8447 11:19:30.819147 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8448 11:19:30.822586 == TX Byte 1 ==
8449 11:19:30.825559 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8450 11:19:30.832447 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8451 11:19:30.832556 ==
8452 11:19:30.835277 Dram Type= 6, Freq= 0, CH_1, rank 0
8453 11:19:30.839008 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8454 11:19:30.839118 ==
8455 11:19:30.852930
8456 11:19:30.855584 TX Vref early break, caculate TX vref
8457 11:19:30.858874 TX Vref=16, minBit 1, minWin=21, winSum=358
8458 11:19:30.862289 TX Vref=18, minBit 1, minWin=22, winSum=366
8459 11:19:30.865553 TX Vref=20, minBit 1, minWin=23, winSum=382
8460 11:19:30.869020 TX Vref=22, minBit 8, minWin=23, winSum=386
8461 11:19:30.872347 TX Vref=24, minBit 0, minWin=24, winSum=399
8462 11:19:30.878690 TX Vref=26, minBit 0, minWin=25, winSum=412
8463 11:19:30.882181 TX Vref=28, minBit 0, minWin=25, winSum=415
8464 11:19:30.885567 TX Vref=30, minBit 0, minWin=24, winSum=409
8465 11:19:30.888773 TX Vref=32, minBit 1, minWin=23, winSum=403
8466 11:19:30.891926 TX Vref=34, minBit 0, minWin=23, winSum=399
8467 11:19:30.898794 TX Vref=36, minBit 1, minWin=22, winSum=380
8468 11:19:30.902130 [TxChooseVref] Worse bit 0, Min win 25, Win sum 415, Final Vref 28
8469 11:19:30.902236
8470 11:19:30.904937 Final TX Range 0 Vref 28
8471 11:19:30.905046
8472 11:19:30.905141 ==
8473 11:19:30.908280 Dram Type= 6, Freq= 0, CH_1, rank 0
8474 11:19:30.911884 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8475 11:19:30.915143 ==
8476 11:19:30.915253
8477 11:19:30.915348
8478 11:19:30.915440 TX Vref Scan disable
8479 11:19:30.921690 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8480 11:19:30.921801 == TX Byte 0 ==
8481 11:19:30.925033 u2DelayCellOfst[0]=22 cells (6 PI)
8482 11:19:30.928498 u2DelayCellOfst[1]=15 cells (4 PI)
8483 11:19:30.931404 u2DelayCellOfst[2]=0 cells (0 PI)
8484 11:19:30.935144 u2DelayCellOfst[3]=11 cells (3 PI)
8485 11:19:30.938015 u2DelayCellOfst[4]=11 cells (3 PI)
8486 11:19:30.941562 u2DelayCellOfst[5]=26 cells (7 PI)
8487 11:19:30.944479 u2DelayCellOfst[6]=26 cells (7 PI)
8488 11:19:30.947995 u2DelayCellOfst[7]=7 cells (2 PI)
8489 11:19:30.951635 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8490 11:19:30.954495 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8491 11:19:30.957970 == TX Byte 1 ==
8492 11:19:30.961371 u2DelayCellOfst[8]=0 cells (0 PI)
8493 11:19:30.964902 u2DelayCellOfst[9]=3 cells (1 PI)
8494 11:19:30.967790 u2DelayCellOfst[10]=11 cells (3 PI)
8495 11:19:30.971135 u2DelayCellOfst[11]=7 cells (2 PI)
8496 11:19:30.974233 u2DelayCellOfst[12]=15 cells (4 PI)
8497 11:19:30.977968 u2DelayCellOfst[13]=18 cells (5 PI)
8498 11:19:30.981179 u2DelayCellOfst[14]=18 cells (5 PI)
8499 11:19:30.981265 u2DelayCellOfst[15]=18 cells (5 PI)
8500 11:19:30.987678 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8501 11:19:30.990922 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8502 11:19:30.994313 DramC Write-DBI on
8503 11:19:30.994424 ==
8504 11:19:30.997719 Dram Type= 6, Freq= 0, CH_1, rank 0
8505 11:19:31.000891 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8506 11:19:31.000989 ==
8507 11:19:31.001060
8508 11:19:31.001167
8509 11:19:31.004385 TX Vref Scan disable
8510 11:19:31.004470 == TX Byte 0 ==
8511 11:19:31.010663 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8512 11:19:31.010749 == TX Byte 1 ==
8513 11:19:31.014052 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8514 11:19:31.017258 DramC Write-DBI off
8515 11:19:31.017343
8516 11:19:31.017410 [DATLAT]
8517 11:19:31.020503 Freq=1600, CH1 RK0
8518 11:19:31.020588
8519 11:19:31.020656 DATLAT Default: 0xf
8520 11:19:31.023939 0, 0xFFFF, sum = 0
8521 11:19:31.027248 1, 0xFFFF, sum = 0
8522 11:19:31.027334 2, 0xFFFF, sum = 0
8523 11:19:31.030022 3, 0xFFFF, sum = 0
8524 11:19:31.030113 4, 0xFFFF, sum = 0
8525 11:19:31.033404 5, 0xFFFF, sum = 0
8526 11:19:31.033491 6, 0xFFFF, sum = 0
8527 11:19:31.036896 7, 0xFFFF, sum = 0
8528 11:19:31.036983 8, 0xFFFF, sum = 0
8529 11:19:31.040713 9, 0xFFFF, sum = 0
8530 11:19:31.040800 10, 0xFFFF, sum = 0
8531 11:19:31.043310 11, 0xFFFF, sum = 0
8532 11:19:31.043385 12, 0xFFFF, sum = 0
8533 11:19:31.046745 13, 0x8FFF, sum = 0
8534 11:19:31.046862 14, 0x0, sum = 1
8535 11:19:31.049806 15, 0x0, sum = 2
8536 11:19:31.049916 16, 0x0, sum = 3
8537 11:19:31.053231 17, 0x0, sum = 4
8538 11:19:31.053338 best_step = 15
8539 11:19:31.053431
8540 11:19:31.053535 ==
8541 11:19:31.056768 Dram Type= 6, Freq= 0, CH_1, rank 0
8542 11:19:31.063255 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8543 11:19:31.063342 ==
8544 11:19:31.063409 RX Vref Scan: 1
8545 11:19:31.063472
8546 11:19:31.066188 Set Vref Range= 24 -> 127
8547 11:19:31.066270
8548 11:19:31.069510 RX Vref 24 -> 127, step: 1
8549 11:19:31.069596
8550 11:19:31.072982 RX Delay 11 -> 252, step: 4
8551 11:19:31.073068
8552 11:19:31.076364 Set Vref, RX VrefLevel [Byte0]: 24
8553 11:19:31.079788 [Byte1]: 24
8554 11:19:31.079871
8555 11:19:31.082665 Set Vref, RX VrefLevel [Byte0]: 25
8556 11:19:31.086286 [Byte1]: 25
8557 11:19:31.086428
8558 11:19:31.089757 Set Vref, RX VrefLevel [Byte0]: 26
8559 11:19:31.092643 [Byte1]: 26
8560 11:19:31.096150
8561 11:19:31.096233 Set Vref, RX VrefLevel [Byte0]: 27
8562 11:19:31.099386 [Byte1]: 27
8563 11:19:31.103438
8564 11:19:31.103521 Set Vref, RX VrefLevel [Byte0]: 28
8565 11:19:31.106785 [Byte1]: 28
8566 11:19:31.111286
8567 11:19:31.111368 Set Vref, RX VrefLevel [Byte0]: 29
8568 11:19:31.115053 [Byte1]: 29
8569 11:19:31.118771
8570 11:19:31.118905 Set Vref, RX VrefLevel [Byte0]: 30
8571 11:19:31.122423 [Byte1]: 30
8572 11:19:31.126871
8573 11:19:31.126954 Set Vref, RX VrefLevel [Byte0]: 31
8574 11:19:31.129625 [Byte1]: 31
8575 11:19:31.133967
8576 11:19:31.134085 Set Vref, RX VrefLevel [Byte0]: 32
8577 11:19:31.137658 [Byte1]: 32
8578 11:19:31.141792
8579 11:19:31.141875 Set Vref, RX VrefLevel [Byte0]: 33
8580 11:19:31.144863 [Byte1]: 33
8581 11:19:31.149629
8582 11:19:31.149743 Set Vref, RX VrefLevel [Byte0]: 34
8583 11:19:31.152460 [Byte1]: 34
8584 11:19:31.157202
8585 11:19:31.157287 Set Vref, RX VrefLevel [Byte0]: 35
8586 11:19:31.160097 [Byte1]: 35
8587 11:19:31.164654
8588 11:19:31.164771 Set Vref, RX VrefLevel [Byte0]: 36
8589 11:19:31.167588 [Byte1]: 36
8590 11:19:31.172123
8591 11:19:31.172234 Set Vref, RX VrefLevel [Byte0]: 37
8592 11:19:31.175872 [Byte1]: 37
8593 11:19:31.179749
8594 11:19:31.179834 Set Vref, RX VrefLevel [Byte0]: 38
8595 11:19:31.183251 [Byte1]: 38
8596 11:19:31.187637
8597 11:19:31.187723 Set Vref, RX VrefLevel [Byte0]: 39
8598 11:19:31.190814 [Byte1]: 39
8599 11:19:31.195018
8600 11:19:31.195103 Set Vref, RX VrefLevel [Byte0]: 40
8601 11:19:31.198481 [Byte1]: 40
8602 11:19:31.202450
8603 11:19:31.202535 Set Vref, RX VrefLevel [Byte0]: 41
8604 11:19:31.205766 [Byte1]: 41
8605 11:19:31.210331
8606 11:19:31.210440 Set Vref, RX VrefLevel [Byte0]: 42
8607 11:19:31.213582 [Byte1]: 42
8608 11:19:31.218064
8609 11:19:31.218179 Set Vref, RX VrefLevel [Byte0]: 43
8610 11:19:31.221021 [Byte1]: 43
8611 11:19:31.225664
8612 11:19:31.225778 Set Vref, RX VrefLevel [Byte0]: 44
8613 11:19:31.229073 [Byte1]: 44
8614 11:19:31.233070
8615 11:19:31.233181 Set Vref, RX VrefLevel [Byte0]: 45
8616 11:19:31.236555 [Byte1]: 45
8617 11:19:31.240551
8618 11:19:31.240659 Set Vref, RX VrefLevel [Byte0]: 46
8619 11:19:31.244110 [Byte1]: 46
8620 11:19:31.248386
8621 11:19:31.248473 Set Vref, RX VrefLevel [Byte0]: 47
8622 11:19:31.251573 [Byte1]: 47
8623 11:19:31.256061
8624 11:19:31.256147 Set Vref, RX VrefLevel [Byte0]: 48
8625 11:19:31.259763 [Byte1]: 48
8626 11:19:31.263960
8627 11:19:31.264045 Set Vref, RX VrefLevel [Byte0]: 49
8628 11:19:31.266764 [Byte1]: 49
8629 11:19:31.271310
8630 11:19:31.271403 Set Vref, RX VrefLevel [Byte0]: 50
8631 11:19:31.274566 [Byte1]: 50
8632 11:19:31.278702
8633 11:19:31.278814 Set Vref, RX VrefLevel [Byte0]: 51
8634 11:19:31.282291 [Byte1]: 51
8635 11:19:31.286531
8636 11:19:31.286615 Set Vref, RX VrefLevel [Byte0]: 52
8637 11:19:31.289896 [Byte1]: 52
8638 11:19:31.294413
8639 11:19:31.294524 Set Vref, RX VrefLevel [Byte0]: 53
8640 11:19:31.297429 [Byte1]: 53
8641 11:19:31.302096
8642 11:19:31.302207 Set Vref, RX VrefLevel [Byte0]: 54
8643 11:19:31.304647 [Byte1]: 54
8644 11:19:31.309104
8645 11:19:31.309191 Set Vref, RX VrefLevel [Byte0]: 55
8646 11:19:31.312625 [Byte1]: 55
8647 11:19:31.316616
8648 11:19:31.316701 Set Vref, RX VrefLevel [Byte0]: 56
8649 11:19:31.320065 [Byte1]: 56
8650 11:19:31.324713
8651 11:19:31.324799 Set Vref, RX VrefLevel [Byte0]: 57
8652 11:19:31.327634 [Byte1]: 57
8653 11:19:31.332237
8654 11:19:31.332322 Set Vref, RX VrefLevel [Byte0]: 58
8655 11:19:31.335178 [Byte1]: 58
8656 11:19:31.339709
8657 11:19:31.339828 Set Vref, RX VrefLevel [Byte0]: 59
8658 11:19:31.343081 [Byte1]: 59
8659 11:19:31.347580
8660 11:19:31.347665 Set Vref, RX VrefLevel [Byte0]: 60
8661 11:19:31.350782 [Byte1]: 60
8662 11:19:31.355025
8663 11:19:31.355149 Set Vref, RX VrefLevel [Byte0]: 61
8664 11:19:31.357912 [Byte1]: 61
8665 11:19:31.362653
8666 11:19:31.362764 Set Vref, RX VrefLevel [Byte0]: 62
8667 11:19:31.365728 [Byte1]: 62
8668 11:19:31.370523
8669 11:19:31.370635 Set Vref, RX VrefLevel [Byte0]: 63
8670 11:19:31.373480 [Byte1]: 63
8671 11:19:31.377977
8672 11:19:31.378061 Set Vref, RX VrefLevel [Byte0]: 64
8673 11:19:31.381460 [Byte1]: 64
8674 11:19:31.385343
8675 11:19:31.385454 Set Vref, RX VrefLevel [Byte0]: 65
8676 11:19:31.388998 [Byte1]: 65
8677 11:19:31.393048
8678 11:19:31.393133 Set Vref, RX VrefLevel [Byte0]: 66
8679 11:19:31.396536 [Byte1]: 66
8680 11:19:31.400439
8681 11:19:31.400524 Set Vref, RX VrefLevel [Byte0]: 67
8682 11:19:31.403876 [Byte1]: 67
8683 11:19:31.408208
8684 11:19:31.408295 Set Vref, RX VrefLevel [Byte0]: 68
8685 11:19:31.411536 [Byte1]: 68
8686 11:19:31.416211
8687 11:19:31.416322 Set Vref, RX VrefLevel [Byte0]: 69
8688 11:19:31.418962 [Byte1]: 69
8689 11:19:31.423629
8690 11:19:31.423712 Set Vref, RX VrefLevel [Byte0]: 70
8691 11:19:31.426430 [Byte1]: 70
8692 11:19:31.431199
8693 11:19:31.431283 Set Vref, RX VrefLevel [Byte0]: 71
8694 11:19:31.434550 [Byte1]: 71
8695 11:19:31.438727
8696 11:19:31.438845 Final RX Vref Byte 0 = 59 to rank0
8697 11:19:31.442055 Final RX Vref Byte 1 = 56 to rank0
8698 11:19:31.445013 Final RX Vref Byte 0 = 59 to rank1
8699 11:19:31.448563 Final RX Vref Byte 1 = 56 to rank1==
8700 11:19:31.452045 Dram Type= 6, Freq= 0, CH_1, rank 0
8701 11:19:31.458469 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8702 11:19:31.458554 ==
8703 11:19:31.458621 DQS Delay:
8704 11:19:31.461799 DQS0 = 0, DQS1 = 0
8705 11:19:31.461913 DQM Delay:
8706 11:19:31.462011 DQM0 = 129, DQM1 = 122
8707 11:19:31.464607 DQ Delay:
8708 11:19:31.468289 DQ0 =136, DQ1 =126, DQ2 =118, DQ3 =126
8709 11:19:31.471262 DQ4 =128, DQ5 =140, DQ6 =140, DQ7 =124
8710 11:19:31.474724 DQ8 =108, DQ9 =112, DQ10 =122, DQ11 =114
8711 11:19:31.478308 DQ12 =130, DQ13 =130, DQ14 =130, DQ15 =130
8712 11:19:31.478388
8713 11:19:31.478488
8714 11:19:31.478579
8715 11:19:31.481120 [DramC_TX_OE_Calibration] TA2
8716 11:19:31.484519 Original DQ_B0 (3 6) =30, OEN = 27
8717 11:19:31.487910 Original DQ_B1 (3 6) =30, OEN = 27
8718 11:19:31.491281 24, 0x0, End_B0=24 End_B1=24
8719 11:19:31.494322 25, 0x0, End_B0=25 End_B1=25
8720 11:19:31.494437 26, 0x0, End_B0=26 End_B1=26
8721 11:19:31.497839 27, 0x0, End_B0=27 End_B1=27
8722 11:19:31.501275 28, 0x0, End_B0=28 End_B1=28
8723 11:19:31.504642 29, 0x0, End_B0=29 End_B1=29
8724 11:19:31.504722 30, 0x0, End_B0=30 End_B1=30
8725 11:19:31.507535 31, 0x4141, End_B0=30 End_B1=30
8726 11:19:31.511044 Byte0 end_step=30 best_step=27
8727 11:19:31.514415 Byte1 end_step=30 best_step=27
8728 11:19:31.517954 Byte0 TX OE(2T, 0.5T) = (3, 3)
8729 11:19:31.520783 Byte1 TX OE(2T, 0.5T) = (3, 3)
8730 11:19:31.520858
8731 11:19:31.520921
8732 11:19:31.527248 [DQSOSCAuto] RK0, (LSB)MR18= 0xa0f, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 404 ps
8733 11:19:31.530781 CH1 RK0: MR19=303, MR18=A0F
8734 11:19:31.537526 CH1_RK0: MR19=0x303, MR18=0xA0F, DQSOSC=402, MR23=63, INC=22, DEC=15
8735 11:19:31.537613
8736 11:19:31.540746 ----->DramcWriteLeveling(PI) begin...
8737 11:19:31.540833 ==
8738 11:19:31.543948 Dram Type= 6, Freq= 0, CH_1, rank 1
8739 11:19:31.547346 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8740 11:19:31.547432 ==
8741 11:19:31.550341 Write leveling (Byte 0): 23 => 23
8742 11:19:31.553562 Write leveling (Byte 1): 29 => 29
8743 11:19:31.557054 DramcWriteLeveling(PI) end<-----
8744 11:19:31.557159
8745 11:19:31.557254 ==
8746 11:19:31.559883 Dram Type= 6, Freq= 0, CH_1, rank 1
8747 11:19:31.566721 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8748 11:19:31.566838 ==
8749 11:19:31.566917 [Gating] SW mode calibration
8750 11:19:31.576688 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8751 11:19:31.579695 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8752 11:19:31.586652 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8753 11:19:31.590315 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8754 11:19:31.592975 1 4 8 | B1->B0 | 2323 3232 | 0 1 | (0 0) (1 1)
8755 11:19:31.599694 1 4 12 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
8756 11:19:31.603094 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8757 11:19:31.605989 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8758 11:19:31.612852 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8759 11:19:31.616400 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8760 11:19:31.619394 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8761 11:19:31.626161 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8762 11:19:31.629346 1 5 8 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 1)
8763 11:19:31.632594 1 5 12 | B1->B0 | 3030 2323 | 0 0 | (0 1) (0 0)
8764 11:19:31.639098 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8765 11:19:31.642505 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8766 11:19:31.645407 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8767 11:19:31.652590 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8768 11:19:31.655375 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8769 11:19:31.658526 1 6 4 | B1->B0 | 2323 2828 | 0 1 | (0 0) (0 0)
8770 11:19:31.665496 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8771 11:19:31.668933 1 6 12 | B1->B0 | 3232 4646 | 0 0 | (0 0) (0 0)
8772 11:19:31.672214 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8773 11:19:31.678605 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8774 11:19:31.682003 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8775 11:19:31.685279 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8776 11:19:31.692189 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8777 11:19:31.695276 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8778 11:19:31.698083 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8779 11:19:31.705068 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8780 11:19:31.708018 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8781 11:19:31.711475 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8782 11:19:31.717865 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8783 11:19:31.721233 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8784 11:19:31.724543 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8785 11:19:31.731132 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8786 11:19:31.734377 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8787 11:19:31.737723 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8788 11:19:31.744323 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8789 11:19:31.748044 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8790 11:19:31.750729 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8791 11:19:31.757703 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8792 11:19:31.760728 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8793 11:19:31.764388 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8794 11:19:31.770745 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8795 11:19:31.773781 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8796 11:19:31.777764 Total UI for P1: 0, mck2ui 16
8797 11:19:31.780577 best dqsien dly found for B0: ( 1, 9, 8)
8798 11:19:31.783995 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8799 11:19:31.787486 Total UI for P1: 0, mck2ui 16
8800 11:19:31.790401 best dqsien dly found for B1: ( 1, 9, 12)
8801 11:19:31.793888 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8802 11:19:31.797215 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8803 11:19:31.797301
8804 11:19:31.803529 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8805 11:19:31.806979 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8806 11:19:31.807065 [Gating] SW calibration Done
8807 11:19:31.810539 ==
8808 11:19:31.813450 Dram Type= 6, Freq= 0, CH_1, rank 1
8809 11:19:31.816830 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8810 11:19:31.816916 ==
8811 11:19:31.816983 RX Vref Scan: 0
8812 11:19:31.817047
8813 11:19:31.820407 RX Vref 0 -> 0, step: 1
8814 11:19:31.820491
8815 11:19:31.823220 RX Delay 0 -> 252, step: 8
8816 11:19:31.826648 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8817 11:19:31.830228 iDelay=200, Bit 1, Center 127 (72 ~ 183) 112
8818 11:19:31.836503 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8819 11:19:31.840011 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8820 11:19:31.843317 iDelay=200, Bit 4, Center 127 (64 ~ 191) 128
8821 11:19:31.846510 iDelay=200, Bit 5, Center 139 (80 ~ 199) 120
8822 11:19:31.849877 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8823 11:19:31.856385 iDelay=200, Bit 7, Center 131 (72 ~ 191) 120
8824 11:19:31.859716 iDelay=200, Bit 8, Center 111 (48 ~ 175) 128
8825 11:19:31.862730 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8826 11:19:31.866117 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8827 11:19:31.869373 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8828 11:19:31.876318 iDelay=200, Bit 12, Center 131 (72 ~ 191) 120
8829 11:19:31.879348 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8830 11:19:31.882666 iDelay=200, Bit 14, Center 131 (72 ~ 191) 120
8831 11:19:31.885850 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8832 11:19:31.885928 ==
8833 11:19:31.889062 Dram Type= 6, Freq= 0, CH_1, rank 1
8834 11:19:31.896257 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8835 11:19:31.896345 ==
8836 11:19:31.896436 DQS Delay:
8837 11:19:31.899331 DQS0 = 0, DQS1 = 0
8838 11:19:31.899407 DQM Delay:
8839 11:19:31.899471 DQM0 = 131, DQM1 = 127
8840 11:19:31.902412 DQ Delay:
8841 11:19:31.906076 DQ0 =135, DQ1 =127, DQ2 =119, DQ3 =131
8842 11:19:31.908918 DQ4 =127, DQ5 =139, DQ6 =139, DQ7 =131
8843 11:19:31.912407 DQ8 =111, DQ9 =115, DQ10 =131, DQ11 =123
8844 11:19:31.915895 DQ12 =131, DQ13 =139, DQ14 =131, DQ15 =139
8845 11:19:31.915980
8846 11:19:31.916047
8847 11:19:31.916109 ==
8848 11:19:31.918756 Dram Type= 6, Freq= 0, CH_1, rank 1
8849 11:19:31.925687 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8850 11:19:31.925772 ==
8851 11:19:31.925840
8852 11:19:31.925902
8853 11:19:31.925962 TX Vref Scan disable
8854 11:19:31.929195 == TX Byte 0 ==
8855 11:19:31.932202 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8856 11:19:31.939098 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8857 11:19:31.939210 == TX Byte 1 ==
8858 11:19:31.941983 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8859 11:19:31.948900 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8860 11:19:31.948986 ==
8861 11:19:31.952141 Dram Type= 6, Freq= 0, CH_1, rank 1
8862 11:19:31.955145 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8863 11:19:31.955230 ==
8864 11:19:31.969545
8865 11:19:31.972872 TX Vref early break, caculate TX vref
8866 11:19:31.976600 TX Vref=16, minBit 0, minWin=22, winSum=373
8867 11:19:31.979247 TX Vref=18, minBit 0, minWin=22, winSum=380
8868 11:19:31.982732 TX Vref=20, minBit 0, minWin=22, winSum=390
8869 11:19:31.986340 TX Vref=22, minBit 0, minWin=23, winSum=397
8870 11:19:31.989076 TX Vref=24, minBit 0, minWin=24, winSum=405
8871 11:19:31.995943 TX Vref=26, minBit 0, minWin=24, winSum=410
8872 11:19:31.999269 TX Vref=28, minBit 0, minWin=25, winSum=416
8873 11:19:32.002813 TX Vref=30, minBit 0, minWin=25, winSum=410
8874 11:19:32.005921 TX Vref=32, minBit 8, minWin=23, winSum=400
8875 11:19:32.008949 TX Vref=34, minBit 1, minWin=24, winSum=395
8876 11:19:32.012291 TX Vref=36, minBit 1, minWin=22, winSum=386
8877 11:19:32.018850 [TxChooseVref] Worse bit 0, Min win 25, Win sum 416, Final Vref 28
8878 11:19:32.018961
8879 11:19:32.022356 Final TX Range 0 Vref 28
8880 11:19:32.022468
8881 11:19:32.022564 ==
8882 11:19:32.025916 Dram Type= 6, Freq= 0, CH_1, rank 1
8883 11:19:32.028672 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8884 11:19:32.028758 ==
8885 11:19:32.032186
8886 11:19:32.032270
8887 11:19:32.032337 TX Vref Scan disable
8888 11:19:32.038785 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =258/100 ps
8889 11:19:32.038903 == TX Byte 0 ==
8890 11:19:32.042078 u2DelayCellOfst[0]=18 cells (5 PI)
8891 11:19:32.045577 u2DelayCellOfst[1]=18 cells (5 PI)
8892 11:19:32.048439 u2DelayCellOfst[2]=0 cells (0 PI)
8893 11:19:32.051975 u2DelayCellOfst[3]=7 cells (2 PI)
8894 11:19:32.055380 u2DelayCellOfst[4]=7 cells (2 PI)
8895 11:19:32.058263 u2DelayCellOfst[5]=22 cells (6 PI)
8896 11:19:32.061539 u2DelayCellOfst[6]=22 cells (6 PI)
8897 11:19:32.064855 u2DelayCellOfst[7]=7 cells (2 PI)
8898 11:19:32.068062 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8899 11:19:32.071795 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8900 11:19:32.074927 == TX Byte 1 ==
8901 11:19:32.078279 u2DelayCellOfst[8]=0 cells (0 PI)
8902 11:19:32.081413 u2DelayCellOfst[9]=7 cells (2 PI)
8903 11:19:32.084752 u2DelayCellOfst[10]=15 cells (4 PI)
8904 11:19:32.088179 u2DelayCellOfst[11]=7 cells (2 PI)
8905 11:19:32.091907 u2DelayCellOfst[12]=18 cells (5 PI)
8906 11:19:32.095265 u2DelayCellOfst[13]=18 cells (5 PI)
8907 11:19:32.095357 u2DelayCellOfst[14]=22 cells (6 PI)
8908 11:19:32.098005 u2DelayCellOfst[15]=22 cells (6 PI)
8909 11:19:32.104909 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8910 11:19:32.107787 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8911 11:19:32.111216 DramC Write-DBI on
8912 11:19:32.111309 ==
8913 11:19:32.114366 Dram Type= 6, Freq= 0, CH_1, rank 1
8914 11:19:32.117656 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8915 11:19:32.117745 ==
8916 11:19:32.117814
8917 11:19:32.117876
8918 11:19:32.121098 TX Vref Scan disable
8919 11:19:32.121186 == TX Byte 0 ==
8920 11:19:32.128200 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8921 11:19:32.128288 == TX Byte 1 ==
8922 11:19:32.130777 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8923 11:19:32.134332 DramC Write-DBI off
8924 11:19:32.134418
8925 11:19:32.134511 [DATLAT]
8926 11:19:32.137784 Freq=1600, CH1 RK1
8927 11:19:32.137897
8928 11:19:32.137998 DATLAT Default: 0xf
8929 11:19:32.140845 0, 0xFFFF, sum = 0
8930 11:19:32.140959 1, 0xFFFF, sum = 0
8931 11:19:32.144268 2, 0xFFFF, sum = 0
8932 11:19:32.147532 3, 0xFFFF, sum = 0
8933 11:19:32.147611 4, 0xFFFF, sum = 0
8934 11:19:32.151022 5, 0xFFFF, sum = 0
8935 11:19:32.151097 6, 0xFFFF, sum = 0
8936 11:19:32.153869 7, 0xFFFF, sum = 0
8937 11:19:32.153969 8, 0xFFFF, sum = 0
8938 11:19:32.157668 9, 0xFFFF, sum = 0
8939 11:19:32.157754 10, 0xFFFF, sum = 0
8940 11:19:32.160405 11, 0xFFFF, sum = 0
8941 11:19:32.160491 12, 0xFFFF, sum = 0
8942 11:19:32.163817 13, 0x8FFF, sum = 0
8943 11:19:32.163897 14, 0x0, sum = 1
8944 11:19:32.167271 15, 0x0, sum = 2
8945 11:19:32.167349 16, 0x0, sum = 3
8946 11:19:32.171085 17, 0x0, sum = 4
8947 11:19:32.171160 best_step = 15
8948 11:19:32.171223
8949 11:19:32.171282 ==
8950 11:19:32.173604 Dram Type= 6, Freq= 0, CH_1, rank 1
8951 11:19:32.180466 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8952 11:19:32.180557 ==
8953 11:19:32.180623 RX Vref Scan: 0
8954 11:19:32.180684
8955 11:19:32.183870 RX Vref 0 -> 0, step: 1
8956 11:19:32.183954
8957 11:19:32.186703 RX Delay 3 -> 252, step: 4
8958 11:19:32.190160 iDelay=195, Bit 0, Center 134 (79 ~ 190) 112
8959 11:19:32.193645 iDelay=195, Bit 1, Center 126 (75 ~ 178) 104
8960 11:19:32.196952 iDelay=195, Bit 2, Center 116 (63 ~ 170) 108
8961 11:19:32.203398 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8962 11:19:32.206563 iDelay=195, Bit 4, Center 124 (67 ~ 182) 116
8963 11:19:32.210195 iDelay=195, Bit 5, Center 140 (87 ~ 194) 108
8964 11:19:32.213644 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
8965 11:19:32.216930 iDelay=195, Bit 7, Center 126 (71 ~ 182) 112
8966 11:19:32.222977 iDelay=195, Bit 8, Center 108 (51 ~ 166) 116
8967 11:19:32.226320 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8968 11:19:32.229786 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8969 11:19:32.233030 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8970 11:19:32.239305 iDelay=195, Bit 12, Center 130 (75 ~ 186) 112
8971 11:19:32.242744 iDelay=195, Bit 13, Center 130 (75 ~ 186) 112
8972 11:19:32.246165 iDelay=195, Bit 14, Center 130 (75 ~ 186) 112
8973 11:19:32.249134 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
8974 11:19:32.249220 ==
8975 11:19:32.252496 Dram Type= 6, Freq= 0, CH_1, rank 1
8976 11:19:32.259534 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8977 11:19:32.259630 ==
8978 11:19:32.259698 DQS Delay:
8979 11:19:32.262440 DQS0 = 0, DQS1 = 0
8980 11:19:32.262532 DQM Delay:
8981 11:19:32.265872 DQM0 = 129, DQM1 = 124
8982 11:19:32.265985 DQ Delay:
8983 11:19:32.269256 DQ0 =134, DQ1 =126, DQ2 =116, DQ3 =128
8984 11:19:32.272807 DQ4 =124, DQ5 =140, DQ6 =140, DQ7 =126
8985 11:19:32.275948 DQ8 =108, DQ9 =112, DQ10 =128, DQ11 =120
8986 11:19:32.279118 DQ12 =130, DQ13 =130, DQ14 =130, DQ15 =136
8987 11:19:32.279210
8988 11:19:32.279299
8989 11:19:32.279381
8990 11:19:32.282400 [DramC_TX_OE_Calibration] TA2
8991 11:19:32.285519 Original DQ_B0 (3 6) =30, OEN = 27
8992 11:19:32.288916 Original DQ_B1 (3 6) =30, OEN = 27
8993 11:19:32.292268 24, 0x0, End_B0=24 End_B1=24
8994 11:19:32.295685 25, 0x0, End_B0=25 End_B1=25
8995 11:19:32.295803 26, 0x0, End_B0=26 End_B1=26
8996 11:19:32.298656 27, 0x0, End_B0=27 End_B1=27
8997 11:19:32.302164 28, 0x0, End_B0=28 End_B1=28
8998 11:19:32.305551 29, 0x0, End_B0=29 End_B1=29
8999 11:19:32.305657 30, 0x0, End_B0=30 End_B1=30
9000 11:19:32.309080 31, 0x4141, End_B0=30 End_B1=30
9001 11:19:32.311802 Byte0 end_step=30 best_step=27
9002 11:19:32.315501 Byte1 end_step=30 best_step=27
9003 11:19:32.318797 Byte0 TX OE(2T, 0.5T) = (3, 3)
9004 11:19:32.321993 Byte1 TX OE(2T, 0.5T) = (3, 3)
9005 11:19:32.322081
9006 11:19:32.322147
9007 11:19:32.328522 [DQSOSCAuto] RK1, (LSB)MR18= 0x101c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 401 ps
9008 11:19:32.331937 CH1 RK1: MR19=303, MR18=101C
9009 11:19:32.338070 CH1_RK1: MR19=0x303, MR18=0x101C, DQSOSC=395, MR23=63, INC=23, DEC=15
9010 11:19:32.341577 [RxdqsGatingPostProcess] freq 1600
9011 11:19:32.348670 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9012 11:19:32.348784 best DQS0 dly(2T, 0.5T) = (1, 1)
9013 11:19:32.351433 best DQS1 dly(2T, 0.5T) = (1, 1)
9014 11:19:32.354846 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9015 11:19:32.358234 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9016 11:19:32.361379 best DQS0 dly(2T, 0.5T) = (1, 1)
9017 11:19:32.364770 best DQS1 dly(2T, 0.5T) = (1, 1)
9018 11:19:32.368270 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9019 11:19:32.371120 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9020 11:19:32.374596 Pre-setting of DQS Precalculation
9021 11:19:32.378036 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9022 11:19:32.387947 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9023 11:19:32.394447 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9024 11:19:32.394559
9025 11:19:32.394628
9026 11:19:32.397715 [Calibration Summary] 3200 Mbps
9027 11:19:32.397839 CH 0, Rank 0
9028 11:19:32.401173 SW Impedance : PASS
9029 11:19:32.401282 DUTY Scan : NO K
9030 11:19:32.404699 ZQ Calibration : PASS
9031 11:19:32.407696 Jitter Meter : NO K
9032 11:19:32.407801 CBT Training : PASS
9033 11:19:32.411408 Write leveling : PASS
9034 11:19:32.414135 RX DQS gating : PASS
9035 11:19:32.414248 RX DQ/DQS(RDDQC) : PASS
9036 11:19:32.417583 TX DQ/DQS : PASS
9037 11:19:32.420833 RX DATLAT : PASS
9038 11:19:32.420944 RX DQ/DQS(Engine): PASS
9039 11:19:32.424244 TX OE : PASS
9040 11:19:32.424350 All Pass.
9041 11:19:32.424445
9042 11:19:32.427649 CH 0, Rank 1
9043 11:19:32.427752 SW Impedance : PASS
9044 11:19:32.430742 DUTY Scan : NO K
9045 11:19:32.434002 ZQ Calibration : PASS
9046 11:19:32.434113 Jitter Meter : NO K
9047 11:19:32.437250 CBT Training : PASS
9048 11:19:32.440317 Write leveling : PASS
9049 11:19:32.440429 RX DQS gating : PASS
9050 11:19:32.443496 RX DQ/DQS(RDDQC) : PASS
9051 11:19:32.447138 TX DQ/DQS : PASS
9052 11:19:32.447253 RX DATLAT : PASS
9053 11:19:32.450555 RX DQ/DQS(Engine): PASS
9054 11:19:32.453538 TX OE : PASS
9055 11:19:32.453629 All Pass.
9056 11:19:32.453700
9057 11:19:32.453764 CH 1, Rank 0
9058 11:19:32.457078 SW Impedance : PASS
9059 11:19:32.460485 DUTY Scan : NO K
9060 11:19:32.460603 ZQ Calibration : PASS
9061 11:19:32.463284 Jitter Meter : NO K
9062 11:19:32.466708 CBT Training : PASS
9063 11:19:32.466815 Write leveling : PASS
9064 11:19:32.470498 RX DQS gating : PASS
9065 11:19:32.473157 RX DQ/DQS(RDDQC) : PASS
9066 11:19:32.473232 TX DQ/DQS : PASS
9067 11:19:32.476789 RX DATLAT : PASS
9068 11:19:32.479514 RX DQ/DQS(Engine): PASS
9069 11:19:32.479594 TX OE : PASS
9070 11:19:32.483009 All Pass.
9071 11:19:32.483115
9072 11:19:32.483237 CH 1, Rank 1
9073 11:19:32.486052 SW Impedance : PASS
9074 11:19:32.486128 DUTY Scan : NO K
9075 11:19:32.489547 ZQ Calibration : PASS
9076 11:19:32.493062 Jitter Meter : NO K
9077 11:19:32.493144 CBT Training : PASS
9078 11:19:32.495968 Write leveling : PASS
9079 11:19:32.499315 RX DQS gating : PASS
9080 11:19:32.499427 RX DQ/DQS(RDDQC) : PASS
9081 11:19:32.502552 TX DQ/DQS : PASS
9082 11:19:32.502637 RX DATLAT : PASS
9083 11:19:32.505876 RX DQ/DQS(Engine): PASS
9084 11:19:32.509253 TX OE : PASS
9085 11:19:32.509341 All Pass.
9086 11:19:32.509407
9087 11:19:32.512714 DramC Write-DBI on
9088 11:19:32.515694 PER_BANK_REFRESH: Hybrid Mode
9089 11:19:32.515779 TX_TRACKING: ON
9090 11:19:32.525294 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9091 11:19:32.532331 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9092 11:19:32.538904 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9093 11:19:32.542505 [FAST_K] Save calibration result to emmc
9094 11:19:32.545444 sync common calibartion params.
9095 11:19:32.548529 sync cbt_mode0:1, 1:1
9096 11:19:32.552216 dram_init: ddr_geometry: 2
9097 11:19:32.552305 dram_init: ddr_geometry: 2
9098 11:19:32.555022 dram_init: ddr_geometry: 2
9099 11:19:32.558447 0:dram_rank_size:100000000
9100 11:19:32.562023 1:dram_rank_size:100000000
9101 11:19:32.564819 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9102 11:19:32.568224 DFS_SHUFFLE_HW_MODE: ON
9103 11:19:32.571704 dramc_set_vcore_voltage set vcore to 725000
9104 11:19:32.574674 Read voltage for 1600, 0
9105 11:19:32.574778 Vio18 = 0
9106 11:19:32.574910 Vcore = 725000
9107 11:19:32.578266 Vdram = 0
9108 11:19:32.578362 Vddq = 0
9109 11:19:32.578452 Vmddr = 0
9110 11:19:32.581439 switch to 3200 Mbps bootup
9111 11:19:32.584909 [DramcRunTimeConfig]
9112 11:19:32.585005 PHYPLL
9113 11:19:32.585095 DPM_CONTROL_AFTERK: ON
9114 11:19:32.587884 PER_BANK_REFRESH: ON
9115 11:19:32.591573 REFRESH_OVERHEAD_REDUCTION: ON
9116 11:19:32.595059 CMD_PICG_NEW_MODE: OFF
9117 11:19:32.595173 XRTWTW_NEW_MODE: ON
9118 11:19:32.597791 XRTRTR_NEW_MODE: ON
9119 11:19:32.597877 TX_TRACKING: ON
9120 11:19:32.601131 RDSEL_TRACKING: OFF
9121 11:19:32.601218 DQS Precalculation for DVFS: ON
9122 11:19:32.604859 RX_TRACKING: OFF
9123 11:19:32.604948 HW_GATING DBG: ON
9124 11:19:32.608033 ZQCS_ENABLE_LP4: ON
9125 11:19:32.611248 RX_PICG_NEW_MODE: ON
9126 11:19:32.611361 TX_PICG_NEW_MODE: ON
9127 11:19:32.614305 ENABLE_RX_DCM_DPHY: ON
9128 11:19:32.617906 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9129 11:19:32.618026 DUMMY_READ_FOR_TRACKING: OFF
9130 11:19:32.621371 !!! SPM_CONTROL_AFTERK: OFF
9131 11:19:32.624300 !!! SPM could not control APHY
9132 11:19:32.627960 IMPEDANCE_TRACKING: ON
9133 11:19:32.628047 TEMP_SENSOR: ON
9134 11:19:32.631188 HW_SAVE_FOR_SR: OFF
9135 11:19:32.634074 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9136 11:19:32.637699 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9137 11:19:32.637817 Read ODT Tracking: ON
9138 11:19:32.641199 Refresh Rate DeBounce: ON
9139 11:19:32.643913 DFS_NO_QUEUE_FLUSH: ON
9140 11:19:32.647657 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9141 11:19:32.647785 ENABLE_DFS_RUNTIME_MRW: OFF
9142 11:19:32.650965 DDR_RESERVE_NEW_MODE: ON
9143 11:19:32.653836 MR_CBT_SWITCH_FREQ: ON
9144 11:19:32.653956 =========================
9145 11:19:32.673979 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9146 11:19:32.677449 dram_init: ddr_geometry: 2
9147 11:19:32.695325 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9148 11:19:32.698855 dram_init: dram init end (result: 0)
9149 11:19:32.705946 DRAM-K: Full calibration passed in 24536 msecs
9150 11:19:32.708809 MRC: failed to locate region type 0.
9151 11:19:32.708912 DRAM rank0 size:0x100000000,
9152 11:19:32.712242 DRAM rank1 size=0x100000000
9153 11:19:32.722369 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9154 11:19:32.729315 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9155 11:19:32.735575 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9156 11:19:32.745340 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9157 11:19:32.745463 DRAM rank0 size:0x100000000,
9158 11:19:32.748174 DRAM rank1 size=0x100000000
9159 11:19:32.748261 CBMEM:
9160 11:19:32.751660 IMD: root @ 0xfffff000 254 entries.
9161 11:19:32.754758 IMD: root @ 0xffffec00 62 entries.
9162 11:19:32.758572 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9163 11:19:32.764760 WARNING: RO_VPD is uninitialized or empty.
9164 11:19:32.768018 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9165 11:19:32.775814 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9166 11:19:32.788462 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9167 11:19:32.799643 BS: romstage times (exec / console): total (unknown) / 24003 ms
9168 11:19:32.799794
9169 11:19:32.799868
9170 11:19:32.809439 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9171 11:19:32.812951 ARM64: Exception handlers installed.
9172 11:19:32.816410 ARM64: Testing exception
9173 11:19:32.819459 ARM64: Done test exception
9174 11:19:32.819549 Enumerating buses...
9175 11:19:32.823028 Show all devs... Before device enumeration.
9176 11:19:32.826122 Root Device: enabled 1
9177 11:19:32.829595 CPU_CLUSTER: 0: enabled 1
9178 11:19:32.829686 CPU: 00: enabled 1
9179 11:19:32.832620 Compare with tree...
9180 11:19:32.832707 Root Device: enabled 1
9181 11:19:32.836106 CPU_CLUSTER: 0: enabled 1
9182 11:19:32.839212 CPU: 00: enabled 1
9183 11:19:32.839296 Root Device scanning...
9184 11:19:32.842518 scan_static_bus for Root Device
9185 11:19:32.845953 CPU_CLUSTER: 0 enabled
9186 11:19:32.849455 scan_static_bus for Root Device done
9187 11:19:32.852315 scan_bus: bus Root Device finished in 8 msecs
9188 11:19:32.852465 done
9189 11:19:32.859137 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9190 11:19:32.862575 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9191 11:19:32.869592 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9192 11:19:32.872684 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9193 11:19:32.875519 Allocating resources...
9194 11:19:32.878746 Reading resources...
9195 11:19:32.882594 Root Device read_resources bus 0 link: 0
9196 11:19:32.885290 DRAM rank0 size:0x100000000,
9197 11:19:32.885387 DRAM rank1 size=0x100000000
9198 11:19:32.892176 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9199 11:19:32.892284 CPU: 00 missing read_resources
9200 11:19:32.898900 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9201 11:19:32.901873 Root Device read_resources bus 0 link: 0 done
9202 11:19:32.905258 Done reading resources.
9203 11:19:32.908796 Show resources in subtree (Root Device)...After reading.
9204 11:19:32.912177 Root Device child on link 0 CPU_CLUSTER: 0
9205 11:19:32.915137 CPU_CLUSTER: 0 child on link 0 CPU: 00
9206 11:19:32.924924 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9207 11:19:32.925035 CPU: 00
9208 11:19:32.931703 Root Device assign_resources, bus 0 link: 0
9209 11:19:32.935135 CPU_CLUSTER: 0 missing set_resources
9210 11:19:32.938023 Root Device assign_resources, bus 0 link: 0 done
9211 11:19:32.938113 Done setting resources.
9212 11:19:32.944819 Show resources in subtree (Root Device)...After assigning values.
9213 11:19:32.948205 Root Device child on link 0 CPU_CLUSTER: 0
9214 11:19:32.954540 CPU_CLUSTER: 0 child on link 0 CPU: 00
9215 11:19:32.961253 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9216 11:19:32.961381 CPU: 00
9217 11:19:32.964826 Done allocating resources.
9218 11:19:32.971281 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9219 11:19:32.971388 Enabling resources...
9220 11:19:32.974248 done.
9221 11:19:32.978074 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9222 11:19:32.981073 Initializing devices...
9223 11:19:32.981168 Root Device init
9224 11:19:32.984288 init hardware done!
9225 11:19:32.984375 0x00000018: ctrlr->caps
9226 11:19:32.987732 52.000 MHz: ctrlr->f_max
9227 11:19:32.990820 0.400 MHz: ctrlr->f_min
9228 11:19:32.993994 0x40ff8080: ctrlr->voltages
9229 11:19:32.994096 sclk: 390625
9230 11:19:32.994169 Bus Width = 1
9231 11:19:32.997694 sclk: 390625
9232 11:19:32.997782 Bus Width = 1
9233 11:19:33.000950 Early init status = 3
9234 11:19:33.003963 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9235 11:19:33.008055 in-header: 03 fc 00 00 01 00 00 00
9236 11:19:33.011524 in-data: 00
9237 11:19:33.014967 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9238 11:19:33.020734 in-header: 03 fd 00 00 00 00 00 00
9239 11:19:33.024215 in-data:
9240 11:19:33.027097 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9241 11:19:33.031734 in-header: 03 fc 00 00 01 00 00 00
9242 11:19:33.034709 in-data: 00
9243 11:19:33.037883 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9244 11:19:33.043519 in-header: 03 fd 00 00 00 00 00 00
9245 11:19:33.047052 in-data:
9246 11:19:33.050341 [SSUSB] Setting up USB HOST controller...
9247 11:19:33.053883 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9248 11:19:33.056820 [SSUSB] phy power-on done.
9249 11:19:33.060361 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9250 11:19:33.066684 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9251 11:19:33.070179 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9252 11:19:33.076585 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9253 11:19:33.083199 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9254 11:19:33.090308 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9255 11:19:33.096512 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9256 11:19:33.102793 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9257 11:19:33.106566 SPM: binary array size = 0x9dc
9258 11:19:33.109463 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9259 11:19:33.115947 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9260 11:19:33.122823 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9261 11:19:33.129211 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9262 11:19:33.132665 configure_display: Starting display init
9263 11:19:33.167013 anx7625_power_on_init: Init interface.
9264 11:19:33.169969 anx7625_disable_pd_protocol: Disabled PD feature.
9265 11:19:33.173602 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9266 11:19:33.201214 anx7625_start_dp_work: Secure OCM version=00
9267 11:19:33.204746 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9268 11:19:33.219533 sp_tx_get_edid_block: EDID Block = 1
9269 11:19:33.322454 Extracted contents:
9270 11:19:33.325073 header: 00 ff ff ff ff ff ff 00
9271 11:19:33.328321 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9272 11:19:33.331961 version: 01 04
9273 11:19:33.335263 basic params: 95 1f 11 78 0a
9274 11:19:33.338748 chroma info: 76 90 94 55 54 90 27 21 50 54
9275 11:19:33.341932 established: 00 00 00
9276 11:19:33.348671 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9277 11:19:33.351404 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9278 11:19:33.358437 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9279 11:19:33.364872 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9280 11:19:33.371665 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9281 11:19:33.375169 extensions: 00
9282 11:19:33.375266 checksum: fb
9283 11:19:33.375331
9284 11:19:33.381483 Manufacturer: IVO Model 57d Serial Number 0
9285 11:19:33.381587 Made week 0 of 2020
9286 11:19:33.384349 EDID version: 1.4
9287 11:19:33.384436 Digital display
9288 11:19:33.387653 6 bits per primary color channel
9289 11:19:33.387743 DisplayPort interface
9290 11:19:33.391424 Maximum image size: 31 cm x 17 cm
9291 11:19:33.394173 Gamma: 220%
9292 11:19:33.394262 Check DPMS levels
9293 11:19:33.401113 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9294 11:19:33.404549 First detailed timing is preferred timing
9295 11:19:33.407931 Established timings supported:
9296 11:19:33.408018 Standard timings supported:
9297 11:19:33.411020 Detailed timings
9298 11:19:33.414150 Hex of detail: 383680a07038204018303c0035ae10000019
9299 11:19:33.420846 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9300 11:19:33.424074 0780 0798 07c8 0820 hborder 0
9301 11:19:33.427290 0438 043b 0447 0458 vborder 0
9302 11:19:33.430433 -hsync -vsync
9303 11:19:33.430521 Did detailed timing
9304 11:19:33.437212 Hex of detail: 000000000000000000000000000000000000
9305 11:19:33.440916 Manufacturer-specified data, tag 0
9306 11:19:33.443667 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9307 11:19:33.447208 ASCII string: InfoVision
9308 11:19:33.450545 Hex of detail: 000000fe00523134304e574635205248200a
9309 11:19:33.453429 ASCII string: R140NWF5 RH
9310 11:19:33.453520 Checksum
9311 11:19:33.457114 Checksum: 0xfb (valid)
9312 11:19:33.460497 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9313 11:19:33.463450 DSI data_rate: 832800000 bps
9314 11:19:33.469969 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9315 11:19:33.473347 anx7625_parse_edid: pixelclock(138800).
9316 11:19:33.476441 hactive(1920), hsync(48), hfp(24), hbp(88)
9317 11:19:33.480038 vactive(1080), vsync(12), vfp(3), vbp(17)
9318 11:19:33.482939 anx7625_dsi_config: config dsi.
9319 11:19:33.489904 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9320 11:19:33.504453 anx7625_dsi_config: success to config DSI
9321 11:19:33.507154 anx7625_dp_start: MIPI phy setup OK.
9322 11:19:33.510824 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9323 11:19:33.513877 mtk_ddp_mode_set invalid vrefresh 60
9324 11:19:33.517270 main_disp_path_setup
9325 11:19:33.517358 ovl_layer_smi_id_en
9326 11:19:33.520731 ovl_layer_smi_id_en
9327 11:19:33.520815 ccorr_config
9328 11:19:33.520879 aal_config
9329 11:19:33.523677 gamma_config
9330 11:19:33.523761 postmask_config
9331 11:19:33.527110 dither_config
9332 11:19:33.530398 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9333 11:19:33.537116 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9334 11:19:33.540102 Root Device init finished in 555 msecs
9335 11:19:33.543967 CPU_CLUSTER: 0 init
9336 11:19:33.550527 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9337 11:19:33.557022 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9338 11:19:33.557146 APU_MBOX 0x190000b0 = 0x10001
9339 11:19:33.559907 APU_MBOX 0x190001b0 = 0x10001
9340 11:19:33.563505 APU_MBOX 0x190005b0 = 0x10001
9341 11:19:33.566775 APU_MBOX 0x190006b0 = 0x10001
9342 11:19:33.573113 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9343 11:19:33.583287 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9344 11:19:33.595734 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9345 11:19:33.602079 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9346 11:19:33.613500 read SPI 0x61c74 0xe8ef: 6410 us, 9302 KB/s, 74.416 Mbps
9347 11:19:33.622983 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9348 11:19:33.626053 CPU_CLUSTER: 0 init finished in 81 msecs
9349 11:19:33.629317 Devices initialized
9350 11:19:33.633074 Show all devs... After init.
9351 11:19:33.633265 Root Device: enabled 1
9352 11:19:33.635862 CPU_CLUSTER: 0: enabled 1
9353 11:19:33.639202 CPU: 00: enabled 1
9354 11:19:33.642444 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9355 11:19:33.645653 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9356 11:19:33.649207 ELOG: NV offset 0x57f000 size 0x1000
9357 11:19:33.655709 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9358 11:19:33.662519 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9359 11:19:33.665841 ELOG: Event(17) added with size 13 at 2023-06-05 11:19:33 UTC
9360 11:19:33.672104 out: cmd=0x121: 03 db 21 01 00 00 00 00
9361 11:19:33.675689 in-header: 03 78 00 00 2c 00 00 00
9362 11:19:33.685462 in-data: e7 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9363 11:19:33.692279 ELOG: Event(A1) added with size 10 at 2023-06-05 11:19:33 UTC
9364 11:19:33.698457 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9365 11:19:33.705276 ELOG: Event(A0) added with size 9 at 2023-06-05 11:19:33 UTC
9366 11:19:33.708434 elog_add_boot_reason: Logged dev mode boot
9367 11:19:33.715526 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9368 11:19:33.715724 Finalize devices...
9369 11:19:33.718611 Devices finalized
9370 11:19:33.721747 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9371 11:19:33.725000 Writing coreboot table at 0xffe64000
9372 11:19:33.728511 0. 000000000010a000-0000000000113fff: RAMSTAGE
9373 11:19:33.734849 1. 0000000040000000-00000000400fffff: RAM
9374 11:19:33.738320 2. 0000000040100000-000000004032afff: RAMSTAGE
9375 11:19:33.741550 3. 000000004032b000-00000000545fffff: RAM
9376 11:19:33.745038 4. 0000000054600000-000000005465ffff: BL31
9377 11:19:33.748468 5. 0000000054660000-00000000ffe63fff: RAM
9378 11:19:33.754754 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9379 11:19:33.757886 7. 0000000100000000-000000023fffffff: RAM
9380 11:19:33.761510 Passing 5 GPIOs to payload:
9381 11:19:33.764819 NAME | PORT | POLARITY | VALUE
9382 11:19:33.771256 EC in RW | 0x000000aa | low | undefined
9383 11:19:33.774326 EC interrupt | 0x00000005 | low | undefined
9384 11:19:33.777845 TPM interrupt | 0x000000ab | high | undefined
9385 11:19:33.784260 SD card detect | 0x00000011 | high | undefined
9386 11:19:33.787813 speaker enable | 0x00000093 | high | undefined
9387 11:19:33.791145 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9388 11:19:33.794493 in-header: 03 f9 00 00 02 00 00 00
9389 11:19:33.797480 in-data: 02 00
9390 11:19:33.800852 ADC[4]: Raw value=896670 ID=7
9391 11:19:33.804227 ADC[3]: Raw value=212700 ID=1
9392 11:19:33.804375 RAM Code: 0x71
9393 11:19:33.807954 ADC[6]: Raw value=74352 ID=0
9394 11:19:33.810577 ADC[5]: Raw value=211960 ID=1
9395 11:19:33.810721 SKU Code: 0x1
9396 11:19:33.817406 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum 7dbf
9397 11:19:33.817641 coreboot table: 964 bytes.
9398 11:19:33.820759 IMD ROOT 0. 0xfffff000 0x00001000
9399 11:19:33.824203 IMD SMALL 1. 0xffffe000 0x00001000
9400 11:19:33.827237 RO MCACHE 2. 0xffffc000 0x00001104
9401 11:19:33.830770 CONSOLE 3. 0xfff7c000 0x00080000
9402 11:19:33.834003 FMAP 4. 0xfff7b000 0x00000452
9403 11:19:33.836896 TIME STAMP 5. 0xfff7a000 0x00000910
9404 11:19:33.840291 VBOOT WORK 6. 0xfff66000 0x00014000
9405 11:19:33.843731 RAMOOPS 7. 0xffe66000 0x00100000
9406 11:19:33.847093 COREBOOT 8. 0xffe64000 0x00002000
9407 11:19:33.850290 IMD small region:
9408 11:19:33.853335 IMD ROOT 0. 0xffffec00 0x00000400
9409 11:19:33.856564 VPD 1. 0xffffeba0 0x0000004c
9410 11:19:33.859899 MMC STATUS 2. 0xffffeb80 0x00000004
9411 11:19:33.866978 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9412 11:19:33.867144 Probing TPM: done!
9413 11:19:33.873240 Connected to device vid:did:rid of 1ae0:0028:00
9414 11:19:33.879976 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9415 11:19:33.883557 Initialized TPM device CR50 revision 0
9416 11:19:33.887127 Checking cr50 for pending updates
9417 11:19:33.892362 Reading cr50 TPM mode
9418 11:19:33.900809 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9419 11:19:33.907567 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9420 11:19:33.947750 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9421 11:19:33.951146 Checking segment from ROM address 0x40100000
9422 11:19:33.954124 Checking segment from ROM address 0x4010001c
9423 11:19:33.960737 Loading segment from ROM address 0x40100000
9424 11:19:33.960883 code (compression=0)
9425 11:19:33.971056 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9426 11:19:33.977282 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9427 11:19:33.977454 it's not compressed!
9428 11:19:33.983836 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9429 11:19:33.990650 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9430 11:19:34.008392 Loading segment from ROM address 0x4010001c
9431 11:19:34.008544 Entry Point 0x80000000
9432 11:19:34.011114 Loaded segments
9433 11:19:34.014622 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9434 11:19:34.021510 Jumping to boot code at 0x80000000(0xffe64000)
9435 11:19:34.027757 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9436 11:19:34.034430 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9437 11:19:34.042535 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9438 11:19:34.045803 Checking segment from ROM address 0x40100000
9439 11:19:34.049266 Checking segment from ROM address 0x4010001c
9440 11:19:34.056236 Loading segment from ROM address 0x40100000
9441 11:19:34.056364 code (compression=1)
9442 11:19:34.062546 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9443 11:19:34.072230 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9444 11:19:34.072377 using LZMA
9445 11:19:34.080801 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9446 11:19:34.087485 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9447 11:19:34.091081 Loading segment from ROM address 0x4010001c
9448 11:19:34.091198 Entry Point 0x54601000
9449 11:19:34.093909 Loaded segments
9450 11:19:34.097552 NOTICE: MT8192 bl31_setup
9451 11:19:34.104558 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9452 11:19:34.107885 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9453 11:19:34.111282 WARNING: region 0:
9454 11:19:34.114357 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9455 11:19:34.114452 WARNING: region 1:
9456 11:19:34.121059 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9457 11:19:34.124534 WARNING: region 2:
9458 11:19:34.128027 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9459 11:19:34.130930 WARNING: region 3:
9460 11:19:34.134480 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9461 11:19:34.137857 WARNING: region 4:
9462 11:19:34.144241 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9463 11:19:34.144360 WARNING: region 5:
9464 11:19:34.147477 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9465 11:19:34.151362 WARNING: region 6:
9466 11:19:34.154333 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9467 11:19:34.157551 WARNING: region 7:
9468 11:19:34.160986 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9469 11:19:34.167933 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9470 11:19:34.170811 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9471 11:19:34.174655 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9472 11:19:34.180729 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9473 11:19:34.184018 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9474 11:19:34.187741 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9475 11:19:34.194353 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9476 11:19:34.197463 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9477 11:19:34.203959 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9478 11:19:34.207459 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9479 11:19:34.210987 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9480 11:19:34.217415 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9481 11:19:34.220897 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9482 11:19:34.227291 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9483 11:19:34.230788 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9484 11:19:34.234049 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9485 11:19:34.240268 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9486 11:19:34.243774 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9487 11:19:34.247580 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9488 11:19:34.254017 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9489 11:19:34.257272 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9490 11:19:34.263625 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9491 11:19:34.267130 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9492 11:19:34.270059 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9493 11:19:34.276659 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9494 11:19:34.280110 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9495 11:19:34.286725 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9496 11:19:34.289888 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9497 11:19:34.296582 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9498 11:19:34.299681 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9499 11:19:34.303542 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9500 11:19:34.309680 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9501 11:19:34.313158 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9502 11:19:34.316610 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9503 11:19:34.319738 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9504 11:19:34.326541 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9505 11:19:34.330005 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9506 11:19:34.333246 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9507 11:19:34.336545 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9508 11:19:34.343446 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9509 11:19:34.346559 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9510 11:19:34.349777 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9511 11:19:34.352790 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9512 11:19:34.359560 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9513 11:19:34.362816 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9514 11:19:34.365983 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9515 11:19:34.372959 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9516 11:19:34.376410 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9517 11:19:34.379544 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9518 11:19:34.385863 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9519 11:19:34.389252 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9520 11:19:34.395811 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9521 11:19:34.399566 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9522 11:19:34.402865 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9523 11:19:34.409605 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9524 11:19:34.412419 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9525 11:19:34.418869 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9526 11:19:34.422463 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9527 11:19:34.428860 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9528 11:19:34.432166 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9529 11:19:34.436091 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9530 11:19:34.442489 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9531 11:19:34.445815 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9532 11:19:34.452514 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9533 11:19:34.456021 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9534 11:19:34.462730 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9535 11:19:34.465878 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9536 11:19:34.472085 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9537 11:19:34.476085 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9538 11:19:34.478713 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9539 11:19:34.485783 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9540 11:19:34.489058 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9541 11:19:34.495538 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9542 11:19:34.498680 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9543 11:19:34.505497 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9544 11:19:34.508653 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9545 11:19:34.515677 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9546 11:19:34.518489 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9547 11:19:34.522005 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9548 11:19:34.528443 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9549 11:19:34.531901 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9550 11:19:34.538231 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9551 11:19:34.541969 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9552 11:19:34.548704 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9553 11:19:34.551473 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9554 11:19:34.558069 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9555 11:19:34.561599 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9556 11:19:34.565098 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9557 11:19:34.571334 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9558 11:19:34.574717 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9559 11:19:34.581665 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9560 11:19:34.584948 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9561 11:19:34.591760 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9562 11:19:34.594869 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9563 11:19:34.601286 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9564 11:19:34.604824 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9565 11:19:34.607921 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9566 11:19:34.611066 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9567 11:19:34.617721 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9568 11:19:34.621436 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9569 11:19:34.624587 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9570 11:19:34.630866 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9571 11:19:34.634373 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9572 11:19:34.641343 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9573 11:19:34.644599 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9574 11:19:34.647586 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9575 11:19:34.654378 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9576 11:19:34.657812 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9577 11:19:34.664015 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9578 11:19:34.667536 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9579 11:19:34.670640 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9580 11:19:34.677363 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9581 11:19:34.680567 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9582 11:19:34.687412 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9583 11:19:34.690693 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9584 11:19:34.693927 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9585 11:19:34.697523 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9586 11:19:34.703960 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9587 11:19:34.707393 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9588 11:19:34.710733 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9589 11:19:34.717347 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9590 11:19:34.720519 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9591 11:19:34.723694 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9592 11:19:34.730216 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9593 11:19:34.733524 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9594 11:19:34.737035 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9595 11:19:34.743425 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9596 11:19:34.746801 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9597 11:19:34.753513 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9598 11:19:34.756879 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9599 11:19:34.760424 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9600 11:19:34.767092 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9601 11:19:34.770257 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9602 11:19:34.773681 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9603 11:19:34.779962 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9604 11:19:34.783757 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9605 11:19:34.789924 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9606 11:19:34.793351 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9607 11:19:34.796770 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9608 11:19:34.803448 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9609 11:19:34.806554 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9610 11:19:34.813337 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9611 11:19:34.816586 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9612 11:19:34.819943 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9613 11:19:34.826271 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9614 11:19:34.830052 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9615 11:19:34.836299 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9616 11:19:34.839945 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9617 11:19:34.842934 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9618 11:19:34.850012 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9619 11:19:34.853159 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9620 11:19:34.856413 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9621 11:19:34.862808 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9622 11:19:34.866479 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9623 11:19:34.872893 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9624 11:19:34.876297 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9625 11:19:34.882538 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9626 11:19:34.886239 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9627 11:19:34.889612 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9628 11:19:34.895975 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9629 11:19:34.899278 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9630 11:19:34.902456 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9631 11:19:34.909133 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9632 11:19:34.912639 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9633 11:19:34.919061 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9634 11:19:34.922345 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9635 11:19:34.925396 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9636 11:19:34.932026 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9637 11:19:34.935379 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9638 11:19:34.942371 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9639 11:19:34.945425 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9640 11:19:34.951802 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9641 11:19:34.955065 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9642 11:19:34.958344 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9643 11:19:34.965399 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9644 11:19:34.968244 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9645 11:19:34.975044 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9646 11:19:34.978430 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9647 11:19:34.981270 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9648 11:19:34.988016 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9649 11:19:34.991187 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9650 11:19:34.997992 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9651 11:19:35.001520 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9652 11:19:35.004251 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9653 11:19:35.011342 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9654 11:19:35.014288 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9655 11:19:35.021136 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9656 11:19:35.024434 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9657 11:19:35.027277 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9658 11:19:35.034084 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9659 11:19:35.037461 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9660 11:19:35.043886 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9661 11:19:35.047711 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9662 11:19:35.050649 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9663 11:19:35.057124 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9664 11:19:35.060583 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9665 11:19:35.067106 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9666 11:19:35.070781 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9667 11:19:35.076985 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9668 11:19:35.080398 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9669 11:19:35.083776 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9670 11:19:35.090526 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9671 11:19:35.094115 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9672 11:19:35.100105 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9673 11:19:35.103430 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9674 11:19:35.110011 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9675 11:19:35.113336 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9676 11:19:35.116485 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9677 11:19:35.123259 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9678 11:19:35.126671 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9679 11:19:35.133460 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9680 11:19:35.136463 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9681 11:19:35.143117 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9682 11:19:35.146602 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9683 11:19:35.150001 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9684 11:19:35.156469 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9685 11:19:35.160176 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9686 11:19:35.166157 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9687 11:19:35.169828 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9688 11:19:35.176172 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9689 11:19:35.179687 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9690 11:19:35.182527 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9691 11:19:35.189559 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9692 11:19:35.192841 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9693 11:19:35.199428 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9694 11:19:35.202497 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9695 11:19:35.208873 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9696 11:19:35.212057 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9697 11:19:35.215694 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9698 11:19:35.221993 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9699 11:19:35.225230 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9700 11:19:35.228782 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9701 11:19:35.232155 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9702 11:19:35.238983 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9703 11:19:35.241720 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9704 11:19:35.245228 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9705 11:19:35.251575 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9706 11:19:35.255001 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9707 11:19:35.258718 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9708 11:19:35.264984 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9709 11:19:35.268021 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9710 11:19:35.274755 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9711 11:19:35.277872 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9712 11:19:35.281340 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9713 11:19:35.288073 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9714 11:19:35.291133 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9715 11:19:35.297739 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9716 11:19:35.301167 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9717 11:19:35.304819 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9718 11:19:35.311083 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9719 11:19:35.314292 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9720 11:19:35.320670 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9721 11:19:35.323793 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9722 11:19:35.327036 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9723 11:19:35.333607 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9724 11:19:35.337025 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9725 11:19:35.340334 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9726 11:19:35.346659 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9727 11:19:35.350029 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9728 11:19:35.356413 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9729 11:19:35.359892 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9730 11:19:35.363405 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9731 11:19:35.369723 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9732 11:19:35.372953 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9733 11:19:35.376186 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9734 11:19:35.382447 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9735 11:19:35.386177 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9736 11:19:35.393018 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9737 11:19:35.395767 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9738 11:19:35.399315 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9739 11:19:35.402796 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9740 11:19:35.409255 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9741 11:19:35.412382 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9742 11:19:35.415465 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9743 11:19:35.418701 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9744 11:19:35.425569 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9745 11:19:35.428740 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9746 11:19:35.432106 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9747 11:19:35.435428 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9748 11:19:35.441877 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9749 11:19:35.445438 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9750 11:19:35.448518 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9751 11:19:35.455404 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9752 11:19:35.458699 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9753 11:19:35.464963 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9754 11:19:35.468503 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9755 11:19:35.474804 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9756 11:19:35.477976 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9757 11:19:35.481434 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9758 11:19:35.488025 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9759 11:19:35.491170 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9760 11:19:35.497783 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9761 11:19:35.501312 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9762 11:19:35.504239 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9763 11:19:35.511227 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9764 11:19:35.514454 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9765 11:19:35.521192 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9766 11:19:35.524490 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9767 11:19:35.530750 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9768 11:19:35.533890 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9769 11:19:35.537359 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9770 11:19:35.543997 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9771 11:19:35.547386 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9772 11:19:35.554153 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9773 11:19:35.557052 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9774 11:19:35.560462 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9775 11:19:35.567478 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9776 11:19:35.570398 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9777 11:19:35.577624 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9778 11:19:35.580581 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9779 11:19:35.586784 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9780 11:19:35.590281 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9781 11:19:35.593648 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9782 11:19:35.600328 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9783 11:19:35.603592 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9784 11:19:35.609773 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9785 11:19:35.613191 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9786 11:19:35.620235 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9787 11:19:35.623363 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9788 11:19:35.626292 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9789 11:19:35.633041 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9790 11:19:35.636759 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9791 11:19:35.642668 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9792 11:19:35.646771 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9793 11:19:35.649615 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9794 11:19:35.656307 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9795 11:19:35.659820 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9796 11:19:35.666046 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9797 11:19:35.669623 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9798 11:19:35.672406 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9799 11:19:35.679329 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9800 11:19:35.682726 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9801 11:19:35.688900 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9802 11:19:35.692325 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9803 11:19:35.698902 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9804 11:19:35.702097 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9805 11:19:35.705635 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9806 11:19:35.712695 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9807 11:19:35.715254 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9808 11:19:35.722460 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9809 11:19:35.725158 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9810 11:19:35.731903 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9811 11:19:35.735369 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9812 11:19:35.738491 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9813 11:19:35.744957 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9814 11:19:35.748124 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9815 11:19:35.755116 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9816 11:19:35.757984 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9817 11:19:35.761182 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9818 11:19:35.767852 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9819 11:19:35.771313 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9820 11:19:35.778212 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9821 11:19:35.781519 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9822 11:19:35.784605 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9823 11:19:35.791279 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9824 11:19:35.794276 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9825 11:19:35.801067 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9826 11:19:35.804578 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9827 11:19:35.810798 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9828 11:19:35.814883 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9829 11:19:35.821233 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9830 11:19:35.824155 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9831 11:19:35.827602 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9832 11:19:35.834400 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9833 11:19:35.837330 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9834 11:19:35.844491 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9835 11:19:35.847507 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9836 11:19:35.853800 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9837 11:19:35.857004 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9838 11:19:35.863683 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9839 11:19:35.866790 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9840 11:19:35.873438 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9841 11:19:35.877000 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9842 11:19:35.880453 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9843 11:19:35.886704 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9844 11:19:35.890153 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9845 11:19:35.896498 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9846 11:19:35.899793 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9847 11:19:35.906628 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9848 11:19:35.909864 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9849 11:19:35.916480 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9850 11:19:35.920072 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9851 11:19:35.922795 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9852 11:19:35.929560 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9853 11:19:35.933265 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9854 11:19:35.939601 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9855 11:19:35.942602 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9856 11:19:35.949409 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9857 11:19:35.952552 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9858 11:19:35.958848 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9859 11:19:35.962193 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9860 11:19:35.968808 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9861 11:19:35.972610 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9862 11:19:35.975784 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9863 11:19:35.981956 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9864 11:19:35.985527 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9865 11:19:35.992141 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9866 11:19:35.995237 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9867 11:19:36.001959 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9868 11:19:36.005486 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9869 11:19:36.011889 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9870 11:19:36.015098 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9871 11:19:36.018563 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9872 11:19:36.025189 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9873 11:19:36.028612 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9874 11:19:36.035193 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9875 11:19:36.038150 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9876 11:19:36.045009 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9877 11:19:36.048093 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9878 11:19:36.054437 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9879 11:19:36.057679 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9880 11:19:36.064466 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9881 11:19:36.067743 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9882 11:19:36.074482 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9883 11:19:36.077552 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9884 11:19:36.084391 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9885 11:19:36.087385 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9886 11:19:36.094332 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9887 11:19:36.097584 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9888 11:19:36.103764 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9889 11:19:36.107218 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9890 11:19:36.110714 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9891 11:19:36.117161 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9892 11:19:36.123381 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9893 11:19:36.126814 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9894 11:19:36.133753 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9895 11:19:36.137181 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9896 11:19:36.143557 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9897 11:19:36.146500 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9898 11:19:36.153214 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9899 11:19:36.156746 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9900 11:19:36.162981 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9901 11:19:36.166811 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9902 11:19:36.173030 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9903 11:19:36.176639 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9904 11:19:36.179557 INFO: [APUAPC] vio 0
9905 11:19:36.182646 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9906 11:19:36.189348 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9907 11:19:36.192705 INFO: [APUAPC] D0_APC_0: 0x400510
9908 11:19:36.192800 INFO: [APUAPC] D0_APC_1: 0x0
9909 11:19:36.196214 INFO: [APUAPC] D0_APC_2: 0x1540
9910 11:19:36.199188 INFO: [APUAPC] D0_APC_3: 0x0
9911 11:19:36.202636 INFO: [APUAPC] D1_APC_0: 0xffffffff
9912 11:19:36.205933 INFO: [APUAPC] D1_APC_1: 0xffffffff
9913 11:19:36.209292 INFO: [APUAPC] D1_APC_2: 0x3fffff
9914 11:19:36.212211 INFO: [APUAPC] D1_APC_3: 0x0
9915 11:19:36.215797 INFO: [APUAPC] D2_APC_0: 0xffffffff
9916 11:19:36.219266 INFO: [APUAPC] D2_APC_1: 0xffffffff
9917 11:19:36.222262 INFO: [APUAPC] D2_APC_2: 0x3fffff
9918 11:19:36.225407 INFO: [APUAPC] D2_APC_3: 0x0
9919 11:19:36.229057 INFO: [APUAPC] D3_APC_0: 0xffffffff
9920 11:19:36.232107 INFO: [APUAPC] D3_APC_1: 0xffffffff
9921 11:19:36.235497 INFO: [APUAPC] D3_APC_2: 0x3fffff
9922 11:19:36.238850 INFO: [APUAPC] D3_APC_3: 0x0
9923 11:19:36.241868 INFO: [APUAPC] D4_APC_0: 0xffffffff
9924 11:19:36.245305 INFO: [APUAPC] D4_APC_1: 0xffffffff
9925 11:19:36.248690 INFO: [APUAPC] D4_APC_2: 0x3fffff
9926 11:19:36.251893 INFO: [APUAPC] D4_APC_3: 0x0
9927 11:19:36.255120 INFO: [APUAPC] D5_APC_0: 0xffffffff
9928 11:19:36.258329 INFO: [APUAPC] D5_APC_1: 0xffffffff
9929 11:19:36.261908 INFO: [APUAPC] D5_APC_2: 0x3fffff
9930 11:19:36.265303 INFO: [APUAPC] D5_APC_3: 0x0
9931 11:19:36.268456 INFO: [APUAPC] D6_APC_0: 0xffffffff
9932 11:19:36.271369 INFO: [APUAPC] D6_APC_1: 0xffffffff
9933 11:19:36.275203 INFO: [APUAPC] D6_APC_2: 0x3fffff
9934 11:19:36.278599 INFO: [APUAPC] D6_APC_3: 0x0
9935 11:19:36.281781 INFO: [APUAPC] D7_APC_0: 0xffffffff
9936 11:19:36.285094 INFO: [APUAPC] D7_APC_1: 0xffffffff
9937 11:19:36.288221 INFO: [APUAPC] D7_APC_2: 0x3fffff
9938 11:19:36.291353 INFO: [APUAPC] D7_APC_3: 0x0
9939 11:19:36.294973 INFO: [APUAPC] D8_APC_0: 0xffffffff
9940 11:19:36.298199 INFO: [APUAPC] D8_APC_1: 0xffffffff
9941 11:19:36.301644 INFO: [APUAPC] D8_APC_2: 0x3fffff
9942 11:19:36.305014 INFO: [APUAPC] D8_APC_3: 0x0
9943 11:19:36.307902 INFO: [APUAPC] D9_APC_0: 0xffffffff
9944 11:19:36.311229 INFO: [APUAPC] D9_APC_1: 0xffffffff
9945 11:19:36.314363 INFO: [APUAPC] D9_APC_2: 0x3fffff
9946 11:19:36.317591 INFO: [APUAPC] D9_APC_3: 0x0
9947 11:19:36.321027 INFO: [APUAPC] D10_APC_0: 0xffffffff
9948 11:19:36.324541 INFO: [APUAPC] D10_APC_1: 0xffffffff
9949 11:19:36.327418 INFO: [APUAPC] D10_APC_2: 0x3fffff
9950 11:19:36.331125 INFO: [APUAPC] D10_APC_3: 0x0
9951 11:19:36.334061 INFO: [APUAPC] D11_APC_0: 0xffffffff
9952 11:19:36.337520 INFO: [APUAPC] D11_APC_1: 0xffffffff
9953 11:19:36.340693 INFO: [APUAPC] D11_APC_2: 0x3fffff
9954 11:19:36.344324 INFO: [APUAPC] D11_APC_3: 0x0
9955 11:19:36.347064 INFO: [APUAPC] D12_APC_0: 0xffffffff
9956 11:19:36.350414 INFO: [APUAPC] D12_APC_1: 0xffffffff
9957 11:19:36.353867 INFO: [APUAPC] D12_APC_2: 0x3fffff
9958 11:19:36.357205 INFO: [APUAPC] D12_APC_3: 0x0
9959 11:19:36.360120 INFO: [APUAPC] D13_APC_0: 0xffffffff
9960 11:19:36.363883 INFO: [APUAPC] D13_APC_1: 0xffffffff
9961 11:19:36.366764 INFO: [APUAPC] D13_APC_2: 0x3fffff
9962 11:19:36.370254 INFO: [APUAPC] D13_APC_3: 0x0
9963 11:19:36.373764 INFO: [APUAPC] D14_APC_0: 0xffffffff
9964 11:19:36.376742 INFO: [APUAPC] D14_APC_1: 0xffffffff
9965 11:19:36.380096 INFO: [APUAPC] D14_APC_2: 0x3fffff
9966 11:19:36.383152 INFO: [APUAPC] D14_APC_3: 0x0
9967 11:19:36.386627 INFO: [APUAPC] D15_APC_0: 0xffffffff
9968 11:19:36.389875 INFO: [APUAPC] D15_APC_1: 0xffffffff
9969 11:19:36.393407 INFO: [APUAPC] D15_APC_2: 0x3fffff
9970 11:19:36.396262 INFO: [APUAPC] D15_APC_3: 0x0
9971 11:19:36.400220 INFO: [APUAPC] APC_CON: 0x4
9972 11:19:36.403093 INFO: [NOCDAPC] D0_APC_0: 0x0
9973 11:19:36.406309 INFO: [NOCDAPC] D0_APC_1: 0x0
9974 11:19:36.409569 INFO: [NOCDAPC] D1_APC_0: 0x0
9975 11:19:36.412932 INFO: [NOCDAPC] D1_APC_1: 0xfff
9976 11:19:36.416421 INFO: [NOCDAPC] D2_APC_0: 0x0
9977 11:19:36.419293 INFO: [NOCDAPC] D2_APC_1: 0xfff
9978 11:19:36.419382 INFO: [NOCDAPC] D3_APC_0: 0x0
9979 11:19:36.423024 INFO: [NOCDAPC] D3_APC_1: 0xfff
9980 11:19:36.426415 INFO: [NOCDAPC] D4_APC_0: 0x0
9981 11:19:36.429509 INFO: [NOCDAPC] D4_APC_1: 0xfff
9982 11:19:36.432839 INFO: [NOCDAPC] D5_APC_0: 0x0
9983 11:19:36.435873 INFO: [NOCDAPC] D5_APC_1: 0xfff
9984 11:19:36.439512 INFO: [NOCDAPC] D6_APC_0: 0x0
9985 11:19:36.442532 INFO: [NOCDAPC] D6_APC_1: 0xfff
9986 11:19:36.445575 INFO: [NOCDAPC] D7_APC_0: 0x0
9987 11:19:36.448876 INFO: [NOCDAPC] D7_APC_1: 0xfff
9988 11:19:36.452431 INFO: [NOCDAPC] D8_APC_0: 0x0
9989 11:19:36.455727 INFO: [NOCDAPC] D8_APC_1: 0xfff
9990 11:19:36.455837 INFO: [NOCDAPC] D9_APC_0: 0x0
9991 11:19:36.458798 INFO: [NOCDAPC] D9_APC_1: 0xfff
9992 11:19:36.462365 INFO: [NOCDAPC] D10_APC_0: 0x0
9993 11:19:36.465239 INFO: [NOCDAPC] D10_APC_1: 0xfff
9994 11:19:36.468562 INFO: [NOCDAPC] D11_APC_0: 0x0
9995 11:19:36.471896 INFO: [NOCDAPC] D11_APC_1: 0xfff
9996 11:19:36.475359 INFO: [NOCDAPC] D12_APC_0: 0x0
9997 11:19:36.478808 INFO: [NOCDAPC] D12_APC_1: 0xfff
9998 11:19:36.482215 INFO: [NOCDAPC] D13_APC_0: 0x0
9999 11:19:36.485771 INFO: [NOCDAPC] D13_APC_1: 0xfff
10000 11:19:36.488670 INFO: [NOCDAPC] D14_APC_0: 0x0
10001 11:19:36.491828 INFO: [NOCDAPC] D14_APC_1: 0xfff
10002 11:19:36.495008 INFO: [NOCDAPC] D15_APC_0: 0x0
10003 11:19:36.498563 INFO: [NOCDAPC] D15_APC_1: 0xfff
10004 11:19:36.501747 INFO: [NOCDAPC] APC_CON: 0x4
10005 11:19:36.505051 INFO: [APUAPC] set_apusys_apc done
10006 11:19:36.508283 INFO: [DEVAPC] devapc_init done
10007 11:19:36.511877 INFO: GICv3 without legacy support detected.
10008 11:19:36.515004 INFO: ARM GICv3 driver initialized in EL3
10009 11:19:36.518091 INFO: Maximum SPI INTID supported: 639
10010 11:19:36.521496 INFO: BL31: Initializing runtime services
10011 11:19:36.527842 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10012 11:19:36.531356 INFO: SPM: enable CPC mode
10013 11:19:36.537855 INFO: mcdi ready for mcusys-off-idle and system suspend
10014 11:19:36.541411 INFO: BL31: Preparing for EL3 exit to normal world
10015 11:19:36.544583 INFO: Entry point address = 0x80000000
10016 11:19:36.547913 INFO: SPSR = 0x8
10017 11:19:36.552696
10018 11:19:36.552793
10019 11:19:36.552862
10020 11:19:36.555802 Starting depthcharge on Spherion...
10021 11:19:36.555923
10022 11:19:36.556013 Wipe memory regions:
10023 11:19:36.556129
10024 11:19:36.556802 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10025 11:19:36.556908 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10026 11:19:36.556996 Setting prompt string to ['asurada:']
10027 11:19:36.557076 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10028 11:19:36.559235 [0x00000040000000, 0x00000054600000)
10029 11:19:36.681380
10030 11:19:36.681534 [0x00000054660000, 0x00000080000000)
10031 11:19:36.941762
10032 11:19:36.941917 [0x000000821a7280, 0x000000ffe64000)
10033 11:19:37.686737
10034 11:19:37.686931 [0x00000100000000, 0x00000240000000)
10035 11:19:39.576568
10036 11:19:39.579671 Initializing XHCI USB controller at 0x11200000.
10037 11:19:40.617646
10038 11:19:40.620627 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10039 11:19:40.620716
10040 11:19:40.620782
10041 11:19:40.620843
10042 11:19:40.621155 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10044 11:19:40.721543 asurada: tftpboot 192.168.201.1 10591280/tftp-deploy-_r2evtbo/kernel/image.itb 10591280/tftp-deploy-_r2evtbo/kernel/cmdline
10045 11:19:40.721729 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10046 11:19:40.721828 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10047 11:19:40.726349 tftpboot 192.168.201.1 10591280/tftp-deploy-_r2evtbo/kernel/image.itp-deploy-_r2evtbo/kernel/cmdline
10048 11:19:40.726439
10049 11:19:40.726504 Waiting for link
10050 11:19:40.886702
10051 11:19:40.886922 R8152: Initializing
10052 11:19:40.887001
10053 11:19:40.889946 Version 6 (ocp_data = 5c30)
10054 11:19:40.890031
10055 11:19:40.893432 R8152: Done initializing
10056 11:19:40.893516
10057 11:19:40.893583 Adding net device
10058 11:19:42.906730
10059 11:19:42.906915 done.
10060 11:19:42.906988
10061 11:19:42.907051 MAC: 00:24:32:30:78:ff
10062 11:19:42.907112
10063 11:19:42.910167 Sending DHCP discover... done.
10064 11:19:42.910275
10065 11:19:42.913796 Waiting for reply... done.
10066 11:19:42.913906
10067 11:19:42.916753 Sending DHCP request... done.
10068 11:19:42.916856
10069 11:19:42.916925 Waiting for reply... done.
10070 11:19:42.920112
10071 11:19:42.920212 My ip is 192.168.201.21
10072 11:19:42.920281
10073 11:19:42.923451 The DHCP server ip is 192.168.201.1
10074 11:19:42.923557
10075 11:19:42.926776 TFTP server IP predefined by user: 192.168.201.1
10076 11:19:42.926926
10077 11:19:42.933298 Bootfile predefined by user: 10591280/tftp-deploy-_r2evtbo/kernel/image.itb
10078 11:19:42.933425
10079 11:19:42.936405 Sending tftp read request... done.
10080 11:19:42.936501
10081 11:19:42.939642 Waiting for the transfer...
10082 11:19:42.942793
10083 11:19:43.599375 00000000 ################################################################
10084 11:19:43.599529
10085 11:19:44.226760 00080000 ################################################################
10086 11:19:44.226943
10087 11:19:44.873126 00100000 ################################################################
10088 11:19:44.873294
10089 11:19:45.463733 00180000 ################################################################
10090 11:19:45.463878
10091 11:19:46.026676 00200000 ################################################################
10092 11:19:46.026870
10093 11:19:46.586108 00280000 ################################################################
10094 11:19:46.586261
10095 11:19:47.151006 00300000 ################################################################
10096 11:19:47.151582
10097 11:19:47.736430 00380000 ################################################################
10098 11:19:47.736573
10099 11:19:48.362108 00400000 ################################################################
10100 11:19:48.362659
10101 11:19:48.965095 00480000 ################################################################
10102 11:19:48.965247
10103 11:19:49.539188 00500000 ################################################################
10104 11:19:49.539695
10105 11:19:50.115976 00580000 ################################################################
10106 11:19:50.116117
10107 11:19:50.663394 00600000 ################################################################
10108 11:19:50.663528
10109 11:19:51.238329 00680000 ################################################################
10110 11:19:51.238989
10111 11:19:51.885800 00700000 ################################################################
10112 11:19:51.885955
10113 11:19:52.503559 00780000 ################################################################
10114 11:19:52.504234
10115 11:19:53.094735 00800000 ################################################################
10116 11:19:53.094879
10117 11:19:53.633068 00880000 ################################################################
10118 11:19:53.633209
10119 11:19:54.196690 00900000 ################################################################
10120 11:19:54.196828
10121 11:19:54.737674 00980000 ################################################################
10122 11:19:54.737850
10123 11:19:55.279600 00a00000 ################################################################
10124 11:19:55.279763
10125 11:19:55.824090 00a80000 ################################################################
10126 11:19:55.824249
10127 11:19:56.369190 00b00000 ################################################################
10128 11:19:56.369351
10129 11:19:56.913697 00b80000 ################################################################
10130 11:19:56.913868
10131 11:19:57.453121 00c00000 ################################################################
10132 11:19:57.453260
10133 11:19:57.999136 00c80000 ################################################################
10134 11:19:57.999269
10135 11:19:58.526557 00d00000 ################################################################
10136 11:19:58.526693
10137 11:19:59.056636 00d80000 ################################################################
10138 11:19:59.056782
10139 11:19:59.593907 00e00000 ################################################################
10140 11:19:59.594057
10141 11:20:00.121856 00e80000 ################################################################
10142 11:20:00.122006
10143 11:20:00.644410 00f00000 ################################################################
10144 11:20:00.644564
10145 11:20:01.171929 00f80000 ################################################################
10146 11:20:01.172064
10147 11:20:01.692963 01000000 ################################################################
10148 11:20:01.693099
10149 11:20:02.220825 01080000 ################################################################
10150 11:20:02.220970
10151 11:20:02.751148 01100000 ################################################################
10152 11:20:02.751291
10153 11:20:03.285942 01180000 ################################################################
10154 11:20:03.286077
10155 11:20:03.820785 01200000 ################################################################
10156 11:20:03.820969
10157 11:20:04.356940 01280000 ################################################################
10158 11:20:04.357081
10159 11:20:04.904087 01300000 ################################################################
10160 11:20:04.904225
10161 11:20:05.458291 01380000 ################################################################
10162 11:20:05.458460
10163 11:20:06.019985 01400000 ################################################################
10164 11:20:06.020129
10165 11:20:06.546552 01480000 ################################################################
10166 11:20:06.546696
10167 11:20:07.091580 01500000 ################################################################
10168 11:20:07.091729
10169 11:20:07.638592 01580000 ################################################################
10170 11:20:07.638745
10171 11:20:08.185139 01600000 ################################################################
10172 11:20:08.185290
10173 11:20:08.720095 01680000 ################################################################
10174 11:20:08.720261
10175 11:20:09.265262 01700000 ################################################################
10176 11:20:09.265401
10177 11:20:09.805203 01780000 ################################################################
10178 11:20:09.805346
10179 11:20:10.350684 01800000 ################################################################
10180 11:20:10.350878
10181 11:20:10.884204 01880000 ################################################################
10182 11:20:10.884358
10183 11:20:11.427681 01900000 ################################################################
10184 11:20:11.427830
10185 11:20:11.970931 01980000 ################################################################
10186 11:20:11.971080
10187 11:20:12.518325 01a00000 ################################################################
10188 11:20:12.518474
10189 11:20:13.082339 01a80000 ################################################################
10190 11:20:13.082475
10191 11:20:13.658995 01b00000 ################################################################
10192 11:20:13.659131
10193 11:20:14.217693 01b80000 ################################################################
10194 11:20:14.217830
10195 11:20:14.744431 01c00000 ################################################################
10196 11:20:14.744576
10197 11:20:15.282756 01c80000 ################################################################
10198 11:20:15.282953
10199 11:20:15.824690 01d00000 ################################################################
10200 11:20:15.824839
10201 11:20:16.346340 01d80000 ################################################################
10202 11:20:16.346506
10203 11:20:16.865071 01e00000 ################################################################
10204 11:20:16.865215
10205 11:20:17.416155 01e80000 ################################################################
10206 11:20:17.416293
10207 11:20:17.983474 01f00000 ################################################################
10208 11:20:17.983625
10209 11:20:18.543748 01f80000 ################################################################
10210 11:20:18.543920
10211 11:20:19.103518 02000000 ################################################################
10212 11:20:19.103670
10213 11:20:19.664530 02080000 ################################################################
10214 11:20:19.664674
10215 11:20:20.230111 02100000 ################################################################
10216 11:20:20.230247
10217 11:20:20.789337 02180000 ################################################################
10218 11:20:20.789484
10219 11:20:21.355739 02200000 ################################################################
10220 11:20:21.355890
10221 11:20:21.916287 02280000 ################################################################
10222 11:20:21.916434
10223 11:20:22.462567 02300000 ################################################################
10224 11:20:22.462749
10225 11:20:23.019991 02380000 ################################################################
10226 11:20:23.020135
10227 11:20:23.557304 02400000 ################################################################
10228 11:20:23.557452
10229 11:20:24.084037 02480000 ################################################################
10230 11:20:24.084192
10231 11:20:24.618523 02500000 ################################################################
10232 11:20:24.618671
10233 11:20:25.145066 02580000 ################################################################
10234 11:20:25.145226
10235 11:20:25.671970 02600000 ################################################################
10236 11:20:25.672122
10237 11:20:26.242685 02680000 ################################################################
10238 11:20:26.242907
10239 11:20:26.806343 02700000 ################################################################
10240 11:20:26.806541
10241 11:20:27.357694 02780000 ################################################################
10242 11:20:27.357844
10243 11:20:27.910039 02800000 ################################################################
10244 11:20:27.910193
10245 11:20:28.454366 02880000 ################################################################
10246 11:20:28.454524
10247 11:20:28.982936 02900000 ################################################################
10248 11:20:28.983075
10249 11:20:29.507095 02980000 ################################################################
10250 11:20:29.507270
10251 11:20:30.029898 02a00000 ################################################################
10252 11:20:30.030082
10253 11:20:30.570455 02a80000 ################################################################
10254 11:20:30.570607
10255 11:20:31.131695 02b00000 ################################################################
10256 11:20:31.131951
10257 11:20:31.660148 02b80000 ################################################################
10258 11:20:31.660339
10259 11:20:32.191399 02c00000 ################################################################
10260 11:20:32.191588
10261 11:20:32.731054 02c80000 ################################################################
10262 11:20:32.731255
10263 11:20:33.275520 02d00000 ################################################################
10264 11:20:33.275656
10265 11:20:33.806654 02d80000 ################################################################
10266 11:20:33.806847
10267 11:20:34.330596 02e00000 ################################################################
10268 11:20:34.330756
10269 11:20:34.863880 02e80000 ################################################################
10270 11:20:34.864047
10271 11:20:35.394520 02f00000 ################################################################
10272 11:20:35.394709
10273 11:20:35.850020 02f80000 ######################################################## done.
10274 11:20:35.850195
10275 11:20:35.853061 The bootfile was 50260186 bytes long.
10276 11:20:35.853171
10277 11:20:35.856746 Sending tftp read request... done.
10278 11:20:35.856871
10279 11:20:35.859736 Waiting for the transfer...
10280 11:20:35.859853
10281 11:20:35.863425 00000000 # done.
10282 11:20:35.863539
10283 11:20:35.870106 Command line loaded dynamically from TFTP file: 10591280/tftp-deploy-_r2evtbo/kernel/cmdline
10284 11:20:35.870230
10285 11:20:35.879521 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10286 11:20:35.879659
10287 11:20:35.882779 Loading FIT.
10288 11:20:35.882893
10289 11:20:35.886029 Image ramdisk-1 has 40125206 bytes.
10290 11:20:35.886120
10291 11:20:35.889402 Image fdt-1 has 46924 bytes.
10292 11:20:35.889517
10293 11:20:35.889615 Image kernel-1 has 10086024 bytes.
10294 11:20:35.892746
10295 11:20:35.899407 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10296 11:20:35.899537
10297 11:20:35.919046 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10298 11:20:35.919192
10299 11:20:35.922539 Choosing best match conf-1 for compat google,spherion-rev2.
10300 11:20:35.926727
10301 11:20:35.931126 Connected to device vid:did:rid of 1ae0:0028:00
10302 11:20:35.938383
10303 11:20:35.941586 tpm_get_response: command 0x17b, return code 0x0
10304 11:20:35.941730
10305 11:20:35.944954 ec_init: CrosEC protocol v3 supported (256, 248)
10306 11:20:35.949955
10307 11:20:35.953733 tpm_cleanup: add release locality here.
10308 11:20:35.953854
10309 11:20:35.953955 Shutting down all USB controllers.
10310 11:20:35.956712
10311 11:20:35.956817 Removing current net device
10312 11:20:35.956915
10313 11:20:35.963514 Exiting depthcharge with code 4 at timestamp: 88683833
10314 11:20:35.963624
10315 11:20:35.967118 LZMA decompressing kernel-1 to 0x821a6718
10316 11:20:35.967235
10317 11:20:35.970145 LZMA decompressing kernel-1 to 0x40000000
10318 11:20:37.236844
10319 11:20:37.237013 jumping to kernel
10320 11:20:37.237746 end: 2.2.4 bootloader-commands (duration 00:01:01) [common]
10321 11:20:37.237877 start: 2.2.5 auto-login-action (timeout 00:03:25) [common]
10322 11:20:37.237999 Setting prompt string to ['Linux version [0-9]']
10323 11:20:37.238112 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10324 11:20:37.238216 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10325 11:20:37.318662
10326 11:20:37.321981 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10327 11:20:37.325404 start: 2.2.5.1 login-action (timeout 00:03:24) [common]
10328 11:20:37.325541 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10329 11:20:37.325667 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10330 11:20:37.325782 Using line separator: #'\n'#
10331 11:20:37.325876 No login prompt set.
10332 11:20:37.325980 Parsing kernel messages
10333 11:20:37.326074 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10334 11:20:37.326251 [login-action] Waiting for messages, (timeout 00:03:24)
10335 11:20:37.344673 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1609115-arm64-gcc-10-defconfig-arm64-chromebook-dplkv) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 10:57:14 UTC 2023
10336 11:20:37.348151 [ 0.000000] random: crng init done
10337 11:20:37.354373 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10338 11:20:37.357788 [ 0.000000] efi: UEFI not found.
10339 11:20:37.364716 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10340 11:20:37.371204 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10341 11:20:37.380833 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10342 11:20:37.390953 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10343 11:20:37.396993 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10344 11:20:37.403469 [ 0.000000] printk: bootconsole [mtk8250] enabled
10345 11:20:37.410408 [ 0.000000] NUMA: No NUMA configuration found
10346 11:20:37.417022 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10347 11:20:37.423315 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10348 11:20:37.423440 [ 0.000000] Zone ranges:
10349 11:20:37.429697 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10350 11:20:37.433379 [ 0.000000] DMA32 empty
10351 11:20:37.440033 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10352 11:20:37.442906 [ 0.000000] Movable zone start for each node
10353 11:20:37.446557 [ 0.000000] Early memory node ranges
10354 11:20:37.453077 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10355 11:20:37.459557 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10356 11:20:37.465722 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10357 11:20:37.472789 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10358 11:20:37.478835 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10359 11:20:37.485562 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10360 11:20:37.542491 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10361 11:20:37.549046 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10362 11:20:37.555663 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10363 11:20:37.558728 [ 0.000000] psci: probing for conduit method from DT.
10364 11:20:37.565188 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10365 11:20:37.568571 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10366 11:20:37.575020 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10367 11:20:37.578540 [ 0.000000] psci: SMC Calling Convention v1.2
10368 11:20:37.585377 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10369 11:20:37.588276 [ 0.000000] Detected VIPT I-cache on CPU0
10370 11:20:37.594641 [ 0.000000] CPU features: detected: GIC system register CPU interface
10371 11:20:37.601405 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10372 11:20:37.607906 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10373 11:20:37.614852 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10374 11:20:37.624659 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10375 11:20:37.631103 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10376 11:20:37.634057 [ 0.000000] alternatives: applying boot alternatives
10377 11:20:37.641142 [ 0.000000] Fallback order for Node 0: 0
10378 11:20:37.647434 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10379 11:20:37.651241 [ 0.000000] Policy zone: Normal
10380 11:20:37.664141 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10381 11:20:37.674011 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10382 11:20:37.684769 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10383 11:20:37.694580 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10384 11:20:37.700623 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10385 11:20:37.704345 <6>[ 0.000000] software IO TLB: area num 8.
10386 11:20:37.760897 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10387 11:20:37.909536 <6>[ 0.000000] Memory: 7933756K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 419012K reserved, 32768K cma-reserved)
10388 11:20:37.916689 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10389 11:20:37.922872 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10390 11:20:37.926218 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10391 11:20:37.932561 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10392 11:20:37.939456 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10393 11:20:37.942731 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10394 11:20:37.952816 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10395 11:20:37.959304 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10396 11:20:37.965933 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10397 11:20:37.971987 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10398 11:20:37.975365 <6>[ 0.000000] GICv3: 608 SPIs implemented
10399 11:20:37.978635 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10400 11:20:37.985222 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10401 11:20:37.988679 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10402 11:20:37.995136 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10403 11:20:38.008386 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10404 11:20:38.021491 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10405 11:20:38.028320 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10406 11:20:38.036434 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10407 11:20:38.049934 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10408 11:20:38.056237 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10409 11:20:38.063072 <6>[ 0.009226] Console: colour dummy device 80x25
10410 11:20:38.072718 <6>[ 0.013953] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10411 11:20:38.079264 <6>[ 0.024460] pid_max: default: 32768 minimum: 301
10412 11:20:38.082860 <6>[ 0.029364] LSM: Security Framework initializing
10413 11:20:38.088949 <6>[ 0.034303] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10414 11:20:38.099053 <6>[ 0.042119] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10415 11:20:38.108740 <6>[ 0.051540] cblist_init_generic: Setting adjustable number of callback queues.
10416 11:20:38.115565 <6>[ 0.059040] cblist_init_generic: Setting shift to 3 and lim to 1.
10417 11:20:38.118604 <6>[ 0.065377] cblist_init_generic: Setting shift to 3 and lim to 1.
10418 11:20:38.125216 <6>[ 0.071783] rcu: Hierarchical SRCU implementation.
10419 11:20:38.132147 <6>[ 0.076828] rcu: Max phase no-delay instances is 1000.
10420 11:20:38.138516 <6>[ 0.083847] EFI services will not be available.
10421 11:20:38.141862 <6>[ 0.088815] smp: Bringing up secondary CPUs ...
10422 11:20:38.149829 <6>[ 0.093866] Detected VIPT I-cache on CPU1
10423 11:20:38.156541 <6>[ 0.093938] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10424 11:20:38.163511 <6>[ 0.093970] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10425 11:20:38.166521 <6>[ 0.094306] Detected VIPT I-cache on CPU2
10426 11:20:38.176339 <6>[ 0.094353] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10427 11:20:38.182933 <6>[ 0.094370] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10428 11:20:38.185756 <6>[ 0.094628] Detected VIPT I-cache on CPU3
10429 11:20:38.192282 <6>[ 0.094674] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10430 11:20:38.199628 <6>[ 0.094688] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10431 11:20:38.202581 <6>[ 0.094991] CPU features: detected: Spectre-v4
10432 11:20:38.209443 <6>[ 0.094997] CPU features: detected: Spectre-BHB
10433 11:20:38.212572 <6>[ 0.095002] Detected PIPT I-cache on CPU4
10434 11:20:38.219102 <6>[ 0.095058] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10435 11:20:38.225918 <6>[ 0.095075] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10436 11:20:38.231971 <6>[ 0.095369] Detected PIPT I-cache on CPU5
10437 11:20:38.238851 <6>[ 0.095432] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10438 11:20:38.245386 <6>[ 0.095448] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10439 11:20:38.248894 <6>[ 0.095730] Detected PIPT I-cache on CPU6
10440 11:20:38.255147 <6>[ 0.095795] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10441 11:20:38.265139 <6>[ 0.095811] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10442 11:20:38.268807 <6>[ 0.096109] Detected PIPT I-cache on CPU7
10443 11:20:38.274758 <6>[ 0.096173] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10444 11:20:38.281501 <6>[ 0.096190] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10445 11:20:38.284688 <6>[ 0.096236] smp: Brought up 1 node, 8 CPUs
10446 11:20:38.291141 <6>[ 0.237476] SMP: Total of 8 processors activated.
10447 11:20:38.298108 <6>[ 0.242397] CPU features: detected: 32-bit EL0 Support
10448 11:20:38.304598 <6>[ 0.247760] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10449 11:20:38.311000 <6>[ 0.256615] CPU features: detected: Common not Private translations
10450 11:20:38.317721 <6>[ 0.263130] CPU features: detected: CRC32 instructions
10451 11:20:38.324156 <6>[ 0.268515] CPU features: detected: RCpc load-acquire (LDAPR)
10452 11:20:38.327639 <6>[ 0.274512] CPU features: detected: LSE atomic instructions
10453 11:20:38.333726 <6>[ 0.280293] CPU features: detected: Privileged Access Never
10454 11:20:38.340583 <6>[ 0.286072] CPU features: detected: RAS Extension Support
10455 11:20:38.346935 <6>[ 0.291681] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10456 11:20:38.350355 <6>[ 0.298933] CPU: All CPU(s) started at EL2
10457 11:20:38.356624 <6>[ 0.303249] alternatives: applying system-wide alternatives
10458 11:20:38.367691 <6>[ 0.313958] devtmpfs: initialized
10459 11:20:38.383162 <6>[ 0.323050] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10460 11:20:38.389972 <6>[ 0.333015] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10461 11:20:38.396347 <6>[ 0.341256] pinctrl core: initialized pinctrl subsystem
10462 11:20:38.399411 <6>[ 0.347925] DMI not present or invalid.
10463 11:20:38.406199 <6>[ 0.352333] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10464 11:20:38.416124 <6>[ 0.359223] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10465 11:20:38.422712 <6>[ 0.366802] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10466 11:20:38.432869 <6>[ 0.375031] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10467 11:20:38.438964 <6>[ 0.383273] audit: initializing netlink subsys (disabled)
10468 11:20:38.445903 <5>[ 0.388969] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10469 11:20:38.452080 <6>[ 0.389679] thermal_sys: Registered thermal governor 'step_wise'
10470 11:20:38.459091 <6>[ 0.396934] thermal_sys: Registered thermal governor 'power_allocator'
10471 11:20:38.461946 <6>[ 0.403191] cpuidle: using governor menu
10472 11:20:38.468799 <6>[ 0.414153] NET: Registered PF_QIPCRTR protocol family
10473 11:20:38.475213 <6>[ 0.419626] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10474 11:20:38.482133 <6>[ 0.426728] ASID allocator initialised with 32768 entries
10475 11:20:38.485099 <6>[ 0.433293] Serial: AMBA PL011 UART driver
10476 11:20:38.495509 <4>[ 0.441987] Trying to register duplicate clock ID: 134
10477 11:20:38.549462 <6>[ 0.499449] KASLR enabled
10478 11:20:38.564542 <6>[ 0.507351] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10479 11:20:38.570790 <6>[ 0.514365] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10480 11:20:38.577410 <6>[ 0.520856] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10481 11:20:38.583934 <6>[ 0.527861] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10482 11:20:38.590508 <6>[ 0.534347] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10483 11:20:38.597178 <6>[ 0.541349] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10484 11:20:38.603563 <6>[ 0.547834] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10485 11:20:38.610480 <6>[ 0.554836] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10486 11:20:38.613235 <6>[ 0.562352] ACPI: Interpreter disabled.
10487 11:20:38.622117 <6>[ 0.568728] iommu: Default domain type: Translated
10488 11:20:38.628783 <6>[ 0.573840] iommu: DMA domain TLB invalidation policy: strict mode
10489 11:20:38.631987 <5>[ 0.580491] SCSI subsystem initialized
10490 11:20:38.639168 <6>[ 0.584656] usbcore: registered new interface driver usbfs
10491 11:20:38.645412 <6>[ 0.590389] usbcore: registered new interface driver hub
10492 11:20:38.648900 <6>[ 0.595938] usbcore: registered new device driver usb
10493 11:20:38.655683 <6>[ 0.602016] pps_core: LinuxPPS API ver. 1 registered
10494 11:20:38.665348 <6>[ 0.607207] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10495 11:20:38.668757 <6>[ 0.616552] PTP clock support registered
10496 11:20:38.672215 <6>[ 0.620793] EDAC MC: Ver: 3.0.0
10497 11:20:38.679679 <6>[ 0.625934] FPGA manager framework
10498 11:20:38.686052 <6>[ 0.629615] Advanced Linux Sound Architecture Driver Initialized.
10499 11:20:38.689657 <6>[ 0.636381] vgaarb: loaded
10500 11:20:38.695963 <6>[ 0.639545] clocksource: Switched to clocksource arch_sys_counter
10501 11:20:38.699439 <5>[ 0.645983] VFS: Disk quotas dquot_6.6.0
10502 11:20:38.705566 <6>[ 0.650164] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10503 11:20:38.709153 <6>[ 0.657350] pnp: PnP ACPI: disabled
10504 11:20:38.717578 <6>[ 0.664077] NET: Registered PF_INET protocol family
10505 11:20:38.727435 <6>[ 0.669679] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10506 11:20:38.738787 <6>[ 0.681980] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10507 11:20:38.748689 <6>[ 0.690797] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10508 11:20:38.755182 <6>[ 0.698768] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10509 11:20:38.764837 <6>[ 0.707464] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10510 11:20:38.772087 <6>[ 0.717200] TCP: Hash tables configured (established 65536 bind 65536)
10511 11:20:38.778018 <6>[ 0.724054] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10512 11:20:38.788422 <6>[ 0.731247] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10513 11:20:38.794619 <6>[ 0.738945] NET: Registered PF_UNIX/PF_LOCAL protocol family
10514 11:20:38.801568 <6>[ 0.745106] RPC: Registered named UNIX socket transport module.
10515 11:20:38.804369 <6>[ 0.751262] RPC: Registered udp transport module.
10516 11:20:38.811180 <6>[ 0.756195] RPC: Registered tcp transport module.
10517 11:20:38.817551 <6>[ 0.761128] RPC: Registered tcp NFSv4.1 backchannel transport module.
10518 11:20:38.820896 <6>[ 0.767792] PCI: CLS 0 bytes, default 64
10519 11:20:38.824477 <6>[ 0.772191] Unpacking initramfs...
10520 11:20:38.834211 <6>[ 0.776015] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10521 11:20:38.840851 <6>[ 0.784630] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10522 11:20:38.847345 <6>[ 0.793466] kvm [1]: IPA Size Limit: 40 bits
10523 11:20:38.850551 <6>[ 0.797994] kvm [1]: GICv3: no GICV resource entry
10524 11:20:38.857413 <6>[ 0.803015] kvm [1]: disabling GICv2 emulation
10525 11:20:38.863785 <6>[ 0.807705] kvm [1]: GIC system register CPU interface enabled
10526 11:20:38.867186 <6>[ 0.813869] kvm [1]: vgic interrupt IRQ18
10527 11:20:38.873938 <6>[ 0.818223] kvm [1]: VHE mode initialized successfully
10528 11:20:38.877162 <5>[ 0.824636] Initialise system trusted keyrings
10529 11:20:38.883738 <6>[ 0.829448] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10530 11:20:38.892737 <6>[ 0.839426] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10531 11:20:38.899696 <5>[ 0.845820] NFS: Registering the id_resolver key type
10532 11:20:38.903015 <5>[ 0.851121] Key type id_resolver registered
10533 11:20:38.909285 <5>[ 0.855537] Key type id_legacy registered
10534 11:20:38.916166 <6>[ 0.859819] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10535 11:20:38.922420 <6>[ 0.866738] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10536 11:20:38.929114 <6>[ 0.874464] 9p: Installing v9fs 9p2000 file system support
10537 11:20:38.966436 <5>[ 0.912260] Key type asymmetric registered
10538 11:20:38.968962 <5>[ 0.916592] Asymmetric key parser 'x509' registered
10539 11:20:38.978968 <6>[ 0.921762] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10540 11:20:38.982794 <6>[ 0.929377] io scheduler mq-deadline registered
10541 11:20:38.985744 <6>[ 0.934136] io scheduler kyber registered
10542 11:20:39.004791 <6>[ 0.951094] EINJ: ACPI disabled.
10543 11:20:39.036946 <4>[ 0.976667] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10544 11:20:39.046729 <4>[ 0.987296] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10545 11:20:39.061875 <6>[ 1.008176] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10546 11:20:39.069827 <6>[ 1.016237] printk: console [ttyS0] disabled
10547 11:20:39.097732 <6>[ 1.040886] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10548 11:20:39.104079 <6>[ 1.050362] printk: console [ttyS0] enabled
10549 11:20:39.107560 <6>[ 1.050362] printk: console [ttyS0] enabled
10550 11:20:39.114323 <6>[ 1.059266] printk: bootconsole [mtk8250] disabled
10551 11:20:39.117256 <6>[ 1.059266] printk: bootconsole [mtk8250] disabled
10552 11:20:39.124265 <6>[ 1.070488] SuperH (H)SCI(F) driver initialized
10553 11:20:39.127583 <6>[ 1.075795] msm_serial: driver initialized
10554 11:20:39.141609 <6>[ 1.084744] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10555 11:20:39.151524 <6>[ 1.093292] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10556 11:20:39.157967 <6>[ 1.101834] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10557 11:20:39.167911 <6>[ 1.110462] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10558 11:20:39.177624 <6>[ 1.119167] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10559 11:20:39.184335 <6>[ 1.127881] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10560 11:20:39.194336 <6>[ 1.136429] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10561 11:20:39.201060 <6>[ 1.145240] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10562 11:20:39.211014 <6>[ 1.153784] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10563 11:20:39.222888 <6>[ 1.169637] loop: module loaded
10564 11:20:39.229414 <6>[ 1.175724] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10565 11:20:39.252771 <4>[ 1.199127] mtk-pmic-keys: Failed to locate of_node [id: -1]
10566 11:20:39.259585 <6>[ 1.205954] megasas: 07.719.03.00-rc1
10567 11:20:39.269050 <6>[ 1.215555] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10568 11:20:39.276685 <6>[ 1.222925] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10569 11:20:39.293187 <6>[ 1.239657] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10570 11:20:39.353544 <6>[ 1.293743] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10571 11:20:40.446137 <6>[ 2.393048] Freeing initrd memory: 39180K
10572 11:20:40.456979 <6>[ 2.403475] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10573 11:20:40.467574 <6>[ 2.414310] tun: Universal TUN/TAP device driver, 1.6
10574 11:20:40.471051 <6>[ 2.420379] thunder_xcv, ver 1.0
10575 11:20:40.474224 <6>[ 2.423883] thunder_bgx, ver 1.0
10576 11:20:40.477510 <6>[ 2.427372] nicpf, ver 1.0
10577 11:20:40.488304 <6>[ 2.431367] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10578 11:20:40.491792 <6>[ 2.438843] hns3: Copyright (c) 2017 Huawei Corporation.
10579 11:20:40.498108 <6>[ 2.444429] hclge is initializing
10580 11:20:40.501077 <6>[ 2.448008] e1000: Intel(R) PRO/1000 Network Driver
10581 11:20:40.507640 <6>[ 2.453137] e1000: Copyright (c) 1999-2006 Intel Corporation.
10582 11:20:40.514397 <6>[ 2.459150] e1000e: Intel(R) PRO/1000 Network Driver
10583 11:20:40.517728 <6>[ 2.464366] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10584 11:20:40.524225 <6>[ 2.470553] igb: Intel(R) Gigabit Ethernet Network Driver
10585 11:20:40.531092 <6>[ 2.476203] igb: Copyright (c) 2007-2014 Intel Corporation.
10586 11:20:40.537466 <6>[ 2.482040] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10587 11:20:40.544380 <6>[ 2.488557] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10588 11:20:40.547360 <6>[ 2.495015] sky2: driver version 1.30
10589 11:20:40.553813 <6>[ 2.500003] VFIO - User Level meta-driver version: 0.3
10590 11:20:40.561333 <6>[ 2.508161] usbcore: registered new interface driver usb-storage
10591 11:20:40.568364 <6>[ 2.514603] usbcore: registered new device driver onboard-usb-hub
10592 11:20:40.576802 <6>[ 2.523637] mt6397-rtc mt6359-rtc: registered as rtc0
10593 11:20:40.586587 <6>[ 2.529101] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-05T11:20:40 UTC (1685964040)
10594 11:20:40.589933 <6>[ 2.538680] i2c_dev: i2c /dev entries driver
10595 11:20:40.607116 <6>[ 2.550399] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10596 11:20:40.614120 <6>[ 2.560586] sdhci: Secure Digital Host Controller Interface driver
10597 11:20:40.620869 <6>[ 2.567024] sdhci: Copyright(c) Pierre Ossman
10598 11:20:40.627073 <6>[ 2.572414] Synopsys Designware Multimedia Card Interface Driver
10599 11:20:40.630548 <6>[ 2.579022] mmc0: CQHCI version 5.10
10600 11:20:40.637095 <6>[ 2.579576] sdhci-pltfm: SDHCI platform and OF driver helper
10601 11:20:40.644465 <6>[ 2.590888] ledtrig-cpu: registered to indicate activity on CPUs
10602 11:20:40.654569 <6>[ 2.598214] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10603 11:20:40.661476 <6>[ 2.605610] usbcore: registered new interface driver usbhid
10604 11:20:40.664859 <6>[ 2.611436] usbhid: USB HID core driver
10605 11:20:40.671358 <6>[ 2.615690] spi_master spi0: will run message pump with realtime priority
10606 11:20:40.716531 <6>[ 2.656618] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10607 11:20:40.735012 <6>[ 2.671686] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10608 11:20:40.738514 <6>[ 2.685257] mmc0: Command Queue Engine enabled
10609 11:20:40.745302 <6>[ 2.690046] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10610 11:20:40.751626 <6>[ 2.697190] cros-ec-spi spi0.0: Chrome EC device registered
10611 11:20:40.755040 <6>[ 2.697437] mmcblk0: mmc0:0001 DA4128 116 GiB
10612 11:20:40.765046 <6>[ 2.711956] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10613 11:20:40.773041 <6>[ 2.719414] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10614 11:20:40.779524 <6>[ 2.725352] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10615 11:20:40.785831 <6>[ 2.731382] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10616 11:20:40.804008 <6>[ 2.747217] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10617 11:20:40.812045 <6>[ 2.758621] NET: Registered PF_PACKET protocol family
10618 11:20:40.818552 <6>[ 2.764066] 9pnet: Installing 9P2000 support
10619 11:20:40.821922 <5>[ 2.768659] Key type dns_resolver registered
10620 11:20:40.824914 <6>[ 2.773808] registered taskstats version 1
10621 11:20:40.831474 <5>[ 2.778225] Loading compiled-in X.509 certificates
10622 11:20:40.865527 <4>[ 2.805853] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10623 11:20:40.875453 <4>[ 2.816545] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10624 11:20:40.885465 <3>[ 2.829169] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10625 11:20:40.898225 <6>[ 2.844592] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10626 11:20:40.905055 <6>[ 2.851345] xhci-mtk 11200000.usb: xHCI Host Controller
10627 11:20:40.911095 <6>[ 2.856849] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10628 11:20:40.921540 <6>[ 2.864698] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10629 11:20:40.927997 <6>[ 2.874152] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10630 11:20:40.934522 <6>[ 2.880261] xhci-mtk 11200000.usb: xHCI Host Controller
10631 11:20:40.940910 <6>[ 2.885887] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10632 11:20:40.947588 <6>[ 2.893598] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10633 11:20:40.954823 <6>[ 2.901507] hub 1-0:1.0: USB hub found
10634 11:20:40.958038 <6>[ 2.905542] hub 1-0:1.0: 1 port detected
10635 11:20:40.967989 <6>[ 2.909890] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10636 11:20:40.970973 <6>[ 2.918504] hub 2-0:1.0: USB hub found
10637 11:20:40.974342 <6>[ 2.922520] hub 2-0:1.0: 1 port detected
10638 11:20:40.982880 <6>[ 2.929597] mtk-msdc 11f70000.mmc: Got CD GPIO
10639 11:20:41.000318 <6>[ 2.943666] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10640 11:20:41.006952 <6>[ 2.951693] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10641 11:20:41.016891 <4>[ 2.959660] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10642 11:20:41.026516 <6>[ 2.969327] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10643 11:20:41.033352 <6>[ 2.977408] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10644 11:20:41.043081 <6>[ 2.985431] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10645 11:20:41.050132 <6>[ 2.993355] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10646 11:20:41.056590 <6>[ 3.001177] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10647 11:20:41.065802 <6>[ 3.009005] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10648 11:20:41.076479 <6>[ 3.019725] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10649 11:20:41.086234 <6>[ 3.028101] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10650 11:20:41.092629 <6>[ 3.036445] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10651 11:20:41.102741 <6>[ 3.044788] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10652 11:20:41.109639 <6>[ 3.053131] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10653 11:20:41.119486 <6>[ 3.061473] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10654 11:20:41.125625 <6>[ 3.069816] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10655 11:20:41.135891 <6>[ 3.078159] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10656 11:20:41.142382 <6>[ 3.086501] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10657 11:20:41.152396 <6>[ 3.094843] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10658 11:20:41.158786 <6>[ 3.103185] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10659 11:20:41.168891 <6>[ 3.111528] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10660 11:20:41.175501 <6>[ 3.119871] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10661 11:20:41.185108 <6>[ 3.128216] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10662 11:20:41.191541 <6>[ 3.136563] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10663 11:20:41.198954 <6>[ 3.145456] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10664 11:20:41.205860 <6>[ 3.152859] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10665 11:20:41.213307 <6>[ 3.159903] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10666 11:20:41.223757 <6>[ 3.167005] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10667 11:20:41.230008 <6>[ 3.174290] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10668 11:20:41.240132 <6>[ 3.181142] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10669 11:20:41.246755 <6>[ 3.190294] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10670 11:20:41.257067 <6>[ 3.199421] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10671 11:20:41.267040 <6>[ 3.208723] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10672 11:20:41.276579 <6>[ 3.218203] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10673 11:20:41.286533 <6>[ 3.227677] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10674 11:20:41.293246 <6>[ 3.236804] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10675 11:20:41.303108 <6>[ 3.246307] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10676 11:20:41.313051 <6>[ 3.255439] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10677 11:20:41.322658 <6>[ 3.264749] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10678 11:20:41.332337 <6>[ 3.274916] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10679 11:20:41.343640 <6>[ 3.286898] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10680 11:20:41.364742 <6>[ 3.308169] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10681 11:20:41.393407 <6>[ 3.339946] hub 2-1:1.0: USB hub found
10682 11:20:41.396677 <6>[ 3.344456] hub 2-1:1.0: 3 ports detected
10683 11:20:41.516399 <6>[ 3.459799] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10684 11:20:41.670350 <6>[ 3.617269] hub 1-1:1.0: USB hub found
10685 11:20:41.673895 <6>[ 3.621702] hub 1-1:1.0: 4 ports detected
10686 11:20:41.752811 <6>[ 3.696066] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10687 11:20:41.996852 <6>[ 3.939852] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10688 11:20:42.129353 <6>[ 4.076097] hub 1-1.4:1.0: USB hub found
10689 11:20:42.132626 <6>[ 4.080750] hub 1-1.4:1.0: 2 ports detected
10690 11:20:42.428096 <6>[ 4.371818] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10691 11:20:42.620091 <6>[ 4.563819] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10692 11:20:53.644774 <6>[ 15.596371] ALSA device list:
10693 11:20:53.651148 <6>[ 15.599627] No soundcards found.
10694 11:20:53.664054 <6>[ 15.612053] Freeing unused kernel memory: 8384K
10695 11:20:53.667098 <6>[ 15.616986] Run /init as init process
10696 11:20:53.697505 <6>[ 15.645730] NET: Registered PF_INET6 protocol family
10697 11:20:53.704295 <6>[ 15.651984] Segment Routing with IPv6
10698 11:20:53.707488 <6>[ 15.655917] In-situ OAM (IOAM) with IPv6
10699 11:20:53.742035 <30>[ 15.670325] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10700 11:20:53.745668 <30>[ 15.694105] systemd[1]: Detected architecture arm64.
10701 11:20:53.745759
10702 11:20:53.751591 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10703 11:20:53.751675
10704 11:20:53.767765 <30>[ 15.715888] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10705 11:20:53.899616 <30>[ 15.844790] systemd[1]: Queued start job for default target Graphical Interface.
10706 11:20:53.932915 <30>[ 15.881243] systemd[1]: Created slice system-getty.slice.
10707 11:20:53.939559 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10708 11:20:53.955967 <30>[ 15.904384] systemd[1]: Created slice system-modprobe.slice.
10709 11:20:53.962553 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10710 11:20:53.981199 <30>[ 15.928940] systemd[1]: Created slice system-serial\x2dgetty.slice.
10711 11:20:53.990959 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10712 11:20:54.004287 <30>[ 15.952333] systemd[1]: Created slice User and Session Slice.
10713 11:20:54.011051 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10714 11:20:54.031265 <30>[ 15.976380] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10715 11:20:54.041721 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10716 11:20:54.059123 <30>[ 16.003989] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10717 11:20:54.065596 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10718 11:20:54.086369 <30>[ 16.027921] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10719 11:20:54.093055 <30>[ 16.039957] systemd[1]: Reached target Local Encrypted Volumes.
10720 11:20:54.099722 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10721 11:20:54.116136 <30>[ 16.064186] systemd[1]: Reached target Paths.
10722 11:20:54.119371 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10723 11:20:54.135661 <30>[ 16.083872] systemd[1]: Reached target Remote File Systems.
10724 11:20:54.142251 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10725 11:20:54.155754 <30>[ 16.103865] systemd[1]: Reached target Slices.
10726 11:20:54.161872 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10727 11:20:54.175712 <30>[ 16.123871] systemd[1]: Reached target Swap.
10728 11:20:54.179179 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10729 11:20:54.199468 <30>[ 16.144183] systemd[1]: Listening on initctl Compatibility Named Pipe.
10730 11:20:54.206103 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10731 11:20:54.212659 <30>[ 16.158958] systemd[1]: Listening on Journal Audit Socket.
10732 11:20:54.218716 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10733 11:20:54.231884 <30>[ 16.180125] systemd[1]: Listening on Journal Socket (/dev/log).
10734 11:20:54.238390 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10735 11:20:54.256562 <30>[ 16.204608] systemd[1]: Listening on Journal Socket.
10736 11:20:54.262873 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10737 11:20:54.279304 <30>[ 16.224256] systemd[1]: Listening on Network Service Netlink Socket.
10738 11:20:54.285776 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10739 11:20:54.300236 <30>[ 16.248590] systemd[1]: Listening on udev Control Socket.
10740 11:20:54.307017 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10741 11:20:54.324341 <30>[ 16.272521] systemd[1]: Listening on udev Kernel Socket.
10742 11:20:54.330763 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10743 11:20:54.368074 <30>[ 16.316233] systemd[1]: Mounting Huge Pages File System...
10744 11:20:54.374658 Mounting [0;1;39mHuge Pages File System[0m...
10745 11:20:54.389688 <30>[ 16.338029] systemd[1]: Mounting POSIX Message Queue File System...
10746 11:20:54.396475 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10747 11:20:54.414095 <30>[ 16.362012] systemd[1]: Mounting Kernel Debug File System...
10748 11:20:54.420675 Mounting [0;1;39mKernel Debug File System[0m...
10749 11:20:54.439571 <30>[ 16.384297] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10750 11:20:54.463567 <30>[ 16.408257] systemd[1]: Starting Create list of static device nodes for the current kernel...
10751 11:20:54.469700 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10752 11:20:54.489637 <30>[ 16.438025] systemd[1]: Starting Load Kernel Module configfs...
10753 11:20:54.496261 Starting [0;1;39mLoad Kernel Module configfs[0m...
10754 11:20:54.524018 <30>[ 16.472382] systemd[1]: Starting Load Kernel Module drm...
10755 11:20:54.530569 Starting [0;1;39mLoad Kernel Module drm[0m...
10756 11:20:54.547248 <30>[ 16.492179] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10757 11:20:54.557883 <30>[ 16.506113] systemd[1]: Starting Journal Service...
10758 11:20:54.561415 Starting [0;1;39mJournal Service[0m...
10759 11:20:54.582548 <30>[ 16.530638] systemd[1]: Starting Load Kernel Modules...
10760 11:20:54.588735 Starting [0;1;39mLoad Kernel Modules[0m...
10761 11:20:54.609536 <30>[ 16.554614] systemd[1]: Starting Remount Root and Kernel File Systems...
10762 11:20:54.615997 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10763 11:20:54.630425 <30>[ 16.578324] systemd[1]: Starting Coldplug All udev Devices...
10764 11:20:54.636733 Starting [0;1;39mColdplug All udev Devices[0m...
10765 11:20:54.654128 <30>[ 16.602499] systemd[1]: Started Journal Service.
10766 11:20:54.661017 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10767 11:20:54.677329 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10768 11:20:54.693261 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10769 11:20:54.708297 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10770 11:20:54.728235 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10771 11:20:54.745032 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10772 11:20:54.761341 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10773 11:20:54.777179 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10774 11:20:54.796584 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10775 11:20:54.811635 See 'systemctl status systemd-remount-fs.service' for details.
10776 11:20:54.848428 Mounting [0;1;39mKernel Configuration File System[0m...
10777 11:20:54.870537 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10778 11:20:54.887918 <46>[ 16.832756] systemd-journald[174]: Received client request to flush runtime journal.
10779 11:20:54.896382 Starting [0;1;39mLoad/Save Random Seed[0m...
10780 11:20:54.914775 Starting [0;1;39mApply Kernel Variables[0m...
10781 11:20:54.931268 Starting [0;1;39mCreate System Users[0m...
10782 11:20:54.955995 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10783 11:20:54.972166 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10784 11:20:54.984679 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10785 11:20:55.000634 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10786 11:20:55.016751 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10787 11:20:55.032600 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10788 11:20:55.076432 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10789 11:20:55.099124 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10790 11:20:55.111868 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10791 11:20:55.128014 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10792 11:20:55.168391 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10793 11:20:55.191344 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10794 11:20:55.209036 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10795 11:20:55.228913 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10796 11:20:55.277215 Starting [0;1;39mNetwork Service[0m...
10797 11:20:55.299788 Starting [0;1;39mNetwork Time Synchronization[0m...
10798 11:20:55.319341 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10799 11:20:55.352600 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10800 11:20:55.369291 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10801 11:20:55.403816 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10802 11:20:55.417398 <6>[ 17.362625] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10803 11:20:55.432125 <6>[ 17.380315] remoteproc remoteproc0: scp is available
10804 11:20:55.438475 <6>[ 17.386586] remoteproc remoteproc0: powering up scp
10805 11:20:55.448562 <6>[ 17.392505] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10806 11:20:55.455027 Startin<6>[ 17.402291] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10807 11:20:55.461437 g [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10808 11:20:55.487912 <6>[ 17.432591] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10809 11:20:55.494804 <6>[ 17.440305] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10810 11:20:55.504038 <6>[ 17.449019] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10811 11:20:55.516808 <3>[ 17.461601] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10812 11:20:55.523438 <3>[ 17.469885] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10813 11:20:55.532863 <3>[ 17.478225] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10814 11:20:55.542894 <3>[ 17.488093] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10815 11:20:55.552988 <3>[ 17.496617] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10816 11:20:55.559476 <3>[ 17.505249] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10817 11:20:55.569176 Startin<3>[ 17.513538] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10818 11:20:55.579250 g [0;1;39mNetwo<4>[ 17.520762] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10819 11:20:55.589222 rk Name Resoluti<3>[ 17.522841] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10820 11:20:55.589307 on[0m...
10821 11:20:55.595612 <6>[ 17.534204] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10822 11:20:55.605207 <6>[ 17.534229] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10823 11:20:55.612197 <6>[ 17.534237] remoteproc remoteproc0: remote processor scp is now up
10824 11:20:55.618604 <4>[ 17.544237] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10825 11:20:55.625157 <3>[ 17.547685] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10826 11:20:55.631790 <6>[ 17.548793] usbcore: registered new interface driver r8152
10827 11:20:55.638240 <3>[ 17.551764] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10828 11:20:55.644627 <6>[ 17.580694] mc: Linux media interface: v0.10
10829 11:20:55.651639 <3>[ 17.585127] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10830 11:20:55.661780 <3>[ 17.585136] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10831 11:20:55.668364 <6>[ 17.610227] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10832 11:20:55.674754 <6>[ 17.620923] pci_bus 0000:00: root bus resource [bus 00-ff]
10833 11:20:55.681557 <3>[ 17.625742] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10834 11:20:55.687749 <6>[ 17.626682] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10835 11:20:55.697904 <3>[ 17.634787] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10836 11:20:55.707559 <6>[ 17.637504] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0002, Sample: 0x0004, IAP: 0x0003
10837 11:20:55.717765 <6>[ 17.641927] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10838 11:20:55.727735 [[0;32m OK [<3>[ 17.649973] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10839 11:20:55.734189 0m] Started [0;<6>[ 17.660141] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10840 11:20:55.744050 1;39mNetwork Tim<3>[ 17.669959] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10841 11:20:55.753965 e Synchronizatio<3>[ 17.669967] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10842 11:20:55.760422 <6>[ 17.672424] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input2
10843 11:20:55.763864 n[0m.
10844 11:20:55.770486 <6>[ 17.679619] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10845 11:20:55.776723 <6>[ 17.679767] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10846 11:20:55.783794 <3>[ 17.694201] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10847 11:20:55.793527 <6>[ 17.696206] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input3
10848 11:20:55.799872 <6>[ 17.696828] pci 0000:00:00.0: supports D1 D2
10849 11:20:55.807068 <6>[ 17.706608] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10850 11:20:55.813228 <6>[ 17.715112] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10851 11:20:55.819710 <6>[ 17.764300] videodev: Linux video capture interface: v2.00
10852 11:20:55.829511 [[0;32m OK [<6>[ 17.775406] usbcore: registered new interface driver cdc_ether
10853 11:20:55.839777 0m] Finished [0<4>[ 17.775917] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10854 11:20:55.849609 ;1;39mLoad/Save <6>[ 17.776720] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10855 11:20:55.856201 Screen …s of l<6>[ 17.776912] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10856 11:20:55.862512 <6>[ 17.776947] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10857 11:20:55.872367 eds:white:kbd_ba<6>[ 17.776971] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10858 11:20:55.872453 cklight[0m.
10859 11:20:55.882260 <6>[ 17.776989] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10860 11:20:55.885619 <6>[ 17.777126] pci 0000:01:00.0: supports D1 D2
10861 11:20:55.892091 <6>[ 17.777129] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10862 11:20:55.898601 <6>[ 17.791938] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10863 11:20:55.908561 <4>[ 17.792380] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10864 11:20:55.915527 <6>[ 17.803043] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10865 11:20:55.918700 <6>[ 17.804858] Bluetooth: Core ver 2.22
10866 11:20:55.925137 <6>[ 17.804955] NET: Registered PF_BLUETOOTH protocol family
10867 11:20:55.932046 <6>[ 17.804958] Bluetooth: HCI device and connection manager initialized
10868 11:20:55.938695 <6>[ 17.804979] Bluetooth: HCI socket layer initialized
10869 11:20:55.942096 <6>[ 17.804985] Bluetooth: L2CAP socket layer initialized
10870 11:20:55.948576 <6>[ 17.804996] Bluetooth: SCO socket layer initialized
10871 11:20:55.955022 <6>[ 17.807312] usbcore: registered new interface driver r8153_ecm
10872 11:20:55.961572 <6>[ 17.849408] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10873 11:20:55.968270 <6>[ 17.853912] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10874 11:20:55.975097 <6>[ 17.854491] usbcore: registered new interface driver btusb
10875 11:20:55.984481 <4>[ 17.861548] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10876 11:20:55.994378 <6>[ 17.869145] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10877 11:20:56.001308 <6>[ 17.869163] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10878 11:20:56.007951 <6>[ 17.869180] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10879 11:20:56.014253 <6>[ 17.869196] pci 0000:00:00.0: PCI bridge to [bus 01]
10880 11:20:56.021388 <3>[ 17.873030] Bluetooth: hci0: Failed to load firmware file (-2)
10881 11:20:56.027690 <6>[ 17.878626] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10882 11:20:56.034301 <3>[ 17.885205] Bluetooth: hci0: Failed to set up firmware (-2)
10883 11:20:56.044219 <4>[ 17.891171] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10884 11:20:56.047697 <4>[ 17.891171] Fallback method does not support PEC.
10885 11:20:56.050729 <6>[ 17.892983] r8152 2-1.3:1.0 eth0: v1.12.13
10886 11:20:56.064110 <4>[ 17.895662] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10887 11:20:56.067454 <6>[ 17.896830] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10888 11:20:56.080328 <6>[ 17.899240] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10889 11:20:56.090312 <6>[ 17.906328] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10890 11:20:56.097205 <6>[ 17.907461] usbcore: registered new interface driver uvcvideo
10891 11:20:56.103597 <6>[ 17.921548] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10892 11:20:56.110096 <6>[ 17.927912] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10893 11:20:56.116700 <6>[ 17.929188] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10894 11:20:56.123650 <6>[ 17.936159] r8152 2-1.3:1.0 enx0024323078ff: renamed from eth0
10895 11:20:56.130850 [[0;32m OK [<6>[ 18.076633] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10896 11:20:56.133913 0m] Found device [0;1;39m/dev/ttyS0[0m.
10897 11:20:56.146988 <3>[ 18.092310] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10898 11:20:56.163570 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m<5>[ 18.106823] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10899 11:20:56.163655 .
10900 11:20:56.179816 <5>[ 18.127482] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10901 11:20:56.189739 <4>[ 18.134407] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10902 11:20:56.199801 <3>[ 18.139733] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10903 11:20:56.203125 <6>[ 18.143304] cfg80211: failed to load regulatory.db
10904 11:20:56.212756 <3>[ 18.152500] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10905 11:20:56.232843 <3>[ 18.177536] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10906 11:20:56.242782 <3>[ 18.187841] power_supply sbs-5-000b: driver failed to report `capacity' property: -6
10907 11:20:56.256741 <6>[ 18.201238] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10908 11:20:56.263535 <3>[ 18.207557] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10909 11:20:56.269968 <6>[ 18.208739] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10910 11:20:56.291746 <3>[ 18.236826] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10911 11:20:56.298340 <6>[ 18.244106] mt7921e 0000:01:00.0: ASIC revision: 79610010
10912 11:20:56.320402 <3>[ 18.265591] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10913 11:20:56.350035 <3>[ 18.294897] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10914 11:20:56.362051 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10915 11:20:56.382452 [[0;32m OK [0m] Reached target [0;1;39mNetw<3>[ 18.327524] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10916 11:20:56.386049 ork[0m.
10917 11:20:56.399088 <4>[ 18.339817] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10918 11:20:56.405987 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10919 11:20:56.419984 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10920 11:20:56.439138 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10921 11:20:56.455823 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10922 11:20:56.471071 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10923 11:20:56.490718 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10924 11:20:56.505702 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10925 11:20:56.520872 <4>[ 18.462579] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10926 11:20:56.531001 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10927 11:20:56.547659 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10928 11:20:56.563351 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10929 11:20:56.583163 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10930 11:20:56.615781 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10931 11:20:56.641989 <4>[ 18.584009] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10932 11:20:56.680267 Starting [0;1;39mUser Login Management[0m...
10933 11:20:56.697784 Starting [0;1;39mPermit User Sessions[0m...
10934 11:20:56.715891 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
10935 11:20:56.732298 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10936 11:20:56.763703 [[0;32m OK [0m] Finished [0;1;39mPermit Use<4>[ 18.705718] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10937 11:20:56.766675 r Sessions[0m.
10938 11:20:56.816242 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10939 11:20:56.834164 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
10940 11:20:56.851855 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10941 11:20:56.875951 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10942 11:20:56.895796 [[0;32m OK [0m] Reached targ<4>[ 18.835822] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10943 11:20:56.899278 et [0;1;39mMulti-User System[0m.
10944 11:20:56.916173 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10945 11:20:56.959917 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
10946 11:20:56.984124 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10947 11:20:57.018262 <4>[ 18.960052] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10948 11:20:57.036043
10949 11:20:57.036129
10950 11:20:57.039441 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10951 11:20:57.039525
10952 11:20:57.042572 debian-bullseye-arm64 login: root (automatic login)
10953 11:20:57.042662
10954 11:20:57.042756
10955 11:20:57.060446 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Mon Jun 5 10:57:14 UTC 2023 aarch64
10956 11:20:57.060530
10957 11:20:57.066984 The programs included with the Debian GNU/Linux system are free software;
10958 11:20:57.073475 the exact distribution terms for each program are described in the
10959 11:20:57.076939 individual files in /usr/share/doc/*/copyright.
10960 11:20:57.077022
10961 11:20:57.083418 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10962 11:20:57.086280 permitted by applicable law.
10963 11:20:57.086619 Matched prompt #10: / #
10965 11:20:57.086825 Setting prompt string to ['/ #']
10966 11:20:57.086926 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10968 11:20:57.087122 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10969 11:20:57.087211 start: 2.2.6 expect-shell-connection (timeout 00:03:05) [common]
10970 11:20:57.087284 Setting prompt string to ['/ #']
10971 11:20:57.087345 Forcing a shell prompt, looking for ['/ #']
10973 11:20:57.137551 / #
10974 11:20:57.137663 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10975 11:20:57.137741 Waiting using forced prompt support (timeout 00:02:30)
10976 11:20:57.140487 <4>[ 19.082295] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10977 11:20:57.140574
10978 11:20:57.183179 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10979 11:20:57.183289 start: 2.2.7 export-device-env (timeout 00:03:05) [common]
10980 11:20:57.183386 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10981 11:20:57.183477 end: 2.2 depthcharge-retry (duration 00:01:55) [common]
10982 11:20:57.183561 end: 2 depthcharge-action (duration 00:01:55) [common]
10983 11:20:57.183648 start: 3 lava-test-retry (timeout 00:07:46) [common]
10984 11:20:57.183732 start: 3.1 lava-test-shell (timeout 00:07:46) [common]
10985 11:20:57.183804 Using namespace: common
10987 11:20:57.284104 / # #
10988 11:20:57.284259 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10989 11:20:57.284375 #<4>[ 19.202235] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10990 11:20:57.288860
10991 11:20:57.289127 Using /lava-10591280
10993 11:20:57.389470 / # export SHELL=/bin/sh
10994 11:20:57.389656 export SHELL=/bin/sh<4>[ 19.322061] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10995 11:20:57.394687
10997 11:20:57.495205 / # . /lava-10591280/environment
10998 11:20:57.538937 . /lava-10591280/environment<4>[ 19.442016] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10999 11:20:57.539042
11001 11:20:57.639556 / # /lava-10591280/bin/lava-test-runner /lava-10591280/0
11002 11:20:57.639671 Test shell timeout: 10s (minimum of the action and connection timeout)
11003 11:20:57.640003 /lava-10591280/bin/lava-test-runner /lava-10591280/0<3>[ 19.560185] mt7921e 0000:01:00.0: hardware init failed
11004 11:20:57.682976 <6>[ 19.591896] IPv6: ADDRCONF(NETDEV_CHANGE): enx0024323078ff: link becomes ready
11005 11:20:57.683066
11006 11:20:57.683132 <6>[ 19.600011] r8152 2-1.3:1.0 enx0024323078ff: carrier on
11007 11:20:57.683193 + export TESTRUN_ID=0_v4l2-compliance-mtk-vcodec-enc
11008 11:20:57.683254 + cd /lava-10591280/0/tests/0_v4l2-compliance-mtk-vcodec-enc
11009 11:20:57.683313 + cat uuid
11010 11:20:57.683371 + UUID=10591280_1.5.2.3.1
11011 11:20:57.683429 + set +x
11012 11:20:57.689025 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-mtk-vcodec-enc 10591280_1.5.2.3.1>
11013 11:20:57.689284 Received signal: <STARTRUN> 0_v4l2-compliance-mtk-vcodec-enc 10591280_1.5.2.3.1
11014 11:20:57.689359 Starting test lava.0_v4l2-compliance-mtk-vcodec-enc (10591280_1.5.2.3.1)
11015 11:20:57.689439 Skipping test definition patterns.
11016 11:20:57.692513 + /usr/bin/v4l2-parser.sh -d mtk-vcodec-enc
11017 11:20:57.699044 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11018 11:20:57.699295 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11020 11:20:57.705520 d<4>[ 19.650826] use of bytesused == 0 is deprecated and will be removed in the future,
11021 11:20:57.712069 evice: /dev/vide<4>[ 19.659414] use the actual size instead.
11022 11:20:57.712151 o2
11023 11:20:57.718993 <4>[ 19.667195] ------------[ cut here ]------------
11024 11:20:57.725492 <4>[ 19.672083] get_vaddr_frames() cannot follow VM_IO mapping
11025 11:20:57.735552 <4>[ 19.672235] WARNING: CPU: 7 PID: 305 at drivers/media/common/videobuf2/frame_vector.c:59 get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11026 11:20:57.784502 <4>[ 19.690334] Modules linked in: mt7921e mt7921_common mt76_connac_lib mt76 mac80211 libarc4 cfg80211 mtk_vcodec_enc mtk_vcodec_common cros_ec_rpmsg btusb mtk_vpu btintel uvcvideo btmtk v4l2_mem2mem videobuf2_dma_contig btrtl videobuf2_vmalloc btbcm videobuf2_memops r8153_ecm bluetooth videobuf2_v4l2 videobuf2_common cdc_ether ecdh_generic videodev usbnet ecc crct10dif_ce sbs_battery rfkill mc r8152 elan_i2c elants_i2c hid_google_hammer cros_ec_chardev cros_ec_typec hid_vivaldi_common pcie_mediatek_gen3 mtk_scp mtk_rpmsg mtk_scp_ipi ip_tables x_tables ipv6
11027 11:20:57.794688 <4>[ 19.739724] CPU: 7 PID: 305 Comm: v4l2-compliance Not tainted 6.1.31 #1
11028 11:20:57.797803 <4>[ 19.746590] Hardware name: Google Spherion (rev0 - 3) (DT)
11029 11:20:57.804806 <4>[ 19.752324] pstate: 60400009 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
11030 11:20:57.811406 <4>[ 19.759538] pc : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11031 11:20:57.817977 <4>[ 19.765635] lr : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11032 11:20:57.821031 <4>[ 19.771731] sp : ffff800008e3b850
11033 11:20:57.827631 <4>[ 19.775295] x29: ffff800008e3b850 x28: ffffbcd8e8c70000 x27: ffffbcd8e8c6c238
11034 11:20:57.837462 <4>[ 19.782683] x26: 0000000000000000 x25: ffffbcd8f40dae18 x24: ffff30b50e569298
11035 11:20:57.843978 <4>[ 19.790070] x23: ffff30b509f46000 x22: ffff30b500d48010 x21: 0000000000000000
11036 11:20:57.850809 <4>[ 19.797457] x20: 00000000fffffff2 x19: ffff30b50dc34800 x18: fffffffffffe9578
11037 11:20:57.857243 <4>[ 19.804845] x17: 0000000000000000 x16: ffffbcd8f228bb60 x15: 0000000000000038
11038 11:20:57.867381 <4>[ 19.812232] x14: ffffbcd8f49c34a8 x13: 0000000000000639 x12: 0000000000000213
11039 11:20:57.874162 <4>[ 19.819619] x11: fffffffffffe9578 x10: fffffffffffe9540 x9 : 00000000fffff213
11040 11:20:57.880366 <4>[ 19.827007] x8 : ffffbcd8f49c34a8 x7 : ffffbcd8f4a1b4a8 x6 : 00000000000018e4
11041 11:20:57.887156 <4>[ 19.834394] x5 : ffff30b63efa5a18 x4 : 00000000fffff213 x3 : ffff73dd4aca3000
11042 11:20:57.897144 <4>[ 19.841780] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff30b50dd10ec0
11043 11:20:57.897231 <4>[ 19.849168] Call trace:
11044 11:20:57.903594 <4>[ 19.851865] get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11045 11:20:57.910293 <4>[ 19.857615] vb2_create_framevec+0x50/0xac [videobuf2_memops]
11046 11:20:57.917019 <4>[ 19.863623] vb2_dc_get_userptr+0x9c/0x310 [videobuf2_dma_contig]
11047 11:20:57.923350 <4>[ 19.869983] __prepare_userptr+0x280/0x410 [videobuf2_common]
11048 11:20:57.926736 <4>[ 19.875993] __buf_prepare+0x1a0/0x244 [videobuf2_common]
11049 11:20:57.933707 <4>[ 19.881656] vb2_core_prepare_buf+0x3c/0x140 [videobuf2_common]
11050 11:20:57.939948 <4>[ 19.887839] vb2_prepare_buf+0x68/0xc0 [videobuf2_v4l2]
11051 11:20:57.946524 <4>[ 19.893337] v4l2_m2m_prepare_buf+0x40/0x90 [v4l2_mem2mem]
11052 11:20:57.953611 <4>[ 19.899097] v4l2_m2m_ioctl_prepare_buf+0x18/0x24 [v4l2_mem2mem]
11053 11:20:57.956563 <4>[ 19.905368] v4l_prepare_buf+0x48/0x60 [videodev]
11054 11:20:57.963505 <4>[ 19.910398] __video_do_ioctl+0x184/0x3d0 [videodev]
11055 11:20:57.966549 <4>[ 19.915648] video_usercopy+0x358/0x680 [videodev]
11056 11:20:57.973354 <4>[ 19.920725] video_ioctl2+0x18/0x30 [videodev]
11057 11:20:57.976207 <4>[ 19.925453] v4l2_ioctl+0x40/0x60 [videodev]
11058 11:20:57.980518 <4>[ 19.930008] __arm64_sys_ioctl+0xa8/0xf0
11059 11:20:57.983227 <4>[ 19.934189] invoke_syscall+0x48/0x114
11060 11:20:57.989822 <4>[ 19.938197] el0_svc_common.constprop.0+0x44/0xec
11061 11:20:57.993494 <4>[ 19.943156] do_el0_svc+0x2c/0xd0
11062 11:20:57.996108 <4>[ 19.946725] el0_svc+0x2c/0x84
11063 11:20:57.999454 <4>[ 19.950039] el0t_64_sync_handler+0xb8/0xc0
11064 11:20:58.006035 <4>[ 19.954477] el0t_64_sync+0x18c/0x190
11065 11:20:58.009492 <4>[ 19.958393] ---[ end trace 0000000000000000 ]---
11066 11:20:58.022527 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
11067 11:20:58.031792 v4l2-compliance SHA: 52926c1f2f03 2023-05-25 13:56:39
11068 11:20:58.036967
11069 11:20:58.048502 Compliance test for mtk-vcodec-enc device /dev/video2:
11070 11:20:58.054355
11071 11:20:58.062993 Driver Info:
11072 11:20:58.072204 Driver name : mtk-vcodec-enc
11073 11:20:58.084400 Card type : MT8192 video encoder
11074 11:20:58.094096 Bus info : platform:17020000.vcodec
11075 11:20:58.099803 Driver version : 6.1.31
11076 11:20:58.109392 Capabilities : 0x84204000
11077 11:20:58.118848 Video Memory-to-Memory Multiplanar
11078 11:20:58.127762 Streaming
11079 11:20:58.137611 Extended Pix Format
11080 11:20:58.146693 Device Capabilities
11081 11:20:58.156040 Device Caps : 0x04204000
11082 11:20:58.166002 Video Memory-to-Memory Multiplanar
11083 11:20:58.175327 Streaming
11084 11:20:58.184480 Extended Pix Format
11085 11:20:58.193850 Detected Stateful Encoder
11086 11:20:58.201792
11087 11:20:58.210765 Required ioctls:
11088 11:20:58.225782 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11089 11:20:58.225868 test VIDIOC_QUERYCAP: OK
11090 11:20:58.226119 Received signal: <TESTSET> START Required-ioctls
11091 11:20:58.226198 Starting test_set Required-ioctls
11092 11:20:58.248802 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11093 11:20:58.249064 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11095 11:20:58.252291 test invalid ioctls: OK
11096 11:20:58.270413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11097 11:20:58.270498
11098 11:20:58.270732 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11100 11:20:58.279097 Allow for multiple opens:
11101 11:20:58.286555 <LAVA_SIGNAL_TESTSET STOP>
11102 11:20:58.286810 Received signal: <TESTSET> STOP
11103 11:20:58.286894 Closing test_set Required-ioctls
11104 11:20:58.295983 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11105 11:20:58.296236 Received signal: <TESTSET> START Allow-for-multiple-opens
11106 11:20:58.296307 Starting test_set Allow-for-multiple-opens
11107 11:20:58.298858 test second /dev/video2 open: OK
11108 11:20:58.321160 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video2-open RESULT=pass>
11109 11:20:58.321416 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video2-open RESULT=pass
11111 11:20:58.324611 test VIDIOC_QUERYCAP: OK
11112 11:20:58.344852 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11113 11:20:58.345105 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11115 11:20:58.348323 test VIDIOC_G/S_PRIORITY: OK
11116 11:20:58.369743 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11117 11:20:58.369995 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11119 11:20:58.373273 test for unlimited opens: OK
11120 11:20:58.393937 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11121 11:20:58.394016
11122 11:20:58.394246 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11124 11:20:58.403358 Debug ioctls:
11125 11:20:58.409671 <LAVA_SIGNAL_TESTSET STOP>
11126 11:20:58.409921 Received signal: <TESTSET> STOP
11127 11:20:58.410003 Closing test_set Allow-for-multiple-opens
11128 11:20:58.419689 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11129 11:20:58.419979 Received signal: <TESTSET> START Debug-ioctls
11130 11:20:58.420078 Starting test_set Debug-ioctls
11131 11:20:58.422525 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11132 11:20:58.442649 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11133 11:20:58.442900 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11135 11:20:58.449154 test VIDIOC_LOG_STATUS: OK (Not Supported)
11136 11:20:58.466562 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11137 11:20:58.466646
11138 11:20:58.466850 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11140 11:20:58.476992 Input ioctls:
11141 11:20:58.484321 <LAVA_SIGNAL_TESTSET STOP>
11142 11:20:58.484572 Received signal: <TESTSET> STOP
11143 11:20:58.484642 Closing test_set Debug-ioctls
11144 11:20:58.493979 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11145 11:20:58.494231 Received signal: <TESTSET> START Input-ioctls
11146 11:20:58.494301 Starting test_set Input-ioctls
11147 11:20:58.497569 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11148 11:20:58.520609 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11149 11:20:58.520862 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11151 11:20:58.523945 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11152 11:20:58.541871 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11153 11:20:58.542123 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11155 11:20:58.548552 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11156 11:20:58.565904 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11157 11:20:58.566158 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11159 11:20:58.572031 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11160 11:20:58.589451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11161 11:20:58.589703 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11163 11:20:58.592409 test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
11164 11:20:58.613144 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11165 11:20:58.613397 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11167 11:20:58.616703 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11168 11:20:58.637619 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11169 11:20:58.637871 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11171 11:20:58.641193 Inputs: 0 Audio Inputs: 0 Tuners: 0
11172 11:20:58.647405
11173 11:20:58.664376 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11174 11:20:58.684960 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11175 11:20:58.685319 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11177 11:20:58.691479 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11178 11:20:58.710278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11179 11:20:58.711016 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11181 11:20:58.716454 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11182 11:20:58.733935 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11183 11:20:58.734650 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11185 11:20:58.740421 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11186 11:20:58.757756 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11187 11:20:58.758474 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11189 11:20:58.764152 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11190 11:20:58.781741 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11191 11:20:58.782208
11192 11:20:58.782821 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11194 11:20:58.799811 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11195 11:20:58.821740 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11196 11:20:58.822459 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11198 11:20:58.828732 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11199 11:20:58.848613 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11200 11:20:58.849338 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11202 11:20:58.852102 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11203 11:20:58.869222 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11204 11:20:58.869939 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11206 11:20:58.872808 test VIDIOC_G/S_EDID: OK (Not Supported)
11207 11:20:58.893461 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11208 11:20:58.893939
11209 11:20:58.894580 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11211 11:20:58.903828 Control ioctls:
11212 11:20:58.910164 <LAVA_SIGNAL_TESTSET STOP>
11213 11:20:58.910953 Received signal: <TESTSET> STOP
11214 11:20:58.911355 Closing test_set Input-ioctls
11215 11:20:58.919247 <LAVA_SIGNAL_TESTSET START Control-ioctls>
11216 11:20:58.919974 Received signal: <TESTSET> START Control-ioctls
11217 11:20:58.920376 Starting test_set Control-ioctls
11218 11:20:58.922141 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11219 11:20:58.945120 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11220 11:20:58.945596 test VIDIOC_QUERYCTRL: OK
11221 11:20:58.946225 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11223 11:20:58.966391 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11224 11:20:58.967165 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11226 11:20:58.969276 test VIDIOC_G/S_CTRL: OK
11227 11:20:58.990105 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11228 11:20:58.990869 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11230 11:20:58.993438 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11231 11:20:59.013229 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11232 11:20:59.013971 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11234 11:20:59.022953 fail: ../utils/v4l2-compliance/v4l2-test-controls.cpp(1167): node->codec_mask & STATEFUL_ENCODER
11235 11:20:59.026517 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: FAIL
11236 11:20:59.049011 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail>
11237 11:20:59.049754 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=fail
11239 11:20:59.052378 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11240 11:20:59.069139 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11241 11:20:59.069868 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11243 11:20:59.072595 Standard Controls: 16 Private Controls: 0
11244 11:20:59.078508
11245 11:20:59.087346 Format ioctls:
11246 11:20:59.093803 <LAVA_SIGNAL_TESTSET STOP>
11247 11:20:59.094640 Received signal: <TESTSET> STOP
11248 11:20:59.095112 Closing test_set Control-ioctls
11249 11:20:59.102594 <LAVA_SIGNAL_TESTSET START Format-ioctls>
11250 11:20:59.103294 Received signal: <TESTSET> START Format-ioctls
11251 11:20:59.103699 Starting test_set Format-ioctls
11252 11:20:59.105965 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11253 11:20:59.129881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11254 11:20:59.130580 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11256 11:20:59.132837 test VIDIOC_G/S_PARM: OK
11257 11:20:59.150559 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11258 11:20:59.151249 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11260 11:20:59.154317 test VIDIOC_G_FBUF: OK (Not Supported)
11261 11:20:59.174234 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11262 11:20:59.175148 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11264 11:20:59.177538 test VIDIOC_G_FMT: OK
11265 11:20:59.198001 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11266 11:20:59.198680 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11268 11:20:59.201075 test VIDIOC_TRY_FMT: OK
11269 11:20:59.221636 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11270 11:20:59.222357 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11272 11:20:59.231984 fail: ../utils/v4l2-compliance/v4l2-test-formats.cpp(924): sel.r.width != fmt.g_width()
11273 11:20:59.232441 test VIDIOC_S_FMT: FAIL
11274 11:20:59.255341 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail>
11275 11:20:59.256029 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=fail
11277 11:20:59.261819 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11278 11:20:59.280932 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11279 11:20:59.281602 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11281 11:20:59.283628 test Cropping: OK
11282 11:20:59.304850 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11283 11:20:59.305576 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11285 11:20:59.308005 test Composing: OK (Not Supported)
11286 11:20:59.329881 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11287 11:20:59.330624 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11289 11:20:59.333079 test Scaling: OK (Not Supported)
11290 11:20:59.352999 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11291 11:20:59.353427
11292 11:20:59.354156 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11294 11:20:59.363599 Codec ioctls:
11295 11:20:59.369875 <LAVA_SIGNAL_TESTSET STOP>
11296 11:20:59.370528 Received signal: <TESTSET> STOP
11297 11:20:59.371049 Closing test_set Format-ioctls
11298 11:20:59.380054 <LAVA_SIGNAL_TESTSET START Codec-ioctls>
11299 11:20:59.380726 Received signal: <TESTSET> START Codec-ioctls
11300 11:20:59.381148 Starting test_set Codec-ioctls
11301 11:20:59.383004 test VIDIOC_(TRY_)ENCODER_CMD: OK
11302 11:20:59.404727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11303 11:20:59.405430 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11305 11:20:59.411802 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11306 11:20:59.429354 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11307 11:20:59.430117 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11309 11:20:59.436079 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11310 11:20:59.453353 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11311 11:20:59.453835
11312 11:20:59.454577 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11314 11:20:59.462898 Buffer ioctls:
11315 11:20:59.469447 <LAVA_SIGNAL_TESTSET STOP>
11316 11:20:59.470193 Received signal: <TESTSET> STOP
11317 11:20:59.470632 Closing test_set Codec-ioctls
11318 11:20:59.478908 <LAVA_SIGNAL_TESTSET START Buffer-ioctls>
11319 11:20:59.479585 Received signal: <TESTSET> START Buffer-ioctls
11320 11:20:59.479981 Starting test_set Buffer-ioctls
11321 11:20:59.481786 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11322 11:20:59.505102 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11323 11:20:59.505640 test VIDIOC_EXPBUF: OK
11324 11:20:59.506346 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11326 11:20:59.532007 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11327 11:20:59.532727 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11329 11:20:59.535077 test Requests: OK (Not Supported)
11330 11:20:59.557633 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11331 11:20:59.558118
11332 11:20:59.558903 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11334 11:20:59.568599 Test input 0:
11335 11:20:59.577899
11336 11:20:59.588381 Streaming ioctls:
11337 11:20:59.594982 <LAVA_SIGNAL_TESTSET STOP>
11338 11:20:59.595661 Received signal: <TESTSET> STOP
11339 11:20:59.596066 Closing test_set Buffer-ioctls
11340 11:20:59.605243 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11341 11:20:59.605919 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11342 11:20:59.606317 Starting test_set Streaming-ioctls_Test-input-0
11343 11:20:59.608609 test read/write: OK (Not Supported)
11344 11:20:59.629843 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11345 11:20:59.630571 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11347 11:20:59.636394 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2778): node->streamon(q.g_type())
11348 11:20:59.646022 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(2825): testBlockingDQBuf(node, q)
11349 11:20:59.650702 test blocking wait: FAIL
11350 11:20:59.673732 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=fail>
11351 11:20:59.674605 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=fail
11353 11:20:59.683744 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11354 11:20:59.687208 test MMAP (select): FAIL
11355 11:20:59.709038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11356 11:20:59.709716 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11358 11:20:59.715945 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1430): node->streamon(q.g_type())
11359 11:20:59.719198 test MMAP (epoll): FAIL
11360 11:20:59.743997 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11361 11:20:59.744842 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11363 11:20:59.750665 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1602): ret && ret != ENOTTY (got 22)
11364 11:20:59.760801 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1733): setupUserPtr(node, q)
11365 11:20:59.764071 test USERPTR (select): FAIL
11366 11:20:59.787570 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=fail>
11367 11:20:59.788249 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=fail
11369 11:20:59.793678 test DMABUF: Cannot test, specify --expbuf-device
11370 11:20:59.794104
11371 11:20:59.813823 Total for mtk-vcodec-enc device /dev/video2: 50, Succeeded: 44, Failed: 6, Warnings: 0
11372 11:20:59.816847 <LAVA_TEST_RUNNER EXIT>
11373 11:20:59.817612 ok: lava_test_shell seems to have completed
11374 11:20:59.818040 Marking unfinished test run as failed
11376 11:20:59.823605 Composing:
result: pass
set: Format-ioctls
Cropping:
result: pass
set: Format-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls
Scaling:
result: pass
set: Format-ioctls
USERPTR-select:
result: fail
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls
VIDIOC_G_FMT:
result: pass
set: Format-ioctls
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls
VIDIOC_S_FMT:
result: fail
set: Format-ioctls
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: fail
set: Control-ioctls
blocking-wait:
result: fail
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video2-open:
result: pass
set: Allow-for-multiple-opens
11377 11:20:59.824229 end: 3.1 lava-test-shell (duration 00:00:03) [common]
11378 11:20:59.824666 end: 3 lava-test-retry (duration 00:00:03) [common]
11379 11:20:59.825113 start: 4 finalize (timeout 00:07:43) [common]
11380 11:20:59.825568 start: 4.1 power-off (timeout 00:00:30) [common]
11381 11:20:59.826307 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-8' '--port=1' '--command=off'
11382 11:20:59.934784 >> Command sent successfully.
11383 11:20:59.937091 Returned 0 in 0 seconds
11384 11:21:00.037462 end: 4.1 power-off (duration 00:00:00) [common]
11386 11:21:00.037781 start: 4.2 read-feedback (timeout 00:07:43) [common]
11387 11:21:00.038036 Listened to connection for namespace 'common' for up to 1s
11388 11:21:01.038964 Finalising connection for namespace 'common'
11389 11:21:01.039189 Disconnecting from shell: Finalise
11390 11:21:01.039275 / #
11391 11:21:01.139570 end: 4.2 read-feedback (duration 00:00:01) [common]
11392 11:21:01.139771 end: 4 finalize (duration 00:00:01) [common]
11393 11:21:01.139917 Cleaning after the job
11394 11:21:01.140047 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591280/tftp-deploy-_r2evtbo/ramdisk
11395 11:21:01.144473 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591280/tftp-deploy-_r2evtbo/kernel
11396 11:21:01.150296 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591280/tftp-deploy-_r2evtbo/dtb
11397 11:21:01.150461 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591280/tftp-deploy-_r2evtbo/modules
11398 11:21:01.155723 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10591280
11399 11:21:01.214499 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10591280
11400 11:21:01.214738 Job finished correctly