Boot log: mt8192-asurada-spherion-r0
- Errors: 1
- Kernel Errors: 31
- Boot result: PASS
- Warnings: 1
- Kernel Warnings: 62
1 11:15:39.687474 lava-dispatcher, installed at version: 2023.05.1
2 11:15:39.687682 start: 0 validate
3 11:15:39.687816 Start time: 2023-06-05 11:15:39.687809+00:00 (UTC)
4 11:15:39.687935 Using caching service: 'http://localhost/cache/?uri=%s'
5 11:15:39.688106 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye-v4l2%2F20230527.0%2Farm64%2Frootfs.cpio.gz exists
6 11:15:39.978221 Using caching service: 'http://localhost/cache/?uri=%s'
7 11:15:39.978403 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 11:15:40.269323 Using caching service: 'http://localhost/cache/?uri=%s'
9 11:15:40.269503 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 11:15:40.556180 Using caching service: 'http://localhost/cache/?uri=%s'
11 11:15:40.556372 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fcip%2Flinux-6.1.y-cip%2Fv6.1.26-1298-g61395b9756bd5%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 11:15:40.843203 validate duration: 1.16
14 11:15:40.843475 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 11:15:40.843580 start: 1.1 download-retry (timeout 00:10:00) [common]
16 11:15:40.843668 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 11:15:40.843792 Not decompressing ramdisk as can be used compressed.
18 11:15:40.843881 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye-v4l2/20230527.0/arm64/rootfs.cpio.gz
19 11:15:40.843947 saving as /var/lib/lava/dispatcher/tmp/10591263/tftp-deploy-_xk_g__a/ramdisk/rootfs.cpio.gz
20 11:15:40.844008 total size: 27151647 (25MB)
21 11:15:40.849652 progress 0% (0MB)
22 11:15:40.858028 progress 5% (1MB)
23 11:15:40.865819 progress 10% (2MB)
24 11:15:40.873813 progress 15% (3MB)
25 11:15:40.880705 progress 20% (5MB)
26 11:15:40.888159 progress 25% (6MB)
27 11:15:40.895493 progress 30% (7MB)
28 11:15:40.902858 progress 35% (9MB)
29 11:15:40.910055 progress 40% (10MB)
30 11:15:40.917429 progress 45% (11MB)
31 11:15:40.924787 progress 50% (12MB)
32 11:15:40.931661 progress 55% (14MB)
33 11:15:40.938810 progress 60% (15MB)
34 11:15:40.945748 progress 65% (16MB)
35 11:15:40.952992 progress 70% (18MB)
36 11:15:40.960109 progress 75% (19MB)
37 11:15:40.967221 progress 80% (20MB)
38 11:15:40.974438 progress 85% (22MB)
39 11:15:40.981554 progress 90% (23MB)
40 11:15:40.988720 progress 95% (24MB)
41 11:15:40.995712 progress 100% (25MB)
42 11:15:40.995907 25MB downloaded in 0.15s (170.47MB/s)
43 11:15:40.996110 end: 1.1.1 http-download (duration 00:00:00) [common]
45 11:15:40.996356 end: 1.1 download-retry (duration 00:00:00) [common]
46 11:15:40.996447 start: 1.2 download-retry (timeout 00:10:00) [common]
47 11:15:40.996529 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 11:15:40.996665 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 11:15:40.996739 saving as /var/lib/lava/dispatcher/tmp/10591263/tftp-deploy-_xk_g__a/kernel/Image
50 11:15:40.996800 total size: 45746688 (43MB)
51 11:15:40.996859 No compression specified
52 11:15:40.997957 progress 0% (0MB)
53 11:15:41.010047 progress 5% (2MB)
54 11:15:41.022071 progress 10% (4MB)
55 11:15:41.034349 progress 15% (6MB)
56 11:15:41.046446 progress 20% (8MB)
57 11:15:41.058461 progress 25% (10MB)
58 11:15:41.070351 progress 30% (13MB)
59 11:15:41.082192 progress 35% (15MB)
60 11:15:41.094171 progress 40% (17MB)
61 11:15:41.106142 progress 45% (19MB)
62 11:15:41.118221 progress 50% (21MB)
63 11:15:41.130113 progress 55% (24MB)
64 11:15:41.142274 progress 60% (26MB)
65 11:15:41.154338 progress 65% (28MB)
66 11:15:41.166358 progress 70% (30MB)
67 11:15:41.178224 progress 75% (32MB)
68 11:15:41.189889 progress 80% (34MB)
69 11:15:41.201778 progress 85% (37MB)
70 11:15:41.213806 progress 90% (39MB)
71 11:15:41.225563 progress 95% (41MB)
72 11:15:41.237531 progress 100% (43MB)
73 11:15:41.237662 43MB downloaded in 0.24s (181.13MB/s)
74 11:15:41.237816 end: 1.2.1 http-download (duration 00:00:00) [common]
76 11:15:41.238049 end: 1.2 download-retry (duration 00:00:00) [common]
77 11:15:41.238141 start: 1.3 download-retry (timeout 00:10:00) [common]
78 11:15:41.238228 start: 1.3.1 http-download (timeout 00:10:00) [common]
79 11:15:41.238365 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 11:15:41.238436 saving as /var/lib/lava/dispatcher/tmp/10591263/tftp-deploy-_xk_g__a/dtb/mt8192-asurada-spherion-r0.dtb
81 11:15:41.238496 total size: 46924 (0MB)
82 11:15:41.238554 No compression specified
83 11:15:41.239692 progress 69% (0MB)
84 11:15:41.239965 progress 100% (0MB)
85 11:15:41.240163 0MB downloaded in 0.00s (26.90MB/s)
86 11:15:41.240281 end: 1.3.1 http-download (duration 00:00:00) [common]
88 11:15:41.240510 end: 1.3 download-retry (duration 00:00:00) [common]
89 11:15:41.240593 start: 1.4 download-retry (timeout 00:10:00) [common]
90 11:15:41.240681 start: 1.4.1 http-download (timeout 00:10:00) [common]
91 11:15:41.240793 downloading http://storage.kernelci.org/cip/linux-6.1.y-cip/v6.1.26-1298-g61395b9756bd5/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 11:15:41.240859 saving as /var/lib/lava/dispatcher/tmp/10591263/tftp-deploy-_xk_g__a/modules/modules.tar
93 11:15:41.240924 total size: 8547328 (8MB)
94 11:15:41.240985 Using unxz to decompress xz
95 11:15:41.244666 progress 0% (0MB)
96 11:15:41.266015 progress 5% (0MB)
97 11:15:41.290207 progress 10% (0MB)
98 11:15:41.315550 progress 15% (1MB)
99 11:15:41.339456 progress 20% (1MB)
100 11:15:41.364708 progress 25% (2MB)
101 11:15:41.388992 progress 30% (2MB)
102 11:15:41.413459 progress 35% (2MB)
103 11:15:41.439343 progress 40% (3MB)
104 11:15:41.464829 progress 45% (3MB)
105 11:15:41.488180 progress 50% (4MB)
106 11:15:41.510344 progress 55% (4MB)
107 11:15:41.534772 progress 60% (4MB)
108 11:15:41.559414 progress 65% (5MB)
109 11:15:41.584010 progress 70% (5MB)
110 11:15:41.609966 progress 75% (6MB)
111 11:15:41.638561 progress 80% (6MB)
112 11:15:41.660688 progress 85% (6MB)
113 11:15:41.685180 progress 90% (7MB)
114 11:15:41.708119 progress 95% (7MB)
115 11:15:41.731217 progress 100% (8MB)
116 11:15:41.737139 8MB downloaded in 0.50s (16.43MB/s)
117 11:15:41.737421 end: 1.4.1 http-download (duration 00:00:00) [common]
119 11:15:41.737680 end: 1.4 download-retry (duration 00:00:00) [common]
120 11:15:41.737770 start: 1.5 prepare-tftp-overlay (timeout 00:09:59) [common]
121 11:15:41.737863 start: 1.5.1 extract-nfsrootfs (timeout 00:09:59) [common]
122 11:15:41.737945 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 11:15:41.738027 start: 1.5.2 lava-overlay (timeout 00:09:59) [common]
124 11:15:41.738246 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/10591263/lava-overlay-9ic_9ij_
125 11:15:41.738373 makedir: /var/lib/lava/dispatcher/tmp/10591263/lava-overlay-9ic_9ij_/lava-10591263/bin
126 11:15:41.738473 makedir: /var/lib/lava/dispatcher/tmp/10591263/lava-overlay-9ic_9ij_/lava-10591263/tests
127 11:15:41.738567 makedir: /var/lib/lava/dispatcher/tmp/10591263/lava-overlay-9ic_9ij_/lava-10591263/results
128 11:15:41.738687 Creating /var/lib/lava/dispatcher/tmp/10591263/lava-overlay-9ic_9ij_/lava-10591263/bin/lava-add-keys
129 11:15:41.738827 Creating /var/lib/lava/dispatcher/tmp/10591263/lava-overlay-9ic_9ij_/lava-10591263/bin/lava-add-sources
130 11:15:41.738950 Creating /var/lib/lava/dispatcher/tmp/10591263/lava-overlay-9ic_9ij_/lava-10591263/bin/lava-background-process-start
131 11:15:41.739074 Creating /var/lib/lava/dispatcher/tmp/10591263/lava-overlay-9ic_9ij_/lava-10591263/bin/lava-background-process-stop
132 11:15:41.739192 Creating /var/lib/lava/dispatcher/tmp/10591263/lava-overlay-9ic_9ij_/lava-10591263/bin/lava-common-functions
133 11:15:41.739308 Creating /var/lib/lava/dispatcher/tmp/10591263/lava-overlay-9ic_9ij_/lava-10591263/bin/lava-echo-ipv4
134 11:15:41.739427 Creating /var/lib/lava/dispatcher/tmp/10591263/lava-overlay-9ic_9ij_/lava-10591263/bin/lava-install-packages
135 11:15:41.739544 Creating /var/lib/lava/dispatcher/tmp/10591263/lava-overlay-9ic_9ij_/lava-10591263/bin/lava-installed-packages
136 11:15:41.739659 Creating /var/lib/lava/dispatcher/tmp/10591263/lava-overlay-9ic_9ij_/lava-10591263/bin/lava-os-build
137 11:15:41.739775 Creating /var/lib/lava/dispatcher/tmp/10591263/lava-overlay-9ic_9ij_/lava-10591263/bin/lava-probe-channel
138 11:15:41.739892 Creating /var/lib/lava/dispatcher/tmp/10591263/lava-overlay-9ic_9ij_/lava-10591263/bin/lava-probe-ip
139 11:15:41.740008 Creating /var/lib/lava/dispatcher/tmp/10591263/lava-overlay-9ic_9ij_/lava-10591263/bin/lava-target-ip
140 11:15:41.740163 Creating /var/lib/lava/dispatcher/tmp/10591263/lava-overlay-9ic_9ij_/lava-10591263/bin/lava-target-mac
141 11:15:41.740279 Creating /var/lib/lava/dispatcher/tmp/10591263/lava-overlay-9ic_9ij_/lava-10591263/bin/lava-target-storage
142 11:15:41.740399 Creating /var/lib/lava/dispatcher/tmp/10591263/lava-overlay-9ic_9ij_/lava-10591263/bin/lava-test-case
143 11:15:41.740516 Creating /var/lib/lava/dispatcher/tmp/10591263/lava-overlay-9ic_9ij_/lava-10591263/bin/lava-test-event
144 11:15:41.740632 Creating /var/lib/lava/dispatcher/tmp/10591263/lava-overlay-9ic_9ij_/lava-10591263/bin/lava-test-feedback
145 11:15:41.740747 Creating /var/lib/lava/dispatcher/tmp/10591263/lava-overlay-9ic_9ij_/lava-10591263/bin/lava-test-raise
146 11:15:41.740865 Creating /var/lib/lava/dispatcher/tmp/10591263/lava-overlay-9ic_9ij_/lava-10591263/bin/lava-test-reference
147 11:15:41.740981 Creating /var/lib/lava/dispatcher/tmp/10591263/lava-overlay-9ic_9ij_/lava-10591263/bin/lava-test-runner
148 11:15:41.741096 Creating /var/lib/lava/dispatcher/tmp/10591263/lava-overlay-9ic_9ij_/lava-10591263/bin/lava-test-set
149 11:15:41.741214 Creating /var/lib/lava/dispatcher/tmp/10591263/lava-overlay-9ic_9ij_/lava-10591263/bin/lava-test-shell
150 11:15:41.741332 Updating /var/lib/lava/dispatcher/tmp/10591263/lava-overlay-9ic_9ij_/lava-10591263/bin/lava-install-packages (oe)
151 11:15:41.741477 Updating /var/lib/lava/dispatcher/tmp/10591263/lava-overlay-9ic_9ij_/lava-10591263/bin/lava-installed-packages (oe)
152 11:15:41.741591 Creating /var/lib/lava/dispatcher/tmp/10591263/lava-overlay-9ic_9ij_/lava-10591263/environment
153 11:15:41.741685 LAVA metadata
154 11:15:41.741757 - LAVA_JOB_ID=10591263
155 11:15:41.741821 - LAVA_DISPATCHER_IP=192.168.201.1
156 11:15:41.741923 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:59) [common]
157 11:15:41.741989 skipped lava-vland-overlay
158 11:15:41.742061 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 11:15:41.742139 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:59) [common]
160 11:15:41.742200 skipped lava-multinode-overlay
161 11:15:41.742273 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 11:15:41.742352 start: 1.5.2.3 test-definition (timeout 00:09:59) [common]
163 11:15:41.742422 Loading test definitions
164 11:15:41.742510 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:59) [common]
165 11:15:41.742585 Using /lava-10591263 at stage 0
166 11:15:41.742877 uuid=10591263_1.5.2.3.1 testdef=None
167 11:15:41.742962 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 11:15:41.743044 start: 1.5.2.3.2 test-overlay (timeout 00:09:59) [common]
169 11:15:41.743537 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 11:15:41.743762 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:59) [common]
172 11:15:41.744389 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 11:15:41.744616 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:59) [common]
175 11:15:41.745186 runner path: /var/lib/lava/dispatcher/tmp/10591263/lava-overlay-9ic_9ij_/lava-10591263/0/tests/0_v4l2-compliance-uvc test_uuid 10591263_1.5.2.3.1
176 11:15:41.745337 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 11:15:41.745544 Creating lava-test-runner.conf files
179 11:15:41.745606 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/10591263/lava-overlay-9ic_9ij_/lava-10591263/0 for stage 0
180 11:15:41.745691 - 0_v4l2-compliance-uvc
181 11:15:41.745784 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
182 11:15:41.745865 start: 1.5.2.4 compress-overlay (timeout 00:09:59) [common]
183 11:15:41.752310 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
184 11:15:41.752412 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:59) [common]
185 11:15:41.752498 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
186 11:15:41.752581 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
187 11:15:41.752670 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:59) [common]
188 11:15:42.447761 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:01) [common]
189 11:15:42.448153 start: 1.5.4 extract-modules (timeout 00:09:58) [common]
190 11:15:42.448267 extracting modules file /var/lib/lava/dispatcher/tmp/10591263/tftp-deploy-_xk_g__a/modules/modules.tar to /var/lib/lava/dispatcher/tmp/10591263/extract-overlay-ramdisk-v30drjct/ramdisk
191 11:15:42.652516 end: 1.5.4 extract-modules (duration 00:00:00) [common]
192 11:15:42.652683 start: 1.5.5 apply-overlay-tftp (timeout 00:09:58) [common]
193 11:15:42.652783 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10591263/compress-overlay-e9xa81ty/overlay-1.5.2.4.tar.gz to ramdisk
194 11:15:42.652854 [common] Applying overlay /var/lib/lava/dispatcher/tmp/10591263/compress-overlay-e9xa81ty/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/10591263/extract-overlay-ramdisk-v30drjct/ramdisk
195 11:15:42.659063 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
196 11:15:42.659172 start: 1.5.6 configure-preseed-file (timeout 00:09:58) [common]
197 11:15:42.659261 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
198 11:15:42.659350 start: 1.5.7 compress-ramdisk (timeout 00:09:58) [common]
199 11:15:42.659429 Building ramdisk /var/lib/lava/dispatcher/tmp/10591263/extract-overlay-ramdisk-v30drjct/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/10591263/extract-overlay-ramdisk-v30drjct/ramdisk
200 11:15:43.252803 >> 230336 blocks
201 11:15:47.193457 rename /var/lib/lava/dispatcher/tmp/10591263/extract-overlay-ramdisk-v30drjct/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/10591263/tftp-deploy-_xk_g__a/ramdisk/ramdisk.cpio.gz
202 11:15:47.193867 end: 1.5.7 compress-ramdisk (duration 00:00:05) [common]
203 11:15:47.193987 start: 1.5.8 prepare-kernel (timeout 00:09:54) [common]
204 11:15:47.194087 start: 1.5.8.1 prepare-fit (timeout 00:09:54) [common]
205 11:15:47.194202 Calling: 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/10591263/tftp-deploy-_xk_g__a/kernel/Image'
206 11:15:58.519628 Returned 0 in 11 seconds
207 11:15:58.620525 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/10591263/tftp-deploy-_xk_g__a/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/10591263/tftp-deploy-_xk_g__a/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/10591263/tftp-deploy-_xk_g__a/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/10591263/tftp-deploy-_xk_g__a/kernel/image.itb
208 11:15:59.215889 output: FIT description: Kernel Image image with one or more FDT blobs
209 11:15:59.216239 output: Created: Mon Jun 5 12:15:59 2023
210 11:15:59.216311 output: Image 0 (kernel-1)
211 11:15:59.216377 output: Description:
212 11:15:59.216441 output: Created: Mon Jun 5 12:15:59 2023
213 11:15:59.216497 output: Type: Kernel Image
214 11:15:59.216557 output: Compression: lzma compressed
215 11:15:59.216617 output: Data Size: 10086024 Bytes = 9849.63 KiB = 9.62 MiB
216 11:15:59.216674 output: Architecture: AArch64
217 11:15:59.216731 output: OS: Linux
218 11:15:59.216789 output: Load Address: 0x00000000
219 11:15:59.216845 output: Entry Point: 0x00000000
220 11:15:59.216901 output: Hash algo: crc32
221 11:15:59.216954 output: Hash value: eb1cf9b8
222 11:15:59.217006 output: Image 1 (fdt-1)
223 11:15:59.217058 output: Description: mt8192-asurada-spherion-r0
224 11:15:59.217110 output: Created: Mon Jun 5 12:15:59 2023
225 11:15:59.217163 output: Type: Flat Device Tree
226 11:15:59.217215 output: Compression: uncompressed
227 11:15:59.217266 output: Data Size: 46924 Bytes = 45.82 KiB = 0.04 MiB
228 11:15:59.217319 output: Architecture: AArch64
229 11:15:59.217371 output: Hash algo: crc32
230 11:15:59.217423 output: Hash value: 1df858fa
231 11:15:59.217475 output: Image 2 (ramdisk-1)
232 11:15:59.217527 output: Description: unavailable
233 11:15:59.217578 output: Created: Mon Jun 5 12:15:59 2023
234 11:15:59.217630 output: Type: RAMDisk Image
235 11:15:59.217682 output: Compression: Unknown Compression
236 11:15:59.217735 output: Data Size: 40124341 Bytes = 39183.93 KiB = 38.27 MiB
237 11:15:59.217787 output: Architecture: AArch64
238 11:15:59.217839 output: OS: Linux
239 11:15:59.217890 output: Load Address: unavailable
240 11:15:59.217941 output: Entry Point: unavailable
241 11:15:59.217993 output: Hash algo: crc32
242 11:15:59.218044 output: Hash value: 1a336cae
243 11:15:59.218096 output: Default Configuration: 'conf-1'
244 11:15:59.218148 output: Configuration 0 (conf-1)
245 11:15:59.218200 output: Description: mt8192-asurada-spherion-r0
246 11:15:59.218252 output: Kernel: kernel-1
247 11:15:59.218303 output: Init Ramdisk: ramdisk-1
248 11:15:59.218355 output: FDT: fdt-1
249 11:15:59.218406 output: Loadables: kernel-1
250 11:15:59.218457 output:
251 11:15:59.218642 end: 1.5.8.1 prepare-fit (duration 00:00:12) [common]
252 11:15:59.218741 end: 1.5.8 prepare-kernel (duration 00:00:12) [common]
253 11:15:59.218842 end: 1.5 prepare-tftp-overlay (duration 00:00:17) [common]
254 11:15:59.218933 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:42) [common]
255 11:15:59.219006 No LXC device requested
256 11:15:59.219082 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
257 11:15:59.219166 start: 1.7 deploy-device-env (timeout 00:09:42) [common]
258 11:15:59.219240 end: 1.7 deploy-device-env (duration 00:00:00) [common]
259 11:15:59.219309 Checking files for TFTP limit of 4294967296 bytes.
260 11:15:59.219787 end: 1 tftp-deploy (duration 00:00:18) [common]
261 11:15:59.219888 start: 2 depthcharge-action (timeout 00:05:00) [common]
262 11:15:59.219979 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
263 11:15:59.220107 substitutions:
264 11:15:59.220175 - {DTB}: 10591263/tftp-deploy-_xk_g__a/dtb/mt8192-asurada-spherion-r0.dtb
265 11:15:59.220237 - {INITRD}: 10591263/tftp-deploy-_xk_g__a/ramdisk/ramdisk.cpio.gz
266 11:15:59.220297 - {KERNEL}: 10591263/tftp-deploy-_xk_g__a/kernel/Image
267 11:15:59.220354 - {LAVA_MAC}: None
268 11:15:59.220410 - {PRESEED_CONFIG}: None
269 11:15:59.220464 - {PRESEED_LOCAL}: None
270 11:15:59.220518 - {RAMDISK}: 10591263/tftp-deploy-_xk_g__a/ramdisk/ramdisk.cpio.gz
271 11:15:59.220572 - {ROOT_PART}: None
272 11:15:59.220626 - {ROOT}: None
273 11:15:59.220679 - {SERVER_IP}: 192.168.201.1
274 11:15:59.220732 - {TEE}: None
275 11:15:59.220786 Parsed boot commands:
276 11:15:59.220839 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
277 11:15:59.221006 Parsed boot commands: tftpboot 192.168.201.1 10591263/tftp-deploy-_xk_g__a/kernel/image.itb 10591263/tftp-deploy-_xk_g__a/kernel/cmdline
278 11:15:59.221091 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
279 11:15:59.221172 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
280 11:15:59.221260 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
281 11:15:59.221345 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
282 11:15:59.221413 Not connected, no need to disconnect.
283 11:15:59.221485 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
284 11:15:59.221562 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
285 11:15:59.221627 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-2'
286 11:15:59.224897 Setting prompt string to ['lava-test: # ']
287 11:15:59.225236 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
288 11:15:59.225343 end: 2.2.1 reset-connection (duration 00:00:00) [common]
289 11:15:59.225434 start: 2.2.2 reset-device (timeout 00:05:00) [common]
290 11:15:59.225529 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
291 11:15:59.225724 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
292 11:16:04.360749 >> Command sent successfully.
293 11:16:04.362994 Returned 0 in 5 seconds
294 11:16:04.463479 end: 2.2.2.1 pdu-reboot (duration 00:00:05) [common]
296 11:16:04.464200 end: 2.2.2 reset-device (duration 00:00:05) [common]
297 11:16:04.464386 start: 2.2.3 depthcharge-start (timeout 00:04:55) [common]
298 11:16:04.464565 Setting prompt string to 'Starting depthcharge on Spherion...'
299 11:16:04.464655 Changing prompt to 'Starting depthcharge on Spherion...'
300 11:16:04.464745 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
301 11:16:04.465054 [Enter `^Ec?' for help]
302 11:16:04.638479
303 11:16:04.638645
304 11:16:04.638731 F0: 102B 0000
305 11:16:04.638808
306 11:16:04.638881 F3: 1001 0000 [0200]
307 11:16:04.638952
308 11:16:04.641680 F3: 1001 0000
309 11:16:04.641792
310 11:16:04.641881 F7: 102D 0000
311 11:16:04.641965
312 11:16:04.642044 F1: 0000 0000
313 11:16:04.645478
314 11:16:04.645600 V0: 0000 0000 [0001]
315 11:16:04.645697
316 11:16:04.645788 00: 0007 8000
317 11:16:04.645878
318 11:16:04.648759 01: 0000 0000
319 11:16:04.648842
320 11:16:04.648907 BP: 0C00 0209 [0000]
321 11:16:04.648969
322 11:16:04.652603 G0: 1182 0000
323 11:16:04.652685
324 11:16:04.652750 EC: 0000 0021 [4000]
325 11:16:04.652811
326 11:16:04.656878 S7: 0000 0000 [0000]
327 11:16:04.656966
328 11:16:04.657035 CC: 0000 0000 [0001]
329 11:16:04.657101
330 11:16:04.660243 T0: 0000 0040 [010F]
331 11:16:04.660664
332 11:16:04.661000 Jump to BL
333 11:16:04.661314
334 11:16:04.685426
335 11:16:04.685509
336 11:16:04.685575
337 11:16:04.692792 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
338 11:16:04.696556 ARM64: Exception handlers installed.
339 11:16:04.699899 ARM64: Testing exception
340 11:16:04.703557 ARM64: Done test exception
341 11:16:04.711177 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
342 11:16:04.718152 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
343 11:16:04.725086 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
344 11:16:04.735711 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
345 11:16:04.742185 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
346 11:16:04.752928 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
347 11:16:04.762513 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
348 11:16:04.769675 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
349 11:16:04.788005 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
350 11:16:04.790875 WDT: Last reset was cold boot
351 11:16:04.794479 SPI1(PAD0) initialized at 2873684 Hz
352 11:16:04.797967 SPI5(PAD0) initialized at 992727 Hz
353 11:16:04.801309 VBOOT: Loading verstage.
354 11:16:04.807944 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
355 11:16:04.811012 FMAP: Found "FLASH" version 1.1 at 0x20000.
356 11:16:04.814535 FMAP: base = 0x0 size = 0x800000 #areas = 25
357 11:16:04.817384 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
358 11:16:04.825338 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
359 11:16:04.832057 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
360 11:16:04.842558 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
361 11:16:04.842649
362 11:16:04.842803
363 11:16:04.853561 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
364 11:16:04.856171 ARM64: Exception handlers installed.
365 11:16:04.859201 ARM64: Testing exception
366 11:16:04.859297 ARM64: Done test exception
367 11:16:04.866524 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
368 11:16:04.870254 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
369 11:16:04.883711 Probing TPM: . done!
370 11:16:04.883823 TPM ready after 0 ms
371 11:16:04.890923 Connected to device vid:did:rid of 1ae0:0028:00
372 11:16:04.898137 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
373 11:16:04.956655 Initialized TPM device CR50 revision 0
374 11:16:04.968267 tlcl_send_startup: Startup return code is 0
375 11:16:04.968731 TPM: setup succeeded
376 11:16:04.979548 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
377 11:16:04.988639 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
378 11:16:05.000303 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
379 11:16:05.010258 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
380 11:16:05.013870 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
381 11:16:05.018483 in-header: 03 07 00 00 08 00 00 00
382 11:16:05.022687 in-data: aa e4 47 04 13 02 00 00
383 11:16:05.026117 Chrome EC: UHEPI supported
384 11:16:05.033186 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
385 11:16:05.037572 in-header: 03 95 00 00 08 00 00 00
386 11:16:05.040509 in-data: 18 20 20 08 00 00 00 00
387 11:16:05.040931 Phase 1
388 11:16:05.044198 FMAP: area GBB found @ 3f5000 (12032 bytes)
389 11:16:05.051984 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
390 11:16:05.055120 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
391 11:16:05.058563 Recovery requested (1009000e)
392 11:16:05.067687 TPM: Extending digest for VBOOT: boot mode into PCR 0
393 11:16:05.073325 tlcl_extend: response is 0
394 11:16:05.082722 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
395 11:16:05.088498 tlcl_extend: response is 0
396 11:16:05.095040 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
397 11:16:05.115172 read SPI 0x210d4 0x2173b: 15140 us, 9050 KB/s, 72.400 Mbps
398 11:16:05.121463 BS: bootblock times (exec / console): total (unknown) / 148 ms
399 11:16:05.122015
400 11:16:05.122356
401 11:16:05.131772 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
402 11:16:05.135283 ARM64: Exception handlers installed.
403 11:16:05.137955 ARM64: Testing exception
404 11:16:05.138399 ARM64: Done test exception
405 11:16:05.160312 pmic_efuse_setting: Set efuses in 11 msecs
406 11:16:05.164124 pmwrap_interface_init: Select PMIF_VLD_RDY
407 11:16:05.170116 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
408 11:16:05.173665 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
409 11:16:05.180696 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
410 11:16:05.184516 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
411 11:16:05.187992 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
412 11:16:05.194540 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
413 11:16:05.198339 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
414 11:16:05.201940 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
415 11:16:05.209144 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
416 11:16:05.212473 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
417 11:16:05.216307 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
418 11:16:05.223961 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
419 11:16:05.227338 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
420 11:16:05.234619 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
421 11:16:05.237869 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
422 11:16:05.244994 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
423 11:16:05.248878 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
424 11:16:05.255410 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
425 11:16:05.263249 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
426 11:16:05.266471 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
427 11:16:05.273792 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
428 11:16:05.277414 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
429 11:16:05.284854 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
430 11:16:05.288762 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
431 11:16:05.295955 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
432 11:16:05.299623 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
433 11:16:05.306362 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
434 11:16:05.310025 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
435 11:16:05.313753 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
436 11:16:05.320838 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
437 11:16:05.324660 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
438 11:16:05.328144 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
439 11:16:05.335063 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
440 11:16:05.338705 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
441 11:16:05.346019 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
442 11:16:05.349470 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
443 11:16:05.353491 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
444 11:16:05.361015 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
445 11:16:05.364408 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
446 11:16:05.368744 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
447 11:16:05.372290 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
448 11:16:05.375482 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
449 11:16:05.382110 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
450 11:16:05.385865 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
451 11:16:05.389214 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
452 11:16:05.393140 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
453 11:16:05.400131 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
454 11:16:05.404180 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
455 11:16:05.407776 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
456 11:16:05.411297 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
457 11:16:05.414942 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
458 11:16:05.422621 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
459 11:16:05.433336 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
460 11:16:05.436838 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
461 11:16:05.444445 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
462 11:16:05.451387 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
463 11:16:05.458883 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
464 11:16:05.462733 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
465 11:16:05.465718 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
466 11:16:05.473980 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x3
467 11:16:05.477866 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
468 11:16:05.485204 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
469 11:16:05.488553 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
470 11:16:05.497922 [RTC]rtc_get_frequency_meter,154: input=15, output=852
471 11:16:05.507290 [RTC]rtc_get_frequency_meter,154: input=7, output=725
472 11:16:05.516698 [RTC]rtc_get_frequency_meter,154: input=11, output=789
473 11:16:05.526322 [RTC]rtc_get_frequency_meter,154: input=13, output=821
474 11:16:05.535932 [RTC]rtc_get_frequency_meter,154: input=12, output=804
475 11:16:05.545600 [RTC]rtc_get_frequency_meter,154: input=11, output=788
476 11:16:05.555377 [RTC]rtc_get_frequency_meter,154: input=12, output=805
477 11:16:05.559171 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
478 11:16:05.562706 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
479 11:16:05.566812 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
480 11:16:05.574366 [RTC]rtc_boot_common,220: irqsta=0, bbpu=81, con=486
481 11:16:05.577388 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
482 11:16:05.581545 [RTC]rtc_bbpu_power_on,300: done BBPU=0x81
483 11:16:05.585104 ADC[4]: Raw value=904064 ID=7
484 11:16:05.585531 ADC[3]: Raw value=213916 ID=1
485 11:16:05.588659 RAM Code: 0x71
486 11:16:05.592193 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
487 11:16:05.599601 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
488 11:16:05.606853 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
489 11:16:05.614208 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
490 11:16:05.614695 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
491 11:16:05.618672 in-header: 03 07 00 00 08 00 00 00
492 11:16:05.622251 in-data: aa e4 47 04 13 02 00 00
493 11:16:05.626366 Chrome EC: UHEPI supported
494 11:16:05.633218 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
495 11:16:05.636971 in-header: 03 95 00 00 08 00 00 00
496 11:16:05.640521 in-data: 18 20 20 08 00 00 00 00
497 11:16:05.640952 MRC: failed to locate region type 0.
498 11:16:05.647136 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
499 11:16:05.651700 DRAM-K: Running full calibration
500 11:16:05.658166 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
501 11:16:05.658604 header.status = 0x0
502 11:16:05.662291 header.version = 0x6 (expected: 0x6)
503 11:16:05.665585 header.size = 0xd00 (expected: 0xd00)
504 11:16:05.669135 header.flags = 0x0
505 11:16:05.672619 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
506 11:16:05.692412 read SPI 0x72590 0x1c583: 12498 us, 9289 KB/s, 74.312 Mbps
507 11:16:05.699389 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
508 11:16:05.702739 dram_init: ddr_geometry: 2
509 11:16:05.702835 [EMI] MDL number = 2
510 11:16:05.706726 [EMI] Get MDL freq = 0
511 11:16:05.706836 dram_init: ddr_type: 0
512 11:16:05.710987 is_discrete_lpddr4: 1
513 11:16:05.714605 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
514 11:16:05.715028
515 11:16:05.715365
516 11:16:05.715674 [Bian_co] ETT version 0.0.0.1
517 11:16:05.721478 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
518 11:16:05.721900
519 11:16:05.724951 dramc_set_vcore_voltage set vcore to 650000
520 11:16:05.728478 Read voltage for 800, 4
521 11:16:05.728905 Vio18 = 0
522 11:16:05.729243 Vcore = 650000
523 11:16:05.731509 Vdram = 0
524 11:16:05.731929 Vddq = 0
525 11:16:05.732318 Vmddr = 0
526 11:16:05.734905 dram_init: config_dvfs: 1
527 11:16:05.738518 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
528 11:16:05.745179 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
529 11:16:05.749204 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
530 11:16:05.752964 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
531 11:16:05.756066 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
532 11:16:05.759662 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
533 11:16:05.763244 MEM_TYPE=3, freq_sel=18
534 11:16:05.766117 sv_algorithm_assistance_LP4_1600
535 11:16:05.769791 ============ PULL DRAM RESETB DOWN ============
536 11:16:05.773215 ========== PULL DRAM RESETB DOWN end =========
537 11:16:05.776202 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
538 11:16:05.780154 ===================================
539 11:16:05.783710 LPDDR4 DRAM CONFIGURATION
540 11:16:05.787568 ===================================
541 11:16:05.788094 EX_ROW_EN[0] = 0x0
542 11:16:05.790460 EX_ROW_EN[1] = 0x0
543 11:16:05.793588 LP4Y_EN = 0x0
544 11:16:05.794033 WORK_FSP = 0x0
545 11:16:05.797662 WL = 0x2
546 11:16:05.798097 RL = 0x2
547 11:16:05.800111 BL = 0x2
548 11:16:05.800541 RPST = 0x0
549 11:16:05.803598 RD_PRE = 0x0
550 11:16:05.804116 WR_PRE = 0x1
551 11:16:05.807231 WR_PST = 0x0
552 11:16:05.807683 DBI_WR = 0x0
553 11:16:05.810324 DBI_RD = 0x0
554 11:16:05.810761 OTF = 0x1
555 11:16:05.813687 ===================================
556 11:16:05.816680 ===================================
557 11:16:05.820691 ANA top config
558 11:16:05.823445 ===================================
559 11:16:05.823901 DLL_ASYNC_EN = 0
560 11:16:05.827025 ALL_SLAVE_EN = 1
561 11:16:05.830078 NEW_RANK_MODE = 1
562 11:16:05.833434 DLL_IDLE_MODE = 1
563 11:16:05.836874 LP45_APHY_COMB_EN = 1
564 11:16:05.837336 TX_ODT_DIS = 1
565 11:16:05.840002 NEW_8X_MODE = 1
566 11:16:05.843554 ===================================
567 11:16:05.846548 ===================================
568 11:16:05.850100 data_rate = 1600
569 11:16:05.853895 CKR = 1
570 11:16:05.856736 DQ_P2S_RATIO = 8
571 11:16:05.860403 ===================================
572 11:16:05.860970 CA_P2S_RATIO = 8
573 11:16:05.863519 DQ_CA_OPEN = 0
574 11:16:05.867362 DQ_SEMI_OPEN = 0
575 11:16:05.870256 CA_SEMI_OPEN = 0
576 11:16:05.873641 CA_FULL_RATE = 0
577 11:16:05.877683 DQ_CKDIV4_EN = 1
578 11:16:05.878170 CA_CKDIV4_EN = 1
579 11:16:05.880456 CA_PREDIV_EN = 0
580 11:16:05.883743 PH8_DLY = 0
581 11:16:05.887317 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
582 11:16:05.890640 DQ_AAMCK_DIV = 4
583 11:16:05.893881 CA_AAMCK_DIV = 4
584 11:16:05.894354 CA_ADMCK_DIV = 4
585 11:16:05.896624 DQ_TRACK_CA_EN = 0
586 11:16:05.900338 CA_PICK = 800
587 11:16:05.903594 CA_MCKIO = 800
588 11:16:05.907034 MCKIO_SEMI = 0
589 11:16:05.910990 PLL_FREQ = 3068
590 11:16:05.911418 DQ_UI_PI_RATIO = 32
591 11:16:05.914059 CA_UI_PI_RATIO = 0
592 11:16:05.918035 ===================================
593 11:16:05.921507 ===================================
594 11:16:05.925233 memory_type:LPDDR4
595 11:16:05.925316 GP_NUM : 10
596 11:16:05.929073 SRAM_EN : 1
597 11:16:05.929155 MD32_EN : 0
598 11:16:05.932644 ===================================
599 11:16:05.935476 [ANA_INIT] >>>>>>>>>>>>>>
600 11:16:05.939289 <<<<<< [CONFIGURE PHASE]: ANA_TX
601 11:16:05.942914 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
602 11:16:05.946216 ===================================
603 11:16:05.946366 data_rate = 1600,PCW = 0X7600
604 11:16:05.950077 ===================================
605 11:16:05.952916 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
606 11:16:05.959807 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
607 11:16:05.966277 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
608 11:16:05.969648 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
609 11:16:05.973367 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
610 11:16:05.976415 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
611 11:16:05.979369 [ANA_INIT] flow start
612 11:16:05.979451 [ANA_INIT] PLL >>>>>>>>
613 11:16:05.983234 [ANA_INIT] PLL <<<<<<<<
614 11:16:05.986461 [ANA_INIT] MIDPI >>>>>>>>
615 11:16:05.989526 [ANA_INIT] MIDPI <<<<<<<<
616 11:16:05.989703 [ANA_INIT] DLL >>>>>>>>
617 11:16:05.992909 [ANA_INIT] flow end
618 11:16:05.996077 ============ LP4 DIFF to SE enter ============
619 11:16:05.999926 ============ LP4 DIFF to SE exit ============
620 11:16:06.002977 [ANA_INIT] <<<<<<<<<<<<<
621 11:16:06.005944 [Flow] Enable top DCM control >>>>>
622 11:16:06.009544 [Flow] Enable top DCM control <<<<<
623 11:16:06.012939 Enable DLL master slave shuffle
624 11:16:06.019335 ==============================================================
625 11:16:06.019434 Gating Mode config
626 11:16:06.026061 ==============================================================
627 11:16:06.026145 Config description:
628 11:16:06.035826 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
629 11:16:06.042496 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
630 11:16:06.049593 SELPH_MODE 0: By rank 1: By Phase
631 11:16:06.052405 ==============================================================
632 11:16:06.055618 GAT_TRACK_EN = 1
633 11:16:06.059140 RX_GATING_MODE = 2
634 11:16:06.062200 RX_GATING_TRACK_MODE = 2
635 11:16:06.065625 SELPH_MODE = 1
636 11:16:06.068755 PICG_EARLY_EN = 1
637 11:16:06.072185 VALID_LAT_VALUE = 1
638 11:16:06.078902 ==============================================================
639 11:16:06.082466 Enter into Gating configuration >>>>
640 11:16:06.085518 Exit from Gating configuration <<<<
641 11:16:06.085621 Enter into DVFS_PRE_config >>>>>
642 11:16:06.098858 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
643 11:16:06.102619 Exit from DVFS_PRE_config <<<<<
644 11:16:06.105417 Enter into PICG configuration >>>>
645 11:16:06.108988 Exit from PICG configuration <<<<
646 11:16:06.109143 [RX_INPUT] configuration >>>>>
647 11:16:06.111893 [RX_INPUT] configuration <<<<<
648 11:16:06.118466 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
649 11:16:06.121909 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
650 11:16:06.128772 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
651 11:16:06.135286 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
652 11:16:06.141876 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
653 11:16:06.148792 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
654 11:16:06.152370 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
655 11:16:06.155210 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
656 11:16:06.162190 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
657 11:16:06.165406 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
658 11:16:06.168701 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
659 11:16:06.172060 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
660 11:16:06.175380 ===================================
661 11:16:06.178808 LPDDR4 DRAM CONFIGURATION
662 11:16:06.182080 ===================================
663 11:16:06.185749 EX_ROW_EN[0] = 0x0
664 11:16:06.186192 EX_ROW_EN[1] = 0x0
665 11:16:06.188595 LP4Y_EN = 0x0
666 11:16:06.189021 WORK_FSP = 0x0
667 11:16:06.192292 WL = 0x2
668 11:16:06.192752 RL = 0x2
669 11:16:06.195112 BL = 0x2
670 11:16:06.195546 RPST = 0x0
671 11:16:06.198384 RD_PRE = 0x0
672 11:16:06.202147 WR_PRE = 0x1
673 11:16:06.202568 WR_PST = 0x0
674 11:16:06.205308 DBI_WR = 0x0
675 11:16:06.205734 DBI_RD = 0x0
676 11:16:06.208325 OTF = 0x1
677 11:16:06.211725 ===================================
678 11:16:06.215544 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
679 11:16:06.218876 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
680 11:16:06.222208 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
681 11:16:06.225285 ===================================
682 11:16:06.227839 LPDDR4 DRAM CONFIGURATION
683 11:16:06.231379 ===================================
684 11:16:06.235256 EX_ROW_EN[0] = 0x10
685 11:16:06.235682 EX_ROW_EN[1] = 0x0
686 11:16:06.238795 LP4Y_EN = 0x0
687 11:16:06.239324 WORK_FSP = 0x0
688 11:16:06.241928 WL = 0x2
689 11:16:06.242452 RL = 0x2
690 11:16:06.245382 BL = 0x2
691 11:16:06.245827 RPST = 0x0
692 11:16:06.248450 RD_PRE = 0x0
693 11:16:06.248876 WR_PRE = 0x1
694 11:16:06.251764 WR_PST = 0x0
695 11:16:06.252259 DBI_WR = 0x0
696 11:16:06.254888 DBI_RD = 0x0
697 11:16:06.258328 OTF = 0x1
698 11:16:06.261741 ===================================
699 11:16:06.264865 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
700 11:16:06.270047 nWR fixed to 40
701 11:16:06.273385 [ModeRegInit_LP4] CH0 RK0
702 11:16:06.273808 [ModeRegInit_LP4] CH0 RK1
703 11:16:06.276931 [ModeRegInit_LP4] CH1 RK0
704 11:16:06.280003 [ModeRegInit_LP4] CH1 RK1
705 11:16:06.280464 match AC timing 13
706 11:16:06.286494 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
707 11:16:06.289615 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
708 11:16:06.293318 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
709 11:16:06.299733 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
710 11:16:06.303212 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
711 11:16:06.306780 [EMI DOE] emi_dcm 0
712 11:16:06.310145 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
713 11:16:06.310679 ==
714 11:16:06.312928 Dram Type= 6, Freq= 0, CH_0, rank 0
715 11:16:06.316347 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
716 11:16:06.316778 ==
717 11:16:06.323335 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
718 11:16:06.329853 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
719 11:16:06.337695 [CA 0] Center 37 (7~68) winsize 62
720 11:16:06.340575 [CA 1] Center 37 (6~68) winsize 63
721 11:16:06.344448 [CA 2] Center 34 (4~65) winsize 62
722 11:16:06.347342 [CA 3] Center 34 (4~65) winsize 62
723 11:16:06.351256 [CA 4] Center 34 (3~65) winsize 63
724 11:16:06.354203 [CA 5] Center 33 (3~64) winsize 62
725 11:16:06.354631
726 11:16:06.357600 [CmdBusTrainingLP45] Vref(ca) range 1: 34
727 11:16:06.358024
728 11:16:06.360776 [CATrainingPosCal] consider 1 rank data
729 11:16:06.364304 u2DelayCellTimex100 = 270/100 ps
730 11:16:06.367851 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
731 11:16:06.370711 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
732 11:16:06.377591 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
733 11:16:06.380525 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
734 11:16:06.384396 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
735 11:16:06.387748 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
736 11:16:06.388228
737 11:16:06.390758 CA PerBit enable=1, Macro0, CA PI delay=33
738 11:16:06.391184
739 11:16:06.393935 [CBTSetCACLKResult] CA Dly = 33
740 11:16:06.394362 CS Dly: 5 (0~36)
741 11:16:06.397372 ==
742 11:16:06.397800 Dram Type= 6, Freq= 0, CH_0, rank 1
743 11:16:06.404301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
744 11:16:06.404734 ==
745 11:16:06.407405 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
746 11:16:06.413765 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
747 11:16:06.423878 [CA 0] Center 38 (7~69) winsize 63
748 11:16:06.426771 [CA 1] Center 37 (7~68) winsize 62
749 11:16:06.429742 [CA 2] Center 35 (5~66) winsize 62
750 11:16:06.433519 [CA 3] Center 35 (4~66) winsize 63
751 11:16:06.436716 [CA 4] Center 34 (3~65) winsize 63
752 11:16:06.440272 [CA 5] Center 33 (3~64) winsize 62
753 11:16:06.440367
754 11:16:06.443591 [CmdBusTrainingLP45] Vref(ca) range 1: 34
755 11:16:06.443750
756 11:16:06.446571 [CATrainingPosCal] consider 2 rank data
757 11:16:06.449891 u2DelayCellTimex100 = 270/100 ps
758 11:16:06.453437 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
759 11:16:06.456749 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
760 11:16:06.463135 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
761 11:16:06.466498 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
762 11:16:06.470065 CA4 delay=34 (3~65),Diff = 1 PI (7 cell)
763 11:16:06.473028 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
764 11:16:06.473111
765 11:16:06.476918 CA PerBit enable=1, Macro0, CA PI delay=33
766 11:16:06.477002
767 11:16:06.479585 [CBTSetCACLKResult] CA Dly = 33
768 11:16:06.479668 CS Dly: 6 (0~38)
769 11:16:06.483591
770 11:16:06.486050 ----->DramcWriteLeveling(PI) begin...
771 11:16:06.486135 ==
772 11:16:06.489985 Dram Type= 6, Freq= 0, CH_0, rank 0
773 11:16:06.494314 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
774 11:16:06.494412 ==
775 11:16:06.498111 Write leveling (Byte 0): 30 => 30
776 11:16:06.498200 Write leveling (Byte 1): 29 => 29
777 11:16:06.501793 DramcWriteLeveling(PI) end<-----
778 11:16:06.501894
779 11:16:06.501971 ==
780 11:16:06.505194 Dram Type= 6, Freq= 0, CH_0, rank 0
781 11:16:06.508248 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
782 11:16:06.512204 ==
783 11:16:06.512316 [Gating] SW mode calibration
784 11:16:06.521836 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
785 11:16:06.524937 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
786 11:16:06.528517 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
787 11:16:06.535105 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
788 11:16:06.538217 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
789 11:16:06.541792 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
790 11:16:06.548052 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
791 11:16:06.551325 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
792 11:16:06.554998 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
793 11:16:06.561622 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
794 11:16:06.564988 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
795 11:16:06.568449 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
796 11:16:06.574991 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
797 11:16:06.578504 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
798 11:16:06.581295 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
799 11:16:06.588136 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
800 11:16:06.591265 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
801 11:16:06.594836 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
802 11:16:06.601298 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
803 11:16:06.604433 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
804 11:16:06.608569 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
805 11:16:06.614509 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 11:16:06.617788 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 11:16:06.621117 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 11:16:06.624591 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 11:16:06.631010 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 11:16:06.634919 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 11:16:06.638329 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 11:16:06.644394 0 9 8 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
813 11:16:06.647692 0 9 12 | B1->B0 | 2e2d 3434 | 1 1 | (0 0) (1 1)
814 11:16:06.650988 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
815 11:16:06.657844 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
816 11:16:06.661346 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
817 11:16:06.664209 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
818 11:16:06.670926 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
819 11:16:06.674305 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 1)
820 11:16:06.677656 0 10 8 | B1->B0 | 3131 2424 | 0 0 | (0 1) (0 0)
821 11:16:06.684648 0 10 12 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
822 11:16:06.687597 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 11:16:06.690582 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 11:16:06.697499 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 11:16:06.700530 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
826 11:16:06.704001 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
827 11:16:06.710695 0 11 4 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (1 1)
828 11:16:06.714318 0 11 8 | B1->B0 | 2626 4343 | 0 0 | (0 0) (0 0)
829 11:16:06.717194 0 11 12 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
830 11:16:06.724348 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
831 11:16:06.727399 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
832 11:16:06.731516 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
833 11:16:06.737368 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
834 11:16:06.740596 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
835 11:16:06.743852 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
836 11:16:06.750314 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
837 11:16:06.753868 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
838 11:16:06.756829 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
839 11:16:06.763943 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
840 11:16:06.767052 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
841 11:16:06.770197 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
842 11:16:06.777382 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
843 11:16:06.780652 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
844 11:16:06.783654 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
845 11:16:06.790847 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
846 11:16:06.793852 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
847 11:16:06.796784 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
848 11:16:06.803539 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
849 11:16:06.806769 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
850 11:16:06.810303 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
851 11:16:06.813762 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
852 11:16:06.817021 Total UI for P1: 0, mck2ui 16
853 11:16:06.820634 best dqsien dly found for B0: ( 0, 14, 2)
854 11:16:06.827112 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
855 11:16:06.830268 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
856 11:16:06.833579 Total UI for P1: 0, mck2ui 16
857 11:16:06.837076 best dqsien dly found for B1: ( 0, 14, 6)
858 11:16:06.840621 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
859 11:16:06.843562 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
860 11:16:06.843982
861 11:16:06.846942 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
862 11:16:06.850751 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
863 11:16:06.853862 [Gating] SW calibration Done
864 11:16:06.854298 ==
865 11:16:06.857104 Dram Type= 6, Freq= 0, CH_0, rank 0
866 11:16:06.864011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
867 11:16:06.864521 ==
868 11:16:06.864962 RX Vref Scan: 0
869 11:16:06.865290
870 11:16:06.867307 RX Vref 0 -> 0, step: 1
871 11:16:06.867728
872 11:16:06.868092 RX Delay -130 -> 252, step: 16
873 11:16:06.874096 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
874 11:16:06.877394 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
875 11:16:06.880348 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
876 11:16:06.884190 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
877 11:16:06.887214 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
878 11:16:06.894166 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
879 11:16:06.897094 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
880 11:16:06.900416 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
881 11:16:06.904001 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
882 11:16:06.906889 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
883 11:16:06.913429 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
884 11:16:06.917562 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
885 11:16:06.920527 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
886 11:16:06.923861 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
887 11:16:06.930209 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
888 11:16:06.933798 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
889 11:16:06.934222 ==
890 11:16:06.936911 Dram Type= 6, Freq= 0, CH_0, rank 0
891 11:16:06.940556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
892 11:16:06.940981 ==
893 11:16:06.943515 DQS Delay:
894 11:16:06.943934 DQS0 = 0, DQS1 = 0
895 11:16:06.944306 DQM Delay:
896 11:16:06.946890 DQM0 = 89, DQM1 = 75
897 11:16:06.947321 DQ Delay:
898 11:16:06.950006 DQ0 =85, DQ1 =93, DQ2 =85, DQ3 =85
899 11:16:06.953560 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
900 11:16:06.957156 DQ8 =69, DQ9 =53, DQ10 =69, DQ11 =69
901 11:16:06.960110 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
902 11:16:06.960531
903 11:16:06.960863
904 11:16:06.961172 ==
905 11:16:06.963354 Dram Type= 6, Freq= 0, CH_0, rank 0
906 11:16:06.970856 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 11:16:06.971281 ==
908 11:16:06.971613
909 11:16:06.971924
910 11:16:06.972261 TX Vref Scan disable
911 11:16:06.973297 == TX Byte 0 ==
912 11:16:06.976888 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
913 11:16:06.983454 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
914 11:16:06.983946 == TX Byte 1 ==
915 11:16:06.986986 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
916 11:16:06.993495 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
917 11:16:06.994035 ==
918 11:16:06.996900 Dram Type= 6, Freq= 0, CH_0, rank 0
919 11:16:07.000121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
920 11:16:07.000547 ==
921 11:16:07.012446 TX Vref=22, minBit 0, minWin=27, winSum=438
922 11:16:07.015424 TX Vref=24, minBit 1, minWin=27, winSum=443
923 11:16:07.019182 TX Vref=26, minBit 1, minWin=27, winSum=446
924 11:16:07.022173 TX Vref=28, minBit 1, minWin=27, winSum=454
925 11:16:07.025295 TX Vref=30, minBit 1, minWin=27, winSum=452
926 11:16:07.032106 TX Vref=32, minBit 1, minWin=27, winSum=449
927 11:16:07.035602 [TxChooseVref] Worse bit 1, Min win 27, Win sum 454, Final Vref 28
928 11:16:07.036157
929 11:16:07.038545 Final TX Range 1 Vref 28
930 11:16:07.038950
931 11:16:07.039273 ==
932 11:16:07.041850 Dram Type= 6, Freq= 0, CH_0, rank 0
933 11:16:07.045298 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 11:16:07.048651 ==
935 11:16:07.049073
936 11:16:07.049408
937 11:16:07.049719 TX Vref Scan disable
938 11:16:07.052630 == TX Byte 0 ==
939 11:16:07.055789 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
940 11:16:07.062517 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
941 11:16:07.062943 == TX Byte 1 ==
942 11:16:07.065515 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
943 11:16:07.072020 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
944 11:16:07.072488
945 11:16:07.072818 [DATLAT]
946 11:16:07.073130 Freq=800, CH0 RK0
947 11:16:07.073430
948 11:16:07.075289 DATLAT Default: 0xa
949 11:16:07.075708 0, 0xFFFF, sum = 0
950 11:16:07.078917 1, 0xFFFF, sum = 0
951 11:16:07.082381 2, 0xFFFF, sum = 0
952 11:16:07.082948 3, 0xFFFF, sum = 0
953 11:16:07.085350 4, 0xFFFF, sum = 0
954 11:16:07.085776 5, 0xFFFF, sum = 0
955 11:16:07.088763 6, 0xFFFF, sum = 0
956 11:16:07.089189 7, 0xFFFF, sum = 0
957 11:16:07.092445 8, 0xFFFF, sum = 0
958 11:16:07.092871 9, 0x0, sum = 1
959 11:16:07.095308 10, 0x0, sum = 2
960 11:16:07.095731 11, 0x0, sum = 3
961 11:16:07.096094 12, 0x0, sum = 4
962 11:16:07.098647 best_step = 10
963 11:16:07.099062
964 11:16:07.099392 ==
965 11:16:07.102172 Dram Type= 6, Freq= 0, CH_0, rank 0
966 11:16:07.105220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
967 11:16:07.105642 ==
968 11:16:07.108983 RX Vref Scan: 1
969 11:16:07.109401
970 11:16:07.112100 Set Vref Range= 32 -> 127
971 11:16:07.112515
972 11:16:07.112849 RX Vref 32 -> 127, step: 1
973 11:16:07.113161
974 11:16:07.115168 RX Delay -111 -> 252, step: 8
975 11:16:07.115730
976 11:16:07.118701 Set Vref, RX VrefLevel [Byte0]: 32
977 11:16:07.121699 [Byte1]: 32
978 11:16:07.125190
979 11:16:07.125631 Set Vref, RX VrefLevel [Byte0]: 33
980 11:16:07.128448 [Byte1]: 33
981 11:16:07.132708
982 11:16:07.133154 Set Vref, RX VrefLevel [Byte0]: 34
983 11:16:07.135911 [Byte1]: 34
984 11:16:07.140198
985 11:16:07.140613 Set Vref, RX VrefLevel [Byte0]: 35
986 11:16:07.143558 [Byte1]: 35
987 11:16:07.148135
988 11:16:07.148565 Set Vref, RX VrefLevel [Byte0]: 36
989 11:16:07.151567 [Byte1]: 36
990 11:16:07.155707
991 11:16:07.156230 Set Vref, RX VrefLevel [Byte0]: 37
992 11:16:07.159579 [Byte1]: 37
993 11:16:07.163913
994 11:16:07.164494 Set Vref, RX VrefLevel [Byte0]: 38
995 11:16:07.167316 [Byte1]: 38
996 11:16:07.171738
997 11:16:07.172198 Set Vref, RX VrefLevel [Byte0]: 39
998 11:16:07.174717 [Byte1]: 39
999 11:16:07.179276
1000 11:16:07.179819 Set Vref, RX VrefLevel [Byte0]: 40
1001 11:16:07.182885 [Byte1]: 40
1002 11:16:07.187172
1003 11:16:07.187618 Set Vref, RX VrefLevel [Byte0]: 41
1004 11:16:07.190338 [Byte1]: 41
1005 11:16:07.193856
1006 11:16:07.194280 Set Vref, RX VrefLevel [Byte0]: 42
1007 11:16:07.197351 [Byte1]: 42
1008 11:16:07.201621
1009 11:16:07.202263 Set Vref, RX VrefLevel [Byte0]: 43
1010 11:16:07.204749 [Byte1]: 43
1011 11:16:07.209877
1012 11:16:07.210299 Set Vref, RX VrefLevel [Byte0]: 44
1013 11:16:07.212860 [Byte1]: 44
1014 11:16:07.217527
1015 11:16:07.217948 Set Vref, RX VrefLevel [Byte0]: 45
1016 11:16:07.220621 [Byte1]: 45
1017 11:16:07.224431
1018 11:16:07.224873 Set Vref, RX VrefLevel [Byte0]: 46
1019 11:16:07.227669 [Byte1]: 46
1020 11:16:07.232810
1021 11:16:07.233236 Set Vref, RX VrefLevel [Byte0]: 47
1022 11:16:07.236403 [Byte1]: 47
1023 11:16:07.239788
1024 11:16:07.240276 Set Vref, RX VrefLevel [Byte0]: 48
1025 11:16:07.243593 [Byte1]: 48
1026 11:16:07.247373
1027 11:16:07.247795 Set Vref, RX VrefLevel [Byte0]: 49
1028 11:16:07.251063 [Byte1]: 49
1029 11:16:07.255105
1030 11:16:07.255640 Set Vref, RX VrefLevel [Byte0]: 50
1031 11:16:07.258535 [Byte1]: 50
1032 11:16:07.263132
1033 11:16:07.263693 Set Vref, RX VrefLevel [Byte0]: 51
1034 11:16:07.265891 [Byte1]: 51
1035 11:16:07.270844
1036 11:16:07.271385 Set Vref, RX VrefLevel [Byte0]: 52
1037 11:16:07.273893 [Byte1]: 52
1038 11:16:07.277937
1039 11:16:07.278487 Set Vref, RX VrefLevel [Byte0]: 53
1040 11:16:07.281401 [Byte1]: 53
1041 11:16:07.285805
1042 11:16:07.286226 Set Vref, RX VrefLevel [Byte0]: 54
1043 11:16:07.289336 [Byte1]: 54
1044 11:16:07.293889
1045 11:16:07.294487 Set Vref, RX VrefLevel [Byte0]: 55
1046 11:16:07.296679 [Byte1]: 55
1047 11:16:07.300893
1048 11:16:07.301444 Set Vref, RX VrefLevel [Byte0]: 56
1049 11:16:07.304495 [Byte1]: 56
1050 11:16:07.308949
1051 11:16:07.309468 Set Vref, RX VrefLevel [Byte0]: 57
1052 11:16:07.311840 [Byte1]: 57
1053 11:16:07.315987
1054 11:16:07.316493 Set Vref, RX VrefLevel [Byte0]: 58
1055 11:16:07.319433 [Byte1]: 58
1056 11:16:07.324288
1057 11:16:07.324858 Set Vref, RX VrefLevel [Byte0]: 59
1058 11:16:07.327031 [Byte1]: 59
1059 11:16:07.332061
1060 11:16:07.332503 Set Vref, RX VrefLevel [Byte0]: 60
1061 11:16:07.334984 [Byte1]: 60
1062 11:16:07.339474
1063 11:16:07.339894 Set Vref, RX VrefLevel [Byte0]: 61
1064 11:16:07.342725 [Byte1]: 61
1065 11:16:07.347045
1066 11:16:07.347565 Set Vref, RX VrefLevel [Byte0]: 62
1067 11:16:07.350079 [Byte1]: 62
1068 11:16:07.354860
1069 11:16:07.355282 Set Vref, RX VrefLevel [Byte0]: 63
1070 11:16:07.358216 [Byte1]: 63
1071 11:16:07.362168
1072 11:16:07.362588 Set Vref, RX VrefLevel [Byte0]: 64
1073 11:16:07.365378 [Byte1]: 64
1074 11:16:07.369781
1075 11:16:07.370358 Set Vref, RX VrefLevel [Byte0]: 65
1076 11:16:07.373122 [Byte1]: 65
1077 11:16:07.377441
1078 11:16:07.377862 Set Vref, RX VrefLevel [Byte0]: 66
1079 11:16:07.381134 [Byte1]: 66
1080 11:16:07.385408
1081 11:16:07.385854 Set Vref, RX VrefLevel [Byte0]: 67
1082 11:16:07.388621 [Byte1]: 67
1083 11:16:07.393010
1084 11:16:07.393473 Set Vref, RX VrefLevel [Byte0]: 68
1085 11:16:07.396003 [Byte1]: 68
1086 11:16:07.400110
1087 11:16:07.400531 Set Vref, RX VrefLevel [Byte0]: 69
1088 11:16:07.404331 [Byte1]: 69
1089 11:16:07.407865
1090 11:16:07.408415 Set Vref, RX VrefLevel [Byte0]: 70
1091 11:16:07.411456 [Byte1]: 70
1092 11:16:07.415544
1093 11:16:07.415983 Set Vref, RX VrefLevel [Byte0]: 71
1094 11:16:07.418735 [Byte1]: 71
1095 11:16:07.423173
1096 11:16:07.423584 Set Vref, RX VrefLevel [Byte0]: 72
1097 11:16:07.426936 [Byte1]: 72
1098 11:16:07.431329
1099 11:16:07.431811 Set Vref, RX VrefLevel [Byte0]: 73
1100 11:16:07.434363 [Byte1]: 73
1101 11:16:07.438499
1102 11:16:07.438976 Final RX Vref Byte 0 = 56 to rank0
1103 11:16:07.441793 Final RX Vref Byte 1 = 59 to rank0
1104 11:16:07.445072 Final RX Vref Byte 0 = 56 to rank1
1105 11:16:07.448836 Final RX Vref Byte 1 = 59 to rank1==
1106 11:16:07.451835 Dram Type= 6, Freq= 0, CH_0, rank 0
1107 11:16:07.458515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1108 11:16:07.458942 ==
1109 11:16:07.459452 DQS Delay:
1110 11:16:07.459897 DQS0 = 0, DQS1 = 0
1111 11:16:07.462038 DQM Delay:
1112 11:16:07.462526 DQM0 = 88, DQM1 = 77
1113 11:16:07.465343 DQ Delay:
1114 11:16:07.468328 DQ0 =88, DQ1 =88, DQ2 =88, DQ3 =84
1115 11:16:07.471639 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1116 11:16:07.475043 DQ8 =68, DQ9 =60, DQ10 =80, DQ11 =72
1117 11:16:07.478397 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1118 11:16:07.478503
1119 11:16:07.478595
1120 11:16:07.484720 [DQSOSCAuto] RK0, (LSB)MR18= 0x2f28, (MSB)MR19= 0x606, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
1121 11:16:07.488426 CH0 RK0: MR19=606, MR18=2F28
1122 11:16:07.494788 CH0_RK0: MR19=0x606, MR18=0x2F28, DQSOSC=397, MR23=63, INC=93, DEC=62
1123 11:16:07.494963
1124 11:16:07.498500 ----->DramcWriteLeveling(PI) begin...
1125 11:16:07.498656 ==
1126 11:16:07.501313 Dram Type= 6, Freq= 0, CH_0, rank 1
1127 11:16:07.504597 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1128 11:16:07.504738 ==
1129 11:16:07.507943 Write leveling (Byte 0): 34 => 34
1130 11:16:07.511006 Write leveling (Byte 1): 27 => 27
1131 11:16:07.514338 DramcWriteLeveling(PI) end<-----
1132 11:16:07.514490
1133 11:16:07.514596 ==
1134 11:16:07.518173 Dram Type= 6, Freq= 0, CH_0, rank 1
1135 11:16:07.521285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1136 11:16:07.521453 ==
1137 11:16:07.524766 [Gating] SW mode calibration
1138 11:16:07.531745 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1139 11:16:07.538117 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1140 11:16:07.541239 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1141 11:16:07.547760 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1142 11:16:07.591786 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1143 11:16:07.592700 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1144 11:16:07.593075 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1145 11:16:07.593393 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1146 11:16:07.593753 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1147 11:16:07.594077 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1148 11:16:07.594371 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1149 11:16:07.594726 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1150 11:16:07.595023 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1151 11:16:07.595358 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1152 11:16:07.636242 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1153 11:16:07.636794 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1154 11:16:07.637522 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1155 11:16:07.637904 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1156 11:16:07.638262 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1157 11:16:07.638693 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1158 11:16:07.639186 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1159 11:16:07.639527 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1160 11:16:07.639943 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1161 11:16:07.640327 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1162 11:16:07.678691 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1163 11:16:07.678847 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1164 11:16:07.679173 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 11:16:07.679441 0 9 4 | B1->B0 | 2323 2424 | 0 1 | (0 0) (1 1)
1166 11:16:07.679723 0 9 8 | B1->B0 | 2323 3333 | 0 1 | (0 0) (1 1)
1167 11:16:07.680224 0 9 12 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
1168 11:16:07.680292 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1169 11:16:07.681239 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1170 11:16:07.681994 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1171 11:16:07.682278 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1172 11:16:07.684311 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1173 11:16:07.687872 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 0) (0 1)
1174 11:16:07.691221 0 10 8 | B1->B0 | 3232 2323 | 0 0 | (0 0) (0 0)
1175 11:16:07.694257 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
1176 11:16:07.701004 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 11:16:07.704528 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 11:16:07.707376 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 11:16:07.714499 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1180 11:16:07.717780 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1181 11:16:07.720817 0 11 4 | B1->B0 | 2323 3333 | 0 1 | (0 0) (0 0)
1182 11:16:07.727438 0 11 8 | B1->B0 | 2f2e 4545 | 1 0 | (0 0) (0 0)
1183 11:16:07.731381 0 11 12 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
1184 11:16:07.734707 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1185 11:16:07.741392 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1186 11:16:07.744761 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1187 11:16:07.748385 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1188 11:16:07.752360 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1189 11:16:07.755603 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1190 11:16:07.762440 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1191 11:16:07.765837 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1192 11:16:07.769104 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1193 11:16:07.776018 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1194 11:16:07.779086 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1195 11:16:07.782932 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1196 11:16:07.789815 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1197 11:16:07.792851 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1198 11:16:07.795592 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1199 11:16:07.802434 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1200 11:16:07.805557 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1201 11:16:07.809158 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1202 11:16:07.812345 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1203 11:16:07.819414 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1204 11:16:07.822998 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1205 11:16:07.825752 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1206 11:16:07.832315 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1207 11:16:07.835802 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1208 11:16:07.840086 Total UI for P1: 0, mck2ui 16
1209 11:16:07.842272 best dqsien dly found for B0: ( 0, 14, 6)
1210 11:16:07.845795 Total UI for P1: 0, mck2ui 16
1211 11:16:07.848803 best dqsien dly found for B1: ( 0, 14, 10)
1212 11:16:07.852437 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1213 11:16:07.855530 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1214 11:16:07.855628
1215 11:16:07.859083 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1216 11:16:07.865288 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1217 11:16:07.865360 [Gating] SW calibration Done
1218 11:16:07.865422 ==
1219 11:16:07.868580 Dram Type= 6, Freq= 0, CH_0, rank 1
1220 11:16:07.875182 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1221 11:16:07.875278 ==
1222 11:16:07.875353 RX Vref Scan: 0
1223 11:16:07.875423
1224 11:16:07.878984 RX Vref 0 -> 0, step: 1
1225 11:16:07.879161
1226 11:16:07.882176 RX Delay -130 -> 252, step: 16
1227 11:16:07.885374 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1228 11:16:07.888741 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1229 11:16:07.892323 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1230 11:16:07.898488 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1231 11:16:07.901815 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1232 11:16:07.905273 iDelay=206, Bit 5, Center 69 (-50 ~ 189) 240
1233 11:16:07.908673 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1234 11:16:07.911715 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1235 11:16:07.918386 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1236 11:16:07.921384 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1237 11:16:07.925021 iDelay=206, Bit 10, Center 77 (-34 ~ 189) 224
1238 11:16:07.928606 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1239 11:16:07.931663 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1240 11:16:07.938366 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1241 11:16:07.941487 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1242 11:16:07.944883 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1243 11:16:07.945067 ==
1244 11:16:07.948173 Dram Type= 6, Freq= 0, CH_0, rank 1
1245 11:16:07.951413 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1246 11:16:07.955090 ==
1247 11:16:07.955173 DQS Delay:
1248 11:16:07.955239 DQS0 = 0, DQS1 = 0
1249 11:16:07.957825 DQM Delay:
1250 11:16:07.957907 DQM0 = 85, DQM1 = 77
1251 11:16:07.961460 DQ Delay:
1252 11:16:07.961573 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1253 11:16:07.964783 DQ4 =93, DQ5 =69, DQ6 =93, DQ7 =93
1254 11:16:07.967903 DQ8 =69, DQ9 =61, DQ10 =77, DQ11 =69
1255 11:16:07.971509 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1256 11:16:07.971602
1257 11:16:07.971667
1258 11:16:07.975153 ==
1259 11:16:07.978058 Dram Type= 6, Freq= 0, CH_0, rank 1
1260 11:16:07.981648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1261 11:16:07.982072 ==
1262 11:16:07.982409
1263 11:16:07.982724
1264 11:16:07.985339 TX Vref Scan disable
1265 11:16:07.985761 == TX Byte 0 ==
1266 11:16:07.991437 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1267 11:16:07.994839 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1268 11:16:07.995373 == TX Byte 1 ==
1269 11:16:07.998639 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1270 11:16:08.004908 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1271 11:16:08.005376 ==
1272 11:16:08.008424 Dram Type= 6, Freq= 0, CH_0, rank 1
1273 11:16:08.011617 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1274 11:16:08.011993 ==
1275 11:16:08.025680 TX Vref=22, minBit 1, minWin=27, winSum=442
1276 11:16:08.029065 TX Vref=24, minBit 1, minWin=27, winSum=446
1277 11:16:08.032441 TX Vref=26, minBit 2, minWin=27, winSum=451
1278 11:16:08.035747 TX Vref=28, minBit 0, minWin=28, winSum=452
1279 11:16:08.038754 TX Vref=30, minBit 5, minWin=27, winSum=452
1280 11:16:08.045399 TX Vref=32, minBit 5, minWin=27, winSum=451
1281 11:16:08.048924 [TxChooseVref] Worse bit 0, Min win 28, Win sum 452, Final Vref 28
1282 11:16:08.049012
1283 11:16:08.051984 Final TX Range 1 Vref 28
1284 11:16:08.052085
1285 11:16:08.052160 ==
1286 11:16:08.055238 Dram Type= 6, Freq= 0, CH_0, rank 1
1287 11:16:08.058393 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1288 11:16:08.058475 ==
1289 11:16:08.061768
1290 11:16:08.061848
1291 11:16:08.061913 TX Vref Scan disable
1292 11:16:08.065351 == TX Byte 0 ==
1293 11:16:08.069087 Update DQ dly =585 (2 ,1, 41) DQ OEN =(1 ,6)
1294 11:16:08.076026 Update DQM dly =585 (2 ,1, 41) DQM OEN =(1 ,6)
1295 11:16:08.076117 == TX Byte 1 ==
1296 11:16:08.079055 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1297 11:16:08.085142 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1298 11:16:08.085222
1299 11:16:08.085285 [DATLAT]
1300 11:16:08.085344 Freq=800, CH0 RK1
1301 11:16:08.085401
1302 11:16:08.088789 DATLAT Default: 0xa
1303 11:16:08.088869 0, 0xFFFF, sum = 0
1304 11:16:08.092011 1, 0xFFFF, sum = 0
1305 11:16:08.095269 2, 0xFFFF, sum = 0
1306 11:16:08.095679 3, 0xFFFF, sum = 0
1307 11:16:08.099694 4, 0xFFFF, sum = 0
1308 11:16:08.100144 5, 0xFFFF, sum = 0
1309 11:16:08.102618 6, 0xFFFF, sum = 0
1310 11:16:08.103049 7, 0xFFFF, sum = 0
1311 11:16:08.105543 8, 0xFFFF, sum = 0
1312 11:16:08.106002 9, 0x0, sum = 1
1313 11:16:08.106350 10, 0x0, sum = 2
1314 11:16:08.109290 11, 0x0, sum = 3
1315 11:16:08.109780 12, 0x0, sum = 4
1316 11:16:08.112442 best_step = 10
1317 11:16:08.112911
1318 11:16:08.113278 ==
1319 11:16:08.115878 Dram Type= 6, Freq= 0, CH_0, rank 1
1320 11:16:08.119438 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1321 11:16:08.119916 ==
1322 11:16:08.122397 RX Vref Scan: 0
1323 11:16:08.122798
1324 11:16:08.123196 RX Vref 0 -> 0, step: 1
1325 11:16:08.123510
1326 11:16:08.125507 RX Delay -95 -> 252, step: 8
1327 11:16:08.132539 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1328 11:16:08.136164 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1329 11:16:08.138677 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1330 11:16:08.142427 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1331 11:16:08.146107 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1332 11:16:08.152026 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1333 11:16:08.155475 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1334 11:16:08.158871 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1335 11:16:08.161947 iDelay=209, Bit 8, Center 68 (-47 ~ 184) 232
1336 11:16:08.165176 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1337 11:16:08.171698 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1338 11:16:08.175271 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1339 11:16:08.178614 iDelay=209, Bit 12, Center 80 (-31 ~ 192) 224
1340 11:16:08.182474 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1341 11:16:08.188006 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1342 11:16:08.191747 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1343 11:16:08.191839 ==
1344 11:16:08.194784 Dram Type= 6, Freq= 0, CH_0, rank 1
1345 11:16:08.197913 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1346 11:16:08.198012 ==
1347 11:16:08.201523 DQS Delay:
1348 11:16:08.201631 DQS0 = 0, DQS1 = 0
1349 11:16:08.201716 DQM Delay:
1350 11:16:08.205199 DQM0 = 86, DQM1 = 77
1351 11:16:08.205317 DQ Delay:
1352 11:16:08.208689 DQ0 =84, DQ1 =92, DQ2 =80, DQ3 =80
1353 11:16:08.211408 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1354 11:16:08.215077 DQ8 =68, DQ9 =64, DQ10 =80, DQ11 =72
1355 11:16:08.218052 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1356 11:16:08.218281
1357 11:16:08.218417
1358 11:16:08.228028 [DQSOSCAuto] RK1, (LSB)MR18= 0x2722, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
1359 11:16:08.228266 CH0 RK1: MR19=606, MR18=2722
1360 11:16:08.234951 CH0_RK1: MR19=0x606, MR18=0x2722, DQSOSC=400, MR23=63, INC=92, DEC=61
1361 11:16:08.238263 [RxdqsGatingPostProcess] freq 800
1362 11:16:08.245126 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1363 11:16:08.248082 Pre-setting of DQS Precalculation
1364 11:16:08.251284 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1365 11:16:08.251695 ==
1366 11:16:08.255117 Dram Type= 6, Freq= 0, CH_1, rank 0
1367 11:16:08.261095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1368 11:16:08.261176 ==
1369 11:16:08.264204 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1370 11:16:08.271228 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1371 11:16:08.280829 [CA 0] Center 37 (6~68) winsize 63
1372 11:16:08.283833 [CA 1] Center 37 (6~68) winsize 63
1373 11:16:08.286933 [CA 2] Center 34 (4~65) winsize 62
1374 11:16:08.291075 [CA 3] Center 34 (4~65) winsize 62
1375 11:16:08.293450 [CA 4] Center 34 (4~65) winsize 62
1376 11:16:08.296954 [CA 5] Center 33 (3~64) winsize 62
1377 11:16:08.297036
1378 11:16:08.300053 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1379 11:16:08.300140
1380 11:16:08.303817 [CATrainingPosCal] consider 1 rank data
1381 11:16:08.306758 u2DelayCellTimex100 = 270/100 ps
1382 11:16:08.310380 CA0 delay=37 (6~68),Diff = 4 PI (28 cell)
1383 11:16:08.317033 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1384 11:16:08.320676 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1385 11:16:08.324072 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1386 11:16:08.326905 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1387 11:16:08.330106 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1388 11:16:08.330217
1389 11:16:08.333661 CA PerBit enable=1, Macro0, CA PI delay=33
1390 11:16:08.333771
1391 11:16:08.336670 [CBTSetCACLKResult] CA Dly = 33
1392 11:16:08.336752 CS Dly: 4 (0~35)
1393 11:16:08.339996 ==
1394 11:16:08.343484 Dram Type= 6, Freq= 0, CH_1, rank 1
1395 11:16:08.346477 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1396 11:16:08.346559 ==
1397 11:16:08.353158 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1398 11:16:08.356818 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1399 11:16:08.366738 [CA 0] Center 36 (6~67) winsize 62
1400 11:16:08.369648 [CA 1] Center 36 (6~67) winsize 62
1401 11:16:08.373359 [CA 2] Center 35 (4~66) winsize 63
1402 11:16:08.377442 [CA 3] Center 33 (3~64) winsize 62
1403 11:16:08.380223 [CA 4] Center 34 (4~65) winsize 62
1404 11:16:08.383558 [CA 5] Center 33 (3~64) winsize 62
1405 11:16:08.384094
1406 11:16:08.386662 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1407 11:16:08.387132
1408 11:16:08.389666 [CATrainingPosCal] consider 2 rank data
1409 11:16:08.393303 u2DelayCellTimex100 = 270/100 ps
1410 11:16:08.396643 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1411 11:16:08.400049 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1412 11:16:08.404040 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
1413 11:16:08.407984 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1414 11:16:08.410969 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1415 11:16:08.414621 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1416 11:16:08.414732
1417 11:16:08.418891 CA PerBit enable=1, Macro0, CA PI delay=33
1418 11:16:08.419001
1419 11:16:08.422442 [CBTSetCACLKResult] CA Dly = 33
1420 11:16:08.426739 CS Dly: 5 (0~37)
1421 11:16:08.426861
1422 11:16:08.429994 ----->DramcWriteLeveling(PI) begin...
1423 11:16:08.430134 ==
1424 11:16:08.433561 Dram Type= 6, Freq= 0, CH_1, rank 0
1425 11:16:08.437176 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1426 11:16:08.437417 ==
1427 11:16:08.440159 Write leveling (Byte 0): 23 => 23
1428 11:16:08.443929 Write leveling (Byte 1): 28 => 28
1429 11:16:08.444178 DramcWriteLeveling(PI) end<-----
1430 11:16:08.444405
1431 11:16:08.446948 ==
1432 11:16:08.450173 Dram Type= 6, Freq= 0, CH_1, rank 0
1433 11:16:08.453512 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1434 11:16:08.453938 ==
1435 11:16:08.457330 [Gating] SW mode calibration
1436 11:16:08.464091 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1437 11:16:08.467278 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1438 11:16:08.474459 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1439 11:16:08.476838 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1440 11:16:08.480105 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1441 11:16:08.487044 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1442 11:16:08.490745 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1443 11:16:08.493252 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1444 11:16:08.500511 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1445 11:16:08.503586 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1446 11:16:08.506497 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1447 11:16:08.513587 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1448 11:16:08.516525 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1449 11:16:08.520344 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1450 11:16:08.526885 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1451 11:16:08.529847 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1452 11:16:08.533491 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1453 11:16:08.540105 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1454 11:16:08.542865 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1455 11:16:08.546747 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
1456 11:16:08.552820 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1457 11:16:08.556374 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1458 11:16:08.559071 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1459 11:16:08.566138 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1460 11:16:08.569247 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1461 11:16:08.572504 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1462 11:16:08.579767 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1463 11:16:08.582641 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1464 11:16:08.586249 0 9 8 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
1465 11:16:08.592459 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1466 11:16:08.595958 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1467 11:16:08.599178 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1468 11:16:08.605961 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1469 11:16:08.609294 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1470 11:16:08.612844 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1471 11:16:08.616126 0 10 4 | B1->B0 | 3131 3232 | 0 0 | (0 1) (0 0)
1472 11:16:08.622622 0 10 8 | B1->B0 | 2525 2525 | 0 0 | (0 0) (0 0)
1473 11:16:08.626093 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 11:16:08.629418 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 11:16:08.636448 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 11:16:08.639431 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 11:16:08.643339 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 11:16:08.649088 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 11:16:08.652798 0 11 4 | B1->B0 | 2525 2c2c | 0 0 | (0 0) (0 0)
1480 11:16:08.655697 0 11 8 | B1->B0 | 3534 3f3f | 1 0 | (0 0) (0 0)
1481 11:16:08.662567 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1482 11:16:08.666154 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1483 11:16:08.668997 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1484 11:16:08.675992 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1485 11:16:08.679119 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1486 11:16:08.682413 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1487 11:16:08.689339 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1488 11:16:08.692664 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1489 11:16:08.695453 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1490 11:16:08.702619 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1491 11:16:08.705653 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1492 11:16:08.708667 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1493 11:16:08.716092 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1494 11:16:08.718584 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1495 11:16:08.721881 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1496 11:16:08.728671 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1497 11:16:08.732017 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1498 11:16:08.735745 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1499 11:16:08.741742 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1500 11:16:08.745571 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1501 11:16:08.749263 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1502 11:16:08.755845 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1503 11:16:08.758734 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1504 11:16:08.761655 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
1505 11:16:08.765381 Total UI for P1: 0, mck2ui 16
1506 11:16:08.768450 best dqsien dly found for B1: ( 0, 14, 4)
1507 11:16:08.775181 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1508 11:16:08.775742 Total UI for P1: 0, mck2ui 16
1509 11:16:08.778396 best dqsien dly found for B0: ( 0, 14, 6)
1510 11:16:08.784810 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1511 11:16:08.788490 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1512 11:16:08.788917
1513 11:16:08.791784 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1514 11:16:08.794749 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1515 11:16:08.798437 [Gating] SW calibration Done
1516 11:16:08.798967 ==
1517 11:16:08.801641 Dram Type= 6, Freq= 0, CH_1, rank 0
1518 11:16:08.805623 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1519 11:16:08.806255 ==
1520 11:16:08.808156 RX Vref Scan: 0
1521 11:16:08.808706
1522 11:16:08.809231 RX Vref 0 -> 0, step: 1
1523 11:16:08.809832
1524 11:16:08.811697 RX Delay -130 -> 252, step: 16
1525 11:16:08.814754 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1526 11:16:08.821310 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1527 11:16:08.824873 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1528 11:16:08.827766 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1529 11:16:08.831936 iDelay=222, Bit 4, Center 77 (-34 ~ 189) 224
1530 11:16:08.834547 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1531 11:16:08.841364 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1532 11:16:08.844624 iDelay=222, Bit 7, Center 77 (-34 ~ 189) 224
1533 11:16:08.848026 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1534 11:16:08.851037 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1535 11:16:08.854426 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1536 11:16:08.860811 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1537 11:16:08.864469 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1538 11:16:08.868124 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1539 11:16:08.871556 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1540 11:16:08.877371 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1541 11:16:08.877849 ==
1542 11:16:08.880617 Dram Type= 6, Freq= 0, CH_1, rank 0
1543 11:16:08.883892 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1544 11:16:08.884358 ==
1545 11:16:08.884705 DQS Delay:
1546 11:16:08.887919 DQS0 = 0, DQS1 = 0
1547 11:16:08.888428 DQM Delay:
1548 11:16:08.890744 DQM0 = 86, DQM1 = 79
1549 11:16:08.891194 DQ Delay:
1550 11:16:08.894024 DQ0 =93, DQ1 =85, DQ2 =69, DQ3 =85
1551 11:16:08.897081 DQ4 =77, DQ5 =101, DQ6 =101, DQ7 =77
1552 11:16:08.900501 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1553 11:16:08.904133 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1554 11:16:08.904555
1555 11:16:08.904916
1556 11:16:08.905250 ==
1557 11:16:08.907398 Dram Type= 6, Freq= 0, CH_1, rank 0
1558 11:16:08.910621 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1559 11:16:08.913994 ==
1560 11:16:08.914531
1561 11:16:08.914972
1562 11:16:08.915294 TX Vref Scan disable
1563 11:16:08.917246 == TX Byte 0 ==
1564 11:16:08.920817 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1565 11:16:08.923700 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1566 11:16:08.926897 == TX Byte 1 ==
1567 11:16:08.930535 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1568 11:16:08.933524 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1569 11:16:08.937172 ==
1570 11:16:08.940299 Dram Type= 6, Freq= 0, CH_1, rank 0
1571 11:16:08.943729 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1572 11:16:08.944286 ==
1573 11:16:08.956260 TX Vref=22, minBit 2, minWin=26, winSum=437
1574 11:16:08.959663 TX Vref=24, minBit 0, minWin=27, winSum=444
1575 11:16:08.963495 TX Vref=26, minBit 0, minWin=27, winSum=449
1576 11:16:08.966391 TX Vref=28, minBit 0, minWin=27, winSum=453
1577 11:16:08.969523 TX Vref=30, minBit 0, minWin=27, winSum=450
1578 11:16:08.976480 TX Vref=32, minBit 2, minWin=27, winSum=453
1579 11:16:08.979334 [TxChooseVref] Worse bit 0, Min win 27, Win sum 453, Final Vref 28
1580 11:16:08.979758
1581 11:16:08.984378 Final TX Range 1 Vref 28
1582 11:16:08.984797
1583 11:16:08.985219 ==
1584 11:16:08.986605 Dram Type= 6, Freq= 0, CH_1, rank 0
1585 11:16:08.989924 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1586 11:16:08.990550 ==
1587 11:16:08.991068
1588 11:16:08.991545
1589 11:16:08.993771 TX Vref Scan disable
1590 11:16:08.996920 == TX Byte 0 ==
1591 11:16:09.000339 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1592 11:16:09.003606 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1593 11:16:09.006683 == TX Byte 1 ==
1594 11:16:09.009804 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1595 11:16:09.013970 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1596 11:16:09.014396
1597 11:16:09.016586 [DATLAT]
1598 11:16:09.017006 Freq=800, CH1 RK0
1599 11:16:09.017363
1600 11:16:09.020018 DATLAT Default: 0xa
1601 11:16:09.020499 0, 0xFFFF, sum = 0
1602 11:16:09.023180 1, 0xFFFF, sum = 0
1603 11:16:09.023740 2, 0xFFFF, sum = 0
1604 11:16:09.026356 3, 0xFFFF, sum = 0
1605 11:16:09.026784 4, 0xFFFF, sum = 0
1606 11:16:09.029689 5, 0xFFFF, sum = 0
1607 11:16:09.030264 6, 0xFFFF, sum = 0
1608 11:16:09.033281 7, 0xFFFF, sum = 0
1609 11:16:09.036134 8, 0xFFFF, sum = 0
1610 11:16:09.036583 9, 0x0, sum = 1
1611 11:16:09.036957 10, 0x0, sum = 2
1612 11:16:09.039630 11, 0x0, sum = 3
1613 11:16:09.040166 12, 0x0, sum = 4
1614 11:16:09.043193 best_step = 10
1615 11:16:09.043629
1616 11:16:09.043960 ==
1617 11:16:09.046242 Dram Type= 6, Freq= 0, CH_1, rank 0
1618 11:16:09.049859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1619 11:16:09.050455 ==
1620 11:16:09.053007 RX Vref Scan: 1
1621 11:16:09.053534
1622 11:16:09.054041 Set Vref Range= 32 -> 127
1623 11:16:09.056657
1624 11:16:09.057135 RX Vref 32 -> 127, step: 1
1625 11:16:09.057663
1626 11:16:09.059320 RX Delay -95 -> 252, step: 8
1627 11:16:09.059954
1628 11:16:09.062584 Set Vref, RX VrefLevel [Byte0]: 32
1629 11:16:09.066573 [Byte1]: 32
1630 11:16:09.067123
1631 11:16:09.069503 Set Vref, RX VrefLevel [Byte0]: 33
1632 11:16:09.073155 [Byte1]: 33
1633 11:16:09.077334
1634 11:16:09.077754 Set Vref, RX VrefLevel [Byte0]: 34
1635 11:16:09.079967 [Byte1]: 34
1636 11:16:09.084064
1637 11:16:09.084594 Set Vref, RX VrefLevel [Byte0]: 35
1638 11:16:09.087574 [Byte1]: 35
1639 11:16:09.091967
1640 11:16:09.092451 Set Vref, RX VrefLevel [Byte0]: 36
1641 11:16:09.095021 [Byte1]: 36
1642 11:16:09.099644
1643 11:16:09.100212 Set Vref, RX VrefLevel [Byte0]: 37
1644 11:16:09.102624 [Byte1]: 37
1645 11:16:09.107042
1646 11:16:09.107600 Set Vref, RX VrefLevel [Byte0]: 38
1647 11:16:09.110460 [Byte1]: 38
1648 11:16:09.114842
1649 11:16:09.115264 Set Vref, RX VrefLevel [Byte0]: 39
1650 11:16:09.118079 [Byte1]: 39
1651 11:16:09.121987
1652 11:16:09.122406 Set Vref, RX VrefLevel [Byte0]: 40
1653 11:16:09.125445 [Byte1]: 40
1654 11:16:09.130266
1655 11:16:09.130725 Set Vref, RX VrefLevel [Byte0]: 41
1656 11:16:09.133250 [Byte1]: 41
1657 11:16:09.137621
1658 11:16:09.138050 Set Vref, RX VrefLevel [Byte0]: 42
1659 11:16:09.140849 [Byte1]: 42
1660 11:16:09.145109
1661 11:16:09.145529 Set Vref, RX VrefLevel [Byte0]: 43
1662 11:16:09.148330 [Byte1]: 43
1663 11:16:09.152541
1664 11:16:09.152988 Set Vref, RX VrefLevel [Byte0]: 44
1665 11:16:09.156465 [Byte1]: 44
1666 11:16:09.160217
1667 11:16:09.160669 Set Vref, RX VrefLevel [Byte0]: 45
1668 11:16:09.163570 [Byte1]: 45
1669 11:16:09.167813
1670 11:16:09.168277 Set Vref, RX VrefLevel [Byte0]: 46
1671 11:16:09.171151 [Byte1]: 46
1672 11:16:09.175539
1673 11:16:09.176105 Set Vref, RX VrefLevel [Byte0]: 47
1674 11:16:09.178529 [Byte1]: 47
1675 11:16:09.182983
1676 11:16:09.183419 Set Vref, RX VrefLevel [Byte0]: 48
1677 11:16:09.186153 [Byte1]: 48
1678 11:16:09.190995
1679 11:16:09.191556 Set Vref, RX VrefLevel [Byte0]: 49
1680 11:16:09.193858 [Byte1]: 49
1681 11:16:09.199105
1682 11:16:09.199534 Set Vref, RX VrefLevel [Byte0]: 50
1683 11:16:09.201307 [Byte1]: 50
1684 11:16:09.206146
1685 11:16:09.206682 Set Vref, RX VrefLevel [Byte0]: 51
1686 11:16:09.210242 [Byte1]: 51
1687 11:16:09.213675
1688 11:16:09.214258 Set Vref, RX VrefLevel [Byte0]: 52
1689 11:16:09.216741 [Byte1]: 52
1690 11:16:09.221017
1691 11:16:09.221436 Set Vref, RX VrefLevel [Byte0]: 53
1692 11:16:09.224283 [Byte1]: 53
1693 11:16:09.228598
1694 11:16:09.229040 Set Vref, RX VrefLevel [Byte0]: 54
1695 11:16:09.232077 [Byte1]: 54
1696 11:16:09.236320
1697 11:16:09.236756 Set Vref, RX VrefLevel [Byte0]: 55
1698 11:16:09.239700 [Byte1]: 55
1699 11:16:09.243826
1700 11:16:09.244305 Set Vref, RX VrefLevel [Byte0]: 56
1701 11:16:09.247187 [Byte1]: 56
1702 11:16:09.251317
1703 11:16:09.251913 Set Vref, RX VrefLevel [Byte0]: 57
1704 11:16:09.255327 [Byte1]: 57
1705 11:16:09.259343
1706 11:16:09.259764 Set Vref, RX VrefLevel [Byte0]: 58
1707 11:16:09.262729 [Byte1]: 58
1708 11:16:09.266675
1709 11:16:09.267097 Set Vref, RX VrefLevel [Byte0]: 59
1710 11:16:09.269784 [Byte1]: 59
1711 11:16:09.274163
1712 11:16:09.274683 Set Vref, RX VrefLevel [Byte0]: 60
1713 11:16:09.277585 [Byte1]: 60
1714 11:16:09.281732
1715 11:16:09.282267 Set Vref, RX VrefLevel [Byte0]: 61
1716 11:16:09.285446 [Byte1]: 61
1717 11:16:09.289389
1718 11:16:09.289979 Set Vref, RX VrefLevel [Byte0]: 62
1719 11:16:09.292539 [Byte1]: 62
1720 11:16:09.296923
1721 11:16:09.297342 Set Vref, RX VrefLevel [Byte0]: 63
1722 11:16:09.301811 [Byte1]: 63
1723 11:16:09.305045
1724 11:16:09.305560 Set Vref, RX VrefLevel [Byte0]: 64
1725 11:16:09.308306 [Byte1]: 64
1726 11:16:09.312066
1727 11:16:09.312624 Set Vref, RX VrefLevel [Byte0]: 65
1728 11:16:09.315634 [Byte1]: 65
1729 11:16:09.319693
1730 11:16:09.320264 Set Vref, RX VrefLevel [Byte0]: 66
1731 11:16:09.322737 [Byte1]: 66
1732 11:16:09.327180
1733 11:16:09.327730 Set Vref, RX VrefLevel [Byte0]: 67
1734 11:16:09.331219 [Byte1]: 67
1735 11:16:09.335021
1736 11:16:09.335509 Set Vref, RX VrefLevel [Byte0]: 68
1737 11:16:09.338508 [Byte1]: 68
1738 11:16:09.342466
1739 11:16:09.343017 Set Vref, RX VrefLevel [Byte0]: 69
1740 11:16:09.346422 [Byte1]: 69
1741 11:16:09.349948
1742 11:16:09.350518 Set Vref, RX VrefLevel [Byte0]: 70
1743 11:16:09.353517 [Byte1]: 70
1744 11:16:09.357870
1745 11:16:09.358436 Set Vref, RX VrefLevel [Byte0]: 71
1746 11:16:09.360923 [Byte1]: 71
1747 11:16:09.365466
1748 11:16:09.365916 Set Vref, RX VrefLevel [Byte0]: 72
1749 11:16:09.368835 [Byte1]: 72
1750 11:16:09.373203
1751 11:16:09.373755 Set Vref, RX VrefLevel [Byte0]: 73
1752 11:16:09.376622 [Byte1]: 73
1753 11:16:09.380851
1754 11:16:09.381457 Set Vref, RX VrefLevel [Byte0]: 74
1755 11:16:09.383756 [Byte1]: 74
1756 11:16:09.387984
1757 11:16:09.388506 Set Vref, RX VrefLevel [Byte0]: 75
1758 11:16:09.391429 [Byte1]: 75
1759 11:16:09.395654
1760 11:16:09.396235 Set Vref, RX VrefLevel [Byte0]: 76
1761 11:16:09.399242 [Byte1]: 76
1762 11:16:09.403228
1763 11:16:09.403728 Set Vref, RX VrefLevel [Byte0]: 77
1764 11:16:09.406616 [Byte1]: 77
1765 11:16:09.410895
1766 11:16:09.411315 Final RX Vref Byte 0 = 59 to rank0
1767 11:16:09.414211 Final RX Vref Byte 1 = 58 to rank0
1768 11:16:09.417723 Final RX Vref Byte 0 = 59 to rank1
1769 11:16:09.420899 Final RX Vref Byte 1 = 58 to rank1==
1770 11:16:09.424786 Dram Type= 6, Freq= 0, CH_1, rank 0
1771 11:16:09.431220 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1772 11:16:09.431775 ==
1773 11:16:09.432256 DQS Delay:
1774 11:16:09.432585 DQS0 = 0, DQS1 = 0
1775 11:16:09.434094 DQM Delay:
1776 11:16:09.434530 DQM0 = 85, DQM1 = 81
1777 11:16:09.437644 DQ Delay:
1778 11:16:09.441074 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1779 11:16:09.444027 DQ4 =80, DQ5 =96, DQ6 =96, DQ7 =80
1780 11:16:09.444488 DQ8 =72, DQ9 =72, DQ10 =80, DQ11 =72
1781 11:16:09.451228 DQ12 =88, DQ13 =92, DQ14 =84, DQ15 =88
1782 11:16:09.451672
1783 11:16:09.452076
1784 11:16:09.457203 [DQSOSCAuto] RK0, (LSB)MR18= 0x1326, (MSB)MR19= 0x606, tDQSOscB0 = 400 ps tDQSOscB1 = 405 ps
1785 11:16:09.460678 CH1 RK0: MR19=606, MR18=1326
1786 11:16:09.467600 CH1_RK0: MR19=0x606, MR18=0x1326, DQSOSC=400, MR23=63, INC=92, DEC=61
1787 11:16:09.468079
1788 11:16:09.470452 ----->DramcWriteLeveling(PI) begin...
1789 11:16:09.470903 ==
1790 11:16:09.474089 Dram Type= 6, Freq= 0, CH_1, rank 1
1791 11:16:09.477558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1792 11:16:09.478095 ==
1793 11:16:09.480403 Write leveling (Byte 0): 25 => 25
1794 11:16:09.484146 Write leveling (Byte 1): 25 => 25
1795 11:16:09.487245 DramcWriteLeveling(PI) end<-----
1796 11:16:09.487900
1797 11:16:09.488355 ==
1798 11:16:09.490848 Dram Type= 6, Freq= 0, CH_1, rank 1
1799 11:16:09.493934 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1800 11:16:09.494496 ==
1801 11:16:09.497088 [Gating] SW mode calibration
1802 11:16:09.503918 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1803 11:16:09.510628 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1804 11:16:09.513692 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1805 11:16:09.520431 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1806 11:16:09.523164 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1807 11:16:09.526849 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1808 11:16:09.533224 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1809 11:16:09.536641 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1810 11:16:09.539689 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1811 11:16:09.546543 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1812 11:16:09.550102 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1813 11:16:09.553147 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1814 11:16:09.559776 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1815 11:16:09.563345 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1816 11:16:09.566597 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1817 11:16:09.573031 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1818 11:16:09.576224 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1819 11:16:09.579676 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1820 11:16:09.583154 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1821 11:16:09.589694 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1822 11:16:09.592859 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1823 11:16:09.596501 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1824 11:16:09.602770 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1825 11:16:09.606449 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1826 11:16:09.609985 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1827 11:16:09.616534 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1828 11:16:09.619263 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1829 11:16:09.622643 0 9 4 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
1830 11:16:09.629482 0 9 8 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1831 11:16:09.632864 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1832 11:16:09.635975 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1833 11:16:09.643147 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1834 11:16:09.645759 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1835 11:16:09.649188 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1836 11:16:09.655998 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
1837 11:16:09.659195 0 10 4 | B1->B0 | 3333 2a2a | 0 1 | (0 0) (1 0)
1838 11:16:09.662463 0 10 8 | B1->B0 | 2b2b 2323 | 0 0 | (0 0) (0 0)
1839 11:16:09.669149 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 11:16:09.672782 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 11:16:09.675560 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 11:16:09.682155 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 11:16:09.685584 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 11:16:09.688702 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 11:16:09.695375 0 11 4 | B1->B0 | 2323 3939 | 0 0 | (0 0) (0 0)
1846 11:16:09.698907 0 11 8 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
1847 11:16:09.702129 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1848 11:16:09.708684 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1849 11:16:09.712224 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1850 11:16:09.715468 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1851 11:16:09.721710 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1852 11:16:09.725148 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
1853 11:16:09.728336 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1854 11:16:09.735569 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1855 11:16:09.738342 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1856 11:16:09.742233 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1857 11:16:09.748742 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1858 11:16:09.751963 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1859 11:16:09.755381 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1860 11:16:09.761476 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1861 11:16:09.764549 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1862 11:16:09.768148 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1863 11:16:09.774850 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1864 11:16:09.778534 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1865 11:16:09.781607 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1866 11:16:09.788587 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1867 11:16:09.791045 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1868 11:16:09.794557 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
1869 11:16:09.797691 Total UI for P1: 0, mck2ui 16
1870 11:16:09.801150 best dqsien dly found for B0: ( 0, 13, 30)
1871 11:16:09.807430 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1872 11:16:09.811130 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1873 11:16:09.814380 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1874 11:16:09.817419 Total UI for P1: 0, mck2ui 16
1875 11:16:09.821322 best dqsien dly found for B1: ( 0, 14, 8)
1876 11:16:09.824172 best DQS0 dly(MCK, UI, PI) = (0, 13, 30)
1877 11:16:09.827386 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1878 11:16:09.827486
1879 11:16:09.830931 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 30)
1880 11:16:09.837734 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1881 11:16:09.837865 [Gating] SW calibration Done
1882 11:16:09.837929 ==
1883 11:16:09.841552 Dram Type= 6, Freq= 0, CH_1, rank 1
1884 11:16:09.847721 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1885 11:16:09.847803 ==
1886 11:16:09.847868 RX Vref Scan: 0
1887 11:16:09.847929
1888 11:16:09.850770 RX Vref 0 -> 0, step: 1
1889 11:16:09.850851
1890 11:16:09.853972 RX Delay -130 -> 252, step: 16
1891 11:16:09.857408 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1892 11:16:09.860420 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1893 11:16:09.864589 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1894 11:16:09.870405 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1895 11:16:09.873886 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1896 11:16:09.877114 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1897 11:16:09.880821 iDelay=206, Bit 6, Center 85 (-34 ~ 205) 240
1898 11:16:09.884025 iDelay=206, Bit 7, Center 77 (-50 ~ 205) 256
1899 11:16:09.890458 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1900 11:16:09.894273 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1901 11:16:09.897035 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1902 11:16:09.900469 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1903 11:16:09.903591 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1904 11:16:09.910172 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1905 11:16:09.913651 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1906 11:16:09.917751 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1907 11:16:09.917833 ==
1908 11:16:09.920129 Dram Type= 6, Freq= 0, CH_1, rank 1
1909 11:16:09.923800 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1910 11:16:09.927210 ==
1911 11:16:09.927297 DQS Delay:
1912 11:16:09.927364 DQS0 = 0, DQS1 = 0
1913 11:16:09.930036 DQM Delay:
1914 11:16:09.930128 DQM0 = 81, DQM1 = 79
1915 11:16:09.933641 DQ Delay:
1916 11:16:09.937074 DQ0 =85, DQ1 =77, DQ2 =69, DQ3 =77
1917 11:16:09.937175 DQ4 =85, DQ5 =93, DQ6 =85, DQ7 =77
1918 11:16:09.940416 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1919 11:16:09.943835 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1920 11:16:09.946767
1921 11:16:09.946886
1922 11:16:09.946981 ==
1923 11:16:09.950015 Dram Type= 6, Freq= 0, CH_1, rank 1
1924 11:16:09.953618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1925 11:16:09.953753 ==
1926 11:16:09.953860
1927 11:16:09.953958
1928 11:16:09.956415 TX Vref Scan disable
1929 11:16:09.956496 == TX Byte 0 ==
1930 11:16:09.963364 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1931 11:16:09.966696 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1932 11:16:09.966777 == TX Byte 1 ==
1933 11:16:09.973405 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1934 11:16:09.977016 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1935 11:16:09.977098 ==
1936 11:16:09.979642 Dram Type= 6, Freq= 0, CH_1, rank 1
1937 11:16:09.982932 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1938 11:16:09.983014 ==
1939 11:16:09.997202 TX Vref=22, minBit 1, minWin=27, winSum=448
1940 11:16:09.999963 TX Vref=24, minBit 1, minWin=27, winSum=450
1941 11:16:10.003279 TX Vref=26, minBit 6, minWin=27, winSum=453
1942 11:16:10.006744 TX Vref=28, minBit 6, minWin=27, winSum=454
1943 11:16:10.010019 TX Vref=30, minBit 0, minWin=28, winSum=457
1944 11:16:10.016544 TX Vref=32, minBit 1, minWin=27, winSum=453
1945 11:16:10.019965 [TxChooseVref] Worse bit 0, Min win 28, Win sum 457, Final Vref 30
1946 11:16:10.020078
1947 11:16:10.023502 Final TX Range 1 Vref 30
1948 11:16:10.023583
1949 11:16:10.023647 ==
1950 11:16:10.026792 Dram Type= 6, Freq= 0, CH_1, rank 1
1951 11:16:10.030407 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1952 11:16:10.030489 ==
1953 11:16:10.033339
1954 11:16:10.033419
1955 11:16:10.033483 TX Vref Scan disable
1956 11:16:10.036611 == TX Byte 0 ==
1957 11:16:10.039944 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1958 11:16:10.046834 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1959 11:16:10.046937 == TX Byte 1 ==
1960 11:16:10.049840 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
1961 11:16:10.056702 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
1962 11:16:10.056789
1963 11:16:10.056859 [DATLAT]
1964 11:16:10.056923 Freq=800, CH1 RK1
1965 11:16:10.056986
1966 11:16:10.059625 DATLAT Default: 0xa
1967 11:16:10.059706 0, 0xFFFF, sum = 0
1968 11:16:10.063168 1, 0xFFFF, sum = 0
1969 11:16:10.066173 2, 0xFFFF, sum = 0
1970 11:16:10.066261 3, 0xFFFF, sum = 0
1971 11:16:10.069798 4, 0xFFFF, sum = 0
1972 11:16:10.069881 5, 0xFFFF, sum = 0
1973 11:16:10.072889 6, 0xFFFF, sum = 0
1974 11:16:10.072970 7, 0xFFFF, sum = 0
1975 11:16:10.076831 8, 0xFFFF, sum = 0
1976 11:16:10.076913 9, 0x0, sum = 1
1977 11:16:10.079819 10, 0x0, sum = 2
1978 11:16:10.079900 11, 0x0, sum = 3
1979 11:16:10.079966 12, 0x0, sum = 4
1980 11:16:10.083093 best_step = 10
1981 11:16:10.083174
1982 11:16:10.083239 ==
1983 11:16:10.086723 Dram Type= 6, Freq= 0, CH_1, rank 1
1984 11:16:10.089472 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1985 11:16:10.089553 ==
1986 11:16:10.092913 RX Vref Scan: 0
1987 11:16:10.092993
1988 11:16:10.096320 RX Vref 0 -> 0, step: 1
1989 11:16:10.096408
1990 11:16:10.096477 RX Delay -95 -> 252, step: 8
1991 11:16:10.103319 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
1992 11:16:10.106910 iDelay=209, Bit 1, Center 84 (-31 ~ 200) 232
1993 11:16:10.109955 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
1994 11:16:10.113253 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1995 11:16:10.116962 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1996 11:16:10.123923 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
1997 11:16:10.126582 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1998 11:16:10.129863 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
1999 11:16:10.132869 iDelay=209, Bit 8, Center 76 (-31 ~ 184) 216
2000 11:16:10.136516 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2001 11:16:10.143278 iDelay=209, Bit 10, Center 88 (-23 ~ 200) 224
2002 11:16:10.146591 iDelay=209, Bit 11, Center 76 (-31 ~ 184) 216
2003 11:16:10.149950 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2004 11:16:10.153047 iDelay=209, Bit 13, Center 88 (-23 ~ 200) 224
2005 11:16:10.159438 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
2006 11:16:10.162693 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2007 11:16:10.162803 ==
2008 11:16:10.166372 Dram Type= 6, Freq= 0, CH_1, rank 1
2009 11:16:10.169995 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2010 11:16:10.170082 ==
2011 11:16:10.172780 DQS Delay:
2012 11:16:10.172866 DQS0 = 0, DQS1 = 0
2013 11:16:10.172936 DQM Delay:
2014 11:16:10.176220 DQM0 = 86, DQM1 = 83
2015 11:16:10.176301 DQ Delay:
2016 11:16:10.179654 DQ0 =92, DQ1 =84, DQ2 =76, DQ3 =80
2017 11:16:10.183086 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
2018 11:16:10.186732 DQ8 =76, DQ9 =72, DQ10 =88, DQ11 =76
2019 11:16:10.190253 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
2020 11:16:10.190700
2021 11:16:10.191039
2022 11:16:10.199295 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a35, (MSB)MR19= 0x606, tDQSOscB0 = 396 ps tDQSOscB1 = 403 ps
2023 11:16:10.199891 CH1 RK1: MR19=606, MR18=1A35
2024 11:16:10.206050 CH1_RK1: MR19=0x606, MR18=0x1A35, DQSOSC=396, MR23=63, INC=94, DEC=62
2025 11:16:10.209859 [RxdqsGatingPostProcess] freq 800
2026 11:16:10.216210 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2027 11:16:10.219530 Pre-setting of DQS Precalculation
2028 11:16:10.222549 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2029 11:16:10.232654 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2030 11:16:10.239103 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2031 11:16:10.239527
2032 11:16:10.239860
2033 11:16:10.242631 [Calibration Summary] 1600 Mbps
2034 11:16:10.243049 CH 0, Rank 0
2035 11:16:10.245808 SW Impedance : PASS
2036 11:16:10.246224 DUTY Scan : NO K
2037 11:16:10.249019 ZQ Calibration : PASS
2038 11:16:10.252890 Jitter Meter : NO K
2039 11:16:10.252970 CBT Training : PASS
2040 11:16:10.255506 Write leveling : PASS
2041 11:16:10.259064 RX DQS gating : PASS
2042 11:16:10.259144 RX DQ/DQS(RDDQC) : PASS
2043 11:16:10.262451 TX DQ/DQS : PASS
2044 11:16:10.262537 RX DATLAT : PASS
2045 11:16:10.265457 RX DQ/DQS(Engine): PASS
2046 11:16:10.269064 TX OE : NO K
2047 11:16:10.269165 All Pass.
2048 11:16:10.269245
2049 11:16:10.269318 CH 0, Rank 1
2050 11:16:10.271977 SW Impedance : PASS
2051 11:16:10.275411 DUTY Scan : NO K
2052 11:16:10.275520 ZQ Calibration : PASS
2053 11:16:10.278925 Jitter Meter : NO K
2054 11:16:10.282138 CBT Training : PASS
2055 11:16:10.282258 Write leveling : PASS
2056 11:16:10.285801 RX DQS gating : PASS
2057 11:16:10.288532 RX DQ/DQS(RDDQC) : PASS
2058 11:16:10.288613 TX DQ/DQS : PASS
2059 11:16:10.291958 RX DATLAT : PASS
2060 11:16:10.295278 RX DQ/DQS(Engine): PASS
2061 11:16:10.295382 TX OE : NO K
2062 11:16:10.298648 All Pass.
2063 11:16:10.298728
2064 11:16:10.298791 CH 1, Rank 0
2065 11:16:10.302094 SW Impedance : PASS
2066 11:16:10.302174 DUTY Scan : NO K
2067 11:16:10.305375 ZQ Calibration : PASS
2068 11:16:10.308553 Jitter Meter : NO K
2069 11:16:10.308635 CBT Training : PASS
2070 11:16:10.311920 Write leveling : PASS
2071 11:16:10.315105 RX DQS gating : PASS
2072 11:16:10.315187 RX DQ/DQS(RDDQC) : PASS
2073 11:16:10.318173 TX DQ/DQS : PASS
2074 11:16:10.321799 RX DATLAT : PASS
2075 11:16:10.321880 RX DQ/DQS(Engine): PASS
2076 11:16:10.324941 TX OE : NO K
2077 11:16:10.325029 All Pass.
2078 11:16:10.325098
2079 11:16:10.328338 CH 1, Rank 1
2080 11:16:10.328425 SW Impedance : PASS
2081 11:16:10.332081 DUTY Scan : NO K
2082 11:16:10.335114 ZQ Calibration : PASS
2083 11:16:10.335301 Jitter Meter : NO K
2084 11:16:10.338424 CBT Training : PASS
2085 11:16:10.338574 Write leveling : PASS
2086 11:16:10.341560 RX DQS gating : PASS
2087 11:16:10.344993 RX DQ/DQS(RDDQC) : PASS
2088 11:16:10.345158 TX DQ/DQS : PASS
2089 11:16:10.347908 RX DATLAT : PASS
2090 11:16:10.351423 RX DQ/DQS(Engine): PASS
2091 11:16:10.351613 TX OE : NO K
2092 11:16:10.354861 All Pass.
2093 11:16:10.355072
2094 11:16:10.355203 DramC Write-DBI off
2095 11:16:10.358009 PER_BANK_REFRESH: Hybrid Mode
2096 11:16:10.361403 TX_TRACKING: ON
2097 11:16:10.365043 [GetDramInforAfterCalByMRR] Vendor 6.
2098 11:16:10.368905 [GetDramInforAfterCalByMRR] Revision 606.
2099 11:16:10.371401 [GetDramInforAfterCalByMRR] Revision 2 0.
2100 11:16:10.371630 MR0 0x3b3b
2101 11:16:10.371819 MR8 0x5151
2102 11:16:10.378040 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2103 11:16:10.378356
2104 11:16:10.378599 MR0 0x3b3b
2105 11:16:10.378824 MR8 0x5151
2106 11:16:10.381360 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2107 11:16:10.381746
2108 11:16:10.391232 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2109 11:16:10.394720 [FAST_K] Save calibration result to emmc
2110 11:16:10.398050 [FAST_K] Save calibration result to emmc
2111 11:16:10.401407 dram_init: config_dvfs: 1
2112 11:16:10.404751 dramc_set_vcore_voltage set vcore to 662500
2113 11:16:10.407689 Read voltage for 1200, 2
2114 11:16:10.408148 Vio18 = 0
2115 11:16:10.408578 Vcore = 662500
2116 11:16:10.411401 Vdram = 0
2117 11:16:10.411827 Vddq = 0
2118 11:16:10.412379 Vmddr = 0
2119 11:16:10.418076 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2120 11:16:10.421087 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2121 11:16:10.424292 MEM_TYPE=3, freq_sel=15
2122 11:16:10.428072 sv_algorithm_assistance_LP4_1600
2123 11:16:10.431276 ============ PULL DRAM RESETB DOWN ============
2124 11:16:10.437557 ========== PULL DRAM RESETB DOWN end =========
2125 11:16:10.440883 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2126 11:16:10.444462 ===================================
2127 11:16:10.447728 LPDDR4 DRAM CONFIGURATION
2128 11:16:10.451252 ===================================
2129 11:16:10.451670 EX_ROW_EN[0] = 0x0
2130 11:16:10.454427 EX_ROW_EN[1] = 0x0
2131 11:16:10.454850 LP4Y_EN = 0x0
2132 11:16:10.458069 WORK_FSP = 0x0
2133 11:16:10.458484 WL = 0x4
2134 11:16:10.460904 RL = 0x4
2135 11:16:10.461315 BL = 0x2
2136 11:16:10.464329 RPST = 0x0
2137 11:16:10.464744 RD_PRE = 0x0
2138 11:16:10.467265 WR_PRE = 0x1
2139 11:16:10.470851 WR_PST = 0x0
2140 11:16:10.471266 DBI_WR = 0x0
2141 11:16:10.474662 DBI_RD = 0x0
2142 11:16:10.475194 OTF = 0x1
2143 11:16:10.477389 ===================================
2144 11:16:10.480944 ===================================
2145 11:16:10.481376 ANA top config
2146 11:16:10.483935 ===================================
2147 11:16:10.487156 DLL_ASYNC_EN = 0
2148 11:16:10.490627 ALL_SLAVE_EN = 0
2149 11:16:10.493693 NEW_RANK_MODE = 1
2150 11:16:10.497248 DLL_IDLE_MODE = 1
2151 11:16:10.497673 LP45_APHY_COMB_EN = 1
2152 11:16:10.500226 TX_ODT_DIS = 1
2153 11:16:10.503726 NEW_8X_MODE = 1
2154 11:16:10.506892 ===================================
2155 11:16:10.510719 ===================================
2156 11:16:10.513404 data_rate = 2400
2157 11:16:10.517335 CKR = 1
2158 11:16:10.520683 DQ_P2S_RATIO = 8
2159 11:16:10.523508 ===================================
2160 11:16:10.523940 CA_P2S_RATIO = 8
2161 11:16:10.527331 DQ_CA_OPEN = 0
2162 11:16:10.530768 DQ_SEMI_OPEN = 0
2163 11:16:10.533486 CA_SEMI_OPEN = 0
2164 11:16:10.537100 CA_FULL_RATE = 0
2165 11:16:10.539885 DQ_CKDIV4_EN = 0
2166 11:16:10.540401 CA_CKDIV4_EN = 0
2167 11:16:10.543561 CA_PREDIV_EN = 0
2168 11:16:10.546999 PH8_DLY = 17
2169 11:16:10.550121 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2170 11:16:10.553761 DQ_AAMCK_DIV = 4
2171 11:16:10.556392 CA_AAMCK_DIV = 4
2172 11:16:10.556808 CA_ADMCK_DIV = 4
2173 11:16:10.559925 DQ_TRACK_CA_EN = 0
2174 11:16:10.563288 CA_PICK = 1200
2175 11:16:10.566565 CA_MCKIO = 1200
2176 11:16:10.569604 MCKIO_SEMI = 0
2177 11:16:10.573405 PLL_FREQ = 2366
2178 11:16:10.576765 DQ_UI_PI_RATIO = 32
2179 11:16:10.577209 CA_UI_PI_RATIO = 0
2180 11:16:10.579989 ===================================
2181 11:16:10.582903 ===================================
2182 11:16:10.586433 memory_type:LPDDR4
2183 11:16:10.589845 GP_NUM : 10
2184 11:16:10.590257 SRAM_EN : 1
2185 11:16:10.593234 MD32_EN : 0
2186 11:16:10.596395 ===================================
2187 11:16:10.599714 [ANA_INIT] >>>>>>>>>>>>>>
2188 11:16:10.603120 <<<<<< [CONFIGURE PHASE]: ANA_TX
2189 11:16:10.606644 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2190 11:16:10.609744 ===================================
2191 11:16:10.610161 data_rate = 2400,PCW = 0X5b00
2192 11:16:10.612953 ===================================
2193 11:16:10.619822 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2194 11:16:10.622659 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2195 11:16:10.630051 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2196 11:16:10.632793 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2197 11:16:10.635969 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2198 11:16:10.639279 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2199 11:16:10.642602 [ANA_INIT] flow start
2200 11:16:10.645717 [ANA_INIT] PLL >>>>>>>>
2201 11:16:10.646169 [ANA_INIT] PLL <<<<<<<<
2202 11:16:10.649432 [ANA_INIT] MIDPI >>>>>>>>
2203 11:16:10.652574 [ANA_INIT] MIDPI <<<<<<<<
2204 11:16:10.652994 [ANA_INIT] DLL >>>>>>>>
2205 11:16:10.656188 [ANA_INIT] DLL <<<<<<<<
2206 11:16:10.659086 [ANA_INIT] flow end
2207 11:16:10.662698 ============ LP4 DIFF to SE enter ============
2208 11:16:10.666280 ============ LP4 DIFF to SE exit ============
2209 11:16:10.669071 [ANA_INIT] <<<<<<<<<<<<<
2210 11:16:10.672349 [Flow] Enable top DCM control >>>>>
2211 11:16:10.675569 [Flow] Enable top DCM control <<<<<
2212 11:16:10.678496 Enable DLL master slave shuffle
2213 11:16:10.682142 ==============================================================
2214 11:16:10.685182 Gating Mode config
2215 11:16:10.691697 ==============================================================
2216 11:16:10.691834 Config description:
2217 11:16:10.701741 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2218 11:16:10.708899 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2219 11:16:10.715129 SELPH_MODE 0: By rank 1: By Phase
2220 11:16:10.718301 ==============================================================
2221 11:16:10.721665 GAT_TRACK_EN = 1
2222 11:16:10.725607 RX_GATING_MODE = 2
2223 11:16:10.728814 RX_GATING_TRACK_MODE = 2
2224 11:16:10.731837 SELPH_MODE = 1
2225 11:16:10.735031 PICG_EARLY_EN = 1
2226 11:16:10.738632 VALID_LAT_VALUE = 1
2227 11:16:10.742047 ==============================================================
2228 11:16:10.745130 Enter into Gating configuration >>>>
2229 11:16:10.748521 Exit from Gating configuration <<<<
2230 11:16:10.752424 Enter into DVFS_PRE_config >>>>>
2231 11:16:10.765858 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2232 11:16:10.768632 Exit from DVFS_PRE_config <<<<<
2233 11:16:10.769010 Enter into PICG configuration >>>>
2234 11:16:10.771952 Exit from PICG configuration <<<<
2235 11:16:10.775396 [RX_INPUT] configuration >>>>>
2236 11:16:10.778443 [RX_INPUT] configuration <<<<<
2237 11:16:10.785028 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2238 11:16:10.788917 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2239 11:16:10.795232 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2240 11:16:10.801920 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2241 11:16:10.808516 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2242 11:16:10.814843 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2243 11:16:10.818125 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2244 11:16:10.821381 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2245 11:16:10.824946 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2246 11:16:10.831811 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2247 11:16:10.835069 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2248 11:16:10.837897 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2249 11:16:10.841363 ===================================
2250 11:16:10.845148 LPDDR4 DRAM CONFIGURATION
2251 11:16:10.847950 ===================================
2252 11:16:10.851536 EX_ROW_EN[0] = 0x0
2253 11:16:10.851994 EX_ROW_EN[1] = 0x0
2254 11:16:10.855487 LP4Y_EN = 0x0
2255 11:16:10.855925 WORK_FSP = 0x0
2256 11:16:10.858452 WL = 0x4
2257 11:16:10.858896 RL = 0x4
2258 11:16:10.861485 BL = 0x2
2259 11:16:10.861905 RPST = 0x0
2260 11:16:10.864557 RD_PRE = 0x0
2261 11:16:10.864977 WR_PRE = 0x1
2262 11:16:10.867962 WR_PST = 0x0
2263 11:16:10.868430 DBI_WR = 0x0
2264 11:16:10.871161 DBI_RD = 0x0
2265 11:16:10.874160 OTF = 0x1
2266 11:16:10.877697 ===================================
2267 11:16:10.881435 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2268 11:16:10.884551 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2269 11:16:10.887603 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2270 11:16:10.890973 ===================================
2271 11:16:10.894520 LPDDR4 DRAM CONFIGURATION
2272 11:16:10.897634 ===================================
2273 11:16:10.901184 EX_ROW_EN[0] = 0x10
2274 11:16:10.901631 EX_ROW_EN[1] = 0x0
2275 11:16:10.904363 LP4Y_EN = 0x0
2276 11:16:10.904840 WORK_FSP = 0x0
2277 11:16:10.907791 WL = 0x4
2278 11:16:10.908269 RL = 0x4
2279 11:16:10.910870 BL = 0x2
2280 11:16:10.911287 RPST = 0x0
2281 11:16:10.914170 RD_PRE = 0x0
2282 11:16:10.914591 WR_PRE = 0x1
2283 11:16:10.917421 WR_PST = 0x0
2284 11:16:10.917896 DBI_WR = 0x0
2285 11:16:10.920859 DBI_RD = 0x0
2286 11:16:10.921278 OTF = 0x1
2287 11:16:10.924129 ===================================
2288 11:16:10.930506 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2289 11:16:10.931004 ==
2290 11:16:10.933838 Dram Type= 6, Freq= 0, CH_0, rank 0
2291 11:16:10.940815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2292 11:16:10.941261 ==
2293 11:16:10.941623 [Duty_Offset_Calibration]
2294 11:16:10.944179 B0:2 B1:0 CA:4
2295 11:16:10.944848
2296 11:16:10.947371 [DutyScan_Calibration_Flow] k_type=0
2297 11:16:10.955812
2298 11:16:10.956386 ==CLK 0==
2299 11:16:10.958566 Final CLK duty delay cell = -4
2300 11:16:10.962736 [-4] MAX Duty = 5031%(X100), DQS PI = 14
2301 11:16:10.965515 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2302 11:16:10.968725 [-4] AVG Duty = 4937%(X100)
2303 11:16:10.969136
2304 11:16:10.971920 CH0 CLK Duty spec in!! Max-Min= 187%
2305 11:16:10.975709 [DutyScan_Calibration_Flow] ====Done====
2306 11:16:10.976167
2307 11:16:10.978757 [DutyScan_Calibration_Flow] k_type=1
2308 11:16:10.994403
2309 11:16:10.994810 ==DQS 0 ==
2310 11:16:10.997828 Final DQS duty delay cell = -4
2311 11:16:11.001179 [-4] MAX Duty = 4969%(X100), DQS PI = 14
2312 11:16:11.004551 [-4] MIN Duty = 4876%(X100), DQS PI = 2
2313 11:16:11.007428 [-4] AVG Duty = 4922%(X100)
2314 11:16:11.007834
2315 11:16:11.008217 ==DQS 1 ==
2316 11:16:11.010945 Final DQS duty delay cell = 0
2317 11:16:11.014667 [0] MAX Duty = 5125%(X100), DQS PI = 4
2318 11:16:11.017285 [0] MIN Duty = 5000%(X100), DQS PI = 0
2319 11:16:11.021249 [0] AVG Duty = 5062%(X100)
2320 11:16:11.021714
2321 11:16:11.024172 CH0 DQS 0 Duty spec in!! Max-Min= 93%
2322 11:16:11.024622
2323 11:16:11.027552 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2324 11:16:11.030674 [DutyScan_Calibration_Flow] ====Done====
2325 11:16:11.031122
2326 11:16:11.034021 [DutyScan_Calibration_Flow] k_type=3
2327 11:16:11.051000
2328 11:16:11.051406 ==DQM 0 ==
2329 11:16:11.054367 Final DQM duty delay cell = 0
2330 11:16:11.057767 [0] MAX Duty = 5125%(X100), DQS PI = 20
2331 11:16:11.061014 [0] MIN Duty = 4844%(X100), DQS PI = 50
2332 11:16:11.064241 [0] AVG Duty = 4984%(X100)
2333 11:16:11.064717
2334 11:16:11.065060 ==DQM 1 ==
2335 11:16:11.067640 Final DQM duty delay cell = 0
2336 11:16:11.070592 [0] MAX Duty = 4969%(X100), DQS PI = 0
2337 11:16:11.074118 [0] MIN Duty = 4844%(X100), DQS PI = 20
2338 11:16:11.077516 [0] AVG Duty = 4906%(X100)
2339 11:16:11.077925
2340 11:16:11.081481 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2341 11:16:11.081891
2342 11:16:11.084022 CH0 DQM 1 Duty spec in!! Max-Min= 125%
2343 11:16:11.087887 [DutyScan_Calibration_Flow] ====Done====
2344 11:16:11.088336
2345 11:16:11.090653 [DutyScan_Calibration_Flow] k_type=2
2346 11:16:11.107511
2347 11:16:11.107916 ==DQ 0 ==
2348 11:16:11.110759 Final DQ duty delay cell = 0
2349 11:16:11.114326 [0] MAX Duty = 5125%(X100), DQS PI = 18
2350 11:16:11.117734 [0] MIN Duty = 5000%(X100), DQS PI = 8
2351 11:16:11.118161 [0] AVG Duty = 5062%(X100)
2352 11:16:11.118499
2353 11:16:11.120838 ==DQ 1 ==
2354 11:16:11.124323 Final DQ duty delay cell = 0
2355 11:16:11.127211 [0] MAX Duty = 5125%(X100), DQS PI = 4
2356 11:16:11.130701 [0] MIN Duty = 4938%(X100), DQS PI = 14
2357 11:16:11.131122 [0] AVG Duty = 5031%(X100)
2358 11:16:11.131460
2359 11:16:11.133937 CH0 DQ 0 Duty spec in!! Max-Min= 125%
2360 11:16:11.137277
2361 11:16:11.140362 CH0 DQ 1 Duty spec in!! Max-Min= 187%
2362 11:16:11.143821 [DutyScan_Calibration_Flow] ====Done====
2363 11:16:11.144291 ==
2364 11:16:11.147522 Dram Type= 6, Freq= 0, CH_1, rank 0
2365 11:16:11.150337 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2366 11:16:11.150758 ==
2367 11:16:11.153605 [Duty_Offset_Calibration]
2368 11:16:11.154021 B0:0 B1:-1 CA:3
2369 11:16:11.154357
2370 11:16:11.157914 [DutyScan_Calibration_Flow] k_type=0
2371 11:16:11.166572
2372 11:16:11.167056 ==CLK 0==
2373 11:16:11.169640 Final CLK duty delay cell = -4
2374 11:16:11.173109 [-4] MAX Duty = 5000%(X100), DQS PI = 0
2375 11:16:11.176956 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2376 11:16:11.179619 [-4] AVG Duty = 4938%(X100)
2377 11:16:11.180061
2378 11:16:11.183192 CH1 CLK Duty spec in!! Max-Min= 124%
2379 11:16:11.186498 [DutyScan_Calibration_Flow] ====Done====
2380 11:16:11.186913
2381 11:16:11.189832 [DutyScan_Calibration_Flow] k_type=1
2382 11:16:11.205971
2383 11:16:11.206380 ==DQS 0 ==
2384 11:16:11.209147 Final DQS duty delay cell = 0
2385 11:16:11.212498 [0] MAX Duty = 5187%(X100), DQS PI = 18
2386 11:16:11.216074 [0] MIN Duty = 4907%(X100), DQS PI = 38
2387 11:16:11.219288 [0] AVG Duty = 5047%(X100)
2388 11:16:11.219805
2389 11:16:11.220182 ==DQS 1 ==
2390 11:16:11.222638 Final DQS duty delay cell = 0
2391 11:16:11.225691 [0] MAX Duty = 5156%(X100), DQS PI = 8
2392 11:16:11.228646 [0] MIN Duty = 5000%(X100), DQS PI = 26
2393 11:16:11.231898 [0] AVG Duty = 5078%(X100)
2394 11:16:11.232003
2395 11:16:11.235980 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2396 11:16:11.236440
2397 11:16:11.238939 CH1 DQS 1 Duty spec in!! Max-Min= 156%
2398 11:16:11.243049 [DutyScan_Calibration_Flow] ====Done====
2399 11:16:11.243589
2400 11:16:11.245690 [DutyScan_Calibration_Flow] k_type=3
2401 11:16:11.262675
2402 11:16:11.262755 ==DQM 0 ==
2403 11:16:11.265802 Final DQM duty delay cell = 0
2404 11:16:11.268759 [0] MAX Duty = 5031%(X100), DQS PI = 28
2405 11:16:11.272294 [0] MIN Duty = 4813%(X100), DQS PI = 38
2406 11:16:11.275520 [0] AVG Duty = 4922%(X100)
2407 11:16:11.275600
2408 11:16:11.275664 ==DQM 1 ==
2409 11:16:11.278799 Final DQM duty delay cell = 0
2410 11:16:11.281882 [0] MAX Duty = 5000%(X100), DQS PI = 34
2411 11:16:11.285259 [0] MIN Duty = 4844%(X100), DQS PI = 0
2412 11:16:11.288747 [0] AVG Duty = 4922%(X100)
2413 11:16:11.288827
2414 11:16:11.291916 CH1 DQM 0 Duty spec in!! Max-Min= 218%
2415 11:16:11.292045
2416 11:16:11.295335 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2417 11:16:11.298608 [DutyScan_Calibration_Flow] ====Done====
2418 11:16:11.298689
2419 11:16:11.301804 [DutyScan_Calibration_Flow] k_type=2
2420 11:16:11.317882
2421 11:16:11.318063 ==DQ 0 ==
2422 11:16:11.321251 Final DQ duty delay cell = -4
2423 11:16:11.324413 [-4] MAX Duty = 5000%(X100), DQS PI = 6
2424 11:16:11.327978 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2425 11:16:11.331531 [-4] AVG Duty = 4922%(X100)
2426 11:16:11.331611
2427 11:16:11.331676 ==DQ 1 ==
2428 11:16:11.334499 Final DQ duty delay cell = 0
2429 11:16:11.337823 [0] MAX Duty = 5031%(X100), DQS PI = 32
2430 11:16:11.341045 [0] MIN Duty = 4844%(X100), DQS PI = 62
2431 11:16:11.344520 [0] AVG Duty = 4937%(X100)
2432 11:16:11.344601
2433 11:16:11.347676 CH1 DQ 0 Duty spec in!! Max-Min= 156%
2434 11:16:11.347756
2435 11:16:11.351220 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2436 11:16:11.354128 [DutyScan_Calibration_Flow] ====Done====
2437 11:16:11.358055 nWR fixed to 30
2438 11:16:11.361051 [ModeRegInit_LP4] CH0 RK0
2439 11:16:11.361137 [ModeRegInit_LP4] CH0 RK1
2440 11:16:11.365235 [ModeRegInit_LP4] CH1 RK0
2441 11:16:11.367673 [ModeRegInit_LP4] CH1 RK1
2442 11:16:11.367810 match AC timing 7
2443 11:16:11.373828 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2444 11:16:11.377336 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2445 11:16:11.380853 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2446 11:16:11.387655 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2447 11:16:11.390548 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2448 11:16:11.390629 ==
2449 11:16:11.393877 Dram Type= 6, Freq= 0, CH_0, rank 0
2450 11:16:11.397809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2451 11:16:11.397891 ==
2452 11:16:11.403921 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2453 11:16:11.410835 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2454 11:16:11.418616 [CA 0] Center 39 (9~70) winsize 62
2455 11:16:11.421825 [CA 1] Center 39 (9~70) winsize 62
2456 11:16:11.425442 [CA 2] Center 35 (5~66) winsize 62
2457 11:16:11.428412 [CA 3] Center 35 (5~66) winsize 62
2458 11:16:11.431986 [CA 4] Center 33 (3~64) winsize 62
2459 11:16:11.434751 [CA 5] Center 33 (3~63) winsize 61
2460 11:16:11.435191
2461 11:16:11.438858 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2462 11:16:11.439275
2463 11:16:11.441688 [CATrainingPosCal] consider 1 rank data
2464 11:16:11.445262 u2DelayCellTimex100 = 270/100 ps
2465 11:16:11.448886 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2466 11:16:11.454783 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2467 11:16:11.458470 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2468 11:16:11.461506 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2469 11:16:11.464773 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2470 11:16:11.468482 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2471 11:16:11.468564
2472 11:16:11.471011 CA PerBit enable=1, Macro0, CA PI delay=33
2473 11:16:11.471093
2474 11:16:11.474858 [CBTSetCACLKResult] CA Dly = 33
2475 11:16:11.474941 CS Dly: 7 (0~38)
2476 11:16:11.477644 ==
2477 11:16:11.481477 Dram Type= 6, Freq= 0, CH_0, rank 1
2478 11:16:11.484295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2479 11:16:11.484442 ==
2480 11:16:11.488037 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2481 11:16:11.494081 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2482 11:16:11.504617 [CA 0] Center 39 (9~70) winsize 62
2483 11:16:11.507096 [CA 1] Center 39 (9~70) winsize 62
2484 11:16:11.510809 [CA 2] Center 35 (5~66) winsize 62
2485 11:16:11.514407 [CA 3] Center 35 (5~66) winsize 62
2486 11:16:11.517025 [CA 4] Center 34 (4~65) winsize 62
2487 11:16:11.520557 [CA 5] Center 33 (3~64) winsize 62
2488 11:16:11.520641
2489 11:16:11.523823 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2490 11:16:11.523906
2491 11:16:11.527091 [CATrainingPosCal] consider 2 rank data
2492 11:16:11.530548 u2DelayCellTimex100 = 270/100 ps
2493 11:16:11.533891 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2494 11:16:11.540397 CA1 delay=39 (9~70),Diff = 6 PI (28 cell)
2495 11:16:11.544027 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2496 11:16:11.547821 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2497 11:16:11.550312 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2498 11:16:11.554137 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2499 11:16:11.554335
2500 11:16:11.557148 CA PerBit enable=1, Macro0, CA PI delay=33
2501 11:16:11.557355
2502 11:16:11.560756 [CBTSetCACLKResult] CA Dly = 33
2503 11:16:11.561031 CS Dly: 8 (0~41)
2504 11:16:11.561229
2505 11:16:11.563808 ----->DramcWriteLeveling(PI) begin...
2506 11:16:11.567114 ==
2507 11:16:11.570586 Dram Type= 6, Freq= 0, CH_0, rank 0
2508 11:16:11.573938 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2509 11:16:11.574267 ==
2510 11:16:11.577422 Write leveling (Byte 0): 31 => 31
2511 11:16:11.581409 Write leveling (Byte 1): 26 => 26
2512 11:16:11.583978 DramcWriteLeveling(PI) end<-----
2513 11:16:11.584415
2514 11:16:11.584726 ==
2515 11:16:11.587376 Dram Type= 6, Freq= 0, CH_0, rank 0
2516 11:16:11.590873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2517 11:16:11.591399 ==
2518 11:16:11.594074 [Gating] SW mode calibration
2519 11:16:11.600528 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2520 11:16:11.607319 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2521 11:16:11.611261 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2522 11:16:11.613744 0 15 4 | B1->B0 | 2c2c 3434 | 1 1 | (0 0) (1 1)
2523 11:16:11.620536 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2524 11:16:11.623819 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2525 11:16:11.627264 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2526 11:16:11.633596 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2527 11:16:11.637454 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2528 11:16:11.640665 0 15 28 | B1->B0 | 3434 2a2a | 1 1 | (1 1) (1 0)
2529 11:16:11.647402 1 0 0 | B1->B0 | 3434 2323 | 0 0 | (0 1) (0 0)
2530 11:16:11.650202 1 0 4 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
2531 11:16:11.653698 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2532 11:16:11.659948 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2533 11:16:11.663211 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2534 11:16:11.666626 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2535 11:16:11.673064 1 0 24 | B1->B0 | 2323 2726 | 0 1 | (0 0) (0 0)
2536 11:16:11.677035 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2537 11:16:11.679950 1 1 0 | B1->B0 | 2b2b 4646 | 0 0 | (0 0) (0 0)
2538 11:16:11.686997 1 1 4 | B1->B0 | 4343 4646 | 0 0 | (0 0) (0 0)
2539 11:16:11.689799 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2540 11:16:11.693226 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2541 11:16:11.699550 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2542 11:16:11.703084 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2543 11:16:11.706952 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2544 11:16:11.709928 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2545 11:16:11.716006 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2546 11:16:11.719390 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2547 11:16:11.722899 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2548 11:16:11.729787 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2549 11:16:11.732781 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2550 11:16:11.736644 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2551 11:16:11.742540 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2552 11:16:11.745990 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2553 11:16:11.750183 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2554 11:16:11.756557 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2555 11:16:11.759607 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2556 11:16:11.762775 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2557 11:16:11.769163 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2558 11:16:11.772642 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2559 11:16:11.776262 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2560 11:16:11.783094 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2561 11:16:11.786137 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2562 11:16:11.789465 Total UI for P1: 0, mck2ui 16
2563 11:16:11.793181 best dqsien dly found for B0: ( 1, 3, 26)
2564 11:16:11.796199 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2565 11:16:11.799074 Total UI for P1: 0, mck2ui 16
2566 11:16:11.802456 best dqsien dly found for B1: ( 1, 4, 0)
2567 11:16:11.805896 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2568 11:16:11.809555 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2569 11:16:11.810123
2570 11:16:11.815640 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2571 11:16:11.819194 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2572 11:16:11.819655 [Gating] SW calibration Done
2573 11:16:11.822103 ==
2574 11:16:11.826344 Dram Type= 6, Freq= 0, CH_0, rank 0
2575 11:16:11.829112 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2576 11:16:11.829670 ==
2577 11:16:11.830043 RX Vref Scan: 0
2578 11:16:11.830386
2579 11:16:11.832517 RX Vref 0 -> 0, step: 1
2580 11:16:11.832977
2581 11:16:11.835743 RX Delay -40 -> 252, step: 8
2582 11:16:11.839577 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2583 11:16:11.842758 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2584 11:16:11.845666 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2585 11:16:11.852237 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2586 11:16:11.855876 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2587 11:16:11.858867 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2588 11:16:11.862291 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2589 11:16:11.865593 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2590 11:16:11.872728 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2591 11:16:11.876136 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2592 11:16:11.879061 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2593 11:16:11.882003 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2594 11:16:11.885363 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2595 11:16:11.892430 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2596 11:16:11.894993 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2597 11:16:11.898430 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2598 11:16:11.898598 ==
2599 11:16:11.901719 Dram Type= 6, Freq= 0, CH_0, rank 0
2600 11:16:11.905384 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2601 11:16:11.908525 ==
2602 11:16:11.908712 DQS Delay:
2603 11:16:11.908810 DQS0 = 0, DQS1 = 0
2604 11:16:11.911907 DQM Delay:
2605 11:16:11.912125 DQM0 = 118, DQM1 = 107
2606 11:16:11.915068 DQ Delay:
2607 11:16:11.918150 DQ0 =115, DQ1 =119, DQ2 =119, DQ3 =111
2608 11:16:11.921637 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =127
2609 11:16:11.925106 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2610 11:16:11.928416 DQ12 =119, DQ13 =111, DQ14 =119, DQ15 =111
2611 11:16:11.928622
2612 11:16:11.928753
2613 11:16:11.928876 ==
2614 11:16:11.931535 Dram Type= 6, Freq= 0, CH_0, rank 0
2615 11:16:11.934887 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2616 11:16:11.935308 ==
2617 11:16:11.935641
2618 11:16:11.938026
2619 11:16:11.938381 TX Vref Scan disable
2620 11:16:11.941480 == TX Byte 0 ==
2621 11:16:11.944783 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2622 11:16:11.947930 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2623 11:16:11.951589 == TX Byte 1 ==
2624 11:16:11.955184 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2625 11:16:11.958158 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2626 11:16:11.958580 ==
2627 11:16:11.961782 Dram Type= 6, Freq= 0, CH_0, rank 0
2628 11:16:11.968287 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2629 11:16:11.968860 ==
2630 11:16:11.979216 TX Vref=22, minBit 5, minWin=25, winSum=411
2631 11:16:11.982422 TX Vref=24, minBit 8, minWin=25, winSum=419
2632 11:16:11.985850 TX Vref=26, minBit 4, minWin=26, winSum=425
2633 11:16:11.989384 TX Vref=28, minBit 1, minWin=26, winSum=430
2634 11:16:11.992604 TX Vref=30, minBit 15, minWin=25, winSum=429
2635 11:16:11.998962 TX Vref=32, minBit 5, minWin=26, winSum=432
2636 11:16:12.002335 [TxChooseVref] Worse bit 5, Min win 26, Win sum 432, Final Vref 32
2637 11:16:12.002905
2638 11:16:12.006003 Final TX Range 1 Vref 32
2639 11:16:12.006574
2640 11:16:12.006944 ==
2641 11:16:12.009044 Dram Type= 6, Freq= 0, CH_0, rank 0
2642 11:16:12.012330 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2643 11:16:12.015241 ==
2644 11:16:12.015713
2645 11:16:12.016131
2646 11:16:12.016488 TX Vref Scan disable
2647 11:16:12.018843 == TX Byte 0 ==
2648 11:16:12.022181 Update DQ dly =850 (3 ,2, 18) DQ OEN =(2 ,7)
2649 11:16:12.028833 Update DQM dly =850 (3 ,2, 18) DQM OEN =(2 ,7)
2650 11:16:12.029297 == TX Byte 1 ==
2651 11:16:12.032192 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2652 11:16:12.038829 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2653 11:16:12.039398
2654 11:16:12.039764 [DATLAT]
2655 11:16:12.040157 Freq=1200, CH0 RK0
2656 11:16:12.040507
2657 11:16:12.042093 DATLAT Default: 0xd
2658 11:16:12.042552 0, 0xFFFF, sum = 0
2659 11:16:12.045787 1, 0xFFFF, sum = 0
2660 11:16:12.048588 2, 0xFFFF, sum = 0
2661 11:16:12.049064 3, 0xFFFF, sum = 0
2662 11:16:12.051767 4, 0xFFFF, sum = 0
2663 11:16:12.052299 5, 0xFFFF, sum = 0
2664 11:16:12.055597 6, 0xFFFF, sum = 0
2665 11:16:12.056177 7, 0xFFFF, sum = 0
2666 11:16:12.058384 8, 0xFFFF, sum = 0
2667 11:16:12.058806 9, 0xFFFF, sum = 0
2668 11:16:12.061975 10, 0xFFFF, sum = 0
2669 11:16:12.062400 11, 0xFFFF, sum = 0
2670 11:16:12.065803 12, 0x0, sum = 1
2671 11:16:12.066335 13, 0x0, sum = 2
2672 11:16:12.068507 14, 0x0, sum = 3
2673 11:16:12.068933 15, 0x0, sum = 4
2674 11:16:12.071763 best_step = 13
2675 11:16:12.072215
2676 11:16:12.072550 ==
2677 11:16:12.075889 Dram Type= 6, Freq= 0, CH_0, rank 0
2678 11:16:12.078151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2679 11:16:12.078577 ==
2680 11:16:12.078909 RX Vref Scan: 1
2681 11:16:12.082314
2682 11:16:12.082846 Set Vref Range= 32 -> 127
2683 11:16:12.083193
2684 11:16:12.085190 RX Vref 32 -> 127, step: 1
2685 11:16:12.085712
2686 11:16:12.088191 RX Delay -21 -> 252, step: 4
2687 11:16:12.088611
2688 11:16:12.091900 Set Vref, RX VrefLevel [Byte0]: 32
2689 11:16:12.095171 [Byte1]: 32
2690 11:16:12.095591
2691 11:16:12.098437 Set Vref, RX VrefLevel [Byte0]: 33
2692 11:16:12.102270 [Byte1]: 33
2693 11:16:12.105648
2694 11:16:12.106168 Set Vref, RX VrefLevel [Byte0]: 34
2695 11:16:12.108922 [Byte1]: 34
2696 11:16:12.113343
2697 11:16:12.113881 Set Vref, RX VrefLevel [Byte0]: 35
2698 11:16:12.116612 [Byte1]: 35
2699 11:16:12.121509
2700 11:16:12.122184 Set Vref, RX VrefLevel [Byte0]: 36
2701 11:16:12.124681 [Byte1]: 36
2702 11:16:12.129217
2703 11:16:12.129739 Set Vref, RX VrefLevel [Byte0]: 37
2704 11:16:12.132591 [Byte1]: 37
2705 11:16:12.137250
2706 11:16:12.137769 Set Vref, RX VrefLevel [Byte0]: 38
2707 11:16:12.140591 [Byte1]: 38
2708 11:16:12.144907
2709 11:16:12.145441 Set Vref, RX VrefLevel [Byte0]: 39
2710 11:16:12.148549 [Byte1]: 39
2711 11:16:12.152715
2712 11:16:12.153136 Set Vref, RX VrefLevel [Byte0]: 40
2713 11:16:12.156221 [Byte1]: 40
2714 11:16:12.161212
2715 11:16:12.161735 Set Vref, RX VrefLevel [Byte0]: 41
2716 11:16:12.164593 [Byte1]: 41
2717 11:16:12.169238
2718 11:16:12.169764 Set Vref, RX VrefLevel [Byte0]: 42
2719 11:16:12.171801 [Byte1]: 42
2720 11:16:12.177099
2721 11:16:12.177624 Set Vref, RX VrefLevel [Byte0]: 43
2722 11:16:12.180107 [Byte1]: 43
2723 11:16:12.184594
2724 11:16:12.185010 Set Vref, RX VrefLevel [Byte0]: 44
2725 11:16:12.188120 [Byte1]: 44
2726 11:16:12.192881
2727 11:16:12.193348 Set Vref, RX VrefLevel [Byte0]: 45
2728 11:16:12.195867 [Byte1]: 45
2729 11:16:12.201208
2730 11:16:12.201770 Set Vref, RX VrefLevel [Byte0]: 46
2731 11:16:12.204089 [Byte1]: 46
2732 11:16:12.208552
2733 11:16:12.209118 Set Vref, RX VrefLevel [Byte0]: 47
2734 11:16:12.212267 [Byte1]: 47
2735 11:16:12.216690
2736 11:16:12.217255 Set Vref, RX VrefLevel [Byte0]: 48
2737 11:16:12.219714 [Byte1]: 48
2738 11:16:12.224709
2739 11:16:12.225175 Set Vref, RX VrefLevel [Byte0]: 49
2740 11:16:12.227898 [Byte1]: 49
2741 11:16:12.232735
2742 11:16:12.233298 Set Vref, RX VrefLevel [Byte0]: 50
2743 11:16:12.236171 [Byte1]: 50
2744 11:16:12.240298
2745 11:16:12.240856 Set Vref, RX VrefLevel [Byte0]: 51
2746 11:16:12.243821 [Byte1]: 51
2747 11:16:12.248441
2748 11:16:12.249012 Set Vref, RX VrefLevel [Byte0]: 52
2749 11:16:12.251403 [Byte1]: 52
2750 11:16:12.256131
2751 11:16:12.256703 Set Vref, RX VrefLevel [Byte0]: 53
2752 11:16:12.259316 [Byte1]: 53
2753 11:16:12.264169
2754 11:16:12.264725 Set Vref, RX VrefLevel [Byte0]: 54
2755 11:16:12.267155 [Byte1]: 54
2756 11:16:12.272007
2757 11:16:12.272495 Set Vref, RX VrefLevel [Byte0]: 55
2758 11:16:12.275736 [Byte1]: 55
2759 11:16:12.279595
2760 11:16:12.280114 Set Vref, RX VrefLevel [Byte0]: 56
2761 11:16:12.283613 [Byte1]: 56
2762 11:16:12.287789
2763 11:16:12.288306 Set Vref, RX VrefLevel [Byte0]: 57
2764 11:16:12.291351 [Byte1]: 57
2765 11:16:12.295950
2766 11:16:12.296564 Set Vref, RX VrefLevel [Byte0]: 58
2767 11:16:12.299229 [Byte1]: 58
2768 11:16:12.303541
2769 11:16:12.304159 Set Vref, RX VrefLevel [Byte0]: 59
2770 11:16:12.306936 [Byte1]: 59
2771 11:16:12.311640
2772 11:16:12.312239 Set Vref, RX VrefLevel [Byte0]: 60
2773 11:16:12.315155 [Byte1]: 60
2774 11:16:12.319573
2775 11:16:12.320186 Set Vref, RX VrefLevel [Byte0]: 61
2776 11:16:12.322693 [Byte1]: 61
2777 11:16:12.327141
2778 11:16:12.327707 Set Vref, RX VrefLevel [Byte0]: 62
2779 11:16:12.330793 [Byte1]: 62
2780 11:16:12.335800
2781 11:16:12.336414 Set Vref, RX VrefLevel [Byte0]: 63
2782 11:16:12.339384 [Byte1]: 63
2783 11:16:12.343469
2784 11:16:12.344068 Set Vref, RX VrefLevel [Byte0]: 64
2785 11:16:12.346730 [Byte1]: 64
2786 11:16:12.351063
2787 11:16:12.351541 Set Vref, RX VrefLevel [Byte0]: 65
2788 11:16:12.354455 [Byte1]: 65
2789 11:16:12.358686
2790 11:16:12.359163 Set Vref, RX VrefLevel [Byte0]: 66
2791 11:16:12.362401 [Byte1]: 66
2792 11:16:12.366725
2793 11:16:12.367326 Set Vref, RX VrefLevel [Byte0]: 67
2794 11:16:12.370065 [Byte1]: 67
2795 11:16:12.375001
2796 11:16:12.375468 Set Vref, RX VrefLevel [Byte0]: 68
2797 11:16:12.378200 [Byte1]: 68
2798 11:16:12.382832
2799 11:16:12.383395 Final RX Vref Byte 0 = 51 to rank0
2800 11:16:12.386331 Final RX Vref Byte 1 = 53 to rank0
2801 11:16:12.389331 Final RX Vref Byte 0 = 51 to rank1
2802 11:16:12.392775 Final RX Vref Byte 1 = 53 to rank1==
2803 11:16:12.395885 Dram Type= 6, Freq= 0, CH_0, rank 0
2804 11:16:12.403042 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2805 11:16:12.403613 ==
2806 11:16:12.403986 DQS Delay:
2807 11:16:12.406119 DQS0 = 0, DQS1 = 0
2808 11:16:12.406683 DQM Delay:
2809 11:16:12.407055 DQM0 = 117, DQM1 = 105
2810 11:16:12.409565 DQ Delay:
2811 11:16:12.412451 DQ0 =118, DQ1 =116, DQ2 =114, DQ3 =114
2812 11:16:12.415981 DQ4 =118, DQ5 =110, DQ6 =124, DQ7 =122
2813 11:16:12.419289 DQ8 =94, DQ9 =88, DQ10 =106, DQ11 =100
2814 11:16:12.422639 DQ12 =114, DQ13 =110, DQ14 =116, DQ15 =112
2815 11:16:12.423203
2816 11:16:12.423790
2817 11:16:12.432982 [DQSOSCAuto] RK0, (LSB)MR18= 0xfdf9, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 411 ps
2818 11:16:12.433555 CH0 RK0: MR19=303, MR18=FDF9
2819 11:16:12.439531 CH0_RK0: MR19=0x303, MR18=0xFDF9, DQSOSC=411, MR23=63, INC=38, DEC=25
2820 11:16:12.440143
2821 11:16:12.442470 ----->DramcWriteLeveling(PI) begin...
2822 11:16:12.443038 ==
2823 11:16:12.446212 Dram Type= 6, Freq= 0, CH_0, rank 1
2824 11:16:12.452294 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2825 11:16:12.452895 ==
2826 11:16:12.455629 Write leveling (Byte 0): 32 => 32
2827 11:16:12.458720 Write leveling (Byte 1): 25 => 25
2828 11:16:12.459258 DramcWriteLeveling(PI) end<-----
2829 11:16:12.459635
2830 11:16:12.462224 ==
2831 11:16:12.465596 Dram Type= 6, Freq= 0, CH_0, rank 1
2832 11:16:12.468404 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2833 11:16:12.468975 ==
2834 11:16:12.471504 [Gating] SW mode calibration
2835 11:16:12.478637 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2836 11:16:12.481708 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2837 11:16:12.488466 0 15 0 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
2838 11:16:12.491951 0 15 4 | B1->B0 | 3232 3434 | 1 1 | (1 1) (1 1)
2839 11:16:12.494816 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2840 11:16:12.501845 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2841 11:16:12.505540 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2842 11:16:12.508477 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2843 11:16:12.515348 0 15 24 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
2844 11:16:12.518214 0 15 28 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
2845 11:16:12.521463 1 0 0 | B1->B0 | 2f2f 2323 | 0 0 | (1 0) (0 0)
2846 11:16:12.528426 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2847 11:16:12.532416 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2848 11:16:12.535036 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2849 11:16:12.541732 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2850 11:16:12.545068 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2851 11:16:12.548195 1 0 24 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
2852 11:16:12.554846 1 0 28 | B1->B0 | 2828 4444 | 0 0 | (0 0) (0 0)
2853 11:16:12.557983 1 1 0 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
2854 11:16:12.561172 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2855 11:16:12.567729 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2856 11:16:12.571323 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2857 11:16:12.573951 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2858 11:16:12.580627 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2859 11:16:12.584539 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2860 11:16:12.587413 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2861 11:16:12.593917 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2862 11:16:12.597103 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2863 11:16:12.600376 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2864 11:16:12.607783 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2865 11:16:12.610924 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2866 11:16:12.613788 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2867 11:16:12.620945 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2868 11:16:12.623818 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2869 11:16:12.627006 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2870 11:16:12.634062 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2871 11:16:12.636870 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2872 11:16:12.640566 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2873 11:16:12.647213 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2874 11:16:12.650598 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2875 11:16:12.653517 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2876 11:16:12.660563 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
2877 11:16:12.660981 Total UI for P1: 0, mck2ui 16
2878 11:16:12.667348 best dqsien dly found for B0: ( 1, 3, 24)
2879 11:16:12.670135 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2880 11:16:12.673619 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2881 11:16:12.676955 Total UI for P1: 0, mck2ui 16
2882 11:16:12.680015 best dqsien dly found for B1: ( 1, 4, 0)
2883 11:16:12.683690 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2884 11:16:12.687061 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2885 11:16:12.687473
2886 11:16:12.690276 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2887 11:16:12.696516 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2888 11:16:12.696932 [Gating] SW calibration Done
2889 11:16:12.697263 ==
2890 11:16:12.700439 Dram Type= 6, Freq= 0, CH_0, rank 1
2891 11:16:12.707121 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2892 11:16:12.707632 ==
2893 11:16:12.707986 RX Vref Scan: 0
2894 11:16:12.708350
2895 11:16:12.710355 RX Vref 0 -> 0, step: 1
2896 11:16:12.710916
2897 11:16:12.713338 RX Delay -40 -> 252, step: 8
2898 11:16:12.716439 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2899 11:16:12.720108 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2900 11:16:12.723314 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
2901 11:16:12.730285 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
2902 11:16:12.733458 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2903 11:16:12.736887 iDelay=200, Bit 5, Center 103 (32 ~ 175) 144
2904 11:16:12.739749 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2905 11:16:12.743479 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2906 11:16:12.749963 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2907 11:16:12.753043 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2908 11:16:12.756893 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2909 11:16:12.759457 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2910 11:16:12.763338 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2911 11:16:12.769590 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2912 11:16:12.772725 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2913 11:16:12.776217 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2914 11:16:12.776776 ==
2915 11:16:12.780436 Dram Type= 6, Freq= 0, CH_0, rank 1
2916 11:16:12.783137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2917 11:16:12.783665 ==
2918 11:16:12.786538 DQS Delay:
2919 11:16:12.787058 DQS0 = 0, DQS1 = 0
2920 11:16:12.789914 DQM Delay:
2921 11:16:12.790430 DQM0 = 116, DQM1 = 108
2922 11:16:12.790768 DQ Delay:
2923 11:16:12.793073 DQ0 =111, DQ1 =119, DQ2 =111, DQ3 =115
2924 11:16:12.799781 DQ4 =119, DQ5 =103, DQ6 =127, DQ7 =123
2925 11:16:12.802899 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
2926 11:16:12.807032 DQ12 =115, DQ13 =111, DQ14 =119, DQ15 =115
2927 11:16:12.807548
2928 11:16:12.807882
2929 11:16:12.808229 ==
2930 11:16:12.809536 Dram Type= 6, Freq= 0, CH_0, rank 1
2931 11:16:12.812874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2932 11:16:12.813297 ==
2933 11:16:12.813632
2934 11:16:12.813942
2935 11:16:12.816316 TX Vref Scan disable
2936 11:16:12.819574 == TX Byte 0 ==
2937 11:16:12.822734 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2938 11:16:12.826114 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2939 11:16:12.829292 == TX Byte 1 ==
2940 11:16:12.833297 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2941 11:16:12.835746 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2942 11:16:12.836208 ==
2943 11:16:12.839437 Dram Type= 6, Freq= 0, CH_0, rank 1
2944 11:16:12.843099 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2945 11:16:12.846163 ==
2946 11:16:12.856543 TX Vref=22, minBit 12, minWin=25, winSum=416
2947 11:16:12.859945 TX Vref=24, minBit 1, minWin=26, winSum=422
2948 11:16:12.863310 TX Vref=26, minBit 2, minWin=26, winSum=427
2949 11:16:12.866282 TX Vref=28, minBit 8, minWin=26, winSum=429
2950 11:16:12.869656 TX Vref=30, minBit 12, minWin=26, winSum=432
2951 11:16:12.876139 TX Vref=32, minBit 6, minWin=26, winSum=427
2952 11:16:12.879815 [TxChooseVref] Worse bit 12, Min win 26, Win sum 432, Final Vref 30
2953 11:16:12.880260
2954 11:16:12.883189 Final TX Range 1 Vref 30
2955 11:16:12.883605
2956 11:16:12.883931 ==
2957 11:16:12.886314 Dram Type= 6, Freq= 0, CH_0, rank 1
2958 11:16:12.889868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2959 11:16:12.893124 ==
2960 11:16:12.893674
2961 11:16:12.894053
2962 11:16:12.894363 TX Vref Scan disable
2963 11:16:12.896545 == TX Byte 0 ==
2964 11:16:12.900226 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2965 11:16:12.906558 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2966 11:16:12.907072 == TX Byte 1 ==
2967 11:16:12.910262 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
2968 11:16:12.913359 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
2969 11:16:12.916465
2970 11:16:12.916877 [DATLAT]
2971 11:16:12.917203 Freq=1200, CH0 RK1
2972 11:16:12.917609
2973 11:16:12.920447 DATLAT Default: 0xd
2974 11:16:12.920960 0, 0xFFFF, sum = 0
2975 11:16:12.923796 1, 0xFFFF, sum = 0
2976 11:16:12.924353 2, 0xFFFF, sum = 0
2977 11:16:12.926515 3, 0xFFFF, sum = 0
2978 11:16:12.930399 4, 0xFFFF, sum = 0
2979 11:16:12.930923 5, 0xFFFF, sum = 0
2980 11:16:12.933118 6, 0xFFFF, sum = 0
2981 11:16:12.933617 7, 0xFFFF, sum = 0
2982 11:16:12.937151 8, 0xFFFF, sum = 0
2983 11:16:12.937730 9, 0xFFFF, sum = 0
2984 11:16:12.939915 10, 0xFFFF, sum = 0
2985 11:16:12.940392 11, 0xFFFF, sum = 0
2986 11:16:12.943200 12, 0x0, sum = 1
2987 11:16:12.943777 13, 0x0, sum = 2
2988 11:16:12.946695 14, 0x0, sum = 3
2989 11:16:12.947215 15, 0x0, sum = 4
2990 11:16:12.947560 best_step = 13
2991 11:16:12.949902
2992 11:16:12.950322 ==
2993 11:16:12.953021 Dram Type= 6, Freq= 0, CH_0, rank 1
2994 11:16:12.956992 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2995 11:16:12.957511 ==
2996 11:16:12.957846 RX Vref Scan: 0
2997 11:16:12.958153
2998 11:16:12.959861 RX Vref 0 -> 0, step: 1
2999 11:16:12.960528
3000 11:16:12.963271 RX Delay -21 -> 252, step: 4
3001 11:16:12.966806 iDelay=195, Bit 0, Center 114 (51 ~ 178) 128
3002 11:16:12.973758 iDelay=195, Bit 1, Center 116 (47 ~ 186) 140
3003 11:16:12.976342 iDelay=195, Bit 2, Center 110 (43 ~ 178) 136
3004 11:16:12.979829 iDelay=195, Bit 3, Center 112 (47 ~ 178) 132
3005 11:16:12.982939 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3006 11:16:12.986977 iDelay=195, Bit 5, Center 108 (43 ~ 174) 132
3007 11:16:12.992967 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3008 11:16:12.996269 iDelay=195, Bit 7, Center 122 (55 ~ 190) 136
3009 11:16:12.999885 iDelay=195, Bit 8, Center 94 (27 ~ 162) 136
3010 11:16:13.003169 iDelay=195, Bit 9, Center 92 (23 ~ 162) 140
3011 11:16:13.006623 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3012 11:16:13.012920 iDelay=195, Bit 11, Center 98 (31 ~ 166) 136
3013 11:16:13.016364 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3014 11:16:13.019636 iDelay=195, Bit 13, Center 110 (43 ~ 178) 136
3015 11:16:13.023900 iDelay=195, Bit 14, Center 120 (55 ~ 186) 132
3016 11:16:13.026255 iDelay=195, Bit 15, Center 114 (47 ~ 182) 136
3017 11:16:13.029554 ==
3018 11:16:13.032426 Dram Type= 6, Freq= 0, CH_0, rank 1
3019 11:16:13.036410 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3020 11:16:13.036990 ==
3021 11:16:13.037347 DQS Delay:
3022 11:16:13.039379 DQS0 = 0, DQS1 = 0
3023 11:16:13.039798 DQM Delay:
3024 11:16:13.042613 DQM0 = 115, DQM1 = 106
3025 11:16:13.043037 DQ Delay:
3026 11:16:13.046015 DQ0 =114, DQ1 =116, DQ2 =110, DQ3 =112
3027 11:16:13.049219 DQ4 =118, DQ5 =108, DQ6 =126, DQ7 =122
3028 11:16:13.053008 DQ8 =94, DQ9 =92, DQ10 =110, DQ11 =98
3029 11:16:13.056012 DQ12 =112, DQ13 =110, DQ14 =120, DQ15 =114
3030 11:16:13.056471
3031 11:16:13.056808
3032 11:16:13.065594 [DQSOSCAuto] RK1, (LSB)MR18= 0xfd, (MSB)MR19= 0x403, tDQSOscB0 = 411 ps tDQSOscB1 = 410 ps
3033 11:16:13.065904 CH0 RK1: MR19=403, MR18=FD
3034 11:16:13.072284 CH0_RK1: MR19=0x403, MR18=0xFD, DQSOSC=410, MR23=63, INC=39, DEC=26
3035 11:16:13.075230 [RxdqsGatingPostProcess] freq 1200
3036 11:16:13.082209 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3037 11:16:13.085337 best DQS0 dly(2T, 0.5T) = (0, 11)
3038 11:16:13.088794 best DQS1 dly(2T, 0.5T) = (0, 12)
3039 11:16:13.092389 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3040 11:16:13.095349 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3041 11:16:13.099005 best DQS0 dly(2T, 0.5T) = (0, 11)
3042 11:16:13.099111 best DQS1 dly(2T, 0.5T) = (0, 12)
3043 11:16:13.101632 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3044 11:16:13.105187 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3045 11:16:13.108606 Pre-setting of DQS Precalculation
3046 11:16:13.115088 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3047 11:16:13.115172 ==
3048 11:16:13.118473 Dram Type= 6, Freq= 0, CH_1, rank 0
3049 11:16:13.122056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3050 11:16:13.122141 ==
3051 11:16:13.128299 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3052 11:16:13.134932 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3053 11:16:13.142178 [CA 0] Center 38 (8~68) winsize 61
3054 11:16:13.145543 [CA 1] Center 38 (8~68) winsize 61
3055 11:16:13.148636 [CA 2] Center 35 (6~65) winsize 60
3056 11:16:13.151835 [CA 3] Center 34 (4~64) winsize 61
3057 11:16:13.154956 [CA 4] Center 34 (4~65) winsize 62
3058 11:16:13.158663 [CA 5] Center 33 (3~63) winsize 61
3059 11:16:13.158753
3060 11:16:13.161560 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3061 11:16:13.161650
3062 11:16:13.165232 [CATrainingPosCal] consider 1 rank data
3063 11:16:13.168257 u2DelayCellTimex100 = 270/100 ps
3064 11:16:13.171540 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3065 11:16:13.178625 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3066 11:16:13.182292 CA2 delay=35 (6~65),Diff = 2 PI (9 cell)
3067 11:16:13.185125 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3068 11:16:13.188835 CA4 delay=34 (4~65),Diff = 1 PI (4 cell)
3069 11:16:13.191844 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3070 11:16:13.192087
3071 11:16:13.194900 CA PerBit enable=1, Macro0, CA PI delay=33
3072 11:16:13.195097
3073 11:16:13.198398 [CBTSetCACLKResult] CA Dly = 33
3074 11:16:13.201818 CS Dly: 5 (0~36)
3075 11:16:13.202089 ==
3076 11:16:13.204615 Dram Type= 6, Freq= 0, CH_1, rank 1
3077 11:16:13.208280 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3078 11:16:13.208588 ==
3079 11:16:13.215085 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3080 11:16:13.218465 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3081 11:16:13.228469 [CA 0] Center 37 (7~68) winsize 62
3082 11:16:13.231407 [CA 1] Center 38 (8~68) winsize 61
3083 11:16:13.234910 [CA 2] Center 34 (4~65) winsize 62
3084 11:16:13.238593 [CA 3] Center 33 (3~64) winsize 62
3085 11:16:13.241348 [CA 4] Center 34 (4~64) winsize 61
3086 11:16:13.244699 [CA 5] Center 33 (3~64) winsize 62
3087 11:16:13.245159
3088 11:16:13.247774 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3089 11:16:13.248225
3090 11:16:13.251452 [CATrainingPosCal] consider 2 rank data
3091 11:16:13.254208 u2DelayCellTimex100 = 270/100 ps
3092 11:16:13.257873 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3093 11:16:13.264272 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3094 11:16:13.267605 CA2 delay=35 (6~65),Diff = 2 PI (9 cell)
3095 11:16:13.271137 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3096 11:16:13.274129 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3097 11:16:13.277496 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
3098 11:16:13.278063
3099 11:16:13.280634 CA PerBit enable=1, Macro0, CA PI delay=33
3100 11:16:13.281204
3101 11:16:13.284132 [CBTSetCACLKResult] CA Dly = 33
3102 11:16:13.287905 CS Dly: 6 (0~39)
3103 11:16:13.288491
3104 11:16:13.290493 ----->DramcWriteLeveling(PI) begin...
3105 11:16:13.290922 ==
3106 11:16:13.294194 Dram Type= 6, Freq= 0, CH_1, rank 0
3107 11:16:13.297284 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3108 11:16:13.297725 ==
3109 11:16:13.300650 Write leveling (Byte 0): 26 => 26
3110 11:16:13.303812 Write leveling (Byte 1): 27 => 27
3111 11:16:13.307527 DramcWriteLeveling(PI) end<-----
3112 11:16:13.308084
3113 11:16:13.308429 ==
3114 11:16:13.310594 Dram Type= 6, Freq= 0, CH_1, rank 0
3115 11:16:13.313962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3116 11:16:13.314512 ==
3117 11:16:13.317406 [Gating] SW mode calibration
3118 11:16:13.323818 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3119 11:16:13.330708 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3120 11:16:13.333813 0 15 0 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
3121 11:16:13.337307 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3122 11:16:13.343603 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3123 11:16:13.346916 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3124 11:16:13.350219 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3125 11:16:13.357434 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3126 11:16:13.360353 0 15 24 | B1->B0 | 3434 3232 | 1 1 | (0 0) (1 0)
3127 11:16:13.363440 0 15 28 | B1->B0 | 3131 2828 | 0 1 | (0 0) (1 0)
3128 11:16:13.370520 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3129 11:16:13.373848 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3130 11:16:13.376756 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3131 11:16:13.383507 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3132 11:16:13.387247 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3133 11:16:13.389983 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3134 11:16:13.396511 1 0 24 | B1->B0 | 2525 2c2b | 0 1 | (1 1) (0 0)
3135 11:16:13.400574 1 0 28 | B1->B0 | 3939 4545 | 1 0 | (0 0) (0 0)
3136 11:16:13.404003 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3137 11:16:13.409877 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3138 11:16:13.413250 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3139 11:16:13.416651 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3140 11:16:13.423526 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3141 11:16:13.427697 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3142 11:16:13.429809 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3143 11:16:13.436556 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3144 11:16:13.439736 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3145 11:16:13.443332 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3146 11:16:13.449775 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3147 11:16:13.453533 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3148 11:16:13.456739 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3149 11:16:13.463240 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3150 11:16:13.466082 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3151 11:16:13.469317 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3152 11:16:13.472803 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3153 11:16:13.479590 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3154 11:16:13.482768 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3155 11:16:13.486219 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3156 11:16:13.492910 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3157 11:16:13.496156 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3158 11:16:13.499464 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3159 11:16:13.506012 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3160 11:16:13.508982 Total UI for P1: 0, mck2ui 16
3161 11:16:13.512972 best dqsien dly found for B0: ( 1, 3, 26)
3162 11:16:13.516577 Total UI for P1: 0, mck2ui 16
3163 11:16:13.519021 best dqsien dly found for B1: ( 1, 3, 26)
3164 11:16:13.523219 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3165 11:16:13.525961 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3166 11:16:13.526378
3167 11:16:13.529184 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3168 11:16:13.532464 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3169 11:16:13.535694 [Gating] SW calibration Done
3170 11:16:13.536294 ==
3171 11:16:13.539227 Dram Type= 6, Freq= 0, CH_1, rank 0
3172 11:16:13.542737 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3173 11:16:13.543303 ==
3174 11:16:13.546044 RX Vref Scan: 0
3175 11:16:13.546611
3176 11:16:13.546985 RX Vref 0 -> 0, step: 1
3177 11:16:13.547332
3178 11:16:13.549291 RX Delay -40 -> 252, step: 8
3179 11:16:13.555781 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3180 11:16:13.559517 iDelay=200, Bit 1, Center 107 (32 ~ 183) 152
3181 11:16:13.562841 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3182 11:16:13.565912 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3183 11:16:13.569259 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3184 11:16:13.572825 iDelay=200, Bit 5, Center 123 (48 ~ 199) 152
3185 11:16:13.579362 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3186 11:16:13.582126 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3187 11:16:13.585591 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3188 11:16:13.588638 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3189 11:16:13.592151 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3190 11:16:13.599179 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3191 11:16:13.601966 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
3192 11:16:13.606057 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3193 11:16:13.608744 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3194 11:16:13.615448 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3195 11:16:13.615963 ==
3196 11:16:13.618863 Dram Type= 6, Freq= 0, CH_1, rank 0
3197 11:16:13.622098 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3198 11:16:13.622620 ==
3199 11:16:13.622955 DQS Delay:
3200 11:16:13.625228 DQS0 = 0, DQS1 = 0
3201 11:16:13.625744 DQM Delay:
3202 11:16:13.629001 DQM0 = 114, DQM1 = 112
3203 11:16:13.629556 DQ Delay:
3204 11:16:13.632388 DQ0 =119, DQ1 =107, DQ2 =107, DQ3 =115
3205 11:16:13.635087 DQ4 =111, DQ5 =123, DQ6 =123, DQ7 =111
3206 11:16:13.639457 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3207 11:16:13.641593 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3208 11:16:13.642054
3209 11:16:13.645248
3210 11:16:13.645819 ==
3211 11:16:13.648959 Dram Type= 6, Freq= 0, CH_1, rank 0
3212 11:16:13.651901 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3213 11:16:13.652475 ==
3214 11:16:13.652821
3215 11:16:13.653133
3216 11:16:13.654997 TX Vref Scan disable
3217 11:16:13.655412 == TX Byte 0 ==
3218 11:16:13.658466 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3219 11:16:13.665150 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3220 11:16:13.665719 == TX Byte 1 ==
3221 11:16:13.671474 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3222 11:16:13.675016 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3223 11:16:13.675532 ==
3224 11:16:13.678662 Dram Type= 6, Freq= 0, CH_1, rank 0
3225 11:16:13.681289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3226 11:16:13.681708 ==
3227 11:16:13.693554 TX Vref=22, minBit 9, minWin=24, winSum=411
3228 11:16:13.696566 TX Vref=24, minBit 3, minWin=25, winSum=418
3229 11:16:13.700298 TX Vref=26, minBit 9, minWin=25, winSum=425
3230 11:16:13.703337 TX Vref=28, minBit 1, minWin=25, winSum=424
3231 11:16:13.706644 TX Vref=30, minBit 0, minWin=26, winSum=427
3232 11:16:13.709880 TX Vref=32, minBit 9, minWin=25, winSum=424
3233 11:16:13.717122 [TxChooseVref] Worse bit 0, Min win 26, Win sum 427, Final Vref 30
3234 11:16:13.717203
3235 11:16:13.719653 Final TX Range 1 Vref 30
3236 11:16:13.719738
3237 11:16:13.719804 ==
3238 11:16:13.723280 Dram Type= 6, Freq= 0, CH_1, rank 0
3239 11:16:13.726854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3240 11:16:13.726944 ==
3241 11:16:13.727016
3242 11:16:13.730367
3243 11:16:13.730467 TX Vref Scan disable
3244 11:16:13.733401 == TX Byte 0 ==
3245 11:16:13.736666 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3246 11:16:13.739880 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3247 11:16:13.743835 == TX Byte 1 ==
3248 11:16:13.746607 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3249 11:16:13.750233 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3250 11:16:13.750376
3251 11:16:13.753655 [DATLAT]
3252 11:16:13.753797 Freq=1200, CH1 RK0
3253 11:16:13.753911
3254 11:16:13.756636 DATLAT Default: 0xd
3255 11:16:13.756797 0, 0xFFFF, sum = 0
3256 11:16:13.759805 1, 0xFFFF, sum = 0
3257 11:16:13.759994 2, 0xFFFF, sum = 0
3258 11:16:13.763174 3, 0xFFFF, sum = 0
3259 11:16:13.763365 4, 0xFFFF, sum = 0
3260 11:16:13.766585 5, 0xFFFF, sum = 0
3261 11:16:13.770364 6, 0xFFFF, sum = 0
3262 11:16:13.770740 7, 0xFFFF, sum = 0
3263 11:16:13.773182 8, 0xFFFF, sum = 0
3264 11:16:13.773459 9, 0xFFFF, sum = 0
3265 11:16:13.776642 10, 0xFFFF, sum = 0
3266 11:16:13.777104 11, 0xFFFF, sum = 0
3267 11:16:13.780161 12, 0x0, sum = 1
3268 11:16:13.780683 13, 0x0, sum = 2
3269 11:16:13.783121 14, 0x0, sum = 3
3270 11:16:13.783539 15, 0x0, sum = 4
3271 11:16:13.783874 best_step = 13
3272 11:16:13.786924
3273 11:16:13.787332 ==
3274 11:16:13.789820 Dram Type= 6, Freq= 0, CH_1, rank 0
3275 11:16:13.793006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3276 11:16:13.793421 ==
3277 11:16:13.793750 RX Vref Scan: 1
3278 11:16:13.794056
3279 11:16:13.796209 Set Vref Range= 32 -> 127
3280 11:16:13.796619
3281 11:16:13.799799 RX Vref 32 -> 127, step: 1
3282 11:16:13.800364
3283 11:16:13.803447 RX Delay -13 -> 252, step: 4
3284 11:16:13.803861
3285 11:16:13.807040 Set Vref, RX VrefLevel [Byte0]: 32
3286 11:16:13.809610 [Byte1]: 32
3287 11:16:13.810063
3288 11:16:13.813284 Set Vref, RX VrefLevel [Byte0]: 33
3289 11:16:13.816222 [Byte1]: 33
3290 11:16:13.819908
3291 11:16:13.820564 Set Vref, RX VrefLevel [Byte0]: 34
3292 11:16:13.823429 [Byte1]: 34
3293 11:16:13.827258
3294 11:16:13.827658 Set Vref, RX VrefLevel [Byte0]: 35
3295 11:16:13.830541 [Byte1]: 35
3296 11:16:13.835669
3297 11:16:13.836093 Set Vref, RX VrefLevel [Byte0]: 36
3298 11:16:13.838662 [Byte1]: 36
3299 11:16:13.843095
3300 11:16:13.843495 Set Vref, RX VrefLevel [Byte0]: 37
3301 11:16:13.847027 [Byte1]: 37
3302 11:16:13.851393
3303 11:16:13.851890 Set Vref, RX VrefLevel [Byte0]: 38
3304 11:16:13.854564 [Byte1]: 38
3305 11:16:13.859416
3306 11:16:13.859915 Set Vref, RX VrefLevel [Byte0]: 39
3307 11:16:13.862285 [Byte1]: 39
3308 11:16:13.866923
3309 11:16:13.867430 Set Vref, RX VrefLevel [Byte0]: 40
3310 11:16:13.870342 [Byte1]: 40
3311 11:16:13.875221
3312 11:16:13.875728 Set Vref, RX VrefLevel [Byte0]: 41
3313 11:16:13.877848 [Byte1]: 41
3314 11:16:13.883072
3315 11:16:13.883585 Set Vref, RX VrefLevel [Byte0]: 42
3316 11:16:13.886252 [Byte1]: 42
3317 11:16:13.890667
3318 11:16:13.891070 Set Vref, RX VrefLevel [Byte0]: 43
3319 11:16:13.894374 [Byte1]: 43
3320 11:16:13.898439
3321 11:16:13.898854 Set Vref, RX VrefLevel [Byte0]: 44
3322 11:16:13.901828 [Byte1]: 44
3323 11:16:13.906417
3324 11:16:13.906927 Set Vref, RX VrefLevel [Byte0]: 45
3325 11:16:13.909356 [Byte1]: 45
3326 11:16:13.914801
3327 11:16:13.915317 Set Vref, RX VrefLevel [Byte0]: 46
3328 11:16:13.917577 [Byte1]: 46
3329 11:16:13.922049
3330 11:16:13.922455 Set Vref, RX VrefLevel [Byte0]: 47
3331 11:16:13.925602 [Byte1]: 47
3332 11:16:13.929813
3333 11:16:13.930350 Set Vref, RX VrefLevel [Byte0]: 48
3334 11:16:13.933568 [Byte1]: 48
3335 11:16:13.938067
3336 11:16:13.938608 Set Vref, RX VrefLevel [Byte0]: 49
3337 11:16:13.941457 [Byte1]: 49
3338 11:16:13.945849
3339 11:16:13.946431 Set Vref, RX VrefLevel [Byte0]: 50
3340 11:16:13.949266 [Byte1]: 50
3341 11:16:13.953670
3342 11:16:13.954119 Set Vref, RX VrefLevel [Byte0]: 51
3343 11:16:13.957226 [Byte1]: 51
3344 11:16:13.961825
3345 11:16:13.962374 Set Vref, RX VrefLevel [Byte0]: 52
3346 11:16:13.964920 [Byte1]: 52
3347 11:16:13.969374
3348 11:16:13.969947 Set Vref, RX VrefLevel [Byte0]: 53
3349 11:16:13.973245 [Byte1]: 53
3350 11:16:13.977382
3351 11:16:13.977926 Set Vref, RX VrefLevel [Byte0]: 54
3352 11:16:13.980857 [Byte1]: 54
3353 11:16:13.985556
3354 11:16:13.986102 Set Vref, RX VrefLevel [Byte0]: 55
3355 11:16:13.988714 [Byte1]: 55
3356 11:16:13.993183
3357 11:16:13.993734 Set Vref, RX VrefLevel [Byte0]: 56
3358 11:16:13.996428 [Byte1]: 56
3359 11:16:14.000939
3360 11:16:14.001479 Set Vref, RX VrefLevel [Byte0]: 57
3361 11:16:14.003846 [Byte1]: 57
3362 11:16:14.008888
3363 11:16:14.009448 Set Vref, RX VrefLevel [Byte0]: 58
3364 11:16:14.012115 [Byte1]: 58
3365 11:16:14.016712
3366 11:16:14.017257 Set Vref, RX VrefLevel [Byte0]: 59
3367 11:16:14.019989 [Byte1]: 59
3368 11:16:14.024662
3369 11:16:14.025186 Set Vref, RX VrefLevel [Byte0]: 60
3370 11:16:14.027516 [Byte1]: 60
3371 11:16:14.032505
3372 11:16:14.032917 Set Vref, RX VrefLevel [Byte0]: 61
3373 11:16:14.035850 [Byte1]: 61
3374 11:16:14.040372
3375 11:16:14.040874 Set Vref, RX VrefLevel [Byte0]: 62
3376 11:16:14.043941 [Byte1]: 62
3377 11:16:14.048425
3378 11:16:14.048976 Set Vref, RX VrefLevel [Byte0]: 63
3379 11:16:14.051554 [Byte1]: 63
3380 11:16:14.055965
3381 11:16:14.059767 Set Vref, RX VrefLevel [Byte0]: 64
3382 11:16:14.062591 [Byte1]: 64
3383 11:16:14.063103
3384 11:16:14.066073 Set Vref, RX VrefLevel [Byte0]: 65
3385 11:16:14.069038 [Byte1]: 65
3386 11:16:14.069450
3387 11:16:14.072252 Set Vref, RX VrefLevel [Byte0]: 66
3388 11:16:14.075766 [Byte1]: 66
3389 11:16:14.079585
3390 11:16:14.079988 Set Vref, RX VrefLevel [Byte0]: 67
3391 11:16:14.082961 [Byte1]: 67
3392 11:16:14.087416
3393 11:16:14.087818 Set Vref, RX VrefLevel [Byte0]: 68
3394 11:16:14.090723 [Byte1]: 68
3395 11:16:14.095448
3396 11:16:14.095851 Final RX Vref Byte 0 = 54 to rank0
3397 11:16:14.098829 Final RX Vref Byte 1 = 53 to rank0
3398 11:16:14.101954 Final RX Vref Byte 0 = 54 to rank1
3399 11:16:14.105294 Final RX Vref Byte 1 = 53 to rank1==
3400 11:16:14.108512 Dram Type= 6, Freq= 0, CH_1, rank 0
3401 11:16:14.115218 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3402 11:16:14.115650 ==
3403 11:16:14.116108 DQS Delay:
3404 11:16:14.116429 DQS0 = 0, DQS1 = 0
3405 11:16:14.118626 DQM Delay:
3406 11:16:14.119029 DQM0 = 114, DQM1 = 113
3407 11:16:14.121883 DQ Delay:
3408 11:16:14.125185 DQ0 =120, DQ1 =108, DQ2 =106, DQ3 =114
3409 11:16:14.128485 DQ4 =110, DQ5 =122, DQ6 =124, DQ7 =110
3410 11:16:14.132020 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =108
3411 11:16:14.135226 DQ12 =122, DQ13 =120, DQ14 =120, DQ15 =122
3412 11:16:14.135774
3413 11:16:14.136157
3414 11:16:14.145089 [DQSOSCAuto] RK0, (LSB)MR18= 0xf2fe, (MSB)MR19= 0x303, tDQSOscB0 = 410 ps tDQSOscB1 = 415 ps
3415 11:16:14.145610 CH1 RK0: MR19=303, MR18=F2FE
3416 11:16:14.151658 CH1_RK0: MR19=0x303, MR18=0xF2FE, DQSOSC=410, MR23=63, INC=39, DEC=26
3417 11:16:14.152215
3418 11:16:14.154910 ----->DramcWriteLeveling(PI) begin...
3419 11:16:14.155454 ==
3420 11:16:14.158393 Dram Type= 6, Freq= 0, CH_1, rank 1
3421 11:16:14.165012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3422 11:16:14.165528 ==
3423 11:16:14.167900 Write leveling (Byte 0): 25 => 25
3424 11:16:14.171593 Write leveling (Byte 1): 27 => 27
3425 11:16:14.172154 DramcWriteLeveling(PI) end<-----
3426 11:16:14.172494
3427 11:16:14.175030 ==
3428 11:16:14.178460 Dram Type= 6, Freq= 0, CH_1, rank 1
3429 11:16:14.181810 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3430 11:16:14.182227 ==
3431 11:16:14.185683 [Gating] SW mode calibration
3432 11:16:14.191793 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3433 11:16:14.194722 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3434 11:16:14.201479 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3435 11:16:14.204805 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3436 11:16:14.208090 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3437 11:16:14.214583 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3438 11:16:14.218230 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3439 11:16:14.221079 0 15 20 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
3440 11:16:14.227983 0 15 24 | B1->B0 | 3434 2626 | 1 0 | (1 1) (1 0)
3441 11:16:14.230992 0 15 28 | B1->B0 | 3333 2323 | 0 0 | (1 0) (0 0)
3442 11:16:14.234812 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3443 11:16:14.241282 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3444 11:16:14.244275 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3445 11:16:14.247807 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3446 11:16:14.254445 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3447 11:16:14.257927 1 0 20 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
3448 11:16:14.260854 1 0 24 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
3449 11:16:14.267801 1 0 28 | B1->B0 | 3b3b 4646 | 1 0 | (0 0) (0 0)
3450 11:16:14.271392 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3451 11:16:14.273785 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3452 11:16:14.280881 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3453 11:16:14.283967 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3454 11:16:14.287387 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3455 11:16:14.294025 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3456 11:16:14.297553 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3457 11:16:14.300682 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3458 11:16:14.307545 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3459 11:16:14.310366 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3460 11:16:14.313754 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3461 11:16:14.320497 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3462 11:16:14.324416 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3463 11:16:14.327143 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3464 11:16:14.333246 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3465 11:16:14.336938 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3466 11:16:14.339677 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3467 11:16:14.346899 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3468 11:16:14.350145 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3469 11:16:14.353283 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3470 11:16:14.360143 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3471 11:16:14.363256 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3472 11:16:14.366571 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3473 11:16:14.373316 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3474 11:16:14.373877 Total UI for P1: 0, mck2ui 16
3475 11:16:14.379822 best dqsien dly found for B0: ( 1, 3, 22)
3476 11:16:14.382886 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3477 11:16:14.386356 Total UI for P1: 0, mck2ui 16
3478 11:16:14.389558 best dqsien dly found for B1: ( 1, 3, 26)
3479 11:16:14.392818 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3480 11:16:14.396419 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3481 11:16:14.397008
3482 11:16:14.399303 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3483 11:16:14.402557 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3484 11:16:14.405938 [Gating] SW calibration Done
3485 11:16:14.406500 ==
3486 11:16:14.409350 Dram Type= 6, Freq= 0, CH_1, rank 1
3487 11:16:14.415771 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3488 11:16:14.416376 ==
3489 11:16:14.416783 RX Vref Scan: 0
3490 11:16:14.417124
3491 11:16:14.419028 RX Vref 0 -> 0, step: 1
3492 11:16:14.419582
3493 11:16:14.422505 RX Delay -40 -> 252, step: 8
3494 11:16:14.425644 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3495 11:16:14.428723 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3496 11:16:14.432110 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3497 11:16:14.438814 iDelay=200, Bit 3, Center 115 (48 ~ 183) 136
3498 11:16:14.442359 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3499 11:16:14.445349 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3500 11:16:14.448834 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3501 11:16:14.452005 iDelay=200, Bit 7, Center 119 (48 ~ 191) 144
3502 11:16:14.458394 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3503 11:16:14.461926 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3504 11:16:14.465108 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3505 11:16:14.468272 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3506 11:16:14.471825 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3507 11:16:14.478300 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3508 11:16:14.481540 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3509 11:16:14.484992 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3510 11:16:14.485514 ==
3511 11:16:14.487868 Dram Type= 6, Freq= 0, CH_1, rank 1
3512 11:16:14.491312 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3513 11:16:14.494799 ==
3514 11:16:14.495315 DQS Delay:
3515 11:16:14.495651 DQS0 = 0, DQS1 = 0
3516 11:16:14.497935 DQM Delay:
3517 11:16:14.498447 DQM0 = 116, DQM1 = 112
3518 11:16:14.501377 DQ Delay:
3519 11:16:14.504866 DQ0 =119, DQ1 =111, DQ2 =103, DQ3 =115
3520 11:16:14.507810 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =119
3521 11:16:14.510948 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3522 11:16:14.514232 DQ12 =123, DQ13 =119, DQ14 =115, DQ15 =119
3523 11:16:14.514749
3524 11:16:14.515083
3525 11:16:14.515387 ==
3526 11:16:14.517584 Dram Type= 6, Freq= 0, CH_1, rank 1
3527 11:16:14.520937 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3528 11:16:14.523996 ==
3529 11:16:14.524557
3530 11:16:14.524888
3531 11:16:14.525195 TX Vref Scan disable
3532 11:16:14.527321 == TX Byte 0 ==
3533 11:16:14.530473 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3534 11:16:14.533663 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3535 11:16:14.537083 == TX Byte 1 ==
3536 11:16:14.541015 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3537 11:16:14.543626 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3538 11:16:14.547455 ==
3539 11:16:14.550235 Dram Type= 6, Freq= 0, CH_1, rank 1
3540 11:16:14.553641 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3541 11:16:14.554057 ==
3542 11:16:14.564755 TX Vref=22, minBit 9, minWin=24, winSum=417
3543 11:16:14.567900 TX Vref=24, minBit 3, minWin=25, winSum=422
3544 11:16:14.571431 TX Vref=26, minBit 9, minWin=25, winSum=424
3545 11:16:14.575122 TX Vref=28, minBit 9, minWin=25, winSum=427
3546 11:16:14.577742 TX Vref=30, minBit 9, minWin=26, winSum=431
3547 11:16:14.584886 TX Vref=32, minBit 9, minWin=25, winSum=432
3548 11:16:14.587951 [TxChooseVref] Worse bit 9, Min win 26, Win sum 431, Final Vref 30
3549 11:16:14.588491
3550 11:16:14.590979 Final TX Range 1 Vref 30
3551 11:16:14.591395
3552 11:16:14.591719 ==
3553 11:16:14.594426 Dram Type= 6, Freq= 0, CH_1, rank 1
3554 11:16:14.597468 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3555 11:16:14.601431 ==
3556 11:16:14.601948
3557 11:16:14.602282
3558 11:16:14.602588 TX Vref Scan disable
3559 11:16:14.604391 == TX Byte 0 ==
3560 11:16:14.607711 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3561 11:16:14.614405 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3562 11:16:14.614929 == TX Byte 1 ==
3563 11:16:14.617381 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3564 11:16:14.624660 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3565 11:16:14.625194
3566 11:16:14.625528 [DATLAT]
3567 11:16:14.625833 Freq=1200, CH1 RK1
3568 11:16:14.626128
3569 11:16:14.627323 DATLAT Default: 0xd
3570 11:16:14.627667 0, 0xFFFF, sum = 0
3571 11:16:14.630591 1, 0xFFFF, sum = 0
3572 11:16:14.635077 2, 0xFFFF, sum = 0
3573 11:16:14.635506 3, 0xFFFF, sum = 0
3574 11:16:14.637899 4, 0xFFFF, sum = 0
3575 11:16:14.638422 5, 0xFFFF, sum = 0
3576 11:16:14.641192 6, 0xFFFF, sum = 0
3577 11:16:14.641714 7, 0xFFFF, sum = 0
3578 11:16:14.644326 8, 0xFFFF, sum = 0
3579 11:16:14.644850 9, 0xFFFF, sum = 0
3580 11:16:14.647457 10, 0xFFFF, sum = 0
3581 11:16:14.647927 11, 0xFFFF, sum = 0
3582 11:16:14.650463 12, 0x0, sum = 1
3583 11:16:14.650880 13, 0x0, sum = 2
3584 11:16:14.653746 14, 0x0, sum = 3
3585 11:16:14.654165 15, 0x0, sum = 4
3586 11:16:14.656996 best_step = 13
3587 11:16:14.657413
3588 11:16:14.657741 ==
3589 11:16:14.660695 Dram Type= 6, Freq= 0, CH_1, rank 1
3590 11:16:14.664001 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3591 11:16:14.664442 ==
3592 11:16:14.664778 RX Vref Scan: 0
3593 11:16:14.667280
3594 11:16:14.667730 RX Vref 0 -> 0, step: 1
3595 11:16:14.668090
3596 11:16:14.670653 RX Delay -13 -> 252, step: 4
3597 11:16:14.677183 iDelay=191, Bit 0, Center 116 (47 ~ 186) 140
3598 11:16:14.680910 iDelay=191, Bit 1, Center 112 (43 ~ 182) 140
3599 11:16:14.683714 iDelay=191, Bit 2, Center 108 (43 ~ 174) 132
3600 11:16:14.687223 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3601 11:16:14.690568 iDelay=191, Bit 4, Center 114 (43 ~ 186) 144
3602 11:16:14.697154 iDelay=191, Bit 5, Center 122 (55 ~ 190) 136
3603 11:16:14.700151 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3604 11:16:14.704362 iDelay=191, Bit 7, Center 112 (43 ~ 182) 140
3605 11:16:14.706960 iDelay=191, Bit 8, Center 100 (39 ~ 162) 124
3606 11:16:14.709929 iDelay=191, Bit 9, Center 104 (43 ~ 166) 124
3607 11:16:14.716600 iDelay=191, Bit 10, Center 114 (51 ~ 178) 128
3608 11:16:14.719902 iDelay=191, Bit 11, Center 106 (43 ~ 170) 128
3609 11:16:14.723431 iDelay=191, Bit 12, Center 120 (59 ~ 182) 124
3610 11:16:14.726978 iDelay=191, Bit 13, Center 118 (55 ~ 182) 128
3611 11:16:14.729938 iDelay=191, Bit 14, Center 120 (59 ~ 182) 124
3612 11:16:14.736597 iDelay=191, Bit 15, Center 122 (59 ~ 186) 128
3613 11:16:14.737112 ==
3614 11:16:14.740073 Dram Type= 6, Freq= 0, CH_1, rank 1
3615 11:16:14.743227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3616 11:16:14.743745 ==
3617 11:16:14.744121 DQS Delay:
3618 11:16:14.746104 DQS0 = 0, DQS1 = 0
3619 11:16:14.746519 DQM Delay:
3620 11:16:14.751045 DQM0 = 114, DQM1 = 113
3621 11:16:14.751558 DQ Delay:
3622 11:16:14.752487 DQ0 =116, DQ1 =112, DQ2 =108, DQ3 =112
3623 11:16:14.756427 DQ4 =114, DQ5 =122, DQ6 =122, DQ7 =112
3624 11:16:14.759076 DQ8 =100, DQ9 =104, DQ10 =114, DQ11 =106
3625 11:16:14.765643 DQ12 =120, DQ13 =118, DQ14 =120, DQ15 =122
3626 11:16:14.766110
3627 11:16:14.766527
3628 11:16:14.772467 [DQSOSCAuto] RK1, (LSB)MR18= 0xf507, (MSB)MR19= 0x304, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
3629 11:16:14.776335 CH1 RK1: MR19=304, MR18=F507
3630 11:16:14.782250 CH1_RK1: MR19=0x304, MR18=0xF507, DQSOSC=407, MR23=63, INC=39, DEC=26
3631 11:16:14.785721 [RxdqsGatingPostProcess] freq 1200
3632 11:16:14.789289 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3633 11:16:14.792370 best DQS0 dly(2T, 0.5T) = (0, 11)
3634 11:16:14.795896 best DQS1 dly(2T, 0.5T) = (0, 11)
3635 11:16:14.798904 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3636 11:16:14.802333 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3637 11:16:14.805186 best DQS0 dly(2T, 0.5T) = (0, 11)
3638 11:16:14.808549 best DQS1 dly(2T, 0.5T) = (0, 11)
3639 11:16:14.812075 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3640 11:16:14.815353 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3641 11:16:14.818675 Pre-setting of DQS Precalculation
3642 11:16:14.824908 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3643 11:16:14.831105 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3644 11:16:14.838186 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3645 11:16:14.838271
3646 11:16:14.838336
3647 11:16:14.841728 [Calibration Summary] 2400 Mbps
3648 11:16:14.842145 CH 0, Rank 0
3649 11:16:14.844825 SW Impedance : PASS
3650 11:16:14.848094 DUTY Scan : NO K
3651 11:16:14.848516 ZQ Calibration : PASS
3652 11:16:14.851774 Jitter Meter : NO K
3653 11:16:14.854559 CBT Training : PASS
3654 11:16:14.854990 Write leveling : PASS
3655 11:16:14.858364 RX DQS gating : PASS
3656 11:16:14.861872 RX DQ/DQS(RDDQC) : PASS
3657 11:16:14.862285 TX DQ/DQS : PASS
3658 11:16:14.864404 RX DATLAT : PASS
3659 11:16:14.864816 RX DQ/DQS(Engine): PASS
3660 11:16:14.867829 TX OE : NO K
3661 11:16:14.868298 All Pass.
3662 11:16:14.868629
3663 11:16:14.870986 CH 0, Rank 1
3664 11:16:14.871398 SW Impedance : PASS
3665 11:16:14.874737 DUTY Scan : NO K
3666 11:16:14.877387 ZQ Calibration : PASS
3667 11:16:14.877799 Jitter Meter : NO K
3668 11:16:14.881227 CBT Training : PASS
3669 11:16:14.883927 Write leveling : PASS
3670 11:16:14.884367 RX DQS gating : PASS
3671 11:16:14.887317 RX DQ/DQS(RDDQC) : PASS
3672 11:16:14.890679 TX DQ/DQS : PASS
3673 11:16:14.891094 RX DATLAT : PASS
3674 11:16:14.893735 RX DQ/DQS(Engine): PASS
3675 11:16:14.897156 TX OE : NO K
3676 11:16:14.897570 All Pass.
3677 11:16:14.897897
3678 11:16:14.898203 CH 1, Rank 0
3679 11:16:14.900791 SW Impedance : PASS
3680 11:16:14.904099 DUTY Scan : NO K
3681 11:16:14.904514 ZQ Calibration : PASS
3682 11:16:14.907673 Jitter Meter : NO K
3683 11:16:14.911068 CBT Training : PASS
3684 11:16:14.911488 Write leveling : PASS
3685 11:16:14.914154 RX DQS gating : PASS
3686 11:16:14.917028 RX DQ/DQS(RDDQC) : PASS
3687 11:16:14.917451 TX DQ/DQS : PASS
3688 11:16:14.920323 RX DATLAT : PASS
3689 11:16:14.923703 RX DQ/DQS(Engine): PASS
3690 11:16:14.924145 TX OE : NO K
3691 11:16:14.927196 All Pass.
3692 11:16:14.927612
3693 11:16:14.927939 CH 1, Rank 1
3694 11:16:14.930282 SW Impedance : PASS
3695 11:16:14.930697 DUTY Scan : NO K
3696 11:16:14.933903 ZQ Calibration : PASS
3697 11:16:14.936570 Jitter Meter : NO K
3698 11:16:14.937168 CBT Training : PASS
3699 11:16:14.940013 Write leveling : PASS
3700 11:16:14.943785 RX DQS gating : PASS
3701 11:16:14.944233 RX DQ/DQS(RDDQC) : PASS
3702 11:16:14.946940 TX DQ/DQS : PASS
3703 11:16:14.950124 RX DATLAT : PASS
3704 11:16:14.950542 RX DQ/DQS(Engine): PASS
3705 11:16:14.953315 TX OE : NO K
3706 11:16:14.953732 All Pass.
3707 11:16:14.954064
3708 11:16:14.956855 DramC Write-DBI off
3709 11:16:14.960224 PER_BANK_REFRESH: Hybrid Mode
3710 11:16:14.960743 TX_TRACKING: ON
3711 11:16:14.969794 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3712 11:16:14.973351 [FAST_K] Save calibration result to emmc
3713 11:16:14.976490 dramc_set_vcore_voltage set vcore to 650000
3714 11:16:14.979573 Read voltage for 600, 5
3715 11:16:14.979988 Vio18 = 0
3716 11:16:14.980348 Vcore = 650000
3717 11:16:14.983218 Vdram = 0
3718 11:16:14.983635 Vddq = 0
3719 11:16:14.983963 Vmddr = 0
3720 11:16:14.989420 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3721 11:16:14.993273 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3722 11:16:14.995974 MEM_TYPE=3, freq_sel=19
3723 11:16:14.999893 sv_algorithm_assistance_LP4_1600
3724 11:16:15.002803 ============ PULL DRAM RESETB DOWN ============
3725 11:16:15.006069 ========== PULL DRAM RESETB DOWN end =========
3726 11:16:15.012247 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3727 11:16:15.015780 ===================================
3728 11:16:15.019134 LPDDR4 DRAM CONFIGURATION
3729 11:16:15.022180 ===================================
3730 11:16:15.022665 EX_ROW_EN[0] = 0x0
3731 11:16:15.025905 EX_ROW_EN[1] = 0x0
3732 11:16:15.026471 LP4Y_EN = 0x0
3733 11:16:15.029241 WORK_FSP = 0x0
3734 11:16:15.029801 WL = 0x2
3735 11:16:15.032206 RL = 0x2
3736 11:16:15.032662 BL = 0x2
3737 11:16:15.035776 RPST = 0x0
3738 11:16:15.038788 RD_PRE = 0x0
3739 11:16:15.039246 WR_PRE = 0x1
3740 11:16:15.041899 WR_PST = 0x0
3741 11:16:15.042465 DBI_WR = 0x0
3742 11:16:15.045270 DBI_RD = 0x0
3743 11:16:15.045711 OTF = 0x1
3744 11:16:15.048642 ===================================
3745 11:16:15.051927 ===================================
3746 11:16:15.055255 ANA top config
3747 11:16:15.058273 ===================================
3748 11:16:15.058700 DLL_ASYNC_EN = 0
3749 11:16:15.062168 ALL_SLAVE_EN = 1
3750 11:16:15.064597 NEW_RANK_MODE = 1
3751 11:16:15.067976 DLL_IDLE_MODE = 1
3752 11:16:15.068422 LP45_APHY_COMB_EN = 1
3753 11:16:15.071309 TX_ODT_DIS = 1
3754 11:16:15.074846 NEW_8X_MODE = 1
3755 11:16:15.078222 ===================================
3756 11:16:15.081122 ===================================
3757 11:16:15.084373 data_rate = 1200
3758 11:16:15.088375 CKR = 1
3759 11:16:15.091219 DQ_P2S_RATIO = 8
3760 11:16:15.095110 ===================================
3761 11:16:15.095679 CA_P2S_RATIO = 8
3762 11:16:15.097679 DQ_CA_OPEN = 0
3763 11:16:15.100859 DQ_SEMI_OPEN = 0
3764 11:16:15.104207 CA_SEMI_OPEN = 0
3765 11:16:15.107605 CA_FULL_RATE = 0
3766 11:16:15.110965 DQ_CKDIV4_EN = 1
3767 11:16:15.113898 CA_CKDIV4_EN = 1
3768 11:16:15.114320 CA_PREDIV_EN = 0
3769 11:16:15.117512 PH8_DLY = 0
3770 11:16:15.120692 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3771 11:16:15.124220 DQ_AAMCK_DIV = 4
3772 11:16:15.127472 CA_AAMCK_DIV = 4
3773 11:16:15.130736 CA_ADMCK_DIV = 4
3774 11:16:15.131254 DQ_TRACK_CA_EN = 0
3775 11:16:15.133976 CA_PICK = 600
3776 11:16:15.136733 CA_MCKIO = 600
3777 11:16:15.140101 MCKIO_SEMI = 0
3778 11:16:15.143628 PLL_FREQ = 2288
3779 11:16:15.147195 DQ_UI_PI_RATIO = 32
3780 11:16:15.150302 CA_UI_PI_RATIO = 0
3781 11:16:15.153483 ===================================
3782 11:16:15.156720 ===================================
3783 11:16:15.157278 memory_type:LPDDR4
3784 11:16:15.160314 GP_NUM : 10
3785 11:16:15.163587 SRAM_EN : 1
3786 11:16:15.164187 MD32_EN : 0
3787 11:16:15.166561 ===================================
3788 11:16:15.170006 [ANA_INIT] >>>>>>>>>>>>>>
3789 11:16:15.173533 <<<<<< [CONFIGURE PHASE]: ANA_TX
3790 11:16:15.177432 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3791 11:16:15.180291 ===================================
3792 11:16:15.183581 data_rate = 1200,PCW = 0X5800
3793 11:16:15.186294 ===================================
3794 11:16:15.189686 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3795 11:16:15.192826 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3796 11:16:15.200100 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3797 11:16:15.206297 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3798 11:16:15.209354 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3799 11:16:15.212775 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3800 11:16:15.213192 [ANA_INIT] flow start
3801 11:16:15.215829 [ANA_INIT] PLL >>>>>>>>
3802 11:16:15.219651 [ANA_INIT] PLL <<<<<<<<
3803 11:16:15.220210 [ANA_INIT] MIDPI >>>>>>>>
3804 11:16:15.222501 [ANA_INIT] MIDPI <<<<<<<<
3805 11:16:15.226527 [ANA_INIT] DLL >>>>>>>>
3806 11:16:15.227042 [ANA_INIT] flow end
3807 11:16:15.232491 ============ LP4 DIFF to SE enter ============
3808 11:16:15.235836 ============ LP4 DIFF to SE exit ============
3809 11:16:15.239236 [ANA_INIT] <<<<<<<<<<<<<
3810 11:16:15.242792 [Flow] Enable top DCM control >>>>>
3811 11:16:15.245589 [Flow] Enable top DCM control <<<<<
3812 11:16:15.246006 Enable DLL master slave shuffle
3813 11:16:15.252588 ==============================================================
3814 11:16:15.256104 Gating Mode config
3815 11:16:15.258654 ==============================================================
3816 11:16:15.262138 Config description:
3817 11:16:15.272193 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3818 11:16:15.278782 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3819 11:16:15.282027 SELPH_MODE 0: By rank 1: By Phase
3820 11:16:15.288534 ==============================================================
3821 11:16:15.291384 GAT_TRACK_EN = 1
3822 11:16:15.294964 RX_GATING_MODE = 2
3823 11:16:15.298376 RX_GATING_TRACK_MODE = 2
3824 11:16:15.301317 SELPH_MODE = 1
3825 11:16:15.304561 PICG_EARLY_EN = 1
3826 11:16:15.308278 VALID_LAT_VALUE = 1
3827 11:16:15.311357 ==============================================================
3828 11:16:15.314379 Enter into Gating configuration >>>>
3829 11:16:15.317543 Exit from Gating configuration <<<<
3830 11:16:15.321545 Enter into DVFS_PRE_config >>>>>
3831 11:16:15.333939 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3832 11:16:15.337830 Exit from DVFS_PRE_config <<<<<
3833 11:16:15.338433 Enter into PICG configuration >>>>
3834 11:16:15.340771 Exit from PICG configuration <<<<
3835 11:16:15.344007 [RX_INPUT] configuration >>>>>
3836 11:16:15.347538 [RX_INPUT] configuration <<<<<
3837 11:16:15.354816 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3838 11:16:15.357095 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3839 11:16:15.364196 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3840 11:16:15.370763 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3841 11:16:15.376663 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3842 11:16:15.384235 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3843 11:16:15.386985 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3844 11:16:15.389931 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3845 11:16:15.396903 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3846 11:16:15.399727 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3847 11:16:15.403050 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3848 11:16:15.406682 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3849 11:16:15.409899 ===================================
3850 11:16:15.412932 LPDDR4 DRAM CONFIGURATION
3851 11:16:15.416274 ===================================
3852 11:16:15.419838 EX_ROW_EN[0] = 0x0
3853 11:16:15.420364 EX_ROW_EN[1] = 0x0
3854 11:16:15.423366 LP4Y_EN = 0x0
3855 11:16:15.423828 WORK_FSP = 0x0
3856 11:16:15.425995 WL = 0x2
3857 11:16:15.426515 RL = 0x2
3858 11:16:15.429698 BL = 0x2
3859 11:16:15.432640 RPST = 0x0
3860 11:16:15.433291 RD_PRE = 0x0
3861 11:16:15.435936 WR_PRE = 0x1
3862 11:16:15.436531 WR_PST = 0x0
3863 11:16:15.439640 DBI_WR = 0x0
3864 11:16:15.440189 DBI_RD = 0x0
3865 11:16:15.442410 OTF = 0x1
3866 11:16:15.446160 ===================================
3867 11:16:15.448813 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3868 11:16:15.452359 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3869 11:16:15.459510 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3870 11:16:15.462320 ===================================
3871 11:16:15.462907 LPDDR4 DRAM CONFIGURATION
3872 11:16:15.465485 ===================================
3873 11:16:15.468802 EX_ROW_EN[0] = 0x10
3874 11:16:15.469238 EX_ROW_EN[1] = 0x0
3875 11:16:15.472312 LP4Y_EN = 0x0
3876 11:16:15.475560 WORK_FSP = 0x0
3877 11:16:15.476144 WL = 0x2
3878 11:16:15.478827 RL = 0x2
3879 11:16:15.479372 BL = 0x2
3880 11:16:15.482641 RPST = 0x0
3881 11:16:15.483187 RD_PRE = 0x0
3882 11:16:15.485715 WR_PRE = 0x1
3883 11:16:15.486258 WR_PST = 0x0
3884 11:16:15.488422 DBI_WR = 0x0
3885 11:16:15.488857 DBI_RD = 0x0
3886 11:16:15.492537 OTF = 0x1
3887 11:16:15.495531 ===================================
3888 11:16:15.501558 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3889 11:16:15.505028 nWR fixed to 30
3890 11:16:15.505556 [ModeRegInit_LP4] CH0 RK0
3891 11:16:15.508137 [ModeRegInit_LP4] CH0 RK1
3892 11:16:15.511745 [ModeRegInit_LP4] CH1 RK0
3893 11:16:15.515042 [ModeRegInit_LP4] CH1 RK1
3894 11:16:15.515587 match AC timing 17
3895 11:16:15.521551 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3896 11:16:15.524727 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3897 11:16:15.528238 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3898 11:16:15.534579 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3899 11:16:15.538217 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3900 11:16:15.538980 ==
3901 11:16:15.540943 Dram Type= 6, Freq= 0, CH_0, rank 0
3902 11:16:15.544431 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3903 11:16:15.544986 ==
3904 11:16:15.551139 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3905 11:16:15.557309 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3906 11:16:15.561099 [CA 0] Center 36 (6~67) winsize 62
3907 11:16:15.563914 [CA 1] Center 36 (6~67) winsize 62
3908 11:16:15.567767 [CA 2] Center 34 (4~65) winsize 62
3909 11:16:15.570950 [CA 3] Center 34 (4~65) winsize 62
3910 11:16:15.573892 [CA 4] Center 33 (3~64) winsize 62
3911 11:16:15.577399 [CA 5] Center 33 (3~64) winsize 62
3912 11:16:15.577955
3913 11:16:15.581144 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3914 11:16:15.581704
3915 11:16:15.584490 [CATrainingPosCal] consider 1 rank data
3916 11:16:15.587598 u2DelayCellTimex100 = 270/100 ps
3917 11:16:15.590849 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3918 11:16:15.594079 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3919 11:16:15.596988 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3920 11:16:15.600865 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3921 11:16:15.607163 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3922 11:16:15.611025 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3923 11:16:15.611592
3924 11:16:15.613572 CA PerBit enable=1, Macro0, CA PI delay=33
3925 11:16:15.614032
3926 11:16:15.617127 [CBTSetCACLKResult] CA Dly = 33
3927 11:16:15.617624 CS Dly: 4 (0~35)
3928 11:16:15.617990 ==
3929 11:16:15.619856 Dram Type= 6, Freq= 0, CH_0, rank 1
3930 11:16:15.626879 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3931 11:16:15.627314 ==
3932 11:16:15.630033 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3933 11:16:15.636657 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
3934 11:16:15.639805 [CA 0] Center 36 (6~67) winsize 62
3935 11:16:15.643422 [CA 1] Center 36 (6~67) winsize 62
3936 11:16:15.646416 [CA 2] Center 34 (4~65) winsize 62
3937 11:16:15.649390 [CA 3] Center 34 (4~65) winsize 62
3938 11:16:15.652862 [CA 4] Center 34 (3~65) winsize 63
3939 11:16:15.656096 [CA 5] Center 33 (3~64) winsize 62
3940 11:16:15.656563
3941 11:16:15.659375 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3942 11:16:15.659846
3943 11:16:15.662945 [CATrainingPosCal] consider 2 rank data
3944 11:16:15.665772 u2DelayCellTimex100 = 270/100 ps
3945 11:16:15.669217 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3946 11:16:15.675895 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
3947 11:16:15.679576 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3948 11:16:15.682735 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3949 11:16:15.686364 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3950 11:16:15.689347 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3951 11:16:15.689919
3952 11:16:15.692170 CA PerBit enable=1, Macro0, CA PI delay=33
3953 11:16:15.692639
3954 11:16:15.695829 [CBTSetCACLKResult] CA Dly = 33
3955 11:16:15.699131 CS Dly: 4 (0~36)
3956 11:16:15.699701
3957 11:16:15.702210 ----->DramcWriteLeveling(PI) begin...
3958 11:16:15.702683 ==
3959 11:16:15.706025 Dram Type= 6, Freq= 0, CH_0, rank 0
3960 11:16:15.709667 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3961 11:16:15.710239 ==
3962 11:16:15.712608 Write leveling (Byte 0): 33 => 33
3963 11:16:15.715643 Write leveling (Byte 1): 29 => 29
3964 11:16:15.719488 DramcWriteLeveling(PI) end<-----
3965 11:16:15.719992
3966 11:16:15.720427 ==
3967 11:16:15.721752 Dram Type= 6, Freq= 0, CH_0, rank 0
3968 11:16:15.726074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3969 11:16:15.726596 ==
3970 11:16:15.728458 [Gating] SW mode calibration
3971 11:16:15.735661 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
3972 11:16:15.741535 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
3973 11:16:15.745323 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3974 11:16:15.748735 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3975 11:16:15.755075 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3976 11:16:15.757946 0 9 12 | B1->B0 | 3434 3030 | 1 1 | (1 1) (1 1)
3977 11:16:15.761533 0 9 16 | B1->B0 | 2e2e 2828 | 0 0 | (0 1) (1 1)
3978 11:16:15.767996 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3979 11:16:15.771497 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3980 11:16:15.777864 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3981 11:16:15.781293 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3982 11:16:15.784620 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3983 11:16:15.791092 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3984 11:16:15.794658 0 10 12 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (0 0)
3985 11:16:15.798056 0 10 16 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
3986 11:16:15.804462 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3987 11:16:15.808158 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3988 11:16:15.811768 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3989 11:16:15.817931 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3990 11:16:15.820573 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3991 11:16:15.824192 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3992 11:16:15.830738 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3993 11:16:15.833444 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
3994 11:16:15.837494 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3995 11:16:15.843312 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3996 11:16:15.846545 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3997 11:16:15.850002 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3998 11:16:15.856462 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3999 11:16:15.859567 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4000 11:16:15.863088 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4001 11:16:15.869556 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4002 11:16:15.873049 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4003 11:16:15.876549 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4004 11:16:15.883402 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4005 11:16:15.886871 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4006 11:16:15.890163 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4007 11:16:15.896460 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4008 11:16:15.899539 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4009 11:16:15.903014 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4010 11:16:15.906223 Total UI for P1: 0, mck2ui 16
4011 11:16:15.909497 best dqsien dly found for B0: ( 0, 13, 12)
4012 11:16:15.916459 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4013 11:16:15.917033 Total UI for P1: 0, mck2ui 16
4014 11:16:15.923133 best dqsien dly found for B1: ( 0, 13, 16)
4015 11:16:15.926272 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4016 11:16:15.928949 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4017 11:16:15.929410
4018 11:16:15.932625 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4019 11:16:15.936167 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4020 11:16:15.939020 [Gating] SW calibration Done
4021 11:16:15.939489 ==
4022 11:16:15.942634 Dram Type= 6, Freq= 0, CH_0, rank 0
4023 11:16:15.946910 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4024 11:16:15.947415 ==
4025 11:16:15.948918 RX Vref Scan: 0
4026 11:16:15.949422
4027 11:16:15.949917 RX Vref 0 -> 0, step: 1
4028 11:16:15.951979
4029 11:16:15.952482 RX Delay -230 -> 252, step: 16
4030 11:16:15.958437 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4031 11:16:15.961812 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4032 11:16:15.965082 iDelay=218, Bit 2, Center 49 (-102 ~ 201) 304
4033 11:16:15.968240 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4034 11:16:15.975167 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4035 11:16:15.978492 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4036 11:16:15.981894 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4037 11:16:15.984606 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4038 11:16:15.991341 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4039 11:16:15.994518 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4040 11:16:15.998221 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4041 11:16:16.001728 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4042 11:16:16.008134 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4043 11:16:16.011567 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4044 11:16:16.014418 iDelay=218, Bit 14, Center 49 (-102 ~ 201) 304
4045 11:16:16.017705 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4046 11:16:16.018127 ==
4047 11:16:16.021268 Dram Type= 6, Freq= 0, CH_0, rank 0
4048 11:16:16.028007 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4049 11:16:16.028567 ==
4050 11:16:16.028913 DQS Delay:
4051 11:16:16.031025 DQS0 = 0, DQS1 = 0
4052 11:16:16.031549 DQM Delay:
4053 11:16:16.031891 DQM0 = 46, DQM1 = 35
4054 11:16:16.034405 DQ Delay:
4055 11:16:16.037600 DQ0 =41, DQ1 =49, DQ2 =49, DQ3 =33
4056 11:16:16.040864 DQ4 =49, DQ5 =33, DQ6 =57, DQ7 =57
4057 11:16:16.043785 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =33
4058 11:16:16.047491 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =49
4059 11:16:16.048251
4060 11:16:16.048627
4061 11:16:16.048966 ==
4062 11:16:16.051001 Dram Type= 6, Freq= 0, CH_0, rank 0
4063 11:16:16.053825 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4064 11:16:16.054398 ==
4065 11:16:16.054770
4066 11:16:16.055105
4067 11:16:16.057383 TX Vref Scan disable
4068 11:16:16.060408 == TX Byte 0 ==
4069 11:16:16.063491 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
4070 11:16:16.067185 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
4071 11:16:16.070503 == TX Byte 1 ==
4072 11:16:16.074069 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4073 11:16:16.077020 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4074 11:16:16.077482 ==
4075 11:16:16.080771 Dram Type= 6, Freq= 0, CH_0, rank 0
4076 11:16:16.087305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4077 11:16:16.087896 ==
4078 11:16:16.088300
4079 11:16:16.088639
4080 11:16:16.088962 TX Vref Scan disable
4081 11:16:16.091626 == TX Byte 0 ==
4082 11:16:16.094527 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4083 11:16:16.101276 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4084 11:16:16.101852 == TX Byte 1 ==
4085 11:16:16.104143 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4086 11:16:16.111395 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4087 11:16:16.111956
4088 11:16:16.112354 [DATLAT]
4089 11:16:16.112693 Freq=600, CH0 RK0
4090 11:16:16.113017
4091 11:16:16.113861 DATLAT Default: 0x9
4092 11:16:16.117463 0, 0xFFFF, sum = 0
4093 11:16:16.118030 1, 0xFFFF, sum = 0
4094 11:16:16.120717 2, 0xFFFF, sum = 0
4095 11:16:16.121184 3, 0xFFFF, sum = 0
4096 11:16:16.124411 4, 0xFFFF, sum = 0
4097 11:16:16.124976 5, 0xFFFF, sum = 0
4098 11:16:16.127514 6, 0xFFFF, sum = 0
4099 11:16:16.128113 7, 0xFFFF, sum = 0
4100 11:16:16.130741 8, 0x0, sum = 1
4101 11:16:16.131303 9, 0x0, sum = 2
4102 11:16:16.133897 10, 0x0, sum = 3
4103 11:16:16.134466 11, 0x0, sum = 4
4104 11:16:16.134839 best_step = 9
4105 11:16:16.137148
4106 11:16:16.137700 ==
4107 11:16:16.140111 Dram Type= 6, Freq= 0, CH_0, rank 0
4108 11:16:16.143386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4109 11:16:16.143851 ==
4110 11:16:16.144263 RX Vref Scan: 1
4111 11:16:16.144607
4112 11:16:16.146899 RX Vref 0 -> 0, step: 1
4113 11:16:16.147462
4114 11:16:16.150580 RX Delay -195 -> 252, step: 8
4115 11:16:16.151140
4116 11:16:16.153546 Set Vref, RX VrefLevel [Byte0]: 51
4117 11:16:16.157093 [Byte1]: 53
4118 11:16:16.160663
4119 11:16:16.161132 Final RX Vref Byte 0 = 51 to rank0
4120 11:16:16.163955 Final RX Vref Byte 1 = 53 to rank0
4121 11:16:16.166481 Final RX Vref Byte 0 = 51 to rank1
4122 11:16:16.169904 Final RX Vref Byte 1 = 53 to rank1==
4123 11:16:16.173558 Dram Type= 6, Freq= 0, CH_0, rank 0
4124 11:16:16.180354 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4125 11:16:16.180775 ==
4126 11:16:16.181101 DQS Delay:
4127 11:16:16.183317 DQS0 = 0, DQS1 = 0
4128 11:16:16.183837 DQM Delay:
4129 11:16:16.184215 DQM0 = 41, DQM1 = 33
4130 11:16:16.186761 DQ Delay:
4131 11:16:16.189459 DQ0 =44, DQ1 =40, DQ2 =36, DQ3 =36
4132 11:16:16.192959 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4133 11:16:16.196378 DQ8 =24, DQ9 =24, DQ10 =32, DQ11 =28
4134 11:16:16.199536 DQ12 =40, DQ13 =40, DQ14 =40, DQ15 =40
4135 11:16:16.200085
4136 11:16:16.200603
4137 11:16:16.206405 [DQSOSCAuto] RK0, (LSB)MR18= 0x473e, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 396 ps
4138 11:16:16.209881 CH0 RK0: MR19=808, MR18=473E
4139 11:16:16.216467 CH0_RK0: MR19=0x808, MR18=0x473E, DQSOSC=396, MR23=63, INC=167, DEC=111
4140 11:16:16.217029
4141 11:16:16.219320 ----->DramcWriteLeveling(PI) begin...
4142 11:16:16.219739 ==
4143 11:16:16.222891 Dram Type= 6, Freq= 0, CH_0, rank 1
4144 11:16:16.225875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4145 11:16:16.226290 ==
4146 11:16:16.229688 Write leveling (Byte 0): 36 => 36
4147 11:16:16.232900 Write leveling (Byte 1): 32 => 32
4148 11:16:16.236386 DramcWriteLeveling(PI) end<-----
4149 11:16:16.236903
4150 11:16:16.237230 ==
4151 11:16:16.239805 Dram Type= 6, Freq= 0, CH_0, rank 1
4152 11:16:16.242559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4153 11:16:16.246351 ==
4154 11:16:16.246867 [Gating] SW mode calibration
4155 11:16:16.253306 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4156 11:16:16.259421 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4157 11:16:16.262195 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4158 11:16:16.269588 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4159 11:16:16.272962 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4160 11:16:16.275839 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 1)
4161 11:16:16.282055 0 9 16 | B1->B0 | 2e2e 2424 | 1 0 | (1 0) (0 0)
4162 11:16:16.285719 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4163 11:16:16.288734 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4164 11:16:16.295289 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4165 11:16:16.298679 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4166 11:16:16.302257 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4167 11:16:16.308248 0 10 8 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
4168 11:16:16.311720 0 10 12 | B1->B0 | 2625 3535 | 1 0 | (0 0) (0 0)
4169 11:16:16.315391 0 10 16 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
4170 11:16:16.322501 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4171 11:16:16.324814 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4172 11:16:16.328483 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4173 11:16:16.334953 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4174 11:16:16.337914 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4175 11:16:16.341163 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4176 11:16:16.347796 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4177 11:16:16.350742 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4178 11:16:16.354475 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4179 11:16:16.360642 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4180 11:16:16.364279 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4181 11:16:16.367513 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4182 11:16:16.374296 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4183 11:16:16.377609 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4184 11:16:16.381093 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4185 11:16:16.387316 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4186 11:16:16.390592 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4187 11:16:16.393740 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4188 11:16:16.400667 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4189 11:16:16.403693 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4190 11:16:16.407240 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4191 11:16:16.413727 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4192 11:16:16.416969 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4193 11:16:16.420212 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4194 11:16:16.423128 Total UI for P1: 0, mck2ui 16
4195 11:16:16.426407 best dqsien dly found for B0: ( 0, 13, 12)
4196 11:16:16.430220 Total UI for P1: 0, mck2ui 16
4197 11:16:16.433637 best dqsien dly found for B1: ( 0, 13, 14)
4198 11:16:16.440251 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4199 11:16:16.443468 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4200 11:16:16.444119
4201 11:16:16.446215 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4202 11:16:16.449995 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4203 11:16:16.453153 [Gating] SW calibration Done
4204 11:16:16.453707 ==
4205 11:16:16.456090 Dram Type= 6, Freq= 0, CH_0, rank 1
4206 11:16:16.459554 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4207 11:16:16.460156 ==
4208 11:16:16.463899 RX Vref Scan: 0
4209 11:16:16.464531
4210 11:16:16.464902 RX Vref 0 -> 0, step: 1
4211 11:16:16.465245
4212 11:16:16.466208 RX Delay -230 -> 252, step: 16
4213 11:16:16.469459 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4214 11:16:16.476079 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4215 11:16:16.479358 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4216 11:16:16.482764 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4217 11:16:16.486173 iDelay=218, Bit 4, Center 49 (-102 ~ 201) 304
4218 11:16:16.492829 iDelay=218, Bit 5, Center 41 (-118 ~ 201) 320
4219 11:16:16.496083 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4220 11:16:16.499045 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4221 11:16:16.502085 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4222 11:16:16.509427 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4223 11:16:16.512660 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4224 11:16:16.515420 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4225 11:16:16.518850 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4226 11:16:16.525532 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4227 11:16:16.528803 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4228 11:16:16.532584 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4229 11:16:16.533146 ==
4230 11:16:16.535219 Dram Type= 6, Freq= 0, CH_0, rank 1
4231 11:16:16.538798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4232 11:16:16.541896 ==
4233 11:16:16.542461 DQS Delay:
4234 11:16:16.542830 DQS0 = 0, DQS1 = 0
4235 11:16:16.545485 DQM Delay:
4236 11:16:16.546165 DQM0 = 46, DQM1 = 35
4237 11:16:16.548205 DQ Delay:
4238 11:16:16.552196 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4239 11:16:16.552754 DQ4 =49, DQ5 =41, DQ6 =57, DQ7 =57
4240 11:16:16.555148 DQ8 =25, DQ9 =17, DQ10 =41, DQ11 =25
4241 11:16:16.561624 DQ12 =41, DQ13 =41, DQ14 =49, DQ15 =41
4242 11:16:16.562188
4243 11:16:16.562558
4244 11:16:16.562902 ==
4245 11:16:16.565358 Dram Type= 6, Freq= 0, CH_0, rank 1
4246 11:16:16.568458 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4247 11:16:16.569026 ==
4248 11:16:16.569398
4249 11:16:16.569763
4250 11:16:16.571248 TX Vref Scan disable
4251 11:16:16.571793 == TX Byte 0 ==
4252 11:16:16.578592 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
4253 11:16:16.581430 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
4254 11:16:16.584799 == TX Byte 1 ==
4255 11:16:16.588314 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4256 11:16:16.591336 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4257 11:16:16.591902 ==
4258 11:16:16.594521 Dram Type= 6, Freq= 0, CH_0, rank 1
4259 11:16:16.597646 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4260 11:16:16.598113 ==
4261 11:16:16.600857
4262 11:16:16.601313
4263 11:16:16.601678 TX Vref Scan disable
4264 11:16:16.604757 == TX Byte 0 ==
4265 11:16:16.608300 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
4266 11:16:16.614975 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
4267 11:16:16.615545 == TX Byte 1 ==
4268 11:16:16.617808 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4269 11:16:16.624141 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4270 11:16:16.624563
4271 11:16:16.624899 [DATLAT]
4272 11:16:16.625306 Freq=600, CH0 RK1
4273 11:16:16.625781
4274 11:16:16.627530 DATLAT Default: 0x9
4275 11:16:16.630960 0, 0xFFFF, sum = 0
4276 11:16:16.631498 1, 0xFFFF, sum = 0
4277 11:16:16.634315 2, 0xFFFF, sum = 0
4278 11:16:16.634742 3, 0xFFFF, sum = 0
4279 11:16:16.637753 4, 0xFFFF, sum = 0
4280 11:16:16.638180 5, 0xFFFF, sum = 0
4281 11:16:16.641515 6, 0xFFFF, sum = 0
4282 11:16:16.642048 7, 0xFFFF, sum = 0
4283 11:16:16.644005 8, 0x0, sum = 1
4284 11:16:16.644648 9, 0x0, sum = 2
4285 11:16:16.647360 10, 0x0, sum = 3
4286 11:16:16.647786 11, 0x0, sum = 4
4287 11:16:16.648200 best_step = 9
4288 11:16:16.648533
4289 11:16:16.650737 ==
4290 11:16:16.654378 Dram Type= 6, Freq= 0, CH_0, rank 1
4291 11:16:16.657104 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4292 11:16:16.657533 ==
4293 11:16:16.657867 RX Vref Scan: 0
4294 11:16:16.658174
4295 11:16:16.660736 RX Vref 0 -> 0, step: 1
4296 11:16:16.661146
4297 11:16:16.663645 RX Delay -195 -> 252, step: 8
4298 11:16:16.670744 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4299 11:16:16.673794 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4300 11:16:16.677375 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4301 11:16:16.680553 iDelay=205, Bit 3, Center 40 (-107 ~ 188) 296
4302 11:16:16.687182 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4303 11:16:16.690249 iDelay=205, Bit 5, Center 32 (-115 ~ 180) 296
4304 11:16:16.693422 iDelay=205, Bit 6, Center 48 (-99 ~ 196) 296
4305 11:16:16.696921 iDelay=205, Bit 7, Center 48 (-99 ~ 196) 296
4306 11:16:16.700099 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4307 11:16:16.706929 iDelay=205, Bit 9, Center 20 (-139 ~ 180) 320
4308 11:16:16.710117 iDelay=205, Bit 10, Center 36 (-115 ~ 188) 304
4309 11:16:16.713789 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4310 11:16:16.716651 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4311 11:16:16.722899 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4312 11:16:16.726367 iDelay=205, Bit 14, Center 48 (-107 ~ 204) 312
4313 11:16:16.730243 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4314 11:16:16.730771 ==
4315 11:16:16.732980 Dram Type= 6, Freq= 0, CH_0, rank 1
4316 11:16:16.739766 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4317 11:16:16.740349 ==
4318 11:16:16.740686 DQS Delay:
4319 11:16:16.740998 DQS0 = 0, DQS1 = 0
4320 11:16:16.742996 DQM Delay:
4321 11:16:16.743509 DQM0 = 41, DQM1 = 34
4322 11:16:16.746049 DQ Delay:
4323 11:16:16.749487 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4324 11:16:16.752881 DQ4 =44, DQ5 =32, DQ6 =48, DQ7 =48
4325 11:16:16.755865 DQ8 =24, DQ9 =20, DQ10 =36, DQ11 =28
4326 11:16:16.759183 DQ12 =40, DQ13 =40, DQ14 =48, DQ15 =40
4327 11:16:16.759692
4328 11:16:16.760024
4329 11:16:16.766172 [DQSOSCAuto] RK1, (LSB)MR18= 0x423d, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
4330 11:16:16.769129 CH0 RK1: MR19=808, MR18=423D
4331 11:16:16.775465 CH0_RK1: MR19=0x808, MR18=0x423D, DQSOSC=397, MR23=63, INC=166, DEC=110
4332 11:16:16.779040 [RxdqsGatingPostProcess] freq 600
4333 11:16:16.785887 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4334 11:16:16.786443 Pre-setting of DQS Precalculation
4335 11:16:16.792246 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4336 11:16:16.792802 ==
4337 11:16:16.795339 Dram Type= 6, Freq= 0, CH_1, rank 0
4338 11:16:16.798673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4339 11:16:16.799218 ==
4340 11:16:16.805253 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4341 11:16:16.811977 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4342 11:16:16.814725 [CA 0] Center 36 (6~66) winsize 61
4343 11:16:16.818338 [CA 1] Center 36 (6~66) winsize 61
4344 11:16:16.821472 [CA 2] Center 34 (4~65) winsize 62
4345 11:16:16.824853 [CA 3] Center 34 (4~65) winsize 62
4346 11:16:16.827808 [CA 4] Center 34 (4~65) winsize 62
4347 11:16:16.831295 [CA 5] Center 34 (3~65) winsize 63
4348 11:16:16.831834
4349 11:16:16.834913 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4350 11:16:16.835457
4351 11:16:16.837850 [CATrainingPosCal] consider 1 rank data
4352 11:16:16.841543 u2DelayCellTimex100 = 270/100 ps
4353 11:16:16.844691 CA0 delay=36 (6~66),Diff = 2 PI (19 cell)
4354 11:16:16.848369 CA1 delay=36 (6~66),Diff = 2 PI (19 cell)
4355 11:16:16.851079 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
4356 11:16:16.854573 CA3 delay=34 (4~65),Diff = 0 PI (0 cell)
4357 11:16:16.857964 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
4358 11:16:16.864671 CA5 delay=34 (3~65),Diff = 0 PI (0 cell)
4359 11:16:16.865224
4360 11:16:16.867768 CA PerBit enable=1, Macro0, CA PI delay=34
4361 11:16:16.868361
4362 11:16:16.870936 [CBTSetCACLKResult] CA Dly = 34
4363 11:16:16.871387 CS Dly: 4 (0~35)
4364 11:16:16.871742 ==
4365 11:16:16.874382 Dram Type= 6, Freq= 0, CH_1, rank 1
4366 11:16:16.877451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4367 11:16:16.881217 ==
4368 11:16:16.884721 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4369 11:16:16.891191 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4370 11:16:16.894223 [CA 0] Center 35 (5~66) winsize 62
4371 11:16:16.897616 [CA 1] Center 36 (6~66) winsize 61
4372 11:16:16.900476 [CA 2] Center 34 (4~65) winsize 62
4373 11:16:16.903710 [CA 3] Center 33 (3~64) winsize 62
4374 11:16:16.907005 [CA 4] Center 34 (4~64) winsize 61
4375 11:16:16.910933 [CA 5] Center 33 (3~64) winsize 62
4376 11:16:16.911493
4377 11:16:16.913793 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4378 11:16:16.914342
4379 11:16:16.916907 [CATrainingPosCal] consider 2 rank data
4380 11:16:16.920096 u2DelayCellTimex100 = 270/100 ps
4381 11:16:16.923578 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4382 11:16:16.930578 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4383 11:16:16.933079 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4384 11:16:16.937048 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4385 11:16:16.939630 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4386 11:16:16.943269 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4387 11:16:16.943835
4388 11:16:16.946135 CA PerBit enable=1, Macro0, CA PI delay=33
4389 11:16:16.946775
4390 11:16:16.950220 [CBTSetCACLKResult] CA Dly = 33
4391 11:16:16.953470 CS Dly: 4 (0~36)
4392 11:16:16.953921
4393 11:16:16.956262 ----->DramcWriteLeveling(PI) begin...
4394 11:16:16.956716 ==
4395 11:16:16.959383 Dram Type= 6, Freq= 0, CH_1, rank 0
4396 11:16:16.963389 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4397 11:16:16.963923 ==
4398 11:16:16.966598 Write leveling (Byte 0): 30 => 30
4399 11:16:16.969431 Write leveling (Byte 1): 30 => 30
4400 11:16:16.973780 DramcWriteLeveling(PI) end<-----
4401 11:16:16.974303
4402 11:16:16.974637 ==
4403 11:16:16.976378 Dram Type= 6, Freq= 0, CH_1, rank 0
4404 11:16:16.979197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4405 11:16:16.979617 ==
4406 11:16:16.982480 [Gating] SW mode calibration
4407 11:16:16.989100 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4408 11:16:16.995959 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4409 11:16:16.999149 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4410 11:16:17.005727 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4411 11:16:17.009049 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4412 11:16:17.012326 0 9 12 | B1->B0 | 3030 2f2f | 0 0 | (0 0) (0 0)
4413 11:16:17.018607 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4414 11:16:17.022082 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4415 11:16:17.025027 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4416 11:16:17.032130 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4417 11:16:17.035435 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4418 11:16:17.038107 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4419 11:16:17.044563 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4420 11:16:17.048198 0 10 12 | B1->B0 | 3232 3c3c | 0 0 | (0 0) (0 0)
4421 11:16:17.051293 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4422 11:16:17.057740 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4423 11:16:17.061077 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4424 11:16:17.064300 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4425 11:16:17.070721 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4426 11:16:17.074117 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4427 11:16:17.077184 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4428 11:16:17.084227 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4429 11:16:17.087382 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4430 11:16:17.090908 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4431 11:16:17.097533 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4432 11:16:17.101257 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4433 11:16:17.104176 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4434 11:16:17.110357 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4435 11:16:17.113816 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4436 11:16:17.117223 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4437 11:16:17.123721 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4438 11:16:17.126848 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4439 11:16:17.130749 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4440 11:16:17.137333 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4441 11:16:17.140736 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4442 11:16:17.143361 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4443 11:16:17.150264 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4444 11:16:17.153537 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 0)
4445 11:16:17.157166 Total UI for P1: 0, mck2ui 16
4446 11:16:17.159980 best dqsien dly found for B1: ( 0, 13, 10)
4447 11:16:17.163258 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4448 11:16:17.166853 Total UI for P1: 0, mck2ui 16
4449 11:16:17.169503 best dqsien dly found for B0: ( 0, 13, 12)
4450 11:16:17.172779 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4451 11:16:17.176371 best DQS1 dly(MCK, UI, PI) = (0, 13, 10)
4452 11:16:17.176506
4453 11:16:17.182836 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4454 11:16:17.186164 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 10)
4455 11:16:17.189255 [Gating] SW calibration Done
4456 11:16:17.189412 ==
4457 11:16:17.192816 Dram Type= 6, Freq= 0, CH_1, rank 0
4458 11:16:17.196514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4459 11:16:17.196766 ==
4460 11:16:17.196954 RX Vref Scan: 0
4461 11:16:17.197153
4462 11:16:17.199552 RX Vref 0 -> 0, step: 1
4463 11:16:17.199756
4464 11:16:17.202606 RX Delay -230 -> 252, step: 16
4465 11:16:17.206007 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4466 11:16:17.212798 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4467 11:16:17.215976 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4468 11:16:17.219435 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4469 11:16:17.222570 iDelay=218, Bit 4, Center 33 (-134 ~ 201) 336
4470 11:16:17.225556 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4471 11:16:17.232792 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4472 11:16:17.235521 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4473 11:16:17.238942 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4474 11:16:17.242179 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4475 11:16:17.248480 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4476 11:16:17.252072 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4477 11:16:17.255034 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4478 11:16:17.258313 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4479 11:16:17.265350 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4480 11:16:17.268524 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4481 11:16:17.268617 ==
4482 11:16:17.271403 Dram Type= 6, Freq= 0, CH_1, rank 0
4483 11:16:17.274583 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4484 11:16:17.274665 ==
4485 11:16:17.277812 DQS Delay:
4486 11:16:17.277893 DQS0 = 0, DQS1 = 0
4487 11:16:17.281618 DQM Delay:
4488 11:16:17.281701 DQM0 = 42, DQM1 = 37
4489 11:16:17.281765 DQ Delay:
4490 11:16:17.284538 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4491 11:16:17.287909 DQ4 =33, DQ5 =57, DQ6 =49, DQ7 =41
4492 11:16:17.291742 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4493 11:16:17.294944 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =41
4494 11:16:17.295080
4495 11:16:17.295152
4496 11:16:17.298057 ==
4497 11:16:17.298236 Dram Type= 6, Freq= 0, CH_1, rank 0
4498 11:16:17.304828 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4499 11:16:17.305007 ==
4500 11:16:17.305116
4501 11:16:17.305205
4502 11:16:17.307878 TX Vref Scan disable
4503 11:16:17.307985 == TX Byte 0 ==
4504 11:16:17.311582 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4505 11:16:17.317481 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4506 11:16:17.317562 == TX Byte 1 ==
4507 11:16:17.324157 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4508 11:16:17.327385 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4509 11:16:17.327469 ==
4510 11:16:17.330700 Dram Type= 6, Freq= 0, CH_1, rank 0
4511 11:16:17.334142 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4512 11:16:17.334223 ==
4513 11:16:17.334287
4514 11:16:17.334346
4515 11:16:17.337516 TX Vref Scan disable
4516 11:16:17.341171 == TX Byte 0 ==
4517 11:16:17.344167 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4518 11:16:17.347564 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4519 11:16:17.350833 == TX Byte 1 ==
4520 11:16:17.354091 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4521 11:16:17.357283 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4522 11:16:17.357698
4523 11:16:17.360695 [DATLAT]
4524 11:16:17.361105 Freq=600, CH1 RK0
4525 11:16:17.361456
4526 11:16:17.363836 DATLAT Default: 0x9
4527 11:16:17.364449 0, 0xFFFF, sum = 0
4528 11:16:17.367208 1, 0xFFFF, sum = 0
4529 11:16:17.367628 2, 0xFFFF, sum = 0
4530 11:16:17.370328 3, 0xFFFF, sum = 0
4531 11:16:17.370747 4, 0xFFFF, sum = 0
4532 11:16:17.373910 5, 0xFFFF, sum = 0
4533 11:16:17.376984 6, 0xFFFF, sum = 0
4534 11:16:17.377403 7, 0xFFFF, sum = 0
4535 11:16:17.377741 8, 0x0, sum = 1
4536 11:16:17.380450 9, 0x0, sum = 2
4537 11:16:17.381003 10, 0x0, sum = 3
4538 11:16:17.383787 11, 0x0, sum = 4
4539 11:16:17.384290 best_step = 9
4540 11:16:17.384625
4541 11:16:17.384932 ==
4542 11:16:17.386923 Dram Type= 6, Freq= 0, CH_1, rank 0
4543 11:16:17.393844 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4544 11:16:17.394263 ==
4545 11:16:17.394594 RX Vref Scan: 1
4546 11:16:17.394898
4547 11:16:17.396854 RX Vref 0 -> 0, step: 1
4548 11:16:17.397265
4549 11:16:17.399933 RX Delay -179 -> 252, step: 8
4550 11:16:17.400501
4551 11:16:17.403393 Set Vref, RX VrefLevel [Byte0]: 54
4552 11:16:17.406692 [Byte1]: 53
4553 11:16:17.407105
4554 11:16:17.409902 Final RX Vref Byte 0 = 54 to rank0
4555 11:16:17.413292 Final RX Vref Byte 1 = 53 to rank0
4556 11:16:17.416584 Final RX Vref Byte 0 = 54 to rank1
4557 11:16:17.419899 Final RX Vref Byte 1 = 53 to rank1==
4558 11:16:17.423558 Dram Type= 6, Freq= 0, CH_1, rank 0
4559 11:16:17.426399 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4560 11:16:17.429424 ==
4561 11:16:17.429854 DQS Delay:
4562 11:16:17.430220 DQS0 = 0, DQS1 = 0
4563 11:16:17.432731 DQM Delay:
4564 11:16:17.433167 DQM0 = 41, DQM1 = 34
4565 11:16:17.436144 DQ Delay:
4566 11:16:17.436594 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4567 11:16:17.439819 DQ4 =36, DQ5 =48, DQ6 =52, DQ7 =36
4568 11:16:17.443096 DQ8 =24, DQ9 =20, DQ10 =36, DQ11 =28
4569 11:16:17.446027 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =40
4570 11:16:17.446449
4571 11:16:17.449688
4572 11:16:17.456093 [DQSOSCAuto] RK0, (LSB)MR18= 0x2943, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
4573 11:16:17.459076 CH1 RK0: MR19=808, MR18=2943
4574 11:16:17.466027 CH1_RK0: MR19=0x808, MR18=0x2943, DQSOSC=397, MR23=63, INC=166, DEC=110
4575 11:16:17.466452
4576 11:16:17.469842 ----->DramcWriteLeveling(PI) begin...
4577 11:16:17.470315 ==
4578 11:16:17.472594 Dram Type= 6, Freq= 0, CH_1, rank 1
4579 11:16:17.475525 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4580 11:16:17.476020 ==
4581 11:16:17.478893 Write leveling (Byte 0): 29 => 29
4582 11:16:17.482138 Write leveling (Byte 1): 30 => 30
4583 11:16:17.485301 DramcWriteLeveling(PI) end<-----
4584 11:16:17.485861
4585 11:16:17.486344 ==
4586 11:16:17.489008 Dram Type= 6, Freq= 0, CH_1, rank 1
4587 11:16:17.492829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4588 11:16:17.493265 ==
4589 11:16:17.495750 [Gating] SW mode calibration
4590 11:16:17.501781 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4591 11:16:17.508273 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4592 11:16:17.511734 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4593 11:16:17.518305 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4594 11:16:17.521432 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4595 11:16:17.524870 0 9 12 | B1->B0 | 3131 3030 | 0 0 | (1 1) (1 1)
4596 11:16:17.531689 0 9 16 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
4597 11:16:17.534765 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4598 11:16:17.538562 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4599 11:16:17.544640 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4600 11:16:17.547881 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4601 11:16:17.551520 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4602 11:16:17.558092 0 10 8 | B1->B0 | 2323 2525 | 0 1 | (0 0) (0 0)
4603 11:16:17.561071 0 10 12 | B1->B0 | 3030 3e3e | 0 0 | (0 0) (0 0)
4604 11:16:17.564615 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4605 11:16:17.570727 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4606 11:16:17.574146 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4607 11:16:17.577319 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4608 11:16:17.583778 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4609 11:16:17.587544 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4610 11:16:17.590430 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4611 11:16:17.597371 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4612 11:16:17.600828 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4613 11:16:17.603537 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4614 11:16:17.610245 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4615 11:16:17.613548 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4616 11:16:17.616805 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4617 11:16:17.623379 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4618 11:16:17.626894 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4619 11:16:17.630035 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4620 11:16:17.637020 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4621 11:16:17.639848 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4622 11:16:17.643937 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4623 11:16:17.649645 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4624 11:16:17.653382 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4625 11:16:17.656324 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4626 11:16:17.663021 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4627 11:16:17.666475 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4628 11:16:17.669771 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4629 11:16:17.673256 Total UI for P1: 0, mck2ui 16
4630 11:16:17.676454 best dqsien dly found for B0: ( 0, 13, 12)
4631 11:16:17.679621 Total UI for P1: 0, mck2ui 16
4632 11:16:17.683084 best dqsien dly found for B1: ( 0, 13, 12)
4633 11:16:17.686300 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4634 11:16:17.692765 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4635 11:16:17.693212
4636 11:16:17.695749 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4637 11:16:17.699040 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4638 11:16:17.702792 [Gating] SW calibration Done
4639 11:16:17.703215 ==
4640 11:16:17.705593 Dram Type= 6, Freq= 0, CH_1, rank 1
4641 11:16:17.708837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4642 11:16:17.709289 ==
4643 11:16:17.712081 RX Vref Scan: 0
4644 11:16:17.712519
4645 11:16:17.712855 RX Vref 0 -> 0, step: 1
4646 11:16:17.713192
4647 11:16:17.715469 RX Delay -230 -> 252, step: 16
4648 11:16:17.718939 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4649 11:16:17.725402 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4650 11:16:17.728563 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4651 11:16:17.732121 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4652 11:16:17.735590 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4653 11:16:17.742233 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4654 11:16:17.745537 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4655 11:16:17.748214 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4656 11:16:17.751540 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4657 11:16:17.758239 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4658 11:16:17.761565 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4659 11:16:17.764651 iDelay=218, Bit 11, Center 41 (-118 ~ 201) 320
4660 11:16:17.768023 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4661 11:16:17.774568 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4662 11:16:17.778355 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4663 11:16:17.781553 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4664 11:16:17.781986 ==
4665 11:16:17.784461 Dram Type= 6, Freq= 0, CH_1, rank 1
4666 11:16:17.787858 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4667 11:16:17.788474 ==
4668 11:16:17.791040 DQS Delay:
4669 11:16:17.791595 DQS0 = 0, DQS1 = 0
4670 11:16:17.794284 DQM Delay:
4671 11:16:17.794658 DQM0 = 43, DQM1 = 40
4672 11:16:17.797982 DQ Delay:
4673 11:16:17.798522 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4674 11:16:17.801432 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =41
4675 11:16:17.804348 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =41
4676 11:16:17.807564 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4677 11:16:17.811948
4678 11:16:17.812515
4679 11:16:17.812852 ==
4680 11:16:17.814119 Dram Type= 6, Freq= 0, CH_1, rank 1
4681 11:16:17.817470 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4682 11:16:17.817967 ==
4683 11:16:17.818308
4684 11:16:17.818641
4685 11:16:17.820953 TX Vref Scan disable
4686 11:16:17.821391 == TX Byte 0 ==
4687 11:16:17.827084 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4688 11:16:17.830447 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4689 11:16:17.830869 == TX Byte 1 ==
4690 11:16:17.837258 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4691 11:16:17.840555 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4692 11:16:17.841004 ==
4693 11:16:17.843765 Dram Type= 6, Freq= 0, CH_1, rank 1
4694 11:16:17.846965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4695 11:16:17.847516 ==
4696 11:16:17.849990
4697 11:16:17.850641
4698 11:16:17.851131 TX Vref Scan disable
4699 11:16:17.853598 == TX Byte 0 ==
4700 11:16:17.857401 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4701 11:16:17.863894 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4702 11:16:17.864400 == TX Byte 1 ==
4703 11:16:17.866994 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4704 11:16:17.873526 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4705 11:16:17.874057
4706 11:16:17.874546 [DATLAT]
4707 11:16:17.875017 Freq=600, CH1 RK1
4708 11:16:17.875453
4709 11:16:17.877454 DATLAT Default: 0x9
4710 11:16:17.880501 0, 0xFFFF, sum = 0
4711 11:16:17.880931 1, 0xFFFF, sum = 0
4712 11:16:17.883641 2, 0xFFFF, sum = 0
4713 11:16:17.884120 3, 0xFFFF, sum = 0
4714 11:16:17.886535 4, 0xFFFF, sum = 0
4715 11:16:17.886987 5, 0xFFFF, sum = 0
4716 11:16:17.890091 6, 0xFFFF, sum = 0
4717 11:16:17.890665 7, 0xFFFF, sum = 0
4718 11:16:17.893352 8, 0x0, sum = 1
4719 11:16:17.893801 9, 0x0, sum = 2
4720 11:16:17.897071 10, 0x0, sum = 3
4721 11:16:17.897499 11, 0x0, sum = 4
4722 11:16:17.897840 best_step = 9
4723 11:16:17.898153
4724 11:16:17.899957 ==
4725 11:16:17.903073 Dram Type= 6, Freq= 0, CH_1, rank 1
4726 11:16:17.906408 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4727 11:16:17.906853 ==
4728 11:16:17.907192 RX Vref Scan: 0
4729 11:16:17.907515
4730 11:16:17.909705 RX Vref 0 -> 0, step: 1
4731 11:16:17.910146
4732 11:16:17.912849 RX Delay -179 -> 252, step: 8
4733 11:16:17.919682 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4734 11:16:17.922619 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4735 11:16:17.926105 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4736 11:16:17.929386 iDelay=205, Bit 3, Center 32 (-123 ~ 188) 312
4737 11:16:17.936206 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4738 11:16:17.938978 iDelay=205, Bit 5, Center 44 (-115 ~ 204) 320
4739 11:16:17.942517 iDelay=205, Bit 6, Center 48 (-107 ~ 204) 312
4740 11:16:17.945747 iDelay=205, Bit 7, Center 36 (-123 ~ 196) 320
4741 11:16:17.949189 iDelay=205, Bit 8, Center 20 (-139 ~ 180) 320
4742 11:16:17.956111 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4743 11:16:17.958960 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4744 11:16:17.962266 iDelay=205, Bit 11, Center 28 (-131 ~ 188) 320
4745 11:16:17.965352 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4746 11:16:17.972670 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4747 11:16:17.975350 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4748 11:16:17.978638 iDelay=205, Bit 15, Center 44 (-115 ~ 204) 320
4749 11:16:17.979093 ==
4750 11:16:17.982225 Dram Type= 6, Freq= 0, CH_1, rank 1
4751 11:16:17.988773 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4752 11:16:17.989382 ==
4753 11:16:17.989732 DQS Delay:
4754 11:16:17.992136 DQS0 = 0, DQS1 = 0
4755 11:16:17.992560 DQM Delay:
4756 11:16:17.992901 DQM0 = 37, DQM1 = 35
4757 11:16:17.994960 DQ Delay:
4758 11:16:17.998428 DQ0 =40, DQ1 =36, DQ2 =28, DQ3 =32
4759 11:16:18.001539 DQ4 =36, DQ5 =44, DQ6 =48, DQ7 =36
4760 11:16:18.004826 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =28
4761 11:16:18.008962 DQ12 =44, DQ13 =40, DQ14 =44, DQ15 =44
4762 11:16:18.009413
4763 11:16:18.009773
4764 11:16:18.014710 [DQSOSCAuto] RK1, (LSB)MR18= 0x365a, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
4765 11:16:18.017878 CH1 RK1: MR19=808, MR18=365A
4766 11:16:18.024701 CH1_RK1: MR19=0x808, MR18=0x365A, DQSOSC=392, MR23=63, INC=170, DEC=113
4767 11:16:18.027868 [RxdqsGatingPostProcess] freq 600
4768 11:16:18.031397 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4769 11:16:18.034738 Pre-setting of DQS Precalculation
4770 11:16:18.041189 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4771 11:16:18.047843 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4772 11:16:18.054726 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4773 11:16:18.055157
4774 11:16:18.055491
4775 11:16:18.057862 [Calibration Summary] 1200 Mbps
4776 11:16:18.061249 CH 0, Rank 0
4777 11:16:18.061778 SW Impedance : PASS
4778 11:16:18.064380 DUTY Scan : NO K
4779 11:16:18.067400 ZQ Calibration : PASS
4780 11:16:18.067965 Jitter Meter : NO K
4781 11:16:18.070581 CBT Training : PASS
4782 11:16:18.071001 Write leveling : PASS
4783 11:16:18.074184 RX DQS gating : PASS
4784 11:16:18.077235 RX DQ/DQS(RDDQC) : PASS
4785 11:16:18.077676 TX DQ/DQS : PASS
4786 11:16:18.081147 RX DATLAT : PASS
4787 11:16:18.083773 RX DQ/DQS(Engine): PASS
4788 11:16:18.084320 TX OE : NO K
4789 11:16:18.086974 All Pass.
4790 11:16:18.087392
4791 11:16:18.087828 CH 0, Rank 1
4792 11:16:18.090463 SW Impedance : PASS
4793 11:16:18.090910 DUTY Scan : NO K
4794 11:16:18.094156 ZQ Calibration : PASS
4795 11:16:18.097201 Jitter Meter : NO K
4796 11:16:18.097642 CBT Training : PASS
4797 11:16:18.100399 Write leveling : PASS
4798 11:16:18.103472 RX DQS gating : PASS
4799 11:16:18.103911 RX DQ/DQS(RDDQC) : PASS
4800 11:16:18.106846 TX DQ/DQS : PASS
4801 11:16:18.110166 RX DATLAT : PASS
4802 11:16:18.110589 RX DQ/DQS(Engine): PASS
4803 11:16:18.113383 TX OE : NO K
4804 11:16:18.113803 All Pass.
4805 11:16:18.114141
4806 11:16:18.116554 CH 1, Rank 0
4807 11:16:18.116977 SW Impedance : PASS
4808 11:16:18.120221 DUTY Scan : NO K
4809 11:16:18.123536 ZQ Calibration : PASS
4810 11:16:18.124069 Jitter Meter : NO K
4811 11:16:18.127055 CBT Training : PASS
4812 11:16:18.130647 Write leveling : PASS
4813 11:16:18.131102 RX DQS gating : PASS
4814 11:16:18.133392 RX DQ/DQS(RDDQC) : PASS
4815 11:16:18.136521 TX DQ/DQS : PASS
4816 11:16:18.136976 RX DATLAT : PASS
4817 11:16:18.139969 RX DQ/DQS(Engine): PASS
4818 11:16:18.143112 TX OE : NO K
4819 11:16:18.143535 All Pass.
4820 11:16:18.143872
4821 11:16:18.144240 CH 1, Rank 1
4822 11:16:18.146834 SW Impedance : PASS
4823 11:16:18.150279 DUTY Scan : NO K
4824 11:16:18.150817 ZQ Calibration : PASS
4825 11:16:18.152806 Jitter Meter : NO K
4826 11:16:18.156200 CBT Training : PASS
4827 11:16:18.156619 Write leveling : PASS
4828 11:16:18.159246 RX DQS gating : PASS
4829 11:16:18.162835 RX DQ/DQS(RDDQC) : PASS
4830 11:16:18.163298 TX DQ/DQS : PASS
4831 11:16:18.166575 RX DATLAT : PASS
4832 11:16:18.166995 RX DQ/DQS(Engine): PASS
4833 11:16:18.170073 TX OE : NO K
4834 11:16:18.170490 All Pass.
4835 11:16:18.170826
4836 11:16:18.172477 DramC Write-DBI off
4837 11:16:18.176111 PER_BANK_REFRESH: Hybrid Mode
4838 11:16:18.176528 TX_TRACKING: ON
4839 11:16:18.186424 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4840 11:16:18.189341 [FAST_K] Save calibration result to emmc
4841 11:16:18.192609 dramc_set_vcore_voltage set vcore to 662500
4842 11:16:18.195943 Read voltage for 933, 3
4843 11:16:18.196388 Vio18 = 0
4844 11:16:18.199054 Vcore = 662500
4845 11:16:18.199578 Vdram = 0
4846 11:16:18.199919 Vddq = 0
4847 11:16:18.200286 Vmddr = 0
4848 11:16:18.205622 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4849 11:16:18.212410 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4850 11:16:18.212831 MEM_TYPE=3, freq_sel=17
4851 11:16:18.215283 sv_algorithm_assistance_LP4_1600
4852 11:16:18.218990 ============ PULL DRAM RESETB DOWN ============
4853 11:16:18.225568 ========== PULL DRAM RESETB DOWN end =========
4854 11:16:18.228708 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4855 11:16:18.231939 ===================================
4856 11:16:18.234995 LPDDR4 DRAM CONFIGURATION
4857 11:16:18.238637 ===================================
4858 11:16:18.239055 EX_ROW_EN[0] = 0x0
4859 11:16:18.242748 EX_ROW_EN[1] = 0x0
4860 11:16:18.244886 LP4Y_EN = 0x0
4861 11:16:18.245371 WORK_FSP = 0x0
4862 11:16:18.248334 WL = 0x3
4863 11:16:18.248801 RL = 0x3
4864 11:16:18.251665 BL = 0x2
4865 11:16:18.252233 RPST = 0x0
4866 11:16:18.254801 RD_PRE = 0x0
4867 11:16:18.255213 WR_PRE = 0x1
4868 11:16:18.258300 WR_PST = 0x0
4869 11:16:18.258715 DBI_WR = 0x0
4870 11:16:18.261266 DBI_RD = 0x0
4871 11:16:18.261682 OTF = 0x1
4872 11:16:18.264799 ===================================
4873 11:16:18.268006 ===================================
4874 11:16:18.271453 ANA top config
4875 11:16:18.274702 ===================================
4876 11:16:18.275116 DLL_ASYNC_EN = 0
4877 11:16:18.278146 ALL_SLAVE_EN = 1
4878 11:16:18.281436 NEW_RANK_MODE = 1
4879 11:16:18.285042 DLL_IDLE_MODE = 1
4880 11:16:18.288267 LP45_APHY_COMB_EN = 1
4881 11:16:18.288680 TX_ODT_DIS = 1
4882 11:16:18.291077 NEW_8X_MODE = 1
4883 11:16:18.294495 ===================================
4884 11:16:18.298443 ===================================
4885 11:16:18.301125 data_rate = 1866
4886 11:16:18.304369 CKR = 1
4887 11:16:18.307485 DQ_P2S_RATIO = 8
4888 11:16:18.310901 ===================================
4889 11:16:18.314269 CA_P2S_RATIO = 8
4890 11:16:18.314678 DQ_CA_OPEN = 0
4891 11:16:18.317524 DQ_SEMI_OPEN = 0
4892 11:16:18.321256 CA_SEMI_OPEN = 0
4893 11:16:18.324290 CA_FULL_RATE = 0
4894 11:16:18.327117 DQ_CKDIV4_EN = 1
4895 11:16:18.330657 CA_CKDIV4_EN = 1
4896 11:16:18.331102 CA_PREDIV_EN = 0
4897 11:16:18.334175 PH8_DLY = 0
4898 11:16:18.337654 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4899 11:16:18.340343 DQ_AAMCK_DIV = 4
4900 11:16:18.344377 CA_AAMCK_DIV = 4
4901 11:16:18.347408 CA_ADMCK_DIV = 4
4902 11:16:18.350495 DQ_TRACK_CA_EN = 0
4903 11:16:18.350911 CA_PICK = 933
4904 11:16:18.353406 CA_MCKIO = 933
4905 11:16:18.357383 MCKIO_SEMI = 0
4906 11:16:18.360159 PLL_FREQ = 3732
4907 11:16:18.363578 DQ_UI_PI_RATIO = 32
4908 11:16:18.367002 CA_UI_PI_RATIO = 0
4909 11:16:18.370152 ===================================
4910 11:16:18.373174 ===================================
4911 11:16:18.376394 memory_type:LPDDR4
4912 11:16:18.376812 GP_NUM : 10
4913 11:16:18.379897 SRAM_EN : 1
4914 11:16:18.380357 MD32_EN : 0
4915 11:16:18.383572 ===================================
4916 11:16:18.386369 [ANA_INIT] >>>>>>>>>>>>>>
4917 11:16:18.389630 <<<<<< [CONFIGURE PHASE]: ANA_TX
4918 11:16:18.392833 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
4919 11:16:18.396000 ===================================
4920 11:16:18.399141 data_rate = 1866,PCW = 0X8f00
4921 11:16:18.402539 ===================================
4922 11:16:18.406108 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
4923 11:16:18.412194 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4924 11:16:18.415815 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
4925 11:16:18.422102 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
4926 11:16:18.426102 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
4927 11:16:18.429431 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
4928 11:16:18.429598 [ANA_INIT] flow start
4929 11:16:18.432191 [ANA_INIT] PLL >>>>>>>>
4930 11:16:18.435619 [ANA_INIT] PLL <<<<<<<<
4931 11:16:18.438739 [ANA_INIT] MIDPI >>>>>>>>
4932 11:16:18.438909 [ANA_INIT] MIDPI <<<<<<<<
4933 11:16:18.442154 [ANA_INIT] DLL >>>>>>>>
4934 11:16:18.442358 [ANA_INIT] flow end
4935 11:16:18.448325 ============ LP4 DIFF to SE enter ============
4936 11:16:18.452028 ============ LP4 DIFF to SE exit ============
4937 11:16:18.455300 [ANA_INIT] <<<<<<<<<<<<<
4938 11:16:18.458656 [Flow] Enable top DCM control >>>>>
4939 11:16:18.462016 [Flow] Enable top DCM control <<<<<
4940 11:16:18.465033 Enable DLL master slave shuffle
4941 11:16:18.468323 ==============================================================
4942 11:16:18.471523 Gating Mode config
4943 11:16:18.474848 ==============================================================
4944 11:16:18.478577 Config description:
4945 11:16:18.488373 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4946 11:16:18.495328 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4947 11:16:18.498239 SELPH_MODE 0: By rank 1: By Phase
4948 11:16:18.505365 ==============================================================
4949 11:16:18.508901 GAT_TRACK_EN = 1
4950 11:16:18.511547 RX_GATING_MODE = 2
4951 11:16:18.515209 RX_GATING_TRACK_MODE = 2
4952 11:16:18.518145 SELPH_MODE = 1
4953 11:16:18.521431 PICG_EARLY_EN = 1
4954 11:16:18.524707 VALID_LAT_VALUE = 1
4955 11:16:18.527907 ==============================================================
4956 11:16:18.531398 Enter into Gating configuration >>>>
4957 11:16:18.534700 Exit from Gating configuration <<<<
4958 11:16:18.538284 Enter into DVFS_PRE_config >>>>>
4959 11:16:18.551417 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4960 11:16:18.553965 Exit from DVFS_PRE_config <<<<<
4961 11:16:18.557880 Enter into PICG configuration >>>>
4962 11:16:18.558450 Exit from PICG configuration <<<<
4963 11:16:18.560656 [RX_INPUT] configuration >>>>>
4964 11:16:18.563720 [RX_INPUT] configuration <<<<<
4965 11:16:18.570982 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4966 11:16:18.573777 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4967 11:16:18.580469 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4968 11:16:18.586963 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4969 11:16:18.593674 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4970 11:16:18.600326 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4971 11:16:18.603451 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4972 11:16:18.606822 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4973 11:16:18.613828 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4974 11:16:18.616872 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4975 11:16:18.620160 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4976 11:16:18.626310 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4977 11:16:18.629416 ===================================
4978 11:16:18.629879 LPDDR4 DRAM CONFIGURATION
4979 11:16:18.632667 ===================================
4980 11:16:18.637084 EX_ROW_EN[0] = 0x0
4981 11:16:18.639743 EX_ROW_EN[1] = 0x0
4982 11:16:18.640393 LP4Y_EN = 0x0
4983 11:16:18.642994 WORK_FSP = 0x0
4984 11:16:18.643542 WL = 0x3
4985 11:16:18.646008 RL = 0x3
4986 11:16:18.646554 BL = 0x2
4987 11:16:18.649495 RPST = 0x0
4988 11:16:18.650047 RD_PRE = 0x0
4989 11:16:18.652559 WR_PRE = 0x1
4990 11:16:18.653107 WR_PST = 0x0
4991 11:16:18.655776 DBI_WR = 0x0
4992 11:16:18.656268 DBI_RD = 0x0
4993 11:16:18.659090 OTF = 0x1
4994 11:16:18.662182 ===================================
4995 11:16:18.665861 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4996 11:16:18.669284 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4997 11:16:18.675277 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4998 11:16:18.679029 ===================================
4999 11:16:18.679588 LPDDR4 DRAM CONFIGURATION
5000 11:16:18.682006 ===================================
5001 11:16:18.685629 EX_ROW_EN[0] = 0x10
5002 11:16:18.688496 EX_ROW_EN[1] = 0x0
5003 11:16:18.689077 LP4Y_EN = 0x0
5004 11:16:18.691825 WORK_FSP = 0x0
5005 11:16:18.692270 WL = 0x3
5006 11:16:18.695021 RL = 0x3
5007 11:16:18.695433 BL = 0x2
5008 11:16:18.698267 RPST = 0x0
5009 11:16:18.698705 RD_PRE = 0x0
5010 11:16:18.701696 WR_PRE = 0x1
5011 11:16:18.702108 WR_PST = 0x0
5012 11:16:18.705347 DBI_WR = 0x0
5013 11:16:18.705759 DBI_RD = 0x0
5014 11:16:18.708758 OTF = 0x1
5015 11:16:18.711671 ===================================
5016 11:16:18.718300 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5017 11:16:18.721693 nWR fixed to 30
5018 11:16:18.724845 [ModeRegInit_LP4] CH0 RK0
5019 11:16:18.725422 [ModeRegInit_LP4] CH0 RK1
5020 11:16:18.728546 [ModeRegInit_LP4] CH1 RK0
5021 11:16:18.731544 [ModeRegInit_LP4] CH1 RK1
5022 11:16:18.732300 match AC timing 9
5023 11:16:18.738334 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5024 11:16:18.741373 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5025 11:16:18.744945 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5026 11:16:18.751164 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5027 11:16:18.754658 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5028 11:16:18.755211 ==
5029 11:16:18.757958 Dram Type= 6, Freq= 0, CH_0, rank 0
5030 11:16:18.761657 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5031 11:16:18.762121 ==
5032 11:16:18.767530 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5033 11:16:18.774047 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5034 11:16:18.777303 [CA 0] Center 37 (7~68) winsize 62
5035 11:16:18.781881 [CA 1] Center 37 (7~68) winsize 62
5036 11:16:18.783877 [CA 2] Center 34 (4~64) winsize 61
5037 11:16:18.787411 [CA 3] Center 34 (4~64) winsize 61
5038 11:16:18.790443 [CA 4] Center 32 (2~63) winsize 62
5039 11:16:18.794068 [CA 5] Center 32 (2~63) winsize 62
5040 11:16:18.794619
5041 11:16:18.797205 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5042 11:16:18.797705
5043 11:16:18.800654 [CATrainingPosCal] consider 1 rank data
5044 11:16:18.803840 u2DelayCellTimex100 = 270/100 ps
5045 11:16:18.807646 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5046 11:16:18.810299 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5047 11:16:18.814124 CA2 delay=34 (4~64),Diff = 2 PI (12 cell)
5048 11:16:18.820271 CA3 delay=34 (4~64),Diff = 2 PI (12 cell)
5049 11:16:18.823381 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5050 11:16:18.827252 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5051 11:16:18.827806
5052 11:16:18.829869 CA PerBit enable=1, Macro0, CA PI delay=32
5053 11:16:18.830326
5054 11:16:18.833525 [CBTSetCACLKResult] CA Dly = 32
5055 11:16:18.834074 CS Dly: 5 (0~36)
5056 11:16:18.834619 ==
5057 11:16:18.836965 Dram Type= 6, Freq= 0, CH_0, rank 1
5058 11:16:18.843515 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5059 11:16:18.844098 ==
5060 11:16:18.847179 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5061 11:16:18.853148 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5062 11:16:18.856834 [CA 0] Center 37 (7~68) winsize 62
5063 11:16:18.860096 [CA 1] Center 37 (7~68) winsize 62
5064 11:16:18.863956 [CA 2] Center 35 (5~65) winsize 61
5065 11:16:18.866480 [CA 3] Center 34 (4~65) winsize 62
5066 11:16:18.869794 [CA 4] Center 33 (3~64) winsize 62
5067 11:16:18.873078 [CA 5] Center 32 (2~63) winsize 62
5068 11:16:18.873537
5069 11:16:18.876678 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5070 11:16:18.877131
5071 11:16:18.879763 [CATrainingPosCal] consider 2 rank data
5072 11:16:18.884351 u2DelayCellTimex100 = 270/100 ps
5073 11:16:18.886358 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5074 11:16:18.892822 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5075 11:16:18.896268 CA2 delay=34 (5~64),Diff = 2 PI (12 cell)
5076 11:16:18.899385 CA3 delay=34 (4~64),Diff = 2 PI (12 cell)
5077 11:16:18.902592 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5078 11:16:18.906025 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5079 11:16:18.906535
5080 11:16:18.909193 CA PerBit enable=1, Macro0, CA PI delay=32
5081 11:16:18.909738
5082 11:16:18.912862 [CBTSetCACLKResult] CA Dly = 32
5083 11:16:18.915809 CS Dly: 6 (0~39)
5084 11:16:18.916395
5085 11:16:18.919477 ----->DramcWriteLeveling(PI) begin...
5086 11:16:18.920078 ==
5087 11:16:18.922422 Dram Type= 6, Freq= 0, CH_0, rank 0
5088 11:16:18.925734 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5089 11:16:18.926213 ==
5090 11:16:18.929428 Write leveling (Byte 0): 34 => 34
5091 11:16:18.932684 Write leveling (Byte 1): 29 => 29
5092 11:16:18.935920 DramcWriteLeveling(PI) end<-----
5093 11:16:18.936521
5094 11:16:18.936887 ==
5095 11:16:18.938959 Dram Type= 6, Freq= 0, CH_0, rank 0
5096 11:16:18.942867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5097 11:16:18.943429 ==
5098 11:16:18.945507 [Gating] SW mode calibration
5099 11:16:18.952516 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5100 11:16:18.959685 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5101 11:16:18.962518 0 14 0 | B1->B0 | 2323 3131 | 1 0 | (1 1) (0 0)
5102 11:16:18.965494 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5103 11:16:18.971720 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5104 11:16:18.975196 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5105 11:16:18.979020 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5106 11:16:18.985231 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5107 11:16:18.988472 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5108 11:16:18.991749 0 14 28 | B1->B0 | 3434 2e2e | 1 1 | (1 1) (1 0)
5109 11:16:18.998508 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 1) (0 0)
5110 11:16:19.001737 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5111 11:16:19.005104 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5112 11:16:19.012097 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5113 11:16:19.015089 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5114 11:16:19.018017 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5115 11:16:19.025012 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5116 11:16:19.028190 0 15 28 | B1->B0 | 2323 3b3a | 0 1 | (0 0) (0 0)
5117 11:16:19.031347 1 0 0 | B1->B0 | 3636 4646 | 1 0 | (0 0) (0 0)
5118 11:16:19.037965 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5119 11:16:19.041208 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5120 11:16:19.044930 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5121 11:16:19.051300 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5122 11:16:19.054457 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5123 11:16:19.057916 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5124 11:16:19.064471 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5125 11:16:19.067598 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
5126 11:16:19.071823 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5127 11:16:19.077822 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5128 11:16:19.080724 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5129 11:16:19.084321 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5130 11:16:19.091175 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5131 11:16:19.094524 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5132 11:16:19.097427 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5133 11:16:19.104179 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5134 11:16:19.106950 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5135 11:16:19.110323 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5136 11:16:19.117307 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5137 11:16:19.120388 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5138 11:16:19.123480 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5139 11:16:19.130246 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5140 11:16:19.133195 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5141 11:16:19.136937 Total UI for P1: 0, mck2ui 16
5142 11:16:19.140440 best dqsien dly found for B0: ( 1, 2, 26)
5143 11:16:19.144177 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5144 11:16:19.150058 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5145 11:16:19.153399 Total UI for P1: 0, mck2ui 16
5146 11:16:19.157198 best dqsien dly found for B1: ( 1, 2, 30)
5147 11:16:19.160543 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5148 11:16:19.163458 best DQS1 dly(MCK, UI, PI) = (1, 2, 30)
5149 11:16:19.164020
5150 11:16:19.166520 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5151 11:16:19.169870 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 30)
5152 11:16:19.173038 [Gating] SW calibration Done
5153 11:16:19.173496 ==
5154 11:16:19.176608 Dram Type= 6, Freq= 0, CH_0, rank 0
5155 11:16:19.179767 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5156 11:16:19.180388 ==
5157 11:16:19.183191 RX Vref Scan: 0
5158 11:16:19.183750
5159 11:16:19.186516 RX Vref 0 -> 0, step: 1
5160 11:16:19.187071
5161 11:16:19.187438 RX Delay -80 -> 252, step: 8
5162 11:16:19.192776 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5163 11:16:19.196230 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5164 11:16:19.199598 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5165 11:16:19.202810 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5166 11:16:19.206189 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5167 11:16:19.209674 iDelay=208, Bit 5, Center 91 (0 ~ 183) 184
5168 11:16:19.215747 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5169 11:16:19.219486 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5170 11:16:19.222759 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5171 11:16:19.225457 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5172 11:16:19.228734 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5173 11:16:19.235677 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5174 11:16:19.239251 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5175 11:16:19.242301 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5176 11:16:19.245797 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5177 11:16:19.249389 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5178 11:16:19.249950 ==
5179 11:16:19.252539 Dram Type= 6, Freq= 0, CH_0, rank 0
5180 11:16:19.259010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5181 11:16:19.259569 ==
5182 11:16:19.259933 DQS Delay:
5183 11:16:19.262422 DQS0 = 0, DQS1 = 0
5184 11:16:19.262876 DQM Delay:
5185 11:16:19.263237 DQM0 = 100, DQM1 = 88
5186 11:16:19.266286 DQ Delay:
5187 11:16:19.268743 DQ0 =103, DQ1 =99, DQ2 =95, DQ3 =95
5188 11:16:19.272164 DQ4 =103, DQ5 =91, DQ6 =107, DQ7 =107
5189 11:16:19.275487 DQ8 =83, DQ9 =75, DQ10 =87, DQ11 =83
5190 11:16:19.278553 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =95
5191 11:16:19.278965
5192 11:16:19.279309
5193 11:16:19.279616 ==
5194 11:16:19.282138 Dram Type= 6, Freq= 0, CH_0, rank 0
5195 11:16:19.285327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5196 11:16:19.285741 ==
5197 11:16:19.286072
5198 11:16:19.286376
5199 11:16:19.288530 TX Vref Scan disable
5200 11:16:19.292495 == TX Byte 0 ==
5201 11:16:19.295373 Update DQ dly =719 (2 ,6, 15) DQ OEN =(2 ,3)
5202 11:16:19.298644 Update DQM dly =719 (2 ,6, 15) DQM OEN =(2 ,3)
5203 11:16:19.302172 == TX Byte 1 ==
5204 11:16:19.305315 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5205 11:16:19.308454 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5206 11:16:19.308973 ==
5207 11:16:19.311536 Dram Type= 6, Freq= 0, CH_0, rank 0
5208 11:16:19.318110 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5209 11:16:19.318627 ==
5210 11:16:19.319017
5211 11:16:19.319329
5212 11:16:19.319626 TX Vref Scan disable
5213 11:16:19.322453 == TX Byte 0 ==
5214 11:16:19.325257 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5215 11:16:19.331781 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5216 11:16:19.332515 == TX Byte 1 ==
5217 11:16:19.335009 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5218 11:16:19.341990 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5219 11:16:19.342511
5220 11:16:19.342846 [DATLAT]
5221 11:16:19.343155 Freq=933, CH0 RK0
5222 11:16:19.343449
5223 11:16:19.345208 DATLAT Default: 0xd
5224 11:16:19.348383 0, 0xFFFF, sum = 0
5225 11:16:19.348913 1, 0xFFFF, sum = 0
5226 11:16:19.351605 2, 0xFFFF, sum = 0
5227 11:16:19.352164 3, 0xFFFF, sum = 0
5228 11:16:19.355261 4, 0xFFFF, sum = 0
5229 11:16:19.355785 5, 0xFFFF, sum = 0
5230 11:16:19.358374 6, 0xFFFF, sum = 0
5231 11:16:19.358796 7, 0xFFFF, sum = 0
5232 11:16:19.361462 8, 0xFFFF, sum = 0
5233 11:16:19.361882 9, 0xFFFF, sum = 0
5234 11:16:19.364604 10, 0x0, sum = 1
5235 11:16:19.365024 11, 0x0, sum = 2
5236 11:16:19.367923 12, 0x0, sum = 3
5237 11:16:19.368376 13, 0x0, sum = 4
5238 11:16:19.371774 best_step = 11
5239 11:16:19.372372
5240 11:16:19.372709 ==
5241 11:16:19.375001 Dram Type= 6, Freq= 0, CH_0, rank 0
5242 11:16:19.378392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5243 11:16:19.378926 ==
5244 11:16:19.379272 RX Vref Scan: 1
5245 11:16:19.381070
5246 11:16:19.381483 RX Vref 0 -> 0, step: 1
5247 11:16:19.381813
5248 11:16:19.384871 RX Delay -61 -> 252, step: 4
5249 11:16:19.385283
5250 11:16:19.387997 Set Vref, RX VrefLevel [Byte0]: 51
5251 11:16:19.391571 [Byte1]: 53
5252 11:16:19.394655
5253 11:16:19.395079 Final RX Vref Byte 0 = 51 to rank0
5254 11:16:19.397959 Final RX Vref Byte 1 = 53 to rank0
5255 11:16:19.401356 Final RX Vref Byte 0 = 51 to rank1
5256 11:16:19.404894 Final RX Vref Byte 1 = 53 to rank1==
5257 11:16:19.408160 Dram Type= 6, Freq= 0, CH_0, rank 0
5258 11:16:19.414706 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5259 11:16:19.415224 ==
5260 11:16:19.415562 DQS Delay:
5261 11:16:19.417944 DQS0 = 0, DQS1 = 0
5262 11:16:19.418462 DQM Delay:
5263 11:16:19.418798 DQM0 = 98, DQM1 = 87
5264 11:16:19.421426 DQ Delay:
5265 11:16:19.424649 DQ0 =100, DQ1 =98, DQ2 =94, DQ3 =96
5266 11:16:19.427524 DQ4 =100, DQ5 =90, DQ6 =108, DQ7 =104
5267 11:16:19.431394 DQ8 =80, DQ9 =74, DQ10 =88, DQ11 =82
5268 11:16:19.433956 DQ12 =94, DQ13 =90, DQ14 =96, DQ15 =94
5269 11:16:19.434372
5270 11:16:19.434698
5271 11:16:19.440732 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b15, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 413 ps
5272 11:16:19.444184 CH0 RK0: MR19=505, MR18=1B15
5273 11:16:19.450612 CH0_RK0: MR19=0x505, MR18=0x1B15, DQSOSC=413, MR23=63, INC=63, DEC=42
5274 11:16:19.451132
5275 11:16:19.454013 ----->DramcWriteLeveling(PI) begin...
5276 11:16:19.454537 ==
5277 11:16:19.458078 Dram Type= 6, Freq= 0, CH_0, rank 1
5278 11:16:19.460403 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5279 11:16:19.460829 ==
5280 11:16:19.463632 Write leveling (Byte 0): 33 => 33
5281 11:16:19.467190 Write leveling (Byte 1): 31 => 31
5282 11:16:19.470705 DramcWriteLeveling(PI) end<-----
5283 11:16:19.471341
5284 11:16:19.471791 ==
5285 11:16:19.474345 Dram Type= 6, Freq= 0, CH_0, rank 1
5286 11:16:19.480552 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5287 11:16:19.481073 ==
5288 11:16:19.481413 [Gating] SW mode calibration
5289 11:16:19.489892 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5290 11:16:19.493166 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5291 11:16:19.500617 0 14 0 | B1->B0 | 2e2e 3434 | 1 1 | (0 0) (1 1)
5292 11:16:19.503405 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5293 11:16:19.506738 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5294 11:16:19.513128 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5295 11:16:19.516359 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5296 11:16:19.519410 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5297 11:16:19.527046 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
5298 11:16:19.529351 0 14 28 | B1->B0 | 3434 2d2d | 1 1 | (1 1) (1 0)
5299 11:16:19.533052 0 15 0 | B1->B0 | 2f2f 2626 | 0 0 | (0 0) (0 0)
5300 11:16:19.539250 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
5301 11:16:19.542804 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5302 11:16:19.545487 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5303 11:16:19.552996 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5304 11:16:19.555437 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5305 11:16:19.558781 0 15 24 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
5306 11:16:19.565471 0 15 28 | B1->B0 | 2929 3d3d | 0 1 | (0 0) (0 0)
5307 11:16:19.568824 1 0 0 | B1->B0 | 4141 4646 | 0 0 | (0 0) (0 0)
5308 11:16:19.572263 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5309 11:16:19.578934 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5310 11:16:19.581764 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5311 11:16:19.584947 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5312 11:16:19.592191 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5313 11:16:19.595086 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5314 11:16:19.598217 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5315 11:16:19.604953 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5316 11:16:19.608366 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5317 11:16:19.611485 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5318 11:16:19.618216 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5319 11:16:19.621109 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5320 11:16:19.624551 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5321 11:16:19.631821 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5322 11:16:19.634512 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5323 11:16:19.638132 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5324 11:16:19.644971 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5325 11:16:19.647849 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5326 11:16:19.651456 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5327 11:16:19.657838 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5328 11:16:19.660708 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5329 11:16:19.663835 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5330 11:16:19.670974 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5331 11:16:19.674197 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5332 11:16:19.677207 Total UI for P1: 0, mck2ui 16
5333 11:16:19.680606 best dqsien dly found for B0: ( 1, 2, 26)
5334 11:16:19.683915 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5335 11:16:19.686828 Total UI for P1: 0, mck2ui 16
5336 11:16:19.690690 best dqsien dly found for B1: ( 1, 3, 0)
5337 11:16:19.693613 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5338 11:16:19.696881 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5339 11:16:19.700244
5340 11:16:19.703200 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5341 11:16:19.706629 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5342 11:16:19.710518 [Gating] SW calibration Done
5343 11:16:19.710814 ==
5344 11:16:19.713048 Dram Type= 6, Freq= 0, CH_0, rank 1
5345 11:16:19.716970 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5346 11:16:19.717196 ==
5347 11:16:19.717373 RX Vref Scan: 0
5348 11:16:19.719769
5349 11:16:19.719992 RX Vref 0 -> 0, step: 1
5350 11:16:19.720198
5351 11:16:19.722912 RX Delay -80 -> 252, step: 8
5352 11:16:19.726415 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5353 11:16:19.729865 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5354 11:16:19.736733 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5355 11:16:19.739567 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5356 11:16:19.742945 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5357 11:16:19.746181 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5358 11:16:19.749582 iDelay=200, Bit 6, Center 107 (16 ~ 199) 184
5359 11:16:19.752595 iDelay=200, Bit 7, Center 107 (16 ~ 199) 184
5360 11:16:19.759611 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5361 11:16:19.762262 iDelay=200, Bit 9, Center 79 (-8 ~ 167) 176
5362 11:16:19.765489 iDelay=200, Bit 10, Center 87 (-8 ~ 183) 192
5363 11:16:19.768804 iDelay=200, Bit 11, Center 83 (-8 ~ 175) 184
5364 11:16:19.772733 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5365 11:16:19.778666 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5366 11:16:19.781957 iDelay=200, Bit 14, Center 99 (8 ~ 191) 184
5367 11:16:19.785454 iDelay=200, Bit 15, Center 91 (0 ~ 183) 184
5368 11:16:19.785541 ==
5369 11:16:19.788710 Dram Type= 6, Freq= 0, CH_0, rank 1
5370 11:16:19.791820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5371 11:16:19.791928 ==
5372 11:16:19.795032 DQS Delay:
5373 11:16:19.795113 DQS0 = 0, DQS1 = 0
5374 11:16:19.798645 DQM Delay:
5375 11:16:19.798726 DQM0 = 99, DQM1 = 89
5376 11:16:19.798791 DQ Delay:
5377 11:16:19.802203 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =95
5378 11:16:19.804946 DQ4 =103, DQ5 =87, DQ6 =107, DQ7 =107
5379 11:16:19.808346 DQ8 =83, DQ9 =79, DQ10 =87, DQ11 =83
5380 11:16:19.811908 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =91
5381 11:16:19.815003
5382 11:16:19.815084
5383 11:16:19.815148 ==
5384 11:16:19.818020 Dram Type= 6, Freq= 0, CH_0, rank 1
5385 11:16:19.822129 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5386 11:16:19.822211 ==
5387 11:16:19.822275
5388 11:16:19.822333
5389 11:16:19.824904 TX Vref Scan disable
5390 11:16:19.824985 == TX Byte 0 ==
5391 11:16:19.831783 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5392 11:16:19.835049 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5393 11:16:19.835131 == TX Byte 1 ==
5394 11:16:19.841219 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5395 11:16:19.845461 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5396 11:16:19.845542 ==
5397 11:16:19.847942 Dram Type= 6, Freq= 0, CH_0, rank 1
5398 11:16:19.851624 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5399 11:16:19.851707 ==
5400 11:16:19.851772
5401 11:16:19.851830
5402 11:16:19.854701 TX Vref Scan disable
5403 11:16:19.857607 == TX Byte 0 ==
5404 11:16:19.860947 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5405 11:16:19.864455 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5406 11:16:19.868344 == TX Byte 1 ==
5407 11:16:19.871350 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5408 11:16:19.874392 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5409 11:16:19.877954
5410 11:16:19.878037 [DATLAT]
5411 11:16:19.878103 Freq=933, CH0 RK1
5412 11:16:19.878165
5413 11:16:19.880790 DATLAT Default: 0xb
5414 11:16:19.880872 0, 0xFFFF, sum = 0
5415 11:16:19.883932 1, 0xFFFF, sum = 0
5416 11:16:19.884026 2, 0xFFFF, sum = 0
5417 11:16:19.887357 3, 0xFFFF, sum = 0
5418 11:16:19.890564 4, 0xFFFF, sum = 0
5419 11:16:19.890648 5, 0xFFFF, sum = 0
5420 11:16:19.894078 6, 0xFFFF, sum = 0
5421 11:16:19.894162 7, 0xFFFF, sum = 0
5422 11:16:19.897381 8, 0xFFFF, sum = 0
5423 11:16:19.897465 9, 0xFFFF, sum = 0
5424 11:16:19.900810 10, 0x0, sum = 1
5425 11:16:19.900894 11, 0x0, sum = 2
5426 11:16:19.904015 12, 0x0, sum = 3
5427 11:16:19.904121 13, 0x0, sum = 4
5428 11:16:19.904190 best_step = 11
5429 11:16:19.904251
5430 11:16:19.907097 ==
5431 11:16:19.910666 Dram Type= 6, Freq= 0, CH_0, rank 1
5432 11:16:19.913859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5433 11:16:19.913942 ==
5434 11:16:19.914008 RX Vref Scan: 0
5435 11:16:19.914067
5436 11:16:19.917538 RX Vref 0 -> 0, step: 1
5437 11:16:19.917620
5438 11:16:19.920220 RX Delay -53 -> 252, step: 4
5439 11:16:19.923768 iDelay=195, Bit 0, Center 96 (11 ~ 182) 172
5440 11:16:19.930201 iDelay=195, Bit 1, Center 98 (7 ~ 190) 184
5441 11:16:19.933889 iDelay=195, Bit 2, Center 92 (3 ~ 182) 180
5442 11:16:19.937263 iDelay=195, Bit 3, Center 94 (7 ~ 182) 176
5443 11:16:19.940178 iDelay=195, Bit 4, Center 100 (7 ~ 194) 188
5444 11:16:19.943932 iDelay=195, Bit 5, Center 88 (-1 ~ 178) 180
5445 11:16:19.950144 iDelay=195, Bit 6, Center 106 (19 ~ 194) 176
5446 11:16:19.953477 iDelay=195, Bit 7, Center 106 (19 ~ 194) 176
5447 11:16:19.956664 iDelay=195, Bit 8, Center 80 (-9 ~ 170) 180
5448 11:16:19.959761 iDelay=195, Bit 9, Center 76 (-13 ~ 166) 180
5449 11:16:19.963285 iDelay=195, Bit 10, Center 88 (-1 ~ 178) 180
5450 11:16:19.966564 iDelay=195, Bit 11, Center 80 (-9 ~ 170) 180
5451 11:16:19.973248 iDelay=195, Bit 12, Center 92 (3 ~ 182) 180
5452 11:16:19.977045 iDelay=195, Bit 13, Center 90 (-1 ~ 182) 184
5453 11:16:19.982936 iDelay=195, Bit 14, Center 98 (11 ~ 186) 176
5454 11:16:19.983820 iDelay=195, Bit 15, Center 92 (3 ~ 182) 180
5455 11:16:19.983903 ==
5456 11:16:19.986307 Dram Type= 6, Freq= 0, CH_0, rank 1
5457 11:16:19.993302 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5458 11:16:19.993387 ==
5459 11:16:19.993453 DQS Delay:
5460 11:16:19.996086 DQS0 = 0, DQS1 = 0
5461 11:16:19.996183 DQM Delay:
5462 11:16:19.996249 DQM0 = 97, DQM1 = 87
5463 11:16:19.999205 DQ Delay:
5464 11:16:20.002761 DQ0 =96, DQ1 =98, DQ2 =92, DQ3 =94
5465 11:16:20.005958 DQ4 =100, DQ5 =88, DQ6 =106, DQ7 =106
5466 11:16:20.009720 DQ8 =80, DQ9 =76, DQ10 =88, DQ11 =80
5467 11:16:20.012170 DQ12 =92, DQ13 =90, DQ14 =98, DQ15 =92
5468 11:16:20.012252
5469 11:16:20.012316
5470 11:16:20.019292 [DQSOSCAuto] RK1, (LSB)MR18= 0x1411, (MSB)MR19= 0x505, tDQSOscB0 = 416 ps tDQSOscB1 = 415 ps
5471 11:16:20.022461 CH0 RK1: MR19=505, MR18=1411
5472 11:16:20.028734 CH0_RK1: MR19=0x505, MR18=0x1411, DQSOSC=415, MR23=63, INC=62, DEC=41
5473 11:16:20.031885 [RxdqsGatingPostProcess] freq 933
5474 11:16:20.038958 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5475 11:16:20.039046 best DQS0 dly(2T, 0.5T) = (0, 10)
5476 11:16:20.042211 best DQS1 dly(2T, 0.5T) = (0, 10)
5477 11:16:20.045293 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5478 11:16:20.048597 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5479 11:16:20.052426 best DQS0 dly(2T, 0.5T) = (0, 10)
5480 11:16:20.054913 best DQS1 dly(2T, 0.5T) = (0, 11)
5481 11:16:20.058181 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5482 11:16:20.062174 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5483 11:16:20.065031 Pre-setting of DQS Precalculation
5484 11:16:20.071247 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5485 11:16:20.071332 ==
5486 11:16:20.075099 Dram Type= 6, Freq= 0, CH_1, rank 0
5487 11:16:20.078348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5488 11:16:20.078430 ==
5489 11:16:20.085163 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5490 11:16:20.091529 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5491 11:16:20.094718 [CA 0] Center 36 (6~67) winsize 62
5492 11:16:20.098062 [CA 1] Center 36 (6~67) winsize 62
5493 11:16:20.101504 [CA 2] Center 34 (4~65) winsize 62
5494 11:16:20.104972 [CA 3] Center 34 (4~64) winsize 61
5495 11:16:20.107770 [CA 4] Center 34 (4~65) winsize 62
5496 11:16:20.107929 [CA 5] Center 33 (3~64) winsize 62
5497 11:16:20.111121
5498 11:16:20.114482 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5499 11:16:20.114641
5500 11:16:20.117864 [CATrainingPosCal] consider 1 rank data
5501 11:16:20.120890 u2DelayCellTimex100 = 270/100 ps
5502 11:16:20.124518 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5503 11:16:20.127595 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5504 11:16:20.131812 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5505 11:16:20.134483 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5506 11:16:20.137285 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5507 11:16:20.141260 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5508 11:16:20.141400
5509 11:16:20.147488 CA PerBit enable=1, Macro0, CA PI delay=33
5510 11:16:20.147617
5511 11:16:20.147682 [CBTSetCACLKResult] CA Dly = 33
5512 11:16:20.151041 CS Dly: 5 (0~36)
5513 11:16:20.151197 ==
5514 11:16:20.154215 Dram Type= 6, Freq= 0, CH_1, rank 1
5515 11:16:20.157143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5516 11:16:20.157301 ==
5517 11:16:20.164191 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5518 11:16:20.170530 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5519 11:16:20.173770 [CA 0] Center 36 (6~67) winsize 62
5520 11:16:20.176947 [CA 1] Center 36 (6~67) winsize 62
5521 11:16:20.180341 [CA 2] Center 34 (4~65) winsize 62
5522 11:16:20.183496 [CA 3] Center 33 (3~64) winsize 62
5523 11:16:20.186915 [CA 4] Center 33 (3~64) winsize 62
5524 11:16:20.190031 [CA 5] Center 33 (3~64) winsize 62
5525 11:16:20.190176
5526 11:16:20.193869 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5527 11:16:20.194019
5528 11:16:20.196695 [CATrainingPosCal] consider 2 rank data
5529 11:16:20.200528 u2DelayCellTimex100 = 270/100 ps
5530 11:16:20.203310 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5531 11:16:20.206482 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5532 11:16:20.209935 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5533 11:16:20.213256 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5534 11:16:20.219818 CA4 delay=34 (4~64),Diff = 1 PI (6 cell)
5535 11:16:20.222940 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5536 11:16:20.223220
5537 11:16:20.226409 CA PerBit enable=1, Macro0, CA PI delay=33
5538 11:16:20.226784
5539 11:16:20.229777 [CBTSetCACLKResult] CA Dly = 33
5540 11:16:20.230142 CS Dly: 6 (0~38)
5541 11:16:20.230420
5542 11:16:20.233032 ----->DramcWriteLeveling(PI) begin...
5543 11:16:20.233504 ==
5544 11:16:20.236259 Dram Type= 6, Freq= 0, CH_1, rank 0
5545 11:16:20.243562 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5546 11:16:20.244144 ==
5547 11:16:20.246715 Write leveling (Byte 0): 28 => 28
5548 11:16:20.250032 Write leveling (Byte 1): 30 => 30
5549 11:16:20.253365 DramcWriteLeveling(PI) end<-----
5550 11:16:20.253923
5551 11:16:20.254290 ==
5552 11:16:20.256249 Dram Type= 6, Freq= 0, CH_1, rank 0
5553 11:16:20.259521 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5554 11:16:20.259982 ==
5555 11:16:20.262754 [Gating] SW mode calibration
5556 11:16:20.269193 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5557 11:16:20.275920 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5558 11:16:20.279549 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5559 11:16:20.282607 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5560 11:16:20.289485 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5561 11:16:20.292554 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5562 11:16:20.295811 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5563 11:16:20.302210 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5564 11:16:20.305224 0 14 24 | B1->B0 | 3434 3333 | 0 0 | (0 0) (0 0)
5565 11:16:20.308632 0 14 28 | B1->B0 | 2d2d 2525 | 0 0 | (1 0) (1 0)
5566 11:16:20.315318 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5567 11:16:20.318514 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5568 11:16:20.322166 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5569 11:16:20.328727 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5570 11:16:20.331866 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5571 11:16:20.334834 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5572 11:16:20.341742 0 15 24 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (1 1)
5573 11:16:20.345442 0 15 28 | B1->B0 | 3737 3f3f | 0 0 | (0 0) (0 0)
5574 11:16:20.348325 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5575 11:16:20.354908 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5576 11:16:20.358002 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5577 11:16:20.361424 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5578 11:16:20.368503 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5579 11:16:20.371827 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5580 11:16:20.374340 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5581 11:16:20.381624 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5582 11:16:20.384992 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5583 11:16:20.388396 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5584 11:16:20.394659 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5585 11:16:20.397636 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5586 11:16:20.400909 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5587 11:16:20.408160 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5588 11:16:20.410994 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5589 11:16:20.414140 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5590 11:16:20.421269 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5591 11:16:20.424216 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5592 11:16:20.427090 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5593 11:16:20.433930 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5594 11:16:20.437108 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5595 11:16:20.440399 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5596 11:16:20.446995 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5597 11:16:20.450509 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5598 11:16:20.454469 Total UI for P1: 0, mck2ui 16
5599 11:16:20.457370 best dqsien dly found for B0: ( 1, 2, 26)
5600 11:16:20.460494 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5601 11:16:20.463118 Total UI for P1: 0, mck2ui 16
5602 11:16:20.466525 best dqsien dly found for B1: ( 1, 2, 28)
5603 11:16:20.469782 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5604 11:16:20.473247 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5605 11:16:20.473813
5606 11:16:20.480197 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5607 11:16:20.482890 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5608 11:16:20.486581 [Gating] SW calibration Done
5609 11:16:20.487142 ==
5610 11:16:20.489792 Dram Type= 6, Freq= 0, CH_1, rank 0
5611 11:16:20.493044 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5612 11:16:20.493613 ==
5613 11:16:20.493984 RX Vref Scan: 0
5614 11:16:20.496168
5615 11:16:20.496622 RX Vref 0 -> 0, step: 1
5616 11:16:20.496987
5617 11:16:20.499405 RX Delay -80 -> 252, step: 8
5618 11:16:20.503201 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5619 11:16:20.506241 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5620 11:16:20.512257 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5621 11:16:20.515895 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5622 11:16:20.519606 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5623 11:16:20.522058 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5624 11:16:20.525567 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5625 11:16:20.529312 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5626 11:16:20.535613 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5627 11:16:20.538723 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5628 11:16:20.541784 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5629 11:16:20.545319 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5630 11:16:20.549127 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5631 11:16:20.555438 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5632 11:16:20.559478 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5633 11:16:20.561708 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5634 11:16:20.562173 ==
5635 11:16:20.565781 Dram Type= 6, Freq= 0, CH_1, rank 0
5636 11:16:20.568310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5637 11:16:20.568782 ==
5638 11:16:20.571384 DQS Delay:
5639 11:16:20.571845 DQS0 = 0, DQS1 = 0
5640 11:16:20.574934 DQM Delay:
5641 11:16:20.575500 DQM0 = 99, DQM1 = 95
5642 11:16:20.575875 DQ Delay:
5643 11:16:20.578228 DQ0 =103, DQ1 =95, DQ2 =87, DQ3 =99
5644 11:16:20.582124 DQ4 =95, DQ5 =111, DQ6 =107, DQ7 =99
5645 11:16:20.585028 DQ8 =79, DQ9 =87, DQ10 =95, DQ11 =87
5646 11:16:20.591842 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5647 11:16:20.592451
5648 11:16:20.592824
5649 11:16:20.593172 ==
5650 11:16:20.594813 Dram Type= 6, Freq= 0, CH_1, rank 0
5651 11:16:20.598179 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5652 11:16:20.598750 ==
5653 11:16:20.599128
5654 11:16:20.599473
5655 11:16:20.601098 TX Vref Scan disable
5656 11:16:20.601674 == TX Byte 0 ==
5657 11:16:20.608320 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5658 11:16:20.611047 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5659 11:16:20.614541 == TX Byte 1 ==
5660 11:16:20.617931 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5661 11:16:20.620964 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5662 11:16:20.621431 ==
5663 11:16:20.623964 Dram Type= 6, Freq= 0, CH_1, rank 0
5664 11:16:20.627804 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5665 11:16:20.630828 ==
5666 11:16:20.631311
5667 11:16:20.631680
5668 11:16:20.632025 TX Vref Scan disable
5669 11:16:20.634343 == TX Byte 0 ==
5670 11:16:20.637964 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5671 11:16:20.644378 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5672 11:16:20.644931 == TX Byte 1 ==
5673 11:16:20.647694 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5674 11:16:20.654047 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5675 11:16:20.654614
5676 11:16:20.654986 [DATLAT]
5677 11:16:20.655329 Freq=933, CH1 RK0
5678 11:16:20.655661
5679 11:16:20.657742 DATLAT Default: 0xd
5680 11:16:20.660717 0, 0xFFFF, sum = 0
5681 11:16:20.661146 1, 0xFFFF, sum = 0
5682 11:16:20.663796 2, 0xFFFF, sum = 0
5683 11:16:20.664423 3, 0xFFFF, sum = 0
5684 11:16:20.666949 4, 0xFFFF, sum = 0
5685 11:16:20.667390 5, 0xFFFF, sum = 0
5686 11:16:20.670964 6, 0xFFFF, sum = 0
5687 11:16:20.671453 7, 0xFFFF, sum = 0
5688 11:16:20.673895 8, 0xFFFF, sum = 0
5689 11:16:20.674486 9, 0xFFFF, sum = 0
5690 11:16:20.677213 10, 0x0, sum = 1
5691 11:16:20.677652 11, 0x0, sum = 2
5692 11:16:20.680222 12, 0x0, sum = 3
5693 11:16:20.680663 13, 0x0, sum = 4
5694 11:16:20.681102 best_step = 11
5695 11:16:20.684184
5696 11:16:20.684611 ==
5697 11:16:20.686852 Dram Type= 6, Freq= 0, CH_1, rank 0
5698 11:16:20.690313 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5699 11:16:20.690859 ==
5700 11:16:20.691302 RX Vref Scan: 1
5701 11:16:20.691711
5702 11:16:20.693863 RX Vref 0 -> 0, step: 1
5703 11:16:20.694401
5704 11:16:20.696880 RX Delay -61 -> 252, step: 4
5705 11:16:20.697311
5706 11:16:20.700326 Set Vref, RX VrefLevel [Byte0]: 54
5707 11:16:20.703524 [Byte1]: 53
5708 11:16:20.706960
5709 11:16:20.707499 Final RX Vref Byte 0 = 54 to rank0
5710 11:16:20.709923 Final RX Vref Byte 1 = 53 to rank0
5711 11:16:20.713777 Final RX Vref Byte 0 = 54 to rank1
5712 11:16:20.716492 Final RX Vref Byte 1 = 53 to rank1==
5713 11:16:20.720409 Dram Type= 6, Freq= 0, CH_1, rank 0
5714 11:16:20.726802 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5715 11:16:20.727346 ==
5716 11:16:20.727798 DQS Delay:
5717 11:16:20.729978 DQS0 = 0, DQS1 = 0
5718 11:16:20.730517 DQM Delay:
5719 11:16:20.730964 DQM0 = 97, DQM1 = 95
5720 11:16:20.732822 DQ Delay:
5721 11:16:20.736419 DQ0 =104, DQ1 =92, DQ2 =86, DQ3 =96
5722 11:16:20.739968 DQ4 =94, DQ5 =108, DQ6 =108, DQ7 =94
5723 11:16:20.743310 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =88
5724 11:16:20.746155 DQ12 =104, DQ13 =104, DQ14 =102, DQ15 =104
5725 11:16:20.746589
5726 11:16:20.747022
5727 11:16:20.753085 [DQSOSCAuto] RK0, (LSB)MR18= 0x616, (MSB)MR19= 0x505, tDQSOscB0 = 414 ps tDQSOscB1 = 420 ps
5728 11:16:20.756003 CH1 RK0: MR19=505, MR18=616
5729 11:16:20.762913 CH1_RK0: MR19=0x505, MR18=0x616, DQSOSC=414, MR23=63, INC=63, DEC=42
5730 11:16:20.763470
5731 11:16:20.766025 ----->DramcWriteLeveling(PI) begin...
5732 11:16:20.766465 ==
5733 11:16:20.769282 Dram Type= 6, Freq= 0, CH_1, rank 1
5734 11:16:20.772629 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5735 11:16:20.775798 ==
5736 11:16:20.776357 Write leveling (Byte 0): 26 => 26
5737 11:16:20.779265 Write leveling (Byte 1): 28 => 28
5738 11:16:20.782616 DramcWriteLeveling(PI) end<-----
5739 11:16:20.783143
5740 11:16:20.783483 ==
5741 11:16:20.785590 Dram Type= 6, Freq= 0, CH_1, rank 1
5742 11:16:20.792333 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5743 11:16:20.792875 ==
5744 11:16:20.795275 [Gating] SW mode calibration
5745 11:16:20.801930 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5746 11:16:20.805603 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5747 11:16:20.811934 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5748 11:16:20.815643 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5749 11:16:20.818318 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5750 11:16:20.825091 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5751 11:16:20.828237 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5752 11:16:20.832125 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5753 11:16:20.838846 0 14 24 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 0)
5754 11:16:20.841958 0 14 28 | B1->B0 | 2d2d 2323 | 0 0 | (0 1) (0 0)
5755 11:16:20.845165 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5756 11:16:20.851453 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5757 11:16:20.854916 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5758 11:16:20.857873 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5759 11:16:20.865046 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5760 11:16:20.867733 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5761 11:16:20.870765 0 15 24 | B1->B0 | 2323 2f2f | 0 0 | (0 0) (0 0)
5762 11:16:20.878344 0 15 28 | B1->B0 | 3a3a 4646 | 1 0 | (0 0) (0 0)
5763 11:16:20.880838 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5764 11:16:20.884090 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5765 11:16:20.891131 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5766 11:16:20.894252 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5767 11:16:20.898054 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5768 11:16:20.904413 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5769 11:16:20.907811 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5770 11:16:20.910735 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5771 11:16:20.917725 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5772 11:16:20.920975 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5773 11:16:20.924348 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5774 11:16:20.930691 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5775 11:16:20.933829 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5776 11:16:20.937138 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5777 11:16:20.943574 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5778 11:16:20.946912 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5779 11:16:20.950142 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5780 11:16:20.956883 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5781 11:16:20.960137 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5782 11:16:20.963998 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5783 11:16:20.969694 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5784 11:16:20.972980 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5785 11:16:20.976276 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5786 11:16:20.983130 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5787 11:16:20.983662 Total UI for P1: 0, mck2ui 16
5788 11:16:20.989708 best dqsien dly found for B0: ( 1, 2, 24)
5789 11:16:20.990220 Total UI for P1: 0, mck2ui 16
5790 11:16:20.996645 best dqsien dly found for B1: ( 1, 2, 26)
5791 11:16:20.999388 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5792 11:16:21.003053 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5793 11:16:21.003582
5794 11:16:21.007068 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5795 11:16:21.009113 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5796 11:16:21.012893 [Gating] SW calibration Done
5797 11:16:21.013416 ==
5798 11:16:21.015929 Dram Type= 6, Freq= 0, CH_1, rank 1
5799 11:16:21.019308 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5800 11:16:21.019734 ==
5801 11:16:21.022516 RX Vref Scan: 0
5802 11:16:21.022935
5803 11:16:21.023271 RX Vref 0 -> 0, step: 1
5804 11:16:21.025594
5805 11:16:21.026014 RX Delay -80 -> 252, step: 8
5806 11:16:21.032974 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5807 11:16:21.035802 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5808 11:16:21.039282 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5809 11:16:21.042359 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5810 11:16:21.046195 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5811 11:16:21.049072 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5812 11:16:21.055427 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5813 11:16:21.058844 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5814 11:16:21.062680 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5815 11:16:21.065855 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5816 11:16:21.068268 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5817 11:16:21.075343 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5818 11:16:21.078516 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5819 11:16:21.082242 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5820 11:16:21.084713 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5821 11:16:21.088497 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5822 11:16:21.088919 ==
5823 11:16:21.091843 Dram Type= 6, Freq= 0, CH_1, rank 1
5824 11:16:21.098310 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5825 11:16:21.098840 ==
5826 11:16:21.099232 DQS Delay:
5827 11:16:21.102124 DQS0 = 0, DQS1 = 0
5828 11:16:21.102648 DQM Delay:
5829 11:16:21.102990 DQM0 = 97, DQM1 = 94
5830 11:16:21.104743 DQ Delay:
5831 11:16:21.108188 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5832 11:16:21.111041 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5833 11:16:21.114684 DQ8 =79, DQ9 =83, DQ10 =95, DQ11 =87
5834 11:16:21.117964 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5835 11:16:21.118489
5836 11:16:21.118826
5837 11:16:21.119137 ==
5838 11:16:21.121245 Dram Type= 6, Freq= 0, CH_1, rank 1
5839 11:16:21.124618 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5840 11:16:21.125041 ==
5841 11:16:21.125376
5842 11:16:21.125688
5843 11:16:21.127853 TX Vref Scan disable
5844 11:16:21.131145 == TX Byte 0 ==
5845 11:16:21.134986 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5846 11:16:21.137720 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5847 11:16:21.141001 == TX Byte 1 ==
5848 11:16:21.144470 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5849 11:16:21.147758 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5850 11:16:21.148320 ==
5851 11:16:21.151238 Dram Type= 6, Freq= 0, CH_1, rank 1
5852 11:16:21.157398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5853 11:16:21.157927 ==
5854 11:16:21.158265
5855 11:16:21.158577
5856 11:16:21.158877 TX Vref Scan disable
5857 11:16:21.161838 == TX Byte 0 ==
5858 11:16:21.164808 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5859 11:16:21.171812 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5860 11:16:21.172411 == TX Byte 1 ==
5861 11:16:21.174792 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5862 11:16:21.181995 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5863 11:16:21.182527
5864 11:16:21.182866 [DATLAT]
5865 11:16:21.183180 Freq=933, CH1 RK1
5866 11:16:21.183481
5867 11:16:21.185006 DATLAT Default: 0xb
5868 11:16:21.185429 0, 0xFFFF, sum = 0
5869 11:16:21.187986 1, 0xFFFF, sum = 0
5870 11:16:21.191424 2, 0xFFFF, sum = 0
5871 11:16:21.191950 3, 0xFFFF, sum = 0
5872 11:16:21.194398 4, 0xFFFF, sum = 0
5873 11:16:21.194956 5, 0xFFFF, sum = 0
5874 11:16:21.197895 6, 0xFFFF, sum = 0
5875 11:16:21.198433 7, 0xFFFF, sum = 0
5876 11:16:21.200963 8, 0xFFFF, sum = 0
5877 11:16:21.201390 9, 0xFFFF, sum = 0
5878 11:16:21.204370 10, 0x0, sum = 1
5879 11:16:21.204798 11, 0x0, sum = 2
5880 11:16:21.208690 12, 0x0, sum = 3
5881 11:16:21.209120 13, 0x0, sum = 4
5882 11:16:21.211352 best_step = 11
5883 11:16:21.211920
5884 11:16:21.212292 ==
5885 11:16:21.214298 Dram Type= 6, Freq= 0, CH_1, rank 1
5886 11:16:21.217814 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5887 11:16:21.218359 ==
5888 11:16:21.218705 RX Vref Scan: 0
5889 11:16:21.220863
5890 11:16:21.221282 RX Vref 0 -> 0, step: 1
5891 11:16:21.221618
5892 11:16:21.224140 RX Delay -61 -> 252, step: 4
5893 11:16:21.230800 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
5894 11:16:21.234467 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
5895 11:16:21.237810 iDelay=199, Bit 2, Center 90 (-1 ~ 182) 184
5896 11:16:21.240594 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
5897 11:16:21.244309 iDelay=199, Bit 4, Center 98 (3 ~ 194) 192
5898 11:16:21.250533 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
5899 11:16:21.254051 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
5900 11:16:21.257077 iDelay=199, Bit 7, Center 96 (3 ~ 190) 188
5901 11:16:21.260917 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
5902 11:16:21.264434 iDelay=199, Bit 9, Center 84 (-5 ~ 174) 180
5903 11:16:21.267376 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
5904 11:16:21.273385 iDelay=199, Bit 11, Center 88 (-1 ~ 178) 180
5905 11:16:21.277163 iDelay=199, Bit 12, Center 98 (7 ~ 190) 184
5906 11:16:21.280174 iDelay=199, Bit 13, Center 100 (7 ~ 194) 188
5907 11:16:21.283880 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
5908 11:16:21.287176 iDelay=199, Bit 15, Center 102 (11 ~ 194) 184
5909 11:16:21.290317 ==
5910 11:16:21.293288 Dram Type= 6, Freq= 0, CH_1, rank 1
5911 11:16:21.296575 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5912 11:16:21.297127 ==
5913 11:16:21.297481 DQS Delay:
5914 11:16:21.299484 DQS0 = 0, DQS1 = 0
5915 11:16:21.299902 DQM Delay:
5916 11:16:21.303029 DQM0 = 97, DQM1 = 92
5917 11:16:21.303448 DQ Delay:
5918 11:16:21.306151 DQ0 =102, DQ1 =94, DQ2 =90, DQ3 =92
5919 11:16:21.309532 DQ4 =98, DQ5 =106, DQ6 =104, DQ7 =96
5920 11:16:21.312854 DQ8 =80, DQ9 =84, DQ10 =92, DQ11 =88
5921 11:16:21.316710 DQ12 =98, DQ13 =100, DQ14 =98, DQ15 =102
5922 11:16:21.317229
5923 11:16:21.317569
5924 11:16:21.326837 [DQSOSCAuto] RK1, (LSB)MR18= 0xb22, (MSB)MR19= 0x505, tDQSOscB0 = 411 ps tDQSOscB1 = 418 ps
5925 11:16:21.327382 CH1 RK1: MR19=505, MR18=B22
5926 11:16:21.332708 CH1_RK1: MR19=0x505, MR18=0xB22, DQSOSC=411, MR23=63, INC=64, DEC=42
5927 11:16:21.335696 [RxdqsGatingPostProcess] freq 933
5928 11:16:21.342627 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5929 11:16:21.345928 best DQS0 dly(2T, 0.5T) = (0, 10)
5930 11:16:21.349557 best DQS1 dly(2T, 0.5T) = (0, 10)
5931 11:16:21.352086 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5932 11:16:21.355762 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5933 11:16:21.359535 best DQS0 dly(2T, 0.5T) = (0, 10)
5934 11:16:21.360088 best DQS1 dly(2T, 0.5T) = (0, 10)
5935 11:16:21.362229 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5936 11:16:21.365267 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
5937 11:16:21.368613 Pre-setting of DQS Precalculation
5938 11:16:21.376393 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5939 11:16:21.381909 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
5940 11:16:21.388558 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
5941 11:16:21.389091
5942 11:16:21.389429
5943 11:16:21.392987 [Calibration Summary] 1866 Mbps
5944 11:16:21.395372 CH 0, Rank 0
5945 11:16:21.395903 SW Impedance : PASS
5946 11:16:21.398450 DUTY Scan : NO K
5947 11:16:21.402253 ZQ Calibration : PASS
5948 11:16:21.402781 Jitter Meter : NO K
5949 11:16:21.405095 CBT Training : PASS
5950 11:16:21.405516 Write leveling : PASS
5951 11:16:21.408635 RX DQS gating : PASS
5952 11:16:21.412377 RX DQ/DQS(RDDQC) : PASS
5953 11:16:21.412909 TX DQ/DQS : PASS
5954 11:16:21.414922 RX DATLAT : PASS
5955 11:16:21.418074 RX DQ/DQS(Engine): PASS
5956 11:16:21.418495 TX OE : NO K
5957 11:16:21.421669 All Pass.
5958 11:16:21.422212
5959 11:16:21.422553 CH 0, Rank 1
5960 11:16:21.424653 SW Impedance : PASS
5961 11:16:21.425185 DUTY Scan : NO K
5962 11:16:21.427808 ZQ Calibration : PASS
5963 11:16:21.430926 Jitter Meter : NO K
5964 11:16:21.431347 CBT Training : PASS
5965 11:16:21.434575 Write leveling : PASS
5966 11:16:21.437871 RX DQS gating : PASS
5967 11:16:21.438293 RX DQ/DQS(RDDQC) : PASS
5968 11:16:21.441725 TX DQ/DQS : PASS
5969 11:16:21.444296 RX DATLAT : PASS
5970 11:16:21.444716 RX DQ/DQS(Engine): PASS
5971 11:16:21.447876 TX OE : NO K
5972 11:16:21.448431 All Pass.
5973 11:16:21.448774
5974 11:16:21.451218 CH 1, Rank 0
5975 11:16:21.451744 SW Impedance : PASS
5976 11:16:21.454761 DUTY Scan : NO K
5977 11:16:21.458153 ZQ Calibration : PASS
5978 11:16:21.458674 Jitter Meter : NO K
5979 11:16:21.461121 CBT Training : PASS
5980 11:16:21.464291 Write leveling : PASS
5981 11:16:21.464820 RX DQS gating : PASS
5982 11:16:21.468053 RX DQ/DQS(RDDQC) : PASS
5983 11:16:21.470719 TX DQ/DQS : PASS
5984 11:16:21.471403 RX DATLAT : PASS
5985 11:16:21.473959 RX DQ/DQS(Engine): PASS
5986 11:16:21.477387 TX OE : NO K
5987 11:16:21.477913 All Pass.
5988 11:16:21.478253
5989 11:16:21.478566 CH 1, Rank 1
5990 11:16:21.480234 SW Impedance : PASS
5991 11:16:21.484662 DUTY Scan : NO K
5992 11:16:21.485188 ZQ Calibration : PASS
5993 11:16:21.487014 Jitter Meter : NO K
5994 11:16:21.490329 CBT Training : PASS
5995 11:16:21.490852 Write leveling : PASS
5996 11:16:21.493927 RX DQS gating : PASS
5997 11:16:21.497020 RX DQ/DQS(RDDQC) : PASS
5998 11:16:21.497501 TX DQ/DQS : PASS
5999 11:16:21.500628 RX DATLAT : PASS
6000 11:16:21.501049 RX DQ/DQS(Engine): PASS
6001 11:16:21.503550 TX OE : NO K
6002 11:16:21.504102 All Pass.
6003 11:16:21.504447
6004 11:16:21.506672 DramC Write-DBI off
6005 11:16:21.510330 PER_BANK_REFRESH: Hybrid Mode
6006 11:16:21.510750 TX_TRACKING: ON
6007 11:16:21.520599 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6008 11:16:21.523278 [FAST_K] Save calibration result to emmc
6009 11:16:21.526588 dramc_set_vcore_voltage set vcore to 650000
6010 11:16:21.529764 Read voltage for 400, 6
6011 11:16:21.530186 Vio18 = 0
6012 11:16:21.533398 Vcore = 650000
6013 11:16:21.533927 Vdram = 0
6014 11:16:21.534267 Vddq = 0
6015 11:16:21.534580 Vmddr = 0
6016 11:16:21.540297 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6017 11:16:21.546932 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6018 11:16:21.547460 MEM_TYPE=3, freq_sel=20
6019 11:16:21.549791 sv_algorithm_assistance_LP4_800
6020 11:16:21.553059 ============ PULL DRAM RESETB DOWN ============
6021 11:16:21.559900 ========== PULL DRAM RESETB DOWN end =========
6022 11:16:21.563183 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6023 11:16:21.566149 ===================================
6024 11:16:21.569853 LPDDR4 DRAM CONFIGURATION
6025 11:16:21.572872 ===================================
6026 11:16:21.573294 EX_ROW_EN[0] = 0x0
6027 11:16:21.575895 EX_ROW_EN[1] = 0x0
6028 11:16:21.579323 LP4Y_EN = 0x0
6029 11:16:21.579853 WORK_FSP = 0x0
6030 11:16:21.582675 WL = 0x2
6031 11:16:21.583198 RL = 0x2
6032 11:16:21.586219 BL = 0x2
6033 11:16:21.586752 RPST = 0x0
6034 11:16:21.589255 RD_PRE = 0x0
6035 11:16:21.589782 WR_PRE = 0x1
6036 11:16:21.592893 WR_PST = 0x0
6037 11:16:21.593312 DBI_WR = 0x0
6038 11:16:21.596212 DBI_RD = 0x0
6039 11:16:21.596631 OTF = 0x1
6040 11:16:21.599286 ===================================
6041 11:16:21.602690 ===================================
6042 11:16:21.605769 ANA top config
6043 11:16:21.609194 ===================================
6044 11:16:21.609620 DLL_ASYNC_EN = 0
6045 11:16:21.612543 ALL_SLAVE_EN = 1
6046 11:16:21.615694 NEW_RANK_MODE = 1
6047 11:16:21.619289 DLL_IDLE_MODE = 1
6048 11:16:21.622278 LP45_APHY_COMB_EN = 1
6049 11:16:21.622900 TX_ODT_DIS = 1
6050 11:16:21.625479 NEW_8X_MODE = 1
6051 11:16:21.628789 ===================================
6052 11:16:21.632290 ===================================
6053 11:16:21.635159 data_rate = 800
6054 11:16:21.638587 CKR = 1
6055 11:16:21.642131 DQ_P2S_RATIO = 4
6056 11:16:21.645243 ===================================
6057 11:16:21.648848 CA_P2S_RATIO = 4
6058 11:16:21.649371 DQ_CA_OPEN = 0
6059 11:16:21.651731 DQ_SEMI_OPEN = 1
6060 11:16:21.655685 CA_SEMI_OPEN = 1
6061 11:16:21.658669 CA_FULL_RATE = 0
6062 11:16:21.661697 DQ_CKDIV4_EN = 0
6063 11:16:21.665278 CA_CKDIV4_EN = 1
6064 11:16:21.665805 CA_PREDIV_EN = 0
6065 11:16:21.668266 PH8_DLY = 0
6066 11:16:21.671819 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6067 11:16:21.675278 DQ_AAMCK_DIV = 0
6068 11:16:21.678931 CA_AAMCK_DIV = 0
6069 11:16:21.681288 CA_ADMCK_DIV = 4
6070 11:16:21.681810 DQ_TRACK_CA_EN = 0
6071 11:16:21.684904 CA_PICK = 800
6072 11:16:21.688445 CA_MCKIO = 400
6073 11:16:21.691638 MCKIO_SEMI = 400
6074 11:16:21.694508 PLL_FREQ = 3016
6075 11:16:21.698380 DQ_UI_PI_RATIO = 32
6076 11:16:21.701891 CA_UI_PI_RATIO = 32
6077 11:16:21.704803 ===================================
6078 11:16:21.708187 ===================================
6079 11:16:21.708738 memory_type:LPDDR4
6080 11:16:21.711539 GP_NUM : 10
6081 11:16:21.714219 SRAM_EN : 1
6082 11:16:21.714642 MD32_EN : 0
6083 11:16:21.717547 ===================================
6084 11:16:21.720891 [ANA_INIT] >>>>>>>>>>>>>>
6085 11:16:21.724602 <<<<<< [CONFIGURE PHASE]: ANA_TX
6086 11:16:21.727269 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6087 11:16:21.730927 ===================================
6088 11:16:21.734338 data_rate = 800,PCW = 0X7400
6089 11:16:21.737498 ===================================
6090 11:16:21.740583 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6091 11:16:21.747477 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6092 11:16:21.757110 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6093 11:16:21.760214 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6094 11:16:21.763752 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6095 11:16:21.770053 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6096 11:16:21.770486 [ANA_INIT] flow start
6097 11:16:21.773598 [ANA_INIT] PLL >>>>>>>>
6098 11:16:21.776612 [ANA_INIT] PLL <<<<<<<<
6099 11:16:21.777031 [ANA_INIT] MIDPI >>>>>>>>
6100 11:16:21.779981 [ANA_INIT] MIDPI <<<<<<<<
6101 11:16:21.783288 [ANA_INIT] DLL >>>>>>>>
6102 11:16:21.783708 [ANA_INIT] flow end
6103 11:16:21.786884 ============ LP4 DIFF to SE enter ============
6104 11:16:21.793402 ============ LP4 DIFF to SE exit ============
6105 11:16:21.793937 [ANA_INIT] <<<<<<<<<<<<<
6106 11:16:21.796561 [Flow] Enable top DCM control >>>>>
6107 11:16:21.799785 [Flow] Enable top DCM control <<<<<
6108 11:16:21.803426 Enable DLL master slave shuffle
6109 11:16:21.809782 ==============================================================
6110 11:16:21.813481 Gating Mode config
6111 11:16:21.816372 ==============================================================
6112 11:16:21.819877 Config description:
6113 11:16:21.829221 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6114 11:16:21.836154 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6115 11:16:21.839709 SELPH_MODE 0: By rank 1: By Phase
6116 11:16:21.845902 ==============================================================
6117 11:16:21.849073 GAT_TRACK_EN = 0
6118 11:16:21.851991 RX_GATING_MODE = 2
6119 11:16:21.855846 RX_GATING_TRACK_MODE = 2
6120 11:16:21.859043 SELPH_MODE = 1
6121 11:16:21.863210 PICG_EARLY_EN = 1
6122 11:16:21.863787 VALID_LAT_VALUE = 1
6123 11:16:21.868686 ==============================================================
6124 11:16:21.872487 Enter into Gating configuration >>>>
6125 11:16:21.875444 Exit from Gating configuration <<<<
6126 11:16:21.878363 Enter into DVFS_PRE_config >>>>>
6127 11:16:21.888353 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6128 11:16:21.891878 Exit from DVFS_PRE_config <<<<<
6129 11:16:21.895168 Enter into PICG configuration >>>>
6130 11:16:21.898351 Exit from PICG configuration <<<<
6131 11:16:21.901722 [RX_INPUT] configuration >>>>>
6132 11:16:21.905477 [RX_INPUT] configuration <<<<<
6133 11:16:21.911546 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6134 11:16:21.914794 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6135 11:16:21.921319 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6136 11:16:21.927819 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6137 11:16:21.934234 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6138 11:16:21.942069 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6139 11:16:21.944488 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6140 11:16:21.948010 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6141 11:16:21.950939 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6142 11:16:21.957589 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6143 11:16:21.960900 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6144 11:16:21.963956 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6145 11:16:21.967744 ===================================
6146 11:16:21.970259 LPDDR4 DRAM CONFIGURATION
6147 11:16:21.973599 ===================================
6148 11:16:21.977490 EX_ROW_EN[0] = 0x0
6149 11:16:21.978060 EX_ROW_EN[1] = 0x0
6150 11:16:21.980415 LP4Y_EN = 0x0
6151 11:16:21.980880 WORK_FSP = 0x0
6152 11:16:21.983655 WL = 0x2
6153 11:16:21.984165 RL = 0x2
6154 11:16:21.987365 BL = 0x2
6155 11:16:21.987892 RPST = 0x0
6156 11:16:21.990425 RD_PRE = 0x0
6157 11:16:21.991017 WR_PRE = 0x1
6158 11:16:21.993835 WR_PST = 0x0
6159 11:16:21.997364 DBI_WR = 0x0
6160 11:16:21.997828 DBI_RD = 0x0
6161 11:16:21.999914 OTF = 0x1
6162 11:16:22.003826 ===================================
6163 11:16:22.007341 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6164 11:16:22.010119 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6165 11:16:22.013073 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6166 11:16:22.016795 ===================================
6167 11:16:22.019946 LPDDR4 DRAM CONFIGURATION
6168 11:16:22.023200 ===================================
6169 11:16:22.026365 EX_ROW_EN[0] = 0x10
6170 11:16:22.026792 EX_ROW_EN[1] = 0x0
6171 11:16:22.030457 LP4Y_EN = 0x0
6172 11:16:22.030996 WORK_FSP = 0x0
6173 11:16:22.033070 WL = 0x2
6174 11:16:22.033488 RL = 0x2
6175 11:16:22.036681 BL = 0x2
6176 11:16:22.037099 RPST = 0x0
6177 11:16:22.039666 RD_PRE = 0x0
6178 11:16:22.043355 WR_PRE = 0x1
6179 11:16:22.043888 WR_PST = 0x0
6180 11:16:22.046351 DBI_WR = 0x0
6181 11:16:22.046879 DBI_RD = 0x0
6182 11:16:22.049512 OTF = 0x1
6183 11:16:22.052911 ===================================
6184 11:16:22.059564 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6185 11:16:22.062361 nWR fixed to 30
6186 11:16:22.062894 [ModeRegInit_LP4] CH0 RK0
6187 11:16:22.066250 [ModeRegInit_LP4] CH0 RK1
6188 11:16:22.069039 [ModeRegInit_LP4] CH1 RK0
6189 11:16:22.069558 [ModeRegInit_LP4] CH1 RK1
6190 11:16:22.072640 match AC timing 19
6191 11:16:22.075808 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6192 11:16:22.082348 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6193 11:16:22.085647 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6194 11:16:22.088859 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6195 11:16:22.095194 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6196 11:16:22.095749 ==
6197 11:16:22.098942 Dram Type= 6, Freq= 0, CH_0, rank 0
6198 11:16:22.101778 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6199 11:16:22.102209 ==
6200 11:16:22.108941 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6201 11:16:22.115610 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6202 11:16:22.118404 [CA 0] Center 36 (8~64) winsize 57
6203 11:16:22.121982 [CA 1] Center 36 (8~64) winsize 57
6204 11:16:22.122539 [CA 2] Center 36 (8~64) winsize 57
6205 11:16:22.125041 [CA 3] Center 36 (8~64) winsize 57
6206 11:16:22.128313 [CA 4] Center 36 (8~64) winsize 57
6207 11:16:22.131864 [CA 5] Center 36 (8~64) winsize 57
6208 11:16:22.132357
6209 11:16:22.138184 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6210 11:16:22.138745
6211 11:16:22.141338 [CATrainingPosCal] consider 1 rank data
6212 11:16:22.144708 u2DelayCellTimex100 = 270/100 ps
6213 11:16:22.147727 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6214 11:16:22.151063 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6215 11:16:22.154815 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6216 11:16:22.157831 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6217 11:16:22.160797 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6218 11:16:22.164853 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6219 11:16:22.165419
6220 11:16:22.167810 CA PerBit enable=1, Macro0, CA PI delay=36
6221 11:16:22.168292
6222 11:16:22.170768 [CBTSetCACLKResult] CA Dly = 36
6223 11:16:22.174306 CS Dly: 1 (0~32)
6224 11:16:22.174765 ==
6225 11:16:22.177616 Dram Type= 6, Freq= 0, CH_0, rank 1
6226 11:16:22.180532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6227 11:16:22.180950 ==
6228 11:16:22.187427 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6229 11:16:22.194250 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6230 11:16:22.197481 [CA 0] Center 36 (8~64) winsize 57
6231 11:16:22.197903 [CA 1] Center 36 (8~64) winsize 57
6232 11:16:22.200446 [CA 2] Center 36 (8~64) winsize 57
6233 11:16:22.203710 [CA 3] Center 36 (8~64) winsize 57
6234 11:16:22.207043 [CA 4] Center 36 (8~64) winsize 57
6235 11:16:22.210613 [CA 5] Center 36 (8~64) winsize 57
6236 11:16:22.211179
6237 11:16:22.213754 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6238 11:16:22.214215
6239 11:16:22.220898 [CATrainingPosCal] consider 2 rank data
6240 11:16:22.221464 u2DelayCellTimex100 = 270/100 ps
6241 11:16:22.227024 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6242 11:16:22.229876 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6243 11:16:22.233617 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6244 11:16:22.236814 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6245 11:16:22.240174 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6246 11:16:22.243600 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6247 11:16:22.244201
6248 11:16:22.247281 CA PerBit enable=1, Macro0, CA PI delay=36
6249 11:16:22.247852
6250 11:16:22.249928 [CBTSetCACLKResult] CA Dly = 36
6251 11:16:22.252945 CS Dly: 1 (0~32)
6252 11:16:22.253401
6253 11:16:22.257255 ----->DramcWriteLeveling(PI) begin...
6254 11:16:22.257725 ==
6255 11:16:22.260005 Dram Type= 6, Freq= 0, CH_0, rank 0
6256 11:16:22.263114 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6257 11:16:22.263684 ==
6258 11:16:22.266429 Write leveling (Byte 0): 40 => 8
6259 11:16:22.269835 Write leveling (Byte 1): 40 => 8
6260 11:16:22.272365 DramcWriteLeveling(PI) end<-----
6261 11:16:22.272791
6262 11:16:22.273130 ==
6263 11:16:22.275668 Dram Type= 6, Freq= 0, CH_0, rank 0
6264 11:16:22.279318 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6265 11:16:22.279868 ==
6266 11:16:22.282867 [Gating] SW mode calibration
6267 11:16:22.288990 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6268 11:16:22.295876 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6269 11:16:22.298945 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6270 11:16:22.305846 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6271 11:16:22.308583 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6272 11:16:22.312064 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6273 11:16:22.319087 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6274 11:16:22.321945 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6275 11:16:22.325440 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6276 11:16:22.331823 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6277 11:16:22.335805 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6278 11:16:22.339490 Total UI for P1: 0, mck2ui 16
6279 11:16:22.342082 best dqsien dly found for B0: ( 0, 14, 24)
6280 11:16:22.344869 Total UI for P1: 0, mck2ui 16
6281 11:16:22.348705 best dqsien dly found for B1: ( 0, 14, 24)
6282 11:16:22.351651 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6283 11:16:22.355405 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6284 11:16:22.355975
6285 11:16:22.358491 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6286 11:16:22.361766 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6287 11:16:22.364856 [Gating] SW calibration Done
6288 11:16:22.365444 ==
6289 11:16:22.368262 Dram Type= 6, Freq= 0, CH_0, rank 0
6290 11:16:22.374642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6291 11:16:22.375316 ==
6292 11:16:22.375808 RX Vref Scan: 0
6293 11:16:22.376203
6294 11:16:22.377509 RX Vref 0 -> 0, step: 1
6295 11:16:22.377984
6296 11:16:22.381312 RX Delay -410 -> 252, step: 16
6297 11:16:22.384121 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6298 11:16:22.387644 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6299 11:16:22.394283 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6300 11:16:22.397873 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6301 11:16:22.401184 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6302 11:16:22.404383 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6303 11:16:22.411213 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6304 11:16:22.414304 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6305 11:16:22.417690 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6306 11:16:22.420436 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6307 11:16:22.428390 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6308 11:16:22.431038 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6309 11:16:22.433596 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6310 11:16:22.436963 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6311 11:16:22.443966 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6312 11:16:22.447268 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6313 11:16:22.447719 ==
6314 11:16:22.450892 Dram Type= 6, Freq= 0, CH_0, rank 0
6315 11:16:22.454536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6316 11:16:22.456525 ==
6317 11:16:22.456974 DQS Delay:
6318 11:16:22.457329 DQS0 = 35, DQS1 = 51
6319 11:16:22.460121 DQM Delay:
6320 11:16:22.460621 DQM0 = 4, DQM1 = 9
6321 11:16:22.465566 DQ Delay:
6322 11:16:22.466104 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6323 11:16:22.466902 DQ4 =0, DQ5 =0, DQ6 =16, DQ7 =16
6324 11:16:22.469674 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6325 11:16:22.472912 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6326 11:16:22.473341
6327 11:16:22.473776
6328 11:16:22.474329 ==
6329 11:16:22.476216 Dram Type= 6, Freq= 0, CH_0, rank 0
6330 11:16:22.483175 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6331 11:16:22.483617 ==
6332 11:16:22.483941
6333 11:16:22.484299
6334 11:16:22.484594 TX Vref Scan disable
6335 11:16:22.487070 == TX Byte 0 ==
6336 11:16:22.489221 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6337 11:16:22.492827 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6338 11:16:22.495886 == TX Byte 1 ==
6339 11:16:22.499153 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6340 11:16:22.502980 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6341 11:16:22.506361 ==
6342 11:16:22.509173 Dram Type= 6, Freq= 0, CH_0, rank 0
6343 11:16:22.512486 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6344 11:16:22.512896 ==
6345 11:16:22.513218
6346 11:16:22.513517
6347 11:16:22.515826 TX Vref Scan disable
6348 11:16:22.516371 == TX Byte 0 ==
6349 11:16:22.519281 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6350 11:16:22.525876 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6351 11:16:22.526380 == TX Byte 1 ==
6352 11:16:22.529391 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6353 11:16:22.536149 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6354 11:16:22.536650
6355 11:16:22.536976 [DATLAT]
6356 11:16:22.537275 Freq=400, CH0 RK0
6357 11:16:22.537565
6358 11:16:22.538821 DATLAT Default: 0xf
6359 11:16:22.542816 0, 0xFFFF, sum = 0
6360 11:16:22.543329 1, 0xFFFF, sum = 0
6361 11:16:22.545678 2, 0xFFFF, sum = 0
6362 11:16:22.546090 3, 0xFFFF, sum = 0
6363 11:16:22.549360 4, 0xFFFF, sum = 0
6364 11:16:22.549867 5, 0xFFFF, sum = 0
6365 11:16:22.552669 6, 0xFFFF, sum = 0
6366 11:16:22.553160 7, 0xFFFF, sum = 0
6367 11:16:22.555336 8, 0xFFFF, sum = 0
6368 11:16:22.555759 9, 0xFFFF, sum = 0
6369 11:16:22.558802 10, 0xFFFF, sum = 0
6370 11:16:22.559322 11, 0xFFFF, sum = 0
6371 11:16:22.562161 12, 0xFFFF, sum = 0
6372 11:16:22.562685 13, 0x0, sum = 1
6373 11:16:22.565976 14, 0x0, sum = 2
6374 11:16:22.566498 15, 0x0, sum = 3
6375 11:16:22.568434 16, 0x0, sum = 4
6376 11:16:22.568856 best_step = 14
6377 11:16:22.569191
6378 11:16:22.569501 ==
6379 11:16:22.571793 Dram Type= 6, Freq= 0, CH_0, rank 0
6380 11:16:22.578584 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6381 11:16:22.579121 ==
6382 11:16:22.579467 RX Vref Scan: 1
6383 11:16:22.579778
6384 11:16:22.581787 RX Vref 0 -> 0, step: 1
6385 11:16:22.582206
6386 11:16:22.585455 RX Delay -343 -> 252, step: 8
6387 11:16:22.585970
6388 11:16:22.588244 Set Vref, RX VrefLevel [Byte0]: 51
6389 11:16:22.591595 [Byte1]: 53
6390 11:16:22.592147
6391 11:16:22.595088 Final RX Vref Byte 0 = 51 to rank0
6392 11:16:22.598300 Final RX Vref Byte 1 = 53 to rank0
6393 11:16:22.601755 Final RX Vref Byte 0 = 51 to rank1
6394 11:16:22.604773 Final RX Vref Byte 1 = 53 to rank1==
6395 11:16:22.607979 Dram Type= 6, Freq= 0, CH_0, rank 0
6396 11:16:22.614986 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6397 11:16:22.615511 ==
6398 11:16:22.615849 DQS Delay:
6399 11:16:22.617795 DQS0 = 40, DQS1 = 60
6400 11:16:22.618309 DQM Delay:
6401 11:16:22.618648 DQM0 = 6, DQM1 = 16
6402 11:16:22.620931 DQ Delay:
6403 11:16:22.624716 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =0
6404 11:16:22.625268 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =12
6405 11:16:22.628266 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6406 11:16:22.631515 DQ12 =24, DQ13 =20, DQ14 =24, DQ15 =24
6407 11:16:22.632063
6408 11:16:22.634243
6409 11:16:22.641020 [DQSOSCAuto] RK0, (LSB)MR18= 0x8a7e, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6410 11:16:22.644530 CH0 RK0: MR19=C0C, MR18=8A7E
6411 11:16:22.651074 CH0_RK0: MR19=0xC0C, MR18=0x8A7E, DQSOSC=392, MR23=63, INC=384, DEC=256
6412 11:16:22.651590 ==
6413 11:16:22.654568 Dram Type= 6, Freq= 0, CH_0, rank 1
6414 11:16:22.657386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6415 11:16:22.657810 ==
6416 11:16:22.661070 [Gating] SW mode calibration
6417 11:16:22.667770 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6418 11:16:22.674061 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6419 11:16:22.677802 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6420 11:16:22.680143 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6421 11:16:22.687047 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6422 11:16:22.690059 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6423 11:16:22.693597 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6424 11:16:22.700153 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6425 11:16:22.703604 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6426 11:16:22.706719 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6427 11:16:22.712870 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6428 11:16:22.713417 Total UI for P1: 0, mck2ui 16
6429 11:16:22.720071 best dqsien dly found for B0: ( 0, 14, 24)
6430 11:16:22.720761 Total UI for P1: 0, mck2ui 16
6431 11:16:22.726399 best dqsien dly found for B1: ( 0, 14, 24)
6432 11:16:22.729728 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6433 11:16:22.733063 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6434 11:16:22.733534
6435 11:16:22.736646 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6436 11:16:22.739511 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6437 11:16:22.743294 [Gating] SW calibration Done
6438 11:16:22.743850 ==
6439 11:16:22.746297 Dram Type= 6, Freq= 0, CH_0, rank 1
6440 11:16:22.749702 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6441 11:16:22.750262 ==
6442 11:16:22.753015 RX Vref Scan: 0
6443 11:16:22.753571
6444 11:16:22.755780 RX Vref 0 -> 0, step: 1
6445 11:16:22.756361
6446 11:16:22.756732 RX Delay -410 -> 252, step: 16
6447 11:16:22.763257 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6448 11:16:22.765872 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6449 11:16:22.770074 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6450 11:16:22.775611 iDelay=230, Bit 3, Center -27 (-266 ~ 213) 480
6451 11:16:22.779172 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6452 11:16:22.782718 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6453 11:16:22.785644 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6454 11:16:22.792364 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6455 11:16:22.795850 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6456 11:16:22.798508 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6457 11:16:22.801952 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6458 11:16:22.809142 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6459 11:16:22.812094 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6460 11:16:22.815188 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6461 11:16:22.821801 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6462 11:16:22.825124 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6463 11:16:22.825703 ==
6464 11:16:22.828250 Dram Type= 6, Freq= 0, CH_0, rank 1
6465 11:16:22.831331 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6466 11:16:22.831891 ==
6467 11:16:22.834912 DQS Delay:
6468 11:16:22.835465 DQS0 = 35, DQS1 = 51
6469 11:16:22.835835 DQM Delay:
6470 11:16:22.838713 DQM0 = 8, DQM1 = 10
6471 11:16:22.839259 DQ Delay:
6472 11:16:22.841230 DQ0 =8, DQ1 =8, DQ2 =0, DQ3 =8
6473 11:16:22.844940 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6474 11:16:22.848018 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =0
6475 11:16:22.851449 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6476 11:16:22.852001
6477 11:16:22.852412
6478 11:16:22.852759 ==
6479 11:16:22.854303 Dram Type= 6, Freq= 0, CH_0, rank 1
6480 11:16:22.858435 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6481 11:16:22.861085 ==
6482 11:16:22.861546
6483 11:16:22.861907
6484 11:16:22.862242 TX Vref Scan disable
6485 11:16:22.864590 == TX Byte 0 ==
6486 11:16:22.867571 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6487 11:16:22.871405 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6488 11:16:22.874126 == TX Byte 1 ==
6489 11:16:22.877361 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6490 11:16:22.880700 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6491 11:16:22.881168 ==
6492 11:16:22.884330 Dram Type= 6, Freq= 0, CH_0, rank 1
6493 11:16:22.892141 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6494 11:16:22.892692 ==
6495 11:16:22.893061
6496 11:16:22.893398
6497 11:16:22.893794 TX Vref Scan disable
6498 11:16:22.894844 == TX Byte 0 ==
6499 11:16:22.897406 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6500 11:16:22.900349 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6501 11:16:22.903896 == TX Byte 1 ==
6502 11:16:22.906876 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6503 11:16:22.910178 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6504 11:16:22.910690
6505 11:16:22.913497 [DATLAT]
6506 11:16:22.913997 Freq=400, CH0 RK1
6507 11:16:22.914333
6508 11:16:22.916769 DATLAT Default: 0xe
6509 11:16:22.917276 0, 0xFFFF, sum = 0
6510 11:16:22.920059 1, 0xFFFF, sum = 0
6511 11:16:22.920487 2, 0xFFFF, sum = 0
6512 11:16:22.924670 3, 0xFFFF, sum = 0
6513 11:16:22.925183 4, 0xFFFF, sum = 0
6514 11:16:22.927216 5, 0xFFFF, sum = 0
6515 11:16:22.927760 6, 0xFFFF, sum = 0
6516 11:16:22.930060 7, 0xFFFF, sum = 0
6517 11:16:22.933494 8, 0xFFFF, sum = 0
6518 11:16:22.934009 9, 0xFFFF, sum = 0
6519 11:16:22.936598 10, 0xFFFF, sum = 0
6520 11:16:22.937114 11, 0xFFFF, sum = 0
6521 11:16:22.939934 12, 0xFFFF, sum = 0
6522 11:16:22.940475 13, 0x0, sum = 1
6523 11:16:22.943487 14, 0x0, sum = 2
6524 11:16:22.943999 15, 0x0, sum = 3
6525 11:16:22.946492 16, 0x0, sum = 4
6526 11:16:22.947004 best_step = 14
6527 11:16:22.947340
6528 11:16:22.947649 ==
6529 11:16:22.949823 Dram Type= 6, Freq= 0, CH_0, rank 1
6530 11:16:22.953353 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6531 11:16:22.953868 ==
6532 11:16:22.956904 RX Vref Scan: 0
6533 11:16:22.957410
6534 11:16:22.960406 RX Vref 0 -> 0, step: 1
6535 11:16:22.960916
6536 11:16:22.961255 RX Delay -343 -> 252, step: 8
6537 11:16:22.968635 iDelay=209, Bit 0, Center -36 (-271 ~ 200) 472
6538 11:16:22.971925 iDelay=209, Bit 1, Center -32 (-271 ~ 208) 480
6539 11:16:22.975867 iDelay=209, Bit 2, Center -40 (-279 ~ 200) 480
6540 11:16:22.981494 iDelay=209, Bit 3, Center -36 (-271 ~ 200) 472
6541 11:16:22.985112 iDelay=209, Bit 4, Center -32 (-271 ~ 208) 480
6542 11:16:22.988227 iDelay=209, Bit 5, Center -44 (-279 ~ 192) 472
6543 11:16:22.991545 iDelay=209, Bit 6, Center -28 (-263 ~ 208) 472
6544 11:16:22.998469 iDelay=209, Bit 7, Center -28 (-263 ~ 208) 472
6545 11:16:23.001222 iDelay=209, Bit 8, Center -52 (-295 ~ 192) 488
6546 11:16:23.004671 iDelay=209, Bit 9, Center -60 (-303 ~ 184) 488
6547 11:16:23.007802 iDelay=209, Bit 10, Center -44 (-287 ~ 200) 488
6548 11:16:23.015162 iDelay=209, Bit 11, Center -48 (-287 ~ 192) 480
6549 11:16:23.017472 iDelay=209, Bit 12, Center -40 (-287 ~ 208) 496
6550 11:16:23.021272 iDelay=209, Bit 13, Center -40 (-279 ~ 200) 480
6551 11:16:23.027465 iDelay=209, Bit 14, Center -36 (-279 ~ 208) 488
6552 11:16:23.031091 iDelay=209, Bit 15, Center -36 (-279 ~ 208) 488
6553 11:16:23.031555 ==
6554 11:16:23.033755 Dram Type= 6, Freq= 0, CH_0, rank 1
6555 11:16:23.037663 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6556 11:16:23.038081 ==
6557 11:16:23.040742 DQS Delay:
6558 11:16:23.041281 DQS0 = 44, DQS1 = 60
6559 11:16:23.041676 DQM Delay:
6560 11:16:23.043810 DQM0 = 9, DQM1 = 15
6561 11:16:23.044268 DQ Delay:
6562 11:16:23.047179 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6563 11:16:23.051122 DQ4 =12, DQ5 =0, DQ6 =16, DQ7 =16
6564 11:16:23.054279 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =12
6565 11:16:23.057419 DQ12 =20, DQ13 =20, DQ14 =24, DQ15 =24
6566 11:16:23.057928
6567 11:16:23.058267
6568 11:16:23.067445 [DQSOSCAuto] RK1, (LSB)MR18= 0x7c75, (MSB)MR19= 0xc0c, tDQSOscB0 = 395 ps tDQSOscB1 = 394 ps
6569 11:16:23.067955 CH0 RK1: MR19=C0C, MR18=7C75
6570 11:16:23.073712 CH0_RK1: MR19=0xC0C, MR18=0x7C75, DQSOSC=394, MR23=63, INC=380, DEC=253
6571 11:16:23.077340 [RxdqsGatingPostProcess] freq 400
6572 11:16:23.083587 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6573 11:16:23.086845 best DQS0 dly(2T, 0.5T) = (0, 10)
6574 11:16:23.090204 best DQS1 dly(2T, 0.5T) = (0, 10)
6575 11:16:23.093248 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6576 11:16:23.096701 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6577 11:16:23.100242 best DQS0 dly(2T, 0.5T) = (0, 10)
6578 11:16:23.103230 best DQS1 dly(2T, 0.5T) = (0, 10)
6579 11:16:23.106857 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6580 11:16:23.110271 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6581 11:16:23.110731 Pre-setting of DQS Precalculation
6582 11:16:23.116445 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6583 11:16:23.116906 ==
6584 11:16:23.119497 Dram Type= 6, Freq= 0, CH_1, rank 0
6585 11:16:23.123224 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6586 11:16:23.123785 ==
6587 11:16:23.129523 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6588 11:16:23.136157 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6589 11:16:23.139758 [CA 0] Center 36 (8~64) winsize 57
6590 11:16:23.142777 [CA 1] Center 36 (8~64) winsize 57
6591 11:16:23.146393 [CA 2] Center 36 (8~64) winsize 57
6592 11:16:23.149569 [CA 3] Center 36 (8~64) winsize 57
6593 11:16:23.152849 [CA 4] Center 36 (8~64) winsize 57
6594 11:16:23.155954 [CA 5] Center 36 (8~64) winsize 57
6595 11:16:23.156553
6596 11:16:23.159254 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6597 11:16:23.159814
6598 11:16:23.163070 [CATrainingPosCal] consider 1 rank data
6599 11:16:23.166377 u2DelayCellTimex100 = 270/100 ps
6600 11:16:23.168948 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6601 11:16:23.172686 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6602 11:16:23.175614 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6603 11:16:23.180112 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6604 11:16:23.183012 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6605 11:16:23.185461 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6606 11:16:23.185918
6607 11:16:23.192186 CA PerBit enable=1, Macro0, CA PI delay=36
6608 11:16:23.192742
6609 11:16:23.193109 [CBTSetCACLKResult] CA Dly = 36
6610 11:16:23.195173 CS Dly: 1 (0~32)
6611 11:16:23.195628 ==
6612 11:16:23.199755 Dram Type= 6, Freq= 0, CH_1, rank 1
6613 11:16:23.201963 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6614 11:16:23.202426 ==
6615 11:16:23.208932 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6616 11:16:23.214885 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6617 11:16:23.218208 [CA 0] Center 36 (8~64) winsize 57
6618 11:16:23.221513 [CA 1] Center 36 (8~64) winsize 57
6619 11:16:23.225251 [CA 2] Center 36 (8~64) winsize 57
6620 11:16:23.228541 [CA 3] Center 36 (8~64) winsize 57
6621 11:16:23.232115 [CA 4] Center 36 (8~64) winsize 57
6622 11:16:23.232684 [CA 5] Center 36 (8~64) winsize 57
6623 11:16:23.234939
6624 11:16:23.238036 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6625 11:16:23.238502
6626 11:16:23.241350 [CATrainingPosCal] consider 2 rank data
6627 11:16:23.245914 u2DelayCellTimex100 = 270/100 ps
6628 11:16:23.248003 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6629 11:16:23.251266 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6630 11:16:23.254677 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6631 11:16:23.257670 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6632 11:16:23.261351 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6633 11:16:23.264781 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6634 11:16:23.265351
6635 11:16:23.267743 CA PerBit enable=1, Macro0, CA PI delay=36
6636 11:16:23.271227
6637 11:16:23.271786 [CBTSetCACLKResult] CA Dly = 36
6638 11:16:23.274792 CS Dly: 1 (0~32)
6639 11:16:23.275359
6640 11:16:23.277630 ----->DramcWriteLeveling(PI) begin...
6641 11:16:23.278327 ==
6642 11:16:23.281586 Dram Type= 6, Freq= 0, CH_1, rank 0
6643 11:16:23.284000 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6644 11:16:23.284505 ==
6645 11:16:23.287191 Write leveling (Byte 0): 40 => 8
6646 11:16:23.290905 Write leveling (Byte 1): 40 => 8
6647 11:16:23.293773 DramcWriteLeveling(PI) end<-----
6648 11:16:23.294191
6649 11:16:23.294518 ==
6650 11:16:23.297408 Dram Type= 6, Freq= 0, CH_1, rank 0
6651 11:16:23.300707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6652 11:16:23.301141 ==
6653 11:16:23.304578 [Gating] SW mode calibration
6654 11:16:23.310303 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6655 11:16:23.316985 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6656 11:16:23.320357 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6657 11:16:23.326965 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6658 11:16:23.329884 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6659 11:16:23.333275 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6660 11:16:23.339886 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6661 11:16:23.344015 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6662 11:16:23.346849 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6663 11:16:23.353153 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6664 11:16:23.356991 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6665 11:16:23.359991 Total UI for P1: 0, mck2ui 16
6666 11:16:23.363197 best dqsien dly found for B0: ( 0, 14, 24)
6667 11:16:23.366565 Total UI for P1: 0, mck2ui 16
6668 11:16:23.370119 best dqsien dly found for B1: ( 0, 14, 24)
6669 11:16:23.373103 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6670 11:16:23.376687 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6671 11:16:23.377157
6672 11:16:23.379417 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6673 11:16:23.386267 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6674 11:16:23.386820 [Gating] SW calibration Done
6675 11:16:23.387189 ==
6676 11:16:23.389646 Dram Type= 6, Freq= 0, CH_1, rank 0
6677 11:16:23.395968 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6678 11:16:23.396546 ==
6679 11:16:23.396920 RX Vref Scan: 0
6680 11:16:23.397261
6681 11:16:23.399639 RX Vref 0 -> 0, step: 1
6682 11:16:23.400080
6683 11:16:23.403094 RX Delay -410 -> 252, step: 16
6684 11:16:23.406496 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6685 11:16:23.409905 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6686 11:16:23.416432 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6687 11:16:23.419694 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6688 11:16:23.423140 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6689 11:16:23.427411 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6690 11:16:23.432592 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6691 11:16:23.435960 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6692 11:16:23.439078 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6693 11:16:23.442287 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6694 11:16:23.449084 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6695 11:16:23.452690 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6696 11:16:23.455814 iDelay=230, Bit 12, Center -19 (-266 ~ 229) 496
6697 11:16:23.462228 iDelay=230, Bit 13, Center -19 (-266 ~ 229) 496
6698 11:16:23.465465 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6699 11:16:23.468796 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6700 11:16:23.469545 ==
6701 11:16:23.472462 Dram Type= 6, Freq= 0, CH_1, rank 0
6702 11:16:23.475434 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6703 11:16:23.478808 ==
6704 11:16:23.479264 DQS Delay:
6705 11:16:23.479633 DQS0 = 35, DQS1 = 51
6706 11:16:23.482122 DQM Delay:
6707 11:16:23.482684 DQM0 = 6, DQM1 = 15
6708 11:16:23.485952 DQ Delay:
6709 11:16:23.486553 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =0
6710 11:16:23.488659 DQ4 =0, DQ5 =16, DQ6 =16, DQ7 =0
6711 11:16:23.492205 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6712 11:16:23.495184 DQ12 =32, DQ13 =32, DQ14 =16, DQ15 =16
6713 11:16:23.495665
6714 11:16:23.496059
6715 11:16:23.498171 ==
6716 11:16:23.498629 Dram Type= 6, Freq= 0, CH_1, rank 0
6717 11:16:23.504848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6718 11:16:23.505402 ==
6719 11:16:23.505776
6720 11:16:23.506114
6721 11:16:23.508355 TX Vref Scan disable
6722 11:16:23.508925 == TX Byte 0 ==
6723 11:16:23.511614 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6724 11:16:23.518293 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6725 11:16:23.518859 == TX Byte 1 ==
6726 11:16:23.521135 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6727 11:16:23.527565 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6728 11:16:23.528160 ==
6729 11:16:23.531186 Dram Type= 6, Freq= 0, CH_1, rank 0
6730 11:16:23.534322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6731 11:16:23.534889 ==
6732 11:16:23.535263
6733 11:16:23.535603
6734 11:16:23.538274 TX Vref Scan disable
6735 11:16:23.538736 == TX Byte 0 ==
6736 11:16:23.540631 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6737 11:16:23.548259 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6738 11:16:23.548827 == TX Byte 1 ==
6739 11:16:23.550866 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6740 11:16:23.557508 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6741 11:16:23.558057
6742 11:16:23.558424 [DATLAT]
6743 11:16:23.560569 Freq=400, CH1 RK0
6744 11:16:23.561029
6745 11:16:23.561404 DATLAT Default: 0xf
6746 11:16:23.564542 0, 0xFFFF, sum = 0
6747 11:16:23.565068 1, 0xFFFF, sum = 0
6748 11:16:23.567014 2, 0xFFFF, sum = 0
6749 11:16:23.567497 3, 0xFFFF, sum = 0
6750 11:16:23.570988 4, 0xFFFF, sum = 0
6751 11:16:23.571517 5, 0xFFFF, sum = 0
6752 11:16:23.574429 6, 0xFFFF, sum = 0
6753 11:16:23.574982 7, 0xFFFF, sum = 0
6754 11:16:23.577623 8, 0xFFFF, sum = 0
6755 11:16:23.578048 9, 0xFFFF, sum = 0
6756 11:16:23.580072 10, 0xFFFF, sum = 0
6757 11:16:23.580501 11, 0xFFFF, sum = 0
6758 11:16:23.583794 12, 0xFFFF, sum = 0
6759 11:16:23.587254 13, 0x0, sum = 1
6760 11:16:23.587778 14, 0x0, sum = 2
6761 11:16:23.588174 15, 0x0, sum = 3
6762 11:16:23.590107 16, 0x0, sum = 4
6763 11:16:23.590536 best_step = 14
6764 11:16:23.590869
6765 11:16:23.591181 ==
6766 11:16:23.593443 Dram Type= 6, Freq= 0, CH_1, rank 0
6767 11:16:23.600713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6768 11:16:23.601235 ==
6769 11:16:23.601572 RX Vref Scan: 1
6770 11:16:23.601883
6771 11:16:23.603317 RX Vref 0 -> 0, step: 1
6772 11:16:23.603732
6773 11:16:23.607435 RX Delay -343 -> 252, step: 8
6774 11:16:23.607959
6775 11:16:23.610472 Set Vref, RX VrefLevel [Byte0]: 54
6776 11:16:23.613463 [Byte1]: 53
6777 11:16:23.617233
6778 11:16:23.617758 Final RX Vref Byte 0 = 54 to rank0
6779 11:16:23.620933 Final RX Vref Byte 1 = 53 to rank0
6780 11:16:23.623678 Final RX Vref Byte 0 = 54 to rank1
6781 11:16:23.627223 Final RX Vref Byte 1 = 53 to rank1==
6782 11:16:23.629682 Dram Type= 6, Freq= 0, CH_1, rank 0
6783 11:16:23.636884 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6784 11:16:23.637408 ==
6785 11:16:23.637745 DQS Delay:
6786 11:16:23.640424 DQS0 = 44, DQS1 = 52
6787 11:16:23.640944 DQM Delay:
6788 11:16:23.642984 DQM0 = 10, DQM1 = 10
6789 11:16:23.643505 DQ Delay:
6790 11:16:23.646677 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =12
6791 11:16:23.649338 DQ4 =4, DQ5 =16, DQ6 =20, DQ7 =4
6792 11:16:23.649760 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =4
6793 11:16:23.656286 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6794 11:16:23.656812
6795 11:16:23.657168
6796 11:16:23.662760 [DQSOSCAuto] RK0, (LSB)MR18= 0x6288, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 397 ps
6797 11:16:23.666032 CH1 RK0: MR19=C0C, MR18=6288
6798 11:16:23.673429 CH1_RK0: MR19=0xC0C, MR18=0x6288, DQSOSC=392, MR23=63, INC=384, DEC=256
6799 11:16:23.673955 ==
6800 11:16:23.676276 Dram Type= 6, Freq= 0, CH_1, rank 1
6801 11:16:23.679278 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6802 11:16:23.679703 ==
6803 11:16:23.682871 [Gating] SW mode calibration
6804 11:16:23.688972 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6805 11:16:23.695978 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6806 11:16:23.699594 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6807 11:16:23.703071 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6808 11:16:23.709216 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6809 11:16:23.712361 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6810 11:16:23.715500 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6811 11:16:23.722440 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6812 11:16:23.725165 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6813 11:16:23.728656 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6814 11:16:23.735194 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6815 11:16:23.738730 Total UI for P1: 0, mck2ui 16
6816 11:16:23.741661 best dqsien dly found for B0: ( 0, 14, 24)
6817 11:16:23.744895 Total UI for P1: 0, mck2ui 16
6818 11:16:23.748187 best dqsien dly found for B1: ( 0, 14, 24)
6819 11:16:23.751583 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6820 11:16:23.754705 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6821 11:16:23.755269
6822 11:16:23.758385 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6823 11:16:23.761367 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6824 11:16:23.764638 [Gating] SW calibration Done
6825 11:16:23.765201 ==
6826 11:16:23.767774 Dram Type= 6, Freq= 0, CH_1, rank 1
6827 11:16:23.770948 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6828 11:16:23.775015 ==
6829 11:16:23.775585 RX Vref Scan: 0
6830 11:16:23.775960
6831 11:16:23.777923 RX Vref 0 -> 0, step: 1
6832 11:16:23.778385
6833 11:16:23.780864 RX Delay -410 -> 252, step: 16
6834 11:16:23.784461 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6835 11:16:23.787924 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6836 11:16:23.790850 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6837 11:16:23.797477 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6838 11:16:23.800534 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6839 11:16:23.803941 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6840 11:16:23.807587 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6841 11:16:23.814448 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6842 11:16:23.817666 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6843 11:16:23.820564 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6844 11:16:23.827170 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6845 11:16:23.830486 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6846 11:16:23.833496 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6847 11:16:23.837090 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6848 11:16:23.843685 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6849 11:16:23.846916 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6850 11:16:23.847479 ==
6851 11:16:23.849963 Dram Type= 6, Freq= 0, CH_1, rank 1
6852 11:16:23.854052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6853 11:16:23.854626 ==
6854 11:16:23.856966 DQS Delay:
6855 11:16:23.857532 DQS0 = 43, DQS1 = 51
6856 11:16:23.859844 DQM Delay:
6857 11:16:23.860428 DQM0 = 10, DQM1 = 14
6858 11:16:23.860801 DQ Delay:
6859 11:16:23.863543 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6860 11:16:23.866806 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6861 11:16:23.869700 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6862 11:16:23.873274 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6863 11:16:23.873832
6864 11:16:23.874200
6865 11:16:23.874535 ==
6866 11:16:23.875947 Dram Type= 6, Freq= 0, CH_1, rank 1
6867 11:16:23.882570 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6868 11:16:23.883036 ==
6869 11:16:23.883401
6870 11:16:23.883737
6871 11:16:23.884093 TX Vref Scan disable
6872 11:16:23.886432 == TX Byte 0 ==
6873 11:16:23.889445 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6874 11:16:23.892712 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6875 11:16:23.896425 == TX Byte 1 ==
6876 11:16:23.899335 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6877 11:16:23.902432 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6878 11:16:23.906768 ==
6879 11:16:23.907286 Dram Type= 6, Freq= 0, CH_1, rank 1
6880 11:16:23.912474 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6881 11:16:23.912986 ==
6882 11:16:23.913330
6883 11:16:23.913639
6884 11:16:23.916086 TX Vref Scan disable
6885 11:16:23.916606 == TX Byte 0 ==
6886 11:16:23.919285 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6887 11:16:23.926660 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6888 11:16:23.927179 == TX Byte 1 ==
6889 11:16:23.928658 Update DQ dly =582 (4 ,2, 6) DQ OEN =(3 ,3)
6890 11:16:23.935939 Update DQM dly =582 (4 ,2, 6) DQM OEN =(3 ,3)
6891 11:16:23.936491
6892 11:16:23.936830 [DATLAT]
6893 11:16:23.937142 Freq=400, CH1 RK1
6894 11:16:23.937441
6895 11:16:23.939389 DATLAT Default: 0xe
6896 11:16:23.939907 0, 0xFFFF, sum = 0
6897 11:16:23.942160 1, 0xFFFF, sum = 0
6898 11:16:23.945215 2, 0xFFFF, sum = 0
6899 11:16:23.945740 3, 0xFFFF, sum = 0
6900 11:16:23.948887 4, 0xFFFF, sum = 0
6901 11:16:23.949412 5, 0xFFFF, sum = 0
6902 11:16:23.952870 6, 0xFFFF, sum = 0
6903 11:16:23.953390 7, 0xFFFF, sum = 0
6904 11:16:23.955310 8, 0xFFFF, sum = 0
6905 11:16:23.955833 9, 0xFFFF, sum = 0
6906 11:16:23.959325 10, 0xFFFF, sum = 0
6907 11:16:23.959849 11, 0xFFFF, sum = 0
6908 11:16:23.962079 12, 0xFFFF, sum = 0
6909 11:16:23.962603 13, 0x0, sum = 1
6910 11:16:23.965146 14, 0x0, sum = 2
6911 11:16:23.965671 15, 0x0, sum = 3
6912 11:16:23.968422 16, 0x0, sum = 4
6913 11:16:23.968847 best_step = 14
6914 11:16:23.969178
6915 11:16:23.969488 ==
6916 11:16:23.972214 Dram Type= 6, Freq= 0, CH_1, rank 1
6917 11:16:23.978040 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6918 11:16:23.978568 ==
6919 11:16:23.978907 RX Vref Scan: 0
6920 11:16:23.979217
6921 11:16:23.981118 RX Vref 0 -> 0, step: 1
6922 11:16:23.981727
6923 11:16:23.984639 RX Delay -343 -> 252, step: 8
6924 11:16:23.991062 iDelay=217, Bit 0, Center -36 (-279 ~ 208) 488
6925 11:16:23.994747 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
6926 11:16:23.997597 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
6927 11:16:24.001634 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
6928 11:16:24.008067 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
6929 11:16:24.011543 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
6930 11:16:24.014825 iDelay=217, Bit 6, Center -32 (-279 ~ 216) 496
6931 11:16:24.017825 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
6932 11:16:24.024467 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6933 11:16:24.027700 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
6934 11:16:24.031072 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
6935 11:16:24.037340 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6936 11:16:24.041205 iDelay=217, Bit 12, Center -32 (-271 ~ 208) 480
6937 11:16:24.043860 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6938 11:16:24.047401 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6939 11:16:24.054304 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6940 11:16:24.054863 ==
6941 11:16:24.057595 Dram Type= 6, Freq= 0, CH_1, rank 1
6942 11:16:24.060794 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6943 11:16:24.061265 ==
6944 11:16:24.061636 DQS Delay:
6945 11:16:24.063822 DQS0 = 48, DQS1 = 52
6946 11:16:24.064384 DQM Delay:
6947 11:16:24.067006 DQM0 = 10, DQM1 = 10
6948 11:16:24.067563 DQ Delay:
6949 11:16:24.070010 DQ0 =12, DQ1 =8, DQ2 =0, DQ3 =8
6950 11:16:24.073687 DQ4 =8, DQ5 =20, DQ6 =16, DQ7 =8
6951 11:16:24.077598 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
6952 11:16:24.080365 DQ12 =20, DQ13 =16, DQ14 =16, DQ15 =16
6953 11:16:24.080873
6954 11:16:24.081233
6955 11:16:24.086665 [DQSOSCAuto] RK1, (LSB)MR18= 0x71a8, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 395 ps
6956 11:16:24.090155 CH1 RK1: MR19=C0C, MR18=71A8
6957 11:16:24.096753 CH1_RK1: MR19=0xC0C, MR18=0x71A8, DQSOSC=388, MR23=63, INC=392, DEC=261
6958 11:16:24.099872 [RxdqsGatingPostProcess] freq 400
6959 11:16:24.106932 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6960 11:16:24.109640 best DQS0 dly(2T, 0.5T) = (0, 10)
6961 11:16:24.112747 best DQS1 dly(2T, 0.5T) = (0, 10)
6962 11:16:24.116504 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6963 11:16:24.119685 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6964 11:16:24.122907 best DQS0 dly(2T, 0.5T) = (0, 10)
6965 11:16:24.123425 best DQS1 dly(2T, 0.5T) = (0, 10)
6966 11:16:24.126701 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6967 11:16:24.129680 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6968 11:16:24.132878 Pre-setting of DQS Precalculation
6969 11:16:24.140228 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6970 11:16:24.146074 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
6971 11:16:24.152768 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6972 11:16:24.153329
6973 11:16:24.153689
6974 11:16:24.156191 [Calibration Summary] 800 Mbps
6975 11:16:24.159648 CH 0, Rank 0
6976 11:16:24.160240 SW Impedance : PASS
6977 11:16:24.162626 DUTY Scan : NO K
6978 11:16:24.163184 ZQ Calibration : PASS
6979 11:16:24.165869 Jitter Meter : NO K
6980 11:16:24.168940 CBT Training : PASS
6981 11:16:24.169496 Write leveling : PASS
6982 11:16:24.172269 RX DQS gating : PASS
6983 11:16:24.175291 RX DQ/DQS(RDDQC) : PASS
6984 11:16:24.175748 TX DQ/DQS : PASS
6985 11:16:24.178454 RX DATLAT : PASS
6986 11:16:24.182163 RX DQ/DQS(Engine): PASS
6987 11:16:24.182803 TX OE : NO K
6988 11:16:24.185213 All Pass.
6989 11:16:24.185825
6990 11:16:24.186197 CH 0, Rank 1
6991 11:16:24.188614 SW Impedance : PASS
6992 11:16:24.189070 DUTY Scan : NO K
6993 11:16:24.191839 ZQ Calibration : PASS
6994 11:16:24.195133 Jitter Meter : NO K
6995 11:16:24.195547 CBT Training : PASS
6996 11:16:24.198294 Write leveling : NO K
6997 11:16:24.202025 RX DQS gating : PASS
6998 11:16:24.202436 RX DQ/DQS(RDDQC) : PASS
6999 11:16:24.204774 TX DQ/DQS : PASS
7000 11:16:24.208326 RX DATLAT : PASS
7001 11:16:24.208838 RX DQ/DQS(Engine): PASS
7002 11:16:24.211810 TX OE : NO K
7003 11:16:24.212363 All Pass.
7004 11:16:24.212695
7005 11:16:24.215308 CH 1, Rank 0
7006 11:16:24.215783 SW Impedance : PASS
7007 11:16:24.218349 DUTY Scan : NO K
7008 11:16:24.221691 ZQ Calibration : PASS
7009 11:16:24.222224 Jitter Meter : NO K
7010 11:16:24.224551 CBT Training : PASS
7011 11:16:24.228340 Write leveling : PASS
7012 11:16:24.228751 RX DQS gating : PASS
7013 11:16:24.231360 RX DQ/DQS(RDDQC) : PASS
7014 11:16:24.234913 TX DQ/DQS : PASS
7015 11:16:24.235330 RX DATLAT : PASS
7016 11:16:24.238282 RX DQ/DQS(Engine): PASS
7017 11:16:24.241702 TX OE : NO K
7018 11:16:24.242221 All Pass.
7019 11:16:24.242586
7020 11:16:24.242897 CH 1, Rank 1
7021 11:16:24.244633 SW Impedance : PASS
7022 11:16:24.248087 DUTY Scan : NO K
7023 11:16:24.248597 ZQ Calibration : PASS
7024 11:16:24.251376 Jitter Meter : NO K
7025 11:16:24.251888 CBT Training : PASS
7026 11:16:24.254531 Write leveling : NO K
7027 11:16:24.257681 RX DQS gating : PASS
7028 11:16:24.258122 RX DQ/DQS(RDDQC) : PASS
7029 11:16:24.261007 TX DQ/DQS : PASS
7030 11:16:24.264431 RX DATLAT : PASS
7031 11:16:24.264946 RX DQ/DQS(Engine): PASS
7032 11:16:24.267897 TX OE : NO K
7033 11:16:24.268452 All Pass.
7034 11:16:24.268787
7035 11:16:24.271063 DramC Write-DBI off
7036 11:16:24.274352 PER_BANK_REFRESH: Hybrid Mode
7037 11:16:24.274868 TX_TRACKING: ON
7038 11:16:24.284127 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7039 11:16:24.287272 [FAST_K] Save calibration result to emmc
7040 11:16:24.290672 dramc_set_vcore_voltage set vcore to 725000
7041 11:16:24.294384 Read voltage for 1600, 0
7042 11:16:24.294903 Vio18 = 0
7043 11:16:24.297112 Vcore = 725000
7044 11:16:24.297525 Vdram = 0
7045 11:16:24.297899 Vddq = 0
7046 11:16:24.298380 Vmddr = 0
7047 11:16:24.303629 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7048 11:16:24.310009 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7049 11:16:24.310635 MEM_TYPE=3, freq_sel=13
7050 11:16:24.313548 sv_algorithm_assistance_LP4_3733
7051 11:16:24.316849 ============ PULL DRAM RESETB DOWN ============
7052 11:16:24.323770 ========== PULL DRAM RESETB DOWN end =========
7053 11:16:24.327196 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7054 11:16:24.329891 ===================================
7055 11:16:24.333362 LPDDR4 DRAM CONFIGURATION
7056 11:16:24.337069 ===================================
7057 11:16:24.337582 EX_ROW_EN[0] = 0x0
7058 11:16:24.339891 EX_ROW_EN[1] = 0x0
7059 11:16:24.343536 LP4Y_EN = 0x0
7060 11:16:24.344077 WORK_FSP = 0x1
7061 11:16:24.346793 WL = 0x5
7062 11:16:24.347228 RL = 0x5
7063 11:16:24.349764 BL = 0x2
7064 11:16:24.350217 RPST = 0x0
7065 11:16:24.353531 RD_PRE = 0x0
7066 11:16:24.354049 WR_PRE = 0x1
7067 11:16:24.356616 WR_PST = 0x1
7068 11:16:24.357129 DBI_WR = 0x0
7069 11:16:24.360082 DBI_RD = 0x0
7070 11:16:24.360596 OTF = 0x1
7071 11:16:24.363457 ===================================
7072 11:16:24.366516 ===================================
7073 11:16:24.369533 ANA top config
7074 11:16:24.373383 ===================================
7075 11:16:24.373904 DLL_ASYNC_EN = 0
7076 11:16:24.376125 ALL_SLAVE_EN = 0
7077 11:16:24.379519 NEW_RANK_MODE = 1
7078 11:16:24.382711 DLL_IDLE_MODE = 1
7079 11:16:24.386694 LP45_APHY_COMB_EN = 1
7080 11:16:24.387215 TX_ODT_DIS = 0
7081 11:16:24.389497 NEW_8X_MODE = 1
7082 11:16:24.392358 ===================================
7083 11:16:24.395762 ===================================
7084 11:16:24.398968 data_rate = 3200
7085 11:16:24.402805 CKR = 1
7086 11:16:24.405687 DQ_P2S_RATIO = 8
7087 11:16:24.409983 ===================================
7088 11:16:24.412057 CA_P2S_RATIO = 8
7089 11:16:24.415982 DQ_CA_OPEN = 0
7090 11:16:24.416486 DQ_SEMI_OPEN = 0
7091 11:16:24.418518 CA_SEMI_OPEN = 0
7092 11:16:24.423142 CA_FULL_RATE = 0
7093 11:16:24.425351 DQ_CKDIV4_EN = 0
7094 11:16:24.428642 CA_CKDIV4_EN = 0
7095 11:16:24.433004 CA_PREDIV_EN = 0
7096 11:16:24.433527 PH8_DLY = 12
7097 11:16:24.435326 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7098 11:16:24.438703 DQ_AAMCK_DIV = 4
7099 11:16:24.441654 CA_AAMCK_DIV = 4
7100 11:16:24.445128 CA_ADMCK_DIV = 4
7101 11:16:24.448457 DQ_TRACK_CA_EN = 0
7102 11:16:24.451718 CA_PICK = 1600
7103 11:16:24.452161 CA_MCKIO = 1600
7104 11:16:24.455173 MCKIO_SEMI = 0
7105 11:16:24.458360 PLL_FREQ = 3068
7106 11:16:24.461686 DQ_UI_PI_RATIO = 32
7107 11:16:24.464975 CA_UI_PI_RATIO = 0
7108 11:16:24.468332 ===================================
7109 11:16:24.471817 ===================================
7110 11:16:24.474954 memory_type:LPDDR4
7111 11:16:24.475516 GP_NUM : 10
7112 11:16:24.478405 SRAM_EN : 1
7113 11:16:24.479067 MD32_EN : 0
7114 11:16:24.481600 ===================================
7115 11:16:24.484547 [ANA_INIT] >>>>>>>>>>>>>>
7116 11:16:24.488245 <<<<<< [CONFIGURE PHASE]: ANA_TX
7117 11:16:24.490986 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7118 11:16:24.494502 ===================================
7119 11:16:24.497619 data_rate = 3200,PCW = 0X7600
7120 11:16:24.501435 ===================================
7121 11:16:24.504461 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7122 11:16:24.510904 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7123 11:16:24.514185 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7124 11:16:24.521274 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7125 11:16:24.523945 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7126 11:16:24.527500 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7127 11:16:24.528122 [ANA_INIT] flow start
7128 11:16:24.530553 [ANA_INIT] PLL >>>>>>>>
7129 11:16:24.533757 [ANA_INIT] PLL <<<<<<<<
7130 11:16:24.537301 [ANA_INIT] MIDPI >>>>>>>>
7131 11:16:24.537729 [ANA_INIT] MIDPI <<<<<<<<
7132 11:16:24.540765 [ANA_INIT] DLL >>>>>>>>
7133 11:16:24.543725 [ANA_INIT] DLL <<<<<<<<
7134 11:16:24.544292 [ANA_INIT] flow end
7135 11:16:24.546735 ============ LP4 DIFF to SE enter ============
7136 11:16:24.553815 ============ LP4 DIFF to SE exit ============
7137 11:16:24.554342 [ANA_INIT] <<<<<<<<<<<<<
7138 11:16:24.557405 [Flow] Enable top DCM control >>>>>
7139 11:16:24.560114 [Flow] Enable top DCM control <<<<<
7140 11:16:24.563830 Enable DLL master slave shuffle
7141 11:16:24.570299 ==============================================================
7142 11:16:24.573137 Gating Mode config
7143 11:16:24.576585 ==============================================================
7144 11:16:24.579744 Config description:
7145 11:16:24.589733 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7146 11:16:24.596334 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7147 11:16:24.600716 SELPH_MODE 0: By rank 1: By Phase
7148 11:16:24.606408 ==============================================================
7149 11:16:24.609645 GAT_TRACK_EN = 1
7150 11:16:24.612593 RX_GATING_MODE = 2
7151 11:16:24.616724 RX_GATING_TRACK_MODE = 2
7152 11:16:24.619311 SELPH_MODE = 1
7153 11:16:24.622563 PICG_EARLY_EN = 1
7154 11:16:24.623128 VALID_LAT_VALUE = 1
7155 11:16:24.628780 ==============================================================
7156 11:16:24.632313 Enter into Gating configuration >>>>
7157 11:16:24.635855 Exit from Gating configuration <<<<
7158 11:16:24.638761 Enter into DVFS_PRE_config >>>>>
7159 11:16:24.648585 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7160 11:16:24.652524 Exit from DVFS_PRE_config <<<<<
7161 11:16:24.655444 Enter into PICG configuration >>>>
7162 11:16:24.658560 Exit from PICG configuration <<<<
7163 11:16:24.662357 [RX_INPUT] configuration >>>>>
7164 11:16:24.665092 [RX_INPUT] configuration <<<<<
7165 11:16:24.672341 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7166 11:16:24.675298 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7167 11:16:24.681399 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7168 11:16:24.688419 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7169 11:16:24.695334 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7170 11:16:24.701424 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7171 11:16:24.705301 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7172 11:16:24.707630 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7173 11:16:24.714667 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7174 11:16:24.717947 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7175 11:16:24.721034 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7176 11:16:24.724699 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7177 11:16:24.728129 ===================================
7178 11:16:24.730834 LPDDR4 DRAM CONFIGURATION
7179 11:16:24.734300 ===================================
7180 11:16:24.738015 EX_ROW_EN[0] = 0x0
7181 11:16:24.738577 EX_ROW_EN[1] = 0x0
7182 11:16:24.740958 LP4Y_EN = 0x0
7183 11:16:24.741574 WORK_FSP = 0x1
7184 11:16:24.744237 WL = 0x5
7185 11:16:24.744981 RL = 0x5
7186 11:16:24.746986 BL = 0x2
7187 11:16:24.747443 RPST = 0x0
7188 11:16:24.750513 RD_PRE = 0x0
7189 11:16:24.750977 WR_PRE = 0x1
7190 11:16:24.753887 WR_PST = 0x1
7191 11:16:24.757058 DBI_WR = 0x0
7192 11:16:24.757617 DBI_RD = 0x0
7193 11:16:24.760336 OTF = 0x1
7194 11:16:24.763501 ===================================
7195 11:16:24.767127 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7196 11:16:24.770483 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7197 11:16:24.773667 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7198 11:16:24.776929 ===================================
7199 11:16:24.780129 LPDDR4 DRAM CONFIGURATION
7200 11:16:24.783919 ===================================
7201 11:16:24.787195 EX_ROW_EN[0] = 0x10
7202 11:16:24.787615 EX_ROW_EN[1] = 0x0
7203 11:16:24.790004 LP4Y_EN = 0x0
7204 11:16:24.790419 WORK_FSP = 0x1
7205 11:16:24.793031 WL = 0x5
7206 11:16:24.793446 RL = 0x5
7207 11:16:24.796451 BL = 0x2
7208 11:16:24.799887 RPST = 0x0
7209 11:16:24.800453 RD_PRE = 0x0
7210 11:16:24.803099 WR_PRE = 0x1
7211 11:16:24.803614 WR_PST = 0x1
7212 11:16:24.806216 DBI_WR = 0x0
7213 11:16:24.806613 DBI_RD = 0x0
7214 11:16:24.810137 OTF = 0x1
7215 11:16:24.813141 ===================================
7216 11:16:24.819625 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7217 11:16:24.820205 ==
7218 11:16:24.823184 Dram Type= 6, Freq= 0, CH_0, rank 0
7219 11:16:24.826063 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7220 11:16:24.826590 ==
7221 11:16:24.829779 [Duty_Offset_Calibration]
7222 11:16:24.830235 B0:2 B1:0 CA:4
7223 11:16:24.830617
7224 11:16:24.832669 [DutyScan_Calibration_Flow] k_type=0
7225 11:16:24.842220
7226 11:16:24.842775 ==CLK 0==
7227 11:16:24.845519 Final CLK duty delay cell = -4
7228 11:16:24.848765 [-4] MAX Duty = 5031%(X100), DQS PI = 32
7229 11:16:24.851900 [-4] MIN Duty = 4844%(X100), DQS PI = 4
7230 11:16:24.855867 [-4] AVG Duty = 4937%(X100)
7231 11:16:24.856376
7232 11:16:24.858865 CH0 CLK Duty spec in!! Max-Min= 187%
7233 11:16:24.861746 [DutyScan_Calibration_Flow] ====Done====
7234 11:16:24.862261
7235 11:16:24.864947 [DutyScan_Calibration_Flow] k_type=1
7236 11:16:24.881420
7237 11:16:24.881974 ==DQS 0 ==
7238 11:16:24.884722 Final DQS duty delay cell = -4
7239 11:16:24.888142 [-4] MAX Duty = 4938%(X100), DQS PI = 46
7240 11:16:24.891393 [-4] MIN Duty = 4782%(X100), DQS PI = 12
7241 11:16:24.894929 [-4] AVG Duty = 4860%(X100)
7242 11:16:24.895488
7243 11:16:24.895852 ==DQS 1 ==
7244 11:16:24.898245 Final DQS duty delay cell = 0
7245 11:16:24.902737 [0] MAX Duty = 5187%(X100), DQS PI = 0
7246 11:16:24.904793 [0] MIN Duty = 4969%(X100), DQS PI = 10
7247 11:16:24.908515 [0] AVG Duty = 5078%(X100)
7248 11:16:24.909070
7249 11:16:24.911680 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7250 11:16:24.912268
7251 11:16:24.914519 CH0 DQS 1 Duty spec in!! Max-Min= 218%
7252 11:16:24.917705 [DutyScan_Calibration_Flow] ====Done====
7253 11:16:24.918165
7254 11:16:24.921084 [DutyScan_Calibration_Flow] k_type=3
7255 11:16:24.939419
7256 11:16:24.940098 ==DQM 0 ==
7257 11:16:24.942178 Final DQM duty delay cell = 0
7258 11:16:24.946779 [0] MAX Duty = 5124%(X100), DQS PI = 20
7259 11:16:24.948808 [0] MIN Duty = 4875%(X100), DQS PI = 54
7260 11:16:24.952353 [0] AVG Duty = 4999%(X100)
7261 11:16:24.952905
7262 11:16:24.953268 ==DQM 1 ==
7263 11:16:24.955861 Final DQM duty delay cell = 0
7264 11:16:24.958749 [0] MAX Duty = 4969%(X100), DQS PI = 0
7265 11:16:24.962312 [0] MIN Duty = 4844%(X100), DQS PI = 34
7266 11:16:24.965847 [0] AVG Duty = 4906%(X100)
7267 11:16:24.966313
7268 11:16:24.968798 CH0 DQM 0 Duty spec in!! Max-Min= 249%
7269 11:16:24.969255
7270 11:16:24.972427 CH0 DQM 1 Duty spec in!! Max-Min= 125%
7271 11:16:24.975173 [DutyScan_Calibration_Flow] ====Done====
7272 11:16:24.975728
7273 11:16:24.978393 [DutyScan_Calibration_Flow] k_type=2
7274 11:16:24.996451
7275 11:16:24.997004 ==DQ 0 ==
7276 11:16:25.000006 Final DQ duty delay cell = 0
7277 11:16:25.003097 [0] MAX Duty = 5124%(X100), DQS PI = 20
7278 11:16:25.006578 [0] MIN Duty = 4938%(X100), DQS PI = 12
7279 11:16:25.009727 [0] AVG Duty = 5031%(X100)
7280 11:16:25.010285
7281 11:16:25.010652 ==DQ 1 ==
7282 11:16:25.012804 Final DQ duty delay cell = 0
7283 11:16:25.016022 [0] MAX Duty = 5187%(X100), DQS PI = 2
7284 11:16:25.020199 [0] MIN Duty = 4938%(X100), DQS PI = 12
7285 11:16:25.022577 [0] AVG Duty = 5062%(X100)
7286 11:16:25.023136
7287 11:16:25.026055 CH0 DQ 0 Duty spec in!! Max-Min= 186%
7288 11:16:25.026512
7289 11:16:25.029410 CH0 DQ 1 Duty spec in!! Max-Min= 249%
7290 11:16:25.032183 [DutyScan_Calibration_Flow] ====Done====
7291 11:16:25.032635 ==
7292 11:16:25.035733 Dram Type= 6, Freq= 0, CH_1, rank 0
7293 11:16:25.038863 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7294 11:16:25.039310 ==
7295 11:16:25.042070 [Duty_Offset_Calibration]
7296 11:16:25.042514 B0:0 B1:-1 CA:3
7297 11:16:25.042834
7298 11:16:25.045940 [DutyScan_Calibration_Flow] k_type=0
7299 11:16:25.056127
7300 11:16:25.056526 ==CLK 0==
7301 11:16:25.059039 Final CLK duty delay cell = -4
7302 11:16:25.062527 [-4] MAX Duty = 5000%(X100), DQS PI = 4
7303 11:16:25.065963 [-4] MIN Duty = 4875%(X100), DQS PI = 12
7304 11:16:25.069134 [-4] AVG Duty = 4937%(X100)
7305 11:16:25.069636
7306 11:16:25.072561 CH1 CLK Duty spec in!! Max-Min= 125%
7307 11:16:25.075319 [DutyScan_Calibration_Flow] ====Done====
7308 11:16:25.075726
7309 11:16:25.078918 [DutyScan_Calibration_Flow] k_type=1
7310 11:16:25.095230
7311 11:16:25.095633 ==DQS 0 ==
7312 11:16:25.098395 Final DQS duty delay cell = 0
7313 11:16:25.101596 [0] MAX Duty = 5250%(X100), DQS PI = 28
7314 11:16:25.104656 [0] MIN Duty = 4938%(X100), DQS PI = 42
7315 11:16:25.107796 [0] AVG Duty = 5094%(X100)
7316 11:16:25.108226
7317 11:16:25.108544 ==DQS 1 ==
7318 11:16:25.111458 Final DQS duty delay cell = -4
7319 11:16:25.114993 [-4] MAX Duty = 5000%(X100), DQS PI = 30
7320 11:16:25.117794 [-4] MIN Duty = 4813%(X100), DQS PI = 0
7321 11:16:25.121113 [-4] AVG Duty = 4906%(X100)
7322 11:16:25.121657
7323 11:16:25.124740 CH1 DQS 0 Duty spec in!! Max-Min= 312%
7324 11:16:25.125286
7325 11:16:25.128414 CH1 DQS 1 Duty spec in!! Max-Min= 187%
7326 11:16:25.131503 [DutyScan_Calibration_Flow] ====Done====
7327 11:16:25.132079
7328 11:16:25.134243 [DutyScan_Calibration_Flow] k_type=3
7329 11:16:25.152128
7330 11:16:25.152673 ==DQM 0 ==
7331 11:16:25.155542 Final DQM duty delay cell = 0
7332 11:16:25.158890 [0] MAX Duty = 5062%(X100), DQS PI = 32
7333 11:16:25.162361 [0] MIN Duty = 4782%(X100), DQS PI = 38
7334 11:16:25.165408 [0] AVG Duty = 4922%(X100)
7335 11:16:25.165967
7336 11:16:25.166324 ==DQM 1 ==
7337 11:16:25.168698 Final DQM duty delay cell = 0
7338 11:16:25.171762 [0] MAX Duty = 5000%(X100), DQS PI = 30
7339 11:16:25.175105 [0] MIN Duty = 4813%(X100), DQS PI = 0
7340 11:16:25.178237 [0] AVG Duty = 4906%(X100)
7341 11:16:25.178802
7342 11:16:25.181391 CH1 DQM 0 Duty spec in!! Max-Min= 280%
7343 11:16:25.181840
7344 11:16:25.184707 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7345 11:16:25.188090 [DutyScan_Calibration_Flow] ====Done====
7346 11:16:25.188557
7347 11:16:25.191528 [DutyScan_Calibration_Flow] k_type=2
7348 11:16:25.208240
7349 11:16:25.208777 ==DQ 0 ==
7350 11:16:25.211903 Final DQ duty delay cell = -4
7351 11:16:25.214711 [-4] MAX Duty = 4969%(X100), DQS PI = 30
7352 11:16:25.218107 [-4] MIN Duty = 4813%(X100), DQS PI = 38
7353 11:16:25.222096 [-4] AVG Duty = 4891%(X100)
7354 11:16:25.222649
7355 11:16:25.223004 ==DQ 1 ==
7356 11:16:25.224347 Final DQ duty delay cell = 0
7357 11:16:25.228565 [0] MAX Duty = 5031%(X100), DQS PI = 30
7358 11:16:25.231496 [0] MIN Duty = 4875%(X100), DQS PI = 54
7359 11:16:25.235248 [0] AVG Duty = 4953%(X100)
7360 11:16:25.235858
7361 11:16:25.237619 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7362 11:16:25.238064
7363 11:16:25.240943 CH1 DQ 1 Duty spec in!! Max-Min= 156%
7364 11:16:25.244738 [DutyScan_Calibration_Flow] ====Done====
7365 11:16:25.247877 nWR fixed to 30
7366 11:16:25.251113 [ModeRegInit_LP4] CH0 RK0
7367 11:16:25.251662 [ModeRegInit_LP4] CH0 RK1
7368 11:16:25.254317 [ModeRegInit_LP4] CH1 RK0
7369 11:16:25.257380 [ModeRegInit_LP4] CH1 RK1
7370 11:16:25.257916 match AC timing 5
7371 11:16:25.264437 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7372 11:16:25.267780 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7373 11:16:25.270934 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7374 11:16:25.278376 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7375 11:16:25.280474 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7376 11:16:25.283777 [MiockJmeterHQA]
7377 11:16:25.284253
7378 11:16:25.287144 [DramcMiockJmeter] u1RxGatingPI = 0
7379 11:16:25.287590 0 : 4363, 4137
7380 11:16:25.287956 4 : 4255, 4029
7381 11:16:25.290176 8 : 4255, 4029
7382 11:16:25.290626 12 : 4257, 4029
7383 11:16:25.293480 16 : 4255, 4029
7384 11:16:25.293909 20 : 4252, 4027
7385 11:16:25.296781 24 : 4365, 4140
7386 11:16:25.297301 28 : 4363, 4138
7387 11:16:25.297631 32 : 4363, 4137
7388 11:16:25.300095 36 : 4253, 4027
7389 11:16:25.300643 40 : 4255, 4029
7390 11:16:25.303624 44 : 4363, 4137
7391 11:16:25.304066 48 : 4252, 4027
7392 11:16:25.307328 52 : 4365, 4140
7393 11:16:25.307747 56 : 4252, 4027
7394 11:16:25.310484 60 : 4253, 4026
7395 11:16:25.311012 64 : 4252, 4027
7396 11:16:25.311352 68 : 4255, 4029
7397 11:16:25.314080 72 : 4361, 4137
7398 11:16:25.314603 76 : 4250, 4027
7399 11:16:25.316704 80 : 4360, 4137
7400 11:16:25.317124 84 : 4363, 4140
7401 11:16:25.319954 88 : 4250, 4027
7402 11:16:25.320411 92 : 4252, 4029
7403 11:16:25.323855 96 : 4361, 3427
7404 11:16:25.324423 100 : 4250, 0
7405 11:16:25.324766 104 : 4250, 0
7406 11:16:25.326787 108 : 4249, 0
7407 11:16:25.327207 112 : 4249, 0
7408 11:16:25.331182 116 : 4252, 0
7409 11:16:25.331705 120 : 4250, 0
7410 11:16:25.332069 124 : 4363, 0
7411 11:16:25.333257 128 : 4254, 0
7412 11:16:25.333675 132 : 4250, 0
7413 11:16:25.334007 136 : 4361, 0
7414 11:16:25.336511 140 : 4250, 0
7415 11:16:25.337034 144 : 4250, 0
7416 11:16:25.339860 148 : 4250, 0
7417 11:16:25.340431 152 : 4252, 0
7418 11:16:25.340775 156 : 4360, 0
7419 11:16:25.343021 160 : 4250, 0
7420 11:16:25.343439 164 : 4250, 0
7421 11:16:25.346554 168 : 4254, 0
7422 11:16:25.347077 172 : 4361, 0
7423 11:16:25.347419 176 : 4250, 0
7424 11:16:25.349550 180 : 4255, 0
7425 11:16:25.349975 184 : 4250, 0
7426 11:16:25.353193 188 : 4250, 0
7427 11:16:25.353720 192 : 4252, 0
7428 11:16:25.354063 196 : 4250, 0
7429 11:16:25.356868 200 : 4250, 0
7430 11:16:25.357384 204 : 4253, 0
7431 11:16:25.359516 208 : 4360, 0
7432 11:16:25.360066 212 : 4360, 0
7433 11:16:25.360413 216 : 4250, 0
7434 11:16:25.363196 220 : 4255, 346
7435 11:16:25.363741 224 : 4254, 3848
7436 11:16:25.366910 228 : 4361, 4137
7437 11:16:25.367481 232 : 4361, 4137
7438 11:16:25.370234 236 : 4250, 4026
7439 11:16:25.370807 240 : 4363, 4137
7440 11:16:25.373756 244 : 4252, 4029
7441 11:16:25.374329 248 : 4250, 4027
7442 11:16:25.376339 252 : 4361, 4137
7443 11:16:25.376931 256 : 4250, 4026
7444 11:16:25.377313 260 : 4252, 4029
7445 11:16:25.380090 264 : 4363, 4140
7446 11:16:25.380623 268 : 4255, 4029
7447 11:16:25.382530 272 : 4250, 4027
7448 11:16:25.382997 276 : 4250, 4026
7449 11:16:25.386497 280 : 4363, 4140
7450 11:16:25.387103 284 : 4363, 4137
7451 11:16:25.389258 288 : 4250, 4027
7452 11:16:25.389773 292 : 4360, 4137
7453 11:16:25.392488 296 : 4252, 4029
7454 11:16:25.392963 300 : 4250, 4026
7455 11:16:25.396136 304 : 4252, 4030
7456 11:16:25.396725 308 : 4250, 4027
7457 11:16:25.399949 312 : 4252, 4029
7458 11:16:25.400583 316 : 4363, 4140
7459 11:16:25.403608 320 : 4255, 4029
7460 11:16:25.404148 324 : 4250, 4027
7461 11:16:25.404626 328 : 4250, 4026
7462 11:16:25.405663 332 : 4363, 4140
7463 11:16:25.406100 336 : 4363, 2011
7464 11:16:25.406438
7465 11:16:25.409229 MIOCK jitter meter ch=0
7466 11:16:25.409764
7467 11:16:25.412608 1T = (336-100) = 236 dly cells
7468 11:16:25.419006 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7469 11:16:25.419517 ==
7470 11:16:25.422915 Dram Type= 6, Freq= 0, CH_0, rank 0
7471 11:16:25.425646 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7472 11:16:25.426216 ==
7473 11:16:25.432421 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7474 11:16:25.435632 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7475 11:16:25.438407 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7476 11:16:25.445340 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7477 11:16:25.455164 [CA 0] Center 43 (13~73) winsize 61
7478 11:16:25.457617 [CA 1] Center 43 (13~73) winsize 61
7479 11:16:25.461359 [CA 2] Center 38 (9~67) winsize 59
7480 11:16:25.465343 [CA 3] Center 37 (8~67) winsize 60
7481 11:16:25.467924 [CA 4] Center 35 (6~65) winsize 60
7482 11:16:25.471029 [CA 5] Center 35 (5~66) winsize 62
7483 11:16:25.471600
7484 11:16:25.474069 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7485 11:16:25.474470
7486 11:16:25.480949 [CATrainingPosCal] consider 1 rank data
7487 11:16:25.481520 u2DelayCellTimex100 = 275/100 ps
7488 11:16:25.487426 CA0 delay=43 (13~73),Diff = 8 PI (28 cell)
7489 11:16:25.490539 CA1 delay=43 (13~73),Diff = 8 PI (28 cell)
7490 11:16:25.494221 CA2 delay=38 (9~67),Diff = 3 PI (10 cell)
7491 11:16:25.496991 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7492 11:16:25.500953 CA4 delay=35 (6~65),Diff = 0 PI (0 cell)
7493 11:16:25.504122 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7494 11:16:25.504652
7495 11:16:25.507297 CA PerBit enable=1, Macro0, CA PI delay=35
7496 11:16:25.507717
7497 11:16:25.510136 [CBTSetCACLKResult] CA Dly = 35
7498 11:16:25.513836 CS Dly: 10 (0~41)
7499 11:16:25.517063 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7500 11:16:25.520194 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7501 11:16:25.520617 ==
7502 11:16:25.523529 Dram Type= 6, Freq= 0, CH_0, rank 1
7503 11:16:25.530194 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7504 11:16:25.530719 ==
7505 11:16:25.533371 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7506 11:16:25.540144 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7507 11:16:25.543525 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7508 11:16:25.549978 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7509 11:16:25.558800 [CA 0] Center 43 (13~74) winsize 62
7510 11:16:25.561726 [CA 1] Center 43 (14~73) winsize 60
7511 11:16:25.564944 [CA 2] Center 38 (9~68) winsize 60
7512 11:16:25.568910 [CA 3] Center 38 (9~68) winsize 60
7513 11:16:25.571424 [CA 4] Center 36 (7~66) winsize 60
7514 11:16:25.574498 [CA 5] Center 36 (7~66) winsize 60
7515 11:16:25.574968
7516 11:16:25.578123 [CmdBusTrainingLP45] Vref(ca) range 0: 30
7517 11:16:25.578701
7518 11:16:25.581709 [CATrainingPosCal] consider 2 rank data
7519 11:16:25.584715 u2DelayCellTimex100 = 275/100 ps
7520 11:16:25.591664 CA0 delay=43 (13~73),Diff = 7 PI (24 cell)
7521 11:16:25.594260 CA1 delay=43 (14~73),Diff = 7 PI (24 cell)
7522 11:16:25.597991 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
7523 11:16:25.600818 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7524 11:16:25.604132 CA4 delay=36 (7~65),Diff = 0 PI (0 cell)
7525 11:16:25.607525 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
7526 11:16:25.608094
7527 11:16:25.611176 CA PerBit enable=1, Macro0, CA PI delay=36
7528 11:16:25.611704
7529 11:16:25.614070 [CBTSetCACLKResult] CA Dly = 36
7530 11:16:25.618278 CS Dly: 11 (0~43)
7531 11:16:25.620948 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7532 11:16:25.624122 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7533 11:16:25.624622
7534 11:16:25.627440 ----->DramcWriteLeveling(PI) begin...
7535 11:16:25.627996 ==
7536 11:16:25.631180 Dram Type= 6, Freq= 0, CH_0, rank 0
7537 11:16:25.637558 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7538 11:16:25.637984 ==
7539 11:16:25.641039 Write leveling (Byte 0): 35 => 35
7540 11:16:25.643975 Write leveling (Byte 1): 26 => 26
7541 11:16:25.644550 DramcWriteLeveling(PI) end<-----
7542 11:16:25.647388
7543 11:16:25.647917 ==
7544 11:16:25.650678 Dram Type= 6, Freq= 0, CH_0, rank 0
7545 11:16:25.653716 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7546 11:16:25.654265 ==
7547 11:16:25.657247 [Gating] SW mode calibration
7548 11:16:25.664577 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7549 11:16:25.667012 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7550 11:16:25.674117 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7551 11:16:25.676894 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7552 11:16:25.680258 1 4 8 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
7553 11:16:25.686847 1 4 12 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
7554 11:16:25.689837 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7555 11:16:25.693676 1 4 20 | B1->B0 | 2f2f 3434 | 0 1 | (0 0) (1 1)
7556 11:16:25.700205 1 4 24 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
7557 11:16:25.703070 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7558 11:16:25.706716 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7559 11:16:25.712931 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7560 11:16:25.716551 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7561 11:16:25.723293 1 5 12 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (0 1)
7562 11:16:25.726768 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7563 11:16:25.729592 1 5 20 | B1->B0 | 3030 2323 | 1 0 | (1 0) (0 0)
7564 11:16:25.733624 1 5 24 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
7565 11:16:25.739422 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7566 11:16:25.742400 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7567 11:16:25.749641 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7568 11:16:25.752676 1 6 8 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
7569 11:16:25.756138 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7570 11:16:25.762512 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7571 11:16:25.765970 1 6 20 | B1->B0 | 3535 4646 | 0 0 | (0 0) (0 0)
7572 11:16:25.768943 1 6 24 | B1->B0 | 4545 4646 | 0 0 | (0 0) (0 0)
7573 11:16:25.775615 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7574 11:16:25.779699 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7575 11:16:25.781722 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7576 11:16:25.788958 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7577 11:16:25.791677 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7578 11:16:25.795078 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7579 11:16:25.801876 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7580 11:16:25.805372 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7581 11:16:25.808240 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7582 11:16:25.815202 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7583 11:16:25.818193 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7584 11:16:25.821599 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7585 11:16:25.828284 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7586 11:16:25.832567 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7587 11:16:25.834581 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7588 11:16:25.841234 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7589 11:16:25.844500 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7590 11:16:25.848176 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7591 11:16:25.854764 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7592 11:16:25.857756 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7593 11:16:25.861451 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7594 11:16:25.867885 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7595 11:16:25.868492 Total UI for P1: 0, mck2ui 16
7596 11:16:25.874366 best dqsien dly found for B0: ( 1, 9, 10)
7597 11:16:25.877747 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7598 11:16:25.880671 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7599 11:16:25.883933 Total UI for P1: 0, mck2ui 16
7600 11:16:25.887314 best dqsien dly found for B1: ( 1, 9, 20)
7601 11:16:25.890793 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7602 11:16:25.893674 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7603 11:16:25.894095
7604 11:16:25.900380 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7605 11:16:25.903959 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7606 11:16:25.907126 [Gating] SW calibration Done
7607 11:16:25.907650 ==
7608 11:16:25.910068 Dram Type= 6, Freq= 0, CH_0, rank 0
7609 11:16:25.913801 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7610 11:16:25.914531 ==
7611 11:16:25.915053 RX Vref Scan: 0
7612 11:16:25.915514
7613 11:16:25.916812 RX Vref 0 -> 0, step: 1
7614 11:16:25.917295
7615 11:16:25.920390 RX Delay 0 -> 252, step: 8
7616 11:16:25.923443 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7617 11:16:25.926952 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7618 11:16:25.933834 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7619 11:16:25.936652 iDelay=192, Bit 3, Center 127 (72 ~ 183) 112
7620 11:16:25.939540 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7621 11:16:25.942954 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7622 11:16:25.946769 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7623 11:16:25.953051 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7624 11:16:25.956149 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
7625 11:16:25.959924 iDelay=192, Bit 9, Center 111 (56 ~ 167) 112
7626 11:16:25.962540 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7627 11:16:25.966033 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7628 11:16:25.972959 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7629 11:16:25.975927 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7630 11:16:25.978929 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7631 11:16:25.982464 iDelay=192, Bit 15, Center 135 (80 ~ 191) 112
7632 11:16:25.985882 ==
7633 11:16:25.986400 Dram Type= 6, Freq= 0, CH_0, rank 0
7634 11:16:25.992702 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7635 11:16:25.993214 ==
7636 11:16:25.993553 DQS Delay:
7637 11:16:25.996100 DQS0 = 0, DQS1 = 0
7638 11:16:25.996520 DQM Delay:
7639 11:16:25.998910 DQM0 = 131, DQM1 = 127
7640 11:16:25.999416 DQ Delay:
7641 11:16:26.002413 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =127
7642 11:16:26.005412 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7643 11:16:26.008503 DQ8 =119, DQ9 =111, DQ10 =127, DQ11 =123
7644 11:16:26.012020 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =135
7645 11:16:26.012489
7646 11:16:26.012823
7647 11:16:26.013136 ==
7648 11:16:26.015636 Dram Type= 6, Freq= 0, CH_0, rank 0
7649 11:16:26.021688 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7650 11:16:26.022185 ==
7651 11:16:26.022522
7652 11:16:26.022833
7653 11:16:26.025306 TX Vref Scan disable
7654 11:16:26.025819 == TX Byte 0 ==
7655 11:16:26.028458 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
7656 11:16:26.035237 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7657 11:16:26.035756 == TX Byte 1 ==
7658 11:16:26.038730 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7659 11:16:26.044664 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7660 11:16:26.045175 ==
7661 11:16:26.048490 Dram Type= 6, Freq= 0, CH_0, rank 0
7662 11:16:26.051380 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7663 11:16:26.051804 ==
7664 11:16:26.065610
7665 11:16:26.069501 TX Vref early break, caculate TX vref
7666 11:16:26.072391 TX Vref=16, minBit 1, minWin=21, winSum=357
7667 11:16:26.075167 TX Vref=18, minBit 7, minWin=21, winSum=366
7668 11:16:26.079156 TX Vref=20, minBit 0, minWin=22, winSum=379
7669 11:16:26.082010 TX Vref=22, minBit 1, minWin=23, winSum=387
7670 11:16:26.085118 TX Vref=24, minBit 1, minWin=23, winSum=403
7671 11:16:26.091749 TX Vref=26, minBit 1, minWin=23, winSum=405
7672 11:16:26.094931 TX Vref=28, minBit 1, minWin=24, winSum=408
7673 11:16:26.098330 TX Vref=30, minBit 0, minWin=24, winSum=404
7674 11:16:26.102176 TX Vref=32, minBit 0, minWin=23, winSum=399
7675 11:16:26.104858 TX Vref=34, minBit 6, minWin=22, winSum=380
7676 11:16:26.111648 [TxChooseVref] Worse bit 1, Min win 24, Win sum 408, Final Vref 28
7677 11:16:26.112217
7678 11:16:26.114933 Final TX Range 0 Vref 28
7679 11:16:26.115447
7680 11:16:26.115879 ==
7681 11:16:26.118436 Dram Type= 6, Freq= 0, CH_0, rank 0
7682 11:16:26.121501 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7683 11:16:26.122006 ==
7684 11:16:26.122341
7685 11:16:26.124519
7686 11:16:26.124928 TX Vref Scan disable
7687 11:16:26.131845 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7688 11:16:26.132402 == TX Byte 0 ==
7689 11:16:26.135015 u2DelayCellOfst[0]=14 cells (4 PI)
7690 11:16:26.138093 u2DelayCellOfst[1]=17 cells (5 PI)
7691 11:16:26.141998 u2DelayCellOfst[2]=10 cells (3 PI)
7692 11:16:26.144651 u2DelayCellOfst[3]=14 cells (4 PI)
7693 11:16:26.147926 u2DelayCellOfst[4]=10 cells (3 PI)
7694 11:16:26.151025 u2DelayCellOfst[5]=0 cells (0 PI)
7695 11:16:26.154709 u2DelayCellOfst[6]=21 cells (6 PI)
7696 11:16:26.157831 u2DelayCellOfst[7]=17 cells (5 PI)
7697 11:16:26.161396 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7698 11:16:26.165192 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
7699 11:16:26.167545 == TX Byte 1 ==
7700 11:16:26.170577 u2DelayCellOfst[8]=0 cells (0 PI)
7701 11:16:26.174381 u2DelayCellOfst[9]=0 cells (0 PI)
7702 11:16:26.177726 u2DelayCellOfst[10]=3 cells (1 PI)
7703 11:16:26.180775 u2DelayCellOfst[11]=0 cells (0 PI)
7704 11:16:26.184151 u2DelayCellOfst[12]=10 cells (3 PI)
7705 11:16:26.187249 u2DelayCellOfst[13]=10 cells (3 PI)
7706 11:16:26.187741 u2DelayCellOfst[14]=14 cells (4 PI)
7707 11:16:26.190242 u2DelayCellOfst[15]=10 cells (3 PI)
7708 11:16:26.197380 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7709 11:16:26.200696 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7710 11:16:26.203766 DramC Write-DBI on
7711 11:16:26.204337 ==
7712 11:16:26.207230 Dram Type= 6, Freq= 0, CH_0, rank 0
7713 11:16:26.210232 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7714 11:16:26.210605 ==
7715 11:16:26.210917
7716 11:16:26.211213
7717 11:16:26.213802 TX Vref Scan disable
7718 11:16:26.214317 == TX Byte 0 ==
7719 11:16:26.220613 Update DQM dly =735 (2 ,6, 31) DQM OEN =(3 ,3)
7720 11:16:26.221220 == TX Byte 1 ==
7721 11:16:26.223619 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7722 11:16:26.226745 DramC Write-DBI off
7723 11:16:26.227258
7724 11:16:26.227590 [DATLAT]
7725 11:16:26.230172 Freq=1600, CH0 RK0
7726 11:16:26.230591
7727 11:16:26.230919 DATLAT Default: 0xf
7728 11:16:26.233279 0, 0xFFFF, sum = 0
7729 11:16:26.233701 1, 0xFFFF, sum = 0
7730 11:16:26.236873 2, 0xFFFF, sum = 0
7731 11:16:26.239952 3, 0xFFFF, sum = 0
7732 11:16:26.240558 4, 0xFFFF, sum = 0
7733 11:16:26.243657 5, 0xFFFF, sum = 0
7734 11:16:26.244208 6, 0xFFFF, sum = 0
7735 11:16:26.247210 7, 0xFFFF, sum = 0
7736 11:16:26.247731 8, 0xFFFF, sum = 0
7737 11:16:26.250868 9, 0xFFFF, sum = 0
7738 11:16:26.251395 10, 0xFFFF, sum = 0
7739 11:16:26.253422 11, 0xFFFF, sum = 0
7740 11:16:26.253948 12, 0xFFFF, sum = 0
7741 11:16:26.256920 13, 0xFFFF, sum = 0
7742 11:16:26.257448 14, 0x0, sum = 1
7743 11:16:26.259906 15, 0x0, sum = 2
7744 11:16:26.260459 16, 0x0, sum = 3
7745 11:16:26.263149 17, 0x0, sum = 4
7746 11:16:26.263668 best_step = 15
7747 11:16:26.263998
7748 11:16:26.264352 ==
7749 11:16:26.266244 Dram Type= 6, Freq= 0, CH_0, rank 0
7750 11:16:26.272916 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7751 11:16:26.273438 ==
7752 11:16:26.273773 RX Vref Scan: 1
7753 11:16:26.274084
7754 11:16:26.276149 Set Vref Range= 24 -> 127
7755 11:16:26.276576
7756 11:16:26.279610 RX Vref 24 -> 127, step: 1
7757 11:16:26.280158
7758 11:16:26.282617 RX Delay 11 -> 252, step: 4
7759 11:16:26.283030
7760 11:16:26.283358 Set Vref, RX VrefLevel [Byte0]: 24
7761 11:16:26.286613 [Byte1]: 24
7762 11:16:26.290884
7763 11:16:26.291295 Set Vref, RX VrefLevel [Byte0]: 25
7764 11:16:26.293649 [Byte1]: 25
7765 11:16:26.298016
7766 11:16:26.298426 Set Vref, RX VrefLevel [Byte0]: 26
7767 11:16:26.301017 [Byte1]: 26
7768 11:16:26.306414
7769 11:16:26.306825 Set Vref, RX VrefLevel [Byte0]: 27
7770 11:16:26.308707 [Byte1]: 27
7771 11:16:26.313473
7772 11:16:26.313986 Set Vref, RX VrefLevel [Byte0]: 28
7773 11:16:26.316522 [Byte1]: 28
7774 11:16:26.320727
7775 11:16:26.321271 Set Vref, RX VrefLevel [Byte0]: 29
7776 11:16:26.325382 [Byte1]: 29
7777 11:16:26.328581
7778 11:16:26.329094 Set Vref, RX VrefLevel [Byte0]: 30
7779 11:16:26.332458 [Byte1]: 30
7780 11:16:26.336267
7781 11:16:26.336684 Set Vref, RX VrefLevel [Byte0]: 31
7782 11:16:26.339363 [Byte1]: 31
7783 11:16:26.344008
7784 11:16:26.344545 Set Vref, RX VrefLevel [Byte0]: 32
7785 11:16:26.347522 [Byte1]: 32
7786 11:16:26.351533
7787 11:16:26.352084 Set Vref, RX VrefLevel [Byte0]: 33
7788 11:16:26.354446 [Byte1]: 33
7789 11:16:26.359327
7790 11:16:26.359839 Set Vref, RX VrefLevel [Byte0]: 34
7791 11:16:26.362807 [Byte1]: 34
7792 11:16:26.366514
7793 11:16:26.367150 Set Vref, RX VrefLevel [Byte0]: 35
7794 11:16:26.370462 [Byte1]: 35
7795 11:16:26.374157
7796 11:16:26.374671 Set Vref, RX VrefLevel [Byte0]: 36
7797 11:16:26.377837 [Byte1]: 36
7798 11:16:26.382030
7799 11:16:26.382584 Set Vref, RX VrefLevel [Byte0]: 37
7800 11:16:26.385521 [Byte1]: 37
7801 11:16:26.389304
7802 11:16:26.389844 Set Vref, RX VrefLevel [Byte0]: 38
7803 11:16:26.393196 [Byte1]: 38
7804 11:16:26.396748
7805 11:16:26.397177 Set Vref, RX VrefLevel [Byte0]: 39
7806 11:16:26.400602 [Byte1]: 39
7807 11:16:26.404514
7808 11:16:26.404925 Set Vref, RX VrefLevel [Byte0]: 40
7809 11:16:26.407971 [Byte1]: 40
7810 11:16:26.412449
7811 11:16:26.412966 Set Vref, RX VrefLevel [Byte0]: 41
7812 11:16:26.415510 [Byte1]: 41
7813 11:16:26.420245
7814 11:16:26.420752 Set Vref, RX VrefLevel [Byte0]: 42
7815 11:16:26.423252 [Byte1]: 42
7816 11:16:26.428109
7817 11:16:26.428621 Set Vref, RX VrefLevel [Byte0]: 43
7818 11:16:26.430477 [Byte1]: 43
7819 11:16:26.435420
7820 11:16:26.435977 Set Vref, RX VrefLevel [Byte0]: 44
7821 11:16:26.438652 [Byte1]: 44
7822 11:16:26.443087
7823 11:16:26.443648 Set Vref, RX VrefLevel [Byte0]: 45
7824 11:16:26.446739 [Byte1]: 45
7825 11:16:26.450645
7826 11:16:26.451202 Set Vref, RX VrefLevel [Byte0]: 46
7827 11:16:26.453411 [Byte1]: 46
7828 11:16:26.458541
7829 11:16:26.459096 Set Vref, RX VrefLevel [Byte0]: 47
7830 11:16:26.461674 [Byte1]: 47
7831 11:16:26.465856
7832 11:16:26.466389 Set Vref, RX VrefLevel [Byte0]: 48
7833 11:16:26.469428 [Byte1]: 48
7834 11:16:26.473266
7835 11:16:26.473823 Set Vref, RX VrefLevel [Byte0]: 49
7836 11:16:26.476653 [Byte1]: 49
7837 11:16:26.480946
7838 11:16:26.481505 Set Vref, RX VrefLevel [Byte0]: 50
7839 11:16:26.484193 [Byte1]: 50
7840 11:16:26.488982
7841 11:16:26.489540 Set Vref, RX VrefLevel [Byte0]: 51
7842 11:16:26.492246 [Byte1]: 51
7843 11:16:26.496832
7844 11:16:26.497289 Set Vref, RX VrefLevel [Byte0]: 52
7845 11:16:26.499446 [Byte1]: 52
7846 11:16:26.503440
7847 11:16:26.503853 Set Vref, RX VrefLevel [Byte0]: 53
7848 11:16:26.506718 [Byte1]: 53
7849 11:16:26.510900
7850 11:16:26.511423 Set Vref, RX VrefLevel [Byte0]: 54
7851 11:16:26.514440 [Byte1]: 54
7852 11:16:26.519104
7853 11:16:26.519634 Set Vref, RX VrefLevel [Byte0]: 55
7854 11:16:26.523375 [Byte1]: 55
7855 11:16:26.526485
7856 11:16:26.526948 Set Vref, RX VrefLevel [Byte0]: 56
7857 11:16:26.529780 [Byte1]: 56
7858 11:16:26.533965
7859 11:16:26.534389 Set Vref, RX VrefLevel [Byte0]: 57
7860 11:16:26.537754 [Byte1]: 57
7861 11:16:26.542207
7862 11:16:26.542735 Set Vref, RX VrefLevel [Byte0]: 58
7863 11:16:26.548382 [Byte1]: 58
7864 11:16:26.548917
7865 11:16:26.551161 Set Vref, RX VrefLevel [Byte0]: 59
7866 11:16:26.554329 [Byte1]: 59
7867 11:16:26.554752
7868 11:16:26.557864 Set Vref, RX VrefLevel [Byte0]: 60
7869 11:16:26.561333 [Byte1]: 60
7870 11:16:26.564909
7871 11:16:26.565433 Set Vref, RX VrefLevel [Byte0]: 61
7872 11:16:26.567670 [Byte1]: 61
7873 11:16:26.572090
7874 11:16:26.572634 Set Vref, RX VrefLevel [Byte0]: 62
7875 11:16:26.575255 [Byte1]: 62
7876 11:16:26.580406
7877 11:16:26.580929 Set Vref, RX VrefLevel [Byte0]: 63
7878 11:16:26.583142 [Byte1]: 63
7879 11:16:26.587405
7880 11:16:26.587930 Set Vref, RX VrefLevel [Byte0]: 64
7881 11:16:26.590807 [Byte1]: 64
7882 11:16:26.594938
7883 11:16:26.595380 Set Vref, RX VrefLevel [Byte0]: 65
7884 11:16:26.598376 [Byte1]: 65
7885 11:16:26.602917
7886 11:16:26.603461 Set Vref, RX VrefLevel [Byte0]: 66
7887 11:16:26.605503 [Byte1]: 66
7888 11:16:26.610566
7889 11:16:26.611116 Set Vref, RX VrefLevel [Byte0]: 67
7890 11:16:26.613321 [Byte1]: 67
7891 11:16:26.618189
7892 11:16:26.618678 Set Vref, RX VrefLevel [Byte0]: 68
7893 11:16:26.620750 [Byte1]: 68
7894 11:16:26.625386
7895 11:16:26.625795 Set Vref, RX VrefLevel [Byte0]: 69
7896 11:16:26.628769 [Byte1]: 69
7897 11:16:26.632729
7898 11:16:26.633142 Set Vref, RX VrefLevel [Byte0]: 70
7899 11:16:26.636063 [Byte1]: 70
7900 11:16:26.641198
7901 11:16:26.641720 Set Vref, RX VrefLevel [Byte0]: 71
7902 11:16:26.644105 [Byte1]: 71
7903 11:16:26.648134
7904 11:16:26.648545 Set Vref, RX VrefLevel [Byte0]: 72
7905 11:16:26.652192 [Byte1]: 72
7906 11:16:26.655942
7907 11:16:26.656499 Set Vref, RX VrefLevel [Byte0]: 73
7908 11:16:26.659236 [Byte1]: 73
7909 11:16:26.663681
7910 11:16:26.664243 Final RX Vref Byte 0 = 62 to rank0
7911 11:16:26.666670 Final RX Vref Byte 1 = 60 to rank0
7912 11:16:26.670173 Final RX Vref Byte 0 = 62 to rank1
7913 11:16:26.673766 Final RX Vref Byte 1 = 60 to rank1==
7914 11:16:26.677079 Dram Type= 6, Freq= 0, CH_0, rank 0
7915 11:16:26.683146 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7916 11:16:26.683672 ==
7917 11:16:26.684009 DQS Delay:
7918 11:16:26.686634 DQS0 = 0, DQS1 = 0
7919 11:16:26.687156 DQM Delay:
7920 11:16:26.687493 DQM0 = 129, DQM1 = 123
7921 11:16:26.689593 DQ Delay:
7922 11:16:26.693092 DQ0 =130, DQ1 =130, DQ2 =126, DQ3 =124
7923 11:16:26.696088 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =136
7924 11:16:26.699506 DQ8 =112, DQ9 =112, DQ10 =124, DQ11 =120
7925 11:16:26.703054 DQ12 =130, DQ13 =128, DQ14 =132, DQ15 =128
7926 11:16:26.703577
7927 11:16:26.703911
7928 11:16:26.704281
7929 11:16:26.706364 [DramC_TX_OE_Calibration] TA2
7930 11:16:26.709580 Original DQ_B0 (3 6) =30, OEN = 27
7931 11:16:26.712741 Original DQ_B1 (3 6) =30, OEN = 27
7932 11:16:26.716258 24, 0x0, End_B0=24 End_B1=24
7933 11:16:26.719387 25, 0x0, End_B0=25 End_B1=25
7934 11:16:26.719940 26, 0x0, End_B0=26 End_B1=26
7935 11:16:26.723001 27, 0x0, End_B0=27 End_B1=27
7936 11:16:26.725516 28, 0x0, End_B0=28 End_B1=28
7937 11:16:26.729017 29, 0x0, End_B0=29 End_B1=29
7938 11:16:26.732099 30, 0x0, End_B0=30 End_B1=30
7939 11:16:26.732526 31, 0x5151, End_B0=30 End_B1=30
7940 11:16:26.735396 Byte0 end_step=30 best_step=27
7941 11:16:26.738708 Byte1 end_step=30 best_step=27
7942 11:16:26.742012 Byte0 TX OE(2T, 0.5T) = (3, 3)
7943 11:16:26.745804 Byte1 TX OE(2T, 0.5T) = (3, 3)
7944 11:16:26.746332
7945 11:16:26.746669
7946 11:16:26.752567 [DQSOSCAuto] RK0, (LSB)MR18= 0x1613, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 398 ps
7947 11:16:26.755783 CH0 RK0: MR19=303, MR18=1613
7948 11:16:26.762371 CH0_RK0: MR19=0x303, MR18=0x1613, DQSOSC=398, MR23=63, INC=23, DEC=15
7949 11:16:26.762897
7950 11:16:26.765318 ----->DramcWriteLeveling(PI) begin...
7951 11:16:26.765740 ==
7952 11:16:26.768702 Dram Type= 6, Freq= 0, CH_0, rank 1
7953 11:16:26.772466 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7954 11:16:26.772991 ==
7955 11:16:26.775265 Write leveling (Byte 0): 36 => 36
7956 11:16:26.778581 Write leveling (Byte 1): 29 => 29
7957 11:16:26.781792 DramcWriteLeveling(PI) end<-----
7958 11:16:26.782209
7959 11:16:26.782542 ==
7960 11:16:26.784710 Dram Type= 6, Freq= 0, CH_0, rank 1
7961 11:16:26.791520 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7962 11:16:26.792065 ==
7963 11:16:26.795285 [Gating] SW mode calibration
7964 11:16:26.801769 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7965 11:16:26.805004 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7966 11:16:26.811233 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7967 11:16:26.814886 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7968 11:16:26.818126 1 4 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
7969 11:16:26.824213 1 4 12 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7970 11:16:26.828642 1 4 16 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
7971 11:16:26.831447 1 4 20 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
7972 11:16:26.837714 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7973 11:16:26.840755 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7974 11:16:26.844481 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7975 11:16:26.850758 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
7976 11:16:26.853790 1 5 8 | B1->B0 | 3434 3232 | 1 1 | (1 1) (1 0)
7977 11:16:26.857080 1 5 12 | B1->B0 | 3434 2a2a | 1 1 | (1 1) (1 0)
7978 11:16:26.863955 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7979 11:16:26.867364 1 5 20 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (0 0)
7980 11:16:26.870867 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7981 11:16:26.877155 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7982 11:16:26.880519 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7983 11:16:26.883790 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7984 11:16:26.890201 1 6 8 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
7985 11:16:26.894207 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7986 11:16:26.896839 1 6 16 | B1->B0 | 2828 4646 | 1 0 | (0 0) (0 0)
7987 11:16:26.904100 1 6 20 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7988 11:16:26.906694 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7989 11:16:26.910511 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7990 11:16:26.916614 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7991 11:16:26.920177 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7992 11:16:26.923449 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7993 11:16:26.930231 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7994 11:16:26.933606 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7995 11:16:26.936486 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7996 11:16:26.942865 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7997 11:16:26.946868 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7998 11:16:26.949657 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7999 11:16:26.955885 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8000 11:16:26.959783 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8001 11:16:26.962658 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8002 11:16:26.969604 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8003 11:16:26.972951 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8004 11:16:26.975873 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8005 11:16:26.982414 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8006 11:16:26.985953 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8007 11:16:26.989373 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8008 11:16:26.996213 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8009 11:16:26.999041 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8010 11:16:27.002380 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8011 11:16:27.005262 Total UI for P1: 0, mck2ui 16
8012 11:16:27.008587 best dqsien dly found for B0: ( 1, 9, 10)
8013 11:16:27.015715 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8014 11:16:27.018473 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8015 11:16:27.022364 Total UI for P1: 0, mck2ui 16
8016 11:16:27.025674 best dqsien dly found for B1: ( 1, 9, 18)
8017 11:16:27.028765 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8018 11:16:27.032229 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8019 11:16:27.032805
8020 11:16:27.035330 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8021 11:16:27.038670 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8022 11:16:27.041807 [Gating] SW calibration Done
8023 11:16:27.042267 ==
8024 11:16:27.044953 Dram Type= 6, Freq= 0, CH_0, rank 1
8025 11:16:27.051618 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8026 11:16:27.052200 ==
8027 11:16:27.052570 RX Vref Scan: 0
8028 11:16:27.052909
8029 11:16:27.054702 RX Vref 0 -> 0, step: 1
8030 11:16:27.055163
8031 11:16:27.057865 RX Delay 0 -> 252, step: 8
8032 11:16:27.061354 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8033 11:16:27.064930 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8034 11:16:27.068136 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
8035 11:16:27.074639 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
8036 11:16:27.078015 iDelay=200, Bit 4, Center 139 (88 ~ 191) 104
8037 11:16:27.080958 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8038 11:16:27.084698 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8039 11:16:27.087549 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8040 11:16:27.094873 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8041 11:16:27.097704 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8042 11:16:27.100552 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8043 11:16:27.104418 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
8044 11:16:27.107834 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8045 11:16:27.114051 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8046 11:16:27.117783 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8047 11:16:27.120874 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8048 11:16:27.121443 ==
8049 11:16:27.124221 Dram Type= 6, Freq= 0, CH_0, rank 1
8050 11:16:27.127440 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8051 11:16:27.130883 ==
8052 11:16:27.131441 DQS Delay:
8053 11:16:27.131812 DQS0 = 0, DQS1 = 0
8054 11:16:27.133845 DQM Delay:
8055 11:16:27.134412 DQM0 = 134, DQM1 = 124
8056 11:16:27.136975 DQ Delay:
8057 11:16:27.140706 DQ0 =131, DQ1 =135, DQ2 =131, DQ3 =131
8058 11:16:27.143737 DQ4 =139, DQ5 =119, DQ6 =143, DQ7 =143
8059 11:16:27.146814 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =119
8060 11:16:27.150347 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8061 11:16:27.150908
8062 11:16:27.151276
8063 11:16:27.151616 ==
8064 11:16:27.153407 Dram Type= 6, Freq= 0, CH_0, rank 1
8065 11:16:27.157572 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8066 11:16:27.160367 ==
8067 11:16:27.160826
8068 11:16:27.161191
8069 11:16:27.161532 TX Vref Scan disable
8070 11:16:27.163425 == TX Byte 0 ==
8071 11:16:27.166411 Update DQ dly =992 (3 ,6, 32) DQ OEN =(3 ,3)
8072 11:16:27.169561 Update DQM dly =992 (3 ,6, 32) DQM OEN =(3 ,3)
8073 11:16:27.173592 == TX Byte 1 ==
8074 11:16:27.176179 Update DQ dly =985 (3 ,6, 25) DQ OEN =(3 ,3)
8075 11:16:27.179524 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8076 11:16:27.183069 ==
8077 11:16:27.186348 Dram Type= 6, Freq= 0, CH_0, rank 1
8078 11:16:27.189834 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8079 11:16:27.190373 ==
8080 11:16:27.204090
8081 11:16:27.207116 TX Vref early break, caculate TX vref
8082 11:16:27.210819 TX Vref=16, minBit 0, minWin=23, winSum=382
8083 11:16:27.213947 TX Vref=18, minBit 3, minWin=22, winSum=385
8084 11:16:27.217298 TX Vref=20, minBit 0, minWin=23, winSum=393
8085 11:16:27.220700 TX Vref=22, minBit 0, minWin=24, winSum=405
8086 11:16:27.223743 TX Vref=24, minBit 3, minWin=24, winSum=411
8087 11:16:27.230275 TX Vref=26, minBit 3, minWin=24, winSum=415
8088 11:16:27.233957 TX Vref=28, minBit 0, minWin=25, winSum=415
8089 11:16:27.237125 TX Vref=30, minBit 4, minWin=24, winSum=411
8090 11:16:27.240322 TX Vref=32, minBit 0, minWin=24, winSum=402
8091 11:16:27.243450 TX Vref=34, minBit 0, minWin=24, winSum=394
8092 11:16:27.246427 TX Vref=36, minBit 0, minWin=23, winSum=385
8093 11:16:27.253728 [TxChooseVref] Worse bit 0, Min win 25, Win sum 415, Final Vref 28
8094 11:16:27.254295
8095 11:16:27.256565 Final TX Range 0 Vref 28
8096 11:16:27.257142
8097 11:16:27.257517 ==
8098 11:16:27.260410 Dram Type= 6, Freq= 0, CH_0, rank 1
8099 11:16:27.263949 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8100 11:16:27.264544 ==
8101 11:16:27.266946
8102 11:16:27.267505
8103 11:16:27.267872 TX Vref Scan disable
8104 11:16:27.273199 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8105 11:16:27.273675 == TX Byte 0 ==
8106 11:16:27.276389 u2DelayCellOfst[0]=10 cells (3 PI)
8107 11:16:27.280125 u2DelayCellOfst[1]=14 cells (4 PI)
8108 11:16:27.283439 u2DelayCellOfst[2]=7 cells (2 PI)
8109 11:16:27.286276 u2DelayCellOfst[3]=10 cells (3 PI)
8110 11:16:27.289514 u2DelayCellOfst[4]=7 cells (2 PI)
8111 11:16:27.292610 u2DelayCellOfst[5]=0 cells (0 PI)
8112 11:16:27.296442 u2DelayCellOfst[6]=14 cells (4 PI)
8113 11:16:27.299504 u2DelayCellOfst[7]=17 cells (5 PI)
8114 11:16:27.302788 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8115 11:16:27.306062 Update DQM dly =993 (3 ,6, 33) DQM OEN =(3 ,3)
8116 11:16:27.309163 == TX Byte 1 ==
8117 11:16:27.312734 u2DelayCellOfst[8]=0 cells (0 PI)
8118 11:16:27.316113 u2DelayCellOfst[9]=0 cells (0 PI)
8119 11:16:27.319951 u2DelayCellOfst[10]=3 cells (1 PI)
8120 11:16:27.323049 u2DelayCellOfst[11]=3 cells (1 PI)
8121 11:16:27.325897 u2DelayCellOfst[12]=10 cells (3 PI)
8122 11:16:27.329287 u2DelayCellOfst[13]=10 cells (3 PI)
8123 11:16:27.329847 u2DelayCellOfst[14]=17 cells (5 PI)
8124 11:16:27.332933 u2DelayCellOfst[15]=14 cells (4 PI)
8125 11:16:27.339725 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8126 11:16:27.342017 Update DQM dly =985 (3 ,6, 25) DQM OEN =(3 ,3)
8127 11:16:27.345639 DramC Write-DBI on
8128 11:16:27.346093 ==
8129 11:16:27.349482 Dram Type= 6, Freq= 0, CH_0, rank 1
8130 11:16:27.352848 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8131 11:16:27.353412 ==
8132 11:16:27.353780
8133 11:16:27.354118
8134 11:16:27.355478 TX Vref Scan disable
8135 11:16:27.355933 == TX Byte 0 ==
8136 11:16:27.362630 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8137 11:16:27.363189 == TX Byte 1 ==
8138 11:16:27.368688 Update DQM dly =726 (2 ,6, 22) DQM OEN =(3 ,3)
8139 11:16:27.369249 DramC Write-DBI off
8140 11:16:27.369613
8141 11:16:27.369946 [DATLAT]
8142 11:16:27.372126 Freq=1600, CH0 RK1
8143 11:16:27.372582
8144 11:16:27.375448 DATLAT Default: 0xf
8145 11:16:27.375999 0, 0xFFFF, sum = 0
8146 11:16:27.378808 1, 0xFFFF, sum = 0
8147 11:16:27.379367 2, 0xFFFF, sum = 0
8148 11:16:27.381553 3, 0xFFFF, sum = 0
8149 11:16:27.382015 4, 0xFFFF, sum = 0
8150 11:16:27.385366 5, 0xFFFF, sum = 0
8151 11:16:27.386025 6, 0xFFFF, sum = 0
8152 11:16:27.388319 7, 0xFFFF, sum = 0
8153 11:16:27.388740 8, 0xFFFF, sum = 0
8154 11:16:27.392318 9, 0xFFFF, sum = 0
8155 11:16:27.392836 10, 0xFFFF, sum = 0
8156 11:16:27.394519 11, 0xFFFF, sum = 0
8157 11:16:27.394936 12, 0xFFFF, sum = 0
8158 11:16:27.398129 13, 0xFFFF, sum = 0
8159 11:16:27.398548 14, 0x0, sum = 1
8160 11:16:27.401379 15, 0x0, sum = 2
8161 11:16:27.401798 16, 0x0, sum = 3
8162 11:16:27.404972 17, 0x0, sum = 4
8163 11:16:27.405390 best_step = 15
8164 11:16:27.405715
8165 11:16:27.406018 ==
8166 11:16:27.408010 Dram Type= 6, Freq= 0, CH_0, rank 1
8167 11:16:27.414806 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8168 11:16:27.415320 ==
8169 11:16:27.415649 RX Vref Scan: 0
8170 11:16:27.415956
8171 11:16:27.417954 RX Vref 0 -> 0, step: 1
8172 11:16:27.418366
8173 11:16:27.421012 RX Delay 11 -> 252, step: 4
8174 11:16:27.424433 iDelay=191, Bit 0, Center 126 (75 ~ 178) 104
8175 11:16:27.427957 iDelay=191, Bit 1, Center 130 (79 ~ 182) 104
8176 11:16:27.434003 iDelay=191, Bit 2, Center 124 (75 ~ 174) 100
8177 11:16:27.437338 iDelay=191, Bit 3, Center 128 (79 ~ 178) 100
8178 11:16:27.440705 iDelay=191, Bit 4, Center 130 (83 ~ 178) 96
8179 11:16:27.444434 iDelay=191, Bit 5, Center 120 (67 ~ 174) 108
8180 11:16:27.447498 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8181 11:16:27.454679 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8182 11:16:27.457229 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8183 11:16:27.460752 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8184 11:16:27.464669 iDelay=191, Bit 10, Center 124 (71 ~ 178) 108
8185 11:16:27.466757 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8186 11:16:27.474069 iDelay=191, Bit 12, Center 128 (75 ~ 182) 108
8187 11:16:27.476940 iDelay=191, Bit 13, Center 130 (79 ~ 182) 104
8188 11:16:27.480270 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8189 11:16:27.484504 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8190 11:16:27.488825 ==
8191 11:16:27.491019 Dram Type= 6, Freq= 0, CH_0, rank 1
8192 11:16:27.493030 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8193 11:16:27.493492 ==
8194 11:16:27.493857 DQS Delay:
8195 11:16:27.496792 DQS0 = 0, DQS1 = 0
8196 11:16:27.497248 DQM Delay:
8197 11:16:27.499942 DQM0 = 128, DQM1 = 123
8198 11:16:27.500436 DQ Delay:
8199 11:16:27.502995 DQ0 =126, DQ1 =130, DQ2 =124, DQ3 =128
8200 11:16:27.506421 DQ4 =130, DQ5 =120, DQ6 =138, DQ7 =134
8201 11:16:27.509580 DQ8 =114, DQ9 =110, DQ10 =124, DQ11 =118
8202 11:16:27.512717 DQ12 =128, DQ13 =130, DQ14 =134, DQ15 =132
8203 11:16:27.513132
8204 11:16:27.513556
8205 11:16:27.513870
8206 11:16:27.516456 [DramC_TX_OE_Calibration] TA2
8207 11:16:27.519594 Original DQ_B0 (3 6) =30, OEN = 27
8208 11:16:27.523190 Original DQ_B1 (3 6) =30, OEN = 27
8209 11:16:27.525885 24, 0x0, End_B0=24 End_B1=24
8210 11:16:27.529448 25, 0x0, End_B0=25 End_B1=25
8211 11:16:27.532935 26, 0x0, End_B0=26 End_B1=26
8212 11:16:27.533465 27, 0x0, End_B0=27 End_B1=27
8213 11:16:27.536238 28, 0x0, End_B0=28 End_B1=28
8214 11:16:27.539384 29, 0x0, End_B0=29 End_B1=29
8215 11:16:27.542403 30, 0x0, End_B0=30 End_B1=30
8216 11:16:27.546997 31, 0x4141, End_B0=30 End_B1=30
8217 11:16:27.547525 Byte0 end_step=30 best_step=27
8218 11:16:27.549801 Byte1 end_step=30 best_step=27
8219 11:16:27.552916 Byte0 TX OE(2T, 0.5T) = (3, 3)
8220 11:16:27.555881 Byte1 TX OE(2T, 0.5T) = (3, 3)
8221 11:16:27.556419
8222 11:16:27.556745
8223 11:16:27.565662 [DQSOSCAuto] RK1, (LSB)MR18= 0x1210, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
8224 11:16:27.566224 CH0 RK1: MR19=303, MR18=1210
8225 11:16:27.572714 CH0_RK1: MR19=0x303, MR18=0x1210, DQSOSC=400, MR23=63, INC=23, DEC=15
8226 11:16:27.575677 [RxdqsGatingPostProcess] freq 1600
8227 11:16:27.582491 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8228 11:16:27.584996 best DQS0 dly(2T, 0.5T) = (1, 1)
8229 11:16:27.588853 best DQS1 dly(2T, 0.5T) = (1, 1)
8230 11:16:27.592196 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8231 11:16:27.595036 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8232 11:16:27.595496 best DQS0 dly(2T, 0.5T) = (1, 1)
8233 11:16:27.599097 best DQS1 dly(2T, 0.5T) = (1, 1)
8234 11:16:27.602786 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8235 11:16:27.605097 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8236 11:16:27.608258 Pre-setting of DQS Precalculation
8237 11:16:27.614797 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8238 11:16:27.615335 ==
8239 11:16:27.618124 Dram Type= 6, Freq= 0, CH_1, rank 0
8240 11:16:27.621471 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8241 11:16:27.621989 ==
8242 11:16:27.627985 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8243 11:16:27.631521 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8244 11:16:27.634209 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8245 11:16:27.641146 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8246 11:16:27.650322 [CA 0] Center 42 (12~72) winsize 61
8247 11:16:27.653905 [CA 1] Center 42 (12~72) winsize 61
8248 11:16:27.657082 [CA 2] Center 38 (9~67) winsize 59
8249 11:16:27.660184 [CA 3] Center 37 (8~66) winsize 59
8250 11:16:27.663580 [CA 4] Center 38 (8~68) winsize 61
8251 11:16:27.666602 [CA 5] Center 36 (7~66) winsize 60
8252 11:16:27.667163
8253 11:16:27.669802 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8254 11:16:27.670346
8255 11:16:27.676310 [CATrainingPosCal] consider 1 rank data
8256 11:16:27.677017 u2DelayCellTimex100 = 275/100 ps
8257 11:16:27.683343 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8258 11:16:27.686677 CA1 delay=42 (12~72),Diff = 6 PI (21 cell)
8259 11:16:27.689853 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8260 11:16:27.692877 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8261 11:16:27.696661 CA4 delay=38 (8~68),Diff = 2 PI (7 cell)
8262 11:16:27.700541 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8263 11:16:27.701128
8264 11:16:27.702757 CA PerBit enable=1, Macro0, CA PI delay=36
8265 11:16:27.703223
8266 11:16:27.706114 [CBTSetCACLKResult] CA Dly = 36
8267 11:16:27.708927 CS Dly: 8 (0~39)
8268 11:16:27.712308 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8269 11:16:27.715880 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8270 11:16:27.716334 ==
8271 11:16:27.719028 Dram Type= 6, Freq= 0, CH_1, rank 1
8272 11:16:27.725456 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8273 11:16:27.725873 ==
8274 11:16:27.729088 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8275 11:16:27.736225 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8276 11:16:27.738660 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8277 11:16:27.745761 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8278 11:16:27.753808 [CA 0] Center 42 (12~72) winsize 61
8279 11:16:27.757054 [CA 1] Center 42 (13~72) winsize 60
8280 11:16:27.760118 [CA 2] Center 38 (8~68) winsize 61
8281 11:16:27.763281 [CA 3] Center 37 (7~67) winsize 61
8282 11:16:27.766376 [CA 4] Center 38 (8~68) winsize 61
8283 11:16:27.769640 [CA 5] Center 37 (7~67) winsize 61
8284 11:16:27.770160
8285 11:16:27.772795 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8286 11:16:27.773211
8287 11:16:27.779838 [CATrainingPosCal] consider 2 rank data
8288 11:16:27.780393 u2DelayCellTimex100 = 275/100 ps
8289 11:16:27.786054 CA0 delay=42 (12~72),Diff = 6 PI (21 cell)
8290 11:16:27.789448 CA1 delay=42 (13~72),Diff = 6 PI (21 cell)
8291 11:16:27.792669 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8292 11:16:27.795893 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8293 11:16:27.799039 CA4 delay=38 (8~68),Diff = 2 PI (7 cell)
8294 11:16:27.802419 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8295 11:16:27.802825
8296 11:16:27.805779 CA PerBit enable=1, Macro0, CA PI delay=36
8297 11:16:27.806184
8298 11:16:27.809024 [CBTSetCACLKResult] CA Dly = 36
8299 11:16:27.812359 CS Dly: 9 (0~42)
8300 11:16:27.815230 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8301 11:16:27.819158 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8302 11:16:27.819665
8303 11:16:27.821901 ----->DramcWriteLeveling(PI) begin...
8304 11:16:27.825059 ==
8305 11:16:27.825472 Dram Type= 6, Freq= 0, CH_1, rank 0
8306 11:16:27.832139 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8307 11:16:27.832657 ==
8308 11:16:27.835878 Write leveling (Byte 0): 24 => 24
8309 11:16:27.838470 Write leveling (Byte 1): 28 => 28
8310 11:16:27.842027 DramcWriteLeveling(PI) end<-----
8311 11:16:27.842717
8312 11:16:27.843059 ==
8313 11:16:27.845125 Dram Type= 6, Freq= 0, CH_1, rank 0
8314 11:16:27.848851 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8315 11:16:27.849285 ==
8316 11:16:27.851505 [Gating] SW mode calibration
8317 11:16:27.858680 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8318 11:16:27.864963 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8319 11:16:27.868142 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8320 11:16:27.871451 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8321 11:16:27.878187 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8322 11:16:27.881338 1 4 12 | B1->B0 | 2525 3434 | 0 0 | (0 0) (0 0)
8323 11:16:27.884901 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8324 11:16:27.891411 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8325 11:16:27.894925 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8326 11:16:27.897843 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8327 11:16:27.904217 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8328 11:16:27.907619 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8329 11:16:27.911180 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8330 11:16:27.917374 1 5 12 | B1->B0 | 3333 2424 | 0 0 | (0 1) (0 0)
8331 11:16:27.920944 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8332 11:16:27.924009 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8333 11:16:27.930639 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8334 11:16:27.934277 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8335 11:16:27.937641 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8336 11:16:27.943797 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8337 11:16:27.947275 1 6 8 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
8338 11:16:27.950524 1 6 12 | B1->B0 | 2727 4141 | 1 1 | (0 0) (0 0)
8339 11:16:27.956907 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8340 11:16:27.960156 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8341 11:16:27.963684 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8342 11:16:27.970142 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8343 11:16:27.973466 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8344 11:16:27.976654 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8345 11:16:27.983302 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8346 11:16:27.986424 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8347 11:16:27.989713 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8348 11:16:27.996634 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8349 11:16:27.999626 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8350 11:16:28.003175 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8351 11:16:28.010094 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8352 11:16:28.012907 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8353 11:16:28.016938 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8354 11:16:28.022395 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8355 11:16:28.025533 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8356 11:16:28.029124 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8357 11:16:28.035480 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8358 11:16:28.039272 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8359 11:16:28.042319 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8360 11:16:28.049135 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8361 11:16:28.052265 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8362 11:16:28.055694 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8363 11:16:28.061944 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8364 11:16:28.065397 Total UI for P1: 0, mck2ui 16
8365 11:16:28.068390 best dqsien dly found for B0: ( 1, 9, 10)
8366 11:16:28.072186 Total UI for P1: 0, mck2ui 16
8367 11:16:28.075255 best dqsien dly found for B1: ( 1, 9, 12)
8368 11:16:28.078904 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8369 11:16:28.082089 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8370 11:16:28.082616
8371 11:16:28.084709 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8372 11:16:28.088460 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8373 11:16:28.091750 [Gating] SW calibration Done
8374 11:16:28.092304 ==
8375 11:16:28.095097 Dram Type= 6, Freq= 0, CH_1, rank 0
8376 11:16:28.097974 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8377 11:16:28.098400 ==
8378 11:16:28.101355 RX Vref Scan: 0
8379 11:16:28.101874
8380 11:16:28.104400 RX Vref 0 -> 0, step: 1
8381 11:16:28.104818
8382 11:16:28.105149 RX Delay 0 -> 252, step: 8
8383 11:16:28.111519 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8384 11:16:28.115051 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8385 11:16:28.117935 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8386 11:16:28.121085 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8387 11:16:28.127646 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8388 11:16:28.131052 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8389 11:16:28.134455 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8390 11:16:28.137343 iDelay=200, Bit 7, Center 127 (72 ~ 183) 112
8391 11:16:28.140938 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8392 11:16:28.147967 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8393 11:16:28.151877 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8394 11:16:28.154058 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8395 11:16:28.157266 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8396 11:16:28.160693 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8397 11:16:28.166960 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8398 11:16:28.170149 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8399 11:16:28.170611 ==
8400 11:16:28.173778 Dram Type= 6, Freq= 0, CH_1, rank 0
8401 11:16:28.176874 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8402 11:16:28.177301 ==
8403 11:16:28.180284 DQS Delay:
8404 11:16:28.180818 DQS0 = 0, DQS1 = 0
8405 11:16:28.183755 DQM Delay:
8406 11:16:28.184192 DQM0 = 134, DQM1 = 130
8407 11:16:28.184527 DQ Delay:
8408 11:16:28.190036 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8409 11:16:28.193586 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =127
8410 11:16:28.196339 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =123
8411 11:16:28.199992 DQ12 =139, DQ13 =143, DQ14 =135, DQ15 =135
8412 11:16:28.200542
8413 11:16:28.200872
8414 11:16:28.201181 ==
8415 11:16:28.202985 Dram Type= 6, Freq= 0, CH_1, rank 0
8416 11:16:28.206736 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8417 11:16:28.207155 ==
8418 11:16:28.207486
8419 11:16:28.207790
8420 11:16:28.209813 TX Vref Scan disable
8421 11:16:28.213016 == TX Byte 0 ==
8422 11:16:28.216655 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8423 11:16:28.219620 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8424 11:16:28.222498 == TX Byte 1 ==
8425 11:16:28.225970 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
8426 11:16:28.229597 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8427 11:16:28.230130 ==
8428 11:16:28.233157 Dram Type= 6, Freq= 0, CH_1, rank 0
8429 11:16:28.239253 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8430 11:16:28.239779 ==
8431 11:16:28.252873
8432 11:16:28.255680 TX Vref early break, caculate TX vref
8433 11:16:28.258774 TX Vref=16, minBit 8, minWin=21, winSum=368
8434 11:16:28.262260 TX Vref=18, minBit 8, minWin=22, winSum=376
8435 11:16:28.265161 TX Vref=20, minBit 8, minWin=23, winSum=387
8436 11:16:28.269019 TX Vref=22, minBit 8, minWin=23, winSum=394
8437 11:16:28.272196 TX Vref=24, minBit 3, minWin=24, winSum=405
8438 11:16:28.278475 TX Vref=26, minBit 8, minWin=24, winSum=412
8439 11:16:28.282570 TX Vref=28, minBit 0, minWin=25, winSum=418
8440 11:16:28.285244 TX Vref=30, minBit 0, minWin=25, winSum=416
8441 11:16:28.288332 TX Vref=32, minBit 0, minWin=25, winSum=413
8442 11:16:28.292092 TX Vref=34, minBit 9, minWin=23, winSum=401
8443 11:16:28.298393 TX Vref=36, minBit 0, minWin=23, winSum=386
8444 11:16:28.301476 [TxChooseVref] Worse bit 0, Min win 25, Win sum 418, Final Vref 28
8445 11:16:28.301904
8446 11:16:28.305111 Final TX Range 0 Vref 28
8447 11:16:28.305531
8448 11:16:28.305865 ==
8449 11:16:28.308432 Dram Type= 6, Freq= 0, CH_1, rank 0
8450 11:16:28.311385 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8451 11:16:28.314684 ==
8452 11:16:28.315205
8453 11:16:28.315659
8454 11:16:28.315982 TX Vref Scan disable
8455 11:16:28.321605 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8456 11:16:28.322134 == TX Byte 0 ==
8457 11:16:28.324615 u2DelayCellOfst[0]=14 cells (4 PI)
8458 11:16:28.328328 u2DelayCellOfst[1]=7 cells (2 PI)
8459 11:16:28.331188 u2DelayCellOfst[2]=0 cells (0 PI)
8460 11:16:28.335339 u2DelayCellOfst[3]=3 cells (1 PI)
8461 11:16:28.338192 u2DelayCellOfst[4]=7 cells (2 PI)
8462 11:16:28.342366 u2DelayCellOfst[5]=14 cells (4 PI)
8463 11:16:28.344206 u2DelayCellOfst[6]=14 cells (4 PI)
8464 11:16:28.347943 u2DelayCellOfst[7]=3 cells (1 PI)
8465 11:16:28.351107 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8466 11:16:28.354388 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8467 11:16:28.357534 == TX Byte 1 ==
8468 11:16:28.361133 u2DelayCellOfst[8]=0 cells (0 PI)
8469 11:16:28.364588 u2DelayCellOfst[9]=0 cells (0 PI)
8470 11:16:28.367998 u2DelayCellOfst[10]=10 cells (3 PI)
8471 11:16:28.370651 u2DelayCellOfst[11]=3 cells (1 PI)
8472 11:16:28.373819 u2DelayCellOfst[12]=10 cells (3 PI)
8473 11:16:28.377428 u2DelayCellOfst[13]=14 cells (4 PI)
8474 11:16:28.380462 u2DelayCellOfst[14]=14 cells (4 PI)
8475 11:16:28.383635 u2DelayCellOfst[15]=14 cells (4 PI)
8476 11:16:28.387204 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8477 11:16:28.390133 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8478 11:16:28.393821 DramC Write-DBI on
8479 11:16:28.394346 ==
8480 11:16:28.397223 Dram Type= 6, Freq= 0, CH_1, rank 0
8481 11:16:28.400114 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8482 11:16:28.400538 ==
8483 11:16:28.400872
8484 11:16:28.401178
8485 11:16:28.403850 TX Vref Scan disable
8486 11:16:28.404313 == TX Byte 0 ==
8487 11:16:28.410445 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8488 11:16:28.410865 == TX Byte 1 ==
8489 11:16:28.416601 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8490 11:16:28.417113 DramC Write-DBI off
8491 11:16:28.417459
8492 11:16:28.417767 [DATLAT]
8493 11:16:28.420186 Freq=1600, CH1 RK0
8494 11:16:28.420707
8495 11:16:28.423424 DATLAT Default: 0xf
8496 11:16:28.423937 0, 0xFFFF, sum = 0
8497 11:16:28.427064 1, 0xFFFF, sum = 0
8498 11:16:28.427584 2, 0xFFFF, sum = 0
8499 11:16:28.430404 3, 0xFFFF, sum = 0
8500 11:16:28.430936 4, 0xFFFF, sum = 0
8501 11:16:28.433461 5, 0xFFFF, sum = 0
8502 11:16:28.433984 6, 0xFFFF, sum = 0
8503 11:16:28.436139 7, 0xFFFF, sum = 0
8504 11:16:28.436562 8, 0xFFFF, sum = 0
8505 11:16:28.439682 9, 0xFFFF, sum = 0
8506 11:16:28.440245 10, 0xFFFF, sum = 0
8507 11:16:28.443961 11, 0xFFFF, sum = 0
8508 11:16:28.444544 12, 0xFFFF, sum = 0
8509 11:16:28.446593 13, 0xFFFF, sum = 0
8510 11:16:28.447112 14, 0x0, sum = 1
8511 11:16:28.449444 15, 0x0, sum = 2
8512 11:16:28.449867 16, 0x0, sum = 3
8513 11:16:28.453099 17, 0x0, sum = 4
8514 11:16:28.453520 best_step = 15
8515 11:16:28.453849
8516 11:16:28.454155 ==
8517 11:16:28.456793 Dram Type= 6, Freq= 0, CH_1, rank 0
8518 11:16:28.462926 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8519 11:16:28.463449 ==
8520 11:16:28.463787 RX Vref Scan: 1
8521 11:16:28.464145
8522 11:16:28.466488 Set Vref Range= 24 -> 127
8523 11:16:28.467002
8524 11:16:28.469428 RX Vref 24 -> 127, step: 1
8525 11:16:28.469952
8526 11:16:28.472616 RX Delay 19 -> 252, step: 4
8527 11:16:28.473134
8528 11:16:28.476003 Set Vref, RX VrefLevel [Byte0]: 24
8529 11:16:28.479704 [Byte1]: 24
8530 11:16:28.480286
8531 11:16:28.482492 Set Vref, RX VrefLevel [Byte0]: 25
8532 11:16:28.486088 [Byte1]: 25
8533 11:16:28.486512
8534 11:16:28.488937 Set Vref, RX VrefLevel [Byte0]: 26
8535 11:16:28.492624 [Byte1]: 26
8536 11:16:28.495786
8537 11:16:28.496350 Set Vref, RX VrefLevel [Byte0]: 27
8538 11:16:28.499091 [Byte1]: 27
8539 11:16:28.503551
8540 11:16:28.504117 Set Vref, RX VrefLevel [Byte0]: 28
8541 11:16:28.506542 [Byte1]: 28
8542 11:16:28.510762
8543 11:16:28.511206 Set Vref, RX VrefLevel [Byte0]: 29
8544 11:16:28.513941 [Byte1]: 29
8545 11:16:28.518695
8546 11:16:28.519207 Set Vref, RX VrefLevel [Byte0]: 30
8547 11:16:28.521996 [Byte1]: 30
8548 11:16:28.526387
8549 11:16:28.526906 Set Vref, RX VrefLevel [Byte0]: 31
8550 11:16:28.529346 [Byte1]: 31
8551 11:16:28.533604
8552 11:16:28.534119 Set Vref, RX VrefLevel [Byte0]: 32
8553 11:16:28.537506 [Byte1]: 32
8554 11:16:28.541320
8555 11:16:28.541771 Set Vref, RX VrefLevel [Byte0]: 33
8556 11:16:28.544561 [Byte1]: 33
8557 11:16:28.548731
8558 11:16:28.549246 Set Vref, RX VrefLevel [Byte0]: 34
8559 11:16:28.552227 [Byte1]: 34
8560 11:16:28.556242
8561 11:16:28.556825 Set Vref, RX VrefLevel [Byte0]: 35
8562 11:16:28.559652 [Byte1]: 35
8563 11:16:28.564587
8564 11:16:28.565141 Set Vref, RX VrefLevel [Byte0]: 36
8565 11:16:28.567315 [Byte1]: 36
8566 11:16:28.572327
8567 11:16:28.572901 Set Vref, RX VrefLevel [Byte0]: 37
8568 11:16:28.574642 [Byte1]: 37
8569 11:16:28.579523
8570 11:16:28.580162 Set Vref, RX VrefLevel [Byte0]: 38
8571 11:16:28.582348 [Byte1]: 38
8572 11:16:28.586590
8573 11:16:28.587055 Set Vref, RX VrefLevel [Byte0]: 39
8574 11:16:28.590165 [Byte1]: 39
8575 11:16:28.594143
8576 11:16:28.594657 Set Vref, RX VrefLevel [Byte0]: 40
8577 11:16:28.597341 [Byte1]: 40
8578 11:16:28.601514
8579 11:16:28.602025 Set Vref, RX VrefLevel [Byte0]: 41
8580 11:16:28.604804 [Byte1]: 41
8581 11:16:28.609261
8582 11:16:28.609681 Set Vref, RX VrefLevel [Byte0]: 42
8583 11:16:28.612501 [Byte1]: 42
8584 11:16:28.616525
8585 11:16:28.616970 Set Vref, RX VrefLevel [Byte0]: 43
8586 11:16:28.620266 [Byte1]: 43
8587 11:16:28.624786
8588 11:16:28.625234 Set Vref, RX VrefLevel [Byte0]: 44
8589 11:16:28.627634 [Byte1]: 44
8590 11:16:28.632217
8591 11:16:28.632724 Set Vref, RX VrefLevel [Byte0]: 45
8592 11:16:28.635535 [Byte1]: 45
8593 11:16:28.639939
8594 11:16:28.640498 Set Vref, RX VrefLevel [Byte0]: 46
8595 11:16:28.643365 [Byte1]: 46
8596 11:16:28.647579
8597 11:16:28.648154 Set Vref, RX VrefLevel [Byte0]: 47
8598 11:16:28.650598 [Byte1]: 47
8599 11:16:28.655848
8600 11:16:28.656408 Set Vref, RX VrefLevel [Byte0]: 48
8601 11:16:28.658156 [Byte1]: 48
8602 11:16:28.662112
8603 11:16:28.662629 Set Vref, RX VrefLevel [Byte0]: 49
8604 11:16:28.665686 [Byte1]: 49
8605 11:16:28.670233
8606 11:16:28.670749 Set Vref, RX VrefLevel [Byte0]: 50
8607 11:16:28.673141 [Byte1]: 50
8608 11:16:28.677412
8609 11:16:28.677928 Set Vref, RX VrefLevel [Byte0]: 51
8610 11:16:28.681263 [Byte1]: 51
8611 11:16:28.685444
8612 11:16:28.685903 Set Vref, RX VrefLevel [Byte0]: 52
8613 11:16:28.688300 [Byte1]: 52
8614 11:16:28.692562
8615 11:16:28.693079 Set Vref, RX VrefLevel [Byte0]: 53
8616 11:16:28.696194 [Byte1]: 53
8617 11:16:28.700525
8618 11:16:28.701047 Set Vref, RX VrefLevel [Byte0]: 54
8619 11:16:28.703510 [Byte1]: 54
8620 11:16:28.707787
8621 11:16:28.708334 Set Vref, RX VrefLevel [Byte0]: 55
8622 11:16:28.710594 [Byte1]: 55
8623 11:16:28.715602
8624 11:16:28.716334 Set Vref, RX VrefLevel [Byte0]: 56
8625 11:16:28.718491 [Byte1]: 56
8626 11:16:28.722761
8627 11:16:28.723272 Set Vref, RX VrefLevel [Byte0]: 57
8628 11:16:28.726002 [Byte1]: 57
8629 11:16:28.730378
8630 11:16:28.730894 Set Vref, RX VrefLevel [Byte0]: 58
8631 11:16:28.734023 [Byte1]: 58
8632 11:16:28.738611
8633 11:16:28.739138 Set Vref, RX VrefLevel [Byte0]: 59
8634 11:16:28.741254 [Byte1]: 59
8635 11:16:28.745576
8636 11:16:28.746096 Set Vref, RX VrefLevel [Byte0]: 60
8637 11:16:28.748916 [Byte1]: 60
8638 11:16:28.753076
8639 11:16:28.753590 Set Vref, RX VrefLevel [Byte0]: 61
8640 11:16:28.756581 [Byte1]: 61
8641 11:16:28.760692
8642 11:16:28.761208 Set Vref, RX VrefLevel [Byte0]: 62
8643 11:16:28.763866 [Byte1]: 62
8644 11:16:28.768632
8645 11:16:28.769150 Set Vref, RX VrefLevel [Byte0]: 63
8646 11:16:28.772384 [Byte1]: 63
8647 11:16:28.776187
8648 11:16:28.776692 Set Vref, RX VrefLevel [Byte0]: 64
8649 11:16:28.779482 [Byte1]: 64
8650 11:16:28.783737
8651 11:16:28.784300 Set Vref, RX VrefLevel [Byte0]: 65
8652 11:16:28.786334 [Byte1]: 65
8653 11:16:28.790602
8654 11:16:28.791062 Set Vref, RX VrefLevel [Byte0]: 66
8655 11:16:28.793920 [Byte1]: 66
8656 11:16:28.798944
8657 11:16:28.799458 Set Vref, RX VrefLevel [Byte0]: 67
8658 11:16:28.801950 [Byte1]: 67
8659 11:16:28.806261
8660 11:16:28.806957 Set Vref, RX VrefLevel [Byte0]: 68
8661 11:16:28.809413 [Byte1]: 68
8662 11:16:28.814263
8663 11:16:28.814783 Set Vref, RX VrefLevel [Byte0]: 69
8664 11:16:28.816732 [Byte1]: 69
8665 11:16:28.822261
8666 11:16:28.822817 Set Vref, RX VrefLevel [Byte0]: 70
8667 11:16:28.824566 [Byte1]: 70
8668 11:16:28.828665
8669 11:16:28.829077 Set Vref, RX VrefLevel [Byte0]: 71
8670 11:16:28.832067 [Byte1]: 71
8671 11:16:28.836657
8672 11:16:28.837185 Final RX Vref Byte 0 = 59 to rank0
8673 11:16:28.839630 Final RX Vref Byte 1 = 60 to rank0
8674 11:16:28.843367 Final RX Vref Byte 0 = 59 to rank1
8675 11:16:28.846055 Final RX Vref Byte 1 = 60 to rank1==
8676 11:16:28.849980 Dram Type= 6, Freq= 0, CH_1, rank 0
8677 11:16:28.856178 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8678 11:16:28.856697 ==
8679 11:16:28.857028 DQS Delay:
8680 11:16:28.859230 DQS0 = 0, DQS1 = 0
8681 11:16:28.859644 DQM Delay:
8682 11:16:28.859970 DQM0 = 132, DQM1 = 128
8683 11:16:28.862901 DQ Delay:
8684 11:16:28.866098 DQ0 =138, DQ1 =128, DQ2 =118, DQ3 =132
8685 11:16:28.869609 DQ4 =128, DQ5 =142, DQ6 =144, DQ7 =126
8686 11:16:28.873105 DQ8 =114, DQ9 =116, DQ10 =128, DQ11 =120
8687 11:16:28.876136 DQ12 =138, DQ13 =138, DQ14 =136, DQ15 =138
8688 11:16:28.876554
8689 11:16:28.876880
8690 11:16:28.877181
8691 11:16:28.879260 [DramC_TX_OE_Calibration] TA2
8692 11:16:28.883091 Original DQ_B0 (3 6) =30, OEN = 27
8693 11:16:28.885577 Original DQ_B1 (3 6) =30, OEN = 27
8694 11:16:28.889717 24, 0x0, End_B0=24 End_B1=24
8695 11:16:28.892406 25, 0x0, End_B0=25 End_B1=25
8696 11:16:28.892933 26, 0x0, End_B0=26 End_B1=26
8697 11:16:28.895485 27, 0x0, End_B0=27 End_B1=27
8698 11:16:28.898721 28, 0x0, End_B0=28 End_B1=28
8699 11:16:28.901985 29, 0x0, End_B0=29 End_B1=29
8700 11:16:28.905127 30, 0x0, End_B0=30 End_B1=30
8701 11:16:28.905550 31, 0x4141, End_B0=30 End_B1=30
8702 11:16:28.908260 Byte0 end_step=30 best_step=27
8703 11:16:28.912258 Byte1 end_step=30 best_step=27
8704 11:16:28.915397 Byte0 TX OE(2T, 0.5T) = (3, 3)
8705 11:16:28.918609 Byte1 TX OE(2T, 0.5T) = (3, 3)
8706 11:16:28.919128
8707 11:16:28.919463
8708 11:16:28.925410 [DQSOSCAuto] RK0, (LSB)MR18= 0x913, (MSB)MR19= 0x303, tDQSOscB0 = 400 ps tDQSOscB1 = 405 ps
8709 11:16:28.928120 CH1 RK0: MR19=303, MR18=913
8710 11:16:28.935142 CH1_RK0: MR19=0x303, MR18=0x913, DQSOSC=400, MR23=63, INC=23, DEC=15
8711 11:16:28.935692
8712 11:16:28.938056 ----->DramcWriteLeveling(PI) begin...
8713 11:16:28.938474 ==
8714 11:16:28.941404 Dram Type= 6, Freq= 0, CH_1, rank 1
8715 11:16:28.944744 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8716 11:16:28.945248 ==
8717 11:16:28.947998 Write leveling (Byte 0): 26 => 26
8718 11:16:28.951502 Write leveling (Byte 1): 26 => 26
8719 11:16:28.954757 DramcWriteLeveling(PI) end<-----
8720 11:16:28.955274
8721 11:16:28.955604 ==
8722 11:16:28.958348 Dram Type= 6, Freq= 0, CH_1, rank 1
8723 11:16:28.964425 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8724 11:16:28.964967 ==
8725 11:16:28.965315 [Gating] SW mode calibration
8726 11:16:28.974670 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8727 11:16:28.978276 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8728 11:16:28.981858 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8729 11:16:28.987701 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8730 11:16:28.990713 1 4 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8731 11:16:28.997862 1 4 12 | B1->B0 | 2524 3434 | 1 1 | (1 1) (1 1)
8732 11:16:29.001130 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8733 11:16:29.003836 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8734 11:16:29.010757 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8735 11:16:29.014210 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8736 11:16:29.017321 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8737 11:16:29.024060 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8738 11:16:29.027379 1 5 8 | B1->B0 | 3434 2323 | 1 0 | (1 0) (1 0)
8739 11:16:29.030286 1 5 12 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8740 11:16:29.037730 1 5 16 | B1->B0 | 2424 2323 | 1 0 | (1 0) (0 0)
8741 11:16:29.040028 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8742 11:16:29.043299 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8743 11:16:29.049963 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8744 11:16:29.053337 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8745 11:16:29.056684 1 6 4 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8746 11:16:29.063131 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8747 11:16:29.066114 1 6 12 | B1->B0 | 3232 4646 | 0 0 | (1 1) (0 0)
8748 11:16:29.070018 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8749 11:16:29.076298 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8750 11:16:29.079601 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8751 11:16:29.083200 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8752 11:16:29.089217 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8753 11:16:29.092536 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8754 11:16:29.096455 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8755 11:16:29.102320 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8756 11:16:29.105718 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8757 11:16:29.109244 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8758 11:16:29.115690 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8759 11:16:29.118945 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8760 11:16:29.122339 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8761 11:16:29.128650 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8762 11:16:29.131882 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8763 11:16:29.136013 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8764 11:16:29.143032 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8765 11:16:29.145073 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8766 11:16:29.148493 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8767 11:16:29.155088 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8768 11:16:29.158575 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8769 11:16:29.162332 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8770 11:16:29.168288 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8771 11:16:29.171663 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8772 11:16:29.175151 Total UI for P1: 0, mck2ui 16
8773 11:16:29.178146 best dqsien dly found for B0: ( 1, 9, 6)
8774 11:16:29.181438 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8775 11:16:29.184844 Total UI for P1: 0, mck2ui 16
8776 11:16:29.188515 best dqsien dly found for B1: ( 1, 9, 12)
8777 11:16:29.191313 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8778 11:16:29.195503 best DQS1 dly(MCK, UI, PI) = (1, 9, 12)
8779 11:16:29.196024
8780 11:16:29.201132 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8781 11:16:29.205332 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 12)
8782 11:16:29.208020 [Gating] SW calibration Done
8783 11:16:29.208473 ==
8784 11:16:29.211326 Dram Type= 6, Freq= 0, CH_1, rank 1
8785 11:16:29.214549 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8786 11:16:29.215073 ==
8787 11:16:29.215405 RX Vref Scan: 0
8788 11:16:29.215710
8789 11:16:29.217742 RX Vref 0 -> 0, step: 1
8790 11:16:29.218260
8791 11:16:29.221335 RX Delay 0 -> 252, step: 8
8792 11:16:29.224189 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8793 11:16:29.228432 iDelay=200, Bit 1, Center 131 (72 ~ 191) 120
8794 11:16:29.234473 iDelay=200, Bit 2, Center 119 (64 ~ 175) 112
8795 11:16:29.237571 iDelay=200, Bit 3, Center 131 (72 ~ 191) 120
8796 11:16:29.240713 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8797 11:16:29.244322 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8798 11:16:29.247705 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8799 11:16:29.254507 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8800 11:16:29.258160 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8801 11:16:29.260492 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8802 11:16:29.263722 iDelay=200, Bit 10, Center 135 (80 ~ 191) 112
8803 11:16:29.267266 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8804 11:16:29.273889 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8805 11:16:29.278197 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8806 11:16:29.279950 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8807 11:16:29.283571 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8808 11:16:29.283984 ==
8809 11:16:29.286690 Dram Type= 6, Freq= 0, CH_1, rank 1
8810 11:16:29.293907 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8811 11:16:29.294439 ==
8812 11:16:29.294777 DQS Delay:
8813 11:16:29.296911 DQS0 = 0, DQS1 = 0
8814 11:16:29.297393 DQM Delay:
8815 11:16:29.300146 DQM0 = 133, DQM1 = 131
8816 11:16:29.300657 DQ Delay:
8817 11:16:29.303585 DQ0 =135, DQ1 =131, DQ2 =119, DQ3 =131
8818 11:16:29.306738 DQ4 =135, DQ5 =143, DQ6 =139, DQ7 =135
8819 11:16:29.309997 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =123
8820 11:16:29.313075 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8821 11:16:29.313500
8822 11:16:29.313860
8823 11:16:29.314171 ==
8824 11:16:29.317079 Dram Type= 6, Freq= 0, CH_1, rank 1
8825 11:16:29.323165 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8826 11:16:29.323684 ==
8827 11:16:29.324021
8828 11:16:29.324366
8829 11:16:29.324660 TX Vref Scan disable
8830 11:16:29.326463 == TX Byte 0 ==
8831 11:16:29.329796 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8832 11:16:29.336589 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8833 11:16:29.337105 == TX Byte 1 ==
8834 11:16:29.340028 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8835 11:16:29.346185 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8836 11:16:29.346712 ==
8837 11:16:29.350133 Dram Type= 6, Freq= 0, CH_1, rank 1
8838 11:16:29.352561 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8839 11:16:29.352982 ==
8840 11:16:29.367517
8841 11:16:29.370588 TX Vref early break, caculate TX vref
8842 11:16:29.374059 TX Vref=16, minBit 9, minWin=22, winSum=377
8843 11:16:29.378083 TX Vref=18, minBit 9, minWin=22, winSum=383
8844 11:16:29.380661 TX Vref=20, minBit 9, minWin=22, winSum=393
8845 11:16:29.383790 TX Vref=22, minBit 9, minWin=23, winSum=401
8846 11:16:29.387289 TX Vref=24, minBit 9, minWin=24, winSum=408
8847 11:16:29.393743 TX Vref=26, minBit 9, minWin=24, winSum=410
8848 11:16:29.397383 TX Vref=28, minBit 1, minWin=25, winSum=415
8849 11:16:29.400423 TX Vref=30, minBit 8, minWin=24, winSum=414
8850 11:16:29.403891 TX Vref=32, minBit 0, minWin=25, winSum=408
8851 11:16:29.407339 TX Vref=34, minBit 0, minWin=24, winSum=399
8852 11:16:29.413337 TX Vref=36, minBit 8, minWin=23, winSum=396
8853 11:16:29.416492 TX Vref=38, minBit 8, minWin=22, winSum=390
8854 11:16:29.420018 [TxChooseVref] Worse bit 1, Min win 25, Win sum 415, Final Vref 28
8855 11:16:29.423355
8856 11:16:29.423886 Final TX Range 0 Vref 28
8857 11:16:29.424291
8858 11:16:29.424606 ==
8859 11:16:29.426635 Dram Type= 6, Freq= 0, CH_1, rank 1
8860 11:16:29.432825 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8861 11:16:29.433388 ==
8862 11:16:29.433761
8863 11:16:29.434102
8864 11:16:29.434424 TX Vref Scan disable
8865 11:16:29.440889 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8866 11:16:29.441411 == TX Byte 0 ==
8867 11:16:29.444265 u2DelayCellOfst[0]=14 cells (4 PI)
8868 11:16:29.446905 u2DelayCellOfst[1]=10 cells (3 PI)
8869 11:16:29.450102 u2DelayCellOfst[2]=0 cells (0 PI)
8870 11:16:29.453431 u2DelayCellOfst[3]=7 cells (2 PI)
8871 11:16:29.456897 u2DelayCellOfst[4]=7 cells (2 PI)
8872 11:16:29.460276 u2DelayCellOfst[5]=14 cells (4 PI)
8873 11:16:29.463288 u2DelayCellOfst[6]=17 cells (5 PI)
8874 11:16:29.467505 u2DelayCellOfst[7]=7 cells (2 PI)
8875 11:16:29.469940 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8876 11:16:29.473063 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8877 11:16:29.476599 == TX Byte 1 ==
8878 11:16:29.479451 u2DelayCellOfst[8]=0 cells (0 PI)
8879 11:16:29.483329 u2DelayCellOfst[9]=7 cells (2 PI)
8880 11:16:29.487057 u2DelayCellOfst[10]=14 cells (4 PI)
8881 11:16:29.489791 u2DelayCellOfst[11]=7 cells (2 PI)
8882 11:16:29.493319 u2DelayCellOfst[12]=17 cells (5 PI)
8883 11:16:29.496162 u2DelayCellOfst[13]=21 cells (6 PI)
8884 11:16:29.499591 u2DelayCellOfst[14]=21 cells (6 PI)
8885 11:16:29.503221 u2DelayCellOfst[15]=21 cells (6 PI)
8886 11:16:29.506150 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8887 11:16:29.509505 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8888 11:16:29.512441 DramC Write-DBI on
8889 11:16:29.512857 ==
8890 11:16:29.515958 Dram Type= 6, Freq= 0, CH_1, rank 1
8891 11:16:29.519083 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8892 11:16:29.519609 ==
8893 11:16:29.519947
8894 11:16:29.520319
8895 11:16:29.522228 TX Vref Scan disable
8896 11:16:29.525688 == TX Byte 0 ==
8897 11:16:29.529146 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8898 11:16:29.529566 == TX Byte 1 ==
8899 11:16:29.535988 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
8900 11:16:29.536542 DramC Write-DBI off
8901 11:16:29.536878
8902 11:16:29.537188 [DATLAT]
8903 11:16:29.538613 Freq=1600, CH1 RK1
8904 11:16:29.539033
8905 11:16:29.542657 DATLAT Default: 0xf
8906 11:16:29.543179 0, 0xFFFF, sum = 0
8907 11:16:29.545719 1, 0xFFFF, sum = 0
8908 11:16:29.546252 2, 0xFFFF, sum = 0
8909 11:16:29.548688 3, 0xFFFF, sum = 0
8910 11:16:29.549217 4, 0xFFFF, sum = 0
8911 11:16:29.552451 5, 0xFFFF, sum = 0
8912 11:16:29.552983 6, 0xFFFF, sum = 0
8913 11:16:29.555847 7, 0xFFFF, sum = 0
8914 11:16:29.556405 8, 0xFFFF, sum = 0
8915 11:16:29.559012 9, 0xFFFF, sum = 0
8916 11:16:29.559535 10, 0xFFFF, sum = 0
8917 11:16:29.562202 11, 0xFFFF, sum = 0
8918 11:16:29.565221 12, 0xFFFF, sum = 0
8919 11:16:29.565752 13, 0xFFFF, sum = 0
8920 11:16:29.568244 14, 0x0, sum = 1
8921 11:16:29.568770 15, 0x0, sum = 2
8922 11:16:29.569109 16, 0x0, sum = 3
8923 11:16:29.571796 17, 0x0, sum = 4
8924 11:16:29.572557 best_step = 15
8925 11:16:29.572926
8926 11:16:29.575209 ==
8927 11:16:29.578606 Dram Type= 6, Freq= 0, CH_1, rank 1
8928 11:16:29.581437 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8929 11:16:29.581966 ==
8930 11:16:29.582313 RX Vref Scan: 0
8931 11:16:29.582630
8932 11:16:29.584610 RX Vref 0 -> 0, step: 1
8933 11:16:29.585031
8934 11:16:29.588156 RX Delay 19 -> 252, step: 4
8935 11:16:29.590946 iDelay=195, Bit 0, Center 134 (83 ~ 186) 104
8936 11:16:29.594478 iDelay=195, Bit 1, Center 130 (79 ~ 182) 104
8937 11:16:29.601747 iDelay=195, Bit 2, Center 120 (67 ~ 174) 108
8938 11:16:29.604606 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8939 11:16:29.607658 iDelay=195, Bit 4, Center 128 (75 ~ 182) 108
8940 11:16:29.611012 iDelay=195, Bit 5, Center 144 (95 ~ 194) 100
8941 11:16:29.617370 iDelay=195, Bit 6, Center 140 (87 ~ 194) 108
8942 11:16:29.621144 iDelay=195, Bit 7, Center 130 (79 ~ 182) 104
8943 11:16:29.624264 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8944 11:16:29.627981 iDelay=195, Bit 9, Center 116 (63 ~ 170) 108
8945 11:16:29.631114 iDelay=195, Bit 10, Center 128 (75 ~ 182) 108
8946 11:16:29.637687 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8947 11:16:29.641252 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
8948 11:16:29.643908 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
8949 11:16:29.647377 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
8950 11:16:29.650483 iDelay=195, Bit 15, Center 138 (87 ~ 190) 104
8951 11:16:29.654018 ==
8952 11:16:29.657660 Dram Type= 6, Freq= 0, CH_1, rank 1
8953 11:16:29.660911 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8954 11:16:29.661502 ==
8955 11:16:29.661881 DQS Delay:
8956 11:16:29.663716 DQS0 = 0, DQS1 = 0
8957 11:16:29.664323 DQM Delay:
8958 11:16:29.666996 DQM0 = 131, DQM1 = 127
8959 11:16:29.667561 DQ Delay:
8960 11:16:29.670314 DQ0 =134, DQ1 =130, DQ2 =120, DQ3 =128
8961 11:16:29.673269 DQ4 =128, DQ5 =144, DQ6 =140, DQ7 =130
8962 11:16:29.677201 DQ8 =114, DQ9 =116, DQ10 =128, DQ11 =120
8963 11:16:29.680163 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =138
8964 11:16:29.680722
8965 11:16:29.681089
8966 11:16:29.681423
8967 11:16:29.683443 [DramC_TX_OE_Calibration] TA2
8968 11:16:29.687307 Original DQ_B0 (3 6) =30, OEN = 27
8969 11:16:29.689943 Original DQ_B1 (3 6) =30, OEN = 27
8970 11:16:29.693228 24, 0x0, End_B0=24 End_B1=24
8971 11:16:29.698260 25, 0x0, End_B0=25 End_B1=25
8972 11:16:29.700230 26, 0x0, End_B0=26 End_B1=26
8973 11:16:29.700811 27, 0x0, End_B0=27 End_B1=27
8974 11:16:29.703088 28, 0x0, End_B0=28 End_B1=28
8975 11:16:29.706290 29, 0x0, End_B0=29 End_B1=29
8976 11:16:29.709475 30, 0x0, End_B0=30 End_B1=30
8977 11:16:29.712615 31, 0x4545, End_B0=30 End_B1=30
8978 11:16:29.713045 Byte0 end_step=30 best_step=27
8979 11:16:29.716140 Byte1 end_step=30 best_step=27
8980 11:16:29.719434 Byte0 TX OE(2T, 0.5T) = (3, 3)
8981 11:16:29.722980 Byte1 TX OE(2T, 0.5T) = (3, 3)
8982 11:16:29.723493
8983 11:16:29.723828
8984 11:16:29.732526 [DQSOSCAuto] RK1, (LSB)MR18= 0xe1c, (MSB)MR19= 0x303, tDQSOscB0 = 395 ps tDQSOscB1 = 402 ps
8985 11:16:29.732949 CH1 RK1: MR19=303, MR18=E1C
8986 11:16:29.739540 CH1_RK1: MR19=0x303, MR18=0xE1C, DQSOSC=395, MR23=63, INC=23, DEC=15
8987 11:16:29.743001 [RxdqsGatingPostProcess] freq 1600
8988 11:16:29.749677 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8989 11:16:29.752566 best DQS0 dly(2T, 0.5T) = (1, 1)
8990 11:16:29.755837 best DQS1 dly(2T, 0.5T) = (1, 1)
8991 11:16:29.759226 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8992 11:16:29.762606 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8993 11:16:29.763153 best DQS0 dly(2T, 0.5T) = (1, 1)
8994 11:16:29.766059 best DQS1 dly(2T, 0.5T) = (1, 1)
8995 11:16:29.768879 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8996 11:16:29.772624 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8997 11:16:29.775858 Pre-setting of DQS Precalculation
8998 11:16:29.781934 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8999 11:16:29.788942 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9000 11:16:29.795857 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9001 11:16:29.796489
9002 11:16:29.796856
9003 11:16:29.798860 [Calibration Summary] 3200 Mbps
9004 11:16:29.799415 CH 0, Rank 0
9005 11:16:29.801767 SW Impedance : PASS
9006 11:16:29.807809 DUTY Scan : NO K
9007 11:16:29.808431 ZQ Calibration : PASS
9008 11:16:29.809136 Jitter Meter : NO K
9009 11:16:29.811866 CBT Training : PASS
9010 11:16:29.812549 Write leveling : PASS
9011 11:16:29.814998 RX DQS gating : PASS
9012 11:16:29.818592 RX DQ/DQS(RDDQC) : PASS
9013 11:16:29.819257 TX DQ/DQS : PASS
9014 11:16:29.821698 RX DATLAT : PASS
9015 11:16:29.824714 RX DQ/DQS(Engine): PASS
9016 11:16:29.825171 TX OE : PASS
9017 11:16:29.827806 All Pass.
9018 11:16:29.828309
9019 11:16:29.828638 CH 0, Rank 1
9020 11:16:29.831186 SW Impedance : PASS
9021 11:16:29.831723 DUTY Scan : NO K
9022 11:16:29.834608 ZQ Calibration : PASS
9023 11:16:29.838259 Jitter Meter : NO K
9024 11:16:29.838776 CBT Training : PASS
9025 11:16:29.841441 Write leveling : PASS
9026 11:16:29.844883 RX DQS gating : PASS
9027 11:16:29.845398 RX DQ/DQS(RDDQC) : PASS
9028 11:16:29.847696 TX DQ/DQS : PASS
9029 11:16:29.851100 RX DATLAT : PASS
9030 11:16:29.851614 RX DQ/DQS(Engine): PASS
9031 11:16:29.854249 TX OE : PASS
9032 11:16:29.854770 All Pass.
9033 11:16:29.855103
9034 11:16:29.857379 CH 1, Rank 0
9035 11:16:29.857794 SW Impedance : PASS
9036 11:16:29.860895 DUTY Scan : NO K
9037 11:16:29.864540 ZQ Calibration : PASS
9038 11:16:29.865056 Jitter Meter : NO K
9039 11:16:29.867526 CBT Training : PASS
9040 11:16:29.868061 Write leveling : PASS
9041 11:16:29.870986 RX DQS gating : PASS
9042 11:16:29.874032 RX DQ/DQS(RDDQC) : PASS
9043 11:16:29.874445 TX DQ/DQS : PASS
9044 11:16:29.877244 RX DATLAT : PASS
9045 11:16:29.880885 RX DQ/DQS(Engine): PASS
9046 11:16:29.881399 TX OE : PASS
9047 11:16:29.884130 All Pass.
9048 11:16:29.884644
9049 11:16:29.884979 CH 1, Rank 1
9050 11:16:29.887211 SW Impedance : PASS
9051 11:16:29.887624 DUTY Scan : NO K
9052 11:16:29.890633 ZQ Calibration : PASS
9053 11:16:29.893174 Jitter Meter : NO K
9054 11:16:29.893593 CBT Training : PASS
9055 11:16:29.896852 Write leveling : PASS
9056 11:16:29.900455 RX DQS gating : PASS
9057 11:16:29.900869 RX DQ/DQS(RDDQC) : PASS
9058 11:16:29.903772 TX DQ/DQS : PASS
9059 11:16:29.906663 RX DATLAT : PASS
9060 11:16:29.907172 RX DQ/DQS(Engine): PASS
9061 11:16:29.909942 TX OE : PASS
9062 11:16:29.910358 All Pass.
9063 11:16:29.910683
9064 11:16:29.912944 DramC Write-DBI on
9065 11:16:29.916448 PER_BANK_REFRESH: Hybrid Mode
9066 11:16:29.916857 TX_TRACKING: ON
9067 11:16:29.926629 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9068 11:16:29.932978 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9069 11:16:29.939822 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9070 11:16:29.946505 [FAST_K] Save calibration result to emmc
9071 11:16:29.947111 sync common calibartion params.
9072 11:16:29.949556 sync cbt_mode0:1, 1:1
9073 11:16:29.953248 dram_init: ddr_geometry: 2
9074 11:16:29.953803 dram_init: ddr_geometry: 2
9075 11:16:29.956490 dram_init: ddr_geometry: 2
9076 11:16:29.959380 0:dram_rank_size:100000000
9077 11:16:29.962397 1:dram_rank_size:100000000
9078 11:16:29.965813 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9079 11:16:29.969289 DFS_SHUFFLE_HW_MODE: ON
9080 11:16:29.972328 dramc_set_vcore_voltage set vcore to 725000
9081 11:16:29.975774 Read voltage for 1600, 0
9082 11:16:29.976363 Vio18 = 0
9083 11:16:29.979052 Vcore = 725000
9084 11:16:29.979606 Vdram = 0
9085 11:16:29.979975 Vddq = 0
9086 11:16:29.982074 Vmddr = 0
9087 11:16:29.982530 switch to 3200 Mbps bootup
9088 11:16:29.985851 [DramcRunTimeConfig]
9089 11:16:29.986432 PHYPLL
9090 11:16:29.988879 DPM_CONTROL_AFTERK: ON
9091 11:16:29.989437 PER_BANK_REFRESH: ON
9092 11:16:29.992175 REFRESH_OVERHEAD_REDUCTION: ON
9093 11:16:29.995451 CMD_PICG_NEW_MODE: OFF
9094 11:16:29.996004 XRTWTW_NEW_MODE: ON
9095 11:16:29.999093 XRTRTR_NEW_MODE: ON
9096 11:16:29.999649 TX_TRACKING: ON
9097 11:16:30.002564 RDSEL_TRACKING: OFF
9098 11:16:30.005814 DQS Precalculation for DVFS: ON
9099 11:16:30.006370 RX_TRACKING: OFF
9100 11:16:30.008693 HW_GATING DBG: ON
9101 11:16:30.009249 ZQCS_ENABLE_LP4: ON
9102 11:16:30.012330 RX_PICG_NEW_MODE: ON
9103 11:16:30.012974 TX_PICG_NEW_MODE: ON
9104 11:16:30.014957 ENABLE_RX_DCM_DPHY: ON
9105 11:16:30.018791 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9106 11:16:30.021872 DUMMY_READ_FOR_TRACKING: OFF
9107 11:16:30.022436 !!! SPM_CONTROL_AFTERK: OFF
9108 11:16:30.025010 !!! SPM could not control APHY
9109 11:16:30.028363 IMPEDANCE_TRACKING: ON
9110 11:16:30.028943 TEMP_SENSOR: ON
9111 11:16:30.032102 HW_SAVE_FOR_SR: OFF
9112 11:16:30.034884 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9113 11:16:30.038494 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9114 11:16:30.041610 Read ODT Tracking: ON
9115 11:16:30.042172 Refresh Rate DeBounce: ON
9116 11:16:30.045222 DFS_NO_QUEUE_FLUSH: ON
9117 11:16:30.047899 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9118 11:16:30.051411 ENABLE_DFS_RUNTIME_MRW: OFF
9119 11:16:30.051924 DDR_RESERVE_NEW_MODE: ON
9120 11:16:30.054864 MR_CBT_SWITCH_FREQ: ON
9121 11:16:30.057948 =========================
9122 11:16:30.075944 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9123 11:16:30.079024 dram_init: ddr_geometry: 2
9124 11:16:30.097728 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9125 11:16:30.100891 dram_init: dram init end (result: 0)
9126 11:16:30.107457 DRAM-K: Full calibration passed in 24443 msecs
9127 11:16:30.110529 MRC: failed to locate region type 0.
9128 11:16:30.111104 DRAM rank0 size:0x100000000,
9129 11:16:30.113455 DRAM rank1 size=0x100000000
9130 11:16:30.124134 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9131 11:16:30.129949 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9132 11:16:30.136561 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9133 11:16:30.146182 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9134 11:16:30.146759 DRAM rank0 size:0x100000000,
9135 11:16:30.149612 DRAM rank1 size=0x100000000
9136 11:16:30.150069 CBMEM:
9137 11:16:30.152647 IMD: root @ 0xfffff000 254 entries.
9138 11:16:30.156640 IMD: root @ 0xffffec00 62 entries.
9139 11:16:30.159539 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9140 11:16:30.166370 WARNING: RO_VPD is uninitialized or empty.
9141 11:16:30.170133 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9142 11:16:30.177349 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9143 11:16:30.190154 read SPI 0x42894 0xe01e: 6225 us, 9216 KB/s, 73.728 Mbps
9144 11:16:30.201485 BS: romstage times (exec / console): total (unknown) / 23968 ms
9145 11:16:30.202044
9146 11:16:30.202410
9147 11:16:30.210973 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9148 11:16:30.215273 ARM64: Exception handlers installed.
9149 11:16:30.217491 ARM64: Testing exception
9150 11:16:30.220992 ARM64: Done test exception
9151 11:16:30.221725 Enumerating buses...
9152 11:16:30.224097 Show all devs... Before device enumeration.
9153 11:16:30.227506 Root Device: enabled 1
9154 11:16:30.230718 CPU_CLUSTER: 0: enabled 1
9155 11:16:30.231257 CPU: 00: enabled 1
9156 11:16:30.234220 Compare with tree...
9157 11:16:30.234777 Root Device: enabled 1
9158 11:16:30.237679 CPU_CLUSTER: 0: enabled 1
9159 11:16:30.240664 CPU: 00: enabled 1
9160 11:16:30.241240 Root Device scanning...
9161 11:16:30.244410 scan_static_bus for Root Device
9162 11:16:30.247389 CPU_CLUSTER: 0 enabled
9163 11:16:30.250518 scan_static_bus for Root Device done
9164 11:16:30.253451 scan_bus: bus Root Device finished in 8 msecs
9165 11:16:30.253874 done
9166 11:16:30.260618 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9167 11:16:30.263818 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9168 11:16:30.270638 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9169 11:16:30.277143 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9170 11:16:30.277713 Allocating resources...
9171 11:16:30.279930 Reading resources...
9172 11:16:30.283563 Root Device read_resources bus 0 link: 0
9173 11:16:30.287018 DRAM rank0 size:0x100000000,
9174 11:16:30.287533 DRAM rank1 size=0x100000000
9175 11:16:30.293465 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9176 11:16:30.293993 CPU: 00 missing read_resources
9177 11:16:30.300057 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9178 11:16:30.303329 Root Device read_resources bus 0 link: 0 done
9179 11:16:30.306172 Done reading resources.
9180 11:16:30.310224 Show resources in subtree (Root Device)...After reading.
9181 11:16:30.313187 Root Device child on link 0 CPU_CLUSTER: 0
9182 11:16:30.316430 CPU_CLUSTER: 0 child on link 0 CPU: 00
9183 11:16:30.325832 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9184 11:16:30.326388 CPU: 00
9185 11:16:30.332549 Root Device assign_resources, bus 0 link: 0
9186 11:16:30.335936 CPU_CLUSTER: 0 missing set_resources
9187 11:16:30.339162 Root Device assign_resources, bus 0 link: 0 done
9188 11:16:30.342620 Done setting resources.
9189 11:16:30.345634 Show resources in subtree (Root Device)...After assigning values.
9190 11:16:30.352245 Root Device child on link 0 CPU_CLUSTER: 0
9191 11:16:30.355821 CPU_CLUSTER: 0 child on link 0 CPU: 00
9192 11:16:30.362015 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9193 11:16:30.365526 CPU: 00
9194 11:16:30.365982 Done allocating resources.
9195 11:16:30.371913 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9196 11:16:30.375161 Enabling resources...
9197 11:16:30.375695 done.
9198 11:16:30.378669 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9199 11:16:30.381682 Initializing devices...
9200 11:16:30.382254 Root Device init
9201 11:16:30.384729 init hardware done!
9202 11:16:30.388346 0x00000018: ctrlr->caps
9203 11:16:30.389004 52.000 MHz: ctrlr->f_max
9204 11:16:30.391675 0.400 MHz: ctrlr->f_min
9205 11:16:30.394796 0x40ff8080: ctrlr->voltages
9206 11:16:30.395219 sclk: 390625
9207 11:16:30.395548 Bus Width = 1
9208 11:16:30.397924 sclk: 390625
9209 11:16:30.398337 Bus Width = 1
9210 11:16:30.402017 Early init status = 3
9211 11:16:30.404994 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9212 11:16:30.409765 in-header: 03 fc 00 00 01 00 00 00
9213 11:16:30.412946 in-data: 00
9214 11:16:30.416767 out: cmd=0x12d: 03 c8 2d 01 00 00 05 00 01 00 00 00 01
9215 11:16:30.422589 in-header: 03 fd 00 00 00 00 00 00
9216 11:16:30.425744 in-data:
9217 11:16:30.428753 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9218 11:16:30.433487 in-header: 03 fc 00 00 01 00 00 00
9219 11:16:30.436871 in-data: 00
9220 11:16:30.439661 out: cmd=0x12d: 03 c9 2d 01 00 00 05 00 00 00 00 00 01
9221 11:16:30.445237 in-header: 03 fd 00 00 00 00 00 00
9222 11:16:30.449068 in-data:
9223 11:16:30.451902 [SSUSB] Setting up USB HOST controller...
9224 11:16:30.456231 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9225 11:16:30.458768 [SSUSB] phy power-on done.
9226 11:16:30.462214 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9227 11:16:30.468470 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9228 11:16:30.472907 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9229 11:16:30.478402 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9230 11:16:30.484649 read SPI 0x50eb0 0x2ad3: 1174 us, 9338 KB/s, 74.704 Mbps
9231 11:16:30.491705 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9232 11:16:30.498773 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9233 11:16:30.504622 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9234 11:16:30.508408 SPM: binary array size = 0x9dc
9235 11:16:30.511325 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9236 11:16:30.518111 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9237 11:16:30.524666 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9238 11:16:30.531429 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9239 11:16:30.534325 configure_display: Starting display init
9240 11:16:30.568747 anx7625_power_on_init: Init interface.
9241 11:16:30.571902 anx7625_disable_pd_protocol: Disabled PD feature.
9242 11:16:30.575188 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9243 11:16:30.603187 anx7625_start_dp_work: Secure OCM version=00
9244 11:16:30.605854 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9245 11:16:30.620874 sp_tx_get_edid_block: EDID Block = 1
9246 11:16:30.724195 Extracted contents:
9247 11:16:30.727576 header: 00 ff ff ff ff ff ff 00
9248 11:16:30.730299 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9249 11:16:30.733424 version: 01 04
9250 11:16:30.736932 basic params: 95 1f 11 78 0a
9251 11:16:30.740023 chroma info: 76 90 94 55 54 90 27 21 50 54
9252 11:16:30.743461 established: 00 00 00
9253 11:16:30.750049 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9254 11:16:30.756593 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9255 11:16:30.759859 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9256 11:16:30.766441 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9257 11:16:30.773311 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9258 11:16:30.776212 extensions: 00
9259 11:16:30.776764 checksum: fb
9260 11:16:30.777130
9261 11:16:30.783300 Manufacturer: IVO Model 57d Serial Number 0
9262 11:16:30.783859 Made week 0 of 2020
9263 11:16:30.786037 EDID version: 1.4
9264 11:16:30.786591 Digital display
9265 11:16:30.789393 6 bits per primary color channel
9266 11:16:30.789855 DisplayPort interface
9267 11:16:30.792876 Maximum image size: 31 cm x 17 cm
9268 11:16:30.796547 Gamma: 220%
9269 11:16:30.797109 Check DPMS levels
9270 11:16:30.804026 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9271 11:16:30.805714 First detailed timing is preferred timing
9272 11:16:30.809227 Established timings supported:
9273 11:16:30.809792 Standard timings supported:
9274 11:16:30.812639 Detailed timings
9275 11:16:30.815752 Hex of detail: 383680a07038204018303c0035ae10000019
9276 11:16:30.822624 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9277 11:16:30.825901 0780 0798 07c8 0820 hborder 0
9278 11:16:30.828879 0438 043b 0447 0458 vborder 0
9279 11:16:30.832350 -hsync -vsync
9280 11:16:30.832900 Did detailed timing
9281 11:16:30.839332 Hex of detail: 000000000000000000000000000000000000
9282 11:16:30.842697 Manufacturer-specified data, tag 0
9283 11:16:30.845498 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9284 11:16:30.849330 ASCII string: InfoVision
9285 11:16:30.852573 Hex of detail: 000000fe00523134304e574635205248200a
9286 11:16:30.855495 ASCII string: R140NWF5 RH
9287 11:16:30.856074 Checksum
9288 11:16:30.858885 Checksum: 0xfb (valid)
9289 11:16:30.862031 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9290 11:16:30.865423 DSI data_rate: 832800000 bps
9291 11:16:30.872129 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9292 11:16:30.875166 anx7625_parse_edid: pixelclock(138800).
9293 11:16:30.878498 hactive(1920), hsync(48), hfp(24), hbp(88)
9294 11:16:30.881420 vactive(1080), vsync(12), vfp(3), vbp(17)
9295 11:16:30.885225 anx7625_dsi_config: config dsi.
9296 11:16:30.891474 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9297 11:16:30.906066 anx7625_dsi_config: success to config DSI
9298 11:16:30.908809 anx7625_dp_start: MIPI phy setup OK.
9299 11:16:30.912363 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9300 11:16:30.915824 mtk_ddp_mode_set invalid vrefresh 60
9301 11:16:30.918679 main_disp_path_setup
9302 11:16:30.919082 ovl_layer_smi_id_en
9303 11:16:30.921884 ovl_layer_smi_id_en
9304 11:16:30.922288 ccorr_config
9305 11:16:30.922607 aal_config
9306 11:16:30.925562 gamma_config
9307 11:16:30.926065 postmask_config
9308 11:16:30.928575 dither_config
9309 11:16:30.932090 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9310 11:16:30.938815 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9311 11:16:30.942075 Root Device init finished in 555 msecs
9312 11:16:30.945131 CPU_CLUSTER: 0 init
9313 11:16:30.951833 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9314 11:16:30.958470 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9315 11:16:30.958982 APU_MBOX 0x190000b0 = 0x10001
9316 11:16:30.962133 APU_MBOX 0x190001b0 = 0x10001
9317 11:16:30.965465 APU_MBOX 0x190005b0 = 0x10001
9318 11:16:30.968566 APU_MBOX 0x190006b0 = 0x10001
9319 11:16:30.975146 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9320 11:16:30.984733 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9321 11:16:30.997333 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9322 11:16:31.003504 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9323 11:16:31.015334 read SPI 0x61c74 0xe8ef: 6408 us, 9305 KB/s, 74.440 Mbps
9324 11:16:31.024369 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9325 11:16:31.027477 CPU_CLUSTER: 0 init finished in 81 msecs
9326 11:16:31.030897 Devices initialized
9327 11:16:31.033992 Show all devs... After init.
9328 11:16:31.034438 Root Device: enabled 1
9329 11:16:31.037355 CPU_CLUSTER: 0: enabled 1
9330 11:16:31.041139 CPU: 00: enabled 1
9331 11:16:31.044376 BS: BS_DEV_INIT run times (exec / console): 213 / 447 ms
9332 11:16:31.047633 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9333 11:16:31.050837 ELOG: NV offset 0x57f000 size 0x1000
9334 11:16:31.057669 read SPI 0x57f000 0x1000: 487 us, 8410 KB/s, 67.280 Mbps
9335 11:16:31.063926 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9336 11:16:31.067295 ELOG: Event(17) added with size 13 at 2023-06-05 11:16:31 UTC
9337 11:16:31.074305 out: cmd=0x121: 03 db 21 01 00 00 00 00
9338 11:16:31.077563 in-header: 03 13 00 00 2c 00 00 00
9339 11:16:31.087460 in-data: 4c 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9340 11:16:31.094191 ELOG: Event(A1) added with size 10 at 2023-06-05 11:16:31 UTC
9341 11:16:31.100420 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9342 11:16:31.108172 ELOG: Event(A0) added with size 9 at 2023-06-05 11:16:31 UTC
9343 11:16:31.110791 elog_add_boot_reason: Logged dev mode boot
9344 11:16:31.117120 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9345 11:16:31.117739 Finalize devices...
9346 11:16:31.120216 Devices finalized
9347 11:16:31.123670 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9348 11:16:31.126823 Writing coreboot table at 0xffe64000
9349 11:16:31.130443 0. 000000000010a000-0000000000113fff: RAMSTAGE
9350 11:16:31.136823 1. 0000000040000000-00000000400fffff: RAM
9351 11:16:31.139890 2. 0000000040100000-000000004032afff: RAMSTAGE
9352 11:16:31.143226 3. 000000004032b000-00000000545fffff: RAM
9353 11:16:31.147306 4. 0000000054600000-000000005465ffff: BL31
9354 11:16:31.149883 5. 0000000054660000-00000000ffe63fff: RAM
9355 11:16:31.156592 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9356 11:16:31.160115 7. 0000000100000000-000000023fffffff: RAM
9357 11:16:31.163563 Passing 5 GPIOs to payload:
9358 11:16:31.166680 NAME | PORT | POLARITY | VALUE
9359 11:16:31.173139 EC in RW | 0x000000aa | low | undefined
9360 11:16:31.176548 EC interrupt | 0x00000005 | low | undefined
9361 11:16:31.179969 TPM interrupt | 0x000000ab | high | undefined
9362 11:16:31.185802 SD card detect | 0x00000011 | high | undefined
9363 11:16:31.189333 speaker enable | 0x00000093 | high | undefined
9364 11:16:31.192416 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9365 11:16:31.195957 in-header: 03 f9 00 00 02 00 00 00
9366 11:16:31.199302 in-data: 02 00
9367 11:16:31.202833 ADC[4]: Raw value=902216 ID=7
9368 11:16:31.205938 ADC[3]: Raw value=213916 ID=1
9369 11:16:31.206467 RAM Code: 0x71
9370 11:16:31.209145 ADC[6]: Raw value=75000 ID=0
9371 11:16:31.212746 ADC[5]: Raw value=213916 ID=1
9372 11:16:31.213303 SKU Code: 0x1
9373 11:16:31.219364 Wrote coreboot table at: 0xffe64000, 0x3ac bytes, checksum a53a
9374 11:16:31.219969 coreboot table: 964 bytes.
9375 11:16:31.222610 IMD ROOT 0. 0xfffff000 0x00001000
9376 11:16:31.226334 IMD SMALL 1. 0xffffe000 0x00001000
9377 11:16:31.229436 RO MCACHE 2. 0xffffc000 0x00001104
9378 11:16:31.232636 CONSOLE 3. 0xfff7c000 0x00080000
9379 11:16:31.236004 FMAP 4. 0xfff7b000 0x00000452
9380 11:16:31.239020 TIME STAMP 5. 0xfff7a000 0x00000910
9381 11:16:31.242657 VBOOT WORK 6. 0xfff66000 0x00014000
9382 11:16:31.245652 RAMOOPS 7. 0xffe66000 0x00100000
9383 11:16:31.249252 COREBOOT 8. 0xffe64000 0x00002000
9384 11:16:31.251982 IMD small region:
9385 11:16:31.255767 IMD ROOT 0. 0xffffec00 0x00000400
9386 11:16:31.258815 VPD 1. 0xffffeba0 0x0000004c
9387 11:16:31.261676 MMC STATUS 2. 0xffffeb80 0x00000004
9388 11:16:31.268298 BS: BS_WRITE_TABLES run times (exec / console): 1 / 137 ms
9389 11:16:31.268883 Probing TPM: done!
9390 11:16:31.275473 Connected to device vid:did:rid of 1ae0:0028:00
9391 11:16:31.282484 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9b9523
9392 11:16:31.284906 Initialized TPM device CR50 revision 0
9393 11:16:31.289199 Checking cr50 for pending updates
9394 11:16:31.294637 Reading cr50 TPM mode
9395 11:16:31.302606 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9396 11:16:31.309674 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9397 11:16:31.349298 read SPI 0x3990ec 0x4f1b0: 34849 us, 9297 KB/s, 74.376 Mbps
9398 11:16:31.352778 Checking segment from ROM address 0x40100000
9399 11:16:31.356388 Checking segment from ROM address 0x4010001c
9400 11:16:31.362970 Loading segment from ROM address 0x40100000
9401 11:16:31.363594 code (compression=0)
9402 11:16:31.372482 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9403 11:16:31.379205 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9404 11:16:31.379797 it's not compressed!
9405 11:16:31.385717 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9406 11:16:31.392703 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9407 11:16:31.410447 Loading segment from ROM address 0x4010001c
9408 11:16:31.411007 Entry Point 0x80000000
9409 11:16:31.413666 Loaded segments
9410 11:16:31.416963 BS: BS_PAYLOAD_LOAD run times (exec / console): 48 / 61 ms
9411 11:16:31.424191 Jumping to boot code at 0x80000000(0xffe64000)
9412 11:16:31.430527 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9413 11:16:31.436710 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9414 11:16:31.444525 read SPI 0x8eb68 0x74a8: 3223 us, 9265 KB/s, 74.120 Mbps
9415 11:16:31.447883 Checking segment from ROM address 0x40100000
9416 11:16:31.451116 Checking segment from ROM address 0x4010001c
9417 11:16:31.459074 Loading segment from ROM address 0x40100000
9418 11:16:31.459636 code (compression=1)
9419 11:16:31.464449 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9420 11:16:31.474517 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9421 11:16:31.475075 using LZMA
9422 11:16:31.483075 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9423 11:16:31.489068 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9424 11:16:31.492530 Loading segment from ROM address 0x4010001c
9425 11:16:31.493051 Entry Point 0x54601000
9426 11:16:31.495745 Loaded segments
9427 11:16:31.499130 NOTICE: MT8192 bl31_setup
9428 11:16:31.506772 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9429 11:16:31.509863 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9430 11:16:31.513214 WARNING: region 0:
9431 11:16:31.516796 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9432 11:16:31.517360 WARNING: region 1:
9433 11:16:31.523027 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9434 11:16:31.526714 WARNING: region 2:
9435 11:16:31.530160 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9436 11:16:31.533647 WARNING: region 3:
9437 11:16:31.536466 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9438 11:16:31.539684 WARNING: region 4:
9439 11:16:31.546387 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9440 11:16:31.546963 WARNING: region 5:
9441 11:16:31.549555 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9442 11:16:31.552914 WARNING: region 6:
9443 11:16:31.556174 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9444 11:16:31.559576 WARNING: region 7:
9445 11:16:31.563512 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9446 11:16:31.570349 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9447 11:16:31.573140 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9448 11:16:31.576559 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9449 11:16:31.583290 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9450 11:16:31.585965 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9451 11:16:31.589619 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9452 11:16:31.596084 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9453 11:16:31.599342 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9454 11:16:31.606275 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9455 11:16:31.609176 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9456 11:16:31.612861 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9457 11:16:31.619416 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9458 11:16:31.622262 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9459 11:16:31.626257 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9460 11:16:31.632491 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9461 11:16:31.635816 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9462 11:16:31.642365 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9463 11:16:31.645675 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9464 11:16:31.648997 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9465 11:16:31.655894 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9466 11:16:31.659289 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9467 11:16:31.665851 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9468 11:16:31.669042 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9469 11:16:31.672314 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9470 11:16:31.678975 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9471 11:16:31.682708 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9472 11:16:31.688889 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9473 11:16:31.691783 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9474 11:16:31.695399 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9475 11:16:31.702048 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9476 11:16:31.705098 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9477 11:16:31.712154 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9478 11:16:31.715330 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9479 11:16:31.718578 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9480 11:16:31.721929 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9481 11:16:31.728305 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9482 11:16:31.731676 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9483 11:16:31.735170 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9484 11:16:31.738490 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9485 11:16:31.744627 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9486 11:16:31.748303 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9487 11:16:31.751703 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9488 11:16:31.754788 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9489 11:16:31.761875 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9490 11:16:31.764557 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9491 11:16:31.768966 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9492 11:16:31.775074 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9493 11:16:31.778466 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9494 11:16:31.781168 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9495 11:16:31.787848 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9496 11:16:31.790741 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9497 11:16:31.797567 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9498 11:16:31.801047 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9499 11:16:31.803972 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9500 11:16:31.810828 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9501 11:16:31.815354 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9502 11:16:31.820893 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9503 11:16:31.824009 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9504 11:16:31.831315 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9505 11:16:31.833769 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9506 11:16:31.840809 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9507 11:16:31.844614 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9508 11:16:31.847466 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9509 11:16:31.854245 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9510 11:16:31.857001 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9511 11:16:31.864974 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9512 11:16:31.867493 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9513 11:16:31.873652 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9514 11:16:31.878100 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9515 11:16:31.883592 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9516 11:16:31.886798 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9517 11:16:31.890813 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9518 11:16:31.896790 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9519 11:16:31.900063 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9520 11:16:31.907401 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9521 11:16:31.910475 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9522 11:16:31.916814 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9523 11:16:31.919990 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9524 11:16:31.926568 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9525 11:16:31.930478 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9526 11:16:31.933050 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9527 11:16:31.939965 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9528 11:16:31.943162 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9529 11:16:31.950014 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9530 11:16:31.953123 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9531 11:16:31.959665 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9532 11:16:31.962847 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9533 11:16:31.969995 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9534 11:16:31.972825 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9535 11:16:31.976244 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9536 11:16:31.983006 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9537 11:16:31.986101 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9538 11:16:31.992857 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9539 11:16:31.996116 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9540 11:16:32.002717 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9541 11:16:32.006027 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9542 11:16:32.008970 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9543 11:16:32.015841 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9544 11:16:32.019434 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9545 11:16:32.022440 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9546 11:16:32.025846 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9547 11:16:32.032343 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9548 11:16:32.036590 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9549 11:16:32.042547 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9550 11:16:32.045745 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9551 11:16:32.049180 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9552 11:16:32.055853 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9553 11:16:32.059636 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9554 11:16:32.065831 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9555 11:16:32.069010 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9556 11:16:32.072660 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9557 11:16:32.079085 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9558 11:16:32.082102 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9559 11:16:32.088884 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9560 11:16:32.092194 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9561 11:16:32.096204 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9562 11:16:32.102473 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9563 11:16:32.105493 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9564 11:16:32.108506 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9565 11:16:32.115350 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9566 11:16:32.118628 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9567 11:16:32.122093 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9568 11:16:32.125489 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9569 11:16:32.131647 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9570 11:16:32.135065 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9571 11:16:32.138831 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9572 11:16:32.145599 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9573 11:16:32.148618 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9574 11:16:32.154876 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9575 11:16:32.158493 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9576 11:16:32.161828 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9577 11:16:32.168273 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9578 11:16:32.171664 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9579 11:16:32.178217 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9580 11:16:32.181138 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9581 11:16:32.184466 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9582 11:16:32.191854 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9583 11:16:32.195006 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9584 11:16:32.201960 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9585 11:16:32.204654 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9586 11:16:32.208126 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9587 11:16:32.214663 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9588 11:16:32.217902 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9589 11:16:32.224841 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9590 11:16:32.228282 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9591 11:16:32.231681 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9592 11:16:32.238136 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9593 11:16:32.242563 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9594 11:16:32.247704 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9595 11:16:32.250965 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9596 11:16:32.254479 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9597 11:16:32.261198 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9598 11:16:32.264700 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9599 11:16:32.267524 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9600 11:16:32.274345 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9601 11:16:32.277330 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9602 11:16:32.284801 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9603 11:16:32.288017 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9604 11:16:32.290743 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9605 11:16:32.298050 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9606 11:16:32.300944 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9607 11:16:32.307846 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9608 11:16:32.310969 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9609 11:16:32.313683 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9610 11:16:32.320690 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9611 11:16:32.324075 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9612 11:16:32.330587 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9613 11:16:32.333564 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9614 11:16:32.336763 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9615 11:16:32.343412 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9616 11:16:32.347257 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9617 11:16:32.353291 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9618 11:16:32.356877 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9619 11:16:32.363069 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9620 11:16:32.366482 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9621 11:16:32.370021 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9622 11:16:32.376370 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9623 11:16:32.379660 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9624 11:16:32.386707 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9625 11:16:32.389294 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9626 11:16:32.392658 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9627 11:16:32.400456 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9628 11:16:32.403185 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9629 11:16:32.409237 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9630 11:16:32.412453 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9631 11:16:32.416152 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9632 11:16:32.422531 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9633 11:16:32.425630 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9634 11:16:32.432518 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9635 11:16:32.435109 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9636 11:16:32.442114 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9637 11:16:32.444956 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9638 11:16:32.448476 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9639 11:16:32.455115 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9640 11:16:32.458416 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9641 11:16:32.464983 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9642 11:16:32.468718 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9643 11:16:32.471668 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9644 11:16:32.478186 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9645 11:16:32.481384 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9646 11:16:32.488159 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9647 11:16:32.491436 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9648 11:16:32.498014 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9649 11:16:32.501457 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9650 11:16:32.504780 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9651 11:16:32.511784 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9652 11:16:32.514416 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9653 11:16:32.521040 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9654 11:16:32.525283 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9655 11:16:32.531349 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9656 11:16:32.533909 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9657 11:16:32.537711 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9658 11:16:32.544073 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9659 11:16:32.547254 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9660 11:16:32.553718 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9661 11:16:32.557094 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9662 11:16:32.563885 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9663 11:16:32.567656 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9664 11:16:32.570711 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9665 11:16:32.576923 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9666 11:16:32.580276 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9667 11:16:32.586931 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9668 11:16:32.589972 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9669 11:16:32.596447 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9670 11:16:32.599864 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9671 11:16:32.607010 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9672 11:16:32.609593 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9673 11:16:32.613638 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9674 11:16:32.620263 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9675 11:16:32.622887 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9676 11:16:32.626150 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9677 11:16:32.629208 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9678 11:16:32.636410 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9679 11:16:32.640230 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9680 11:16:32.642758 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9681 11:16:32.649185 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9682 11:16:32.652522 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9683 11:16:32.659521 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9684 11:16:32.662655 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9685 11:16:32.665368 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9686 11:16:32.672391 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9687 11:16:32.675811 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9688 11:16:32.682253 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9689 11:16:32.685325 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9690 11:16:32.688930 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9691 11:16:32.695192 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9692 11:16:32.698042 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9693 11:16:32.701706 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9694 11:16:32.708293 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9695 11:16:32.711632 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9696 11:16:32.718090 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9697 11:16:32.721167 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9698 11:16:32.724965 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9699 11:16:32.730999 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9700 11:16:32.734411 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9701 11:16:32.737551 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9702 11:16:32.744345 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9703 11:16:32.747424 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9704 11:16:32.750816 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9705 11:16:32.757199 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9706 11:16:32.760451 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9707 11:16:32.767516 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9708 11:16:32.770699 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9709 11:16:32.773658 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9710 11:16:32.780608 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9711 11:16:32.783852 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9712 11:16:32.790292 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9713 11:16:32.793810 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9714 11:16:32.796950 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9715 11:16:32.800937 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9716 11:16:32.807244 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9717 11:16:32.810831 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9718 11:16:32.813665 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9719 11:16:32.816917 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9720 11:16:32.823210 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9721 11:16:32.827373 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9722 11:16:32.830273 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9723 11:16:32.833197 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9724 11:16:32.839890 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9725 11:16:32.843471 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9726 11:16:32.847197 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9727 11:16:32.853277 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9728 11:16:32.856362 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9729 11:16:32.859905 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9730 11:16:32.866300 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9731 11:16:32.869385 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9732 11:16:32.876714 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9733 11:16:32.879822 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9734 11:16:32.886177 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9735 11:16:32.888997 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9736 11:16:32.892907 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9737 11:16:32.899847 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9738 11:16:32.902519 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9739 11:16:32.909053 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9740 11:16:32.912706 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9741 11:16:32.918691 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9742 11:16:32.922323 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9743 11:16:32.925642 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9744 11:16:32.932088 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9745 11:16:32.935352 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9746 11:16:32.941753 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9747 11:16:32.945483 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9748 11:16:32.948479 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9749 11:16:32.955582 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9750 11:16:32.958619 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9751 11:16:32.965000 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9752 11:16:32.968510 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9753 11:16:32.971732 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9754 11:16:32.978355 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9755 11:16:32.981451 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9756 11:16:32.988257 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9757 11:16:32.991662 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9758 11:16:32.997853 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9759 11:16:33.001168 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9760 11:16:33.004638 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9761 11:16:33.011330 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9762 11:16:33.014209 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9763 11:16:33.021297 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9764 11:16:33.024196 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9765 11:16:33.030655 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9766 11:16:33.033949 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9767 11:16:33.037413 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9768 11:16:33.044083 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9769 11:16:33.047614 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9770 11:16:33.053799 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9771 11:16:33.057309 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9772 11:16:33.064407 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9773 11:16:33.066960 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9774 11:16:33.070330 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9775 11:16:33.077263 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9776 11:16:33.080138 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9777 11:16:33.086859 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9778 11:16:33.090215 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9779 11:16:33.093336 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9780 11:16:33.100334 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9781 11:16:33.102975 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9782 11:16:33.111236 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9783 11:16:33.113385 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9784 11:16:33.116459 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9785 11:16:33.123352 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9786 11:16:33.126541 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9787 11:16:33.133228 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9788 11:16:33.136616 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9789 11:16:33.143124 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9790 11:16:33.146220 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9791 11:16:33.150422 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9792 11:16:33.156719 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9793 11:16:33.159548 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9794 11:16:33.165984 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9795 11:16:33.169545 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9796 11:16:33.176176 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9797 11:16:33.179427 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9798 11:16:33.182640 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9799 11:16:33.189115 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9800 11:16:33.192416 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9801 11:16:33.199406 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9802 11:16:33.202120 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9803 11:16:33.208919 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9804 11:16:33.212409 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9805 11:16:33.218380 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9806 11:16:33.222827 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9807 11:16:33.225637 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9808 11:16:33.231720 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9809 11:16:33.235429 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9810 11:16:33.241834 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9811 11:16:33.245230 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9812 11:16:33.252082 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9813 11:16:33.255734 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9814 11:16:33.261656 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9815 11:16:33.264968 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9816 11:16:33.268418 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9817 11:16:33.274749 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9818 11:16:33.278851 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
9819 11:16:33.285296 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
9820 11:16:33.288263 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
9821 11:16:33.295100 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
9822 11:16:33.297673 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
9823 11:16:33.300711 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
9824 11:16:33.307671 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
9825 11:16:33.310704 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
9826 11:16:33.317896 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
9827 11:16:33.320879 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
9828 11:16:33.327399 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
9829 11:16:33.330347 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
9830 11:16:33.337037 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
9831 11:16:33.340614 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
9832 11:16:33.344164 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
9833 11:16:33.350731 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
9834 11:16:33.353906 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
9835 11:16:33.360497 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
9836 11:16:33.363496 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
9837 11:16:33.370586 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
9838 11:16:33.373456 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
9839 11:16:33.379866 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
9840 11:16:33.383183 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
9841 11:16:33.389904 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
9842 11:16:33.393424 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
9843 11:16:33.396583 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
9844 11:16:33.403131 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
9845 11:16:33.406252 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
9846 11:16:33.413172 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
9847 11:16:33.416427 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
9848 11:16:33.419781 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
9849 11:16:33.426636 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
9850 11:16:33.429010 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
9851 11:16:33.435902 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
9852 11:16:33.439059 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
9853 11:16:33.446341 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
9854 11:16:33.448723 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
9855 11:16:33.455748 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
9856 11:16:33.459337 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
9857 11:16:33.465286 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
9858 11:16:33.469130 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
9859 11:16:33.476282 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
9860 11:16:33.478956 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
9861 11:16:33.485465 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
9862 11:16:33.488231 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
9863 11:16:33.495679 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
9864 11:16:33.498257 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
9865 11:16:33.504738 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
9866 11:16:33.508078 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
9867 11:16:33.514477 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
9868 11:16:33.517943 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
9869 11:16:33.524491 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
9870 11:16:33.527430 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
9871 11:16:33.534376 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
9872 11:16:33.537919 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
9873 11:16:33.543986 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
9874 11:16:33.547676 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
9875 11:16:33.554121 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
9876 11:16:33.560949 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
9877 11:16:33.563828 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
9878 11:16:33.570360 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
9879 11:16:33.573839 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
9880 11:16:33.578011 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
9881 11:16:33.581274 INFO: [APUAPC] vio 0
9882 11:16:33.583781 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
9883 11:16:33.590856 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
9884 11:16:33.594075 INFO: [APUAPC] D0_APC_0: 0x400510
9885 11:16:33.597416 INFO: [APUAPC] D0_APC_1: 0x0
9886 11:16:33.600430 INFO: [APUAPC] D0_APC_2: 0x1540
9887 11:16:33.600937 INFO: [APUAPC] D0_APC_3: 0x0
9888 11:16:33.604076 INFO: [APUAPC] D1_APC_0: 0xffffffff
9889 11:16:33.610401 INFO: [APUAPC] D1_APC_1: 0xffffffff
9890 11:16:33.613370 INFO: [APUAPC] D1_APC_2: 0x3fffff
9891 11:16:33.613834 INFO: [APUAPC] D1_APC_3: 0x0
9892 11:16:33.620440 INFO: [APUAPC] D2_APC_0: 0xffffffff
9893 11:16:33.623711 INFO: [APUAPC] D2_APC_1: 0xffffffff
9894 11:16:33.626862 INFO: [APUAPC] D2_APC_2: 0x3fffff
9895 11:16:33.627305 INFO: [APUAPC] D2_APC_3: 0x0
9896 11:16:33.629970 INFO: [APUAPC] D3_APC_0: 0xffffffff
9897 11:16:33.636553 INFO: [APUAPC] D3_APC_1: 0xffffffff
9898 11:16:33.640201 INFO: [APUAPC] D3_APC_2: 0x3fffff
9899 11:16:33.640621 INFO: [APUAPC] D3_APC_3: 0x0
9900 11:16:33.643267 INFO: [APUAPC] D4_APC_0: 0xffffffff
9901 11:16:33.646538 INFO: [APUAPC] D4_APC_1: 0xffffffff
9902 11:16:33.649438 INFO: [APUAPC] D4_APC_2: 0x3fffff
9903 11:16:33.652932 INFO: [APUAPC] D4_APC_3: 0x0
9904 11:16:33.656243 INFO: [APUAPC] D5_APC_0: 0xffffffff
9905 11:16:33.659627 INFO: [APUAPC] D5_APC_1: 0xffffffff
9906 11:16:33.663653 INFO: [APUAPC] D5_APC_2: 0x3fffff
9907 11:16:33.666275 INFO: [APUAPC] D5_APC_3: 0x0
9908 11:16:33.669807 INFO: [APUAPC] D6_APC_0: 0xffffffff
9909 11:16:33.672743 INFO: [APUAPC] D6_APC_1: 0xffffffff
9910 11:16:33.676239 INFO: [APUAPC] D6_APC_2: 0x3fffff
9911 11:16:33.679796 INFO: [APUAPC] D6_APC_3: 0x0
9912 11:16:33.683100 INFO: [APUAPC] D7_APC_0: 0xffffffff
9913 11:16:33.686124 INFO: [APUAPC] D7_APC_1: 0xffffffff
9914 11:16:33.689456 INFO: [APUAPC] D7_APC_2: 0x3fffff
9915 11:16:33.692201 INFO: [APUAPC] D7_APC_3: 0x0
9916 11:16:33.696219 INFO: [APUAPC] D8_APC_0: 0xffffffff
9917 11:16:33.699126 INFO: [APUAPC] D8_APC_1: 0xffffffff
9918 11:16:33.702518 INFO: [APUAPC] D8_APC_2: 0x3fffff
9919 11:16:33.706037 INFO: [APUAPC] D8_APC_3: 0x0
9920 11:16:33.708837 INFO: [APUAPC] D9_APC_0: 0xffffffff
9921 11:16:33.711887 INFO: [APUAPC] D9_APC_1: 0xffffffff
9922 11:16:33.715456 INFO: [APUAPC] D9_APC_2: 0x3fffff
9923 11:16:33.718702 INFO: [APUAPC] D9_APC_3: 0x0
9924 11:16:33.722044 INFO: [APUAPC] D10_APC_0: 0xffffffff
9925 11:16:33.724815 INFO: [APUAPC] D10_APC_1: 0xffffffff
9926 11:16:33.728529 INFO: [APUAPC] D10_APC_2: 0x3fffff
9927 11:16:33.731901 INFO: [APUAPC] D10_APC_3: 0x0
9928 11:16:33.735201 INFO: [APUAPC] D11_APC_0: 0xffffffff
9929 11:16:33.738070 INFO: [APUAPC] D11_APC_1: 0xffffffff
9930 11:16:33.742107 INFO: [APUAPC] D11_APC_2: 0x3fffff
9931 11:16:33.745028 INFO: [APUAPC] D11_APC_3: 0x0
9932 11:16:33.748195 INFO: [APUAPC] D12_APC_0: 0xffffffff
9933 11:16:33.751760 INFO: [APUAPC] D12_APC_1: 0xffffffff
9934 11:16:33.755034 INFO: [APUAPC] D12_APC_2: 0x3fffff
9935 11:16:33.758312 INFO: [APUAPC] D12_APC_3: 0x0
9936 11:16:33.761710 INFO: [APUAPC] D13_APC_0: 0xffffffff
9937 11:16:33.768193 INFO: [APUAPC] D13_APC_1: 0xffffffff
9938 11:16:33.771168 INFO: [APUAPC] D13_APC_2: 0x3fffff
9939 11:16:33.771687 INFO: [APUAPC] D13_APC_3: 0x0
9940 11:16:33.774620 INFO: [APUAPC] D14_APC_0: 0xffffffff
9941 11:16:33.781693 INFO: [APUAPC] D14_APC_1: 0xffffffff
9942 11:16:33.784789 INFO: [APUAPC] D14_APC_2: 0x3fffff
9943 11:16:33.785317 INFO: [APUAPC] D14_APC_3: 0x0
9944 11:16:33.791437 INFO: [APUAPC] D15_APC_0: 0xffffffff
9945 11:16:33.795317 INFO: [APUAPC] D15_APC_1: 0xffffffff
9946 11:16:33.797554 INFO: [APUAPC] D15_APC_2: 0x3fffff
9947 11:16:33.801301 INFO: [APUAPC] D15_APC_3: 0x0
9948 11:16:33.801820 INFO: [APUAPC] APC_CON: 0x4
9949 11:16:33.804990 INFO: [NOCDAPC] D0_APC_0: 0x0
9950 11:16:33.807763 INFO: [NOCDAPC] D0_APC_1: 0x0
9951 11:16:33.811042 INFO: [NOCDAPC] D1_APC_0: 0x0
9952 11:16:33.814073 INFO: [NOCDAPC] D1_APC_1: 0xfff
9953 11:16:33.817421 INFO: [NOCDAPC] D2_APC_0: 0x0
9954 11:16:33.820666 INFO: [NOCDAPC] D2_APC_1: 0xfff
9955 11:16:33.823728 INFO: [NOCDAPC] D3_APC_0: 0x0
9956 11:16:33.827096 INFO: [NOCDAPC] D3_APC_1: 0xfff
9957 11:16:33.831086 INFO: [NOCDAPC] D4_APC_0: 0x0
9958 11:16:33.831545 INFO: [NOCDAPC] D4_APC_1: 0xfff
9959 11:16:33.833544 INFO: [NOCDAPC] D5_APC_0: 0x0
9960 11:16:33.837216 INFO: [NOCDAPC] D5_APC_1: 0xfff
9961 11:16:33.840567 INFO: [NOCDAPC] D6_APC_0: 0x0
9962 11:16:33.843665 INFO: [NOCDAPC] D6_APC_1: 0xfff
9963 11:16:33.847142 INFO: [NOCDAPC] D7_APC_0: 0x0
9964 11:16:33.849993 INFO: [NOCDAPC] D7_APC_1: 0xfff
9965 11:16:33.853453 INFO: [NOCDAPC] D8_APC_0: 0x0
9966 11:16:33.856765 INFO: [NOCDAPC] D8_APC_1: 0xfff
9967 11:16:33.859835 INFO: [NOCDAPC] D9_APC_0: 0x0
9968 11:16:33.863942 INFO: [NOCDAPC] D9_APC_1: 0xfff
9969 11:16:33.866904 INFO: [NOCDAPC] D10_APC_0: 0x0
9970 11:16:33.869881 INFO: [NOCDAPC] D10_APC_1: 0xfff
9971 11:16:33.870295 INFO: [NOCDAPC] D11_APC_0: 0x0
9972 11:16:33.873449 INFO: [NOCDAPC] D11_APC_1: 0xfff
9973 11:16:33.876651 INFO: [NOCDAPC] D12_APC_0: 0x0
9974 11:16:33.880104 INFO: [NOCDAPC] D12_APC_1: 0xfff
9975 11:16:33.883722 INFO: [NOCDAPC] D13_APC_0: 0x0
9976 11:16:33.886037 INFO: [NOCDAPC] D13_APC_1: 0xfff
9977 11:16:33.889889 INFO: [NOCDAPC] D14_APC_0: 0x0
9978 11:16:33.892756 INFO: [NOCDAPC] D14_APC_1: 0xfff
9979 11:16:33.896549 INFO: [NOCDAPC] D15_APC_0: 0x0
9980 11:16:33.899339 INFO: [NOCDAPC] D15_APC_1: 0xfff
9981 11:16:33.903342 INFO: [NOCDAPC] APC_CON: 0x4
9982 11:16:33.906254 INFO: [APUAPC] set_apusys_apc done
9983 11:16:33.909669 INFO: [DEVAPC] devapc_init done
9984 11:16:33.912550 INFO: GICv3 without legacy support detected.
9985 11:16:33.916104 INFO: ARM GICv3 driver initialized in EL3
9986 11:16:33.919421 INFO: Maximum SPI INTID supported: 639
9987 11:16:33.925328 INFO: BL31: Initializing runtime services
9988 11:16:33.929326 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
9989 11:16:33.931915 INFO: SPM: enable CPC mode
9990 11:16:33.939279 INFO: mcdi ready for mcusys-off-idle and system suspend
9991 11:16:33.942998 INFO: BL31: Preparing for EL3 exit to normal world
9992 11:16:33.945785 INFO: Entry point address = 0x80000000
9993 11:16:33.948971 INFO: SPSR = 0x8
9994 11:16:33.955136
9995 11:16:33.955693
9996 11:16:33.956131
9997 11:16:33.957558 Starting depthcharge on Spherion...
9998 11:16:33.958022
9999 11:16:33.958386 Wipe memory regions:
10000 11:16:33.958726
10001 11:16:33.961034 end: 2.2.3 depthcharge-start (duration 00:00:29) [common]
10002 11:16:33.961515 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10003 11:16:33.961916 Setting prompt string to ['asurada:']
10004 11:16:33.962325 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10005 11:16:33.962971 [0x00000040000000, 0x00000054600000)
10006 11:16:34.083529
10007 11:16:34.084124 [0x00000054660000, 0x00000080000000)
10008 11:16:34.344190
10009 11:16:34.344749 [0x000000821a7280, 0x000000ffe64000)
10010 11:16:35.089036
10011 11:16:35.089599 [0x00000100000000, 0x00000240000000)
10012 11:16:36.979115
10013 11:16:36.982397 Initializing XHCI USB controller at 0x11200000.
10014 11:16:38.020372
10015 11:16:38.023515 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10016 11:16:38.024113
10017 11:16:38.024498
10018 11:16:38.024844
10019 11:16:38.025611 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10021 11:16:38.126814 asurada: tftpboot 192.168.201.1 10591263/tftp-deploy-_xk_g__a/kernel/image.itb 10591263/tftp-deploy-_xk_g__a/kernel/cmdline
10022 11:16:38.127478 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10023 11:16:38.128014 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:21)
10024 11:16:38.132649 tftpboot 192.168.201.1 10591263/tftp-deploy-_xk_g__a/kernel/image.itp-deploy-_xk_g__a/kernel/cmdline
10025 11:16:38.133212
10026 11:16:38.133585 Waiting for link
10027 11:16:38.292943
10028 11:16:38.293521 R8152: Initializing
10029 11:16:38.293931
10030 11:16:38.295929 Version 6 (ocp_data = 5c30)
10031 11:16:38.296471
10032 11:16:38.299703 R8152: Done initializing
10033 11:16:38.300304
10034 11:16:38.300679 Adding net device
10035 11:16:40.229997
10036 11:16:40.230553 done.
10037 11:16:40.230925
10038 11:16:40.231270 MAC: 00:24:32:30:7c:7b
10039 11:16:40.231606
10040 11:16:40.232832 Sending DHCP discover... done.
10041 11:16:40.233297
10042 11:16:50.298952 Waiting for reply... R8152: Bulk read error 0xffffffbf
10043 11:16:50.299572
10044 11:16:50.301915 Receive failed.
10045 11:16:50.302369
10046 11:16:50.302766 done.
10047 11:16:50.303156
10048 11:16:50.305184 Sending DHCP request... done.
10049 11:16:50.305637
10050 11:16:50.312571 Waiting for reply... done.
10051 11:16:50.313054
10052 11:16:50.313413 My ip is 192.168.201.14
10053 11:16:50.313751
10054 11:16:50.315534 The DHCP server ip is 192.168.201.1
10055 11:16:50.315948
10056 11:16:50.322673 TFTP server IP predefined by user: 192.168.201.1
10057 11:16:50.323222
10058 11:16:50.329325 Bootfile predefined by user: 10591263/tftp-deploy-_xk_g__a/kernel/image.itb
10059 11:16:50.329843
10060 11:16:50.331877 Sending tftp read request... done.
10061 11:16:50.332356
10062 11:16:50.338281 Waiting for the transfer...
10063 11:16:50.338702
10064 11:16:50.992152 00000000 ################################################################
10065 11:16:50.992659
10066 11:16:51.668818 00080000 ################################################################
10067 11:16:51.668960
10068 11:16:52.298836 00100000 ################################################################
10069 11:16:52.298978
10070 11:16:52.924525 00180000 ################################################################
10071 11:16:52.924670
10072 11:16:53.580247 00200000 ################################################################
10073 11:16:53.580405
10074 11:16:54.231812 00280000 ################################################################
10075 11:16:54.231956
10076 11:16:54.880869 00300000 ################################################################
10077 11:16:54.881015
10078 11:16:55.530134 00380000 ################################################################
10079 11:16:55.530279
10080 11:16:56.190953 00400000 ################################################################
10081 11:16:56.191508
10082 11:16:56.874253 00480000 ################################################################
10083 11:16:56.874753
10084 11:16:57.579002 00500000 ################################################################
10085 11:16:57.579509
10086 11:16:58.266372 00580000 ################################################################
10087 11:16:58.266925
10088 11:16:58.942884 00600000 ################################################################
10089 11:16:58.943029
10090 11:16:59.613081 00680000 ################################################################
10091 11:16:59.613625
10092 11:17:00.300107 00700000 ################################################################
10093 11:17:00.300638
10094 11:17:00.964985 00780000 ################################################################
10095 11:17:00.965536
10096 11:17:01.628137 00800000 ################################################################
10097 11:17:01.628737
10098 11:17:02.209634 00880000 ################################################################
10099 11:17:02.209787
10100 11:17:02.830672 00900000 ################################################################
10101 11:17:02.830813
10102 11:17:03.451174 00980000 ################################################################
10103 11:17:03.451324
10104 11:17:04.062056 00a00000 ################################################################
10105 11:17:04.062568
10106 11:17:04.742065 00a80000 ################################################################
10107 11:17:04.742583
10108 11:17:05.395230 00b00000 ################################################################
10109 11:17:05.395387
10110 11:17:06.035770 00b80000 ################################################################
10111 11:17:06.035908
10112 11:17:06.688976 00c00000 ################################################################
10113 11:17:06.689118
10114 11:17:07.312820 00c80000 ################################################################
10115 11:17:07.312961
10116 11:17:07.951587 00d00000 ################################################################
10117 11:17:07.951728
10118 11:17:08.591673 00d80000 ################################################################
10119 11:17:08.591822
10120 11:17:09.233032 00e00000 ################################################################
10121 11:17:09.233178
10122 11:17:09.877778 00e80000 ################################################################
10123 11:17:09.877923
10124 11:17:10.519911 00f00000 ################################################################
10125 11:17:10.520082
10126 11:17:11.169410 00f80000 ################################################################
10127 11:17:11.169551
10128 11:17:11.798057 01000000 ################################################################
10129 11:17:11.798203
10130 11:17:12.447299 01080000 ################################################################
10131 11:17:12.447443
10132 11:17:13.094141 01100000 ################################################################
10133 11:17:13.094298
10134 11:17:13.766456 01180000 ################################################################
10135 11:17:13.766956
10136 11:17:14.435789 01200000 ################################################################
10137 11:17:14.436334
10138 11:17:15.092702 01280000 ################################################################
10139 11:17:15.093206
10140 11:17:15.758031 01300000 ################################################################
10141 11:17:15.758617
10142 11:17:16.445622 01380000 ################################################################
10143 11:17:16.446129
10144 11:17:17.058636 01400000 ################################################################
10145 11:17:17.058780
10146 11:17:17.668346 01480000 ################################################################
10147 11:17:17.668485
10148 11:17:18.286417 01500000 ################################################################
10149 11:17:18.286553
10150 11:17:18.878680 01580000 ################################################################
10151 11:17:18.878818
10152 11:17:19.519212 01600000 ################################################################
10153 11:17:19.519364
10154 11:17:20.130744 01680000 ################################################################
10155 11:17:20.130882
10156 11:17:20.764829 01700000 ################################################################
10157 11:17:20.764972
10158 11:17:21.409441 01780000 ################################################################
10159 11:17:21.409585
10160 11:17:21.985128 01800000 ################################################################
10161 11:17:21.985310
10162 11:17:22.564356 01880000 ################################################################
10163 11:17:22.564521
10164 11:17:23.205685 01900000 ################################################################
10165 11:17:23.205829
10166 11:17:23.846335 01980000 ################################################################
10167 11:17:23.846480
10168 11:17:24.488027 01a00000 ################################################################
10169 11:17:24.488207
10170 11:17:25.129804 01a80000 ################################################################
10171 11:17:25.129951
10172 11:17:25.798229 01b00000 ################################################################
10173 11:17:25.798785
10174 11:17:26.446785 01b80000 ################################################################
10175 11:17:26.446954
10176 11:17:27.083838 01c00000 ################################################################
10177 11:17:27.083982
10178 11:17:27.721060 01c80000 ################################################################
10179 11:17:27.721205
10180 11:17:28.359476 01d00000 ################################################################
10181 11:17:28.359621
10182 11:17:28.981336 01d80000 ################################################################
10183 11:17:28.981497
10184 11:17:29.580247 01e00000 ################################################################
10185 11:17:29.580407
10186 11:17:30.152815 01e80000 ################################################################
10187 11:17:30.152959
10188 11:17:30.750274 01f00000 ################################################################
10189 11:17:30.750420
10190 11:17:31.361957 01f80000 ################################################################
10191 11:17:31.362102
10192 11:17:31.935828 02000000 ################################################################
10193 11:17:31.935976
10194 11:17:32.532997 02080000 ################################################################
10195 11:17:32.533316
10196 11:17:33.217037 02100000 ################################################################
10197 11:17:33.217547
10198 11:17:33.857525 02180000 ################################################################
10199 11:17:33.857674
10200 11:17:34.499942 02200000 ################################################################
10201 11:17:34.500104
10202 11:17:35.115078 02280000 ################################################################
10203 11:17:35.115224
10204 11:17:35.719746 02300000 ################################################################
10205 11:17:35.719891
10206 11:17:36.292242 02380000 ################################################################
10207 11:17:36.292384
10208 11:17:36.869353 02400000 ################################################################
10209 11:17:36.869501
10210 11:17:37.456340 02480000 ################################################################
10211 11:17:37.456849
10212 11:17:38.125535 02500000 ################################################################
10213 11:17:38.126048
10214 11:17:38.799217 02580000 ################################################################
10215 11:17:38.799736
10216 11:17:39.457911 02600000 ################################################################
10217 11:17:39.458427
10218 11:17:40.093942 02680000 ################################################################
10219 11:17:40.094087
10220 11:17:40.727447 02700000 ################################################################
10221 11:17:40.727972
10222 11:17:41.409442 02780000 ################################################################
10223 11:17:41.409961
10224 11:17:42.094876 02800000 ################################################################
10225 11:17:42.095386
10226 11:17:42.722199 02880000 ################################################################
10227 11:17:42.722720
10228 11:17:43.392836 02900000 ################################################################
10229 11:17:43.393466
10230 11:17:44.071536 02980000 ################################################################
10231 11:17:44.072090
10232 11:17:44.720671 02a00000 ################################################################
10233 11:17:44.721247
10234 11:17:45.397812 02a80000 ################################################################
10235 11:17:45.398377
10236 11:17:46.074862 02b00000 ################################################################
10237 11:17:46.075369
10238 11:17:46.753385 02b80000 ################################################################
10239 11:17:46.753890
10240 11:17:47.436943 02c00000 ################################################################
10241 11:17:47.437454
10242 11:17:48.066682 02c80000 ################################################################
10243 11:17:48.066828
10244 11:17:48.726694 02d00000 ################################################################
10245 11:17:48.727209
10246 11:17:49.368163 02d80000 ################################################################
10247 11:17:49.368312
10248 11:17:49.946099 02e00000 ################################################################
10249 11:17:49.946247
10250 11:17:50.552824 02e80000 ################################################################
10251 11:17:50.552969
10252 11:17:51.180816 02f00000 ################################################################
10253 11:17:51.180958
10254 11:17:51.722202 02f80000 ######################################################## done.
10255 11:17:51.722343
10256 11:17:51.725332 The bootfile was 50259322 bytes long.
10257 11:17:51.725418
10258 11:17:51.729285 Sending tftp read request... done.
10259 11:17:51.729370
10260 11:17:51.732235 Waiting for the transfer...
10261 11:17:51.732325
10262 11:17:51.732398 00000000 # done.
10263 11:17:51.732467
10264 11:17:51.741672 Command line loaded dynamically from TFTP file: 10591263/tftp-deploy-_xk_g__a/kernel/cmdline
10265 11:17:51.741853
10266 11:17:51.751574 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10267 11:17:51.751776
10268 11:17:51.755334 Loading FIT.
10269 11:17:51.755611
10270 11:17:51.758457 Image ramdisk-1 has 40124341 bytes.
10271 11:17:51.758678
10272 11:17:51.758802 Image fdt-1 has 46924 bytes.
10273 11:17:51.758917
10274 11:17:51.761955 Image kernel-1 has 10086024 bytes.
10275 11:17:51.762200
10276 11:17:51.771532 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10277 11:17:51.771843
10278 11:17:51.788345 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10279 11:17:51.788903
10280 11:17:51.795339 Choosing best match conf-1 for compat google,spherion-rev2.
10281 11:17:51.798893
10282 11:17:51.804075 Connected to device vid:did:rid of 1ae0:0028:00
10283 11:17:51.811606
10284 11:17:51.815045 tpm_get_response: command 0x17b, return code 0x0
10285 11:17:51.815597
10286 11:17:51.821593 ec_init: CrosEC protocol v3 supported (256, 248)
10287 11:17:51.822129
10288 11:17:51.824862 tpm_cleanup: add release locality here.
10289 11:17:51.825322
10290 11:17:51.828105 Shutting down all USB controllers.
10291 11:17:51.828563
10292 11:17:51.831926 Removing current net device
10293 11:17:51.832525
10294 11:17:51.835182 Exiting depthcharge with code 4 at timestamp: 107148238
10295 11:17:51.835669
10296 11:17:51.841282 LZMA decompressing kernel-1 to 0x821a6718
10297 11:17:51.841879
10298 11:17:51.844725 LZMA decompressing kernel-1 to 0x40000000
10299 11:17:53.110050
10300 11:17:53.110184 jumping to kernel
10301 11:17:53.110598 end: 2.2.4 bootloader-commands (duration 00:01:19) [common]
10302 11:17:53.110695 start: 2.2.5 auto-login-action (timeout 00:03:06) [common]
10303 11:17:53.110769 Setting prompt string to ['Linux version [0-9]']
10304 11:17:53.110864 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10305 11:17:53.110975 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10306 11:17:53.192103
10307 11:17:53.195732 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10308 11:17:53.198931 start: 2.2.5.1 login-action (timeout 00:03:06) [common]
10309 11:17:53.199021 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10310 11:17:53.199108 Setting prompt string to ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing']
10311 11:17:53.199182 Using line separator: #'\n'#
10312 11:17:53.199240 No login prompt set.
10313 11:17:53.199330 Parsing kernel messages
10314 11:17:53.199384 ['-\\[ cut here \\]', 'Unhandled fault', 'BUG: KCSAN:', 'BUG: KASAN:', 'BUG: KFENCE:', 'Oops(?: -|:)', 'WARNING:', '(kernel BUG at|BUG:)', 'invalid opcode:', 'Kernel panic - not syncing', '/ #', 'Login timed out', 'Login incorrect']
10315 11:17:53.199481 [login-action] Waiting for messages, (timeout 00:03:06)
10316 11:17:53.218919 [ 0.000000] Linux version 6.1.31 (KernelCI@build-j1609115-arm64-gcc-10-defconfig-arm64-chromebook-dplkv) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Mon Jun 5 10:57:14 UTC 2023
10317 11:17:53.222011 [ 0.000000] random: crng init done
10318 11:17:53.228349 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10319 11:17:53.231774 [ 0.000000] efi: UEFI not found.
10320 11:17:53.238010 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10321 11:17:53.244598 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10322 11:17:53.254860 [ 0.000000] software IO TLB: Reserved memory: created restricted DMA pool at 0x00000000c0000000, size 64 MiB
10323 11:17:53.264522 [ 0.000000] OF: reserved mem: initialized node wifi@c0000000, compatible id restricted-dma-pool
10324 11:17:53.271013 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10325 11:17:53.277753 [ 0.000000] printk: bootconsole [mtk8250] enabled
10326 11:17:53.284660 [ 0.000000] NUMA: No NUMA configuration found
10327 11:17:53.291475 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10328 11:17:53.294535 [ 0.000000] NUMA: NODE_DATA [mem 0x23efcda00-0x23efcffff]
10329 11:17:53.297493 [ 0.000000] Zone ranges:
10330 11:17:53.304289 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10331 11:17:53.307199 [ 0.000000] DMA32 empty
10332 11:17:53.314388 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10333 11:17:53.317011 [ 0.000000] Movable zone start for each node
10334 11:17:53.320463 [ 0.000000] Early memory node ranges
10335 11:17:53.327269 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10336 11:17:53.333326 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10337 11:17:53.339934 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10338 11:17:53.346900 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10339 11:17:53.353267 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10340 11:17:53.359570 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10341 11:17:53.415650 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10342 11:17:53.422430 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10343 11:17:53.428968 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10344 11:17:53.431905 [ 0.000000] psci: probing for conduit method from DT.
10345 11:17:53.439295 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10346 11:17:53.441714 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10347 11:17:53.448970 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10348 11:17:53.451947 [ 0.000000] psci: SMC Calling Convention v1.2
10349 11:17:53.458373 [ 0.000000] percpu: Embedded 21 pages/cpu s45224 r8192 d32600 u86016
10350 11:17:53.461873 [ 0.000000] Detected VIPT I-cache on CPU0
10351 11:17:53.468893 [ 0.000000] CPU features: detected: GIC system register CPU interface
10352 11:17:53.474925 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10353 11:17:53.481491 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10354 11:17:53.488069 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10355 11:17:53.498027 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10356 11:17:53.505177 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10357 11:17:53.508348 [ 0.000000] alternatives: applying boot alternatives
10358 11:17:53.514476 [ 0.000000] Fallback order for Node 0: 0
10359 11:17:53.521066 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10360 11:17:53.524654 [ 0.000000] Policy zone: Normal
10361 11:17:53.534199 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10362 11:17:53.547746 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10363 11:17:53.557293 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10364 11:17:53.567184 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10365 11:17:53.574022 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10366 11:17:53.577395 <6>[ 0.000000] software IO TLB: area num 8.
10367 11:17:53.635149 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10368 11:17:53.784276 <6>[ 0.000000] Memory: 7933756K/8385536K available (17984K kernel code, 4098K rwdata, 14068K rodata, 8384K init, 615K bss, 419012K reserved, 32768K cma-reserved)
10369 11:17:53.791250 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10370 11:17:53.797287 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10371 11:17:53.800849 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10372 11:17:53.807190 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10373 11:17:53.814350 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10374 11:17:53.817209 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10375 11:17:53.827508 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10376 11:17:53.833469 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10377 11:17:53.841281 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10378 11:17:53.846550 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10379 11:17:53.850071 <6>[ 0.000000] GICv3: 608 SPIs implemented
10380 11:17:53.853120 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10381 11:17:53.860296 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10382 11:17:53.863530 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10383 11:17:53.869765 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10384 11:17:53.883095 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10385 11:17:53.896663 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10386 11:17:53.903172 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10387 11:17:53.911404 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10388 11:17:53.924321 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10389 11:17:53.930876 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10390 11:17:53.937532 <6>[ 0.009174] Console: colour dummy device 80x25
10391 11:17:53.947347 <6>[ 0.013901] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10392 11:17:53.953508 <6>[ 0.024408] pid_max: default: 32768 minimum: 301
10393 11:17:53.956964 <6>[ 0.029280] LSM: Security Framework initializing
10394 11:17:53.963349 <6>[ 0.034220] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10395 11:17:53.973600 <6>[ 0.042034] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10396 11:17:53.983238 <6>[ 0.051458] cblist_init_generic: Setting adjustable number of callback queues.
10397 11:17:53.990084 <6>[ 0.058913] cblist_init_generic: Setting shift to 3 and lim to 1.
10398 11:17:53.993220 <6>[ 0.065251] cblist_init_generic: Setting shift to 3 and lim to 1.
10399 11:17:54.000278 <6>[ 0.071658] rcu: Hierarchical SRCU implementation.
10400 11:17:54.006413 <6>[ 0.076702] rcu: Max phase no-delay instances is 1000.
10401 11:17:54.012943 <6>[ 0.083756] EFI services will not be available.
10402 11:17:54.016066 <6>[ 0.088728] smp: Bringing up secondary CPUs ...
10403 11:17:54.024288 <6>[ 0.093811] Detected VIPT I-cache on CPU1
10404 11:17:54.031468 <6>[ 0.093883] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10405 11:17:54.037544 <6>[ 0.093915] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10406 11:17:54.040655 <6>[ 0.094251] Detected VIPT I-cache on CPU2
10407 11:17:54.050825 <6>[ 0.094303] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10408 11:17:54.057380 <6>[ 0.094320] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10409 11:17:54.060414 <6>[ 0.094586] Detected VIPT I-cache on CPU3
10410 11:17:54.067296 <6>[ 0.094634] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10411 11:17:54.073510 <6>[ 0.094648] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10412 11:17:54.080460 <6>[ 0.094952] CPU features: detected: Spectre-v4
10413 11:17:54.084008 <6>[ 0.094957] CPU features: detected: Spectre-BHB
10414 11:17:54.086831 <6>[ 0.094964] Detected PIPT I-cache on CPU4
10415 11:17:54.093369 <6>[ 0.095021] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10416 11:17:54.103403 <6>[ 0.095038] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10417 11:17:54.106799 <6>[ 0.095337] Detected PIPT I-cache on CPU5
10418 11:17:54.112907 <6>[ 0.095401] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10419 11:17:54.119534 <6>[ 0.095417] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10420 11:17:54.122935 <6>[ 0.095702] Detected PIPT I-cache on CPU6
10421 11:17:54.132839 <6>[ 0.095767] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10422 11:17:54.140093 <6>[ 0.095784] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10423 11:17:54.142887 <6>[ 0.096082] Detected PIPT I-cache on CPU7
10424 11:17:54.149298 <6>[ 0.096148] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10425 11:17:54.156254 <6>[ 0.096164] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10426 11:17:54.159113 <6>[ 0.096211] smp: Brought up 1 node, 8 CPUs
10427 11:17:54.165868 <6>[ 0.237710] SMP: Total of 8 processors activated.
10428 11:17:54.172365 <6>[ 0.242661] CPU features: detected: 32-bit EL0 Support
10429 11:17:54.178874 <6>[ 0.248058] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10430 11:17:54.185619 <6>[ 0.256858] CPU features: detected: Common not Private translations
10431 11:17:54.191878 <6>[ 0.263334] CPU features: detected: CRC32 instructions
10432 11:17:54.199697 <6>[ 0.268685] CPU features: detected: RCpc load-acquire (LDAPR)
10433 11:17:54.202012 <6>[ 0.274645] CPU features: detected: LSE atomic instructions
10434 11:17:54.208354 <6>[ 0.280426] CPU features: detected: Privileged Access Never
10435 11:17:54.215370 <6>[ 0.286241] CPU features: detected: RAS Extension Support
10436 11:17:54.221906 <6>[ 0.291850] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10437 11:17:54.226003 <6>[ 0.299069] CPU: All CPU(s) started at EL2
10438 11:17:54.232290 <6>[ 0.303412] alternatives: applying system-wide alternatives
10439 11:17:54.241886 <6>[ 0.314156] devtmpfs: initialized
10440 11:17:54.255142 <6>[ 0.323311] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10441 11:17:54.264932 <6>[ 0.333277] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10442 11:17:54.271696 <6>[ 0.341320] pinctrl core: initialized pinctrl subsystem
10443 11:17:54.275252 <6>[ 0.347992] DMI not present or invalid.
10444 11:17:54.281146 <6>[ 0.352399] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10445 11:17:54.291348 <6>[ 0.359277] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10446 11:17:54.297891 <6>[ 0.366853] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10447 11:17:54.307771 <6>[ 0.375065] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10448 11:17:54.310850 <6>[ 0.383307] audit: initializing netlink subsys (disabled)
10449 11:17:54.320942 <5>[ 0.389001] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10450 11:17:54.327999 <6>[ 0.389711] thermal_sys: Registered thermal governor 'step_wise'
10451 11:17:54.333609 <6>[ 0.396967] thermal_sys: Registered thermal governor 'power_allocator'
10452 11:17:54.336886 <6>[ 0.403218] cpuidle: using governor menu
10453 11:17:54.343607 <6>[ 0.414178] NET: Registered PF_QIPCRTR protocol family
10454 11:17:54.350095 <6>[ 0.419656] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10455 11:17:54.356581 <6>[ 0.426760] ASID allocator initialised with 32768 entries
10456 11:17:54.359823 <6>[ 0.433336] Serial: AMBA PL011 UART driver
10457 11:17:54.370208 <4>[ 0.442009] Trying to register duplicate clock ID: 134
10458 11:17:54.424329 <6>[ 0.499608] KASLR enabled
10459 11:17:54.439362 <6>[ 0.507542] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10460 11:17:54.445161 <6>[ 0.514553] HugeTLB: 0 KiB vmemmap can be freed for a 1.00 GiB page
10461 11:17:54.451623 <6>[ 0.521043] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10462 11:17:54.458375 <6>[ 0.528047] HugeTLB: 0 KiB vmemmap can be freed for a 32.0 MiB page
10463 11:17:54.465721 <6>[ 0.534536] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10464 11:17:54.472171 <6>[ 0.541542] HugeTLB: 0 KiB vmemmap can be freed for a 2.00 MiB page
10465 11:17:54.478428 <6>[ 0.548029] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10466 11:17:54.484618 <6>[ 0.555037] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10467 11:17:54.488368 <6>[ 0.562565] ACPI: Interpreter disabled.
10468 11:17:54.496826 <6>[ 0.568968] iommu: Default domain type: Translated
10469 11:17:54.504066 <6>[ 0.574080] iommu: DMA domain TLB invalidation policy: strict mode
10470 11:17:54.507036 <5>[ 0.580734] SCSI subsystem initialized
10471 11:17:54.513698 <6>[ 0.584901] usbcore: registered new interface driver usbfs
10472 11:17:54.519949 <6>[ 0.590635] usbcore: registered new interface driver hub
10473 11:17:54.523100 <6>[ 0.596185] usbcore: registered new device driver usb
10474 11:17:54.530709 <6>[ 0.602266] pps_core: LinuxPPS API ver. 1 registered
10475 11:17:54.540756 <6>[ 0.607459] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10476 11:17:54.543511 <6>[ 0.616807] PTP clock support registered
10477 11:17:54.546926 <6>[ 0.621048] EDAC MC: Ver: 3.0.0
10478 11:17:54.554262 <6>[ 0.626185] FPGA manager framework
10479 11:17:54.557903 <6>[ 0.629865] Advanced Linux Sound Architecture Driver Initialized.
10480 11:17:54.561091 <6>[ 0.636644] vgaarb: loaded
10481 11:17:54.567961 <6>[ 0.639810] clocksource: Switched to clocksource arch_sys_counter
10482 11:17:54.574949 <5>[ 0.646248] VFS: Disk quotas dquot_6.6.0
10483 11:17:54.581068 <6>[ 0.650432] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10484 11:17:54.584229 <6>[ 0.657618] pnp: PnP ACPI: disabled
10485 11:17:54.592979 <6>[ 0.664364] NET: Registered PF_INET protocol family
10486 11:17:54.602158 <6>[ 0.669961] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10487 11:17:54.613576 <6>[ 0.682269] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10488 11:17:54.624186 <6>[ 0.691083] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10489 11:17:54.629965 <6>[ 0.699056] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10490 11:17:54.640370 <6>[ 0.707754] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10491 11:17:54.647041 <6>[ 0.717497] TCP: Hash tables configured (established 65536 bind 65536)
10492 11:17:54.653259 <6>[ 0.724353] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10493 11:17:54.662678 <6>[ 0.731552] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10494 11:17:54.669295 <6>[ 0.739249] NET: Registered PF_UNIX/PF_LOCAL protocol family
10495 11:17:54.676319 <6>[ 0.745416] RPC: Registered named UNIX socket transport module.
10496 11:17:54.679170 <6>[ 0.751568] RPC: Registered udp transport module.
10497 11:17:54.686054 <6>[ 0.756504] RPC: Registered tcp transport module.
10498 11:17:54.692433 <6>[ 0.761436] RPC: Registered tcp NFSv4.1 backchannel transport module.
10499 11:17:54.696377 <6>[ 0.768104] PCI: CLS 0 bytes, default 64
10500 11:17:54.699203 <6>[ 0.772494] Unpacking initramfs...
10501 11:17:54.709957 <6>[ 0.776297] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10502 11:17:54.715768 <6>[ 0.784965] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10503 11:17:54.722168 <6>[ 0.793754] kvm [1]: IPA Size Limit: 40 bits
10504 11:17:54.725492 <6>[ 0.798280] kvm [1]: GICv3: no GICV resource entry
10505 11:17:54.732411 <6>[ 0.803303] kvm [1]: disabling GICv2 emulation
10506 11:17:54.738819 <6>[ 0.807988] kvm [1]: GIC system register CPU interface enabled
10507 11:17:54.742301 <6>[ 0.814158] kvm [1]: vgic interrupt IRQ18
10508 11:17:54.745583 <6>[ 0.818515] kvm [1]: VHE mode initialized successfully
10509 11:17:54.752800 <5>[ 0.824916] Initialise system trusted keyrings
10510 11:17:54.759376 <6>[ 0.829704] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10511 11:17:54.767614 <6>[ 0.839769] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10512 11:17:54.774281 <5>[ 0.846162] NFS: Registering the id_resolver key type
10513 11:17:54.777735 <5>[ 0.851467] Key type id_resolver registered
10514 11:17:54.784488 <5>[ 0.855883] Key type id_legacy registered
10515 11:17:54.790901 <6>[ 0.860162] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10516 11:17:54.797211 <6>[ 0.867084] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10517 11:17:54.803767 <6>[ 0.874804] 9p: Installing v9fs 9p2000 file system support
10518 11:17:54.840972 <5>[ 0.913034] Key type asymmetric registered
10519 11:17:54.844364 <5>[ 0.917367] Asymmetric key parser 'x509' registered
10520 11:17:54.854479 <6>[ 0.922508] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
10521 11:17:54.857825 <6>[ 0.930127] io scheduler mq-deadline registered
10522 11:17:54.860680 <6>[ 0.934885] io scheduler kyber registered
10523 11:17:54.880200 <6>[ 0.951704] EINJ: ACPI disabled.
10524 11:17:54.911744 <4>[ 0.977077] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10525 11:17:54.921656 <4>[ 0.987739] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10526 11:17:54.936368 <6>[ 1.008481] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10527 11:17:54.944221 <6>[ 1.016464] printk: console [ttyS0] disabled
10528 11:17:54.972440 <6>[ 1.041106] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 255, base_baud = 1625000) is a ST16650V2
10529 11:17:54.978740 <6>[ 1.050597] printk: console [ttyS0] enabled
10530 11:17:54.981985 <6>[ 1.050597] printk: console [ttyS0] enabled
10531 11:17:54.989017 <6>[ 1.059500] printk: bootconsole [mtk8250] disabled
10532 11:17:54.992143 <6>[ 1.059500] printk: bootconsole [mtk8250] disabled
10533 11:17:54.998816 <6>[ 1.070755] SuperH (H)SCI(F) driver initialized
10534 11:17:55.001915 <6>[ 1.076026] msm_serial: driver initialized
10535 11:17:55.016176 <6>[ 1.084940] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14005000
10536 11:17:55.026183 <6>[ 1.093487] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14006000
10537 11:17:55.032867 <6>[ 1.102029] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14007000
10538 11:17:55.042655 <6>[ 1.110658] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/color@14009000
10539 11:17:55.052335 <6>[ 1.119362] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ccorr@1400a000
10540 11:17:55.059013 <6>[ 1.128081] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/aal@1400b000
10541 11:17:55.069267 <6>[ 1.136622] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/gamma@1400c000
10542 11:17:55.075576 <6>[ 1.145420] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/ovl@14014000
10543 11:17:55.085479 <6>[ 1.153963] mediatek-drm mediatek-drm.1.auto: Adding component match for /soc/rdma@14015000
10544 11:17:55.097736 <6>[ 1.169632] loop: module loaded
10545 11:17:55.104349 <6>[ 1.175747] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10546 11:17:55.127444 <4>[ 1.199358] mtk-pmic-keys: Failed to locate of_node [id: -1]
10547 11:17:55.134622 <6>[ 1.206385] megasas: 07.719.03.00-rc1
10548 11:17:55.143999 <6>[ 1.216138] spi-nor spi2.0: w25q64jwm (8192 Kbytes)
10549 11:17:55.155276 <6>[ 1.227189] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 2
10550 11:17:55.172186 <6>[ 1.244015] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10551 11:17:55.229039 <6>[ 1.294498] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_B:0.6.153/cr50_v3.94_pp.113-620c9
10552 11:17:56.324353 <6>[ 2.396546] Freeing initrd memory: 39180K
10553 11:17:56.334282 <6>[ 2.406569] mtk-spi-nor 11234000.spi: spi frequency: 52000000 Hz
10554 11:17:56.345415 <6>[ 2.417537] tun: Universal TUN/TAP device driver, 1.6
10555 11:17:56.348792 <6>[ 2.423585] thunder_xcv, ver 1.0
10556 11:17:56.351828 <6>[ 2.427087] thunder_bgx, ver 1.0
10557 11:17:56.355283 <6>[ 2.430583] nicpf, ver 1.0
10558 11:17:56.365934 <6>[ 2.434583] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10559 11:17:56.369094 <6>[ 2.442058] hns3: Copyright (c) 2017 Huawei Corporation.
10560 11:17:56.376039 <6>[ 2.447644] hclge is initializing
10561 11:17:56.379244 <6>[ 2.451223] e1000: Intel(R) PRO/1000 Network Driver
10562 11:17:56.385721 <6>[ 2.456352] e1000: Copyright (c) 1999-2006 Intel Corporation.
10563 11:17:56.389090 <6>[ 2.462365] e1000e: Intel(R) PRO/1000 Network Driver
10564 11:17:56.395545 <6>[ 2.467581] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10565 11:17:56.401995 <6>[ 2.473769] igb: Intel(R) Gigabit Ethernet Network Driver
10566 11:17:56.409536 <6>[ 2.479420] igb: Copyright (c) 2007-2014 Intel Corporation.
10567 11:17:56.415791 <6>[ 2.485256] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10568 11:17:56.421780 <6>[ 2.491775] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10569 11:17:56.425261 <6>[ 2.498234] sky2: driver version 1.30
10570 11:17:56.431662 <6>[ 2.503206] VFIO - User Level meta-driver version: 0.3
10571 11:17:56.439064 <6>[ 2.511338] usbcore: registered new interface driver usb-storage
10572 11:17:56.445956 <6>[ 2.517785] usbcore: registered new device driver onboard-usb-hub
10573 11:17:56.455084 <6>[ 2.526806] mt6397-rtc mt6359-rtc: registered as rtc0
10574 11:17:56.464340 <6>[ 2.532271] mt6397-rtc mt6359-rtc: setting system clock to 2023-06-05T11:17:56 UTC (1685963876)
10575 11:17:56.468337 <6>[ 2.541834] i2c_dev: i2c /dev entries driver
10576 11:17:56.484638 <6>[ 2.553478] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10577 11:17:56.491777 <6>[ 2.563667] sdhci: Secure Digital Host Controller Interface driver
10578 11:17:56.498257 <6>[ 2.570106] sdhci: Copyright(c) Pierre Ossman
10579 11:17:56.504674 <6>[ 2.575499] Synopsys Designware Multimedia Card Interface Driver
10580 11:17:56.507970 <6>[ 2.582230] mmc0: CQHCI version 5.10
10581 11:17:56.514418 <6>[ 2.582653] sdhci-pltfm: SDHCI platform and OF driver helper
10582 11:17:56.522380 <6>[ 2.594143] ledtrig-cpu: registered to indicate activity on CPUs
10583 11:17:56.532684 <6>[ 2.601432] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10584 11:17:56.536010 <6>[ 2.608818] usbcore: registered new interface driver usbhid
10585 11:17:56.542894 <6>[ 2.614644] usbhid: USB HID core driver
10586 11:17:56.548859 <6>[ 2.618886] spi_master spi0: will run message pump with realtime priority
10587 11:17:56.593848 <6>[ 2.659438] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10588 11:17:56.611863 <6>[ 2.674426] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10589 11:17:56.615876 <6>[ 2.687999] mmc0: Command Queue Engine enabled
10590 11:17:56.622118 <6>[ 2.692745] mmc0: new HS400 Enhanced strobe MMC card at address 0001
10591 11:17:56.628795 <6>[ 2.699920] cros-ec-spi spi0.0: Chrome EC device registered
10592 11:17:56.632693 <6>[ 2.700151] mmcblk0: mmc0:0001 DA4128 116 GiB
10593 11:17:56.645102 <6>[ 2.717650] mmcblk0: p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12
10594 11:17:56.652610 <6>[ 2.725006] mmcblk0boot0: mmc0:0001 DA4128 4.00 MiB
10595 11:17:56.659632 <6>[ 2.731027] mmcblk0boot1: mmc0:0001 DA4128 4.00 MiB
10596 11:17:56.665985 <6>[ 2.736990] mmcblk0rpmb: mmc0:0001 DA4128 16.0 MiB, chardev (507:0)
10597 11:17:56.676168 <6>[ 2.738620] mt6359-sound mt6359-sound: mt6359_parse_dt() failed to read mic-type-1, use default (0)
10598 11:17:56.682660 <6>[ 2.754858] NET: Registered PF_PACKET protocol family
10599 11:17:56.689395 <6>[ 2.760308] 9pnet: Installing 9P2000 support
10600 11:17:56.692318 <5>[ 2.764897] Key type dns_resolver registered
10601 11:17:56.695790 <6>[ 2.770065] registered taskstats version 1
10602 11:17:56.702146 <5>[ 2.774478] Loading compiled-in X.509 certificates
10603 11:17:56.738780 <4>[ 2.804088] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10604 11:17:56.748230 <4>[ 2.814856] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10605 11:17:56.758459 <3>[ 2.827469] mediatek-mutex 14001000.mutex: error -2 can't parse gce-client-reg property (0)
10606 11:17:56.770859 <6>[ 2.842842] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10607 11:17:56.777759 <6>[ 2.849599] xhci-mtk 11200000.usb: xHCI Host Controller
10608 11:17:56.783846 <6>[ 2.855097] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10609 11:17:56.793874 <6>[ 2.862949] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10610 11:17:56.800546 <6>[ 2.872382] xhci-mtk 11200000.usb: irq 271, io mem 0x11200000
10611 11:17:56.807057 <6>[ 2.878469] xhci-mtk 11200000.usb: xHCI Host Controller
10612 11:17:56.814157 <6>[ 2.884051] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10613 11:17:56.820344 <6>[ 2.891723] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10614 11:17:56.827155 <6>[ 2.899453] hub 1-0:1.0: USB hub found
10615 11:17:56.830684 <6>[ 2.903485] hub 1-0:1.0: 1 port detected
10616 11:17:56.840323 <6>[ 2.907835] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10617 11:17:56.843952 <6>[ 2.916431] hub 2-0:1.0: USB hub found
10618 11:17:56.847224 <6>[ 2.920446] hub 2-0:1.0: 1 port detected
10619 11:17:56.855326 <6>[ 2.927486] mtk-msdc 11f70000.mmc: Got CD GPIO
10620 11:17:56.871799 <6>[ 2.940769] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_resume()
10621 11:17:56.878651 <6>[ 2.948795] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_enable_clock()
10622 11:17:56.889996 <4>[ 2.956757] mt8192-audio 11210000.syscon:mt8192-afe-pcm: No cache defaults, reading back from HW
10623 11:17:56.898880 <6>[ 2.966426] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_runtime_suspend()
10624 11:17:56.904699 <6>[ 2.974506] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_afe_disable_clock()
10625 11:17:56.914942 <6>[ 2.982535] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_adda_register()
10626 11:17:56.921485 <6>[ 2.990451] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_pcm_register()
10627 11:17:56.928253 <6>[ 2.998272] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mt8192_dai_tdm_register()
10628 11:17:56.937956 <6>[ 3.006093] mt8192-audio 11210000.syscon:mt8192-afe-pcm: mtk_afe_combine_sub_dai(), num of dai 39
10629 11:17:56.948173 <6>[ 3.016855] mtk-iommu 1401d000.m4u: bound 14003000.larb (ops mtk_smi_larb_component_ops)
10630 11:17:56.958234 <6>[ 3.025225] mtk-iommu 1401d000.m4u: bound 14004000.larb (ops mtk_smi_larb_component_ops)
10631 11:17:56.964333 <6>[ 3.033573] mtk-iommu 1401d000.m4u: bound 1f002000.larb (ops mtk_smi_larb_component_ops)
10632 11:17:56.974203 <6>[ 3.041916] mtk-iommu 1401d000.m4u: bound 1602e000.larb (ops mtk_smi_larb_component_ops)
10633 11:17:56.981025 <6>[ 3.050261] mtk-iommu 1401d000.m4u: bound 1600d000.larb (ops mtk_smi_larb_component_ops)
10634 11:17:56.991253 <6>[ 3.058604] mtk-iommu 1401d000.m4u: bound 17010000.larb (ops mtk_smi_larb_component_ops)
10635 11:17:56.997623 <6>[ 3.066946] mtk-iommu 1401d000.m4u: bound 1502e000.larb (ops mtk_smi_larb_component_ops)
10636 11:17:57.007327 <6>[ 3.075289] mtk-iommu 1401d000.m4u: bound 1582e000.larb (ops mtk_smi_larb_component_ops)
10637 11:17:57.014366 <6>[ 3.083632] mtk-iommu 1401d000.m4u: bound 1a001000.larb (ops mtk_smi_larb_component_ops)
10638 11:17:57.023667 <6>[ 3.091974] mtk-iommu 1401d000.m4u: bound 1a002000.larb (ops mtk_smi_larb_component_ops)
10639 11:17:57.030273 <6>[ 3.100317] mtk-iommu 1401d000.m4u: bound 1a00f000.larb (ops mtk_smi_larb_component_ops)
10640 11:17:57.040319 <6>[ 3.108660] mtk-iommu 1401d000.m4u: bound 1a010000.larb (ops mtk_smi_larb_component_ops)
10641 11:17:57.046898 <6>[ 3.117002] mtk-iommu 1401d000.m4u: bound 1a011000.larb (ops mtk_smi_larb_component_ops)
10642 11:17:57.057394 <6>[ 3.125346] mtk-iommu 1401d000.m4u: bound 1b10f000.larb (ops mtk_smi_larb_component_ops)
10643 11:17:57.063273 <6>[ 3.133693] mtk-iommu 1401d000.m4u: bound 1b00f000.larb (ops mtk_smi_larb_component_ops)
10644 11:17:57.070423 <6>[ 3.142607] mediatek-disp-ovl 14005000.ovl: Adding to iommu group 0
10645 11:17:57.077937 <6>[ 3.150046] mediatek-disp-ovl 14006000.ovl: Adding to iommu group 0
10646 11:17:57.085144 <6>[ 3.157070] mediatek-disp-ovl 14014000.ovl: Adding to iommu group 0
10647 11:17:57.095410 <6>[ 3.164179] mediatek-disp-rdma 14007000.rdma: Adding to iommu group 0
10648 11:17:57.102201 <6>[ 3.171462] mediatek-disp-rdma 14015000.rdma: Adding to iommu group 0
10649 11:17:57.111964 <6>[ 3.178369] mediatek-drm mediatek-drm.1.auto: bound 14005000.ovl (ops mtk_disp_ovl_component_ops)
10650 11:17:57.118958 <6>[ 3.187512] mediatek-drm mediatek-drm.1.auto: bound 14006000.ovl (ops mtk_disp_ovl_component_ops)
10651 11:17:57.128589 <6>[ 3.196639] mediatek-drm mediatek-drm.1.auto: bound 14007000.rdma (ops mtk_disp_rdma_component_ops)
10652 11:17:57.138764 <6>[ 3.205942] mediatek-drm mediatek-drm.1.auto: bound 14009000.color (ops mtk_disp_color_component_ops)
10653 11:17:57.148207 <6>[ 3.215417] mediatek-drm mediatek-drm.1.auto: bound 1400a000.ccorr (ops mtk_disp_ccorr_component_ops)
10654 11:17:57.157843 <6>[ 3.224892] mediatek-drm mediatek-drm.1.auto: bound 1400b000.aal (ops mtk_disp_aal_component_ops)
10655 11:17:57.165339 <6>[ 3.234019] mediatek-drm mediatek-drm.1.auto: bound 1400c000.gamma (ops mtk_disp_gamma_component_ops)
10656 11:17:57.174480 <6>[ 3.243499] mediatek-drm mediatek-drm.1.auto: bound 14014000.ovl (ops mtk_disp_ovl_component_ops)
10657 11:17:57.184571 <6>[ 3.252630] mediatek-drm mediatek-drm.1.auto: bound 14015000.rdma (ops mtk_disp_rdma_component_ops)
10658 11:17:57.194361 <6>[ 3.261932] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 14 is disabled or missing
10659 11:17:57.204392 <6>[ 3.272098] mediatek-drm mediatek-drm.1.auto: Not creating crtc 0 because component 10 is disabled or missing
10660 11:17:57.214833 <6>[ 3.283869] [drm] Initialized mediatek 1.0.0 20150513 for mediatek-drm.1.auto on minor 0
10661 11:17:57.258823 <6>[ 3.328087] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10662 11:17:57.412700 <6>[ 3.485022] hub 1-1:1.0: USB hub found
10663 11:17:57.415828 <6>[ 3.489454] hub 1-1:1.0: 4 ports detected
10664 11:17:57.539357 <6>[ 3.608291] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10665 11:17:57.564273 <6>[ 3.636565] hub 2-1:1.0: USB hub found
10666 11:17:57.567875 <6>[ 3.640961] hub 2-1:1.0: 3 ports detected
10667 11:17:57.735093 <6>[ 3.804088] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10668 11:17:57.867886 <6>[ 3.940152] hub 1-1.4:1.0: USB hub found
10669 11:17:57.871848 <6>[ 3.944772] hub 1-1.4:1.0: 2 ports detected
10670 11:17:57.947707 <6>[ 4.016315] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10671 11:17:58.167530 <6>[ 4.236082] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10672 11:17:58.358868 <6>[ 4.428083] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10673 11:18:09.488035 <6>[ 15.564709] ALSA device list:
10674 11:18:09.494364 <6>[ 15.567967] No soundcards found.
10675 11:18:09.506863 <6>[ 15.580405] Freeing unused kernel memory: 8384K
10676 11:18:09.509913 <6>[ 15.585336] Run /init as init process
10677 11:18:09.540385 <6>[ 15.614286] NET: Registered PF_INET6 protocol family
10678 11:18:09.547027 <6>[ 15.620889] Segment Routing with IPv6
10679 11:18:09.550511 <6>[ 15.624845] In-situ OAM (IOAM) with IPv6
10680 11:18:09.585469 <30>[ 15.639430] systemd[1]: systemd 247.3-7+deb11u2 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
10681 11:18:09.589015 <30>[ 15.663183] systemd[1]: Detected architecture arm64.
10682 11:18:09.589102
10683 11:18:09.595613 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
10684 11:18:09.595723
10685 11:18:09.610611 <30>[ 15.684238] systemd[1]: Set hostname to <debian-bullseye-arm64>.
10686 11:18:09.755972 <30>[ 15.825919] systemd[1]: Queued start job for default target Graphical Interface.
10687 11:18:09.799723 <30>[ 15.873216] systemd[1]: Created slice system-getty.slice.
10688 11:18:09.806072 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
10689 11:18:09.822937 <30>[ 15.896630] systemd[1]: Created slice system-modprobe.slice.
10690 11:18:09.829582 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
10691 11:18:09.847977 <30>[ 15.921227] systemd[1]: Created slice system-serial\x2dgetty.slice.
10692 11:18:09.857569 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
10693 11:18:09.871116 <30>[ 15.944576] systemd[1]: Created slice User and Session Slice.
10694 11:18:09.877581 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
10695 11:18:09.898008 <30>[ 15.968644] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
10696 11:18:09.908236 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
10697 11:18:09.926559 <30>[ 15.996253] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
10698 11:18:09.932431 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
10699 11:18:09.953421 <30>[ 16.020170] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
10700 11:18:09.959812 <30>[ 16.032196] systemd[1]: Reached target Local Encrypted Volumes.
10701 11:18:09.966745 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
10702 11:18:09.982196 <30>[ 16.056181] systemd[1]: Reached target Paths.
10703 11:18:09.985549 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
10704 11:18:10.002167 <30>[ 16.076124] systemd[1]: Reached target Remote File Systems.
10705 11:18:10.009432 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
10706 11:18:10.022888 <30>[ 16.096103] systemd[1]: Reached target Slices.
10707 11:18:10.025519 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
10708 11:18:10.042415 <30>[ 16.116126] systemd[1]: Reached target Swap.
10709 11:18:10.045540 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
10710 11:18:10.066182 <30>[ 16.136380] systemd[1]: Listening on initctl Compatibility Named Pipe.
10711 11:18:10.072283 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
10712 11:18:10.079039 <30>[ 16.151055] systemd[1]: Listening on Journal Audit Socket.
10713 11:18:10.085911 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
10714 11:18:10.098335 <30>[ 16.172374] systemd[1]: Listening on Journal Socket (/dev/log).
10715 11:18:10.105479 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
10716 11:18:10.123183 <30>[ 16.196861] systemd[1]: Listening on Journal Socket.
10717 11:18:10.129758 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
10718 11:18:10.146129 <30>[ 16.216507] systemd[1]: Listening on Network Service Netlink Socket.
10719 11:18:10.153246 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
10720 11:18:10.167088 <30>[ 16.240882] systemd[1]: Listening on udev Control Socket.
10721 11:18:10.173871 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
10722 11:18:10.190890 <30>[ 16.264798] systemd[1]: Listening on udev Kernel Socket.
10723 11:18:10.197557 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
10724 11:18:10.234849 <30>[ 16.308300] systemd[1]: Mounting Huge Pages File System...
10725 11:18:10.241433 Mounting [0;1;39mHuge Pages File System[0m...
10726 11:18:10.256281 <30>[ 16.330086] systemd[1]: Mounting POSIX Message Queue File System...
10727 11:18:10.262881 Mounting [0;1;39mPOSIX Message Queue File System[0m...
10728 11:18:10.280516 <30>[ 16.354056] systemd[1]: Mounting Kernel Debug File System...
10729 11:18:10.286816 Mounting [0;1;39mKernel Debug File System[0m...
10730 11:18:10.305557 <30>[ 16.376289] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
10731 11:18:10.316667 <30>[ 16.387111] systemd[1]: Starting Create list of static device nodes for the current kernel...
10732 11:18:10.323267 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
10733 11:18:10.340661 <30>[ 16.414181] systemd[1]: Starting Load Kernel Module configfs...
10734 11:18:10.347218 Starting [0;1;39mLoad Kernel Module configfs[0m...
10735 11:18:10.364416 <30>[ 16.438214] systemd[1]: Starting Load Kernel Module drm...
10736 11:18:10.370813 Starting [0;1;39mLoad Kernel Module drm[0m...
10737 11:18:10.389890 <30>[ 16.460221] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
10738 11:18:10.400433 <30>[ 16.473805] systemd[1]: Starting Journal Service...
10739 11:18:10.403460 Starting [0;1;39mJournal Service[0m...
10740 11:18:10.420879 <30>[ 16.494766] systemd[1]: Starting Load Kernel Modules...
10741 11:18:10.427569 Starting [0;1;39mLoad Kernel Modules[0m...
10742 11:18:10.448782 <30>[ 16.518562] systemd[1]: Starting Remount Root and Kernel File Systems...
10743 11:18:10.454453 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
10744 11:18:10.468917 <30>[ 16.542954] systemd[1]: Starting Coldplug All udev Devices...
10745 11:18:10.475731 Starting [0;1;39mColdplug All udev Devices[0m...
10746 11:18:10.493818 <30>[ 16.567491] systemd[1]: Mounted Huge Pages File System.
10747 11:18:10.500292 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
10748 11:18:10.514897 <30>[ 16.588845] systemd[1]: Started Journal Service.
10749 11:18:10.521723 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
10750 11:18:10.536904 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
10751 11:18:10.554904 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
10752 11:18:10.575201 [[0;32m OK [0m] Finished [0;1;39mCreate list of st… nodes for the current kernel[0m.
10753 11:18:10.591828 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
10754 11:18:10.607516 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
10755 11:18:10.623897 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
10756 11:18:10.643594 [[0;1;31mFAILED[0m] Failed to start [0;1;39mRemount Root and Kernel File Systems[0m.
10757 11:18:10.658594 See 'systemctl status systemd-remount-fs.service' for details.
10758 11:18:10.715534 Mounting [0;1;39mKernel Configuration File System[0m...
10759 11:18:10.733010 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
10760 11:18:10.750553 <46>[ 16.821177] systemd-journald[174]: Received client request to flush runtime journal.
10761 11:18:10.759117 Starting [0;1;39mLoad/Save Random Seed[0m...
10762 11:18:10.776961 Starting [0;1;39mApply Kernel Variables[0m...
10763 11:18:10.793906 Starting [0;1;39mCreate System Users[0m...
10764 11:18:10.809125 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
10765 11:18:10.834686 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
10766 11:18:10.847276 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
10767 11:18:10.863259 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
10768 11:18:10.883895 [[0;32m OK [0m] Finished [0;1;39mColdplug All udev Devices[0m.
10769 11:18:10.903132 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
10770 11:18:10.943074 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
10771 11:18:10.965451 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
10772 11:18:10.979358 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
10773 11:18:10.994203 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
10774 11:18:11.042788 Starting [0;1;39mCreate Volatile Files and Directories[0m...
10775 11:18:11.066299 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
10776 11:18:11.083926 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
10777 11:18:11.103767 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
10778 11:18:11.167515 Starting [0;1;39mNetwork Service[0m...
10779 11:18:11.190163 Starting [0;1;39mNetwork Time Synchronization[0m...
10780 11:18:11.212011 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
10781 11:18:11.261317 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
10782 11:18:11.276209 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
10783 11:18:11.312681 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
10784 11:18:11.347874 <6>[ 17.418479] mtk-pcie-gen3 11230000.pcie: host bridge /soc/pcie@11230000 ranges:
10785 11:18:11.357799 <6>[ 17.426467] mtk-pcie-gen3 11230000.pcie: MEM 0x0012000000..0x00127fffff -> 0x0012000000
10786 11:18:11.364160 <6>[ 17.435330] mtk-pcie-gen3 11230000.pcie: IO 0x0012800000..0x0012ffffff -> 0x0012800000
10787 11:18:11.371434 <6>[ 17.437602] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10788 11:18:11.381331 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
10789 11:18:11.395676 <3>[ 17.466172] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10790 11:18:11.402673 <3>[ 17.474391] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10791 11:18:11.408753 <6>[ 17.476385] remoteproc remoteproc0: scp is available
10792 11:18:11.415299 <3>[ 17.482773] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10793 11:18:11.421986 <6>[ 17.489411] remoteproc remoteproc0: powering up scp
10794 11:18:11.431804 <3>[ 17.498452] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10795 11:18:11.438719 <6>[ 17.501358] remoteproc remoteproc0: Booting fw image mediatek/mt8192/scp.img, size 309164
10796 11:18:11.441635 <6>[ 17.501817] mc: Linux media interface: v0.10
10797 11:18:11.451588 <3>[ 17.509393] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10798 11:18:11.458587 <6>[ 17.517821] mtk-scp 10500000.scp: IPI buf addr 0x000ffdb0
10799 11:18:11.465013 <4>[ 17.518772] elants_i2c 4-0010: supply vcc33 not found, using dummy regulator
10800 11:18:11.471674 <6>[ 17.520354] videodev: Linux video capture interface: v2.00
10801 11:18:11.478014 <3>[ 17.522432] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10802 11:18:11.484662 <4>[ 17.531758] elants_i2c 4-0010: supply vccio not found, using dummy regulator
10803 11:18:11.494641 <3>[ 17.552325] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10804 11:18:11.501491 <6>[ 17.560956] sbs-battery 5-000b: sbs-battery: battery gas gauge device registered
10805 11:18:11.510922 <3>[ 17.564780] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10806 11:18:11.518148 <6>[ 17.566637] mtk-pcie-gen3 11230000.pcie: PCI host bridge to bus 0000:00
10807 11:18:11.521695 <6>[ 17.566646] pci_bus 0000:00: root bus resource [bus 00-ff]
10808 11:18:11.531082 <6>[ 17.566652] pci_bus 0000:00: root bus resource [mem 0x12000000-0x127fffff]
10809 11:18:11.540750 <6>[ 17.566657] pci_bus 0000:00: root bus resource [io 0x0000-0x7fffff] (bus address [0x12800000-0x12ffffff])
10810 11:18:11.544018 <6>[ 17.566689] pci 0000:00:00.0: [14c3:6786] type 01 class 0x060400
10811 11:18:11.554174 <6>[ 17.566709] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x00003fff 64bit pref]
10812 11:18:11.557764 <6>[ 17.566793] pci 0000:00:00.0: supports D1 D2
10813 11:18:11.564303 <6>[ 17.566797] pci 0000:00:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10814 11:18:11.574006 <6>[ 17.568548] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
10815 11:18:11.581490 <6>[ 17.573398] pci 0000:01:00.0: [14c3:7961] type 00 class 0x028000
10816 11:18:11.587121 <3>[ 17.580715] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10817 11:18:11.597629 <6>[ 17.588929] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x000fffff 64bit pref]
10818 11:18:11.603863 <3>[ 17.602770] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10819 11:18:11.610235 <6>[ 17.605202] usbcore: registered new interface driver r8152
10820 11:18:11.616628 <6>[ 17.608608] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00003fff 64bit pref]
10821 11:18:11.623414 <3>[ 17.618838] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10822 11:18:11.633604 <6>[ 17.624709] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00000fff 64bit pref]
10823 11:18:11.636885 <6>[ 17.624947] pci 0000:01:00.0: supports D1 D2
10824 11:18:11.646903 <4>[ 17.632283] sbs-battery 5-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10825 11:18:11.650792 <4>[ 17.632283] Fallback method does not support PEC.
10826 11:18:11.659936 <3>[ 17.632817] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10827 11:18:11.666730 <3>[ 17.633010] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10828 11:18:11.673169 <3>[ 17.633020] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10829 11:18:11.683034 <3>[ 17.633033] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10830 11:18:11.689736 <3>[ 17.633050] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10831 11:18:11.699438 <3>[ 17.633105] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10832 11:18:11.706374 <3>[ 17.633231] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10833 11:18:11.713009 <6>[ 17.639946] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold
10834 11:18:11.722804 <6>[ 17.715988] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10835 11:18:11.729797 <6>[ 17.729519] mtk-scp 10500000.scp: creating channel cros-ec-rpmsg addr 0xd
10836 11:18:11.736196 <6>[ 17.729798] input: Elan Touchscreen as /devices/platform/soc/11f00000.i2c/i2c-4/4-0010/input/input2
10837 11:18:11.745986 <6>[ 17.748054] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
10838 11:18:11.752617 <6>[ 17.753730] mtk-scp 10500000.scp: SCP is ready. FW version asurada_scp_v2.0.20536+a3bcde3e
10839 11:18:11.759987 <6>[ 17.761822] pci 0000:00:00.0: BAR 15: assigned [mem 0x12000000-0x121fffff 64bit pref]
10840 11:18:11.766000 <6>[ 17.770467] remoteproc remoteproc0: remote processor scp is now up
10841 11:18:11.775972 <6>[ 17.778081] pci 0000:00:00.0: BAR 0: assigned [mem 0x12200000-0x12203fff 64bit pref]
10842 11:18:11.786417 <6>[ 17.788958] elan_i2c 3-0015: Elan Touchpad: Module ID: 0x0128, Firmware: 0x0001, Sample: 0x0001, IAP: 0x0003
10843 11:18:11.795953 <4>[ 17.789802] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10844 11:18:11.802336 <4>[ 17.789817] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10845 11:18:11.812678 <6>[ 17.792982] pci 0000:01:00.0: BAR 0: assigned [mem 0x12000000-0x120fffff 64bit pref]
10846 11:18:11.819206 <6>[ 17.795446] cros-ec-dev cros-ec-dev.10.auto: CrOS System Control Processor MCU detected
10847 11:18:11.828746 <6>[ 17.798571] cros-ec-rpmsg 10500000.scp.cros-ec-rpmsg.13.-1: Chrome EC device registered
10848 11:18:11.835467 <6>[ 17.800873] input: Elan Touchpad as /devices/platform/soc/11d21000.i2c/i2c-3/3-0015/input/input3
10849 11:18:11.845390 <6>[ 17.807146] pci 0000:01:00.0: BAR 2: assigned [mem 0x12100000-0x12103fff 64bit pref]
10850 11:18:11.851871 <6>[ 17.807163] pci 0000:01:00.0: BAR 4: assigned [mem 0x12104000-0x12104fff 64bit pref]
10851 11:18:11.858690 <6>[ 17.807181] pci 0000:00:00.0: PCI bridge to [bus 01]
10852 11:18:11.865286 <3>[ 17.837874] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10853 11:18:11.875106 <6>[ 17.839987] pci 0000:00:00.0: bridge window [mem 0x12000000-0x121fffff 64bit pref]
10854 11:18:11.881607 <6>[ 17.841179] usbcore: registered new interface driver cdc_ether
10855 11:18:11.885082 <6>[ 17.860645] usbcore: registered new interface driver r8153_ecm
10856 11:18:11.891542 <6>[ 17.883073] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
10857 11:18:11.898045 <6>[ 17.885815] Bluetooth: Core ver 2.22
10858 11:18:11.901397 <6>[ 17.886210] NET: Registered PF_BLUETOOTH protocol family
10859 11:18:11.908015 <6>[ 17.886213] Bluetooth: HCI device and connection manager initialized
10860 11:18:11.915116 <6>[ 17.886229] Bluetooth: HCI socket layer initialized
10861 11:18:11.918407 <6>[ 17.886235] Bluetooth: L2CAP socket layer initialized
10862 11:18:11.925025 <6>[ 17.886249] Bluetooth: SCO socket layer initialized
10863 11:18:11.931421 <6>[ 17.906594] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10864 11:18:11.937843 <6>[ 17.916754] pcieport 0000:00:00.0: PME: Signaling with IRQ 282
10865 11:18:11.945168 <6>[ 17.916880] mtk-vcodec-enc 17020000.vcodec: Adding to iommu group 0
10866 11:18:11.947906 <6>[ 17.923796] r8152 2-1.3:1.0 eth0: v1.12.13
10867 11:18:11.960861 <6>[ 17.925276] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input4
10868 11:18:11.967594 <6>[ 17.925430] usbcore: registered new interface driver uvcvideo
10869 11:18:11.974618 <6>[ 17.932029] pcieport 0000:00:00.0: AER: enabled with IRQ 282
10870 11:18:11.977563 <6>[ 17.946456] usbcore: registered new interface driver btusb
10871 11:18:11.987658 <4>[ 17.946936] bluetooth hci0: Direct firmware load for mediatek/BT_RAM_CODE_MT7961_1_2_hdr.bin failed with error -2
10872 11:18:11.994082 <3>[ 17.946946] Bluetooth: hci0: Failed to load firmware file (-2)
10873 11:18:12.000572 <3>[ 17.946955] Bluetooth: hci0: Failed to set up firmware (-2)
10874 11:18:12.010726 <4>[ 17.946959] Bluetooth: hci0: HCI Enhanced Setup Synchronous Connection command is advertised, but not supported.
10875 11:18:12.017106 <6>[ 17.948397] r8152 2-1.3:1.0 enx002432307c7b: renamed from eth0
10876 11:18:12.023682 Starting [0;1;39mNetwork Name Resolution[0m...
10877 11:18:12.037791 <5>[ 18.107028] cfg80211: Loading compiled-in X.509 certificates for regulatory database
10878 11:18:12.043929 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
10879 11:18:12.057445 <3>[ 18.127205] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10880 11:18:12.065065 <5>[ 18.127353] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
10881 11:18:12.074705 <3>[ 18.128096] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -6
10882 11:18:12.080677 <3>[ 18.136144] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10883 11:18:12.090862 <3>[ 18.160912] power_supply sbs-5-000b: driver failed to report `temp' property: -6
10884 11:18:12.097481 <4>[ 18.162375] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
10885 11:18:12.104450 [[0;32m OK [<6>[ 18.177605] cfg80211: failed to load regulatory.db
10886 11:18:12.118137 0m] Started [0;1;39mNetwork Name Resolution[0m<3>[ 18.187055] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10887 11:18:12.118286 .
10888 11:18:12.140563 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
10889 11:18:12.146882 <3>[ 18.218685] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10890 11:18:12.157184 <6>[ 18.225041] mt7921e 0000:01:00.0: assigned reserved memory node wifi@c0000000
10891 11:18:12.163995 <6>[ 18.235014] mt7921e 0000:01:00.0: enabling device (0000 -> 0002)
10892 11:18:12.167174 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
10893 11:18:12.176993 <3>[ 18.247978] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10894 11:18:12.187553 <6>[ 18.261753] mt7921e 0000:01:00.0: ASIC revision: 79610010
10895 11:18:12.207814 <3>[ 18.278465] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10896 11:18:12.240412 <3>[ 18.310735] power_supply sbs-5-000b: driver failed to report `time_to_empty_now' property: -5
10897 11:18:12.293375 <4>[ 18.360465] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10898 11:18:12.345410 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
10899 11:18:12.362290 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
10900 11:18:12.381506 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
10901 11:18:12.397883 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
10902 11:18:12.415153 <4>[ 18.482637] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10903 11:18:12.425204 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
10904 11:18:12.432272 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
10905 11:18:12.438042 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
10906 11:18:12.457873 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
10907 11:18:12.470373 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
10908 11:18:12.489951 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
10909 11:18:12.502074 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
10910 11:18:12.518526 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
10911 11:18:12.535067 <4>[ 18.602246] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10912 11:18:12.545072 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
10913 11:18:12.582664 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
10914 11:18:12.608924 Starting [0;1;39mUser Login Management[0m...
10915 11:18:12.624591 Starting [0;1;39mPermit User Sessions[0m...
10916 11:18:12.660627 Starting [0;1;39mLoad/<4>[ 18.726256] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10917 11:18:12.664359 Save RF Kill Switch Status[0m...
10918 11:18:12.673875 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
10919 11:18:12.688601 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
10920 11:18:12.731413 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
10921 11:18:12.780117 [[0;32m OK [0m] Started [0;1;39mSerial Gett<4>[ 18.847195] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10922 11:18:12.783558 y on ttyS0[0m.
10923 11:18:12.789582 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
10924 11:18:12.804323 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
10925 11:18:12.823453 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
10926 11:18:12.838984 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
10927 11:18:12.904767 Starting [0;1;39mUpdate UTMP about Sys<4>[ 18.971788] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10928 11:18:12.907977 tem Runlevel Changes[0m...
10929 11:18:12.939208 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
10930 11:18:12.962160
10931 11:18:12.962687
10932 11:18:12.964133 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
10933 11:18:12.964524
10934 11:18:12.968004 debian-bullseye-arm64 login: root (automatic login)
10935 11:18:12.968524
10936 11:18:12.968844
10937 11:18:12.984568 Linux debian-bullseye-arm64 6.1.31 #1 SMP PREEMPT Mon Jun 5 10:57:14 UTC 2023 aarch64
10938 11:18:12.985100
10939 11:18:12.991326 The programs included with the Debian GNU/Linux system are free software;
10940 11:18:12.997627 the exact distribution terms for each program are described in the
10941 11:18:13.001019 individual files in /usr/share/doc/*/copyright.
10942 11:18:13.001561
10943 11:18:13.007463 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
10944 11:18:13.011110 permitted by applicable law.
10945 11:18:13.012286 Matched prompt #10: / #
10947 11:18:13.013218 Setting prompt string to ['/ #']
10948 11:18:13.013631 end: 2.2.5.1 login-action (duration 00:00:20) [common]
10950 11:18:13.014529 end: 2.2.5 auto-login-action (duration 00:00:20) [common]
10951 11:18:13.014935 start: 2.2.6 expect-shell-connection (timeout 00:02:46) [common]
10952 11:18:13.015260 Setting prompt string to ['/ #']
10953 11:18:13.015544 Forcing a shell prompt, looking for ['/ #']
10955 11:18:13.066426 / # <4>[
10956 11:18:13.067036 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10957 11:18:13.067457 Waiting using forced prompt support (timeout 00:02:30)
10958 11:18:13.067907 19.090656] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10959 11:18:13.072434
10960 11:18:13.073282 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10961 11:18:13.073729 start: 2.2.7 export-device-env (timeout 00:02:46) [common]
10962 11:18:13.074153 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10963 11:18:13.074560 end: 2.2 depthcharge-retry (duration 00:02:14) [common]
10964 11:18:13.074947 end: 2 depthcharge-action (duration 00:02:14) [common]
10965 11:18:13.075342 start: 3 lava-test-retry (timeout 00:07:28) [common]
10966 11:18:13.075721 start: 3.1 lava-test-shell (timeout 00:07:28) [common]
10967 11:18:13.076091 Using namespace: common
10969 11:18:13.177216 / # #
10970 11:18:13.177853 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:10:00)
10971 11:18:13.178429 #<4>[ 19.210489] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10972 11:18:13.183242
10973 11:18:13.183941 Using /lava-10591263
10975 11:18:13.285134 / # export SHELL=/bin/sh
10976 11:18:13.285373 export SHELL=/bin/sh<4>[ 19.330445] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10977 11:18:13.290527
10979 11:18:13.391280 / # . /lava-10591263/environment
10980 11:18:13.391657 . /lava-10591263/environment<4>[ 19.450496] mt7921e 0000:01:00.0: Direct firmware load for mediatek/WIFI_MT7961_patch_mcu_1_2_hdr.bin failed with error -2
10981 11:18:13.391826 <6>[ 19.462544] IPv6: ADDRCONF(NETDEV_CHANGE): enx002432307c7b: link becomes ready
10982 11:18:13.440423 <6>[ 19.471322] r8152 2-1.3:1.0 enx002432307c7b: carrier on
10983 11:18:13.440885
10985 11:18:13.542186 / # /lava-10591263/bin/lava-test-runner /lava-10591263/0
10986 11:18:13.542728 Test shell timeout: 10s (minimum of the action and connection timeout)
10987 11:18:13.544067 <3>[ 19.568209] mt7921e 0000:01:00.0: hardware init failed
10988 11:18:13.548263 /lava-10591263/bin/lava-test-runner /lava-10591263/0
10989 11:18:13.592446 + export TESTRUN_ID=0_v4l2-compliance-uvc
10990 11:18:13.592945 + cd /lava-10591263/0/tests/0_v4l2-compliance-uvc
10991 11:18:13.593248 + cat uuid
10992 11:18:13.593525 + UUID=10591263_1.5.2.3.1
10993 11:18:13.593794 + set +x
10994 11:18:13.594055 <LAVA_SIGNAL_STARTRUN 0_v4l2-compliance-uvc 10591263_1.5.2.3.1>
10995 11:18:13.594314 + /usr/bin/v4l2-parser.sh -d uvcvideo
10996 11:18:13.594817 Received signal: <STARTRUN> 0_v4l2-compliance-uvc 10591263_1.5.2.3.1
10997 11:18:13.595105 Starting test lava.0_v4l2-compliance-uvc (10591263_1.5.2.3.1)
10998 11:18:13.595437 Skipping test definition patterns.
10999 11:18:13.595875 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=device-presence RESULT=pass>
11000 11:18:13.596205 device: /dev/video1
11001 11:18:13.596705 Received signal: <TESTCASE> TEST_CASE_ID=device-presence RESULT=pass
11003 11:18:17.653523 <4>[ 23.727823] ------------[ cut here ]------------
11004 11:18:17.659792 <4>[ 23.732715] get_vaddr_frames() cannot follow VM_IO mapping
11005 11:18:17.673343 <4>[ 23.732867] WARNING: CPU: 6 PID: 308 at drivers/media/common/videobuf2/frame_vector.c:59 get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11006 11:18:17.719238 <4>[ 23.750970] Modules linked in: mt7921e mt7921_common mt76_connac_lib mt76 mac80211 libarc4 cfg80211 btusb btintel btmtk mtk_vcodec_enc mtk_vcodec_common btrtl btbcm mtk_vpu uvcvideo v4l2_mem2mem videobuf2_vmalloc r8153_ecm videobuf2_dma_contig cdc_ether videobuf2_memops bluetooth videobuf2_v4l2 usbnet cros_ec_rpmsg r8152 crct10dif_ce videobuf2_common videodev ecdh_generic elan_i2c ecc mc rfkill sbs_battery elants_i2c cros_ec_typec cros_ec_chardev mtk_scp hid_google_hammer mtk_rpmsg hid_vivaldi_common pcie_mediatek_gen3 mtk_scp_ipi ip_tables x_tables ipv6
11007 11:18:17.729387 <4>[ 23.800375] CPU: 6 PID: 308 Comm: v4l2-compliance Not tainted 6.1.31 #1
11008 11:18:17.732668 <4>[ 23.807241] Hardware name: Google Spherion (rev0 - 3) (DT)
11009 11:18:17.739183 <4>[ 23.812976] pstate: 60400009 (nZCv daif +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
11010 11:18:17.746088 <4>[ 23.820189] pc : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11011 11:18:17.752690 <4>[ 23.826287] lr : get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11012 11:18:17.755555 <4>[ 23.832384] sp : ffff8000091ab810
11013 11:18:17.762974 <4>[ 23.835948] x29: ffff8000091ab810 x28: ffffd5dfe03e9000 x27: ffffd5dfe03e5238
11014 11:18:17.772353 <4>[ 23.843336] x26: 0000000000000000 x25: ffffd5dfe03e94c0 x24: ffff197ac017c538
11015 11:18:17.779580 <4>[ 23.850724] x23: 00000000001c2000 x22: 0000000000000000 x21: 0000000000000000
11016 11:18:17.785352 <4>[ 23.858112] x20: 00000000fffffff2 x19: ffff197acf46a000 x18: fffffffffffe9528
11017 11:18:17.792158 <4>[ 23.865500] x17: 0000000000000000 x16: ffffd5dfefa8bb60 x15: 0000000000000038
11018 11:18:17.802356 <4>[ 23.872886] x14: ffffd5dff21c34a8 x13: 0000000000000636 x12: 0000000000000212
11019 11:18:17.808545 <4>[ 23.880274] x11: fffffffffffe9528 x10: fffffffffffe94f0 x9 : 00000000fffff212
11020 11:18:17.815915 <4>[ 23.887662] x8 : ffffd5dff21c34a8 x7 : ffffd5dff221b4a8 x6 : 00000000000018d8
11021 11:18:17.822154 <4>[ 23.895049] x5 : ffff197bfef90a18 x4 : 00000000fffff212 x3 : ffff439c0d48e000
11022 11:18:17.832417 <4>[ 23.902436] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff197acca45880
11023 11:18:17.832911 <4>[ 23.909824] Call trace:
11024 11:18:17.838713 <4>[ 23.912521] get_vaddr_frames+0xa8/0xb0 [videobuf2_common]
11025 11:18:17.845142 <4>[ 23.918271] vb2_create_framevec+0x50/0xac [videobuf2_memops]
11026 11:18:17.851556 <4>[ 23.924277] vb2_vmalloc_get_userptr+0x60/0x1a0 [videobuf2_vmalloc]
11027 11:18:17.858200 <4>[ 23.930805] __prepare_userptr+0x280/0x410 [videobuf2_common]
11028 11:18:17.861415 <4>[ 23.936815] __buf_prepare+0x1a0/0x244 [videobuf2_common]
11029 11:18:17.868617 <4>[ 23.942478] vb2_core_qbuf+0x3c8/0x5e0 [videobuf2_common]
11030 11:18:17.875007 <4>[ 23.948140] vb2_qbuf+0x90/0xf0 [videobuf2_v4l2]
11031 11:18:17.878298 <4>[ 23.953030] uvc_queue_buffer+0x3c/0x60 [uvcvideo]
11032 11:18:17.884718 <4>[ 23.958098] uvc_ioctl_qbuf+0x2c/0x40 [uvcvideo]
11033 11:18:17.888134 <4>[ 23.962980] v4l_qbuf+0x48/0x60 [videodev]
11034 11:18:17.894947 <4>[ 23.967402] __video_do_ioctl+0x184/0x3d0 [videodev]
11035 11:18:17.898419 <4>[ 23.972653] video_usercopy+0x358/0x680 [videodev]
11036 11:18:17.904578 <4>[ 23.977730] video_ioctl2+0x18/0x30 [videodev]
11037 11:18:17.908236 <4>[ 23.982460] v4l2_ioctl+0x40/0x60 [videodev]
11038 11:18:17.911359 <4>[ 23.987016] __arm64_sys_ioctl+0xa8/0xf0
11039 11:18:17.915335 <4>[ 23.991197] invoke_syscall+0x48/0x114
11040 11:18:17.921047 <4>[ 23.995204] el0_svc_common.constprop.0+0x44/0xec
11041 11:18:17.924731 <4>[ 24.000163] do_el0_svc+0x2c/0xd0
11042 11:18:17.928521 <4>[ 24.003732] el0_svc+0x2c/0x84
11043 11:18:17.931220 <4>[ 24.007045] el0t_64_sync_handler+0xb8/0xc0
11044 11:18:17.934724 <4>[ 24.011483] el0t_64_sync+0x18c/0x190
11045 11:18:17.941418 <4>[ 24.015398] ---[ end trace 0000000000000000 ]---
11046 11:18:20.359912 v4l2-compliance 1.25.0-1, 64 bits, 64-bit time_t
11047 11:18:20.369331 v4l2-compliance SHA: 52926c1f2f03 2023-05-25 13:56:39
11048 11:18:20.374584
11049 11:18:20.387276 Compliance test for uvcvideo device /dev/video1:
11050 11:18:20.392456
11051 11:18:20.402818 Driver Info:
11052 11:18:20.412197 Driver name : uvcvideo
11053 11:18:20.425345 Card type : HD User Facing: HD User Facing
11054 11:18:20.435007 Bus info : usb-11200000.usb-1.4.1
11055 11:18:20.440640 Driver version : 6.1.31
11056 11:18:20.450797 Capabilities : 0x84a00001
11057 11:18:20.462975 Metadata Capture
11058 11:18:20.473231 Streaming
11059 11:18:20.482017 Extended Pix Format
11060 11:18:20.491842 Device Capabilities
11061 11:18:20.501285 Device Caps : 0x04200001
11062 11:18:20.512577 Streaming
11063 11:18:20.522537 Extended Pix Format
11064 11:18:20.531853 Media Driver Info:
11065 11:18:20.541326 Driver name : uvcvideo
11066 11:18:20.554335 Model : HD User Facing: HD User Facing
11067 11:18:20.561040 Serial : 200901010001
11068 11:18:20.573612 Bus info : usb-11200000.usb-1.4.1
11069 11:18:20.580124 Media version : 6.1.31
11070 11:18:20.592349 Hardware revision: 0x00009758 (38744)
11071 11:18:20.598380 Driver version : 6.1.31
11072 11:18:20.607688 Interface Info:
11073 11:18:20.621843 <LAVA_SIGNAL_TESTSET START Interface-Info>
11074 11:18:20.621930 ID : 0x03000002
11075 11:18:20.622179 Received signal: <TESTSET> START Interface-Info
11076 11:18:20.622255 Starting test_set Interface-Info
11077 11:18:20.633346 Type : V4L Video
11078 11:18:20.644319 Entity Info:
11079 11:18:20.651044 <LAVA_SIGNAL_TESTSET STOP>
11080 11:18:20.651312 Received signal: <TESTSET> STOP
11081 11:18:20.651388 Closing test_set Interface-Info
11082 11:18:20.661188 <LAVA_SIGNAL_TESTSET START Entity-Info>
11083 11:18:20.661449 Received signal: <TESTSET> START Entity-Info
11084 11:18:20.661520 Starting test_set Entity-Info
11085 11:18:20.664343 ID : 0x00000001 (1)
11086 11:18:20.673068 Name : HD User Facing: HD User Facing
11087 11:18:20.679455 Function : V4L2 I/O
11088 11:18:20.688363 Flags : default
11089 11:18:20.698179 Pad 0x01000007 : 0: Sink
11090 11:18:20.717681 Link 0x02000013: from remote pad 0x100000a of entity 'Realtek Extended Controls Unit' (Video Pixel Formatter): Data, Enabled, Immutable
11091 11:18:20.717815
11092 11:18:20.726821 Required ioctls:
11093 11:18:20.733681 <LAVA_SIGNAL_TESTSET STOP>
11094 11:18:20.733936 Received signal: <TESTSET> STOP
11095 11:18:20.734009 Closing test_set Entity-Info
11096 11:18:20.743838 <LAVA_SIGNAL_TESTSET START Required-ioctls>
11097 11:18:20.744081 Received signal: <TESTSET> START Required-ioctls
11098 11:18:20.744150 Starting test_set Required-ioctls
11099 11:18:20.747187 test MC information (see 'Media Driver Info' above): OK
11100 11:18:20.769653 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass>
11101 11:18:20.769904 Received signal: <TESTCASE> TEST_CASE_ID=MC-information-see-Media-Driver-Info-above RESULT=pass
11103 11:18:20.773190 test VIDIOC_QUERYCAP: OK
11104 11:18:20.788627 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11105 11:18:20.788882 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11107 11:18:20.791954 test invalid ioctls: OK
11108 11:18:20.811927 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=invalid-ioctls RESULT=pass>
11109 11:18:20.812076
11110 11:18:20.812326 Received signal: <TESTCASE> TEST_CASE_ID=invalid-ioctls RESULT=pass
11112 11:18:20.823168 Allow for multiple opens:
11113 11:18:20.830013 <LAVA_SIGNAL_TESTSET STOP>
11114 11:18:20.830291 Received signal: <TESTSET> STOP
11115 11:18:20.830360 Closing test_set Required-ioctls
11116 11:18:20.839822 <LAVA_SIGNAL_TESTSET START Allow-for-multiple-opens>
11117 11:18:20.840066 Received signal: <TESTSET> START Allow-for-multiple-opens
11118 11:18:20.840149 Starting test_set Allow-for-multiple-opens
11119 11:18:20.842933 test second /dev/video1 open: OK
11120 11:18:20.863450 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=second-/dev/video1-open RESULT=pass>
11121 11:18:20.863701 Received signal: <TESTCASE> TEST_CASE_ID=second-/dev/video1-open RESULT=pass
11123 11:18:20.866496 test VIDIOC_QUERYCAP: OK
11124 11:18:20.886706 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass>
11125 11:18:20.886961 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCAP RESULT=pass
11127 11:18:20.889997 test VIDIOC_G/S_PRIORITY: OK
11128 11:18:20.911923 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass>
11129 11:18:20.912175 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PRIORITY RESULT=pass
11131 11:18:20.914646 test for unlimited opens: OK
11132 11:18:20.934882 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=for-unlimited-opens RESULT=pass>
11133 11:18:20.934968
11134 11:18:20.935200 Received signal: <TESTCASE> TEST_CASE_ID=for-unlimited-opens RESULT=pass
11136 11:18:20.945198 Debug ioctls:
11137 11:18:20.951593 <LAVA_SIGNAL_TESTSET STOP>
11138 11:18:20.951843 Received signal: <TESTSET> STOP
11139 11:18:20.951910 Closing test_set Allow-for-multiple-opens
11140 11:18:20.961262 <LAVA_SIGNAL_TESTSET START Debug-ioctls>
11141 11:18:20.961514 Received signal: <TESTSET> START Debug-ioctls
11142 11:18:20.961586 Starting test_set Debug-ioctls
11143 11:18:20.965150 test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
11144 11:18:20.985841 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass>
11145 11:18:20.986125 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DBG_G/S_REGISTER RESULT=pass
11147 11:18:20.991720 test VIDIOC_LOG_STATUS: OK (Not Supported)
11148 11:18:21.008366 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass>
11149 11:18:21.008448
11150 11:18:21.008680 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_LOG_STATUS RESULT=pass
11152 11:18:21.017884 Input ioctls:
11153 11:18:21.025023 <LAVA_SIGNAL_TESTSET STOP>
11154 11:18:21.025272 Received signal: <TESTSET> STOP
11155 11:18:21.025339 Closing test_set Debug-ioctls
11156 11:18:21.033602 <LAVA_SIGNAL_TESTSET START Input-ioctls>
11157 11:18:21.033854 Received signal: <TESTSET> START Input-ioctls
11158 11:18:21.033924 Starting test_set Input-ioctls
11159 11:18:21.036841 test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
11160 11:18:21.059347 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass>
11161 11:18:21.059601 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS RESULT=pass
11163 11:18:21.062400 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11164 11:18:21.080557 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11165 11:18:21.080811 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11167 11:18:21.087050 test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
11168 11:18:21.104943 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass>
11169 11:18:21.105195 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_HW_FREQ_SEEK RESULT=pass
11171 11:18:21.110949 test VIDIOC_ENUMAUDIO: OK (Not Supported)
11172 11:18:21.128397 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass>
11173 11:18:21.128653 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDIO RESULT=pass
11175 11:18:21.131746 test VIDIOC_G/S/ENUMINPUT: OK
11176 11:18:21.152278 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass>
11177 11:18:21.152614 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMINPUT RESULT=pass
11179 11:18:21.155548 test VIDIOC_G/S_AUDIO: OK (Not Supported)
11180 11:18:21.176974 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass>
11181 11:18:21.177228 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDIO RESULT=pass
11183 11:18:21.179940 Inputs: 1 Audio Inputs: 0 Tuners: 0
11184 11:18:21.187439
11185 11:18:21.204389 test VIDIOC_G/S_MODULATOR: OK (Not Supported)
11186 11:18:21.223441 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass>
11187 11:18:21.223698 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_MODULATOR RESULT=pass
11189 11:18:21.230458 test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
11190 11:18:21.248038 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass>
11191 11:18:21.248325 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_FREQUENCY RESULT=pass
11193 11:18:21.254787 test VIDIOC_ENUMAUDOUT: OK (Not Supported)
11194 11:18:21.271860 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass>
11195 11:18:21.272117 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUMAUDOUT RESULT=pass
11197 11:18:21.278879 test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
11198 11:18:21.296171 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass>
11199 11:18:21.296427 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/ENUMOUTPUT RESULT=pass
11201 11:18:21.302570 test VIDIOC_G/S_AUDOUT: OK (Not Supported)
11202 11:18:21.318328 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass>
11203 11:18:21.318439
11204 11:18:21.318705 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_AUDOUT RESULT=pass
11206 11:18:21.338287 test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
11207 11:18:21.359293 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass>
11208 11:18:21.359550 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_STD RESULT=pass
11210 11:18:21.366545 test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
11211 11:18:21.387092 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass>
11212 11:18:21.387351 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS RESULT=pass
11214 11:18:21.390267 test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
11215 11:18:21.408058 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass>
11216 11:18:21.408329 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_DV_TIMINGS_CAP RESULT=pass
11218 11:18:21.414281 test VIDIOC_G/S_EDID: OK (Not Supported)
11219 11:18:21.431970 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass>
11220 11:18:21.432086
11221 11:18:21.432322 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_EDID RESULT=pass
11223 11:18:21.442890 Control ioctls (Input 0):
11224 11:18:21.449112 <LAVA_SIGNAL_TESTSET STOP>
11225 11:18:21.449364 Received signal: <TESTSET> STOP
11226 11:18:21.449436 Closing test_set Input-ioctls
11227 11:18:21.458788 <LAVA_SIGNAL_TESTSET START Control-ioctls-Input-0>
11228 11:18:21.459064 Received signal: <TESTSET> START Control-ioctls-Input-0
11229 11:18:21.459165 Starting test_set Control-ioctls-Input-0
11230 11:18:21.461748 test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
11231 11:18:21.486235 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass>
11232 11:18:21.486332 test VIDIOC_QUERYCTRL: OK
11233 11:18:21.486570 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERY_EXT_CTRL/QUERYMENU RESULT=pass
11235 11:18:21.508292 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass>
11236 11:18:21.508546 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_QUERYCTRL RESULT=pass
11238 11:18:21.511680 test VIDIOC_G/S_CTRL: OK
11239 11:18:21.532247 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass>
11240 11:18:21.532500 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_CTRL RESULT=pass
11242 11:18:21.535273 test VIDIOC_G/S/TRY_EXT_CTRLS: OK
11243 11:18:21.555446 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass>
11244 11:18:21.555699 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S/TRY_EXT_CTRLS RESULT=pass
11246 11:18:21.561923 test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
11247 11:18:21.581727 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass>
11248 11:18:21.581989 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT RESULT=pass
11250 11:18:21.584842 test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
11251 11:18:21.602496 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass>
11252 11:18:21.602749 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_JPEGCOMP RESULT=pass
11254 11:18:21.605772 Standard Controls: 16 Private Controls: 0
11255 11:18:21.612875
11256 11:18:21.623050 Format ioctls (Input 0):
11257 11:18:21.630144 <LAVA_SIGNAL_TESTSET STOP>
11258 11:18:21.630394 Received signal: <TESTSET> STOP
11259 11:18:21.630462 Closing test_set Control-ioctls-Input-0
11260 11:18:21.639502 <LAVA_SIGNAL_TESTSET START Format-ioctls-Input-0>
11261 11:18:21.639754 Received signal: <TESTSET> START Format-ioctls-Input-0
11262 11:18:21.639823 Starting test_set Format-ioctls-Input-0
11263 11:18:21.643206 test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
11264 11:18:21.667373 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass>
11265 11:18:21.667629 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS RESULT=pass
11267 11:18:21.670294 test VIDIOC_G/S_PARM: OK
11268 11:18:21.688227 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass>
11269 11:18:21.688489 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G/S_PARM RESULT=pass
11271 11:18:21.691240 test VIDIOC_G_FBUF: OK (Not Supported)
11272 11:18:21.713560 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass>
11273 11:18:21.713813 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FBUF RESULT=pass
11275 11:18:21.716152 test VIDIOC_G_FMT: OK
11276 11:18:21.736504 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass>
11277 11:18:21.736757 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_FMT RESULT=pass
11279 11:18:21.739864 test VIDIOC_TRY_FMT: OK
11280 11:18:21.759606 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass>
11281 11:18:21.759857 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_FMT RESULT=pass
11283 11:18:21.766227 warn: ../utils/v4l2-compliance/v4l2-test-formats.cpp(1046): Could not set fmt2
11284 11:18:21.769663 test VIDIOC_S_FMT: OK
11285 11:18:21.795028 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass>
11286 11:18:21.795312 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_S_FMT RESULT=pass
11288 11:18:21.798328 test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
11289 11:18:21.819413 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass>
11290 11:18:21.819662 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_SLICED_VBI_CAP RESULT=pass
11292 11:18:21.822483 test Cropping: OK (Not Supported)
11293 11:18:21.843380 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Cropping RESULT=pass>
11294 11:18:21.843630 Received signal: <TESTCASE> TEST_CASE_ID=Cropping RESULT=pass
11296 11:18:21.846774 test Composing: OK (Not Supported)
11297 11:18:21.867744 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Composing RESULT=pass>
11298 11:18:21.868013 Received signal: <TESTCASE> TEST_CASE_ID=Composing RESULT=pass
11300 11:18:21.870672 test Scaling: OK (Not Supported)
11301 11:18:21.890930 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Scaling RESULT=pass>
11302 11:18:21.891044
11303 11:18:21.891306 Received signal: <TESTCASE> TEST_CASE_ID=Scaling RESULT=pass
11305 11:18:21.901239 Codec ioctls (Input 0):
11306 11:18:21.908657 <LAVA_SIGNAL_TESTSET STOP>
11307 11:18:21.908928 Received signal: <TESTSET> STOP
11308 11:18:21.909021 Closing test_set Format-ioctls-Input-0
11309 11:18:21.917791 <LAVA_SIGNAL_TESTSET START Codec-ioctls-Input-0>
11310 11:18:21.918062 Received signal: <TESTSET> START Codec-ioctls-Input-0
11311 11:18:21.918131 Starting test_set Codec-ioctls-Input-0
11312 11:18:21.920939 test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
11313 11:18:21.941202 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass>
11314 11:18:21.941451 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_ENCODER_CMD RESULT=pass
11316 11:18:21.947444 test VIDIOC_G_ENC_INDEX: OK (Not Supported)
11317 11:18:21.966730 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass>
11318 11:18:21.967002 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_G_ENC_INDEX RESULT=pass
11320 11:18:21.972355 test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
11321 11:18:21.990804 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass>
11322 11:18:21.990913
11323 11:18:21.991176 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_TRY_DECODER_CMD RESULT=pass
11325 11:18:22.000589 Buffer ioctls (Input 0):
11326 11:18:22.006512 <LAVA_SIGNAL_TESTSET STOP>
11327 11:18:22.006755 Received signal: <TESTSET> STOP
11328 11:18:22.006821 Closing test_set Codec-ioctls-Input-0
11329 11:18:22.015831 <LAVA_SIGNAL_TESTSET START Buffer-ioctls-Input-0>
11330 11:18:22.016103 Received signal: <TESTSET> START Buffer-ioctls-Input-0
11331 11:18:22.016171 Starting test_set Buffer-ioctls-Input-0
11332 11:18:22.018992 test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
11333 11:18:22.042913 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass>
11334 11:18:22.042997 test VIDIOC_EXPBUF: OK
11335 11:18:22.043229 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF RESULT=pass
11337 11:18:22.063571 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass>
11338 11:18:22.063821 Received signal: <TESTCASE> TEST_CASE_ID=VIDIOC_EXPBUF RESULT=pass
11340 11:18:22.066597 test Requests: OK (Not Supported)
11341 11:18:22.087258 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=Requests RESULT=pass>
11342 11:18:22.087343
11343 11:18:22.087576 Received signal: <TESTCASE> TEST_CASE_ID=Requests RESULT=pass
11345 11:18:22.096781 Test input 0:
11346 11:18:22.107020
11347 11:18:22.130412 Streaming ioctls:
11348 11:18:22.136843 <LAVA_SIGNAL_TESTSET STOP>
11349 11:18:22.137097 Received signal: <TESTSET> STOP
11350 11:18:22.137171 Closing test_set Buffer-ioctls-Input-0
11351 11:18:22.145858 <LAVA_SIGNAL_TESTSET START Streaming-ioctls_Test-input-0>
11352 11:18:22.146110 Received signal: <TESTSET> START Streaming-ioctls_Test-input-0
11353 11:18:22.146185 Starting test_set Streaming-ioctls_Test-input-0
11354 11:18:22.149454 test read/write: OK (Not Supported)
11355 11:18:22.171451 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=read/write RESULT=pass>
11356 11:18:22.171704 Received signal: <TESTCASE> TEST_CASE_ID=read/write RESULT=pass
11358 11:18:22.175196 test blocking wait: OK
11359 11:18:22.195623 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=blocking-wait RESULT=pass>
11360 11:18:22.195886 Received signal: <TESTCASE> TEST_CASE_ID=blocking-wait RESULT=pass
11362 11:18:22.205636 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11363 11:18:22.208630 test MMAP (no poll): FAIL
11364 11:18:22.228336 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-no-poll RESULT=fail>
11365 11:18:22.228593 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-no-poll RESULT=fail
11367 11:18:22.238233 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11368 11:18:22.238318 test MMAP (select): FAIL
11369 11:18:22.263145 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-select RESULT=fail>
11370 11:18:22.263401 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-select RESULT=fail
11372 11:18:22.272310 fail: ../utils/v4l2-compliance/v4l2-test-buffers.cpp(1346): node->streamon(q.g_type()) != EINVAL
11373 11:18:22.275497 test MMAP (epoll): FAIL
11374 11:18:22.298731 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=MMAP-epoll RESULT=fail>
11375 11:18:22.298816
11376 11:18:22.299051 Received signal: <TESTCASE> TEST_CASE_ID=MMAP-epoll RESULT=fail
11378 11:18:22.310500
11379 11:18:22.515918
11380 11:18:22.523410 test USERPTR (no poll): OK
11381 11:18:22.546876 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-no-poll RESULT=pass>
11382 11:18:22.546965
11383 11:18:22.547204 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-no-poll RESULT=pass
11385 11:18:22.558382
11386 11:18:22.712465
11387 11:18:22.718680 test USERPTR (select): OK
11388 11:18:22.742594 <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=USERPTR-select RESULT=pass>
11389 11:18:22.742855 Received signal: <TESTCASE> TEST_CASE_ID=USERPTR-select RESULT=pass
11391 11:18:22.748868 test DMABUF: Cannot test, specify --expbuf-device
11392 11:18:22.753048
11393 11:18:22.769790 Total for uvcvideo device /dev/video1: 53, Succeeded: 50, Failed: 3, Warnings: 3
11394 11:18:22.772724 <LAVA_TEST_RUNNER EXIT>
11395 11:18:22.773005 ok: lava_test_shell seems to have completed
11396 11:18:22.773084 Marking unfinished test run as failed
11398 11:18:22.774026 Composing:
result: pass
set: Format-ioctls-Input-0
Cropping:
result: pass
set: Format-ioctls-Input-0
MC-information-see-Media-Driver-Info-above:
result: pass
set: Required-ioctls
MMAP-epoll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-no-poll:
result: fail
set: Streaming-ioctls_Test-input-0
MMAP-select:
result: fail
set: Streaming-ioctls_Test-input-0
Requests:
result: pass
set: Buffer-ioctls-Input-0
Scaling:
result: pass
set: Format-ioctls-Input-0
USERPTR-no-poll:
result: pass
set: Streaming-ioctls_Test-input-0
USERPTR-select:
result: pass
set: Streaming-ioctls_Test-input-0
VIDIOC_DBG_G/S_REGISTER:
result: pass
set: Debug-ioctls
VIDIOC_DV_TIMINGS_CAP:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS:
result: pass
set: Input-ioctls
VIDIOC_ENUM/G/S/QUERY_STD:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDIO:
result: pass
set: Input-ioctls
VIDIOC_ENUMAUDOUT:
result: pass
set: Input-ioctls
VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS:
result: pass
set: Format-ioctls-Input-0
VIDIOC_EXPBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_G/S/ENUMINPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/ENUMOUTPUT:
result: pass
set: Input-ioctls
VIDIOC_G/S/TRY_EXT_CTRLS:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_AUDIO:
result: pass
set: Input-ioctls
VIDIOC_G/S_AUDOUT:
result: pass
set: Input-ioctls
VIDIOC_G/S_CTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_EDID:
result: pass
set: Input-ioctls
VIDIOC_G/S_FREQUENCY:
result: pass
set: Input-ioctls
VIDIOC_G/S_JPEGCOMP:
result: pass
set: Control-ioctls-Input-0
VIDIOC_G/S_MODULATOR:
result: pass
set: Input-ioctls
VIDIOC_G/S_PARM:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G/S_PRIORITY:
result: pass
set: Allow-for-multiple-opens
VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS:
result: pass
set: Input-ioctls
VIDIOC_G_ENC_INDEX:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_G_FBUF:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_G_SLICED_VBI_CAP:
result: pass
set: Format-ioctls-Input-0
VIDIOC_LOG_STATUS:
result: pass
set: Debug-ioctls
VIDIOC_QUERYCAP:
result: pass
set: Allow-for-multiple-opens
VIDIOC_QUERYCTRL:
result: pass
set: Control-ioctls-Input-0
VIDIOC_QUERY_EXT_CTRL/QUERYMENU:
result: pass
set: Control-ioctls-Input-0
VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF:
result: pass
set: Buffer-ioctls-Input-0
VIDIOC_S_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_S_HW_FREQ_SEEK:
result: pass
set: Input-ioctls
VIDIOC_TRY_DECODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_ENCODER_CMD:
result: pass
set: Codec-ioctls-Input-0
VIDIOC_TRY_FMT:
result: pass
set: Format-ioctls-Input-0
VIDIOC_UNSUBSCRIBE_EVENT/DQEVENT:
result: pass
set: Control-ioctls-Input-0
blocking-wait:
result: pass
set: Streaming-ioctls_Test-input-0
device-presence: pass
for-unlimited-opens:
result: pass
set: Allow-for-multiple-opens
invalid-ioctls:
result: pass
set: Required-ioctls
read/write:
result: pass
set: Streaming-ioctls_Test-input-0
second-/dev/video1-open:
result: pass
set: Allow-for-multiple-opens
11399 11:18:22.774150 end: 3.1 lava-test-shell (duration 00:00:10) [common]
11400 11:18:22.774242 end: 3 lava-test-retry (duration 00:00:10) [common]
11401 11:18:22.774345 start: 4 finalize (timeout 00:07:18) [common]
11402 11:18:22.774434 start: 4.1 power-off (timeout 00:00:30) [common]
11403 11:18:22.774594 Calling: 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
11404 11:18:22.849747 >> Command sent successfully.
11405 11:18:22.851981 Returned 0 in 0 seconds
11406 11:18:22.952381 end: 4.1 power-off (duration 00:00:00) [common]
11408 11:18:22.952708 start: 4.2 read-feedback (timeout 00:07:18) [common]
11409 11:18:22.952969 Listened to connection for namespace 'common' for up to 1s
11410 11:18:23.953889 Finalising connection for namespace 'common'
11411 11:18:23.954065 Disconnecting from shell: Finalise
11412 11:18:23.954147 / #
11413 11:18:24.054432 end: 4.2 read-feedback (duration 00:00:01) [common]
11414 11:18:24.054591 end: 4 finalize (duration 00:00:01) [common]
11415 11:18:24.054715 Cleaning after the job
11416 11:18:24.054809 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591263/tftp-deploy-_xk_g__a/ramdisk
11417 11:18:24.059225 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591263/tftp-deploy-_xk_g__a/kernel
11418 11:18:24.070116 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591263/tftp-deploy-_xk_g__a/dtb
11419 11:18:24.070314 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/10591263/tftp-deploy-_xk_g__a/modules
11420 11:18:24.075700 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/10591263
11421 11:18:24.130717 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/10591263
11422 11:18:24.130899 Job finished correctly